diff --git a/esp32/src/aes/endian.rs b/esp32/src/aes/endian.rs
index 9e9c5a1d50..c3a2f126dd 100644
--- a/esp32/src/aes/endian.rs
+++ b/esp32/src/aes/endian.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENDIAN")
-            .field("endian", &format_args!("{}", self.endian().bits()))
+            .field("endian", &self.endian())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENDIAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Endianness selection register. See Table 22-2 for details."]
     #[inline(always)]
diff --git a/esp32/src/aes/idle.rs b/esp32/src/aes/idle.rs
index 836ef53afe..c290d2e082 100644
--- a/esp32/src/aes/idle.rs
+++ b/esp32/src/aes/idle.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("IDLE")
-            .field("idle", &format_args!("{}", self.idle().bit()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("IDLE").field("idle", &self.idle()).finish()
     }
 }
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idle::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/aes/key.rs b/esp32/src/aes/key.rs
index c952c1e2a2..32b6f52fa2 100644
--- a/esp32/src/aes/key.rs
+++ b/esp32/src/aes/key.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("KEY")
-            .field("key", &format_args!("{}", self.key().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<KEY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("KEY").field("key", &self.key()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/aes/mode.rs b/esp32/src/aes/mode.rs
index 44172e368c..e1ea8e5f2d 100644
--- a/esp32/src/aes/mode.rs
+++ b/esp32/src/aes/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/aes/text.rs b/esp32/src/aes/text.rs
index 2432c68e60..b5f79baab8 100644
--- a/esp32/src/aes/text.rs
+++ b/esp32/src/aes/text.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("TEXT")
-            .field("text", &format_args!("{}", self.text().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEXT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("TEXT").field("text", &self.text()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/apb_ctrl/apb_saradc_ctrl.rs b/esp32/src/apb_ctrl/apb_saradc_ctrl.rs
index 4d6b8bb492..2a5beb594f 100644
--- a/esp32/src/apb_ctrl/apb_saradc_ctrl.rs
+++ b/esp32/src/apb_ctrl/apb_saradc_ctrl.rs
@@ -125,67 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_SARADC_CTRL")
-            .field(
-                "saradc_start_force",
-                &format_args!("{}", self.saradc_start_force().bit()),
-            )
-            .field(
-                "saradc_start",
-                &format_args!("{}", self.saradc_start().bit()),
-            )
-            .field(
-                "saradc_sar2_mux",
-                &format_args!("{}", self.saradc_sar2_mux().bit()),
-            )
-            .field(
-                "saradc_work_mode",
-                &format_args!("{}", self.saradc_work_mode().bits()),
-            )
-            .field(
-                "saradc_sar_sel",
-                &format_args!("{}", self.saradc_sar_sel().bit()),
-            )
-            .field(
-                "saradc_sar_clk_gated",
-                &format_args!("{}", self.saradc_sar_clk_gated().bit()),
-            )
-            .field(
-                "saradc_sar_clk_div",
-                &format_args!("{}", self.saradc_sar_clk_div().bits()),
-            )
-            .field(
-                "saradc_sar1_patt_len",
-                &format_args!("{}", self.saradc_sar1_patt_len().bits()),
-            )
-            .field(
-                "saradc_sar2_patt_len",
-                &format_args!("{}", self.saradc_sar2_patt_len().bits()),
-            )
-            .field(
-                "saradc_sar1_patt_p_clear",
-                &format_args!("{}", self.saradc_sar1_patt_p_clear().bit()),
-            )
-            .field(
-                "saradc_sar2_patt_p_clear",
-                &format_args!("{}", self.saradc_sar2_patt_p_clear().bit()),
-            )
-            .field(
-                "saradc_data_sar_sel",
-                &format_args!("{}", self.saradc_data_sar_sel().bit()),
-            )
-            .field(
-                "saradc_data_to_i2s",
-                &format_args!("{}", self.saradc_data_to_i2s().bit()),
-            )
+            .field("saradc_start_force", &self.saradc_start_force())
+            .field("saradc_start", &self.saradc_start())
+            .field("saradc_sar2_mux", &self.saradc_sar2_mux())
+            .field("saradc_work_mode", &self.saradc_work_mode())
+            .field("saradc_sar_sel", &self.saradc_sar_sel())
+            .field("saradc_sar_clk_gated", &self.saradc_sar_clk_gated())
+            .field("saradc_sar_clk_div", &self.saradc_sar_clk_div())
+            .field("saradc_sar1_patt_len", &self.saradc_sar1_patt_len())
+            .field("saradc_sar2_patt_len", &self.saradc_sar2_patt_len())
+            .field("saradc_sar1_patt_p_clear", &self.saradc_sar1_patt_p_clear())
+            .field("saradc_sar2_patt_p_clear", &self.saradc_sar2_patt_p_clear())
+            .field("saradc_data_sar_sel", &self.saradc_data_sar_sel())
+            .field("saradc_data_to_i2s", &self.saradc_data_to_i2s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_SARADC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/apb_ctrl/apb_saradc_ctrl2.rs b/esp32/src/apb_ctrl/apb_saradc_ctrl2.rs
index 89ca97fce4..fd433dfa16 100644
--- a/esp32/src/apb_ctrl/apb_saradc_ctrl2.rs
+++ b/esp32/src/apb_ctrl/apb_saradc_ctrl2.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_SARADC_CTRL2")
-            .field(
-                "saradc_meas_num_limit",
-                &format_args!("{}", self.saradc_meas_num_limit().bit()),
-            )
-            .field(
-                "saradc_max_meas_num",
-                &format_args!("{}", self.saradc_max_meas_num().bits()),
-            )
-            .field(
-                "saradc_sar1_inv",
-                &format_args!("{}", self.saradc_sar1_inv().bit()),
-            )
-            .field(
-                "saradc_sar2_inv",
-                &format_args!("{}", self.saradc_sar2_inv().bit()),
-            )
+            .field("saradc_meas_num_limit", &self.saradc_meas_num_limit())
+            .field("saradc_max_meas_num", &self.saradc_max_meas_num())
+            .field("saradc_sar1_inv", &self.saradc_sar1_inv())
+            .field("saradc_sar2_inv", &self.saradc_sar2_inv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_SARADC_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/apb_ctrl/apb_saradc_fsm.rs b/esp32/src/apb_ctrl/apb_saradc_fsm.rs
index a421496de5..cd8caa65e9 100644
--- a/esp32/src/apb_ctrl/apb_saradc_fsm.rs
+++ b/esp32/src/apb_ctrl/apb_saradc_fsm.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_SARADC_FSM")
-            .field(
-                "saradc_rstb_wait",
-                &format_args!("{}", self.saradc_rstb_wait().bits()),
-            )
-            .field(
-                "saradc_standby_wait",
-                &format_args!("{}", self.saradc_standby_wait().bits()),
-            )
-            .field(
-                "saradc_start_wait",
-                &format_args!("{}", self.saradc_start_wait().bits()),
-            )
-            .field(
-                "saradc_sample_cycle",
-                &format_args!("{}", self.saradc_sample_cycle().bits()),
-            )
+            .field("saradc_rstb_wait", &self.saradc_rstb_wait())
+            .field("saradc_standby_wait", &self.saradc_standby_wait())
+            .field("saradc_start_wait", &self.saradc_start_wait())
+            .field("saradc_sample_cycle", &self.saradc_sample_cycle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_SARADC_FSM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/apb_ctrl/apb_saradc_sar1_patt_tab.rs b/esp32/src/apb_ctrl/apb_saradc_sar1_patt_tab.rs
index d8a8282d0b..fc10d43e69 100644
--- a/esp32/src/apb_ctrl/apb_saradc_sar1_patt_tab.rs
+++ b/esp32/src/apb_ctrl/apb_saradc_sar1_patt_tab.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_SARADC_SAR1_PATT_TAB")
-            .field(
-                "saradc_sar1_patt_tab1",
-                &format_args!("{}", self.saradc_sar1_patt_tab1().bits()),
-            )
+            .field("saradc_sar1_patt_tab1", &self.saradc_sar1_patt_tab1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_SARADC_SAR1_PATT_TAB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - item 0 ~ 3 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32/src/apb_ctrl/apb_saradc_sar2_patt_tab.rs b/esp32/src/apb_ctrl/apb_saradc_sar2_patt_tab.rs
index ad6300a3a4..23fce0e917 100644
--- a/esp32/src/apb_ctrl/apb_saradc_sar2_patt_tab.rs
+++ b/esp32/src/apb_ctrl/apb_saradc_sar2_patt_tab.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_SARADC_SAR2_PATT_TAB")
-            .field(
-                "saradc_sar2_patt_tab1",
-                &format_args!("{}", self.saradc_sar2_patt_tab1().bits()),
-            )
+            .field("saradc_sar2_patt_tab1", &self.saradc_sar2_patt_tab1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_SARADC_SAR2_PATT_TAB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - item 0 ~ 3 for pattern table 2 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32/src/apb_ctrl/apll_tick_conf.rs b/esp32/src/apb_ctrl/apll_tick_conf.rs
index b0dccc8c64..029a00b1e1 100644
--- a/esp32/src/apb_ctrl/apll_tick_conf.rs
+++ b/esp32/src/apb_ctrl/apll_tick_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APLL_TICK_CONF")
-            .field(
-                "apll_tick_num",
-                &format_args!("{}", self.apll_tick_num().bits()),
-            )
+            .field("apll_tick_num", &self.apll_tick_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APLL_TICK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/apb_ctrl/ck8m_tick_conf.rs b/esp32/src/apb_ctrl/ck8m_tick_conf.rs
index bc3006d4d8..13616cf2a3 100644
--- a/esp32/src/apb_ctrl/ck8m_tick_conf.rs
+++ b/esp32/src/apb_ctrl/ck8m_tick_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CK8M_TICK_CONF")
-            .field(
-                "ck8m_tick_num",
-                &format_args!("{}", self.ck8m_tick_num().bits()),
-            )
+            .field("ck8m_tick_num", &self.ck8m_tick_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CK8M_TICK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/apb_ctrl/date.rs b/esp32/src/apb_ctrl/date.rs
index 26bd148995..09c9d271d1 100644
--- a/esp32/src/apb_ctrl/date.rs
+++ b/esp32/src/apb_ctrl/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/apb_ctrl/pll_tick_conf.rs b/esp32/src/apb_ctrl/pll_tick_conf.rs
index c82a92ebee..42f1648a57 100644
--- a/esp32/src/apb_ctrl/pll_tick_conf.rs
+++ b/esp32/src/apb_ctrl/pll_tick_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PLL_TICK_CONF")
-            .field(
-                "pll_tick_num",
-                &format_args!("{}", self.pll_tick_num().bits()),
-            )
+            .field("pll_tick_num", &self.pll_tick_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PLL_TICK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/apb_ctrl/sysclk_conf.rs b/esp32/src/apb_ctrl/sysclk_conf.rs
index 7e0539a399..6f5f95a9c2 100644
--- a/esp32/src/apb_ctrl/sysclk_conf.rs
+++ b/esp32/src/apb_ctrl/sysclk_conf.rs
@@ -53,29 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSCLK_CONF")
-            .field(
-                "pre_div_cnt",
-                &format_args!("{}", self.pre_div_cnt().bits()),
-            )
-            .field("clk_320m_en", &format_args!("{}", self.clk_320m_en().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "rst_tick_cnt",
-                &format_args!("{}", self.rst_tick_cnt().bit()),
-            )
-            .field(
-                "quick_clk_chng",
-                &format_args!("{}", self.quick_clk_chng().bit()),
-            )
+            .field("pre_div_cnt", &self.pre_div_cnt())
+            .field("clk_320m_en", &self.clk_320m_en())
+            .field("clk_en", &self.clk_en())
+            .field("rst_tick_cnt", &self.rst_tick_cnt())
+            .field("quick_clk_chng", &self.quick_clk_chng())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
diff --git a/esp32/src/apb_ctrl/xtal_tick_conf.rs b/esp32/src/apb_ctrl/xtal_tick_conf.rs
index f5e6d164dd..76e5bd9a5a 100644
--- a/esp32/src/apb_ctrl/xtal_tick_conf.rs
+++ b/esp32/src/apb_ctrl/xtal_tick_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL_TICK_CONF")
-            .field(
-                "xtal_tick_num",
-                &format_args!("{}", self.xtal_tick_num().bits()),
-            )
+            .field("xtal_tick_num", &self.xtal_tick_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL_TICK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/bb/bbpd_ctrl.rs b/esp32/src/bb/bbpd_ctrl.rs
index 7e31e667bb..28cf2656e4 100644
--- a/esp32/src/bb/bbpd_ctrl.rs
+++ b/esp32/src/bb/bbpd_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BBPD_CTRL")
-            .field(
-                "dc_est_force_pd",
-                &format_args!("{}", self.dc_est_force_pd().bit()),
-            )
-            .field(
-                "dc_est_force_pu",
-                &format_args!("{}", self.dc_est_force_pu().bit()),
-            )
-            .field(
-                "fft_force_pd",
-                &format_args!("{}", self.fft_force_pd().bit()),
-            )
-            .field(
-                "fft_force_pu",
-                &format_args!("{}", self.fft_force_pu().bit()),
-            )
+            .field("dc_est_force_pd", &self.dc_est_force_pd())
+            .field("dc_est_force_pu", &self.dc_est_force_pu())
+            .field("fft_force_pd", &self.fft_force_pd())
+            .field("fft_force_pu", &self.fft_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BBPD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/access_check.rs b/esp32/src/dport/access_check.rs
index c9c80b89cc..ef4857712a 100644
--- a/esp32/src/dport/access_check.rs
+++ b/esp32/src/dport/access_check.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ACCESS_CHECK")
-            .field("pro", &format_args!("{}", self.pro().bit()))
-            .field("app", &format_args!("{}", self.app().bit()))
+            .field("pro", &self.pro())
+            .field("app", &self.app())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ACCESS_CHECK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`access_check::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ACCESS_CHECK_SPEC;
 impl crate::RegisterSpec for ACCESS_CHECK_SPEC {
diff --git a/esp32/src/dport/ahb_lite_mask.rs b/esp32/src/dport/ahb_lite_mask.rs
index 4d35713717..9dbfbfbe8c 100644
--- a/esp32/src/dport/ahb_lite_mask.rs
+++ b/esp32/src/dport/ahb_lite_mask.rs
@@ -62,24 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_LITE_MASK")
-            .field("pro", &format_args!("{}", self.pro().bit()))
-            .field("app", &format_args!("{}", self.app().bit()))
-            .field("sdio", &format_args!("{}", self.sdio().bit()))
-            .field("prodport", &format_args!("{}", self.prodport().bit()))
-            .field("appdport", &format_args!("{}", self.appdport().bit()))
-            .field(
-                "ahb_lite_sdhost_pid",
-                &format_args!("{}", self.ahb_lite_sdhost_pid().bits()),
-            )
+            .field("pro", &self.pro())
+            .field("app", &self.app())
+            .field("sdio", &self.sdio())
+            .field("prodport", &self.prodport())
+            .field("appdport", &self.appdport())
+            .field("ahb_lite_sdhost_pid", &self.ahb_lite_sdhost_pid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_LITE_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahb_mpu_table_0.rs b/esp32/src/dport/ahb_mpu_table_0.rs
index 915485a122..c3c7e93d1e 100644
--- a/esp32/src/dport/ahb_mpu_table_0.rs
+++ b/esp32/src/dport/ahb_mpu_table_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_MPU_TABLE_0")
-            .field(
-                "ahb_access_grant_0",
-                &format_args!("{}", self.ahb_access_grant_0().bits()),
-            )
+            .field("ahb_access_grant_0", &self.ahb_access_grant_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_MPU_TABLE_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahb_mpu_table_1.rs b/esp32/src/dport/ahb_mpu_table_1.rs
index 7b42fa734d..1d0dcd8bba 100644
--- a/esp32/src/dport/ahb_mpu_table_1.rs
+++ b/esp32/src/dport/ahb_mpu_table_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_MPU_TABLE_1")
-            .field(
-                "ahb_access_grant_1",
-                &format_args!("{}", self.ahb_access_grant_1().bits()),
-            )
+            .field("ahb_access_grant_1", &self.ahb_access_grant_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_MPU_TABLE_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_apb_ctrl.rs b/esp32/src/dport/ahblite_mpu_table_apb_ctrl.rs
index 6cd42c751e..a3f080aa8d 100644
--- a/esp32/src/dport/ahblite_mpu_table_apb_ctrl.rs
+++ b/esp32/src/dport/ahblite_mpu_table_apb_ctrl.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_APB_CTRL")
             .field(
                 "apbctrl_access_grant_config",
-                &format_args!("{}", self.apbctrl_access_grant_config().bits()),
+                &self.apbctrl_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_APB_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_bb.rs b/esp32/src/dport/ahblite_mpu_table_bb.rs
index c74b5f0774..27be3dc8fd 100644
--- a/esp32/src/dport/ahblite_mpu_table_bb.rs
+++ b/esp32/src/dport/ahblite_mpu_table_bb.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_BB")
-            .field(
-                "bb_access_grant_config",
-                &format_args!("{}", self.bb_access_grant_config().bits()),
-            )
+            .field("bb_access_grant_config", &self.bb_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_BB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_bt.rs b/esp32/src/dport/ahblite_mpu_table_bt.rs
index 18787babae..2842c25835 100644
--- a/esp32/src/dport/ahblite_mpu_table_bt.rs
+++ b/esp32/src/dport/ahblite_mpu_table_bt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_BT")
-            .field(
-                "bt_access_grant_config",
-                &format_args!("{}", self.bt_access_grant_config().bits()),
-            )
+            .field("bt_access_grant_config", &self.bt_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_BT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_bt_buffer.rs b/esp32/src/dport/ahblite_mpu_table_bt_buffer.rs
index 1abf0dd534..7f9a143b0f 100644
--- a/esp32/src/dport/ahblite_mpu_table_bt_buffer.rs
+++ b/esp32/src/dport/ahblite_mpu_table_bt_buffer.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_BT_BUFFER")
             .field(
                 "btbuffer_access_grant_config",
-                &format_args!("{}", self.btbuffer_access_grant_config().bits()),
+                &self.btbuffer_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_BT_BUFFER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_btmac.rs b/esp32/src/dport/ahblite_mpu_table_btmac.rs
index 505fb420fe..03178454e8 100644
--- a/esp32/src/dport/ahblite_mpu_table_btmac.rs
+++ b/esp32/src/dport/ahblite_mpu_table_btmac.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_BTMAC")
             .field(
                 "btmac_access_grant_config",
-                &format_args!("{}", self.btmac_access_grant_config().bits()),
+                &self.btmac_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_BTMAC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_can.rs b/esp32/src/dport/ahblite_mpu_table_can.rs
index 261884659b..cd28b29923 100644
--- a/esp32/src/dport/ahblite_mpu_table_can.rs
+++ b/esp32/src/dport/ahblite_mpu_table_can.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_CAN")
-            .field(
-                "can_access_grant_config",
-                &format_args!("{}", self.can_access_grant_config().bits()),
-            )
+            .field("can_access_grant_config", &self.can_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_CAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_efuse.rs b/esp32/src/dport/ahblite_mpu_table_efuse.rs
index f8f5365375..166f3c4c35 100644
--- a/esp32/src/dport/ahblite_mpu_table_efuse.rs
+++ b/esp32/src/dport/ahblite_mpu_table_efuse.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_EFUSE")
             .field(
                 "efuse_access_grant_config",
-                &format_args!("{}", self.efuse_access_grant_config().bits()),
+                &self.efuse_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_EFUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_emac.rs b/esp32/src/dport/ahblite_mpu_table_emac.rs
index 479967cef9..899c9f3199 100644
--- a/esp32/src/dport/ahblite_mpu_table_emac.rs
+++ b/esp32/src/dport/ahblite_mpu_table_emac.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_EMAC")
-            .field(
-                "emac_access_grant_config",
-                &format_args!("{}", self.emac_access_grant_config().bits()),
-            )
+            .field("emac_access_grant_config", &self.emac_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_EMAC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_fe.rs b/esp32/src/dport/ahblite_mpu_table_fe.rs
index d5550b3795..97af9898ef 100644
--- a/esp32/src/dport/ahblite_mpu_table_fe.rs
+++ b/esp32/src/dport/ahblite_mpu_table_fe.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_FE")
-            .field(
-                "fe_access_grant_config",
-                &format_args!("{}", self.fe_access_grant_config().bits()),
-            )
+            .field("fe_access_grant_config", &self.fe_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_FE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_fe2.rs b/esp32/src/dport/ahblite_mpu_table_fe2.rs
index 73ba4ea0f9..adec5d38a6 100644
--- a/esp32/src/dport/ahblite_mpu_table_fe2.rs
+++ b/esp32/src/dport/ahblite_mpu_table_fe2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_FE2")
-            .field(
-                "fe2_access_grant_config",
-                &format_args!("{}", self.fe2_access_grant_config().bits()),
-            )
+            .field("fe2_access_grant_config", &self.fe2_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_FE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_gpio.rs b/esp32/src/dport/ahblite_mpu_table_gpio.rs
index f3437ae7dd..e5a40f8f50 100644
--- a/esp32/src/dport/ahblite_mpu_table_gpio.rs
+++ b/esp32/src/dport/ahblite_mpu_table_gpio.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_GPIO")
-            .field(
-                "gpio_access_grant_config",
-                &format_args!("{}", self.gpio_access_grant_config().bits()),
-            )
+            .field("gpio_access_grant_config", &self.gpio_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_GPIO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_hinf.rs b/esp32/src/dport/ahblite_mpu_table_hinf.rs
index aa28ae5fea..5033a3cae1 100644
--- a/esp32/src/dport/ahblite_mpu_table_hinf.rs
+++ b/esp32/src/dport/ahblite_mpu_table_hinf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_HINF")
-            .field(
-                "hinf_access_grant_config",
-                &format_args!("{}", self.hinf_access_grant_config().bits()),
-            )
+            .field("hinf_access_grant_config", &self.hinf_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_HINF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_i2c.rs b/esp32/src/dport/ahblite_mpu_table_i2c.rs
index 295a1463e3..3f5fc195af 100644
--- a/esp32/src/dport/ahblite_mpu_table_i2c.rs
+++ b/esp32/src/dport/ahblite_mpu_table_i2c.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_I2C")
-            .field(
-                "i2c_access_grant_config",
-                &format_args!("{}", self.i2c_access_grant_config().bits()),
-            )
+            .field("i2c_access_grant_config", &self.i2c_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_I2C_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_i2c_ext0.rs b/esp32/src/dport/ahblite_mpu_table_i2c_ext0.rs
index 04211ebb97..b2a61091e7 100644
--- a/esp32/src/dport/ahblite_mpu_table_i2c_ext0.rs
+++ b/esp32/src/dport/ahblite_mpu_table_i2c_ext0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_I2C_EXT0")
             .field(
                 "i2cext0_access_grant_config",
-                &format_args!("{}", self.i2cext0_access_grant_config().bits()),
+                &self.i2cext0_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_I2C_EXT0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_i2c_ext1.rs b/esp32/src/dport/ahblite_mpu_table_i2c_ext1.rs
index c5e119d95c..b879e0ec37 100644
--- a/esp32/src/dport/ahblite_mpu_table_i2c_ext1.rs
+++ b/esp32/src/dport/ahblite_mpu_table_i2c_ext1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_I2C_EXT1")
             .field(
                 "i2cext1_access_grant_config",
-                &format_args!("{}", self.i2cext1_access_grant_config().bits()),
+                &self.i2cext1_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_I2C_EXT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_i2s0.rs b/esp32/src/dport/ahblite_mpu_table_i2s0.rs
index 446d765c7d..0c31ff0976 100644
--- a/esp32/src/dport/ahblite_mpu_table_i2s0.rs
+++ b/esp32/src/dport/ahblite_mpu_table_i2s0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_I2S0")
-            .field(
-                "i2s0_access_grant_config",
-                &format_args!("{}", self.i2s0_access_grant_config().bits()),
-            )
+            .field("i2s0_access_grant_config", &self.i2s0_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_I2S0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_i2s1.rs b/esp32/src/dport/ahblite_mpu_table_i2s1.rs
index 51c449e0e4..8624f66b0b 100644
--- a/esp32/src/dport/ahblite_mpu_table_i2s1.rs
+++ b/esp32/src/dport/ahblite_mpu_table_i2s1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_I2S1")
-            .field(
-                "i2s1_access_grant_config",
-                &format_args!("{}", self.i2s1_access_grant_config().bits()),
-            )
+            .field("i2s1_access_grant_config", &self.i2s1_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_I2S1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_io_mux.rs b/esp32/src/dport/ahblite_mpu_table_io_mux.rs
index 612b367bbe..e3f684f693 100644
--- a/esp32/src/dport/ahblite_mpu_table_io_mux.rs
+++ b/esp32/src/dport/ahblite_mpu_table_io_mux.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_IO_MUX")
             .field(
                 "iomux_access_grant_config",
-                &format_args!("{}", self.iomux_access_grant_config().bits()),
+                &self.iomux_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_IO_MUX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_ledc.rs b/esp32/src/dport/ahblite_mpu_table_ledc.rs
index 18c787fcc9..132af2e32d 100644
--- a/esp32/src/dport/ahblite_mpu_table_ledc.rs
+++ b/esp32/src/dport/ahblite_mpu_table_ledc.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_LEDC")
-            .field(
-                "ledc_access_grant_config",
-                &format_args!("{}", self.ledc_access_grant_config().bits()),
-            )
+            .field("ledc_access_grant_config", &self.ledc_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_LEDC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_misc.rs b/esp32/src/dport/ahblite_mpu_table_misc.rs
index 13edabafe5..d81b90c4b3 100644
--- a/esp32/src/dport/ahblite_mpu_table_misc.rs
+++ b/esp32/src/dport/ahblite_mpu_table_misc.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_MISC")
-            .field(
-                "misc_access_grant_config",
-                &format_args!("{}", self.misc_access_grant_config().bits()),
-            )
+            .field("misc_access_grant_config", &self.misc_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_pcnt.rs b/esp32/src/dport/ahblite_mpu_table_pcnt.rs
index 3f9e01050b..30705c9459 100644
--- a/esp32/src/dport/ahblite_mpu_table_pcnt.rs
+++ b/esp32/src/dport/ahblite_mpu_table_pcnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_PCNT")
-            .field(
-                "pcnt_access_grant_config",
-                &format_args!("{}", self.pcnt_access_grant_config().bits()),
-            )
+            .field("pcnt_access_grant_config", &self.pcnt_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_PCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_pwm0.rs b/esp32/src/dport/ahblite_mpu_table_pwm0.rs
index ddf3145a90..716a6e95fa 100644
--- a/esp32/src/dport/ahblite_mpu_table_pwm0.rs
+++ b/esp32/src/dport/ahblite_mpu_table_pwm0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_PWM0")
-            .field(
-                "pwm0_access_grant_config",
-                &format_args!("{}", self.pwm0_access_grant_config().bits()),
-            )
+            .field("pwm0_access_grant_config", &self.pwm0_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_PWM0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_pwm1.rs b/esp32/src/dport/ahblite_mpu_table_pwm1.rs
index a508fbb3ff..9cf8bb4562 100644
--- a/esp32/src/dport/ahblite_mpu_table_pwm1.rs
+++ b/esp32/src/dport/ahblite_mpu_table_pwm1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_PWM1")
-            .field(
-                "pwm1_access_grant_config",
-                &format_args!("{}", self.pwm1_access_grant_config().bits()),
-            )
+            .field("pwm1_access_grant_config", &self.pwm1_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_PWM1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_pwm2.rs b/esp32/src/dport/ahblite_mpu_table_pwm2.rs
index 55a8b0cb4d..0cbdfb6cbe 100644
--- a/esp32/src/dport/ahblite_mpu_table_pwm2.rs
+++ b/esp32/src/dport/ahblite_mpu_table_pwm2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_PWM2")
-            .field(
-                "pwm2_access_grant_config",
-                &format_args!("{}", self.pwm2_access_grant_config().bits()),
-            )
+            .field("pwm2_access_grant_config", &self.pwm2_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_PWM2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_pwm3.rs b/esp32/src/dport/ahblite_mpu_table_pwm3.rs
index d4b5704d82..25b2f3ece4 100644
--- a/esp32/src/dport/ahblite_mpu_table_pwm3.rs
+++ b/esp32/src/dport/ahblite_mpu_table_pwm3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_PWM3")
-            .field(
-                "pwm3_access_grant_config",
-                &format_args!("{}", self.pwm3_access_grant_config().bits()),
-            )
+            .field("pwm3_access_grant_config", &self.pwm3_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_PWM3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_pwr.rs b/esp32/src/dport/ahblite_mpu_table_pwr.rs
index 47acf20383..ac33d84e09 100644
--- a/esp32/src/dport/ahblite_mpu_table_pwr.rs
+++ b/esp32/src/dport/ahblite_mpu_table_pwr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_PWR")
-            .field(
-                "pwr_access_grant_config",
-                &format_args!("{}", self.pwr_access_grant_config().bits()),
-            )
+            .field("pwr_access_grant_config", &self.pwr_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_PWR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_rmt.rs b/esp32/src/dport/ahblite_mpu_table_rmt.rs
index d1add53796..ff97e184c5 100644
--- a/esp32/src/dport/ahblite_mpu_table_rmt.rs
+++ b/esp32/src/dport/ahblite_mpu_table_rmt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_RMT")
-            .field(
-                "rmt_access_grant_config",
-                &format_args!("{}", self.rmt_access_grant_config().bits()),
-            )
+            .field("rmt_access_grant_config", &self.rmt_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_RMT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_rtc.rs b/esp32/src/dport/ahblite_mpu_table_rtc.rs
index 59fa7b00da..4ed265edc6 100644
--- a/esp32/src/dport/ahblite_mpu_table_rtc.rs
+++ b/esp32/src/dport/ahblite_mpu_table_rtc.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_RTC")
-            .field(
-                "rtc_access_grant_config",
-                &format_args!("{}", self.rtc_access_grant_config().bits()),
-            )
+            .field("rtc_access_grant_config", &self.rtc_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_RTC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_rwbt.rs b/esp32/src/dport/ahblite_mpu_table_rwbt.rs
index 44189ea0d3..d84bf28e64 100644
--- a/esp32/src/dport/ahblite_mpu_table_rwbt.rs
+++ b/esp32/src/dport/ahblite_mpu_table_rwbt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_RWBT")
-            .field(
-                "rwbt_access_grant_config",
-                &format_args!("{}", self.rwbt_access_grant_config().bits()),
-            )
+            .field("rwbt_access_grant_config", &self.rwbt_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_RWBT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_sdio_host.rs b/esp32/src/dport/ahblite_mpu_table_sdio_host.rs
index 8f02f43c6b..8e52e985f7 100644
--- a/esp32/src/dport/ahblite_mpu_table_sdio_host.rs
+++ b/esp32/src/dport/ahblite_mpu_table_sdio_host.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_SDIO_HOST")
             .field(
                 "sdiohost_access_grant_config",
-                &format_args!("{}", self.sdiohost_access_grant_config().bits()),
+                &self.sdiohost_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_SDIO_HOST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_slc.rs b/esp32/src/dport/ahblite_mpu_table_slc.rs
index f5e61479f3..369e2879bb 100644
--- a/esp32/src/dport/ahblite_mpu_table_slc.rs
+++ b/esp32/src/dport/ahblite_mpu_table_slc.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_SLC")
-            .field(
-                "slc_access_grant_config",
-                &format_args!("{}", self.slc_access_grant_config().bits()),
-            )
+            .field("slc_access_grant_config", &self.slc_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_SLC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_slchost.rs b/esp32/src/dport/ahblite_mpu_table_slchost.rs
index 08c303b1cc..e52b0068e8 100644
--- a/esp32/src/dport/ahblite_mpu_table_slchost.rs
+++ b/esp32/src/dport/ahblite_mpu_table_slchost.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_SLCHOST")
             .field(
                 "slchost_access_grant_config",
-                &format_args!("{}", self.slchost_access_grant_config().bits()),
+                &self.slchost_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_SLCHOST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_spi0.rs b/esp32/src/dport/ahblite_mpu_table_spi0.rs
index b2bed06fc4..68e5a80c9d 100644
--- a/esp32/src/dport/ahblite_mpu_table_spi0.rs
+++ b/esp32/src/dport/ahblite_mpu_table_spi0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_SPI0")
-            .field(
-                "spi0_access_grant_config",
-                &format_args!("{}", self.spi0_access_grant_config().bits()),
-            )
+            .field("spi0_access_grant_config", &self.spi0_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_SPI0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_spi1.rs b/esp32/src/dport/ahblite_mpu_table_spi1.rs
index fe7eadff76..bf7d1a3530 100644
--- a/esp32/src/dport/ahblite_mpu_table_spi1.rs
+++ b/esp32/src/dport/ahblite_mpu_table_spi1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_SPI1")
-            .field(
-                "spi1_access_grant_config",
-                &format_args!("{}", self.spi1_access_grant_config().bits()),
-            )
+            .field("spi1_access_grant_config", &self.spi1_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_SPI1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_spi2.rs b/esp32/src/dport/ahblite_mpu_table_spi2.rs
index b4d1e5b46c..c3b9a7efd0 100644
--- a/esp32/src/dport/ahblite_mpu_table_spi2.rs
+++ b/esp32/src/dport/ahblite_mpu_table_spi2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_SPI2")
-            .field(
-                "spi2_access_grant_config",
-                &format_args!("{}", self.spi2_access_grant_config().bits()),
-            )
+            .field("spi2_access_grant_config", &self.spi2_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_SPI2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_spi3.rs b/esp32/src/dport/ahblite_mpu_table_spi3.rs
index dc2edbbe43..f842c1dc82 100644
--- a/esp32/src/dport/ahblite_mpu_table_spi3.rs
+++ b/esp32/src/dport/ahblite_mpu_table_spi3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_SPI3")
-            .field(
-                "spi3_access_grant_config",
-                &format_args!("{}", self.spi3_access_grant_config().bits()),
-            )
+            .field("spi3_access_grant_config", &self.spi3_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_SPI3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_spi_encrypt.rs b/esp32/src/dport/ahblite_mpu_table_spi_encrypt.rs
index 8618a1de0c..b316951583 100644
--- a/esp32/src/dport/ahblite_mpu_table_spi_encrypt.rs
+++ b/esp32/src/dport/ahblite_mpu_table_spi_encrypt.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_SPI_ENCRYPT")
             .field(
                 "spi_encrypy_access_grant_config",
-                &format_args!("{}", self.spi_encrypy_access_grant_config().bits()),
+                &self.spi_encrypy_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_SPI_ENCRYPT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_timer.rs b/esp32/src/dport/ahblite_mpu_table_timer.rs
index c6412cbd5c..b280f0f79f 100644
--- a/esp32/src/dport/ahblite_mpu_table_timer.rs
+++ b/esp32/src/dport/ahblite_mpu_table_timer.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_TIMER")
             .field(
                 "timer_access_grant_config",
-                &format_args!("{}", self.timer_access_grant_config().bits()),
+                &self.timer_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_TIMER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_timergroup.rs b/esp32/src/dport/ahblite_mpu_table_timergroup.rs
index 02dc448faa..2790eb5269 100644
--- a/esp32/src/dport/ahblite_mpu_table_timergroup.rs
+++ b/esp32/src/dport/ahblite_mpu_table_timergroup.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_TIMERGROUP")
             .field(
                 "timergroup_access_grant_config",
-                &format_args!("{}", self.timergroup_access_grant_config().bits()),
+                &self.timergroup_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_TIMERGROUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_timergroup1.rs b/esp32/src/dport/ahblite_mpu_table_timergroup1.rs
index 6db6757ab8..1792b8d0a2 100644
--- a/esp32/src/dport/ahblite_mpu_table_timergroup1.rs
+++ b/esp32/src/dport/ahblite_mpu_table_timergroup1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_TIMERGROUP1")
             .field(
                 "timergroup1_access_grant_config",
-                &format_args!("{}", self.timergroup1_access_grant_config().bits()),
+                &self.timergroup1_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_TIMERGROUP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_uart.rs b/esp32/src/dport/ahblite_mpu_table_uart.rs
index 1746c6f051..1a943a61c6 100644
--- a/esp32/src/dport/ahblite_mpu_table_uart.rs
+++ b/esp32/src/dport/ahblite_mpu_table_uart.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_UART")
-            .field(
-                "uart_access_grant_config",
-                &format_args!("{}", self.uart_access_grant_config().bits()),
-            )
+            .field("uart_access_grant_config", &self.uart_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_UART_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_uart1.rs b/esp32/src/dport/ahblite_mpu_table_uart1.rs
index b07fee0c40..8f985f8d8f 100644
--- a/esp32/src/dport/ahblite_mpu_table_uart1.rs
+++ b/esp32/src/dport/ahblite_mpu_table_uart1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_UART1")
             .field(
                 "uart1_access_grant_config",
-                &format_args!("{}", self.uart1_access_grant_config().bits()),
+                &self.uart1_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_UART1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_uart2.rs b/esp32/src/dport/ahblite_mpu_table_uart2.rs
index 3c683dea9f..1840a38f7b 100644
--- a/esp32/src/dport/ahblite_mpu_table_uart2.rs
+++ b/esp32/src/dport/ahblite_mpu_table_uart2.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_UART2")
             .field(
                 "uart2_access_grant_config",
-                &format_args!("{}", self.uart2_access_grant_config().bits()),
+                &self.uart2_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_UART2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_uhci0.rs b/esp32/src/dport/ahblite_mpu_table_uhci0.rs
index e29ab2dfe4..377692119b 100644
--- a/esp32/src/dport/ahblite_mpu_table_uhci0.rs
+++ b/esp32/src/dport/ahblite_mpu_table_uhci0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_UHCI0")
             .field(
                 "uhci0_access_grant_config",
-                &format_args!("{}", self.uhci0_access_grant_config().bits()),
+                &self.uhci0_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_UHCI0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_uhci1.rs b/esp32/src/dport/ahblite_mpu_table_uhci1.rs
index 272b5d8ee8..420de37dbc 100644
--- a/esp32/src/dport/ahblite_mpu_table_uhci1.rs
+++ b/esp32/src/dport/ahblite_mpu_table_uhci1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_UHCI1")
             .field(
                 "uhci1_access_grant_config",
-                &format_args!("{}", self.uhci1_access_grant_config().bits()),
+                &self.uhci1_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_UHCI1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_wdg.rs b/esp32/src/dport/ahblite_mpu_table_wdg.rs
index 4ccf693e3e..81507b2e21 100644
--- a/esp32/src/dport/ahblite_mpu_table_wdg.rs
+++ b/esp32/src/dport/ahblite_mpu_table_wdg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHBLITE_MPU_TABLE_WDG")
-            .field(
-                "wdg_access_grant_config",
-                &format_args!("{}", self.wdg_access_grant_config().bits()),
-            )
+            .field("wdg_access_grant_config", &self.wdg_access_grant_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_WDG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/ahblite_mpu_table_wifimac.rs b/esp32/src/dport/ahblite_mpu_table_wifimac.rs
index ae27d56b7a..2b18e3ceb4 100644
--- a/esp32/src/dport/ahblite_mpu_table_wifimac.rs
+++ b/esp32/src/dport/ahblite_mpu_table_wifimac.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHBLITE_MPU_TABLE_WIFIMAC")
             .field(
                 "wifimac_access_grant_config",
-                &format_args!("{}", self.wifimac_access_grant_config().bits()),
+                &self.wifimac_access_grant_config(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHBLITE_MPU_TABLE_WIFIMAC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_bb_int_map.rs b/esp32/src/dport/app_bb_int_map.rs
index cea937023e..dfbc898de1 100644
--- a/esp32/src/dport/app_bb_int_map.rs
+++ b/esp32/src/dport/app_bb_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_BB_INT_MAP")
-            .field(
-                "app_bb_int_map",
-                &format_args!("{}", self.app_bb_int_map().bits()),
-            )
+            .field("app_bb_int_map", &self.app_bb_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_BB_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_boot_remap_ctrl.rs b/esp32/src/dport/app_boot_remap_ctrl.rs
index 4e47c2e6da..8210bacf43 100644
--- a/esp32/src/dport/app_boot_remap_ctrl.rs
+++ b/esp32/src/dport/app_boot_remap_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_BOOT_REMAP_CTRL")
-            .field(
-                "app_boot_remap",
-                &format_args!("{}", self.app_boot_remap().bit()),
-            )
+            .field("app_boot_remap", &self.app_boot_remap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_BOOT_REMAP_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_bt_bb_int_map.rs b/esp32/src/dport/app_bt_bb_int_map.rs
index c45b360155..cc29019af8 100644
--- a/esp32/src/dport/app_bt_bb_int_map.rs
+++ b/esp32/src/dport/app_bt_bb_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_BT_BB_INT_MAP")
-            .field(
-                "app_bt_bb_int_map",
-                &format_args!("{}", self.app_bt_bb_int_map().bits()),
-            )
+            .field("app_bt_bb_int_map", &self.app_bt_bb_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_BT_BB_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_bt_bb_nmi_map.rs b/esp32/src/dport/app_bt_bb_nmi_map.rs
index e99b4d7c2f..95d5005c24 100644
--- a/esp32/src/dport/app_bt_bb_nmi_map.rs
+++ b/esp32/src/dport/app_bt_bb_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_BT_BB_NMI_MAP")
-            .field(
-                "app_bt_bb_nmi_map",
-                &format_args!("{}", self.app_bt_bb_nmi_map().bits()),
-            )
+            .field("app_bt_bb_nmi_map", &self.app_bt_bb_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_BT_BB_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_bt_mac_int_map.rs b/esp32/src/dport/app_bt_mac_int_map.rs
index b89b9d524f..4f2acc1a9a 100644
--- a/esp32/src/dport/app_bt_mac_int_map.rs
+++ b/esp32/src/dport/app_bt_mac_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_BT_MAC_INT_MAP")
-            .field(
-                "app_bt_mac_int_map",
-                &format_args!("{}", self.app_bt_mac_int_map().bits()),
-            )
+            .field("app_bt_mac_int_map", &self.app_bt_mac_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_BT_MAC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_cache_ctrl.rs b/esp32/src/dport/app_cache_ctrl.rs
index fcb5516150..2da975e25d 100644
--- a/esp32/src/dport/app_cache_ctrl.rs
+++ b/esp32/src/dport/app_cache_ctrl.rs
@@ -119,64 +119,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CACHE_CTRL")
-            .field(
-                "app_cache_mode",
-                &format_args!("{}", self.app_cache_mode().bit()),
-            )
-            .field(
-                "app_cache_enable",
-                &format_args!("{}", self.app_cache_enable().bit()),
-            )
-            .field(
-                "app_cache_flush_ena",
-                &format_args!("{}", self.app_cache_flush_ena().bit()),
-            )
-            .field(
-                "app_cache_flush_done",
-                &format_args!("{}", self.app_cache_flush_done().bit()),
-            )
-            .field(
-                "app_cache_lock_0_en",
-                &format_args!("{}", self.app_cache_lock_0_en().bit()),
-            )
-            .field(
-                "app_cache_lock_1_en",
-                &format_args!("{}", self.app_cache_lock_1_en().bit()),
-            )
-            .field(
-                "app_cache_lock_2_en",
-                &format_args!("{}", self.app_cache_lock_2_en().bit()),
-            )
-            .field(
-                "app_cache_lock_3_en",
-                &format_args!("{}", self.app_cache_lock_3_en().bit()),
-            )
-            .field(
-                "app_single_iram_ena",
-                &format_args!("{}", self.app_single_iram_ena().bit()),
-            )
-            .field(
-                "app_dram_split",
-                &format_args!("{}", self.app_dram_split().bit()),
-            )
-            .field(
-                "app_ahb_spi_req",
-                &format_args!("{}", self.app_ahb_spi_req().bit()),
-            )
-            .field(
-                "app_slave_req",
-                &format_args!("{}", self.app_slave_req().bit()),
-            )
-            .field("app_dram_hl", &format_args!("{}", self.app_dram_hl().bit()))
+            .field("app_cache_mode", &self.app_cache_mode())
+            .field("app_cache_enable", &self.app_cache_enable())
+            .field("app_cache_flush_ena", &self.app_cache_flush_ena())
+            .field("app_cache_flush_done", &self.app_cache_flush_done())
+            .field("app_cache_lock_0_en", &self.app_cache_lock_0_en())
+            .field("app_cache_lock_1_en", &self.app_cache_lock_1_en())
+            .field("app_cache_lock_2_en", &self.app_cache_lock_2_en())
+            .field("app_cache_lock_3_en", &self.app_cache_lock_3_en())
+            .field("app_single_iram_ena", &self.app_single_iram_ena())
+            .field("app_dram_split", &self.app_dram_split())
+            .field("app_ahb_spi_req", &self.app_ahb_spi_req())
+            .field("app_slave_req", &self.app_slave_req())
+            .field("app_dram_hl", &self.app_dram_hl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CACHE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_cache_ctrl1.rs b/esp32/src/dport/app_cache_ctrl1.rs
index bb96301d88..6dbe5a3c14 100644
--- a/esp32/src/dport/app_cache_ctrl1.rs
+++ b/esp32/src/dport/app_cache_ctrl1.rs
@@ -107,56 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CACHE_CTRL1")
-            .field(
-                "app_cache_mask_iram0",
-                &format_args!("{}", self.app_cache_mask_iram0().bit()),
-            )
-            .field(
-                "app_cache_mask_iram1",
-                &format_args!("{}", self.app_cache_mask_iram1().bit()),
-            )
-            .field(
-                "app_cache_mask_irom0",
-                &format_args!("{}", self.app_cache_mask_irom0().bit()),
-            )
-            .field(
-                "app_cache_mask_dram1",
-                &format_args!("{}", self.app_cache_mask_dram1().bit()),
-            )
-            .field(
-                "app_cache_mask_drom0",
-                &format_args!("{}", self.app_cache_mask_drom0().bit()),
-            )
-            .field(
-                "app_cache_mask_opsdram",
-                &format_args!("{}", self.app_cache_mask_opsdram().bit()),
-            )
-            .field(
-                "app_cmmu_sram_page_mode",
-                &format_args!("{}", self.app_cmmu_sram_page_mode().bits()),
-            )
-            .field(
-                "app_cmmu_flash_page_mode",
-                &format_args!("{}", self.app_cmmu_flash_page_mode().bits()),
-            )
-            .field(
-                "app_cmmu_force_on",
-                &format_args!("{}", self.app_cmmu_force_on().bit()),
-            )
-            .field("app_cmmu_pd", &format_args!("{}", self.app_cmmu_pd().bit()))
-            .field(
-                "app_cache_mmu_ia_clr",
-                &format_args!("{}", self.app_cache_mmu_ia_clr().bit()),
-            )
+            .field("app_cache_mask_iram0", &self.app_cache_mask_iram0())
+            .field("app_cache_mask_iram1", &self.app_cache_mask_iram1())
+            .field("app_cache_mask_irom0", &self.app_cache_mask_irom0())
+            .field("app_cache_mask_dram1", &self.app_cache_mask_dram1())
+            .field("app_cache_mask_drom0", &self.app_cache_mask_drom0())
+            .field("app_cache_mask_opsdram", &self.app_cache_mask_opsdram())
+            .field("app_cmmu_sram_page_mode", &self.app_cmmu_sram_page_mode())
+            .field("app_cmmu_flash_page_mode", &self.app_cmmu_flash_page_mode())
+            .field("app_cmmu_force_on", &self.app_cmmu_force_on())
+            .field("app_cmmu_pd", &self.app_cmmu_pd())
+            .field("app_cache_mmu_ia_clr", &self.app_cache_mmu_ia_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CACHE_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_cache_ia_int_map.rs b/esp32/src/dport/app_cache_ia_int_map.rs
index efdeca4d97..22a7d90657 100644
--- a/esp32/src/dport/app_cache_ia_int_map.rs
+++ b/esp32/src/dport/app_cache_ia_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CACHE_IA_INT_MAP")
-            .field(
-                "app_cache_ia_int_map",
-                &format_args!("{}", self.app_cache_ia_int_map().bits()),
-            )
+            .field("app_cache_ia_int_map", &self.app_cache_ia_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CACHE_IA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_cache_lock_0_addr.rs b/esp32/src/dport/app_cache_lock_0_addr.rs
index fc6ea21d3c..d5ec5db343 100644
--- a/esp32/src/dport/app_cache_lock_0_addr.rs
+++ b/esp32/src/dport/app_cache_lock_0_addr.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CACHE_LOCK_0_ADDR")
-            .field("pre", &format_args!("{}", self.pre().bits()))
-            .field("min", &format_args!("{}", self.min().bits()))
-            .field("max", &format_args!("{}", self.max().bits()))
+            .field("pre", &self.pre())
+            .field("min", &self.min())
+            .field("max", &self.max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CACHE_LOCK_0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_cache_lock_1_addr.rs b/esp32/src/dport/app_cache_lock_1_addr.rs
index 428e20cbc8..dc3b20132a 100644
--- a/esp32/src/dport/app_cache_lock_1_addr.rs
+++ b/esp32/src/dport/app_cache_lock_1_addr.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CACHE_LOCK_1_ADDR")
-            .field("pre", &format_args!("{}", self.pre().bits()))
-            .field("min", &format_args!("{}", self.min().bits()))
-            .field("max", &format_args!("{}", self.max().bits()))
+            .field("pre", &self.pre())
+            .field("min", &self.min())
+            .field("max", &self.max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CACHE_LOCK_1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_cache_lock_2_addr.rs b/esp32/src/dport/app_cache_lock_2_addr.rs
index f3eb077a52..93399dcd1d 100644
--- a/esp32/src/dport/app_cache_lock_2_addr.rs
+++ b/esp32/src/dport/app_cache_lock_2_addr.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CACHE_LOCK_2_ADDR")
-            .field("pre", &format_args!("{}", self.pre().bits()))
-            .field("min", &format_args!("{}", self.min().bits()))
-            .field("max", &format_args!("{}", self.max().bits()))
+            .field("pre", &self.pre())
+            .field("min", &self.min())
+            .field("max", &self.max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CACHE_LOCK_2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_cache_lock_3_addr.rs b/esp32/src/dport/app_cache_lock_3_addr.rs
index 363869e7a8..29b08a9a0c 100644
--- a/esp32/src/dport/app_cache_lock_3_addr.rs
+++ b/esp32/src/dport/app_cache_lock_3_addr.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CACHE_LOCK_3_ADDR")
-            .field("pre", &format_args!("{}", self.pre().bits()))
-            .field("min", &format_args!("{}", self.min().bits()))
-            .field("max", &format_args!("{}", self.max().bits()))
+            .field("pre", &self.pre())
+            .field("min", &self.min())
+            .field("max", &self.max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CACHE_LOCK_3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_can_int_map.rs b/esp32/src/dport/app_can_int_map.rs
index 0d89e806c1..c4278c07a2 100644
--- a/esp32/src/dport/app_can_int_map.rs
+++ b/esp32/src/dport/app_can_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CAN_INT_MAP")
-            .field(
-                "app_can_int_map",
-                &format_args!("{}", self.app_can_int_map().bits()),
-            )
+            .field("app_can_int_map", &self.app_can_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CAN_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_cpu_intr_from_cpu_0_map.rs b/esp32/src/dport/app_cpu_intr_from_cpu_0_map.rs
index ddebaaecde..46cfc3e457 100644
--- a/esp32/src/dport/app_cpu_intr_from_cpu_0_map.rs
+++ b/esp32/src/dport/app_cpu_intr_from_cpu_0_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APP_CPU_INTR_FROM_CPU_0_MAP")
             .field(
                 "app_cpu_intr_from_cpu_0_map",
-                &format_args!("{}", self.app_cpu_intr_from_cpu_0_map().bits()),
+                &self.app_cpu_intr_from_cpu_0_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CPU_INTR_FROM_CPU_0_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_cpu_intr_from_cpu_1_map.rs b/esp32/src/dport/app_cpu_intr_from_cpu_1_map.rs
index 06e7cfa9e8..af473dc828 100644
--- a/esp32/src/dport/app_cpu_intr_from_cpu_1_map.rs
+++ b/esp32/src/dport/app_cpu_intr_from_cpu_1_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APP_CPU_INTR_FROM_CPU_1_MAP")
             .field(
                 "app_cpu_intr_from_cpu_1_map",
-                &format_args!("{}", self.app_cpu_intr_from_cpu_1_map().bits()),
+                &self.app_cpu_intr_from_cpu_1_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CPU_INTR_FROM_CPU_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_cpu_intr_from_cpu_2_map.rs b/esp32/src/dport/app_cpu_intr_from_cpu_2_map.rs
index 1421bed22e..1dfc109d08 100644
--- a/esp32/src/dport/app_cpu_intr_from_cpu_2_map.rs
+++ b/esp32/src/dport/app_cpu_intr_from_cpu_2_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APP_CPU_INTR_FROM_CPU_2_MAP")
             .field(
                 "app_cpu_intr_from_cpu_2_map",
-                &format_args!("{}", self.app_cpu_intr_from_cpu_2_map().bits()),
+                &self.app_cpu_intr_from_cpu_2_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CPU_INTR_FROM_CPU_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_cpu_intr_from_cpu_3_map.rs b/esp32/src/dport/app_cpu_intr_from_cpu_3_map.rs
index 20c1b8d510..9410e656e8 100644
--- a/esp32/src/dport/app_cpu_intr_from_cpu_3_map.rs
+++ b/esp32/src/dport/app_cpu_intr_from_cpu_3_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APP_CPU_INTR_FROM_CPU_3_MAP")
             .field(
                 "app_cpu_intr_from_cpu_3_map",
-                &format_args!("{}", self.app_cpu_intr_from_cpu_3_map().bits()),
+                &self.app_cpu_intr_from_cpu_3_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CPU_INTR_FROM_CPU_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_cpu_record_ctrl.rs b/esp32/src/dport/app_cpu_record_ctrl.rs
index f4b996f2c0..49f78e5658 100644
--- a/esp32/src/dport/app_cpu_record_ctrl.rs
+++ b/esp32/src/dport/app_cpu_record_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CPU_RECORD_CTRL")
-            .field(
-                "app_cpu_record_enable",
-                &format_args!("{}", self.app_cpu_record_enable().bit()),
-            )
-            .field(
-                "app_cpu_record_disable",
-                &format_args!("{}", self.app_cpu_record_disable().bit()),
-            )
-            .field(
-                "app_cpu_pdebug_enable",
-                &format_args!("{}", self.app_cpu_pdebug_enable().bit()),
-            )
+            .field("app_cpu_record_enable", &self.app_cpu_record_enable())
+            .field("app_cpu_record_disable", &self.app_cpu_record_disable())
+            .field("app_cpu_pdebug_enable", &self.app_cpu_pdebug_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CPU_RECORD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_cpu_record_pdebugdata.rs b/esp32/src/dport/app_cpu_record_pdebugdata.rs
index 60d10d2cf1..102d93c2be 100644
--- a/esp32/src/dport/app_cpu_record_pdebugdata.rs
+++ b/esp32/src/dport/app_cpu_record_pdebugdata.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CPU_RECORD_PDEBUGDATA")
-            .field(
-                "record_app_pdebugdata",
-                &format_args!("{}", self.record_app_pdebugdata().bits()),
-            )
+            .field("record_app_pdebugdata", &self.record_app_pdebugdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CPU_RECORD_PDEBUGDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_cpu_record_pdebugdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_CPU_RECORD_PDEBUGDATA_SPEC;
 impl crate::RegisterSpec for APP_CPU_RECORD_PDEBUGDATA_SPEC {
diff --git a/esp32/src/dport/app_cpu_record_pdebuginst.rs b/esp32/src/dport/app_cpu_record_pdebuginst.rs
index d593165330..1be335127c 100644
--- a/esp32/src/dport/app_cpu_record_pdebuginst.rs
+++ b/esp32/src/dport/app_cpu_record_pdebuginst.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CPU_RECORD_PDEBUGINST")
-            .field(
-                "record_app_pdebuginst",
-                &format_args!("{}", self.record_app_pdebuginst().bits()),
-            )
+            .field("record_app_pdebuginst", &self.record_app_pdebuginst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CPU_RECORD_PDEBUGINST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_cpu_record_pdebuginst::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_CPU_RECORD_PDEBUGINST_SPEC;
 impl crate::RegisterSpec for APP_CPU_RECORD_PDEBUGINST_SPEC {
diff --git a/esp32/src/dport/app_cpu_record_pdebugls0addr.rs b/esp32/src/dport/app_cpu_record_pdebugls0addr.rs
index d099026156..68a77b3e4b 100644
--- a/esp32/src/dport/app_cpu_record_pdebugls0addr.rs
+++ b/esp32/src/dport/app_cpu_record_pdebugls0addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CPU_RECORD_PDEBUGLS0ADDR")
-            .field(
-                "record_app_pdebugls0addr",
-                &format_args!("{}", self.record_app_pdebugls0addr().bits()),
-            )
+            .field("record_app_pdebugls0addr", &self.record_app_pdebugls0addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CPU_RECORD_PDEBUGLS0ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_cpu_record_pdebugls0addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_CPU_RECORD_PDEBUGLS0ADDR_SPEC;
 impl crate::RegisterSpec for APP_CPU_RECORD_PDEBUGLS0ADDR_SPEC {
diff --git a/esp32/src/dport/app_cpu_record_pdebugls0data.rs b/esp32/src/dport/app_cpu_record_pdebugls0data.rs
index ad3a96da47..e8d23a69ee 100644
--- a/esp32/src/dport/app_cpu_record_pdebugls0data.rs
+++ b/esp32/src/dport/app_cpu_record_pdebugls0data.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CPU_RECORD_PDEBUGLS0DATA")
-            .field(
-                "record_app_pdebugls0data",
-                &format_args!("{}", self.record_app_pdebugls0data().bits()),
-            )
+            .field("record_app_pdebugls0data", &self.record_app_pdebugls0data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CPU_RECORD_PDEBUGLS0DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_cpu_record_pdebugls0data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_CPU_RECORD_PDEBUGLS0DATA_SPEC;
 impl crate::RegisterSpec for APP_CPU_RECORD_PDEBUGLS0DATA_SPEC {
diff --git a/esp32/src/dport/app_cpu_record_pdebugls0stat.rs b/esp32/src/dport/app_cpu_record_pdebugls0stat.rs
index 98d69689c1..ab89ec382c 100644
--- a/esp32/src/dport/app_cpu_record_pdebugls0stat.rs
+++ b/esp32/src/dport/app_cpu_record_pdebugls0stat.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CPU_RECORD_PDEBUGLS0STAT")
-            .field(
-                "record_app_pdebugls0stat",
-                &format_args!("{}", self.record_app_pdebugls0stat().bits()),
-            )
+            .field("record_app_pdebugls0stat", &self.record_app_pdebugls0stat())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CPU_RECORD_PDEBUGLS0STAT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_cpu_record_pdebugls0stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_CPU_RECORD_PDEBUGLS0STAT_SPEC;
 impl crate::RegisterSpec for APP_CPU_RECORD_PDEBUGLS0STAT_SPEC {
diff --git a/esp32/src/dport/app_cpu_record_pdebugpc.rs b/esp32/src/dport/app_cpu_record_pdebugpc.rs
index 8b122714e6..16757a7f2c 100644
--- a/esp32/src/dport/app_cpu_record_pdebugpc.rs
+++ b/esp32/src/dport/app_cpu_record_pdebugpc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CPU_RECORD_PDEBUGPC")
-            .field(
-                "record_app_pdebugpc",
-                &format_args!("{}", self.record_app_pdebugpc().bits()),
-            )
+            .field("record_app_pdebugpc", &self.record_app_pdebugpc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CPU_RECORD_PDEBUGPC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_cpu_record_pdebugpc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_CPU_RECORD_PDEBUGPC_SPEC;
 impl crate::RegisterSpec for APP_CPU_RECORD_PDEBUGPC_SPEC {
diff --git a/esp32/src/dport/app_cpu_record_pdebugstatus.rs b/esp32/src/dport/app_cpu_record_pdebugstatus.rs
index 51f1f6c8c3..b5284f43b5 100644
--- a/esp32/src/dport/app_cpu_record_pdebugstatus.rs
+++ b/esp32/src/dport/app_cpu_record_pdebugstatus.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CPU_RECORD_PDEBUGSTATUS")
-            .field(
-                "record_app_pdebugstatus",
-                &format_args!("{}", self.record_app_pdebugstatus().bits()),
-            )
+            .field("record_app_pdebugstatus", &self.record_app_pdebugstatus())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CPU_RECORD_PDEBUGSTATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_cpu_record_pdebugstatus::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_CPU_RECORD_PDEBUGSTATUS_SPEC;
 impl crate::RegisterSpec for APP_CPU_RECORD_PDEBUGSTATUS_SPEC {
diff --git a/esp32/src/dport/app_cpu_record_pid.rs b/esp32/src/dport/app_cpu_record_pid.rs
index 1ef7ae908c..d4e9f8390f 100644
--- a/esp32/src/dport/app_cpu_record_pid.rs
+++ b/esp32/src/dport/app_cpu_record_pid.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CPU_RECORD_PID")
-            .field(
-                "record_app_pid",
-                &format_args!("{}", self.record_app_pid().bits()),
-            )
+            .field("record_app_pid", &self.record_app_pid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CPU_RECORD_PID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_cpu_record_pid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_CPU_RECORD_PID_SPEC;
 impl crate::RegisterSpec for APP_CPU_RECORD_PID_SPEC {
diff --git a/esp32/src/dport/app_cpu_record_status.rs b/esp32/src/dport/app_cpu_record_status.rs
index 7001f94910..ac104786b4 100644
--- a/esp32/src/dport/app_cpu_record_status.rs
+++ b/esp32/src/dport/app_cpu_record_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_CPU_RECORD_STATUS")
-            .field(
-                "app_cpu_recording",
-                &format_args!("{}", self.app_cpu_recording().bit()),
-            )
+            .field("app_cpu_recording", &self.app_cpu_recording())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_CPU_RECORD_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_cpu_record_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_CPU_RECORD_STATUS_SPEC;
 impl crate::RegisterSpec for APP_CPU_RECORD_STATUS_SPEC {
diff --git a/esp32/src/dport/app_dcache_dbug0.rs b/esp32/src/dport/app_dcache_dbug0.rs
index 199bf9b833..deb328f6ea 100644
--- a/esp32/src/dport/app_dcache_dbug0.rs
+++ b/esp32/src/dport/app_dcache_dbug0.rs
@@ -73,45 +73,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_DCACHE_DBUG0")
-            .field(
-                "app_slave_wdata",
-                &format_args!("{}", self.app_slave_wdata().bit()),
-            )
-            .field(
-                "app_cache_mmu_ia",
-                &format_args!("{}", self.app_cache_mmu_ia().bit()),
-            )
-            .field(
-                "app_cache_ia",
-                &format_args!("{}", self.app_cache_ia().bits()),
-            )
-            .field(
-                "app_cache_state",
-                &format_args!("{}", self.app_cache_state().bits()),
-            )
-            .field(
-                "app_wr_bak_to_read",
-                &format_args!("{}", self.app_wr_bak_to_read().bit()),
-            )
-            .field("app_tx_end", &format_args!("{}", self.app_tx_end().bit()))
-            .field(
-                "app_slave_wr",
-                &format_args!("{}", self.app_slave_wr().bit()),
-            )
-            .field(
-                "app_slave_wdata_v",
-                &format_args!("{}", self.app_slave_wdata_v().bit()),
-            )
-            .field("app_rx_end", &format_args!("{}", self.app_rx_end().bit()))
+            .field("app_slave_wdata", &self.app_slave_wdata())
+            .field("app_cache_mmu_ia", &self.app_cache_mmu_ia())
+            .field("app_cache_ia", &self.app_cache_ia())
+            .field("app_cache_state", &self.app_cache_state())
+            .field("app_wr_bak_to_read", &self.app_wr_bak_to_read())
+            .field("app_tx_end", &self.app_tx_end())
+            .field("app_slave_wr", &self.app_slave_wr())
+            .field("app_slave_wdata_v", &self.app_slave_wdata_v())
+            .field("app_rx_end", &self.app_rx_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_DCACHE_DBUG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_dcache_dbug1.rs b/esp32/src/dport/app_dcache_dbug1.rs
index 92f025f7d8..3349f78d08 100644
--- a/esp32/src/dport/app_dcache_dbug1.rs
+++ b/esp32/src/dport/app_dcache_dbug1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_DCACHE_DBUG1")
-            .field(
-                "app_ctag_ram_rdata",
-                &format_args!("{}", self.app_ctag_ram_rdata().bits()),
-            )
+            .field("app_ctag_ram_rdata", &self.app_ctag_ram_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_DCACHE_DBUG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_dcache_dbug1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_DCACHE_DBUG1_SPEC;
 impl crate::RegisterSpec for APP_DCACHE_DBUG1_SPEC {
diff --git a/esp32/src/dport/app_dcache_dbug2.rs b/esp32/src/dport/app_dcache_dbug2.rs
index a147181417..c647ffb00d 100644
--- a/esp32/src/dport/app_dcache_dbug2.rs
+++ b/esp32/src/dport/app_dcache_dbug2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_DCACHE_DBUG2")
-            .field(
-                "app_cache_vaddr",
-                &format_args!("{}", self.app_cache_vaddr().bits()),
-            )
+            .field("app_cache_vaddr", &self.app_cache_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_DCACHE_DBUG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_dcache_dbug2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_DCACHE_DBUG2_SPEC;
 impl crate::RegisterSpec for APP_DCACHE_DBUG2_SPEC {
diff --git a/esp32/src/dport/app_dcache_dbug3.rs b/esp32/src/dport/app_dcache_dbug3.rs
index d63cb1de38..6ca4a5202f 100644
--- a/esp32/src/dport/app_dcache_dbug3.rs
+++ b/esp32/src/dport/app_dcache_dbug3.rs
@@ -83,51 +83,42 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_DCACHE_DBUG3")
-            .field(
-                "app_mmu_rdata",
-                &format_args!("{}", self.app_mmu_rdata().bits()),
-            )
+            .field("app_mmu_rdata", &self.app_mmu_rdata())
             .field(
                 "app_cpu_disabled_cache_ia",
-                &format_args!("{}", self.app_cpu_disabled_cache_ia().bits()),
+                &self.app_cpu_disabled_cache_ia(),
             )
             .field(
                 "app_cpu_disabled_cache_ia_opposite",
-                &format_args!("{}", self.app_cpu_disabled_cache_ia_opposite().bit()),
+                &self.app_cpu_disabled_cache_ia_opposite(),
             )
             .field(
                 "app_cpu_disabled_cache_ia_dram1",
-                &format_args!("{}", self.app_cpu_disabled_cache_ia_dram1().bit()),
+                &self.app_cpu_disabled_cache_ia_dram1(),
             )
             .field(
                 "app_cpu_disabled_cache_ia_irom0",
-                &format_args!("{}", self.app_cpu_disabled_cache_ia_irom0().bit()),
+                &self.app_cpu_disabled_cache_ia_irom0(),
             )
             .field(
                 "app_cpu_disabled_cache_ia_iram1",
-                &format_args!("{}", self.app_cpu_disabled_cache_ia_iram1().bit()),
+                &self.app_cpu_disabled_cache_ia_iram1(),
             )
             .field(
                 "app_cpu_disabled_cache_ia_iram0",
-                &format_args!("{}", self.app_cpu_disabled_cache_ia_iram0().bit()),
+                &self.app_cpu_disabled_cache_ia_iram0(),
             )
             .field(
                 "app_cpu_disabled_cache_ia_drom0",
-                &format_args!("{}", self.app_cpu_disabled_cache_ia_drom0().bit()),
+                &self.app_cpu_disabled_cache_ia_drom0(),
             )
             .field(
                 "app_cache_iram0_pid_error",
-                &format_args!("{}", self.app_cache_iram0_pid_error().bit()),
+                &self.app_cache_iram0_pid_error(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_DCACHE_DBUG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_dcache_dbug4.rs b/esp32/src/dport/app_dcache_dbug4.rs
index 36df9c6312..7994aff50d 100644
--- a/esp32/src/dport/app_dcache_dbug4.rs
+++ b/esp32/src/dport/app_dcache_dbug4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_DCACHE_DBUG4")
-            .field(
-                "app_dram1addr0_ia",
-                &format_args!("{}", self.app_dram1addr0_ia().bits()),
-            )
+            .field("app_dram1addr0_ia", &self.app_dram1addr0_ia())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_DCACHE_DBUG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_dcache_dbug4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_DCACHE_DBUG4_SPEC;
 impl crate::RegisterSpec for APP_DCACHE_DBUG4_SPEC {
diff --git a/esp32/src/dport/app_dcache_dbug5.rs b/esp32/src/dport/app_dcache_dbug5.rs
index b2dd80dac9..e7b2216720 100644
--- a/esp32/src/dport/app_dcache_dbug5.rs
+++ b/esp32/src/dport/app_dcache_dbug5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_DCACHE_DBUG5")
-            .field(
-                "app_drom0addr0_ia",
-                &format_args!("{}", self.app_drom0addr0_ia().bits()),
-            )
+            .field("app_drom0addr0_ia", &self.app_drom0addr0_ia())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_DCACHE_DBUG5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_dcache_dbug5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_DCACHE_DBUG5_SPEC;
 impl crate::RegisterSpec for APP_DCACHE_DBUG5_SPEC {
diff --git a/esp32/src/dport/app_dcache_dbug6.rs b/esp32/src/dport/app_dcache_dbug6.rs
index faf99dd9a1..5f1d04c620 100644
--- a/esp32/src/dport/app_dcache_dbug6.rs
+++ b/esp32/src/dport/app_dcache_dbug6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_DCACHE_DBUG6")
-            .field(
-                "app_iram0addr_ia",
-                &format_args!("{}", self.app_iram0addr_ia().bits()),
-            )
+            .field("app_iram0addr_ia", &self.app_iram0addr_ia())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_DCACHE_DBUG6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_dcache_dbug6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_DCACHE_DBUG6_SPEC;
 impl crate::RegisterSpec for APP_DCACHE_DBUG6_SPEC {
diff --git a/esp32/src/dport/app_dcache_dbug7.rs b/esp32/src/dport/app_dcache_dbug7.rs
index a66c0637f5..f7ba7f9ec7 100644
--- a/esp32/src/dport/app_dcache_dbug7.rs
+++ b/esp32/src/dport/app_dcache_dbug7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_DCACHE_DBUG7")
-            .field(
-                "app_iram1addr_ia",
-                &format_args!("{}", self.app_iram1addr_ia().bits()),
-            )
+            .field("app_iram1addr_ia", &self.app_iram1addr_ia())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_DCACHE_DBUG7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_dcache_dbug7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_DCACHE_DBUG7_SPEC;
 impl crate::RegisterSpec for APP_DCACHE_DBUG7_SPEC {
diff --git a/esp32/src/dport/app_dcache_dbug8.rs b/esp32/src/dport/app_dcache_dbug8.rs
index 15755a64f3..e757c63013 100644
--- a/esp32/src/dport/app_dcache_dbug8.rs
+++ b/esp32/src/dport/app_dcache_dbug8.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_DCACHE_DBUG8")
-            .field(
-                "app_irom0addr_ia",
-                &format_args!("{}", self.app_irom0addr_ia().bits()),
-            )
+            .field("app_irom0addr_ia", &self.app_irom0addr_ia())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_DCACHE_DBUG8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_dcache_dbug8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_DCACHE_DBUG8_SPEC;
 impl crate::RegisterSpec for APP_DCACHE_DBUG8_SPEC {
diff --git a/esp32/src/dport/app_dcache_dbug9.rs b/esp32/src/dport/app_dcache_dbug9.rs
index feb0f7c6e5..a4c83243d9 100644
--- a/esp32/src/dport/app_dcache_dbug9.rs
+++ b/esp32/src/dport/app_dcache_dbug9.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_DCACHE_DBUG9")
-            .field(
-                "app_opsdramaddr_ia",
-                &format_args!("{}", self.app_opsdramaddr_ia().bits()),
-            )
+            .field("app_opsdramaddr_ia", &self.app_opsdramaddr_ia())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_DCACHE_DBUG9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_dcache_dbug9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_DCACHE_DBUG9_SPEC;
 impl crate::RegisterSpec for APP_DCACHE_DBUG9_SPEC {
diff --git a/esp32/src/dport/app_dport_apb_mask0.rs b/esp32/src/dport/app_dport_apb_mask0.rs
index c1021974ec..98e957a158 100644
--- a/esp32/src/dport/app_dport_apb_mask0.rs
+++ b/esp32/src/dport/app_dport_apb_mask0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_DPORT_APB_MASK0")
-            .field(
-                "appdport_apb_mask0",
-                &format_args!("{}", self.appdport_apb_mask0().bits()),
-            )
+            .field("appdport_apb_mask0", &self.appdport_apb_mask0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_DPORT_APB_MASK0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_dport_apb_mask1.rs b/esp32/src/dport/app_dport_apb_mask1.rs
index fcf2c2be50..3d991cf7b6 100644
--- a/esp32/src/dport/app_dport_apb_mask1.rs
+++ b/esp32/src/dport/app_dport_apb_mask1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_DPORT_APB_MASK1")
-            .field(
-                "appdport_apb_mask1",
-                &format_args!("{}", self.appdport_apb_mask1().bits()),
-            )
+            .field("appdport_apb_mask1", &self.appdport_apb_mask1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_DPORT_APB_MASK1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_efuse_int_map.rs b/esp32/src/dport/app_efuse_int_map.rs
index 5863cc12ec..1db12ab6da 100644
--- a/esp32/src/dport/app_efuse_int_map.rs
+++ b/esp32/src/dport/app_efuse_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_EFUSE_INT_MAP")
-            .field(
-                "app_efuse_int_map",
-                &format_args!("{}", self.app_efuse_int_map().bits()),
-            )
+            .field("app_efuse_int_map", &self.app_efuse_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_EFUSE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_emac_int_map.rs b/esp32/src/dport/app_emac_int_map.rs
index 5c8662bfa1..0b2ff39ea9 100644
--- a/esp32/src/dport/app_emac_int_map.rs
+++ b/esp32/src/dport/app_emac_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_EMAC_INT_MAP")
-            .field(
-                "app_emac_int_map",
-                &format_args!("{}", self.app_emac_int_map().bits()),
-            )
+            .field("app_emac_int_map", &self.app_emac_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_EMAC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_gpio_interrupt_map.rs b/esp32/src/dport/app_gpio_interrupt_map.rs
index 1a908f7d46..994806bbc3 100644
--- a/esp32/src/dport/app_gpio_interrupt_map.rs
+++ b/esp32/src/dport/app_gpio_interrupt_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APP_GPIO_INTERRUPT_MAP")
             .field(
                 "app_gpio_interrupt_app_map",
-                &format_args!("{}", self.app_gpio_interrupt_app_map().bits()),
+                &self.app_gpio_interrupt_app_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_GPIO_INTERRUPT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_gpio_interrupt_nmi_map.rs b/esp32/src/dport/app_gpio_interrupt_nmi_map.rs
index 8a0510afbc..49a6535f62 100644
--- a/esp32/src/dport/app_gpio_interrupt_nmi_map.rs
+++ b/esp32/src/dport/app_gpio_interrupt_nmi_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APP_GPIO_INTERRUPT_NMI_MAP")
             .field(
                 "app_gpio_interrupt_app_nmi_map",
-                &format_args!("{}", self.app_gpio_interrupt_app_nmi_map().bits()),
+                &self.app_gpio_interrupt_app_nmi_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_GPIO_INTERRUPT_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_i2c_ext0_intr_map.rs b/esp32/src/dport/app_i2c_ext0_intr_map.rs
index b5bde30982..60869e83e1 100644
--- a/esp32/src/dport/app_i2c_ext0_intr_map.rs
+++ b/esp32/src/dport/app_i2c_ext0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_I2C_EXT0_INTR_MAP")
-            .field(
-                "app_i2c_ext0_intr_map",
-                &format_args!("{}", self.app_i2c_ext0_intr_map().bits()),
-            )
+            .field("app_i2c_ext0_intr_map", &self.app_i2c_ext0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_I2C_EXT0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_i2c_ext1_intr_map.rs b/esp32/src/dport/app_i2c_ext1_intr_map.rs
index 12792af426..a921485206 100644
--- a/esp32/src/dport/app_i2c_ext1_intr_map.rs
+++ b/esp32/src/dport/app_i2c_ext1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_I2C_EXT1_INTR_MAP")
-            .field(
-                "app_i2c_ext1_intr_map",
-                &format_args!("{}", self.app_i2c_ext1_intr_map().bits()),
-            )
+            .field("app_i2c_ext1_intr_map", &self.app_i2c_ext1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_I2C_EXT1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_i2s0_int_map.rs b/esp32/src/dport/app_i2s0_int_map.rs
index 5b0c11f6da..8459bccd7d 100644
--- a/esp32/src/dport/app_i2s0_int_map.rs
+++ b/esp32/src/dport/app_i2s0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_I2S0_INT_MAP")
-            .field(
-                "app_i2s0_int_map",
-                &format_args!("{}", self.app_i2s0_int_map().bits()),
-            )
+            .field("app_i2s0_int_map", &self.app_i2s0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_I2S0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_i2s1_int_map.rs b/esp32/src/dport/app_i2s1_int_map.rs
index 969d6ef10b..2482d2352c 100644
--- a/esp32/src/dport/app_i2s1_int_map.rs
+++ b/esp32/src/dport/app_i2s1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_I2S1_INT_MAP")
-            .field(
-                "app_i2s1_int_map",
-                &format_args!("{}", self.app_i2s1_int_map().bits()),
-            )
+            .field("app_i2s1_int_map", &self.app_i2s1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_I2S1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_intr_status_0.rs b/esp32/src/dport/app_intr_status_0.rs
index 268fc2135c..6a0692e966 100644
--- a/esp32/src/dport/app_intr_status_0.rs
+++ b/esp32/src/dport/app_intr_status_0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_INTR_STATUS_0")
-            .field(
-                "app_intr_status_0",
-                &format_args!("{}", self.app_intr_status_0().bits()),
-            )
+            .field("app_intr_status_0", &self.app_intr_status_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_INTR_STATUS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_intr_status_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_INTR_STATUS_0_SPEC;
 impl crate::RegisterSpec for APP_INTR_STATUS_0_SPEC {
diff --git a/esp32/src/dport/app_intr_status_1.rs b/esp32/src/dport/app_intr_status_1.rs
index 299b980060..38c7e4228d 100644
--- a/esp32/src/dport/app_intr_status_1.rs
+++ b/esp32/src/dport/app_intr_status_1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_INTR_STATUS_1")
-            .field(
-                "app_intr_status_1",
-                &format_args!("{}", self.app_intr_status_1().bits()),
-            )
+            .field("app_intr_status_1", &self.app_intr_status_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_INTR_STATUS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_intr_status_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_INTR_STATUS_1_SPEC;
 impl crate::RegisterSpec for APP_INTR_STATUS_1_SPEC {
diff --git a/esp32/src/dport/app_intr_status_2.rs b/esp32/src/dport/app_intr_status_2.rs
index 16c66f937b..cf2d2910b9 100644
--- a/esp32/src/dport/app_intr_status_2.rs
+++ b/esp32/src/dport/app_intr_status_2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_INTR_STATUS_2")
-            .field(
-                "app_intr_status_2",
-                &format_args!("{}", self.app_intr_status_2().bits()),
-            )
+            .field("app_intr_status_2", &self.app_intr_status_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_INTR_STATUS_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_intr_status_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_INTR_STATUS_2_SPEC;
 impl crate::RegisterSpec for APP_INTR_STATUS_2_SPEC {
diff --git a/esp32/src/dport/app_intrusion_ctrl.rs b/esp32/src/dport/app_intrusion_ctrl.rs
index 78cd8ac8f6..92381134fc 100644
--- a/esp32/src/dport/app_intrusion_ctrl.rs
+++ b/esp32/src/dport/app_intrusion_ctrl.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APP_INTRUSION_CTRL")
             .field(
                 "app_intrusion_record_reset_n",
-                &format_args!("{}", self.app_intrusion_record_reset_n().bit()),
+                &self.app_intrusion_record_reset_n(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_INTRUSION_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_intrusion_status.rs b/esp32/src/dport/app_intrusion_status.rs
index 4e4939c306..ee977a3cde 100644
--- a/esp32/src/dport/app_intrusion_status.rs
+++ b/esp32/src/dport/app_intrusion_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_INTRUSION_STATUS")
-            .field(
-                "app_intrusion_record",
-                &format_args!("{}", self.app_intrusion_record().bits()),
-            )
+            .field("app_intrusion_record", &self.app_intrusion_record())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_INTRUSION_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_intrusion_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_INTRUSION_STATUS_SPEC;
 impl crate::RegisterSpec for APP_INTRUSION_STATUS_SPEC {
diff --git a/esp32/src/dport/app_ledc_int_map.rs b/esp32/src/dport/app_ledc_int_map.rs
index 7f09b77df2..02afffec7f 100644
--- a/esp32/src/dport/app_ledc_int_map.rs
+++ b/esp32/src/dport/app_ledc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_LEDC_INT_MAP")
-            .field(
-                "app_ledc_int_map",
-                &format_args!("{}", self.app_ledc_int_map().bits()),
-            )
+            .field("app_ledc_int_map", &self.app_ledc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_LEDC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_mac_intr_map.rs b/esp32/src/dport/app_mac_intr_map.rs
index e0ad3ec7d4..9c22bb498d 100644
--- a/esp32/src/dport/app_mac_intr_map.rs
+++ b/esp32/src/dport/app_mac_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_MAC_INTR_MAP")
-            .field(
-                "app_mac_intr_map",
-                &format_args!("{}", self.app_mac_intr_map().bits()),
-            )
+            .field("app_mac_intr_map", &self.app_mac_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_MAC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_mac_nmi_map.rs b/esp32/src/dport/app_mac_nmi_map.rs
index bbdd991f02..6b88035f8b 100644
--- a/esp32/src/dport/app_mac_nmi_map.rs
+++ b/esp32/src/dport/app_mac_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_MAC_NMI_MAP")
-            .field(
-                "app_mac_nmi_map",
-                &format_args!("{}", self.app_mac_nmi_map().bits()),
-            )
+            .field("app_mac_nmi_map", &self.app_mac_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_MAC_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_mmu_ia_int_map.rs b/esp32/src/dport/app_mmu_ia_int_map.rs
index 722dc0f08d..7caac81b23 100644
--- a/esp32/src/dport/app_mmu_ia_int_map.rs
+++ b/esp32/src/dport/app_mmu_ia_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_MMU_IA_INT_MAP")
-            .field(
-                "app_mmu_ia_int_map",
-                &format_args!("{}", self.app_mmu_ia_int_map().bits()),
-            )
+            .field("app_mmu_ia_int_map", &self.app_mmu_ia_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_MMU_IA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_mpu_ia_int_map.rs b/esp32/src/dport/app_mpu_ia_int_map.rs
index 5b1a4a896c..6299662290 100644
--- a/esp32/src/dport/app_mpu_ia_int_map.rs
+++ b/esp32/src/dport/app_mpu_ia_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_MPU_IA_INT_MAP")
-            .field(
-                "app_mpu_ia_int_map",
-                &format_args!("{}", self.app_mpu_ia_int_map().bits()),
-            )
+            .field("app_mpu_ia_int_map", &self.app_mpu_ia_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_MPU_IA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_pcnt_intr_map.rs b/esp32/src/dport/app_pcnt_intr_map.rs
index 0a02fd9fb1..969ee88d6d 100644
--- a/esp32/src/dport/app_pcnt_intr_map.rs
+++ b/esp32/src/dport/app_pcnt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_PCNT_INTR_MAP")
-            .field(
-                "app_pcnt_intr_map",
-                &format_args!("{}", self.app_pcnt_intr_map().bits()),
-            )
+            .field("app_pcnt_intr_map", &self.app_pcnt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_PCNT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_pwm0_intr_map.rs b/esp32/src/dport/app_pwm0_intr_map.rs
index 384c0cd2cf..60c7d4ef99 100644
--- a/esp32/src/dport/app_pwm0_intr_map.rs
+++ b/esp32/src/dport/app_pwm0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_PWM0_INTR_MAP")
-            .field(
-                "app_pwm0_intr_map",
-                &format_args!("{}", self.app_pwm0_intr_map().bits()),
-            )
+            .field("app_pwm0_intr_map", &self.app_pwm0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_PWM0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_pwm1_intr_map.rs b/esp32/src/dport/app_pwm1_intr_map.rs
index 992ef4be81..41bf14491d 100644
--- a/esp32/src/dport/app_pwm1_intr_map.rs
+++ b/esp32/src/dport/app_pwm1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_PWM1_INTR_MAP")
-            .field(
-                "app_pwm1_intr_map",
-                &format_args!("{}", self.app_pwm1_intr_map().bits()),
-            )
+            .field("app_pwm1_intr_map", &self.app_pwm1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_PWM1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_pwm2_intr_map.rs b/esp32/src/dport/app_pwm2_intr_map.rs
index 13fd4d1811..8041b4bf35 100644
--- a/esp32/src/dport/app_pwm2_intr_map.rs
+++ b/esp32/src/dport/app_pwm2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_PWM2_INTR_MAP")
-            .field(
-                "app_pwm2_intr_map",
-                &format_args!("{}", self.app_pwm2_intr_map().bits()),
-            )
+            .field("app_pwm2_intr_map", &self.app_pwm2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_PWM2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_pwm3_intr_map.rs b/esp32/src/dport/app_pwm3_intr_map.rs
index b64602fa49..2d169fc004 100644
--- a/esp32/src/dport/app_pwm3_intr_map.rs
+++ b/esp32/src/dport/app_pwm3_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_PWM3_INTR_MAP")
-            .field(
-                "app_pwm3_intr_map",
-                &format_args!("{}", self.app_pwm3_intr_map().bits()),
-            )
+            .field("app_pwm3_intr_map", &self.app_pwm3_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_PWM3_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_rmt_intr_map.rs b/esp32/src/dport/app_rmt_intr_map.rs
index 12ffa4fee3..9b30b6af5e 100644
--- a/esp32/src/dport/app_rmt_intr_map.rs
+++ b/esp32/src/dport/app_rmt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_RMT_INTR_MAP")
-            .field(
-                "app_rmt_intr_map",
-                &format_args!("{}", self.app_rmt_intr_map().bits()),
-            )
+            .field("app_rmt_intr_map", &self.app_rmt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_RMT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_rsa_intr_map.rs b/esp32/src/dport/app_rsa_intr_map.rs
index fc8b5693c8..1770e080c4 100644
--- a/esp32/src/dport/app_rsa_intr_map.rs
+++ b/esp32/src/dport/app_rsa_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_RSA_INTR_MAP")
-            .field(
-                "app_rsa_intr_map",
-                &format_args!("{}", self.app_rsa_intr_map().bits()),
-            )
+            .field("app_rsa_intr_map", &self.app_rsa_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_RSA_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_rtc_core_intr_map.rs b/esp32/src/dport/app_rtc_core_intr_map.rs
index 43b7de2ecf..e62a75b7e7 100644
--- a/esp32/src/dport/app_rtc_core_intr_map.rs
+++ b/esp32/src/dport/app_rtc_core_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_RTC_CORE_INTR_MAP")
-            .field(
-                "app_rtc_core_intr_map",
-                &format_args!("{}", self.app_rtc_core_intr_map().bits()),
-            )
+            .field("app_rtc_core_intr_map", &self.app_rtc_core_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_RTC_CORE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_rwble_irq_map.rs b/esp32/src/dport/app_rwble_irq_map.rs
index 4639d960b9..f26a679436 100644
--- a/esp32/src/dport/app_rwble_irq_map.rs
+++ b/esp32/src/dport/app_rwble_irq_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_RWBLE_IRQ_MAP")
-            .field(
-                "app_rwble_irq_map",
-                &format_args!("{}", self.app_rwble_irq_map().bits()),
-            )
+            .field("app_rwble_irq_map", &self.app_rwble_irq_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_RWBLE_IRQ_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_rwble_nmi_map.rs b/esp32/src/dport/app_rwble_nmi_map.rs
index f29188c64e..1a350ce218 100644
--- a/esp32/src/dport/app_rwble_nmi_map.rs
+++ b/esp32/src/dport/app_rwble_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_RWBLE_NMI_MAP")
-            .field(
-                "app_rwble_nmi_map",
-                &format_args!("{}", self.app_rwble_nmi_map().bits()),
-            )
+            .field("app_rwble_nmi_map", &self.app_rwble_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_RWBLE_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_rwbt_irq_map.rs b/esp32/src/dport/app_rwbt_irq_map.rs
index 786ad7492b..13c1031379 100644
--- a/esp32/src/dport/app_rwbt_irq_map.rs
+++ b/esp32/src/dport/app_rwbt_irq_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_RWBT_IRQ_MAP")
-            .field(
-                "app_rwbt_irq_map",
-                &format_args!("{}", self.app_rwbt_irq_map().bits()),
-            )
+            .field("app_rwbt_irq_map", &self.app_rwbt_irq_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_RWBT_IRQ_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_rwbt_nmi_map.rs b/esp32/src/dport/app_rwbt_nmi_map.rs
index a1dd8c8349..492a692074 100644
--- a/esp32/src/dport/app_rwbt_nmi_map.rs
+++ b/esp32/src/dport/app_rwbt_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_RWBT_NMI_MAP")
-            .field(
-                "app_rwbt_nmi_map",
-                &format_args!("{}", self.app_rwbt_nmi_map().bits()),
-            )
+            .field("app_rwbt_nmi_map", &self.app_rwbt_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_RWBT_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_sdio_host_interrupt_map.rs b/esp32/src/dport/app_sdio_host_interrupt_map.rs
index 90bbd78f6a..11bff8e2ef 100644
--- a/esp32/src/dport/app_sdio_host_interrupt_map.rs
+++ b/esp32/src/dport/app_sdio_host_interrupt_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APP_SDIO_HOST_INTERRUPT_MAP")
             .field(
                 "app_sdio_host_interrupt_map",
-                &format_args!("{}", self.app_sdio_host_interrupt_map().bits()),
+                &self.app_sdio_host_interrupt_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_SDIO_HOST_INTERRUPT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_slc0_intr_map.rs b/esp32/src/dport/app_slc0_intr_map.rs
index 1adde4534d..1f6e036166 100644
--- a/esp32/src/dport/app_slc0_intr_map.rs
+++ b/esp32/src/dport/app_slc0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_SLC0_INTR_MAP")
-            .field(
-                "app_slc0_intr_map",
-                &format_args!("{}", self.app_slc0_intr_map().bits()),
-            )
+            .field("app_slc0_intr_map", &self.app_slc0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_SLC0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_slc1_intr_map.rs b/esp32/src/dport/app_slc1_intr_map.rs
index 5b3570ff6a..23eb0cb55a 100644
--- a/esp32/src/dport/app_slc1_intr_map.rs
+++ b/esp32/src/dport/app_slc1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_SLC1_INTR_MAP")
-            .field(
-                "app_slc1_intr_map",
-                &format_args!("{}", self.app_slc1_intr_map().bits()),
-            )
+            .field("app_slc1_intr_map", &self.app_slc1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_SLC1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_spi1_dma_int_map.rs b/esp32/src/dport/app_spi1_dma_int_map.rs
index 48eccef17f..84c31e042f 100644
--- a/esp32/src/dport/app_spi1_dma_int_map.rs
+++ b/esp32/src/dport/app_spi1_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_SPI1_DMA_INT_MAP")
-            .field(
-                "app_spi1_dma_int_map",
-                &format_args!("{}", self.app_spi1_dma_int_map().bits()),
-            )
+            .field("app_spi1_dma_int_map", &self.app_spi1_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_SPI1_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_spi2_dma_int_map.rs b/esp32/src/dport/app_spi2_dma_int_map.rs
index 6eaa5106bd..da851123ee 100644
--- a/esp32/src/dport/app_spi2_dma_int_map.rs
+++ b/esp32/src/dport/app_spi2_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_SPI2_DMA_INT_MAP")
-            .field(
-                "app_spi2_dma_int_map",
-                &format_args!("{}", self.app_spi2_dma_int_map().bits()),
-            )
+            .field("app_spi2_dma_int_map", &self.app_spi2_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_SPI2_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_spi3_dma_int_map.rs b/esp32/src/dport/app_spi3_dma_int_map.rs
index b4a7b2cd4b..8803d465b8 100644
--- a/esp32/src/dport/app_spi3_dma_int_map.rs
+++ b/esp32/src/dport/app_spi3_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_SPI3_DMA_INT_MAP")
-            .field(
-                "app_spi3_dma_int_map",
-                &format_args!("{}", self.app_spi3_dma_int_map().bits()),
-            )
+            .field("app_spi3_dma_int_map", &self.app_spi3_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_SPI3_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_spi_intr_0_map.rs b/esp32/src/dport/app_spi_intr_0_map.rs
index 652761763c..dc747b9f6c 100644
--- a/esp32/src/dport/app_spi_intr_0_map.rs
+++ b/esp32/src/dport/app_spi_intr_0_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_SPI_INTR_0_MAP")
-            .field(
-                "app_spi_intr_0_map",
-                &format_args!("{}", self.app_spi_intr_0_map().bits()),
-            )
+            .field("app_spi_intr_0_map", &self.app_spi_intr_0_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_SPI_INTR_0_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_spi_intr_1_map.rs b/esp32/src/dport/app_spi_intr_1_map.rs
index 1591430ea0..56ad745057 100644
--- a/esp32/src/dport/app_spi_intr_1_map.rs
+++ b/esp32/src/dport/app_spi_intr_1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_SPI_INTR_1_MAP")
-            .field(
-                "app_spi_intr_1_map",
-                &format_args!("{}", self.app_spi_intr_1_map().bits()),
-            )
+            .field("app_spi_intr_1_map", &self.app_spi_intr_1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_SPI_INTR_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_spi_intr_2_map.rs b/esp32/src/dport/app_spi_intr_2_map.rs
index b38b92ba1e..5d0b6149fa 100644
--- a/esp32/src/dport/app_spi_intr_2_map.rs
+++ b/esp32/src/dport/app_spi_intr_2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_SPI_INTR_2_MAP")
-            .field(
-                "app_spi_intr_2_map",
-                &format_args!("{}", self.app_spi_intr_2_map().bits()),
-            )
+            .field("app_spi_intr_2_map", &self.app_spi_intr_2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_SPI_INTR_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_spi_intr_3_map.rs b/esp32/src/dport/app_spi_intr_3_map.rs
index 56cb2c22c2..3105abd6a2 100644
--- a/esp32/src/dport/app_spi_intr_3_map.rs
+++ b/esp32/src/dport/app_spi_intr_3_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_SPI_INTR_3_MAP")
-            .field(
-                "app_spi_intr_3_map",
-                &format_args!("{}", self.app_spi_intr_3_map().bits()),
-            )
+            .field("app_spi_intr_3_map", &self.app_spi_intr_3_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_SPI_INTR_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg1_lact_edge_int_map.rs b/esp32/src/dport/app_tg1_lact_edge_int_map.rs
index 1cfdbcc863..577ccb995c 100644
--- a/esp32/src/dport/app_tg1_lact_edge_int_map.rs
+++ b/esp32/src/dport/app_tg1_lact_edge_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APP_TG1_LACT_EDGE_INT_MAP")
             .field(
                 "app_tg1_lact_edge_int_map",
-                &format_args!("{}", self.app_tg1_lact_edge_int_map().bits()),
+                &self.app_tg1_lact_edge_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG1_LACT_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg1_lact_level_int_map.rs b/esp32/src/dport/app_tg1_lact_level_int_map.rs
index 47826c1399..52708ffdab 100644
--- a/esp32/src/dport/app_tg1_lact_level_int_map.rs
+++ b/esp32/src/dport/app_tg1_lact_level_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APP_TG1_LACT_LEVEL_INT_MAP")
             .field(
                 "app_tg1_lact_level_int_map",
-                &format_args!("{}", self.app_tg1_lact_level_int_map().bits()),
+                &self.app_tg1_lact_level_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG1_LACT_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg1_t0_edge_int_map.rs b/esp32/src/dport/app_tg1_t0_edge_int_map.rs
index 3f04ddc190..8274ddf19b 100644
--- a/esp32/src/dport/app_tg1_t0_edge_int_map.rs
+++ b/esp32/src/dport/app_tg1_t0_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_TG1_T0_EDGE_INT_MAP")
-            .field(
-                "app_tg1_t0_edge_int_map",
-                &format_args!("{}", self.app_tg1_t0_edge_int_map().bits()),
-            )
+            .field("app_tg1_t0_edge_int_map", &self.app_tg1_t0_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG1_T0_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg1_t0_level_int_map.rs b/esp32/src/dport/app_tg1_t0_level_int_map.rs
index 1a47497dad..bcf1227206 100644
--- a/esp32/src/dport/app_tg1_t0_level_int_map.rs
+++ b/esp32/src/dport/app_tg1_t0_level_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_TG1_T0_LEVEL_INT_MAP")
-            .field(
-                "app_tg1_t0_level_int_map",
-                &format_args!("{}", self.app_tg1_t0_level_int_map().bits()),
-            )
+            .field("app_tg1_t0_level_int_map", &self.app_tg1_t0_level_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG1_T0_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg1_t1_edge_int_map.rs b/esp32/src/dport/app_tg1_t1_edge_int_map.rs
index 748c031cb0..dae126e4d9 100644
--- a/esp32/src/dport/app_tg1_t1_edge_int_map.rs
+++ b/esp32/src/dport/app_tg1_t1_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_TG1_T1_EDGE_INT_MAP")
-            .field(
-                "app_tg1_t1_edge_int_map",
-                &format_args!("{}", self.app_tg1_t1_edge_int_map().bits()),
-            )
+            .field("app_tg1_t1_edge_int_map", &self.app_tg1_t1_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG1_T1_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg1_t1_level_int_map.rs b/esp32/src/dport/app_tg1_t1_level_int_map.rs
index 931eb3beb3..90ccade5b5 100644
--- a/esp32/src/dport/app_tg1_t1_level_int_map.rs
+++ b/esp32/src/dport/app_tg1_t1_level_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_TG1_T1_LEVEL_INT_MAP")
-            .field(
-                "app_tg1_t1_level_int_map",
-                &format_args!("{}", self.app_tg1_t1_level_int_map().bits()),
-            )
+            .field("app_tg1_t1_level_int_map", &self.app_tg1_t1_level_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG1_T1_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg1_wdt_edge_int_map.rs b/esp32/src/dport/app_tg1_wdt_edge_int_map.rs
index 4d2f784d3f..549c48797e 100644
--- a/esp32/src/dport/app_tg1_wdt_edge_int_map.rs
+++ b/esp32/src/dport/app_tg1_wdt_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_TG1_WDT_EDGE_INT_MAP")
-            .field(
-                "app_tg1_wdt_edge_int_map",
-                &format_args!("{}", self.app_tg1_wdt_edge_int_map().bits()),
-            )
+            .field("app_tg1_wdt_edge_int_map", &self.app_tg1_wdt_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG1_WDT_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg1_wdt_level_int_map.rs b/esp32/src/dport/app_tg1_wdt_level_int_map.rs
index d731b3fe25..10df8a5a65 100644
--- a/esp32/src/dport/app_tg1_wdt_level_int_map.rs
+++ b/esp32/src/dport/app_tg1_wdt_level_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APP_TG1_WDT_LEVEL_INT_MAP")
             .field(
                 "app_tg1_wdt_level_int_map",
-                &format_args!("{}", self.app_tg1_wdt_level_int_map().bits()),
+                &self.app_tg1_wdt_level_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG1_WDT_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg_lact_edge_int_map.rs b/esp32/src/dport/app_tg_lact_edge_int_map.rs
index 76b091f399..e7bed3e6d1 100644
--- a/esp32/src/dport/app_tg_lact_edge_int_map.rs
+++ b/esp32/src/dport/app_tg_lact_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_TG_LACT_EDGE_INT_MAP")
-            .field(
-                "app_tg_lact_edge_int_map",
-                &format_args!("{}", self.app_tg_lact_edge_int_map().bits()),
-            )
+            .field("app_tg_lact_edge_int_map", &self.app_tg_lact_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG_LACT_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg_lact_level_int_map.rs b/esp32/src/dport/app_tg_lact_level_int_map.rs
index 0721ddde7c..14439bdba8 100644
--- a/esp32/src/dport/app_tg_lact_level_int_map.rs
+++ b/esp32/src/dport/app_tg_lact_level_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APP_TG_LACT_LEVEL_INT_MAP")
             .field(
                 "app_tg_lact_level_int_map",
-                &format_args!("{}", self.app_tg_lact_level_int_map().bits()),
+                &self.app_tg_lact_level_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG_LACT_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg_t0_edge_int_map.rs b/esp32/src/dport/app_tg_t0_edge_int_map.rs
index 7797572743..880f006f8f 100644
--- a/esp32/src/dport/app_tg_t0_edge_int_map.rs
+++ b/esp32/src/dport/app_tg_t0_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_TG_T0_EDGE_INT_MAP")
-            .field(
-                "app_tg_t0_edge_int_map",
-                &format_args!("{}", self.app_tg_t0_edge_int_map().bits()),
-            )
+            .field("app_tg_t0_edge_int_map", &self.app_tg_t0_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG_T0_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg_t0_level_int_map.rs b/esp32/src/dport/app_tg_t0_level_int_map.rs
index 4edfd3b12b..498f142116 100644
--- a/esp32/src/dport/app_tg_t0_level_int_map.rs
+++ b/esp32/src/dport/app_tg_t0_level_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_TG_T0_LEVEL_INT_MAP")
-            .field(
-                "app_tg_t0_level_int_map",
-                &format_args!("{}", self.app_tg_t0_level_int_map().bits()),
-            )
+            .field("app_tg_t0_level_int_map", &self.app_tg_t0_level_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG_T0_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg_t1_edge_int_map.rs b/esp32/src/dport/app_tg_t1_edge_int_map.rs
index 5e450eb11a..ea6343aed4 100644
--- a/esp32/src/dport/app_tg_t1_edge_int_map.rs
+++ b/esp32/src/dport/app_tg_t1_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_TG_T1_EDGE_INT_MAP")
-            .field(
-                "app_tg_t1_edge_int_map",
-                &format_args!("{}", self.app_tg_t1_edge_int_map().bits()),
-            )
+            .field("app_tg_t1_edge_int_map", &self.app_tg_t1_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG_T1_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg_t1_level_int_map.rs b/esp32/src/dport/app_tg_t1_level_int_map.rs
index 78f16b7f34..85642dae66 100644
--- a/esp32/src/dport/app_tg_t1_level_int_map.rs
+++ b/esp32/src/dport/app_tg_t1_level_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_TG_T1_LEVEL_INT_MAP")
-            .field(
-                "app_tg_t1_level_int_map",
-                &format_args!("{}", self.app_tg_t1_level_int_map().bits()),
-            )
+            .field("app_tg_t1_level_int_map", &self.app_tg_t1_level_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG_T1_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg_wdt_edge_int_map.rs b/esp32/src/dport/app_tg_wdt_edge_int_map.rs
index 1fe62d9971..d5161e5440 100644
--- a/esp32/src/dport/app_tg_wdt_edge_int_map.rs
+++ b/esp32/src/dport/app_tg_wdt_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_TG_WDT_EDGE_INT_MAP")
-            .field(
-                "app_tg_wdt_edge_int_map",
-                &format_args!("{}", self.app_tg_wdt_edge_int_map().bits()),
-            )
+            .field("app_tg_wdt_edge_int_map", &self.app_tg_wdt_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG_WDT_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tg_wdt_level_int_map.rs b/esp32/src/dport/app_tg_wdt_level_int_map.rs
index 9ca206eda6..7f03967693 100644
--- a/esp32/src/dport/app_tg_wdt_level_int_map.rs
+++ b/esp32/src/dport/app_tg_wdt_level_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_TG_WDT_LEVEL_INT_MAP")
-            .field(
-                "app_tg_wdt_level_int_map",
-                &format_args!("{}", self.app_tg_wdt_level_int_map().bits()),
-            )
+            .field("app_tg_wdt_level_int_map", &self.app_tg_wdt_level_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TG_WDT_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_timer_int1_map.rs b/esp32/src/dport/app_timer_int1_map.rs
index b02081c9fb..78424cc259 100644
--- a/esp32/src/dport/app_timer_int1_map.rs
+++ b/esp32/src/dport/app_timer_int1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_TIMER_INT1_MAP")
-            .field(
-                "app_timer_int1_map",
-                &format_args!("{}", self.app_timer_int1_map().bits()),
-            )
+            .field("app_timer_int1_map", &self.app_timer_int1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TIMER_INT1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_timer_int2_map.rs b/esp32/src/dport/app_timer_int2_map.rs
index 8c5f3a7d84..be4a9974ea 100644
--- a/esp32/src/dport/app_timer_int2_map.rs
+++ b/esp32/src/dport/app_timer_int2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_TIMER_INT2_MAP")
-            .field(
-                "app_timer_int2_map",
-                &format_args!("{}", self.app_timer_int2_map().bits()),
-            )
+            .field("app_timer_int2_map", &self.app_timer_int2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TIMER_INT2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_tracemem_ena.rs b/esp32/src/dport/app_tracemem_ena.rs
index 3110b43fe3..8e881d67b3 100644
--- a/esp32/src/dport/app_tracemem_ena.rs
+++ b/esp32/src/dport/app_tracemem_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_TRACEMEM_ENA")
-            .field(
-                "app_tracemem_ena",
-                &format_args!("{}", self.app_tracemem_ena().bit()),
-            )
+            .field("app_tracemem_ena", &self.app_tracemem_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_TRACEMEM_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_uart1_intr_map.rs b/esp32/src/dport/app_uart1_intr_map.rs
index 0aae323785..2838ca081c 100644
--- a/esp32/src/dport/app_uart1_intr_map.rs
+++ b/esp32/src/dport/app_uart1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_UART1_INTR_MAP")
-            .field(
-                "app_uart1_intr_map",
-                &format_args!("{}", self.app_uart1_intr_map().bits()),
-            )
+            .field("app_uart1_intr_map", &self.app_uart1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_UART1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_uart2_intr_map.rs b/esp32/src/dport/app_uart2_intr_map.rs
index 95f22bce2e..55ca9600a3 100644
--- a/esp32/src/dport/app_uart2_intr_map.rs
+++ b/esp32/src/dport/app_uart2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_UART2_INTR_MAP")
-            .field(
-                "app_uart2_intr_map",
-                &format_args!("{}", self.app_uart2_intr_map().bits()),
-            )
+            .field("app_uart2_intr_map", &self.app_uart2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_UART2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_uart_intr_map.rs b/esp32/src/dport/app_uart_intr_map.rs
index 91d1e3543a..4038b7afcd 100644
--- a/esp32/src/dport/app_uart_intr_map.rs
+++ b/esp32/src/dport/app_uart_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_UART_INTR_MAP")
-            .field(
-                "app_uart_intr_map",
-                &format_args!("{}", self.app_uart_intr_map().bits()),
-            )
+            .field("app_uart_intr_map", &self.app_uart_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_UART_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_uhci0_intr_map.rs b/esp32/src/dport/app_uhci0_intr_map.rs
index 8a995b8e98..1971fa5aa4 100644
--- a/esp32/src/dport/app_uhci0_intr_map.rs
+++ b/esp32/src/dport/app_uhci0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_UHCI0_INTR_MAP")
-            .field(
-                "app_uhci0_intr_map",
-                &format_args!("{}", self.app_uhci0_intr_map().bits()),
-            )
+            .field("app_uhci0_intr_map", &self.app_uhci0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_UHCI0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_uhci1_intr_map.rs b/esp32/src/dport/app_uhci1_intr_map.rs
index 62f0958d7e..19c393a3e7 100644
--- a/esp32/src/dport/app_uhci1_intr_map.rs
+++ b/esp32/src/dport/app_uhci1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_UHCI1_INTR_MAP")
-            .field(
-                "app_uhci1_intr_map",
-                &format_args!("{}", self.app_uhci1_intr_map().bits()),
-            )
+            .field("app_uhci1_intr_map", &self.app_uhci1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_UHCI1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_vecbase_ctrl.rs b/esp32/src/dport/app_vecbase_ctrl.rs
index 0b1d42bdab..36e01a8666 100644
--- a/esp32/src/dport/app_vecbase_ctrl.rs
+++ b/esp32/src/dport/app_vecbase_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_VECBASE_CTRL")
-            .field(
-                "app_out_vecbase_sel",
-                &format_args!("{}", self.app_out_vecbase_sel().bits()),
-            )
+            .field("app_out_vecbase_sel", &self.app_out_vecbase_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_VECBASE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_vecbase_set.rs b/esp32/src/dport/app_vecbase_set.rs
index c71a9eceac..50702528d3 100644
--- a/esp32/src/dport/app_vecbase_set.rs
+++ b/esp32/src/dport/app_vecbase_set.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_VECBASE_SET")
-            .field(
-                "app_out_vecbase",
-                &format_args!("{}", self.app_out_vecbase().bits()),
-            )
+            .field("app_out_vecbase", &self.app_out_vecbase())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_VECBASE_SET_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21"]
     #[inline(always)]
diff --git a/esp32/src/dport/app_wdg_int_map.rs b/esp32/src/dport/app_wdg_int_map.rs
index 492deb0539..0bfd6e9204 100644
--- a/esp32/src/dport/app_wdg_int_map.rs
+++ b/esp32/src/dport/app_wdg_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_WDG_INT_MAP")
-            .field(
-                "app_wdg_int_map",
-                &format_args!("{}", self.app_wdg_int_map().bits()),
-            )
+            .field("app_wdg_int_map", &self.app_wdg_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_WDG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/appcpu_ctrl_a.rs b/esp32/src/dport/appcpu_ctrl_a.rs
index 04edc0243d..3e27040e67 100644
--- a/esp32/src/dport/appcpu_ctrl_a.rs
+++ b/esp32/src/dport/appcpu_ctrl_a.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APPCPU_CTRL_A")
-            .field(
-                "appcpu_resetting",
-                &format_args!("{}", self.appcpu_resetting().bit()),
-            )
+            .field("appcpu_resetting", &self.appcpu_resetting())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APPCPU_CTRL_A_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/appcpu_ctrl_b.rs b/esp32/src/dport/appcpu_ctrl_b.rs
index 73b3d96746..8ff1eb0e03 100644
--- a/esp32/src/dport/appcpu_ctrl_b.rs
+++ b/esp32/src/dport/appcpu_ctrl_b.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APPCPU_CTRL_B")
-            .field(
-                "appcpu_clkgate_en",
-                &format_args!("{}", self.appcpu_clkgate_en().bit()),
-            )
+            .field("appcpu_clkgate_en", &self.appcpu_clkgate_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APPCPU_CTRL_B_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/appcpu_ctrl_c.rs b/esp32/src/dport/appcpu_ctrl_c.rs
index 5a4cb5b2ff..39cd3ecf74 100644
--- a/esp32/src/dport/appcpu_ctrl_c.rs
+++ b/esp32/src/dport/appcpu_ctrl_c.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APPCPU_CTRL_C")
-            .field(
-                "appcpu_runstall",
-                &format_args!("{}", self.appcpu_runstall().bit()),
-            )
+            .field("appcpu_runstall", &self.appcpu_runstall())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APPCPU_CTRL_C_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/appcpu_ctrl_d.rs b/esp32/src/dport/appcpu_ctrl_d.rs
index 354dc867aa..8d6fcf0bca 100644
--- a/esp32/src/dport/appcpu_ctrl_d.rs
+++ b/esp32/src/dport/appcpu_ctrl_d.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APPCPU_CTRL_D")
-            .field(
-                "appcpu_boot_addr",
-                &format_args!("{}", self.appcpu_boot_addr().bits()),
-            )
+            .field("appcpu_boot_addr", &self.appcpu_boot_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APPCPU_CTRL_D_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/dport/bt_lpck_div_frac.rs b/esp32/src/dport/bt_lpck_div_frac.rs
index 46939cb437..3973f93c12 100644
--- a/esp32/src/dport/bt_lpck_div_frac.rs
+++ b/esp32/src/dport/bt_lpck_div_frac.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_LPCK_DIV_FRAC")
-            .field(
-                "bt_lpck_div_b",
-                &format_args!("{}", self.bt_lpck_div_b().bits()),
-            )
-            .field(
-                "bt_lpck_div_a",
-                &format_args!("{}", self.bt_lpck_div_a().bits()),
-            )
-            .field(
-                "lpclk_sel_rtc_slow",
-                &format_args!("{}", self.lpclk_sel_rtc_slow().bit()),
-            )
-            .field(
-                "lpclk_sel_8m",
-                &format_args!("{}", self.lpclk_sel_8m().bit()),
-            )
-            .field(
-                "lpclk_sel_xtal",
-                &format_args!("{}", self.lpclk_sel_xtal().bit()),
-            )
-            .field(
-                "lpclk_sel_xtal32k",
-                &format_args!("{}", self.lpclk_sel_xtal32k().bit()),
-            )
+            .field("bt_lpck_div_b", &self.bt_lpck_div_b())
+            .field("bt_lpck_div_a", &self.bt_lpck_div_a())
+            .field("lpclk_sel_rtc_slow", &self.lpclk_sel_rtc_slow())
+            .field("lpclk_sel_8m", &self.lpclk_sel_8m())
+            .field("lpclk_sel_xtal", &self.lpclk_sel_xtal())
+            .field("lpclk_sel_xtal32k", &self.lpclk_sel_xtal32k())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_LPCK_DIV_FRAC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
diff --git a/esp32/src/dport/bt_lpck_div_int.rs b/esp32/src/dport/bt_lpck_div_int.rs
index d2a2aff6c6..723530b6d0 100644
--- a/esp32/src/dport/bt_lpck_div_int.rs
+++ b/esp32/src/dport/bt_lpck_div_int.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_LPCK_DIV_INT")
-            .field(
-                "bt_lpck_div_num",
-                &format_args!("{}", self.bt_lpck_div_num().bits()),
-            )
-            .field(
-                "btextwakeup_req",
-                &format_args!("{}", self.btextwakeup_req().bit()),
-            )
+            .field("bt_lpck_div_num", &self.bt_lpck_div_num())
+            .field("btextwakeup_req", &self.btextwakeup_req())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_LPCK_DIV_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
diff --git a/esp32/src/dport/cache_ia_int_en.rs b/esp32/src/dport/cache_ia_int_en.rs
index 4f4965e6e7..085dd1af50 100644
--- a/esp32/src/dport/cache_ia_int_en.rs
+++ b/esp32/src/dport/cache_ia_int_en.rs
@@ -125,67 +125,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_IA_INT_EN")
-            .field(
-                "cache_ia_int_en",
-                &format_args!("{}", self.cache_ia_int_en().bits()),
-            )
-            .field(
-                "cache_ia_int_app_drom0",
-                &format_args!("{}", self.cache_ia_int_app_drom0().bit()),
-            )
-            .field(
-                "cache_ia_int_app_iram0",
-                &format_args!("{}", self.cache_ia_int_app_iram0().bit()),
-            )
-            .field(
-                "cache_ia_int_app_iram1",
-                &format_args!("{}", self.cache_ia_int_app_iram1().bit()),
-            )
-            .field(
-                "cache_ia_int_app_irom0",
-                &format_args!("{}", self.cache_ia_int_app_irom0().bit()),
-            )
-            .field(
-                "cache_ia_int_app_dram1",
-                &format_args!("{}", self.cache_ia_int_app_dram1().bit()),
-            )
+            .field("cache_ia_int_en", &self.cache_ia_int_en())
+            .field("cache_ia_int_app_drom0", &self.cache_ia_int_app_drom0())
+            .field("cache_ia_int_app_iram0", &self.cache_ia_int_app_iram0())
+            .field("cache_ia_int_app_iram1", &self.cache_ia_int_app_iram1())
+            .field("cache_ia_int_app_irom0", &self.cache_ia_int_app_irom0())
+            .field("cache_ia_int_app_dram1", &self.cache_ia_int_app_dram1())
             .field(
                 "cache_ia_int_app_opposite",
-                &format_args!("{}", self.cache_ia_int_app_opposite().bit()),
-            )
-            .field(
-                "cache_ia_int_pro_drom0",
-                &format_args!("{}", self.cache_ia_int_pro_drom0().bit()),
-            )
-            .field(
-                "cache_ia_int_pro_iram0",
-                &format_args!("{}", self.cache_ia_int_pro_iram0().bit()),
-            )
-            .field(
-                "cache_ia_int_pro_iram1",
-                &format_args!("{}", self.cache_ia_int_pro_iram1().bit()),
-            )
-            .field(
-                "cache_ia_int_pro_irom0",
-                &format_args!("{}", self.cache_ia_int_pro_irom0().bit()),
-            )
-            .field(
-                "cache_ia_int_pro_dram1",
-                &format_args!("{}", self.cache_ia_int_pro_dram1().bit()),
+                &self.cache_ia_int_app_opposite(),
             )
+            .field("cache_ia_int_pro_drom0", &self.cache_ia_int_pro_drom0())
+            .field("cache_ia_int_pro_iram0", &self.cache_ia_int_pro_iram0())
+            .field("cache_ia_int_pro_iram1", &self.cache_ia_int_pro_iram1())
+            .field("cache_ia_int_pro_irom0", &self.cache_ia_int_pro_irom0())
+            .field("cache_ia_int_pro_dram1", &self.cache_ia_int_pro_dram1())
             .field(
                 "cache_ia_int_pro_opposite",
-                &format_args!("{}", self.cache_ia_int_pro_opposite().bit()),
+                &self.cache_ia_int_pro_opposite(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_IA_INT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Interrupt enable bits for various invalid cache access reasons"]
     #[inline(always)]
diff --git a/esp32/src/dport/cache_mux_mode.rs b/esp32/src/dport/cache_mux_mode.rs
index 2603796947..e194705a1b 100644
--- a/esp32/src/dport/cache_mux_mode.rs
+++ b/esp32/src/dport/cache_mux_mode.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MUX_MODE")
-            .field(
-                "cache_mux_mode",
-                &format_args!("{}", self.cache_mux_mode().bits()),
-            )
+            .field("cache_mux_mode", &self.cache_mux_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MUX_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/core_rst_en.rs b/esp32/src/dport/core_rst_en.rs
index 2ae841fbf1..c7f7cee984 100644
--- a/esp32/src/dport/core_rst_en.rs
+++ b/esp32/src/dport/core_rst_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_RST_EN")
-            .field("core_rst", &format_args!("{}", self.core_rst().bits()))
+            .field("core_rst", &self.core_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_RST_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/dport/cpu_intr_from_cpu_0.rs b/esp32/src/dport/cpu_intr_from_cpu_0.rs
index 15466d0a58..5849399505 100644
--- a/esp32/src/dport/cpu_intr_from_cpu_0.rs
+++ b/esp32/src/dport/cpu_intr_from_cpu_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_0")
-            .field(
-                "cpu_intr_from_cpu_0",
-                &format_args!("{}", self.cpu_intr_from_cpu_0().bit()),
-            )
+            .field("cpu_intr_from_cpu_0", &self.cpu_intr_from_cpu_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/cpu_intr_from_cpu_1.rs b/esp32/src/dport/cpu_intr_from_cpu_1.rs
index 9b70539a5c..86fe8c77e8 100644
--- a/esp32/src/dport/cpu_intr_from_cpu_1.rs
+++ b/esp32/src/dport/cpu_intr_from_cpu_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_1")
-            .field(
-                "cpu_intr_from_cpu_1",
-                &format_args!("{}", self.cpu_intr_from_cpu_1().bit()),
-            )
+            .field("cpu_intr_from_cpu_1", &self.cpu_intr_from_cpu_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/cpu_intr_from_cpu_2.rs b/esp32/src/dport/cpu_intr_from_cpu_2.rs
index 8b56c30a45..d381bb69e9 100644
--- a/esp32/src/dport/cpu_intr_from_cpu_2.rs
+++ b/esp32/src/dport/cpu_intr_from_cpu_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_2")
-            .field(
-                "cpu_intr_from_cpu_2",
-                &format_args!("{}", self.cpu_intr_from_cpu_2().bit()),
-            )
+            .field("cpu_intr_from_cpu_2", &self.cpu_intr_from_cpu_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/cpu_intr_from_cpu_3.rs b/esp32/src/dport/cpu_intr_from_cpu_3.rs
index d4e2902a89..2029c90b21 100644
--- a/esp32/src/dport/cpu_intr_from_cpu_3.rs
+++ b/esp32/src/dport/cpu_intr_from_cpu_3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_3")
-            .field(
-                "cpu_intr_from_cpu_3",
-                &format_args!("{}", self.cpu_intr_from_cpu_3().bit()),
-            )
+            .field("cpu_intr_from_cpu_3", &self.cpu_intr_from_cpu_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/cpu_per_conf.rs b/esp32/src/dport/cpu_per_conf.rs
index fc1f32f934..d39d3c7f6c 100644
--- a/esp32/src/dport/cpu_per_conf.rs
+++ b/esp32/src/dport/cpu_per_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PER_CONF")
-            .field(
-                "cpuperiod_sel",
-                &format_args!("{}", self.cpuperiod_sel().bits()),
-            )
-            .field(
-                "lowspeed_clk_sel",
-                &format_args!("{}", self.lowspeed_clk_sel().bit()),
-            )
-            .field(
-                "fast_clk_rtc_sel",
-                &format_args!("{}", self.fast_clk_rtc_sel().bit()),
-            )
+            .field("cpuperiod_sel", &self.cpuperiod_sel())
+            .field("lowspeed_clk_sel", &self.lowspeed_clk_sel())
+            .field("fast_clk_rtc_sel", &self.fast_clk_rtc_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PER_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/date.rs b/esp32/src/dport/date.rs
index 86c2099643..d13ce18e6e 100644
--- a/esp32/src/dport/date.rs
+++ b/esp32/src/dport/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/dport/dmmu_page_mode.rs b/esp32/src/dport/dmmu_page_mode.rs
index 3477557c92..bb937be150 100644
--- a/esp32/src/dport/dmmu_page_mode.rs
+++ b/esp32/src/dport/dmmu_page_mode.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_PAGE_MODE")
-            .field(
-                "internal_sram_dmmu_ena",
-                &format_args!("{}", self.internal_sram_dmmu_ena().bit()),
-            )
-            .field(
-                "dmmu_page_mode",
-                &format_args!("{}", self.dmmu_page_mode().bits()),
-            )
+            .field("internal_sram_dmmu_ena", &self.internal_sram_dmmu_ena())
+            .field("dmmu_page_mode", &self.dmmu_page_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_PAGE_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table0.rs b/esp32/src/dport/dmmu_table0.rs
index 8d779df937..6e5ff9da51 100644
--- a/esp32/src/dport/dmmu_table0.rs
+++ b/esp32/src/dport/dmmu_table0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE0")
-            .field(
-                "dmmu_table0",
-                &format_args!("{}", self.dmmu_table0().bits()),
-            )
+            .field("dmmu_table0", &self.dmmu_table0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table1.rs b/esp32/src/dport/dmmu_table1.rs
index 63a673c9d1..cd61e8f026 100644
--- a/esp32/src/dport/dmmu_table1.rs
+++ b/esp32/src/dport/dmmu_table1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE1")
-            .field(
-                "dmmu_table1",
-                &format_args!("{}", self.dmmu_table1().bits()),
-            )
+            .field("dmmu_table1", &self.dmmu_table1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table10.rs b/esp32/src/dport/dmmu_table10.rs
index a5cbcc6988..0ecc13d7b5 100644
--- a/esp32/src/dport/dmmu_table10.rs
+++ b/esp32/src/dport/dmmu_table10.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE10")
-            .field(
-                "dmmu_table10",
-                &format_args!("{}", self.dmmu_table10().bits()),
-            )
+            .field("dmmu_table10", &self.dmmu_table10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table11.rs b/esp32/src/dport/dmmu_table11.rs
index 2d669a75e1..e4add55a15 100644
--- a/esp32/src/dport/dmmu_table11.rs
+++ b/esp32/src/dport/dmmu_table11.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE11")
-            .field(
-                "dmmu_table11",
-                &format_args!("{}", self.dmmu_table11().bits()),
-            )
+            .field("dmmu_table11", &self.dmmu_table11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table12.rs b/esp32/src/dport/dmmu_table12.rs
index 4662f87058..58c2521fcd 100644
--- a/esp32/src/dport/dmmu_table12.rs
+++ b/esp32/src/dport/dmmu_table12.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE12")
-            .field(
-                "dmmu_table12",
-                &format_args!("{}", self.dmmu_table12().bits()),
-            )
+            .field("dmmu_table12", &self.dmmu_table12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table13.rs b/esp32/src/dport/dmmu_table13.rs
index 8d06aff0c6..6a2c0ccaf5 100644
--- a/esp32/src/dport/dmmu_table13.rs
+++ b/esp32/src/dport/dmmu_table13.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE13")
-            .field(
-                "dmmu_table13",
-                &format_args!("{}", self.dmmu_table13().bits()),
-            )
+            .field("dmmu_table13", &self.dmmu_table13())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table14.rs b/esp32/src/dport/dmmu_table14.rs
index 873546286a..d4becfd4e1 100644
--- a/esp32/src/dport/dmmu_table14.rs
+++ b/esp32/src/dport/dmmu_table14.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE14")
-            .field(
-                "dmmu_table14",
-                &format_args!("{}", self.dmmu_table14().bits()),
-            )
+            .field("dmmu_table14", &self.dmmu_table14())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table15.rs b/esp32/src/dport/dmmu_table15.rs
index fe6ed47b85..a423c7af6a 100644
--- a/esp32/src/dport/dmmu_table15.rs
+++ b/esp32/src/dport/dmmu_table15.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE15")
-            .field(
-                "dmmu_table15",
-                &format_args!("{}", self.dmmu_table15().bits()),
-            )
+            .field("dmmu_table15", &self.dmmu_table15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table2.rs b/esp32/src/dport/dmmu_table2.rs
index 028b4cd3b7..ad66e325a8 100644
--- a/esp32/src/dport/dmmu_table2.rs
+++ b/esp32/src/dport/dmmu_table2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE2")
-            .field(
-                "dmmu_table2",
-                &format_args!("{}", self.dmmu_table2().bits()),
-            )
+            .field("dmmu_table2", &self.dmmu_table2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table3.rs b/esp32/src/dport/dmmu_table3.rs
index 38168bc37c..66ad9dcecc 100644
--- a/esp32/src/dport/dmmu_table3.rs
+++ b/esp32/src/dport/dmmu_table3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE3")
-            .field(
-                "dmmu_table3",
-                &format_args!("{}", self.dmmu_table3().bits()),
-            )
+            .field("dmmu_table3", &self.dmmu_table3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table4.rs b/esp32/src/dport/dmmu_table4.rs
index 508b47008d..51c90729c2 100644
--- a/esp32/src/dport/dmmu_table4.rs
+++ b/esp32/src/dport/dmmu_table4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE4")
-            .field(
-                "dmmu_table4",
-                &format_args!("{}", self.dmmu_table4().bits()),
-            )
+            .field("dmmu_table4", &self.dmmu_table4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table5.rs b/esp32/src/dport/dmmu_table5.rs
index 51a48a0706..aa6fbd6356 100644
--- a/esp32/src/dport/dmmu_table5.rs
+++ b/esp32/src/dport/dmmu_table5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE5")
-            .field(
-                "dmmu_table5",
-                &format_args!("{}", self.dmmu_table5().bits()),
-            )
+            .field("dmmu_table5", &self.dmmu_table5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table6.rs b/esp32/src/dport/dmmu_table6.rs
index 00e51e85f7..ccab989dce 100644
--- a/esp32/src/dport/dmmu_table6.rs
+++ b/esp32/src/dport/dmmu_table6.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE6")
-            .field(
-                "dmmu_table6",
-                &format_args!("{}", self.dmmu_table6().bits()),
-            )
+            .field("dmmu_table6", &self.dmmu_table6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table7.rs b/esp32/src/dport/dmmu_table7.rs
index f03c626be1..67929bd0b5 100644
--- a/esp32/src/dport/dmmu_table7.rs
+++ b/esp32/src/dport/dmmu_table7.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE7")
-            .field(
-                "dmmu_table7",
-                &format_args!("{}", self.dmmu_table7().bits()),
-            )
+            .field("dmmu_table7", &self.dmmu_table7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table8.rs b/esp32/src/dport/dmmu_table8.rs
index b977ba6ae4..707bad372e 100644
--- a/esp32/src/dport/dmmu_table8.rs
+++ b/esp32/src/dport/dmmu_table8.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE8")
-            .field(
-                "dmmu_table8",
-                &format_args!("{}", self.dmmu_table8().bits()),
-            )
+            .field("dmmu_table8", &self.dmmu_table8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/dmmu_table9.rs b/esp32/src/dport/dmmu_table9.rs
index f6fbe39d11..aeb4f9a0d5 100644
--- a/esp32/src/dport/dmmu_table9.rs
+++ b/esp32/src/dport/dmmu_table9.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMMU_TABLE9")
-            .field(
-                "dmmu_table9",
-                &format_args!("{}", self.dmmu_table9().bits()),
-            )
+            .field("dmmu_table9", &self.dmmu_table9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMMU_TABLE9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/front_end_mem_pd.rs b/esp32/src/dport/front_end_mem_pd.rs
index 466b2c7e17..481d0cba2b 100644
--- a/esp32/src/dport/front_end_mem_pd.rs
+++ b/esp32/src/dport/front_end_mem_pd.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FRONT_END_MEM_PD")
-            .field(
-                "agc_mem_force_pu",
-                &format_args!("{}", self.agc_mem_force_pu().bit()),
-            )
-            .field(
-                "agc_mem_force_pd",
-                &format_args!("{}", self.agc_mem_force_pd().bit()),
-            )
-            .field(
-                "pbus_mem_force_pu",
-                &format_args!("{}", self.pbus_mem_force_pu().bit()),
-            )
-            .field(
-                "pbus_mem_force_pd",
-                &format_args!("{}", self.pbus_mem_force_pd().bit()),
-            )
+            .field("agc_mem_force_pu", &self.agc_mem_force_pu())
+            .field("agc_mem_force_pd", &self.agc_mem_force_pd())
+            .field("pbus_mem_force_pu", &self.pbus_mem_force_pu())
+            .field("pbus_mem_force_pd", &self.pbus_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FRONT_END_MEM_PD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/host_inf_sel.rs b/esp32/src/dport/host_inf_sel.rs
index 5d87f16539..0eb0c6f543 100644
--- a/esp32/src/dport/host_inf_sel.rs
+++ b/esp32/src/dport/host_inf_sel.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_INF_SEL")
-            .field(
-                "peri_io_swap",
-                &format_args!("{}", self.peri_io_swap().bits()),
-            )
-            .field(
-                "link_device_sel",
-                &format_args!("{}", self.link_device_sel().bits()),
-            )
+            .field("peri_io_swap", &self.peri_io_swap())
+            .field("link_device_sel", &self.link_device_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_INF_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_page_mode.rs b/esp32/src/dport/immu_page_mode.rs
index 0418acf3c9..3041d5b721 100644
--- a/esp32/src/dport/immu_page_mode.rs
+++ b/esp32/src/dport/immu_page_mode.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_PAGE_MODE")
-            .field(
-                "internal_sram_immu_ena",
-                &format_args!("{}", self.internal_sram_immu_ena().bit()),
-            )
-            .field(
-                "immu_page_mode",
-                &format_args!("{}", self.immu_page_mode().bits()),
-            )
+            .field("internal_sram_immu_ena", &self.internal_sram_immu_ena())
+            .field("immu_page_mode", &self.immu_page_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_PAGE_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table0.rs b/esp32/src/dport/immu_table0.rs
index cf03884b73..bbb78f238d 100644
--- a/esp32/src/dport/immu_table0.rs
+++ b/esp32/src/dport/immu_table0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE0")
-            .field(
-                "immu_table0",
-                &format_args!("{}", self.immu_table0().bits()),
-            )
+            .field("immu_table0", &self.immu_table0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table1.rs b/esp32/src/dport/immu_table1.rs
index e8943c164b..cf19a54f59 100644
--- a/esp32/src/dport/immu_table1.rs
+++ b/esp32/src/dport/immu_table1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE1")
-            .field(
-                "immu_table1",
-                &format_args!("{}", self.immu_table1().bits()),
-            )
+            .field("immu_table1", &self.immu_table1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table10.rs b/esp32/src/dport/immu_table10.rs
index 023a165122..97dc1b0fe7 100644
--- a/esp32/src/dport/immu_table10.rs
+++ b/esp32/src/dport/immu_table10.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE10")
-            .field(
-                "immu_table10",
-                &format_args!("{}", self.immu_table10().bits()),
-            )
+            .field("immu_table10", &self.immu_table10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table11.rs b/esp32/src/dport/immu_table11.rs
index 0e3ab1f064..eb21a788c3 100644
--- a/esp32/src/dport/immu_table11.rs
+++ b/esp32/src/dport/immu_table11.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE11")
-            .field(
-                "immu_table11",
-                &format_args!("{}", self.immu_table11().bits()),
-            )
+            .field("immu_table11", &self.immu_table11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table12.rs b/esp32/src/dport/immu_table12.rs
index e49400728d..96cdf80537 100644
--- a/esp32/src/dport/immu_table12.rs
+++ b/esp32/src/dport/immu_table12.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE12")
-            .field(
-                "immu_table12",
-                &format_args!("{}", self.immu_table12().bits()),
-            )
+            .field("immu_table12", &self.immu_table12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table13.rs b/esp32/src/dport/immu_table13.rs
index f040acbab4..71c5fccd6e 100644
--- a/esp32/src/dport/immu_table13.rs
+++ b/esp32/src/dport/immu_table13.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE13")
-            .field(
-                "immu_table13",
-                &format_args!("{}", self.immu_table13().bits()),
-            )
+            .field("immu_table13", &self.immu_table13())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table14.rs b/esp32/src/dport/immu_table14.rs
index 59f0bfb6b6..09eccc7bf9 100644
--- a/esp32/src/dport/immu_table14.rs
+++ b/esp32/src/dport/immu_table14.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE14")
-            .field(
-                "immu_table14",
-                &format_args!("{}", self.immu_table14().bits()),
-            )
+            .field("immu_table14", &self.immu_table14())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table15.rs b/esp32/src/dport/immu_table15.rs
index 0b561b1ebc..7cf6ffc6ac 100644
--- a/esp32/src/dport/immu_table15.rs
+++ b/esp32/src/dport/immu_table15.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE15")
-            .field(
-                "immu_table15",
-                &format_args!("{}", self.immu_table15().bits()),
-            )
+            .field("immu_table15", &self.immu_table15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table2.rs b/esp32/src/dport/immu_table2.rs
index d49f2943e1..c3417368aa 100644
--- a/esp32/src/dport/immu_table2.rs
+++ b/esp32/src/dport/immu_table2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE2")
-            .field(
-                "immu_table2",
-                &format_args!("{}", self.immu_table2().bits()),
-            )
+            .field("immu_table2", &self.immu_table2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table3.rs b/esp32/src/dport/immu_table3.rs
index b28864e823..8280b353eb 100644
--- a/esp32/src/dport/immu_table3.rs
+++ b/esp32/src/dport/immu_table3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE3")
-            .field(
-                "immu_table3",
-                &format_args!("{}", self.immu_table3().bits()),
-            )
+            .field("immu_table3", &self.immu_table3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table4.rs b/esp32/src/dport/immu_table4.rs
index 3f0a650e73..64e20eaa52 100644
--- a/esp32/src/dport/immu_table4.rs
+++ b/esp32/src/dport/immu_table4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE4")
-            .field(
-                "immu_table4",
-                &format_args!("{}", self.immu_table4().bits()),
-            )
+            .field("immu_table4", &self.immu_table4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table5.rs b/esp32/src/dport/immu_table5.rs
index c871fc019c..4880e72882 100644
--- a/esp32/src/dport/immu_table5.rs
+++ b/esp32/src/dport/immu_table5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE5")
-            .field(
-                "immu_table5",
-                &format_args!("{}", self.immu_table5().bits()),
-            )
+            .field("immu_table5", &self.immu_table5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table6.rs b/esp32/src/dport/immu_table6.rs
index 8d35615673..241f446a2a 100644
--- a/esp32/src/dport/immu_table6.rs
+++ b/esp32/src/dport/immu_table6.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE6")
-            .field(
-                "immu_table6",
-                &format_args!("{}", self.immu_table6().bits()),
-            )
+            .field("immu_table6", &self.immu_table6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table7.rs b/esp32/src/dport/immu_table7.rs
index 7934737c6a..068599bef8 100644
--- a/esp32/src/dport/immu_table7.rs
+++ b/esp32/src/dport/immu_table7.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE7")
-            .field(
-                "immu_table7",
-                &format_args!("{}", self.immu_table7().bits()),
-            )
+            .field("immu_table7", &self.immu_table7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table8.rs b/esp32/src/dport/immu_table8.rs
index 3edc4f08be..4b1dcab981 100644
--- a/esp32/src/dport/immu_table8.rs
+++ b/esp32/src/dport/immu_table8.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE8")
-            .field(
-                "immu_table8",
-                &format_args!("{}", self.immu_table8().bits()),
-            )
+            .field("immu_table8", &self.immu_table8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/immu_table9.rs b/esp32/src/dport/immu_table9.rs
index f3babf4c62..a159c4e803 100644
--- a/esp32/src/dport/immu_table9.rs
+++ b/esp32/src/dport/immu_table9.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMMU_TABLE9")
-            .field(
-                "immu_table9",
-                &format_args!("{}", self.immu_table9().bits()),
-            )
+            .field("immu_table9", &self.immu_table9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMMU_TABLE9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/dport/iram_dram_ahb_sel.rs b/esp32/src/dport/iram_dram_ahb_sel.rs
index 76daf5034b..aa2c29df67 100644
--- a/esp32/src/dport/iram_dram_ahb_sel.rs
+++ b/esp32/src/dport/iram_dram_ahb_sel.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IRAM_DRAM_AHB_SEL")
-            .field(
-                "mask_pro_iram",
-                &format_args!("{}", self.mask_pro_iram().bit()),
-            )
-            .field(
-                "mask_app_iram",
-                &format_args!("{}", self.mask_app_iram().bit()),
-            )
-            .field(
-                "mask_pro_dram",
-                &format_args!("{}", self.mask_pro_dram().bit()),
-            )
-            .field(
-                "mask_app_dram",
-                &format_args!("{}", self.mask_app_dram().bit()),
-            )
-            .field("mask_ahb", &format_args!("{}", self.mask_ahb().bit()))
-            .field(
-                "mac_dump_mode",
-                &format_args!("{}", self.mac_dump_mode().bits()),
-            )
+            .field("mask_pro_iram", &self.mask_pro_iram())
+            .field("mask_app_iram", &self.mask_app_iram())
+            .field("mask_pro_dram", &self.mask_pro_dram())
+            .field("mask_app_dram", &self.mask_app_dram())
+            .field("mask_ahb", &self.mask_ahb())
+            .field("mac_dump_mode", &self.mac_dump_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IRAM_DRAM_AHB_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/mem_access_dbug0.rs b/esp32/src/dport/mem_access_dbug0.rs
index cc9a677a82..2cc5c12187 100644
--- a/esp32/src/dport/mem_access_dbug0.rs
+++ b/esp32/src/dport/mem_access_dbug0.rs
@@ -69,45 +69,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_ACCESS_DBUG0")
-            .field(
-                "pro_rom_mpu_ad",
-                &format_args!("{}", self.pro_rom_mpu_ad().bit()),
-            )
-            .field("pro_rom_ia", &format_args!("{}", self.pro_rom_ia().bit()))
-            .field(
-                "app_rom_mpu_ad",
-                &format_args!("{}", self.app_rom_mpu_ad().bit()),
-            )
-            .field("app_rom_ia", &format_args!("{}", self.app_rom_ia().bit()))
-            .field(
-                "share_rom_mpu_ad",
-                &format_args!("{}", self.share_rom_mpu_ad().bits()),
-            )
-            .field(
-                "share_rom_ia",
-                &format_args!("{}", self.share_rom_ia().bits()),
-            )
-            .field(
-                "internal_sram_mmu_ad",
-                &format_args!("{}", self.internal_sram_mmu_ad().bits()),
-            )
-            .field(
-                "internal_sram_ia",
-                &format_args!("{}", self.internal_sram_ia().bits()),
-            )
+            .field("pro_rom_mpu_ad", &self.pro_rom_mpu_ad())
+            .field("pro_rom_ia", &self.pro_rom_ia())
+            .field("app_rom_mpu_ad", &self.app_rom_mpu_ad())
+            .field("app_rom_ia", &self.app_rom_ia())
+            .field("share_rom_mpu_ad", &self.share_rom_mpu_ad())
+            .field("share_rom_ia", &self.share_rom_ia())
+            .field("internal_sram_mmu_ad", &self.internal_sram_mmu_ad())
+            .field("internal_sram_ia", &self.internal_sram_ia())
             .field(
                 "internal_sram_mmu_multi_hit",
-                &format_args!("{}", self.internal_sram_mmu_multi_hit().bits()),
+                &self.internal_sram_mmu_multi_hit(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_ACCESS_DBUG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_access_dbug0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_ACCESS_DBUG0_SPEC;
 impl crate::RegisterSpec for MEM_ACCESS_DBUG0_SPEC {
diff --git a/esp32/src/dport/mem_access_dbug1.rs b/esp32/src/dport/mem_access_dbug1.rs
index 6e720e3a8c..7b5d3d7fec 100644
--- a/esp32/src/dport/mem_access_dbug1.rs
+++ b/esp32/src/dport/mem_access_dbug1.rs
@@ -48,30 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_ACCESS_DBUG1")
-            .field(
-                "internal_sram_mmu_miss",
-                &format_args!("{}", self.internal_sram_mmu_miss().bits()),
-            )
-            .field("arb_ia", &format_args!("{}", self.arb_ia().bits()))
-            .field("pidgen_ia", &format_args!("{}", self.pidgen_ia().bits()))
-            .field(
-                "ahb_access_deny",
-                &format_args!("{}", self.ahb_access_deny().bit()),
-            )
-            .field(
-                "ahblite_access_deny",
-                &format_args!("{}", self.ahblite_access_deny().bit()),
-            )
-            .field("ahblite_ia", &format_args!("{}", self.ahblite_ia().bit()))
+            .field("internal_sram_mmu_miss", &self.internal_sram_mmu_miss())
+            .field("arb_ia", &self.arb_ia())
+            .field("pidgen_ia", &self.pidgen_ia())
+            .field("ahb_access_deny", &self.ahb_access_deny())
+            .field("ahblite_access_deny", &self.ahblite_access_deny())
+            .field("ahblite_ia", &self.ahblite_ia())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_ACCESS_DBUG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_access_dbug1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_ACCESS_DBUG1_SPEC;
 impl crate::RegisterSpec for MEM_ACCESS_DBUG1_SPEC {
diff --git a/esp32/src/dport/mem_pd_mask.rs b/esp32/src/dport/mem_pd_mask.rs
index 187ea24cb7..4771f5216b 100644
--- a/esp32/src/dport/mem_pd_mask.rs
+++ b/esp32/src/dport/mem_pd_mask.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_PD_MASK")
-            .field(
-                "lslp_mem_pd_mask",
-                &format_args!("{}", self.lslp_mem_pd_mask().bit()),
-            )
+            .field("lslp_mem_pd_mask", &self.lslp_mem_pd_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_PD_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/mmu_ia_int_en.rs b/esp32/src/dport/mmu_ia_int_en.rs
index 7005a0c4d1..60509cd838 100644
--- a/esp32/src/dport/mmu_ia_int_en.rs
+++ b/esp32/src/dport/mmu_ia_int_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MMU_IA_INT_EN")
-            .field(
-                "mmu_ia_int_en",
-                &format_args!("{}", self.mmu_ia_int_en().bits()),
-            )
+            .field("mmu_ia_int_en", &self.mmu_ia_int_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MMU_IA_INT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23"]
     #[inline(always)]
diff --git a/esp32/src/dport/mpu_ia_int_en.rs b/esp32/src/dport/mpu_ia_int_en.rs
index 77ee104a14..88ca491a5e 100644
--- a/esp32/src/dport/mpu_ia_int_en.rs
+++ b/esp32/src/dport/mpu_ia_int_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MPU_IA_INT_EN")
-            .field(
-                "mpu_ia_int_en",
-                &format_args!("{}", self.mpu_ia_int_en().bits()),
-            )
+            .field("mpu_ia_int_en", &self.mpu_ia_int_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MPU_IA_INT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:16"]
     #[inline(always)]
diff --git a/esp32/src/dport/peri_clk_en.rs b/esp32/src/dport/peri_clk_en.rs
index ea26afc07e..0bde94599e 100644
--- a/esp32/src/dport/peri_clk_en.rs
+++ b/esp32/src/dport/peri_clk_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_EN")
-            .field(
-                "peri_clk_en",
-                &format_args!("{}", self.peri_clk_en().bits()),
-            )
+            .field("peri_clk_en", &self.peri_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/dport/peri_rst_en.rs b/esp32/src/dport/peri_rst_en.rs
index d2031a5862..70b90f4b58 100644
--- a/esp32/src/dport/peri_rst_en.rs
+++ b/esp32/src/dport/peri_rst_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_RST_EN")
-            .field(
-                "peri_rst_en",
-                &format_args!("{}", self.peri_rst_en().bits()),
-            )
+            .field("peri_rst_en", &self.peri_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_RST_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/dport/perip_clk_en.rs b/esp32/src/dport/perip_clk_en.rs
index 0efdf3b2c2..c992f4bcc7 100644
--- a/esp32/src/dport/perip_clk_en.rs
+++ b/esp32/src/dport/perip_clk_en.rs
@@ -251,81 +251,36 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_CLK_EN")
-            .field(
-                "timers_clk_en",
-                &format_args!("{}", self.timers_clk_en().bit()),
-            )
-            .field(
-                "spi01_clk_en",
-                &format_args!("{}", self.spi01_clk_en().bit()),
-            )
-            .field("uart_clk_en", &format_args!("{}", self.uart_clk_en().bit()))
-            .field("wdg_clk_en", &format_args!("{}", self.wdg_clk_en().bit()))
-            .field("i2s0_clk_en", &format_args!("{}", self.i2s0_clk_en().bit()))
-            .field(
-                "uart1_clk_en",
-                &format_args!("{}", self.uart1_clk_en().bit()),
-            )
-            .field("spi2_clk_en", &format_args!("{}", self.spi2_clk_en().bit()))
-            .field(
-                "i2c0_ext0_clk_en",
-                &format_args!("{}", self.i2c0_ext0_clk_en().bit()),
-            )
-            .field(
-                "uhci0_clk_en",
-                &format_args!("{}", self.uhci0_clk_en().bit()),
-            )
-            .field("rmt_clk_en", &format_args!("{}", self.rmt_clk_en().bit()))
-            .field("pcnt_clk_en", &format_args!("{}", self.pcnt_clk_en().bit()))
-            .field("ledc_clk_en", &format_args!("{}", self.ledc_clk_en().bit()))
-            .field(
-                "uhci1_clk_en",
-                &format_args!("{}", self.uhci1_clk_en().bit()),
-            )
-            .field(
-                "timergroup_clk_en",
-                &format_args!("{}", self.timergroup_clk_en().bit()),
-            )
-            .field(
-                "efuse_clk_en",
-                &format_args!("{}", self.efuse_clk_en().bit()),
-            )
-            .field(
-                "timergroup1_clk_en",
-                &format_args!("{}", self.timergroup1_clk_en().bit()),
-            )
-            .field("spi3_clk_en", &format_args!("{}", self.spi3_clk_en().bit()))
-            .field("pwm0_clk_en", &format_args!("{}", self.pwm0_clk_en().bit()))
-            .field(
-                "i2c_ext1_clk_en",
-                &format_args!("{}", self.i2c_ext1_clk_en().bit()),
-            )
-            .field("twai_clk_en", &format_args!("{}", self.twai_clk_en().bit()))
-            .field("pwm1_clk_en", &format_args!("{}", self.pwm1_clk_en().bit()))
-            .field("i2s1_clk_en", &format_args!("{}", self.i2s1_clk_en().bit()))
-            .field(
-                "spi_dma_clk_en",
-                &format_args!("{}", self.spi_dma_clk_en().bit()),
-            )
-            .field(
-                "uart2_clk_en",
-                &format_args!("{}", self.uart2_clk_en().bit()),
-            )
-            .field(
-                "uart_mem_clk_en",
-                &format_args!("{}", self.uart_mem_clk_en().bit()),
-            )
-            .field("pwm2_clk_en", &format_args!("{}", self.pwm2_clk_en().bit()))
-            .field("pwm3_clk_en", &format_args!("{}", self.pwm3_clk_en().bit()))
+            .field("timers_clk_en", &self.timers_clk_en())
+            .field("spi01_clk_en", &self.spi01_clk_en())
+            .field("uart_clk_en", &self.uart_clk_en())
+            .field("wdg_clk_en", &self.wdg_clk_en())
+            .field("i2s0_clk_en", &self.i2s0_clk_en())
+            .field("uart1_clk_en", &self.uart1_clk_en())
+            .field("spi2_clk_en", &self.spi2_clk_en())
+            .field("i2c0_ext0_clk_en", &self.i2c0_ext0_clk_en())
+            .field("uhci0_clk_en", &self.uhci0_clk_en())
+            .field("rmt_clk_en", &self.rmt_clk_en())
+            .field("pcnt_clk_en", &self.pcnt_clk_en())
+            .field("ledc_clk_en", &self.ledc_clk_en())
+            .field("uhci1_clk_en", &self.uhci1_clk_en())
+            .field("timergroup_clk_en", &self.timergroup_clk_en())
+            .field("efuse_clk_en", &self.efuse_clk_en())
+            .field("timergroup1_clk_en", &self.timergroup1_clk_en())
+            .field("spi3_clk_en", &self.spi3_clk_en())
+            .field("pwm0_clk_en", &self.pwm0_clk_en())
+            .field("i2c_ext1_clk_en", &self.i2c_ext1_clk_en())
+            .field("twai_clk_en", &self.twai_clk_en())
+            .field("pwm1_clk_en", &self.pwm1_clk_en())
+            .field("i2s1_clk_en", &self.i2s1_clk_en())
+            .field("spi_dma_clk_en", &self.spi_dma_clk_en())
+            .field("uart2_clk_en", &self.uart2_clk_en())
+            .field("uart_mem_clk_en", &self.uart_mem_clk_en())
+            .field("pwm2_clk_en", &self.pwm2_clk_en())
+            .field("pwm3_clk_en", &self.pwm3_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/perip_rst_en.rs b/esp32/src/dport/perip_rst_en.rs
index 09e96f0d89..2966fa368c 100644
--- a/esp32/src/dport/perip_rst_en.rs
+++ b/esp32/src/dport/perip_rst_en.rs
@@ -251,57 +251,36 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_RST_EN")
-            .field("timers_rst", &format_args!("{}", self.timers_rst().bit()))
-            .field("spi01_rst", &format_args!("{}", self.spi01_rst().bit()))
-            .field("uart_rst", &format_args!("{}", self.uart_rst().bit()))
-            .field("wdg_rst", &format_args!("{}", self.wdg_rst().bit()))
-            .field("i2s0_rst", &format_args!("{}", self.i2s0_rst().bit()))
-            .field("uart1_rst", &format_args!("{}", self.uart1_rst().bit()))
-            .field("spi2_rst", &format_args!("{}", self.spi2_rst().bit()))
-            .field(
-                "i2c0_ext0_rst",
-                &format_args!("{}", self.i2c0_ext0_rst().bit()),
-            )
-            .field("uhci0_rst", &format_args!("{}", self.uhci0_rst().bit()))
-            .field("rmt_rst", &format_args!("{}", self.rmt_rst().bit()))
-            .field("pcnt_rst", &format_args!("{}", self.pcnt_rst().bit()))
-            .field("ledc_rst", &format_args!("{}", self.ledc_rst().bit()))
-            .field("uhci1_rst", &format_args!("{}", self.uhci1_rst().bit()))
-            .field(
-                "timergroup_rst",
-                &format_args!("{}", self.timergroup_rst().bit()),
-            )
-            .field("efuse_rst", &format_args!("{}", self.efuse_rst().bit()))
-            .field(
-                "timergroup1_rst",
-                &format_args!("{}", self.timergroup1_rst().bit()),
-            )
-            .field("spi3_rst", &format_args!("{}", self.spi3_rst().bit()))
-            .field("pwm0_rst", &format_args!("{}", self.pwm0_rst().bit()))
-            .field(
-                "i2c_ext1_rst",
-                &format_args!("{}", self.i2c_ext1_rst().bit()),
-            )
-            .field("twai_rst", &format_args!("{}", self.twai_rst().bit()))
-            .field("pwm1_rst", &format_args!("{}", self.pwm1_rst().bit()))
-            .field("i2s1_rst", &format_args!("{}", self.i2s1_rst().bit()))
-            .field("spi_dma_rst", &format_args!("{}", self.spi_dma_rst().bit()))
-            .field("uart2_rst", &format_args!("{}", self.uart2_rst().bit()))
-            .field(
-                "uart_mem_rst",
-                &format_args!("{}", self.uart_mem_rst().bit()),
-            )
-            .field("pwm2_rst", &format_args!("{}", self.pwm2_rst().bit()))
-            .field("pwm3_rst", &format_args!("{}", self.pwm3_rst().bit()))
+            .field("timers_rst", &self.timers_rst())
+            .field("spi01_rst", &self.spi01_rst())
+            .field("uart_rst", &self.uart_rst())
+            .field("wdg_rst", &self.wdg_rst())
+            .field("i2s0_rst", &self.i2s0_rst())
+            .field("uart1_rst", &self.uart1_rst())
+            .field("spi2_rst", &self.spi2_rst())
+            .field("i2c0_ext0_rst", &self.i2c0_ext0_rst())
+            .field("uhci0_rst", &self.uhci0_rst())
+            .field("rmt_rst", &self.rmt_rst())
+            .field("pcnt_rst", &self.pcnt_rst())
+            .field("ledc_rst", &self.ledc_rst())
+            .field("uhci1_rst", &self.uhci1_rst())
+            .field("timergroup_rst", &self.timergroup_rst())
+            .field("efuse_rst", &self.efuse_rst())
+            .field("timergroup1_rst", &self.timergroup1_rst())
+            .field("spi3_rst", &self.spi3_rst())
+            .field("pwm0_rst", &self.pwm0_rst())
+            .field("i2c_ext1_rst", &self.i2c_ext1_rst())
+            .field("twai_rst", &self.twai_rst())
+            .field("pwm1_rst", &self.pwm1_rst())
+            .field("i2s1_rst", &self.i2s1_rst())
+            .field("spi_dma_rst", &self.spi_dma_rst())
+            .field("uart2_rst", &self.uart2_rst())
+            .field("uart_mem_rst", &self.uart_mem_rst())
+            .field("pwm2_rst", &self.pwm2_rst())
+            .field("pwm3_rst", &self.pwm3_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_RST_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_bb_int_map.rs b/esp32/src/dport/pro_bb_int_map.rs
index 16674ae6b6..b3f4b91d8b 100644
--- a/esp32/src/dport/pro_bb_int_map.rs
+++ b/esp32/src/dport/pro_bb_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_BB_INT_MAP")
-            .field(
-                "pro_bb_int_map",
-                &format_args!("{}", self.pro_bb_int_map().bits()),
-            )
+            .field("pro_bb_int_map", &self.pro_bb_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_BB_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_boot_remap_ctrl.rs b/esp32/src/dport/pro_boot_remap_ctrl.rs
index e6ff9b37a4..05c516d49a 100644
--- a/esp32/src/dport/pro_boot_remap_ctrl.rs
+++ b/esp32/src/dport/pro_boot_remap_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_BOOT_REMAP_CTRL")
-            .field(
-                "pro_boot_remap",
-                &format_args!("{}", self.pro_boot_remap().bit()),
-            )
+            .field("pro_boot_remap", &self.pro_boot_remap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_BOOT_REMAP_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_bt_bb_int_map.rs b/esp32/src/dport/pro_bt_bb_int_map.rs
index bfbda54b25..ff1f57d1b8 100644
--- a/esp32/src/dport/pro_bt_bb_int_map.rs
+++ b/esp32/src/dport/pro_bt_bb_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_BT_BB_INT_MAP")
-            .field(
-                "pro_bt_bb_int_map",
-                &format_args!("{}", self.pro_bt_bb_int_map().bits()),
-            )
+            .field("pro_bt_bb_int_map", &self.pro_bt_bb_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_BT_BB_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_bt_bb_nmi_map.rs b/esp32/src/dport/pro_bt_bb_nmi_map.rs
index af784f097f..a12c61215d 100644
--- a/esp32/src/dport/pro_bt_bb_nmi_map.rs
+++ b/esp32/src/dport/pro_bt_bb_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_BT_BB_NMI_MAP")
-            .field(
-                "pro_bt_bb_nmi_map",
-                &format_args!("{}", self.pro_bt_bb_nmi_map().bits()),
-            )
+            .field("pro_bt_bb_nmi_map", &self.pro_bt_bb_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_BT_BB_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_bt_mac_int_map.rs b/esp32/src/dport/pro_bt_mac_int_map.rs
index b994353ac4..9df77f3091 100644
--- a/esp32/src/dport/pro_bt_mac_int_map.rs
+++ b/esp32/src/dport/pro_bt_mac_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_BT_MAC_INT_MAP")
-            .field(
-                "pro_bt_mac_int_map",
-                &format_args!("{}", self.pro_bt_mac_int_map().bits()),
-            )
+            .field("pro_bt_mac_int_map", &self.pro_bt_mac_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_BT_MAC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cache_ctrl.rs b/esp32/src/dport/pro_cache_ctrl.rs
index d81a25dd55..5778984e55 100644
--- a/esp32/src/dport/pro_cache_ctrl.rs
+++ b/esp32/src/dport/pro_cache_ctrl.rs
@@ -133,66 +133,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CACHE_CTRL")
-            .field(
-                "pro_cache_mode",
-                &format_args!("{}", self.pro_cache_mode().bit()),
-            )
-            .field(
-                "pro_cache_enable",
-                &format_args!("{}", self.pro_cache_enable().bit()),
-            )
-            .field(
-                "pro_cache_flush_ena",
-                &format_args!("{}", self.pro_cache_flush_ena().bit()),
-            )
-            .field(
-                "pro_cache_flush_done",
-                &format_args!("{}", self.pro_cache_flush_done().bit()),
-            )
-            .field(
-                "pro_cache_lock_0_en",
-                &format_args!("{}", self.pro_cache_lock_0_en().bit()),
-            )
-            .field(
-                "pro_cache_lock_1_en",
-                &format_args!("{}", self.pro_cache_lock_1_en().bit()),
-            )
-            .field(
-                "pro_cache_lock_2_en",
-                &format_args!("{}", self.pro_cache_lock_2_en().bit()),
-            )
-            .field(
-                "pro_cache_lock_3_en",
-                &format_args!("{}", self.pro_cache_lock_3_en().bit()),
-            )
-            .field(
-                "pro_single_iram_ena",
-                &format_args!("{}", self.pro_single_iram_ena().bit()),
-            )
-            .field(
-                "pro_dram_split",
-                &format_args!("{}", self.pro_dram_split().bit()),
-            )
-            .field(
-                "pro_ahb_spi_req",
-                &format_args!("{}", self.pro_ahb_spi_req().bit()),
-            )
-            .field(
-                "pro_slave_req",
-                &format_args!("{}", self.pro_slave_req().bit()),
-            )
-            .field("ahb_spi_req", &format_args!("{}", self.ahb_spi_req().bit()))
-            .field("slave_req", &format_args!("{}", self.slave_req().bit()))
-            .field("pro_dram_hl", &format_args!("{}", self.pro_dram_hl().bit()))
+            .field("pro_cache_mode", &self.pro_cache_mode())
+            .field("pro_cache_enable", &self.pro_cache_enable())
+            .field("pro_cache_flush_ena", &self.pro_cache_flush_ena())
+            .field("pro_cache_flush_done", &self.pro_cache_flush_done())
+            .field("pro_cache_lock_0_en", &self.pro_cache_lock_0_en())
+            .field("pro_cache_lock_1_en", &self.pro_cache_lock_1_en())
+            .field("pro_cache_lock_2_en", &self.pro_cache_lock_2_en())
+            .field("pro_cache_lock_3_en", &self.pro_cache_lock_3_en())
+            .field("pro_single_iram_ena", &self.pro_single_iram_ena())
+            .field("pro_dram_split", &self.pro_dram_split())
+            .field("pro_ahb_spi_req", &self.pro_ahb_spi_req())
+            .field("pro_slave_req", &self.pro_slave_req())
+            .field("ahb_spi_req", &self.ahb_spi_req())
+            .field("slave_req", &self.slave_req())
+            .field("pro_dram_hl", &self.pro_dram_hl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cache_ctrl1.rs b/esp32/src/dport/pro_cache_ctrl1.rs
index eba93fa650..3fa7a83d86 100644
--- a/esp32/src/dport/pro_cache_ctrl1.rs
+++ b/esp32/src/dport/pro_cache_ctrl1.rs
@@ -107,56 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CACHE_CTRL1")
-            .field(
-                "pro_cache_mask_iram0",
-                &format_args!("{}", self.pro_cache_mask_iram0().bit()),
-            )
-            .field(
-                "pro_cache_mask_iram1",
-                &format_args!("{}", self.pro_cache_mask_iram1().bit()),
-            )
-            .field(
-                "pro_cache_mask_irom0",
-                &format_args!("{}", self.pro_cache_mask_irom0().bit()),
-            )
-            .field(
-                "pro_cache_mask_dram1",
-                &format_args!("{}", self.pro_cache_mask_dram1().bit()),
-            )
-            .field(
-                "pro_cache_mask_drom0",
-                &format_args!("{}", self.pro_cache_mask_drom0().bit()),
-            )
-            .field(
-                "pro_cache_mask_opsdram",
-                &format_args!("{}", self.pro_cache_mask_opsdram().bit()),
-            )
-            .field(
-                "pro_cmmu_sram_page_mode",
-                &format_args!("{}", self.pro_cmmu_sram_page_mode().bits()),
-            )
-            .field(
-                "pro_cmmu_flash_page_mode",
-                &format_args!("{}", self.pro_cmmu_flash_page_mode().bits()),
-            )
-            .field(
-                "pro_cmmu_force_on",
-                &format_args!("{}", self.pro_cmmu_force_on().bit()),
-            )
-            .field("pro_cmmu_pd", &format_args!("{}", self.pro_cmmu_pd().bit()))
-            .field(
-                "pro_cache_mmu_ia_clr",
-                &format_args!("{}", self.pro_cache_mmu_ia_clr().bit()),
-            )
+            .field("pro_cache_mask_iram0", &self.pro_cache_mask_iram0())
+            .field("pro_cache_mask_iram1", &self.pro_cache_mask_iram1())
+            .field("pro_cache_mask_irom0", &self.pro_cache_mask_irom0())
+            .field("pro_cache_mask_dram1", &self.pro_cache_mask_dram1())
+            .field("pro_cache_mask_drom0", &self.pro_cache_mask_drom0())
+            .field("pro_cache_mask_opsdram", &self.pro_cache_mask_opsdram())
+            .field("pro_cmmu_sram_page_mode", &self.pro_cmmu_sram_page_mode())
+            .field("pro_cmmu_flash_page_mode", &self.pro_cmmu_flash_page_mode())
+            .field("pro_cmmu_force_on", &self.pro_cmmu_force_on())
+            .field("pro_cmmu_pd", &self.pro_cmmu_pd())
+            .field("pro_cache_mmu_ia_clr", &self.pro_cache_mmu_ia_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cache_ia_int_map.rs b/esp32/src/dport/pro_cache_ia_int_map.rs
index aad8bb3469..5bd1ee3268 100644
--- a/esp32/src/dport/pro_cache_ia_int_map.rs
+++ b/esp32/src/dport/pro_cache_ia_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CACHE_IA_INT_MAP")
-            .field(
-                "pro_cache_ia_int_map",
-                &format_args!("{}", self.pro_cache_ia_int_map().bits()),
-            )
+            .field("pro_cache_ia_int_map", &self.pro_cache_ia_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_IA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cache_lock_0_addr.rs b/esp32/src/dport/pro_cache_lock_0_addr.rs
index 41742dbba6..7dbd42401e 100644
--- a/esp32/src/dport/pro_cache_lock_0_addr.rs
+++ b/esp32/src/dport/pro_cache_lock_0_addr.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CACHE_LOCK_0_ADDR")
-            .field("pre", &format_args!("{}", self.pre().bits()))
-            .field("min", &format_args!("{}", self.min().bits()))
-            .field("max", &format_args!("{}", self.max().bits()))
+            .field("pre", &self.pre())
+            .field("min", &self.min())
+            .field("max", &self.max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_LOCK_0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cache_lock_1_addr.rs b/esp32/src/dport/pro_cache_lock_1_addr.rs
index 253e4084c4..cde9c6bc11 100644
--- a/esp32/src/dport/pro_cache_lock_1_addr.rs
+++ b/esp32/src/dport/pro_cache_lock_1_addr.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CACHE_LOCK_1_ADDR")
-            .field("pre", &format_args!("{}", self.pre().bits()))
-            .field("min", &format_args!("{}", self.min().bits()))
-            .field("max", &format_args!("{}", self.max().bits()))
+            .field("pre", &self.pre())
+            .field("min", &self.min())
+            .field("max", &self.max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_LOCK_1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cache_lock_2_addr.rs b/esp32/src/dport/pro_cache_lock_2_addr.rs
index 8e7197678b..800d39ae4a 100644
--- a/esp32/src/dport/pro_cache_lock_2_addr.rs
+++ b/esp32/src/dport/pro_cache_lock_2_addr.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CACHE_LOCK_2_ADDR")
-            .field("pre", &format_args!("{}", self.pre().bits()))
-            .field("min", &format_args!("{}", self.min().bits()))
-            .field("max", &format_args!("{}", self.max().bits()))
+            .field("pre", &self.pre())
+            .field("min", &self.min())
+            .field("max", &self.max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_LOCK_2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cache_lock_3_addr.rs b/esp32/src/dport/pro_cache_lock_3_addr.rs
index f467529462..19000ecf9c 100644
--- a/esp32/src/dport/pro_cache_lock_3_addr.rs
+++ b/esp32/src/dport/pro_cache_lock_3_addr.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CACHE_LOCK_3_ADDR")
-            .field("pre", &format_args!("{}", self.pre().bits()))
-            .field("min", &format_args!("{}", self.min().bits()))
-            .field("max", &format_args!("{}", self.max().bits()))
+            .field("pre", &self.pre())
+            .field("min", &self.min())
+            .field("max", &self.max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_LOCK_3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_can_int_map.rs b/esp32/src/dport/pro_can_int_map.rs
index 4dbe2a5b1e..fa5525e84b 100644
--- a/esp32/src/dport/pro_can_int_map.rs
+++ b/esp32/src/dport/pro_can_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CAN_INT_MAP")
-            .field(
-                "pro_can_int_map",
-                &format_args!("{}", self.pro_can_int_map().bits()),
-            )
+            .field("pro_can_int_map", &self.pro_can_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CAN_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cpu_intr_from_cpu_0_map.rs b/esp32/src/dport/pro_cpu_intr_from_cpu_0_map.rs
index fed322bb2c..0b9bd160a3 100644
--- a/esp32/src/dport/pro_cpu_intr_from_cpu_0_map.rs
+++ b/esp32/src/dport/pro_cpu_intr_from_cpu_0_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_CPU_INTR_FROM_CPU_0_MAP")
             .field(
                 "pro_cpu_intr_from_cpu_0_map",
-                &format_args!("{}", self.pro_cpu_intr_from_cpu_0_map().bits()),
+                &self.pro_cpu_intr_from_cpu_0_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_INTR_FROM_CPU_0_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cpu_intr_from_cpu_1_map.rs b/esp32/src/dport/pro_cpu_intr_from_cpu_1_map.rs
index 34ee4ba5b4..9ac155f19c 100644
--- a/esp32/src/dport/pro_cpu_intr_from_cpu_1_map.rs
+++ b/esp32/src/dport/pro_cpu_intr_from_cpu_1_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_CPU_INTR_FROM_CPU_1_MAP")
             .field(
                 "pro_cpu_intr_from_cpu_1_map",
-                &format_args!("{}", self.pro_cpu_intr_from_cpu_1_map().bits()),
+                &self.pro_cpu_intr_from_cpu_1_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_INTR_FROM_CPU_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cpu_intr_from_cpu_2_map.rs b/esp32/src/dport/pro_cpu_intr_from_cpu_2_map.rs
index 9618df3bc2..186480c3fd 100644
--- a/esp32/src/dport/pro_cpu_intr_from_cpu_2_map.rs
+++ b/esp32/src/dport/pro_cpu_intr_from_cpu_2_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_CPU_INTR_FROM_CPU_2_MAP")
             .field(
                 "pro_cpu_intr_from_cpu_2_map",
-                &format_args!("{}", self.pro_cpu_intr_from_cpu_2_map().bits()),
+                &self.pro_cpu_intr_from_cpu_2_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_INTR_FROM_CPU_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cpu_intr_from_cpu_3_map.rs b/esp32/src/dport/pro_cpu_intr_from_cpu_3_map.rs
index 4df47020e8..cbe3411026 100644
--- a/esp32/src/dport/pro_cpu_intr_from_cpu_3_map.rs
+++ b/esp32/src/dport/pro_cpu_intr_from_cpu_3_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_CPU_INTR_FROM_CPU_3_MAP")
             .field(
                 "pro_cpu_intr_from_cpu_3_map",
-                &format_args!("{}", self.pro_cpu_intr_from_cpu_3_map().bits()),
+                &self.pro_cpu_intr_from_cpu_3_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_INTR_FROM_CPU_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cpu_record_ctrl.rs b/esp32/src/dport/pro_cpu_record_ctrl.rs
index de9f09c31f..422c135b09 100644
--- a/esp32/src/dport/pro_cpu_record_ctrl.rs
+++ b/esp32/src/dport/pro_cpu_record_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CPU_RECORD_CTRL")
-            .field(
-                "pro_cpu_record_enable",
-                &format_args!("{}", self.pro_cpu_record_enable().bit()),
-            )
-            .field(
-                "pro_cpu_record_disable",
-                &format_args!("{}", self.pro_cpu_record_disable().bit()),
-            )
-            .field(
-                "pro_cpu_pdebug_enable",
-                &format_args!("{}", self.pro_cpu_pdebug_enable().bit()),
-            )
+            .field("pro_cpu_record_enable", &self.pro_cpu_record_enable())
+            .field("pro_cpu_record_disable", &self.pro_cpu_record_disable())
+            .field("pro_cpu_pdebug_enable", &self.pro_cpu_pdebug_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_RECORD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cpu_record_pdebugdata.rs b/esp32/src/dport/pro_cpu_record_pdebugdata.rs
index b5f49f8826..7f5999fa33 100644
--- a/esp32/src/dport/pro_cpu_record_pdebugdata.rs
+++ b/esp32/src/dport/pro_cpu_record_pdebugdata.rs
@@ -294,143 +294,128 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CPU_RECORD_PDEBUGDATA")
-            .field(
-                "record_pro_pdebugdata",
-                &format_args!("{}", self.record_pro_pdebugdata().bits()),
-            )
+            .field("record_pro_pdebugdata", &self.record_pro_pdebugdata())
             .field(
                 "record_pdebugdata_dep_other",
-                &format_args!("{}", self.record_pdebugdata_dep_other().bit()),
-            )
-            .field(
-                "record_pdebugdata_excvec",
-                &format_args!("{}", self.record_pdebugdata_excvec().bits()),
+                &self.record_pdebugdata_dep_other(),
             )
+            .field("record_pdebugdata_excvec", &self.record_pdebugdata_excvec())
             .field(
                 "record_pdebugdata_insntype_sr",
-                &format_args!("{}", self.record_pdebugdata_insntype_sr().bits()),
+                &self.record_pdebugdata_insntype_sr(),
             )
             .field(
                 "record_pdebugdata_insntype_rer",
-                &format_args!("{}", self.record_pdebugdata_insntype_rer().bit()),
+                &self.record_pdebugdata_insntype_rer(),
             )
             .field(
                 "record_pdebugdata_stall_buff",
-                &format_args!("{}", self.record_pdebugdata_stall_buff().bit()),
+                &self.record_pdebugdata_stall_buff(),
             )
             .field(
                 "record_pdebugdata_insntype_wer",
-                &format_args!("{}", self.record_pdebugdata_insntype_wer().bit()),
+                &self.record_pdebugdata_insntype_wer(),
             )
             .field(
                 "record_pdebugdata_stall_buffconfl",
-                &format_args!("{}", self.record_pdebugdata_stall_buffconfl().bit()),
+                &self.record_pdebugdata_stall_buffconfl(),
             )
             .field(
                 "record_pdebugdata_insntype_er",
-                &format_args!("{}", self.record_pdebugdata_insntype_er().bits()),
+                &self.record_pdebugdata_insntype_er(),
             )
             .field(
                 "record_pdebugdata_stall_dcm",
-                &format_args!("{}", self.record_pdebugdata_stall_dcm().bit()),
+                &self.record_pdebugdata_stall_dcm(),
             )
             .field(
                 "record_pdebugdata_stall_lsu",
-                &format_args!("{}", self.record_pdebugdata_stall_lsu().bit()),
+                &self.record_pdebugdata_stall_lsu(),
             )
             .field(
                 "record_pdebugdata_stall_icm",
-                &format_args!("{}", self.record_pdebugdata_stall_icm().bit()),
+                &self.record_pdebugdata_stall_icm(),
             )
             .field(
                 "record_pdebugdata_stall_irambusy",
-                &format_args!("{}", self.record_pdebugdata_stall_irambusy().bit()),
+                &self.record_pdebugdata_stall_irambusy(),
             )
             .field(
                 "record_pdebugdata_dep_lsu",
-                &format_args!("{}", self.record_pdebugdata_dep_lsu().bit()),
+                &self.record_pdebugdata_dep_lsu(),
             )
             .field(
                 "record_pdebugdata_stall_ipif",
-                &format_args!("{}", self.record_pdebugdata_stall_ipif().bit()),
+                &self.record_pdebugdata_stall_ipif(),
             )
             .field(
                 "record_pdebugdata_insntype_rsr",
-                &format_args!("{}", self.record_pdebugdata_insntype_rsr().bit()),
+                &self.record_pdebugdata_insntype_rsr(),
             )
             .field(
                 "record_pdebugdata_stall_tie",
-                &format_args!("{}", self.record_pdebugdata_stall_tie().bit()),
+                &self.record_pdebugdata_stall_tie(),
             )
             .field(
                 "record_pdebugdata_insntype_wsr",
-                &format_args!("{}", self.record_pdebugdata_insntype_wsr().bit()),
+                &self.record_pdebugdata_insntype_wsr(),
             )
             .field(
                 "record_pdebugdata_stall_run",
-                &format_args!("{}", self.record_pdebugdata_stall_run().bit()),
+                &self.record_pdebugdata_stall_run(),
             )
             .field(
                 "record_pdebugdata_insntype_xsr",
-                &format_args!("{}", self.record_pdebugdata_insntype_xsr().bit()),
+                &self.record_pdebugdata_insntype_xsr(),
             )
             .field(
                 "record_pdebugdata_dep_str",
-                &format_args!("{}", self.record_pdebugdata_dep_str().bit()),
-            )
-            .field(
-                "record_pdebugdata_dep",
-                &format_args!("{}", self.record_pdebugdata_dep().bit()),
+                &self.record_pdebugdata_dep_str(),
             )
+            .field("record_pdebugdata_dep", &self.record_pdebugdata_dep())
             .field(
                 "record_pdebugdata_stall_bpifetch",
-                &format_args!("{}", self.record_pdebugdata_stall_bpifetch().bit()),
+                &self.record_pdebugdata_stall_bpifetch(),
             )
             .field(
                 "record_pdebugdata_stall_l32r",
-                &format_args!("{}", self.record_pdebugdata_stall_l32r().bit()),
+                &self.record_pdebugdata_stall_l32r(),
             )
             .field(
                 "record_pdebugdata_stall_lsproc",
-                &format_args!("{}", self.record_pdebugdata_stall_lsproc().bit()),
+                &self.record_pdebugdata_stall_lsproc(),
             )
             .field(
                 "record_pdebugdata_stall_bpload",
-                &format_args!("{}", self.record_pdebugdata_stall_bpload().bit()),
+                &self.record_pdebugdata_stall_bpload(),
             )
             .field(
                 "record_pdebugdata_dep_memw",
-                &format_args!("{}", self.record_pdebugdata_dep_memw().bit()),
+                &self.record_pdebugdata_dep_memw(),
             )
             .field(
                 "record_pdebugdata_exccause",
-                &format_args!("{}", self.record_pdebugdata_exccause().bits()),
+                &self.record_pdebugdata_exccause(),
             )
             .field(
                 "record_pdebugdata_stall_bankconfl",
-                &format_args!("{}", self.record_pdebugdata_stall_bankconfl().bit()),
+                &self.record_pdebugdata_stall_bankconfl(),
             )
             .field(
                 "record_pdebugdata_dep_halt",
-                &format_args!("{}", self.record_pdebugdata_dep_halt().bit()),
+                &self.record_pdebugdata_dep_halt(),
             )
             .field(
                 "record_pdebugdata_stall_itermul",
-                &format_args!("{}", self.record_pdebugdata_stall_itermul().bit()),
+                &self.record_pdebugdata_stall_itermul(),
             )
             .field(
                 "record_pdebugdata_stall_iterdiv",
-                &format_args!("{}", self.record_pdebugdata_stall_iterdiv().bit()),
+                &self.record_pdebugdata_stall_iterdiv(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_RECORD_PDEBUGDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cpu_record_pdebuginst.rs b/esp32/src/dport/pro_cpu_record_pdebuginst.rs
index 7e78c6dd0d..a0655c77fe 100644
--- a/esp32/src/dport/pro_cpu_record_pdebuginst.rs
+++ b/esp32/src/dport/pro_cpu_record_pdebuginst.rs
@@ -60,39 +60,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CPU_RECORD_PDEBUGINST")
-            .field(
-                "record_pro_pdebuginst",
-                &format_args!("{}", self.record_pro_pdebuginst().bits()),
-            )
-            .field(
-                "record_pdebuginst_sz",
-                &format_args!("{}", self.record_pdebuginst_sz().bits()),
-            )
-            .field(
-                "record_pdebuginst_isrc",
-                &format_args!("{}", self.record_pdebuginst_isrc().bits()),
-            )
+            .field("record_pro_pdebuginst", &self.record_pro_pdebuginst())
+            .field("record_pdebuginst_sz", &self.record_pdebuginst_sz())
+            .field("record_pdebuginst_isrc", &self.record_pdebuginst_isrc())
             .field(
                 "record_pdebuginst_loop_rep",
-                &format_args!("{}", self.record_pdebuginst_loop_rep().bit()),
-            )
-            .field(
-                "record_pdebuginst_loop",
-                &format_args!("{}", self.record_pdebuginst_loop().bit()),
-            )
-            .field(
-                "record_pdebuginst_cintl",
-                &format_args!("{}", self.record_pdebuginst_cintl().bits()),
+                &self.record_pdebuginst_loop_rep(),
             )
+            .field("record_pdebuginst_loop", &self.record_pdebuginst_loop())
+            .field("record_pdebuginst_cintl", &self.record_pdebuginst_cintl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_RECORD_PDEBUGINST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cpu_record_pdebugls0addr.rs b/esp32/src/dport/pro_cpu_record_pdebugls0addr.rs
index 3f37efe5fb..c3f1635b75 100644
--- a/esp32/src/dport/pro_cpu_record_pdebugls0addr.rs
+++ b/esp32/src/dport/pro_cpu_record_pdebugls0addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CPU_RECORD_PDEBUGLS0ADDR")
-            .field(
-                "record_pro_pdebugls0addr",
-                &format_args!("{}", self.record_pro_pdebugls0addr().bits()),
-            )
+            .field("record_pro_pdebugls0addr", &self.record_pro_pdebugls0addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_RECORD_PDEBUGLS0ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_cpu_record_pdebugls0addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_CPU_RECORD_PDEBUGLS0ADDR_SPEC;
 impl crate::RegisterSpec for PRO_CPU_RECORD_PDEBUGLS0ADDR_SPEC {
diff --git a/esp32/src/dport/pro_cpu_record_pdebugls0data.rs b/esp32/src/dport/pro_cpu_record_pdebugls0data.rs
index 1cb5859172..7cd4c396e4 100644
--- a/esp32/src/dport/pro_cpu_record_pdebugls0data.rs
+++ b/esp32/src/dport/pro_cpu_record_pdebugls0data.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CPU_RECORD_PDEBUGLS0DATA")
-            .field(
-                "record_pro_pdebugls0data",
-                &format_args!("{}", self.record_pro_pdebugls0data().bits()),
-            )
+            .field("record_pro_pdebugls0data", &self.record_pro_pdebugls0data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_RECORD_PDEBUGLS0DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_cpu_record_pdebugls0data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_CPU_RECORD_PDEBUGLS0DATA_SPEC;
 impl crate::RegisterSpec for PRO_CPU_RECORD_PDEBUGLS0DATA_SPEC {
diff --git a/esp32/src/dport/pro_cpu_record_pdebugls0stat.rs b/esp32/src/dport/pro_cpu_record_pdebugls0stat.rs
index 2af22a3610..1abfd5f157 100644
--- a/esp32/src/dport/pro_cpu_record_pdebugls0stat.rs
+++ b/esp32/src/dport/pro_cpu_record_pdebugls0stat.rs
@@ -105,59 +105,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CPU_RECORD_PDEBUGLS0STAT")
-            .field(
-                "record_pro_pdebugls0stat",
-                &format_args!("{}", self.record_pro_pdebugls0stat().bits()),
-            )
+            .field("record_pro_pdebugls0stat", &self.record_pro_pdebugls0stat())
             .field(
                 "record_pdebugls0stat_type",
-                &format_args!("{}", self.record_pdebugls0stat_type().bits()),
-            )
-            .field(
-                "record_pdebugls0stat_sz",
-                &format_args!("{}", self.record_pdebugls0stat_sz().bits()),
+                &self.record_pdebugls0stat_type(),
             )
+            .field("record_pdebugls0stat_sz", &self.record_pdebugls0stat_sz())
             .field(
                 "record_pdebugls0stat_dtlbm",
-                &format_args!("{}", self.record_pdebugls0stat_dtlbm().bit()),
-            )
-            .field(
-                "record_pdebugls0stat_dcm",
-                &format_args!("{}", self.record_pdebugls0stat_dcm().bit()),
-            )
-            .field(
-                "record_pdebugls0stat_dch",
-                &format_args!("{}", self.record_pdebugls0stat_dch().bit()),
-            )
-            .field(
-                "record_pdebugls0stat_uc",
-                &format_args!("{}", self.record_pdebugls0stat_uc().bit()),
-            )
-            .field(
-                "record_pdebugls0stat_wb",
-                &format_args!("{}", self.record_pdebugls0stat_wb().bit()),
-            )
-            .field(
-                "record_pdebugls0stat_coh",
-                &format_args!("{}", self.record_pdebugls0stat_coh().bit()),
+                &self.record_pdebugls0stat_dtlbm(),
             )
+            .field("record_pdebugls0stat_dcm", &self.record_pdebugls0stat_dcm())
+            .field("record_pdebugls0stat_dch", &self.record_pdebugls0stat_dch())
+            .field("record_pdebugls0stat_uc", &self.record_pdebugls0stat_uc())
+            .field("record_pdebugls0stat_wb", &self.record_pdebugls0stat_wb())
+            .field("record_pdebugls0stat_coh", &self.record_pdebugls0stat_coh())
             .field(
                 "record_pdebugls0stat_stcoh",
-                &format_args!("{}", self.record_pdebugls0stat_stcoh().bits()),
-            )
-            .field(
-                "record_pdebugls0stat_tgt",
-                &format_args!("{}", self.record_pdebugls0stat_tgt().bits()),
+                &self.record_pdebugls0stat_stcoh(),
             )
+            .field("record_pdebugls0stat_tgt", &self.record_pdebugls0stat_tgt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_RECORD_PDEBUGLS0STAT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cpu_record_pdebugpc.rs b/esp32/src/dport/pro_cpu_record_pdebugpc.rs
index d16f622ca7..6c75b85f14 100644
--- a/esp32/src/dport/pro_cpu_record_pdebugpc.rs
+++ b/esp32/src/dport/pro_cpu_record_pdebugpc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CPU_RECORD_PDEBUGPC")
-            .field(
-                "record_pro_pdebugpc",
-                &format_args!("{}", self.record_pro_pdebugpc().bits()),
-            )
+            .field("record_pro_pdebugpc", &self.record_pro_pdebugpc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_RECORD_PDEBUGPC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_cpu_record_pdebugpc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_CPU_RECORD_PDEBUGPC_SPEC;
 impl crate::RegisterSpec for PRO_CPU_RECORD_PDEBUGPC_SPEC {
diff --git a/esp32/src/dport/pro_cpu_record_pdebugstatus.rs b/esp32/src/dport/pro_cpu_record_pdebugstatus.rs
index 1d27a45877..c8c9885e77 100644
--- a/esp32/src/dport/pro_cpu_record_pdebugstatus.rs
+++ b/esp32/src/dport/pro_cpu_record_pdebugstatus.rs
@@ -33,27 +33,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CPU_RECORD_PDEBUGSTATUS")
-            .field(
-                "record_pro_pdebugstatus",
-                &format_args!("{}", self.record_pro_pdebugstatus().bits()),
-            )
+            .field("record_pro_pdebugstatus", &self.record_pro_pdebugstatus())
             .field(
                 "record_pdebugstatus_bbcause",
-                &format_args!("{}", self.record_pdebugstatus_bbcause().bits()),
+                &self.record_pdebugstatus_bbcause(),
             )
             .field(
                 "record_pdebugstatus_insntype",
-                &format_args!("{}", self.record_pdebugstatus_insntype().bits()),
+                &self.record_pdebugstatus_insntype(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_RECORD_PDEBUGSTATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_cpu_record_pid.rs b/esp32/src/dport/pro_cpu_record_pid.rs
index 3c7fdf9b33..5962363d17 100644
--- a/esp32/src/dport/pro_cpu_record_pid.rs
+++ b/esp32/src/dport/pro_cpu_record_pid.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CPU_RECORD_PID")
-            .field(
-                "record_pro_pid",
-                &format_args!("{}", self.record_pro_pid().bits()),
-            )
+            .field("record_pro_pid", &self.record_pro_pid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_RECORD_PID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_cpu_record_pid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_CPU_RECORD_PID_SPEC;
 impl crate::RegisterSpec for PRO_CPU_RECORD_PID_SPEC {
diff --git a/esp32/src/dport/pro_cpu_record_status.rs b/esp32/src/dport/pro_cpu_record_status.rs
index 800e59bf93..2a46016774 100644
--- a/esp32/src/dport/pro_cpu_record_status.rs
+++ b/esp32/src/dport/pro_cpu_record_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CPU_RECORD_STATUS")
-            .field(
-                "pro_cpu_recording",
-                &format_args!("{}", self.pro_cpu_recording().bit()),
-            )
+            .field("pro_cpu_recording", &self.pro_cpu_recording())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_RECORD_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_cpu_record_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_CPU_RECORD_STATUS_SPEC;
 impl crate::RegisterSpec for PRO_CPU_RECORD_STATUS_SPEC {
diff --git a/esp32/src/dport/pro_dcache_dbug0.rs b/esp32/src/dport/pro_dcache_dbug0.rs
index 3c060a21af..99feafa5b7 100644
--- a/esp32/src/dport/pro_dcache_dbug0.rs
+++ b/esp32/src/dport/pro_dcache_dbug0.rs
@@ -73,45 +73,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_DBUG0")
-            .field(
-                "pro_slave_wdata",
-                &format_args!("{}", self.pro_slave_wdata().bit()),
-            )
-            .field(
-                "pro_cache_mmu_ia",
-                &format_args!("{}", self.pro_cache_mmu_ia().bit()),
-            )
-            .field(
-                "pro_cache_ia",
-                &format_args!("{}", self.pro_cache_ia().bits()),
-            )
-            .field(
-                "pro_cache_state",
-                &format_args!("{}", self.pro_cache_state().bits()),
-            )
-            .field(
-                "pro_wr_bak_to_read",
-                &format_args!("{}", self.pro_wr_bak_to_read().bit()),
-            )
-            .field("pro_tx_end", &format_args!("{}", self.pro_tx_end().bit()))
-            .field(
-                "pro_slave_wr",
-                &format_args!("{}", self.pro_slave_wr().bit()),
-            )
-            .field(
-                "pro_slave_wdata_v",
-                &format_args!("{}", self.pro_slave_wdata_v().bit()),
-            )
-            .field("pro_rx_end", &format_args!("{}", self.pro_rx_end().bit()))
+            .field("pro_slave_wdata", &self.pro_slave_wdata())
+            .field("pro_cache_mmu_ia", &self.pro_cache_mmu_ia())
+            .field("pro_cache_ia", &self.pro_cache_ia())
+            .field("pro_cache_state", &self.pro_cache_state())
+            .field("pro_wr_bak_to_read", &self.pro_wr_bak_to_read())
+            .field("pro_tx_end", &self.pro_tx_end())
+            .field("pro_slave_wr", &self.pro_slave_wr())
+            .field("pro_slave_wdata_v", &self.pro_slave_wdata_v())
+            .field("pro_rx_end", &self.pro_rx_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_DBUG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_dcache_dbug1.rs b/esp32/src/dport/pro_dcache_dbug1.rs
index 3d73988fee..f04acf787a 100644
--- a/esp32/src/dport/pro_dcache_dbug1.rs
+++ b/esp32/src/dport/pro_dcache_dbug1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_DBUG1")
-            .field(
-                "pro_ctag_ram_rdata",
-                &format_args!("{}", self.pro_ctag_ram_rdata().bits()),
-            )
+            .field("pro_ctag_ram_rdata", &self.pro_ctag_ram_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_DBUG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_dcache_dbug1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_DCACHE_DBUG1_SPEC;
 impl crate::RegisterSpec for PRO_DCACHE_DBUG1_SPEC {
diff --git a/esp32/src/dport/pro_dcache_dbug2.rs b/esp32/src/dport/pro_dcache_dbug2.rs
index 4cd0684946..ba0bcace01 100644
--- a/esp32/src/dport/pro_dcache_dbug2.rs
+++ b/esp32/src/dport/pro_dcache_dbug2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_DBUG2")
-            .field(
-                "pro_cache_vaddr",
-                &format_args!("{}", self.pro_cache_vaddr().bits()),
-            )
+            .field("pro_cache_vaddr", &self.pro_cache_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_DBUG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_dcache_dbug2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_DCACHE_DBUG2_SPEC;
 impl crate::RegisterSpec for PRO_DCACHE_DBUG2_SPEC {
diff --git a/esp32/src/dport/pro_dcache_dbug3.rs b/esp32/src/dport/pro_dcache_dbug3.rs
index 3e368758d8..f31fcd7493 100644
--- a/esp32/src/dport/pro_dcache_dbug3.rs
+++ b/esp32/src/dport/pro_dcache_dbug3.rs
@@ -83,51 +83,42 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_DBUG3")
-            .field(
-                "pro_mmu_rdata",
-                &format_args!("{}", self.pro_mmu_rdata().bits()),
-            )
+            .field("pro_mmu_rdata", &self.pro_mmu_rdata())
             .field(
                 "pro_cpu_disabled_cache_ia",
-                &format_args!("{}", self.pro_cpu_disabled_cache_ia().bits()),
+                &self.pro_cpu_disabled_cache_ia(),
             )
             .field(
                 "pro_cpu_disabled_cache_ia_opposite",
-                &format_args!("{}", self.pro_cpu_disabled_cache_ia_opposite().bit()),
+                &self.pro_cpu_disabled_cache_ia_opposite(),
             )
             .field(
                 "pro_cpu_disabled_cache_ia_dram1",
-                &format_args!("{}", self.pro_cpu_disabled_cache_ia_dram1().bit()),
+                &self.pro_cpu_disabled_cache_ia_dram1(),
             )
             .field(
                 "pro_cpu_disabled_cache_ia_irom0",
-                &format_args!("{}", self.pro_cpu_disabled_cache_ia_irom0().bit()),
+                &self.pro_cpu_disabled_cache_ia_irom0(),
             )
             .field(
                 "pro_cpu_disabled_cache_ia_iram1",
-                &format_args!("{}", self.pro_cpu_disabled_cache_ia_iram1().bit()),
+                &self.pro_cpu_disabled_cache_ia_iram1(),
             )
             .field(
                 "pro_cpu_disabled_cache_ia_iram0",
-                &format_args!("{}", self.pro_cpu_disabled_cache_ia_iram0().bit()),
+                &self.pro_cpu_disabled_cache_ia_iram0(),
             )
             .field(
                 "pro_cpu_disabled_cache_ia_drom0",
-                &format_args!("{}", self.pro_cpu_disabled_cache_ia_drom0().bit()),
+                &self.pro_cpu_disabled_cache_ia_drom0(),
             )
             .field(
                 "pro_cache_iram0_pid_error",
-                &format_args!("{}", self.pro_cache_iram0_pid_error().bit()),
+                &self.pro_cache_iram0_pid_error(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_DBUG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_dcache_dbug4.rs b/esp32/src/dport/pro_dcache_dbug4.rs
index 9fb6f544c1..935e445bd7 100644
--- a/esp32/src/dport/pro_dcache_dbug4.rs
+++ b/esp32/src/dport/pro_dcache_dbug4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_DBUG4")
-            .field(
-                "pro_dram1addr0_ia",
-                &format_args!("{}", self.pro_dram1addr0_ia().bits()),
-            )
+            .field("pro_dram1addr0_ia", &self.pro_dram1addr0_ia())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_DBUG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_dcache_dbug4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_DCACHE_DBUG4_SPEC;
 impl crate::RegisterSpec for PRO_DCACHE_DBUG4_SPEC {
diff --git a/esp32/src/dport/pro_dcache_dbug5.rs b/esp32/src/dport/pro_dcache_dbug5.rs
index b9c0b97e37..ef8765fd18 100644
--- a/esp32/src/dport/pro_dcache_dbug5.rs
+++ b/esp32/src/dport/pro_dcache_dbug5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_DBUG5")
-            .field(
-                "pro_drom0addr0_ia",
-                &format_args!("{}", self.pro_drom0addr0_ia().bits()),
-            )
+            .field("pro_drom0addr0_ia", &self.pro_drom0addr0_ia())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_DBUG5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_dcache_dbug5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_DCACHE_DBUG5_SPEC;
 impl crate::RegisterSpec for PRO_DCACHE_DBUG5_SPEC {
diff --git a/esp32/src/dport/pro_dcache_dbug6.rs b/esp32/src/dport/pro_dcache_dbug6.rs
index 6c6bb1d406..fb04762978 100644
--- a/esp32/src/dport/pro_dcache_dbug6.rs
+++ b/esp32/src/dport/pro_dcache_dbug6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_DBUG6")
-            .field(
-                "pro_iram0addr_ia",
-                &format_args!("{}", self.pro_iram0addr_ia().bits()),
-            )
+            .field("pro_iram0addr_ia", &self.pro_iram0addr_ia())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_DBUG6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_dcache_dbug6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_DCACHE_DBUG6_SPEC;
 impl crate::RegisterSpec for PRO_DCACHE_DBUG6_SPEC {
diff --git a/esp32/src/dport/pro_dcache_dbug7.rs b/esp32/src/dport/pro_dcache_dbug7.rs
index 6d08e5d34f..e9c006129f 100644
--- a/esp32/src/dport/pro_dcache_dbug7.rs
+++ b/esp32/src/dport/pro_dcache_dbug7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_DBUG7")
-            .field(
-                "pro_iram1addr_ia",
-                &format_args!("{}", self.pro_iram1addr_ia().bits()),
-            )
+            .field("pro_iram1addr_ia", &self.pro_iram1addr_ia())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_DBUG7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_dcache_dbug7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_DCACHE_DBUG7_SPEC;
 impl crate::RegisterSpec for PRO_DCACHE_DBUG7_SPEC {
diff --git a/esp32/src/dport/pro_dcache_dbug8.rs b/esp32/src/dport/pro_dcache_dbug8.rs
index 4b03cdc22a..c85e0a856f 100644
--- a/esp32/src/dport/pro_dcache_dbug8.rs
+++ b/esp32/src/dport/pro_dcache_dbug8.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_DBUG8")
-            .field(
-                "pro_irom0addr_ia",
-                &format_args!("{}", self.pro_irom0addr_ia().bits()),
-            )
+            .field("pro_irom0addr_ia", &self.pro_irom0addr_ia())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_DBUG8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_dcache_dbug8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_DCACHE_DBUG8_SPEC;
 impl crate::RegisterSpec for PRO_DCACHE_DBUG8_SPEC {
diff --git a/esp32/src/dport/pro_dcache_dbug9.rs b/esp32/src/dport/pro_dcache_dbug9.rs
index 672b368b75..9169a2dac6 100644
--- a/esp32/src/dport/pro_dcache_dbug9.rs
+++ b/esp32/src/dport/pro_dcache_dbug9.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_DBUG9")
-            .field(
-                "pro_opsdramaddr_ia",
-                &format_args!("{}", self.pro_opsdramaddr_ia().bits()),
-            )
+            .field("pro_opsdramaddr_ia", &self.pro_opsdramaddr_ia())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_DBUG9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_dcache_dbug9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_DCACHE_DBUG9_SPEC;
 impl crate::RegisterSpec for PRO_DCACHE_DBUG9_SPEC {
diff --git a/esp32/src/dport/pro_dport_apb_mask0.rs b/esp32/src/dport/pro_dport_apb_mask0.rs
index 0f5b62bf92..180603655d 100644
--- a/esp32/src/dport/pro_dport_apb_mask0.rs
+++ b/esp32/src/dport/pro_dport_apb_mask0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DPORT_APB_MASK0")
-            .field(
-                "prodport_apb_mask0",
-                &format_args!("{}", self.prodport_apb_mask0().bits()),
-            )
+            .field("prodport_apb_mask0", &self.prodport_apb_mask0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DPORT_APB_MASK0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_dport_apb_mask1.rs b/esp32/src/dport/pro_dport_apb_mask1.rs
index 7a9797a998..6598fef760 100644
--- a/esp32/src/dport/pro_dport_apb_mask1.rs
+++ b/esp32/src/dport/pro_dport_apb_mask1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DPORT_APB_MASK1")
-            .field(
-                "prodport_apb_mask1",
-                &format_args!("{}", self.prodport_apb_mask1().bits()),
-            )
+            .field("prodport_apb_mask1", &self.prodport_apb_mask1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DPORT_APB_MASK1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_efuse_int_map.rs b/esp32/src/dport/pro_efuse_int_map.rs
index 8b94229032..ade5f6dc2b 100644
--- a/esp32/src/dport/pro_efuse_int_map.rs
+++ b/esp32/src/dport/pro_efuse_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_EFUSE_INT_MAP")
-            .field(
-                "pro_efuse_int_map",
-                &format_args!("{}", self.pro_efuse_int_map().bits()),
-            )
+            .field("pro_efuse_int_map", &self.pro_efuse_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_EFUSE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_emac_int_map.rs b/esp32/src/dport/pro_emac_int_map.rs
index 4ba6325f75..e45c925462 100644
--- a/esp32/src/dport/pro_emac_int_map.rs
+++ b/esp32/src/dport/pro_emac_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_EMAC_INT_MAP")
-            .field(
-                "pro_emac_int_map",
-                &format_args!("{}", self.pro_emac_int_map().bits()),
-            )
+            .field("pro_emac_int_map", &self.pro_emac_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_EMAC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_gpio_interrupt_map.rs b/esp32/src/dport/pro_gpio_interrupt_map.rs
index 3b95a16ad5..ac6dbab08d 100644
--- a/esp32/src/dport/pro_gpio_interrupt_map.rs
+++ b/esp32/src/dport/pro_gpio_interrupt_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_GPIO_INTERRUPT_MAP")
             .field(
                 "pro_gpio_interrupt_pro_map",
-                &format_args!("{}", self.pro_gpio_interrupt_pro_map().bits()),
+                &self.pro_gpio_interrupt_pro_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_GPIO_INTERRUPT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_gpio_interrupt_nmi_map.rs b/esp32/src/dport/pro_gpio_interrupt_nmi_map.rs
index 164746e550..be62c815cf 100644
--- a/esp32/src/dport/pro_gpio_interrupt_nmi_map.rs
+++ b/esp32/src/dport/pro_gpio_interrupt_nmi_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_GPIO_INTERRUPT_NMI_MAP")
             .field(
                 "pro_gpio_interrupt_pro_nmi_map",
-                &format_args!("{}", self.pro_gpio_interrupt_pro_nmi_map().bits()),
+                &self.pro_gpio_interrupt_pro_nmi_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_GPIO_INTERRUPT_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_i2c_ext0_intr_map.rs b/esp32/src/dport/pro_i2c_ext0_intr_map.rs
index d9200ac495..28ee50d17a 100644
--- a/esp32/src/dport/pro_i2c_ext0_intr_map.rs
+++ b/esp32/src/dport/pro_i2c_ext0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_I2C_EXT0_INTR_MAP")
-            .field(
-                "pro_i2c_ext0_intr_map",
-                &format_args!("{}", self.pro_i2c_ext0_intr_map().bits()),
-            )
+            .field("pro_i2c_ext0_intr_map", &self.pro_i2c_ext0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_I2C_EXT0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_i2c_ext1_intr_map.rs b/esp32/src/dport/pro_i2c_ext1_intr_map.rs
index 676e09e3d1..4079fb8cca 100644
--- a/esp32/src/dport/pro_i2c_ext1_intr_map.rs
+++ b/esp32/src/dport/pro_i2c_ext1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_I2C_EXT1_INTR_MAP")
-            .field(
-                "pro_i2c_ext1_intr_map",
-                &format_args!("{}", self.pro_i2c_ext1_intr_map().bits()),
-            )
+            .field("pro_i2c_ext1_intr_map", &self.pro_i2c_ext1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_I2C_EXT1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_i2s0_int_map.rs b/esp32/src/dport/pro_i2s0_int_map.rs
index a4e5cf6529..69e50a1b77 100644
--- a/esp32/src/dport/pro_i2s0_int_map.rs
+++ b/esp32/src/dport/pro_i2s0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_I2S0_INT_MAP")
-            .field(
-                "pro_i2s0_int_map",
-                &format_args!("{}", self.pro_i2s0_int_map().bits()),
-            )
+            .field("pro_i2s0_int_map", &self.pro_i2s0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_I2S0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_i2s1_int_map.rs b/esp32/src/dport/pro_i2s1_int_map.rs
index d32eb54ce2..46c16f6538 100644
--- a/esp32/src/dport/pro_i2s1_int_map.rs
+++ b/esp32/src/dport/pro_i2s1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_I2S1_INT_MAP")
-            .field(
-                "pro_i2s1_int_map",
-                &format_args!("{}", self.pro_i2s1_int_map().bits()),
-            )
+            .field("pro_i2s1_int_map", &self.pro_i2s1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_I2S1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_intr_status_0.rs b/esp32/src/dport/pro_intr_status_0.rs
index 77a41f4368..d7986ebf67 100644
--- a/esp32/src/dport/pro_intr_status_0.rs
+++ b/esp32/src/dport/pro_intr_status_0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_INTR_STATUS_0")
-            .field(
-                "pro_intr_status_0",
-                &format_args!("{}", self.pro_intr_status_0().bits()),
-            )
+            .field("pro_intr_status_0", &self.pro_intr_status_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_INTR_STATUS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_intr_status_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_INTR_STATUS_0_SPEC;
 impl crate::RegisterSpec for PRO_INTR_STATUS_0_SPEC {
diff --git a/esp32/src/dport/pro_intr_status_1.rs b/esp32/src/dport/pro_intr_status_1.rs
index 7a07cdc05b..de1f64f488 100644
--- a/esp32/src/dport/pro_intr_status_1.rs
+++ b/esp32/src/dport/pro_intr_status_1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_INTR_STATUS_1")
-            .field(
-                "pro_intr_status_1",
-                &format_args!("{}", self.pro_intr_status_1().bits()),
-            )
+            .field("pro_intr_status_1", &self.pro_intr_status_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_INTR_STATUS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_intr_status_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_INTR_STATUS_1_SPEC;
 impl crate::RegisterSpec for PRO_INTR_STATUS_1_SPEC {
diff --git a/esp32/src/dport/pro_intr_status_2.rs b/esp32/src/dport/pro_intr_status_2.rs
index e5db18831a..95c9c3f769 100644
--- a/esp32/src/dport/pro_intr_status_2.rs
+++ b/esp32/src/dport/pro_intr_status_2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_INTR_STATUS_2")
-            .field(
-                "pro_intr_status_2",
-                &format_args!("{}", self.pro_intr_status_2().bits()),
-            )
+            .field("pro_intr_status_2", &self.pro_intr_status_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_INTR_STATUS_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_intr_status_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_INTR_STATUS_2_SPEC;
 impl crate::RegisterSpec for PRO_INTR_STATUS_2_SPEC {
diff --git a/esp32/src/dport/pro_intrusion_ctrl.rs b/esp32/src/dport/pro_intrusion_ctrl.rs
index d10db46a6a..dc6182e9f7 100644
--- a/esp32/src/dport/pro_intrusion_ctrl.rs
+++ b/esp32/src/dport/pro_intrusion_ctrl.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_INTRUSION_CTRL")
             .field(
                 "pro_intrusion_record_reset_n",
-                &format_args!("{}", self.pro_intrusion_record_reset_n().bit()),
+                &self.pro_intrusion_record_reset_n(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_INTRUSION_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_intrusion_status.rs b/esp32/src/dport/pro_intrusion_status.rs
index 3bbcbf8464..a2aceba129 100644
--- a/esp32/src/dport/pro_intrusion_status.rs
+++ b/esp32/src/dport/pro_intrusion_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_INTRUSION_STATUS")
-            .field(
-                "pro_intrusion_record",
-                &format_args!("{}", self.pro_intrusion_record().bits()),
-            )
+            .field("pro_intrusion_record", &self.pro_intrusion_record())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_INTRUSION_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_intrusion_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_INTRUSION_STATUS_SPEC;
 impl crate::RegisterSpec for PRO_INTRUSION_STATUS_SPEC {
diff --git a/esp32/src/dport/pro_ledc_int_map.rs b/esp32/src/dport/pro_ledc_int_map.rs
index 567fc3ce10..92b6ebec16 100644
--- a/esp32/src/dport/pro_ledc_int_map.rs
+++ b/esp32/src/dport/pro_ledc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_LEDC_INT_MAP")
-            .field(
-                "pro_ledc_int_map",
-                &format_args!("{}", self.pro_ledc_int_map().bits()),
-            )
+            .field("pro_ledc_int_map", &self.pro_ledc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_LEDC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_mac_intr_map.rs b/esp32/src/dport/pro_mac_intr_map.rs
index da87edec01..7bf7f44abd 100644
--- a/esp32/src/dport/pro_mac_intr_map.rs
+++ b/esp32/src/dport/pro_mac_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_MAC_INTR_MAP")
-            .field(
-                "pro_mac_intr_map",
-                &format_args!("{}", self.pro_mac_intr_map().bits()),
-            )
+            .field("pro_mac_intr_map", &self.pro_mac_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_MAC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_mac_nmi_map.rs b/esp32/src/dport/pro_mac_nmi_map.rs
index e5aabeb454..09010d8648 100644
--- a/esp32/src/dport/pro_mac_nmi_map.rs
+++ b/esp32/src/dport/pro_mac_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_MAC_NMI_MAP")
-            .field(
-                "pro_mac_nmi_map",
-                &format_args!("{}", self.pro_mac_nmi_map().bits()),
-            )
+            .field("pro_mac_nmi_map", &self.pro_mac_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_MAC_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_mmu_ia_int_map.rs b/esp32/src/dport/pro_mmu_ia_int_map.rs
index 30e9e5132d..8111d95c36 100644
--- a/esp32/src/dport/pro_mmu_ia_int_map.rs
+++ b/esp32/src/dport/pro_mmu_ia_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_MMU_IA_INT_MAP")
-            .field(
-                "pro_mmu_ia_int_map",
-                &format_args!("{}", self.pro_mmu_ia_int_map().bits()),
-            )
+            .field("pro_mmu_ia_int_map", &self.pro_mmu_ia_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_MMU_IA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_mpu_ia_int_map.rs b/esp32/src/dport/pro_mpu_ia_int_map.rs
index 7ae599ae39..560c391684 100644
--- a/esp32/src/dport/pro_mpu_ia_int_map.rs
+++ b/esp32/src/dport/pro_mpu_ia_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_MPU_IA_INT_MAP")
-            .field(
-                "pro_mpu_ia_int_map",
-                &format_args!("{}", self.pro_mpu_ia_int_map().bits()),
-            )
+            .field("pro_mpu_ia_int_map", &self.pro_mpu_ia_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_MPU_IA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_pcnt_intr_map.rs b/esp32/src/dport/pro_pcnt_intr_map.rs
index 64b512778e..43b78970f8 100644
--- a/esp32/src/dport/pro_pcnt_intr_map.rs
+++ b/esp32/src/dport/pro_pcnt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_PCNT_INTR_MAP")
-            .field(
-                "pro_pcnt_intr_map",
-                &format_args!("{}", self.pro_pcnt_intr_map().bits()),
-            )
+            .field("pro_pcnt_intr_map", &self.pro_pcnt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PCNT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_pwm0_intr_map.rs b/esp32/src/dport/pro_pwm0_intr_map.rs
index 1709368ae6..38bddc6a5c 100644
--- a/esp32/src/dport/pro_pwm0_intr_map.rs
+++ b/esp32/src/dport/pro_pwm0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_PWM0_INTR_MAP")
-            .field(
-                "pro_pwm0_intr_map",
-                &format_args!("{}", self.pro_pwm0_intr_map().bits()),
-            )
+            .field("pro_pwm0_intr_map", &self.pro_pwm0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PWM0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_pwm1_intr_map.rs b/esp32/src/dport/pro_pwm1_intr_map.rs
index f968677d13..477c72cbfb 100644
--- a/esp32/src/dport/pro_pwm1_intr_map.rs
+++ b/esp32/src/dport/pro_pwm1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_PWM1_INTR_MAP")
-            .field(
-                "pro_pwm1_intr_map",
-                &format_args!("{}", self.pro_pwm1_intr_map().bits()),
-            )
+            .field("pro_pwm1_intr_map", &self.pro_pwm1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PWM1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_pwm2_intr_map.rs b/esp32/src/dport/pro_pwm2_intr_map.rs
index 0a2620326c..75263421aa 100644
--- a/esp32/src/dport/pro_pwm2_intr_map.rs
+++ b/esp32/src/dport/pro_pwm2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_PWM2_INTR_MAP")
-            .field(
-                "pro_pwm2_intr_map",
-                &format_args!("{}", self.pro_pwm2_intr_map().bits()),
-            )
+            .field("pro_pwm2_intr_map", &self.pro_pwm2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PWM2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_pwm3_intr_map.rs b/esp32/src/dport/pro_pwm3_intr_map.rs
index 469caa9041..9e4fd6b42b 100644
--- a/esp32/src/dport/pro_pwm3_intr_map.rs
+++ b/esp32/src/dport/pro_pwm3_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_PWM3_INTR_MAP")
-            .field(
-                "pro_pwm3_intr_map",
-                &format_args!("{}", self.pro_pwm3_intr_map().bits()),
-            )
+            .field("pro_pwm3_intr_map", &self.pro_pwm3_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PWM3_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_rmt_intr_map.rs b/esp32/src/dport/pro_rmt_intr_map.rs
index e77c0f9877..192b9a6a7c 100644
--- a/esp32/src/dport/pro_rmt_intr_map.rs
+++ b/esp32/src/dport/pro_rmt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_RMT_INTR_MAP")
-            .field(
-                "pro_rmt_intr_map",
-                &format_args!("{}", self.pro_rmt_intr_map().bits()),
-            )
+            .field("pro_rmt_intr_map", &self.pro_rmt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_RMT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_rsa_intr_map.rs b/esp32/src/dport/pro_rsa_intr_map.rs
index b2b1de1d1d..c5de83defb 100644
--- a/esp32/src/dport/pro_rsa_intr_map.rs
+++ b/esp32/src/dport/pro_rsa_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_RSA_INTR_MAP")
-            .field(
-                "pro_rsa_intr_map",
-                &format_args!("{}", self.pro_rsa_intr_map().bits()),
-            )
+            .field("pro_rsa_intr_map", &self.pro_rsa_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_RSA_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_rtc_core_intr_map.rs b/esp32/src/dport/pro_rtc_core_intr_map.rs
index 7ac57c8d3d..9ed1c0ab58 100644
--- a/esp32/src/dport/pro_rtc_core_intr_map.rs
+++ b/esp32/src/dport/pro_rtc_core_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_RTC_CORE_INTR_MAP")
-            .field(
-                "pro_rtc_core_intr_map",
-                &format_args!("{}", self.pro_rtc_core_intr_map().bits()),
-            )
+            .field("pro_rtc_core_intr_map", &self.pro_rtc_core_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_RTC_CORE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_rwble_irq_map.rs b/esp32/src/dport/pro_rwble_irq_map.rs
index 4f53dc0da8..bfb7ccf43d 100644
--- a/esp32/src/dport/pro_rwble_irq_map.rs
+++ b/esp32/src/dport/pro_rwble_irq_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_RWBLE_IRQ_MAP")
-            .field(
-                "pro_rwble_irq_map",
-                &format_args!("{}", self.pro_rwble_irq_map().bits()),
-            )
+            .field("pro_rwble_irq_map", &self.pro_rwble_irq_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_RWBLE_IRQ_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_rwble_nmi_map.rs b/esp32/src/dport/pro_rwble_nmi_map.rs
index 888aa1cc1a..1917ccd894 100644
--- a/esp32/src/dport/pro_rwble_nmi_map.rs
+++ b/esp32/src/dport/pro_rwble_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_RWBLE_NMI_MAP")
-            .field(
-                "pro_rwble_nmi_map",
-                &format_args!("{}", self.pro_rwble_nmi_map().bits()),
-            )
+            .field("pro_rwble_nmi_map", &self.pro_rwble_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_RWBLE_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_rwbt_irq_map.rs b/esp32/src/dport/pro_rwbt_irq_map.rs
index 3510dc267e..01d976d3f9 100644
--- a/esp32/src/dport/pro_rwbt_irq_map.rs
+++ b/esp32/src/dport/pro_rwbt_irq_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_RWBT_IRQ_MAP")
-            .field(
-                "pro_rwbt_irq_map",
-                &format_args!("{}", self.pro_rwbt_irq_map().bits()),
-            )
+            .field("pro_rwbt_irq_map", &self.pro_rwbt_irq_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_RWBT_IRQ_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_rwbt_nmi_map.rs b/esp32/src/dport/pro_rwbt_nmi_map.rs
index 1d82895919..f74f4604d4 100644
--- a/esp32/src/dport/pro_rwbt_nmi_map.rs
+++ b/esp32/src/dport/pro_rwbt_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_RWBT_NMI_MAP")
-            .field(
-                "pro_rwbt_nmi_map",
-                &format_args!("{}", self.pro_rwbt_nmi_map().bits()),
-            )
+            .field("pro_rwbt_nmi_map", &self.pro_rwbt_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_RWBT_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_sdio_host_interrupt_map.rs b/esp32/src/dport/pro_sdio_host_interrupt_map.rs
index ae07e0d3d0..e99979e7d9 100644
--- a/esp32/src/dport/pro_sdio_host_interrupt_map.rs
+++ b/esp32/src/dport/pro_sdio_host_interrupt_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_SDIO_HOST_INTERRUPT_MAP")
             .field(
                 "pro_sdio_host_interrupt_map",
-                &format_args!("{}", self.pro_sdio_host_interrupt_map().bits()),
+                &self.pro_sdio_host_interrupt_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SDIO_HOST_INTERRUPT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_slc0_intr_map.rs b/esp32/src/dport/pro_slc0_intr_map.rs
index 86e32f0b93..843165e278 100644
--- a/esp32/src/dport/pro_slc0_intr_map.rs
+++ b/esp32/src/dport/pro_slc0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SLC0_INTR_MAP")
-            .field(
-                "pro_slc0_intr_map",
-                &format_args!("{}", self.pro_slc0_intr_map().bits()),
-            )
+            .field("pro_slc0_intr_map", &self.pro_slc0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SLC0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_slc1_intr_map.rs b/esp32/src/dport/pro_slc1_intr_map.rs
index 6f118d1c69..2ca9ba5866 100644
--- a/esp32/src/dport/pro_slc1_intr_map.rs
+++ b/esp32/src/dport/pro_slc1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SLC1_INTR_MAP")
-            .field(
-                "pro_slc1_intr_map",
-                &format_args!("{}", self.pro_slc1_intr_map().bits()),
-            )
+            .field("pro_slc1_intr_map", &self.pro_slc1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SLC1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_spi1_dma_int_map.rs b/esp32/src/dport/pro_spi1_dma_int_map.rs
index 75c27fc429..21fdcc6054 100644
--- a/esp32/src/dport/pro_spi1_dma_int_map.rs
+++ b/esp32/src/dport/pro_spi1_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SPI1_DMA_INT_MAP")
-            .field(
-                "pro_spi1_dma_int_map",
-                &format_args!("{}", self.pro_spi1_dma_int_map().bits()),
-            )
+            .field("pro_spi1_dma_int_map", &self.pro_spi1_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SPI1_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_spi2_dma_int_map.rs b/esp32/src/dport/pro_spi2_dma_int_map.rs
index 7f93b7214f..d1ee8210f5 100644
--- a/esp32/src/dport/pro_spi2_dma_int_map.rs
+++ b/esp32/src/dport/pro_spi2_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SPI2_DMA_INT_MAP")
-            .field(
-                "pro_spi2_dma_int_map",
-                &format_args!("{}", self.pro_spi2_dma_int_map().bits()),
-            )
+            .field("pro_spi2_dma_int_map", &self.pro_spi2_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SPI2_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_spi3_dma_int_map.rs b/esp32/src/dport/pro_spi3_dma_int_map.rs
index 390d845405..5ee98d6fe8 100644
--- a/esp32/src/dport/pro_spi3_dma_int_map.rs
+++ b/esp32/src/dport/pro_spi3_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SPI3_DMA_INT_MAP")
-            .field(
-                "pro_spi3_dma_int_map",
-                &format_args!("{}", self.pro_spi3_dma_int_map().bits()),
-            )
+            .field("pro_spi3_dma_int_map", &self.pro_spi3_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SPI3_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_spi_intr_0_map.rs b/esp32/src/dport/pro_spi_intr_0_map.rs
index 25d1c11d3f..ff0ce3e80c 100644
--- a/esp32/src/dport/pro_spi_intr_0_map.rs
+++ b/esp32/src/dport/pro_spi_intr_0_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SPI_INTR_0_MAP")
-            .field(
-                "pro_spi_intr_0_map",
-                &format_args!("{}", self.pro_spi_intr_0_map().bits()),
-            )
+            .field("pro_spi_intr_0_map", &self.pro_spi_intr_0_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SPI_INTR_0_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_spi_intr_1_map.rs b/esp32/src/dport/pro_spi_intr_1_map.rs
index f59d8467ec..1f800aef5f 100644
--- a/esp32/src/dport/pro_spi_intr_1_map.rs
+++ b/esp32/src/dport/pro_spi_intr_1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SPI_INTR_1_MAP")
-            .field(
-                "pro_spi_intr_1_map",
-                &format_args!("{}", self.pro_spi_intr_1_map().bits()),
-            )
+            .field("pro_spi_intr_1_map", &self.pro_spi_intr_1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SPI_INTR_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_spi_intr_2_map.rs b/esp32/src/dport/pro_spi_intr_2_map.rs
index e83af6dca1..ddf1eca3ba 100644
--- a/esp32/src/dport/pro_spi_intr_2_map.rs
+++ b/esp32/src/dport/pro_spi_intr_2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SPI_INTR_2_MAP")
-            .field(
-                "pro_spi_intr_2_map",
-                &format_args!("{}", self.pro_spi_intr_2_map().bits()),
-            )
+            .field("pro_spi_intr_2_map", &self.pro_spi_intr_2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SPI_INTR_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_spi_intr_3_map.rs b/esp32/src/dport/pro_spi_intr_3_map.rs
index 2ebf34c12a..7a25e892fe 100644
--- a/esp32/src/dport/pro_spi_intr_3_map.rs
+++ b/esp32/src/dport/pro_spi_intr_3_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SPI_INTR_3_MAP")
-            .field(
-                "pro_spi_intr_3_map",
-                &format_args!("{}", self.pro_spi_intr_3_map().bits()),
-            )
+            .field("pro_spi_intr_3_map", &self.pro_spi_intr_3_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SPI_INTR_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg1_lact_edge_int_map.rs b/esp32/src/dport/pro_tg1_lact_edge_int_map.rs
index a5b7cf773c..7627dadb52 100644
--- a/esp32/src/dport/pro_tg1_lact_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg1_lact_edge_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_TG1_LACT_EDGE_INT_MAP")
             .field(
                 "pro_tg1_lact_edge_int_map",
-                &format_args!("{}", self.pro_tg1_lact_edge_int_map().bits()),
+                &self.pro_tg1_lact_edge_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_LACT_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg1_lact_level_int_map.rs b/esp32/src/dport/pro_tg1_lact_level_int_map.rs
index 01dd4320c8..6f8c167aa1 100644
--- a/esp32/src/dport/pro_tg1_lact_level_int_map.rs
+++ b/esp32/src/dport/pro_tg1_lact_level_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_TG1_LACT_LEVEL_INT_MAP")
             .field(
                 "pro_tg1_lact_level_int_map",
-                &format_args!("{}", self.pro_tg1_lact_level_int_map().bits()),
+                &self.pro_tg1_lact_level_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_LACT_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg1_t0_edge_int_map.rs b/esp32/src/dport/pro_tg1_t0_edge_int_map.rs
index 8fcc3b505d..94349bc04d 100644
--- a/esp32/src/dport/pro_tg1_t0_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg1_t0_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG1_T0_EDGE_INT_MAP")
-            .field(
-                "pro_tg1_t0_edge_int_map",
-                &format_args!("{}", self.pro_tg1_t0_edge_int_map().bits()),
-            )
+            .field("pro_tg1_t0_edge_int_map", &self.pro_tg1_t0_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_T0_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg1_t0_level_int_map.rs b/esp32/src/dport/pro_tg1_t0_level_int_map.rs
index ad56e605f7..4866b9cab8 100644
--- a/esp32/src/dport/pro_tg1_t0_level_int_map.rs
+++ b/esp32/src/dport/pro_tg1_t0_level_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG1_T0_LEVEL_INT_MAP")
-            .field(
-                "pro_tg1_t0_level_int_map",
-                &format_args!("{}", self.pro_tg1_t0_level_int_map().bits()),
-            )
+            .field("pro_tg1_t0_level_int_map", &self.pro_tg1_t0_level_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_T0_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg1_t1_edge_int_map.rs b/esp32/src/dport/pro_tg1_t1_edge_int_map.rs
index f004aaebee..e016907e85 100644
--- a/esp32/src/dport/pro_tg1_t1_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg1_t1_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG1_T1_EDGE_INT_MAP")
-            .field(
-                "pro_tg1_t1_edge_int_map",
-                &format_args!("{}", self.pro_tg1_t1_edge_int_map().bits()),
-            )
+            .field("pro_tg1_t1_edge_int_map", &self.pro_tg1_t1_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_T1_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg1_t1_level_int_map.rs b/esp32/src/dport/pro_tg1_t1_level_int_map.rs
index b33f032b9d..63484fb8f0 100644
--- a/esp32/src/dport/pro_tg1_t1_level_int_map.rs
+++ b/esp32/src/dport/pro_tg1_t1_level_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG1_T1_LEVEL_INT_MAP")
-            .field(
-                "pro_tg1_t1_level_int_map",
-                &format_args!("{}", self.pro_tg1_t1_level_int_map().bits()),
-            )
+            .field("pro_tg1_t1_level_int_map", &self.pro_tg1_t1_level_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_T1_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg1_wdt_edge_int_map.rs b/esp32/src/dport/pro_tg1_wdt_edge_int_map.rs
index 10d7fae8e7..ed7cf7c221 100644
--- a/esp32/src/dport/pro_tg1_wdt_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg1_wdt_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG1_WDT_EDGE_INT_MAP")
-            .field(
-                "pro_tg1_wdt_edge_int_map",
-                &format_args!("{}", self.pro_tg1_wdt_edge_int_map().bits()),
-            )
+            .field("pro_tg1_wdt_edge_int_map", &self.pro_tg1_wdt_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_WDT_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg1_wdt_level_int_map.rs b/esp32/src/dport/pro_tg1_wdt_level_int_map.rs
index bebb847b9c..a7107d5665 100644
--- a/esp32/src/dport/pro_tg1_wdt_level_int_map.rs
+++ b/esp32/src/dport/pro_tg1_wdt_level_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_TG1_WDT_LEVEL_INT_MAP")
             .field(
                 "pro_tg1_wdt_level_int_map",
-                &format_args!("{}", self.pro_tg1_wdt_level_int_map().bits()),
+                &self.pro_tg1_wdt_level_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_WDT_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg_lact_edge_int_map.rs b/esp32/src/dport/pro_tg_lact_edge_int_map.rs
index a5ddb41a4e..836430cc05 100644
--- a/esp32/src/dport/pro_tg_lact_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg_lact_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG_LACT_EDGE_INT_MAP")
-            .field(
-                "pro_tg_lact_edge_int_map",
-                &format_args!("{}", self.pro_tg_lact_edge_int_map().bits()),
-            )
+            .field("pro_tg_lact_edge_int_map", &self.pro_tg_lact_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_LACT_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg_lact_level_int_map.rs b/esp32/src/dport/pro_tg_lact_level_int_map.rs
index b8847b451a..928a7a6a46 100644
--- a/esp32/src/dport/pro_tg_lact_level_int_map.rs
+++ b/esp32/src/dport/pro_tg_lact_level_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_TG_LACT_LEVEL_INT_MAP")
             .field(
                 "pro_tg_lact_level_int_map",
-                &format_args!("{}", self.pro_tg_lact_level_int_map().bits()),
+                &self.pro_tg_lact_level_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_LACT_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg_t0_edge_int_map.rs b/esp32/src/dport/pro_tg_t0_edge_int_map.rs
index bbd6d2a485..22d1430914 100644
--- a/esp32/src/dport/pro_tg_t0_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg_t0_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG_T0_EDGE_INT_MAP")
-            .field(
-                "pro_tg_t0_edge_int_map",
-                &format_args!("{}", self.pro_tg_t0_edge_int_map().bits()),
-            )
+            .field("pro_tg_t0_edge_int_map", &self.pro_tg_t0_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_T0_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg_t0_level_int_map.rs b/esp32/src/dport/pro_tg_t0_level_int_map.rs
index 8d53d7d65b..67f7813ab2 100644
--- a/esp32/src/dport/pro_tg_t0_level_int_map.rs
+++ b/esp32/src/dport/pro_tg_t0_level_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG_T0_LEVEL_INT_MAP")
-            .field(
-                "pro_tg_t0_level_int_map",
-                &format_args!("{}", self.pro_tg_t0_level_int_map().bits()),
-            )
+            .field("pro_tg_t0_level_int_map", &self.pro_tg_t0_level_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_T0_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg_t1_edge_int_map.rs b/esp32/src/dport/pro_tg_t1_edge_int_map.rs
index 5ffa627a1d..7f5b10e4c7 100644
--- a/esp32/src/dport/pro_tg_t1_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg_t1_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG_T1_EDGE_INT_MAP")
-            .field(
-                "pro_tg_t1_edge_int_map",
-                &format_args!("{}", self.pro_tg_t1_edge_int_map().bits()),
-            )
+            .field("pro_tg_t1_edge_int_map", &self.pro_tg_t1_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_T1_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg_t1_level_int_map.rs b/esp32/src/dport/pro_tg_t1_level_int_map.rs
index aba25125b0..81df61a3db 100644
--- a/esp32/src/dport/pro_tg_t1_level_int_map.rs
+++ b/esp32/src/dport/pro_tg_t1_level_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG_T1_LEVEL_INT_MAP")
-            .field(
-                "pro_tg_t1_level_int_map",
-                &format_args!("{}", self.pro_tg_t1_level_int_map().bits()),
-            )
+            .field("pro_tg_t1_level_int_map", &self.pro_tg_t1_level_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_T1_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg_wdt_edge_int_map.rs b/esp32/src/dport/pro_tg_wdt_edge_int_map.rs
index f11c393bb7..24fa9e9d31 100644
--- a/esp32/src/dport/pro_tg_wdt_edge_int_map.rs
+++ b/esp32/src/dport/pro_tg_wdt_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG_WDT_EDGE_INT_MAP")
-            .field(
-                "pro_tg_wdt_edge_int_map",
-                &format_args!("{}", self.pro_tg_wdt_edge_int_map().bits()),
-            )
+            .field("pro_tg_wdt_edge_int_map", &self.pro_tg_wdt_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_WDT_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tg_wdt_level_int_map.rs b/esp32/src/dport/pro_tg_wdt_level_int_map.rs
index a401a7946e..bbc79dbfd4 100644
--- a/esp32/src/dport/pro_tg_wdt_level_int_map.rs
+++ b/esp32/src/dport/pro_tg_wdt_level_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG_WDT_LEVEL_INT_MAP")
-            .field(
-                "pro_tg_wdt_level_int_map",
-                &format_args!("{}", self.pro_tg_wdt_level_int_map().bits()),
-            )
+            .field("pro_tg_wdt_level_int_map", &self.pro_tg_wdt_level_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_WDT_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_timer_int1_map.rs b/esp32/src/dport/pro_timer_int1_map.rs
index 30097ad4aa..88fa3ff055 100644
--- a/esp32/src/dport/pro_timer_int1_map.rs
+++ b/esp32/src/dport/pro_timer_int1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TIMER_INT1_MAP")
-            .field(
-                "pro_timer_int1_map",
-                &format_args!("{}", self.pro_timer_int1_map().bits()),
-            )
+            .field("pro_timer_int1_map", &self.pro_timer_int1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TIMER_INT1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_timer_int2_map.rs b/esp32/src/dport/pro_timer_int2_map.rs
index a585966d05..7e68ca02e2 100644
--- a/esp32/src/dport/pro_timer_int2_map.rs
+++ b/esp32/src/dport/pro_timer_int2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TIMER_INT2_MAP")
-            .field(
-                "pro_timer_int2_map",
-                &format_args!("{}", self.pro_timer_int2_map().bits()),
-            )
+            .field("pro_timer_int2_map", &self.pro_timer_int2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TIMER_INT2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_tracemem_ena.rs b/esp32/src/dport/pro_tracemem_ena.rs
index 6041c0c43e..b1ec20db1a 100644
--- a/esp32/src/dport/pro_tracemem_ena.rs
+++ b/esp32/src/dport/pro_tracemem_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TRACEMEM_ENA")
-            .field(
-                "pro_tracemem_ena",
-                &format_args!("{}", self.pro_tracemem_ena().bit()),
-            )
+            .field("pro_tracemem_ena", &self.pro_tracemem_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TRACEMEM_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_uart1_intr_map.rs b/esp32/src/dport/pro_uart1_intr_map.rs
index ac8be7a3df..e6035a11fb 100644
--- a/esp32/src/dport/pro_uart1_intr_map.rs
+++ b/esp32/src/dport/pro_uart1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_UART1_INTR_MAP")
-            .field(
-                "pro_uart1_intr_map",
-                &format_args!("{}", self.pro_uart1_intr_map().bits()),
-            )
+            .field("pro_uart1_intr_map", &self.pro_uart1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_UART1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_uart2_intr_map.rs b/esp32/src/dport/pro_uart2_intr_map.rs
index 477ef8bed3..0403447b41 100644
--- a/esp32/src/dport/pro_uart2_intr_map.rs
+++ b/esp32/src/dport/pro_uart2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_UART2_INTR_MAP")
-            .field(
-                "pro_uart2_intr_map",
-                &format_args!("{}", self.pro_uart2_intr_map().bits()),
-            )
+            .field("pro_uart2_intr_map", &self.pro_uart2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_UART2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_uart_intr_map.rs b/esp32/src/dport/pro_uart_intr_map.rs
index 7c6030bd4a..52dc91e022 100644
--- a/esp32/src/dport/pro_uart_intr_map.rs
+++ b/esp32/src/dport/pro_uart_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_UART_INTR_MAP")
-            .field(
-                "pro_uart_intr_map",
-                &format_args!("{}", self.pro_uart_intr_map().bits()),
-            )
+            .field("pro_uart_intr_map", &self.pro_uart_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_UART_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_uhci0_intr_map.rs b/esp32/src/dport/pro_uhci0_intr_map.rs
index 7fecc7dc55..6b743811ec 100644
--- a/esp32/src/dport/pro_uhci0_intr_map.rs
+++ b/esp32/src/dport/pro_uhci0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_UHCI0_INTR_MAP")
-            .field(
-                "pro_uhci0_intr_map",
-                &format_args!("{}", self.pro_uhci0_intr_map().bits()),
-            )
+            .field("pro_uhci0_intr_map", &self.pro_uhci0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_UHCI0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_uhci1_intr_map.rs b/esp32/src/dport/pro_uhci1_intr_map.rs
index ccc59443c0..0e5f9cd83b 100644
--- a/esp32/src/dport/pro_uhci1_intr_map.rs
+++ b/esp32/src/dport/pro_uhci1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_UHCI1_INTR_MAP")
-            .field(
-                "pro_uhci1_intr_map",
-                &format_args!("{}", self.pro_uhci1_intr_map().bits()),
-            )
+            .field("pro_uhci1_intr_map", &self.pro_uhci1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_UHCI1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_vecbase_ctrl.rs b/esp32/src/dport/pro_vecbase_ctrl.rs
index 124b3e7ba5..0fea6da47e 100644
--- a/esp32/src/dport/pro_vecbase_ctrl.rs
+++ b/esp32/src/dport/pro_vecbase_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_VECBASE_CTRL")
-            .field(
-                "pro_out_vecbase_sel",
-                &format_args!("{}", self.pro_out_vecbase_sel().bits()),
-            )
+            .field("pro_out_vecbase_sel", &self.pro_out_vecbase_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_VECBASE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_vecbase_set.rs b/esp32/src/dport/pro_vecbase_set.rs
index 998c114bc2..7086b7c9cc 100644
--- a/esp32/src/dport/pro_vecbase_set.rs
+++ b/esp32/src/dport/pro_vecbase_set.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_VECBASE_SET")
-            .field(
-                "pro_out_vecbase",
-                &format_args!("{}", self.pro_out_vecbase().bits()),
-            )
+            .field("pro_out_vecbase", &self.pro_out_vecbase())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_VECBASE_SET_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21"]
     #[inline(always)]
diff --git a/esp32/src/dport/pro_wdg_int_map.rs b/esp32/src/dport/pro_wdg_int_map.rs
index 1b8d341293..21ef872cab 100644
--- a/esp32/src/dport/pro_wdg_int_map.rs
+++ b/esp32/src/dport/pro_wdg_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_WDG_INT_MAP")
-            .field(
-                "pro_wdg_int_map",
-                &format_args!("{}", self.pro_wdg_int_map().bits()),
-            )
+            .field("pro_wdg_int_map", &self.pro_wdg_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_WDG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/dport/rom_fo_ctrl.rs b/esp32/src/dport/rom_fo_ctrl.rs
index c175a5e79d..a52b4a8571 100644
--- a/esp32/src/dport/rom_fo_ctrl.rs
+++ b/esp32/src/dport/rom_fo_ctrl.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_FO_CTRL")
-            .field("pro_rom_fo", &format_args!("{}", self.pro_rom_fo().bit()))
-            .field("app_rom_fo", &format_args!("{}", self.app_rom_fo().bit()))
-            .field(
-                "share_rom_fo",
-                &format_args!("{}", self.share_rom_fo().bits()),
-            )
+            .field("pro_rom_fo", &self.pro_rom_fo())
+            .field("app_rom_fo", &self.app_rom_fo())
+            .field("share_rom_fo", &self.share_rom_fo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_FO_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/rom_mpu_ena.rs b/esp32/src/dport/rom_mpu_ena.rs
index 085d38d1ef..ce8645fb02 100644
--- a/esp32/src/dport/rom_mpu_ena.rs
+++ b/esp32/src/dport/rom_mpu_ena.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_MPU_ENA")
-            .field(
-                "share_rom_mpu_ena",
-                &format_args!("{}", self.share_rom_mpu_ena().bit()),
-            )
-            .field(
-                "pro_rom_mpu_ena",
-                &format_args!("{}", self.pro_rom_mpu_ena().bit()),
-            )
-            .field(
-                "app_rom_mpu_ena",
-                &format_args!("{}", self.app_rom_mpu_ena().bit()),
-            )
+            .field("share_rom_mpu_ena", &self.share_rom_mpu_ena())
+            .field("pro_rom_mpu_ena", &self.pro_rom_mpu_ena())
+            .field("app_rom_mpu_ena", &self.app_rom_mpu_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_MPU_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/rom_mpu_table0.rs b/esp32/src/dport/rom_mpu_table0.rs
index a46587d3b1..00ecfd2b00 100644
--- a/esp32/src/dport/rom_mpu_table0.rs
+++ b/esp32/src/dport/rom_mpu_table0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_MPU_TABLE0")
-            .field(
-                "rom_mpu_table0",
-                &format_args!("{}", self.rom_mpu_table0().bits()),
-            )
+            .field("rom_mpu_table0", &self.rom_mpu_table0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_MPU_TABLE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/rom_mpu_table1.rs b/esp32/src/dport/rom_mpu_table1.rs
index b3aa010ad8..e3c7f8bfa8 100644
--- a/esp32/src/dport/rom_mpu_table1.rs
+++ b/esp32/src/dport/rom_mpu_table1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_MPU_TABLE1")
-            .field(
-                "rom_mpu_table1",
-                &format_args!("{}", self.rom_mpu_table1().bits()),
-            )
+            .field("rom_mpu_table1", &self.rom_mpu_table1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_MPU_TABLE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/rom_mpu_table2.rs b/esp32/src/dport/rom_mpu_table2.rs
index 80a15926e3..fe05caefbc 100644
--- a/esp32/src/dport/rom_mpu_table2.rs
+++ b/esp32/src/dport/rom_mpu_table2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_MPU_TABLE2")
-            .field(
-                "rom_mpu_table2",
-                &format_args!("{}", self.rom_mpu_table2().bits()),
-            )
+            .field("rom_mpu_table2", &self.rom_mpu_table2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_MPU_TABLE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/rom_mpu_table3.rs b/esp32/src/dport/rom_mpu_table3.rs
index a77f5154ce..c993ddd093 100644
--- a/esp32/src/dport/rom_mpu_table3.rs
+++ b/esp32/src/dport/rom_mpu_table3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_MPU_TABLE3")
-            .field(
-                "rom_mpu_table3",
-                &format_args!("{}", self.rom_mpu_table3().bits()),
-            )
+            .field("rom_mpu_table3", &self.rom_mpu_table3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_MPU_TABLE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/rom_pd_ctrl.rs b/esp32/src/dport/rom_pd_ctrl.rs
index 354d6c4d51..99b925a250 100644
--- a/esp32/src/dport/rom_pd_ctrl.rs
+++ b/esp32/src/dport/rom_pd_ctrl.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_PD_CTRL")
-            .field("pro_rom_pd", &format_args!("{}", self.pro_rom_pd().bit()))
-            .field("app_rom_pd", &format_args!("{}", self.app_rom_pd().bit()))
-            .field(
-                "share_rom_pd",
-                &format_args!("{}", self.share_rom_pd().bits()),
-            )
+            .field("pro_rom_pd", &self.pro_rom_pd())
+            .field("app_rom_pd", &self.app_rom_pd())
+            .field("share_rom_pd", &self.share_rom_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/rsa_pd_ctrl.rs b/esp32/src/dport/rsa_pd_ctrl.rs
index 7f0fe4727f..9ebd503f4c 100644
--- a/esp32/src/dport/rsa_pd_ctrl.rs
+++ b/esp32/src/dport/rsa_pd_ctrl.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_PD_CTRL")
-            .field("rsa_pd", &format_args!("{}", self.rsa_pd().bit()))
+            .field("rsa_pd", &self.rsa_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/secure_boot_ctrl.rs b/esp32/src/dport/secure_boot_ctrl.rs
index 749161afa7..a05237774f 100644
--- a/esp32/src/dport/secure_boot_ctrl.rs
+++ b/esp32/src/dport/secure_boot_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SECURE_BOOT_CTRL")
-            .field(
-                "sw_bootloader_sel",
-                &format_args!("{}", self.sw_bootloader_sel().bit()),
-            )
+            .field("sw_bootloader_sel", &self.sw_bootloader_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SECURE_BOOT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table0.rs b/esp32/src/dport/shrom_mpu_table0.rs
index a0694c6b6f..c0f1637006 100644
--- a/esp32/src/dport/shrom_mpu_table0.rs
+++ b/esp32/src/dport/shrom_mpu_table0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE0")
-            .field(
-                "shrom_mpu_table0",
-                &format_args!("{}", self.shrom_mpu_table0().bits()),
-            )
+            .field("shrom_mpu_table0", &self.shrom_mpu_table0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table1.rs b/esp32/src/dport/shrom_mpu_table1.rs
index bbf723ccc6..ac9c8c678b 100644
--- a/esp32/src/dport/shrom_mpu_table1.rs
+++ b/esp32/src/dport/shrom_mpu_table1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE1")
-            .field(
-                "shrom_mpu_table1",
-                &format_args!("{}", self.shrom_mpu_table1().bits()),
-            )
+            .field("shrom_mpu_table1", &self.shrom_mpu_table1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table10.rs b/esp32/src/dport/shrom_mpu_table10.rs
index c2512d6f5b..950c829551 100644
--- a/esp32/src/dport/shrom_mpu_table10.rs
+++ b/esp32/src/dport/shrom_mpu_table10.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE10")
-            .field(
-                "shrom_mpu_table10",
-                &format_args!("{}", self.shrom_mpu_table10().bits()),
-            )
+            .field("shrom_mpu_table10", &self.shrom_mpu_table10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table11.rs b/esp32/src/dport/shrom_mpu_table11.rs
index 89b2e0b8dd..e76ffbea34 100644
--- a/esp32/src/dport/shrom_mpu_table11.rs
+++ b/esp32/src/dport/shrom_mpu_table11.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE11")
-            .field(
-                "shrom_mpu_table11",
-                &format_args!("{}", self.shrom_mpu_table11().bits()),
-            )
+            .field("shrom_mpu_table11", &self.shrom_mpu_table11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table12.rs b/esp32/src/dport/shrom_mpu_table12.rs
index 7f8f55cfee..51a0d140be 100644
--- a/esp32/src/dport/shrom_mpu_table12.rs
+++ b/esp32/src/dport/shrom_mpu_table12.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE12")
-            .field(
-                "shrom_mpu_table12",
-                &format_args!("{}", self.shrom_mpu_table12().bits()),
-            )
+            .field("shrom_mpu_table12", &self.shrom_mpu_table12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table13.rs b/esp32/src/dport/shrom_mpu_table13.rs
index 613cdfc3f0..b1656cebd2 100644
--- a/esp32/src/dport/shrom_mpu_table13.rs
+++ b/esp32/src/dport/shrom_mpu_table13.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE13")
-            .field(
-                "shrom_mpu_table13",
-                &format_args!("{}", self.shrom_mpu_table13().bits()),
-            )
+            .field("shrom_mpu_table13", &self.shrom_mpu_table13())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table14.rs b/esp32/src/dport/shrom_mpu_table14.rs
index bcb4a49f79..6f863666e2 100644
--- a/esp32/src/dport/shrom_mpu_table14.rs
+++ b/esp32/src/dport/shrom_mpu_table14.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE14")
-            .field(
-                "shrom_mpu_table14",
-                &format_args!("{}", self.shrom_mpu_table14().bits()),
-            )
+            .field("shrom_mpu_table14", &self.shrom_mpu_table14())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table15.rs b/esp32/src/dport/shrom_mpu_table15.rs
index 7fbba0258e..151901ca2b 100644
--- a/esp32/src/dport/shrom_mpu_table15.rs
+++ b/esp32/src/dport/shrom_mpu_table15.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE15")
-            .field(
-                "shrom_mpu_table15",
-                &format_args!("{}", self.shrom_mpu_table15().bits()),
-            )
+            .field("shrom_mpu_table15", &self.shrom_mpu_table15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table16.rs b/esp32/src/dport/shrom_mpu_table16.rs
index 13b4a2eac2..977e814548 100644
--- a/esp32/src/dport/shrom_mpu_table16.rs
+++ b/esp32/src/dport/shrom_mpu_table16.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE16")
-            .field(
-                "shrom_mpu_table16",
-                &format_args!("{}", self.shrom_mpu_table16().bits()),
-            )
+            .field("shrom_mpu_table16", &self.shrom_mpu_table16())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE16_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table17.rs b/esp32/src/dport/shrom_mpu_table17.rs
index 6b7893ce98..64dcb27a0e 100644
--- a/esp32/src/dport/shrom_mpu_table17.rs
+++ b/esp32/src/dport/shrom_mpu_table17.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE17")
-            .field(
-                "shrom_mpu_table17",
-                &format_args!("{}", self.shrom_mpu_table17().bits()),
-            )
+            .field("shrom_mpu_table17", &self.shrom_mpu_table17())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE17_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table18.rs b/esp32/src/dport/shrom_mpu_table18.rs
index 1daa185b4b..a9fed8e9ed 100644
--- a/esp32/src/dport/shrom_mpu_table18.rs
+++ b/esp32/src/dport/shrom_mpu_table18.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE18")
-            .field(
-                "shrom_mpu_table18",
-                &format_args!("{}", self.shrom_mpu_table18().bits()),
-            )
+            .field("shrom_mpu_table18", &self.shrom_mpu_table18())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE18_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table19.rs b/esp32/src/dport/shrom_mpu_table19.rs
index e718fb961a..36d6b06fe0 100644
--- a/esp32/src/dport/shrom_mpu_table19.rs
+++ b/esp32/src/dport/shrom_mpu_table19.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE19")
-            .field(
-                "shrom_mpu_table19",
-                &format_args!("{}", self.shrom_mpu_table19().bits()),
-            )
+            .field("shrom_mpu_table19", &self.shrom_mpu_table19())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE19_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table2.rs b/esp32/src/dport/shrom_mpu_table2.rs
index cd5d951315..754442e17d 100644
--- a/esp32/src/dport/shrom_mpu_table2.rs
+++ b/esp32/src/dport/shrom_mpu_table2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE2")
-            .field(
-                "shrom_mpu_table2",
-                &format_args!("{}", self.shrom_mpu_table2().bits()),
-            )
+            .field("shrom_mpu_table2", &self.shrom_mpu_table2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table20.rs b/esp32/src/dport/shrom_mpu_table20.rs
index 0b7fbabad5..70455ccfcd 100644
--- a/esp32/src/dport/shrom_mpu_table20.rs
+++ b/esp32/src/dport/shrom_mpu_table20.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE20")
-            .field(
-                "shrom_mpu_table20",
-                &format_args!("{}", self.shrom_mpu_table20().bits()),
-            )
+            .field("shrom_mpu_table20", &self.shrom_mpu_table20())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE20_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table21.rs b/esp32/src/dport/shrom_mpu_table21.rs
index 3d48d589e6..86decfd8f0 100644
--- a/esp32/src/dport/shrom_mpu_table21.rs
+++ b/esp32/src/dport/shrom_mpu_table21.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE21")
-            .field(
-                "shrom_mpu_table21",
-                &format_args!("{}", self.shrom_mpu_table21().bits()),
-            )
+            .field("shrom_mpu_table21", &self.shrom_mpu_table21())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE21_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table22.rs b/esp32/src/dport/shrom_mpu_table22.rs
index d6309f3d09..2798bda6ac 100644
--- a/esp32/src/dport/shrom_mpu_table22.rs
+++ b/esp32/src/dport/shrom_mpu_table22.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE22")
-            .field(
-                "shrom_mpu_table22",
-                &format_args!("{}", self.shrom_mpu_table22().bits()),
-            )
+            .field("shrom_mpu_table22", &self.shrom_mpu_table22())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE22_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table23.rs b/esp32/src/dport/shrom_mpu_table23.rs
index ff6045c3d7..ee9a1991ce 100644
--- a/esp32/src/dport/shrom_mpu_table23.rs
+++ b/esp32/src/dport/shrom_mpu_table23.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE23")
-            .field(
-                "shrom_mpu_table23",
-                &format_args!("{}", self.shrom_mpu_table23().bits()),
-            )
+            .field("shrom_mpu_table23", &self.shrom_mpu_table23())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE23_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table3.rs b/esp32/src/dport/shrom_mpu_table3.rs
index bb26c9e620..698640c932 100644
--- a/esp32/src/dport/shrom_mpu_table3.rs
+++ b/esp32/src/dport/shrom_mpu_table3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE3")
-            .field(
-                "shrom_mpu_table3",
-                &format_args!("{}", self.shrom_mpu_table3().bits()),
-            )
+            .field("shrom_mpu_table3", &self.shrom_mpu_table3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table4.rs b/esp32/src/dport/shrom_mpu_table4.rs
index f491a76636..0eb23673d4 100644
--- a/esp32/src/dport/shrom_mpu_table4.rs
+++ b/esp32/src/dport/shrom_mpu_table4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE4")
-            .field(
-                "shrom_mpu_table4",
-                &format_args!("{}", self.shrom_mpu_table4().bits()),
-            )
+            .field("shrom_mpu_table4", &self.shrom_mpu_table4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table5.rs b/esp32/src/dport/shrom_mpu_table5.rs
index e1b8483311..7e93a7cc03 100644
--- a/esp32/src/dport/shrom_mpu_table5.rs
+++ b/esp32/src/dport/shrom_mpu_table5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE5")
-            .field(
-                "shrom_mpu_table5",
-                &format_args!("{}", self.shrom_mpu_table5().bits()),
-            )
+            .field("shrom_mpu_table5", &self.shrom_mpu_table5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table6.rs b/esp32/src/dport/shrom_mpu_table6.rs
index cdac5b220b..201945084e 100644
--- a/esp32/src/dport/shrom_mpu_table6.rs
+++ b/esp32/src/dport/shrom_mpu_table6.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE6")
-            .field(
-                "shrom_mpu_table6",
-                &format_args!("{}", self.shrom_mpu_table6().bits()),
-            )
+            .field("shrom_mpu_table6", &self.shrom_mpu_table6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table7.rs b/esp32/src/dport/shrom_mpu_table7.rs
index 1101c80327..1c769f54e6 100644
--- a/esp32/src/dport/shrom_mpu_table7.rs
+++ b/esp32/src/dport/shrom_mpu_table7.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE7")
-            .field(
-                "shrom_mpu_table7",
-                &format_args!("{}", self.shrom_mpu_table7().bits()),
-            )
+            .field("shrom_mpu_table7", &self.shrom_mpu_table7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table8.rs b/esp32/src/dport/shrom_mpu_table8.rs
index 74af111c82..7d80a62d48 100644
--- a/esp32/src/dport/shrom_mpu_table8.rs
+++ b/esp32/src/dport/shrom_mpu_table8.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE8")
-            .field(
-                "shrom_mpu_table8",
-                &format_args!("{}", self.shrom_mpu_table8().bits()),
-            )
+            .field("shrom_mpu_table8", &self.shrom_mpu_table8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/shrom_mpu_table9.rs b/esp32/src/dport/shrom_mpu_table9.rs
index 9c7452d392..389aeeedeb 100644
--- a/esp32/src/dport/shrom_mpu_table9.rs
+++ b/esp32/src/dport/shrom_mpu_table9.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHROM_MPU_TABLE9")
-            .field(
-                "shrom_mpu_table9",
-                &format_args!("{}", self.shrom_mpu_table9().bits()),
-            )
+            .field("shrom_mpu_table9", &self.shrom_mpu_table9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHROM_MPU_TABLE9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/slave_spi_config.rs b/esp32/src/dport/slave_spi_config.rs
index 16acb65bb7..eacf856b92 100644
--- a/esp32/src/dport/slave_spi_config.rs
+++ b/esp32/src/dport/slave_spi_config.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE_SPI_CONFIG")
-            .field(
-                "slave_spi_mask_pro",
-                &format_args!("{}", self.slave_spi_mask_pro().bit()),
-            )
-            .field(
-                "slave_spi_mask_app",
-                &format_args!("{}", self.slave_spi_mask_app().bit()),
-            )
-            .field(
-                "spi_encrypt_enable",
-                &format_args!("{}", self.spi_encrypt_enable().bit()),
-            )
-            .field(
-                "spi_decrypt_enable",
-                &format_args!("{}", self.spi_decrypt_enable().bit()),
-            )
+            .field("slave_spi_mask_pro", &self.slave_spi_mask_pro())
+            .field("slave_spi_mask_app", &self.slave_spi_mask_app())
+            .field("spi_encrypt_enable", &self.spi_encrypt_enable())
+            .field("spi_decrypt_enable", &self.spi_decrypt_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_SPI_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/spi_dma_chan_sel.rs b/esp32/src/dport/spi_dma_chan_sel.rs
index c7c2480d06..07a4c3dee0 100644
--- a/esp32/src/dport/spi_dma_chan_sel.rs
+++ b/esp32/src/dport/spi_dma_chan_sel.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_DMA_CHAN_SEL")
-            .field(
-                "spi1_dma_chan_sel",
-                &format_args!("{}", self.spi1_dma_chan_sel().bits()),
-            )
-            .field(
-                "spi2_dma_chan_sel",
-                &format_args!("{}", self.spi2_dma_chan_sel().bits()),
-            )
-            .field(
-                "spi3_dma_chan_sel",
-                &format_args!("{}", self.spi3_dma_chan_sel().bits()),
-            )
+            .field("spi1_dma_chan_sel", &self.spi1_dma_chan_sel())
+            .field("spi2_dma_chan_sel", &self.spi2_dma_chan_sel())
+            .field("spi3_dma_chan_sel", &self.spi3_dma_chan_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_DMA_CHAN_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/sram_fo_ctrl_0.rs b/esp32/src/dport/sram_fo_ctrl_0.rs
index 6b3bdd7568..29976d172c 100644
--- a/esp32/src/dport/sram_fo_ctrl_0.rs
+++ b/esp32/src/dport/sram_fo_ctrl_0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_FO_CTRL_0")
-            .field("sram_fo_0", &format_args!("{}", self.sram_fo_0().bits()))
+            .field("sram_fo_0", &self.sram_fo_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_FO_CTRL_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/dport/sram_fo_ctrl_1.rs b/esp32/src/dport/sram_fo_ctrl_1.rs
index d06a48c751..3ccd06fa10 100644
--- a/esp32/src/dport/sram_fo_ctrl_1.rs
+++ b/esp32/src/dport/sram_fo_ctrl_1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_FO_CTRL_1")
-            .field("sram_fo_1", &format_args!("{}", self.sram_fo_1().bit()))
+            .field("sram_fo_1", &self.sram_fo_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_FO_CTRL_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/sram_pd_ctrl_0.rs b/esp32/src/dport/sram_pd_ctrl_0.rs
index 04bc6e9f2f..2f19af8941 100644
--- a/esp32/src/dport/sram_pd_ctrl_0.rs
+++ b/esp32/src/dport/sram_pd_ctrl_0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_PD_CTRL_0")
-            .field("sram_pd_0", &format_args!("{}", self.sram_pd_0().bits()))
+            .field("sram_pd_0", &self.sram_pd_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_PD_CTRL_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/dport/sram_pd_ctrl_1.rs b/esp32/src/dport/sram_pd_ctrl_1.rs
index 3155617784..d91ca1f51f 100644
--- a/esp32/src/dport/sram_pd_ctrl_1.rs
+++ b/esp32/src/dport/sram_pd_ctrl_1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_PD_CTRL_1")
-            .field("sram_pd_1", &format_args!("{}", self.sram_pd_1().bit()))
+            .field("sram_pd_1", &self.sram_pd_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_PD_CTRL_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/tag_fo_ctrl.rs b/esp32/src/dport/tag_fo_ctrl.rs
index 6c20beb8d1..dd0a0ce17d 100644
--- a/esp32/src/dport/tag_fo_ctrl.rs
+++ b/esp32/src/dport/tag_fo_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TAG_FO_CTRL")
-            .field(
-                "pro_cache_tag_force_on",
-                &format_args!("{}", self.pro_cache_tag_force_on().bit()),
-            )
-            .field(
-                "pro_cache_tag_pd",
-                &format_args!("{}", self.pro_cache_tag_pd().bit()),
-            )
-            .field(
-                "app_cache_tag_force_on",
-                &format_args!("{}", self.app_cache_tag_force_on().bit()),
-            )
-            .field(
-                "app_cache_tag_pd",
-                &format_args!("{}", self.app_cache_tag_pd().bit()),
-            )
+            .field("pro_cache_tag_force_on", &self.pro_cache_tag_force_on())
+            .field("pro_cache_tag_pd", &self.pro_cache_tag_pd())
+            .field("app_cache_tag_force_on", &self.app_cache_tag_force_on())
+            .field("app_cache_tag_pd", &self.app_cache_tag_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TAG_FO_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/dport/tracemem_mux_mode.rs b/esp32/src/dport/tracemem_mux_mode.rs
index 58dc9f8e36..e3ef797ef5 100644
--- a/esp32/src/dport/tracemem_mux_mode.rs
+++ b/esp32/src/dport/tracemem_mux_mode.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TRACEMEM_MUX_MODE")
-            .field(
-                "tracemem_mux_mode",
-                &format_args!("{}", self.tracemem_mux_mode().bits()),
-            )
+            .field("tracemem_mux_mode", &self.tracemem_mux_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TRACEMEM_MUX_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/dport/wifi_bb_cfg.rs b/esp32/src/dport/wifi_bb_cfg.rs
index add5c8d9d1..484f9dd15b 100644
--- a/esp32/src/dport/wifi_bb_cfg.rs
+++ b/esp32/src/dport/wifi_bb_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_BB_CFG")
-            .field(
-                "wifi_bb_cfg",
-                &format_args!("{}", self.wifi_bb_cfg().bits()),
-            )
+            .field("wifi_bb_cfg", &self.wifi_bb_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_BB_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/dport/wifi_bb_cfg_2.rs b/esp32/src/dport/wifi_bb_cfg_2.rs
index f70cd5bd14..64cb926b9b 100644
--- a/esp32/src/dport/wifi_bb_cfg_2.rs
+++ b/esp32/src/dport/wifi_bb_cfg_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_BB_CFG_2")
-            .field(
-                "wifi_bb_cfg_2",
-                &format_args!("{}", self.wifi_bb_cfg_2().bits()),
-            )
+            .field("wifi_bb_cfg_2", &self.wifi_bb_cfg_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_BB_CFG_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/dport/wifi_clk_en.rs b/esp32/src/dport/wifi_clk_en.rs
index 27fb5ec788..d119bcf54d 100644
--- a/esp32/src/dport/wifi_clk_en.rs
+++ b/esp32/src/dport/wifi_clk_en.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_CLK_EN")
-            .field(
-                "wifi_clk_en",
-                &format_args!("{}", self.wifi_clk_en().bits()),
-            )
-            .field(
-                "wifi_clk_wifi_en",
-                &format_args!("{}", self.wifi_clk_wifi_en().bits()),
-            )
-            .field(
-                "wifi_clk_wifi_bt_common",
-                &format_args!("{}", self.wifi_clk_wifi_bt_common().bits()),
-            )
-            .field(
-                "wifi_clk_bt_en",
-                &format_args!("{}", self.wifi_clk_bt_en().bits()),
-            )
+            .field("wifi_clk_en", &self.wifi_clk_en())
+            .field("wifi_clk_wifi_en", &self.wifi_clk_wifi_en())
+            .field("wifi_clk_wifi_bt_common", &self.wifi_clk_wifi_bt_common())
+            .field("wifi_clk_bt_en", &self.wifi_clk_bt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk0_rdata0.rs b/esp32/src/efuse/blk0_rdata0.rs
index a3bf744274..30b9249192 100644
--- a/esp32/src/efuse/blk0_rdata0.rs
+++ b/esp32/src/efuse/blk0_rdata0.rs
@@ -41,35 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK0_RDATA0")
-            .field(
-                "rd_efuse_wr_dis",
-                &format_args!("{}", self.rd_efuse_wr_dis().bits()),
-            )
-            .field(
-                "rd_efuse_rd_dis",
-                &format_args!("{}", self.rd_efuse_rd_dis().bits()),
-            )
-            .field(
-                "rd_flash_crypt_cnt",
-                &format_args!("{}", self.rd_flash_crypt_cnt().bits()),
-            )
-            .field(
-                "rd_uart_download_dis",
-                &format_args!("{}", self.rd_uart_download_dis().bit()),
-            )
-            .field(
-                "reserved_0_28",
-                &format_args!("{}", self.reserved_0_28().bits()),
-            )
+            .field("rd_efuse_wr_dis", &self.rd_efuse_wr_dis())
+            .field("rd_efuse_rd_dis", &self.rd_efuse_rd_dis())
+            .field("rd_flash_crypt_cnt", &self.rd_flash_crypt_cnt())
+            .field("rd_uart_download_dis", &self.rd_uart_download_dis())
+            .field("reserved_0_28", &self.reserved_0_28())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_RDATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_rdata0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_RDATA0_SPEC;
 impl crate::RegisterSpec for BLK0_RDATA0_SPEC {
diff --git a/esp32/src/efuse/blk0_rdata1.rs b/esp32/src/efuse/blk0_rdata1.rs
index da1ef7534f..3c042b9c56 100644
--- a/esp32/src/efuse/blk0_rdata1.rs
+++ b/esp32/src/efuse/blk0_rdata1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK0_RDATA1")
-            .field("rd_mac", &format_args!("{}", self.rd_mac().bits()))
+            .field("rd_mac", &self.rd_mac())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_RDATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_rdata1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_RDATA1_SPEC;
 impl crate::RegisterSpec for BLK0_RDATA1_SPEC {
diff --git a/esp32/src/efuse/blk0_rdata2.rs b/esp32/src/efuse/blk0_rdata2.rs
index f2c2b47b65..60e7b743ea 100644
--- a/esp32/src/efuse/blk0_rdata2.rs
+++ b/esp32/src/efuse/blk0_rdata2.rs
@@ -31,21 +31,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK0_RDATA2")
-            .field("rd_mac_1", &format_args!("{}", self.rd_mac_1().bits()))
-            .field("rd_mac_crc", &format_args!("{}", self.rd_mac_crc().bits()))
-            .field(
-                "rd_reserve_0_88",
-                &format_args!("{}", self.rd_reserve_0_88().bits()),
-            )
+            .field("rd_mac_1", &self.rd_mac_1())
+            .field("rd_mac_crc", &self.rd_mac_crc())
+            .field("rd_reserve_0_88", &self.rd_reserve_0_88())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_RDATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 24:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk0_rdata3.rs b/esp32/src/efuse/blk0_rdata3.rs
index 39811d54b8..a930f06bb3 100644
--- a/esp32/src/efuse/blk0_rdata3.rs
+++ b/esp32/src/efuse/blk0_rdata3.rs
@@ -97,59 +97,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK0_RDATA3")
-            .field(
-                "rd_disable_app_cpu",
-                &format_args!("{}", self.rd_disable_app_cpu().bit()),
-            )
-            .field(
-                "rd_disable_bt",
-                &format_args!("{}", self.rd_disable_bt().bit()),
-            )
-            .field(
-                "rd_chip_package_4bit",
-                &format_args!("{}", self.rd_chip_package_4bit().bit()),
-            )
-            .field(
-                "rd_dis_cache",
-                &format_args!("{}", self.rd_dis_cache().bit()),
-            )
-            .field(
-                "rd_spi_pad_config_hd",
-                &format_args!("{}", self.rd_spi_pad_config_hd().bits()),
-            )
-            .field(
-                "rd_chip_package",
-                &format_args!("{}", self.rd_chip_package().bits()),
-            )
-            .field(
-                "rd_chip_cpu_freq_low",
-                &format_args!("{}", self.rd_chip_cpu_freq_low().bit()),
-            )
-            .field(
-                "rd_chip_cpu_freq_rated",
-                &format_args!("{}", self.rd_chip_cpu_freq_rated().bit()),
-            )
-            .field(
-                "rd_blk3_part_reserve",
-                &format_args!("{}", self.rd_blk3_part_reserve().bit()),
-            )
-            .field(
-                "rd_chip_ver_rev1",
-                &format_args!("{}", self.rd_chip_ver_rev1().bit()),
-            )
-            .field(
-                "rd_reserve_0_112",
-                &format_args!("{}", self.rd_reserve_0_112().bits()),
-            )
+            .field("rd_disable_app_cpu", &self.rd_disable_app_cpu())
+            .field("rd_disable_bt", &self.rd_disable_bt())
+            .field("rd_chip_package_4bit", &self.rd_chip_package_4bit())
+            .field("rd_dis_cache", &self.rd_dis_cache())
+            .field("rd_spi_pad_config_hd", &self.rd_spi_pad_config_hd())
+            .field("rd_chip_package", &self.rd_chip_package())
+            .field("rd_chip_cpu_freq_low", &self.rd_chip_cpu_freq_low())
+            .field("rd_chip_cpu_freq_rated", &self.rd_chip_cpu_freq_rated())
+            .field("rd_blk3_part_reserve", &self.rd_blk3_part_reserve())
+            .field("rd_chip_ver_rev1", &self.rd_chip_ver_rev1())
+            .field("rd_reserve_0_112", &self.rd_reserve_0_112())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_RDATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 9:11"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk0_rdata4.rs b/esp32/src/efuse/blk0_rdata4.rs
index c01a129935..ad33913f2a 100644
--- a/esp32/src/efuse/blk0_rdata4.rs
+++ b/esp32/src/efuse/blk0_rdata4.rs
@@ -63,40 +63,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK0_RDATA4")
-            .field(
-                "rd_clk8m_freq",
-                &format_args!("{}", self.rd_clk8m_freq().bits()),
-            )
-            .field(
-                "rd_adc_vref",
-                &format_args!("{}", self.rd_adc_vref().bits()),
-            )
-            .field(
-                "rd_reserve_0_141",
-                &format_args!("{}", self.rd_reserve_0_141().bit()),
-            )
-            .field("rd_xpd_sdio", &format_args!("{}", self.rd_xpd_sdio().bit()))
-            .field(
-                "rd_xpd_sdio_tieh",
-                &format_args!("{}", self.rd_xpd_sdio_tieh().bit()),
-            )
-            .field(
-                "rd_xpd_sdio_force",
-                &format_args!("{}", self.rd_xpd_sdio_force().bit()),
-            )
-            .field(
-                "rd_reserve_0_145",
-                &format_args!("{}", self.rd_reserve_0_145().bits()),
-            )
+            .field("rd_clk8m_freq", &self.rd_clk8m_freq())
+            .field("rd_adc_vref", &self.rd_adc_vref())
+            .field("rd_reserve_0_141", &self.rd_reserve_0_141())
+            .field("rd_xpd_sdio", &self.rd_xpd_sdio())
+            .field("rd_xpd_sdio_tieh", &self.rd_xpd_sdio_tieh())
+            .field("rd_xpd_sdio_force", &self.rd_xpd_sdio_force())
+            .field("rd_reserve_0_145", &self.rd_reserve_0_145())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_RDATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:12"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk0_rdata5.rs b/esp32/src/efuse/blk0_rdata5.rs
index d729a140a4..76d05c7458 100644
--- a/esp32/src/efuse/blk0_rdata5.rs
+++ b/esp32/src/efuse/blk0_rdata5.rs
@@ -82,55 +82,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK0_RDATA5")
-            .field(
-                "rd_spi_pad_config_clk",
-                &format_args!("{}", self.rd_spi_pad_config_clk().bits()),
-            )
-            .field(
-                "rd_spi_pad_config_q",
-                &format_args!("{}", self.rd_spi_pad_config_q().bits()),
-            )
-            .field(
-                "rd_spi_pad_config_d",
-                &format_args!("{}", self.rd_spi_pad_config_d().bits()),
-            )
-            .field(
-                "rd_spi_pad_config_cs0",
-                &format_args!("{}", self.rd_spi_pad_config_cs0().bits()),
-            )
-            .field(
-                "rd_chip_ver_rev2",
-                &format_args!("{}", self.rd_chip_ver_rev2().bit()),
-            )
-            .field(
-                "rd_reserve_0_181",
-                &format_args!("{}", self.rd_reserve_0_181().bit()),
-            )
-            .field(
-                "rd_vol_level_hp_inv",
-                &format_args!("{}", self.rd_vol_level_hp_inv().bits()),
-            )
-            .field(
-                "rd_wafer_version_minor",
-                &format_args!("{}", self.rd_wafer_version_minor().bits()),
-            )
-            .field(
-                "rd_reserve_0_186",
-                &format_args!("{}", self.rd_reserve_0_186().bits()),
-            )
-            .field(
-                "rd_flash_crypt_config",
-                &format_args!("{}", self.rd_flash_crypt_config().bits()),
-            )
+            .field("rd_spi_pad_config_clk", &self.rd_spi_pad_config_clk())
+            .field("rd_spi_pad_config_q", &self.rd_spi_pad_config_q())
+            .field("rd_spi_pad_config_d", &self.rd_spi_pad_config_d())
+            .field("rd_spi_pad_config_cs0", &self.rd_spi_pad_config_cs0())
+            .field("rd_chip_ver_rev2", &self.rd_chip_ver_rev2())
+            .field("rd_reserve_0_181", &self.rd_reserve_0_181())
+            .field("rd_vol_level_hp_inv", &self.rd_vol_level_hp_inv())
+            .field("rd_wafer_version_minor", &self.rd_wafer_version_minor())
+            .field("rd_reserve_0_186", &self.rd_reserve_0_186())
+            .field("rd_flash_crypt_config", &self.rd_flash_crypt_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_RDATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk0_rdata6.rs b/esp32/src/efuse/blk0_rdata6.rs
index c989023a83..fcddc170fb 100644
--- a/esp32/src/efuse/blk0_rdata6.rs
+++ b/esp32/src/efuse/blk0_rdata6.rs
@@ -87,59 +87,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK0_RDATA6")
-            .field(
-                "rd_coding_scheme",
-                &format_args!("{}", self.rd_coding_scheme().bits()),
-            )
-            .field(
-                "rd_console_debug_disable",
-                &format_args!("{}", self.rd_console_debug_disable().bit()),
-            )
-            .field(
-                "rd_disable_sdio_host",
-                &format_args!("{}", self.rd_disable_sdio_host().bit()),
-            )
-            .field(
-                "rd_abs_done_0",
-                &format_args!("{}", self.rd_abs_done_0().bit()),
-            )
-            .field(
-                "rd_abs_done_1",
-                &format_args!("{}", self.rd_abs_done_1().bit()),
-            )
-            .field(
-                "rd_jtag_disable",
-                &format_args!("{}", self.rd_jtag_disable().bit()),
-            )
-            .field(
-                "rd_disable_dl_encrypt",
-                &format_args!("{}", self.rd_disable_dl_encrypt().bit()),
-            )
-            .field(
-                "rd_disable_dl_decrypt",
-                &format_args!("{}", self.rd_disable_dl_decrypt().bit()),
-            )
-            .field(
-                "rd_disable_dl_cache",
-                &format_args!("{}", self.rd_disable_dl_cache().bit()),
-            )
-            .field(
-                "rd_key_status",
-                &format_args!("{}", self.rd_key_status().bit()),
-            )
-            .field(
-                "rd_reserve_0_203",
-                &format_args!("{}", self.rd_reserve_0_203().bits()),
-            )
+            .field("rd_coding_scheme", &self.rd_coding_scheme())
+            .field("rd_console_debug_disable", &self.rd_console_debug_disable())
+            .field("rd_disable_sdio_host", &self.rd_disable_sdio_host())
+            .field("rd_abs_done_0", &self.rd_abs_done_0())
+            .field("rd_abs_done_1", &self.rd_abs_done_1())
+            .field("rd_jtag_disable", &self.rd_jtag_disable())
+            .field("rd_disable_dl_encrypt", &self.rd_disable_dl_encrypt())
+            .field("rd_disable_dl_decrypt", &self.rd_disable_dl_decrypt())
+            .field("rd_disable_dl_cache", &self.rd_disable_dl_cache())
+            .field("rd_key_status", &self.rd_key_status())
+            .field("rd_reserve_0_203", &self.rd_reserve_0_203())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_RDATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 11:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk0_wdata0.rs b/esp32/src/efuse/blk0_wdata0.rs
index ef18e6a3f2..46141324d7 100644
--- a/esp32/src/efuse/blk0_wdata0.rs
+++ b/esp32/src/efuse/blk0_wdata0.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK0_WDATA0")
-            .field("wr_dis", &format_args!("{}", self.wr_dis().bits()))
-            .field("rd_dis", &format_args!("{}", self.rd_dis().bits()))
-            .field(
-                "flash_crypt_cnt",
-                &format_args!("{}", self.flash_crypt_cnt().bits()),
-            )
+            .field("wr_dis", &self.wr_dis())
+            .field("rd_dis", &self.rd_dis())
+            .field("flash_crypt_cnt", &self.flash_crypt_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_WDATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk0_wdata1.rs b/esp32/src/efuse/blk0_wdata1.rs
index 7ea97d41a1..27c61dfe07 100644
--- a/esp32/src/efuse/blk0_wdata1.rs
+++ b/esp32/src/efuse/blk0_wdata1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK0_WDATA1")
-            .field(
-                "wifi_mac_crc_low",
-                &format_args!("{}", self.wifi_mac_crc_low().bits()),
-            )
+            .field("wifi_mac_crc_low", &self.wifi_mac_crc_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_WDATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk0_wdata2.rs b/esp32/src/efuse/blk0_wdata2.rs
index b78c7a5528..c34ddfce87 100644
--- a/esp32/src/efuse/blk0_wdata2.rs
+++ b/esp32/src/efuse/blk0_wdata2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK0_WDATA2")
-            .field(
-                "wifi_mac_crc_high",
-                &format_args!("{}", self.wifi_mac_crc_high().bits()),
-            )
+            .field("wifi_mac_crc_high", &self.wifi_mac_crc_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_WDATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk0_wdata3.rs b/esp32/src/efuse/blk0_wdata3.rs
index fb49d08306..ccab9310d2 100644
--- a/esp32/src/efuse/blk0_wdata3.rs
+++ b/esp32/src/efuse/blk0_wdata3.rs
@@ -97,53 +97,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK0_WDATA3")
-            .field(
-                "disable_app_cpu",
-                &format_args!("{}", self.disable_app_cpu().bit()),
-            )
-            .field("disable_bt", &format_args!("{}", self.disable_bt().bit()))
-            .field(
-                "chip_package_4bit",
-                &format_args!("{}", self.chip_package_4bit().bit()),
-            )
-            .field("dis_cache", &format_args!("{}", self.dis_cache().bit()))
-            .field(
-                "spi_pad_config_hd",
-                &format_args!("{}", self.spi_pad_config_hd().bits()),
-            )
-            .field(
-                "chip_package",
-                &format_args!("{}", self.chip_package().bits()),
-            )
-            .field(
-                "chip_cpu_freq_low",
-                &format_args!("{}", self.chip_cpu_freq_low().bit()),
-            )
-            .field(
-                "chip_cpu_freq_rated",
-                &format_args!("{}", self.chip_cpu_freq_rated().bit()),
-            )
-            .field(
-                "blk3_part_reserve",
-                &format_args!("{}", self.blk3_part_reserve().bit()),
-            )
-            .field(
-                "chip_ver_rev1",
-                &format_args!("{}", self.chip_ver_rev1().bit()),
-            )
-            .field(
-                "reserve_0_112",
-                &format_args!("{}", self.reserve_0_112().bits()),
-            )
+            .field("disable_app_cpu", &self.disable_app_cpu())
+            .field("disable_bt", &self.disable_bt())
+            .field("chip_package_4bit", &self.chip_package_4bit())
+            .field("dis_cache", &self.dis_cache())
+            .field("spi_pad_config_hd", &self.spi_pad_config_hd())
+            .field("chip_package", &self.chip_package())
+            .field("chip_cpu_freq_low", &self.chip_cpu_freq_low())
+            .field("chip_cpu_freq_rated", &self.chip_cpu_freq_rated())
+            .field("blk3_part_reserve", &self.blk3_part_reserve())
+            .field("chip_ver_rev1", &self.chip_ver_rev1())
+            .field("reserve_0_112", &self.reserve_0_112())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_WDATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 9:11"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk0_wdata4.rs b/esp32/src/efuse/blk0_wdata4.rs
index 5c11c387b5..2e3aa6c122 100644
--- a/esp32/src/efuse/blk0_wdata4.rs
+++ b/esp32/src/efuse/blk0_wdata4.rs
@@ -63,34 +63,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK0_WDATA4")
-            .field("clk8m_freq", &format_args!("{}", self.clk8m_freq().bits()))
-            .field("adc_vref", &format_args!("{}", self.adc_vref().bits()))
-            .field(
-                "reserve_0_141",
-                &format_args!("{}", self.reserve_0_141().bit()),
-            )
-            .field("xpd_sdio", &format_args!("{}", self.xpd_sdio().bit()))
-            .field(
-                "xpd_sdio_tieh",
-                &format_args!("{}", self.xpd_sdio_tieh().bit()),
-            )
-            .field(
-                "xpd_sdio_force",
-                &format_args!("{}", self.xpd_sdio_force().bit()),
-            )
-            .field(
-                "reserve_0_145",
-                &format_args!("{}", self.reserve_0_145().bits()),
-            )
+            .field("clk8m_freq", &self.clk8m_freq())
+            .field("adc_vref", &self.adc_vref())
+            .field("reserve_0_141", &self.reserve_0_141())
+            .field("xpd_sdio", &self.xpd_sdio())
+            .field("xpd_sdio_tieh", &self.xpd_sdio_tieh())
+            .field("xpd_sdio_force", &self.xpd_sdio_force())
+            .field("reserve_0_145", &self.reserve_0_145())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_WDATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:12"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk0_wdata5.rs b/esp32/src/efuse/blk0_wdata5.rs
index 296d72b137..23165d228a 100644
--- a/esp32/src/efuse/blk0_wdata5.rs
+++ b/esp32/src/efuse/blk0_wdata5.rs
@@ -82,55 +82,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK0_WDATA5")
-            .field(
-                "spi_pad_config_clk",
-                &format_args!("{}", self.spi_pad_config_clk().bits()),
-            )
-            .field(
-                "spi_pad_config_q",
-                &format_args!("{}", self.spi_pad_config_q().bits()),
-            )
-            .field(
-                "spi_pad_config_d",
-                &format_args!("{}", self.spi_pad_config_d().bits()),
-            )
-            .field(
-                "spi_pad_config_cs0",
-                &format_args!("{}", self.spi_pad_config_cs0().bits()),
-            )
-            .field(
-                "chip_ver_rev2",
-                &format_args!("{}", self.chip_ver_rev2().bit()),
-            )
-            .field(
-                "reserve_0_181",
-                &format_args!("{}", self.reserve_0_181().bit()),
-            )
-            .field(
-                "vol_level_hp_inv",
-                &format_args!("{}", self.vol_level_hp_inv().bits()),
-            )
-            .field(
-                "wafer_version_minor",
-                &format_args!("{}", self.wafer_version_minor().bits()),
-            )
-            .field(
-                "reserve_0_186",
-                &format_args!("{}", self.reserve_0_186().bits()),
-            )
-            .field(
-                "flash_crypt_config",
-                &format_args!("{}", self.flash_crypt_config().bits()),
-            )
+            .field("spi_pad_config_clk", &self.spi_pad_config_clk())
+            .field("spi_pad_config_q", &self.spi_pad_config_q())
+            .field("spi_pad_config_d", &self.spi_pad_config_d())
+            .field("spi_pad_config_cs0", &self.spi_pad_config_cs0())
+            .field("chip_ver_rev2", &self.chip_ver_rev2())
+            .field("reserve_0_181", &self.reserve_0_181())
+            .field("vol_level_hp_inv", &self.vol_level_hp_inv())
+            .field("wafer_version_minor", &self.wafer_version_minor())
+            .field("reserve_0_186", &self.reserve_0_186())
+            .field("flash_crypt_config", &self.flash_crypt_config())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_WDATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk0_wdata6.rs b/esp32/src/efuse/blk0_wdata6.rs
index 0d6742dedf..a0cd39a85a 100644
--- a/esp32/src/efuse/blk0_wdata6.rs
+++ b/esp32/src/efuse/blk0_wdata6.rs
@@ -98,46 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK0_WDATA6")
-            .field(
-                "coding_scheme",
-                &format_args!("{}", self.coding_scheme().bits()),
-            )
-            .field(
-                "console_debug_disable",
-                &format_args!("{}", self.console_debug_disable().bit()),
-            )
-            .field(
-                "disable_sdio_host",
-                &format_args!("{}", self.disable_sdio_host().bit()),
-            )
-            .field("abs_done_0", &format_args!("{}", self.abs_done_0().bit()))
-            .field("abs_done_1", &format_args!("{}", self.abs_done_1().bit()))
-            .field(
-                "disable_jtag",
-                &format_args!("{}", self.disable_jtag().bit()),
-            )
-            .field(
-                "disable_dl_encrypt",
-                &format_args!("{}", self.disable_dl_encrypt().bit()),
-            )
-            .field(
-                "disable_dl_decrypt",
-                &format_args!("{}", self.disable_dl_decrypt().bit()),
-            )
-            .field(
-                "disable_dl_cache",
-                &format_args!("{}", self.disable_dl_cache().bit()),
-            )
-            .field("key_status", &format_args!("{}", self.key_status().bit()))
+            .field("coding_scheme", &self.coding_scheme())
+            .field("console_debug_disable", &self.console_debug_disable())
+            .field("disable_sdio_host", &self.disable_sdio_host())
+            .field("abs_done_0", &self.abs_done_0())
+            .field("abs_done_1", &self.abs_done_1())
+            .field("disable_jtag", &self.disable_jtag())
+            .field("disable_dl_encrypt", &self.disable_dl_encrypt())
+            .field("disable_dl_decrypt", &self.disable_dl_decrypt())
+            .field("disable_dl_cache", &self.disable_dl_cache())
+            .field("key_status", &self.key_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_WDATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk1_rdata0.rs b/esp32/src/efuse/blk1_rdata0.rs
index 2cc177813f..d0e152f627 100644
--- a/esp32/src/efuse/blk1_rdata0.rs
+++ b/esp32/src/efuse/blk1_rdata0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_RDATA0")
-            .field("rd_block1", &format_args!("{}", self.rd_block1().bits()))
+            .field("rd_block1", &self.rd_block1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_RDATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_rdata0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_RDATA0_SPEC;
 impl crate::RegisterSpec for BLK1_RDATA0_SPEC {
diff --git a/esp32/src/efuse/blk1_rdata1.rs b/esp32/src/efuse/blk1_rdata1.rs
index 6a50b4a604..577559f660 100644
--- a/esp32/src/efuse/blk1_rdata1.rs
+++ b/esp32/src/efuse/blk1_rdata1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_RDATA1")
-            .field(
-                "rd_block1_1",
-                &format_args!("{}", self.rd_block1_1().bits()),
-            )
+            .field("rd_block1_1", &self.rd_block1_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_RDATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_rdata1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_RDATA1_SPEC;
 impl crate::RegisterSpec for BLK1_RDATA1_SPEC {
diff --git a/esp32/src/efuse/blk1_rdata2.rs b/esp32/src/efuse/blk1_rdata2.rs
index 1f3cdfa394..831fc9857b 100644
--- a/esp32/src/efuse/blk1_rdata2.rs
+++ b/esp32/src/efuse/blk1_rdata2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_RDATA2")
-            .field(
-                "rd_block1_2",
-                &format_args!("{}", self.rd_block1_2().bits()),
-            )
+            .field("rd_block1_2", &self.rd_block1_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_RDATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_rdata2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_RDATA2_SPEC;
 impl crate::RegisterSpec for BLK1_RDATA2_SPEC {
diff --git a/esp32/src/efuse/blk1_rdata3.rs b/esp32/src/efuse/blk1_rdata3.rs
index f87c66bdd5..cec5b27f88 100644
--- a/esp32/src/efuse/blk1_rdata3.rs
+++ b/esp32/src/efuse/blk1_rdata3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_RDATA3")
-            .field(
-                "rd_block1_3",
-                &format_args!("{}", self.rd_block1_3().bits()),
-            )
+            .field("rd_block1_3", &self.rd_block1_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_RDATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_rdata3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_RDATA3_SPEC;
 impl crate::RegisterSpec for BLK1_RDATA3_SPEC {
diff --git a/esp32/src/efuse/blk1_rdata4.rs b/esp32/src/efuse/blk1_rdata4.rs
index dcba12a89d..41cf184e0a 100644
--- a/esp32/src/efuse/blk1_rdata4.rs
+++ b/esp32/src/efuse/blk1_rdata4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_RDATA4")
-            .field(
-                "rd_block1_4",
-                &format_args!("{}", self.rd_block1_4().bits()),
-            )
+            .field("rd_block1_4", &self.rd_block1_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_RDATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_rdata4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_RDATA4_SPEC;
 impl crate::RegisterSpec for BLK1_RDATA4_SPEC {
diff --git a/esp32/src/efuse/blk1_rdata5.rs b/esp32/src/efuse/blk1_rdata5.rs
index 0df319353b..bb8bf31a13 100644
--- a/esp32/src/efuse/blk1_rdata5.rs
+++ b/esp32/src/efuse/blk1_rdata5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_RDATA5")
-            .field(
-                "rd_block1_5",
-                &format_args!("{}", self.rd_block1_5().bits()),
-            )
+            .field("rd_block1_5", &self.rd_block1_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_RDATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_rdata5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_RDATA5_SPEC;
 impl crate::RegisterSpec for BLK1_RDATA5_SPEC {
diff --git a/esp32/src/efuse/blk1_rdata6.rs b/esp32/src/efuse/blk1_rdata6.rs
index 2552bff20b..8de5a770fd 100644
--- a/esp32/src/efuse/blk1_rdata6.rs
+++ b/esp32/src/efuse/blk1_rdata6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_RDATA6")
-            .field(
-                "rd_block1_6",
-                &format_args!("{}", self.rd_block1_6().bits()),
-            )
+            .field("rd_block1_6", &self.rd_block1_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_RDATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_rdata6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_RDATA6_SPEC;
 impl crate::RegisterSpec for BLK1_RDATA6_SPEC {
diff --git a/esp32/src/efuse/blk1_rdata7.rs b/esp32/src/efuse/blk1_rdata7.rs
index dcbde73702..1b2107ca10 100644
--- a/esp32/src/efuse/blk1_rdata7.rs
+++ b/esp32/src/efuse/blk1_rdata7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_RDATA7")
-            .field(
-                "rd_block1_7",
-                &format_args!("{}", self.rd_block1_7().bits()),
-            )
+            .field("rd_block1_7", &self.rd_block1_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_RDATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_rdata7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_RDATA7_SPEC;
 impl crate::RegisterSpec for BLK1_RDATA7_SPEC {
diff --git a/esp32/src/efuse/blk1_wdata0.rs b/esp32/src/efuse/blk1_wdata0.rs
index 093cab31e3..3d7f656560 100644
--- a/esp32/src/efuse/blk1_wdata0.rs
+++ b/esp32/src/efuse/blk1_wdata0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_WDATA0")
-            .field("blk1_din0", &format_args!("{}", self.blk1_din0().bits()))
+            .field("blk1_din0", &self.blk1_din0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_WDATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk1_wdata1.rs b/esp32/src/efuse/blk1_wdata1.rs
index 54ef843784..8b639e9516 100644
--- a/esp32/src/efuse/blk1_wdata1.rs
+++ b/esp32/src/efuse/blk1_wdata1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_WDATA1")
-            .field("blk1_din1", &format_args!("{}", self.blk1_din1().bits()))
+            .field("blk1_din1", &self.blk1_din1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_WDATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk1_wdata2.rs b/esp32/src/efuse/blk1_wdata2.rs
index 38f96a8cb1..c606733377 100644
--- a/esp32/src/efuse/blk1_wdata2.rs
+++ b/esp32/src/efuse/blk1_wdata2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_WDATA2")
-            .field("blk1_din2", &format_args!("{}", self.blk1_din2().bits()))
+            .field("blk1_din2", &self.blk1_din2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_WDATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk1_wdata3.rs b/esp32/src/efuse/blk1_wdata3.rs
index 02d6d05ed6..a2e441393e 100644
--- a/esp32/src/efuse/blk1_wdata3.rs
+++ b/esp32/src/efuse/blk1_wdata3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_WDATA3")
-            .field("blk1_din3", &format_args!("{}", self.blk1_din3().bits()))
+            .field("blk1_din3", &self.blk1_din3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_WDATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk1_wdata4.rs b/esp32/src/efuse/blk1_wdata4.rs
index 6f1047c954..3e3ca095d5 100644
--- a/esp32/src/efuse/blk1_wdata4.rs
+++ b/esp32/src/efuse/blk1_wdata4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_WDATA4")
-            .field("blk1_din4", &format_args!("{}", self.blk1_din4().bits()))
+            .field("blk1_din4", &self.blk1_din4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_WDATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk1_wdata5.rs b/esp32/src/efuse/blk1_wdata5.rs
index 270f61aba5..c5174a2ba2 100644
--- a/esp32/src/efuse/blk1_wdata5.rs
+++ b/esp32/src/efuse/blk1_wdata5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_WDATA5")
-            .field("blk1_din5", &format_args!("{}", self.blk1_din5().bits()))
+            .field("blk1_din5", &self.blk1_din5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_WDATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk1_wdata6.rs b/esp32/src/efuse/blk1_wdata6.rs
index 002d622839..939bcba8ce 100644
--- a/esp32/src/efuse/blk1_wdata6.rs
+++ b/esp32/src/efuse/blk1_wdata6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_WDATA6")
-            .field("blk1_din6", &format_args!("{}", self.blk1_din6().bits()))
+            .field("blk1_din6", &self.blk1_din6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_WDATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk1_wdata7.rs b/esp32/src/efuse/blk1_wdata7.rs
index e5215179bc..0af969d732 100644
--- a/esp32/src/efuse/blk1_wdata7.rs
+++ b/esp32/src/efuse/blk1_wdata7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_WDATA7")
-            .field("blk1_din7", &format_args!("{}", self.blk1_din7().bits()))
+            .field("blk1_din7", &self.blk1_din7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_WDATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk2_rdata0.rs b/esp32/src/efuse/blk2_rdata0.rs
index 225f62a493..77a7126bcc 100644
--- a/esp32/src/efuse/blk2_rdata0.rs
+++ b/esp32/src/efuse/blk2_rdata0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_RDATA0")
-            .field("rd_block2", &format_args!("{}", self.rd_block2().bits()))
+            .field("rd_block2", &self.rd_block2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_RDATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_rdata0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_RDATA0_SPEC;
 impl crate::RegisterSpec for BLK2_RDATA0_SPEC {
diff --git a/esp32/src/efuse/blk2_rdata1.rs b/esp32/src/efuse/blk2_rdata1.rs
index 3601d80a39..c5d12a6601 100644
--- a/esp32/src/efuse/blk2_rdata1.rs
+++ b/esp32/src/efuse/blk2_rdata1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_RDATA1")
-            .field(
-                "rd_block2_1",
-                &format_args!("{}", self.rd_block2_1().bits()),
-            )
+            .field("rd_block2_1", &self.rd_block2_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_RDATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_rdata1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_RDATA1_SPEC;
 impl crate::RegisterSpec for BLK2_RDATA1_SPEC {
diff --git a/esp32/src/efuse/blk2_rdata2.rs b/esp32/src/efuse/blk2_rdata2.rs
index 596f84eba5..f0031b632c 100644
--- a/esp32/src/efuse/blk2_rdata2.rs
+++ b/esp32/src/efuse/blk2_rdata2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_RDATA2")
-            .field(
-                "rd_block2_2",
-                &format_args!("{}", self.rd_block2_2().bits()),
-            )
+            .field("rd_block2_2", &self.rd_block2_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_RDATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_rdata2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_RDATA2_SPEC;
 impl crate::RegisterSpec for BLK2_RDATA2_SPEC {
diff --git a/esp32/src/efuse/blk2_rdata3.rs b/esp32/src/efuse/blk2_rdata3.rs
index ceadaafc76..6a967ed688 100644
--- a/esp32/src/efuse/blk2_rdata3.rs
+++ b/esp32/src/efuse/blk2_rdata3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_RDATA3")
-            .field(
-                "rd_block2_3",
-                &format_args!("{}", self.rd_block2_3().bits()),
-            )
+            .field("rd_block2_3", &self.rd_block2_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_RDATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_rdata3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_RDATA3_SPEC;
 impl crate::RegisterSpec for BLK2_RDATA3_SPEC {
diff --git a/esp32/src/efuse/blk2_rdata4.rs b/esp32/src/efuse/blk2_rdata4.rs
index b7b4881d7c..029f53a5ce 100644
--- a/esp32/src/efuse/blk2_rdata4.rs
+++ b/esp32/src/efuse/blk2_rdata4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_RDATA4")
-            .field(
-                "rd_block2_4",
-                &format_args!("{}", self.rd_block2_4().bits()),
-            )
+            .field("rd_block2_4", &self.rd_block2_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_RDATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_rdata4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_RDATA4_SPEC;
 impl crate::RegisterSpec for BLK2_RDATA4_SPEC {
diff --git a/esp32/src/efuse/blk2_rdata5.rs b/esp32/src/efuse/blk2_rdata5.rs
index 47d6bba5e8..1a86377b78 100644
--- a/esp32/src/efuse/blk2_rdata5.rs
+++ b/esp32/src/efuse/blk2_rdata5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_RDATA5")
-            .field(
-                "rd_block2_5",
-                &format_args!("{}", self.rd_block2_5().bits()),
-            )
+            .field("rd_block2_5", &self.rd_block2_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_RDATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_rdata5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_RDATA5_SPEC;
 impl crate::RegisterSpec for BLK2_RDATA5_SPEC {
diff --git a/esp32/src/efuse/blk2_rdata6.rs b/esp32/src/efuse/blk2_rdata6.rs
index d884193493..e5319b0ec3 100644
--- a/esp32/src/efuse/blk2_rdata6.rs
+++ b/esp32/src/efuse/blk2_rdata6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_RDATA6")
-            .field(
-                "rd_block2_6",
-                &format_args!("{}", self.rd_block2_6().bits()),
-            )
+            .field("rd_block2_6", &self.rd_block2_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_RDATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_rdata6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_RDATA6_SPEC;
 impl crate::RegisterSpec for BLK2_RDATA6_SPEC {
diff --git a/esp32/src/efuse/blk2_rdata7.rs b/esp32/src/efuse/blk2_rdata7.rs
index 2132c94720..92b7fb3e69 100644
--- a/esp32/src/efuse/blk2_rdata7.rs
+++ b/esp32/src/efuse/blk2_rdata7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_RDATA7")
-            .field(
-                "rd_block2_7",
-                &format_args!("{}", self.rd_block2_7().bits()),
-            )
+            .field("rd_block2_7", &self.rd_block2_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_RDATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_rdata7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_RDATA7_SPEC;
 impl crate::RegisterSpec for BLK2_RDATA7_SPEC {
diff --git a/esp32/src/efuse/blk2_wdata0.rs b/esp32/src/efuse/blk2_wdata0.rs
index 06b269a419..68edacd4ec 100644
--- a/esp32/src/efuse/blk2_wdata0.rs
+++ b/esp32/src/efuse/blk2_wdata0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_WDATA0")
-            .field("blk2_din0", &format_args!("{}", self.blk2_din0().bits()))
+            .field("blk2_din0", &self.blk2_din0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_WDATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk2_wdata1.rs b/esp32/src/efuse/blk2_wdata1.rs
index 5891997c23..283ade91d0 100644
--- a/esp32/src/efuse/blk2_wdata1.rs
+++ b/esp32/src/efuse/blk2_wdata1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_WDATA1")
-            .field("blk2_din1", &format_args!("{}", self.blk2_din1().bits()))
+            .field("blk2_din1", &self.blk2_din1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_WDATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk2_wdata2.rs b/esp32/src/efuse/blk2_wdata2.rs
index 5a62c09422..0b22596c09 100644
--- a/esp32/src/efuse/blk2_wdata2.rs
+++ b/esp32/src/efuse/blk2_wdata2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_WDATA2")
-            .field("blk2_din2", &format_args!("{}", self.blk2_din2().bits()))
+            .field("blk2_din2", &self.blk2_din2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_WDATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk2_wdata3.rs b/esp32/src/efuse/blk2_wdata3.rs
index a5b0a4c4c0..115e24df09 100644
--- a/esp32/src/efuse/blk2_wdata3.rs
+++ b/esp32/src/efuse/blk2_wdata3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_WDATA3")
-            .field("blk2_din3", &format_args!("{}", self.blk2_din3().bits()))
+            .field("blk2_din3", &self.blk2_din3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_WDATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk2_wdata4.rs b/esp32/src/efuse/blk2_wdata4.rs
index 95d97f3226..5f8a55f914 100644
--- a/esp32/src/efuse/blk2_wdata4.rs
+++ b/esp32/src/efuse/blk2_wdata4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_WDATA4")
-            .field("blk2_din4", &format_args!("{}", self.blk2_din4().bits()))
+            .field("blk2_din4", &self.blk2_din4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_WDATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk2_wdata5.rs b/esp32/src/efuse/blk2_wdata5.rs
index a56a01fe07..20a0f94d2a 100644
--- a/esp32/src/efuse/blk2_wdata5.rs
+++ b/esp32/src/efuse/blk2_wdata5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_WDATA5")
-            .field("blk2_din5", &format_args!("{}", self.blk2_din5().bits()))
+            .field("blk2_din5", &self.blk2_din5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_WDATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk2_wdata6.rs b/esp32/src/efuse/blk2_wdata6.rs
index 66f9b0b7ef..7f57c47aa0 100644
--- a/esp32/src/efuse/blk2_wdata6.rs
+++ b/esp32/src/efuse/blk2_wdata6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_WDATA6")
-            .field("blk2_din6", &format_args!("{}", self.blk2_din6().bits()))
+            .field("blk2_din6", &self.blk2_din6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_WDATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk2_wdata7.rs b/esp32/src/efuse/blk2_wdata7.rs
index 887274d84b..2b4a61deb6 100644
--- a/esp32/src/efuse/blk2_wdata7.rs
+++ b/esp32/src/efuse/blk2_wdata7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_WDATA7")
-            .field("blk2_din7", &format_args!("{}", self.blk2_din7().bits()))
+            .field("blk2_din7", &self.blk2_din7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_WDATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk3_rdata0.rs b/esp32/src/efuse/blk3_rdata0.rs
index b2b7d9aa30..c50cbcb4fe 100644
--- a/esp32/src/efuse/blk3_rdata0.rs
+++ b/esp32/src/efuse/blk3_rdata0.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_RDATA0")
-            .field(
-                "rd_custom_mac_crc",
-                &format_args!("{}", self.rd_custom_mac_crc().bits()),
-            )
-            .field(
-                "rd_custom_mac",
-                &format_args!("{}", self.rd_custom_mac().bits()),
-            )
+            .field("rd_custom_mac_crc", &self.rd_custom_mac_crc())
+            .field("rd_custom_mac", &self.rd_custom_mac())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_RDATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_rdata0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_RDATA0_SPEC;
 impl crate::RegisterSpec for BLK3_RDATA0_SPEC {
diff --git a/esp32/src/efuse/blk3_rdata1.rs b/esp32/src/efuse/blk3_rdata1.rs
index fb45f75847..9e465db7a0 100644
--- a/esp32/src/efuse/blk3_rdata1.rs
+++ b/esp32/src/efuse/blk3_rdata1.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_RDATA1")
-            .field(
-                "rd_custom_mac_1",
-                &format_args!("{}", self.rd_custom_mac_1().bits()),
-            )
-            .field(
-                "reserved_3_56",
-                &format_args!("{}", self.reserved_3_56().bits()),
-            )
+            .field("rd_custom_mac_1", &self.rd_custom_mac_1())
+            .field("reserved_3_56", &self.reserved_3_56())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_RDATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_rdata1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_RDATA1_SPEC;
 impl crate::RegisterSpec for BLK3_RDATA1_SPEC {
diff --git a/esp32/src/efuse/blk3_rdata2.rs b/esp32/src/efuse/blk3_rdata2.rs
index 389f9b149f..cb583a057d 100644
--- a/esp32/src/efuse/blk3_rdata2.rs
+++ b/esp32/src/efuse/blk3_rdata2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_RDATA2")
-            .field(
-                "rd_blk3_reserved_2",
-                &format_args!("{}", self.rd_blk3_reserved_2().bits()),
-            )
+            .field("rd_blk3_reserved_2", &self.rd_blk3_reserved_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_RDATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_rdata2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_RDATA2_SPEC;
 impl crate::RegisterSpec for BLK3_RDATA2_SPEC {
diff --git a/esp32/src/efuse/blk3_rdata3.rs b/esp32/src/efuse/blk3_rdata3.rs
index f0c50dc5db..c124f3e117 100644
--- a/esp32/src/efuse/blk3_rdata3.rs
+++ b/esp32/src/efuse/blk3_rdata3.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_RDATA3")
-            .field(
-                "rd_adc1_tp_low",
-                &format_args!("{}", self.rd_adc1_tp_low().bits()),
-            )
-            .field(
-                "rd_adc1_tp_high",
-                &format_args!("{}", self.rd_adc1_tp_high().bits()),
-            )
-            .field(
-                "rd_adc2_tp_low",
-                &format_args!("{}", self.rd_adc2_tp_low().bits()),
-            )
-            .field(
-                "rd_adc2_tp_high",
-                &format_args!("{}", self.rd_adc2_tp_high().bits()),
-            )
+            .field("rd_adc1_tp_low", &self.rd_adc1_tp_low())
+            .field("rd_adc1_tp_high", &self.rd_adc1_tp_high())
+            .field("rd_adc2_tp_low", &self.rd_adc2_tp_low())
+            .field("rd_adc2_tp_high", &self.rd_adc2_tp_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_RDATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk3_rdata4.rs b/esp32/src/efuse/blk3_rdata4.rs
index 7fb3912852..4dfb9b4d32 100644
--- a/esp32/src/efuse/blk3_rdata4.rs
+++ b/esp32/src/efuse/blk3_rdata4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_RDATA4")
-            .field(
-                "rd_secure_version",
-                &format_args!("{}", self.rd_secure_version().bits()),
-            )
+            .field("rd_secure_version", &self.rd_secure_version())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_RDATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_rdata4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_RDATA4_SPEC;
 impl crate::RegisterSpec for BLK3_RDATA4_SPEC {
diff --git a/esp32/src/efuse/blk3_rdata5.rs b/esp32/src/efuse/blk3_rdata5.rs
index 152ee564f0..4252330558 100644
--- a/esp32/src/efuse/blk3_rdata5.rs
+++ b/esp32/src/efuse/blk3_rdata5.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_RDATA5")
-            .field(
-                "reserved_3_160",
-                &format_args!("{}", self.reserved_3_160().bits()),
-            )
-            .field(
-                "rd_mac_version",
-                &format_args!("{}", self.rd_mac_version().bits()),
-            )
+            .field("reserved_3_160", &self.reserved_3_160())
+            .field("rd_mac_version", &self.rd_mac_version())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_RDATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_rdata5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_RDATA5_SPEC;
 impl crate::RegisterSpec for BLK3_RDATA5_SPEC {
diff --git a/esp32/src/efuse/blk3_rdata6.rs b/esp32/src/efuse/blk3_rdata6.rs
index c1656c8777..63b83d269d 100644
--- a/esp32/src/efuse/blk3_rdata6.rs
+++ b/esp32/src/efuse/blk3_rdata6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_RDATA6")
-            .field(
-                "rd_blk3_reserved_6",
-                &format_args!("{}", self.rd_blk3_reserved_6().bits()),
-            )
+            .field("rd_blk3_reserved_6", &self.rd_blk3_reserved_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_RDATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_rdata6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_RDATA6_SPEC;
 impl crate::RegisterSpec for BLK3_RDATA6_SPEC {
diff --git a/esp32/src/efuse/blk3_rdata7.rs b/esp32/src/efuse/blk3_rdata7.rs
index cf219b0bf5..46594c6662 100644
--- a/esp32/src/efuse/blk3_rdata7.rs
+++ b/esp32/src/efuse/blk3_rdata7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_RDATA7")
-            .field(
-                "rd_blk3_reserved_7",
-                &format_args!("{}", self.rd_blk3_reserved_7().bits()),
-            )
+            .field("rd_blk3_reserved_7", &self.rd_blk3_reserved_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_RDATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_rdata7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_RDATA7_SPEC;
 impl crate::RegisterSpec for BLK3_RDATA7_SPEC {
diff --git a/esp32/src/efuse/blk3_wdata0.rs b/esp32/src/efuse/blk3_wdata0.rs
index e597f97bd4..0dc4e8158e 100644
--- a/esp32/src/efuse/blk3_wdata0.rs
+++ b/esp32/src/efuse/blk3_wdata0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_WDATA0")
-            .field("blk3_din0", &format_args!("{}", self.blk3_din0().bits()))
+            .field("blk3_din0", &self.blk3_din0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_WDATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk3_wdata1.rs b/esp32/src/efuse/blk3_wdata1.rs
index eeb7fcdbff..6ce0877da9 100644
--- a/esp32/src/efuse/blk3_wdata1.rs
+++ b/esp32/src/efuse/blk3_wdata1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_WDATA1")
-            .field("blk3_din1", &format_args!("{}", self.blk3_din1().bits()))
+            .field("blk3_din1", &self.blk3_din1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_WDATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk3_wdata2.rs b/esp32/src/efuse/blk3_wdata2.rs
index 78caa69144..3e0ee8abaa 100644
--- a/esp32/src/efuse/blk3_wdata2.rs
+++ b/esp32/src/efuse/blk3_wdata2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_WDATA2")
-            .field("blk3_din2", &format_args!("{}", self.blk3_din2().bits()))
+            .field("blk3_din2", &self.blk3_din2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_WDATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk3_wdata3.rs b/esp32/src/efuse/blk3_wdata3.rs
index 9b0825fda3..fc81ab6e47 100644
--- a/esp32/src/efuse/blk3_wdata3.rs
+++ b/esp32/src/efuse/blk3_wdata3.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_WDATA3")
-            .field(
-                "adc1_tp_low",
-                &format_args!("{}", self.adc1_tp_low().bits()),
-            )
-            .field(
-                "adc1_tp_high",
-                &format_args!("{}", self.adc1_tp_high().bits()),
-            )
-            .field(
-                "adc2_tp_low",
-                &format_args!("{}", self.adc2_tp_low().bits()),
-            )
-            .field(
-                "adc2_tp_high",
-                &format_args!("{}", self.adc2_tp_high().bits()),
-            )
+            .field("adc1_tp_low", &self.adc1_tp_low())
+            .field("adc1_tp_high", &self.adc1_tp_high())
+            .field("adc2_tp_low", &self.adc2_tp_low())
+            .field("adc2_tp_high", &self.adc2_tp_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_WDATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk3_wdata4.rs b/esp32/src/efuse/blk3_wdata4.rs
index ff838dc187..5da5f791b9 100644
--- a/esp32/src/efuse/blk3_wdata4.rs
+++ b/esp32/src/efuse/blk3_wdata4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_WDATA4")
-            .field(
-                "secure_version",
-                &format_args!("{}", self.secure_version().bits()),
-            )
+            .field("secure_version", &self.secure_version())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_WDATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_wdata4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_WDATA4_SPEC;
 impl crate::RegisterSpec for BLK3_WDATA4_SPEC {
diff --git a/esp32/src/efuse/blk3_wdata5.rs b/esp32/src/efuse/blk3_wdata5.rs
index a7efeb7848..bce117f76b 100644
--- a/esp32/src/efuse/blk3_wdata5.rs
+++ b/esp32/src/efuse/blk3_wdata5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_WDATA5")
-            .field("blk3_din5", &format_args!("{}", self.blk3_din5().bits()))
+            .field("blk3_din5", &self.blk3_din5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_WDATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk3_wdata6.rs b/esp32/src/efuse/blk3_wdata6.rs
index 988cdce822..7a983b589d 100644
--- a/esp32/src/efuse/blk3_wdata6.rs
+++ b/esp32/src/efuse/blk3_wdata6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_WDATA6")
-            .field("blk3_din6", &format_args!("{}", self.blk3_din6().bits()))
+            .field("blk3_din6", &self.blk3_din6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_WDATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/blk3_wdata7.rs b/esp32/src/efuse/blk3_wdata7.rs
index 4cb517a638..0f3f854b9f 100644
--- a/esp32/src/efuse/blk3_wdata7.rs
+++ b/esp32/src/efuse/blk3_wdata7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_WDATA7")
-            .field("blk3_din7", &format_args!("{}", self.blk3_din7().bits()))
+            .field("blk3_din7", &self.blk3_din7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_WDATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/efuse/clk.rs b/esp32/src/efuse/clk.rs
index 4afc8d1d4b..3ba629398e 100644
--- a/esp32/src/efuse/clk.rs
+++ b/esp32/src/efuse/clk.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK")
-            .field("sel0", &format_args!("{}", self.sel0().bits()))
-            .field("sel1", &format_args!("{}", self.sel1().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("sel0", &self.sel0())
+            .field("sel1", &self.sel1())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/efuse/cmd.rs b/esp32/src/efuse/cmd.rs
index 36c37288ef..fc1e5026e2 100644
--- a/esp32/src/efuse/cmd.rs
+++ b/esp32/src/efuse/cmd.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("read_cmd", &format_args!("{}", self.read_cmd().bit()))
-            .field("pgm_cmd", &format_args!("{}", self.pgm_cmd().bit()))
+            .field("read_cmd", &self.read_cmd())
+            .field("pgm_cmd", &self.pgm_cmd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/efuse/conf.rs b/esp32/src/efuse/conf.rs
index 1cac8ad8d0..bfd8fe3b38 100644
--- a/esp32/src/efuse/conf.rs
+++ b/esp32/src/efuse/conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("op_code", &format_args!("{}", self.op_code().bits()))
-            .field(
-                "force_no_wr_rd_dis",
-                &format_args!("{}", self.force_no_wr_rd_dis().bit()),
-            )
+            .field("op_code", &self.op_code())
+            .field("force_no_wr_rd_dis", &self.force_no_wr_rd_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32/src/efuse/dac_conf.rs b/esp32/src/efuse/dac_conf.rs
index 9d01da9404..16bfdce25b 100644
--- a/esp32/src/efuse/dac_conf.rs
+++ b/esp32/src/efuse/dac_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DAC_CONF")
-            .field(
-                "dac_clk_div",
-                &format_args!("{}", self.dac_clk_div().bits()),
-            )
-            .field(
-                "dac_clk_pad_sel",
-                &format_args!("{}", self.dac_clk_pad_sel().bit()),
-            )
+            .field("dac_clk_div", &self.dac_clk_div())
+            .field("dac_clk_pad_sel", &self.dac_clk_pad_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DAC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/efuse/date.rs b/esp32/src/efuse/date.rs
index d7814bb833..fce4be761e 100644
--- a/esp32/src/efuse/date.rs
+++ b/esp32/src/efuse/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/efuse/dec_status.rs b/esp32/src/efuse/dec_status.rs
index ccd7e2eedb..e5fa212ccb 100644
--- a/esp32/src/efuse/dec_status.rs
+++ b/esp32/src/efuse/dec_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEC_STATUS")
-            .field(
-                "dec_warnings",
-                &format_args!("{}", self.dec_warnings().bits()),
-            )
+            .field("dec_warnings", &self.dec_warnings())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEC_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dec_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEC_STATUS_SPEC;
 impl crate::RegisterSpec for DEC_STATUS_SPEC {
diff --git a/esp32/src/efuse/int_ena.rs b/esp32/src/efuse/int_ena.rs
index 52a92388d3..d4ae4e125d 100644
--- a/esp32/src/efuse/int_ena.rs
+++ b/esp32/src/efuse/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/efuse/int_raw.rs b/esp32/src/efuse/int_raw.rs
index 39b2200bf4..bf3e8d12f1 100644
--- a/esp32/src/efuse/int_raw.rs
+++ b/esp32/src/efuse/int_raw.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32/src/efuse/int_st.rs b/esp32/src/efuse/int_st.rs
index cfcde2ea27..611c866476 100644
--- a/esp32/src/efuse/int_st.rs
+++ b/esp32/src/efuse/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32/src/efuse/status.rs b/esp32/src/efuse/status.rs
index 64202ba5da..e9570f316e 100644
--- a/esp32/src/efuse/status.rs
+++ b/esp32/src/efuse/status.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("debug", &format_args!("{}", self.debug().bits()))
+            .field("debug", &self.debug())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32/src/emac_dma/dmabusmode.rs b/esp32/src/emac_dma/dmabusmode.rs
index 1e23293cc7..f949375330 100644
--- a/esp32/src/emac_dma/dmabusmode.rs
+++ b/esp32/src/emac_dma/dmabusmode.rs
@@ -116,42 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMABUSMODE")
-            .field("sw_rst", &format_args!("{}", self.sw_rst().bit()))
-            .field("dma_arb_sch", &format_args!("{}", self.dma_arb_sch().bit()))
-            .field(
-                "desc_skip_len",
-                &format_args!("{}", self.desc_skip_len().bits()),
-            )
-            .field(
-                "alt_desc_size",
-                &format_args!("{}", self.alt_desc_size().bit()),
-            )
-            .field(
-                "prog_burst_len",
-                &format_args!("{}", self.prog_burst_len().bits()),
-            )
-            .field("pri_ratio", &format_args!("{}", self.pri_ratio().bits()))
-            .field("fixed_burst", &format_args!("{}", self.fixed_burst().bit()))
-            .field("rx_dma_pbl", &format_args!("{}", self.rx_dma_pbl().bits()))
-            .field("use_sep_pbl", &format_args!("{}", self.use_sep_pbl().bit()))
-            .field("pblx8_mode", &format_args!("{}", self.pblx8_mode().bit()))
-            .field(
-                "dmaaddralibea",
-                &format_args!("{}", self.dmaaddralibea().bit()),
-            )
-            .field(
-                "dmamixedburst",
-                &format_args!("{}", self.dmamixedburst().bit()),
-            )
+            .field("sw_rst", &self.sw_rst())
+            .field("dma_arb_sch", &self.dma_arb_sch())
+            .field("desc_skip_len", &self.desc_skip_len())
+            .field("alt_desc_size", &self.alt_desc_size())
+            .field("prog_burst_len", &self.prog_burst_len())
+            .field("pri_ratio", &self.pri_ratio())
+            .field("fixed_burst", &self.fixed_burst())
+            .field("rx_dma_pbl", &self.rx_dma_pbl())
+            .field("use_sep_pbl", &self.use_sep_pbl())
+            .field("pblx8_mode", &self.pblx8_mode())
+            .field("dmaaddralibea", &self.dmaaddralibea())
+            .field("dmamixedburst", &self.dmamixedburst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMABUSMODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When this bit is set the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC you should read a zero (0) value in this bit."]
     #[inline(always)]
diff --git a/esp32/src/emac_dma/dmain_en.rs b/esp32/src/emac_dma/dmain_en.rs
index edd0059b14..42bfc8dfc5 100644
--- a/esp32/src/emac_dma/dmain_en.rs
+++ b/esp32/src/emac_dma/dmain_en.rs
@@ -143,30 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMAIN_EN")
-            .field("dmain_tie", &format_args!("{}", self.dmain_tie().bit()))
-            .field("dmain_tse", &format_args!("{}", self.dmain_tse().bit()))
-            .field("dmain_tbue", &format_args!("{}", self.dmain_tbue().bit()))
-            .field("dmain_tjte", &format_args!("{}", self.dmain_tjte().bit()))
-            .field("dmain_oie", &format_args!("{}", self.dmain_oie().bit()))
-            .field("dmain_uie", &format_args!("{}", self.dmain_uie().bit()))
-            .field("dmain_rie", &format_args!("{}", self.dmain_rie().bit()))
-            .field("dmain_rbue", &format_args!("{}", self.dmain_rbue().bit()))
-            .field("dmain_rse", &format_args!("{}", self.dmain_rse().bit()))
-            .field("dmain_rwte", &format_args!("{}", self.dmain_rwte().bit()))
-            .field("dmain_etie", &format_args!("{}", self.dmain_etie().bit()))
-            .field("dmain_fbee", &format_args!("{}", self.dmain_fbee().bit()))
-            .field("dmain_erie", &format_args!("{}", self.dmain_erie().bit()))
-            .field("dmain_aise", &format_args!("{}", self.dmain_aise().bit()))
-            .field("dmain_nise", &format_args!("{}", self.dmain_nise().bit()))
+            .field("dmain_tie", &self.dmain_tie())
+            .field("dmain_tse", &self.dmain_tse())
+            .field("dmain_tbue", &self.dmain_tbue())
+            .field("dmain_tjte", &self.dmain_tjte())
+            .field("dmain_oie", &self.dmain_oie())
+            .field("dmain_uie", &self.dmain_uie())
+            .field("dmain_rie", &self.dmain_rie())
+            .field("dmain_rbue", &self.dmain_rbue())
+            .field("dmain_rse", &self.dmain_rse())
+            .field("dmain_rwte", &self.dmain_rwte())
+            .field("dmain_etie", &self.dmain_etie())
+            .field("dmain_fbee", &self.dmain_fbee())
+            .field("dmain_erie", &self.dmain_erie())
+            .field("dmain_aise", &self.dmain_aise())
+            .field("dmain_nise", &self.dmain_nise())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMAIN_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When this bit is set with Normal Interrupt Summary Enable (Bit\\[16\\]) the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled."]
     #[inline(always)]
diff --git a/esp32/src/emac_dma/dmamissedfr.rs b/esp32/src/emac_dma/dmamissedfr.rs
index 635d9e2935..a3c6c1c090 100644
--- a/esp32/src/emac_dma/dmamissedfr.rs
+++ b/esp32/src/emac_dma/dmamissedfr.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMAMISSEDFR")
-            .field("missed_fc", &format_args!("{}", self.missed_fc().bits()))
-            .field(
-                "overflow_bmfc",
-                &format_args!("{}", self.overflow_bmfc().bit()),
-            )
-            .field(
-                "overflow_fc",
-                &format_args!("{}", self.overflow_fc().bits()),
-            )
-            .field(
-                "overflow_bfoc",
-                &format_args!("{}", self.overflow_bfoc().bit()),
-            )
+            .field("missed_fc", &self.missed_fc())
+            .field("overflow_bmfc", &self.overflow_bmfc())
+            .field("overflow_fc", &self.overflow_fc())
+            .field("overflow_bfoc", &self.overflow_bfoc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMAMISSEDFR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read."]
     #[inline(always)]
diff --git a/esp32/src/emac_dma/dmaoperation_mode.rs b/esp32/src/emac_dma/dmaoperation_mode.rs
index 78d2f54526..d522e2ade1 100644
--- a/esp32/src/emac_dma/dmaoperation_mode.rs
+++ b/esp32/src/emac_dma/dmaoperation_mode.rs
@@ -125,61 +125,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMAOPERATION_MODE")
-            .field(
-                "start_stop_rx",
-                &format_args!("{}", self.start_stop_rx().bit()),
-            )
-            .field(
-                "opt_second_frame",
-                &format_args!("{}", self.opt_second_frame().bit()),
-            )
-            .field(
-                "rx_thresh_ctrl",
-                &format_args!("{}", self.rx_thresh_ctrl().bits()),
-            )
-            .field("drop_gfrm", &format_args!("{}", self.drop_gfrm().bit()))
-            .field(
-                "fwd_under_gf",
-                &format_args!("{}", self.fwd_under_gf().bit()),
-            )
-            .field(
-                "fwd_err_frame",
-                &format_args!("{}", self.fwd_err_frame().bit()),
-            )
+            .field("start_stop_rx", &self.start_stop_rx())
+            .field("opt_second_frame", &self.opt_second_frame())
+            .field("rx_thresh_ctrl", &self.rx_thresh_ctrl())
+            .field("drop_gfrm", &self.drop_gfrm())
+            .field("fwd_under_gf", &self.fwd_under_gf())
+            .field("fwd_err_frame", &self.fwd_err_frame())
             .field(
                 "start_stop_transmission_command",
-                &format_args!("{}", self.start_stop_transmission_command().bit()),
-            )
-            .field(
-                "tx_thresh_ctrl",
-                &format_args!("{}", self.tx_thresh_ctrl().bits()),
-            )
-            .field(
-                "flush_tx_fifo",
-                &format_args!("{}", self.flush_tx_fifo().bit()),
-            )
-            .field("tx_str_fwd", &format_args!("{}", self.tx_str_fwd().bit()))
-            .field(
-                "dis_flush_recv_frames",
-                &format_args!("{}", self.dis_flush_recv_frames().bit()),
-            )
-            .field(
-                "rx_store_forward",
-                &format_args!("{}", self.rx_store_forward().bit()),
-            )
-            .field(
-                "dis_drop_tcpip_err_fram",
-                &format_args!("{}", self.dis_drop_tcpip_err_fram().bit()),
+                &self.start_stop_transmission_command(),
             )
+            .field("tx_thresh_ctrl", &self.tx_thresh_ctrl())
+            .field("flush_tx_fifo", &self.flush_tx_fifo())
+            .field("tx_str_fwd", &self.tx_str_fwd())
+            .field("dis_flush_recv_frames", &self.dis_flush_recv_frames())
+            .field("rx_store_forward", &self.rx_store_forward())
+            .field("dis_drop_tcpip_err_fram", &self.dis_drop_tcpip_err_fram())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMAOPERATION_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - When this bit is set the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.When this bit is cleared the Rx DMA operation is stopped after the transfer of the current frame."]
     #[inline(always)]
diff --git a/esp32/src/emac_dma/dmarintwdtimer.rs b/esp32/src/emac_dma/dmarintwdtimer.rs
index d1fff87771..beef3fe098 100644
--- a/esp32/src/emac_dma/dmarintwdtimer.rs
+++ b/esp32/src/emac_dma/dmarintwdtimer.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMARINTWDTIMER")
-            .field("riwtc", &format_args!("{}", self.riwtc().bits()))
+            .field("riwtc", &self.riwtc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMARINTWDTIMER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI(RECV_INT) status bit is not set because of the setting in the corresponding descriptor RDES1\\[31\\]. When the watchdog timer runs out the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1\\[31\\] of any received frame."]
     #[inline(always)]
diff --git a/esp32/src/emac_dma/dmarxbaseaddr.rs b/esp32/src/emac_dma/dmarxbaseaddr.rs
index c8eb2df344..066256227d 100644
--- a/esp32/src/emac_dma/dmarxbaseaddr.rs
+++ b/esp32/src/emac_dma/dmarxbaseaddr.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMARXBASEADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB Bits\\[1:0\\] are ignored and internally taken as all-zero by the DMA. Therefore these LSB bits are read-only.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmarxbaseaddr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmarxbaseaddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMARXBASEADDR_SPEC;
diff --git a/esp32/src/emac_dma/dmarxcurraddr_buf.rs b/esp32/src/emac_dma/dmarxcurraddr_buf.rs
index 9d64d6e6b4..daab9a238b 100644
--- a/esp32/src/emac_dma/dmarxcurraddr_buf.rs
+++ b/esp32/src/emac_dma/dmarxcurraddr_buf.rs
@@ -6,12 +6,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMARXCURRADDR_BUF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmarxcurraddr_buf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMARXCURRADDR_BUF_SPEC;
 impl crate::RegisterSpec for DMARXCURRADDR_BUF_SPEC {
diff --git a/esp32/src/emac_dma/dmarxcurrdesc.rs b/esp32/src/emac_dma/dmarxcurrdesc.rs
index c8b3d87cff..8424cf8681 100644
--- a/esp32/src/emac_dma/dmarxcurrdesc.rs
+++ b/esp32/src/emac_dma/dmarxcurrdesc.rs
@@ -6,12 +6,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMARXCURRDESC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmarxcurrdesc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMARXCURRDESC_SPEC;
 impl crate::RegisterSpec for DMARXCURRDESC_SPEC {
diff --git a/esp32/src/emac_dma/dmarxpolldemand.rs b/esp32/src/emac_dma/dmarxpolldemand.rs
index f0b24ac12a..6ec724ff49 100644
--- a/esp32/src/emac_dma/dmarxpolldemand.rs
+++ b/esp32/src/emac_dma/dmarxpolldemand.rs
@@ -6,12 +6,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMARXPOLLDEMAND_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "When these bits are written with any value the DMA reads the current descriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is not available (owned by the Host) the reception returns to the Suspended state and Bit\\[7\\] (RU) of Status Register is asserted. If the descriptor is available the Rx DMA returns to the active state.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmarxpolldemand::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMARXPOLLDEMAND_SPEC;
 impl crate::RegisterSpec for DMARXPOLLDEMAND_SPEC {
diff --git a/esp32/src/emac_dma/dmastatus.rs b/esp32/src/emac_dma/dmastatus.rs
index 44abc55a7b..37519c3b2b 100644
--- a/esp32/src/emac_dma/dmastatus.rs
+++ b/esp32/src/emac_dma/dmastatus.rs
@@ -188,74 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMASTATUS")
-            .field("trans_int", &format_args!("{}", self.trans_int().bit()))
-            .field(
-                "trans_proc_stop",
-                &format_args!("{}", self.trans_proc_stop().bit()),
-            )
-            .field(
-                "trans_buf_unavail",
-                &format_args!("{}", self.trans_buf_unavail().bit()),
-            )
-            .field(
-                "trans_jabber_to",
-                &format_args!("{}", self.trans_jabber_to().bit()),
-            )
-            .field("recv_ovflow", &format_args!("{}", self.recv_ovflow().bit()))
-            .field(
-                "trans_undflow",
-                &format_args!("{}", self.trans_undflow().bit()),
-            )
-            .field("recv_int", &format_args!("{}", self.recv_int().bit()))
-            .field(
-                "recv_buf_unavail",
-                &format_args!("{}", self.recv_buf_unavail().bit()),
-            )
-            .field(
-                "recv_proc_stop",
-                &format_args!("{}", self.recv_proc_stop().bit()),
-            )
-            .field("recv_wdt_to", &format_args!("{}", self.recv_wdt_to().bit()))
-            .field(
-                "early_trans_int",
-                &format_args!("{}", self.early_trans_int().bit()),
-            )
-            .field(
-                "fatal_bus_err_int",
-                &format_args!("{}", self.fatal_bus_err_int().bit()),
-            )
-            .field(
-                "early_recv_int",
-                &format_args!("{}", self.early_recv_int().bit()),
-            )
-            .field(
-                "abn_int_summ",
-                &format_args!("{}", self.abn_int_summ().bit()),
-            )
-            .field(
-                "norm_int_summ",
-                &format_args!("{}", self.norm_int_summ().bit()),
-            )
-            .field(
-                "recv_proc_state",
-                &format_args!("{}", self.recv_proc_state().bits()),
-            )
-            .field(
-                "trans_proc_state",
-                &format_args!("{}", self.trans_proc_state().bits()),
-            )
-            .field("error_bits", &format_args!("{}", self.error_bits().bits()))
-            .field("pmt_int", &format_args!("{}", self.pmt_int().bit()))
-            .field("ts_tri_int", &format_args!("{}", self.ts_tri_int().bit()))
+            .field("trans_int", &self.trans_int())
+            .field("trans_proc_stop", &self.trans_proc_stop())
+            .field("trans_buf_unavail", &self.trans_buf_unavail())
+            .field("trans_jabber_to", &self.trans_jabber_to())
+            .field("recv_ovflow", &self.recv_ovflow())
+            .field("trans_undflow", &self.trans_undflow())
+            .field("recv_int", &self.recv_int())
+            .field("recv_buf_unavail", &self.recv_buf_unavail())
+            .field("recv_proc_stop", &self.recv_proc_stop())
+            .field("recv_wdt_to", &self.recv_wdt_to())
+            .field("early_trans_int", &self.early_trans_int())
+            .field("fatal_bus_err_int", &self.fatal_bus_err_int())
+            .field("early_recv_int", &self.early_recv_int())
+            .field("abn_int_summ", &self.abn_int_summ())
+            .field("norm_int_summ", &self.norm_int_summ())
+            .field("recv_proc_state", &self.recv_proc_state())
+            .field("trans_proc_state", &self.trans_proc_state())
+            .field("error_bits", &self.error_bits())
+            .field("pmt_int", &self.pmt_int())
+            .field("ts_tri_int", &self.ts_tri_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMASTATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit indicates that the frame transmission is complete. When transmission is complete Bit\\[31\\] (OWN) of TDES0 is reset and the specific frame status information is updated in the Descriptor."]
     #[inline(always)]
diff --git a/esp32/src/emac_dma/dmatxbaseaddr.rs b/esp32/src/emac_dma/dmatxbaseaddr.rs
index bfcefee116..24fc2e4168 100644
--- a/esp32/src/emac_dma/dmatxbaseaddr.rs
+++ b/esp32/src/emac_dma/dmatxbaseaddr.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMATXBASEADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB Bits\\[1:0\\] are ignored and are internally taken as all-zero by the DMA.Therefore these LSB bits are read-only.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmatxbaseaddr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmatxbaseaddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMATXBASEADDR_SPEC;
diff --git a/esp32/src/emac_dma/dmatxcurraddr_buf.rs b/esp32/src/emac_dma/dmatxcurraddr_buf.rs
index c05bf759f1..795ebed685 100644
--- a/esp32/src/emac_dma/dmatxcurraddr_buf.rs
+++ b/esp32/src/emac_dma/dmatxcurraddr_buf.rs
@@ -6,12 +6,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMATXCURRADDR_BUF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmatxcurraddr_buf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMATXCURRADDR_BUF_SPEC;
 impl crate::RegisterSpec for DMATXCURRADDR_BUF_SPEC {
diff --git a/esp32/src/emac_dma/dmatxcurrdesc.rs b/esp32/src/emac_dma/dmatxcurrdesc.rs
index f256d4f866..7443bbb0bd 100644
--- a/esp32/src/emac_dma/dmatxcurrdesc.rs
+++ b/esp32/src/emac_dma/dmatxcurrdesc.rs
@@ -6,12 +6,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMATXCURRDESC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmatxcurrdesc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMATXCURRDESC_SPEC;
 impl crate::RegisterSpec for DMATXCURRDESC_SPEC {
diff --git a/esp32/src/emac_dma/dmatxpolldemand.rs b/esp32/src/emac_dma/dmatxpolldemand.rs
index f77b606044..7fa900ba61 100644
--- a/esp32/src/emac_dma/dmatxpolldemand.rs
+++ b/esp32/src/emac_dma/dmatxpolldemand.rs
@@ -6,12 +6,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMATXPOLLDEMAND_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "When these bits are written with any value the DMA reads the current descriptor to which the Register (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host) the transmission returns to the suspend state and Bit\\[2\\] (TU) of Status Register is asserted. If the descriptor is available the transmission resumes.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmatxpolldemand::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMATXPOLLDEMAND_SPEC;
 impl crate::RegisterSpec for DMATXPOLLDEMAND_SPEC {
diff --git a/esp32/src/emac_ext/ex_clk_ctrl.rs b/esp32/src/emac_ext/ex_clk_ctrl.rs
index aceec78d35..c2a0264883 100644
--- a/esp32/src/emac_ext/ex_clk_ctrl.rs
+++ b/esp32/src/emac_ext/ex_clk_ctrl.rs
@@ -62,30 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EX_CLK_CTRL")
-            .field("ext_en", &format_args!("{}", self.ext_en().bit()))
-            .field("int_en", &format_args!("{}", self.int_en().bit()))
-            .field(
-                "rx_125_clk_en",
-                &format_args!("{}", self.rx_125_clk_en().bit()),
-            )
-            .field(
-                "mii_clk_tx_en",
-                &format_args!("{}", self.mii_clk_tx_en().bit()),
-            )
-            .field(
-                "mii_clk_rx_en",
-                &format_args!("{}", self.mii_clk_rx_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("ext_en", &self.ext_en())
+            .field("int_en", &self.int_en())
+            .field("rx_125_clk_en", &self.rx_125_clk_en())
+            .field("mii_clk_tx_en", &self.mii_clk_tx_en())
+            .field("mii_clk_rx_en", &self.mii_clk_rx_en())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EX_CLK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/emac_ext/ex_clkout_conf.rs b/esp32/src/emac_ext/ex_clkout_conf.rs
index ce3d85cae2..5ed652a888 100644
--- a/esp32/src/emac_ext/ex_clkout_conf.rs
+++ b/esp32/src/emac_ext/ex_clkout_conf.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EX_CLKOUT_CONF")
-            .field("div_num", &format_args!("{}", self.div_num().bits()))
-            .field("h_div_num", &format_args!("{}", self.h_div_num().bits()))
-            .field("dly_num", &format_args!("{}", self.dly_num().bits()))
+            .field("div_num", &self.div_num())
+            .field("h_div_num", &self.h_div_num())
+            .field("dly_num", &self.dly_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EX_CLKOUT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32/src/emac_ext/ex_date.rs b/esp32/src/emac_ext/ex_date.rs
index 9ba70d8e60..820041c543 100644
--- a/esp32/src/emac_ext/ex_date.rs
+++ b/esp32/src/emac_ext/ex_date.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EX_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ex_date::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ex_date::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EX_DATE_SPEC;
diff --git a/esp32/src/emac_ext/ex_oscclk_conf.rs b/esp32/src/emac_ext/ex_oscclk_conf.rs
index 052c0fe0fb..dbe8ebd687 100644
--- a/esp32/src/emac_ext/ex_oscclk_conf.rs
+++ b/esp32/src/emac_ext/ex_oscclk_conf.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EX_OSCCLK_CONF")
-            .field(
-                "div_num_10m",
-                &format_args!("{}", self.div_num_10m().bits()),
-            )
-            .field(
-                "h_div_num_10m",
-                &format_args!("{}", self.h_div_num_10m().bits()),
-            )
-            .field(
-                "div_num_100m",
-                &format_args!("{}", self.div_num_100m().bits()),
-            )
-            .field(
-                "h_div_num_100m",
-                &format_args!("{}", self.h_div_num_100m().bits()),
-            )
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bit()))
+            .field("div_num_10m", &self.div_num_10m())
+            .field("h_div_num_10m", &self.h_div_num_10m())
+            .field("div_num_100m", &self.div_num_100m())
+            .field("h_div_num_100m", &self.h_div_num_100m())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EX_OSCCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/emac_ext/ex_phyinf_conf.rs b/esp32/src/emac_ext/ex_phyinf_conf.rs
index 8fa1978f30..93cd096b2d 100644
--- a/esp32/src/emac_ext/ex_phyinf_conf.rs
+++ b/esp32/src/emac_ext/ex_phyinf_conf.rs
@@ -107,53 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EX_PHYINF_CONF")
-            .field(
-                "int_revmii_rx_clk_sel",
-                &format_args!("{}", self.int_revmii_rx_clk_sel().bit()),
-            )
-            .field(
-                "ext_revmii_rx_clk_sel",
-                &format_args!("{}", self.ext_revmii_rx_clk_sel().bit()),
-            )
-            .field(
-                "sbd_flowctrl",
-                &format_args!("{}", self.sbd_flowctrl().bit()),
-            )
-            .field(
-                "core_phy_addr",
-                &format_args!("{}", self.core_phy_addr().bits()),
-            )
-            .field(
-                "revmii_phy_addr",
-                &format_args!("{}", self.revmii_phy_addr().bits()),
-            )
-            .field(
-                "phy_intf_sel",
-                &format_args!("{}", self.phy_intf_sel().bits()),
-            )
-            .field("ss_mode", &format_args!("{}", self.ss_mode().bit()))
-            .field(
-                "sbd_clk_gating_en",
-                &format_args!("{}", self.sbd_clk_gating_en().bit()),
-            )
-            .field("pmt_ctrl_en", &format_args!("{}", self.pmt_ctrl_en().bit()))
-            .field(
-                "scr_smi_dly_rx_sync",
-                &format_args!("{}", self.scr_smi_dly_rx_sync().bit()),
-            )
-            .field(
-                "tx_err_out_en",
-                &format_args!("{}", self.tx_err_out_en().bit()),
-            )
+            .field("int_revmii_rx_clk_sel", &self.int_revmii_rx_clk_sel())
+            .field("ext_revmii_rx_clk_sel", &self.ext_revmii_rx_clk_sel())
+            .field("sbd_flowctrl", &self.sbd_flowctrl())
+            .field("core_phy_addr", &self.core_phy_addr())
+            .field("revmii_phy_addr", &self.revmii_phy_addr())
+            .field("phy_intf_sel", &self.phy_intf_sel())
+            .field("ss_mode", &self.ss_mode())
+            .field("sbd_clk_gating_en", &self.sbd_clk_gating_en())
+            .field("pmt_ctrl_en", &self.pmt_ctrl_en())
+            .field("scr_smi_dly_rx_sync", &self.scr_smi_dly_rx_sync())
+            .field("tx_err_out_en", &self.tx_err_out_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EX_PHYINF_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/emac_ext/pd_sel.rs b/esp32/src/emac_ext/pd_sel.rs
index 35371c9329..89118e6d3c 100644
--- a/esp32/src/emac_ext/pd_sel.rs
+++ b/esp32/src/emac_ext/pd_sel.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PD_SEL")
-            .field("ram_pd_en", &format_args!("{}", self.ram_pd_en().bits()))
+            .field("ram_pd_en", &self.ram_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PD_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/emacaddr0high.rs b/esp32/src/emac_mac/emacaddr0high.rs
index 18a54697d5..510c03dc18 100644
--- a/esp32/src/emac_mac/emacaddr0high.rs
+++ b/esp32/src/emac_mac/emacaddr0high.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACADDR0HIGH")
-            .field(
-                "address0_hi",
-                &format_args!("{}", self.address0_hi().bits()),
-            )
-            .field(
-                "address_enable0",
-                &format_args!("{}", self.address_enable0().bit()),
-            )
+            .field("address0_hi", &self.address0_hi())
+            .field("address_enable0", &self.address_enable0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR0HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits (47:32) of the first 6-byte MAC address.The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames."]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/emacaddr0low.rs b/esp32/src/emac_mac/emacaddr0low.rs
index 0d5128bf1f..09efe24994 100644
--- a/esp32/src/emac_mac/emacaddr0low.rs
+++ b/esp32/src/emac_mac/emacaddr0low.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR0LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emacaddr0low::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emacaddr0low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EMACADDR0LOW_SPEC;
diff --git a/esp32/src/emac_mac/emacaddr1high.rs b/esp32/src/emac_mac/emacaddr1high.rs
index 2fe3b60836..e14460b81d 100644
--- a/esp32/src/emac_mac/emacaddr1high.rs
+++ b/esp32/src/emac_mac/emacaddr1high.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACADDR1HIGH")
-            .field(
-                "mac_address1_hi",
-                &format_args!("{}", self.mac_address1_hi().bits()),
-            )
-            .field(
-                "mask_byte_control",
-                &format_args!("{}", self.mask_byte_control().bits()),
-            )
-            .field(
-                "source_address",
-                &format_args!("{}", self.source_address().bit()),
-            )
-            .field(
-                "address_enable1",
-                &format_args!("{}", self.address_enable1().bit()),
-            )
+            .field("mac_address1_hi", &self.mac_address1_hi())
+            .field("mask_byte_control", &self.mask_byte_control())
+            .field("source_address", &self.source_address())
+            .field("address_enable1", &self.address_enable1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR1HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits Bits\\[47:32\\] of the second 6-byte MAC Address."]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/emacaddr1low.rs b/esp32/src/emac_mac/emacaddr1low.rs
index 852b5d2812..49179334cd 100644
--- a/esp32/src/emac_mac/emacaddr1low.rs
+++ b/esp32/src/emac_mac/emacaddr1low.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR1LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "This field contains the lower 32 bits of the second 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emacaddr1low::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emacaddr1low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EMACADDR1LOW_SPEC;
diff --git a/esp32/src/emac_mac/emacaddr2high.rs b/esp32/src/emac_mac/emacaddr2high.rs
index 9384477418..fc753c4e0d 100644
--- a/esp32/src/emac_mac/emacaddr2high.rs
+++ b/esp32/src/emac_mac/emacaddr2high.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACADDR2HIGH")
-            .field(
-                "mac_address2_hi",
-                &format_args!("{}", self.mac_address2_hi().bits()),
-            )
-            .field(
-                "mask_byte_control2",
-                &format_args!("{}", self.mask_byte_control2().bits()),
-            )
-            .field(
-                "source_address2",
-                &format_args!("{}", self.source_address2().bit()),
-            )
-            .field(
-                "address_enable2",
-                &format_args!("{}", self.address_enable2().bit()),
-            )
+            .field("mac_address2_hi", &self.mac_address2_hi())
+            .field("mask_byte_control2", &self.mask_byte_control2())
+            .field("source_address2", &self.source_address2())
+            .field("address_enable2", &self.address_enable2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR2HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits Bits\\[47:32\\] of the third 6-byte MAC address."]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/emacaddr2low.rs b/esp32/src/emac_mac/emacaddr2low.rs
index 9b08fac5bb..e4042b72f9 100644
--- a/esp32/src/emac_mac/emacaddr2low.rs
+++ b/esp32/src/emac_mac/emacaddr2low.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR2LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "This field contains the lower 32 bits of the third 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emacaddr2low::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emacaddr2low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EMACADDR2LOW_SPEC;
diff --git a/esp32/src/emac_mac/emacaddr3high.rs b/esp32/src/emac_mac/emacaddr3high.rs
index d32f5b0fa6..4ad865fc34 100644
--- a/esp32/src/emac_mac/emacaddr3high.rs
+++ b/esp32/src/emac_mac/emacaddr3high.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACADDR3HIGH")
-            .field(
-                "mac_address3_hi",
-                &format_args!("{}", self.mac_address3_hi().bits()),
-            )
-            .field(
-                "mask_byte_control3",
-                &format_args!("{}", self.mask_byte_control3().bits()),
-            )
-            .field(
-                "source_address3",
-                &format_args!("{}", self.source_address3().bit()),
-            )
-            .field(
-                "address_enable3",
-                &format_args!("{}", self.address_enable3().bit()),
-            )
+            .field("mac_address3_hi", &self.mac_address3_hi())
+            .field("mask_byte_control3", &self.mask_byte_control3())
+            .field("source_address3", &self.source_address3())
+            .field("address_enable3", &self.address_enable3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR3HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits Bits\\[47:32\\] of the fourth 6-byte MAC address."]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/emacaddr3low.rs b/esp32/src/emac_mac/emacaddr3low.rs
index 6af450c2d4..06a871f9e4 100644
--- a/esp32/src/emac_mac/emacaddr3low.rs
+++ b/esp32/src/emac_mac/emacaddr3low.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR3LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "This field contains the lower 32 bits of the fourth 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emacaddr3low::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emacaddr3low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EMACADDR3LOW_SPEC;
diff --git a/esp32/src/emac_mac/emacaddr4high.rs b/esp32/src/emac_mac/emacaddr4high.rs
index 565c7f6701..465bdeba0a 100644
--- a/esp32/src/emac_mac/emacaddr4high.rs
+++ b/esp32/src/emac_mac/emacaddr4high.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACADDR4HIGH")
-            .field(
-                "mac_address4_hi",
-                &format_args!("{}", self.mac_address4_hi().bits()),
-            )
-            .field(
-                "mask_byte_control4",
-                &format_args!("{}", self.mask_byte_control4().bits()),
-            )
-            .field(
-                "source_address4",
-                &format_args!("{}", self.source_address4().bit()),
-            )
-            .field(
-                "address_enable4",
-                &format_args!("{}", self.address_enable4().bit()),
-            )
+            .field("mac_address4_hi", &self.mac_address4_hi())
+            .field("mask_byte_control4", &self.mask_byte_control4())
+            .field("source_address4", &self.source_address4())
+            .field("address_enable4", &self.address_enable4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR4HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits Bits\\[47:32\\] of the fifth 6-byte MAC address."]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/emacaddr4low.rs b/esp32/src/emac_mac/emacaddr4low.rs
index d47aa28b34..31ea9d3277 100644
--- a/esp32/src/emac_mac/emacaddr4low.rs
+++ b/esp32/src/emac_mac/emacaddr4low.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR4LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "This field contains the lower 32 bits of the fifth 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emacaddr4low::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emacaddr4low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EMACADDR4LOW_SPEC;
diff --git a/esp32/src/emac_mac/emacaddr5high.rs b/esp32/src/emac_mac/emacaddr5high.rs
index 73246c8b1c..119f2b80c7 100644
--- a/esp32/src/emac_mac/emacaddr5high.rs
+++ b/esp32/src/emac_mac/emacaddr5high.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACADDR5HIGH")
-            .field(
-                "mac_address5_hi",
-                &format_args!("{}", self.mac_address5_hi().bits()),
-            )
-            .field(
-                "mask_byte_control5",
-                &format_args!("{}", self.mask_byte_control5().bits()),
-            )
-            .field(
-                "source_address5",
-                &format_args!("{}", self.source_address5().bit()),
-            )
-            .field(
-                "address_enable5",
-                &format_args!("{}", self.address_enable5().bit()),
-            )
+            .field("mac_address5_hi", &self.mac_address5_hi())
+            .field("mask_byte_control5", &self.mask_byte_control5())
+            .field("source_address5", &self.source_address5())
+            .field("address_enable5", &self.address_enable5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR5HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits Bits\\[47:32\\] of the sixth 6-byte MAC address."]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/emacaddr5low.rs b/esp32/src/emac_mac/emacaddr5low.rs
index bd52d201f0..28b49861ef 100644
--- a/esp32/src/emac_mac/emacaddr5low.rs
+++ b/esp32/src/emac_mac/emacaddr5low.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR5LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "This field contains the lower 32 bits of the sixth 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emacaddr5low::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emacaddr5low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EMACADDR5LOW_SPEC;
diff --git a/esp32/src/emac_mac/emacaddr6high.rs b/esp32/src/emac_mac/emacaddr6high.rs
index 4979ae26bc..00a7d35ffe 100644
--- a/esp32/src/emac_mac/emacaddr6high.rs
+++ b/esp32/src/emac_mac/emacaddr6high.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACADDR6HIGH")
-            .field(
-                "mac_address6_hi",
-                &format_args!("{}", self.mac_address6_hi().bits()),
-            )
-            .field(
-                "mask_byte_control6",
-                &format_args!("{}", self.mask_byte_control6().bits()),
-            )
-            .field(
-                "source_address6",
-                &format_args!("{}", self.source_address6().bit()),
-            )
-            .field(
-                "address_enable6",
-                &format_args!("{}", self.address_enable6().bit()),
-            )
+            .field("mac_address6_hi", &self.mac_address6_hi())
+            .field("mask_byte_control6", &self.mask_byte_control6())
+            .field("source_address6", &self.source_address6())
+            .field("address_enable6", &self.address_enable6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR6HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits Bits\\[47:32\\] of the seventh 6-byte MAC Address."]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/emacaddr6low.rs b/esp32/src/emac_mac/emacaddr6low.rs
index 98d8247312..96cd0441ef 100644
--- a/esp32/src/emac_mac/emacaddr6low.rs
+++ b/esp32/src/emac_mac/emacaddr6low.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR6LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "This field contains the lower 32 bits of the seventh 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emacaddr6low::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emacaddr6low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EMACADDR6LOW_SPEC;
diff --git a/esp32/src/emac_mac/emacaddr7high.rs b/esp32/src/emac_mac/emacaddr7high.rs
index dce8b65a76..b78e5472d6 100644
--- a/esp32/src/emac_mac/emacaddr7high.rs
+++ b/esp32/src/emac_mac/emacaddr7high.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACADDR7HIGH")
-            .field(
-                "mac_address7_hi",
-                &format_args!("{}", self.mac_address7_hi().bits()),
-            )
-            .field(
-                "mask_byte_control7",
-                &format_args!("{}", self.mask_byte_control7().bits()),
-            )
-            .field(
-                "source_address7",
-                &format_args!("{}", self.source_address7().bit()),
-            )
-            .field(
-                "address_enable7",
-                &format_args!("{}", self.address_enable7().bit()),
-            )
+            .field("mac_address7_hi", &self.mac_address7_hi())
+            .field("mask_byte_control7", &self.mask_byte_control7())
+            .field("source_address7", &self.source_address7())
+            .field("address_enable7", &self.address_enable7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR7HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This field contains the upper 16 bits Bits\\[47:32\\] of the eighth 6-byte MAC Address."]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/emacaddr7low.rs b/esp32/src/emac_mac/emacaddr7low.rs
index 592d4d91a1..be5154f7a7 100644
--- a/esp32/src/emac_mac/emacaddr7low.rs
+++ b/esp32/src/emac_mac/emacaddr7low.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACADDR7LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "This field contains the lower 32 bits of the eighth 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emacaddr7low::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emacaddr7low::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EMACADDR7LOW_SPEC;
diff --git a/esp32/src/emac_mac/emacconfig.rs b/esp32/src/emac_mac/emacconfig.rs
index 2cfa5ed85c..6cc2be967f 100644
--- a/esp32/src/emac_mac/emacconfig.rs
+++ b/esp32/src/emac_mac/emacconfig.rs
@@ -188,47 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACCONFIG")
-            .field("pltf", &format_args!("{}", self.pltf().bits()))
-            .field("rx", &format_args!("{}", self.rx().bit()))
-            .field("tx", &format_args!("{}", self.tx().bit()))
-            .field(
-                "deferralcheck",
-                &format_args!("{}", self.deferralcheck().bit()),
-            )
-            .field(
-                "backofflimit",
-                &format_args!("{}", self.backofflimit().bits()),
-            )
-            .field("padcrcstrip", &format_args!("{}", self.padcrcstrip().bit()))
-            .field("retry", &format_args!("{}", self.retry().bit()))
-            .field(
-                "rxipcoffload",
-                &format_args!("{}", self.rxipcoffload().bit()),
-            )
-            .field("duplex", &format_args!("{}", self.duplex().bit()))
-            .field("loopback", &format_args!("{}", self.loopback().bit()))
-            .field("rxown", &format_args!("{}", self.rxown().bit()))
-            .field("fespeed", &format_args!("{}", self.fespeed().bit()))
-            .field("mii", &format_args!("{}", self.mii().bit()))
-            .field("disablecrs", &format_args!("{}", self.disablecrs().bit()))
-            .field(
-                "interframegap",
-                &format_args!("{}", self.interframegap().bits()),
-            )
-            .field("jumboframe", &format_args!("{}", self.jumboframe().bit()))
-            .field("jabber", &format_args!("{}", self.jabber().bit()))
-            .field("watchdog", &format_args!("{}", self.watchdog().bit()))
-            .field("ass2kp", &format_args!("{}", self.ass2kp().bit()))
-            .field("sairc", &format_args!("{}", self.sairc().bits()))
+            .field("pltf", &self.pltf())
+            .field("rx", &self.rx())
+            .field("tx", &self.tx())
+            .field("deferralcheck", &self.deferralcheck())
+            .field("backofflimit", &self.backofflimit())
+            .field("padcrcstrip", &self.padcrcstrip())
+            .field("retry", &self.retry())
+            .field("rxipcoffload", &self.rxipcoffload())
+            .field("duplex", &self.duplex())
+            .field("loopback", &self.loopback())
+            .field("rxown", &self.rxown())
+            .field("fespeed", &self.fespeed())
+            .field("mii", &self.mii())
+            .field("disablecrs", &self.disablecrs())
+            .field("interframegap", &self.interframegap())
+            .field("jumboframe", &self.jumboframe())
+            .field("jabber", &self.jabber())
+            .field("watchdog", &self.watchdog())
+            .field("ass2kp", &self.ass2kp())
+            .field("sairc", &self.sairc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACCONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble."]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/emaccstatus.rs b/esp32/src/emac_mac/emaccstatus.rs
index 7338de277b..7ec7c1ab47 100644
--- a/esp32/src/emac_mac/emaccstatus.rs
+++ b/esp32/src/emac_mac/emaccstatus.rs
@@ -27,21 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACCSTATUS")
-            .field("link_mode", &format_args!("{}", self.link_mode().bit()))
-            .field("link_speed", &format_args!("{}", self.link_speed().bits()))
-            .field(
-                "jabber_timeout",
-                &format_args!("{}", self.jabber_timeout().bit()),
-            )
+            .field("link_mode", &self.link_mode())
+            .field("link_speed", &self.link_speed())
+            .field("jabber_timeout", &self.jabber_timeout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACCSTATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Link communication status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emaccstatus::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EMACCSTATUS_SPEC;
 impl crate::RegisterSpec for EMACCSTATUS_SPEC {
diff --git a/esp32/src/emac_mac/emacdebug.rs b/esp32/src/emac_mac/emacdebug.rs
index fc802f24ac..ad5f180c5c 100644
--- a/esp32/src/emac_mac/emacdebug.rs
+++ b/esp32/src/emac_mac/emacdebug.rs
@@ -90,27 +90,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACDEBUG")
-            .field("macrpes", &format_args!("{}", self.macrpes().bit()))
-            .field("macrffcs", &format_args!("{}", self.macrffcs().bits()))
-            .field("mtlrfwcas", &format_args!("{}", self.mtlrfwcas().bit()))
-            .field("mtlrfrcs", &format_args!("{}", self.mtlrfrcs().bits()))
-            .field("mtlrffls", &format_args!("{}", self.mtlrffls().bits()))
-            .field("mactpes", &format_args!("{}", self.mactpes().bit()))
-            .field("mactfcs", &format_args!("{}", self.mactfcs().bits()))
-            .field("mactp", &format_args!("{}", self.mactp().bit()))
-            .field("mtltfrcs", &format_args!("{}", self.mtltfrcs().bits()))
-            .field("mtltfwcs", &format_args!("{}", self.mtltfwcs().bit()))
-            .field("mtltfnes", &format_args!("{}", self.mtltfnes().bit()))
-            .field("mtltsffs", &format_args!("{}", self.mtltsffs().bit()))
+            .field("macrpes", &self.macrpes())
+            .field("macrffcs", &self.macrffcs())
+            .field("mtlrfwcas", &self.mtlrfwcas())
+            .field("mtlrfrcs", &self.mtlrfrcs())
+            .field("mtlrffls", &self.mtlrffls())
+            .field("mactpes", &self.mactpes())
+            .field("mactfcs", &self.mactfcs())
+            .field("mactp", &self.mactp())
+            .field("mtltfrcs", &self.mtltfrcs())
+            .field("mtltfwcs", &self.mtltfwcs())
+            .field("mtltfnes", &self.mtltfnes())
+            .field("mtltsffs", &self.mtltsffs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACDEBUG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status debugging bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emacdebug::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EMACDEBUG_SPEC;
 impl crate::RegisterSpec for EMACDEBUG_SPEC {
diff --git a/esp32/src/emac_mac/emacfc.rs b/esp32/src/emac_mac/emacfc.rs
index 793a0f1d4c..9b53f2a18d 100644
--- a/esp32/src/emac_mac/emacfc.rs
+++ b/esp32/src/emac_mac/emacfc.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACFC")
-            .field("fcbba", &format_args!("{}", self.fcbba().bit()))
-            .field("tfce", &format_args!("{}", self.tfce().bit()))
-            .field("rfce", &format_args!("{}", self.rfce().bit()))
-            .field("upfd", &format_args!("{}", self.upfd().bit()))
-            .field("plt", &format_args!("{}", self.plt().bits()))
-            .field("dzpq", &format_args!("{}", self.dzpq().bit()))
-            .field("pause_time", &format_args!("{}", self.pause_time().bits()))
+            .field("fcbba", &self.fcbba())
+            .field("tfce", &self.tfce())
+            .field("rfce", &self.rfce())
+            .field("upfd", &self.upfd())
+            .field("plt", &self.plt())
+            .field("dzpq", &self.dzpq())
+            .field("pause_time", &self.pause_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACFC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFCE bit is set. In the full-duplex mode this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame the Application must set this bit to 1'b1. During a transfer of the Control Frame this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode when this bit is set (and TFCE is set) then backpressure is asserted by the MAC. During backpressure when the MAC receives a new frame the transmitter starts sending a JAM pattern resulting in a collision. When the MAC is configured for the full-duplex mode the BPA(backpressure activate) is automatically disabled."]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/emacff.rs b/esp32/src/emac_mac/emacff.rs
index e08e15251b..14935d01cd 100644
--- a/esp32/src/emac_mac/emacff.rs
+++ b/esp32/src/emac_mac/emacff.rs
@@ -80,23 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACFF")
-            .field("pmode", &format_args!("{}", self.pmode().bit()))
-            .field("daif", &format_args!("{}", self.daif().bit()))
-            .field("pam", &format_args!("{}", self.pam().bit()))
-            .field("dbf", &format_args!("{}", self.dbf().bit()))
-            .field("pcf", &format_args!("{}", self.pcf().bits()))
-            .field("saif", &format_args!("{}", self.saif().bit()))
-            .field("safe", &format_args!("{}", self.safe().bit()))
-            .field("receive_all", &format_args!("{}", self.receive_all().bit()))
+            .field("pmode", &self.pmode())
+            .field("daif", &self.daif())
+            .field("pam", &self.pam())
+            .field("dbf", &self.dbf())
+            .field("pcf", &self.pcf())
+            .field("saif", &self.saif())
+            .field("safe", &self.safe())
+            .field("receive_all", &self.receive_all())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACFF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When this bit is set the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR(PRI_RATIO) is set."]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/emacgmiiaddr.rs b/esp32/src/emac_mac/emacgmiiaddr.rs
index 041a9ae3bc..d10d972d3d 100644
--- a/esp32/src/emac_mac/emacgmiiaddr.rs
+++ b/esp32/src/emac_mac/emacgmiiaddr.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACGMIIADDR")
-            .field("miibusy", &format_args!("{}", self.miibusy().bit()))
-            .field("miiwrite", &format_args!("{}", self.miiwrite().bit()))
-            .field("miicsrclk", &format_args!("{}", self.miicsrclk().bits()))
-            .field("miireg", &format_args!("{}", self.miireg().bits()))
-            .field("miidev", &format_args!("{}", self.miidev().bits()))
+            .field("miibusy", &self.miibusy())
+            .field("miiwrite", &self.miiwrite())
+            .field("miicsrclk", &self.miicsrclk())
+            .field("miireg", &self.miireg())
+            .field("miidev", &self.miidev())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACGMIIADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit should read logic 0 before writing to PHY Addr Register and PHY data Register.During a PHY register access the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress. PHY data Register is invalid until this bit is cleared by the MAC. Therefore PHY data Register (MII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed there is no change in the functionality of this bit even when the PHY is not Present."]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/emacintmask.rs b/esp32/src/emac_mac/emacintmask.rs
index 377fafbc77..2cad3ebffd 100644
--- a/esp32/src/emac_mac/emacintmask.rs
+++ b/esp32/src/emac_mac/emacintmask.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACINTMASK")
-            .field("pmtintmask", &format_args!("{}", self.pmtintmask().bit()))
-            .field("lpiintmask", &format_args!("{}", self.lpiintmask().bit()))
+            .field("pmtintmask", &self.pmtintmask())
+            .field("lpiintmask", &self.lpiintmask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACINTMASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - When set this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register (Interrupt Status Register)."]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/emacints.rs b/esp32/src/emac_mac/emacints.rs
index 0d96009cd6..95b679e4f2 100644
--- a/esp32/src/emac_mac/emacints.rs
+++ b/esp32/src/emac_mac/emacints.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACINTS")
-            .field("pmtints", &format_args!("{}", self.pmtints().bit()))
-            .field("lpiis", &format_args!("{}", self.lpiis().bit()))
+            .field("pmtints", &self.pmtints())
+            .field("lpiis", &self.lpiis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACINTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emacints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EMACINTS_SPEC;
 impl crate::RegisterSpec for EMACINTS_SPEC {
diff --git a/esp32/src/emac_mac/emaclpi_crs.rs b/esp32/src/emac_mac/emaclpi_crs.rs
index 39f10a7d08..f2692b8c24 100644
--- a/esp32/src/emac_mac/emaclpi_crs.rs
+++ b/esp32/src/emac_mac/emaclpi_crs.rs
@@ -69,24 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACLPI_CRS")
-            .field("tlpien", &format_args!("{}", self.tlpien().bit()))
-            .field("tlpiex", &format_args!("{}", self.tlpiex().bit()))
-            .field("rlpien", &format_args!("{}", self.rlpien().bit()))
-            .field("rlpiex", &format_args!("{}", self.rlpiex().bit()))
-            .field("tlpist", &format_args!("{}", self.tlpist().bit()))
-            .field("rlpist", &format_args!("{}", self.rlpist().bit()))
-            .field("lpien", &format_args!("{}", self.lpien().bit()))
-            .field("pls", &format_args!("{}", self.pls().bit()))
-            .field("lpitxa", &format_args!("{}", self.lpitxa().bit()))
+            .field("tlpien", &self.tlpien())
+            .field("tlpiex", &self.tlpiex())
+            .field("rlpien", &self.rlpien())
+            .field("rlpiex", &self.rlpiex())
+            .field("tlpist", &self.tlpist())
+            .field("rlpist", &self.rlpist())
+            .field("lpien", &self.lpien())
+            .field("pls", &self.pls())
+            .field("lpitxa", &self.lpitxa())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACLPI_CRS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "LPI Control and Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emaclpi_crs::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EMACLPI_CRS_SPEC;
 impl crate::RegisterSpec for EMACLPI_CRS_SPEC {
diff --git a/esp32/src/emac_mac/emaclpitimerscontrol.rs b/esp32/src/emac_mac/emaclpitimerscontrol.rs
index d21feb0539..d05d22cb25 100644
--- a/esp32/src/emac_mac/emaclpitimerscontrol.rs
+++ b/esp32/src/emac_mac/emaclpitimerscontrol.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACLPITIMERSCONTROL")
-            .field(
-                "lpi_tw_timer",
-                &format_args!("{}", self.lpi_tw_timer().bits()),
-            )
-            .field(
-                "lpi_ls_timer",
-                &format_args!("{}", self.lpi_ls_timer().bits()),
-            )
+            .field("lpi_tw_timer", &self.lpi_tw_timer())
+            .field("lpi_ls_timer", &self.lpi_ls_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACLPITIMERSCONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "LPI Timers Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emaclpitimerscontrol::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EMACLPITIMERSCONTROL_SPEC;
 impl crate::RegisterSpec for EMACLPITIMERSCONTROL_SPEC {
diff --git a/esp32/src/emac_mac/emacmiidata.rs b/esp32/src/emac_mac/emacmiidata.rs
index b57e568416..67d9f82c18 100644
--- a/esp32/src/emac_mac/emacmiidata.rs
+++ b/esp32/src/emac_mac/emacmiidata.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACMIIDATA")
-            .field("mii_data", &format_args!("{}", self.mii_data().bits()))
+            .field("mii_data", &self.mii_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACMIIDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation."]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/emacwdogto.rs b/esp32/src/emac_mac/emacwdogto.rs
index d380a5d190..917487d96c 100644
--- a/esp32/src/emac_mac/emacwdogto.rs
+++ b/esp32/src/emac_mac/emacwdogto.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMACWDOGTO")
-            .field("wdogto", &format_args!("{}", self.wdogto().bits()))
-            .field("pwdogen", &format_args!("{}", self.pwdogen().bit()))
+            .field("wdogto", &self.wdogto())
+            .field("pwdogen", &self.pwdogen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMACWDOGTO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - When Bit\\[16\\] (PWE) is set and Bit\\[23\\] (WD) of EMACCONFIG_REG is reset this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field such frame is terminated and declared as an error frame."]
     #[inline(always)]
diff --git a/esp32/src/emac_mac/pmt_csr.rs b/esp32/src/emac_mac/pmt_csr.rs
index 89e82b567a..3fc321afac 100644
--- a/esp32/src/emac_mac/pmt_csr.rs
+++ b/esp32/src/emac_mac/pmt_csr.rs
@@ -62,23 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMT_CSR")
-            .field("pwrdwn", &format_args!("{}", self.pwrdwn().bit()))
-            .field("mgkpkten", &format_args!("{}", self.mgkpkten().bit()))
-            .field("rwkpkten", &format_args!("{}", self.rwkpkten().bit()))
-            .field("mgkprcvd", &format_args!("{}", self.mgkprcvd().bit()))
-            .field("rwkprcvd", &format_args!("{}", self.rwkprcvd().bit()))
-            .field("glblucast", &format_args!("{}", self.glblucast().bit()))
-            .field("rwkptr", &format_args!("{}", self.rwkptr().bits()))
-            .field("rwkfiltrst", &format_args!("{}", self.rwkfiltrst().bit()))
+            .field("pwrdwn", &self.pwrdwn())
+            .field("mgkpkten", &self.mgkpkten())
+            .field("rwkpkten", &self.rwkpkten())
+            .field("mgkprcvd", &self.mgkprcvd())
+            .field("rwkprcvd", &self.rwkprcvd())
+            .field("glblucast", &self.glblucast())
+            .field("rwkptr", &self.rwkptr())
+            .field("rwkfiltrst", &self.rwkfiltrst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMT_CSR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "PMT Control and Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmt_csr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PMT_CSR_SPEC;
 impl crate::RegisterSpec for PMT_CSR_SPEC {
diff --git a/esp32/src/emac_mac/pmt_rwuffr.rs b/esp32/src/emac_mac/pmt_rwuffr.rs
index c680e26008..6a0de1a1c7 100644
--- a/esp32/src/emac_mac/pmt_rwuffr.rs
+++ b/esp32/src/emac_mac/pmt_rwuffr.rs
@@ -6,12 +6,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMT_RWUFFR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The MSB (31st bit) must be zero.Bit j\\[30:0\\] is the byte mask. If Bit 1/2/3/4 (byte number) of the byte mask is set the CRC block processes the Filter 1/2/3/4 Offset + j of the incoming packet(PWKPTR is 0/1/2/3).RWKPTR is 0:Filter 0 Byte Mask .RWKPTR is 1:Filter 1 Byte Mask RWKPTR is 2:Filter 2 Byte Mask RWKPTR is 3:Filter 3 Byte Mask RWKPTR is 4:Bit 3/11/19/27 specifies the address type defining the destination address type of the pattern.When the bit is set the pattern applies to only multicast packets\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmt_rwuffr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PMT_RWUFFR_SPEC;
 impl crate::RegisterSpec for PMT_RWUFFR_SPEC {
diff --git a/esp32/src/flash_encryption/done.rs b/esp32/src/flash_encryption/done.rs
index 4004371782..a546decb91 100644
--- a/esp32/src/flash_encryption/done.rs
+++ b/esp32/src/flash_encryption/done.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DONE")
-            .field("flash_done", &format_args!("{}", self.flash_done().bit()))
+            .field("flash_done", &self.flash_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DONE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`done::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DONE_SPEC;
 impl crate::RegisterSpec for DONE_SPEC {
diff --git a/esp32/src/frc_timer/timer_alarm.rs b/esp32/src/frc_timer/timer_alarm.rs
index 533b907e70..8c42ca4ff0 100644
--- a/esp32/src/frc_timer/timer_alarm.rs
+++ b/esp32/src/frc_timer/timer_alarm.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_ALARM")
-            .field(
-                "timer_alarm",
-                &format_args!("{}", self.timer_alarm().bits()),
-            )
+            .field("timer_alarm", &self.timer_alarm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_ALARM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/frc_timer/timer_count.rs b/esp32/src/frc_timer/timer_count.rs
index 9a82fbb585..7cd06983a9 100644
--- a/esp32/src/frc_timer/timer_count.rs
+++ b/esp32/src/frc_timer/timer_count.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_COUNT")
-            .field(
-                "timer_count",
-                &format_args!("{}", self.timer_count().bits()),
-            )
+            .field("timer_count", &self.timer_count())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_COUNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/frc_timer/timer_ctrl.rs b/esp32/src/frc_timer/timer_ctrl.rs
index a97cbabc6d..3d5ddd9257 100644
--- a/esp32/src/frc_timer/timer_ctrl.rs
+++ b/esp32/src/frc_timer/timer_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_CTRL")
-            .field(
-                "timer_prescaler",
-                &format_args!("{}", self.timer_prescaler().bits()),
-            )
+            .field("timer_prescaler", &self.timer_prescaler())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 1:8"]
     #[inline(always)]
diff --git a/esp32/src/frc_timer/timer_int.rs b/esp32/src/frc_timer/timer_int.rs
index e74ce33dd4..6722832068 100644
--- a/esp32/src/frc_timer/timer_int.rs
+++ b/esp32/src/frc_timer/timer_int.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_INT")
-            .field("clr", &format_args!("{}", self.clr().bit()))
+            .field("clr", &self.clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/frc_timer/timer_load.rs b/esp32/src/frc_timer/timer_load.rs
index 83502a0b75..e38849a92e 100644
--- a/esp32/src/frc_timer/timer_load.rs
+++ b/esp32/src/frc_timer/timer_load.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_LOAD")
-            .field("value", &format_args!("{}", self.value().bits()))
+            .field("value", &self.value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_LOAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/generic.rs b/esp32/src/generic.rs
index a2ae6aa053..45ebed16c4 100644
--- a/esp32/src/generic.rs
+++ b/esp32/src/generic.rs
@@ -48,7 +48,7 @@ pub trait RegisterSpec {
 #[doc = " Raw field type"]
 pub trait FieldSpec: Sized {
     #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
-    type Ux: Copy + PartialEq + From<Self>;
+    type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
 }
 #[doc = " Marker for fields with fixed values"]
 pub trait IsEnum: FieldSpec {}
@@ -237,6 +237,14 @@ impl<REG: Readable + Writable> Reg<REG> {
         );
     }
 }
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
 #[doc(hidden)]
 pub mod raw;
 #[doc = " Register reader."]
@@ -302,6 +310,11 @@ impl<FI: FieldSpec> FieldReader<FI> {
         self.bits
     }
 }
+impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 impl<FI> PartialEq<FI> for FieldReader<FI>
 where
     FI: FieldSpec + Copy,
@@ -338,10 +351,21 @@ impl<FI> BitReader<FI> {
         self.bit()
     }
 }
+impl<FI> core::fmt::Debug for BitReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 #[doc = " Marker for register/field writers which can take any value of specified width"]
 pub struct Safe;
 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
 pub struct Unsafe;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct Range<const MIN: u64, const MAX: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeFrom<const MIN: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeTo<const MAX: u64>;
 #[doc = " Write field Proxy"]
 pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
     raw::FieldWriter<'a, REG, WI, FI, Safety>;
@@ -393,6 +417,58 @@ where
         unsafe { self.bits(value) }
     }
 }
+impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
+    FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN && value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
 impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
diff --git a/esp32/src/gpio/acpu_int.rs b/esp32/src/gpio/acpu_int.rs
index 55b31e6c55..8b6161e55b 100644
--- a/esp32/src/gpio/acpu_int.rs
+++ b/esp32/src/gpio/acpu_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ACPU_INT")
-            .field("appcpu_int", &format_args!("{}", self.appcpu_int().bits()))
+            .field("appcpu_int", &self.appcpu_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ACPU_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acpu_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ACPU_INT_SPEC;
 impl crate::RegisterSpec for ACPU_INT_SPEC {
diff --git a/esp32/src/gpio/acpu_int1.rs b/esp32/src/gpio/acpu_int1.rs
index a4a119f148..a1cafa346c 100644
--- a/esp32/src/gpio/acpu_int1.rs
+++ b/esp32/src/gpio/acpu_int1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ACPU_INT1")
-            .field(
-                "appcpu_int_h",
-                &format_args!("{}", self.appcpu_int_h().bits()),
-            )
+            .field("appcpu_int_h", &self.appcpu_int_h())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ACPU_INT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acpu_int1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ACPU_INT1_SPEC;
 impl crate::RegisterSpec for ACPU_INT1_SPEC {
diff --git a/esp32/src/gpio/acpu_nmi_int.rs b/esp32/src/gpio/acpu_nmi_int.rs
index c40b22d4a4..c1f90b85ce 100644
--- a/esp32/src/gpio/acpu_nmi_int.rs
+++ b/esp32/src/gpio/acpu_nmi_int.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ACPU_NMI_INT")
-            .field(
-                "appcpu_nmi_int",
-                &format_args!("{}", self.appcpu_nmi_int().bits()),
-            )
+            .field("appcpu_nmi_int", &self.appcpu_nmi_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ACPU_NMI_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acpu_nmi_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ACPU_NMI_INT_SPEC;
 impl crate::RegisterSpec for ACPU_NMI_INT_SPEC {
diff --git a/esp32/src/gpio/acpu_nmi_int1.rs b/esp32/src/gpio/acpu_nmi_int1.rs
index 6cfe7c612a..241f892320 100644
--- a/esp32/src/gpio/acpu_nmi_int1.rs
+++ b/esp32/src/gpio/acpu_nmi_int1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ACPU_NMI_INT1")
-            .field(
-                "appcpu_nmi_int_h",
-                &format_args!("{}", self.appcpu_nmi_int_h().bits()),
-            )
+            .field("appcpu_nmi_int_h", &self.appcpu_nmi_int_h())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ACPU_NMI_INT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acpu_nmi_int1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ACPU_NMI_INT1_SPEC;
 impl crate::RegisterSpec for ACPU_NMI_INT1_SPEC {
diff --git a/esp32/src/gpio/bt_select.rs b/esp32/src/gpio/bt_select.rs
index 7716f84955..f0195756a3 100644
--- a/esp32/src/gpio/bt_select.rs
+++ b/esp32/src/gpio/bt_select.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_SELECT")
-            .field("bt_sel", &format_args!("{}", self.bt_sel().bits()))
+            .field("bt_sel", &self.bt_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_SELECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32/src/gpio/cali_conf.rs b/esp32/src/gpio/cali_conf.rs
index 58d26f7edb..a65b370622 100644
--- a/esp32/src/gpio/cali_conf.rs
+++ b/esp32/src/gpio/cali_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("cali_conf")
-            .field(
-                "cali_rtc_max",
-                &format_args!("{}", self.cali_rtc_max().bits()),
-            )
-            .field("cali_start", &format_args!("{}", self.cali_start().bit()))
+            .field("cali_rtc_max", &self.cali_rtc_max())
+            .field("cali_start", &self.cali_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CALI_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
diff --git a/esp32/src/gpio/cali_data.rs b/esp32/src/gpio/cali_data.rs
index 37c05faec5..9f1a0071a3 100644
--- a/esp32/src/gpio/cali_data.rs
+++ b/esp32/src/gpio/cali_data.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("cali_data")
-            .field(
-                "cali_value_sync2",
-                &format_args!("{}", self.cali_value_sync2().bits()),
-            )
-            .field(
-                "cali_rdy_real",
-                &format_args!("{}", self.cali_rdy_real().bit()),
-            )
-            .field(
-                "cali_rdy_sync2",
-                &format_args!("{}", self.cali_rdy_sync2().bit()),
-            )
+            .field("cali_value_sync2", &self.cali_value_sync2())
+            .field("cali_rdy_real", &self.cali_rdy_real())
+            .field("cali_rdy_sync2", &self.cali_rdy_sync2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CALI_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cali_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CALI_DATA_SPEC;
 impl crate::RegisterSpec for CALI_DATA_SPEC {
diff --git a/esp32/src/gpio/cpusdio_int.rs b/esp32/src/gpio/cpusdio_int.rs
index 97ca2babf4..63c5be6237 100644
--- a/esp32/src/gpio/cpusdio_int.rs
+++ b/esp32/src/gpio/cpusdio_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPUSDIO_INT")
-            .field("sdio_int", &format_args!("{}", self.sdio_int().bits()))
+            .field("sdio_int", &self.sdio_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPUSDIO_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpusdio_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPUSDIO_INT_SPEC;
 impl crate::RegisterSpec for CPUSDIO_INT_SPEC {
diff --git a/esp32/src/gpio/cpusdio_int1.rs b/esp32/src/gpio/cpusdio_int1.rs
index 43715f7447..5ad55e222b 100644
--- a/esp32/src/gpio/cpusdio_int1.rs
+++ b/esp32/src/gpio/cpusdio_int1.rs
@@ -60,33 +60,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPUSDIO_INT1")
-            .field("sdio_int_h", &format_args!("{}", self.sdio_int_h().bits()))
-            .field(
-                "pin_pad_driver",
-                &format_args!("{}", self.pin_pad_driver().bit()),
-            )
-            .field(
-                "pin_int_type",
-                &format_args!("{}", self.pin_int_type().bits()),
-            )
-            .field(
-                "pin_wakeup_enable",
-                &format_args!("{}", self.pin_wakeup_enable().bit()),
-            )
-            .field("pin_config", &format_args!("{}", self.pin_config().bits()))
-            .field(
-                "pin_int_ena",
-                &format_args!("{}", self.pin_int_ena().bits()),
-            )
+            .field("sdio_int_h", &self.sdio_int_h())
+            .field("pin_pad_driver", &self.pin_pad_driver())
+            .field("pin_int_type", &self.pin_int_type())
+            .field("pin_wakeup_enable", &self.pin_wakeup_enable())
+            .field("pin_config", &self.pin_config())
+            .field("pin_int_ena", &self.pin_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPUSDIO_INT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
diff --git a/esp32/src/gpio/enable.rs b/esp32/src/gpio/enable.rs
index 36d2771ddd..79877c05d2 100644
--- a/esp32/src/gpio/enable.rs
+++ b/esp32/src/gpio/enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 output enable"]
     #[inline(always)]
diff --git a/esp32/src/gpio/enable1.rs b/esp32/src/gpio/enable1.rs
index 385d372983..7e569df2f6 100644
--- a/esp32/src/gpio/enable1.rs
+++ b/esp32/src/gpio/enable1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE1")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 output enable"]
     #[inline(always)]
diff --git a/esp32/src/gpio/enable1_w1tc.rs b/esp32/src/gpio/enable1_w1tc.rs
index d9f742ac81..f748f161b3 100644
--- a/esp32/src/gpio/enable1_w1tc.rs
+++ b/esp32/src/gpio/enable1_w1tc.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE1_W1TC")
-            .field(
-                "enable1_data_w1tc",
-                &format_args!("{}", self.enable1_data_w1tc().bits()),
-            )
+            .field("enable1_data_w1tc", &self.enable1_data_w1tc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE1_W1TC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 output enable write 1 to clear"]
     #[inline(always)]
diff --git a/esp32/src/gpio/enable1_w1ts.rs b/esp32/src/gpio/enable1_w1ts.rs
index 98f25c1f72..96355e99a0 100644
--- a/esp32/src/gpio/enable1_w1ts.rs
+++ b/esp32/src/gpio/enable1_w1ts.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE1_W1TS")
-            .field(
-                "enable1_data_w1ts",
-                &format_args!("{}", self.enable1_data_w1ts().bits()),
-            )
+            .field("enable1_data_w1ts", &self.enable1_data_w1ts())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE1_W1TS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 output enable write 1 to set"]
     #[inline(always)]
diff --git a/esp32/src/gpio/enable_w1tc.rs b/esp32/src/gpio/enable_w1tc.rs
index 74fe620b7c..2d0b11f5cd 100644
--- a/esp32/src/gpio/enable_w1tc.rs
+++ b/esp32/src/gpio/enable_w1tc.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE_W1TC")
-            .field(
-                "enable_data_w1tc",
-                &format_args!("{}", self.enable_data_w1tc().bits()),
-            )
+            .field("enable_data_w1tc", &self.enable_data_w1tc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE_W1TC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 output enable write 1 to clear"]
     #[inline(always)]
diff --git a/esp32/src/gpio/enable_w1ts.rs b/esp32/src/gpio/enable_w1ts.rs
index d430022a2e..9f786e736f 100644
--- a/esp32/src/gpio/enable_w1ts.rs
+++ b/esp32/src/gpio/enable_w1ts.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE_W1TS")
-            .field(
-                "enable_data_w1ts",
-                &format_args!("{}", self.enable_data_w1ts().bits()),
-            )
+            .field("enable_data_w1ts", &self.enable_data_w1ts())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE_W1TS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 output enable write 1 to set"]
     #[inline(always)]
diff --git a/esp32/src/gpio/func_in_sel_cfg.rs b/esp32/src/gpio/func_in_sel_cfg.rs
index 02be3a7b1f..8fe98cb77e 100644
--- a/esp32/src/gpio/func_in_sel_cfg.rs
+++ b/esp32/src/gpio/func_in_sel_cfg.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_IN_SEL_CFG")
-            .field("in_sel", &format_args!("{}", self.in_sel().bits()))
-            .field("in_inv_sel", &format_args!("{}", self.in_inv_sel().bit()))
-            .field("sel", &format_args!("{}", self.sel().bit()))
+            .field("in_sel", &self.in_sel())
+            .field("in_inv_sel", &self.in_inv_sel())
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - select one of the 256 inputs"]
     #[inline(always)]
diff --git a/esp32/src/gpio/func_out_sel_cfg.rs b/esp32/src/gpio/func_out_sel_cfg.rs
index f106ca9c29..77fba54dcb 100644
--- a/esp32/src/gpio/func_out_sel_cfg.rs
+++ b/esp32/src/gpio/func_out_sel_cfg.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_OUT_SEL_CFG")
-            .field("out_sel", &format_args!("{}", self.out_sel().bits()))
-            .field("inv_sel", &format_args!("{}", self.inv_sel().bit()))
-            .field("oen_sel", &format_args!("{}", self.oen_sel().bit()))
-            .field("oen_inv_sel", &format_args!("{}", self.oen_inv_sel().bit()))
+            .field("out_sel", &self.out_sel())
+            .field("inv_sel", &self.inv_sel())
+            .field("oen_sel", &self.oen_sel())
+            .field("oen_inv_sel", &self.oen_inv_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - select one of the 256 output to 40 GPIO"]
     #[inline(always)]
diff --git a/esp32/src/gpio/in1.rs b/esp32/src/gpio/in1.rs
index a6fe20c036..26e08185de 100644
--- a/esp32/src/gpio/in1.rs
+++ b/esp32/src/gpio/in1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN1")
-            .field("data_next", &format_args!("{}", self.data_next().bits()))
+            .field("data_next", &self.data_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 input value"]
     #[inline(always)]
diff --git a/esp32/src/gpio/in_.rs b/esp32/src/gpio/in_.rs
index 5df2748d6d..e109705c1e 100644
--- a/esp32/src/gpio/in_.rs
+++ b/esp32/src/gpio/in_.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN")
-            .field("data_next", &format_args!("{}", self.data_next().bits()))
+            .field("data_next", &self.data_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 input value"]
     #[inline(always)]
diff --git a/esp32/src/gpio/out.rs b/esp32/src/gpio/out.rs
index 59772cacb9..98890a8acf 100644
--- a/esp32/src/gpio/out.rs
+++ b/esp32/src/gpio/out.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("OUT")
-            .field("data", &format_args!("{}", self.data().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("OUT").field("data", &self.data()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/gpio/out1.rs b/esp32/src/gpio/out1.rs
index 864646e059..9a802e4297 100644
--- a/esp32/src/gpio/out1.rs
+++ b/esp32/src/gpio/out1.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("OUT1")
-            .field("data", &format_args!("{}", self.data().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("OUT1").field("data", &self.data()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/gpio/out1_w1tc.rs b/esp32/src/gpio/out1_w1tc.rs
index 70d42f0f0d..7a815e5fff 100644
--- a/esp32/src/gpio/out1_w1tc.rs
+++ b/esp32/src/gpio/out1_w1tc.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT1_W1TC")
-            .field(
-                "out1_data_w1tc",
-                &format_args!("{}", self.out1_data_w1tc().bits()),
-            )
+            .field("out1_data_w1tc", &self.out1_data_w1tc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT1_W1TC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 output value write 1 to clear"]
     #[inline(always)]
diff --git a/esp32/src/gpio/out1_w1ts.rs b/esp32/src/gpio/out1_w1ts.rs
index a5c4cc53f1..3a62a3f330 100644
--- a/esp32/src/gpio/out1_w1ts.rs
+++ b/esp32/src/gpio/out1_w1ts.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT1_W1TS")
-            .field(
-                "out1_data_w1ts",
-                &format_args!("{}", self.out1_data_w1ts().bits()),
-            )
+            .field("out1_data_w1ts", &self.out1_data_w1ts())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT1_W1TS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 output value write 1 to set"]
     #[inline(always)]
diff --git a/esp32/src/gpio/out_w1tc.rs b/esp32/src/gpio/out_w1tc.rs
index c15ca2ffb4..7acf611d25 100644
--- a/esp32/src/gpio/out_w1tc.rs
+++ b/esp32/src/gpio/out_w1tc.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_W1TC")
-            .field(
-                "out_data_w1tc",
-                &format_args!("{}", self.out_data_w1tc().bits()),
-            )
+            .field("out_data_w1tc", &self.out_data_w1tc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_W1TC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 output value write 1 to clear"]
     #[inline(always)]
diff --git a/esp32/src/gpio/out_w1ts.rs b/esp32/src/gpio/out_w1ts.rs
index 32f676fd04..b4c4b1f580 100644
--- a/esp32/src/gpio/out_w1ts.rs
+++ b/esp32/src/gpio/out_w1ts.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_W1TS")
-            .field(
-                "out_data_w1ts",
-                &format_args!("{}", self.out_data_w1ts().bits()),
-            )
+            .field("out_data_w1ts", &self.out_data_w1ts())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_W1TS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 output value write 1 to set"]
     #[inline(always)]
diff --git a/esp32/src/gpio/pcpu_int.rs b/esp32/src/gpio/pcpu_int.rs
index 6306a5853b..0e160dbc15 100644
--- a/esp32/src/gpio/pcpu_int.rs
+++ b/esp32/src/gpio/pcpu_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_INT")
-            .field("procpu_int", &format_args!("{}", self.procpu_int().bits()))
+            .field("procpu_int", &self.procpu_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_INT_SPEC;
 impl crate::RegisterSpec for PCPU_INT_SPEC {
diff --git a/esp32/src/gpio/pcpu_int1.rs b/esp32/src/gpio/pcpu_int1.rs
index e37f021ed8..6d02cba653 100644
--- a/esp32/src/gpio/pcpu_int1.rs
+++ b/esp32/src/gpio/pcpu_int1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_INT1")
-            .field(
-                "procpu_int_h",
-                &format_args!("{}", self.procpu_int_h().bits()),
-            )
+            .field("procpu_int_h", &self.procpu_int_h())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_INT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_int1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_INT1_SPEC;
 impl crate::RegisterSpec for PCPU_INT1_SPEC {
diff --git a/esp32/src/gpio/pcpu_nmi_int.rs b/esp32/src/gpio/pcpu_nmi_int.rs
index 00b366a8d6..637988be3b 100644
--- a/esp32/src/gpio/pcpu_nmi_int.rs
+++ b/esp32/src/gpio/pcpu_nmi_int.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_NMI_INT")
-            .field(
-                "procpu_nmi_int",
-                &format_args!("{}", self.procpu_nmi_int().bits()),
-            )
+            .field("procpu_nmi_int", &self.procpu_nmi_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_NMI_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_nmi_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_NMI_INT_SPEC;
 impl crate::RegisterSpec for PCPU_NMI_INT_SPEC {
diff --git a/esp32/src/gpio/pcpu_nmi_int1.rs b/esp32/src/gpio/pcpu_nmi_int1.rs
index e4f88629a1..23908aed81 100644
--- a/esp32/src/gpio/pcpu_nmi_int1.rs
+++ b/esp32/src/gpio/pcpu_nmi_int1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_NMI_INT1")
-            .field(
-                "procpu_nmi_int_h",
-                &format_args!("{}", self.procpu_nmi_int_h().bits()),
-            )
+            .field("procpu_nmi_int_h", &self.procpu_nmi_int_h())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_NMI_INT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_nmi_int1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_NMI_INT1_SPEC;
 impl crate::RegisterSpec for PCPU_NMI_INT1_SPEC {
diff --git a/esp32/src/gpio/pin.rs b/esp32/src/gpio/pin.rs
index 2d9895ddd9..ce18b326ce 100644
--- a/esp32/src/gpio/pin.rs
+++ b/esp32/src/gpio/pin.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("config", &format_args!("{}", self.config().bits()))
-            .field("int_ena", &format_args!("{}", self.int_ena().bits()))
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("config", &self.config())
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32/src/gpio/sdio_select.rs b/esp32/src/gpio/sdio_select.rs
index f078a28221..acc5079158 100644
--- a/esp32/src/gpio/sdio_select.rs
+++ b/esp32/src/gpio/sdio_select.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_SELECT")
-            .field("sdio_sel", &format_args!("{}", self.sdio_sel().bits()))
+            .field("sdio_sel", &self.sdio_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_SELECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - SDIO PADS on/off control from outside"]
     #[inline(always)]
diff --git a/esp32/src/gpio/status.rs b/esp32/src/gpio/status.rs
index 34fc2bd522..0bff6767c5 100644
--- a/esp32/src/gpio/status.rs
+++ b/esp32/src/gpio/status.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("STATUS")
-            .field("int", &format_args!("{}", self.int().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("STATUS").field("int", &self.int()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/gpio/status1.rs b/esp32/src/gpio/status1.rs
index 71ca70ea97..fcd66ef4b4 100644
--- a/esp32/src/gpio/status1.rs
+++ b/esp32/src/gpio/status1.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("STATUS1")
-            .field("int", &format_args!("{}", self.int().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("STATUS1").field("int", &self.int()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/gpio/status1_w1tc.rs b/esp32/src/gpio/status1_w1tc.rs
index b8aa411382..1441744f19 100644
--- a/esp32/src/gpio/status1_w1tc.rs
+++ b/esp32/src/gpio/status1_w1tc.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS1_W1TC")
-            .field(
-                "status1_int_w1tc",
-                &format_args!("{}", self.status1_int_w1tc().bits()),
-            )
+            .field("status1_int_w1tc", &self.status1_int_w1tc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS1_W1TC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 interrupt status write 1 to clear"]
     #[inline(always)]
diff --git a/esp32/src/gpio/status1_w1ts.rs b/esp32/src/gpio/status1_w1ts.rs
index f8b0ebb67d..e82d843552 100644
--- a/esp32/src/gpio/status1_w1ts.rs
+++ b/esp32/src/gpio/status1_w1ts.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS1_W1TS")
-            .field(
-                "status1_int_w1ts",
-                &format_args!("{}", self.status1_int_w1ts().bits()),
-            )
+            .field("status1_int_w1ts", &self.status1_int_w1ts())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS1_W1TS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - GPIO32~39 interrupt status write 1 to set"]
     #[inline(always)]
diff --git a/esp32/src/gpio/status_w1tc.rs b/esp32/src/gpio/status_w1tc.rs
index 019657b444..9918173823 100644
--- a/esp32/src/gpio/status_w1tc.rs
+++ b/esp32/src/gpio/status_w1tc.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_W1TC")
-            .field(
-                "status_int_w1tc",
-                &format_args!("{}", self.status_int_w1tc().bits()),
-            )
+            .field("status_int_w1tc", &self.status_int_w1tc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_W1TC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 interrupt status write 1 to clear"]
     #[inline(always)]
diff --git a/esp32/src/gpio/status_w1ts.rs b/esp32/src/gpio/status_w1ts.rs
index 3e72980bd1..3ff8ce0e95 100644
--- a/esp32/src/gpio/status_w1ts.rs
+++ b/esp32/src/gpio/status_w1ts.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_W1TS")
-            .field(
-                "status_int_w1ts",
-                &format_args!("{}", self.status_int_w1ts().bits()),
-            )
+            .field("status_int_w1ts", &self.status_int_w1ts())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_W1TS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 interrupt status write 1 to set"]
     #[inline(always)]
diff --git a/esp32/src/gpio/strap.rs b/esp32/src/gpio/strap.rs
index f9946f26e2..5e958ff13b 100644
--- a/esp32/src/gpio/strap.rs
+++ b/esp32/src/gpio/strap.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STRAP")
-            .field("strapping", &format_args!("{}", self.strapping().bits()))
+            .field("strapping", &self.strapping())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STRAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`strap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STRAP_SPEC;
 impl crate::RegisterSpec for STRAP_SPEC {
diff --git a/esp32/src/gpio_sd/clock_gate.rs b/esp32/src/gpio_sd/clock_gate.rs
index d717034fcf..7108c383c9 100644
--- a/esp32/src/gpio_sd/clock_gate.rs
+++ b/esp32/src/gpio_sd/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31"]
     #[inline(always)]
diff --git a/esp32/src/gpio_sd/sigmadelta.rs b/esp32/src/gpio_sd/sigmadelta.rs
index df63b6af27..9d5f11e002 100644
--- a/esp32/src/gpio_sd/sigmadelta.rs
+++ b/esp32/src/gpio_sd/sigmadelta.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SIGMADELTA")
-            .field("in_", &format_args!("{}", self.in_().bits()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
+            .field("in_", &self.in_())
+            .field("prescale", &self.prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SIGMADELTA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/gpio_sd/sigmadelta_misc.rs b/esp32/src/gpio_sd/sigmadelta_misc.rs
index 3bc7bd5c59..69f7f39807 100644
--- a/esp32/src/gpio_sd/sigmadelta_misc.rs
+++ b/esp32/src/gpio_sd/sigmadelta_misc.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SIGMADELTA_MISC")
-            .field("spi_swap", &format_args!("{}", self.spi_swap().bit()))
+            .field("spi_swap", &self.spi_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SIGMADELTA_MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31"]
     #[inline(always)]
diff --git a/esp32/src/gpio_sd/version.rs b/esp32/src/gpio_sd/version.rs
index 708b8ea863..74d3333e55 100644
--- a/esp32/src/gpio_sd/version.rs
+++ b/esp32/src/gpio_sd/version.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field(
-                "gpio_sd_date",
-                &format_args!("{}", self.gpio_sd_date().bits()),
-            )
+            .field("gpio_sd_date", &self.gpio_sd_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27"]
     #[inline(always)]
diff --git a/esp32/src/hinf/cfg_data0.rs b/esp32/src/hinf/cfg_data0.rs
index 01581c234d..f3243b8973 100644
--- a/esp32/src/hinf/cfg_data0.rs
+++ b/esp32/src/hinf/cfg_data0.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG_DATA0")
-            .field(
-                "user_id_fn1",
-                &format_args!("{}", self.user_id_fn1().bits()),
-            )
-            .field(
-                "device_id_fn1",
-                &format_args!("{}", self.device_id_fn1().bits()),
-            )
+            .field("user_id_fn1", &self.user_id_fn1())
+            .field("device_id_fn1", &self.device_id_fn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32/src/hinf/cfg_data1.rs b/esp32/src/hinf/cfg_data1.rs
index a6a8e573d9..060aa46728 100644
--- a/esp32/src/hinf/cfg_data1.rs
+++ b/esp32/src/hinf/cfg_data1.rs
@@ -138,55 +138,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG_DATA1")
-            .field("sdio_enable", &format_args!("{}", self.sdio_enable().bit()))
-            .field(
-                "sdio_ioready1",
-                &format_args!("{}", self.sdio_ioready1().bit()),
-            )
-            .field(
-                "highspeed_enable",
-                &format_args!("{}", self.highspeed_enable().bit()),
-            )
-            .field(
-                "highspeed_mode",
-                &format_args!("{}", self.highspeed_mode().bit()),
-            )
-            .field(
-                "sdio_cd_enable",
-                &format_args!("{}", self.sdio_cd_enable().bit()),
-            )
-            .field(
-                "sdio_ioready2",
-                &format_args!("{}", self.sdio_ioready2().bit()),
-            )
-            .field(
-                "sdio_int_mask",
-                &format_args!("{}", self.sdio_int_mask().bit()),
-            )
-            .field("ioenable2", &format_args!("{}", self.ioenable2().bit()))
-            .field("cd_disable", &format_args!("{}", self.cd_disable().bit()))
-            .field("func1_eps", &format_args!("{}", self.func1_eps().bit()))
-            .field("emp", &format_args!("{}", self.emp().bit()))
-            .field("ioenable1", &format_args!("{}", self.ioenable1().bit()))
-            .field(
-                "sdio20_conf0",
-                &format_args!("{}", self.sdio20_conf0().bits()),
-            )
-            .field("sdio_ver", &format_args!("{}", self.sdio_ver().bits()))
-            .field("func2_eps", &format_args!("{}", self.func2_eps().bit()))
-            .field(
-                "sdio20_conf1",
-                &format_args!("{}", self.sdio20_conf1().bits()),
-            )
+            .field("sdio_enable", &self.sdio_enable())
+            .field("sdio_ioready1", &self.sdio_ioready1())
+            .field("highspeed_enable", &self.highspeed_enable())
+            .field("highspeed_mode", &self.highspeed_mode())
+            .field("sdio_cd_enable", &self.sdio_cd_enable())
+            .field("sdio_ioready2", &self.sdio_ioready2())
+            .field("sdio_int_mask", &self.sdio_int_mask())
+            .field("ioenable2", &self.ioenable2())
+            .field("cd_disable", &self.cd_disable())
+            .field("func1_eps", &self.func1_eps())
+            .field("emp", &self.emp())
+            .field("ioenable1", &self.ioenable1())
+            .field("sdio20_conf0", &self.sdio20_conf0())
+            .field("sdio_ver", &self.sdio_ver())
+            .field("func2_eps", &self.func2_eps())
+            .field("sdio20_conf1", &self.sdio20_conf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/hinf/cfg_data16.rs b/esp32/src/hinf/cfg_data16.rs
index 4bf4fadf75..ce200bbcd0 100644
--- a/esp32/src/hinf/cfg_data16.rs
+++ b/esp32/src/hinf/cfg_data16.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG_DATA16")
-            .field(
-                "user_id_fn2",
-                &format_args!("{}", self.user_id_fn2().bits()),
-            )
-            .field(
-                "device_id_fn2",
-                &format_args!("{}", self.device_id_fn2().bits()),
-            )
+            .field("user_id_fn2", &self.user_id_fn2())
+            .field("device_id_fn2", &self.device_id_fn2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG_DATA16_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32/src/hinf/cfg_data7.rs b/esp32/src/hinf/cfg_data7.rs
index 7f645e1317..b41e28b572 100644
--- a/esp32/src/hinf/cfg_data7.rs
+++ b/esp32/src/hinf/cfg_data7.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG_DATA7")
-            .field("pin_state", &format_args!("{}", self.pin_state().bits()))
-            .field("chip_state", &format_args!("{}", self.chip_state().bits()))
-            .field("sdio_rst", &format_args!("{}", self.sdio_rst().bit()))
-            .field(
-                "sdio_ioready0",
-                &format_args!("{}", self.sdio_ioready0().bit()),
-            )
+            .field("pin_state", &self.pin_state())
+            .field("chip_state", &self.chip_state())
+            .field("sdio_rst", &self.sdio_rst())
+            .field("sdio_ioready0", &self.sdio_ioready0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/hinf/cis_conf0.rs b/esp32/src/hinf/cis_conf0.rs
index 5fca0135c3..aa9585e7c0 100644
--- a/esp32/src/hinf/cis_conf0.rs
+++ b/esp32/src/hinf/cis_conf0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF0")
-            .field(
-                "cis_conf_w0",
-                &format_args!("{}", self.cis_conf_w0().bits()),
-            )
+            .field("cis_conf_w0", &self.cis_conf_w0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/hinf/cis_conf1.rs b/esp32/src/hinf/cis_conf1.rs
index 48941cce53..bbecdea815 100644
--- a/esp32/src/hinf/cis_conf1.rs
+++ b/esp32/src/hinf/cis_conf1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF1")
-            .field(
-                "cis_conf_w1",
-                &format_args!("{}", self.cis_conf_w1().bits()),
-            )
+            .field("cis_conf_w1", &self.cis_conf_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/hinf/cis_conf2.rs b/esp32/src/hinf/cis_conf2.rs
index 514dc7e1f6..1c872bc319 100644
--- a/esp32/src/hinf/cis_conf2.rs
+++ b/esp32/src/hinf/cis_conf2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF2")
-            .field(
-                "cis_conf_w2",
-                &format_args!("{}", self.cis_conf_w2().bits()),
-            )
+            .field("cis_conf_w2", &self.cis_conf_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/hinf/cis_conf3.rs b/esp32/src/hinf/cis_conf3.rs
index d9ee469342..a809368aba 100644
--- a/esp32/src/hinf/cis_conf3.rs
+++ b/esp32/src/hinf/cis_conf3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF3")
-            .field(
-                "cis_conf_w3",
-                &format_args!("{}", self.cis_conf_w3().bits()),
-            )
+            .field("cis_conf_w3", &self.cis_conf_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/hinf/cis_conf4.rs b/esp32/src/hinf/cis_conf4.rs
index 73c2b2b6ef..198b723a84 100644
--- a/esp32/src/hinf/cis_conf4.rs
+++ b/esp32/src/hinf/cis_conf4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF4")
-            .field(
-                "cis_conf_w4",
-                &format_args!("{}", self.cis_conf_w4().bits()),
-            )
+            .field("cis_conf_w4", &self.cis_conf_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/hinf/cis_conf5.rs b/esp32/src/hinf/cis_conf5.rs
index 3b2145d018..99cc966ee3 100644
--- a/esp32/src/hinf/cis_conf5.rs
+++ b/esp32/src/hinf/cis_conf5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF5")
-            .field(
-                "cis_conf_w5",
-                &format_args!("{}", self.cis_conf_w5().bits()),
-            )
+            .field("cis_conf_w5", &self.cis_conf_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/hinf/cis_conf6.rs b/esp32/src/hinf/cis_conf6.rs
index 8968b9bbb9..1ff5fab49d 100644
--- a/esp32/src/hinf/cis_conf6.rs
+++ b/esp32/src/hinf/cis_conf6.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF6")
-            .field(
-                "cis_conf_w6",
-                &format_args!("{}", self.cis_conf_w6().bits()),
-            )
+            .field("cis_conf_w6", &self.cis_conf_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/hinf/cis_conf7.rs b/esp32/src/hinf/cis_conf7.rs
index 48e4d33082..8ea5c8968a 100644
--- a/esp32/src/hinf/cis_conf7.rs
+++ b/esp32/src/hinf/cis_conf7.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF7")
-            .field(
-                "cis_conf_w7",
-                &format_args!("{}", self.cis_conf_w7().bits()),
-            )
+            .field("cis_conf_w7", &self.cis_conf_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/hinf/date.rs b/esp32/src/hinf/date.rs
index 4fcca0ec0e..bb813697e8 100644
--- a/esp32/src/hinf/date.rs
+++ b/esp32/src/hinf/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("sdio_date", &format_args!("{}", self.sdio_date().bits()))
+            .field("sdio_date", &self.sdio_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/i2c0/comd.rs b/esp32/src/i2c0/comd.rs
index b1a7656456..0e753d2625 100644
--- a/esp32/src/i2c0/comd.rs
+++ b/esp32/src/i2c0/comd.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMD")
-            .field("command", &format_args!("{}", self.command().bits()))
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This is the content of command0. It consists of three part. op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit."]
     #[inline(always)]
diff --git a/esp32/src/i2c0/ctr.rs b/esp32/src/i2c0/ctr.rs
index c003925657..f3892182cd 100644
--- a/esp32/src/i2c0/ctr.rs
+++ b/esp32/src/i2c0/ctr.rs
@@ -80,38 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTR")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field(
-                "sample_scl_level",
-                &format_args!("{}", self.sample_scl_level().bit()),
-            )
-            .field("ms_mode", &format_args!("{}", self.ms_mode().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("sample_scl_level", &self.sample_scl_level())
+            .field("ms_mode", &self.ms_mode())
+            .field("trans_start", &self.trans_start())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: normally ouput sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)"]
     #[inline(always)]
diff --git a/esp32/src/i2c0/data.rs b/esp32/src/i2c0/data.rs
index 0678798c80..d374d70dae 100644
--- a/esp32/src/i2c0/data.rs
+++ b/esp32/src/i2c0/data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field("fifo_rdata", &format_args!("{}", self.fifo_rdata().bits()))
+            .field("fifo_rdata", &self.fifo_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DATA_SPEC;
 impl crate::RegisterSpec for DATA_SPEC {
diff --git a/esp32/src/i2c0/date.rs b/esp32/src/i2c0/date.rs
index 26bd148995..09c9d271d1 100644
--- a/esp32/src/i2c0/date.rs
+++ b/esp32/src/i2c0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/i2c0/fifo_conf.rs b/esp32/src/i2c0/fifo_conf.rs
index 78123419fc..c5e742f207 100644
--- a/esp32/src/i2c0/fifo_conf.rs
+++ b/esp32/src/i2c0/fifo_conf.rs
@@ -80,38 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CONF")
-            .field(
-                "rxfifo_full_thrhd",
-                &format_args!("{}", self.rxfifo_full_thrhd().bits()),
-            )
-            .field(
-                "txfifo_empty_thrhd",
-                &format_args!("{}", self.txfifo_empty_thrhd().bits()),
-            )
-            .field("nonfifo_en", &format_args!("{}", self.nonfifo_en().bit()))
-            .field(
-                "fifo_addr_cfg_en",
-                &format_args!("{}", self.fifo_addr_cfg_en().bit()),
-            )
-            .field("rx_fifo_rst", &format_args!("{}", self.rx_fifo_rst().bit()))
-            .field("tx_fifo_rst", &format_args!("{}", self.tx_fifo_rst().bit()))
-            .field(
-                "nonfifo_rx_thres",
-                &format_args!("{}", self.nonfifo_rx_thres().bits()),
-            )
-            .field(
-                "nonfifo_tx_thres",
-                &format_args!("{}", self.nonfifo_tx_thres().bits()),
-            )
+            .field("rxfifo_full_thrhd", &self.rxfifo_full_thrhd())
+            .field("txfifo_empty_thrhd", &self.txfifo_empty_thrhd())
+            .field("nonfifo_en", &self.nonfifo_en())
+            .field("fifo_addr_cfg_en", &self.fifo_addr_cfg_en())
+            .field("rx_fifo_rst", &self.rx_fifo_rst())
+            .field("tx_fifo_rst", &self.tx_fifo_rst())
+            .field("nonfifo_rx_thres", &self.nonfifo_rx_thres())
+            .field("nonfifo_tx_thres", &self.nonfifo_tx_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/i2c0/fifo_start_addr.rs b/esp32/src/i2c0/fifo_start_addr.rs
index e8a7360754..9ca45c7d39 100644
--- a/esp32/src/i2c0/fifo_start_addr.rs
+++ b/esp32/src/i2c0/fifo_start_addr.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_start_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_start_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_START_ADDR_SPEC;
diff --git a/esp32/src/i2c0/int_ena.rs b/esp32/src/i2c0/int_ena.rs
index 6b766548a0..1e59c40fb0 100644
--- a/esp32/src/i2c0/int_ena.rs
+++ b/esp32/src/i2c0/int_ena.rs
@@ -125,46 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "slave_tran_comp",
-                &format_args!("{}", self.slave_tran_comp().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_tran_comp",
-                &format_args!("{}", self.master_tran_comp().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("ack_err", &format_args!("{}", self.ack_err().bit()))
-            .field("rx_rec_full", &format_args!("{}", self.rx_rec_full().bit()))
-            .field(
-                "tx_send_empty",
-                &format_args!("{}", self.tx_send_empty().bit()),
-            )
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("slave_tran_comp", &self.slave_tran_comp())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_tran_comp", &self.master_tran_comp())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("ack_err", &self.ack_err())
+            .field("rx_rec_full", &self.rx_rec_full())
+            .field("tx_send_empty", &self.tx_send_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for rxfifo_full_int interrupt."]
     #[inline(always)]
diff --git a/esp32/src/i2c0/int_raw.rs b/esp32/src/i2c0/int_raw.rs
index 9778992898..f0f1babf25 100644
--- a/esp32/src/i2c0/int_raw.rs
+++ b/esp32/src/i2c0/int_raw.rs
@@ -97,46 +97,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "slave_tran_comp",
-                &format_args!("{}", self.slave_tran_comp().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_tran_comp",
-                &format_args!("{}", self.master_tran_comp().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("ack_err", &format_args!("{}", self.ack_err().bit()))
-            .field("rx_rec_full", &format_args!("{}", self.rx_rec_full().bit()))
-            .field(
-                "tx_send_empty",
-                &format_args!("{}", self.tx_send_empty().bit()),
-            )
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("slave_tran_comp", &self.slave_tran_comp())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_tran_comp", &self.master_tran_comp())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("ack_err", &self.ack_err())
+            .field("rx_rec_full", &self.rx_rec_full())
+            .field("tx_send_empty", &self.tx_send_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32/src/i2c0/int_st.rs b/esp32/src/i2c0/int_st.rs
index b32cb09be1..2b0bf0842a 100644
--- a/esp32/src/i2c0/int_st.rs
+++ b/esp32/src/i2c0/int_st.rs
@@ -97,46 +97,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "slave_tran_comp",
-                &format_args!("{}", self.slave_tran_comp().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_tran_comp",
-                &format_args!("{}", self.master_tran_comp().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("ack_err", &format_args!("{}", self.ack_err().bit()))
-            .field("rx_rec_full", &format_args!("{}", self.rx_rec_full().bit()))
-            .field(
-                "tx_send_empty",
-                &format_args!("{}", self.tx_send_empty().bit()),
-            )
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("slave_tran_comp", &self.slave_tran_comp())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_tran_comp", &self.master_tran_comp())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("ack_err", &self.ack_err())
+            .field("rx_rec_full", &self.rx_rec_full())
+            .field("tx_send_empty", &self.tx_send_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32/src/i2c0/rxfifo_st.rs b/esp32/src/i2c0/rxfifo_st.rs
index 583c4563d1..0239296884 100644
--- a/esp32/src/i2c0/rxfifo_st.rs
+++ b/esp32/src/i2c0/rxfifo_st.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXFIFO_ST")
-            .field(
-                "rxfifo_start_addr",
-                &format_args!("{}", self.rxfifo_start_addr().bits()),
-            )
-            .field(
-                "rxfifo_end_addr",
-                &format_args!("{}", self.rxfifo_end_addr().bits()),
-            )
-            .field(
-                "txfifo_start_addr",
-                &format_args!("{}", self.txfifo_start_addr().bits()),
-            )
-            .field(
-                "txfifo_end_addr",
-                &format_args!("{}", self.txfifo_end_addr().bits()),
-            )
+            .field("rxfifo_start_addr", &self.rxfifo_start_addr())
+            .field("rxfifo_end_addr", &self.rxfifo_end_addr())
+            .field("txfifo_start_addr", &self.txfifo_start_addr())
+            .field("txfifo_end_addr", &self.txfifo_end_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXFIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifo_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXFIFO_ST_SPEC;
 impl crate::RegisterSpec for RXFIFO_ST_SPEC {
diff --git a/esp32/src/i2c0/scl_filter_cfg.rs b/esp32/src/i2c0/scl_filter_cfg.rs
index ef20466319..5f0802099a 100644
--- a/esp32/src/i2c0/scl_filter_cfg.rs
+++ b/esp32/src/i2c0/scl_filter_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_FILTER_CFG")
-            .field(
-                "scl_filter_thres",
-                &format_args!("{}", self.scl_filter_thres().bits()),
-            )
-            .field(
-                "scl_filter_en",
-                &format_args!("{}", self.scl_filter_en().bit()),
-            )
+            .field("scl_filter_thres", &self.scl_filter_thres())
+            .field("scl_filter_en", &self.scl_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_FILTER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - When input SCL's pulse width is smaller than this register value I2C ignores this pulse."]
     #[inline(always)]
diff --git a/esp32/src/i2c0/scl_high_period.rs b/esp32/src/i2c0/scl_high_period.rs
index 5b8d7cfc37..06267955bd 100644
--- a/esp32/src/i2c0/scl_high_period.rs
+++ b/esp32/src/i2c0/scl_high_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH_PERIOD")
-            .field(
-                "scl_high_period",
-                &format_args!("{}", self.scl_high_period().bits()),
-            )
+            .field("scl_high_period", &self.scl_high_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This register is used to configure the clock num during SCL is low level."]
     #[inline(always)]
diff --git a/esp32/src/i2c0/scl_low_period.rs b/esp32/src/i2c0/scl_low_period.rs
index a8ead53a66..c05d25cd29 100644
--- a/esp32/src/i2c0/scl_low_period.rs
+++ b/esp32/src/i2c0/scl_low_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW_PERIOD")
-            .field(
-                "scl_low_period",
-                &format_args!("{}", self.scl_low_period().bits()),
-            )
+            .field("scl_low_period", &self.scl_low_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This register is used to configure the low level width of SCL clock."]
     #[inline(always)]
diff --git a/esp32/src/i2c0/scl_rstart_setup.rs b/esp32/src/i2c0/scl_rstart_setup.rs
index 114e54fa2b..214b567e2d 100644
--- a/esp32/src/i2c0/scl_rstart_setup.rs
+++ b/esp32/src/i2c0/scl_rstart_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_RSTART_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_RSTART_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark."]
     #[inline(always)]
diff --git a/esp32/src/i2c0/scl_start_hold.rs b/esp32/src/i2c0/scl_start_hold.rs
index e38124d2fe..061537c588 100644
--- a/esp32/src/i2c0/scl_start_hold.rs
+++ b/esp32/src/i2c0/scl_start_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark."]
     #[inline(always)]
diff --git a/esp32/src/i2c0/scl_stop_hold.rs b/esp32/src/i2c0/scl_stop_hold.rs
index d88fed4a28..941b42645f 100644
--- a/esp32/src/i2c0/scl_stop_hold.rs
+++ b/esp32/src/i2c0/scl_stop_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This register is used to configure the clock num after the STOP bit's posedge."]
     #[inline(always)]
diff --git a/esp32/src/i2c0/scl_stop_setup.rs b/esp32/src/i2c0/scl_stop_setup.rs
index 628a55665e..2a2f1b9a38 100644
--- a/esp32/src/i2c0/scl_stop_setup.rs
+++ b/esp32/src/i2c0/scl_stop_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the clock num between the posedge of SCL and the posedge of SDA."]
     #[inline(always)]
diff --git a/esp32/src/i2c0/sda_filter_cfg.rs b/esp32/src/i2c0/sda_filter_cfg.rs
index 0f79884013..c9a782dd3d 100644
--- a/esp32/src/i2c0/sda_filter_cfg.rs
+++ b/esp32/src/i2c0/sda_filter_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_FILTER_CFG")
-            .field(
-                "sda_filter_thres",
-                &format_args!("{}", self.sda_filter_thres().bits()),
-            )
-            .field(
-                "sda_filter_en",
-                &format_args!("{}", self.sda_filter_en().bit()),
-            )
+            .field("sda_filter_thres", &self.sda_filter_thres())
+            .field("sda_filter_en", &self.sda_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_FILTER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - When input SCL's pulse width is smaller than this register value I2C ignores this pulse."]
     #[inline(always)]
diff --git a/esp32/src/i2c0/sda_hold.rs b/esp32/src/i2c0/sda_hold.rs
index 75ee506e2c..5decf839c0 100644
--- a/esp32/src/i2c0/sda_hold.rs
+++ b/esp32/src/i2c0/sda_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the clock num I2C used to hold the data after the negedge of SCL."]
     #[inline(always)]
diff --git a/esp32/src/i2c0/sda_sample.rs b/esp32/src/i2c0/sda_sample.rs
index 13f42f8e19..9789356f2b 100644
--- a/esp32/src/i2c0/sda_sample.rs
+++ b/esp32/src/i2c0/sda_sample.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_SAMPLE")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL"]
     #[inline(always)]
diff --git a/esp32/src/i2c0/slave_addr.rs b/esp32/src/i2c0/slave_addr.rs
index bc08b9b3a2..22fa66d230 100644
--- a/esp32/src/i2c0/slave_addr.rs
+++ b/esp32/src/i2c0/slave_addr.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE_ADDR")
-            .field("slave_addr", &format_args!("{}", self.slave_addr().bits()))
-            .field(
-                "addr_10bit_en",
-                &format_args!("{}", self.addr_10bit_en().bit()),
-            )
+            .field("slave_addr", &self.slave_addr())
+            .field("addr_10bit_en", &self.addr_10bit_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - when configured as i2c slave this register is used to configure slave's address."]
     #[inline(always)]
diff --git a/esp32/src/i2c0/sr.rs b/esp32/src/i2c0/sr.rs
index 49ceda4207..0073cb007e 100644
--- a/esp32/src/i2c0/sr.rs
+++ b/esp32/src/i2c0/sr.rs
@@ -83,35 +83,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR")
-            .field("ack_rec", &format_args!("{}", self.ack_rec().bit()))
-            .field("slave_rw", &format_args!("{}", self.slave_rw().bit()))
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field(
-                "slave_addressed",
-                &format_args!("{}", self.slave_addressed().bit()),
-            )
-            .field("byte_trans", &format_args!("{}", self.byte_trans().bit()))
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field(
-                "scl_main_state_last",
-                &format_args!("{}", self.scl_main_state_last().bits()),
-            )
-            .field(
-                "scl_state_last",
-                &format_args!("{}", self.scl_state_last().bits()),
-            )
+            .field("ack_rec", &self.ack_rec())
+            .field("slave_rw", &self.slave_rw())
+            .field("time_out", &self.time_out())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("slave_addressed", &self.slave_addressed())
+            .field("byte_trans", &self.byte_trans())
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("scl_main_state_last", &self.scl_main_state_last())
+            .field("scl_state_last", &self.scl_state_last())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SR_SPEC;
 impl crate::RegisterSpec for SR_SPEC {
diff --git a/esp32/src/i2c0/to.rs b/esp32/src/i2c0/to.rs
index 36984a4168..20f40d2800 100644
--- a/esp32/src/i2c0/to.rs
+++ b/esp32/src/i2c0/to.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO")
-            .field("time_out", &format_args!("{}", self.time_out().bits()))
+            .field("time_out", &self.time_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register is used to configure the max clock number of receiving a data."]
     #[inline(always)]
diff --git a/esp32/src/i2s0/ahb_test.rs b/esp32/src/i2s0/ahb_test.rs
index 29a0221d0f..091f96998f 100644
--- a/esp32/src/i2s0/ahb_test.rs
+++ b/esp32/src/i2s0/ahb_test.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_TEST")
-            .field(
-                "ahb_testmode",
-                &format_args!("{}", self.ahb_testmode().bits()),
-            )
-            .field(
-                "ahb_testaddr",
-                &format_args!("{}", self.ahb_testaddr().bits()),
-            )
+            .field("ahb_testmode", &self.ahb_testmode())
+            .field("ahb_testaddr", &self.ahb_testaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_TEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/clkm_conf.rs b/esp32/src/i2s0/clkm_conf.rs
index 8439f989b2..41861c5e96 100644
--- a/esp32/src/i2s0/clkm_conf.rs
+++ b/esp32/src/i2s0/clkm_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKM_CONF")
-            .field(
-                "clkm_div_num",
-                &format_args!("{}", self.clkm_div_num().bits()),
-            )
-            .field("clkm_div_b", &format_args!("{}", self.clkm_div_b().bits()))
-            .field("clkm_div_a", &format_args!("{}", self.clkm_div_a().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("clka_ena", &format_args!("{}", self.clka_ena().bit()))
+            .field("clkm_div_num", &self.clkm_div_num())
+            .field("clkm_div_b", &self.clkm_div_b())
+            .field("clkm_div_a", &self.clkm_div_a())
+            .field("clk_en", &self.clk_en())
+            .field("clka_ena", &self.clka_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/conf.rs b/esp32/src/i2s0/conf.rs
index 5231e6d897..ad2602ac07 100644
--- a/esp32/src/i2s0/conf.rs
+++ b/esp32/src/i2s0/conf.rs
@@ -179,73 +179,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("tx_reset", &format_args!("{}", self.tx_reset().bit()))
-            .field("rx_reset", &format_args!("{}", self.rx_reset().bit()))
-            .field(
-                "tx_fifo_reset",
-                &format_args!("{}", self.tx_fifo_reset().bit()),
-            )
-            .field(
-                "rx_fifo_reset",
-                &format_args!("{}", self.rx_fifo_reset().bit()),
-            )
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field(
-                "tx_slave_mod",
-                &format_args!("{}", self.tx_slave_mod().bit()),
-            )
-            .field(
-                "rx_slave_mod",
-                &format_args!("{}", self.rx_slave_mod().bit()),
-            )
-            .field(
-                "tx_right_first",
-                &format_args!("{}", self.tx_right_first().bit()),
-            )
-            .field(
-                "rx_right_first",
-                &format_args!("{}", self.rx_right_first().bit()),
-            )
-            .field(
-                "tx_msb_shift",
-                &format_args!("{}", self.tx_msb_shift().bit()),
-            )
-            .field(
-                "rx_msb_shift",
-                &format_args!("{}", self.rx_msb_shift().bit()),
-            )
-            .field(
-                "tx_short_sync",
-                &format_args!("{}", self.tx_short_sync().bit()),
-            )
-            .field(
-                "rx_short_sync",
-                &format_args!("{}", self.rx_short_sync().bit()),
-            )
-            .field("tx_mono", &format_args!("{}", self.tx_mono().bit()))
-            .field("rx_mono", &format_args!("{}", self.rx_mono().bit()))
-            .field(
-                "tx_msb_right",
-                &format_args!("{}", self.tx_msb_right().bit()),
-            )
-            .field(
-                "rx_msb_right",
-                &format_args!("{}", self.rx_msb_right().bit()),
-            )
-            .field(
-                "sig_loopback",
-                &format_args!("{}", self.sig_loopback().bit()),
-            )
+            .field("tx_reset", &self.tx_reset())
+            .field("rx_reset", &self.rx_reset())
+            .field("tx_fifo_reset", &self.tx_fifo_reset())
+            .field("rx_fifo_reset", &self.rx_fifo_reset())
+            .field("tx_start", &self.tx_start())
+            .field("rx_start", &self.rx_start())
+            .field("tx_slave_mod", &self.tx_slave_mod())
+            .field("rx_slave_mod", &self.rx_slave_mod())
+            .field("tx_right_first", &self.tx_right_first())
+            .field("rx_right_first", &self.rx_right_first())
+            .field("tx_msb_shift", &self.tx_msb_shift())
+            .field("rx_msb_shift", &self.rx_msb_shift())
+            .field("tx_short_sync", &self.tx_short_sync())
+            .field("rx_short_sync", &self.rx_short_sync())
+            .field("tx_mono", &self.tx_mono())
+            .field("rx_mono", &self.rx_mono())
+            .field("tx_msb_right", &self.tx_msb_right())
+            .field("rx_msb_right", &self.rx_msb_right())
+            .field("sig_loopback", &self.sig_loopback())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/conf1.rs b/esp32/src/i2s0/conf1.rs
index 9bdd3e5ce8..92462ca338 100644
--- a/esp32/src/i2s0/conf1.rs
+++ b/esp32/src/i2s0/conf1.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "tx_pcm_conf",
-                &format_args!("{}", self.tx_pcm_conf().bits()),
-            )
-            .field(
-                "tx_pcm_bypass",
-                &format_args!("{}", self.tx_pcm_bypass().bit()),
-            )
-            .field(
-                "rx_pcm_conf",
-                &format_args!("{}", self.rx_pcm_conf().bits()),
-            )
-            .field(
-                "rx_pcm_bypass",
-                &format_args!("{}", self.rx_pcm_bypass().bit()),
-            )
-            .field("tx_stop_en", &format_args!("{}", self.tx_stop_en().bit()))
-            .field(
-                "tx_zeros_rm_en",
-                &format_args!("{}", self.tx_zeros_rm_en().bit()),
-            )
+            .field("tx_pcm_conf", &self.tx_pcm_conf())
+            .field("tx_pcm_bypass", &self.tx_pcm_bypass())
+            .field("rx_pcm_conf", &self.rx_pcm_conf())
+            .field("rx_pcm_bypass", &self.rx_pcm_bypass())
+            .field("tx_stop_en", &self.tx_stop_en())
+            .field("tx_zeros_rm_en", &self.tx_zeros_rm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/conf2.rs b/esp32/src/i2s0/conf2.rs
index 447e3bf238..acf6d46d68 100644
--- a/esp32/src/i2s0/conf2.rs
+++ b/esp32/src/i2s0/conf2.rs
@@ -80,38 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF2")
-            .field("camera_en", &format_args!("{}", self.camera_en().bit()))
-            .field(
-                "lcd_tx_wrx2_en",
-                &format_args!("{}", self.lcd_tx_wrx2_en().bit()),
-            )
-            .field(
-                "lcd_tx_sdx2_en",
-                &format_args!("{}", self.lcd_tx_sdx2_en().bit()),
-            )
-            .field(
-                "data_enable_test_en",
-                &format_args!("{}", self.data_enable_test_en().bit()),
-            )
-            .field("data_enable", &format_args!("{}", self.data_enable().bit()))
-            .field("lcd_en", &format_args!("{}", self.lcd_en().bit()))
-            .field(
-                "ext_adc_start_en",
-                &format_args!("{}", self.ext_adc_start_en().bit()),
-            )
-            .field(
-                "inter_valid_en",
-                &format_args!("{}", self.inter_valid_en().bit()),
-            )
+            .field("camera_en", &self.camera_en())
+            .field("lcd_tx_wrx2_en", &self.lcd_tx_wrx2_en())
+            .field("lcd_tx_sdx2_en", &self.lcd_tx_sdx2_en())
+            .field("data_enable_test_en", &self.data_enable_test_en())
+            .field("data_enable", &self.data_enable())
+            .field("lcd_en", &self.lcd_en())
+            .field("ext_adc_start_en", &self.ext_adc_start_en())
+            .field("inter_valid_en", &self.inter_valid_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/conf_chan.rs b/esp32/src/i2s0/conf_chan.rs
index 429b80c4be..9483532570 100644
--- a/esp32/src/i2s0/conf_chan.rs
+++ b/esp32/src/i2s0/conf_chan.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_CHAN")
-            .field(
-                "tx_chan_mod",
-                &format_args!("{}", self.tx_chan_mod().bits()),
-            )
-            .field(
-                "rx_chan_mod",
-                &format_args!("{}", self.rx_chan_mod().bits()),
-            )
+            .field("tx_chan_mod", &self.tx_chan_mod())
+            .field("rx_chan_mod", &self.rx_chan_mod())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_CHAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/conf_sigle_data.rs b/esp32/src/i2s0/conf_sigle_data.rs
index 65940b62f3..fe8de90ebc 100644
--- a/esp32/src/i2s0/conf_sigle_data.rs
+++ b/esp32/src/i2s0/conf_sigle_data.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_SIGLE_DATA")
-            .field("sigle_data", &format_args!("{}", self.sigle_data().bits()))
+            .field("sigle_data", &self.sigle_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SIGLE_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/cvsd_conf0.rs b/esp32/src/i2s0/cvsd_conf0.rs
index fbf449aaa5..2ed0b55620 100644
--- a/esp32/src/i2s0/cvsd_conf0.rs
+++ b/esp32/src/i2s0/cvsd_conf0.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CVSD_CONF0")
-            .field("cvsd_y_max", &format_args!("{}", self.cvsd_y_max().bits()))
-            .field("cvsd_y_min", &format_args!("{}", self.cvsd_y_min().bits()))
+            .field("cvsd_y_max", &self.cvsd_y_max())
+            .field("cvsd_y_min", &self.cvsd_y_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CVSD_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/cvsd_conf1.rs b/esp32/src/i2s0/cvsd_conf1.rs
index 1d00923d3e..852dbaf9df 100644
--- a/esp32/src/i2s0/cvsd_conf1.rs
+++ b/esp32/src/i2s0/cvsd_conf1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CVSD_CONF1")
-            .field(
-                "cvsd_sigma_max",
-                &format_args!("{}", self.cvsd_sigma_max().bits()),
-            )
-            .field(
-                "cvsd_sigma_min",
-                &format_args!("{}", self.cvsd_sigma_min().bits()),
-            )
+            .field("cvsd_sigma_max", &self.cvsd_sigma_max())
+            .field("cvsd_sigma_min", &self.cvsd_sigma_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CVSD_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/cvsd_conf2.rs b/esp32/src/i2s0/cvsd_conf2.rs
index f2790a6eee..a1bc6ca1c5 100644
--- a/esp32/src/i2s0/cvsd_conf2.rs
+++ b/esp32/src/i2s0/cvsd_conf2.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CVSD_CONF2")
-            .field("cvsd_k", &format_args!("{}", self.cvsd_k().bits()))
-            .field("cvsd_j", &format_args!("{}", self.cvsd_j().bits()))
-            .field("cvsd_beta", &format_args!("{}", self.cvsd_beta().bits()))
-            .field("cvsd_h", &format_args!("{}", self.cvsd_h().bits()))
+            .field("cvsd_k", &self.cvsd_k())
+            .field("cvsd_j", &self.cvsd_j())
+            .field("cvsd_beta", &self.cvsd_beta())
+            .field("cvsd_h", &self.cvsd_h())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CVSD_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/date.rs b/esp32/src/i2s0/date.rs
index f8253dea86..dc8e22ab8c 100644
--- a/esp32/src/i2s0/date.rs
+++ b/esp32/src/i2s0/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("i2sdate", &format_args!("{}", self.i2sdate().bits()))
+            .field("i2sdate", &self.i2sdate())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/esco_conf0.rs b/esp32/src/i2s0/esco_conf0.rs
index f1af330d25..c5971640de 100644
--- a/esp32/src/i2s0/esco_conf0.rs
+++ b/esp32/src/i2s0/esco_conf0.rs
@@ -89,42 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ESCO_CONF0")
-            .field("esco_en", &format_args!("{}", self.esco_en().bit()))
-            .field(
-                "esco_chan_mod",
-                &format_args!("{}", self.esco_chan_mod().bit()),
-            )
-            .field(
-                "esco_cvsd_dec_pack_err",
-                &format_args!("{}", self.esco_cvsd_dec_pack_err().bit()),
-            )
-            .field(
-                "esco_cvsd_pack_len_8k",
-                &format_args!("{}", self.esco_cvsd_pack_len_8k().bits()),
-            )
-            .field(
-                "esco_cvsd_inf_en",
-                &format_args!("{}", self.esco_cvsd_inf_en().bit()),
-            )
-            .field(
-                "cvsd_dec_start",
-                &format_args!("{}", self.cvsd_dec_start().bit()),
-            )
-            .field(
-                "cvsd_dec_reset",
-                &format_args!("{}", self.cvsd_dec_reset().bit()),
-            )
-            .field("plc_en", &format_args!("{}", self.plc_en().bit()))
-            .field("plc2dma_en", &format_args!("{}", self.plc2dma_en().bit()))
+            .field("esco_en", &self.esco_en())
+            .field("esco_chan_mod", &self.esco_chan_mod())
+            .field("esco_cvsd_dec_pack_err", &self.esco_cvsd_dec_pack_err())
+            .field("esco_cvsd_pack_len_8k", &self.esco_cvsd_pack_len_8k())
+            .field("esco_cvsd_inf_en", &self.esco_cvsd_inf_en())
+            .field("cvsd_dec_start", &self.cvsd_dec_start())
+            .field("cvsd_dec_reset", &self.cvsd_dec_reset())
+            .field("plc_en", &self.plc_en())
+            .field("plc2dma_en", &self.plc2dma_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ESCO_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/fifo_conf.rs b/esp32/src/i2s0/fifo_conf.rs
index 4de0b4d209..bbaa36c646 100644
--- a/esp32/src/i2s0/fifo_conf.rs
+++ b/esp32/src/i2s0/fifo_conf.rs
@@ -71,40 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CONF")
-            .field(
-                "rx_data_num",
-                &format_args!("{}", self.rx_data_num().bits()),
-            )
-            .field(
-                "tx_data_num",
-                &format_args!("{}", self.tx_data_num().bits()),
-            )
-            .field("dscr_en", &format_args!("{}", self.dscr_en().bit()))
-            .field(
-                "tx_fifo_mod",
-                &format_args!("{}", self.tx_fifo_mod().bits()),
-            )
-            .field(
-                "rx_fifo_mod",
-                &format_args!("{}", self.rx_fifo_mod().bits()),
-            )
-            .field(
-                "tx_fifo_mod_force_en",
-                &format_args!("{}", self.tx_fifo_mod_force_en().bit()),
-            )
-            .field(
-                "rx_fifo_mod_force_en",
-                &format_args!("{}", self.rx_fifo_mod_force_en().bit()),
-            )
+            .field("rx_data_num", &self.rx_data_num())
+            .field("tx_data_num", &self.tx_data_num())
+            .field("dscr_en", &self.dscr_en())
+            .field("tx_fifo_mod", &self.tx_fifo_mod())
+            .field("rx_fifo_mod", &self.rx_fifo_mod())
+            .field("tx_fifo_mod_force_en", &self.tx_fifo_mod_force_en())
+            .field("rx_fifo_mod_force_en", &self.rx_fifo_mod_force_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/in_eof_des_addr.rs b/esp32/src/i2s0/in_eof_des_addr.rs
index 9e38030301..3a9ec0e430 100644
--- a/esp32/src/i2s0/in_eof_des_addr.rs
+++ b/esp32/src/i2s0/in_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EOF_DES_ADDR")
-            .field(
-                "in_suc_eof_des_addr",
-                &format_args!("{}", self.in_suc_eof_des_addr().bits()),
-            )
+            .field("in_suc_eof_des_addr", &self.in_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_EOF_DES_ADDR_SPEC {
diff --git a/esp32/src/i2s0/in_link.rs b/esp32/src/i2s0/in_link.rs
index 8668229478..56c6b41537 100644
--- a/esp32/src/i2s0/in_link.rs
+++ b/esp32/src/i2s0/in_link.rs
@@ -51,29 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_LINK")
-            .field(
-                "inlink_addr",
-                &format_args!("{}", self.inlink_addr().bits()),
-            )
-            .field("inlink_stop", &format_args!("{}", self.inlink_stop().bit()))
-            .field(
-                "inlink_start",
-                &format_args!("{}", self.inlink_start().bit()),
-            )
-            .field(
-                "inlink_restart",
-                &format_args!("{}", self.inlink_restart().bit()),
-            )
-            .field("inlink_park", &format_args!("{}", self.inlink_park().bit()))
+            .field("inlink_addr", &self.inlink_addr())
+            .field("inlink_stop", &self.inlink_stop())
+            .field("inlink_start", &self.inlink_start())
+            .field("inlink_restart", &self.inlink_restart())
+            .field("inlink_park", &self.inlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/infifo_pop.rs b/esp32/src/i2s0/infifo_pop.rs
index f9b36bb596..e279dfc8f4 100644
--- a/esp32/src/i2s0/infifo_pop.rs
+++ b/esp32/src/i2s0/infifo_pop.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INFIFO_POP")
-            .field(
-                "infifo_rdata",
-                &format_args!("{}", self.infifo_rdata().bits()),
-            )
-            .field("infifo_pop", &format_args!("{}", self.infifo_pop().bit()))
+            .field("infifo_rdata", &self.infifo_rdata())
+            .field("infifo_pop", &self.infifo_pop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INFIFO_POP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/inlink_dscr.rs b/esp32/src/i2s0/inlink_dscr.rs
index 0600b0a39f..71ba61d903 100644
--- a/esp32/src/i2s0/inlink_dscr.rs
+++ b/esp32/src/i2s0/inlink_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INLINK_DSCR")
-            .field(
-                "inlink_dscr",
-                &format_args!("{}", self.inlink_dscr().bits()),
-            )
+            .field("inlink_dscr", &self.inlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INLINK_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inlink_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INLINK_DSCR_SPEC;
 impl crate::RegisterSpec for INLINK_DSCR_SPEC {
diff --git a/esp32/src/i2s0/inlink_dscr_bf0.rs b/esp32/src/i2s0/inlink_dscr_bf0.rs
index 308af4e24a..1bcdbf8e2d 100644
--- a/esp32/src/i2s0/inlink_dscr_bf0.rs
+++ b/esp32/src/i2s0/inlink_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INLINK_DSCR_BF0")
-            .field(
-                "inlink_dscr_bf0",
-                &format_args!("{}", self.inlink_dscr_bf0().bits()),
-            )
+            .field("inlink_dscr_bf0", &self.inlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INLINK_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inlink_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INLINK_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for INLINK_DSCR_BF0_SPEC {
diff --git a/esp32/src/i2s0/inlink_dscr_bf1.rs b/esp32/src/i2s0/inlink_dscr_bf1.rs
index bad227b092..548f088d77 100644
--- a/esp32/src/i2s0/inlink_dscr_bf1.rs
+++ b/esp32/src/i2s0/inlink_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INLINK_DSCR_BF1")
-            .field(
-                "inlink_dscr_bf1",
-                &format_args!("{}", self.inlink_dscr_bf1().bits()),
-            )
+            .field("inlink_dscr_bf1", &self.inlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INLINK_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inlink_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INLINK_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for INLINK_DSCR_BF1_SPEC {
diff --git a/esp32/src/i2s0/int_ena.rs b/esp32/src/i2s0/int_ena.rs
index b27e555620..5bf708f11f 100644
--- a/esp32/src/i2s0/int_ena.rs
+++ b/esp32/src/i2s0/int_ena.rs
@@ -161,44 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "rx_take_data",
-                &format_args!("{}", self.rx_take_data().bit()),
-            )
-            .field("tx_put_data", &format_args!("{}", self.tx_put_data().bit()))
-            .field("rx_wfull", &format_args!("{}", self.rx_wfull().bit()))
-            .field("rx_rempty", &format_args!("{}", self.rx_rempty().bit()))
-            .field("tx_wfull", &format_args!("{}", self.tx_wfull().bit()))
-            .field("tx_rempty", &format_args!("{}", self.tx_rempty().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
+            .field("rx_take_data", &self.rx_take_data())
+            .field("tx_put_data", &self.tx_put_data())
+            .field("rx_wfull", &self.rx_wfull())
+            .field("rx_rempty", &self.rx_rempty())
+            .field("tx_wfull", &self.tx_wfull())
+            .field("tx_rempty", &self.tx_rempty())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("out_total_eof", &self.out_total_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/int_raw.rs b/esp32/src/i2s0/int_raw.rs
index 63101520a6..09a04163bd 100644
--- a/esp32/src/i2s0/int_raw.rs
+++ b/esp32/src/i2s0/int_raw.rs
@@ -125,44 +125,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "rx_take_data",
-                &format_args!("{}", self.rx_take_data().bit()),
-            )
-            .field("tx_put_data", &format_args!("{}", self.tx_put_data().bit()))
-            .field("rx_wfull", &format_args!("{}", self.rx_wfull().bit()))
-            .field("rx_rempty", &format_args!("{}", self.rx_rempty().bit()))
-            .field("tx_wfull", &format_args!("{}", self.tx_wfull().bit()))
-            .field("tx_rempty", &format_args!("{}", self.tx_rempty().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
+            .field("rx_take_data", &self.rx_take_data())
+            .field("tx_put_data", &self.tx_put_data())
+            .field("rx_wfull", &self.rx_wfull())
+            .field("rx_rempty", &self.rx_rempty())
+            .field("tx_wfull", &self.tx_wfull())
+            .field("tx_rempty", &self.tx_rempty())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("out_total_eof", &self.out_total_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32/src/i2s0/int_st.rs b/esp32/src/i2s0/int_st.rs
index db98b9af4f..77a3cd726c 100644
--- a/esp32/src/i2s0/int_st.rs
+++ b/esp32/src/i2s0/int_st.rs
@@ -125,44 +125,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "rx_take_data",
-                &format_args!("{}", self.rx_take_data().bit()),
-            )
-            .field("tx_put_data", &format_args!("{}", self.tx_put_data().bit()))
-            .field("rx_wfull", &format_args!("{}", self.rx_wfull().bit()))
-            .field("rx_rempty", &format_args!("{}", self.rx_rempty().bit()))
-            .field("tx_wfull", &format_args!("{}", self.tx_wfull().bit()))
-            .field("tx_rempty", &format_args!("{}", self.tx_rempty().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
+            .field("rx_take_data", &self.rx_take_data())
+            .field("tx_put_data", &self.tx_put_data())
+            .field("rx_wfull", &self.rx_wfull())
+            .field("rx_rempty", &self.rx_rempty())
+            .field("tx_wfull", &self.tx_wfull())
+            .field("tx_rempty", &self.tx_rempty())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("out_total_eof", &self.out_total_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32/src/i2s0/lc_conf.rs b/esp32/src/i2s0/lc_conf.rs
index 8d3e7fabd3..9dd91b735b 100644
--- a/esp32/src/i2s0/lc_conf.rs
+++ b/esp32/src/i2s0/lc_conf.rs
@@ -134,59 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_CONF")
-            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
-            .field("out_rst", &format_args!("{}", self.out_rst().bit()))
-            .field(
-                "ahbm_fifo_rst",
-                &format_args!("{}", self.ahbm_fifo_rst().bit()),
-            )
-            .field("ahbm_rst", &format_args!("{}", self.ahbm_rst().bit()))
-            .field(
-                "out_loop_test",
-                &format_args!("{}", self.out_loop_test().bit()),
-            )
-            .field(
-                "in_loop_test",
-                &format_args!("{}", self.in_loop_test().bit()),
-            )
-            .field(
-                "out_auto_wrback",
-                &format_args!("{}", self.out_auto_wrback().bit()),
-            )
-            .field(
-                "out_no_restart_clr",
-                &format_args!("{}", self.out_no_restart_clr().bit()),
-            )
-            .field(
-                "out_eof_mode",
-                &format_args!("{}", self.out_eof_mode().bit()),
-            )
-            .field(
-                "outdscr_burst_en",
-                &format_args!("{}", self.outdscr_burst_en().bit()),
-            )
-            .field(
-                "indscr_burst_en",
-                &format_args!("{}", self.indscr_burst_en().bit()),
-            )
-            .field(
-                "out_data_burst_en",
-                &format_args!("{}", self.out_data_burst_en().bit()),
-            )
-            .field("check_owner", &format_args!("{}", self.check_owner().bit()))
-            .field(
-                "mem_trans_en",
-                &format_args!("{}", self.mem_trans_en().bit()),
-            )
+            .field("in_rst", &self.in_rst())
+            .field("out_rst", &self.out_rst())
+            .field("ahbm_fifo_rst", &self.ahbm_fifo_rst())
+            .field("ahbm_rst", &self.ahbm_rst())
+            .field("out_loop_test", &self.out_loop_test())
+            .field("in_loop_test", &self.in_loop_test())
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("out_no_restart_clr", &self.out_no_restart_clr())
+            .field("out_eof_mode", &self.out_eof_mode())
+            .field("outdscr_burst_en", &self.outdscr_burst_en())
+            .field("indscr_burst_en", &self.indscr_burst_en())
+            .field("out_data_burst_en", &self.out_data_burst_en())
+            .field("check_owner", &self.check_owner())
+            .field("mem_trans_en", &self.mem_trans_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/lc_hung_conf.rs b/esp32/src/i2s0/lc_hung_conf.rs
index 0868f74b6d..f3424e586a 100644
--- a/esp32/src/i2s0/lc_hung_conf.rs
+++ b/esp32/src/i2s0/lc_hung_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_HUNG_CONF")
-            .field(
-                "lc_fifo_timeout",
-                &format_args!("{}", self.lc_fifo_timeout().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_shift",
-                &format_args!("{}", self.lc_fifo_timeout_shift().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_ena",
-                &format_args!("{}", self.lc_fifo_timeout_ena().bit()),
-            )
+            .field("lc_fifo_timeout", &self.lc_fifo_timeout())
+            .field("lc_fifo_timeout_shift", &self.lc_fifo_timeout_shift())
+            .field("lc_fifo_timeout_ena", &self.lc_fifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/lc_state0.rs b/esp32/src/i2s0/lc_state0.rs
index e4a3ed7294..f4dd68f9b7 100644
--- a/esp32/src/i2s0/lc_state0.rs
+++ b/esp32/src/i2s0/lc_state0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_STATE0")
-            .field("lc_state0", &format_args!("{}", self.lc_state0().bits()))
+            .field("lc_state0", &self.lc_state0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_state0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LC_STATE0_SPEC;
 impl crate::RegisterSpec for LC_STATE0_SPEC {
diff --git a/esp32/src/i2s0/lc_state1.rs b/esp32/src/i2s0/lc_state1.rs
index 4d2549b9b7..b42eaed8c4 100644
--- a/esp32/src/i2s0/lc_state1.rs
+++ b/esp32/src/i2s0/lc_state1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_STATE1")
-            .field("lc_state1", &format_args!("{}", self.lc_state1().bits()))
+            .field("lc_state1", &self.lc_state1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_STATE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_state1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LC_STATE1_SPEC;
 impl crate::RegisterSpec for LC_STATE1_SPEC {
diff --git a/esp32/src/i2s0/out_eof_bfr_des_addr.rs b/esp32/src/i2s0/out_eof_bfr_des_addr.rs
index a096f84036..b256b8d05e 100644
--- a/esp32/src/i2s0/out_eof_bfr_des_addr.rs
+++ b/esp32/src/i2s0/out_eof_bfr_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_BFR_DES_ADDR")
-            .field(
-                "out_eof_bfr_des_addr",
-                &format_args!("{}", self.out_eof_bfr_des_addr().bits()),
-            )
+            .field("out_eof_bfr_des_addr", &self.out_eof_bfr_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_BFR_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_bfr_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_BFR_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_SPEC {
diff --git a/esp32/src/i2s0/out_eof_des_addr.rs b/esp32/src/i2s0/out_eof_des_addr.rs
index ed3b1390bf..955ae89852 100644
--- a/esp32/src/i2s0/out_eof_des_addr.rs
+++ b/esp32/src/i2s0/out_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_DES_ADDR")
-            .field(
-                "out_eof_des_addr",
-                &format_args!("{}", self.out_eof_des_addr().bits()),
-            )
+            .field("out_eof_des_addr", &self.out_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_DES_ADDR_SPEC {
diff --git a/esp32/src/i2s0/out_link.rs b/esp32/src/i2s0/out_link.rs
index a26138a975..6662d61077 100644
--- a/esp32/src/i2s0/out_link.rs
+++ b/esp32/src/i2s0/out_link.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_LINK")
-            .field(
-                "outlink_addr",
-                &format_args!("{}", self.outlink_addr().bits()),
-            )
-            .field(
-                "outlink_stop",
-                &format_args!("{}", self.outlink_stop().bit()),
-            )
-            .field(
-                "outlink_start",
-                &format_args!("{}", self.outlink_start().bit()),
-            )
-            .field(
-                "outlink_restart",
-                &format_args!("{}", self.outlink_restart().bit()),
-            )
-            .field(
-                "outlink_park",
-                &format_args!("{}", self.outlink_park().bit()),
-            )
+            .field("outlink_addr", &self.outlink_addr())
+            .field("outlink_stop", &self.outlink_stop())
+            .field("outlink_start", &self.outlink_start())
+            .field("outlink_restart", &self.outlink_restart())
+            .field("outlink_park", &self.outlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/outfifo_push.rs b/esp32/src/i2s0/outfifo_push.rs
index 89d19d813e..d7d03f6cad 100644
--- a/esp32/src/i2s0/outfifo_push.rs
+++ b/esp32/src/i2s0/outfifo_push.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTFIFO_PUSH")
-            .field(
-                "outfifo_wdata",
-                &format_args!("{}", self.outfifo_wdata().bits()),
-            )
-            .field(
-                "outfifo_push",
-                &format_args!("{}", self.outfifo_push().bit()),
-            )
+            .field("outfifo_wdata", &self.outfifo_wdata())
+            .field("outfifo_push", &self.outfifo_push())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTFIFO_PUSH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/outlink_dscr.rs b/esp32/src/i2s0/outlink_dscr.rs
index cd2b504cb8..7798f97bff 100644
--- a/esp32/src/i2s0/outlink_dscr.rs
+++ b/esp32/src/i2s0/outlink_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTLINK_DSCR")
-            .field(
-                "outlink_dscr",
-                &format_args!("{}", self.outlink_dscr().bits()),
-            )
+            .field("outlink_dscr", &self.outlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTLINK_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outlink_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTLINK_DSCR_SPEC;
 impl crate::RegisterSpec for OUTLINK_DSCR_SPEC {
diff --git a/esp32/src/i2s0/outlink_dscr_bf0.rs b/esp32/src/i2s0/outlink_dscr_bf0.rs
index 9cadc7c9f4..69b9366d1e 100644
--- a/esp32/src/i2s0/outlink_dscr_bf0.rs
+++ b/esp32/src/i2s0/outlink_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTLINK_DSCR_BF0")
-            .field(
-                "outlink_dscr_bf0",
-                &format_args!("{}", self.outlink_dscr_bf0().bits()),
-            )
+            .field("outlink_dscr_bf0", &self.outlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTLINK_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outlink_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTLINK_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for OUTLINK_DSCR_BF0_SPEC {
diff --git a/esp32/src/i2s0/outlink_dscr_bf1.rs b/esp32/src/i2s0/outlink_dscr_bf1.rs
index 0fd9856ba0..eca40447a0 100644
--- a/esp32/src/i2s0/outlink_dscr_bf1.rs
+++ b/esp32/src/i2s0/outlink_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTLINK_DSCR_BF1")
-            .field(
-                "outlink_dscr_bf1",
-                &format_args!("{}", self.outlink_dscr_bf1().bits()),
-            )
+            .field("outlink_dscr_bf1", &self.outlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTLINK_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outlink_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTLINK_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for OUTLINK_DSCR_BF1_SPEC {
diff --git a/esp32/src/i2s0/pd_conf.rs b/esp32/src/i2s0/pd_conf.rs
index b1131e44b1..a0e18cc5a5 100644
--- a/esp32/src/i2s0/pd_conf.rs
+++ b/esp32/src/i2s0/pd_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PD_CONF")
-            .field(
-                "fifo_force_pd",
-                &format_args!("{}", self.fifo_force_pd().bit()),
-            )
-            .field(
-                "fifo_force_pu",
-                &format_args!("{}", self.fifo_force_pu().bit()),
-            )
-            .field(
-                "plc_mem_force_pd",
-                &format_args!("{}", self.plc_mem_force_pd().bit()),
-            )
-            .field(
-                "plc_mem_force_pu",
-                &format_args!("{}", self.plc_mem_force_pu().bit()),
-            )
+            .field("fifo_force_pd", &self.fifo_force_pd())
+            .field("fifo_force_pu", &self.fifo_force_pu())
+            .field("plc_mem_force_pd", &self.plc_mem_force_pd())
+            .field("plc_mem_force_pu", &self.plc_mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/pdm_conf.rs b/esp32/src/i2s0/pdm_conf.rs
index 9cd68e61c9..4470cfcafd 100644
--- a/esp32/src/i2s0/pdm_conf.rs
+++ b/esp32/src/i2s0/pdm_conf.rs
@@ -116,57 +116,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PDM_CONF")
-            .field("tx_pdm_en", &format_args!("{}", self.tx_pdm_en().bit()))
-            .field("rx_pdm_en", &format_args!("{}", self.rx_pdm_en().bit()))
-            .field(
-                "pcm2pdm_conv_en",
-                &format_args!("{}", self.pcm2pdm_conv_en().bit()),
-            )
-            .field(
-                "pdm2pcm_conv_en",
-                &format_args!("{}", self.pdm2pcm_conv_en().bit()),
-            )
-            .field(
-                "tx_pdm_sinc_osr2",
-                &format_args!("{}", self.tx_pdm_sinc_osr2().bits()),
-            )
-            .field(
-                "tx_pdm_prescale",
-                &format_args!("{}", self.tx_pdm_prescale().bits()),
-            )
-            .field(
-                "tx_pdm_hp_in_shift",
-                &format_args!("{}", self.tx_pdm_hp_in_shift().bits()),
-            )
-            .field(
-                "tx_pdm_lp_in_shift",
-                &format_args!("{}", self.tx_pdm_lp_in_shift().bits()),
-            )
-            .field(
-                "tx_pdm_sinc_in_shift",
-                &format_args!("{}", self.tx_pdm_sinc_in_shift().bits()),
-            )
+            .field("tx_pdm_en", &self.tx_pdm_en())
+            .field("rx_pdm_en", &self.rx_pdm_en())
+            .field("pcm2pdm_conv_en", &self.pcm2pdm_conv_en())
+            .field("pdm2pcm_conv_en", &self.pdm2pcm_conv_en())
+            .field("tx_pdm_sinc_osr2", &self.tx_pdm_sinc_osr2())
+            .field("tx_pdm_prescale", &self.tx_pdm_prescale())
+            .field("tx_pdm_hp_in_shift", &self.tx_pdm_hp_in_shift())
+            .field("tx_pdm_lp_in_shift", &self.tx_pdm_lp_in_shift())
+            .field("tx_pdm_sinc_in_shift", &self.tx_pdm_sinc_in_shift())
             .field(
                 "tx_pdm_sigmadelta_in_shift",
-                &format_args!("{}", self.tx_pdm_sigmadelta_in_shift().bits()),
-            )
-            .field(
-                "rx_pdm_sinc_dsr_16_en",
-                &format_args!("{}", self.rx_pdm_sinc_dsr_16_en().bit()),
-            )
-            .field(
-                "tx_pdm_hp_bypass",
-                &format_args!("{}", self.tx_pdm_hp_bypass().bit()),
+                &self.tx_pdm_sigmadelta_in_shift(),
             )
+            .field("rx_pdm_sinc_dsr_16_en", &self.rx_pdm_sinc_dsr_16_en())
+            .field("tx_pdm_hp_bypass", &self.tx_pdm_hp_bypass())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PDM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/pdm_freq_conf.rs b/esp32/src/i2s0/pdm_freq_conf.rs
index 4dc7bcb910..f305f7d8da 100644
--- a/esp32/src/i2s0/pdm_freq_conf.rs
+++ b/esp32/src/i2s0/pdm_freq_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PDM_FREQ_CONF")
-            .field("tx_pdm_fs", &format_args!("{}", self.tx_pdm_fs().bits()))
-            .field("tx_pdm_fp", &format_args!("{}", self.tx_pdm_fp().bits()))
+            .field("tx_pdm_fs", &self.tx_pdm_fs())
+            .field("tx_pdm_fp", &self.tx_pdm_fp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PDM_FREQ_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/plc_conf0.rs b/esp32/src/i2s0/plc_conf0.rs
index b722760858..07fc7f84f6 100644
--- a/esp32/src/i2s0/plc_conf0.rs
+++ b/esp32/src/i2s0/plc_conf0.rs
@@ -62,30 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PLC_CONF0")
-            .field(
-                "good_pack_max",
-                &format_args!("{}", self.good_pack_max().bits()),
-            )
-            .field("n_err_seg", &format_args!("{}", self.n_err_seg().bits()))
-            .field("shift_rate", &format_args!("{}", self.shift_rate().bits()))
-            .field(
-                "max_slide_sample",
-                &format_args!("{}", self.max_slide_sample().bits()),
-            )
-            .field(
-                "pack_len_8k",
-                &format_args!("{}", self.pack_len_8k().bits()),
-            )
-            .field("n_min_err", &format_args!("{}", self.n_min_err().bits()))
+            .field("good_pack_max", &self.good_pack_max())
+            .field("n_err_seg", &self.n_err_seg())
+            .field("shift_rate", &self.shift_rate())
+            .field("max_slide_sample", &self.max_slide_sample())
+            .field("pack_len_8k", &self.pack_len_8k())
+            .field("n_min_err", &self.n_min_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PLC_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/plc_conf1.rs b/esp32/src/i2s0/plc_conf1.rs
index 3cbbc6eb63..98aa7b7d71 100644
--- a/esp32/src/i2s0/plc_conf1.rs
+++ b/esp32/src/i2s0/plc_conf1.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PLC_CONF1")
-            .field(
-                "bad_cef_atten_para",
-                &format_args!("{}", self.bad_cef_atten_para().bits()),
-            )
-            .field(
-                "bad_cef_atten_para_shift",
-                &format_args!("{}", self.bad_cef_atten_para_shift().bits()),
-            )
-            .field(
-                "bad_ola_win2_para_shift",
-                &format_args!("{}", self.bad_ola_win2_para_shift().bits()),
-            )
-            .field(
-                "bad_ola_win2_para",
-                &format_args!("{}", self.bad_ola_win2_para().bits()),
-            )
-            .field(
-                "slide_win_len",
-                &format_args!("{}", self.slide_win_len().bits()),
-            )
+            .field("bad_cef_atten_para", &self.bad_cef_atten_para())
+            .field("bad_cef_atten_para_shift", &self.bad_cef_atten_para_shift())
+            .field("bad_ola_win2_para_shift", &self.bad_ola_win2_para_shift())
+            .field("bad_ola_win2_para", &self.bad_ola_win2_para())
+            .field("slide_win_len", &self.slide_win_len())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PLC_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/plc_conf2.rs b/esp32/src/i2s0/plc_conf2.rs
index 18c1a0ded5..1cba2a52e6 100644
--- a/esp32/src/i2s0/plc_conf2.rs
+++ b/esp32/src/i2s0/plc_conf2.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PLC_CONF2")
-            .field(
-                "cvsd_seg_mod",
-                &format_args!("{}", self.cvsd_seg_mod().bits()),
-            )
-            .field("min_period", &format_args!("{}", self.min_period().bits()))
+            .field("cvsd_seg_mod", &self.cvsd_seg_mod())
+            .field("min_period", &self.min_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PLC_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/rxeof_num.rs b/esp32/src/i2s0/rxeof_num.rs
index 21be70761b..7f7d95b0a1 100644
--- a/esp32/src/i2s0/rxeof_num.rs
+++ b/esp32/src/i2s0/rxeof_num.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXEOF_NUM")
-            .field("rx_eof_num", &format_args!("{}", self.rx_eof_num().bits()))
+            .field("rx_eof_num", &self.rx_eof_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXEOF_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/sample_rate_conf.rs b/esp32/src/i2s0/sample_rate_conf.rs
index c5f6c50aa6..0df690266a 100644
--- a/esp32/src/i2s0/sample_rate_conf.rs
+++ b/esp32/src/i2s0/sample_rate_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAMPLE_RATE_CONF")
-            .field(
-                "tx_bck_div_num",
-                &format_args!("{}", self.tx_bck_div_num().bits()),
-            )
-            .field(
-                "rx_bck_div_num",
-                &format_args!("{}", self.rx_bck_div_num().bits()),
-            )
-            .field(
-                "tx_bits_mod",
-                &format_args!("{}", self.tx_bits_mod().bits()),
-            )
-            .field(
-                "rx_bits_mod",
-                &format_args!("{}", self.rx_bits_mod().bits()),
-            )
+            .field("tx_bck_div_num", &self.tx_bck_div_num())
+            .field("rx_bck_div_num", &self.rx_bck_div_num())
+            .field("tx_bits_mod", &self.tx_bits_mod())
+            .field("rx_bits_mod", &self.rx_bits_mod())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAMPLE_RATE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/sco_conf0.rs b/esp32/src/i2s0/sco_conf0.rs
index b7ad4c4f0d..0f02ac2e5a 100644
--- a/esp32/src/i2s0/sco_conf0.rs
+++ b/esp32/src/i2s0/sco_conf0.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCO_CONF0")
-            .field(
-                "sco_with_i2s_en",
-                &format_args!("{}", self.sco_with_i2s_en().bit()),
-            )
-            .field(
-                "sco_no_i2s_en",
-                &format_args!("{}", self.sco_no_i2s_en().bit()),
-            )
-            .field(
-                "cvsd_enc_start",
-                &format_args!("{}", self.cvsd_enc_start().bit()),
-            )
-            .field(
-                "cvsd_enc_reset",
-                &format_args!("{}", self.cvsd_enc_reset().bit()),
-            )
+            .field("sco_with_i2s_en", &self.sco_with_i2s_en())
+            .field("sco_no_i2s_en", &self.sco_no_i2s_en())
+            .field("cvsd_enc_start", &self.cvsd_enc_start())
+            .field("cvsd_enc_reset", &self.cvsd_enc_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCO_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/i2s0/state.rs b/esp32/src/i2s0/state.rs
index fe9dc37924..3cd2141029 100644
--- a/esp32/src/i2s0/state.rs
+++ b/esp32/src/i2s0/state.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("tx_idle", &format_args!("{}", self.tx_idle().bit()))
-            .field(
-                "tx_fifo_reset_back",
-                &format_args!("{}", self.tx_fifo_reset_back().bit()),
-            )
-            .field(
-                "rx_fifo_reset_back",
-                &format_args!("{}", self.rx_fifo_reset_back().bit()),
-            )
+            .field("tx_idle", &self.tx_idle())
+            .field("tx_fifo_reset_back", &self.tx_fifo_reset_back())
+            .field("rx_fifo_reset_back", &self.rx_fifo_reset_back())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32/src/i2s0/timing.rs b/esp32/src/i2s0/timing.rs
index 53c6139828..b09945011a 100644
--- a/esp32/src/i2s0/timing.rs
+++ b/esp32/src/i2s0/timing.rs
@@ -134,65 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMING")
-            .field(
-                "tx_bck_in_delay",
-                &format_args!("{}", self.tx_bck_in_delay().bits()),
-            )
-            .field(
-                "tx_ws_in_delay",
-                &format_args!("{}", self.tx_ws_in_delay().bits()),
-            )
-            .field(
-                "rx_bck_in_delay",
-                &format_args!("{}", self.rx_bck_in_delay().bits()),
-            )
-            .field(
-                "rx_ws_in_delay",
-                &format_args!("{}", self.rx_ws_in_delay().bits()),
-            )
-            .field(
-                "rx_sd_in_delay",
-                &format_args!("{}", self.rx_sd_in_delay().bits()),
-            )
-            .field(
-                "tx_bck_out_delay",
-                &format_args!("{}", self.tx_bck_out_delay().bits()),
-            )
-            .field(
-                "tx_ws_out_delay",
-                &format_args!("{}", self.tx_ws_out_delay().bits()),
-            )
-            .field(
-                "tx_sd_out_delay",
-                &format_args!("{}", self.tx_sd_out_delay().bits()),
-            )
-            .field(
-                "rx_ws_out_delay",
-                &format_args!("{}", self.rx_ws_out_delay().bits()),
-            )
-            .field(
-                "rx_bck_out_delay",
-                &format_args!("{}", self.rx_bck_out_delay().bits()),
-            )
-            .field("tx_dsync_sw", &format_args!("{}", self.tx_dsync_sw().bit()))
-            .field("rx_dsync_sw", &format_args!("{}", self.rx_dsync_sw().bit()))
-            .field(
-                "data_enable_delay",
-                &format_args!("{}", self.data_enable_delay().bits()),
-            )
-            .field(
-                "tx_bck_in_inv",
-                &format_args!("{}", self.tx_bck_in_inv().bit()),
-            )
+            .field("tx_bck_in_delay", &self.tx_bck_in_delay())
+            .field("tx_ws_in_delay", &self.tx_ws_in_delay())
+            .field("rx_bck_in_delay", &self.rx_bck_in_delay())
+            .field("rx_ws_in_delay", &self.rx_ws_in_delay())
+            .field("rx_sd_in_delay", &self.rx_sd_in_delay())
+            .field("tx_bck_out_delay", &self.tx_bck_out_delay())
+            .field("tx_ws_out_delay", &self.tx_ws_out_delay())
+            .field("tx_sd_out_delay", &self.tx_sd_out_delay())
+            .field("rx_ws_out_delay", &self.rx_ws_out_delay())
+            .field("rx_bck_out_delay", &self.rx_bck_out_delay())
+            .field("tx_dsync_sw", &self.tx_dsync_sw())
+            .field("rx_dsync_sw", &self.rx_dsync_sw())
+            .field("data_enable_delay", &self.data_enable_delay())
+            .field("tx_bck_in_inv", &self.tx_bck_in_inv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio0.rs b/esp32/src/io_mux/gpio0.rs
index b2b9af5840..ffbdf12e72 100644
--- a/esp32/src/io_mux/gpio0.rs
+++ b/esp32/src/io_mux/gpio0.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO0")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio1.rs b/esp32/src/io_mux/gpio1.rs
index 7ea37499b5..75a49e6587 100644
--- a/esp32/src/io_mux/gpio1.rs
+++ b/esp32/src/io_mux/gpio1.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO1")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio10.rs b/esp32/src/io_mux/gpio10.rs
index 7f562137d1..fa48a3e793 100644
--- a/esp32/src/io_mux/gpio10.rs
+++ b/esp32/src/io_mux/gpio10.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO10")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio11.rs b/esp32/src/io_mux/gpio11.rs
index 74362ee7c9..7ca3c299b6 100644
--- a/esp32/src/io_mux/gpio11.rs
+++ b/esp32/src/io_mux/gpio11.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO11")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio12.rs b/esp32/src/io_mux/gpio12.rs
index d64448c36b..8cf55a6d73 100644
--- a/esp32/src/io_mux/gpio12.rs
+++ b/esp32/src/io_mux/gpio12.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO12")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio13.rs b/esp32/src/io_mux/gpio13.rs
index c9845275bc..58d855b383 100644
--- a/esp32/src/io_mux/gpio13.rs
+++ b/esp32/src/io_mux/gpio13.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO13")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio14.rs b/esp32/src/io_mux/gpio14.rs
index 63ebce360a..c43d1141a0 100644
--- a/esp32/src/io_mux/gpio14.rs
+++ b/esp32/src/io_mux/gpio14.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO14")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio15.rs b/esp32/src/io_mux/gpio15.rs
index dd4a9f77ba..5a3d2f5428 100644
--- a/esp32/src/io_mux/gpio15.rs
+++ b/esp32/src/io_mux/gpio15.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO15")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio16.rs b/esp32/src/io_mux/gpio16.rs
index 06c81855db..4bf4dfb0ca 100644
--- a/esp32/src/io_mux/gpio16.rs
+++ b/esp32/src/io_mux/gpio16.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO16")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO16_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio17.rs b/esp32/src/io_mux/gpio17.rs
index e196ca4dbe..9f4ee43635 100644
--- a/esp32/src/io_mux/gpio17.rs
+++ b/esp32/src/io_mux/gpio17.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO17")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO17_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio18.rs b/esp32/src/io_mux/gpio18.rs
index 739fb9416d..e338f1db47 100644
--- a/esp32/src/io_mux/gpio18.rs
+++ b/esp32/src/io_mux/gpio18.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO18")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO18_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio19.rs b/esp32/src/io_mux/gpio19.rs
index 4a1a004963..0da7d2dbcb 100644
--- a/esp32/src/io_mux/gpio19.rs
+++ b/esp32/src/io_mux/gpio19.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO19")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO19_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio2.rs b/esp32/src/io_mux/gpio2.rs
index 34a7220b07..6bb7ea3a66 100644
--- a/esp32/src/io_mux/gpio2.rs
+++ b/esp32/src/io_mux/gpio2.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO2")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio20.rs b/esp32/src/io_mux/gpio20.rs
index 1a7960c75b..99083c2422 100644
--- a/esp32/src/io_mux/gpio20.rs
+++ b/esp32/src/io_mux/gpio20.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO20")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO20_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio21.rs b/esp32/src/io_mux/gpio21.rs
index 3237883a7c..d088ab9728 100644
--- a/esp32/src/io_mux/gpio21.rs
+++ b/esp32/src/io_mux/gpio21.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO21")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO21_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio22.rs b/esp32/src/io_mux/gpio22.rs
index fc29f07753..4991a02d73 100644
--- a/esp32/src/io_mux/gpio22.rs
+++ b/esp32/src/io_mux/gpio22.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO22")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO22_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio23.rs b/esp32/src/io_mux/gpio23.rs
index 6a84de2030..f56caa7780 100644
--- a/esp32/src/io_mux/gpio23.rs
+++ b/esp32/src/io_mux/gpio23.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO23")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO23_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio24.rs b/esp32/src/io_mux/gpio24.rs
index 1296f0b4b0..d574b96be3 100644
--- a/esp32/src/io_mux/gpio24.rs
+++ b/esp32/src/io_mux/gpio24.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO24")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO24_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio25.rs b/esp32/src/io_mux/gpio25.rs
index 018c26cc9f..4de51d388b 100644
--- a/esp32/src/io_mux/gpio25.rs
+++ b/esp32/src/io_mux/gpio25.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO25")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO25_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio26.rs b/esp32/src/io_mux/gpio26.rs
index 852b8ddb2b..fe9293570b 100644
--- a/esp32/src/io_mux/gpio26.rs
+++ b/esp32/src/io_mux/gpio26.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO26")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO26_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio27.rs b/esp32/src/io_mux/gpio27.rs
index 899d8bc1c6..8c41c5838f 100644
--- a/esp32/src/io_mux/gpio27.rs
+++ b/esp32/src/io_mux/gpio27.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO27")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO27_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio3.rs b/esp32/src/io_mux/gpio3.rs
index cc6d97d4f0..e808385646 100644
--- a/esp32/src/io_mux/gpio3.rs
+++ b/esp32/src/io_mux/gpio3.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO3")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio32.rs b/esp32/src/io_mux/gpio32.rs
index 002be039c5..18b730e2ce 100644
--- a/esp32/src/io_mux/gpio32.rs
+++ b/esp32/src/io_mux/gpio32.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO32")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO32_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio33.rs b/esp32/src/io_mux/gpio33.rs
index 4abdf757bc..e2c7c3a564 100644
--- a/esp32/src/io_mux/gpio33.rs
+++ b/esp32/src/io_mux/gpio33.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO33")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO33_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio34.rs b/esp32/src/io_mux/gpio34.rs
index 3345d2aadc..d2526d35c3 100644
--- a/esp32/src/io_mux/gpio34.rs
+++ b/esp32/src/io_mux/gpio34.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO34")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO34_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio35.rs b/esp32/src/io_mux/gpio35.rs
index a7bd2b2c70..9268454cb3 100644
--- a/esp32/src/io_mux/gpio35.rs
+++ b/esp32/src/io_mux/gpio35.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO35")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO35_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio36.rs b/esp32/src/io_mux/gpio36.rs
index 456905efae..1acbae6c19 100644
--- a/esp32/src/io_mux/gpio36.rs
+++ b/esp32/src/io_mux/gpio36.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO36")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO36_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio37.rs b/esp32/src/io_mux/gpio37.rs
index a29ba39233..9d97891481 100644
--- a/esp32/src/io_mux/gpio37.rs
+++ b/esp32/src/io_mux/gpio37.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO37")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO37_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio38.rs b/esp32/src/io_mux/gpio38.rs
index 9aa9c8578d..e7dea50045 100644
--- a/esp32/src/io_mux/gpio38.rs
+++ b/esp32/src/io_mux/gpio38.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO38")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO38_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio39.rs b/esp32/src/io_mux/gpio39.rs
index e1b6d47ab6..f6c35299ac 100644
--- a/esp32/src/io_mux/gpio39.rs
+++ b/esp32/src/io_mux/gpio39.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO39")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO39_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio4.rs b/esp32/src/io_mux/gpio4.rs
index a40656bb30..2031a43b26 100644
--- a/esp32/src/io_mux/gpio4.rs
+++ b/esp32/src/io_mux/gpio4.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO4")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio5.rs b/esp32/src/io_mux/gpio5.rs
index fd1742e516..74cdbd15d2 100644
--- a/esp32/src/io_mux/gpio5.rs
+++ b/esp32/src/io_mux/gpio5.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO5")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio6.rs b/esp32/src/io_mux/gpio6.rs
index ca8f14d245..23e9ac2621 100644
--- a/esp32/src/io_mux/gpio6.rs
+++ b/esp32/src/io_mux/gpio6.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO6")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio7.rs b/esp32/src/io_mux/gpio7.rs
index ab0c3726f1..5c644efc4c 100644
--- a/esp32/src/io_mux/gpio7.rs
+++ b/esp32/src/io_mux/gpio7.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO7")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio8.rs b/esp32/src/io_mux/gpio8.rs
index 91b05c5b6b..e207bd4a12 100644
--- a/esp32/src/io_mux/gpio8.rs
+++ b/esp32/src/io_mux/gpio8.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO8")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/gpio9.rs b/esp32/src/io_mux/gpio9.rs
index 456009a7e3..da9833a399 100644
--- a/esp32/src/io_mux/gpio9.rs
+++ b/esp32/src/io_mux/gpio9.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO9")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: enable output; 0: disable output."]
     #[inline(always)]
diff --git a/esp32/src/io_mux/pin_ctrl.rs b/esp32/src/io_mux/pin_ctrl.rs
index d545f7d679..179659dbec 100644
--- a/esp32/src/io_mux/pin_ctrl.rs
+++ b/esp32/src/io_mux/pin_ctrl.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN_CTRL")
-            .field("clk1", &format_args!("{}", self.clk1().bits()))
-            .field("clk2", &format_args!("{}", self.clk2().bits()))
-            .field("clk3", &format_args!("{}", self.clk3().bits()))
+            .field("clk1", &self.clk1())
+            .field("clk2", &self.clk2())
+            .field("clk3", &self.clk3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL\\[3:0\\] = 0x0; CLK_OUT2, then set PIN_CTRL\\[3:0\\] = 0x0 and PIN_CTRL\\[7:4\\] = 0x0; CLK_OUT3, then set PIN_CTRL\\[3:0\\] = 0x0 and PIN_CTRL\\[11:8\\] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL\\[3:0\\] = 0xF; CLK_OUT2, then set PIN_CTRL\\[3:0\\] = 0xF and PIN_CTRL\\[7:4\\] = 0x0; CLK_OUT3, then set PIN_CTRL\\[3:0\\] = 0xF and PIN_CTRL\\[11:8\\] = 0x0."]
     #[inline(always)]
diff --git a/esp32/src/ledc/conf.rs b/esp32/src/ledc/conf.rs
index d0b3969ebc..39fbc9bd36 100644
--- a/esp32/src/ledc/conf.rs
+++ b/esp32/src/ledc/conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("apb_clk_sel", &format_args!("{}", self.apb_clk_sel().bit()))
+            .field("apb_clk_sel", &self.apb_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz"]
     #[inline(always)]
diff --git a/esp32/src/ledc/date.rs b/esp32/src/ledc/date.rs
index 738390e220..d7b1426d45 100644
--- a/esp32/src/ledc/date.rs
+++ b/esp32/src/ledc/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/ledc/hsch/conf0.rs b/esp32/src/ledc/hsch/conf0.rs
index e4061a9eae..65f13caf91 100644
--- a/esp32/src/ledc/hsch/conf0.rs
+++ b/esp32/src/ledc/hsch/conf0.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("timer_sel", &format_args!("{}", self.timer_sel().bits()))
-            .field("sig_out_en", &format_args!("{}", self.sig_out_en().bit()))
-            .field("idle_lv", &format_args!("{}", self.idle_lv().bit()))
+            .field("timer_sel", &self.timer_sel())
+            .field("sig_out_en", &self.sig_out_en())
+            .field("idle_lv", &self.idle_lv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - There are four high speed timers the two bits are used to select one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3."]
     #[inline(always)]
diff --git a/esp32/src/ledc/hsch/conf1.rs b/esp32/src/ledc/hsch/conf1.rs
index d8150b79e0..fdaa574306 100644
--- a/esp32/src/ledc/hsch/conf1.rs
+++ b/esp32/src/ledc/hsch/conf1.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field("duty_scale", &format_args!("{}", self.duty_scale().bits()))
-            .field("duty_cycle", &format_args!("{}", self.duty_cycle().bits()))
-            .field("duty_num", &format_args!("{}", self.duty_num().bits()))
-            .field("duty_inc", &format_args!("{}", self.duty_inc().bit()))
-            .field("duty_start", &format_args!("{}", self.duty_start().bit()))
+            .field("duty_scale", &self.duty_scale())
+            .field("duty_cycle", &self.duty_cycle())
+            .field("duty_num", &self.duty_num())
+            .field("duty_inc", &self.duty_inc())
+            .field("duty_start", &self.duty_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register controls the increase or decrease step scale for high speed channel0."]
     #[inline(always)]
diff --git a/esp32/src/ledc/hsch/duty.rs b/esp32/src/ledc/hsch/duty.rs
index 175e9a73ba..e69360e161 100644
--- a/esp32/src/ledc/hsch/duty.rs
+++ b/esp32/src/ledc/hsch/duty.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DUTY")
-            .field("duty", &format_args!("{}", self.duty().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DUTY").field("duty", &self.duty()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/ledc/hsch/duty_r.rs b/esp32/src/ledc/hsch/duty_r.rs
index a616ec20d9..e73df05446 100644
--- a/esp32/src/ledc/hsch/duty_r.rs
+++ b/esp32/src/ledc/hsch/duty_r.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DUTY_R")
-            .field("duty_r", &format_args!("{}", self.duty_r().bits()))
+            .field("duty_r", &self.duty_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_R_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`duty_r::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DUTY_R_SPEC;
 impl crate::RegisterSpec for DUTY_R_SPEC {
diff --git a/esp32/src/ledc/hsch/hpoint.rs b/esp32/src/ledc/hsch/hpoint.rs
index 958e70e66e..e690b0af5d 100644
--- a/esp32/src/ledc/hsch/hpoint.rs
+++ b/esp32/src/ledc/hsch/hpoint.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPOINT")
-            .field("hpoint", &format_args!("{}", self.hpoint().bits()))
+            .field("hpoint", &self.hpoint())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPOINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - The output value changes to high when htimerx(x=\\[0 3\\]) selected by high speed channel0 has reached reg_hpoint_hsch0\\[19:0\\]"]
     #[inline(always)]
diff --git a/esp32/src/ledc/hstimer/conf.rs b/esp32/src/ledc/hstimer/conf.rs
index bbe4be195f..531a573381 100644
--- a/esp32/src/ledc/hstimer/conf.rs
+++ b/esp32/src/ledc/hstimer/conf.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("duty_res", &format_args!("{}", self.duty_res().bits()))
-            .field("div_num", &format_args!("{}", self.div_num().bits()))
-            .field("pause", &format_args!("{}", self.pause().bit()))
-            .field("rst", &format_args!("{}", self.rst().bit()))
-            .field("tick_sel", &format_args!("{}", self.tick_sel().bit()))
+            .field("duty_res", &self.duty_res())
+            .field("div_num", &self.div_num())
+            .field("pause", &self.pause())
+            .field("rst", &self.rst())
+            .field("tick_sel", &self.tick_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register controls the range of the counter in high speed timer0. the counter range is \\[0 2**reg_hstimer0_lim\\] the max bit width for counter is 20."]
     #[inline(always)]
diff --git a/esp32/src/ledc/hstimer/value.rs b/esp32/src/ledc/hstimer/value.rs
index 23074d2bcd..2969a320a0 100644
--- a/esp32/src/ledc/hstimer/value.rs
+++ b/esp32/src/ledc/hstimer/value.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("VALUE")
-            .field("cnt", &format_args!("{}", self.cnt().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("VALUE").field("cnt", &self.cnt()).finish()
     }
 }
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/ledc/int_ena.rs b/esp32/src/ledc/int_ena.rs
index 30103631b7..f7bce48e30 100644
--- a/esp32/src/ledc/int_ena.rs
+++ b/esp32/src/ledc/int_ena.rs
@@ -204,111 +204,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "hstimer0_ovf",
-                &format_args!("{}", self.hstimer0_ovf().bit()),
-            )
-            .field(
-                "hstimer1_ovf",
-                &format_args!("{}", self.hstimer1_ovf().bit()),
-            )
-            .field(
-                "hstimer2_ovf",
-                &format_args!("{}", self.hstimer2_ovf().bit()),
-            )
-            .field(
-                "hstimer3_ovf",
-                &format_args!("{}", self.hstimer3_ovf().bit()),
-            )
-            .field(
-                "lstimer0_ovf",
-                &format_args!("{}", self.lstimer0_ovf().bit()),
-            )
-            .field(
-                "lstimer1_ovf",
-                &format_args!("{}", self.lstimer1_ovf().bit()),
-            )
-            .field(
-                "lstimer2_ovf",
-                &format_args!("{}", self.lstimer2_ovf().bit()),
-            )
-            .field(
-                "lstimer3_ovf",
-                &format_args!("{}", self.lstimer3_ovf().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch0",
-                &format_args!("{}", self.duty_chng_end_hsch0().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch1",
-                &format_args!("{}", self.duty_chng_end_hsch1().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch2",
-                &format_args!("{}", self.duty_chng_end_hsch2().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch3",
-                &format_args!("{}", self.duty_chng_end_hsch3().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch4",
-                &format_args!("{}", self.duty_chng_end_hsch4().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch5",
-                &format_args!("{}", self.duty_chng_end_hsch5().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch6",
-                &format_args!("{}", self.duty_chng_end_hsch6().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch7",
-                &format_args!("{}", self.duty_chng_end_hsch7().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch0",
-                &format_args!("{}", self.duty_chng_end_lsch0().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch1",
-                &format_args!("{}", self.duty_chng_end_lsch1().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch2",
-                &format_args!("{}", self.duty_chng_end_lsch2().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch3",
-                &format_args!("{}", self.duty_chng_end_lsch3().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch4",
-                &format_args!("{}", self.duty_chng_end_lsch4().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch5",
-                &format_args!("{}", self.duty_chng_end_lsch5().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch6",
-                &format_args!("{}", self.duty_chng_end_lsch6().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch7",
-                &format_args!("{}", self.duty_chng_end_lsch7().bit()),
-            )
+            .field("hstimer0_ovf", &self.hstimer0_ovf())
+            .field("hstimer1_ovf", &self.hstimer1_ovf())
+            .field("hstimer2_ovf", &self.hstimer2_ovf())
+            .field("hstimer3_ovf", &self.hstimer3_ovf())
+            .field("lstimer0_ovf", &self.lstimer0_ovf())
+            .field("lstimer1_ovf", &self.lstimer1_ovf())
+            .field("lstimer2_ovf", &self.lstimer2_ovf())
+            .field("lstimer3_ovf", &self.lstimer3_ovf())
+            .field("duty_chng_end_hsch0", &self.duty_chng_end_hsch0())
+            .field("duty_chng_end_hsch1", &self.duty_chng_end_hsch1())
+            .field("duty_chng_end_hsch2", &self.duty_chng_end_hsch2())
+            .field("duty_chng_end_hsch3", &self.duty_chng_end_hsch3())
+            .field("duty_chng_end_hsch4", &self.duty_chng_end_hsch4())
+            .field("duty_chng_end_hsch5", &self.duty_chng_end_hsch5())
+            .field("duty_chng_end_hsch6", &self.duty_chng_end_hsch6())
+            .field("duty_chng_end_hsch7", &self.duty_chng_end_hsch7())
+            .field("duty_chng_end_lsch0", &self.duty_chng_end_lsch0())
+            .field("duty_chng_end_lsch1", &self.duty_chng_end_lsch1())
+            .field("duty_chng_end_lsch2", &self.duty_chng_end_lsch2())
+            .field("duty_chng_end_lsch3", &self.duty_chng_end_lsch3())
+            .field("duty_chng_end_lsch4", &self.duty_chng_end_lsch4())
+            .field("duty_chng_end_lsch5", &self.duty_chng_end_lsch5())
+            .field("duty_chng_end_lsch6", &self.duty_chng_end_lsch6())
+            .field("duty_chng_end_lsch7", &self.duty_chng_end_lsch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for high speed channel(0-3) counter overflow interrupt."]
     #[doc = ""]
diff --git a/esp32/src/ledc/int_raw.rs b/esp32/src/ledc/int_raw.rs
index dc4d8839b2..b7f490fcb7 100644
--- a/esp32/src/ledc/int_raw.rs
+++ b/esp32/src/ledc/int_raw.rs
@@ -204,111 +204,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "hstimer0_ovf",
-                &format_args!("{}", self.hstimer0_ovf().bit()),
-            )
-            .field(
-                "hstimer1_ovf",
-                &format_args!("{}", self.hstimer1_ovf().bit()),
-            )
-            .field(
-                "hstimer2_ovf",
-                &format_args!("{}", self.hstimer2_ovf().bit()),
-            )
-            .field(
-                "hstimer3_ovf",
-                &format_args!("{}", self.hstimer3_ovf().bit()),
-            )
-            .field(
-                "lstimer0_ovf",
-                &format_args!("{}", self.lstimer0_ovf().bit()),
-            )
-            .field(
-                "lstimer1_ovf",
-                &format_args!("{}", self.lstimer1_ovf().bit()),
-            )
-            .field(
-                "lstimer2_ovf",
-                &format_args!("{}", self.lstimer2_ovf().bit()),
-            )
-            .field(
-                "lstimer3_ovf",
-                &format_args!("{}", self.lstimer3_ovf().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch0",
-                &format_args!("{}", self.duty_chng_end_hsch0().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch1",
-                &format_args!("{}", self.duty_chng_end_hsch1().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch2",
-                &format_args!("{}", self.duty_chng_end_hsch2().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch3",
-                &format_args!("{}", self.duty_chng_end_hsch3().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch4",
-                &format_args!("{}", self.duty_chng_end_hsch4().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch5",
-                &format_args!("{}", self.duty_chng_end_hsch5().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch6",
-                &format_args!("{}", self.duty_chng_end_hsch6().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch7",
-                &format_args!("{}", self.duty_chng_end_hsch7().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch0",
-                &format_args!("{}", self.duty_chng_end_lsch0().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch1",
-                &format_args!("{}", self.duty_chng_end_lsch1().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch2",
-                &format_args!("{}", self.duty_chng_end_lsch2().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch3",
-                &format_args!("{}", self.duty_chng_end_lsch3().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch4",
-                &format_args!("{}", self.duty_chng_end_lsch4().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch5",
-                &format_args!("{}", self.duty_chng_end_lsch5().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch6",
-                &format_args!("{}", self.duty_chng_end_lsch6().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch7",
-                &format_args!("{}", self.duty_chng_end_lsch7().bit()),
-            )
+            .field("hstimer0_ovf", &self.hstimer0_ovf())
+            .field("hstimer1_ovf", &self.hstimer1_ovf())
+            .field("hstimer2_ovf", &self.hstimer2_ovf())
+            .field("hstimer3_ovf", &self.hstimer3_ovf())
+            .field("lstimer0_ovf", &self.lstimer0_ovf())
+            .field("lstimer1_ovf", &self.lstimer1_ovf())
+            .field("lstimer2_ovf", &self.lstimer2_ovf())
+            .field("lstimer3_ovf", &self.lstimer3_ovf())
+            .field("duty_chng_end_hsch0", &self.duty_chng_end_hsch0())
+            .field("duty_chng_end_hsch1", &self.duty_chng_end_hsch1())
+            .field("duty_chng_end_hsch2", &self.duty_chng_end_hsch2())
+            .field("duty_chng_end_hsch3", &self.duty_chng_end_hsch3())
+            .field("duty_chng_end_hsch4", &self.duty_chng_end_hsch4())
+            .field("duty_chng_end_hsch5", &self.duty_chng_end_hsch5())
+            .field("duty_chng_end_hsch6", &self.duty_chng_end_hsch6())
+            .field("duty_chng_end_hsch7", &self.duty_chng_end_hsch7())
+            .field("duty_chng_end_lsch0", &self.duty_chng_end_lsch0())
+            .field("duty_chng_end_lsch1", &self.duty_chng_end_lsch1())
+            .field("duty_chng_end_lsch2", &self.duty_chng_end_lsch2())
+            .field("duty_chng_end_lsch3", &self.duty_chng_end_lsch3())
+            .field("duty_chng_end_lsch4", &self.duty_chng_end_lsch4())
+            .field("duty_chng_end_lsch5", &self.duty_chng_end_lsch5())
+            .field("duty_chng_end_lsch6", &self.duty_chng_end_lsch6())
+            .field("duty_chng_end_lsch7", &self.duty_chng_end_lsch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt raw bit for high speed channel(0-3) counter overflow."]
     #[doc = ""]
diff --git a/esp32/src/ledc/int_st.rs b/esp32/src/ledc/int_st.rs
index d147b38103..ff4c3711d1 100644
--- a/esp32/src/ledc/int_st.rs
+++ b/esp32/src/ledc/int_st.rs
@@ -194,111 +194,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "hstimer0_ovf",
-                &format_args!("{}", self.hstimer0_ovf().bit()),
-            )
-            .field(
-                "hstimer1_ovf",
-                &format_args!("{}", self.hstimer1_ovf().bit()),
-            )
-            .field(
-                "hstimer2_ovf",
-                &format_args!("{}", self.hstimer2_ovf().bit()),
-            )
-            .field(
-                "hstimer3_ovf",
-                &format_args!("{}", self.hstimer3_ovf().bit()),
-            )
-            .field(
-                "lstimer0_ovf",
-                &format_args!("{}", self.lstimer0_ovf().bit()),
-            )
-            .field(
-                "lstimer1_ovf",
-                &format_args!("{}", self.lstimer1_ovf().bit()),
-            )
-            .field(
-                "lstimer2_ovf",
-                &format_args!("{}", self.lstimer2_ovf().bit()),
-            )
-            .field(
-                "lstimer3_ovf",
-                &format_args!("{}", self.lstimer3_ovf().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch0",
-                &format_args!("{}", self.duty_chng_end_hsch0().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch1",
-                &format_args!("{}", self.duty_chng_end_hsch1().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch2",
-                &format_args!("{}", self.duty_chng_end_hsch2().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch3",
-                &format_args!("{}", self.duty_chng_end_hsch3().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch4",
-                &format_args!("{}", self.duty_chng_end_hsch4().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch5",
-                &format_args!("{}", self.duty_chng_end_hsch5().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch6",
-                &format_args!("{}", self.duty_chng_end_hsch6().bit()),
-            )
-            .field(
-                "duty_chng_end_hsch7",
-                &format_args!("{}", self.duty_chng_end_hsch7().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch0",
-                &format_args!("{}", self.duty_chng_end_lsch0().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch1",
-                &format_args!("{}", self.duty_chng_end_lsch1().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch2",
-                &format_args!("{}", self.duty_chng_end_lsch2().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch3",
-                &format_args!("{}", self.duty_chng_end_lsch3().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch4",
-                &format_args!("{}", self.duty_chng_end_lsch4().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch5",
-                &format_args!("{}", self.duty_chng_end_lsch5().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch6",
-                &format_args!("{}", self.duty_chng_end_lsch6().bit()),
-            )
-            .field(
-                "duty_chng_end_lsch7",
-                &format_args!("{}", self.duty_chng_end_lsch7().bit()),
-            )
+            .field("hstimer0_ovf", &self.hstimer0_ovf())
+            .field("hstimer1_ovf", &self.hstimer1_ovf())
+            .field("hstimer2_ovf", &self.hstimer2_ovf())
+            .field("hstimer3_ovf", &self.hstimer3_ovf())
+            .field("lstimer0_ovf", &self.lstimer0_ovf())
+            .field("lstimer1_ovf", &self.lstimer1_ovf())
+            .field("lstimer2_ovf", &self.lstimer2_ovf())
+            .field("lstimer3_ovf", &self.lstimer3_ovf())
+            .field("duty_chng_end_hsch0", &self.duty_chng_end_hsch0())
+            .field("duty_chng_end_hsch1", &self.duty_chng_end_hsch1())
+            .field("duty_chng_end_hsch2", &self.duty_chng_end_hsch2())
+            .field("duty_chng_end_hsch3", &self.duty_chng_end_hsch3())
+            .field("duty_chng_end_hsch4", &self.duty_chng_end_hsch4())
+            .field("duty_chng_end_hsch5", &self.duty_chng_end_hsch5())
+            .field("duty_chng_end_hsch6", &self.duty_chng_end_hsch6())
+            .field("duty_chng_end_hsch7", &self.duty_chng_end_hsch7())
+            .field("duty_chng_end_lsch0", &self.duty_chng_end_lsch0())
+            .field("duty_chng_end_lsch1", &self.duty_chng_end_lsch1())
+            .field("duty_chng_end_lsch2", &self.duty_chng_end_lsch2())
+            .field("duty_chng_end_lsch3", &self.duty_chng_end_lsch3())
+            .field("duty_chng_end_lsch4", &self.duty_chng_end_lsch4())
+            .field("duty_chng_end_lsch5", &self.duty_chng_end_lsch5())
+            .field("duty_chng_end_lsch6", &self.duty_chng_end_lsch6())
+            .field("duty_chng_end_lsch7", &self.duty_chng_end_lsch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32/src/ledc/lsch/conf0.rs b/esp32/src/ledc/lsch/conf0.rs
index 4b0c46b966..6522094771 100644
--- a/esp32/src/ledc/lsch/conf0.rs
+++ b/esp32/src/ledc/lsch/conf0.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("timer_sel", &format_args!("{}", self.timer_sel().bits()))
-            .field("sig_out_en", &format_args!("{}", self.sig_out_en().bit()))
-            .field("idle_lv", &format_args!("{}", self.idle_lv().bit()))
-            .field("para_up", &format_args!("{}", self.para_up().bit()))
+            .field("timer_sel", &self.timer_sel())
+            .field("sig_out_en", &self.sig_out_en())
+            .field("idle_lv", &self.idle_lv())
+            .field("para_up", &self.para_up())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - There are four low speed timers the two bits are used to select one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3."]
     #[inline(always)]
diff --git a/esp32/src/ledc/lsch/conf1.rs b/esp32/src/ledc/lsch/conf1.rs
index 09c5ca8874..f8092e089a 100644
--- a/esp32/src/ledc/lsch/conf1.rs
+++ b/esp32/src/ledc/lsch/conf1.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field("duty_scale", &format_args!("{}", self.duty_scale().bits()))
-            .field("duty_cycle", &format_args!("{}", self.duty_cycle().bits()))
-            .field("duty_num", &format_args!("{}", self.duty_num().bits()))
-            .field("duty_inc", &format_args!("{}", self.duty_inc().bit()))
-            .field("duty_start", &format_args!("{}", self.duty_start().bit()))
+            .field("duty_scale", &self.duty_scale())
+            .field("duty_cycle", &self.duty_cycle())
+            .field("duty_num", &self.duty_num())
+            .field("duty_inc", &self.duty_inc())
+            .field("duty_start", &self.duty_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register controls the increase or decrease step scale for low speed channel0."]
     #[inline(always)]
diff --git a/esp32/src/ledc/lsch/duty.rs b/esp32/src/ledc/lsch/duty.rs
index b7e12e8ab7..7d6c4cb789 100644
--- a/esp32/src/ledc/lsch/duty.rs
+++ b/esp32/src/ledc/lsch/duty.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DUTY")
-            .field("duty", &format_args!("{}", self.duty().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DUTY").field("duty", &self.duty()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/ledc/lsch/duty_r.rs b/esp32/src/ledc/lsch/duty_r.rs
index cd2eb82764..fa3ad9a4d4 100644
--- a/esp32/src/ledc/lsch/duty_r.rs
+++ b/esp32/src/ledc/lsch/duty_r.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DUTY_R")
-            .field("duty_r", &format_args!("{}", self.duty_r().bits()))
+            .field("duty_r", &self.duty_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_R_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`duty_r::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DUTY_R_SPEC;
 impl crate::RegisterSpec for DUTY_R_SPEC {
diff --git a/esp32/src/ledc/lsch/hpoint.rs b/esp32/src/ledc/lsch/hpoint.rs
index d2f13ae77a..a4bde82e85 100644
--- a/esp32/src/ledc/lsch/hpoint.rs
+++ b/esp32/src/ledc/lsch/hpoint.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPOINT")
-            .field("hpoint", &format_args!("{}", self.hpoint().bits()))
+            .field("hpoint", &self.hpoint())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPOINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - The output value changes to high when lstimerx(x=\\[0 3\\]) selected by low speed channel0 has reached reg_hpoint_lsch0\\[19:0\\]"]
     #[inline(always)]
diff --git a/esp32/src/ledc/lstimer/conf.rs b/esp32/src/ledc/lstimer/conf.rs
index a0c02a4da9..fdf73187f5 100644
--- a/esp32/src/ledc/lstimer/conf.rs
+++ b/esp32/src/ledc/lstimer/conf.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("duty_res", &format_args!("{}", self.duty_res().bits()))
-            .field("div_num", &format_args!("{}", self.div_num().bits()))
-            .field("pause", &format_args!("{}", self.pause().bit()))
-            .field("rst", &format_args!("{}", self.rst().bit()))
-            .field("tick_sel", &format_args!("{}", self.tick_sel().bit()))
-            .field("para_up", &format_args!("{}", self.para_up().bit()))
+            .field("duty_res", &self.duty_res())
+            .field("div_num", &self.div_num())
+            .field("pause", &self.pause())
+            .field("rst", &self.rst())
+            .field("tick_sel", &self.tick_sel())
+            .field("para_up", &self.para_up())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register controls the range of the counter in low speed timer0. the counter range is \\[0 2**reg_lstimer0_lim\\] the max bit width for counter is 20."]
     #[inline(always)]
diff --git a/esp32/src/ledc/lstimer/value.rs b/esp32/src/ledc/lstimer/value.rs
index 3464ace18d..ff1f594e3f 100644
--- a/esp32/src/ledc/lstimer/value.rs
+++ b/esp32/src/ledc/lstimer/value.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("VALUE")
-            .field("cnt", &format_args!("{}", self.cnt().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("VALUE").field("cnt", &self.cnt()).finish()
     }
 }
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/lib.rs b/esp32/src/lib.rs
index ff121fa2e0..1cd8c11f93 100644
--- a/esp32/src/lib.rs
+++ b/esp32/src/lib.rs
@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32 microcontrollers (generated using svd2rust v0.33.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32 microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
diff --git a/esp32/src/mcpwm0/cap_ch.rs b/esp32/src/mcpwm0/cap_ch.rs
index 0ad800327f..abcc7ee595 100644
--- a/esp32/src/mcpwm0/cap_ch.rs
+++ b/esp32/src/mcpwm0/cap_ch.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_CH")
-            .field("value", &format_args!("{}", self.value().bits()))
+            .field("value", &self.value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Value of last capture on channel %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_ch::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CAP_CH_SPEC;
 impl crate::RegisterSpec for CAP_CH_SPEC {
diff --git a/esp32/src/mcpwm0/cap_ch_cfg.rs b/esp32/src/mcpwm0/cap_ch_cfg.rs
index 8eb52ea977..f4948b3ad8 100644
--- a/esp32/src/mcpwm0/cap_ch_cfg.rs
+++ b/esp32/src/mcpwm0/cap_ch_cfg.rs
@@ -46,19 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_CH_CFG")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
-            .field("in_invert", &format_args!("{}", self.in_invert().bit()))
+            .field("en", &self.en())
+            .field("mode", &self.mode())
+            .field("prescale", &self.prescale())
+            .field("in_invert", &self.in_invert())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_CH_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/cap_status.rs b/esp32/src/mcpwm0/cap_status.rs
index 2d6fe2c440..e69b9ceca3 100644
--- a/esp32/src/mcpwm0/cap_status.rs
+++ b/esp32/src/mcpwm0/cap_status.rs
@@ -27,18 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_STATUS")
-            .field("cap0_edge", &format_args!("{}", self.cap0_edge().bit()))
-            .field("cap1_edge", &format_args!("{}", self.cap1_edge().bit()))
-            .field("cap2_edge", &format_args!("{}", self.cap2_edge().bit()))
+            .field("cap0_edge", &self.cap0_edge())
+            .field("cap1_edge", &self.cap1_edge())
+            .field("cap2_edge", &self.cap2_edge())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CAP_STATUS_SPEC;
 impl crate::RegisterSpec for CAP_STATUS_SPEC {
diff --git a/esp32/src/mcpwm0/cap_timer_cfg.rs b/esp32/src/mcpwm0/cap_timer_cfg.rs
index 32ca3cfd3f..de7fba705e 100644
--- a/esp32/src/mcpwm0/cap_timer_cfg.rs
+++ b/esp32/src/mcpwm0/cap_timer_cfg.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_TIMER_CFG")
-            .field(
-                "cap_timer_en",
-                &format_args!("{}", self.cap_timer_en().bit()),
-            )
-            .field(
-                "cap_synci_en",
-                &format_args!("{}", self.cap_synci_en().bit()),
-            )
-            .field(
-                "cap_synci_sel",
-                &format_args!("{}", self.cap_synci_sel().bits()),
-            )
+            .field("cap_timer_en", &self.cap_timer_en())
+            .field("cap_synci_en", &self.cap_synci_en())
+            .field("cap_synci_sel", &self.cap_synci_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_TIMER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/cap_timer_phase.rs b/esp32/src/mcpwm0/cap_timer_phase.rs
index 9937020ad2..8c5d8279dd 100644
--- a/esp32/src/mcpwm0/cap_timer_phase.rs
+++ b/esp32/src/mcpwm0/cap_timer_phase.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_TIMER_PHASE")
-            .field(
-                "cap_timer_phase",
-                &format_args!("{}", self.cap_timer_phase().bits()),
-            )
+            .field("cap_timer_phase", &self.cap_timer_phase())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_TIMER_PHASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/ch/carrier_cfg.rs b/esp32/src/mcpwm0/ch/carrier_cfg.rs
index 2935186471..bf354974f1 100644
--- a/esp32/src/mcpwm0/ch/carrier_cfg.rs
+++ b/esp32/src/mcpwm0/ch/carrier_cfg.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CARRIER_CFG")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
-            .field("duty", &format_args!("{}", self.duty().bits()))
-            .field("oshtwth", &format_args!("{}", self.oshtwth().bits()))
-            .field("out_invert", &format_args!("{}", self.out_invert().bit()))
-            .field("in_invert", &format_args!("{}", self.in_invert().bit()))
+            .field("en", &self.en())
+            .field("prescale", &self.prescale())
+            .field("duty", &self.duty())
+            .field("oshtwth", &self.oshtwth())
+            .field("out_invert", &self.out_invert())
+            .field("in_invert", &self.in_invert())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CARRIER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/ch/dt_cfg.rs b/esp32/src/mcpwm0/ch/dt_cfg.rs
index 1c507acdd4..d3a886379f 100644
--- a/esp32/src/mcpwm0/ch/dt_cfg.rs
+++ b/esp32/src/mcpwm0/ch/dt_cfg.rs
@@ -116,39 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DT_CFG")
-            .field(
-                "fed_upmethod",
-                &format_args!("{}", self.fed_upmethod().bits()),
-            )
-            .field(
-                "red_upmethod",
-                &format_args!("{}", self.red_upmethod().bits()),
-            )
-            .field("deb_mode", &format_args!("{}", self.deb_mode().bit()))
-            .field("a_outswap", &format_args!("{}", self.a_outswap().bit()))
-            .field("b_outswap", &format_args!("{}", self.b_outswap().bit()))
-            .field("red_insel", &format_args!("{}", self.red_insel().bit()))
-            .field("fed_insel", &format_args!("{}", self.fed_insel().bit()))
-            .field(
-                "red_outinvert",
-                &format_args!("{}", self.red_outinvert().bit()),
-            )
-            .field(
-                "fed_outinvert",
-                &format_args!("{}", self.fed_outinvert().bit()),
-            )
-            .field("a_outbypass", &format_args!("{}", self.a_outbypass().bit()))
-            .field("b_outbypass", &format_args!("{}", self.b_outbypass().bit()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bit()))
+            .field("fed_upmethod", &self.fed_upmethod())
+            .field("red_upmethod", &self.red_upmethod())
+            .field("deb_mode", &self.deb_mode())
+            .field("a_outswap", &self.a_outswap())
+            .field("b_outswap", &self.b_outswap())
+            .field("red_insel", &self.red_insel())
+            .field("fed_insel", &self.fed_insel())
+            .field("red_outinvert", &self.red_outinvert())
+            .field("fed_outinvert", &self.fed_outinvert())
+            .field("a_outbypass", &self.a_outbypass())
+            .field("b_outbypass", &self.b_outbypass())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DT_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/ch/dt_fed_cfg.rs b/esp32/src/mcpwm0/ch/dt_fed_cfg.rs
index fc2eafc348..c4a1678ab5 100644
--- a/esp32/src/mcpwm0/ch/dt_fed_cfg.rs
+++ b/esp32/src/mcpwm0/ch/dt_fed_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DT_FED_CFG")
-            .field("fed", &format_args!("{}", self.fed().bits()))
+            .field("fed", &self.fed())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DT_FED_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/ch/dt_red_cfg.rs b/esp32/src/mcpwm0/ch/dt_red_cfg.rs
index f76c1a69ab..34c8cdb851 100644
--- a/esp32/src/mcpwm0/ch/dt_red_cfg.rs
+++ b/esp32/src/mcpwm0/ch/dt_red_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DT_RED_CFG")
-            .field("red", &format_args!("{}", self.red().bits()))
+            .field("red", &self.red())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DT_RED_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/ch/fh_cfg0.rs b/esp32/src/mcpwm0/ch/fh_cfg0.rs
index f74a122820..cfc83174c9 100644
--- a/esp32/src/mcpwm0/ch/fh_cfg0.rs
+++ b/esp32/src/mcpwm0/ch/fh_cfg0.rs
@@ -152,31 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FH_CFG0")
-            .field("sw_cbc", &format_args!("{}", self.sw_cbc().bit()))
-            .field("f2_cbc", &format_args!("{}", self.f2_cbc().bit()))
-            .field("f1_cbc", &format_args!("{}", self.f1_cbc().bit()))
-            .field("f0_cbc", &format_args!("{}", self.f0_cbc().bit()))
-            .field("sw_ost", &format_args!("{}", self.sw_ost().bit()))
-            .field("f2_ost", &format_args!("{}", self.f2_ost().bit()))
-            .field("f1_ost", &format_args!("{}", self.f1_ost().bit()))
-            .field("f0_ost", &format_args!("{}", self.f0_ost().bit()))
-            .field("a_cbc_d", &format_args!("{}", self.a_cbc_d().bits()))
-            .field("a_cbc_u", &format_args!("{}", self.a_cbc_u().bits()))
-            .field("a_ost_d", &format_args!("{}", self.a_ost_d().bits()))
-            .field("a_ost_u", &format_args!("{}", self.a_ost_u().bits()))
-            .field("b_cbc_d", &format_args!("{}", self.b_cbc_d().bits()))
-            .field("b_cbc_u", &format_args!("{}", self.b_cbc_u().bits()))
-            .field("b_ost_d", &format_args!("{}", self.b_ost_d().bits()))
-            .field("b_ost_u", &format_args!("{}", self.b_ost_u().bits()))
+            .field("sw_cbc", &self.sw_cbc())
+            .field("f2_cbc", &self.f2_cbc())
+            .field("f1_cbc", &self.f1_cbc())
+            .field("f0_cbc", &self.f0_cbc())
+            .field("sw_ost", &self.sw_ost())
+            .field("f2_ost", &self.f2_ost())
+            .field("f1_ost", &self.f1_ost())
+            .field("f0_ost", &self.f0_ost())
+            .field("a_cbc_d", &self.a_cbc_d())
+            .field("a_cbc_u", &self.a_cbc_u())
+            .field("a_ost_d", &self.a_ost_d())
+            .field("a_ost_u", &self.a_ost_u())
+            .field("b_cbc_d", &self.b_cbc_d())
+            .field("b_cbc_u", &self.b_cbc_u())
+            .field("b_ost_d", &self.b_ost_d())
+            .field("b_ost_u", &self.b_ost_u())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FH_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/ch/fh_cfg1.rs b/esp32/src/mcpwm0/ch/fh_cfg1.rs
index f935dadb75..83a9c40e81 100644
--- a/esp32/src/mcpwm0/ch/fh_cfg1.rs
+++ b/esp32/src/mcpwm0/ch/fh_cfg1.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FH_CFG1")
-            .field("clr_ost", &format_args!("{}", self.clr_ost().bit()))
-            .field("cbcpulse", &format_args!("{}", self.cbcpulse().bits()))
-            .field("force_cbc", &format_args!("{}", self.force_cbc().bit()))
-            .field("force_ost", &format_args!("{}", self.force_ost().bit()))
+            .field("clr_ost", &self.clr_ost())
+            .field("cbcpulse", &self.cbcpulse())
+            .field("force_cbc", &self.force_cbc())
+            .field("force_ost", &self.force_ost())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FH_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/ch/fh_status.rs b/esp32/src/mcpwm0/ch/fh_status.rs
index f265d438a1..dad13974f3 100644
--- a/esp32/src/mcpwm0/ch/fh_status.rs
+++ b/esp32/src/mcpwm0/ch/fh_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FH_STATUS")
-            .field("cbc_on", &format_args!("{}", self.cbc_on().bit()))
-            .field("ost_on", &format_args!("{}", self.ost_on().bit()))
+            .field("cbc_on", &self.cbc_on())
+            .field("ost_on", &self.ost_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FH_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of fault events.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FH_STATUS_SPEC;
 impl crate::RegisterSpec for FH_STATUS_SPEC {
diff --git a/esp32/src/mcpwm0/ch/gen.rs b/esp32/src/mcpwm0/ch/gen.rs
index 3e87d806f9..0f48fbc6db 100644
--- a/esp32/src/mcpwm0/ch/gen.rs
+++ b/esp32/src/mcpwm0/ch/gen.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN")
-            .field("utez", &format_args!("{}", self.utez().bits()))
-            .field("utep", &format_args!("{}", self.utep().bits()))
-            .field("utea", &format_args!("{}", self.utea().bits()))
-            .field("uteb", &format_args!("{}", self.uteb().bits()))
-            .field("ut0", &format_args!("{}", self.ut0().bits()))
-            .field("ut1", &format_args!("{}", self.ut1().bits()))
-            .field("dtez", &format_args!("{}", self.dtez().bits()))
-            .field("dtep", &format_args!("{}", self.dtep().bits()))
-            .field("dtea", &format_args!("{}", self.dtea().bits()))
-            .field("dteb", &format_args!("{}", self.dteb().bits()))
-            .field("dt0", &format_args!("{}", self.dt0().bits()))
-            .field("dt1", &format_args!("{}", self.dt1().bits()))
+            .field("utez", &self.utez())
+            .field("utep", &self.utep())
+            .field("utea", &self.utea())
+            .field("uteb", &self.uteb())
+            .field("ut0", &self.ut0())
+            .field("ut1", &self.ut1())
+            .field("dtez", &self.dtez())
+            .field("dtep", &self.dtep())
+            .field("dtea", &self.dtea())
+            .field("dteb", &self.dteb())
+            .field("dt0", &self.dt0())
+            .field("dt1", &self.dt1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/ch/gen_cfg0.rs b/esp32/src/mcpwm0/ch/gen_cfg0.rs
index 7ed37fd49e..a1f5bdf37e 100644
--- a/esp32/src/mcpwm0/ch/gen_cfg0.rs
+++ b/esp32/src/mcpwm0/ch/gen_cfg0.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_CFG0")
-            .field(
-                "cfg_upmethod",
-                &format_args!("{}", self.cfg_upmethod().bits()),
-            )
-            .field("t0_sel", &format_args!("{}", self.t0_sel().bits()))
-            .field("t1_sel", &format_args!("{}", self.t1_sel().bits()))
+            .field("cfg_upmethod", &self.cfg_upmethod())
+            .field("t0_sel", &self.t0_sel())
+            .field("t1_sel", &self.t1_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/ch/gen_force.rs b/esp32/src/mcpwm0/ch/gen_force.rs
index 21fe0206a6..971443f21d 100644
--- a/esp32/src/mcpwm0/ch/gen_force.rs
+++ b/esp32/src/mcpwm0/ch/gen_force.rs
@@ -71,37 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_FORCE")
-            .field(
-                "cntuforce_upmethod",
-                &format_args!("{}", self.cntuforce_upmethod().bits()),
-            )
-            .field(
-                "a_cntuforce_mode",
-                &format_args!("{}", self.a_cntuforce_mode().bits()),
-            )
-            .field(
-                "b_cntuforce_mode",
-                &format_args!("{}", self.b_cntuforce_mode().bits()),
-            )
-            .field("a_nciforce", &format_args!("{}", self.a_nciforce().bit()))
-            .field(
-                "a_nciforce_mode",
-                &format_args!("{}", self.a_nciforce_mode().bits()),
-            )
-            .field("b_nciforce", &format_args!("{}", self.b_nciforce().bit()))
-            .field(
-                "b_nciforce_mode",
-                &format_args!("{}", self.b_nciforce_mode().bits()),
-            )
+            .field("cntuforce_upmethod", &self.cntuforce_upmethod())
+            .field("a_cntuforce_mode", &self.a_cntuforce_mode())
+            .field("b_cntuforce_mode", &self.b_cntuforce_mode())
+            .field("a_nciforce", &self.a_nciforce())
+            .field("a_nciforce_mode", &self.a_nciforce_mode())
+            .field("b_nciforce", &self.b_nciforce())
+            .field("b_nciforce_mode", &self.b_nciforce_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_FORCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/ch/gen_stmp_cfg.rs b/esp32/src/mcpwm0/ch/gen_stmp_cfg.rs
index 76c321c6a1..d89a5f2889 100644
--- a/esp32/src/mcpwm0/ch/gen_stmp_cfg.rs
+++ b/esp32/src/mcpwm0/ch/gen_stmp_cfg.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_STMP_CFG")
-            .field("a_upmethod", &format_args!("{}", self.a_upmethod().bits()))
-            .field("b_upmethod", &format_args!("{}", self.b_upmethod().bits()))
-            .field("a_shdw_full", &format_args!("{}", self.a_shdw_full().bit()))
-            .field("b_shdw_full", &format_args!("{}", self.b_shdw_full().bit()))
+            .field("a_upmethod", &self.a_upmethod())
+            .field("b_upmethod", &self.b_upmethod())
+            .field("a_shdw_full", &self.a_shdw_full())
+            .field("b_shdw_full", &self.b_shdw_full())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_STMP_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/ch/gen_tstmp_a.rs b/esp32/src/mcpwm0/ch/gen_tstmp_a.rs
index f39155bb07..fc069b381e 100644
--- a/esp32/src/mcpwm0/ch/gen_tstmp_a.rs
+++ b/esp32/src/mcpwm0/ch/gen_tstmp_a.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("GEN_TSTMP_A")
-            .field("a", &format_args!("{}", self.a().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_TSTMP_A_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("GEN_TSTMP_A").field("a", &self.a()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/mcpwm0/ch/gen_tstmp_b.rs b/esp32/src/mcpwm0/ch/gen_tstmp_b.rs
index dc698ba850..2912392ff5 100644
--- a/esp32/src/mcpwm0/ch/gen_tstmp_b.rs
+++ b/esp32/src/mcpwm0/ch/gen_tstmp_b.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("GEN_TSTMP_B")
-            .field("b", &format_args!("{}", self.b().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_TSTMP_B_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("GEN_TSTMP_B").field("b", &self.b()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/mcpwm0/clk.rs b/esp32/src/mcpwm0/clk.rs
index c3fe4315a7..e822d48f61 100644
--- a/esp32/src/mcpwm0/clk.rs
+++ b/esp32/src/mcpwm0/clk.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CLK")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CLK").field("en", &self.en()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/mcpwm0/clk_cfg.rs b/esp32/src/mcpwm0/clk_cfg.rs
index 5f8deea12c..cb6d959273 100644
--- a/esp32/src/mcpwm0/clk_cfg.rs
+++ b/esp32/src/mcpwm0/clk_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CFG")
-            .field(
-                "clk_prescale",
-                &format_args!("{}", self.clk_prescale().bits()),
-            )
+            .field("clk_prescale", &self.clk_prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/fault_detect.rs b/esp32/src/mcpwm0/fault_detect.rs
index 384fcaaf33..522e91a9c7 100644
--- a/esp32/src/mcpwm0/fault_detect.rs
+++ b/esp32/src/mcpwm0/fault_detect.rs
@@ -83,24 +83,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FAULT_DETECT")
-            .field("f0_en", &format_args!("{}", self.f0_en().bit()))
-            .field("f1_en", &format_args!("{}", self.f1_en().bit()))
-            .field("f2_en", &format_args!("{}", self.f2_en().bit()))
-            .field("f0_pole", &format_args!("{}", self.f0_pole().bit()))
-            .field("f1_pole", &format_args!("{}", self.f1_pole().bit()))
-            .field("f2_pole", &format_args!("{}", self.f2_pole().bit()))
-            .field("event_f0", &format_args!("{}", self.event_f0().bit()))
-            .field("event_f1", &format_args!("{}", self.event_f1().bit()))
-            .field("event_f2", &format_args!("{}", self.event_f2().bit()))
+            .field("f0_en", &self.f0_en())
+            .field("f1_en", &self.f1_en())
+            .field("f2_en", &self.f2_en())
+            .field("f0_pole", &self.f0_pole())
+            .field("f1_pole", &self.f1_pole())
+            .field("f2_pole", &self.f2_pole())
+            .field("event_f0", &self.event_f0())
+            .field("event_f1", &self.event_f1())
+            .field("event_f2", &self.event_f2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FAULT_DETECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/int_ena.rs b/esp32/src/mcpwm0/int_ena.rs
index 018fc58ee5..bc324d183f 100644
--- a/esp32/src/mcpwm0/int_ena.rs
+++ b/esp32/src/mcpwm0/int_ena.rs
@@ -278,45 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("fault0", &format_args!("{}", self.fault0().bit()))
-            .field("fault1", &format_args!("{}", self.fault1().bit()))
-            .field("fault2", &format_args!("{}", self.fault2().bit()))
-            .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
-            .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
-            .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
-            .field("op0_tea", &format_args!("{}", self.op0_tea().bit()))
-            .field("op1_tea", &format_args!("{}", self.op1_tea().bit()))
-            .field("op2_tea", &format_args!("{}", self.op2_tea().bit()))
-            .field("op0_teb", &format_args!("{}", self.op0_teb().bit()))
-            .field("op1_teb", &format_args!("{}", self.op1_teb().bit()))
-            .field("op2_teb", &format_args!("{}", self.op2_teb().bit()))
-            .field("fh0_cbc", &format_args!("{}", self.fh0_cbc().bit()))
-            .field("fh1_cbc", &format_args!("{}", self.fh1_cbc().bit()))
-            .field("fh2_cbc", &format_args!("{}", self.fh2_cbc().bit()))
-            .field("fh0_ost", &format_args!("{}", self.fh0_ost().bit()))
-            .field("fh1_ost", &format_args!("{}", self.fh1_ost().bit()))
-            .field("fh2_ost", &format_args!("{}", self.fh2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("op0_tea", &self.op0_tea())
+            .field("op1_tea", &self.op1_tea())
+            .field("op2_tea", &self.op2_tea())
+            .field("op0_teb", &self.op0_teb())
+            .field("op1_teb", &self.op1_teb())
+            .field("op2_teb", &self.op2_teb())
+            .field("fh0_cbc", &self.fh0_cbc())
+            .field("fh1_cbc", &self.fh1_cbc())
+            .field("fh2_cbc", &self.fh2_cbc())
+            .field("fh0_ost", &self.fh0_ost())
+            .field("fh1_ost", &self.fh1_ost())
+            .field("fh2_ost", &self.fh2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/int_raw.rs b/esp32/src/mcpwm0/int_raw.rs
index bdab46cd61..99d9ff0f5c 100644
--- a/esp32/src/mcpwm0/int_raw.rs
+++ b/esp32/src/mcpwm0/int_raw.rs
@@ -278,45 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("fault0", &format_args!("{}", self.fault0().bit()))
-            .field("fault1", &format_args!("{}", self.fault1().bit()))
-            .field("fault2", &format_args!("{}", self.fault2().bit()))
-            .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
-            .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
-            .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
-            .field("op0_tea", &format_args!("{}", self.op0_tea().bit()))
-            .field("op1_tea", &format_args!("{}", self.op1_tea().bit()))
-            .field("op2_tea", &format_args!("{}", self.op2_tea().bit()))
-            .field("op0_teb", &format_args!("{}", self.op0_teb().bit()))
-            .field("op1_teb", &format_args!("{}", self.op1_teb().bit()))
-            .field("op2_teb", &format_args!("{}", self.op2_teb().bit()))
-            .field("fh0_cbc", &format_args!("{}", self.fh0_cbc().bit()))
-            .field("fh1_cbc", &format_args!("{}", self.fh1_cbc().bit()))
-            .field("fh2_cbc", &format_args!("{}", self.fh2_cbc().bit()))
-            .field("fh0_ost", &format_args!("{}", self.fh0_ost().bit()))
-            .field("fh1_ost", &format_args!("{}", self.fh1_ost().bit()))
-            .field("fh2_ost", &format_args!("{}", self.fh2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("op0_tea", &self.op0_tea())
+            .field("op1_tea", &self.op1_tea())
+            .field("op2_tea", &self.op2_tea())
+            .field("op0_teb", &self.op0_teb())
+            .field("op1_teb", &self.op1_teb())
+            .field("op2_teb", &self.op2_teb())
+            .field("fh0_cbc", &self.fh0_cbc())
+            .field("fh1_cbc", &self.fh1_cbc())
+            .field("fh2_cbc", &self.fh2_cbc())
+            .field("fh0_ost", &self.fh0_ost())
+            .field("fh1_ost", &self.fh1_ost())
+            .field("fh2_ost", &self.fh2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/int_st.rs b/esp32/src/mcpwm0/int_st.rs
index 8c88370551..d0b132e22d 100644
--- a/esp32/src/mcpwm0/int_st.rs
+++ b/esp32/src/mcpwm0/int_st.rs
@@ -216,45 +216,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("fault0", &format_args!("{}", self.fault0().bit()))
-            .field("fault1", &format_args!("{}", self.fault1().bit()))
-            .field("fault2", &format_args!("{}", self.fault2().bit()))
-            .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
-            .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
-            .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
-            .field("op0_tea", &format_args!("{}", self.op0_tea().bit()))
-            .field("op1_tea", &format_args!("{}", self.op1_tea().bit()))
-            .field("op2_tea", &format_args!("{}", self.op2_tea().bit()))
-            .field("op0_teb", &format_args!("{}", self.op0_teb().bit()))
-            .field("op1_teb", &format_args!("{}", self.op1_teb().bit()))
-            .field("op2_teb", &format_args!("{}", self.op2_teb().bit()))
-            .field("fh0_cbc", &format_args!("{}", self.fh0_cbc().bit()))
-            .field("fh1_cbc", &format_args!("{}", self.fh1_cbc().bit()))
-            .field("fh2_cbc", &format_args!("{}", self.fh2_cbc().bit()))
-            .field("fh0_ost", &format_args!("{}", self.fh0_ost().bit()))
-            .field("fh1_ost", &format_args!("{}", self.fh1_ost().bit()))
-            .field("fh2_ost", &format_args!("{}", self.fh2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("op0_tea", &self.op0_tea())
+            .field("op1_tea", &self.op1_tea())
+            .field("op2_tea", &self.op2_tea())
+            .field("op0_teb", &self.op0_teb())
+            .field("op1_teb", &self.op1_teb())
+            .field("op2_teb", &self.op2_teb())
+            .field("fh0_cbc", &self.fh0_cbc())
+            .field("fh1_cbc", &self.fh1_cbc())
+            .field("fh2_cbc", &self.fh2_cbc())
+            .field("fh0_ost", &self.fh0_ost())
+            .field("fh1_ost", &self.fh1_ost())
+            .field("fh2_ost", &self.fh2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32/src/mcpwm0/operator_timersel.rs b/esp32/src/mcpwm0/operator_timersel.rs
index 48f0bc53fa..3cf2981dcf 100644
--- a/esp32/src/mcpwm0/operator_timersel.rs
+++ b/esp32/src/mcpwm0/operator_timersel.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OPERATOR_TIMERSEL")
-            .field(
-                "operator0_timersel",
-                &format_args!("{}", self.operator0_timersel().bits()),
-            )
-            .field(
-                "operator1_timersel",
-                &format_args!("{}", self.operator1_timersel().bits()),
-            )
-            .field(
-                "operator2_timersel",
-                &format_args!("{}", self.operator2_timersel().bits()),
-            )
+            .field("operator0_timersel", &self.operator0_timersel())
+            .field("operator1_timersel", &self.operator1_timersel())
+            .field("operator2_timersel", &self.operator2_timersel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OPERATOR_TIMERSEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/timer/cfg0.rs b/esp32/src/mcpwm0/timer/cfg0.rs
index 2d95fbd892..393c347100 100644
--- a/esp32/src/mcpwm0/timer/cfg0.rs
+++ b/esp32/src/mcpwm0/timer/cfg0.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG0")
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
-            .field("period", &format_args!("{}", self.period().bits()))
-            .field(
-                "period_upmethod",
-                &format_args!("{}", self.period_upmethod().bits()),
-            )
+            .field("prescale", &self.prescale())
+            .field("period", &self.period())
+            .field("period_upmethod", &self.period_upmethod())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/timer/cfg1.rs b/esp32/src/mcpwm0/timer/cfg1.rs
index b4d9541f04..335111d862 100644
--- a/esp32/src/mcpwm0/timer/cfg1.rs
+++ b/esp32/src/mcpwm0/timer/cfg1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG1")
-            .field("start", &format_args!("{}", self.start().bits()))
-            .field("mod_", &format_args!("{}", self.mod_().bits()))
+            .field("start", &self.start())
+            .field("mod_", &self.mod_())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/timer/status.rs b/esp32/src/mcpwm0/timer/status.rs
index eb14d50ceb..500ba93403 100644
--- a/esp32/src/mcpwm0/timer/status.rs
+++ b/esp32/src/mcpwm0/timer/status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("value", &format_args!("{}", self.value().bits()))
-            .field("direction", &format_args!("{}", self.direction().bit()))
+            .field("value", &self.value())
+            .field("direction", &self.direction())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "PWM TIMERx status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32/src/mcpwm0/timer/sync.rs b/esp32/src/mcpwm0/timer/sync.rs
index f93674dad1..058d606713 100644
--- a/esp32/src/mcpwm0/timer/sync.rs
+++ b/esp32/src/mcpwm0/timer/sync.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYNC")
-            .field("synci_en", &format_args!("{}", self.synci_en().bit()))
-            .field("sw", &format_args!("{}", self.sw().bit()))
-            .field("synco_sel", &format_args!("{}", self.synco_sel().bits()))
-            .field("phase", &format_args!("{}", self.phase().bits()))
-            .field(
-                "phase_direction",
-                &format_args!("{}", self.phase_direction().bit()),
-            )
+            .field("synci_en", &self.synci_en())
+            .field("sw", &self.sw())
+            .field("synco_sel", &self.synco_sel())
+            .field("phase", &self.phase())
+            .field("phase_direction", &self.phase_direction())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/timer_synci_cfg.rs b/esp32/src/mcpwm0/timer_synci_cfg.rs
index 352813633e..259c3dbf6f 100644
--- a/esp32/src/mcpwm0/timer_synci_cfg.rs
+++ b/esp32/src/mcpwm0/timer_synci_cfg.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_SYNCI_CFG")
-            .field(
-                "timer0_syncisel",
-                &format_args!("{}", self.timer0_syncisel().bits()),
-            )
-            .field(
-                "timer1_syncisel",
-                &format_args!("{}", self.timer1_syncisel().bits()),
-            )
-            .field(
-                "timer2_syncisel",
-                &format_args!("{}", self.timer2_syncisel().bits()),
-            )
-            .field(
-                "external_synci0_invert",
-                &format_args!("{}", self.external_synci0_invert().bit()),
-            )
-            .field(
-                "external_synci1_invert",
-                &format_args!("{}", self.external_synci1_invert().bit()),
-            )
-            .field(
-                "external_synci2_invert",
-                &format_args!("{}", self.external_synci2_invert().bit()),
-            )
+            .field("timer0_syncisel", &self.timer0_syncisel())
+            .field("timer1_syncisel", &self.timer1_syncisel())
+            .field("timer2_syncisel", &self.timer2_syncisel())
+            .field("external_synci0_invert", &self.external_synci0_invert())
+            .field("external_synci1_invert", &self.external_synci1_invert())
+            .field("external_synci2_invert", &self.external_synci2_invert())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_SYNCI_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/update_cfg.rs b/esp32/src/mcpwm0/update_cfg.rs
index 5e6727ae7b..3234c10dcc 100644
--- a/esp32/src/mcpwm0/update_cfg.rs
+++ b/esp32/src/mcpwm0/update_cfg.rs
@@ -80,38 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE_CFG")
-            .field(
-                "global_up_en",
-                &format_args!("{}", self.global_up_en().bit()),
-            )
-            .field(
-                "global_force_up",
-                &format_args!("{}", self.global_force_up().bit()),
-            )
-            .field("op0_up_en", &format_args!("{}", self.op0_up_en().bit()))
-            .field(
-                "op0_force_up",
-                &format_args!("{}", self.op0_force_up().bit()),
-            )
-            .field("op1_up_en", &format_args!("{}", self.op1_up_en().bit()))
-            .field(
-                "op1_force_up",
-                &format_args!("{}", self.op1_force_up().bit()),
-            )
-            .field("op2_up_en", &format_args!("{}", self.op2_up_en().bit()))
-            .field(
-                "op2_force_up",
-                &format_args!("{}", self.op2_force_up().bit()),
-            )
+            .field("global_up_en", &self.global_up_en())
+            .field("global_force_up", &self.global_force_up())
+            .field("op0_up_en", &self.op0_up_en())
+            .field("op0_force_up", &self.op0_force_up())
+            .field("op1_up_en", &self.op1_up_en())
+            .field("op1_force_up", &self.op1_force_up())
+            .field("op2_up_en", &self.op2_up_en())
+            .field("op2_force_up", &self.op2_force_up())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/mcpwm0/version.rs b/esp32/src/mcpwm0/version.rs
index fcfa130756..7aa8ea7a9d 100644
--- a/esp32/src/mcpwm0/version.rs
+++ b/esp32/src/mcpwm0/version.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27"]
     #[inline(always)]
diff --git a/esp32/src/nrx/nrxpd_ctrl.rs b/esp32/src/nrx/nrxpd_ctrl.rs
index b3414c74f0..cc6d942cda 100644
--- a/esp32/src/nrx/nrxpd_ctrl.rs
+++ b/esp32/src/nrx/nrxpd_ctrl.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NRXPD_CTRL")
-            .field(
-                "demap_force_pd",
-                &format_args!("{}", self.demap_force_pd().bit()),
-            )
-            .field(
-                "demap_force_pu",
-                &format_args!("{}", self.demap_force_pu().bit()),
-            )
-            .field(
-                "vit_force_pd",
-                &format_args!("{}", self.vit_force_pd().bit()),
-            )
-            .field(
-                "vit_force_pu",
-                &format_args!("{}", self.vit_force_pu().bit()),
-            )
-            .field(
-                "rx_rot_force_pd",
-                &format_args!("{}", self.rx_rot_force_pd().bit()),
-            )
-            .field(
-                "rx_rot_force_pu",
-                &format_args!("{}", self.rx_rot_force_pu().bit()),
-            )
-            .field(
-                "chan_est_force_pd",
-                &format_args!("{}", self.chan_est_force_pd().bit()),
-            )
-            .field(
-                "chan_est_force_pu",
-                &format_args!("{}", self.chan_est_force_pu().bit()),
-            )
+            .field("demap_force_pd", &self.demap_force_pd())
+            .field("demap_force_pu", &self.demap_force_pu())
+            .field("vit_force_pd", &self.vit_force_pd())
+            .field("vit_force_pu", &self.vit_force_pu())
+            .field("rx_rot_force_pd", &self.rx_rot_force_pd())
+            .field("rx_rot_force_pu", &self.rx_rot_force_pu())
+            .field("chan_est_force_pd", &self.chan_est_force_pd())
+            .field("chan_est_force_pu", &self.chan_est_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NRXPD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/pcnt/ctrl.rs b/esp32/src/pcnt/ctrl.rs
index 07978b3c03..8ac1a745ff 100644
--- a/esp32/src/pcnt/ctrl.rs
+++ b/esp32/src/pcnt/ctrl.rs
@@ -135,56 +135,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("cnt_rst_u0", &format_args!("{}", self.cnt_rst_u0().bit()))
-            .field("cnt_rst_u1", &format_args!("{}", self.cnt_rst_u1().bit()))
-            .field("cnt_rst_u2", &format_args!("{}", self.cnt_rst_u2().bit()))
-            .field("cnt_rst_u3", &format_args!("{}", self.cnt_rst_u3().bit()))
-            .field("cnt_rst_u4", &format_args!("{}", self.cnt_rst_u4().bit()))
-            .field("cnt_rst_u5", &format_args!("{}", self.cnt_rst_u5().bit()))
-            .field("cnt_rst_u6", &format_args!("{}", self.cnt_rst_u6().bit()))
-            .field("cnt_rst_u7", &format_args!("{}", self.cnt_rst_u7().bit()))
-            .field(
-                "cnt_pause_u0",
-                &format_args!("{}", self.cnt_pause_u0().bit()),
-            )
-            .field(
-                "cnt_pause_u1",
-                &format_args!("{}", self.cnt_pause_u1().bit()),
-            )
-            .field(
-                "cnt_pause_u2",
-                &format_args!("{}", self.cnt_pause_u2().bit()),
-            )
-            .field(
-                "cnt_pause_u3",
-                &format_args!("{}", self.cnt_pause_u3().bit()),
-            )
-            .field(
-                "cnt_pause_u4",
-                &format_args!("{}", self.cnt_pause_u4().bit()),
-            )
-            .field(
-                "cnt_pause_u5",
-                &format_args!("{}", self.cnt_pause_u5().bit()),
-            )
-            .field(
-                "cnt_pause_u6",
-                &format_args!("{}", self.cnt_pause_u6().bit()),
-            )
-            .field(
-                "cnt_pause_u7",
-                &format_args!("{}", self.cnt_pause_u7().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("cnt_rst_u0", &self.cnt_rst_u0())
+            .field("cnt_rst_u1", &self.cnt_rst_u1())
+            .field("cnt_rst_u2", &self.cnt_rst_u2())
+            .field("cnt_rst_u3", &self.cnt_rst_u3())
+            .field("cnt_rst_u4", &self.cnt_rst_u4())
+            .field("cnt_rst_u5", &self.cnt_rst_u5())
+            .field("cnt_rst_u6", &self.cnt_rst_u6())
+            .field("cnt_rst_u7", &self.cnt_rst_u7())
+            .field("cnt_pause_u0", &self.cnt_pause_u0())
+            .field("cnt_pause_u1", &self.cnt_pause_u1())
+            .field("cnt_pause_u2", &self.cnt_pause_u2())
+            .field("cnt_pause_u3", &self.cnt_pause_u3())
+            .field("cnt_pause_u4", &self.cnt_pause_u4())
+            .field("cnt_pause_u5", &self.cnt_pause_u5())
+            .field("cnt_pause_u6", &self.cnt_pause_u6())
+            .field("cnt_pause_u7", &self.cnt_pause_u7())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Set this bit to clear unit(0-7)'s counter."]
     #[doc = ""]
diff --git a/esp32/src/pcnt/date.rs b/esp32/src/pcnt/date.rs
index 4c01e9d1e1..93cf4ff562 100644
--- a/esp32/src/pcnt/date.rs
+++ b/esp32/src/pcnt/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/pcnt/int_ena.rs b/esp32/src/pcnt/int_ena.rs
index bcf4842ecb..7132f6312c 100644
--- a/esp32/src/pcnt/int_ena.rs
+++ b/esp32/src/pcnt/int_ena.rs
@@ -67,47 +67,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
-            .field(
-                "cnt_thr_event_u4",
-                &format_args!("{}", self.cnt_thr_event_u4().bit()),
-            )
-            .field(
-                "cnt_thr_event_u5",
-                &format_args!("{}", self.cnt_thr_event_u5().bit()),
-            )
-            .field(
-                "cnt_thr_event_u6",
-                &format_args!("{}", self.cnt_thr_event_u6().bit()),
-            )
-            .field(
-                "cnt_thr_event_u7",
-                &format_args!("{}", self.cnt_thr_event_u7().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
+            .field("cnt_thr_event_u4", &self.cnt_thr_event_u4())
+            .field("cnt_thr_event_u5", &self.cnt_thr_event_u5())
+            .field("cnt_thr_event_u6", &self.cnt_thr_event_u6())
+            .field("cnt_thr_event_u7", &self.cnt_thr_event_u7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "This is the interrupt enable bit for channel(0-7) event."]
     #[doc = ""]
diff --git a/esp32/src/pcnt/int_raw.rs b/esp32/src/pcnt/int_raw.rs
index 1e34809bfd..3a167c24f6 100644
--- a/esp32/src/pcnt/int_raw.rs
+++ b/esp32/src/pcnt/int_raw.rs
@@ -63,47 +63,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
-            .field(
-                "cnt_thr_event_u4",
-                &format_args!("{}", self.cnt_thr_event_u4().bit()),
-            )
-            .field(
-                "cnt_thr_event_u5",
-                &format_args!("{}", self.cnt_thr_event_u5().bit()),
-            )
-            .field(
-                "cnt_thr_event_u6",
-                &format_args!("{}", self.cnt_thr_event_u6().bit()),
-            )
-            .field(
-                "cnt_thr_event_u7",
-                &format_args!("{}", self.cnt_thr_event_u7().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
+            .field("cnt_thr_event_u4", &self.cnt_thr_event_u4())
+            .field("cnt_thr_event_u5", &self.cnt_thr_event_u5())
+            .field("cnt_thr_event_u6", &self.cnt_thr_event_u6())
+            .field("cnt_thr_event_u7", &self.cnt_thr_event_u7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32/src/pcnt/int_st.rs b/esp32/src/pcnt/int_st.rs
index 6c87497fd8..0824cd4011 100644
--- a/esp32/src/pcnt/int_st.rs
+++ b/esp32/src/pcnt/int_st.rs
@@ -63,47 +63,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
-            .field(
-                "cnt_thr_event_u4",
-                &format_args!("{}", self.cnt_thr_event_u4().bit()),
-            )
-            .field(
-                "cnt_thr_event_u5",
-                &format_args!("{}", self.cnt_thr_event_u5().bit()),
-            )
-            .field(
-                "cnt_thr_event_u6",
-                &format_args!("{}", self.cnt_thr_event_u6().bit()),
-            )
-            .field(
-                "cnt_thr_event_u7",
-                &format_args!("{}", self.cnt_thr_event_u7().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
+            .field("cnt_thr_event_u4", &self.cnt_thr_event_u4())
+            .field("cnt_thr_event_u5", &self.cnt_thr_event_u5())
+            .field("cnt_thr_event_u6", &self.cnt_thr_event_u6())
+            .field("cnt_thr_event_u7", &self.cnt_thr_event_u7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32/src/pcnt/u_cnt.rs b/esp32/src/pcnt/u_cnt.rs
index 7db383a672..191fe0fe70 100644
--- a/esp32/src/pcnt/u_cnt.rs
+++ b/esp32/src/pcnt/u_cnt.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("U_CNT")
-            .field("cnt", &format_args!("{}", self.cnt().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("U_CNT").field("cnt", &self.cnt()).finish()
     }
 }
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/pcnt/u_status.rs b/esp32/src/pcnt/u_status.rs
index 79a71ef882..78fec621d8 100644
--- a/esp32/src/pcnt/u_status.rs
+++ b/esp32/src/pcnt/u_status.rs
@@ -69,25 +69,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("U_STATUS")
-            .field(
-                "core_status",
-                &format_args!("{}", self.core_status().bits()),
-            )
-            .field("zero_mode", &format_args!("{}", self.zero_mode().bits()))
-            .field("thres1", &format_args!("{}", self.thres1().bit()))
-            .field("thres0", &format_args!("{}", self.thres0().bit()))
-            .field("l_lim", &format_args!("{}", self.l_lim().bit()))
-            .field("h_lim", &format_args!("{}", self.h_lim().bit()))
-            .field("zero", &format_args!("{}", self.zero().bit()))
+            .field("core_status", &self.core_status())
+            .field("zero_mode", &self.zero_mode())
+            .field("thres1", &self.thres1())
+            .field("thres0", &self.thres0())
+            .field("l_lim", &self.l_lim())
+            .field("h_lim", &self.h_lim())
+            .field("zero", &self.zero())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32/src/pcnt/unit/conf0.rs b/esp32/src/pcnt/unit/conf0.rs
index 8132bbe6bd..b7b230f6df 100644
--- a/esp32/src/pcnt/unit/conf0.rs
+++ b/esp32/src/pcnt/unit/conf0.rs
@@ -325,69 +325,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field(
-                "filter_thres",
-                &format_args!("{}", self.filter_thres().bits()),
-            )
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
-            .field("thr_zero_en", &format_args!("{}", self.thr_zero_en().bit()))
-            .field(
-                "thr_h_lim_en",
-                &format_args!("{}", self.thr_h_lim_en().bit()),
-            )
-            .field(
-                "thr_l_lim_en",
-                &format_args!("{}", self.thr_l_lim_en().bit()),
-            )
-            .field(
-                "thr_thres0_en",
-                &format_args!("{}", self.thr_thres0_en().bit()),
-            )
-            .field(
-                "thr_thres1_en",
-                &format_args!("{}", self.thr_thres1_en().bit()),
-            )
-            .field(
-                "ch0_neg_mode",
-                &format_args!("{}", self.ch0_neg_mode().bits()),
-            )
-            .field(
-                "ch1_neg_mode",
-                &format_args!("{}", self.ch1_neg_mode().bits()),
-            )
-            .field(
-                "ch0_pos_mode",
-                &format_args!("{}", self.ch0_pos_mode().bits()),
-            )
-            .field(
-                "ch1_pos_mode",
-                &format_args!("{}", self.ch1_pos_mode().bits()),
-            )
-            .field(
-                "ch0_hctrl_mode",
-                &format_args!("{}", self.ch0_hctrl_mode().bits()),
-            )
-            .field(
-                "ch1_hctrl_mode",
-                &format_args!("{}", self.ch1_hctrl_mode().bits()),
-            )
-            .field(
-                "ch0_lctrl_mode",
-                &format_args!("{}", self.ch0_lctrl_mode().bits()),
-            )
-            .field(
-                "ch1_lctrl_mode",
-                &format_args!("{}", self.ch1_lctrl_mode().bits()),
-            )
+            .field("filter_thres", &self.filter_thres())
+            .field("filter_en", &self.filter_en())
+            .field("thr_zero_en", &self.thr_zero_en())
+            .field("thr_h_lim_en", &self.thr_h_lim_en())
+            .field("thr_l_lim_en", &self.thr_l_lim_en())
+            .field("thr_thres0_en", &self.thr_thres0_en())
+            .field("thr_thres1_en", &self.thr_thres1_en())
+            .field("ch0_neg_mode", &self.ch0_neg_mode())
+            .field("ch1_neg_mode", &self.ch1_neg_mode())
+            .field("ch0_pos_mode", &self.ch0_pos_mode())
+            .field("ch1_pos_mode", &self.ch1_pos_mode())
+            .field("ch0_hctrl_mode", &self.ch0_hctrl_mode())
+            .field("ch1_hctrl_mode", &self.ch1_hctrl_mode())
+            .field("ch0_lctrl_mode", &self.ch0_lctrl_mode())
+            .field("ch1_lctrl_mode", &self.ch1_lctrl_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register is used to filter pluse whose width is smaller than this value for unit0."]
     #[inline(always)]
diff --git a/esp32/src/pcnt/unit/conf1.rs b/esp32/src/pcnt/unit/conf1.rs
index ae8abd7a97..366234acd2 100644
--- a/esp32/src/pcnt/unit/conf1.rs
+++ b/esp32/src/pcnt/unit/conf1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field("cnt_thres0", &format_args!("{}", self.cnt_thres0().bits()))
-            .field("cnt_thres1", &format_args!("{}", self.cnt_thres1().bits()))
+            .field("cnt_thres0", &self.cnt_thres0())
+            .field("cnt_thres1", &self.cnt_thres1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure thres0 value for unit0."]
     #[inline(always)]
diff --git a/esp32/src/pcnt/unit/conf2.rs b/esp32/src/pcnt/unit/conf2.rs
index 9a70874f43..e65ce2e06b 100644
--- a/esp32/src/pcnt/unit/conf2.rs
+++ b/esp32/src/pcnt/unit/conf2.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF2")
-            .field("cnt_h_lim", &format_args!("{}", self.cnt_h_lim().bits()))
-            .field("cnt_l_lim", &format_args!("{}", self.cnt_l_lim().bits()))
+            .field("cnt_h_lim", &self.cnt_h_lim())
+            .field("cnt_l_lim", &self.cnt_l_lim())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure thr_h_lim value for unit0."]
     #[inline(always)]
diff --git a/esp32/src/rmt/apb_conf.rs b/esp32/src/rmt/apb_conf.rs
index bb76bf0cd5..9a3c53c98d 100644
--- a/esp32/src/rmt/apb_conf.rs
+++ b/esp32/src/rmt/apb_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_CONF")
-            .field(
-                "apb_fifo_mask",
-                &format_args!("{}", self.apb_fifo_mask().bit()),
-            )
-            .field(
-                "mem_tx_wrap_en",
-                &format_args!("{}", self.mem_tx_wrap_en().bit()),
-            )
+            .field("apb_fifo_mask", &self.apb_fifo_mask())
+            .field("mem_tx_wrap_en", &self.mem_tx_wrap_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to disable apb fifo access"]
     #[inline(always)]
diff --git a/esp32/src/rmt/ch_tx_lim.rs b/esp32/src/rmt/ch_tx_lim.rs
index 8a8f956341..088d42e8ab 100644
--- a/esp32/src/rmt/ch_tx_lim.rs
+++ b/esp32/src/rmt/ch_tx_lim.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_TX_LIM")
-            .field("tx_lim", &format_args!("{}", self.tx_lim().bits()))
+            .field("tx_lim", &self.tx_lim())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_TX_LIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0 produce the relative interrupt."]
     #[inline(always)]
diff --git a/esp32/src/rmt/chaddr.rs b/esp32/src/rmt/chaddr.rs
index 91c4e72f4d..8711765e4e 100644
--- a/esp32/src/rmt/chaddr.rs
+++ b/esp32/src/rmt/chaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHADDR")
-            .field(
-                "apb_mem_addr",
-                &format_args!("{}", self.apb_mem_addr().bits()),
-            )
+            .field("apb_mem_addr", &self.apb_mem_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CHADDR_SPEC;
 impl crate::RegisterSpec for CHADDR_SPEC {
diff --git a/esp32/src/rmt/chcarrier_duty.rs b/esp32/src/rmt/chcarrier_duty.rs
index d3893f1b52..cbb069b07c 100644
--- a/esp32/src/rmt/chcarrier_duty.rs
+++ b/esp32/src/rmt/chcarrier_duty.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHCARRIER_DUTY")
-            .field(
-                "carrier_low",
-                &format_args!("{}", self.carrier_low().bits()),
-            )
-            .field(
-                "carrier_high",
-                &format_args!("{}", self.carrier_high().bits()),
-            )
+            .field("carrier_low", &self.carrier_low())
+            .field("carrier_high", &self.carrier_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHCARRIER_DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure carrier wave's low level value for channel0."]
     #[inline(always)]
diff --git a/esp32/src/rmt/chconf0.rs b/esp32/src/rmt/chconf0.rs
index f7ddcadfb5..b83ba2b8f1 100644
--- a/esp32/src/rmt/chconf0.rs
+++ b/esp32/src/rmt/chconf0.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHCONF0")
-            .field("div_cnt", &format_args!("{}", self.div_cnt().bits()))
-            .field("idle_thres", &format_args!("{}", self.idle_thres().bits()))
-            .field("mem_size", &format_args!("{}", self.mem_size().bits()))
-            .field("carrier_en", &format_args!("{}", self.carrier_en().bit()))
-            .field(
-                "carrier_out_lv",
-                &format_args!("{}", self.carrier_out_lv().bit()),
-            )
-            .field("mem_pd", &format_args!("{}", self.mem_pd().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("div_cnt", &self.div_cnt())
+            .field("idle_thres", &self.idle_thres())
+            .field("mem_size", &self.mem_size())
+            .field("carrier_en", &self.carrier_en())
+            .field("carrier_out_lv", &self.carrier_out_lv())
+            .field("mem_pd", &self.mem_pd())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHCONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the frequency divider's factor in channel0."]
     #[inline(always)]
diff --git a/esp32/src/rmt/chconf1.rs b/esp32/src/rmt/chconf1.rs
index 738841c22f..aaed094506 100644
--- a/esp32/src/rmt/chconf1.rs
+++ b/esp32/src/rmt/chconf1.rs
@@ -125,40 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHCONF1")
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_en", &format_args!("{}", self.rx_en().bit()))
-            .field("mem_wr_rst", &format_args!("{}", self.mem_wr_rst().bit()))
-            .field("mem_rd_rst", &format_args!("{}", self.mem_rd_rst().bit()))
-            .field("apb_mem_rst", &format_args!("{}", self.apb_mem_rst().bit()))
-            .field("mem_owner", &format_args!("{}", self.mem_owner().bit()))
-            .field(
-                "tx_conti_mode",
-                &format_args!("{}", self.tx_conti_mode().bit()),
-            )
-            .field(
-                "rx_filter_en",
-                &format_args!("{}", self.rx_filter_en().bit()),
-            )
-            .field(
-                "rx_filter_thres",
-                &format_args!("{}", self.rx_filter_thres().bits()),
-            )
-            .field("ref_cnt_rst", &format_args!("{}", self.ref_cnt_rst().bit()))
-            .field(
-                "ref_always_on",
-                &format_args!("{}", self.ref_always_on().bit()),
-            )
-            .field("idle_out_lv", &format_args!("{}", self.idle_out_lv().bit()))
-            .field("idle_out_en", &format_args!("{}", self.idle_out_en().bit()))
+            .field("tx_start", &self.tx_start())
+            .field("rx_en", &self.rx_en())
+            .field("mem_wr_rst", &self.mem_wr_rst())
+            .field("mem_rd_rst", &self.mem_rd_rst())
+            .field("apb_mem_rst", &self.apb_mem_rst())
+            .field("mem_owner", &self.mem_owner())
+            .field("tx_conti_mode", &self.tx_conti_mode())
+            .field("rx_filter_en", &self.rx_filter_en())
+            .field("rx_filter_thres", &self.rx_filter_thres())
+            .field("ref_cnt_rst", &self.ref_cnt_rst())
+            .field("ref_always_on", &self.ref_always_on())
+            .field("idle_out_lv", &self.idle_out_lv())
+            .field("idle_out_en", &self.idle_out_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHCONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to start sending data for channel0."]
     #[inline(always)]
diff --git a/esp32/src/rmt/chdata.rs b/esp32/src/rmt/chdata.rs
index 4d86cc8d27..20e80cb4d1 100644
--- a/esp32/src/rmt/chdata.rs
+++ b/esp32/src/rmt/chdata.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chdata::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chdata::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CHDATA_SPEC;
diff --git a/esp32/src/rmt/chstatus.rs b/esp32/src/rmt/chstatus.rs
index 8260fdebcf..cd09cb6689 100644
--- a/esp32/src/rmt/chstatus.rs
+++ b/esp32/src/rmt/chstatus.rs
@@ -69,39 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHSTATUS")
-            .field("status", &format_args!("{}", self.status().bits()))
-            .field(
-                "mem_waddr_ex",
-                &format_args!("{}", self.mem_waddr_ex().bits()),
-            )
-            .field(
-                "mem_raddr_ex",
-                &format_args!("{}", self.mem_raddr_ex().bits()),
-            )
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field(
-                "mem_owner_err",
-                &format_args!("{}", self.mem_owner_err().bit()),
-            )
-            .field("mem_full", &format_args!("{}", self.mem_full().bit()))
-            .field("mem_empty", &format_args!("{}", self.mem_empty().bit()))
-            .field(
-                "apb_mem_wr_err",
-                &format_args!("{}", self.apb_mem_wr_err().bit()),
-            )
-            .field(
-                "apb_mem_rd_err",
-                &format_args!("{}", self.apb_mem_rd_err().bit()),
-            )
+            .field("status", &self.status())
+            .field("mem_waddr_ex", &self.mem_waddr_ex())
+            .field("mem_raddr_ex", &self.mem_raddr_ex())
+            .field("state", &self.state())
+            .field("mem_owner_err", &self.mem_owner_err())
+            .field("mem_full", &self.mem_full())
+            .field("mem_empty", &self.mem_empty())
+            .field("apb_mem_wr_err", &self.apb_mem_wr_err())
+            .field("apb_mem_rd_err", &self.apb_mem_rd_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHSTATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chstatus::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CHSTATUS_SPEC;
 impl crate::RegisterSpec for CHSTATUS_SPEC {
diff --git a/esp32/src/rmt/date.rs b/esp32/src/rmt/date.rs
index e36070b4a5..ef5e9561a0 100644
--- a/esp32/src/rmt/date.rs
+++ b/esp32/src/rmt/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/rmt/int_ena.rs b/esp32/src/rmt/int_ena.rs
index 448c9b1c99..91af44caf5 100644
--- a/esp32/src/rmt/int_ena.rs
+++ b/esp32/src/rmt/int_ena.rs
@@ -244,71 +244,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_tx_end", &format_args!("{}", self.ch2_tx_end().bit()))
-            .field("ch3_tx_end", &format_args!("{}", self.ch3_tx_end().bit()))
-            .field("ch4_tx_end", &format_args!("{}", self.ch4_tx_end().bit()))
-            .field("ch5_tx_end", &format_args!("{}", self.ch5_tx_end().bit()))
-            .field("ch6_tx_end", &format_args!("{}", self.ch6_tx_end().bit()))
-            .field("ch7_tx_end", &format_args!("{}", self.ch7_tx_end().bit()))
-            .field("ch0_rx_end", &format_args!("{}", self.ch0_rx_end().bit()))
-            .field("ch1_rx_end", &format_args!("{}", self.ch1_rx_end().bit()))
-            .field("ch2_rx_end", &format_args!("{}", self.ch2_rx_end().bit()))
-            .field("ch3_rx_end", &format_args!("{}", self.ch3_rx_end().bit()))
-            .field("ch4_rx_end", &format_args!("{}", self.ch4_rx_end().bit()))
-            .field("ch5_rx_end", &format_args!("{}", self.ch5_rx_end().bit()))
-            .field("ch6_rx_end", &format_args!("{}", self.ch6_rx_end().bit()))
-            .field("ch7_rx_end", &format_args!("{}", self.ch7_rx_end().bit()))
-            .field("ch0_err", &format_args!("{}", self.ch0_err().bit()))
-            .field("ch1_err", &format_args!("{}", self.ch1_err().bit()))
-            .field("ch2_err", &format_args!("{}", self.ch2_err().bit()))
-            .field("ch3_err", &format_args!("{}", self.ch3_err().bit()))
-            .field("ch4_err", &format_args!("{}", self.ch4_err().bit()))
-            .field("ch5_err", &format_args!("{}", self.ch5_err().bit()))
-            .field("ch6_err", &format_args!("{}", self.ch6_err().bit()))
-            .field("ch7_err", &format_args!("{}", self.ch7_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_tx_thr_event",
-                &format_args!("{}", self.ch2_tx_thr_event().bit()),
-            )
-            .field(
-                "ch3_tx_thr_event",
-                &format_args!("{}", self.ch3_tx_thr_event().bit()),
-            )
-            .field(
-                "ch4_tx_thr_event",
-                &format_args!("{}", self.ch4_tx_thr_event().bit()),
-            )
-            .field(
-                "ch5_tx_thr_event",
-                &format_args!("{}", self.ch5_tx_thr_event().bit()),
-            )
-            .field(
-                "ch6_tx_thr_event",
-                &format_args!("{}", self.ch6_tx_thr_event().bit()),
-            )
-            .field(
-                "ch7_tx_thr_event",
-                &format_args!("{}", self.ch7_tx_thr_event().bit()),
-            )
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_tx_end", &self.ch2_tx_end())
+            .field("ch3_tx_end", &self.ch3_tx_end())
+            .field("ch4_tx_end", &self.ch4_tx_end())
+            .field("ch5_tx_end", &self.ch5_tx_end())
+            .field("ch6_tx_end", &self.ch6_tx_end())
+            .field("ch7_tx_end", &self.ch7_tx_end())
+            .field("ch0_rx_end", &self.ch0_rx_end())
+            .field("ch1_rx_end", &self.ch1_rx_end())
+            .field("ch2_rx_end", &self.ch2_rx_end())
+            .field("ch3_rx_end", &self.ch3_rx_end())
+            .field("ch4_rx_end", &self.ch4_rx_end())
+            .field("ch5_rx_end", &self.ch5_rx_end())
+            .field("ch6_rx_end", &self.ch6_rx_end())
+            .field("ch7_rx_end", &self.ch7_rx_end())
+            .field("ch0_err", &self.ch0_err())
+            .field("ch1_err", &self.ch1_err())
+            .field("ch2_err", &self.ch2_err())
+            .field("ch3_err", &self.ch3_err())
+            .field("ch4_err", &self.ch4_err())
+            .field("ch5_err", &self.ch5_err())
+            .field("ch6_err", &self.ch6_err())
+            .field("ch7_err", &self.ch7_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_tx_thr_event", &self.ch2_tx_thr_event())
+            .field("ch3_tx_thr_event", &self.ch3_tx_thr_event())
+            .field("ch4_tx_thr_event", &self.ch4_tx_thr_event())
+            .field("ch5_tx_thr_event", &self.ch5_tx_thr_event())
+            .field("ch6_tx_thr_event", &self.ch6_tx_thr_event())
+            .field("ch7_tx_thr_event", &self.ch7_tx_thr_event())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Set this bit to enable rmt_ch(0-7)_tx_end_int_st."]
     #[doc = ""]
diff --git a/esp32/src/rmt/int_raw.rs b/esp32/src/rmt/int_raw.rs
index 8c5428e03c..d511032076 100644
--- a/esp32/src/rmt/int_raw.rs
+++ b/esp32/src/rmt/int_raw.rs
@@ -234,71 +234,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_tx_end", &format_args!("{}", self.ch2_tx_end().bit()))
-            .field("ch3_tx_end", &format_args!("{}", self.ch3_tx_end().bit()))
-            .field("ch4_tx_end", &format_args!("{}", self.ch4_tx_end().bit()))
-            .field("ch5_tx_end", &format_args!("{}", self.ch5_tx_end().bit()))
-            .field("ch6_tx_end", &format_args!("{}", self.ch6_tx_end().bit()))
-            .field("ch7_tx_end", &format_args!("{}", self.ch7_tx_end().bit()))
-            .field("ch0_rx_end", &format_args!("{}", self.ch0_rx_end().bit()))
-            .field("ch1_rx_end", &format_args!("{}", self.ch1_rx_end().bit()))
-            .field("ch2_rx_end", &format_args!("{}", self.ch2_rx_end().bit()))
-            .field("ch3_rx_end", &format_args!("{}", self.ch3_rx_end().bit()))
-            .field("ch4_rx_end", &format_args!("{}", self.ch4_rx_end().bit()))
-            .field("ch5_rx_end", &format_args!("{}", self.ch5_rx_end().bit()))
-            .field("ch6_rx_end", &format_args!("{}", self.ch6_rx_end().bit()))
-            .field("ch7_rx_end", &format_args!("{}", self.ch7_rx_end().bit()))
-            .field("ch0_err", &format_args!("{}", self.ch0_err().bit()))
-            .field("ch1_err", &format_args!("{}", self.ch1_err().bit()))
-            .field("ch2_err", &format_args!("{}", self.ch2_err().bit()))
-            .field("ch3_err", &format_args!("{}", self.ch3_err().bit()))
-            .field("ch4_err", &format_args!("{}", self.ch4_err().bit()))
-            .field("ch5_err", &format_args!("{}", self.ch5_err().bit()))
-            .field("ch6_err", &format_args!("{}", self.ch6_err().bit()))
-            .field("ch7_err", &format_args!("{}", self.ch7_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_tx_thr_event",
-                &format_args!("{}", self.ch2_tx_thr_event().bit()),
-            )
-            .field(
-                "ch3_tx_thr_event",
-                &format_args!("{}", self.ch3_tx_thr_event().bit()),
-            )
-            .field(
-                "ch4_tx_thr_event",
-                &format_args!("{}", self.ch4_tx_thr_event().bit()),
-            )
-            .field(
-                "ch5_tx_thr_event",
-                &format_args!("{}", self.ch5_tx_thr_event().bit()),
-            )
-            .field(
-                "ch6_tx_thr_event",
-                &format_args!("{}", self.ch6_tx_thr_event().bit()),
-            )
-            .field(
-                "ch7_tx_thr_event",
-                &format_args!("{}", self.ch7_tx_thr_event().bit()),
-            )
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_tx_end", &self.ch2_tx_end())
+            .field("ch3_tx_end", &self.ch3_tx_end())
+            .field("ch4_tx_end", &self.ch4_tx_end())
+            .field("ch5_tx_end", &self.ch5_tx_end())
+            .field("ch6_tx_end", &self.ch6_tx_end())
+            .field("ch7_tx_end", &self.ch7_tx_end())
+            .field("ch0_rx_end", &self.ch0_rx_end())
+            .field("ch1_rx_end", &self.ch1_rx_end())
+            .field("ch2_rx_end", &self.ch2_rx_end())
+            .field("ch3_rx_end", &self.ch3_rx_end())
+            .field("ch4_rx_end", &self.ch4_rx_end())
+            .field("ch5_rx_end", &self.ch5_rx_end())
+            .field("ch6_rx_end", &self.ch6_rx_end())
+            .field("ch7_rx_end", &self.ch7_rx_end())
+            .field("ch0_err", &self.ch0_err())
+            .field("ch1_err", &self.ch1_err())
+            .field("ch2_err", &self.ch2_err())
+            .field("ch3_err", &self.ch3_err())
+            .field("ch4_err", &self.ch4_err())
+            .field("ch5_err", &self.ch5_err())
+            .field("ch6_err", &self.ch6_err())
+            .field("ch7_err", &self.ch7_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_tx_thr_event", &self.ch2_tx_thr_event())
+            .field("ch3_tx_thr_event", &self.ch3_tx_thr_event())
+            .field("ch4_tx_thr_event", &self.ch4_tx_thr_event())
+            .field("ch5_tx_thr_event", &self.ch5_tx_thr_event())
+            .field("ch6_tx_thr_event", &self.ch6_tx_thr_event())
+            .field("ch7_tx_thr_event", &self.ch7_tx_thr_event())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32/src/rmt/int_st.rs b/esp32/src/rmt/int_st.rs
index 51938e3044..615c8b9b6f 100644
--- a/esp32/src/rmt/int_st.rs
+++ b/esp32/src/rmt/int_st.rs
@@ -234,71 +234,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_tx_end", &format_args!("{}", self.ch2_tx_end().bit()))
-            .field("ch3_tx_end", &format_args!("{}", self.ch3_tx_end().bit()))
-            .field("ch4_tx_end", &format_args!("{}", self.ch4_tx_end().bit()))
-            .field("ch5_tx_end", &format_args!("{}", self.ch5_tx_end().bit()))
-            .field("ch6_tx_end", &format_args!("{}", self.ch6_tx_end().bit()))
-            .field("ch7_tx_end", &format_args!("{}", self.ch7_tx_end().bit()))
-            .field("ch0_rx_end", &format_args!("{}", self.ch0_rx_end().bit()))
-            .field("ch1_rx_end", &format_args!("{}", self.ch1_rx_end().bit()))
-            .field("ch2_rx_end", &format_args!("{}", self.ch2_rx_end().bit()))
-            .field("ch3_rx_end", &format_args!("{}", self.ch3_rx_end().bit()))
-            .field("ch4_rx_end", &format_args!("{}", self.ch4_rx_end().bit()))
-            .field("ch5_rx_end", &format_args!("{}", self.ch5_rx_end().bit()))
-            .field("ch6_rx_end", &format_args!("{}", self.ch6_rx_end().bit()))
-            .field("ch7_rx_end", &format_args!("{}", self.ch7_rx_end().bit()))
-            .field("ch0_err", &format_args!("{}", self.ch0_err().bit()))
-            .field("ch1_err", &format_args!("{}", self.ch1_err().bit()))
-            .field("ch2_err", &format_args!("{}", self.ch2_err().bit()))
-            .field("ch3_err", &format_args!("{}", self.ch3_err().bit()))
-            .field("ch4_err", &format_args!("{}", self.ch4_err().bit()))
-            .field("ch5_err", &format_args!("{}", self.ch5_err().bit()))
-            .field("ch6_err", &format_args!("{}", self.ch6_err().bit()))
-            .field("ch7_err", &format_args!("{}", self.ch7_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_tx_thr_event",
-                &format_args!("{}", self.ch2_tx_thr_event().bit()),
-            )
-            .field(
-                "ch3_tx_thr_event",
-                &format_args!("{}", self.ch3_tx_thr_event().bit()),
-            )
-            .field(
-                "ch4_tx_thr_event",
-                &format_args!("{}", self.ch4_tx_thr_event().bit()),
-            )
-            .field(
-                "ch5_tx_thr_event",
-                &format_args!("{}", self.ch5_tx_thr_event().bit()),
-            )
-            .field(
-                "ch6_tx_thr_event",
-                &format_args!("{}", self.ch6_tx_thr_event().bit()),
-            )
-            .field(
-                "ch7_tx_thr_event",
-                &format_args!("{}", self.ch7_tx_thr_event().bit()),
-            )
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_tx_end", &self.ch2_tx_end())
+            .field("ch3_tx_end", &self.ch3_tx_end())
+            .field("ch4_tx_end", &self.ch4_tx_end())
+            .field("ch5_tx_end", &self.ch5_tx_end())
+            .field("ch6_tx_end", &self.ch6_tx_end())
+            .field("ch7_tx_end", &self.ch7_tx_end())
+            .field("ch0_rx_end", &self.ch0_rx_end())
+            .field("ch1_rx_end", &self.ch1_rx_end())
+            .field("ch2_rx_end", &self.ch2_rx_end())
+            .field("ch3_rx_end", &self.ch3_rx_end())
+            .field("ch4_rx_end", &self.ch4_rx_end())
+            .field("ch5_rx_end", &self.ch5_rx_end())
+            .field("ch6_rx_end", &self.ch6_rx_end())
+            .field("ch7_rx_end", &self.ch7_rx_end())
+            .field("ch0_err", &self.ch0_err())
+            .field("ch1_err", &self.ch1_err())
+            .field("ch2_err", &self.ch2_err())
+            .field("ch3_err", &self.ch3_err())
+            .field("ch4_err", &self.ch4_err())
+            .field("ch5_err", &self.ch5_err())
+            .field("ch6_err", &self.ch6_err())
+            .field("ch7_err", &self.ch7_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_tx_thr_event", &self.ch2_tx_thr_event())
+            .field("ch3_tx_thr_event", &self.ch3_tx_thr_event())
+            .field("ch4_tx_thr_event", &self.ch4_tx_thr_event())
+            .field("ch5_tx_thr_event", &self.ch5_tx_thr_event())
+            .field("ch6_tx_thr_event", &self.ch6_tx_thr_event())
+            .field("ch7_tx_thr_event", &self.ch7_tx_thr_event())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32/src/rng/data.rs b/esp32/src/rng/data.rs
index 016046274d..4d812a63aa 100644
--- a/esp32/src/rng/data.rs
+++ b/esp32/src/rng/data.rs
@@ -6,12 +6,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Random number data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DATA_SPEC;
 impl crate::RegisterSpec for DATA_SPEC {
diff --git a/esp32/src/rsa/clean.rs b/esp32/src/rsa/clean.rs
index 85764d7a97..6cd4f9e138 100644
--- a/esp32/src/rsa/clean.rs
+++ b/esp32/src/rsa/clean.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLEAN")
-            .field("clean", &format_args!("{}", self.clean().bit()))
+            .field("clean", &self.clean())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLEAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clean::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLEAN_SPEC;
 impl crate::RegisterSpec for CLEAN_SPEC {
diff --git a/esp32/src/rsa/interrupt.rs b/esp32/src/rsa/interrupt.rs
index a6df50e7f1..3bf5bda4a9 100644
--- a/esp32/src/rsa/interrupt.rs
+++ b/esp32/src/rsa/interrupt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT")
-            .field("interrupt", &format_args!("{}", self.interrupt().bit()))
+            .field("interrupt", &self.interrupt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - RSA interrupt status register. Will read 1 once an operation has completed."]
     #[inline(always)]
diff --git a/esp32/src/rsa/m_mem.rs b/esp32/src/rsa/m_mem.rs
index f889cb91cf..cdddfe42b8 100644
--- a/esp32/src/rsa/m_mem.rs
+++ b/esp32/src/rsa/m_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Represents M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct M_MEM_SPEC;
diff --git a/esp32/src/rsa/m_prime.rs b/esp32/src/rsa/m_prime.rs
index 327035d966..14d2c244cf 100644
--- a/esp32/src/rsa/m_prime.rs
+++ b/esp32/src/rsa/m_prime.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("M_PRIME")
-            .field("m_prime", &format_args!("{}", self.m_prime().bits()))
+            .field("m_prime", &self.m_prime())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_PRIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register contains M’."]
     #[inline(always)]
diff --git a/esp32/src/rsa/modexp_mode.rs b/esp32/src/rsa/modexp_mode.rs
index 4c166a7a14..3fe76588de 100644
--- a/esp32/src/rsa/modexp_mode.rs
+++ b/esp32/src/rsa/modexp_mode.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODEXP_MODE")
-            .field(
-                "modexp_mode",
-                &format_args!("{}", self.modexp_mode().bits()),
-            )
+            .field("modexp_mode", &self.modexp_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODEXP_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - This register contains the mode of modular exponentiation."]
     #[inline(always)]
diff --git a/esp32/src/rsa/mult_mode.rs b/esp32/src/rsa/mult_mode.rs
index f63494feef..846946a0d0 100644
--- a/esp32/src/rsa/mult_mode.rs
+++ b/esp32/src/rsa/mult_mode.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_MODE")
-            .field("mult_mode", &format_args!("{}", self.mult_mode().bits()))
+            .field("mult_mode", &self.mult_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - This register contains the mode of modular multiplication and multiplication."]
     #[inline(always)]
diff --git a/esp32/src/rsa/x_mem.rs b/esp32/src/rsa/x_mem.rs
index edcf1cf0c4..122f41e2e1 100644
--- a/esp32/src/rsa/x_mem.rs
+++ b/esp32/src/rsa/x_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<X_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Represents X\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`x_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`x_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct X_MEM_SPEC;
diff --git a/esp32/src/rsa/y_mem.rs b/esp32/src/rsa/y_mem.rs
index c687cd0a52..fe33d71507 100644
--- a/esp32/src/rsa/y_mem.rs
+++ b/esp32/src/rsa/y_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Y_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Represents Y\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Y_MEM_SPEC;
diff --git a/esp32/src/rsa/z_mem.rs b/esp32/src/rsa/z_mem.rs
index 6826e9d664..5bee6c1785 100644
--- a/esp32/src/rsa/z_mem.rs
+++ b/esp32/src/rsa/z_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Z_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Represents Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Z_MEM_SPEC;
diff --git a/esp32/src/rtc_cntl/ana_conf.rs b/esp32/src/rtc_cntl/ana_conf.rs
index e1483f59a2..e0e8784aac 100644
--- a/esp32/src/rtc_cntl/ana_conf.rs
+++ b/esp32/src/rtc_cntl/ana_conf.rs
@@ -80,38 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ANA_CONF")
-            .field(
-                "plla_force_pd",
-                &format_args!("{}", self.plla_force_pd().bit()),
-            )
-            .field(
-                "plla_force_pu",
-                &format_args!("{}", self.plla_force_pu().bit()),
-            )
-            .field(
-                "bbpll_cal_slp_start",
-                &format_args!("{}", self.bbpll_cal_slp_start().bit()),
-            )
-            .field("pvtmon_pu", &format_args!("{}", self.pvtmon_pu().bit()))
-            .field("txrf_i2c_pu", &format_args!("{}", self.txrf_i2c_pu().bit()))
-            .field(
-                "rfrx_pbus_pu",
-                &format_args!("{}", self.rfrx_pbus_pu().bit()),
-            )
-            .field(
-                "ckgen_i2c_pu",
-                &format_args!("{}", self.ckgen_i2c_pu().bit()),
-            )
-            .field("pll_i2c_pu", &format_args!("{}", self.pll_i2c_pu().bit()))
+            .field("plla_force_pd", &self.plla_force_pd())
+            .field("plla_force_pu", &self.plla_force_pu())
+            .field("bbpll_cal_slp_start", &self.bbpll_cal_slp_start())
+            .field("pvtmon_pu", &self.pvtmon_pu())
+            .field("txrf_i2c_pu", &self.txrf_i2c_pu())
+            .field("rfrx_pbus_pu", &self.rfrx_pbus_pu())
+            .field("ckgen_i2c_pu", &self.ckgen_i2c_pu())
+            .field("pll_i2c_pu", &self.pll_i2c_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ANA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 23 - PLLA force power down"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/bias_conf.rs b/esp32/src/rtc_cntl/bias_conf.rs
index 3cdd022543..c24f36a0d4 100644
--- a/esp32/src/rtc_cntl/bias_conf.rs
+++ b/esp32/src/rtc_cntl/bias_conf.rs
@@ -71,40 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BIAS_CONF")
-            .field("dbg_atten", &format_args!("{}", self.dbg_atten().bits()))
-            .field(
-                "enb_sck_xtal",
-                &format_args!("{}", self.enb_sck_xtal().bit()),
-            )
-            .field(
-                "inc_heartbeat_refresh",
-                &format_args!("{}", self.inc_heartbeat_refresh().bit()),
-            )
-            .field(
-                "dec_heartbeat_period",
-                &format_args!("{}", self.dec_heartbeat_period().bit()),
-            )
-            .field(
-                "inc_heartbeat_period",
-                &format_args!("{}", self.inc_heartbeat_period().bit()),
-            )
-            .field(
-                "dec_heartbeat_width",
-                &format_args!("{}", self.dec_heartbeat_width().bit()),
-            )
-            .field(
-                "rst_bias_i2c",
-                &format_args!("{}", self.rst_bias_i2c().bit()),
-            )
+            .field("dbg_atten", &self.dbg_atten())
+            .field("enb_sck_xtal", &self.enb_sck_xtal())
+            .field("inc_heartbeat_refresh", &self.inc_heartbeat_refresh())
+            .field("dec_heartbeat_period", &self.dec_heartbeat_period())
+            .field("inc_heartbeat_period", &self.inc_heartbeat_period())
+            .field("dec_heartbeat_width", &self.dec_heartbeat_width())
+            .field("rst_bias_i2c", &self.rst_bias_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BIAS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 24:25 - DBG_ATTEN"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/brown_out.rs b/esp32/src/rtc_cntl/brown_out.rs
index b025b7a308..43d203fcdf 100644
--- a/esp32/src/rtc_cntl/brown_out.rs
+++ b/esp32/src/rtc_cntl/brown_out.rs
@@ -114,48 +114,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BROWN_OUT")
-            .field(
-                "rtc_mem_pid_conf",
-                &format_args!("{}", self.rtc_mem_pid_conf().bits()),
-            )
-            .field(
-                "rtc_mem_crc_start",
-                &format_args!("{}", self.rtc_mem_crc_start().bit()),
-            )
-            .field(
-                "rtc_mem_crc_addr",
-                &format_args!("{}", self.rtc_mem_crc_addr().bits()),
-            )
-            .field(
-                "close_flash_ena",
-                &format_args!("{}", self.close_flash_ena().bit()),
-            )
-            .field("pd_rf_ena", &format_args!("{}", self.pd_rf_ena().bit()))
-            .field("rst_wait", &format_args!("{}", self.rst_wait().bits()))
-            .field(
-                "rtc_mem_crc_len",
-                &format_args!("{}", self.rtc_mem_crc_len().bits()),
-            )
-            .field("rst_ena", &format_args!("{}", self.rst_ena().bit()))
-            .field(
-                "dbrown_out_thres",
-                &format_args!("{}", self.dbrown_out_thres().bits()),
-            )
-            .field("ena", &format_args!("{}", self.ena().bit()))
-            .field("det", &format_args!("{}", self.det().bit()))
-            .field(
-                "rtc_mem_crc_finish",
-                &format_args!("{}", self.rtc_mem_crc_finish().bit()),
-            )
+            .field("rtc_mem_pid_conf", &self.rtc_mem_pid_conf())
+            .field("rtc_mem_crc_start", &self.rtc_mem_crc_start())
+            .field("rtc_mem_crc_addr", &self.rtc_mem_crc_addr())
+            .field("close_flash_ena", &self.close_flash_ena())
+            .field("pd_rf_ena", &self.pd_rf_ena())
+            .field("rst_wait", &self.rst_wait())
+            .field("rtc_mem_crc_len", &self.rtc_mem_crc_len())
+            .field("rst_ena", &self.rst_ena())
+            .field("dbrown_out_thres", &self.dbrown_out_thres())
+            .field("ena", &self.ena())
+            .field("det", &self.det())
+            .field("rtc_mem_crc_finish", &self.rtc_mem_crc_finish())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BROWN_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/clk_conf.rs b/esp32/src/rtc_cntl/clk_conf.rs
index ed2d1a6fd9..5a96ada0f5 100644
--- a/esp32/src/rtc_cntl/clk_conf.rs
+++ b/esp32/src/rtc_cntl/clk_conf.rs
@@ -488,70 +488,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field("ck8m_div", &format_args!("{}", self.ck8m_div().bits()))
-            .field("enb_ck8m", &format_args!("{}", self.enb_ck8m().bit()))
-            .field(
-                "enb_ck8m_div",
-                &format_args!("{}", self.enb_ck8m_div().bit()),
-            )
-            .field(
-                "dig_xtal32k_en",
-                &format_args!("{}", self.dig_xtal32k_en().bit()),
-            )
-            .field(
-                "dig_clk8m_d256_en",
-                &format_args!("{}", self.dig_clk8m_d256_en().bit()),
-            )
-            .field(
-                "dig_clk8m_en",
-                &format_args!("{}", self.dig_clk8m_en().bit()),
-            )
-            .field(
-                "ck8m_dfreq_force",
-                &format_args!("{}", self.ck8m_dfreq_force().bit()),
-            )
-            .field(
-                "ck8m_div_sel",
-                &format_args!("{}", self.ck8m_div_sel().bits()),
-            )
-            .field(
-                "xtal_force_nogating",
-                &format_args!("{}", self.xtal_force_nogating().bit()),
-            )
-            .field(
-                "ck8m_force_nogating",
-                &format_args!("{}", self.ck8m_force_nogating().bit()),
-            )
-            .field("ck8m_dfreq", &format_args!("{}", self.ck8m_dfreq().bits()))
-            .field(
-                "ck8m_force_pd",
-                &format_args!("{}", self.ck8m_force_pd().bit()),
-            )
-            .field(
-                "ck8m_force_pu",
-                &format_args!("{}", self.ck8m_force_pu().bit()),
-            )
-            .field(
-                "soc_clk_sel",
-                &format_args!("{}", self.soc_clk_sel().bits()),
-            )
-            .field(
-                "fast_clk_rtc_sel",
-                &format_args!("{}", self.fast_clk_rtc_sel().bit()),
-            )
-            .field(
-                "ana_clk_rtc_sel",
-                &format_args!("{}", self.ana_clk_rtc_sel().bits()),
-            )
+            .field("ck8m_div", &self.ck8m_div())
+            .field("enb_ck8m", &self.enb_ck8m())
+            .field("enb_ck8m_div", &self.enb_ck8m_div())
+            .field("dig_xtal32k_en", &self.dig_xtal32k_en())
+            .field("dig_clk8m_d256_en", &self.dig_clk8m_d256_en())
+            .field("dig_clk8m_en", &self.dig_clk8m_en())
+            .field("ck8m_dfreq_force", &self.ck8m_dfreq_force())
+            .field("ck8m_div_sel", &self.ck8m_div_sel())
+            .field("xtal_force_nogating", &self.xtal_force_nogating())
+            .field("ck8m_force_nogating", &self.ck8m_force_nogating())
+            .field("ck8m_dfreq", &self.ck8m_dfreq())
+            .field("ck8m_force_pd", &self.ck8m_force_pd())
+            .field("ck8m_force_pu", &self.ck8m_force_pu())
+            .field("soc_clk_sel", &self.soc_clk_sel())
+            .field("fast_clk_rtc_sel", &self.fast_clk_rtc_sel())
+            .field("ana_clk_rtc_sel", &self.ana_clk_rtc_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 4:5 - CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024."]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/cpu_period_conf.rs b/esp32/src/rtc_cntl/cpu_period_conf.rs
index acdba80d84..ecad77634d 100644
--- a/esp32/src/rtc_cntl/cpu_period_conf.rs
+++ b/esp32/src/rtc_cntl/cpu_period_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERIOD_CONF")
-            .field("cpusel_conf", &format_args!("{}", self.cpusel_conf().bit()))
-            .field(
-                "cpuperiod_sel",
-                &format_args!("{}", self.cpuperiod_sel().bits()),
-            )
+            .field("cpusel_conf", &self.cpusel_conf())
+            .field("cpuperiod_sel", &self.cpuperiod_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERIOD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 29 - CPU sel option"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/date.rs b/esp32/src/rtc_cntl/date.rs
index a5dba0a6b8..4c4dc374d0 100644
--- a/esp32/src/rtc_cntl/date.rs
+++ b/esp32/src/rtc_cntl/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("cntl_date", &format_args!("{}", self.cntl_date().bits()))
+            .field("cntl_date", &self.cntl_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/diag1.rs b/esp32/src/rtc_cntl/diag1.rs
index b869cd8fdd..59dc8a7454 100644
--- a/esp32/src/rtc_cntl/diag1.rs
+++ b/esp32/src/rtc_cntl/diag1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIAG1")
-            .field(
-                "low_power_diag1",
-                &format_args!("{}", self.low_power_diag1().bits()),
-            )
+            .field("low_power_diag1", &self.low_power_diag1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIAG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diag1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIAG1_SPEC;
 impl crate::RegisterSpec for DIAG1_SPEC {
diff --git a/esp32/src/rtc_cntl/dig_iso.rs b/esp32/src/rtc_cntl/dig_iso.rs
index 8931acd3bf..d84e0598a2 100644
--- a/esp32/src/rtc_cntl/dig_iso.rs
+++ b/esp32/src/rtc_cntl/dig_iso.rs
@@ -224,105 +224,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIG_ISO")
-            .field("force_off", &format_args!("{}", self.force_off().bit()))
-            .field("force_on", &format_args!("{}", self.force_on().bit()))
-            .field(
-                "dg_pad_autohold",
-                &format_args!("{}", self.dg_pad_autohold().bit()),
-            )
-            .field(
-                "dg_pad_autohold_en",
-                &format_args!("{}", self.dg_pad_autohold_en().bit()),
-            )
-            .field(
-                "dg_pad_force_noiso",
-                &format_args!("{}", self.dg_pad_force_noiso().bit()),
-            )
-            .field(
-                "dg_pad_force_iso",
-                &format_args!("{}", self.dg_pad_force_iso().bit()),
-            )
-            .field(
-                "dg_pad_force_unhold",
-                &format_args!("{}", self.dg_pad_force_unhold().bit()),
-            )
-            .field(
-                "dg_pad_force_hold",
-                &format_args!("{}", self.dg_pad_force_hold().bit()),
-            )
-            .field(
-                "rom0_force_iso",
-                &format_args!("{}", self.rom0_force_iso().bit()),
-            )
-            .field(
-                "rom0_force_noiso",
-                &format_args!("{}", self.rom0_force_noiso().bit()),
-            )
-            .field(
-                "inter_ram0_force_iso",
-                &format_args!("{}", self.inter_ram0_force_iso().bit()),
-            )
-            .field(
-                "inter_ram0_force_noiso",
-                &format_args!("{}", self.inter_ram0_force_noiso().bit()),
-            )
-            .field(
-                "inter_ram1_force_iso",
-                &format_args!("{}", self.inter_ram1_force_iso().bit()),
-            )
-            .field(
-                "inter_ram1_force_noiso",
-                &format_args!("{}", self.inter_ram1_force_noiso().bit()),
-            )
-            .field(
-                "inter_ram2_force_iso",
-                &format_args!("{}", self.inter_ram2_force_iso().bit()),
-            )
-            .field(
-                "inter_ram2_force_noiso",
-                &format_args!("{}", self.inter_ram2_force_noiso().bit()),
-            )
-            .field(
-                "inter_ram3_force_iso",
-                &format_args!("{}", self.inter_ram3_force_iso().bit()),
-            )
-            .field(
-                "inter_ram3_force_noiso",
-                &format_args!("{}", self.inter_ram3_force_noiso().bit()),
-            )
-            .field(
-                "inter_ram4_force_iso",
-                &format_args!("{}", self.inter_ram4_force_iso().bit()),
-            )
-            .field(
-                "inter_ram4_force_noiso",
-                &format_args!("{}", self.inter_ram4_force_noiso().bit()),
-            )
-            .field(
-                "wifi_force_iso",
-                &format_args!("{}", self.wifi_force_iso().bit()),
-            )
-            .field(
-                "wifi_force_noiso",
-                &format_args!("{}", self.wifi_force_noiso().bit()),
-            )
-            .field(
-                "dg_wrap_force_iso",
-                &format_args!("{}", self.dg_wrap_force_iso().bit()),
-            )
-            .field(
-                "dg_wrap_force_noiso",
-                &format_args!("{}", self.dg_wrap_force_noiso().bit()),
-            )
+            .field("force_off", &self.force_off())
+            .field("force_on", &self.force_on())
+            .field("dg_pad_autohold", &self.dg_pad_autohold())
+            .field("dg_pad_autohold_en", &self.dg_pad_autohold_en())
+            .field("dg_pad_force_noiso", &self.dg_pad_force_noiso())
+            .field("dg_pad_force_iso", &self.dg_pad_force_iso())
+            .field("dg_pad_force_unhold", &self.dg_pad_force_unhold())
+            .field("dg_pad_force_hold", &self.dg_pad_force_hold())
+            .field("rom0_force_iso", &self.rom0_force_iso())
+            .field("rom0_force_noiso", &self.rom0_force_noiso())
+            .field("inter_ram0_force_iso", &self.inter_ram0_force_iso())
+            .field("inter_ram0_force_noiso", &self.inter_ram0_force_noiso())
+            .field("inter_ram1_force_iso", &self.inter_ram1_force_iso())
+            .field("inter_ram1_force_noiso", &self.inter_ram1_force_noiso())
+            .field("inter_ram2_force_iso", &self.inter_ram2_force_iso())
+            .field("inter_ram2_force_noiso", &self.inter_ram2_force_noiso())
+            .field("inter_ram3_force_iso", &self.inter_ram3_force_iso())
+            .field("inter_ram3_force_noiso", &self.inter_ram3_force_noiso())
+            .field("inter_ram4_force_iso", &self.inter_ram4_force_iso())
+            .field("inter_ram4_force_noiso", &self.inter_ram4_force_noiso())
+            .field("wifi_force_iso", &self.wifi_force_iso())
+            .field("wifi_force_noiso", &self.wifi_force_noiso())
+            .field("dg_wrap_force_iso", &self.dg_wrap_force_iso())
+            .field("dg_wrap_force_noiso", &self.dg_wrap_force_noiso())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIG_ISO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/dig_pwc.rs b/esp32/src/rtc_cntl/dig_pwc.rs
index 0bf3b622d6..f32c25a3b0 100644
--- a/esp32/src/rtc_cntl/dig_pwc.rs
+++ b/esp32/src/rtc_cntl/dig_pwc.rs
@@ -242,113 +242,35 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIG_PWC")
-            .field(
-                "lslp_mem_force_pd",
-                &format_args!("{}", self.lslp_mem_force_pd().bit()),
-            )
-            .field(
-                "lslp_mem_force_pu",
-                &format_args!("{}", self.lslp_mem_force_pu().bit()),
-            )
-            .field(
-                "rom0_force_pd",
-                &format_args!("{}", self.rom0_force_pd().bit()),
-            )
-            .field(
-                "rom0_force_pu",
-                &format_args!("{}", self.rom0_force_pu().bit()),
-            )
-            .field(
-                "inter_ram0_force_pd",
-                &format_args!("{}", self.inter_ram0_force_pd().bit()),
-            )
-            .field(
-                "inter_ram0_force_pu",
-                &format_args!("{}", self.inter_ram0_force_pu().bit()),
-            )
-            .field(
-                "inter_ram1_force_pd",
-                &format_args!("{}", self.inter_ram1_force_pd().bit()),
-            )
-            .field(
-                "inter_ram1_force_pu",
-                &format_args!("{}", self.inter_ram1_force_pu().bit()),
-            )
-            .field(
-                "inter_ram2_force_pd",
-                &format_args!("{}", self.inter_ram2_force_pd().bit()),
-            )
-            .field(
-                "inter_ram2_force_pu",
-                &format_args!("{}", self.inter_ram2_force_pu().bit()),
-            )
-            .field(
-                "inter_ram3_force_pd",
-                &format_args!("{}", self.inter_ram3_force_pd().bit()),
-            )
-            .field(
-                "inter_ram3_force_pu",
-                &format_args!("{}", self.inter_ram3_force_pu().bit()),
-            )
-            .field(
-                "inter_ram4_force_pd",
-                &format_args!("{}", self.inter_ram4_force_pd().bit()),
-            )
-            .field(
-                "inter_ram4_force_pu",
-                &format_args!("{}", self.inter_ram4_force_pu().bit()),
-            )
-            .field(
-                "wifi_force_pd",
-                &format_args!("{}", self.wifi_force_pd().bit()),
-            )
-            .field(
-                "wifi_force_pu",
-                &format_args!("{}", self.wifi_force_pu().bit()),
-            )
-            .field(
-                "dg_wrap_force_pd",
-                &format_args!("{}", self.dg_wrap_force_pd().bit()),
-            )
-            .field(
-                "dg_wrap_force_pu",
-                &format_args!("{}", self.dg_wrap_force_pu().bit()),
-            )
-            .field("rom0_pd_en", &format_args!("{}", self.rom0_pd_en().bit()))
-            .field(
-                "inter_ram0_pd_en",
-                &format_args!("{}", self.inter_ram0_pd_en().bit()),
-            )
-            .field(
-                "inter_ram1_pd_en",
-                &format_args!("{}", self.inter_ram1_pd_en().bit()),
-            )
-            .field(
-                "inter_ram2_pd_en",
-                &format_args!("{}", self.inter_ram2_pd_en().bit()),
-            )
-            .field(
-                "inter_ram3_pd_en",
-                &format_args!("{}", self.inter_ram3_pd_en().bit()),
-            )
-            .field(
-                "inter_ram4_pd_en",
-                &format_args!("{}", self.inter_ram4_pd_en().bit()),
-            )
-            .field("wifi_pd_en", &format_args!("{}", self.wifi_pd_en().bit()))
-            .field(
-                "dg_wrap_pd_en",
-                &format_args!("{}", self.dg_wrap_pd_en().bit()),
-            )
+            .field("lslp_mem_force_pd", &self.lslp_mem_force_pd())
+            .field("lslp_mem_force_pu", &self.lslp_mem_force_pu())
+            .field("rom0_force_pd", &self.rom0_force_pd())
+            .field("rom0_force_pu", &self.rom0_force_pu())
+            .field("inter_ram0_force_pd", &self.inter_ram0_force_pd())
+            .field("inter_ram0_force_pu", &self.inter_ram0_force_pu())
+            .field("inter_ram1_force_pd", &self.inter_ram1_force_pd())
+            .field("inter_ram1_force_pu", &self.inter_ram1_force_pu())
+            .field("inter_ram2_force_pd", &self.inter_ram2_force_pd())
+            .field("inter_ram2_force_pu", &self.inter_ram2_force_pu())
+            .field("inter_ram3_force_pd", &self.inter_ram3_force_pd())
+            .field("inter_ram3_force_pu", &self.inter_ram3_force_pu())
+            .field("inter_ram4_force_pd", &self.inter_ram4_force_pd())
+            .field("inter_ram4_force_pu", &self.inter_ram4_force_pu())
+            .field("wifi_force_pd", &self.wifi_force_pd())
+            .field("wifi_force_pu", &self.wifi_force_pu())
+            .field("dg_wrap_force_pd", &self.dg_wrap_force_pd())
+            .field("dg_wrap_force_pu", &self.dg_wrap_force_pu())
+            .field("rom0_pd_en", &self.rom0_pd_en())
+            .field("inter_ram0_pd_en", &self.inter_ram0_pd_en())
+            .field("inter_ram1_pd_en", &self.inter_ram1_pd_en())
+            .field("inter_ram2_pd_en", &self.inter_ram2_pd_en())
+            .field("inter_ram3_pd_en", &self.inter_ram3_pd_en())
+            .field("inter_ram4_pd_en", &self.inter_ram4_pd_en())
+            .field("wifi_pd_en", &self.wifi_pd_en())
+            .field("dg_wrap_pd_en", &self.dg_wrap_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIG_PWC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - memories in digital core force PD in sleep"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/ext_wakeup1.rs b/esp32/src/rtc_cntl/ext_wakeup1.rs
index 2763c62593..8490e2e984 100644
--- a/esp32/src/rtc_cntl/ext_wakeup1.rs
+++ b/esp32/src/rtc_cntl/ext_wakeup1.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP1")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - Bitmap to select RTC pads for ext wakeup1"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/ext_wakeup1_status.rs b/esp32/src/rtc_cntl/ext_wakeup1_status.rs
index 6e7001303e..7297829ad7 100644
--- a/esp32/src/rtc_cntl/ext_wakeup1_status.rs
+++ b/esp32/src/rtc_cntl/ext_wakeup1_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP1_STATUS")
-            .field(
-                "ext_wakeup1_status",
-                &format_args!("{}", self.ext_wakeup1_status().bits()),
-            )
+            .field("ext_wakeup1_status", &self.ext_wakeup1_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP1_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup1_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXT_WAKEUP1_STATUS_SPEC;
 impl crate::RegisterSpec for EXT_WAKEUP1_STATUS_SPEC {
diff --git a/esp32/src/rtc_cntl/ext_wakeup_conf.rs b/esp32/src/rtc_cntl/ext_wakeup_conf.rs
index 49c13ddc14..6bef18c58f 100644
--- a/esp32/src/rtc_cntl/ext_wakeup_conf.rs
+++ b/esp32/src/rtc_cntl/ext_wakeup_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP_CONF")
-            .field(
-                "ext_wakeup0_lv",
-                &format_args!("{}", self.ext_wakeup0_lv().bit()),
-            )
-            .field(
-                "ext_wakeup1_lv",
-                &format_args!("{}", self.ext_wakeup1_lv().bit()),
-            )
+            .field("ext_wakeup0_lv", &self.ext_wakeup0_lv())
+            .field("ext_wakeup1_lv", &self.ext_wakeup1_lv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - 0: external wakeup at low level 1: external wakeup at high level"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/ext_xtl_conf.rs b/esp32/src/rtc_cntl/ext_xtl_conf.rs
index b585e96feb..e0b97e9808 100644
--- a/esp32/src/rtc_cntl/ext_xtl_conf.rs
+++ b/esp32/src/rtc_cntl/ext_xtl_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_XTL_CONF")
-            .field(
-                "xtl_ext_ctr_lv",
-                &format_args!("{}", self.xtl_ext_ctr_lv().bit()),
-            )
-            .field(
-                "xtl_ext_ctr_en",
-                &format_args!("{}", self.xtl_ext_ctr_en().bit()),
-            )
+            .field("xtl_ext_ctr_lv", &self.xtl_ext_ctr_lv())
+            .field("xtl_ext_ctr_en", &self.xtl_ext_ctr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_XTL_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - 0: power down XTAL at high level 1: power down XTAL at low level"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/hold_force.rs b/esp32/src/rtc_cntl/hold_force.rs
index d7b124c495..da5685f4a4 100644
--- a/esp32/src/rtc_cntl/hold_force.rs
+++ b/esp32/src/rtc_cntl/hold_force.rs
@@ -170,87 +170,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOLD_FORCE")
-            .field(
-                "adc1_hold_force",
-                &format_args!("{}", self.adc1_hold_force().bit()),
-            )
-            .field(
-                "adc2_hold_force",
-                &format_args!("{}", self.adc2_hold_force().bit()),
-            )
-            .field(
-                "pdac1_hold_force",
-                &format_args!("{}", self.pdac1_hold_force().bit()),
-            )
-            .field(
-                "pdac2_hold_force",
-                &format_args!("{}", self.pdac2_hold_force().bit()),
-            )
-            .field(
-                "sense1_hold_force",
-                &format_args!("{}", self.sense1_hold_force().bit()),
-            )
-            .field(
-                "sense2_hold_force",
-                &format_args!("{}", self.sense2_hold_force().bit()),
-            )
-            .field(
-                "sense3_hold_force",
-                &format_args!("{}", self.sense3_hold_force().bit()),
-            )
-            .field(
-                "sense4_hold_force",
-                &format_args!("{}", self.sense4_hold_force().bit()),
-            )
-            .field(
-                "touch_pad0_hold_force",
-                &format_args!("{}", self.touch_pad0_hold_force().bit()),
-            )
-            .field(
-                "touch_pad1_hold_force",
-                &format_args!("{}", self.touch_pad1_hold_force().bit()),
-            )
-            .field(
-                "touch_pad2_hold_force",
-                &format_args!("{}", self.touch_pad2_hold_force().bit()),
-            )
-            .field(
-                "touch_pad3_hold_force",
-                &format_args!("{}", self.touch_pad3_hold_force().bit()),
-            )
-            .field(
-                "touch_pad4_hold_force",
-                &format_args!("{}", self.touch_pad4_hold_force().bit()),
-            )
-            .field(
-                "touch_pad5_hold_force",
-                &format_args!("{}", self.touch_pad5_hold_force().bit()),
-            )
-            .field(
-                "touch_pad6_hold_force",
-                &format_args!("{}", self.touch_pad6_hold_force().bit()),
-            )
-            .field(
-                "touch_pad7_hold_force",
-                &format_args!("{}", self.touch_pad7_hold_force().bit()),
-            )
-            .field(
-                "x32p_hold_force",
-                &format_args!("{}", self.x32p_hold_force().bit()),
-            )
-            .field(
-                "x32n_hold_force",
-                &format_args!("{}", self.x32n_hold_force().bit()),
-            )
+            .field("adc1_hold_force", &self.adc1_hold_force())
+            .field("adc2_hold_force", &self.adc2_hold_force())
+            .field("pdac1_hold_force", &self.pdac1_hold_force())
+            .field("pdac2_hold_force", &self.pdac2_hold_force())
+            .field("sense1_hold_force", &self.sense1_hold_force())
+            .field("sense2_hold_force", &self.sense2_hold_force())
+            .field("sense3_hold_force", &self.sense3_hold_force())
+            .field("sense4_hold_force", &self.sense4_hold_force())
+            .field("touch_pad0_hold_force", &self.touch_pad0_hold_force())
+            .field("touch_pad1_hold_force", &self.touch_pad1_hold_force())
+            .field("touch_pad2_hold_force", &self.touch_pad2_hold_force())
+            .field("touch_pad3_hold_force", &self.touch_pad3_hold_force())
+            .field("touch_pad4_hold_force", &self.touch_pad4_hold_force())
+            .field("touch_pad5_hold_force", &self.touch_pad5_hold_force())
+            .field("touch_pad6_hold_force", &self.touch_pad6_hold_force())
+            .field("touch_pad7_hold_force", &self.touch_pad7_hold_force())
+            .field("x32p_hold_force", &self.x32p_hold_force())
+            .field("x32n_hold_force", &self.x32n_hold_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOLD_FORCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/int_ena.rs b/esp32/src/rtc_cntl/int_ena.rs
index 46c69b03d8..4e2cdb36a8 100644
--- a/esp32/src/rtc_cntl/int_ena.rs
+++ b/esp32/src/rtc_cntl/int_ena.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("time_valid", &format_args!("{}", self.time_valid().bit()))
-            .field("ulp_cp", &format_args!("{}", self.ulp_cp().bit()))
-            .field("touch", &format_args!("{}", self.touch().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("wdt", &self.wdt())
+            .field("time_valid", &self.time_valid())
+            .field("ulp_cp", &self.ulp_cp())
+            .field("touch", &self.touch())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable sleep wakeup interrupt"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/int_raw.rs b/esp32/src/rtc_cntl/int_raw.rs
index e9f59060ca..f3b84d30e5 100644
--- a/esp32/src/rtc_cntl/int_raw.rs
+++ b/esp32/src/rtc_cntl/int_raw.rs
@@ -69,24 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("time_valid", &format_args!("{}", self.time_valid().bit()))
-            .field("ulp_cp", &format_args!("{}", self.ulp_cp().bit()))
-            .field("touch", &format_args!("{}", self.touch().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("wdt", &self.wdt())
+            .field("time_valid", &self.time_valid())
+            .field("ulp_cp", &self.ulp_cp())
+            .field("touch", &self.touch())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32/src/rtc_cntl/int_st.rs b/esp32/src/rtc_cntl/int_st.rs
index 38bb99cf92..200c91b996 100644
--- a/esp32/src/rtc_cntl/int_st.rs
+++ b/esp32/src/rtc_cntl/int_st.rs
@@ -69,24 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("time_valid", &format_args!("{}", self.time_valid().bit()))
-            .field("sar", &format_args!("{}", self.sar().bit()))
-            .field("touch", &format_args!("{}", self.touch().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("wdt", &self.wdt())
+            .field("time_valid", &self.time_valid())
+            .field("sar", &self.sar())
+            .field("touch", &self.touch())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32/src/rtc_cntl/low_power_st.rs b/esp32/src/rtc_cntl/low_power_st.rs
index 83dd56d217..6321074b7e 100644
--- a/esp32/src/rtc_cntl/low_power_st.rs
+++ b/esp32/src/rtc_cntl/low_power_st.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOW_POWER_ST")
-            .field(
-                "low_power_diag0",
-                &format_args!("{}", self.low_power_diag0().bits()),
-            )
-            .field(
-                "rdy_for_wakeup",
-                &format_args!("{}", self.rdy_for_wakeup().bit()),
-            )
+            .field("low_power_diag0", &self.low_power_diag0())
+            .field("rdy_for_wakeup", &self.rdy_for_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOW_POWER_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`low_power_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOW_POWER_ST_SPEC;
 impl crate::RegisterSpec for LOW_POWER_ST_SPEC {
diff --git a/esp32/src/rtc_cntl/options0.rs b/esp32/src/rtc_cntl/options0.rs
index e9b7420d30..365100a158 100644
--- a/esp32/src/rtc_cntl/options0.rs
+++ b/esp32/src/rtc_cntl/options0.rs
@@ -257,123 +257,36 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OPTIONS0")
-            .field(
-                "sw_stall_appcpu_c0",
-                &format_args!("{}", self.sw_stall_appcpu_c0().bits()),
-            )
-            .field(
-                "sw_stall_procpu_c0",
-                &format_args!("{}", self.sw_stall_procpu_c0().bits()),
-            )
-            .field(
-                "bb_i2c_force_pd",
-                &format_args!("{}", self.bb_i2c_force_pd().bit()),
-            )
-            .field(
-                "bb_i2c_force_pu",
-                &format_args!("{}", self.bb_i2c_force_pu().bit()),
-            )
-            .field(
-                "bbpll_i2c_force_pd",
-                &format_args!("{}", self.bbpll_i2c_force_pd().bit()),
-            )
-            .field(
-                "bbpll_i2c_force_pu",
-                &format_args!("{}", self.bbpll_i2c_force_pu().bit()),
-            )
-            .field(
-                "bbpll_force_pd",
-                &format_args!("{}", self.bbpll_force_pd().bit()),
-            )
-            .field(
-                "bbpll_force_pu",
-                &format_args!("{}", self.bbpll_force_pu().bit()),
-            )
-            .field(
-                "xtl_force_pd",
-                &format_args!("{}", self.xtl_force_pd().bit()),
-            )
-            .field(
-                "xtl_force_pu",
-                &format_args!("{}", self.xtl_force_pu().bit()),
-            )
-            .field(
-                "bias_sleep_folw_8m",
-                &format_args!("{}", self.bias_sleep_folw_8m().bit()),
-            )
-            .field(
-                "bias_force_sleep",
-                &format_args!("{}", self.bias_force_sleep().bit()),
-            )
-            .field(
-                "bias_force_nosleep",
-                &format_args!("{}", self.bias_force_nosleep().bit()),
-            )
-            .field(
-                "bias_i2c_folw_8m",
-                &format_args!("{}", self.bias_i2c_folw_8m().bit()),
-            )
-            .field(
-                "bias_i2c_force_pd",
-                &format_args!("{}", self.bias_i2c_force_pd().bit()),
-            )
-            .field(
-                "bias_i2c_force_pu",
-                &format_args!("{}", self.bias_i2c_force_pu().bit()),
-            )
-            .field(
-                "bias_core_folw_8m",
-                &format_args!("{}", self.bias_core_folw_8m().bit()),
-            )
-            .field(
-                "bias_core_force_pd",
-                &format_args!("{}", self.bias_core_force_pd().bit()),
-            )
-            .field(
-                "bias_core_force_pu",
-                &format_args!("{}", self.bias_core_force_pu().bit()),
-            )
-            .field(
-                "xtl_force_iso",
-                &format_args!("{}", self.xtl_force_iso().bit()),
-            )
-            .field(
-                "pll_force_iso",
-                &format_args!("{}", self.pll_force_iso().bit()),
-            )
-            .field(
-                "analog_force_iso",
-                &format_args!("{}", self.analog_force_iso().bit()),
-            )
-            .field(
-                "xtl_force_noiso",
-                &format_args!("{}", self.xtl_force_noiso().bit()),
-            )
-            .field(
-                "pll_force_noiso",
-                &format_args!("{}", self.pll_force_noiso().bit()),
-            )
-            .field(
-                "analog_force_noiso",
-                &format_args!("{}", self.analog_force_noiso().bit()),
-            )
-            .field(
-                "dg_wrap_force_rst",
-                &format_args!("{}", self.dg_wrap_force_rst().bit()),
-            )
-            .field(
-                "dg_wrap_force_norst",
-                &format_args!("{}", self.dg_wrap_force_norst().bit()),
-            )
+            .field("sw_stall_appcpu_c0", &self.sw_stall_appcpu_c0())
+            .field("sw_stall_procpu_c0", &self.sw_stall_procpu_c0())
+            .field("bb_i2c_force_pd", &self.bb_i2c_force_pd())
+            .field("bb_i2c_force_pu", &self.bb_i2c_force_pu())
+            .field("bbpll_i2c_force_pd", &self.bbpll_i2c_force_pd())
+            .field("bbpll_i2c_force_pu", &self.bbpll_i2c_force_pu())
+            .field("bbpll_force_pd", &self.bbpll_force_pd())
+            .field("bbpll_force_pu", &self.bbpll_force_pu())
+            .field("xtl_force_pd", &self.xtl_force_pd())
+            .field("xtl_force_pu", &self.xtl_force_pu())
+            .field("bias_sleep_folw_8m", &self.bias_sleep_folw_8m())
+            .field("bias_force_sleep", &self.bias_force_sleep())
+            .field("bias_force_nosleep", &self.bias_force_nosleep())
+            .field("bias_i2c_folw_8m", &self.bias_i2c_folw_8m())
+            .field("bias_i2c_force_pd", &self.bias_i2c_force_pd())
+            .field("bias_i2c_force_pu", &self.bias_i2c_force_pu())
+            .field("bias_core_folw_8m", &self.bias_core_folw_8m())
+            .field("bias_core_force_pd", &self.bias_core_force_pd())
+            .field("bias_core_force_pu", &self.bias_core_force_pu())
+            .field("xtl_force_iso", &self.xtl_force_iso())
+            .field("pll_force_iso", &self.pll_force_iso())
+            .field("analog_force_iso", &self.analog_force_iso())
+            .field("xtl_force_noiso", &self.xtl_force_noiso())
+            .field("pll_force_noiso", &self.pll_force_noiso())
+            .field("analog_force_noiso", &self.analog_force_noiso())
+            .field("dg_wrap_force_rst", &self.dg_wrap_force_rst())
+            .field("dg_wrap_force_norst", &self.dg_wrap_force_norst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OPTIONS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - {reg_sw_stall_appcpu_c1\\[5:0\\] reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/pwc.rs b/esp32/src/rtc_cntl/pwc.rs
index d2c0975abd..34dacbe79d 100644
--- a/esp32/src/rtc_cntl/pwc.rs
+++ b/esp32/src/rtc_cntl/pwc.rs
@@ -197,84 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWC")
-            .field(
-                "fastmem_force_noiso",
-                &format_args!("{}", self.fastmem_force_noiso().bit()),
-            )
-            .field(
-                "fastmem_force_iso",
-                &format_args!("{}", self.fastmem_force_iso().bit()),
-            )
-            .field(
-                "slowmem_force_noiso",
-                &format_args!("{}", self.slowmem_force_noiso().bit()),
-            )
-            .field(
-                "slowmem_force_iso",
-                &format_args!("{}", self.slowmem_force_iso().bit()),
-            )
-            .field("force_iso", &format_args!("{}", self.force_iso().bit()))
-            .field("force_noiso", &format_args!("{}", self.force_noiso().bit()))
-            .field(
-                "fastmem_folw_cpu",
-                &format_args!("{}", self.fastmem_folw_cpu().bit()),
-            )
-            .field(
-                "fastmem_force_lpd",
-                &format_args!("{}", self.fastmem_force_lpd().bit()),
-            )
-            .field(
-                "fastmem_force_lpu",
-                &format_args!("{}", self.fastmem_force_lpu().bit()),
-            )
-            .field(
-                "slowmem_folw_cpu",
-                &format_args!("{}", self.slowmem_folw_cpu().bit()),
-            )
-            .field(
-                "slowmem_force_lpd",
-                &format_args!("{}", self.slowmem_force_lpd().bit()),
-            )
-            .field(
-                "slowmem_force_lpu",
-                &format_args!("{}", self.slowmem_force_lpu().bit()),
-            )
-            .field(
-                "fastmem_force_pd",
-                &format_args!("{}", self.fastmem_force_pd().bit()),
-            )
-            .field(
-                "fastmem_force_pu",
-                &format_args!("{}", self.fastmem_force_pu().bit()),
-            )
-            .field(
-                "fastmem_pd_en",
-                &format_args!("{}", self.fastmem_pd_en().bit()),
-            )
-            .field(
-                "slowmem_force_pd",
-                &format_args!("{}", self.slowmem_force_pd().bit()),
-            )
-            .field(
-                "slowmem_force_pu",
-                &format_args!("{}", self.slowmem_force_pu().bit()),
-            )
-            .field(
-                "slowmem_pd_en",
-                &format_args!("{}", self.slowmem_pd_en().bit()),
-            )
-            .field("force_pd", &format_args!("{}", self.force_pd().bit()))
-            .field("force_pu", &format_args!("{}", self.force_pu().bit()))
-            .field("pd_en", &format_args!("{}", self.pd_en().bit()))
+            .field("fastmem_force_noiso", &self.fastmem_force_noiso())
+            .field("fastmem_force_iso", &self.fastmem_force_iso())
+            .field("slowmem_force_noiso", &self.slowmem_force_noiso())
+            .field("slowmem_force_iso", &self.slowmem_force_iso())
+            .field("force_iso", &self.force_iso())
+            .field("force_noiso", &self.force_noiso())
+            .field("fastmem_folw_cpu", &self.fastmem_folw_cpu())
+            .field("fastmem_force_lpd", &self.fastmem_force_lpd())
+            .field("fastmem_force_lpu", &self.fastmem_force_lpu())
+            .field("slowmem_folw_cpu", &self.slowmem_folw_cpu())
+            .field("slowmem_force_lpd", &self.slowmem_force_lpd())
+            .field("slowmem_force_lpu", &self.slowmem_force_lpu())
+            .field("fastmem_force_pd", &self.fastmem_force_pd())
+            .field("fastmem_force_pu", &self.fastmem_force_pu())
+            .field("fastmem_pd_en", &self.fastmem_pd_en())
+            .field("slowmem_force_pd", &self.slowmem_force_pd())
+            .field("slowmem_force_pu", &self.slowmem_force_pu())
+            .field("slowmem_pd_en", &self.slowmem_pd_en())
+            .field("force_pd", &self.force_pd())
+            .field("force_pu", &self.force_pu())
+            .field("pd_en", &self.pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Fast RTC memory force no ISO"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/reg.rs b/esp32/src/rtc_cntl/reg.rs
index ec93e87076..8c08882ee1 100644
--- a/esp32/src/rtc_cntl/reg.rs
+++ b/esp32/src/rtc_cntl/reg.rs
@@ -98,40 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG")
-            .field(
-                "sck_dcap_force",
-                &format_args!("{}", self.sck_dcap_force().bit()),
-            )
-            .field(
-                "dig_dbias_slp",
-                &format_args!("{}", self.dig_dbias_slp().bits()),
-            )
-            .field(
-                "dig_dbias_wak",
-                &format_args!("{}", self.dig_dbias_wak().bits()),
-            )
-            .field("sck_dcap", &format_args!("{}", self.sck_dcap().bits()))
-            .field("dbias_slp", &format_args!("{}", self.dbias_slp().bits()))
-            .field("dbias_wak", &format_args!("{}", self.dbias_wak().bits()))
-            .field(
-                "dboost_force_pd",
-                &format_args!("{}", self.dboost_force_pd().bit()),
-            )
-            .field(
-                "dboost_force_pu",
-                &format_args!("{}", self.dboost_force_pu().bit()),
-            )
-            .field("force_pd", &format_args!("{}", self.force_pd().bit()))
-            .field("force_pu", &format_args!("{}", self.force_pu().bit()))
+            .field("sck_dcap_force", &self.sck_dcap_force())
+            .field("dig_dbias_slp", &self.dig_dbias_slp())
+            .field("dig_dbias_wak", &self.dig_dbias_wak())
+            .field("sck_dcap", &self.sck_dcap())
+            .field("dbias_slp", &self.dbias_slp())
+            .field("dbias_wak", &self.dbias_wak())
+            .field("dboost_force_pd", &self.dboost_force_pd())
+            .field("dboost_force_pu", &self.dboost_force_pu())
+            .field("force_pd", &self.force_pd())
+            .field("force_pu", &self.force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - N/A"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/reset_state.rs b/esp32/src/rtc_cntl/reset_state.rs
index c0d403ad13..37385a70eb 100644
--- a/esp32/src/rtc_cntl/reset_state.rs
+++ b/esp32/src/rtc_cntl/reset_state.rs
@@ -40,31 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET_STATE")
-            .field(
-                "reset_cause_procpu",
-                &format_args!("{}", self.reset_cause_procpu().bits()),
-            )
-            .field(
-                "reset_cause_appcpu",
-                &format_args!("{}", self.reset_cause_appcpu().bits()),
-            )
-            .field(
-                "appcpu_stat_vector_sel",
-                &format_args!("{}", self.appcpu_stat_vector_sel().bit()),
-            )
-            .field(
-                "procpu_stat_vector_sel",
-                &format_args!("{}", self.procpu_stat_vector_sel().bit()),
-            )
+            .field("reset_cause_procpu", &self.reset_cause_procpu())
+            .field("reset_cause_appcpu", &self.reset_cause_appcpu())
+            .field("appcpu_stat_vector_sel", &self.appcpu_stat_vector_sel())
+            .field("procpu_stat_vector_sel", &self.procpu_stat_vector_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - APP CPU state vector sel"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/sdio_act_conf.rs b/esp32/src/rtc_cntl/sdio_act_conf.rs
index 50e2da42c5..163d8b1bdf 100644
--- a/esp32/src/rtc_cntl/sdio_act_conf.rs
+++ b/esp32/src/rtc_cntl/sdio_act_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_ACT_CONF")
-            .field(
-                "sdio_act_dnum",
-                &format_args!("{}", self.sdio_act_dnum().bits()),
-            )
+            .field("sdio_act_dnum", &self.sdio_act_dnum())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_ACT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:31"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/sdio_conf.rs b/esp32/src/rtc_cntl/sdio_conf.rs
index caa6d4f0a6..769c9b071a 100644
--- a/esp32/src/rtc_cntl/sdio_conf.rs
+++ b/esp32/src/rtc_cntl/sdio_conf.rs
@@ -78,26 +78,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_CONF")
-            .field("sdio_pd_en", &format_args!("{}", self.sdio_pd_en().bit()))
-            .field("sdio_force", &format_args!("{}", self.sdio_force().bit()))
-            .field("sdio_tieh", &format_args!("{}", self.sdio_tieh().bit()))
-            .field(
-                "reg1p8_ready",
-                &format_args!("{}", self.reg1p8_ready().bit()),
-            )
-            .field("drefl_sdio", &format_args!("{}", self.drefl_sdio().bits()))
-            .field("drefm_sdio", &format_args!("{}", self.drefm_sdio().bits()))
-            .field("drefh_sdio", &format_args!("{}", self.drefh_sdio().bits()))
-            .field("xpd_sdio", &format_args!("{}", self.xpd_sdio().bit()))
+            .field("sdio_pd_en", &self.sdio_pd_en())
+            .field("sdio_force", &self.sdio_force())
+            .field("sdio_tieh", &self.sdio_tieh())
+            .field("reg1p8_ready", &self.reg1p8_ready())
+            .field("drefl_sdio", &self.drefl_sdio())
+            .field("drefm_sdio", &self.drefm_sdio())
+            .field("drefh_sdio", &self.drefh_sdio())
+            .field("xpd_sdio", &self.xpd_sdio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - power down SDIO_REG in sleep. Only active when reg_sdio_force = 0"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/slp_reject_conf.rs b/esp32/src/rtc_cntl/slp_reject_conf.rs
index 139fcfb170..0a177270d7 100644
--- a/esp32/src/rtc_cntl/slp_reject_conf.rs
+++ b/esp32/src/rtc_cntl/slp_reject_conf.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_REJECT_CONF")
-            .field(
-                "gpio_reject_en",
-                &format_args!("{}", self.gpio_reject_en().bit()),
-            )
-            .field(
-                "sdio_reject_en",
-                &format_args!("{}", self.sdio_reject_en().bit()),
-            )
-            .field(
-                "light_slp_reject_en",
-                &format_args!("{}", self.light_slp_reject_en().bit()),
-            )
-            .field(
-                "deep_slp_reject_en",
-                &format_args!("{}", self.deep_slp_reject_en().bit()),
-            )
-            .field(
-                "reject_cause",
-                &format_args!("{}", self.reject_cause().bits()),
-            )
+            .field("gpio_reject_en", &self.gpio_reject_en())
+            .field("sdio_reject_en", &self.sdio_reject_en())
+            .field("light_slp_reject_en", &self.light_slp_reject_en())
+            .field("deep_slp_reject_en", &self.deep_slp_reject_en())
+            .field("reject_cause", &self.reject_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_REJECT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - enable GPIO reject"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/slp_timer0.rs b/esp32/src/rtc_cntl/slp_timer0.rs
index 81977083d4..a6a2573cd0 100644
--- a/esp32/src/rtc_cntl/slp_timer0.rs
+++ b/esp32/src/rtc_cntl/slp_timer0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_TIMER0")
-            .field("slp_val_lo", &format_args!("{}", self.slp_val_lo().bits()))
+            .field("slp_val_lo", &self.slp_val_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_TIMER0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - RTC sleep timer low 32 bits"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/slp_timer1.rs b/esp32/src/rtc_cntl/slp_timer1.rs
index c3f0d3d575..2ecd87eea9 100644
--- a/esp32/src/rtc_cntl/slp_timer1.rs
+++ b/esp32/src/rtc_cntl/slp_timer1.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_TIMER1")
-            .field("slp_val_hi", &format_args!("{}", self.slp_val_hi().bits()))
-            .field(
-                "main_timer_alarm_en",
-                &format_args!("{}", self.main_timer_alarm_en().bit()),
-            )
+            .field("slp_val_hi", &self.slp_val_hi())
+            .field("main_timer_alarm_en", &self.main_timer_alarm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_TIMER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - RTC sleep timer high 16 bits"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/state0.rs b/esp32/src/rtc_cntl/state0.rs
index fffdc85d68..b86605cdde 100644
--- a/esp32/src/rtc_cntl/state0.rs
+++ b/esp32/src/rtc_cntl/state0.rs
@@ -87,42 +87,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE0")
-            .field(
-                "touch_wakeup_force_en",
-                &format_args!("{}", self.touch_wakeup_force_en().bit()),
-            )
-            .field(
-                "ulp_cp_wakeup_force_en",
-                &format_args!("{}", self.ulp_cp_wakeup_force_en().bit()),
-            )
-            .field(
-                "apb2rtc_bridge_sel",
-                &format_args!("{}", self.apb2rtc_bridge_sel().bit()),
-            )
-            .field(
-                "touch_slp_timer_en",
-                &format_args!("{}", self.touch_slp_timer_en().bit()),
-            )
-            .field(
-                "ulp_cp_slp_timer_en",
-                &format_args!("{}", self.ulp_cp_slp_timer_en().bit()),
-            )
-            .field(
-                "sdio_active_ind",
-                &format_args!("{}", self.sdio_active_ind().bit()),
-            )
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("sleep_en", &format_args!("{}", self.sleep_en().bit()))
+            .field("touch_wakeup_force_en", &self.touch_wakeup_force_en())
+            .field("ulp_cp_wakeup_force_en", &self.ulp_cp_wakeup_force_en())
+            .field("apb2rtc_bridge_sel", &self.apb2rtc_bridge_sel())
+            .field("touch_slp_timer_en", &self.touch_slp_timer_en())
+            .field("ulp_cp_slp_timer_en", &self.ulp_cp_slp_timer_en())
+            .field("sdio_active_ind", &self.sdio_active_ind())
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sleep_en", &self.sleep_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - touch controller force wake up"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/store0.rs b/esp32/src/rtc_cntl/store0.rs
index 4284c361a5..beb8c55276 100644
--- a/esp32/src/rtc_cntl/store0.rs
+++ b/esp32/src/rtc_cntl/store0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE0")
-            .field("scratch0", &format_args!("{}", self.scratch0().bits()))
+            .field("scratch0", &self.scratch0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/store1.rs b/esp32/src/rtc_cntl/store1.rs
index 0a9d8f808c..1013b84a6e 100644
--- a/esp32/src/rtc_cntl/store1.rs
+++ b/esp32/src/rtc_cntl/store1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE1")
-            .field("scratch1", &format_args!("{}", self.scratch1().bits()))
+            .field("scratch1", &self.scratch1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/store2.rs b/esp32/src/rtc_cntl/store2.rs
index 32ca6fb0d3..dd05f38d7c 100644
--- a/esp32/src/rtc_cntl/store2.rs
+++ b/esp32/src/rtc_cntl/store2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE2")
-            .field("scratch2", &format_args!("{}", self.scratch2().bits()))
+            .field("scratch2", &self.scratch2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/store3.rs b/esp32/src/rtc_cntl/store3.rs
index 36c86f9fae..3b832e2d31 100644
--- a/esp32/src/rtc_cntl/store3.rs
+++ b/esp32/src/rtc_cntl/store3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE3")
-            .field("scratch3", &format_args!("{}", self.scratch3().bits()))
+            .field("scratch3", &self.scratch3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/store4.rs b/esp32/src/rtc_cntl/store4.rs
index c6f528e96b..4ad780c69d 100644
--- a/esp32/src/rtc_cntl/store4.rs
+++ b/esp32/src/rtc_cntl/store4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE4")
-            .field("scratch4", &format_args!("{}", self.scratch4().bits()))
+            .field("scratch4", &self.scratch4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/store5.rs b/esp32/src/rtc_cntl/store5.rs
index 6384f6392e..dcbb20ef38 100644
--- a/esp32/src/rtc_cntl/store5.rs
+++ b/esp32/src/rtc_cntl/store5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE5")
-            .field("scratch5", &format_args!("{}", self.scratch5().bits()))
+            .field("scratch5", &self.scratch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/store6.rs b/esp32/src/rtc_cntl/store6.rs
index 5fa17ad854..122ce90fe4 100644
--- a/esp32/src/rtc_cntl/store6.rs
+++ b/esp32/src/rtc_cntl/store6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE6")
-            .field("scratch6", &format_args!("{}", self.scratch6().bits()))
+            .field("scratch6", &self.scratch6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/store7.rs b/esp32/src/rtc_cntl/store7.rs
index e5a430c8a3..3b40f29296 100644
--- a/esp32/src/rtc_cntl/store7.rs
+++ b/esp32/src/rtc_cntl/store7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE7")
-            .field("scratch7", &format_args!("{}", self.scratch7().bits()))
+            .field("scratch7", &self.scratch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 32-bit general purpose retention register"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/sw_cpu_stall.rs b/esp32/src/rtc_cntl/sw_cpu_stall.rs
index d6775082ea..1f653a303d 100644
--- a/esp32/src/rtc_cntl/sw_cpu_stall.rs
+++ b/esp32/src/rtc_cntl/sw_cpu_stall.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SW_CPU_STALL")
-            .field(
-                "sw_stall_appcpu_c1",
-                &format_args!("{}", self.sw_stall_appcpu_c1().bits()),
-            )
-            .field(
-                "sw_stall_procpu_c1",
-                &format_args!("{}", self.sw_stall_procpu_c1().bits()),
-            )
+            .field("sw_stall_appcpu_c1", &self.sw_stall_appcpu_c1())
+            .field("sw_stall_procpu_c1", &self.sw_stall_procpu_c1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SW_CPU_STALL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:25 - {reg_sw_stall_appcpu_c1\\[5:0\\] reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/test_mux.rs b/esp32/src/rtc_cntl/test_mux.rs
index 839466cc4a..332c85ac6c 100644
--- a/esp32/src/rtc_cntl/test_mux.rs
+++ b/esp32/src/rtc_cntl/test_mux.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEST_MUX")
-            .field("ent_rtc", &format_args!("{}", self.ent_rtc().bit()))
-            .field("dtest_rtc", &format_args!("{}", self.dtest_rtc().bits()))
+            .field("ent_rtc", &self.ent_rtc())
+            .field("dtest_rtc", &self.dtest_rtc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEST_MUX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 29 - ENT_RTC"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/time0.rs b/esp32/src/rtc_cntl/time0.rs
index 0a7f8712ab..54075eafa9 100644
--- a/esp32/src/rtc_cntl/time0.rs
+++ b/esp32/src/rtc_cntl/time0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME0")
-            .field("time_lo", &format_args!("{}", self.time_lo().bits()))
+            .field("time_lo", &self.time_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIME0_SPEC;
 impl crate::RegisterSpec for TIME0_SPEC {
diff --git a/esp32/src/rtc_cntl/time1.rs b/esp32/src/rtc_cntl/time1.rs
index 3d6752493e..3857dda837 100644
--- a/esp32/src/rtc_cntl/time1.rs
+++ b/esp32/src/rtc_cntl/time1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME1")
-            .field("time_hi", &format_args!("{}", self.time_hi().bits()))
+            .field("time_hi", &self.time_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIME1_SPEC;
 impl crate::RegisterSpec for TIME1_SPEC {
diff --git a/esp32/src/rtc_cntl/time_update.rs b/esp32/src/rtc_cntl/time_update.rs
index 26716a26f1..c570b44cfa 100644
--- a/esp32/src/rtc_cntl/time_update.rs
+++ b/esp32/src/rtc_cntl/time_update.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_UPDATE")
-            .field("time_valid", &format_args!("{}", self.time_valid().bit()))
+            .field("time_valid", &self.time_valid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Set 1: to update register with RTC timer"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/timer1.rs b/esp32/src/rtc_cntl/timer1.rs
index 445b52332b..f2c03d790b 100644
--- a/esp32/src/rtc_cntl/timer1.rs
+++ b/esp32/src/rtc_cntl/timer1.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER1")
-            .field(
-                "cpu_stall_en",
-                &format_args!("{}", self.cpu_stall_en().bit()),
-            )
-            .field(
-                "cpu_stall_wait",
-                &format_args!("{}", self.cpu_stall_wait().bits()),
-            )
-            .field("ck8m_wait", &format_args!("{}", self.ck8m_wait().bits()))
-            .field(
-                "xtl_buf_wait",
-                &format_args!("{}", self.xtl_buf_wait().bits()),
-            )
-            .field(
-                "pll_buf_wait",
-                &format_args!("{}", self.pll_buf_wait().bits()),
-            )
+            .field("cpu_stall_en", &self.cpu_stall_en())
+            .field("cpu_stall_wait", &self.cpu_stall_wait())
+            .field("ck8m_wait", &self.ck8m_wait())
+            .field("xtl_buf_wait", &self.xtl_buf_wait())
+            .field("pll_buf_wait", &self.pll_buf_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - CPU stall enable bit"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/timer2.rs b/esp32/src/rtc_cntl/timer2.rs
index f7815d40b3..c9b8204ded 100644
--- a/esp32/src/rtc_cntl/timer2.rs
+++ b/esp32/src/rtc_cntl/timer2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER2")
-            .field(
-                "ulpcp_touch_start_wait",
-                &format_args!("{}", self.ulpcp_touch_start_wait().bits()),
-            )
-            .field(
-                "min_time_ck8m_off",
-                &format_args!("{}", self.min_time_ck8m_off().bits()),
-            )
+            .field("ulpcp_touch_start_wait", &self.ulpcp_touch_start_wait())
+            .field("min_time_ck8m_off", &self.min_time_ck8m_off())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 15:23 - wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/timer3.rs b/esp32/src/rtc_cntl/timer3.rs
index f224f54d4b..2039577093 100644
--- a/esp32/src/rtc_cntl/timer3.rs
+++ b/esp32/src/rtc_cntl/timer3.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER3")
-            .field(
-                "wifi_wait_timer",
-                &format_args!("{}", self.wifi_wait_timer().bits()),
-            )
-            .field(
-                "wifi_powerup_timer",
-                &format_args!("{}", self.wifi_powerup_timer().bits()),
-            )
-            .field(
-                "rom_ram_wait_timer",
-                &format_args!("{}", self.rom_ram_wait_timer().bits()),
-            )
-            .field(
-                "rom_ram_powerup_timer",
-                &format_args!("{}", self.rom_ram_powerup_timer().bits()),
-            )
+            .field("wifi_wait_timer", &self.wifi_wait_timer())
+            .field("wifi_powerup_timer", &self.wifi_powerup_timer())
+            .field("rom_ram_wait_timer", &self.rom_ram_wait_timer())
+            .field("rom_ram_powerup_timer", &self.rom_ram_powerup_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/timer4.rs b/esp32/src/rtc_cntl/timer4.rs
index d1ca99ccac..6ae23f2e69 100644
--- a/esp32/src/rtc_cntl/timer4.rs
+++ b/esp32/src/rtc_cntl/timer4.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER4")
-            .field("wait_timer", &format_args!("{}", self.wait_timer().bits()))
-            .field(
-                "powerup_timer",
-                &format_args!("{}", self.powerup_timer().bits()),
-            )
-            .field(
-                "dg_wrap_wait_timer",
-                &format_args!("{}", self.dg_wrap_wait_timer().bits()),
-            )
-            .field(
-                "dg_wrap_powerup_timer",
-                &format_args!("{}", self.dg_wrap_powerup_timer().bits()),
-            )
+            .field("wait_timer", &self.wait_timer())
+            .field("powerup_timer", &self.powerup_timer())
+            .field("dg_wrap_wait_timer", &self.dg_wrap_wait_timer())
+            .field("dg_wrap_powerup_timer", &self.dg_wrap_powerup_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/timer5.rs b/esp32/src/rtc_cntl/timer5.rs
index eb0d1023d7..bef8298094 100644
--- a/esp32/src/rtc_cntl/timer5.rs
+++ b/esp32/src/rtc_cntl/timer5.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER5")
-            .field(
-                "ulp_cp_subtimer_prediv",
-                &format_args!("{}", self.ulp_cp_subtimer_prediv().bits()),
-            )
-            .field(
-                "min_slp_val",
-                &format_args!("{}", self.min_slp_val().bits()),
-            )
-            .field(
-                "rtcmem_wait_timer",
-                &format_args!("{}", self.rtcmem_wait_timer().bits()),
-            )
-            .field(
-                "rtcmem_powerup_timer",
-                &format_args!("{}", self.rtcmem_powerup_timer().bits()),
-            )
+            .field("ulp_cp_subtimer_prediv", &self.ulp_cp_subtimer_prediv())
+            .field("min_slp_val", &self.min_slp_val())
+            .field("rtcmem_wait_timer", &self.rtcmem_wait_timer())
+            .field("rtcmem_powerup_timer", &self.rtcmem_powerup_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/wakeup_state.rs b/esp32/src/rtc_cntl/wakeup_state.rs
index eab0972559..2ad756c4a0 100644
--- a/esp32/src/rtc_cntl/wakeup_state.rs
+++ b/esp32/src/rtc_cntl/wakeup_state.rs
@@ -33,24 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WAKEUP_STATE")
-            .field(
-                "wakeup_cause",
-                &format_args!("{}", self.wakeup_cause().bits()),
-            )
-            .field("wakeup_ena", &format_args!("{}", self.wakeup_ena().bits()))
-            .field(
-                "gpio_wakeup_filter",
-                &format_args!("{}", self.gpio_wakeup_filter().bit()),
-            )
+            .field("wakeup_cause", &self.wakeup_cause())
+            .field("wakeup_ena", &self.wakeup_ena())
+            .field("gpio_wakeup_filter", &self.gpio_wakeup_filter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WAKEUP_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 11:21 - wakeup enable bitmap"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/wdtconfig0.rs b/esp32/src/rtc_cntl/wdtconfig0.rs
index b4c4ea0ce1..e89bd9e9c2 100644
--- a/esp32/src/rtc_cntl/wdtconfig0.rs
+++ b/esp32/src/rtc_cntl/wdtconfig0.rs
@@ -125,52 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG0")
-            .field(
-                "wdt_pause_in_slp",
-                &format_args!("{}", self.wdt_pause_in_slp().bit()),
-            )
-            .field(
-                "wdt_appcpu_reset_en",
-                &format_args!("{}", self.wdt_appcpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field(
-                "wdt_level_int_en",
-                &format_args!("{}", self.wdt_level_int_en().bit()),
-            )
-            .field(
-                "wdt_edge_int_en",
-                &format_args!("{}", self.wdt_edge_int_en().bit()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_pause_in_slp", &self.wdt_pause_in_slp())
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_level_int_en", &self.wdt_level_int_en())
+            .field("wdt_edge_int_en", &self.wdt_edge_int_en())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - pause WDT in sleep"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/wdtconfig1.rs b/esp32/src/rtc_cntl/wdtconfig1.rs
index 3831c62c3f..3306cd0805 100644
--- a/esp32/src/rtc_cntl/wdtconfig1.rs
+++ b/esp32/src/rtc_cntl/wdtconfig1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG1")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/wdtconfig2.rs b/esp32/src/rtc_cntl/wdtconfig2.rs
index f9a03ad862..458fa94e24 100644
--- a/esp32/src/rtc_cntl/wdtconfig2.rs
+++ b/esp32/src/rtc_cntl/wdtconfig2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG2")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/wdtconfig3.rs b/esp32/src/rtc_cntl/wdtconfig3.rs
index 21a8a4fa73..89393b54eb 100644
--- a/esp32/src/rtc_cntl/wdtconfig3.rs
+++ b/esp32/src/rtc_cntl/wdtconfig3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG3")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/wdtconfig4.rs b/esp32/src/rtc_cntl/wdtconfig4.rs
index 09daf5bc71..31770376ff 100644
--- a/esp32/src/rtc_cntl/wdtconfig4.rs
+++ b/esp32/src/rtc_cntl/wdtconfig4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG4")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/rtc_cntl/wdtwprotect.rs b/esp32/src/rtc_cntl/wdtwprotect.rs
index a985454939..ba3cefc560 100644
--- a/esp32/src/rtc_cntl/wdtwprotect.rs
+++ b/esp32/src/rtc_cntl/wdtwprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTWPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTWPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/rtc_i2c/cmd.rs b/esp32/src/rtc_i2c/cmd.rs
index c4728a599a..1686a7ae81 100644
--- a/esp32/src/rtc_i2c/cmd.rs
+++ b/esp32/src/rtc_i2c/cmd.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("val", &format_args!("{}", self.val().bits()))
-            .field("done", &format_args!("{}", self.done().bit()))
+            .field("val", &self.val())
+            .field("done", &self.done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Command content"]
     #[inline(always)]
diff --git a/esp32/src/rtc_i2c/ctrl.rs b/esp32/src/rtc_i2c/ctrl.rs
index 90967bb35b..3c1b3e378a 100644
--- a/esp32/src/rtc_i2c/ctrl.rs
+++ b/esp32/src/rtc_i2c/ctrl.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field("ms_mode", &format_args!("{}", self.ms_mode().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("ms_mode", &self.ms_mode())
+            .field("trans_start", &self.trans_start())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SDA is push-pull (1) or open-drain (0)"]
     #[inline(always)]
diff --git a/esp32/src/rtc_i2c/data.rs b/esp32/src/rtc_i2c/data.rs
index 1902201042..591adb5ab0 100644
--- a/esp32/src/rtc_i2c/data.rs
+++ b/esp32/src/rtc_i2c/data.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DATA_SPEC;
diff --git a/esp32/src/rtc_i2c/debug_status.rs b/esp32/src/rtc_i2c/debug_status.rs
index e7326e30dd..d883d02022 100644
--- a/esp32/src/rtc_i2c/debug_status.rs
+++ b/esp32/src/rtc_i2c/debug_status.rs
@@ -89,27 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEBUG_STATUS")
-            .field("ack_val", &format_args!("{}", self.ack_val().bit()))
-            .field("slave_rw", &format_args!("{}", self.slave_rw().bit()))
-            .field("timed_out", &format_args!("{}", self.timed_out().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field(
-                "slave_addr_match",
-                &format_args!("{}", self.slave_addr_match().bit()),
-            )
-            .field("byte_trans", &format_args!("{}", self.byte_trans().bit()))
-            .field("main_state", &format_args!("{}", self.main_state().bits()))
-            .field("scl_state", &format_args!("{}", self.scl_state().bits()))
+            .field("ack_val", &self.ack_val())
+            .field("slave_rw", &self.slave_rw())
+            .field("timed_out", &self.timed_out())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("slave_addr_match", &self.slave_addr_match())
+            .field("byte_trans", &self.byte_trans())
+            .field("main_state", &self.main_state())
+            .field("scl_state", &self.scl_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBUG_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The value of an acknowledge signal on the bus"]
     #[inline(always)]
diff --git a/esp32/src/rtc_i2c/int_clr.rs b/esp32/src/rtc_i2c/int_clr.rs
index 2f345654df..c9e462b9bc 100644
--- a/esp32/src/rtc_i2c/int_clr.rs
+++ b/esp32/src/rtc_i2c/int_clr.rs
@@ -46,31 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_CLR")
-            .field(
-                "slave_trans_complete",
-                &format_args!("{}", self.slave_trans_complete().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_trans_complete",
-                &format_args!("{}", self.master_trans_complete().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
+            .field("slave_trans_complete", &self.slave_trans_complete())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_trans_complete", &self.master_trans_complete())
+            .field("trans_complete", &self.trans_complete())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4"]
     #[inline(always)]
diff --git a/esp32/src/rtc_i2c/int_ena.rs b/esp32/src/rtc_i2c/int_ena.rs
index b793533a80..67446e9fe0 100644
--- a/esp32/src/rtc_i2c/int_ena.rs
+++ b/esp32/src/rtc_i2c/int_ena.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ENA_SPEC;
diff --git a/esp32/src/rtc_i2c/int_raw.rs b/esp32/src/rtc_i2c/int_raw.rs
index ae71de0b7f..21943162f7 100644
--- a/esp32/src/rtc_i2c/int_raw.rs
+++ b/esp32/src/rtc_i2c/int_raw.rs
@@ -51,32 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "slave_trans_complete",
-                &format_args!("{}", self.slave_trans_complete().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_trans_complete",
-                &format_args!("{}", self.master_trans_complete().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
+            .field("slave_trans_complete", &self.slave_trans_complete())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_trans_complete", &self.master_trans_complete())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - Slave accepted 1 byte and address matched"]
     #[inline(always)]
diff --git a/esp32/src/rtc_i2c/int_st.rs b/esp32/src/rtc_i2c/int_st.rs
index 39ed180708..55191ddc74 100644
--- a/esp32/src/rtc_i2c/int_st.rs
+++ b/esp32/src/rtc_i2c/int_st.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_st::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
diff --git a/esp32/src/rtc_i2c/scl_high_period.rs b/esp32/src/rtc_i2c/scl_high_period.rs
index 6ae0ed1d08..e819443649 100644
--- a/esp32/src/rtc_i2c/scl_high_period.rs
+++ b/esp32/src/rtc_i2c/scl_high_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH_PERIOD")
-            .field(
-                "scl_high_period",
-                &format_args!("{}", self.scl_high_period().bits()),
-            )
+            .field("scl_high_period", &self.scl_high_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - Number of FAST_CLK cycles for SCL to be high"]
     #[inline(always)]
diff --git a/esp32/src/rtc_i2c/scl_low_period.rs b/esp32/src/rtc_i2c/scl_low_period.rs
index 680c1ddd18..84196a2b83 100644
--- a/esp32/src/rtc_i2c/scl_low_period.rs
+++ b/esp32/src/rtc_i2c/scl_low_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW_PERIOD")
-            .field(
-                "scl_low_period",
-                &format_args!("{}", self.scl_low_period().bits()),
-            )
+            .field("scl_low_period", &self.scl_low_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:24 - number of cycles that scl == 0"]
     #[inline(always)]
diff --git a/esp32/src/rtc_i2c/scl_start_period.rs b/esp32/src/rtc_i2c/scl_start_period.rs
index 39a81a914f..7cfc95b8a6 100644
--- a/esp32/src/rtc_i2c/scl_start_period.rs
+++ b/esp32/src/rtc_i2c/scl_start_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_PERIOD")
-            .field(
-                "scl_start_period",
-                &format_args!("{}", self.scl_start_period().bits()),
-            )
+            .field("scl_start_period", &self.scl_start_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - Number of FAST_CLK cycles to wait before generating start condition"]
     #[inline(always)]
diff --git a/esp32/src/rtc_i2c/scl_stop_period.rs b/esp32/src/rtc_i2c/scl_stop_period.rs
index bc99453ea2..23fb54ed51 100644
--- a/esp32/src/rtc_i2c/scl_stop_period.rs
+++ b/esp32/src/rtc_i2c/scl_stop_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_PERIOD")
-            .field(
-                "scl_stop_period",
-                &format_args!("{}", self.scl_stop_period().bits()),
-            )
+            .field("scl_stop_period", &self.scl_stop_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - Number of FAST_CLK cycles to wait before generating stop condition"]
     #[inline(always)]
diff --git a/esp32/src/rtc_i2c/sda_duty.rs b/esp32/src/rtc_i2c/sda_duty.rs
index c7e84e4a0f..3da7dd229d 100644
--- a/esp32/src/rtc_i2c/sda_duty.rs
+++ b/esp32/src/rtc_i2c/sda_duty.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_DUTY")
-            .field("sda_duty", &format_args!("{}", self.sda_duty().bits()))
+            .field("sda_duty", &self.sda_duty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - Number of FAST_CLK cycles SDA will switch after falling edge of SCL"]
     #[inline(always)]
diff --git a/esp32/src/rtc_i2c/slave_addr.rs b/esp32/src/rtc_i2c/slave_addr.rs
index 7f7ffe7690..8568df2360 100644
--- a/esp32/src/rtc_i2c/slave_addr.rs
+++ b/esp32/src/rtc_i2c/slave_addr.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE_ADDR")
-            .field("slave_addr", &format_args!("{}", self.slave_addr().bits()))
-            .field("_10bit", &format_args!("{}", self._10bit().bit()))
+            .field("slave_addr", &self.slave_addr())
+            .field("_10bit", &self._10bit())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - local slave address"]
     #[inline(always)]
diff --git a/esp32/src/rtc_i2c/timeout.rs b/esp32/src/rtc_i2c/timeout.rs
index 65f194e4c7..e9894bedd6 100644
--- a/esp32/src/rtc_i2c/timeout.rs
+++ b/esp32/src/rtc_i2c/timeout.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMEOUT")
-            .field("timeout", &format_args!("{}", self.timeout().bits()))
+            .field("timeout", &self.timeout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMEOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - Maximum number of FAST_CLK cycles that the transmission can take"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/adc_pad.rs b/esp32/src/rtc_io/adc_pad.rs
index 3df85bf709..ffe7c0269a 100644
--- a/esp32/src/rtc_io/adc_pad.rs
+++ b/esp32/src/rtc_io/adc_pad.rs
@@ -116,45 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADC_PAD")
-            .field("adc2_fun_ie", &format_args!("{}", self.adc2_fun_ie().bit()))
-            .field("adc2_slp_ie", &format_args!("{}", self.adc2_slp_ie().bit()))
-            .field(
-                "adc2_slp_sel",
-                &format_args!("{}", self.adc2_slp_sel().bit()),
-            )
-            .field(
-                "adc2_fun_sel",
-                &format_args!("{}", self.adc2_fun_sel().bits()),
-            )
-            .field("adc1_fun_ie", &format_args!("{}", self.adc1_fun_ie().bit()))
-            .field("adc1_slp_ie", &format_args!("{}", self.adc1_slp_ie().bit()))
-            .field(
-                "adc1_slp_sel",
-                &format_args!("{}", self.adc1_slp_sel().bit()),
-            )
-            .field(
-                "adc1_fun_sel",
-                &format_args!("{}", self.adc1_fun_sel().bits()),
-            )
-            .field(
-                "adc2_mux_sel",
-                &format_args!("{}", self.adc2_mux_sel().bit()),
-            )
-            .field(
-                "adc1_mux_sel",
-                &format_args!("{}", self.adc1_mux_sel().bit()),
-            )
-            .field("adc2_hold", &format_args!("{}", self.adc2_hold().bit()))
-            .field("adc1_hold", &format_args!("{}", self.adc1_hold().bit()))
+            .field("adc2_fun_ie", &self.adc2_fun_ie())
+            .field("adc2_slp_ie", &self.adc2_slp_ie())
+            .field("adc2_slp_sel", &self.adc2_slp_sel())
+            .field("adc2_fun_sel", &self.adc2_fun_sel())
+            .field("adc1_fun_ie", &self.adc1_fun_ie())
+            .field("adc1_slp_ie", &self.adc1_slp_ie())
+            .field("adc1_slp_sel", &self.adc1_slp_sel())
+            .field("adc1_fun_sel", &self.adc1_fun_sel())
+            .field("adc2_mux_sel", &self.adc2_mux_sel())
+            .field("adc1_mux_sel", &self.adc1_mux_sel())
+            .field("adc2_hold", &self.adc2_hold())
+            .field("adc1_hold", &self.adc1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADC_PAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - the input enable of the pad"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/date.rs b/esp32/src/rtc_io/date.rs
index 5da5c412c6..34227eb244 100644
--- a/esp32/src/rtc_io/date.rs
+++ b/esp32/src/rtc_io/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("io_date", &format_args!("{}", self.io_date().bits()))
+            .field("io_date", &self.io_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - date"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/dig_pad_hold.rs b/esp32/src/rtc_io/dig_pad_hold.rs
index ba0aebadb1..581c205437 100644
--- a/esp32/src/rtc_io/dig_pad_hold.rs
+++ b/esp32/src/rtc_io/dig_pad_hold.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIG_PAD_HOLD")
-            .field(
-                "dig_pad_hold",
-                &format_args!("{}", self.dig_pad_hold().bits()),
-            )
+            .field("dig_pad_hold", &self.dig_pad_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIG_PAD_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - select the digital pad hold value."]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/enable.rs b/esp32/src/rtc_io/enable.rs
index 2d46ba5213..ea35b6887b 100644
--- a/esp32/src/rtc_io/enable.rs
+++ b/esp32/src/rtc_io/enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE")
-            .field("enable", &format_args!("{}", self.enable().bits()))
+            .field("enable", &self.enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 14:31 - GPIO0~17 output enable"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/ext_wakeup0.rs b/esp32/src/rtc_io/ext_wakeup0.rs
index 5c457a98ca..e5bc38df77 100644
--- a/esp32/src/rtc_io/ext_wakeup0.rs
+++ b/esp32/src/rtc_io/ext_wakeup0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP0")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 27:31 - select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/hall_sens.rs b/esp32/src/rtc_io/hall_sens.rs
index 59089766c1..aa0b2b8d41 100644
--- a/esp32/src/rtc_io/hall_sens.rs
+++ b/esp32/src/rtc_io/hall_sens.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HALL_SENS")
-            .field("hall_phase", &format_args!("{}", self.hall_phase().bit()))
-            .field("xpd_hall", &format_args!("{}", self.xpd_hall().bit()))
+            .field("hall_phase", &self.hall_phase())
+            .field("xpd_hall", &self.xpd_hall())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HALL_SENS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - Reverse phase of hall sensor"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/in_.rs b/esp32/src/rtc_io/in_.rs
index 20f8df617f..6b6a6b19bf 100644
--- a/esp32/src/rtc_io/in_.rs
+++ b/esp32/src/rtc_io/in_.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("IN")
-            .field("next", &format_args!("{}", self.next().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("IN").field("next", &self.next()).finish()
     }
 }
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/rtc_io/out.rs b/esp32/src/rtc_io/out.rs
index 0be7d8fe10..9b0b5abc53 100644
--- a/esp32/src/rtc_io/out.rs
+++ b/esp32/src/rtc_io/out.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("OUT")
-            .field("data", &format_args!("{}", self.data().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("OUT").field("data", &self.data()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/rtc_io/pad_dac1.rs b/esp32/src/rtc_io/pad_dac1.rs
index 5b4b2c5d60..3e014bd089 100644
--- a/esp32/src/rtc_io/pad_dac1.rs
+++ b/esp32/src/rtc_io/pad_dac1.rs
@@ -125,52 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_DAC1")
-            .field(
-                "pdac1_dac_xpd_force",
-                &format_args!("{}", self.pdac1_dac_xpd_force().bit()),
-            )
-            .field(
-                "pdac1_fun_ie",
-                &format_args!("{}", self.pdac1_fun_ie().bit()),
-            )
-            .field(
-                "pdac1_slp_oe",
-                &format_args!("{}", self.pdac1_slp_oe().bit()),
-            )
-            .field(
-                "pdac1_slp_ie",
-                &format_args!("{}", self.pdac1_slp_ie().bit()),
-            )
-            .field(
-                "pdac1_slp_sel",
-                &format_args!("{}", self.pdac1_slp_sel().bit()),
-            )
-            .field(
-                "pdac1_fun_sel",
-                &format_args!("{}", self.pdac1_fun_sel().bits()),
-            )
-            .field(
-                "pdac1_mux_sel",
-                &format_args!("{}", self.pdac1_mux_sel().bit()),
-            )
-            .field(
-                "pdac1_xpd_dac",
-                &format_args!("{}", self.pdac1_xpd_dac().bit()),
-            )
-            .field("pdac1_dac", &format_args!("{}", self.pdac1_dac().bits()))
-            .field("pdac1_rue", &format_args!("{}", self.pdac1_rue().bit()))
-            .field("pdac1_rde", &format_args!("{}", self.pdac1_rde().bit()))
-            .field("pdac1_hold", &format_args!("{}", self.pdac1_hold().bit()))
-            .field("pdac1_drv", &format_args!("{}", self.pdac1_drv().bits()))
+            .field("pdac1_dac_xpd_force", &self.pdac1_dac_xpd_force())
+            .field("pdac1_fun_ie", &self.pdac1_fun_ie())
+            .field("pdac1_slp_oe", &self.pdac1_slp_oe())
+            .field("pdac1_slp_ie", &self.pdac1_slp_ie())
+            .field("pdac1_slp_sel", &self.pdac1_slp_sel())
+            .field("pdac1_fun_sel", &self.pdac1_fun_sel())
+            .field("pdac1_mux_sel", &self.pdac1_mux_sel())
+            .field("pdac1_xpd_dac", &self.pdac1_xpd_dac())
+            .field("pdac1_dac", &self.pdac1_dac())
+            .field("pdac1_rue", &self.pdac1_rue())
+            .field("pdac1_rde", &self.pdac1_rde())
+            .field("pdac1_hold", &self.pdac1_hold())
+            .field("pdac1_drv", &self.pdac1_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_DAC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 10 - Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/pad_dac2.rs b/esp32/src/rtc_io/pad_dac2.rs
index d4a4e20dbf..5dd71e757d 100644
--- a/esp32/src/rtc_io/pad_dac2.rs
+++ b/esp32/src/rtc_io/pad_dac2.rs
@@ -125,52 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_DAC2")
-            .field(
-                "pdac2_dac_xpd_force",
-                &format_args!("{}", self.pdac2_dac_xpd_force().bit()),
-            )
-            .field(
-                "pdac2_fun_ie",
-                &format_args!("{}", self.pdac2_fun_ie().bit()),
-            )
-            .field(
-                "pdac2_slp_oe",
-                &format_args!("{}", self.pdac2_slp_oe().bit()),
-            )
-            .field(
-                "pdac2_slp_ie",
-                &format_args!("{}", self.pdac2_slp_ie().bit()),
-            )
-            .field(
-                "pdac2_slp_sel",
-                &format_args!("{}", self.pdac2_slp_sel().bit()),
-            )
-            .field(
-                "pdac2_fun_sel",
-                &format_args!("{}", self.pdac2_fun_sel().bits()),
-            )
-            .field(
-                "pdac2_mux_sel",
-                &format_args!("{}", self.pdac2_mux_sel().bit()),
-            )
-            .field(
-                "pdac2_xpd_dac",
-                &format_args!("{}", self.pdac2_xpd_dac().bit()),
-            )
-            .field("pdac2_dac", &format_args!("{}", self.pdac2_dac().bits()))
-            .field("pdac2_rue", &format_args!("{}", self.pdac2_rue().bit()))
-            .field("pdac2_rde", &format_args!("{}", self.pdac2_rde().bit()))
-            .field("pdac2_hold", &format_args!("{}", self.pdac2_hold().bit()))
-            .field("pdac2_drv", &format_args!("{}", self.pdac2_drv().bits()))
+            .field("pdac2_dac_xpd_force", &self.pdac2_dac_xpd_force())
+            .field("pdac2_fun_ie", &self.pdac2_fun_ie())
+            .field("pdac2_slp_oe", &self.pdac2_slp_oe())
+            .field("pdac2_slp_ie", &self.pdac2_slp_ie())
+            .field("pdac2_slp_sel", &self.pdac2_slp_sel())
+            .field("pdac2_fun_sel", &self.pdac2_fun_sel())
+            .field("pdac2_mux_sel", &self.pdac2_mux_sel())
+            .field("pdac2_xpd_dac", &self.pdac2_xpd_dac())
+            .field("pdac2_dac", &self.pdac2_dac())
+            .field("pdac2_rue", &self.pdac2_rue())
+            .field("pdac2_rde", &self.pdac2_rde())
+            .field("pdac2_hold", &self.pdac2_hold())
+            .field("pdac2_drv", &self.pdac2_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_DAC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 10 - Power on DAC2. Usually we need to tristate PDAC2 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/pin.rs b/esp32/src/rtc_io/pin.rs
index 0ff1de97c6..694b69369d 100644
--- a/esp32/src/rtc_io/pin.rs
+++ b/esp32/src/rtc_io/pin.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/rtc_debug_sel.rs b/esp32/src/rtc_io/rtc_debug_sel.rs
index 2deaf55b8d..8d5f19e276 100644
--- a/esp32/src/rtc_io/rtc_debug_sel.rs
+++ b/esp32/src/rtc_io/rtc_debug_sel.rs
@@ -62,24 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_DEBUG_SEL")
-            .field("debug_sel0", &format_args!("{}", self.debug_sel0().bits()))
-            .field("debug_sel1", &format_args!("{}", self.debug_sel1().bits()))
-            .field("debug_sel2", &format_args!("{}", self.debug_sel2().bits()))
-            .field("debug_sel3", &format_args!("{}", self.debug_sel3().bits()))
-            .field("debug_sel4", &format_args!("{}", self.debug_sel4().bits()))
-            .field(
-                "debug_12m_no_gating",
-                &format_args!("{}", self.debug_12m_no_gating().bit()),
-            )
+            .field("debug_sel0", &self.debug_sel0())
+            .field("debug_sel1", &self.debug_sel1())
+            .field("debug_sel2", &self.debug_sel2())
+            .field("debug_sel3", &self.debug_sel3())
+            .field("debug_sel4", &self.debug_sel4())
+            .field("debug_12m_no_gating", &self.debug_12m_no_gating())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_DEBUG_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/sar_i2c_io.rs b/esp32/src/rtc_io/sar_i2c_io.rs
index 7c389b892d..2d39a56a75 100644
--- a/esp32/src/rtc_io/sar_i2c_io.rs
+++ b/esp32/src/rtc_io/sar_i2c_io.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_I2C_IO")
-            .field(
-                "sar_debug_bit_sel",
-                &format_args!("{}", self.sar_debug_bit_sel().bits()),
-            )
-            .field(
-                "sar_i2c_scl_sel",
-                &format_args!("{}", self.sar_i2c_scl_sel().bits()),
-            )
-            .field(
-                "sar_i2c_sda_sel",
-                &format_args!("{}", self.sar_i2c_sda_sel().bits()),
-            )
+            .field("sar_debug_bit_sel", &self.sar_debug_bit_sel())
+            .field("sar_i2c_scl_sel", &self.sar_i2c_scl_sel())
+            .field("sar_i2c_sda_sel", &self.sar_i2c_sda_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_I2C_IO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:27"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/sensor_pads.rs b/esp32/src/rtc_io/sensor_pads.rs
index 362d43529f..9827d9fff5 100644
--- a/esp32/src/rtc_io/sensor_pads.rs
+++ b/esp32/src/rtc_io/sensor_pads.rs
@@ -224,99 +224,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SENSOR_PADS")
-            .field(
-                "sense4_fun_ie",
-                &format_args!("{}", self.sense4_fun_ie().bit()),
-            )
-            .field(
-                "sense4_slp_ie",
-                &format_args!("{}", self.sense4_slp_ie().bit()),
-            )
-            .field(
-                "sense4_slp_sel",
-                &format_args!("{}", self.sense4_slp_sel().bit()),
-            )
-            .field(
-                "sense4_fun_sel",
-                &format_args!("{}", self.sense4_fun_sel().bits()),
-            )
-            .field(
-                "sense3_fun_ie",
-                &format_args!("{}", self.sense3_fun_ie().bit()),
-            )
-            .field(
-                "sense3_slp_ie",
-                &format_args!("{}", self.sense3_slp_ie().bit()),
-            )
-            .field(
-                "sense3_slp_sel",
-                &format_args!("{}", self.sense3_slp_sel().bit()),
-            )
-            .field(
-                "sense3_fun_sel",
-                &format_args!("{}", self.sense3_fun_sel().bits()),
-            )
-            .field(
-                "sense2_fun_ie",
-                &format_args!("{}", self.sense2_fun_ie().bit()),
-            )
-            .field(
-                "sense2_slp_ie",
-                &format_args!("{}", self.sense2_slp_ie().bit()),
-            )
-            .field(
-                "sense2_slp_sel",
-                &format_args!("{}", self.sense2_slp_sel().bit()),
-            )
-            .field(
-                "sense2_fun_sel",
-                &format_args!("{}", self.sense2_fun_sel().bits()),
-            )
-            .field(
-                "sense1_fun_ie",
-                &format_args!("{}", self.sense1_fun_ie().bit()),
-            )
-            .field(
-                "sense1_slp_ie",
-                &format_args!("{}", self.sense1_slp_ie().bit()),
-            )
-            .field(
-                "sense1_slp_sel",
-                &format_args!("{}", self.sense1_slp_sel().bit()),
-            )
-            .field(
-                "sense1_fun_sel",
-                &format_args!("{}", self.sense1_fun_sel().bits()),
-            )
-            .field(
-                "sense4_mux_sel",
-                &format_args!("{}", self.sense4_mux_sel().bit()),
-            )
-            .field(
-                "sense3_mux_sel",
-                &format_args!("{}", self.sense3_mux_sel().bit()),
-            )
-            .field(
-                "sense2_mux_sel",
-                &format_args!("{}", self.sense2_mux_sel().bit()),
-            )
-            .field(
-                "sense1_mux_sel",
-                &format_args!("{}", self.sense1_mux_sel().bit()),
-            )
-            .field("sense4_hold", &format_args!("{}", self.sense4_hold().bit()))
-            .field("sense3_hold", &format_args!("{}", self.sense3_hold().bit()))
-            .field("sense2_hold", &format_args!("{}", self.sense2_hold().bit()))
-            .field("sense1_hold", &format_args!("{}", self.sense1_hold().bit()))
+            .field("sense4_fun_ie", &self.sense4_fun_ie())
+            .field("sense4_slp_ie", &self.sense4_slp_ie())
+            .field("sense4_slp_sel", &self.sense4_slp_sel())
+            .field("sense4_fun_sel", &self.sense4_fun_sel())
+            .field("sense3_fun_ie", &self.sense3_fun_ie())
+            .field("sense3_slp_ie", &self.sense3_slp_ie())
+            .field("sense3_slp_sel", &self.sense3_slp_sel())
+            .field("sense3_fun_sel", &self.sense3_fun_sel())
+            .field("sense2_fun_ie", &self.sense2_fun_ie())
+            .field("sense2_slp_ie", &self.sense2_slp_ie())
+            .field("sense2_slp_sel", &self.sense2_slp_sel())
+            .field("sense2_fun_sel", &self.sense2_fun_sel())
+            .field("sense1_fun_ie", &self.sense1_fun_ie())
+            .field("sense1_slp_ie", &self.sense1_slp_ie())
+            .field("sense1_slp_sel", &self.sense1_slp_sel())
+            .field("sense1_fun_sel", &self.sense1_fun_sel())
+            .field("sense4_mux_sel", &self.sense4_mux_sel())
+            .field("sense3_mux_sel", &self.sense3_mux_sel())
+            .field("sense2_mux_sel", &self.sense2_mux_sel())
+            .field("sense1_mux_sel", &self.sense1_mux_sel())
+            .field("sense4_hold", &self.sense4_hold())
+            .field("sense3_hold", &self.sense3_hold())
+            .field("sense2_hold", &self.sense2_hold())
+            .field("sense1_hold", &self.sense1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SENSOR_PADS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - the input enable of the pad"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/status.rs b/esp32/src/rtc_io/status.rs
index 9fd814c6a8..ecdee48618 100644
--- a/esp32/src/rtc_io/status.rs
+++ b/esp32/src/rtc_io/status.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("STATUS")
-            .field("int", &format_args!("{}", self.int().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("STATUS").field("int", &self.int()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/rtc_io/touch_cfg.rs b/esp32/src/rtc_io/touch_cfg.rs
index d7775e2393..59741ac165 100644
--- a/esp32/src/rtc_io/touch_cfg.rs
+++ b/esp32/src/rtc_io/touch_cfg.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_CFG")
-            .field("touch_dcur", &format_args!("{}", self.touch_dcur().bits()))
-            .field(
-                "touch_drange",
-                &format_args!("{}", self.touch_drange().bits()),
-            )
-            .field(
-                "touch_drefl",
-                &format_args!("{}", self.touch_drefl().bits()),
-            )
-            .field(
-                "touch_drefh",
-                &format_args!("{}", self.touch_drefh().bits()),
-            )
-            .field(
-                "touch_xpd_bias",
-                &format_args!("{}", self.touch_xpd_bias().bit()),
-            )
+            .field("touch_dcur", &self.touch_dcur())
+            .field("touch_drange", &self.touch_drange())
+            .field("touch_drefl", &self.touch_drefl())
+            .field("touch_drefh", &self.touch_drefh())
+            .field("touch_xpd_bias", &self.touch_xpd_bias())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:24 - touch sensor bias current. Should have option to tie with BIAS_SLEEP(When BIAS_SLEEP this setting is available"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/touch_pad0.rs b/esp32/src/rtc_io/touch_pad0.rs
index 63c99d9212..fe9d89b073 100644
--- a/esp32/src/rtc_io/touch_pad0.rs
+++ b/esp32/src/rtc_io/touch_pad0.rs
@@ -143,30 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD0")
-            .field("to_gpio", &format_args!("{}", self.to_gpio().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("dac", &format_args!("{}", self.dac().bits()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
-            .field("hold", &format_args!("{}", self.hold().bit()))
+            .field("to_gpio", &self.to_gpio())
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("dac", &self.dac())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
+            .field("hold", &self.hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/touch_pad1.rs b/esp32/src/rtc_io/touch_pad1.rs
index d8f807fa12..fadd18831c 100644
--- a/esp32/src/rtc_io/touch_pad1.rs
+++ b/esp32/src/rtc_io/touch_pad1.rs
@@ -143,30 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD1")
-            .field("to_gpio", &format_args!("{}", self.to_gpio().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("dac", &format_args!("{}", self.dac().bits()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
-            .field("hold", &format_args!("{}", self.hold().bit()))
+            .field("to_gpio", &self.to_gpio())
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("dac", &self.dac())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
+            .field("hold", &self.hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/touch_pad2.rs b/esp32/src/rtc_io/touch_pad2.rs
index 9f68087fab..91b323caf6 100644
--- a/esp32/src/rtc_io/touch_pad2.rs
+++ b/esp32/src/rtc_io/touch_pad2.rs
@@ -143,30 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD2")
-            .field("to_gpio", &format_args!("{}", self.to_gpio().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("dac", &format_args!("{}", self.dac().bits()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
-            .field("hold", &format_args!("{}", self.hold().bit()))
+            .field("to_gpio", &self.to_gpio())
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("dac", &self.dac())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
+            .field("hold", &self.hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/touch_pad3.rs b/esp32/src/rtc_io/touch_pad3.rs
index b9ace7797c..b9ff5e0e4a 100644
--- a/esp32/src/rtc_io/touch_pad3.rs
+++ b/esp32/src/rtc_io/touch_pad3.rs
@@ -143,30 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD3")
-            .field("to_gpio", &format_args!("{}", self.to_gpio().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("dac", &format_args!("{}", self.dac().bits()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
-            .field("hold", &format_args!("{}", self.hold().bit()))
+            .field("to_gpio", &self.to_gpio())
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("dac", &self.dac())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
+            .field("hold", &self.hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/touch_pad4.rs b/esp32/src/rtc_io/touch_pad4.rs
index 4d52ce1c0b..cb45c6c7f3 100644
--- a/esp32/src/rtc_io/touch_pad4.rs
+++ b/esp32/src/rtc_io/touch_pad4.rs
@@ -143,30 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD4")
-            .field("to_gpio", &format_args!("{}", self.to_gpio().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("dac", &format_args!("{}", self.dac().bits()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
-            .field("hold", &format_args!("{}", self.hold().bit()))
+            .field("to_gpio", &self.to_gpio())
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("dac", &self.dac())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
+            .field("hold", &self.hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/touch_pad5.rs b/esp32/src/rtc_io/touch_pad5.rs
index 59c3904dfe..005408c48b 100644
--- a/esp32/src/rtc_io/touch_pad5.rs
+++ b/esp32/src/rtc_io/touch_pad5.rs
@@ -143,30 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD5")
-            .field("to_gpio", &format_args!("{}", self.to_gpio().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("dac", &format_args!("{}", self.dac().bits()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
-            .field("hold", &format_args!("{}", self.hold().bit()))
+            .field("to_gpio", &self.to_gpio())
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("dac", &self.dac())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
+            .field("hold", &self.hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/touch_pad6.rs b/esp32/src/rtc_io/touch_pad6.rs
index fc3be06532..8022d19c23 100644
--- a/esp32/src/rtc_io/touch_pad6.rs
+++ b/esp32/src/rtc_io/touch_pad6.rs
@@ -143,30 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD6")
-            .field("to_gpio", &format_args!("{}", self.to_gpio().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("dac", &format_args!("{}", self.dac().bits()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
-            .field("hold", &format_args!("{}", self.hold().bit()))
+            .field("to_gpio", &self.to_gpio())
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("dac", &self.dac())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
+            .field("hold", &self.hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/touch_pad7.rs b/esp32/src/rtc_io/touch_pad7.rs
index c28a13294a..8ed1928728 100644
--- a/esp32/src/rtc_io/touch_pad7.rs
+++ b/esp32/src/rtc_io/touch_pad7.rs
@@ -143,30 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD7")
-            .field("to_gpio", &format_args!("{}", self.to_gpio().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("dac", &format_args!("{}", self.dac().bits()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
-            .field("hold", &format_args!("{}", self.hold().bit()))
+            .field("to_gpio", &self.to_gpio())
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("dac", &self.dac())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
+            .field("hold", &self.hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/touch_pad8.rs b/esp32/src/rtc_io/touch_pad8.rs
index a927e481e3..56556724fa 100644
--- a/esp32/src/rtc_io/touch_pad8.rs
+++ b/esp32/src/rtc_io/touch_pad8.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD8")
-            .field("to_gpio", &format_args!("{}", self.to_gpio().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("dac", &format_args!("{}", self.dac().bits()))
+            .field("to_gpio", &self.to_gpio())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("dac", &self.dac())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 19 - connect the rtc pad input to digital pad input Ó0Ó is availbale"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/touch_pad9.rs b/esp32/src/rtc_io/touch_pad9.rs
index 947d42b5c6..c401aa61b2 100644
--- a/esp32/src/rtc_io/touch_pad9.rs
+++ b/esp32/src/rtc_io/touch_pad9.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD9")
-            .field("to_gpio", &format_args!("{}", self.to_gpio().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("dac", &format_args!("{}", self.dac().bits()))
+            .field("to_gpio", &self.to_gpio())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("dac", &self.dac())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 19 - connect the rtc pad input to digital pad input Ó0Ó is availbale"]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/xtal_32k_pad.rs b/esp32/src/rtc_io/xtal_32k_pad.rs
index cc0cd14321..52c655cf4a 100644
--- a/esp32/src/rtc_io/xtal_32k_pad.rs
+++ b/esp32/src/rtc_io/xtal_32k_pad.rs
@@ -224,69 +224,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL_32K_PAD")
-            .field(
-                "dbias_xtal_32k",
-                &format_args!("{}", self.dbias_xtal_32k().bits()),
-            )
-            .field(
-                "dres_xtal_32k",
-                &format_args!("{}", self.dres_xtal_32k().bits()),
-            )
-            .field("x32p_fun_ie", &format_args!("{}", self.x32p_fun_ie().bit()))
-            .field("x32p_slp_oe", &format_args!("{}", self.x32p_slp_oe().bit()))
-            .field("x32p_slp_ie", &format_args!("{}", self.x32p_slp_ie().bit()))
-            .field(
-                "x32p_slp_sel",
-                &format_args!("{}", self.x32p_slp_sel().bit()),
-            )
-            .field(
-                "x32p_fun_sel",
-                &format_args!("{}", self.x32p_fun_sel().bits()),
-            )
-            .field("x32n_fun_ie", &format_args!("{}", self.x32n_fun_ie().bit()))
-            .field("x32n_slp_oe", &format_args!("{}", self.x32n_slp_oe().bit()))
-            .field("x32n_slp_ie", &format_args!("{}", self.x32n_slp_ie().bit()))
-            .field(
-                "x32n_slp_sel",
-                &format_args!("{}", self.x32n_slp_sel().bit()),
-            )
-            .field(
-                "x32n_fun_sel",
-                &format_args!("{}", self.x32n_fun_sel().bits()),
-            )
-            .field(
-                "x32p_mux_sel",
-                &format_args!("{}", self.x32p_mux_sel().bit()),
-            )
-            .field(
-                "x32n_mux_sel",
-                &format_args!("{}", self.x32n_mux_sel().bit()),
-            )
-            .field(
-                "xpd_xtal_32k",
-                &format_args!("{}", self.xpd_xtal_32k().bit()),
-            )
-            .field(
-                "dac_xtal_32k",
-                &format_args!("{}", self.dac_xtal_32k().bits()),
-            )
-            .field("x32p_rue", &format_args!("{}", self.x32p_rue().bit()))
-            .field("x32p_rde", &format_args!("{}", self.x32p_rde().bit()))
-            .field("x32p_hold", &format_args!("{}", self.x32p_hold().bit()))
-            .field("x32p_drv", &format_args!("{}", self.x32p_drv().bits()))
-            .field("x32n_rue", &format_args!("{}", self.x32n_rue().bit()))
-            .field("x32n_rde", &format_args!("{}", self.x32n_rde().bit()))
-            .field("x32n_hold", &format_args!("{}", self.x32n_hold().bit()))
-            .field("x32n_drv", &format_args!("{}", self.x32n_drv().bits()))
+            .field("dbias_xtal_32k", &self.dbias_xtal_32k())
+            .field("dres_xtal_32k", &self.dres_xtal_32k())
+            .field("x32p_fun_ie", &self.x32p_fun_ie())
+            .field("x32p_slp_oe", &self.x32p_slp_oe())
+            .field("x32p_slp_ie", &self.x32p_slp_ie())
+            .field("x32p_slp_sel", &self.x32p_slp_sel())
+            .field("x32p_fun_sel", &self.x32p_fun_sel())
+            .field("x32n_fun_ie", &self.x32n_fun_ie())
+            .field("x32n_slp_oe", &self.x32n_slp_oe())
+            .field("x32n_slp_ie", &self.x32n_slp_ie())
+            .field("x32n_slp_sel", &self.x32n_slp_sel())
+            .field("x32n_fun_sel", &self.x32n_fun_sel())
+            .field("x32p_mux_sel", &self.x32p_mux_sel())
+            .field("x32n_mux_sel", &self.x32n_mux_sel())
+            .field("xpd_xtal_32k", &self.xpd_xtal_32k())
+            .field("dac_xtal_32k", &self.dac_xtal_32k())
+            .field("x32p_rue", &self.x32p_rue())
+            .field("x32p_rde", &self.x32p_rde())
+            .field("x32p_hold", &self.x32p_hold())
+            .field("x32p_drv", &self.x32p_drv())
+            .field("x32n_rue", &self.x32n_rue())
+            .field("x32n_rde", &self.x32n_rde())
+            .field("x32n_hold", &self.x32n_hold())
+            .field("x32n_drv", &self.x32n_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL_32K_PAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 1:2 - 32K XTAL self-bias reference control."]
     #[inline(always)]
diff --git a/esp32/src/rtc_io/xtl_ext_ctr.rs b/esp32/src/rtc_io/xtl_ext_ctr.rs
index 7b2fe166ea..2c59dd807a 100644
--- a/esp32/src/rtc_io/xtl_ext_ctr.rs
+++ b/esp32/src/rtc_io/xtl_ext_ctr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTL_EXT_CTR")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTL_EXT_CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 27:31 - select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17"]
     #[inline(always)]
diff --git a/esp32/src/sdhost/blksiz.rs b/esp32/src/sdhost/blksiz.rs
index 661464ff62..cc43139dce 100644
--- a/esp32/src/sdhost/blksiz.rs
+++ b/esp32/src/sdhost/blksiz.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLKSIZ")
-            .field("block_size", &format_args!("{}", self.block_size().bits()))
+            .field("block_size", &self.block_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLKSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Block size."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/bmod.rs b/esp32/src/sdhost/bmod.rs
index 84e024e84c..40bf525ef2 100644
--- a/esp32/src/sdhost/bmod.rs
+++ b/esp32/src/sdhost/bmod.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BMOD")
-            .field("swr", &format_args!("{}", self.swr().bit()))
-            .field("fb", &format_args!("{}", self.fb().bit()))
-            .field("de", &format_args!("{}", self.de().bit()))
-            .field("pbl", &format_args!("{}", self.pbl().bits()))
+            .field("swr", &self.swr())
+            .field("fb", &self.fb())
+            .field("de", &self.de())
+            .field("pbl", &self.pbl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BMOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/bufaddr.rs b/esp32/src/sdhost/bufaddr.rs
index 720082ccb4..432972a890 100644
--- a/esp32/src/sdhost/bufaddr.rs
+++ b/esp32/src/sdhost/bufaddr.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUFADDR")
-            .field("bufaddr", &format_args!("{}", self.bufaddr().bits()))
+            .field("bufaddr", &self.bufaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUFADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Host buffer address pointer register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bufaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUFADDR_SPEC;
 impl crate::RegisterSpec for BUFADDR_SPEC {
diff --git a/esp32/src/sdhost/buffifo.rs b/esp32/src/sdhost/buffifo.rs
index fad83364df..75e09b3936 100644
--- a/esp32/src/sdhost/buffifo.rs
+++ b/esp32/src/sdhost/buffifo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUFFIFO")
-            .field("buffifo", &format_args!("{}", self.buffifo().bits()))
+            .field("buffifo", &self.buffifo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUFFIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - CPU write and read transmit data by FIFO. This register points to the current Data FIFO ."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/bytcnt.rs b/esp32/src/sdhost/bytcnt.rs
index af93408fdf..fed252d44c 100644
--- a/esp32/src/sdhost/bytcnt.rs
+++ b/esp32/src/sdhost/bytcnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BYTCNT")
-            .field("byte_count", &format_args!("{}", self.byte_count().bits()))
+            .field("byte_count", &self.byte_count())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BYTCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/cardthrctl.rs b/esp32/src/sdhost/cardthrctl.rs
index 9273aba36f..b1a29d375d 100644
--- a/esp32/src/sdhost/cardthrctl.rs
+++ b/esp32/src/sdhost/cardthrctl.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CARDTHRCTL")
-            .field("cardrdthren", &format_args!("{}", self.cardrdthren().bit()))
-            .field(
-                "cardclrinten",
-                &format_args!("{}", self.cardclrinten().bit()),
-            )
-            .field("cardwrthren", &format_args!("{}", self.cardwrthren().bit()))
-            .field(
-                "cardthreshold",
-                &format_args!("{}", self.cardthreshold().bits()),
-            )
+            .field("cardrdthren", &self.cardrdthren())
+            .field("cardclrinten", &self.cardclrinten())
+            .field("cardwrthren", &self.cardwrthren())
+            .field("cardthreshold", &self.cardthreshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CARDTHRCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Card read threshold enable. 1'b0-Card read threshold disabled. 1'b1-Card read threshold enabled."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/cdetect.rs b/esp32/src/sdhost/cdetect.rs
index b8c669a95b..e9df01474b 100644
--- a/esp32/src/sdhost/cdetect.rs
+++ b/esp32/src/sdhost/cdetect.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CDETECT")
-            .field(
-                "card_detect_n",
-                &format_args!("{}", self.card_detect_n().bits()),
-            )
+            .field("card_detect_n", &self.card_detect_n())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CDETECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Card detect register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cdetect::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CDETECT_SPEC;
 impl crate::RegisterSpec for CDETECT_SPEC {
diff --git a/esp32/src/sdhost/clk_edge_sel.rs b/esp32/src/sdhost/clk_edge_sel.rs
index 78eb8dc746..5b20d9bb0a 100644
--- a/esp32/src/sdhost/clk_edge_sel.rs
+++ b/esp32/src/sdhost/clk_edge_sel.rs
@@ -89,42 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EDGE_SEL")
-            .field(
-                "cclkin_edge_drv_sel",
-                &format_args!("{}", self.cclkin_edge_drv_sel().bits()),
-            )
-            .field(
-                "cclkin_edge_sam_sel",
-                &format_args!("{}", self.cclkin_edge_sam_sel().bits()),
-            )
-            .field(
-                "cclkin_edge_slf_sel",
-                &format_args!("{}", self.cclkin_edge_slf_sel().bits()),
-            )
-            .field(
-                "ccllkin_edge_h",
-                &format_args!("{}", self.ccllkin_edge_h().bits()),
-            )
-            .field(
-                "ccllkin_edge_l",
-                &format_args!("{}", self.ccllkin_edge_l().bits()),
-            )
-            .field(
-                "ccllkin_edge_n",
-                &format_args!("{}", self.ccllkin_edge_n().bits()),
-            )
-            .field("esdio_mode", &format_args!("{}", self.esdio_mode().bit()))
-            .field("esd_mode", &format_args!("{}", self.esd_mode().bit()))
-            .field("cclk_en", &format_args!("{}", self.cclk_en().bit()))
+            .field("cclkin_edge_drv_sel", &self.cclkin_edge_drv_sel())
+            .field("cclkin_edge_sam_sel", &self.cclkin_edge_sam_sel())
+            .field("cclkin_edge_slf_sel", &self.cclkin_edge_slf_sel())
+            .field("ccllkin_edge_h", &self.ccllkin_edge_h())
+            .field("ccllkin_edge_l", &self.ccllkin_edge_l())
+            .field("ccllkin_edge_n", &self.ccllkin_edge_n())
+            .field("esdio_mode", &self.esdio_mode())
+            .field("esd_mode", &self.esd_mode())
+            .field("cclk_en", &self.cclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EDGE_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/clkdiv.rs b/esp32/src/sdhost/clkdiv.rs
index 1f025bc3a7..ecb1a5c6e4 100644
--- a/esp32/src/sdhost/clkdiv.rs
+++ b/esp32/src/sdhost/clkdiv.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKDIV")
-            .field(
-                "clk_divider0",
-                &format_args!("{}", self.clk_divider0().bits()),
-            )
-            .field(
-                "clk_divider1",
-                &format_args!("{}", self.clk_divider1().bits()),
-            )
-            .field(
-                "clk_divider2",
-                &format_args!("{}", self.clk_divider2().bits()),
-            )
-            .field(
-                "clk_divider3",
-                &format_args!("{}", self.clk_divider3().bits()),
-            )
+            .field("clk_divider0", &self.clk_divider0())
+            .field("clk_divider1", &self.clk_divider1())
+            .field("clk_divider2", &self.clk_divider2())
+            .field("clk_divider3", &self.clk_divider3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKDIV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/clkena.rs b/esp32/src/sdhost/clkena.rs
index b9ab1045ee..9c066422e5 100644
--- a/esp32/src/sdhost/clkena.rs
+++ b/esp32/src/sdhost/clkena.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKENA")
-            .field(
-                "cclk_enable",
-                &format_args!("{}", self.cclk_enable().bits()),
-            )
-            .field("lp_enable", &format_args!("{}", self.lp_enable().bits()))
+            .field("cclk_enable", &self.cclk_enable())
+            .field("lp_enable", &self.lp_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. 0: Clock disabled; 1: Clock enabled."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/clksrc.rs b/esp32/src/sdhost/clksrc.rs
index 4e506db40d..c65f699e31 100644
--- a/esp32/src/sdhost/clksrc.rs
+++ b/esp32/src/sdhost/clksrc.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKSRC")
-            .field("clksrc", &format_args!("{}", self.clksrc().bits()))
+            .field("clksrc", &self.clksrc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKSRC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/cmd.rs b/esp32/src/sdhost/cmd.rs
index 8b4fddb7df..83e946ce37 100644
--- a/esp32/src/sdhost/cmd.rs
+++ b/esp32/src/sdhost/cmd.rs
@@ -161,71 +161,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("index", &format_args!("{}", self.index().bits()))
-            .field(
-                "response_expect",
-                &format_args!("{}", self.response_expect().bit()),
-            )
-            .field(
-                "response_length",
-                &format_args!("{}", self.response_length().bit()),
-            )
-            .field(
-                "check_response_crc",
-                &format_args!("{}", self.check_response_crc().bit()),
-            )
-            .field(
-                "data_expected",
-                &format_args!("{}", self.data_expected().bit()),
-            )
-            .field("read_write", &format_args!("{}", self.read_write().bit()))
-            .field(
-                "transfer_mode",
-                &format_args!("{}", self.transfer_mode().bit()),
-            )
-            .field(
-                "send_auto_stop",
-                &format_args!("{}", self.send_auto_stop().bit()),
-            )
-            .field(
-                "wait_prvdata_complete",
-                &format_args!("{}", self.wait_prvdata_complete().bit()),
-            )
-            .field(
-                "stop_abort_cmd",
-                &format_args!("{}", self.stop_abort_cmd().bit()),
-            )
-            .field(
-                "send_initialization",
-                &format_args!("{}", self.send_initialization().bit()),
-            )
-            .field(
-                "card_number",
-                &format_args!("{}", self.card_number().bits()),
-            )
+            .field("index", &self.index())
+            .field("response_expect", &self.response_expect())
+            .field("response_length", &self.response_length())
+            .field("check_response_crc", &self.check_response_crc())
+            .field("data_expected", &self.data_expected())
+            .field("read_write", &self.read_write())
+            .field("transfer_mode", &self.transfer_mode())
+            .field("send_auto_stop", &self.send_auto_stop())
+            .field("wait_prvdata_complete", &self.wait_prvdata_complete())
+            .field("stop_abort_cmd", &self.stop_abort_cmd())
+            .field("send_initialization", &self.send_initialization())
+            .field("card_number", &self.card_number())
             .field(
                 "update_clock_registers_only",
-                &format_args!("{}", self.update_clock_registers_only().bit()),
+                &self.update_clock_registers_only(),
             )
-            .field(
-                "read_ceata_device",
-                &format_args!("{}", self.read_ceata_device().bit()),
-            )
-            .field(
-                "ccs_expected",
-                &format_args!("{}", self.ccs_expected().bit()),
-            )
-            .field("use_hole", &format_args!("{}", self.use_hole().bit()))
-            .field("start_cmd", &format_args!("{}", self.start_cmd().bit()))
+            .field("read_ceata_device", &self.read_ceata_device())
+            .field("ccs_expected", &self.ccs_expected())
+            .field("use_hole", &self.use_hole())
+            .field("start_cmd", &self.start_cmd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Command index."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/cmdarg.rs b/esp32/src/sdhost/cmdarg.rs
index db8f85bd5c..94ac7da52a 100644
--- a/esp32/src/sdhost/cmdarg.rs
+++ b/esp32/src/sdhost/cmdarg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMDARG")
-            .field("cmdarg", &format_args!("{}", self.cmdarg().bits()))
+            .field("cmdarg", &self.cmdarg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMDARG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Value indicates command argument to be passed to the card."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/ctrl.rs b/esp32/src/sdhost/ctrl.rs
index f0e1ff619d..e9544443a1 100644
--- a/esp32/src/sdhost/ctrl.rs
+++ b/esp32/src/sdhost/ctrl.rs
@@ -98,40 +98,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field(
-                "controller_reset",
-                &format_args!("{}", self.controller_reset().bit()),
-            )
-            .field("fifo_reset", &format_args!("{}", self.fifo_reset().bit()))
-            .field("dma_reset", &format_args!("{}", self.dma_reset().bit()))
-            .field("int_enable", &format_args!("{}", self.int_enable().bit()))
-            .field("read_wait", &format_args!("{}", self.read_wait().bit()))
-            .field(
-                "send_irq_response",
-                &format_args!("{}", self.send_irq_response().bit()),
-            )
-            .field(
-                "abort_read_data",
-                &format_args!("{}", self.abort_read_data().bit()),
-            )
-            .field("send_ccsd", &format_args!("{}", self.send_ccsd().bit()))
-            .field(
-                "send_auto_stop_ccsd",
-                &format_args!("{}", self.send_auto_stop_ccsd().bit()),
-            )
+            .field("controller_reset", &self.controller_reset())
+            .field("fifo_reset", &self.fifo_reset())
+            .field("dma_reset", &self.dma_reset())
+            .field("int_enable", &self.int_enable())
+            .field("read_wait", &self.read_wait())
+            .field("send_irq_response", &self.send_irq_response())
+            .field("abort_read_data", &self.abort_read_data())
+            .field("send_ccsd", &self.send_ccsd())
+            .field("send_auto_stop_ccsd", &self.send_auto_stop_ccsd())
             .field(
                 "ceata_device_interrupt_status",
-                &format_args!("{}", self.ceata_device_interrupt_status().bit()),
+                &self.ceata_device_interrupt_status(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/ctype.rs b/esp32/src/sdhost/ctype.rs
index 3d50d29f24..55173aecd3 100644
--- a/esp32/src/sdhost/ctype.rs
+++ b/esp32/src/sdhost/ctype.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTYPE")
-            .field(
-                "card_width4",
-                &format_args!("{}", self.card_width4().bits()),
-            )
-            .field(
-                "card_width8",
-                &format_args!("{}", self.card_width8().bits()),
-            )
+            .field("card_width4", &self.card_width4())
+            .field("card_width8", &self.card_width8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTYPE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit\\[1:0\\] correspond to card\\[1:0\\] respectively."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/dbaddr.rs b/esp32/src/sdhost/dbaddr.rs
index ea5fb55c53..3866cfa354 100644
--- a/esp32/src/sdhost/dbaddr.rs
+++ b/esp32/src/sdhost/dbaddr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBADDR")
-            .field("dbaddr", &format_args!("{}", self.dbaddr().bits()))
+            .field("dbaddr", &self.dbaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits \\[1:0\\] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/debnce.rs b/esp32/src/sdhost/debnce.rs
index a7f179fe77..022482c4a3 100644
--- a/esp32/src/sdhost/debnce.rs
+++ b/esp32/src/sdhost/debnce.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEBNCE")
-            .field(
-                "debounce_count",
-                &format_args!("{}", self.debounce_count().bits()),
-            )
+            .field("debounce_count", &self.debounce_count())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBNCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/dscaddr.rs b/esp32/src/sdhost/dscaddr.rs
index a8b43628b2..0e5e74f7e0 100644
--- a/esp32/src/sdhost/dscaddr.rs
+++ b/esp32/src/sdhost/dscaddr.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSCADDR")
-            .field("dscaddr", &format_args!("{}", self.dscaddr().bits()))
+            .field("dscaddr", &self.dscaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSCADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Host descriptor address pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dscaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DSCADDR_SPEC;
 impl crate::RegisterSpec for DSCADDR_SPEC {
diff --git a/esp32/src/sdhost/emmcddr.rs b/esp32/src/sdhost/emmcddr.rs
index a7905808ae..c09a8b9611 100644
--- a/esp32/src/sdhost/emmcddr.rs
+++ b/esp32/src/sdhost/emmcddr.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMMCDDR")
-            .field(
-                "halfstartbit",
-                &format_args!("{}", self.halfstartbit().bits()),
-            )
-            .field("hs400_mode", &format_args!("{}", self.hs400_mode().bit()))
+            .field("halfstartbit", &self.halfstartbit())
+            .field("hs400_mode", &self.hs400_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMMCDDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: 1'b0-Full cycle. 1'b1-less than one full cycle."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/enshift.rs b/esp32/src/sdhost/enshift.rs
index fb0f2357dc..5f8e486fda 100644
--- a/esp32/src/sdhost/enshift.rs
+++ b/esp32/src/sdhost/enshift.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENSHIFT")
-            .field(
-                "enable_shift",
-                &format_args!("{}", self.enable_shift().bits()),
-            )
+            .field("enable_shift", &self.enable_shift())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENSHIFT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. 2'b00-Default phase shift. 2'b01-Enables shifted to next immediate positive edge. 2'b10-Enables shifted to next immediate negative edge. 2'b11-Reserved."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/fifoth.rs b/esp32/src/sdhost/fifoth.rs
index b0e03f0226..735765f001 100644
--- a/esp32/src/sdhost/fifoth.rs
+++ b/esp32/src/sdhost/fifoth.rs
@@ -35,21 +35,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFOTH")
-            .field("tx_wmark", &format_args!("{}", self.tx_wmark().bits()))
-            .field("rx_wmark", &format_args!("{}", self.rx_wmark().bits()))
+            .field("tx_wmark", &self.tx_wmark())
+            .field("rx_wmark", &self.rx_wmark())
             .field(
                 "dma_multiple_transaction_size",
-                &format_args!("{}", self.dma_multiple_transaction_size().bits()),
+                &self.dma_multiple_transaction_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFOTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/hcon.rs b/esp32/src/sdhost/hcon.rs
index 0200e41188..f7790404e1 100644
--- a/esp32/src/sdhost/hcon.rs
+++ b/esp32/src/sdhost/hcon.rs
@@ -69,27 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HCON")
-            .field("card_type", &format_args!("{}", self.card_type().bit()))
-            .field("card_num", &format_args!("{}", self.card_num().bits()))
-            .field("bus_type", &format_args!("{}", self.bus_type().bit()))
-            .field("data_width", &format_args!("{}", self.data_width().bits()))
-            .field("addr_width", &format_args!("{}", self.addr_width().bits()))
-            .field("dma_width", &format_args!("{}", self.dma_width().bits()))
-            .field("ram_indise", &format_args!("{}", self.ram_indise().bit()))
-            .field("hold", &format_args!("{}", self.hold().bit()))
-            .field(
-                "num_clk_div",
-                &format_args!("{}", self.num_clk_div().bits()),
-            )
+            .field("card_type", &self.card_type())
+            .field("card_num", &self.card_num())
+            .field("bus_type", &self.bus_type())
+            .field("data_width", &self.data_width())
+            .field("addr_width", &self.addr_width())
+            .field("dma_width", &self.dma_width())
+            .field("ram_indise", &self.ram_indise())
+            .field("hold", &self.hold())
+            .field("num_clk_div", &self.num_clk_div())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HCON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Hardware feature register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcon::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HCON_SPEC;
 impl crate::RegisterSpec for HCON_SPEC {
diff --git a/esp32/src/sdhost/idinten.rs b/esp32/src/sdhost/idinten.rs
index 7998f81685..709ad85941 100644
--- a/esp32/src/sdhost/idinten.rs
+++ b/esp32/src/sdhost/idinten.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDINTEN")
-            .field("ti", &format_args!("{}", self.ti().bit()))
-            .field("ri", &format_args!("{}", self.ri().bit()))
-            .field("fbe", &format_args!("{}", self.fbe().bit()))
-            .field("du", &format_args!("{}", self.du().bit()))
-            .field("ces", &format_args!("{}", self.ces().bit()))
-            .field("ni", &format_args!("{}", self.ni().bit()))
-            .field("ai", &format_args!("{}", self.ai().bit()))
+            .field("ti", &self.ti())
+            .field("ri", &self.ri())
+            .field("fbe", &self.fbe())
+            .field("du", &self.du())
+            .field("ces", &self.ces())
+            .field("ni", &self.ni())
+            .field("ai", &self.ai())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDINTEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/idsts.rs b/esp32/src/sdhost/idsts.rs
index c4d4f42dcc..a3de143483 100644
--- a/esp32/src/sdhost/idsts.rs
+++ b/esp32/src/sdhost/idsts.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDSTS")
-            .field("ti", &format_args!("{}", self.ti().bit()))
-            .field("ri", &format_args!("{}", self.ri().bit()))
-            .field("fbe", &format_args!("{}", self.fbe().bit()))
-            .field("du", &format_args!("{}", self.du().bit()))
-            .field("ces", &format_args!("{}", self.ces().bit()))
-            .field("nis", &format_args!("{}", self.nis().bit()))
-            .field("ais", &format_args!("{}", self.ais().bit()))
-            .field("fbe_code", &format_args!("{}", self.fbe_code().bits()))
-            .field("fsm", &format_args!("{}", self.fsm().bits()))
+            .field("ti", &self.ti())
+            .field("ri", &self.ri())
+            .field("fbe", &self.fbe())
+            .field("du", &self.du())
+            .field("ces", &self.ces())
+            .field("nis", &self.nis())
+            .field("ais", &self.ais())
+            .field("fbe_code", &self.fbe_code())
+            .field("fsm", &self.fsm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/intmask.rs b/esp32/src/sdhost/intmask.rs
index d19916144a..c55d4e7c79 100644
--- a/esp32/src/sdhost/intmask.rs
+++ b/esp32/src/sdhost/intmask.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTMASK")
-            .field("int_mask", &format_args!("{}", self.int_mask().bits()))
-            .field(
-                "sdio_int_mask",
-                &format_args!("{}", self.sdio_int_mask().bits()),
-            )
+            .field("int_mask", &self.int_mask())
+            .field("sdio_int_mask", &self.sdio_int_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTMASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): Rx Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation-by-host timeout; Bit 9 (DRTO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/mintsts.rs b/esp32/src/sdhost/mintsts.rs
index ce1a8af58f..4f907e6f71 100644
--- a/esp32/src/sdhost/mintsts.rs
+++ b/esp32/src/sdhost/mintsts.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MINTSTS")
-            .field(
-                "int_status_msk",
-                &format_args!("{}", self.int_status_msk().bits()),
-            )
-            .field(
-                "sdio_interrupt_msk",
-                &format_args!("{}", self.sdio_interrupt_msk().bits()),
-            )
+            .field("int_status_msk", &self.int_status_msk())
+            .field("sdio_interrupt_msk", &self.sdio_interrupt_msk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MINTSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mintsts::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MINTSTS_SPEC;
 impl crate::RegisterSpec for MINTSTS_SPEC {
diff --git a/esp32/src/sdhost/resp0.rs b/esp32/src/sdhost/resp0.rs
index 1b4aa21517..9ff09e1a06 100644
--- a/esp32/src/sdhost/resp0.rs
+++ b/esp32/src/sdhost/resp0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESP0")
-            .field("response0", &format_args!("{}", self.response0().bits()))
+            .field("response0", &self.response0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESP0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESP0_SPEC;
 impl crate::RegisterSpec for RESP0_SPEC {
diff --git a/esp32/src/sdhost/resp1.rs b/esp32/src/sdhost/resp1.rs
index 1b69601dd9..f7356973c4 100644
--- a/esp32/src/sdhost/resp1.rs
+++ b/esp32/src/sdhost/resp1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESP1")
-            .field("response1", &format_args!("{}", self.response1().bits()))
+            .field("response1", &self.response1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Long response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESP1_SPEC;
 impl crate::RegisterSpec for RESP1_SPEC {
diff --git a/esp32/src/sdhost/resp2.rs b/esp32/src/sdhost/resp2.rs
index 1a43d9001f..178a098e32 100644
--- a/esp32/src/sdhost/resp2.rs
+++ b/esp32/src/sdhost/resp2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESP2")
-            .field("response2", &format_args!("{}", self.response2().bits()))
+            .field("response2", &self.response2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESP2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Long response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESP2_SPEC;
 impl crate::RegisterSpec for RESP2_SPEC {
diff --git a/esp32/src/sdhost/resp3.rs b/esp32/src/sdhost/resp3.rs
index 73432f9173..b73efbf947 100644
--- a/esp32/src/sdhost/resp3.rs
+++ b/esp32/src/sdhost/resp3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESP3")
-            .field("response3", &format_args!("{}", self.response3().bits()))
+            .field("response3", &self.response3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESP3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Long response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESP3_SPEC;
 impl crate::RegisterSpec for RESP3_SPEC {
diff --git a/esp32/src/sdhost/rintsts.rs b/esp32/src/sdhost/rintsts.rs
index 25724778fc..ead4f84f3d 100644
--- a/esp32/src/sdhost/rintsts.rs
+++ b/esp32/src/sdhost/rintsts.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RINTSTS")
-            .field(
-                "int_status_raw",
-                &format_args!("{}", self.int_status_raw().bits()),
-            )
-            .field(
-                "sdio_interrupt_raw",
-                &format_args!("{}", self.sdio_interrupt_raw().bits()),
-            )
+            .field("int_status_raw", &self.int_status_raw())
+            .field("sdio_interrupt_raw", &self.sdio_interrupt_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RINTSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/rst_n.rs b/esp32/src/sdhost/rst_n.rs
index d4fad96220..515c3ad743 100644
--- a/esp32/src/sdhost/rst_n.rs
+++ b/esp32/src/sdhost/rst_n.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RST_N")
-            .field("card_reset", &format_args!("{}", self.card_reset().bits()))
+            .field("card_reset", &self.card_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RST_N_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Hardware reset. 1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET\\[0\\] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET\\[1\\] should be set to 1'b0 to reset card1."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/status.rs b/esp32/src/sdhost/status.rs
index a4ae56c313..ef268c61e4 100644
--- a/esp32/src/sdhost/status.rs
+++ b/esp32/src/sdhost/status.rs
@@ -76,43 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field(
-                "fifo_rx_watermark",
-                &format_args!("{}", self.fifo_rx_watermark().bit()),
-            )
-            .field(
-                "fifo_tx_watermark",
-                &format_args!("{}", self.fifo_tx_watermark().bit()),
-            )
-            .field("fifo_empty", &format_args!("{}", self.fifo_empty().bit()))
-            .field("fifo_full", &format_args!("{}", self.fifo_full().bit()))
-            .field(
-                "command_fsm_states",
-                &format_args!("{}", self.command_fsm_states().bits()),
-            )
-            .field(
-                "data_3_status",
-                &format_args!("{}", self.data_3_status().bit()),
-            )
-            .field("data_busy", &format_args!("{}", self.data_busy().bit()))
-            .field(
-                "data_state_mc_busy",
-                &format_args!("{}", self.data_state_mc_busy().bit()),
-            )
-            .field(
-                "response_index",
-                &format_args!("{}", self.response_index().bits()),
-            )
-            .field("fifo_count", &format_args!("{}", self.fifo_count().bits()))
+            .field("fifo_rx_watermark", &self.fifo_rx_watermark())
+            .field("fifo_tx_watermark", &self.fifo_tx_watermark())
+            .field("fifo_empty", &self.fifo_empty())
+            .field("fifo_full", &self.fifo_full())
+            .field("command_fsm_states", &self.command_fsm_states())
+            .field("data_3_status", &self.data_3_status())
+            .field("data_busy", &self.data_busy())
+            .field("data_state_mc_busy", &self.data_state_mc_busy())
+            .field("response_index", &self.response_index())
+            .field("fifo_count", &self.fifo_count())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SD/MMC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32/src/sdhost/tbbcnt.rs b/esp32/src/sdhost/tbbcnt.rs
index 410acd8cd8..bb4ac6ca03 100644
--- a/esp32/src/sdhost/tbbcnt.rs
+++ b/esp32/src/sdhost/tbbcnt.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TBBCNT")
-            .field("tbbcnt", &format_args!("{}", self.tbbcnt().bits()))
+            .field("tbbcnt", &self.tbbcnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TBBCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transferred byte count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbbcnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TBBCNT_SPEC;
 impl crate::RegisterSpec for TBBCNT_SPEC {
diff --git a/esp32/src/sdhost/tcbcnt.rs b/esp32/src/sdhost/tcbcnt.rs
index 0332649df8..2f744b171a 100644
--- a/esp32/src/sdhost/tcbcnt.rs
+++ b/esp32/src/sdhost/tcbcnt.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TCBCNT")
-            .field("tcbcnt", &format_args!("{}", self.tcbcnt().bits()))
+            .field("tcbcnt", &self.tcbcnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCBCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transferred byte count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcbcnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TCBCNT_SPEC;
 impl crate::RegisterSpec for TCBCNT_SPEC {
diff --git a/esp32/src/sdhost/tmout.rs b/esp32/src/sdhost/tmout.rs
index b0ad6750a7..f9a4084a1b 100644
--- a/esp32/src/sdhost/tmout.rs
+++ b/esp32/src/sdhost/tmout.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TMOUT")
-            .field(
-                "response_timeout",
-                &format_args!("{}", self.response_timeout().bits()),
-            )
-            .field(
-                "data_timeout",
-                &format_args!("{}", self.data_timeout().bits()),
-            )
+            .field("response_timeout", &self.response_timeout())
+            .field("data_timeout", &self.data_timeout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TMOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/uhs.rs b/esp32/src/sdhost/uhs.rs
index a4da564e20..13762b101a 100644
--- a/esp32/src/sdhost/uhs.rs
+++ b/esp32/src/sdhost/uhs.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("UHS")
-            .field("ddr", &format_args!("{}", self.ddr().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UHS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("UHS").field("ddr", &self.ddr()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/sdhost/usrid.rs b/esp32/src/sdhost/usrid.rs
index c1f4d4468f..00a625ffb6 100644
--- a/esp32/src/sdhost/usrid.rs
+++ b/esp32/src/sdhost/usrid.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USRID")
-            .field("usrid", &format_args!("{}", self.usrid().bits()))
+            .field("usrid", &self.usrid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USRID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - User identification register, value set by user. Can also be used as a scratchpad register by user."]
     #[inline(always)]
diff --git a/esp32/src/sdhost/verid.rs b/esp32/src/sdhost/verid.rs
index 0874ea6135..4c138b6386 100644
--- a/esp32/src/sdhost/verid.rs
+++ b/esp32/src/sdhost/verid.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERID")
-            .field("versionid", &format_args!("{}", self.versionid().bits()))
+            .field("versionid", &self.versionid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Version ID (scratchpad) register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`verid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VERID_SPEC;
 impl crate::RegisterSpec for VERID_SPEC {
diff --git a/esp32/src/sdhost/wrtprt.rs b/esp32/src/sdhost/wrtprt.rs
index cd98eab48c..ed6a8d409e 100644
--- a/esp32/src/sdhost/wrtprt.rs
+++ b/esp32/src/sdhost/wrtprt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WRTPRT")
-            .field(
-                "write_protect",
-                &format_args!("{}", self.write_protect().bits()),
-            )
+            .field("write_protect", &self.write_protect())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WRTPRT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Card write protection (WP) status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wrtprt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WRTPRT_SPEC;
 impl crate::RegisterSpec for WRTPRT_SPEC {
diff --git a/esp32/src/sens/sar_atten1.rs b/esp32/src/sens/sar_atten1.rs
index 4cb13b4563..b19cd53a92 100644
--- a/esp32/src/sens/sar_atten1.rs
+++ b/esp32/src/sens/sar_atten1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_ATTEN1")
-            .field("sar1_atten", &format_args!("{}", self.sar1_atten().bits()))
+            .field("sar1_atten", &self.sar1_atten())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_ATTEN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_atten2.rs b/esp32/src/sens/sar_atten2.rs
index bdf9a8733c..3907ff9a8d 100644
--- a/esp32/src/sens/sar_atten2.rs
+++ b/esp32/src/sens/sar_atten2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_ATTEN2")
-            .field("sar2_atten", &format_args!("{}", self.sar2_atten().bits()))
+            .field("sar2_atten", &self.sar2_atten())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_ATTEN2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_dac_ctrl1.rs b/esp32/src/sens/sar_dac_ctrl1.rs
index 71b7922d94..14f1384e5f 100644
--- a/esp32/src/sens/sar_dac_ctrl1.rs
+++ b/esp32/src/sens/sar_dac_ctrl1.rs
@@ -71,34 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_DAC_CTRL1")
-            .field("sw_fstep", &format_args!("{}", self.sw_fstep().bits()))
-            .field("sw_tone_en", &format_args!("{}", self.sw_tone_en().bit()))
-            .field(
-                "debug_bit_sel",
-                &format_args!("{}", self.debug_bit_sel().bits()),
-            )
-            .field(
-                "dac_dig_force",
-                &format_args!("{}", self.dac_dig_force().bit()),
-            )
-            .field(
-                "dac_clk_force_low",
-                &format_args!("{}", self.dac_clk_force_low().bit()),
-            )
-            .field(
-                "dac_clk_force_high",
-                &format_args!("{}", self.dac_clk_force_high().bit()),
-            )
-            .field("dac_clk_inv", &format_args!("{}", self.dac_clk_inv().bit()))
+            .field("sw_fstep", &self.sw_fstep())
+            .field("sw_tone_en", &self.sw_tone_en())
+            .field("debug_bit_sel", &self.debug_bit_sel())
+            .field("dac_dig_force", &self.dac_dig_force())
+            .field("dac_clk_force_low", &self.dac_clk_force_low())
+            .field("dac_clk_force_high", &self.dac_clk_force_high())
+            .field("dac_clk_inv", &self.dac_clk_inv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_DAC_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - frequency step for CW generator can be used to adjust the frequency"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_dac_ctrl2.rs b/esp32/src/sens/sar_dac_ctrl2.rs
index 71ffc51f7a..85bddf0d4a 100644
--- a/esp32/src/sens/sar_dac_ctrl2.rs
+++ b/esp32/src/sens/sar_dac_ctrl2.rs
@@ -80,23 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_DAC_CTRL2")
-            .field("dac_dc1", &format_args!("{}", self.dac_dc1().bits()))
-            .field("dac_dc2", &format_args!("{}", self.dac_dc2().bits()))
-            .field("dac_scale1", &format_args!("{}", self.dac_scale1().bits()))
-            .field("dac_scale2", &format_args!("{}", self.dac_scale2().bits()))
-            .field("dac_inv1", &format_args!("{}", self.dac_inv1().bits()))
-            .field("dac_inv2", &format_args!("{}", self.dac_inv2().bits()))
-            .field("dac_cw_en1", &format_args!("{}", self.dac_cw_en1().bit()))
-            .field("dac_cw_en2", &format_args!("{}", self.dac_cw_en2().bit()))
+            .field("dac_dc1", &self.dac_dc1())
+            .field("dac_dc2", &self.dac_dc2())
+            .field("dac_scale1", &self.dac_scale1())
+            .field("dac_scale2", &self.dac_scale2())
+            .field("dac_inv1", &self.dac_inv1())
+            .field("dac_inv2", &self.dac_inv2())
+            .field("dac_cw_en1", &self.dac_cw_en1())
+            .field("dac_cw_en2", &self.dac_cw_en2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_DAC_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - DC offset for DAC1 CW generator"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_i2c_ctrl.rs b/esp32/src/sens/sar_i2c_ctrl.rs
index c557277c6e..29becf9b44 100644
--- a/esp32/src/sens/sar_i2c_ctrl.rs
+++ b/esp32/src/sens/sar_i2c_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_I2C_CTRL")
-            .field(
-                "sar_i2c_ctrl",
-                &format_args!("{}", self.sar_i2c_ctrl().bits()),
-            )
-            .field(
-                "sar_i2c_start",
-                &format_args!("{}", self.sar_i2c_start().bit()),
-            )
-            .field(
-                "sar_i2c_start_force",
-                &format_args!("{}", self.sar_i2c_start_force().bit()),
-            )
+            .field("sar_i2c_ctrl", &self.sar_i2c_ctrl())
+            .field("sar_i2c_start", &self.sar_i2c_start())
+            .field("sar_i2c_start_force", &self.sar_i2c_start_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_I2C_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - I2C control data only active when reg_sar_i2c_start_force = 1"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_meas_ctrl.rs b/esp32/src/sens/sar_meas_ctrl.rs
index 822ff22ea3..d9723b075a 100644
--- a/esp32/src/sens/sar_meas_ctrl.rs
+++ b/esp32/src/sens/sar_meas_ctrl.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS_CTRL")
-            .field(
-                "xpd_sar_amp_fsm",
-                &format_args!("{}", self.xpd_sar_amp_fsm().bits()),
-            )
-            .field(
-                "amp_rst_fb_fsm",
-                &format_args!("{}", self.amp_rst_fb_fsm().bits()),
-            )
-            .field(
-                "amp_short_ref_fsm",
-                &format_args!("{}", self.amp_short_ref_fsm().bits()),
-            )
-            .field(
-                "amp_short_ref_gnd_fsm",
-                &format_args!("{}", self.amp_short_ref_gnd_fsm().bits()),
-            )
-            .field(
-                "xpd_sar_fsm",
-                &format_args!("{}", self.xpd_sar_fsm().bits()),
-            )
-            .field(
-                "sar_rstb_fsm",
-                &format_args!("{}", self.sar_rstb_fsm().bits()),
-            )
-            .field(
-                "sar2_xpd_wait",
-                &format_args!("{}", self.sar2_xpd_wait().bits()),
-            )
+            .field("xpd_sar_amp_fsm", &self.xpd_sar_amp_fsm())
+            .field("amp_rst_fb_fsm", &self.amp_rst_fb_fsm())
+            .field("amp_short_ref_fsm", &self.amp_short_ref_fsm())
+            .field("amp_short_ref_gnd_fsm", &self.amp_short_ref_gnd_fsm())
+            .field("xpd_sar_fsm", &self.xpd_sar_fsm())
+            .field("sar_rstb_fsm", &self.sar_rstb_fsm())
+            .field("sar2_xpd_wait", &self.sar2_xpd_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_meas_ctrl2.rs b/esp32/src/sens/sar_meas_ctrl2.rs
index 6ad6f6d837..74348b6560 100644
--- a/esp32/src/sens/sar_meas_ctrl2.rs
+++ b/esp32/src/sens/sar_meas_ctrl2.rs
@@ -116,63 +116,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS_CTRL2")
-            .field(
-                "sar1_dac_xpd_fsm",
-                &format_args!("{}", self.sar1_dac_xpd_fsm().bits()),
-            )
-            .field(
-                "sar1_dac_xpd_fsm_idle",
-                &format_args!("{}", self.sar1_dac_xpd_fsm_idle().bit()),
-            )
-            .field(
-                "xpd_sar_amp_fsm_idle",
-                &format_args!("{}", self.xpd_sar_amp_fsm_idle().bit()),
-            )
-            .field(
-                "amp_rst_fb_fsm_idle",
-                &format_args!("{}", self.amp_rst_fb_fsm_idle().bit()),
-            )
-            .field(
-                "amp_short_ref_fsm_idle",
-                &format_args!("{}", self.amp_short_ref_fsm_idle().bit()),
-            )
+            .field("sar1_dac_xpd_fsm", &self.sar1_dac_xpd_fsm())
+            .field("sar1_dac_xpd_fsm_idle", &self.sar1_dac_xpd_fsm_idle())
+            .field("xpd_sar_amp_fsm_idle", &self.xpd_sar_amp_fsm_idle())
+            .field("amp_rst_fb_fsm_idle", &self.amp_rst_fb_fsm_idle())
+            .field("amp_short_ref_fsm_idle", &self.amp_short_ref_fsm_idle())
             .field(
                 "amp_short_ref_gnd_fsm_idle",
-                &format_args!("{}", self.amp_short_ref_gnd_fsm_idle().bit()),
-            )
-            .field(
-                "xpd_sar_fsm_idle",
-                &format_args!("{}", self.xpd_sar_fsm_idle().bit()),
-            )
-            .field(
-                "sar_rstb_fsm_idle",
-                &format_args!("{}", self.sar_rstb_fsm_idle().bit()),
-            )
-            .field(
-                "sar2_rstb_force",
-                &format_args!("{}", self.sar2_rstb_force().bits()),
-            )
-            .field(
-                "amp_rst_fb_force",
-                &format_args!("{}", self.amp_rst_fb_force().bits()),
-            )
-            .field(
-                "amp_short_ref_force",
-                &format_args!("{}", self.amp_short_ref_force().bits()),
-            )
-            .field(
-                "amp_short_ref_gnd_force",
-                &format_args!("{}", self.amp_short_ref_gnd_force().bits()),
+                &self.amp_short_ref_gnd_fsm_idle(),
             )
+            .field("xpd_sar_fsm_idle", &self.xpd_sar_fsm_idle())
+            .field("sar_rstb_fsm_idle", &self.sar_rstb_fsm_idle())
+            .field("sar2_rstb_force", &self.sar2_rstb_force())
+            .field("amp_rst_fb_force", &self.amp_rst_fb_force())
+            .field("amp_short_ref_force", &self.amp_short_ref_force())
+            .field("amp_short_ref_gnd_force", &self.amp_short_ref_gnd_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_meas_start1.rs b/esp32/src/sens/sar_meas_start1.rs
index 25445e5a32..a94f583507 100644
--- a/esp32/src/sens/sar_meas_start1.rs
+++ b/esp32/src/sens/sar_meas_start1.rs
@@ -58,39 +58,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS_START1")
-            .field(
-                "meas1_data_sar",
-                &format_args!("{}", self.meas1_data_sar().bits()),
-            )
-            .field(
-                "meas1_done_sar",
-                &format_args!("{}", self.meas1_done_sar().bit()),
-            )
-            .field(
-                "meas1_start_sar",
-                &format_args!("{}", self.meas1_start_sar().bit()),
-            )
-            .field(
-                "meas1_start_force",
-                &format_args!("{}", self.meas1_start_force().bit()),
-            )
-            .field(
-                "sar1_en_pad",
-                &format_args!("{}", self.sar1_en_pad().bits()),
-            )
-            .field(
-                "sar1_en_pad_force",
-                &format_args!("{}", self.sar1_en_pad_force().bit()),
-            )
+            .field("meas1_data_sar", &self.meas1_data_sar())
+            .field("meas1_done_sar", &self.meas1_done_sar())
+            .field("meas1_start_sar", &self.meas1_start_sar())
+            .field("meas1_start_force", &self.meas1_start_force())
+            .field("sar1_en_pad", &self.sar1_en_pad())
+            .field("sar1_en_pad_force", &self.sar1_en_pad_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS_START1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - SAR ADC1 controller (in RTC) starts conversion only active when reg_meas1_start_force = 1"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_meas_start2.rs b/esp32/src/sens/sar_meas_start2.rs
index 9109cb4a61..d94e66a2c8 100644
--- a/esp32/src/sens/sar_meas_start2.rs
+++ b/esp32/src/sens/sar_meas_start2.rs
@@ -58,39 +58,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS_START2")
-            .field(
-                "meas2_data_sar",
-                &format_args!("{}", self.meas2_data_sar().bits()),
-            )
-            .field(
-                "meas2_done_sar",
-                &format_args!("{}", self.meas2_done_sar().bit()),
-            )
-            .field(
-                "meas2_start_sar",
-                &format_args!("{}", self.meas2_start_sar().bit()),
-            )
-            .field(
-                "meas2_start_force",
-                &format_args!("{}", self.meas2_start_force().bit()),
-            )
-            .field(
-                "sar2_en_pad",
-                &format_args!("{}", self.sar2_en_pad().bits()),
-            )
-            .field(
-                "sar2_en_pad_force",
-                &format_args!("{}", self.sar2_en_pad_force().bit()),
-            )
+            .field("meas2_data_sar", &self.meas2_data_sar())
+            .field("meas2_done_sar", &self.meas2_done_sar())
+            .field("meas2_start_sar", &self.meas2_start_sar())
+            .field("meas2_start_force", &self.meas2_start_force())
+            .field("sar2_en_pad", &self.sar2_en_pad())
+            .field("sar2_en_pad_force", &self.sar2_en_pad_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS_START2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - SAR ADC2 controller (in RTC) starts conversion only active when reg_meas2_start_force = 1"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_meas_wait1.rs b/esp32/src/sens/sar_meas_wait1.rs
index 1ce8bdb7ab..f2a9b93167 100644
--- a/esp32/src/sens/sar_meas_wait1.rs
+++ b/esp32/src/sens/sar_meas_wait1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS_WAIT1")
-            .field(
-                "sar_amp_wait1",
-                &format_args!("{}", self.sar_amp_wait1().bits()),
-            )
-            .field(
-                "sar_amp_wait2",
-                &format_args!("{}", self.sar_amp_wait2().bits()),
-            )
+            .field("sar_amp_wait1", &self.sar_amp_wait1())
+            .field("sar_amp_wait2", &self.sar_amp_wait2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS_WAIT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_meas_wait2.rs b/esp32/src/sens/sar_meas_wait2.rs
index 04bb39ddf0..80dad0c316 100644
--- a/esp32/src/sens/sar_meas_wait2.rs
+++ b/esp32/src/sens/sar_meas_wait2.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS_WAIT2")
-            .field(
-                "force_xpd_sar_sw",
-                &format_args!("{}", self.force_xpd_sar_sw().bit()),
-            )
-            .field(
-                "sar_amp_wait3",
-                &format_args!("{}", self.sar_amp_wait3().bits()),
-            )
-            .field(
-                "force_xpd_amp",
-                &format_args!("{}", self.force_xpd_amp().bits()),
-            )
-            .field(
-                "force_xpd_sar",
-                &format_args!("{}", self.force_xpd_sar().bits()),
-            )
-            .field(
-                "sar2_rstb_wait",
-                &format_args!("{}", self.sar2_rstb_wait().bits()),
-            )
+            .field("force_xpd_sar_sw", &self.force_xpd_sar_sw())
+            .field("sar_amp_wait3", &self.sar_amp_wait3())
+            .field("force_xpd_amp", &self.force_xpd_amp())
+            .field("force_xpd_sar", &self.force_xpd_sar())
+            .field("sar2_rstb_wait", &self.sar2_rstb_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS_WAIT2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_mem_wr_ctrl.rs b/esp32/src/sens/sar_mem_wr_ctrl.rs
index 01b29b1def..00ecd7a3b9 100644
--- a/esp32/src/sens/sar_mem_wr_ctrl.rs
+++ b/esp32/src/sens/sar_mem_wr_ctrl.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEM_WR_CTRL")
-            .field(
-                "mem_wr_addr_init",
-                &format_args!("{}", self.mem_wr_addr_init().bits()),
-            )
-            .field(
-                "mem_wr_addr_size",
-                &format_args!("{}", self.mem_wr_addr_size().bits()),
-            )
+            .field("mem_wr_addr_init", &self.mem_wr_addr_init())
+            .field("mem_wr_addr_size", &self.mem_wr_addr_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEM_WR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_nouse.rs b/esp32/src/sens/sar_nouse.rs
index 709835507d..75a502921a 100644
--- a/esp32/src/sens/sar_nouse.rs
+++ b/esp32/src/sens/sar_nouse.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_NOUSE")
-            .field("sar_nouse", &format_args!("{}", self.sar_nouse().bits()))
+            .field("sar_nouse", &self.sar_nouse())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_NOUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_read_ctrl.rs b/esp32/src/sens/sar_read_ctrl.rs
index 03f34661d5..b23f6b63ff 100644
--- a/esp32/src/sens/sar_read_ctrl.rs
+++ b/esp32/src/sens/sar_read_ctrl.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_READ_CTRL")
-            .field(
-                "sar1_clk_div",
-                &format_args!("{}", self.sar1_clk_div().bits()),
-            )
-            .field(
-                "sar1_sample_cycle",
-                &format_args!("{}", self.sar1_sample_cycle().bits()),
-            )
-            .field(
-                "sar1_sample_bit",
-                &format_args!("{}", self.sar1_sample_bit().bits()),
-            )
-            .field(
-                "sar1_clk_gated",
-                &format_args!("{}", self.sar1_clk_gated().bit()),
-            )
-            .field(
-                "sar1_sample_num",
-                &format_args!("{}", self.sar1_sample_num().bits()),
-            )
-            .field(
-                "sar1_dig_force",
-                &format_args!("{}", self.sar1_dig_force().bit()),
-            )
-            .field(
-                "sar1_data_inv",
-                &format_args!("{}", self.sar1_data_inv().bit()),
-            )
+            .field("sar1_clk_div", &self.sar1_clk_div())
+            .field("sar1_sample_cycle", &self.sar1_sample_cycle())
+            .field("sar1_sample_bit", &self.sar1_sample_bit())
+            .field("sar1_clk_gated", &self.sar1_clk_gated())
+            .field("sar1_sample_num", &self.sar1_sample_num())
+            .field("sar1_dig_force", &self.sar1_dig_force())
+            .field("sar1_data_inv", &self.sar1_data_inv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_READ_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - clock divider"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_read_ctrl2.rs b/esp32/src/sens/sar_read_ctrl2.rs
index b2513d4fcf..06c1e79c7c 100644
--- a/esp32/src/sens/sar_read_ctrl2.rs
+++ b/esp32/src/sens/sar_read_ctrl2.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_READ_CTRL2")
-            .field(
-                "sar2_clk_div",
-                &format_args!("{}", self.sar2_clk_div().bits()),
-            )
-            .field(
-                "sar2_sample_cycle",
-                &format_args!("{}", self.sar2_sample_cycle().bits()),
-            )
-            .field(
-                "sar2_sample_bit",
-                &format_args!("{}", self.sar2_sample_bit().bits()),
-            )
-            .field(
-                "sar2_clk_gated",
-                &format_args!("{}", self.sar2_clk_gated().bit()),
-            )
-            .field(
-                "sar2_sample_num",
-                &format_args!("{}", self.sar2_sample_num().bits()),
-            )
-            .field(
-                "sar2_pwdet_force",
-                &format_args!("{}", self.sar2_pwdet_force().bit()),
-            )
-            .field(
-                "sar2_dig_force",
-                &format_args!("{}", self.sar2_dig_force().bit()),
-            )
-            .field(
-                "sar2_data_inv",
-                &format_args!("{}", self.sar2_data_inv().bit()),
-            )
+            .field("sar2_clk_div", &self.sar2_clk_div())
+            .field("sar2_sample_cycle", &self.sar2_sample_cycle())
+            .field("sar2_sample_bit", &self.sar2_sample_bit())
+            .field("sar2_clk_gated", &self.sar2_clk_gated())
+            .field("sar2_sample_num", &self.sar2_sample_num())
+            .field("sar2_pwdet_force", &self.sar2_pwdet_force())
+            .field("sar2_dig_force", &self.sar2_dig_force())
+            .field("sar2_data_inv", &self.sar2_data_inv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_READ_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - clock divider"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_read_status1.rs b/esp32/src/sens/sar_read_status1.rs
index b3746f80d5..149c8e1918 100644
--- a/esp32/src/sens/sar_read_status1.rs
+++ b/esp32/src/sens/sar_read_status1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_READ_STATUS1")
-            .field(
-                "sar1_reader_status",
-                &format_args!("{}", self.sar1_reader_status().bits()),
-            )
+            .field("sar1_reader_status", &self.sar1_reader_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_READ_STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_read_status1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_READ_STATUS1_SPEC;
 impl crate::RegisterSpec for SAR_READ_STATUS1_SPEC {
diff --git a/esp32/src/sens/sar_read_status2.rs b/esp32/src/sens/sar_read_status2.rs
index cb1ee23439..0e74ac5559 100644
--- a/esp32/src/sens/sar_read_status2.rs
+++ b/esp32/src/sens/sar_read_status2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_READ_STATUS2")
-            .field(
-                "sar2_reader_status",
-                &format_args!("{}", self.sar2_reader_status().bits()),
-            )
+            .field("sar2_reader_status", &self.sar2_reader_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_READ_STATUS2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_read_status2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_READ_STATUS2_SPEC;
 impl crate::RegisterSpec for SAR_READ_STATUS2_SPEC {
diff --git a/esp32/src/sens/sar_slave_addr1.rs b/esp32/src/sens/sar_slave_addr1.rs
index a214a869c9..92c610300d 100644
--- a/esp32/src/sens/sar_slave_addr1.rs
+++ b/esp32/src/sens/sar_slave_addr1.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR1")
-            .field(
-                "i2c_slave_addr1",
-                &format_args!("{}", self.i2c_slave_addr1().bits()),
-            )
-            .field(
-                "i2c_slave_addr0",
-                &format_args!("{}", self.i2c_slave_addr0().bits()),
-            )
-            .field(
-                "meas_status",
-                &format_args!("{}", self.meas_status().bits()),
-            )
+            .field("i2c_slave_addr1", &self.i2c_slave_addr1())
+            .field("i2c_slave_addr0", &self.i2c_slave_addr0())
+            .field("meas_status", &self.meas_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_slave_addr2.rs b/esp32/src/sens/sar_slave_addr2.rs
index 50ea8042d8..8b1d34ade6 100644
--- a/esp32/src/sens/sar_slave_addr2.rs
+++ b/esp32/src/sens/sar_slave_addr2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR2")
-            .field(
-                "i2c_slave_addr3",
-                &format_args!("{}", self.i2c_slave_addr3().bits()),
-            )
-            .field(
-                "i2c_slave_addr2",
-                &format_args!("{}", self.i2c_slave_addr2().bits()),
-            )
+            .field("i2c_slave_addr3", &self.i2c_slave_addr3())
+            .field("i2c_slave_addr2", &self.i2c_slave_addr2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_slave_addr3.rs b/esp32/src/sens/sar_slave_addr3.rs
index eeb29e1f63..ee49ed8475 100644
--- a/esp32/src/sens/sar_slave_addr3.rs
+++ b/esp32/src/sens/sar_slave_addr3.rs
@@ -40,28 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR3")
-            .field(
-                "i2c_slave_addr5",
-                &format_args!("{}", self.i2c_slave_addr5().bits()),
-            )
-            .field(
-                "i2c_slave_addr4",
-                &format_args!("{}", self.i2c_slave_addr4().bits()),
-            )
-            .field("tsens_out", &format_args!("{}", self.tsens_out().bits()))
-            .field(
-                "tsens_rdy_out",
-                &format_args!("{}", self.tsens_rdy_out().bit()),
-            )
+            .field("i2c_slave_addr5", &self.i2c_slave_addr5())
+            .field("i2c_slave_addr4", &self.i2c_slave_addr4())
+            .field("tsens_out", &self.tsens_out())
+            .field("tsens_rdy_out", &self.tsens_rdy_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_slave_addr4.rs b/esp32/src/sens/sar_slave_addr4.rs
index c98857a85f..1861418d9a 100644
--- a/esp32/src/sens/sar_slave_addr4.rs
+++ b/esp32/src/sens/sar_slave_addr4.rs
@@ -40,25 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR4")
-            .field(
-                "i2c_slave_addr7",
-                &format_args!("{}", self.i2c_slave_addr7().bits()),
-            )
-            .field(
-                "i2c_slave_addr6",
-                &format_args!("{}", self.i2c_slave_addr6().bits()),
-            )
-            .field("i2c_rdata", &format_args!("{}", self.i2c_rdata().bits()))
-            .field("i2c_done", &format_args!("{}", self.i2c_done().bit()))
+            .field("i2c_slave_addr7", &self.i2c_slave_addr7())
+            .field("i2c_slave_addr6", &self.i2c_slave_addr6())
+            .field("i2c_rdata", &self.i2c_rdata())
+            .field("i2c_done", &self.i2c_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_start_force.rs b/esp32/src/sens/sar_start_force.rs
index 5de9db8c61..c4bc78ffe8 100644
--- a/esp32/src/sens/sar_start_force.rs
+++ b/esp32/src/sens/sar_start_force.rs
@@ -107,47 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_START_FORCE")
-            .field(
-                "sar1_bit_width",
-                &format_args!("{}", self.sar1_bit_width().bits()),
-            )
-            .field(
-                "sar2_bit_width",
-                &format_args!("{}", self.sar2_bit_width().bits()),
-            )
-            .field(
-                "sar2_en_test",
-                &format_args!("{}", self.sar2_en_test().bit()),
-            )
-            .field(
-                "sar2_pwdet_cct",
-                &format_args!("{}", self.sar2_pwdet_cct().bits()),
-            )
-            .field(
-                "ulp_cp_force_start_top",
-                &format_args!("{}", self.ulp_cp_force_start_top().bit()),
-            )
-            .field(
-                "ulp_cp_start_top",
-                &format_args!("{}", self.ulp_cp_start_top().bit()),
-            )
-            .field("sarclk_en", &format_args!("{}", self.sarclk_en().bit()))
-            .field("pc_init", &format_args!("{}", self.pc_init().bits()))
-            .field("sar2_stop", &format_args!("{}", self.sar2_stop().bit()))
-            .field("sar1_stop", &format_args!("{}", self.sar1_stop().bit()))
-            .field(
-                "sar2_pwdet_en",
-                &format_args!("{}", self.sar2_pwdet_en().bit()),
-            )
+            .field("sar1_bit_width", &self.sar1_bit_width())
+            .field("sar2_bit_width", &self.sar2_bit_width())
+            .field("sar2_en_test", &self.sar2_en_test())
+            .field("sar2_pwdet_cct", &self.sar2_pwdet_cct())
+            .field("ulp_cp_force_start_top", &self.ulp_cp_force_start_top())
+            .field("ulp_cp_start_top", &self.ulp_cp_start_top())
+            .field("sarclk_en", &self.sarclk_en())
+            .field("pc_init", &self.pc_init())
+            .field("sar2_stop", &self.sar2_stop())
+            .field("sar1_stop", &self.sar1_stop())
+            .field("sar2_pwdet_en", &self.sar2_pwdet_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_START_FORCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_touch_ctrl1.rs b/esp32/src/sens/sar_touch_ctrl1.rs
index c65831649c..23c90a48cf 100644
--- a/esp32/src/sens/sar_touch_ctrl1.rs
+++ b/esp32/src/sens/sar_touch_ctrl1.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_CTRL1")
-            .field(
-                "touch_meas_delay",
-                &format_args!("{}", self.touch_meas_delay().bits()),
-            )
-            .field(
-                "touch_xpd_wait",
-                &format_args!("{}", self.touch_xpd_wait().bits()),
-            )
-            .field(
-                "touch_out_sel",
-                &format_args!("{}", self.touch_out_sel().bit()),
-            )
-            .field(
-                "touch_out_1en",
-                &format_args!("{}", self.touch_out_1en().bit()),
-            )
-            .field(
-                "xpd_hall_force",
-                &format_args!("{}", self.xpd_hall_force().bit()),
-            )
-            .field(
-                "hall_phase_force",
-                &format_args!("{}", self.hall_phase_force().bit()),
-            )
+            .field("touch_meas_delay", &self.touch_meas_delay())
+            .field("touch_xpd_wait", &self.touch_xpd_wait())
+            .field("touch_out_sel", &self.touch_out_sel())
+            .field("touch_out_1en", &self.touch_out_1en())
+            .field("xpd_hall_force", &self.xpd_hall_force())
+            .field("hall_phase_force", &self.hall_phase_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - the meas length (in 8MHz)"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_touch_ctrl2.rs b/esp32/src/sens/sar_touch_ctrl2.rs
index bfb7f258d1..1a380af2e3 100644
--- a/esp32/src/sens/sar_touch_ctrl2.rs
+++ b/esp32/src/sens/sar_touch_ctrl2.rs
@@ -60,39 +60,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_CTRL2")
-            .field(
-                "touch_meas_en",
-                &format_args!("{}", self.touch_meas_en().bits()),
-            )
-            .field(
-                "touch_meas_done",
-                &format_args!("{}", self.touch_meas_done().bit()),
-            )
-            .field(
-                "touch_start_fsm_en",
-                &format_args!("{}", self.touch_start_fsm_en().bit()),
-            )
-            .field(
-                "touch_start_en",
-                &format_args!("{}", self.touch_start_en().bit()),
-            )
-            .field(
-                "touch_start_force",
-                &format_args!("{}", self.touch_start_force().bit()),
-            )
-            .field(
-                "touch_sleep_cycles",
-                &format_args!("{}", self.touch_sleep_cycles().bits()),
-            )
+            .field("touch_meas_en", &self.touch_meas_en())
+            .field("touch_meas_done", &self.touch_meas_done())
+            .field("touch_start_fsm_en", &self.touch_start_fsm_en())
+            .field("touch_start_en", &self.touch_start_en())
+            .field("touch_start_force", &self.touch_start_force())
+            .field("touch_sleep_cycles", &self.touch_sleep_cycles())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 11 - 1: TOUCH_START &amp; TOUCH_XPD is controlled by touch fsm 0: TOUCH_START &amp; TOUCH_XPD is controlled by registers"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_touch_enable.rs b/esp32/src/sens/sar_touch_enable.rs
index 6f4f5f2cd2..75332612a9 100644
--- a/esp32/src/sens/sar_touch_enable.rs
+++ b/esp32/src/sens/sar_touch_enable.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_ENABLE")
-            .field(
-                "touch_pad_worken",
-                &format_args!("{}", self.touch_pad_worken().bits()),
-            )
-            .field(
-                "touch_pad_outen2",
-                &format_args!("{}", self.touch_pad_outen2().bits()),
-            )
-            .field(
-                "touch_pad_outen1",
-                &format_args!("{}", self.touch_pad_outen1().bits()),
-            )
+            .field("touch_pad_worken", &self.touch_pad_worken())
+            .field("touch_pad_outen2", &self.touch_pad_outen2())
+            .field("touch_pad_outen1", &self.touch_pad_outen1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - Bitmap defining the working set during the measurement."]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_touch_out1.rs b/esp32/src/sens/sar_touch_out1.rs
index f21cf59fa5..d103f5cea7 100644
--- a/esp32/src/sens/sar_touch_out1.rs
+++ b/esp32/src/sens/sar_touch_out1.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_OUT1")
-            .field(
-                "touch_meas_out1",
-                &format_args!("{}", self.touch_meas_out1().bits()),
-            )
-            .field(
-                "touch_meas_out0",
-                &format_args!("{}", self.touch_meas_out0().bits()),
-            )
+            .field("touch_meas_out1", &self.touch_meas_out1())
+            .field("touch_meas_out0", &self.touch_meas_out0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_OUT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_out1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_OUT1_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_OUT1_SPEC {
diff --git a/esp32/src/sens/sar_touch_out2.rs b/esp32/src/sens/sar_touch_out2.rs
index 842bcb7e15..792c0c75c3 100644
--- a/esp32/src/sens/sar_touch_out2.rs
+++ b/esp32/src/sens/sar_touch_out2.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_OUT2")
-            .field(
-                "touch_meas_out3",
-                &format_args!("{}", self.touch_meas_out3().bits()),
-            )
-            .field(
-                "touch_meas_out2",
-                &format_args!("{}", self.touch_meas_out2().bits()),
-            )
+            .field("touch_meas_out3", &self.touch_meas_out3())
+            .field("touch_meas_out2", &self.touch_meas_out2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_OUT2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_out2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_OUT2_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_OUT2_SPEC {
diff --git a/esp32/src/sens/sar_touch_out3.rs b/esp32/src/sens/sar_touch_out3.rs
index 0ab2fd8e81..13e21e98e6 100644
--- a/esp32/src/sens/sar_touch_out3.rs
+++ b/esp32/src/sens/sar_touch_out3.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_OUT3")
-            .field(
-                "touch_meas_out5",
-                &format_args!("{}", self.touch_meas_out5().bits()),
-            )
-            .field(
-                "touch_meas_out4",
-                &format_args!("{}", self.touch_meas_out4().bits()),
-            )
+            .field("touch_meas_out5", &self.touch_meas_out5())
+            .field("touch_meas_out4", &self.touch_meas_out4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_OUT3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_out3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_OUT3_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_OUT3_SPEC {
diff --git a/esp32/src/sens/sar_touch_out4.rs b/esp32/src/sens/sar_touch_out4.rs
index 0b5b4063a0..6f49f25c9b 100644
--- a/esp32/src/sens/sar_touch_out4.rs
+++ b/esp32/src/sens/sar_touch_out4.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_OUT4")
-            .field(
-                "touch_meas_out7",
-                &format_args!("{}", self.touch_meas_out7().bits()),
-            )
-            .field(
-                "touch_meas_out6",
-                &format_args!("{}", self.touch_meas_out6().bits()),
-            )
+            .field("touch_meas_out7", &self.touch_meas_out7())
+            .field("touch_meas_out6", &self.touch_meas_out6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_OUT4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_out4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_OUT4_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_OUT4_SPEC {
diff --git a/esp32/src/sens/sar_touch_out5.rs b/esp32/src/sens/sar_touch_out5.rs
index ea3898cb62..475cdcf795 100644
--- a/esp32/src/sens/sar_touch_out5.rs
+++ b/esp32/src/sens/sar_touch_out5.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_OUT5")
-            .field(
-                "touch_meas_out9",
-                &format_args!("{}", self.touch_meas_out9().bits()),
-            )
-            .field(
-                "touch_meas_out8",
-                &format_args!("{}", self.touch_meas_out8().bits()),
-            )
+            .field("touch_meas_out9", &self.touch_meas_out9())
+            .field("touch_meas_out8", &self.touch_meas_out8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_OUT5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_out5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_OUT5_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_OUT5_SPEC {
diff --git a/esp32/src/sens/sar_touch_thres1.rs b/esp32/src/sens/sar_touch_thres1.rs
index 202a93ca27..ac015b7d1f 100644
--- a/esp32/src/sens/sar_touch_thres1.rs
+++ b/esp32/src/sens/sar_touch_thres1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES1")
-            .field(
-                "touch_out_th1",
-                &format_args!("{}", self.touch_out_th1().bits()),
-            )
-            .field(
-                "touch_out_th0",
-                &format_args!("{}", self.touch_out_th0().bits()),
-            )
+            .field("touch_out_th1", &self.touch_out_th1())
+            .field("touch_out_th0", &self.touch_out_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - the threshold for touch pad 1"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_touch_thres2.rs b/esp32/src/sens/sar_touch_thres2.rs
index 3efea6195e..9d852f4e2f 100644
--- a/esp32/src/sens/sar_touch_thres2.rs
+++ b/esp32/src/sens/sar_touch_thres2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES2")
-            .field(
-                "touch_out_th3",
-                &format_args!("{}", self.touch_out_th3().bits()),
-            )
-            .field(
-                "touch_out_th2",
-                &format_args!("{}", self.touch_out_th2().bits()),
-            )
+            .field("touch_out_th3", &self.touch_out_th3())
+            .field("touch_out_th2", &self.touch_out_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - the threshold for touch pad 3"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_touch_thres3.rs b/esp32/src/sens/sar_touch_thres3.rs
index aa511ea5c0..71c5af80fa 100644
--- a/esp32/src/sens/sar_touch_thres3.rs
+++ b/esp32/src/sens/sar_touch_thres3.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES3")
-            .field(
-                "touch_out_th5",
-                &format_args!("{}", self.touch_out_th5().bits()),
-            )
-            .field(
-                "touch_out_th4",
-                &format_args!("{}", self.touch_out_th4().bits()),
-            )
+            .field("touch_out_th5", &self.touch_out_th5())
+            .field("touch_out_th4", &self.touch_out_th4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - the threshold for touch pad 5"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_touch_thres4.rs b/esp32/src/sens/sar_touch_thres4.rs
index 42c1a0867d..00c910a473 100644
--- a/esp32/src/sens/sar_touch_thres4.rs
+++ b/esp32/src/sens/sar_touch_thres4.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES4")
-            .field(
-                "touch_out_th7",
-                &format_args!("{}", self.touch_out_th7().bits()),
-            )
-            .field(
-                "touch_out_th6",
-                &format_args!("{}", self.touch_out_th6().bits()),
-            )
+            .field("touch_out_th7", &self.touch_out_th7())
+            .field("touch_out_th6", &self.touch_out_th6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - the threshold for touch pad 7"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_touch_thres5.rs b/esp32/src/sens/sar_touch_thres5.rs
index fec1d8ba01..49285f0fe1 100644
--- a/esp32/src/sens/sar_touch_thres5.rs
+++ b/esp32/src/sens/sar_touch_thres5.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES5")
-            .field(
-                "touch_out_th9",
-                &format_args!("{}", self.touch_out_th9().bits()),
-            )
-            .field(
-                "touch_out_th8",
-                &format_args!("{}", self.touch_out_th8().bits()),
-            )
+            .field("touch_out_th9", &self.touch_out_th9())
+            .field("touch_out_th8", &self.touch_out_th8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - the threshold for touch pad 9"]
     #[inline(always)]
diff --git a/esp32/src/sens/sar_tsens_ctrl.rs b/esp32/src/sens/sar_tsens_ctrl.rs
index 49b40077cf..1b8ec73d65 100644
--- a/esp32/src/sens/sar_tsens_ctrl.rs
+++ b/esp32/src/sens/sar_tsens_ctrl.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TSENS_CTRL")
-            .field(
-                "tsens_xpd_wait",
-                &format_args!("{}", self.tsens_xpd_wait().bits()),
-            )
-            .field(
-                "tsens_xpd_force",
-                &format_args!("{}", self.tsens_xpd_force().bit()),
-            )
-            .field(
-                "tsens_clk_inv",
-                &format_args!("{}", self.tsens_clk_inv().bit()),
-            )
-            .field(
-                "tsens_clk_gated",
-                &format_args!("{}", self.tsens_clk_gated().bit()),
-            )
-            .field(
-                "tsens_in_inv",
-                &format_args!("{}", self.tsens_in_inv().bit()),
-            )
-            .field(
-                "tsens_clk_div",
-                &format_args!("{}", self.tsens_clk_div().bits()),
-            )
-            .field(
-                "tsens_power_up",
-                &format_args!("{}", self.tsens_power_up().bit()),
-            )
-            .field(
-                "tsens_power_up_force",
-                &format_args!("{}", self.tsens_power_up_force().bit()),
-            )
-            .field(
-                "tsens_dump_out",
-                &format_args!("{}", self.tsens_dump_out().bit()),
-            )
+            .field("tsens_xpd_wait", &self.tsens_xpd_wait())
+            .field("tsens_xpd_force", &self.tsens_xpd_force())
+            .field("tsens_clk_inv", &self.tsens_clk_inv())
+            .field("tsens_clk_gated", &self.tsens_clk_gated())
+            .field("tsens_in_inv", &self.tsens_in_inv())
+            .field("tsens_clk_div", &self.tsens_clk_div())
+            .field("tsens_power_up", &self.tsens_power_up())
+            .field("tsens_power_up_force", &self.tsens_power_up_force())
+            .field("tsens_dump_out", &self.tsens_dump_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TSENS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
diff --git a/esp32/src/sens/sardate.rs b/esp32/src/sens/sardate.rs
index 4d1d2a7dc0..35d5adf073 100644
--- a/esp32/src/sens/sardate.rs
+++ b/esp32/src/sens/sardate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SARDATE")
-            .field("sar_date", &format_args!("{}", self.sar_date().bits()))
+            .field("sar_date", &self.sar_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SARDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27"]
     #[inline(always)]
diff --git a/esp32/src/sens/ulp_cp_sleep_cyc0.rs b/esp32/src/sens/ulp_cp_sleep_cyc0.rs
index 088abf24c1..89c1edf32e 100644
--- a/esp32/src/sens/ulp_cp_sleep_cyc0.rs
+++ b/esp32/src/sens/ulp_cp_sleep_cyc0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_SLEEP_CYC0")
-            .field(
-                "sleep_cycles_s0",
-                &format_args!("{}", self.sleep_cycles_s0().bits()),
-            )
+            .field("sleep_cycles_s0", &self.sleep_cycles_s0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_SLEEP_CYC0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - sleep cycles for ULP-coprocessor timer"]
     #[inline(always)]
diff --git a/esp32/src/sens/ulp_cp_sleep_cyc1.rs b/esp32/src/sens/ulp_cp_sleep_cyc1.rs
index 181518cede..25a5493d95 100644
--- a/esp32/src/sens/ulp_cp_sleep_cyc1.rs
+++ b/esp32/src/sens/ulp_cp_sleep_cyc1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_SLEEP_CYC1")
-            .field(
-                "sleep_cycles_s1",
-                &format_args!("{}", self.sleep_cycles_s1().bits()),
-            )
+            .field("sleep_cycles_s1", &self.sleep_cycles_s1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_SLEEP_CYC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/sens/ulp_cp_sleep_cyc2.rs b/esp32/src/sens/ulp_cp_sleep_cyc2.rs
index 984fd2a9b4..e935072bc8 100644
--- a/esp32/src/sens/ulp_cp_sleep_cyc2.rs
+++ b/esp32/src/sens/ulp_cp_sleep_cyc2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_SLEEP_CYC2")
-            .field(
-                "sleep_cycles_s2",
-                &format_args!("{}", self.sleep_cycles_s2().bits()),
-            )
+            .field("sleep_cycles_s2", &self.sleep_cycles_s2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_SLEEP_CYC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/sens/ulp_cp_sleep_cyc3.rs b/esp32/src/sens/ulp_cp_sleep_cyc3.rs
index a88a8c5306..b96150c3ce 100644
--- a/esp32/src/sens/ulp_cp_sleep_cyc3.rs
+++ b/esp32/src/sens/ulp_cp_sleep_cyc3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_SLEEP_CYC3")
-            .field(
-                "sleep_cycles_s3",
-                &format_args!("{}", self.sleep_cycles_s3().bits()),
-            )
+            .field("sleep_cycles_s3", &self.sleep_cycles_s3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_SLEEP_CYC3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/sens/ulp_cp_sleep_cyc4.rs b/esp32/src/sens/ulp_cp_sleep_cyc4.rs
index 1d8f28cc2d..2a8d3524a2 100644
--- a/esp32/src/sens/ulp_cp_sleep_cyc4.rs
+++ b/esp32/src/sens/ulp_cp_sleep_cyc4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_SLEEP_CYC4")
-            .field(
-                "sleep_cycles_s4",
-                &format_args!("{}", self.sleep_cycles_s4().bits()),
-            )
+            .field("sleep_cycles_s4", &self.sleep_cycles_s4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_SLEEP_CYC4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/sha/sha1_busy.rs b/esp32/src/sha/sha1_busy.rs
index 5b20134c01..31b806548b 100644
--- a/esp32/src/sha/sha1_busy.rs
+++ b/esp32/src/sha/sha1_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA1_BUSY")
-            .field("sha1_busy", &format_args!("{}", self.sha1_busy().bit()))
+            .field("sha1_busy", &self.sha1_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA1_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sha1_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SHA1_BUSY_SPEC;
 impl crate::RegisterSpec for SHA1_BUSY_SPEC {
diff --git a/esp32/src/sha/sha256_busy.rs b/esp32/src/sha/sha256_busy.rs
index b22f47d9e9..53f22ca9ff 100644
--- a/esp32/src/sha/sha256_busy.rs
+++ b/esp32/src/sha/sha256_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA256_BUSY")
-            .field("sha256_busy", &format_args!("{}", self.sha256_busy().bit()))
+            .field("sha256_busy", &self.sha256_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA256_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sha256_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SHA256_BUSY_SPEC;
 impl crate::RegisterSpec for SHA256_BUSY_SPEC {
diff --git a/esp32/src/sha/sha384_busy.rs b/esp32/src/sha/sha384_busy.rs
index bac5307bc3..1f9449e56b 100644
--- a/esp32/src/sha/sha384_busy.rs
+++ b/esp32/src/sha/sha384_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA384_BUSY")
-            .field("sha384_busy", &format_args!("{}", self.sha384_busy().bit()))
+            .field("sha384_busy", &self.sha384_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA384_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sha384_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SHA384_BUSY_SPEC;
 impl crate::RegisterSpec for SHA384_BUSY_SPEC {
diff --git a/esp32/src/sha/sha512_busy.rs b/esp32/src/sha/sha512_busy.rs
index 17800973d5..e12b7218e2 100644
--- a/esp32/src/sha/sha512_busy.rs
+++ b/esp32/src/sha/sha512_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA512_BUSY")
-            .field("sha512_busy", &format_args!("{}", self.sha512_busy().bit()))
+            .field("sha512_busy", &self.sha512_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA512_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sha512_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SHA512_BUSY_SPEC;
 impl crate::RegisterSpec for SHA512_BUSY_SPEC {
diff --git a/esp32/src/sha/text.rs b/esp32/src/sha/text.rs
index da2268b377..c7c239fea4 100644
--- a/esp32/src/sha/text.rs
+++ b/esp32/src/sha/text.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("TEXT")
-            .field("text", &format_args!("{}", self.text().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEXT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("TEXT").field("text", &self.text()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/slc/_0_done_dscr_addr.rs b/esp32/src/slc/_0_done_dscr_addr.rs
index 542aee279d..081cf7aaca 100644
--- a/esp32/src/slc/_0_done_dscr_addr.rs
+++ b/esp32/src/slc/_0_done_dscr_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_DONE_DSCR_ADDR")
-            .field(
-                "slc0_rx_done_dscr_addr",
-                &format_args!("{}", self.slc0_rx_done_dscr_addr().bits()),
-            )
+            .field("slc0_rx_done_dscr_addr", &self.slc0_rx_done_dscr_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_DONE_DSCR_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_done_dscr_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_DONE_DSCR_ADDR_SPEC;
 impl crate::RegisterSpec for _0_DONE_DSCR_ADDR_SPEC {
diff --git a/esp32/src/slc/_0_dscr_cnt.rs b/esp32/src/slc/_0_dscr_cnt.rs
index 8475272133..5891c43fba 100644
--- a/esp32/src/slc/_0_dscr_cnt.rs
+++ b/esp32/src/slc/_0_dscr_cnt.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_DSCR_CNT")
-            .field(
-                "slc0_rx_dscr_cnt_lat",
-                &format_args!("{}", self.slc0_rx_dscr_cnt_lat().bits()),
-            )
-            .field(
-                "slc0_rx_get_eof_occ",
-                &format_args!("{}", self.slc0_rx_get_eof_occ().bit()),
-            )
+            .field("slc0_rx_dscr_cnt_lat", &self.slc0_rx_dscr_cnt_lat())
+            .field("slc0_rx_get_eof_occ", &self.slc0_rx_get_eof_occ())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_DSCR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_dscr_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_DSCR_CNT_SPEC;
 impl crate::RegisterSpec for _0_DSCR_CNT_SPEC {
diff --git a/esp32/src/slc/_0_dscr_rec_conf.rs b/esp32/src/slc/_0_dscr_rec_conf.rs
index f8d9bf12cb..7187f48e7e 100644
--- a/esp32/src/slc/_0_dscr_rec_conf.rs
+++ b/esp32/src/slc/_0_dscr_rec_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_DSCR_REC_CONF")
-            .field(
-                "slc0_rx_dscr_rec_lim",
-                &format_args!("{}", self.slc0_rx_dscr_rec_lim().bits()),
-            )
+            .field("slc0_rx_dscr_rec_lim", &self.slc0_rx_dscr_rec_lim())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_DSCR_REC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
diff --git a/esp32/src/slc/_0_eof_start_des.rs b/esp32/src/slc/_0_eof_start_des.rs
index cfdbe1496e..687bbeb63c 100644
--- a/esp32/src/slc/_0_eof_start_des.rs
+++ b/esp32/src/slc/_0_eof_start_des.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_EOF_START_DES")
-            .field(
-                "slc0_eof_start_des_addr",
-                &format_args!("{}", self.slc0_eof_start_des_addr().bits()),
-            )
+            .field("slc0_eof_start_des_addr", &self.slc0_eof_start_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_EOF_START_DES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_eof_start_des::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_EOF_START_DES_SPEC;
 impl crate::RegisterSpec for _0_EOF_START_DES_SPEC {
diff --git a/esp32/src/slc/_0_len_conf.rs b/esp32/src/slc/_0_len_conf.rs
index a6ff92fc3a..9a65c90484 100644
--- a/esp32/src/slc/_0_len_conf.rs
+++ b/esp32/src/slc/_0_len_conf.rs
@@ -52,31 +52,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_LEN_CONF")
-            .field(
-                "slc0_rx_packet_load_en",
-                &format_args!("{}", self.slc0_rx_packet_load_en().bit()),
-            )
-            .field(
-                "slc0_tx_packet_load_en",
-                &format_args!("{}", self.slc0_tx_packet_load_en().bit()),
-            )
-            .field(
-                "slc0_rx_new_pkt_ind",
-                &format_args!("{}", self.slc0_rx_new_pkt_ind().bit()),
-            )
-            .field(
-                "slc0_tx_new_pkt_ind",
-                &format_args!("{}", self.slc0_tx_new_pkt_ind().bit()),
-            )
+            .field("slc0_rx_packet_load_en", &self.slc0_rx_packet_load_en())
+            .field("slc0_tx_packet_load_en", &self.slc0_tx_packet_load_en())
+            .field("slc0_rx_new_pkt_ind", &self.slc0_rx_new_pkt_ind())
+            .field("slc0_tx_new_pkt_ind", &self.slc0_tx_new_pkt_ind())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_LEN_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
diff --git a/esp32/src/slc/_0_len_lim_conf.rs b/esp32/src/slc/_0_len_lim_conf.rs
index 656a0ca8d4..076a5125d4 100644
--- a/esp32/src/slc/_0_len_lim_conf.rs
+++ b/esp32/src/slc/_0_len_lim_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_LEN_LIM_CONF")
-            .field(
-                "slc0_len_lim",
-                &format_args!("{}", self.slc0_len_lim().bits()),
-            )
+            .field("slc0_len_lim", &self.slc0_len_lim())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_LEN_LIM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
diff --git a/esp32/src/slc/_0_length.rs b/esp32/src/slc/_0_length.rs
index db4c14e910..ccc91153eb 100644
--- a/esp32/src/slc/_0_length.rs
+++ b/esp32/src/slc/_0_length.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_LENGTH")
-            .field("slc0_len", &format_args!("{}", self.slc0_len().bits()))
+            .field("slc0_len", &self.slc0_len())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_LENGTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_length::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_LENGTH_SPEC;
 impl crate::RegisterSpec for _0_LENGTH_SPEC {
diff --git a/esp32/src/slc/_0_push_dscr_addr.rs b/esp32/src/slc/_0_push_dscr_addr.rs
index 50970cf0a2..fe4cad2d9f 100644
--- a/esp32/src/slc/_0_push_dscr_addr.rs
+++ b/esp32/src/slc/_0_push_dscr_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_PUSH_DSCR_ADDR")
-            .field(
-                "slc0_rx_push_dscr_addr",
-                &format_args!("{}", self.slc0_rx_push_dscr_addr().bits()),
-            )
+            .field("slc0_rx_push_dscr_addr", &self.slc0_rx_push_dscr_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_PUSH_DSCR_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_push_dscr_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_PUSH_DSCR_ADDR_SPEC;
 impl crate::RegisterSpec for _0_PUSH_DSCR_ADDR_SPEC {
diff --git a/esp32/src/slc/_0_rxlink_dscr.rs b/esp32/src/slc/_0_rxlink_dscr.rs
index d594d50292..949e8d960a 100644
--- a/esp32/src/slc/_0_rxlink_dscr.rs
+++ b/esp32/src/slc/_0_rxlink_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_RXLINK_DSCR")
-            .field(
-                "slc0_rxlink_dscr",
-                &format_args!("{}", self.slc0_rxlink_dscr().bits()),
-            )
+            .field("slc0_rxlink_dscr", &self.slc0_rxlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_RXLINK_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_rxlink_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_RXLINK_DSCR_SPEC;
 impl crate::RegisterSpec for _0_RXLINK_DSCR_SPEC {
diff --git a/esp32/src/slc/_0_rxlink_dscr_bf0.rs b/esp32/src/slc/_0_rxlink_dscr_bf0.rs
index 8340c6533a..4a0c111f84 100644
--- a/esp32/src/slc/_0_rxlink_dscr_bf0.rs
+++ b/esp32/src/slc/_0_rxlink_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_RXLINK_DSCR_BF0")
-            .field(
-                "slc0_rxlink_dscr_bf0",
-                &format_args!("{}", self.slc0_rxlink_dscr_bf0().bits()),
-            )
+            .field("slc0_rxlink_dscr_bf0", &self.slc0_rxlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_RXLINK_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_rxlink_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_RXLINK_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for _0_RXLINK_DSCR_BF0_SPEC {
diff --git a/esp32/src/slc/_0_rxlink_dscr_bf1.rs b/esp32/src/slc/_0_rxlink_dscr_bf1.rs
index 721d6969d6..4a8dde2101 100644
--- a/esp32/src/slc/_0_rxlink_dscr_bf1.rs
+++ b/esp32/src/slc/_0_rxlink_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_RXLINK_DSCR_BF1")
-            .field(
-                "slc0_rxlink_dscr_bf1",
-                &format_args!("{}", self.slc0_rxlink_dscr_bf1().bits()),
-            )
+            .field("slc0_rxlink_dscr_bf1", &self.slc0_rxlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_RXLINK_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_rxlink_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_RXLINK_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for _0_RXLINK_DSCR_BF1_SPEC {
diff --git a/esp32/src/slc/_0_rxpkt_e_dscr.rs b/esp32/src/slc/_0_rxpkt_e_dscr.rs
index cff875ab96..5c6467dbd2 100644
--- a/esp32/src/slc/_0_rxpkt_e_dscr.rs
+++ b/esp32/src/slc/_0_rxpkt_e_dscr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_RXPKT_E_DSCR")
-            .field(
-                "slc0_rx_pkt_e_dscr_addr",
-                &format_args!("{}", self.slc0_rx_pkt_e_dscr_addr().bits()),
-            )
+            .field("slc0_rx_pkt_e_dscr_addr", &self.slc0_rx_pkt_e_dscr_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_RXPKT_E_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/slc/_0_rxpkt_h_dscr.rs b/esp32/src/slc/_0_rxpkt_h_dscr.rs
index 364d5f9705..41e0adb5a8 100644
--- a/esp32/src/slc/_0_rxpkt_h_dscr.rs
+++ b/esp32/src/slc/_0_rxpkt_h_dscr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_RXPKT_H_DSCR")
-            .field(
-                "slc0_rx_pkt_h_dscr_addr",
-                &format_args!("{}", self.slc0_rx_pkt_h_dscr_addr().bits()),
-            )
+            .field("slc0_rx_pkt_h_dscr_addr", &self.slc0_rx_pkt_h_dscr_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_RXPKT_H_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/slc/_0_rxpktu_e_dscr.rs b/esp32/src/slc/_0_rxpktu_e_dscr.rs
index 3f85e04827..49dffa0522 100644
--- a/esp32/src/slc/_0_rxpktu_e_dscr.rs
+++ b/esp32/src/slc/_0_rxpktu_e_dscr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("_0_RXPKTU_E_DSCR")
             .field(
                 "slc0_rx_pkt_end_dscr_addr",
-                &format_args!("{}", self.slc0_rx_pkt_end_dscr_addr().bits()),
+                &self.slc0_rx_pkt_end_dscr_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_RXPKTU_E_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_rxpktu_e_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_RXPKTU_E_DSCR_SPEC;
 impl crate::RegisterSpec for _0_RXPKTU_E_DSCR_SPEC {
diff --git a/esp32/src/slc/_0_rxpktu_h_dscr.rs b/esp32/src/slc/_0_rxpktu_h_dscr.rs
index 8ea359cd3d..3d29d6afa3 100644
--- a/esp32/src/slc/_0_rxpktu_h_dscr.rs
+++ b/esp32/src/slc/_0_rxpktu_h_dscr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("_0_RXPKTU_H_DSCR")
             .field(
                 "slc0_rx_pkt_start_dscr_addr",
-                &format_args!("{}", self.slc0_rx_pkt_start_dscr_addr().bits()),
+                &self.slc0_rx_pkt_start_dscr_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_RXPKTU_H_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_rxpktu_h_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_RXPKTU_H_DSCR_SPEC;
 impl crate::RegisterSpec for _0_RXPKTU_H_DSCR_SPEC {
diff --git a/esp32/src/slc/_0_state0.rs b/esp32/src/slc/_0_state0.rs
index 55e92b06c9..20836b00ed 100644
--- a/esp32/src/slc/_0_state0.rs
+++ b/esp32/src/slc/_0_state0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_STATE0")
-            .field(
-                "slc0_state0",
-                &format_args!("{}", self.slc0_state0().bits()),
-            )
+            .field("slc0_state0", &self.slc0_state0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_state0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_STATE0_SPEC;
 impl crate::RegisterSpec for _0_STATE0_SPEC {
diff --git a/esp32/src/slc/_0_state1.rs b/esp32/src/slc/_0_state1.rs
index d097f879b7..969c7830cb 100644
--- a/esp32/src/slc/_0_state1.rs
+++ b/esp32/src/slc/_0_state1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_STATE1")
-            .field(
-                "slc0_state1",
-                &format_args!("{}", self.slc0_state1().bits()),
-            )
+            .field("slc0_state1", &self.slc0_state1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_STATE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_state1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_STATE1_SPEC;
 impl crate::RegisterSpec for _0_STATE1_SPEC {
diff --git a/esp32/src/slc/_0_sub_start_des.rs b/esp32/src/slc/_0_sub_start_des.rs
index 2fd698f88d..e088237eed 100644
--- a/esp32/src/slc/_0_sub_start_des.rs
+++ b/esp32/src/slc/_0_sub_start_des.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("_0_SUB_START_DES")
             .field(
                 "slc0_sub_pac_start_dscr_addr",
-                &format_args!("{}", self.slc0_sub_pac_start_dscr_addr().bits()),
+                &self.slc0_sub_pac_start_dscr_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_SUB_START_DES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_sub_start_des::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_SUB_START_DES_SPEC;
 impl crate::RegisterSpec for _0_SUB_START_DES_SPEC {
diff --git a/esp32/src/slc/_0_to_eof_bfr_des_addr.rs b/esp32/src/slc/_0_to_eof_bfr_des_addr.rs
index fe6929c646..baf6467b6b 100644
--- a/esp32/src/slc/_0_to_eof_bfr_des_addr.rs
+++ b/esp32/src/slc/_0_to_eof_bfr_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_TO_EOF_BFR_DES_ADDR")
-            .field(
-                "slc0_to_eof_bfr_des_addr",
-                &format_args!("{}", self.slc0_to_eof_bfr_des_addr().bits()),
-            )
+            .field("slc0_to_eof_bfr_des_addr", &self.slc0_to_eof_bfr_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_TO_EOF_BFR_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_to_eof_bfr_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_TO_EOF_BFR_DES_ADDR_SPEC;
 impl crate::RegisterSpec for _0_TO_EOF_BFR_DES_ADDR_SPEC {
diff --git a/esp32/src/slc/_0_to_eof_des_addr.rs b/esp32/src/slc/_0_to_eof_des_addr.rs
index ce47a91741..232bf3fa3a 100644
--- a/esp32/src/slc/_0_to_eof_des_addr.rs
+++ b/esp32/src/slc/_0_to_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_TO_EOF_DES_ADDR")
-            .field(
-                "slc0_to_eof_des_addr",
-                &format_args!("{}", self.slc0_to_eof_des_addr().bits()),
-            )
+            .field("slc0_to_eof_des_addr", &self.slc0_to_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_TO_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_to_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_TO_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for _0_TO_EOF_DES_ADDR_SPEC {
diff --git a/esp32/src/slc/_0_tx_eof_des_addr.rs b/esp32/src/slc/_0_tx_eof_des_addr.rs
index 50292e496c..6968b9f0d5 100644
--- a/esp32/src/slc/_0_tx_eof_des_addr.rs
+++ b/esp32/src/slc/_0_tx_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_TX_EOF_DES_ADDR")
-            .field(
-                "slc0_tx_suc_eof_des_addr",
-                &format_args!("{}", self.slc0_tx_suc_eof_des_addr().bits()),
-            )
+            .field("slc0_tx_suc_eof_des_addr", &self.slc0_tx_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_TX_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_tx_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_TX_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for _0_TX_EOF_DES_ADDR_SPEC {
diff --git a/esp32/src/slc/_0_tx_erreof_des_addr.rs b/esp32/src/slc/_0_tx_erreof_des_addr.rs
index 6acf30ea66..fd2838f5fd 100644
--- a/esp32/src/slc/_0_tx_erreof_des_addr.rs
+++ b/esp32/src/slc/_0_tx_erreof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_TX_ERREOF_DES_ADDR")
-            .field(
-                "slc0_tx_err_eof_des_addr",
-                &format_args!("{}", self.slc0_tx_err_eof_des_addr().bits()),
-            )
+            .field("slc0_tx_err_eof_des_addr", &self.slc0_tx_err_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_TX_ERREOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_tx_erreof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_TX_ERREOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for _0_TX_ERREOF_DES_ADDR_SPEC {
diff --git a/esp32/src/slc/_0_txlink_dscr.rs b/esp32/src/slc/_0_txlink_dscr.rs
index f3adbe96f8..c15df9bdcb 100644
--- a/esp32/src/slc/_0_txlink_dscr.rs
+++ b/esp32/src/slc/_0_txlink_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_TXLINK_DSCR")
-            .field(
-                "slc0_txlink_dscr",
-                &format_args!("{}", self.slc0_txlink_dscr().bits()),
-            )
+            .field("slc0_txlink_dscr", &self.slc0_txlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_TXLINK_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_txlink_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_TXLINK_DSCR_SPEC;
 impl crate::RegisterSpec for _0_TXLINK_DSCR_SPEC {
diff --git a/esp32/src/slc/_0_txlink_dscr_bf0.rs b/esp32/src/slc/_0_txlink_dscr_bf0.rs
index 63a993f81c..524c2035eb 100644
--- a/esp32/src/slc/_0_txlink_dscr_bf0.rs
+++ b/esp32/src/slc/_0_txlink_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_TXLINK_DSCR_BF0")
-            .field(
-                "slc0_txlink_dscr_bf0",
-                &format_args!("{}", self.slc0_txlink_dscr_bf0().bits()),
-            )
+            .field("slc0_txlink_dscr_bf0", &self.slc0_txlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_TXLINK_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_txlink_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_TXLINK_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for _0_TXLINK_DSCR_BF0_SPEC {
diff --git a/esp32/src/slc/_0_txlink_dscr_bf1.rs b/esp32/src/slc/_0_txlink_dscr_bf1.rs
index 3fe72900c8..445eb98a87 100644
--- a/esp32/src/slc/_0_txlink_dscr_bf1.rs
+++ b/esp32/src/slc/_0_txlink_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_TXLINK_DSCR_BF1")
-            .field(
-                "slc0_txlink_dscr_bf1",
-                &format_args!("{}", self.slc0_txlink_dscr_bf1().bits()),
-            )
+            .field("slc0_txlink_dscr_bf1", &self.slc0_txlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_TXLINK_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_txlink_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_TXLINK_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for _0_TXLINK_DSCR_BF1_SPEC {
diff --git a/esp32/src/slc/_0_txpkt_e_dscr.rs b/esp32/src/slc/_0_txpkt_e_dscr.rs
index 670714ab97..86986137bb 100644
--- a/esp32/src/slc/_0_txpkt_e_dscr.rs
+++ b/esp32/src/slc/_0_txpkt_e_dscr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_TXPKT_E_DSCR")
-            .field(
-                "slc0_tx_pkt_e_dscr_addr",
-                &format_args!("{}", self.slc0_tx_pkt_e_dscr_addr().bits()),
-            )
+            .field("slc0_tx_pkt_e_dscr_addr", &self.slc0_tx_pkt_e_dscr_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_TXPKT_E_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/slc/_0_txpkt_h_dscr.rs b/esp32/src/slc/_0_txpkt_h_dscr.rs
index 698eb72df0..d30409ca6b 100644
--- a/esp32/src/slc/_0_txpkt_h_dscr.rs
+++ b/esp32/src/slc/_0_txpkt_h_dscr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0_TXPKT_H_DSCR")
-            .field(
-                "slc0_tx_pkt_h_dscr_addr",
-                &format_args!("{}", self.slc0_tx_pkt_h_dscr_addr().bits()),
-            )
+            .field("slc0_tx_pkt_h_dscr_addr", &self.slc0_tx_pkt_h_dscr_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_TXPKT_H_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/slc/_0_txpktu_e_dscr.rs b/esp32/src/slc/_0_txpktu_e_dscr.rs
index 810d6ce491..8649589e57 100644
--- a/esp32/src/slc/_0_txpktu_e_dscr.rs
+++ b/esp32/src/slc/_0_txpktu_e_dscr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("_0_TXPKTU_E_DSCR")
             .field(
                 "slc0_tx_pkt_end_dscr_addr",
-                &format_args!("{}", self.slc0_tx_pkt_end_dscr_addr().bits()),
+                &self.slc0_tx_pkt_end_dscr_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_TXPKTU_E_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_txpktu_e_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_TXPKTU_E_DSCR_SPEC;
 impl crate::RegisterSpec for _0_TXPKTU_E_DSCR_SPEC {
diff --git a/esp32/src/slc/_0_txpktu_h_dscr.rs b/esp32/src/slc/_0_txpktu_h_dscr.rs
index 571a458744..6dd2cd0659 100644
--- a/esp32/src/slc/_0_txpktu_h_dscr.rs
+++ b/esp32/src/slc/_0_txpktu_h_dscr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("_0_TXPKTU_H_DSCR")
             .field(
                 "slc0_tx_pkt_start_dscr_addr",
-                &format_args!("{}", self.slc0_tx_pkt_start_dscr_addr().bits()),
+                &self.slc0_tx_pkt_start_dscr_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0_TXPKTU_H_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0_txpktu_h_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0_TXPKTU_H_DSCR_SPEC;
 impl crate::RegisterSpec for _0_TXPKTU_H_DSCR_SPEC {
diff --git a/esp32/src/slc/_0int_ena.rs b/esp32/src/slc/_0int_ena.rs
index 14066a83b5..356da24a01 100644
--- a/esp32/src/slc/_0int_ena.rs
+++ b/esp32/src/slc/_0int_ena.rs
@@ -251,123 +251,45 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0INT_ENA")
-            .field(
-                "frhost_bit0_int_ena",
-                &format_args!("{}", self.frhost_bit0_int_ena().bit()),
-            )
-            .field(
-                "frhost_bit1_int_ena",
-                &format_args!("{}", self.frhost_bit1_int_ena().bit()),
-            )
-            .field(
-                "frhost_bit2_int_ena",
-                &format_args!("{}", self.frhost_bit2_int_ena().bit()),
-            )
-            .field(
-                "frhost_bit3_int_ena",
-                &format_args!("{}", self.frhost_bit3_int_ena().bit()),
-            )
-            .field(
-                "frhost_bit4_int_ena",
-                &format_args!("{}", self.frhost_bit4_int_ena().bit()),
-            )
-            .field(
-                "frhost_bit5_int_ena",
-                &format_args!("{}", self.frhost_bit5_int_ena().bit()),
-            )
-            .field(
-                "frhost_bit6_int_ena",
-                &format_args!("{}", self.frhost_bit6_int_ena().bit()),
-            )
-            .field(
-                "frhost_bit7_int_ena",
-                &format_args!("{}", self.frhost_bit7_int_ena().bit()),
-            )
-            .field(
-                "slc0_rx_start_int_ena",
-                &format_args!("{}", self.slc0_rx_start_int_ena().bit()),
-            )
-            .field(
-                "slc0_tx_start_int_ena",
-                &format_args!("{}", self.slc0_tx_start_int_ena().bit()),
-            )
-            .field(
-                "slc0_rx_udf_int_ena",
-                &format_args!("{}", self.slc0_rx_udf_int_ena().bit()),
-            )
-            .field(
-                "slc0_tx_ovf_int_ena",
-                &format_args!("{}", self.slc0_tx_ovf_int_ena().bit()),
-            )
-            .field(
-                "slc0_token0_1to0_int_ena",
-                &format_args!("{}", self.slc0_token0_1to0_int_ena().bit()),
-            )
-            .field(
-                "slc0_token1_1to0_int_ena",
-                &format_args!("{}", self.slc0_token1_1to0_int_ena().bit()),
-            )
-            .field(
-                "slc0_tx_done_int_ena",
-                &format_args!("{}", self.slc0_tx_done_int_ena().bit()),
-            )
-            .field(
-                "slc0_tx_suc_eof_int_ena",
-                &format_args!("{}", self.slc0_tx_suc_eof_int_ena().bit()),
-            )
-            .field(
-                "slc0_rx_done_int_ena",
-                &format_args!("{}", self.slc0_rx_done_int_ena().bit()),
-            )
-            .field(
-                "slc0_rx_eof_int_ena",
-                &format_args!("{}", self.slc0_rx_eof_int_ena().bit()),
-            )
-            .field(
-                "slc0_tohost_int_ena",
-                &format_args!("{}", self.slc0_tohost_int_ena().bit()),
-            )
-            .field(
-                "slc0_tx_dscr_err_int_ena",
-                &format_args!("{}", self.slc0_tx_dscr_err_int_ena().bit()),
-            )
-            .field(
-                "slc0_rx_dscr_err_int_ena",
-                &format_args!("{}", self.slc0_rx_dscr_err_int_ena().bit()),
-            )
+            .field("frhost_bit0_int_ena", &self.frhost_bit0_int_ena())
+            .field("frhost_bit1_int_ena", &self.frhost_bit1_int_ena())
+            .field("frhost_bit2_int_ena", &self.frhost_bit2_int_ena())
+            .field("frhost_bit3_int_ena", &self.frhost_bit3_int_ena())
+            .field("frhost_bit4_int_ena", &self.frhost_bit4_int_ena())
+            .field("frhost_bit5_int_ena", &self.frhost_bit5_int_ena())
+            .field("frhost_bit6_int_ena", &self.frhost_bit6_int_ena())
+            .field("frhost_bit7_int_ena", &self.frhost_bit7_int_ena())
+            .field("slc0_rx_start_int_ena", &self.slc0_rx_start_int_ena())
+            .field("slc0_tx_start_int_ena", &self.slc0_tx_start_int_ena())
+            .field("slc0_rx_udf_int_ena", &self.slc0_rx_udf_int_ena())
+            .field("slc0_tx_ovf_int_ena", &self.slc0_tx_ovf_int_ena())
+            .field("slc0_token0_1to0_int_ena", &self.slc0_token0_1to0_int_ena())
+            .field("slc0_token1_1to0_int_ena", &self.slc0_token1_1to0_int_ena())
+            .field("slc0_tx_done_int_ena", &self.slc0_tx_done_int_ena())
+            .field("slc0_tx_suc_eof_int_ena", &self.slc0_tx_suc_eof_int_ena())
+            .field("slc0_rx_done_int_ena", &self.slc0_rx_done_int_ena())
+            .field("slc0_rx_eof_int_ena", &self.slc0_rx_eof_int_ena())
+            .field("slc0_tohost_int_ena", &self.slc0_tohost_int_ena())
+            .field("slc0_tx_dscr_err_int_ena", &self.slc0_tx_dscr_err_int_ena())
+            .field("slc0_rx_dscr_err_int_ena", &self.slc0_rx_dscr_err_int_ena())
             .field(
                 "slc0_tx_dscr_empty_int_ena",
-                &format_args!("{}", self.slc0_tx_dscr_empty_int_ena().bit()),
-            )
-            .field(
-                "slc0_host_rd_ack_int_ena",
-                &format_args!("{}", self.slc0_host_rd_ack_int_ena().bit()),
+                &self.slc0_tx_dscr_empty_int_ena(),
             )
+            .field("slc0_host_rd_ack_int_ena", &self.slc0_host_rd_ack_int_ena())
             .field(
                 "slc0_wr_retry_done_int_ena",
-                &format_args!("{}", self.slc0_wr_retry_done_int_ena().bit()),
-            )
-            .field(
-                "slc0_tx_err_eof_int_ena",
-                &format_args!("{}", self.slc0_tx_err_eof_int_ena().bit()),
-            )
-            .field(
-                "cmd_dtc_int_ena",
-                &format_args!("{}", self.cmd_dtc_int_ena().bit()),
+                &self.slc0_wr_retry_done_int_ena(),
             )
+            .field("slc0_tx_err_eof_int_ena", &self.slc0_tx_err_eof_int_ena())
+            .field("cmd_dtc_int_ena", &self.cmd_dtc_int_ena())
             .field(
                 "slc0_rx_quick_eof_int_ena",
-                &format_args!("{}", self.slc0_rx_quick_eof_int_ena().bit()),
+                &self.slc0_rx_quick_eof_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slc/_0int_ena1.rs b/esp32/src/slc/_0int_ena1.rs
index 2ed77461e3..eb60fd893c 100644
--- a/esp32/src/slc/_0int_ena1.rs
+++ b/esp32/src/slc/_0int_ena1.rs
@@ -251,123 +251,60 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0INT_ENA1")
-            .field(
-                "frhost_bit0_int_ena1",
-                &format_args!("{}", self.frhost_bit0_int_ena1().bit()),
-            )
-            .field(
-                "frhost_bit1_int_ena1",
-                &format_args!("{}", self.frhost_bit1_int_ena1().bit()),
-            )
-            .field(
-                "frhost_bit2_int_ena1",
-                &format_args!("{}", self.frhost_bit2_int_ena1().bit()),
-            )
-            .field(
-                "frhost_bit3_int_ena1",
-                &format_args!("{}", self.frhost_bit3_int_ena1().bit()),
-            )
-            .field(
-                "frhost_bit4_int_ena1",
-                &format_args!("{}", self.frhost_bit4_int_ena1().bit()),
-            )
-            .field(
-                "frhost_bit5_int_ena1",
-                &format_args!("{}", self.frhost_bit5_int_ena1().bit()),
-            )
-            .field(
-                "frhost_bit6_int_ena1",
-                &format_args!("{}", self.frhost_bit6_int_ena1().bit()),
-            )
-            .field(
-                "frhost_bit7_int_ena1",
-                &format_args!("{}", self.frhost_bit7_int_ena1().bit()),
-            )
-            .field(
-                "slc0_rx_start_int_ena1",
-                &format_args!("{}", self.slc0_rx_start_int_ena1().bit()),
-            )
-            .field(
-                "slc0_tx_start_int_ena1",
-                &format_args!("{}", self.slc0_tx_start_int_ena1().bit()),
-            )
-            .field(
-                "slc0_rx_udf_int_ena1",
-                &format_args!("{}", self.slc0_rx_udf_int_ena1().bit()),
-            )
-            .field(
-                "slc0_tx_ovf_int_ena1",
-                &format_args!("{}", self.slc0_tx_ovf_int_ena1().bit()),
-            )
+            .field("frhost_bit0_int_ena1", &self.frhost_bit0_int_ena1())
+            .field("frhost_bit1_int_ena1", &self.frhost_bit1_int_ena1())
+            .field("frhost_bit2_int_ena1", &self.frhost_bit2_int_ena1())
+            .field("frhost_bit3_int_ena1", &self.frhost_bit3_int_ena1())
+            .field("frhost_bit4_int_ena1", &self.frhost_bit4_int_ena1())
+            .field("frhost_bit5_int_ena1", &self.frhost_bit5_int_ena1())
+            .field("frhost_bit6_int_ena1", &self.frhost_bit6_int_ena1())
+            .field("frhost_bit7_int_ena1", &self.frhost_bit7_int_ena1())
+            .field("slc0_rx_start_int_ena1", &self.slc0_rx_start_int_ena1())
+            .field("slc0_tx_start_int_ena1", &self.slc0_tx_start_int_ena1())
+            .field("slc0_rx_udf_int_ena1", &self.slc0_rx_udf_int_ena1())
+            .field("slc0_tx_ovf_int_ena1", &self.slc0_tx_ovf_int_ena1())
             .field(
                 "slc0_token0_1to0_int_ena1",
-                &format_args!("{}", self.slc0_token0_1to0_int_ena1().bit()),
+                &self.slc0_token0_1to0_int_ena1(),
             )
             .field(
                 "slc0_token1_1to0_int_ena1",
-                &format_args!("{}", self.slc0_token1_1to0_int_ena1().bit()),
-            )
-            .field(
-                "slc0_tx_done_int_ena1",
-                &format_args!("{}", self.slc0_tx_done_int_ena1().bit()),
-            )
-            .field(
-                "slc0_tx_suc_eof_int_ena1",
-                &format_args!("{}", self.slc0_tx_suc_eof_int_ena1().bit()),
-            )
-            .field(
-                "slc0_rx_done_int_ena1",
-                &format_args!("{}", self.slc0_rx_done_int_ena1().bit()),
-            )
-            .field(
-                "slc0_rx_eof_int_ena1",
-                &format_args!("{}", self.slc0_rx_eof_int_ena1().bit()),
-            )
-            .field(
-                "slc0_tohost_int_ena1",
-                &format_args!("{}", self.slc0_tohost_int_ena1().bit()),
+                &self.slc0_token1_1to0_int_ena1(),
             )
+            .field("slc0_tx_done_int_ena1", &self.slc0_tx_done_int_ena1())
+            .field("slc0_tx_suc_eof_int_ena1", &self.slc0_tx_suc_eof_int_ena1())
+            .field("slc0_rx_done_int_ena1", &self.slc0_rx_done_int_ena1())
+            .field("slc0_rx_eof_int_ena1", &self.slc0_rx_eof_int_ena1())
+            .field("slc0_tohost_int_ena1", &self.slc0_tohost_int_ena1())
             .field(
                 "slc0_tx_dscr_err_int_ena1",
-                &format_args!("{}", self.slc0_tx_dscr_err_int_ena1().bit()),
+                &self.slc0_tx_dscr_err_int_ena1(),
             )
             .field(
                 "slc0_rx_dscr_err_int_ena1",
-                &format_args!("{}", self.slc0_rx_dscr_err_int_ena1().bit()),
+                &self.slc0_rx_dscr_err_int_ena1(),
             )
             .field(
                 "slc0_tx_dscr_empty_int_ena1",
-                &format_args!("{}", self.slc0_tx_dscr_empty_int_ena1().bit()),
+                &self.slc0_tx_dscr_empty_int_ena1(),
             )
             .field(
                 "slc0_host_rd_ack_int_ena1",
-                &format_args!("{}", self.slc0_host_rd_ack_int_ena1().bit()),
+                &self.slc0_host_rd_ack_int_ena1(),
             )
             .field(
                 "slc0_wr_retry_done_int_ena1",
-                &format_args!("{}", self.slc0_wr_retry_done_int_ena1().bit()),
-            )
-            .field(
-                "slc0_tx_err_eof_int_ena1",
-                &format_args!("{}", self.slc0_tx_err_eof_int_ena1().bit()),
-            )
-            .field(
-                "cmd_dtc_int_ena1",
-                &format_args!("{}", self.cmd_dtc_int_ena1().bit()),
+                &self.slc0_wr_retry_done_int_ena1(),
             )
+            .field("slc0_tx_err_eof_int_ena1", &self.slc0_tx_err_eof_int_ena1())
+            .field("cmd_dtc_int_ena1", &self.cmd_dtc_int_ena1())
             .field(
                 "slc0_rx_quick_eof_int_ena1",
-                &format_args!("{}", self.slc0_rx_quick_eof_int_ena1().bit()),
+                &self.slc0_rx_quick_eof_int_ena1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0INT_ENA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slc/_0int_raw.rs b/esp32/src/slc/_0int_raw.rs
index b910e579b3..9aa9460cf2 100644
--- a/esp32/src/slc/_0int_raw.rs
+++ b/esp32/src/slc/_0int_raw.rs
@@ -195,123 +195,45 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0INT_RAW")
-            .field(
-                "frhost_bit0_int_raw",
-                &format_args!("{}", self.frhost_bit0_int_raw().bit()),
-            )
-            .field(
-                "frhost_bit1_int_raw",
-                &format_args!("{}", self.frhost_bit1_int_raw().bit()),
-            )
-            .field(
-                "frhost_bit2_int_raw",
-                &format_args!("{}", self.frhost_bit2_int_raw().bit()),
-            )
-            .field(
-                "frhost_bit3_int_raw",
-                &format_args!("{}", self.frhost_bit3_int_raw().bit()),
-            )
-            .field(
-                "frhost_bit4_int_raw",
-                &format_args!("{}", self.frhost_bit4_int_raw().bit()),
-            )
-            .field(
-                "frhost_bit5_int_raw",
-                &format_args!("{}", self.frhost_bit5_int_raw().bit()),
-            )
-            .field(
-                "frhost_bit6_int_raw",
-                &format_args!("{}", self.frhost_bit6_int_raw().bit()),
-            )
-            .field(
-                "frhost_bit7_int_raw",
-                &format_args!("{}", self.frhost_bit7_int_raw().bit()),
-            )
-            .field(
-                "slc0_rx_start_int_raw",
-                &format_args!("{}", self.slc0_rx_start_int_raw().bit()),
-            )
-            .field(
-                "slc0_tx_start_int_raw",
-                &format_args!("{}", self.slc0_tx_start_int_raw().bit()),
-            )
-            .field(
-                "slc0_rx_udf_int_raw",
-                &format_args!("{}", self.slc0_rx_udf_int_raw().bit()),
-            )
-            .field(
-                "slc0_tx_ovf_int_raw",
-                &format_args!("{}", self.slc0_tx_ovf_int_raw().bit()),
-            )
-            .field(
-                "slc0_token0_1to0_int_raw",
-                &format_args!("{}", self.slc0_token0_1to0_int_raw().bit()),
-            )
-            .field(
-                "slc0_token1_1to0_int_raw",
-                &format_args!("{}", self.slc0_token1_1to0_int_raw().bit()),
-            )
-            .field(
-                "slc0_tx_done_int_raw",
-                &format_args!("{}", self.slc0_tx_done_int_raw().bit()),
-            )
-            .field(
-                "slc0_tx_suc_eof_int_raw",
-                &format_args!("{}", self.slc0_tx_suc_eof_int_raw().bit()),
-            )
-            .field(
-                "slc0_rx_done_int_raw",
-                &format_args!("{}", self.slc0_rx_done_int_raw().bit()),
-            )
-            .field(
-                "slc0_rx_eof_int_raw",
-                &format_args!("{}", self.slc0_rx_eof_int_raw().bit()),
-            )
-            .field(
-                "slc0_tohost_int_raw",
-                &format_args!("{}", self.slc0_tohost_int_raw().bit()),
-            )
-            .field(
-                "slc0_tx_dscr_err_int_raw",
-                &format_args!("{}", self.slc0_tx_dscr_err_int_raw().bit()),
-            )
-            .field(
-                "slc0_rx_dscr_err_int_raw",
-                &format_args!("{}", self.slc0_rx_dscr_err_int_raw().bit()),
-            )
+            .field("frhost_bit0_int_raw", &self.frhost_bit0_int_raw())
+            .field("frhost_bit1_int_raw", &self.frhost_bit1_int_raw())
+            .field("frhost_bit2_int_raw", &self.frhost_bit2_int_raw())
+            .field("frhost_bit3_int_raw", &self.frhost_bit3_int_raw())
+            .field("frhost_bit4_int_raw", &self.frhost_bit4_int_raw())
+            .field("frhost_bit5_int_raw", &self.frhost_bit5_int_raw())
+            .field("frhost_bit6_int_raw", &self.frhost_bit6_int_raw())
+            .field("frhost_bit7_int_raw", &self.frhost_bit7_int_raw())
+            .field("slc0_rx_start_int_raw", &self.slc0_rx_start_int_raw())
+            .field("slc0_tx_start_int_raw", &self.slc0_tx_start_int_raw())
+            .field("slc0_rx_udf_int_raw", &self.slc0_rx_udf_int_raw())
+            .field("slc0_tx_ovf_int_raw", &self.slc0_tx_ovf_int_raw())
+            .field("slc0_token0_1to0_int_raw", &self.slc0_token0_1to0_int_raw())
+            .field("slc0_token1_1to0_int_raw", &self.slc0_token1_1to0_int_raw())
+            .field("slc0_tx_done_int_raw", &self.slc0_tx_done_int_raw())
+            .field("slc0_tx_suc_eof_int_raw", &self.slc0_tx_suc_eof_int_raw())
+            .field("slc0_rx_done_int_raw", &self.slc0_rx_done_int_raw())
+            .field("slc0_rx_eof_int_raw", &self.slc0_rx_eof_int_raw())
+            .field("slc0_tohost_int_raw", &self.slc0_tohost_int_raw())
+            .field("slc0_tx_dscr_err_int_raw", &self.slc0_tx_dscr_err_int_raw())
+            .field("slc0_rx_dscr_err_int_raw", &self.slc0_rx_dscr_err_int_raw())
             .field(
                 "slc0_tx_dscr_empty_int_raw",
-                &format_args!("{}", self.slc0_tx_dscr_empty_int_raw().bit()),
-            )
-            .field(
-                "slc0_host_rd_ack_int_raw",
-                &format_args!("{}", self.slc0_host_rd_ack_int_raw().bit()),
+                &self.slc0_tx_dscr_empty_int_raw(),
             )
+            .field("slc0_host_rd_ack_int_raw", &self.slc0_host_rd_ack_int_raw())
             .field(
                 "slc0_wr_retry_done_int_raw",
-                &format_args!("{}", self.slc0_wr_retry_done_int_raw().bit()),
-            )
-            .field(
-                "slc0_tx_err_eof_int_raw",
-                &format_args!("{}", self.slc0_tx_err_eof_int_raw().bit()),
-            )
-            .field(
-                "cmd_dtc_int_raw",
-                &format_args!("{}", self.cmd_dtc_int_raw().bit()),
+                &self.slc0_wr_retry_done_int_raw(),
             )
+            .field("slc0_tx_err_eof_int_raw", &self.slc0_tx_err_eof_int_raw())
+            .field("cmd_dtc_int_raw", &self.cmd_dtc_int_raw())
             .field(
                 "slc0_rx_quick_eof_int_raw",
-                &format_args!("{}", self.slc0_rx_quick_eof_int_raw().bit()),
+                &self.slc0_rx_quick_eof_int_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0INT_RAW_SPEC;
 impl crate::RegisterSpec for _0INT_RAW_SPEC {
diff --git a/esp32/src/slc/_0int_st.rs b/esp32/src/slc/_0int_st.rs
index 0343960e1e..eeb22fe38f 100644
--- a/esp32/src/slc/_0int_st.rs
+++ b/esp32/src/slc/_0int_st.rs
@@ -195,123 +195,42 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0INT_ST")
-            .field(
-                "frhost_bit0_int_st",
-                &format_args!("{}", self.frhost_bit0_int_st().bit()),
-            )
-            .field(
-                "frhost_bit1_int_st",
-                &format_args!("{}", self.frhost_bit1_int_st().bit()),
-            )
-            .field(
-                "frhost_bit2_int_st",
-                &format_args!("{}", self.frhost_bit2_int_st().bit()),
-            )
-            .field(
-                "frhost_bit3_int_st",
-                &format_args!("{}", self.frhost_bit3_int_st().bit()),
-            )
-            .field(
-                "frhost_bit4_int_st",
-                &format_args!("{}", self.frhost_bit4_int_st().bit()),
-            )
-            .field(
-                "frhost_bit5_int_st",
-                &format_args!("{}", self.frhost_bit5_int_st().bit()),
-            )
-            .field(
-                "frhost_bit6_int_st",
-                &format_args!("{}", self.frhost_bit6_int_st().bit()),
-            )
-            .field(
-                "frhost_bit7_int_st",
-                &format_args!("{}", self.frhost_bit7_int_st().bit()),
-            )
-            .field(
-                "slc0_rx_start_int_st",
-                &format_args!("{}", self.slc0_rx_start_int_st().bit()),
-            )
-            .field(
-                "slc0_tx_start_int_st",
-                &format_args!("{}", self.slc0_tx_start_int_st().bit()),
-            )
-            .field(
-                "slc0_rx_udf_int_st",
-                &format_args!("{}", self.slc0_rx_udf_int_st().bit()),
-            )
-            .field(
-                "slc0_tx_ovf_int_st",
-                &format_args!("{}", self.slc0_tx_ovf_int_st().bit()),
-            )
-            .field(
-                "slc0_token0_1to0_int_st",
-                &format_args!("{}", self.slc0_token0_1to0_int_st().bit()),
-            )
-            .field(
-                "slc0_token1_1to0_int_st",
-                &format_args!("{}", self.slc0_token1_1to0_int_st().bit()),
-            )
-            .field(
-                "slc0_tx_done_int_st",
-                &format_args!("{}", self.slc0_tx_done_int_st().bit()),
-            )
-            .field(
-                "slc0_tx_suc_eof_int_st",
-                &format_args!("{}", self.slc0_tx_suc_eof_int_st().bit()),
-            )
-            .field(
-                "slc0_rx_done_int_st",
-                &format_args!("{}", self.slc0_rx_done_int_st().bit()),
-            )
-            .field(
-                "slc0_rx_eof_int_st",
-                &format_args!("{}", self.slc0_rx_eof_int_st().bit()),
-            )
-            .field(
-                "slc0_tohost_int_st",
-                &format_args!("{}", self.slc0_tohost_int_st().bit()),
-            )
-            .field(
-                "slc0_tx_dscr_err_int_st",
-                &format_args!("{}", self.slc0_tx_dscr_err_int_st().bit()),
-            )
-            .field(
-                "slc0_rx_dscr_err_int_st",
-                &format_args!("{}", self.slc0_rx_dscr_err_int_st().bit()),
-            )
+            .field("frhost_bit0_int_st", &self.frhost_bit0_int_st())
+            .field("frhost_bit1_int_st", &self.frhost_bit1_int_st())
+            .field("frhost_bit2_int_st", &self.frhost_bit2_int_st())
+            .field("frhost_bit3_int_st", &self.frhost_bit3_int_st())
+            .field("frhost_bit4_int_st", &self.frhost_bit4_int_st())
+            .field("frhost_bit5_int_st", &self.frhost_bit5_int_st())
+            .field("frhost_bit6_int_st", &self.frhost_bit6_int_st())
+            .field("frhost_bit7_int_st", &self.frhost_bit7_int_st())
+            .field("slc0_rx_start_int_st", &self.slc0_rx_start_int_st())
+            .field("slc0_tx_start_int_st", &self.slc0_tx_start_int_st())
+            .field("slc0_rx_udf_int_st", &self.slc0_rx_udf_int_st())
+            .field("slc0_tx_ovf_int_st", &self.slc0_tx_ovf_int_st())
+            .field("slc0_token0_1to0_int_st", &self.slc0_token0_1to0_int_st())
+            .field("slc0_token1_1to0_int_st", &self.slc0_token1_1to0_int_st())
+            .field("slc0_tx_done_int_st", &self.slc0_tx_done_int_st())
+            .field("slc0_tx_suc_eof_int_st", &self.slc0_tx_suc_eof_int_st())
+            .field("slc0_rx_done_int_st", &self.slc0_rx_done_int_st())
+            .field("slc0_rx_eof_int_st", &self.slc0_rx_eof_int_st())
+            .field("slc0_tohost_int_st", &self.slc0_tohost_int_st())
+            .field("slc0_tx_dscr_err_int_st", &self.slc0_tx_dscr_err_int_st())
+            .field("slc0_rx_dscr_err_int_st", &self.slc0_rx_dscr_err_int_st())
             .field(
                 "slc0_tx_dscr_empty_int_st",
-                &format_args!("{}", self.slc0_tx_dscr_empty_int_st().bit()),
-            )
-            .field(
-                "slc0_host_rd_ack_int_st",
-                &format_args!("{}", self.slc0_host_rd_ack_int_st().bit()),
+                &self.slc0_tx_dscr_empty_int_st(),
             )
+            .field("slc0_host_rd_ack_int_st", &self.slc0_host_rd_ack_int_st())
             .field(
                 "slc0_wr_retry_done_int_st",
-                &format_args!("{}", self.slc0_wr_retry_done_int_st().bit()),
-            )
-            .field(
-                "slc0_tx_err_eof_int_st",
-                &format_args!("{}", self.slc0_tx_err_eof_int_st().bit()),
-            )
-            .field(
-                "cmd_dtc_int_st",
-                &format_args!("{}", self.cmd_dtc_int_st().bit()),
-            )
-            .field(
-                "slc0_rx_quick_eof_int_st",
-                &format_args!("{}", self.slc0_rx_quick_eof_int_st().bit()),
+                &self.slc0_wr_retry_done_int_st(),
             )
+            .field("slc0_tx_err_eof_int_st", &self.slc0_tx_err_eof_int_st())
+            .field("cmd_dtc_int_st", &self.cmd_dtc_int_st())
+            .field("slc0_rx_quick_eof_int_st", &self.slc0_rx_quick_eof_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0INT_ST_SPEC;
 impl crate::RegisterSpec for _0INT_ST_SPEC {
diff --git a/esp32/src/slc/_0int_st1.rs b/esp32/src/slc/_0int_st1.rs
index 7acb459928..a46427a719 100644
--- a/esp32/src/slc/_0int_st1.rs
+++ b/esp32/src/slc/_0int_st1.rs
@@ -195,123 +195,45 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0INT_ST1")
-            .field(
-                "frhost_bit0_int_st1",
-                &format_args!("{}", self.frhost_bit0_int_st1().bit()),
-            )
-            .field(
-                "frhost_bit1_int_st1",
-                &format_args!("{}", self.frhost_bit1_int_st1().bit()),
-            )
-            .field(
-                "frhost_bit2_int_st1",
-                &format_args!("{}", self.frhost_bit2_int_st1().bit()),
-            )
-            .field(
-                "frhost_bit3_int_st1",
-                &format_args!("{}", self.frhost_bit3_int_st1().bit()),
-            )
-            .field(
-                "frhost_bit4_int_st1",
-                &format_args!("{}", self.frhost_bit4_int_st1().bit()),
-            )
-            .field(
-                "frhost_bit5_int_st1",
-                &format_args!("{}", self.frhost_bit5_int_st1().bit()),
-            )
-            .field(
-                "frhost_bit6_int_st1",
-                &format_args!("{}", self.frhost_bit6_int_st1().bit()),
-            )
-            .field(
-                "frhost_bit7_int_st1",
-                &format_args!("{}", self.frhost_bit7_int_st1().bit()),
-            )
-            .field(
-                "slc0_rx_start_int_st1",
-                &format_args!("{}", self.slc0_rx_start_int_st1().bit()),
-            )
-            .field(
-                "slc0_tx_start_int_st1",
-                &format_args!("{}", self.slc0_tx_start_int_st1().bit()),
-            )
-            .field(
-                "slc0_rx_udf_int_st1",
-                &format_args!("{}", self.slc0_rx_udf_int_st1().bit()),
-            )
-            .field(
-                "slc0_tx_ovf_int_st1",
-                &format_args!("{}", self.slc0_tx_ovf_int_st1().bit()),
-            )
-            .field(
-                "slc0_token0_1to0_int_st1",
-                &format_args!("{}", self.slc0_token0_1to0_int_st1().bit()),
-            )
-            .field(
-                "slc0_token1_1to0_int_st1",
-                &format_args!("{}", self.slc0_token1_1to0_int_st1().bit()),
-            )
-            .field(
-                "slc0_tx_done_int_st1",
-                &format_args!("{}", self.slc0_tx_done_int_st1().bit()),
-            )
-            .field(
-                "slc0_tx_suc_eof_int_st1",
-                &format_args!("{}", self.slc0_tx_suc_eof_int_st1().bit()),
-            )
-            .field(
-                "slc0_rx_done_int_st1",
-                &format_args!("{}", self.slc0_rx_done_int_st1().bit()),
-            )
-            .field(
-                "slc0_rx_eof_int_st1",
-                &format_args!("{}", self.slc0_rx_eof_int_st1().bit()),
-            )
-            .field(
-                "slc0_tohost_int_st1",
-                &format_args!("{}", self.slc0_tohost_int_st1().bit()),
-            )
-            .field(
-                "slc0_tx_dscr_err_int_st1",
-                &format_args!("{}", self.slc0_tx_dscr_err_int_st1().bit()),
-            )
-            .field(
-                "slc0_rx_dscr_err_int_st1",
-                &format_args!("{}", self.slc0_rx_dscr_err_int_st1().bit()),
-            )
+            .field("frhost_bit0_int_st1", &self.frhost_bit0_int_st1())
+            .field("frhost_bit1_int_st1", &self.frhost_bit1_int_st1())
+            .field("frhost_bit2_int_st1", &self.frhost_bit2_int_st1())
+            .field("frhost_bit3_int_st1", &self.frhost_bit3_int_st1())
+            .field("frhost_bit4_int_st1", &self.frhost_bit4_int_st1())
+            .field("frhost_bit5_int_st1", &self.frhost_bit5_int_st1())
+            .field("frhost_bit6_int_st1", &self.frhost_bit6_int_st1())
+            .field("frhost_bit7_int_st1", &self.frhost_bit7_int_st1())
+            .field("slc0_rx_start_int_st1", &self.slc0_rx_start_int_st1())
+            .field("slc0_tx_start_int_st1", &self.slc0_tx_start_int_st1())
+            .field("slc0_rx_udf_int_st1", &self.slc0_rx_udf_int_st1())
+            .field("slc0_tx_ovf_int_st1", &self.slc0_tx_ovf_int_st1())
+            .field("slc0_token0_1to0_int_st1", &self.slc0_token0_1to0_int_st1())
+            .field("slc0_token1_1to0_int_st1", &self.slc0_token1_1to0_int_st1())
+            .field("slc0_tx_done_int_st1", &self.slc0_tx_done_int_st1())
+            .field("slc0_tx_suc_eof_int_st1", &self.slc0_tx_suc_eof_int_st1())
+            .field("slc0_rx_done_int_st1", &self.slc0_rx_done_int_st1())
+            .field("slc0_rx_eof_int_st1", &self.slc0_rx_eof_int_st1())
+            .field("slc0_tohost_int_st1", &self.slc0_tohost_int_st1())
+            .field("slc0_tx_dscr_err_int_st1", &self.slc0_tx_dscr_err_int_st1())
+            .field("slc0_rx_dscr_err_int_st1", &self.slc0_rx_dscr_err_int_st1())
             .field(
                 "slc0_tx_dscr_empty_int_st1",
-                &format_args!("{}", self.slc0_tx_dscr_empty_int_st1().bit()),
-            )
-            .field(
-                "slc0_host_rd_ack_int_st1",
-                &format_args!("{}", self.slc0_host_rd_ack_int_st1().bit()),
+                &self.slc0_tx_dscr_empty_int_st1(),
             )
+            .field("slc0_host_rd_ack_int_st1", &self.slc0_host_rd_ack_int_st1())
             .field(
                 "slc0_wr_retry_done_int_st1",
-                &format_args!("{}", self.slc0_wr_retry_done_int_st1().bit()),
-            )
-            .field(
-                "slc0_tx_err_eof_int_st1",
-                &format_args!("{}", self.slc0_tx_err_eof_int_st1().bit()),
-            )
-            .field(
-                "cmd_dtc_int_st1",
-                &format_args!("{}", self.cmd_dtc_int_st1().bit()),
+                &self.slc0_wr_retry_done_int_st1(),
             )
+            .field("slc0_tx_err_eof_int_st1", &self.slc0_tx_err_eof_int_st1())
+            .field("cmd_dtc_int_st1", &self.cmd_dtc_int_st1())
             .field(
                 "slc0_rx_quick_eof_int_st1",
-                &format_args!("{}", self.slc0_rx_quick_eof_int_st1().bit()),
+                &self.slc0_rx_quick_eof_int_st1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0INT_ST1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_0int_st1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _0INT_ST1_SPEC;
 impl crate::RegisterSpec for _0INT_ST1_SPEC {
diff --git a/esp32/src/slc/_0rx_link.rs b/esp32/src/slc/_0rx_link.rs
index abf627cfd3..536603649e 100644
--- a/esp32/src/slc/_0rx_link.rs
+++ b/esp32/src/slc/_0rx_link.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0RX_LINK")
-            .field(
-                "slc0_rxlink_addr",
-                &format_args!("{}", self.slc0_rxlink_addr().bits()),
-            )
-            .field(
-                "slc0_rxlink_stop",
-                &format_args!("{}", self.slc0_rxlink_stop().bit()),
-            )
-            .field(
-                "slc0_rxlink_start",
-                &format_args!("{}", self.slc0_rxlink_start().bit()),
-            )
-            .field(
-                "slc0_rxlink_restart",
-                &format_args!("{}", self.slc0_rxlink_restart().bit()),
-            )
-            .field(
-                "slc0_rxlink_park",
-                &format_args!("{}", self.slc0_rxlink_park().bit()),
-            )
+            .field("slc0_rxlink_addr", &self.slc0_rxlink_addr())
+            .field("slc0_rxlink_stop", &self.slc0_rxlink_stop())
+            .field("slc0_rxlink_start", &self.slc0_rxlink_start())
+            .field("slc0_rxlink_restart", &self.slc0_rxlink_restart())
+            .field("slc0_rxlink_park", &self.slc0_rxlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0RX_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
diff --git a/esp32/src/slc/_0rxfifo_push.rs b/esp32/src/slc/_0rxfifo_push.rs
index 692bf3e65d..bf90b7829f 100644
--- a/esp32/src/slc/_0rxfifo_push.rs
+++ b/esp32/src/slc/_0rxfifo_push.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0RXFIFO_PUSH")
-            .field(
-                "slc0_rxfifo_wdata",
-                &format_args!("{}", self.slc0_rxfifo_wdata().bits()),
-            )
-            .field(
-                "slc0_rxfifo_push",
-                &format_args!("{}", self.slc0_rxfifo_push().bit()),
-            )
+            .field("slc0_rxfifo_wdata", &self.slc0_rxfifo_wdata())
+            .field("slc0_rxfifo_push", &self.slc0_rxfifo_push())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0RXFIFO_PUSH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
diff --git a/esp32/src/slc/_0token0.rs b/esp32/src/slc/_0token0.rs
index 6285b36000..3a4331f976 100644
--- a/esp32/src/slc/_0token0.rs
+++ b/esp32/src/slc/_0token0.rs
@@ -23,19 +23,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0TOKEN0")
-            .field(
-                "slc0_token0",
-                &format_args!("{}", self.slc0_token0().bits()),
-            )
+            .field("slc0_token0", &self.slc0_token0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0TOKEN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
diff --git a/esp32/src/slc/_0token1.rs b/esp32/src/slc/_0token1.rs
index 6389580aab..2ec21dd2f2 100644
--- a/esp32/src/slc/_0token1.rs
+++ b/esp32/src/slc/_0token1.rs
@@ -23,19 +23,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0TOKEN1")
-            .field(
-                "slc0_token1",
-                &format_args!("{}", self.slc0_token1().bits()),
-            )
+            .field("slc0_token1", &self.slc0_token1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0TOKEN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
diff --git a/esp32/src/slc/_0tx_link.rs b/esp32/src/slc/_0tx_link.rs
index 51175e1ecb..67d9a8c222 100644
--- a/esp32/src/slc/_0tx_link.rs
+++ b/esp32/src/slc/_0tx_link.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0TX_LINK")
-            .field(
-                "slc0_txlink_addr",
-                &format_args!("{}", self.slc0_txlink_addr().bits()),
-            )
-            .field(
-                "slc0_txlink_stop",
-                &format_args!("{}", self.slc0_txlink_stop().bit()),
-            )
-            .field(
-                "slc0_txlink_start",
-                &format_args!("{}", self.slc0_txlink_start().bit()),
-            )
-            .field(
-                "slc0_txlink_restart",
-                &format_args!("{}", self.slc0_txlink_restart().bit()),
-            )
-            .field(
-                "slc0_txlink_park",
-                &format_args!("{}", self.slc0_txlink_park().bit()),
-            )
+            .field("slc0_txlink_addr", &self.slc0_txlink_addr())
+            .field("slc0_txlink_stop", &self.slc0_txlink_stop())
+            .field("slc0_txlink_start", &self.slc0_txlink_start())
+            .field("slc0_txlink_restart", &self.slc0_txlink_restart())
+            .field("slc0_txlink_park", &self.slc0_txlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0TX_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
diff --git a/esp32/src/slc/_0txfifo_pop.rs b/esp32/src/slc/_0txfifo_pop.rs
index 5da6c1f018..7ac1716b5f 100644
--- a/esp32/src/slc/_0txfifo_pop.rs
+++ b/esp32/src/slc/_0txfifo_pop.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_0TXFIFO_POP")
-            .field(
-                "slc0_txfifo_rdata",
-                &format_args!("{}", self.slc0_txfifo_rdata().bits()),
-            )
-            .field(
-                "slc0_txfifo_pop",
-                &format_args!("{}", self.slc0_txfifo_pop().bit()),
-            )
+            .field("slc0_txfifo_rdata", &self.slc0_txfifo_rdata())
+            .field("slc0_txfifo_pop", &self.slc0_txfifo_pop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_0TXFIFO_POP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16"]
     #[inline(always)]
diff --git a/esp32/src/slc/_1_rxlink_dscr.rs b/esp32/src/slc/_1_rxlink_dscr.rs
index ec052f5ddb..91bd10f055 100644
--- a/esp32/src/slc/_1_rxlink_dscr.rs
+++ b/esp32/src/slc/_1_rxlink_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1_RXLINK_DSCR")
-            .field(
-                "slc1_rxlink_dscr",
-                &format_args!("{}", self.slc1_rxlink_dscr().bits()),
-            )
+            .field("slc1_rxlink_dscr", &self.slc1_rxlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1_RXLINK_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_1_rxlink_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _1_RXLINK_DSCR_SPEC;
 impl crate::RegisterSpec for _1_RXLINK_DSCR_SPEC {
diff --git a/esp32/src/slc/_1_rxlink_dscr_bf0.rs b/esp32/src/slc/_1_rxlink_dscr_bf0.rs
index abde4a613b..1b97b5577b 100644
--- a/esp32/src/slc/_1_rxlink_dscr_bf0.rs
+++ b/esp32/src/slc/_1_rxlink_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1_RXLINK_DSCR_BF0")
-            .field(
-                "slc1_rxlink_dscr_bf0",
-                &format_args!("{}", self.slc1_rxlink_dscr_bf0().bits()),
-            )
+            .field("slc1_rxlink_dscr_bf0", &self.slc1_rxlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1_RXLINK_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_1_rxlink_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _1_RXLINK_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for _1_RXLINK_DSCR_BF0_SPEC {
diff --git a/esp32/src/slc/_1_rxlink_dscr_bf1.rs b/esp32/src/slc/_1_rxlink_dscr_bf1.rs
index a8213d21be..55994250c6 100644
--- a/esp32/src/slc/_1_rxlink_dscr_bf1.rs
+++ b/esp32/src/slc/_1_rxlink_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1_RXLINK_DSCR_BF1")
-            .field(
-                "slc1_rxlink_dscr_bf1",
-                &format_args!("{}", self.slc1_rxlink_dscr_bf1().bits()),
-            )
+            .field("slc1_rxlink_dscr_bf1", &self.slc1_rxlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1_RXLINK_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_1_rxlink_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _1_RXLINK_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for _1_RXLINK_DSCR_BF1_SPEC {
diff --git a/esp32/src/slc/_1_state0.rs b/esp32/src/slc/_1_state0.rs
index 60c4d0b9da..c2aecbe529 100644
--- a/esp32/src/slc/_1_state0.rs
+++ b/esp32/src/slc/_1_state0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1_STATE0")
-            .field(
-                "slc1_state0",
-                &format_args!("{}", self.slc1_state0().bits()),
-            )
+            .field("slc1_state0", &self.slc1_state0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1_STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_1_state0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _1_STATE0_SPEC;
 impl crate::RegisterSpec for _1_STATE0_SPEC {
diff --git a/esp32/src/slc/_1_state1.rs b/esp32/src/slc/_1_state1.rs
index ff5aa36cd4..467d1a65e1 100644
--- a/esp32/src/slc/_1_state1.rs
+++ b/esp32/src/slc/_1_state1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1_STATE1")
-            .field(
-                "slc1_state1",
-                &format_args!("{}", self.slc1_state1().bits()),
-            )
+            .field("slc1_state1", &self.slc1_state1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1_STATE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_1_state1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _1_STATE1_SPEC;
 impl crate::RegisterSpec for _1_STATE1_SPEC {
diff --git a/esp32/src/slc/_1_to_eof_bfr_des_addr.rs b/esp32/src/slc/_1_to_eof_bfr_des_addr.rs
index 9b768a9a67..961f4bdbcf 100644
--- a/esp32/src/slc/_1_to_eof_bfr_des_addr.rs
+++ b/esp32/src/slc/_1_to_eof_bfr_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1_TO_EOF_BFR_DES_ADDR")
-            .field(
-                "slc1_to_eof_bfr_des_addr",
-                &format_args!("{}", self.slc1_to_eof_bfr_des_addr().bits()),
-            )
+            .field("slc1_to_eof_bfr_des_addr", &self.slc1_to_eof_bfr_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1_TO_EOF_BFR_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_1_to_eof_bfr_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _1_TO_EOF_BFR_DES_ADDR_SPEC;
 impl crate::RegisterSpec for _1_TO_EOF_BFR_DES_ADDR_SPEC {
diff --git a/esp32/src/slc/_1_to_eof_des_addr.rs b/esp32/src/slc/_1_to_eof_des_addr.rs
index 37b826f6b7..81a73d36f8 100644
--- a/esp32/src/slc/_1_to_eof_des_addr.rs
+++ b/esp32/src/slc/_1_to_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1_TO_EOF_DES_ADDR")
-            .field(
-                "slc1_to_eof_des_addr",
-                &format_args!("{}", self.slc1_to_eof_des_addr().bits()),
-            )
+            .field("slc1_to_eof_des_addr", &self.slc1_to_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1_TO_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_1_to_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _1_TO_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for _1_TO_EOF_DES_ADDR_SPEC {
diff --git a/esp32/src/slc/_1_tx_eof_des_addr.rs b/esp32/src/slc/_1_tx_eof_des_addr.rs
index e555b3b736..ca7ec7f97a 100644
--- a/esp32/src/slc/_1_tx_eof_des_addr.rs
+++ b/esp32/src/slc/_1_tx_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1_TX_EOF_DES_ADDR")
-            .field(
-                "slc1_tx_suc_eof_des_addr",
-                &format_args!("{}", self.slc1_tx_suc_eof_des_addr().bits()),
-            )
+            .field("slc1_tx_suc_eof_des_addr", &self.slc1_tx_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1_TX_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_1_tx_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _1_TX_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for _1_TX_EOF_DES_ADDR_SPEC {
diff --git a/esp32/src/slc/_1_tx_erreof_des_addr.rs b/esp32/src/slc/_1_tx_erreof_des_addr.rs
index eaeb7a0edd..c39afbb780 100644
--- a/esp32/src/slc/_1_tx_erreof_des_addr.rs
+++ b/esp32/src/slc/_1_tx_erreof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1_TX_ERREOF_DES_ADDR")
-            .field(
-                "slc1_tx_err_eof_des_addr",
-                &format_args!("{}", self.slc1_tx_err_eof_des_addr().bits()),
-            )
+            .field("slc1_tx_err_eof_des_addr", &self.slc1_tx_err_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1_TX_ERREOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_1_tx_erreof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _1_TX_ERREOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for _1_TX_ERREOF_DES_ADDR_SPEC {
diff --git a/esp32/src/slc/_1_txlink_dscr.rs b/esp32/src/slc/_1_txlink_dscr.rs
index 291219a36a..3f4df0e761 100644
--- a/esp32/src/slc/_1_txlink_dscr.rs
+++ b/esp32/src/slc/_1_txlink_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1_TXLINK_DSCR")
-            .field(
-                "slc1_txlink_dscr",
-                &format_args!("{}", self.slc1_txlink_dscr().bits()),
-            )
+            .field("slc1_txlink_dscr", &self.slc1_txlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1_TXLINK_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_1_txlink_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _1_TXLINK_DSCR_SPEC;
 impl crate::RegisterSpec for _1_TXLINK_DSCR_SPEC {
diff --git a/esp32/src/slc/_1_txlink_dscr_bf0.rs b/esp32/src/slc/_1_txlink_dscr_bf0.rs
index fc2dd74b13..ba72125468 100644
--- a/esp32/src/slc/_1_txlink_dscr_bf0.rs
+++ b/esp32/src/slc/_1_txlink_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1_TXLINK_DSCR_BF0")
-            .field(
-                "slc1_txlink_dscr_bf0",
-                &format_args!("{}", self.slc1_txlink_dscr_bf0().bits()),
-            )
+            .field("slc1_txlink_dscr_bf0", &self.slc1_txlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1_TXLINK_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_1_txlink_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _1_TXLINK_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for _1_TXLINK_DSCR_BF0_SPEC {
diff --git a/esp32/src/slc/_1_txlink_dscr_bf1.rs b/esp32/src/slc/_1_txlink_dscr_bf1.rs
index ae6a6eef2d..03b6d5bc20 100644
--- a/esp32/src/slc/_1_txlink_dscr_bf1.rs
+++ b/esp32/src/slc/_1_txlink_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1_TXLINK_DSCR_BF1")
-            .field(
-                "slc1_txlink_dscr_bf1",
-                &format_args!("{}", self.slc1_txlink_dscr_bf1().bits()),
-            )
+            .field("slc1_txlink_dscr_bf1", &self.slc1_txlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1_TXLINK_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_1_txlink_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _1_TXLINK_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for _1_TXLINK_DSCR_BF1_SPEC {
diff --git a/esp32/src/slc/_1int_ena.rs b/esp32/src/slc/_1int_ena.rs
index aecd1f71f0..ba95d57987 100644
--- a/esp32/src/slc/_1int_ena.rs
+++ b/esp32/src/slc/_1int_ena.rs
@@ -233,115 +233,40 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1INT_ENA")
-            .field(
-                "frhost_bit8_int_ena",
-                &format_args!("{}", self.frhost_bit8_int_ena().bit()),
-            )
-            .field(
-                "frhost_bit9_int_ena",
-                &format_args!("{}", self.frhost_bit9_int_ena().bit()),
-            )
-            .field(
-                "frhost_bit10_int_ena",
-                &format_args!("{}", self.frhost_bit10_int_ena().bit()),
-            )
-            .field(
-                "frhost_bit11_int_ena",
-                &format_args!("{}", self.frhost_bit11_int_ena().bit()),
-            )
-            .field(
-                "frhost_bit12_int_ena",
-                &format_args!("{}", self.frhost_bit12_int_ena().bit()),
-            )
-            .field(
-                "frhost_bit13_int_ena",
-                &format_args!("{}", self.frhost_bit13_int_ena().bit()),
-            )
-            .field(
-                "frhost_bit14_int_ena",
-                &format_args!("{}", self.frhost_bit14_int_ena().bit()),
-            )
-            .field(
-                "frhost_bit15_int_ena",
-                &format_args!("{}", self.frhost_bit15_int_ena().bit()),
-            )
-            .field(
-                "slc1_rx_start_int_ena",
-                &format_args!("{}", self.slc1_rx_start_int_ena().bit()),
-            )
-            .field(
-                "slc1_tx_start_int_ena",
-                &format_args!("{}", self.slc1_tx_start_int_ena().bit()),
-            )
-            .field(
-                "slc1_rx_udf_int_ena",
-                &format_args!("{}", self.slc1_rx_udf_int_ena().bit()),
-            )
-            .field(
-                "slc1_tx_ovf_int_ena",
-                &format_args!("{}", self.slc1_tx_ovf_int_ena().bit()),
-            )
-            .field(
-                "slc1_token0_1to0_int_ena",
-                &format_args!("{}", self.slc1_token0_1to0_int_ena().bit()),
-            )
-            .field(
-                "slc1_token1_1to0_int_ena",
-                &format_args!("{}", self.slc1_token1_1to0_int_ena().bit()),
-            )
-            .field(
-                "slc1_tx_done_int_ena",
-                &format_args!("{}", self.slc1_tx_done_int_ena().bit()),
-            )
-            .field(
-                "slc1_tx_suc_eof_int_ena",
-                &format_args!("{}", self.slc1_tx_suc_eof_int_ena().bit()),
-            )
-            .field(
-                "slc1_rx_done_int_ena",
-                &format_args!("{}", self.slc1_rx_done_int_ena().bit()),
-            )
-            .field(
-                "slc1_rx_eof_int_ena",
-                &format_args!("{}", self.slc1_rx_eof_int_ena().bit()),
-            )
-            .field(
-                "slc1_tohost_int_ena",
-                &format_args!("{}", self.slc1_tohost_int_ena().bit()),
-            )
-            .field(
-                "slc1_tx_dscr_err_int_ena",
-                &format_args!("{}", self.slc1_tx_dscr_err_int_ena().bit()),
-            )
-            .field(
-                "slc1_rx_dscr_err_int_ena",
-                &format_args!("{}", self.slc1_rx_dscr_err_int_ena().bit()),
-            )
+            .field("frhost_bit8_int_ena", &self.frhost_bit8_int_ena())
+            .field("frhost_bit9_int_ena", &self.frhost_bit9_int_ena())
+            .field("frhost_bit10_int_ena", &self.frhost_bit10_int_ena())
+            .field("frhost_bit11_int_ena", &self.frhost_bit11_int_ena())
+            .field("frhost_bit12_int_ena", &self.frhost_bit12_int_ena())
+            .field("frhost_bit13_int_ena", &self.frhost_bit13_int_ena())
+            .field("frhost_bit14_int_ena", &self.frhost_bit14_int_ena())
+            .field("frhost_bit15_int_ena", &self.frhost_bit15_int_ena())
+            .field("slc1_rx_start_int_ena", &self.slc1_rx_start_int_ena())
+            .field("slc1_tx_start_int_ena", &self.slc1_tx_start_int_ena())
+            .field("slc1_rx_udf_int_ena", &self.slc1_rx_udf_int_ena())
+            .field("slc1_tx_ovf_int_ena", &self.slc1_tx_ovf_int_ena())
+            .field("slc1_token0_1to0_int_ena", &self.slc1_token0_1to0_int_ena())
+            .field("slc1_token1_1to0_int_ena", &self.slc1_token1_1to0_int_ena())
+            .field("slc1_tx_done_int_ena", &self.slc1_tx_done_int_ena())
+            .field("slc1_tx_suc_eof_int_ena", &self.slc1_tx_suc_eof_int_ena())
+            .field("slc1_rx_done_int_ena", &self.slc1_rx_done_int_ena())
+            .field("slc1_rx_eof_int_ena", &self.slc1_rx_eof_int_ena())
+            .field("slc1_tohost_int_ena", &self.slc1_tohost_int_ena())
+            .field("slc1_tx_dscr_err_int_ena", &self.slc1_tx_dscr_err_int_ena())
+            .field("slc1_rx_dscr_err_int_ena", &self.slc1_rx_dscr_err_int_ena())
             .field(
                 "slc1_tx_dscr_empty_int_ena",
-                &format_args!("{}", self.slc1_tx_dscr_empty_int_ena().bit()),
-            )
-            .field(
-                "slc1_host_rd_ack_int_ena",
-                &format_args!("{}", self.slc1_host_rd_ack_int_ena().bit()),
+                &self.slc1_tx_dscr_empty_int_ena(),
             )
+            .field("slc1_host_rd_ack_int_ena", &self.slc1_host_rd_ack_int_ena())
             .field(
                 "slc1_wr_retry_done_int_ena",
-                &format_args!("{}", self.slc1_wr_retry_done_int_ena().bit()),
-            )
-            .field(
-                "slc1_tx_err_eof_int_ena",
-                &format_args!("{}", self.slc1_tx_err_eof_int_ena().bit()),
+                &self.slc1_wr_retry_done_int_ena(),
             )
+            .field("slc1_tx_err_eof_int_ena", &self.slc1_tx_err_eof_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slc/_1int_ena1.rs b/esp32/src/slc/_1int_ena1.rs
index 54d8acd309..7d7727aae3 100644
--- a/esp32/src/slc/_1int_ena1.rs
+++ b/esp32/src/slc/_1int_ena1.rs
@@ -233,115 +233,55 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1INT_ENA1")
-            .field(
-                "frhost_bit8_int_ena1",
-                &format_args!("{}", self.frhost_bit8_int_ena1().bit()),
-            )
-            .field(
-                "frhost_bit9_int_ena1",
-                &format_args!("{}", self.frhost_bit9_int_ena1().bit()),
-            )
-            .field(
-                "frhost_bit10_int_ena1",
-                &format_args!("{}", self.frhost_bit10_int_ena1().bit()),
-            )
-            .field(
-                "frhost_bit11_int_ena1",
-                &format_args!("{}", self.frhost_bit11_int_ena1().bit()),
-            )
-            .field(
-                "frhost_bit12_int_ena1",
-                &format_args!("{}", self.frhost_bit12_int_ena1().bit()),
-            )
-            .field(
-                "frhost_bit13_int_ena1",
-                &format_args!("{}", self.frhost_bit13_int_ena1().bit()),
-            )
-            .field(
-                "frhost_bit14_int_ena1",
-                &format_args!("{}", self.frhost_bit14_int_ena1().bit()),
-            )
-            .field(
-                "frhost_bit15_int_ena1",
-                &format_args!("{}", self.frhost_bit15_int_ena1().bit()),
-            )
-            .field(
-                "slc1_rx_start_int_ena1",
-                &format_args!("{}", self.slc1_rx_start_int_ena1().bit()),
-            )
-            .field(
-                "slc1_tx_start_int_ena1",
-                &format_args!("{}", self.slc1_tx_start_int_ena1().bit()),
-            )
-            .field(
-                "slc1_rx_udf_int_ena1",
-                &format_args!("{}", self.slc1_rx_udf_int_ena1().bit()),
-            )
-            .field(
-                "slc1_tx_ovf_int_ena1",
-                &format_args!("{}", self.slc1_tx_ovf_int_ena1().bit()),
-            )
+            .field("frhost_bit8_int_ena1", &self.frhost_bit8_int_ena1())
+            .field("frhost_bit9_int_ena1", &self.frhost_bit9_int_ena1())
+            .field("frhost_bit10_int_ena1", &self.frhost_bit10_int_ena1())
+            .field("frhost_bit11_int_ena1", &self.frhost_bit11_int_ena1())
+            .field("frhost_bit12_int_ena1", &self.frhost_bit12_int_ena1())
+            .field("frhost_bit13_int_ena1", &self.frhost_bit13_int_ena1())
+            .field("frhost_bit14_int_ena1", &self.frhost_bit14_int_ena1())
+            .field("frhost_bit15_int_ena1", &self.frhost_bit15_int_ena1())
+            .field("slc1_rx_start_int_ena1", &self.slc1_rx_start_int_ena1())
+            .field("slc1_tx_start_int_ena1", &self.slc1_tx_start_int_ena1())
+            .field("slc1_rx_udf_int_ena1", &self.slc1_rx_udf_int_ena1())
+            .field("slc1_tx_ovf_int_ena1", &self.slc1_tx_ovf_int_ena1())
             .field(
                 "slc1_token0_1to0_int_ena1",
-                &format_args!("{}", self.slc1_token0_1to0_int_ena1().bit()),
+                &self.slc1_token0_1to0_int_ena1(),
             )
             .field(
                 "slc1_token1_1to0_int_ena1",
-                &format_args!("{}", self.slc1_token1_1to0_int_ena1().bit()),
-            )
-            .field(
-                "slc1_tx_done_int_ena1",
-                &format_args!("{}", self.slc1_tx_done_int_ena1().bit()),
-            )
-            .field(
-                "slc1_tx_suc_eof_int_ena1",
-                &format_args!("{}", self.slc1_tx_suc_eof_int_ena1().bit()),
-            )
-            .field(
-                "slc1_rx_done_int_ena1",
-                &format_args!("{}", self.slc1_rx_done_int_ena1().bit()),
-            )
-            .field(
-                "slc1_rx_eof_int_ena1",
-                &format_args!("{}", self.slc1_rx_eof_int_ena1().bit()),
-            )
-            .field(
-                "slc1_tohost_int_ena1",
-                &format_args!("{}", self.slc1_tohost_int_ena1().bit()),
+                &self.slc1_token1_1to0_int_ena1(),
             )
+            .field("slc1_tx_done_int_ena1", &self.slc1_tx_done_int_ena1())
+            .field("slc1_tx_suc_eof_int_ena1", &self.slc1_tx_suc_eof_int_ena1())
+            .field("slc1_rx_done_int_ena1", &self.slc1_rx_done_int_ena1())
+            .field("slc1_rx_eof_int_ena1", &self.slc1_rx_eof_int_ena1())
+            .field("slc1_tohost_int_ena1", &self.slc1_tohost_int_ena1())
             .field(
                 "slc1_tx_dscr_err_int_ena1",
-                &format_args!("{}", self.slc1_tx_dscr_err_int_ena1().bit()),
+                &self.slc1_tx_dscr_err_int_ena1(),
             )
             .field(
                 "slc1_rx_dscr_err_int_ena1",
-                &format_args!("{}", self.slc1_rx_dscr_err_int_ena1().bit()),
+                &self.slc1_rx_dscr_err_int_ena1(),
             )
             .field(
                 "slc1_tx_dscr_empty_int_ena1",
-                &format_args!("{}", self.slc1_tx_dscr_empty_int_ena1().bit()),
+                &self.slc1_tx_dscr_empty_int_ena1(),
             )
             .field(
                 "slc1_host_rd_ack_int_ena1",
-                &format_args!("{}", self.slc1_host_rd_ack_int_ena1().bit()),
+                &self.slc1_host_rd_ack_int_ena1(),
             )
             .field(
                 "slc1_wr_retry_done_int_ena1",
-                &format_args!("{}", self.slc1_wr_retry_done_int_ena1().bit()),
-            )
-            .field(
-                "slc1_tx_err_eof_int_ena1",
-                &format_args!("{}", self.slc1_tx_err_eof_int_ena1().bit()),
+                &self.slc1_wr_retry_done_int_ena1(),
             )
+            .field("slc1_tx_err_eof_int_ena1", &self.slc1_tx_err_eof_int_ena1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1INT_ENA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slc/_1int_raw.rs b/esp32/src/slc/_1int_raw.rs
index c787080860..cc306522f2 100644
--- a/esp32/src/slc/_1int_raw.rs
+++ b/esp32/src/slc/_1int_raw.rs
@@ -181,115 +181,40 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1INT_RAW")
-            .field(
-                "frhost_bit8_int_raw",
-                &format_args!("{}", self.frhost_bit8_int_raw().bit()),
-            )
-            .field(
-                "frhost_bit9_int_raw",
-                &format_args!("{}", self.frhost_bit9_int_raw().bit()),
-            )
-            .field(
-                "frhost_bit10_int_raw",
-                &format_args!("{}", self.frhost_bit10_int_raw().bit()),
-            )
-            .field(
-                "frhost_bit11_int_raw",
-                &format_args!("{}", self.frhost_bit11_int_raw().bit()),
-            )
-            .field(
-                "frhost_bit12_int_raw",
-                &format_args!("{}", self.frhost_bit12_int_raw().bit()),
-            )
-            .field(
-                "frhost_bit13_int_raw",
-                &format_args!("{}", self.frhost_bit13_int_raw().bit()),
-            )
-            .field(
-                "frhost_bit14_int_raw",
-                &format_args!("{}", self.frhost_bit14_int_raw().bit()),
-            )
-            .field(
-                "frhost_bit15_int_raw",
-                &format_args!("{}", self.frhost_bit15_int_raw().bit()),
-            )
-            .field(
-                "slc1_rx_start_int_raw",
-                &format_args!("{}", self.slc1_rx_start_int_raw().bit()),
-            )
-            .field(
-                "slc1_tx_start_int_raw",
-                &format_args!("{}", self.slc1_tx_start_int_raw().bit()),
-            )
-            .field(
-                "slc1_rx_udf_int_raw",
-                &format_args!("{}", self.slc1_rx_udf_int_raw().bit()),
-            )
-            .field(
-                "slc1_tx_ovf_int_raw",
-                &format_args!("{}", self.slc1_tx_ovf_int_raw().bit()),
-            )
-            .field(
-                "slc1_token0_1to0_int_raw",
-                &format_args!("{}", self.slc1_token0_1to0_int_raw().bit()),
-            )
-            .field(
-                "slc1_token1_1to0_int_raw",
-                &format_args!("{}", self.slc1_token1_1to0_int_raw().bit()),
-            )
-            .field(
-                "slc1_tx_done_int_raw",
-                &format_args!("{}", self.slc1_tx_done_int_raw().bit()),
-            )
-            .field(
-                "slc1_tx_suc_eof_int_raw",
-                &format_args!("{}", self.slc1_tx_suc_eof_int_raw().bit()),
-            )
-            .field(
-                "slc1_rx_done_int_raw",
-                &format_args!("{}", self.slc1_rx_done_int_raw().bit()),
-            )
-            .field(
-                "slc1_rx_eof_int_raw",
-                &format_args!("{}", self.slc1_rx_eof_int_raw().bit()),
-            )
-            .field(
-                "slc1_tohost_int_raw",
-                &format_args!("{}", self.slc1_tohost_int_raw().bit()),
-            )
-            .field(
-                "slc1_tx_dscr_err_int_raw",
-                &format_args!("{}", self.slc1_tx_dscr_err_int_raw().bit()),
-            )
-            .field(
-                "slc1_rx_dscr_err_int_raw",
-                &format_args!("{}", self.slc1_rx_dscr_err_int_raw().bit()),
-            )
+            .field("frhost_bit8_int_raw", &self.frhost_bit8_int_raw())
+            .field("frhost_bit9_int_raw", &self.frhost_bit9_int_raw())
+            .field("frhost_bit10_int_raw", &self.frhost_bit10_int_raw())
+            .field("frhost_bit11_int_raw", &self.frhost_bit11_int_raw())
+            .field("frhost_bit12_int_raw", &self.frhost_bit12_int_raw())
+            .field("frhost_bit13_int_raw", &self.frhost_bit13_int_raw())
+            .field("frhost_bit14_int_raw", &self.frhost_bit14_int_raw())
+            .field("frhost_bit15_int_raw", &self.frhost_bit15_int_raw())
+            .field("slc1_rx_start_int_raw", &self.slc1_rx_start_int_raw())
+            .field("slc1_tx_start_int_raw", &self.slc1_tx_start_int_raw())
+            .field("slc1_rx_udf_int_raw", &self.slc1_rx_udf_int_raw())
+            .field("slc1_tx_ovf_int_raw", &self.slc1_tx_ovf_int_raw())
+            .field("slc1_token0_1to0_int_raw", &self.slc1_token0_1to0_int_raw())
+            .field("slc1_token1_1to0_int_raw", &self.slc1_token1_1to0_int_raw())
+            .field("slc1_tx_done_int_raw", &self.slc1_tx_done_int_raw())
+            .field("slc1_tx_suc_eof_int_raw", &self.slc1_tx_suc_eof_int_raw())
+            .field("slc1_rx_done_int_raw", &self.slc1_rx_done_int_raw())
+            .field("slc1_rx_eof_int_raw", &self.slc1_rx_eof_int_raw())
+            .field("slc1_tohost_int_raw", &self.slc1_tohost_int_raw())
+            .field("slc1_tx_dscr_err_int_raw", &self.slc1_tx_dscr_err_int_raw())
+            .field("slc1_rx_dscr_err_int_raw", &self.slc1_rx_dscr_err_int_raw())
             .field(
                 "slc1_tx_dscr_empty_int_raw",
-                &format_args!("{}", self.slc1_tx_dscr_empty_int_raw().bit()),
-            )
-            .field(
-                "slc1_host_rd_ack_int_raw",
-                &format_args!("{}", self.slc1_host_rd_ack_int_raw().bit()),
+                &self.slc1_tx_dscr_empty_int_raw(),
             )
+            .field("slc1_host_rd_ack_int_raw", &self.slc1_host_rd_ack_int_raw())
             .field(
                 "slc1_wr_retry_done_int_raw",
-                &format_args!("{}", self.slc1_wr_retry_done_int_raw().bit()),
-            )
-            .field(
-                "slc1_tx_err_eof_int_raw",
-                &format_args!("{}", self.slc1_tx_err_eof_int_raw().bit()),
+                &self.slc1_wr_retry_done_int_raw(),
             )
+            .field("slc1_tx_err_eof_int_raw", &self.slc1_tx_err_eof_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_1int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _1INT_RAW_SPEC;
 impl crate::RegisterSpec for _1INT_RAW_SPEC {
diff --git a/esp32/src/slc/_1int_st.rs b/esp32/src/slc/_1int_st.rs
index d42fdf7653..ba02f0bba0 100644
--- a/esp32/src/slc/_1int_st.rs
+++ b/esp32/src/slc/_1int_st.rs
@@ -181,115 +181,40 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1INT_ST")
-            .field(
-                "frhost_bit8_int_st",
-                &format_args!("{}", self.frhost_bit8_int_st().bit()),
-            )
-            .field(
-                "frhost_bit9_int_st",
-                &format_args!("{}", self.frhost_bit9_int_st().bit()),
-            )
-            .field(
-                "frhost_bit10_int_st",
-                &format_args!("{}", self.frhost_bit10_int_st().bit()),
-            )
-            .field(
-                "frhost_bit11_int_st",
-                &format_args!("{}", self.frhost_bit11_int_st().bit()),
-            )
-            .field(
-                "frhost_bit12_int_st",
-                &format_args!("{}", self.frhost_bit12_int_st().bit()),
-            )
-            .field(
-                "frhost_bit13_int_st",
-                &format_args!("{}", self.frhost_bit13_int_st().bit()),
-            )
-            .field(
-                "frhost_bit14_int_st",
-                &format_args!("{}", self.frhost_bit14_int_st().bit()),
-            )
-            .field(
-                "frhost_bit15_int_st",
-                &format_args!("{}", self.frhost_bit15_int_st().bit()),
-            )
-            .field(
-                "slc1_rx_start_int_st",
-                &format_args!("{}", self.slc1_rx_start_int_st().bit()),
-            )
-            .field(
-                "slc1_tx_start_int_st",
-                &format_args!("{}", self.slc1_tx_start_int_st().bit()),
-            )
-            .field(
-                "slc1_rx_udf_int_st",
-                &format_args!("{}", self.slc1_rx_udf_int_st().bit()),
-            )
-            .field(
-                "slc1_tx_ovf_int_st",
-                &format_args!("{}", self.slc1_tx_ovf_int_st().bit()),
-            )
-            .field(
-                "slc1_token0_1to0_int_st",
-                &format_args!("{}", self.slc1_token0_1to0_int_st().bit()),
-            )
-            .field(
-                "slc1_token1_1to0_int_st",
-                &format_args!("{}", self.slc1_token1_1to0_int_st().bit()),
-            )
-            .field(
-                "slc1_tx_done_int_st",
-                &format_args!("{}", self.slc1_tx_done_int_st().bit()),
-            )
-            .field(
-                "slc1_tx_suc_eof_int_st",
-                &format_args!("{}", self.slc1_tx_suc_eof_int_st().bit()),
-            )
-            .field(
-                "slc1_rx_done_int_st",
-                &format_args!("{}", self.slc1_rx_done_int_st().bit()),
-            )
-            .field(
-                "slc1_rx_eof_int_st",
-                &format_args!("{}", self.slc1_rx_eof_int_st().bit()),
-            )
-            .field(
-                "slc1_tohost_int_st",
-                &format_args!("{}", self.slc1_tohost_int_st().bit()),
-            )
-            .field(
-                "slc1_tx_dscr_err_int_st",
-                &format_args!("{}", self.slc1_tx_dscr_err_int_st().bit()),
-            )
-            .field(
-                "slc1_rx_dscr_err_int_st",
-                &format_args!("{}", self.slc1_rx_dscr_err_int_st().bit()),
-            )
+            .field("frhost_bit8_int_st", &self.frhost_bit8_int_st())
+            .field("frhost_bit9_int_st", &self.frhost_bit9_int_st())
+            .field("frhost_bit10_int_st", &self.frhost_bit10_int_st())
+            .field("frhost_bit11_int_st", &self.frhost_bit11_int_st())
+            .field("frhost_bit12_int_st", &self.frhost_bit12_int_st())
+            .field("frhost_bit13_int_st", &self.frhost_bit13_int_st())
+            .field("frhost_bit14_int_st", &self.frhost_bit14_int_st())
+            .field("frhost_bit15_int_st", &self.frhost_bit15_int_st())
+            .field("slc1_rx_start_int_st", &self.slc1_rx_start_int_st())
+            .field("slc1_tx_start_int_st", &self.slc1_tx_start_int_st())
+            .field("slc1_rx_udf_int_st", &self.slc1_rx_udf_int_st())
+            .field("slc1_tx_ovf_int_st", &self.slc1_tx_ovf_int_st())
+            .field("slc1_token0_1to0_int_st", &self.slc1_token0_1to0_int_st())
+            .field("slc1_token1_1to0_int_st", &self.slc1_token1_1to0_int_st())
+            .field("slc1_tx_done_int_st", &self.slc1_tx_done_int_st())
+            .field("slc1_tx_suc_eof_int_st", &self.slc1_tx_suc_eof_int_st())
+            .field("slc1_rx_done_int_st", &self.slc1_rx_done_int_st())
+            .field("slc1_rx_eof_int_st", &self.slc1_rx_eof_int_st())
+            .field("slc1_tohost_int_st", &self.slc1_tohost_int_st())
+            .field("slc1_tx_dscr_err_int_st", &self.slc1_tx_dscr_err_int_st())
+            .field("slc1_rx_dscr_err_int_st", &self.slc1_rx_dscr_err_int_st())
             .field(
                 "slc1_tx_dscr_empty_int_st",
-                &format_args!("{}", self.slc1_tx_dscr_empty_int_st().bit()),
-            )
-            .field(
-                "slc1_host_rd_ack_int_st",
-                &format_args!("{}", self.slc1_host_rd_ack_int_st().bit()),
+                &self.slc1_tx_dscr_empty_int_st(),
             )
+            .field("slc1_host_rd_ack_int_st", &self.slc1_host_rd_ack_int_st())
             .field(
                 "slc1_wr_retry_done_int_st",
-                &format_args!("{}", self.slc1_wr_retry_done_int_st().bit()),
-            )
-            .field(
-                "slc1_tx_err_eof_int_st",
-                &format_args!("{}", self.slc1_tx_err_eof_int_st().bit()),
+                &self.slc1_wr_retry_done_int_st(),
             )
+            .field("slc1_tx_err_eof_int_st", &self.slc1_tx_err_eof_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_1int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _1INT_ST_SPEC;
 impl crate::RegisterSpec for _1INT_ST_SPEC {
diff --git a/esp32/src/slc/_1int_st1.rs b/esp32/src/slc/_1int_st1.rs
index 6515312002..daadbbf296 100644
--- a/esp32/src/slc/_1int_st1.rs
+++ b/esp32/src/slc/_1int_st1.rs
@@ -181,115 +181,40 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1INT_ST1")
-            .field(
-                "frhost_bit8_int_st1",
-                &format_args!("{}", self.frhost_bit8_int_st1().bit()),
-            )
-            .field(
-                "frhost_bit9_int_st1",
-                &format_args!("{}", self.frhost_bit9_int_st1().bit()),
-            )
-            .field(
-                "frhost_bit10_int_st1",
-                &format_args!("{}", self.frhost_bit10_int_st1().bit()),
-            )
-            .field(
-                "frhost_bit11_int_st1",
-                &format_args!("{}", self.frhost_bit11_int_st1().bit()),
-            )
-            .field(
-                "frhost_bit12_int_st1",
-                &format_args!("{}", self.frhost_bit12_int_st1().bit()),
-            )
-            .field(
-                "frhost_bit13_int_st1",
-                &format_args!("{}", self.frhost_bit13_int_st1().bit()),
-            )
-            .field(
-                "frhost_bit14_int_st1",
-                &format_args!("{}", self.frhost_bit14_int_st1().bit()),
-            )
-            .field(
-                "frhost_bit15_int_st1",
-                &format_args!("{}", self.frhost_bit15_int_st1().bit()),
-            )
-            .field(
-                "slc1_rx_start_int_st1",
-                &format_args!("{}", self.slc1_rx_start_int_st1().bit()),
-            )
-            .field(
-                "slc1_tx_start_int_st1",
-                &format_args!("{}", self.slc1_tx_start_int_st1().bit()),
-            )
-            .field(
-                "slc1_rx_udf_int_st1",
-                &format_args!("{}", self.slc1_rx_udf_int_st1().bit()),
-            )
-            .field(
-                "slc1_tx_ovf_int_st1",
-                &format_args!("{}", self.slc1_tx_ovf_int_st1().bit()),
-            )
-            .field(
-                "slc1_token0_1to0_int_st1",
-                &format_args!("{}", self.slc1_token0_1to0_int_st1().bit()),
-            )
-            .field(
-                "slc1_token1_1to0_int_st1",
-                &format_args!("{}", self.slc1_token1_1to0_int_st1().bit()),
-            )
-            .field(
-                "slc1_tx_done_int_st1",
-                &format_args!("{}", self.slc1_tx_done_int_st1().bit()),
-            )
-            .field(
-                "slc1_tx_suc_eof_int_st1",
-                &format_args!("{}", self.slc1_tx_suc_eof_int_st1().bit()),
-            )
-            .field(
-                "slc1_rx_done_int_st1",
-                &format_args!("{}", self.slc1_rx_done_int_st1().bit()),
-            )
-            .field(
-                "slc1_rx_eof_int_st1",
-                &format_args!("{}", self.slc1_rx_eof_int_st1().bit()),
-            )
-            .field(
-                "slc1_tohost_int_st1",
-                &format_args!("{}", self.slc1_tohost_int_st1().bit()),
-            )
-            .field(
-                "slc1_tx_dscr_err_int_st1",
-                &format_args!("{}", self.slc1_tx_dscr_err_int_st1().bit()),
-            )
-            .field(
-                "slc1_rx_dscr_err_int_st1",
-                &format_args!("{}", self.slc1_rx_dscr_err_int_st1().bit()),
-            )
+            .field("frhost_bit8_int_st1", &self.frhost_bit8_int_st1())
+            .field("frhost_bit9_int_st1", &self.frhost_bit9_int_st1())
+            .field("frhost_bit10_int_st1", &self.frhost_bit10_int_st1())
+            .field("frhost_bit11_int_st1", &self.frhost_bit11_int_st1())
+            .field("frhost_bit12_int_st1", &self.frhost_bit12_int_st1())
+            .field("frhost_bit13_int_st1", &self.frhost_bit13_int_st1())
+            .field("frhost_bit14_int_st1", &self.frhost_bit14_int_st1())
+            .field("frhost_bit15_int_st1", &self.frhost_bit15_int_st1())
+            .field("slc1_rx_start_int_st1", &self.slc1_rx_start_int_st1())
+            .field("slc1_tx_start_int_st1", &self.slc1_tx_start_int_st1())
+            .field("slc1_rx_udf_int_st1", &self.slc1_rx_udf_int_st1())
+            .field("slc1_tx_ovf_int_st1", &self.slc1_tx_ovf_int_st1())
+            .field("slc1_token0_1to0_int_st1", &self.slc1_token0_1to0_int_st1())
+            .field("slc1_token1_1to0_int_st1", &self.slc1_token1_1to0_int_st1())
+            .field("slc1_tx_done_int_st1", &self.slc1_tx_done_int_st1())
+            .field("slc1_tx_suc_eof_int_st1", &self.slc1_tx_suc_eof_int_st1())
+            .field("slc1_rx_done_int_st1", &self.slc1_rx_done_int_st1())
+            .field("slc1_rx_eof_int_st1", &self.slc1_rx_eof_int_st1())
+            .field("slc1_tohost_int_st1", &self.slc1_tohost_int_st1())
+            .field("slc1_tx_dscr_err_int_st1", &self.slc1_tx_dscr_err_int_st1())
+            .field("slc1_rx_dscr_err_int_st1", &self.slc1_rx_dscr_err_int_st1())
             .field(
                 "slc1_tx_dscr_empty_int_st1",
-                &format_args!("{}", self.slc1_tx_dscr_empty_int_st1().bit()),
-            )
-            .field(
-                "slc1_host_rd_ack_int_st1",
-                &format_args!("{}", self.slc1_host_rd_ack_int_st1().bit()),
+                &self.slc1_tx_dscr_empty_int_st1(),
             )
+            .field("slc1_host_rd_ack_int_st1", &self.slc1_host_rd_ack_int_st1())
             .field(
                 "slc1_wr_retry_done_int_st1",
-                &format_args!("{}", self.slc1_wr_retry_done_int_st1().bit()),
-            )
-            .field(
-                "slc1_tx_err_eof_int_st1",
-                &format_args!("{}", self.slc1_tx_err_eof_int_st1().bit()),
+                &self.slc1_wr_retry_done_int_st1(),
             )
+            .field("slc1_tx_err_eof_int_st1", &self.slc1_tx_err_eof_int_st1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1INT_ST1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`_1int_st1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct _1INT_ST1_SPEC;
 impl crate::RegisterSpec for _1INT_ST1_SPEC {
diff --git a/esp32/src/slc/_1rx_link.rs b/esp32/src/slc/_1rx_link.rs
index 569e7d2d8f..19984b481f 100644
--- a/esp32/src/slc/_1rx_link.rs
+++ b/esp32/src/slc/_1rx_link.rs
@@ -60,39 +60,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1RX_LINK")
-            .field(
-                "slc1_rxlink_addr",
-                &format_args!("{}", self.slc1_rxlink_addr().bits()),
-            )
-            .field(
-                "slc1_bt_packet",
-                &format_args!("{}", self.slc1_bt_packet().bit()),
-            )
-            .field(
-                "slc1_rxlink_stop",
-                &format_args!("{}", self.slc1_rxlink_stop().bit()),
-            )
-            .field(
-                "slc1_rxlink_start",
-                &format_args!("{}", self.slc1_rxlink_start().bit()),
-            )
-            .field(
-                "slc1_rxlink_restart",
-                &format_args!("{}", self.slc1_rxlink_restart().bit()),
-            )
-            .field(
-                "slc1_rxlink_park",
-                &format_args!("{}", self.slc1_rxlink_park().bit()),
-            )
+            .field("slc1_rxlink_addr", &self.slc1_rxlink_addr())
+            .field("slc1_bt_packet", &self.slc1_bt_packet())
+            .field("slc1_rxlink_stop", &self.slc1_rxlink_stop())
+            .field("slc1_rxlink_start", &self.slc1_rxlink_start())
+            .field("slc1_rxlink_restart", &self.slc1_rxlink_restart())
+            .field("slc1_rxlink_park", &self.slc1_rxlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1RX_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
diff --git a/esp32/src/slc/_1rxfifo_push.rs b/esp32/src/slc/_1rxfifo_push.rs
index 7d4fe2840d..654c89c7d4 100644
--- a/esp32/src/slc/_1rxfifo_push.rs
+++ b/esp32/src/slc/_1rxfifo_push.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1RXFIFO_PUSH")
-            .field(
-                "slc1_rxfifo_wdata",
-                &format_args!("{}", self.slc1_rxfifo_wdata().bits()),
-            )
-            .field(
-                "slc1_rxfifo_push",
-                &format_args!("{}", self.slc1_rxfifo_push().bit()),
-            )
+            .field("slc1_rxfifo_wdata", &self.slc1_rxfifo_wdata())
+            .field("slc1_rxfifo_push", &self.slc1_rxfifo_push())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1RXFIFO_PUSH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
diff --git a/esp32/src/slc/_1token0.rs b/esp32/src/slc/_1token0.rs
index b2ab89934f..798b3e80a7 100644
--- a/esp32/src/slc/_1token0.rs
+++ b/esp32/src/slc/_1token0.rs
@@ -23,19 +23,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1TOKEN0")
-            .field(
-                "slc1_token0",
-                &format_args!("{}", self.slc1_token0().bits()),
-            )
+            .field("slc1_token0", &self.slc1_token0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1TOKEN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
diff --git a/esp32/src/slc/_1token1.rs b/esp32/src/slc/_1token1.rs
index 4cbed76813..c77a8f02ea 100644
--- a/esp32/src/slc/_1token1.rs
+++ b/esp32/src/slc/_1token1.rs
@@ -23,19 +23,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1TOKEN1")
-            .field(
-                "slc1_token1",
-                &format_args!("{}", self.slc1_token1().bits()),
-            )
+            .field("slc1_token1", &self.slc1_token1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1TOKEN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
diff --git a/esp32/src/slc/_1tx_link.rs b/esp32/src/slc/_1tx_link.rs
index af2eb79ce6..e7a0b290ee 100644
--- a/esp32/src/slc/_1tx_link.rs
+++ b/esp32/src/slc/_1tx_link.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1TX_LINK")
-            .field(
-                "slc1_txlink_addr",
-                &format_args!("{}", self.slc1_txlink_addr().bits()),
-            )
-            .field(
-                "slc1_txlink_stop",
-                &format_args!("{}", self.slc1_txlink_stop().bit()),
-            )
-            .field(
-                "slc1_txlink_start",
-                &format_args!("{}", self.slc1_txlink_start().bit()),
-            )
-            .field(
-                "slc1_txlink_restart",
-                &format_args!("{}", self.slc1_txlink_restart().bit()),
-            )
-            .field(
-                "slc1_txlink_park",
-                &format_args!("{}", self.slc1_txlink_park().bit()),
-            )
+            .field("slc1_txlink_addr", &self.slc1_txlink_addr())
+            .field("slc1_txlink_stop", &self.slc1_txlink_stop())
+            .field("slc1_txlink_start", &self.slc1_txlink_start())
+            .field("slc1_txlink_restart", &self.slc1_txlink_restart())
+            .field("slc1_txlink_park", &self.slc1_txlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1TX_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
diff --git a/esp32/src/slc/_1txfifo_pop.rs b/esp32/src/slc/_1txfifo_pop.rs
index 1e4bb1fe44..4221f38b34 100644
--- a/esp32/src/slc/_1txfifo_pop.rs
+++ b/esp32/src/slc/_1txfifo_pop.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("_1TXFIFO_POP")
-            .field(
-                "slc1_txfifo_rdata",
-                &format_args!("{}", self.slc1_txfifo_rdata().bits()),
-            )
-            .field(
-                "slc1_txfifo_pop",
-                &format_args!("{}", self.slc1_txfifo_pop().bit()),
-            )
+            .field("slc1_txfifo_rdata", &self.slc1_txfifo_rdata())
+            .field("slc1_txfifo_pop", &self.slc1_txfifo_pop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<_1TXFIFO_POP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16"]
     #[inline(always)]
diff --git a/esp32/src/slc/ahb_test.rs b/esp32/src/slc/ahb_test.rs
index 29a0221d0f..091f96998f 100644
--- a/esp32/src/slc/ahb_test.rs
+++ b/esp32/src/slc/ahb_test.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_TEST")
-            .field(
-                "ahb_testmode",
-                &format_args!("{}", self.ahb_testmode().bits()),
-            )
-            .field(
-                "ahb_testaddr",
-                &format_args!("{}", self.ahb_testaddr().bits()),
-            )
+            .field("ahb_testmode", &self.ahb_testmode())
+            .field("ahb_testaddr", &self.ahb_testaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_TEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32/src/slc/bridge_conf.rs b/esp32/src/slc/bridge_conf.rs
index 03e7268545..b5ee83453d 100644
--- a/esp32/src/slc/bridge_conf.rs
+++ b/esp32/src/slc/bridge_conf.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BRIDGE_CONF")
-            .field("txeof_ena", &format_args!("{}", self.txeof_ena().bits()))
-            .field(
-                "fifo_map_ena",
-                &format_args!("{}", self.fifo_map_ena().bits()),
-            )
-            .field(
-                "slc0_tx_dummy_mode",
-                &format_args!("{}", self.slc0_tx_dummy_mode().bit()),
-            )
-            .field(
-                "hda_map_128k",
-                &format_args!("{}", self.hda_map_128k().bit()),
-            )
-            .field(
-                "slc1_tx_dummy_mode",
-                &format_args!("{}", self.slc1_tx_dummy_mode().bit()),
-            )
-            .field(
-                "tx_push_idle_num",
-                &format_args!("{}", self.tx_push_idle_num().bits()),
-            )
+            .field("txeof_ena", &self.txeof_ena())
+            .field("fifo_map_ena", &self.fifo_map_ena())
+            .field("slc0_tx_dummy_mode", &self.slc0_tx_dummy_mode())
+            .field("hda_map_128k", &self.hda_map_128k())
+            .field("slc1_tx_dummy_mode", &self.slc1_tx_dummy_mode())
+            .field("tx_push_idle_num", &self.tx_push_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BRIDGE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32/src/slc/cmd_infor0.rs b/esp32/src/slc/cmd_infor0.rs
index 0ae3f8bcb8..44102ce338 100644
--- a/esp32/src/slc/cmd_infor0.rs
+++ b/esp32/src/slc/cmd_infor0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD_INFOR0")
-            .field(
-                "cmd_content0",
-                &format_args!("{}", self.cmd_content0().bits()),
-            )
+            .field("cmd_content0", &self.cmd_content0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_INFOR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_infor0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CMD_INFOR0_SPEC;
 impl crate::RegisterSpec for CMD_INFOR0_SPEC {
diff --git a/esp32/src/slc/cmd_infor1.rs b/esp32/src/slc/cmd_infor1.rs
index 950ac13e8a..3b6e07178a 100644
--- a/esp32/src/slc/cmd_infor1.rs
+++ b/esp32/src/slc/cmd_infor1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD_INFOR1")
-            .field(
-                "cmd_content1",
-                &format_args!("{}", self.cmd_content1().bits()),
-            )
+            .field("cmd_content1", &self.cmd_content1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_INFOR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_infor1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CMD_INFOR1_SPEC;
 impl crate::RegisterSpec for CMD_INFOR1_SPEC {
diff --git a/esp32/src/slc/conf0.rs b/esp32/src/slc/conf0.rs
index c65fecd53b..8a98356f32 100644
--- a/esp32/src/slc/conf0.rs
+++ b/esp32/src/slc/conf0.rs
@@ -296,128 +296,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("slc0_tx_rst", &format_args!("{}", self.slc0_tx_rst().bit()))
-            .field("slc0_rx_rst", &format_args!("{}", self.slc0_rx_rst().bit()))
-            .field(
-                "ahbm_fifo_rst",
-                &format_args!("{}", self.ahbm_fifo_rst().bit()),
-            )
-            .field("ahbm_rst", &format_args!("{}", self.ahbm_rst().bit()))
-            .field(
-                "slc0_tx_loop_test",
-                &format_args!("{}", self.slc0_tx_loop_test().bit()),
-            )
-            .field(
-                "slc0_rx_loop_test",
-                &format_args!("{}", self.slc0_rx_loop_test().bit()),
-            )
-            .field(
-                "slc0_rx_auto_wrback",
-                &format_args!("{}", self.slc0_rx_auto_wrback().bit()),
-            )
-            .field(
-                "slc0_rx_no_restart_clr",
-                &format_args!("{}", self.slc0_rx_no_restart_clr().bit()),
-            )
-            .field(
-                "slc0_rxdscr_burst_en",
-                &format_args!("{}", self.slc0_rxdscr_burst_en().bit()),
-            )
-            .field(
-                "slc0_rxdata_burst_en",
-                &format_args!("{}", self.slc0_rxdata_burst_en().bit()),
-            )
-            .field(
-                "slc0_rxlink_auto_ret",
-                &format_args!("{}", self.slc0_rxlink_auto_ret().bit()),
-            )
-            .field(
-                "slc0_txlink_auto_ret",
-                &format_args!("{}", self.slc0_txlink_auto_ret().bit()),
-            )
-            .field(
-                "slc0_txdscr_burst_en",
-                &format_args!("{}", self.slc0_txdscr_burst_en().bit()),
-            )
-            .field(
-                "slc0_txdata_burst_en",
-                &format_args!("{}", self.slc0_txdata_burst_en().bit()),
-            )
-            .field(
-                "slc0_token_auto_clr",
-                &format_args!("{}", self.slc0_token_auto_clr().bit()),
-            )
-            .field(
-                "slc0_token_sel",
-                &format_args!("{}", self.slc0_token_sel().bit()),
-            )
-            .field("slc1_tx_rst", &format_args!("{}", self.slc1_tx_rst().bit()))
-            .field("slc1_rx_rst", &format_args!("{}", self.slc1_rx_rst().bit()))
-            .field(
-                "slc0_wr_retry_mask_en",
-                &format_args!("{}", self.slc0_wr_retry_mask_en().bit()),
-            )
-            .field(
-                "slc1_wr_retry_mask_en",
-                &format_args!("{}", self.slc1_wr_retry_mask_en().bit()),
-            )
-            .field(
-                "slc1_tx_loop_test",
-                &format_args!("{}", self.slc1_tx_loop_test().bit()),
-            )
-            .field(
-                "slc1_rx_loop_test",
-                &format_args!("{}", self.slc1_rx_loop_test().bit()),
-            )
-            .field(
-                "slc1_rx_auto_wrback",
-                &format_args!("{}", self.slc1_rx_auto_wrback().bit()),
-            )
-            .field(
-                "slc1_rx_no_restart_clr",
-                &format_args!("{}", self.slc1_rx_no_restart_clr().bit()),
-            )
-            .field(
-                "slc1_rxdscr_burst_en",
-                &format_args!("{}", self.slc1_rxdscr_burst_en().bit()),
-            )
-            .field(
-                "slc1_rxdata_burst_en",
-                &format_args!("{}", self.slc1_rxdata_burst_en().bit()),
-            )
-            .field(
-                "slc1_rxlink_auto_ret",
-                &format_args!("{}", self.slc1_rxlink_auto_ret().bit()),
-            )
-            .field(
-                "slc1_txlink_auto_ret",
-                &format_args!("{}", self.slc1_txlink_auto_ret().bit()),
-            )
-            .field(
-                "slc1_txdscr_burst_en",
-                &format_args!("{}", self.slc1_txdscr_burst_en().bit()),
-            )
-            .field(
-                "slc1_txdata_burst_en",
-                &format_args!("{}", self.slc1_txdata_burst_en().bit()),
-            )
-            .field(
-                "slc1_token_auto_clr",
-                &format_args!("{}", self.slc1_token_auto_clr().bit()),
-            )
-            .field(
-                "slc1_token_sel",
-                &format_args!("{}", self.slc1_token_sel().bit()),
-            )
+            .field("slc0_tx_rst", &self.slc0_tx_rst())
+            .field("slc0_rx_rst", &self.slc0_rx_rst())
+            .field("ahbm_fifo_rst", &self.ahbm_fifo_rst())
+            .field("ahbm_rst", &self.ahbm_rst())
+            .field("slc0_tx_loop_test", &self.slc0_tx_loop_test())
+            .field("slc0_rx_loop_test", &self.slc0_rx_loop_test())
+            .field("slc0_rx_auto_wrback", &self.slc0_rx_auto_wrback())
+            .field("slc0_rx_no_restart_clr", &self.slc0_rx_no_restart_clr())
+            .field("slc0_rxdscr_burst_en", &self.slc0_rxdscr_burst_en())
+            .field("slc0_rxdata_burst_en", &self.slc0_rxdata_burst_en())
+            .field("slc0_rxlink_auto_ret", &self.slc0_rxlink_auto_ret())
+            .field("slc0_txlink_auto_ret", &self.slc0_txlink_auto_ret())
+            .field("slc0_txdscr_burst_en", &self.slc0_txdscr_burst_en())
+            .field("slc0_txdata_burst_en", &self.slc0_txdata_burst_en())
+            .field("slc0_token_auto_clr", &self.slc0_token_auto_clr())
+            .field("slc0_token_sel", &self.slc0_token_sel())
+            .field("slc1_tx_rst", &self.slc1_tx_rst())
+            .field("slc1_rx_rst", &self.slc1_rx_rst())
+            .field("slc0_wr_retry_mask_en", &self.slc0_wr_retry_mask_en())
+            .field("slc1_wr_retry_mask_en", &self.slc1_wr_retry_mask_en())
+            .field("slc1_tx_loop_test", &self.slc1_tx_loop_test())
+            .field("slc1_rx_loop_test", &self.slc1_rx_loop_test())
+            .field("slc1_rx_auto_wrback", &self.slc1_rx_auto_wrback())
+            .field("slc1_rx_no_restart_clr", &self.slc1_rx_no_restart_clr())
+            .field("slc1_rxdscr_burst_en", &self.slc1_rxdscr_burst_en())
+            .field("slc1_rxdata_burst_en", &self.slc1_rxdata_burst_en())
+            .field("slc1_rxlink_auto_ret", &self.slc1_rxlink_auto_ret())
+            .field("slc1_txlink_auto_ret", &self.slc1_txlink_auto_ret())
+            .field("slc1_txdscr_burst_en", &self.slc1_txdscr_burst_en())
+            .field("slc1_txdata_burst_en", &self.slc1_txdata_burst_en())
+            .field("slc1_token_auto_clr", &self.slc1_token_auto_clr())
+            .field("slc1_token_sel", &self.slc1_token_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slc/conf1.rs b/esp32/src/slc/conf1.rs
index bcb2ecfb2f..5fc3875a46 100644
--- a/esp32/src/slc/conf1.rs
+++ b/esp32/src/slc/conf1.rs
@@ -134,65 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "slc0_check_owner",
-                &format_args!("{}", self.slc0_check_owner().bit()),
-            )
-            .field(
-                "slc0_tx_check_sum_en",
-                &format_args!("{}", self.slc0_tx_check_sum_en().bit()),
-            )
-            .field(
-                "slc0_rx_check_sum_en",
-                &format_args!("{}", self.slc0_rx_check_sum_en().bit()),
-            )
-            .field("cmd_hold_en", &format_args!("{}", self.cmd_hold_en().bit()))
-            .field(
-                "slc0_len_auto_clr",
-                &format_args!("{}", self.slc0_len_auto_clr().bit()),
-            )
-            .field(
-                "slc0_tx_stitch_en",
-                &format_args!("{}", self.slc0_tx_stitch_en().bit()),
-            )
-            .field(
-                "slc0_rx_stitch_en",
-                &format_args!("{}", self.slc0_rx_stitch_en().bit()),
-            )
-            .field(
-                "slc1_check_owner",
-                &format_args!("{}", self.slc1_check_owner().bit()),
-            )
-            .field(
-                "slc1_tx_check_sum_en",
-                &format_args!("{}", self.slc1_tx_check_sum_en().bit()),
-            )
-            .field(
-                "slc1_rx_check_sum_en",
-                &format_args!("{}", self.slc1_rx_check_sum_en().bit()),
-            )
-            .field(
-                "host_int_level_sel",
-                &format_args!("{}", self.host_int_level_sel().bit()),
-            )
-            .field(
-                "slc1_tx_stitch_en",
-                &format_args!("{}", self.slc1_tx_stitch_en().bit()),
-            )
-            .field(
-                "slc1_rx_stitch_en",
-                &format_args!("{}", self.slc1_rx_stitch_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("slc0_check_owner", &self.slc0_check_owner())
+            .field("slc0_tx_check_sum_en", &self.slc0_tx_check_sum_en())
+            .field("slc0_rx_check_sum_en", &self.slc0_rx_check_sum_en())
+            .field("cmd_hold_en", &self.cmd_hold_en())
+            .field("slc0_len_auto_clr", &self.slc0_len_auto_clr())
+            .field("slc0_tx_stitch_en", &self.slc0_tx_stitch_en())
+            .field("slc0_rx_stitch_en", &self.slc0_rx_stitch_en())
+            .field("slc1_check_owner", &self.slc1_check_owner())
+            .field("slc1_tx_check_sum_en", &self.slc1_tx_check_sum_en())
+            .field("slc1_rx_check_sum_en", &self.slc1_rx_check_sum_en())
+            .field("host_int_level_sel", &self.host_int_level_sel())
+            .field("slc1_tx_stitch_en", &self.slc1_tx_stitch_en())
+            .field("slc1_rx_stitch_en", &self.slc1_rx_stitch_en())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slc/date.rs b/esp32/src/slc/date.rs
index c531532dec..e365414ef8 100644
--- a/esp32/src/slc/date.rs
+++ b/esp32/src/slc/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/slc/id.rs b/esp32/src/slc/id.rs
index 8c38a11242..e43cd18525 100644
--- a/esp32/src/slc/id.rs
+++ b/esp32/src/slc/id.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("ID")
-            .field("id", &format_args!("{}", self.id().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("ID").field("id", &self.id()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/slc/rx_dscr_conf.rs b/esp32/src/slc/rx_dscr_conf.rs
index dca8a83a25..86b300471b 100644
--- a/esp32/src/slc/rx_dscr_conf.rs
+++ b/esp32/src/slc/rx_dscr_conf.rs
@@ -116,63 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_DSCR_CONF")
-            .field(
-                "slc0_token_no_replace",
-                &format_args!("{}", self.slc0_token_no_replace().bit()),
-            )
-            .field(
-                "slc0_infor_no_replace",
-                &format_args!("{}", self.slc0_infor_no_replace().bit()),
-            )
-            .field(
-                "slc0_rx_fill_mode",
-                &format_args!("{}", self.slc0_rx_fill_mode().bit()),
-            )
-            .field(
-                "slc0_rx_eof_mode",
-                &format_args!("{}", self.slc0_rx_eof_mode().bit()),
-            )
-            .field(
-                "slc0_rx_fill_en",
-                &format_args!("{}", self.slc0_rx_fill_en().bit()),
-            )
-            .field(
-                "slc0_rd_retry_threshold",
-                &format_args!("{}", self.slc0_rd_retry_threshold().bits()),
-            )
-            .field(
-                "slc1_token_no_replace",
-                &format_args!("{}", self.slc1_token_no_replace().bit()),
-            )
-            .field(
-                "slc1_infor_no_replace",
-                &format_args!("{}", self.slc1_infor_no_replace().bit()),
-            )
-            .field(
-                "slc1_rx_fill_mode",
-                &format_args!("{}", self.slc1_rx_fill_mode().bit()),
-            )
-            .field(
-                "slc1_rx_eof_mode",
-                &format_args!("{}", self.slc1_rx_eof_mode().bit()),
-            )
-            .field(
-                "slc1_rx_fill_en",
-                &format_args!("{}", self.slc1_rx_fill_en().bit()),
-            )
-            .field(
-                "slc1_rd_retry_threshold",
-                &format_args!("{}", self.slc1_rd_retry_threshold().bits()),
-            )
+            .field("slc0_token_no_replace", &self.slc0_token_no_replace())
+            .field("slc0_infor_no_replace", &self.slc0_infor_no_replace())
+            .field("slc0_rx_fill_mode", &self.slc0_rx_fill_mode())
+            .field("slc0_rx_eof_mode", &self.slc0_rx_eof_mode())
+            .field("slc0_rx_fill_en", &self.slc0_rx_fill_en())
+            .field("slc0_rd_retry_threshold", &self.slc0_rd_retry_threshold())
+            .field("slc1_token_no_replace", &self.slc1_token_no_replace())
+            .field("slc1_infor_no_replace", &self.slc1_infor_no_replace())
+            .field("slc1_rx_fill_mode", &self.slc1_rx_fill_mode())
+            .field("slc1_rx_eof_mode", &self.slc1_rx_eof_mode())
+            .field("slc1_rx_fill_en", &self.slc1_rx_fill_en())
+            .field("slc1_rd_retry_threshold", &self.slc1_rd_retry_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_DSCR_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slc/rx_status.rs b/esp32/src/slc/rx_status.rs
index 5c733b9475..f902470b90 100644
--- a/esp32/src/slc/rx_status.rs
+++ b/esp32/src/slc/rx_status.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_STATUS")
-            .field(
-                "slc0_rx_full",
-                &format_args!("{}", self.slc0_rx_full().bit()),
-            )
-            .field(
-                "slc0_rx_empty",
-                &format_args!("{}", self.slc0_rx_empty().bit()),
-            )
-            .field(
-                "slc1_rx_full",
-                &format_args!("{}", self.slc1_rx_full().bit()),
-            )
-            .field(
-                "slc1_rx_empty",
-                &format_args!("{}", self.slc1_rx_empty().bit()),
-            )
+            .field("slc0_rx_full", &self.slc0_rx_full())
+            .field("slc0_rx_empty", &self.slc0_rx_empty())
+            .field("slc1_rx_full", &self.slc1_rx_full())
+            .field("slc1_rx_empty", &self.slc1_rx_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_STATUS_SPEC;
 impl crate::RegisterSpec for RX_STATUS_SPEC {
diff --git a/esp32/src/slc/sdio_crc_st0.rs b/esp32/src/slc/sdio_crc_st0.rs
index 6db8e7d170..2df91adcc4 100644
--- a/esp32/src/slc/sdio_crc_st0.rs
+++ b/esp32/src/slc/sdio_crc_st0.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_CRC_ST0")
-            .field(
-                "dat0_crc_err_cnt",
-                &format_args!("{}", self.dat0_crc_err_cnt().bits()),
-            )
-            .field(
-                "dat1_crc_err_cnt",
-                &format_args!("{}", self.dat1_crc_err_cnt().bits()),
-            )
-            .field(
-                "dat2_crc_err_cnt",
-                &format_args!("{}", self.dat2_crc_err_cnt().bits()),
-            )
-            .field(
-                "dat3_crc_err_cnt",
-                &format_args!("{}", self.dat3_crc_err_cnt().bits()),
-            )
+            .field("dat0_crc_err_cnt", &self.dat0_crc_err_cnt())
+            .field("dat1_crc_err_cnt", &self.dat1_crc_err_cnt())
+            .field("dat2_crc_err_cnt", &self.dat2_crc_err_cnt())
+            .field("dat3_crc_err_cnt", &self.dat3_crc_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_CRC_ST0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdio_crc_st0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SDIO_CRC_ST0_SPEC;
 impl crate::RegisterSpec for SDIO_CRC_ST0_SPEC {
diff --git a/esp32/src/slc/sdio_crc_st1.rs b/esp32/src/slc/sdio_crc_st1.rs
index d195148585..0bfb940b18 100644
--- a/esp32/src/slc/sdio_crc_st1.rs
+++ b/esp32/src/slc/sdio_crc_st1.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_CRC_ST1")
-            .field(
-                "cmd_crc_err_cnt",
-                &format_args!("{}", self.cmd_crc_err_cnt().bits()),
-            )
-            .field("err_cnt_clr", &format_args!("{}", self.err_cnt_clr().bit()))
+            .field("cmd_crc_err_cnt", &self.cmd_crc_err_cnt())
+            .field("err_cnt_clr", &self.err_cnt_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_CRC_ST1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31"]
     #[inline(always)]
diff --git a/esp32/src/slc/sdio_st.rs b/esp32/src/slc/sdio_st.rs
index 987f9012bb..6c466ac6b1 100644
--- a/esp32/src/slc/sdio_st.rs
+++ b/esp32/src/slc/sdio_st.rs
@@ -48,27 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_ST")
-            .field("cmd_st", &format_args!("{}", self.cmd_st().bits()))
-            .field("func_st", &format_args!("{}", self.func_st().bits()))
-            .field("sdio_wakeup", &format_args!("{}", self.sdio_wakeup().bit()))
-            .field("bus_st", &format_args!("{}", self.bus_st().bits()))
-            .field(
-                "func1_acc_state",
-                &format_args!("{}", self.func1_acc_state().bits()),
-            )
-            .field(
-                "func2_acc_state",
-                &format_args!("{}", self.func2_acc_state().bits()),
-            )
+            .field("cmd_st", &self.cmd_st())
+            .field("func_st", &self.func_st())
+            .field("sdio_wakeup", &self.sdio_wakeup())
+            .field("bus_st", &self.bus_st())
+            .field("func1_acc_state", &self.func1_acc_state())
+            .field("func2_acc_state", &self.func2_acc_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdio_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SDIO_ST_SPEC;
 impl crate::RegisterSpec for SDIO_ST_SPEC {
diff --git a/esp32/src/slc/seq_position.rs b/esp32/src/slc/seq_position.rs
index f53d8cc3fd..bb3b8f208d 100644
--- a/esp32/src/slc/seq_position.rs
+++ b/esp32/src/slc/seq_position.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEQ_POSITION")
-            .field(
-                "slc0_seq_position",
-                &format_args!("{}", self.slc0_seq_position().bits()),
-            )
-            .field(
-                "slc1_seq_position",
-                &format_args!("{}", self.slc1_seq_position().bits()),
-            )
+            .field("slc0_seq_position", &self.slc0_seq_position())
+            .field("slc1_seq_position", &self.slc1_seq_position())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEQ_POSITION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slc/token_lat.rs b/esp32/src/slc/token_lat.rs
index 1da245e711..e6baac04f5 100644
--- a/esp32/src/slc/token_lat.rs
+++ b/esp32/src/slc/token_lat.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOKEN_LAT")
-            .field("slc0_token", &format_args!("{}", self.slc0_token().bits()))
-            .field("slc1_token", &format_args!("{}", self.slc1_token().bits()))
+            .field("slc0_token", &self.slc0_token())
+            .field("slc1_token", &self.slc1_token())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOKEN_LAT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`token_lat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TOKEN_LAT_SPEC;
 impl crate::RegisterSpec for TOKEN_LAT_SPEC {
diff --git a/esp32/src/slc/tx_dscr_conf.rs b/esp32/src/slc/tx_dscr_conf.rs
index 337d6cd0a4..f365113d03 100644
--- a/esp32/src/slc/tx_dscr_conf.rs
+++ b/esp32/src/slc/tx_dscr_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_DSCR_CONF")
-            .field(
-                "wr_retry_threshold",
-                &format_args!("{}", self.wr_retry_threshold().bits()),
-            )
+            .field("wr_retry_threshold", &self.wr_retry_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_DSCR_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32/src/slc/tx_status.rs b/esp32/src/slc/tx_status.rs
index 51121bace8..80dd63e879 100644
--- a/esp32/src/slc/tx_status.rs
+++ b/esp32/src/slc/tx_status.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_STATUS")
-            .field(
-                "slc0_tx_full",
-                &format_args!("{}", self.slc0_tx_full().bit()),
-            )
-            .field(
-                "slc0_tx_empty",
-                &format_args!("{}", self.slc0_tx_empty().bit()),
-            )
-            .field(
-                "slc1_tx_full",
-                &format_args!("{}", self.slc1_tx_full().bit()),
-            )
-            .field(
-                "slc1_tx_empty",
-                &format_args!("{}", self.slc1_tx_empty().bit()),
-            )
+            .field("slc0_tx_full", &self.slc0_tx_full())
+            .field("slc0_tx_empty", &self.slc0_tx_empty())
+            .field("slc1_tx_full", &self.slc1_tx_full())
+            .field("slc1_tx_empty", &self.slc1_tx_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TX_STATUS_SPEC;
 impl crate::RegisterSpec for TX_STATUS_SPEC {
diff --git a/esp32/src/slchost/host_slc0_host_pf.rs b/esp32/src/slchost/host_slc0_host_pf.rs
index 3fa957f9ad..cf1d8823ae 100644
--- a/esp32/src/slchost/host_slc0_host_pf.rs
+++ b/esp32/src/slchost/host_slc0_host_pf.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLC0_HOST_PF")
-            .field(
-                "host_slc0_pf_data",
-                &format_args!("{}", self.host_slc0_pf_data().bits()),
-            )
+            .field("host_slc0_pf_data", &self.host_slc0_pf_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC0_HOST_PF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slc0_host_pf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLC0_HOST_PF_SPEC;
 impl crate::RegisterSpec for HOST_SLC0_HOST_PF_SPEC {
diff --git a/esp32/src/slchost/host_slc0host_func1_int_ena.rs b/esp32/src/slchost/host_slc0host_func1_int_ena.rs
index d62f8c168d..01473bf785 100644
--- a/esp32/src/slchost/host_slc0host_func1_int_ena.rs
+++ b/esp32/src/slchost/host_slc0host_func1_int_ena.rs
@@ -244,117 +244,111 @@ impl core::fmt::Debug for R {
         f.debug_struct("HOST_SLC0HOST_FUNC1_INT_ENA")
             .field(
                 "host_fn1_slc0_tohost_bit0_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_tohost_bit0_int_ena().bit()),
+                &self.host_fn1_slc0_tohost_bit0_int_ena(),
             )
             .field(
                 "host_fn1_slc0_tohost_bit1_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_tohost_bit1_int_ena().bit()),
+                &self.host_fn1_slc0_tohost_bit1_int_ena(),
             )
             .field(
                 "host_fn1_slc0_tohost_bit2_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_tohost_bit2_int_ena().bit()),
+                &self.host_fn1_slc0_tohost_bit2_int_ena(),
             )
             .field(
                 "host_fn1_slc0_tohost_bit3_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_tohost_bit3_int_ena().bit()),
+                &self.host_fn1_slc0_tohost_bit3_int_ena(),
             )
             .field(
                 "host_fn1_slc0_tohost_bit4_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_tohost_bit4_int_ena().bit()),
+                &self.host_fn1_slc0_tohost_bit4_int_ena(),
             )
             .field(
                 "host_fn1_slc0_tohost_bit5_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_tohost_bit5_int_ena().bit()),
+                &self.host_fn1_slc0_tohost_bit5_int_ena(),
             )
             .field(
                 "host_fn1_slc0_tohost_bit6_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_tohost_bit6_int_ena().bit()),
+                &self.host_fn1_slc0_tohost_bit6_int_ena(),
             )
             .field(
                 "host_fn1_slc0_tohost_bit7_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_tohost_bit7_int_ena().bit()),
+                &self.host_fn1_slc0_tohost_bit7_int_ena(),
             )
             .field(
                 "host_fn1_slc0_token0_1to0_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_token0_1to0_int_ena().bit()),
+                &self.host_fn1_slc0_token0_1to0_int_ena(),
             )
             .field(
                 "host_fn1_slc0_token1_1to0_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_token1_1to0_int_ena().bit()),
+                &self.host_fn1_slc0_token1_1to0_int_ena(),
             )
             .field(
                 "host_fn1_slc0_token0_0to1_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_token0_0to1_int_ena().bit()),
+                &self.host_fn1_slc0_token0_0to1_int_ena(),
             )
             .field(
                 "host_fn1_slc0_token1_0to1_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_token1_0to1_int_ena().bit()),
+                &self.host_fn1_slc0_token1_0to1_int_ena(),
             )
             .field(
                 "host_fn1_slc0host_rx_sof_int_ena",
-                &format_args!("{}", self.host_fn1_slc0host_rx_sof_int_ena().bit()),
+                &self.host_fn1_slc0host_rx_sof_int_ena(),
             )
             .field(
                 "host_fn1_slc0host_rx_eof_int_ena",
-                &format_args!("{}", self.host_fn1_slc0host_rx_eof_int_ena().bit()),
+                &self.host_fn1_slc0host_rx_eof_int_ena(),
             )
             .field(
                 "host_fn1_slc0host_rx_start_int_ena",
-                &format_args!("{}", self.host_fn1_slc0host_rx_start_int_ena().bit()),
+                &self.host_fn1_slc0host_rx_start_int_ena(),
             )
             .field(
                 "host_fn1_slc0host_tx_start_int_ena",
-                &format_args!("{}", self.host_fn1_slc0host_tx_start_int_ena().bit()),
+                &self.host_fn1_slc0host_tx_start_int_ena(),
             )
             .field(
                 "host_fn1_slc0_rx_udf_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_rx_udf_int_ena().bit()),
+                &self.host_fn1_slc0_rx_udf_int_ena(),
             )
             .field(
                 "host_fn1_slc0_tx_ovf_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_tx_ovf_int_ena().bit()),
+                &self.host_fn1_slc0_tx_ovf_int_ena(),
             )
             .field(
                 "host_fn1_slc0_rx_pf_valid_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_rx_pf_valid_int_ena().bit()),
+                &self.host_fn1_slc0_rx_pf_valid_int_ena(),
             )
             .field(
                 "host_fn1_slc0_ext_bit0_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_ext_bit0_int_ena().bit()),
+                &self.host_fn1_slc0_ext_bit0_int_ena(),
             )
             .field(
                 "host_fn1_slc0_ext_bit1_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_ext_bit1_int_ena().bit()),
+                &self.host_fn1_slc0_ext_bit1_int_ena(),
             )
             .field(
                 "host_fn1_slc0_ext_bit2_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_ext_bit2_int_ena().bit()),
+                &self.host_fn1_slc0_ext_bit2_int_ena(),
             )
             .field(
                 "host_fn1_slc0_ext_bit3_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_ext_bit3_int_ena().bit()),
+                &self.host_fn1_slc0_ext_bit3_int_ena(),
             )
             .field(
                 "host_fn1_slc0_rx_new_packet_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_rx_new_packet_int_ena().bit()),
+                &self.host_fn1_slc0_rx_new_packet_int_ena(),
             )
             .field(
                 "host_fn1_slc0_host_rd_retry_int_ena",
-                &format_args!("{}", self.host_fn1_slc0_host_rd_retry_int_ena().bit()),
+                &self.host_fn1_slc0_host_rd_retry_int_ena(),
             )
             .field(
                 "host_fn1_gpio_sdio_int_ena",
-                &format_args!("{}", self.host_fn1_gpio_sdio_int_ena().bit()),
+                &self.host_fn1_gpio_sdio_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC0HOST_FUNC1_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slc0host_func2_int_ena.rs b/esp32/src/slchost/host_slc0host_func2_int_ena.rs
index 3fe8fdd5e2..c5ebdc531e 100644
--- a/esp32/src/slchost/host_slc0host_func2_int_ena.rs
+++ b/esp32/src/slchost/host_slc0host_func2_int_ena.rs
@@ -244,117 +244,111 @@ impl core::fmt::Debug for R {
         f.debug_struct("HOST_SLC0HOST_FUNC2_INT_ENA")
             .field(
                 "host_fn2_slc0_tohost_bit0_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_tohost_bit0_int_ena().bit()),
+                &self.host_fn2_slc0_tohost_bit0_int_ena(),
             )
             .field(
                 "host_fn2_slc0_tohost_bit1_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_tohost_bit1_int_ena().bit()),
+                &self.host_fn2_slc0_tohost_bit1_int_ena(),
             )
             .field(
                 "host_fn2_slc0_tohost_bit2_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_tohost_bit2_int_ena().bit()),
+                &self.host_fn2_slc0_tohost_bit2_int_ena(),
             )
             .field(
                 "host_fn2_slc0_tohost_bit3_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_tohost_bit3_int_ena().bit()),
+                &self.host_fn2_slc0_tohost_bit3_int_ena(),
             )
             .field(
                 "host_fn2_slc0_tohost_bit4_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_tohost_bit4_int_ena().bit()),
+                &self.host_fn2_slc0_tohost_bit4_int_ena(),
             )
             .field(
                 "host_fn2_slc0_tohost_bit5_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_tohost_bit5_int_ena().bit()),
+                &self.host_fn2_slc0_tohost_bit5_int_ena(),
             )
             .field(
                 "host_fn2_slc0_tohost_bit6_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_tohost_bit6_int_ena().bit()),
+                &self.host_fn2_slc0_tohost_bit6_int_ena(),
             )
             .field(
                 "host_fn2_slc0_tohost_bit7_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_tohost_bit7_int_ena().bit()),
+                &self.host_fn2_slc0_tohost_bit7_int_ena(),
             )
             .field(
                 "host_fn2_slc0_token0_1to0_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_token0_1to0_int_ena().bit()),
+                &self.host_fn2_slc0_token0_1to0_int_ena(),
             )
             .field(
                 "host_fn2_slc0_token1_1to0_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_token1_1to0_int_ena().bit()),
+                &self.host_fn2_slc0_token1_1to0_int_ena(),
             )
             .field(
                 "host_fn2_slc0_token0_0to1_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_token0_0to1_int_ena().bit()),
+                &self.host_fn2_slc0_token0_0to1_int_ena(),
             )
             .field(
                 "host_fn2_slc0_token1_0to1_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_token1_0to1_int_ena().bit()),
+                &self.host_fn2_slc0_token1_0to1_int_ena(),
             )
             .field(
                 "host_fn2_slc0host_rx_sof_int_ena",
-                &format_args!("{}", self.host_fn2_slc0host_rx_sof_int_ena().bit()),
+                &self.host_fn2_slc0host_rx_sof_int_ena(),
             )
             .field(
                 "host_fn2_slc0host_rx_eof_int_ena",
-                &format_args!("{}", self.host_fn2_slc0host_rx_eof_int_ena().bit()),
+                &self.host_fn2_slc0host_rx_eof_int_ena(),
             )
             .field(
                 "host_fn2_slc0host_rx_start_int_ena",
-                &format_args!("{}", self.host_fn2_slc0host_rx_start_int_ena().bit()),
+                &self.host_fn2_slc0host_rx_start_int_ena(),
             )
             .field(
                 "host_fn2_slc0host_tx_start_int_ena",
-                &format_args!("{}", self.host_fn2_slc0host_tx_start_int_ena().bit()),
+                &self.host_fn2_slc0host_tx_start_int_ena(),
             )
             .field(
                 "host_fn2_slc0_rx_udf_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_rx_udf_int_ena().bit()),
+                &self.host_fn2_slc0_rx_udf_int_ena(),
             )
             .field(
                 "host_fn2_slc0_tx_ovf_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_tx_ovf_int_ena().bit()),
+                &self.host_fn2_slc0_tx_ovf_int_ena(),
             )
             .field(
                 "host_fn2_slc0_rx_pf_valid_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_rx_pf_valid_int_ena().bit()),
+                &self.host_fn2_slc0_rx_pf_valid_int_ena(),
             )
             .field(
                 "host_fn2_slc0_ext_bit0_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_ext_bit0_int_ena().bit()),
+                &self.host_fn2_slc0_ext_bit0_int_ena(),
             )
             .field(
                 "host_fn2_slc0_ext_bit1_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_ext_bit1_int_ena().bit()),
+                &self.host_fn2_slc0_ext_bit1_int_ena(),
             )
             .field(
                 "host_fn2_slc0_ext_bit2_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_ext_bit2_int_ena().bit()),
+                &self.host_fn2_slc0_ext_bit2_int_ena(),
             )
             .field(
                 "host_fn2_slc0_ext_bit3_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_ext_bit3_int_ena().bit()),
+                &self.host_fn2_slc0_ext_bit3_int_ena(),
             )
             .field(
                 "host_fn2_slc0_rx_new_packet_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_rx_new_packet_int_ena().bit()),
+                &self.host_fn2_slc0_rx_new_packet_int_ena(),
             )
             .field(
                 "host_fn2_slc0_host_rd_retry_int_ena",
-                &format_args!("{}", self.host_fn2_slc0_host_rd_retry_int_ena().bit()),
+                &self.host_fn2_slc0_host_rd_retry_int_ena(),
             )
             .field(
                 "host_fn2_gpio_sdio_int_ena",
-                &format_args!("{}", self.host_fn2_gpio_sdio_int_ena().bit()),
+                &self.host_fn2_gpio_sdio_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC0HOST_FUNC2_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slc0host_int_ena.rs b/esp32/src/slchost/host_slc0host_int_ena.rs
index 9b32aacac6..b52a2f848c 100644
--- a/esp32/src/slchost/host_slc0host_int_ena.rs
+++ b/esp32/src/slchost/host_slc0host_int_ena.rs
@@ -244,117 +244,102 @@ impl core::fmt::Debug for R {
         f.debug_struct("HOST_SLC0HOST_INT_ENA")
             .field(
                 "host_slc0_tohost_bit0_int_ena",
-                &format_args!("{}", self.host_slc0_tohost_bit0_int_ena().bit()),
+                &self.host_slc0_tohost_bit0_int_ena(),
             )
             .field(
                 "host_slc0_tohost_bit1_int_ena",
-                &format_args!("{}", self.host_slc0_tohost_bit1_int_ena().bit()),
+                &self.host_slc0_tohost_bit1_int_ena(),
             )
             .field(
                 "host_slc0_tohost_bit2_int_ena",
-                &format_args!("{}", self.host_slc0_tohost_bit2_int_ena().bit()),
+                &self.host_slc0_tohost_bit2_int_ena(),
             )
             .field(
                 "host_slc0_tohost_bit3_int_ena",
-                &format_args!("{}", self.host_slc0_tohost_bit3_int_ena().bit()),
+                &self.host_slc0_tohost_bit3_int_ena(),
             )
             .field(
                 "host_slc0_tohost_bit4_int_ena",
-                &format_args!("{}", self.host_slc0_tohost_bit4_int_ena().bit()),
+                &self.host_slc0_tohost_bit4_int_ena(),
             )
             .field(
                 "host_slc0_tohost_bit5_int_ena",
-                &format_args!("{}", self.host_slc0_tohost_bit5_int_ena().bit()),
+                &self.host_slc0_tohost_bit5_int_ena(),
             )
             .field(
                 "host_slc0_tohost_bit6_int_ena",
-                &format_args!("{}", self.host_slc0_tohost_bit6_int_ena().bit()),
+                &self.host_slc0_tohost_bit6_int_ena(),
             )
             .field(
                 "host_slc0_tohost_bit7_int_ena",
-                &format_args!("{}", self.host_slc0_tohost_bit7_int_ena().bit()),
+                &self.host_slc0_tohost_bit7_int_ena(),
             )
             .field(
                 "host_slc0_token0_1to0_int_ena",
-                &format_args!("{}", self.host_slc0_token0_1to0_int_ena().bit()),
+                &self.host_slc0_token0_1to0_int_ena(),
             )
             .field(
                 "host_slc0_token1_1to0_int_ena",
-                &format_args!("{}", self.host_slc0_token1_1to0_int_ena().bit()),
+                &self.host_slc0_token1_1to0_int_ena(),
             )
             .field(
                 "host_slc0_token0_0to1_int_ena",
-                &format_args!("{}", self.host_slc0_token0_0to1_int_ena().bit()),
+                &self.host_slc0_token0_0to1_int_ena(),
             )
             .field(
                 "host_slc0_token1_0to1_int_ena",
-                &format_args!("{}", self.host_slc0_token1_0to1_int_ena().bit()),
+                &self.host_slc0_token1_0to1_int_ena(),
             )
             .field(
                 "host_slc0host_rx_sof_int_ena",
-                &format_args!("{}", self.host_slc0host_rx_sof_int_ena().bit()),
+                &self.host_slc0host_rx_sof_int_ena(),
             )
             .field(
                 "host_slc0host_rx_eof_int_ena",
-                &format_args!("{}", self.host_slc0host_rx_eof_int_ena().bit()),
+                &self.host_slc0host_rx_eof_int_ena(),
             )
             .field(
                 "host_slc0host_rx_start_int_ena",
-                &format_args!("{}", self.host_slc0host_rx_start_int_ena().bit()),
+                &self.host_slc0host_rx_start_int_ena(),
             )
             .field(
                 "host_slc0host_tx_start_int_ena",
-                &format_args!("{}", self.host_slc0host_tx_start_int_ena().bit()),
-            )
-            .field(
-                "host_slc0_rx_udf_int_ena",
-                &format_args!("{}", self.host_slc0_rx_udf_int_ena().bit()),
-            )
-            .field(
-                "host_slc0_tx_ovf_int_ena",
-                &format_args!("{}", self.host_slc0_tx_ovf_int_ena().bit()),
+                &self.host_slc0host_tx_start_int_ena(),
             )
+            .field("host_slc0_rx_udf_int_ena", &self.host_slc0_rx_udf_int_ena())
+            .field("host_slc0_tx_ovf_int_ena", &self.host_slc0_tx_ovf_int_ena())
             .field(
                 "host_slc0_rx_pf_valid_int_ena",
-                &format_args!("{}", self.host_slc0_rx_pf_valid_int_ena().bit()),
+                &self.host_slc0_rx_pf_valid_int_ena(),
             )
             .field(
                 "host_slc0_ext_bit0_int_ena",
-                &format_args!("{}", self.host_slc0_ext_bit0_int_ena().bit()),
+                &self.host_slc0_ext_bit0_int_ena(),
             )
             .field(
                 "host_slc0_ext_bit1_int_ena",
-                &format_args!("{}", self.host_slc0_ext_bit1_int_ena().bit()),
+                &self.host_slc0_ext_bit1_int_ena(),
             )
             .field(
                 "host_slc0_ext_bit2_int_ena",
-                &format_args!("{}", self.host_slc0_ext_bit2_int_ena().bit()),
+                &self.host_slc0_ext_bit2_int_ena(),
             )
             .field(
                 "host_slc0_ext_bit3_int_ena",
-                &format_args!("{}", self.host_slc0_ext_bit3_int_ena().bit()),
+                &self.host_slc0_ext_bit3_int_ena(),
             )
             .field(
                 "host_slc0_rx_new_packet_int_ena",
-                &format_args!("{}", self.host_slc0_rx_new_packet_int_ena().bit()),
+                &self.host_slc0_rx_new_packet_int_ena(),
             )
             .field(
                 "host_slc0_host_rd_retry_int_ena",
-                &format_args!("{}", self.host_slc0_host_rd_retry_int_ena().bit()),
-            )
-            .field(
-                "host_gpio_sdio_int_ena",
-                &format_args!("{}", self.host_gpio_sdio_int_ena().bit()),
+                &self.host_slc0_host_rd_retry_int_ena(),
             )
+            .field("host_gpio_sdio_int_ena", &self.host_gpio_sdio_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC0HOST_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slc0host_int_ena1.rs b/esp32/src/slchost/host_slc0host_int_ena1.rs
index 6b2f69fb2f..b05b28df2c 100644
--- a/esp32/src/slchost/host_slc0host_int_ena1.rs
+++ b/esp32/src/slchost/host_slc0host_int_ena1.rs
@@ -244,117 +244,108 @@ impl core::fmt::Debug for R {
         f.debug_struct("HOST_SLC0HOST_INT_ENA1")
             .field(
                 "host_slc0_tohost_bit0_int_ena1",
-                &format_args!("{}", self.host_slc0_tohost_bit0_int_ena1().bit()),
+                &self.host_slc0_tohost_bit0_int_ena1(),
             )
             .field(
                 "host_slc0_tohost_bit1_int_ena1",
-                &format_args!("{}", self.host_slc0_tohost_bit1_int_ena1().bit()),
+                &self.host_slc0_tohost_bit1_int_ena1(),
             )
             .field(
                 "host_slc0_tohost_bit2_int_ena1",
-                &format_args!("{}", self.host_slc0_tohost_bit2_int_ena1().bit()),
+                &self.host_slc0_tohost_bit2_int_ena1(),
             )
             .field(
                 "host_slc0_tohost_bit3_int_ena1",
-                &format_args!("{}", self.host_slc0_tohost_bit3_int_ena1().bit()),
+                &self.host_slc0_tohost_bit3_int_ena1(),
             )
             .field(
                 "host_slc0_tohost_bit4_int_ena1",
-                &format_args!("{}", self.host_slc0_tohost_bit4_int_ena1().bit()),
+                &self.host_slc0_tohost_bit4_int_ena1(),
             )
             .field(
                 "host_slc0_tohost_bit5_int_ena1",
-                &format_args!("{}", self.host_slc0_tohost_bit5_int_ena1().bit()),
+                &self.host_slc0_tohost_bit5_int_ena1(),
             )
             .field(
                 "host_slc0_tohost_bit6_int_ena1",
-                &format_args!("{}", self.host_slc0_tohost_bit6_int_ena1().bit()),
+                &self.host_slc0_tohost_bit6_int_ena1(),
             )
             .field(
                 "host_slc0_tohost_bit7_int_ena1",
-                &format_args!("{}", self.host_slc0_tohost_bit7_int_ena1().bit()),
+                &self.host_slc0_tohost_bit7_int_ena1(),
             )
             .field(
                 "host_slc0_token0_1to0_int_ena1",
-                &format_args!("{}", self.host_slc0_token0_1to0_int_ena1().bit()),
+                &self.host_slc0_token0_1to0_int_ena1(),
             )
             .field(
                 "host_slc0_token1_1to0_int_ena1",
-                &format_args!("{}", self.host_slc0_token1_1to0_int_ena1().bit()),
+                &self.host_slc0_token1_1to0_int_ena1(),
             )
             .field(
                 "host_slc0_token0_0to1_int_ena1",
-                &format_args!("{}", self.host_slc0_token0_0to1_int_ena1().bit()),
+                &self.host_slc0_token0_0to1_int_ena1(),
             )
             .field(
                 "host_slc0_token1_0to1_int_ena1",
-                &format_args!("{}", self.host_slc0_token1_0to1_int_ena1().bit()),
+                &self.host_slc0_token1_0to1_int_ena1(),
             )
             .field(
                 "host_slc0host_rx_sof_int_ena1",
-                &format_args!("{}", self.host_slc0host_rx_sof_int_ena1().bit()),
+                &self.host_slc0host_rx_sof_int_ena1(),
             )
             .field(
                 "host_slc0host_rx_eof_int_ena1",
-                &format_args!("{}", self.host_slc0host_rx_eof_int_ena1().bit()),
+                &self.host_slc0host_rx_eof_int_ena1(),
             )
             .field(
                 "host_slc0host_rx_start_int_ena1",
-                &format_args!("{}", self.host_slc0host_rx_start_int_ena1().bit()),
+                &self.host_slc0host_rx_start_int_ena1(),
             )
             .field(
                 "host_slc0host_tx_start_int_ena1",
-                &format_args!("{}", self.host_slc0host_tx_start_int_ena1().bit()),
+                &self.host_slc0host_tx_start_int_ena1(),
             )
             .field(
                 "host_slc0_rx_udf_int_ena1",
-                &format_args!("{}", self.host_slc0_rx_udf_int_ena1().bit()),
+                &self.host_slc0_rx_udf_int_ena1(),
             )
             .field(
                 "host_slc0_tx_ovf_int_ena1",
-                &format_args!("{}", self.host_slc0_tx_ovf_int_ena1().bit()),
+                &self.host_slc0_tx_ovf_int_ena1(),
             )
             .field(
                 "host_slc0_rx_pf_valid_int_ena1",
-                &format_args!("{}", self.host_slc0_rx_pf_valid_int_ena1().bit()),
+                &self.host_slc0_rx_pf_valid_int_ena1(),
             )
             .field(
                 "host_slc0_ext_bit0_int_ena1",
-                &format_args!("{}", self.host_slc0_ext_bit0_int_ena1().bit()),
+                &self.host_slc0_ext_bit0_int_ena1(),
             )
             .field(
                 "host_slc0_ext_bit1_int_ena1",
-                &format_args!("{}", self.host_slc0_ext_bit1_int_ena1().bit()),
+                &self.host_slc0_ext_bit1_int_ena1(),
             )
             .field(
                 "host_slc0_ext_bit2_int_ena1",
-                &format_args!("{}", self.host_slc0_ext_bit2_int_ena1().bit()),
+                &self.host_slc0_ext_bit2_int_ena1(),
             )
             .field(
                 "host_slc0_ext_bit3_int_ena1",
-                &format_args!("{}", self.host_slc0_ext_bit3_int_ena1().bit()),
+                &self.host_slc0_ext_bit3_int_ena1(),
             )
             .field(
                 "host_slc0_rx_new_packet_int_ena1",
-                &format_args!("{}", self.host_slc0_rx_new_packet_int_ena1().bit()),
+                &self.host_slc0_rx_new_packet_int_ena1(),
             )
             .field(
                 "host_slc0_host_rd_retry_int_ena1",
-                &format_args!("{}", self.host_slc0_host_rd_retry_int_ena1().bit()),
-            )
-            .field(
-                "host_gpio_sdio_int_ena1",
-                &format_args!("{}", self.host_gpio_sdio_int_ena1().bit()),
+                &self.host_slc0_host_rd_retry_int_ena1(),
             )
+            .field("host_gpio_sdio_int_ena1", &self.host_gpio_sdio_int_ena1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC0HOST_INT_ENA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slc0host_int_raw.rs b/esp32/src/slchost/host_slc0host_int_raw.rs
index d26be4c8c5..6cc52a08c8 100644
--- a/esp32/src/slchost/host_slc0host_int_raw.rs
+++ b/esp32/src/slchost/host_slc0host_int_raw.rs
@@ -190,117 +190,102 @@ impl core::fmt::Debug for R {
         f.debug_struct("HOST_SLC0HOST_INT_RAW")
             .field(
                 "host_slc0_tohost_bit0_int_raw",
-                &format_args!("{}", self.host_slc0_tohost_bit0_int_raw().bit()),
+                &self.host_slc0_tohost_bit0_int_raw(),
             )
             .field(
                 "host_slc0_tohost_bit1_int_raw",
-                &format_args!("{}", self.host_slc0_tohost_bit1_int_raw().bit()),
+                &self.host_slc0_tohost_bit1_int_raw(),
             )
             .field(
                 "host_slc0_tohost_bit2_int_raw",
-                &format_args!("{}", self.host_slc0_tohost_bit2_int_raw().bit()),
+                &self.host_slc0_tohost_bit2_int_raw(),
             )
             .field(
                 "host_slc0_tohost_bit3_int_raw",
-                &format_args!("{}", self.host_slc0_tohost_bit3_int_raw().bit()),
+                &self.host_slc0_tohost_bit3_int_raw(),
             )
             .field(
                 "host_slc0_tohost_bit4_int_raw",
-                &format_args!("{}", self.host_slc0_tohost_bit4_int_raw().bit()),
+                &self.host_slc0_tohost_bit4_int_raw(),
             )
             .field(
                 "host_slc0_tohost_bit5_int_raw",
-                &format_args!("{}", self.host_slc0_tohost_bit5_int_raw().bit()),
+                &self.host_slc0_tohost_bit5_int_raw(),
             )
             .field(
                 "host_slc0_tohost_bit6_int_raw",
-                &format_args!("{}", self.host_slc0_tohost_bit6_int_raw().bit()),
+                &self.host_slc0_tohost_bit6_int_raw(),
             )
             .field(
                 "host_slc0_tohost_bit7_int_raw",
-                &format_args!("{}", self.host_slc0_tohost_bit7_int_raw().bit()),
+                &self.host_slc0_tohost_bit7_int_raw(),
             )
             .field(
                 "host_slc0_token0_1to0_int_raw",
-                &format_args!("{}", self.host_slc0_token0_1to0_int_raw().bit()),
+                &self.host_slc0_token0_1to0_int_raw(),
             )
             .field(
                 "host_slc0_token1_1to0_int_raw",
-                &format_args!("{}", self.host_slc0_token1_1to0_int_raw().bit()),
+                &self.host_slc0_token1_1to0_int_raw(),
             )
             .field(
                 "host_slc0_token0_0to1_int_raw",
-                &format_args!("{}", self.host_slc0_token0_0to1_int_raw().bit()),
+                &self.host_slc0_token0_0to1_int_raw(),
             )
             .field(
                 "host_slc0_token1_0to1_int_raw",
-                &format_args!("{}", self.host_slc0_token1_0to1_int_raw().bit()),
+                &self.host_slc0_token1_0to1_int_raw(),
             )
             .field(
                 "host_slc0host_rx_sof_int_raw",
-                &format_args!("{}", self.host_slc0host_rx_sof_int_raw().bit()),
+                &self.host_slc0host_rx_sof_int_raw(),
             )
             .field(
                 "host_slc0host_rx_eof_int_raw",
-                &format_args!("{}", self.host_slc0host_rx_eof_int_raw().bit()),
+                &self.host_slc0host_rx_eof_int_raw(),
             )
             .field(
                 "host_slc0host_rx_start_int_raw",
-                &format_args!("{}", self.host_slc0host_rx_start_int_raw().bit()),
+                &self.host_slc0host_rx_start_int_raw(),
             )
             .field(
                 "host_slc0host_tx_start_int_raw",
-                &format_args!("{}", self.host_slc0host_tx_start_int_raw().bit()),
-            )
-            .field(
-                "host_slc0_rx_udf_int_raw",
-                &format_args!("{}", self.host_slc0_rx_udf_int_raw().bit()),
-            )
-            .field(
-                "host_slc0_tx_ovf_int_raw",
-                &format_args!("{}", self.host_slc0_tx_ovf_int_raw().bit()),
+                &self.host_slc0host_tx_start_int_raw(),
             )
+            .field("host_slc0_rx_udf_int_raw", &self.host_slc0_rx_udf_int_raw())
+            .field("host_slc0_tx_ovf_int_raw", &self.host_slc0_tx_ovf_int_raw())
             .field(
                 "host_slc0_rx_pf_valid_int_raw",
-                &format_args!("{}", self.host_slc0_rx_pf_valid_int_raw().bit()),
+                &self.host_slc0_rx_pf_valid_int_raw(),
             )
             .field(
                 "host_slc0_ext_bit0_int_raw",
-                &format_args!("{}", self.host_slc0_ext_bit0_int_raw().bit()),
+                &self.host_slc0_ext_bit0_int_raw(),
             )
             .field(
                 "host_slc0_ext_bit1_int_raw",
-                &format_args!("{}", self.host_slc0_ext_bit1_int_raw().bit()),
+                &self.host_slc0_ext_bit1_int_raw(),
             )
             .field(
                 "host_slc0_ext_bit2_int_raw",
-                &format_args!("{}", self.host_slc0_ext_bit2_int_raw().bit()),
+                &self.host_slc0_ext_bit2_int_raw(),
             )
             .field(
                 "host_slc0_ext_bit3_int_raw",
-                &format_args!("{}", self.host_slc0_ext_bit3_int_raw().bit()),
+                &self.host_slc0_ext_bit3_int_raw(),
             )
             .field(
                 "host_slc0_rx_new_packet_int_raw",
-                &format_args!("{}", self.host_slc0_rx_new_packet_int_raw().bit()),
+                &self.host_slc0_rx_new_packet_int_raw(),
             )
             .field(
                 "host_slc0_host_rd_retry_int_raw",
-                &format_args!("{}", self.host_slc0_host_rd_retry_int_raw().bit()),
-            )
-            .field(
-                "host_gpio_sdio_int_raw",
-                &format_args!("{}", self.host_gpio_sdio_int_raw().bit()),
+                &self.host_slc0_host_rd_retry_int_raw(),
             )
+            .field("host_gpio_sdio_int_raw", &self.host_gpio_sdio_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC0HOST_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slc0host_int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLC0HOST_INT_RAW_SPEC;
 impl crate::RegisterSpec for HOST_SLC0HOST_INT_RAW_SPEC {
diff --git a/esp32/src/slchost/host_slc0host_int_st.rs b/esp32/src/slchost/host_slc0host_int_st.rs
index 5b8176f68f..ab5d267f39 100644
--- a/esp32/src/slchost/host_slc0host_int_st.rs
+++ b/esp32/src/slchost/host_slc0host_int_st.rs
@@ -190,117 +190,102 @@ impl core::fmt::Debug for R {
         f.debug_struct("HOST_SLC0HOST_INT_ST")
             .field(
                 "host_slc0_tohost_bit0_int_st",
-                &format_args!("{}", self.host_slc0_tohost_bit0_int_st().bit()),
+                &self.host_slc0_tohost_bit0_int_st(),
             )
             .field(
                 "host_slc0_tohost_bit1_int_st",
-                &format_args!("{}", self.host_slc0_tohost_bit1_int_st().bit()),
+                &self.host_slc0_tohost_bit1_int_st(),
             )
             .field(
                 "host_slc0_tohost_bit2_int_st",
-                &format_args!("{}", self.host_slc0_tohost_bit2_int_st().bit()),
+                &self.host_slc0_tohost_bit2_int_st(),
             )
             .field(
                 "host_slc0_tohost_bit3_int_st",
-                &format_args!("{}", self.host_slc0_tohost_bit3_int_st().bit()),
+                &self.host_slc0_tohost_bit3_int_st(),
             )
             .field(
                 "host_slc0_tohost_bit4_int_st",
-                &format_args!("{}", self.host_slc0_tohost_bit4_int_st().bit()),
+                &self.host_slc0_tohost_bit4_int_st(),
             )
             .field(
                 "host_slc0_tohost_bit5_int_st",
-                &format_args!("{}", self.host_slc0_tohost_bit5_int_st().bit()),
+                &self.host_slc0_tohost_bit5_int_st(),
             )
             .field(
                 "host_slc0_tohost_bit6_int_st",
-                &format_args!("{}", self.host_slc0_tohost_bit6_int_st().bit()),
+                &self.host_slc0_tohost_bit6_int_st(),
             )
             .field(
                 "host_slc0_tohost_bit7_int_st",
-                &format_args!("{}", self.host_slc0_tohost_bit7_int_st().bit()),
+                &self.host_slc0_tohost_bit7_int_st(),
             )
             .field(
                 "host_slc0_token0_1to0_int_st",
-                &format_args!("{}", self.host_slc0_token0_1to0_int_st().bit()),
+                &self.host_slc0_token0_1to0_int_st(),
             )
             .field(
                 "host_slc0_token1_1to0_int_st",
-                &format_args!("{}", self.host_slc0_token1_1to0_int_st().bit()),
+                &self.host_slc0_token1_1to0_int_st(),
             )
             .field(
                 "host_slc0_token0_0to1_int_st",
-                &format_args!("{}", self.host_slc0_token0_0to1_int_st().bit()),
+                &self.host_slc0_token0_0to1_int_st(),
             )
             .field(
                 "host_slc0_token1_0to1_int_st",
-                &format_args!("{}", self.host_slc0_token1_0to1_int_st().bit()),
+                &self.host_slc0_token1_0to1_int_st(),
             )
             .field(
                 "host_slc0host_rx_sof_int_st",
-                &format_args!("{}", self.host_slc0host_rx_sof_int_st().bit()),
+                &self.host_slc0host_rx_sof_int_st(),
             )
             .field(
                 "host_slc0host_rx_eof_int_st",
-                &format_args!("{}", self.host_slc0host_rx_eof_int_st().bit()),
+                &self.host_slc0host_rx_eof_int_st(),
             )
             .field(
                 "host_slc0host_rx_start_int_st",
-                &format_args!("{}", self.host_slc0host_rx_start_int_st().bit()),
+                &self.host_slc0host_rx_start_int_st(),
             )
             .field(
                 "host_slc0host_tx_start_int_st",
-                &format_args!("{}", self.host_slc0host_tx_start_int_st().bit()),
-            )
-            .field(
-                "host_slc0_rx_udf_int_st",
-                &format_args!("{}", self.host_slc0_rx_udf_int_st().bit()),
-            )
-            .field(
-                "host_slc0_tx_ovf_int_st",
-                &format_args!("{}", self.host_slc0_tx_ovf_int_st().bit()),
+                &self.host_slc0host_tx_start_int_st(),
             )
+            .field("host_slc0_rx_udf_int_st", &self.host_slc0_rx_udf_int_st())
+            .field("host_slc0_tx_ovf_int_st", &self.host_slc0_tx_ovf_int_st())
             .field(
                 "host_slc0_rx_pf_valid_int_st",
-                &format_args!("{}", self.host_slc0_rx_pf_valid_int_st().bit()),
+                &self.host_slc0_rx_pf_valid_int_st(),
             )
             .field(
                 "host_slc0_ext_bit0_int_st",
-                &format_args!("{}", self.host_slc0_ext_bit0_int_st().bit()),
+                &self.host_slc0_ext_bit0_int_st(),
             )
             .field(
                 "host_slc0_ext_bit1_int_st",
-                &format_args!("{}", self.host_slc0_ext_bit1_int_st().bit()),
+                &self.host_slc0_ext_bit1_int_st(),
             )
             .field(
                 "host_slc0_ext_bit2_int_st",
-                &format_args!("{}", self.host_slc0_ext_bit2_int_st().bit()),
+                &self.host_slc0_ext_bit2_int_st(),
             )
             .field(
                 "host_slc0_ext_bit3_int_st",
-                &format_args!("{}", self.host_slc0_ext_bit3_int_st().bit()),
+                &self.host_slc0_ext_bit3_int_st(),
             )
             .field(
                 "host_slc0_rx_new_packet_int_st",
-                &format_args!("{}", self.host_slc0_rx_new_packet_int_st().bit()),
+                &self.host_slc0_rx_new_packet_int_st(),
             )
             .field(
                 "host_slc0_host_rd_retry_int_st",
-                &format_args!("{}", self.host_slc0_host_rd_retry_int_st().bit()),
-            )
-            .field(
-                "host_gpio_sdio_int_st",
-                &format_args!("{}", self.host_gpio_sdio_int_st().bit()),
+                &self.host_slc0_host_rd_retry_int_st(),
             )
+            .field("host_gpio_sdio_int_st", &self.host_gpio_sdio_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC0HOST_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slc0host_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLC0HOST_INT_ST_SPEC;
 impl crate::RegisterSpec for HOST_SLC0HOST_INT_ST_SPEC {
diff --git a/esp32/src/slchost/host_slc0host_len_wd.rs b/esp32/src/slchost/host_slc0host_len_wd.rs
index 9c0f84e05f..ef0b675541 100644
--- a/esp32/src/slchost/host_slc0host_len_wd.rs
+++ b/esp32/src/slchost/host_slc0host_len_wd.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLC0HOST_LEN_WD")
-            .field(
-                "host_slc0host_len_wd",
-                &format_args!("{}", self.host_slc0host_len_wd().bits()),
-            )
+            .field("host_slc0host_len_wd", &self.host_slc0host_len_wd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC0HOST_LEN_WD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slc0host_rx_infor.rs b/esp32/src/slchost/host_slc0host_rx_infor.rs
index 71b6fc535d..bac32b1eb5 100644
--- a/esp32/src/slchost/host_slc0host_rx_infor.rs
+++ b/esp32/src/slchost/host_slc0host_rx_infor.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLC0HOST_RX_INFOR")
-            .field(
-                "host_slc0host_rx_infor",
-                &format_args!("{}", self.host_slc0host_rx_infor().bits()),
-            )
+            .field("host_slc0host_rx_infor", &self.host_slc0host_rx_infor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC0HOST_RX_INFOR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slc0host_token_rdata.rs b/esp32/src/slchost/host_slc0host_token_rdata.rs
index e2c9895d47..d404316ff0 100644
--- a/esp32/src/slchost/host_slc0host_token_rdata.rs
+++ b/esp32/src/slchost/host_slc0host_token_rdata.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLC0HOST_TOKEN_RDATA")
-            .field(
-                "host_slc0_token0",
-                &format_args!("{}", self.host_slc0_token0().bits()),
-            )
-            .field(
-                "host_slc0_rx_pf_valid",
-                &format_args!("{}", self.host_slc0_rx_pf_valid().bit()),
-            )
-            .field(
-                "host_hostslc0_token1",
-                &format_args!("{}", self.host_hostslc0_token1().bits()),
-            )
-            .field(
-                "host_slc0_rx_pf_eof",
-                &format_args!("{}", self.host_slc0_rx_pf_eof().bits()),
-            )
+            .field("host_slc0_token0", &self.host_slc0_token0())
+            .field("host_slc0_rx_pf_valid", &self.host_slc0_rx_pf_valid())
+            .field("host_hostslc0_token1", &self.host_hostslc0_token1())
+            .field("host_slc0_rx_pf_eof", &self.host_slc0_rx_pf_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC0HOST_TOKEN_RDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slc0host_token_rdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLC0HOST_TOKEN_RDATA_SPEC;
 impl crate::RegisterSpec for HOST_SLC0HOST_TOKEN_RDATA_SPEC {
diff --git a/esp32/src/slchost/host_slc0host_token_wdata.rs b/esp32/src/slchost/host_slc0host_token_wdata.rs
index d166cd1480..b9d25f4cb1 100644
--- a/esp32/src/slchost/host_slc0host_token_wdata.rs
+++ b/esp32/src/slchost/host_slc0host_token_wdata.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLC0HOST_TOKEN_WDATA")
-            .field(
-                "host_slc0host_token0_wd",
-                &format_args!("{}", self.host_slc0host_token0_wd().bits()),
-            )
-            .field(
-                "host_slc0host_token1_wd",
-                &format_args!("{}", self.host_slc0host_token1_wd().bits()),
-            )
+            .field("host_slc0host_token0_wd", &self.host_slc0host_token0_wd())
+            .field("host_slc0host_token1_wd", &self.host_slc0host_token1_wd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC0HOST_TOKEN_WDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slc1_host_pf.rs b/esp32/src/slchost/host_slc1_host_pf.rs
index 1864231c1c..88dd4cf15c 100644
--- a/esp32/src/slchost/host_slc1_host_pf.rs
+++ b/esp32/src/slchost/host_slc1_host_pf.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLC1_HOST_PF")
-            .field(
-                "host_slc1_pf_data",
-                &format_args!("{}", self.host_slc1_pf_data().bits()),
-            )
+            .field("host_slc1_pf_data", &self.host_slc1_pf_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC1_HOST_PF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slc1_host_pf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLC1_HOST_PF_SPEC;
 impl crate::RegisterSpec for HOST_SLC1_HOST_PF_SPEC {
diff --git a/esp32/src/slchost/host_slc1host_func1_int_ena.rs b/esp32/src/slchost/host_slc1host_func1_int_ena.rs
index a8d9219ccc..17847ee1ca 100644
--- a/esp32/src/slchost/host_slc1host_func1_int_ena.rs
+++ b/esp32/src/slchost/host_slc1host_func1_int_ena.rs
@@ -248,117 +248,111 @@ impl core::fmt::Debug for R {
         f.debug_struct("HOST_SLC1HOST_FUNC1_INT_ENA")
             .field(
                 "host_fn1_slc1_tohost_bit0_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_tohost_bit0_int_ena().bit()),
+                &self.host_fn1_slc1_tohost_bit0_int_ena(),
             )
             .field(
                 "host_fn1_slc1_tohost_bit1_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_tohost_bit1_int_ena().bit()),
+                &self.host_fn1_slc1_tohost_bit1_int_ena(),
             )
             .field(
                 "host_fn1_slc1_tohost_bit2_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_tohost_bit2_int_ena().bit()),
+                &self.host_fn1_slc1_tohost_bit2_int_ena(),
             )
             .field(
                 "host_fn1_slc1_tohost_bit3_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_tohost_bit3_int_ena().bit()),
+                &self.host_fn1_slc1_tohost_bit3_int_ena(),
             )
             .field(
                 "host_fn1_slc1_tohost_bit4_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_tohost_bit4_int_ena().bit()),
+                &self.host_fn1_slc1_tohost_bit4_int_ena(),
             )
             .field(
                 "host_fn1_slc1_tohost_bit5_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_tohost_bit5_int_ena().bit()),
+                &self.host_fn1_slc1_tohost_bit5_int_ena(),
             )
             .field(
                 "host_fn1_slc1_tohost_bit6_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_tohost_bit6_int_ena().bit()),
+                &self.host_fn1_slc1_tohost_bit6_int_ena(),
             )
             .field(
                 "host_fn1_slc1_tohost_bit7_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_tohost_bit7_int_ena().bit()),
+                &self.host_fn1_slc1_tohost_bit7_int_ena(),
             )
             .field(
                 "host_fn1_slc1_token0_1to0_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_token0_1to0_int_ena().bit()),
+                &self.host_fn1_slc1_token0_1to0_int_ena(),
             )
             .field(
                 "host_fn1_slc1_token1_1to0_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_token1_1to0_int_ena().bit()),
+                &self.host_fn1_slc1_token1_1to0_int_ena(),
             )
             .field(
                 "host_fn1_slc1_token0_0to1_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_token0_0to1_int_ena().bit()),
+                &self.host_fn1_slc1_token0_0to1_int_ena(),
             )
             .field(
                 "host_fn1_slc1_token1_0to1_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_token1_0to1_int_ena().bit()),
+                &self.host_fn1_slc1_token1_0to1_int_ena(),
             )
             .field(
                 "host_fn1_slc1host_rx_sof_int_ena",
-                &format_args!("{}", self.host_fn1_slc1host_rx_sof_int_ena().bit()),
+                &self.host_fn1_slc1host_rx_sof_int_ena(),
             )
             .field(
                 "host_fn1_slc1host_rx_eof_int_ena",
-                &format_args!("{}", self.host_fn1_slc1host_rx_eof_int_ena().bit()),
+                &self.host_fn1_slc1host_rx_eof_int_ena(),
             )
             .field(
                 "host_fn1_slc1host_rx_start_int_ena",
-                &format_args!("{}", self.host_fn1_slc1host_rx_start_int_ena().bit()),
+                &self.host_fn1_slc1host_rx_start_int_ena(),
             )
             .field(
                 "host_fn1_slc1host_tx_start_int_ena",
-                &format_args!("{}", self.host_fn1_slc1host_tx_start_int_ena().bit()),
+                &self.host_fn1_slc1host_tx_start_int_ena(),
             )
             .field(
                 "host_fn1_slc1_rx_udf_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_rx_udf_int_ena().bit()),
+                &self.host_fn1_slc1_rx_udf_int_ena(),
             )
             .field(
                 "host_fn1_slc1_tx_ovf_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_tx_ovf_int_ena().bit()),
+                &self.host_fn1_slc1_tx_ovf_int_ena(),
             )
             .field(
                 "host_fn1_slc1_rx_pf_valid_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_rx_pf_valid_int_ena().bit()),
+                &self.host_fn1_slc1_rx_pf_valid_int_ena(),
             )
             .field(
                 "host_fn1_slc1_ext_bit0_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_ext_bit0_int_ena().bit()),
+                &self.host_fn1_slc1_ext_bit0_int_ena(),
             )
             .field(
                 "host_fn1_slc1_ext_bit1_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_ext_bit1_int_ena().bit()),
+                &self.host_fn1_slc1_ext_bit1_int_ena(),
             )
             .field(
                 "host_fn1_slc1_ext_bit2_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_ext_bit2_int_ena().bit()),
+                &self.host_fn1_slc1_ext_bit2_int_ena(),
             )
             .field(
                 "host_fn1_slc1_ext_bit3_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_ext_bit3_int_ena().bit()),
+                &self.host_fn1_slc1_ext_bit3_int_ena(),
             )
             .field(
                 "host_fn1_slc1_wifi_rx_new_packet_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_wifi_rx_new_packet_int_ena().bit()),
+                &self.host_fn1_slc1_wifi_rx_new_packet_int_ena(),
             )
             .field(
                 "host_fn1_slc1_host_rd_retry_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_host_rd_retry_int_ena().bit()),
+                &self.host_fn1_slc1_host_rd_retry_int_ena(),
             )
             .field(
                 "host_fn1_slc1_bt_rx_new_packet_int_ena",
-                &format_args!("{}", self.host_fn1_slc1_bt_rx_new_packet_int_ena().bit()),
+                &self.host_fn1_slc1_bt_rx_new_packet_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC1HOST_FUNC1_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slc1host_func2_int_ena.rs b/esp32/src/slchost/host_slc1host_func2_int_ena.rs
index a9f237ce33..ff1b58659f 100644
--- a/esp32/src/slchost/host_slc1host_func2_int_ena.rs
+++ b/esp32/src/slchost/host_slc1host_func2_int_ena.rs
@@ -248,117 +248,111 @@ impl core::fmt::Debug for R {
         f.debug_struct("HOST_SLC1HOST_FUNC2_INT_ENA")
             .field(
                 "host_fn2_slc1_tohost_bit0_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_tohost_bit0_int_ena().bit()),
+                &self.host_fn2_slc1_tohost_bit0_int_ena(),
             )
             .field(
                 "host_fn2_slc1_tohost_bit1_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_tohost_bit1_int_ena().bit()),
+                &self.host_fn2_slc1_tohost_bit1_int_ena(),
             )
             .field(
                 "host_fn2_slc1_tohost_bit2_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_tohost_bit2_int_ena().bit()),
+                &self.host_fn2_slc1_tohost_bit2_int_ena(),
             )
             .field(
                 "host_fn2_slc1_tohost_bit3_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_tohost_bit3_int_ena().bit()),
+                &self.host_fn2_slc1_tohost_bit3_int_ena(),
             )
             .field(
                 "host_fn2_slc1_tohost_bit4_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_tohost_bit4_int_ena().bit()),
+                &self.host_fn2_slc1_tohost_bit4_int_ena(),
             )
             .field(
                 "host_fn2_slc1_tohost_bit5_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_tohost_bit5_int_ena().bit()),
+                &self.host_fn2_slc1_tohost_bit5_int_ena(),
             )
             .field(
                 "host_fn2_slc1_tohost_bit6_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_tohost_bit6_int_ena().bit()),
+                &self.host_fn2_slc1_tohost_bit6_int_ena(),
             )
             .field(
                 "host_fn2_slc1_tohost_bit7_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_tohost_bit7_int_ena().bit()),
+                &self.host_fn2_slc1_tohost_bit7_int_ena(),
             )
             .field(
                 "host_fn2_slc1_token0_1to0_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_token0_1to0_int_ena().bit()),
+                &self.host_fn2_slc1_token0_1to0_int_ena(),
             )
             .field(
                 "host_fn2_slc1_token1_1to0_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_token1_1to0_int_ena().bit()),
+                &self.host_fn2_slc1_token1_1to0_int_ena(),
             )
             .field(
                 "host_fn2_slc1_token0_0to1_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_token0_0to1_int_ena().bit()),
+                &self.host_fn2_slc1_token0_0to1_int_ena(),
             )
             .field(
                 "host_fn2_slc1_token1_0to1_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_token1_0to1_int_ena().bit()),
+                &self.host_fn2_slc1_token1_0to1_int_ena(),
             )
             .field(
                 "host_fn2_slc1host_rx_sof_int_ena",
-                &format_args!("{}", self.host_fn2_slc1host_rx_sof_int_ena().bit()),
+                &self.host_fn2_slc1host_rx_sof_int_ena(),
             )
             .field(
                 "host_fn2_slc1host_rx_eof_int_ena",
-                &format_args!("{}", self.host_fn2_slc1host_rx_eof_int_ena().bit()),
+                &self.host_fn2_slc1host_rx_eof_int_ena(),
             )
             .field(
                 "host_fn2_slc1host_rx_start_int_ena",
-                &format_args!("{}", self.host_fn2_slc1host_rx_start_int_ena().bit()),
+                &self.host_fn2_slc1host_rx_start_int_ena(),
             )
             .field(
                 "host_fn2_slc1host_tx_start_int_ena",
-                &format_args!("{}", self.host_fn2_slc1host_tx_start_int_ena().bit()),
+                &self.host_fn2_slc1host_tx_start_int_ena(),
             )
             .field(
                 "host_fn2_slc1_rx_udf_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_rx_udf_int_ena().bit()),
+                &self.host_fn2_slc1_rx_udf_int_ena(),
             )
             .field(
                 "host_fn2_slc1_tx_ovf_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_tx_ovf_int_ena().bit()),
+                &self.host_fn2_slc1_tx_ovf_int_ena(),
             )
             .field(
                 "host_fn2_slc1_rx_pf_valid_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_rx_pf_valid_int_ena().bit()),
+                &self.host_fn2_slc1_rx_pf_valid_int_ena(),
             )
             .field(
                 "host_fn2_slc1_ext_bit0_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_ext_bit0_int_ena().bit()),
+                &self.host_fn2_slc1_ext_bit0_int_ena(),
             )
             .field(
                 "host_fn2_slc1_ext_bit1_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_ext_bit1_int_ena().bit()),
+                &self.host_fn2_slc1_ext_bit1_int_ena(),
             )
             .field(
                 "host_fn2_slc1_ext_bit2_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_ext_bit2_int_ena().bit()),
+                &self.host_fn2_slc1_ext_bit2_int_ena(),
             )
             .field(
                 "host_fn2_slc1_ext_bit3_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_ext_bit3_int_ena().bit()),
+                &self.host_fn2_slc1_ext_bit3_int_ena(),
             )
             .field(
                 "host_fn2_slc1_wifi_rx_new_packet_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_wifi_rx_new_packet_int_ena().bit()),
+                &self.host_fn2_slc1_wifi_rx_new_packet_int_ena(),
             )
             .field(
                 "host_fn2_slc1_host_rd_retry_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_host_rd_retry_int_ena().bit()),
+                &self.host_fn2_slc1_host_rd_retry_int_ena(),
             )
             .field(
                 "host_fn2_slc1_bt_rx_new_packet_int_ena",
-                &format_args!("{}", self.host_fn2_slc1_bt_rx_new_packet_int_ena().bit()),
+                &self.host_fn2_slc1_bt_rx_new_packet_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC1HOST_FUNC2_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slc1host_int_ena.rs b/esp32/src/slchost/host_slc1host_int_ena.rs
index 0c7e66f085..5a125580ad 100644
--- a/esp32/src/slchost/host_slc1host_int_ena.rs
+++ b/esp32/src/slchost/host_slc1host_int_ena.rs
@@ -244,117 +244,105 @@ impl core::fmt::Debug for R {
         f.debug_struct("HOST_SLC1HOST_INT_ENA")
             .field(
                 "host_slc1_tohost_bit0_int_ena",
-                &format_args!("{}", self.host_slc1_tohost_bit0_int_ena().bit()),
+                &self.host_slc1_tohost_bit0_int_ena(),
             )
             .field(
                 "host_slc1_tohost_bit1_int_ena",
-                &format_args!("{}", self.host_slc1_tohost_bit1_int_ena().bit()),
+                &self.host_slc1_tohost_bit1_int_ena(),
             )
             .field(
                 "host_slc1_tohost_bit2_int_ena",
-                &format_args!("{}", self.host_slc1_tohost_bit2_int_ena().bit()),
+                &self.host_slc1_tohost_bit2_int_ena(),
             )
             .field(
                 "host_slc1_tohost_bit3_int_ena",
-                &format_args!("{}", self.host_slc1_tohost_bit3_int_ena().bit()),
+                &self.host_slc1_tohost_bit3_int_ena(),
             )
             .field(
                 "host_slc1_tohost_bit4_int_ena",
-                &format_args!("{}", self.host_slc1_tohost_bit4_int_ena().bit()),
+                &self.host_slc1_tohost_bit4_int_ena(),
             )
             .field(
                 "host_slc1_tohost_bit5_int_ena",
-                &format_args!("{}", self.host_slc1_tohost_bit5_int_ena().bit()),
+                &self.host_slc1_tohost_bit5_int_ena(),
             )
             .field(
                 "host_slc1_tohost_bit6_int_ena",
-                &format_args!("{}", self.host_slc1_tohost_bit6_int_ena().bit()),
+                &self.host_slc1_tohost_bit6_int_ena(),
             )
             .field(
                 "host_slc1_tohost_bit7_int_ena",
-                &format_args!("{}", self.host_slc1_tohost_bit7_int_ena().bit()),
+                &self.host_slc1_tohost_bit7_int_ena(),
             )
             .field(
                 "host_slc1_token0_1to0_int_ena",
-                &format_args!("{}", self.host_slc1_token0_1to0_int_ena().bit()),
+                &self.host_slc1_token0_1to0_int_ena(),
             )
             .field(
                 "host_slc1_token1_1to0_int_ena",
-                &format_args!("{}", self.host_slc1_token1_1to0_int_ena().bit()),
+                &self.host_slc1_token1_1to0_int_ena(),
             )
             .field(
                 "host_slc1_token0_0to1_int_ena",
-                &format_args!("{}", self.host_slc1_token0_0to1_int_ena().bit()),
+                &self.host_slc1_token0_0to1_int_ena(),
             )
             .field(
                 "host_slc1_token1_0to1_int_ena",
-                &format_args!("{}", self.host_slc1_token1_0to1_int_ena().bit()),
+                &self.host_slc1_token1_0to1_int_ena(),
             )
             .field(
                 "host_slc1host_rx_sof_int_ena",
-                &format_args!("{}", self.host_slc1host_rx_sof_int_ena().bit()),
+                &self.host_slc1host_rx_sof_int_ena(),
             )
             .field(
                 "host_slc1host_rx_eof_int_ena",
-                &format_args!("{}", self.host_slc1host_rx_eof_int_ena().bit()),
+                &self.host_slc1host_rx_eof_int_ena(),
             )
             .field(
                 "host_slc1host_rx_start_int_ena",
-                &format_args!("{}", self.host_slc1host_rx_start_int_ena().bit()),
+                &self.host_slc1host_rx_start_int_ena(),
             )
             .field(
                 "host_slc1host_tx_start_int_ena",
-                &format_args!("{}", self.host_slc1host_tx_start_int_ena().bit()),
-            )
-            .field(
-                "host_slc1_rx_udf_int_ena",
-                &format_args!("{}", self.host_slc1_rx_udf_int_ena().bit()),
-            )
-            .field(
-                "host_slc1_tx_ovf_int_ena",
-                &format_args!("{}", self.host_slc1_tx_ovf_int_ena().bit()),
+                &self.host_slc1host_tx_start_int_ena(),
             )
+            .field("host_slc1_rx_udf_int_ena", &self.host_slc1_rx_udf_int_ena())
+            .field("host_slc1_tx_ovf_int_ena", &self.host_slc1_tx_ovf_int_ena())
             .field(
                 "host_slc1_rx_pf_valid_int_ena",
-                &format_args!("{}", self.host_slc1_rx_pf_valid_int_ena().bit()),
+                &self.host_slc1_rx_pf_valid_int_ena(),
             )
             .field(
                 "host_slc1_ext_bit0_int_ena",
-                &format_args!("{}", self.host_slc1_ext_bit0_int_ena().bit()),
+                &self.host_slc1_ext_bit0_int_ena(),
             )
             .field(
                 "host_slc1_ext_bit1_int_ena",
-                &format_args!("{}", self.host_slc1_ext_bit1_int_ena().bit()),
+                &self.host_slc1_ext_bit1_int_ena(),
             )
             .field(
                 "host_slc1_ext_bit2_int_ena",
-                &format_args!("{}", self.host_slc1_ext_bit2_int_ena().bit()),
+                &self.host_slc1_ext_bit2_int_ena(),
             )
             .field(
                 "host_slc1_ext_bit3_int_ena",
-                &format_args!("{}", self.host_slc1_ext_bit3_int_ena().bit()),
+                &self.host_slc1_ext_bit3_int_ena(),
             )
             .field(
                 "host_slc1_wifi_rx_new_packet_int_ena",
-                &format_args!("{}", self.host_slc1_wifi_rx_new_packet_int_ena().bit()),
+                &self.host_slc1_wifi_rx_new_packet_int_ena(),
             )
             .field(
                 "host_slc1_host_rd_retry_int_ena",
-                &format_args!("{}", self.host_slc1_host_rd_retry_int_ena().bit()),
+                &self.host_slc1_host_rd_retry_int_ena(),
             )
             .field(
                 "host_slc1_bt_rx_new_packet_int_ena",
-                &format_args!("{}", self.host_slc1_bt_rx_new_packet_int_ena().bit()),
+                &self.host_slc1_bt_rx_new_packet_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC1HOST_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slc1host_int_ena1.rs b/esp32/src/slchost/host_slc1host_int_ena1.rs
index 567482a634..dc5e13da2c 100644
--- a/esp32/src/slchost/host_slc1host_int_ena1.rs
+++ b/esp32/src/slchost/host_slc1host_int_ena1.rs
@@ -244,117 +244,111 @@ impl core::fmt::Debug for R {
         f.debug_struct("HOST_SLC1HOST_INT_ENA1")
             .field(
                 "host_slc1_tohost_bit0_int_ena1",
-                &format_args!("{}", self.host_slc1_tohost_bit0_int_ena1().bit()),
+                &self.host_slc1_tohost_bit0_int_ena1(),
             )
             .field(
                 "host_slc1_tohost_bit1_int_ena1",
-                &format_args!("{}", self.host_slc1_tohost_bit1_int_ena1().bit()),
+                &self.host_slc1_tohost_bit1_int_ena1(),
             )
             .field(
                 "host_slc1_tohost_bit2_int_ena1",
-                &format_args!("{}", self.host_slc1_tohost_bit2_int_ena1().bit()),
+                &self.host_slc1_tohost_bit2_int_ena1(),
             )
             .field(
                 "host_slc1_tohost_bit3_int_ena1",
-                &format_args!("{}", self.host_slc1_tohost_bit3_int_ena1().bit()),
+                &self.host_slc1_tohost_bit3_int_ena1(),
             )
             .field(
                 "host_slc1_tohost_bit4_int_ena1",
-                &format_args!("{}", self.host_slc1_tohost_bit4_int_ena1().bit()),
+                &self.host_slc1_tohost_bit4_int_ena1(),
             )
             .field(
                 "host_slc1_tohost_bit5_int_ena1",
-                &format_args!("{}", self.host_slc1_tohost_bit5_int_ena1().bit()),
+                &self.host_slc1_tohost_bit5_int_ena1(),
             )
             .field(
                 "host_slc1_tohost_bit6_int_ena1",
-                &format_args!("{}", self.host_slc1_tohost_bit6_int_ena1().bit()),
+                &self.host_slc1_tohost_bit6_int_ena1(),
             )
             .field(
                 "host_slc1_tohost_bit7_int_ena1",
-                &format_args!("{}", self.host_slc1_tohost_bit7_int_ena1().bit()),
+                &self.host_slc1_tohost_bit7_int_ena1(),
             )
             .field(
                 "host_slc1_token0_1to0_int_ena1",
-                &format_args!("{}", self.host_slc1_token0_1to0_int_ena1().bit()),
+                &self.host_slc1_token0_1to0_int_ena1(),
             )
             .field(
                 "host_slc1_token1_1to0_int_ena1",
-                &format_args!("{}", self.host_slc1_token1_1to0_int_ena1().bit()),
+                &self.host_slc1_token1_1to0_int_ena1(),
             )
             .field(
                 "host_slc1_token0_0to1_int_ena1",
-                &format_args!("{}", self.host_slc1_token0_0to1_int_ena1().bit()),
+                &self.host_slc1_token0_0to1_int_ena1(),
             )
             .field(
                 "host_slc1_token1_0to1_int_ena1",
-                &format_args!("{}", self.host_slc1_token1_0to1_int_ena1().bit()),
+                &self.host_slc1_token1_0to1_int_ena1(),
             )
             .field(
                 "host_slc1host_rx_sof_int_ena1",
-                &format_args!("{}", self.host_slc1host_rx_sof_int_ena1().bit()),
+                &self.host_slc1host_rx_sof_int_ena1(),
             )
             .field(
                 "host_slc1host_rx_eof_int_ena1",
-                &format_args!("{}", self.host_slc1host_rx_eof_int_ena1().bit()),
+                &self.host_slc1host_rx_eof_int_ena1(),
             )
             .field(
                 "host_slc1host_rx_start_int_ena1",
-                &format_args!("{}", self.host_slc1host_rx_start_int_ena1().bit()),
+                &self.host_slc1host_rx_start_int_ena1(),
             )
             .field(
                 "host_slc1host_tx_start_int_ena1",
-                &format_args!("{}", self.host_slc1host_tx_start_int_ena1().bit()),
+                &self.host_slc1host_tx_start_int_ena1(),
             )
             .field(
                 "host_slc1_rx_udf_int_ena1",
-                &format_args!("{}", self.host_slc1_rx_udf_int_ena1().bit()),
+                &self.host_slc1_rx_udf_int_ena1(),
             )
             .field(
                 "host_slc1_tx_ovf_int_ena1",
-                &format_args!("{}", self.host_slc1_tx_ovf_int_ena1().bit()),
+                &self.host_slc1_tx_ovf_int_ena1(),
             )
             .field(
                 "host_slc1_rx_pf_valid_int_ena1",
-                &format_args!("{}", self.host_slc1_rx_pf_valid_int_ena1().bit()),
+                &self.host_slc1_rx_pf_valid_int_ena1(),
             )
             .field(
                 "host_slc1_ext_bit0_int_ena1",
-                &format_args!("{}", self.host_slc1_ext_bit0_int_ena1().bit()),
+                &self.host_slc1_ext_bit0_int_ena1(),
             )
             .field(
                 "host_slc1_ext_bit1_int_ena1",
-                &format_args!("{}", self.host_slc1_ext_bit1_int_ena1().bit()),
+                &self.host_slc1_ext_bit1_int_ena1(),
             )
             .field(
                 "host_slc1_ext_bit2_int_ena1",
-                &format_args!("{}", self.host_slc1_ext_bit2_int_ena1().bit()),
+                &self.host_slc1_ext_bit2_int_ena1(),
             )
             .field(
                 "host_slc1_ext_bit3_int_ena1",
-                &format_args!("{}", self.host_slc1_ext_bit3_int_ena1().bit()),
+                &self.host_slc1_ext_bit3_int_ena1(),
             )
             .field(
                 "host_slc1_wifi_rx_new_packet_int_ena1",
-                &format_args!("{}", self.host_slc1_wifi_rx_new_packet_int_ena1().bit()),
+                &self.host_slc1_wifi_rx_new_packet_int_ena1(),
             )
             .field(
                 "host_slc1_host_rd_retry_int_ena1",
-                &format_args!("{}", self.host_slc1_host_rd_retry_int_ena1().bit()),
+                &self.host_slc1_host_rd_retry_int_ena1(),
             )
             .field(
                 "host_slc1_bt_rx_new_packet_int_ena1",
-                &format_args!("{}", self.host_slc1_bt_rx_new_packet_int_ena1().bit()),
+                &self.host_slc1_bt_rx_new_packet_int_ena1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC1HOST_INT_ENA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slc1host_int_raw.rs b/esp32/src/slchost/host_slc1host_int_raw.rs
index a4625bdbb8..f149070cfa 100644
--- a/esp32/src/slchost/host_slc1host_int_raw.rs
+++ b/esp32/src/slchost/host_slc1host_int_raw.rs
@@ -190,117 +190,105 @@ impl core::fmt::Debug for R {
         f.debug_struct("HOST_SLC1HOST_INT_RAW")
             .field(
                 "host_slc1_tohost_bit0_int_raw",
-                &format_args!("{}", self.host_slc1_tohost_bit0_int_raw().bit()),
+                &self.host_slc1_tohost_bit0_int_raw(),
             )
             .field(
                 "host_slc1_tohost_bit1_int_raw",
-                &format_args!("{}", self.host_slc1_tohost_bit1_int_raw().bit()),
+                &self.host_slc1_tohost_bit1_int_raw(),
             )
             .field(
                 "host_slc1_tohost_bit2_int_raw",
-                &format_args!("{}", self.host_slc1_tohost_bit2_int_raw().bit()),
+                &self.host_slc1_tohost_bit2_int_raw(),
             )
             .field(
                 "host_slc1_tohost_bit3_int_raw",
-                &format_args!("{}", self.host_slc1_tohost_bit3_int_raw().bit()),
+                &self.host_slc1_tohost_bit3_int_raw(),
             )
             .field(
                 "host_slc1_tohost_bit4_int_raw",
-                &format_args!("{}", self.host_slc1_tohost_bit4_int_raw().bit()),
+                &self.host_slc1_tohost_bit4_int_raw(),
             )
             .field(
                 "host_slc1_tohost_bit5_int_raw",
-                &format_args!("{}", self.host_slc1_tohost_bit5_int_raw().bit()),
+                &self.host_slc1_tohost_bit5_int_raw(),
             )
             .field(
                 "host_slc1_tohost_bit6_int_raw",
-                &format_args!("{}", self.host_slc1_tohost_bit6_int_raw().bit()),
+                &self.host_slc1_tohost_bit6_int_raw(),
             )
             .field(
                 "host_slc1_tohost_bit7_int_raw",
-                &format_args!("{}", self.host_slc1_tohost_bit7_int_raw().bit()),
+                &self.host_slc1_tohost_bit7_int_raw(),
             )
             .field(
                 "host_slc1_token0_1to0_int_raw",
-                &format_args!("{}", self.host_slc1_token0_1to0_int_raw().bit()),
+                &self.host_slc1_token0_1to0_int_raw(),
             )
             .field(
                 "host_slc1_token1_1to0_int_raw",
-                &format_args!("{}", self.host_slc1_token1_1to0_int_raw().bit()),
+                &self.host_slc1_token1_1to0_int_raw(),
             )
             .field(
                 "host_slc1_token0_0to1_int_raw",
-                &format_args!("{}", self.host_slc1_token0_0to1_int_raw().bit()),
+                &self.host_slc1_token0_0to1_int_raw(),
             )
             .field(
                 "host_slc1_token1_0to1_int_raw",
-                &format_args!("{}", self.host_slc1_token1_0to1_int_raw().bit()),
+                &self.host_slc1_token1_0to1_int_raw(),
             )
             .field(
                 "host_slc1host_rx_sof_int_raw",
-                &format_args!("{}", self.host_slc1host_rx_sof_int_raw().bit()),
+                &self.host_slc1host_rx_sof_int_raw(),
             )
             .field(
                 "host_slc1host_rx_eof_int_raw",
-                &format_args!("{}", self.host_slc1host_rx_eof_int_raw().bit()),
+                &self.host_slc1host_rx_eof_int_raw(),
             )
             .field(
                 "host_slc1host_rx_start_int_raw",
-                &format_args!("{}", self.host_slc1host_rx_start_int_raw().bit()),
+                &self.host_slc1host_rx_start_int_raw(),
             )
             .field(
                 "host_slc1host_tx_start_int_raw",
-                &format_args!("{}", self.host_slc1host_tx_start_int_raw().bit()),
-            )
-            .field(
-                "host_slc1_rx_udf_int_raw",
-                &format_args!("{}", self.host_slc1_rx_udf_int_raw().bit()),
-            )
-            .field(
-                "host_slc1_tx_ovf_int_raw",
-                &format_args!("{}", self.host_slc1_tx_ovf_int_raw().bit()),
+                &self.host_slc1host_tx_start_int_raw(),
             )
+            .field("host_slc1_rx_udf_int_raw", &self.host_slc1_rx_udf_int_raw())
+            .field("host_slc1_tx_ovf_int_raw", &self.host_slc1_tx_ovf_int_raw())
             .field(
                 "host_slc1_rx_pf_valid_int_raw",
-                &format_args!("{}", self.host_slc1_rx_pf_valid_int_raw().bit()),
+                &self.host_slc1_rx_pf_valid_int_raw(),
             )
             .field(
                 "host_slc1_ext_bit0_int_raw",
-                &format_args!("{}", self.host_slc1_ext_bit0_int_raw().bit()),
+                &self.host_slc1_ext_bit0_int_raw(),
             )
             .field(
                 "host_slc1_ext_bit1_int_raw",
-                &format_args!("{}", self.host_slc1_ext_bit1_int_raw().bit()),
+                &self.host_slc1_ext_bit1_int_raw(),
             )
             .field(
                 "host_slc1_ext_bit2_int_raw",
-                &format_args!("{}", self.host_slc1_ext_bit2_int_raw().bit()),
+                &self.host_slc1_ext_bit2_int_raw(),
             )
             .field(
                 "host_slc1_ext_bit3_int_raw",
-                &format_args!("{}", self.host_slc1_ext_bit3_int_raw().bit()),
+                &self.host_slc1_ext_bit3_int_raw(),
             )
             .field(
                 "host_slc1_wifi_rx_new_packet_int_raw",
-                &format_args!("{}", self.host_slc1_wifi_rx_new_packet_int_raw().bit()),
+                &self.host_slc1_wifi_rx_new_packet_int_raw(),
             )
             .field(
                 "host_slc1_host_rd_retry_int_raw",
-                &format_args!("{}", self.host_slc1_host_rd_retry_int_raw().bit()),
+                &self.host_slc1_host_rd_retry_int_raw(),
             )
             .field(
                 "host_slc1_bt_rx_new_packet_int_raw",
-                &format_args!("{}", self.host_slc1_bt_rx_new_packet_int_raw().bit()),
+                &self.host_slc1_bt_rx_new_packet_int_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC1HOST_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slc1host_int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLC1HOST_INT_RAW_SPEC;
 impl crate::RegisterSpec for HOST_SLC1HOST_INT_RAW_SPEC {
diff --git a/esp32/src/slchost/host_slc1host_int_st.rs b/esp32/src/slchost/host_slc1host_int_st.rs
index 0533905348..759ffeda1e 100644
--- a/esp32/src/slchost/host_slc1host_int_st.rs
+++ b/esp32/src/slchost/host_slc1host_int_st.rs
@@ -190,117 +190,105 @@ impl core::fmt::Debug for R {
         f.debug_struct("HOST_SLC1HOST_INT_ST")
             .field(
                 "host_slc1_tohost_bit0_int_st",
-                &format_args!("{}", self.host_slc1_tohost_bit0_int_st().bit()),
+                &self.host_slc1_tohost_bit0_int_st(),
             )
             .field(
                 "host_slc1_tohost_bit1_int_st",
-                &format_args!("{}", self.host_slc1_tohost_bit1_int_st().bit()),
+                &self.host_slc1_tohost_bit1_int_st(),
             )
             .field(
                 "host_slc1_tohost_bit2_int_st",
-                &format_args!("{}", self.host_slc1_tohost_bit2_int_st().bit()),
+                &self.host_slc1_tohost_bit2_int_st(),
             )
             .field(
                 "host_slc1_tohost_bit3_int_st",
-                &format_args!("{}", self.host_slc1_tohost_bit3_int_st().bit()),
+                &self.host_slc1_tohost_bit3_int_st(),
             )
             .field(
                 "host_slc1_tohost_bit4_int_st",
-                &format_args!("{}", self.host_slc1_tohost_bit4_int_st().bit()),
+                &self.host_slc1_tohost_bit4_int_st(),
             )
             .field(
                 "host_slc1_tohost_bit5_int_st",
-                &format_args!("{}", self.host_slc1_tohost_bit5_int_st().bit()),
+                &self.host_slc1_tohost_bit5_int_st(),
             )
             .field(
                 "host_slc1_tohost_bit6_int_st",
-                &format_args!("{}", self.host_slc1_tohost_bit6_int_st().bit()),
+                &self.host_slc1_tohost_bit6_int_st(),
             )
             .field(
                 "host_slc1_tohost_bit7_int_st",
-                &format_args!("{}", self.host_slc1_tohost_bit7_int_st().bit()),
+                &self.host_slc1_tohost_bit7_int_st(),
             )
             .field(
                 "host_slc1_token0_1to0_int_st",
-                &format_args!("{}", self.host_slc1_token0_1to0_int_st().bit()),
+                &self.host_slc1_token0_1to0_int_st(),
             )
             .field(
                 "host_slc1_token1_1to0_int_st",
-                &format_args!("{}", self.host_slc1_token1_1to0_int_st().bit()),
+                &self.host_slc1_token1_1to0_int_st(),
             )
             .field(
                 "host_slc1_token0_0to1_int_st",
-                &format_args!("{}", self.host_slc1_token0_0to1_int_st().bit()),
+                &self.host_slc1_token0_0to1_int_st(),
             )
             .field(
                 "host_slc1_token1_0to1_int_st",
-                &format_args!("{}", self.host_slc1_token1_0to1_int_st().bit()),
+                &self.host_slc1_token1_0to1_int_st(),
             )
             .field(
                 "host_slc1host_rx_sof_int_st",
-                &format_args!("{}", self.host_slc1host_rx_sof_int_st().bit()),
+                &self.host_slc1host_rx_sof_int_st(),
             )
             .field(
                 "host_slc1host_rx_eof_int_st",
-                &format_args!("{}", self.host_slc1host_rx_eof_int_st().bit()),
+                &self.host_slc1host_rx_eof_int_st(),
             )
             .field(
                 "host_slc1host_rx_start_int_st",
-                &format_args!("{}", self.host_slc1host_rx_start_int_st().bit()),
+                &self.host_slc1host_rx_start_int_st(),
             )
             .field(
                 "host_slc1host_tx_start_int_st",
-                &format_args!("{}", self.host_slc1host_tx_start_int_st().bit()),
-            )
-            .field(
-                "host_slc1_rx_udf_int_st",
-                &format_args!("{}", self.host_slc1_rx_udf_int_st().bit()),
-            )
-            .field(
-                "host_slc1_tx_ovf_int_st",
-                &format_args!("{}", self.host_slc1_tx_ovf_int_st().bit()),
+                &self.host_slc1host_tx_start_int_st(),
             )
+            .field("host_slc1_rx_udf_int_st", &self.host_slc1_rx_udf_int_st())
+            .field("host_slc1_tx_ovf_int_st", &self.host_slc1_tx_ovf_int_st())
             .field(
                 "host_slc1_rx_pf_valid_int_st",
-                &format_args!("{}", self.host_slc1_rx_pf_valid_int_st().bit()),
+                &self.host_slc1_rx_pf_valid_int_st(),
             )
             .field(
                 "host_slc1_ext_bit0_int_st",
-                &format_args!("{}", self.host_slc1_ext_bit0_int_st().bit()),
+                &self.host_slc1_ext_bit0_int_st(),
             )
             .field(
                 "host_slc1_ext_bit1_int_st",
-                &format_args!("{}", self.host_slc1_ext_bit1_int_st().bit()),
+                &self.host_slc1_ext_bit1_int_st(),
             )
             .field(
                 "host_slc1_ext_bit2_int_st",
-                &format_args!("{}", self.host_slc1_ext_bit2_int_st().bit()),
+                &self.host_slc1_ext_bit2_int_st(),
             )
             .field(
                 "host_slc1_ext_bit3_int_st",
-                &format_args!("{}", self.host_slc1_ext_bit3_int_st().bit()),
+                &self.host_slc1_ext_bit3_int_st(),
             )
             .field(
                 "host_slc1_wifi_rx_new_packet_int_st",
-                &format_args!("{}", self.host_slc1_wifi_rx_new_packet_int_st().bit()),
+                &self.host_slc1_wifi_rx_new_packet_int_st(),
             )
             .field(
                 "host_slc1_host_rd_retry_int_st",
-                &format_args!("{}", self.host_slc1_host_rd_retry_int_st().bit()),
+                &self.host_slc1_host_rd_retry_int_st(),
             )
             .field(
                 "host_slc1_bt_rx_new_packet_int_st",
-                &format_args!("{}", self.host_slc1_bt_rx_new_packet_int_st().bit()),
+                &self.host_slc1_bt_rx_new_packet_int_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC1HOST_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slc1host_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLC1HOST_INT_ST_SPEC;
 impl crate::RegisterSpec for HOST_SLC1HOST_INT_ST_SPEC {
diff --git a/esp32/src/slchost/host_slc1host_rx_infor.rs b/esp32/src/slchost/host_slc1host_rx_infor.rs
index d22a5bac91..281fc234f0 100644
--- a/esp32/src/slchost/host_slc1host_rx_infor.rs
+++ b/esp32/src/slchost/host_slc1host_rx_infor.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLC1HOST_RX_INFOR")
-            .field(
-                "host_slc1host_rx_infor",
-                &format_args!("{}", self.host_slc1host_rx_infor().bits()),
-            )
+            .field("host_slc1host_rx_infor", &self.host_slc1host_rx_infor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC1HOST_RX_INFOR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slc1host_token_rdata.rs b/esp32/src/slchost/host_slc1host_token_rdata.rs
index b04609b294..bb2ba30160 100644
--- a/esp32/src/slchost/host_slc1host_token_rdata.rs
+++ b/esp32/src/slchost/host_slc1host_token_rdata.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLC1HOST_TOKEN_RDATA")
-            .field(
-                "host_slc1_token0",
-                &format_args!("{}", self.host_slc1_token0().bits()),
-            )
-            .field(
-                "host_slc1_rx_pf_valid",
-                &format_args!("{}", self.host_slc1_rx_pf_valid().bit()),
-            )
-            .field(
-                "host_hostslc1_token1",
-                &format_args!("{}", self.host_hostslc1_token1().bits()),
-            )
-            .field(
-                "host_slc1_rx_pf_eof",
-                &format_args!("{}", self.host_slc1_rx_pf_eof().bits()),
-            )
+            .field("host_slc1_token0", &self.host_slc1_token0())
+            .field("host_slc1_rx_pf_valid", &self.host_slc1_rx_pf_valid())
+            .field("host_hostslc1_token1", &self.host_hostslc1_token1())
+            .field("host_slc1_rx_pf_eof", &self.host_slc1_rx_pf_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC1HOST_TOKEN_RDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slc1host_token_rdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLC1HOST_TOKEN_RDATA_SPEC;
 impl crate::RegisterSpec for HOST_SLC1HOST_TOKEN_RDATA_SPEC {
diff --git a/esp32/src/slchost/host_slc1host_token_wdata.rs b/esp32/src/slchost/host_slc1host_token_wdata.rs
index c97cd45b05..91158f1a82 100644
--- a/esp32/src/slchost/host_slc1host_token_wdata.rs
+++ b/esp32/src/slchost/host_slc1host_token_wdata.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLC1HOST_TOKEN_WDATA")
-            .field(
-                "host_slc1host_token0_wd",
-                &format_args!("{}", self.host_slc1host_token0_wd().bits()),
-            )
-            .field(
-                "host_slc1host_token1_wd",
-                &format_args!("{}", self.host_slc1host_token1_wd().bits()),
-            )
+            .field("host_slc1host_token0_wd", &self.host_slc1host_token0_wd())
+            .field("host_slc1host_token1_wd", &self.host_slc1host_token1_wd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC1HOST_TOKEN_WDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slc_apbwin_conf.rs b/esp32/src/slchost/host_slc_apbwin_conf.rs
index ffdb9511e8..cc5a1fdd03 100644
--- a/esp32/src/slchost/host_slc_apbwin_conf.rs
+++ b/esp32/src/slchost/host_slc_apbwin_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLC_APBWIN_CONF")
-            .field(
-                "host_slc_apbwin_addr",
-                &format_args!("{}", self.host_slc_apbwin_addr().bits()),
-            )
-            .field(
-                "host_slc_apbwin_wr",
-                &format_args!("{}", self.host_slc_apbwin_wr().bit()),
-            )
-            .field(
-                "host_slc_apbwin_start",
-                &format_args!("{}", self.host_slc_apbwin_start().bit()),
-            )
+            .field("host_slc_apbwin_addr", &self.host_slc_apbwin_addr())
+            .field("host_slc_apbwin_wr", &self.host_slc_apbwin_wr())
+            .field("host_slc_apbwin_start", &self.host_slc_apbwin_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC_APBWIN_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slc_apbwin_rdata.rs b/esp32/src/slchost/host_slc_apbwin_rdata.rs
index daaf79bd21..577b97c512 100644
--- a/esp32/src/slchost/host_slc_apbwin_rdata.rs
+++ b/esp32/src/slchost/host_slc_apbwin_rdata.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLC_APBWIN_RDATA")
-            .field(
-                "host_slc_apbwin_rdata",
-                &format_args!("{}", self.host_slc_apbwin_rdata().bits()),
-            )
+            .field("host_slc_apbwin_rdata", &self.host_slc_apbwin_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC_APBWIN_RDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slc_apbwin_rdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLC_APBWIN_RDATA_SPEC;
 impl crate::RegisterSpec for HOST_SLC_APBWIN_RDATA_SPEC {
diff --git a/esp32/src/slchost/host_slc_apbwin_wdata.rs b/esp32/src/slchost/host_slc_apbwin_wdata.rs
index 8f0fd10c02..e53bd526bf 100644
--- a/esp32/src/slchost/host_slc_apbwin_wdata.rs
+++ b/esp32/src/slchost/host_slc_apbwin_wdata.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLC_APBWIN_WDATA")
-            .field(
-                "host_slc_apbwin_wdata",
-                &format_args!("{}", self.host_slc_apbwin_wdata().bits()),
-            )
+            .field("host_slc_apbwin_wdata", &self.host_slc_apbwin_wdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLC_APBWIN_WDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_check_sum0.rs b/esp32/src/slchost/host_slchost_check_sum0.rs
index bab0178f0c..cba4616cb0 100644
--- a/esp32/src/slchost/host_slchost_check_sum0.rs
+++ b/esp32/src/slchost/host_slchost_check_sum0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CHECK_SUM0")
-            .field(
-                "host_slchost_check_sum0",
-                &format_args!("{}", self.host_slchost_check_sum0().bits()),
-            )
+            .field("host_slchost_check_sum0", &self.host_slchost_check_sum0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CHECK_SUM0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slchost_check_sum0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLCHOST_CHECK_SUM0_SPEC;
 impl crate::RegisterSpec for HOST_SLCHOST_CHECK_SUM0_SPEC {
diff --git a/esp32/src/slchost/host_slchost_check_sum1.rs b/esp32/src/slchost/host_slchost_check_sum1.rs
index ac86d35964..c10020c605 100644
--- a/esp32/src/slchost/host_slchost_check_sum1.rs
+++ b/esp32/src/slchost/host_slchost_check_sum1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CHECK_SUM1")
-            .field(
-                "host_slchost_check_sum1",
-                &format_args!("{}", self.host_slchost_check_sum1().bits()),
-            )
+            .field("host_slchost_check_sum1", &self.host_slchost_check_sum1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CHECK_SUM1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slchost_check_sum1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLCHOST_CHECK_SUM1_SPEC;
 impl crate::RegisterSpec for HOST_SLCHOST_CHECK_SUM1_SPEC {
diff --git a/esp32/src/slchost/host_slchost_conf.rs b/esp32/src/slchost/host_slchost_conf.rs
index 03e8f8cc73..867c73c427 100644
--- a/esp32/src/slchost/host_slchost_conf.rs
+++ b/esp32/src/slchost/host_slchost_conf.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF")
-            .field(
-                "host_frc_sdio11",
-                &format_args!("{}", self.host_frc_sdio11().bits()),
-            )
-            .field(
-                "host_frc_sdio20",
-                &format_args!("{}", self.host_frc_sdio20().bits()),
-            )
-            .field(
-                "host_frc_neg_samp",
-                &format_args!("{}", self.host_frc_neg_samp().bits()),
-            )
-            .field(
-                "host_frc_pos_samp",
-                &format_args!("{}", self.host_frc_pos_samp().bits()),
-            )
-            .field(
-                "host_frc_quick_in",
-                &format_args!("{}", self.host_frc_quick_in().bits()),
-            )
-            .field(
-                "host_sdio20_int_delay",
-                &format_args!("{}", self.host_sdio20_int_delay().bit()),
-            )
-            .field(
-                "host_sdio_pad_pullup",
-                &format_args!("{}", self.host_sdio_pad_pullup().bit()),
-            )
-            .field(
-                "host_hspeed_con_en",
-                &format_args!("{}", self.host_hspeed_con_en().bit()),
-            )
+            .field("host_frc_sdio11", &self.host_frc_sdio11())
+            .field("host_frc_sdio20", &self.host_frc_sdio20())
+            .field("host_frc_neg_samp", &self.host_frc_neg_samp())
+            .field("host_frc_pos_samp", &self.host_frc_pos_samp())
+            .field("host_frc_quick_in", &self.host_frc_quick_in())
+            .field("host_sdio20_int_delay", &self.host_sdio20_int_delay())
+            .field("host_sdio_pad_pullup", &self.host_sdio_pad_pullup())
+            .field("host_hspeed_con_en", &self.host_hspeed_con_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w0.rs b/esp32/src/slchost/host_slchost_conf_w0.rs
index cc423171b0..ef34d63264 100644
--- a/esp32/src/slchost/host_slchost_conf_w0.rs
+++ b/esp32/src/slchost/host_slchost_conf_w0.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W0")
-            .field(
-                "host_slchost_conf0",
-                &format_args!("{}", self.host_slchost_conf0().bits()),
-            )
-            .field(
-                "host_slchost_conf1",
-                &format_args!("{}", self.host_slchost_conf1().bits()),
-            )
-            .field(
-                "host_slchost_conf2",
-                &format_args!("{}", self.host_slchost_conf2().bits()),
-            )
-            .field(
-                "host_slchost_conf3",
-                &format_args!("{}", self.host_slchost_conf3().bits()),
-            )
+            .field("host_slchost_conf0", &self.host_slchost_conf0())
+            .field("host_slchost_conf1", &self.host_slchost_conf1())
+            .field("host_slchost_conf2", &self.host_slchost_conf2())
+            .field("host_slchost_conf3", &self.host_slchost_conf3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w1.rs b/esp32/src/slchost/host_slchost_conf_w1.rs
index f8063ee988..1a6945ea8e 100644
--- a/esp32/src/slchost/host_slchost_conf_w1.rs
+++ b/esp32/src/slchost/host_slchost_conf_w1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W1")
-            .field(
-                "host_slchost_conf4",
-                &format_args!("{}", self.host_slchost_conf4().bits()),
-            )
-            .field(
-                "host_slchost_conf5",
-                &format_args!("{}", self.host_slchost_conf5().bits()),
-            )
-            .field(
-                "host_slchost_conf6",
-                &format_args!("{}", self.host_slchost_conf6().bits()),
-            )
-            .field(
-                "host_slchost_conf7",
-                &format_args!("{}", self.host_slchost_conf7().bits()),
-            )
+            .field("host_slchost_conf4", &self.host_slchost_conf4())
+            .field("host_slchost_conf5", &self.host_slchost_conf5())
+            .field("host_slchost_conf6", &self.host_slchost_conf6())
+            .field("host_slchost_conf7", &self.host_slchost_conf7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w10.rs b/esp32/src/slchost/host_slchost_conf_w10.rs
index f12045c859..00434a0f75 100644
--- a/esp32/src/slchost/host_slchost_conf_w10.rs
+++ b/esp32/src/slchost/host_slchost_conf_w10.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W10")
-            .field(
-                "host_slchost_conf40",
-                &format_args!("{}", self.host_slchost_conf40().bits()),
-            )
-            .field(
-                "host_slchost_conf41",
-                &format_args!("{}", self.host_slchost_conf41().bits()),
-            )
-            .field(
-                "host_slchost_conf42",
-                &format_args!("{}", self.host_slchost_conf42().bits()),
-            )
-            .field(
-                "host_slchost_conf43",
-                &format_args!("{}", self.host_slchost_conf43().bits()),
-            )
+            .field("host_slchost_conf40", &self.host_slchost_conf40())
+            .field("host_slchost_conf41", &self.host_slchost_conf41())
+            .field("host_slchost_conf42", &self.host_slchost_conf42())
+            .field("host_slchost_conf43", &self.host_slchost_conf43())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w11.rs b/esp32/src/slchost/host_slchost_conf_w11.rs
index e1de3c2f46..5ffaf97f98 100644
--- a/esp32/src/slchost/host_slchost_conf_w11.rs
+++ b/esp32/src/slchost/host_slchost_conf_w11.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W11")
-            .field(
-                "host_slchost_conf44",
-                &format_args!("{}", self.host_slchost_conf44().bits()),
-            )
-            .field(
-                "host_slchost_conf45",
-                &format_args!("{}", self.host_slchost_conf45().bits()),
-            )
-            .field(
-                "host_slchost_conf46",
-                &format_args!("{}", self.host_slchost_conf46().bits()),
-            )
-            .field(
-                "host_slchost_conf47",
-                &format_args!("{}", self.host_slchost_conf47().bits()),
-            )
+            .field("host_slchost_conf44", &self.host_slchost_conf44())
+            .field("host_slchost_conf45", &self.host_slchost_conf45())
+            .field("host_slchost_conf46", &self.host_slchost_conf46())
+            .field("host_slchost_conf47", &self.host_slchost_conf47())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w12.rs b/esp32/src/slchost/host_slchost_conf_w12.rs
index 98c6966be7..d117b65e5b 100644
--- a/esp32/src/slchost/host_slchost_conf_w12.rs
+++ b/esp32/src/slchost/host_slchost_conf_w12.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W12")
-            .field(
-                "host_slchost_conf48",
-                &format_args!("{}", self.host_slchost_conf48().bits()),
-            )
-            .field(
-                "host_slchost_conf49",
-                &format_args!("{}", self.host_slchost_conf49().bits()),
-            )
-            .field(
-                "host_slchost_conf50",
-                &format_args!("{}", self.host_slchost_conf50().bits()),
-            )
-            .field(
-                "host_slchost_conf51",
-                &format_args!("{}", self.host_slchost_conf51().bits()),
-            )
+            .field("host_slchost_conf48", &self.host_slchost_conf48())
+            .field("host_slchost_conf49", &self.host_slchost_conf49())
+            .field("host_slchost_conf50", &self.host_slchost_conf50())
+            .field("host_slchost_conf51", &self.host_slchost_conf51())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w13.rs b/esp32/src/slchost/host_slchost_conf_w13.rs
index 654c979455..d8c5e71ff0 100644
--- a/esp32/src/slchost/host_slchost_conf_w13.rs
+++ b/esp32/src/slchost/host_slchost_conf_w13.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W13")
-            .field(
-                "host_slchost_conf52",
-                &format_args!("{}", self.host_slchost_conf52().bits()),
-            )
-            .field(
-                "host_slchost_conf53",
-                &format_args!("{}", self.host_slchost_conf53().bits()),
-            )
-            .field(
-                "host_slchost_conf54",
-                &format_args!("{}", self.host_slchost_conf54().bits()),
-            )
-            .field(
-                "host_slchost_conf55",
-                &format_args!("{}", self.host_slchost_conf55().bits()),
-            )
+            .field("host_slchost_conf52", &self.host_slchost_conf52())
+            .field("host_slchost_conf53", &self.host_slchost_conf53())
+            .field("host_slchost_conf54", &self.host_slchost_conf54())
+            .field("host_slchost_conf55", &self.host_slchost_conf55())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w14.rs b/esp32/src/slchost/host_slchost_conf_w14.rs
index b07849447e..e59179365d 100644
--- a/esp32/src/slchost/host_slchost_conf_w14.rs
+++ b/esp32/src/slchost/host_slchost_conf_w14.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W14")
-            .field(
-                "host_slchost_conf56",
-                &format_args!("{}", self.host_slchost_conf56().bits()),
-            )
-            .field(
-                "host_slchost_conf57",
-                &format_args!("{}", self.host_slchost_conf57().bits()),
-            )
-            .field(
-                "host_slchost_conf58",
-                &format_args!("{}", self.host_slchost_conf58().bits()),
-            )
-            .field(
-                "host_slchost_conf59",
-                &format_args!("{}", self.host_slchost_conf59().bits()),
-            )
+            .field("host_slchost_conf56", &self.host_slchost_conf56())
+            .field("host_slchost_conf57", &self.host_slchost_conf57())
+            .field("host_slchost_conf58", &self.host_slchost_conf58())
+            .field("host_slchost_conf59", &self.host_slchost_conf59())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w15.rs b/esp32/src/slchost/host_slchost_conf_w15.rs
index ff218ff490..19ac5c0ee2 100644
--- a/esp32/src/slchost/host_slchost_conf_w15.rs
+++ b/esp32/src/slchost/host_slchost_conf_w15.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W15")
-            .field(
-                "host_slchost_conf60",
-                &format_args!("{}", self.host_slchost_conf60().bits()),
-            )
-            .field(
-                "host_slchost_conf61",
-                &format_args!("{}", self.host_slchost_conf61().bits()),
-            )
-            .field(
-                "host_slchost_conf62",
-                &format_args!("{}", self.host_slchost_conf62().bits()),
-            )
-            .field(
-                "host_slchost_conf63",
-                &format_args!("{}", self.host_slchost_conf63().bits()),
-            )
+            .field("host_slchost_conf60", &self.host_slchost_conf60())
+            .field("host_slchost_conf61", &self.host_slchost_conf61())
+            .field("host_slchost_conf62", &self.host_slchost_conf62())
+            .field("host_slchost_conf63", &self.host_slchost_conf63())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w2.rs b/esp32/src/slchost/host_slchost_conf_w2.rs
index e78bb00b1e..63f6aec618 100644
--- a/esp32/src/slchost/host_slchost_conf_w2.rs
+++ b/esp32/src/slchost/host_slchost_conf_w2.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W2")
-            .field(
-                "host_slchost_conf8",
-                &format_args!("{}", self.host_slchost_conf8().bits()),
-            )
-            .field(
-                "host_slchost_conf9",
-                &format_args!("{}", self.host_slchost_conf9().bits()),
-            )
-            .field(
-                "host_slchost_conf10",
-                &format_args!("{}", self.host_slchost_conf10().bits()),
-            )
-            .field(
-                "host_slchost_conf11",
-                &format_args!("{}", self.host_slchost_conf11().bits()),
-            )
+            .field("host_slchost_conf8", &self.host_slchost_conf8())
+            .field("host_slchost_conf9", &self.host_slchost_conf9())
+            .field("host_slchost_conf10", &self.host_slchost_conf10())
+            .field("host_slchost_conf11", &self.host_slchost_conf11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w3.rs b/esp32/src/slchost/host_slchost_conf_w3.rs
index bd32a17c55..4efcee6294 100644
--- a/esp32/src/slchost/host_slchost_conf_w3.rs
+++ b/esp32/src/slchost/host_slchost_conf_w3.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W3")
-            .field(
-                "host_slchost_conf12",
-                &format_args!("{}", self.host_slchost_conf12().bits()),
-            )
-            .field(
-                "host_slchost_conf13",
-                &format_args!("{}", self.host_slchost_conf13().bits()),
-            )
-            .field(
-                "host_slchost_conf14",
-                &format_args!("{}", self.host_slchost_conf14().bits()),
-            )
-            .field(
-                "host_slchost_conf15",
-                &format_args!("{}", self.host_slchost_conf15().bits()),
-            )
+            .field("host_slchost_conf12", &self.host_slchost_conf12())
+            .field("host_slchost_conf13", &self.host_slchost_conf13())
+            .field("host_slchost_conf14", &self.host_slchost_conf14())
+            .field("host_slchost_conf15", &self.host_slchost_conf15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w4.rs b/esp32/src/slchost/host_slchost_conf_w4.rs
index e30069bda8..990e578202 100644
--- a/esp32/src/slchost/host_slchost_conf_w4.rs
+++ b/esp32/src/slchost/host_slchost_conf_w4.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W4")
-            .field(
-                "host_slchost_conf16",
-                &format_args!("{}", self.host_slchost_conf16().bits()),
-            )
-            .field(
-                "host_slchost_conf17",
-                &format_args!("{}", self.host_slchost_conf17().bits()),
-            )
-            .field(
-                "host_slchost_conf18",
-                &format_args!("{}", self.host_slchost_conf18().bits()),
-            )
-            .field(
-                "host_slchost_conf19",
-                &format_args!("{}", self.host_slchost_conf19().bits()),
-            )
+            .field("host_slchost_conf16", &self.host_slchost_conf16())
+            .field("host_slchost_conf17", &self.host_slchost_conf17())
+            .field("host_slchost_conf18", &self.host_slchost_conf18())
+            .field("host_slchost_conf19", &self.host_slchost_conf19())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - SLC timeout value"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w5.rs b/esp32/src/slchost/host_slchost_conf_w5.rs
index 5f4d5546a5..716199f039 100644
--- a/esp32/src/slchost/host_slchost_conf_w5.rs
+++ b/esp32/src/slchost/host_slchost_conf_w5.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W5")
-            .field(
-                "host_slchost_conf20",
-                &format_args!("{}", self.host_slchost_conf20().bits()),
-            )
-            .field(
-                "host_slchost_conf21",
-                &format_args!("{}", self.host_slchost_conf21().bits()),
-            )
-            .field(
-                "host_slchost_conf22",
-                &format_args!("{}", self.host_slchost_conf22().bits()),
-            )
-            .field(
-                "host_slchost_conf23",
-                &format_args!("{}", self.host_slchost_conf23().bits()),
-            )
+            .field("host_slchost_conf20", &self.host_slchost_conf20())
+            .field("host_slchost_conf21", &self.host_slchost_conf21())
+            .field("host_slchost_conf22", &self.host_slchost_conf22())
+            .field("host_slchost_conf23", &self.host_slchost_conf23())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w6.rs b/esp32/src/slchost/host_slchost_conf_w6.rs
index e4015b2ab7..d8bed12f10 100644
--- a/esp32/src/slchost/host_slchost_conf_w6.rs
+++ b/esp32/src/slchost/host_slchost_conf_w6.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W6")
-            .field(
-                "host_slchost_conf24",
-                &format_args!("{}", self.host_slchost_conf24().bits()),
-            )
-            .field(
-                "host_slchost_conf25",
-                &format_args!("{}", self.host_slchost_conf25().bits()),
-            )
-            .field(
-                "host_slchost_conf26",
-                &format_args!("{}", self.host_slchost_conf26().bits()),
-            )
-            .field(
-                "host_slchost_conf27",
-                &format_args!("{}", self.host_slchost_conf27().bits()),
-            )
+            .field("host_slchost_conf24", &self.host_slchost_conf24())
+            .field("host_slchost_conf25", &self.host_slchost_conf25())
+            .field("host_slchost_conf26", &self.host_slchost_conf26())
+            .field("host_slchost_conf27", &self.host_slchost_conf27())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w7.rs b/esp32/src/slchost/host_slchost_conf_w7.rs
index e71d358618..573d0fea79 100644
--- a/esp32/src/slchost/host_slchost_conf_w7.rs
+++ b/esp32/src/slchost/host_slchost_conf_w7.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W7")
-            .field(
-                "host_slchost_conf28",
-                &format_args!("{}", self.host_slchost_conf28().bits()),
-            )
-            .field(
-                "host_slchost_conf29",
-                &format_args!("{}", self.host_slchost_conf29().bits()),
-            )
-            .field(
-                "host_slchost_conf30",
-                &format_args!("{}", self.host_slchost_conf30().bits()),
-            )
-            .field(
-                "host_slchost_conf31",
-                &format_args!("{}", self.host_slchost_conf31().bits()),
-            )
+            .field("host_slchost_conf28", &self.host_slchost_conf28())
+            .field("host_slchost_conf29", &self.host_slchost_conf29())
+            .field("host_slchost_conf30", &self.host_slchost_conf30())
+            .field("host_slchost_conf31", &self.host_slchost_conf31())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w8.rs b/esp32/src/slchost/host_slchost_conf_w8.rs
index d22ee31114..c7fd679860 100644
--- a/esp32/src/slchost/host_slchost_conf_w8.rs
+++ b/esp32/src/slchost/host_slchost_conf_w8.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W8")
-            .field(
-                "host_slchost_conf32",
-                &format_args!("{}", self.host_slchost_conf32().bits()),
-            )
-            .field(
-                "host_slchost_conf33",
-                &format_args!("{}", self.host_slchost_conf33().bits()),
-            )
-            .field(
-                "host_slchost_conf34",
-                &format_args!("{}", self.host_slchost_conf34().bits()),
-            )
-            .field(
-                "host_slchost_conf35",
-                &format_args!("{}", self.host_slchost_conf35().bits()),
-            )
+            .field("host_slchost_conf32", &self.host_slchost_conf32())
+            .field("host_slchost_conf33", &self.host_slchost_conf33())
+            .field("host_slchost_conf34", &self.host_slchost_conf34())
+            .field("host_slchost_conf35", &self.host_slchost_conf35())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_conf_w9.rs b/esp32/src/slchost/host_slchost_conf_w9.rs
index 1d7abc5bac..f018cd6a69 100644
--- a/esp32/src/slchost/host_slchost_conf_w9.rs
+++ b/esp32/src/slchost/host_slchost_conf_w9.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_CONF_W9")
-            .field(
-                "host_slchost_conf36",
-                &format_args!("{}", self.host_slchost_conf36().bits()),
-            )
-            .field(
-                "host_slchost_conf37",
-                &format_args!("{}", self.host_slchost_conf37().bits()),
-            )
-            .field(
-                "host_slchost_conf38",
-                &format_args!("{}", self.host_slchost_conf38().bits()),
-            )
-            .field(
-                "host_slchost_conf39",
-                &format_args!("{}", self.host_slchost_conf39().bits()),
-            )
+            .field("host_slchost_conf36", &self.host_slchost_conf36())
+            .field("host_slchost_conf37", &self.host_slchost_conf37())
+            .field("host_slchost_conf38", &self.host_slchost_conf38())
+            .field("host_slchost_conf39", &self.host_slchost_conf39())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_CONF_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_func2_0.rs b/esp32/src/slchost/host_slchost_func2_0.rs
index 39b7fe1f3c..a304a97b97 100644
--- a/esp32/src/slchost/host_slchost_func2_0.rs
+++ b/esp32/src/slchost/host_slchost_func2_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_FUNC2_0")
-            .field(
-                "host_slc_func2_int",
-                &format_args!("{}", self.host_slc_func2_int().bit()),
-            )
+            .field("host_slc_func2_int", &self.host_slc_func2_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_FUNC2_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_func2_1.rs b/esp32/src/slchost/host_slchost_func2_1.rs
index 4698bff711..a6177aa394 100644
--- a/esp32/src/slchost/host_slchost_func2_1.rs
+++ b/esp32/src/slchost/host_slchost_func2_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_FUNC2_1")
-            .field(
-                "host_slc_func2_int_en",
-                &format_args!("{}", self.host_slc_func2_int_en().bit()),
-            )
+            .field("host_slc_func2_int_en", &self.host_slc_func2_int_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_FUNC2_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_func2_2.rs b/esp32/src/slchost/host_slchost_func2_2.rs
index f4c5a9fe47..aef095ece9 100644
--- a/esp32/src/slchost/host_slchost_func2_2.rs
+++ b/esp32/src/slchost/host_slchost_func2_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_FUNC2_2")
-            .field(
-                "host_slc_func1_mdstat",
-                &format_args!("{}", self.host_slc_func1_mdstat().bit()),
-            )
+            .field("host_slc_func1_mdstat", &self.host_slc_func1_mdstat())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_FUNC2_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_gpio_in0.rs b/esp32/src/slchost/host_slchost_gpio_in0.rs
index 6decd78486..9f29255bd5 100644
--- a/esp32/src/slchost/host_slchost_gpio_in0.rs
+++ b/esp32/src/slchost/host_slchost_gpio_in0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_GPIO_IN0")
-            .field(
-                "host_gpio_sdio_in0",
-                &format_args!("{}", self.host_gpio_sdio_in0().bits()),
-            )
+            .field("host_gpio_sdio_in0", &self.host_gpio_sdio_in0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_GPIO_IN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slchost_gpio_in0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLCHOST_GPIO_IN0_SPEC;
 impl crate::RegisterSpec for HOST_SLCHOST_GPIO_IN0_SPEC {
diff --git a/esp32/src/slchost/host_slchost_gpio_in1.rs b/esp32/src/slchost/host_slchost_gpio_in1.rs
index 33ecbcd3b4..61855bc79a 100644
--- a/esp32/src/slchost/host_slchost_gpio_in1.rs
+++ b/esp32/src/slchost/host_slchost_gpio_in1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_GPIO_IN1")
-            .field(
-                "host_gpio_sdio_in1",
-                &format_args!("{}", self.host_gpio_sdio_in1().bits()),
-            )
+            .field("host_gpio_sdio_in1", &self.host_gpio_sdio_in1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_GPIO_IN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slchost_gpio_in1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLCHOST_GPIO_IN1_SPEC;
 impl crate::RegisterSpec for HOST_SLCHOST_GPIO_IN1_SPEC {
diff --git a/esp32/src/slchost/host_slchost_gpio_status0.rs b/esp32/src/slchost/host_slchost_gpio_status0.rs
index 140e783082..9ac5105b36 100644
--- a/esp32/src/slchost/host_slchost_gpio_status0.rs
+++ b/esp32/src/slchost/host_slchost_gpio_status0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_GPIO_STATUS0")
-            .field(
-                "host_gpio_sdio_int0",
-                &format_args!("{}", self.host_gpio_sdio_int0().bits()),
-            )
+            .field("host_gpio_sdio_int0", &self.host_gpio_sdio_int0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_GPIO_STATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slchost_gpio_status0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLCHOST_GPIO_STATUS0_SPEC;
 impl crate::RegisterSpec for HOST_SLCHOST_GPIO_STATUS0_SPEC {
diff --git a/esp32/src/slchost/host_slchost_gpio_status1.rs b/esp32/src/slchost/host_slchost_gpio_status1.rs
index 941b6d827c..6346fe5316 100644
--- a/esp32/src/slchost/host_slchost_gpio_status1.rs
+++ b/esp32/src/slchost/host_slchost_gpio_status1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_GPIO_STATUS1")
-            .field(
-                "host_gpio_sdio_int1",
-                &format_args!("{}", self.host_gpio_sdio_int1().bits()),
-            )
+            .field("host_gpio_sdio_int1", &self.host_gpio_sdio_int1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_GPIO_STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slchost_gpio_status1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLCHOST_GPIO_STATUS1_SPEC;
 impl crate::RegisterSpec for HOST_SLCHOST_GPIO_STATUS1_SPEC {
diff --git a/esp32/src/slchost/host_slchost_inf_st.rs b/esp32/src/slchost/host_slchost_inf_st.rs
index 1e38b39fa8..fa5a0b3dfe 100644
--- a/esp32/src/slchost/host_slchost_inf_st.rs
+++ b/esp32/src/slchost/host_slchost_inf_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_INF_ST")
-            .field(
-                "host_sdio20_mode",
-                &format_args!("{}", self.host_sdio20_mode().bits()),
-            )
-            .field(
-                "host_sdio_neg_samp",
-                &format_args!("{}", self.host_sdio_neg_samp().bits()),
-            )
-            .field(
-                "host_sdio_quick_in",
-                &format_args!("{}", self.host_sdio_quick_in().bits()),
-            )
+            .field("host_sdio20_mode", &self.host_sdio20_mode())
+            .field("host_sdio_neg_samp", &self.host_sdio_neg_samp())
+            .field("host_sdio_quick_in", &self.host_sdio_quick_in())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_INF_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slchost_inf_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLCHOST_INF_ST_SPEC;
 impl crate::RegisterSpec for HOST_SLCHOST_INF_ST_SPEC {
diff --git a/esp32/src/slchost/host_slchost_pkt_len.rs b/esp32/src/slchost/host_slchost_pkt_len.rs
index 9d42500478..639ef33248 100644
--- a/esp32/src/slchost/host_slchost_pkt_len.rs
+++ b/esp32/src/slchost/host_slchost_pkt_len.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_PKT_LEN")
-            .field(
-                "host_hostslc0_len",
-                &format_args!("{}", self.host_hostslc0_len().bits()),
-            )
-            .field(
-                "host_hostslc0_len_check",
-                &format_args!("{}", self.host_hostslc0_len_check().bits()),
-            )
+            .field("host_hostslc0_len", &self.host_hostslc0_len())
+            .field("host_hostslc0_len_check", &self.host_hostslc0_len_check())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_PKT_LEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slchost_pkt_len::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLCHOST_PKT_LEN_SPEC;
 impl crate::RegisterSpec for HOST_SLCHOST_PKT_LEN_SPEC {
diff --git a/esp32/src/slchost/host_slchost_pkt_len0.rs b/esp32/src/slchost/host_slchost_pkt_len0.rs
index 2739135aac..2af8832f02 100644
--- a/esp32/src/slchost/host_slchost_pkt_len0.rs
+++ b/esp32/src/slchost/host_slchost_pkt_len0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_PKT_LEN0")
-            .field(
-                "host_hostslc0_len0",
-                &format_args!("{}", self.host_hostslc0_len0().bits()),
-            )
+            .field("host_hostslc0_len0", &self.host_hostslc0_len0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_PKT_LEN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slchost_pkt_len0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLCHOST_PKT_LEN0_SPEC;
 impl crate::RegisterSpec for HOST_SLCHOST_PKT_LEN0_SPEC {
diff --git a/esp32/src/slchost/host_slchost_pkt_len1.rs b/esp32/src/slchost/host_slchost_pkt_len1.rs
index 7d81ca8af5..6fc2a87eb2 100644
--- a/esp32/src/slchost/host_slchost_pkt_len1.rs
+++ b/esp32/src/slchost/host_slchost_pkt_len1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_PKT_LEN1")
-            .field(
-                "host_hostslc0_len1",
-                &format_args!("{}", self.host_hostslc0_len1().bits()),
-            )
+            .field("host_hostslc0_len1", &self.host_hostslc0_len1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_PKT_LEN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slchost_pkt_len1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLCHOST_PKT_LEN1_SPEC;
 impl crate::RegisterSpec for HOST_SLCHOST_PKT_LEN1_SPEC {
diff --git a/esp32/src/slchost/host_slchost_pkt_len2.rs b/esp32/src/slchost/host_slchost_pkt_len2.rs
index 588aa516ae..2b42c00188 100644
--- a/esp32/src/slchost/host_slchost_pkt_len2.rs
+++ b/esp32/src/slchost/host_slchost_pkt_len2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_PKT_LEN2")
-            .field(
-                "host_hostslc0_len2",
-                &format_args!("{}", self.host_hostslc0_len2().bits()),
-            )
+            .field("host_hostslc0_len2", &self.host_hostslc0_len2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_PKT_LEN2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slchost_pkt_len2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLCHOST_PKT_LEN2_SPEC;
 impl crate::RegisterSpec for HOST_SLCHOST_PKT_LEN2_SPEC {
diff --git a/esp32/src/slchost/host_slchost_rdclr0.rs b/esp32/src/slchost/host_slchost_rdclr0.rs
index 1d4b381c38..0730706847 100644
--- a/esp32/src/slchost/host_slchost_rdclr0.rs
+++ b/esp32/src/slchost/host_slchost_rdclr0.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("HOST_SLCHOST_RDCLR0")
             .field(
                 "host_slchost_slc0_bit7_clraddr",
-                &format_args!("{}", self.host_slchost_slc0_bit7_clraddr().bits()),
+                &self.host_slchost_slc0_bit7_clraddr(),
             )
             .field(
                 "host_slchost_slc0_bit6_clraddr",
-                &format_args!("{}", self.host_slchost_slc0_bit6_clraddr().bits()),
+                &self.host_slchost_slc0_bit6_clraddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_RDCLR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_rdclr1.rs b/esp32/src/slchost/host_slchost_rdclr1.rs
index e389fadf05..2cb9553c46 100644
--- a/esp32/src/slchost/host_slchost_rdclr1.rs
+++ b/esp32/src/slchost/host_slchost_rdclr1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("HOST_SLCHOST_RDCLR1")
             .field(
                 "host_slchost_slc1_bit7_clraddr",
-                &format_args!("{}", self.host_slchost_slc1_bit7_clraddr().bits()),
+                &self.host_slchost_slc1_bit7_clraddr(),
             )
             .field(
                 "host_slchost_slc1_bit6_clraddr",
-                &format_args!("{}", self.host_slchost_slc1_bit6_clraddr().bits()),
+                &self.host_slchost_slc1_bit6_clraddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_RDCLR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchost_state_w0.rs b/esp32/src/slchost/host_slchost_state_w0.rs
index 81869db7e1..131d5bbcd1 100644
--- a/esp32/src/slchost/host_slchost_state_w0.rs
+++ b/esp32/src/slchost/host_slchost_state_w0.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_STATE_W0")
-            .field(
-                "host_slchost_state0",
-                &format_args!("{}", self.host_slchost_state0().bits()),
-            )
-            .field(
-                "host_slchost_state1",
-                &format_args!("{}", self.host_slchost_state1().bits()),
-            )
-            .field(
-                "host_slchost_state2",
-                &format_args!("{}", self.host_slchost_state2().bits()),
-            )
-            .field(
-                "host_slchost_state3",
-                &format_args!("{}", self.host_slchost_state3().bits()),
-            )
+            .field("host_slchost_state0", &self.host_slchost_state0())
+            .field("host_slchost_state1", &self.host_slchost_state1())
+            .field("host_slchost_state2", &self.host_slchost_state2())
+            .field("host_slchost_state3", &self.host_slchost_state3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_STATE_W0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slchost_state_w0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLCHOST_STATE_W0_SPEC;
 impl crate::RegisterSpec for HOST_SLCHOST_STATE_W0_SPEC {
diff --git a/esp32/src/slchost/host_slchost_state_w1.rs b/esp32/src/slchost/host_slchost_state_w1.rs
index 3e721f81f1..fc30d5e299 100644
--- a/esp32/src/slchost/host_slchost_state_w1.rs
+++ b/esp32/src/slchost/host_slchost_state_w1.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOST_STATE_W1")
-            .field(
-                "host_slchost_state4",
-                &format_args!("{}", self.host_slchost_state4().bits()),
-            )
-            .field(
-                "host_slchost_state5",
-                &format_args!("{}", self.host_slchost_state5().bits()),
-            )
-            .field(
-                "host_slchost_state6",
-                &format_args!("{}", self.host_slchost_state6().bits()),
-            )
-            .field(
-                "host_slchost_state7",
-                &format_args!("{}", self.host_slchost_state7().bits()),
-            )
+            .field("host_slchost_state4", &self.host_slchost_state4())
+            .field("host_slchost_state5", &self.host_slchost_state5())
+            .field("host_slchost_state6", &self.host_slchost_state6())
+            .field("host_slchost_state7", &self.host_slchost_state7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_STATE_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slchost_state_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLCHOST_STATE_W1_SPEC;
 impl crate::RegisterSpec for HOST_SLCHOST_STATE_W1_SPEC {
diff --git a/esp32/src/slchost/host_slchost_win_cmd.rs b/esp32/src/slchost/host_slchost_win_cmd.rs
index 243d04d7bf..8a5d360a58 100644
--- a/esp32/src/slchost/host_slchost_win_cmd.rs
+++ b/esp32/src/slchost/host_slchost_win_cmd.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOST_WIN_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`host_slchost_win_cmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`host_slchost_win_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HOST_SLCHOST_WIN_CMD_SPEC;
diff --git a/esp32/src/slchost/host_slchostdate.rs b/esp32/src/slchost/host_slchostdate.rs
index 71c18a8a93..951be34899 100644
--- a/esp32/src/slchost/host_slchostdate.rs
+++ b/esp32/src/slchost/host_slchostdate.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOSTDATE")
-            .field(
-                "host_slchost_date",
-                &format_args!("{}", self.host_slchost_date().bits()),
-            )
+            .field("host_slchost_date", &self.host_slchost_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOSTDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/slchost/host_slchostid.rs b/esp32/src/slchost/host_slchostid.rs
index 2751ae373f..6054841e4a 100644
--- a/esp32/src/slchost/host_slchostid.rs
+++ b/esp32/src/slchost/host_slchostid.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_SLCHOSTID")
-            .field(
-                "host_slchost_id",
-                &format_args!("{}", self.host_slchost_id().bits()),
-            )
+            .field("host_slchost_id", &self.host_slchost_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_SLCHOSTID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/spi0/addr.rs b/esp32/src/spi0/addr.rs
index 3aa0fc138b..e797e26c18 100644
--- a/esp32/src/spi0/addr.rs
+++ b/esp32/src/spi0/addr.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ADDR_SPEC;
diff --git a/esp32/src/spi0/cache_fctrl.rs b/esp32/src/spi0/cache_fctrl.rs
index 2b507356cb..cb89db9b90 100644
--- a/esp32/src/spi0/cache_fctrl.rs
+++ b/esp32/src/spi0/cache_fctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_FCTRL")
-            .field(
-                "cache_req_en",
-                &format_args!("{}", self.cache_req_en().bit()),
-            )
-            .field(
-                "cache_usr_cmd_4byte",
-                &format_args!("{}", self.cache_usr_cmd_4byte().bit()),
-            )
-            .field(
-                "cache_flash_usr_cmd",
-                &format_args!("{}", self.cache_flash_usr_cmd().bit()),
-            )
-            .field(
-                "cache_flash_pes_en",
-                &format_args!("{}", self.cache_flash_pes_en().bit()),
-            )
+            .field("cache_req_en", &self.cache_req_en())
+            .field("cache_usr_cmd_4byte", &self.cache_usr_cmd_4byte())
+            .field("cache_flash_usr_cmd", &self.cache_flash_usr_cmd())
+            .field("cache_flash_pes_en", &self.cache_flash_pes_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_FCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - For SPI0 Cache access enable 1: enable 0:disable."]
     #[inline(always)]
diff --git a/esp32/src/spi0/cache_sctrl.rs b/esp32/src/spi0/cache_sctrl.rs
index fab9e1ca31..ea9b5502b1 100644
--- a/esp32/src/spi0/cache_sctrl.rs
+++ b/esp32/src/spi0/cache_sctrl.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_SCTRL")
-            .field(
-                "usr_sram_dio",
-                &format_args!("{}", self.usr_sram_dio().bit()),
-            )
-            .field(
-                "usr_sram_qio",
-                &format_args!("{}", self.usr_sram_qio().bit()),
-            )
-            .field(
-                "usr_wr_sram_dummy",
-                &format_args!("{}", self.usr_wr_sram_dummy().bit()),
-            )
-            .field(
-                "usr_rd_sram_dummy",
-                &format_args!("{}", self.usr_rd_sram_dummy().bit()),
-            )
-            .field(
-                "cache_sram_usr_rcmd",
-                &format_args!("{}", self.cache_sram_usr_rcmd().bit()),
-            )
-            .field(
-                "sram_bytes_len",
-                &format_args!("{}", self.sram_bytes_len().bits()),
-            )
-            .field(
-                "sram_dummy_cyclelen",
-                &format_args!("{}", self.sram_dummy_cyclelen().bits()),
-            )
-            .field(
-                "sram_addr_bitlen",
-                &format_args!("{}", self.sram_addr_bitlen().bits()),
-            )
-            .field(
-                "cache_sram_usr_wcmd",
-                &format_args!("{}", self.cache_sram_usr_wcmd().bit()),
-            )
+            .field("usr_sram_dio", &self.usr_sram_dio())
+            .field("usr_sram_qio", &self.usr_sram_qio())
+            .field("usr_wr_sram_dummy", &self.usr_wr_sram_dummy())
+            .field("usr_rd_sram_dummy", &self.usr_rd_sram_dummy())
+            .field("cache_sram_usr_rcmd", &self.cache_sram_usr_rcmd())
+            .field("sram_bytes_len", &self.sram_bytes_len())
+            .field("sram_dummy_cyclelen", &self.sram_dummy_cyclelen())
+            .field("sram_addr_bitlen", &self.sram_addr_bitlen())
+            .field("cache_sram_usr_wcmd", &self.cache_sram_usr_wcmd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_SCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable"]
     #[inline(always)]
diff --git a/esp32/src/spi0/clock.rs b/esp32/src/spi0/clock.rs
index 12e30ce122..dfb23f726b 100644
--- a/esp32/src/spi0/clock.rs
+++ b/esp32/src/spi0/clock.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field("clkdiv_pre", &format_args!("{}", self.clkdiv_pre().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clkdiv_pre", &self.clkdiv_pre())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0."]
     #[inline(always)]
diff --git a/esp32/src/spi0/cmd.rs b/esp32/src/spi0/cmd.rs
index eb7c0a7881..5392df2d42 100644
--- a/esp32/src/spi0/cmd.rs
+++ b/esp32/src/spi0/cmd.rs
@@ -152,31 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("flash_per", &format_args!("{}", self.flash_per().bit()))
-            .field("flash_pes", &format_args!("{}", self.flash_pes().bit()))
-            .field("usr", &format_args!("{}", self.usr().bit()))
-            .field("flash_hpm", &format_args!("{}", self.flash_hpm().bit()))
-            .field("flash_res", &format_args!("{}", self.flash_res().bit()))
-            .field("flash_dp", &format_args!("{}", self.flash_dp().bit()))
-            .field("flash_ce", &format_args!("{}", self.flash_ce().bit()))
-            .field("flash_be", &format_args!("{}", self.flash_be().bit()))
-            .field("flash_se", &format_args!("{}", self.flash_se().bit()))
-            .field("flash_pp", &format_args!("{}", self.flash_pp().bit()))
-            .field("flash_wrsr", &format_args!("{}", self.flash_wrsr().bit()))
-            .field("flash_rdsr", &format_args!("{}", self.flash_rdsr().bit()))
-            .field("flash_rdid", &format_args!("{}", self.flash_rdid().bit()))
-            .field("flash_wrdi", &format_args!("{}", self.flash_wrdi().bit()))
-            .field("flash_wren", &format_args!("{}", self.flash_wren().bit()))
-            .field("flash_read", &format_args!("{}", self.flash_read().bit()))
+            .field("flash_per", &self.flash_per())
+            .field("flash_pes", &self.flash_pes())
+            .field("usr", &self.usr())
+            .field("flash_hpm", &self.flash_hpm())
+            .field("flash_res", &self.flash_res())
+            .field("flash_dp", &self.flash_dp())
+            .field("flash_ce", &self.flash_ce())
+            .field("flash_be", &self.flash_be())
+            .field("flash_se", &self.flash_se())
+            .field("flash_pp", &self.flash_pp())
+            .field("flash_wrsr", &self.flash_wrsr())
+            .field("flash_rdsr", &self.flash_rdsr())
+            .field("flash_rdid", &self.flash_rdid())
+            .field("flash_wrdi", &self.flash_wrdi())
+            .field("flash_wren", &self.flash_wren())
+            .field("flash_read", &self.flash_read())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16 - program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32/src/spi0/ctrl.rs b/esp32/src/spi0/ctrl.rs
index 73faffe662..ca58424f74 100644
--- a/esp32/src/spi0/ctrl.rs
+++ b/esp32/src/spi0/ctrl.rs
@@ -125,37 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("fcs_crc_en", &format_args!("{}", self.fcs_crc_en().bit()))
-            .field("tx_crc_en", &format_args!("{}", self.tx_crc_en().bit()))
-            .field(
-                "wait_flash_idle_en",
-                &format_args!("{}", self.wait_flash_idle_en().bit()),
-            )
-            .field("fastrd_mode", &format_args!("{}", self.fastrd_mode().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("resandres", &format_args!("{}", self.resandres().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("wp", &format_args!("{}", self.wp().bit()))
-            .field("wrsr_2b", &format_args!("{}", self.wrsr_2b().bit()))
-            .field("fread_dio", &format_args!("{}", self.fread_dio().bit()))
-            .field("fread_qio", &format_args!("{}", self.fread_qio().bit()))
-            .field(
-                "rd_bit_order",
-                &format_args!("{}", self.rd_bit_order().bit()),
-            )
-            .field(
-                "wr_bit_order",
-                &format_args!("{}", self.wr_bit_order().bit()),
-            )
+            .field("fcs_crc_en", &self.fcs_crc_en())
+            .field("tx_crc_en", &self.tx_crc_en())
+            .field("wait_flash_idle_en", &self.wait_flash_idle_en())
+            .field("fastrd_mode", &self.fastrd_mode())
+            .field("fread_dual", &self.fread_dual())
+            .field("resandres", &self.resandres())
+            .field("fread_quad", &self.fread_quad())
+            .field("wp", &self.wp())
+            .field("wrsr_2b", &self.wrsr_2b())
+            .field("fread_dio", &self.fread_dio())
+            .field("fread_qio", &self.fread_qio())
+            .field("rd_bit_order", &self.rd_bit_order())
+            .field("wr_bit_order", &self.wr_bit_order())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 10 - For SPI1 initialize crc32 module before writing encrypted data to flash. Active low."]
     #[inline(always)]
diff --git a/esp32/src/spi0/ctrl1.rs b/esp32/src/spi0/ctrl1.rs
index 1d3c92c787..02c90685b4 100644
--- a/esp32/src/spi0/ctrl1.rs
+++ b/esp32/src/spi0/ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL1")
-            .field(
-                "cs_hold_delay_res",
-                &format_args!("{}", self.cs_hold_delay_res().bits()),
-            )
-            .field(
-                "cs_hold_delay",
-                &format_args!("{}", self.cs_hold_delay().bits()),
-            )
+            .field("cs_hold_delay_res", &self.cs_hold_delay_res())
+            .field("cs_hold_delay", &self.cs_hold_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:27 - Delay cycles of resume Flash when resume Flash is enable by spi clock."]
     #[inline(always)]
diff --git a/esp32/src/spi0/ctrl2.rs b/esp32/src/spi0/ctrl2.rs
index ed23ff05c1..a4ab113fd3 100644
--- a/esp32/src/spi0/ctrl2.rs
+++ b/esp32/src/spi0/ctrl2.rs
@@ -98,49 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field("setup_time", &format_args!("{}", self.setup_time().bits()))
-            .field("hold_time", &format_args!("{}", self.hold_time().bits()))
-            .field(
-                "ck_out_low_mode",
-                &format_args!("{}", self.ck_out_low_mode().bits()),
-            )
-            .field(
-                "ck_out_high_mode",
-                &format_args!("{}", self.ck_out_high_mode().bits()),
-            )
-            .field(
-                "miso_delay_mode",
-                &format_args!("{}", self.miso_delay_mode().bits()),
-            )
-            .field(
-                "miso_delay_num",
-                &format_args!("{}", self.miso_delay_num().bits()),
-            )
-            .field(
-                "mosi_delay_mode",
-                &format_args!("{}", self.mosi_delay_mode().bits()),
-            )
-            .field(
-                "mosi_delay_num",
-                &format_args!("{}", self.mosi_delay_num().bits()),
-            )
-            .field(
-                "cs_delay_mode",
-                &format_args!("{}", self.cs_delay_mode().bits()),
-            )
-            .field(
-                "cs_delay_num",
-                &format_args!("{}", self.cs_delay_num().bits()),
-            )
+            .field("setup_time", &self.setup_time())
+            .field("hold_time", &self.hold_time())
+            .field("ck_out_low_mode", &self.ck_out_low_mode())
+            .field("ck_out_high_mode", &self.ck_out_high_mode())
+            .field("miso_delay_mode", &self.miso_delay_mode())
+            .field("miso_delay_num", &self.miso_delay_num())
+            .field("mosi_delay_mode", &self.mosi_delay_mode())
+            .field("mosi_delay_num", &self.mosi_delay_num())
+            .field("cs_delay_mode", &self.cs_delay_mode())
+            .field("cs_delay_num", &self.cs_delay_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - (cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit."]
     #[inline(always)]
diff --git a/esp32/src/spi0/date.rs b/esp32/src/spi0/date.rs
index f935c5f0b8..271a3edaf9 100644
--- a/esp32/src/spi0/date.rs
+++ b/esp32/src/spi0/date.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/spi0/dma_conf.rs b/esp32/src/spi0/dma_conf.rs
index 6e52b24dcb..f7c27760c3 100644
--- a/esp32/src/spi0/dma_conf.rs
+++ b/esp32/src/spi0/dma_conf.rs
@@ -134,56 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
-            .field("out_rst", &format_args!("{}", self.out_rst().bit()))
-            .field(
-                "ahbm_fifo_rst",
-                &format_args!("{}", self.ahbm_fifo_rst().bit()),
-            )
-            .field("ahbm_rst", &format_args!("{}", self.ahbm_rst().bit()))
-            .field(
-                "in_loop_test",
-                &format_args!("{}", self.in_loop_test().bit()),
-            )
-            .field(
-                "out_loop_test",
-                &format_args!("{}", self.out_loop_test().bit()),
-            )
-            .field(
-                "out_auto_wrback",
-                &format_args!("{}", self.out_auto_wrback().bit()),
-            )
-            .field(
-                "out_eof_mode",
-                &format_args!("{}", self.out_eof_mode().bit()),
-            )
-            .field(
-                "outdscr_burst_en",
-                &format_args!("{}", self.outdscr_burst_en().bit()),
-            )
-            .field(
-                "indscr_burst_en",
-                &format_args!("{}", self.indscr_burst_en().bit()),
-            )
-            .field(
-                "out_data_burst_en",
-                &format_args!("{}", self.out_data_burst_en().bit()),
-            )
-            .field("dma_rx_stop", &format_args!("{}", self.dma_rx_stop().bit()))
-            .field("dma_tx_stop", &format_args!("{}", self.dma_tx_stop().bit()))
-            .field(
-                "dma_continue",
-                &format_args!("{}", self.dma_continue().bit()),
-            )
+            .field("in_rst", &self.in_rst())
+            .field("out_rst", &self.out_rst())
+            .field("ahbm_fifo_rst", &self.ahbm_fifo_rst())
+            .field("ahbm_rst", &self.ahbm_rst())
+            .field("in_loop_test", &self.in_loop_test())
+            .field("out_loop_test", &self.out_loop_test())
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("out_eof_mode", &self.out_eof_mode())
+            .field("outdscr_burst_en", &self.outdscr_burst_en())
+            .field("indscr_burst_en", &self.indscr_burst_en())
+            .field("out_data_burst_en", &self.out_data_burst_en())
+            .field("dma_rx_stop", &self.dma_rx_stop())
+            .field("dma_tx_stop", &self.dma_tx_stop())
+            .field("dma_continue", &self.dma_continue())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - The bit is used to reset in dma fsm and in data fifo pointer."]
     #[inline(always)]
diff --git a/esp32/src/spi0/dma_in_link.rs b/esp32/src/spi0/dma_in_link.rs
index 226f8decb3..d9cedef12f 100644
--- a/esp32/src/spi0/dma_in_link.rs
+++ b/esp32/src/spi0/dma_in_link.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_LINK")
-            .field(
-                "inlink_addr",
-                &format_args!("{}", self.inlink_addr().bits()),
-            )
-            .field(
-                "inlink_auto_ret",
-                &format_args!("{}", self.inlink_auto_ret().bit()),
-            )
-            .field("inlink_stop", &format_args!("{}", self.inlink_stop().bit()))
-            .field(
-                "inlink_start",
-                &format_args!("{}", self.inlink_start().bit()),
-            )
-            .field(
-                "inlink_restart",
-                &format_args!("{}", self.inlink_restart().bit()),
-            )
+            .field("inlink_addr", &self.inlink_addr())
+            .field("inlink_auto_ret", &self.inlink_auto_ret())
+            .field("inlink_stop", &self.inlink_stop())
+            .field("inlink_start", &self.inlink_start())
+            .field("inlink_restart", &self.inlink_restart())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - The address of the first inlink descriptor."]
     #[inline(always)]
diff --git a/esp32/src/spi0/dma_int_clr.rs b/esp32/src/spi0/dma_int_clr.rs
index 4350d085b3..ddf1098082 100644
--- a/esp32/src/spi0/dma_int_clr.rs
+++ b/esp32/src/spi0/dma_int_clr.rs
@@ -89,36 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_CLR")
-            .field(
-                "inlink_dscr_empty",
-                &format_args!("{}", self.inlink_dscr_empty().bit()),
-            )
-            .field(
-                "outlink_dscr_error",
-                &format_args!("{}", self.outlink_dscr_error().bit()),
-            )
-            .field(
-                "inlink_dscr_error",
-                &format_args!("{}", self.inlink_dscr_error().bit()),
-            )
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
+            .field("inlink_dscr_empty", &self.inlink_dscr_empty())
+            .field("outlink_dscr_error", &self.outlink_dscr_error())
+            .field("inlink_dscr_error", &self.inlink_dscr_error())
+            .field("in_done", &self.in_done())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_total_eof", &self.out_total_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The clear bit for lack of enough inlink descriptors."]
     #[inline(always)]
diff --git a/esp32/src/spi0/dma_int_ena.rs b/esp32/src/spi0/dma_int_ena.rs
index 7ce229861d..71aee5773c 100644
--- a/esp32/src/spi0/dma_int_ena.rs
+++ b/esp32/src/spi0/dma_int_ena.rs
@@ -89,36 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ENA")
-            .field(
-                "inlink_dscr_empty",
-                &format_args!("{}", self.inlink_dscr_empty().bit()),
-            )
-            .field(
-                "outlink_dscr_error",
-                &format_args!("{}", self.outlink_dscr_error().bit()),
-            )
-            .field(
-                "inlink_dscr_error",
-                &format_args!("{}", self.inlink_dscr_error().bit()),
-            )
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
+            .field("inlink_dscr_empty", &self.inlink_dscr_empty())
+            .field("outlink_dscr_error", &self.outlink_dscr_error())
+            .field("inlink_dscr_error", &self.inlink_dscr_error())
+            .field("in_done", &self.in_done())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_total_eof", &self.out_total_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for lack of enough inlink descriptors."]
     #[inline(always)]
diff --git a/esp32/src/spi0/dma_int_raw.rs b/esp32/src/spi0/dma_int_raw.rs
index 8e1b4f1e1c..31b580f44e 100644
--- a/esp32/src/spi0/dma_int_raw.rs
+++ b/esp32/src/spi0/dma_int_raw.rs
@@ -69,36 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_RAW")
-            .field(
-                "inlink_dscr_empty",
-                &format_args!("{}", self.inlink_dscr_empty().bit()),
-            )
-            .field(
-                "outlink_dscr_error",
-                &format_args!("{}", self.outlink_dscr_error().bit()),
-            )
-            .field(
-                "inlink_dscr_error",
-                &format_args!("{}", self.inlink_dscr_error().bit()),
-            )
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
+            .field("inlink_dscr_empty", &self.inlink_dscr_empty())
+            .field("outlink_dscr_error", &self.outlink_dscr_error())
+            .field("inlink_dscr_error", &self.inlink_dscr_error())
+            .field("in_done", &self.in_done())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_total_eof", &self.out_total_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_INT_RAW_SPEC;
 impl crate::RegisterSpec for DMA_INT_RAW_SPEC {
diff --git a/esp32/src/spi0/dma_int_st.rs b/esp32/src/spi0/dma_int_st.rs
index 4e847f34a0..e3f394d621 100644
--- a/esp32/src/spi0/dma_int_st.rs
+++ b/esp32/src/spi0/dma_int_st.rs
@@ -69,36 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ST")
-            .field(
-                "inlink_dscr_empty",
-                &format_args!("{}", self.inlink_dscr_empty().bit()),
-            )
-            .field(
-                "outlink_dscr_error",
-                &format_args!("{}", self.outlink_dscr_error().bit()),
-            )
-            .field(
-                "inlink_dscr_error",
-                &format_args!("{}", self.inlink_dscr_error().bit()),
-            )
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
+            .field("inlink_dscr_empty", &self.inlink_dscr_empty())
+            .field("outlink_dscr_error", &self.outlink_dscr_error())
+            .field("inlink_dscr_error", &self.inlink_dscr_error())
+            .field("in_done", &self.in_done())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_total_eof", &self.out_total_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_INT_ST_SPEC;
 impl crate::RegisterSpec for DMA_INT_ST_SPEC {
diff --git a/esp32/src/spi0/dma_out_link.rs b/esp32/src/spi0/dma_out_link.rs
index fe0f5c683a..bf47874bbd 100644
--- a/esp32/src/spi0/dma_out_link.rs
+++ b/esp32/src/spi0/dma_out_link.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_LINK")
-            .field(
-                "outlink_addr",
-                &format_args!("{}", self.outlink_addr().bits()),
-            )
-            .field(
-                "outlink_stop",
-                &format_args!("{}", self.outlink_stop().bit()),
-            )
-            .field(
-                "outlink_start",
-                &format_args!("{}", self.outlink_start().bit()),
-            )
-            .field(
-                "outlink_restart",
-                &format_args!("{}", self.outlink_restart().bit()),
-            )
+            .field("outlink_addr", &self.outlink_addr())
+            .field("outlink_stop", &self.outlink_stop())
+            .field("outlink_start", &self.outlink_start())
+            .field("outlink_restart", &self.outlink_restart())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - The address of the first outlink descriptor."]
     #[inline(always)]
diff --git a/esp32/src/spi0/dma_rstatus.rs b/esp32/src/spi0/dma_rstatus.rs
index f672b4f4bf..11943bb384 100644
--- a/esp32/src/spi0/dma_rstatus.rs
+++ b/esp32/src/spi0/dma_rstatus.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_RSTATUS")
-            .field(
-                "dma_out_status",
-                &format_args!("{}", self.dma_out_status().bits()),
-            )
+            .field("dma_out_status", &self.dma_out_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_RSTATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_rstatus::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_RSTATUS_SPEC;
 impl crate::RegisterSpec for DMA_RSTATUS_SPEC {
diff --git a/esp32/src/spi0/dma_status.rs b/esp32/src/spi0/dma_status.rs
index fe92166ff3..f40e388c45 100644
--- a/esp32/src/spi0/dma_status.rs
+++ b/esp32/src/spi0/dma_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_STATUS")
-            .field("dma_rx_en", &format_args!("{}", self.dma_rx_en().bit()))
-            .field("dma_tx_en", &format_args!("{}", self.dma_tx_en().bit()))
+            .field("dma_rx_en", &self.dma_rx_en())
+            .field("dma_tx_en", &self.dma_tx_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_STATUS_SPEC;
 impl crate::RegisterSpec for DMA_STATUS_SPEC {
diff --git a/esp32/src/spi0/dma_tstatus.rs b/esp32/src/spi0/dma_tstatus.rs
index 1c8dc6fe78..0e1859f585 100644
--- a/esp32/src/spi0/dma_tstatus.rs
+++ b/esp32/src/spi0/dma_tstatus.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_TSTATUS")
-            .field(
-                "dma_in_status",
-                &format_args!("{}", self.dma_in_status().bits()),
-            )
+            .field("dma_in_status", &self.dma_in_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_TSTATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_tstatus::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_TSTATUS_SPEC;
 impl crate::RegisterSpec for DMA_TSTATUS_SPEC {
diff --git a/esp32/src/spi0/ext0.rs b/esp32/src/spi0/ext0.rs
index 58a06079b3..9e21c60482 100644
--- a/esp32/src/spi0/ext0.rs
+++ b/esp32/src/spi0/ext0.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT0")
-            .field("t_pp_time", &format_args!("{}", self.t_pp_time().bits()))
-            .field("t_pp_shift", &format_args!("{}", self.t_pp_shift().bits()))
-            .field("t_pp_ena", &format_args!("{}", self.t_pp_ena().bit()))
+            .field("t_pp_time", &self.t_pp_time())
+            .field("t_pp_shift", &self.t_pp_shift())
+            .field("t_pp_ena", &self.t_pp_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - page program delay time by system clock."]
     #[inline(always)]
diff --git a/esp32/src/spi0/ext1.rs b/esp32/src/spi0/ext1.rs
index 9440631863..e98a09dc79 100644
--- a/esp32/src/spi0/ext1.rs
+++ b/esp32/src/spi0/ext1.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT1")
-            .field(
-                "t_erase_time",
-                &format_args!("{}", self.t_erase_time().bits()),
-            )
-            .field(
-                "t_erase_shift",
-                &format_args!("{}", self.t_erase_shift().bits()),
-            )
-            .field("t_erase_ena", &format_args!("{}", self.t_erase_ena().bit()))
+            .field("t_erase_time", &self.t_erase_time())
+            .field("t_erase_shift", &self.t_erase_shift())
+            .field("t_erase_ena", &self.t_erase_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - erase flash delay time by system clock."]
     #[inline(always)]
diff --git a/esp32/src/spi0/ext2.rs b/esp32/src/spi0/ext2.rs
index 176375d881..f4ae0656c2 100644
--- a/esp32/src/spi0/ext2.rs
+++ b/esp32/src/spi0/ext2.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("EXT2")
-            .field("st", &format_args!("{}", self.st().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("EXT2").field("st", &self.st()).finish()
     }
 }
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/spi0/ext3.rs b/esp32/src/spi0/ext3.rs
index ef3ce201b4..0969785401 100644
--- a/esp32/src/spi0/ext3.rs
+++ b/esp32/src/spi0/ext3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT3")
-            .field(
-                "int_hold_ena",
-                &format_args!("{}", self.int_hold_ena().bits()),
-            )
+            .field("int_hold_ena", &self.int_hold_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase."]
     #[inline(always)]
diff --git a/esp32/src/spi0/in_err_eof_des_addr.rs b/esp32/src/spi0/in_err_eof_des_addr.rs
index 378493a2fa..a15f9110f7 100644
--- a/esp32/src/spi0/in_err_eof_des_addr.rs
+++ b/esp32/src/spi0/in_err_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_ERR_EOF_DES_ADDR")
-            .field(
-                "dma_in_err_eof_des_addr",
-                &format_args!("{}", self.dma_in_err_eof_des_addr().bits()),
-            )
+            .field("dma_in_err_eof_des_addr", &self.dma_in_err_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_ERR_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_ERR_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_SPEC {
diff --git a/esp32/src/spi0/in_suc_eof_des_addr.rs b/esp32/src/spi0/in_suc_eof_des_addr.rs
index a79cfe33fe..cca6f1caee 100644
--- a/esp32/src/spi0/in_suc_eof_des_addr.rs
+++ b/esp32/src/spi0/in_suc_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_SUC_EOF_DES_ADDR")
-            .field(
-                "dma_in_suc_eof_des_addr",
-                &format_args!("{}", self.dma_in_suc_eof_des_addr().bits()),
-            )
+            .field("dma_in_suc_eof_des_addr", &self.dma_in_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SUC_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SUC_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_SPEC {
diff --git a/esp32/src/spi0/inlink_dscr.rs b/esp32/src/spi0/inlink_dscr.rs
index 970b51abe3..7b2a10550f 100644
--- a/esp32/src/spi0/inlink_dscr.rs
+++ b/esp32/src/spi0/inlink_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INLINK_DSCR")
-            .field(
-                "dma_inlink_dscr",
-                &format_args!("{}", self.dma_inlink_dscr().bits()),
-            )
+            .field("dma_inlink_dscr", &self.dma_inlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INLINK_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inlink_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INLINK_DSCR_SPEC;
 impl crate::RegisterSpec for INLINK_DSCR_SPEC {
diff --git a/esp32/src/spi0/inlink_dscr_bf0.rs b/esp32/src/spi0/inlink_dscr_bf0.rs
index 81deb8a580..392f50737c 100644
--- a/esp32/src/spi0/inlink_dscr_bf0.rs
+++ b/esp32/src/spi0/inlink_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INLINK_DSCR_BF0")
-            .field(
-                "dma_inlink_dscr_bf0",
-                &format_args!("{}", self.dma_inlink_dscr_bf0().bits()),
-            )
+            .field("dma_inlink_dscr_bf0", &self.dma_inlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INLINK_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inlink_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INLINK_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for INLINK_DSCR_BF0_SPEC {
diff --git a/esp32/src/spi0/inlink_dscr_bf1.rs b/esp32/src/spi0/inlink_dscr_bf1.rs
index c3e3d36837..d8a1e4d160 100644
--- a/esp32/src/spi0/inlink_dscr_bf1.rs
+++ b/esp32/src/spi0/inlink_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INLINK_DSCR_BF1")
-            .field(
-                "dma_inlink_dscr_bf1",
-                &format_args!("{}", self.dma_inlink_dscr_bf1().bits()),
-            )
+            .field("dma_inlink_dscr_bf1", &self.dma_inlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INLINK_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inlink_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INLINK_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for INLINK_DSCR_BF1_SPEC {
diff --git a/esp32/src/spi0/miso_dlen.rs b/esp32/src/spi0/miso_dlen.rs
index 753ba738b9..c0a9e2b463 100644
--- a/esp32/src/spi0/miso_dlen.rs
+++ b/esp32/src/spi0/miso_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISO_DLEN")
-            .field(
-                "usr_miso_dbitlen",
-                &format_args!("{}", self.usr_miso_dbitlen().bits()),
-            )
+            .field("usr_miso_dbitlen", &self.usr_miso_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISO_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - The length in bits of read-data. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32/src/spi0/mosi_dlen.rs b/esp32/src/spi0/mosi_dlen.rs
index aa961edf6e..efec202f3b 100644
--- a/esp32/src/spi0/mosi_dlen.rs
+++ b/esp32/src/spi0/mosi_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MOSI_DLEN")
-            .field(
-                "usr_mosi_dbitlen",
-                &format_args!("{}", self.usr_mosi_dbitlen().bits()),
-            )
+            .field("usr_mosi_dbitlen", &self.usr_mosi_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MOSI_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - The length in bits of write-data. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32/src/spi0/out_eof_bfr_des_addr.rs b/esp32/src/spi0/out_eof_bfr_des_addr.rs
index 0fab95f0b3..2193263642 100644
--- a/esp32/src/spi0/out_eof_bfr_des_addr.rs
+++ b/esp32/src/spi0/out_eof_bfr_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_BFR_DES_ADDR")
-            .field(
-                "dma_out_eof_bfr_des_addr",
-                &format_args!("{}", self.dma_out_eof_bfr_des_addr().bits()),
-            )
+            .field("dma_out_eof_bfr_des_addr", &self.dma_out_eof_bfr_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_BFR_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_bfr_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_BFR_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_SPEC {
diff --git a/esp32/src/spi0/out_eof_des_addr.rs b/esp32/src/spi0/out_eof_des_addr.rs
index 3c7ad031c8..23d911c633 100644
--- a/esp32/src/spi0/out_eof_des_addr.rs
+++ b/esp32/src/spi0/out_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_DES_ADDR")
-            .field(
-                "dma_out_eof_des_addr",
-                &format_args!("{}", self.dma_out_eof_des_addr().bits()),
-            )
+            .field("dma_out_eof_des_addr", &self.dma_out_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_DES_ADDR_SPEC {
diff --git a/esp32/src/spi0/outlink_dscr.rs b/esp32/src/spi0/outlink_dscr.rs
index 822ff48689..01368bcc93 100644
--- a/esp32/src/spi0/outlink_dscr.rs
+++ b/esp32/src/spi0/outlink_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTLINK_DSCR")
-            .field(
-                "dma_outlink_dscr",
-                &format_args!("{}", self.dma_outlink_dscr().bits()),
-            )
+            .field("dma_outlink_dscr", &self.dma_outlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTLINK_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outlink_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTLINK_DSCR_SPEC;
 impl crate::RegisterSpec for OUTLINK_DSCR_SPEC {
diff --git a/esp32/src/spi0/outlink_dscr_bf0.rs b/esp32/src/spi0/outlink_dscr_bf0.rs
index aab8d1ae43..92aae186ac 100644
--- a/esp32/src/spi0/outlink_dscr_bf0.rs
+++ b/esp32/src/spi0/outlink_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTLINK_DSCR_BF0")
-            .field(
-                "dma_outlink_dscr_bf0",
-                &format_args!("{}", self.dma_outlink_dscr_bf0().bits()),
-            )
+            .field("dma_outlink_dscr_bf0", &self.dma_outlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTLINK_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outlink_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTLINK_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for OUTLINK_DSCR_BF0_SPEC {
diff --git a/esp32/src/spi0/outlink_dscr_bf1.rs b/esp32/src/spi0/outlink_dscr_bf1.rs
index 7626c2c132..ed0323de8c 100644
--- a/esp32/src/spi0/outlink_dscr_bf1.rs
+++ b/esp32/src/spi0/outlink_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTLINK_DSCR_BF1")
-            .field(
-                "dma_outlink_dscr_bf1",
-                &format_args!("{}", self.dma_outlink_dscr_bf1().bits()),
-            )
+            .field("dma_outlink_dscr_bf1", &self.dma_outlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTLINK_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outlink_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTLINK_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for OUTLINK_DSCR_BF1_SPEC {
diff --git a/esp32/src/spi0/pin.rs b/esp32/src/spi0/pin.rs
index 543b464959..87574419bf 100644
--- a/esp32/src/spi0/pin.rs
+++ b/esp32/src/spi0/pin.rs
@@ -80,35 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN")
-            .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
-            .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
-            .field("cs2_dis", &format_args!("{}", self.cs2_dis().bit()))
-            .field("ck_dis", &format_args!("{}", self.ck_dis().bit()))
-            .field(
-                "master_cs_pol",
-                &format_args!("{}", self.master_cs_pol().bits()),
-            )
-            .field(
-                "master_ck_sel",
-                &format_args!("{}", self.master_ck_sel().bits()),
-            )
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("cs2_dis", &self.cs2_dis())
+            .field("ck_dis", &self.ck_dis())
+            .field("master_cs_pol", &self.master_cs_pol())
+            .field("master_ck_sel", &self.master_ck_sel())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin"]
     #[inline(always)]
diff --git a/esp32/src/spi0/rd_status.rs b/esp32/src/spi0/rd_status.rs
index 2060bead07..31c6d0b1b2 100644
--- a/esp32/src/spi0/rd_status.rs
+++ b/esp32/src/spi0/rd_status.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_STATUS")
-            .field("status", &format_args!("{}", self.status().bits()))
-            .field("wb_mode", &format_args!("{}", self.wb_mode().bits()))
-            .field("status_ext", &format_args!("{}", self.status_ext().bits()))
+            .field("status", &self.status())
+            .field("wb_mode", &self.wb_mode())
+            .field("status_ext", &self.status_ext())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - In the slave mode, it is the status for master to read out."]
     #[inline(always)]
diff --git a/esp32/src/spi0/slave.rs b/esp32/src/spi0/slave.rs
index 060e807bae..8c342d44a0 100644
--- a/esp32/src/spi0/slave.rs
+++ b/esp32/src/spi0/slave.rs
@@ -137,57 +137,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE")
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field(
-                "slv_rd_sta_done",
-                &format_args!("{}", self.slv_rd_sta_done().bit()),
-            )
-            .field(
-                "slv_wr_sta_done",
-                &format_args!("{}", self.slv_wr_sta_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field("int_en", &format_args!("{}", self.int_en().bits()))
-            .field("cs_i_mode", &format_args!("{}", self.cs_i_mode().bits()))
-            .field(
-                "slv_last_command",
-                &format_args!("{}", self.slv_last_command().bits()),
-            )
-            .field(
-                "slv_last_state",
-                &format_args!("{}", self.slv_last_state().bits()),
-            )
-            .field("trans_cnt", &format_args!("{}", self.trans_cnt().bits()))
-            .field(
-                "slv_cmd_define",
-                &format_args!("{}", self.slv_cmd_define().bit()),
-            )
-            .field(
-                "slv_wr_rd_sta_en",
-                &format_args!("{}", self.slv_wr_rd_sta_en().bit()),
-            )
-            .field(
-                "slv_wr_rd_buf_en",
-                &format_args!("{}", self.slv_wr_rd_buf_en().bit()),
-            )
-            .field("mode", &format_args!("{}", self.mode().bit()))
-            .field("sync_reset", &format_args!("{}", self.sync_reset().bit()))
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("slv_rd_sta_done", &self.slv_rd_sta_done())
+            .field("slv_wr_sta_done", &self.slv_wr_sta_done())
+            .field("trans_done", &self.trans_done())
+            .field("int_en", &self.int_en())
+            .field("cs_i_mode", &self.cs_i_mode())
+            .field("slv_last_command", &self.slv_last_command())
+            .field("slv_last_state", &self.slv_last_state())
+            .field("trans_cnt", &self.trans_cnt())
+            .field("slv_cmd_define", &self.slv_cmd_define())
+            .field("slv_wr_rd_sta_en", &self.slv_wr_rd_sta_en())
+            .field("slv_wr_rd_buf_en", &self.slv_wr_rd_buf_en())
+            .field("mode", &self.mode())
+            .field("sync_reset", &self.sync_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt raw bit for the completion of read-buffer operation in the slave mode."]
     #[inline(always)]
diff --git a/esp32/src/spi0/slave1.rs b/esp32/src/spi0/slave1.rs
index 27e2213c46..6cc326643c 100644
--- a/esp32/src/spi0/slave1.rs
+++ b/esp32/src/spi0/slave1.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE1")
-            .field(
-                "slv_rdbuf_dummy_en",
-                &format_args!("{}", self.slv_rdbuf_dummy_en().bit()),
-            )
-            .field(
-                "slv_wrbuf_dummy_en",
-                &format_args!("{}", self.slv_wrbuf_dummy_en().bit()),
-            )
-            .field(
-                "slv_rdsta_dummy_en",
-                &format_args!("{}", self.slv_rdsta_dummy_en().bit()),
-            )
-            .field(
-                "slv_wrsta_dummy_en",
-                &format_args!("{}", self.slv_wrsta_dummy_en().bit()),
-            )
-            .field(
-                "slv_wr_addr_bitlen",
-                &format_args!("{}", self.slv_wr_addr_bitlen().bits()),
-            )
-            .field(
-                "slv_rd_addr_bitlen",
-                &format_args!("{}", self.slv_rd_addr_bitlen().bits()),
-            )
-            .field(
-                "slv_status_readback",
-                &format_args!("{}", self.slv_status_readback().bit()),
-            )
-            .field(
-                "slv_status_fast_en",
-                &format_args!("{}", self.slv_status_fast_en().bit()),
-            )
-            .field(
-                "slv_status_bitlen",
-                &format_args!("{}", self.slv_status_bitlen().bits()),
-            )
+            .field("slv_rdbuf_dummy_en", &self.slv_rdbuf_dummy_en())
+            .field("slv_wrbuf_dummy_en", &self.slv_wrbuf_dummy_en())
+            .field("slv_rdsta_dummy_en", &self.slv_rdsta_dummy_en())
+            .field("slv_wrsta_dummy_en", &self.slv_wrsta_dummy_en())
+            .field("slv_wr_addr_bitlen", &self.slv_wr_addr_bitlen())
+            .field("slv_rd_addr_bitlen", &self.slv_rd_addr_bitlen())
+            .field("slv_status_readback", &self.slv_status_readback())
+            .field("slv_status_fast_en", &self.slv_status_fast_en())
+            .field("slv_status_bitlen", &self.slv_status_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - In the slave mode it is the enable bit of dummy phase for read-buffer operations."]
     #[inline(always)]
diff --git a/esp32/src/spi0/slave2.rs b/esp32/src/spi0/slave2.rs
index 98e33ff006..d64cdd34e2 100644
--- a/esp32/src/spi0/slave2.rs
+++ b/esp32/src/spi0/slave2.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE2")
-            .field(
-                "slv_rdsta_dummy_cyclelen",
-                &format_args!("{}", self.slv_rdsta_dummy_cyclelen().bits()),
-            )
-            .field(
-                "slv_wrsta_dummy_cyclelen",
-                &format_args!("{}", self.slv_wrsta_dummy_cyclelen().bits()),
-            )
-            .field(
-                "slv_rdbuf_dummy_cyclelen",
-                &format_args!("{}", self.slv_rdbuf_dummy_cyclelen().bits()),
-            )
-            .field(
-                "slv_wrbuf_dummy_cyclelen",
-                &format_args!("{}", self.slv_wrbuf_dummy_cyclelen().bits()),
-            )
+            .field("slv_rdsta_dummy_cyclelen", &self.slv_rdsta_dummy_cyclelen())
+            .field("slv_wrsta_dummy_cyclelen", &self.slv_wrsta_dummy_cyclelen())
+            .field("slv_rdbuf_dummy_cyclelen", &self.slv_rdbuf_dummy_cyclelen())
+            .field("slv_wrbuf_dummy_cyclelen", &self.slv_wrbuf_dummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1)."]
     #[inline(always)]
diff --git a/esp32/src/spi0/slave3.rs b/esp32/src/spi0/slave3.rs
index 719ffb8198..4e9ec8cd64 100644
--- a/esp32/src/spi0/slave3.rs
+++ b/esp32/src/spi0/slave3.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE3")
-            .field(
-                "slv_rdbuf_cmd_value",
-                &format_args!("{}", self.slv_rdbuf_cmd_value().bits()),
-            )
-            .field(
-                "slv_wrbuf_cmd_value",
-                &format_args!("{}", self.slv_wrbuf_cmd_value().bits()),
-            )
-            .field(
-                "slv_rdsta_cmd_value",
-                &format_args!("{}", self.slv_rdsta_cmd_value().bits()),
-            )
-            .field(
-                "slv_wrsta_cmd_value",
-                &format_args!("{}", self.slv_wrsta_cmd_value().bits()),
-            )
+            .field("slv_rdbuf_cmd_value", &self.slv_rdbuf_cmd_value())
+            .field("slv_wrbuf_cmd_value", &self.slv_wrbuf_cmd_value())
+            .field("slv_rdsta_cmd_value", &self.slv_rdsta_cmd_value())
+            .field("slv_wrsta_cmd_value", &self.slv_wrsta_cmd_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In the slave mode it is the value of read-buffer command."]
     #[inline(always)]
diff --git a/esp32/src/spi0/slv_rd_bit.rs b/esp32/src/spi0/slv_rd_bit.rs
index a29e4f9c86..9814bf3763 100644
--- a/esp32/src/spi0/slv_rd_bit.rs
+++ b/esp32/src/spi0/slv_rd_bit.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLV_RD_BIT")
-            .field(
-                "slv_rdata_bit",
-                &format_args!("{}", self.slv_rdata_bit().bits()),
-            )
+            .field("slv_rdata_bit", &self.slv_rdata_bit())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLV_RD_BIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - In the slave mode it is the bit length of read data. The value is the length - 1."]
     #[inline(always)]
diff --git a/esp32/src/spi0/slv_rdbuf_dlen.rs b/esp32/src/spi0/slv_rdbuf_dlen.rs
index b238cde338..ec96972fac 100644
--- a/esp32/src/spi0/slv_rdbuf_dlen.rs
+++ b/esp32/src/spi0/slv_rdbuf_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLV_RDBUF_DLEN")
-            .field(
-                "slv_rdbuf_dbitlen",
-                &format_args!("{}", self.slv_rdbuf_dbitlen().bits()),
-            )
+            .field("slv_rdbuf_dbitlen", &self.slv_rdbuf_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLV_RDBUF_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32/src/spi0/slv_wr_status.rs b/esp32/src/spi0/slv_wr_status.rs
index d57892f7d5..5fb3c478c2 100644
--- a/esp32/src/spi0/slv_wr_status.rs
+++ b/esp32/src/spi0/slv_wr_status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLV_WR_STATUS")
-            .field("slv_wr_st", &format_args!("{}", self.slv_wr_st().bits()))
+            .field("slv_wr_st", &self.slv_wr_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLV_WR_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition."]
     #[inline(always)]
diff --git a/esp32/src/spi0/slv_wrbuf_dlen.rs b/esp32/src/spi0/slv_wrbuf_dlen.rs
index b998529e6c..b0e504bfa6 100644
--- a/esp32/src/spi0/slv_wrbuf_dlen.rs
+++ b/esp32/src/spi0/slv_wrbuf_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLV_WRBUF_DLEN")
-            .field(
-                "slv_wrbuf_dbitlen",
-                &format_args!("{}", self.slv_wrbuf_dbitlen().bits()),
-            )
+            .field("slv_wrbuf_dbitlen", &self.slv_wrbuf_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLV_WRBUF_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32/src/spi0/sram_cmd.rs b/esp32/src/spi0/sram_cmd.rs
index 3237261d3a..25b74ecfc9 100644
--- a/esp32/src/spi0/sram_cmd.rs
+++ b/esp32/src/spi0/sram_cmd.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_CMD")
-            .field("sram_dio", &format_args!("{}", self.sram_dio().bit()))
-            .field("sram_qio", &format_args!("{}", self.sram_qio().bit()))
-            .field("sram_rstio", &format_args!("{}", self.sram_rstio().bit()))
+            .field("sram_dio", &self.sram_dio())
+            .field("sram_qio", &self.sram_qio())
+            .field("sram_rstio", &self.sram_rstio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done."]
     #[inline(always)]
diff --git a/esp32/src/spi0/sram_drd_cmd.rs b/esp32/src/spi0/sram_drd_cmd.rs
index 0d66c47810..b69d9f2d7f 100644
--- a/esp32/src/spi0/sram_drd_cmd.rs
+++ b/esp32/src/spi0/sram_drd_cmd.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("SRAM_DRD_CMD")
             .field(
                 "cache_sram_usr_rd_cmd_value",
-                &format_args!("{}", self.cache_sram_usr_rd_cmd_value().bits()),
+                &self.cache_sram_usr_rd_cmd_value(),
             )
             .field(
                 "cache_sram_usr_rd_cmd_bitlen",
-                &format_args!("{}", self.cache_sram_usr_rd_cmd_bitlen().bits()),
+                &self.cache_sram_usr_rd_cmd_bitlen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_DRD_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - For SPI0 When cache mode is enable it is the read command value of command phase for SRAM."]
     #[inline(always)]
diff --git a/esp32/src/spi0/sram_dwr_cmd.rs b/esp32/src/spi0/sram_dwr_cmd.rs
index 2e250767ce..abde249495 100644
--- a/esp32/src/spi0/sram_dwr_cmd.rs
+++ b/esp32/src/spi0/sram_dwr_cmd.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("SRAM_DWR_CMD")
             .field(
                 "cache_sram_usr_wr_cmd_value",
-                &format_args!("{}", self.cache_sram_usr_wr_cmd_value().bits()),
+                &self.cache_sram_usr_wr_cmd_value(),
             )
             .field(
                 "cache_sram_usr_wr_cmd_bitlen",
-                &format_args!("{}", self.cache_sram_usr_wr_cmd_bitlen().bits()),
+                &self.cache_sram_usr_wr_cmd_bitlen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_DWR_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - For SPI0 When cache mode is enable it is the write command value of command phase for SRAM."]
     #[inline(always)]
diff --git a/esp32/src/spi0/tx_crc.rs b/esp32/src/spi0/tx_crc.rs
index e6c9bc3ad6..19ab9286ba 100644
--- a/esp32/src/spi0/tx_crc.rs
+++ b/esp32/src/spi0/tx_crc.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - For SPI1 the value of crc32 for 256 bits data."]
     #[inline(always)]
diff --git a/esp32/src/spi0/user.rs b/esp32/src/spi0/user.rs
index 365e96ccbe..6869e9a84f 100644
--- a/esp32/src/spi0/user.rs
+++ b/esp32/src/spi0/user.rs
@@ -251,78 +251,36 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("doutdin", &format_args!("{}", self.doutdin().bit()))
-            .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
-            .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
-            .field("ck_i_edge", &format_args!("{}", self.ck_i_edge().bit()))
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field(
-                "rd_byte_order",
-                &format_args!("{}", self.rd_byte_order().bit()),
-            )
-            .field(
-                "wr_byte_order",
-                &format_args!("{}", self.wr_byte_order().bit()),
-            )
-            .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
-            .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
-            .field("fwrite_dio", &format_args!("{}", self.fwrite_dio().bit()))
-            .field("fwrite_qio", &format_args!("{}", self.fwrite_qio().bit()))
-            .field("sio", &format_args!("{}", self.sio().bit()))
-            .field(
-                "usr_hold_pol",
-                &format_args!("{}", self.usr_hold_pol().bit()),
-            )
-            .field(
-                "usr_dout_hold",
-                &format_args!("{}", self.usr_dout_hold().bit()),
-            )
-            .field(
-                "usr_din_hold",
-                &format_args!("{}", self.usr_din_hold().bit()),
-            )
-            .field(
-                "usr_dummy_hold",
-                &format_args!("{}", self.usr_dummy_hold().bit()),
-            )
-            .field(
-                "usr_addr_hold",
-                &format_args!("{}", self.usr_addr_hold().bit()),
-            )
-            .field(
-                "usr_cmd_hold",
-                &format_args!("{}", self.usr_cmd_hold().bit()),
-            )
-            .field(
-                "usr_prep_hold",
-                &format_args!("{}", self.usr_prep_hold().bit()),
-            )
-            .field(
-                "usr_miso_highpart",
-                &format_args!("{}", self.usr_miso_highpart().bit()),
-            )
-            .field(
-                "usr_mosi_highpart",
-                &format_args!("{}", self.usr_mosi_highpart().bit()),
-            )
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
-            .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
-            .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
-            .field("usr_command", &format_args!("{}", self.usr_command().bit()))
+            .field("doutdin", &self.doutdin())
+            .field("cs_hold", &self.cs_hold())
+            .field("cs_setup", &self.cs_setup())
+            .field("ck_i_edge", &self.ck_i_edge())
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("rd_byte_order", &self.rd_byte_order())
+            .field("wr_byte_order", &self.wr_byte_order())
+            .field("fwrite_dual", &self.fwrite_dual())
+            .field("fwrite_quad", &self.fwrite_quad())
+            .field("fwrite_dio", &self.fwrite_dio())
+            .field("fwrite_qio", &self.fwrite_qio())
+            .field("sio", &self.sio())
+            .field("usr_hold_pol", &self.usr_hold_pol())
+            .field("usr_dout_hold", &self.usr_dout_hold())
+            .field("usr_din_hold", &self.usr_din_hold())
+            .field("usr_dummy_hold", &self.usr_dummy_hold())
+            .field("usr_addr_hold", &self.usr_addr_hold())
+            .field("usr_cmd_hold", &self.usr_cmd_hold())
+            .field("usr_prep_hold", &self.usr_prep_hold())
+            .field("usr_miso_highpart", &self.usr_miso_highpart())
+            .field("usr_mosi_highpart", &self.usr_mosi_highpart())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_mosi", &self.usr_mosi())
+            .field("usr_miso", &self.usr_miso())
+            .field("usr_dummy", &self.usr_dummy())
+            .field("usr_addr", &self.usr_addr())
+            .field("usr_command", &self.usr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32/src/spi0/user1.rs b/esp32/src/spi0/user1.rs
index ca5c42ea04..52272cc8c6 100644
--- a/esp32/src/spi0/user1.rs
+++ b/esp32/src/spi0/user1.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
     #[inline(always)]
diff --git a/esp32/src/spi0/user2.rs b/esp32/src/spi0/user2.rs
index c6f4649535..860f0be363 100644
--- a/esp32/src/spi0/user2.rs
+++ b/esp32/src/spi0/user2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command."]
     #[inline(always)]
diff --git a/esp32/src/spi0/w.rs b/esp32/src/spi0/w.rs
index 09f540b746..4cf82c8334 100644
--- a/esp32/src/spi0/w.rs
+++ b/esp32/src/spi0/w.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("W")
-            .field("buf", &format_args!("{}", self.buf().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<W_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("W").field("buf", &self.buf()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/timg0/int_ena_timers.rs b/esp32/src/timg0/int_ena_timers.rs
index 66db17b8d9..10a5109d0e 100644
--- a/esp32/src/timg0/int_ena_timers.rs
+++ b/esp32/src/timg0/int_ena_timers.rs
@@ -55,19 +55,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("t1", &format_args!("{}", self.t1().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("lact", &format_args!("{}", self.lact().bit()))
+            .field("t0", &self.t0())
+            .field("t1", &self.t1())
+            .field("wdt", &self.wdt())
+            .field("lact", &self.lact())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "interrupt when timer(0-1) alarm"]
     #[doc = ""]
diff --git a/esp32/src/timg0/int_raw_timers.rs b/esp32/src/timg0/int_raw_timers.rs
index 6ed30d0e9a..629bacfc19 100644
--- a/esp32/src/timg0/int_raw_timers.rs
+++ b/esp32/src/timg0/int_raw_timers.rs
@@ -47,19 +47,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("t1", &format_args!("{}", self.t1().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("lact", &format_args!("{}", self.lact().bit()))
+            .field("t0", &self.t0())
+            .field("t1", &self.t1())
+            .field("wdt", &self.wdt())
+            .field("lact", &self.lact())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_TIMERS_SPEC;
 impl crate::RegisterSpec for INT_RAW_TIMERS_SPEC {
diff --git a/esp32/src/timg0/int_st_timers.rs b/esp32/src/timg0/int_st_timers.rs
index d2e35077fe..1729ae2149 100644
--- a/esp32/src/timg0/int_st_timers.rs
+++ b/esp32/src/timg0/int_st_timers.rs
@@ -47,19 +47,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("t1", &format_args!("{}", self.t1().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("lact", &format_args!("{}", self.lact().bit()))
+            .field("t0", &self.t0())
+            .field("t1", &self.t1())
+            .field("wdt", &self.wdt())
+            .field("lact", &self.lact())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_TIMERS_SPEC;
 impl crate::RegisterSpec for INT_ST_TIMERS_SPEC {
diff --git a/esp32/src/timg0/lactalarmhi.rs b/esp32/src/timg0/lactalarmhi.rs
index 7fa11079d2..75e652f23b 100644
--- a/esp32/src/timg0/lactalarmhi.rs
+++ b/esp32/src/timg0/lactalarmhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LACTALARMHI")
-            .field("alarm_hi", &format_args!("{}", self.alarm_hi().bits()))
+            .field("alarm_hi", &self.alarm_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTALARMHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/timg0/lactalarmlo.rs b/esp32/src/timg0/lactalarmlo.rs
index b235158b65..eff8867909 100644
--- a/esp32/src/timg0/lactalarmlo.rs
+++ b/esp32/src/timg0/lactalarmlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LACTALARMLO")
-            .field("alarm_lo", &format_args!("{}", self.alarm_lo().bits()))
+            .field("alarm_lo", &self.alarm_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTALARMLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/timg0/lactconfig.rs b/esp32/src/timg0/lactconfig.rs
index 32291a5c00..4cd92c4b6e 100644
--- a/esp32/src/timg0/lactconfig.rs
+++ b/esp32/src/timg0/lactconfig.rs
@@ -98,28 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LACTCONFIG")
-            .field("rtc_only", &format_args!("{}", self.rtc_only().bit()))
-            .field("cpst_en", &format_args!("{}", self.cpst_en().bit()))
-            .field("lac_en", &format_args!("{}", self.lac_en().bit()))
-            .field("alarm_en", &format_args!("{}", self.alarm_en().bit()))
-            .field(
-                "level_int_en",
-                &format_args!("{}", self.level_int_en().bit()),
-            )
-            .field("edge_int_en", &format_args!("{}", self.edge_int_en().bit()))
-            .field("divider", &format_args!("{}", self.divider().bits()))
-            .field("autoreload", &format_args!("{}", self.autoreload().bit()))
-            .field("increase", &format_args!("{}", self.increase().bit()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("rtc_only", &self.rtc_only())
+            .field("cpst_en", &self.cpst_en())
+            .field("lac_en", &self.lac_en())
+            .field("alarm_en", &self.alarm_en())
+            .field("level_int_en", &self.level_int_en())
+            .field("edge_int_en", &self.edge_int_en())
+            .field("divider", &self.divider())
+            .field("autoreload", &self.autoreload())
+            .field("increase", &self.increase())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTCONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7"]
     #[inline(always)]
diff --git a/esp32/src/timg0/lacthi.rs b/esp32/src/timg0/lacthi.rs
index f1ae17b3ea..e71ceb1e7c 100644
--- a/esp32/src/timg0/lacthi.rs
+++ b/esp32/src/timg0/lacthi.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LACTHI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LACTHI").field("hi", &self.hi()).finish()
     }
 }
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lacthi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/timg0/lactlo.rs b/esp32/src/timg0/lactlo.rs
index 064ce69700..590a9a3291 100644
--- a/esp32/src/timg0/lactlo.rs
+++ b/esp32/src/timg0/lactlo.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LACTLO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LACTLO").field("lo", &self.lo()).finish()
     }
 }
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lactlo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/timg0/lactloadhi.rs b/esp32/src/timg0/lactloadhi.rs
index c91187db0f..f339a4080d 100644
--- a/esp32/src/timg0/lactloadhi.rs
+++ b/esp32/src/timg0/lactloadhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LACTLOADHI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTLOADHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/timg0/lactloadlo.rs b/esp32/src/timg0/lactloadlo.rs
index 3fa9ca531b..b7d43bccde 100644
--- a/esp32/src/timg0/lactloadlo.rs
+++ b/esp32/src/timg0/lactloadlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LACTLOADLO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTLOADLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32/src/timg0/lactrtc.rs b/esp32/src/timg0/lactrtc.rs
index cbdd3140e2..2ca5ac4302 100644
--- a/esp32/src/timg0/lactrtc.rs
+++ b/esp32/src/timg0/lactrtc.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LACTRTC")
-            .field(
-                "rtc_step_len",
-                &format_args!("{}", self.rtc_step_len().bits()),
-            )
+            .field("rtc_step_len", &self.rtc_step_len())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTRTC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 6:31"]
     #[inline(always)]
diff --git a/esp32/src/timg0/ntimers_date.rs b/esp32/src/timg0/ntimers_date.rs
index 5227ebe053..781e1d11c6 100644
--- a/esp32/src/timg0/ntimers_date.rs
+++ b/esp32/src/timg0/ntimers_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NTIMERS_DATE")
-            .field(
-                "ntimers_date",
-                &format_args!("{}", self.ntimers_date().bits()),
-            )
+            .field("ntimers_date", &self.ntimers_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NTIMERS_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version of this regfile"]
     #[inline(always)]
diff --git a/esp32/src/timg0/rtccalicfg.rs b/esp32/src/timg0/rtccalicfg.rs
index 6511249c37..b1692e438b 100644
--- a/esp32/src/timg0/rtccalicfg.rs
+++ b/esp32/src/timg0/rtccalicfg.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG")
-            .field(
-                "rtc_cali_start_cycling",
-                &format_args!("{}", self.rtc_cali_start_cycling().bit()),
-            )
-            .field(
-                "rtc_cali_clk_sel",
-                &format_args!("{}", self.rtc_cali_clk_sel().bits()),
-            )
-            .field(
-                "rtc_cali_rdy",
-                &format_args!("{}", self.rtc_cali_rdy().bit()),
-            )
-            .field(
-                "rtc_cali_max",
-                &format_args!("{}", self.rtc_cali_max().bits()),
-            )
-            .field(
-                "rtc_cali_start",
-                &format_args!("{}", self.rtc_cali_start().bit()),
-            )
+            .field("rtc_cali_start_cycling", &self.rtc_cali_start_cycling())
+            .field("rtc_cali_clk_sel", &self.rtc_cali_clk_sel())
+            .field("rtc_cali_rdy", &self.rtc_cali_rdy())
+            .field("rtc_cali_max", &self.rtc_cali_max())
+            .field("rtc_cali_start", &self.rtc_cali_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12"]
     #[inline(always)]
diff --git a/esp32/src/timg0/rtccalicfg1.rs b/esp32/src/timg0/rtccalicfg1.rs
index 0d2a10e0da..a6bbd91f3f 100644
--- a/esp32/src/timg0/rtccalicfg1.rs
+++ b/esp32/src/timg0/rtccalicfg1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG1")
-            .field(
-                "rtc_cali_value",
-                &format_args!("{}", self.rtc_cali_value().bits()),
-            )
+            .field("rtc_cali_value", &self.rtc_cali_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtccalicfg1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTCCALICFG1_SPEC;
 impl crate::RegisterSpec for RTCCALICFG1_SPEC {
diff --git a/esp32/src/timg0/t/alarmhi.rs b/esp32/src/timg0/t/alarmhi.rs
index e6cca62faf..bc19d414bf 100644
--- a/esp32/src/timg0/t/alarmhi.rs
+++ b/esp32/src/timg0/t/alarmhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMHI")
-            .field("alarm_hi", &format_args!("{}", self.alarm_hi().bits()))
+            .field("alarm_hi", &self.alarm_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Timer 0 time-base counter value higher 32 bits that will trigger the alarm"]
     #[inline(always)]
diff --git a/esp32/src/timg0/t/alarmlo.rs b/esp32/src/timg0/t/alarmlo.rs
index 8bcc067073..2c5cf31e4c 100644
--- a/esp32/src/timg0/t/alarmlo.rs
+++ b/esp32/src/timg0/t/alarmlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMLO")
-            .field("alarm_lo", &format_args!("{}", self.alarm_lo().bits()))
+            .field("alarm_lo", &self.alarm_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Timer 0 time-base counter value lower 32 bits that will trigger the alarm"]
     #[inline(always)]
diff --git a/esp32/src/timg0/t/config.rs b/esp32/src/timg0/t/config.rs
index a9da49f395..42fd0ef6d6 100644
--- a/esp32/src/timg0/t/config.rs
+++ b/esp32/src/timg0/t/config.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG")
-            .field("alarm_en", &format_args!("{}", self.alarm_en().bit()))
-            .field(
-                "level_int_en",
-                &format_args!("{}", self.level_int_en().bit()),
-            )
-            .field("edge_int_en", &format_args!("{}", self.edge_int_en().bit()))
-            .field("divider", &format_args!("{}", self.divider().bits()))
-            .field("autoreload", &format_args!("{}", self.autoreload().bit()))
-            .field("increase", &format_args!("{}", self.increase().bit()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("alarm_en", &self.alarm_en())
+            .field("level_int_en", &self.level_int_en())
+            .field("edge_int_en", &self.edge_int_en())
+            .field("divider", &self.divider())
+            .field("autoreload", &self.autoreload())
+            .field("increase", &self.increase())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 10 - When set alarm is enabled"]
     #[inline(always)]
diff --git a/esp32/src/timg0/t/hi.rs b/esp32/src/timg0/t/hi.rs
index 5305396151..a434d567d1 100644
--- a/esp32/src/timg0/t/hi.rs
+++ b/esp32/src/timg0/t/hi.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
     }
 }
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/timg0/t/lo.rs b/esp32/src/timg0/t/lo.rs
index 5f85d5f7dd..7a891f3b0b 100644
--- a/esp32/src/timg0/t/lo.rs
+++ b/esp32/src/timg0/t/lo.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
     }
 }
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32/src/timg0/t/loadhi.rs b/esp32/src/timg0/t/loadhi.rs
index d8e69d5f70..0882cd9a90 100644
--- a/esp32/src/timg0/t/loadhi.rs
+++ b/esp32/src/timg0/t/loadhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADHI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - higher 32 bits of the value that will load into timer 0 time-base counter"]
     #[inline(always)]
diff --git a/esp32/src/timg0/t/loadlo.rs b/esp32/src/timg0/t/loadlo.rs
index 54f26e5b75..ed801e8870 100644
--- a/esp32/src/timg0/t/loadlo.rs
+++ b/esp32/src/timg0/t/loadlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADLO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Lower 32 bits of the value that will load into timer 0 time-base counter"]
     #[inline(always)]
diff --git a/esp32/src/timg0/t/update.rs b/esp32/src/timg0/t/update.rs
index fc82d04eca..d1612be335 100644
--- a/esp32/src/timg0/t/update.rs
+++ b/esp32/src/timg0/t/update.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE")
-            .field("update", &format_args!("{}", self.update().bit()))
+            .field("update", &self.update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)"]
     #[inline(always)]
diff --git a/esp32/src/timg0/timgclk.rs b/esp32/src/timg0/timgclk.rs
index 8e12279c00..5f6fbc0f55 100644
--- a/esp32/src/timg0/timgclk.rs
+++ b/esp32/src/timg0/timgclk.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMGCLK")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMGCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Force clock enable for this regfile"]
     #[inline(always)]
diff --git a/esp32/src/timg0/wdtconfig0.rs b/esp32/src/timg0/wdtconfig0.rs
index fa0f3e728a..ca2b3fdd3b 100644
--- a/esp32/src/timg0/wdtconfig0.rs
+++ b/esp32/src/timg0/wdtconfig0.rs
@@ -453,40 +453,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG0")
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field(
-                "wdt_level_int_en",
-                &format_args!("{}", self.wdt_level_int_en().bit()),
-            )
-            .field(
-                "wdt_edge_int_en",
-                &format_args!("{}", self.wdt_edge_int_en().bit()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_level_int_en", &self.wdt_level_int_en())
+            .field("wdt_edge_int_en", &self.wdt_edge_int_en())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 14 - When set flash boot protection is enabled"]
     #[inline(always)]
diff --git a/esp32/src/timg0/wdtconfig1.rs b/esp32/src/timg0/wdtconfig1.rs
index a4c495d751..25e36a86bf 100644
--- a/esp32/src/timg0/wdtconfig1.rs
+++ b/esp32/src/timg0/wdtconfig1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG1")
-            .field(
-                "wdt_clk_prescale",
-                &format_args!("{}", self.wdt_clk_prescale().bits()),
-            )
+            .field("wdt_clk_prescale", &self.wdt_clk_prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - SWDT clock prescale value. Period = 12.5ns * value stored in this register"]
     #[inline(always)]
diff --git a/esp32/src/timg0/wdtconfig2.rs b/esp32/src/timg0/wdtconfig2.rs
index 496335cb9d..132ae3c01c 100644
--- a/esp32/src/timg0/wdtconfig2.rs
+++ b/esp32/src/timg0/wdtconfig2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG2")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 0 timeout value in SWDT clock cycles"]
     #[inline(always)]
diff --git a/esp32/src/timg0/wdtconfig3.rs b/esp32/src/timg0/wdtconfig3.rs
index 49cbe87575..e9d1cb19e6 100644
--- a/esp32/src/timg0/wdtconfig3.rs
+++ b/esp32/src/timg0/wdtconfig3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG3")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 1 timeout value in SWDT clock cycles"]
     #[inline(always)]
diff --git a/esp32/src/timg0/wdtconfig4.rs b/esp32/src/timg0/wdtconfig4.rs
index 680870fe25..24153f0ea9 100644
--- a/esp32/src/timg0/wdtconfig4.rs
+++ b/esp32/src/timg0/wdtconfig4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG4")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 2 timeout value in SWDT clock cycles"]
     #[inline(always)]
diff --git a/esp32/src/timg0/wdtconfig5.rs b/esp32/src/timg0/wdtconfig5.rs
index d65eddb77e..2152a6552e 100644
--- a/esp32/src/timg0/wdtconfig5.rs
+++ b/esp32/src/timg0/wdtconfig5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG5")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 3 timeout value in SWDT clock cycles"]
     #[inline(always)]
diff --git a/esp32/src/timg0/wdtwprotect.rs b/esp32/src/timg0/wdtwprotect.rs
index 9eda540556..a0a374b9e2 100644
--- a/esp32/src/timg0/wdtwprotect.rs
+++ b/esp32/src/timg0/wdtwprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTWPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTWPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - If change its value from default then write protection is on."]
     #[inline(always)]
diff --git a/esp32/src/twai0/arb_lost_cap.rs b/esp32/src/twai0/arb_lost_cap.rs
index 20ab158c4b..02b4812ac4 100644
--- a/esp32/src/twai0/arb_lost_cap.rs
+++ b/esp32/src/twai0/arb_lost_cap.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_LOST_CAP")
-            .field(
-                "arb_lost_cap",
-                &format_args!("{}", self.arb_lost_cap().bits()),
-            )
+            .field("arb_lost_cap", &self.arb_lost_cap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_LOST_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Arbitration Lost Capture Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_lost_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ARB_LOST_CAP_SPEC;
 impl crate::RegisterSpec for ARB_LOST_CAP_SPEC {
diff --git a/esp32/src/twai0/bus_timing_0.rs b/esp32/src/twai0/bus_timing_0.rs
index a30a783a51..2a0f95ed4b 100644
--- a/esp32/src/twai0/bus_timing_0.rs
+++ b/esp32/src/twai0/bus_timing_0.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMING_0")
-            .field("baud_presc", &format_args!("{}", self.baud_presc().bits()))
-            .field(
-                "sync_jump_width",
-                &format_args!("{}", self.sync_jump_width().bits()),
-            )
+            .field("baud_presc", &self.baud_presc())
+            .field("sync_jump_width", &self.sync_jump_width())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMING_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Baud Rate Prescaler, determines the frequency dividing ratio."]
     #[inline(always)]
diff --git a/esp32/src/twai0/bus_timing_1.rs b/esp32/src/twai0/bus_timing_1.rs
index ec698b25b8..89a5dcc905 100644
--- a/esp32/src/twai0/bus_timing_1.rs
+++ b/esp32/src/twai0/bus_timing_1.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMING_1")
-            .field("time_seg1", &format_args!("{}", self.time_seg1().bits()))
-            .field("time_seg2", &format_args!("{}", self.time_seg2().bits()))
-            .field("time_samp", &format_args!("{}", self.time_samp().bit()))
+            .field("time_seg1", &self.time_seg1())
+            .field("time_seg2", &self.time_seg2())
+            .field("time_samp", &self.time_samp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMING_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The width of PBS1."]
     #[inline(always)]
diff --git a/esp32/src/twai0/clock_divider.rs b/esp32/src/twai0/clock_divider.rs
index 9d5176aca5..3021eab737 100644
--- a/esp32/src/twai0/clock_divider.rs
+++ b/esp32/src/twai0/clock_divider.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_DIVIDER")
-            .field("cd", &format_args!("{}", self.cd().bits()))
-            .field("clock_off", &format_args!("{}", self.clock_off().bit()))
+            .field("cd", &self.cd())
+            .field("clock_off", &self.clock_off())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_DIVIDER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - These bits are used to configure frequency dividing coefficients of the external CLKOUT pin."]
     #[inline(always)]
diff --git a/esp32/src/twai0/data_0.rs b/esp32/src/twai0/data_0.rs
index 921ebf3ab0..d87f222f23 100644
--- a/esp32/src/twai0/data_0.rs
+++ b/esp32/src/twai0/data_0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_0")
-            .field("tx_byte_0", &format_args!("{}", self.tx_byte_0().bits()))
+            .field("tx_byte_0", &self.tx_byte_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32/src/twai0/data_1.rs b/esp32/src/twai0/data_1.rs
index aacde9f161..1e7ca2029e 100644
--- a/esp32/src/twai0/data_1.rs
+++ b/esp32/src/twai0/data_1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_1")
-            .field("tx_byte_1", &format_args!("{}", self.tx_byte_1().bits()))
+            .field("tx_byte_1", &self.tx_byte_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32/src/twai0/data_10.rs b/esp32/src/twai0/data_10.rs
index d978cb608a..77ea6c46e1 100644
--- a/esp32/src/twai0/data_10.rs
+++ b/esp32/src/twai0/data_10.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_10")
-            .field("tx_byte_10", &format_args!("{}", self.tx_byte_10().bits()))
+            .field("tx_byte_10", &self.tx_byte_10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stored the 10th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32/src/twai0/data_11.rs b/esp32/src/twai0/data_11.rs
index 69b3c01179..ea0f6a7d35 100644
--- a/esp32/src/twai0/data_11.rs
+++ b/esp32/src/twai0/data_11.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_11")
-            .field("tx_byte_11", &format_args!("{}", self.tx_byte_11().bits()))
+            .field("tx_byte_11", &self.tx_byte_11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stored the 11th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32/src/twai0/data_12.rs b/esp32/src/twai0/data_12.rs
index be60409250..d8afde2384 100644
--- a/esp32/src/twai0/data_12.rs
+++ b/esp32/src/twai0/data_12.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_12")
-            .field("tx_byte_12", &format_args!("{}", self.tx_byte_12().bits()))
+            .field("tx_byte_12", &self.tx_byte_12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stored the 12th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32/src/twai0/data_2.rs b/esp32/src/twai0/data_2.rs
index 8dfbf55812..f993610525 100644
--- a/esp32/src/twai0/data_2.rs
+++ b/esp32/src/twai0/data_2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_2")
-            .field("tx_byte_2", &format_args!("{}", self.tx_byte_2().bits()))
+            .field("tx_byte_2", &self.tx_byte_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32/src/twai0/data_3.rs b/esp32/src/twai0/data_3.rs
index af279627a4..60075e6328 100644
--- a/esp32/src/twai0/data_3.rs
+++ b/esp32/src/twai0/data_3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_3")
-            .field("tx_byte_3", &format_args!("{}", self.tx_byte_3().bits()))
+            .field("tx_byte_3", &self.tx_byte_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32/src/twai0/data_4.rs b/esp32/src/twai0/data_4.rs
index b55cb89b50..d64e72daaa 100644
--- a/esp32/src/twai0/data_4.rs
+++ b/esp32/src/twai0/data_4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_4")
-            .field("tx_byte_4", &format_args!("{}", self.tx_byte_4().bits()))
+            .field("tx_byte_4", &self.tx_byte_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32/src/twai0/data_5.rs b/esp32/src/twai0/data_5.rs
index 81b906ce88..0378e6b32e 100644
--- a/esp32/src/twai0/data_5.rs
+++ b/esp32/src/twai0/data_5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_5")
-            .field("tx_byte_5", &format_args!("{}", self.tx_byte_5().bits()))
+            .field("tx_byte_5", &self.tx_byte_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32/src/twai0/data_6.rs b/esp32/src/twai0/data_6.rs
index 9ea130bcfc..0de8e69ce7 100644
--- a/esp32/src/twai0/data_6.rs
+++ b/esp32/src/twai0/data_6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_6")
-            .field("tx_byte_6", &format_args!("{}", self.tx_byte_6().bits()))
+            .field("tx_byte_6", &self.tx_byte_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32/src/twai0/data_7.rs b/esp32/src/twai0/data_7.rs
index 4081ec2628..0339194cea 100644
--- a/esp32/src/twai0/data_7.rs
+++ b/esp32/src/twai0/data_7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_7")
-            .field("tx_byte_7", &format_args!("{}", self.tx_byte_7().bits()))
+            .field("tx_byte_7", &self.tx_byte_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32/src/twai0/data_8.rs b/esp32/src/twai0/data_8.rs
index 29694983b1..09ffc85913 100644
--- a/esp32/src/twai0/data_8.rs
+++ b/esp32/src/twai0/data_8.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_8")
-            .field("tx_byte_8", &format_args!("{}", self.tx_byte_8().bits()))
+            .field("tx_byte_8", &self.tx_byte_8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stored the 8th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32/src/twai0/data_9.rs b/esp32/src/twai0/data_9.rs
index 6cb211c10e..60f9949a12 100644
--- a/esp32/src/twai0/data_9.rs
+++ b/esp32/src/twai0/data_9.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_9")
-            .field("tx_byte_9", &format_args!("{}", self.tx_byte_9().bits()))
+            .field("tx_byte_9", &self.tx_byte_9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stored the 9th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32/src/twai0/err_code_cap.rs b/esp32/src/twai0/err_code_cap.rs
index 77f4f8b361..f4ce2b4b16 100644
--- a/esp32/src/twai0/err_code_cap.rs
+++ b/esp32/src/twai0/err_code_cap.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERR_CODE_CAP")
-            .field(
-                "ecc_segment",
-                &format_args!("{}", self.ecc_segment().bits()),
-            )
-            .field(
-                "ecc_direction",
-                &format_args!("{}", self.ecc_direction().bit()),
-            )
-            .field("ecc_type", &format_args!("{}", self.ecc_type().bits()))
+            .field("ecc_segment", &self.ecc_segment())
+            .field("ecc_direction", &self.ecc_direction())
+            .field("ecc_type", &self.ecc_type())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERR_CODE_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Error Code Capture Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_code_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ERR_CODE_CAP_SPEC;
 impl crate::RegisterSpec for ERR_CODE_CAP_SPEC {
diff --git a/esp32/src/twai0/err_warning_limit.rs b/esp32/src/twai0/err_warning_limit.rs
index eaca9801b5..0197a2df38 100644
--- a/esp32/src/twai0/err_warning_limit.rs
+++ b/esp32/src/twai0/err_warning_limit.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERR_WARNING_LIMIT")
-            .field(
-                "err_warning_limit",
-                &format_args!("{}", self.err_warning_limit().bits()),
-            )
+            .field("err_warning_limit", &self.err_warning_limit())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERR_WARNING_LIMIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid)."]
     #[inline(always)]
diff --git a/esp32/src/twai0/int_ena.rs b/esp32/src/twai0/int_ena.rs
index 750cc94df5..01ac1eef65 100644
--- a/esp32/src/twai0/int_ena.rs
+++ b/esp32/src/twai0/int_ena.rs
@@ -71,37 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_int_ena", &format_args!("{}", self.rx_int_ena().bit()))
-            .field("tx_int_ena", &format_args!("{}", self.tx_int_ena().bit()))
-            .field(
-                "err_warn_int_ena",
-                &format_args!("{}", self.err_warn_int_ena().bit()),
-            )
-            .field(
-                "overrun_int_ena",
-                &format_args!("{}", self.overrun_int_ena().bit()),
-            )
-            .field(
-                "err_passive_int_ena",
-                &format_args!("{}", self.err_passive_int_ena().bit()),
-            )
-            .field(
-                "arb_lost_int_ena",
-                &format_args!("{}", self.arb_lost_int_ena().bit()),
-            )
-            .field(
-                "bus_err_int_ena",
-                &format_args!("{}", self.bus_err_int_ena().bit()),
-            )
+            .field("rx_int_ena", &self.rx_int_ena())
+            .field("tx_int_ena", &self.tx_int_ena())
+            .field("err_warn_int_ena", &self.err_warn_int_ena())
+            .field("overrun_int_ena", &self.overrun_int_ena())
+            .field("err_passive_int_ena", &self.err_passive_int_ena())
+            .field("arb_lost_int_ena", &self.arb_lost_int_ena())
+            .field("bus_err_int_ena", &self.bus_err_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable receive interrupt."]
     #[inline(always)]
diff --git a/esp32/src/twai0/int_raw.rs b/esp32/src/twai0/int_raw.rs
index bcb5a07717..fe0b2105a8 100644
--- a/esp32/src/twai0/int_raw.rs
+++ b/esp32/src/twai0/int_raw.rs
@@ -55,37 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_int_st", &format_args!("{}", self.rx_int_st().bit()))
-            .field("tx_int_st", &format_args!("{}", self.tx_int_st().bit()))
-            .field(
-                "err_warn_int_st",
-                &format_args!("{}", self.err_warn_int_st().bit()),
-            )
-            .field(
-                "overrun_int_st",
-                &format_args!("{}", self.overrun_int_st().bit()),
-            )
-            .field(
-                "err_passive_int_st",
-                &format_args!("{}", self.err_passive_int_st().bit()),
-            )
-            .field(
-                "arb_lost_int_st",
-                &format_args!("{}", self.arb_lost_int_st().bit()),
-            )
-            .field(
-                "bus_err_int_st",
-                &format_args!("{}", self.bus_err_int_st().bit()),
-            )
+            .field("rx_int_st", &self.rx_int_st())
+            .field("tx_int_st", &self.tx_int_st())
+            .field("err_warn_int_st", &self.err_warn_int_st())
+            .field("overrun_int_st", &self.overrun_int_st())
+            .field("err_passive_int_st", &self.err_passive_int_st())
+            .field("arb_lost_int_st", &self.arb_lost_int_st())
+            .field("bus_err_int_st", &self.bus_err_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32/src/twai0/mode.rs b/esp32/src/twai0/mode.rs
index dc3560c7e3..0d66f9a85c 100644
--- a/esp32/src/twai0/mode.rs
+++ b/esp32/src/twai0/mode.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODE")
-            .field("reset_mode", &format_args!("{}", self.reset_mode().bit()))
-            .field(
-                "listen_only_mode",
-                &format_args!("{}", self.listen_only_mode().bit()),
-            )
-            .field(
-                "self_test_mode",
-                &format_args!("{}", self.self_test_mode().bit()),
-            )
-            .field(
-                "rx_filter_mode",
-                &format_args!("{}", self.rx_filter_mode().bit()),
-            )
+            .field("reset_mode", &self.reset_mode())
+            .field("listen_only_mode", &self.listen_only_mode())
+            .field("self_test_mode", &self.self_test_mode())
+            .field("rx_filter_mode", &self.rx_filter_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode."]
     #[inline(always)]
diff --git a/esp32/src/twai0/rx_err_cnt.rs b/esp32/src/twai0/rx_err_cnt.rs
index 66bf5c5d52..9c05d16bf3 100644
--- a/esp32/src/twai0/rx_err_cnt.rs
+++ b/esp32/src/twai0/rx_err_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ERR_CNT")
-            .field("rx_err_cnt", &format_args!("{}", self.rx_err_cnt().bits()))
+            .field("rx_err_cnt", &self.rx_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ERR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The RX error counter register, reflects value changes under reception status."]
     #[inline(always)]
diff --git a/esp32/src/twai0/rx_message_cnt.rs b/esp32/src/twai0/rx_message_cnt.rs
index 606f9b251e..13ca2f8eb4 100644
--- a/esp32/src/twai0/rx_message_cnt.rs
+++ b/esp32/src/twai0/rx_message_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_MESSAGE_CNT")
-            .field(
-                "rx_message_counter",
-                &format_args!("{}", self.rx_message_counter().bits()),
-            )
+            .field("rx_message_counter", &self.rx_message_counter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_MESSAGE_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive Message Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_message_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_MESSAGE_CNT_SPEC;
 impl crate::RegisterSpec for RX_MESSAGE_CNT_SPEC {
diff --git a/esp32/src/twai0/status.rs b/esp32/src/twai0/status.rs
index c9d0dd58e5..9a577030bd 100644
--- a/esp32/src/twai0/status.rs
+++ b/esp32/src/twai0/status.rs
@@ -69,24 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rx_buf_st", &format_args!("{}", self.rx_buf_st().bit()))
-            .field("overrun_st", &format_args!("{}", self.overrun_st().bit()))
-            .field("tx_buf_st", &format_args!("{}", self.tx_buf_st().bit()))
-            .field("tx_complete", &format_args!("{}", self.tx_complete().bit()))
-            .field("rx_st", &format_args!("{}", self.rx_st().bit()))
-            .field("tx_st", &format_args!("{}", self.tx_st().bit()))
-            .field("err_st", &format_args!("{}", self.err_st().bit()))
-            .field("bus_off_st", &format_args!("{}", self.bus_off_st().bit()))
-            .field("miss_st", &format_args!("{}", self.miss_st().bit()))
+            .field("rx_buf_st", &self.rx_buf_st())
+            .field("overrun_st", &self.overrun_st())
+            .field("tx_buf_st", &self.tx_buf_st())
+            .field("tx_complete", &self.tx_complete())
+            .field("rx_st", &self.rx_st())
+            .field("tx_st", &self.tx_st())
+            .field("err_st", &self.err_st())
+            .field("bus_off_st", &self.bus_off_st())
+            .field("miss_st", &self.miss_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32/src/twai0/tx_err_cnt.rs b/esp32/src/twai0/tx_err_cnt.rs
index 3fb0a9d0ef..5d5b84441c 100644
--- a/esp32/src/twai0/tx_err_cnt.rs
+++ b/esp32/src/twai0/tx_err_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_ERR_CNT")
-            .field("tx_err_cnt", &format_args!("{}", self.tx_err_cnt().bits()))
+            .field("tx_err_cnt", &self.tx_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_ERR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The TX error counter register, reflects value changes under transmission status."]
     #[inline(always)]
diff --git a/esp32/src/uart0/at_cmd_char.rs b/esp32/src/uart0/at_cmd_char.rs
index 2350c66b06..0ec5a1f9b0 100644
--- a/esp32/src/uart0/at_cmd_char.rs
+++ b/esp32/src/uart0/at_cmd_char.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_CHAR")
-            .field(
-                "at_cmd_char",
-                &format_args!("{}", self.at_cmd_char().bits()),
-            )
-            .field("char_num", &format_args!("{}", self.char_num().bits()))
+            .field("at_cmd_char", &self.at_cmd_char())
+            .field("char_num", &self.char_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_CHAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."]
     #[inline(always)]
diff --git a/esp32/src/uart0/at_cmd_gaptout.rs b/esp32/src/uart0/at_cmd_gaptout.rs
index 3dc3d99cb1..176b9954da 100644
--- a/esp32/src/uart0/at_cmd_gaptout.rs
+++ b/esp32/src/uart0/at_cmd_gaptout.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_GAPTOUT")
-            .field(
-                "rx_gap_tout",
-                &format_args!("{}", self.rx_gap_tout().bits()),
-            )
+            .field("rx_gap_tout", &self.rx_gap_tout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_GAPTOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - This register is used to configure the duration time between the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars."]
     #[inline(always)]
diff --git a/esp32/src/uart0/at_cmd_postcnt.rs b/esp32/src/uart0/at_cmd_postcnt.rs
index 08c44fce54..a241527fe4 100644
--- a/esp32/src/uart0/at_cmd_postcnt.rs
+++ b/esp32/src/uart0/at_cmd_postcnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_POSTCNT")
-            .field(
-                "post_idle_num",
-                &format_args!("{}", self.post_idle_num().bits()),
-            )
+            .field("post_idle_num", &self.post_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_POSTCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - This register is used to configure the duration time between the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char."]
     #[inline(always)]
diff --git a/esp32/src/uart0/at_cmd_precnt.rs b/esp32/src/uart0/at_cmd_precnt.rs
index 0157afe2d0..1cc51fc43e 100644
--- a/esp32/src/uart0/at_cmd_precnt.rs
+++ b/esp32/src/uart0/at_cmd_precnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_PRECNT")
-            .field(
-                "pre_idle_num",
-                &format_args!("{}", self.pre_idle_num().bits()),
-            )
+            .field("pre_idle_num", &self.pre_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_PRECNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - This register is used to configure the idle duration time before the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char."]
     #[inline(always)]
diff --git a/esp32/src/uart0/autobaud.rs b/esp32/src/uart0/autobaud.rs
index 8991caa534..dbb54b4023 100644
--- a/esp32/src/uart0/autobaud.rs
+++ b/esp32/src/uart0/autobaud.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AUTOBAUD")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field(
-                "glitch_filt",
-                &format_args!("{}", self.glitch_filt().bits()),
-            )
+            .field("en", &self.en())
+            .field("glitch_filt", &self.glitch_filt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AUTOBAUD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enable bit for detecting baudrate."]
     #[inline(always)]
diff --git a/esp32/src/uart0/clkdiv.rs b/esp32/src/uart0/clkdiv.rs
index 7d252f4b72..9d2a5c4887 100644
--- a/esp32/src/uart0/clkdiv.rs
+++ b/esp32/src/uart0/clkdiv.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKDIV")
-            .field("clkdiv", &format_args!("{}", self.clkdiv().bits()))
-            .field("frag", &format_args!("{}", self.frag().bits()))
+            .field("clkdiv", &self.clkdiv())
+            .field("frag", &self.frag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKDIV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - The register value is the integer part of the frequency divider's factor."]
     #[inline(always)]
diff --git a/esp32/src/uart0/conf0.rs b/esp32/src/uart0/conf0.rs
index f2aa033616..efcd325f04 100644
--- a/esp32/src/uart0/conf0.rs
+++ b/esp32/src/uart0/conf0.rs
@@ -242,47 +242,35 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("parity", &format_args!("{}", self.parity().bit()))
-            .field("parity_en", &format_args!("{}", self.parity_en().bit()))
-            .field("bit_num", &format_args!("{}", self.bit_num().bits()))
-            .field(
-                "stop_bit_num",
-                &format_args!("{}", self.stop_bit_num().bits()),
-            )
-            .field("sw_rts", &format_args!("{}", self.sw_rts().bit()))
-            .field("sw_dtr", &format_args!("{}", self.sw_dtr().bit()))
-            .field("txd_brk", &format_args!("{}", self.txd_brk().bit()))
-            .field("irda_dplx", &format_args!("{}", self.irda_dplx().bit()))
-            .field("irda_tx_en", &format_args!("{}", self.irda_tx_en().bit()))
-            .field("irda_wctl", &format_args!("{}", self.irda_wctl().bit()))
-            .field("irda_tx_inv", &format_args!("{}", self.irda_tx_inv().bit()))
-            .field("irda_rx_inv", &format_args!("{}", self.irda_rx_inv().bit()))
-            .field("loopback", &format_args!("{}", self.loopback().bit()))
-            .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit()))
-            .field("irda_en", &format_args!("{}", self.irda_en().bit()))
-            .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit()))
-            .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit()))
-            .field("rxd_inv", &format_args!("{}", self.rxd_inv().bit()))
-            .field("cts_inv", &format_args!("{}", self.cts_inv().bit()))
-            .field("dsr_inv", &format_args!("{}", self.dsr_inv().bit()))
-            .field("txd_inv", &format_args!("{}", self.txd_inv().bit()))
-            .field("rts_inv", &format_args!("{}", self.rts_inv().bit()))
-            .field("dtr_inv", &format_args!("{}", self.dtr_inv().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("err_wr_mask", &format_args!("{}", self.err_wr_mask().bit()))
-            .field(
-                "tick_ref_always_on",
-                &format_args!("{}", self.tick_ref_always_on().bit()),
-            )
+            .field("parity", &self.parity())
+            .field("parity_en", &self.parity_en())
+            .field("bit_num", &self.bit_num())
+            .field("stop_bit_num", &self.stop_bit_num())
+            .field("sw_rts", &self.sw_rts())
+            .field("sw_dtr", &self.sw_dtr())
+            .field("txd_brk", &self.txd_brk())
+            .field("irda_dplx", &self.irda_dplx())
+            .field("irda_tx_en", &self.irda_tx_en())
+            .field("irda_wctl", &self.irda_wctl())
+            .field("irda_tx_inv", &self.irda_tx_inv())
+            .field("irda_rx_inv", &self.irda_rx_inv())
+            .field("loopback", &self.loopback())
+            .field("tx_flow_en", &self.tx_flow_en())
+            .field("irda_en", &self.irda_en())
+            .field("rxfifo_rst", &self.rxfifo_rst())
+            .field("txfifo_rst", &self.txfifo_rst())
+            .field("rxd_inv", &self.rxd_inv())
+            .field("cts_inv", &self.cts_inv())
+            .field("dsr_inv", &self.dsr_inv())
+            .field("txd_inv", &self.txd_inv())
+            .field("rts_inv", &self.rts_inv())
+            .field("dtr_inv", &self.dtr_inv())
+            .field("clk_en", &self.clk_en())
+            .field("err_wr_mask", &self.err_wr_mask())
+            .field("tick_ref_always_on", &self.tick_ref_always_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to configure the parity check mode. 0:even 1:odd"]
     #[inline(always)]
diff --git a/esp32/src/uart0/conf1.rs b/esp32/src/uart0/conf1.rs
index 93d488cb3f..af3cc26d64 100644
--- a/esp32/src/uart0/conf1.rs
+++ b/esp32/src/uart0/conf1.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "rxfifo_full_thrhd",
-                &format_args!("{}", self.rxfifo_full_thrhd().bits()),
-            )
-            .field(
-                "txfifo_empty_thrhd",
-                &format_args!("{}", self.txfifo_empty_thrhd().bits()),
-            )
-            .field(
-                "rx_flow_thrhd",
-                &format_args!("{}", self.rx_flow_thrhd().bits()),
-            )
-            .field("rx_flow_en", &format_args!("{}", self.rx_flow_en().bit()))
-            .field(
-                "rx_tout_thrhd",
-                &format_args!("{}", self.rx_tout_thrhd().bits()),
-            )
-            .field("rx_tout_en", &format_args!("{}", self.rx_tout_en().bit()))
+            .field("rxfifo_full_thrhd", &self.rxfifo_full_thrhd())
+            .field("txfifo_empty_thrhd", &self.txfifo_empty_thrhd())
+            .field("rx_flow_thrhd", &self.rx_flow_thrhd())
+            .field("rx_flow_en", &self.rx_flow_en())
+            .field("rx_tout_thrhd", &self.rx_tout_thrhd())
+            .field("rx_tout_en", &self.rx_tout_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - When receiver receives more data than its threshold value.receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd)."]
     #[inline(always)]
diff --git a/esp32/src/uart0/date.rs b/esp32/src/uart0/date.rs
index 5a35f60832..9a314ad5a8 100644
--- a/esp32/src/uart0/date.rs
+++ b/esp32/src/uart0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/uart0/fifo.rs b/esp32/src/uart0/fifo.rs
index 20c1fccd13..96bea90f25 100644
--- a/esp32/src/uart0/fifo.rs
+++ b/esp32/src/uart0/fifo.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO")
-            .field(
-                "rxfifo_rd_byte",
-                &format_args!("{}", self.rxfifo_rd_byte().bits()),
-            )
+            .field("rxfifo_rd_byte", &self.rxfifo_rd_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register stores one byte data read by rx fifo."]
     #[inline(always)]
diff --git a/esp32/src/uart0/flow_conf.rs b/esp32/src/uart0/flow_conf.rs
index 28bf010628..81bf85b327 100644
--- a/esp32/src/uart0/flow_conf.rs
+++ b/esp32/src/uart0/flow_conf.rs
@@ -62,24 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLOW_CONF")
-            .field(
-                "sw_flow_con_en",
-                &format_args!("{}", self.sw_flow_con_en().bit()),
-            )
-            .field("xonoff_del", &format_args!("{}", self.xonoff_del().bit()))
-            .field("force_xon", &format_args!("{}", self.force_xon().bit()))
-            .field("force_xoff", &format_args!("{}", self.force_xoff().bit()))
-            .field("send_xon", &format_args!("{}", self.send_xon().bit()))
-            .field("send_xoff", &format_args!("{}", self.send_xoff().bit()))
+            .field("sw_flow_con_en", &self.sw_flow_con_en())
+            .field("xonoff_del", &self.xonoff_del())
+            .field("force_xon", &self.force_xon())
+            .field("force_xoff", &self.force_xoff())
+            .field("send_xon", &self.send_xon())
+            .field("send_xoff", &self.send_xoff())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLOW_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff ."]
     #[inline(always)]
diff --git a/esp32/src/uart0/highpulse.rs b/esp32/src/uart0/highpulse.rs
index 8e1ff5910d..8feb1636d3 100644
--- a/esp32/src/uart0/highpulse.rs
+++ b/esp32/src/uart0/highpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIGHPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIGHPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`highpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIGHPULSE_SPEC;
 impl crate::RegisterSpec for HIGHPULSE_SPEC {
diff --git a/esp32/src/uart0/id.rs b/esp32/src/uart0/id.rs
index bb65be740c..a6e3189076 100644
--- a/esp32/src/uart0/id.rs
+++ b/esp32/src/uart0/id.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("ID")
-            .field("id", &format_args!("{}", self.id().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("ID").field("id", &self.id()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/uart0/idle_conf.rs b/esp32/src/uart0/idle_conf.rs
index 1ed80aab9d..e592c46b21 100644
--- a/esp32/src/uart0/idle_conf.rs
+++ b/esp32/src/uart0/idle_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDLE_CONF")
-            .field(
-                "rx_idle_thrhd",
-                &format_args!("{}", self.rx_idle_thrhd().bits()),
-            )
-            .field(
-                "tx_idle_num",
-                &format_args!("{}", self.tx_idle_num().bits()),
-            )
-            .field("tx_brk_num", &format_args!("{}", self.tx_brk_num().bits()))
+            .field("rx_idle_thrhd", &self.rx_idle_thrhd())
+            .field("tx_idle_num", &self.tx_idle_num())
+            .field("tx_brk_num", &self.tx_brk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - when receiver takes more time than this register value to receive a byte data. it will produce frame end signal for uhci to stop receiving data."]
     #[inline(always)]
diff --git a/esp32/src/uart0/int_ena.rs b/esp32/src/uart0/int_ena.rs
index dd2938ad8f..ae953fbfc9 100644
--- a/esp32/src/uart0/int_ena.rs
+++ b/esp32/src/uart0/int_ena.rs
@@ -179,49 +179,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
     #[inline(always)]
diff --git a/esp32/src/uart0/int_raw.rs b/esp32/src/uart0/int_raw.rs
index 25392d9e4b..053f804564 100644
--- a/esp32/src/uart0/int_raw.rs
+++ b/esp32/src/uart0/int_raw.rs
@@ -139,49 +139,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32/src/uart0/int_st.rs b/esp32/src/uart0/int_st.rs
index 46dd5b8577..c6b2740cf2 100644
--- a/esp32/src/uart0/int_st.rs
+++ b/esp32/src/uart0/int_st.rs
@@ -139,49 +139,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32/src/uart0/lowpulse.rs b/esp32/src/uart0/lowpulse.rs
index 33c167d6f3..bfa5b3663e 100644
--- a/esp32/src/uart0/lowpulse.rs
+++ b/esp32/src/uart0/lowpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOWPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOWPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lowpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOWPULSE_SPEC;
 impl crate::RegisterSpec for LOWPULSE_SPEC {
diff --git a/esp32/src/uart0/mem_cnt_status.rs b/esp32/src/uart0/mem_cnt_status.rs
index 5b9ae2aa61..39827a54bd 100644
--- a/esp32/src/uart0/mem_cnt_status.rs
+++ b/esp32/src/uart0/mem_cnt_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CNT_STATUS")
-            .field("rx_mem_cnt", &format_args!("{}", self.rx_mem_cnt().bits()))
-            .field("tx_mem_cnt", &format_args!("{}", self.tx_mem_cnt().bits()))
+            .field("rx_mem_cnt", &self.rx_mem_cnt())
+            .field("tx_mem_cnt", &self.tx_mem_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CNT_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_cnt_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_CNT_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_CNT_STATUS_SPEC {
diff --git a/esp32/src/uart0/mem_conf.rs b/esp32/src/uart0/mem_conf.rs
index fc0319e8b8..d99beb0cee 100644
--- a/esp32/src/uart0/mem_conf.rs
+++ b/esp32/src/uart0/mem_conf.rs
@@ -89,42 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field("mem_pd", &format_args!("{}", self.mem_pd().bit()))
-            .field("rx_size", &format_args!("{}", self.rx_size().bits()))
-            .field("tx_size", &format_args!("{}", self.tx_size().bits()))
-            .field(
-                "rx_flow_thrhd_h3",
-                &format_args!("{}", self.rx_flow_thrhd_h3().bits()),
-            )
-            .field(
-                "rx_tout_thrhd_h3",
-                &format_args!("{}", self.rx_tout_thrhd_h3().bits()),
-            )
-            .field(
-                "xon_threshold_h2",
-                &format_args!("{}", self.xon_threshold_h2().bits()),
-            )
-            .field(
-                "xoff_threshold_h2",
-                &format_args!("{}", self.xoff_threshold_h2().bits()),
-            )
-            .field(
-                "rx_mem_full_thrhd",
-                &format_args!("{}", self.rx_mem_full_thrhd().bits()),
-            )
-            .field(
-                "tx_mem_empty_thrhd",
-                &format_args!("{}", self.tx_mem_empty_thrhd().bits()),
-            )
+            .field("mem_pd", &self.mem_pd())
+            .field("rx_size", &self.rx_size())
+            .field("tx_size", &self.tx_size())
+            .field("rx_flow_thrhd_h3", &self.rx_flow_thrhd_h3())
+            .field("rx_tout_thrhd_h3", &self.rx_tout_thrhd_h3())
+            .field("xon_threshold_h2", &self.xon_threshold_h2())
+            .field("xoff_threshold_h2", &self.xoff_threshold_h2())
+            .field("rx_mem_full_thrhd", &self.rx_mem_full_thrhd())
+            .field("tx_mem_empty_thrhd", &self.tx_mem_empty_thrhd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to power down mem.when reg_mem_pd registers in the 3 uarts are all set to 1 mem will enter low power mode."]
     #[inline(always)]
diff --git a/esp32/src/uart0/mem_rx_status.rs b/esp32/src/uart0/mem_rx_status.rs
index 03092bf541..3cf2445163 100644
--- a/esp32/src/uart0/mem_rx_status.rs
+++ b/esp32/src/uart0/mem_rx_status.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_RX_STATUS")
-            .field(
-                "mem_rx_status",
-                &format_args!("{}", self.mem_rx_status().bits()),
-            )
-            .field(
-                "mem_rx_rd_addr",
-                &format_args!("{}", self.mem_rx_rd_addr().bits()),
-            )
-            .field(
-                "mem_rx_wr_addr",
-                &format_args!("{}", self.mem_rx_wr_addr().bits()),
-            )
+            .field("mem_rx_status", &self.mem_rx_status())
+            .field("mem_rx_rd_addr", &self.mem_rx_rd_addr())
+            .field("mem_rx_wr_addr", &self.mem_rx_wr_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_RX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_RX_STATUS_SPEC {
diff --git a/esp32/src/uart0/mem_tx_status.rs b/esp32/src/uart0/mem_tx_status.rs
index ed8b745d7e..3751e09309 100644
--- a/esp32/src/uart0/mem_tx_status.rs
+++ b/esp32/src/uart0/mem_tx_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_TX_STATUS")
-            .field(
-                "mem_tx_status",
-                &format_args!("{}", self.mem_tx_status().bits()),
-            )
+            .field("mem_tx_status", &self.mem_tx_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_TX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_TX_STATUS_SPEC {
diff --git a/esp32/src/uart0/negpulse.rs b/esp32/src/uart0/negpulse.rs
index 7ecf0ddd6b..ac67de07d6 100644
--- a/esp32/src/uart0/negpulse.rs
+++ b/esp32/src/uart0/negpulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NEGPULSE")
-            .field(
-                "negedge_min_cnt",
-                &format_args!("{}", self.negedge_min_cnt().bits()),
-            )
+            .field("negedge_min_cnt", &self.negedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NEGPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`negpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NEGPULSE_SPEC;
 impl crate::RegisterSpec for NEGPULSE_SPEC {
diff --git a/esp32/src/uart0/pospulse.rs b/esp32/src/uart0/pospulse.rs
index 0803fee59f..eac679c452 100644
--- a/esp32/src/uart0/pospulse.rs
+++ b/esp32/src/uart0/pospulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POSPULSE")
-            .field(
-                "posedge_min_cnt",
-                &format_args!("{}", self.posedge_min_cnt().bits()),
-            )
+            .field("posedge_min_cnt", &self.posedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POSPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pospulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct POSPULSE_SPEC;
 impl crate::RegisterSpec for POSPULSE_SPEC {
diff --git a/esp32/src/uart0/rs485_conf.rs b/esp32/src/uart0/rs485_conf.rs
index f201aded77..52dc0fb904 100644
--- a/esp32/src/uart0/rs485_conf.rs
+++ b/esp32/src/uart0/rs485_conf.rs
@@ -71,34 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RS485_CONF")
-            .field("rs485_en", &format_args!("{}", self.rs485_en().bit()))
-            .field("dl0_en", &format_args!("{}", self.dl0_en().bit()))
-            .field("dl1_en", &format_args!("{}", self.dl1_en().bit()))
-            .field(
-                "rs485tx_rx_en",
-                &format_args!("{}", self.rs485tx_rx_en().bit()),
-            )
-            .field(
-                "rs485rxby_tx_en",
-                &format_args!("{}", self.rs485rxby_tx_en().bit()),
-            )
-            .field(
-                "rs485_rx_dly_num",
-                &format_args!("{}", self.rs485_rx_dly_num().bit()),
-            )
-            .field(
-                "rs485_tx_dly_num",
-                &format_args!("{}", self.rs485_tx_dly_num().bits()),
-            )
+            .field("rs485_en", &self.rs485_en())
+            .field("dl0_en", &self.dl0_en())
+            .field("dl1_en", &self.dl1_en())
+            .field("rs485tx_rx_en", &self.rs485tx_rx_en())
+            .field("rs485rxby_tx_en", &self.rs485rxby_tx_en())
+            .field("rs485_rx_dly_num", &self.rs485_rx_dly_num())
+            .field("rs485_tx_dly_num", &self.rs485_tx_dly_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RS485_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to choose rs485 mode."]
     #[inline(always)]
diff --git a/esp32/src/uart0/rxd_cnt.rs b/esp32/src/uart0/rxd_cnt.rs
index 17c4e10a98..829d776e7a 100644
--- a/esp32/src/uart0/rxd_cnt.rs
+++ b/esp32/src/uart0/rxd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXD_CNT")
-            .field(
-                "rxd_edge_cnt",
-                &format_args!("{}", self.rxd_edge_cnt().bits()),
-            )
+            .field("rxd_edge_cnt", &self.rxd_edge_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXD_CNT_SPEC;
 impl crate::RegisterSpec for RXD_CNT_SPEC {
diff --git a/esp32/src/uart0/sleep_conf.rs b/esp32/src/uart0/sleep_conf.rs
index 611fa1687e..8f0bad977a 100644
--- a/esp32/src/uart0/sleep_conf.rs
+++ b/esp32/src/uart0/sleep_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF")
-            .field(
-                "active_threshold",
-                &format_args!("{}", self.active_threshold().bits()),
-            )
+            .field("active_threshold", &self.active_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - When the input rxd edge changes more than this register value. the uart is active from light sleeping mode."]
     #[inline(always)]
diff --git a/esp32/src/uart0/status.rs b/esp32/src/uart0/status.rs
index e2e08642a1..ea3a3e97e6 100644
--- a/esp32/src/uart0/status.rs
+++ b/esp32/src/uart0/status.rs
@@ -76,25 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("st_urx_out", &format_args!("{}", self.st_urx_out().bits()))
-            .field("dsrn", &format_args!("{}", self.dsrn().bit()))
-            .field("ctsn", &format_args!("{}", self.ctsn().bit()))
-            .field("rxd", &format_args!("{}", self.rxd().bit()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field("st_utx_out", &format_args!("{}", self.st_utx_out().bits()))
-            .field("dtrn", &format_args!("{}", self.dtrn().bit()))
-            .field("rtsn", &format_args!("{}", self.rtsn().bit()))
-            .field("txd", &format_args!("{}", self.txd().bit()))
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("st_urx_out", &self.st_urx_out())
+            .field("dsrn", &self.dsrn())
+            .field("ctsn", &self.ctsn())
+            .field("rxd", &self.rxd())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("st_utx_out", &self.st_utx_out())
+            .field("dtrn", &self.dtrn())
+            .field("rtsn", &self.rtsn())
+            .field("txd", &self.txd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32/src/uart0/swfc_conf.rs b/esp32/src/uart0/swfc_conf.rs
index e14f1a037d..e71b2c8955 100644
--- a/esp32/src/uart0/swfc_conf.rs
+++ b/esp32/src/uart0/swfc_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF")
-            .field(
-                "xon_threshold",
-                &format_args!("{}", self.xon_threshold().bits()),
-            )
-            .field(
-                "xoff_threshold",
-                &format_args!("{}", self.xoff_threshold().bits()),
-            )
-            .field("xon_char", &format_args!("{}", self.xon_char().bits()))
-            .field("xoff_char", &format_args!("{}", self.xoff_char().bits()))
+            .field("xon_threshold", &self.xon_threshold())
+            .field("xoff_threshold", &self.xoff_threshold())
+            .field("xon_char", &self.xon_char())
+            .field("xoff_char", &self.xoff_char())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - when the data amount in receiver's fifo is more than this register value. it will send a xoff char with uart_sw_flow_con_en set to 1."]
     #[inline(always)]
diff --git a/esp32/src/uhci0/ack_num.rs b/esp32/src/uhci0/ack_num.rs
index a7ad2e88be..7bed155fa5 100644
--- a/esp32/src/uhci0/ack_num.rs
+++ b/esp32/src/uhci0/ack_num.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ACK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ack_num::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ack_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ACK_NUM_SPEC;
diff --git a/esp32/src/uhci0/ahb_test.rs b/esp32/src/uhci0/ahb_test.rs
index cc842de33f..89e994574d 100644
--- a/esp32/src/uhci0/ahb_test.rs
+++ b/esp32/src/uhci0/ahb_test.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_TEST")
-            .field(
-                "ahb_testmode",
-                &format_args!("{}", self.ahb_testmode().bits()),
-            )
-            .field(
-                "ahb_testaddr",
-                &format_args!("{}", self.ahb_testaddr().bits()),
-            )
+            .field("ahb_testmode", &self.ahb_testmode())
+            .field("ahb_testaddr", &self.ahb_testaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_TEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - bit2 is ahb bus test enable ,bit1 is used to choose wrtie(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)"]
     #[inline(always)]
diff --git a/esp32/src/uhci0/conf0.rs b/esp32/src/uhci0/conf0.rs
index 2b51da9e6d..d9436d90a0 100644
--- a/esp32/src/uhci0/conf0.rs
+++ b/esp32/src/uhci0/conf0.rs
@@ -224,78 +224,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
-            .field("out_rst", &format_args!("{}", self.out_rst().bit()))
-            .field(
-                "ahbm_fifo_rst",
-                &format_args!("{}", self.ahbm_fifo_rst().bit()),
-            )
-            .field("ahbm_rst", &format_args!("{}", self.ahbm_rst().bit()))
-            .field(
-                "in_loop_test",
-                &format_args!("{}", self.in_loop_test().bit()),
-            )
-            .field(
-                "out_loop_test",
-                &format_args!("{}", self.out_loop_test().bit()),
-            )
-            .field(
-                "out_auto_wrback",
-                &format_args!("{}", self.out_auto_wrback().bit()),
-            )
-            .field(
-                "out_no_restart_clr",
-                &format_args!("{}", self.out_no_restart_clr().bit()),
-            )
-            .field(
-                "out_eof_mode",
-                &format_args!("{}", self.out_eof_mode().bit()),
-            )
-            .field("uart0_ce", &format_args!("{}", self.uart0_ce().bit()))
-            .field("uart1_ce", &format_args!("{}", self.uart1_ce().bit()))
-            .field("uart2_ce", &format_args!("{}", self.uart2_ce().bit()))
-            .field(
-                "outdscr_burst_en",
-                &format_args!("{}", self.outdscr_burst_en().bit()),
-            )
-            .field(
-                "indscr_burst_en",
-                &format_args!("{}", self.indscr_burst_en().bit()),
-            )
-            .field(
-                "out_data_burst_en",
-                &format_args!("{}", self.out_data_burst_en().bit()),
-            )
-            .field(
-                "mem_trans_en",
-                &format_args!("{}", self.mem_trans_en().bit()),
-            )
-            .field("seper_en", &format_args!("{}", self.seper_en().bit()))
-            .field("head_en", &format_args!("{}", self.head_en().bit()))
-            .field("crc_rec_en", &format_args!("{}", self.crc_rec_en().bit()))
-            .field(
-                "uart_idle_eof_en",
-                &format_args!("{}", self.uart_idle_eof_en().bit()),
-            )
-            .field("len_eof_en", &format_args!("{}", self.len_eof_en().bit()))
-            .field(
-                "encode_crc_en",
-                &format_args!("{}", self.encode_crc_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "uart_rx_brk_eof_en",
-                &format_args!("{}", self.uart_rx_brk_eof_en().bit()),
-            )
+            .field("in_rst", &self.in_rst())
+            .field("out_rst", &self.out_rst())
+            .field("ahbm_fifo_rst", &self.ahbm_fifo_rst())
+            .field("ahbm_rst", &self.ahbm_rst())
+            .field("in_loop_test", &self.in_loop_test())
+            .field("out_loop_test", &self.out_loop_test())
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("out_no_restart_clr", &self.out_no_restart_clr())
+            .field("out_eof_mode", &self.out_eof_mode())
+            .field("uart0_ce", &self.uart0_ce())
+            .field("uart1_ce", &self.uart1_ce())
+            .field("uart2_ce", &self.uart2_ce())
+            .field("outdscr_burst_en", &self.outdscr_burst_en())
+            .field("indscr_burst_en", &self.indscr_burst_en())
+            .field("out_data_burst_en", &self.out_data_burst_en())
+            .field("mem_trans_en", &self.mem_trans_en())
+            .field("seper_en", &self.seper_en())
+            .field("head_en", &self.head_en())
+            .field("crc_rec_en", &self.crc_rec_en())
+            .field("uart_idle_eof_en", &self.uart_idle_eof_en())
+            .field("len_eof_en", &self.len_eof_en())
+            .field("encode_crc_en", &self.encode_crc_en())
+            .field("clk_en", &self.clk_en())
+            .field("uart_rx_brk_eof_en", &self.uart_rx_brk_eof_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset in link operations."]
     #[inline(always)]
diff --git a/esp32/src/uhci0/conf1.rs b/esp32/src/uhci0/conf1.rs
index 90968d3f4f..a684be20d7 100644
--- a/esp32/src/uhci0/conf1.rs
+++ b/esp32/src/uhci0/conf1.rs
@@ -98,43 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "check_sum_en",
-                &format_args!("{}", self.check_sum_en().bit()),
-            )
-            .field(
-                "check_seq_en",
-                &format_args!("{}", self.check_seq_en().bit()),
-            )
-            .field("crc_disable", &format_args!("{}", self.crc_disable().bit()))
-            .field("save_head", &format_args!("{}", self.save_head().bit()))
-            .field(
-                "tx_check_sum_re",
-                &format_args!("{}", self.tx_check_sum_re().bit()),
-            )
-            .field(
-                "tx_ack_num_re",
-                &format_args!("{}", self.tx_ack_num_re().bit()),
-            )
-            .field("check_owner", &format_args!("{}", self.check_owner().bit()))
-            .field(
-                "wait_sw_start",
-                &format_args!("{}", self.wait_sw_start().bit()),
-            )
-            .field("sw_start", &format_args!("{}", self.sw_start().bit()))
-            .field(
-                "dma_infifo_full_thrs",
-                &format_args!("{}", self.dma_infifo_full_thrs().bits()),
-            )
+            .field("check_sum_en", &self.check_sum_en())
+            .field("check_seq_en", &self.check_seq_en())
+            .field("crc_disable", &self.crc_disable())
+            .field("save_head", &self.save_head())
+            .field("tx_check_sum_re", &self.tx_check_sum_re())
+            .field("tx_ack_num_re", &self.tx_ack_num_re())
+            .field("check_owner", &self.check_owner())
+            .field("wait_sw_start", &self.wait_sw_start())
+            .field("sw_start", &self.sw_start())
+            .field("dma_infifo_full_thrs", &self.dma_infifo_full_thrs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable decoder to check check_sum in packet header."]
     #[inline(always)]
diff --git a/esp32/src/uhci0/date.rs b/esp32/src/uhci0/date.rs
index f9fd3da639..4ede102ffa 100644
--- a/esp32/src/uhci0/date.rs
+++ b/esp32/src/uhci0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32/src/uhci0/dma_in_dscr.rs b/esp32/src/uhci0/dma_in_dscr.rs
index 8a978fdff6..d30991e730 100644
--- a/esp32/src/uhci0/dma_in_dscr.rs
+++ b/esp32/src/uhci0/dma_in_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_DSCR")
-            .field(
-                "inlink_dscr",
-                &format_args!("{}", self.inlink_dscr().bits()),
-            )
+            .field("inlink_dscr", &self.inlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_in_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_IN_DSCR_SPEC;
 impl crate::RegisterSpec for DMA_IN_DSCR_SPEC {
diff --git a/esp32/src/uhci0/dma_in_dscr_bf0.rs b/esp32/src/uhci0/dma_in_dscr_bf0.rs
index 736a8adf5d..b51f08094c 100644
--- a/esp32/src/uhci0/dma_in_dscr_bf0.rs
+++ b/esp32/src/uhci0/dma_in_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_DSCR_BF0")
-            .field(
-                "inlink_dscr_bf0",
-                &format_args!("{}", self.inlink_dscr_bf0().bits()),
-            )
+            .field("inlink_dscr_bf0", &self.inlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_in_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_IN_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for DMA_IN_DSCR_BF0_SPEC {
diff --git a/esp32/src/uhci0/dma_in_dscr_bf1.rs b/esp32/src/uhci0/dma_in_dscr_bf1.rs
index b732f997fe..3a1aca957e 100644
--- a/esp32/src/uhci0/dma_in_dscr_bf1.rs
+++ b/esp32/src/uhci0/dma_in_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_DSCR_BF1")
-            .field(
-                "inlink_dscr_bf1",
-                &format_args!("{}", self.inlink_dscr_bf1().bits()),
-            )
+            .field("inlink_dscr_bf1", &self.inlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_in_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_IN_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for DMA_IN_DSCR_BF1_SPEC {
diff --git a/esp32/src/uhci0/dma_in_err_eof_des_addr.rs b/esp32/src/uhci0/dma_in_err_eof_des_addr.rs
index 0859412de6..f468c63dbc 100644
--- a/esp32/src/uhci0/dma_in_err_eof_des_addr.rs
+++ b/esp32/src/uhci0/dma_in_err_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_ERR_EOF_DES_ADDR")
-            .field(
-                "in_err_eof_des_addr",
-                &format_args!("{}", self.in_err_eof_des_addr().bits()),
-            )
+            .field("in_err_eof_des_addr", &self.in_err_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_ERR_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_in_err_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_IN_ERR_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for DMA_IN_ERR_EOF_DES_ADDR_SPEC {
diff --git a/esp32/src/uhci0/dma_in_link.rs b/esp32/src/uhci0/dma_in_link.rs
index 2853762c06..b32d3c1442 100644
--- a/esp32/src/uhci0/dma_in_link.rs
+++ b/esp32/src/uhci0/dma_in_link.rs
@@ -60,33 +60,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_LINK")
-            .field(
-                "inlink_addr",
-                &format_args!("{}", self.inlink_addr().bits()),
-            )
-            .field(
-                "inlink_auto_ret",
-                &format_args!("{}", self.inlink_auto_ret().bit()),
-            )
-            .field("inlink_stop", &format_args!("{}", self.inlink_stop().bit()))
-            .field(
-                "inlink_start",
-                &format_args!("{}", self.inlink_start().bit()),
-            )
-            .field(
-                "inlink_restart",
-                &format_args!("{}", self.inlink_restart().bit()),
-            )
-            .field("inlink_park", &format_args!("{}", self.inlink_park().bit()))
+            .field("inlink_addr", &self.inlink_addr())
+            .field("inlink_auto_ret", &self.inlink_auto_ret())
+            .field("inlink_stop", &self.inlink_stop())
+            .field("inlink_start", &self.inlink_start())
+            .field("inlink_restart", &self.inlink_restart())
+            .field("inlink_park", &self.inlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register stores the least 20 bits of the first in link descriptor's address."]
     #[inline(always)]
diff --git a/esp32/src/uhci0/dma_in_pop.rs b/esp32/src/uhci0/dma_in_pop.rs
index e61a0346e7..aaca5635c6 100644
--- a/esp32/src/uhci0/dma_in_pop.rs
+++ b/esp32/src/uhci0/dma_in_pop.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_POP")
-            .field(
-                "infifo_rdata",
-                &format_args!("{}", self.infifo_rdata().bits()),
-            )
-            .field("infifo_pop", &format_args!("{}", self.infifo_pop().bit()))
+            .field("infifo_rdata", &self.infifo_rdata())
+            .field("infifo_pop", &self.infifo_pop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_POP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16 - Set this bit to pop data in in link descriptor's fifo."]
     #[inline(always)]
diff --git a/esp32/src/uhci0/dma_in_status.rs b/esp32/src/uhci0/dma_in_status.rs
index 86b3f00c39..afcef11dc4 100644
--- a/esp32/src/uhci0/dma_in_status.rs
+++ b/esp32/src/uhci0/dma_in_status.rs
@@ -27,21 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_STATUS")
-            .field("in_full", &format_args!("{}", self.in_full().bit()))
-            .field("in_empty", &format_args!("{}", self.in_empty().bit()))
-            .field(
-                "rx_err_cause",
-                &format_args!("{}", self.rx_err_cause().bits()),
-            )
+            .field("in_full", &self.in_full())
+            .field("in_empty", &self.in_empty())
+            .field("rx_err_cause", &self.rx_err_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_in_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_IN_STATUS_SPEC;
 impl crate::RegisterSpec for DMA_IN_STATUS_SPEC {
diff --git a/esp32/src/uhci0/dma_in_suc_eof_des_addr.rs b/esp32/src/uhci0/dma_in_suc_eof_des_addr.rs
index 3732d462a6..120f2187db 100644
--- a/esp32/src/uhci0/dma_in_suc_eof_des_addr.rs
+++ b/esp32/src/uhci0/dma_in_suc_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_SUC_EOF_DES_ADDR")
-            .field(
-                "in_suc_eof_des_addr",
-                &format_args!("{}", self.in_suc_eof_des_addr().bits()),
-            )
+            .field("in_suc_eof_des_addr", &self.in_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_SUC_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_in_suc_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_IN_SUC_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for DMA_IN_SUC_EOF_DES_ADDR_SPEC {
diff --git a/esp32/src/uhci0/dma_out_dscr.rs b/esp32/src/uhci0/dma_out_dscr.rs
index 4ff6acfb86..5ff5a2949f 100644
--- a/esp32/src/uhci0/dma_out_dscr.rs
+++ b/esp32/src/uhci0/dma_out_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_DSCR")
-            .field(
-                "outlink_dscr",
-                &format_args!("{}", self.outlink_dscr().bits()),
-            )
+            .field("outlink_dscr", &self.outlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_out_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_OUT_DSCR_SPEC;
 impl crate::RegisterSpec for DMA_OUT_DSCR_SPEC {
diff --git a/esp32/src/uhci0/dma_out_dscr_bf0.rs b/esp32/src/uhci0/dma_out_dscr_bf0.rs
index 3554f65adc..0fd2d9d1dd 100644
--- a/esp32/src/uhci0/dma_out_dscr_bf0.rs
+++ b/esp32/src/uhci0/dma_out_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_DSCR_BF0")
-            .field(
-                "outlink_dscr_bf0",
-                &format_args!("{}", self.outlink_dscr_bf0().bits()),
-            )
+            .field("outlink_dscr_bf0", &self.outlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_out_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_OUT_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for DMA_OUT_DSCR_BF0_SPEC {
diff --git a/esp32/src/uhci0/dma_out_dscr_bf1.rs b/esp32/src/uhci0/dma_out_dscr_bf1.rs
index 0e43c5b5b0..af9eb95855 100644
--- a/esp32/src/uhci0/dma_out_dscr_bf1.rs
+++ b/esp32/src/uhci0/dma_out_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_DSCR_BF1")
-            .field(
-                "outlink_dscr_bf1",
-                &format_args!("{}", self.outlink_dscr_bf1().bits()),
-            )
+            .field("outlink_dscr_bf1", &self.outlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_out_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_OUT_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for DMA_OUT_DSCR_BF1_SPEC {
diff --git a/esp32/src/uhci0/dma_out_eof_bfr_des_addr.rs b/esp32/src/uhci0/dma_out_eof_bfr_des_addr.rs
index b86fceefe7..93393f3f50 100644
--- a/esp32/src/uhci0/dma_out_eof_bfr_des_addr.rs
+++ b/esp32/src/uhci0/dma_out_eof_bfr_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_EOF_BFR_DES_ADDR")
-            .field(
-                "out_eof_bfr_des_addr",
-                &format_args!("{}", self.out_eof_bfr_des_addr().bits()),
-            )
+            .field("out_eof_bfr_des_addr", &self.out_eof_bfr_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_EOF_BFR_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_out_eof_bfr_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_OUT_EOF_BFR_DES_ADDR_SPEC;
 impl crate::RegisterSpec for DMA_OUT_EOF_BFR_DES_ADDR_SPEC {
diff --git a/esp32/src/uhci0/dma_out_eof_des_addr.rs b/esp32/src/uhci0/dma_out_eof_des_addr.rs
index 91bc2b66ed..919870d77f 100644
--- a/esp32/src/uhci0/dma_out_eof_des_addr.rs
+++ b/esp32/src/uhci0/dma_out_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_EOF_DES_ADDR")
-            .field(
-                "out_eof_des_addr",
-                &format_args!("{}", self.out_eof_des_addr().bits()),
-            )
+            .field("out_eof_des_addr", &self.out_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_out_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_OUT_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for DMA_OUT_EOF_DES_ADDR_SPEC {
diff --git a/esp32/src/uhci0/dma_out_link.rs b/esp32/src/uhci0/dma_out_link.rs
index 36b974f318..6ea2e68d39 100644
--- a/esp32/src/uhci0/dma_out_link.rs
+++ b/esp32/src/uhci0/dma_out_link.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_LINK")
-            .field(
-                "outlink_addr",
-                &format_args!("{}", self.outlink_addr().bits()),
-            )
-            .field(
-                "outlink_stop",
-                &format_args!("{}", self.outlink_stop().bit()),
-            )
-            .field(
-                "outlink_start",
-                &format_args!("{}", self.outlink_start().bit()),
-            )
-            .field(
-                "outlink_restart",
-                &format_args!("{}", self.outlink_restart().bit()),
-            )
-            .field(
-                "outlink_park",
-                &format_args!("{}", self.outlink_park().bit()),
-            )
+            .field("outlink_addr", &self.outlink_addr())
+            .field("outlink_stop", &self.outlink_stop())
+            .field("outlink_start", &self.outlink_start())
+            .field("outlink_restart", &self.outlink_restart())
+            .field("outlink_park", &self.outlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register stores the least 20 bits of the first out link descriptor's address."]
     #[inline(always)]
diff --git a/esp32/src/uhci0/dma_out_push.rs b/esp32/src/uhci0/dma_out_push.rs
index 1a2ed1e0a6..9382997410 100644
--- a/esp32/src/uhci0/dma_out_push.rs
+++ b/esp32/src/uhci0/dma_out_push.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_PUSH")
-            .field(
-                "outfifo_wdata",
-                &format_args!("{}", self.outfifo_wdata().bits()),
-            )
-            .field(
-                "outfifo_push",
-                &format_args!("{}", self.outfifo_push().bit()),
-            )
+            .field("outfifo_wdata", &self.outfifo_wdata())
+            .field("outfifo_push", &self.outfifo_push())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_PUSH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This is the data need to be pushed into out link descriptor's fifo."]
     #[inline(always)]
diff --git a/esp32/src/uhci0/dma_out_status.rs b/esp32/src/uhci0/dma_out_status.rs
index e2ef7e899f..1943d658e4 100644
--- a/esp32/src/uhci0/dma_out_status.rs
+++ b/esp32/src/uhci0/dma_out_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_STATUS")
-            .field("out_full", &format_args!("{}", self.out_full().bit()))
-            .field("out_empty", &format_args!("{}", self.out_empty().bit()))
+            .field("out_full", &self.out_full())
+            .field("out_empty", &self.out_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_out_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_OUT_STATUS_SPEC;
 impl crate::RegisterSpec for DMA_OUT_STATUS_SPEC {
diff --git a/esp32/src/uhci0/esc_conf.rs b/esp32/src/uhci0/esc_conf.rs
index 21bc9dc997..f35e26b867 100644
--- a/esp32/src/uhci0/esc_conf.rs
+++ b/esp32/src/uhci0/esc_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ESC_CONF")
-            .field("seper_char", &format_args!("{}", self.seper_char().bits()))
-            .field(
-                "seper_esc_char0",
-                &format_args!("{}", self.seper_esc_char0().bits()),
-            )
-            .field(
-                "seper_esc_char1",
-                &format_args!("{}", self.seper_esc_char1().bits()),
-            )
+            .field("seper_char", &self.seper_char())
+            .field("seper_esc_char0", &self.seper_esc_char0())
+            .field("seper_esc_char1", &self.seper_esc_char1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ESC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register stores the seperator char seperator char is used to seperate the data frame."]
     #[inline(always)]
diff --git a/esp32/src/uhci0/escape_conf.rs b/esp32/src/uhci0/escape_conf.rs
index 5fd480eb4b..f3e3314ddd 100644
--- a/esp32/src/uhci0/escape_conf.rs
+++ b/esp32/src/uhci0/escape_conf.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ESCAPE_CONF")
-            .field(
-                "tx_c0_esc_en",
-                &format_args!("{}", self.tx_c0_esc_en().bit()),
-            )
-            .field(
-                "tx_db_esc_en",
-                &format_args!("{}", self.tx_db_esc_en().bit()),
-            )
-            .field(
-                "tx_11_esc_en",
-                &format_args!("{}", self.tx_11_esc_en().bit()),
-            )
-            .field(
-                "tx_13_esc_en",
-                &format_args!("{}", self.tx_13_esc_en().bit()),
-            )
-            .field(
-                "rx_c0_esc_en",
-                &format_args!("{}", self.rx_c0_esc_en().bit()),
-            )
-            .field(
-                "rx_db_esc_en",
-                &format_args!("{}", self.rx_db_esc_en().bit()),
-            )
-            .field(
-                "rx_11_esc_en",
-                &format_args!("{}", self.rx_11_esc_en().bit()),
-            )
-            .field(
-                "rx_13_esc_en",
-                &format_args!("{}", self.rx_13_esc_en().bit()),
-            )
+            .field("tx_c0_esc_en", &self.tx_c0_esc_en())
+            .field("tx_db_esc_en", &self.tx_db_esc_en())
+            .field("tx_11_esc_en", &self.tx_11_esc_en())
+            .field("tx_13_esc_en", &self.tx_13_esc_en())
+            .field("rx_c0_esc_en", &self.rx_c0_esc_en())
+            .field("rx_db_esc_en", &self.rx_db_esc_en())
+            .field("rx_11_esc_en", &self.rx_11_esc_en())
+            .field("rx_13_esc_en", &self.rx_13_esc_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ESCAPE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable 0xc0 char decode when DMA receives data."]
     #[inline(always)]
diff --git a/esp32/src/uhci0/hung_conf.rs b/esp32/src/uhci0/hung_conf.rs
index d23621395d..de39f2b37f 100644
--- a/esp32/src/uhci0/hung_conf.rs
+++ b/esp32/src/uhci0/hung_conf.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HUNG_CONF")
-            .field(
-                "txfifo_timeout",
-                &format_args!("{}", self.txfifo_timeout().bits()),
-            )
-            .field(
-                "txfifo_timeout_shift",
-                &format_args!("{}", self.txfifo_timeout_shift().bits()),
-            )
-            .field(
-                "txfifo_timeout_ena",
-                &format_args!("{}", self.txfifo_timeout_ena().bit()),
-            )
-            .field(
-                "rxfifo_timeout",
-                &format_args!("{}", self.rxfifo_timeout().bits()),
-            )
-            .field(
-                "rxfifo_timeout_shift",
-                &format_args!("{}", self.rxfifo_timeout_shift().bits()),
-            )
-            .field(
-                "rxfifo_timeout_ena",
-                &format_args!("{}", self.rxfifo_timeout_ena().bit()),
-            )
+            .field("txfifo_timeout", &self.txfifo_timeout())
+            .field("txfifo_timeout_shift", &self.txfifo_timeout_shift())
+            .field("txfifo_timeout_ena", &self.txfifo_timeout_ena())
+            .field("rxfifo_timeout", &self.rxfifo_timeout())
+            .field("rxfifo_timeout_shift", &self.rxfifo_timeout_shift())
+            .field("rxfifo_timeout_ena", &self.rxfifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt."]
     #[inline(always)]
diff --git a/esp32/src/uhci0/int_ena.rs b/esp32/src/uhci0/int_ena.rs
index 32bfbebbea..9286a24cb5 100644
--- a/esp32/src/uhci0/int_ena.rs
+++ b/esp32/src/uhci0/int_ena.rs
@@ -161,47 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("send_s_q", &format_args!("{}", self.send_s_q().bit()))
-            .field("send_a_q", &format_args!("{}", self.send_a_q().bit()))
-            .field(
-                "dma_infifo_full_wm",
-                &format_args!("{}", self.dma_infifo_full_wm().bit()),
-            )
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("send_s_q", &self.send_s_q())
+            .field("send_a_q", &self.send_a_q())
+            .field("dma_infifo_full_wm", &self.dma_infifo_full_wm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32/src/uhci0/int_raw.rs b/esp32/src/uhci0/int_raw.rs
index f063bbb129..d08ddc015b 100644
--- a/esp32/src/uhci0/int_raw.rs
+++ b/esp32/src/uhci0/int_raw.rs
@@ -125,47 +125,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("send_s_q", &format_args!("{}", self.send_s_q().bit()))
-            .field("send_a_q", &format_args!("{}", self.send_a_q().bit()))
-            .field(
-                "dma_infifo_full_wm",
-                &format_args!("{}", self.dma_infifo_full_wm().bit()),
-            )
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("send_s_q", &self.send_s_q())
+            .field("send_a_q", &self.send_a_q())
+            .field("dma_infifo_full_wm", &self.dma_infifo_full_wm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32/src/uhci0/int_st.rs b/esp32/src/uhci0/int_st.rs
index dbe4ccdeda..c40a9418e8 100644
--- a/esp32/src/uhci0/int_st.rs
+++ b/esp32/src/uhci0/int_st.rs
@@ -125,47 +125,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("send_s_q", &format_args!("{}", self.send_s_q().bit()))
-            .field("send_a_q", &format_args!("{}", self.send_a_q().bit()))
-            .field(
-                "dma_infifo_full_wm",
-                &format_args!("{}", self.dma_infifo_full_wm().bit()),
-            )
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("send_s_q", &self.send_s_q())
+            .field("send_a_q", &self.send_a_q())
+            .field("dma_infifo_full_wm", &self.dma_infifo_full_wm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32/src/uhci0/pkt_thres.rs b/esp32/src/uhci0/pkt_thres.rs
index 2627516025..eaf4ee0b06 100644
--- a/esp32/src/uhci0/pkt_thres.rs
+++ b/esp32/src/uhci0/pkt_thres.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PKT_THRES")
-            .field("pkt_thrs", &format_args!("{}", self.pkt_thrs().bits()))
+            .field("pkt_thrs", &self.pkt_thrs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PKT_THRES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - when the amount of packet payload is greater than this value the process of receiving data is done."]
     #[inline(always)]
diff --git a/esp32/src/uhci0/q/word0.rs b/esp32/src/uhci0/q/word0.rs
index 9410768333..0729202bd5 100644
--- a/esp32/src/uhci0/q/word0.rs
+++ b/esp32/src/uhci0/q/word0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WORD0")
-            .field("send_word", &format_args!("{}", self.send_word().bits()))
+            .field("send_word", &self.send_word())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WORD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register stores the content of short packet's first dword"]
     #[inline(always)]
diff --git a/esp32/src/uhci0/q/word1.rs b/esp32/src/uhci0/q/word1.rs
index 6be0328b17..f4c117b54b 100644
--- a/esp32/src/uhci0/q/word1.rs
+++ b/esp32/src/uhci0/q/word1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WORD1")
-            .field("send_word", &format_args!("{}", self.send_word().bits()))
+            .field("send_word", &self.send_word())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WORD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register stores the content of short packet's second dword"]
     #[inline(always)]
diff --git a/esp32/src/uhci0/quick_sent.rs b/esp32/src/uhci0/quick_sent.rs
index 049446498a..a0fcebe802 100644
--- a/esp32/src/uhci0/quick_sent.rs
+++ b/esp32/src/uhci0/quick_sent.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUICK_SENT")
-            .field(
-                "single_send_num",
-                &format_args!("{}", self.single_send_num().bits()),
-            )
-            .field(
-                "single_send_en",
-                &format_args!("{}", self.single_send_en().bit()),
-            )
-            .field(
-                "always_send_num",
-                &format_args!("{}", self.always_send_num().bits()),
-            )
-            .field(
-                "always_send_en",
-                &format_args!("{}", self.always_send_en().bit()),
-            )
+            .field("single_send_num", &self.single_send_num())
+            .field("single_send_en", &self.single_send_en())
+            .field("always_send_num", &self.always_send_num())
+            .field("always_send_en", &self.always_send_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUICK_SENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - The bits are used to choose which short packet"]
     #[inline(always)]
diff --git a/esp32/src/uhci0/rx_head.rs b/esp32/src/uhci0/rx_head.rs
index 4a060b56f0..9b10bec559 100644
--- a/esp32/src/uhci0/rx_head.rs
+++ b/esp32/src/uhci0/rx_head.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_HEAD")
-            .field("rx_head", &format_args!("{}", self.rx_head().bits()))
+            .field("rx_head", &self.rx_head())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_HEAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_head::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_HEAD_SPEC;
 impl crate::RegisterSpec for RX_HEAD_SPEC {
diff --git a/esp32/src/uhci0/state0.rs b/esp32/src/uhci0/state0.rs
index 3f5620a366..9b3cae97d3 100644
--- a/esp32/src/uhci0/state0.rs
+++ b/esp32/src/uhci0/state0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE0")
-            .field("state0", &format_args!("{}", self.state0().bits()))
+            .field("state0", &self.state0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE0_SPEC;
 impl crate::RegisterSpec for STATE0_SPEC {
diff --git a/esp32/src/uhci0/state1.rs b/esp32/src/uhci0/state1.rs
index e64975288c..1e77beac1b 100644
--- a/esp32/src/uhci0/state1.rs
+++ b/esp32/src/uhci0/state1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE1")
-            .field("state1", &format_args!("{}", self.state1().bits()))
+            .field("state1", &self.state1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE1_SPEC;
 impl crate::RegisterSpec for STATE1_SPEC {
diff --git a/esp32c2/src/apb_ctrl/clk_out_en.rs b/esp32c2/src/apb_ctrl/clk_out_en.rs
index 93e01e1332..1b1c9ce00b 100644
--- a/esp32c2/src/apb_ctrl/clk_out_en.rs
+++ b/esp32c2/src/apb_ctrl/clk_out_en.rs
@@ -107,41 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_OUT_EN")
-            .field("clk20_oen", &format_args!("{}", self.clk20_oen().bit()))
-            .field("clk22_oen", &format_args!("{}", self.clk22_oen().bit()))
-            .field("clk44_oen", &format_args!("{}", self.clk44_oen().bit()))
-            .field("clk_bb_oen", &format_args!("{}", self.clk_bb_oen().bit()))
-            .field("clk80_oen", &format_args!("{}", self.clk80_oen().bit()))
-            .field("clk160_oen", &format_args!("{}", self.clk160_oen().bit()))
-            .field(
-                "clk_320m_oen",
-                &format_args!("{}", self.clk_320m_oen().bit()),
-            )
-            .field(
-                "clk_adc_inf_oen",
-                &format_args!("{}", self.clk_adc_inf_oen().bit()),
-            )
-            .field(
-                "clk_dac_cpu_oen",
-                &format_args!("{}", self.clk_dac_cpu_oen().bit()),
-            )
-            .field(
-                "clk40x_bb_oen",
-                &format_args!("{}", self.clk40x_bb_oen().bit()),
-            )
-            .field(
-                "clk_xtal_oen",
-                &format_args!("{}", self.clk_xtal_oen().bit()),
-            )
+            .field("clk20_oen", &self.clk20_oen())
+            .field("clk22_oen", &self.clk22_oen())
+            .field("clk44_oen", &self.clk44_oen())
+            .field("clk_bb_oen", &self.clk_bb_oen())
+            .field("clk80_oen", &self.clk80_oen())
+            .field("clk160_oen", &self.clk160_oen())
+            .field("clk_320m_oen", &self.clk_320m_oen())
+            .field("clk_adc_inf_oen", &self.clk_adc_inf_oen())
+            .field("clk_dac_cpu_oen", &self.clk_dac_cpu_oen())
+            .field("clk40x_bb_oen", &self.clk40x_bb_oen())
+            .field("clk_xtal_oen", &self.clk_xtal_oen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_OUT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_clk20_oen"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/clkgate_force_on.rs b/esp32c2/src/apb_ctrl/clkgate_force_on.rs
index 3f69694cfa..69ef419a91 100644
--- a/esp32c2/src/apb_ctrl/clkgate_force_on.rs
+++ b/esp32c2/src/apb_ctrl/clkgate_force_on.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKGATE_FORCE_ON")
-            .field(
-                "rom_clkgate_force_on",
-                &format_args!("{}", self.rom_clkgate_force_on().bits()),
-            )
-            .field(
-                "sram_clkgate_force_on",
-                &format_args!("{}", self.sram_clkgate_force_on().bits()),
-            )
+            .field("rom_clkgate_force_on", &self.rom_clkgate_force_on())
+            .field("sram_clkgate_force_on", &self.sram_clkgate_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKGATE_FORCE_ON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Set the bit to 1 to force rom always have clock, for low power can clear to 0 then only when have access the rom have clock"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/date.rs b/esp32c2/src/apb_ctrl/date.rs
index 1e68678f56..6c2ac789ba 100644
--- a/esp32c2/src/apb_ctrl/date.rs
+++ b/esp32c2/src/apb_ctrl/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/apb_ctrl/ext_mem_pms_lock.rs b/esp32c2/src/apb_ctrl/ext_mem_pms_lock.rs
index a5affca905..4e5099000c 100644
--- a/esp32c2/src/apb_ctrl/ext_mem_pms_lock.rs
+++ b/esp32c2/src/apb_ctrl/ext_mem_pms_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_MEM_PMS_LOCK")
-            .field(
-                "ext_mem_pms_lock",
-                &format_args!("{}", self.ext_mem_pms_lock().bit()),
-            )
+            .field("ext_mem_pms_lock", &self.ext_mem_pms_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_MEM_PMS_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_ext_mem_pms_lock"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/flash_ace0_addr.rs b/esp32c2/src/apb_ctrl/flash_ace0_addr.rs
index 3bb5a3b8b5..a5e9b9ff55 100644
--- a/esp32c2/src/apb_ctrl/flash_ace0_addr.rs
+++ b/esp32c2/src/apb_ctrl/flash_ace0_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE0_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_flash_ace0_addr_s"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/flash_ace0_attr.rs b/esp32c2/src/apb_ctrl/flash_ace0_attr.rs
index 2a43c5ae1c..031fee3f6b 100644
--- a/esp32c2/src/apb_ctrl/flash_ace0_attr.rs
+++ b/esp32c2/src/apb_ctrl/flash_ace0_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE0_ATTR")
-            .field(
-                "flash_ace0_attr",
-                &format_args!("{}", self.flash_ace0_attr().bits()),
-            )
+            .field("flash_ace0_attr", &self.flash_ace0_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE0_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reg_flash_ace0_attr"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/flash_ace0_size.rs b/esp32c2/src/apb_ctrl/flash_ace0_size.rs
index 720efba105..810deee936 100644
--- a/esp32c2/src/apb_ctrl/flash_ace0_size.rs
+++ b/esp32c2/src/apb_ctrl/flash_ace0_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE0_SIZE")
-            .field(
-                "flash_ace0_size",
-                &format_args!("{}", self.flash_ace0_size().bits()),
-            )
+            .field("flash_ace0_size", &self.flash_ace0_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - reg_flash_ace0_size"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/flash_ace1_addr.rs b/esp32c2/src/apb_ctrl/flash_ace1_addr.rs
index 821f446694..86c641aa6a 100644
--- a/esp32c2/src/apb_ctrl/flash_ace1_addr.rs
+++ b/esp32c2/src/apb_ctrl/flash_ace1_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE1_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_flash_ace1_addr_s"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/flash_ace1_attr.rs b/esp32c2/src/apb_ctrl/flash_ace1_attr.rs
index 76b34f4cf0..1f2e7fbc73 100644
--- a/esp32c2/src/apb_ctrl/flash_ace1_attr.rs
+++ b/esp32c2/src/apb_ctrl/flash_ace1_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE1_ATTR")
-            .field(
-                "flash_ace1_attr",
-                &format_args!("{}", self.flash_ace1_attr().bits()),
-            )
+            .field("flash_ace1_attr", &self.flash_ace1_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE1_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reg_flash_ace1_attr"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/flash_ace1_size.rs b/esp32c2/src/apb_ctrl/flash_ace1_size.rs
index bff39c1b6c..8d529961e2 100644
--- a/esp32c2/src/apb_ctrl/flash_ace1_size.rs
+++ b/esp32c2/src/apb_ctrl/flash_ace1_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE1_SIZE")
-            .field(
-                "flash_ace1_size",
-                &format_args!("{}", self.flash_ace1_size().bits()),
-            )
+            .field("flash_ace1_size", &self.flash_ace1_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - reg_flash_ace1_size"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/flash_ace2_addr.rs b/esp32c2/src/apb_ctrl/flash_ace2_addr.rs
index b9267f6e04..462402d3a2 100644
--- a/esp32c2/src/apb_ctrl/flash_ace2_addr.rs
+++ b/esp32c2/src/apb_ctrl/flash_ace2_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE2_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_flash_ace2_addr_s"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/flash_ace2_attr.rs b/esp32c2/src/apb_ctrl/flash_ace2_attr.rs
index 10dff6bf3e..cc17a0a38d 100644
--- a/esp32c2/src/apb_ctrl/flash_ace2_attr.rs
+++ b/esp32c2/src/apb_ctrl/flash_ace2_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE2_ATTR")
-            .field(
-                "flash_ace2_attr",
-                &format_args!("{}", self.flash_ace2_attr().bits()),
-            )
+            .field("flash_ace2_attr", &self.flash_ace2_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE2_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reg_flash_ace2_attr"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/flash_ace2_size.rs b/esp32c2/src/apb_ctrl/flash_ace2_size.rs
index 8dee90db82..88378bd2f9 100644
--- a/esp32c2/src/apb_ctrl/flash_ace2_size.rs
+++ b/esp32c2/src/apb_ctrl/flash_ace2_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE2_SIZE")
-            .field(
-                "flash_ace2_size",
-                &format_args!("{}", self.flash_ace2_size().bits()),
-            )
+            .field("flash_ace2_size", &self.flash_ace2_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE2_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - reg_flash_ace2_size"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/flash_ace3_addr.rs b/esp32c2/src/apb_ctrl/flash_ace3_addr.rs
index f715ccd5b5..afc734c8a8 100644
--- a/esp32c2/src/apb_ctrl/flash_ace3_addr.rs
+++ b/esp32c2/src/apb_ctrl/flash_ace3_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE3_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_flash_ace3_addr_s"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/flash_ace3_attr.rs b/esp32c2/src/apb_ctrl/flash_ace3_attr.rs
index cc60a454e4..6488958d4b 100644
--- a/esp32c2/src/apb_ctrl/flash_ace3_attr.rs
+++ b/esp32c2/src/apb_ctrl/flash_ace3_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE3_ATTR")
-            .field(
-                "flash_ace3_attr",
-                &format_args!("{}", self.flash_ace3_attr().bits()),
-            )
+            .field("flash_ace3_attr", &self.flash_ace3_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE3_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reg_flash_ace3_attr"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/flash_ace3_size.rs b/esp32c2/src/apb_ctrl/flash_ace3_size.rs
index ff5e15e842..2b2b172450 100644
--- a/esp32c2/src/apb_ctrl/flash_ace3_size.rs
+++ b/esp32c2/src/apb_ctrl/flash_ace3_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE3_SIZE")
-            .field(
-                "flash_ace3_size",
-                &format_args!("{}", self.flash_ace3_size().bits()),
-            )
+            .field("flash_ace3_size", &self.flash_ace3_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE3_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - reg_flash_ace3_size"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/front_end_mem_pd.rs b/esp32c2/src/apb_ctrl/front_end_mem_pd.rs
index 5552d02a57..a382e48a54 100644
--- a/esp32c2/src/apb_ctrl/front_end_mem_pd.rs
+++ b/esp32c2/src/apb_ctrl/front_end_mem_pd.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FRONT_END_MEM_PD")
-            .field(
-                "agc_mem_force_pu",
-                &format_args!("{}", self.agc_mem_force_pu().bit()),
-            )
-            .field(
-                "agc_mem_force_pd",
-                &format_args!("{}", self.agc_mem_force_pd().bit()),
-            )
-            .field(
-                "pbus_mem_force_pu",
-                &format_args!("{}", self.pbus_mem_force_pu().bit()),
-            )
-            .field(
-                "pbus_mem_force_pd",
-                &format_args!("{}", self.pbus_mem_force_pd().bit()),
-            )
-            .field(
-                "dc_mem_force_pu",
-                &format_args!("{}", self.dc_mem_force_pu().bit()),
-            )
-            .field(
-                "dc_mem_force_pd",
-                &format_args!("{}", self.dc_mem_force_pd().bit()),
-            )
-            .field(
-                "freq_mem_force_pu",
-                &format_args!("{}", self.freq_mem_force_pu().bit()),
-            )
-            .field(
-                "freq_mem_force_pd",
-                &format_args!("{}", self.freq_mem_force_pd().bit()),
-            )
+            .field("agc_mem_force_pu", &self.agc_mem_force_pu())
+            .field("agc_mem_force_pd", &self.agc_mem_force_pd())
+            .field("pbus_mem_force_pu", &self.pbus_mem_force_pu())
+            .field("pbus_mem_force_pd", &self.pbus_mem_force_pd())
+            .field("dc_mem_force_pu", &self.dc_mem_force_pu())
+            .field("dc_mem_force_pd", &self.dc_mem_force_pd())
+            .field("freq_mem_force_pu", &self.freq_mem_force_pu())
+            .field("freq_mem_force_pd", &self.freq_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FRONT_END_MEM_PD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_agc_mem_force_pu"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/host_inf_sel.rs b/esp32c2/src/apb_ctrl/host_inf_sel.rs
index d2d026224a..98a34776f7 100644
--- a/esp32c2/src/apb_ctrl/host_inf_sel.rs
+++ b/esp32c2/src/apb_ctrl/host_inf_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_INF_SEL")
-            .field(
-                "peri_io_swap",
-                &format_args!("{}", self.peri_io_swap().bits()),
-            )
+            .field("peri_io_swap", &self.peri_io_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_INF_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - reg_peri_io_swap"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/mem_power_down.rs b/esp32c2/src/apb_ctrl/mem_power_down.rs
index 3dc0d370fe..baa6a1e8dd 100644
--- a/esp32c2/src/apb_ctrl/mem_power_down.rs
+++ b/esp32c2/src/apb_ctrl/mem_power_down.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_POWER_DOWN")
-            .field(
-                "rom_power_down",
-                &format_args!("{}", self.rom_power_down().bits()),
-            )
-            .field(
-                "sram_power_down",
-                &format_args!("{}", self.sram_power_down().bits()),
-            )
+            .field("rom_power_down", &self.rom_power_down())
+            .field("sram_power_down", &self.sram_power_down())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_POWER_DOWN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Set 1 to let rom power down"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/mem_power_up.rs b/esp32c2/src/apb_ctrl/mem_power_up.rs
index 263e3f0f84..c806e0b9c1 100644
--- a/esp32c2/src/apb_ctrl/mem_power_up.rs
+++ b/esp32c2/src/apb_ctrl/mem_power_up.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_POWER_UP")
-            .field(
-                "rom_power_up",
-                &format_args!("{}", self.rom_power_up().bits()),
-            )
-            .field(
-                "sram_power_up",
-                &format_args!("{}", self.sram_power_up().bits()),
-            )
+            .field("rom_power_up", &self.rom_power_up())
+            .field("sram_power_up", &self.sram_power_up())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_POWER_UP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Set 1 to let rom power up"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/peri_backup_apb_addr.rs b/esp32c2/src/apb_ctrl/peri_backup_apb_addr.rs
index be8ff6a3b9..f453646600 100644
--- a/esp32c2/src/apb_ctrl/peri_backup_apb_addr.rs
+++ b/esp32c2/src/apb_ctrl/peri_backup_apb_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_BACKUP_APB_ADDR")
-            .field(
-                "backup_apb_start_addr",
-                &format_args!("{}", self.backup_apb_start_addr().bits()),
-            )
+            .field("backup_apb_start_addr", &self.backup_apb_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_BACKUP_APB_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_backup_apb_start_addr"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/peri_backup_config.rs b/esp32c2/src/apb_ctrl/peri_backup_config.rs
index 7d98ed340a..1817d99a10 100644
--- a/esp32c2/src/apb_ctrl/peri_backup_config.rs
+++ b/esp32c2/src/apb_ctrl/peri_backup_config.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_BACKUP_CONFIG")
-            .field(
-                "peri_backup_flow_err",
-                &format_args!("{}", self.peri_backup_flow_err().bits()),
-            )
-            .field(
-                "peri_backup_burst_limit",
-                &format_args!("{}", self.peri_backup_burst_limit().bits()),
-            )
-            .field(
-                "peri_backup_tout_thres",
-                &format_args!("{}", self.peri_backup_tout_thres().bits()),
-            )
-            .field(
-                "peri_backup_size",
-                &format_args!("{}", self.peri_backup_size().bits()),
-            )
-            .field(
-                "peri_backup_to_mem",
-                &format_args!("{}", self.peri_backup_to_mem().bit()),
-            )
-            .field(
-                "peri_backup_ena",
-                &format_args!("{}", self.peri_backup_ena().bit()),
-            )
+            .field("peri_backup_flow_err", &self.peri_backup_flow_err())
+            .field("peri_backup_burst_limit", &self.peri_backup_burst_limit())
+            .field("peri_backup_tout_thres", &self.peri_backup_tout_thres())
+            .field("peri_backup_size", &self.peri_backup_size())
+            .field("peri_backup_to_mem", &self.peri_backup_to_mem())
+            .field("peri_backup_ena", &self.peri_backup_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_BACKUP_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 4:8 - reg_peri_backup_burst_limit"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/peri_backup_int_ena.rs b/esp32c2/src/apb_ctrl/peri_backup_int_ena.rs
index 468af4e912..85708f8e9e 100644
--- a/esp32c2/src/apb_ctrl/peri_backup_int_ena.rs
+++ b/esp32c2/src/apb_ctrl/peri_backup_int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_BACKUP_INT_ENA")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("err", &format_args!("{}", self.err().bit()))
+            .field("done", &self.done())
+            .field("err", &self.err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_BACKUP_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_peri_backup_done_int_ena"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/peri_backup_int_raw.rs b/esp32c2/src/apb_ctrl/peri_backup_int_raw.rs
index 1a45cbdcc5..776d3b1a3a 100644
--- a/esp32c2/src/apb_ctrl/peri_backup_int_raw.rs
+++ b/esp32c2/src/apb_ctrl/peri_backup_int_raw.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_BACKUP_INT_RAW")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("err", &format_args!("{}", self.err().bit()))
+            .field("done", &self.done())
+            .field("err", &self.err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_BACKUP_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "APB_CTRL_PERI_BACKUP_INT_RAW_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_backup_int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PERI_BACKUP_INT_RAW_SPEC;
 impl crate::RegisterSpec for PERI_BACKUP_INT_RAW_SPEC {
diff --git a/esp32c2/src/apb_ctrl/peri_backup_int_st.rs b/esp32c2/src/apb_ctrl/peri_backup_int_st.rs
index a83e4e6e14..a15a578d43 100644
--- a/esp32c2/src/apb_ctrl/peri_backup_int_st.rs
+++ b/esp32c2/src/apb_ctrl/peri_backup_int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_BACKUP_INT_ST")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("err", &format_args!("{}", self.err().bit()))
+            .field("done", &self.done())
+            .field("err", &self.err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_BACKUP_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "APB_CTRL_PERI_BACKUP_INT_ST_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_backup_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PERI_BACKUP_INT_ST_SPEC;
 impl crate::RegisterSpec for PERI_BACKUP_INT_ST_SPEC {
diff --git a/esp32c2/src/apb_ctrl/peri_backup_mem_addr.rs b/esp32c2/src/apb_ctrl/peri_backup_mem_addr.rs
index 3f1d4eb47c..0a315fd0a5 100644
--- a/esp32c2/src/apb_ctrl/peri_backup_mem_addr.rs
+++ b/esp32c2/src/apb_ctrl/peri_backup_mem_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_BACKUP_MEM_ADDR")
-            .field(
-                "backup_mem_start_addr",
-                &format_args!("{}", self.backup_mem_start_addr().bits()),
-            )
+            .field("backup_mem_start_addr", &self.backup_mem_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_BACKUP_MEM_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_backup_mem_start_addr"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/redcy_sig0.rs b/esp32c2/src/apb_ctrl/redcy_sig0.rs
index 53686995f7..b36adf4a88 100644
--- a/esp32c2/src/apb_ctrl/redcy_sig0.rs
+++ b/esp32c2/src/apb_ctrl/redcy_sig0.rs
@@ -24,17 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDCY_SIG0")
-            .field("redcy_sig0", &format_args!("{}", self.redcy_sig0().bits()))
-            .field("redcy_andor", &format_args!("{}", self.redcy_andor().bit()))
+            .field("redcy_sig0", &self.redcy_sig0())
+            .field("redcy_andor", &self.redcy_andor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDCY_SIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - reg_redcy_sig0"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/redcy_sig1.rs b/esp32c2/src/apb_ctrl/redcy_sig1.rs
index a9db07e7cc..45bd29f629 100644
--- a/esp32c2/src/apb_ctrl/redcy_sig1.rs
+++ b/esp32c2/src/apb_ctrl/redcy_sig1.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDCY_SIG1")
-            .field("redcy_sig1", &format_args!("{}", self.redcy_sig1().bits()))
-            .field(
-                "redcy_nandor",
-                &format_args!("{}", self.redcy_nandor().bit()),
-            )
+            .field("redcy_sig1", &self.redcy_sig1())
+            .field("redcy_nandor", &self.redcy_nandor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDCY_SIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - reg_redcy_sig1"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/retention_ctrl.rs b/esp32c2/src/apb_ctrl/retention_ctrl.rs
index 704f720fdb..976ca1625e 100644
--- a/esp32c2/src/apb_ctrl/retention_ctrl.rs
+++ b/esp32c2/src/apb_ctrl/retention_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_CTRL")
-            .field(
-                "retention_link_addr",
-                &format_args!("{}", self.retention_link_addr().bits()),
-            )
-            .field(
-                "nobypass_cpu_iso_rst",
-                &format_args!("{}", self.nobypass_cpu_iso_rst().bit()),
-            )
+            .field("retention_link_addr", &self.retention_link_addr())
+            .field("nobypass_cpu_iso_rst", &self.nobypass_cpu_iso_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:26 - reg_retention_link_addr"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/rnd_data.rs b/esp32c2/src/apb_ctrl/rnd_data.rs
index 5b90e4e5f7..913e725f74 100644
--- a/esp32c2/src/apb_ctrl/rnd_data.rs
+++ b/esp32c2/src/apb_ctrl/rnd_data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_DATA")
-            .field("rnd_data", &format_args!("{}", self.rnd_data().bits()))
+            .field("rnd_data", &self.rnd_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "APB_CTRL_RND_DATA_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RND_DATA_SPEC;
 impl crate::RegisterSpec for RND_DATA_SPEC {
diff --git a/esp32c2/src/apb_ctrl/sdio_ctrl.rs b/esp32c2/src/apb_ctrl/sdio_ctrl.rs
index 739b409e3c..8ac4b3c4ef 100644
--- a/esp32c2/src/apb_ctrl/sdio_ctrl.rs
+++ b/esp32c2/src/apb_ctrl/sdio_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_CTRL")
-            .field(
-                "sdio_win_access_en",
-                &format_args!("{}", self.sdio_win_access_en().bit()),
-            )
+            .field("sdio_win_access_en", &self.sdio_win_access_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_sdio_win_access_en"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/spi_mem_pms_ctrl.rs b/esp32c2/src/apb_ctrl/spi_mem_pms_ctrl.rs
index 1198b6854f..046cf11d0d 100644
--- a/esp32c2/src/apb_ctrl/spi_mem_pms_ctrl.rs
+++ b/esp32c2/src/apb_ctrl/spi_mem_pms_ctrl.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_MEM_PMS_CTRL")
-            .field(
-                "spi_mem_reject_int",
-                &format_args!("{}", self.spi_mem_reject_int().bit()),
-            )
-            .field(
-                "spi_mem_reject_cde",
-                &format_args!("{}", self.spi_mem_reject_cde().bits()),
-            )
+            .field("spi_mem_reject_int", &self.spi_mem_reject_int())
+            .field("spi_mem_reject_cde", &self.spi_mem_reject_cde())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_MEM_PMS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - reg_spi_mem_reject_clr"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/spi_mem_reject_addr.rs b/esp32c2/src/apb_ctrl/spi_mem_reject_addr.rs
index 64c06819c5..6a50fedaae 100644
--- a/esp32c2/src/apb_ctrl/spi_mem_reject_addr.rs
+++ b/esp32c2/src/apb_ctrl/spi_mem_reject_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_MEM_REJECT_ADDR")
-            .field(
-                "spi_mem_reject_addr",
-                &format_args!("{}", self.spi_mem_reject_addr().bits()),
-            )
+            .field("spi_mem_reject_addr", &self.spi_mem_reject_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_MEM_REJECT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "APB_CTRL_SPI_MEM_REJECT_ADDR_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_reject_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_MEM_REJECT_ADDR_SPEC;
 impl crate::RegisterSpec for SPI_MEM_REJECT_ADDR_SPEC {
diff --git a/esp32c2/src/apb_ctrl/sysclk_conf.rs b/esp32c2/src/apb_ctrl/sysclk_conf.rs
index 8bae21435c..1d301eac95 100644
--- a/esp32c2/src/apb_ctrl/sysclk_conf.rs
+++ b/esp32c2/src/apb_ctrl/sysclk_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSCLK_CONF")
-            .field(
-                "pre_div_cnt",
-                &format_args!("{}", self.pre_div_cnt().bits()),
-            )
-            .field("clk_320m_en", &format_args!("{}", self.clk_320m_en().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "rst_tick_cnt",
-                &format_args!("{}", self.rst_tick_cnt().bit()),
-            )
+            .field("pre_div_cnt", &self.pre_div_cnt())
+            .field("clk_320m_en", &self.clk_320m_en())
+            .field("clk_en", &self.clk_en())
+            .field("rst_tick_cnt", &self.rst_tick_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - reg_pre_div_cnt"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/tick_conf.rs b/esp32c2/src/apb_ctrl/tick_conf.rs
index 8870955ad5..0b33674272 100644
--- a/esp32c2/src/apb_ctrl/tick_conf.rs
+++ b/esp32c2/src/apb_ctrl/tick_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TICK_CONF")
-            .field(
-                "xtal_tick_num",
-                &format_args!("{}", self.xtal_tick_num().bits()),
-            )
-            .field(
-                "ck8m_tick_num",
-                &format_args!("{}", self.ck8m_tick_num().bits()),
-            )
-            .field("tick_enable", &format_args!("{}", self.tick_enable().bit()))
+            .field("xtal_tick_num", &self.xtal_tick_num())
+            .field("ck8m_tick_num", &self.ck8m_tick_num())
+            .field("tick_enable", &self.tick_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TICK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - reg_xtal_tick_num"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/wifi_bb_cfg.rs b/esp32c2/src/apb_ctrl/wifi_bb_cfg.rs
index 47177b633e..330d15909b 100644
--- a/esp32c2/src/apb_ctrl/wifi_bb_cfg.rs
+++ b/esp32c2/src/apb_ctrl/wifi_bb_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_BB_CFG")
-            .field(
-                "wifi_bb_cfg",
-                &format_args!("{}", self.wifi_bb_cfg().bits()),
-            )
+            .field("wifi_bb_cfg", &self.wifi_bb_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_BB_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_wifi_bb_cfg"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/wifi_bb_cfg_2.rs b/esp32c2/src/apb_ctrl/wifi_bb_cfg_2.rs
index 8264944a2d..7dcd6cfe96 100644
--- a/esp32c2/src/apb_ctrl/wifi_bb_cfg_2.rs
+++ b/esp32c2/src/apb_ctrl/wifi_bb_cfg_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_BB_CFG_2")
-            .field(
-                "wifi_bb_cfg_2",
-                &format_args!("{}", self.wifi_bb_cfg_2().bits()),
-            )
+            .field("wifi_bb_cfg_2", &self.wifi_bb_cfg_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_BB_CFG_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_wifi_bb_cfg_2"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/wifi_clk_en.rs b/esp32c2/src/apb_ctrl/wifi_clk_en.rs
index 9f820ac8a9..7f04191acd 100644
--- a/esp32c2/src/apb_ctrl/wifi_clk_en.rs
+++ b/esp32c2/src/apb_ctrl/wifi_clk_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_CLK_EN")
-            .field(
-                "wifi_clk_en",
-                &format_args!("{}", self.wifi_clk_en().bits()),
-            )
+            .field("wifi_clk_en", &self.wifi_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_wifi_clk_en"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_ctrl/wifi_rst_en.rs b/esp32c2/src/apb_ctrl/wifi_rst_en.rs
index f43618ae81..e47449aef7 100644
--- a/esp32c2/src/apb_ctrl/wifi_rst_en.rs
+++ b/esp32c2/src/apb_ctrl/wifi_rst_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_RST_EN")
-            .field("wifi_rst", &format_args!("{}", self.wifi_rst().bits()))
+            .field("wifi_rst", &self.wifi_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_RST_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_wifi_rst"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/arb_ctrl.rs b/esp32c2/src/apb_saradc/arb_ctrl.rs
index 6369f6c219..70063d6aa2 100644
--- a/esp32c2/src/apb_saradc/arb_ctrl.rs
+++ b/esp32c2/src/apb_saradc/arb_ctrl.rs
@@ -80,35 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_CTRL")
-            .field("apb_force", &format_args!("{}", self.apb_force().bit()))
-            .field("rtc_force", &format_args!("{}", self.rtc_force().bit()))
-            .field("wifi_force", &format_args!("{}", self.wifi_force().bit()))
-            .field("grant_force", &format_args!("{}", self.grant_force().bit()))
-            .field(
-                "apb_priority",
-                &format_args!("{}", self.apb_priority().bits()),
-            )
-            .field(
-                "rtc_priority",
-                &format_args!("{}", self.rtc_priority().bits()),
-            )
-            .field(
-                "wifi_priority",
-                &format_args!("{}", self.wifi_priority().bits()),
-            )
-            .field(
-                "fix_priority",
-                &format_args!("{}", self.fix_priority().bit()),
-            )
+            .field("apb_force", &self.apb_force())
+            .field("rtc_force", &self.rtc_force())
+            .field("wifi_force", &self.wifi_force())
+            .field("grant_force", &self.grant_force())
+            .field("apb_priority", &self.apb_priority())
+            .field("rtc_priority", &self.rtc_priority())
+            .field("wifi_priority", &self.wifi_priority())
+            .field("fix_priority", &self.fix_priority())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - adc2 arbiter force to enableapb controller"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/cali.rs b/esp32c2/src/apb_saradc/cali.rs
index 1448a37ccf..8754349da9 100644
--- a/esp32c2/src/apb_saradc/cali.rs
+++ b/esp32c2/src/apb_saradc/cali.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CALI")
-            .field("cfg", &format_args!("{}", self.cfg().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CALI").field("cfg", &self.cfg()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/apb_saradc/clkm_conf.rs b/esp32c2/src/apb_saradc/clkm_conf.rs
index cf0152c6ec..9213a4e11c 100644
--- a/esp32c2/src/apb_saradc/clkm_conf.rs
+++ b/esp32c2/src/apb_saradc/clkm_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKM_CONF")
-            .field(
-                "clkm_div_num",
-                &format_args!("{}", self.clkm_div_num().bits()),
-            )
-            .field("clkm_div_b", &format_args!("{}", self.clkm_div_b().bits()))
-            .field("clkm_div_a", &format_args!("{}", self.clkm_div_a().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bits()))
+            .field("clkm_div_num", &self.clkm_div_num())
+            .field("clkm_div_b", &self.clkm_div_b())
+            .field("clkm_div_a", &self.clkm_div_a())
+            .field("clk_en", &self.clk_en())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral I2S clock divider value"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/ctrl.rs b/esp32c2/src/apb_saradc/ctrl.rs
index 509fd3b984..6bf0d955db 100644
--- a/esp32c2/src/apb_saradc/ctrl.rs
+++ b/esp32c2/src/apb_saradc/ctrl.rs
@@ -80,41 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("start_force", &format_args!("{}", self.start_force().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field(
-                "sar_clk_gated",
-                &format_args!("{}", self.sar_clk_gated().bit()),
-            )
-            .field(
-                "sar_clk_div",
-                &format_args!("{}", self.sar_clk_div().bits()),
-            )
-            .field(
-                "sar_patt_len",
-                &format_args!("{}", self.sar_patt_len().bits()),
-            )
-            .field(
-                "sar_patt_p_clear",
-                &format_args!("{}", self.sar_patt_p_clear().bit()),
-            )
-            .field(
-                "xpd_sar_force",
-                &format_args!("{}", self.xpd_sar_force().bits()),
-            )
-            .field(
-                "wait_arb_cycle",
-                &format_args!("{}", self.wait_arb_cycle().bits()),
-            )
+            .field("start_force", &self.start_force())
+            .field("start", &self.start())
+            .field("sar_clk_gated", &self.sar_clk_gated())
+            .field("sar_clk_div", &self.sar_clk_div())
+            .field("sar_patt_len", &self.sar_patt_len())
+            .field("sar_patt_p_clear", &self.sar_patt_p_clear())
+            .field("xpd_sar_force", &self.xpd_sar_force())
+            .field("wait_arb_cycle", &self.wait_arb_cycle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/ctrl2.rs b/esp32c2/src/apb_saradc/ctrl2.rs
index f3a390a86c..4391718400 100644
--- a/esp32c2/src/apb_saradc/ctrl2.rs
+++ b/esp32c2/src/apb_saradc/ctrl2.rs
@@ -62,30 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field(
-                "meas_num_limit",
-                &format_args!("{}", self.meas_num_limit().bit()),
-            )
-            .field(
-                "max_meas_num",
-                &format_args!("{}", self.max_meas_num().bits()),
-            )
-            .field("sar1_inv", &format_args!("{}", self.sar1_inv().bit()))
-            .field("sar2_inv", &format_args!("{}", self.sar2_inv().bit()))
-            .field(
-                "timer_target",
-                &format_args!("{}", self.timer_target().bits()),
-            )
-            .field("timer_en", &format_args!("{}", self.timer_en().bit()))
+            .field("meas_num_limit", &self.meas_num_limit())
+            .field("max_meas_num", &self.max_meas_num())
+            .field("sar1_inv", &self.sar1_inv())
+            .field("sar2_inv", &self.sar2_inv())
+            .field("timer_target", &self.timer_target())
+            .field("timer_en", &self.timer_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/ctrl_date.rs b/esp32c2/src/apb_saradc/ctrl_date.rs
index e2231c3d2c..90ac9d86c7 100644
--- a/esp32c2/src/apb_saradc/ctrl_date.rs
+++ b/esp32c2/src/apb_saradc/ctrl_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL_DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/dma_conf.rs b/esp32c2/src/apb_saradc/dma_conf.rs
index ef28162fc6..589363e6bb 100644
--- a/esp32c2/src/apb_saradc/dma_conf.rs
+++ b/esp32c2/src/apb_saradc/dma_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field(
-                "adc_eof_num",
-                &format_args!("{}", self.adc_eof_num().bits()),
-            )
-            .field(
-                "adc_reset_fsm",
-                &format_args!("{}", self.adc_reset_fsm().bit()),
-            )
-            .field("adc_trans", &format_args!("{}", self.adc_trans().bit()))
+            .field("adc_eof_num", &self.adc_eof_num())
+            .field("adc_reset_fsm", &self.adc_reset_fsm())
+            .field("adc_trans", &self.adc_trans())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - the dma_in_suc_eof gen when sample cnt = spi_eof_num"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/filter_ctrl0.rs b/esp32c2/src/apb_saradc/filter_ctrl0.rs
index 21dc62c282..5ca7189f30 100644
--- a/esp32c2/src/apb_saradc/filter_ctrl0.rs
+++ b/esp32c2/src/apb_saradc/filter_ctrl0.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CTRL0")
-            .field(
-                "filter_channel1",
-                &format_args!("{}", self.filter_channel1().bits()),
-            )
-            .field(
-                "filter_channel0",
-                &format_args!("{}", self.filter_channel0().bits()),
-            )
-            .field(
-                "filter_reset",
-                &format_args!("{}", self.filter_reset().bit()),
-            )
+            .field("filter_channel1", &self.filter_channel1())
+            .field("filter_channel0", &self.filter_channel0())
+            .field("filter_reset", &self.filter_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 18:21 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/filter_ctrl1.rs b/esp32c2/src/apb_saradc/filter_ctrl1.rs
index c7d161314c..96020331ca 100644
--- a/esp32c2/src/apb_saradc/filter_ctrl1.rs
+++ b/esp32c2/src/apb_saradc/filter_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CTRL1")
-            .field(
-                "filter_factor1",
-                &format_args!("{}", self.filter_factor1().bits()),
-            )
-            .field(
-                "filter_factor0",
-                &format_args!("{}", self.filter_factor0().bits()),
-            )
+            .field("filter_factor1", &self.filter_factor1())
+            .field("filter_factor0", &self.filter_factor0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 26:28 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/fsm_wait.rs b/esp32c2/src/apb_saradc/fsm_wait.rs
index 2fecade3c4..451a820ea1 100644
--- a/esp32c2/src/apb_saradc/fsm_wait.rs
+++ b/esp32c2/src/apb_saradc/fsm_wait.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_WAIT")
-            .field("xpd_wait", &format_args!("{}", self.xpd_wait().bits()))
-            .field("rstb_wait", &format_args!("{}", self.rstb_wait().bits()))
-            .field(
-                "standby_wait",
-                &format_args!("{}", self.standby_wait().bits()),
-            )
+            .field("xpd_wait", &self.xpd_wait())
+            .field("rstb_wait", &self.rstb_wait())
+            .field("standby_wait", &self.standby_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_WAIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/int_ena.rs b/esp32c2/src/apb_saradc/int_ena.rs
index 0b3ef2fc0c..011e126abb 100644
--- a/esp32c2/src/apb_saradc/int_ena.rs
+++ b/esp32c2/src/apb_saradc/int_ena.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/int_raw.rs b/esp32c2/src/apb_saradc/int_raw.rs
index d67f245c86..c7dea20f5d 100644
--- a/esp32c2/src/apb_saradc/int_raw.rs
+++ b/esp32c2/src/apb_saradc/int_raw.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32c2/src/apb_saradc/int_st.rs b/esp32c2/src/apb_saradc/int_st.rs
index 52a70230d9..f28dd0ea79 100644
--- a/esp32c2/src/apb_saradc/int_st.rs
+++ b/esp32c2/src/apb_saradc/int_st.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c2/src/apb_saradc/onetime_sample.rs b/esp32c2/src/apb_saradc/onetime_sample.rs
index 8a490f0dfd..4f44a31346 100644
--- a/esp32c2/src/apb_saradc/onetime_sample.rs
+++ b/esp32c2/src/apb_saradc/onetime_sample.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ONETIME_SAMPLE")
-            .field(
-                "onetime_atten",
-                &format_args!("{}", self.onetime_atten().bits()),
-            )
-            .field(
-                "onetime_channel",
-                &format_args!("{}", self.onetime_channel().bits()),
-            )
-            .field(
-                "onetime_start",
-                &format_args!("{}", self.onetime_start().bit()),
-            )
-            .field(
-                "saradc2_onetime_sample",
-                &format_args!("{}", self.saradc2_onetime_sample().bit()),
-            )
-            .field(
-                "saradc1_onetime_sample",
-                &format_args!("{}", self.saradc1_onetime_sample().bit()),
-            )
+            .field("onetime_atten", &self.onetime_atten())
+            .field("onetime_channel", &self.onetime_channel())
+            .field("onetime_start", &self.onetime_start())
+            .field("saradc2_onetime_sample", &self.saradc2_onetime_sample())
+            .field("saradc1_onetime_sample", &self.saradc1_onetime_sample())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ONETIME_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:24 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/sar1_status.rs b/esp32c2/src/apb_saradc/sar1_status.rs
index 23a6e85074..01acc25648 100644
--- a/esp32c2/src/apb_saradc/sar1_status.rs
+++ b/esp32c2/src/apb_saradc/sar1_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_STATUS")
-            .field(
-                "sar1_status",
-                &format_args!("{}", self.sar1_status().bits()),
-            )
+            .field("sar1_status", &self.sar1_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR1_STATUS_SPEC;
 impl crate::RegisterSpec for SAR1_STATUS_SPEC {
diff --git a/esp32c2/src/apb_saradc/sar1data_status.rs b/esp32c2/src/apb_saradc/sar1data_status.rs
index 87dc1868f8..f7518d9fac 100644
--- a/esp32c2/src/apb_saradc/sar1data_status.rs
+++ b/esp32c2/src/apb_saradc/sar1data_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1DATA_STATUS")
-            .field(
-                "saradc1_data",
-                &format_args!("{}", self.saradc1_data().bits()),
-            )
+            .field("saradc1_data", &self.saradc1_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1DATA_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1data_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR1DATA_STATUS_SPEC;
 impl crate::RegisterSpec for SAR1DATA_STATUS_SPEC {
diff --git a/esp32c2/src/apb_saradc/sar2_status.rs b/esp32c2/src/apb_saradc/sar2_status.rs
index 9c4caeaae0..600bf87661 100644
--- a/esp32c2/src/apb_saradc/sar2_status.rs
+++ b/esp32c2/src/apb_saradc/sar2_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_STATUS")
-            .field(
-                "sar2_status",
-                &format_args!("{}", self.sar2_status().bits()),
-            )
+            .field("sar2_status", &self.sar2_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR2_STATUS_SPEC;
 impl crate::RegisterSpec for SAR2_STATUS_SPEC {
diff --git a/esp32c2/src/apb_saradc/sar2data_status.rs b/esp32c2/src/apb_saradc/sar2data_status.rs
index 45adabf09a..fd214687dd 100644
--- a/esp32c2/src/apb_saradc/sar2data_status.rs
+++ b/esp32c2/src/apb_saradc/sar2data_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2DATA_STATUS")
-            .field(
-                "saradc2_data",
-                &format_args!("{}", self.saradc2_data().bits()),
-            )
+            .field("saradc2_data", &self.saradc2_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2DATA_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2data_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR2DATA_STATUS_SPEC;
 impl crate::RegisterSpec for SAR2DATA_STATUS_SPEC {
diff --git a/esp32c2/src/apb_saradc/sar_patt_tab1.rs b/esp32c2/src/apb_saradc/sar_patt_tab1.rs
index ecef0cd48d..6de2aa99a0 100644
--- a/esp32c2/src/apb_saradc/sar_patt_tab1.rs
+++ b/esp32c2/src/apb_saradc/sar_patt_tab1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_PATT_TAB1")
-            .field(
-                "sar_patt_tab1",
-                &format_args!("{}", self.sar_patt_tab1().bits()),
-            )
+            .field("sar_patt_tab1", &self.sar_patt_tab1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_PATT_TAB1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/sar_patt_tab2.rs b/esp32c2/src/apb_saradc/sar_patt_tab2.rs
index bd5fb33a29..8da9239b77 100644
--- a/esp32c2/src/apb_saradc/sar_patt_tab2.rs
+++ b/esp32c2/src/apb_saradc/sar_patt_tab2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_PATT_TAB2")
-            .field(
-                "sar_patt_tab2",
-                &format_args!("{}", self.sar_patt_tab2().bits()),
-            )
+            .field("sar_patt_tab2", &self.sar_patt_tab2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_PATT_TAB2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/thres0_ctrl.rs b/esp32c2/src/apb_saradc/thres0_ctrl.rs
index 516965dfab..dd90b1580a 100644
--- a/esp32c2/src/apb_saradc/thres0_ctrl.rs
+++ b/esp32c2/src/apb_saradc/thres0_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES0_CTRL")
-            .field(
-                "thres0_channel",
-                &format_args!("{}", self.thres0_channel().bits()),
-            )
-            .field(
-                "thres0_high",
-                &format_args!("{}", self.thres0_high().bits()),
-            )
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bits()))
+            .field("thres0_channel", &self.thres0_channel())
+            .field("thres0_high", &self.thres0_high())
+            .field("thres0_low", &self.thres0_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES0_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/thres1_ctrl.rs b/esp32c2/src/apb_saradc/thres1_ctrl.rs
index 0b582e13d1..b852d570e1 100644
--- a/esp32c2/src/apb_saradc/thres1_ctrl.rs
+++ b/esp32c2/src/apb_saradc/thres1_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES1_CTRL")
-            .field(
-                "thres1_channel",
-                &format_args!("{}", self.thres1_channel().bits()),
-            )
-            .field(
-                "thres1_high",
-                &format_args!("{}", self.thres1_high().bits()),
-            )
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bits()))
+            .field("thres1_channel", &self.thres1_channel())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres1_low", &self.thres1_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES1_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/thres_ctrl.rs b/esp32c2/src/apb_saradc/thres_ctrl.rs
index 7d5c67b874..237962c33f 100644
--- a/esp32c2/src/apb_saradc/thres_ctrl.rs
+++ b/esp32c2/src/apb_saradc/thres_ctrl.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES_CTRL")
-            .field(
-                "thres_all_en",
-                &format_args!("{}", self.thres_all_en().bit()),
-            )
-            .field("thres3_en", &format_args!("{}", self.thres3_en().bit()))
-            .field("thres2_en", &format_args!("{}", self.thres2_en().bit()))
-            .field("thres1_en", &format_args!("{}", self.thres1_en().bit()))
-            .field("thres0_en", &format_args!("{}", self.thres0_en().bit()))
+            .field("thres_all_en", &self.thres_all_en())
+            .field("thres3_en", &self.thres3_en())
+            .field("thres2_en", &self.thres2_en())
+            .field("thres1_en", &self.thres1_en())
+            .field("thres0_en", &self.thres0_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/tsens_ctrl.rs b/esp32c2/src/apb_saradc/tsens_ctrl.rs
index 6ada62fd97..a4fe2a0a1d 100644
--- a/esp32c2/src/apb_saradc/tsens_ctrl.rs
+++ b/esp32c2/src/apb_saradc/tsens_ctrl.rs
@@ -42,19 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSENS_CTRL")
-            .field("out", &format_args!("{}", self.out().bits()))
-            .field("in_inv", &format_args!("{}", self.in_inv().bit()))
-            .field("clk_div", &format_args!("{}", self.clk_div().bits()))
-            .field("pu", &format_args!("{}", self.pu().bit()))
+            .field("out", &self.out())
+            .field("in_inv", &self.in_inv())
+            .field("clk_div", &self.clk_div())
+            .field("pu", &self.pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSENS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/apb_saradc/tsens_ctrl2.rs b/esp32c2/src/apb_saradc/tsens_ctrl2.rs
index 53fd4214ea..286dc6fba9 100644
--- a/esp32c2/src/apb_saradc/tsens_ctrl2.rs
+++ b/esp32c2/src/apb_saradc/tsens_ctrl2.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSENS_CTRL2")
-            .field("xpd_wait", &format_args!("{}", self.xpd_wait().bits()))
-            .field("xpd_force", &format_args!("{}", self.xpd_force().bits()))
-            .field("clk_inv", &format_args!("{}", self.clk_inv().bit()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bit()))
+            .field("xpd_wait", &self.xpd_wait())
+            .field("xpd_force", &self.xpd_force())
+            .field("clk_inv", &self.clk_inv())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSENS_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/assist_debug/clock_gate.rs b/esp32c2/src/assist_debug/clock_gate.rs
index 00c587eb3d..7493f33190 100644
--- a/esp32c2/src/assist_debug/clock_gate.rs
+++ b/esp32c2/src/assist_debug/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - clock gate register"]
     #[inline(always)]
diff --git a/esp32c2/src/assist_debug/core_0_debug_mode.rs b/esp32c2/src/assist_debug/core_0_debug_mode.rs
index 7936884e12..3c11aaa92f 100644
--- a/esp32c2/src/assist_debug/core_0_debug_mode.rs
+++ b/esp32c2/src/assist_debug/core_0_debug_mode.rs
@@ -20,23 +20,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_DEBUG_MODE")
-            .field(
-                "core_0_debug_mode",
-                &format_args!("{}", self.core_0_debug_mode().bit()),
-            )
+            .field("core_0_debug_mode", &self.core_0_debug_mode())
             .field(
                 "core_0_debug_module_active",
-                &format_args!("{}", self.core_0_debug_module_active().bit()),
+                &self.core_0_debug_module_active(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DEBUG_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_debug_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DEBUG_MODE_SPEC;
 impl crate::RegisterSpec for CORE_0_DEBUG_MODE_SPEC {
diff --git a/esp32c2/src/assist_debug/core_0_intr_ena.rs b/esp32c2/src/assist_debug/core_0_intr_ena.rs
index d5fb94c41d..8a5e05982f 100644
--- a/esp32c2/src/assist_debug/core_0_intr_ena.rs
+++ b/esp32c2/src/assist_debug/core_0_intr_ena.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_INTR_ENA")
             .field(
                 "core_0_sp_spill_min_intr_ena",
-                &format_args!("{}", self.core_0_sp_spill_min_intr_ena().bit()),
+                &self.core_0_sp_spill_min_intr_ena(),
             )
             .field(
                 "core_0_sp_spill_max_intr_ena",
-                &format_args!("{}", self.core_0_sp_spill_max_intr_ena().bit()),
+                &self.core_0_sp_spill_max_intr_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_INTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enbale sp underlow monitor interrupt"]
     #[inline(always)]
diff --git a/esp32c2/src/assist_debug/core_0_intr_raw.rs b/esp32c2/src/assist_debug/core_0_intr_raw.rs
index 208738d0b2..8183ade767 100644
--- a/esp32c2/src/assist_debug/core_0_intr_raw.rs
+++ b/esp32c2/src/assist_debug/core_0_intr_raw.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_INTR_RAW")
-            .field(
-                "core_0_sp_spill_min_raw",
-                &format_args!("{}", self.core_0_sp_spill_min_raw().bit()),
-            )
-            .field(
-                "core_0_sp_spill_max_raw",
-                &format_args!("{}", self.core_0_sp_spill_max_raw().bit()),
-            )
+            .field("core_0_sp_spill_min_raw", &self.core_0_sp_spill_min_raw())
+            .field("core_0_sp_spill_max_raw", &self.core_0_sp_spill_max_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_INTR_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 monitor interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_intr_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_INTR_RAW_SPEC;
 impl crate::RegisterSpec for CORE_0_INTR_RAW_SPEC {
diff --git a/esp32c2/src/assist_debug/core_0_lastpc_before_exception.rs b/esp32c2/src/assist_debug/core_0_lastpc_before_exception.rs
index c785394f03..7e8b529461 100644
--- a/esp32c2/src/assist_debug/core_0_lastpc_before_exception.rs
+++ b/esp32c2/src/assist_debug/core_0_lastpc_before_exception.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_LASTPC_BEFORE_EXCEPTION")
-            .field(
-                "core_0_lastpc_before_exc",
-                &format_args!("{}", self.core_0_lastpc_before_exc().bits()),
-            )
+            .field("core_0_lastpc_before_exc", &self.core_0_lastpc_before_exc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_LASTPC_BEFORE_EXCEPTION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_lastpc_before_exception::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_LASTPC_BEFORE_EXCEPTION_SPEC;
 impl crate::RegisterSpec for CORE_0_LASTPC_BEFORE_EXCEPTION_SPEC {
diff --git a/esp32c2/src/assist_debug/core_0_montr_ena.rs b/esp32c2/src/assist_debug/core_0_montr_ena.rs
index a1e1380ed8..876d4a4919 100644
--- a/esp32c2/src/assist_debug/core_0_montr_ena.rs
+++ b/esp32c2/src/assist_debug/core_0_montr_ena.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_MONTR_ENA")
-            .field(
-                "core_0_sp_spill_min_ena",
-                &format_args!("{}", self.core_0_sp_spill_min_ena().bit()),
-            )
-            .field(
-                "core_0_sp_spill_max_ena",
-                &format_args!("{}", self.core_0_sp_spill_max_ena().bit()),
-            )
+            .field("core_0_sp_spill_min_ena", &self.core_0_sp_spill_min_ena())
+            .field("core_0_sp_spill_max_ena", &self.core_0_sp_spill_max_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_MONTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enbale sp underlow monitor"]
     #[inline(always)]
diff --git a/esp32c2/src/assist_debug/core_0_rcd_en.rs b/esp32c2/src/assist_debug/core_0_rcd_en.rs
index c32ca92cbc..8a365dc63d 100644
--- a/esp32c2/src/assist_debug/core_0_rcd_en.rs
+++ b/esp32c2/src/assist_debug/core_0_rcd_en.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_EN")
-            .field(
-                "core_0_rcd_recorden",
-                &format_args!("{}", self.core_0_rcd_recorden().bit()),
-            )
-            .field(
-                "core_0_rcd_pdebugen",
-                &format_args!("{}", self.core_0_rcd_pdebugen().bit()),
-            )
+            .field("core_0_rcd_recorden", &self.core_0_rcd_recorden())
+            .field("core_0_rcd_pdebugen", &self.core_0_rcd_pdebugen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable record PC"]
     #[inline(always)]
diff --git a/esp32c2/src/assist_debug/core_0_rcd_pdebugpc.rs b/esp32c2/src/assist_debug/core_0_rcd_pdebugpc.rs
index 57525f3096..f683fc645a 100644
--- a/esp32c2/src/assist_debug/core_0_rcd_pdebugpc.rs
+++ b/esp32c2/src/assist_debug/core_0_rcd_pdebugpc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGPC")
-            .field(
-                "core_0_rcd_pdebugpc",
-                &format_args!("{}", self.core_0_rcd_pdebugpc().bits()),
-            )
+            .field("core_0_rcd_pdebugpc", &self.core_0_rcd_pdebugpc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGPC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugpc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGPC_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGPC_SPEC {
diff --git a/esp32c2/src/assist_debug/core_0_rcd_pdebugsp.rs b/esp32c2/src/assist_debug/core_0_rcd_pdebugsp.rs
index 5299a97c98..acd394b30c 100644
--- a/esp32c2/src/assist_debug/core_0_rcd_pdebugsp.rs
+++ b/esp32c2/src/assist_debug/core_0_rcd_pdebugsp.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGSP")
-            .field(
-                "core_0_rcd_pdebugsp",
-                &format_args!("{}", self.core_0_rcd_pdebugsp().bits()),
-            )
+            .field("core_0_rcd_pdebugsp", &self.core_0_rcd_pdebugsp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGSP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugsp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGSP_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGSP_SPEC {
diff --git a/esp32c2/src/assist_debug/core_0_sp_max.rs b/esp32c2/src/assist_debug/core_0_sp_max.rs
index 551ad6e6e3..33cb4259d1 100644
--- a/esp32c2/src/assist_debug/core_0_sp_max.rs
+++ b/esp32c2/src/assist_debug/core_0_sp_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_MAX")
-            .field(
-                "core_0_sp_max",
-                &format_args!("{}", self.core_0_sp_max().bits()),
-            )
+            .field("core_0_sp_max", &self.core_0_sp_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - core0 sp pc status register"]
     #[inline(always)]
diff --git a/esp32c2/src/assist_debug/core_0_sp_min.rs b/esp32c2/src/assist_debug/core_0_sp_min.rs
index 385b8a1a99..5ab4adde01 100644
--- a/esp32c2/src/assist_debug/core_0_sp_min.rs
+++ b/esp32c2/src/assist_debug/core_0_sp_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_MIN")
-            .field(
-                "core_0_sp_min",
-                &format_args!("{}", self.core_0_sp_min().bits()),
-            )
+            .field("core_0_sp_min", &self.core_0_sp_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - core0 sp region configuration regsiter"]
     #[inline(always)]
diff --git a/esp32c2/src/assist_debug/core_0_sp_pc.rs b/esp32c2/src/assist_debug/core_0_sp_pc.rs
index edb35da31e..a876b3c942 100644
--- a/esp32c2/src/assist_debug/core_0_sp_pc.rs
+++ b/esp32c2/src/assist_debug/core_0_sp_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_PC")
-            .field(
-                "core_0_sp_pc",
-                &format_args!("{}", self.core_0_sp_pc().bits()),
-            )
+            .field("core_0_sp_pc", &self.core_0_sp_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "stack monitor pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_sp_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_SP_PC_SPEC;
 impl crate::RegisterSpec for CORE_0_SP_PC_SPEC {
diff --git a/esp32c2/src/assist_debug/date.rs b/esp32c2/src/assist_debug/date.rs
index 67d55d67d7..b99111644b 100644
--- a/esp32c2/src/assist_debug/date.rs
+++ b/esp32c2/src/assist_debug/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/bb/bbpd_ctrl.rs b/esp32c2/src/bb/bbpd_ctrl.rs
index 7e31e667bb..28cf2656e4 100644
--- a/esp32c2/src/bb/bbpd_ctrl.rs
+++ b/esp32c2/src/bb/bbpd_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BBPD_CTRL")
-            .field(
-                "dc_est_force_pd",
-                &format_args!("{}", self.dc_est_force_pd().bit()),
-            )
-            .field(
-                "dc_est_force_pu",
-                &format_args!("{}", self.dc_est_force_pu().bit()),
-            )
-            .field(
-                "fft_force_pd",
-                &format_args!("{}", self.fft_force_pd().bit()),
-            )
-            .field(
-                "fft_force_pu",
-                &format_args!("{}", self.fft_force_pu().bit()),
-            )
+            .field("dc_est_force_pd", &self.dc_est_force_pd())
+            .field("dc_est_force_pu", &self.dc_est_force_pu())
+            .field("fft_force_pd", &self.fft_force_pd())
+            .field("fft_force_pu", &self.fft_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BBPD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c2/src/dma/ahb_test.rs b/esp32c2/src/dma/ahb_test.rs
index a5ac5899ab..27da2686f3 100644
--- a/esp32c2/src/dma/ahb_test.rs
+++ b/esp32c2/src/dma/ahb_test.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_TEST")
-            .field(
-                "ahb_testmode",
-                &format_args!("{}", self.ahb_testmode().bits()),
-            )
-            .field(
-                "ahb_testaddr",
-                &format_args!("{}", self.ahb_testaddr().bits()),
-            )
+            .field("ahb_testmode", &self.ahb_testmode())
+            .field("ahb_testaddr", &self.ahb_testaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_TEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - reserved"]
     #[inline(always)]
diff --git a/esp32c2/src/dma/ch/in_conf0.rs b/esp32c2/src/dma/ch/in_conf0.rs
index 86cecf5d9f..4cd323f5d3 100644
--- a/esp32c2/src/dma/ch/in_conf0.rs
+++ b/esp32c2/src/dma/ch/in_conf0.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF0")
-            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
-            .field(
-                "in_loop_test",
-                &format_args!("{}", self.in_loop_test().bit()),
-            )
-            .field(
-                "indscr_burst_en",
-                &format_args!("{}", self.indscr_burst_en().bit()),
-            )
-            .field(
-                "in_data_burst_en",
-                &format_args!("{}", self.in_data_burst_en().bit()),
-            )
-            .field(
-                "mem_trans_en",
-                &format_args!("{}", self.mem_trans_en().bit()),
-            )
+            .field("in_rst", &self.in_rst())
+            .field("in_loop_test", &self.in_loop_test())
+            .field("indscr_burst_en", &self.indscr_burst_en())
+            .field("in_data_burst_en", &self.in_data_burst_en())
+            .field("mem_trans_en", &self.mem_trans_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
     #[inline(always)]
diff --git a/esp32c2/src/dma/ch/in_conf1.rs b/esp32c2/src/dma/ch/in_conf1.rs
index 748835195a..b974c77057 100644
--- a/esp32c2/src/dma/ch/in_conf1.rs
+++ b/esp32c2/src/dma/ch/in_conf1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF1")
-            .field(
-                "in_check_owner",
-                &format_args!("{}", self.in_check_owner().bit()),
-            )
+            .field("in_check_owner", &self.in_check_owner())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
diff --git a/esp32c2/src/dma/ch/in_dscr.rs b/esp32c2/src/dma/ch/in_dscr.rs
index e74ef4e6cd..56c85914b1 100644
--- a/esp32c2/src/dma/ch/in_dscr.rs
+++ b/esp32c2/src/dma/ch/in_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR")
-            .field(
-                "inlink_dscr",
-                &format_args!("{}", self.inlink_dscr().bits()),
-            )
+            .field("inlink_dscr", &self.inlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_IN_DSCR_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_SPEC;
 impl crate::RegisterSpec for IN_DSCR_SPEC {
diff --git a/esp32c2/src/dma/ch/in_dscr_bf0.rs b/esp32c2/src/dma/ch/in_dscr_bf0.rs
index eaad9c8cc9..0bc2f59f68 100644
--- a/esp32c2/src/dma/ch/in_dscr_bf0.rs
+++ b/esp32c2/src/dma/ch/in_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF0")
-            .field(
-                "inlink_dscr_bf0",
-                &format_args!("{}", self.inlink_dscr_bf0().bits()),
-            )
+            .field("inlink_dscr_bf0", &self.inlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_IN_DSCR_BF0_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for IN_DSCR_BF0_SPEC {
diff --git a/esp32c2/src/dma/ch/in_dscr_bf1.rs b/esp32c2/src/dma/ch/in_dscr_bf1.rs
index 6fd8b46b77..d11bdd1b7a 100644
--- a/esp32c2/src/dma/ch/in_dscr_bf1.rs
+++ b/esp32c2/src/dma/ch/in_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF1")
-            .field(
-                "inlink_dscr_bf1",
-                &format_args!("{}", self.inlink_dscr_bf1().bits()),
-            )
+            .field("inlink_dscr_bf1", &self.inlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_IN_DSCR_BF1_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for IN_DSCR_BF1_SPEC {
diff --git a/esp32c2/src/dma/ch/in_err_eof_des_addr.rs b/esp32c2/src/dma/ch/in_err_eof_des_addr.rs
index 139a0113da..8bb5db9ad4 100644
--- a/esp32c2/src/dma/ch/in_err_eof_des_addr.rs
+++ b/esp32c2/src/dma/ch/in_err_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_ERR_EOF_DES_ADDR")
-            .field(
-                "in_err_eof_des_addr",
-                &format_args!("{}", self.in_err_eof_des_addr().bits()),
-            )
+            .field("in_err_eof_des_addr", &self.in_err_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_ERR_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_ERR_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_SPEC {
diff --git a/esp32c2/src/dma/ch/in_link.rs b/esp32c2/src/dma/ch/in_link.rs
index cafde6fdeb..b93d563052 100644
--- a/esp32c2/src/dma/ch/in_link.rs
+++ b/esp32c2/src/dma/ch/in_link.rs
@@ -60,33 +60,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_LINK")
-            .field(
-                "inlink_addr",
-                &format_args!("{}", self.inlink_addr().bits()),
-            )
-            .field(
-                "inlink_auto_ret",
-                &format_args!("{}", self.inlink_auto_ret().bit()),
-            )
-            .field("inlink_stop", &format_args!("{}", self.inlink_stop().bit()))
-            .field(
-                "inlink_start",
-                &format_args!("{}", self.inlink_start().bit()),
-            )
-            .field(
-                "inlink_restart",
-                &format_args!("{}", self.inlink_restart().bit()),
-            )
-            .field("inlink_park", &format_args!("{}", self.inlink_park().bit()))
+            .field("inlink_addr", &self.inlink_addr())
+            .field("inlink_auto_ret", &self.inlink_auto_ret())
+            .field("inlink_stop", &self.inlink_stop())
+            .field("inlink_start", &self.inlink_start())
+            .field("inlink_restart", &self.inlink_restart())
+            .field("inlink_park", &self.inlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32c2/src/dma/ch/in_peri_sel.rs b/esp32c2/src/dma/ch/in_peri_sel.rs
index faae5ed134..c8c7bee389 100644
--- a/esp32c2/src/dma/ch/in_peri_sel.rs
+++ b/esp32c2/src/dma/ch/in_peri_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_PERI_SEL")
-            .field(
-                "peri_in_sel",
-                &format_args!("{}", self.peri_in_sel().bits()),
-            )
+            .field("peri_in_sel", &self.peri_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_PERI_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."]
     #[inline(always)]
diff --git a/esp32c2/src/dma/ch/in_pop.rs b/esp32c2/src/dma/ch/in_pop.rs
index 9ea3ea9034..99fd4feca3 100644
--- a/esp32c2/src/dma/ch/in_pop.rs
+++ b/esp32c2/src/dma/ch/in_pop.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_POP")
-            .field(
-                "infifo_rdata",
-                &format_args!("{}", self.infifo_rdata().bits()),
-            )
-            .field("infifo_pop", &format_args!("{}", self.infifo_pop().bit()))
+            .field("infifo_rdata", &self.infifo_rdata())
+            .field("infifo_pop", &self.infifo_pop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_POP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."]
     #[inline(always)]
diff --git a/esp32c2/src/dma/ch/in_pri.rs b/esp32c2/src/dma/ch/in_pri.rs
index e8c8c8ce27..f2e9585ca5 100644
--- a/esp32c2/src/dma/ch/in_pri.rs
+++ b/esp32c2/src/dma/ch/in_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_PRI")
-            .field("rx_pri", &format_args!("{}", self.rx_pri().bits()))
+            .field("rx_pri", &self.rx_pri())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value, the higher of the priority."]
     #[inline(always)]
diff --git a/esp32c2/src/dma/ch/in_state.rs b/esp32c2/src/dma/ch/in_state.rs
index 4c9e8154ef..a0a70a2e6d 100644
--- a/esp32c2/src/dma/ch/in_state.rs
+++ b/esp32c2/src/dma/ch/in_state.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_STATE")
-            .field(
-                "inlink_dscr_addr",
-                &format_args!("{}", self.inlink_dscr_addr().bits()),
-            )
-            .field(
-                "in_dscr_state",
-                &format_args!("{}", self.in_dscr_state().bits()),
-            )
-            .field("in_state", &format_args!("{}", self.in_state().bits()))
+            .field("inlink_dscr_addr", &self.inlink_dscr_addr())
+            .field("in_dscr_state", &self.in_dscr_state())
+            .field("in_state", &self.in_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_IN_STATE_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_STATE_SPEC;
 impl crate::RegisterSpec for IN_STATE_SPEC {
diff --git a/esp32c2/src/dma/ch/in_suc_eof_des_addr.rs b/esp32c2/src/dma/ch/in_suc_eof_des_addr.rs
index 2858f6eae2..a669061d06 100644
--- a/esp32c2/src/dma/ch/in_suc_eof_des_addr.rs
+++ b/esp32c2/src/dma/ch/in_suc_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_SUC_EOF_DES_ADDR")
-            .field(
-                "in_suc_eof_des_addr",
-                &format_args!("{}", self.in_suc_eof_des_addr().bits()),
-            )
+            .field("in_suc_eof_des_addr", &self.in_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SUC_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SUC_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_SPEC {
diff --git a/esp32c2/src/dma/ch/infifo_status.rs b/esp32c2/src/dma/ch/infifo_status.rs
index c789296be5..e1e405141c 100644
--- a/esp32c2/src/dma/ch/infifo_status.rs
+++ b/esp32c2/src/dma/ch/infifo_status.rs
@@ -62,41 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INFIFO_STATUS")
-            .field("infifo_full", &format_args!("{}", self.infifo_full().bit()))
-            .field(
-                "infifo_empty",
-                &format_args!("{}", self.infifo_empty().bit()),
-            )
-            .field("infifo_cnt", &format_args!("{}", self.infifo_cnt().bits()))
-            .field(
-                "in_remain_under_1b",
-                &format_args!("{}", self.in_remain_under_1b().bit()),
-            )
-            .field(
-                "in_remain_under_2b",
-                &format_args!("{}", self.in_remain_under_2b().bit()),
-            )
-            .field(
-                "in_remain_under_3b",
-                &format_args!("{}", self.in_remain_under_3b().bit()),
-            )
-            .field(
-                "in_remain_under_4b",
-                &format_args!("{}", self.in_remain_under_4b().bit()),
-            )
-            .field(
-                "in_buf_hungry",
-                &format_args!("{}", self.in_buf_hungry().bit()),
-            )
+            .field("infifo_full", &self.infifo_full())
+            .field("infifo_empty", &self.infifo_empty())
+            .field("infifo_cnt", &self.infifo_cnt())
+            .field("in_remain_under_1b", &self.in_remain_under_1b())
+            .field("in_remain_under_2b", &self.in_remain_under_2b())
+            .field("in_remain_under_3b", &self.in_remain_under_3b())
+            .field("in_remain_under_4b", &self.in_remain_under_4b())
+            .field("in_buf_hungry", &self.in_buf_hungry())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_INFIFO_STATUS_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for INFIFO_STATUS_SPEC {
diff --git a/esp32c2/src/dma/ch/out_conf0.rs b/esp32c2/src/dma/ch/out_conf0.rs
index e9b56e54df..093cf4b2e7 100644
--- a/esp32c2/src/dma/ch/out_conf0.rs
+++ b/esp32c2/src/dma/ch/out_conf0.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CONF0")
-            .field("out_rst", &format_args!("{}", self.out_rst().bit()))
-            .field(
-                "out_loop_test",
-                &format_args!("{}", self.out_loop_test().bit()),
-            )
-            .field(
-                "out_auto_wrback",
-                &format_args!("{}", self.out_auto_wrback().bit()),
-            )
-            .field(
-                "out_eof_mode",
-                &format_args!("{}", self.out_eof_mode().bit()),
-            )
-            .field(
-                "outdscr_burst_en",
-                &format_args!("{}", self.outdscr_burst_en().bit()),
-            )
-            .field(
-                "out_data_burst_en",
-                &format_args!("{}", self.out_data_burst_en().bit()),
-            )
+            .field("out_rst", &self.out_rst())
+            .field("out_loop_test", &self.out_loop_test())
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("out_eof_mode", &self.out_eof_mode())
+            .field("outdscr_burst_en", &self.outdscr_burst_en())
+            .field("out_data_burst_en", &self.out_data_burst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."]
     #[inline(always)]
diff --git a/esp32c2/src/dma/ch/out_conf1.rs b/esp32c2/src/dma/ch/out_conf1.rs
index ef66aafcff..cc807db11c 100644
--- a/esp32c2/src/dma/ch/out_conf1.rs
+++ b/esp32c2/src/dma/ch/out_conf1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CONF1")
-            .field(
-                "out_check_owner",
-                &format_args!("{}", self.out_check_owner().bit()),
-            )
+            .field("out_check_owner", &self.out_check_owner())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
diff --git a/esp32c2/src/dma/ch/out_dscr.rs b/esp32c2/src/dma/ch/out_dscr.rs
index 48eb84fb2a..333c3c8faf 100644
--- a/esp32c2/src/dma/ch/out_dscr.rs
+++ b/esp32c2/src/dma/ch/out_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR")
-            .field(
-                "outlink_dscr",
-                &format_args!("{}", self.outlink_dscr().bits()),
-            )
+            .field("outlink_dscr", &self.outlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_OUT_DSCR_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_SPEC {
diff --git a/esp32c2/src/dma/ch/out_dscr_bf0.rs b/esp32c2/src/dma/ch/out_dscr_bf0.rs
index 920aa77731..ad66c7d030 100644
--- a/esp32c2/src/dma/ch/out_dscr_bf0.rs
+++ b/esp32c2/src/dma/ch/out_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR_BF0")
-            .field(
-                "outlink_dscr_bf0",
-                &format_args!("{}", self.outlink_dscr_bf0().bits()),
-            )
+            .field("outlink_dscr_bf0", &self.outlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_OUT_DSCR_BF0_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_BF0_SPEC {
diff --git a/esp32c2/src/dma/ch/out_dscr_bf1.rs b/esp32c2/src/dma/ch/out_dscr_bf1.rs
index 832e1d146f..229b0c1196 100644
--- a/esp32c2/src/dma/ch/out_dscr_bf1.rs
+++ b/esp32c2/src/dma/ch/out_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR_BF1")
-            .field(
-                "outlink_dscr_bf1",
-                &format_args!("{}", self.outlink_dscr_bf1().bits()),
-            )
+            .field("outlink_dscr_bf1", &self.outlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_OUT_DSCR_BF1_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_BF1_SPEC {
diff --git a/esp32c2/src/dma/ch/out_eof_bfr_des_addr.rs b/esp32c2/src/dma/ch/out_eof_bfr_des_addr.rs
index bf376f49d0..0d89d6c0fa 100644
--- a/esp32c2/src/dma/ch/out_eof_bfr_des_addr.rs
+++ b/esp32c2/src/dma/ch/out_eof_bfr_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_BFR_DES_ADDR")
-            .field(
-                "out_eof_bfr_des_addr",
-                &format_args!("{}", self.out_eof_bfr_des_addr().bits()),
-            )
+            .field("out_eof_bfr_des_addr", &self.out_eof_bfr_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_BFR_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_bfr_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_BFR_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_SPEC {
diff --git a/esp32c2/src/dma/ch/out_eof_des_addr.rs b/esp32c2/src/dma/ch/out_eof_des_addr.rs
index af80ad16ae..dd9c7dc379 100644
--- a/esp32c2/src/dma/ch/out_eof_des_addr.rs
+++ b/esp32c2/src/dma/ch/out_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_DES_ADDR")
-            .field(
-                "out_eof_des_addr",
-                &format_args!("{}", self.out_eof_des_addr().bits()),
-            )
+            .field("out_eof_des_addr", &self.out_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_OUT_EOF_DES_ADDR_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_DES_ADDR_SPEC {
diff --git a/esp32c2/src/dma/ch/out_link.rs b/esp32c2/src/dma/ch/out_link.rs
index 7a7b8b99a3..bfeb1647d5 100644
--- a/esp32c2/src/dma/ch/out_link.rs
+++ b/esp32c2/src/dma/ch/out_link.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_LINK")
-            .field(
-                "outlink_addr",
-                &format_args!("{}", self.outlink_addr().bits()),
-            )
-            .field(
-                "outlink_stop",
-                &format_args!("{}", self.outlink_stop().bit()),
-            )
-            .field(
-                "outlink_start",
-                &format_args!("{}", self.outlink_start().bit()),
-            )
-            .field(
-                "outlink_restart",
-                &format_args!("{}", self.outlink_restart().bit()),
-            )
-            .field(
-                "outlink_park",
-                &format_args!("{}", self.outlink_park().bit()),
-            )
+            .field("outlink_addr", &self.outlink_addr())
+            .field("outlink_stop", &self.outlink_stop())
+            .field("outlink_start", &self.outlink_start())
+            .field("outlink_restart", &self.outlink_restart())
+            .field("outlink_park", &self.outlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32c2/src/dma/ch/out_peri_sel.rs b/esp32c2/src/dma/ch/out_peri_sel.rs
index bb9eeb200a..07816e8dcd 100644
--- a/esp32c2/src/dma/ch/out_peri_sel.rs
+++ b/esp32c2/src/dma/ch/out_peri_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PERI_SEL")
-            .field(
-                "peri_out_sel",
-                &format_args!("{}", self.peri_out_sel().bits()),
-            )
+            .field("peri_out_sel", &self.peri_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PERI_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."]
     #[inline(always)]
diff --git a/esp32c2/src/dma/ch/out_pri.rs b/esp32c2/src/dma/ch/out_pri.rs
index 5ea7f98279..bbdb19628c 100644
--- a/esp32c2/src/dma/ch/out_pri.rs
+++ b/esp32c2/src/dma/ch/out_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PRI")
-            .field("tx_pri", &format_args!("{}", self.tx_pri().bits()))
+            .field("tx_pri", &self.tx_pri())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value, the higher of the priority."]
     #[inline(always)]
diff --git a/esp32c2/src/dma/ch/out_push.rs b/esp32c2/src/dma/ch/out_push.rs
index 9489e7584a..13d4f3a1a1 100644
--- a/esp32c2/src/dma/ch/out_push.rs
+++ b/esp32c2/src/dma/ch/out_push.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PUSH")
-            .field(
-                "outfifo_wdata",
-                &format_args!("{}", self.outfifo_wdata().bits()),
-            )
-            .field(
-                "outfifo_push",
-                &format_args!("{}", self.outfifo_push().bit()),
-            )
+            .field("outfifo_wdata", &self.outfifo_wdata())
+            .field("outfifo_push", &self.outfifo_push())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PUSH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."]
     #[inline(always)]
diff --git a/esp32c2/src/dma/ch/out_state.rs b/esp32c2/src/dma/ch/out_state.rs
index eac446b3fe..ff7cd28120 100644
--- a/esp32c2/src/dma/ch/out_state.rs
+++ b/esp32c2/src/dma/ch/out_state.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_STATE")
-            .field(
-                "outlink_dscr_addr",
-                &format_args!("{}", self.outlink_dscr_addr().bits()),
-            )
-            .field(
-                "out_dscr_state",
-                &format_args!("{}", self.out_dscr_state().bits()),
-            )
-            .field("out_state", &format_args!("{}", self.out_state().bits()))
+            .field("outlink_dscr_addr", &self.outlink_dscr_addr())
+            .field("out_dscr_state", &self.out_dscr_state())
+            .field("out_state", &self.out_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_OUT_STATE_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_STATE_SPEC;
 impl crate::RegisterSpec for OUT_STATE_SPEC {
diff --git a/esp32c2/src/dma/ch/outfifo_status.rs b/esp32c2/src/dma/ch/outfifo_status.rs
index 041edec34d..03becc8d02 100644
--- a/esp32c2/src/dma/ch/outfifo_status.rs
+++ b/esp32c2/src/dma/ch/outfifo_status.rs
@@ -55,43 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTFIFO_STATUS")
-            .field(
-                "outfifo_full",
-                &format_args!("{}", self.outfifo_full().bit()),
-            )
-            .field(
-                "outfifo_empty",
-                &format_args!("{}", self.outfifo_empty().bit()),
-            )
-            .field(
-                "outfifo_cnt",
-                &format_args!("{}", self.outfifo_cnt().bits()),
-            )
-            .field(
-                "out_remain_under_1b",
-                &format_args!("{}", self.out_remain_under_1b().bit()),
-            )
-            .field(
-                "out_remain_under_2b",
-                &format_args!("{}", self.out_remain_under_2b().bit()),
-            )
-            .field(
-                "out_remain_under_3b",
-                &format_args!("{}", self.out_remain_under_3b().bit()),
-            )
-            .field(
-                "out_remain_under_4b",
-                &format_args!("{}", self.out_remain_under_4b().bit()),
-            )
+            .field("outfifo_full", &self.outfifo_full())
+            .field("outfifo_empty", &self.outfifo_empty())
+            .field("outfifo_cnt", &self.outfifo_cnt())
+            .field("out_remain_under_1b", &self.out_remain_under_1b())
+            .field("out_remain_under_2b", &self.out_remain_under_2b())
+            .field("out_remain_under_3b", &self.out_remain_under_3b())
+            .field("out_remain_under_4b", &self.out_remain_under_4b())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_OUTFIFO_STATUS_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for OUTFIFO_STATUS_SPEC {
diff --git a/esp32c2/src/dma/date.rs b/esp32c2/src/dma/date.rs
index f2369dab2e..f6935f3415 100644
--- a/esp32c2/src/dma/date.rs
+++ b/esp32c2/src/dma/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/dma/int_ch/ena.rs b/esp32c2/src/dma/int_ch/ena.rs
index dde917e343..4722681149 100644
--- a/esp32c2/src/dma/int_ch/ena.rs
+++ b/esp32c2/src/dma/int_ch/ena.rs
@@ -125,37 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENA")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c2/src/dma/int_ch/raw.rs b/esp32c2/src/dma/int_ch/raw.rs
index fdfe355480..cffd672123 100644
--- a/esp32c2/src/dma/int_ch/raw.rs
+++ b/esp32c2/src/dma/int_ch/raw.rs
@@ -125,37 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RAW")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
     #[inline(always)]
diff --git a/esp32c2/src/dma/int_ch/st.rs b/esp32c2/src/dma/int_ch/st.rs
index b5efca6c32..53f8894444 100644
--- a/esp32c2/src/dma/int_ch/st.rs
+++ b/esp32c2/src/dma/int_ch/st.rs
@@ -97,37 +97,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ST")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_INT_ST_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ST_SPEC;
 impl crate::RegisterSpec for ST_SPEC {
diff --git a/esp32c2/src/dma/misc_conf.rs b/esp32c2/src/dma/misc_conf.rs
index d3c2265842..d9a0cd0b79 100644
--- a/esp32c2/src/dma/misc_conf.rs
+++ b/esp32c2/src/dma/misc_conf.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC_CONF")
-            .field(
-                "ahbm_rst_inter",
-                &format_args!("{}", self.ahbm_rst_inter().bit()),
-            )
-            .field("arb_pri_dis", &format_args!("{}", self.arb_pri_dis().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("ahbm_rst_inter", &self.ahbm_rst_inter())
+            .field("arb_pri_dis", &self.arb_pri_dis())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit, then clear this bit to reset the internal ahb FSM."]
     #[inline(always)]
diff --git a/esp32c2/src/ecc/k_mem.rs b/esp32c2/src/ecc/k_mem.rs
index 0931b81173..8e55d12095 100644
--- a/esp32c2/src/ecc/k_mem.rs
+++ b/esp32c2/src/ecc/k_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<K_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores k.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`k_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`k_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct K_MEM_SPEC;
diff --git a/esp32c2/src/ecc/mult_conf.rs b/esp32c2/src/ecc/mult_conf.rs
index a715ff5b1a..2c52076b40 100644
--- a/esp32c2/src/ecc/mult_conf.rs
+++ b/esp32c2/src/ecc/mult_conf.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_CONF")
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("key_length", &format_args!("{}", self.key_length().bit()))
-            .field(
-                "security_mode",
-                &format_args!("{}", self.security_mode().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("work_mode", &format_args!("{}", self.work_mode().bits()))
-            .field(
-                "verification_result",
-                &format_args!("{}", self.verification_result().bit()),
-            )
+            .field("start", &self.start())
+            .field("key_length", &self.key_length())
+            .field("security_mode", &self.security_mode())
+            .field("clk_en", &self.clk_en())
+            .field("work_mode", &self.work_mode())
+            .field("verification_result", &self.verification_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset receiver"]
     #[inline(always)]
diff --git a/esp32c2/src/ecc/mult_date.rs b/esp32c2/src/ecc/mult_date.rs
index 4394b7e0ca..ef5728625a 100644
--- a/esp32c2/src/ecc/mult_date.rs
+++ b/esp32c2/src/ecc/mult_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - ECC mult version control register"]
     #[inline(always)]
diff --git a/esp32c2/src/ecc/mult_int_ena.rs b/esp32c2/src/ecc/mult_int_ena.rs
index 79989c989a..69d3e2f134 100644
--- a/esp32c2/src/ecc/mult_int_ena.rs
+++ b/esp32c2/src/ecc/mult_int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_INT_ENA")
-            .field("calc_done", &format_args!("{}", self.calc_done().bit()))
+            .field("calc_done", &self.calc_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"]
     #[inline(always)]
diff --git a/esp32c2/src/ecc/mult_int_raw.rs b/esp32c2/src/ecc/mult_int_raw.rs
index 4ae7197d07..c812773019 100644
--- a/esp32c2/src/ecc/mult_int_raw.rs
+++ b/esp32c2/src/ecc/mult_int_raw.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_INT_RAW")
-            .field("calc_done", &format_args!("{}", self.calc_done().bit()))
+            .field("calc_done", &self.calc_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MULT_INT_RAW_SPEC;
 impl crate::RegisterSpec for MULT_INT_RAW_SPEC {
diff --git a/esp32c2/src/ecc/mult_int_st.rs b/esp32c2/src/ecc/mult_int_st.rs
index 2034bfc27a..925a1eb350 100644
--- a/esp32c2/src/ecc/mult_int_st.rs
+++ b/esp32c2/src/ecc/mult_int_st.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_INT_ST")
-            .field("calc_done", &format_args!("{}", self.calc_done().bit()))
+            .field("calc_done", &self.calc_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MULT_INT_ST_SPEC;
 impl crate::RegisterSpec for MULT_INT_ST_SPEC {
diff --git a/esp32c2/src/ecc/px_mem.rs b/esp32c2/src/ecc/px_mem.rs
index 3a8e843f61..3a24d84d16 100644
--- a/esp32c2/src/ecc/px_mem.rs
+++ b/esp32c2/src/ecc/px_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PX_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores Px.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`px_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`px_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PX_MEM_SPEC;
diff --git a/esp32c2/src/ecc/py_mem.rs b/esp32c2/src/ecc/py_mem.rs
index 8129141315..e5d383ac34 100644
--- a/esp32c2/src/ecc/py_mem.rs
+++ b/esp32c2/src/ecc/py_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PY_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores Py.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`py_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`py_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PY_MEM_SPEC;
diff --git a/esp32c2/src/efuse/clk.rs b/esp32c2/src/efuse/clk.rs
index 9d7225a659..e2bcfaffbf 100644
--- a/esp32c2/src/efuse/clk.rs
+++ b/esp32c2/src/efuse/clk.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK")
-            .field(
-                "efuse_mem_force_pd",
-                &format_args!("{}", self.efuse_mem_force_pd().bit()),
-            )
-            .field(
-                "mem_clk_force_on",
-                &format_args!("{}", self.mem_clk_force_on().bit()),
-            )
-            .field(
-                "efuse_mem_force_pu",
-                &format_args!("{}", self.efuse_mem_force_pu().bit()),
-            )
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("efuse_mem_force_pd", &self.efuse_mem_force_pd())
+            .field("mem_clk_force_on", &self.mem_clk_force_on())
+            .field("efuse_mem_force_pu", &self.efuse_mem_force_pu())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to force eFuse SRAM into power-saving mode."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/cmd.rs b/esp32c2/src/efuse/cmd.rs
index 385957663f..5f03730bd0 100644
--- a/esp32c2/src/efuse/cmd.rs
+++ b/esp32c2/src/efuse/cmd.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("read_cmd", &format_args!("{}", self.read_cmd().bit()))
-            .field("pgm_cmd", &format_args!("{}", self.pgm_cmd().bit()))
-            .field("blk_num", &format_args!("{}", self.blk_num().bits()))
+            .field("read_cmd", &self.read_cmd())
+            .field("pgm_cmd", &self.pgm_cmd())
+            .field("blk_num", &self.blk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to send read command."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/conf.rs b/esp32c2/src/efuse/conf.rs
index 0aebe5f24c..3f9d5c90f6 100644
--- a/esp32c2/src/efuse/conf.rs
+++ b/esp32c2/src/efuse/conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("op_code", &format_args!("{}", self.op_code().bits()))
+            .field("op_code", &self.op_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - 0x5A5A: Operate programming command 0x5AA5: Operate read command."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/dac_conf.rs b/esp32c2/src/efuse/dac_conf.rs
index 46081e022e..e9db91d486 100644
--- a/esp32c2/src/efuse/dac_conf.rs
+++ b/esp32c2/src/efuse/dac_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DAC_CONF")
-            .field(
-                "dac_clk_div",
-                &format_args!("{}", self.dac_clk_div().bits()),
-            )
-            .field(
-                "dac_clk_pad_sel",
-                &format_args!("{}", self.dac_clk_pad_sel().bit()),
-            )
-            .field("dac_num", &format_args!("{}", self.dac_num().bits()))
-            .field("oe_clr", &format_args!("{}", self.oe_clr().bit()))
+            .field("dac_clk_div", &self.dac_clk_div())
+            .field("dac_clk_pad_sel", &self.dac_clk_pad_sel())
+            .field("dac_num", &self.dac_num())
+            .field("oe_clr", &self.oe_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DAC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Controls the division factor of the rising clock of the programming voltage."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/date.rs b/esp32c2/src/efuse/date.rs
index 098faa6dfc..f107a30d1f 100644
--- a/esp32c2/src/efuse/date.rs
+++ b/esp32c2/src/efuse/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/efuse/int_ena.rs b/esp32c2/src/efuse/int_ena.rs
index 6386df2821..0020c7e668 100644
--- a/esp32c2/src/efuse/int_ena.rs
+++ b/esp32c2/src/efuse/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable signal for read_done interrupt."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/int_raw.rs b/esp32c2/src/efuse/int_raw.rs
index 914c4f8c84..3d99203c2c 100644
--- a/esp32c2/src/efuse/int_raw.rs
+++ b/esp32c2/src/efuse/int_raw.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw bit signal for read_done interrupt."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/int_st.rs b/esp32c2/src/efuse/int_st.rs
index 898ceb8e8b..efba508ff2 100644
--- a/esp32c2/src/efuse/int_st.rs
+++ b/esp32c2/src/efuse/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c2/src/efuse/pgm_check_value0.rs b/esp32c2/src/efuse/pgm_check_value0.rs
index c116858f94..a6d3c26060 100644
--- a/esp32c2/src/efuse/pgm_check_value0.rs
+++ b/esp32c2/src/efuse/pgm_check_value0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE0")
-            .field(
-                "pgm_rs_data_0",
-                &format_args!("{}", self.pgm_rs_data_0().bits()),
-            )
+            .field("pgm_rs_data_0", &self.pgm_rs_data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 0th 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/pgm_check_value1.rs b/esp32c2/src/efuse/pgm_check_value1.rs
index 331e741927..875b090b36 100644
--- a/esp32c2/src/efuse/pgm_check_value1.rs
+++ b/esp32c2/src/efuse/pgm_check_value1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE1")
-            .field(
-                "pgm_rs_data_1",
-                &format_args!("{}", self.pgm_rs_data_1().bits()),
-            )
+            .field("pgm_rs_data_1", &self.pgm_rs_data_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 1st 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/pgm_check_value2.rs b/esp32c2/src/efuse/pgm_check_value2.rs
index 57aaf58855..571fe98175 100644
--- a/esp32c2/src/efuse/pgm_check_value2.rs
+++ b/esp32c2/src/efuse/pgm_check_value2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE2")
-            .field(
-                "pgm_rs_data_2",
-                &format_args!("{}", self.pgm_rs_data_2().bits()),
-            )
+            .field("pgm_rs_data_2", &self.pgm_rs_data_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 2nd 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/pgm_data0.rs b/esp32c2/src/efuse/pgm_data0.rs
index 3cc5ffca3b..b04bf3a372 100644
--- a/esp32c2/src/efuse/pgm_data0.rs
+++ b/esp32c2/src/efuse/pgm_data0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA0")
-            .field("pgm_data_0", &format_args!("{}", self.pgm_data_0().bits()))
+            .field("pgm_data_0", &self.pgm_data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 0th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/pgm_data1.rs b/esp32c2/src/efuse/pgm_data1.rs
index e01b369302..4d0e9f9794 100644
--- a/esp32c2/src/efuse/pgm_data1.rs
+++ b/esp32c2/src/efuse/pgm_data1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA1")
-            .field("pgm_data_1", &format_args!("{}", self.pgm_data_1().bits()))
+            .field("pgm_data_1", &self.pgm_data_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 1st 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/pgm_data2.rs b/esp32c2/src/efuse/pgm_data2.rs
index bb62a4d24f..f04c46cc20 100644
--- a/esp32c2/src/efuse/pgm_data2.rs
+++ b/esp32c2/src/efuse/pgm_data2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA2")
-            .field("pgm_data_2", &format_args!("{}", self.pgm_data_2().bits()))
+            .field("pgm_data_2", &self.pgm_data_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 2nd 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/pgm_data3.rs b/esp32c2/src/efuse/pgm_data3.rs
index 835e17347f..50d284df5b 100644
--- a/esp32c2/src/efuse/pgm_data3.rs
+++ b/esp32c2/src/efuse/pgm_data3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA3")
-            .field("pgm_data_3", &format_args!("{}", self.pgm_data_3().bits()))
+            .field("pgm_data_3", &self.pgm_data_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 3rd 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/pgm_data4.rs b/esp32c2/src/efuse/pgm_data4.rs
index 6806135803..0de88ae64c 100644
--- a/esp32c2/src/efuse/pgm_data4.rs
+++ b/esp32c2/src/efuse/pgm_data4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA4")
-            .field("pgm_data_4", &format_args!("{}", self.pgm_data_4().bits()))
+            .field("pgm_data_4", &self.pgm_data_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 4th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/pgm_data5.rs b/esp32c2/src/efuse/pgm_data5.rs
index e76d9ed490..839f0680b0 100644
--- a/esp32c2/src/efuse/pgm_data5.rs
+++ b/esp32c2/src/efuse/pgm_data5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA5")
-            .field("pgm_data_5", &format_args!("{}", self.pgm_data_5().bits()))
+            .field("pgm_data_5", &self.pgm_data_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 5th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/pgm_data6.rs b/esp32c2/src/efuse/pgm_data6.rs
index e50d19c967..f66b3f5d01 100644
--- a/esp32c2/src/efuse/pgm_data6.rs
+++ b/esp32c2/src/efuse/pgm_data6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA6")
-            .field("pgm_data_6", &format_args!("{}", self.pgm_data_6().bits()))
+            .field("pgm_data_6", &self.pgm_data_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 6th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/pgm_data7.rs b/esp32c2/src/efuse/pgm_data7.rs
index 886fcdcb3c..f8a8d36257 100644
--- a/esp32c2/src/efuse/pgm_data7.rs
+++ b/esp32c2/src/efuse/pgm_data7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA7")
-            .field("pgm_data_7", &format_args!("{}", self.pgm_data_7().bits()))
+            .field("pgm_data_7", &self.pgm_data_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 7th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/rd_blk1_data0.rs b/esp32c2/src/efuse/rd_blk1_data0.rs
index 3303d8ee27..2e96c84755 100644
--- a/esp32c2/src/efuse/rd_blk1_data0.rs
+++ b/esp32c2/src/efuse/rd_blk1_data0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK1_DATA0")
-            .field(
-                "system_data0",
-                &format_args!("{}", self.system_data0().bits()),
-            )
+            .field("system_data0", &self.system_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK1_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk1_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK1_DATA0_SPEC;
 impl crate::RegisterSpec for RD_BLK1_DATA0_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk1_data1.rs b/esp32c2/src/efuse/rd_blk1_data1.rs
index 93af0ca5b5..9b764a696d 100644
--- a/esp32c2/src/efuse/rd_blk1_data1.rs
+++ b/esp32c2/src/efuse/rd_blk1_data1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK1_DATA1")
-            .field(
-                "system_data1",
-                &format_args!("{}", self.system_data1().bits()),
-            )
+            .field("system_data1", &self.system_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK1_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk1_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK1_DATA1_SPEC;
 impl crate::RegisterSpec for RD_BLK1_DATA1_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk1_data2.rs b/esp32c2/src/efuse/rd_blk1_data2.rs
index 2fc1ec2560..a51d4d635e 100644
--- a/esp32c2/src/efuse/rd_blk1_data2.rs
+++ b/esp32c2/src/efuse/rd_blk1_data2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK1_DATA2")
-            .field(
-                "system_data2",
-                &format_args!("{}", self.system_data2().bits()),
-            )
+            .field("system_data2", &self.system_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK1_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk1_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK1_DATA2_SPEC;
 impl crate::RegisterSpec for RD_BLK1_DATA2_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk2_data0.rs b/esp32c2/src/efuse/rd_blk2_data0.rs
index 21663938b0..10cc64ace3 100644
--- a/esp32c2/src/efuse/rd_blk2_data0.rs
+++ b/esp32c2/src/efuse/rd_blk2_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK2_DATA0")
-            .field("blk2_data0", &format_args!("{}", self.blk2_data0().bits()))
+            .field("blk2_data0", &self.blk2_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK2_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk2_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK2_DATA0_SPEC;
 impl crate::RegisterSpec for RD_BLK2_DATA0_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk2_data1.rs b/esp32c2/src/efuse/rd_blk2_data1.rs
index d7461ac4fb..34b51aadcf 100644
--- a/esp32c2/src/efuse/rd_blk2_data1.rs
+++ b/esp32c2/src/efuse/rd_blk2_data1.rs
@@ -48,39 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK2_DATA1")
-            .field(
-                "mac_id_high",
-                &format_args!("{}", self.mac_id_high().bits()),
-            )
-            .field(
-                "wafer_version",
-                &format_args!("{}", self.wafer_version().bits()),
-            )
-            .field(
-                "pkg_version",
-                &format_args!("{}", self.pkg_version().bits()),
-            )
-            .field(
-                "blk2_efuse_version",
-                &format_args!("{}", self.blk2_efuse_version().bits()),
-            )
-            .field(
-                "rf_ref_i_bias_config",
-                &format_args!("{}", self.rf_ref_i_bias_config().bits()),
-            )
-            .field(
-                "ldo_vol_bias_config_low",
-                &format_args!("{}", self.ldo_vol_bias_config_low().bits()),
-            )
+            .field("mac_id_high", &self.mac_id_high())
+            .field("wafer_version", &self.wafer_version())
+            .field("pkg_version", &self.pkg_version())
+            .field("blk2_efuse_version", &self.blk2_efuse_version())
+            .field("rf_ref_i_bias_config", &self.rf_ref_i_bias_config())
+            .field("ldo_vol_bias_config_low", &self.ldo_vol_bias_config_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK2_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk2_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK2_DATA1_SPEC;
 impl crate::RegisterSpec for RD_BLK2_DATA1_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk2_data2.rs b/esp32c2/src/efuse/rd_blk2_data2.rs
index d23336cb41..d38efc5988 100644
--- a/esp32c2/src/efuse/rd_blk2_data2.rs
+++ b/esp32c2/src/efuse/rd_blk2_data2.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK2_DATA2")
-            .field(
-                "ldo_vol_bias_config_high",
-                &format_args!("{}", self.ldo_vol_bias_config_high().bits()),
-            )
-            .field("pvt_low", &format_args!("{}", self.pvt_low().bits()))
+            .field("ldo_vol_bias_config_high", &self.ldo_vol_bias_config_high())
+            .field("pvt_low", &self.pvt_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK2_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk2_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK2_DATA2_SPEC;
 impl crate::RegisterSpec for RD_BLK2_DATA2_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk2_data3.rs b/esp32c2/src/efuse/rd_blk2_data3.rs
index 14ae5b3770..764805ebaa 100644
--- a/esp32c2/src/efuse/rd_blk2_data3.rs
+++ b/esp32c2/src/efuse/rd_blk2_data3.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK2_DATA3")
-            .field("pvt_high", &format_args!("{}", self.pvt_high().bits()))
-            .field(
-                "adc_calibration_0",
-                &format_args!("{}", self.adc_calibration_0().bits()),
-            )
+            .field("pvt_high", &self.pvt_high())
+            .field("adc_calibration_0", &self.adc_calibration_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK2_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk2_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK2_DATA3_SPEC;
 impl crate::RegisterSpec for RD_BLK2_DATA3_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk2_data4.rs b/esp32c2/src/efuse/rd_blk2_data4.rs
index fd3fdac02d..5011f2908c 100644
--- a/esp32c2/src/efuse/rd_blk2_data4.rs
+++ b/esp32c2/src/efuse/rd_blk2_data4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK2_DATA4")
-            .field(
-                "adc_calibration_1",
-                &format_args!("{}", self.adc_calibration_1().bits()),
-            )
+            .field("adc_calibration_1", &self.adc_calibration_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK2_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk2_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK2_DATA4_SPEC;
 impl crate::RegisterSpec for RD_BLK2_DATA4_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk2_data5.rs b/esp32c2/src/efuse/rd_blk2_data5.rs
index ce732e25d9..251d9d02af 100644
--- a/esp32c2/src/efuse/rd_blk2_data5.rs
+++ b/esp32c2/src/efuse/rd_blk2_data5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK2_DATA5")
-            .field(
-                "adc_calibration_2",
-                &format_args!("{}", self.adc_calibration_2().bits()),
-            )
+            .field("adc_calibration_2", &self.adc_calibration_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK2_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk2_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK2_DATA5_SPEC;
 impl crate::RegisterSpec for RD_BLK2_DATA5_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk2_data6.rs b/esp32c2/src/efuse/rd_blk2_data6.rs
index 6c6d07e220..abc05fc62b 100644
--- a/esp32c2/src/efuse/rd_blk2_data6.rs
+++ b/esp32c2/src/efuse/rd_blk2_data6.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK2_DATA6")
-            .field(
-                "adc_calibration_3",
-                &format_args!("{}", self.adc_calibration_3().bits()),
-            )
-            .field(
-                "blk2_reserved_data_0",
-                &format_args!("{}", self.blk2_reserved_data_0().bits()),
-            )
+            .field("adc_calibration_3", &self.adc_calibration_3())
+            .field("blk2_reserved_data_0", &self.blk2_reserved_data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK2_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk2_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK2_DATA6_SPEC;
 impl crate::RegisterSpec for RD_BLK2_DATA6_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk2_data7.rs b/esp32c2/src/efuse/rd_blk2_data7.rs
index 0d4ba0795a..4f64ba03d5 100644
--- a/esp32c2/src/efuse/rd_blk2_data7.rs
+++ b/esp32c2/src/efuse/rd_blk2_data7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK2_DATA7")
-            .field(
-                "blk2_reserved_data_1",
-                &format_args!("{}", self.blk2_reserved_data_1().bits()),
-            )
+            .field("blk2_reserved_data_1", &self.blk2_reserved_data_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK2_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk2_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK2_DATA7_SPEC;
 impl crate::RegisterSpec for RD_BLK2_DATA7_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk3_data0.rs b/esp32c2/src/efuse/rd_blk3_data0.rs
index 530a4d5d43..2af5e4d75c 100644
--- a/esp32c2/src/efuse/rd_blk3_data0.rs
+++ b/esp32c2/src/efuse/rd_blk3_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK3_DATA0")
-            .field("blk3_data0", &format_args!("{}", self.blk3_data0().bits()))
+            .field("blk3_data0", &self.blk3_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK3_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk3_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK3_DATA0_SPEC;
 impl crate::RegisterSpec for RD_BLK3_DATA0_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk3_data1.rs b/esp32c2/src/efuse/rd_blk3_data1.rs
index 4f0726cbe4..cca8c2f550 100644
--- a/esp32c2/src/efuse/rd_blk3_data1.rs
+++ b/esp32c2/src/efuse/rd_blk3_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK3_DATA1")
-            .field("blk3_data1", &format_args!("{}", self.blk3_data1().bits()))
+            .field("blk3_data1", &self.blk3_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK3_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk3_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK3_DATA1_SPEC;
 impl crate::RegisterSpec for RD_BLK3_DATA1_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk3_data2.rs b/esp32c2/src/efuse/rd_blk3_data2.rs
index 9767746ec4..4faf1d48fa 100644
--- a/esp32c2/src/efuse/rd_blk3_data2.rs
+++ b/esp32c2/src/efuse/rd_blk3_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK3_DATA2")
-            .field("blk3_data2", &format_args!("{}", self.blk3_data2().bits()))
+            .field("blk3_data2", &self.blk3_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK3_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk3_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK3_DATA2_SPEC;
 impl crate::RegisterSpec for RD_BLK3_DATA2_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk3_data3.rs b/esp32c2/src/efuse/rd_blk3_data3.rs
index 843ff837fa..fbc03750f5 100644
--- a/esp32c2/src/efuse/rd_blk3_data3.rs
+++ b/esp32c2/src/efuse/rd_blk3_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK3_DATA3")
-            .field("blk3_data3", &format_args!("{}", self.blk3_data3().bits()))
+            .field("blk3_data3", &self.blk3_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK3_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk3_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK3_DATA3_SPEC;
 impl crate::RegisterSpec for RD_BLK3_DATA3_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk3_data4.rs b/esp32c2/src/efuse/rd_blk3_data4.rs
index 9d3827ad55..f00604661e 100644
--- a/esp32c2/src/efuse/rd_blk3_data4.rs
+++ b/esp32c2/src/efuse/rd_blk3_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK3_DATA4")
-            .field("blk3_data4", &format_args!("{}", self.blk3_data4().bits()))
+            .field("blk3_data4", &self.blk3_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK3_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk3_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK3_DATA4_SPEC;
 impl crate::RegisterSpec for RD_BLK3_DATA4_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk3_data5.rs b/esp32c2/src/efuse/rd_blk3_data5.rs
index 9c72dac22e..043a3db546 100644
--- a/esp32c2/src/efuse/rd_blk3_data5.rs
+++ b/esp32c2/src/efuse/rd_blk3_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK3_DATA5")
-            .field("blk3_data5", &format_args!("{}", self.blk3_data5().bits()))
+            .field("blk3_data5", &self.blk3_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK3_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk3_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK3_DATA5_SPEC;
 impl crate::RegisterSpec for RD_BLK3_DATA5_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk3_data6.rs b/esp32c2/src/efuse/rd_blk3_data6.rs
index 97154a50a4..17622d2970 100644
--- a/esp32c2/src/efuse/rd_blk3_data6.rs
+++ b/esp32c2/src/efuse/rd_blk3_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK3_DATA6")
-            .field("blk3_data6", &format_args!("{}", self.blk3_data6().bits()))
+            .field("blk3_data6", &self.blk3_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK3_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk3_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK3_DATA6_SPEC;
 impl crate::RegisterSpec for RD_BLK3_DATA6_SPEC {
diff --git a/esp32c2/src/efuse/rd_blk3_data7.rs b/esp32c2/src/efuse/rd_blk3_data7.rs
index 6e7ef49e7e..129e33eedb 100644
--- a/esp32c2/src/efuse/rd_blk3_data7.rs
+++ b/esp32c2/src/efuse/rd_blk3_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_BLK3_DATA7")
-            .field("blk3_data7", &format_args!("{}", self.blk3_data7().bits()))
+            .field("blk3_data7", &self.blk3_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_BLK3_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_blk3_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_BLK3_DATA7_SPEC;
 impl crate::RegisterSpec for RD_BLK3_DATA7_SPEC {
diff --git a/esp32c2/src/efuse/rd_repeat_data0.rs b/esp32c2/src/efuse/rd_repeat_data0.rs
index 86a6b1973c..0b9f6162e8 100644
--- a/esp32c2/src/efuse/rd_repeat_data0.rs
+++ b/esp32c2/src/efuse/rd_repeat_data0.rs
@@ -111,69 +111,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA0")
-            .field("rd_dis", &format_args!("{}", self.rd_dis().bits()))
-            .field(
-                "wdt_delay_sel",
-                &format_args!("{}", self.wdt_delay_sel().bits()),
-            )
-            .field(
-                "dis_pad_jtag",
-                &format_args!("{}", self.dis_pad_jtag().bit()),
-            )
-            .field(
-                "dis_download_icache",
-                &format_args!("{}", self.dis_download_icache().bit()),
-            )
+            .field("rd_dis", &self.rd_dis())
+            .field("wdt_delay_sel", &self.wdt_delay_sel())
+            .field("dis_pad_jtag", &self.dis_pad_jtag())
+            .field("dis_download_icache", &self.dis_download_icache())
             .field(
                 "dis_download_manual_encrypt",
-                &format_args!("{}", self.dis_download_manual_encrypt().bit()),
+                &self.dis_download_manual_encrypt(),
             )
             .field(
                 "spi_boot_encrypt_decrypt_cnt",
-                &format_args!("{}", self.spi_boot_encrypt_decrypt_cnt().bits()),
-            )
-            .field(
-                "xts_key_length_256",
-                &format_args!("{}", self.xts_key_length_256().bit()),
-            )
-            .field(
-                "uart_print_control",
-                &format_args!("{}", self.uart_print_control().bits()),
-            )
-            .field(
-                "force_send_resume",
-                &format_args!("{}", self.force_send_resume().bit()),
-            )
-            .field(
-                "dis_download_mode",
-                &format_args!("{}", self.dis_download_mode().bit()),
-            )
-            .field(
-                "dis_direct_boot",
-                &format_args!("{}", self.dis_direct_boot().bit()),
-            )
-            .field(
-                "enable_security_download",
-                &format_args!("{}", self.enable_security_download().bit()),
-            )
-            .field("flash_tpuw", &format_args!("{}", self.flash_tpuw().bits()))
-            .field(
-                "secure_boot_en",
-                &format_args!("{}", self.secure_boot_en().bit()),
-            )
-            .field(
-                "rpt4_reserved",
-                &format_args!("{}", self.rpt4_reserved().bits()),
+                &self.spi_boot_encrypt_decrypt_cnt(),
             )
+            .field("xts_key_length_256", &self.xts_key_length_256())
+            .field("uart_print_control", &self.uart_print_control())
+            .field("force_send_resume", &self.force_send_resume())
+            .field("dis_download_mode", &self.dis_download_mode())
+            .field("dis_direct_boot", &self.dis_direct_boot())
+            .field("enable_security_download", &self.enable_security_download())
+            .field("flash_tpuw", &self.flash_tpuw())
+            .field("secure_boot_en", &self.secure_boot_en())
+            .field("rpt4_reserved", &self.rpt4_reserved())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA0_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA0_SPEC {
diff --git a/esp32c2/src/efuse/rd_repeat_err.rs b/esp32c2/src/efuse/rd_repeat_err.rs
index 2c18ed7d25..2f454e1753 100644
--- a/esp32c2/src/efuse/rd_repeat_err.rs
+++ b/esp32c2/src/efuse/rd_repeat_err.rs
@@ -111,72 +111,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR")
-            .field("rd_dis_err", &format_args!("{}", self.rd_dis_err().bits()))
-            .field(
-                "wdt_delay_sel_err",
-                &format_args!("{}", self.wdt_delay_sel_err().bits()),
-            )
-            .field(
-                "dis_pad_jtag_err",
-                &format_args!("{}", self.dis_pad_jtag_err().bit()),
-            )
-            .field(
-                "dis_download_icache_err",
-                &format_args!("{}", self.dis_download_icache_err().bit()),
-            )
+            .field("rd_dis_err", &self.rd_dis_err())
+            .field("wdt_delay_sel_err", &self.wdt_delay_sel_err())
+            .field("dis_pad_jtag_err", &self.dis_pad_jtag_err())
+            .field("dis_download_icache_err", &self.dis_download_icache_err())
             .field(
                 "dis_download_manual_encrypt_err",
-                &format_args!("{}", self.dis_download_manual_encrypt_err().bit()),
+                &self.dis_download_manual_encrypt_err(),
             )
             .field(
                 "spi_boot_encrypt_decrypt_cnt_err",
-                &format_args!("{}", self.spi_boot_encrypt_decrypt_cnt_err().bits()),
-            )
-            .field(
-                "xts_key_length_256_err",
-                &format_args!("{}", self.xts_key_length_256_err().bit()),
-            )
-            .field(
-                "uart_print_control_err",
-                &format_args!("{}", self.uart_print_control_err().bits()),
-            )
-            .field(
-                "force_send_resume_err",
-                &format_args!("{}", self.force_send_resume_err().bit()),
-            )
-            .field(
-                "dis_download_mode_err",
-                &format_args!("{}", self.dis_download_mode_err().bit()),
-            )
-            .field(
-                "dis_direct_boot_err",
-                &format_args!("{}", self.dis_direct_boot_err().bit()),
+                &self.spi_boot_encrypt_decrypt_cnt_err(),
             )
+            .field("xts_key_length_256_err", &self.xts_key_length_256_err())
+            .field("uart_print_control_err", &self.uart_print_control_err())
+            .field("force_send_resume_err", &self.force_send_resume_err())
+            .field("dis_download_mode_err", &self.dis_download_mode_err())
+            .field("dis_direct_boot_err", &self.dis_direct_boot_err())
             .field(
                 "enable_security_download_err",
-                &format_args!("{}", self.enable_security_download_err().bit()),
-            )
-            .field(
-                "flash_tpuw_err",
-                &format_args!("{}", self.flash_tpuw_err().bits()),
-            )
-            .field(
-                "secure_boot_en_err",
-                &format_args!("{}", self.secure_boot_en_err().bit()),
-            )
-            .field(
-                "rpt4_reserved_err",
-                &format_args!("{}", self.rpt4_reserved_err().bits()),
+                &self.enable_security_download_err(),
             )
+            .field("flash_tpuw_err", &self.flash_tpuw_err())
+            .field("secure_boot_en_err", &self.secure_boot_en_err())
+            .field("rpt4_reserved_err", &self.rpt4_reserved_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 0 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR_SPEC {
diff --git a/esp32c2/src/efuse/rd_rs_err.rs b/esp32c2/src/efuse/rd_rs_err.rs
index 29c42c2f1e..82722b1a23 100644
--- a/esp32c2/src/efuse/rd_rs_err.rs
+++ b/esp32c2/src/efuse/rd_rs_err.rs
@@ -48,30 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_RS_ERR")
-            .field(
-                "blk1_err_num",
-                &format_args!("{}", self.blk1_err_num().bits()),
-            )
-            .field("blk1_fail", &format_args!("{}", self.blk1_fail().bit()))
-            .field(
-                "blk2_err_num",
-                &format_args!("{}", self.blk2_err_num().bits()),
-            )
-            .field("blk2_fail", &format_args!("{}", self.blk2_fail().bit()))
-            .field(
-                "blk3_err_num",
-                &format_args!("{}", self.blk3_err_num().bits()),
-            )
-            .field("blk3_fail", &format_args!("{}", self.blk3_fail().bit()))
+            .field("blk1_err_num", &self.blk1_err_num())
+            .field("blk1_fail", &self.blk1_fail())
+            .field("blk2_err_num", &self.blk2_err_num())
+            .field("blk2_fail", &self.blk2_fail())
+            .field("blk3_err_num", &self.blk3_err_num())
+            .field("blk3_fail", &self.blk3_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RS_ERR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 0 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RS_ERR_SPEC;
 impl crate::RegisterSpec for RD_RS_ERR_SPEC {
diff --git a/esp32c2/src/efuse/rd_tim_conf.rs b/esp32c2/src/efuse/rd_tim_conf.rs
index 572c00025e..64dc01a10b 100644
--- a/esp32c2/src/efuse/rd_tim_conf.rs
+++ b/esp32c2/src/efuse/rd_tim_conf.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_TIM_CONF")
-            .field("thr_a", &format_args!("{}", self.thr_a().bits()))
-            .field("trd", &format_args!("{}", self.trd().bits()))
-            .field("tsur_a", &format_args!("{}", self.tsur_a().bits()))
-            .field(
-                "read_init_num",
-                &format_args!("{}", self.read_init_num().bits()),
-            )
+            .field("thr_a", &self.thr_a())
+            .field("trd", &self.trd())
+            .field("tsur_a", &self.tsur_a())
+            .field("read_init_num", &self.read_init_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_TIM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures hold time for efuse read."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/rd_wr_dis.rs b/esp32c2/src/efuse/rd_wr_dis.rs
index db64b0dae1..be27bd3208 100644
--- a/esp32c2/src/efuse/rd_wr_dis.rs
+++ b/esp32c2/src/efuse/rd_wr_dis.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_WR_DIS")
-            .field("wr_dis", &format_args!("{}", self.wr_dis().bits()))
+            .field("wr_dis", &self.wr_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_WR_DIS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_wr_dis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_WR_DIS_SPEC;
 impl crate::RegisterSpec for RD_WR_DIS_SPEC {
diff --git a/esp32c2/src/efuse/status.rs b/esp32c2/src/efuse/status.rs
index fd9919bb22..ec77dfcf99 100644
--- a/esp32c2/src/efuse/status.rs
+++ b/esp32c2/src/efuse/status.rs
@@ -62,38 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field("otp_load_sw", &format_args!("{}", self.otp_load_sw().bit()))
-            .field(
-                "otp_vddq_c_sync2",
-                &format_args!("{}", self.otp_vddq_c_sync2().bit()),
-            )
-            .field(
-                "otp_strobe_sw",
-                &format_args!("{}", self.otp_strobe_sw().bit()),
-            )
-            .field("otp_csb_sw", &format_args!("{}", self.otp_csb_sw().bit()))
-            .field(
-                "otp_pgenb_sw",
-                &format_args!("{}", self.otp_pgenb_sw().bit()),
-            )
-            .field(
-                "otp_vddq_is_sw",
-                &format_args!("{}", self.otp_vddq_is_sw().bit()),
-            )
-            .field(
-                "blk0_valid_bit_cnt",
-                &format_args!("{}", self.blk0_valid_bit_cnt().bits()),
-            )
+            .field("state", &self.state())
+            .field("otp_load_sw", &self.otp_load_sw())
+            .field("otp_vddq_c_sync2", &self.otp_vddq_c_sync2())
+            .field("otp_strobe_sw", &self.otp_strobe_sw())
+            .field("otp_csb_sw", &self.otp_csb_sw())
+            .field("otp_pgenb_sw", &self.otp_pgenb_sw())
+            .field("otp_vddq_is_sw", &self.otp_vddq_is_sw())
+            .field("blk0_valid_bit_cnt", &self.blk0_valid_bit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32c2/src/efuse/wr_tim_conf0.rs b/esp32c2/src/efuse/wr_tim_conf0.rs
index a579e7a827..6e1bbb3cf3 100644
--- a/esp32c2/src/efuse/wr_tim_conf0.rs
+++ b/esp32c2/src/efuse/wr_tim_conf0.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF0")
-            .field("thp_a", &format_args!("{}", self.thp_a().bits()))
-            .field(
-                "tpgm_inactive",
-                &format_args!("{}", self.tpgm_inactive().bits()),
-            )
-            .field("tpgm", &format_args!("{}", self.tpgm().bits()))
+            .field("thp_a", &self.thp_a())
+            .field("tpgm_inactive", &self.tpgm_inactive())
+            .field("tpgm", &self.tpgm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures hold time for efuse program."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/wr_tim_conf1.rs b/esp32c2/src/efuse/wr_tim_conf1.rs
index 0282d268ca..31eebdbb29 100644
--- a/esp32c2/src/efuse/wr_tim_conf1.rs
+++ b/esp32c2/src/efuse/wr_tim_conf1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF1")
-            .field("tsup_a", &format_args!("{}", self.tsup_a().bits()))
-            .field("pwr_on_num", &format_args!("{}", self.pwr_on_num().bits()))
+            .field("tsup_a", &self.tsup_a())
+            .field("pwr_on_num", &self.pwr_on_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures setup time for efuse program."]
     #[inline(always)]
diff --git a/esp32c2/src/efuse/wr_tim_conf2.rs b/esp32c2/src/efuse/wr_tim_conf2.rs
index 8a270afb59..3318449f16 100644
--- a/esp32c2/src/efuse/wr_tim_conf2.rs
+++ b/esp32c2/src/efuse/wr_tim_conf2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF2")
-            .field(
-                "pwr_off_num",
-                &format_args!("{}", self.pwr_off_num().bits()),
-            )
+            .field("pwr_off_num", &self.pwr_off_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures the power outage time for VDDQ."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/cache_conf_misc.rs b/esp32c2/src/extmem/cache_conf_misc.rs
index d779e63718..21493ab37c 100644
--- a/esp32c2/src/extmem/cache_conf_misc.rs
+++ b/esp32c2/src/extmem/cache_conf_misc.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("CACHE_CONF_MISC")
             .field(
                 "cache_ignore_preload_mmu_entry_fault",
-                &format_args!("{}", self.cache_ignore_preload_mmu_entry_fault().bit()),
+                &self.cache_ignore_preload_mmu_entry_fault(),
             )
             .field(
                 "cache_ignore_sync_mmu_entry_fault",
-                &format_args!("{}", self.cache_ignore_sync_mmu_entry_fault().bit()),
-            )
-            .field(
-                "cache_trace_ena",
-                &format_args!("{}", self.cache_trace_ena().bit()),
-            )
-            .field(
-                "cache_mmu_page_size",
-                &format_args!("{}", self.cache_mmu_page_size().bits()),
+                &self.cache_ignore_sync_mmu_entry_fault(),
             )
+            .field("cache_trace_ena", &self.cache_trace_ena())
+            .field("cache_mmu_page_size", &self.cache_mmu_page_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CONF_MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable checking mmu entry fault by preload operation."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/cache_encrypt_decrypt_clk_force_on.rs b/esp32c2/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
index 3a05102710..923f8273e8 100644
--- a/esp32c2/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
+++ b/esp32c2/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON")
             .field(
                 "clk_force_on_manual_crypt",
-                &format_args!("{}", self.clk_force_on_manual_crypt().bit()),
-            )
-            .field(
-                "clk_force_on_auto_crypt",
-                &format_args!("{}", self.clk_force_on_auto_crypt().bit()),
-            )
-            .field(
-                "clk_force_on_crypt",
-                &format_args!("{}", self.clk_force_on_crypt().bit()),
+                &self.clk_force_on_manual_crypt(),
             )
+            .field("clk_force_on_auto_crypt", &self.clk_force_on_auto_crypt())
+            .field("clk_force_on_crypt", &self.clk_force_on_crypt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/cache_encrypt_decrypt_record_disable.rs b/esp32c2/src/extmem/cache_encrypt_decrypt_record_disable.rs
index 9c41127873..96c9078f3e 100644
--- a/esp32c2/src/extmem/cache_encrypt_decrypt_record_disable.rs
+++ b/esp32c2/src/extmem/cache_encrypt_decrypt_record_disable.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE")
             .field(
                 "record_disable_db_encrypt",
-                &format_args!("{}", self.record_disable_db_encrypt().bit()),
+                &self.record_disable_db_encrypt(),
             )
             .field(
                 "record_disable_g0cb_decrypt",
-                &format_args!("{}", self.record_disable_g0cb_decrypt().bit()),
+                &self.record_disable_g0cb_decrypt(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/cache_ilg_int_ena.rs b/esp32c2/src/extmem/cache_ilg_int_ena.rs
index 82ee5de7bb..c4df66c1db 100644
--- a/esp32c2/src/extmem/cache_ilg_int_ena.rs
+++ b/esp32c2/src/extmem/cache_ilg_int_ena.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_ILG_INT_ENA")
-            .field(
-                "icache_sync_op_fault",
-                &format_args!("{}", self.icache_sync_op_fault().bit()),
-            )
-            .field(
-                "icache_preload_op_fault",
-                &format_args!("{}", self.icache_preload_op_fault().bit()),
-            )
-            .field(
-                "mmu_entry_fault",
-                &format_args!("{}", self.mmu_entry_fault().bit()),
-            )
-            .field(
-                "ibus_cnt_ovf",
-                &format_args!("{}", self.ibus_cnt_ovf().bit()),
-            )
-            .field(
-                "dbus_cnt_ovf",
-                &format_args!("{}", self.dbus_cnt_ovf().bit()),
-            )
+            .field("icache_sync_op_fault", &self.icache_sync_op_fault())
+            .field("icache_preload_op_fault", &self.icache_preload_op_fault())
+            .field("mmu_entry_fault", &self.mmu_entry_fault())
+            .field("ibus_cnt_ovf", &self.ibus_cnt_ovf())
+            .field("dbus_cnt_ovf", &self.dbus_cnt_ovf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_ILG_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable interrupt by sync configurations fault."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/cache_ilg_int_st.rs b/esp32c2/src/extmem/cache_ilg_int_st.rs
index 0ea6947478..8795284dc0 100644
--- a/esp32c2/src/extmem/cache_ilg_int_st.rs
+++ b/esp32c2/src/extmem/cache_ilg_int_st.rs
@@ -55,43 +55,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_ILG_INT_ST")
-            .field(
-                "icache_sync_op_fault",
-                &format_args!("{}", self.icache_sync_op_fault().bit()),
-            )
-            .field(
-                "icache_preload_op_fault",
-                &format_args!("{}", self.icache_preload_op_fault().bit()),
-            )
-            .field(
-                "mmu_entry_fault",
-                &format_args!("{}", self.mmu_entry_fault().bit()),
-            )
-            .field(
-                "ibus_acs_cnt_ovf",
-                &format_args!("{}", self.ibus_acs_cnt_ovf().bit()),
-            )
-            .field(
-                "ibus_acs_miss_cnt_ovf",
-                &format_args!("{}", self.ibus_acs_miss_cnt_ovf().bit()),
-            )
-            .field(
-                "dbus_acs_cnt_ovf",
-                &format_args!("{}", self.dbus_acs_cnt_ovf().bit()),
-            )
+            .field("icache_sync_op_fault", &self.icache_sync_op_fault())
+            .field("icache_preload_op_fault", &self.icache_preload_op_fault())
+            .field("mmu_entry_fault", &self.mmu_entry_fault())
+            .field("ibus_acs_cnt_ovf", &self.ibus_acs_cnt_ovf())
+            .field("ibus_acs_miss_cnt_ovf", &self.ibus_acs_miss_cnt_ovf())
+            .field("dbus_acs_cnt_ovf", &self.dbus_acs_cnt_ovf())
             .field(
                 "dbus_acs_flash_miss_cnt_ovf",
-                &format_args!("{}", self.dbus_acs_flash_miss_cnt_ovf().bit()),
+                &self.dbus_acs_flash_miss_cnt_ovf(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_ILG_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_ilg_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_ILG_INT_ST_SPEC;
 impl crate::RegisterSpec for CACHE_ILG_INT_ST_SPEC {
diff --git a/esp32c2/src/extmem/cache_mmu_fault_content.rs b/esp32c2/src/extmem/cache_mmu_fault_content.rs
index 866b36f427..958b7e0d97 100644
--- a/esp32c2/src/extmem/cache_mmu_fault_content.rs
+++ b/esp32c2/src/extmem/cache_mmu_fault_content.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_FAULT_CONTENT")
-            .field(
-                "cache_mmu_fault_content",
-                &format_args!("{}", self.cache_mmu_fault_content().bits()),
-            )
-            .field(
-                "cache_mmu_fault_code",
-                &format_args!("{}", self.cache_mmu_fault_code().bits()),
-            )
+            .field("cache_mmu_fault_content", &self.cache_mmu_fault_content())
+            .field("cache_mmu_fault_code", &self.cache_mmu_fault_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_FAULT_CONTENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_mmu_fault_content::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_MMU_FAULT_CONTENT_SPEC;
 impl crate::RegisterSpec for CACHE_MMU_FAULT_CONTENT_SPEC {
diff --git a/esp32c2/src/extmem/cache_mmu_fault_vaddr.rs b/esp32c2/src/extmem/cache_mmu_fault_vaddr.rs
index 259c7a8f7a..d7426d0622 100644
--- a/esp32c2/src/extmem/cache_mmu_fault_vaddr.rs
+++ b/esp32c2/src/extmem/cache_mmu_fault_vaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_FAULT_VADDR")
-            .field(
-                "cache_mmu_fault_vaddr",
-                &format_args!("{}", self.cache_mmu_fault_vaddr().bits()),
-            )
+            .field("cache_mmu_fault_vaddr", &self.cache_mmu_fault_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_FAULT_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_mmu_fault_vaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_MMU_FAULT_VADDR_SPEC;
 impl crate::RegisterSpec for CACHE_MMU_FAULT_VADDR_SPEC {
diff --git a/esp32c2/src/extmem/cache_mmu_owner.rs b/esp32c2/src/extmem/cache_mmu_owner.rs
index a3d072da00..0e51e3b984 100644
--- a/esp32c2/src/extmem/cache_mmu_owner.rs
+++ b/esp32c2/src/extmem/cache_mmu_owner.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_OWNER")
-            .field(
-                "cache_mmu_owner",
-                &format_args!("{}", self.cache_mmu_owner().bits()),
-            )
+            .field("cache_mmu_owner", &self.cache_mmu_owner())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_OWNER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus"]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/cache_mmu_power_ctrl.rs b/esp32c2/src/extmem/cache_mmu_power_ctrl.rs
index 78764d6540..fea61d4975 100644
--- a/esp32c2/src/extmem/cache_mmu_power_ctrl.rs
+++ b/esp32c2/src/extmem/cache_mmu_power_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_POWER_CTRL")
-            .field(
-                "cache_mmu_mem_force_on",
-                &format_args!("{}", self.cache_mmu_mem_force_on().bit()),
-            )
-            .field(
-                "cache_mmu_mem_force_pd",
-                &format_args!("{}", self.cache_mmu_mem_force_pd().bit()),
-            )
-            .field(
-                "cache_mmu_mem_force_pu",
-                &format_args!("{}", self.cache_mmu_mem_force_pu().bit()),
-            )
+            .field("cache_mmu_mem_force_on", &self.cache_mmu_mem_force_on())
+            .field("cache_mmu_mem_force_pd", &self.cache_mmu_mem_force_pd())
+            .field("cache_mmu_mem_force_pu", &self.cache_mmu_mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable"]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/cache_preload_int_ctrl.rs b/esp32c2/src/extmem/cache_preload_int_ctrl.rs
index 722c0de8ae..9e7cb958f8 100644
--- a/esp32c2/src/extmem/cache_preload_int_ctrl.rs
+++ b/esp32c2/src/extmem/cache_preload_int_ctrl.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_PRELOAD_INT_CTRL")
-            .field("st", &format_args!("{}", self.st().bit()))
-            .field("ena", &format_args!("{}", self.ena().bit()))
+            .field("st", &self.st())
+            .field("ena", &self.ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_PRELOAD_INT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - The bit is used to enable the interrupt by icache pre-load done."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/cache_request.rs b/esp32c2/src/extmem/cache_request.rs
index 8ff3734f13..7717cb7164 100644
--- a/esp32c2/src/extmem/cache_request.rs
+++ b/esp32c2/src/extmem/cache_request.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_REQUEST")
-            .field("bypass", &format_args!("{}", self.bypass().bit()))
+            .field("bypass", &self.bypass())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_REQUEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable request recording which could cause performance issue"]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/cache_state.rs b/esp32c2/src/extmem/cache_state.rs
index 57c172ae51..897f15abc7 100644
--- a/esp32c2/src/extmem/cache_state.rs
+++ b/esp32c2/src/extmem/cache_state.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_STATE")
-            .field(
-                "icache_state",
-                &format_args!("{}", self.icache_state().bits()),
-            )
+            .field("icache_state", &self.icache_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_STATE_SPEC;
 impl crate::RegisterSpec for CACHE_STATE_SPEC {
diff --git a/esp32c2/src/extmem/cache_sync_int_ctrl.rs b/esp32c2/src/extmem/cache_sync_int_ctrl.rs
index bd3dab87e5..ff6cccfc1d 100644
--- a/esp32c2/src/extmem/cache_sync_int_ctrl.rs
+++ b/esp32c2/src/extmem/cache_sync_int_ctrl.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_SYNC_INT_CTRL")
-            .field("st", &format_args!("{}", self.st().bit()))
-            .field("ena", &format_args!("{}", self.ena().bit()))
+            .field("st", &self.st())
+            .field("ena", &self.ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_SYNC_INT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - The bit is used to enable the interrupt by icache sync done."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/cache_wrap_around_ctrl.rs b/esp32c2/src/extmem/cache_wrap_around_ctrl.rs
index df47c13944..8c8e5fe6fb 100644
--- a/esp32c2/src/extmem/cache_wrap_around_ctrl.rs
+++ b/esp32c2/src/extmem/cache_wrap_around_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_WRAP_AROUND_CTRL")
-            .field(
-                "cache_flash_wrap_around",
-                &format_args!("{}", self.cache_flash_wrap_around().bit()),
-            )
+            .field("cache_flash_wrap_around", &self.cache_flash_wrap_around())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_WRAP_AROUND_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable wrap around mode when read data from flash."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/clock_gate.rs b/esp32c2/src/extmem/clock_gate.rs
index 10a6a1b70f..9f7a96137e 100644
--- a/esp32c2/src/extmem/clock_gate.rs
+++ b/esp32c2/src/extmem/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - clock gate enable."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/core0_acs_cache_int_ena.rs b/esp32c2/src/extmem/core0_acs_cache_int_ena.rs
index b7f892f452..a718d0c112 100644
--- a/esp32c2/src/extmem/core0_acs_cache_int_ena.rs
+++ b/esp32c2/src/extmem/core0_acs_cache_int_ena.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE0_ACS_CACHE_INT_ENA")
-            .field(
-                "core0_ibus_acs_msk_ic",
-                &format_args!("{}", self.core0_ibus_acs_msk_ic().bit()),
-            )
-            .field(
-                "core0_ibus_wr_ic",
-                &format_args!("{}", self.core0_ibus_wr_ic().bit()),
-            )
-            .field(
-                "core0_ibus_reject",
-                &format_args!("{}", self.core0_ibus_reject().bit()),
-            )
-            .field(
-                "core0_dbus_acs_msk_ic",
-                &format_args!("{}", self.core0_dbus_acs_msk_ic().bit()),
-            )
-            .field(
-                "core0_dbus_reject",
-                &format_args!("{}", self.core0_dbus_reject().bit()),
-            )
-            .field(
-                "core0_dbus_wr_ic",
-                &format_args!("{}", self.core0_dbus_wr_ic().bit()),
-            )
+            .field("core0_ibus_acs_msk_ic", &self.core0_ibus_acs_msk_ic())
+            .field("core0_ibus_wr_ic", &self.core0_ibus_wr_ic())
+            .field("core0_ibus_reject", &self.core0_ibus_reject())
+            .field("core0_dbus_acs_msk_ic", &self.core0_dbus_acs_msk_ic())
+            .field("core0_dbus_reject", &self.core0_dbus_reject())
+            .field("core0_dbus_wr_ic", &self.core0_dbus_wr_ic())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_ACS_CACHE_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/core0_acs_cache_int_st.rs b/esp32c2/src/extmem/core0_acs_cache_int_st.rs
index c4ffbb6de4..3c73f9c30d 100644
--- a/esp32c2/src/extmem/core0_acs_cache_int_st.rs
+++ b/esp32c2/src/extmem/core0_acs_cache_int_st.rs
@@ -50,37 +50,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE0_ACS_CACHE_INT_ST")
             .field(
                 "core0_ibus_acs_msk_icache",
-                &format_args!("{}", self.core0_ibus_acs_msk_icache().bit()),
-            )
-            .field(
-                "core0_ibus_wr_icache",
-                &format_args!("{}", self.core0_ibus_wr_icache().bit()),
-            )
-            .field(
-                "core0_ibus_reject",
-                &format_args!("{}", self.core0_ibus_reject().bit()),
+                &self.core0_ibus_acs_msk_icache(),
             )
+            .field("core0_ibus_wr_icache", &self.core0_ibus_wr_icache())
+            .field("core0_ibus_reject", &self.core0_ibus_reject())
             .field(
                 "core0_dbus_acs_msk_icache",
-                &format_args!("{}", self.core0_dbus_acs_msk_icache().bit()),
-            )
-            .field(
-                "core0_dbus_reject",
-                &format_args!("{}", self.core0_dbus_reject().bit()),
-            )
-            .field(
-                "core0_dbus_wr_icache",
-                &format_args!("{}", self.core0_dbus_wr_icache().bit()),
+                &self.core0_dbus_acs_msk_icache(),
             )
+            .field("core0_dbus_reject", &self.core0_dbus_reject())
+            .field("core0_dbus_wr_icache", &self.core0_dbus_wr_icache())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_ACS_CACHE_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_acs_cache_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE0_ACS_CACHE_INT_ST_SPEC;
 impl crate::RegisterSpec for CORE0_ACS_CACHE_INT_ST_SPEC {
diff --git a/esp32c2/src/extmem/core0_dbus_reject_st.rs b/esp32c2/src/extmem/core0_dbus_reject_st.rs
index 8fdfd8c053..a4bc8e7799 100644
--- a/esp32c2/src/extmem/core0_dbus_reject_st.rs
+++ b/esp32c2/src/extmem/core0_dbus_reject_st.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE0_DBUS_REJECT_ST")
-            .field(
-                "core0_dbus_attr",
-                &format_args!("{}", self.core0_dbus_attr().bits()),
-            )
-            .field(
-                "core0_dbus_world",
-                &format_args!("{}", self.core0_dbus_world().bit()),
-            )
+            .field("core0_dbus_attr", &self.core0_dbus_attr())
+            .field("core0_dbus_world", &self.core0_dbus_world())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_DBUS_REJECT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_dbus_reject_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE0_DBUS_REJECT_ST_SPEC;
 impl crate::RegisterSpec for CORE0_DBUS_REJECT_ST_SPEC {
diff --git a/esp32c2/src/extmem/core0_dbus_reject_vaddr.rs b/esp32c2/src/extmem/core0_dbus_reject_vaddr.rs
index 68c7e84849..a17bb73b98 100644
--- a/esp32c2/src/extmem/core0_dbus_reject_vaddr.rs
+++ b/esp32c2/src/extmem/core0_dbus_reject_vaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE0_DBUS_REJECT_VADDR")
-            .field(
-                "core0_dbus_vaddr",
-                &format_args!("{}", self.core0_dbus_vaddr().bits()),
-            )
+            .field("core0_dbus_vaddr", &self.core0_dbus_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_DBUS_REJECT_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_dbus_reject_vaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE0_DBUS_REJECT_VADDR_SPEC;
 impl crate::RegisterSpec for CORE0_DBUS_REJECT_VADDR_SPEC {
diff --git a/esp32c2/src/extmem/core0_ibus_reject_st.rs b/esp32c2/src/extmem/core0_ibus_reject_st.rs
index 50c6012fe5..0aaa797004 100644
--- a/esp32c2/src/extmem/core0_ibus_reject_st.rs
+++ b/esp32c2/src/extmem/core0_ibus_reject_st.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE0_IBUS_REJECT_ST")
-            .field(
-                "core0_ibus_attr",
-                &format_args!("{}", self.core0_ibus_attr().bits()),
-            )
-            .field(
-                "core0_ibus_world",
-                &format_args!("{}", self.core0_ibus_world().bit()),
-            )
+            .field("core0_ibus_attr", &self.core0_ibus_attr())
+            .field("core0_ibus_world", &self.core0_ibus_world())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_IBUS_REJECT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_ibus_reject_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE0_IBUS_REJECT_ST_SPEC;
 impl crate::RegisterSpec for CORE0_IBUS_REJECT_ST_SPEC {
diff --git a/esp32c2/src/extmem/core0_ibus_reject_vaddr.rs b/esp32c2/src/extmem/core0_ibus_reject_vaddr.rs
index b057eee3ec..5ec40b0949 100644
--- a/esp32c2/src/extmem/core0_ibus_reject_vaddr.rs
+++ b/esp32c2/src/extmem/core0_ibus_reject_vaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE0_IBUS_REJECT_VADDR")
-            .field(
-                "core0_ibus_vaddr",
-                &format_args!("{}", self.core0_ibus_vaddr().bits()),
-            )
+            .field("core0_ibus_vaddr", &self.core0_ibus_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_IBUS_REJECT_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_ibus_reject_vaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE0_IBUS_REJECT_VADDR_SPEC;
 impl crate::RegisterSpec for CORE0_IBUS_REJECT_VADDR_SPEC {
diff --git a/esp32c2/src/extmem/dbus_to_flash_end_vaddr.rs b/esp32c2/src/extmem/dbus_to_flash_end_vaddr.rs
index 12b9409c79..c208f1eb46 100644
--- a/esp32c2/src/extmem/dbus_to_flash_end_vaddr.rs
+++ b/esp32c2/src/extmem/dbus_to_flash_end_vaddr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS_TO_FLASH_END_VADDR")
-            .field(
-                "dbus_to_flash_end_vaddr",
-                &format_args!("{}", self.dbus_to_flash_end_vaddr().bits()),
-            )
+            .field("dbus_to_flash_end_vaddr", &self.dbus_to_flash_end_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_TO_FLASH_END_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/dbus_to_flash_start_vaddr.rs b/esp32c2/src/extmem/dbus_to_flash_start_vaddr.rs
index d1c1be85ea..c55bfa68da 100644
--- a/esp32c2/src/extmem/dbus_to_flash_start_vaddr.rs
+++ b/esp32c2/src/extmem/dbus_to_flash_start_vaddr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DBUS_TO_FLASH_START_VADDR")
             .field(
                 "dbus_to_flash_start_vaddr",
-                &format_args!("{}", self.dbus_to_flash_start_vaddr().bits()),
+                &self.dbus_to_flash_start_vaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_TO_FLASH_START_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/ibus_to_flash_end_vaddr.rs b/esp32c2/src/extmem/ibus_to_flash_end_vaddr.rs
index 4faaf9186c..da99ec46a0 100644
--- a/esp32c2/src/extmem/ibus_to_flash_end_vaddr.rs
+++ b/esp32c2/src/extmem/ibus_to_flash_end_vaddr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS_TO_FLASH_END_VADDR")
-            .field(
-                "ibus_to_flash_end_vaddr",
-                &format_args!("{}", self.ibus_to_flash_end_vaddr().bits()),
-            )
+            .field("ibus_to_flash_end_vaddr", &self.ibus_to_flash_end_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS_TO_FLASH_END_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/ibus_to_flash_start_vaddr.rs b/esp32c2/src/extmem/ibus_to_flash_start_vaddr.rs
index 281f5fcb29..2375f70cb2 100644
--- a/esp32c2/src/extmem/ibus_to_flash_start_vaddr.rs
+++ b/esp32c2/src/extmem/ibus_to_flash_start_vaddr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("IBUS_TO_FLASH_START_VADDR")
             .field(
                 "ibus_to_flash_start_vaddr",
-                &format_args!("{}", self.ibus_to_flash_start_vaddr().bits()),
+                &self.ibus_to_flash_start_vaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS_TO_FLASH_START_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/icache_atomic_operate_ena.rs b/esp32c2/src/extmem/icache_atomic_operate_ena.rs
index 618836c304..4b13688395 100644
--- a/esp32c2/src/extmem/icache_atomic_operate_ena.rs
+++ b/esp32c2/src/extmem/icache_atomic_operate_ena.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ICACHE_ATOMIC_OPERATE_ENA")
             .field(
                 "icache_atomic_operate_ena",
-                &format_args!("{}", self.icache_atomic_operate_ena().bit()),
+                &self.icache_atomic_operate_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_ATOMIC_OPERATE_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/icache_ctrl.rs b/esp32c2/src/extmem/icache_ctrl.rs
index d66682cf3e..686c2c437d 100644
--- a/esp32c2/src/extmem/icache_ctrl.rs
+++ b/esp32c2/src/extmem/icache_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_CTRL")
-            .field(
-                "icache_enable",
-                &format_args!("{}", self.icache_enable().bit()),
-            )
+            .field("icache_enable", &self.icache_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/icache_ctrl1.rs b/esp32c2/src/extmem/icache_ctrl1.rs
index cb385d3e1b..67c2d4831e 100644
--- a/esp32c2/src/extmem/icache_ctrl1.rs
+++ b/esp32c2/src/extmem/icache_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_CTRL1")
-            .field(
-                "icache_shut_ibus",
-                &format_args!("{}", self.icache_shut_ibus().bit()),
-            )
-            .field(
-                "icache_shut_dbus",
-                &format_args!("{}", self.icache_shut_dbus().bit()),
-            )
+            .field("icache_shut_ibus", &self.icache_shut_ibus())
+            .field("icache_shut_dbus", &self.icache_shut_dbus())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable core0 ibus, 0: enable, 1: disable"]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/icache_freeze.rs b/esp32c2/src/extmem/icache_freeze.rs
index 4005fb2d4f..ec25af3086 100644
--- a/esp32c2/src/extmem/icache_freeze.rs
+++ b/esp32c2/src/extmem/icache_freeze.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_FREEZE")
-            .field("ena", &format_args!("{}", self.ena().bit()))
-            .field("mode", &format_args!("{}", self.mode().bit()))
-            .field("done", &format_args!("{}", self.done().bit()))
+            .field("ena", &self.ena())
+            .field("mode", &self.mode())
+            .field("done", &self.done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_FREEZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable icache freeze mode"]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/icache_sync_addr.rs b/esp32c2/src/extmem/icache_sync_addr.rs
index 9cac709d40..e2b333138a 100644
--- a/esp32c2/src/extmem/icache_sync_addr.rs
+++ b/esp32c2/src/extmem/icache_sync_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_SYNC_ADDR")
-            .field(
-                "icache_sync_addr",
-                &format_args!("{}", self.icache_sync_addr().bits()),
-            )
+            .field("icache_sync_addr", &self.icache_sync_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_SYNC_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/icache_sync_ctrl.rs b/esp32c2/src/extmem/icache_sync_ctrl.rs
index 7b54757039..cca9b51d32 100644
--- a/esp32c2/src/extmem/icache_sync_ctrl.rs
+++ b/esp32c2/src/extmem/icache_sync_ctrl.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_SYNC_CTRL")
-            .field(
-                "icache_invalidate_ena",
-                &format_args!("{}", self.icache_invalidate_ena().bit()),
-            )
-            .field(
-                "icache_sync_done",
-                &format_args!("{}", self.icache_sync_done().bit()),
-            )
+            .field("icache_invalidate_ena", &self.icache_invalidate_ena())
+            .field("icache_sync_done", &self.icache_sync_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_SYNC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/icache_sync_size.rs b/esp32c2/src/extmem/icache_sync_size.rs
index ee9ab1b5f5..49b7a8d882 100644
--- a/esp32c2/src/extmem/icache_sync_size.rs
+++ b/esp32c2/src/extmem/icache_sync_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_SYNC_SIZE")
-            .field(
-                "icache_sync_size",
-                &format_args!("{}", self.icache_sync_size().bits()),
-            )
+            .field("icache_sync_size", &self.icache_sync_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_SYNC_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:22 - The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/icache_tag_power_ctrl.rs b/esp32c2/src/extmem/icache_tag_power_ctrl.rs
index c098fe63ce..2c7a413dba 100644
--- a/esp32c2/src/extmem/icache_tag_power_ctrl.rs
+++ b/esp32c2/src/extmem/icache_tag_power_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_TAG_POWER_CTRL")
-            .field(
-                "icache_tag_mem_force_on",
-                &format_args!("{}", self.icache_tag_mem_force_on().bit()),
-            )
-            .field(
-                "icache_tag_mem_force_pd",
-                &format_args!("{}", self.icache_tag_mem_force_pd().bit()),
-            )
-            .field(
-                "icache_tag_mem_force_pu",
-                &format_args!("{}", self.icache_tag_mem_force_pu().bit()),
-            )
+            .field("icache_tag_mem_force_on", &self.icache_tag_mem_force_on())
+            .field("icache_tag_mem_force_pd", &self.icache_tag_mem_force_pd())
+            .field("icache_tag_mem_force_pu", &self.icache_tag_mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_TAG_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32c2/src/extmem/reg_date.rs b/esp32c2/src/extmem/reg_date.rs
index a66336d1bb..b9f4c55d15 100644
--- a/esp32c2/src/extmem/reg_date.rs
+++ b/esp32c2/src/extmem/reg_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - version information"]
     #[inline(always)]
diff --git a/esp32c2/src/generic.rs b/esp32c2/src/generic.rs
index a2ae6aa053..45ebed16c4 100644
--- a/esp32c2/src/generic.rs
+++ b/esp32c2/src/generic.rs
@@ -48,7 +48,7 @@ pub trait RegisterSpec {
 #[doc = " Raw field type"]
 pub trait FieldSpec: Sized {
     #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
-    type Ux: Copy + PartialEq + From<Self>;
+    type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
 }
 #[doc = " Marker for fields with fixed values"]
 pub trait IsEnum: FieldSpec {}
@@ -237,6 +237,14 @@ impl<REG: Readable + Writable> Reg<REG> {
         );
     }
 }
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
 #[doc(hidden)]
 pub mod raw;
 #[doc = " Register reader."]
@@ -302,6 +310,11 @@ impl<FI: FieldSpec> FieldReader<FI> {
         self.bits
     }
 }
+impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 impl<FI> PartialEq<FI> for FieldReader<FI>
 where
     FI: FieldSpec + Copy,
@@ -338,10 +351,21 @@ impl<FI> BitReader<FI> {
         self.bit()
     }
 }
+impl<FI> core::fmt::Debug for BitReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 #[doc = " Marker for register/field writers which can take any value of specified width"]
 pub struct Safe;
 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
 pub struct Unsafe;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct Range<const MIN: u64, const MAX: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeFrom<const MIN: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeTo<const MAX: u64>;
 #[doc = " Write field Proxy"]
 pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
     raw::FieldWriter<'a, REG, WI, FI, Safety>;
@@ -393,6 +417,58 @@ where
         unsafe { self.bits(value) }
     }
 }
+impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
+    FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN && value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
 impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
diff --git a/esp32c2/src/gpio/bt_select.rs b/esp32c2/src/gpio/bt_select.rs
index d4bbc43143..d78b414754 100644
--- a/esp32c2/src/gpio/bt_select.rs
+++ b/esp32c2/src/gpio/bt_select.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_SELECT")
-            .field("bt_sel", &format_args!("{}", self.bt_sel().bits()))
+            .field("bt_sel", &self.bt_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_SELECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO bit select register"]
     #[inline(always)]
diff --git a/esp32c2/src/gpio/clock_gate.rs b/esp32c2/src/gpio/clock_gate.rs
index ebd199051e..d2bfefd1b8 100644
--- a/esp32c2/src/gpio/clock_gate.rs
+++ b/esp32c2/src/gpio/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this bit to enable GPIO clock gate"]
     #[inline(always)]
diff --git a/esp32c2/src/gpio/cpusdio_int.rs b/esp32c2/src/gpio/cpusdio_int.rs
index 97dd349f30..1b86891ffe 100644
--- a/esp32c2/src/gpio/cpusdio_int.rs
+++ b/esp32c2/src/gpio/cpusdio_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPUSDIO_INT")
-            .field("sdio_int", &format_args!("{}", self.sdio_int().bits()))
+            .field("sdio_int", &self.sdio_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPUSDIO_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO CPUSDIO interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpusdio_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPUSDIO_INT_SPEC;
 impl crate::RegisterSpec for CPUSDIO_INT_SPEC {
diff --git a/esp32c2/src/gpio/enable.rs b/esp32c2/src/gpio/enable.rs
index de0fa0734b..1dd8d29765 100644
--- a/esp32c2/src/gpio/enable.rs
+++ b/esp32c2/src/gpio/enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:24 - GPIO output enable register for GPIO0-24"]
     #[inline(always)]
diff --git a/esp32c2/src/gpio/func_in_sel_cfg.rs b/esp32c2/src/gpio/func_in_sel_cfg.rs
index 2b4b31c383..2bed8a7021 100644
--- a/esp32c2/src/gpio/func_in_sel_cfg.rs
+++ b/esp32c2/src/gpio/func_in_sel_cfg.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_IN_SEL_CFG")
-            .field("in_sel", &format_args!("{}", self.in_sel().bits()))
-            .field("in_inv_sel", &format_args!("{}", self.in_inv_sel().bit()))
-            .field("sel", &format_args!("{}", self.sel().bit()))
+            .field("in_sel", &self.in_sel())
+            .field("in_inv_sel", &self.in_inv_sel())
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - set this value: s=0-53: connect GPIO\\[s\\] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level."]
     #[inline(always)]
diff --git a/esp32c2/src/gpio/func_out_sel_cfg.rs b/esp32c2/src/gpio/func_out_sel_cfg.rs
index 8173ce0edb..fb8dff8c69 100644
--- a/esp32c2/src/gpio/func_out_sel_cfg.rs
+++ b/esp32c2/src/gpio/func_out_sel_cfg.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_OUT_SEL_CFG")
-            .field("out_sel", &format_args!("{}", self.out_sel().bits()))
-            .field("inv_sel", &format_args!("{}", self.inv_sel().bit()))
-            .field("oen_sel", &format_args!("{}", self.oen_sel().bit()))
-            .field("oen_inv_sel", &format_args!("{}", self.oen_inv_sel().bit()))
+            .field("out_sel", &self.out_sel())
+            .field("inv_sel", &self.inv_sel())
+            .field("oen_sel", &self.oen_sel())
+            .field("oen_inv_sel", &self.oen_inv_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
     #[inline(always)]
diff --git a/esp32c2/src/gpio/in_.rs b/esp32c2/src/gpio/in_.rs
index ac3dd4c7b9..7dfd708041 100644
--- a/esp32c2/src/gpio/in_.rs
+++ b/esp32c2/src/gpio/in_.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN")
-            .field("data_next", &format_args!("{}", self.data_next().bits()))
+            .field("data_next", &self.data_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO input register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SPEC;
 impl crate::RegisterSpec for IN_SPEC {
diff --git a/esp32c2/src/gpio/out.rs b/esp32c2/src/gpio/out.rs
index 6454488c54..5665b45382 100644
--- a/esp32c2/src/gpio/out.rs
+++ b/esp32c2/src/gpio/out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT")
-            .field("data_orig", &format_args!("{}", self.data_orig().bits()))
+            .field("data_orig", &self.data_orig())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:24 - GPIO output register for GPIO0-24"]
     #[inline(always)]
diff --git a/esp32c2/src/gpio/pcpu_int.rs b/esp32c2/src/gpio/pcpu_int.rs
index d972c4c1b3..552c5140b2 100644
--- a/esp32c2/src/gpio/pcpu_int.rs
+++ b/esp32c2/src/gpio/pcpu_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_INT")
-            .field("procpu_int", &format_args!("{}", self.procpu_int().bits()))
+            .field("procpu_int", &self.procpu_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO PRO_CPU interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_INT_SPEC;
 impl crate::RegisterSpec for PCPU_INT_SPEC {
diff --git a/esp32c2/src/gpio/pcpu_nmi_int.rs b/esp32c2/src/gpio/pcpu_nmi_int.rs
index 56de383a7e..b4e1e2065d 100644
--- a/esp32c2/src/gpio/pcpu_nmi_int.rs
+++ b/esp32c2/src/gpio/pcpu_nmi_int.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_NMI_INT")
-            .field(
-                "procpu_nmi_int",
-                &format_args!("{}", self.procpu_nmi_int().bits()),
-            )
+            .field("procpu_nmi_int", &self.procpu_nmi_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_NMI_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO PRO_CPU(not shielded) interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_nmi_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_NMI_INT_SPEC;
 impl crate::RegisterSpec for PCPU_NMI_INT_SPEC {
diff --git a/esp32c2/src/gpio/pin.rs b/esp32c2/src/gpio/pin.rs
index 582513e76d..37d6329326 100644
--- a/esp32c2/src/gpio/pin.rs
+++ b/esp32c2/src/gpio/pin.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN")
-            .field(
-                "sync2_bypass",
-                &format_args!("{}", self.sync2_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field(
-                "sync1_bypass",
-                &format_args!("{}", self.sync1_bypass().bits()),
-            )
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("config", &format_args!("{}", self.config().bits()))
-            .field("int_ena", &format_args!("{}", self.int_ena().bits()))
+            .field("sync2_bypass", &self.sync2_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("sync1_bypass", &self.sync1_bypass())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("config", &self.config())
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
     #[inline(always)]
diff --git a/esp32c2/src/gpio/reg_date.rs b/esp32c2/src/gpio/reg_date.rs
index fd918b3744..e92ec41b06 100644
--- a/esp32c2/src/gpio/reg_date.rs
+++ b/esp32c2/src/gpio/reg_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_DATE")
-            .field("reg_date", &format_args!("{}", self.reg_date().bits()))
+            .field("reg_date", &self.reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - version register"]
     #[inline(always)]
diff --git a/esp32c2/src/gpio/sdio_select.rs b/esp32c2/src/gpio/sdio_select.rs
index 0f94b5932d..557422a488 100644
--- a/esp32c2/src/gpio/sdio_select.rs
+++ b/esp32c2/src/gpio/sdio_select.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_SELECT")
-            .field("sdio_sel", &format_args!("{}", self.sdio_sel().bits()))
+            .field("sdio_sel", &self.sdio_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_SELECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - GPIO sdio select register"]
     #[inline(always)]
diff --git a/esp32c2/src/gpio/status.rs b/esp32c2/src/gpio/status.rs
index 4e35d2d5aa..548219ed3b 100644
--- a/esp32c2/src/gpio/status.rs
+++ b/esp32c2/src/gpio/status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("interrupt", &format_args!("{}", self.interrupt().bits()))
+            .field("interrupt", &self.interrupt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:24 - GPIO interrupt status register for GPIO0-24"]
     #[inline(always)]
diff --git a/esp32c2/src/gpio/status_next.rs b/esp32c2/src/gpio/status_next.rs
index 6364355d37..80238cfa32 100644
--- a/esp32c2/src/gpio/status_next.rs
+++ b/esp32c2/src/gpio/status_next.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_NEXT")
-            .field(
-                "status_interrupt_next",
-                &format_args!("{}", self.status_interrupt_next().bits()),
-            )
+            .field("status_interrupt_next", &self.status_interrupt_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_NEXT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt source register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_NEXT_SPEC;
 impl crate::RegisterSpec for STATUS_NEXT_SPEC {
diff --git a/esp32c2/src/gpio/strap.rs b/esp32c2/src/gpio/strap.rs
index dfc141ecfb..3bc90c4409 100644
--- a/esp32c2/src/gpio/strap.rs
+++ b/esp32c2/src/gpio/strap.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STRAP")
-            .field("strapping", &format_args!("{}", self.strapping().bits()))
+            .field("strapping", &self.strapping())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STRAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "pad strapping register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`strap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STRAP_SPEC;
 impl crate::RegisterSpec for STRAP_SPEC {
diff --git a/esp32c2/src/i2c0/clk_conf.rs b/esp32c2/src/i2c0/clk_conf.rs
index 0c369fb990..8575bb85bf 100644
--- a/esp32c2/src/i2c0/clk_conf.rs
+++ b/esp32c2/src/i2c0/clk_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bit()))
-            .field("sclk_active", &format_args!("{}", self.sclk_active().bit()))
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_active", &self.sclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/comd.rs b/esp32c2/src/i2c0/comd.rs
index 6f909ae304..980d858d87 100644
--- a/esp32c2/src/i2c0/comd.rs
+++ b/esp32c2/src/i2c0/comd.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMD")
-            .field("command", &format_args!("{}", self.command().bits()))
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This is the content of command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/ctr.rs b/esp32c2/src/i2c0/ctr.rs
index 29bd0cd789..552db031e9 100644
--- a/esp32c2/src/i2c0/ctr.rs
+++ b/esp32c2/src/i2c0/ctr.rs
@@ -104,49 +104,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTR")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field(
-                "sample_scl_level",
-                &format_args!("{}", self.sample_scl_level().bit()),
-            )
-            .field(
-                "rx_full_ack_level",
-                &format_args!("{}", self.rx_full_ack_level().bit()),
-            )
-            .field("ms_mode", &format_args!("{}", self.ms_mode().bit()))
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "arbitration_en",
-                &format_args!("{}", self.arbitration_en().bit()),
-            )
-            .field(
-                "slv_tx_auto_start_en",
-                &format_args!("{}", self.slv_tx_auto_start_en().bit()),
-            )
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("sample_scl_level", &self.sample_scl_level())
+            .field("rx_full_ack_level", &self.rx_full_ack_level())
+            .field("ms_mode", &self.ms_mode())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("clk_en", &self.clk_en())
+            .field("arbitration_en", &self.arbitration_en())
+            .field("slv_tx_auto_start_en", &self.slv_tx_auto_start_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 0: direct output, 1: open drain output."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/data.rs b/esp32c2/src/i2c0/data.rs
index 098982488f..ffd32b29d3 100644
--- a/esp32c2/src/i2c0/data.rs
+++ b/esp32c2/src/i2c0/data.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field("fifo_rdata", &format_args!("{}", self.fifo_rdata().bits()))
+            .field("fifo_rdata", &self.fifo_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value of rx FIFO read data."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/date.rs b/esp32c2/src/i2c0/date.rs
index 5e9f82ca34..d563e38ed2 100644
--- a/esp32c2/src/i2c0/date.rs
+++ b/esp32c2/src/i2c0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/i2c0/fifo_conf.rs b/esp32c2/src/i2c0/fifo_conf.rs
index 8d7bcf4e41..765107a861 100644
--- a/esp32c2/src/i2c0/fifo_conf.rs
+++ b/esp32c2/src/i2c0/fifo_conf.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CONF")
-            .field(
-                "rxfifo_wm_thrhd",
-                &format_args!("{}", self.rxfifo_wm_thrhd().bits()),
-            )
-            .field(
-                "txfifo_wm_thrhd",
-                &format_args!("{}", self.txfifo_wm_thrhd().bits()),
-            )
-            .field("nonfifo_en", &format_args!("{}", self.nonfifo_en().bit()))
-            .field("rx_fifo_rst", &format_args!("{}", self.rx_fifo_rst().bit()))
-            .field("tx_fifo_rst", &format_args!("{}", self.tx_fifo_rst().bit()))
-            .field("fifo_prt_en", &format_args!("{}", self.fifo_prt_en().bit()))
+            .field("rxfifo_wm_thrhd", &self.rxfifo_wm_thrhd())
+            .field("txfifo_wm_thrhd", &self.txfifo_wm_thrhd())
+            .field("nonfifo_en", &self.nonfifo_en())
+            .field("rx_fifo_rst", &self.rx_fifo_rst())
+            .field("tx_fifo_rst", &self.tx_fifo_rst())
+            .field("fifo_prt_en", &self.fifo_prt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[3:0\\], reg_rxfifo_wm_int_raw bit will be valid."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/fifo_st.rs b/esp32c2/src/i2c0/fifo_st.rs
index 566d9a1fdb..fda04e5d4d 100644
--- a/esp32c2/src/i2c0/fifo_st.rs
+++ b/esp32c2/src/i2c0/fifo_st.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_ST")
-            .field(
-                "rxfifo_raddr",
-                &format_args!("{}", self.rxfifo_raddr().bits()),
-            )
-            .field(
-                "rxfifo_waddr",
-                &format_args!("{}", self.rxfifo_waddr().bits()),
-            )
-            .field(
-                "txfifo_raddr",
-                &format_args!("{}", self.txfifo_raddr().bits()),
-            )
-            .field(
-                "txfifo_waddr",
-                &format_args!("{}", self.txfifo_waddr().bits()),
-            )
+            .field("rxfifo_raddr", &self.rxfifo_raddr())
+            .field("rxfifo_waddr", &self.rxfifo_waddr())
+            .field("txfifo_raddr", &self.txfifo_raddr())
+            .field("txfifo_waddr", &self.txfifo_waddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "FIFO status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_ST_SPEC;
 impl crate::RegisterSpec for FIFO_ST_SPEC {
diff --git a/esp32c2/src/i2c0/filter_cfg.rs b/esp32c2/src/i2c0/filter_cfg.rs
index b05ae9a4bf..98bdaa5979 100644
--- a/esp32c2/src/i2c0/filter_cfg.rs
+++ b/esp32c2/src/i2c0/filter_cfg.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CFG")
-            .field(
-                "scl_filter_thres",
-                &format_args!("{}", self.scl_filter_thres().bits()),
-            )
-            .field(
-                "sda_filter_thres",
-                &format_args!("{}", self.sda_filter_thres().bits()),
-            )
-            .field(
-                "scl_filter_en",
-                &format_args!("{}", self.scl_filter_en().bit()),
-            )
-            .field(
-                "sda_filter_en",
-                &format_args!("{}", self.sda_filter_en().bit()),
-            )
+            .field("scl_filter_thres", &self.scl_filter_thres())
+            .field("sda_filter_thres", &self.sda_filter_thres())
+            .field("scl_filter_en", &self.scl_filter_en())
+            .field("sda_filter_en", &self.sda_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/int_ena.rs b/esp32c2/src/i2c0/int_ena.rs
index 8accc9e1dd..535b34f92b 100644
--- a/esp32c2/src/i2c0/int_ena.rs
+++ b/esp32c2/src/i2c0/int_ena.rs
@@ -152,46 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/int_raw.rs b/esp32c2/src/i2c0/int_raw.rs
index 1ac9726d40..cd92338ced 100644
--- a/esp32c2/src/i2c0/int_raw.rs
+++ b/esp32c2/src/i2c0/int_raw.rs
@@ -118,46 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32c2/src/i2c0/int_st.rs b/esp32c2/src/i2c0/int_st.rs
index 1ffb4021ac..3ca3ab4a2e 100644
--- a/esp32c2/src/i2c0/int_st.rs
+++ b/esp32c2/src/i2c0/int_st.rs
@@ -118,46 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of captured I2C communication events\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c2/src/i2c0/rxfifo_start_addr.rs b/esp32c2/src/i2c0/rxfifo_start_addr.rs
index 634e8c8360..be2fa3cb09 100644
--- a/esp32c2/src/i2c0/rxfifo_start_addr.rs
+++ b/esp32c2/src/i2c0/rxfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXFIFO_START_ADDR")
-            .field(
-                "rxfifo_start_addr",
-                &format_args!("{}", self.rxfifo_start_addr().bits()),
-            )
+            .field("rxfifo_start_addr", &self.rxfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C RXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for RXFIFO_START_ADDR_SPEC {
diff --git a/esp32c2/src/i2c0/scl_high_period.rs b/esp32c2/src/i2c0/scl_high_period.rs
index f8a536137d..d5ba861338 100644
--- a/esp32c2/src/i2c0/scl_high_period.rs
+++ b/esp32c2/src/i2c0/scl_high_period.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH_PERIOD")
-            .field(
-                "scl_high_period",
-                &format_args!("{}", self.scl_high_period().bits()),
-            )
-            .field(
-                "scl_wait_high_period",
-                &format_args!("{}", self.scl_wait_high_period().bits()),
-            )
+            .field("scl_high_period", &self.scl_high_period())
+            .field("scl_wait_high_period", &self.scl_wait_high_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/scl_low_period.rs b/esp32c2/src/i2c0/scl_low_period.rs
index bb4cd05e6d..c75461f0c7 100644
--- a/esp32c2/src/i2c0/scl_low_period.rs
+++ b/esp32c2/src/i2c0/scl_low_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW_PERIOD")
-            .field(
-                "scl_low_period",
-                &format_args!("{}", self.scl_low_period().bits()),
-            )
+            .field("scl_low_period", &self.scl_low_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/scl_main_st_time_out.rs b/esp32c2/src/i2c0/scl_main_st_time_out.rs
index 7c392d273a..99069d3ce8 100644
--- a/esp32c2/src/i2c0/scl_main_st_time_out.rs
+++ b/esp32c2/src/i2c0/scl_main_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_MAIN_ST_TIME_OUT")
-            .field(
-                "scl_main_st_to_i2c",
-                &format_args!("{}", self.scl_main_st_to_i2c().bits()),
-            )
+            .field("scl_main_st_to_i2c", &self.scl_main_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_MAIN_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23"]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/scl_rstart_setup.rs b/esp32c2/src/i2c0/scl_rstart_setup.rs
index 5f61d4fc91..63ddddc0f2 100644
--- a/esp32c2/src/i2c0/scl_rstart_setup.rs
+++ b/esp32c2/src/i2c0/scl_rstart_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_RSTART_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_RSTART_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/scl_sp_conf.rs b/esp32c2/src/i2c0/scl_sp_conf.rs
index e3cdc353bf..492452e245 100644
--- a/esp32c2/src/i2c0/scl_sp_conf.rs
+++ b/esp32c2/src/i2c0/scl_sp_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_SP_CONF")
-            .field(
-                "scl_rst_slv_en",
-                &format_args!("{}", self.scl_rst_slv_en().bit()),
-            )
-            .field(
-                "scl_rst_slv_num",
-                &format_args!("{}", self.scl_rst_slv_num().bits()),
-            )
-            .field("scl_pd_en", &format_args!("{}", self.scl_pd_en().bit()))
-            .field("sda_pd_en", &format_args!("{}", self.sda_pd_en().bit()))
+            .field("scl_rst_slv_en", &self.scl_rst_slv_en())
+            .field("scl_rst_slv_num", &self.scl_rst_slv_num())
+            .field("scl_pd_en", &self.scl_pd_en())
+            .field("sda_pd_en", &self.sda_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_SP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/scl_st_time_out.rs b/esp32c2/src/i2c0/scl_st_time_out.rs
index ba02a4a885..e56dd94c72 100644
--- a/esp32c2/src/i2c0/scl_st_time_out.rs
+++ b/esp32c2/src/i2c0/scl_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_ST_TIME_OUT")
-            .field(
-                "scl_st_to_i2c",
-                &format_args!("{}", self.scl_st_to_i2c().bits()),
-            )
+            .field("scl_st_to_i2c", &self.scl_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The threshold value of SCL_FSM state unchanged period. It should be o more than 23"]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/scl_start_hold.rs b/esp32c2/src/i2c0/scl_start_hold.rs
index eaa7d6ef78..073d03f4ca 100644
--- a/esp32c2/src/i2c0/scl_start_hold.rs
+++ b/esp32c2/src/i2c0/scl_start_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/scl_stop_hold.rs b/esp32c2/src/i2c0/scl_stop_hold.rs
index edfbb10e29..3a115f7912 100644
--- a/esp32c2/src/i2c0/scl_stop_hold.rs
+++ b/esp32c2/src/i2c0/scl_stop_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the delay after the STOP condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/scl_stop_setup.rs b/esp32c2/src/i2c0/scl_stop_setup.rs
index f231319c28..592044b6a2 100644
--- a/esp32c2/src/i2c0/scl_stop_setup.rs
+++ b/esp32c2/src/i2c0/scl_stop_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/sda_hold.rs b/esp32c2/src/i2c0/sda_hold.rs
index b16485e33b..817872197e 100644
--- a/esp32c2/src/i2c0/sda_hold.rs
+++ b/esp32c2/src/i2c0/sda_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time to hold the data after the negative edge of SCL, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/sda_sample.rs b/esp32c2/src/i2c0/sda_sample.rs
index 5a56fc1aa2..a8bd733614 100644
--- a/esp32c2/src/i2c0/sda_sample.rs
+++ b/esp32c2/src/i2c0/sda_sample.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_SAMPLE")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SDA is sampled, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/sr.rs b/esp32c2/src/i2c0/sr.rs
index b12f9fe5e7..12408b7b23 100644
--- a/esp32c2/src/i2c0/sr.rs
+++ b/esp32c2/src/i2c0/sr.rs
@@ -55,28 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR")
-            .field("resp_rec", &format_args!("{}", self.resp_rec().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field(
-                "scl_main_state_last",
-                &format_args!("{}", self.scl_main_state_last().bits()),
-            )
-            .field(
-                "scl_state_last",
-                &format_args!("{}", self.scl_state_last().bits()),
-            )
+            .field("resp_rec", &self.resp_rec())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("scl_main_state_last", &self.scl_main_state_last())
+            .field("scl_state_last", &self.scl_state_last())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Describe I2C work status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SR_SPEC;
 impl crate::RegisterSpec for SR_SPEC {
diff --git a/esp32c2/src/i2c0/to.rs b/esp32c2/src/i2c0/to.rs
index 92f73cdd2b..cf95ff843d 100644
--- a/esp32c2/src/i2c0/to.rs
+++ b/esp32c2/src/i2c0/to.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO")
-            .field(
-                "time_out_value",
-                &format_args!("{}", self.time_out_value().bits()),
-            )
-            .field("time_out_en", &format_args!("{}", self.time_out_en().bit()))
+            .field("time_out_value", &self.time_out_value())
+            .field("time_out_en", &self.time_out_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to configure the timeout for receiving a data bit in APB clock cycles."]
     #[inline(always)]
diff --git a/esp32c2/src/i2c0/txfifo_start_addr.rs b/esp32c2/src/i2c0/txfifo_start_addr.rs
index 8df0b6828e..c7cd4f0ea5 100644
--- a/esp32c2/src/i2c0/txfifo_start_addr.rs
+++ b/esp32c2/src/i2c0/txfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXFIFO_START_ADDR")
-            .field(
-                "txfifo_start_addr",
-                &format_args!("{}", self.txfifo_start_addr().bits()),
-            )
+            .field("txfifo_start_addr", &self.txfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C TXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for TXFIFO_START_ADDR_SPEC {
diff --git a/esp32c2/src/interrupt_core0/apb_adc_int_map.rs b/esp32c2/src/interrupt_core0/apb_adc_int_map.rs
index 45f590b04f..2f34e475fc 100644
--- a/esp32c2/src/interrupt_core0/apb_adc_int_map.rs
+++ b/esp32c2/src/interrupt_core0/apb_adc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_ADC_INT_MAP")
-            .field(
-                "apb_adc_int_map",
-                &format_args!("{}", self.apb_adc_int_map().bits()),
-            )
+            .field("apb_adc_int_map", &self.apb_adc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_ADC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/apb_ctrl_intr_map.rs b/esp32c2/src/interrupt_core0/apb_ctrl_intr_map.rs
index e2659955d9..402f8643d5 100644
--- a/esp32c2/src/interrupt_core0/apb_ctrl_intr_map.rs
+++ b/esp32c2/src/interrupt_core0/apb_ctrl_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_CTRL_INTR_MAP")
-            .field(
-                "apb_ctrl_intr_map",
-                &format_args!("{}", self.apb_ctrl_intr_map().bits()),
-            )
+            .field("apb_ctrl_intr_map", &self.apb_ctrl_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_CTRL_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/assist_debug_intr_map.rs b/esp32c2/src/interrupt_core0/assist_debug_intr_map.rs
index 076077ee3c..0bb44517d8 100644
--- a/esp32c2/src/interrupt_core0/assist_debug_intr_map.rs
+++ b/esp32c2/src/interrupt_core0/assist_debug_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ASSIST_DEBUG_INTR_MAP")
-            .field(
-                "assist_debug_intr_map",
-                &format_args!("{}", self.assist_debug_intr_map().bits()),
-            )
+            .field("assist_debug_intr_map", &self.assist_debug_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ASSIST_DEBUG_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/ble_sec_int_map.rs b/esp32c2/src/interrupt_core0/ble_sec_int_map.rs
index a1abe5bfab..edd05cef1a 100644
--- a/esp32c2/src/interrupt_core0/ble_sec_int_map.rs
+++ b/esp32c2/src/interrupt_core0/ble_sec_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLE_SEC_INT_MAP")
-            .field(
-                "ble_sec_int_map",
-                &format_args!("{}", self.ble_sec_int_map().bits()),
-            )
+            .field("ble_sec_int_map", &self.ble_sec_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLE_SEC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/ble_timer_int_map.rs b/esp32c2/src/interrupt_core0/ble_timer_int_map.rs
index 613f57cc06..36eb1010cf 100644
--- a/esp32c2/src/interrupt_core0/ble_timer_int_map.rs
+++ b/esp32c2/src/interrupt_core0/ble_timer_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLE_TIMER_INT_MAP")
-            .field(
-                "ble_timer_int_map",
-                &format_args!("{}", self.ble_timer_int_map().bits()),
-            )
+            .field("ble_timer_int_map", &self.ble_timer_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLE_TIMER_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/bt_bb_int_map.rs b/esp32c2/src/interrupt_core0/bt_bb_int_map.rs
index ad46e2549f..351b9e88c8 100644
--- a/esp32c2/src/interrupt_core0/bt_bb_int_map.rs
+++ b/esp32c2/src/interrupt_core0/bt_bb_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_BB_INT_MAP")
-            .field(
-                "bt_bb_int_map",
-                &format_args!("{}", self.bt_bb_int_map().bits()),
-            )
+            .field("bt_bb_int_map", &self.bt_bb_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_BB_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/bt_bb_nmi_map.rs b/esp32c2/src/interrupt_core0/bt_bb_nmi_map.rs
index bb82782f07..ed8c9bec71 100644
--- a/esp32c2/src/interrupt_core0/bt_bb_nmi_map.rs
+++ b/esp32c2/src/interrupt_core0/bt_bb_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_BB_NMI_MAP")
-            .field(
-                "bt_bb_nmi_map",
-                &format_args!("{}", self.bt_bb_nmi_map().bits()),
-            )
+            .field("bt_bb_nmi_map", &self.bt_bb_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_BB_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/bt_mac_int_map.rs b/esp32c2/src/interrupt_core0/bt_mac_int_map.rs
index 1ddf48a370..99d86a0c44 100644
--- a/esp32c2/src/interrupt_core0/bt_mac_int_map.rs
+++ b/esp32c2/src/interrupt_core0/bt_mac_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_MAC_INT_MAP")
-            .field(
-                "bt_mac_int_map",
-                &format_args!("{}", self.bt_mac_int_map().bits()),
-            )
+            .field("bt_mac_int_map", &self.bt_mac_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_MAC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/cache_core0_acs_int_map.rs b/esp32c2/src/interrupt_core0/cache_core0_acs_int_map.rs
index a4cae2dfdf..38591af650 100644
--- a/esp32c2/src/interrupt_core0/cache_core0_acs_int_map.rs
+++ b/esp32c2/src/interrupt_core0/cache_core0_acs_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_CORE0_ACS_INT_MAP")
-            .field(
-                "cache_core0_acs_int_map",
-                &format_args!("{}", self.cache_core0_acs_int_map().bits()),
-            )
+            .field("cache_core0_acs_int_map", &self.cache_core0_acs_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CORE0_ACS_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/cache_ia_int_map.rs b/esp32c2/src/interrupt_core0/cache_ia_int_map.rs
index e5da0ab7db..0f60d2c814 100644
--- a/esp32c2/src/interrupt_core0/cache_ia_int_map.rs
+++ b/esp32c2/src/interrupt_core0/cache_ia_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_IA_INT_MAP")
-            .field(
-                "cache_ia_int_map",
-                &format_args!("{}", self.cache_ia_int_map().bits()),
-            )
+            .field("cache_ia_int_map", &self.cache_ia_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_IA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/clock_gate.rs b/esp32c2/src/interrupt_core0/clock_gate.rs
index 57e612f429..f275565282 100644
--- a/esp32c2/src/interrupt_core0/clock_gate.rs
+++ b/esp32c2/src/interrupt_core0/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("reg_clk_en", &format_args!("{}", self.reg_clk_en().bit()))
+            .field("reg_clk_en", &self.reg_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/coex_int_map.rs b/esp32c2/src/interrupt_core0/coex_int_map.rs
index 07428ae61c..853159eb43 100644
--- a/esp32c2/src/interrupt_core0/coex_int_map.rs
+++ b/esp32c2/src/interrupt_core0/coex_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COEX_INT_MAP")
-            .field(
-                "coex_int_map",
-                &format_args!("{}", self.coex_int_map().bits()),
-            )
+            .field("coex_int_map", &self.coex_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COEX_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs b/esp32c2/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs
index c8af3ba7c0..1cd0014fb2 100644
--- a/esp32c2/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs
+++ b/esp32c2/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP")
             .field(
                 "core_0_pif_pms_monitor_violate_size_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_violate_size_intr_map().bits()
-                ),
+                &self.core_0_pif_pms_monitor_violate_size_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/cpu_int_clear.rs b/esp32c2/src/interrupt_core0/cpu_int_clear.rs
index b9912b3374..cbc49231c0 100644
--- a/esp32c2/src/interrupt_core0/cpu_int_clear.rs
+++ b/esp32c2/src/interrupt_core0/cpu_int_clear.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_CLEAR")
-            .field(
-                "cpu_int_clear",
-                &format_args!("{}", self.cpu_int_clear().bits()),
-            )
+            .field("cpu_int_clear", &self.cpu_int_clear())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_CLEAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/cpu_int_eip_status.rs b/esp32c2/src/interrupt_core0/cpu_int_eip_status.rs
index b7ee1aaed5..1f188e92e8 100644
--- a/esp32c2/src/interrupt_core0/cpu_int_eip_status.rs
+++ b/esp32c2/src/interrupt_core0/cpu_int_eip_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_EIP_STATUS")
-            .field(
-                "cpu_int_eip_status",
-                &format_args!("{}", self.cpu_int_eip_status().bits()),
-            )
+            .field("cpu_int_eip_status", &self.cpu_int_eip_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_EIP_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_eip_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPU_INT_EIP_STATUS_SPEC;
 impl crate::RegisterSpec for CPU_INT_EIP_STATUS_SPEC {
diff --git a/esp32c2/src/interrupt_core0/cpu_int_enable.rs b/esp32c2/src/interrupt_core0/cpu_int_enable.rs
index f25a329e68..64ed8c3e2c 100644
--- a/esp32c2/src/interrupt_core0/cpu_int_enable.rs
+++ b/esp32c2/src/interrupt_core0/cpu_int_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_ENABLE")
-            .field(
-                "cpu_int_enable",
-                &format_args!("{}", self.cpu_int_enable().bits()),
-            )
+            .field("cpu_int_enable", &self.cpu_int_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/cpu_int_pri.rs b/esp32c2/src/interrupt_core0/cpu_int_pri.rs
index 1554f14e1a..cb451abfa9 100644
--- a/esp32c2/src/interrupt_core0/cpu_int_pri.rs
+++ b/esp32c2/src/interrupt_core0/cpu_int_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_PRI")
-            .field("map", &format_args!("{}", self.map().bits()))
+            .field("map", &self.map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/cpu_int_thresh.rs b/esp32c2/src/interrupt_core0/cpu_int_thresh.rs
index 779c525c03..914e7a8173 100644
--- a/esp32c2/src/interrupt_core0/cpu_int_thresh.rs
+++ b/esp32c2/src/interrupt_core0/cpu_int_thresh.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_THRESH")
-            .field(
-                "cpu_int_thresh",
-                &format_args!("{}", self.cpu_int_thresh().bits()),
-            )
+            .field("cpu_int_thresh", &self.cpu_int_thresh())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_THRESH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/cpu_int_type.rs b/esp32c2/src/interrupt_core0/cpu_int_type.rs
index 7582423a54..89be1b6343 100644
--- a/esp32c2/src/interrupt_core0/cpu_int_type.rs
+++ b/esp32c2/src/interrupt_core0/cpu_int_type.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_TYPE")
-            .field(
-                "cpu_int_type",
-                &format_args!("{}", self.cpu_int_type().bits()),
-            )
+            .field("cpu_int_type", &self.cpu_int_type())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_TYPE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs b/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
index b13234a40f..7f50bfcac5 100644
--- a/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
+++ b/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_0_MAP")
-            .field(
-                "cpu_intr_from_cpu_0_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_0_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_0_map", &self.cpu_intr_from_cpu_0_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_0_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs b/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
index bb2fe4df7d..112775d93f 100644
--- a/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
+++ b/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_1_MAP")
-            .field(
-                "cpu_intr_from_cpu_1_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_1_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_1_map", &self.cpu_intr_from_cpu_1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs b/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
index eb3d17f93c..dd39cdc18f 100644
--- a/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
+++ b/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_2_MAP")
-            .field(
-                "cpu_intr_from_cpu_2_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_2_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_2_map", &self.cpu_intr_from_cpu_2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs b/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
index 2cff0addd2..4aebdf5186 100644
--- a/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
+++ b/esp32c2/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_3_MAP")
-            .field(
-                "cpu_intr_from_cpu_3_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_3_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_3_map", &self.cpu_intr_from_cpu_3_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/dma_ch0_int_map.rs b/esp32c2/src/interrupt_core0/dma_ch0_int_map.rs
index 600de46455..3f9f5fce7c 100644
--- a/esp32c2/src/interrupt_core0/dma_ch0_int_map.rs
+++ b/esp32c2/src/interrupt_core0/dma_ch0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CH0_INT_MAP")
-            .field(
-                "dma_ch0_int_map",
-                &format_args!("{}", self.dma_ch0_int_map().bits()),
-            )
+            .field("dma_ch0_int_map", &self.dma_ch0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/ecc_int_map.rs b/esp32c2/src/interrupt_core0/ecc_int_map.rs
index ad81c02a15..4b89bb2c15 100644
--- a/esp32c2/src/interrupt_core0/ecc_int_map.rs
+++ b/esp32c2/src/interrupt_core0/ecc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_INT_MAP")
-            .field(
-                "ecc_int_map",
-                &format_args!("{}", self.ecc_int_map().bits()),
-            )
+            .field("ecc_int_map", &self.ecc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/efuse_int_map.rs b/esp32c2/src/interrupt_core0/efuse_int_map.rs
index e036e49ccf..f18c7f525c 100644
--- a/esp32c2/src/interrupt_core0/efuse_int_map.rs
+++ b/esp32c2/src/interrupt_core0/efuse_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EFUSE_INT_MAP")
-            .field(
-                "efuse_int_map",
-                &format_args!("{}", self.efuse_int_map().bits()),
-            )
+            .field("efuse_int_map", &self.efuse_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EFUSE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/gpio_interrupt_pro_map.rs b/esp32c2/src/interrupt_core0/gpio_interrupt_pro_map.rs
index a793a47730..022da9106e 100644
--- a/esp32c2/src/interrupt_core0/gpio_interrupt_pro_map.rs
+++ b/esp32c2/src/interrupt_core0/gpio_interrupt_pro_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INTERRUPT_PRO_MAP")
-            .field(
-                "gpio_interrupt_pro_map",
-                &format_args!("{}", self.gpio_interrupt_pro_map().bits()),
-            )
+            .field("gpio_interrupt_pro_map", &self.gpio_interrupt_pro_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_PRO_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs b/esp32c2/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
index a946ff6d89..76820b70f0 100644
--- a/esp32c2/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
+++ b/esp32c2/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("GPIO_INTERRUPT_PRO_NMI_MAP")
             .field(
                 "gpio_interrupt_pro_nmi_map",
-                &format_args!("{}", self.gpio_interrupt_pro_nmi_map().bits()),
+                &self.gpio_interrupt_pro_nmi_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_PRO_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/i2c_ext0_intr_map.rs b/esp32c2/src/interrupt_core0/i2c_ext0_intr_map.rs
index 7cb40c692a..812e727ab2 100644
--- a/esp32c2/src/interrupt_core0/i2c_ext0_intr_map.rs
+++ b/esp32c2/src/interrupt_core0/i2c_ext0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_EXT0_INTR_MAP")
-            .field(
-                "i2c_ext0_intr_map",
-                &format_args!("{}", self.i2c_ext0_intr_map().bits()),
-            )
+            .field("i2c_ext0_intr_map", &self.i2c_ext0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_EXT0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/i2c_mst_int_map.rs b/esp32c2/src/interrupt_core0/i2c_mst_int_map.rs
index e608f0ef47..5992265fae 100644
--- a/esp32c2/src/interrupt_core0/i2c_mst_int_map.rs
+++ b/esp32c2/src/interrupt_core0/i2c_mst_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_MST_INT_MAP")
-            .field(
-                "i2c_mst_int_map",
-                &format_args!("{}", self.i2c_mst_int_map().bits()),
-            )
+            .field("i2c_mst_int_map", &self.i2c_mst_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_MST_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/icache_preload_int_map.rs b/esp32c2/src/interrupt_core0/icache_preload_int_map.rs
index 844884b04f..c04c19c215 100644
--- a/esp32c2/src/interrupt_core0/icache_preload_int_map.rs
+++ b/esp32c2/src/interrupt_core0/icache_preload_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOAD_INT_MAP")
-            .field(
-                "icache_preload_int_map",
-                &format_args!("{}", self.icache_preload_int_map().bits()),
-            )
+            .field("icache_preload_int_map", &self.icache_preload_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOAD_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/icache_sync_int_map.rs b/esp32c2/src/interrupt_core0/icache_sync_int_map.rs
index c99ce80378..582e6a9b2d 100644
--- a/esp32c2/src/interrupt_core0/icache_sync_int_map.rs
+++ b/esp32c2/src/interrupt_core0/icache_sync_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_SYNC_INT_MAP")
-            .field(
-                "icache_sync_int_map",
-                &format_args!("{}", self.icache_sync_int_map().bits()),
-            )
+            .field("icache_sync_int_map", &self.icache_sync_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_SYNC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/interrupt_reg_date.rs b/esp32c2/src/interrupt_core0/interrupt_reg_date.rs
index 9e11a2f64a..98063951f8 100644
--- a/esp32c2/src/interrupt_core0/interrupt_reg_date.rs
+++ b/esp32c2/src/interrupt_core0/interrupt_reg_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT_REG_DATE")
-            .field(
-                "interrupt_reg_date",
-                &format_args!("{}", self.interrupt_reg_date().bits()),
-            )
+            .field("interrupt_reg_date", &self.interrupt_reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/intr_status_reg_0.rs b/esp32c2/src/interrupt_core0/intr_status_reg_0.rs
index cc8075d962..89b267af7a 100644
--- a/esp32c2/src/interrupt_core0/intr_status_reg_0.rs
+++ b/esp32c2/src/interrupt_core0/intr_status_reg_0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_0")
-            .field(
-                "intr_status_0",
-                &format_args!("{}", self.intr_status_0().bits()),
-            )
+            .field("intr_status_0", &self.intr_status_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_0_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_0_SPEC {
diff --git a/esp32c2/src/interrupt_core0/intr_status_reg_1.rs b/esp32c2/src/interrupt_core0/intr_status_reg_1.rs
index 2ba3ae0e12..1b93576572 100644
--- a/esp32c2/src/interrupt_core0/intr_status_reg_1.rs
+++ b/esp32c2/src/interrupt_core0/intr_status_reg_1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_1")
-            .field(
-                "intr_status_1",
-                &format_args!("{}", self.intr_status_1().bits()),
-            )
+            .field("intr_status_1", &self.intr_status_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_1_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_1_SPEC {
diff --git a/esp32c2/src/interrupt_core0/ledc_int_map.rs b/esp32c2/src/interrupt_core0/ledc_int_map.rs
index 26d6040909..e53152b43f 100644
--- a/esp32c2/src/interrupt_core0/ledc_int_map.rs
+++ b/esp32c2/src/interrupt_core0/ledc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEDC_INT_MAP")
-            .field(
-                "ledc_int_map",
-                &format_args!("{}", self.ledc_int_map().bits()),
-            )
+            .field("ledc_int_map", &self.ledc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEDC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/lp_timer_int_map.rs b/esp32c2/src/interrupt_core0/lp_timer_int_map.rs
index 8f1f649abd..36481a6435 100644
--- a/esp32c2/src/interrupt_core0/lp_timer_int_map.rs
+++ b/esp32c2/src/interrupt_core0/lp_timer_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_TIMER_INT_MAP")
-            .field(
-                "lp_timer_int_map",
-                &format_args!("{}", self.lp_timer_int_map().bits()),
-            )
+            .field("lp_timer_int_map", &self.lp_timer_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TIMER_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/mac_intr_map.rs b/esp32c2/src/interrupt_core0/mac_intr_map.rs
index 73c7ad4fdc..b202269ea7 100644
--- a/esp32c2/src/interrupt_core0/mac_intr_map.rs
+++ b/esp32c2/src/interrupt_core0/mac_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAC_INTR_MAP")
-            .field(
-                "wifi_mac_int_map",
-                &format_args!("{}", self.wifi_mac_int_map().bits()),
-            )
+            .field("wifi_mac_int_map", &self.wifi_mac_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/rtc_core_intr_map.rs b/esp32c2/src/interrupt_core0/rtc_core_intr_map.rs
index a2252312e5..bfec19d9a2 100644
--- a/esp32c2/src/interrupt_core0/rtc_core_intr_map.rs
+++ b/esp32c2/src/interrupt_core0/rtc_core_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_CORE_INTR_MAP")
-            .field(
-                "rtc_core_intr_map",
-                &format_args!("{}", self.rtc_core_intr_map().bits()),
-            )
+            .field("rtc_core_intr_map", &self.rtc_core_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_CORE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/sha_int_map.rs b/esp32c2/src/interrupt_core0/sha_int_map.rs
index bec312dfad..884c11be4c 100644
--- a/esp32c2/src/interrupt_core0/sha_int_map.rs
+++ b/esp32c2/src/interrupt_core0/sha_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA_INT_MAP")
-            .field(
-                "sha_int_map",
-                &format_args!("{}", self.sha_int_map().bits()),
-            )
+            .field("sha_int_map", &self.sha_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/spi_intr_1_map.rs b/esp32c2/src/interrupt_core0/spi_intr_1_map.rs
index 388845143b..31d3313f44 100644
--- a/esp32c2/src/interrupt_core0/spi_intr_1_map.rs
+++ b/esp32c2/src/interrupt_core0/spi_intr_1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_INTR_1_MAP")
-            .field(
-                "spi_intr_1_map",
-                &format_args!("{}", self.spi_intr_1_map().bits()),
-            )
+            .field("spi_intr_1_map", &self.spi_intr_1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_INTR_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/spi_intr_2_map.rs b/esp32c2/src/interrupt_core0/spi_intr_2_map.rs
index 9f0fcc045c..c733eed8af 100644
--- a/esp32c2/src/interrupt_core0/spi_intr_2_map.rs
+++ b/esp32c2/src/interrupt_core0/spi_intr_2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_INTR_2_MAP")
-            .field(
-                "spi_intr_2_map",
-                &format_args!("{}", self.spi_intr_2_map().bits()),
-            )
+            .field("spi_intr_2_map", &self.spi_intr_2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_INTR_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/spi_mem_reject_intr_map.rs b/esp32c2/src/interrupt_core0/spi_mem_reject_intr_map.rs
index be9fbf71dd..bc35269b86 100644
--- a/esp32c2/src/interrupt_core0/spi_mem_reject_intr_map.rs
+++ b/esp32c2/src/interrupt_core0/spi_mem_reject_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_MEM_REJECT_INTR_MAP")
-            .field(
-                "spi_mem_reject_intr_map",
-                &format_args!("{}", self.spi_mem_reject_intr_map().bits()),
-            )
+            .field("spi_mem_reject_intr_map", &self.spi_mem_reject_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_MEM_REJECT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/systimer_target0_int_map.rs b/esp32c2/src/interrupt_core0/systimer_target0_int_map.rs
index 9e52cc7430..dd5b8c5604 100644
--- a/esp32c2/src/interrupt_core0/systimer_target0_int_map.rs
+++ b/esp32c2/src/interrupt_core0/systimer_target0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_TARGET0_INT_MAP")
-            .field(
-                "systimer_target0_int_map",
-                &format_args!("{}", self.systimer_target0_int_map().bits()),
-            )
+            .field("systimer_target0_int_map", &self.systimer_target0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/systimer_target1_int_map.rs b/esp32c2/src/interrupt_core0/systimer_target1_int_map.rs
index aaa67a6f50..294cd4e3bc 100644
--- a/esp32c2/src/interrupt_core0/systimer_target1_int_map.rs
+++ b/esp32c2/src/interrupt_core0/systimer_target1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_TARGET1_INT_MAP")
-            .field(
-                "systimer_target1_int_map",
-                &format_args!("{}", self.systimer_target1_int_map().bits()),
-            )
+            .field("systimer_target1_int_map", &self.systimer_target1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/systimer_target2_int_map.rs b/esp32c2/src/interrupt_core0/systimer_target2_int_map.rs
index 6c86a6a675..e2aa73a015 100644
--- a/esp32c2/src/interrupt_core0/systimer_target2_int_map.rs
+++ b/esp32c2/src/interrupt_core0/systimer_target2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_TARGET2_INT_MAP")
-            .field(
-                "systimer_target2_int_map",
-                &format_args!("{}", self.systimer_target2_int_map().bits()),
-            )
+            .field("systimer_target2_int_map", &self.systimer_target2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/tg_t0_int_map.rs b/esp32c2/src/interrupt_core0/tg_t0_int_map.rs
index 0c6074d79a..e155dbcbc2 100644
--- a/esp32c2/src/interrupt_core0/tg_t0_int_map.rs
+++ b/esp32c2/src/interrupt_core0/tg_t0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG_T0_INT_MAP")
-            .field(
-                "tg_t0_int_map",
-                &format_args!("{}", self.tg_t0_int_map().bits()),
-            )
+            .field("tg_t0_int_map", &self.tg_t0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG_T0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/tg_wdt_int_map.rs b/esp32c2/src/interrupt_core0/tg_wdt_int_map.rs
index 0a6261fd39..28eef81d33 100644
--- a/esp32c2/src/interrupt_core0/tg_wdt_int_map.rs
+++ b/esp32c2/src/interrupt_core0/tg_wdt_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG_WDT_INT_MAP")
-            .field(
-                "tg_wdt_int_map",
-                &format_args!("{}", self.tg_wdt_int_map().bits()),
-            )
+            .field("tg_wdt_int_map", &self.tg_wdt_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG_WDT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/uart1_intr_map.rs b/esp32c2/src/interrupt_core0/uart1_intr_map.rs
index b19f64d061..992884832c 100644
--- a/esp32c2/src/interrupt_core0/uart1_intr_map.rs
+++ b/esp32c2/src/interrupt_core0/uart1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART1_INTR_MAP")
-            .field(
-                "uart1_intr_map",
-                &format_args!("{}", self.uart1_intr_map().bits()),
-            )
+            .field("uart1_intr_map", &self.uart1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/uart_intr_map.rs b/esp32c2/src/interrupt_core0/uart_intr_map.rs
index 911f21061d..6cdca8ddba 100644
--- a/esp32c2/src/interrupt_core0/uart_intr_map.rs
+++ b/esp32c2/src/interrupt_core0/uart_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART_INTR_MAP")
-            .field(
-                "uart_intr_map",
-                &format_args!("{}", self.uart_intr_map().bits()),
-            )
+            .field("uart_intr_map", &self.uart_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/wifi_bb_int_map.rs b/esp32c2/src/interrupt_core0/wifi_bb_int_map.rs
index 06252b881a..92956ddce1 100644
--- a/esp32c2/src/interrupt_core0/wifi_bb_int_map.rs
+++ b/esp32c2/src/interrupt_core0/wifi_bb_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_BB_INT_MAP")
-            .field(
-                "wifi_bb_int_map",
-                &format_args!("{}", self.wifi_bb_int_map().bits()),
-            )
+            .field("wifi_bb_int_map", &self.wifi_bb_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_BB_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/wifi_mac_nmi_map.rs b/esp32c2/src/interrupt_core0/wifi_mac_nmi_map.rs
index 1ff2b63854..72b9cb1f93 100644
--- a/esp32c2/src/interrupt_core0/wifi_mac_nmi_map.rs
+++ b/esp32c2/src/interrupt_core0/wifi_mac_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_MAC_NMI_MAP")
-            .field(
-                "wifi_mac_nmi_map",
-                &format_args!("{}", self.wifi_mac_nmi_map().bits()),
-            )
+            .field("wifi_mac_nmi_map", &self.wifi_mac_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_MAC_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/interrupt_core0/wifi_pwr_int_map.rs b/esp32c2/src/interrupt_core0/wifi_pwr_int_map.rs
index 431a3e74ee..84512de2ee 100644
--- a/esp32c2/src/interrupt_core0/wifi_pwr_int_map.rs
+++ b/esp32c2/src/interrupt_core0/wifi_pwr_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_PWR_INT_MAP")
-            .field(
-                "wifi_pwr_int_map",
-                &format_args!("{}", self.wifi_pwr_int_map().bits()),
-            )
+            .field("wifi_pwr_int_map", &self.wifi_pwr_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_PWR_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/io_mux/date.rs b/esp32c2/src/io_mux/date.rs
index 63f16ccacf..489c12dcb5 100644
--- a/esp32c2/src/io_mux/date.rs
+++ b/esp32c2/src/io_mux/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("reg_date", &format_args!("{}", self.reg_date().bits()))
+            .field("reg_date", &self.reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
diff --git a/esp32c2/src/io_mux/gpio.rs b/esp32c2/src/io_mux/gpio.rs
index ff75f38c3f..77004b071f 100644
--- a/esp32c2/src/io_mux/gpio.rs
+++ b/esp32c2/src/io_mux/gpio.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled."]
     #[inline(always)]
diff --git a/esp32c2/src/io_mux/pin_ctrl.rs b/esp32c2/src/io_mux/pin_ctrl.rs
index ecec0837d7..9628744bc2 100644
--- a/esp32c2/src/io_mux/pin_ctrl.rs
+++ b/esp32c2/src/io_mux/pin_ctrl.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN_CTRL")
-            .field("clk_out1", &format_args!("{}", self.clk_out1().bits()))
-            .field("clk_out2", &format_args!("{}", self.clk_out2().bits()))
-            .field("clk_out3", &format_args!("{}", self.clk_out3().bits()))
+            .field("clk_out1", &self.clk_out1())
+            .field("clk_out2", &self.clk_out2())
+            .field("clk_out3", &self.clk_out3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals."]
     #[inline(always)]
diff --git a/esp32c2/src/ledc/ch/conf0.rs b/esp32c2/src/ledc/ch/conf0.rs
index 5344aaf146..330ab9a6ac 100644
--- a/esp32c2/src/ledc/ch/conf0.rs
+++ b/esp32c2/src/ledc/ch/conf0.rs
@@ -57,20 +57,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("timer_sel", &format_args!("{}", self.timer_sel().bits()))
-            .field("sig_out_en", &format_args!("{}", self.sig_out_en().bit()))
-            .field("idle_lv", &format_args!("{}", self.idle_lv().bit()))
-            .field("ovf_num", &format_args!("{}", self.ovf_num().bits()))
-            .field("ovf_cnt_en", &format_args!("{}", self.ovf_cnt_en().bit()))
+            .field("timer_sel", &self.timer_sel())
+            .field("sig_out_en", &self.sig_out_en())
+            .field("idle_lv", &self.idle_lv())
+            .field("ovf_num", &self.ovf_num())
+            .field("ovf_cnt_en", &self.ovf_cnt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to select one of timers for channel %s. 0: select timer0; 1: select timer1; 2: select timer2; 3: select timer3"]
     #[inline(always)]
diff --git a/esp32c2/src/ledc/ch/conf1.rs b/esp32c2/src/ledc/ch/conf1.rs
index e413752336..4d1d093144 100644
--- a/esp32c2/src/ledc/ch/conf1.rs
+++ b/esp32c2/src/ledc/ch/conf1.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field("duty_scale", &format_args!("{}", self.duty_scale().bits()))
-            .field("duty_cycle", &format_args!("{}", self.duty_cycle().bits()))
-            .field("duty_num", &format_args!("{}", self.duty_num().bits()))
-            .field("duty_inc", &format_args!("{}", self.duty_inc().bit()))
-            .field("duty_start", &format_args!("{}", self.duty_start().bit()))
+            .field("duty_scale", &self.duty_scale())
+            .field("duty_cycle", &self.duty_cycle())
+            .field("duty_num", &self.duty_num())
+            .field("duty_inc", &self.duty_inc())
+            .field("duty_start", &self.duty_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the changing step scale of duty on channel %s."]
     #[inline(always)]
diff --git a/esp32c2/src/ledc/ch/duty.rs b/esp32c2/src/ledc/ch/duty.rs
index dd4f150d88..03e1bba638 100644
--- a/esp32c2/src/ledc/ch/duty.rs
+++ b/esp32c2/src/ledc/ch/duty.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DUTY")
-            .field("duty", &format_args!("{}", self.duty().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DUTY").field("duty", &self.duty()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/ledc/ch/duty_r.rs b/esp32c2/src/ledc/ch/duty_r.rs
index b1870f3014..28e94586f2 100644
--- a/esp32c2/src/ledc/ch/duty_r.rs
+++ b/esp32c2/src/ledc/ch/duty_r.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DUTY_R")
-            .field("duty_r", &format_args!("{}", self.duty_r().bits()))
+            .field("duty_r", &self.duty_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_R_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current duty cycle for channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`duty_r::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DUTY_R_SPEC;
 impl crate::RegisterSpec for DUTY_R_SPEC {
diff --git a/esp32c2/src/ledc/ch/hpoint.rs b/esp32c2/src/ledc/ch/hpoint.rs
index 559465bb7f..c2c53fa871 100644
--- a/esp32c2/src/ledc/ch/hpoint.rs
+++ b/esp32c2/src/ledc/ch/hpoint.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPOINT")
-            .field("hpoint", &format_args!("{}", self.hpoint().bits()))
+            .field("hpoint", &self.hpoint())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPOINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - The output value changes to high when the selected timers has reached the value specified by this register."]
     #[inline(always)]
diff --git a/esp32c2/src/ledc/conf.rs b/esp32c2/src/ledc/conf.rs
index 4a420f4ae7..9dfab9d08b 100644
--- a/esp32c2/src/ledc/conf.rs
+++ b/esp32c2/src/ledc/conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field(
-                "apb_clk_sel",
-                &format_args!("{}", self.apb_clk_sel().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("apb_clk_sel", &self.apb_clk_sel())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This bit is used to select clock source for the 4 timers . 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK"]
     #[inline(always)]
diff --git a/esp32c2/src/ledc/date.rs b/esp32c2/src/ledc/date.rs
index 84a68051c0..c8a656dfa7 100644
--- a/esp32c2/src/ledc/date.rs
+++ b/esp32c2/src/ledc/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("ledc_date", &format_args!("{}", self.ledc_date().bits()))
+            .field("ledc_date", &self.ledc_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This is the version control register."]
     #[inline(always)]
diff --git a/esp32c2/src/ledc/int_ena.rs b/esp32c2/src/ledc/int_ena.rs
index 2d0e239da2..431c4d2b83 100644
--- a/esp32c2/src/ledc/int_ena.rs
+++ b/esp32c2/src/ledc/int_ena.rs
@@ -145,49 +145,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the TIMER(0-3)_OVF interrupt."]
     #[doc = ""]
diff --git a/esp32c2/src/ledc/int_raw.rs b/esp32c2/src/ledc/int_raw.rs
index 1db2dbe164..407d180a98 100644
--- a/esp32c2/src/ledc/int_raw.rs
+++ b/esp32c2/src/ledc/int_raw.rs
@@ -145,49 +145,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Triggered when the timer(0-3) has reached its maximum counter value."]
     #[doc = ""]
diff --git a/esp32c2/src/ledc/int_st.rs b/esp32c2/src/ledc/int_st.rs
index 500df0ce01..757272798e 100644
--- a/esp32c2/src/ledc/int_st.rs
+++ b/esp32c2/src/ledc/int_st.rs
@@ -137,49 +137,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c2/src/ledc/timer/conf.rs b/esp32c2/src/ledc/timer/conf.rs
index 20def84693..d770931c62 100644
--- a/esp32c2/src/ledc/timer/conf.rs
+++ b/esp32c2/src/ledc/timer/conf.rs
@@ -55,20 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("duty_res", &format_args!("{}", self.duty_res().bits()))
-            .field("clk_div", &format_args!("{}", self.clk_div().bits()))
-            .field("pause", &format_args!("{}", self.pause().bit()))
-            .field("rst", &format_args!("{}", self.rst().bit()))
-            .field("tick_sel", &format_args!("{}", self.tick_sel().bit()))
+            .field("duty_res", &self.duty_res())
+            .field("clk_div", &self.clk_div())
+            .field("pause", &self.pause())
+            .field("rst", &self.rst())
+            .field("tick_sel", &self.tick_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - This register is used to control the range of the counter in timer %s."]
     #[inline(always)]
diff --git a/esp32c2/src/ledc/timer/value.rs b/esp32c2/src/ledc/timer/value.rs
index ee3ddb9c1b..598dc71136 100644
--- a/esp32c2/src/ledc/timer/value.rs
+++ b/esp32c2/src/ledc/timer/value.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("VALUE")
-            .field("cnt", &format_args!("{}", self.cnt().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("VALUE").field("cnt", &self.cnt()).finish()
     }
 }
 #[doc = "Timer 0 current counter value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c2/src/lib.rs b/esp32c2/src/lib.rs
index b28f39ba47..0e3bc4ec96 100644
--- a/esp32c2/src/lib.rs
+++ b/esp32c2/src/lib.rs
@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32-C2 microcontrollers (generated using svd2rust v0.33.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32-C2 microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
diff --git a/esp32c2/src/modem_clkrst/ble_timer_clk_conf.rs b/esp32c2/src/modem_clkrst/ble_timer_clk_conf.rs
index 66e6a1e444..23678f1a14 100644
--- a/esp32c2/src/modem_clkrst/ble_timer_clk_conf.rs
+++ b/esp32c2/src/modem_clkrst/ble_timer_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLE_TIMER_CLK_CONF")
-            .field(
-                "bletimer_use_xtal",
-                &format_args!("{}", self.bletimer_use_xtal().bit()),
-            )
-            .field(
-                "bletimer_clk_is_active",
-                &format_args!("{}", self.bletimer_clk_is_active().bit()),
-            )
+            .field("bletimer_use_xtal", &self.bletimer_use_xtal())
+            .field("bletimer_clk_is_active", &self.bletimer_clk_is_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLE_TIMER_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ."]
     #[inline(always)]
diff --git a/esp32c2/src/modem_clkrst/clk_conf.rs b/esp32c2/src/modem_clkrst/clk_conf.rs
index 328dd10fd8..34526ba1a7 100644
--- a/esp32c2/src/modem_clkrst/clk_conf.rs
+++ b/esp32c2/src/modem_clkrst/clk_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ."]
     #[inline(always)]
diff --git a/esp32c2/src/modem_clkrst/coex_lp_clk_conf.rs b/esp32c2/src/modem_clkrst/coex_lp_clk_conf.rs
index 56f8b574a5..bbd4294700 100644
--- a/esp32c2/src/modem_clkrst/coex_lp_clk_conf.rs
+++ b/esp32c2/src/modem_clkrst/coex_lp_clk_conf.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COEX_LP_CLK_CONF")
-            .field(
-                "coex_lpclk_sel_rtc_slow",
-                &format_args!("{}", self.coex_lpclk_sel_rtc_slow().bit()),
-            )
-            .field(
-                "coex_lpclk_sel_8m",
-                &format_args!("{}", self.coex_lpclk_sel_8m().bit()),
-            )
-            .field(
-                "coex_lpclk_sel_xtal",
-                &format_args!("{}", self.coex_lpclk_sel_xtal().bit()),
-            )
-            .field(
-                "coex_lpclk_sel_xtal32k",
-                &format_args!("{}", self.coex_lpclk_sel_xtal32k().bit()),
-            )
-            .field(
-                "coex_lpclk_div_num",
-                &format_args!("{}", self.coex_lpclk_div_num().bits()),
-            )
+            .field("coex_lpclk_sel_rtc_slow", &self.coex_lpclk_sel_rtc_slow())
+            .field("coex_lpclk_sel_8m", &self.coex_lpclk_sel_8m())
+            .field("coex_lpclk_sel_xtal", &self.coex_lpclk_sel_xtal())
+            .field("coex_lpclk_sel_xtal32k", &self.coex_lpclk_sel_xtal32k())
+            .field("coex_lpclk_div_num", &self.coex_lpclk_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COEX_LP_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ."]
     #[inline(always)]
diff --git a/esp32c2/src/modem_clkrst/date.rs b/esp32c2/src/modem_clkrst/date.rs
index 46f7e7e83a..100a920b3a 100644
--- a/esp32c2/src/modem_clkrst/date.rs
+++ b/esp32c2/src/modem_clkrst/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/modem_clkrst/etm_clk_conf.rs b/esp32c2/src/modem_clkrst/etm_clk_conf.rs
index 19921b7d29..89fb4a7e75 100644
--- a/esp32c2/src/modem_clkrst/etm_clk_conf.rs
+++ b/esp32c2/src/modem_clkrst/etm_clk_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_CLK_CONF")
-            .field("etm_clk_sel", &format_args!("{}", self.etm_clk_sel().bit()))
-            .field(
-                "etm_clk_active",
-                &format_args!("{}", self.etm_clk_active().bit()),
-            )
+            .field("etm_clk_sel", &self.etm_clk_sel())
+            .field("etm_clk_active", &self.etm_clk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ."]
     #[inline(always)]
diff --git a/esp32c2/src/modem_clkrst/modem_lp_timer_conf.rs b/esp32c2/src/modem_clkrst/modem_lp_timer_conf.rs
index bc20bd275c..8245990ba3 100644
--- a/esp32c2/src/modem_clkrst/modem_lp_timer_conf.rs
+++ b/esp32c2/src/modem_clkrst/modem_lp_timer_conf.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODEM_LP_TIMER_CONF")
-            .field(
-                "lp_timer_sel_rtc_slow",
-                &format_args!("{}", self.lp_timer_sel_rtc_slow().bit()),
-            )
-            .field(
-                "lp_timer_sel_8m",
-                &format_args!("{}", self.lp_timer_sel_8m().bit()),
-            )
-            .field(
-                "lp_timer_sel_xtal",
-                &format_args!("{}", self.lp_timer_sel_xtal().bit()),
-            )
-            .field(
-                "lp_timer_sel_xtal32k",
-                &format_args!("{}", self.lp_timer_sel_xtal32k().bit()),
-            )
-            .field(
-                "lp_timer_clk_div_num",
-                &format_args!("{}", self.lp_timer_clk_div_num().bits()),
-            )
+            .field("lp_timer_sel_rtc_slow", &self.lp_timer_sel_rtc_slow())
+            .field("lp_timer_sel_8m", &self.lp_timer_sel_8m())
+            .field("lp_timer_sel_xtal", &self.lp_timer_sel_xtal())
+            .field("lp_timer_sel_xtal32k", &self.lp_timer_sel_xtal32k())
+            .field("lp_timer_clk_div_num", &self.lp_timer_clk_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODEM_LP_TIMER_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ."]
     #[inline(always)]
diff --git a/esp32c2/src/rng/data.rs b/esp32c2/src/rng/data.rs
index 016046274d..4d812a63aa 100644
--- a/esp32c2/src/rng/data.rs
+++ b/esp32c2/src/rng/data.rs
@@ -6,12 +6,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Random number data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DATA_SPEC;
 impl crate::RegisterSpec for DATA_SPEC {
diff --git a/esp32c2/src/rtc_cntl/ana_conf.rs b/esp32c2/src/rtc_cntl/ana_conf.rs
index c145c7a63b..1d81e5e0a7 100644
--- a/esp32c2/src/rtc_cntl/ana_conf.rs
+++ b/esp32c2/src/rtc_cntl/ana_conf.rs
@@ -98,46 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ANA_CONF")
-            .field(
-                "i2c_reset_por_force_pd",
-                &format_args!("{}", self.i2c_reset_por_force_pd().bit()),
-            )
-            .field(
-                "i2c_reset_por_force_pu",
-                &format_args!("{}", self.i2c_reset_por_force_pu().bit()),
-            )
-            .field("sar_i2c_pu", &format_args!("{}", self.sar_i2c_pu().bit()))
-            .field(
-                "bbpll_cal_slp_start",
-                &format_args!("{}", self.bbpll_cal_slp_start().bit()),
-            )
-            .field("txrf_i2c_pu", &format_args!("{}", self.txrf_i2c_pu().bit()))
-            .field(
-                "rfrx_pbus_pu",
-                &format_args!("{}", self.rfrx_pbus_pu().bit()),
-            )
-            .field(
-                "ckgen_i2c_pu",
-                &format_args!("{}", self.ckgen_i2c_pu().bit()),
-            )
-            .field("pll_i2c_pu", &format_args!("{}", self.pll_i2c_pu().bit()))
-            .field(
-                "plla_force_pd",
-                &format_args!("{}", self.plla_force_pd().bit()),
-            )
-            .field(
-                "plla_force_pu",
-                &format_args!("{}", self.plla_force_pu().bit()),
-            )
+            .field("i2c_reset_por_force_pd", &self.i2c_reset_por_force_pd())
+            .field("i2c_reset_por_force_pu", &self.i2c_reset_por_force_pu())
+            .field("sar_i2c_pu", &self.sar_i2c_pu())
+            .field("bbpll_cal_slp_start", &self.bbpll_cal_slp_start())
+            .field("txrf_i2c_pu", &self.txrf_i2c_pu())
+            .field("rfrx_pbus_pu", &self.rfrx_pbus_pu())
+            .field("ckgen_i2c_pu", &self.ckgen_i2c_pu())
+            .field("pll_i2c_pu", &self.pll_i2c_pu())
+            .field("plla_force_pd", &self.plla_force_pd())
+            .field("plla_force_pu", &self.plla_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ANA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/bias_conf.rs b/esp32c2/src/rtc_cntl/bias_conf.rs
index 524aeccbd3..271dcb8616 100644
--- a/esp32c2/src/rtc_cntl/bias_conf.rs
+++ b/esp32c2/src/rtc_cntl/bias_conf.rs
@@ -125,67 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BIAS_CONF")
-            .field(
-                "dg_vdd_drv_b_slp",
-                &format_args!("{}", self.dg_vdd_drv_b_slp().bits()),
-            )
-            .field(
-                "dg_vdd_drv_b_slp_en",
-                &format_args!("{}", self.dg_vdd_drv_b_slp_en().bit()),
-            )
-            .field(
-                "bias_buf_idle",
-                &format_args!("{}", self.bias_buf_idle().bit()),
-            )
-            .field(
-                "bias_buf_wake",
-                &format_args!("{}", self.bias_buf_wake().bit()),
-            )
-            .field(
-                "bias_buf_deep_slp",
-                &format_args!("{}", self.bias_buf_deep_slp().bit()),
-            )
-            .field(
-                "bias_buf_monitor",
-                &format_args!("{}", self.bias_buf_monitor().bit()),
-            )
-            .field(
-                "pd_cur_deep_slp",
-                &format_args!("{}", self.pd_cur_deep_slp().bit()),
-            )
-            .field(
-                "pd_cur_monitor",
-                &format_args!("{}", self.pd_cur_monitor().bit()),
-            )
-            .field(
-                "bias_sleep_deep_slp",
-                &format_args!("{}", self.bias_sleep_deep_slp().bit()),
-            )
-            .field(
-                "bias_sleep_monitor",
-                &format_args!("{}", self.bias_sleep_monitor().bit()),
-            )
-            .field(
-                "dbg_atten_deep_slp",
-                &format_args!("{}", self.dbg_atten_deep_slp().bits()),
-            )
-            .field(
-                "dbg_atten_monitor",
-                &format_args!("{}", self.dbg_atten_monitor().bits()),
-            )
-            .field(
-                "dbg_atten_active",
-                &format_args!("{}", self.dbg_atten_active().bits()),
-            )
+            .field("dg_vdd_drv_b_slp", &self.dg_vdd_drv_b_slp())
+            .field("dg_vdd_drv_b_slp_en", &self.dg_vdd_drv_b_slp_en())
+            .field("bias_buf_idle", &self.bias_buf_idle())
+            .field("bias_buf_wake", &self.bias_buf_wake())
+            .field("bias_buf_deep_slp", &self.bias_buf_deep_slp())
+            .field("bias_buf_monitor", &self.bias_buf_monitor())
+            .field("pd_cur_deep_slp", &self.pd_cur_deep_slp())
+            .field("pd_cur_monitor", &self.pd_cur_monitor())
+            .field("bias_sleep_deep_slp", &self.bias_sleep_deep_slp())
+            .field("bias_sleep_monitor", &self.bias_sleep_monitor())
+            .field("dbg_atten_deep_slp", &self.dbg_atten_deep_slp())
+            .field("dbg_atten_monitor", &self.dbg_atten_monitor())
+            .field("dbg_atten_active", &self.dbg_atten_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BIAS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/brown_out.rs b/esp32c2/src/rtc_cntl/brown_out.rs
index 3aeeba3200..ce012e4c87 100644
--- a/esp32c2/src/rtc_cntl/brown_out.rs
+++ b/esp32c2/src/rtc_cntl/brown_out.rs
@@ -98,52 +98,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BROWN_OUT")
-            .field(
-                "brown_out_int_wait",
-                &format_args!("{}", self.brown_out_int_wait().bits()),
-            )
+            .field("brown_out_int_wait", &self.brown_out_int_wait())
             .field(
                 "brown_out_close_flash_ena",
-                &format_args!("{}", self.brown_out_close_flash_ena().bit()),
-            )
-            .field(
-                "brown_out_pd_rf_ena",
-                &format_args!("{}", self.brown_out_pd_rf_ena().bit()),
-            )
-            .field(
-                "brown_out_rst_wait",
-                &format_args!("{}", self.brown_out_rst_wait().bits()),
-            )
-            .field(
-                "brown_out_rst_ena",
-                &format_args!("{}", self.brown_out_rst_ena().bit()),
-            )
-            .field(
-                "brown_out_rst_sel",
-                &format_args!("{}", self.brown_out_rst_sel().bit()),
+                &self.brown_out_close_flash_ena(),
             )
-            .field(
-                "brown_out_ana_rst_en",
-                &format_args!("{}", self.brown_out_ana_rst_en().bit()),
-            )
-            .field(
-                "brown_out_cnt_clr",
-                &format_args!("{}", self.brown_out_cnt_clr().bit()),
-            )
-            .field(
-                "brown_out_ena",
-                &format_args!("{}", self.brown_out_ena().bit()),
-            )
-            .field("det", &format_args!("{}", self.det().bit()))
+            .field("brown_out_pd_rf_ena", &self.brown_out_pd_rf_ena())
+            .field("brown_out_rst_wait", &self.brown_out_rst_wait())
+            .field("brown_out_rst_ena", &self.brown_out_rst_ena())
+            .field("brown_out_rst_sel", &self.brown_out_rst_sel())
+            .field("brown_out_ana_rst_en", &self.brown_out_ana_rst_en())
+            .field("brown_out_cnt_clr", &self.brown_out_cnt_clr())
+            .field("brown_out_ena", &self.brown_out_ena())
+            .field("det", &self.det())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BROWN_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 4:13 - brown out interrupt wait cycles"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/clk_conf.rs b/esp32c2/src/rtc_cntl/clk_conf.rs
index 294ee79426..2dabbd5823 100644
--- a/esp32c2/src/rtc_cntl/clk_conf.rs
+++ b/esp32c2/src/rtc_cntl/clk_conf.rs
@@ -179,82 +179,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field(
-                "efuse_clk_force_gating",
-                &format_args!("{}", self.efuse_clk_force_gating().bit()),
-            )
-            .field(
-                "efuse_clk_force_nogating",
-                &format_args!("{}", self.efuse_clk_force_nogating().bit()),
-            )
-            .field(
-                "ck8m_div_sel_vld",
-                &format_args!("{}", self.ck8m_div_sel_vld().bit()),
-            )
-            .field("ck8m_div", &format_args!("{}", self.ck8m_div().bits()))
-            .field("enb_ck8m", &format_args!("{}", self.enb_ck8m().bit()))
-            .field(
-                "enb_ck8m_div",
-                &format_args!("{}", self.enb_ck8m_div().bit()),
-            )
-            .field(
-                "dig_xtal32k_en",
-                &format_args!("{}", self.dig_xtal32k_en().bit()),
-            )
-            .field(
-                "dig_clk8m_d256_en",
-                &format_args!("{}", self.dig_clk8m_d256_en().bit()),
-            )
-            .field(
-                "dig_clk8m_en",
-                &format_args!("{}", self.dig_clk8m_en().bit()),
-            )
-            .field(
-                "ck8m_div_sel",
-                &format_args!("{}", self.ck8m_div_sel().bits()),
-            )
-            .field(
-                "xtal_force_nogating",
-                &format_args!("{}", self.xtal_force_nogating().bit()),
-            )
-            .field(
-                "ck8m_force_nogating",
-                &format_args!("{}", self.ck8m_force_nogating().bit()),
-            )
-            .field("ck8m_dfreq", &format_args!("{}", self.ck8m_dfreq().bits()))
-            .field(
-                "ck8m_force_pd",
-                &format_args!("{}", self.ck8m_force_pd().bit()),
-            )
-            .field(
-                "ck8m_force_pu",
-                &format_args!("{}", self.ck8m_force_pu().bit()),
-            )
-            .field(
-                "xtal_global_force_gating",
-                &format_args!("{}", self.xtal_global_force_gating().bit()),
-            )
+            .field("efuse_clk_force_gating", &self.efuse_clk_force_gating())
+            .field("efuse_clk_force_nogating", &self.efuse_clk_force_nogating())
+            .field("ck8m_div_sel_vld", &self.ck8m_div_sel_vld())
+            .field("ck8m_div", &self.ck8m_div())
+            .field("enb_ck8m", &self.enb_ck8m())
+            .field("enb_ck8m_div", &self.enb_ck8m_div())
+            .field("dig_xtal32k_en", &self.dig_xtal32k_en())
+            .field("dig_clk8m_d256_en", &self.dig_clk8m_d256_en())
+            .field("dig_clk8m_en", &self.dig_clk8m_en())
+            .field("ck8m_div_sel", &self.ck8m_div_sel())
+            .field("xtal_force_nogating", &self.xtal_force_nogating())
+            .field("ck8m_force_nogating", &self.ck8m_force_nogating())
+            .field("ck8m_dfreq", &self.ck8m_dfreq())
+            .field("ck8m_force_pd", &self.ck8m_force_pd())
+            .field("ck8m_force_pu", &self.ck8m_force_pu())
+            .field("xtal_global_force_gating", &self.xtal_global_force_gating())
             .field(
                 "xtal_global_force_nogating",
-                &format_args!("{}", self.xtal_global_force_nogating().bit()),
-            )
-            .field(
-                "fast_clk_rtc_sel",
-                &format_args!("{}", self.fast_clk_rtc_sel().bit()),
-            )
-            .field(
-                "ana_clk_rtc_sel",
-                &format_args!("{}", self.ana_clk_rtc_sel().bits()),
+                &self.xtal_global_force_nogating(),
             )
+            .field("fast_clk_rtc_sel", &self.fast_clk_rtc_sel())
+            .field("ana_clk_rtc_sel", &self.ana_clk_rtc_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/cntl_date.rs b/esp32c2/src/rtc_cntl/cntl_date.rs
index 1f933aba3c..4147369671 100644
--- a/esp32c2/src/rtc_cntl/cntl_date.rs
+++ b/esp32c2/src/rtc_cntl/cntl_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CNTL_DATE")
-            .field("cntl_date", &format_args!("{}", self.cntl_date().bits()))
+            .field("cntl_date", &self.cntl_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CNTL_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/cntl_dbg_map.rs b/esp32c2/src/rtc_cntl/cntl_dbg_map.rs
index aa883079d5..b8d2805832 100644
--- a/esp32c2/src/rtc_cntl/cntl_dbg_map.rs
+++ b/esp32c2/src/rtc_cntl/cntl_dbg_map.rs
@@ -116,63 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CNTL_DBG_MAP")
-            .field(
-                "gpio_pin5_mux_sel",
-                &format_args!("{}", self.gpio_pin5_mux_sel().bit()),
-            )
-            .field(
-                "gpio_pin4_mux_sel",
-                &format_args!("{}", self.gpio_pin4_mux_sel().bit()),
-            )
-            .field(
-                "gpio_pin3_mux_sel",
-                &format_args!("{}", self.gpio_pin3_mux_sel().bit()),
-            )
-            .field(
-                "gpio_pin2_mux_sel",
-                &format_args!("{}", self.gpio_pin2_mux_sel().bit()),
-            )
-            .field(
-                "gpio_pin1_mux_sel",
-                &format_args!("{}", self.gpio_pin1_mux_sel().bit()),
-            )
-            .field(
-                "gpio_pin0_mux_sel",
-                &format_args!("{}", self.gpio_pin0_mux_sel().bit()),
-            )
-            .field(
-                "gpio_pin5_fun_sel",
-                &format_args!("{}", self.gpio_pin5_fun_sel().bits()),
-            )
-            .field(
-                "gpio_pin4_fun_sel",
-                &format_args!("{}", self.gpio_pin4_fun_sel().bits()),
-            )
-            .field(
-                "gpio_pin3_fun_sel",
-                &format_args!("{}", self.gpio_pin3_fun_sel().bits()),
-            )
-            .field(
-                "gpio_pin2_fun_sel",
-                &format_args!("{}", self.gpio_pin2_fun_sel().bits()),
-            )
-            .field(
-                "gpio_pin1_fun_sel",
-                &format_args!("{}", self.gpio_pin1_fun_sel().bits()),
-            )
-            .field(
-                "gpio_pin0_fun_sel",
-                &format_args!("{}", self.gpio_pin0_fun_sel().bits()),
-            )
+            .field("gpio_pin5_mux_sel", &self.gpio_pin5_mux_sel())
+            .field("gpio_pin4_mux_sel", &self.gpio_pin4_mux_sel())
+            .field("gpio_pin3_mux_sel", &self.gpio_pin3_mux_sel())
+            .field("gpio_pin2_mux_sel", &self.gpio_pin2_mux_sel())
+            .field("gpio_pin1_mux_sel", &self.gpio_pin1_mux_sel())
+            .field("gpio_pin0_mux_sel", &self.gpio_pin0_mux_sel())
+            .field("gpio_pin5_fun_sel", &self.gpio_pin5_fun_sel())
+            .field("gpio_pin4_fun_sel", &self.gpio_pin4_fun_sel())
+            .field("gpio_pin3_fun_sel", &self.gpio_pin3_fun_sel())
+            .field("gpio_pin2_fun_sel", &self.gpio_pin2_fun_sel())
+            .field("gpio_pin1_fun_sel", &self.gpio_pin1_fun_sel())
+            .field("gpio_pin0_fun_sel", &self.gpio_pin0_fun_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CNTL_DBG_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/cntl_dbg_sar_sel.rs b/esp32c2/src/rtc_cntl/cntl_dbg_sar_sel.rs
index 2de509eb82..5d4ce05033 100644
--- a/esp32c2/src/rtc_cntl/cntl_dbg_sar_sel.rs
+++ b/esp32c2/src/rtc_cntl/cntl_dbg_sar_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CNTL_DBG_SAR_SEL")
-            .field(
-                "sar_debug_sel",
-                &format_args!("{}", self.sar_debug_sel().bits()),
-            )
+            .field("sar_debug_sel", &self.sar_debug_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CNTL_DBG_SAR_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 27:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/cntl_dbg_sel.rs b/esp32c2/src/rtc_cntl/cntl_dbg_sel.rs
index a235ba4852..8bd9c2a812 100644
--- a/esp32c2/src/rtc_cntl/cntl_dbg_sel.rs
+++ b/esp32c2/src/rtc_cntl/cntl_dbg_sel.rs
@@ -71,28 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CNTL_DBG_SEL")
-            .field(
-                "debug_12m_no_gating",
-                &format_args!("{}", self.debug_12m_no_gating().bit()),
-            )
-            .field(
-                "debug_bit_sel",
-                &format_args!("{}", self.debug_bit_sel().bits()),
-            )
-            .field("debug_sel0", &format_args!("{}", self.debug_sel0().bits()))
-            .field("debug_sel1", &format_args!("{}", self.debug_sel1().bits()))
-            .field("debug_sel2", &format_args!("{}", self.debug_sel2().bits()))
-            .field("debug_sel3", &format_args!("{}", self.debug_sel3().bits()))
-            .field("debug_sel4", &format_args!("{}", self.debug_sel4().bits()))
+            .field("debug_12m_no_gating", &self.debug_12m_no_gating())
+            .field("debug_bit_sel", &self.debug_bit_sel())
+            .field("debug_sel0", &self.debug_sel0())
+            .field("debug_sel1", &self.debug_sel1())
+            .field("debug_sel2", &self.debug_sel2())
+            .field("debug_sel3", &self.debug_sel3())
+            .field("debug_sel4", &self.debug_sel4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CNTL_DBG_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/cntl_gpio_wakeup.rs b/esp32c2/src/rtc_cntl/cntl_gpio_wakeup.rs
index 2ce03c0fd6..7ae5770980 100644
--- a/esp32c2/src/rtc_cntl/cntl_gpio_wakeup.rs
+++ b/esp32c2/src/rtc_cntl/cntl_gpio_wakeup.rs
@@ -143,75 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CNTL_GPIO_WAKEUP")
-            .field(
-                "gpio_wakeup_status",
-                &format_args!("{}", self.gpio_wakeup_status().bits()),
-            )
-            .field(
-                "gpio_wakeup_status_clr",
-                &format_args!("{}", self.gpio_wakeup_status_clr().bit()),
-            )
-            .field(
-                "gpio_pin_clk_gate",
-                &format_args!("{}", self.gpio_pin_clk_gate().bit()),
-            )
-            .field(
-                "gpio_pin5_int_type",
-                &format_args!("{}", self.gpio_pin5_int_type().bits()),
-            )
-            .field(
-                "gpio_pin4_int_type",
-                &format_args!("{}", self.gpio_pin4_int_type().bits()),
-            )
-            .field(
-                "gpio_pin3_int_type",
-                &format_args!("{}", self.gpio_pin3_int_type().bits()),
-            )
-            .field(
-                "gpio_pin2_int_type",
-                &format_args!("{}", self.gpio_pin2_int_type().bits()),
-            )
-            .field(
-                "gpio_pin1_int_type",
-                &format_args!("{}", self.gpio_pin1_int_type().bits()),
-            )
-            .field(
-                "gpio_pin0_int_type",
-                &format_args!("{}", self.gpio_pin0_int_type().bits()),
-            )
-            .field(
-                "gpio_pin5_wakeup_enable",
-                &format_args!("{}", self.gpio_pin5_wakeup_enable().bit()),
-            )
-            .field(
-                "gpio_pin4_wakeup_enable",
-                &format_args!("{}", self.gpio_pin4_wakeup_enable().bit()),
-            )
-            .field(
-                "gpio_pin3_wakeup_enable",
-                &format_args!("{}", self.gpio_pin3_wakeup_enable().bit()),
-            )
-            .field(
-                "gpio_pin2_wakeup_enable",
-                &format_args!("{}", self.gpio_pin2_wakeup_enable().bit()),
-            )
-            .field(
-                "gpio_pin1_wakeup_enable",
-                &format_args!("{}", self.gpio_pin1_wakeup_enable().bit()),
-            )
-            .field(
-                "gpio_pin0_wakeup_enable",
-                &format_args!("{}", self.gpio_pin0_wakeup_enable().bit()),
-            )
+            .field("gpio_wakeup_status", &self.gpio_wakeup_status())
+            .field("gpio_wakeup_status_clr", &self.gpio_wakeup_status_clr())
+            .field("gpio_pin_clk_gate", &self.gpio_pin_clk_gate())
+            .field("gpio_pin5_int_type", &self.gpio_pin5_int_type())
+            .field("gpio_pin4_int_type", &self.gpio_pin4_int_type())
+            .field("gpio_pin3_int_type", &self.gpio_pin3_int_type())
+            .field("gpio_pin2_int_type", &self.gpio_pin2_int_type())
+            .field("gpio_pin1_int_type", &self.gpio_pin1_int_type())
+            .field("gpio_pin0_int_type", &self.gpio_pin0_int_type())
+            .field("gpio_pin5_wakeup_enable", &self.gpio_pin5_wakeup_enable())
+            .field("gpio_pin4_wakeup_enable", &self.gpio_pin4_wakeup_enable())
+            .field("gpio_pin3_wakeup_enable", &self.gpio_pin3_wakeup_enable())
+            .field("gpio_pin2_wakeup_enable", &self.gpio_pin2_wakeup_enable())
+            .field("gpio_pin1_wakeup_enable", &self.gpio_pin1_wakeup_enable())
+            .field("gpio_pin0_wakeup_enable", &self.gpio_pin0_wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CNTL_GPIO_WAKEUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/cntl_retention_ctrl.rs b/esp32c2/src/rtc_cntl/cntl_retention_ctrl.rs
index dc5eda97c3..361b8fcfd5 100644
--- a/esp32c2/src/rtc_cntl/cntl_retention_ctrl.rs
+++ b/esp32c2/src/rtc_cntl/cntl_retention_ctrl.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CNTL_RETENTION_CTRL")
-            .field(
-                "retention_clk_sel",
-                &format_args!("{}", self.retention_clk_sel().bit()),
-            )
-            .field(
-                "retention_done_wait",
-                &format_args!("{}", self.retention_done_wait().bits()),
-            )
-            .field(
-                "retention_clkoff_wait",
-                &format_args!("{}", self.retention_clkoff_wait().bits()),
-            )
-            .field(
-                "retention_en",
-                &format_args!("{}", self.retention_en().bit()),
-            )
-            .field(
-                "retention_wait",
-                &format_args!("{}", self.retention_wait().bits()),
-            )
+            .field("retention_clk_sel", &self.retention_clk_sel())
+            .field("retention_done_wait", &self.retention_done_wait())
+            .field("retention_clkoff_wait", &self.retention_clkoff_wait())
+            .field("retention_en", &self.retention_en())
+            .field("retention_wait", &self.retention_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CNTL_RETENTION_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/cntl_sensor_ctrl.rs b/esp32c2/src/rtc_cntl/cntl_sensor_ctrl.rs
index 74d075f587..2a4d7fe233 100644
--- a/esp32c2/src/rtc_cntl/cntl_sensor_ctrl.rs
+++ b/esp32c2/src/rtc_cntl/cntl_sensor_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CNTL_SENSOR_CTRL")
-            .field(
-                "sar2_pwdet_cct",
-                &format_args!("{}", self.sar2_pwdet_cct().bits()),
-            )
-            .field(
-                "force_xpd_sar",
-                &format_args!("{}", self.force_xpd_sar().bits()),
-            )
+            .field("sar2_pwdet_cct", &self.sar2_pwdet_cct())
+            .field("force_xpd_sar", &self.force_xpd_sar())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CNTL_SENSOR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 27:29 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/cpu_period_conf.rs b/esp32c2/src/rtc_cntl/cpu_period_conf.rs
index c4a8ecf332..75a58c920c 100644
--- a/esp32c2/src/rtc_cntl/cpu_period_conf.rs
+++ b/esp32c2/src/rtc_cntl/cpu_period_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERIOD_CONF")
-            .field("cpusel_conf", &format_args!("{}", self.cpusel_conf().bit()))
-            .field(
-                "cpuperiod_sel",
-                &format_args!("{}", self.cpuperiod_sel().bits()),
-            )
+            .field("cpusel_conf", &self.cpusel_conf())
+            .field("cpuperiod_sel", &self.cpuperiod_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERIOD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 29 - CPU sel option"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/diag0.rs b/esp32c2/src/rtc_cntl/diag0.rs
index 0f7a877e22..7f230165ad 100644
--- a/esp32c2/src/rtc_cntl/diag0.rs
+++ b/esp32c2/src/rtc_cntl/diag0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIAG0")
-            .field(
-                "low_power_diag1",
-                &format_args!("{}", self.low_power_diag1().bits()),
-            )
+            .field("low_power_diag1", &self.low_power_diag1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIAG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/dig_iso.rs b/esp32c2/src/rtc_cntl/dig_iso.rs
index c4a5449049..27cc29d3db 100644
--- a/esp32c2/src/rtc_cntl/dig_iso.rs
+++ b/esp32c2/src/rtc_cntl/dig_iso.rs
@@ -107,53 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIG_ISO")
-            .field("force_off", &format_args!("{}", self.force_off().bit()))
-            .field("force_on", &format_args!("{}", self.force_on().bit()))
-            .field(
-                "dg_pad_autohold",
-                &format_args!("{}", self.dg_pad_autohold().bit()),
-            )
-            .field(
-                "clr_dg_pad_autohold",
-                &format_args!("{}", self.clr_dg_pad_autohold().bit()),
-            )
-            .field(
-                "dg_pad_autohold_en",
-                &format_args!("{}", self.dg_pad_autohold_en().bit()),
-            )
-            .field(
-                "dg_pad_force_noiso",
-                &format_args!("{}", self.dg_pad_force_noiso().bit()),
-            )
-            .field(
-                "dg_pad_force_iso",
-                &format_args!("{}", self.dg_pad_force_iso().bit()),
-            )
-            .field(
-                "dg_pad_force_unhold",
-                &format_args!("{}", self.dg_pad_force_unhold().bit()),
-            )
-            .field(
-                "dg_pad_force_hold",
-                &format_args!("{}", self.dg_pad_force_hold().bit()),
-            )
-            .field(
-                "dg_wrap_force_iso",
-                &format_args!("{}", self.dg_wrap_force_iso().bit()),
-            )
-            .field(
-                "dg_wrap_force_noiso",
-                &format_args!("{}", self.dg_wrap_force_noiso().bit()),
-            )
+            .field("force_off", &self.force_off())
+            .field("force_on", &self.force_on())
+            .field("dg_pad_autohold", &self.dg_pad_autohold())
+            .field("clr_dg_pad_autohold", &self.clr_dg_pad_autohold())
+            .field("dg_pad_autohold_en", &self.dg_pad_autohold_en())
+            .field("dg_pad_force_noiso", &self.dg_pad_force_noiso())
+            .field("dg_pad_force_iso", &self.dg_pad_force_iso())
+            .field("dg_pad_force_unhold", &self.dg_pad_force_unhold())
+            .field("dg_pad_force_hold", &self.dg_pad_force_hold())
+            .field("dg_wrap_force_iso", &self.dg_wrap_force_iso())
+            .field("dg_wrap_force_noiso", &self.dg_wrap_force_noiso())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIG_ISO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/dig_pad_hold.rs b/esp32c2/src/rtc_cntl/dig_pad_hold.rs
index 35c0e4bcf6..60ee0ad4ff 100644
--- a/esp32c2/src/rtc_cntl/dig_pad_hold.rs
+++ b/esp32c2/src/rtc_cntl/dig_pad_hold.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIG_PAD_HOLD")
-            .field(
-                "dig_pad_hold",
-                &format_args!("{}", self.dig_pad_hold().bits()),
-            )
+            .field("dig_pad_hold", &self.dig_pad_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIG_PAD_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/dig_pwc.rs b/esp32c2/src/rtc_cntl/dig_pwc.rs
index bfb38a8602..51876f6599 100644
--- a/esp32c2/src/rtc_cntl/dig_pwc.rs
+++ b/esp32c2/src/rtc_cntl/dig_pwc.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIG_PWC")
-            .field(
-                "vdd_spi_pwr_drv",
-                &format_args!("{}", self.vdd_spi_pwr_drv().bits()),
-            )
-            .field(
-                "vdd_spi_pwr_force",
-                &format_args!("{}", self.vdd_spi_pwr_force().bit()),
-            )
-            .field(
-                "vdd_spi_pd_en",
-                &format_args!("{}", self.vdd_spi_pd_en().bit()),
-            )
-            .field(
-                "lslp_mem_force_pd",
-                &format_args!("{}", self.lslp_mem_force_pd().bit()),
-            )
-            .field(
-                "lslp_mem_force_pu",
-                &format_args!("{}", self.lslp_mem_force_pu().bit()),
-            )
-            .field(
-                "dg_wrap_force_pd",
-                &format_args!("{}", self.dg_wrap_force_pd().bit()),
-            )
-            .field(
-                "dg_wrap_force_pu",
-                &format_args!("{}", self.dg_wrap_force_pu().bit()),
-            )
-            .field(
-                "dg_wrap_pd_en",
-                &format_args!("{}", self.dg_wrap_pd_en().bit()),
-            )
+            .field("vdd_spi_pwr_drv", &self.vdd_spi_pwr_drv())
+            .field("vdd_spi_pwr_force", &self.vdd_spi_pwr_force())
+            .field("vdd_spi_pd_en", &self.vdd_spi_pd_en())
+            .field("lslp_mem_force_pd", &self.lslp_mem_force_pd())
+            .field("lslp_mem_force_pu", &self.lslp_mem_force_pu())
+            .field("dg_wrap_force_pd", &self.dg_wrap_force_pd())
+            .field("dg_wrap_force_pu", &self.dg_wrap_force_pu())
+            .field("dg_wrap_pd_en", &self.dg_wrap_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIG_PWC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/ext_wakeup_conf.rs b/esp32c2/src/rtc_cntl/ext_wakeup_conf.rs
index 6cb26b72b4..e1b9f06c60 100644
--- a/esp32c2/src/rtc_cntl/ext_wakeup_conf.rs
+++ b/esp32c2/src/rtc_cntl/ext_wakeup_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP_CONF")
-            .field(
-                "gpio_wakeup_filter",
-                &format_args!("{}", self.gpio_wakeup_filter().bit()),
-            )
+            .field("gpio_wakeup_filter", &self.gpio_wakeup_filter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - enable filter for gpio wakeup event"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/ext_xtl_conf.rs b/esp32c2/src/rtc_cntl/ext_xtl_conf.rs
index fb2f0f3f59..3330d399f5 100644
--- a/esp32c2/src/rtc_cntl/ext_xtl_conf.rs
+++ b/esp32c2/src/rtc_cntl/ext_xtl_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_XTL_CONF")
-            .field(
-                "xtl_ext_ctr_lv",
-                &format_args!("{}", self.xtl_ext_ctr_lv().bit()),
-            )
-            .field(
-                "xtl_ext_ctr_en",
-                &format_args!("{}", self.xtl_ext_ctr_en().bit()),
-            )
+            .field("xtl_ext_ctr_lv", &self.xtl_ext_ctr_lv())
+            .field("xtl_ext_ctr_en", &self.xtl_ext_ctr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_XTL_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - 0: power down XTAL at high level"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/fib_sel.rs b/esp32c2/src/rtc_cntl/fib_sel.rs
index f5c0f0a9c9..f8c4ff1809 100644
--- a/esp32c2/src/rtc_cntl/fib_sel.rs
+++ b/esp32c2/src/rtc_cntl/fib_sel.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIB_SEL")
-            .field("fib_sel", &format_args!("{}", self.fib_sel().bits()))
+            .field("fib_sel", &self.fib_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIB_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - select use analog fib signal"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/int_clr.rs b/esp32c2/src/rtc_cntl/int_clr.rs
index 2aa289bb61..f280dc863f 100644
--- a/esp32c2/src/rtc_cntl/int_clr.rs
+++ b/esp32c2/src/rtc_cntl/int_clr.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_CLR")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
-            .field("swd", &format_args!("{}", self.swd().bit()))
-            .field("bbpll_cal", &format_args!("{}", self.bbpll_cal().bit()))
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("wdt", &self.wdt())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("swd", &self.swd())
+            .field("bbpll_cal", &self.bbpll_cal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Clear sleep wakeup interrupt state"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/int_ena.rs b/esp32c2/src/rtc_cntl/int_ena.rs
index 6f93c3b6c9..abba236606 100644
--- a/esp32c2/src/rtc_cntl/int_ena.rs
+++ b/esp32c2/src/rtc_cntl/int_ena.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
-            .field("swd", &format_args!("{}", self.swd().bit()))
-            .field("bbpll_cal", &format_args!("{}", self.bbpll_cal().bit()))
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("wdt", &self.wdt())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("swd", &self.swd())
+            .field("bbpll_cal", &self.bbpll_cal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable sleep wakeup interrupt"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/int_ena_rtc_w1tc.rs b/esp32c2/src/rtc_cntl/int_ena_rtc_w1tc.rs
index f4d59e8601..58cf07c2a2 100644
--- a/esp32c2/src/rtc_cntl/int_ena_rtc_w1tc.rs
+++ b/esp32c2/src/rtc_cntl/int_ena_rtc_w1tc.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA_RTC_W1TC")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
-            .field("swd", &format_args!("{}", self.swd().bit()))
-            .field("bbpll_cal", &format_args!("{}", self.bbpll_cal().bit()))
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("wdt", &self.wdt())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("swd", &self.swd())
+            .field("bbpll_cal", &self.bbpll_cal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_RTC_W1TC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable sleep wakeup interrupt"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/int_ena_rtc_w1ts.rs b/esp32c2/src/rtc_cntl/int_ena_rtc_w1ts.rs
index d3da8c5f8b..d9b619c108 100644
--- a/esp32c2/src/rtc_cntl/int_ena_rtc_w1ts.rs
+++ b/esp32c2/src/rtc_cntl/int_ena_rtc_w1ts.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA_RTC_W1TS")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
-            .field("swd", &format_args!("{}", self.swd().bit()))
-            .field("bbpll_cal", &format_args!("{}", self.bbpll_cal().bit()))
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("wdt", &self.wdt())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("swd", &self.swd())
+            .field("bbpll_cal", &self.bbpll_cal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_RTC_W1TS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable sleep wakeup interrupt"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/int_raw.rs b/esp32c2/src/rtc_cntl/int_raw.rs
index c891330d75..facd121992 100644
--- a/esp32c2/src/rtc_cntl/int_raw.rs
+++ b/esp32c2/src/rtc_cntl/int_raw.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
-            .field("swd", &format_args!("{}", self.swd().bit()))
-            .field("bbpll_cal", &format_args!("{}", self.bbpll_cal().bit()))
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("wdt", &self.wdt())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("swd", &self.swd())
+            .field("bbpll_cal", &self.bbpll_cal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - sleep wakeup interrupt raw"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/int_st.rs b/esp32c2/src/rtc_cntl/int_st.rs
index 3e9f031cee..44dad66d7a 100644
--- a/esp32c2/src/rtc_cntl/int_st.rs
+++ b/esp32c2/src/rtc_cntl/int_st.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
-            .field("swd", &format_args!("{}", self.swd().bit()))
-            .field("bbpll_cal", &format_args!("{}", self.bbpll_cal().bit()))
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("wdt", &self.wdt())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("swd", &self.swd())
+            .field("bbpll_cal", &self.bbpll_cal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - sleep wakeup interrupt state"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/low_power_st.rs b/esp32c2/src/rtc_cntl/low_power_st.rs
index 1f6cc3406a..e2b35e5113 100644
--- a/esp32c2/src/rtc_cntl/low_power_st.rs
+++ b/esp32c2/src/rtc_cntl/low_power_st.rs
@@ -197,93 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOW_POWER_ST")
-            .field("xpd_dig", &format_args!("{}", self.xpd_dig().bit()))
-            .field(
-                "touch_state_start",
-                &format_args!("{}", self.touch_state_start().bit()),
-            )
-            .field(
-                "touch_state_switch",
-                &format_args!("{}", self.touch_state_switch().bit()),
-            )
-            .field(
-                "touch_state_slp",
-                &format_args!("{}", self.touch_state_slp().bit()),
-            )
-            .field(
-                "touch_state_done",
-                &format_args!("{}", self.touch_state_done().bit()),
-            )
-            .field(
-                "cocpu_state_start",
-                &format_args!("{}", self.cocpu_state_start().bit()),
-            )
-            .field(
-                "cocpu_state_switch",
-                &format_args!("{}", self.cocpu_state_switch().bit()),
-            )
-            .field(
-                "cocpu_state_slp",
-                &format_args!("{}", self.cocpu_state_slp().bit()),
-            )
-            .field(
-                "cocpu_state_done",
-                &format_args!("{}", self.cocpu_state_done().bit()),
-            )
-            .field(
-                "main_state_xtal_iso",
-                &format_args!("{}", self.main_state_xtal_iso().bit()),
-            )
-            .field(
-                "main_state_pll_on",
-                &format_args!("{}", self.main_state_pll_on().bit()),
-            )
-            .field(
-                "rdy_for_wakeup",
-                &format_args!("{}", self.rdy_for_wakeup().bit()),
-            )
-            .field(
-                "main_state_wait_end",
-                &format_args!("{}", self.main_state_wait_end().bit()),
-            )
-            .field(
-                "in_wakeup_state",
-                &format_args!("{}", self.in_wakeup_state().bit()),
-            )
-            .field(
-                "in_low_power_state",
-                &format_args!("{}", self.in_low_power_state().bit()),
-            )
-            .field(
-                "main_state_in_wait_8m",
-                &format_args!("{}", self.main_state_in_wait_8m().bit()),
-            )
-            .field(
-                "main_state_in_wait_pll",
-                &format_args!("{}", self.main_state_in_wait_pll().bit()),
-            )
-            .field(
-                "main_state_in_wait_xtl",
-                &format_args!("{}", self.main_state_in_wait_xtl().bit()),
-            )
-            .field(
-                "main_state_in_slp",
-                &format_args!("{}", self.main_state_in_slp().bit()),
-            )
-            .field(
-                "main_state_in_idle",
-                &format_args!("{}", self.main_state_in_idle().bit()),
-            )
-            .field("main_state", &format_args!("{}", self.main_state().bits()))
+            .field("xpd_dig", &self.xpd_dig())
+            .field("touch_state_start", &self.touch_state_start())
+            .field("touch_state_switch", &self.touch_state_switch())
+            .field("touch_state_slp", &self.touch_state_slp())
+            .field("touch_state_done", &self.touch_state_done())
+            .field("cocpu_state_start", &self.cocpu_state_start())
+            .field("cocpu_state_switch", &self.cocpu_state_switch())
+            .field("cocpu_state_slp", &self.cocpu_state_slp())
+            .field("cocpu_state_done", &self.cocpu_state_done())
+            .field("main_state_xtal_iso", &self.main_state_xtal_iso())
+            .field("main_state_pll_on", &self.main_state_pll_on())
+            .field("rdy_for_wakeup", &self.rdy_for_wakeup())
+            .field("main_state_wait_end", &self.main_state_wait_end())
+            .field("in_wakeup_state", &self.in_wakeup_state())
+            .field("in_low_power_state", &self.in_low_power_state())
+            .field("main_state_in_wait_8m", &self.main_state_in_wait_8m())
+            .field("main_state_in_wait_pll", &self.main_state_in_wait_pll())
+            .field("main_state_in_wait_xtl", &self.main_state_in_wait_xtl())
+            .field("main_state_in_slp", &self.main_state_in_slp())
+            .field("main_state_in_idle", &self.main_state_in_idle())
+            .field("main_state", &self.main_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOW_POWER_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - digital wrap power down"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/option1.rs b/esp32c2/src/rtc_cntl/option1.rs
index b8afe209ab..69b0ef49e3 100644
--- a/esp32c2/src/rtc_cntl/option1.rs
+++ b/esp32c2/src/rtc_cntl/option1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OPTION1")
-            .field(
-                "force_download_boot",
-                &format_args!("{}", self.force_download_boot().bit()),
-            )
+            .field("force_download_boot", &self.force_download_boot())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OPTION1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/options0.rs b/esp32c2/src/rtc_cntl/options0.rs
index a895a5b0b8..f4041dd56e 100644
--- a/esp32c2/src/rtc_cntl/options0.rs
+++ b/esp32c2/src/rtc_cntl/options0.rs
@@ -161,80 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OPTIONS0")
-            .field(
-                "sw_stall_procpu_c0",
-                &format_args!("{}", self.sw_stall_procpu_c0().bits()),
-            )
-            .field(
-                "sw_procpu_rst",
-                &format_args!("{}", self.sw_procpu_rst().bit()),
-            )
-            .field(
-                "bb_i2c_force_pd",
-                &format_args!("{}", self.bb_i2c_force_pd().bit()),
-            )
-            .field(
-                "bb_i2c_force_pu",
-                &format_args!("{}", self.bb_i2c_force_pu().bit()),
-            )
-            .field(
-                "bbpll_i2c_force_pd",
-                &format_args!("{}", self.bbpll_i2c_force_pd().bit()),
-            )
-            .field(
-                "bbpll_i2c_force_pu",
-                &format_args!("{}", self.bbpll_i2c_force_pu().bit()),
-            )
-            .field(
-                "bbpll_force_pd",
-                &format_args!("{}", self.bbpll_force_pd().bit()),
-            )
-            .field(
-                "bbpll_force_pu",
-                &format_args!("{}", self.bbpll_force_pu().bit()),
-            )
-            .field(
-                "xtl_force_pd",
-                &format_args!("{}", self.xtl_force_pd().bit()),
-            )
-            .field(
-                "xtl_force_pu",
-                &format_args!("{}", self.xtl_force_pu().bit()),
-            )
-            .field(
-                "xtl_en_wait",
-                &format_args!("{}", self.xtl_en_wait().bits()),
-            )
-            .field(
-                "xtl_ext_ctr_sel",
-                &format_args!("{}", self.xtl_ext_ctr_sel().bits()),
-            )
-            .field(
-                "analog_force_iso",
-                &format_args!("{}", self.analog_force_iso().bit()),
-            )
-            .field(
-                "analog_force_noiso",
-                &format_args!("{}", self.analog_force_noiso().bit()),
-            )
-            .field(
-                "dg_wrap_force_rst",
-                &format_args!("{}", self.dg_wrap_force_rst().bit()),
-            )
-            .field(
-                "dg_wrap_force_norst",
-                &format_args!("{}", self.dg_wrap_force_norst().bit()),
-            )
-            .field("sw_sys_rst", &format_args!("{}", self.sw_sys_rst().bit()))
+            .field("sw_stall_procpu_c0", &self.sw_stall_procpu_c0())
+            .field("sw_procpu_rst", &self.sw_procpu_rst())
+            .field("bb_i2c_force_pd", &self.bb_i2c_force_pd())
+            .field("bb_i2c_force_pu", &self.bb_i2c_force_pu())
+            .field("bbpll_i2c_force_pd", &self.bbpll_i2c_force_pd())
+            .field("bbpll_i2c_force_pu", &self.bbpll_i2c_force_pu())
+            .field("bbpll_force_pd", &self.bbpll_force_pd())
+            .field("bbpll_force_pu", &self.bbpll_force_pu())
+            .field("xtl_force_pd", &self.xtl_force_pd())
+            .field("xtl_force_pu", &self.xtl_force_pu())
+            .field("xtl_en_wait", &self.xtl_en_wait())
+            .field("xtl_ext_ctr_sel", &self.xtl_ext_ctr_sel())
+            .field("analog_force_iso", &self.analog_force_iso())
+            .field("analog_force_noiso", &self.analog_force_noiso())
+            .field("dg_wrap_force_rst", &self.dg_wrap_force_rst())
+            .field("dg_wrap_force_norst", &self.dg_wrap_force_norst())
+            .field("sw_sys_rst", &self.sw_sys_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OPTIONS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 2:3 - {reg_sw_stall_procpu_c1\\[5:0\\], reg_sw_stall_procpu_c0\\[1:0\\]} == 0x86 will stall PRO CPU"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/pad_hold.rs b/esp32c2/src/rtc_cntl/pad_hold.rs
index 16c620a2de..2fead680bd 100644
--- a/esp32c2/src/rtc_cntl/pad_hold.rs
+++ b/esp32c2/src/rtc_cntl/pad_hold.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_HOLD")
-            .field(
-                "gpio_pin0_hold",
-                &format_args!("{}", self.gpio_pin0_hold().bit()),
-            )
-            .field(
-                "gpio_pin1_hold",
-                &format_args!("{}", self.gpio_pin1_hold().bit()),
-            )
-            .field(
-                "gpio_pin2_hold",
-                &format_args!("{}", self.gpio_pin2_hold().bit()),
-            )
-            .field(
-                "gpio_pin3_hold",
-                &format_args!("{}", self.gpio_pin3_hold().bit()),
-            )
-            .field(
-                "gpio_pin4_hold",
-                &format_args!("{}", self.gpio_pin4_hold().bit()),
-            )
-            .field(
-                "gpio_pin5_hold",
-                &format_args!("{}", self.gpio_pin5_hold().bit()),
-            )
+            .field("gpio_pin0_hold", &self.gpio_pin0_hold())
+            .field("gpio_pin1_hold", &self.gpio_pin1_hold())
+            .field("gpio_pin2_hold", &self.gpio_pin2_hold())
+            .field("gpio_pin3_hold", &self.gpio_pin3_hold())
+            .field("gpio_pin4_hold", &self.gpio_pin4_hold())
+            .field("gpio_pin5_hold", &self.gpio_pin5_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/pwc.rs b/esp32c2/src/rtc_cntl/pwc.rs
index 9c3f536d72..47fd0924df 100644
--- a/esp32c2/src/rtc_cntl/pwc.rs
+++ b/esp32c2/src/rtc_cntl/pwc.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWC")
-            .field(
-                "pad_force_hold",
-                &format_args!("{}", self.pad_force_hold().bit()),
-            )
+            .field("pad_force_hold", &self.pad_force_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - rtc pad force hold"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/reset_state.rs b/esp32c2/src/rtc_cntl/reset_state.rs
index b872b62fee..96ffb8f328 100644
--- a/esp32c2/src/rtc_cntl/reset_state.rs
+++ b/esp32c2/src/rtc_cntl/reset_state.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET_STATE")
-            .field(
-                "reset_cause_procpu",
-                &format_args!("{}", self.reset_cause_procpu().bits()),
-            )
-            .field(
-                "stat_vector_sel_procpu",
-                &format_args!("{}", self.stat_vector_sel_procpu().bit()),
-            )
-            .field(
-                "ocd_halt_on_reset_procpu",
-                &format_args!("{}", self.ocd_halt_on_reset_procpu().bit()),
-            )
-            .field(
-                "dreset_mask_procpu",
-                &format_args!("{}", self.dreset_mask_procpu().bit()),
-            )
+            .field("reset_cause_procpu", &self.reset_cause_procpu())
+            .field("stat_vector_sel_procpu", &self.stat_vector_sel_procpu())
+            .field("ocd_halt_on_reset_procpu", &self.ocd_halt_on_reset_procpu())
+            .field("dreset_mask_procpu", &self.dreset_mask_procpu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - reset cause of PRO CPU"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/rtc_cntl.rs b/esp32c2/src/rtc_cntl/rtc_cntl.rs
index 31d65b292f..62eab00901 100644
--- a/esp32c2/src/rtc_cntl/rtc_cntl.rs
+++ b/esp32c2/src/rtc_cntl/rtc_cntl.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_CNTL")
-            .field(
-                "dig_reg_cal_en",
-                &format_args!("{}", self.dig_reg_cal_en().bit()),
-            )
-            .field("sck_dcap", &format_args!("{}", self.sck_dcap().bits()))
-            .field(
-                "regulator_force_pd",
-                &format_args!("{}", self.regulator_force_pd().bit()),
-            )
-            .field(
-                "regulator_force_pu",
-                &format_args!("{}", self.regulator_force_pu().bit()),
-            )
+            .field("dig_reg_cal_en", &self.dig_reg_cal_en())
+            .field("sck_dcap", &self.sck_dcap())
+            .field("regulator_force_pd", &self.regulator_force_pd())
+            .field("regulator_force_pu", &self.regulator_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/slow_clk_conf.rs b/esp32c2/src/rtc_cntl/slow_clk_conf.rs
index 6946571c16..fd65a51c30 100644
--- a/esp32c2/src/rtc_cntl/slow_clk_conf.rs
+++ b/esp32c2/src/rtc_cntl/slow_clk_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLOW_CLK_CONF")
-            .field(
-                "ana_clk_div_vld",
-                &format_args!("{}", self.ana_clk_div_vld().bit()),
-            )
-            .field(
-                "ana_clk_div",
-                &format_args!("{}", self.ana_clk_div().bits()),
-            )
-            .field(
-                "slow_clk_next_edge",
-                &format_args!("{}", self.slow_clk_next_edge().bit()),
-            )
+            .field("ana_clk_div_vld", &self.ana_clk_div_vld())
+            .field("ana_clk_div", &self.ana_clk_div())
+            .field("slow_clk_next_edge", &self.slow_clk_next_edge())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLOW_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 22 - used to sync div bus. clear vld before set reg_rtc_ana_clk_div"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/slp_reject_cause.rs b/esp32c2/src/rtc_cntl/slp_reject_cause.rs
index c02b425d16..5eaeb29f0d 100644
--- a/esp32c2/src/rtc_cntl/slp_reject_cause.rs
+++ b/esp32c2/src/rtc_cntl/slp_reject_cause.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_REJECT_CAUSE")
-            .field(
-                "reject_cause",
-                &format_args!("{}", self.reject_cause().bits()),
-            )
+            .field("reject_cause", &self.reject_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_REJECT_CAUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - sleep reject cause"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/slp_reject_conf.rs b/esp32c2/src/rtc_cntl/slp_reject_conf.rs
index a3f3e85f97..eb5b98e00b 100644
--- a/esp32c2/src/rtc_cntl/slp_reject_conf.rs
+++ b/esp32c2/src/rtc_cntl/slp_reject_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_REJECT_CONF")
-            .field(
-                "sleep_reject_ena",
-                &format_args!("{}", self.sleep_reject_ena().bits()),
-            )
-            .field(
-                "light_slp_reject_en",
-                &format_args!("{}", self.light_slp_reject_en().bit()),
-            )
-            .field(
-                "deep_slp_reject_en",
-                &format_args!("{}", self.deep_slp_reject_en().bit()),
-            )
+            .field("sleep_reject_ena", &self.sleep_reject_ena())
+            .field("light_slp_reject_en", &self.light_slp_reject_en())
+            .field("deep_slp_reject_en", &self.deep_slp_reject_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_REJECT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 12:29 - sleep reject enable"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/slp_timer0.rs b/esp32c2/src/rtc_cntl/slp_timer0.rs
index ab7ce66441..fbb54dc331 100644
--- a/esp32c2/src/rtc_cntl/slp_timer0.rs
+++ b/esp32c2/src/rtc_cntl/slp_timer0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_TIMER0")
-            .field("slp_val_lo", &format_args!("{}", self.slp_val_lo().bits()))
+            .field("slp_val_lo", &self.slp_val_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_TIMER0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/slp_timer1.rs b/esp32c2/src/rtc_cntl/slp_timer1.rs
index 86539a3d99..8fe206e128 100644
--- a/esp32c2/src/rtc_cntl/slp_timer1.rs
+++ b/esp32c2/src/rtc_cntl/slp_timer1.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_TIMER1")
-            .field("slp_val_hi", &format_args!("{}", self.slp_val_hi().bits()))
-            .field(
-                "main_timer_alarm_en",
-                &format_args!("{}", self.main_timer_alarm_en().bit()),
-            )
+            .field("slp_val_hi", &self.slp_val_hi())
+            .field("main_timer_alarm_en", &self.main_timer_alarm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_TIMER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - RTC sleep timer high 16 bits"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/slp_wakeup_cause.rs b/esp32c2/src/rtc_cntl/slp_wakeup_cause.rs
index b4ade7fb88..8df9be8aab 100644
--- a/esp32c2/src/rtc_cntl/slp_wakeup_cause.rs
+++ b/esp32c2/src/rtc_cntl/slp_wakeup_cause.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CAUSE")
-            .field(
-                "wakeup_cause",
-                &format_args!("{}", self.wakeup_cause().bits()),
-            )
+            .field("wakeup_cause", &self.wakeup_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CAUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:16 - sleep wakeup cause"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/state0.rs b/esp32c2/src/rtc_cntl/state0.rs
index cc9d1f8c05..f5c50116ac 100644
--- a/esp32c2/src/rtc_cntl/state0.rs
+++ b/esp32c2/src/rtc_cntl/state0.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE0")
-            .field("sw_cpu_int", &format_args!("{}", self.sw_cpu_int().bit()))
-            .field(
-                "slp_reject_cause_clr",
-                &format_args!("{}", self.slp_reject_cause_clr().bit()),
-            )
-            .field(
-                "apb2rtc_bridge_sel",
-                &format_args!("{}", self.apb2rtc_bridge_sel().bit()),
-            )
-            .field(
-                "sdio_active_ind",
-                &format_args!("{}", self.sdio_active_ind().bit()),
-            )
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("sleep_en", &format_args!("{}", self.sleep_en().bit()))
+            .field("sw_cpu_int", &self.sw_cpu_int())
+            .field("slp_reject_cause_clr", &self.slp_reject_cause_clr())
+            .field("apb2rtc_bridge_sel", &self.apb2rtc_bridge_sel())
+            .field("sdio_active_ind", &self.sdio_active_ind())
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sleep_en", &self.sleep_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - rtc software interrupt to main cpu"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/store0.rs b/esp32c2/src/rtc_cntl/store0.rs
index 9563fcf49d..ffbcdba174 100644
--- a/esp32c2/src/rtc_cntl/store0.rs
+++ b/esp32c2/src/rtc_cntl/store0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE0")
-            .field("scratch0", &format_args!("{}", self.scratch0().bits()))
+            .field("scratch0", &self.scratch0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/store1.rs b/esp32c2/src/rtc_cntl/store1.rs
index 72bdd14d72..e7a1ee8e8a 100644
--- a/esp32c2/src/rtc_cntl/store1.rs
+++ b/esp32c2/src/rtc_cntl/store1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE1")
-            .field("scratch1", &format_args!("{}", self.scratch1().bits()))
+            .field("scratch1", &self.scratch1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/store2.rs b/esp32c2/src/rtc_cntl/store2.rs
index 9747536f5d..4f39dd2aa1 100644
--- a/esp32c2/src/rtc_cntl/store2.rs
+++ b/esp32c2/src/rtc_cntl/store2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE2")
-            .field("scratch2", &format_args!("{}", self.scratch2().bits()))
+            .field("scratch2", &self.scratch2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/store3.rs b/esp32c2/src/rtc_cntl/store3.rs
index 1880ba7c8d..5d77fa3ee9 100644
--- a/esp32c2/src/rtc_cntl/store3.rs
+++ b/esp32c2/src/rtc_cntl/store3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE3")
-            .field("scratch3", &format_args!("{}", self.scratch3().bits()))
+            .field("scratch3", &self.scratch3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/store4.rs b/esp32c2/src/rtc_cntl/store4.rs
index 9bed837687..6ab1af493d 100644
--- a/esp32c2/src/rtc_cntl/store4.rs
+++ b/esp32c2/src/rtc_cntl/store4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE4")
-            .field("scratch4", &format_args!("{}", self.scratch4().bits()))
+            .field("scratch4", &self.scratch4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/store5.rs b/esp32c2/src/rtc_cntl/store5.rs
index 88e640ef57..0555f63aa6 100644
--- a/esp32c2/src/rtc_cntl/store5.rs
+++ b/esp32c2/src/rtc_cntl/store5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE5")
-            .field("scratch5", &format_args!("{}", self.scratch5().bits()))
+            .field("scratch5", &self.scratch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/store6.rs b/esp32c2/src/rtc_cntl/store6.rs
index 5f403da20d..f0263cd628 100644
--- a/esp32c2/src/rtc_cntl/store6.rs
+++ b/esp32c2/src/rtc_cntl/store6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE6")
-            .field("scratch6", &format_args!("{}", self.scratch6().bits()))
+            .field("scratch6", &self.scratch6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/store7.rs b/esp32c2/src/rtc_cntl/store7.rs
index d47b230142..2501500c16 100644
--- a/esp32c2/src/rtc_cntl/store7.rs
+++ b/esp32c2/src/rtc_cntl/store7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE7")
-            .field("scratch7", &format_args!("{}", self.scratch7().bits()))
+            .field("scratch7", &self.scratch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/sw_cpu_stall.rs b/esp32c2/src/rtc_cntl/sw_cpu_stall.rs
index 4629866b5b..511535635a 100644
--- a/esp32c2/src/rtc_cntl/sw_cpu_stall.rs
+++ b/esp32c2/src/rtc_cntl/sw_cpu_stall.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SW_CPU_STALL")
-            .field(
-                "sw_stall_procpu_c1",
-                &format_args!("{}", self.sw_stall_procpu_c1().bits()),
-            )
+            .field("sw_stall_procpu_c1", &self.sw_stall_procpu_c1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SW_CPU_STALL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 26:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/swd_conf.rs b/esp32c2/src/rtc_cntl/swd_conf.rs
index 3135afda41..b3580f0356 100644
--- a/esp32c2/src/rtc_cntl/swd_conf.rs
+++ b/esp32c2/src/rtc_cntl/swd_conf.rs
@@ -80,41 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_CONF")
-            .field(
-                "swd_reset_flag",
-                &format_args!("{}", self.swd_reset_flag().bit()),
-            )
-            .field(
-                "swd_feed_int",
-                &format_args!("{}", self.swd_feed_int().bit()),
-            )
-            .field(
-                "swd_bypass_rst",
-                &format_args!("{}", self.swd_bypass_rst().bit()),
-            )
-            .field(
-                "swd_signal_width",
-                &format_args!("{}", self.swd_signal_width().bits()),
-            )
-            .field(
-                "swd_rst_flag_clr",
-                &format_args!("{}", self.swd_rst_flag_clr().bit()),
-            )
-            .field("swd_feed", &format_args!("{}", self.swd_feed().bit()))
-            .field("swd_disable", &format_args!("{}", self.swd_disable().bit()))
-            .field(
-                "swd_auto_feed_en",
-                &format_args!("{}", self.swd_auto_feed_en().bit()),
-            )
+            .field("swd_reset_flag", &self.swd_reset_flag())
+            .field("swd_feed_int", &self.swd_feed_int())
+            .field("swd_bypass_rst", &self.swd_bypass_rst())
+            .field("swd_signal_width", &self.swd_signal_width())
+            .field("swd_rst_flag_clr", &self.swd_rst_flag_clr())
+            .field("swd_feed", &self.swd_feed())
+            .field("swd_disable", &self.swd_disable())
+            .field("swd_auto_feed_en", &self.swd_auto_feed_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - swd reset flag"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/swd_wprotect.rs b/esp32c2/src/rtc_cntl/swd_wprotect.rs
index 54b8c033f0..1d58f03cfb 100644
--- a/esp32c2/src/rtc_cntl/swd_wprotect.rs
+++ b/esp32c2/src/rtc_cntl/swd_wprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_WPROTECT")
-            .field("swd_wkey", &format_args!("{}", self.swd_wkey().bits()))
+            .field("swd_wkey", &self.swd_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_WPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/time_high0.rs b/esp32c2/src/rtc_cntl/time_high0.rs
index 0f865d2a14..faab50575d 100644
--- a/esp32c2/src/rtc_cntl/time_high0.rs
+++ b/esp32c2/src/rtc_cntl/time_high0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_HIGH0")
-            .field(
-                "timer_value0_high",
-                &format_args!("{}", self.timer_value0_high().bits()),
-            )
+            .field("timer_value0_high", &self.timer_value0_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_HIGH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - RTC timer high 16 bits"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/time_high1.rs b/esp32c2/src/rtc_cntl/time_high1.rs
index e105d5570b..a55aa16682 100644
--- a/esp32c2/src/rtc_cntl/time_high1.rs
+++ b/esp32c2/src/rtc_cntl/time_high1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_HIGH1")
-            .field(
-                "timer_value1_high",
-                &format_args!("{}", self.timer_value1_high().bits()),
-            )
+            .field("timer_value1_high", &self.timer_value1_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_HIGH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - RTC timer high 16 bits"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/time_low0.rs b/esp32c2/src/rtc_cntl/time_low0.rs
index f9476fc83e..91d781d1be 100644
--- a/esp32c2/src/rtc_cntl/time_low0.rs
+++ b/esp32c2/src/rtc_cntl/time_low0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_LOW0")
-            .field(
-                "timer_value0_low",
-                &format_args!("{}", self.timer_value0_low().bits()),
-            )
+            .field("timer_value0_low", &self.timer_value0_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_LOW0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - RTC timer low 32 bits"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/time_low1.rs b/esp32c2/src/rtc_cntl/time_low1.rs
index 34cd8e1089..d7b573582d 100644
--- a/esp32c2/src/rtc_cntl/time_low1.rs
+++ b/esp32c2/src/rtc_cntl/time_low1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_LOW1")
-            .field(
-                "timer_value1_low",
-                &format_args!("{}", self.timer_value1_low().bits()),
-            )
+            .field("timer_value1_low", &self.timer_value1_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_LOW1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - RTC timer low 32 bits"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/time_update.rs b/esp32c2/src/rtc_cntl/time_update.rs
index 3fde0820b3..2eb8b7a73f 100644
--- a/esp32c2/src/rtc_cntl/time_update.rs
+++ b/esp32c2/src/rtc_cntl/time_update.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_UPDATE")
-            .field(
-                "timer_sys_stall",
-                &format_args!("{}", self.timer_sys_stall().bit()),
-            )
-            .field(
-                "timer_xtl_off",
-                &format_args!("{}", self.timer_xtl_off().bit()),
-            )
-            .field(
-                "timer_sys_rst",
-                &format_args!("{}", self.timer_sys_rst().bit()),
-            )
-            .field("time_update", &format_args!("{}", self.time_update().bit()))
+            .field("timer_sys_stall", &self.timer_sys_stall())
+            .field("timer_xtl_off", &self.timer_xtl_off())
+            .field("timer_sys_rst", &self.timer_sys_rst())
+            .field("time_update", &self.time_update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - Enable to record system stall time"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/timer1.rs b/esp32c2/src/rtc_cntl/timer1.rs
index 528f164305..05812b6271 100644
--- a/esp32c2/src/rtc_cntl/timer1.rs
+++ b/esp32c2/src/rtc_cntl/timer1.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER1")
-            .field(
-                "cpu_stall_en",
-                &format_args!("{}", self.cpu_stall_en().bit()),
-            )
-            .field(
-                "cpu_stall_wait",
-                &format_args!("{}", self.cpu_stall_wait().bits()),
-            )
-            .field("ck8m_wait", &format_args!("{}", self.ck8m_wait().bits()))
-            .field(
-                "xtl_buf_wait",
-                &format_args!("{}", self.xtl_buf_wait().bits()),
-            )
-            .field(
-                "pll_buf_wait",
-                &format_args!("{}", self.pll_buf_wait().bits()),
-            )
+            .field("cpu_stall_en", &self.cpu_stall_en())
+            .field("cpu_stall_wait", &self.cpu_stall_wait())
+            .field("ck8m_wait", &self.ck8m_wait())
+            .field("xtl_buf_wait", &self.xtl_buf_wait())
+            .field("pll_buf_wait", &self.pll_buf_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - CPU stall enable bit"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/timer2.rs b/esp32c2/src/rtc_cntl/timer2.rs
index 68186321f0..ebe18ac3ba 100644
--- a/esp32c2/src/rtc_cntl/timer2.rs
+++ b/esp32c2/src/rtc_cntl/timer2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER2")
-            .field(
-                "min_time_ck8m_off",
-                &format_args!("{}", self.min_time_ck8m_off().bits()),
-            )
+            .field("min_time_ck8m_off", &self.min_time_ck8m_off())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 24:31 - minimal cycles in slow_clk_rtc for CK8M in power down state"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/timer4.rs b/esp32c2/src/rtc_cntl/timer4.rs
index fc23432f6b..33719cc365 100644
--- a/esp32c2/src/rtc_cntl/timer4.rs
+++ b/esp32c2/src/rtc_cntl/timer4.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER4")
-            .field(
-                "dg_wrap_wait_timer",
-                &format_args!("{}", self.dg_wrap_wait_timer().bits()),
-            )
-            .field(
-                "dg_wrap_powerup_timer",
-                &format_args!("{}", self.dg_wrap_powerup_timer().bits()),
-            )
+            .field("dg_wrap_wait_timer", &self.dg_wrap_wait_timer())
+            .field("dg_wrap_powerup_timer", &self.dg_wrap_powerup_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:24 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/timer5.rs b/esp32c2/src/rtc_cntl/timer5.rs
index 1e6f2cc883..9ab29b6c84 100644
--- a/esp32c2/src/rtc_cntl/timer5.rs
+++ b/esp32c2/src/rtc_cntl/timer5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER5")
-            .field(
-                "min_slp_val",
-                &format_args!("{}", self.min_slp_val().bits()),
-            )
+            .field("min_slp_val", &self.min_slp_val())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:15 - minimal sleep cycles in slow_clk_rtc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/ulp_cp_timer_1.rs b/esp32c2/src/rtc_cntl/ulp_cp_timer_1.rs
index 5e4dc1b769..3c95ff2335 100644
--- a/esp32c2/src/rtc_cntl/ulp_cp_timer_1.rs
+++ b/esp32c2/src/rtc_cntl/ulp_cp_timer_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_TIMER_1")
-            .field(
-                "ulp_cp_timer_slp_cycle",
-                &format_args!("{}", self.ulp_cp_timer_slp_cycle().bits()),
-            )
+            .field("ulp_cp_timer_slp_cycle", &self.ulp_cp_timer_slp_cycle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_TIMER_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:31 - sleep cycles for ULP-coprocessor timer"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/usb_conf.rs b/esp32c2/src/rtc_cntl/usb_conf.rs
index 8a25b27ef8..e05c857a55 100644
--- a/esp32c2/src/rtc_cntl/usb_conf.rs
+++ b/esp32c2/src/rtc_cntl/usb_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_CONF")
-            .field(
-                "io_mux_reset_disable",
-                &format_args!("{}", self.io_mux_reset_disable().bit()),
-            )
+            .field("io_mux_reset_disable", &self.io_mux_reset_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/wakeup_state.rs b/esp32c2/src/rtc_cntl/wakeup_state.rs
index 0b0512c6ef..307604b525 100644
--- a/esp32c2/src/rtc_cntl/wakeup_state.rs
+++ b/esp32c2/src/rtc_cntl/wakeup_state.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WAKEUP_STATE")
-            .field("wakeup_ena", &format_args!("{}", self.wakeup_ena().bits()))
+            .field("wakeup_ena", &self.wakeup_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WAKEUP_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 15:31 - wakeup enable bitmap"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/wdtconfig0.rs b/esp32c2/src/rtc_cntl/wdtconfig0.rs
index 75cdf394e7..c1d2020a36 100644
--- a/esp32c2/src/rtc_cntl/wdtconfig0.rs
+++ b/esp32c2/src/rtc_cntl/wdtconfig0.rs
@@ -116,48 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG0")
-            .field(
-                "wdt_chip_reset_width",
-                &format_args!("{}", self.wdt_chip_reset_width().bits()),
-            )
-            .field(
-                "wdt_chip_reset_en",
-                &format_args!("{}", self.wdt_chip_reset_en().bit()),
-            )
-            .field(
-                "wdt_pause_in_slp",
-                &format_args!("{}", self.wdt_pause_in_slp().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_chip_reset_width", &self.wdt_chip_reset_width())
+            .field("wdt_chip_reset_en", &self.wdt_chip_reset_en())
+            .field("wdt_pause_in_slp", &self.wdt_pause_in_slp())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - chip reset siginal pulse width"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/wdtconfig1.rs b/esp32c2/src/rtc_cntl/wdtconfig1.rs
index d507f2e691..aa6961a2c3 100644
--- a/esp32c2/src/rtc_cntl/wdtconfig1.rs
+++ b/esp32c2/src/rtc_cntl/wdtconfig1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG1")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/wdtconfig2.rs b/esp32c2/src/rtc_cntl/wdtconfig2.rs
index 7a33aeba16..934d7b75f1 100644
--- a/esp32c2/src/rtc_cntl/wdtconfig2.rs
+++ b/esp32c2/src/rtc_cntl/wdtconfig2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG2")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/wdtconfig3.rs b/esp32c2/src/rtc_cntl/wdtconfig3.rs
index 4f6cf5c290..ee0548c58b 100644
--- a/esp32c2/src/rtc_cntl/wdtconfig3.rs
+++ b/esp32c2/src/rtc_cntl/wdtconfig3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG3")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/wdtconfig4.rs b/esp32c2/src/rtc_cntl/wdtconfig4.rs
index 6efca39af7..43b5bbf715 100644
--- a/esp32c2/src/rtc_cntl/wdtconfig4.rs
+++ b/esp32c2/src/rtc_cntl/wdtconfig4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG4")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/wdtfeed.rs b/esp32c2/src/rtc_cntl/wdtfeed.rs
index d7a4c1d6fa..2766e5fa9b 100644
--- a/esp32c2/src/rtc_cntl/wdtfeed.rs
+++ b/esp32c2/src/rtc_cntl/wdtfeed.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTFEED")
-            .field("wdt_feed", &format_args!("{}", self.wdt_feed().bit()))
+            .field("wdt_feed", &self.wdt_feed())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTFEED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/rtc_cntl/wdtwprotect.rs b/esp32c2/src/rtc_cntl/wdtwprotect.rs
index 2ed49c23c1..9c27e21d52 100644
--- a/esp32c2/src/rtc_cntl/wdtwprotect.rs
+++ b/esp32c2/src/rtc_cntl/wdtwprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTWPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTWPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add desc"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/apb_peripheral_access_0.rs b/esp32c2/src/sensitive/apb_peripheral_access_0.rs
index 83407daa8c..f8101328b5 100644
--- a/esp32c2/src/sensitive/apb_peripheral_access_0.rs
+++ b/esp32c2/src/sensitive/apb_peripheral_access_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB_PERIPHERAL_ACCESS_0")
             .field(
                 "apb_peripheral_access_lock",
-                &format_args!("{}", self.apb_peripheral_access_lock().bit()),
+                &self.apb_peripheral_access_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_PERIPHERAL_ACCESS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/apb_peripheral_access_1.rs b/esp32c2/src/sensitive/apb_peripheral_access_1.rs
index 1e4f54af2f..398b95f57b 100644
--- a/esp32c2/src/sensitive/apb_peripheral_access_1.rs
+++ b/esp32c2/src/sensitive/apb_peripheral_access_1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB_PERIPHERAL_ACCESS_1")
             .field(
                 "apb_peripheral_access_split_burst",
-                &format_args!("{}", self.apb_peripheral_access_split_burst().bit()),
+                &self.apb_peripheral_access_split_burst(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_PERIPHERAL_ACCESS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/cache_mmu_access_0.rs b/esp32c2/src/sensitive/cache_mmu_access_0.rs
index a2a73de960..c4106bfd53 100644
--- a/esp32c2/src/sensitive/cache_mmu_access_0.rs
+++ b/esp32c2/src/sensitive/cache_mmu_access_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_ACCESS_0")
-            .field(
-                "cache_mmu_access_lock",
-                &format_args!("{}", self.cache_mmu_access_lock().bit()),
-            )
+            .field("cache_mmu_access_lock", &self.cache_mmu_access_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_ACCESS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/cache_mmu_access_1.rs b/esp32c2/src/sensitive/cache_mmu_access_1.rs
index 8b9035e6f7..ba34a19aeb 100644
--- a/esp32c2/src/sensitive/cache_mmu_access_1.rs
+++ b/esp32c2/src/sensitive/cache_mmu_access_1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_ACCESS_1")
-            .field(
-                "pro_mmu_rd_acs",
-                &format_args!("{}", self.pro_mmu_rd_acs().bit()),
-            )
-            .field(
-                "pro_mmu_wr_acs",
-                &format_args!("{}", self.pro_mmu_wr_acs().bit()),
-            )
+            .field("pro_mmu_rd_acs", &self.pro_mmu_rd_acs())
+            .field("pro_mmu_wr_acs", &self.pro_mmu_wr_acs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_ACCESS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/cache_tag_access_0.rs b/esp32c2/src/sensitive/cache_tag_access_0.rs
index 4c08c4092f..54c724961b 100644
--- a/esp32c2/src/sensitive/cache_tag_access_0.rs
+++ b/esp32c2/src/sensitive/cache_tag_access_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_TAG_ACCESS_0")
-            .field(
-                "cache_tag_access_lock",
-                &format_args!("{}", self.cache_tag_access_lock().bit()),
-            )
+            .field("cache_tag_access_lock", &self.cache_tag_access_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_TAG_ACCESS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/cache_tag_access_1.rs b/esp32c2/src/sensitive/cache_tag_access_1.rs
index a644ef9c17..ae54639d29 100644
--- a/esp32c2/src/sensitive/cache_tag_access_1.rs
+++ b/esp32c2/src/sensitive/cache_tag_access_1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_TAG_ACCESS_1")
-            .field(
-                "pro_i_tag_rd_acs",
-                &format_args!("{}", self.pro_i_tag_rd_acs().bit()),
-            )
-            .field(
-                "pro_i_tag_wr_acs",
-                &format_args!("{}", self.pro_i_tag_wr_acs().bit()),
-            )
-            .field(
-                "pro_d_tag_rd_acs",
-                &format_args!("{}", self.pro_d_tag_rd_acs().bit()),
-            )
-            .field(
-                "pro_d_tag_wr_acs",
-                &format_args!("{}", self.pro_d_tag_wr_acs().bit()),
-            )
+            .field("pro_i_tag_rd_acs", &self.pro_i_tag_rd_acs())
+            .field("pro_i_tag_wr_acs", &self.pro_i_tag_wr_acs())
+            .field("pro_d_tag_rd_acs", &self.pro_d_tag_rd_acs())
+            .field("pro_d_tag_wr_acs", &self.pro_d_tag_wr_acs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_TAG_ACCESS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/clock_gate.rs b/esp32c2/src/sensitive/clock_gate.rs
index 8f6f21be25..b4f346377e 100644
--- a/esp32c2/src/sensitive/clock_gate.rs
+++ b/esp32c2/src/sensitive/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/internal_sram_usage_0.rs b/esp32c2/src/sensitive/internal_sram_usage_0.rs
index 136c2c1cd9..9d3ae3282c 100644
--- a/esp32c2/src/sensitive/internal_sram_usage_0.rs
+++ b/esp32c2/src/sensitive/internal_sram_usage_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERNAL_SRAM_USAGE_0")
-            .field(
-                "internal_sram_usage_lock",
-                &format_args!("{}", self.internal_sram_usage_lock().bit()),
-            )
+            .field("internal_sram_usage_lock", &self.internal_sram_usage_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERNAL_SRAM_USAGE_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/internal_sram_usage_1.rs b/esp32c2/src/sensitive/internal_sram_usage_1.rs
index 1d9fe7279b..201c4f8241 100644
--- a/esp32c2/src/sensitive/internal_sram_usage_1.rs
+++ b/esp32c2/src/sensitive/internal_sram_usage_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTERNAL_SRAM_USAGE_1")
             .field(
                 "internal_sram_usage_cpu_cache",
-                &format_args!("{}", self.internal_sram_usage_cpu_cache().bit()),
+                &self.internal_sram_usage_cpu_cache(),
             )
             .field(
                 "internal_sram_usage_cpu_sram",
-                &format_args!("{}", self.internal_sram_usage_cpu_sram().bits()),
+                &self.internal_sram_usage_cpu_sram(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERNAL_SRAM_USAGE_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/internal_sram_usage_3.rs b/esp32c2/src/sensitive/internal_sram_usage_3.rs
index dc52ea016d..510ca97f12 100644
--- a/esp32c2/src/sensitive/internal_sram_usage_3.rs
+++ b/esp32c2/src/sensitive/internal_sram_usage_3.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTERNAL_SRAM_USAGE_3")
             .field(
                 "internal_sram_usage_mac_dump_sram",
-                &format_args!("{}", self.internal_sram_usage_mac_dump_sram().bits()),
+                &self.internal_sram_usage_mac_dump_sram(),
             )
             .field(
                 "internal_sram_alloc_mac_dump",
-                &format_args!("{}", self.internal_sram_alloc_mac_dump().bit()),
+                &self.internal_sram_alloc_mac_dump(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERNAL_SRAM_USAGE_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/pif_access_monitor_0.rs b/esp32c2/src/sensitive/pif_access_monitor_0.rs
index 6da5f562fa..fdca4892a5 100644
--- a/esp32c2/src/sensitive/pif_access_monitor_0.rs
+++ b/esp32c2/src/sensitive/pif_access_monitor_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIF_ACCESS_MONITOR_0")
-            .field(
-                "pif_access_monitor_lock",
-                &format_args!("{}", self.pif_access_monitor_lock().bit()),
-            )
+            .field("pif_access_monitor_lock", &self.pif_access_monitor_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIF_ACCESS_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/pif_access_monitor_1.rs b/esp32c2/src/sensitive/pif_access_monitor_1.rs
index 8e092f43e7..b3f4a817e9 100644
--- a/esp32c2/src/sensitive/pif_access_monitor_1.rs
+++ b/esp32c2/src/sensitive/pif_access_monitor_1.rs
@@ -30,21 +30,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIF_ACCESS_MONITOR_1")
             .field(
                 "pif_access_monitor_nonword_violate_clr",
-                &format_args!("{}", self.pif_access_monitor_nonword_violate_clr().bit()),
+                &self.pif_access_monitor_nonword_violate_clr(),
             )
             .field(
                 "pif_access_monitor_nonword_violate_en",
-                &format_args!("{}", self.pif_access_monitor_nonword_violate_en().bit()),
+                &self.pif_access_monitor_nonword_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIF_ACCESS_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/pif_access_monitor_2.rs b/esp32c2/src/sensitive/pif_access_monitor_2.rs
index 4cd2b37923..cd916db057 100644
--- a/esp32c2/src/sensitive/pif_access_monitor_2.rs
+++ b/esp32c2/src/sensitive/pif_access_monitor_2.rs
@@ -26,25 +26,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIF_ACCESS_MONITOR_2")
             .field(
                 "pif_access_monitor_nonword_violate_intr",
-                &format_args!("{}", self.pif_access_monitor_nonword_violate_intr().bit()),
+                &self.pif_access_monitor_nonword_violate_intr(),
             )
             .field(
                 "pif_access_monitor_nonword_violate_status_hsize",
-                &format_args!(
-                    "{}",
-                    self.pif_access_monitor_nonword_violate_status_hsize()
-                        .bits()
-                ),
+                &self.pif_access_monitor_nonword_violate_status_hsize(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIF_ACCESS_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pif_access_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PIF_ACCESS_MONITOR_2_SPEC;
 impl crate::RegisterSpec for PIF_ACCESS_MONITOR_2_SPEC {
diff --git a/esp32c2/src/sensitive/pif_access_monitor_3.rs b/esp32c2/src/sensitive/pif_access_monitor_3.rs
index f6825aed45..d2120a472a 100644
--- a/esp32c2/src/sensitive/pif_access_monitor_3.rs
+++ b/esp32c2/src/sensitive/pif_access_monitor_3.rs
@@ -17,21 +17,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIF_ACCESS_MONITOR_3")
             .field(
                 "pif_access_monitor_nonword_violate_status_haddr",
-                &format_args!(
-                    "{}",
-                    self.pif_access_monitor_nonword_violate_status_haddr()
-                        .bits()
-                ),
+                &self.pif_access_monitor_nonword_violate_status_haddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIF_ACCESS_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pif_access_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PIF_ACCESS_MONITOR_3_SPEC;
 impl crate::RegisterSpec for PIF_ACCESS_MONITOR_3_SPEC {
diff --git a/esp32c2/src/sensitive/rom_table.rs b/esp32c2/src/sensitive/rom_table.rs
index acd998ddab..20329edf5e 100644
--- a/esp32c2/src/sensitive/rom_table.rs
+++ b/esp32c2/src/sensitive/rom_table.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_TABLE")
-            .field("rom_table", &format_args!("{}", self.rom_table().bits()))
+            .field("rom_table", &self.rom_table())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_TABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/rom_table_lock.rs b/esp32c2/src/sensitive/rom_table_lock.rs
index 327fadcc33..f9735bd598 100644
--- a/esp32c2/src/sensitive/rom_table_lock.rs
+++ b/esp32c2/src/sensitive/rom_table_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_TABLE_LOCK")
-            .field(
-                "rom_table_lock",
-                &format_args!("{}", self.rom_table_lock().bit()),
-            )
+            .field("rom_table_lock", &self.rom_table_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_TABLE_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/sensitive_reg_date.rs b/esp32c2/src/sensitive/sensitive_reg_date.rs
index c4e64b6d24..4ae63c6b86 100644
--- a/esp32c2/src/sensitive/sensitive_reg_date.rs
+++ b/esp32c2/src/sensitive/sensitive_reg_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SENSITIVE_REG_DATE")
-            .field(
-                "sensitive_reg_date",
-                &format_args!("{}", self.sensitive_reg_date().bits()),
-            )
+            .field("sensitive_reg_date", &self.sensitive_reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SENSITIVE_REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Need add description"]
     #[inline(always)]
diff --git a/esp32c2/src/sensitive/xts_aes_key_update.rs b/esp32c2/src/sensitive/xts_aes_key_update.rs
index 5d41ac24c4..3fee8a5cc8 100644
--- a/esp32c2/src/sensitive/xts_aes_key_update.rs
+++ b/esp32c2/src/sensitive/xts_aes_key_update.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_AES_KEY_UPDATE")
-            .field(
-                "xts_aes_key_update",
-                &format_args!("{}", self.xts_aes_key_update().bit()),
-            )
+            .field("xts_aes_key_update", &self.xts_aes_key_update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_AES_KEY_UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to update xts_aes key"]
     #[inline(always)]
diff --git a/esp32c2/src/sha/busy.rs b/esp32c2/src/sha/busy.rs
index d586138364..ec4ecab687 100644
--- a/esp32c2/src/sha/busy.rs
+++ b/esp32c2/src/sha/busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUSY")
-            .field("state", &format_args!("{}", self.state().bit()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Busy register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUSY_SPEC;
 impl crate::RegisterSpec for BUSY_SPEC {
diff --git a/esp32c2/src/sha/date.rs b/esp32c2/src/sha/date.rs
index 0320a0619a..7d041db081 100644
--- a/esp32c2/src/sha/date.rs
+++ b/esp32c2/src/sha/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/sha/dma_block_num.rs b/esp32c2/src/sha/dma_block_num.rs
index 235679368f..be8854254d 100644
--- a/esp32c2/src/sha/dma_block_num.rs
+++ b/esp32c2/src/sha/dma_block_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_BLOCK_NUM")
-            .field(
-                "dma_block_num",
-                &format_args!("{}", self.dma_block_num().bits()),
-            )
+            .field("dma_block_num", &self.dma_block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Dma-sha block number."]
     #[inline(always)]
diff --git a/esp32c2/src/sha/h_mem.rs b/esp32c2/src/sha/h_mem.rs
index e0865c92c6..13a6f95266 100644
--- a/esp32c2/src/sha/h_mem.rs
+++ b/esp32c2/src/sha/h_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Sha H memory which contains intermediate hash or finial hash.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct H_MEM_SPEC;
diff --git a/esp32c2/src/sha/irq_ena.rs b/esp32c2/src/sha/irq_ena.rs
index 8d61ac4aae..725a0f2641 100644
--- a/esp32c2/src/sha/irq_ena.rs
+++ b/esp32c2/src/sha/irq_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IRQ_ENA")
-            .field(
-                "interrupt_ena",
-                &format_args!("{}", self.interrupt_ena().bit()),
-            )
+            .field("interrupt_ena", &self.interrupt_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IRQ_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable."]
     #[inline(always)]
diff --git a/esp32c2/src/sha/m_mem.rs b/esp32c2/src/sha/m_mem.rs
index ccac5e7d71..7418659e89 100644
--- a/esp32c2/src/sha/m_mem.rs
+++ b/esp32c2/src/sha/m_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Sha M memory which contains message.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct M_MEM_SPEC;
diff --git a/esp32c2/src/sha/mode.rs b/esp32c2/src/sha/mode.rs
index 2b849314d6..ab2c8b2b20 100644
--- a/esp32c2/src/sha/mode.rs
+++ b/esp32c2/src/sha/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/sha/t_length.rs b/esp32c2/src/sha/t_length.rs
index 523a021805..845f709a89 100644
--- a/esp32c2/src/sha/t_length.rs
+++ b/esp32c2/src/sha/t_length.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T_LENGTH")
-            .field("t_length", &format_args!("{}", self.t_length().bits()))
+            .field("t_length", &self.t_length())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T_LENGTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Sha t_length (used if and only if mode == SHA_512/t)."]
     #[inline(always)]
diff --git a/esp32c2/src/sha/t_string.rs b/esp32c2/src/sha/t_string.rs
index db1093db4b..c533a0e0d5 100644
--- a/esp32c2/src/sha/t_string.rs
+++ b/esp32c2/src/sha/t_string.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T_STRING")
-            .field("t_string", &format_args!("{}", self.t_string().bits()))
+            .field("t_string", &self.t_string())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T_STRING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Sha t_string (used if and only if mode == SHA_512/t)."]
     #[inline(always)]
diff --git a/esp32c2/src/spi0/cache_fctrl.rs b/esp32c2/src/spi0/cache_fctrl.rs
index 72f388883f..bd069158f3 100644
--- a/esp32c2/src/spi0/cache_fctrl.rs
+++ b/esp32c2/src/spi0/cache_fctrl.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_FCTRL")
-            .field(
-                "cache_req_en",
-                &format_args!("{}", self.cache_req_en().bit()),
-            )
-            .field(
-                "cache_usr_addr_4byte",
-                &format_args!("{}", self.cache_usr_addr_4byte().bit()),
-            )
-            .field(
-                "cache_flash_usr_cmd",
-                &format_args!("{}", self.cache_flash_usr_cmd().bit()),
-            )
-            .field("fdin_dual", &format_args!("{}", self.fdin_dual().bit()))
-            .field("fdout_dual", &format_args!("{}", self.fdout_dual().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("fdin_quad", &format_args!("{}", self.fdin_quad().bit()))
-            .field("fdout_quad", &format_args!("{}", self.fdout_quad().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
+            .field("cache_req_en", &self.cache_req_en())
+            .field("cache_usr_addr_4byte", &self.cache_usr_addr_4byte())
+            .field("cache_flash_usr_cmd", &self.cache_flash_usr_cmd())
+            .field("fdin_dual", &self.fdin_dual())
+            .field("fdout_dual", &self.fdout_dual())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("fdin_quad", &self.fdin_quad())
+            .field("fdout_quad", &self.fdout_quad())
+            .field("faddr_quad", &self.faddr_quad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_FCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - For SPI0, Cache access enable, 1: enable, 0:disable."]
     #[inline(always)]
diff --git a/esp32c2/src/spi0/clock.rs b/esp32c2/src/spi0/clock.rs
index 999d107e76..6f3d2a552b 100644
--- a/esp32c2/src/spi0/clock.rs
+++ b/esp32c2/src/spi0/clock.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."]
     #[inline(always)]
diff --git a/esp32c2/src/spi0/clock_gate.rs b/esp32c2/src/spi0/clock_gate.rs
index 9137df9c1e..82cb1e6398 100644
--- a/esp32c2/src/spi0/clock_gate.rs
+++ b/esp32c2/src/spi0/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."]
     #[inline(always)]
diff --git a/esp32c2/src/spi0/core_clk_sel.rs b/esp32c2/src/spi0/core_clk_sel.rs
index ba35380df7..6a5fdadee1 100644
--- a/esp32c2/src/spi0/core_clk_sel.rs
+++ b/esp32c2/src/spi0/core_clk_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_CLK_SEL")
-            .field(
-                "spi01_clk_sel",
-                &format_args!("{}", self.spi01_clk_sel().bits()),
-            )
+            .field("spi01_clk_sel", &self.spi01_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_CLK_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used."]
     #[inline(always)]
diff --git a/esp32c2/src/spi0/ctrl.rs b/esp32c2/src/spi0/ctrl.rs
index 76992c6668..fbb91a4dc4 100644
--- a/esp32c2/src/spi0/ctrl.rs
+++ b/esp32c2/src/spi0/ctrl.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("fdummy_out", &format_args!("{}", self.fdummy_out().bit()))
-            .field("fcmd_dual", &format_args!("{}", self.fcmd_dual().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fastrd_mode", &format_args!("{}", self.fastrd_mode().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("wp", &format_args!("{}", self.wp().bit()))
-            .field("fread_dio", &format_args!("{}", self.fread_dio().bit()))
-            .field("fread_qio", &format_args!("{}", self.fread_qio().bit()))
+            .field("fdummy_out", &self.fdummy_out())
+            .field("fcmd_dual", &self.fcmd_dual())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fastrd_mode", &self.fastrd_mode())
+            .field("fread_dual", &self.fread_dual())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("fread_quad", &self.fread_quad())
+            .field("wp", &self.wp())
+            .field("fread_dio", &self.fread_dio())
+            .field("fread_qio", &self.fread_qio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - In the dummy phase the signal level of spi is output by the spi controller."]
     #[inline(always)]
diff --git a/esp32c2/src/spi0/ctrl1.rs b/esp32c2/src/spi0/ctrl1.rs
index 47ee6011ea..a29f19c785 100644
--- a/esp32c2/src/spi0/ctrl1.rs
+++ b/esp32c2/src/spi0/ctrl1.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL1")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
+            .field("clk_mode", &self.clk_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
     #[inline(always)]
diff --git a/esp32c2/src/spi0/ctrl2.rs b/esp32c2/src/spi0/ctrl2.rs
index 36195ca9d1..6cd2906084 100644
--- a/esp32c2/src/spi0/ctrl2.rs
+++ b/esp32c2/src/spi0/ctrl2.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field(
-                "cs_setup_time",
-                &format_args!("{}", self.cs_setup_time().bits()),
-            )
-            .field(
-                "cs_hold_time",
-                &format_args!("{}", self.cs_hold_time().bits()),
-            )
-            .field(
-                "cs_hold_delay",
-                &format_args!("{}", self.cs_hold_delay().bits()),
-            )
+            .field("cs_setup_time", &self.cs_setup_time())
+            .field("cs_hold_time", &self.cs_hold_time())
+            .field("cs_hold_delay", &self.cs_hold_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit."]
     #[inline(always)]
diff --git a/esp32c2/src/spi0/date.rs b/esp32c2/src/spi0/date.rs
index f7b049b85c..a01e948b04 100644
--- a/esp32c2/src/spi0/date.rs
+++ b/esp32c2/src/spi0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/spi0/din_mode.rs b/esp32c2/src/spi0/din_mode.rs
index fbbc0a0fbc..c3ea295d0b 100644
--- a/esp32c2/src/spi0/din_mode.rs
+++ b/esp32c2/src/spi0/din_mode.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_MODE")
-            .field("din0_mode", &format_args!("{}", self.din0_mode().bits()))
-            .field("din1_mode", &format_args!("{}", self.din1_mode().bits()))
-            .field("din2_mode", &format_args!("{}", self.din2_mode().bits()))
-            .field("din3_mode", &format_args!("{}", self.din3_mode().bits()))
+            .field("din0_mode", &self.din0_mode())
+            .field("din1_mode", &self.din1_mode())
+            .field("din2_mode", &self.din2_mode())
+            .field("din3_mode", &self.din3_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 input delay mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIN_MODE_SPEC;
 impl crate::RegisterSpec for DIN_MODE_SPEC {
diff --git a/esp32c2/src/spi0/din_num.rs b/esp32c2/src/spi0/din_num.rs
index e39c3f721f..e17699dbdb 100644
--- a/esp32c2/src/spi0/din_num.rs
+++ b/esp32c2/src/spi0/din_num.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_NUM")
-            .field("din0_num", &format_args!("{}", self.din0_num().bit()))
-            .field("din1_num", &format_args!("{}", self.din1_num().bit()))
-            .field("din2_num", &format_args!("{}", self.din2_num().bit()))
-            .field("din3_num", &format_args!("{}", self.din3_num().bit()))
+            .field("din0_num", &self.din0_num())
+            .field("din1_num", &self.din1_num())
+            .field("din2_num", &self.din2_num())
+            .field("din3_num", &self.din3_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 input delay number control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din_num::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIN_NUM_SPEC;
 impl crate::RegisterSpec for DIN_NUM_SPEC {
diff --git a/esp32c2/src/spi0/dout_mode.rs b/esp32c2/src/spi0/dout_mode.rs
index 84067ce035..e14ebf7fbe 100644
--- a/esp32c2/src/spi0/dout_mode.rs
+++ b/esp32c2/src/spi0/dout_mode.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOUT_MODE")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bit()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bit()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bit()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bit()))
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 output delay mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dout_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DOUT_MODE_SPEC;
 impl crate::RegisterSpec for DOUT_MODE_SPEC {
diff --git a/esp32c2/src/spi0/fsm.rs b/esp32c2/src/spi0/fsm.rs
index 02d06cc456..95b6e02ace 100644
--- a/esp32c2/src/spi0/fsm.rs
+++ b/esp32c2/src/spi0/fsm.rs
@@ -31,21 +31,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM")
-            .field("cspi_st", &format_args!("{}", self.cspi_st().bits()))
-            .field("em_st", &format_args!("{}", self.em_st().bits()))
-            .field(
-                "cspi_lock_delay_time",
-                &format_args!("{}", self.cspi_lock_delay_time().bits()),
-            )
+            .field("cspi_st", &self.cspi_st())
+            .field("em_st", &self.em_st())
+            .field("cspi_lock_delay_time", &self.cspi_lock_delay_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 7:11 - The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1."]
     #[inline(always)]
diff --git a/esp32c2/src/spi0/misc.rs b/esp32c2/src/spi0/misc.rs
index 426bcd686a..e1ec9d4aa9 100644
--- a/esp32c2/src/spi0/misc.rs
+++ b/esp32c2/src/spi0/misc.rs
@@ -62,36 +62,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("trans_end", &format_args!("{}", self.trans_end().bit()))
-            .field(
-                "trans_end_int_ena",
-                &format_args!("{}", self.trans_end_int_ena().bit()),
-            )
-            .field(
-                "cspi_st_trans_end",
-                &format_args!("{}", self.cspi_st_trans_end().bit()),
-            )
+            .field("trans_end", &self.trans_end())
+            .field("trans_end_int_ena", &self.trans_end_int_ena())
+            .field("cspi_st_trans_end", &self.cspi_st_trans_end())
             .field(
                 "cspi_st_trans_end_int_ena",
-                &format_args!("{}", self.cspi_st_trans_end_int_ena().bit()),
-            )
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
+                &self.cspi_st_trans_end_int_ena(),
             )
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - The bit is used to indicate the spi0_mst_st controlled transmitting is done."]
     #[inline(always)]
diff --git a/esp32c2/src/spi0/rd_status.rs b/esp32c2/src/spi0/rd_status.rs
index f0916ef916..ce4af380ee 100644
--- a/esp32c2/src/spi0/rd_status.rs
+++ b/esp32c2/src/spi0/rd_status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_STATUS")
-            .field("wb_mode", &format_args!("{}", self.wb_mode().bits()))
+            .field("wb_mode", &self.wb_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:23 - Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit."]
     #[inline(always)]
diff --git a/esp32c2/src/spi0/timing_cali.rs b/esp32c2/src/spi0/timing_cali.rs
index 90a8a489e8..a366c973cd 100644
--- a/esp32c2/src/spi0/timing_cali.rs
+++ b/esp32c2/src/spi0/timing_cali.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMING_CALI")
-            .field(
-                "timing_clk_ena",
-                &format_args!("{}", self.timing_clk_ena().bit()),
-            )
-            .field("timing_cali", &format_args!("{}", self.timing_cali().bit()))
-            .field(
-                "extra_dummy_cyclelen",
-                &format_args!("{}", self.extra_dummy_cyclelen().bits()),
-            )
+            .field("timing_clk_ena", &self.timing_clk_ena())
+            .field("timing_cali", &self.timing_cali())
+            .field("extra_dummy_cyclelen", &self.extra_dummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 timing calibration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timing_cali::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMING_CALI_SPEC;
 impl crate::RegisterSpec for TIMING_CALI_SPEC {
diff --git a/esp32c2/src/spi0/user.rs b/esp32c2/src/spi0/user.rs
index 62c66529ef..3191631ea8 100644
--- a/esp32c2/src/spi0/user.rs
+++ b/esp32c2/src/spi0/user.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
-            .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
+            .field("cs_hold", &self.cs_hold())
+            .field("cs_setup", &self.cs_setup())
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_dummy", &self.usr_dummy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32c2/src/spi0/user1.rs b/esp32c2/src/spi0/user1.rs
index 3384bb8a56..88b12b4269 100644
--- a/esp32c2/src/spi0/user1.rs
+++ b/esp32c2/src/spi0/user1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
     #[inline(always)]
diff --git a/esp32c2/src/spi0/user2.rs b/esp32c2/src/spi0/user2.rs
index 801f605c21..d0bf1413f5 100644
--- a/esp32c2/src/spi0/user2.rs
+++ b/esp32c2/src/spi0/user2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/addr.rs b/esp32c2/src/spi1/addr.rs
index 565e7916d4..cc9a0e1b42 100644
--- a/esp32c2/src/spi1/addr.rs
+++ b/esp32c2/src/spi1/addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR")
-            .field(
-                "usr_addr_value",
-                &format_args!("{}", self.usr_addr_value().bits()),
-            )
+            .field("usr_addr_value", &self.usr_addr_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/cache_fctrl.rs b/esp32c2/src/spi1/cache_fctrl.rs
index c8eafade55..3a22f1f847 100644
--- a/esp32c2/src/spi1/cache_fctrl.rs
+++ b/esp32c2/src/spi1/cache_fctrl.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_FCTRL")
-            .field(
-                "cache_usr_addr_4byte",
-                &format_args!("{}", self.cache_usr_addr_4byte().bit()),
-            )
-            .field("fdin_dual", &format_args!("{}", self.fdin_dual().bit()))
-            .field("fdout_dual", &format_args!("{}", self.fdout_dual().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("fdin_quad", &format_args!("{}", self.fdin_quad().bit()))
-            .field("fdout_quad", &format_args!("{}", self.fdout_quad().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
+            .field("cache_usr_addr_4byte", &self.cache_usr_addr_4byte())
+            .field("fdin_dual", &self.fdin_dual())
+            .field("fdout_dual", &self.fdout_dual())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("fdin_quad", &self.fdin_quad())
+            .field("fdout_quad", &self.fdout_quad())
+            .field("faddr_quad", &self.faddr_quad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_FCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/clock.rs b/esp32c2/src/spi1/clock.rs
index 250a0c660f..ec805aad92 100644
--- a/esp32c2/src/spi1/clock.rs
+++ b/esp32c2/src/spi1/clock.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/clock_gate.rs b/esp32c2/src/spi1/clock_gate.rs
index c60d396767..69477e9842 100644
--- a/esp32c2/src/spi1/clock_gate.rs
+++ b/esp32c2/src/spi1/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/cmd.rs b/esp32c2/src/spi1/cmd.rs
index 31cc3b2e6b..2283088975 100644
--- a/esp32c2/src/spi1/cmd.rs
+++ b/esp32c2/src/spi1/cmd.rs
@@ -157,35 +157,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field(
-                "spi1_mst_st",
-                &format_args!("{}", self.spi1_mst_st().bits()),
-            )
-            .field("mspi_st", &format_args!("{}", self.mspi_st().bits()))
-            .field("flash_pe", &format_args!("{}", self.flash_pe().bit()))
-            .field("usr", &format_args!("{}", self.usr().bit()))
-            .field("flash_hpm", &format_args!("{}", self.flash_hpm().bit()))
-            .field("flash_res", &format_args!("{}", self.flash_res().bit()))
-            .field("flash_dp", &format_args!("{}", self.flash_dp().bit()))
-            .field("flash_ce", &format_args!("{}", self.flash_ce().bit()))
-            .field("flash_be", &format_args!("{}", self.flash_be().bit()))
-            .field("flash_se", &format_args!("{}", self.flash_se().bit()))
-            .field("flash_pp", &format_args!("{}", self.flash_pp().bit()))
-            .field("flash_wrsr", &format_args!("{}", self.flash_wrsr().bit()))
-            .field("flash_rdsr", &format_args!("{}", self.flash_rdsr().bit()))
-            .field("flash_rdid", &format_args!("{}", self.flash_rdid().bit()))
-            .field("flash_wrdi", &format_args!("{}", self.flash_wrdi().bit()))
-            .field("flash_wren", &format_args!("{}", self.flash_wren().bit()))
-            .field("flash_read", &format_args!("{}", self.flash_read().bit()))
+            .field("spi1_mst_st", &self.spi1_mst_st())
+            .field("mspi_st", &self.mspi_st())
+            .field("flash_pe", &self.flash_pe())
+            .field("usr", &self.usr())
+            .field("flash_hpm", &self.flash_hpm())
+            .field("flash_res", &self.flash_res())
+            .field("flash_dp", &self.flash_dp())
+            .field("flash_ce", &self.flash_ce())
+            .field("flash_be", &self.flash_be())
+            .field("flash_se", &self.flash_se())
+            .field("flash_pp", &self.flash_pp())
+            .field("flash_wrsr", &self.flash_wrsr())
+            .field("flash_rdsr", &self.flash_rdsr())
+            .field("flash_rdid", &self.flash_rdid())
+            .field("flash_wrdi", &self.flash_wrdi())
+            .field("flash_wren", &self.flash_wren())
+            .field("flash_read", &self.flash_read())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/ctrl.rs b/esp32c2/src/spi1/ctrl.rs
index 8d0aef82cb..6462c91847 100644
--- a/esp32c2/src/spi1/ctrl.rs
+++ b/esp32c2/src/spi1/ctrl.rs
@@ -143,30 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("fdummy_out", &format_args!("{}", self.fdummy_out().bit()))
-            .field("fcmd_dual", &format_args!("{}", self.fcmd_dual().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcs_crc_en", &format_args!("{}", self.fcs_crc_en().bit()))
-            .field("tx_crc_en", &format_args!("{}", self.tx_crc_en().bit()))
-            .field("fastrd_mode", &format_args!("{}", self.fastrd_mode().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("resandres", &format_args!("{}", self.resandres().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("wp", &format_args!("{}", self.wp().bit()))
-            .field("wrsr_2b", &format_args!("{}", self.wrsr_2b().bit()))
-            .field("fread_dio", &format_args!("{}", self.fread_dio().bit()))
-            .field("fread_qio", &format_args!("{}", self.fread_qio().bit()))
+            .field("fdummy_out", &self.fdummy_out())
+            .field("fcmd_dual", &self.fcmd_dual())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcs_crc_en", &self.fcs_crc_en())
+            .field("tx_crc_en", &self.tx_crc_en())
+            .field("fastrd_mode", &self.fastrd_mode())
+            .field("fread_dual", &self.fread_dual())
+            .field("resandres", &self.resandres())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("fread_quad", &self.fread_quad())
+            .field("wp", &self.wp())
+            .field("wrsr_2b", &self.wrsr_2b())
+            .field("fread_dio", &self.fread_dio())
+            .field("fread_qio", &self.fread_qio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - In the dummy phase the signal level of spi is output by the spi controller."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/ctrl1.rs b/esp32c2/src/spi1/ctrl1.rs
index 72546d185b..bde8ad35ad 100644
--- a/esp32c2/src/spi1/ctrl1.rs
+++ b/esp32c2/src/spi1/ctrl1.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL1")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
-            .field(
-                "cs_hold_dly_res",
-                &format_args!("{}", self.cs_hold_dly_res().bits()),
-            )
+            .field("clk_mode", &self.clk_mode())
+            .field("cs_hold_dly_res", &self.cs_hold_dly_res())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/date.rs b/esp32c2/src/spi1/date.rs
index fcc0e9959f..c67e2cee45 100644
--- a/esp32c2/src/spi1/date.rs
+++ b/esp32c2/src/spi1/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/spi1/flash_sus_cmd.rs b/esp32c2/src/spi1/flash_sus_cmd.rs
index 7efa867925..8fd24bd900 100644
--- a/esp32c2/src/spi1/flash_sus_cmd.rs
+++ b/esp32c2/src/spi1/flash_sus_cmd.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_SUS_CMD")
-            .field(
-                "flash_per_command",
-                &format_args!("{}", self.flash_per_command().bits()),
-            )
-            .field(
-                "flash_pes_command",
-                &format_args!("{}", self.flash_pes_command().bits()),
-            )
-            .field(
-                "wait_pesr_command",
-                &format_args!("{}", self.wait_pesr_command().bits()),
-            )
+            .field("flash_per_command", &self.flash_per_command())
+            .field("flash_pes_command", &self.flash_pes_command())
+            .field("wait_pesr_command", &self.wait_pesr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_SUS_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Program/Erase resume command."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/flash_sus_ctrl.rs b/esp32c2/src/spi1/flash_sus_ctrl.rs
index 187f971488..1f8d0298dd 100644
--- a/esp32c2/src/spi1/flash_sus_ctrl.rs
+++ b/esp32c2/src/spi1/flash_sus_ctrl.rs
@@ -107,44 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_SUS_CTRL")
-            .field("flash_per", &format_args!("{}", self.flash_per().bit()))
-            .field("flash_pes", &format_args!("{}", self.flash_pes().bit()))
-            .field(
-                "flash_per_wait_en",
-                &format_args!("{}", self.flash_per_wait_en().bit()),
-            )
-            .field(
-                "flash_pes_wait_en",
-                &format_args!("{}", self.flash_pes_wait_en().bit()),
-            )
-            .field("pes_per_en", &format_args!("{}", self.pes_per_en().bit()))
-            .field(
-                "flash_pes_en",
-                &format_args!("{}", self.flash_pes_en().bit()),
-            )
-            .field(
-                "pesr_end_msk",
-                &format_args!("{}", self.pesr_end_msk().bits()),
-            )
-            .field(
-                "spi_fmem_rd_sus_2b",
-                &format_args!("{}", self.spi_fmem_rd_sus_2b().bit()),
-            )
-            .field("per_end_en", &format_args!("{}", self.per_end_en().bit()))
-            .field("pes_end_en", &format_args!("{}", self.pes_end_en().bit()))
-            .field(
-                "sus_timeout_cnt",
-                &format_args!("{}", self.sus_timeout_cnt().bits()),
-            )
+            .field("flash_per", &self.flash_per())
+            .field("flash_pes", &self.flash_pes())
+            .field("flash_per_wait_en", &self.flash_per_wait_en())
+            .field("flash_pes_wait_en", &self.flash_pes_wait_en())
+            .field("pes_per_en", &self.pes_per_en())
+            .field("flash_pes_en", &self.flash_pes_en())
+            .field("pesr_end_msk", &self.pesr_end_msk())
+            .field("spi_fmem_rd_sus_2b", &self.spi_fmem_rd_sus_2b())
+            .field("per_end_en", &self.per_end_en())
+            .field("pes_end_en", &self.pes_end_en())
+            .field("sus_timeout_cnt", &self.sus_timeout_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_SUS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/flash_waiti_ctrl.rs b/esp32c2/src/spi1/flash_waiti_ctrl.rs
index 5c6c3680ad..9e16f840ea 100644
--- a/esp32c2/src/spi1/flash_waiti_ctrl.rs
+++ b/esp32c2/src/spi1/flash_waiti_ctrl.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_WAITI_CTRL")
-            .field("waiti_dummy", &format_args!("{}", self.waiti_dummy().bit()))
-            .field("waiti_cmd", &format_args!("{}", self.waiti_cmd().bits()))
-            .field(
-                "waiti_dummy_cyclelen",
-                &format_args!("{}", self.waiti_dummy_cyclelen().bits()),
-            )
+            .field("waiti_dummy", &self.waiti_dummy())
+            .field("waiti_cmd", &self.waiti_cmd())
+            .field("waiti_dummy_cyclelen", &self.waiti_dummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_WAITI_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - The dummy phase enable when wait flash idle (RDSR)"]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/int_ena.rs b/esp32c2/src/spi1/int_ena.rs
index 9929ac6eb0..e9c031c045 100644
--- a/esp32c2/src/spi1/int_ena.rs
+++ b/esp32c2/src/spi1/int_ena.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("wpe_end", &self.wpe_end())
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("brown_out", &self.brown_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for SPI_MEM_PER_END_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/int_raw.rs b/esp32c2/src/spi1/int_raw.rs
index ecdf8a942e..a7e2987559 100644
--- a/esp32c2/src/spi1/int_raw.rs
+++ b/esp32c2/src/spi1/int_raw.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("wpe_end", &self.wpe_end())
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("brown_out", &self.brown_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/int_st.rs b/esp32c2/src/spi1/int_st.rs
index bda638affd..b2ee3022fe 100644
--- a/esp32c2/src/spi1/int_st.rs
+++ b/esp32c2/src/spi1/int_st.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("wpe_end", &self.wpe_end())
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("brown_out", &self.brown_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c2/src/spi1/misc.rs b/esp32c2/src/spi1/misc.rs
index 980afa45ae..7c1f213c28 100644
--- a/esp32c2/src/spi1/misc.rs
+++ b/esp32c2/src/spi1/misc.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
-            .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/miso_dlen.rs b/esp32c2/src/spi1/miso_dlen.rs
index 737f493c8c..6813af19b3 100644
--- a/esp32c2/src/spi1/miso_dlen.rs
+++ b/esp32c2/src/spi1/miso_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISO_DLEN")
-            .field(
-                "usr_miso_dbitlen",
-                &format_args!("{}", self.usr_miso_dbitlen().bits()),
-            )
+            .field("usr_miso_dbitlen", &self.usr_miso_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISO_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The length in bits of read-data. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/mosi_dlen.rs b/esp32c2/src/spi1/mosi_dlen.rs
index b21b936f88..5cd5d155af 100644
--- a/esp32c2/src/spi1/mosi_dlen.rs
+++ b/esp32c2/src/spi1/mosi_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MOSI_DLEN")
-            .field(
-                "usr_mosi_dbitlen",
-                &format_args!("{}", self.usr_mosi_dbitlen().bits()),
-            )
+            .field("usr_mosi_dbitlen", &self.usr_mosi_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MOSI_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The length in bits of write-data. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/rd_status.rs b/esp32c2/src/spi1/rd_status.rs
index 6088e50d21..7368a19e92 100644
--- a/esp32c2/src/spi1/rd_status.rs
+++ b/esp32c2/src/spi1/rd_status.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_STATUS")
-            .field("status", &format_args!("{}", self.status().bits()))
-            .field("wb_mode", &format_args!("{}", self.wb_mode().bits()))
+            .field("status", &self.status())
+            .field("wb_mode", &self.wb_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/sus_status.rs b/esp32c2/src/spi1/sus_status.rs
index 07934fd36c..ad6e934807 100644
--- a/esp32c2/src/spi1/sus_status.rs
+++ b/esp32c2/src/spi1/sus_status.rs
@@ -80,44 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SUS_STATUS")
-            .field("flash_sus", &format_args!("{}", self.flash_sus().bit()))
-            .field(
-                "wait_pesr_cmd_2b",
-                &format_args!("{}", self.wait_pesr_cmd_2b().bit()),
-            )
-            .field(
-                "flash_hpm_dly_128",
-                &format_args!("{}", self.flash_hpm_dly_128().bit()),
-            )
-            .field(
-                "flash_res_dly_128",
-                &format_args!("{}", self.flash_res_dly_128().bit()),
-            )
-            .field(
-                "flash_dp_dly_128",
-                &format_args!("{}", self.flash_dp_dly_128().bit()),
-            )
-            .field(
-                "flash_per_dly_128",
-                &format_args!("{}", self.flash_per_dly_128().bit()),
-            )
-            .field(
-                "flash_pes_dly_128",
-                &format_args!("{}", self.flash_pes_dly_128().bit()),
-            )
-            .field(
-                "spi0_lock_en",
-                &format_args!("{}", self.spi0_lock_en().bit()),
-            )
+            .field("flash_sus", &self.flash_sus())
+            .field("wait_pesr_cmd_2b", &self.wait_pesr_cmd_2b())
+            .field("flash_hpm_dly_128", &self.flash_hpm_dly_128())
+            .field("flash_res_dly_128", &self.flash_res_dly_128())
+            .field("flash_dp_dly_128", &self.flash_dp_dly_128())
+            .field("flash_per_dly_128", &self.flash_per_dly_128())
+            .field("flash_pes_dly_128", &self.flash_pes_dly_128())
+            .field("spi0_lock_en", &self.spi0_lock_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SUS_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The status of flash suspend, only used in SPI1."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/timing_cali.rs b/esp32c2/src/spi1/timing_cali.rs
index 26d29adcb1..30cedb419e 100644
--- a/esp32c2/src/spi1/timing_cali.rs
+++ b/esp32c2/src/spi1/timing_cali.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMING_CALI")
-            .field("timing_cali", &format_args!("{}", self.timing_cali().bit()))
-            .field(
-                "extra_dummy_cyclelen",
-                &format_args!("{}", self.extra_dummy_cyclelen().bits()),
-            )
+            .field("timing_cali", &self.timing_cali())
+            .field("extra_dummy_cyclelen", &self.extra_dummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timing_cali::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMING_CALI_SPEC;
 impl crate::RegisterSpec for TIMING_CALI_SPEC {
diff --git a/esp32c2/src/spi1/tx_crc.rs b/esp32c2/src/spi1/tx_crc.rs
index 9faa1c440d..253fff1be1 100644
--- a/esp32c2/src/spi1/tx_crc.rs
+++ b/esp32c2/src/spi1/tx_crc.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 TX CRC data register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TX_CRC_SPEC;
 impl crate::RegisterSpec for TX_CRC_SPEC {
diff --git a/esp32c2/src/spi1/user.rs b/esp32c2/src/spi1/user.rs
index 66260b25e0..c53de90555 100644
--- a/esp32c2/src/spi1/user.rs
+++ b/esp32c2/src/spi1/user.rs
@@ -125,37 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
-            .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
-            .field("fwrite_dio", &format_args!("{}", self.fwrite_dio().bit()))
-            .field("fwrite_qio", &format_args!("{}", self.fwrite_qio().bit()))
-            .field(
-                "usr_miso_highpart",
-                &format_args!("{}", self.usr_miso_highpart().bit()),
-            )
-            .field(
-                "usr_mosi_highpart",
-                &format_args!("{}", self.usr_mosi_highpart().bit()),
-            )
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
-            .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
-            .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
-            .field("usr_command", &format_args!("{}", self.usr_command().bit()))
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("fwrite_dual", &self.fwrite_dual())
+            .field("fwrite_quad", &self.fwrite_quad())
+            .field("fwrite_dio", &self.fwrite_dio())
+            .field("fwrite_qio", &self.fwrite_qio())
+            .field("usr_miso_highpart", &self.usr_miso_highpart())
+            .field("usr_mosi_highpart", &self.usr_mosi_highpart())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_mosi", &self.usr_mosi())
+            .field("usr_miso", &self.usr_miso())
+            .field("usr_dummy", &self.usr_dummy())
+            .field("usr_addr", &self.usr_addr())
+            .field("usr_command", &self.usr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/user1.rs b/esp32c2/src/spi1/user1.rs
index 4b36bbf30d..8f28ca2ba4 100644
--- a/esp32c2/src/spi1/user1.rs
+++ b/esp32c2/src/spi1/user1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/user2.rs b/esp32c2/src/spi1/user2.rs
index 382c76224c..4bd67c802f 100644
--- a/esp32c2/src/spi1/user2.rs
+++ b/esp32c2/src/spi1/user2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command."]
     #[inline(always)]
diff --git a/esp32c2/src/spi1/w.rs b/esp32c2/src/spi1/w.rs
index 319a8e0611..43137019f7 100644
--- a/esp32c2/src/spi1/w.rs
+++ b/esp32c2/src/spi1/w.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("W")
-            .field("buf", &format_args!("{}", self.buf().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<W_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("W").field("buf", &self.buf()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/spi2/addr.rs b/esp32c2/src/spi2/addr.rs
index 0429f136d3..a43f100c19 100644
--- a/esp32c2/src/spi2/addr.rs
+++ b/esp32c2/src/spi2/addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR")
-            .field(
-                "usr_addr_value",
-                &format_args!("{}", self.usr_addr_value().bits()),
-            )
+            .field("usr_addr_value", &self.usr_addr_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Address to slave. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c2/src/spi2/clk_gate.rs b/esp32c2/src/spi2/clk_gate.rs
index c690702c68..c633026011 100644
--- a/esp32c2/src/spi2/clk_gate.rs
+++ b/esp32c2/src/spi2/clk_gate.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "mst_clk_active",
-                &format_args!("{}", self.mst_clk_active().bit()),
-            )
-            .field("mst_clk_sel", &format_args!("{}", self.mst_clk_sel().bit()))
+            .field("clk_en", &self.clk_en())
+            .field("mst_clk_active", &self.mst_clk_active())
+            .field("mst_clk_sel", &self.mst_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable clk gate"]
     #[inline(always)]
diff --git a/esp32c2/src/spi2/clock.rs b/esp32c2/src/spi2/clock.rs
index a980aa1ac0..336dc15885 100644
--- a/esp32c2/src/spi2/clock.rs
+++ b/esp32c2/src/spi2/clock.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field("clkdiv_pre", &format_args!("{}", self.clkdiv_pre().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clkdiv_pre", &self.clkdiv_pre())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c2/src/spi2/cmd.rs b/esp32c2/src/spi2/cmd.rs
index d9c54a966c..8d8333ec63 100644
--- a/esp32c2/src/spi2/cmd.rs
+++ b/esp32c2/src/spi2/cmd.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field(
-                "conf_bitlen",
-                &format_args!("{}", self.conf_bitlen().bits()),
-            )
-            .field("update", &format_args!("{}", self.update().bit()))
-            .field("usr", &format_args!("{}", self.usr().bit()))
+            .field("conf_bitlen", &self.conf_bitlen())
+            .field("update", &self.update())
+            .field("usr", &self.usr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - Define the APB cycles of SPI_CONF state. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c2/src/spi2/ctrl.rs b/esp32c2/src/spi2/ctrl.rs
index 13c41ae699..88e92d9320 100644
--- a/esp32c2/src/spi2/ctrl.rs
+++ b/esp32c2/src/spi2/ctrl.rs
@@ -146,37 +146,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("dummy_out", &format_args!("{}", self.dummy_out().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
-            .field("faddr_oct", &format_args!("{}", self.faddr_oct().bit()))
-            .field("fcmd_dual", &format_args!("{}", self.fcmd_dual().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcmd_oct", &format_args!("{}", self.fcmd_oct().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("fread_oct", &format_args!("{}", self.fread_oct().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("hold_pol", &format_args!("{}", self.hold_pol().bit()))
-            .field("wp_pol", &format_args!("{}", self.wp_pol().bit()))
-            .field(
-                "rd_bit_order",
-                &format_args!("{}", self.rd_bit_order().bits()),
-            )
-            .field(
-                "wr_bit_order",
-                &format_args!("{}", self.wr_bit_order().bits()),
-            )
+            .field("dummy_out", &self.dummy_out())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("faddr_quad", &self.faddr_quad())
+            .field("faddr_oct", &self.faddr_oct())
+            .field("fcmd_dual", &self.fcmd_dual())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcmd_oct", &self.fcmd_oct())
+            .field("fread_dual", &self.fread_dual())
+            .field("fread_quad", &self.fread_quad())
+            .field("fread_oct", &self.fread_oct())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("hold_pol", &self.hold_pol())
+            .field("wp_pol", &self.wp_pol())
+            .field("rd_bit_order", &self.rd_bit_order())
+            .field("wr_bit_order", &self.wr_bit_order())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c2/src/spi2/date.rs b/esp32c2/src/spi2/date.rs
index 68027aca25..43a2328d1a 100644
--- a/esp32c2/src/spi2/date.rs
+++ b/esp32c2/src/spi2/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/spi2/din_mode.rs b/esp32c2/src/spi2/din_mode.rs
index 47cdd78f7c..8a41474b12 100644
--- a/esp32c2/src/spi2/din_mode.rs
+++ b/esp32c2/src/spi2/din_mode.rs
@@ -69,27 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_MODE")
-            .field("din0_mode", &format_args!("{}", self.din0_mode().bits()))
-            .field("din1_mode", &format_args!("{}", self.din1_mode().bits()))
-            .field("din2_mode", &format_args!("{}", self.din2_mode().bits()))
-            .field("din3_mode", &format_args!("{}", self.din3_mode().bits()))
-            .field("din4_mode", &format_args!("{}", self.din4_mode().bits()))
-            .field("din5_mode", &format_args!("{}", self.din5_mode().bits()))
-            .field("din6_mode", &format_args!("{}", self.din6_mode().bits()))
-            .field("din7_mode", &format_args!("{}", self.din7_mode().bits()))
-            .field(
-                "timing_hclk_active",
-                &format_args!("{}", self.timing_hclk_active().bit()),
-            )
+            .field("din0_mode", &self.din0_mode())
+            .field("din1_mode", &self.din1_mode())
+            .field("din2_mode", &self.din2_mode())
+            .field("din3_mode", &self.din3_mode())
+            .field("din4_mode", &self.din4_mode())
+            .field("din5_mode", &self.din5_mode())
+            .field("din6_mode", &self.din6_mode())
+            .field("din7_mode", &self.din7_mode())
+            .field("timing_hclk_active", &self.timing_hclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI input delay mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIN_MODE_SPEC;
 impl crate::RegisterSpec for DIN_MODE_SPEC {
diff --git a/esp32c2/src/spi2/din_num.rs b/esp32c2/src/spi2/din_num.rs
index 96c0328186..e285c2bcb5 100644
--- a/esp32c2/src/spi2/din_num.rs
+++ b/esp32c2/src/spi2/din_num.rs
@@ -62,23 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_NUM")
-            .field("din0_num", &format_args!("{}", self.din0_num().bits()))
-            .field("din1_num", &format_args!("{}", self.din1_num().bits()))
-            .field("din2_num", &format_args!("{}", self.din2_num().bits()))
-            .field("din3_num", &format_args!("{}", self.din3_num().bits()))
-            .field("din4_num", &format_args!("{}", self.din4_num().bits()))
-            .field("din5_num", &format_args!("{}", self.din5_num().bits()))
-            .field("din6_num", &format_args!("{}", self.din6_num().bits()))
-            .field("din7_num", &format_args!("{}", self.din7_num().bits()))
+            .field("din0_num", &self.din0_num())
+            .field("din1_num", &self.din1_num())
+            .field("din2_num", &self.din2_num())
+            .field("din3_num", &self.din3_num())
+            .field("din4_num", &self.din4_num())
+            .field("din5_num", &self.din5_num())
+            .field("din6_num", &self.din6_num())
+            .field("din7_num", &self.din7_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI input delay number configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din_num::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIN_NUM_SPEC;
 impl crate::RegisterSpec for DIN_NUM_SPEC {
diff --git a/esp32c2/src/spi2/dma_conf.rs b/esp32c2/src/spi2/dma_conf.rs
index 2c8ad8198f..573e0e214e 100644
--- a/esp32c2/src/spi2/dma_conf.rs
+++ b/esp32c2/src/spi2/dma_conf.rs
@@ -82,38 +82,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field(
-                "dma_outfifo_empty",
-                &format_args!("{}", self.dma_outfifo_empty().bit()),
-            )
-            .field(
-                "dma_infifo_full",
-                &format_args!("{}", self.dma_infifo_full().bit()),
-            )
-            .field(
-                "dma_slv_seg_trans_en",
-                &format_args!("{}", self.dma_slv_seg_trans_en().bit()),
-            )
-            .field(
-                "slv_rx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_rx_seg_trans_clr_en().bit()),
-            )
-            .field(
-                "slv_tx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_tx_seg_trans_clr_en().bit()),
-            )
-            .field("rx_eof_en", &format_args!("{}", self.rx_eof_en().bit()))
-            .field("dma_rx_ena", &format_args!("{}", self.dma_rx_ena().bit()))
-            .field("dma_tx_ena", &format_args!("{}", self.dma_tx_ena().bit()))
+            .field("dma_outfifo_empty", &self.dma_outfifo_empty())
+            .field("dma_infifo_full", &self.dma_infifo_full())
+            .field("dma_slv_seg_trans_en", &self.dma_slv_seg_trans_en())
+            .field("slv_rx_seg_trans_clr_en", &self.slv_rx_seg_trans_clr_en())
+            .field("slv_tx_seg_trans_clr_en", &self.slv_tx_seg_trans_clr_en())
+            .field("rx_eof_en", &self.rx_eof_en())
+            .field("dma_rx_ena", &self.dma_rx_ena())
+            .field("dma_tx_ena", &self.dma_tx_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
     #[inline(always)]
diff --git a/esp32c2/src/spi2/dma_int_ena.rs b/esp32c2/src/spi2/dma_int_ena.rs
index 5a2520a556..57d74d21ae 100644
--- a/esp32c2/src/spi2/dma_int_ena.rs
+++ b/esp32c2/src/spi2/dma_int_ena.rs
@@ -197,69 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ENA")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c2/src/spi2/dma_int_raw.rs b/esp32c2/src/spi2/dma_int_raw.rs
index 4e27e4ae69..c8e69e9935 100644
--- a/esp32c2/src/spi2/dma_int_raw.rs
+++ b/esp32c2/src/spi2/dma_int_raw.rs
@@ -197,69 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_RAW")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."]
     #[inline(always)]
diff --git a/esp32c2/src/spi2/dma_int_st.rs b/esp32c2/src/spi2/dma_int_st.rs
index 424ec36870..5143fbdd5e 100644
--- a/esp32c2/src/spi2/dma_int_st.rs
+++ b/esp32c2/src/spi2/dma_int_st.rs
@@ -153,69 +153,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ST")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_INT_ST_SPEC;
 impl crate::RegisterSpec for DMA_INT_ST_SPEC {
diff --git a/esp32c2/src/spi2/dout_mode.rs b/esp32c2/src/spi2/dout_mode.rs
index e9d539211c..81c7f41a23 100644
--- a/esp32c2/src/spi2/dout_mode.rs
+++ b/esp32c2/src/spi2/dout_mode.rs
@@ -69,24 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOUT_MODE")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bit()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bit()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bit()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bit()))
-            .field("dout4_mode", &format_args!("{}", self.dout4_mode().bit()))
-            .field("dout5_mode", &format_args!("{}", self.dout5_mode().bit()))
-            .field("dout6_mode", &format_args!("{}", self.dout6_mode().bit()))
-            .field("dout7_mode", &format_args!("{}", self.dout7_mode().bit()))
-            .field("d_dqs_mode", &format_args!("{}", self.d_dqs_mode().bit()))
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
+            .field("dout4_mode", &self.dout4_mode())
+            .field("dout5_mode", &self.dout5_mode())
+            .field("dout6_mode", &self.dout6_mode())
+            .field("dout7_mode", &self.dout7_mode())
+            .field("d_dqs_mode", &self.d_dqs_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI output delay mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dout_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DOUT_MODE_SPEC;
 impl crate::RegisterSpec for DOUT_MODE_SPEC {
diff --git a/esp32c2/src/spi2/misc.rs b/esp32c2/src/spi2/misc.rs
index 1537a1ca6c..1a2a256246 100644
--- a/esp32c2/src/spi2/misc.rs
+++ b/esp32c2/src/spi2/misc.rs
@@ -151,53 +151,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
-            .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
-            .field("cs2_dis", &format_args!("{}", self.cs2_dis().bit()))
-            .field("cs3_dis", &format_args!("{}", self.cs3_dis().bit()))
-            .field("cs4_dis", &format_args!("{}", self.cs4_dis().bit()))
-            .field("cs5_dis", &format_args!("{}", self.cs5_dis().bit()))
-            .field("ck_dis", &format_args!("{}", self.ck_dis().bit()))
-            .field(
-                "master_cs_pol",
-                &format_args!("{}", self.master_cs_pol().bits()),
-            )
-            .field(
-                "clk_data_dtr_en",
-                &format_args!("{}", self.clk_data_dtr_en().bit()),
-            )
-            .field("data_dtr_en", &format_args!("{}", self.data_dtr_en().bit()))
-            .field("addr_dtr_en", &format_args!("{}", self.addr_dtr_en().bit()))
-            .field("cmd_dtr_en", &format_args!("{}", self.cmd_dtr_en().bit()))
-            .field(
-                "slave_cs_pol",
-                &format_args!("{}", self.slave_cs_pol().bit()),
-            )
-            .field(
-                "dqs_idle_edge",
-                &format_args!("{}", self.dqs_idle_edge().bit()),
-            )
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
-            .field(
-                "quad_din_pin_swap",
-                &format_args!("{}", self.quad_din_pin_swap().bit()),
-            )
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("cs2_dis", &self.cs2_dis())
+            .field("cs3_dis", &self.cs3_dis())
+            .field("cs4_dis", &self.cs4_dis())
+            .field("cs5_dis", &self.cs5_dis())
+            .field("ck_dis", &self.ck_dis())
+            .field("master_cs_pol", &self.master_cs_pol())
+            .field("clk_data_dtr_en", &self.clk_data_dtr_en())
+            .field("data_dtr_en", &self.data_dtr_en())
+            .field("addr_dtr_en", &self.addr_dtr_en())
+            .field("cmd_dtr_en", &self.cmd_dtr_en())
+            .field("slave_cs_pol", &self.slave_cs_pol())
+            .field("dqs_idle_edge", &self.dqs_idle_edge())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
+            .field("quad_din_pin_swap", &self.quad_din_pin_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c2/src/spi2/ms_dlen.rs b/esp32c2/src/spi2/ms_dlen.rs
index 116939582c..94a2915785 100644
--- a/esp32c2/src/spi2/ms_dlen.rs
+++ b/esp32c2/src/spi2/ms_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MS_DLEN")
-            .field(
-                "ms_data_bitlen",
-                &format_args!("{}", self.ms_data_bitlen().bits()),
-            )
+            .field("ms_data_bitlen", &self.ms_data_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MS_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c2/src/spi2/slave.rs b/esp32c2/src/spi2/slave.rs
index 2deadc74df..91a5b8108d 100644
--- a/esp32c2/src/spi2/slave.rs
+++ b/esp32c2/src/spi2/slave.rs
@@ -100,43 +100,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
-            .field("clk_mode_13", &format_args!("{}", self.clk_mode_13().bit()))
-            .field(
-                "rsck_data_out",
-                &format_args!("{}", self.rsck_data_out().bit()),
-            )
-            .field(
-                "slv_rddma_bitlen_en",
-                &format_args!("{}", self.slv_rddma_bitlen_en().bit()),
-            )
-            .field(
-                "slv_wrdma_bitlen_en",
-                &format_args!("{}", self.slv_wrdma_bitlen_en().bit()),
-            )
-            .field(
-                "slv_rdbuf_bitlen_en",
-                &format_args!("{}", self.slv_rdbuf_bitlen_en().bit()),
-            )
-            .field(
-                "slv_wrbuf_bitlen_en",
-                &format_args!("{}", self.slv_wrbuf_bitlen_en().bit()),
-            )
-            .field(
-                "dma_seg_magic_value",
-                &format_args!("{}", self.dma_seg_magic_value().bits()),
-            )
-            .field("mode", &format_args!("{}", self.mode().bit()))
-            .field("usr_conf", &format_args!("{}", self.usr_conf().bit()))
+            .field("clk_mode", &self.clk_mode())
+            .field("clk_mode_13", &self.clk_mode_13())
+            .field("rsck_data_out", &self.rsck_data_out())
+            .field("slv_rddma_bitlen_en", &self.slv_rddma_bitlen_en())
+            .field("slv_wrdma_bitlen_en", &self.slv_wrdma_bitlen_en())
+            .field("slv_rdbuf_bitlen_en", &self.slv_rdbuf_bitlen_en())
+            .field("slv_wrbuf_bitlen_en", &self.slv_wrbuf_bitlen_en())
+            .field("dma_seg_magic_value", &self.dma_seg_magic_value())
+            .field("mode", &self.mode())
+            .field("usr_conf", &self.usr_conf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c2/src/spi2/slave1.rs b/esp32c2/src/spi2/slave1.rs
index 7e216d9f86..98ad1b4b32 100644
--- a/esp32c2/src/spi2/slave1.rs
+++ b/esp32c2/src/spi2/slave1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE1")
-            .field(
-                "slv_data_bitlen",
-                &format_args!("{}", self.slv_data_bitlen().bits()),
-            )
-            .field(
-                "slv_last_command",
-                &format_args!("{}", self.slv_last_command().bits()),
-            )
-            .field(
-                "slv_last_addr",
-                &format_args!("{}", self.slv_last_addr().bits()),
-            )
+            .field("slv_data_bitlen", &self.slv_data_bitlen())
+            .field("slv_last_command", &self.slv_last_command())
+            .field("slv_last_addr", &self.slv_last_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - The transferred data bit length in SPI slave FD and HD mode."]
     #[inline(always)]
diff --git a/esp32c2/src/spi2/user.rs b/esp32c2/src/spi2/user.rs
index 61f673a063..e5405195fb 100644
--- a/esp32c2/src/spi2/user.rs
+++ b/esp32c2/src/spi2/user.rs
@@ -193,48 +193,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("doutdin", &format_args!("{}", self.doutdin().bit()))
-            .field("qpi_mode", &format_args!("{}", self.qpi_mode().bit()))
-            .field("opi_mode", &format_args!("{}", self.opi_mode().bit()))
-            .field("tsck_i_edge", &format_args!("{}", self.tsck_i_edge().bit()))
-            .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
-            .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
-            .field("rsck_i_edge", &format_args!("{}", self.rsck_i_edge().bit()))
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
-            .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
-            .field("fwrite_oct", &format_args!("{}", self.fwrite_oct().bit()))
-            .field(
-                "usr_conf_nxt",
-                &format_args!("{}", self.usr_conf_nxt().bit()),
-            )
-            .field("sio", &format_args!("{}", self.sio().bit()))
-            .field(
-                "usr_miso_highpart",
-                &format_args!("{}", self.usr_miso_highpart().bit()),
-            )
-            .field(
-                "usr_mosi_highpart",
-                &format_args!("{}", self.usr_mosi_highpart().bit()),
-            )
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
-            .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
-            .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
-            .field("usr_command", &format_args!("{}", self.usr_command().bit()))
+            .field("doutdin", &self.doutdin())
+            .field("qpi_mode", &self.qpi_mode())
+            .field("opi_mode", &self.opi_mode())
+            .field("tsck_i_edge", &self.tsck_i_edge())
+            .field("cs_hold", &self.cs_hold())
+            .field("cs_setup", &self.cs_setup())
+            .field("rsck_i_edge", &self.rsck_i_edge())
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("fwrite_dual", &self.fwrite_dual())
+            .field("fwrite_quad", &self.fwrite_quad())
+            .field("fwrite_oct", &self.fwrite_oct())
+            .field("usr_conf_nxt", &self.usr_conf_nxt())
+            .field("sio", &self.sio())
+            .field("usr_miso_highpart", &self.usr_miso_highpart())
+            .field("usr_mosi_highpart", &self.usr_mosi_highpart())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_mosi", &self.usr_mosi())
+            .field("usr_miso", &self.usr_miso())
+            .field("usr_dummy", &self.usr_dummy())
+            .field("usr_addr", &self.usr_addr())
+            .field("usr_command", &self.usr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c2/src/spi2/user1.rs b/esp32c2/src/spi2/user1.rs
index acb564ca07..1dd612d409 100644
--- a/esp32c2/src/spi2/user1.rs
+++ b/esp32c2/src/spi2/user1.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "mst_wfull_err_end_en",
-                &format_args!("{}", self.mst_wfull_err_end_en().bit()),
-            )
-            .field(
-                "cs_setup_time",
-                &format_args!("{}", self.cs_setup_time().bits()),
-            )
-            .field(
-                "cs_hold_time",
-                &format_args!("{}", self.cs_hold_time().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("mst_wfull_err_end_en", &self.mst_wfull_err_end_en())
+            .field("cs_setup_time", &self.cs_setup_time())
+            .field("cs_hold_time", &self.cs_hold_time())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c2/src/spi2/user2.rs b/esp32c2/src/spi2/user2.rs
index 065c536363..c2d5092cd2 100644
--- a/esp32c2/src/spi2/user2.rs
+++ b/esp32c2/src/spi2/user2.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "mst_rempty_err_end_en",
-                &format_args!("{}", self.mst_rempty_err_end_en().bit()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("mst_rempty_err_end_en", &self.mst_rempty_err_end_en())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c2/src/spi2/w.rs b/esp32c2/src/spi2/w.rs
index bd1588a6f2..016fb59d7c 100644
--- a/esp32c2/src/spi2/w.rs
+++ b/esp32c2/src/spi2/w.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("W")
-            .field("buf", &format_args!("{}", self.buf().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<W_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("W").field("buf", &self.buf()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/system/bt_lpck_div_frac.rs b/esp32c2/src/system/bt_lpck_div_frac.rs
index 33fe41cb99..113c21373e 100644
--- a/esp32c2/src/system/bt_lpck_div_frac.rs
+++ b/esp32c2/src/system/bt_lpck_div_frac.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_LPCK_DIV_FRAC")
-            .field(
-                "bt_lpck_div_b",
-                &format_args!("{}", self.bt_lpck_div_b().bits()),
-            )
-            .field(
-                "bt_lpck_div_a",
-                &format_args!("{}", self.bt_lpck_div_a().bits()),
-            )
-            .field(
-                "lpclk_sel_rtc_slow",
-                &format_args!("{}", self.lpclk_sel_rtc_slow().bit()),
-            )
-            .field(
-                "lpclk_sel_8m",
-                &format_args!("{}", self.lpclk_sel_8m().bit()),
-            )
-            .field(
-                "lpclk_sel_xtal",
-                &format_args!("{}", self.lpclk_sel_xtal().bit()),
-            )
-            .field(
-                "lpclk_sel_xtal32k",
-                &format_args!("{}", self.lpclk_sel_xtal32k().bit()),
-            )
-            .field(
-                "lpclk_rtc_en",
-                &format_args!("{}", self.lpclk_rtc_en().bit()),
-            )
+            .field("bt_lpck_div_b", &self.bt_lpck_div_b())
+            .field("bt_lpck_div_a", &self.bt_lpck_div_a())
+            .field("lpclk_sel_rtc_slow", &self.lpclk_sel_rtc_slow())
+            .field("lpclk_sel_8m", &self.lpclk_sel_8m())
+            .field("lpclk_sel_xtal", &self.lpclk_sel_xtal())
+            .field("lpclk_sel_xtal32k", &self.lpclk_sel_xtal32k())
+            .field("lpclk_rtc_en", &self.lpclk_rtc_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_LPCK_DIV_FRAC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - This field is lower power clock frequent division factor b"]
     #[inline(always)]
diff --git a/esp32c2/src/system/bt_lpck_div_int.rs b/esp32c2/src/system/bt_lpck_div_int.rs
index 42735c1a59..4bab9b33bf 100644
--- a/esp32c2/src/system/bt_lpck_div_int.rs
+++ b/esp32c2/src/system/bt_lpck_div_int.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_LPCK_DIV_INT")
-            .field(
-                "bt_lpck_div_num",
-                &format_args!("{}", self.bt_lpck_div_num().bits()),
-            )
+            .field("bt_lpck_div_num", &self.bt_lpck_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_LPCK_DIV_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - This field is lower power clock frequent division factor"]
     #[inline(always)]
diff --git a/esp32c2/src/system/cache_control.rs b/esp32c2/src/system/cache_control.rs
index 5d4247ea9c..42be63ff45 100644
--- a/esp32c2/src/system/cache_control.rs
+++ b/esp32c2/src/system/cache_control.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_CONTROL")
-            .field(
-                "icache_clk_on",
-                &format_args!("{}", self.icache_clk_on().bit()),
-            )
-            .field(
-                "icache_reset",
-                &format_args!("{}", self.icache_reset().bit()),
-            )
-            .field(
-                "dcache_clk_on",
-                &format_args!("{}", self.dcache_clk_on().bit()),
-            )
-            .field(
-                "dcache_reset",
-                &format_args!("{}", self.dcache_reset().bit()),
-            )
+            .field("icache_clk_on", &self.icache_clk_on())
+            .field("icache_reset", &self.icache_reset())
+            .field("dcache_clk_on", &self.dcache_clk_on())
+            .field("dcache_reset", &self.dcache_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable icache clock"]
     #[inline(always)]
diff --git a/esp32c2/src/system/clock_gate.rs b/esp32c2/src/system/clock_gate.rs
index 0ea9f4e7a3..0260550609 100644
--- a/esp32c2/src/system/clock_gate.rs
+++ b/esp32c2/src/system/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_clk_en"]
     #[inline(always)]
diff --git a/esp32c2/src/system/comb_pvt_err_hvt_site0.rs b/esp32c2/src/system/comb_pvt_err_hvt_site0.rs
index 3b0b5228b1..2e5426ed5e 100644
--- a/esp32c2/src/system/comb_pvt_err_hvt_site0.rs
+++ b/esp32c2/src/system/comb_pvt_err_hvt_site0.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_HVT_SITE0")
             .field(
                 "comb_timing_err_cnt_hvt_site0",
-                &format_args!("{}", self.comb_timing_err_cnt_hvt_site0().bits()),
+                &self.comb_timing_err_cnt_hvt_site0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_HVT_SITE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_hvt_site0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_HVT_SITE0_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE0_SPEC {
diff --git a/esp32c2/src/system/comb_pvt_err_hvt_site1.rs b/esp32c2/src/system/comb_pvt_err_hvt_site1.rs
index 283388ac5e..c21f017ecd 100644
--- a/esp32c2/src/system/comb_pvt_err_hvt_site1.rs
+++ b/esp32c2/src/system/comb_pvt_err_hvt_site1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_HVT_SITE1")
             .field(
                 "comb_timing_err_cnt_hvt_site1",
-                &format_args!("{}", self.comb_timing_err_cnt_hvt_site1().bits()),
+                &self.comb_timing_err_cnt_hvt_site1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_HVT_SITE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_hvt_site1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_HVT_SITE1_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE1_SPEC {
diff --git a/esp32c2/src/system/comb_pvt_err_hvt_site2.rs b/esp32c2/src/system/comb_pvt_err_hvt_site2.rs
index 390dd0be24..0f154a986d 100644
--- a/esp32c2/src/system/comb_pvt_err_hvt_site2.rs
+++ b/esp32c2/src/system/comb_pvt_err_hvt_site2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_HVT_SITE2")
             .field(
                 "comb_timing_err_cnt_hvt_site2",
-                &format_args!("{}", self.comb_timing_err_cnt_hvt_site2().bits()),
+                &self.comb_timing_err_cnt_hvt_site2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_HVT_SITE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_hvt_site2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_HVT_SITE2_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE2_SPEC {
diff --git a/esp32c2/src/system/comb_pvt_err_hvt_site3.rs b/esp32c2/src/system/comb_pvt_err_hvt_site3.rs
index 55535ac027..d9700c5a61 100644
--- a/esp32c2/src/system/comb_pvt_err_hvt_site3.rs
+++ b/esp32c2/src/system/comb_pvt_err_hvt_site3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_HVT_SITE3")
             .field(
                 "comb_timing_err_cnt_hvt_site3",
-                &format_args!("{}", self.comb_timing_err_cnt_hvt_site3().bits()),
+                &self.comb_timing_err_cnt_hvt_site3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_HVT_SITE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_hvt_site3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_HVT_SITE3_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE3_SPEC {
diff --git a/esp32c2/src/system/comb_pvt_err_lvt_site0.rs b/esp32c2/src/system/comb_pvt_err_lvt_site0.rs
index 30714d37de..2889b2742b 100644
--- a/esp32c2/src/system/comb_pvt_err_lvt_site0.rs
+++ b/esp32c2/src/system/comb_pvt_err_lvt_site0.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_LVT_SITE0")
             .field(
                 "comb_timing_err_cnt_lvt_site0",
-                &format_args!("{}", self.comb_timing_err_cnt_lvt_site0().bits()),
+                &self.comb_timing_err_cnt_lvt_site0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_LVT_SITE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_lvt_site0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_LVT_SITE0_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE0_SPEC {
diff --git a/esp32c2/src/system/comb_pvt_err_lvt_site1.rs b/esp32c2/src/system/comb_pvt_err_lvt_site1.rs
index fbf134e4fb..1410f1e2e7 100644
--- a/esp32c2/src/system/comb_pvt_err_lvt_site1.rs
+++ b/esp32c2/src/system/comb_pvt_err_lvt_site1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_LVT_SITE1")
             .field(
                 "comb_timing_err_cnt_lvt_site1",
-                &format_args!("{}", self.comb_timing_err_cnt_lvt_site1().bits()),
+                &self.comb_timing_err_cnt_lvt_site1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_LVT_SITE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_lvt_site1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_LVT_SITE1_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE1_SPEC {
diff --git a/esp32c2/src/system/comb_pvt_err_lvt_site2.rs b/esp32c2/src/system/comb_pvt_err_lvt_site2.rs
index 2372dc60c5..b9ed5bc385 100644
--- a/esp32c2/src/system/comb_pvt_err_lvt_site2.rs
+++ b/esp32c2/src/system/comb_pvt_err_lvt_site2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_LVT_SITE2")
             .field(
                 "comb_timing_err_cnt_lvt_site2",
-                &format_args!("{}", self.comb_timing_err_cnt_lvt_site2().bits()),
+                &self.comb_timing_err_cnt_lvt_site2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_LVT_SITE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_lvt_site2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_LVT_SITE2_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE2_SPEC {
diff --git a/esp32c2/src/system/comb_pvt_err_lvt_site3.rs b/esp32c2/src/system/comb_pvt_err_lvt_site3.rs
index 407766ecb2..c9f922eec2 100644
--- a/esp32c2/src/system/comb_pvt_err_lvt_site3.rs
+++ b/esp32c2/src/system/comb_pvt_err_lvt_site3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_LVT_SITE3")
             .field(
                 "comb_timing_err_cnt_lvt_site3",
-                &format_args!("{}", self.comb_timing_err_cnt_lvt_site3().bits()),
+                &self.comb_timing_err_cnt_lvt_site3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_LVT_SITE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_lvt_site3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_LVT_SITE3_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE3_SPEC {
diff --git a/esp32c2/src/system/comb_pvt_err_nvt_site0.rs b/esp32c2/src/system/comb_pvt_err_nvt_site0.rs
index 150832d2ef..b3895071a9 100644
--- a/esp32c2/src/system/comb_pvt_err_nvt_site0.rs
+++ b/esp32c2/src/system/comb_pvt_err_nvt_site0.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_NVT_SITE0")
             .field(
                 "comb_timing_err_cnt_nvt_site0",
-                &format_args!("{}", self.comb_timing_err_cnt_nvt_site0().bits()),
+                &self.comb_timing_err_cnt_nvt_site0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_NVT_SITE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_nvt_site0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_NVT_SITE0_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE0_SPEC {
diff --git a/esp32c2/src/system/comb_pvt_err_nvt_site1.rs b/esp32c2/src/system/comb_pvt_err_nvt_site1.rs
index 1485f3c151..25e3c41cec 100644
--- a/esp32c2/src/system/comb_pvt_err_nvt_site1.rs
+++ b/esp32c2/src/system/comb_pvt_err_nvt_site1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_NVT_SITE1")
             .field(
                 "comb_timing_err_cnt_nvt_site1",
-                &format_args!("{}", self.comb_timing_err_cnt_nvt_site1().bits()),
+                &self.comb_timing_err_cnt_nvt_site1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_NVT_SITE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_nvt_site1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_NVT_SITE1_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE1_SPEC {
diff --git a/esp32c2/src/system/comb_pvt_err_nvt_site2.rs b/esp32c2/src/system/comb_pvt_err_nvt_site2.rs
index 829924c30b..e741e1d1fb 100644
--- a/esp32c2/src/system/comb_pvt_err_nvt_site2.rs
+++ b/esp32c2/src/system/comb_pvt_err_nvt_site2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_NVT_SITE2")
             .field(
                 "comb_timing_err_cnt_nvt_site2",
-                &format_args!("{}", self.comb_timing_err_cnt_nvt_site2().bits()),
+                &self.comb_timing_err_cnt_nvt_site2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_NVT_SITE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_nvt_site2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_NVT_SITE2_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE2_SPEC {
diff --git a/esp32c2/src/system/comb_pvt_err_nvt_site3.rs b/esp32c2/src/system/comb_pvt_err_nvt_site3.rs
index 0a168d741b..2ee4f7571f 100644
--- a/esp32c2/src/system/comb_pvt_err_nvt_site3.rs
+++ b/esp32c2/src/system/comb_pvt_err_nvt_site3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_NVT_SITE3")
             .field(
                 "comb_timing_err_cnt_nvt_site3",
-                &format_args!("{}", self.comb_timing_err_cnt_nvt_site3().bits()),
+                &self.comb_timing_err_cnt_nvt_site3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_NVT_SITE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_nvt_site3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_NVT_SITE3_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE3_SPEC {
diff --git a/esp32c2/src/system/comb_pvt_hvt_conf.rs b/esp32c2/src/system/comb_pvt_hvt_conf.rs
index 6339be4d21..8d02a891e0 100644
--- a/esp32c2/src/system/comb_pvt_hvt_conf.rs
+++ b/esp32c2/src/system/comb_pvt_hvt_conf.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMB_PVT_HVT_CONF")
-            .field(
-                "comb_path_len_hvt",
-                &format_args!("{}", self.comb_path_len_hvt().bits()),
-            )
-            .field(
-                "comb_pvt_monitor_en_hvt",
-                &format_args!("{}", self.comb_pvt_monitor_en_hvt().bit()),
-            )
+            .field("comb_path_len_hvt", &self.comb_path_len_hvt())
+            .field("comb_pvt_monitor_en_hvt", &self.comb_pvt_monitor_en_hvt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_HVT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - reg_comb_path_len_hvt"]
     #[inline(always)]
diff --git a/esp32c2/src/system/comb_pvt_lvt_conf.rs b/esp32c2/src/system/comb_pvt_lvt_conf.rs
index 0ededa85b3..44af302bb9 100644
--- a/esp32c2/src/system/comb_pvt_lvt_conf.rs
+++ b/esp32c2/src/system/comb_pvt_lvt_conf.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMB_PVT_LVT_CONF")
-            .field(
-                "comb_path_len_lvt",
-                &format_args!("{}", self.comb_path_len_lvt().bits()),
-            )
-            .field(
-                "comb_pvt_monitor_en_lvt",
-                &format_args!("{}", self.comb_pvt_monitor_en_lvt().bit()),
-            )
+            .field("comb_path_len_lvt", &self.comb_path_len_lvt())
+            .field("comb_pvt_monitor_en_lvt", &self.comb_pvt_monitor_en_lvt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_LVT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - reg_comb_path_len_lvt"]
     #[inline(always)]
diff --git a/esp32c2/src/system/comb_pvt_nvt_conf.rs b/esp32c2/src/system/comb_pvt_nvt_conf.rs
index a1fbea424f..ab4db014e7 100644
--- a/esp32c2/src/system/comb_pvt_nvt_conf.rs
+++ b/esp32c2/src/system/comb_pvt_nvt_conf.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMB_PVT_NVT_CONF")
-            .field(
-                "comb_path_len_nvt",
-                &format_args!("{}", self.comb_path_len_nvt().bits()),
-            )
-            .field(
-                "comb_pvt_monitor_en_nvt",
-                &format_args!("{}", self.comb_pvt_monitor_en_nvt().bit()),
-            )
+            .field("comb_path_len_nvt", &self.comb_path_len_nvt())
+            .field("comb_pvt_monitor_en_nvt", &self.comb_pvt_monitor_en_nvt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_NVT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - reg_comb_path_len_nvt"]
     #[inline(always)]
diff --git a/esp32c2/src/system/cpu_intr_from_cpu_0.rs b/esp32c2/src/system/cpu_intr_from_cpu_0.rs
index 369b6934d1..7479dcf81b 100644
--- a/esp32c2/src/system/cpu_intr_from_cpu_0.rs
+++ b/esp32c2/src/system/cpu_intr_from_cpu_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_0")
-            .field(
-                "cpu_intr_from_cpu_0",
-                &format_args!("{}", self.cpu_intr_from_cpu_0().bit()),
-            )
+            .field("cpu_intr_from_cpu_0", &self.cpu_intr_from_cpu_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to generate cpu interrupt 0"]
     #[inline(always)]
diff --git a/esp32c2/src/system/cpu_intr_from_cpu_1.rs b/esp32c2/src/system/cpu_intr_from_cpu_1.rs
index df35a587b3..3ccd8760ff 100644
--- a/esp32c2/src/system/cpu_intr_from_cpu_1.rs
+++ b/esp32c2/src/system/cpu_intr_from_cpu_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_1")
-            .field(
-                "cpu_intr_from_cpu_1",
-                &format_args!("{}", self.cpu_intr_from_cpu_1().bit()),
-            )
+            .field("cpu_intr_from_cpu_1", &self.cpu_intr_from_cpu_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to generate cpu interrupt 1"]
     #[inline(always)]
diff --git a/esp32c2/src/system/cpu_intr_from_cpu_2.rs b/esp32c2/src/system/cpu_intr_from_cpu_2.rs
index cd35d7c8aa..5e05d69319 100644
--- a/esp32c2/src/system/cpu_intr_from_cpu_2.rs
+++ b/esp32c2/src/system/cpu_intr_from_cpu_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_2")
-            .field(
-                "cpu_intr_from_cpu_2",
-                &format_args!("{}", self.cpu_intr_from_cpu_2().bit()),
-            )
+            .field("cpu_intr_from_cpu_2", &self.cpu_intr_from_cpu_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to generate cpu interrupt 2"]
     #[inline(always)]
diff --git a/esp32c2/src/system/cpu_intr_from_cpu_3.rs b/esp32c2/src/system/cpu_intr_from_cpu_3.rs
index 5a5f616a56..662b2c510a 100644
--- a/esp32c2/src/system/cpu_intr_from_cpu_3.rs
+++ b/esp32c2/src/system/cpu_intr_from_cpu_3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_3")
-            .field(
-                "cpu_intr_from_cpu_3",
-                &format_args!("{}", self.cpu_intr_from_cpu_3().bit()),
-            )
+            .field("cpu_intr_from_cpu_3", &self.cpu_intr_from_cpu_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to generate cpu interrupt 3"]
     #[inline(always)]
diff --git a/esp32c2/src/system/cpu_per_conf.rs b/esp32c2/src/system/cpu_per_conf.rs
index f5048291aa..d1642a5796 100644
--- a/esp32c2/src/system/cpu_per_conf.rs
+++ b/esp32c2/src/system/cpu_per_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PER_CONF")
-            .field(
-                "cpuperiod_sel",
-                &format_args!("{}", self.cpuperiod_sel().bits()),
-            )
-            .field(
-                "pll_freq_sel",
-                &format_args!("{}", self.pll_freq_sel().bit()),
-            )
-            .field(
-                "cpu_wait_mode_force_on",
-                &format_args!("{}", self.cpu_wait_mode_force_on().bit()),
-            )
-            .field(
-                "cpu_waiti_delay_num",
-                &format_args!("{}", self.cpu_waiti_delay_num().bits()),
-            )
+            .field("cpuperiod_sel", &self.cpuperiod_sel())
+            .field("pll_freq_sel", &self.pll_freq_sel())
+            .field("cpu_wait_mode_force_on", &self.cpu_wait_mode_force_on())
+            .field("cpu_waiti_delay_num", &self.cpu_waiti_delay_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PER_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field used to sel cpu clock frequent."]
     #[inline(always)]
diff --git a/esp32c2/src/system/cpu_peri_clk_en.rs b/esp32c2/src/system/cpu_peri_clk_en.rs
index 91f5b806ff..0217c15c1d 100644
--- a/esp32c2/src/system/cpu_peri_clk_en.rs
+++ b/esp32c2/src/system/cpu_peri_clk_en.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERI_CLK_EN")
-            .field(
-                "clk_en_assist_debug",
-                &format_args!("{}", self.clk_en_assist_debug().bit()),
-            )
-            .field(
-                "clk_en_dedicated_gpio",
-                &format_args!("{}", self.clk_en_dedicated_gpio().bit()),
-            )
+            .field("clk_en_assist_debug", &self.clk_en_assist_debug())
+            .field("clk_en_dedicated_gpio", &self.clk_en_dedicated_gpio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - Set 1 to open assist_debug module clock"]
     #[inline(always)]
diff --git a/esp32c2/src/system/cpu_peri_rst_en.rs b/esp32c2/src/system/cpu_peri_rst_en.rs
index 9cc5f05b99..73004006fa 100644
--- a/esp32c2/src/system/cpu_peri_rst_en.rs
+++ b/esp32c2/src/system/cpu_peri_rst_en.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERI_RST_EN")
-            .field(
-                "rst_en_assist_debug",
-                &format_args!("{}", self.rst_en_assist_debug().bit()),
-            )
-            .field(
-                "rst_en_dedicated_gpio",
-                &format_args!("{}", self.rst_en_dedicated_gpio().bit()),
-            )
+            .field("rst_en_assist_debug", &self.rst_en_assist_debug())
+            .field("rst_en_dedicated_gpio", &self.rst_en_dedicated_gpio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_RST_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - Set 1 to let assist_debug module reset"]
     #[inline(always)]
diff --git a/esp32c2/src/system/edma_ctrl.rs b/esp32c2/src/system/edma_ctrl.rs
index 95dcf71a8c..8ce2aecabe 100644
--- a/esp32c2/src/system/edma_ctrl.rs
+++ b/esp32c2/src/system/edma_ctrl.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_CTRL")
-            .field("edma_clk_on", &format_args!("{}", self.edma_clk_on().bit()))
-            .field("edma_reset", &format_args!("{}", self.edma_reset().bit()))
+            .field("edma_clk_on", &self.edma_clk_on())
+            .field("edma_reset", &self.edma_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable EDMA clock."]
     #[inline(always)]
diff --git a/esp32c2/src/system/external_device_encrypt_decrypt_control.rs b/esp32c2/src/system/external_device_encrypt_decrypt_control.rs
index 534ecbbdb5..3c69248500 100644
--- a/esp32c2/src/system/external_device_encrypt_decrypt_control.rs
+++ b/esp32c2/src/system/external_device_encrypt_decrypt_control.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL")
             .field(
                 "enable_spi_manual_encrypt",
-                &format_args!("{}", self.enable_spi_manual_encrypt().bit()),
+                &self.enable_spi_manual_encrypt(),
             )
             .field(
                 "enable_download_db_encrypt",
-                &format_args!("{}", self.enable_download_db_encrypt().bit()),
+                &self.enable_download_db_encrypt(),
             )
             .field(
                 "enable_download_g0cb_decrypt",
-                &format_args!("{}", self.enable_download_g0cb_decrypt().bit()),
+                &self.enable_download_g0cb_decrypt(),
             )
             .field(
                 "enable_download_manual_encrypt",
-                &format_args!("{}", self.enable_download_manual_encrypt().bit()),
+                &self.enable_download_manual_encrypt(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable the SPI manual encrypt."]
     #[inline(always)]
diff --git a/esp32c2/src/system/mem_pd_mask.rs b/esp32c2/src/system/mem_pd_mask.rs
index 438d5d36d5..f442e16ef1 100644
--- a/esp32c2/src/system/mem_pd_mask.rs
+++ b/esp32c2/src/system/mem_pd_mask.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_PD_MASK")
-            .field(
-                "lslp_mem_pd_mask",
-                &format_args!("{}", self.lslp_mem_pd_mask().bit()),
-            )
+            .field("lslp_mem_pd_mask", &self.lslp_mem_pd_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_PD_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to mask memory power down."]
     #[inline(always)]
diff --git a/esp32c2/src/system/mem_pvt.rs b/esp32c2/src/system/mem_pvt.rs
index 8055e22279..fc047f3021 100644
--- a/esp32c2/src/system/mem_pvt.rs
+++ b/esp32c2/src/system/mem_pvt.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_PVT")
-            .field(
-                "mem_path_len",
-                &format_args!("{}", self.mem_path_len().bits()),
-            )
-            .field("monitor_en", &format_args!("{}", self.monitor_en().bit()))
-            .field(
-                "mem_timing_err_cnt",
-                &format_args!("{}", self.mem_timing_err_cnt().bits()),
-            )
-            .field("mem_vt_sel", &format_args!("{}", self.mem_vt_sel().bits()))
+            .field("mem_path_len", &self.mem_path_len())
+            .field("monitor_en", &self.monitor_en())
+            .field("mem_timing_err_cnt", &self.mem_timing_err_cnt())
+            .field("mem_vt_sel", &self.mem_vt_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_PVT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - reg_mem_path_len"]
     #[inline(always)]
diff --git a/esp32c2/src/system/perip_clk_en0.rs b/esp32c2/src/system/perip_clk_en0.rs
index 28638ec6a3..3d215ad440 100644
--- a/esp32c2/src/system/perip_clk_en0.rs
+++ b/esp32c2/src/system/perip_clk_en0.rs
@@ -107,50 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_CLK_EN0")
-            .field(
-                "spi01_clk_en",
-                &format_args!("{}", self.spi01_clk_en().bit()),
-            )
-            .field("uart_clk_en", &format_args!("{}", self.uart_clk_en().bit()))
-            .field(
-                "uart1_clk_en",
-                &format_args!("{}", self.uart1_clk_en().bit()),
-            )
-            .field("spi2_clk_en", &format_args!("{}", self.spi2_clk_en().bit()))
-            .field(
-                "i2c_ext0_clk_en",
-                &format_args!("{}", self.i2c_ext0_clk_en().bit()),
-            )
-            .field("ledc_clk_en", &format_args!("{}", self.ledc_clk_en().bit()))
-            .field(
-                "timergroup_clk_en",
-                &format_args!("{}", self.timergroup_clk_en().bit()),
-            )
-            .field(
-                "uart_mem_clk_en",
-                &format_args!("{}", self.uart_mem_clk_en().bit()),
-            )
-            .field(
-                "apb_saradc_clk_en",
-                &format_args!("{}", self.apb_saradc_clk_en().bit()),
-            )
-            .field(
-                "systimer_clk_en",
-                &format_args!("{}", self.systimer_clk_en().bit()),
-            )
-            .field(
-                "adc2_arb_clk_en",
-                &format_args!("{}", self.adc2_arb_clk_en().bit()),
-            )
+            .field("spi01_clk_en", &self.spi01_clk_en())
+            .field("uart_clk_en", &self.uart_clk_en())
+            .field("uart1_clk_en", &self.uart1_clk_en())
+            .field("spi2_clk_en", &self.spi2_clk_en())
+            .field("i2c_ext0_clk_en", &self.i2c_ext0_clk_en())
+            .field("ledc_clk_en", &self.ledc_clk_en())
+            .field("timergroup_clk_en", &self.timergroup_clk_en())
+            .field("uart_mem_clk_en", &self.uart_mem_clk_en())
+            .field("apb_saradc_clk_en", &self.apb_saradc_clk_en())
+            .field("systimer_clk_en", &self.systimer_clk_en())
+            .field("adc2_arb_clk_en", &self.adc2_arb_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_CLK_EN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set 1 to enable SPI01 clock"]
     #[inline(always)]
diff --git a/esp32c2/src/system/perip_clk_en1.rs b/esp32c2/src/system/perip_clk_en1.rs
index c8ce8fd935..ca80cd400a 100644
--- a/esp32c2/src/system/perip_clk_en1.rs
+++ b/esp32c2/src/system/perip_clk_en1.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_CLK_EN1")
-            .field(
-                "crypto_ecc_clk_en",
-                &format_args!("{}", self.crypto_ecc_clk_en().bit()),
-            )
-            .field(
-                "crypto_sha_clk_en",
-                &format_args!("{}", self.crypto_sha_clk_en().bit()),
-            )
-            .field("dma_clk_en", &format_args!("{}", self.dma_clk_en().bit()))
-            .field(
-                "tsens_clk_en",
-                &format_args!("{}", self.tsens_clk_en().bit()),
-            )
+            .field("crypto_ecc_clk_en", &self.crypto_ecc_clk_en())
+            .field("crypto_sha_clk_en", &self.crypto_sha_clk_en())
+            .field("dma_clk_en", &self.dma_clk_en())
+            .field("tsens_clk_en", &self.tsens_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_CLK_EN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set 1 to enable ECC clock"]
     #[inline(always)]
diff --git a/esp32c2/src/system/perip_rst_en0.rs b/esp32c2/src/system/perip_rst_en0.rs
index f1884d52c4..92347a14bf 100644
--- a/esp32c2/src/system/perip_rst_en0.rs
+++ b/esp32c2/src/system/perip_rst_en0.rs
@@ -107,44 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_RST_EN0")
-            .field("spi01_rst", &format_args!("{}", self.spi01_rst().bit()))
-            .field("uart_rst", &format_args!("{}", self.uart_rst().bit()))
-            .field("uart1_rst", &format_args!("{}", self.uart1_rst().bit()))
-            .field("spi2_rst", &format_args!("{}", self.spi2_rst().bit()))
-            .field(
-                "i2c_ext0_rst",
-                &format_args!("{}", self.i2c_ext0_rst().bit()),
-            )
-            .field("ledc_rst", &format_args!("{}", self.ledc_rst().bit()))
-            .field(
-                "timergroup_rst",
-                &format_args!("{}", self.timergroup_rst().bit()),
-            )
-            .field(
-                "uart_mem_rst",
-                &format_args!("{}", self.uart_mem_rst().bit()),
-            )
-            .field(
-                "apb_saradc_rst",
-                &format_args!("{}", self.apb_saradc_rst().bit()),
-            )
-            .field(
-                "systimer_rst",
-                &format_args!("{}", self.systimer_rst().bit()),
-            )
-            .field(
-                "adc2_arb_rst",
-                &format_args!("{}", self.adc2_arb_rst().bit()),
-            )
+            .field("spi01_rst", &self.spi01_rst())
+            .field("uart_rst", &self.uart_rst())
+            .field("uart1_rst", &self.uart1_rst())
+            .field("spi2_rst", &self.spi2_rst())
+            .field("i2c_ext0_rst", &self.i2c_ext0_rst())
+            .field("ledc_rst", &self.ledc_rst())
+            .field("timergroup_rst", &self.timergroup_rst())
+            .field("uart_mem_rst", &self.uart_mem_rst())
+            .field("apb_saradc_rst", &self.apb_saradc_rst())
+            .field("systimer_rst", &self.systimer_rst())
+            .field("adc2_arb_rst", &self.adc2_arb_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_RST_EN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set 1 to let SPI01 reset"]
     #[inline(always)]
diff --git a/esp32c2/src/system/perip_rst_en1.rs b/esp32c2/src/system/perip_rst_en1.rs
index c7d2e51744..240508eb68 100644
--- a/esp32c2/src/system/perip_rst_en1.rs
+++ b/esp32c2/src/system/perip_rst_en1.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_RST_EN1")
-            .field(
-                "crypto_ecc_rst",
-                &format_args!("{}", self.crypto_ecc_rst().bit()),
-            )
-            .field(
-                "crypto_sha_rst",
-                &format_args!("{}", self.crypto_sha_rst().bit()),
-            )
-            .field("dma_rst", &format_args!("{}", self.dma_rst().bit()))
-            .field("tsens_rst", &format_args!("{}", self.tsens_rst().bit()))
+            .field("crypto_ecc_rst", &self.crypto_ecc_rst())
+            .field("crypto_sha_rst", &self.crypto_sha_rst())
+            .field("dma_rst", &self.dma_rst())
+            .field("tsens_rst", &self.tsens_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_RST_EN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set 1 to let CRYPTO_ECC reset"]
     #[inline(always)]
diff --git a/esp32c2/src/system/redundant_eco_ctrl.rs b/esp32c2/src/system/redundant_eco_ctrl.rs
index f77b0357ec..0460bc2fe7 100644
--- a/esp32c2/src/system/redundant_eco_ctrl.rs
+++ b/esp32c2/src/system/redundant_eco_ctrl.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDUNDANT_ECO_CTRL")
-            .field(
-                "redundant_eco_drive",
-                &format_args!("{}", self.redundant_eco_drive().bit()),
-            )
-            .field(
-                "redundant_eco_result",
-                &format_args!("{}", self.redundant_eco_result().bit()),
-            )
+            .field("redundant_eco_drive", &self.redundant_eco_drive())
+            .field("redundant_eco_result", &self.redundant_eco_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDUNDANT_ECO_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_redundant_eco_drive"]
     #[inline(always)]
diff --git a/esp32c2/src/system/reg_date.rs b/esp32c2/src/system/reg_date.rs
index 4dc3887675..36db230347 100644
--- a/esp32c2/src/system/reg_date.rs
+++ b/esp32c2/src/system/reg_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_DATE")
-            .field(
-                "system_reg_date",
-                &format_args!("{}", self.system_reg_date().bits()),
-            )
+            .field("system_reg_date", &self.system_reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - reg_system_reg_date"]
     #[inline(always)]
diff --git a/esp32c2/src/system/rsa_pd_ctrl.rs b/esp32c2/src/system/rsa_pd_ctrl.rs
index a6f81238b4..ce95a6d340 100644
--- a/esp32c2/src/system/rsa_pd_ctrl.rs
+++ b/esp32c2/src/system/rsa_pd_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_PD_CTRL")
-            .field("rsa_mem_pd", &format_args!("{}", self.rsa_mem_pd().bit()))
-            .field(
-                "rsa_mem_force_pu",
-                &format_args!("{}", self.rsa_mem_force_pu().bit()),
-            )
-            .field(
-                "rsa_mem_force_pd",
-                &format_args!("{}", self.rsa_mem_force_pd().bit()),
-            )
+            .field("rsa_mem_pd", &self.rsa_mem_pd())
+            .field("rsa_mem_force_pu", &self.rsa_mem_force_pu())
+            .field("rsa_mem_force_pd", &self.rsa_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA. This bit is invalid."]
     #[inline(always)]
diff --git a/esp32c2/src/system/rtc_fastmem_config.rs b/esp32c2/src/system/rtc_fastmem_config.rs
index 7aa4ef3cc1..56535fbf75 100644
--- a/esp32c2/src/system/rtc_fastmem_config.rs
+++ b/esp32c2/src/system/rtc_fastmem_config.rs
@@ -42,31 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_FASTMEM_CONFIG")
-            .field(
-                "rtc_mem_crc_start",
-                &format_args!("{}", self.rtc_mem_crc_start().bit()),
-            )
-            .field(
-                "rtc_mem_crc_addr",
-                &format_args!("{}", self.rtc_mem_crc_addr().bits()),
-            )
-            .field(
-                "rtc_mem_crc_len",
-                &format_args!("{}", self.rtc_mem_crc_len().bits()),
-            )
-            .field(
-                "rtc_mem_crc_finish",
-                &format_args!("{}", self.rtc_mem_crc_finish().bit()),
-            )
+            .field("rtc_mem_crc_start", &self.rtc_mem_crc_start())
+            .field("rtc_mem_crc_addr", &self.rtc_mem_crc_addr())
+            .field("rtc_mem_crc_len", &self.rtc_mem_crc_len())
+            .field("rtc_mem_crc_finish", &self.rtc_mem_crc_finish())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_FASTMEM_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - Set 1 to start the CRC of RTC memory"]
     #[inline(always)]
diff --git a/esp32c2/src/system/rtc_fastmem_crc.rs b/esp32c2/src/system/rtc_fastmem_crc.rs
index 6bd1e22618..4b95f2add5 100644
--- a/esp32c2/src/system/rtc_fastmem_crc.rs
+++ b/esp32c2/src/system/rtc_fastmem_crc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_FASTMEM_CRC")
-            .field(
-                "rtc_mem_crc_res",
-                &format_args!("{}", self.rtc_mem_crc_res().bits()),
-            )
+            .field("rtc_mem_crc_res", &self.rtc_mem_crc_res())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_FASTMEM_CRC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_fastmem_crc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTC_FASTMEM_CRC_SPEC;
 impl crate::RegisterSpec for RTC_FASTMEM_CRC_SPEC {
diff --git a/esp32c2/src/system/sysclk_conf.rs b/esp32c2/src/system/sysclk_conf.rs
index def8785123..82382ca27e 100644
--- a/esp32c2/src/system/sysclk_conf.rs
+++ b/esp32c2/src/system/sysclk_conf.rs
@@ -40,28 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSCLK_CONF")
-            .field(
-                "pre_div_cnt",
-                &format_args!("{}", self.pre_div_cnt().bits()),
-            )
-            .field(
-                "soc_clk_sel",
-                &format_args!("{}", self.soc_clk_sel().bits()),
-            )
-            .field(
-                "clk_xtal_freq",
-                &format_args!("{}", self.clk_xtal_freq().bits()),
-            )
-            .field("clk_div_en", &format_args!("{}", self.clk_div_en().bit()))
+            .field("pre_div_cnt", &self.pre_div_cnt())
+            .field("soc_clk_sel", &self.soc_clk_sel())
+            .field("clk_xtal_freq", &self.clk_xtal_freq())
+            .field("clk_div_en", &self.clk_div_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This field is used to set the count of prescaler of XTAL_CLK."]
     #[inline(always)]
diff --git a/esp32c2/src/systimer/conf.rs b/esp32c2/src/systimer/conf.rs
index 40ff74a8b9..1111a16ca4 100644
--- a/esp32c2/src/systimer/conf.rs
+++ b/esp32c2/src/systimer/conf.rs
@@ -107,56 +107,32 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field(
-                "systimer_clk_fo",
-                &format_args!("{}", self.systimer_clk_fo().bit()),
-            )
-            .field(
-                "target2_work_en",
-                &format_args!("{}", self.target2_work_en().bit()),
-            )
-            .field(
-                "target1_work_en",
-                &format_args!("{}", self.target1_work_en().bit()),
-            )
-            .field(
-                "target0_work_en",
-                &format_args!("{}", self.target0_work_en().bit()),
-            )
+            .field("systimer_clk_fo", &self.systimer_clk_fo())
+            .field("target2_work_en", &self.target2_work_en())
+            .field("target1_work_en", &self.target1_work_en())
+            .field("target0_work_en", &self.target0_work_en())
             .field(
                 "timer_unit1_core1_stall_en",
-                &format_args!("{}", self.timer_unit1_core1_stall_en().bit()),
+                &self.timer_unit1_core1_stall_en(),
             )
             .field(
                 "timer_unit1_core0_stall_en",
-                &format_args!("{}", self.timer_unit1_core0_stall_en().bit()),
+                &self.timer_unit1_core0_stall_en(),
             )
             .field(
                 "timer_unit0_core1_stall_en",
-                &format_args!("{}", self.timer_unit0_core1_stall_en().bit()),
+                &self.timer_unit0_core1_stall_en(),
             )
             .field(
                 "timer_unit0_core0_stall_en",
-                &format_args!("{}", self.timer_unit0_core0_stall_en().bit()),
+                &self.timer_unit0_core0_stall_en(),
             )
-            .field(
-                "timer_unit1_work_en",
-                &format_args!("{}", self.timer_unit1_work_en().bit()),
-            )
-            .field(
-                "timer_unit0_work_en",
-                &format_args!("{}", self.timer_unit0_work_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("timer_unit1_work_en", &self.timer_unit1_work_en())
+            .field("timer_unit0_work_en", &self.timer_unit0_work_en())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - systimer clock force on"]
     #[inline(always)]
diff --git a/esp32c2/src/systimer/date.rs b/esp32c2/src/systimer/date.rs
index ac8c0009cc..2387e338ef 100644
--- a/esp32c2/src/systimer/date.rs
+++ b/esp32c2/src/systimer/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/systimer/int_ena.rs b/esp32c2/src/systimer/int_ena.rs
index 9afbd67324..bf39753584 100644
--- a/esp32c2/src/systimer/int_ena.rs
+++ b/esp32c2/src/systimer/int_ena.rs
@@ -42,18 +42,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "interupt(0-2) enable"]
     #[doc = ""]
diff --git a/esp32c2/src/systimer/int_raw.rs b/esp32c2/src/systimer/int_raw.rs
index 9487c30025..395cb8187f 100644
--- a/esp32c2/src/systimer/int_raw.rs
+++ b/esp32c2/src/systimer/int_raw.rs
@@ -42,18 +42,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "interupt(0-2) raw"]
     #[doc = ""]
diff --git a/esp32c2/src/systimer/int_st.rs b/esp32c2/src/systimer/int_st.rs
index 4c4d3c12f8..1dc503012b 100644
--- a/esp32c2/src/systimer/int_st.rs
+++ b/esp32c2/src/systimer/int_st.rs
@@ -38,18 +38,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "systimer interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c2/src/systimer/target_conf.rs b/esp32c2/src/systimer/target_conf.rs
index 351218e2ba..48184bd1f3 100644
--- a/esp32c2/src/systimer/target_conf.rs
+++ b/esp32c2/src/systimer/target_conf.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TARGET_CONF")
-            .field("period", &format_args!("{}", self.period().bits()))
-            .field("period_mode", &format_args!("{}", self.period_mode().bit()))
-            .field(
-                "timer_unit_sel",
-                &format_args!("{}", self.timer_unit_sel().bit()),
-            )
+            .field("period", &self.period())
+            .field("period_mode", &self.period_mode())
+            .field("timer_unit_sel", &self.timer_unit_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TARGET_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - target0 period"]
     #[inline(always)]
diff --git a/esp32c2/src/systimer/trgt/hi.rs b/esp32c2/src/systimer/trgt/hi.rs
index 9ba19aedd7..1bbcc8532f 100644
--- a/esp32c2/src/systimer/trgt/hi.rs
+++ b/esp32c2/src/systimer/trgt/hi.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/systimer/trgt/lo.rs b/esp32c2/src/systimer/trgt/lo.rs
index cf5618b115..870fcb7923 100644
--- a/esp32c2/src/systimer/trgt/lo.rs
+++ b/esp32c2/src/systimer/trgt/lo.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/systimer/unit_op.rs b/esp32c2/src/systimer/unit_op.rs
index 161504c169..5a004338a8 100644
--- a/esp32c2/src/systimer/unit_op.rs
+++ b/esp32c2/src/systimer/unit_op.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UNIT_OP")
-            .field("value_valid", &format_args!("{}", self.value_valid().bit()))
+            .field("value_valid", &self.value_valid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UNIT_OP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - update timer_unit0"]
     #[inline(always)]
diff --git a/esp32c2/src/systimer/unit_value/hi.rs b/esp32c2/src/systimer/unit_value/hi.rs
index 3cd25b4d55..10523f249f 100644
--- a/esp32c2/src/systimer/unit_value/hi.rs
+++ b/esp32c2/src/systimer/unit_value/hi.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HI")
-            .field("value_hi", &format_args!("{}", self.value_hi().bits()))
+            .field("value_hi", &self.value_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "system timer unit0 value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HI_SPEC;
 impl crate::RegisterSpec for HI_SPEC {
diff --git a/esp32c2/src/systimer/unit_value/lo.rs b/esp32c2/src/systimer/unit_value/lo.rs
index a60743963d..92c3f4e991 100644
--- a/esp32c2/src/systimer/unit_value/lo.rs
+++ b/esp32c2/src/systimer/unit_value/lo.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LO")
-            .field("value_lo", &format_args!("{}", self.value_lo().bits()))
+            .field("value_lo", &self.value_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "system timer unit0 value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LO_SPEC;
 impl crate::RegisterSpec for LO_SPEC {
diff --git a/esp32c2/src/systimer/unitload/hi.rs b/esp32c2/src/systimer/unitload/hi.rs
index 3d663b8225..a758293265 100644
--- a/esp32c2/src/systimer/unitload/hi.rs
+++ b/esp32c2/src/systimer/unitload/hi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - timer unit0 load high 20 bits"]
     #[inline(always)]
diff --git a/esp32c2/src/systimer/unitload/lo.rs b/esp32c2/src/systimer/unitload/lo.rs
index 15e267cf3c..e01c2efb83 100644
--- a/esp32c2/src/systimer/unitload/lo.rs
+++ b/esp32c2/src/systimer/unitload/lo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - timer unit0 load low 32 bits"]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/int_ena_timers.rs b/esp32c2/src/timg0/int_ena_timers.rs
index 8171c5599d..851aed4658 100644
--- a/esp32c2/src/timg0/int_ena_timers.rs
+++ b/esp32c2/src/timg0/int_ena_timers.rs
@@ -41,17 +41,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the TIMG_T(0-0)_INT interrupt."]
     #[doc = ""]
diff --git a/esp32c2/src/timg0/int_raw_timers.rs b/esp32c2/src/timg0/int_raw_timers.rs
index b0a2087cba..4774f3725d 100644
--- a/esp32c2/src/timg0/int_raw_timers.rs
+++ b/esp32c2/src/timg0/int_raw_timers.rs
@@ -35,17 +35,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_TIMERS_SPEC;
 impl crate::RegisterSpec for INT_RAW_TIMERS_SPEC {
diff --git a/esp32c2/src/timg0/int_st_timers.rs b/esp32c2/src/timg0/int_st_timers.rs
index f79f0e92cf..81866103ca 100644
--- a/esp32c2/src/timg0/int_st_timers.rs
+++ b/esp32c2/src/timg0/int_st_timers.rs
@@ -35,17 +35,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_TIMERS_SPEC;
 impl crate::RegisterSpec for INT_ST_TIMERS_SPEC {
diff --git a/esp32c2/src/timg0/ntimers_date.rs b/esp32c2/src/timg0/ntimers_date.rs
index dc19dc76f4..0d0942d7f3 100644
--- a/esp32c2/src/timg0/ntimers_date.rs
+++ b/esp32c2/src/timg0/ntimers_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NTIMERS_DATE")
-            .field(
-                "ntimgs_date",
-                &format_args!("{}", self.ntimgs_date().bits()),
-            )
+            .field("ntimgs_date", &self.ntimgs_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NTIMERS_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Timer version control register"]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/regclk.rs b/esp32c2/src/timg0/regclk.rs
index 88e1a03dda..174eb90ceb 100644
--- a/esp32c2/src/timg0/regclk.rs
+++ b/esp32c2/src/timg0/regclk.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGCLK")
-            .field(
-                "wdt_clk_is_active",
-                &format_args!("{}", self.wdt_clk_is_active().bit()),
-            )
-            .field(
-                "timer_clk_is_active",
-                &format_args!("{}", self.timer_clk_is_active().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("wdt_clk_is_active", &self.wdt_clk_is_active())
+            .field("timer_clk_is_active", &self.timer_clk_is_active())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 29 - enable WDT's clock"]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/rtccalicfg.rs b/esp32c2/src/timg0/rtccalicfg.rs
index 30d85ffe9d..6a8b0073df 100644
--- a/esp32c2/src/timg0/rtccalicfg.rs
+++ b/esp32c2/src/timg0/rtccalicfg.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG")
-            .field(
-                "rtc_cali_start_cycling",
-                &format_args!("{}", self.rtc_cali_start_cycling().bit()),
-            )
-            .field(
-                "rtc_cali_clk_sel",
-                &format_args!("{}", self.rtc_cali_clk_sel().bits()),
-            )
-            .field(
-                "rtc_cali_rdy",
-                &format_args!("{}", self.rtc_cali_rdy().bit()),
-            )
-            .field(
-                "rtc_cali_max",
-                &format_args!("{}", self.rtc_cali_max().bits()),
-            )
-            .field(
-                "rtc_cali_start",
-                &format_args!("{}", self.rtc_cali_start().bit()),
-            )
+            .field("rtc_cali_start_cycling", &self.rtc_cali_start_cycling())
+            .field("rtc_cali_clk_sel", &self.rtc_cali_clk_sel())
+            .field("rtc_cali_rdy", &self.rtc_cali_rdy())
+            .field("rtc_cali_max", &self.rtc_cali_max())
+            .field("rtc_cali_start", &self.rtc_cali_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Reserved"]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/rtccalicfg1.rs b/esp32c2/src/timg0/rtccalicfg1.rs
index ef581397c8..c5d12a9d71 100644
--- a/esp32c2/src/timg0/rtccalicfg1.rs
+++ b/esp32c2/src/timg0/rtccalicfg1.rs
@@ -22,21 +22,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("RTCCALICFG1")
             .field(
                 "rtc_cali_cycling_data_vld",
-                &format_args!("{}", self.rtc_cali_cycling_data_vld().bit()),
-            )
-            .field(
-                "rtc_cali_value",
-                &format_args!("{}", self.rtc_cali_value().bits()),
+                &self.rtc_cali_cycling_data_vld(),
             )
+            .field("rtc_cali_value", &self.rtc_cali_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC calibration configure1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtccalicfg1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTCCALICFG1_SPEC;
 impl crate::RegisterSpec for RTCCALICFG1_SPEC {
diff --git a/esp32c2/src/timg0/rtccalicfg2.rs b/esp32c2/src/timg0/rtccalicfg2.rs
index a0ea39a67b..2142857b29 100644
--- a/esp32c2/src/timg0/rtccalicfg2.rs
+++ b/esp32c2/src/timg0/rtccalicfg2.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG2")
-            .field(
-                "rtc_cali_timeout",
-                &format_args!("{}", self.rtc_cali_timeout().bit()),
-            )
-            .field(
-                "rtc_cali_timeout_rst_cnt",
-                &format_args!("{}", self.rtc_cali_timeout_rst_cnt().bits()),
-            )
-            .field(
-                "rtc_cali_timeout_thres",
-                &format_args!("{}", self.rtc_cali_timeout_thres().bits()),
-            )
+            .field("rtc_cali_timeout", &self.rtc_cali_timeout())
+            .field("rtc_cali_timeout_rst_cnt", &self.rtc_cali_timeout_rst_cnt())
+            .field("rtc_cali_timeout_thres", &self.rtc_cali_timeout_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:6 - Cycles that release calibration timeout reset"]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/t/alarmhi.rs b/esp32c2/src/timg0/t/alarmhi.rs
index edd0b2a2a2..fcba374986 100644
--- a/esp32c2/src/timg0/t/alarmhi.rs
+++ b/esp32c2/src/timg0/t/alarmhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMHI")
-            .field("alarm_hi", &format_args!("{}", self.alarm_hi().bits()))
+            .field("alarm_hi", &self.alarm_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Timer %s alarm trigger time-base counter value, high 22 bits."]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/t/alarmlo.rs b/esp32c2/src/timg0/t/alarmlo.rs
index 498db1e4af..49ecd50884 100644
--- a/esp32c2/src/timg0/t/alarmlo.rs
+++ b/esp32c2/src/timg0/t/alarmlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMLO")
-            .field("alarm_lo", &format_args!("{}", self.alarm_lo().bits()))
+            .field("alarm_lo", &self.alarm_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Timer %s alarm trigger time-base counter value, low 32 bits."]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/t/config.rs b/esp32c2/src/timg0/t/config.rs
index 4f94cffd85..498be19d87 100644
--- a/esp32c2/src/timg0/t/config.rs
+++ b/esp32c2/src/timg0/t/config.rs
@@ -64,21 +64,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG")
-            .field("use_xtal", &format_args!("{}", self.use_xtal().bit()))
-            .field("alarm_en", &format_args!("{}", self.alarm_en().bit()))
-            .field("divider", &format_args!("{}", self.divider().bits()))
-            .field("autoreload", &format_args!("{}", self.autoreload().bit()))
-            .field("increase", &format_args!("{}", self.increase().bit()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("use_xtal", &self.use_xtal())
+            .field("alarm_en", &self.alarm_en())
+            .field("divider", &self.divider())
+            .field("autoreload", &self.autoreload())
+            .field("increase", &self.increase())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/t/hi.rs b/esp32c2/src/timg0/t/hi.rs
index 0a24b62b63..7bf96de0ea 100644
--- a/esp32c2/src/timg0/t/hi.rs
+++ b/esp32c2/src/timg0/t/hi.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
     }
 }
 #[doc = "Timer %s current value, high 22 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c2/src/timg0/t/lo.rs b/esp32c2/src/timg0/t/lo.rs
index 973812bd12..40cb61bb7b 100644
--- a/esp32c2/src/timg0/t/lo.rs
+++ b/esp32c2/src/timg0/t/lo.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
     }
 }
 #[doc = "Timer %s current value, low 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c2/src/timg0/t/loadhi.rs b/esp32c2/src/timg0/t/loadhi.rs
index a069a77d70..14ce76e51c 100644
--- a/esp32c2/src/timg0/t/loadhi.rs
+++ b/esp32c2/src/timg0/t/loadhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADHI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - High 22 bits of the value that a reload will load onto timer %s time-base counter."]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/t/loadlo.rs b/esp32c2/src/timg0/t/loadlo.rs
index cd932cce0b..ed74e0c51d 100644
--- a/esp32c2/src/timg0/t/loadlo.rs
+++ b/esp32c2/src/timg0/t/loadlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADLO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Low 32 bits of the value that a reload will load onto timer %s time-base Counter."]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/t/update.rs b/esp32c2/src/timg0/t/update.rs
index dda84cfacc..bff3589c08 100644
--- a/esp32c2/src/timg0/t/update.rs
+++ b/esp32c2/src/timg0/t/update.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE")
-            .field("update", &format_args!("{}", self.update().bit()))
+            .field("update", &self.update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched."]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/wdtconfig0.rs b/esp32c2/src/timg0/wdtconfig0.rs
index 014e057348..49ca18cd2d 100644
--- a/esp32c2/src/timg0/wdtconfig0.rs
+++ b/esp32c2/src/timg0/wdtconfig0.rs
@@ -109,44 +109,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG0")
-            .field(
-                "wdt_appcpu_reset_en",
-                &format_args!("{}", self.wdt_appcpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field(
-                "wdt_use_xtal",
-                &format_args!("{}", self.wdt_use_xtal().bit()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_use_xtal", &self.wdt_use_xtal())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - WDT reset CPU enable."]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/wdtconfig1.rs b/esp32c2/src/timg0/wdtconfig1.rs
index 29740ede70..225f2e7355 100644
--- a/esp32c2/src/timg0/wdtconfig1.rs
+++ b/esp32c2/src/timg0/wdtconfig1.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG1")
-            .field(
-                "wdt_clk_prescale",
-                &format_args!("{}", self.wdt_clk_prescale().bits()),
-            )
+            .field("wdt_clk_prescale", &self.wdt_clk_prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, WDT 's clock divider counter will be reset."]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/wdtconfig2.rs b/esp32c2/src/timg0/wdtconfig2.rs
index f6646544fa..70947ea581 100644
--- a/esp32c2/src/timg0/wdtconfig2.rs
+++ b/esp32c2/src/timg0/wdtconfig2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG2")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 0 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/wdtconfig3.rs b/esp32c2/src/timg0/wdtconfig3.rs
index da0cf49ce2..63b4ed60f6 100644
--- a/esp32c2/src/timg0/wdtconfig3.rs
+++ b/esp32c2/src/timg0/wdtconfig3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG3")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 1 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/wdtconfig4.rs b/esp32c2/src/timg0/wdtconfig4.rs
index 2bbbc5bfe8..d132842f1f 100644
--- a/esp32c2/src/timg0/wdtconfig4.rs
+++ b/esp32c2/src/timg0/wdtconfig4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG4")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 2 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/wdtconfig5.rs b/esp32c2/src/timg0/wdtconfig5.rs
index 661482c54b..d101561533 100644
--- a/esp32c2/src/timg0/wdtconfig5.rs
+++ b/esp32c2/src/timg0/wdtconfig5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG5")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 3 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32c2/src/timg0/wdtwprotect.rs b/esp32c2/src/timg0/wdtwprotect.rs
index 44efc107f3..ca73442322 100644
--- a/esp32c2/src/timg0/wdtwprotect.rs
+++ b/esp32c2/src/timg0/wdtwprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTWPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTWPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - If the register contains a different value than its reset value, write protection is enabled."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/at_cmd_char.rs b/esp32c2/src/uart0/at_cmd_char.rs
index 17e9222fe8..e75e1409cd 100644
--- a/esp32c2/src/uart0/at_cmd_char.rs
+++ b/esp32c2/src/uart0/at_cmd_char.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_CHAR")
-            .field(
-                "at_cmd_char",
-                &format_args!("{}", self.at_cmd_char().bits()),
-            )
-            .field("char_num", &format_args!("{}", self.char_num().bits()))
+            .field("at_cmd_char", &self.at_cmd_char())
+            .field("char_num", &self.char_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_CHAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/at_cmd_gaptout.rs b/esp32c2/src/uart0/at_cmd_gaptout.rs
index c7373436b0..7091ac8125 100644
--- a/esp32c2/src/uart0/at_cmd_gaptout.rs
+++ b/esp32c2/src/uart0/at_cmd_gaptout.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_GAPTOUT")
-            .field(
-                "rx_gap_tout",
-                &format_args!("{}", self.rx_gap_tout().bits()),
-            )
+            .field("rx_gap_tout", &self.rx_gap_tout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_GAPTOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the at_cmd chars."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/at_cmd_postcnt.rs b/esp32c2/src/uart0/at_cmd_postcnt.rs
index 078c4bb6a1..5db8445554 100644
--- a/esp32c2/src/uart0/at_cmd_postcnt.rs
+++ b/esp32c2/src/uart0/at_cmd_postcnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_POSTCNT")
-            .field(
-                "post_idle_num",
-                &format_args!("{}", self.post_idle_num().bits()),
-            )
+            .field("post_idle_num", &self.post_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_POSTCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the last at_cmd and the next data."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/at_cmd_precnt.rs b/esp32c2/src/uart0/at_cmd_precnt.rs
index 9e4a1cc58c..41790b5e67 100644
--- a/esp32c2/src/uart0/at_cmd_precnt.rs
+++ b/esp32c2/src/uart0/at_cmd_precnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_PRECNT")
-            .field(
-                "pre_idle_num",
-                &format_args!("{}", self.pre_idle_num().bits()),
-            )
+            .field("pre_idle_num", &self.pre_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_PRECNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first at_cmd is received by receiver."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/clk_conf.rs b/esp32c2/src/uart0/clk_conf.rs
index 0ddb29638f..9f3c3a3eb2 100644
--- a/esp32c2/src/uart0/clk_conf.rs
+++ b/esp32c2/src/uart0/clk_conf.rs
@@ -98,28 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bits()))
-            .field("sclk_en", &format_args!("{}", self.sclk_en().bit()))
-            .field("rst_core", &format_args!("{}", self.rst_core().bit()))
-            .field("tx_sclk_en", &format_args!("{}", self.tx_sclk_en().bit()))
-            .field("rx_sclk_en", &format_args!("{}", self.rx_sclk_en().bit()))
-            .field("tx_rst_core", &format_args!("{}", self.tx_rst_core().bit()))
-            .field("rx_rst_core", &format_args!("{}", self.rx_rst_core().bit()))
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_en", &self.sclk_en())
+            .field("rst_core", &self.rst_core())
+            .field("tx_sclk_en", &self.tx_sclk_en())
+            .field("rx_sclk_en", &self.rx_sclk_en())
+            .field("tx_rst_core", &self.tx_rst_core())
+            .field("rx_rst_core", &self.rx_rst_core())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/clkdiv.rs b/esp32c2/src/uart0/clkdiv.rs
index c020543f66..0c1138e013 100644
--- a/esp32c2/src/uart0/clkdiv.rs
+++ b/esp32c2/src/uart0/clkdiv.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKDIV")
-            .field("clkdiv", &format_args!("{}", self.clkdiv().bits()))
-            .field("frag", &format_args!("{}", self.frag().bits()))
+            .field("clkdiv", &self.clkdiv())
+            .field("frag", &self.frag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKDIV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/conf0.rs b/esp32c2/src/uart0/conf0.rs
index a2981cbdc7..880c32a12e 100644
--- a/esp32c2/src/uart0/conf0.rs
+++ b/esp32c2/src/uart0/conf0.rs
@@ -251,45 +251,36 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("parity", &format_args!("{}", self.parity().bit()))
-            .field("parity_en", &format_args!("{}", self.parity_en().bit()))
-            .field("bit_num", &format_args!("{}", self.bit_num().bits()))
-            .field(
-                "stop_bit_num",
-                &format_args!("{}", self.stop_bit_num().bits()),
-            )
-            .field("sw_rts", &format_args!("{}", self.sw_rts().bit()))
-            .field("sw_dtr", &format_args!("{}", self.sw_dtr().bit()))
-            .field("txd_brk", &format_args!("{}", self.txd_brk().bit()))
-            .field("irda_dplx", &format_args!("{}", self.irda_dplx().bit()))
-            .field("irda_tx_en", &format_args!("{}", self.irda_tx_en().bit()))
-            .field("irda_wctl", &format_args!("{}", self.irda_wctl().bit()))
-            .field("irda_tx_inv", &format_args!("{}", self.irda_tx_inv().bit()))
-            .field("irda_rx_inv", &format_args!("{}", self.irda_rx_inv().bit()))
-            .field("loopback", &format_args!("{}", self.loopback().bit()))
-            .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit()))
-            .field("irda_en", &format_args!("{}", self.irda_en().bit()))
-            .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit()))
-            .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit()))
-            .field("rxd_inv", &format_args!("{}", self.rxd_inv().bit()))
-            .field("cts_inv", &format_args!("{}", self.cts_inv().bit()))
-            .field("dsr_inv", &format_args!("{}", self.dsr_inv().bit()))
-            .field("txd_inv", &format_args!("{}", self.txd_inv().bit()))
-            .field("rts_inv", &format_args!("{}", self.rts_inv().bit()))
-            .field("dtr_inv", &format_args!("{}", self.dtr_inv().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("err_wr_mask", &format_args!("{}", self.err_wr_mask().bit()))
-            .field("autobaud_en", &format_args!("{}", self.autobaud_en().bit()))
-            .field("mem_clk_en", &format_args!("{}", self.mem_clk_en().bit()))
+            .field("parity", &self.parity())
+            .field("parity_en", &self.parity_en())
+            .field("bit_num", &self.bit_num())
+            .field("stop_bit_num", &self.stop_bit_num())
+            .field("sw_rts", &self.sw_rts())
+            .field("sw_dtr", &self.sw_dtr())
+            .field("txd_brk", &self.txd_brk())
+            .field("irda_dplx", &self.irda_dplx())
+            .field("irda_tx_en", &self.irda_tx_en())
+            .field("irda_wctl", &self.irda_wctl())
+            .field("irda_tx_inv", &self.irda_tx_inv())
+            .field("irda_rx_inv", &self.irda_rx_inv())
+            .field("loopback", &self.loopback())
+            .field("tx_flow_en", &self.tx_flow_en())
+            .field("irda_en", &self.irda_en())
+            .field("rxfifo_rst", &self.rxfifo_rst())
+            .field("txfifo_rst", &self.txfifo_rst())
+            .field("rxd_inv", &self.rxd_inv())
+            .field("cts_inv", &self.cts_inv())
+            .field("dsr_inv", &self.dsr_inv())
+            .field("txd_inv", &self.txd_inv())
+            .field("rts_inv", &self.rts_inv())
+            .field("dtr_inv", &self.dtr_inv())
+            .field("clk_en", &self.clk_en())
+            .field("err_wr_mask", &self.err_wr_mask())
+            .field("autobaud_en", &self.autobaud_en())
+            .field("mem_clk_en", &self.mem_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to configure the parity check mode."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/conf1.rs b/esp32c2/src/uart0/conf1.rs
index b0b2648ed1..e255d104f4 100644
--- a/esp32c2/src/uart0/conf1.rs
+++ b/esp32c2/src/uart0/conf1.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "rxfifo_full_thrhd",
-                &format_args!("{}", self.rxfifo_full_thrhd().bits()),
-            )
-            .field(
-                "txfifo_empty_thrhd",
-                &format_args!("{}", self.txfifo_empty_thrhd().bits()),
-            )
-            .field(
-                "dis_rx_dat_ovf",
-                &format_args!("{}", self.dis_rx_dat_ovf().bit()),
-            )
-            .field(
-                "rx_tout_flow_dis",
-                &format_args!("{}", self.rx_tout_flow_dis().bit()),
-            )
-            .field("rx_flow_en", &format_args!("{}", self.rx_flow_en().bit()))
-            .field("rx_tout_en", &format_args!("{}", self.rx_tout_en().bit()))
+            .field("rxfifo_full_thrhd", &self.rxfifo_full_thrhd())
+            .field("txfifo_empty_thrhd", &self.txfifo_empty_thrhd())
+            .field("dis_rx_dat_ovf", &self.dis_rx_dat_ovf())
+            .field("rx_tout_flow_dis", &self.rx_tout_flow_dis())
+            .field("rx_flow_en", &self.rx_flow_en())
+            .field("rx_tout_en", &self.rx_tout_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/date.rs b/esp32c2/src/uart0/date.rs
index 816469bbff..ac4c156a82 100644
--- a/esp32c2/src/uart0/date.rs
+++ b/esp32c2/src/uart0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/uart0/fifo.rs b/esp32c2/src/uart0/fifo.rs
index 3ea719e7ab..fdc9ee6700 100644
--- a/esp32c2/src/uart0/fifo.rs
+++ b/esp32c2/src/uart0/fifo.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO")
-            .field(
-                "rxfifo_rd_byte",
-                &format_args!("{}", self.rxfifo_rd_byte().bits()),
-            )
+            .field("rxfifo_rd_byte", &self.rxfifo_rd_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - UART 0 accesses FIFO via this register."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/flow_conf.rs b/esp32c2/src/uart0/flow_conf.rs
index f20cf9572e..215821f1b6 100644
--- a/esp32c2/src/uart0/flow_conf.rs
+++ b/esp32c2/src/uart0/flow_conf.rs
@@ -62,24 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLOW_CONF")
-            .field(
-                "sw_flow_con_en",
-                &format_args!("{}", self.sw_flow_con_en().bit()),
-            )
-            .field("xonoff_del", &format_args!("{}", self.xonoff_del().bit()))
-            .field("force_xon", &format_args!("{}", self.force_xon().bit()))
-            .field("force_xoff", &format_args!("{}", self.force_xoff().bit()))
-            .field("send_xon", &format_args!("{}", self.send_xon().bit()))
-            .field("send_xoff", &format_args!("{}", self.send_xoff().bit()))
+            .field("sw_flow_con_en", &self.sw_flow_con_en())
+            .field("xonoff_del", &self.xonoff_del())
+            .field("force_xon", &self.force_xon())
+            .field("force_xoff", &self.force_xoff())
+            .field("send_xon", &self.send_xon())
+            .field("send_xoff", &self.send_xoff())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLOW_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/fsm_status.rs b/esp32c2/src/uart0/fsm_status.rs
index 7e47b06bf6..4088ac153f 100644
--- a/esp32c2/src/uart0/fsm_status.rs
+++ b/esp32c2/src/uart0/fsm_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_STATUS")
-            .field("st_urx_out", &format_args!("{}", self.st_urx_out().bits()))
-            .field("st_utx_out", &format_args!("{}", self.st_utx_out().bits()))
+            .field("st_urx_out", &self.st_urx_out())
+            .field("st_utx_out", &self.st_utx_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART transmit and receive status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FSM_STATUS_SPEC;
 impl crate::RegisterSpec for FSM_STATUS_SPEC {
diff --git a/esp32c2/src/uart0/highpulse.rs b/esp32c2/src/uart0/highpulse.rs
index 2a100f783a..8445906dbf 100644
--- a/esp32c2/src/uart0/highpulse.rs
+++ b/esp32c2/src/uart0/highpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIGHPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIGHPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud minimum high pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`highpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIGHPULSE_SPEC;
 impl crate::RegisterSpec for HIGHPULSE_SPEC {
diff --git a/esp32c2/src/uart0/id.rs b/esp32c2/src/uart0/id.rs
index a379a1b045..d398acf67f 100644
--- a/esp32c2/src/uart0/id.rs
+++ b/esp32c2/src/uart0/id.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ID")
-            .field("id", &format_args!("{}", self.id().bits()))
-            .field("high_speed", &format_args!("{}", self.high_speed().bit()))
-            .field("reg_update", &format_args!("{}", self.reg_update().bit()))
+            .field("id", &self.id())
+            .field("high_speed", &self.high_speed())
+            .field("reg_update", &self.reg_update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - This register is used to configure the uart_id."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/idle_conf.rs b/esp32c2/src/uart0/idle_conf.rs
index bc986732bf..a2f200e19e 100644
--- a/esp32c2/src/uart0/idle_conf.rs
+++ b/esp32c2/src/uart0/idle_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDLE_CONF")
-            .field(
-                "rx_idle_thrhd",
-                &format_args!("{}", self.rx_idle_thrhd().bits()),
-            )
-            .field(
-                "tx_idle_num",
-                &format_args!("{}", self.tx_idle_num().bits()),
-            )
+            .field("rx_idle_thrhd", &self.rx_idle_thrhd())
+            .field("tx_idle_num", &self.tx_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/int_ena.rs b/esp32c2/src/uart0/int_ena.rs
index fea57f25bd..3a8a9f2f95 100644
--- a/esp32c2/src/uart0/int_ena.rs
+++ b/esp32c2/src/uart0/int_ena.rs
@@ -188,50 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/int_raw.rs b/esp32c2/src/uart0/int_raw.rs
index 525414943b..5a2e80fea2 100644
--- a/esp32c2/src/uart0/int_raw.rs
+++ b/esp32c2/src/uart0/int_raw.rs
@@ -188,50 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/int_st.rs b/esp32c2/src/uart0/int_st.rs
index 417bc433a0..c67c7f4b75 100644
--- a/esp32c2/src/uart0/int_st.rs
+++ b/esp32c2/src/uart0/int_st.rs
@@ -146,50 +146,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c2/src/uart0/lowpulse.rs b/esp32c2/src/uart0/lowpulse.rs
index 6736272863..03a2b35c08 100644
--- a/esp32c2/src/uart0/lowpulse.rs
+++ b/esp32c2/src/uart0/lowpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOWPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOWPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud minimum low pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lowpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOWPULSE_SPEC;
 impl crate::RegisterSpec for LOWPULSE_SPEC {
diff --git a/esp32c2/src/uart0/mem_conf.rs b/esp32c2/src/uart0/mem_conf.rs
index 3406996321..95fd5904d1 100644
--- a/esp32c2/src/uart0/mem_conf.rs
+++ b/esp32c2/src/uart0/mem_conf.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field("rx_size", &format_args!("{}", self.rx_size().bits()))
-            .field("tx_size", &format_args!("{}", self.tx_size().bits()))
-            .field(
-                "rx_flow_thrhd",
-                &format_args!("{}", self.rx_flow_thrhd().bits()),
-            )
-            .field(
-                "rx_tout_thrhd",
-                &format_args!("{}", self.rx_tout_thrhd().bits()),
-            )
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
+            .field("rx_size", &self.rx_size())
+            .field("tx_size", &self.tx_size())
+            .field("rx_flow_thrhd", &self.rx_flow_thrhd())
+            .field("rx_tout_thrhd", &self.rx_tout_thrhd())
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 1:3 - This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/mem_rx_status.rs b/esp32c2/src/uart0/mem_rx_status.rs
index 00b4094b66..7820e80b36 100644
--- a/esp32c2/src/uart0/mem_rx_status.rs
+++ b/esp32c2/src/uart0/mem_rx_status.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_RX_STATUS")
-            .field(
-                "apb_rx_raddr",
-                &format_args!("{}", self.apb_rx_raddr().bits()),
-            )
-            .field("rx_waddr", &format_args!("{}", self.rx_waddr().bits()))
+            .field("apb_rx_raddr", &self.apb_rx_raddr())
+            .field("rx_waddr", &self.rx_waddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Rx-FIFO write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_RX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_RX_STATUS_SPEC {
diff --git a/esp32c2/src/uart0/mem_tx_status.rs b/esp32c2/src/uart0/mem_tx_status.rs
index cacd384e62..9ddad52610 100644
--- a/esp32c2/src/uart0/mem_tx_status.rs
+++ b/esp32c2/src/uart0/mem_tx_status.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_TX_STATUS")
-            .field(
-                "apb_tx_waddr",
-                &format_args!("{}", self.apb_tx_waddr().bits()),
-            )
-            .field("tx_raddr", &format_args!("{}", self.tx_raddr().bits()))
+            .field("apb_tx_waddr", &self.apb_tx_waddr())
+            .field("tx_raddr", &self.tx_raddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Tx-FIFO write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_TX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_TX_STATUS_SPEC {
diff --git a/esp32c2/src/uart0/negpulse.rs b/esp32c2/src/uart0/negpulse.rs
index 0daf3b983f..d033b00895 100644
--- a/esp32c2/src/uart0/negpulse.rs
+++ b/esp32c2/src/uart0/negpulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NEGPULSE")
-            .field(
-                "negedge_min_cnt",
-                &format_args!("{}", self.negedge_min_cnt().bits()),
-            )
+            .field("negedge_min_cnt", &self.negedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NEGPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud low pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`negpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NEGPULSE_SPEC;
 impl crate::RegisterSpec for NEGPULSE_SPEC {
diff --git a/esp32c2/src/uart0/pospulse.rs b/esp32c2/src/uart0/pospulse.rs
index 67a98ae05f..acf540a226 100644
--- a/esp32c2/src/uart0/pospulse.rs
+++ b/esp32c2/src/uart0/pospulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POSPULSE")
-            .field(
-                "posedge_min_cnt",
-                &format_args!("{}", self.posedge_min_cnt().bits()),
-            )
+            .field("posedge_min_cnt", &self.posedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POSPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud high pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pospulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct POSPULSE_SPEC;
 impl crate::RegisterSpec for POSPULSE_SPEC {
diff --git a/esp32c2/src/uart0/rs485_conf.rs b/esp32c2/src/uart0/rs485_conf.rs
index 5480b03198..dbf27d91ba 100644
--- a/esp32c2/src/uart0/rs485_conf.rs
+++ b/esp32c2/src/uart0/rs485_conf.rs
@@ -71,34 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RS485_CONF")
-            .field("rs485_en", &format_args!("{}", self.rs485_en().bit()))
-            .field("dl0_en", &format_args!("{}", self.dl0_en().bit()))
-            .field("dl1_en", &format_args!("{}", self.dl1_en().bit()))
-            .field(
-                "rs485tx_rx_en",
-                &format_args!("{}", self.rs485tx_rx_en().bit()),
-            )
-            .field(
-                "rs485rxby_tx_en",
-                &format_args!("{}", self.rs485rxby_tx_en().bit()),
-            )
-            .field(
-                "rs485_rx_dly_num",
-                &format_args!("{}", self.rs485_rx_dly_num().bit()),
-            )
-            .field(
-                "rs485_tx_dly_num",
-                &format_args!("{}", self.rs485_tx_dly_num().bits()),
-            )
+            .field("rs485_en", &self.rs485_en())
+            .field("dl0_en", &self.dl0_en())
+            .field("dl1_en", &self.dl1_en())
+            .field("rs485tx_rx_en", &self.rs485tx_rx_en())
+            .field("rs485rxby_tx_en", &self.rs485rxby_tx_en())
+            .field("rs485_rx_dly_num", &self.rs485_rx_dly_num())
+            .field("rs485_tx_dly_num", &self.rs485_tx_dly_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RS485_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to choose the rs485 mode."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/rx_filt.rs b/esp32c2/src/uart0/rx_filt.rs
index 8b59a9e77a..c19d58140c 100644
--- a/esp32c2/src/uart0/rx_filt.rs
+++ b/esp32c2/src/uart0/rx_filt.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_FILT")
-            .field(
-                "glitch_filt",
-                &format_args!("{}", self.glitch_filt().bits()),
-            )
-            .field(
-                "glitch_filt_en",
-                &format_args!("{}", self.glitch_filt_en().bit()),
-            )
+            .field("glitch_filt", &self.glitch_filt())
+            .field("glitch_filt_en", &self.glitch_filt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_FILT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - when input pulse width is lower than this value, the pulse is ignored."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/rxd_cnt.rs b/esp32c2/src/uart0/rxd_cnt.rs
index f08d5e0323..c3c3052a66 100644
--- a/esp32c2/src/uart0/rxd_cnt.rs
+++ b/esp32c2/src/uart0/rxd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXD_CNT")
-            .field(
-                "rxd_edge_cnt",
-                &format_args!("{}", self.rxd_edge_cnt().bits()),
-            )
+            .field("rxd_edge_cnt", &self.rxd_edge_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud edge change count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXD_CNT_SPEC;
 impl crate::RegisterSpec for RXD_CNT_SPEC {
diff --git a/esp32c2/src/uart0/sleep_conf.rs b/esp32c2/src/uart0/sleep_conf.rs
index 1715cd71a2..bfe6d45eb0 100644
--- a/esp32c2/src/uart0/sleep_conf.rs
+++ b/esp32c2/src/uart0/sleep_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF")
-            .field(
-                "active_threshold",
-                &format_args!("{}", self.active_threshold().bits()),
-            )
+            .field("active_threshold", &self.active_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/status.rs b/esp32c2/src/uart0/status.rs
index 4e1eee73c3..43e7f84e00 100644
--- a/esp32c2/src/uart0/status.rs
+++ b/esp32c2/src/uart0/status.rs
@@ -62,23 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("dsrn", &format_args!("{}", self.dsrn().bit()))
-            .field("ctsn", &format_args!("{}", self.ctsn().bit()))
-            .field("rxd", &format_args!("{}", self.rxd().bit()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field("dtrn", &format_args!("{}", self.dtrn().bit()))
-            .field("rtsn", &format_args!("{}", self.rtsn().bit()))
-            .field("txd", &format_args!("{}", self.txd().bit()))
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("dsrn", &self.dsrn())
+            .field("ctsn", &self.ctsn())
+            .field("rxd", &self.rxd())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("dtrn", &self.dtrn())
+            .field("rtsn", &self.rtsn())
+            .field("txd", &self.txd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32c2/src/uart0/swfc_conf0.rs b/esp32c2/src/uart0/swfc_conf0.rs
index 30f5c56ba0..448e91c539 100644
--- a/esp32c2/src/uart0/swfc_conf0.rs
+++ b/esp32c2/src/uart0/swfc_conf0.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF0")
-            .field(
-                "xoff_threshold",
-                &format_args!("{}", self.xoff_threshold().bits()),
-            )
-            .field("xoff_char", &format_args!("{}", self.xoff_char().bits()))
+            .field("xoff_threshold", &self.xoff_threshold())
+            .field("xoff_char", &self.xoff_char())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/swfc_conf1.rs b/esp32c2/src/uart0/swfc_conf1.rs
index 0a328df376..5dd689e5b0 100644
--- a/esp32c2/src/uart0/swfc_conf1.rs
+++ b/esp32c2/src/uart0/swfc_conf1.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF1")
-            .field(
-                "xon_threshold",
-                &format_args!("{}", self.xon_threshold().bits()),
-            )
-            .field("xon_char", &format_args!("{}", self.xon_char().bits()))
+            .field("xon_threshold", &self.xon_threshold())
+            .field("xon_char", &self.xon_char())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char."]
     #[inline(always)]
diff --git a/esp32c2/src/uart0/txbrk_conf.rs b/esp32c2/src/uart0/txbrk_conf.rs
index bfa2a9b911..65d37271c2 100644
--- a/esp32c2/src/uart0/txbrk_conf.rs
+++ b/esp32c2/src/uart0/txbrk_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXBRK_CONF")
-            .field("tx_brk_num", &format_args!("{}", self.tx_brk_num().bits()))
+            .field("tx_brk_num", &self.tx_brk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXBRK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."]
     #[inline(always)]
diff --git a/esp32c2/src/xts_aes/date.rs b/esp32c2/src/xts_aes/date.rs
index 06bf4cb620..2eb7ba08c7 100644
--- a/esp32c2/src/xts_aes/date.rs
+++ b/esp32c2/src/xts_aes/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c2/src/xts_aes/destination.rs b/esp32c2/src/xts_aes/destination.rs
index bc69d838ce..1ed3e118bc 100644
--- a/esp32c2/src/xts_aes/destination.rs
+++ b/esp32c2/src/xts_aes/destination.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DESTINATION")
-            .field("destination", &format_args!("{}", self.destination().bit()))
+            .field("destination", &self.destination())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DESTINATION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit stores the destination. 0: flash(default). 1: reserved."]
     #[inline(always)]
diff --git a/esp32c2/src/xts_aes/linesize.rs b/esp32c2/src/xts_aes/linesize.rs
index 63b82089ab..965f433768 100644
--- a/esp32c2/src/xts_aes/linesize.rs
+++ b/esp32c2/src/xts_aes/linesize.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LINESIZE")
-            .field("linesize", &format_args!("{}", self.linesize().bit()))
+            .field("linesize", &self.linesize())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LINESIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit stores the line size parameter. 0: 16Byte, 1: 32Byte."]
     #[inline(always)]
diff --git a/esp32c2/src/xts_aes/physical_address.rs b/esp32c2/src/xts_aes/physical_address.rs
index 5146820356..ff4e5032db 100644
--- a/esp32c2/src/xts_aes/physical_address.rs
+++ b/esp32c2/src/xts_aes/physical_address.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHYSICAL_ADDRESS")
-            .field(
-                "physical_address",
-                &format_args!("{}", self.physical_address().bits()),
-            )
+            .field("physical_address", &self.physical_address())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHYSICAL_ADDRESS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes."]
     #[inline(always)]
diff --git a/esp32c2/src/xts_aes/plain_mem.rs b/esp32c2/src/xts_aes/plain_mem.rs
index d6b012bb1f..1f80f61b9f 100644
--- a/esp32c2/src/xts_aes/plain_mem.rs
+++ b/esp32c2/src/xts_aes/plain_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PLAIN_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores plaintext\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`plain_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`plain_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PLAIN_MEM_SPEC;
diff --git a/esp32c2/src/xts_aes/state.rs b/esp32c2/src/xts_aes/state.rs
index 27302f7c38..8588613069 100644
--- a/esp32c2/src/xts_aes/state.rs
+++ b/esp32c2/src/xts_aes/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("state", &format_args!("{}", self.state().bits()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "XTS-AES status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32c3/src/aes/aad_block_num.rs b/esp32c3/src/aes/aad_block_num.rs
index 75e37b35ae..34160ca226 100644
--- a/esp32c3/src/aes/aad_block_num.rs
+++ b/esp32c3/src/aes/aad_block_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AAD_BLOCK_NUM")
-            .field(
-                "aad_block_num",
-                &format_args!("{}", self.aad_block_num().bits()),
-            )
+            .field("aad_block_num", &self.aad_block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AAD_BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits stores the number of AAD block."]
     #[inline(always)]
diff --git a/esp32c3/src/aes/block_mode.rs b/esp32c3/src/aes/block_mode.rs
index e1da4c4f3c..b2e3b5efc6 100644
--- a/esp32c3/src/aes/block_mode.rs
+++ b/esp32c3/src/aes/block_mode.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLOCK_MODE")
-            .field("block_mode", &format_args!("{}", self.block_mode().bits()))
+            .field("block_mode", &self.block_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLOCK_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved."]
     #[inline(always)]
diff --git a/esp32c3/src/aes/block_num.rs b/esp32c3/src/aes/block_num.rs
index 80e2290bb3..a1897ab822 100644
--- a/esp32c3/src/aes/block_num.rs
+++ b/esp32c3/src/aes/block_num.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLOCK_NUM")
-            .field("block_num", &format_args!("{}", self.block_num().bits()))
+            .field("block_num", &self.block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits stores the number of Plaintext/ciphertext block."]
     #[inline(always)]
diff --git a/esp32c3/src/aes/date.rs b/esp32c3/src/aes/date.rs
index a22c32c101..5e7e48df64 100644
--- a/esp32c3/src/aes/date.rs
+++ b/esp32c3/src/aes/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/aes/dma_enable.rs b/esp32c3/src/aes/dma_enable.rs
index 3fa34abee5..1f5f535a07 100644
--- a/esp32c3/src/aes/dma_enable.rs
+++ b/esp32c3/src/aes/dma_enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_ENABLE")
-            .field("dma_enable", &format_args!("{}", self.dma_enable().bit()))
+            .field("dma_enable", &self.dma_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."]
     #[inline(always)]
diff --git a/esp32c3/src/aes/endian.rs b/esp32c3/src/aes/endian.rs
index e5a3e93efc..30ecf46902 100644
--- a/esp32c3/src/aes/endian.rs
+++ b/esp32c3/src/aes/endian.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENDIAN")
-            .field("endian", &format_args!("{}", self.endian().bits()))
+            .field("endian", &self.endian())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENDIAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - endian. \\[1:0\\] key endian, \\[3:2\\] text_in endian or in_stream endian, \\[5:4\\] text_out endian or out_stream endian"]
     #[inline(always)]
diff --git a/esp32c3/src/aes/h_mem.rs b/esp32c3/src/aes/h_mem.rs
index fcd1d250f9..2e4334ff37 100644
--- a/esp32c3/src/aes/h_mem.rs
+++ b/esp32c3/src/aes/h_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores GCM hash subkey\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct H_MEM_SPEC;
diff --git a/esp32c3/src/aes/inc_sel.rs b/esp32c3/src/aes/inc_sel.rs
index a6665d07ec..69d24607c0 100644
--- a/esp32c3/src/aes/inc_sel.rs
+++ b/esp32c3/src/aes/inc_sel.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INC_SEL")
-            .field("inc_sel", &format_args!("{}", self.inc_sel().bit()))
+            .field("inc_sel", &self.inc_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INC_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit decides the standard incrementing function. 0: INC32. 1: INC128."]
     #[inline(always)]
diff --git a/esp32c3/src/aes/int_ena.rs b/esp32c3/src/aes/int_ena.rs
index ccd96d099f..1abedbe830 100644
--- a/esp32c3/src/aes/int_ena.rs
+++ b/esp32c3/src/aes/int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("int_ena", &format_args!("{}", self.int_ena().bit()))
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable interrupt that occurs when DMA-AES calculation is done."]
     #[inline(always)]
diff --git a/esp32c3/src/aes/iv_mem.rs b/esp32c3/src/aes/iv_mem.rs
index e8b4d332de..20bdbb631b 100644
--- a/esp32c3/src/aes/iv_mem.rs
+++ b/esp32c3/src/aes/iv_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IV_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores initialization vector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iv_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iv_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IV_MEM_SPEC;
diff --git a/esp32c3/src/aes/j0_mem.rs b/esp32c3/src/aes/j0_mem.rs
index a78fdd3452..002c675bfe 100644
--- a/esp32c3/src/aes/j0_mem.rs
+++ b/esp32c3/src/aes/j0_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<J0_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores J0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`j0_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`j0_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct J0_MEM_SPEC;
diff --git a/esp32c3/src/aes/key.rs b/esp32c3/src/aes/key.rs
index 8b2a51282a..c1d2c046ad 100644
--- a/esp32c3/src/aes/key.rs
+++ b/esp32c3/src/aes/key.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("KEY")
-            .field("key", &format_args!("{}", self.key().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<KEY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("KEY").field("key", &self.key()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/aes/mode.rs b/esp32c3/src/aes/mode.rs
index edc4a67756..aa353f24b7 100644
--- a/esp32c3/src/aes/mode.rs
+++ b/esp32c3/src/aes/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/aes/remainder_bit_num.rs b/esp32c3/src/aes/remainder_bit_num.rs
index 330809cbc6..73a3610f09 100644
--- a/esp32c3/src/aes/remainder_bit_num.rs
+++ b/esp32c3/src/aes/remainder_bit_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REMAINDER_BIT_NUM")
-            .field(
-                "remainder_bit_num",
-                &format_args!("{}", self.remainder_bit_num().bits()),
-            )
+            .field("remainder_bit_num", &self.remainder_bit_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REMAINDER_BIT_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Those bits stores the number of remainder bit."]
     #[inline(always)]
diff --git a/esp32c3/src/aes/state.rs b/esp32c3/src/aes/state.rs
index 5a58b13248..8a38798ae3 100644
--- a/esp32c3/src/aes/state.rs
+++ b/esp32c3/src/aes/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("state", &format_args!("{}", self.state().bits()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "AES state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32c3/src/aes/t0_mem.rs b/esp32c3/src/aes/t0_mem.rs
index 1b3fcafdb6..e2445d62f8 100644
--- a/esp32c3/src/aes/t0_mem.rs
+++ b/esp32c3/src/aes/t0_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T0_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores T0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct T0_MEM_SPEC;
diff --git a/esp32c3/src/aes/text_in.rs b/esp32c3/src/aes/text_in.rs
index 71ff18340a..24a5810ee3 100644
--- a/esp32c3/src/aes/text_in.rs
+++ b/esp32c3/src/aes/text_in.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEXT_IN")
-            .field("text_in", &format_args!("{}", self.text_in().bits()))
+            .field("text_in", &self.text_in())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEXT_IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This bits stores text_in_0 that is a part of source text material."]
     #[inline(always)]
diff --git a/esp32c3/src/aes/text_out.rs b/esp32c3/src/aes/text_out.rs
index 4040aae24b..29f631b4b2 100644
--- a/esp32c3/src/aes/text_out.rs
+++ b/esp32c3/src/aes/text_out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEXT_OUT")
-            .field("text_out", &format_args!("{}", self.text_out().bits()))
+            .field("text_out", &self.text_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEXT_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This bits stores text_out_0 that is a part of result text material."]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/clk_out_en.rs b/esp32c3/src/apb_ctrl/clk_out_en.rs
index 93e01e1332..1b1c9ce00b 100644
--- a/esp32c3/src/apb_ctrl/clk_out_en.rs
+++ b/esp32c3/src/apb_ctrl/clk_out_en.rs
@@ -107,41 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_OUT_EN")
-            .field("clk20_oen", &format_args!("{}", self.clk20_oen().bit()))
-            .field("clk22_oen", &format_args!("{}", self.clk22_oen().bit()))
-            .field("clk44_oen", &format_args!("{}", self.clk44_oen().bit()))
-            .field("clk_bb_oen", &format_args!("{}", self.clk_bb_oen().bit()))
-            .field("clk80_oen", &format_args!("{}", self.clk80_oen().bit()))
-            .field("clk160_oen", &format_args!("{}", self.clk160_oen().bit()))
-            .field(
-                "clk_320m_oen",
-                &format_args!("{}", self.clk_320m_oen().bit()),
-            )
-            .field(
-                "clk_adc_inf_oen",
-                &format_args!("{}", self.clk_adc_inf_oen().bit()),
-            )
-            .field(
-                "clk_dac_cpu_oen",
-                &format_args!("{}", self.clk_dac_cpu_oen().bit()),
-            )
-            .field(
-                "clk40x_bb_oen",
-                &format_args!("{}", self.clk40x_bb_oen().bit()),
-            )
-            .field(
-                "clk_xtal_oen",
-                &format_args!("{}", self.clk_xtal_oen().bit()),
-            )
+            .field("clk20_oen", &self.clk20_oen())
+            .field("clk22_oen", &self.clk22_oen())
+            .field("clk44_oen", &self.clk44_oen())
+            .field("clk_bb_oen", &self.clk_bb_oen())
+            .field("clk80_oen", &self.clk80_oen())
+            .field("clk160_oen", &self.clk160_oen())
+            .field("clk_320m_oen", &self.clk_320m_oen())
+            .field("clk_adc_inf_oen", &self.clk_adc_inf_oen())
+            .field("clk_dac_cpu_oen", &self.clk_dac_cpu_oen())
+            .field("clk40x_bb_oen", &self.clk40x_bb_oen())
+            .field("clk_xtal_oen", &self.clk_xtal_oen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_OUT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_clk20_oen"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/clkgate_force_on.rs b/esp32c3/src/apb_ctrl/clkgate_force_on.rs
index 4671332838..c4c8604caf 100644
--- a/esp32c3/src/apb_ctrl/clkgate_force_on.rs
+++ b/esp32c3/src/apb_ctrl/clkgate_force_on.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKGATE_FORCE_ON")
-            .field(
-                "rom_clkgate_force_on",
-                &format_args!("{}", self.rom_clkgate_force_on().bits()),
-            )
-            .field(
-                "sram_clkgate_force_on",
-                &format_args!("{}", self.sram_clkgate_force_on().bits()),
-            )
+            .field("rom_clkgate_force_on", &self.rom_clkgate_force_on())
+            .field("sram_clkgate_force_on", &self.sram_clkgate_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKGATE_FORCE_ON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reg_rom_clkgate_force_on"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/date.rs b/esp32c3/src/apb_ctrl/date.rs
index af40008b17..6c13c5d8f7 100644
--- a/esp32c3/src/apb_ctrl/date.rs
+++ b/esp32c3/src/apb_ctrl/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/apb_ctrl/ext_mem_pms_lock.rs b/esp32c3/src/apb_ctrl/ext_mem_pms_lock.rs
index a5affca905..4e5099000c 100644
--- a/esp32c3/src/apb_ctrl/ext_mem_pms_lock.rs
+++ b/esp32c3/src/apb_ctrl/ext_mem_pms_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_MEM_PMS_LOCK")
-            .field(
-                "ext_mem_pms_lock",
-                &format_args!("{}", self.ext_mem_pms_lock().bit()),
-            )
+            .field("ext_mem_pms_lock", &self.ext_mem_pms_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_MEM_PMS_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_ext_mem_pms_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/flash_ace0_addr.rs b/esp32c3/src/apb_ctrl/flash_ace0_addr.rs
index 3bb5a3b8b5..a5e9b9ff55 100644
--- a/esp32c3/src/apb_ctrl/flash_ace0_addr.rs
+++ b/esp32c3/src/apb_ctrl/flash_ace0_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE0_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_flash_ace0_addr_s"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/flash_ace0_attr.rs b/esp32c3/src/apb_ctrl/flash_ace0_attr.rs
index 2a43c5ae1c..031fee3f6b 100644
--- a/esp32c3/src/apb_ctrl/flash_ace0_attr.rs
+++ b/esp32c3/src/apb_ctrl/flash_ace0_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE0_ATTR")
-            .field(
-                "flash_ace0_attr",
-                &format_args!("{}", self.flash_ace0_attr().bits()),
-            )
+            .field("flash_ace0_attr", &self.flash_ace0_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE0_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reg_flash_ace0_attr"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/flash_ace0_size.rs b/esp32c3/src/apb_ctrl/flash_ace0_size.rs
index 720efba105..810deee936 100644
--- a/esp32c3/src/apb_ctrl/flash_ace0_size.rs
+++ b/esp32c3/src/apb_ctrl/flash_ace0_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE0_SIZE")
-            .field(
-                "flash_ace0_size",
-                &format_args!("{}", self.flash_ace0_size().bits()),
-            )
+            .field("flash_ace0_size", &self.flash_ace0_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - reg_flash_ace0_size"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/flash_ace1_addr.rs b/esp32c3/src/apb_ctrl/flash_ace1_addr.rs
index 821f446694..86c641aa6a 100644
--- a/esp32c3/src/apb_ctrl/flash_ace1_addr.rs
+++ b/esp32c3/src/apb_ctrl/flash_ace1_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE1_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_flash_ace1_addr_s"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/flash_ace1_attr.rs b/esp32c3/src/apb_ctrl/flash_ace1_attr.rs
index 76b34f4cf0..1f2e7fbc73 100644
--- a/esp32c3/src/apb_ctrl/flash_ace1_attr.rs
+++ b/esp32c3/src/apb_ctrl/flash_ace1_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE1_ATTR")
-            .field(
-                "flash_ace1_attr",
-                &format_args!("{}", self.flash_ace1_attr().bits()),
-            )
+            .field("flash_ace1_attr", &self.flash_ace1_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE1_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reg_flash_ace1_attr"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/flash_ace1_size.rs b/esp32c3/src/apb_ctrl/flash_ace1_size.rs
index bff39c1b6c..8d529961e2 100644
--- a/esp32c3/src/apb_ctrl/flash_ace1_size.rs
+++ b/esp32c3/src/apb_ctrl/flash_ace1_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE1_SIZE")
-            .field(
-                "flash_ace1_size",
-                &format_args!("{}", self.flash_ace1_size().bits()),
-            )
+            .field("flash_ace1_size", &self.flash_ace1_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - reg_flash_ace1_size"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/flash_ace2_addr.rs b/esp32c3/src/apb_ctrl/flash_ace2_addr.rs
index b9267f6e04..462402d3a2 100644
--- a/esp32c3/src/apb_ctrl/flash_ace2_addr.rs
+++ b/esp32c3/src/apb_ctrl/flash_ace2_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE2_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_flash_ace2_addr_s"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/flash_ace2_attr.rs b/esp32c3/src/apb_ctrl/flash_ace2_attr.rs
index 10dff6bf3e..cc17a0a38d 100644
--- a/esp32c3/src/apb_ctrl/flash_ace2_attr.rs
+++ b/esp32c3/src/apb_ctrl/flash_ace2_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE2_ATTR")
-            .field(
-                "flash_ace2_attr",
-                &format_args!("{}", self.flash_ace2_attr().bits()),
-            )
+            .field("flash_ace2_attr", &self.flash_ace2_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE2_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reg_flash_ace2_attr"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/flash_ace2_size.rs b/esp32c3/src/apb_ctrl/flash_ace2_size.rs
index 8dee90db82..88378bd2f9 100644
--- a/esp32c3/src/apb_ctrl/flash_ace2_size.rs
+++ b/esp32c3/src/apb_ctrl/flash_ace2_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE2_SIZE")
-            .field(
-                "flash_ace2_size",
-                &format_args!("{}", self.flash_ace2_size().bits()),
-            )
+            .field("flash_ace2_size", &self.flash_ace2_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE2_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - reg_flash_ace2_size"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/flash_ace3_addr.rs b/esp32c3/src/apb_ctrl/flash_ace3_addr.rs
index f715ccd5b5..afc734c8a8 100644
--- a/esp32c3/src/apb_ctrl/flash_ace3_addr.rs
+++ b/esp32c3/src/apb_ctrl/flash_ace3_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE3_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_flash_ace3_addr_s"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/flash_ace3_attr.rs b/esp32c3/src/apb_ctrl/flash_ace3_attr.rs
index cc60a454e4..6488958d4b 100644
--- a/esp32c3/src/apb_ctrl/flash_ace3_attr.rs
+++ b/esp32c3/src/apb_ctrl/flash_ace3_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE3_ATTR")
-            .field(
-                "flash_ace3_attr",
-                &format_args!("{}", self.flash_ace3_attr().bits()),
-            )
+            .field("flash_ace3_attr", &self.flash_ace3_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE3_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reg_flash_ace3_attr"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/flash_ace3_size.rs b/esp32c3/src/apb_ctrl/flash_ace3_size.rs
index ff5e15e842..2b2b172450 100644
--- a/esp32c3/src/apb_ctrl/flash_ace3_size.rs
+++ b/esp32c3/src/apb_ctrl/flash_ace3_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE3_SIZE")
-            .field(
-                "flash_ace3_size",
-                &format_args!("{}", self.flash_ace3_size().bits()),
-            )
+            .field("flash_ace3_size", &self.flash_ace3_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE3_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - reg_flash_ace3_size"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/front_end_mem_pd.rs b/esp32c3/src/apb_ctrl/front_end_mem_pd.rs
index 26408adfe3..90555d3668 100644
--- a/esp32c3/src/apb_ctrl/front_end_mem_pd.rs
+++ b/esp32c3/src/apb_ctrl/front_end_mem_pd.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FRONT_END_MEM_PD")
-            .field(
-                "agc_mem_force_pu",
-                &format_args!("{}", self.agc_mem_force_pu().bit()),
-            )
-            .field(
-                "agc_mem_force_pd",
-                &format_args!("{}", self.agc_mem_force_pd().bit()),
-            )
-            .field(
-                "pbus_mem_force_pu",
-                &format_args!("{}", self.pbus_mem_force_pu().bit()),
-            )
-            .field(
-                "pbus_mem_force_pd",
-                &format_args!("{}", self.pbus_mem_force_pd().bit()),
-            )
-            .field(
-                "dc_mem_force_pu",
-                &format_args!("{}", self.dc_mem_force_pu().bit()),
-            )
-            .field(
-                "dc_mem_force_pd",
-                &format_args!("{}", self.dc_mem_force_pd().bit()),
-            )
+            .field("agc_mem_force_pu", &self.agc_mem_force_pu())
+            .field("agc_mem_force_pd", &self.agc_mem_force_pd())
+            .field("pbus_mem_force_pu", &self.pbus_mem_force_pu())
+            .field("pbus_mem_force_pd", &self.pbus_mem_force_pd())
+            .field("dc_mem_force_pu", &self.dc_mem_force_pu())
+            .field("dc_mem_force_pd", &self.dc_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FRONT_END_MEM_PD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_agc_mem_force_pu"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/host_inf_sel.rs b/esp32c3/src/apb_ctrl/host_inf_sel.rs
index d2d026224a..98a34776f7 100644
--- a/esp32c3/src/apb_ctrl/host_inf_sel.rs
+++ b/esp32c3/src/apb_ctrl/host_inf_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_INF_SEL")
-            .field(
-                "peri_io_swap",
-                &format_args!("{}", self.peri_io_swap().bits()),
-            )
+            .field("peri_io_swap", &self.peri_io_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_INF_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - reg_peri_io_swap"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/mem_power_down.rs b/esp32c3/src/apb_ctrl/mem_power_down.rs
index f062f77a42..c841372a90 100644
--- a/esp32c3/src/apb_ctrl/mem_power_down.rs
+++ b/esp32c3/src/apb_ctrl/mem_power_down.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_POWER_DOWN")
-            .field(
-                "rom_power_down",
-                &format_args!("{}", self.rom_power_down().bits()),
-            )
-            .field(
-                "sram_power_down",
-                &format_args!("{}", self.sram_power_down().bits()),
-            )
+            .field("rom_power_down", &self.rom_power_down())
+            .field("sram_power_down", &self.sram_power_down())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_POWER_DOWN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reg_rom_power_down"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/mem_power_up.rs b/esp32c3/src/apb_ctrl/mem_power_up.rs
index 323e35a636..98a4240e79 100644
--- a/esp32c3/src/apb_ctrl/mem_power_up.rs
+++ b/esp32c3/src/apb_ctrl/mem_power_up.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_POWER_UP")
-            .field(
-                "rom_power_up",
-                &format_args!("{}", self.rom_power_up().bits()),
-            )
-            .field(
-                "sram_power_up",
-                &format_args!("{}", self.sram_power_up().bits()),
-            )
+            .field("rom_power_up", &self.rom_power_up())
+            .field("sram_power_up", &self.sram_power_up())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_POWER_UP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reg_rom_power_up"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/peri_backup_apb_addr.rs b/esp32c3/src/apb_ctrl/peri_backup_apb_addr.rs
index be8ff6a3b9..f453646600 100644
--- a/esp32c3/src/apb_ctrl/peri_backup_apb_addr.rs
+++ b/esp32c3/src/apb_ctrl/peri_backup_apb_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_BACKUP_APB_ADDR")
-            .field(
-                "backup_apb_start_addr",
-                &format_args!("{}", self.backup_apb_start_addr().bits()),
-            )
+            .field("backup_apb_start_addr", &self.backup_apb_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_BACKUP_APB_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_backup_apb_start_addr"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/peri_backup_config.rs b/esp32c3/src/apb_ctrl/peri_backup_config.rs
index 7d98ed340a..1817d99a10 100644
--- a/esp32c3/src/apb_ctrl/peri_backup_config.rs
+++ b/esp32c3/src/apb_ctrl/peri_backup_config.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_BACKUP_CONFIG")
-            .field(
-                "peri_backup_flow_err",
-                &format_args!("{}", self.peri_backup_flow_err().bits()),
-            )
-            .field(
-                "peri_backup_burst_limit",
-                &format_args!("{}", self.peri_backup_burst_limit().bits()),
-            )
-            .field(
-                "peri_backup_tout_thres",
-                &format_args!("{}", self.peri_backup_tout_thres().bits()),
-            )
-            .field(
-                "peri_backup_size",
-                &format_args!("{}", self.peri_backup_size().bits()),
-            )
-            .field(
-                "peri_backup_to_mem",
-                &format_args!("{}", self.peri_backup_to_mem().bit()),
-            )
-            .field(
-                "peri_backup_ena",
-                &format_args!("{}", self.peri_backup_ena().bit()),
-            )
+            .field("peri_backup_flow_err", &self.peri_backup_flow_err())
+            .field("peri_backup_burst_limit", &self.peri_backup_burst_limit())
+            .field("peri_backup_tout_thres", &self.peri_backup_tout_thres())
+            .field("peri_backup_size", &self.peri_backup_size())
+            .field("peri_backup_to_mem", &self.peri_backup_to_mem())
+            .field("peri_backup_ena", &self.peri_backup_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_BACKUP_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 4:8 - reg_peri_backup_burst_limit"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/peri_backup_int_ena.rs b/esp32c3/src/apb_ctrl/peri_backup_int_ena.rs
index 468af4e912..85708f8e9e 100644
--- a/esp32c3/src/apb_ctrl/peri_backup_int_ena.rs
+++ b/esp32c3/src/apb_ctrl/peri_backup_int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_BACKUP_INT_ENA")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("err", &format_args!("{}", self.err().bit()))
+            .field("done", &self.done())
+            .field("err", &self.err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_BACKUP_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_peri_backup_done_int_ena"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/peri_backup_int_raw.rs b/esp32c3/src/apb_ctrl/peri_backup_int_raw.rs
index 1a45cbdcc5..776d3b1a3a 100644
--- a/esp32c3/src/apb_ctrl/peri_backup_int_raw.rs
+++ b/esp32c3/src/apb_ctrl/peri_backup_int_raw.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_BACKUP_INT_RAW")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("err", &format_args!("{}", self.err().bit()))
+            .field("done", &self.done())
+            .field("err", &self.err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_BACKUP_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "APB_CTRL_PERI_BACKUP_INT_RAW_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_backup_int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PERI_BACKUP_INT_RAW_SPEC;
 impl crate::RegisterSpec for PERI_BACKUP_INT_RAW_SPEC {
diff --git a/esp32c3/src/apb_ctrl/peri_backup_int_st.rs b/esp32c3/src/apb_ctrl/peri_backup_int_st.rs
index a83e4e6e14..a15a578d43 100644
--- a/esp32c3/src/apb_ctrl/peri_backup_int_st.rs
+++ b/esp32c3/src/apb_ctrl/peri_backup_int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_BACKUP_INT_ST")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("err", &format_args!("{}", self.err().bit()))
+            .field("done", &self.done())
+            .field("err", &self.err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_BACKUP_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "APB_CTRL_PERI_BACKUP_INT_ST_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_backup_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PERI_BACKUP_INT_ST_SPEC;
 impl crate::RegisterSpec for PERI_BACKUP_INT_ST_SPEC {
diff --git a/esp32c3/src/apb_ctrl/peri_backup_mem_addr.rs b/esp32c3/src/apb_ctrl/peri_backup_mem_addr.rs
index 3f1d4eb47c..0a315fd0a5 100644
--- a/esp32c3/src/apb_ctrl/peri_backup_mem_addr.rs
+++ b/esp32c3/src/apb_ctrl/peri_backup_mem_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_BACKUP_MEM_ADDR")
-            .field(
-                "backup_mem_start_addr",
-                &format_args!("{}", self.backup_mem_start_addr().bits()),
-            )
+            .field("backup_mem_start_addr", &self.backup_mem_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_BACKUP_MEM_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_backup_mem_start_addr"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/redcy_sig0.rs b/esp32c3/src/apb_ctrl/redcy_sig0.rs
index 53686995f7..b36adf4a88 100644
--- a/esp32c3/src/apb_ctrl/redcy_sig0.rs
+++ b/esp32c3/src/apb_ctrl/redcy_sig0.rs
@@ -24,17 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDCY_SIG0")
-            .field("redcy_sig0", &format_args!("{}", self.redcy_sig0().bits()))
-            .field("redcy_andor", &format_args!("{}", self.redcy_andor().bit()))
+            .field("redcy_sig0", &self.redcy_sig0())
+            .field("redcy_andor", &self.redcy_andor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDCY_SIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - reg_redcy_sig0"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/redcy_sig1.rs b/esp32c3/src/apb_ctrl/redcy_sig1.rs
index a9db07e7cc..45bd29f629 100644
--- a/esp32c3/src/apb_ctrl/redcy_sig1.rs
+++ b/esp32c3/src/apb_ctrl/redcy_sig1.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDCY_SIG1")
-            .field("redcy_sig1", &format_args!("{}", self.redcy_sig1().bits()))
-            .field(
-                "redcy_nandor",
-                &format_args!("{}", self.redcy_nandor().bit()),
-            )
+            .field("redcy_sig1", &self.redcy_sig1())
+            .field("redcy_nandor", &self.redcy_nandor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDCY_SIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - reg_redcy_sig1"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/retention_ctrl.rs b/esp32c3/src/apb_ctrl/retention_ctrl.rs
index 704f720fdb..976ca1625e 100644
--- a/esp32c3/src/apb_ctrl/retention_ctrl.rs
+++ b/esp32c3/src/apb_ctrl/retention_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_CTRL")
-            .field(
-                "retention_link_addr",
-                &format_args!("{}", self.retention_link_addr().bits()),
-            )
-            .field(
-                "nobypass_cpu_iso_rst",
-                &format_args!("{}", self.nobypass_cpu_iso_rst().bit()),
-            )
+            .field("retention_link_addr", &self.retention_link_addr())
+            .field("nobypass_cpu_iso_rst", &self.nobypass_cpu_iso_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:26 - reg_retention_link_addr"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/rnd_data.rs b/esp32c3/src/apb_ctrl/rnd_data.rs
index 5b90e4e5f7..913e725f74 100644
--- a/esp32c3/src/apb_ctrl/rnd_data.rs
+++ b/esp32c3/src/apb_ctrl/rnd_data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_DATA")
-            .field("rnd_data", &format_args!("{}", self.rnd_data().bits()))
+            .field("rnd_data", &self.rnd_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "APB_CTRL_RND_DATA_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RND_DATA_SPEC;
 impl crate::RegisterSpec for RND_DATA_SPEC {
diff --git a/esp32c3/src/apb_ctrl/sdio_ctrl.rs b/esp32c3/src/apb_ctrl/sdio_ctrl.rs
index 739b409e3c..8ac4b3c4ef 100644
--- a/esp32c3/src/apb_ctrl/sdio_ctrl.rs
+++ b/esp32c3/src/apb_ctrl/sdio_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_CTRL")
-            .field(
-                "sdio_win_access_en",
-                &format_args!("{}", self.sdio_win_access_en().bit()),
-            )
+            .field("sdio_win_access_en", &self.sdio_win_access_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_sdio_win_access_en"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/spi_mem_pms_ctrl.rs b/esp32c3/src/apb_ctrl/spi_mem_pms_ctrl.rs
index 1198b6854f..046cf11d0d 100644
--- a/esp32c3/src/apb_ctrl/spi_mem_pms_ctrl.rs
+++ b/esp32c3/src/apb_ctrl/spi_mem_pms_ctrl.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_MEM_PMS_CTRL")
-            .field(
-                "spi_mem_reject_int",
-                &format_args!("{}", self.spi_mem_reject_int().bit()),
-            )
-            .field(
-                "spi_mem_reject_cde",
-                &format_args!("{}", self.spi_mem_reject_cde().bits()),
-            )
+            .field("spi_mem_reject_int", &self.spi_mem_reject_int())
+            .field("spi_mem_reject_cde", &self.spi_mem_reject_cde())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_MEM_PMS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - reg_spi_mem_reject_clr"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/spi_mem_reject_addr.rs b/esp32c3/src/apb_ctrl/spi_mem_reject_addr.rs
index 64c06819c5..6a50fedaae 100644
--- a/esp32c3/src/apb_ctrl/spi_mem_reject_addr.rs
+++ b/esp32c3/src/apb_ctrl/spi_mem_reject_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_MEM_REJECT_ADDR")
-            .field(
-                "spi_mem_reject_addr",
-                &format_args!("{}", self.spi_mem_reject_addr().bits()),
-            )
+            .field("spi_mem_reject_addr", &self.spi_mem_reject_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_MEM_REJECT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "APB_CTRL_SPI_MEM_REJECT_ADDR_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_reject_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_MEM_REJECT_ADDR_SPEC;
 impl crate::RegisterSpec for SPI_MEM_REJECT_ADDR_SPEC {
diff --git a/esp32c3/src/apb_ctrl/sysclk_conf.rs b/esp32c3/src/apb_ctrl/sysclk_conf.rs
index 8bae21435c..1d301eac95 100644
--- a/esp32c3/src/apb_ctrl/sysclk_conf.rs
+++ b/esp32c3/src/apb_ctrl/sysclk_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSCLK_CONF")
-            .field(
-                "pre_div_cnt",
-                &format_args!("{}", self.pre_div_cnt().bits()),
-            )
-            .field("clk_320m_en", &format_args!("{}", self.clk_320m_en().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "rst_tick_cnt",
-                &format_args!("{}", self.rst_tick_cnt().bit()),
-            )
+            .field("pre_div_cnt", &self.pre_div_cnt())
+            .field("clk_320m_en", &self.clk_320m_en())
+            .field("clk_en", &self.clk_en())
+            .field("rst_tick_cnt", &self.rst_tick_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - reg_pre_div_cnt"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/tick_conf.rs b/esp32c3/src/apb_ctrl/tick_conf.rs
index 8870955ad5..0b33674272 100644
--- a/esp32c3/src/apb_ctrl/tick_conf.rs
+++ b/esp32c3/src/apb_ctrl/tick_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TICK_CONF")
-            .field(
-                "xtal_tick_num",
-                &format_args!("{}", self.xtal_tick_num().bits()),
-            )
-            .field(
-                "ck8m_tick_num",
-                &format_args!("{}", self.ck8m_tick_num().bits()),
-            )
-            .field("tick_enable", &format_args!("{}", self.tick_enable().bit()))
+            .field("xtal_tick_num", &self.xtal_tick_num())
+            .field("ck8m_tick_num", &self.ck8m_tick_num())
+            .field("tick_enable", &self.tick_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TICK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - reg_xtal_tick_num"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/wifi_bb_cfg.rs b/esp32c3/src/apb_ctrl/wifi_bb_cfg.rs
index 47177b633e..330d15909b 100644
--- a/esp32c3/src/apb_ctrl/wifi_bb_cfg.rs
+++ b/esp32c3/src/apb_ctrl/wifi_bb_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_BB_CFG")
-            .field(
-                "wifi_bb_cfg",
-                &format_args!("{}", self.wifi_bb_cfg().bits()),
-            )
+            .field("wifi_bb_cfg", &self.wifi_bb_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_BB_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_wifi_bb_cfg"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/wifi_bb_cfg_2.rs b/esp32c3/src/apb_ctrl/wifi_bb_cfg_2.rs
index 8264944a2d..7dcd6cfe96 100644
--- a/esp32c3/src/apb_ctrl/wifi_bb_cfg_2.rs
+++ b/esp32c3/src/apb_ctrl/wifi_bb_cfg_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_BB_CFG_2")
-            .field(
-                "wifi_bb_cfg_2",
-                &format_args!("{}", self.wifi_bb_cfg_2().bits()),
-            )
+            .field("wifi_bb_cfg_2", &self.wifi_bb_cfg_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_BB_CFG_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_wifi_bb_cfg_2"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/wifi_clk_en.rs b/esp32c3/src/apb_ctrl/wifi_clk_en.rs
index 9f820ac8a9..7f04191acd 100644
--- a/esp32c3/src/apb_ctrl/wifi_clk_en.rs
+++ b/esp32c3/src/apb_ctrl/wifi_clk_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_CLK_EN")
-            .field(
-                "wifi_clk_en",
-                &format_args!("{}", self.wifi_clk_en().bits()),
-            )
+            .field("wifi_clk_en", &self.wifi_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_wifi_clk_en"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_ctrl/wifi_rst_en.rs b/esp32c3/src/apb_ctrl/wifi_rst_en.rs
index f43618ae81..e47449aef7 100644
--- a/esp32c3/src/apb_ctrl/wifi_rst_en.rs
+++ b/esp32c3/src/apb_ctrl/wifi_rst_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_RST_EN")
-            .field("wifi_rst", &format_args!("{}", self.wifi_rst().bits()))
+            .field("wifi_rst", &self.wifi_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_RST_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_wifi_rst"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/arb_ctrl.rs b/esp32c3/src/apb_saradc/arb_ctrl.rs
index de8828334b..51290b0767 100644
--- a/esp32c3/src/apb_saradc/arb_ctrl.rs
+++ b/esp32c3/src/apb_saradc/arb_ctrl.rs
@@ -80,35 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_CTRL")
-            .field("apb_force", &format_args!("{}", self.apb_force().bit()))
-            .field("rtc_force", &format_args!("{}", self.rtc_force().bit()))
-            .field("wifi_force", &format_args!("{}", self.wifi_force().bit()))
-            .field("grant_force", &format_args!("{}", self.grant_force().bit()))
-            .field(
-                "apb_priority",
-                &format_args!("{}", self.apb_priority().bits()),
-            )
-            .field(
-                "rtc_priority",
-                &format_args!("{}", self.rtc_priority().bits()),
-            )
-            .field(
-                "wifi_priority",
-                &format_args!("{}", self.wifi_priority().bits()),
-            )
-            .field(
-                "fix_priority",
-                &format_args!("{}", self.fix_priority().bit()),
-            )
+            .field("apb_force", &self.apb_force())
+            .field("rtc_force", &self.rtc_force())
+            .field("wifi_force", &self.wifi_force())
+            .field("grant_force", &self.grant_force())
+            .field("apb_priority", &self.apb_priority())
+            .field("rtc_priority", &self.rtc_priority())
+            .field("wifi_priority", &self.wifi_priority())
+            .field("fix_priority", &self.fix_priority())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - adc2 arbiter force to enableapb controller"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/cali.rs b/esp32c3/src/apb_saradc/cali.rs
index f8159301ec..4a5f73518e 100644
--- a/esp32c3/src/apb_saradc/cali.rs
+++ b/esp32c3/src/apb_saradc/cali.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CALI")
-            .field("cfg", &format_args!("{}", self.cfg().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CALI").field("cfg", &self.cfg()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/apb_saradc/clkm_conf.rs b/esp32c3/src/apb_saradc/clkm_conf.rs
index 090b7974c0..6d87345504 100644
--- a/esp32c3/src/apb_saradc/clkm_conf.rs
+++ b/esp32c3/src/apb_saradc/clkm_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKM_CONF")
-            .field(
-                "clkm_div_num",
-                &format_args!("{}", self.clkm_div_num().bits()),
-            )
-            .field("clkm_div_b", &format_args!("{}", self.clkm_div_b().bits()))
-            .field("clkm_div_a", &format_args!("{}", self.clkm_div_a().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bits()))
+            .field("clkm_div_num", &self.clkm_div_num())
+            .field("clkm_div_b", &self.clkm_div_b())
+            .field("clkm_div_a", &self.clkm_div_a())
+            .field("clk_en", &self.clk_en())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral I2S clock divider value"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/ctrl.rs b/esp32c3/src/apb_saradc/ctrl.rs
index 0a34ef5977..f07a9eb3af 100644
--- a/esp32c3/src/apb_saradc/ctrl.rs
+++ b/esp32c3/src/apb_saradc/ctrl.rs
@@ -80,41 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("start_force", &format_args!("{}", self.start_force().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field(
-                "sar_clk_gated",
-                &format_args!("{}", self.sar_clk_gated().bit()),
-            )
-            .field(
-                "sar_clk_div",
-                &format_args!("{}", self.sar_clk_div().bits()),
-            )
-            .field(
-                "sar_patt_len",
-                &format_args!("{}", self.sar_patt_len().bits()),
-            )
-            .field(
-                "sar_patt_p_clear",
-                &format_args!("{}", self.sar_patt_p_clear().bit()),
-            )
-            .field(
-                "xpd_sar_force",
-                &format_args!("{}", self.xpd_sar_force().bits()),
-            )
-            .field(
-                "wait_arb_cycle",
-                &format_args!("{}", self.wait_arb_cycle().bits()),
-            )
+            .field("start_force", &self.start_force())
+            .field("start", &self.start())
+            .field("sar_clk_gated", &self.sar_clk_gated())
+            .field("sar_clk_div", &self.sar_clk_div())
+            .field("sar_patt_len", &self.sar_patt_len())
+            .field("sar_patt_p_clear", &self.sar_patt_p_clear())
+            .field("xpd_sar_force", &self.xpd_sar_force())
+            .field("wait_arb_cycle", &self.wait_arb_cycle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - select software enable saradc sample"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/ctrl2.rs b/esp32c3/src/apb_saradc/ctrl2.rs
index 0f067495b8..f8dd029bce 100644
--- a/esp32c3/src/apb_saradc/ctrl2.rs
+++ b/esp32c3/src/apb_saradc/ctrl2.rs
@@ -62,30 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field(
-                "meas_num_limit",
-                &format_args!("{}", self.meas_num_limit().bit()),
-            )
-            .field(
-                "max_meas_num",
-                &format_args!("{}", self.max_meas_num().bits()),
-            )
-            .field("sar1_inv", &format_args!("{}", self.sar1_inv().bit()))
-            .field("sar2_inv", &format_args!("{}", self.sar2_inv().bit()))
-            .field(
-                "timer_target",
-                &format_args!("{}", self.timer_target().bits()),
-            )
-            .field("timer_en", &format_args!("{}", self.timer_en().bit()))
+            .field("meas_num_limit", &self.meas_num_limit())
+            .field("max_meas_num", &self.max_meas_num())
+            .field("sar1_inv", &self.sar1_inv())
+            .field("sar2_inv", &self.sar2_inv())
+            .field("timer_target", &self.timer_target())
+            .field("timer_en", &self.timer_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable max meas num"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/ctrl_date.rs b/esp32c3/src/apb_saradc/ctrl_date.rs
index 3c417ed534..4d9ff96da7 100644
--- a/esp32c3/src/apb_saradc/ctrl_date.rs
+++ b/esp32c3/src/apb_saradc/ctrl_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL_DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - version"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/dma_conf.rs b/esp32c3/src/apb_saradc/dma_conf.rs
index f4528f9f98..e8ef94a4b7 100644
--- a/esp32c3/src/apb_saradc/dma_conf.rs
+++ b/esp32c3/src/apb_saradc/dma_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field(
-                "adc_eof_num",
-                &format_args!("{}", self.adc_eof_num().bits()),
-            )
-            .field(
-                "adc_reset_fsm",
-                &format_args!("{}", self.adc_reset_fsm().bit()),
-            )
-            .field("adc_trans", &format_args!("{}", self.adc_trans().bit()))
+            .field("adc_eof_num", &self.adc_eof_num())
+            .field("adc_reset_fsm", &self.adc_reset_fsm())
+            .field("adc_trans", &self.adc_trans())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - the dma_in_suc_eof gen when sample cnt = spi_eof_num"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/filter_ctrl0.rs b/esp32c3/src/apb_saradc/filter_ctrl0.rs
index 17eaaa1fd2..36c2d5446d 100644
--- a/esp32c3/src/apb_saradc/filter_ctrl0.rs
+++ b/esp32c3/src/apb_saradc/filter_ctrl0.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CTRL0")
-            .field(
-                "filter_channel1",
-                &format_args!("{}", self.filter_channel1().bits()),
-            )
-            .field(
-                "filter_channel0",
-                &format_args!("{}", self.filter_channel0().bits()),
-            )
-            .field(
-                "filter_reset",
-                &format_args!("{}", self.filter_reset().bit()),
-            )
+            .field("filter_channel1", &self.filter_channel1())
+            .field("filter_channel0", &self.filter_channel0())
+            .field("filter_reset", &self.filter_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 18:21 - configure filter1 to adc channel"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/filter_ctrl1.rs b/esp32c3/src/apb_saradc/filter_ctrl1.rs
index 5b4e0f3523..9893496ebf 100644
--- a/esp32c3/src/apb_saradc/filter_ctrl1.rs
+++ b/esp32c3/src/apb_saradc/filter_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CTRL1")
-            .field(
-                "filter_factor1",
-                &format_args!("{}", self.filter_factor1().bits()),
-            )
-            .field(
-                "filter_factor0",
-                &format_args!("{}", self.filter_factor0().bits()),
-            )
+            .field("filter_factor1", &self.filter_factor1())
+            .field("filter_factor0", &self.filter_factor0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 26:28 - Factor of saradc filter1"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/fsm_wait.rs b/esp32c3/src/apb_saradc/fsm_wait.rs
index fa4cd82fd6..d100d69e0f 100644
--- a/esp32c3/src/apb_saradc/fsm_wait.rs
+++ b/esp32c3/src/apb_saradc/fsm_wait.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_WAIT")
-            .field("xpd_wait", &format_args!("{}", self.xpd_wait().bits()))
-            .field("rstb_wait", &format_args!("{}", self.rstb_wait().bits()))
-            .field(
-                "standby_wait",
-                &format_args!("{}", self.standby_wait().bits()),
-            )
+            .field("xpd_wait", &self.xpd_wait())
+            .field("rstb_wait", &self.rstb_wait())
+            .field("standby_wait", &self.standby_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_WAIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - saradc_xpd_wait"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/int_ena.rs b/esp32c3/src/apb_saradc/int_ena.rs
index af17fd4ca1..29833bbcc9 100644
--- a/esp32c3/src/apb_saradc/int_ena.rs
+++ b/esp32c3/src/apb_saradc/int_ena.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - saradc thres1 low interrupt enable"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/int_raw.rs b/esp32c3/src/apb_saradc/int_raw.rs
index 627c367220..b0267d97f2 100644
--- a/esp32c3/src/apb_saradc/int_raw.rs
+++ b/esp32c3/src/apb_saradc/int_raw.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc int register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32c3/src/apb_saradc/int_st.rs b/esp32c3/src/apb_saradc/int_st.rs
index 0950d82a01..579a117942 100644
--- a/esp32c3/src/apb_saradc/int_st.rs
+++ b/esp32c3/src/apb_saradc/int_st.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc int register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c3/src/apb_saradc/onetime_sample.rs b/esp32c3/src/apb_saradc/onetime_sample.rs
index 0c838e5d4d..3e7f7d7c2a 100644
--- a/esp32c3/src/apb_saradc/onetime_sample.rs
+++ b/esp32c3/src/apb_saradc/onetime_sample.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ONETIME_SAMPLE")
-            .field(
-                "onetime_atten",
-                &format_args!("{}", self.onetime_atten().bits()),
-            )
-            .field(
-                "onetime_channel",
-                &format_args!("{}", self.onetime_channel().bits()),
-            )
-            .field(
-                "onetime_start",
-                &format_args!("{}", self.onetime_start().bit()),
-            )
-            .field(
-                "saradc2_onetime_sample",
-                &format_args!("{}", self.saradc2_onetime_sample().bit()),
-            )
-            .field(
-                "saradc1_onetime_sample",
-                &format_args!("{}", self.saradc1_onetime_sample().bit()),
-            )
+            .field("onetime_atten", &self.onetime_atten())
+            .field("onetime_channel", &self.onetime_channel())
+            .field("onetime_start", &self.onetime_start())
+            .field("saradc2_onetime_sample", &self.saradc2_onetime_sample())
+            .field("saradc1_onetime_sample", &self.saradc1_onetime_sample())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ONETIME_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:24 - configure onetime atten"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/sar1_status.rs b/esp32c3/src/apb_saradc/sar1_status.rs
index 73b8a1b01d..ab791c3b16 100644
--- a/esp32c3/src/apb_saradc/sar1_status.rs
+++ b/esp32c3/src/apb_saradc/sar1_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_STATUS")
-            .field(
-                "sar1_status",
-                &format_args!("{}", self.sar1_status().bits()),
-            )
+            .field("sar1_status", &self.sar1_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR1_STATUS_SPEC;
 impl crate::RegisterSpec for SAR1_STATUS_SPEC {
diff --git a/esp32c3/src/apb_saradc/sar1data_status.rs b/esp32c3/src/apb_saradc/sar1data_status.rs
index 413ab6231c..8304d75d71 100644
--- a/esp32c3/src/apb_saradc/sar1data_status.rs
+++ b/esp32c3/src/apb_saradc/sar1data_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1DATA_STATUS")
-            .field(
-                "saradc1_data",
-                &format_args!("{}", self.saradc1_data().bits()),
-            )
+            .field("saradc1_data", &self.saradc1_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1DATA_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1data_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR1DATA_STATUS_SPEC;
 impl crate::RegisterSpec for SAR1DATA_STATUS_SPEC {
diff --git a/esp32c3/src/apb_saradc/sar2_status.rs b/esp32c3/src/apb_saradc/sar2_status.rs
index de5d59e3a1..2bec6bf5dc 100644
--- a/esp32c3/src/apb_saradc/sar2_status.rs
+++ b/esp32c3/src/apb_saradc/sar2_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_STATUS")
-            .field(
-                "sar2_status",
-                &format_args!("{}", self.sar2_status().bits()),
-            )
+            .field("sar2_status", &self.sar2_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR2_STATUS_SPEC;
 impl crate::RegisterSpec for SAR2_STATUS_SPEC {
diff --git a/esp32c3/src/apb_saradc/sar2data_status.rs b/esp32c3/src/apb_saradc/sar2data_status.rs
index 9052cd0794..67cd6c6ec5 100644
--- a/esp32c3/src/apb_saradc/sar2data_status.rs
+++ b/esp32c3/src/apb_saradc/sar2data_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2DATA_STATUS")
-            .field(
-                "saradc2_data",
-                &format_args!("{}", self.saradc2_data().bits()),
-            )
+            .field("saradc2_data", &self.saradc2_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2DATA_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2data_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR2DATA_STATUS_SPEC;
 impl crate::RegisterSpec for SAR2DATA_STATUS_SPEC {
diff --git a/esp32c3/src/apb_saradc/sar_patt_tab1.rs b/esp32c3/src/apb_saradc/sar_patt_tab1.rs
index 1fdd0dcc3f..9ced45eca8 100644
--- a/esp32c3/src/apb_saradc/sar_patt_tab1.rs
+++ b/esp32c3/src/apb_saradc/sar_patt_tab1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_PATT_TAB1")
-            .field(
-                "sar_patt_tab1",
-                &format_args!("{}", self.sar_patt_tab1().bits()),
-            )
+            .field("sar_patt_tab1", &self.sar_patt_tab1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_PATT_TAB1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/sar_patt_tab2.rs b/esp32c3/src/apb_saradc/sar_patt_tab2.rs
index 7a6124c96d..5957064868 100644
--- a/esp32c3/src/apb_saradc/sar_patt_tab2.rs
+++ b/esp32c3/src/apb_saradc/sar_patt_tab2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_PATT_TAB2")
-            .field(
-                "sar_patt_tab2",
-                &format_args!("{}", self.sar_patt_tab2().bits()),
-            )
+            .field("sar_patt_tab2", &self.sar_patt_tab2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_PATT_TAB2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/thres0_ctrl.rs b/esp32c3/src/apb_saradc/thres0_ctrl.rs
index 1c7ff5e5c3..3b735155e3 100644
--- a/esp32c3/src/apb_saradc/thres0_ctrl.rs
+++ b/esp32c3/src/apb_saradc/thres0_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES0_CTRL")
-            .field(
-                "thres0_channel",
-                &format_args!("{}", self.thres0_channel().bits()),
-            )
-            .field(
-                "thres0_high",
-                &format_args!("{}", self.thres0_high().bits()),
-            )
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bits()))
+            .field("thres0_channel", &self.thres0_channel())
+            .field("thres0_high", &self.thres0_high())
+            .field("thres0_low", &self.thres0_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES0_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - configure thres0 to adc channel"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/thres1_ctrl.rs b/esp32c3/src/apb_saradc/thres1_ctrl.rs
index 26fb78f9e4..0ae0172e5c 100644
--- a/esp32c3/src/apb_saradc/thres1_ctrl.rs
+++ b/esp32c3/src/apb_saradc/thres1_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES1_CTRL")
-            .field(
-                "thres1_channel",
-                &format_args!("{}", self.thres1_channel().bits()),
-            )
-            .field(
-                "thres1_high",
-                &format_args!("{}", self.thres1_high().bits()),
-            )
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bits()))
+            .field("thres1_channel", &self.thres1_channel())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres1_low", &self.thres1_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES1_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - configure thres1 to adc channel"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/thres_ctrl.rs b/esp32c3/src/apb_saradc/thres_ctrl.rs
index c3d03adf77..040e84e114 100644
--- a/esp32c3/src/apb_saradc/thres_ctrl.rs
+++ b/esp32c3/src/apb_saradc/thres_ctrl.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES_CTRL")
-            .field(
-                "thres_all_en",
-                &format_args!("{}", self.thres_all_en().bit()),
-            )
-            .field("thres1_en", &format_args!("{}", self.thres1_en().bit()))
-            .field("thres0_en", &format_args!("{}", self.thres0_en().bit()))
+            .field("thres_all_en", &self.thres_all_en())
+            .field("thres1_en", &self.thres1_en())
+            .field("thres0_en", &self.thres0_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - enable thres to all channel"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/tsens_ctrl.rs b/esp32c3/src/apb_saradc/tsens_ctrl.rs
index 129833c5d4..07bc801dd7 100644
--- a/esp32c3/src/apb_saradc/tsens_ctrl.rs
+++ b/esp32c3/src/apb_saradc/tsens_ctrl.rs
@@ -42,19 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSENS_CTRL")
-            .field("out", &format_args!("{}", self.out().bits()))
-            .field("in_inv", &format_args!("{}", self.in_inv().bit()))
-            .field("clk_div", &format_args!("{}", self.clk_div().bits()))
-            .field("pu", &format_args!("{}", self.pu().bit()))
+            .field("out", &self.out())
+            .field("in_inv", &self.in_inv())
+            .field("clk_div", &self.clk_div())
+            .field("pu", &self.pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSENS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - invert temperature sensor data"]
     #[inline(always)]
diff --git a/esp32c3/src/apb_saradc/tsens_ctrl2.rs b/esp32c3/src/apb_saradc/tsens_ctrl2.rs
index bd67d42d0e..dd559966b9 100644
--- a/esp32c3/src/apb_saradc/tsens_ctrl2.rs
+++ b/esp32c3/src/apb_saradc/tsens_ctrl2.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSENS_CTRL2")
-            .field("xpd_wait", &format_args!("{}", self.xpd_wait().bits()))
-            .field("xpd_force", &format_args!("{}", self.xpd_force().bits()))
-            .field("clk_inv", &format_args!("{}", self.clk_inv().bit()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bit()))
+            .field("xpd_wait", &self.xpd_wait())
+            .field("xpd_force", &self.xpd_force())
+            .field("clk_inv", &self.clk_inv())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSENS_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - the time that power up tsens need wait"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/c0re_0_debug_mode.rs b/esp32c3/src/assist_debug/c0re_0_debug_mode.rs
index 85b98d9ae1..6698af1aa7 100644
--- a/esp32c3/src/assist_debug/c0re_0_debug_mode.rs
+++ b/esp32c3/src/assist_debug/c0re_0_debug_mode.rs
@@ -20,23 +20,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("C0RE_0_DEBUG_MODE")
-            .field(
-                "core_0_debug_mode",
-                &format_args!("{}", self.core_0_debug_mode().bit()),
-            )
+            .field("core_0_debug_mode", &self.core_0_debug_mode())
             .field(
                 "core_0_debug_module_active",
-                &format_args!("{}", self.core_0_debug_module_active().bit()),
+                &self.core_0_debug_module_active(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<C0RE_0_DEBUG_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ASSIST_DEBUG_C0RE_0_DEBUG_MODE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0re_0_debug_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct C0RE_0_DEBUG_MODE_SPEC;
 impl crate::RegisterSpec for C0RE_0_DEBUG_MODE_SPEC {
diff --git a/esp32c3/src/assist_debug/c0re_0_lastpc_before_exception.rs b/esp32c3/src/assist_debug/c0re_0_lastpc_before_exception.rs
index 336b3e173d..492cadf7a6 100644
--- a/esp32c3/src/assist_debug/c0re_0_lastpc_before_exception.rs
+++ b/esp32c3/src/assist_debug/c0re_0_lastpc_before_exception.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("C0RE_0_LASTPC_BEFORE_EXCEPTION")
-            .field(
-                "core_0_lastpc_before_exc",
-                &format_args!("{}", self.core_0_lastpc_before_exc().bits()),
-            )
+            .field("core_0_lastpc_before_exc", &self.core_0_lastpc_before_exc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<C0RE_0_LASTPC_BEFORE_EXCEPTION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0re_0_lastpc_before_exception::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct C0RE_0_LASTPC_BEFORE_EXCEPTION_SPEC;
 impl crate::RegisterSpec for C0RE_0_LASTPC_BEFORE_EXCEPTION_SPEC {
diff --git a/esp32c3/src/assist_debug/core_0_area_dram0_0_max.rs b/esp32c3/src/assist_debug/core_0_area_dram0_0_max.rs
index e86acaca2a..be1da9503f 100644
--- a/esp32c3/src/assist_debug/core_0_area_dram0_0_max.rs
+++ b/esp32c3/src/assist_debug/core_0_area_dram0_0_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_0_MAX")
-            .field(
-                "core_0_area_dram0_0_max",
-                &format_args!("{}", self.core_0_area_dram0_0_max().bits()),
-            )
+            .field("core_0_area_dram0_0_max", &self.core_0_area_dram0_0_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_0_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_core_0_area_dram0_0_max"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/core_0_area_dram0_0_min.rs b/esp32c3/src/assist_debug/core_0_area_dram0_0_min.rs
index 0d45baacd3..e00db42210 100644
--- a/esp32c3/src/assist_debug/core_0_area_dram0_0_min.rs
+++ b/esp32c3/src/assist_debug/core_0_area_dram0_0_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_0_MIN")
-            .field(
-                "core_0_area_dram0_0_min",
-                &format_args!("{}", self.core_0_area_dram0_0_min().bits()),
-            )
+            .field("core_0_area_dram0_0_min", &self.core_0_area_dram0_0_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_0_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_core_0_area_dram0_0_min"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/core_0_area_dram0_1_max.rs b/esp32c3/src/assist_debug/core_0_area_dram0_1_max.rs
index 259e388a96..51b4955b20 100644
--- a/esp32c3/src/assist_debug/core_0_area_dram0_1_max.rs
+++ b/esp32c3/src/assist_debug/core_0_area_dram0_1_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_1_MAX")
-            .field(
-                "core_0_area_dram0_1_max",
-                &format_args!("{}", self.core_0_area_dram0_1_max().bits()),
-            )
+            .field("core_0_area_dram0_1_max", &self.core_0_area_dram0_1_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_1_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_core_0_area_dram0_1_max"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/core_0_area_dram0_1_min.rs b/esp32c3/src/assist_debug/core_0_area_dram0_1_min.rs
index afed067730..15ccf154c8 100644
--- a/esp32c3/src/assist_debug/core_0_area_dram0_1_min.rs
+++ b/esp32c3/src/assist_debug/core_0_area_dram0_1_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_1_MIN")
-            .field(
-                "core_0_area_dram0_1_min",
-                &format_args!("{}", self.core_0_area_dram0_1_min().bits()),
-            )
+            .field("core_0_area_dram0_1_min", &self.core_0_area_dram0_1_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_1_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_core_0_area_dram0_1_min"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/core_0_area_pc.rs b/esp32c3/src/assist_debug/core_0_area_pc.rs
index 291cba3ac7..c7dbeff431 100644
--- a/esp32c3/src/assist_debug/core_0_area_pc.rs
+++ b/esp32c3/src/assist_debug/core_0_area_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PC")
-            .field(
-                "core_0_area_pc",
-                &format_args!("{}", self.core_0_area_pc().bits()),
-            )
+            .field("core_0_area_pc", &self.core_0_area_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ASSIST_DEBUG_CORE_0_AREA_PC_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_AREA_PC_SPEC;
 impl crate::RegisterSpec for CORE_0_AREA_PC_SPEC {
diff --git a/esp32c3/src/assist_debug/core_0_area_pif_0_max.rs b/esp32c3/src/assist_debug/core_0_area_pif_0_max.rs
index debeb05688..1b3b04cc7b 100644
--- a/esp32c3/src/assist_debug/core_0_area_pif_0_max.rs
+++ b/esp32c3/src/assist_debug/core_0_area_pif_0_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_0_MAX")
-            .field(
-                "core_0_area_pif_0_max",
-                &format_args!("{}", self.core_0_area_pif_0_max().bits()),
-            )
+            .field("core_0_area_pif_0_max", &self.core_0_area_pif_0_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_0_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_core_0_area_pif_0_max"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/core_0_area_pif_0_min.rs b/esp32c3/src/assist_debug/core_0_area_pif_0_min.rs
index e2e41a2b2a..11c5a191d1 100644
--- a/esp32c3/src/assist_debug/core_0_area_pif_0_min.rs
+++ b/esp32c3/src/assist_debug/core_0_area_pif_0_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_0_MIN")
-            .field(
-                "core_0_area_pif_0_min",
-                &format_args!("{}", self.core_0_area_pif_0_min().bits()),
-            )
+            .field("core_0_area_pif_0_min", &self.core_0_area_pif_0_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_0_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_core_0_area_pif_0_min"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/core_0_area_pif_1_max.rs b/esp32c3/src/assist_debug/core_0_area_pif_1_max.rs
index 75d341c895..baa7022192 100644
--- a/esp32c3/src/assist_debug/core_0_area_pif_1_max.rs
+++ b/esp32c3/src/assist_debug/core_0_area_pif_1_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_1_MAX")
-            .field(
-                "core_0_area_pif_1_max",
-                &format_args!("{}", self.core_0_area_pif_1_max().bits()),
-            )
+            .field("core_0_area_pif_1_max", &self.core_0_area_pif_1_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_1_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_core_0_area_pif_1_max"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/core_0_area_pif_1_min.rs b/esp32c3/src/assist_debug/core_0_area_pif_1_min.rs
index cdba16d8d8..29bfe88e8a 100644
--- a/esp32c3/src/assist_debug/core_0_area_pif_1_min.rs
+++ b/esp32c3/src/assist_debug/core_0_area_pif_1_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_1_MIN")
-            .field(
-                "core_0_area_pif_1_min",
-                &format_args!("{}", self.core_0_area_pif_1_min().bits()),
-            )
+            .field("core_0_area_pif_1_min", &self.core_0_area_pif_1_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_1_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_core_0_area_pif_1_min"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/core_0_area_sp.rs b/esp32c3/src/assist_debug/core_0_area_sp.rs
index 3b79f97b4c..dee3ba1c33 100644
--- a/esp32c3/src/assist_debug/core_0_area_sp.rs
+++ b/esp32c3/src/assist_debug/core_0_area_sp.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_SP")
-            .field(
-                "core_0_area_sp",
-                &format_args!("{}", self.core_0_area_sp().bits()),
-            )
+            .field("core_0_area_sp", &self.core_0_area_sp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_SP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ASSIST_DEBUG_CORE_0_AREA_SP_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_sp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_AREA_SP_SPEC;
 impl crate::RegisterSpec for CORE_0_AREA_SP_SPEC {
diff --git a/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_0.rs b/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_0.rs
index 64db08831e..5f5b8976be 100644
--- a/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_0.rs
+++ b/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_0.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_0_dram0_recording_addr_0",
-                &format_args!("{}", self.core_0_dram0_recording_addr_0().bits()),
+                &self.core_0_dram0_recording_addr_0(),
             )
             .field(
                 "core_0_dram0_recording_wr_0",
-                &format_args!("{}", self.core_0_dram0_recording_wr_0().bit()),
+                &self.core_0_dram0_recording_wr_0(),
             )
             .field(
                 "core_0_dram0_recording_byteen_0",
-                &format_args!("{}", self.core_0_dram0_recording_byteen_0().bits()),
+                &self.core_0_dram0_recording_byteen_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC {
diff --git a/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_1.rs b/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_1.rs
index eed3a76857..85a9459aac 100644
--- a/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_1.rs
+++ b/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_0_dram0_recording_pc_0",
-                &format_args!("{}", self.core_0_dram0_recording_pc_0().bits()),
+                &self.core_0_dram0_recording_pc_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC {
diff --git a/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_2.rs b/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_2.rs
index 2a3bcee7af..322ff75ae5 100644
--- a/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_2.rs
+++ b/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_2.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_2")
             .field(
                 "core_0_dram0_recording_addr_1",
-                &format_args!("{}", self.core_0_dram0_recording_addr_1().bits()),
+                &self.core_0_dram0_recording_addr_1(),
             )
             .field(
                 "core_0_dram0_recording_wr_1",
-                &format_args!("{}", self.core_0_dram0_recording_wr_1().bit()),
+                &self.core_0_dram0_recording_wr_1(),
             )
             .field(
                 "core_0_dram0_recording_byteen_1",
-                &format_args!("{}", self.core_0_dram0_recording_byteen_1().bits()),
+                &self.core_0_dram0_recording_byteen_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC {
diff --git a/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_3.rs b/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_3.rs
index 260548dcd7..8ff6db78a2 100644
--- a/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_3.rs
+++ b/esp32c3/src/assist_debug/core_0_dram0_exception_monitor_3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_3")
             .field(
                 "core_0_dram0_recording_pc_1",
-                &format_args!("{}", self.core_0_dram0_recording_pc_1().bits()),
+                &self.core_0_dram0_recording_pc_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC {
diff --git a/esp32c3/src/assist_debug/core_0_intr_clr.rs b/esp32c3/src/assist_debug/core_0_intr_clr.rs
index 24fb01a360..f5926a098d 100644
--- a/esp32c3/src/assist_debug/core_0_intr_clr.rs
+++ b/esp32c3/src/assist_debug/core_0_intr_clr.rs
@@ -118,61 +118,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_INTR_CLR")
             .field(
                 "core_0_area_dram0_0_rd_clr",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_clr().bit()),
+                &self.core_0_area_dram0_0_rd_clr(),
             )
             .field(
                 "core_0_area_dram0_0_wr_clr",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_clr().bit()),
+                &self.core_0_area_dram0_0_wr_clr(),
             )
             .field(
                 "core_0_area_dram0_1_rd_clr",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_clr().bit()),
+                &self.core_0_area_dram0_1_rd_clr(),
             )
             .field(
                 "core_0_area_dram0_1_wr_clr",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_clr().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_rd_clr",
-                &format_args!("{}", self.core_0_area_pif_0_rd_clr().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_wr_clr",
-                &format_args!("{}", self.core_0_area_pif_0_wr_clr().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_rd_clr",
-                &format_args!("{}", self.core_0_area_pif_1_rd_clr().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_wr_clr",
-                &format_args!("{}", self.core_0_area_pif_1_wr_clr().bit()),
-            )
-            .field(
-                "core_0_sp_spill_min_clr",
-                &format_args!("{}", self.core_0_sp_spill_min_clr().bit()),
-            )
-            .field(
-                "core_0_sp_spill_max_clr",
-                &format_args!("{}", self.core_0_sp_spill_max_clr().bit()),
+                &self.core_0_area_dram0_1_wr_clr(),
             )
+            .field("core_0_area_pif_0_rd_clr", &self.core_0_area_pif_0_rd_clr())
+            .field("core_0_area_pif_0_wr_clr", &self.core_0_area_pif_0_wr_clr())
+            .field("core_0_area_pif_1_rd_clr", &self.core_0_area_pif_1_rd_clr())
+            .field("core_0_area_pif_1_wr_clr", &self.core_0_area_pif_1_wr_clr())
+            .field("core_0_sp_spill_min_clr", &self.core_0_sp_spill_min_clr())
+            .field("core_0_sp_spill_max_clr", &self.core_0_sp_spill_max_clr())
             .field(
                 "core_0_iram0_exception_monitor_clr",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_clr().bit()),
+                &self.core_0_iram0_exception_monitor_clr(),
             )
             .field(
                 "core_0_dram0_exception_monitor_clr",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_clr().bit()),
+                &self.core_0_dram0_exception_monitor_clr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_INTR_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_core_0_area_dram0_0_rd_clr"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/core_0_intr_ena.rs b/esp32c3/src/assist_debug/core_0_intr_ena.rs
index 41e49cfede..faed4e39cd 100644
--- a/esp32c3/src/assist_debug/core_0_intr_ena.rs
+++ b/esp32c3/src/assist_debug/core_0_intr_ena.rs
@@ -118,61 +118,55 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_INTR_ENA")
             .field(
                 "core_0_area_dram0_0_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_intr_ena().bit()),
+                &self.core_0_area_dram0_0_rd_intr_ena(),
             )
             .field(
                 "core_0_area_dram0_0_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_intr_ena().bit()),
+                &self.core_0_area_dram0_0_wr_intr_ena(),
             )
             .field(
                 "core_0_area_dram0_1_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_intr_ena().bit()),
+                &self.core_0_area_dram0_1_rd_intr_ena(),
             )
             .field(
                 "core_0_area_dram0_1_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_intr_ena().bit()),
+                &self.core_0_area_dram0_1_wr_intr_ena(),
             )
             .field(
                 "core_0_area_pif_0_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_0_rd_intr_ena().bit()),
+                &self.core_0_area_pif_0_rd_intr_ena(),
             )
             .field(
                 "core_0_area_pif_0_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_0_wr_intr_ena().bit()),
+                &self.core_0_area_pif_0_wr_intr_ena(),
             )
             .field(
                 "core_0_area_pif_1_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_1_rd_intr_ena().bit()),
+                &self.core_0_area_pif_1_rd_intr_ena(),
             )
             .field(
                 "core_0_area_pif_1_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_1_wr_intr_ena().bit()),
+                &self.core_0_area_pif_1_wr_intr_ena(),
             )
             .field(
                 "core_0_sp_spill_min_intr_ena",
-                &format_args!("{}", self.core_0_sp_spill_min_intr_ena().bit()),
+                &self.core_0_sp_spill_min_intr_ena(),
             )
             .field(
                 "core_0_sp_spill_max_intr_ena",
-                &format_args!("{}", self.core_0_sp_spill_max_intr_ena().bit()),
+                &self.core_0_sp_spill_max_intr_ena(),
             )
             .field(
                 "core_0_iram0_exception_monitor_rls",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_rls().bit()),
+                &self.core_0_iram0_exception_monitor_rls(),
             )
             .field(
                 "core_0_dram0_exception_monitor_rls",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_rls().bit()),
+                &self.core_0_dram0_exception_monitor_rls(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_INTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_core_0_area_dram0_0_rd_intr_ena"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/core_0_intr_raw.rs b/esp32c3/src/assist_debug/core_0_intr_raw.rs
index 936a2ef16d..f56467f51c 100644
--- a/esp32c3/src/assist_debug/core_0_intr_raw.rs
+++ b/esp32c3/src/assist_debug/core_0_intr_raw.rs
@@ -92,61 +92,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_INTR_RAW")
             .field(
                 "core_0_area_dram0_0_rd_raw",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_raw().bit()),
+                &self.core_0_area_dram0_0_rd_raw(),
             )
             .field(
                 "core_0_area_dram0_0_wr_raw",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_raw().bit()),
+                &self.core_0_area_dram0_0_wr_raw(),
             )
             .field(
                 "core_0_area_dram0_1_rd_raw",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_raw().bit()),
+                &self.core_0_area_dram0_1_rd_raw(),
             )
             .field(
                 "core_0_area_dram0_1_wr_raw",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_rd_raw",
-                &format_args!("{}", self.core_0_area_pif_0_rd_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_wr_raw",
-                &format_args!("{}", self.core_0_area_pif_0_wr_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_rd_raw",
-                &format_args!("{}", self.core_0_area_pif_1_rd_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_wr_raw",
-                &format_args!("{}", self.core_0_area_pif_1_wr_raw().bit()),
-            )
-            .field(
-                "core_0_sp_spill_min_raw",
-                &format_args!("{}", self.core_0_sp_spill_min_raw().bit()),
-            )
-            .field(
-                "core_0_sp_spill_max_raw",
-                &format_args!("{}", self.core_0_sp_spill_max_raw().bit()),
+                &self.core_0_area_dram0_1_wr_raw(),
             )
+            .field("core_0_area_pif_0_rd_raw", &self.core_0_area_pif_0_rd_raw())
+            .field("core_0_area_pif_0_wr_raw", &self.core_0_area_pif_0_wr_raw())
+            .field("core_0_area_pif_1_rd_raw", &self.core_0_area_pif_1_rd_raw())
+            .field("core_0_area_pif_1_wr_raw", &self.core_0_area_pif_1_wr_raw())
+            .field("core_0_sp_spill_min_raw", &self.core_0_sp_spill_min_raw())
+            .field("core_0_sp_spill_max_raw", &self.core_0_sp_spill_max_raw())
             .field(
                 "core_0_iram0_exception_monitor_raw",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_raw().bit()),
+                &self.core_0_iram0_exception_monitor_raw(),
             )
             .field(
                 "core_0_dram0_exception_monitor_raw",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_raw().bit()),
+                &self.core_0_dram0_exception_monitor_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_INTR_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ASSIST_DEBUG_CORE_0_INTR_RAW_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_intr_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_INTR_RAW_SPEC;
 impl crate::RegisterSpec for CORE_0_INTR_RAW_SPEC {
diff --git a/esp32c3/src/assist_debug/core_0_iram0_exception_monitor_0.rs b/esp32c3/src/assist_debug/core_0_iram0_exception_monitor_0.rs
index 48a2fbf058..b6a4fc04ea 100644
--- a/esp32c3/src/assist_debug/core_0_iram0_exception_monitor_0.rs
+++ b/esp32c3/src/assist_debug/core_0_iram0_exception_monitor_0.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_0_iram0_recording_addr_0",
-                &format_args!("{}", self.core_0_iram0_recording_addr_0().bits()),
+                &self.core_0_iram0_recording_addr_0(),
             )
             .field(
                 "core_0_iram0_recording_wr_0",
-                &format_args!("{}", self.core_0_iram0_recording_wr_0().bit()),
+                &self.core_0_iram0_recording_wr_0(),
             )
             .field(
                 "core_0_iram0_recording_loadstore_0",
-                &format_args!("{}", self.core_0_iram0_recording_loadstore_0().bit()),
+                &self.core_0_iram0_recording_loadstore_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_exception_monitor_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC;
 impl crate::RegisterSpec for CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC {
diff --git a/esp32c3/src/assist_debug/core_0_iram0_exception_monitor_1.rs b/esp32c3/src/assist_debug/core_0_iram0_exception_monitor_1.rs
index 384905c113..2660f6f5cb 100644
--- a/esp32c3/src/assist_debug/core_0_iram0_exception_monitor_1.rs
+++ b/esp32c3/src/assist_debug/core_0_iram0_exception_monitor_1.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_0_iram0_recording_addr_1",
-                &format_args!("{}", self.core_0_iram0_recording_addr_1().bits()),
+                &self.core_0_iram0_recording_addr_1(),
             )
             .field(
                 "core_0_iram0_recording_wr_1",
-                &format_args!("{}", self.core_0_iram0_recording_wr_1().bit()),
+                &self.core_0_iram0_recording_wr_1(),
             )
             .field(
                 "core_0_iram0_recording_loadstore_1",
-                &format_args!("{}", self.core_0_iram0_recording_loadstore_1().bit()),
+                &self.core_0_iram0_recording_loadstore_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_exception_monitor_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC;
 impl crate::RegisterSpec for CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC {
diff --git a/esp32c3/src/assist_debug/core_0_montr_ena.rs b/esp32c3/src/assist_debug/core_0_montr_ena.rs
index e3a317f978..f5befd9c4c 100644
--- a/esp32c3/src/assist_debug/core_0_montr_ena.rs
+++ b/esp32c3/src/assist_debug/core_0_montr_ena.rs
@@ -118,61 +118,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_MONTR_ENA")
             .field(
                 "core_0_area_dram0_0_rd_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_ena().bit()),
+                &self.core_0_area_dram0_0_rd_ena(),
             )
             .field(
                 "core_0_area_dram0_0_wr_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_ena().bit()),
+                &self.core_0_area_dram0_0_wr_ena(),
             )
             .field(
                 "core_0_area_dram0_1_rd_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_ena().bit()),
+                &self.core_0_area_dram0_1_rd_ena(),
             )
             .field(
                 "core_0_area_dram0_1_wr_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_rd_ena",
-                &format_args!("{}", self.core_0_area_pif_0_rd_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_wr_ena",
-                &format_args!("{}", self.core_0_area_pif_0_wr_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_rd_ena",
-                &format_args!("{}", self.core_0_area_pif_1_rd_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_wr_ena",
-                &format_args!("{}", self.core_0_area_pif_1_wr_ena().bit()),
-            )
-            .field(
-                "core_0_sp_spill_min_ena",
-                &format_args!("{}", self.core_0_sp_spill_min_ena().bit()),
-            )
-            .field(
-                "core_0_sp_spill_max_ena",
-                &format_args!("{}", self.core_0_sp_spill_max_ena().bit()),
+                &self.core_0_area_dram0_1_wr_ena(),
             )
+            .field("core_0_area_pif_0_rd_ena", &self.core_0_area_pif_0_rd_ena())
+            .field("core_0_area_pif_0_wr_ena", &self.core_0_area_pif_0_wr_ena())
+            .field("core_0_area_pif_1_rd_ena", &self.core_0_area_pif_1_rd_ena())
+            .field("core_0_area_pif_1_wr_ena", &self.core_0_area_pif_1_wr_ena())
+            .field("core_0_sp_spill_min_ena", &self.core_0_sp_spill_min_ena())
+            .field("core_0_sp_spill_max_ena", &self.core_0_sp_spill_max_ena())
             .field(
                 "core_0_iram0_exception_monitor_ena",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_ena().bit()),
+                &self.core_0_iram0_exception_monitor_ena(),
             )
             .field(
                 "core_0_dram0_exception_monitor_ena",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_ena().bit()),
+                &self.core_0_dram0_exception_monitor_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_MONTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_core_0_area_dram0_0_rd_ena"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/core_0_rcd_en.rs b/esp32c3/src/assist_debug/core_0_rcd_en.rs
index 684c02ec23..9038789c2d 100644
--- a/esp32c3/src/assist_debug/core_0_rcd_en.rs
+++ b/esp32c3/src/assist_debug/core_0_rcd_en.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_EN")
-            .field(
-                "core_0_rcd_recorden",
-                &format_args!("{}", self.core_0_rcd_recorden().bit()),
-            )
-            .field(
-                "core_0_rcd_pdebugen",
-                &format_args!("{}", self.core_0_rcd_pdebugen().bit()),
-            )
+            .field("core_0_rcd_recorden", &self.core_0_rcd_recorden())
+            .field("core_0_rcd_pdebugen", &self.core_0_rcd_pdebugen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_core_0_rcd_recorden"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/core_0_rcd_pdebugpc.rs b/esp32c3/src/assist_debug/core_0_rcd_pdebugpc.rs
index 67d82fceac..b42f1cc52c 100644
--- a/esp32c3/src/assist_debug/core_0_rcd_pdebugpc.rs
+++ b/esp32c3/src/assist_debug/core_0_rcd_pdebugpc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGPC")
-            .field(
-                "core_0_rcd_pdebugpc",
-                &format_args!("{}", self.core_0_rcd_pdebugpc().bits()),
-            )
+            .field("core_0_rcd_pdebugpc", &self.core_0_rcd_pdebugpc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGPC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugpc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGPC_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGPC_SPEC {
diff --git a/esp32c3/src/assist_debug/core_0_rcd_pdebugsp.rs b/esp32c3/src/assist_debug/core_0_rcd_pdebugsp.rs
index 3510b0e2a5..3a5afa4b4e 100644
--- a/esp32c3/src/assist_debug/core_0_rcd_pdebugsp.rs
+++ b/esp32c3/src/assist_debug/core_0_rcd_pdebugsp.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGSP")
-            .field(
-                "core_0_rcd_pdebugsp",
-                &format_args!("{}", self.core_0_rcd_pdebugsp().bits()),
-            )
+            .field("core_0_rcd_pdebugsp", &self.core_0_rcd_pdebugsp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGSP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugsp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGSP_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGSP_SPEC {
diff --git a/esp32c3/src/assist_debug/core_0_sp_max.rs b/esp32c3/src/assist_debug/core_0_sp_max.rs
index 890c602a82..40ad284b17 100644
--- a/esp32c3/src/assist_debug/core_0_sp_max.rs
+++ b/esp32c3/src/assist_debug/core_0_sp_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_MAX")
-            .field(
-                "core_0_sp_max",
-                &format_args!("{}", self.core_0_sp_max().bits()),
-            )
+            .field("core_0_sp_max", &self.core_0_sp_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_core_0_sp_max"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/core_0_sp_min.rs b/esp32c3/src/assist_debug/core_0_sp_min.rs
index e854d77a73..412f7d7170 100644
--- a/esp32c3/src/assist_debug/core_0_sp_min.rs
+++ b/esp32c3/src/assist_debug/core_0_sp_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_MIN")
-            .field(
-                "core_0_sp_min",
-                &format_args!("{}", self.core_0_sp_min().bits()),
-            )
+            .field("core_0_sp_min", &self.core_0_sp_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_core_0_sp_min"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/core_0_sp_pc.rs b/esp32c3/src/assist_debug/core_0_sp_pc.rs
index 1eda8bb56e..0005fde821 100644
--- a/esp32c3/src/assist_debug/core_0_sp_pc.rs
+++ b/esp32c3/src/assist_debug/core_0_sp_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_PC")
-            .field(
-                "core_0_sp_pc",
-                &format_args!("{}", self.core_0_sp_pc().bits()),
-            )
+            .field("core_0_sp_pc", &self.core_0_sp_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ASSIST_DEBUG_CORE_0_SP_PC_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_sp_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_SP_PC_SPEC;
 impl crate::RegisterSpec for CORE_0_SP_PC_SPEC {
diff --git a/esp32c3/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs b/esp32c3/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
index 8fd18d756d..77ced4a3a5 100644
--- a/esp32c3/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
+++ b/esp32c3/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_x_iram0_dram0_limit_cycle_0",
-                &format_args!("{}", self.core_x_iram0_dram0_limit_cycle_0().bits()),
+                &self.core_x_iram0_dram0_limit_cycle_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - reg_core_x_iram0_dram0_limit_cycle_0"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs b/esp32c3/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
index 707b8f551e..2b5ff36d95 100644
--- a/esp32c3/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
+++ b/esp32c3/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_x_iram0_dram0_limit_cycle_1",
-                &format_args!("{}", self.core_x_iram0_dram0_limit_cycle_1().bits()),
+                &self.core_x_iram0_dram0_limit_cycle_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - reg_core_x_iram0_dram0_limit_cycle_1"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/date.rs b/esp32c3/src/assist_debug/date.rs
index 92dccb5830..cc8f5762b1 100644
--- a/esp32c3/src/assist_debug/date.rs
+++ b/esp32c3/src/assist_debug/date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "assist_debug_date",
-                &format_args!("{}", self.assist_debug_date().bits()),
-            )
+            .field("assist_debug_date", &self.assist_debug_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - reg_assist_debug_date"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/log_data_0.rs b/esp32c3/src/assist_debug/log_data_0.rs
index a4261d60c4..7e559556d9 100644
--- a/esp32c3/src/assist_debug/log_data_0.rs
+++ b/esp32c3/src/assist_debug/log_data_0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_DATA_0")
-            .field("log_data_0", &format_args!("{}", self.log_data_0().bits()))
+            .field("log_data_0", &self.log_data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_DATA_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_log_data_0"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/log_data_mask.rs b/esp32c3/src/assist_debug/log_data_mask.rs
index 8a83521fbb..5bd016318e 100644
--- a/esp32c3/src/assist_debug/log_data_mask.rs
+++ b/esp32c3/src/assist_debug/log_data_mask.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_DATA_MASK")
-            .field(
-                "log_data_size",
-                &format_args!("{}", self.log_data_size().bits()),
-            )
+            .field("log_data_size", &self.log_data_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_DATA_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - reg_log_data_size"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/log_max.rs b/esp32c3/src/assist_debug/log_max.rs
index 71435e7376..7b7d6bf4c3 100644
--- a/esp32c3/src/assist_debug/log_max.rs
+++ b/esp32c3/src/assist_debug/log_max.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MAX")
-            .field("log_max", &format_args!("{}", self.log_max().bits()))
+            .field("log_max", &self.log_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_log_max"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/log_mem_end.rs b/esp32c3/src/assist_debug/log_mem_end.rs
index 0229af9083..c28bc91fcf 100644
--- a/esp32c3/src/assist_debug/log_mem_end.rs
+++ b/esp32c3/src/assist_debug/log_mem_end.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_END")
-            .field(
-                "log_mem_end",
-                &format_args!("{}", self.log_mem_end().bits()),
-            )
+            .field("log_mem_end", &self.log_mem_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_END_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_log_mem_end"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/log_mem_full_flag.rs b/esp32c3/src/assist_debug/log_mem_full_flag.rs
index e4617946c8..7b6e90a79a 100644
--- a/esp32c3/src/assist_debug/log_mem_full_flag.rs
+++ b/esp32c3/src/assist_debug/log_mem_full_flag.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_FULL_FLAG")
-            .field(
-                "log_mem_full_flag",
-                &format_args!("{}", self.log_mem_full_flag().bit()),
-            )
-            .field(
-                "clr_log_mem_full_flag",
-                &format_args!("{}", self.clr_log_mem_full_flag().bit()),
-            )
+            .field("log_mem_full_flag", &self.log_mem_full_flag())
+            .field("clr_log_mem_full_flag", &self.clr_log_mem_full_flag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_FULL_FLAG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - reg_clr_log_mem_full_flag"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/log_mem_start.rs b/esp32c3/src/assist_debug/log_mem_start.rs
index 07d305a772..a9444fa4ce 100644
--- a/esp32c3/src/assist_debug/log_mem_start.rs
+++ b/esp32c3/src/assist_debug/log_mem_start.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_START")
-            .field(
-                "log_mem_start",
-                &format_args!("{}", self.log_mem_start().bits()),
-            )
+            .field("log_mem_start", &self.log_mem_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_START_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_log_mem_start"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/log_mem_writing_addr.rs b/esp32c3/src/assist_debug/log_mem_writing_addr.rs
index 84dec582a1..46e897315f 100644
--- a/esp32c3/src/assist_debug/log_mem_writing_addr.rs
+++ b/esp32c3/src/assist_debug/log_mem_writing_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_WRITING_ADDR")
-            .field(
-                "log_mem_writing_addr",
-                &format_args!("{}", self.log_mem_writing_addr().bits()),
-            )
+            .field("log_mem_writing_addr", &self.log_mem_writing_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_WRITING_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`log_mem_writing_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOG_MEM_WRITING_ADDR_SPEC;
 impl crate::RegisterSpec for LOG_MEM_WRITING_ADDR_SPEC {
diff --git a/esp32c3/src/assist_debug/log_min.rs b/esp32c3/src/assist_debug/log_min.rs
index 2da61b3c29..b23acc0c5c 100644
--- a/esp32c3/src/assist_debug/log_min.rs
+++ b/esp32c3/src/assist_debug/log_min.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MIN")
-            .field("log_min", &format_args!("{}", self.log_min().bits()))
+            .field("log_min", &self.log_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_log_min"]
     #[inline(always)]
diff --git a/esp32c3/src/assist_debug/log_setting.rs b/esp32c3/src/assist_debug/log_setting.rs
index b58c277a72..313f0bc4c3 100644
--- a/esp32c3/src/assist_debug/log_setting.rs
+++ b/esp32c3/src/assist_debug/log_setting.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_SETTING")
-            .field("log_ena", &format_args!("{}", self.log_ena().bits()))
-            .field("log_mode", &format_args!("{}", self.log_mode().bits()))
-            .field(
-                "log_mem_loop_enable",
-                &format_args!("{}", self.log_mem_loop_enable().bit()),
-            )
+            .field("log_ena", &self.log_ena())
+            .field("log_mode", &self.log_mode())
+            .field("log_mem_loop_enable", &self.log_mem_loop_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_SETTING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - reg_log_ena"]
     #[inline(always)]
diff --git a/esp32c3/src/bb/bbpd_ctrl.rs b/esp32c3/src/bb/bbpd_ctrl.rs
index 7e31e667bb..28cf2656e4 100644
--- a/esp32c3/src/bb/bbpd_ctrl.rs
+++ b/esp32c3/src/bb/bbpd_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BBPD_CTRL")
-            .field(
-                "dc_est_force_pd",
-                &format_args!("{}", self.dc_est_force_pd().bit()),
-            )
-            .field(
-                "dc_est_force_pu",
-                &format_args!("{}", self.dc_est_force_pu().bit()),
-            )
-            .field(
-                "fft_force_pd",
-                &format_args!("{}", self.fft_force_pd().bit()),
-            )
-            .field(
-                "fft_force_pu",
-                &format_args!("{}", self.fft_force_pu().bit()),
-            )
+            .field("dc_est_force_pd", &self.dc_est_force_pd())
+            .field("dc_est_force_pu", &self.dc_est_force_pu())
+            .field("fft_force_pd", &self.fft_force_pd())
+            .field("fft_force_pu", &self.fft_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BBPD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c3/src/dma/ahb_test.rs b/esp32c3/src/dma/ahb_test.rs
index a5ac5899ab..27da2686f3 100644
--- a/esp32c3/src/dma/ahb_test.rs
+++ b/esp32c3/src/dma/ahb_test.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_TEST")
-            .field(
-                "ahb_testmode",
-                &format_args!("{}", self.ahb_testmode().bits()),
-            )
-            .field(
-                "ahb_testaddr",
-                &format_args!("{}", self.ahb_testaddr().bits()),
-            )
+            .field("ahb_testmode", &self.ahb_testmode())
+            .field("ahb_testaddr", &self.ahb_testaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_TEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - reserved"]
     #[inline(always)]
diff --git a/esp32c3/src/dma/ch/in_conf0.rs b/esp32c3/src/dma/ch/in_conf0.rs
index 86cecf5d9f..4cd323f5d3 100644
--- a/esp32c3/src/dma/ch/in_conf0.rs
+++ b/esp32c3/src/dma/ch/in_conf0.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF0")
-            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
-            .field(
-                "in_loop_test",
-                &format_args!("{}", self.in_loop_test().bit()),
-            )
-            .field(
-                "indscr_burst_en",
-                &format_args!("{}", self.indscr_burst_en().bit()),
-            )
-            .field(
-                "in_data_burst_en",
-                &format_args!("{}", self.in_data_burst_en().bit()),
-            )
-            .field(
-                "mem_trans_en",
-                &format_args!("{}", self.mem_trans_en().bit()),
-            )
+            .field("in_rst", &self.in_rst())
+            .field("in_loop_test", &self.in_loop_test())
+            .field("indscr_burst_en", &self.indscr_burst_en())
+            .field("in_data_burst_en", &self.in_data_burst_en())
+            .field("mem_trans_en", &self.mem_trans_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
     #[inline(always)]
diff --git a/esp32c3/src/dma/ch/in_conf1.rs b/esp32c3/src/dma/ch/in_conf1.rs
index 748835195a..b974c77057 100644
--- a/esp32c3/src/dma/ch/in_conf1.rs
+++ b/esp32c3/src/dma/ch/in_conf1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF1")
-            .field(
-                "in_check_owner",
-                &format_args!("{}", self.in_check_owner().bit()),
-            )
+            .field("in_check_owner", &self.in_check_owner())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
diff --git a/esp32c3/src/dma/ch/in_dscr.rs b/esp32c3/src/dma/ch/in_dscr.rs
index e74ef4e6cd..56c85914b1 100644
--- a/esp32c3/src/dma/ch/in_dscr.rs
+++ b/esp32c3/src/dma/ch/in_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR")
-            .field(
-                "inlink_dscr",
-                &format_args!("{}", self.inlink_dscr().bits()),
-            )
+            .field("inlink_dscr", &self.inlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_IN_DSCR_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_SPEC;
 impl crate::RegisterSpec for IN_DSCR_SPEC {
diff --git a/esp32c3/src/dma/ch/in_dscr_bf0.rs b/esp32c3/src/dma/ch/in_dscr_bf0.rs
index eaad9c8cc9..0bc2f59f68 100644
--- a/esp32c3/src/dma/ch/in_dscr_bf0.rs
+++ b/esp32c3/src/dma/ch/in_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF0")
-            .field(
-                "inlink_dscr_bf0",
-                &format_args!("{}", self.inlink_dscr_bf0().bits()),
-            )
+            .field("inlink_dscr_bf0", &self.inlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_IN_DSCR_BF0_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for IN_DSCR_BF0_SPEC {
diff --git a/esp32c3/src/dma/ch/in_dscr_bf1.rs b/esp32c3/src/dma/ch/in_dscr_bf1.rs
index 6fd8b46b77..d11bdd1b7a 100644
--- a/esp32c3/src/dma/ch/in_dscr_bf1.rs
+++ b/esp32c3/src/dma/ch/in_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF1")
-            .field(
-                "inlink_dscr_bf1",
-                &format_args!("{}", self.inlink_dscr_bf1().bits()),
-            )
+            .field("inlink_dscr_bf1", &self.inlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_IN_DSCR_BF1_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for IN_DSCR_BF1_SPEC {
diff --git a/esp32c3/src/dma/ch/in_err_eof_des_addr.rs b/esp32c3/src/dma/ch/in_err_eof_des_addr.rs
index 139a0113da..8bb5db9ad4 100644
--- a/esp32c3/src/dma/ch/in_err_eof_des_addr.rs
+++ b/esp32c3/src/dma/ch/in_err_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_ERR_EOF_DES_ADDR")
-            .field(
-                "in_err_eof_des_addr",
-                &format_args!("{}", self.in_err_eof_des_addr().bits()),
-            )
+            .field("in_err_eof_des_addr", &self.in_err_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_ERR_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_ERR_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_SPEC {
diff --git a/esp32c3/src/dma/ch/in_link.rs b/esp32c3/src/dma/ch/in_link.rs
index cafde6fdeb..b93d563052 100644
--- a/esp32c3/src/dma/ch/in_link.rs
+++ b/esp32c3/src/dma/ch/in_link.rs
@@ -60,33 +60,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_LINK")
-            .field(
-                "inlink_addr",
-                &format_args!("{}", self.inlink_addr().bits()),
-            )
-            .field(
-                "inlink_auto_ret",
-                &format_args!("{}", self.inlink_auto_ret().bit()),
-            )
-            .field("inlink_stop", &format_args!("{}", self.inlink_stop().bit()))
-            .field(
-                "inlink_start",
-                &format_args!("{}", self.inlink_start().bit()),
-            )
-            .field(
-                "inlink_restart",
-                &format_args!("{}", self.inlink_restart().bit()),
-            )
-            .field("inlink_park", &format_args!("{}", self.inlink_park().bit()))
+            .field("inlink_addr", &self.inlink_addr())
+            .field("inlink_auto_ret", &self.inlink_auto_ret())
+            .field("inlink_stop", &self.inlink_stop())
+            .field("inlink_start", &self.inlink_start())
+            .field("inlink_restart", &self.inlink_restart())
+            .field("inlink_park", &self.inlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32c3/src/dma/ch/in_peri_sel.rs b/esp32c3/src/dma/ch/in_peri_sel.rs
index faae5ed134..c8c7bee389 100644
--- a/esp32c3/src/dma/ch/in_peri_sel.rs
+++ b/esp32c3/src/dma/ch/in_peri_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_PERI_SEL")
-            .field(
-                "peri_in_sel",
-                &format_args!("{}", self.peri_in_sel().bits()),
-            )
+            .field("peri_in_sel", &self.peri_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_PERI_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."]
     #[inline(always)]
diff --git a/esp32c3/src/dma/ch/in_pop.rs b/esp32c3/src/dma/ch/in_pop.rs
index 9ea3ea9034..99fd4feca3 100644
--- a/esp32c3/src/dma/ch/in_pop.rs
+++ b/esp32c3/src/dma/ch/in_pop.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_POP")
-            .field(
-                "infifo_rdata",
-                &format_args!("{}", self.infifo_rdata().bits()),
-            )
-            .field("infifo_pop", &format_args!("{}", self.infifo_pop().bit()))
+            .field("infifo_rdata", &self.infifo_rdata())
+            .field("infifo_pop", &self.infifo_pop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_POP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."]
     #[inline(always)]
diff --git a/esp32c3/src/dma/ch/in_pri.rs b/esp32c3/src/dma/ch/in_pri.rs
index e8c8c8ce27..f2e9585ca5 100644
--- a/esp32c3/src/dma/ch/in_pri.rs
+++ b/esp32c3/src/dma/ch/in_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_PRI")
-            .field("rx_pri", &format_args!("{}", self.rx_pri().bits()))
+            .field("rx_pri", &self.rx_pri())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value, the higher of the priority."]
     #[inline(always)]
diff --git a/esp32c3/src/dma/ch/in_state.rs b/esp32c3/src/dma/ch/in_state.rs
index 4c9e8154ef..a0a70a2e6d 100644
--- a/esp32c3/src/dma/ch/in_state.rs
+++ b/esp32c3/src/dma/ch/in_state.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_STATE")
-            .field(
-                "inlink_dscr_addr",
-                &format_args!("{}", self.inlink_dscr_addr().bits()),
-            )
-            .field(
-                "in_dscr_state",
-                &format_args!("{}", self.in_dscr_state().bits()),
-            )
-            .field("in_state", &format_args!("{}", self.in_state().bits()))
+            .field("inlink_dscr_addr", &self.inlink_dscr_addr())
+            .field("in_dscr_state", &self.in_dscr_state())
+            .field("in_state", &self.in_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_IN_STATE_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_STATE_SPEC;
 impl crate::RegisterSpec for IN_STATE_SPEC {
diff --git a/esp32c3/src/dma/ch/in_suc_eof_des_addr.rs b/esp32c3/src/dma/ch/in_suc_eof_des_addr.rs
index 2858f6eae2..a669061d06 100644
--- a/esp32c3/src/dma/ch/in_suc_eof_des_addr.rs
+++ b/esp32c3/src/dma/ch/in_suc_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_SUC_EOF_DES_ADDR")
-            .field(
-                "in_suc_eof_des_addr",
-                &format_args!("{}", self.in_suc_eof_des_addr().bits()),
-            )
+            .field("in_suc_eof_des_addr", &self.in_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SUC_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SUC_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_SPEC {
diff --git a/esp32c3/src/dma/ch/infifo_status.rs b/esp32c3/src/dma/ch/infifo_status.rs
index c789296be5..e1e405141c 100644
--- a/esp32c3/src/dma/ch/infifo_status.rs
+++ b/esp32c3/src/dma/ch/infifo_status.rs
@@ -62,41 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INFIFO_STATUS")
-            .field("infifo_full", &format_args!("{}", self.infifo_full().bit()))
-            .field(
-                "infifo_empty",
-                &format_args!("{}", self.infifo_empty().bit()),
-            )
-            .field("infifo_cnt", &format_args!("{}", self.infifo_cnt().bits()))
-            .field(
-                "in_remain_under_1b",
-                &format_args!("{}", self.in_remain_under_1b().bit()),
-            )
-            .field(
-                "in_remain_under_2b",
-                &format_args!("{}", self.in_remain_under_2b().bit()),
-            )
-            .field(
-                "in_remain_under_3b",
-                &format_args!("{}", self.in_remain_under_3b().bit()),
-            )
-            .field(
-                "in_remain_under_4b",
-                &format_args!("{}", self.in_remain_under_4b().bit()),
-            )
-            .field(
-                "in_buf_hungry",
-                &format_args!("{}", self.in_buf_hungry().bit()),
-            )
+            .field("infifo_full", &self.infifo_full())
+            .field("infifo_empty", &self.infifo_empty())
+            .field("infifo_cnt", &self.infifo_cnt())
+            .field("in_remain_under_1b", &self.in_remain_under_1b())
+            .field("in_remain_under_2b", &self.in_remain_under_2b())
+            .field("in_remain_under_3b", &self.in_remain_under_3b())
+            .field("in_remain_under_4b", &self.in_remain_under_4b())
+            .field("in_buf_hungry", &self.in_buf_hungry())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_INFIFO_STATUS_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for INFIFO_STATUS_SPEC {
diff --git a/esp32c3/src/dma/ch/out_conf0.rs b/esp32c3/src/dma/ch/out_conf0.rs
index e9b56e54df..093cf4b2e7 100644
--- a/esp32c3/src/dma/ch/out_conf0.rs
+++ b/esp32c3/src/dma/ch/out_conf0.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CONF0")
-            .field("out_rst", &format_args!("{}", self.out_rst().bit()))
-            .field(
-                "out_loop_test",
-                &format_args!("{}", self.out_loop_test().bit()),
-            )
-            .field(
-                "out_auto_wrback",
-                &format_args!("{}", self.out_auto_wrback().bit()),
-            )
-            .field(
-                "out_eof_mode",
-                &format_args!("{}", self.out_eof_mode().bit()),
-            )
-            .field(
-                "outdscr_burst_en",
-                &format_args!("{}", self.outdscr_burst_en().bit()),
-            )
-            .field(
-                "out_data_burst_en",
-                &format_args!("{}", self.out_data_burst_en().bit()),
-            )
+            .field("out_rst", &self.out_rst())
+            .field("out_loop_test", &self.out_loop_test())
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("out_eof_mode", &self.out_eof_mode())
+            .field("outdscr_burst_en", &self.outdscr_burst_en())
+            .field("out_data_burst_en", &self.out_data_burst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."]
     #[inline(always)]
diff --git a/esp32c3/src/dma/ch/out_conf1.rs b/esp32c3/src/dma/ch/out_conf1.rs
index ef66aafcff..cc807db11c 100644
--- a/esp32c3/src/dma/ch/out_conf1.rs
+++ b/esp32c3/src/dma/ch/out_conf1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CONF1")
-            .field(
-                "out_check_owner",
-                &format_args!("{}", self.out_check_owner().bit()),
-            )
+            .field("out_check_owner", &self.out_check_owner())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
diff --git a/esp32c3/src/dma/ch/out_dscr.rs b/esp32c3/src/dma/ch/out_dscr.rs
index 48eb84fb2a..333c3c8faf 100644
--- a/esp32c3/src/dma/ch/out_dscr.rs
+++ b/esp32c3/src/dma/ch/out_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR")
-            .field(
-                "outlink_dscr",
-                &format_args!("{}", self.outlink_dscr().bits()),
-            )
+            .field("outlink_dscr", &self.outlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_OUT_DSCR_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_SPEC {
diff --git a/esp32c3/src/dma/ch/out_dscr_bf0.rs b/esp32c3/src/dma/ch/out_dscr_bf0.rs
index 920aa77731..ad66c7d030 100644
--- a/esp32c3/src/dma/ch/out_dscr_bf0.rs
+++ b/esp32c3/src/dma/ch/out_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR_BF0")
-            .field(
-                "outlink_dscr_bf0",
-                &format_args!("{}", self.outlink_dscr_bf0().bits()),
-            )
+            .field("outlink_dscr_bf0", &self.outlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_OUT_DSCR_BF0_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_BF0_SPEC {
diff --git a/esp32c3/src/dma/ch/out_dscr_bf1.rs b/esp32c3/src/dma/ch/out_dscr_bf1.rs
index 832e1d146f..229b0c1196 100644
--- a/esp32c3/src/dma/ch/out_dscr_bf1.rs
+++ b/esp32c3/src/dma/ch/out_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR_BF1")
-            .field(
-                "outlink_dscr_bf1",
-                &format_args!("{}", self.outlink_dscr_bf1().bits()),
-            )
+            .field("outlink_dscr_bf1", &self.outlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_OUT_DSCR_BF1_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_BF1_SPEC {
diff --git a/esp32c3/src/dma/ch/out_eof_bfr_des_addr.rs b/esp32c3/src/dma/ch/out_eof_bfr_des_addr.rs
index bf376f49d0..0d89d6c0fa 100644
--- a/esp32c3/src/dma/ch/out_eof_bfr_des_addr.rs
+++ b/esp32c3/src/dma/ch/out_eof_bfr_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_BFR_DES_ADDR")
-            .field(
-                "out_eof_bfr_des_addr",
-                &format_args!("{}", self.out_eof_bfr_des_addr().bits()),
-            )
+            .field("out_eof_bfr_des_addr", &self.out_eof_bfr_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_BFR_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_bfr_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_BFR_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_SPEC {
diff --git a/esp32c3/src/dma/ch/out_eof_des_addr.rs b/esp32c3/src/dma/ch/out_eof_des_addr.rs
index af80ad16ae..dd9c7dc379 100644
--- a/esp32c3/src/dma/ch/out_eof_des_addr.rs
+++ b/esp32c3/src/dma/ch/out_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_DES_ADDR")
-            .field(
-                "out_eof_des_addr",
-                &format_args!("{}", self.out_eof_des_addr().bits()),
-            )
+            .field("out_eof_des_addr", &self.out_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_OUT_EOF_DES_ADDR_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_DES_ADDR_SPEC {
diff --git a/esp32c3/src/dma/ch/out_link.rs b/esp32c3/src/dma/ch/out_link.rs
index 7a7b8b99a3..bfeb1647d5 100644
--- a/esp32c3/src/dma/ch/out_link.rs
+++ b/esp32c3/src/dma/ch/out_link.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_LINK")
-            .field(
-                "outlink_addr",
-                &format_args!("{}", self.outlink_addr().bits()),
-            )
-            .field(
-                "outlink_stop",
-                &format_args!("{}", self.outlink_stop().bit()),
-            )
-            .field(
-                "outlink_start",
-                &format_args!("{}", self.outlink_start().bit()),
-            )
-            .field(
-                "outlink_restart",
-                &format_args!("{}", self.outlink_restart().bit()),
-            )
-            .field(
-                "outlink_park",
-                &format_args!("{}", self.outlink_park().bit()),
-            )
+            .field("outlink_addr", &self.outlink_addr())
+            .field("outlink_stop", &self.outlink_stop())
+            .field("outlink_start", &self.outlink_start())
+            .field("outlink_restart", &self.outlink_restart())
+            .field("outlink_park", &self.outlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32c3/src/dma/ch/out_peri_sel.rs b/esp32c3/src/dma/ch/out_peri_sel.rs
index bb9eeb200a..07816e8dcd 100644
--- a/esp32c3/src/dma/ch/out_peri_sel.rs
+++ b/esp32c3/src/dma/ch/out_peri_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PERI_SEL")
-            .field(
-                "peri_out_sel",
-                &format_args!("{}", self.peri_out_sel().bits()),
-            )
+            .field("peri_out_sel", &self.peri_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PERI_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC."]
     #[inline(always)]
diff --git a/esp32c3/src/dma/ch/out_pri.rs b/esp32c3/src/dma/ch/out_pri.rs
index 5ea7f98279..bbdb19628c 100644
--- a/esp32c3/src/dma/ch/out_pri.rs
+++ b/esp32c3/src/dma/ch/out_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PRI")
-            .field("tx_pri", &format_args!("{}", self.tx_pri().bits()))
+            .field("tx_pri", &self.tx_pri())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value, the higher of the priority."]
     #[inline(always)]
diff --git a/esp32c3/src/dma/ch/out_push.rs b/esp32c3/src/dma/ch/out_push.rs
index 9489e7584a..13d4f3a1a1 100644
--- a/esp32c3/src/dma/ch/out_push.rs
+++ b/esp32c3/src/dma/ch/out_push.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PUSH")
-            .field(
-                "outfifo_wdata",
-                &format_args!("{}", self.outfifo_wdata().bits()),
-            )
-            .field(
-                "outfifo_push",
-                &format_args!("{}", self.outfifo_push().bit()),
-            )
+            .field("outfifo_wdata", &self.outfifo_wdata())
+            .field("outfifo_push", &self.outfifo_push())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PUSH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."]
     #[inline(always)]
diff --git a/esp32c3/src/dma/ch/out_state.rs b/esp32c3/src/dma/ch/out_state.rs
index eac446b3fe..ff7cd28120 100644
--- a/esp32c3/src/dma/ch/out_state.rs
+++ b/esp32c3/src/dma/ch/out_state.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_STATE")
-            .field(
-                "outlink_dscr_addr",
-                &format_args!("{}", self.outlink_dscr_addr().bits()),
-            )
-            .field(
-                "out_dscr_state",
-                &format_args!("{}", self.out_dscr_state().bits()),
-            )
-            .field("out_state", &format_args!("{}", self.out_state().bits()))
+            .field("outlink_dscr_addr", &self.outlink_dscr_addr())
+            .field("out_dscr_state", &self.out_dscr_state())
+            .field("out_state", &self.out_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_OUT_STATE_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_STATE_SPEC;
 impl crate::RegisterSpec for OUT_STATE_SPEC {
diff --git a/esp32c3/src/dma/ch/outfifo_status.rs b/esp32c3/src/dma/ch/outfifo_status.rs
index 041edec34d..03becc8d02 100644
--- a/esp32c3/src/dma/ch/outfifo_status.rs
+++ b/esp32c3/src/dma/ch/outfifo_status.rs
@@ -55,43 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTFIFO_STATUS")
-            .field(
-                "outfifo_full",
-                &format_args!("{}", self.outfifo_full().bit()),
-            )
-            .field(
-                "outfifo_empty",
-                &format_args!("{}", self.outfifo_empty().bit()),
-            )
-            .field(
-                "outfifo_cnt",
-                &format_args!("{}", self.outfifo_cnt().bits()),
-            )
-            .field(
-                "out_remain_under_1b",
-                &format_args!("{}", self.out_remain_under_1b().bit()),
-            )
-            .field(
-                "out_remain_under_2b",
-                &format_args!("{}", self.out_remain_under_2b().bit()),
-            )
-            .field(
-                "out_remain_under_3b",
-                &format_args!("{}", self.out_remain_under_3b().bit()),
-            )
-            .field(
-                "out_remain_under_4b",
-                &format_args!("{}", self.out_remain_under_4b().bit()),
-            )
+            .field("outfifo_full", &self.outfifo_full())
+            .field("outfifo_empty", &self.outfifo_empty())
+            .field("outfifo_cnt", &self.outfifo_cnt())
+            .field("out_remain_under_1b", &self.out_remain_under_1b())
+            .field("out_remain_under_2b", &self.out_remain_under_2b())
+            .field("out_remain_under_3b", &self.out_remain_under_3b())
+            .field("out_remain_under_4b", &self.out_remain_under_4b())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_OUTFIFO_STATUS_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for OUTFIFO_STATUS_SPEC {
diff --git a/esp32c3/src/dma/date.rs b/esp32c3/src/dma/date.rs
index d076c5c731..490a7f0d50 100644
--- a/esp32c3/src/dma/date.rs
+++ b/esp32c3/src/dma/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/dma/int_ch/ena.rs b/esp32c3/src/dma/int_ch/ena.rs
index dde917e343..4722681149 100644
--- a/esp32c3/src/dma/int_ch/ena.rs
+++ b/esp32c3/src/dma/int_ch/ena.rs
@@ -125,37 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENA")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c3/src/dma/int_ch/raw.rs b/esp32c3/src/dma/int_ch/raw.rs
index fdfe355480..cffd672123 100644
--- a/esp32c3/src/dma/int_ch/raw.rs
+++ b/esp32c3/src/dma/int_ch/raw.rs
@@ -125,37 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RAW")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
     #[inline(always)]
diff --git a/esp32c3/src/dma/int_ch/st.rs b/esp32c3/src/dma/int_ch/st.rs
index b5efca6c32..53f8894444 100644
--- a/esp32c3/src/dma/int_ch/st.rs
+++ b/esp32c3/src/dma/int_ch/st.rs
@@ -97,37 +97,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ST")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA_INT_ST_CH0_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ST_SPEC;
 impl crate::RegisterSpec for ST_SPEC {
diff --git a/esp32c3/src/dma/misc_conf.rs b/esp32c3/src/dma/misc_conf.rs
index d3c2265842..d9a0cd0b79 100644
--- a/esp32c3/src/dma/misc_conf.rs
+++ b/esp32c3/src/dma/misc_conf.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC_CONF")
-            .field(
-                "ahbm_rst_inter",
-                &format_args!("{}", self.ahbm_rst_inter().bit()),
-            )
-            .field("arb_pri_dis", &format_args!("{}", self.arb_pri_dis().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("ahbm_rst_inter", &self.ahbm_rst_inter())
+            .field("arb_pri_dis", &self.arb_pri_dis())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit, then clear this bit to reset the internal ahb FSM."]
     #[inline(always)]
diff --git a/esp32c3/src/ds/box_mem.rs b/esp32c3/src/ds/box_mem.rs
index cbc5e04146..af6085c630 100644
--- a/esp32c3/src/ds/box_mem.rs
+++ b/esp32c3/src/ds/box_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BOX_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores BOX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`box_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`box_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BOX_MEM_SPEC;
diff --git a/esp32c3/src/ds/date.rs b/esp32c3/src/ds/date.rs
index 0b73492be1..97e7b03565 100644
--- a/esp32c3/src/ds/date.rs
+++ b/esp32c3/src/ds/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/ds/iv_mem.rs b/esp32c3/src/ds/iv_mem.rs
index c51ece9da1..7be27e59f5 100644
--- a/esp32c3/src/ds/iv_mem.rs
+++ b/esp32c3/src/ds/iv_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IV_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "IV block data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iv_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iv_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IV_MEM_SPEC;
diff --git a/esp32c3/src/ds/m_mem.rs b/esp32c3/src/ds/m_mem.rs
index feb455544d..34f49f49a5 100644
--- a/esp32c3/src/ds/m_mem.rs
+++ b/esp32c3/src/ds/m_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct M_MEM_SPEC;
diff --git a/esp32c3/src/ds/query_busy.rs b/esp32c3/src/ds/query_busy.rs
index 28c895caf6..ab7489a518 100644
--- a/esp32c3/src/ds/query_busy.rs
+++ b/esp32c3/src/ds/query_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_BUSY")
-            .field("query_busy", &format_args!("{}", self.query_busy().bit()))
+            .field("query_busy", &self.query_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DS query busy register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_BUSY_SPEC;
 impl crate::RegisterSpec for QUERY_BUSY_SPEC {
diff --git a/esp32c3/src/ds/query_check.rs b/esp32c3/src/ds/query_check.rs
index 278370e20f..e1d1c02fe7 100644
--- a/esp32c3/src/ds/query_check.rs
+++ b/esp32c3/src/ds/query_check.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_CHECK")
-            .field("md_error", &format_args!("{}", self.md_error().bit()))
-            .field("padding_bad", &format_args!("{}", self.padding_bad().bit()))
+            .field("md_error", &self.md_error())
+            .field("padding_bad", &self.padding_bad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_CHECK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DS query check result register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_check::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_CHECK_SPEC;
 impl crate::RegisterSpec for QUERY_CHECK_SPEC {
diff --git a/esp32c3/src/ds/query_key_wrong.rs b/esp32c3/src/ds/query_key_wrong.rs
index 30a1e7aae4..7ce4bf99a0 100644
--- a/esp32c3/src/ds/query_key_wrong.rs
+++ b/esp32c3/src/ds/query_key_wrong.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_KEY_WRONG")
-            .field(
-                "query_key_wrong",
-                &format_args!("{}", self.query_key_wrong().bits()),
-            )
+            .field("query_key_wrong", &self.query_key_wrong())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_KEY_WRONG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DS query key-wrong counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_key_wrong::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_KEY_WRONG_SPEC;
 impl crate::RegisterSpec for QUERY_KEY_WRONG_SPEC {
diff --git a/esp32c3/src/ds/rb_mem.rs b/esp32c3/src/ds/rb_mem.rs
index 601da234a3..c7e0a211be 100644
--- a/esp32c3/src/ds/rb_mem.rs
+++ b/esp32c3/src/ds/rb_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RB_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores Rb\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rb_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rb_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RB_MEM_SPEC;
diff --git a/esp32c3/src/ds/x_mem.rs b/esp32c3/src/ds/x_mem.rs
index b018ad10ba..5cfb1f6eb6 100644
--- a/esp32c3/src/ds/x_mem.rs
+++ b/esp32c3/src/ds/x_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<X_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores X\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`x_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`x_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct X_MEM_SPEC;
diff --git a/esp32c3/src/ds/y_mem.rs b/esp32c3/src/ds/y_mem.rs
index 00ad225968..3376d35f4e 100644
--- a/esp32c3/src/ds/y_mem.rs
+++ b/esp32c3/src/ds/y_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Y_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores Y\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Y_MEM_SPEC;
diff --git a/esp32c3/src/ds/z_mem.rs b/esp32c3/src/ds/z_mem.rs
index de03c7e5de..978b2c0d66 100644
--- a/esp32c3/src/ds/z_mem.rs
+++ b/esp32c3/src/ds/z_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Z_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Z_MEM_SPEC;
diff --git a/esp32c3/src/efuse/clk.rs b/esp32c3/src/efuse/clk.rs
index aecb3b96c6..dc33b42611 100644
--- a/esp32c3/src/efuse/clk.rs
+++ b/esp32c3/src/efuse/clk.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK")
-            .field(
-                "efuse_mem_force_pd",
-                &format_args!("{}", self.efuse_mem_force_pd().bit()),
-            )
-            .field(
-                "mem_clk_force_on",
-                &format_args!("{}", self.mem_clk_force_on().bit()),
-            )
-            .field(
-                "efuse_mem_force_pu",
-                &format_args!("{}", self.efuse_mem_force_pu().bit()),
-            )
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("efuse_mem_force_pd", &self.efuse_mem_force_pd())
+            .field("mem_clk_force_on", &self.mem_clk_force_on())
+            .field("efuse_mem_force_pu", &self.efuse_mem_force_pu())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to force eFuse SRAM into power-saving mode."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/cmd.rs b/esp32c3/src/efuse/cmd.rs
index 8dee79bc65..094d443be3 100644
--- a/esp32c3/src/efuse/cmd.rs
+++ b/esp32c3/src/efuse/cmd.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("read_cmd", &format_args!("{}", self.read_cmd().bit()))
-            .field("pgm_cmd", &format_args!("{}", self.pgm_cmd().bit()))
-            .field("blk_num", &format_args!("{}", self.blk_num().bits()))
+            .field("read_cmd", &self.read_cmd())
+            .field("pgm_cmd", &self.pgm_cmd())
+            .field("blk_num", &self.blk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to send read command."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/conf.rs b/esp32c3/src/efuse/conf.rs
index 284405f03b..e43dff5b4e 100644
--- a/esp32c3/src/efuse/conf.rs
+++ b/esp32c3/src/efuse/conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("op_code", &format_args!("{}", self.op_code().bits()))
+            .field("op_code", &self.op_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - 0x5A5A: Operate programming command 0x5AA5: Operate read command."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/dac_conf.rs b/esp32c3/src/efuse/dac_conf.rs
index 46081e022e..e9db91d486 100644
--- a/esp32c3/src/efuse/dac_conf.rs
+++ b/esp32c3/src/efuse/dac_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DAC_CONF")
-            .field(
-                "dac_clk_div",
-                &format_args!("{}", self.dac_clk_div().bits()),
-            )
-            .field(
-                "dac_clk_pad_sel",
-                &format_args!("{}", self.dac_clk_pad_sel().bit()),
-            )
-            .field("dac_num", &format_args!("{}", self.dac_num().bits()))
-            .field("oe_clr", &format_args!("{}", self.oe_clr().bit()))
+            .field("dac_clk_div", &self.dac_clk_div())
+            .field("dac_clk_pad_sel", &self.dac_clk_pad_sel())
+            .field("dac_num", &self.dac_num())
+            .field("oe_clr", &self.oe_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DAC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Controls the division factor of the rising clock of the programming voltage."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/date.rs b/esp32c3/src/efuse/date.rs
index 0ea3a943bb..aa1cd2e44b 100644
--- a/esp32c3/src/efuse/date.rs
+++ b/esp32c3/src/efuse/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/efuse/int_ena.rs b/esp32c3/src/efuse/int_ena.rs
index 6386df2821..0020c7e668 100644
--- a/esp32c3/src/efuse/int_ena.rs
+++ b/esp32c3/src/efuse/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable signal for read_done interrupt."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/int_raw.rs b/esp32c3/src/efuse/int_raw.rs
index 914c4f8c84..3d99203c2c 100644
--- a/esp32c3/src/efuse/int_raw.rs
+++ b/esp32c3/src/efuse/int_raw.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw bit signal for read_done interrupt."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/int_st.rs b/esp32c3/src/efuse/int_st.rs
index 898ceb8e8b..efba508ff2 100644
--- a/esp32c3/src/efuse/int_st.rs
+++ b/esp32c3/src/efuse/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c3/src/efuse/pgm_check_value0.rs b/esp32c3/src/efuse/pgm_check_value0.rs
index c116858f94..a6d3c26060 100644
--- a/esp32c3/src/efuse/pgm_check_value0.rs
+++ b/esp32c3/src/efuse/pgm_check_value0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE0")
-            .field(
-                "pgm_rs_data_0",
-                &format_args!("{}", self.pgm_rs_data_0().bits()),
-            )
+            .field("pgm_rs_data_0", &self.pgm_rs_data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 0th 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/pgm_check_value1.rs b/esp32c3/src/efuse/pgm_check_value1.rs
index 331e741927..875b090b36 100644
--- a/esp32c3/src/efuse/pgm_check_value1.rs
+++ b/esp32c3/src/efuse/pgm_check_value1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE1")
-            .field(
-                "pgm_rs_data_1",
-                &format_args!("{}", self.pgm_rs_data_1().bits()),
-            )
+            .field("pgm_rs_data_1", &self.pgm_rs_data_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 1st 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/pgm_check_value2.rs b/esp32c3/src/efuse/pgm_check_value2.rs
index 57aaf58855..571fe98175 100644
--- a/esp32c3/src/efuse/pgm_check_value2.rs
+++ b/esp32c3/src/efuse/pgm_check_value2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE2")
-            .field(
-                "pgm_rs_data_2",
-                &format_args!("{}", self.pgm_rs_data_2().bits()),
-            )
+            .field("pgm_rs_data_2", &self.pgm_rs_data_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 2nd 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/pgm_data0.rs b/esp32c3/src/efuse/pgm_data0.rs
index 3cc5ffca3b..b04bf3a372 100644
--- a/esp32c3/src/efuse/pgm_data0.rs
+++ b/esp32c3/src/efuse/pgm_data0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA0")
-            .field("pgm_data_0", &format_args!("{}", self.pgm_data_0().bits()))
+            .field("pgm_data_0", &self.pgm_data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 0th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/pgm_data1.rs b/esp32c3/src/efuse/pgm_data1.rs
index e01b369302..4d0e9f9794 100644
--- a/esp32c3/src/efuse/pgm_data1.rs
+++ b/esp32c3/src/efuse/pgm_data1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA1")
-            .field("pgm_data_1", &format_args!("{}", self.pgm_data_1().bits()))
+            .field("pgm_data_1", &self.pgm_data_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 1st 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/pgm_data2.rs b/esp32c3/src/efuse/pgm_data2.rs
index bb62a4d24f..f04c46cc20 100644
--- a/esp32c3/src/efuse/pgm_data2.rs
+++ b/esp32c3/src/efuse/pgm_data2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA2")
-            .field("pgm_data_2", &format_args!("{}", self.pgm_data_2().bits()))
+            .field("pgm_data_2", &self.pgm_data_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 2nd 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/pgm_data3.rs b/esp32c3/src/efuse/pgm_data3.rs
index 835e17347f..50d284df5b 100644
--- a/esp32c3/src/efuse/pgm_data3.rs
+++ b/esp32c3/src/efuse/pgm_data3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA3")
-            .field("pgm_data_3", &format_args!("{}", self.pgm_data_3().bits()))
+            .field("pgm_data_3", &self.pgm_data_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 3rd 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/pgm_data4.rs b/esp32c3/src/efuse/pgm_data4.rs
index 6806135803..0de88ae64c 100644
--- a/esp32c3/src/efuse/pgm_data4.rs
+++ b/esp32c3/src/efuse/pgm_data4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA4")
-            .field("pgm_data_4", &format_args!("{}", self.pgm_data_4().bits()))
+            .field("pgm_data_4", &self.pgm_data_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 4th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/pgm_data5.rs b/esp32c3/src/efuse/pgm_data5.rs
index e76d9ed490..839f0680b0 100644
--- a/esp32c3/src/efuse/pgm_data5.rs
+++ b/esp32c3/src/efuse/pgm_data5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA5")
-            .field("pgm_data_5", &format_args!("{}", self.pgm_data_5().bits()))
+            .field("pgm_data_5", &self.pgm_data_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 5th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/pgm_data6.rs b/esp32c3/src/efuse/pgm_data6.rs
index e50d19c967..f66b3f5d01 100644
--- a/esp32c3/src/efuse/pgm_data6.rs
+++ b/esp32c3/src/efuse/pgm_data6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA6")
-            .field("pgm_data_6", &format_args!("{}", self.pgm_data_6().bits()))
+            .field("pgm_data_6", &self.pgm_data_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 6th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/pgm_data7.rs b/esp32c3/src/efuse/pgm_data7.rs
index 886fcdcb3c..f8a8d36257 100644
--- a/esp32c3/src/efuse/pgm_data7.rs
+++ b/esp32c3/src/efuse/pgm_data7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA7")
-            .field("pgm_data_7", &format_args!("{}", self.pgm_data_7().bits()))
+            .field("pgm_data_7", &self.pgm_data_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 7th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/rd_key0_data0.rs b/esp32c3/src/efuse/rd_key0_data0.rs
index c4170de549..a46c1ad944 100644
--- a/esp32c3/src/efuse/rd_key0_data0.rs
+++ b/esp32c3/src/efuse/rd_key0_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA0")
-            .field("key0_data0", &format_args!("{}", self.key0_data0().bits()))
+            .field("key0_data0", &self.key0_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA0_SPEC {
diff --git a/esp32c3/src/efuse/rd_key0_data1.rs b/esp32c3/src/efuse/rd_key0_data1.rs
index c545a21ca4..d802c4324d 100644
--- a/esp32c3/src/efuse/rd_key0_data1.rs
+++ b/esp32c3/src/efuse/rd_key0_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA1")
-            .field("key0_data1", &format_args!("{}", self.key0_data1().bits()))
+            .field("key0_data1", &self.key0_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA1_SPEC {
diff --git a/esp32c3/src/efuse/rd_key0_data2.rs b/esp32c3/src/efuse/rd_key0_data2.rs
index 75a9d79d9b..c125d21c76 100644
--- a/esp32c3/src/efuse/rd_key0_data2.rs
+++ b/esp32c3/src/efuse/rd_key0_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA2")
-            .field("key0_data2", &format_args!("{}", self.key0_data2().bits()))
+            .field("key0_data2", &self.key0_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA2_SPEC {
diff --git a/esp32c3/src/efuse/rd_key0_data3.rs b/esp32c3/src/efuse/rd_key0_data3.rs
index ce90c2cf18..a9043355cf 100644
--- a/esp32c3/src/efuse/rd_key0_data3.rs
+++ b/esp32c3/src/efuse/rd_key0_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA3")
-            .field("key0_data3", &format_args!("{}", self.key0_data3().bits()))
+            .field("key0_data3", &self.key0_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA3_SPEC {
diff --git a/esp32c3/src/efuse/rd_key0_data4.rs b/esp32c3/src/efuse/rd_key0_data4.rs
index f27e3d5095..d80cc60787 100644
--- a/esp32c3/src/efuse/rd_key0_data4.rs
+++ b/esp32c3/src/efuse/rd_key0_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA4")
-            .field("key0_data4", &format_args!("{}", self.key0_data4().bits()))
+            .field("key0_data4", &self.key0_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA4_SPEC {
diff --git a/esp32c3/src/efuse/rd_key0_data5.rs b/esp32c3/src/efuse/rd_key0_data5.rs
index d4fbdcadc6..0df76ff5a6 100644
--- a/esp32c3/src/efuse/rd_key0_data5.rs
+++ b/esp32c3/src/efuse/rd_key0_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA5")
-            .field("key0_data5", &format_args!("{}", self.key0_data5().bits()))
+            .field("key0_data5", &self.key0_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA5_SPEC {
diff --git a/esp32c3/src/efuse/rd_key0_data6.rs b/esp32c3/src/efuse/rd_key0_data6.rs
index 85a08de8fa..eb4c2beec8 100644
--- a/esp32c3/src/efuse/rd_key0_data6.rs
+++ b/esp32c3/src/efuse/rd_key0_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA6")
-            .field("key0_data6", &format_args!("{}", self.key0_data6().bits()))
+            .field("key0_data6", &self.key0_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA6_SPEC {
diff --git a/esp32c3/src/efuse/rd_key0_data7.rs b/esp32c3/src/efuse/rd_key0_data7.rs
index 2cfe17e0d2..b453d144d1 100644
--- a/esp32c3/src/efuse/rd_key0_data7.rs
+++ b/esp32c3/src/efuse/rd_key0_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA7")
-            .field("key0_data7", &format_args!("{}", self.key0_data7().bits()))
+            .field("key0_data7", &self.key0_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA7_SPEC {
diff --git a/esp32c3/src/efuse/rd_key1_data0.rs b/esp32c3/src/efuse/rd_key1_data0.rs
index 291c7485e1..cbdf301dd6 100644
--- a/esp32c3/src/efuse/rd_key1_data0.rs
+++ b/esp32c3/src/efuse/rd_key1_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA0")
-            .field("key1_data0", &format_args!("{}", self.key1_data0().bits()))
+            .field("key1_data0", &self.key1_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA0_SPEC {
diff --git a/esp32c3/src/efuse/rd_key1_data1.rs b/esp32c3/src/efuse/rd_key1_data1.rs
index 2b30399c9e..0d2ca792e8 100644
--- a/esp32c3/src/efuse/rd_key1_data1.rs
+++ b/esp32c3/src/efuse/rd_key1_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA1")
-            .field("key1_data1", &format_args!("{}", self.key1_data1().bits()))
+            .field("key1_data1", &self.key1_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA1_SPEC {
diff --git a/esp32c3/src/efuse/rd_key1_data2.rs b/esp32c3/src/efuse/rd_key1_data2.rs
index d19bb9bf8c..0cfb551fa0 100644
--- a/esp32c3/src/efuse/rd_key1_data2.rs
+++ b/esp32c3/src/efuse/rd_key1_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA2")
-            .field("key1_data2", &format_args!("{}", self.key1_data2().bits()))
+            .field("key1_data2", &self.key1_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA2_SPEC {
diff --git a/esp32c3/src/efuse/rd_key1_data3.rs b/esp32c3/src/efuse/rd_key1_data3.rs
index f392fa1939..0e48686024 100644
--- a/esp32c3/src/efuse/rd_key1_data3.rs
+++ b/esp32c3/src/efuse/rd_key1_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA3")
-            .field("key1_data3", &format_args!("{}", self.key1_data3().bits()))
+            .field("key1_data3", &self.key1_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA3_SPEC {
diff --git a/esp32c3/src/efuse/rd_key1_data4.rs b/esp32c3/src/efuse/rd_key1_data4.rs
index 9eec3ea746..7856929463 100644
--- a/esp32c3/src/efuse/rd_key1_data4.rs
+++ b/esp32c3/src/efuse/rd_key1_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA4")
-            .field("key1_data4", &format_args!("{}", self.key1_data4().bits()))
+            .field("key1_data4", &self.key1_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA4_SPEC {
diff --git a/esp32c3/src/efuse/rd_key1_data5.rs b/esp32c3/src/efuse/rd_key1_data5.rs
index abb6571e50..3e1c7a10ca 100644
--- a/esp32c3/src/efuse/rd_key1_data5.rs
+++ b/esp32c3/src/efuse/rd_key1_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA5")
-            .field("key1_data5", &format_args!("{}", self.key1_data5().bits()))
+            .field("key1_data5", &self.key1_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA5_SPEC {
diff --git a/esp32c3/src/efuse/rd_key1_data6.rs b/esp32c3/src/efuse/rd_key1_data6.rs
index 2480507f1d..f9e0c0b597 100644
--- a/esp32c3/src/efuse/rd_key1_data6.rs
+++ b/esp32c3/src/efuse/rd_key1_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA6")
-            .field("key1_data6", &format_args!("{}", self.key1_data6().bits()))
+            .field("key1_data6", &self.key1_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA6_SPEC {
diff --git a/esp32c3/src/efuse/rd_key1_data7.rs b/esp32c3/src/efuse/rd_key1_data7.rs
index e912db2958..3aae5b0aa5 100644
--- a/esp32c3/src/efuse/rd_key1_data7.rs
+++ b/esp32c3/src/efuse/rd_key1_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA7")
-            .field("key1_data7", &format_args!("{}", self.key1_data7().bits()))
+            .field("key1_data7", &self.key1_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA7_SPEC {
diff --git a/esp32c3/src/efuse/rd_key2_data0.rs b/esp32c3/src/efuse/rd_key2_data0.rs
index f4e6afd656..7213af4aa1 100644
--- a/esp32c3/src/efuse/rd_key2_data0.rs
+++ b/esp32c3/src/efuse/rd_key2_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA0")
-            .field("key2_data0", &format_args!("{}", self.key2_data0().bits()))
+            .field("key2_data0", &self.key2_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA0_SPEC {
diff --git a/esp32c3/src/efuse/rd_key2_data1.rs b/esp32c3/src/efuse/rd_key2_data1.rs
index c4742c50b6..e5c0bcfc43 100644
--- a/esp32c3/src/efuse/rd_key2_data1.rs
+++ b/esp32c3/src/efuse/rd_key2_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA1")
-            .field("key2_data1", &format_args!("{}", self.key2_data1().bits()))
+            .field("key2_data1", &self.key2_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA1_SPEC {
diff --git a/esp32c3/src/efuse/rd_key2_data2.rs b/esp32c3/src/efuse/rd_key2_data2.rs
index 5f49546147..7ae05d7b8b 100644
--- a/esp32c3/src/efuse/rd_key2_data2.rs
+++ b/esp32c3/src/efuse/rd_key2_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA2")
-            .field("key2_data2", &format_args!("{}", self.key2_data2().bits()))
+            .field("key2_data2", &self.key2_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA2_SPEC {
diff --git a/esp32c3/src/efuse/rd_key2_data3.rs b/esp32c3/src/efuse/rd_key2_data3.rs
index eb778f7774..b0856f695b 100644
--- a/esp32c3/src/efuse/rd_key2_data3.rs
+++ b/esp32c3/src/efuse/rd_key2_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA3")
-            .field("key2_data3", &format_args!("{}", self.key2_data3().bits()))
+            .field("key2_data3", &self.key2_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA3_SPEC {
diff --git a/esp32c3/src/efuse/rd_key2_data4.rs b/esp32c3/src/efuse/rd_key2_data4.rs
index 613b92fb18..f8cccf58ca 100644
--- a/esp32c3/src/efuse/rd_key2_data4.rs
+++ b/esp32c3/src/efuse/rd_key2_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA4")
-            .field("key2_data4", &format_args!("{}", self.key2_data4().bits()))
+            .field("key2_data4", &self.key2_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA4_SPEC {
diff --git a/esp32c3/src/efuse/rd_key2_data5.rs b/esp32c3/src/efuse/rd_key2_data5.rs
index f759177d7f..4b3e9fb766 100644
--- a/esp32c3/src/efuse/rd_key2_data5.rs
+++ b/esp32c3/src/efuse/rd_key2_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA5")
-            .field("key2_data5", &format_args!("{}", self.key2_data5().bits()))
+            .field("key2_data5", &self.key2_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA5_SPEC {
diff --git a/esp32c3/src/efuse/rd_key2_data6.rs b/esp32c3/src/efuse/rd_key2_data6.rs
index e4532e5ac7..25c9cf68ef 100644
--- a/esp32c3/src/efuse/rd_key2_data6.rs
+++ b/esp32c3/src/efuse/rd_key2_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA6")
-            .field("key2_data6", &format_args!("{}", self.key2_data6().bits()))
+            .field("key2_data6", &self.key2_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA6_SPEC {
diff --git a/esp32c3/src/efuse/rd_key2_data7.rs b/esp32c3/src/efuse/rd_key2_data7.rs
index 3cc83cb7e1..4a67033e6f 100644
--- a/esp32c3/src/efuse/rd_key2_data7.rs
+++ b/esp32c3/src/efuse/rd_key2_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA7")
-            .field("key2_data7", &format_args!("{}", self.key2_data7().bits()))
+            .field("key2_data7", &self.key2_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA7_SPEC {
diff --git a/esp32c3/src/efuse/rd_key3_data0.rs b/esp32c3/src/efuse/rd_key3_data0.rs
index b53838b293..edc175d9ea 100644
--- a/esp32c3/src/efuse/rd_key3_data0.rs
+++ b/esp32c3/src/efuse/rd_key3_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA0")
-            .field("key3_data0", &format_args!("{}", self.key3_data0().bits()))
+            .field("key3_data0", &self.key3_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA0_SPEC {
diff --git a/esp32c3/src/efuse/rd_key3_data1.rs b/esp32c3/src/efuse/rd_key3_data1.rs
index 9bab6de8e8..20834c399e 100644
--- a/esp32c3/src/efuse/rd_key3_data1.rs
+++ b/esp32c3/src/efuse/rd_key3_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA1")
-            .field("key3_data1", &format_args!("{}", self.key3_data1().bits()))
+            .field("key3_data1", &self.key3_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA1_SPEC {
diff --git a/esp32c3/src/efuse/rd_key3_data2.rs b/esp32c3/src/efuse/rd_key3_data2.rs
index 8642471a16..e957b7fe84 100644
--- a/esp32c3/src/efuse/rd_key3_data2.rs
+++ b/esp32c3/src/efuse/rd_key3_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA2")
-            .field("key3_data2", &format_args!("{}", self.key3_data2().bits()))
+            .field("key3_data2", &self.key3_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA2_SPEC {
diff --git a/esp32c3/src/efuse/rd_key3_data3.rs b/esp32c3/src/efuse/rd_key3_data3.rs
index dbc82ce3e9..f3b0215503 100644
--- a/esp32c3/src/efuse/rd_key3_data3.rs
+++ b/esp32c3/src/efuse/rd_key3_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA3")
-            .field("key3_data3", &format_args!("{}", self.key3_data3().bits()))
+            .field("key3_data3", &self.key3_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA3_SPEC {
diff --git a/esp32c3/src/efuse/rd_key3_data4.rs b/esp32c3/src/efuse/rd_key3_data4.rs
index 7f6aa4b29a..7cc8bbe55a 100644
--- a/esp32c3/src/efuse/rd_key3_data4.rs
+++ b/esp32c3/src/efuse/rd_key3_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA4")
-            .field("key3_data4", &format_args!("{}", self.key3_data4().bits()))
+            .field("key3_data4", &self.key3_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA4_SPEC {
diff --git a/esp32c3/src/efuse/rd_key3_data5.rs b/esp32c3/src/efuse/rd_key3_data5.rs
index ba520c7d60..a5579ffdc5 100644
--- a/esp32c3/src/efuse/rd_key3_data5.rs
+++ b/esp32c3/src/efuse/rd_key3_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA5")
-            .field("key3_data5", &format_args!("{}", self.key3_data5().bits()))
+            .field("key3_data5", &self.key3_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA5_SPEC {
diff --git a/esp32c3/src/efuse/rd_key3_data6.rs b/esp32c3/src/efuse/rd_key3_data6.rs
index b5fbe2051a..57afdeaf52 100644
--- a/esp32c3/src/efuse/rd_key3_data6.rs
+++ b/esp32c3/src/efuse/rd_key3_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA6")
-            .field("key3_data6", &format_args!("{}", self.key3_data6().bits()))
+            .field("key3_data6", &self.key3_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA6_SPEC {
diff --git a/esp32c3/src/efuse/rd_key3_data7.rs b/esp32c3/src/efuse/rd_key3_data7.rs
index 4bf010d286..7224fccfd6 100644
--- a/esp32c3/src/efuse/rd_key3_data7.rs
+++ b/esp32c3/src/efuse/rd_key3_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA7")
-            .field("key3_data7", &format_args!("{}", self.key3_data7().bits()))
+            .field("key3_data7", &self.key3_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA7_SPEC {
diff --git a/esp32c3/src/efuse/rd_key4_data0.rs b/esp32c3/src/efuse/rd_key4_data0.rs
index 224e960459..e82346659e 100644
--- a/esp32c3/src/efuse/rd_key4_data0.rs
+++ b/esp32c3/src/efuse/rd_key4_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA0")
-            .field("key4_data0", &format_args!("{}", self.key4_data0().bits()))
+            .field("key4_data0", &self.key4_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA0_SPEC {
diff --git a/esp32c3/src/efuse/rd_key4_data1.rs b/esp32c3/src/efuse/rd_key4_data1.rs
index 6ff0dfd449..34e5bcdf93 100644
--- a/esp32c3/src/efuse/rd_key4_data1.rs
+++ b/esp32c3/src/efuse/rd_key4_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA1")
-            .field("key4_data1", &format_args!("{}", self.key4_data1().bits()))
+            .field("key4_data1", &self.key4_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA1_SPEC {
diff --git a/esp32c3/src/efuse/rd_key4_data2.rs b/esp32c3/src/efuse/rd_key4_data2.rs
index f997607afe..445df040aa 100644
--- a/esp32c3/src/efuse/rd_key4_data2.rs
+++ b/esp32c3/src/efuse/rd_key4_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA2")
-            .field("key4_data2", &format_args!("{}", self.key4_data2().bits()))
+            .field("key4_data2", &self.key4_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA2_SPEC {
diff --git a/esp32c3/src/efuse/rd_key4_data3.rs b/esp32c3/src/efuse/rd_key4_data3.rs
index a834d67a07..4c4e20f86e 100644
--- a/esp32c3/src/efuse/rd_key4_data3.rs
+++ b/esp32c3/src/efuse/rd_key4_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA3")
-            .field("key4_data3", &format_args!("{}", self.key4_data3().bits()))
+            .field("key4_data3", &self.key4_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA3_SPEC {
diff --git a/esp32c3/src/efuse/rd_key4_data4.rs b/esp32c3/src/efuse/rd_key4_data4.rs
index d3955483ff..25683fd8ac 100644
--- a/esp32c3/src/efuse/rd_key4_data4.rs
+++ b/esp32c3/src/efuse/rd_key4_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA4")
-            .field("key4_data4", &format_args!("{}", self.key4_data4().bits()))
+            .field("key4_data4", &self.key4_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA4_SPEC {
diff --git a/esp32c3/src/efuse/rd_key4_data5.rs b/esp32c3/src/efuse/rd_key4_data5.rs
index 6a04334533..91cdeaf66b 100644
--- a/esp32c3/src/efuse/rd_key4_data5.rs
+++ b/esp32c3/src/efuse/rd_key4_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA5")
-            .field("key4_data5", &format_args!("{}", self.key4_data5().bits()))
+            .field("key4_data5", &self.key4_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA5_SPEC {
diff --git a/esp32c3/src/efuse/rd_key4_data6.rs b/esp32c3/src/efuse/rd_key4_data6.rs
index a074f789f0..a2a37a60a0 100644
--- a/esp32c3/src/efuse/rd_key4_data6.rs
+++ b/esp32c3/src/efuse/rd_key4_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA6")
-            .field("key4_data6", &format_args!("{}", self.key4_data6().bits()))
+            .field("key4_data6", &self.key4_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA6_SPEC {
diff --git a/esp32c3/src/efuse/rd_key4_data7.rs b/esp32c3/src/efuse/rd_key4_data7.rs
index da0d7a8a25..92015173a2 100644
--- a/esp32c3/src/efuse/rd_key4_data7.rs
+++ b/esp32c3/src/efuse/rd_key4_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA7")
-            .field("key4_data7", &format_args!("{}", self.key4_data7().bits()))
+            .field("key4_data7", &self.key4_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA7_SPEC {
diff --git a/esp32c3/src/efuse/rd_key5_data0.rs b/esp32c3/src/efuse/rd_key5_data0.rs
index 77933e6ce1..ce5f01baec 100644
--- a/esp32c3/src/efuse/rd_key5_data0.rs
+++ b/esp32c3/src/efuse/rd_key5_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA0")
-            .field("key5_data0", &format_args!("{}", self.key5_data0().bits()))
+            .field("key5_data0", &self.key5_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA0_SPEC {
diff --git a/esp32c3/src/efuse/rd_key5_data1.rs b/esp32c3/src/efuse/rd_key5_data1.rs
index 541bbb93af..29fbb2fa9b 100644
--- a/esp32c3/src/efuse/rd_key5_data1.rs
+++ b/esp32c3/src/efuse/rd_key5_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA1")
-            .field("key5_data1", &format_args!("{}", self.key5_data1().bits()))
+            .field("key5_data1", &self.key5_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA1_SPEC {
diff --git a/esp32c3/src/efuse/rd_key5_data2.rs b/esp32c3/src/efuse/rd_key5_data2.rs
index 99bf133501..4c07c8914e 100644
--- a/esp32c3/src/efuse/rd_key5_data2.rs
+++ b/esp32c3/src/efuse/rd_key5_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA2")
-            .field("key5_data2", &format_args!("{}", self.key5_data2().bits()))
+            .field("key5_data2", &self.key5_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA2_SPEC {
diff --git a/esp32c3/src/efuse/rd_key5_data3.rs b/esp32c3/src/efuse/rd_key5_data3.rs
index 363fc5aff8..3964d455f7 100644
--- a/esp32c3/src/efuse/rd_key5_data3.rs
+++ b/esp32c3/src/efuse/rd_key5_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA3")
-            .field("key5_data3", &format_args!("{}", self.key5_data3().bits()))
+            .field("key5_data3", &self.key5_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA3_SPEC {
diff --git a/esp32c3/src/efuse/rd_key5_data4.rs b/esp32c3/src/efuse/rd_key5_data4.rs
index 37367759f0..05999f9ce2 100644
--- a/esp32c3/src/efuse/rd_key5_data4.rs
+++ b/esp32c3/src/efuse/rd_key5_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA4")
-            .field("key5_data4", &format_args!("{}", self.key5_data4().bits()))
+            .field("key5_data4", &self.key5_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA4_SPEC {
diff --git a/esp32c3/src/efuse/rd_key5_data5.rs b/esp32c3/src/efuse/rd_key5_data5.rs
index d26e0a4811..fbbb97ea40 100644
--- a/esp32c3/src/efuse/rd_key5_data5.rs
+++ b/esp32c3/src/efuse/rd_key5_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA5")
-            .field("key5_data5", &format_args!("{}", self.key5_data5().bits()))
+            .field("key5_data5", &self.key5_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA5_SPEC {
diff --git a/esp32c3/src/efuse/rd_key5_data6.rs b/esp32c3/src/efuse/rd_key5_data6.rs
index 70ee60bd3f..c4561ed596 100644
--- a/esp32c3/src/efuse/rd_key5_data6.rs
+++ b/esp32c3/src/efuse/rd_key5_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA6")
-            .field("key5_data6", &format_args!("{}", self.key5_data6().bits()))
+            .field("key5_data6", &self.key5_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA6_SPEC {
diff --git a/esp32c3/src/efuse/rd_key5_data7.rs b/esp32c3/src/efuse/rd_key5_data7.rs
index f6c536431d..8d595e1adb 100644
--- a/esp32c3/src/efuse/rd_key5_data7.rs
+++ b/esp32c3/src/efuse/rd_key5_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA7")
-            .field("key5_data7", &format_args!("{}", self.key5_data7().bits()))
+            .field("key5_data7", &self.key5_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA7_SPEC {
diff --git a/esp32c3/src/efuse/rd_mac_spi_sys_0.rs b/esp32c3/src/efuse/rd_mac_spi_sys_0.rs
index 829e8e72f7..6511a28a09 100644
--- a/esp32c3/src/efuse/rd_mac_spi_sys_0.rs
+++ b/esp32c3/src/efuse/rd_mac_spi_sys_0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_0")
-            .field("mac_0", &format_args!("{}", self.mac_0().bits()))
+            .field("mac_0", &self.mac_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_0_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_0_SPEC {
diff --git a/esp32c3/src/efuse/rd_mac_spi_sys_1.rs b/esp32c3/src/efuse/rd_mac_spi_sys_1.rs
index 9256f8c032..4aec88e0e2 100644
--- a/esp32c3/src/efuse/rd_mac_spi_sys_1.rs
+++ b/esp32c3/src/efuse/rd_mac_spi_sys_1.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_1")
-            .field("mac_1", &format_args!("{}", self.mac_1().bits()))
-            .field(
-                "spi_pad_conf_0",
-                &format_args!("{}", self.spi_pad_conf_0().bits()),
-            )
+            .field("mac_1", &self.mac_1())
+            .field("spi_pad_conf_0", &self.spi_pad_conf_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_1_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_1_SPEC {
diff --git a/esp32c3/src/efuse/rd_mac_spi_sys_2.rs b/esp32c3/src/efuse/rd_mac_spi_sys_2.rs
index 7d62025d45..e5df412b3f 100644
--- a/esp32c3/src/efuse/rd_mac_spi_sys_2.rs
+++ b/esp32c3/src/efuse/rd_mac_spi_sys_2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_2")
-            .field(
-                "spi_pad_conf_1",
-                &format_args!("{}", self.spi_pad_conf_1().bits()),
-            )
+            .field("spi_pad_conf_1", &self.spi_pad_conf_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_2_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_2_SPEC {
diff --git a/esp32c3/src/efuse/rd_mac_spi_sys_3.rs b/esp32c3/src/efuse/rd_mac_spi_sys_3.rs
index 89db0e4b65..81936d0f06 100644
--- a/esp32c3/src/efuse/rd_mac_spi_sys_3.rs
+++ b/esp32c3/src/efuse/rd_mac_spi_sys_3.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_3")
-            .field(
-                "spi_pad_conf_2",
-                &format_args!("{}", self.spi_pad_conf_2().bits()),
-            )
-            .field(
-                "sys_data_part0_0",
-                &format_args!("{}", self.sys_data_part0_0().bits()),
-            )
+            .field("spi_pad_conf_2", &self.spi_pad_conf_2())
+            .field("sys_data_part0_0", &self.sys_data_part0_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_3_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_3_SPEC {
diff --git a/esp32c3/src/efuse/rd_mac_spi_sys_4.rs b/esp32c3/src/efuse/rd_mac_spi_sys_4.rs
index e0c07a6c42..27b7fa9845 100644
--- a/esp32c3/src/efuse/rd_mac_spi_sys_4.rs
+++ b/esp32c3/src/efuse/rd_mac_spi_sys_4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_4")
-            .field(
-                "sys_data_part0_1",
-                &format_args!("{}", self.sys_data_part0_1().bits()),
-            )
+            .field("sys_data_part0_1", &self.sys_data_part0_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register 4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_4_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_4_SPEC {
diff --git a/esp32c3/src/efuse/rd_mac_spi_sys_5.rs b/esp32c3/src/efuse/rd_mac_spi_sys_5.rs
index ffcbc45b90..d1cc8adab6 100644
--- a/esp32c3/src/efuse/rd_mac_spi_sys_5.rs
+++ b/esp32c3/src/efuse/rd_mac_spi_sys_5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_5")
-            .field(
-                "sys_data_part0_2",
-                &format_args!("{}", self.sys_data_part0_2().bits()),
-            )
+            .field("sys_data_part0_2", &self.sys_data_part0_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register 5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_5_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_5_SPEC {
diff --git a/esp32c3/src/efuse/rd_repeat_data0.rs b/esp32c3/src/efuse/rd_repeat_data0.rs
index e60d97b617..22242eaf8d 100644
--- a/esp32c3/src/efuse/rd_repeat_data0.rs
+++ b/esp32c3/src/efuse/rd_repeat_data0.rs
@@ -146,80 +146,32 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA0")
-            .field("rd_dis", &format_args!("{}", self.rd_dis().bits()))
-            .field(
-                "dis_rtc_ram_boot",
-                &format_args!("{}", self.dis_rtc_ram_boot().bit()),
-            )
-            .field("dis_icache", &format_args!("{}", self.dis_icache().bit()))
-            .field(
-                "dis_usb_jtag",
-                &format_args!("{}", self.dis_usb_jtag().bit()),
-            )
-            .field(
-                "dis_download_icache",
-                &format_args!("{}", self.dis_download_icache().bit()),
-            )
-            .field(
-                "dis_usb_device",
-                &format_args!("{}", self.dis_usb_device().bit()),
-            )
-            .field(
-                "dis_force_download",
-                &format_args!("{}", self.dis_force_download().bit()),
-            )
-            .field(
-                "rpt4_reserved6",
-                &format_args!("{}", self.rpt4_reserved6().bit()),
-            )
-            .field("dis_can", &format_args!("{}", self.dis_can().bit()))
-            .field(
-                "jtag_sel_enable",
-                &format_args!("{}", self.jtag_sel_enable().bit()),
-            )
-            .field(
-                "soft_dis_jtag",
-                &format_args!("{}", self.soft_dis_jtag().bits()),
-            )
-            .field(
-                "dis_pad_jtag",
-                &format_args!("{}", self.dis_pad_jtag().bit()),
-            )
+            .field("rd_dis", &self.rd_dis())
+            .field("dis_rtc_ram_boot", &self.dis_rtc_ram_boot())
+            .field("dis_icache", &self.dis_icache())
+            .field("dis_usb_jtag", &self.dis_usb_jtag())
+            .field("dis_download_icache", &self.dis_download_icache())
+            .field("dis_usb_device", &self.dis_usb_device())
+            .field("dis_force_download", &self.dis_force_download())
+            .field("rpt4_reserved6", &self.rpt4_reserved6())
+            .field("dis_can", &self.dis_can())
+            .field("jtag_sel_enable", &self.jtag_sel_enable())
+            .field("soft_dis_jtag", &self.soft_dis_jtag())
+            .field("dis_pad_jtag", &self.dis_pad_jtag())
             .field(
                 "dis_download_manual_encrypt",
-                &format_args!("{}", self.dis_download_manual_encrypt().bit()),
-            )
-            .field("usb_drefh", &format_args!("{}", self.usb_drefh().bits()))
-            .field("usb_drefl", &format_args!("{}", self.usb_drefl().bits()))
-            .field(
-                "usb_exchg_pins",
-                &format_args!("{}", self.usb_exchg_pins().bit()),
-            )
-            .field(
-                "vdd_spi_as_gpio",
-                &format_args!("{}", self.vdd_spi_as_gpio().bit()),
-            )
-            .field(
-                "btlc_gpio_enable",
-                &format_args!("{}", self.btlc_gpio_enable().bits()),
-            )
-            .field(
-                "powerglitch_en",
-                &format_args!("{}", self.powerglitch_en().bit()),
-            )
-            .field(
-                "power_glitch_dsense",
-                &format_args!("{}", self.power_glitch_dsense().bits()),
+                &self.dis_download_manual_encrypt(),
             )
+            .field("usb_drefh", &self.usb_drefh())
+            .field("usb_drefl", &self.usb_drefl())
+            .field("usb_exchg_pins", &self.usb_exchg_pins())
+            .field("vdd_spi_as_gpio", &self.vdd_spi_as_gpio())
+            .field("btlc_gpio_enable", &self.btlc_gpio_enable())
+            .field("powerglitch_en", &self.powerglitch_en())
+            .field("power_glitch_dsense", &self.power_glitch_dsense())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA0_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA0_SPEC {
diff --git a/esp32c3/src/efuse/rd_repeat_data1.rs b/esp32c3/src/efuse/rd_repeat_data1.rs
index 048accaacc..a5bcfae469 100644
--- a/esp32c3/src/efuse/rd_repeat_data1.rs
+++ b/esp32c3/src/efuse/rd_repeat_data1.rs
@@ -62,47 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA1")
-            .field(
-                "rpt4_reserved2",
-                &format_args!("{}", self.rpt4_reserved2().bits()),
-            )
-            .field(
-                "wdt_delay_sel",
-                &format_args!("{}", self.wdt_delay_sel().bits()),
-            )
-            .field(
-                "spi_boot_crypt_cnt",
-                &format_args!("{}", self.spi_boot_crypt_cnt().bits()),
-            )
-            .field(
-                "secure_boot_key_revoke0",
-                &format_args!("{}", self.secure_boot_key_revoke0().bit()),
-            )
-            .field(
-                "secure_boot_key_revoke1",
-                &format_args!("{}", self.secure_boot_key_revoke1().bit()),
-            )
-            .field(
-                "secure_boot_key_revoke2",
-                &format_args!("{}", self.secure_boot_key_revoke2().bit()),
-            )
-            .field(
-                "key_purpose_0",
-                &format_args!("{}", self.key_purpose_0().bits()),
-            )
-            .field(
-                "key_purpose_1",
-                &format_args!("{}", self.key_purpose_1().bits()),
-            )
+            .field("rpt4_reserved2", &self.rpt4_reserved2())
+            .field("wdt_delay_sel", &self.wdt_delay_sel())
+            .field("spi_boot_crypt_cnt", &self.spi_boot_crypt_cnt())
+            .field("secure_boot_key_revoke0", &self.secure_boot_key_revoke0())
+            .field("secure_boot_key_revoke1", &self.secure_boot_key_revoke1())
+            .field("secure_boot_key_revoke2", &self.secure_boot_key_revoke2())
+            .field("key_purpose_0", &self.key_purpose_0())
+            .field("key_purpose_1", &self.key_purpose_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA1_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA1_SPEC {
diff --git a/esp32c3/src/efuse/rd_repeat_data2.rs b/esp32c3/src/efuse/rd_repeat_data2.rs
index ed30f98ed2..41a64d745a 100644
--- a/esp32c3/src/efuse/rd_repeat_data2.rs
+++ b/esp32c3/src/efuse/rd_repeat_data2.rs
@@ -69,48 +69,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA2")
-            .field(
-                "key_purpose_2",
-                &format_args!("{}", self.key_purpose_2().bits()),
-            )
-            .field(
-                "key_purpose_3",
-                &format_args!("{}", self.key_purpose_3().bits()),
-            )
-            .field(
-                "key_purpose_4",
-                &format_args!("{}", self.key_purpose_4().bits()),
-            )
-            .field(
-                "key_purpose_5",
-                &format_args!("{}", self.key_purpose_5().bits()),
-            )
-            .field(
-                "rpt4_reserved3",
-                &format_args!("{}", self.rpt4_reserved3().bits()),
-            )
-            .field(
-                "secure_boot_en",
-                &format_args!("{}", self.secure_boot_en().bit()),
-            )
+            .field("key_purpose_2", &self.key_purpose_2())
+            .field("key_purpose_3", &self.key_purpose_3())
+            .field("key_purpose_4", &self.key_purpose_4())
+            .field("key_purpose_5", &self.key_purpose_5())
+            .field("rpt4_reserved3", &self.rpt4_reserved3())
+            .field("secure_boot_en", &self.secure_boot_en())
             .field(
                 "secure_boot_aggressive_revoke",
-                &format_args!("{}", self.secure_boot_aggressive_revoke().bit()),
-            )
-            .field(
-                "rpt4_reserved0",
-                &format_args!("{}", self.rpt4_reserved0().bits()),
+                &self.secure_boot_aggressive_revoke(),
             )
-            .field("flash_tpuw", &format_args!("{}", self.flash_tpuw().bits()))
+            .field("rpt4_reserved0", &self.rpt4_reserved0())
+            .field("flash_tpuw", &self.flash_tpuw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA2_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA2_SPEC {
diff --git a/esp32c3/src/efuse/rd_repeat_data3.rs b/esp32c3/src/efuse/rd_repeat_data3.rs
index 7bb583d1b0..38e3cef306 100644
--- a/esp32c3/src/efuse/rd_repeat_data3.rs
+++ b/esp32c3/src/efuse/rd_repeat_data3.rs
@@ -104,68 +104,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA3")
-            .field(
-                "dis_download_mode",
-                &format_args!("{}", self.dis_download_mode().bit()),
-            )
-            .field(
-                "dis_legacy_spi_boot",
-                &format_args!("{}", self.dis_legacy_spi_boot().bit()),
-            )
-            .field(
-                "uart_print_channel",
-                &format_args!("{}", self.uart_print_channel().bit()),
-            )
-            .field(
-                "flash_ecc_mode",
-                &format_args!("{}", self.flash_ecc_mode().bit()),
-            )
-            .field(
-                "dis_usb_download_mode",
-                &format_args!("{}", self.dis_usb_download_mode().bit()),
-            )
-            .field(
-                "enable_security_download",
-                &format_args!("{}", self.enable_security_download().bit()),
-            )
-            .field(
-                "uart_print_control",
-                &format_args!("{}", self.uart_print_control().bits()),
-            )
-            .field(
-                "pin_power_selection",
-                &format_args!("{}", self.pin_power_selection().bit()),
-            )
-            .field("flash_type", &format_args!("{}", self.flash_type().bit()))
-            .field(
-                "flash_page_size",
-                &format_args!("{}", self.flash_page_size().bits()),
-            )
-            .field(
-                "flash_ecc_en",
-                &format_args!("{}", self.flash_ecc_en().bit()),
-            )
-            .field(
-                "force_send_resume",
-                &format_args!("{}", self.force_send_resume().bit()),
-            )
-            .field(
-                "secure_version",
-                &format_args!("{}", self.secure_version().bits()),
-            )
-            .field(
-                "rpt4_reserved1",
-                &format_args!("{}", self.rpt4_reserved1().bits()),
-            )
+            .field("dis_download_mode", &self.dis_download_mode())
+            .field("dis_legacy_spi_boot", &self.dis_legacy_spi_boot())
+            .field("uart_print_channel", &self.uart_print_channel())
+            .field("flash_ecc_mode", &self.flash_ecc_mode())
+            .field("dis_usb_download_mode", &self.dis_usb_download_mode())
+            .field("enable_security_download", &self.enable_security_download())
+            .field("uart_print_control", &self.uart_print_control())
+            .field("pin_power_selection", &self.pin_power_selection())
+            .field("flash_type", &self.flash_type())
+            .field("flash_page_size", &self.flash_page_size())
+            .field("flash_ecc_en", &self.flash_ecc_en())
+            .field("force_send_resume", &self.force_send_resume())
+            .field("secure_version", &self.secure_version())
+            .field("rpt4_reserved1", &self.rpt4_reserved1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA3_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA3_SPEC {
diff --git a/esp32c3/src/efuse/rd_repeat_data4.rs b/esp32c3/src/efuse/rd_repeat_data4.rs
index ba01379741..6e550005bd 100644
--- a/esp32c3/src/efuse/rd_repeat_data4.rs
+++ b/esp32c3/src/efuse/rd_repeat_data4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA4")
-            .field(
-                "rpt4_reserved4",
-                &format_args!("{}", self.rpt4_reserved4().bits()),
-            )
+            .field("rpt4_reserved4", &self.rpt4_reserved4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA4_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA4_SPEC {
diff --git a/esp32c3/src/efuse/rd_repeat_err0.rs b/esp32c3/src/efuse/rd_repeat_err0.rs
index 990ab7e376..29d4f45c3f 100644
--- a/esp32c3/src/efuse/rd_repeat_err0.rs
+++ b/esp32c3/src/efuse/rd_repeat_err0.rs
@@ -146,89 +146,32 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR0")
-            .field("rd_dis_err", &format_args!("{}", self.rd_dis_err().bits()))
-            .field(
-                "dis_rtc_ram_boot_err",
-                &format_args!("{}", self.dis_rtc_ram_boot_err().bit()),
-            )
-            .field(
-                "dis_icache_err",
-                &format_args!("{}", self.dis_icache_err().bit()),
-            )
-            .field(
-                "dis_usb_jtag_err",
-                &format_args!("{}", self.dis_usb_jtag_err().bit()),
-            )
-            .field(
-                "dis_download_icache_err",
-                &format_args!("{}", self.dis_download_icache_err().bit()),
-            )
-            .field(
-                "dis_usb_device_err",
-                &format_args!("{}", self.dis_usb_device_err().bit()),
-            )
-            .field(
-                "dis_force_download_err",
-                &format_args!("{}", self.dis_force_download_err().bit()),
-            )
-            .field(
-                "rpt4_reserved6_err",
-                &format_args!("{}", self.rpt4_reserved6_err().bit()),
-            )
-            .field("dis_can_err", &format_args!("{}", self.dis_can_err().bit()))
-            .field(
-                "jtag_sel_enable_err",
-                &format_args!("{}", self.jtag_sel_enable_err().bit()),
-            )
-            .field(
-                "soft_dis_jtag_err",
-                &format_args!("{}", self.soft_dis_jtag_err().bits()),
-            )
-            .field(
-                "dis_pad_jtag_err",
-                &format_args!("{}", self.dis_pad_jtag_err().bit()),
-            )
+            .field("rd_dis_err", &self.rd_dis_err())
+            .field("dis_rtc_ram_boot_err", &self.dis_rtc_ram_boot_err())
+            .field("dis_icache_err", &self.dis_icache_err())
+            .field("dis_usb_jtag_err", &self.dis_usb_jtag_err())
+            .field("dis_download_icache_err", &self.dis_download_icache_err())
+            .field("dis_usb_device_err", &self.dis_usb_device_err())
+            .field("dis_force_download_err", &self.dis_force_download_err())
+            .field("rpt4_reserved6_err", &self.rpt4_reserved6_err())
+            .field("dis_can_err", &self.dis_can_err())
+            .field("jtag_sel_enable_err", &self.jtag_sel_enable_err())
+            .field("soft_dis_jtag_err", &self.soft_dis_jtag_err())
+            .field("dis_pad_jtag_err", &self.dis_pad_jtag_err())
             .field(
                 "dis_download_manual_encrypt_err",
-                &format_args!("{}", self.dis_download_manual_encrypt_err().bit()),
-            )
-            .field(
-                "usb_drefh_err",
-                &format_args!("{}", self.usb_drefh_err().bits()),
-            )
-            .field(
-                "usb_drefl_err",
-                &format_args!("{}", self.usb_drefl_err().bits()),
-            )
-            .field(
-                "usb_exchg_pins_err",
-                &format_args!("{}", self.usb_exchg_pins_err().bit()),
-            )
-            .field(
-                "vdd_spi_as_gpio_err",
-                &format_args!("{}", self.vdd_spi_as_gpio_err().bit()),
-            )
-            .field(
-                "btlc_gpio_enable_err",
-                &format_args!("{}", self.btlc_gpio_enable_err().bits()),
-            )
-            .field(
-                "powerglitch_en_err",
-                &format_args!("{}", self.powerglitch_en_err().bit()),
-            )
-            .field(
-                "power_glitch_dsense_err",
-                &format_args!("{}", self.power_glitch_dsense_err().bits()),
-            )
+                &self.dis_download_manual_encrypt_err(),
+            )
+            .field("usb_drefh_err", &self.usb_drefh_err())
+            .field("usb_drefl_err", &self.usb_drefl_err())
+            .field("usb_exchg_pins_err", &self.usb_exchg_pins_err())
+            .field("vdd_spi_as_gpio_err", &self.vdd_spi_as_gpio_err())
+            .field("btlc_gpio_enable_err", &self.btlc_gpio_enable_err())
+            .field("powerglitch_en_err", &self.powerglitch_en_err())
+            .field("power_glitch_dsense_err", &self.power_glitch_dsense_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 0 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR0_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR0_SPEC {
diff --git a/esp32c3/src/efuse/rd_repeat_err1.rs b/esp32c3/src/efuse/rd_repeat_err1.rs
index ddbc565265..c424ecb5ae 100644
--- a/esp32c3/src/efuse/rd_repeat_err1.rs
+++ b/esp32c3/src/efuse/rd_repeat_err1.rs
@@ -62,47 +62,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR1")
-            .field(
-                "rpt4_reserved2_err",
-                &format_args!("{}", self.rpt4_reserved2_err().bits()),
-            )
-            .field(
-                "wdt_delay_sel_err",
-                &format_args!("{}", self.wdt_delay_sel_err().bits()),
-            )
-            .field(
-                "spi_boot_crypt_cnt_err",
-                &format_args!("{}", self.spi_boot_crypt_cnt_err().bits()),
-            )
+            .field("rpt4_reserved2_err", &self.rpt4_reserved2_err())
+            .field("wdt_delay_sel_err", &self.wdt_delay_sel_err())
+            .field("spi_boot_crypt_cnt_err", &self.spi_boot_crypt_cnt_err())
             .field(
                 "secure_boot_key_revoke0_err",
-                &format_args!("{}", self.secure_boot_key_revoke0_err().bit()),
+                &self.secure_boot_key_revoke0_err(),
             )
             .field(
                 "secure_boot_key_revoke1_err",
-                &format_args!("{}", self.secure_boot_key_revoke1_err().bit()),
+                &self.secure_boot_key_revoke1_err(),
             )
             .field(
                 "secure_boot_key_revoke2_err",
-                &format_args!("{}", self.secure_boot_key_revoke2_err().bit()),
-            )
-            .field(
-                "key_purpose_0_err",
-                &format_args!("{}", self.key_purpose_0_err().bits()),
-            )
-            .field(
-                "key_purpose_1_err",
-                &format_args!("{}", self.key_purpose_1_err().bits()),
+                &self.secure_boot_key_revoke2_err(),
             )
+            .field("key_purpose_0_err", &self.key_purpose_0_err())
+            .field("key_purpose_1_err", &self.key_purpose_1_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 1 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR1_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR1_SPEC {
diff --git a/esp32c3/src/efuse/rd_repeat_err2.rs b/esp32c3/src/efuse/rd_repeat_err2.rs
index 57e6108cf1..cee17d038a 100644
--- a/esp32c3/src/efuse/rd_repeat_err2.rs
+++ b/esp32c3/src/efuse/rd_repeat_err2.rs
@@ -69,51 +69,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR2")
-            .field(
-                "key_purpose_2_err",
-                &format_args!("{}", self.key_purpose_2_err().bits()),
-            )
-            .field(
-                "key_purpose_3_err",
-                &format_args!("{}", self.key_purpose_3_err().bits()),
-            )
-            .field(
-                "key_purpose_4_err",
-                &format_args!("{}", self.key_purpose_4_err().bits()),
-            )
-            .field(
-                "key_purpose_5_err",
-                &format_args!("{}", self.key_purpose_5_err().bits()),
-            )
-            .field(
-                "rpt4_reserved3_err",
-                &format_args!("{}", self.rpt4_reserved3_err().bits()),
-            )
-            .field(
-                "secure_boot_en_err",
-                &format_args!("{}", self.secure_boot_en_err().bit()),
-            )
+            .field("key_purpose_2_err", &self.key_purpose_2_err())
+            .field("key_purpose_3_err", &self.key_purpose_3_err())
+            .field("key_purpose_4_err", &self.key_purpose_4_err())
+            .field("key_purpose_5_err", &self.key_purpose_5_err())
+            .field("rpt4_reserved3_err", &self.rpt4_reserved3_err())
+            .field("secure_boot_en_err", &self.secure_boot_en_err())
             .field(
                 "secure_boot_aggressive_revoke_err",
-                &format_args!("{}", self.secure_boot_aggressive_revoke_err().bit()),
-            )
-            .field(
-                "rpt4_reserved0_err",
-                &format_args!("{}", self.rpt4_reserved0_err().bits()),
-            )
-            .field(
-                "flash_tpuw_err",
-                &format_args!("{}", self.flash_tpuw_err().bits()),
+                &self.secure_boot_aggressive_revoke_err(),
             )
+            .field("rpt4_reserved0_err", &self.rpt4_reserved0_err())
+            .field("flash_tpuw_err", &self.flash_tpuw_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 2 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR2_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR2_SPEC {
diff --git a/esp32c3/src/efuse/rd_repeat_err3.rs b/esp32c3/src/efuse/rd_repeat_err3.rs
index a3216bd770..a6c7217c17 100644
--- a/esp32c3/src/efuse/rd_repeat_err3.rs
+++ b/esp32c3/src/efuse/rd_repeat_err3.rs
@@ -104,71 +104,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR3")
-            .field(
-                "dis_download_mode_err",
-                &format_args!("{}", self.dis_download_mode_err().bit()),
-            )
-            .field(
-                "dis_legacy_spi_boot_err",
-                &format_args!("{}", self.dis_legacy_spi_boot_err().bit()),
-            )
-            .field(
-                "uart_print_channel_err",
-                &format_args!("{}", self.uart_print_channel_err().bit()),
-            )
-            .field(
-                "flash_ecc_mode_err",
-                &format_args!("{}", self.flash_ecc_mode_err().bit()),
-            )
+            .field("dis_download_mode_err", &self.dis_download_mode_err())
+            .field("dis_legacy_spi_boot_err", &self.dis_legacy_spi_boot_err())
+            .field("uart_print_channel_err", &self.uart_print_channel_err())
+            .field("flash_ecc_mode_err", &self.flash_ecc_mode_err())
             .field(
                 "dis_usb_download_mode_err",
-                &format_args!("{}", self.dis_usb_download_mode_err().bit()),
+                &self.dis_usb_download_mode_err(),
             )
             .field(
                 "enable_security_download_err",
-                &format_args!("{}", self.enable_security_download_err().bit()),
-            )
-            .field(
-                "uart_print_control_err",
-                &format_args!("{}", self.uart_print_control_err().bits()),
-            )
-            .field(
-                "pin_power_selection_err",
-                &format_args!("{}", self.pin_power_selection_err().bit()),
-            )
-            .field(
-                "flash_type_err",
-                &format_args!("{}", self.flash_type_err().bit()),
-            )
-            .field(
-                "flash_page_size_err",
-                &format_args!("{}", self.flash_page_size_err().bits()),
-            )
-            .field(
-                "flash_ecc_en_err",
-                &format_args!("{}", self.flash_ecc_en_err().bit()),
-            )
-            .field(
-                "force_send_resume_err",
-                &format_args!("{}", self.force_send_resume_err().bit()),
-            )
-            .field(
-                "secure_version_err",
-                &format_args!("{}", self.secure_version_err().bits()),
-            )
-            .field(
-                "rpt4_reserved1_err",
-                &format_args!("{}", self.rpt4_reserved1_err().bits()),
+                &self.enable_security_download_err(),
             )
+            .field("uart_print_control_err", &self.uart_print_control_err())
+            .field("pin_power_selection_err", &self.pin_power_selection_err())
+            .field("flash_type_err", &self.flash_type_err())
+            .field("flash_page_size_err", &self.flash_page_size_err())
+            .field("flash_ecc_en_err", &self.flash_ecc_en_err())
+            .field("force_send_resume_err", &self.force_send_resume_err())
+            .field("secure_version_err", &self.secure_version_err())
+            .field("rpt4_reserved1_err", &self.rpt4_reserved1_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 3 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR3_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR3_SPEC {
diff --git a/esp32c3/src/efuse/rd_repeat_err4.rs b/esp32c3/src/efuse/rd_repeat_err4.rs
index d586399af8..9d02a1a1cf 100644
--- a/esp32c3/src/efuse/rd_repeat_err4.rs
+++ b/esp32c3/src/efuse/rd_repeat_err4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR4")
-            .field(
-                "rpt4_reserved4_err",
-                &format_args!("{}", self.rpt4_reserved4_err().bits()),
-            )
+            .field("rpt4_reserved4_err", &self.rpt4_reserved4_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 4 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR4_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR4_SPEC {
diff --git a/esp32c3/src/efuse/rd_rs_err0.rs b/esp32c3/src/efuse/rd_rs_err0.rs
index ea7bad6e93..ed5dc386c0 100644
--- a/esp32c3/src/efuse/rd_rs_err0.rs
+++ b/esp32c3/src/efuse/rd_rs_err0.rs
@@ -118,64 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_RS_ERR0")
-            .field(
-                "mac_spi_8m_err_num",
-                &format_args!("{}", self.mac_spi_8m_err_num().bits()),
-            )
-            .field(
-                "mac_spi_8m_fail",
-                &format_args!("{}", self.mac_spi_8m_fail().bit()),
-            )
-            .field(
-                "sys_part1_num",
-                &format_args!("{}", self.sys_part1_num().bits()),
-            )
-            .field(
-                "sys_part1_fail",
-                &format_args!("{}", self.sys_part1_fail().bit()),
-            )
-            .field(
-                "usr_data_err_num",
-                &format_args!("{}", self.usr_data_err_num().bits()),
-            )
-            .field(
-                "usr_data_fail",
-                &format_args!("{}", self.usr_data_fail().bit()),
-            )
-            .field(
-                "key0_err_num",
-                &format_args!("{}", self.key0_err_num().bits()),
-            )
-            .field("key0_fail", &format_args!("{}", self.key0_fail().bit()))
-            .field(
-                "key1_err_num",
-                &format_args!("{}", self.key1_err_num().bits()),
-            )
-            .field("key1_fail", &format_args!("{}", self.key1_fail().bit()))
-            .field(
-                "key2_err_num",
-                &format_args!("{}", self.key2_err_num().bits()),
-            )
-            .field("key2_fail", &format_args!("{}", self.key2_fail().bit()))
-            .field(
-                "key3_err_num",
-                &format_args!("{}", self.key3_err_num().bits()),
-            )
-            .field("key3_fail", &format_args!("{}", self.key3_fail().bit()))
-            .field(
-                "key4_err_num",
-                &format_args!("{}", self.key4_err_num().bits()),
-            )
-            .field("key4_fail", &format_args!("{}", self.key4_fail().bit()))
+            .field("mac_spi_8m_err_num", &self.mac_spi_8m_err_num())
+            .field("mac_spi_8m_fail", &self.mac_spi_8m_fail())
+            .field("sys_part1_num", &self.sys_part1_num())
+            .field("sys_part1_fail", &self.sys_part1_fail())
+            .field("usr_data_err_num", &self.usr_data_err_num())
+            .field("usr_data_fail", &self.usr_data_fail())
+            .field("key0_err_num", &self.key0_err_num())
+            .field("key0_fail", &self.key0_fail())
+            .field("key1_err_num", &self.key1_err_num())
+            .field("key1_fail", &self.key1_fail())
+            .field("key2_err_num", &self.key2_err_num())
+            .field("key2_fail", &self.key2_fail())
+            .field("key3_err_num", &self.key3_err_num())
+            .field("key3_fail", &self.key3_fail())
+            .field("key4_err_num", &self.key4_err_num())
+            .field("key4_fail", &self.key4_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RS_ERR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 0 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RS_ERR0_SPEC;
 impl crate::RegisterSpec for RD_RS_ERR0_SPEC {
diff --git a/esp32c3/src/efuse/rd_rs_err1.rs b/esp32c3/src/efuse/rd_rs_err1.rs
index 902a43ca7f..66b22ef556 100644
--- a/esp32c3/src/efuse/rd_rs_err1.rs
+++ b/esp32c3/src/efuse/rd_rs_err1.rs
@@ -34,28 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_RS_ERR1")
-            .field(
-                "key5_err_num",
-                &format_args!("{}", self.key5_err_num().bits()),
-            )
-            .field("key5_fail", &format_args!("{}", self.key5_fail().bit()))
-            .field(
-                "sys_part2_err_num",
-                &format_args!("{}", self.sys_part2_err_num().bits()),
-            )
-            .field(
-                "sys_part2_fail",
-                &format_args!("{}", self.sys_part2_fail().bit()),
-            )
+            .field("key5_err_num", &self.key5_err_num())
+            .field("key5_fail", &self.key5_fail())
+            .field("sys_part2_err_num", &self.sys_part2_err_num())
+            .field("sys_part2_fail", &self.sys_part2_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RS_ERR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 1 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RS_ERR1_SPEC;
 impl crate::RegisterSpec for RD_RS_ERR1_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part1_data0.rs b/esp32c3/src/efuse/rd_sys_part1_data0.rs
index fd380c93c9..d8f23ea6d5 100644
--- a/esp32c3/src/efuse/rd_sys_part1_data0.rs
+++ b/esp32c3/src/efuse/rd_sys_part1_data0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA0")
-            .field(
-                "sys_data_part1_0",
-                &format_args!("{}", self.sys_data_part1_0().bits()),
-            )
+            .field("sys_data_part1_0", &self.sys_data_part1_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA0_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA0_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part1_data1.rs b/esp32c3/src/efuse/rd_sys_part1_data1.rs
index 36cc24f084..d55067d5f0 100644
--- a/esp32c3/src/efuse/rd_sys_part1_data1.rs
+++ b/esp32c3/src/efuse/rd_sys_part1_data1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA1")
-            .field(
-                "sys_data_part1_1",
-                &format_args!("{}", self.sys_data_part1_1().bits()),
-            )
+            .field("sys_data_part1_1", &self.sys_data_part1_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA1_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA1_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part1_data2.rs b/esp32c3/src/efuse/rd_sys_part1_data2.rs
index 053a53e4ee..dcf911b5a3 100644
--- a/esp32c3/src/efuse/rd_sys_part1_data2.rs
+++ b/esp32c3/src/efuse/rd_sys_part1_data2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA2")
-            .field(
-                "sys_data_part1_2",
-                &format_args!("{}", self.sys_data_part1_2().bits()),
-            )
+            .field("sys_data_part1_2", &self.sys_data_part1_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA2_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA2_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part1_data3.rs b/esp32c3/src/efuse/rd_sys_part1_data3.rs
index d6179df3fb..eaa838b43b 100644
--- a/esp32c3/src/efuse/rd_sys_part1_data3.rs
+++ b/esp32c3/src/efuse/rd_sys_part1_data3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA3")
-            .field(
-                "sys_data_part1_3",
-                &format_args!("{}", self.sys_data_part1_3().bits()),
-            )
+            .field("sys_data_part1_3", &self.sys_data_part1_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA3_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA3_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part1_data4.rs b/esp32c3/src/efuse/rd_sys_part1_data4.rs
index 4a3f06dcd5..623a089550 100644
--- a/esp32c3/src/efuse/rd_sys_part1_data4.rs
+++ b/esp32c3/src/efuse/rd_sys_part1_data4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA4")
-            .field(
-                "sys_data_part1_4",
-                &format_args!("{}", self.sys_data_part1_4().bits()),
-            )
+            .field("sys_data_part1_4", &self.sys_data_part1_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA4_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA4_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part1_data5.rs b/esp32c3/src/efuse/rd_sys_part1_data5.rs
index f78c94865c..c5f8c57f12 100644
--- a/esp32c3/src/efuse/rd_sys_part1_data5.rs
+++ b/esp32c3/src/efuse/rd_sys_part1_data5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA5")
-            .field(
-                "sys_data_part1_5",
-                &format_args!("{}", self.sys_data_part1_5().bits()),
-            )
+            .field("sys_data_part1_5", &self.sys_data_part1_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA5_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA5_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part1_data6.rs b/esp32c3/src/efuse/rd_sys_part1_data6.rs
index 45addd4640..515cd46774 100644
--- a/esp32c3/src/efuse/rd_sys_part1_data6.rs
+++ b/esp32c3/src/efuse/rd_sys_part1_data6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA6")
-            .field(
-                "sys_data_part1_6",
-                &format_args!("{}", self.sys_data_part1_6().bits()),
-            )
+            .field("sys_data_part1_6", &self.sys_data_part1_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA6_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA6_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part1_data7.rs b/esp32c3/src/efuse/rd_sys_part1_data7.rs
index 444f64edf4..82ed838944 100644
--- a/esp32c3/src/efuse/rd_sys_part1_data7.rs
+++ b/esp32c3/src/efuse/rd_sys_part1_data7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA7")
-            .field(
-                "sys_data_part1_7",
-                &format_args!("{}", self.sys_data_part1_7().bits()),
-            )
+            .field("sys_data_part1_7", &self.sys_data_part1_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA7_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA7_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part2_data0.rs b/esp32c3/src/efuse/rd_sys_part2_data0.rs
index d2479c149f..3062fa64da 100644
--- a/esp32c3/src/efuse/rd_sys_part2_data0.rs
+++ b/esp32c3/src/efuse/rd_sys_part2_data0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA0")
-            .field(
-                "sys_data_part2_0",
-                &format_args!("{}", self.sys_data_part2_0().bits()),
-            )
+            .field("sys_data_part2_0", &self.sys_data_part2_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA0_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA0_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part2_data1.rs b/esp32c3/src/efuse/rd_sys_part2_data1.rs
index 7c058b757e..27afe242c7 100644
--- a/esp32c3/src/efuse/rd_sys_part2_data1.rs
+++ b/esp32c3/src/efuse/rd_sys_part2_data1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA1")
-            .field(
-                "sys_data_part2_1",
-                &format_args!("{}", self.sys_data_part2_1().bits()),
-            )
+            .field("sys_data_part2_1", &self.sys_data_part2_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA1_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA1_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part2_data2.rs b/esp32c3/src/efuse/rd_sys_part2_data2.rs
index 0ace9e8c48..7e396cd4a9 100644
--- a/esp32c3/src/efuse/rd_sys_part2_data2.rs
+++ b/esp32c3/src/efuse/rd_sys_part2_data2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA2")
-            .field(
-                "sys_data_part2_2",
-                &format_args!("{}", self.sys_data_part2_2().bits()),
-            )
+            .field("sys_data_part2_2", &self.sys_data_part2_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA2_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA2_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part2_data3.rs b/esp32c3/src/efuse/rd_sys_part2_data3.rs
index 840a4dcc26..27c19d4b56 100644
--- a/esp32c3/src/efuse/rd_sys_part2_data3.rs
+++ b/esp32c3/src/efuse/rd_sys_part2_data3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA3")
-            .field(
-                "sys_data_part2_3",
-                &format_args!("{}", self.sys_data_part2_3().bits()),
-            )
+            .field("sys_data_part2_3", &self.sys_data_part2_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA3_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA3_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part2_data4.rs b/esp32c3/src/efuse/rd_sys_part2_data4.rs
index 7b765221e6..f7c056a5ed 100644
--- a/esp32c3/src/efuse/rd_sys_part2_data4.rs
+++ b/esp32c3/src/efuse/rd_sys_part2_data4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA4")
-            .field(
-                "sys_data_part2_4",
-                &format_args!("{}", self.sys_data_part2_4().bits()),
-            )
+            .field("sys_data_part2_4", &self.sys_data_part2_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA4_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA4_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part2_data5.rs b/esp32c3/src/efuse/rd_sys_part2_data5.rs
index e64e6c88cb..49323b99f0 100644
--- a/esp32c3/src/efuse/rd_sys_part2_data5.rs
+++ b/esp32c3/src/efuse/rd_sys_part2_data5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA5")
-            .field(
-                "sys_data_part2_5",
-                &format_args!("{}", self.sys_data_part2_5().bits()),
-            )
+            .field("sys_data_part2_5", &self.sys_data_part2_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA5_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA5_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part2_data6.rs b/esp32c3/src/efuse/rd_sys_part2_data6.rs
index 152193ce2b..94bdb0430b 100644
--- a/esp32c3/src/efuse/rd_sys_part2_data6.rs
+++ b/esp32c3/src/efuse/rd_sys_part2_data6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA6")
-            .field(
-                "sys_data_part2_6",
-                &format_args!("{}", self.sys_data_part2_6().bits()),
-            )
+            .field("sys_data_part2_6", &self.sys_data_part2_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA6_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA6_SPEC {
diff --git a/esp32c3/src/efuse/rd_sys_part2_data7.rs b/esp32c3/src/efuse/rd_sys_part2_data7.rs
index 9dba6cb0e1..0d79007131 100644
--- a/esp32c3/src/efuse/rd_sys_part2_data7.rs
+++ b/esp32c3/src/efuse/rd_sys_part2_data7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA7")
-            .field(
-                "sys_data_part2_7",
-                &format_args!("{}", self.sys_data_part2_7().bits()),
-            )
+            .field("sys_data_part2_7", &self.sys_data_part2_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA7_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA7_SPEC {
diff --git a/esp32c3/src/efuse/rd_tim_conf.rs b/esp32c3/src/efuse/rd_tim_conf.rs
index 04a800fe3a..f862b2b2b2 100644
--- a/esp32c3/src/efuse/rd_tim_conf.rs
+++ b/esp32c3/src/efuse/rd_tim_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_TIM_CONF")
-            .field(
-                "read_init_num",
-                &format_args!("{}", self.read_init_num().bits()),
-            )
+            .field("read_init_num", &self.read_init_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_TIM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 24:31 - Configures the initial read time of eFuse."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/rd_usr_data0.rs b/esp32c3/src/efuse/rd_usr_data0.rs
index fce5121318..4f54f71ffd 100644
--- a/esp32c3/src/efuse/rd_usr_data0.rs
+++ b/esp32c3/src/efuse/rd_usr_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA0")
-            .field("usr_data0", &format_args!("{}", self.usr_data0().bits()))
+            .field("usr_data0", &self.usr_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA0_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA0_SPEC {
diff --git a/esp32c3/src/efuse/rd_usr_data1.rs b/esp32c3/src/efuse/rd_usr_data1.rs
index f85c53cdc2..d95f9d04d8 100644
--- a/esp32c3/src/efuse/rd_usr_data1.rs
+++ b/esp32c3/src/efuse/rd_usr_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA1")
-            .field("usr_data1", &format_args!("{}", self.usr_data1().bits()))
+            .field("usr_data1", &self.usr_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA1_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA1_SPEC {
diff --git a/esp32c3/src/efuse/rd_usr_data2.rs b/esp32c3/src/efuse/rd_usr_data2.rs
index 92364c1659..37f85f90d8 100644
--- a/esp32c3/src/efuse/rd_usr_data2.rs
+++ b/esp32c3/src/efuse/rd_usr_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA2")
-            .field("usr_data2", &format_args!("{}", self.usr_data2().bits()))
+            .field("usr_data2", &self.usr_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA2_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA2_SPEC {
diff --git a/esp32c3/src/efuse/rd_usr_data3.rs b/esp32c3/src/efuse/rd_usr_data3.rs
index 054770e514..fba0fe4cde 100644
--- a/esp32c3/src/efuse/rd_usr_data3.rs
+++ b/esp32c3/src/efuse/rd_usr_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA3")
-            .field("usr_data3", &format_args!("{}", self.usr_data3().bits()))
+            .field("usr_data3", &self.usr_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA3_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA3_SPEC {
diff --git a/esp32c3/src/efuse/rd_usr_data4.rs b/esp32c3/src/efuse/rd_usr_data4.rs
index 46c132fcdc..41942f3a5e 100644
--- a/esp32c3/src/efuse/rd_usr_data4.rs
+++ b/esp32c3/src/efuse/rd_usr_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA4")
-            .field("usr_data4", &format_args!("{}", self.usr_data4().bits()))
+            .field("usr_data4", &self.usr_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA4_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA4_SPEC {
diff --git a/esp32c3/src/efuse/rd_usr_data5.rs b/esp32c3/src/efuse/rd_usr_data5.rs
index f5f463e31d..f1e941203a 100644
--- a/esp32c3/src/efuse/rd_usr_data5.rs
+++ b/esp32c3/src/efuse/rd_usr_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA5")
-            .field("usr_data5", &format_args!("{}", self.usr_data5().bits()))
+            .field("usr_data5", &self.usr_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA5_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA5_SPEC {
diff --git a/esp32c3/src/efuse/rd_usr_data6.rs b/esp32c3/src/efuse/rd_usr_data6.rs
index 8dbf84538d..221b83a84e 100644
--- a/esp32c3/src/efuse/rd_usr_data6.rs
+++ b/esp32c3/src/efuse/rd_usr_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA6")
-            .field("usr_data6", &format_args!("{}", self.usr_data6().bits()))
+            .field("usr_data6", &self.usr_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA6_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA6_SPEC {
diff --git a/esp32c3/src/efuse/rd_usr_data7.rs b/esp32c3/src/efuse/rd_usr_data7.rs
index 3010768b19..3ae6bdeb03 100644
--- a/esp32c3/src/efuse/rd_usr_data7.rs
+++ b/esp32c3/src/efuse/rd_usr_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA7")
-            .field("usr_data7", &format_args!("{}", self.usr_data7().bits()))
+            .field("usr_data7", &self.usr_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA7_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA7_SPEC {
diff --git a/esp32c3/src/efuse/rd_wr_dis.rs b/esp32c3/src/efuse/rd_wr_dis.rs
index 606a047d13..badd8bfe7d 100644
--- a/esp32c3/src/efuse/rd_wr_dis.rs
+++ b/esp32c3/src/efuse/rd_wr_dis.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_WR_DIS")
-            .field("wr_dis", &format_args!("{}", self.wr_dis().bits()))
+            .field("wr_dis", &self.wr_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_WR_DIS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_wr_dis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_WR_DIS_SPEC;
 impl crate::RegisterSpec for RD_WR_DIS_SPEC {
diff --git a/esp32c3/src/efuse/status.rs b/esp32c3/src/efuse/status.rs
index 88ccd0f914..2402480c94 100644
--- a/esp32c3/src/efuse/status.rs
+++ b/esp32c3/src/efuse/status.rs
@@ -62,38 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field("otp_load_sw", &format_args!("{}", self.otp_load_sw().bit()))
-            .field(
-                "otp_vddq_c_sync2",
-                &format_args!("{}", self.otp_vddq_c_sync2().bit()),
-            )
-            .field(
-                "otp_strobe_sw",
-                &format_args!("{}", self.otp_strobe_sw().bit()),
-            )
-            .field("otp_csb_sw", &format_args!("{}", self.otp_csb_sw().bit()))
-            .field(
-                "otp_pgenb_sw",
-                &format_args!("{}", self.otp_pgenb_sw().bit()),
-            )
-            .field(
-                "otp_vddq_is_sw",
-                &format_args!("{}", self.otp_vddq_is_sw().bit()),
-            )
-            .field(
-                "repeat_err_cnt",
-                &format_args!("{}", self.repeat_err_cnt().bits()),
-            )
+            .field("state", &self.state())
+            .field("otp_load_sw", &self.otp_load_sw())
+            .field("otp_vddq_c_sync2", &self.otp_vddq_c_sync2())
+            .field("otp_strobe_sw", &self.otp_strobe_sw())
+            .field("otp_csb_sw", &self.otp_csb_sw())
+            .field("otp_pgenb_sw", &self.otp_pgenb_sw())
+            .field("otp_vddq_is_sw", &self.otp_vddq_is_sw())
+            .field("repeat_err_cnt", &self.repeat_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32c3/src/efuse/wr_tim_conf1.rs b/esp32c3/src/efuse/wr_tim_conf1.rs
index 6e70a3da1b..ebe3b08c1e 100644
--- a/esp32c3/src/efuse/wr_tim_conf1.rs
+++ b/esp32c3/src/efuse/wr_tim_conf1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF1")
-            .field("pwr_on_num", &format_args!("{}", self.pwr_on_num().bits()))
+            .field("pwr_on_num", &self.pwr_on_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:23 - Configures the power up time for VDDQ."]
     #[inline(always)]
diff --git a/esp32c3/src/efuse/wr_tim_conf2.rs b/esp32c3/src/efuse/wr_tim_conf2.rs
index 80c193cb0d..eb2cfd48b6 100644
--- a/esp32c3/src/efuse/wr_tim_conf2.rs
+++ b/esp32c3/src/efuse/wr_tim_conf2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF2")
-            .field(
-                "pwr_off_num",
-                &format_args!("{}", self.pwr_off_num().bits()),
-            )
+            .field("pwr_off_num", &self.pwr_off_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures the power outage time for VDDQ."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/cache_conf_misc.rs b/esp32c3/src/extmem/cache_conf_misc.rs
index 52abd1dd8f..3838f7bc81 100644
--- a/esp32c3/src/extmem/cache_conf_misc.rs
+++ b/esp32c3/src/extmem/cache_conf_misc.rs
@@ -37,25 +37,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("CACHE_CONF_MISC")
             .field(
                 "cache_ignore_preload_mmu_entry_fault",
-                &format_args!("{}", self.cache_ignore_preload_mmu_entry_fault().bit()),
+                &self.cache_ignore_preload_mmu_entry_fault(),
             )
             .field(
                 "cache_ignore_sync_mmu_entry_fault",
-                &format_args!("{}", self.cache_ignore_sync_mmu_entry_fault().bit()),
-            )
-            .field(
-                "cache_trace_ena",
-                &format_args!("{}", self.cache_trace_ena().bit()),
+                &self.cache_ignore_sync_mmu_entry_fault(),
             )
+            .field("cache_trace_ena", &self.cache_trace_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CONF_MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable checking mmu entry fault by preload operation."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/cache_encrypt_decrypt_clk_force_on.rs b/esp32c3/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
index 3a05102710..923f8273e8 100644
--- a/esp32c3/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
+++ b/esp32c3/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON")
             .field(
                 "clk_force_on_manual_crypt",
-                &format_args!("{}", self.clk_force_on_manual_crypt().bit()),
-            )
-            .field(
-                "clk_force_on_auto_crypt",
-                &format_args!("{}", self.clk_force_on_auto_crypt().bit()),
-            )
-            .field(
-                "clk_force_on_crypt",
-                &format_args!("{}", self.clk_force_on_crypt().bit()),
+                &self.clk_force_on_manual_crypt(),
             )
+            .field("clk_force_on_auto_crypt", &self.clk_force_on_auto_crypt())
+            .field("clk_force_on_crypt", &self.clk_force_on_crypt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/cache_encrypt_decrypt_record_disable.rs b/esp32c3/src/extmem/cache_encrypt_decrypt_record_disable.rs
index 9c41127873..96c9078f3e 100644
--- a/esp32c3/src/extmem/cache_encrypt_decrypt_record_disable.rs
+++ b/esp32c3/src/extmem/cache_encrypt_decrypt_record_disable.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE")
             .field(
                 "record_disable_db_encrypt",
-                &format_args!("{}", self.record_disable_db_encrypt().bit()),
+                &self.record_disable_db_encrypt(),
             )
             .field(
                 "record_disable_g0cb_decrypt",
-                &format_args!("{}", self.record_disable_g0cb_decrypt().bit()),
+                &self.record_disable_g0cb_decrypt(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/cache_ilg_int_ena.rs b/esp32c3/src/extmem/cache_ilg_int_ena.rs
index 82ee5de7bb..c4df66c1db 100644
--- a/esp32c3/src/extmem/cache_ilg_int_ena.rs
+++ b/esp32c3/src/extmem/cache_ilg_int_ena.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_ILG_INT_ENA")
-            .field(
-                "icache_sync_op_fault",
-                &format_args!("{}", self.icache_sync_op_fault().bit()),
-            )
-            .field(
-                "icache_preload_op_fault",
-                &format_args!("{}", self.icache_preload_op_fault().bit()),
-            )
-            .field(
-                "mmu_entry_fault",
-                &format_args!("{}", self.mmu_entry_fault().bit()),
-            )
-            .field(
-                "ibus_cnt_ovf",
-                &format_args!("{}", self.ibus_cnt_ovf().bit()),
-            )
-            .field(
-                "dbus_cnt_ovf",
-                &format_args!("{}", self.dbus_cnt_ovf().bit()),
-            )
+            .field("icache_sync_op_fault", &self.icache_sync_op_fault())
+            .field("icache_preload_op_fault", &self.icache_preload_op_fault())
+            .field("mmu_entry_fault", &self.mmu_entry_fault())
+            .field("ibus_cnt_ovf", &self.ibus_cnt_ovf())
+            .field("dbus_cnt_ovf", &self.dbus_cnt_ovf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_ILG_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable interrupt by sync configurations fault."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/cache_ilg_int_st.rs b/esp32c3/src/extmem/cache_ilg_int_st.rs
index 0ea6947478..8795284dc0 100644
--- a/esp32c3/src/extmem/cache_ilg_int_st.rs
+++ b/esp32c3/src/extmem/cache_ilg_int_st.rs
@@ -55,43 +55,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_ILG_INT_ST")
-            .field(
-                "icache_sync_op_fault",
-                &format_args!("{}", self.icache_sync_op_fault().bit()),
-            )
-            .field(
-                "icache_preload_op_fault",
-                &format_args!("{}", self.icache_preload_op_fault().bit()),
-            )
-            .field(
-                "mmu_entry_fault",
-                &format_args!("{}", self.mmu_entry_fault().bit()),
-            )
-            .field(
-                "ibus_acs_cnt_ovf",
-                &format_args!("{}", self.ibus_acs_cnt_ovf().bit()),
-            )
-            .field(
-                "ibus_acs_miss_cnt_ovf",
-                &format_args!("{}", self.ibus_acs_miss_cnt_ovf().bit()),
-            )
-            .field(
-                "dbus_acs_cnt_ovf",
-                &format_args!("{}", self.dbus_acs_cnt_ovf().bit()),
-            )
+            .field("icache_sync_op_fault", &self.icache_sync_op_fault())
+            .field("icache_preload_op_fault", &self.icache_preload_op_fault())
+            .field("mmu_entry_fault", &self.mmu_entry_fault())
+            .field("ibus_acs_cnt_ovf", &self.ibus_acs_cnt_ovf())
+            .field("ibus_acs_miss_cnt_ovf", &self.ibus_acs_miss_cnt_ovf())
+            .field("dbus_acs_cnt_ovf", &self.dbus_acs_cnt_ovf())
             .field(
                 "dbus_acs_flash_miss_cnt_ovf",
-                &format_args!("{}", self.dbus_acs_flash_miss_cnt_ovf().bit()),
+                &self.dbus_acs_flash_miss_cnt_ovf(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_ILG_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_ilg_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_ILG_INT_ST_SPEC;
 impl crate::RegisterSpec for CACHE_ILG_INT_ST_SPEC {
diff --git a/esp32c3/src/extmem/cache_mmu_fault_content.rs b/esp32c3/src/extmem/cache_mmu_fault_content.rs
index 88ceadb32e..5026913ff1 100644
--- a/esp32c3/src/extmem/cache_mmu_fault_content.rs
+++ b/esp32c3/src/extmem/cache_mmu_fault_content.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_FAULT_CONTENT")
-            .field(
-                "cache_mmu_fault_content",
-                &format_args!("{}", self.cache_mmu_fault_content().bits()),
-            )
-            .field(
-                "cache_mmu_fault_code",
-                &format_args!("{}", self.cache_mmu_fault_code().bits()),
-            )
+            .field("cache_mmu_fault_content", &self.cache_mmu_fault_content())
+            .field("cache_mmu_fault_code", &self.cache_mmu_fault_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_FAULT_CONTENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_mmu_fault_content::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_MMU_FAULT_CONTENT_SPEC;
 impl crate::RegisterSpec for CACHE_MMU_FAULT_CONTENT_SPEC {
diff --git a/esp32c3/src/extmem/cache_mmu_fault_vaddr.rs b/esp32c3/src/extmem/cache_mmu_fault_vaddr.rs
index 259c7a8f7a..d7426d0622 100644
--- a/esp32c3/src/extmem/cache_mmu_fault_vaddr.rs
+++ b/esp32c3/src/extmem/cache_mmu_fault_vaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_FAULT_VADDR")
-            .field(
-                "cache_mmu_fault_vaddr",
-                &format_args!("{}", self.cache_mmu_fault_vaddr().bits()),
-            )
+            .field("cache_mmu_fault_vaddr", &self.cache_mmu_fault_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_FAULT_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_mmu_fault_vaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_MMU_FAULT_VADDR_SPEC;
 impl crate::RegisterSpec for CACHE_MMU_FAULT_VADDR_SPEC {
diff --git a/esp32c3/src/extmem/cache_mmu_owner.rs b/esp32c3/src/extmem/cache_mmu_owner.rs
index a3d072da00..0e51e3b984 100644
--- a/esp32c3/src/extmem/cache_mmu_owner.rs
+++ b/esp32c3/src/extmem/cache_mmu_owner.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_OWNER")
-            .field(
-                "cache_mmu_owner",
-                &format_args!("{}", self.cache_mmu_owner().bits()),
-            )
+            .field("cache_mmu_owner", &self.cache_mmu_owner())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_OWNER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/cache_mmu_power_ctrl.rs b/esp32c3/src/extmem/cache_mmu_power_ctrl.rs
index 78764d6540..fea61d4975 100644
--- a/esp32c3/src/extmem/cache_mmu_power_ctrl.rs
+++ b/esp32c3/src/extmem/cache_mmu_power_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_POWER_CTRL")
-            .field(
-                "cache_mmu_mem_force_on",
-                &format_args!("{}", self.cache_mmu_mem_force_on().bit()),
-            )
-            .field(
-                "cache_mmu_mem_force_pd",
-                &format_args!("{}", self.cache_mmu_mem_force_pd().bit()),
-            )
-            .field(
-                "cache_mmu_mem_force_pu",
-                &format_args!("{}", self.cache_mmu_mem_force_pu().bit()),
-            )
+            .field("cache_mmu_mem_force_on", &self.cache_mmu_mem_force_on())
+            .field("cache_mmu_mem_force_pd", &self.cache_mmu_mem_force_pd())
+            .field("cache_mmu_mem_force_pu", &self.cache_mmu_mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/cache_preload_int_ctrl.rs b/esp32c3/src/extmem/cache_preload_int_ctrl.rs
index 722c0de8ae..9e7cb958f8 100644
--- a/esp32c3/src/extmem/cache_preload_int_ctrl.rs
+++ b/esp32c3/src/extmem/cache_preload_int_ctrl.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_PRELOAD_INT_CTRL")
-            .field("st", &format_args!("{}", self.st().bit()))
-            .field("ena", &format_args!("{}", self.ena().bit()))
+            .field("st", &self.st())
+            .field("ena", &self.ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_PRELOAD_INT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - The bit is used to enable the interrupt by icache pre-load done."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/cache_request.rs b/esp32c3/src/extmem/cache_request.rs
index 8ff3734f13..7717cb7164 100644
--- a/esp32c3/src/extmem/cache_request.rs
+++ b/esp32c3/src/extmem/cache_request.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_REQUEST")
-            .field("bypass", &format_args!("{}", self.bypass().bit()))
+            .field("bypass", &self.bypass())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_REQUEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable request recording which could cause performance issue"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/cache_state.rs b/esp32c3/src/extmem/cache_state.rs
index 57c172ae51..897f15abc7 100644
--- a/esp32c3/src/extmem/cache_state.rs
+++ b/esp32c3/src/extmem/cache_state.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_STATE")
-            .field(
-                "icache_state",
-                &format_args!("{}", self.icache_state().bits()),
-            )
+            .field("icache_state", &self.icache_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_STATE_SPEC;
 impl crate::RegisterSpec for CACHE_STATE_SPEC {
diff --git a/esp32c3/src/extmem/cache_sync_int_ctrl.rs b/esp32c3/src/extmem/cache_sync_int_ctrl.rs
index bd3dab87e5..ff6cccfc1d 100644
--- a/esp32c3/src/extmem/cache_sync_int_ctrl.rs
+++ b/esp32c3/src/extmem/cache_sync_int_ctrl.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_SYNC_INT_CTRL")
-            .field("st", &format_args!("{}", self.st().bit()))
-            .field("ena", &format_args!("{}", self.ena().bit()))
+            .field("st", &self.st())
+            .field("ena", &self.ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_SYNC_INT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - The bit is used to enable the interrupt by icache sync done."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/cache_wrap_around_ctrl.rs b/esp32c3/src/extmem/cache_wrap_around_ctrl.rs
index df47c13944..8c8e5fe6fb 100644
--- a/esp32c3/src/extmem/cache_wrap_around_ctrl.rs
+++ b/esp32c3/src/extmem/cache_wrap_around_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_WRAP_AROUND_CTRL")
-            .field(
-                "cache_flash_wrap_around",
-                &format_args!("{}", self.cache_flash_wrap_around().bit()),
-            )
+            .field("cache_flash_wrap_around", &self.cache_flash_wrap_around())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_WRAP_AROUND_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable wrap around mode when read data from flash."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/clock_gate.rs b/esp32c3/src/extmem/clock_gate.rs
index 10a6a1b70f..9f7a96137e 100644
--- a/esp32c3/src/extmem/clock_gate.rs
+++ b/esp32c3/src/extmem/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - clock gate enable."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/core0_acs_cache_int_ena.rs b/esp32c3/src/extmem/core0_acs_cache_int_ena.rs
index b7f892f452..a718d0c112 100644
--- a/esp32c3/src/extmem/core0_acs_cache_int_ena.rs
+++ b/esp32c3/src/extmem/core0_acs_cache_int_ena.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE0_ACS_CACHE_INT_ENA")
-            .field(
-                "core0_ibus_acs_msk_ic",
-                &format_args!("{}", self.core0_ibus_acs_msk_ic().bit()),
-            )
-            .field(
-                "core0_ibus_wr_ic",
-                &format_args!("{}", self.core0_ibus_wr_ic().bit()),
-            )
-            .field(
-                "core0_ibus_reject",
-                &format_args!("{}", self.core0_ibus_reject().bit()),
-            )
-            .field(
-                "core0_dbus_acs_msk_ic",
-                &format_args!("{}", self.core0_dbus_acs_msk_ic().bit()),
-            )
-            .field(
-                "core0_dbus_reject",
-                &format_args!("{}", self.core0_dbus_reject().bit()),
-            )
-            .field(
-                "core0_dbus_wr_ic",
-                &format_args!("{}", self.core0_dbus_wr_ic().bit()),
-            )
+            .field("core0_ibus_acs_msk_ic", &self.core0_ibus_acs_msk_ic())
+            .field("core0_ibus_wr_ic", &self.core0_ibus_wr_ic())
+            .field("core0_ibus_reject", &self.core0_ibus_reject())
+            .field("core0_dbus_acs_msk_ic", &self.core0_dbus_acs_msk_ic())
+            .field("core0_dbus_reject", &self.core0_dbus_reject())
+            .field("core0_dbus_wr_ic", &self.core0_dbus_wr_ic())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_ACS_CACHE_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/core0_acs_cache_int_st.rs b/esp32c3/src/extmem/core0_acs_cache_int_st.rs
index c4ffbb6de4..3c73f9c30d 100644
--- a/esp32c3/src/extmem/core0_acs_cache_int_st.rs
+++ b/esp32c3/src/extmem/core0_acs_cache_int_st.rs
@@ -50,37 +50,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE0_ACS_CACHE_INT_ST")
             .field(
                 "core0_ibus_acs_msk_icache",
-                &format_args!("{}", self.core0_ibus_acs_msk_icache().bit()),
-            )
-            .field(
-                "core0_ibus_wr_icache",
-                &format_args!("{}", self.core0_ibus_wr_icache().bit()),
-            )
-            .field(
-                "core0_ibus_reject",
-                &format_args!("{}", self.core0_ibus_reject().bit()),
+                &self.core0_ibus_acs_msk_icache(),
             )
+            .field("core0_ibus_wr_icache", &self.core0_ibus_wr_icache())
+            .field("core0_ibus_reject", &self.core0_ibus_reject())
             .field(
                 "core0_dbus_acs_msk_icache",
-                &format_args!("{}", self.core0_dbus_acs_msk_icache().bit()),
-            )
-            .field(
-                "core0_dbus_reject",
-                &format_args!("{}", self.core0_dbus_reject().bit()),
-            )
-            .field(
-                "core0_dbus_wr_icache",
-                &format_args!("{}", self.core0_dbus_wr_icache().bit()),
+                &self.core0_dbus_acs_msk_icache(),
             )
+            .field("core0_dbus_reject", &self.core0_dbus_reject())
+            .field("core0_dbus_wr_icache", &self.core0_dbus_wr_icache())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_ACS_CACHE_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_acs_cache_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE0_ACS_CACHE_INT_ST_SPEC;
 impl crate::RegisterSpec for CORE0_ACS_CACHE_INT_ST_SPEC {
diff --git a/esp32c3/src/extmem/core0_dbus_reject_st.rs b/esp32c3/src/extmem/core0_dbus_reject_st.rs
index 8fdfd8c053..a4bc8e7799 100644
--- a/esp32c3/src/extmem/core0_dbus_reject_st.rs
+++ b/esp32c3/src/extmem/core0_dbus_reject_st.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE0_DBUS_REJECT_ST")
-            .field(
-                "core0_dbus_attr",
-                &format_args!("{}", self.core0_dbus_attr().bits()),
-            )
-            .field(
-                "core0_dbus_world",
-                &format_args!("{}", self.core0_dbus_world().bit()),
-            )
+            .field("core0_dbus_attr", &self.core0_dbus_attr())
+            .field("core0_dbus_world", &self.core0_dbus_world())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_DBUS_REJECT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_dbus_reject_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE0_DBUS_REJECT_ST_SPEC;
 impl crate::RegisterSpec for CORE0_DBUS_REJECT_ST_SPEC {
diff --git a/esp32c3/src/extmem/core0_dbus_reject_vaddr.rs b/esp32c3/src/extmem/core0_dbus_reject_vaddr.rs
index 68c7e84849..a17bb73b98 100644
--- a/esp32c3/src/extmem/core0_dbus_reject_vaddr.rs
+++ b/esp32c3/src/extmem/core0_dbus_reject_vaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE0_DBUS_REJECT_VADDR")
-            .field(
-                "core0_dbus_vaddr",
-                &format_args!("{}", self.core0_dbus_vaddr().bits()),
-            )
+            .field("core0_dbus_vaddr", &self.core0_dbus_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_DBUS_REJECT_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_dbus_reject_vaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE0_DBUS_REJECT_VADDR_SPEC;
 impl crate::RegisterSpec for CORE0_DBUS_REJECT_VADDR_SPEC {
diff --git a/esp32c3/src/extmem/core0_ibus_reject_st.rs b/esp32c3/src/extmem/core0_ibus_reject_st.rs
index 50c6012fe5..0aaa797004 100644
--- a/esp32c3/src/extmem/core0_ibus_reject_st.rs
+++ b/esp32c3/src/extmem/core0_ibus_reject_st.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE0_IBUS_REJECT_ST")
-            .field(
-                "core0_ibus_attr",
-                &format_args!("{}", self.core0_ibus_attr().bits()),
-            )
-            .field(
-                "core0_ibus_world",
-                &format_args!("{}", self.core0_ibus_world().bit()),
-            )
+            .field("core0_ibus_attr", &self.core0_ibus_attr())
+            .field("core0_ibus_world", &self.core0_ibus_world())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_IBUS_REJECT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_ibus_reject_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE0_IBUS_REJECT_ST_SPEC;
 impl crate::RegisterSpec for CORE0_IBUS_REJECT_ST_SPEC {
diff --git a/esp32c3/src/extmem/core0_ibus_reject_vaddr.rs b/esp32c3/src/extmem/core0_ibus_reject_vaddr.rs
index b057eee3ec..5ec40b0949 100644
--- a/esp32c3/src/extmem/core0_ibus_reject_vaddr.rs
+++ b/esp32c3/src/extmem/core0_ibus_reject_vaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE0_IBUS_REJECT_VADDR")
-            .field(
-                "core0_ibus_vaddr",
-                &format_args!("{}", self.core0_ibus_vaddr().bits()),
-            )
+            .field("core0_ibus_vaddr", &self.core0_ibus_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_IBUS_REJECT_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_ibus_reject_vaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE0_IBUS_REJECT_VADDR_SPEC;
 impl crate::RegisterSpec for CORE0_IBUS_REJECT_VADDR_SPEC {
diff --git a/esp32c3/src/extmem/dbus_acs_cnt.rs b/esp32c3/src/extmem/dbus_acs_cnt.rs
index 44be557f28..cd77cdb019 100644
--- a/esp32c3/src/extmem/dbus_acs_cnt.rs
+++ b/esp32c3/src/extmem/dbus_acs_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS_ACS_CNT")
-            .field(
-                "dbus_acs_cnt",
-                &format_args!("{}", self.dbus_acs_cnt().bits()),
-            )
+            .field("dbus_acs_cnt", &self.dbus_acs_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_ACS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus_acs_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS_ACS_CNT_SPEC;
 impl crate::RegisterSpec for DBUS_ACS_CNT_SPEC {
diff --git a/esp32c3/src/extmem/dbus_acs_flash_miss_cnt.rs b/esp32c3/src/extmem/dbus_acs_flash_miss_cnt.rs
index 41502b08ff..79d109ffd6 100644
--- a/esp32c3/src/extmem/dbus_acs_flash_miss_cnt.rs
+++ b/esp32c3/src/extmem/dbus_acs_flash_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS_ACS_FLASH_MISS_CNT")
-            .field(
-                "dbus_acs_flash_miss_cnt",
-                &format_args!("{}", self.dbus_acs_flash_miss_cnt().bits()),
-            )
+            .field("dbus_acs_flash_miss_cnt", &self.dbus_acs_flash_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_ACS_FLASH_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus_acs_flash_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS_ACS_FLASH_MISS_CNT_SPEC;
 impl crate::RegisterSpec for DBUS_ACS_FLASH_MISS_CNT_SPEC {
diff --git a/esp32c3/src/extmem/dbus_pms_tbl_attr.rs b/esp32c3/src/extmem/dbus_pms_tbl_attr.rs
index aa0a763476..73a4f64c41 100644
--- a/esp32c3/src/extmem/dbus_pms_tbl_attr.rs
+++ b/esp32c3/src/extmem/dbus_pms_tbl_attr.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS_PMS_TBL_ATTR")
-            .field(
-                "dbus_pms_sct1_attr",
-                &format_args!("{}", self.dbus_pms_sct1_attr().bits()),
-            )
-            .field(
-                "dbus_pms_sct2_attr",
-                &format_args!("{}", self.dbus_pms_sct2_attr().bits()),
-            )
+            .field("dbus_pms_sct1_attr", &self.dbus_pms_sct1_attr())
+            .field("dbus_pms_sct2_attr", &self.dbus_pms_sct2_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_PMS_TBL_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The bit is used to configure attribute of the dbus permission control section1, bit0: load in world0, bit2: load in world1"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/dbus_pms_tbl_boundary0.rs b/esp32c3/src/extmem/dbus_pms_tbl_boundary0.rs
index db87746b65..18069f2812 100644
--- a/esp32c3/src/extmem/dbus_pms_tbl_boundary0.rs
+++ b/esp32c3/src/extmem/dbus_pms_tbl_boundary0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS_PMS_TBL_BOUNDARY0")
-            .field(
-                "dbus_pms_boundary0",
-                &format_args!("{}", self.dbus_pms_boundary0().bits()),
-            )
+            .field("dbus_pms_boundary0", &self.dbus_pms_boundary0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_PMS_TBL_BOUNDARY0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The bit is used to configure the dbus permission control section boundary0"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/dbus_pms_tbl_boundary1.rs b/esp32c3/src/extmem/dbus_pms_tbl_boundary1.rs
index 680bd51341..1dc23d548e 100644
--- a/esp32c3/src/extmem/dbus_pms_tbl_boundary1.rs
+++ b/esp32c3/src/extmem/dbus_pms_tbl_boundary1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS_PMS_TBL_BOUNDARY1")
-            .field(
-                "dbus_pms_boundary1",
-                &format_args!("{}", self.dbus_pms_boundary1().bits()),
-            )
+            .field("dbus_pms_boundary1", &self.dbus_pms_boundary1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_PMS_TBL_BOUNDARY1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The bit is used to configure the dbus permission control section boundary1"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/dbus_pms_tbl_boundary2.rs b/esp32c3/src/extmem/dbus_pms_tbl_boundary2.rs
index a9ef3f19aa..57e80b77a4 100644
--- a/esp32c3/src/extmem/dbus_pms_tbl_boundary2.rs
+++ b/esp32c3/src/extmem/dbus_pms_tbl_boundary2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS_PMS_TBL_BOUNDARY2")
-            .field(
-                "dbus_pms_boundary2",
-                &format_args!("{}", self.dbus_pms_boundary2().bits()),
-            )
+            .field("dbus_pms_boundary2", &self.dbus_pms_boundary2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_PMS_TBL_BOUNDARY2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The bit is used to configure the dbus permission control section boundary2"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/dbus_pms_tbl_lock.rs b/esp32c3/src/extmem/dbus_pms_tbl_lock.rs
index b8d4024859..ad682c0cec 100644
--- a/esp32c3/src/extmem/dbus_pms_tbl_lock.rs
+++ b/esp32c3/src/extmem/dbus_pms_tbl_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS_PMS_TBL_LOCK")
-            .field(
-                "dbus_pms_lock",
-                &format_args!("{}", self.dbus_pms_lock().bit()),
-            )
+            .field("dbus_pms_lock", &self.dbus_pms_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_PMS_TBL_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to configure the ibus permission control section boundary0"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/dbus_to_flash_end_vaddr.rs b/esp32c3/src/extmem/dbus_to_flash_end_vaddr.rs
index 029bd3824e..8c2f806abd 100644
--- a/esp32c3/src/extmem/dbus_to_flash_end_vaddr.rs
+++ b/esp32c3/src/extmem/dbus_to_flash_end_vaddr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS_TO_FLASH_END_VADDR")
-            .field(
-                "dbus_to_flash_end_vaddr",
-                &format_args!("{}", self.dbus_to_flash_end_vaddr().bits()),
-            )
+            .field("dbus_to_flash_end_vaddr", &self.dbus_to_flash_end_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_TO_FLASH_END_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/dbus_to_flash_start_vaddr.rs b/esp32c3/src/extmem/dbus_to_flash_start_vaddr.rs
index d1c1be85ea..c55bfa68da 100644
--- a/esp32c3/src/extmem/dbus_to_flash_start_vaddr.rs
+++ b/esp32c3/src/extmem/dbus_to_flash_start_vaddr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DBUS_TO_FLASH_START_VADDR")
             .field(
                 "dbus_to_flash_start_vaddr",
-                &format_args!("{}", self.dbus_to_flash_start_vaddr().bits()),
+                &self.dbus_to_flash_start_vaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_TO_FLASH_START_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/ibus_acs_cnt.rs b/esp32c3/src/extmem/ibus_acs_cnt.rs
index f1ff4be11d..2161ef1c74 100644
--- a/esp32c3/src/extmem/ibus_acs_cnt.rs
+++ b/esp32c3/src/extmem/ibus_acs_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS_ACS_CNT")
-            .field(
-                "ibus_acs_cnt",
-                &format_args!("{}", self.ibus_acs_cnt().bits()),
-            )
+            .field("ibus_acs_cnt", &self.ibus_acs_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS_ACS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibus_acs_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IBUS_ACS_CNT_SPEC;
 impl crate::RegisterSpec for IBUS_ACS_CNT_SPEC {
diff --git a/esp32c3/src/extmem/ibus_acs_miss_cnt.rs b/esp32c3/src/extmem/ibus_acs_miss_cnt.rs
index 9de69361e3..c928951a7e 100644
--- a/esp32c3/src/extmem/ibus_acs_miss_cnt.rs
+++ b/esp32c3/src/extmem/ibus_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS_ACS_MISS_CNT")
-            .field(
-                "ibus_acs_miss_cnt",
-                &format_args!("{}", self.ibus_acs_miss_cnt().bits()),
-            )
+            .field("ibus_acs_miss_cnt", &self.ibus_acs_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibus_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IBUS_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for IBUS_ACS_MISS_CNT_SPEC {
diff --git a/esp32c3/src/extmem/ibus_pms_tbl_attr.rs b/esp32c3/src/extmem/ibus_pms_tbl_attr.rs
index 2ae1fdd7ab..08060558bb 100644
--- a/esp32c3/src/extmem/ibus_pms_tbl_attr.rs
+++ b/esp32c3/src/extmem/ibus_pms_tbl_attr.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS_PMS_TBL_ATTR")
-            .field(
-                "ibus_pms_sct1_attr",
-                &format_args!("{}", self.ibus_pms_sct1_attr().bits()),
-            )
-            .field(
-                "ibus_pms_sct2_attr",
-                &format_args!("{}", self.ibus_pms_sct2_attr().bits()),
-            )
+            .field("ibus_pms_sct1_attr", &self.ibus_pms_sct1_attr())
+            .field("ibus_pms_sct2_attr", &self.ibus_pms_sct2_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS_PMS_TBL_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The bit is used to configure attribute of the ibus permission control section1, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/ibus_pms_tbl_boundary0.rs b/esp32c3/src/extmem/ibus_pms_tbl_boundary0.rs
index 9f8f166c61..b65ff44b93 100644
--- a/esp32c3/src/extmem/ibus_pms_tbl_boundary0.rs
+++ b/esp32c3/src/extmem/ibus_pms_tbl_boundary0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS_PMS_TBL_BOUNDARY0")
-            .field(
-                "ibus_pms_boundary0",
-                &format_args!("{}", self.ibus_pms_boundary0().bits()),
-            )
+            .field("ibus_pms_boundary0", &self.ibus_pms_boundary0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS_PMS_TBL_BOUNDARY0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The bit is used to configure the ibus permission control section boundary0"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/ibus_pms_tbl_boundary1.rs b/esp32c3/src/extmem/ibus_pms_tbl_boundary1.rs
index 8d47556340..ead60ef15b 100644
--- a/esp32c3/src/extmem/ibus_pms_tbl_boundary1.rs
+++ b/esp32c3/src/extmem/ibus_pms_tbl_boundary1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS_PMS_TBL_BOUNDARY1")
-            .field(
-                "ibus_pms_boundary1",
-                &format_args!("{}", self.ibus_pms_boundary1().bits()),
-            )
+            .field("ibus_pms_boundary1", &self.ibus_pms_boundary1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS_PMS_TBL_BOUNDARY1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The bit is used to configure the ibus permission control section boundary1"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/ibus_pms_tbl_boundary2.rs b/esp32c3/src/extmem/ibus_pms_tbl_boundary2.rs
index 2254f987dd..8c07a0c2be 100644
--- a/esp32c3/src/extmem/ibus_pms_tbl_boundary2.rs
+++ b/esp32c3/src/extmem/ibus_pms_tbl_boundary2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS_PMS_TBL_BOUNDARY2")
-            .field(
-                "ibus_pms_boundary2",
-                &format_args!("{}", self.ibus_pms_boundary2().bits()),
-            )
+            .field("ibus_pms_boundary2", &self.ibus_pms_boundary2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS_PMS_TBL_BOUNDARY2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The bit is used to configure the ibus permission control section boundary2"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/ibus_pms_tbl_lock.rs b/esp32c3/src/extmem/ibus_pms_tbl_lock.rs
index 4c095c2394..fac09f09ff 100644
--- a/esp32c3/src/extmem/ibus_pms_tbl_lock.rs
+++ b/esp32c3/src/extmem/ibus_pms_tbl_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS_PMS_TBL_LOCK")
-            .field(
-                "ibus_pms_lock",
-                &format_args!("{}", self.ibus_pms_lock().bit()),
-            )
+            .field("ibus_pms_lock", &self.ibus_pms_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS_PMS_TBL_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to configure the ibus permission control section boundary0"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/ibus_to_flash_end_vaddr.rs b/esp32c3/src/extmem/ibus_to_flash_end_vaddr.rs
index c479808432..e58bcee105 100644
--- a/esp32c3/src/extmem/ibus_to_flash_end_vaddr.rs
+++ b/esp32c3/src/extmem/ibus_to_flash_end_vaddr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS_TO_FLASH_END_VADDR")
-            .field(
-                "ibus_to_flash_end_vaddr",
-                &format_args!("{}", self.ibus_to_flash_end_vaddr().bits()),
-            )
+            .field("ibus_to_flash_end_vaddr", &self.ibus_to_flash_end_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS_TO_FLASH_END_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/ibus_to_flash_start_vaddr.rs b/esp32c3/src/extmem/ibus_to_flash_start_vaddr.rs
index 281f5fcb29..2375f70cb2 100644
--- a/esp32c3/src/extmem/ibus_to_flash_start_vaddr.rs
+++ b/esp32c3/src/extmem/ibus_to_flash_start_vaddr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("IBUS_TO_FLASH_START_VADDR")
             .field(
                 "ibus_to_flash_start_vaddr",
-                &format_args!("{}", self.ibus_to_flash_start_vaddr().bits()),
+                &self.ibus_to_flash_start_vaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS_TO_FLASH_START_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_atomic_operate_ena.rs b/esp32c3/src/extmem/icache_atomic_operate_ena.rs
index 618836c304..4b13688395 100644
--- a/esp32c3/src/extmem/icache_atomic_operate_ena.rs
+++ b/esp32c3/src/extmem/icache_atomic_operate_ena.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ICACHE_ATOMIC_OPERATE_ENA")
             .field(
                 "icache_atomic_operate_ena",
-                &format_args!("{}", self.icache_atomic_operate_ena().bit()),
+                &self.icache_atomic_operate_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_ATOMIC_OPERATE_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_autoload_ctrl.rs b/esp32c3/src/extmem/icache_autoload_ctrl.rs
index 7ead1a43b0..27647b8df6 100644
--- a/esp32c3/src/extmem/icache_autoload_ctrl.rs
+++ b/esp32c3/src/extmem/icache_autoload_ctrl.rs
@@ -60,39 +60,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_AUTOLOAD_CTRL")
-            .field(
-                "icache_autoload_sct0_ena",
-                &format_args!("{}", self.icache_autoload_sct0_ena().bit()),
-            )
-            .field(
-                "icache_autoload_sct1_ena",
-                &format_args!("{}", self.icache_autoload_sct1_ena().bit()),
-            )
-            .field(
-                "icache_autoload_ena",
-                &format_args!("{}", self.icache_autoload_ena().bit()),
-            )
-            .field(
-                "icache_autoload_done",
-                &format_args!("{}", self.icache_autoload_done().bit()),
-            )
-            .field(
-                "icache_autoload_order",
-                &format_args!("{}", self.icache_autoload_order().bit()),
-            )
-            .field(
-                "icache_autoload_rqst",
-                &format_args!("{}", self.icache_autoload_rqst().bits()),
-            )
+            .field("icache_autoload_sct0_ena", &self.icache_autoload_sct0_ena())
+            .field("icache_autoload_sct1_ena", &self.icache_autoload_sct1_ena())
+            .field("icache_autoload_ena", &self.icache_autoload_ena())
+            .field("icache_autoload_done", &self.icache_autoload_done())
+            .field("icache_autoload_order", &self.icache_autoload_order())
+            .field("icache_autoload_rqst", &self.icache_autoload_rqst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_AUTOLOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bits are used to enable the first section for autoload operation."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_autoload_sct0_addr.rs b/esp32c3/src/extmem/icache_autoload_sct0_addr.rs
index 6f82746da5..1f1269bac4 100644
--- a/esp32c3/src/extmem/icache_autoload_sct0_addr.rs
+++ b/esp32c3/src/extmem/icache_autoload_sct0_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ICACHE_AUTOLOAD_SCT0_ADDR")
             .field(
                 "icache_autoload_sct0_addr",
-                &format_args!("{}", self.icache_autoload_sct0_addr().bits()),
+                &self.icache_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_AUTOLOAD_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_autoload_sct0_size.rs b/esp32c3/src/extmem/icache_autoload_sct0_size.rs
index 04851dc4fc..cea57038ce 100644
--- a/esp32c3/src/extmem/icache_autoload_sct0_size.rs
+++ b/esp32c3/src/extmem/icache_autoload_sct0_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ICACHE_AUTOLOAD_SCT0_SIZE")
             .field(
                 "icache_autoload_sct0_size",
-                &format_args!("{}", self.icache_autoload_sct0_size().bits()),
+                &self.icache_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_AUTOLOAD_SCT0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:26 - The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_autoload_sct1_addr.rs b/esp32c3/src/extmem/icache_autoload_sct1_addr.rs
index 6778f14f34..8f1adb7c2c 100644
--- a/esp32c3/src/extmem/icache_autoload_sct1_addr.rs
+++ b/esp32c3/src/extmem/icache_autoload_sct1_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ICACHE_AUTOLOAD_SCT1_ADDR")
             .field(
                 "icache_autoload_sct1_addr",
-                &format_args!("{}", self.icache_autoload_sct1_addr().bits()),
+                &self.icache_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_AUTOLOAD_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_autoload_sct1_size.rs b/esp32c3/src/extmem/icache_autoload_sct1_size.rs
index 5c539770de..38e6932c52 100644
--- a/esp32c3/src/extmem/icache_autoload_sct1_size.rs
+++ b/esp32c3/src/extmem/icache_autoload_sct1_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ICACHE_AUTOLOAD_SCT1_SIZE")
             .field(
                 "icache_autoload_sct1_size",
-                &format_args!("{}", self.icache_autoload_sct1_size().bits()),
+                &self.icache_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_AUTOLOAD_SCT1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:26 - The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_ctrl.rs b/esp32c3/src/extmem/icache_ctrl.rs
index d66682cf3e..686c2c437d 100644
--- a/esp32c3/src/extmem/icache_ctrl.rs
+++ b/esp32c3/src/extmem/icache_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_CTRL")
-            .field(
-                "icache_enable",
-                &format_args!("{}", self.icache_enable().bit()),
-            )
+            .field("icache_enable", &self.icache_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_ctrl1.rs b/esp32c3/src/extmem/icache_ctrl1.rs
index cb385d3e1b..67c2d4831e 100644
--- a/esp32c3/src/extmem/icache_ctrl1.rs
+++ b/esp32c3/src/extmem/icache_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_CTRL1")
-            .field(
-                "icache_shut_ibus",
-                &format_args!("{}", self.icache_shut_ibus().bit()),
-            )
-            .field(
-                "icache_shut_dbus",
-                &format_args!("{}", self.icache_shut_dbus().bit()),
-            )
+            .field("icache_shut_ibus", &self.icache_shut_ibus())
+            .field("icache_shut_dbus", &self.icache_shut_dbus())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable core0 ibus, 0: enable, 1: disable"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_freeze.rs b/esp32c3/src/extmem/icache_freeze.rs
index 4005fb2d4f..ec25af3086 100644
--- a/esp32c3/src/extmem/icache_freeze.rs
+++ b/esp32c3/src/extmem/icache_freeze.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_FREEZE")
-            .field("ena", &format_args!("{}", self.ena().bit()))
-            .field("mode", &format_args!("{}", self.mode().bit()))
-            .field("done", &format_args!("{}", self.done().bit()))
+            .field("ena", &self.ena())
+            .field("mode", &self.mode())
+            .field("done", &self.done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_FREEZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable icache freeze mode"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_lock_addr.rs b/esp32c3/src/extmem/icache_lock_addr.rs
index 647b684a91..1c9ad7eac7 100644
--- a/esp32c3/src/extmem/icache_lock_addr.rs
+++ b/esp32c3/src/extmem/icache_lock_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_LOCK_ADDR")
-            .field(
-                "icache_lock_addr",
-                &format_args!("{}", self.icache_lock_addr().bits()),
-            )
+            .field("icache_lock_addr", &self.icache_lock_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_LOCK_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_lock_ctrl.rs b/esp32c3/src/extmem/icache_lock_ctrl.rs
index 6a50f243b4..0fdc422e7c 100644
--- a/esp32c3/src/extmem/icache_lock_ctrl.rs
+++ b/esp32c3/src/extmem/icache_lock_ctrl.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_LOCK_CTRL")
-            .field(
-                "icache_lock_ena",
-                &format_args!("{}", self.icache_lock_ena().bit()),
-            )
-            .field(
-                "icache_unlock_ena",
-                &format_args!("{}", self.icache_unlock_ena().bit()),
-            )
-            .field(
-                "icache_lock_done",
-                &format_args!("{}", self.icache_lock_done().bit()),
-            )
+            .field("icache_lock_ena", &self.icache_lock_ena())
+            .field("icache_unlock_ena", &self.icache_unlock_ena())
+            .field("icache_lock_done", &self.icache_lock_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_LOCK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_lock_size.rs b/esp32c3/src/extmem/icache_lock_size.rs
index 4ad34e5913..cfcabb1b35 100644
--- a/esp32c3/src/extmem/icache_lock_size.rs
+++ b/esp32c3/src/extmem/icache_lock_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_LOCK_SIZE")
-            .field(
-                "icache_lock_size",
-                &format_args!("{}", self.icache_lock_size().bits()),
-            )
+            .field("icache_lock_size", &self.icache_lock_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_LOCK_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_preload_addr.rs b/esp32c3/src/extmem/icache_preload_addr.rs
index 046037f17c..730df132b4 100644
--- a/esp32c3/src/extmem/icache_preload_addr.rs
+++ b/esp32c3/src/extmem/icache_preload_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOAD_ADDR")
-            .field(
-                "icache_preload_addr",
-                &format_args!("{}", self.icache_preload_addr().bits()),
-            )
+            .field("icache_preload_addr", &self.icache_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_preload_ctrl.rs b/esp32c3/src/extmem/icache_preload_ctrl.rs
index 88a5afc243..e8045bc4c2 100644
--- a/esp32c3/src/extmem/icache_preload_ctrl.rs
+++ b/esp32c3/src/extmem/icache_preload_ctrl.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOAD_CTRL")
-            .field(
-                "icache_preload_ena",
-                &format_args!("{}", self.icache_preload_ena().bit()),
-            )
-            .field(
-                "icache_preload_done",
-                &format_args!("{}", self.icache_preload_done().bit()),
-            )
-            .field(
-                "icache_preload_order",
-                &format_args!("{}", self.icache_preload_order().bit()),
-            )
+            .field("icache_preload_ena", &self.icache_preload_ena())
+            .field("icache_preload_done", &self.icache_preload_done())
+            .field("icache_preload_order", &self.icache_preload_order())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_preload_size.rs b/esp32c3/src/extmem/icache_preload_size.rs
index 65365342cd..122c5024e8 100644
--- a/esp32c3/src/extmem/icache_preload_size.rs
+++ b/esp32c3/src/extmem/icache_preload_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOAD_SIZE")
-            .field(
-                "icache_preload_size",
-                &format_args!("{}", self.icache_preload_size().bits()),
-            )
+            .field("icache_preload_size", &self.icache_preload_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG.."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_prelock_ctrl.rs b/esp32c3/src/extmem/icache_prelock_ctrl.rs
index 7531f9f9ea..4b843c552e 100644
--- a/esp32c3/src/extmem/icache_prelock_ctrl.rs
+++ b/esp32c3/src/extmem/icache_prelock_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOCK_CTRL")
-            .field(
-                "icache_prelock_sct0_en",
-                &format_args!("{}", self.icache_prelock_sct0_en().bit()),
-            )
-            .field(
-                "icache_prelock_sct1_en",
-                &format_args!("{}", self.icache_prelock_sct1_en().bit()),
-            )
+            .field("icache_prelock_sct0_en", &self.icache_prelock_sct0_en())
+            .field("icache_prelock_sct1_en", &self.icache_prelock_sct1_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOCK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable the first section of prelock function."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_prelock_sct0_addr.rs b/esp32c3/src/extmem/icache_prelock_sct0_addr.rs
index 0a53a2721a..884557fda5 100644
--- a/esp32c3/src/extmem/icache_prelock_sct0_addr.rs
+++ b/esp32c3/src/extmem/icache_prelock_sct0_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOCK_SCT0_ADDR")
-            .field(
-                "icache_prelock_sct0_addr",
-                &format_args!("{}", self.icache_prelock_sct0_addr().bits()),
-            )
+            .field("icache_prelock_sct0_addr", &self.icache_prelock_sct0_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOCK_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_prelock_sct1_addr.rs b/esp32c3/src/extmem/icache_prelock_sct1_addr.rs
index caf7954d7f..237d073ba4 100644
--- a/esp32c3/src/extmem/icache_prelock_sct1_addr.rs
+++ b/esp32c3/src/extmem/icache_prelock_sct1_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOCK_SCT1_ADDR")
-            .field(
-                "icache_prelock_sct1_addr",
-                &format_args!("{}", self.icache_prelock_sct1_addr().bits()),
-            )
+            .field("icache_prelock_sct1_addr", &self.icache_prelock_sct1_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOCK_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_prelock_sct_size.rs b/esp32c3/src/extmem/icache_prelock_sct_size.rs
index a7e1665d2e..dc95419788 100644
--- a/esp32c3/src/extmem/icache_prelock_sct_size.rs
+++ b/esp32c3/src/extmem/icache_prelock_sct_size.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOCK_SCT_SIZE")
-            .field(
-                "icache_prelock_sct1_size",
-                &format_args!("{}", self.icache_prelock_sct1_size().bits()),
-            )
-            .field(
-                "icache_prelock_sct0_size",
-                &format_args!("{}", self.icache_prelock_sct0_size().bits()),
-            )
+            .field("icache_prelock_sct1_size", &self.icache_prelock_sct1_size())
+            .field("icache_prelock_sct0_size", &self.icache_prelock_sct0_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOCK_SCT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_sync_addr.rs b/esp32c3/src/extmem/icache_sync_addr.rs
index 9cac709d40..e2b333138a 100644
--- a/esp32c3/src/extmem/icache_sync_addr.rs
+++ b/esp32c3/src/extmem/icache_sync_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_SYNC_ADDR")
-            .field(
-                "icache_sync_addr",
-                &format_args!("{}", self.icache_sync_addr().bits()),
-            )
+            .field("icache_sync_addr", &self.icache_sync_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_SYNC_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_sync_ctrl.rs b/esp32c3/src/extmem/icache_sync_ctrl.rs
index 7b54757039..cca9b51d32 100644
--- a/esp32c3/src/extmem/icache_sync_ctrl.rs
+++ b/esp32c3/src/extmem/icache_sync_ctrl.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_SYNC_CTRL")
-            .field(
-                "icache_invalidate_ena",
-                &format_args!("{}", self.icache_invalidate_ena().bit()),
-            )
-            .field(
-                "icache_sync_done",
-                &format_args!("{}", self.icache_sync_done().bit()),
-            )
+            .field("icache_invalidate_ena", &self.icache_invalidate_ena())
+            .field("icache_sync_done", &self.icache_sync_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_SYNC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_sync_size.rs b/esp32c3/src/extmem/icache_sync_size.rs
index ee9ab1b5f5..49b7a8d882 100644
--- a/esp32c3/src/extmem/icache_sync_size.rs
+++ b/esp32c3/src/extmem/icache_sync_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_SYNC_SIZE")
-            .field(
-                "icache_sync_size",
-                &format_args!("{}", self.icache_sync_size().bits()),
-            )
+            .field("icache_sync_size", &self.icache_sync_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_SYNC_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:22 - The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/icache_tag_power_ctrl.rs b/esp32c3/src/extmem/icache_tag_power_ctrl.rs
index c098fe63ce..2c7a413dba 100644
--- a/esp32c3/src/extmem/icache_tag_power_ctrl.rs
+++ b/esp32c3/src/extmem/icache_tag_power_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_TAG_POWER_CTRL")
-            .field(
-                "icache_tag_mem_force_on",
-                &format_args!("{}", self.icache_tag_mem_force_on().bit()),
-            )
-            .field(
-                "icache_tag_mem_force_pd",
-                &format_args!("{}", self.icache_tag_mem_force_pd().bit()),
-            )
-            .field(
-                "icache_tag_mem_force_pu",
-                &format_args!("{}", self.icache_tag_mem_force_pu().bit()),
-            )
+            .field("icache_tag_mem_force_on", &self.icache_tag_mem_force_on())
+            .field("icache_tag_mem_force_pd", &self.icache_tag_mem_force_pd())
+            .field("icache_tag_mem_force_pu", &self.icache_tag_mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_TAG_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32c3/src/extmem/reg_date.rs b/esp32c3/src/extmem/reg_date.rs
index 39b6e4351f..5c1a6867a8 100644
--- a/esp32c3/src/extmem/reg_date.rs
+++ b/esp32c3/src/extmem/reg_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - version information"]
     #[inline(always)]
diff --git a/esp32c3/src/generic.rs b/esp32c3/src/generic.rs
index a2ae6aa053..45ebed16c4 100644
--- a/esp32c3/src/generic.rs
+++ b/esp32c3/src/generic.rs
@@ -48,7 +48,7 @@ pub trait RegisterSpec {
 #[doc = " Raw field type"]
 pub trait FieldSpec: Sized {
     #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
-    type Ux: Copy + PartialEq + From<Self>;
+    type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
 }
 #[doc = " Marker for fields with fixed values"]
 pub trait IsEnum: FieldSpec {}
@@ -237,6 +237,14 @@ impl<REG: Readable + Writable> Reg<REG> {
         );
     }
 }
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
 #[doc(hidden)]
 pub mod raw;
 #[doc = " Register reader."]
@@ -302,6 +310,11 @@ impl<FI: FieldSpec> FieldReader<FI> {
         self.bits
     }
 }
+impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 impl<FI> PartialEq<FI> for FieldReader<FI>
 where
     FI: FieldSpec + Copy,
@@ -338,10 +351,21 @@ impl<FI> BitReader<FI> {
         self.bit()
     }
 }
+impl<FI> core::fmt::Debug for BitReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 #[doc = " Marker for register/field writers which can take any value of specified width"]
 pub struct Safe;
 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
 pub struct Unsafe;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct Range<const MIN: u64, const MAX: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeFrom<const MIN: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeTo<const MAX: u64>;
 #[doc = " Write field Proxy"]
 pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
     raw::FieldWriter<'a, REG, WI, FI, Safety>;
@@ -393,6 +417,58 @@ where
         unsafe { self.bits(value) }
     }
 }
+impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
+    FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN && value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
 impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
diff --git a/esp32c3/src/gpio/bt_select.rs b/esp32c3/src/gpio/bt_select.rs
index d4bbc43143..d78b414754 100644
--- a/esp32c3/src/gpio/bt_select.rs
+++ b/esp32c3/src/gpio/bt_select.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_SELECT")
-            .field("bt_sel", &format_args!("{}", self.bt_sel().bits()))
+            .field("bt_sel", &self.bt_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_SELECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO bit select register"]
     #[inline(always)]
diff --git a/esp32c3/src/gpio/clock_gate.rs b/esp32c3/src/gpio/clock_gate.rs
index ebd199051e..d2bfefd1b8 100644
--- a/esp32c3/src/gpio/clock_gate.rs
+++ b/esp32c3/src/gpio/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this bit to enable GPIO clock gate"]
     #[inline(always)]
diff --git a/esp32c3/src/gpio/cpusdio_int.rs b/esp32c3/src/gpio/cpusdio_int.rs
index bf563ad9c2..0081bc49ad 100644
--- a/esp32c3/src/gpio/cpusdio_int.rs
+++ b/esp32c3/src/gpio/cpusdio_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPUSDIO_INT")
-            .field("sdio_int", &format_args!("{}", self.sdio_int().bits()))
+            .field("sdio_int", &self.sdio_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPUSDIO_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO CPUSDIO interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpusdio_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPUSDIO_INT_SPEC;
 impl crate::RegisterSpec for CPUSDIO_INT_SPEC {
diff --git a/esp32c3/src/gpio/enable.rs b/esp32c3/src/gpio/enable.rs
index 20139e3aa4..17f9d77639 100644
--- a/esp32c3/src/gpio/enable.rs
+++ b/esp32c3/src/gpio/enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - GPIO output enable register for GPIO0-25"]
     #[inline(always)]
diff --git a/esp32c3/src/gpio/func_in_sel_cfg.rs b/esp32c3/src/gpio/func_in_sel_cfg.rs
index 2b4b31c383..2bed8a7021 100644
--- a/esp32c3/src/gpio/func_in_sel_cfg.rs
+++ b/esp32c3/src/gpio/func_in_sel_cfg.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_IN_SEL_CFG")
-            .field("in_sel", &format_args!("{}", self.in_sel().bits()))
-            .field("in_inv_sel", &format_args!("{}", self.in_inv_sel().bit()))
-            .field("sel", &format_args!("{}", self.sel().bit()))
+            .field("in_sel", &self.in_sel())
+            .field("in_inv_sel", &self.in_inv_sel())
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - set this value: s=0-53: connect GPIO\\[s\\] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level."]
     #[inline(always)]
diff --git a/esp32c3/src/gpio/func_out_sel_cfg.rs b/esp32c3/src/gpio/func_out_sel_cfg.rs
index 8173ce0edb..fb8dff8c69 100644
--- a/esp32c3/src/gpio/func_out_sel_cfg.rs
+++ b/esp32c3/src/gpio/func_out_sel_cfg.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_OUT_SEL_CFG")
-            .field("out_sel", &format_args!("{}", self.out_sel().bits()))
-            .field("inv_sel", &format_args!("{}", self.inv_sel().bit()))
-            .field("oen_sel", &format_args!("{}", self.oen_sel().bit()))
-            .field("oen_inv_sel", &format_args!("{}", self.oen_inv_sel().bit()))
+            .field("out_sel", &self.out_sel())
+            .field("inv_sel", &self.inv_sel())
+            .field("oen_sel", &self.oen_sel())
+            .field("oen_inv_sel", &self.oen_inv_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
     #[inline(always)]
diff --git a/esp32c3/src/gpio/in_.rs b/esp32c3/src/gpio/in_.rs
index 282eb8b03d..9a080567a0 100644
--- a/esp32c3/src/gpio/in_.rs
+++ b/esp32c3/src/gpio/in_.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN")
-            .field("data_next", &format_args!("{}", self.data_next().bits()))
+            .field("data_next", &self.data_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO input register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SPEC;
 impl crate::RegisterSpec for IN_SPEC {
diff --git a/esp32c3/src/gpio/out.rs b/esp32c3/src/gpio/out.rs
index 753ac80949..23ab5ee5c1 100644
--- a/esp32c3/src/gpio/out.rs
+++ b/esp32c3/src/gpio/out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT")
-            .field("data_orig", &format_args!("{}", self.data_orig().bits()))
+            .field("data_orig", &self.data_orig())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - GPIO output register for GPIO0-25"]
     #[inline(always)]
diff --git a/esp32c3/src/gpio/pcpu_int.rs b/esp32c3/src/gpio/pcpu_int.rs
index c1e8ee99d3..891c53f38b 100644
--- a/esp32c3/src/gpio/pcpu_int.rs
+++ b/esp32c3/src/gpio/pcpu_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_INT")
-            .field("procpu_int", &format_args!("{}", self.procpu_int().bits()))
+            .field("procpu_int", &self.procpu_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO PRO_CPU interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_INT_SPEC;
 impl crate::RegisterSpec for PCPU_INT_SPEC {
diff --git a/esp32c3/src/gpio/pcpu_nmi_int.rs b/esp32c3/src/gpio/pcpu_nmi_int.rs
index 45fc6335b3..d32d8248ae 100644
--- a/esp32c3/src/gpio/pcpu_nmi_int.rs
+++ b/esp32c3/src/gpio/pcpu_nmi_int.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_NMI_INT")
-            .field(
-                "procpu_nmi_int",
-                &format_args!("{}", self.procpu_nmi_int().bits()),
-            )
+            .field("procpu_nmi_int", &self.procpu_nmi_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_NMI_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO PRO_CPU(not shielded) interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_nmi_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_NMI_INT_SPEC;
 impl crate::RegisterSpec for PCPU_NMI_INT_SPEC {
diff --git a/esp32c3/src/gpio/pin.rs b/esp32c3/src/gpio/pin.rs
index 582513e76d..37d6329326 100644
--- a/esp32c3/src/gpio/pin.rs
+++ b/esp32c3/src/gpio/pin.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN")
-            .field(
-                "sync2_bypass",
-                &format_args!("{}", self.sync2_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field(
-                "sync1_bypass",
-                &format_args!("{}", self.sync1_bypass().bits()),
-            )
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("config", &format_args!("{}", self.config().bits()))
-            .field("int_ena", &format_args!("{}", self.int_ena().bits()))
+            .field("sync2_bypass", &self.sync2_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("sync1_bypass", &self.sync1_bypass())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("config", &self.config())
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
     #[inline(always)]
diff --git a/esp32c3/src/gpio/reg_date.rs b/esp32c3/src/gpio/reg_date.rs
index f882abc16c..f115c60b24 100644
--- a/esp32c3/src/gpio/reg_date.rs
+++ b/esp32c3/src/gpio/reg_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_DATE")
-            .field("reg_date", &format_args!("{}", self.reg_date().bits()))
+            .field("reg_date", &self.reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - version register"]
     #[inline(always)]
diff --git a/esp32c3/src/gpio/sdio_select.rs b/esp32c3/src/gpio/sdio_select.rs
index 0f94b5932d..557422a488 100644
--- a/esp32c3/src/gpio/sdio_select.rs
+++ b/esp32c3/src/gpio/sdio_select.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_SELECT")
-            .field("sdio_sel", &format_args!("{}", self.sdio_sel().bits()))
+            .field("sdio_sel", &self.sdio_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_SELECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - GPIO sdio select register"]
     #[inline(always)]
diff --git a/esp32c3/src/gpio/status.rs b/esp32c3/src/gpio/status.rs
index f12d681ee9..57851e68d7 100644
--- a/esp32c3/src/gpio/status.rs
+++ b/esp32c3/src/gpio/status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("interrupt", &format_args!("{}", self.interrupt().bits()))
+            .field("interrupt", &self.interrupt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - GPIO interrupt status register for GPIO0-25"]
     #[inline(always)]
diff --git a/esp32c3/src/gpio/status_next.rs b/esp32c3/src/gpio/status_next.rs
index 0b2aa2ef46..082a56419c 100644
--- a/esp32c3/src/gpio/status_next.rs
+++ b/esp32c3/src/gpio/status_next.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_NEXT")
-            .field(
-                "status_interrupt_next",
-                &format_args!("{}", self.status_interrupt_next().bits()),
-            )
+            .field("status_interrupt_next", &self.status_interrupt_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_NEXT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt source register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_NEXT_SPEC;
 impl crate::RegisterSpec for STATUS_NEXT_SPEC {
diff --git a/esp32c3/src/gpio/strap.rs b/esp32c3/src/gpio/strap.rs
index dfc141ecfb..3bc90c4409 100644
--- a/esp32c3/src/gpio/strap.rs
+++ b/esp32c3/src/gpio/strap.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STRAP")
-            .field("strapping", &format_args!("{}", self.strapping().bits()))
+            .field("strapping", &self.strapping())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STRAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "pad strapping register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`strap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STRAP_SPEC;
 impl crate::RegisterSpec for STRAP_SPEC {
diff --git a/esp32c3/src/gpio_sd/clock_gate.rs b/esp32c3/src/gpio_sd/clock_gate.rs
index 5d6939c423..449c80d9a8 100644
--- a/esp32c3/src/gpio_sd/clock_gate.rs
+++ b/esp32c3/src/gpio_sd/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Clock enable bit of configuration registers for sigma delta modulation."]
     #[inline(always)]
diff --git a/esp32c3/src/gpio_sd/sigmadelta.rs b/esp32c3/src/gpio_sd/sigmadelta.rs
index 2cb8973865..1d31bcd5d8 100644
--- a/esp32c3/src/gpio_sd/sigmadelta.rs
+++ b/esp32c3/src/gpio_sd/sigmadelta.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SIGMADELTA")
-            .field("in_", &format_args!("{}", self.in_().bits()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
+            .field("in_", &self.in_())
+            .field("prescale", &self.prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SIGMADELTA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."]
     #[inline(always)]
diff --git a/esp32c3/src/gpio_sd/sigmadelta_misc.rs b/esp32c3/src/gpio_sd/sigmadelta_misc.rs
index b0c196b157..973947d549 100644
--- a/esp32c3/src/gpio_sd/sigmadelta_misc.rs
+++ b/esp32c3/src/gpio_sd/sigmadelta_misc.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SIGMADELTA_MISC")
-            .field(
-                "function_clk_en",
-                &format_args!("{}", self.function_clk_en().bit()),
-            )
-            .field("spi_swap", &format_args!("{}", self.spi_swap().bit()))
+            .field("function_clk_en", &self.function_clk_en())
+            .field("spi_swap", &self.spi_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SIGMADELTA_MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - Clock enable bit of sigma delta modulation."]
     #[inline(always)]
diff --git a/esp32c3/src/gpio_sd/version.rs b/esp32c3/src/gpio_sd/version.rs
index 79cc1baf0b..bd1cac1bd3 100644
--- a/esp32c3/src/gpio_sd/version.rs
+++ b/esp32c3/src/gpio_sd/version.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field(
-                "gpio_sd_date",
-                &format_args!("{}", self.gpio_sd_date().bits()),
-            )
+            .field("gpio_sd_date", &self.gpio_sd_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register."]
     #[inline(always)]
diff --git a/esp32c3/src/hmac/query_busy.rs b/esp32c3/src/hmac/query_busy.rs
index b2162c1fb3..6f817e76f4 100644
--- a/esp32c3/src/hmac/query_busy.rs
+++ b/esp32c3/src/hmac/query_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_BUSY")
-            .field("busy_state", &format_args!("{}", self.busy_state().bit()))
+            .field("busy_state", &self.busy_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Busy register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_BUSY_SPEC;
 impl crate::RegisterSpec for QUERY_BUSY_SPEC {
diff --git a/esp32c3/src/hmac/query_error.rs b/esp32c3/src/hmac/query_error.rs
index dccd8dd32f..8f5b2d284b 100644
--- a/esp32c3/src/hmac/query_error.rs
+++ b/esp32c3/src/hmac/query_error.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_ERROR")
-            .field("query_check", &format_args!("{}", self.query_check().bit()))
+            .field("query_check", &self.query_check())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_ERROR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Error register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_error::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_ERROR_SPEC;
 impl crate::RegisterSpec for QUERY_ERROR_SPEC {
diff --git a/esp32c3/src/hmac/rd_result_mem.rs b/esp32c3/src/hmac/rd_result_mem.rs
index e93fc1892c..15ad43ddc6 100644
--- a/esp32c3/src/hmac/rd_result_mem.rs
+++ b/esp32c3/src/hmac/rd_result_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RESULT_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Result from upstream.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_result_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rd_result_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RESULT_MEM_SPEC;
diff --git a/esp32c3/src/hmac/wr_message_mem.rs b/esp32c3/src/hmac/wr_message_mem.rs
index e4eda3e0e5..2779a44011 100644
--- a/esp32c3/src/hmac/wr_message_mem.rs
+++ b/esp32c3/src/hmac/wr_message_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_MESSAGE_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Message block memory.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_message_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_message_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WR_MESSAGE_MEM_SPEC;
diff --git a/esp32c3/src/i2c0/clk_conf.rs b/esp32c3/src/i2c0/clk_conf.rs
index d5661974f8..79e6631d54 100644
--- a/esp32c3/src/i2c0/clk_conf.rs
+++ b/esp32c3/src/i2c0/clk_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bit()))
-            .field("sclk_active", &format_args!("{}", self.sclk_active().bit()))
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_active", &self.sclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - reg_sclk_div_num"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/comd.rs b/esp32c3/src/i2c0/comd.rs
index 05c8243650..529c1ead88 100644
--- a/esp32c3/src/i2c0/comd.rs
+++ b/esp32c3/src/i2c0/comd.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMD")
-            .field("command", &format_args!("{}", self.command().bits()))
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - reg_command"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/ctr.rs b/esp32c3/src/i2c0/ctr.rs
index 576495faa8..631c0daa4f 100644
--- a/esp32c3/src/i2c0/ctr.rs
+++ b/esp32c3/src/i2c0/ctr.rs
@@ -122,57 +122,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTR")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field(
-                "sample_scl_level",
-                &format_args!("{}", self.sample_scl_level().bit()),
-            )
-            .field(
-                "rx_full_ack_level",
-                &format_args!("{}", self.rx_full_ack_level().bit()),
-            )
-            .field("ms_mode", &format_args!("{}", self.ms_mode().bit()))
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "arbitration_en",
-                &format_args!("{}", self.arbitration_en().bit()),
-            )
-            .field(
-                "slv_tx_auto_start_en",
-                &format_args!("{}", self.slv_tx_auto_start_en().bit()),
-            )
-            .field(
-                "addr_10bit_rw_check_en",
-                &format_args!("{}", self.addr_10bit_rw_check_en().bit()),
-            )
-            .field(
-                "addr_broadcasting_en",
-                &format_args!("{}", self.addr_broadcasting_en().bit()),
-            )
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("sample_scl_level", &self.sample_scl_level())
+            .field("rx_full_ack_level", &self.rx_full_ack_level())
+            .field("ms_mode", &self.ms_mode())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("clk_en", &self.clk_en())
+            .field("arbitration_en", &self.arbitration_en())
+            .field("slv_tx_auto_start_en", &self.slv_tx_auto_start_en())
+            .field("addr_10bit_rw_check_en", &self.addr_10bit_rw_check_en())
+            .field("addr_broadcasting_en", &self.addr_broadcasting_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_sda_force_out"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/data.rs b/esp32c3/src/i2c0/data.rs
index 1d702773e7..fccb2b9187 100644
--- a/esp32c3/src/i2c0/data.rs
+++ b/esp32c3/src/i2c0/data.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field("fifo_rdata", &format_args!("{}", self.fifo_rdata().bits()))
+            .field("fifo_rdata", &self.fifo_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - reg_fifo_rdata"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/date.rs b/esp32c3/src/i2c0/date.rs
index de990eb607..30abe57bd3 100644
--- a/esp32c3/src/i2c0/date.rs
+++ b/esp32c3/src/i2c0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/i2c0/fifo_conf.rs b/esp32c3/src/i2c0/fifo_conf.rs
index 286b137f6e..eab2156c47 100644
--- a/esp32c3/src/i2c0/fifo_conf.rs
+++ b/esp32c3/src/i2c0/fifo_conf.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CONF")
-            .field(
-                "rxfifo_wm_thrhd",
-                &format_args!("{}", self.rxfifo_wm_thrhd().bits()),
-            )
-            .field(
-                "txfifo_wm_thrhd",
-                &format_args!("{}", self.txfifo_wm_thrhd().bits()),
-            )
-            .field("nonfifo_en", &format_args!("{}", self.nonfifo_en().bit()))
-            .field(
-                "fifo_addr_cfg_en",
-                &format_args!("{}", self.fifo_addr_cfg_en().bit()),
-            )
-            .field("rx_fifo_rst", &format_args!("{}", self.rx_fifo_rst().bit()))
-            .field("tx_fifo_rst", &format_args!("{}", self.tx_fifo_rst().bit()))
-            .field("fifo_prt_en", &format_args!("{}", self.fifo_prt_en().bit()))
+            .field("rxfifo_wm_thrhd", &self.rxfifo_wm_thrhd())
+            .field("txfifo_wm_thrhd", &self.txfifo_wm_thrhd())
+            .field("nonfifo_en", &self.nonfifo_en())
+            .field("fifo_addr_cfg_en", &self.fifo_addr_cfg_en())
+            .field("rx_fifo_rst", &self.rx_fifo_rst())
+            .field("tx_fifo_rst", &self.tx_fifo_rst())
+            .field("fifo_prt_en", &self.fifo_prt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_rxfifo_wm_thrhd"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/fifo_st.rs b/esp32c3/src/i2c0/fifo_st.rs
index 89060ebc5e..b4e8167d27 100644
--- a/esp32c3/src/i2c0/fifo_st.rs
+++ b/esp32c3/src/i2c0/fifo_st.rs
@@ -41,35 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_ST")
-            .field(
-                "rxfifo_raddr",
-                &format_args!("{}", self.rxfifo_raddr().bits()),
-            )
-            .field(
-                "rxfifo_waddr",
-                &format_args!("{}", self.rxfifo_waddr().bits()),
-            )
-            .field(
-                "txfifo_raddr",
-                &format_args!("{}", self.txfifo_raddr().bits()),
-            )
-            .field(
-                "txfifo_waddr",
-                &format_args!("{}", self.txfifo_waddr().bits()),
-            )
-            .field(
-                "slave_rw_point",
-                &format_args!("{}", self.slave_rw_point().bits()),
-            )
+            .field("rxfifo_raddr", &self.rxfifo_raddr())
+            .field("rxfifo_waddr", &self.rxfifo_waddr())
+            .field("txfifo_raddr", &self.txfifo_raddr())
+            .field("txfifo_waddr", &self.txfifo_waddr())
+            .field("slave_rw_point", &self.slave_rw_point())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C_FIFO_ST_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_ST_SPEC;
 impl crate::RegisterSpec for FIFO_ST_SPEC {
diff --git a/esp32c3/src/i2c0/filter_cfg.rs b/esp32c3/src/i2c0/filter_cfg.rs
index b54799c9ce..1006fbafdc 100644
--- a/esp32c3/src/i2c0/filter_cfg.rs
+++ b/esp32c3/src/i2c0/filter_cfg.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CFG")
-            .field(
-                "scl_filter_thres",
-                &format_args!("{}", self.scl_filter_thres().bits()),
-            )
-            .field(
-                "sda_filter_thres",
-                &format_args!("{}", self.sda_filter_thres().bits()),
-            )
-            .field(
-                "scl_filter_en",
-                &format_args!("{}", self.scl_filter_en().bit()),
-            )
-            .field(
-                "sda_filter_en",
-                &format_args!("{}", self.sda_filter_en().bit()),
-            )
+            .field("scl_filter_thres", &self.scl_filter_thres())
+            .field("sda_filter_thres", &self.sda_filter_thres())
+            .field("scl_filter_en", &self.scl_filter_en())
+            .field("sda_filter_en", &self.sda_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - reg_scl_filter_thres"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/int_ena.rs b/esp32c3/src/i2c0/int_ena.rs
index dae3449dd1..831dd0a463 100644
--- a/esp32c3/src/i2c0/int_ena.rs
+++ b/esp32c3/src/i2c0/int_ena.rs
@@ -170,54 +170,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
-            .field(
-                "general_call",
-                &format_args!("{}", self.general_call().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
+            .field("general_call", &self.general_call())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_rxfifo_wm_int_ena"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/int_raw.rs b/esp32c3/src/i2c0/int_raw.rs
index 226223b85a..7a6f922b76 100644
--- a/esp32c3/src/i2c0/int_raw.rs
+++ b/esp32c3/src/i2c0/int_raw.rs
@@ -132,54 +132,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
-            .field(
-                "general_call",
-                &format_args!("{}", self.general_call().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
+            .field("general_call", &self.general_call())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C_INT_RAW_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32c3/src/i2c0/int_st.rs b/esp32c3/src/i2c0/int_st.rs
index bf9cbbd87f..8b8b34e72d 100644
--- a/esp32c3/src/i2c0/int_st.rs
+++ b/esp32c3/src/i2c0/int_st.rs
@@ -132,54 +132,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
-            .field(
-                "general_call",
-                &format_args!("{}", self.general_call().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
+            .field("general_call", &self.general_call())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C_INT_STATUS_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c3/src/i2c0/rxfifo_start_addr.rs b/esp32c3/src/i2c0/rxfifo_start_addr.rs
index 8ae4468e45..78eaa6e7fe 100644
--- a/esp32c3/src/i2c0/rxfifo_start_addr.rs
+++ b/esp32c3/src/i2c0/rxfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXFIFO_START_ADDR")
-            .field(
-                "rxfifo_start_addr",
-                &format_args!("{}", self.rxfifo_start_addr().bits()),
-            )
+            .field("rxfifo_start_addr", &self.rxfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C_RXFIFO_START_ADDR_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for RXFIFO_START_ADDR_SPEC {
diff --git a/esp32c3/src/i2c0/scl_high_period.rs b/esp32c3/src/i2c0/scl_high_period.rs
index ebccae5a95..fccf2b0a01 100644
--- a/esp32c3/src/i2c0/scl_high_period.rs
+++ b/esp32c3/src/i2c0/scl_high_period.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH_PERIOD")
-            .field(
-                "scl_high_period",
-                &format_args!("{}", self.scl_high_period().bits()),
-            )
-            .field(
-                "scl_wait_high_period",
-                &format_args!("{}", self.scl_wait_high_period().bits()),
-            )
+            .field("scl_high_period", &self.scl_high_period())
+            .field("scl_wait_high_period", &self.scl_wait_high_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - reg_scl_high_period"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/scl_low_period.rs b/esp32c3/src/i2c0/scl_low_period.rs
index a8eb91d7b8..207d96b9b6 100644
--- a/esp32c3/src/i2c0/scl_low_period.rs
+++ b/esp32c3/src/i2c0/scl_low_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW_PERIOD")
-            .field(
-                "scl_low_period",
-                &format_args!("{}", self.scl_low_period().bits()),
-            )
+            .field("scl_low_period", &self.scl_low_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - reg_scl_low_period"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/scl_main_st_time_out.rs b/esp32c3/src/i2c0/scl_main_st_time_out.rs
index 4f7fba23a7..5276dd3d84 100644
--- a/esp32c3/src/i2c0/scl_main_st_time_out.rs
+++ b/esp32c3/src/i2c0/scl_main_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_MAIN_ST_TIME_OUT")
-            .field(
-                "scl_main_st_to_i2c",
-                &format_args!("{}", self.scl_main_st_to_i2c().bits()),
-            )
+            .field("scl_main_st_to_i2c", &self.scl_main_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_MAIN_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_scl_main_st_to_regno more than 23"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/scl_rstart_setup.rs b/esp32c3/src/i2c0/scl_rstart_setup.rs
index fbe2fed9b5..82314066ed 100644
--- a/esp32c3/src/i2c0/scl_rstart_setup.rs
+++ b/esp32c3/src/i2c0/scl_rstart_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_RSTART_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_RSTART_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - reg_scl_rstart_setup_time"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/scl_sp_conf.rs b/esp32c3/src/i2c0/scl_sp_conf.rs
index 4f82ead0a4..fb99cd455e 100644
--- a/esp32c3/src/i2c0/scl_sp_conf.rs
+++ b/esp32c3/src/i2c0/scl_sp_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_SP_CONF")
-            .field(
-                "scl_rst_slv_en",
-                &format_args!("{}", self.scl_rst_slv_en().bit()),
-            )
-            .field(
-                "scl_rst_slv_num",
-                &format_args!("{}", self.scl_rst_slv_num().bits()),
-            )
-            .field("scl_pd_en", &format_args!("{}", self.scl_pd_en().bit()))
-            .field("sda_pd_en", &format_args!("{}", self.sda_pd_en().bit()))
+            .field("scl_rst_slv_en", &self.scl_rst_slv_en())
+            .field("scl_rst_slv_num", &self.scl_rst_slv_num())
+            .field("scl_pd_en", &self.scl_pd_en())
+            .field("sda_pd_en", &self.sda_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_SP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_scl_rst_slv_en"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/scl_st_time_out.rs b/esp32c3/src/i2c0/scl_st_time_out.rs
index 6d8590888d..27b0b9ed29 100644
--- a/esp32c3/src/i2c0/scl_st_time_out.rs
+++ b/esp32c3/src/i2c0/scl_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_ST_TIME_OUT")
-            .field(
-                "scl_st_to_i2c",
-                &format_args!("{}", self.scl_st_to_i2c().bits()),
-            )
+            .field("scl_st_to_i2c", &self.scl_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_scl_st_to_regno more than 23"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/scl_start_hold.rs b/esp32c3/src/i2c0/scl_start_hold.rs
index 7a067037f2..14eafb50fc 100644
--- a/esp32c3/src/i2c0/scl_start_hold.rs
+++ b/esp32c3/src/i2c0/scl_start_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - reg_scl_start_hold_time"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/scl_stop_hold.rs b/esp32c3/src/i2c0/scl_stop_hold.rs
index fd60767d27..41fb57efe8 100644
--- a/esp32c3/src/i2c0/scl_stop_hold.rs
+++ b/esp32c3/src/i2c0/scl_stop_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - reg_scl_stop_hold_time"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/scl_stop_setup.rs b/esp32c3/src/i2c0/scl_stop_setup.rs
index bb7f5831cf..dd9b33d6d8 100644
--- a/esp32c3/src/i2c0/scl_stop_setup.rs
+++ b/esp32c3/src/i2c0/scl_stop_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - reg_scl_stop_setup_time"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/scl_stretch_conf.rs b/esp32c3/src/i2c0/scl_stretch_conf.rs
index f8b4e1cfa8..d04a59d775 100644
--- a/esp32c3/src/i2c0/scl_stretch_conf.rs
+++ b/esp32c3/src/i2c0/scl_stretch_conf.rs
@@ -46,31 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STRETCH_CONF")
-            .field(
-                "stretch_protect_num",
-                &format_args!("{}", self.stretch_protect_num().bits()),
-            )
-            .field(
-                "slave_scl_stretch_en",
-                &format_args!("{}", self.slave_scl_stretch_en().bit()),
-            )
-            .field(
-                "slave_byte_ack_ctl_en",
-                &format_args!("{}", self.slave_byte_ack_ctl_en().bit()),
-            )
-            .field(
-                "slave_byte_ack_lvl",
-                &format_args!("{}", self.slave_byte_ack_lvl().bit()),
-            )
+            .field("stretch_protect_num", &self.stretch_protect_num())
+            .field("slave_scl_stretch_en", &self.slave_scl_stretch_en())
+            .field("slave_byte_ack_ctl_en", &self.slave_byte_ack_ctl_en())
+            .field("slave_byte_ack_lvl", &self.slave_byte_ack_lvl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STRETCH_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - reg_stretch_protect_num"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/sda_hold.rs b/esp32c3/src/i2c0/sda_hold.rs
index e8064f8585..445c86d4a0 100644
--- a/esp32c3/src/i2c0/sda_hold.rs
+++ b/esp32c3/src/i2c0/sda_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - reg_sda_hold_time"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/sda_sample.rs b/esp32c3/src/i2c0/sda_sample.rs
index 0efb0284e5..ab7a5dc6ce 100644
--- a/esp32c3/src/i2c0/sda_sample.rs
+++ b/esp32c3/src/i2c0/sda_sample.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_SAMPLE")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - reg_sda_sample_time"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/slave_addr.rs b/esp32c3/src/i2c0/slave_addr.rs
index a44a8b5b44..a098198bd8 100644
--- a/esp32c3/src/i2c0/slave_addr.rs
+++ b/esp32c3/src/i2c0/slave_addr.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE_ADDR")
-            .field("slave_addr", &format_args!("{}", self.slave_addr().bits()))
-            .field(
-                "addr_10bit_en",
-                &format_args!("{}", self.addr_10bit_en().bit()),
-            )
+            .field("slave_addr", &self.slave_addr())
+            .field("addr_10bit_en", &self.addr_10bit_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - reg_slave_addr"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/sr.rs b/esp32c3/src/i2c0/sr.rs
index f682a2ba53..5582def4dd 100644
--- a/esp32c3/src/i2c0/sr.rs
+++ b/esp32c3/src/i2c0/sr.rs
@@ -76,37 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR")
-            .field("resp_rec", &format_args!("{}", self.resp_rec().bit()))
-            .field("slave_rw", &format_args!("{}", self.slave_rw().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field(
-                "slave_addressed",
-                &format_args!("{}", self.slave_addressed().bit()),
-            )
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field(
-                "stretch_cause",
-                &format_args!("{}", self.stretch_cause().bits()),
-            )
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field(
-                "scl_main_state_last",
-                &format_args!("{}", self.scl_main_state_last().bits()),
-            )
-            .field(
-                "scl_state_last",
-                &format_args!("{}", self.scl_state_last().bits()),
-            )
+            .field("resp_rec", &self.resp_rec())
+            .field("slave_rw", &self.slave_rw())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("slave_addressed", &self.slave_addressed())
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("stretch_cause", &self.stretch_cause())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("scl_main_state_last", &self.scl_main_state_last())
+            .field("scl_state_last", &self.scl_state_last())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C_SR_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SR_SPEC;
 impl crate::RegisterSpec for SR_SPEC {
diff --git a/esp32c3/src/i2c0/to.rs b/esp32c3/src/i2c0/to.rs
index 19326e00ed..2201ffd7c8 100644
--- a/esp32c3/src/i2c0/to.rs
+++ b/esp32c3/src/i2c0/to.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO")
-            .field(
-                "time_out_value",
-                &format_args!("{}", self.time_out_value().bits()),
-            )
-            .field("time_out_en", &format_args!("{}", self.time_out_en().bit()))
+            .field("time_out_value", &self.time_out_value())
+            .field("time_out_en", &self.time_out_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_time_out_value"]
     #[inline(always)]
diff --git a/esp32c3/src/i2c0/txfifo_start_addr.rs b/esp32c3/src/i2c0/txfifo_start_addr.rs
index 906361a42a..d5ad567a4e 100644
--- a/esp32c3/src/i2c0/txfifo_start_addr.rs
+++ b/esp32c3/src/i2c0/txfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXFIFO_START_ADDR")
-            .field(
-                "txfifo_start_addr",
-                &format_args!("{}", self.txfifo_start_addr().bits()),
-            )
+            .field("txfifo_start_addr", &self.txfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C_TXFIFO_START_ADDR_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for TXFIFO_START_ADDR_SPEC {
diff --git a/esp32c3/src/i2s0/conf_sigle_data.rs b/esp32c3/src/i2s0/conf_sigle_data.rs
index f979345988..3c75f59255 100644
--- a/esp32c3/src/i2s0/conf_sigle_data.rs
+++ b/esp32c3/src/i2s0/conf_sigle_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_SIGLE_DATA")
-            .field(
-                "single_data",
-                &format_args!("{}", self.single_data().bits()),
-            )
+            .field("single_data", &self.single_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SIGLE_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The configured constant channel data to be sent out."]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/date.rs b/esp32c3/src/i2s0/date.rs
index 4a178d983f..8ebb9e1b35 100644
--- a/esp32c3/src/i2s0/date.rs
+++ b/esp32c3/src/i2s0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/i2s0/int_ena.rs b/esp32c3/src/i2s0/int_ena.rs
index ffbc92bacc..0a538b90e5 100644
--- a/esp32c3/src/i2s0/int_ena.rs
+++ b/esp32c3/src/i2s0/int_ena.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/int_raw.rs b/esp32c3/src/i2s0/int_raw.rs
index 7ec2d42cfd..e69602c0be 100644
--- a/esp32c3/src/i2s0/int_raw.rs
+++ b/esp32c3/src/i2s0/int_raw.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32c3/src/i2s0/int_st.rs b/esp32c3/src/i2s0/int_st.rs
index 5eac7b9c9d..ddf72a352e 100644
--- a/esp32c3/src/i2s0/int_st.rs
+++ b/esp32c3/src/i2s0/int_st.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c3/src/i2s0/lc_hung_conf.rs b/esp32c3/src/i2s0/lc_hung_conf.rs
index 060b1cdb60..71f0c84fa7 100644
--- a/esp32c3/src/i2s0/lc_hung_conf.rs
+++ b/esp32c3/src/i2s0/lc_hung_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_HUNG_CONF")
-            .field(
-                "lc_fifo_timeout",
-                &format_args!("{}", self.lc_fifo_timeout().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_shift",
-                &format_args!("{}", self.lc_fifo_timeout_shift().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_ena",
-                &format_args!("{}", self.lc_fifo_timeout_ena().bit()),
-            )
+            .field("lc_fifo_timeout", &self.lc_fifo_timeout())
+            .field("lc_fifo_timeout_shift", &self.lc_fifo_timeout_shift())
+            .field("lc_fifo_timeout_ena", &self.lc_fifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/rx_clkm_conf.rs b/esp32c3/src/i2s0/rx_clkm_conf.rs
index 79ff9b2470..5bbb7a360a 100644
--- a/esp32c3/src/i2s0/rx_clkm_conf.rs
+++ b/esp32c3/src/i2s0/rx_clkm_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CLKM_CONF")
-            .field(
-                "rx_clkm_div_num",
-                &format_args!("{}", self.rx_clkm_div_num().bits()),
-            )
-            .field(
-                "rx_clk_active",
-                &format_args!("{}", self.rx_clk_active().bit()),
-            )
-            .field("rx_clk_sel", &format_args!("{}", self.rx_clk_sel().bits()))
-            .field("mclk_sel", &format_args!("{}", self.mclk_sel().bit()))
+            .field("rx_clkm_div_num", &self.rx_clkm_div_num())
+            .field("rx_clk_active", &self.rx_clk_active())
+            .field("rx_clk_sel", &self.rx_clk_sel())
+            .field("mclk_sel", &self.mclk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral I2S clock divider value"]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/rx_clkm_div_conf.rs b/esp32c3/src/i2s0/rx_clkm_div_conf.rs
index 9dc32721ed..d4f0ee53bc 100644
--- a/esp32c3/src/i2s0/rx_clkm_div_conf.rs
+++ b/esp32c3/src/i2s0/rx_clkm_div_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CLKM_DIV_CONF")
-            .field(
-                "rx_clkm_div_z",
-                &format_args!("{}", self.rx_clkm_div_z().bits()),
-            )
-            .field(
-                "rx_clkm_div_y",
-                &format_args!("{}", self.rx_clkm_div_y().bits()),
-            )
-            .field(
-                "rx_clkm_div_x",
-                &format_args!("{}", self.rx_clkm_div_x().bits()),
-            )
-            .field(
-                "rx_clkm_div_yn1",
-                &format_args!("{}", self.rx_clkm_div_yn1().bit()),
-            )
+            .field("rx_clkm_div_z", &self.rx_clkm_div_z())
+            .field("rx_clkm_div_y", &self.rx_clkm_div_y())
+            .field("rx_clkm_div_x", &self.rx_clkm_div_x())
+            .field("rx_clkm_div_yn1", &self.rx_clkm_div_yn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CLKM_DIV_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/rx_conf.rs b/esp32c3/src/i2s0/rx_conf.rs
index 87a73e205b..bc22e600af 100644
--- a/esp32c3/src/i2s0/rx_conf.rs
+++ b/esp32c3/src/i2s0/rx_conf.rs
@@ -147,60 +147,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CONF")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field(
-                "rx_slave_mod",
-                &format_args!("{}", self.rx_slave_mod().bit()),
-            )
-            .field("rx_mono", &format_args!("{}", self.rx_mono().bit()))
-            .field(
-                "rx_big_endian",
-                &format_args!("{}", self.rx_big_endian().bit()),
-            )
-            .field("rx_update", &format_args!("{}", self.rx_update().bit()))
-            .field(
-                "rx_mono_fst_vld",
-                &format_args!("{}", self.rx_mono_fst_vld().bit()),
-            )
-            .field(
-                "rx_pcm_conf",
-                &format_args!("{}", self.rx_pcm_conf().bits()),
-            )
-            .field(
-                "rx_pcm_bypass",
-                &format_args!("{}", self.rx_pcm_bypass().bit()),
-            )
-            .field(
-                "rx_stop_mode",
-                &format_args!("{}", self.rx_stop_mode().bits()),
-            )
-            .field(
-                "rx_left_align",
-                &format_args!("{}", self.rx_left_align().bit()),
-            )
-            .field(
-                "rx_24_fill_en",
-                &format_args!("{}", self.rx_24_fill_en().bit()),
-            )
-            .field(
-                "rx_ws_idle_pol",
-                &format_args!("{}", self.rx_ws_idle_pol().bit()),
-            )
-            .field(
-                "rx_bit_order",
-                &format_args!("{}", self.rx_bit_order().bit()),
-            )
-            .field("rx_tdm_en", &format_args!("{}", self.rx_tdm_en().bit()))
-            .field("rx_pdm_en", &format_args!("{}", self.rx_pdm_en().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("rx_slave_mod", &self.rx_slave_mod())
+            .field("rx_mono", &self.rx_mono())
+            .field("rx_big_endian", &self.rx_big_endian())
+            .field("rx_update", &self.rx_update())
+            .field("rx_mono_fst_vld", &self.rx_mono_fst_vld())
+            .field("rx_pcm_conf", &self.rx_pcm_conf())
+            .field("rx_pcm_bypass", &self.rx_pcm_bypass())
+            .field("rx_stop_mode", &self.rx_stop_mode())
+            .field("rx_left_align", &self.rx_left_align())
+            .field("rx_24_fill_en", &self.rx_24_fill_en())
+            .field("rx_ws_idle_pol", &self.rx_ws_idle_pol())
+            .field("rx_bit_order", &self.rx_bit_order())
+            .field("rx_tdm_en", &self.rx_tdm_en())
+            .field("rx_pdm_en", &self.rx_pdm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset receiver"]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/rx_conf1.rs b/esp32c3/src/i2s0/rx_conf1.rs
index 24c13494fb..31fa7a1f88 100644
--- a/esp32c3/src/i2s0/rx_conf1.rs
+++ b/esp32c3/src/i2s0/rx_conf1.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CONF1")
-            .field(
-                "rx_tdm_ws_width",
-                &format_args!("{}", self.rx_tdm_ws_width().bits()),
-            )
-            .field(
-                "rx_bck_div_num",
-                &format_args!("{}", self.rx_bck_div_num().bits()),
-            )
-            .field(
-                "rx_bits_mod",
-                &format_args!("{}", self.rx_bits_mod().bits()),
-            )
-            .field(
-                "rx_half_sample_bits",
-                &format_args!("{}", self.rx_half_sample_bits().bits()),
-            )
-            .field(
-                "rx_tdm_chan_bits",
-                &format_args!("{}", self.rx_tdm_chan_bits().bits()),
-            )
-            .field(
-                "rx_msb_shift",
-                &format_args!("{}", self.rx_msb_shift().bit()),
-            )
+            .field("rx_tdm_ws_width", &self.rx_tdm_ws_width())
+            .field("rx_bck_div_num", &self.rx_bck_div_num())
+            .field("rx_bits_mod", &self.rx_bits_mod())
+            .field("rx_half_sample_bits", &self.rx_half_sample_bits())
+            .field("rx_tdm_chan_bits", &self.rx_tdm_chan_bits())
+            .field("rx_msb_shift", &self.rx_msb_shift())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/rx_tdm_ctrl.rs b/esp32c3/src/i2s0/rx_tdm_ctrl.rs
index fe01f97aeb..0d18f522f2 100644
--- a/esp32c3/src/i2s0/rx_tdm_ctrl.rs
+++ b/esp32c3/src/i2s0/rx_tdm_ctrl.rs
@@ -161,83 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_TDM_CTRL")
-            .field(
-                "rx_tdm_pdm_chan0_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan0_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan1_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan1_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan2_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan2_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan3_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan3_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan4_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan4_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan5_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan5_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan6_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan6_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan7_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan7_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan8_en",
-                &format_args!("{}", self.rx_tdm_chan8_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan9_en",
-                &format_args!("{}", self.rx_tdm_chan9_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan10_en",
-                &format_args!("{}", self.rx_tdm_chan10_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan11_en",
-                &format_args!("{}", self.rx_tdm_chan11_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan12_en",
-                &format_args!("{}", self.rx_tdm_chan12_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan13_en",
-                &format_args!("{}", self.rx_tdm_chan13_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan14_en",
-                &format_args!("{}", self.rx_tdm_chan14_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan15_en",
-                &format_args!("{}", self.rx_tdm_chan15_en().bit()),
-            )
-            .field(
-                "rx_tdm_tot_chan_num",
-                &format_args!("{}", self.rx_tdm_tot_chan_num().bits()),
-            )
+            .field("rx_tdm_pdm_chan0_en", &self.rx_tdm_pdm_chan0_en())
+            .field("rx_tdm_pdm_chan1_en", &self.rx_tdm_pdm_chan1_en())
+            .field("rx_tdm_pdm_chan2_en", &self.rx_tdm_pdm_chan2_en())
+            .field("rx_tdm_pdm_chan3_en", &self.rx_tdm_pdm_chan3_en())
+            .field("rx_tdm_pdm_chan4_en", &self.rx_tdm_pdm_chan4_en())
+            .field("rx_tdm_pdm_chan5_en", &self.rx_tdm_pdm_chan5_en())
+            .field("rx_tdm_pdm_chan6_en", &self.rx_tdm_pdm_chan6_en())
+            .field("rx_tdm_pdm_chan7_en", &self.rx_tdm_pdm_chan7_en())
+            .field("rx_tdm_chan8_en", &self.rx_tdm_chan8_en())
+            .field("rx_tdm_chan9_en", &self.rx_tdm_chan9_en())
+            .field("rx_tdm_chan10_en", &self.rx_tdm_chan10_en())
+            .field("rx_tdm_chan11_en", &self.rx_tdm_chan11_en())
+            .field("rx_tdm_chan12_en", &self.rx_tdm_chan12_en())
+            .field("rx_tdm_chan13_en", &self.rx_tdm_chan13_en())
+            .field("rx_tdm_chan14_en", &self.rx_tdm_chan14_en())
+            .field("rx_tdm_chan15_en", &self.rx_tdm_chan15_en())
+            .field("rx_tdm_tot_chan_num", &self.rx_tdm_tot_chan_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_TDM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/rx_timing.rs b/esp32c3/src/i2s0/rx_timing.rs
index 66daf81e08..fe227b5840 100644
--- a/esp32c3/src/i2s0/rx_timing.rs
+++ b/esp32c3/src/i2s0/rx_timing.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_TIMING")
-            .field(
-                "rx_sd_in_dm",
-                &format_args!("{}", self.rx_sd_in_dm().bits()),
-            )
-            .field(
-                "rx_ws_out_dm",
-                &format_args!("{}", self.rx_ws_out_dm().bits()),
-            )
-            .field(
-                "rx_bck_out_dm",
-                &format_args!("{}", self.rx_bck_out_dm().bits()),
-            )
-            .field(
-                "rx_ws_in_dm",
-                &format_args!("{}", self.rx_ws_in_dm().bits()),
-            )
-            .field(
-                "rx_bck_in_dm",
-                &format_args!("{}", self.rx_bck_in_dm().bits()),
-            )
+            .field("rx_sd_in_dm", &self.rx_sd_in_dm())
+            .field("rx_ws_out_dm", &self.rx_ws_out_dm())
+            .field("rx_bck_out_dm", &self.rx_bck_out_dm())
+            .field("rx_ws_in_dm", &self.rx_ws_in_dm())
+            .field("rx_bck_in_dm", &self.rx_bck_in_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/rxeof_num.rs b/esp32c3/src/i2s0/rxeof_num.rs
index 06f6d22ff0..b9674d5891 100644
--- a/esp32c3/src/i2s0/rxeof_num.rs
+++ b/esp32c3/src/i2s0/rxeof_num.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXEOF_NUM")
-            .field("rx_eof_num", &format_args!("{}", self.rx_eof_num().bits()))
+            .field("rx_eof_num", &self.rx_eof_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXEOF_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/state.rs b/esp32c3/src/i2s0/state.rs
index 7988d4067c..d16247a40d 100644
--- a/esp32c3/src/i2s0/state.rs
+++ b/esp32c3/src/i2s0/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("tx_idle", &format_args!("{}", self.tx_idle().bit()))
+            .field("tx_idle", &self.tx_idle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S TX status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32c3/src/i2s0/tx_clkm_conf.rs b/esp32c3/src/i2s0/tx_clkm_conf.rs
index ef82d04116..2584244722 100644
--- a/esp32c3/src/i2s0/tx_clkm_conf.rs
+++ b/esp32c3/src/i2s0/tx_clkm_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CLKM_CONF")
-            .field(
-                "tx_clkm_div_num",
-                &format_args!("{}", self.tx_clkm_div_num().bits()),
-            )
-            .field(
-                "tx_clk_active",
-                &format_args!("{}", self.tx_clk_active().bit()),
-            )
-            .field("tx_clk_sel", &format_args!("{}", self.tx_clk_sel().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("tx_clkm_div_num", &self.tx_clkm_div_num())
+            .field("tx_clk_active", &self.tx_clk_active())
+            .field("tx_clk_sel", &self.tx_clk_sel())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b &lt;= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/tx_clkm_div_conf.rs b/esp32c3/src/i2s0/tx_clkm_div_conf.rs
index eb02e39a99..8421d21999 100644
--- a/esp32c3/src/i2s0/tx_clkm_div_conf.rs
+++ b/esp32c3/src/i2s0/tx_clkm_div_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CLKM_DIV_CONF")
-            .field(
-                "tx_clkm_div_z",
-                &format_args!("{}", self.tx_clkm_div_z().bits()),
-            )
-            .field(
-                "tx_clkm_div_y",
-                &format_args!("{}", self.tx_clkm_div_y().bits()),
-            )
-            .field(
-                "tx_clkm_div_x",
-                &format_args!("{}", self.tx_clkm_div_x().bits()),
-            )
-            .field(
-                "tx_clkm_div_yn1",
-                &format_args!("{}", self.tx_clkm_div_yn1().bit()),
-            )
+            .field("tx_clkm_div_z", &self.tx_clkm_div_z())
+            .field("tx_clkm_div_y", &self.tx_clkm_div_y())
+            .field("tx_clkm_div_x", &self.tx_clkm_div_x())
+            .field("tx_clkm_div_yn1", &self.tx_clkm_div_yn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CLKM_DIV_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/tx_conf.rs b/esp32c3/src/i2s0/tx_conf.rs
index b10d6ccc62..83a890333d 100644
--- a/esp32c3/src/i2s0/tx_conf.rs
+++ b/esp32c3/src/i2s0/tx_conf.rs
@@ -174,69 +174,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CONF")
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field(
-                "tx_slave_mod",
-                &format_args!("{}", self.tx_slave_mod().bit()),
-            )
-            .field("tx_mono", &format_args!("{}", self.tx_mono().bit()))
-            .field(
-                "tx_chan_equal",
-                &format_args!("{}", self.tx_chan_equal().bit()),
-            )
-            .field(
-                "tx_big_endian",
-                &format_args!("{}", self.tx_big_endian().bit()),
-            )
-            .field("tx_update", &format_args!("{}", self.tx_update().bit()))
-            .field(
-                "tx_mono_fst_vld",
-                &format_args!("{}", self.tx_mono_fst_vld().bit()),
-            )
-            .field(
-                "tx_pcm_conf",
-                &format_args!("{}", self.tx_pcm_conf().bits()),
-            )
-            .field(
-                "tx_pcm_bypass",
-                &format_args!("{}", self.tx_pcm_bypass().bit()),
-            )
-            .field("tx_stop_en", &format_args!("{}", self.tx_stop_en().bit()))
-            .field(
-                "tx_left_align",
-                &format_args!("{}", self.tx_left_align().bit()),
-            )
-            .field(
-                "tx_24_fill_en",
-                &format_args!("{}", self.tx_24_fill_en().bit()),
-            )
-            .field(
-                "tx_ws_idle_pol",
-                &format_args!("{}", self.tx_ws_idle_pol().bit()),
-            )
-            .field(
-                "tx_bit_order",
-                &format_args!("{}", self.tx_bit_order().bit()),
-            )
-            .field("tx_tdm_en", &format_args!("{}", self.tx_tdm_en().bit()))
-            .field("tx_pdm_en", &format_args!("{}", self.tx_pdm_en().bit()))
-            .field(
-                "tx_chan_mod",
-                &format_args!("{}", self.tx_chan_mod().bits()),
-            )
-            .field(
-                "sig_loopback",
-                &format_args!("{}", self.sig_loopback().bit()),
-            )
+            .field("tx_start", &self.tx_start())
+            .field("tx_slave_mod", &self.tx_slave_mod())
+            .field("tx_mono", &self.tx_mono())
+            .field("tx_chan_equal", &self.tx_chan_equal())
+            .field("tx_big_endian", &self.tx_big_endian())
+            .field("tx_update", &self.tx_update())
+            .field("tx_mono_fst_vld", &self.tx_mono_fst_vld())
+            .field("tx_pcm_conf", &self.tx_pcm_conf())
+            .field("tx_pcm_bypass", &self.tx_pcm_bypass())
+            .field("tx_stop_en", &self.tx_stop_en())
+            .field("tx_left_align", &self.tx_left_align())
+            .field("tx_24_fill_en", &self.tx_24_fill_en())
+            .field("tx_ws_idle_pol", &self.tx_ws_idle_pol())
+            .field("tx_bit_order", &self.tx_bit_order())
+            .field("tx_tdm_en", &self.tx_tdm_en())
+            .field("tx_pdm_en", &self.tx_pdm_en())
+            .field("tx_chan_mod", &self.tx_chan_mod())
+            .field("sig_loopback", &self.sig_loopback())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset transmitter"]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/tx_conf1.rs b/esp32c3/src/i2s0/tx_conf1.rs
index 736705832c..8d70da3870 100644
--- a/esp32c3/src/i2s0/tx_conf1.rs
+++ b/esp32c3/src/i2s0/tx_conf1.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CONF1")
-            .field(
-                "tx_tdm_ws_width",
-                &format_args!("{}", self.tx_tdm_ws_width().bits()),
-            )
-            .field(
-                "tx_bck_div_num",
-                &format_args!("{}", self.tx_bck_div_num().bits()),
-            )
-            .field(
-                "tx_bits_mod",
-                &format_args!("{}", self.tx_bits_mod().bits()),
-            )
-            .field(
-                "tx_half_sample_bits",
-                &format_args!("{}", self.tx_half_sample_bits().bits()),
-            )
-            .field(
-                "tx_tdm_chan_bits",
-                &format_args!("{}", self.tx_tdm_chan_bits().bits()),
-            )
-            .field(
-                "tx_msb_shift",
-                &format_args!("{}", self.tx_msb_shift().bit()),
-            )
-            .field(
-                "tx_bck_no_dly",
-                &format_args!("{}", self.tx_bck_no_dly().bit()),
-            )
+            .field("tx_tdm_ws_width", &self.tx_tdm_ws_width())
+            .field("tx_bck_div_num", &self.tx_bck_div_num())
+            .field("tx_bits_mod", &self.tx_bits_mod())
+            .field("tx_half_sample_bits", &self.tx_half_sample_bits())
+            .field("tx_tdm_chan_bits", &self.tx_tdm_chan_bits())
+            .field("tx_msb_shift", &self.tx_msb_shift())
+            .field("tx_bck_no_dly", &self.tx_bck_no_dly())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/tx_pcm2pdm_conf.rs b/esp32c3/src/i2s0/tx_pcm2pdm_conf.rs
index f361f43fa5..833a737465 100644
--- a/esp32c3/src/i2s0/tx_pcm2pdm_conf.rs
+++ b/esp32c3/src/i2s0/tx_pcm2pdm_conf.rs
@@ -116,63 +116,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_PCM2PDM_CONF")
-            .field(
-                "tx_pdm_hp_bypass",
-                &format_args!("{}", self.tx_pdm_hp_bypass().bit()),
-            )
-            .field(
-                "tx_pdm_sinc_osr2",
-                &format_args!("{}", self.tx_pdm_sinc_osr2().bits()),
-            )
-            .field(
-                "tx_pdm_prescale",
-                &format_args!("{}", self.tx_pdm_prescale().bits()),
-            )
-            .field(
-                "tx_pdm_hp_in_shift",
-                &format_args!("{}", self.tx_pdm_hp_in_shift().bits()),
-            )
-            .field(
-                "tx_pdm_lp_in_shift",
-                &format_args!("{}", self.tx_pdm_lp_in_shift().bits()),
-            )
-            .field(
-                "tx_pdm_sinc_in_shift",
-                &format_args!("{}", self.tx_pdm_sinc_in_shift().bits()),
-            )
+            .field("tx_pdm_hp_bypass", &self.tx_pdm_hp_bypass())
+            .field("tx_pdm_sinc_osr2", &self.tx_pdm_sinc_osr2())
+            .field("tx_pdm_prescale", &self.tx_pdm_prescale())
+            .field("tx_pdm_hp_in_shift", &self.tx_pdm_hp_in_shift())
+            .field("tx_pdm_lp_in_shift", &self.tx_pdm_lp_in_shift())
+            .field("tx_pdm_sinc_in_shift", &self.tx_pdm_sinc_in_shift())
             .field(
                 "tx_pdm_sigmadelta_in_shift",
-                &format_args!("{}", self.tx_pdm_sigmadelta_in_shift().bits()),
+                &self.tx_pdm_sigmadelta_in_shift(),
             )
             .field(
                 "tx_pdm_sigmadelta_dither2",
-                &format_args!("{}", self.tx_pdm_sigmadelta_dither2().bit()),
-            )
-            .field(
-                "tx_pdm_sigmadelta_dither",
-                &format_args!("{}", self.tx_pdm_sigmadelta_dither().bit()),
-            )
-            .field(
-                "tx_pdm_dac_2out_en",
-                &format_args!("{}", self.tx_pdm_dac_2out_en().bit()),
-            )
-            .field(
-                "tx_pdm_dac_mode_en",
-                &format_args!("{}", self.tx_pdm_dac_mode_en().bit()),
-            )
-            .field(
-                "pcm2pdm_conv_en",
-                &format_args!("{}", self.pcm2pdm_conv_en().bit()),
+                &self.tx_pdm_sigmadelta_dither2(),
             )
+            .field("tx_pdm_sigmadelta_dither", &self.tx_pdm_sigmadelta_dither())
+            .field("tx_pdm_dac_2out_en", &self.tx_pdm_dac_2out_en())
+            .field("tx_pdm_dac_mode_en", &self.tx_pdm_dac_mode_en())
+            .field("pcm2pdm_conv_en", &self.pcm2pdm_conv_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_PCM2PDM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - I2S TX PDM bypass hp filter or not. The option has been removed."]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/tx_pcm2pdm_conf1.rs b/esp32c3/src/i2s0/tx_pcm2pdm_conf1.rs
index dfcd334df0..48c460dc25 100644
--- a/esp32c3/src/i2s0/tx_pcm2pdm_conf1.rs
+++ b/esp32c3/src/i2s0/tx_pcm2pdm_conf1.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_PCM2PDM_CONF1")
-            .field("tx_pdm_fp", &format_args!("{}", self.tx_pdm_fp().bits()))
-            .field("tx_pdm_fs", &format_args!("{}", self.tx_pdm_fs().bits()))
-            .field(
-                "tx_iir_hp_mult12_5",
-                &format_args!("{}", self.tx_iir_hp_mult12_5().bits()),
-            )
-            .field(
-                "tx_iir_hp_mult12_0",
-                &format_args!("{}", self.tx_iir_hp_mult12_0().bits()),
-            )
+            .field("tx_pdm_fp", &self.tx_pdm_fp())
+            .field("tx_pdm_fs", &self.tx_pdm_fs())
+            .field("tx_iir_hp_mult12_5", &self.tx_iir_hp_mult12_5())
+            .field("tx_iir_hp_mult12_0", &self.tx_iir_hp_mult12_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_PCM2PDM_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - I2S TX PDM Fp"]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/tx_tdm_ctrl.rs b/esp32c3/src/i2s0/tx_tdm_ctrl.rs
index a6511fa2f9..8b06e96c6c 100644
--- a/esp32c3/src/i2s0/tx_tdm_ctrl.rs
+++ b/esp32c3/src/i2s0/tx_tdm_ctrl.rs
@@ -170,87 +170,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_TDM_CTRL")
-            .field(
-                "tx_tdm_chan0_en",
-                &format_args!("{}", self.tx_tdm_chan0_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan1_en",
-                &format_args!("{}", self.tx_tdm_chan1_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan2_en",
-                &format_args!("{}", self.tx_tdm_chan2_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan3_en",
-                &format_args!("{}", self.tx_tdm_chan3_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan4_en",
-                &format_args!("{}", self.tx_tdm_chan4_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan5_en",
-                &format_args!("{}", self.tx_tdm_chan5_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan6_en",
-                &format_args!("{}", self.tx_tdm_chan6_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan7_en",
-                &format_args!("{}", self.tx_tdm_chan7_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan8_en",
-                &format_args!("{}", self.tx_tdm_chan8_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan9_en",
-                &format_args!("{}", self.tx_tdm_chan9_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan10_en",
-                &format_args!("{}", self.tx_tdm_chan10_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan11_en",
-                &format_args!("{}", self.tx_tdm_chan11_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan12_en",
-                &format_args!("{}", self.tx_tdm_chan12_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan13_en",
-                &format_args!("{}", self.tx_tdm_chan13_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan14_en",
-                &format_args!("{}", self.tx_tdm_chan14_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan15_en",
-                &format_args!("{}", self.tx_tdm_chan15_en().bit()),
-            )
-            .field(
-                "tx_tdm_tot_chan_num",
-                &format_args!("{}", self.tx_tdm_tot_chan_num().bits()),
-            )
-            .field(
-                "tx_tdm_skip_msk_en",
-                &format_args!("{}", self.tx_tdm_skip_msk_en().bit()),
-            )
+            .field("tx_tdm_chan0_en", &self.tx_tdm_chan0_en())
+            .field("tx_tdm_chan1_en", &self.tx_tdm_chan1_en())
+            .field("tx_tdm_chan2_en", &self.tx_tdm_chan2_en())
+            .field("tx_tdm_chan3_en", &self.tx_tdm_chan3_en())
+            .field("tx_tdm_chan4_en", &self.tx_tdm_chan4_en())
+            .field("tx_tdm_chan5_en", &self.tx_tdm_chan5_en())
+            .field("tx_tdm_chan6_en", &self.tx_tdm_chan6_en())
+            .field("tx_tdm_chan7_en", &self.tx_tdm_chan7_en())
+            .field("tx_tdm_chan8_en", &self.tx_tdm_chan8_en())
+            .field("tx_tdm_chan9_en", &self.tx_tdm_chan9_en())
+            .field("tx_tdm_chan10_en", &self.tx_tdm_chan10_en())
+            .field("tx_tdm_chan11_en", &self.tx_tdm_chan11_en())
+            .field("tx_tdm_chan12_en", &self.tx_tdm_chan12_en())
+            .field("tx_tdm_chan13_en", &self.tx_tdm_chan13_en())
+            .field("tx_tdm_chan14_en", &self.tx_tdm_chan14_en())
+            .field("tx_tdm_chan15_en", &self.tx_tdm_chan15_en())
+            .field("tx_tdm_tot_chan_num", &self.tx_tdm_tot_chan_num())
+            .field("tx_tdm_skip_msk_en", &self.tx_tdm_skip_msk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_TDM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
diff --git a/esp32c3/src/i2s0/tx_timing.rs b/esp32c3/src/i2s0/tx_timing.rs
index 90d44db432..550930d1b6 100644
--- a/esp32c3/src/i2s0/tx_timing.rs
+++ b/esp32c3/src/i2s0/tx_timing.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_TIMING")
-            .field(
-                "tx_sd_out_dm",
-                &format_args!("{}", self.tx_sd_out_dm().bits()),
-            )
-            .field(
-                "tx_sd1_out_dm",
-                &format_args!("{}", self.tx_sd1_out_dm().bits()),
-            )
-            .field(
-                "tx_ws_out_dm",
-                &format_args!("{}", self.tx_ws_out_dm().bits()),
-            )
-            .field(
-                "tx_bck_out_dm",
-                &format_args!("{}", self.tx_bck_out_dm().bits()),
-            )
-            .field(
-                "tx_ws_in_dm",
-                &format_args!("{}", self.tx_ws_in_dm().bits()),
-            )
-            .field(
-                "tx_bck_in_dm",
-                &format_args!("{}", self.tx_bck_in_dm().bits()),
-            )
+            .field("tx_sd_out_dm", &self.tx_sd_out_dm())
+            .field("tx_sd1_out_dm", &self.tx_sd1_out_dm())
+            .field("tx_ws_out_dm", &self.tx_ws_out_dm())
+            .field("tx_bck_out_dm", &self.tx_bck_out_dm())
+            .field("tx_ws_in_dm", &self.tx_ws_in_dm())
+            .field("tx_bck_in_dm", &self.tx_bck_in_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/aes_int_map.rs b/esp32c3/src/interrupt_core0/aes_int_map.rs
index ac1c457d8e..d98e400908 100644
--- a/esp32c3/src/interrupt_core0/aes_int_map.rs
+++ b/esp32c3/src/interrupt_core0/aes_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AES_INT_MAP")
-            .field(
-                "aes_int_map",
-                &format_args!("{}", self.aes_int_map().bits()),
-            )
+            .field("aes_int_map", &self.aes_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AES_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_aes_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/apb_adc_int_map.rs b/esp32c3/src/interrupt_core0/apb_adc_int_map.rs
index e22aaab62f..1e794336f0 100644
--- a/esp32c3/src/interrupt_core0/apb_adc_int_map.rs
+++ b/esp32c3/src/interrupt_core0/apb_adc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_ADC_INT_MAP")
-            .field(
-                "apb_adc_int_map",
-                &format_args!("{}", self.apb_adc_int_map().bits()),
-            )
+            .field("apb_adc_int_map", &self.apb_adc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_ADC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_apb_adc_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/apb_ctrl_intr_map.rs b/esp32c3/src/interrupt_core0/apb_ctrl_intr_map.rs
index c96f6f9f95..4b6b34b3ab 100644
--- a/esp32c3/src/interrupt_core0/apb_ctrl_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/apb_ctrl_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_CTRL_INTR_MAP")
-            .field(
-                "apb_ctrl_intr_map",
-                &format_args!("{}", self.apb_ctrl_intr_map().bits()),
-            )
+            .field("apb_ctrl_intr_map", &self.apb_ctrl_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_CTRL_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_apb_ctrl_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/assist_debug_intr_map.rs b/esp32c3/src/interrupt_core0/assist_debug_intr_map.rs
index 48accca883..ae982311ff 100644
--- a/esp32c3/src/interrupt_core0/assist_debug_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/assist_debug_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ASSIST_DEBUG_INTR_MAP")
-            .field(
-                "assist_debug_intr_map",
-                &format_args!("{}", self.assist_debug_intr_map().bits()),
-            )
+            .field("assist_debug_intr_map", &self.assist_debug_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ASSIST_DEBUG_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_assist_debug_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/backup_pms_violate_intr_map.rs b/esp32c3/src/interrupt_core0/backup_pms_violate_intr_map.rs
index 3d5c70bc15..b4e201a87d 100644
--- a/esp32c3/src/interrupt_core0/backup_pms_violate_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/backup_pms_violate_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_PMS_VIOLATE_INTR_MAP")
             .field(
                 "backup_pms_violate_intr_map",
-                &format_args!("{}", self.backup_pms_violate_intr_map().bits()),
+                &self.backup_pms_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_PMS_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_backup_pms_violate_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/bb_int_map.rs b/esp32c3/src/interrupt_core0/bb_int_map.rs
index cc00809a8c..3e9826251e 100644
--- a/esp32c3/src/interrupt_core0/bb_int_map.rs
+++ b/esp32c3/src/interrupt_core0/bb_int_map.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BB_INT_MAP")
-            .field("bb_int_map", &format_args!("{}", self.bb_int_map().bits()))
+            .field("bb_int_map", &self.bb_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BB_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_bb_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/bt_bb_int_map.rs b/esp32c3/src/interrupt_core0/bt_bb_int_map.rs
index 975a301509..e2c9d715ef 100644
--- a/esp32c3/src/interrupt_core0/bt_bb_int_map.rs
+++ b/esp32c3/src/interrupt_core0/bt_bb_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_BB_INT_MAP")
-            .field(
-                "bt_bb_int_map",
-                &format_args!("{}", self.bt_bb_int_map().bits()),
-            )
+            .field("bt_bb_int_map", &self.bt_bb_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_BB_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_bt_bb_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/bt_bb_nmi_map.rs b/esp32c3/src/interrupt_core0/bt_bb_nmi_map.rs
index 3f583192e5..719dd53e66 100644
--- a/esp32c3/src/interrupt_core0/bt_bb_nmi_map.rs
+++ b/esp32c3/src/interrupt_core0/bt_bb_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_BB_NMI_MAP")
-            .field(
-                "bt_bb_nmi_map",
-                &format_args!("{}", self.bt_bb_nmi_map().bits()),
-            )
+            .field("bt_bb_nmi_map", &self.bt_bb_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_BB_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_bt_bb_nmi_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/bt_mac_int_map.rs b/esp32c3/src/interrupt_core0/bt_mac_int_map.rs
index d145972d5e..14f075cce0 100644
--- a/esp32c3/src/interrupt_core0/bt_mac_int_map.rs
+++ b/esp32c3/src/interrupt_core0/bt_mac_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_MAC_INT_MAP")
-            .field(
-                "bt_mac_int_map",
-                &format_args!("{}", self.bt_mac_int_map().bits()),
-            )
+            .field("bt_mac_int_map", &self.bt_mac_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_MAC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_bt_mac_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/cache_core0_acs_int_map.rs b/esp32c3/src/interrupt_core0/cache_core0_acs_int_map.rs
index 254dae04a4..7804ea37a3 100644
--- a/esp32c3/src/interrupt_core0/cache_core0_acs_int_map.rs
+++ b/esp32c3/src/interrupt_core0/cache_core0_acs_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_CORE0_ACS_INT_MAP")
-            .field(
-                "cache_core0_acs_int_map",
-                &format_args!("{}", self.cache_core0_acs_int_map().bits()),
-            )
+            .field("cache_core0_acs_int_map", &self.cache_core0_acs_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CORE0_ACS_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_cache_core0_acs_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/cache_ia_int_map.rs b/esp32c3/src/interrupt_core0/cache_ia_int_map.rs
index 0095e42fa1..ba6af8ed1b 100644
--- a/esp32c3/src/interrupt_core0/cache_ia_int_map.rs
+++ b/esp32c3/src/interrupt_core0/cache_ia_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_IA_INT_MAP")
-            .field(
-                "cache_ia_int_map",
-                &format_args!("{}", self.cache_ia_int_map().bits()),
-            )
+            .field("cache_ia_int_map", &self.cache_ia_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_IA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_cache_ia_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/can_int_map.rs b/esp32c3/src/interrupt_core0/can_int_map.rs
index 0614e1f7f9..ee78d38784 100644
--- a/esp32c3/src/interrupt_core0/can_int_map.rs
+++ b/esp32c3/src/interrupt_core0/can_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAN_INT_MAP")
-            .field(
-                "can_int_map",
-                &format_args!("{}", self.can_int_map().bits()),
-            )
+            .field("can_int_map", &self.can_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAN_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_can_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/clock_gate.rs b/esp32c3/src/interrupt_core0/clock_gate.rs
index 7e26761866..e653c941be 100644
--- a/esp32c3/src/interrupt_core0/clock_gate.rs
+++ b/esp32c3/src/interrupt_core0/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("reg_clk_en", &format_args!("{}", self.reg_clk_en().bit()))
+            .field("reg_clk_en", &self.reg_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_core0_reg_clk_en"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/core_0_dram0_pms_monitor_violate_intr_map.rs b/esp32c3/src/interrupt_core0/core_0_dram0_pms_monitor_violate_intr_map.rs
index edf73164e1..c1e15ed750 100644
--- a/esp32c3/src/interrupt_core0/core_0_dram0_pms_monitor_violate_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/core_0_dram0_pms_monitor_violate_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "core_0_dram0_pms_monitor_violate_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_0_dram0_pms_monitor_violate_intr_map().bits()
-                ),
+                &self.core_0_dram0_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_core_0_dram0_pms_monitor_violate_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/core_0_iram0_pms_monitor_violate_intr_map.rs b/esp32c3/src/interrupt_core0/core_0_iram0_pms_monitor_violate_intr_map.rs
index 43747e7a47..138b54cb8e 100644
--- a/esp32c3/src/interrupt_core0/core_0_iram0_pms_monitor_violate_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/core_0_iram0_pms_monitor_violate_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "core_0_iram0_pms_monitor_violate_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_0_iram0_pms_monitor_violate_intr_map().bits()
-                ),
+                &self.core_0_iram0_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_core_0_iram0_pms_monitor_violate_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/core_0_pif_pms_monitor_violate_intr_map.rs b/esp32c3/src/interrupt_core0/core_0_pif_pms_monitor_violate_intr_map.rs
index da42a3868d..103597a108 100644
--- a/esp32c3/src/interrupt_core0/core_0_pif_pms_monitor_violate_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/core_0_pif_pms_monitor_violate_intr_map.rs
@@ -21,17 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "core_0_pif_pms_monitor_violate_intr_map",
-                &format_args!("{}", self.core_0_pif_pms_monitor_violate_intr_map().bits()),
+                &self.core_0_pif_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_core_0_pif_pms_monitor_violate_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs b/esp32c3/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs
index 0e60fa3b2e..2a4f89654b 100644
--- a/esp32c3/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP")
             .field(
                 "core_0_pif_pms_monitor_violate_size_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_violate_size_intr_map().bits()
-                ),
+                &self.core_0_pif_pms_monitor_violate_size_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_core_0_pif_pms_monitor_violate_size_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/cpu_int_clear.rs b/esp32c3/src/interrupt_core0/cpu_int_clear.rs
index d221018ba3..7e237cbebd 100644
--- a/esp32c3/src/interrupt_core0/cpu_int_clear.rs
+++ b/esp32c3/src/interrupt_core0/cpu_int_clear.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_CLEAR")
-            .field(
-                "cpu_int_clear",
-                &format_args!("{}", self.cpu_int_clear().bits()),
-            )
+            .field("cpu_int_clear", &self.cpu_int_clear())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_CLEAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_core0_cpu_int_clear"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/cpu_int_eip_status.rs b/esp32c3/src/interrupt_core0/cpu_int_eip_status.rs
index 5ec63cc9b1..8de65388af 100644
--- a/esp32c3/src/interrupt_core0/cpu_int_eip_status.rs
+++ b/esp32c3/src/interrupt_core0/cpu_int_eip_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_EIP_STATUS")
-            .field(
-                "cpu_int_eip_status",
-                &format_args!("{}", self.cpu_int_eip_status().bits()),
-            )
+            .field("cpu_int_eip_status", &self.cpu_int_eip_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_EIP_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mac intr map register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_eip_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPU_INT_EIP_STATUS_SPEC;
 impl crate::RegisterSpec for CPU_INT_EIP_STATUS_SPEC {
diff --git a/esp32c3/src/interrupt_core0/cpu_int_enable.rs b/esp32c3/src/interrupt_core0/cpu_int_enable.rs
index e9ae0e7fae..b45d0fd0b4 100644
--- a/esp32c3/src/interrupt_core0/cpu_int_enable.rs
+++ b/esp32c3/src/interrupt_core0/cpu_int_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_ENABLE")
-            .field(
-                "cpu_int_enable",
-                &format_args!("{}", self.cpu_int_enable().bits()),
-            )
+            .field("cpu_int_enable", &self.cpu_int_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_core0_cpu_int_enable"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/cpu_int_pri.rs b/esp32c3/src/interrupt_core0/cpu_int_pri.rs
index 191d8f2926..9f14adc8f3 100644
--- a/esp32c3/src/interrupt_core0/cpu_int_pri.rs
+++ b/esp32c3/src/interrupt_core0/cpu_int_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_PRI")
-            .field("map", &format_args!("{}", self.map().bits()))
+            .field("map", &self.map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - reg_core0_cpu_pri_0_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/cpu_int_thresh.rs b/esp32c3/src/interrupt_core0/cpu_int_thresh.rs
index 7b6f749ad9..2965f018ec 100644
--- a/esp32c3/src/interrupt_core0/cpu_int_thresh.rs
+++ b/esp32c3/src/interrupt_core0/cpu_int_thresh.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_THRESH")
-            .field(
-                "cpu_int_thresh",
-                &format_args!("{}", self.cpu_int_thresh().bits()),
-            )
+            .field("cpu_int_thresh", &self.cpu_int_thresh())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_THRESH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - reg_core0_cpu_int_thresh"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/cpu_int_type.rs b/esp32c3/src/interrupt_core0/cpu_int_type.rs
index 366110432c..ba4f2d0cfb 100644
--- a/esp32c3/src/interrupt_core0/cpu_int_type.rs
+++ b/esp32c3/src/interrupt_core0/cpu_int_type.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_TYPE")
-            .field(
-                "cpu_int_type",
-                &format_args!("{}", self.cpu_int_type().bits()),
-            )
+            .field("cpu_int_type", &self.cpu_int_type())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_TYPE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_core0_cpu_int_type"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs b/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
index 7f2d9f504a..6186c8438e 100644
--- a/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
+++ b/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_0_MAP")
-            .field(
-                "cpu_intr_from_cpu_0_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_0_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_0_map", &self.cpu_intr_from_cpu_0_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_0_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_cpu_intr_from_cpu_0_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs b/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
index 7b6a49fe25..29c05f9a70 100644
--- a/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
+++ b/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_1_MAP")
-            .field(
-                "cpu_intr_from_cpu_1_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_1_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_1_map", &self.cpu_intr_from_cpu_1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_cpu_intr_from_cpu_1_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs b/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
index 28914d53a7..5205af337f 100644
--- a/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
+++ b/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_2_MAP")
-            .field(
-                "cpu_intr_from_cpu_2_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_2_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_2_map", &self.cpu_intr_from_cpu_2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_cpu_intr_from_cpu_2_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs b/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
index fd186751b9..1543522ccd 100644
--- a/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
+++ b/esp32c3/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_3_MAP")
-            .field(
-                "cpu_intr_from_cpu_3_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_3_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_3_map", &self.cpu_intr_from_cpu_3_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_cpu_intr_from_cpu_3_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/dma_apbperi_pms_monitor_violate_intr_map.rs b/esp32c3/src/interrupt_core0/dma_apbperi_pms_monitor_violate_intr_map.rs
index cbbfb74404..46ea09f6fd 100644
--- a/esp32c3/src/interrupt_core0/dma_apbperi_pms_monitor_violate_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/dma_apbperi_pms_monitor_violate_intr_map.rs
@@ -21,17 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "dma_apbperi_pms_monitor_violate_intr_map",
-                &format_args!("{}", self.dma_apbperi_pms_monitor_violate_intr_map().bits()),
+                &self.dma_apbperi_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_dma_apbperi_pms_monitor_violate_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/dma_ch0_int_map.rs b/esp32c3/src/interrupt_core0/dma_ch0_int_map.rs
index 8824d9bbfb..079e4a5fdf 100644
--- a/esp32c3/src/interrupt_core0/dma_ch0_int_map.rs
+++ b/esp32c3/src/interrupt_core0/dma_ch0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CH0_INT_MAP")
-            .field(
-                "dma_ch0_int_map",
-                &format_args!("{}", self.dma_ch0_int_map().bits()),
-            )
+            .field("dma_ch0_int_map", &self.dma_ch0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_dma_ch0_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/dma_ch1_int_map.rs b/esp32c3/src/interrupt_core0/dma_ch1_int_map.rs
index 3df25a03ff..e0a24eaca1 100644
--- a/esp32c3/src/interrupt_core0/dma_ch1_int_map.rs
+++ b/esp32c3/src/interrupt_core0/dma_ch1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CH1_INT_MAP")
-            .field(
-                "dma_ch1_int_map",
-                &format_args!("{}", self.dma_ch1_int_map().bits()),
-            )
+            .field("dma_ch1_int_map", &self.dma_ch1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_dma_ch1_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/dma_ch2_int_map.rs b/esp32c3/src/interrupt_core0/dma_ch2_int_map.rs
index a8a5bf07ee..990ad5d943 100644
--- a/esp32c3/src/interrupt_core0/dma_ch2_int_map.rs
+++ b/esp32c3/src/interrupt_core0/dma_ch2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CH2_INT_MAP")
-            .field(
-                "dma_ch2_int_map",
-                &format_args!("{}", self.dma_ch2_int_map().bits()),
-            )
+            .field("dma_ch2_int_map", &self.dma_ch2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_dma_ch2_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/efuse_int_map.rs b/esp32c3/src/interrupt_core0/efuse_int_map.rs
index 7537ab7b52..1a291f4a94 100644
--- a/esp32c3/src/interrupt_core0/efuse_int_map.rs
+++ b/esp32c3/src/interrupt_core0/efuse_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EFUSE_INT_MAP")
-            .field(
-                "efuse_int_map",
-                &format_args!("{}", self.efuse_int_map().bits()),
-            )
+            .field("efuse_int_map", &self.efuse_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EFUSE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_efuse_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/gpio_interrupt_pro_map.rs b/esp32c3/src/interrupt_core0/gpio_interrupt_pro_map.rs
index 6ab1bd04a8..72c02cc806 100644
--- a/esp32c3/src/interrupt_core0/gpio_interrupt_pro_map.rs
+++ b/esp32c3/src/interrupt_core0/gpio_interrupt_pro_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INTERRUPT_PRO_MAP")
-            .field(
-                "gpio_interrupt_pro_map",
-                &format_args!("{}", self.gpio_interrupt_pro_map().bits()),
-            )
+            .field("gpio_interrupt_pro_map", &self.gpio_interrupt_pro_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_PRO_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_gpio_interrupt_pro_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs b/esp32c3/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
index 8557fb779e..2e26301ccf 100644
--- a/esp32c3/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
+++ b/esp32c3/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("GPIO_INTERRUPT_PRO_NMI_MAP")
             .field(
                 "gpio_interrupt_pro_nmi_map",
-                &format_args!("{}", self.gpio_interrupt_pro_nmi_map().bits()),
+                &self.gpio_interrupt_pro_nmi_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_PRO_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_gpio_interrupt_pro_nmi_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/i2c_ext0_intr_map.rs b/esp32c3/src/interrupt_core0/i2c_ext0_intr_map.rs
index 09731ade9f..273bac7509 100644
--- a/esp32c3/src/interrupt_core0/i2c_ext0_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/i2c_ext0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_EXT0_INTR_MAP")
-            .field(
-                "i2c_ext0_intr_map",
-                &format_args!("{}", self.i2c_ext0_intr_map().bits()),
-            )
+            .field("i2c_ext0_intr_map", &self.i2c_ext0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_EXT0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_i2c_ext0_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/i2c_mst_int_map.rs b/esp32c3/src/interrupt_core0/i2c_mst_int_map.rs
index 0581d6b06f..d12e550b15 100644
--- a/esp32c3/src/interrupt_core0/i2c_mst_int_map.rs
+++ b/esp32c3/src/interrupt_core0/i2c_mst_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_MST_INT_MAP")
-            .field(
-                "i2c_mst_int_map",
-                &format_args!("{}", self.i2c_mst_int_map().bits()),
-            )
+            .field("i2c_mst_int_map", &self.i2c_mst_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_MST_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_i2c_mst_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/i2s1_int_map.rs b/esp32c3/src/interrupt_core0/i2s1_int_map.rs
index 45bfa2117c..39f8ac75f4 100644
--- a/esp32c3/src/interrupt_core0/i2s1_int_map.rs
+++ b/esp32c3/src/interrupt_core0/i2s1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S1_INT_MAP")
-            .field(
-                "i2s1_int_map",
-                &format_args!("{}", self.i2s1_int_map().bits()),
-            )
+            .field("i2s1_int_map", &self.i2s1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_i2s1_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/icache_preload_int_map.rs b/esp32c3/src/interrupt_core0/icache_preload_int_map.rs
index 9ef423ba94..ffec179ae9 100644
--- a/esp32c3/src/interrupt_core0/icache_preload_int_map.rs
+++ b/esp32c3/src/interrupt_core0/icache_preload_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOAD_INT_MAP")
-            .field(
-                "icache_preload_int_map",
-                &format_args!("{}", self.icache_preload_int_map().bits()),
-            )
+            .field("icache_preload_int_map", &self.icache_preload_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOAD_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_icache_preload_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/icache_sync_int_map.rs b/esp32c3/src/interrupt_core0/icache_sync_int_map.rs
index 4d0251382b..25544ed936 100644
--- a/esp32c3/src/interrupt_core0/icache_sync_int_map.rs
+++ b/esp32c3/src/interrupt_core0/icache_sync_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_SYNC_INT_MAP")
-            .field(
-                "icache_sync_int_map",
-                &format_args!("{}", self.icache_sync_int_map().bits()),
-            )
+            .field("icache_sync_int_map", &self.icache_sync_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_SYNC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_icache_sync_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/interrupt_reg_date.rs b/esp32c3/src/interrupt_core0/interrupt_reg_date.rs
index f362b1adc8..f1f1d00f33 100644
--- a/esp32c3/src/interrupt_core0/interrupt_reg_date.rs
+++ b/esp32c3/src/interrupt_core0/interrupt_reg_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT_REG_DATE")
-            .field(
-                "interrupt_reg_date",
-                &format_args!("{}", self.interrupt_reg_date().bits()),
-            )
+            .field("interrupt_reg_date", &self.interrupt_reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - reg_core0_interrupt_reg_date"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/intr_status_reg_0.rs b/esp32c3/src/interrupt_core0/intr_status_reg_0.rs
index bf2b3276d2..1fedce7ee6 100644
--- a/esp32c3/src/interrupt_core0/intr_status_reg_0.rs
+++ b/esp32c3/src/interrupt_core0/intr_status_reg_0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_0")
-            .field(
-                "intr_status_0",
-                &format_args!("{}", self.intr_status_0().bits()),
-            )
+            .field("intr_status_0", &self.intr_status_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mac intr map register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_0_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_0_SPEC {
diff --git a/esp32c3/src/interrupt_core0/intr_status_reg_1.rs b/esp32c3/src/interrupt_core0/intr_status_reg_1.rs
index 439df992ff..2068164bac 100644
--- a/esp32c3/src/interrupt_core0/intr_status_reg_1.rs
+++ b/esp32c3/src/interrupt_core0/intr_status_reg_1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_1")
-            .field(
-                "intr_status_1",
-                &format_args!("{}", self.intr_status_1().bits()),
-            )
+            .field("intr_status_1", &self.intr_status_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mac intr map register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_1_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_1_SPEC {
diff --git a/esp32c3/src/interrupt_core0/ledc_int_map.rs b/esp32c3/src/interrupt_core0/ledc_int_map.rs
index e8d50d52ed..12fdca4458 100644
--- a/esp32c3/src/interrupt_core0/ledc_int_map.rs
+++ b/esp32c3/src/interrupt_core0/ledc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEDC_INT_MAP")
-            .field(
-                "ledc_int_map",
-                &format_args!("{}", self.ledc_int_map().bits()),
-            )
+            .field("ledc_int_map", &self.ledc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEDC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_ledc_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/mac_intr_map.rs b/esp32c3/src/interrupt_core0/mac_intr_map.rs
index da6251de07..1a38a846b2 100644
--- a/esp32c3/src/interrupt_core0/mac_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/mac_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAC_INTR_MAP")
-            .field(
-                "mac_intr_map",
-                &format_args!("{}", self.mac_intr_map().bits()),
-            )
+            .field("mac_intr_map", &self.mac_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - core0_mac_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/mac_nmi_map.rs b/esp32c3/src/interrupt_core0/mac_nmi_map.rs
index 759e789123..ba4c2f1e0c 100644
--- a/esp32c3/src/interrupt_core0/mac_nmi_map.rs
+++ b/esp32c3/src/interrupt_core0/mac_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAC_NMI_MAP")
-            .field(
-                "mac_nmi_map",
-                &format_args!("{}", self.mac_nmi_map().bits()),
-            )
+            .field("mac_nmi_map", &self.mac_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAC_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_mac_nmi_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/pwr_intr_map.rs b/esp32c3/src/interrupt_core0/pwr_intr_map.rs
index e5492d4174..de18c966b8 100644
--- a/esp32c3/src/interrupt_core0/pwr_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/pwr_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWR_INTR_MAP")
-            .field(
-                "pwr_intr_map",
-                &format_args!("{}", self.pwr_intr_map().bits()),
-            )
+            .field("pwr_intr_map", &self.pwr_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWR_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_pwr_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/rmt_intr_map.rs b/esp32c3/src/interrupt_core0/rmt_intr_map.rs
index c59e0eb587..73c36c0daf 100644
--- a/esp32c3/src/interrupt_core0/rmt_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/rmt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RMT_INTR_MAP")
-            .field(
-                "rmt_intr_map",
-                &format_args!("{}", self.rmt_intr_map().bits()),
-            )
+            .field("rmt_intr_map", &self.rmt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RMT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_rmt_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/rsa_int_map.rs b/esp32c3/src/interrupt_core0/rsa_int_map.rs
index a9925e6f87..03e8dc7dea 100644
--- a/esp32c3/src/interrupt_core0/rsa_int_map.rs
+++ b/esp32c3/src/interrupt_core0/rsa_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_INT_MAP")
-            .field(
-                "rsa_int_map",
-                &format_args!("{}", self.rsa_int_map().bits()),
-            )
+            .field("rsa_int_map", &self.rsa_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_rsa_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/rtc_core_intr_map.rs b/esp32c3/src/interrupt_core0/rtc_core_intr_map.rs
index e997ec25d8..3c25cd1347 100644
--- a/esp32c3/src/interrupt_core0/rtc_core_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/rtc_core_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_CORE_INTR_MAP")
-            .field(
-                "rtc_core_intr_map",
-                &format_args!("{}", self.rtc_core_intr_map().bits()),
-            )
+            .field("rtc_core_intr_map", &self.rtc_core_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_CORE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_rtc_core_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/rwble_irq_map.rs b/esp32c3/src/interrupt_core0/rwble_irq_map.rs
index 30b5572a91..a60506b387 100644
--- a/esp32c3/src/interrupt_core0/rwble_irq_map.rs
+++ b/esp32c3/src/interrupt_core0/rwble_irq_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RWBLE_IRQ_MAP")
-            .field(
-                "rwble_irq_map",
-                &format_args!("{}", self.rwble_irq_map().bits()),
-            )
+            .field("rwble_irq_map", &self.rwble_irq_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RWBLE_IRQ_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_rwble_irq_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/rwble_nmi_map.rs b/esp32c3/src/interrupt_core0/rwble_nmi_map.rs
index 39590a91ed..adf018a22a 100644
--- a/esp32c3/src/interrupt_core0/rwble_nmi_map.rs
+++ b/esp32c3/src/interrupt_core0/rwble_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RWBLE_NMI_MAP")
-            .field(
-                "rwble_nmi_map",
-                &format_args!("{}", self.rwble_nmi_map().bits()),
-            )
+            .field("rwble_nmi_map", &self.rwble_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RWBLE_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_rwble_nmi_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/rwbt_irq_map.rs b/esp32c3/src/interrupt_core0/rwbt_irq_map.rs
index f3994bd84a..d971596eb8 100644
--- a/esp32c3/src/interrupt_core0/rwbt_irq_map.rs
+++ b/esp32c3/src/interrupt_core0/rwbt_irq_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RWBT_IRQ_MAP")
-            .field(
-                "rwbt_irq_map",
-                &format_args!("{}", self.rwbt_irq_map().bits()),
-            )
+            .field("rwbt_irq_map", &self.rwbt_irq_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RWBT_IRQ_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_rwbt_irq_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/rwbt_nmi_map.rs b/esp32c3/src/interrupt_core0/rwbt_nmi_map.rs
index 11285089d9..1c0b7f0b66 100644
--- a/esp32c3/src/interrupt_core0/rwbt_nmi_map.rs
+++ b/esp32c3/src/interrupt_core0/rwbt_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RWBT_NMI_MAP")
-            .field(
-                "rwbt_nmi_map",
-                &format_args!("{}", self.rwbt_nmi_map().bits()),
-            )
+            .field("rwbt_nmi_map", &self.rwbt_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RWBT_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_rwbt_nmi_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/sha_int_map.rs b/esp32c3/src/interrupt_core0/sha_int_map.rs
index 68f504a349..52a64ccfec 100644
--- a/esp32c3/src/interrupt_core0/sha_int_map.rs
+++ b/esp32c3/src/interrupt_core0/sha_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA_INT_MAP")
-            .field(
-                "sha_int_map",
-                &format_args!("{}", self.sha_int_map().bits()),
-            )
+            .field("sha_int_map", &self.sha_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_sha_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/slc0_intr_map.rs b/esp32c3/src/interrupt_core0/slc0_intr_map.rs
index 9dd085ba5a..7f4f69058e 100644
--- a/esp32c3/src/interrupt_core0/slc0_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/slc0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC0_INTR_MAP")
-            .field(
-                "slc0_intr_map",
-                &format_args!("{}", self.slc0_intr_map().bits()),
-            )
+            .field("slc0_intr_map", &self.slc0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_slc0_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/slc1_intr_map.rs b/esp32c3/src/interrupt_core0/slc1_intr_map.rs
index 9d94394702..21bfe9528e 100644
--- a/esp32c3/src/interrupt_core0/slc1_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/slc1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC1_INTR_MAP")
-            .field(
-                "slc1_intr_map",
-                &format_args!("{}", self.slc1_intr_map().bits()),
-            )
+            .field("slc1_intr_map", &self.slc1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_slc1_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/spi_intr_1_map.rs b/esp32c3/src/interrupt_core0/spi_intr_1_map.rs
index 80607c6f88..3cfcf55ac4 100644
--- a/esp32c3/src/interrupt_core0/spi_intr_1_map.rs
+++ b/esp32c3/src/interrupt_core0/spi_intr_1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_INTR_1_MAP")
-            .field(
-                "spi_intr_1_map",
-                &format_args!("{}", self.spi_intr_1_map().bits()),
-            )
+            .field("spi_intr_1_map", &self.spi_intr_1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_INTR_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_spi_intr_1_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/spi_intr_2_map.rs b/esp32c3/src/interrupt_core0/spi_intr_2_map.rs
index 079d8963ac..b7d5e39adc 100644
--- a/esp32c3/src/interrupt_core0/spi_intr_2_map.rs
+++ b/esp32c3/src/interrupt_core0/spi_intr_2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_INTR_2_MAP")
-            .field(
-                "spi_intr_2_map",
-                &format_args!("{}", self.spi_intr_2_map().bits()),
-            )
+            .field("spi_intr_2_map", &self.spi_intr_2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_INTR_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_spi_intr_2_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/spi_mem_reject_intr_map.rs b/esp32c3/src/interrupt_core0/spi_mem_reject_intr_map.rs
index 2fe8f2bd11..bddfa626e2 100644
--- a/esp32c3/src/interrupt_core0/spi_mem_reject_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/spi_mem_reject_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_MEM_REJECT_INTR_MAP")
-            .field(
-                "spi_mem_reject_intr_map",
-                &format_args!("{}", self.spi_mem_reject_intr_map().bits()),
-            )
+            .field("spi_mem_reject_intr_map", &self.spi_mem_reject_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_MEM_REJECT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_spi_mem_reject_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/systimer_target0_int_map.rs b/esp32c3/src/interrupt_core0/systimer_target0_int_map.rs
index 8c088dfe03..11470d22ea 100644
--- a/esp32c3/src/interrupt_core0/systimer_target0_int_map.rs
+++ b/esp32c3/src/interrupt_core0/systimer_target0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_TARGET0_INT_MAP")
-            .field(
-                "systimer_target0_int_map",
-                &format_args!("{}", self.systimer_target0_int_map().bits()),
-            )
+            .field("systimer_target0_int_map", &self.systimer_target0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_systimer_target0_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/systimer_target1_int_map.rs b/esp32c3/src/interrupt_core0/systimer_target1_int_map.rs
index 914ccf0ba1..700c732775 100644
--- a/esp32c3/src/interrupt_core0/systimer_target1_int_map.rs
+++ b/esp32c3/src/interrupt_core0/systimer_target1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_TARGET1_INT_MAP")
-            .field(
-                "systimer_target1_int_map",
-                &format_args!("{}", self.systimer_target1_int_map().bits()),
-            )
+            .field("systimer_target1_int_map", &self.systimer_target1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_systimer_target1_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/systimer_target2_int_map.rs b/esp32c3/src/interrupt_core0/systimer_target2_int_map.rs
index 73f142ff8d..c2760f128c 100644
--- a/esp32c3/src/interrupt_core0/systimer_target2_int_map.rs
+++ b/esp32c3/src/interrupt_core0/systimer_target2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_TARGET2_INT_MAP")
-            .field(
-                "systimer_target2_int_map",
-                &format_args!("{}", self.systimer_target2_int_map().bits()),
-            )
+            .field("systimer_target2_int_map", &self.systimer_target2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_systimer_target2_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/tg1_t0_int_map.rs b/esp32c3/src/interrupt_core0/tg1_t0_int_map.rs
index f8787c0044..ed32522b46 100644
--- a/esp32c3/src/interrupt_core0/tg1_t0_int_map.rs
+++ b/esp32c3/src/interrupt_core0/tg1_t0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG1_T0_INT_MAP")
-            .field(
-                "tg1_t0_int_map",
-                &format_args!("{}", self.tg1_t0_int_map().bits()),
-            )
+            .field("tg1_t0_int_map", &self.tg1_t0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG1_T0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_tg1_t0_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/tg1_wdt_int_map.rs b/esp32c3/src/interrupt_core0/tg1_wdt_int_map.rs
index 593c837c33..c8279ceeaf 100644
--- a/esp32c3/src/interrupt_core0/tg1_wdt_int_map.rs
+++ b/esp32c3/src/interrupt_core0/tg1_wdt_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG1_WDT_INT_MAP")
-            .field(
-                "tg1_wdt_int_map",
-                &format_args!("{}", self.tg1_wdt_int_map().bits()),
-            )
+            .field("tg1_wdt_int_map", &self.tg1_wdt_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG1_WDT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_tg1_wdt_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/tg_t0_int_map.rs b/esp32c3/src/interrupt_core0/tg_t0_int_map.rs
index 1775d33e4b..7d1255fb24 100644
--- a/esp32c3/src/interrupt_core0/tg_t0_int_map.rs
+++ b/esp32c3/src/interrupt_core0/tg_t0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG_T0_INT_MAP")
-            .field(
-                "tg_t0_int_map",
-                &format_args!("{}", self.tg_t0_int_map().bits()),
-            )
+            .field("tg_t0_int_map", &self.tg_t0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG_T0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_tg_t0_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/tg_wdt_int_map.rs b/esp32c3/src/interrupt_core0/tg_wdt_int_map.rs
index bd71053c51..e72c3a86b9 100644
--- a/esp32c3/src/interrupt_core0/tg_wdt_int_map.rs
+++ b/esp32c3/src/interrupt_core0/tg_wdt_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG_WDT_INT_MAP")
-            .field(
-                "tg_wdt_int_map",
-                &format_args!("{}", self.tg_wdt_int_map().bits()),
-            )
+            .field("tg_wdt_int_map", &self.tg_wdt_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG_WDT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_tg_wdt_int_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/timer_int1_map.rs b/esp32c3/src/interrupt_core0/timer_int1_map.rs
index f3a8c7eacc..f3c57f569c 100644
--- a/esp32c3/src/interrupt_core0/timer_int1_map.rs
+++ b/esp32c3/src/interrupt_core0/timer_int1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_INT1_MAP")
-            .field(
-                "timer_int1_map",
-                &format_args!("{}", self.timer_int1_map().bits()),
-            )
+            .field("timer_int1_map", &self.timer_int1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_INT1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_timer_int1_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/timer_int2_map.rs b/esp32c3/src/interrupt_core0/timer_int2_map.rs
index 4000f1b7ba..70519ce620 100644
--- a/esp32c3/src/interrupt_core0/timer_int2_map.rs
+++ b/esp32c3/src/interrupt_core0/timer_int2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_INT2_MAP")
-            .field(
-                "timer_int2_map",
-                &format_args!("{}", self.timer_int2_map().bits()),
-            )
+            .field("timer_int2_map", &self.timer_int2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_INT2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_timer_int2_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/uart1_intr_map.rs b/esp32c3/src/interrupt_core0/uart1_intr_map.rs
index cd13e9407a..0336610983 100644
--- a/esp32c3/src/interrupt_core0/uart1_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/uart1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART1_INTR_MAP")
-            .field(
-                "uart1_intr_map",
-                &format_args!("{}", self.uart1_intr_map().bits()),
-            )
+            .field("uart1_intr_map", &self.uart1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_uart1_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/uart_intr_map.rs b/esp32c3/src/interrupt_core0/uart_intr_map.rs
index abe2be9c70..0a227b9958 100644
--- a/esp32c3/src/interrupt_core0/uart_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/uart_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART_INTR_MAP")
-            .field(
-                "uart_intr_map",
-                &format_args!("{}", self.uart_intr_map().bits()),
-            )
+            .field("uart_intr_map", &self.uart_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_uart_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/uhci0_intr_map.rs b/esp32c3/src/interrupt_core0/uhci0_intr_map.rs
index dfdf873fc4..fca57831f4 100644
--- a/esp32c3/src/interrupt_core0/uhci0_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/uhci0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UHCI0_INTR_MAP")
-            .field(
-                "uhci0_intr_map",
-                &format_args!("{}", self.uhci0_intr_map().bits()),
-            )
+            .field("uhci0_intr_map", &self.uhci0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UHCI0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_uhci0_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/interrupt_core0/usb_intr_map.rs b/esp32c3/src/interrupt_core0/usb_intr_map.rs
index a74175aaa9..fbc79e37a2 100644
--- a/esp32c3/src/interrupt_core0/usb_intr_map.rs
+++ b/esp32c3/src/interrupt_core0/usb_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_INTR_MAP")
-            .field(
-                "usb_intr_map",
-                &format_args!("{}", self.usb_intr_map().bits()),
-            )
+            .field("usb_intr_map", &self.usb_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_core0_usb_intr_map"]
     #[inline(always)]
diff --git a/esp32c3/src/io_mux/date.rs b/esp32c3/src/io_mux/date.rs
index 0c84b0ecdc..af7f59ecf0 100644
--- a/esp32c3/src/io_mux/date.rs
+++ b/esp32c3/src/io_mux/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("reg_date", &format_args!("{}", self.reg_date().bits()))
+            .field("reg_date", &self.reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
diff --git a/esp32c3/src/io_mux/gpio.rs b/esp32c3/src/io_mux/gpio.rs
index ff75f38c3f..77004b071f 100644
--- a/esp32c3/src/io_mux/gpio.rs
+++ b/esp32c3/src/io_mux/gpio.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled."]
     #[inline(always)]
diff --git a/esp32c3/src/io_mux/pin_ctrl.rs b/esp32c3/src/io_mux/pin_ctrl.rs
index ecec0837d7..9628744bc2 100644
--- a/esp32c3/src/io_mux/pin_ctrl.rs
+++ b/esp32c3/src/io_mux/pin_ctrl.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN_CTRL")
-            .field("clk_out1", &format_args!("{}", self.clk_out1().bits()))
-            .field("clk_out2", &format_args!("{}", self.clk_out2().bits()))
-            .field("clk_out3", &format_args!("{}", self.clk_out3().bits()))
+            .field("clk_out1", &self.clk_out1())
+            .field("clk_out2", &self.clk_out2())
+            .field("clk_out3", &self.clk_out3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals."]
     #[inline(always)]
diff --git a/esp32c3/src/ledc/ch/conf0.rs b/esp32c3/src/ledc/ch/conf0.rs
index e7a2307eed..0a3504547b 100644
--- a/esp32c3/src/ledc/ch/conf0.rs
+++ b/esp32c3/src/ledc/ch/conf0.rs
@@ -57,20 +57,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("timer_sel", &format_args!("{}", self.timer_sel().bits()))
-            .field("sig_out_en", &format_args!("{}", self.sig_out_en().bit()))
-            .field("idle_lv", &format_args!("{}", self.idle_lv().bit()))
-            .field("ovf_num", &format_args!("{}", self.ovf_num().bits()))
-            .field("ovf_cnt_en", &format_args!("{}", self.ovf_cnt_en().bit()))
+            .field("timer_sel", &self.timer_sel())
+            .field("sig_out_en", &self.sig_out_en())
+            .field("idle_lv", &self.idle_lv())
+            .field("ovf_num", &self.ovf_num())
+            .field("ovf_cnt_en", &self.ovf_cnt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reg_timer_sel_lsch0."]
     #[inline(always)]
diff --git a/esp32c3/src/ledc/ch/conf1.rs b/esp32c3/src/ledc/ch/conf1.rs
index 854bfef729..d72219fd78 100644
--- a/esp32c3/src/ledc/ch/conf1.rs
+++ b/esp32c3/src/ledc/ch/conf1.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field("duty_scale", &format_args!("{}", self.duty_scale().bits()))
-            .field("duty_cycle", &format_args!("{}", self.duty_cycle().bits()))
-            .field("duty_num", &format_args!("{}", self.duty_num().bits()))
-            .field("duty_inc", &format_args!("{}", self.duty_inc().bit()))
-            .field("duty_start", &format_args!("{}", self.duty_start().bit()))
+            .field("duty_scale", &self.duty_scale())
+            .field("duty_cycle", &self.duty_cycle())
+            .field("duty_num", &self.duty_num())
+            .field("duty_inc", &self.duty_inc())
+            .field("duty_start", &self.duty_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - reg_duty_scale_lsch0."]
     #[inline(always)]
diff --git a/esp32c3/src/ledc/ch/duty.rs b/esp32c3/src/ledc/ch/duty.rs
index 6d50fa0b58..25731ba345 100644
--- a/esp32c3/src/ledc/ch/duty.rs
+++ b/esp32c3/src/ledc/ch/duty.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DUTY")
-            .field("duty", &format_args!("{}", self.duty().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DUTY").field("duty", &self.duty()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/ledc/ch/duty_r.rs b/esp32c3/src/ledc/ch/duty_r.rs
index cfa5ba0443..dc49f22fae 100644
--- a/esp32c3/src/ledc/ch/duty_r.rs
+++ b/esp32c3/src/ledc/ch/duty_r.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DUTY_R")
-            .field("duty_r", &format_args!("{}", self.duty_r().bits()))
+            .field("duty_r", &self.duty_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_R_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "LEDC_LSCH0_DUTY_R.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`duty_r::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DUTY_R_SPEC;
 impl crate::RegisterSpec for DUTY_R_SPEC {
diff --git a/esp32c3/src/ledc/ch/hpoint.rs b/esp32c3/src/ledc/ch/hpoint.rs
index 2e311795d5..2849b316d6 100644
--- a/esp32c3/src/ledc/ch/hpoint.rs
+++ b/esp32c3/src/ledc/ch/hpoint.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPOINT")
-            .field("hpoint", &format_args!("{}", self.hpoint().bits()))
+            .field("hpoint", &self.hpoint())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPOINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - reg_hpoint_lsch0."]
     #[inline(always)]
diff --git a/esp32c3/src/ledc/conf.rs b/esp32c3/src/ledc/conf.rs
index e077242c11..af9668219c 100644
--- a/esp32c3/src/ledc/conf.rs
+++ b/esp32c3/src/ledc/conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field(
-                "apb_clk_sel",
-                &format_args!("{}", self.apb_clk_sel().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("apb_clk_sel", &self.apb_clk_sel())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reg_apb_clk_sel."]
     #[inline(always)]
diff --git a/esp32c3/src/ledc/date.rs b/esp32c3/src/ledc/date.rs
index 75d632ce11..2d88bc761a 100644
--- a/esp32c3/src/ledc/date.rs
+++ b/esp32c3/src/ledc/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("ledc_date", &format_args!("{}", self.ledc_date().bits()))
+            .field("ledc_date", &self.ledc_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_ledc_date."]
     #[inline(always)]
diff --git a/esp32c3/src/ledc/int_ena.rs b/esp32c3/src/ledc/int_ena.rs
index ea85e28446..a9812774e4 100644
--- a/esp32c3/src/ledc/int_ena.rs
+++ b/esp32c3/src/ledc/int_ena.rs
@@ -145,49 +145,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the TIMER(0-3)_OVF interrupt."]
     #[doc = ""]
diff --git a/esp32c3/src/ledc/int_raw.rs b/esp32c3/src/ledc/int_raw.rs
index 316cea9ca7..538cd99080 100644
--- a/esp32c3/src/ledc/int_raw.rs
+++ b/esp32c3/src/ledc/int_raw.rs
@@ -145,49 +145,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "reg_lstimer(0-3)_ovf_int_raw."]
     #[doc = ""]
diff --git a/esp32c3/src/ledc/int_st.rs b/esp32c3/src/ledc/int_st.rs
index 12470f90ad..9a22b39b5b 100644
--- a/esp32c3/src/ledc/int_st.rs
+++ b/esp32c3/src/ledc/int_st.rs
@@ -137,49 +137,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "LEDC_INT_ST.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c3/src/ledc/timer/conf.rs b/esp32c3/src/ledc/timer/conf.rs
index 5a5af23e5d..727495d06a 100644
--- a/esp32c3/src/ledc/timer/conf.rs
+++ b/esp32c3/src/ledc/timer/conf.rs
@@ -55,20 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("duty_res", &format_args!("{}", self.duty_res().bits()))
-            .field("clk_div", &format_args!("{}", self.clk_div().bits()))
-            .field("pause", &format_args!("{}", self.pause().bit()))
-            .field("rst", &format_args!("{}", self.rst().bit()))
-            .field("tick_sel", &format_args!("{}", self.tick_sel().bit()))
+            .field("duty_res", &self.duty_res())
+            .field("clk_div", &self.clk_div())
+            .field("pause", &self.pause())
+            .field("rst", &self.rst())
+            .field("tick_sel", &self.tick_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - reg_lstimer0_duty_res."]
     #[inline(always)]
diff --git a/esp32c3/src/ledc/timer/value.rs b/esp32c3/src/ledc/timer/value.rs
index 487673a33a..ff33f0b7e0 100644
--- a/esp32c3/src/ledc/timer/value.rs
+++ b/esp32c3/src/ledc/timer/value.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("VALUE")
-            .field("cnt", &format_args!("{}", self.cnt().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("VALUE").field("cnt", &self.cnt()).finish()
     }
 }
 #[doc = "LEDC_LSTIMER0_VALUE.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c3/src/lib.rs b/esp32c3/src/lib.rs
index 6461daad75..f5224b530e 100644
--- a/esp32c3/src/lib.rs
+++ b/esp32c3/src/lib.rs
@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32-C3 microcontrollers (generated using svd2rust v0.33.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32-C3 microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
diff --git a/esp32c3/src/rmt/ch_rx_carrier_rm.rs b/esp32c3/src/rmt/ch_rx_carrier_rm.rs
index 9d8e5fbbce..524c4b7a59 100644
--- a/esp32c3/src/rmt/ch_rx_carrier_rm.rs
+++ b/esp32c3/src/rmt/ch_rx_carrier_rm.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_CARRIER_RM")
-            .field(
-                "carrier_low_thres",
-                &format_args!("{}", self.carrier_low_thres().bits()),
-            )
-            .field(
-                "carrier_high_thres",
-                &format_args!("{}", self.carrier_high_thres().bits()),
-            )
+            .field("carrier_low_thres", &self.carrier_low_thres())
+            .field("carrier_high_thres", &self.carrier_high_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_CARRIER_RM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - reg_carrier_low_thres_ch2."]
     #[inline(always)]
diff --git a/esp32c3/src/rmt/ch_rx_conf0.rs b/esp32c3/src/rmt/ch_rx_conf0.rs
index 24c0e327a5..5cd2fb10cf 100644
--- a/esp32c3/src/rmt/ch_rx_conf0.rs
+++ b/esp32c3/src/rmt/ch_rx_conf0.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_CONF0")
-            .field("div_cnt", &format_args!("{}", self.div_cnt().bits()))
-            .field("idle_thres", &format_args!("{}", self.idle_thres().bits()))
-            .field("mem_size", &format_args!("{}", self.mem_size().bits()))
-            .field("carrier_en", &format_args!("{}", self.carrier_en().bit()))
-            .field(
-                "carrier_out_lv",
-                &format_args!("{}", self.carrier_out_lv().bit()),
-            )
+            .field("div_cnt", &self.div_cnt())
+            .field("idle_thres", &self.idle_thres())
+            .field("mem_size", &self.mem_size())
+            .field("carrier_en", &self.carrier_en())
+            .field("carrier_out_lv", &self.carrier_out_lv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - reg_div_cnt_ch2."]
     #[inline(always)]
diff --git a/esp32c3/src/rmt/ch_rx_conf1.rs b/esp32c3/src/rmt/ch_rx_conf1.rs
index 4c73720eba..864733668f 100644
--- a/esp32c3/src/rmt/ch_rx_conf1.rs
+++ b/esp32c3/src/rmt/ch_rx_conf1.rs
@@ -61,29 +61,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_CONF1")
-            .field("rx_en", &format_args!("{}", self.rx_en().bit()))
-            .field("mem_owner", &format_args!("{}", self.mem_owner().bit()))
-            .field(
-                "rx_filter_en",
-                &format_args!("{}", self.rx_filter_en().bit()),
-            )
-            .field(
-                "rx_filter_thres",
-                &format_args!("{}", self.rx_filter_thres().bits()),
-            )
-            .field(
-                "mem_rx_wrap_en",
-                &format_args!("{}", self.mem_rx_wrap_en().bit()),
-            )
+            .field("rx_en", &self.rx_en())
+            .field("mem_owner", &self.mem_owner())
+            .field("rx_filter_en", &self.rx_filter_en())
+            .field("rx_filter_thres", &self.rx_filter_thres())
+            .field("mem_rx_wrap_en", &self.mem_rx_wrap_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_rx_en_ch2."]
     #[inline(always)]
diff --git a/esp32c3/src/rmt/ch_rx_lim.rs b/esp32c3/src/rmt/ch_rx_lim.rs
index 6e30e08c10..57fc419660 100644
--- a/esp32c3/src/rmt/ch_rx_lim.rs
+++ b/esp32c3/src/rmt/ch_rx_lim.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_LIM")
-            .field("rx_lim", &format_args!("{}", self.rx_lim().bits()))
+            .field("rx_lim", &self.rx_lim())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_LIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - reg_rmt_rx_lim_ch2."]
     #[inline(always)]
diff --git a/esp32c3/src/rmt/ch_rx_status.rs b/esp32c3/src/rmt/ch_rx_status.rs
index e7488e4618..86997ee0b5 100644
--- a/esp32c3/src/rmt/ch_rx_status.rs
+++ b/esp32c3/src/rmt/ch_rx_status.rs
@@ -48,33 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_STATUS")
-            .field(
-                "mem_waddr_ex",
-                &format_args!("{}", self.mem_waddr_ex().bits()),
-            )
-            .field(
-                "apb_mem_raddr",
-                &format_args!("{}", self.apb_mem_raddr().bits()),
-            )
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field(
-                "mem_owner_err",
-                &format_args!("{}", self.mem_owner_err().bit()),
-            )
-            .field("mem_full", &format_args!("{}", self.mem_full().bit()))
-            .field(
-                "apb_mem_rd_err",
-                &format_args!("{}", self.apb_mem_rd_err().bit()),
-            )
+            .field("mem_waddr_ex", &self.mem_waddr_ex())
+            .field("apb_mem_raddr", &self.apb_mem_raddr())
+            .field("state", &self.state())
+            .field("mem_owner_err", &self.mem_owner_err())
+            .field("mem_full", &self.mem_full())
+            .field("apb_mem_rd_err", &self.apb_mem_rd_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RMT_CH2STATUS_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_RX_STATUS_SPEC;
 impl crate::RegisterSpec for CH_RX_STATUS_SPEC {
diff --git a/esp32c3/src/rmt/ch_tx_conf0.rs b/esp32c3/src/rmt/ch_tx_conf0.rs
index 869497dedf..1dfc1fd4df 100644
--- a/esp32c3/src/rmt/ch_tx_conf0.rs
+++ b/esp32c3/src/rmt/ch_tx_conf0.rs
@@ -108,37 +108,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_TX_CONF0")
-            .field(
-                "tx_conti_mode",
-                &format_args!("{}", self.tx_conti_mode().bit()),
-            )
-            .field(
-                "mem_tx_wrap_en",
-                &format_args!("{}", self.mem_tx_wrap_en().bit()),
-            )
-            .field("idle_out_lv", &format_args!("{}", self.idle_out_lv().bit()))
-            .field("idle_out_en", &format_args!("{}", self.idle_out_en().bit()))
-            .field("tx_stop", &format_args!("{}", self.tx_stop().bit()))
-            .field("div_cnt", &format_args!("{}", self.div_cnt().bits()))
-            .field("mem_size", &format_args!("{}", self.mem_size().bits()))
-            .field(
-                "carrier_eff_en",
-                &format_args!("{}", self.carrier_eff_en().bit()),
-            )
-            .field("carrier_en", &format_args!("{}", self.carrier_en().bit()))
-            .field(
-                "carrier_out_lv",
-                &format_args!("{}", self.carrier_out_lv().bit()),
-            )
+            .field("tx_conti_mode", &self.tx_conti_mode())
+            .field("mem_tx_wrap_en", &self.mem_tx_wrap_en())
+            .field("idle_out_lv", &self.idle_out_lv())
+            .field("idle_out_en", &self.idle_out_en())
+            .field("tx_stop", &self.tx_stop())
+            .field("div_cnt", &self.div_cnt())
+            .field("mem_size", &self.mem_size())
+            .field("carrier_eff_en", &self.carrier_eff_en())
+            .field("carrier_en", &self.carrier_en())
+            .field("carrier_out_lv", &self.carrier_out_lv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_TX_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_tx_start_ch0."]
     #[inline(always)]
diff --git a/esp32c3/src/rmt/ch_tx_lim.rs b/esp32c3/src/rmt/ch_tx_lim.rs
index ca2113d207..bae9ca154d 100644
--- a/esp32c3/src/rmt/ch_tx_lim.rs
+++ b/esp32c3/src/rmt/ch_tx_lim.rs
@@ -37,24 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_TX_LIM")
-            .field("tx_lim", &format_args!("{}", self.tx_lim().bits()))
-            .field(
-                "tx_loop_num",
-                &format_args!("{}", self.tx_loop_num().bits()),
-            )
-            .field(
-                "tx_loop_cnt_en",
-                &format_args!("{}", self.tx_loop_cnt_en().bit()),
-            )
+            .field("tx_lim", &self.tx_lim())
+            .field("tx_loop_num", &self.tx_loop_num())
+            .field("tx_loop_cnt_en", &self.tx_loop_cnt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_TX_LIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - reg_rmt_tx_lim_ch0."]
     #[inline(always)]
diff --git a/esp32c3/src/rmt/ch_tx_status.rs b/esp32c3/src/rmt/ch_tx_status.rs
index d38f6085e9..c6dd1b9a3b 100644
--- a/esp32c3/src/rmt/ch_tx_status.rs
+++ b/esp32c3/src/rmt/ch_tx_status.rs
@@ -55,37 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_TX_STATUS")
-            .field(
-                "mem_raddr_ex",
-                &format_args!("{}", self.mem_raddr_ex().bits()),
-            )
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field(
-                "apb_mem_waddr",
-                &format_args!("{}", self.apb_mem_waddr().bits()),
-            )
-            .field(
-                "apb_mem_rd_err",
-                &format_args!("{}", self.apb_mem_rd_err().bit()),
-            )
-            .field("mem_empty", &format_args!("{}", self.mem_empty().bit()))
-            .field(
-                "apb_mem_wr_err",
-                &format_args!("{}", self.apb_mem_wr_err().bit()),
-            )
-            .field(
-                "apb_mem_raddr",
-                &format_args!("{}", self.apb_mem_raddr().bits()),
-            )
+            .field("mem_raddr_ex", &self.mem_raddr_ex())
+            .field("state", &self.state())
+            .field("apb_mem_waddr", &self.apb_mem_waddr())
+            .field("apb_mem_rd_err", &self.apb_mem_rd_err())
+            .field("mem_empty", &self.mem_empty())
+            .field("apb_mem_wr_err", &self.apb_mem_wr_err())
+            .field("apb_mem_raddr", &self.apb_mem_raddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RMT_CH%sSTATUS_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_TX_STATUS_SPEC;
 impl crate::RegisterSpec for CH_TX_STATUS_SPEC {
diff --git a/esp32c3/src/rmt/chcarrier_duty.rs b/esp32c3/src/rmt/chcarrier_duty.rs
index 681c3361b2..4b0aff9adf 100644
--- a/esp32c3/src/rmt/chcarrier_duty.rs
+++ b/esp32c3/src/rmt/chcarrier_duty.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHCARRIER_DUTY")
-            .field(
-                "carrier_low",
-                &format_args!("{}", self.carrier_low().bits()),
-            )
-            .field(
-                "carrier_high",
-                &format_args!("{}", self.carrier_high().bits()),
-            )
+            .field("carrier_low", &self.carrier_low())
+            .field("carrier_high", &self.carrier_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHCARRIER_DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - reg_carrier_low_ch0."]
     #[inline(always)]
diff --git a/esp32c3/src/rmt/chdata.rs b/esp32c3/src/rmt/chdata.rs
index e416c1f7bc..02fcd040aa 100644
--- a/esp32c3/src/rmt/chdata.rs
+++ b/esp32c3/src/rmt/chdata.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHDATA")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
diff --git a/esp32c3/src/rmt/date.rs b/esp32c3/src/rmt/date.rs
index c0740fe1e7..1eab98cf7e 100644
--- a/esp32c3/src/rmt/date.rs
+++ b/esp32c3/src/rmt/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/rmt/int_ena.rs b/esp32c3/src/rmt/int_ena.rs
index 69ae99164a..4660818d23 100644
--- a/esp32c3/src/rmt/int_ena.rs
+++ b/esp32c3/src/rmt/int_ena.rs
@@ -211,41 +211,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_rx_end", &format_args!("{}", self.ch2_rx_end().bit()))
-            .field("ch3_rx_end", &format_args!("{}", self.ch3_rx_end().bit()))
-            .field("ch0_tx_err", &format_args!("{}", self.ch0_tx_err().bit()))
-            .field("ch1_tx_err", &format_args!("{}", self.ch1_tx_err().bit()))
-            .field("ch2_rx_err", &format_args!("{}", self.ch2_rx_err().bit()))
-            .field("ch3_rx_err", &format_args!("{}", self.ch3_rx_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_rx_thr_event",
-                &format_args!("{}", self.ch2_rx_thr_event().bit()),
-            )
-            .field(
-                "ch3_rx_thr_event",
-                &format_args!("{}", self.ch3_rx_thr_event().bit()),
-            )
-            .field("ch0_tx_loop", &format_args!("{}", self.ch0_tx_loop().bit()))
-            .field("ch1_tx_loop", &format_args!("{}", self.ch1_tx_loop().bit()))
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_rx_end", &self.ch2_rx_end())
+            .field("ch3_rx_end", &self.ch3_rx_end())
+            .field("ch0_tx_err", &self.ch0_tx_err())
+            .field("ch1_tx_err", &self.ch1_tx_err())
+            .field("ch2_rx_err", &self.ch2_rx_err())
+            .field("ch3_rx_err", &self.ch3_rx_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_rx_thr_event", &self.ch2_rx_thr_event())
+            .field("ch3_rx_thr_event", &self.ch3_rx_thr_event())
+            .field("ch0_tx_loop", &self.ch0_tx_loop())
+            .field("ch1_tx_loop", &self.ch1_tx_loop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "reg_ch(0-1)_tx_end_int_ena."]
     #[doc = ""]
diff --git a/esp32c3/src/rmt/int_raw.rs b/esp32c3/src/rmt/int_raw.rs
index 3260a20948..4963cac20c 100644
--- a/esp32c3/src/rmt/int_raw.rs
+++ b/esp32c3/src/rmt/int_raw.rs
@@ -211,41 +211,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_rx_end", &format_args!("{}", self.ch2_rx_end().bit()))
-            .field("ch3_rx_end", &format_args!("{}", self.ch3_rx_end().bit()))
-            .field("ch0_tx_err", &format_args!("{}", self.ch0_tx_err().bit()))
-            .field("ch1_tx_err", &format_args!("{}", self.ch1_tx_err().bit()))
-            .field("ch2_rx_err", &format_args!("{}", self.ch2_rx_err().bit()))
-            .field("ch3_rx_err", &format_args!("{}", self.ch3_rx_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_rx_thr_event",
-                &format_args!("{}", self.ch2_rx_thr_event().bit()),
-            )
-            .field(
-                "ch3_rx_thr_event",
-                &format_args!("{}", self.ch3_rx_thr_event().bit()),
-            )
-            .field("ch0_tx_loop", &format_args!("{}", self.ch0_tx_loop().bit()))
-            .field("ch1_tx_loop", &format_args!("{}", self.ch1_tx_loop().bit()))
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_rx_end", &self.ch2_rx_end())
+            .field("ch3_rx_end", &self.ch3_rx_end())
+            .field("ch0_tx_err", &self.ch0_tx_err())
+            .field("ch1_tx_err", &self.ch1_tx_err())
+            .field("ch2_rx_err", &self.ch2_rx_err())
+            .field("ch3_rx_err", &self.ch3_rx_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_rx_thr_event", &self.ch2_rx_thr_event())
+            .field("ch3_rx_thr_event", &self.ch3_rx_thr_event())
+            .field("ch0_tx_loop", &self.ch0_tx_loop())
+            .field("ch1_tx_loop", &self.ch1_tx_loop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "reg_ch(0-1)_tx_end_int_raw."]
     #[doc = ""]
diff --git a/esp32c3/src/rmt/int_st.rs b/esp32c3/src/rmt/int_st.rs
index b645ad531c..22930f3c6b 100644
--- a/esp32c3/src/rmt/int_st.rs
+++ b/esp32c3/src/rmt/int_st.rs
@@ -195,41 +195,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_rx_end", &format_args!("{}", self.ch2_rx_end().bit()))
-            .field("ch3_rx_end", &format_args!("{}", self.ch3_rx_end().bit()))
-            .field("ch0_tx_err", &format_args!("{}", self.ch0_tx_err().bit()))
-            .field("ch1_tx_err", &format_args!("{}", self.ch1_tx_err().bit()))
-            .field("ch2_rx_err", &format_args!("{}", self.ch2_rx_err().bit()))
-            .field("ch3_rx_err", &format_args!("{}", self.ch3_rx_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_rx_thr_event",
-                &format_args!("{}", self.ch2_rx_thr_event().bit()),
-            )
-            .field(
-                "ch3_rx_thr_event",
-                &format_args!("{}", self.ch3_rx_thr_event().bit()),
-            )
-            .field("ch0_tx_loop", &format_args!("{}", self.ch0_tx_loop().bit()))
-            .field("ch1_tx_loop", &format_args!("{}", self.ch1_tx_loop().bit()))
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_rx_end", &self.ch2_rx_end())
+            .field("ch3_rx_end", &self.ch3_rx_end())
+            .field("ch0_tx_err", &self.ch0_tx_err())
+            .field("ch1_tx_err", &self.ch1_tx_err())
+            .field("ch2_rx_err", &self.ch2_rx_err())
+            .field("ch3_rx_err", &self.ch3_rx_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_rx_thr_event", &self.ch2_rx_thr_event())
+            .field("ch3_rx_thr_event", &self.ch3_rx_thr_event())
+            .field("ch0_tx_loop", &self.ch0_tx_loop())
+            .field("ch1_tx_loop", &self.ch1_tx_loop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RMT_INT_ST_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c3/src/rmt/sys_conf.rs b/esp32c3/src/rmt/sys_conf.rs
index 042ed72eba..c6f16dafda 100644
--- a/esp32c3/src/rmt/sys_conf.rs
+++ b/esp32c3/src/rmt/sys_conf.rs
@@ -98,40 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYS_CONF")
-            .field(
-                "apb_fifo_mask",
-                &format_args!("{}", self.apb_fifo_mask().bit()),
-            )
-            .field(
-                "mem_clk_force_on",
-                &format_args!("{}", self.mem_clk_force_on().bit()),
-            )
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bits()))
-            .field("sclk_active", &format_args!("{}", self.sclk_active().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("apb_fifo_mask", &self.apb_fifo_mask())
+            .field("mem_clk_force_on", &self.mem_clk_force_on())
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_active", &self.sclk_active())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_apb_fifo_mask."]
     #[inline(always)]
diff --git a/esp32c3/src/rmt/tx_sim.rs b/esp32c3/src/rmt/tx_sim.rs
index c04e29009d..2894f4c58f 100644
--- a/esp32c3/src/rmt/tx_sim.rs
+++ b/esp32c3/src/rmt/tx_sim.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_SIM")
-            .field("tx_sim_ch0", &format_args!("{}", self.tx_sim_ch0().bit()))
-            .field("tx_sim_ch1", &format_args!("{}", self.tx_sim_ch1().bit()))
-            .field("tx_sim_en", &format_args!("{}", self.tx_sim_en().bit()))
+            .field("tx_sim_ch0", &self.tx_sim_ch0())
+            .field("tx_sim_ch1", &self.tx_sim_ch1())
+            .field("tx_sim_en", &self.tx_sim_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_SIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_rmt_tx_sim_ch0."]
     #[inline(always)]
diff --git a/esp32c3/src/rng/data.rs b/esp32c3/src/rng/data.rs
index 016046274d..4d812a63aa 100644
--- a/esp32c3/src/rng/data.rs
+++ b/esp32c3/src/rng/data.rs
@@ -6,12 +6,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Random number data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DATA_SPEC;
 impl crate::RegisterSpec for DATA_SPEC {
diff --git a/esp32c3/src/rsa/constant_time.rs b/esp32c3/src/rsa/constant_time.rs
index 1218a4629e..48a70f00c6 100644
--- a/esp32c3/src/rsa/constant_time.rs
+++ b/esp32c3/src/rsa/constant_time.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONSTANT_TIME")
-            .field(
-                "constant_time",
-                &format_args!("{}", self.constant_time().bit()),
-            )
+            .field("constant_time", &self.constant_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONSTANT_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut)."]
     #[inline(always)]
diff --git a/esp32c3/src/rsa/date.rs b/esp32c3/src/rsa/date.rs
index 257c27a30f..2104bd74f2 100644
--- a/esp32c3/src/rsa/date.rs
+++ b/esp32c3/src/rsa/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/rsa/int_ena.rs b/esp32c3/src/rsa/int_ena.rs
index ee0342e223..54ca8aba4a 100644
--- a/esp32c3/src/rsa/int_ena.rs
+++ b/esp32c3/src/rsa/int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("int_ena", &format_args!("{}", self.int_ena().bit()))
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default)."]
     #[inline(always)]
diff --git a/esp32c3/src/rsa/m_mem.rs b/esp32c3/src/rsa/m_mem.rs
index 88b032f702..c11e96b5b6 100644
--- a/esp32c3/src/rsa/m_mem.rs
+++ b/esp32c3/src/rsa/m_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct M_MEM_SPEC;
diff --git a/esp32c3/src/rsa/m_prime.rs b/esp32c3/src/rsa/m_prime.rs
index dd91ab2b36..7dced3affe 100644
--- a/esp32c3/src/rsa/m_prime.rs
+++ b/esp32c3/src/rsa/m_prime.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("M_PRIME")
-            .field("m_prime", &format_args!("{}", self.m_prime().bits()))
+            .field("m_prime", &self.m_prime())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_PRIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits stores m'"]
     #[inline(always)]
diff --git a/esp32c3/src/rsa/mode.rs b/esp32c3/src/rsa/mode.rs
index 9d2802c4ed..96daa5a1d3 100644
--- a/esp32c3/src/rsa/mode.rs
+++ b/esp32c3/src/rsa/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/rsa/query_clean.rs b/esp32c3/src/rsa/query_clean.rs
index cf0e470a9d..5aa0a3e027 100644
--- a/esp32c3/src/rsa/query_clean.rs
+++ b/esp32c3/src/rsa/query_clean.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_CLEAN")
-            .field("query_clean", &format_args!("{}", self.query_clean().bit()))
+            .field("query_clean", &self.query_clean())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_CLEAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RSA query clean register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_clean::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_CLEAN_SPEC;
 impl crate::RegisterSpec for QUERY_CLEAN_SPEC {
diff --git a/esp32c3/src/rsa/query_idle.rs b/esp32c3/src/rsa/query_idle.rs
index 77327c1e08..7daf803404 100644
--- a/esp32c3/src/rsa/query_idle.rs
+++ b/esp32c3/src/rsa/query_idle.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_IDLE")
-            .field("query_idle", &format_args!("{}", self.query_idle().bit()))
+            .field("query_idle", &self.query_idle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_IDLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RSA query idle register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_idle::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_IDLE_SPEC;
 impl crate::RegisterSpec for QUERY_IDLE_SPEC {
diff --git a/esp32c3/src/rsa/search_enable.rs b/esp32c3/src/rsa/search_enable.rs
index c6b830fb9d..06926facc7 100644
--- a/esp32c3/src/rsa/search_enable.rs
+++ b/esp32c3/src/rsa/search_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEARCH_ENABLE")
-            .field(
-                "search_enable",
-                &format_args!("{}", self.search_enable().bit()),
-            )
+            .field("search_enable", &self.search_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEARCH_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS."]
     #[inline(always)]
diff --git a/esp32c3/src/rsa/search_pos.rs b/esp32c3/src/rsa/search_pos.rs
index ba9c95915e..829c6fd704 100644
--- a/esp32c3/src/rsa/search_pos.rs
+++ b/esp32c3/src/rsa/search_pos.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEARCH_POS")
-            .field("search_pos", &format_args!("{}", self.search_pos().bits()))
+            .field("search_pos", &self.search_pos())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEARCH_POS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high."]
     #[inline(always)]
diff --git a/esp32c3/src/rsa/x_mem.rs b/esp32c3/src/rsa/x_mem.rs
index 1b86313bff..f13f895113 100644
--- a/esp32c3/src/rsa/x_mem.rs
+++ b/esp32c3/src/rsa/x_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<X_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores X\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`x_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`x_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct X_MEM_SPEC;
diff --git a/esp32c3/src/rsa/y_mem.rs b/esp32c3/src/rsa/y_mem.rs
index a4cf622a6e..608abec954 100644
--- a/esp32c3/src/rsa/y_mem.rs
+++ b/esp32c3/src/rsa/y_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Y_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores Y\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Y_MEM_SPEC;
diff --git a/esp32c3/src/rsa/z_mem.rs b/esp32c3/src/rsa/z_mem.rs
index b590e91783..0e9e81e6de 100644
--- a/esp32c3/src/rsa/z_mem.rs
+++ b/esp32c3/src/rsa/z_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Z_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Z_MEM_SPEC;
diff --git a/esp32c3/src/rtc_cntl/ana_conf.rs b/esp32c3/src/rtc_cntl/ana_conf.rs
index 2f9547681c..d344aaf0e1 100644
--- a/esp32c3/src/rtc_cntl/ana_conf.rs
+++ b/esp32c3/src/rtc_cntl/ana_conf.rs
@@ -116,51 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ANA_CONF")
-            .field(
-                "reset_por_force_pd",
-                &format_args!("{}", self.reset_por_force_pd().bit()),
-            )
-            .field(
-                "reset_por_force_pu",
-                &format_args!("{}", self.reset_por_force_pu().bit()),
-            )
-            .field(
-                "glitch_rst_en",
-                &format_args!("{}", self.glitch_rst_en().bit()),
-            )
-            .field("sar_i2c_pu", &format_args!("{}", self.sar_i2c_pu().bit()))
-            .field(
-                "plla_force_pd",
-                &format_args!("{}", self.plla_force_pd().bit()),
-            )
-            .field(
-                "plla_force_pu",
-                &format_args!("{}", self.plla_force_pu().bit()),
-            )
-            .field(
-                "bbpll_cal_slp_start",
-                &format_args!("{}", self.bbpll_cal_slp_start().bit()),
-            )
-            .field("pvtmon_pu", &format_args!("{}", self.pvtmon_pu().bit()))
-            .field("txrf_i2c_pu", &format_args!("{}", self.txrf_i2c_pu().bit()))
-            .field(
-                "rfrx_pbus_pu",
-                &format_args!("{}", self.rfrx_pbus_pu().bit()),
-            )
-            .field(
-                "ckgen_i2c_pu",
-                &format_args!("{}", self.ckgen_i2c_pu().bit()),
-            )
-            .field("pll_i2c_pu", &format_args!("{}", self.pll_i2c_pu().bit()))
+            .field("reset_por_force_pd", &self.reset_por_force_pd())
+            .field("reset_por_force_pu", &self.reset_por_force_pu())
+            .field("glitch_rst_en", &self.glitch_rst_en())
+            .field("sar_i2c_pu", &self.sar_i2c_pu())
+            .field("plla_force_pd", &self.plla_force_pd())
+            .field("plla_force_pu", &self.plla_force_pu())
+            .field("bbpll_cal_slp_start", &self.bbpll_cal_slp_start())
+            .field("pvtmon_pu", &self.pvtmon_pu())
+            .field("txrf_i2c_pu", &self.txrf_i2c_pu())
+            .field("rfrx_pbus_pu", &self.rfrx_pbus_pu())
+            .field("ckgen_i2c_pu", &self.ckgen_i2c_pu())
+            .field("pll_i2c_pu", &self.pll_i2c_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ANA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - force no bypass i2c power on reset"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/bias_conf.rs b/esp32c3/src/rtc_cntl/bias_conf.rs
index 5661a00aa3..75d7ca6b9c 100644
--- a/esp32c3/src/rtc_cntl/bias_conf.rs
+++ b/esp32c3/src/rtc_cntl/bias_conf.rs
@@ -116,63 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BIAS_CONF")
-            .field(
-                "dg_vdd_drv_b_slp",
-                &format_args!("{}", self.dg_vdd_drv_b_slp().bits()),
-            )
-            .field(
-                "dg_vdd_drv_b_slp_en",
-                &format_args!("{}", self.dg_vdd_drv_b_slp_en().bit()),
-            )
-            .field(
-                "bias_buf_idle",
-                &format_args!("{}", self.bias_buf_idle().bit()),
-            )
-            .field(
-                "bias_buf_wake",
-                &format_args!("{}", self.bias_buf_wake().bit()),
-            )
-            .field(
-                "bias_buf_deep_slp",
-                &format_args!("{}", self.bias_buf_deep_slp().bit()),
-            )
-            .field(
-                "bias_buf_monitor",
-                &format_args!("{}", self.bias_buf_monitor().bit()),
-            )
-            .field(
-                "pd_cur_deep_slp",
-                &format_args!("{}", self.pd_cur_deep_slp().bit()),
-            )
-            .field(
-                "pd_cur_monitor",
-                &format_args!("{}", self.pd_cur_monitor().bit()),
-            )
-            .field(
-                "bias_sleep_deep_slp",
-                &format_args!("{}", self.bias_sleep_deep_slp().bit()),
-            )
-            .field(
-                "bias_sleep_monitor",
-                &format_args!("{}", self.bias_sleep_monitor().bit()),
-            )
-            .field(
-                "dbg_atten_deep_slp",
-                &format_args!("{}", self.dbg_atten_deep_slp().bits()),
-            )
-            .field(
-                "dbg_atten_monitor",
-                &format_args!("{}", self.dbg_atten_monitor().bits()),
-            )
+            .field("dg_vdd_drv_b_slp", &self.dg_vdd_drv_b_slp())
+            .field("dg_vdd_drv_b_slp_en", &self.dg_vdd_drv_b_slp_en())
+            .field("bias_buf_idle", &self.bias_buf_idle())
+            .field("bias_buf_wake", &self.bias_buf_wake())
+            .field("bias_buf_deep_slp", &self.bias_buf_deep_slp())
+            .field("bias_buf_monitor", &self.bias_buf_monitor())
+            .field("pd_cur_deep_slp", &self.pd_cur_deep_slp())
+            .field("pd_cur_monitor", &self.pd_cur_monitor())
+            .field("bias_sleep_deep_slp", &self.bias_sleep_deep_slp())
+            .field("bias_sleep_monitor", &self.bias_sleep_monitor())
+            .field("dbg_atten_deep_slp", &self.dbg_atten_deep_slp())
+            .field("dbg_atten_monitor", &self.dbg_atten_monitor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BIAS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/brown_out.rs b/esp32c3/src/rtc_cntl/brown_out.rs
index 3083fb1b3f..5b56873dbe 100644
--- a/esp32c3/src/rtc_cntl/brown_out.rs
+++ b/esp32c3/src/rtc_cntl/brown_out.rs
@@ -89,48 +89,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BROWN_OUT")
-            .field(
-                "brown_out_int_wait",
-                &format_args!("{}", self.brown_out_int_wait().bits()),
-            )
+            .field("brown_out_int_wait", &self.brown_out_int_wait())
             .field(
                 "brown_out_close_flash_ena",
-                &format_args!("{}", self.brown_out_close_flash_ena().bit()),
+                &self.brown_out_close_flash_ena(),
             )
-            .field(
-                "brown_out_pd_rf_ena",
-                &format_args!("{}", self.brown_out_pd_rf_ena().bit()),
-            )
-            .field(
-                "brown_out_rst_wait",
-                &format_args!("{}", self.brown_out_rst_wait().bits()),
-            )
-            .field(
-                "brown_out_rst_ena",
-                &format_args!("{}", self.brown_out_rst_ena().bit()),
-            )
-            .field(
-                "brown_out_rst_sel",
-                &format_args!("{}", self.brown_out_rst_sel().bit()),
-            )
-            .field(
-                "brown_out_ana_rst_en",
-                &format_args!("{}", self.brown_out_ana_rst_en().bit()),
-            )
-            .field(
-                "brown_out_ena",
-                &format_args!("{}", self.brown_out_ena().bit()),
-            )
-            .field("det", &format_args!("{}", self.det().bit()))
+            .field("brown_out_pd_rf_ena", &self.brown_out_pd_rf_ena())
+            .field("brown_out_rst_wait", &self.brown_out_rst_wait())
+            .field("brown_out_rst_ena", &self.brown_out_rst_ena())
+            .field("brown_out_rst_sel", &self.brown_out_rst_sel())
+            .field("brown_out_ana_rst_en", &self.brown_out_ana_rst_en())
+            .field("brown_out_ena", &self.brown_out_ena())
+            .field("det", &self.det())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BROWN_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 4:13 - brown out interrupt wait cycles"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/clk_conf.rs b/esp32c3/src/rtc_cntl/clk_conf.rs
index e2833f5cc7..34d329d80e 100644
--- a/esp32c3/src/rtc_cntl/clk_conf.rs
+++ b/esp32c3/src/rtc_cntl/clk_conf.rs
@@ -179,82 +179,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field(
-                "efuse_clk_force_gating",
-                &format_args!("{}", self.efuse_clk_force_gating().bit()),
-            )
-            .field(
-                "efuse_clk_force_nogating",
-                &format_args!("{}", self.efuse_clk_force_nogating().bit()),
-            )
-            .field(
-                "ck8m_div_sel_vld",
-                &format_args!("{}", self.ck8m_div_sel_vld().bit()),
-            )
-            .field("ck8m_div", &format_args!("{}", self.ck8m_div().bits()))
-            .field("enb_ck8m", &format_args!("{}", self.enb_ck8m().bit()))
-            .field(
-                "enb_ck8m_div",
-                &format_args!("{}", self.enb_ck8m_div().bit()),
-            )
-            .field(
-                "dig_xtal32k_en",
-                &format_args!("{}", self.dig_xtal32k_en().bit()),
-            )
-            .field(
-                "dig_clk8m_d256_en",
-                &format_args!("{}", self.dig_clk8m_d256_en().bit()),
-            )
-            .field(
-                "dig_clk8m_en",
-                &format_args!("{}", self.dig_clk8m_en().bit()),
-            )
-            .field(
-                "ck8m_div_sel",
-                &format_args!("{}", self.ck8m_div_sel().bits()),
-            )
-            .field(
-                "xtal_force_nogating",
-                &format_args!("{}", self.xtal_force_nogating().bit()),
-            )
-            .field(
-                "ck8m_force_nogating",
-                &format_args!("{}", self.ck8m_force_nogating().bit()),
-            )
-            .field("ck8m_dfreq", &format_args!("{}", self.ck8m_dfreq().bits()))
-            .field(
-                "ck8m_force_pd",
-                &format_args!("{}", self.ck8m_force_pd().bit()),
-            )
-            .field(
-                "ck8m_force_pu",
-                &format_args!("{}", self.ck8m_force_pu().bit()),
-            )
-            .field(
-                "xtal_global_force_gating",
-                &format_args!("{}", self.xtal_global_force_gating().bit()),
-            )
+            .field("efuse_clk_force_gating", &self.efuse_clk_force_gating())
+            .field("efuse_clk_force_nogating", &self.efuse_clk_force_nogating())
+            .field("ck8m_div_sel_vld", &self.ck8m_div_sel_vld())
+            .field("ck8m_div", &self.ck8m_div())
+            .field("enb_ck8m", &self.enb_ck8m())
+            .field("enb_ck8m_div", &self.enb_ck8m_div())
+            .field("dig_xtal32k_en", &self.dig_xtal32k_en())
+            .field("dig_clk8m_d256_en", &self.dig_clk8m_d256_en())
+            .field("dig_clk8m_en", &self.dig_clk8m_en())
+            .field("ck8m_div_sel", &self.ck8m_div_sel())
+            .field("xtal_force_nogating", &self.xtal_force_nogating())
+            .field("ck8m_force_nogating", &self.ck8m_force_nogating())
+            .field("ck8m_dfreq", &self.ck8m_dfreq())
+            .field("ck8m_force_pd", &self.ck8m_force_pd())
+            .field("ck8m_force_pu", &self.ck8m_force_pu())
+            .field("xtal_global_force_gating", &self.xtal_global_force_gating())
             .field(
                 "xtal_global_force_nogating",
-                &format_args!("{}", self.xtal_global_force_nogating().bit()),
-            )
-            .field(
-                "fast_clk_rtc_sel",
-                &format_args!("{}", self.fast_clk_rtc_sel().bit()),
-            )
-            .field(
-                "ana_clk_rtc_sel",
-                &format_args!("{}", self.ana_clk_rtc_sel().bits()),
+                &self.xtal_global_force_nogating(),
             )
+            .field("fast_clk_rtc_sel", &self.fast_clk_rtc_sel())
+            .field("ana_clk_rtc_sel", &self.ana_clk_rtc_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - efuse_clk_force_gating"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/cpu_period_conf.rs b/esp32c3/src/rtc_cntl/cpu_period_conf.rs
index a638a6d7ad..f2f3f74e2e 100644
--- a/esp32c3/src/rtc_cntl/cpu_period_conf.rs
+++ b/esp32c3/src/rtc_cntl/cpu_period_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERIOD_CONF")
-            .field("cpusel_conf", &format_args!("{}", self.cpusel_conf().bit()))
-            .field(
-                "cpuperiod_sel",
-                &format_args!("{}", self.cpuperiod_sel().bits()),
-            )
+            .field("cpusel_conf", &self.cpusel_conf())
+            .field("cpuperiod_sel", &self.cpuperiod_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERIOD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 29 - CPU sel option"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/date.rs b/esp32c3/src/rtc_cntl/date.rs
index 65dd634327..10f17aad5a 100644
--- a/esp32c3/src/rtc_cntl/date.rs
+++ b/esp32c3/src/rtc_cntl/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/rtc_cntl/dbg_map.rs b/esp32c3/src/rtc_cntl/dbg_map.rs
index 274e91cee5..5a5faa516b 100644
--- a/esp32c3/src/rtc_cntl/dbg_map.rs
+++ b/esp32c3/src/rtc_cntl/dbg_map.rs
@@ -116,63 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBG_MAP")
-            .field(
-                "gpio_pin5_mux_sel",
-                &format_args!("{}", self.gpio_pin5_mux_sel().bit()),
-            )
-            .field(
-                "gpio_pin4_mux_sel",
-                &format_args!("{}", self.gpio_pin4_mux_sel().bit()),
-            )
-            .field(
-                "gpio_pin3_mux_sel",
-                &format_args!("{}", self.gpio_pin3_mux_sel().bit()),
-            )
-            .field(
-                "gpio_pin2_mux_sel",
-                &format_args!("{}", self.gpio_pin2_mux_sel().bit()),
-            )
-            .field(
-                "gpio_pin1_mux_sel",
-                &format_args!("{}", self.gpio_pin1_mux_sel().bit()),
-            )
-            .field(
-                "gpio_pin0_mux_sel",
-                &format_args!("{}", self.gpio_pin0_mux_sel().bit()),
-            )
-            .field(
-                "gpio_pin5_fun_sel",
-                &format_args!("{}", self.gpio_pin5_fun_sel().bits()),
-            )
-            .field(
-                "gpio_pin4_fun_sel",
-                &format_args!("{}", self.gpio_pin4_fun_sel().bits()),
-            )
-            .field(
-                "gpio_pin3_fun_sel",
-                &format_args!("{}", self.gpio_pin3_fun_sel().bits()),
-            )
-            .field(
-                "gpio_pin2_fun_sel",
-                &format_args!("{}", self.gpio_pin2_fun_sel().bits()),
-            )
-            .field(
-                "gpio_pin1_fun_sel",
-                &format_args!("{}", self.gpio_pin1_fun_sel().bits()),
-            )
-            .field(
-                "gpio_pin0_fun_sel",
-                &format_args!("{}", self.gpio_pin0_fun_sel().bits()),
-            )
+            .field("gpio_pin5_mux_sel", &self.gpio_pin5_mux_sel())
+            .field("gpio_pin4_mux_sel", &self.gpio_pin4_mux_sel())
+            .field("gpio_pin3_mux_sel", &self.gpio_pin3_mux_sel())
+            .field("gpio_pin2_mux_sel", &self.gpio_pin2_mux_sel())
+            .field("gpio_pin1_mux_sel", &self.gpio_pin1_mux_sel())
+            .field("gpio_pin0_mux_sel", &self.gpio_pin0_mux_sel())
+            .field("gpio_pin5_fun_sel", &self.gpio_pin5_fun_sel())
+            .field("gpio_pin4_fun_sel", &self.gpio_pin4_fun_sel())
+            .field("gpio_pin3_fun_sel", &self.gpio_pin3_fun_sel())
+            .field("gpio_pin2_fun_sel", &self.gpio_pin2_fun_sel())
+            .field("gpio_pin1_fun_sel", &self.gpio_pin1_fun_sel())
+            .field("gpio_pin0_fun_sel", &self.gpio_pin0_fun_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBG_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - use for debug"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/dbg_sar_sel.rs b/esp32c3/src/rtc_cntl/dbg_sar_sel.rs
index f23894f86e..24c250d6ca 100644
--- a/esp32c3/src/rtc_cntl/dbg_sar_sel.rs
+++ b/esp32c3/src/rtc_cntl/dbg_sar_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBG_SAR_SEL")
-            .field(
-                "sar_debug_sel",
-                &format_args!("{}", self.sar_debug_sel().bits()),
-            )
+            .field("sar_debug_sel", &self.sar_debug_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBG_SAR_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 27:31 - use for debug"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/dbg_sel.rs b/esp32c3/src/rtc_cntl/dbg_sel.rs
index 5a3dce230a..eb26e4746f 100644
--- a/esp32c3/src/rtc_cntl/dbg_sel.rs
+++ b/esp32c3/src/rtc_cntl/dbg_sel.rs
@@ -71,28 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBG_SEL")
-            .field(
-                "debug_12m_no_gating",
-                &format_args!("{}", self.debug_12m_no_gating().bit()),
-            )
-            .field(
-                "debug_bit_sel",
-                &format_args!("{}", self.debug_bit_sel().bits()),
-            )
-            .field("debug_sel0", &format_args!("{}", self.debug_sel0().bits()))
-            .field("debug_sel1", &format_args!("{}", self.debug_sel1().bits()))
-            .field("debug_sel2", &format_args!("{}", self.debug_sel2().bits()))
-            .field("debug_sel3", &format_args!("{}", self.debug_sel3().bits()))
-            .field("debug_sel4", &format_args!("{}", self.debug_sel4().bits()))
+            .field("debug_12m_no_gating", &self.debug_12m_no_gating())
+            .field("debug_bit_sel", &self.debug_bit_sel())
+            .field("debug_sel0", &self.debug_sel0())
+            .field("debug_sel1", &self.debug_sel1())
+            .field("debug_sel2", &self.debug_sel2())
+            .field("debug_sel3", &self.debug_sel3())
+            .field("debug_sel4", &self.debug_sel4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBG_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - use for debug"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/diag0.rs b/esp32c3/src/rtc_cntl/diag0.rs
index b3fe246bbc..e370f75913 100644
--- a/esp32c3/src/rtc_cntl/diag0.rs
+++ b/esp32c3/src/rtc_cntl/diag0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIAG0")
-            .field(
-                "low_power_diag1",
-                &format_args!("{}", self.low_power_diag1().bits()),
-            )
+            .field("low_power_diag1", &self.low_power_diag1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIAG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rtc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diag0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIAG0_SPEC;
 impl crate::RegisterSpec for DIAG0_SPEC {
diff --git a/esp32c3/src/rtc_cntl/dig_iso.rs b/esp32c3/src/rtc_cntl/dig_iso.rs
index 5f4c06e0cf..a576b38760 100644
--- a/esp32c3/src/rtc_cntl/dig_iso.rs
+++ b/esp32c3/src/rtc_cntl/dig_iso.rs
@@ -170,81 +170,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIG_ISO")
-            .field("force_off", &format_args!("{}", self.force_off().bit()))
-            .field("force_on", &format_args!("{}", self.force_on().bit()))
-            .field(
-                "dg_pad_autohold",
-                &format_args!("{}", self.dg_pad_autohold().bit()),
-            )
-            .field(
-                "dg_pad_autohold_en",
-                &format_args!("{}", self.dg_pad_autohold_en().bit()),
-            )
-            .field(
-                "dg_pad_force_noiso",
-                &format_args!("{}", self.dg_pad_force_noiso().bit()),
-            )
-            .field(
-                "dg_pad_force_iso",
-                &format_args!("{}", self.dg_pad_force_iso().bit()),
-            )
-            .field(
-                "dg_pad_force_unhold",
-                &format_args!("{}", self.dg_pad_force_unhold().bit()),
-            )
-            .field(
-                "dg_pad_force_hold",
-                &format_args!("{}", self.dg_pad_force_hold().bit()),
-            )
-            .field(
-                "bt_force_iso",
-                &format_args!("{}", self.bt_force_iso().bit()),
-            )
-            .field(
-                "bt_force_noiso",
-                &format_args!("{}", self.bt_force_noiso().bit()),
-            )
-            .field(
-                "dg_peri_force_iso",
-                &format_args!("{}", self.dg_peri_force_iso().bit()),
-            )
-            .field(
-                "dg_peri_force_noiso",
-                &format_args!("{}", self.dg_peri_force_noiso().bit()),
-            )
-            .field(
-                "cpu_top_force_iso",
-                &format_args!("{}", self.cpu_top_force_iso().bit()),
-            )
-            .field(
-                "cpu_top_force_noiso",
-                &format_args!("{}", self.cpu_top_force_noiso().bit()),
-            )
-            .field(
-                "wifi_force_iso",
-                &format_args!("{}", self.wifi_force_iso().bit()),
-            )
-            .field(
-                "wifi_force_noiso",
-                &format_args!("{}", self.wifi_force_noiso().bit()),
-            )
-            .field(
-                "dg_wrap_force_iso",
-                &format_args!("{}", self.dg_wrap_force_iso().bit()),
-            )
-            .field(
-                "dg_wrap_force_noiso",
-                &format_args!("{}", self.dg_wrap_force_noiso().bit()),
-            )
+            .field("force_off", &self.force_off())
+            .field("force_on", &self.force_on())
+            .field("dg_pad_autohold", &self.dg_pad_autohold())
+            .field("dg_pad_autohold_en", &self.dg_pad_autohold_en())
+            .field("dg_pad_force_noiso", &self.dg_pad_force_noiso())
+            .field("dg_pad_force_iso", &self.dg_pad_force_iso())
+            .field("dg_pad_force_unhold", &self.dg_pad_force_unhold())
+            .field("dg_pad_force_hold", &self.dg_pad_force_hold())
+            .field("bt_force_iso", &self.bt_force_iso())
+            .field("bt_force_noiso", &self.bt_force_noiso())
+            .field("dg_peri_force_iso", &self.dg_peri_force_iso())
+            .field("dg_peri_force_noiso", &self.dg_peri_force_noiso())
+            .field("cpu_top_force_iso", &self.cpu_top_force_iso())
+            .field("cpu_top_force_noiso", &self.cpu_top_force_noiso())
+            .field("wifi_force_iso", &self.wifi_force_iso())
+            .field("wifi_force_noiso", &self.wifi_force_noiso())
+            .field("dg_wrap_force_iso", &self.dg_wrap_force_iso())
+            .field("dg_wrap_force_noiso", &self.dg_wrap_force_noiso())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIG_ISO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - DIG_ISO force off"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/dig_pad_hold.rs b/esp32c3/src/rtc_cntl/dig_pad_hold.rs
index eb47581ae1..e4ae6a135c 100644
--- a/esp32c3/src/rtc_cntl/dig_pad_hold.rs
+++ b/esp32c3/src/rtc_cntl/dig_pad_hold.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIG_PAD_HOLD")
-            .field(
-                "dig_pad_hold",
-                &format_args!("{}", self.dig_pad_hold().bits()),
-            )
+            .field("dig_pad_hold", &self.dig_pad_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIG_PAD_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - the configure of digital pad"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/dig_pwc.rs b/esp32c3/src/rtc_cntl/dig_pwc.rs
index 8d54844cc5..2b416c8ce2 100644
--- a/esp32c3/src/rtc_cntl/dig_pwc.rs
+++ b/esp32c3/src/rtc_cntl/dig_pwc.rs
@@ -197,87 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIG_PWC")
-            .field(
-                "vdd_spi_pwr_drv",
-                &format_args!("{}", self.vdd_spi_pwr_drv().bits()),
-            )
-            .field(
-                "vdd_spi_pwr_force",
-                &format_args!("{}", self.vdd_spi_pwr_force().bit()),
-            )
-            .field(
-                "lslp_mem_force_pd",
-                &format_args!("{}", self.lslp_mem_force_pd().bit()),
-            )
-            .field(
-                "lslp_mem_force_pu",
-                &format_args!("{}", self.lslp_mem_force_pu().bit()),
-            )
-            .field("bt_force_pd", &format_args!("{}", self.bt_force_pd().bit()))
-            .field("bt_force_pu", &format_args!("{}", self.bt_force_pu().bit()))
-            .field(
-                "dg_peri_force_pd",
-                &format_args!("{}", self.dg_peri_force_pd().bit()),
-            )
-            .field(
-                "dg_peri_force_pu",
-                &format_args!("{}", self.dg_peri_force_pu().bit()),
-            )
-            .field(
-                "fastmem_force_lpd",
-                &format_args!("{}", self.fastmem_force_lpd().bit()),
-            )
-            .field(
-                "fastmem_force_lpu",
-                &format_args!("{}", self.fastmem_force_lpu().bit()),
-            )
-            .field(
-                "wifi_force_pd",
-                &format_args!("{}", self.wifi_force_pd().bit()),
-            )
-            .field(
-                "wifi_force_pu",
-                &format_args!("{}", self.wifi_force_pu().bit()),
-            )
-            .field(
-                "dg_wrap_force_pd",
-                &format_args!("{}", self.dg_wrap_force_pd().bit()),
-            )
-            .field(
-                "dg_wrap_force_pu",
-                &format_args!("{}", self.dg_wrap_force_pu().bit()),
-            )
-            .field(
-                "cpu_top_force_pd",
-                &format_args!("{}", self.cpu_top_force_pd().bit()),
-            )
-            .field(
-                "cpu_top_force_pu",
-                &format_args!("{}", self.cpu_top_force_pu().bit()),
-            )
-            .field("bt_pd_en", &format_args!("{}", self.bt_pd_en().bit()))
-            .field(
-                "dg_peri_pd_en",
-                &format_args!("{}", self.dg_peri_pd_en().bit()),
-            )
-            .field(
-                "cpu_top_pd_en",
-                &format_args!("{}", self.cpu_top_pd_en().bit()),
-            )
-            .field("wifi_pd_en", &format_args!("{}", self.wifi_pd_en().bit()))
-            .field(
-                "dg_wrap_pd_en",
-                &format_args!("{}", self.dg_wrap_pd_en().bit()),
-            )
+            .field("vdd_spi_pwr_drv", &self.vdd_spi_pwr_drv())
+            .field("vdd_spi_pwr_force", &self.vdd_spi_pwr_force())
+            .field("lslp_mem_force_pd", &self.lslp_mem_force_pd())
+            .field("lslp_mem_force_pu", &self.lslp_mem_force_pu())
+            .field("bt_force_pd", &self.bt_force_pd())
+            .field("bt_force_pu", &self.bt_force_pu())
+            .field("dg_peri_force_pd", &self.dg_peri_force_pd())
+            .field("dg_peri_force_pu", &self.dg_peri_force_pu())
+            .field("fastmem_force_lpd", &self.fastmem_force_lpd())
+            .field("fastmem_force_lpu", &self.fastmem_force_lpu())
+            .field("wifi_force_pd", &self.wifi_force_pd())
+            .field("wifi_force_pu", &self.wifi_force_pu())
+            .field("dg_wrap_force_pd", &self.dg_wrap_force_pd())
+            .field("dg_wrap_force_pu", &self.dg_wrap_force_pu())
+            .field("cpu_top_force_pd", &self.cpu_top_force_pd())
+            .field("cpu_top_force_pu", &self.cpu_top_force_pu())
+            .field("bt_pd_en", &self.bt_pd_en())
+            .field("dg_peri_pd_en", &self.dg_peri_pd_en())
+            .field("cpu_top_pd_en", &self.cpu_top_pd_en())
+            .field("wifi_pd_en", &self.wifi_pd_en())
+            .field("dg_wrap_pd_en", &self.dg_wrap_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIG_PWC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - vdd_spi drv's software value"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/ext_wakeup_conf.rs b/esp32c3/src/rtc_cntl/ext_wakeup_conf.rs
index 6a668840c8..3e47a0dccd 100644
--- a/esp32c3/src/rtc_cntl/ext_wakeup_conf.rs
+++ b/esp32c3/src/rtc_cntl/ext_wakeup_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP_CONF")
-            .field(
-                "gpio_wakeup_filter",
-                &format_args!("{}", self.gpio_wakeup_filter().bit()),
-            )
+            .field("gpio_wakeup_filter", &self.gpio_wakeup_filter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - enable filter for gpio wakeup event"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/ext_xtl_conf.rs b/esp32c3/src/rtc_cntl/ext_xtl_conf.rs
index dd7be78e8c..1231dacfff 100644
--- a/esp32c3/src/rtc_cntl/ext_xtl_conf.rs
+++ b/esp32c3/src/rtc_cntl/ext_xtl_conf.rs
@@ -168,84 +168,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_XTL_CONF")
-            .field(
-                "xtal32k_wdt_en",
-                &format_args!("{}", self.xtal32k_wdt_en().bit()),
-            )
-            .field(
-                "xtal32k_wdt_clk_fo",
-                &format_args!("{}", self.xtal32k_wdt_clk_fo().bit()),
-            )
-            .field(
-                "xtal32k_wdt_reset",
-                &format_args!("{}", self.xtal32k_wdt_reset().bit()),
-            )
-            .field(
-                "xtal32k_ext_clk_fo",
-                &format_args!("{}", self.xtal32k_ext_clk_fo().bit()),
-            )
-            .field(
-                "xtal32k_auto_backup",
-                &format_args!("{}", self.xtal32k_auto_backup().bit()),
-            )
-            .field(
-                "xtal32k_auto_restart",
-                &format_args!("{}", self.xtal32k_auto_restart().bit()),
-            )
-            .field(
-                "xtal32k_auto_return",
-                &format_args!("{}", self.xtal32k_auto_return().bit()),
-            )
-            .field(
-                "xtal32k_xpd_force",
-                &format_args!("{}", self.xtal32k_xpd_force().bit()),
-            )
-            .field(
-                "enckinit_xtal_32k",
-                &format_args!("{}", self.enckinit_xtal_32k().bit()),
-            )
-            .field(
-                "dbuf_xtal_32k",
-                &format_args!("{}", self.dbuf_xtal_32k().bit()),
-            )
-            .field(
-                "dgm_xtal_32k",
-                &format_args!("{}", self.dgm_xtal_32k().bits()),
-            )
-            .field(
-                "dres_xtal_32k",
-                &format_args!("{}", self.dres_xtal_32k().bits()),
-            )
-            .field(
-                "xpd_xtal_32k",
-                &format_args!("{}", self.xpd_xtal_32k().bit()),
-            )
-            .field(
-                "dac_xtal_32k",
-                &format_args!("{}", self.dac_xtal_32k().bits()),
-            )
-            .field("wdt_state", &format_args!("{}", self.wdt_state().bits()))
-            .field(
-                "xtal32k_gpio_sel",
-                &format_args!("{}", self.xtal32k_gpio_sel().bit()),
-            )
-            .field(
-                "xtl_ext_ctr_lv",
-                &format_args!("{}", self.xtl_ext_ctr_lv().bit()),
-            )
-            .field(
-                "xtl_ext_ctr_en",
-                &format_args!("{}", self.xtl_ext_ctr_en().bit()),
-            )
+            .field("xtal32k_wdt_en", &self.xtal32k_wdt_en())
+            .field("xtal32k_wdt_clk_fo", &self.xtal32k_wdt_clk_fo())
+            .field("xtal32k_wdt_reset", &self.xtal32k_wdt_reset())
+            .field("xtal32k_ext_clk_fo", &self.xtal32k_ext_clk_fo())
+            .field("xtal32k_auto_backup", &self.xtal32k_auto_backup())
+            .field("xtal32k_auto_restart", &self.xtal32k_auto_restart())
+            .field("xtal32k_auto_return", &self.xtal32k_auto_return())
+            .field("xtal32k_xpd_force", &self.xtal32k_xpd_force())
+            .field("enckinit_xtal_32k", &self.enckinit_xtal_32k())
+            .field("dbuf_xtal_32k", &self.dbuf_xtal_32k())
+            .field("dgm_xtal_32k", &self.dgm_xtal_32k())
+            .field("dres_xtal_32k", &self.dres_xtal_32k())
+            .field("xpd_xtal_32k", &self.xpd_xtal_32k())
+            .field("dac_xtal_32k", &self.dac_xtal_32k())
+            .field("wdt_state", &self.wdt_state())
+            .field("xtal32k_gpio_sel", &self.xtal32k_gpio_sel())
+            .field("xtl_ext_ctr_lv", &self.xtl_ext_ctr_lv())
+            .field("xtl_ext_ctr_en", &self.xtl_ext_ctr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_XTL_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - xtal 32k watch dog enable"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/fib_sel.rs b/esp32c3/src/rtc_cntl/fib_sel.rs
index 43374c0cc3..12e9648494 100644
--- a/esp32c3/src/rtc_cntl/fib_sel.rs
+++ b/esp32c3/src/rtc_cntl/fib_sel.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIB_SEL")
-            .field("fib_sel", &format_args!("{}", self.fib_sel().bits()))
+            .field("fib_sel", &self.fib_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIB_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - select use analog fib signal"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/gpio_wakeup.rs b/esp32c3/src/rtc_cntl/gpio_wakeup.rs
index fdd308839f..49df5d1da1 100644
--- a/esp32c3/src/rtc_cntl/gpio_wakeup.rs
+++ b/esp32c3/src/rtc_cntl/gpio_wakeup.rs
@@ -141,75 +141,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_WAKEUP")
-            .field(
-                "gpio_wakeup_status",
-                &format_args!("{}", self.gpio_wakeup_status().bits()),
-            )
-            .field(
-                "gpio_wakeup_status_clr",
-                &format_args!("{}", self.gpio_wakeup_status_clr().bit()),
-            )
-            .field(
-                "gpio_pin_clk_gate",
-                &format_args!("{}", self.gpio_pin_clk_gate().bit()),
-            )
-            .field(
-                "gpio_pin5_int_type",
-                &format_args!("{}", self.gpio_pin5_int_type().bits()),
-            )
-            .field(
-                "gpio_pin4_int_type",
-                &format_args!("{}", self.gpio_pin4_int_type().bits()),
-            )
-            .field(
-                "gpio_pin3_int_type",
-                &format_args!("{}", self.gpio_pin3_int_type().bits()),
-            )
-            .field(
-                "gpio_pin2_int_type",
-                &format_args!("{}", self.gpio_pin2_int_type().bits()),
-            )
-            .field(
-                "gpio_pin1_int_type",
-                &format_args!("{}", self.gpio_pin1_int_type().bits()),
-            )
-            .field(
-                "gpio_pin0_int_type",
-                &format_args!("{}", self.gpio_pin0_int_type().bits()),
-            )
-            .field(
-                "gpio_pin5_wakeup_enable",
-                &format_args!("{}", self.gpio_pin5_wakeup_enable().bit()),
-            )
-            .field(
-                "gpio_pin4_wakeup_enable",
-                &format_args!("{}", self.gpio_pin4_wakeup_enable().bit()),
-            )
-            .field(
-                "gpio_pin3_wakeup_enable",
-                &format_args!("{}", self.gpio_pin3_wakeup_enable().bit()),
-            )
-            .field(
-                "gpio_pin2_wakeup_enable",
-                &format_args!("{}", self.gpio_pin2_wakeup_enable().bit()),
-            )
-            .field(
-                "gpio_pin1_wakeup_enable",
-                &format_args!("{}", self.gpio_pin1_wakeup_enable().bit()),
-            )
-            .field(
-                "gpio_pin0_wakeup_enable",
-                &format_args!("{}", self.gpio_pin0_wakeup_enable().bit()),
-            )
+            .field("gpio_wakeup_status", &self.gpio_wakeup_status())
+            .field("gpio_wakeup_status_clr", &self.gpio_wakeup_status_clr())
+            .field("gpio_pin_clk_gate", &self.gpio_pin_clk_gate())
+            .field("gpio_pin5_int_type", &self.gpio_pin5_int_type())
+            .field("gpio_pin4_int_type", &self.gpio_pin4_int_type())
+            .field("gpio_pin3_int_type", &self.gpio_pin3_int_type())
+            .field("gpio_pin2_int_type", &self.gpio_pin2_int_type())
+            .field("gpio_pin1_int_type", &self.gpio_pin1_int_type())
+            .field("gpio_pin0_int_type", &self.gpio_pin0_int_type())
+            .field("gpio_pin5_wakeup_enable", &self.gpio_pin5_wakeup_enable())
+            .field("gpio_pin4_wakeup_enable", &self.gpio_pin4_wakeup_enable())
+            .field("gpio_pin3_wakeup_enable", &self.gpio_pin3_wakeup_enable())
+            .field("gpio_pin2_wakeup_enable", &self.gpio_pin2_wakeup_enable())
+            .field("gpio_pin1_wakeup_enable", &self.gpio_pin1_wakeup_enable())
+            .field("gpio_pin0_wakeup_enable", &self.gpio_pin0_wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_WAKEUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - clear rtc gpio wakeup flag"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/int_ena.rs b/esp32c3/src/rtc_cntl/int_ena.rs
index 42009c6bef..cd1f54e355 100644
--- a/esp32c3/src/rtc_cntl/int_ena.rs
+++ b/esp32c3/src/rtc_cntl/int_ena.rs
@@ -89,27 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
-            .field("swd", &format_args!("{}", self.swd().bit()))
-            .field(
-                "xtal32k_dead",
-                &format_args!("{}", self.xtal32k_dead().bit()),
-            )
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("bbpll_cal", &format_args!("{}", self.bbpll_cal().bit()))
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("wdt", &self.wdt())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("swd", &self.swd())
+            .field("xtal32k_dead", &self.xtal32k_dead())
+            .field("glitch_det", &self.glitch_det())
+            .field("bbpll_cal", &self.bbpll_cal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable sleep wakeup interrupt"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/int_raw.rs b/esp32c3/src/rtc_cntl/int_raw.rs
index bc61c426c4..e618da94cb 100644
--- a/esp32c3/src/rtc_cntl/int_raw.rs
+++ b/esp32c3/src/rtc_cntl/int_raw.rs
@@ -69,27 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
-            .field("swd", &format_args!("{}", self.swd().bit()))
-            .field(
-                "xtal32k_dead",
-                &format_args!("{}", self.xtal32k_dead().bit()),
-            )
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("bbpll_cal", &format_args!("{}", self.bbpll_cal().bit()))
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("wdt", &self.wdt())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("swd", &self.swd())
+            .field("xtal32k_dead", &self.xtal32k_dead())
+            .field("glitch_det", &self.glitch_det())
+            .field("bbpll_cal", &self.bbpll_cal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rtc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32c3/src/rtc_cntl/int_st.rs b/esp32c3/src/rtc_cntl/int_st.rs
index 42d402a3aa..23fcd43b4e 100644
--- a/esp32c3/src/rtc_cntl/int_st.rs
+++ b/esp32c3/src/rtc_cntl/int_st.rs
@@ -69,27 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
-            .field("swd", &format_args!("{}", self.swd().bit()))
-            .field(
-                "xtal32k_dead",
-                &format_args!("{}", self.xtal32k_dead().bit()),
-            )
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("bbpll_cal", &format_args!("{}", self.bbpll_cal().bit()))
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("wdt", &self.wdt())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("swd", &self.swd())
+            .field("xtal32k_dead", &self.xtal32k_dead())
+            .field("glitch_det", &self.glitch_det())
+            .field("bbpll_cal", &self.bbpll_cal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rtc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c3/src/rtc_cntl/low_power_st.rs b/esp32c3/src/rtc_cntl/low_power_st.rs
index 39a9ddd64d..d2e60fd582 100644
--- a/esp32c3/src/rtc_cntl/low_power_st.rs
+++ b/esp32c3/src/rtc_cntl/low_power_st.rs
@@ -202,106 +202,37 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOW_POWER_ST")
-            .field("xpd_rom0", &format_args!("{}", self.xpd_rom0().bit()))
-            .field(
-                "xpd_dig_dcdc",
-                &format_args!("{}", self.xpd_dig_dcdc().bit()),
-            )
-            .field("peri_iso", &format_args!("{}", self.peri_iso().bit()))
-            .field(
-                "xpd_rtc_peri",
-                &format_args!("{}", self.xpd_rtc_peri().bit()),
-            )
-            .field("wifi_iso", &format_args!("{}", self.wifi_iso().bit()))
-            .field("xpd_wifi", &format_args!("{}", self.xpd_wifi().bit()))
-            .field("dig_iso", &format_args!("{}", self.dig_iso().bit()))
-            .field("xpd_dig", &format_args!("{}", self.xpd_dig().bit()))
-            .field(
-                "touch_state_start",
-                &format_args!("{}", self.touch_state_start().bit()),
-            )
-            .field(
-                "touch_state_switch",
-                &format_args!("{}", self.touch_state_switch().bit()),
-            )
-            .field(
-                "touch_state_slp",
-                &format_args!("{}", self.touch_state_slp().bit()),
-            )
-            .field(
-                "touch_state_done",
-                &format_args!("{}", self.touch_state_done().bit()),
-            )
-            .field(
-                "cocpu_state_start",
-                &format_args!("{}", self.cocpu_state_start().bit()),
-            )
-            .field(
-                "cocpu_state_switch",
-                &format_args!("{}", self.cocpu_state_switch().bit()),
-            )
-            .field(
-                "cocpu_state_slp",
-                &format_args!("{}", self.cocpu_state_slp().bit()),
-            )
-            .field(
-                "cocpu_state_done",
-                &format_args!("{}", self.cocpu_state_done().bit()),
-            )
-            .field(
-                "main_state_xtal_iso",
-                &format_args!("{}", self.main_state_xtal_iso().bit()),
-            )
-            .field(
-                "main_state_pll_on",
-                &format_args!("{}", self.main_state_pll_on().bit()),
-            )
-            .field(
-                "rdy_for_wakeup",
-                &format_args!("{}", self.rdy_for_wakeup().bit()),
-            )
-            .field(
-                "main_state_wait_end",
-                &format_args!("{}", self.main_state_wait_end().bit()),
-            )
-            .field(
-                "in_wakeup_state",
-                &format_args!("{}", self.in_wakeup_state().bit()),
-            )
-            .field(
-                "in_low_power_state",
-                &format_args!("{}", self.in_low_power_state().bit()),
-            )
-            .field(
-                "main_state_in_wait_8m",
-                &format_args!("{}", self.main_state_in_wait_8m().bit()),
-            )
-            .field(
-                "main_state_in_wait_pll",
-                &format_args!("{}", self.main_state_in_wait_pll().bit()),
-            )
-            .field(
-                "main_state_in_wait_xtl",
-                &format_args!("{}", self.main_state_in_wait_xtl().bit()),
-            )
-            .field(
-                "main_state_in_slp",
-                &format_args!("{}", self.main_state_in_slp().bit()),
-            )
-            .field(
-                "main_state_in_idle",
-                &format_args!("{}", self.main_state_in_idle().bit()),
-            )
-            .field("main_state", &format_args!("{}", self.main_state().bits()))
+            .field("xpd_rom0", &self.xpd_rom0())
+            .field("xpd_dig_dcdc", &self.xpd_dig_dcdc())
+            .field("peri_iso", &self.peri_iso())
+            .field("xpd_rtc_peri", &self.xpd_rtc_peri())
+            .field("wifi_iso", &self.wifi_iso())
+            .field("xpd_wifi", &self.xpd_wifi())
+            .field("dig_iso", &self.dig_iso())
+            .field("xpd_dig", &self.xpd_dig())
+            .field("touch_state_start", &self.touch_state_start())
+            .field("touch_state_switch", &self.touch_state_switch())
+            .field("touch_state_slp", &self.touch_state_slp())
+            .field("touch_state_done", &self.touch_state_done())
+            .field("cocpu_state_start", &self.cocpu_state_start())
+            .field("cocpu_state_switch", &self.cocpu_state_switch())
+            .field("cocpu_state_slp", &self.cocpu_state_slp())
+            .field("cocpu_state_done", &self.cocpu_state_done())
+            .field("main_state_xtal_iso", &self.main_state_xtal_iso())
+            .field("main_state_pll_on", &self.main_state_pll_on())
+            .field("rdy_for_wakeup", &self.rdy_for_wakeup())
+            .field("main_state_wait_end", &self.main_state_wait_end())
+            .field("in_wakeup_state", &self.in_wakeup_state())
+            .field("in_low_power_state", &self.in_low_power_state())
+            .field("main_state_in_wait_8m", &self.main_state_in_wait_8m())
+            .field("main_state_in_wait_pll", &self.main_state_in_wait_pll())
+            .field("main_state_in_wait_xtl", &self.main_state_in_wait_xtl())
+            .field("main_state_in_slp", &self.main_state_in_slp())
+            .field("main_state_in_idle", &self.main_state_in_idle())
+            .field("main_state", &self.main_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOW_POWER_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rtc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`low_power_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOW_POWER_ST_SPEC;
 impl crate::RegisterSpec for LOW_POWER_ST_SPEC {
diff --git a/esp32c3/src/rtc_cntl/option1.rs b/esp32c3/src/rtc_cntl/option1.rs
index fb8b24b88e..2de8aa2666 100644
--- a/esp32c3/src/rtc_cntl/option1.rs
+++ b/esp32c3/src/rtc_cntl/option1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OPTION1")
-            .field(
-                "force_download_boot",
-                &format_args!("{}", self.force_download_boot().bit()),
-            )
+            .field("force_download_boot", &self.force_download_boot())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OPTION1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - force chip entry download mode"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/options0.rs b/esp32c3/src/rtc_cntl/options0.rs
index 264b6c6157..7a26ca0238 100644
--- a/esp32c3/src/rtc_cntl/options0.rs
+++ b/esp32c3/src/rtc_cntl/options0.rs
@@ -194,95 +194,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OPTIONS0")
-            .field(
-                "sw_stall_appcpu_c0",
-                &format_args!("{}", self.sw_stall_appcpu_c0().bits()),
-            )
-            .field(
-                "sw_stall_procpu_c0",
-                &format_args!("{}", self.sw_stall_procpu_c0().bits()),
-            )
-            .field(
-                "bb_i2c_force_pd",
-                &format_args!("{}", self.bb_i2c_force_pd().bit()),
-            )
-            .field(
-                "bb_i2c_force_pu",
-                &format_args!("{}", self.bb_i2c_force_pu().bit()),
-            )
-            .field(
-                "bbpll_i2c_force_pd",
-                &format_args!("{}", self.bbpll_i2c_force_pd().bit()),
-            )
-            .field(
-                "bbpll_i2c_force_pu",
-                &format_args!("{}", self.bbpll_i2c_force_pu().bit()),
-            )
-            .field(
-                "bbpll_force_pd",
-                &format_args!("{}", self.bbpll_force_pd().bit()),
-            )
-            .field(
-                "bbpll_force_pu",
-                &format_args!("{}", self.bbpll_force_pu().bit()),
-            )
-            .field(
-                "xtl_force_pd",
-                &format_args!("{}", self.xtl_force_pd().bit()),
-            )
-            .field(
-                "xtl_force_pu",
-                &format_args!("{}", self.xtl_force_pu().bit()),
-            )
-            .field(
-                "xtl_en_wait",
-                &format_args!("{}", self.xtl_en_wait().bits()),
-            )
-            .field(
-                "xtl_ext_ctr_sel",
-                &format_args!("{}", self.xtl_ext_ctr_sel().bits()),
-            )
-            .field(
-                "xtl_force_iso",
-                &format_args!("{}", self.xtl_force_iso().bit()),
-            )
-            .field(
-                "pll_force_iso",
-                &format_args!("{}", self.pll_force_iso().bit()),
-            )
-            .field(
-                "analog_force_iso",
-                &format_args!("{}", self.analog_force_iso().bit()),
-            )
-            .field(
-                "xtl_force_noiso",
-                &format_args!("{}", self.xtl_force_noiso().bit()),
-            )
-            .field(
-                "pll_force_noiso",
-                &format_args!("{}", self.pll_force_noiso().bit()),
-            )
-            .field(
-                "analog_force_noiso",
-                &format_args!("{}", self.analog_force_noiso().bit()),
-            )
-            .field(
-                "dg_wrap_force_rst",
-                &format_args!("{}", self.dg_wrap_force_rst().bit()),
-            )
-            .field(
-                "dg_wrap_force_norst",
-                &format_args!("{}", self.dg_wrap_force_norst().bit()),
-            )
+            .field("sw_stall_appcpu_c0", &self.sw_stall_appcpu_c0())
+            .field("sw_stall_procpu_c0", &self.sw_stall_procpu_c0())
+            .field("bb_i2c_force_pd", &self.bb_i2c_force_pd())
+            .field("bb_i2c_force_pu", &self.bb_i2c_force_pu())
+            .field("bbpll_i2c_force_pd", &self.bbpll_i2c_force_pd())
+            .field("bbpll_i2c_force_pu", &self.bbpll_i2c_force_pu())
+            .field("bbpll_force_pd", &self.bbpll_force_pd())
+            .field("bbpll_force_pu", &self.bbpll_force_pu())
+            .field("xtl_force_pd", &self.xtl_force_pd())
+            .field("xtl_force_pu", &self.xtl_force_pu())
+            .field("xtl_en_wait", &self.xtl_en_wait())
+            .field("xtl_ext_ctr_sel", &self.xtl_ext_ctr_sel())
+            .field("xtl_force_iso", &self.xtl_force_iso())
+            .field("pll_force_iso", &self.pll_force_iso())
+            .field("analog_force_iso", &self.analog_force_iso())
+            .field("xtl_force_noiso", &self.xtl_force_noiso())
+            .field("pll_force_noiso", &self.pll_force_noiso())
+            .field("analog_force_noiso", &self.analog_force_noiso())
+            .field("dg_wrap_force_rst", &self.dg_wrap_force_rst())
+            .field("dg_wrap_force_norst", &self.dg_wrap_force_norst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OPTIONS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/pad_hold.rs b/esp32c3/src/rtc_cntl/pad_hold.rs
index 188d0fde79..e98f35122d 100644
--- a/esp32c3/src/rtc_cntl/pad_hold.rs
+++ b/esp32c3/src/rtc_cntl/pad_hold.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_HOLD")
-            .field(
-                "gpio_pin0_hold",
-                &format_args!("{}", self.gpio_pin0_hold().bit()),
-            )
-            .field(
-                "gpio_pin1_hold",
-                &format_args!("{}", self.gpio_pin1_hold().bit()),
-            )
-            .field(
-                "gpio_pin2_hold",
-                &format_args!("{}", self.gpio_pin2_hold().bit()),
-            )
-            .field(
-                "gpio_pin3_hold",
-                &format_args!("{}", self.gpio_pin3_hold().bit()),
-            )
-            .field(
-                "gpio_pin4_hold",
-                &format_args!("{}", self.gpio_pin4_hold().bit()),
-            )
-            .field(
-                "gpio_pin5_hold",
-                &format_args!("{}", self.gpio_pin5_hold().bit()),
-            )
+            .field("gpio_pin0_hold", &self.gpio_pin0_hold())
+            .field("gpio_pin1_hold", &self.gpio_pin1_hold())
+            .field("gpio_pin2_hold", &self.gpio_pin2_hold())
+            .field("gpio_pin3_hold", &self.gpio_pin3_hold())
+            .field("gpio_pin4_hold", &self.gpio_pin4_hold())
+            .field("gpio_pin5_hold", &self.gpio_pin5_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - the hold configure of rtc gpio0"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/pg_ctrl.rs b/esp32c3/src/rtc_cntl/pg_ctrl.rs
index ab58bbeab4..03ef00d71c 100644
--- a/esp32c3/src/rtc_cntl/pg_ctrl.rs
+++ b/esp32c3/src/rtc_cntl/pg_ctrl.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PG_CTRL")
-            .field(
-                "power_glitch_dsense",
-                &format_args!("{}", self.power_glitch_dsense().bits()),
-            )
-            .field(
-                "power_glitch_force_pd",
-                &format_args!("{}", self.power_glitch_force_pd().bit()),
-            )
-            .field(
-                "power_glitch_force_pu",
-                &format_args!("{}", self.power_glitch_force_pu().bit()),
-            )
-            .field(
-                "power_glitch_efuse_sel",
-                &format_args!("{}", self.power_glitch_efuse_sel().bit()),
-            )
-            .field(
-                "power_glitch_en",
-                &format_args!("{}", self.power_glitch_en().bit()),
-            )
+            .field("power_glitch_dsense", &self.power_glitch_dsense())
+            .field("power_glitch_force_pd", &self.power_glitch_force_pd())
+            .field("power_glitch_force_pu", &self.power_glitch_force_pu())
+            .field("power_glitch_efuse_sel", &self.power_glitch_efuse_sel())
+            .field("power_glitch_en", &self.power_glitch_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PG_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 26:27 - power glitch desense"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/pwc.rs b/esp32c3/src/rtc_cntl/pwc.rs
index 000a5219dd..ab6f484d53 100644
--- a/esp32c3/src/rtc_cntl/pwc.rs
+++ b/esp32c3/src/rtc_cntl/pwc.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWC")
-            .field(
-                "pad_force_hold",
-                &format_args!("{}", self.pad_force_hold().bit()),
-            )
+            .field("pad_force_hold", &self.pad_force_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - rtc pad force hold"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/reset_state.rs b/esp32c3/src/rtc_cntl/reset_state.rs
index 30bebb3e8b..43bd88f6bb 100644
--- a/esp32c3/src/rtc_cntl/reset_state.rs
+++ b/esp32c3/src/rtc_cntl/reset_state.rs
@@ -112,63 +112,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET_STATE")
-            .field(
-                "reset_cause_procpu",
-                &format_args!("{}", self.reset_cause_procpu().bits()),
-            )
-            .field(
-                "reset_cause_appcpu",
-                &format_args!("{}", self.reset_cause_appcpu().bits()),
-            )
-            .field(
-                "stat_vector_sel_appcpu",
-                &format_args!("{}", self.stat_vector_sel_appcpu().bit()),
-            )
-            .field(
-                "stat_vector_sel_procpu",
-                &format_args!("{}", self.stat_vector_sel_procpu().bit()),
-            )
-            .field(
-                "all_reset_flag_procpu",
-                &format_args!("{}", self.all_reset_flag_procpu().bit()),
-            )
-            .field(
-                "all_reset_flag_appcpu",
-                &format_args!("{}", self.all_reset_flag_appcpu().bit()),
-            )
-            .field(
-                "ocd_halt_on_reset_appcpu",
-                &format_args!("{}", self.ocd_halt_on_reset_appcpu().bit()),
-            )
-            .field(
-                "ocd_halt_on_reset_procpu",
-                &format_args!("{}", self.ocd_halt_on_reset_procpu().bit()),
-            )
-            .field(
-                "jtag_reset_flag_procpu",
-                &format_args!("{}", self.jtag_reset_flag_procpu().bit()),
-            )
-            .field(
-                "jtag_reset_flag_appcpu",
-                &format_args!("{}", self.jtag_reset_flag_appcpu().bit()),
-            )
-            .field(
-                "dreset_mask_appcpu",
-                &format_args!("{}", self.dreset_mask_appcpu().bit()),
-            )
-            .field(
-                "dreset_mask_procpu",
-                &format_args!("{}", self.dreset_mask_procpu().bit()),
-            )
+            .field("reset_cause_procpu", &self.reset_cause_procpu())
+            .field("reset_cause_appcpu", &self.reset_cause_appcpu())
+            .field("stat_vector_sel_appcpu", &self.stat_vector_sel_appcpu())
+            .field("stat_vector_sel_procpu", &self.stat_vector_sel_procpu())
+            .field("all_reset_flag_procpu", &self.all_reset_flag_procpu())
+            .field("all_reset_flag_appcpu", &self.all_reset_flag_appcpu())
+            .field("ocd_halt_on_reset_appcpu", &self.ocd_halt_on_reset_appcpu())
+            .field("ocd_halt_on_reset_procpu", &self.ocd_halt_on_reset_procpu())
+            .field("jtag_reset_flag_procpu", &self.jtag_reset_flag_procpu())
+            .field("jtag_reset_flag_appcpu", &self.jtag_reset_flag_appcpu())
+            .field("dreset_mask_appcpu", &self.dreset_mask_appcpu())
+            .field("dreset_mask_procpu", &self.dreset_mask_procpu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - APP CPU state vector sel"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/retention_ctrl.rs b/esp32c3/src/rtc_cntl/retention_ctrl.rs
index 4d28cbc9ed..8825c0adaa 100644
--- a/esp32c3/src/rtc_cntl/retention_ctrl.rs
+++ b/esp32c3/src/rtc_cntl/retention_ctrl.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_CTRL")
-            .field(
-                "retention_clk_sel",
-                &format_args!("{}", self.retention_clk_sel().bit()),
-            )
-            .field(
-                "retention_done_wait",
-                &format_args!("{}", self.retention_done_wait().bits()),
-            )
-            .field(
-                "retention_clkoff_wait",
-                &format_args!("{}", self.retention_clkoff_wait().bits()),
-            )
-            .field(
-                "retention_en",
-                &format_args!("{}", self.retention_en().bit()),
-            )
-            .field(
-                "retention_wait",
-                &format_args!("{}", self.retention_wait().bits()),
-            )
+            .field("retention_clk_sel", &self.retention_clk_sel())
+            .field("retention_done_wait", &self.retention_done_wait())
+            .field("retention_clkoff_wait", &self.retention_clkoff_wait())
+            .field("retention_en", &self.retention_en())
+            .field("retention_wait", &self.retention_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - Retention clk sel"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/rtc_cntl.rs b/esp32c3/src/rtc_cntl/rtc_cntl.rs
index 0022ac087b..354ba813b7 100644
--- a/esp32c3/src/rtc_cntl/rtc_cntl.rs
+++ b/esp32c3/src/rtc_cntl/rtc_cntl.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_CNTL")
-            .field(
-                "dig_reg_cal_en",
-                &format_args!("{}", self.dig_reg_cal_en().bit()),
-            )
-            .field("sck_dcap", &format_args!("{}", self.sck_dcap().bits()))
-            .field(
-                "dboost_force_pd",
-                &format_args!("{}", self.dboost_force_pd().bit()),
-            )
-            .field(
-                "dboost_force_pu",
-                &format_args!("{}", self.dboost_force_pu().bit()),
-            )
-            .field(
-                "regulator_force_pd",
-                &format_args!("{}", self.regulator_force_pd().bit()),
-            )
-            .field(
-                "regulator_force_pu",
-                &format_args!("{}", self.regulator_force_pu().bit()),
-            )
+            .field("dig_reg_cal_en", &self.dig_reg_cal_en())
+            .field("sck_dcap", &self.sck_dcap())
+            .field("dboost_force_pd", &self.dboost_force_pd())
+            .field("dboost_force_pu", &self.dboost_force_pu())
+            .field("regulator_force_pd", &self.regulator_force_pd())
+            .field("regulator_force_pu", &self.regulator_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - software enable digital regulator cali"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/sdio_conf.rs b/esp32c3/src/rtc_cntl/sdio_conf.rs
index 6f44157e25..c1b76ef852 100644
--- a/esp32c3/src/rtc_cntl/sdio_conf.rs
+++ b/esp32c3/src/rtc_cntl/sdio_conf.rs
@@ -150,52 +150,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_CONF")
-            .field(
-                "sdio_timer_target",
-                &format_args!("{}", self.sdio_timer_target().bits()),
-            )
-            .field(
-                "sdio_dthdrv",
-                &format_args!("{}", self.sdio_dthdrv().bits()),
-            )
-            .field("sdio_dcap", &format_args!("{}", self.sdio_dcap().bits()))
-            .field("sdio_initi", &format_args!("{}", self.sdio_initi().bits()))
-            .field(
-                "sdio_en_initi",
-                &format_args!("{}", self.sdio_en_initi().bit()),
-            )
-            .field(
-                "sdio_dcurlim",
-                &format_args!("{}", self.sdio_dcurlim().bits()),
-            )
-            .field(
-                "sdio_modecurlim",
-                &format_args!("{}", self.sdio_modecurlim().bit()),
-            )
-            .field(
-                "sdio_encurlim",
-                &format_args!("{}", self.sdio_encurlim().bit()),
-            )
-            .field(
-                "sdio_reg_pd_en",
-                &format_args!("{}", self.sdio_reg_pd_en().bit()),
-            )
-            .field("sdio_force", &format_args!("{}", self.sdio_force().bit()))
-            .field("sdio_tieh", &format_args!("{}", self.sdio_tieh().bit()))
-            .field("_1p8_ready", &format_args!("{}", self._1p8_ready().bit()))
-            .field("drefl_sdio", &format_args!("{}", self.drefl_sdio().bits()))
-            .field("drefm_sdio", &format_args!("{}", self.drefm_sdio().bits()))
-            .field("drefh_sdio", &format_args!("{}", self.drefh_sdio().bits()))
-            .field("xpd_sdio", &format_args!("{}", self.xpd_sdio().bit()))
+            .field("sdio_timer_target", &self.sdio_timer_target())
+            .field("sdio_dthdrv", &self.sdio_dthdrv())
+            .field("sdio_dcap", &self.sdio_dcap())
+            .field("sdio_initi", &self.sdio_initi())
+            .field("sdio_en_initi", &self.sdio_en_initi())
+            .field("sdio_dcurlim", &self.sdio_dcurlim())
+            .field("sdio_modecurlim", &self.sdio_modecurlim())
+            .field("sdio_encurlim", &self.sdio_encurlim())
+            .field("sdio_reg_pd_en", &self.sdio_reg_pd_en())
+            .field("sdio_force", &self.sdio_force())
+            .field("sdio_tieh", &self.sdio_tieh())
+            .field("_1p8_ready", &self._1p8_ready())
+            .field("drefl_sdio", &self.drefl_sdio())
+            .field("drefm_sdio", &self.drefm_sdio())
+            .field("drefh_sdio", &self.drefh_sdio())
+            .field("xpd_sdio", &self.xpd_sdio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - timer count to apply reg_sdio_dcap after sdio power on"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/sensor_ctrl.rs b/esp32c3/src/rtc_cntl/sensor_ctrl.rs
index 8b8bcfd92c..ae375002a8 100644
--- a/esp32c3/src/rtc_cntl/sensor_ctrl.rs
+++ b/esp32c3/src/rtc_cntl/sensor_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SENSOR_CTRL")
-            .field(
-                "sar2_pwdet_cct",
-                &format_args!("{}", self.sar2_pwdet_cct().bits()),
-            )
-            .field(
-                "force_xpd_sar",
-                &format_args!("{}", self.force_xpd_sar().bits()),
-            )
+            .field("sar2_pwdet_cct", &self.sar2_pwdet_cct())
+            .field("force_xpd_sar", &self.force_xpd_sar())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SENSOR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 27:29 - reg_sar2_pwdet_cct"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/slow_clk_conf.rs b/esp32c3/src/rtc_cntl/slow_clk_conf.rs
index 887e30e73d..bb4b0f0a16 100644
--- a/esp32c3/src/rtc_cntl/slow_clk_conf.rs
+++ b/esp32c3/src/rtc_cntl/slow_clk_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLOW_CLK_CONF")
-            .field(
-                "ana_clk_div_vld",
-                &format_args!("{}", self.ana_clk_div_vld().bit()),
-            )
-            .field(
-                "ana_clk_div",
-                &format_args!("{}", self.ana_clk_div().bits()),
-            )
-            .field(
-                "slow_clk_next_edge",
-                &format_args!("{}", self.slow_clk_next_edge().bit()),
-            )
+            .field("ana_clk_div_vld", &self.ana_clk_div_vld())
+            .field("ana_clk_div", &self.ana_clk_div())
+            .field("slow_clk_next_edge", &self.slow_clk_next_edge())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLOW_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 22 - used to sync div bus. clear vld before set reg_rtc_ana_clk_div"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/slp_reject_cause.rs b/esp32c3/src/rtc_cntl/slp_reject_cause.rs
index 861ba32ef3..1e6ce2d868 100644
--- a/esp32c3/src/rtc_cntl/slp_reject_cause.rs
+++ b/esp32c3/src/rtc_cntl/slp_reject_cause.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_REJECT_CAUSE")
-            .field(
-                "reject_cause",
-                &format_args!("{}", self.reject_cause().bits()),
-            )
+            .field("reject_cause", &self.reject_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_REJECT_CAUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_reject_cause::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLP_REJECT_CAUSE_SPEC;
 impl crate::RegisterSpec for SLP_REJECT_CAUSE_SPEC {
diff --git a/esp32c3/src/rtc_cntl/slp_reject_conf.rs b/esp32c3/src/rtc_cntl/slp_reject_conf.rs
index c8a890a5eb..a7b1f477ab 100644
--- a/esp32c3/src/rtc_cntl/slp_reject_conf.rs
+++ b/esp32c3/src/rtc_cntl/slp_reject_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_REJECT_CONF")
-            .field(
-                "sleep_reject_ena",
-                &format_args!("{}", self.sleep_reject_ena().bits()),
-            )
-            .field(
-                "light_slp_reject_en",
-                &format_args!("{}", self.light_slp_reject_en().bit()),
-            )
-            .field(
-                "deep_slp_reject_en",
-                &format_args!("{}", self.deep_slp_reject_en().bit()),
-            )
+            .field("sleep_reject_ena", &self.sleep_reject_ena())
+            .field("light_slp_reject_en", &self.light_slp_reject_en())
+            .field("deep_slp_reject_en", &self.deep_slp_reject_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_REJECT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 12:29 - sleep reject enable"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/slp_timer0.rs b/esp32c3/src/rtc_cntl/slp_timer0.rs
index 5236aa7aea..72f53b7b54 100644
--- a/esp32c3/src/rtc_cntl/slp_timer0.rs
+++ b/esp32c3/src/rtc_cntl/slp_timer0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_TIMER0")
-            .field("slp_val_lo", &format_args!("{}", self.slp_val_lo().bits()))
+            .field("slp_val_lo", &self.slp_val_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_TIMER0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - configure the sleep time"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/slp_timer1.rs b/esp32c3/src/rtc_cntl/slp_timer1.rs
index 7a579150d1..a3efeb084d 100644
--- a/esp32c3/src/rtc_cntl/slp_timer1.rs
+++ b/esp32c3/src/rtc_cntl/slp_timer1.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_TIMER1")
-            .field("slp_val_hi", &format_args!("{}", self.slp_val_hi().bits()))
+            .field("slp_val_hi", &self.slp_val_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_TIMER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - RTC sleep timer high 16 bits"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/slp_wakeup_cause.rs b/esp32c3/src/rtc_cntl/slp_wakeup_cause.rs
index 9885991d2c..9cb5d2eea6 100644
--- a/esp32c3/src/rtc_cntl/slp_wakeup_cause.rs
+++ b/esp32c3/src/rtc_cntl/slp_wakeup_cause.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CAUSE")
-            .field(
-                "wakeup_cause",
-                &format_args!("{}", self.wakeup_cause().bits()),
-            )
+            .field("wakeup_cause", &self.wakeup_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CAUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cause::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLP_WAKEUP_CAUSE_SPEC;
 impl crate::RegisterSpec for SLP_WAKEUP_CAUSE_SPEC {
diff --git a/esp32c3/src/rtc_cntl/state0.rs b/esp32c3/src/rtc_cntl/state0.rs
index 76139baf60..5fb98f7d0b 100644
--- a/esp32c3/src/rtc_cntl/state0.rs
+++ b/esp32c3/src/rtc_cntl/state0.rs
@@ -55,26 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE0")
-            .field(
-                "apb2rtc_bridge_sel",
-                &format_args!("{}", self.apb2rtc_bridge_sel().bit()),
-            )
-            .field(
-                "sdio_active_ind",
-                &format_args!("{}", self.sdio_active_ind().bit()),
-            )
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("sleep_en", &format_args!("{}", self.sleep_en().bit()))
+            .field("apb2rtc_bridge_sel", &self.apb2rtc_bridge_sel())
+            .field("sdio_active_ind", &self.sdio_active_ind())
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sleep_en", &self.sleep_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - rtc software interrupt to main cpu"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/store0.rs b/esp32c3/src/rtc_cntl/store0.rs
index 36ee36c6e5..106f2eea4a 100644
--- a/esp32c3/src/rtc_cntl/store0.rs
+++ b/esp32c3/src/rtc_cntl/store0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE0")
-            .field("scratch0", &format_args!("{}", self.scratch0().bits()))
+            .field("scratch0", &self.scratch0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/store1.rs b/esp32c3/src/rtc_cntl/store1.rs
index fb606a1d42..6e8bce028d 100644
--- a/esp32c3/src/rtc_cntl/store1.rs
+++ b/esp32c3/src/rtc_cntl/store1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE1")
-            .field("scratch1", &format_args!("{}", self.scratch1().bits()))
+            .field("scratch1", &self.scratch1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/store2.rs b/esp32c3/src/rtc_cntl/store2.rs
index be651f7ee9..b4b070d291 100644
--- a/esp32c3/src/rtc_cntl/store2.rs
+++ b/esp32c3/src/rtc_cntl/store2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE2")
-            .field("scratch2", &format_args!("{}", self.scratch2().bits()))
+            .field("scratch2", &self.scratch2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/store3.rs b/esp32c3/src/rtc_cntl/store3.rs
index 6eae51ef2c..78a872ae0d 100644
--- a/esp32c3/src/rtc_cntl/store3.rs
+++ b/esp32c3/src/rtc_cntl/store3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE3")
-            .field("scratch3", &format_args!("{}", self.scratch3().bits()))
+            .field("scratch3", &self.scratch3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/store4.rs b/esp32c3/src/rtc_cntl/store4.rs
index 4250467847..ddbed62e2c 100644
--- a/esp32c3/src/rtc_cntl/store4.rs
+++ b/esp32c3/src/rtc_cntl/store4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE4")
-            .field("scratch4", &format_args!("{}", self.scratch4().bits()))
+            .field("scratch4", &self.scratch4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/store5.rs b/esp32c3/src/rtc_cntl/store5.rs
index 531d517e49..784e9abe12 100644
--- a/esp32c3/src/rtc_cntl/store5.rs
+++ b/esp32c3/src/rtc_cntl/store5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE5")
-            .field("scratch5", &format_args!("{}", self.scratch5().bits()))
+            .field("scratch5", &self.scratch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/store6.rs b/esp32c3/src/rtc_cntl/store6.rs
index 2cdea3d50e..01bda69a1f 100644
--- a/esp32c3/src/rtc_cntl/store6.rs
+++ b/esp32c3/src/rtc_cntl/store6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE6")
-            .field("scratch6", &format_args!("{}", self.scratch6().bits()))
+            .field("scratch6", &self.scratch6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/store7.rs b/esp32c3/src/rtc_cntl/store7.rs
index bda7b2bc05..da8718265c 100644
--- a/esp32c3/src/rtc_cntl/store7.rs
+++ b/esp32c3/src/rtc_cntl/store7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE7")
-            .field("scratch7", &format_args!("{}", self.scratch7().bits()))
+            .field("scratch7", &self.scratch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/sw_cpu_stall.rs b/esp32c3/src/rtc_cntl/sw_cpu_stall.rs
index 09ecc13b01..9c01679ccf 100644
--- a/esp32c3/src/rtc_cntl/sw_cpu_stall.rs
+++ b/esp32c3/src/rtc_cntl/sw_cpu_stall.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SW_CPU_STALL")
-            .field(
-                "sw_stall_appcpu_c1",
-                &format_args!("{}", self.sw_stall_appcpu_c1().bits()),
-            )
-            .field(
-                "sw_stall_procpu_c1",
-                &format_args!("{}", self.sw_stall_procpu_c1().bits()),
-            )
+            .field("sw_stall_appcpu_c1", &self.sw_stall_appcpu_c1())
+            .field("sw_stall_procpu_c1", &self.sw_stall_procpu_c1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SW_CPU_STALL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:25 - {reg_sw_stall_appcpu_c1\\[5:0\\]"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/swd_conf.rs b/esp32c3/src/rtc_cntl/swd_conf.rs
index 5bcaa7dda6..0343c6f826 100644
--- a/esp32c3/src/rtc_cntl/swd_conf.rs
+++ b/esp32c3/src/rtc_cntl/swd_conf.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_CONF")
-            .field(
-                "swd_reset_flag",
-                &format_args!("{}", self.swd_reset_flag().bit()),
-            )
-            .field(
-                "swd_feed_int",
-                &format_args!("{}", self.swd_feed_int().bit()),
-            )
-            .field(
-                "swd_bypass_rst",
-                &format_args!("{}", self.swd_bypass_rst().bit()),
-            )
-            .field(
-                "swd_signal_width",
-                &format_args!("{}", self.swd_signal_width().bits()),
-            )
-            .field("swd_disable", &format_args!("{}", self.swd_disable().bit()))
-            .field(
-                "swd_auto_feed_en",
-                &format_args!("{}", self.swd_auto_feed_en().bit()),
-            )
+            .field("swd_reset_flag", &self.swd_reset_flag())
+            .field("swd_feed_int", &self.swd_feed_int())
+            .field("swd_bypass_rst", &self.swd_bypass_rst())
+            .field("swd_signal_width", &self.swd_signal_width())
+            .field("swd_disable", &self.swd_disable())
+            .field("swd_auto_feed_en", &self.swd_auto_feed_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - Bypass swd rst"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/swd_wprotect.rs b/esp32c3/src/rtc_cntl/swd_wprotect.rs
index de04649946..5b7a75b171 100644
--- a/esp32c3/src/rtc_cntl/swd_wprotect.rs
+++ b/esp32c3/src/rtc_cntl/swd_wprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_WPROTECT")
-            .field("swd_wkey", &format_args!("{}", self.swd_wkey().bits()))
+            .field("swd_wkey", &self.swd_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_WPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - the key of super wdt"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/time_high0.rs b/esp32c3/src/rtc_cntl/time_high0.rs
index 6d644accb7..522b0a54f7 100644
--- a/esp32c3/src/rtc_cntl/time_high0.rs
+++ b/esp32c3/src/rtc_cntl/time_high0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_HIGH0")
-            .field(
-                "timer_value0_high",
-                &format_args!("{}", self.timer_value0_high().bits()),
-            )
+            .field("timer_value0_high", &self.timer_value0_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_HIGH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rtc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_high0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIME_HIGH0_SPEC;
 impl crate::RegisterSpec for TIME_HIGH0_SPEC {
diff --git a/esp32c3/src/rtc_cntl/time_high1.rs b/esp32c3/src/rtc_cntl/time_high1.rs
index 8283af55bb..2fb277b5e0 100644
--- a/esp32c3/src/rtc_cntl/time_high1.rs
+++ b/esp32c3/src/rtc_cntl/time_high1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_HIGH1")
-            .field(
-                "timer_value1_high",
-                &format_args!("{}", self.timer_value1_high().bits()),
-            )
+            .field("timer_value1_high", &self.timer_value1_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_HIGH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rtc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_high1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIME_HIGH1_SPEC;
 impl crate::RegisterSpec for TIME_HIGH1_SPEC {
diff --git a/esp32c3/src/rtc_cntl/time_low0.rs b/esp32c3/src/rtc_cntl/time_low0.rs
index 04bd431b5d..df60be29d6 100644
--- a/esp32c3/src/rtc_cntl/time_low0.rs
+++ b/esp32c3/src/rtc_cntl/time_low0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_LOW0")
-            .field(
-                "timer_value0_low",
-                &format_args!("{}", self.timer_value0_low().bits()),
-            )
+            .field("timer_value0_low", &self.timer_value0_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_LOW0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rtc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_low0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIME_LOW0_SPEC;
 impl crate::RegisterSpec for TIME_LOW0_SPEC {
diff --git a/esp32c3/src/rtc_cntl/time_low1.rs b/esp32c3/src/rtc_cntl/time_low1.rs
index c87043e223..a80b988f3d 100644
--- a/esp32c3/src/rtc_cntl/time_low1.rs
+++ b/esp32c3/src/rtc_cntl/time_low1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_LOW1")
-            .field(
-                "timer_value1_low",
-                &format_args!("{}", self.timer_value1_low().bits()),
-            )
+            .field("timer_value1_low", &self.timer_value1_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_LOW1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rtc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_low1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIME_LOW1_SPEC;
 impl crate::RegisterSpec for TIME_LOW1_SPEC {
diff --git a/esp32c3/src/rtc_cntl/time_update.rs b/esp32c3/src/rtc_cntl/time_update.rs
index 4ef38c1e20..74c7c513a1 100644
--- a/esp32c3/src/rtc_cntl/time_update.rs
+++ b/esp32c3/src/rtc_cntl/time_update.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_UPDATE")
-            .field(
-                "timer_sys_stall",
-                &format_args!("{}", self.timer_sys_stall().bit()),
-            )
-            .field(
-                "timer_xtl_off",
-                &format_args!("{}", self.timer_xtl_off().bit()),
-            )
-            .field(
-                "timer_sys_rst",
-                &format_args!("{}", self.timer_sys_rst().bit()),
-            )
+            .field("timer_sys_stall", &self.timer_sys_stall())
+            .field("timer_xtl_off", &self.timer_xtl_off())
+            .field("timer_sys_rst", &self.timer_sys_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - Enable to record system stall time"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/timer1.rs b/esp32c3/src/rtc_cntl/timer1.rs
index d80f6071f0..0c15bf32d7 100644
--- a/esp32c3/src/rtc_cntl/timer1.rs
+++ b/esp32c3/src/rtc_cntl/timer1.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER1")
-            .field(
-                "cpu_stall_en",
-                &format_args!("{}", self.cpu_stall_en().bit()),
-            )
-            .field(
-                "cpu_stall_wait",
-                &format_args!("{}", self.cpu_stall_wait().bits()),
-            )
-            .field("ck8m_wait", &format_args!("{}", self.ck8m_wait().bits()))
-            .field(
-                "xtl_buf_wait",
-                &format_args!("{}", self.xtl_buf_wait().bits()),
-            )
-            .field(
-                "pll_buf_wait",
-                &format_args!("{}", self.pll_buf_wait().bits()),
-            )
+            .field("cpu_stall_en", &self.cpu_stall_en())
+            .field("cpu_stall_wait", &self.cpu_stall_wait())
+            .field("ck8m_wait", &self.ck8m_wait())
+            .field("xtl_buf_wait", &self.xtl_buf_wait())
+            .field("pll_buf_wait", &self.pll_buf_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - CPU stall enable bit"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/timer2.rs b/esp32c3/src/rtc_cntl/timer2.rs
index 6e63183412..9be2c93828 100644
--- a/esp32c3/src/rtc_cntl/timer2.rs
+++ b/esp32c3/src/rtc_cntl/timer2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER2")
-            .field(
-                "min_time_ck8m_off",
-                &format_args!("{}", self.min_time_ck8m_off().bits()),
-            )
+            .field("min_time_ck8m_off", &self.min_time_ck8m_off())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 24:31 - minimal cycles in slow_clk_rtc for CK8M in power down state"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/timer3.rs b/esp32c3/src/rtc_cntl/timer3.rs
index 7bc8fe3476..c681cbada2 100644
--- a/esp32c3/src/rtc_cntl/timer3.rs
+++ b/esp32c3/src/rtc_cntl/timer3.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER3")
-            .field(
-                "wifi_wait_timer",
-                &format_args!("{}", self.wifi_wait_timer().bits()),
-            )
-            .field(
-                "wifi_powerup_timer",
-                &format_args!("{}", self.wifi_powerup_timer().bits()),
-            )
-            .field(
-                "bt_wait_timer",
-                &format_args!("{}", self.bt_wait_timer().bits()),
-            )
-            .field(
-                "bt_powerup_timer",
-                &format_args!("{}", self.bt_powerup_timer().bits()),
-            )
+            .field("wifi_wait_timer", &self.wifi_wait_timer())
+            .field("wifi_powerup_timer", &self.wifi_powerup_timer())
+            .field("bt_wait_timer", &self.bt_wait_timer())
+            .field("bt_powerup_timer", &self.bt_powerup_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - wifi power domain wakeup time"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/timer4.rs b/esp32c3/src/rtc_cntl/timer4.rs
index 74e24ba7e5..48cdbf1cc3 100644
--- a/esp32c3/src/rtc_cntl/timer4.rs
+++ b/esp32c3/src/rtc_cntl/timer4.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER4")
-            .field(
-                "cpu_top_wait_timer",
-                &format_args!("{}", self.cpu_top_wait_timer().bits()),
-            )
-            .field(
-                "cpu_top_powerup_timer",
-                &format_args!("{}", self.cpu_top_powerup_timer().bits()),
-            )
-            .field(
-                "dg_wrap_wait_timer",
-                &format_args!("{}", self.dg_wrap_wait_timer().bits()),
-            )
-            .field(
-                "dg_wrap_powerup_timer",
-                &format_args!("{}", self.dg_wrap_powerup_timer().bits()),
-            )
+            .field("cpu_top_wait_timer", &self.cpu_top_wait_timer())
+            .field("cpu_top_powerup_timer", &self.cpu_top_powerup_timer())
+            .field("dg_wrap_wait_timer", &self.dg_wrap_wait_timer())
+            .field("dg_wrap_powerup_timer", &self.dg_wrap_powerup_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - cpu top power domain wakeup time"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/timer5.rs b/esp32c3/src/rtc_cntl/timer5.rs
index e3ec95fd9b..106776dc1a 100644
--- a/esp32c3/src/rtc_cntl/timer5.rs
+++ b/esp32c3/src/rtc_cntl/timer5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER5")
-            .field(
-                "min_slp_val",
-                &format_args!("{}", self.min_slp_val().bits()),
-            )
+            .field("min_slp_val", &self.min_slp_val())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:15 - minimal sleep cycles in slow_clk_rtc"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/timer6.rs b/esp32c3/src/rtc_cntl/timer6.rs
index 97fb427eeb..7888476dad 100644
--- a/esp32c3/src/rtc_cntl/timer6.rs
+++ b/esp32c3/src/rtc_cntl/timer6.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER6")
-            .field(
-                "dg_peri_wait_timer",
-                &format_args!("{}", self.dg_peri_wait_timer().bits()),
-            )
-            .field(
-                "dg_peri_powerup_timer",
-                &format_args!("{}", self.dg_peri_powerup_timer().bits()),
-            )
+            .field("dg_peri_wait_timer", &self.dg_peri_wait_timer())
+            .field("dg_peri_powerup_timer", &self.dg_peri_powerup_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:24 - digital peri power domain wakeup time"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/ulp_cp_timer_1.rs b/esp32c3/src/rtc_cntl/ulp_cp_timer_1.rs
index 02d7c9e07d..eba9f76c94 100644
--- a/esp32c3/src/rtc_cntl/ulp_cp_timer_1.rs
+++ b/esp32c3/src/rtc_cntl/ulp_cp_timer_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_TIMER_1")
-            .field(
-                "ulp_cp_timer_slp_cycle",
-                &format_args!("{}", self.ulp_cp_timer_slp_cycle().bits()),
-            )
+            .field("ulp_cp_timer_slp_cycle", &self.ulp_cp_timer_slp_cycle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_TIMER_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:31 - sleep cycles for ULP-coprocessor timer"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/usb_conf.rs b/esp32c3/src/rtc_cntl/usb_conf.rs
index fc8f9451e0..6bf9ca16a3 100644
--- a/esp32c3/src/rtc_cntl/usb_conf.rs
+++ b/esp32c3/src/rtc_cntl/usb_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_CONF")
-            .field(
-                "io_mux_reset_disable",
-                &format_args!("{}", self.io_mux_reset_disable().bit()),
-            )
+            .field("io_mux_reset_disable", &self.io_mux_reset_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - disable io_mux reset"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/wakeup_state.rs b/esp32c3/src/rtc_cntl/wakeup_state.rs
index 607de30507..8ee1267d16 100644
--- a/esp32c3/src/rtc_cntl/wakeup_state.rs
+++ b/esp32c3/src/rtc_cntl/wakeup_state.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WAKEUP_STATE")
-            .field("wakeup_ena", &format_args!("{}", self.wakeup_ena().bits()))
+            .field("wakeup_ena", &self.wakeup_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WAKEUP_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 15:31 - wakeup enable bitmap"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/wdtconfig0.rs b/esp32c3/src/rtc_cntl/wdtconfig0.rs
index 42ae1b8723..7da9469eed 100644
--- a/esp32c3/src/rtc_cntl/wdtconfig0.rs
+++ b/esp32c3/src/rtc_cntl/wdtconfig0.rs
@@ -125,52 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG0")
-            .field(
-                "wdt_chip_reset_width",
-                &format_args!("{}", self.wdt_chip_reset_width().bits()),
-            )
-            .field(
-                "wdt_chip_reset_en",
-                &format_args!("{}", self.wdt_chip_reset_en().bit()),
-            )
-            .field(
-                "wdt_pause_in_slp",
-                &format_args!("{}", self.wdt_pause_in_slp().bit()),
-            )
-            .field(
-                "wdt_appcpu_reset_en",
-                &format_args!("{}", self.wdt_appcpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_chip_reset_width", &self.wdt_chip_reset_width())
+            .field("wdt_chip_reset_en", &self.wdt_chip_reset_en())
+            .field("wdt_pause_in_slp", &self.wdt_pause_in_slp())
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - chip reset siginal pulse width"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/wdtconfig1.rs b/esp32c3/src/rtc_cntl/wdtconfig1.rs
index 7d878d7c0b..51fdca6f0f 100644
--- a/esp32c3/src/rtc_cntl/wdtconfig1.rs
+++ b/esp32c3/src/rtc_cntl/wdtconfig1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG1")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - the hold time of stage0"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/wdtconfig2.rs b/esp32c3/src/rtc_cntl/wdtconfig2.rs
index f2791e7066..8b5ee0db7a 100644
--- a/esp32c3/src/rtc_cntl/wdtconfig2.rs
+++ b/esp32c3/src/rtc_cntl/wdtconfig2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG2")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - the hold time of stage1"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/wdtconfig3.rs b/esp32c3/src/rtc_cntl/wdtconfig3.rs
index ae7ccf03c9..e5eda7035a 100644
--- a/esp32c3/src/rtc_cntl/wdtconfig3.rs
+++ b/esp32c3/src/rtc_cntl/wdtconfig3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG3")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - the hold time of stage2"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/wdtconfig4.rs b/esp32c3/src/rtc_cntl/wdtconfig4.rs
index 6c1b263e5b..460c357a48 100644
--- a/esp32c3/src/rtc_cntl/wdtconfig4.rs
+++ b/esp32c3/src/rtc_cntl/wdtconfig4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG4")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - the hold time of stage3"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/wdtwprotect.rs b/esp32c3/src/rtc_cntl/wdtwprotect.rs
index 8e753b7965..922f8869b0 100644
--- a/esp32c3/src/rtc_cntl/wdtwprotect.rs
+++ b/esp32c3/src/rtc_cntl/wdtwprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTWPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTWPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - the key of rtc wdt"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/xtal32k_clk_factor.rs b/esp32c3/src/rtc_cntl/xtal32k_clk_factor.rs
index 2c751d9bac..7716b3ac3c 100644
--- a/esp32c3/src/rtc_cntl/xtal32k_clk_factor.rs
+++ b/esp32c3/src/rtc_cntl/xtal32k_clk_factor.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL32K_CLK_FACTOR")
-            .field(
-                "xtal32k_clk_factor",
-                &format_args!("{}", self.xtal32k_clk_factor().bits()),
-            )
+            .field("xtal32k_clk_factor", &self.xtal32k_clk_factor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL32K_CLK_FACTOR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - xtal 32k watch dog backup clock factor"]
     #[inline(always)]
diff --git a/esp32c3/src/rtc_cntl/xtal32k_conf.rs b/esp32c3/src/rtc_cntl/xtal32k_conf.rs
index e80dbbfc36..6eb72576b1 100644
--- a/esp32c3/src/rtc_cntl/xtal32k_conf.rs
+++ b/esp32c3/src/rtc_cntl/xtal32k_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL32K_CONF")
-            .field(
-                "xtal32k_return_wait",
-                &format_args!("{}", self.xtal32k_return_wait().bits()),
-            )
-            .field(
-                "xtal32k_restart_wait",
-                &format_args!("{}", self.xtal32k_restart_wait().bits()),
-            )
-            .field(
-                "xtal32k_wdt_timeout",
-                &format_args!("{}", self.xtal32k_wdt_timeout().bits()),
-            )
-            .field(
-                "xtal32k_stable_thres",
-                &format_args!("{}", self.xtal32k_stable_thres().bits()),
-            )
+            .field("xtal32k_return_wait", &self.xtal32k_return_wait())
+            .field("xtal32k_restart_wait", &self.xtal32k_restart_wait())
+            .field("xtal32k_wdt_timeout", &self.xtal32k_wdt_timeout())
+            .field("xtal32k_stable_thres", &self.xtal32k_stable_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL32K_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - cycles to wait to return noral xtal 32k"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/apb_peripheral_access_0.rs b/esp32c3/src/sensitive/apb_peripheral_access_0.rs
index c0101faffd..c1b2a45c1c 100644
--- a/esp32c3/src/sensitive/apb_peripheral_access_0.rs
+++ b/esp32c3/src/sensitive/apb_peripheral_access_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB_PERIPHERAL_ACCESS_0")
             .field(
                 "apb_peripheral_access_lock",
-                &format_args!("{}", self.apb_peripheral_access_lock().bit()),
+                &self.apb_peripheral_access_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_PERIPHERAL_ACCESS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - apb_peripheral_access_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/apb_peripheral_access_1.rs b/esp32c3/src/sensitive/apb_peripheral_access_1.rs
index d79c3e221e..a1d1d5ad04 100644
--- a/esp32c3/src/sensitive/apb_peripheral_access_1.rs
+++ b/esp32c3/src/sensitive/apb_peripheral_access_1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB_PERIPHERAL_ACCESS_1")
             .field(
                 "apb_peripheral_access_split_burst",
-                &format_args!("{}", self.apb_peripheral_access_split_burst().bit()),
+                &self.apb_peripheral_access_split_burst(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_PERIPHERAL_ACCESS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - apb_peripheral_access_split_burst"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/backup_bus_pms_constrain_0.rs b/esp32c3/src/sensitive/backup_bus_pms_constrain_0.rs
index 443b3fb9ba..4f1dc327c6 100644
--- a/esp32c3/src/sensitive/backup_bus_pms_constrain_0.rs
+++ b/esp32c3/src/sensitive/backup_bus_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_0")
             .field(
                 "backup_bus_pms_constrain_lock",
-                &format_args!("{}", self.backup_bus_pms_constrain_lock().bit()),
+                &self.backup_bus_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - backup_bus_pms_constrain_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/backup_bus_pms_constrain_1.rs b/esp32c3/src/sensitive/backup_bus_pms_constrain_1.rs
index 7ef84433a0..58f1226b95 100644
--- a/esp32c3/src/sensitive/backup_bus_pms_constrain_1.rs
+++ b/esp32c3/src/sensitive/backup_bus_pms_constrain_1.rs
@@ -127,65 +127,59 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_1")
             .field(
                 "backup_bus_pms_constrain_uart",
-                &format_args!("{}", self.backup_bus_pms_constrain_uart().bits()),
+                &self.backup_bus_pms_constrain_uart(),
             )
             .field(
                 "backup_bus_pms_constrain_g0spi_1",
-                &format_args!("{}", self.backup_bus_pms_constrain_g0spi_1().bits()),
+                &self.backup_bus_pms_constrain_g0spi_1(),
             )
             .field(
                 "backup_bus_pms_constrain_g0spi_0",
-                &format_args!("{}", self.backup_bus_pms_constrain_g0spi_0().bits()),
+                &self.backup_bus_pms_constrain_g0spi_0(),
             )
             .field(
                 "backup_bus_pms_constrain_gpio",
-                &format_args!("{}", self.backup_bus_pms_constrain_gpio().bits()),
+                &self.backup_bus_pms_constrain_gpio(),
             )
             .field(
                 "backup_bus_pms_constrain_fe2",
-                &format_args!("{}", self.backup_bus_pms_constrain_fe2().bits()),
+                &self.backup_bus_pms_constrain_fe2(),
             )
             .field(
                 "backup_bus_pms_constrain_fe",
-                &format_args!("{}", self.backup_bus_pms_constrain_fe().bits()),
+                &self.backup_bus_pms_constrain_fe(),
             )
             .field(
                 "backup_bus_pms_constrain_timer",
-                &format_args!("{}", self.backup_bus_pms_constrain_timer().bits()),
+                &self.backup_bus_pms_constrain_timer(),
             )
             .field(
                 "backup_bus_pms_constrain_rtc",
-                &format_args!("{}", self.backup_bus_pms_constrain_rtc().bits()),
+                &self.backup_bus_pms_constrain_rtc(),
             )
             .field(
                 "backup_bus_pms_constrain_io_mux",
-                &format_args!("{}", self.backup_bus_pms_constrain_io_mux().bits()),
+                &self.backup_bus_pms_constrain_io_mux(),
             )
             .field(
                 "backup_bus_pms_constrain_wdg",
-                &format_args!("{}", self.backup_bus_pms_constrain_wdg().bits()),
+                &self.backup_bus_pms_constrain_wdg(),
             )
             .field(
                 "backup_bus_pms_constrain_misc",
-                &format_args!("{}", self.backup_bus_pms_constrain_misc().bits()),
+                &self.backup_bus_pms_constrain_misc(),
             )
             .field(
                 "backup_bus_pms_constrain_i2c",
-                &format_args!("{}", self.backup_bus_pms_constrain_i2c().bits()),
+                &self.backup_bus_pms_constrain_i2c(),
             )
             .field(
                 "backup_bus_pms_constrain_uart1",
-                &format_args!("{}", self.backup_bus_pms_constrain_uart1().bits()),
+                &self.backup_bus_pms_constrain_uart1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - backup_bus_pms_constrain_uart"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/backup_bus_pms_constrain_2.rs b/esp32c3/src/sensitive/backup_bus_pms_constrain_2.rs
index 5f70cac0b0..19caefb105 100644
--- a/esp32c3/src/sensitive/backup_bus_pms_constrain_2.rs
+++ b/esp32c3/src/sensitive/backup_bus_pms_constrain_2.rs
@@ -91,49 +91,43 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_2")
             .field(
                 "backup_bus_pms_constrain_bt",
-                &format_args!("{}", self.backup_bus_pms_constrain_bt().bits()),
+                &self.backup_bus_pms_constrain_bt(),
             )
             .field(
                 "backup_bus_pms_constrain_i2c_ext0",
-                &format_args!("{}", self.backup_bus_pms_constrain_i2c_ext0().bits()),
+                &self.backup_bus_pms_constrain_i2c_ext0(),
             )
             .field(
                 "backup_bus_pms_constrain_uhci0",
-                &format_args!("{}", self.backup_bus_pms_constrain_uhci0().bits()),
+                &self.backup_bus_pms_constrain_uhci0(),
             )
             .field(
                 "backup_bus_pms_constrain_rmt",
-                &format_args!("{}", self.backup_bus_pms_constrain_rmt().bits()),
+                &self.backup_bus_pms_constrain_rmt(),
             )
             .field(
                 "backup_bus_pms_constrain_ledc",
-                &format_args!("{}", self.backup_bus_pms_constrain_ledc().bits()),
+                &self.backup_bus_pms_constrain_ledc(),
             )
             .field(
                 "backup_bus_pms_constrain_bb",
-                &format_args!("{}", self.backup_bus_pms_constrain_bb().bits()),
+                &self.backup_bus_pms_constrain_bb(),
             )
             .field(
                 "backup_bus_pms_constrain_timergroup",
-                &format_args!("{}", self.backup_bus_pms_constrain_timergroup().bits()),
+                &self.backup_bus_pms_constrain_timergroup(),
             )
             .field(
                 "backup_bus_pms_constrain_timergroup1",
-                &format_args!("{}", self.backup_bus_pms_constrain_timergroup1().bits()),
+                &self.backup_bus_pms_constrain_timergroup1(),
             )
             .field(
                 "backup_bus_pms_constrain_systimer",
-                &format_args!("{}", self.backup_bus_pms_constrain_systimer().bits()),
+                &self.backup_bus_pms_constrain_systimer(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - backup_bus_pms_constrain_bt"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/backup_bus_pms_constrain_3.rs b/esp32c3/src/sensitive/backup_bus_pms_constrain_3.rs
index c13e9707f0..1e7067f19a 100644
--- a/esp32c3/src/sensitive/backup_bus_pms_constrain_3.rs
+++ b/esp32c3/src/sensitive/backup_bus_pms_constrain_3.rs
@@ -73,41 +73,35 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_3")
             .field(
                 "backup_bus_pms_constrain_spi_2",
-                &format_args!("{}", self.backup_bus_pms_constrain_spi_2().bits()),
+                &self.backup_bus_pms_constrain_spi_2(),
             )
             .field(
                 "backup_bus_pms_constrain_apb_ctrl",
-                &format_args!("{}", self.backup_bus_pms_constrain_apb_ctrl().bits()),
+                &self.backup_bus_pms_constrain_apb_ctrl(),
             )
             .field(
                 "backup_bus_pms_constrain_can",
-                &format_args!("{}", self.backup_bus_pms_constrain_can().bits()),
+                &self.backup_bus_pms_constrain_can(),
             )
             .field(
                 "backup_bus_pms_constrain_i2s1",
-                &format_args!("{}", self.backup_bus_pms_constrain_i2s1().bits()),
+                &self.backup_bus_pms_constrain_i2s1(),
             )
             .field(
                 "backup_bus_pms_constrain_rwbt",
-                &format_args!("{}", self.backup_bus_pms_constrain_rwbt().bits()),
+                &self.backup_bus_pms_constrain_rwbt(),
             )
             .field(
                 "backup_bus_pms_constrain_wifimac",
-                &format_args!("{}", self.backup_bus_pms_constrain_wifimac().bits()),
+                &self.backup_bus_pms_constrain_wifimac(),
             )
             .field(
                 "backup_bus_pms_constrain_pwr",
-                &format_args!("{}", self.backup_bus_pms_constrain_pwr().bits()),
+                &self.backup_bus_pms_constrain_pwr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - backup_bus_pms_constrain_spi_2"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/backup_bus_pms_constrain_4.rs b/esp32c3/src/sensitive/backup_bus_pms_constrain_4.rs
index 5f9998bd9e..d525ba99fd 100644
--- a/esp32c3/src/sensitive/backup_bus_pms_constrain_4.rs
+++ b/esp32c3/src/sensitive/backup_bus_pms_constrain_4.rs
@@ -64,37 +64,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_4")
             .field(
                 "backup_bus_pms_constrain_usb_wrap",
-                &format_args!("{}", self.backup_bus_pms_constrain_usb_wrap().bits()),
+                &self.backup_bus_pms_constrain_usb_wrap(),
             )
             .field(
                 "backup_bus_pms_constrain_crypto_peri",
-                &format_args!("{}", self.backup_bus_pms_constrain_crypto_peri().bits()),
+                &self.backup_bus_pms_constrain_crypto_peri(),
             )
             .field(
                 "backup_bus_pms_constrain_crypto_dma",
-                &format_args!("{}", self.backup_bus_pms_constrain_crypto_dma().bits()),
+                &self.backup_bus_pms_constrain_crypto_dma(),
             )
             .field(
                 "backup_bus_pms_constrain_apb_adc",
-                &format_args!("{}", self.backup_bus_pms_constrain_apb_adc().bits()),
+                &self.backup_bus_pms_constrain_apb_adc(),
             )
             .field(
                 "backup_bus_pms_constrain_bt_pwr",
-                &format_args!("{}", self.backup_bus_pms_constrain_bt_pwr().bits()),
+                &self.backup_bus_pms_constrain_bt_pwr(),
             )
             .field(
                 "backup_bus_pms_constrain_usb_device",
-                &format_args!("{}", self.backup_bus_pms_constrain_usb_device().bits()),
+                &self.backup_bus_pms_constrain_usb_device(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 2:3 - backup_bus_pms_constrain_usb_wrap"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/backup_bus_pms_monitor_0.rs b/esp32c3/src/sensitive/backup_bus_pms_monitor_0.rs
index 3b8a250e2e..bb0a4a07b1 100644
--- a/esp32c3/src/sensitive/backup_bus_pms_monitor_0.rs
+++ b/esp32c3/src/sensitive/backup_bus_pms_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_MONITOR_0")
             .field(
                 "backup_bus_pms_monitor_lock",
-                &format_args!("{}", self.backup_bus_pms_monitor_lock().bit()),
+                &self.backup_bus_pms_monitor_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - backup_bus_pms_monitor_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/backup_bus_pms_monitor_1.rs b/esp32c3/src/sensitive/backup_bus_pms_monitor_1.rs
index d0f5815749..67b461d061 100644
--- a/esp32c3/src/sensitive/backup_bus_pms_monitor_1.rs
+++ b/esp32c3/src/sensitive/backup_bus_pms_monitor_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_MONITOR_1")
             .field(
                 "backup_bus_pms_monitor_violate_clr",
-                &format_args!("{}", self.backup_bus_pms_monitor_violate_clr().bit()),
+                &self.backup_bus_pms_monitor_violate_clr(),
             )
             .field(
                 "backup_bus_pms_monitor_violate_en",
-                &format_args!("{}", self.backup_bus_pms_monitor_violate_en().bit()),
+                &self.backup_bus_pms_monitor_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - backup_bus_pms_monitor_violate_clr"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/backup_bus_pms_monitor_2.rs b/esp32c3/src/sensitive/backup_bus_pms_monitor_2.rs
index c6649ecef7..46c45e88c8 100644
--- a/esp32c3/src/sensitive/backup_bus_pms_monitor_2.rs
+++ b/esp32c3/src/sensitive/backup_bus_pms_monitor_2.rs
@@ -42,38 +42,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_MONITOR_2")
             .field(
                 "backup_bus_pms_monitor_violate_intr",
-                &format_args!("{}", self.backup_bus_pms_monitor_violate_intr().bit()),
+                &self.backup_bus_pms_monitor_violate_intr(),
             )
             .field(
                 "backup_bus_pms_monitor_violate_status_htrans",
-                &format_args!(
-                    "{}",
-                    self.backup_bus_pms_monitor_violate_status_htrans().bits()
-                ),
+                &self.backup_bus_pms_monitor_violate_status_htrans(),
             )
             .field(
                 "backup_bus_pms_monitor_violate_status_hsize",
-                &format_args!(
-                    "{}",
-                    self.backup_bus_pms_monitor_violate_status_hsize().bits()
-                ),
+                &self.backup_bus_pms_monitor_violate_status_hsize(),
             )
             .field(
                 "backup_bus_pms_monitor_violate_status_hwrite",
-                &format_args!(
-                    "{}",
-                    self.backup_bus_pms_monitor_violate_status_hwrite().bit()
-                ),
+                &self.backup_bus_pms_monitor_violate_status_hwrite(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`backup_bus_pms_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BACKUP_BUS_PMS_MONITOR_2_SPEC;
 impl crate::RegisterSpec for BACKUP_BUS_PMS_MONITOR_2_SPEC {
diff --git a/esp32c3/src/sensitive/backup_bus_pms_monitor_3.rs b/esp32c3/src/sensitive/backup_bus_pms_monitor_3.rs
index d0b09f8824..7308cf9bb9 100644
--- a/esp32c3/src/sensitive/backup_bus_pms_monitor_3.rs
+++ b/esp32c3/src/sensitive/backup_bus_pms_monitor_3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_MONITOR_3")
             .field(
                 "backup_bus_pms_monitor_violate_haddr",
-                &format_args!("{}", self.backup_bus_pms_monitor_violate_haddr().bits()),
+                &self.backup_bus_pms_monitor_violate_haddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`backup_bus_pms_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BACKUP_BUS_PMS_MONITOR_3_SPEC;
 impl crate::RegisterSpec for BACKUP_BUS_PMS_MONITOR_3_SPEC {
diff --git a/esp32c3/src/sensitive/cache_mmu_access_0.rs b/esp32c3/src/sensitive/cache_mmu_access_0.rs
index a5d02f8a91..0de25e91d8 100644
--- a/esp32c3/src/sensitive/cache_mmu_access_0.rs
+++ b/esp32c3/src/sensitive/cache_mmu_access_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_ACCESS_0")
-            .field(
-                "cache_mmu_access_lock",
-                &format_args!("{}", self.cache_mmu_access_lock().bit()),
-            )
+            .field("cache_mmu_access_lock", &self.cache_mmu_access_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_ACCESS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - cache_mmu_access_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/cache_mmu_access_1.rs b/esp32c3/src/sensitive/cache_mmu_access_1.rs
index 78c0017219..4d1aa3733b 100644
--- a/esp32c3/src/sensitive/cache_mmu_access_1.rs
+++ b/esp32c3/src/sensitive/cache_mmu_access_1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_ACCESS_1")
-            .field(
-                "pro_mmu_rd_acs",
-                &format_args!("{}", self.pro_mmu_rd_acs().bit()),
-            )
-            .field(
-                "pro_mmu_wr_acs",
-                &format_args!("{}", self.pro_mmu_wr_acs().bit()),
-            )
+            .field("pro_mmu_rd_acs", &self.pro_mmu_rd_acs())
+            .field("pro_mmu_wr_acs", &self.pro_mmu_wr_acs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_ACCESS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - pro_mmu_rd_acs"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/cache_tag_access_0.rs b/esp32c3/src/sensitive/cache_tag_access_0.rs
index 70c452bd34..5d297ed20c 100644
--- a/esp32c3/src/sensitive/cache_tag_access_0.rs
+++ b/esp32c3/src/sensitive/cache_tag_access_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_TAG_ACCESS_0")
-            .field(
-                "cache_tag_access_lock",
-                &format_args!("{}", self.cache_tag_access_lock().bit()),
-            )
+            .field("cache_tag_access_lock", &self.cache_tag_access_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_TAG_ACCESS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - cache_tag_access_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/cache_tag_access_1.rs b/esp32c3/src/sensitive/cache_tag_access_1.rs
index c9e1208412..dbb199bf53 100644
--- a/esp32c3/src/sensitive/cache_tag_access_1.rs
+++ b/esp32c3/src/sensitive/cache_tag_access_1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_TAG_ACCESS_1")
-            .field(
-                "pro_i_tag_rd_acs",
-                &format_args!("{}", self.pro_i_tag_rd_acs().bit()),
-            )
-            .field(
-                "pro_i_tag_wr_acs",
-                &format_args!("{}", self.pro_i_tag_wr_acs().bit()),
-            )
-            .field(
-                "pro_d_tag_rd_acs",
-                &format_args!("{}", self.pro_d_tag_rd_acs().bit()),
-            )
-            .field(
-                "pro_d_tag_wr_acs",
-                &format_args!("{}", self.pro_d_tag_wr_acs().bit()),
-            )
+            .field("pro_i_tag_rd_acs", &self.pro_i_tag_rd_acs())
+            .field("pro_i_tag_wr_acs", &self.pro_i_tag_wr_acs())
+            .field("pro_d_tag_rd_acs", &self.pro_d_tag_rd_acs())
+            .field("pro_d_tag_wr_acs", &self.pro_d_tag_wr_acs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_TAG_ACCESS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - pro_i_tag_rd_acs"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/clock_gate.rs b/esp32c3/src/sensitive/clock_gate.rs
index 1d2ff02630..00bc148090 100644
--- a/esp32c3/src/sensitive/clock_gate.rs
+++ b/esp32c3/src/sensitive/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - clk_en"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_dram0_pms_monitor_0.rs b/esp32c3/src/sensitive/core_0_dram0_pms_monitor_0.rs
index 1218891a0d..b66162800e 100644
--- a/esp32c3/src/sensitive/core_0_dram0_pms_monitor_0.rs
+++ b/esp32c3/src/sensitive/core_0_dram0_pms_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_PMS_MONITOR_0")
             .field(
                 "core_0_dram0_pms_monitor_lock",
-                &format_args!("{}", self.core_0_dram0_pms_monitor_lock().bit()),
+                &self.core_0_dram0_pms_monitor_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_PMS_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - core_0_dram0_pms_monitor_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_dram0_pms_monitor_1.rs b/esp32c3/src/sensitive/core_0_dram0_pms_monitor_1.rs
index 26ea57c558..0357d0c8fa 100644
--- a/esp32c3/src/sensitive/core_0_dram0_pms_monitor_1.rs
+++ b/esp32c3/src/sensitive/core_0_dram0_pms_monitor_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_PMS_MONITOR_1")
             .field(
                 "core_0_dram0_pms_monitor_violate_clr",
-                &format_args!("{}", self.core_0_dram0_pms_monitor_violate_clr().bit()),
+                &self.core_0_dram0_pms_monitor_violate_clr(),
             )
             .field(
                 "core_0_dram0_pms_monitor_violate_en",
-                &format_args!("{}", self.core_0_dram0_pms_monitor_violate_en().bit()),
+                &self.core_0_dram0_pms_monitor_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_PMS_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - core_0_dram0_pms_monitor_violate_clr"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_dram0_pms_monitor_2.rs b/esp32c3/src/sensitive/core_0_dram0_pms_monitor_2.rs
index 5b961fd00d..c25639b4e5 100644
--- a/esp32c3/src/sensitive/core_0_dram0_pms_monitor_2.rs
+++ b/esp32c3/src/sensitive/core_0_dram0_pms_monitor_2.rs
@@ -42,38 +42,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_PMS_MONITOR_2")
             .field(
                 "core_0_dram0_pms_monitor_violate_intr",
-                &format_args!("{}", self.core_0_dram0_pms_monitor_violate_intr().bit()),
+                &self.core_0_dram0_pms_monitor_violate_intr(),
             )
             .field(
                 "core_0_dram0_pms_monitor_violate_status_lock",
-                &format_args!(
-                    "{}",
-                    self.core_0_dram0_pms_monitor_violate_status_lock().bit()
-                ),
+                &self.core_0_dram0_pms_monitor_violate_status_lock(),
             )
             .field(
                 "core_0_dram0_pms_monitor_violate_status_world",
-                &format_args!(
-                    "{}",
-                    self.core_0_dram0_pms_monitor_violate_status_world().bits()
-                ),
+                &self.core_0_dram0_pms_monitor_violate_status_world(),
             )
             .field(
                 "core_0_dram0_pms_monitor_violate_status_addr",
-                &format_args!(
-                    "{}",
-                    self.core_0_dram0_pms_monitor_violate_status_addr().bits()
-                ),
+                &self.core_0_dram0_pms_monitor_violate_status_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_PMS_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_pms_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_PMS_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_PMS_MONITOR_2_SPEC {
diff --git a/esp32c3/src/sensitive/core_0_dram0_pms_monitor_3.rs b/esp32c3/src/sensitive/core_0_dram0_pms_monitor_3.rs
index e9e1338bb7..0f74bb8ff7 100644
--- a/esp32c3/src/sensitive/core_0_dram0_pms_monitor_3.rs
+++ b/esp32c3/src/sensitive/core_0_dram0_pms_monitor_3.rs
@@ -26,27 +26,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_PMS_MONITOR_3")
             .field(
                 "core_0_dram0_pms_monitor_violate_status_wr",
-                &format_args!(
-                    "{}",
-                    self.core_0_dram0_pms_monitor_violate_status_wr().bit()
-                ),
+                &self.core_0_dram0_pms_monitor_violate_status_wr(),
             )
             .field(
                 "core_0_dram0_pms_monitor_violate_status_byteen",
-                &format_args!(
-                    "{}",
-                    self.core_0_dram0_pms_monitor_violate_status_byteen().bits()
-                ),
+                &self.core_0_dram0_pms_monitor_violate_status_byteen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_PMS_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_pms_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_PMS_MONITOR_3_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_PMS_MONITOR_3_SPEC {
diff --git a/esp32c3/src/sensitive/core_0_iram0_pms_monitor_0.rs b/esp32c3/src/sensitive/core_0_iram0_pms_monitor_0.rs
index 675790cf93..d73b007451 100644
--- a/esp32c3/src/sensitive/core_0_iram0_pms_monitor_0.rs
+++ b/esp32c3/src/sensitive/core_0_iram0_pms_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_PMS_MONITOR_0")
             .field(
                 "core_0_iram0_pms_monitor_lock",
-                &format_args!("{}", self.core_0_iram0_pms_monitor_lock().bit()),
+                &self.core_0_iram0_pms_monitor_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_PMS_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - core_0_iram0_pms_monitor_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_iram0_pms_monitor_1.rs b/esp32c3/src/sensitive/core_0_iram0_pms_monitor_1.rs
index eac1f76878..7093a79290 100644
--- a/esp32c3/src/sensitive/core_0_iram0_pms_monitor_1.rs
+++ b/esp32c3/src/sensitive/core_0_iram0_pms_monitor_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_PMS_MONITOR_1")
             .field(
                 "core_0_iram0_pms_monitor_violate_clr",
-                &format_args!("{}", self.core_0_iram0_pms_monitor_violate_clr().bit()),
+                &self.core_0_iram0_pms_monitor_violate_clr(),
             )
             .field(
                 "core_0_iram0_pms_monitor_violate_en",
-                &format_args!("{}", self.core_0_iram0_pms_monitor_violate_en().bit()),
+                &self.core_0_iram0_pms_monitor_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_PMS_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - core_0_iram0_pms_monitor_violate_clr"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_iram0_pms_monitor_2.rs b/esp32c3/src/sensitive/core_0_iram0_pms_monitor_2.rs
index b1f4cdc51d..00b91e932b 100644
--- a/esp32c3/src/sensitive/core_0_iram0_pms_monitor_2.rs
+++ b/esp32c3/src/sensitive/core_0_iram0_pms_monitor_2.rs
@@ -51,46 +51,27 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_PMS_MONITOR_2")
             .field(
                 "core_0_iram0_pms_monitor_violate_intr",
-                &format_args!("{}", self.core_0_iram0_pms_monitor_violate_intr().bit()),
+                &self.core_0_iram0_pms_monitor_violate_intr(),
             )
             .field(
                 "core_0_iram0_pms_monitor_violate_status_wr",
-                &format_args!(
-                    "{}",
-                    self.core_0_iram0_pms_monitor_violate_status_wr().bit()
-                ),
+                &self.core_0_iram0_pms_monitor_violate_status_wr(),
             )
             .field(
                 "core_0_iram0_pms_monitor_violate_status_loadstore",
-                &format_args!(
-                    "{}",
-                    self.core_0_iram0_pms_monitor_violate_status_loadstore()
-                        .bit()
-                ),
+                &self.core_0_iram0_pms_monitor_violate_status_loadstore(),
             )
             .field(
                 "core_0_iram0_pms_monitor_violate_status_world",
-                &format_args!(
-                    "{}",
-                    self.core_0_iram0_pms_monitor_violate_status_world().bits()
-                ),
+                &self.core_0_iram0_pms_monitor_violate_status_world(),
             )
             .field(
                 "core_0_iram0_pms_monitor_violate_status_addr",
-                &format_args!(
-                    "{}",
-                    self.core_0_iram0_pms_monitor_violate_status_addr().bits()
-                ),
+                &self.core_0_iram0_pms_monitor_violate_status_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_PMS_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_pms_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_IRAM0_PMS_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_0_IRAM0_PMS_MONITOR_2_SPEC {
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_constrain_0.rs b/esp32c3/src/sensitive/core_0_pif_pms_constrain_0.rs
index 1c3b9ece45..03020e7f72 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_constrain_0.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_0")
             .field(
                 "core_0_pif_pms_constrain_lock",
-                &format_args!("{}", self.core_0_pif_pms_constrain_lock().bit()),
+                &self.core_0_pif_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - core_0_pif_pms_constrain_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_constrain_1.rs b/esp32c3/src/sensitive/core_0_pif_pms_constrain_1.rs
index 4761c19643..289133feb1 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_constrain_1.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_constrain_1.rs
@@ -137,65 +137,59 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_1")
             .field(
                 "core_0_pif_pms_constrain_world_0_uart",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_uart().bits()),
+                &self.core_0_pif_pms_constrain_world_0_uart(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_g0spi_1",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_g0spi_1().bits()),
+                &self.core_0_pif_pms_constrain_world_0_g0spi_1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_g0spi_0",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_g0spi_0().bits()),
+                &self.core_0_pif_pms_constrain_world_0_g0spi_0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_gpio",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_gpio().bits()),
+                &self.core_0_pif_pms_constrain_world_0_gpio(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_fe2",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_fe2().bits()),
+                &self.core_0_pif_pms_constrain_world_0_fe2(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_fe",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_fe().bits()),
+                &self.core_0_pif_pms_constrain_world_0_fe(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_timer",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_timer().bits()),
+                &self.core_0_pif_pms_constrain_world_0_timer(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_rtc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_rtc().bits()),
+                &self.core_0_pif_pms_constrain_world_0_rtc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_io_mux",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_io_mux().bits()),
+                &self.core_0_pif_pms_constrain_world_0_io_mux(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_wdg",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_wdg().bits()),
+                &self.core_0_pif_pms_constrain_world_0_wdg(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_misc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_misc().bits()),
+                &self.core_0_pif_pms_constrain_world_0_misc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_i2c",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_i2c().bits()),
+                &self.core_0_pif_pms_constrain_world_0_i2c(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_uart1",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_uart1().bits()),
+                &self.core_0_pif_pms_constrain_world_0_uart1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - core_0_pif_pms_constrain_world_0_uart"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_constrain_10.rs b/esp32c3/src/sensitive/core_0_pif_pms_constrain_10.rs
index 2cf15dbdbb..ea26ec4756 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_constrain_10.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_constrain_10.rs
@@ -54,41 +54,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_10")
             .field(
                 "core_0_pif_pms_constrain_rtcfast_world_0_l",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcfast_world_0_l().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcfast_world_0_l(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcfast_world_0_h",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcfast_world_0_h().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcfast_world_0_h(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcfast_world_1_l",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcfast_world_1_l().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcfast_world_1_l(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcfast_world_1_h",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcfast_world_1_h().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcfast_world_1_h(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - core_0_pif_pms_constrain_rtcfast_world_0_l"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_constrain_2.rs b/esp32c3/src/sensitive/core_0_pif_pms_constrain_2.rs
index a16ee8857b..4befd2f1f0 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_constrain_2.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_constrain_2.rs
@@ -101,61 +101,43 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_2")
             .field(
                 "core_0_pif_pms_constrain_world_0_bt",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_bt().bits()),
+                &self.core_0_pif_pms_constrain_world_0_bt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_i2c_ext0",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_i2c_ext0().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_i2c_ext0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_uhci0",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_uhci0().bits()),
+                &self.core_0_pif_pms_constrain_world_0_uhci0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_rmt",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_rmt().bits()),
+                &self.core_0_pif_pms_constrain_world_0_rmt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_ledc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_ledc().bits()),
+                &self.core_0_pif_pms_constrain_world_0_ledc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_bb",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_bb().bits()),
+                &self.core_0_pif_pms_constrain_world_0_bb(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_timergroup",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_timergroup().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_timergroup(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_timergroup1",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_timergroup1().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_timergroup1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_systimer",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_systimer().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_systimer(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - core_0_pif_pms_constrain_world_0_bt"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_constrain_3.rs b/esp32c3/src/sensitive/core_0_pif_pms_constrain_3.rs
index dcc391d260..b138b044a1 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_constrain_3.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_constrain_3.rs
@@ -79,44 +79,35 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_3")
             .field(
                 "core_0_pif_pms_constrain_world_0_spi_2",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_spi_2().bits()),
+                &self.core_0_pif_pms_constrain_world_0_spi_2(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_apb_ctrl",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_apb_ctrl().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_apb_ctrl(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_can",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_can().bits()),
+                &self.core_0_pif_pms_constrain_world_0_can(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_i2s1",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_i2s1().bits()),
+                &self.core_0_pif_pms_constrain_world_0_i2s1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_rwbt",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_rwbt().bits()),
+                &self.core_0_pif_pms_constrain_world_0_rwbt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_wifimac",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_wifimac().bits()),
+                &self.core_0_pif_pms_constrain_world_0_wifimac(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_pwr",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_pwr().bits()),
+                &self.core_0_pif_pms_constrain_world_0_pwr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - core_0_pif_pms_constrain_world_0_spi_2"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_constrain_4.rs b/esp32c3/src/sensitive/core_0_pif_pms_constrain_4.rs
index 12002a813e..50ebcb6194 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_constrain_4.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_constrain_4.rs
@@ -161,97 +161,63 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_4")
             .field(
                 "core_0_pif_pms_constrain_world_0_usb_wrap",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_usb_wrap().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_usb_wrap(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_crypto_peri",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_crypto_peri().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_crypto_peri(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_crypto_dma",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_crypto_dma().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_crypto_dma(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_apb_adc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_apb_adc().bits()),
+                &self.core_0_pif_pms_constrain_world_0_apb_adc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_bt_pwr",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_bt_pwr().bits()),
+                &self.core_0_pif_pms_constrain_world_0_bt_pwr(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_usb_device",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_usb_device().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_usb_device(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_system",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_system().bits()),
+                &self.core_0_pif_pms_constrain_world_0_system(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_sensitive",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_sensitive().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_sensitive(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_interrupt",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_interrupt().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_interrupt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_dma_copy",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_dma_copy().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_dma_copy(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_cache_config",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_cache_config().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_cache_config(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_ad",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_ad().bits()),
+                &self.core_0_pif_pms_constrain_world_0_ad(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_dio",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_dio().bits()),
+                &self.core_0_pif_pms_constrain_world_0_dio(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_world_controller",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_world_controller()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_world_controller(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 2:3 - core_0_pif_pms_constrain_world_0_usb_wrap"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_constrain_5.rs b/esp32c3/src/sensitive/core_0_pif_pms_constrain_5.rs
index adc3a5db43..8f4eab5b0a 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_constrain_5.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_constrain_5.rs
@@ -137,65 +137,59 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_5")
             .field(
                 "core_0_pif_pms_constrain_world_1_uart",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_uart().bits()),
+                &self.core_0_pif_pms_constrain_world_1_uart(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_g0spi_1",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_g0spi_1().bits()),
+                &self.core_0_pif_pms_constrain_world_1_g0spi_1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_g0spi_0",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_g0spi_0().bits()),
+                &self.core_0_pif_pms_constrain_world_1_g0spi_0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_gpio",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_gpio().bits()),
+                &self.core_0_pif_pms_constrain_world_1_gpio(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_fe2",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_fe2().bits()),
+                &self.core_0_pif_pms_constrain_world_1_fe2(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_fe",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_fe().bits()),
+                &self.core_0_pif_pms_constrain_world_1_fe(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_timer",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_timer().bits()),
+                &self.core_0_pif_pms_constrain_world_1_timer(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_rtc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_rtc().bits()),
+                &self.core_0_pif_pms_constrain_world_1_rtc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_io_mux",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_io_mux().bits()),
+                &self.core_0_pif_pms_constrain_world_1_io_mux(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_wdg",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_wdg().bits()),
+                &self.core_0_pif_pms_constrain_world_1_wdg(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_misc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_misc().bits()),
+                &self.core_0_pif_pms_constrain_world_1_misc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_i2c",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_i2c().bits()),
+                &self.core_0_pif_pms_constrain_world_1_i2c(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_uart1",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_uart1().bits()),
+                &self.core_0_pif_pms_constrain_world_1_uart1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - core_0_pif_pms_constrain_world_1_uart"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_constrain_6.rs b/esp32c3/src/sensitive/core_0_pif_pms_constrain_6.rs
index 29a867840e..83b00da2d2 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_constrain_6.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_constrain_6.rs
@@ -101,61 +101,43 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_6")
             .field(
                 "core_0_pif_pms_constrain_world_1_bt",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_bt().bits()),
+                &self.core_0_pif_pms_constrain_world_1_bt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_i2c_ext0",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_i2c_ext0().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_i2c_ext0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_uhci0",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_uhci0().bits()),
+                &self.core_0_pif_pms_constrain_world_1_uhci0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_rmt",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_rmt().bits()),
+                &self.core_0_pif_pms_constrain_world_1_rmt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_ledc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_ledc().bits()),
+                &self.core_0_pif_pms_constrain_world_1_ledc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_bb",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_bb().bits()),
+                &self.core_0_pif_pms_constrain_world_1_bb(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_timergroup",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_timergroup().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_timergroup(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_timergroup1",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_timergroup1().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_timergroup1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_systimer",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_systimer().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_systimer(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - core_0_pif_pms_constrain_world_1_bt"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_constrain_7.rs b/esp32c3/src/sensitive/core_0_pif_pms_constrain_7.rs
index 198dd0f105..44cf72999a 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_constrain_7.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_constrain_7.rs
@@ -79,44 +79,35 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_7")
             .field(
                 "core_0_pif_pms_constrain_world_1_spi_2",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_spi_2().bits()),
+                &self.core_0_pif_pms_constrain_world_1_spi_2(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_apb_ctrl",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_apb_ctrl().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_apb_ctrl(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_can",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_can().bits()),
+                &self.core_0_pif_pms_constrain_world_1_can(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_i2s1",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_i2s1().bits()),
+                &self.core_0_pif_pms_constrain_world_1_i2s1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_rwbt",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_rwbt().bits()),
+                &self.core_0_pif_pms_constrain_world_1_rwbt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_wifimac",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_wifimac().bits()),
+                &self.core_0_pif_pms_constrain_world_1_wifimac(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_pwr",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_pwr().bits()),
+                &self.core_0_pif_pms_constrain_world_1_pwr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - core_0_pif_pms_constrain_world_1_spi_2"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_constrain_8.rs b/esp32c3/src/sensitive/core_0_pif_pms_constrain_8.rs
index cddefd6690..a4ab2c171f 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_constrain_8.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_constrain_8.rs
@@ -161,97 +161,63 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_8")
             .field(
                 "core_0_pif_pms_constrain_world_1_usb_wrap",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_usb_wrap().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_usb_wrap(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_crypto_peri",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_crypto_peri().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_crypto_peri(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_crypto_dma",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_crypto_dma().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_crypto_dma(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_apb_adc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_apb_adc().bits()),
+                &self.core_0_pif_pms_constrain_world_1_apb_adc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_bt_pwr",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_bt_pwr().bits()),
+                &self.core_0_pif_pms_constrain_world_1_bt_pwr(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_usb_device",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_usb_device().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_usb_device(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_system",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_system().bits()),
+                &self.core_0_pif_pms_constrain_world_1_system(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_sensitive",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_sensitive().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_sensitive(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_interrupt",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_interrupt().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_interrupt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_dma_copy",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_dma_copy().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_dma_copy(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_cache_config",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_cache_config().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_cache_config(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_ad",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_ad().bits()),
+                &self.core_0_pif_pms_constrain_world_1_ad(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_dio",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_dio().bits()),
+                &self.core_0_pif_pms_constrain_world_1_dio(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_world_controller",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_world_controller()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_world_controller(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 2:3 - core_0_pif_pms_constrain_world_1_usb_wrap"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_constrain_9.rs b/esp32c3/src/sensitive/core_0_pif_pms_constrain_9.rs
index 11c4b2260e..f953dab101 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_constrain_9.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_constrain_9.rs
@@ -36,29 +36,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_9")
             .field(
                 "core_0_pif_pms_constrain_rtcfast_spltaddr_world_0",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcfast_spltaddr_world_0()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcfast_spltaddr_world_0(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcfast_spltaddr_world_1",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcfast_spltaddr_world_1()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcfast_spltaddr_world_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - core_0_pif_pms_constrain_rtcfast_spltaddr_world_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_monitor_0.rs b/esp32c3/src/sensitive/core_0_pif_pms_monitor_0.rs
index 47ac594052..05f0a0c41c 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_monitor_0.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_0")
             .field(
                 "core_0_pif_pms_monitor_lock",
-                &format_args!("{}", self.core_0_pif_pms_monitor_lock().bit()),
+                &self.core_0_pif_pms_monitor_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - core_0_pif_pms_monitor_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_monitor_1.rs b/esp32c3/src/sensitive/core_0_pif_pms_monitor_1.rs
index de4e959ce0..fa83fd7c40 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_monitor_1.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_monitor_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_1")
             .field(
                 "core_0_pif_pms_monitor_violate_clr",
-                &format_args!("{}", self.core_0_pif_pms_monitor_violate_clr().bit()),
+                &self.core_0_pif_pms_monitor_violate_clr(),
             )
             .field(
                 "core_0_pif_pms_monitor_violate_en",
-                &format_args!("{}", self.core_0_pif_pms_monitor_violate_en().bit()),
+                &self.core_0_pif_pms_monitor_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - core_0_pif_pms_monitor_violate_clr"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_monitor_2.rs b/esp32c3/src/sensitive/core_0_pif_pms_monitor_2.rs
index 627ef23217..0415a330f6 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_monitor_2.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_monitor_2.rs
@@ -51,45 +51,27 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_2")
             .field(
                 "core_0_pif_pms_monitor_violate_intr",
-                &format_args!("{}", self.core_0_pif_pms_monitor_violate_intr().bit()),
+                &self.core_0_pif_pms_monitor_violate_intr(),
             )
             .field(
                 "core_0_pif_pms_monitor_violate_status_hport_0",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_violate_status_hport_0().bit()
-                ),
+                &self.core_0_pif_pms_monitor_violate_status_hport_0(),
             )
             .field(
                 "core_0_pif_pms_monitor_violate_status_hsize",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_violate_status_hsize().bits()
-                ),
+                &self.core_0_pif_pms_monitor_violate_status_hsize(),
             )
             .field(
                 "core_0_pif_pms_monitor_violate_status_hwrite",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_violate_status_hwrite().bit()
-                ),
+                &self.core_0_pif_pms_monitor_violate_status_hwrite(),
             )
             .field(
                 "core_0_pif_pms_monitor_violate_status_hworld",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_violate_status_hworld().bits()
-                ),
+                &self.core_0_pif_pms_monitor_violate_status_hworld(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_pif_pms_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_PIF_PMS_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_0_PIF_PMS_MONITOR_2_SPEC {
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_monitor_3.rs b/esp32c3/src/sensitive/core_0_pif_pms_monitor_3.rs
index fed7f30616..044f01f921 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_monitor_3.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_monitor_3.rs
@@ -17,20 +17,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_3")
             .field(
                 "core_0_pif_pms_monitor_violate_status_haddr",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_violate_status_haddr().bits()
-                ),
+                &self.core_0_pif_pms_monitor_violate_status_haddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_pif_pms_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_PIF_PMS_MONITOR_3_SPEC;
 impl crate::RegisterSpec for CORE_0_PIF_PMS_MONITOR_3_SPEC {
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_monitor_4.rs b/esp32c3/src/sensitive/core_0_pif_pms_monitor_4.rs
index 57f9ec0581..caf9c97eb6 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_monitor_4.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_monitor_4.rs
@@ -32,24 +32,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_4")
             .field(
                 "core_0_pif_pms_monitor_nonword_violate_clr",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_nonword_violate_clr().bit()
-                ),
+                &self.core_0_pif_pms_monitor_nonword_violate_clr(),
             )
             .field(
                 "core_0_pif_pms_monitor_nonword_violate_en",
-                &format_args!("{}", self.core_0_pif_pms_monitor_nonword_violate_en().bit()),
+                &self.core_0_pif_pms_monitor_nonword_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - core_0_pif_pms_monitor_nonword_violate_clr"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_monitor_5.rs b/esp32c3/src/sensitive/core_0_pif_pms_monitor_5.rs
index d65c7cc1f3..2b049ce28c 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_monitor_5.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_monitor_5.rs
@@ -35,36 +35,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_5")
             .field(
                 "core_0_pif_pms_monitor_nonword_violate_intr",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_nonword_violate_intr().bit()
-                ),
+                &self.core_0_pif_pms_monitor_nonword_violate_intr(),
             )
             .field(
                 "core_0_pif_pms_monitor_nonword_violate_status_hsize",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_nonword_violate_status_hsize()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_monitor_nonword_violate_status_hsize(),
             )
             .field(
                 "core_0_pif_pms_monitor_nonword_violate_status_hworld",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_nonword_violate_status_hworld()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_monitor_nonword_violate_status_hworld(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_pif_pms_monitor_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_PIF_PMS_MONITOR_5_SPEC;
 impl crate::RegisterSpec for CORE_0_PIF_PMS_MONITOR_5_SPEC {
diff --git a/esp32c3/src/sensitive/core_0_pif_pms_monitor_6.rs b/esp32c3/src/sensitive/core_0_pif_pms_monitor_6.rs
index 671fb4a09e..ad326ae9fa 100644
--- a/esp32c3/src/sensitive/core_0_pif_pms_monitor_6.rs
+++ b/esp32c3/src/sensitive/core_0_pif_pms_monitor_6.rs
@@ -17,21 +17,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_6")
             .field(
                 "core_0_pif_pms_monitor_nonword_violate_status_haddr",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_nonword_violate_status_haddr()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_monitor_nonword_violate_status_haddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_pif_pms_monitor_6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_PIF_PMS_MONITOR_6_SPEC;
 impl crate::RegisterSpec for CORE_0_PIF_PMS_MONITOR_6_SPEC {
diff --git a/esp32c3/src/sensitive/core_x_dram0_pms_constrain_0.rs b/esp32c3/src/sensitive/core_x_dram0_pms_constrain_0.rs
index b9e98b3579..3d4f31d1fb 100644
--- a/esp32c3/src/sensitive/core_x_dram0_pms_constrain_0.rs
+++ b/esp32c3/src/sensitive/core_x_dram0_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_DRAM0_PMS_CONSTRAIN_0")
             .field(
                 "core_x_dram0_pms_constrain_lock",
-                &format_args!("{}", self.core_x_dram0_pms_constrain_lock().bit()),
+                &self.core_x_dram0_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_DRAM0_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - core_x_dram0_pms_constrain_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_x_dram0_pms_constrain_1.rs b/esp32c3/src/sensitive/core_x_dram0_pms_constrain_1.rs
index ebe06d0baa..bddeb70d80 100644
--- a/esp32c3/src/sensitive/core_x_dram0_pms_constrain_1.rs
+++ b/esp32c3/src/sensitive/core_x_dram0_pms_constrain_1.rs
@@ -120,83 +120,47 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_DRAM0_PMS_CONSTRAIN_1")
             .field(
                 "core_x_dram0_pms_constrain_sram_world_0_pms_0",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_0_pms_0().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_0_pms_0(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_0_pms_1",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_0_pms_1().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_0_pms_1(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_0_pms_2",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_0_pms_2().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_0_pms_2(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_0_pms_3",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_0_pms_3().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_0_pms_3(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_1_pms_0",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_1_pms_0().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_1_pms_0(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_1_pms_1",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_1_pms_1().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_1_pms_1(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_1_pms_2",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_1_pms_2().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_1_pms_2(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_1_pms_3",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_1_pms_3().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_1_pms_3(),
             )
             .field(
                 "core_x_dram0_pms_constrain_rom_world_0_pms",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_rom_world_0_pms().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_rom_world_0_pms(),
             )
             .field(
                 "core_x_dram0_pms_constrain_rom_world_1_pms",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_rom_world_1_pms().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_rom_world_1_pms(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_DRAM0_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - core_x_dram0_pms_constrain_sram_world_0_pms_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_0.rs b/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_0.rs
index 1c9e4d4902..53a67f188d 100644
--- a/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_0.rs
+++ b/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_0.rs
@@ -21,21 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0")
             .field(
                 "core_x_iram0_dram0_dma_split_line_constrain_lock",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_dram0_dma_split_line_constrain_lock()
-                        .bit()
-                ),
+                &self.core_x_iram0_dram0_dma_split_line_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - core_x_iram0_dram0_dma_split_line_constrain_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_1.rs b/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_1.rs
index 77476524de..df9546475f 100644
--- a/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_1.rs
+++ b/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_1.rs
@@ -52,29 +52,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1")
             .field(
                 "core_x_iram0_dram0_dma_sram_category_0",
-                &format_args!("{}", self.core_x_iram0_dram0_dma_sram_category_0().bits()),
+                &self.core_x_iram0_dram0_dma_sram_category_0(),
             )
             .field(
                 "core_x_iram0_dram0_dma_sram_category_1",
-                &format_args!("{}", self.core_x_iram0_dram0_dma_sram_category_1().bits()),
+                &self.core_x_iram0_dram0_dma_sram_category_1(),
             )
             .field(
                 "core_x_iram0_dram0_dma_sram_category_2",
-                &format_args!("{}", self.core_x_iram0_dram0_dma_sram_category_2().bits()),
+                &self.core_x_iram0_dram0_dma_sram_category_2(),
             )
             .field(
                 "core_x_iram0_dram0_dma_sram_splitaddr",
-                &format_args!("{}", self.core_x_iram0_dram0_dma_sram_splitaddr().bits()),
+                &self.core_x_iram0_dram0_dma_sram_splitaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - core_x_iram0_dram0_dma_sram_category_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_2.rs b/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_2.rs
index 21005468b7..151c397d38 100644
--- a/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_2.rs
+++ b/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_2.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2")
             .field(
                 "core_x_iram0_sram_line_0_category_0",
-                &format_args!("{}", self.core_x_iram0_sram_line_0_category_0().bits()),
+                &self.core_x_iram0_sram_line_0_category_0(),
             )
             .field(
                 "core_x_iram0_sram_line_0_category_1",
-                &format_args!("{}", self.core_x_iram0_sram_line_0_category_1().bits()),
+                &self.core_x_iram0_sram_line_0_category_1(),
             )
             .field(
                 "core_x_iram0_sram_line_0_category_2",
-                &format_args!("{}", self.core_x_iram0_sram_line_0_category_2().bits()),
+                &self.core_x_iram0_sram_line_0_category_2(),
             )
             .field(
                 "core_x_iram0_sram_line_0_splitaddr",
-                &format_args!("{}", self.core_x_iram0_sram_line_0_splitaddr().bits()),
+                &self.core_x_iram0_sram_line_0_splitaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - core_x_iram0_sram_line_0_category_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_3.rs b/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_3.rs
index 1374d614a3..26f4653438 100644
--- a/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_3.rs
+++ b/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_3.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3")
             .field(
                 "core_x_iram0_sram_line_1_category_0",
-                &format_args!("{}", self.core_x_iram0_sram_line_1_category_0().bits()),
+                &self.core_x_iram0_sram_line_1_category_0(),
             )
             .field(
                 "core_x_iram0_sram_line_1_category_1",
-                &format_args!("{}", self.core_x_iram0_sram_line_1_category_1().bits()),
+                &self.core_x_iram0_sram_line_1_category_1(),
             )
             .field(
                 "core_x_iram0_sram_line_1_category_2",
-                &format_args!("{}", self.core_x_iram0_sram_line_1_category_2().bits()),
+                &self.core_x_iram0_sram_line_1_category_2(),
             )
             .field(
                 "core_x_iram0_sram_line_1_splitaddr",
-                &format_args!("{}", self.core_x_iram0_sram_line_1_splitaddr().bits()),
+                &self.core_x_iram0_sram_line_1_splitaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - core_x_iram0_sram_line_1_category_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_4.rs b/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_4.rs
index 350ab406cf..1e0c64c613 100644
--- a/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_4.rs
+++ b/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_4.rs
@@ -54,29 +54,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4")
             .field(
                 "core_x_dram0_dma_sram_line_0_category_0",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_0_category_0().bits()),
+                &self.core_x_dram0_dma_sram_line_0_category_0(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_0_category_1",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_0_category_1().bits()),
+                &self.core_x_dram0_dma_sram_line_0_category_1(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_0_category_2",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_0_category_2().bits()),
+                &self.core_x_dram0_dma_sram_line_0_category_2(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_0_splitaddr",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_0_splitaddr().bits()),
+                &self.core_x_dram0_dma_sram_line_0_splitaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - core_x_dram0_dma_sram_line_0_category_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_5.rs b/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_5.rs
index c8de684aeb..e92106b38b 100644
--- a/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_5.rs
+++ b/esp32c3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_5.rs
@@ -54,29 +54,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5")
             .field(
                 "core_x_dram0_dma_sram_line_1_category_0",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_1_category_0().bits()),
+                &self.core_x_dram0_dma_sram_line_1_category_0(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_1_category_1",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_1_category_1().bits()),
+                &self.core_x_dram0_dma_sram_line_1_category_1(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_1_category_2",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_1_category_2().bits()),
+                &self.core_x_dram0_dma_sram_line_1_category_2(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_1_splitaddr",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_1_splitaddr().bits()),
+                &self.core_x_dram0_dma_sram_line_1_splitaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - core_x_dram0_dma_sram_line_1_category_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_x_iram0_pms_constrain_0.rs b/esp32c3/src/sensitive/core_x_iram0_pms_constrain_0.rs
index d29e35ce22..2e08881358 100644
--- a/esp32c3/src/sensitive/core_x_iram0_pms_constrain_0.rs
+++ b/esp32c3/src/sensitive/core_x_iram0_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_PMS_CONSTRAIN_0")
             .field(
                 "core_x_iram0_pms_constrain_lock",
-                &format_args!("{}", self.core_x_iram0_pms_constrain_lock().bit()),
+                &self.core_x_iram0_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - core_x_iram0_pms_constrain_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_x_iram0_pms_constrain_1.rs b/esp32c3/src/sensitive/core_x_iram0_pms_constrain_1.rs
index a23a300fe1..bd4f8dfd36 100644
--- a/esp32c3/src/sensitive/core_x_iram0_pms_constrain_1.rs
+++ b/esp32c3/src/sensitive/core_x_iram0_pms_constrain_1.rs
@@ -79,56 +79,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_PMS_CONSTRAIN_1")
             .field(
                 "core_x_iram0_pms_constrain_sram_world_1_pms_0",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_1_pms_0().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_1_pms_0(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_1_pms_1",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_1_pms_1().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_1_pms_1(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_1_pms_2",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_1_pms_2().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_1_pms_2(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_1_pms_3",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_1_pms_3().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_1_pms_3(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0(),
             )
             .field(
                 "core_x_iram0_pms_constrain_rom_world_1_pms",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_rom_world_1_pms().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_rom_world_1_pms(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - core_x_iram0_pms_constrain_sram_world_1_pms_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/core_x_iram0_pms_constrain_2.rs b/esp32c3/src/sensitive/core_x_iram0_pms_constrain_2.rs
index 1623806360..256cd0b1db 100644
--- a/esp32c3/src/sensitive/core_x_iram0_pms_constrain_2.rs
+++ b/esp32c3/src/sensitive/core_x_iram0_pms_constrain_2.rs
@@ -79,56 +79,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_PMS_CONSTRAIN_2")
             .field(
                 "core_x_iram0_pms_constrain_sram_world_0_pms_0",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_0_pms_0().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_0_pms_0(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_0_pms_1",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_0_pms_1().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_0_pms_1(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_0_pms_2",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_0_pms_2().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_0_pms_2(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_0_pms_3",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_0_pms_3().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_0_pms_3(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0(),
             )
             .field(
                 "core_x_iram0_pms_constrain_rom_world_0_pms",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_rom_world_0_pms().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_rom_world_0_pms(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_PMS_CONSTRAIN_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - core_x_iram0_pms_constrain_sram_world_0_pms_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/date.rs b/esp32c3/src/sensitive/date.rs
index 2ee76a5f12..e7364ca4de 100644
--- a/esp32c3/src/sensitive/date.rs
+++ b/esp32c3/src/sensitive/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_0.rs b/esp32c3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_0.rs
index 4fcbec427b..c6d312c47e 100644
--- a/esp32c3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_0.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_0.rs
@@ -21,17 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_adc_dac_pms_constrain_lock().bit()),
+                &self.dma_apbperi_adc_dac_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - dma_apbperi_adc_dac_pms_constrain_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_1.rs b/esp32c3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_1.rs
index 9f5babc18a..b56edcdb91 100644
--- a/esp32c3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_1.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_1.rs
@@ -106,77 +106,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0(),
             )
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1(),
             )
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2(),
             )
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3(),
             )
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0(),
             )
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1(),
             )
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2(),
             )
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_aes_pms_constrain_0.rs b/esp32c3/src/sensitive/dma_apbperi_aes_pms_constrain_0.rs
index ff3a12e288..c9da13b34a 100644
--- a/esp32c3/src/sensitive/dma_apbperi_aes_pms_constrain_0.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_aes_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_AES_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_aes_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_aes_pms_constrain_lock().bit()),
+                &self.dma_apbperi_aes_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_AES_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - dma_apbperi_aes_pms_constrain_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_aes_pms_constrain_1.rs b/esp32c3/src/sensitive/dma_apbperi_aes_pms_constrain_1.rs
index aacd93f4ac..5bda58b12c 100644
--- a/esp32c3/src/sensitive/dma_apbperi_aes_pms_constrain_1.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_aes_pms_constrain_1.rs
@@ -106,77 +106,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_AES_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_aes_pms_constrain_sram_world_0_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_aes_pms_constrain_sram_world_0_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_aes_pms_constrain_sram_world_0_pms_0(),
             )
             .field(
                 "dma_apbperi_aes_pms_constrain_sram_world_0_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_aes_pms_constrain_sram_world_0_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_aes_pms_constrain_sram_world_0_pms_1(),
             )
             .field(
                 "dma_apbperi_aes_pms_constrain_sram_world_0_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_aes_pms_constrain_sram_world_0_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_aes_pms_constrain_sram_world_0_pms_2(),
             )
             .field(
                 "dma_apbperi_aes_pms_constrain_sram_world_0_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_aes_pms_constrain_sram_world_0_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_aes_pms_constrain_sram_world_0_pms_3(),
             )
             .field(
                 "dma_apbperi_aes_pms_constrain_sram_world_1_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_aes_pms_constrain_sram_world_1_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_aes_pms_constrain_sram_world_1_pms_0(),
             )
             .field(
                 "dma_apbperi_aes_pms_constrain_sram_world_1_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_aes_pms_constrain_sram_world_1_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_aes_pms_constrain_sram_world_1_pms_1(),
             )
             .field(
                 "dma_apbperi_aes_pms_constrain_sram_world_1_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_aes_pms_constrain_sram_world_1_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_aes_pms_constrain_sram_world_1_pms_2(),
             )
             .field(
                 "dma_apbperi_aes_pms_constrain_sram_world_1_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_aes_pms_constrain_sram_world_1_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_aes_pms_constrain_sram_world_1_pms_3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_AES_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - dma_apbperi_aes_pms_constrain_sram_world_0_pms_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_backup_pms_constrain_0.rs b/esp32c3/src/sensitive/dma_apbperi_backup_pms_constrain_0.rs
index 6718f07696..06db30b51f 100644
--- a/esp32c3/src/sensitive/dma_apbperi_backup_pms_constrain_0.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_backup_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_backup_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_backup_pms_constrain_lock().bit()),
+                &self.dma_apbperi_backup_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - dma_apbperi_backup_pms_constrain_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_backup_pms_constrain_1.rs b/esp32c3/src/sensitive/dma_apbperi_backup_pms_constrain_1.rs
index a12bd3ff8e..3586274b52 100644
--- a/esp32c3/src/sensitive/dma_apbperi_backup_pms_constrain_1.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_backup_pms_constrain_1.rs
@@ -106,77 +106,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_backup_pms_constrain_sram_world_0_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_backup_pms_constrain_sram_world_0_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_backup_pms_constrain_sram_world_0_pms_0(),
             )
             .field(
                 "dma_apbperi_backup_pms_constrain_sram_world_0_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_backup_pms_constrain_sram_world_0_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_backup_pms_constrain_sram_world_0_pms_1(),
             )
             .field(
                 "dma_apbperi_backup_pms_constrain_sram_world_0_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_backup_pms_constrain_sram_world_0_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_backup_pms_constrain_sram_world_0_pms_2(),
             )
             .field(
                 "dma_apbperi_backup_pms_constrain_sram_world_0_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_backup_pms_constrain_sram_world_0_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_backup_pms_constrain_sram_world_0_pms_3(),
             )
             .field(
                 "dma_apbperi_backup_pms_constrain_sram_world_1_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_backup_pms_constrain_sram_world_1_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_backup_pms_constrain_sram_world_1_pms_0(),
             )
             .field(
                 "dma_apbperi_backup_pms_constrain_sram_world_1_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_backup_pms_constrain_sram_world_1_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_backup_pms_constrain_sram_world_1_pms_1(),
             )
             .field(
                 "dma_apbperi_backup_pms_constrain_sram_world_1_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_backup_pms_constrain_sram_world_1_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_backup_pms_constrain_sram_world_1_pms_2(),
             )
             .field(
                 "dma_apbperi_backup_pms_constrain_sram_world_1_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_backup_pms_constrain_sram_world_1_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_backup_pms_constrain_sram_world_1_pms_3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - dma_apbperi_backup_pms_constrain_sram_world_0_pms_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_i2s0_pms_constrain_0.rs b/esp32c3/src/sensitive/dma_apbperi_i2s0_pms_constrain_0.rs
index 40cd9aa04b..51a018dfe2 100644
--- a/esp32c3/src/sensitive/dma_apbperi_i2s0_pms_constrain_0.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_i2s0_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_I2S0_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_i2s0_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_i2s0_pms_constrain_lock().bit()),
+                &self.dma_apbperi_i2s0_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - dma_apbperi_i2s0_pms_constrain_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_i2s0_pms_constrain_1.rs b/esp32c3/src/sensitive/dma_apbperi_i2s0_pms_constrain_1.rs
index 1b2f830332..b781c1c938 100644
--- a/esp32c3/src/sensitive/dma_apbperi_i2s0_pms_constrain_1.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_i2s0_pms_constrain_1.rs
@@ -106,77 +106,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_I2S0_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0(),
             )
             .field(
                 "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1(),
             )
             .field(
                 "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2(),
             )
             .field(
                 "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3(),
             )
             .field(
                 "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0(),
             )
             .field(
                 "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1(),
             )
             .field(
                 "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2(),
             )
             .field(
                 "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_lc_pms_constrain_0.rs b/esp32c3/src/sensitive/dma_apbperi_lc_pms_constrain_0.rs
index 8f942ef8dd..56afb34b8b 100644
--- a/esp32c3/src/sensitive/dma_apbperi_lc_pms_constrain_0.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_lc_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_LC_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_lc_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_lc_pms_constrain_lock().bit()),
+                &self.dma_apbperi_lc_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_LC_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - dma_apbperi_lc_pms_constrain_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_lc_pms_constrain_1.rs b/esp32c3/src/sensitive/dma_apbperi_lc_pms_constrain_1.rs
index bd36ea58a2..95ceb82307 100644
--- a/esp32c3/src/sensitive/dma_apbperi_lc_pms_constrain_1.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_lc_pms_constrain_1.rs
@@ -106,77 +106,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_LC_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_lc_pms_constrain_sram_world_0_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lc_pms_constrain_sram_world_0_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_lc_pms_constrain_sram_world_0_pms_0(),
             )
             .field(
                 "dma_apbperi_lc_pms_constrain_sram_world_0_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lc_pms_constrain_sram_world_0_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_lc_pms_constrain_sram_world_0_pms_1(),
             )
             .field(
                 "dma_apbperi_lc_pms_constrain_sram_world_0_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lc_pms_constrain_sram_world_0_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_lc_pms_constrain_sram_world_0_pms_2(),
             )
             .field(
                 "dma_apbperi_lc_pms_constrain_sram_world_0_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lc_pms_constrain_sram_world_0_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_lc_pms_constrain_sram_world_0_pms_3(),
             )
             .field(
                 "dma_apbperi_lc_pms_constrain_sram_world_1_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lc_pms_constrain_sram_world_1_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_lc_pms_constrain_sram_world_1_pms_0(),
             )
             .field(
                 "dma_apbperi_lc_pms_constrain_sram_world_1_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lc_pms_constrain_sram_world_1_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_lc_pms_constrain_sram_world_1_pms_1(),
             )
             .field(
                 "dma_apbperi_lc_pms_constrain_sram_world_1_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lc_pms_constrain_sram_world_1_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_lc_pms_constrain_sram_world_1_pms_2(),
             )
             .field(
                 "dma_apbperi_lc_pms_constrain_sram_world_1_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lc_pms_constrain_sram_world_1_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_lc_pms_constrain_sram_world_1_pms_3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_LC_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - dma_apbperi_lc_pms_constrain_sram_world_0_pms_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_mac_pms_constrain_0.rs b/esp32c3/src/sensitive/dma_apbperi_mac_pms_constrain_0.rs
index 8ad1296af3..367660793e 100644
--- a/esp32c3/src/sensitive/dma_apbperi_mac_pms_constrain_0.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_mac_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_MAC_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_mac_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_mac_pms_constrain_lock().bit()),
+                &self.dma_apbperi_mac_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_MAC_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - dma_apbperi_mac_pms_constrain_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_mac_pms_constrain_1.rs b/esp32c3/src/sensitive/dma_apbperi_mac_pms_constrain_1.rs
index b977965a16..06dbf25fa3 100644
--- a/esp32c3/src/sensitive/dma_apbperi_mac_pms_constrain_1.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_mac_pms_constrain_1.rs
@@ -106,77 +106,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_MAC_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_mac_pms_constrain_sram_world_0_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_mac_pms_constrain_sram_world_0_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_mac_pms_constrain_sram_world_0_pms_0(),
             )
             .field(
                 "dma_apbperi_mac_pms_constrain_sram_world_0_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_mac_pms_constrain_sram_world_0_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_mac_pms_constrain_sram_world_0_pms_1(),
             )
             .field(
                 "dma_apbperi_mac_pms_constrain_sram_world_0_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_mac_pms_constrain_sram_world_0_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_mac_pms_constrain_sram_world_0_pms_2(),
             )
             .field(
                 "dma_apbperi_mac_pms_constrain_sram_world_0_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_mac_pms_constrain_sram_world_0_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_mac_pms_constrain_sram_world_0_pms_3(),
             )
             .field(
                 "dma_apbperi_mac_pms_constrain_sram_world_1_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_mac_pms_constrain_sram_world_1_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_mac_pms_constrain_sram_world_1_pms_0(),
             )
             .field(
                 "dma_apbperi_mac_pms_constrain_sram_world_1_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_mac_pms_constrain_sram_world_1_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_mac_pms_constrain_sram_world_1_pms_1(),
             )
             .field(
                 "dma_apbperi_mac_pms_constrain_sram_world_1_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_mac_pms_constrain_sram_world_1_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_mac_pms_constrain_sram_world_1_pms_2(),
             )
             .field(
                 "dma_apbperi_mac_pms_constrain_sram_world_1_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_mac_pms_constrain_sram_world_1_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_mac_pms_constrain_sram_world_1_pms_3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_MAC_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - dma_apbperi_mac_pms_constrain_sram_world_0_pms_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_pms_monitor_0.rs b/esp32c3/src/sensitive/dma_apbperi_pms_monitor_0.rs
index 1fbe71831d..31b9e1d52a 100644
--- a/esp32c3/src/sensitive/dma_apbperi_pms_monitor_0.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_pms_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_PMS_MONITOR_0")
             .field(
                 "dma_apbperi_pms_monitor_lock",
-                &format_args!("{}", self.dma_apbperi_pms_monitor_lock().bit()),
+                &self.dma_apbperi_pms_monitor_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_PMS_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - dma_apbperi_pms_monitor_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_pms_monitor_1.rs b/esp32c3/src/sensitive/dma_apbperi_pms_monitor_1.rs
index f5b18b3a3a..8aee0bf3ff 100644
--- a/esp32c3/src/sensitive/dma_apbperi_pms_monitor_1.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_pms_monitor_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_PMS_MONITOR_1")
             .field(
                 "dma_apbperi_pms_monitor_violate_clr",
-                &format_args!("{}", self.dma_apbperi_pms_monitor_violate_clr().bit()),
+                &self.dma_apbperi_pms_monitor_violate_clr(),
             )
             .field(
                 "dma_apbperi_pms_monitor_violate_en",
-                &format_args!("{}", self.dma_apbperi_pms_monitor_violate_en().bit()),
+                &self.dma_apbperi_pms_monitor_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_PMS_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - dma_apbperi_pms_monitor_violate_clr"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_pms_monitor_2.rs b/esp32c3/src/sensitive/dma_apbperi_pms_monitor_2.rs
index 828244d4df..5ddee725bb 100644
--- a/esp32c3/src/sensitive/dma_apbperi_pms_monitor_2.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_pms_monitor_2.rs
@@ -33,31 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_PMS_MONITOR_2")
             .field(
                 "dma_apbperi_pms_monitor_violate_intr",
-                &format_args!("{}", self.dma_apbperi_pms_monitor_violate_intr().bit()),
+                &self.dma_apbperi_pms_monitor_violate_intr(),
             )
             .field(
                 "dma_apbperi_pms_monitor_violate_status_world",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_pms_monitor_violate_status_world().bits()
-                ),
+                &self.dma_apbperi_pms_monitor_violate_status_world(),
             )
             .field(
                 "dma_apbperi_pms_monitor_violate_status_addr",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_pms_monitor_violate_status_addr().bits()
-                ),
+                &self.dma_apbperi_pms_monitor_violate_status_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_PMS_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_apbperi_pms_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_APBPERI_PMS_MONITOR_2_SPEC;
 impl crate::RegisterSpec for DMA_APBPERI_PMS_MONITOR_2_SPEC {
diff --git a/esp32c3/src/sensitive/dma_apbperi_pms_monitor_3.rs b/esp32c3/src/sensitive/dma_apbperi_pms_monitor_3.rs
index 5267da523d..93805549d2 100644
--- a/esp32c3/src/sensitive/dma_apbperi_pms_monitor_3.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_pms_monitor_3.rs
@@ -26,24 +26,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_PMS_MONITOR_3")
             .field(
                 "dma_apbperi_pms_monitor_violate_status_wr",
-                &format_args!("{}", self.dma_apbperi_pms_monitor_violate_status_wr().bit()),
+                &self.dma_apbperi_pms_monitor_violate_status_wr(),
             )
             .field(
                 "dma_apbperi_pms_monitor_violate_status_byteen",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_pms_monitor_violate_status_byteen().bits()
-                ),
+                &self.dma_apbperi_pms_monitor_violate_status_byteen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_PMS_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_apbperi_pms_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_APBPERI_PMS_MONITOR_3_SPEC;
 impl crate::RegisterSpec for DMA_APBPERI_PMS_MONITOR_3_SPEC {
diff --git a/esp32c3/src/sensitive/dma_apbperi_sha_pms_constrain_0.rs b/esp32c3/src/sensitive/dma_apbperi_sha_pms_constrain_0.rs
index 72d4232d4c..86d2e5b476 100644
--- a/esp32c3/src/sensitive/dma_apbperi_sha_pms_constrain_0.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_sha_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_SHA_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_sha_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_sha_pms_constrain_lock().bit()),
+                &self.dma_apbperi_sha_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_SHA_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - dma_apbperi_sha_pms_constrain_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_sha_pms_constrain_1.rs b/esp32c3/src/sensitive/dma_apbperi_sha_pms_constrain_1.rs
index d725416301..98bd5ccee4 100644
--- a/esp32c3/src/sensitive/dma_apbperi_sha_pms_constrain_1.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_sha_pms_constrain_1.rs
@@ -106,77 +106,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_SHA_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_sha_pms_constrain_sram_world_0_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sha_pms_constrain_sram_world_0_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_sha_pms_constrain_sram_world_0_pms_0(),
             )
             .field(
                 "dma_apbperi_sha_pms_constrain_sram_world_0_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sha_pms_constrain_sram_world_0_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_sha_pms_constrain_sram_world_0_pms_1(),
             )
             .field(
                 "dma_apbperi_sha_pms_constrain_sram_world_0_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sha_pms_constrain_sram_world_0_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_sha_pms_constrain_sram_world_0_pms_2(),
             )
             .field(
                 "dma_apbperi_sha_pms_constrain_sram_world_0_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sha_pms_constrain_sram_world_0_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_sha_pms_constrain_sram_world_0_pms_3(),
             )
             .field(
                 "dma_apbperi_sha_pms_constrain_sram_world_1_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sha_pms_constrain_sram_world_1_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_sha_pms_constrain_sram_world_1_pms_0(),
             )
             .field(
                 "dma_apbperi_sha_pms_constrain_sram_world_1_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sha_pms_constrain_sram_world_1_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_sha_pms_constrain_sram_world_1_pms_1(),
             )
             .field(
                 "dma_apbperi_sha_pms_constrain_sram_world_1_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sha_pms_constrain_sram_world_1_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_sha_pms_constrain_sram_world_1_pms_2(),
             )
             .field(
                 "dma_apbperi_sha_pms_constrain_sram_world_1_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sha_pms_constrain_sram_world_1_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_sha_pms_constrain_sram_world_1_pms_3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_SHA_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - dma_apbperi_sha_pms_constrain_sram_world_0_pms_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_spi2_pms_constrain_0.rs b/esp32c3/src/sensitive/dma_apbperi_spi2_pms_constrain_0.rs
index 07b5c897f1..ca712fefa7 100644
--- a/esp32c3/src/sensitive/dma_apbperi_spi2_pms_constrain_0.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_spi2_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_SPI2_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_spi2_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_spi2_pms_constrain_lock().bit()),
+                &self.dma_apbperi_spi2_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - dma_apbperi_spi2_pms_constrain_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_spi2_pms_constrain_1.rs b/esp32c3/src/sensitive/dma_apbperi_spi2_pms_constrain_1.rs
index 3ef068c4cd..8c1b52dedf 100644
--- a/esp32c3/src/sensitive/dma_apbperi_spi2_pms_constrain_1.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_spi2_pms_constrain_1.rs
@@ -106,77 +106,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_SPI2_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0(),
             )
             .field(
                 "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1(),
             )
             .field(
                 "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2(),
             )
             .field(
                 "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3(),
             )
             .field(
                 "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0(),
             )
             .field(
                 "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1(),
             )
             .field(
                 "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2(),
             )
             .field(
                 "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_uchi0_pms_constrain_0.rs b/esp32c3/src/sensitive/dma_apbperi_uchi0_pms_constrain_0.rs
index 268d7dde87..929acb1f1e 100644
--- a/esp32c3/src/sensitive/dma_apbperi_uchi0_pms_constrain_0.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_uchi0_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_uchi0_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_uchi0_pms_constrain_lock().bit()),
+                &self.dma_apbperi_uchi0_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - dma_apbperi_uchi0_pms_constrain_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/dma_apbperi_uchi0_pms_constrain_1.rs b/esp32c3/src/sensitive/dma_apbperi_uchi0_pms_constrain_1.rs
index a3ad7826a3..4dc41d1e08 100644
--- a/esp32c3/src/sensitive/dma_apbperi_uchi0_pms_constrain_1.rs
+++ b/esp32c3/src/sensitive/dma_apbperi_uchi0_pms_constrain_1.rs
@@ -106,77 +106,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0(),
             )
             .field(
                 "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1(),
             )
             .field(
                 "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2(),
             )
             .field(
                 "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3(),
             )
             .field(
                 "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0(),
             )
             .field(
                 "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1(),
             )
             .field(
                 "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2()
-                        .bits()
-                ),
+                &self.dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2(),
             )
             .field(
                 "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3()
-                        .bits()
-                ),
+                &self.dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/internal_sram_usage_0.rs b/esp32c3/src/sensitive/internal_sram_usage_0.rs
index 0dd269d007..7b28ee0a44 100644
--- a/esp32c3/src/sensitive/internal_sram_usage_0.rs
+++ b/esp32c3/src/sensitive/internal_sram_usage_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERNAL_SRAM_USAGE_0")
-            .field(
-                "internal_sram_usage_lock",
-                &format_args!("{}", self.internal_sram_usage_lock().bit()),
-            )
+            .field("internal_sram_usage_lock", &self.internal_sram_usage_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERNAL_SRAM_USAGE_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - internal_sram_usage_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/internal_sram_usage_1.rs b/esp32c3/src/sensitive/internal_sram_usage_1.rs
index 6c823797fb..f6007f6860 100644
--- a/esp32c3/src/sensitive/internal_sram_usage_1.rs
+++ b/esp32c3/src/sensitive/internal_sram_usage_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTERNAL_SRAM_USAGE_1")
             .field(
                 "internal_sram_usage_cpu_cache",
-                &format_args!("{}", self.internal_sram_usage_cpu_cache().bit()),
+                &self.internal_sram_usage_cpu_cache(),
             )
             .field(
                 "internal_sram_usage_cpu_sram",
-                &format_args!("{}", self.internal_sram_usage_cpu_sram().bits()),
+                &self.internal_sram_usage_cpu_sram(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERNAL_SRAM_USAGE_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - internal_sram_usage_cpu_cache"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/internal_sram_usage_3.rs b/esp32c3/src/sensitive/internal_sram_usage_3.rs
index a647055f78..d26534df87 100644
--- a/esp32c3/src/sensitive/internal_sram_usage_3.rs
+++ b/esp32c3/src/sensitive/internal_sram_usage_3.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTERNAL_SRAM_USAGE_3")
             .field(
                 "internal_sram_usage_mac_dump_sram",
-                &format_args!("{}", self.internal_sram_usage_mac_dump_sram().bits()),
+                &self.internal_sram_usage_mac_dump_sram(),
             )
             .field(
                 "internal_sram_alloc_mac_dump",
-                &format_args!("{}", self.internal_sram_alloc_mac_dump().bit()),
+                &self.internal_sram_alloc_mac_dump(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERNAL_SRAM_USAGE_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - internal_sram_usage_mac_dump_sram"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/internal_sram_usage_4.rs b/esp32c3/src/sensitive/internal_sram_usage_4.rs
index 54b3049177..4dcb3f740f 100644
--- a/esp32c3/src/sensitive/internal_sram_usage_4.rs
+++ b/esp32c3/src/sensitive/internal_sram_usage_4.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTERNAL_SRAM_USAGE_4")
             .field(
                 "internal_sram_usage_log_sram",
-                &format_args!("{}", self.internal_sram_usage_log_sram().bit()),
+                &self.internal_sram_usage_log_sram(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERNAL_SRAM_USAGE_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - internal_sram_usage_log_sram"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/privilege_mode_sel.rs b/esp32c3/src/sensitive/privilege_mode_sel.rs
index 206dd8e63c..cab317b372 100644
--- a/esp32c3/src/sensitive/privilege_mode_sel.rs
+++ b/esp32c3/src/sensitive/privilege_mode_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRIVILEGE_MODE_SEL")
-            .field(
-                "privilege_mode_sel",
-                &format_args!("{}", self.privilege_mode_sel().bit()),
-            )
+            .field("privilege_mode_sel", &self.privilege_mode_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRIVILEGE_MODE_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - privilege_mode_sel"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/privilege_mode_sel_lock.rs b/esp32c3/src/sensitive/privilege_mode_sel_lock.rs
index 76605b75bd..1a3c467387 100644
--- a/esp32c3/src/sensitive/privilege_mode_sel_lock.rs
+++ b/esp32c3/src/sensitive/privilege_mode_sel_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRIVILEGE_MODE_SEL_LOCK")
-            .field(
-                "privilege_mode_sel_lock",
-                &format_args!("{}", self.privilege_mode_sel_lock().bit()),
-            )
+            .field("privilege_mode_sel_lock", &self.privilege_mode_sel_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRIVILEGE_MODE_SEL_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - privilege_mode_sel_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/region_pms_constrain_0.rs b/esp32c3/src/sensitive/region_pms_constrain_0.rs
index b9e019810a..37abf3500c 100644
--- a/esp32c3/src/sensitive/region_pms_constrain_0.rs
+++ b/esp32c3/src/sensitive/region_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("REGION_PMS_CONSTRAIN_0")
             .field(
                 "region_pms_constrain_lock",
-                &format_args!("{}", self.region_pms_constrain_lock().bit()),
+                &self.region_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - region_pms_constrain_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/region_pms_constrain_1.rs b/esp32c3/src/sensitive/region_pms_constrain_1.rs
index 8cbe3a1aff..15f93ac31f 100644
--- a/esp32c3/src/sensitive/region_pms_constrain_1.rs
+++ b/esp32c3/src/sensitive/region_pms_constrain_1.rs
@@ -73,41 +73,35 @@ impl core::fmt::Debug for R {
         f.debug_struct("REGION_PMS_CONSTRAIN_1")
             .field(
                 "region_pms_constrain_world_0_area_0",
-                &format_args!("{}", self.region_pms_constrain_world_0_area_0().bits()),
+                &self.region_pms_constrain_world_0_area_0(),
             )
             .field(
                 "region_pms_constrain_world_0_area_1",
-                &format_args!("{}", self.region_pms_constrain_world_0_area_1().bits()),
+                &self.region_pms_constrain_world_0_area_1(),
             )
             .field(
                 "region_pms_constrain_world_0_area_2",
-                &format_args!("{}", self.region_pms_constrain_world_0_area_2().bits()),
+                &self.region_pms_constrain_world_0_area_2(),
             )
             .field(
                 "region_pms_constrain_world_0_area_3",
-                &format_args!("{}", self.region_pms_constrain_world_0_area_3().bits()),
+                &self.region_pms_constrain_world_0_area_3(),
             )
             .field(
                 "region_pms_constrain_world_0_area_4",
-                &format_args!("{}", self.region_pms_constrain_world_0_area_4().bits()),
+                &self.region_pms_constrain_world_0_area_4(),
             )
             .field(
                 "region_pms_constrain_world_0_area_5",
-                &format_args!("{}", self.region_pms_constrain_world_0_area_5().bits()),
+                &self.region_pms_constrain_world_0_area_5(),
             )
             .field(
                 "region_pms_constrain_world_0_area_6",
-                &format_args!("{}", self.region_pms_constrain_world_0_area_6().bits()),
+                &self.region_pms_constrain_world_0_area_6(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - region_pms_constrain_world_0_area_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/region_pms_constrain_10.rs b/esp32c3/src/sensitive/region_pms_constrain_10.rs
index c2d7e77f46..8b76a3fda6 100644
--- a/esp32c3/src/sensitive/region_pms_constrain_10.rs
+++ b/esp32c3/src/sensitive/region_pms_constrain_10.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("REGION_PMS_CONSTRAIN_10")
             .field(
                 "region_pms_constrain_addr_7",
-                &format_args!("{}", self.region_pms_constrain_addr_7().bits()),
+                &self.region_pms_constrain_addr_7(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_PMS_CONSTRAIN_10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - region_pms_constrain_addr_7"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/region_pms_constrain_2.rs b/esp32c3/src/sensitive/region_pms_constrain_2.rs
index da8e540e9a..0f2893dbc8 100644
--- a/esp32c3/src/sensitive/region_pms_constrain_2.rs
+++ b/esp32c3/src/sensitive/region_pms_constrain_2.rs
@@ -73,41 +73,35 @@ impl core::fmt::Debug for R {
         f.debug_struct("REGION_PMS_CONSTRAIN_2")
             .field(
                 "region_pms_constrain_world_1_area_0",
-                &format_args!("{}", self.region_pms_constrain_world_1_area_0().bits()),
+                &self.region_pms_constrain_world_1_area_0(),
             )
             .field(
                 "region_pms_constrain_world_1_area_1",
-                &format_args!("{}", self.region_pms_constrain_world_1_area_1().bits()),
+                &self.region_pms_constrain_world_1_area_1(),
             )
             .field(
                 "region_pms_constrain_world_1_area_2",
-                &format_args!("{}", self.region_pms_constrain_world_1_area_2().bits()),
+                &self.region_pms_constrain_world_1_area_2(),
             )
             .field(
                 "region_pms_constrain_world_1_area_3",
-                &format_args!("{}", self.region_pms_constrain_world_1_area_3().bits()),
+                &self.region_pms_constrain_world_1_area_3(),
             )
             .field(
                 "region_pms_constrain_world_1_area_4",
-                &format_args!("{}", self.region_pms_constrain_world_1_area_4().bits()),
+                &self.region_pms_constrain_world_1_area_4(),
             )
             .field(
                 "region_pms_constrain_world_1_area_5",
-                &format_args!("{}", self.region_pms_constrain_world_1_area_5().bits()),
+                &self.region_pms_constrain_world_1_area_5(),
             )
             .field(
                 "region_pms_constrain_world_1_area_6",
-                &format_args!("{}", self.region_pms_constrain_world_1_area_6().bits()),
+                &self.region_pms_constrain_world_1_area_6(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_PMS_CONSTRAIN_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - region_pms_constrain_world_1_area_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/region_pms_constrain_3.rs b/esp32c3/src/sensitive/region_pms_constrain_3.rs
index 63e876b6e7..229dd403be 100644
--- a/esp32c3/src/sensitive/region_pms_constrain_3.rs
+++ b/esp32c3/src/sensitive/region_pms_constrain_3.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("REGION_PMS_CONSTRAIN_3")
             .field(
                 "region_pms_constrain_addr_0",
-                &format_args!("{}", self.region_pms_constrain_addr_0().bits()),
+                &self.region_pms_constrain_addr_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_PMS_CONSTRAIN_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - region_pms_constrain_addr_0"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/region_pms_constrain_4.rs b/esp32c3/src/sensitive/region_pms_constrain_4.rs
index 2135154a88..2717940270 100644
--- a/esp32c3/src/sensitive/region_pms_constrain_4.rs
+++ b/esp32c3/src/sensitive/region_pms_constrain_4.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("REGION_PMS_CONSTRAIN_4")
             .field(
                 "region_pms_constrain_addr_1",
-                &format_args!("{}", self.region_pms_constrain_addr_1().bits()),
+                &self.region_pms_constrain_addr_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_PMS_CONSTRAIN_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - region_pms_constrain_addr_1"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/region_pms_constrain_5.rs b/esp32c3/src/sensitive/region_pms_constrain_5.rs
index 3d95fb5607..db1ed0ce0c 100644
--- a/esp32c3/src/sensitive/region_pms_constrain_5.rs
+++ b/esp32c3/src/sensitive/region_pms_constrain_5.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("REGION_PMS_CONSTRAIN_5")
             .field(
                 "region_pms_constrain_addr_2",
-                &format_args!("{}", self.region_pms_constrain_addr_2().bits()),
+                &self.region_pms_constrain_addr_2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_PMS_CONSTRAIN_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - region_pms_constrain_addr_2"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/region_pms_constrain_6.rs b/esp32c3/src/sensitive/region_pms_constrain_6.rs
index ae59f75e2e..b30c855638 100644
--- a/esp32c3/src/sensitive/region_pms_constrain_6.rs
+++ b/esp32c3/src/sensitive/region_pms_constrain_6.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("REGION_PMS_CONSTRAIN_6")
             .field(
                 "region_pms_constrain_addr_3",
-                &format_args!("{}", self.region_pms_constrain_addr_3().bits()),
+                &self.region_pms_constrain_addr_3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_PMS_CONSTRAIN_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - region_pms_constrain_addr_3"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/region_pms_constrain_7.rs b/esp32c3/src/sensitive/region_pms_constrain_7.rs
index bfe2f2c660..850413e4f2 100644
--- a/esp32c3/src/sensitive/region_pms_constrain_7.rs
+++ b/esp32c3/src/sensitive/region_pms_constrain_7.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("REGION_PMS_CONSTRAIN_7")
             .field(
                 "region_pms_constrain_addr_4",
-                &format_args!("{}", self.region_pms_constrain_addr_4().bits()),
+                &self.region_pms_constrain_addr_4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_PMS_CONSTRAIN_7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - region_pms_constrain_addr_4"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/region_pms_constrain_8.rs b/esp32c3/src/sensitive/region_pms_constrain_8.rs
index 4a6edcdddf..b597cefc07 100644
--- a/esp32c3/src/sensitive/region_pms_constrain_8.rs
+++ b/esp32c3/src/sensitive/region_pms_constrain_8.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("REGION_PMS_CONSTRAIN_8")
             .field(
                 "region_pms_constrain_addr_5",
-                &format_args!("{}", self.region_pms_constrain_addr_5().bits()),
+                &self.region_pms_constrain_addr_5(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_PMS_CONSTRAIN_8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - region_pms_constrain_addr_5"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/region_pms_constrain_9.rs b/esp32c3/src/sensitive/region_pms_constrain_9.rs
index cb0a777a7d..76f66cfbf4 100644
--- a/esp32c3/src/sensitive/region_pms_constrain_9.rs
+++ b/esp32c3/src/sensitive/region_pms_constrain_9.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("REGION_PMS_CONSTRAIN_9")
             .field(
                 "region_pms_constrain_addr_6",
-                &format_args!("{}", self.region_pms_constrain_addr_6().bits()),
+                &self.region_pms_constrain_addr_6(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_PMS_CONSTRAIN_9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - region_pms_constrain_addr_6"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/rom_table.rs b/esp32c3/src/sensitive/rom_table.rs
index f23a29115b..ba2465b2c7 100644
--- a/esp32c3/src/sensitive/rom_table.rs
+++ b/esp32c3/src/sensitive/rom_table.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_TABLE")
-            .field("rom_table", &format_args!("{}", self.rom_table().bits()))
+            .field("rom_table", &self.rom_table())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_TABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - rom_table"]
     #[inline(always)]
diff --git a/esp32c3/src/sensitive/rom_table_lock.rs b/esp32c3/src/sensitive/rom_table_lock.rs
index 0dfbf129db..557b56d971 100644
--- a/esp32c3/src/sensitive/rom_table_lock.rs
+++ b/esp32c3/src/sensitive/rom_table_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_TABLE_LOCK")
-            .field(
-                "rom_table_lock",
-                &format_args!("{}", self.rom_table_lock().bit()),
-            )
+            .field("rom_table_lock", &self.rom_table_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_TABLE_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - rom_table_lock"]
     #[inline(always)]
diff --git a/esp32c3/src/sha/busy.rs b/esp32c3/src/sha/busy.rs
index d586138364..ec4ecab687 100644
--- a/esp32c3/src/sha/busy.rs
+++ b/esp32c3/src/sha/busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUSY")
-            .field("state", &format_args!("{}", self.state().bit()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Busy register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUSY_SPEC;
 impl crate::RegisterSpec for BUSY_SPEC {
diff --git a/esp32c3/src/sha/date.rs b/esp32c3/src/sha/date.rs
index 0320a0619a..7d041db081 100644
--- a/esp32c3/src/sha/date.rs
+++ b/esp32c3/src/sha/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/sha/dma_block_num.rs b/esp32c3/src/sha/dma_block_num.rs
index 235679368f..be8854254d 100644
--- a/esp32c3/src/sha/dma_block_num.rs
+++ b/esp32c3/src/sha/dma_block_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_BLOCK_NUM")
-            .field(
-                "dma_block_num",
-                &format_args!("{}", self.dma_block_num().bits()),
-            )
+            .field("dma_block_num", &self.dma_block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Dma-sha block number."]
     #[inline(always)]
diff --git a/esp32c3/src/sha/h_mem.rs b/esp32c3/src/sha/h_mem.rs
index e0865c92c6..13a6f95266 100644
--- a/esp32c3/src/sha/h_mem.rs
+++ b/esp32c3/src/sha/h_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Sha H memory which contains intermediate hash or finial hash.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct H_MEM_SPEC;
diff --git a/esp32c3/src/sha/irq_ena.rs b/esp32c3/src/sha/irq_ena.rs
index 8d61ac4aae..725a0f2641 100644
--- a/esp32c3/src/sha/irq_ena.rs
+++ b/esp32c3/src/sha/irq_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IRQ_ENA")
-            .field(
-                "interrupt_ena",
-                &format_args!("{}", self.interrupt_ena().bit()),
-            )
+            .field("interrupt_ena", &self.interrupt_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IRQ_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable."]
     #[inline(always)]
diff --git a/esp32c3/src/sha/m_mem.rs b/esp32c3/src/sha/m_mem.rs
index ccac5e7d71..7418659e89 100644
--- a/esp32c3/src/sha/m_mem.rs
+++ b/esp32c3/src/sha/m_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Sha M memory which contains message.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct M_MEM_SPEC;
diff --git a/esp32c3/src/sha/mode.rs b/esp32c3/src/sha/mode.rs
index 2b849314d6..ab2c8b2b20 100644
--- a/esp32c3/src/sha/mode.rs
+++ b/esp32c3/src/sha/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/sha/t_length.rs b/esp32c3/src/sha/t_length.rs
index 523a021805..845f709a89 100644
--- a/esp32c3/src/sha/t_length.rs
+++ b/esp32c3/src/sha/t_length.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T_LENGTH")
-            .field("t_length", &format_args!("{}", self.t_length().bits()))
+            .field("t_length", &self.t_length())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T_LENGTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Sha t_length (used if and only if mode == SHA_512/t)."]
     #[inline(always)]
diff --git a/esp32c3/src/sha/t_string.rs b/esp32c3/src/sha/t_string.rs
index db1093db4b..c533a0e0d5 100644
--- a/esp32c3/src/sha/t_string.rs
+++ b/esp32c3/src/sha/t_string.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T_STRING")
-            .field("t_string", &format_args!("{}", self.t_string().bits()))
+            .field("t_string", &self.t_string())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T_STRING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Sha t_string (used if and only if mode == SHA_512/t)."]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/cache_fctrl.rs b/esp32c3/src/spi0/cache_fctrl.rs
index 72f388883f..bd069158f3 100644
--- a/esp32c3/src/spi0/cache_fctrl.rs
+++ b/esp32c3/src/spi0/cache_fctrl.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_FCTRL")
-            .field(
-                "cache_req_en",
-                &format_args!("{}", self.cache_req_en().bit()),
-            )
-            .field(
-                "cache_usr_addr_4byte",
-                &format_args!("{}", self.cache_usr_addr_4byte().bit()),
-            )
-            .field(
-                "cache_flash_usr_cmd",
-                &format_args!("{}", self.cache_flash_usr_cmd().bit()),
-            )
-            .field("fdin_dual", &format_args!("{}", self.fdin_dual().bit()))
-            .field("fdout_dual", &format_args!("{}", self.fdout_dual().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("fdin_quad", &format_args!("{}", self.fdin_quad().bit()))
-            .field("fdout_quad", &format_args!("{}", self.fdout_quad().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
+            .field("cache_req_en", &self.cache_req_en())
+            .field("cache_usr_addr_4byte", &self.cache_usr_addr_4byte())
+            .field("cache_flash_usr_cmd", &self.cache_flash_usr_cmd())
+            .field("fdin_dual", &self.fdin_dual())
+            .field("fdout_dual", &self.fdout_dual())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("fdin_quad", &self.fdin_quad())
+            .field("fdout_quad", &self.fdout_quad())
+            .field("faddr_quad", &self.faddr_quad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_FCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - For SPI0, Cache access enable, 1: enable, 0:disable."]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/clock.rs b/esp32c3/src/spi0/clock.rs
index 999d107e76..6f3d2a552b 100644
--- a/esp32c3/src/spi0/clock.rs
+++ b/esp32c3/src/spi0/clock.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/clock_gate.rs b/esp32c3/src/spi0/clock_gate.rs
index 9137df9c1e..82cb1e6398 100644
--- a/esp32c3/src/spi0/clock_gate.rs
+++ b/esp32c3/src/spi0/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/core_clk_sel.rs b/esp32c3/src/spi0/core_clk_sel.rs
index ba35380df7..6a5fdadee1 100644
--- a/esp32c3/src/spi0/core_clk_sel.rs
+++ b/esp32c3/src/spi0/core_clk_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_CLK_SEL")
-            .field(
-                "spi01_clk_sel",
-                &format_args!("{}", self.spi01_clk_sel().bits()),
-            )
+            .field("spi01_clk_sel", &self.spi01_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_CLK_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used."]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/ctrl.rs b/esp32c3/src/spi0/ctrl.rs
index becfdbb8ff..77825baba5 100644
--- a/esp32c3/src/spi0/ctrl.rs
+++ b/esp32c3/src/spi0/ctrl.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("fdummy_out", &format_args!("{}", self.fdummy_out().bit()))
-            .field("fcmd_dual", &format_args!("{}", self.fcmd_dual().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fastrd_mode", &format_args!("{}", self.fastrd_mode().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("wp", &format_args!("{}", self.wp().bit()))
-            .field("fread_dio", &format_args!("{}", self.fread_dio().bit()))
-            .field("fread_qio", &format_args!("{}", self.fread_qio().bit()))
+            .field("fdummy_out", &self.fdummy_out())
+            .field("fcmd_dual", &self.fcmd_dual())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fastrd_mode", &self.fastrd_mode())
+            .field("fread_dual", &self.fread_dual())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("fread_quad", &self.fread_quad())
+            .field("wp", &self.wp())
+            .field("fread_dio", &self.fread_dio())
+            .field("fread_qio", &self.fread_qio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - In the dummy phase the signal level of spi is output by the spi controller."]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/ctrl1.rs b/esp32c3/src/spi0/ctrl1.rs
index 47ee6011ea..a29f19c785 100644
--- a/esp32c3/src/spi0/ctrl1.rs
+++ b/esp32c3/src/spi0/ctrl1.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL1")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
+            .field("clk_mode", &self.clk_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/ctrl2.rs b/esp32c3/src/spi0/ctrl2.rs
index 36195ca9d1..6cd2906084 100644
--- a/esp32c3/src/spi0/ctrl2.rs
+++ b/esp32c3/src/spi0/ctrl2.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field(
-                "cs_setup_time",
-                &format_args!("{}", self.cs_setup_time().bits()),
-            )
-            .field(
-                "cs_hold_time",
-                &format_args!("{}", self.cs_hold_time().bits()),
-            )
-            .field(
-                "cs_hold_delay",
-                &format_args!("{}", self.cs_hold_delay().bits()),
-            )
+            .field("cs_setup_time", &self.cs_setup_time())
+            .field("cs_hold_time", &self.cs_hold_time())
+            .field("cs_hold_delay", &self.cs_hold_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit."]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/date.rs b/esp32c3/src/spi0/date.rs
index c6e517c05a..110ece079d 100644
--- a/esp32c3/src/spi0/date.rs
+++ b/esp32c3/src/spi0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/spi0/din_mode.rs b/esp32c3/src/spi0/din_mode.rs
index e5bbc59ca6..09c136f6a0 100644
--- a/esp32c3/src/spi0/din_mode.rs
+++ b/esp32c3/src/spi0/din_mode.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_MODE")
-            .field("din0_mode", &format_args!("{}", self.din0_mode().bits()))
-            .field("din1_mode", &format_args!("{}", self.din1_mode().bits()))
-            .field("din2_mode", &format_args!("{}", self.din2_mode().bits()))
-            .field("din3_mode", &format_args!("{}", self.din3_mode().bits()))
+            .field("din0_mode", &self.din0_mode())
+            .field("din1_mode", &self.din1_mode())
+            .field("din2_mode", &self.din2_mode())
+            .field("din3_mode", &self.din3_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/din_num.rs b/esp32c3/src/spi0/din_num.rs
index c57afc9413..80b92e8a49 100644
--- a/esp32c3/src/spi0/din_num.rs
+++ b/esp32c3/src/spi0/din_num.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_NUM")
-            .field("din0_num", &format_args!("{}", self.din0_num().bits()))
-            .field("din1_num", &format_args!("{}", self.din1_num().bits()))
-            .field("din2_num", &format_args!("{}", self.din2_num().bits()))
-            .field("din3_num", &format_args!("{}", self.din3_num().bits()))
+            .field("din0_num", &self.din0_num())
+            .field("din1_num", &self.din1_num())
+            .field("din2_num", &self.din2_num())
+            .field("din3_num", &self.din3_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/dout_mode.rs b/esp32c3/src/spi0/dout_mode.rs
index 2b03948597..5d4be8990e 100644
--- a/esp32c3/src/spi0/dout_mode.rs
+++ b/esp32c3/src/spi0/dout_mode.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOUT_MODE")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bit()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bit()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bit()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bit()))
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/fsm.rs b/esp32c3/src/spi0/fsm.rs
index 02d06cc456..95b6e02ace 100644
--- a/esp32c3/src/spi0/fsm.rs
+++ b/esp32c3/src/spi0/fsm.rs
@@ -31,21 +31,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM")
-            .field("cspi_st", &format_args!("{}", self.cspi_st().bits()))
-            .field("em_st", &format_args!("{}", self.em_st().bits()))
-            .field(
-                "cspi_lock_delay_time",
-                &format_args!("{}", self.cspi_lock_delay_time().bits()),
-            )
+            .field("cspi_st", &self.cspi_st())
+            .field("em_st", &self.em_st())
+            .field("cspi_lock_delay_time", &self.cspi_lock_delay_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 7:11 - The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1."]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/misc.rs b/esp32c3/src/spi0/misc.rs
index 426bcd686a..e1ec9d4aa9 100644
--- a/esp32c3/src/spi0/misc.rs
+++ b/esp32c3/src/spi0/misc.rs
@@ -62,36 +62,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("trans_end", &format_args!("{}", self.trans_end().bit()))
-            .field(
-                "trans_end_int_ena",
-                &format_args!("{}", self.trans_end_int_ena().bit()),
-            )
-            .field(
-                "cspi_st_trans_end",
-                &format_args!("{}", self.cspi_st_trans_end().bit()),
-            )
+            .field("trans_end", &self.trans_end())
+            .field("trans_end_int_ena", &self.trans_end_int_ena())
+            .field("cspi_st_trans_end", &self.cspi_st_trans_end())
             .field(
                 "cspi_st_trans_end_int_ena",
-                &format_args!("{}", self.cspi_st_trans_end_int_ena().bit()),
-            )
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
+                &self.cspi_st_trans_end_int_ena(),
             )
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - The bit is used to indicate the spi0_mst_st controlled transmitting is done."]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/rd_status.rs b/esp32c3/src/spi0/rd_status.rs
index f0916ef916..ce4af380ee 100644
--- a/esp32c3/src/spi0/rd_status.rs
+++ b/esp32c3/src/spi0/rd_status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_STATUS")
-            .field("wb_mode", &format_args!("{}", self.wb_mode().bits()))
+            .field("wb_mode", &self.wb_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:23 - Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit."]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/timing_cali.rs b/esp32c3/src/spi0/timing_cali.rs
index 081136706e..0335cd6bf5 100644
--- a/esp32c3/src/spi0/timing_cali.rs
+++ b/esp32c3/src/spi0/timing_cali.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMING_CALI")
-            .field(
-                "timing_clk_ena",
-                &format_args!("{}", self.timing_clk_ena().bit()),
-            )
-            .field("timing_cali", &format_args!("{}", self.timing_cali().bit()))
-            .field(
-                "extra_dummy_cyclelen",
-                &format_args!("{}", self.extra_dummy_cyclelen().bits()),
-            )
+            .field("timing_clk_ena", &self.timing_clk_ena())
+            .field("timing_cali", &self.timing_cali())
+            .field("extra_dummy_cyclelen", &self.extra_dummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable timing adjust clock for all reading operations."]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/user.rs b/esp32c3/src/spi0/user.rs
index 62c66529ef..3191631ea8 100644
--- a/esp32c3/src/spi0/user.rs
+++ b/esp32c3/src/spi0/user.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
-            .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
+            .field("cs_hold", &self.cs_hold())
+            .field("cs_setup", &self.cs_setup())
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_dummy", &self.usr_dummy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/user1.rs b/esp32c3/src/spi0/user1.rs
index 3384bb8a56..88b12b4269 100644
--- a/esp32c3/src/spi0/user1.rs
+++ b/esp32c3/src/spi0/user1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
     #[inline(always)]
diff --git a/esp32c3/src/spi0/user2.rs b/esp32c3/src/spi0/user2.rs
index 801f605c21..d0bf1413f5 100644
--- a/esp32c3/src/spi0/user2.rs
+++ b/esp32c3/src/spi0/user2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/addr.rs b/esp32c3/src/spi1/addr.rs
index 565e7916d4..cc9a0e1b42 100644
--- a/esp32c3/src/spi1/addr.rs
+++ b/esp32c3/src/spi1/addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR")
-            .field(
-                "usr_addr_value",
-                &format_args!("{}", self.usr_addr_value().bits()),
-            )
+            .field("usr_addr_value", &self.usr_addr_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/cache_fctrl.rs b/esp32c3/src/spi1/cache_fctrl.rs
index c8eafade55..3a22f1f847 100644
--- a/esp32c3/src/spi1/cache_fctrl.rs
+++ b/esp32c3/src/spi1/cache_fctrl.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_FCTRL")
-            .field(
-                "cache_usr_addr_4byte",
-                &format_args!("{}", self.cache_usr_addr_4byte().bit()),
-            )
-            .field("fdin_dual", &format_args!("{}", self.fdin_dual().bit()))
-            .field("fdout_dual", &format_args!("{}", self.fdout_dual().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("fdin_quad", &format_args!("{}", self.fdin_quad().bit()))
-            .field("fdout_quad", &format_args!("{}", self.fdout_quad().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
+            .field("cache_usr_addr_4byte", &self.cache_usr_addr_4byte())
+            .field("fdin_dual", &self.fdin_dual())
+            .field("fdout_dual", &self.fdout_dual())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("fdin_quad", &self.fdin_quad())
+            .field("fdout_quad", &self.fdout_quad())
+            .field("faddr_quad", &self.faddr_quad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_FCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/clock.rs b/esp32c3/src/spi1/clock.rs
index 250a0c660f..ec805aad92 100644
--- a/esp32c3/src/spi1/clock.rs
+++ b/esp32c3/src/spi1/clock.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/clock_gate.rs b/esp32c3/src/spi1/clock_gate.rs
index c60d396767..69477e9842 100644
--- a/esp32c3/src/spi1/clock_gate.rs
+++ b/esp32c3/src/spi1/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/cmd.rs b/esp32c3/src/spi1/cmd.rs
index 31cc3b2e6b..2283088975 100644
--- a/esp32c3/src/spi1/cmd.rs
+++ b/esp32c3/src/spi1/cmd.rs
@@ -157,35 +157,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field(
-                "spi1_mst_st",
-                &format_args!("{}", self.spi1_mst_st().bits()),
-            )
-            .field("mspi_st", &format_args!("{}", self.mspi_st().bits()))
-            .field("flash_pe", &format_args!("{}", self.flash_pe().bit()))
-            .field("usr", &format_args!("{}", self.usr().bit()))
-            .field("flash_hpm", &format_args!("{}", self.flash_hpm().bit()))
-            .field("flash_res", &format_args!("{}", self.flash_res().bit()))
-            .field("flash_dp", &format_args!("{}", self.flash_dp().bit()))
-            .field("flash_ce", &format_args!("{}", self.flash_ce().bit()))
-            .field("flash_be", &format_args!("{}", self.flash_be().bit()))
-            .field("flash_se", &format_args!("{}", self.flash_se().bit()))
-            .field("flash_pp", &format_args!("{}", self.flash_pp().bit()))
-            .field("flash_wrsr", &format_args!("{}", self.flash_wrsr().bit()))
-            .field("flash_rdsr", &format_args!("{}", self.flash_rdsr().bit()))
-            .field("flash_rdid", &format_args!("{}", self.flash_rdid().bit()))
-            .field("flash_wrdi", &format_args!("{}", self.flash_wrdi().bit()))
-            .field("flash_wren", &format_args!("{}", self.flash_wren().bit()))
-            .field("flash_read", &format_args!("{}", self.flash_read().bit()))
+            .field("spi1_mst_st", &self.spi1_mst_st())
+            .field("mspi_st", &self.mspi_st())
+            .field("flash_pe", &self.flash_pe())
+            .field("usr", &self.usr())
+            .field("flash_hpm", &self.flash_hpm())
+            .field("flash_res", &self.flash_res())
+            .field("flash_dp", &self.flash_dp())
+            .field("flash_ce", &self.flash_ce())
+            .field("flash_be", &self.flash_be())
+            .field("flash_se", &self.flash_se())
+            .field("flash_pp", &self.flash_pp())
+            .field("flash_wrsr", &self.flash_wrsr())
+            .field("flash_rdsr", &self.flash_rdsr())
+            .field("flash_rdid", &self.flash_rdid())
+            .field("flash_wrdi", &self.flash_wrdi())
+            .field("flash_wren", &self.flash_wren())
+            .field("flash_read", &self.flash_read())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/ctrl.rs b/esp32c3/src/spi1/ctrl.rs
index 8d0aef82cb..6462c91847 100644
--- a/esp32c3/src/spi1/ctrl.rs
+++ b/esp32c3/src/spi1/ctrl.rs
@@ -143,30 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("fdummy_out", &format_args!("{}", self.fdummy_out().bit()))
-            .field("fcmd_dual", &format_args!("{}", self.fcmd_dual().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcs_crc_en", &format_args!("{}", self.fcs_crc_en().bit()))
-            .field("tx_crc_en", &format_args!("{}", self.tx_crc_en().bit()))
-            .field("fastrd_mode", &format_args!("{}", self.fastrd_mode().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("resandres", &format_args!("{}", self.resandres().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("wp", &format_args!("{}", self.wp().bit()))
-            .field("wrsr_2b", &format_args!("{}", self.wrsr_2b().bit()))
-            .field("fread_dio", &format_args!("{}", self.fread_dio().bit()))
-            .field("fread_qio", &format_args!("{}", self.fread_qio().bit()))
+            .field("fdummy_out", &self.fdummy_out())
+            .field("fcmd_dual", &self.fcmd_dual())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcs_crc_en", &self.fcs_crc_en())
+            .field("tx_crc_en", &self.tx_crc_en())
+            .field("fastrd_mode", &self.fastrd_mode())
+            .field("fread_dual", &self.fread_dual())
+            .field("resandres", &self.resandres())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("fread_quad", &self.fread_quad())
+            .field("wp", &self.wp())
+            .field("wrsr_2b", &self.wrsr_2b())
+            .field("fread_dio", &self.fread_dio())
+            .field("fread_qio", &self.fread_qio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - In the dummy phase the signal level of spi is output by the spi controller."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/ctrl1.rs b/esp32c3/src/spi1/ctrl1.rs
index 72546d185b..bde8ad35ad 100644
--- a/esp32c3/src/spi1/ctrl1.rs
+++ b/esp32c3/src/spi1/ctrl1.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL1")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
-            .field(
-                "cs_hold_dly_res",
-                &format_args!("{}", self.cs_hold_dly_res().bits()),
-            )
+            .field("clk_mode", &self.clk_mode())
+            .field("cs_hold_dly_res", &self.cs_hold_dly_res())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/date.rs b/esp32c3/src/spi1/date.rs
index 60d273620b..86ef9aac67 100644
--- a/esp32c3/src/spi1/date.rs
+++ b/esp32c3/src/spi1/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/spi1/flash_sus_cmd.rs b/esp32c3/src/spi1/flash_sus_cmd.rs
index 7efa867925..8fd24bd900 100644
--- a/esp32c3/src/spi1/flash_sus_cmd.rs
+++ b/esp32c3/src/spi1/flash_sus_cmd.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_SUS_CMD")
-            .field(
-                "flash_per_command",
-                &format_args!("{}", self.flash_per_command().bits()),
-            )
-            .field(
-                "flash_pes_command",
-                &format_args!("{}", self.flash_pes_command().bits()),
-            )
-            .field(
-                "wait_pesr_command",
-                &format_args!("{}", self.wait_pesr_command().bits()),
-            )
+            .field("flash_per_command", &self.flash_per_command())
+            .field("flash_pes_command", &self.flash_pes_command())
+            .field("wait_pesr_command", &self.wait_pesr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_SUS_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Program/Erase resume command."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/flash_sus_ctrl.rs b/esp32c3/src/spi1/flash_sus_ctrl.rs
index fd999cd295..e794c1070e 100644
--- a/esp32c3/src/spi1/flash_sus_ctrl.rs
+++ b/esp32c3/src/spi1/flash_sus_ctrl.rs
@@ -107,41 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_SUS_CTRL")
-            .field("flash_per", &format_args!("{}", self.flash_per().bit()))
-            .field("flash_pes", &format_args!("{}", self.flash_pes().bit()))
-            .field(
-                "flash_per_wait_en",
-                &format_args!("{}", self.flash_per_wait_en().bit()),
-            )
-            .field(
-                "flash_pes_wait_en",
-                &format_args!("{}", self.flash_pes_wait_en().bit()),
-            )
-            .field("pes_per_en", &format_args!("{}", self.pes_per_en().bit()))
-            .field(
-                "flash_pes_en",
-                &format_args!("{}", self.flash_pes_en().bit()),
-            )
-            .field(
-                "pesr_end_msk",
-                &format_args!("{}", self.pesr_end_msk().bits()),
-            )
-            .field("rd_sus_2b", &format_args!("{}", self.rd_sus_2b().bit()))
-            .field("per_end_en", &format_args!("{}", self.per_end_en().bit()))
-            .field("pes_end_en", &format_args!("{}", self.pes_end_en().bit()))
-            .field(
-                "sus_timeout_cnt",
-                &format_args!("{}", self.sus_timeout_cnt().bits()),
-            )
+            .field("flash_per", &self.flash_per())
+            .field("flash_pes", &self.flash_pes())
+            .field("flash_per_wait_en", &self.flash_per_wait_en())
+            .field("flash_pes_wait_en", &self.flash_pes_wait_en())
+            .field("pes_per_en", &self.pes_per_en())
+            .field("flash_pes_en", &self.flash_pes_en())
+            .field("pesr_end_msk", &self.pesr_end_msk())
+            .field("rd_sus_2b", &self.rd_sus_2b())
+            .field("per_end_en", &self.per_end_en())
+            .field("pes_end_en", &self.pes_end_en())
+            .field("sus_timeout_cnt", &self.sus_timeout_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_SUS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/flash_waiti_ctrl.rs b/esp32c3/src/spi1/flash_waiti_ctrl.rs
index 5c6c3680ad..9e16f840ea 100644
--- a/esp32c3/src/spi1/flash_waiti_ctrl.rs
+++ b/esp32c3/src/spi1/flash_waiti_ctrl.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_WAITI_CTRL")
-            .field("waiti_dummy", &format_args!("{}", self.waiti_dummy().bit()))
-            .field("waiti_cmd", &format_args!("{}", self.waiti_cmd().bits()))
-            .field(
-                "waiti_dummy_cyclelen",
-                &format_args!("{}", self.waiti_dummy_cyclelen().bits()),
-            )
+            .field("waiti_dummy", &self.waiti_dummy())
+            .field("waiti_cmd", &self.waiti_cmd())
+            .field("waiti_dummy_cyclelen", &self.waiti_dummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_WAITI_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - The dummy phase enable when wait flash idle (RDSR)"]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/int_ena.rs b/esp32c3/src/spi1/int_ena.rs
index 8b12718a27..f9b805ea1e 100644
--- a/esp32c3/src/spi1/int_ena.rs
+++ b/esp32c3/src/spi1/int_ena.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("wpe_end", &self.wpe_end())
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for SPI_MEM_PER_END_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/int_raw.rs b/esp32c3/src/spi1/int_raw.rs
index 860d4111d2..0f6227ca48 100644
--- a/esp32c3/src/spi1/int_raw.rs
+++ b/esp32c3/src/spi1/int_raw.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("wpe_end", &self.wpe_end())
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/int_st.rs b/esp32c3/src/spi1/int_st.rs
index 66005e8452..32b1627a85 100644
--- a/esp32c3/src/spi1/int_st.rs
+++ b/esp32c3/src/spi1/int_st.rs
@@ -41,20 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("wpe_end", &self.wpe_end())
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c3/src/spi1/misc.rs b/esp32c3/src/spi1/misc.rs
index 980afa45ae..7c1f213c28 100644
--- a/esp32c3/src/spi1/misc.rs
+++ b/esp32c3/src/spi1/misc.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
-            .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/miso_dlen.rs b/esp32c3/src/spi1/miso_dlen.rs
index 737f493c8c..6813af19b3 100644
--- a/esp32c3/src/spi1/miso_dlen.rs
+++ b/esp32c3/src/spi1/miso_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISO_DLEN")
-            .field(
-                "usr_miso_dbitlen",
-                &format_args!("{}", self.usr_miso_dbitlen().bits()),
-            )
+            .field("usr_miso_dbitlen", &self.usr_miso_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISO_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The length in bits of read-data. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/mosi_dlen.rs b/esp32c3/src/spi1/mosi_dlen.rs
index b21b936f88..5cd5d155af 100644
--- a/esp32c3/src/spi1/mosi_dlen.rs
+++ b/esp32c3/src/spi1/mosi_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MOSI_DLEN")
-            .field(
-                "usr_mosi_dbitlen",
-                &format_args!("{}", self.usr_mosi_dbitlen().bits()),
-            )
+            .field("usr_mosi_dbitlen", &self.usr_mosi_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MOSI_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The length in bits of write-data. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/rd_status.rs b/esp32c3/src/spi1/rd_status.rs
index 6088e50d21..7368a19e92 100644
--- a/esp32c3/src/spi1/rd_status.rs
+++ b/esp32c3/src/spi1/rd_status.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_STATUS")
-            .field("status", &format_args!("{}", self.status().bits()))
-            .field("wb_mode", &format_args!("{}", self.wb_mode().bits()))
+            .field("status", &self.status())
+            .field("wb_mode", &self.wb_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/sus_status.rs b/esp32c3/src/spi1/sus_status.rs
index 07934fd36c..ad6e934807 100644
--- a/esp32c3/src/spi1/sus_status.rs
+++ b/esp32c3/src/spi1/sus_status.rs
@@ -80,44 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SUS_STATUS")
-            .field("flash_sus", &format_args!("{}", self.flash_sus().bit()))
-            .field(
-                "wait_pesr_cmd_2b",
-                &format_args!("{}", self.wait_pesr_cmd_2b().bit()),
-            )
-            .field(
-                "flash_hpm_dly_128",
-                &format_args!("{}", self.flash_hpm_dly_128().bit()),
-            )
-            .field(
-                "flash_res_dly_128",
-                &format_args!("{}", self.flash_res_dly_128().bit()),
-            )
-            .field(
-                "flash_dp_dly_128",
-                &format_args!("{}", self.flash_dp_dly_128().bit()),
-            )
-            .field(
-                "flash_per_dly_128",
-                &format_args!("{}", self.flash_per_dly_128().bit()),
-            )
-            .field(
-                "flash_pes_dly_128",
-                &format_args!("{}", self.flash_pes_dly_128().bit()),
-            )
-            .field(
-                "spi0_lock_en",
-                &format_args!("{}", self.spi0_lock_en().bit()),
-            )
+            .field("flash_sus", &self.flash_sus())
+            .field("wait_pesr_cmd_2b", &self.wait_pesr_cmd_2b())
+            .field("flash_hpm_dly_128", &self.flash_hpm_dly_128())
+            .field("flash_res_dly_128", &self.flash_res_dly_128())
+            .field("flash_dp_dly_128", &self.flash_dp_dly_128())
+            .field("flash_per_dly_128", &self.flash_per_dly_128())
+            .field("flash_pes_dly_128", &self.flash_pes_dly_128())
+            .field("spi0_lock_en", &self.spi0_lock_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SUS_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The status of flash suspend, only used in SPI1."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/timing_cali.rs b/esp32c3/src/spi1/timing_cali.rs
index 507064ae31..c6a30a5847 100644
--- a/esp32c3/src/spi1/timing_cali.rs
+++ b/esp32c3/src/spi1/timing_cali.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMING_CALI")
-            .field("timing_cali", &format_args!("{}", self.timing_cali().bit()))
-            .field(
-                "extra_dummy_cyclelen",
-                &format_args!("{}", self.extra_dummy_cyclelen().bits()),
-            )
+            .field("timing_cali", &self.timing_cali())
+            .field("extra_dummy_cyclelen", &self.extra_dummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/tx_crc.rs b/esp32c3/src/spi1/tx_crc.rs
index 9faa1c440d..253fff1be1 100644
--- a/esp32c3/src/spi1/tx_crc.rs
+++ b/esp32c3/src/spi1/tx_crc.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 TX CRC data register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TX_CRC_SPEC;
 impl crate::RegisterSpec for TX_CRC_SPEC {
diff --git a/esp32c3/src/spi1/user.rs b/esp32c3/src/spi1/user.rs
index 66260b25e0..c53de90555 100644
--- a/esp32c3/src/spi1/user.rs
+++ b/esp32c3/src/spi1/user.rs
@@ -125,37 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
-            .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
-            .field("fwrite_dio", &format_args!("{}", self.fwrite_dio().bit()))
-            .field("fwrite_qio", &format_args!("{}", self.fwrite_qio().bit()))
-            .field(
-                "usr_miso_highpart",
-                &format_args!("{}", self.usr_miso_highpart().bit()),
-            )
-            .field(
-                "usr_mosi_highpart",
-                &format_args!("{}", self.usr_mosi_highpart().bit()),
-            )
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
-            .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
-            .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
-            .field("usr_command", &format_args!("{}", self.usr_command().bit()))
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("fwrite_dual", &self.fwrite_dual())
+            .field("fwrite_quad", &self.fwrite_quad())
+            .field("fwrite_dio", &self.fwrite_dio())
+            .field("fwrite_qio", &self.fwrite_qio())
+            .field("usr_miso_highpart", &self.usr_miso_highpart())
+            .field("usr_mosi_highpart", &self.usr_mosi_highpart())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_mosi", &self.usr_mosi())
+            .field("usr_miso", &self.usr_miso())
+            .field("usr_dummy", &self.usr_dummy())
+            .field("usr_addr", &self.usr_addr())
+            .field("usr_command", &self.usr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/user1.rs b/esp32c3/src/spi1/user1.rs
index 4b36bbf30d..8f28ca2ba4 100644
--- a/esp32c3/src/spi1/user1.rs
+++ b/esp32c3/src/spi1/user1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/user2.rs b/esp32c3/src/spi1/user2.rs
index 382c76224c..4bd67c802f 100644
--- a/esp32c3/src/spi1/user2.rs
+++ b/esp32c3/src/spi1/user2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command."]
     #[inline(always)]
diff --git a/esp32c3/src/spi1/w.rs b/esp32c3/src/spi1/w.rs
index 319a8e0611..43137019f7 100644
--- a/esp32c3/src/spi1/w.rs
+++ b/esp32c3/src/spi1/w.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("W")
-            .field("buf", &format_args!("{}", self.buf().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<W_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("W").field("buf", &self.buf()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/spi2/addr.rs b/esp32c3/src/spi2/addr.rs
index 0429f136d3..a43f100c19 100644
--- a/esp32c3/src/spi2/addr.rs
+++ b/esp32c3/src/spi2/addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR")
-            .field(
-                "usr_addr_value",
-                &format_args!("{}", self.usr_addr_value().bits()),
-            )
+            .field("usr_addr_value", &self.usr_addr_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Address to slave. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/clk_gate.rs b/esp32c3/src/spi2/clk_gate.rs
index c690702c68..c633026011 100644
--- a/esp32c3/src/spi2/clk_gate.rs
+++ b/esp32c3/src/spi2/clk_gate.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "mst_clk_active",
-                &format_args!("{}", self.mst_clk_active().bit()),
-            )
-            .field("mst_clk_sel", &format_args!("{}", self.mst_clk_sel().bit()))
+            .field("clk_en", &self.clk_en())
+            .field("mst_clk_active", &self.mst_clk_active())
+            .field("mst_clk_sel", &self.mst_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable clk gate"]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/clock.rs b/esp32c3/src/spi2/clock.rs
index a980aa1ac0..336dc15885 100644
--- a/esp32c3/src/spi2/clock.rs
+++ b/esp32c3/src/spi2/clock.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field("clkdiv_pre", &format_args!("{}", self.clkdiv_pre().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clkdiv_pre", &self.clkdiv_pre())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/cmd.rs b/esp32c3/src/spi2/cmd.rs
index d9c54a966c..8d8333ec63 100644
--- a/esp32c3/src/spi2/cmd.rs
+++ b/esp32c3/src/spi2/cmd.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field(
-                "conf_bitlen",
-                &format_args!("{}", self.conf_bitlen().bits()),
-            )
-            .field("update", &format_args!("{}", self.update().bit()))
-            .field("usr", &format_args!("{}", self.usr().bit()))
+            .field("conf_bitlen", &self.conf_bitlen())
+            .field("update", &self.update())
+            .field("usr", &self.usr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - Define the APB cycles of SPI_CONF state. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/ctrl.rs b/esp32c3/src/spi2/ctrl.rs
index ea9763bfcf..59ff28e7b2 100644
--- a/esp32c3/src/spi2/ctrl.rs
+++ b/esp32c3/src/spi2/ctrl.rs
@@ -125,34 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("dummy_out", &format_args!("{}", self.dummy_out().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
-            .field("fcmd_dual", &format_args!("{}", self.fcmd_dual().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("hold_pol", &format_args!("{}", self.hold_pol().bit()))
-            .field("wp_pol", &format_args!("{}", self.wp_pol().bit()))
-            .field(
-                "rd_bit_order",
-                &format_args!("{}", self.rd_bit_order().bit()),
-            )
-            .field(
-                "wr_bit_order",
-                &format_args!("{}", self.wr_bit_order().bit()),
-            )
+            .field("dummy_out", &self.dummy_out())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("faddr_quad", &self.faddr_quad())
+            .field("fcmd_dual", &self.fcmd_dual())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fread_dual", &self.fread_dual())
+            .field("fread_quad", &self.fread_quad())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("hold_pol", &self.hold_pol())
+            .field("wp_pol", &self.wp_pol())
+            .field("rd_bit_order", &self.rd_bit_order())
+            .field("wr_bit_order", &self.wr_bit_order())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/date.rs b/esp32c3/src/spi2/date.rs
index 77ad202862..f2217bbf99 100644
--- a/esp32c3/src/spi2/date.rs
+++ b/esp32c3/src/spi2/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/spi2/din_mode.rs b/esp32c3/src/spi2/din_mode.rs
index 02ecb02d51..1f85bb8c0b 100644
--- a/esp32c3/src/spi2/din_mode.rs
+++ b/esp32c3/src/spi2/din_mode.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_MODE")
-            .field("din0_mode", &format_args!("{}", self.din0_mode().bits()))
-            .field("din1_mode", &format_args!("{}", self.din1_mode().bits()))
-            .field("din2_mode", &format_args!("{}", self.din2_mode().bits()))
-            .field("din3_mode", &format_args!("{}", self.din3_mode().bits()))
-            .field(
-                "timing_hclk_active",
-                &format_args!("{}", self.timing_hclk_active().bit()),
-            )
+            .field("din0_mode", &self.din0_mode())
+            .field("din1_mode", &self.din1_mode())
+            .field("din2_mode", &self.din2_mode())
+            .field("din3_mode", &self.din3_mode())
+            .field("timing_hclk_active", &self.timing_hclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/din_num.rs b/esp32c3/src/spi2/din_num.rs
index 102655776e..3fd2574245 100644
--- a/esp32c3/src/spi2/din_num.rs
+++ b/esp32c3/src/spi2/din_num.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_NUM")
-            .field("din0_num", &format_args!("{}", self.din0_num().bits()))
-            .field("din1_num", &format_args!("{}", self.din1_num().bits()))
-            .field("din2_num", &format_args!("{}", self.din2_num().bits()))
-            .field("din3_num", &format_args!("{}", self.din3_num().bits()))
+            .field("din0_num", &self.din0_num())
+            .field("din1_num", &self.din1_num())
+            .field("din2_num", &self.din2_num())
+            .field("din3_num", &self.din3_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/dma_conf.rs b/esp32c3/src/spi2/dma_conf.rs
index e941ae8d5d..71f75b201c 100644
--- a/esp32c3/src/spi2/dma_conf.rs
+++ b/esp32c3/src/spi2/dma_conf.rs
@@ -68,30 +68,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field(
-                "dma_slv_seg_trans_en",
-                &format_args!("{}", self.dma_slv_seg_trans_en().bit()),
-            )
-            .field(
-                "slv_rx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_rx_seg_trans_clr_en().bit()),
-            )
-            .field(
-                "slv_tx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_tx_seg_trans_clr_en().bit()),
-            )
-            .field("rx_eof_en", &format_args!("{}", self.rx_eof_en().bit()))
-            .field("dma_rx_ena", &format_args!("{}", self.dma_rx_ena().bit()))
-            .field("dma_tx_ena", &format_args!("{}", self.dma_tx_ena().bit()))
+            .field("dma_slv_seg_trans_en", &self.dma_slv_seg_trans_en())
+            .field("slv_rx_seg_trans_clr_en", &self.slv_rx_seg_trans_clr_en())
+            .field("slv_tx_seg_trans_clr_en", &self.slv_tx_seg_trans_clr_en())
+            .field("rx_eof_en", &self.rx_eof_en())
+            .field("dma_rx_ena", &self.dma_rx_ena())
+            .field("dma_tx_ena", &self.dma_tx_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/dma_int_ena.rs b/esp32c3/src/spi2/dma_int_ena.rs
index b5ba071e6e..c08afd623b 100644
--- a/esp32c3/src/spi2/dma_int_ena.rs
+++ b/esp32c3/src/spi2/dma_int_ena.rs
@@ -197,69 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ENA")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/dma_int_raw.rs b/esp32c3/src/spi2/dma_int_raw.rs
index afc56997a6..068e28dece 100644
--- a/esp32c3/src/spi2/dma_int_raw.rs
+++ b/esp32c3/src/spi2/dma_int_raw.rs
@@ -197,69 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_RAW")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/dma_int_st.rs b/esp32c3/src/spi2/dma_int_st.rs
index 41c6ecf268..2b527df75d 100644
--- a/esp32c3/src/spi2/dma_int_st.rs
+++ b/esp32c3/src/spi2/dma_int_st.rs
@@ -153,69 +153,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ST")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI DMA interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_INT_ST_SPEC;
 impl crate::RegisterSpec for DMA_INT_ST_SPEC {
diff --git a/esp32c3/src/spi2/dout_mode.rs b/esp32c3/src/spi2/dout_mode.rs
index 7acc1b2deb..8a10dbd9fd 100644
--- a/esp32c3/src/spi2/dout_mode.rs
+++ b/esp32c3/src/spi2/dout_mode.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOUT_MODE")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bit()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bit()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bit()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bit()))
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/misc.rs b/esp32c3/src/spi2/misc.rs
index 697b803b7e..c30641ad04 100644
--- a/esp32c3/src/spi2/misc.rs
+++ b/esp32c3/src/spi2/misc.rs
@@ -116,42 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
-            .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
-            .field("cs2_dis", &format_args!("{}", self.cs2_dis().bit()))
-            .field("cs3_dis", &format_args!("{}", self.cs3_dis().bit()))
-            .field("cs4_dis", &format_args!("{}", self.cs4_dis().bit()))
-            .field("cs5_dis", &format_args!("{}", self.cs5_dis().bit()))
-            .field("ck_dis", &format_args!("{}", self.ck_dis().bit()))
-            .field(
-                "master_cs_pol",
-                &format_args!("{}", self.master_cs_pol().bits()),
-            )
-            .field(
-                "slave_cs_pol",
-                &format_args!("{}", self.slave_cs_pol().bit()),
-            )
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
-            .field(
-                "quad_din_pin_swap",
-                &format_args!("{}", self.quad_din_pin_swap().bit()),
-            )
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("cs2_dis", &self.cs2_dis())
+            .field("cs3_dis", &self.cs3_dis())
+            .field("cs4_dis", &self.cs4_dis())
+            .field("cs5_dis", &self.cs5_dis())
+            .field("ck_dis", &self.ck_dis())
+            .field("master_cs_pol", &self.master_cs_pol())
+            .field("slave_cs_pol", &self.slave_cs_pol())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
+            .field("quad_din_pin_swap", &self.quad_din_pin_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/ms_dlen.rs b/esp32c3/src/spi2/ms_dlen.rs
index 116939582c..94a2915785 100644
--- a/esp32c3/src/spi2/ms_dlen.rs
+++ b/esp32c3/src/spi2/ms_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MS_DLEN")
-            .field(
-                "ms_data_bitlen",
-                &format_args!("{}", self.ms_data_bitlen().bits()),
-            )
+            .field("ms_data_bitlen", &self.ms_data_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MS_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/slave.rs b/esp32c3/src/spi2/slave.rs
index 2deadc74df..91a5b8108d 100644
--- a/esp32c3/src/spi2/slave.rs
+++ b/esp32c3/src/spi2/slave.rs
@@ -100,43 +100,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
-            .field("clk_mode_13", &format_args!("{}", self.clk_mode_13().bit()))
-            .field(
-                "rsck_data_out",
-                &format_args!("{}", self.rsck_data_out().bit()),
-            )
-            .field(
-                "slv_rddma_bitlen_en",
-                &format_args!("{}", self.slv_rddma_bitlen_en().bit()),
-            )
-            .field(
-                "slv_wrdma_bitlen_en",
-                &format_args!("{}", self.slv_wrdma_bitlen_en().bit()),
-            )
-            .field(
-                "slv_rdbuf_bitlen_en",
-                &format_args!("{}", self.slv_rdbuf_bitlen_en().bit()),
-            )
-            .field(
-                "slv_wrbuf_bitlen_en",
-                &format_args!("{}", self.slv_wrbuf_bitlen_en().bit()),
-            )
-            .field(
-                "dma_seg_magic_value",
-                &format_args!("{}", self.dma_seg_magic_value().bits()),
-            )
-            .field("mode", &format_args!("{}", self.mode().bit()))
-            .field("usr_conf", &format_args!("{}", self.usr_conf().bit()))
+            .field("clk_mode", &self.clk_mode())
+            .field("clk_mode_13", &self.clk_mode_13())
+            .field("rsck_data_out", &self.rsck_data_out())
+            .field("slv_rddma_bitlen_en", &self.slv_rddma_bitlen_en())
+            .field("slv_wrdma_bitlen_en", &self.slv_wrdma_bitlen_en())
+            .field("slv_rdbuf_bitlen_en", &self.slv_rdbuf_bitlen_en())
+            .field("slv_wrbuf_bitlen_en", &self.slv_wrbuf_bitlen_en())
+            .field("dma_seg_magic_value", &self.dma_seg_magic_value())
+            .field("mode", &self.mode())
+            .field("usr_conf", &self.usr_conf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/slave1.rs b/esp32c3/src/spi2/slave1.rs
index 7e216d9f86..98ad1b4b32 100644
--- a/esp32c3/src/spi2/slave1.rs
+++ b/esp32c3/src/spi2/slave1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE1")
-            .field(
-                "slv_data_bitlen",
-                &format_args!("{}", self.slv_data_bitlen().bits()),
-            )
-            .field(
-                "slv_last_command",
-                &format_args!("{}", self.slv_last_command().bits()),
-            )
-            .field(
-                "slv_last_addr",
-                &format_args!("{}", self.slv_last_addr().bits()),
-            )
+            .field("slv_data_bitlen", &self.slv_data_bitlen())
+            .field("slv_last_command", &self.slv_last_command())
+            .field("slv_last_addr", &self.slv_last_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - The transferred data bit length in SPI slave FD and HD mode."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/user.rs b/esp32c3/src/spi2/user.rs
index 6607c18e53..0257770f92 100644
--- a/esp32c3/src/spi2/user.rs
+++ b/esp32c3/src/spi2/user.rs
@@ -179,46 +179,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("doutdin", &format_args!("{}", self.doutdin().bit()))
-            .field("qpi_mode", &format_args!("{}", self.qpi_mode().bit()))
-            .field("tsck_i_edge", &format_args!("{}", self.tsck_i_edge().bit()))
-            .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
-            .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
-            .field("rsck_i_edge", &format_args!("{}", self.rsck_i_edge().bit()))
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
-            .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
-            .field(
-                "usr_conf_nxt",
-                &format_args!("{}", self.usr_conf_nxt().bit()),
-            )
-            .field("sio", &format_args!("{}", self.sio().bit()))
-            .field(
-                "usr_miso_highpart",
-                &format_args!("{}", self.usr_miso_highpart().bit()),
-            )
-            .field(
-                "usr_mosi_highpart",
-                &format_args!("{}", self.usr_mosi_highpart().bit()),
-            )
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
-            .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
-            .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
-            .field("usr_command", &format_args!("{}", self.usr_command().bit()))
+            .field("doutdin", &self.doutdin())
+            .field("qpi_mode", &self.qpi_mode())
+            .field("tsck_i_edge", &self.tsck_i_edge())
+            .field("cs_hold", &self.cs_hold())
+            .field("cs_setup", &self.cs_setup())
+            .field("rsck_i_edge", &self.rsck_i_edge())
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("fwrite_dual", &self.fwrite_dual())
+            .field("fwrite_quad", &self.fwrite_quad())
+            .field("usr_conf_nxt", &self.usr_conf_nxt())
+            .field("sio", &self.sio())
+            .field("usr_miso_highpart", &self.usr_miso_highpart())
+            .field("usr_mosi_highpart", &self.usr_mosi_highpart())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_mosi", &self.usr_mosi())
+            .field("usr_miso", &self.usr_miso())
+            .field("usr_dummy", &self.usr_dummy())
+            .field("usr_addr", &self.usr_addr())
+            .field("usr_command", &self.usr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/user1.rs b/esp32c3/src/spi2/user1.rs
index acb564ca07..1dd612d409 100644
--- a/esp32c3/src/spi2/user1.rs
+++ b/esp32c3/src/spi2/user1.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "mst_wfull_err_end_en",
-                &format_args!("{}", self.mst_wfull_err_end_en().bit()),
-            )
-            .field(
-                "cs_setup_time",
-                &format_args!("{}", self.cs_setup_time().bits()),
-            )
-            .field(
-                "cs_hold_time",
-                &format_args!("{}", self.cs_hold_time().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("mst_wfull_err_end_en", &self.mst_wfull_err_end_en())
+            .field("cs_setup_time", &self.cs_setup_time())
+            .field("cs_hold_time", &self.cs_hold_time())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/user2.rs b/esp32c3/src/spi2/user2.rs
index 065c536363..c2d5092cd2 100644
--- a/esp32c3/src/spi2/user2.rs
+++ b/esp32c3/src/spi2/user2.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "mst_rempty_err_end_en",
-                &format_args!("{}", self.mst_rempty_err_end_en().bit()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("mst_rempty_err_end_en", &self.mst_rempty_err_end_en())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c3/src/spi2/w.rs b/esp32c3/src/spi2/w.rs
index bd1588a6f2..016fb59d7c 100644
--- a/esp32c3/src/spi2/w.rs
+++ b/esp32c3/src/spi2/w.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("W")
-            .field("buf", &format_args!("{}", self.buf().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<W_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("W").field("buf", &self.buf()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/system/bt_lpck_div_frac.rs b/esp32c3/src/system/bt_lpck_div_frac.rs
index 8ab89160c9..6a05ce2836 100644
--- a/esp32c3/src/system/bt_lpck_div_frac.rs
+++ b/esp32c3/src/system/bt_lpck_div_frac.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_LPCK_DIV_FRAC")
-            .field(
-                "bt_lpck_div_b",
-                &format_args!("{}", self.bt_lpck_div_b().bits()),
-            )
-            .field(
-                "bt_lpck_div_a",
-                &format_args!("{}", self.bt_lpck_div_a().bits()),
-            )
-            .field(
-                "lpclk_sel_rtc_slow",
-                &format_args!("{}", self.lpclk_sel_rtc_slow().bit()),
-            )
-            .field(
-                "lpclk_sel_8m",
-                &format_args!("{}", self.lpclk_sel_8m().bit()),
-            )
-            .field(
-                "lpclk_sel_xtal",
-                &format_args!("{}", self.lpclk_sel_xtal().bit()),
-            )
-            .field(
-                "lpclk_sel_xtal32k",
-                &format_args!("{}", self.lpclk_sel_xtal32k().bit()),
-            )
-            .field(
-                "lpclk_rtc_en",
-                &format_args!("{}", self.lpclk_rtc_en().bit()),
-            )
+            .field("bt_lpck_div_b", &self.bt_lpck_div_b())
+            .field("bt_lpck_div_a", &self.bt_lpck_div_a())
+            .field("lpclk_sel_rtc_slow", &self.lpclk_sel_rtc_slow())
+            .field("lpclk_sel_8m", &self.lpclk_sel_8m())
+            .field("lpclk_sel_xtal", &self.lpclk_sel_xtal())
+            .field("lpclk_sel_xtal32k", &self.lpclk_sel_xtal32k())
+            .field("lpclk_rtc_en", &self.lpclk_rtc_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_LPCK_DIV_FRAC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - reg_bt_lpck_div_b"]
     #[inline(always)]
diff --git a/esp32c3/src/system/bt_lpck_div_int.rs b/esp32c3/src/system/bt_lpck_div_int.rs
index 316217a2e5..d5c1adc9ca 100644
--- a/esp32c3/src/system/bt_lpck_div_int.rs
+++ b/esp32c3/src/system/bt_lpck_div_int.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_LPCK_DIV_INT")
-            .field(
-                "bt_lpck_div_num",
-                &format_args!("{}", self.bt_lpck_div_num().bits()),
-            )
+            .field("bt_lpck_div_num", &self.bt_lpck_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_LPCK_DIV_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - reg_bt_lpck_div_num"]
     #[inline(always)]
diff --git a/esp32c3/src/system/cache_control.rs b/esp32c3/src/system/cache_control.rs
index 260eca85e1..a25eb0269e 100644
--- a/esp32c3/src/system/cache_control.rs
+++ b/esp32c3/src/system/cache_control.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_CONTROL")
-            .field(
-                "icache_clk_on",
-                &format_args!("{}", self.icache_clk_on().bit()),
-            )
-            .field(
-                "icache_reset",
-                &format_args!("{}", self.icache_reset().bit()),
-            )
-            .field(
-                "dcache_clk_on",
-                &format_args!("{}", self.dcache_clk_on().bit()),
-            )
-            .field(
-                "dcache_reset",
-                &format_args!("{}", self.dcache_reset().bit()),
-            )
+            .field("icache_clk_on", &self.icache_clk_on())
+            .field("icache_reset", &self.icache_reset())
+            .field("dcache_clk_on", &self.dcache_clk_on())
+            .field("dcache_reset", &self.dcache_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_icache_clk_on"]
     #[inline(always)]
diff --git a/esp32c3/src/system/clock_gate.rs b/esp32c3/src/system/clock_gate.rs
index 0ea9f4e7a3..0260550609 100644
--- a/esp32c3/src/system/clock_gate.rs
+++ b/esp32c3/src/system/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_clk_en"]
     #[inline(always)]
diff --git a/esp32c3/src/system/comb_pvt_err_hvt_site0.rs b/esp32c3/src/system/comb_pvt_err_hvt_site0.rs
index 3b0b5228b1..2e5426ed5e 100644
--- a/esp32c3/src/system/comb_pvt_err_hvt_site0.rs
+++ b/esp32c3/src/system/comb_pvt_err_hvt_site0.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_HVT_SITE0")
             .field(
                 "comb_timing_err_cnt_hvt_site0",
-                &format_args!("{}", self.comb_timing_err_cnt_hvt_site0().bits()),
+                &self.comb_timing_err_cnt_hvt_site0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_HVT_SITE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_hvt_site0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_HVT_SITE0_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE0_SPEC {
diff --git a/esp32c3/src/system/comb_pvt_err_hvt_site1.rs b/esp32c3/src/system/comb_pvt_err_hvt_site1.rs
index 283388ac5e..c21f017ecd 100644
--- a/esp32c3/src/system/comb_pvt_err_hvt_site1.rs
+++ b/esp32c3/src/system/comb_pvt_err_hvt_site1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_HVT_SITE1")
             .field(
                 "comb_timing_err_cnt_hvt_site1",
-                &format_args!("{}", self.comb_timing_err_cnt_hvt_site1().bits()),
+                &self.comb_timing_err_cnt_hvt_site1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_HVT_SITE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_hvt_site1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_HVT_SITE1_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE1_SPEC {
diff --git a/esp32c3/src/system/comb_pvt_err_hvt_site2.rs b/esp32c3/src/system/comb_pvt_err_hvt_site2.rs
index 390dd0be24..0f154a986d 100644
--- a/esp32c3/src/system/comb_pvt_err_hvt_site2.rs
+++ b/esp32c3/src/system/comb_pvt_err_hvt_site2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_HVT_SITE2")
             .field(
                 "comb_timing_err_cnt_hvt_site2",
-                &format_args!("{}", self.comb_timing_err_cnt_hvt_site2().bits()),
+                &self.comb_timing_err_cnt_hvt_site2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_HVT_SITE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_hvt_site2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_HVT_SITE2_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE2_SPEC {
diff --git a/esp32c3/src/system/comb_pvt_err_hvt_site3.rs b/esp32c3/src/system/comb_pvt_err_hvt_site3.rs
index 55535ac027..d9700c5a61 100644
--- a/esp32c3/src/system/comb_pvt_err_hvt_site3.rs
+++ b/esp32c3/src/system/comb_pvt_err_hvt_site3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_HVT_SITE3")
             .field(
                 "comb_timing_err_cnt_hvt_site3",
-                &format_args!("{}", self.comb_timing_err_cnt_hvt_site3().bits()),
+                &self.comb_timing_err_cnt_hvt_site3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_HVT_SITE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_hvt_site3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_HVT_SITE3_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE3_SPEC {
diff --git a/esp32c3/src/system/comb_pvt_err_lvt_site0.rs b/esp32c3/src/system/comb_pvt_err_lvt_site0.rs
index 30714d37de..2889b2742b 100644
--- a/esp32c3/src/system/comb_pvt_err_lvt_site0.rs
+++ b/esp32c3/src/system/comb_pvt_err_lvt_site0.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_LVT_SITE0")
             .field(
                 "comb_timing_err_cnt_lvt_site0",
-                &format_args!("{}", self.comb_timing_err_cnt_lvt_site0().bits()),
+                &self.comb_timing_err_cnt_lvt_site0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_LVT_SITE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_lvt_site0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_LVT_SITE0_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE0_SPEC {
diff --git a/esp32c3/src/system/comb_pvt_err_lvt_site1.rs b/esp32c3/src/system/comb_pvt_err_lvt_site1.rs
index fbf134e4fb..1410f1e2e7 100644
--- a/esp32c3/src/system/comb_pvt_err_lvt_site1.rs
+++ b/esp32c3/src/system/comb_pvt_err_lvt_site1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_LVT_SITE1")
             .field(
                 "comb_timing_err_cnt_lvt_site1",
-                &format_args!("{}", self.comb_timing_err_cnt_lvt_site1().bits()),
+                &self.comb_timing_err_cnt_lvt_site1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_LVT_SITE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_lvt_site1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_LVT_SITE1_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE1_SPEC {
diff --git a/esp32c3/src/system/comb_pvt_err_lvt_site2.rs b/esp32c3/src/system/comb_pvt_err_lvt_site2.rs
index 2372dc60c5..b9ed5bc385 100644
--- a/esp32c3/src/system/comb_pvt_err_lvt_site2.rs
+++ b/esp32c3/src/system/comb_pvt_err_lvt_site2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_LVT_SITE2")
             .field(
                 "comb_timing_err_cnt_lvt_site2",
-                &format_args!("{}", self.comb_timing_err_cnt_lvt_site2().bits()),
+                &self.comb_timing_err_cnt_lvt_site2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_LVT_SITE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_lvt_site2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_LVT_SITE2_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE2_SPEC {
diff --git a/esp32c3/src/system/comb_pvt_err_lvt_site3.rs b/esp32c3/src/system/comb_pvt_err_lvt_site3.rs
index 407766ecb2..c9f922eec2 100644
--- a/esp32c3/src/system/comb_pvt_err_lvt_site3.rs
+++ b/esp32c3/src/system/comb_pvt_err_lvt_site3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_LVT_SITE3")
             .field(
                 "comb_timing_err_cnt_lvt_site3",
-                &format_args!("{}", self.comb_timing_err_cnt_lvt_site3().bits()),
+                &self.comb_timing_err_cnt_lvt_site3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_LVT_SITE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_lvt_site3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_LVT_SITE3_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE3_SPEC {
diff --git a/esp32c3/src/system/comb_pvt_err_nvt_site0.rs b/esp32c3/src/system/comb_pvt_err_nvt_site0.rs
index 150832d2ef..b3895071a9 100644
--- a/esp32c3/src/system/comb_pvt_err_nvt_site0.rs
+++ b/esp32c3/src/system/comb_pvt_err_nvt_site0.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_NVT_SITE0")
             .field(
                 "comb_timing_err_cnt_nvt_site0",
-                &format_args!("{}", self.comb_timing_err_cnt_nvt_site0().bits()),
+                &self.comb_timing_err_cnt_nvt_site0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_NVT_SITE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_nvt_site0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_NVT_SITE0_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE0_SPEC {
diff --git a/esp32c3/src/system/comb_pvt_err_nvt_site1.rs b/esp32c3/src/system/comb_pvt_err_nvt_site1.rs
index 1485f3c151..25e3c41cec 100644
--- a/esp32c3/src/system/comb_pvt_err_nvt_site1.rs
+++ b/esp32c3/src/system/comb_pvt_err_nvt_site1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_NVT_SITE1")
             .field(
                 "comb_timing_err_cnt_nvt_site1",
-                &format_args!("{}", self.comb_timing_err_cnt_nvt_site1().bits()),
+                &self.comb_timing_err_cnt_nvt_site1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_NVT_SITE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_nvt_site1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_NVT_SITE1_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE1_SPEC {
diff --git a/esp32c3/src/system/comb_pvt_err_nvt_site2.rs b/esp32c3/src/system/comb_pvt_err_nvt_site2.rs
index 829924c30b..e741e1d1fb 100644
--- a/esp32c3/src/system/comb_pvt_err_nvt_site2.rs
+++ b/esp32c3/src/system/comb_pvt_err_nvt_site2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_NVT_SITE2")
             .field(
                 "comb_timing_err_cnt_nvt_site2",
-                &format_args!("{}", self.comb_timing_err_cnt_nvt_site2().bits()),
+                &self.comb_timing_err_cnt_nvt_site2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_NVT_SITE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_nvt_site2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_NVT_SITE2_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE2_SPEC {
diff --git a/esp32c3/src/system/comb_pvt_err_nvt_site3.rs b/esp32c3/src/system/comb_pvt_err_nvt_site3.rs
index 0a168d741b..2ee4f7571f 100644
--- a/esp32c3/src/system/comb_pvt_err_nvt_site3.rs
+++ b/esp32c3/src/system/comb_pvt_err_nvt_site3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_NVT_SITE3")
             .field(
                 "comb_timing_err_cnt_nvt_site3",
-                &format_args!("{}", self.comb_timing_err_cnt_nvt_site3().bits()),
+                &self.comb_timing_err_cnt_nvt_site3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_NVT_SITE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem pvt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_nvt_site3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_NVT_SITE3_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE3_SPEC {
diff --git a/esp32c3/src/system/comb_pvt_hvt_conf.rs b/esp32c3/src/system/comb_pvt_hvt_conf.rs
index 53d561831d..62bf54eeff 100644
--- a/esp32c3/src/system/comb_pvt_hvt_conf.rs
+++ b/esp32c3/src/system/comb_pvt_hvt_conf.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMB_PVT_HVT_CONF")
-            .field(
-                "comb_path_len_hvt",
-                &format_args!("{}", self.comb_path_len_hvt().bits()),
-            )
-            .field(
-                "comb_pvt_monitor_en_hvt",
-                &format_args!("{}", self.comb_pvt_monitor_en_hvt().bit()),
-            )
+            .field("comb_path_len_hvt", &self.comb_path_len_hvt())
+            .field("comb_pvt_monitor_en_hvt", &self.comb_pvt_monitor_en_hvt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_HVT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_comb_path_len_hvt"]
     #[inline(always)]
diff --git a/esp32c3/src/system/comb_pvt_lvt_conf.rs b/esp32c3/src/system/comb_pvt_lvt_conf.rs
index 21f5168ec8..7d9fe0b92e 100644
--- a/esp32c3/src/system/comb_pvt_lvt_conf.rs
+++ b/esp32c3/src/system/comb_pvt_lvt_conf.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMB_PVT_LVT_CONF")
-            .field(
-                "comb_path_len_lvt",
-                &format_args!("{}", self.comb_path_len_lvt().bits()),
-            )
-            .field(
-                "comb_pvt_monitor_en_lvt",
-                &format_args!("{}", self.comb_pvt_monitor_en_lvt().bit()),
-            )
+            .field("comb_path_len_lvt", &self.comb_path_len_lvt())
+            .field("comb_pvt_monitor_en_lvt", &self.comb_pvt_monitor_en_lvt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_LVT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_comb_path_len_lvt"]
     #[inline(always)]
diff --git a/esp32c3/src/system/comb_pvt_nvt_conf.rs b/esp32c3/src/system/comb_pvt_nvt_conf.rs
index 2e41eab88e..4483220920 100644
--- a/esp32c3/src/system/comb_pvt_nvt_conf.rs
+++ b/esp32c3/src/system/comb_pvt_nvt_conf.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMB_PVT_NVT_CONF")
-            .field(
-                "comb_path_len_nvt",
-                &format_args!("{}", self.comb_path_len_nvt().bits()),
-            )
-            .field(
-                "comb_pvt_monitor_en_nvt",
-                &format_args!("{}", self.comb_pvt_monitor_en_nvt().bit()),
-            )
+            .field("comb_path_len_nvt", &self.comb_path_len_nvt())
+            .field("comb_pvt_monitor_en_nvt", &self.comb_pvt_monitor_en_nvt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_NVT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - reg_comb_path_len_nvt"]
     #[inline(always)]
diff --git a/esp32c3/src/system/cpu_intr_from_cpu_0.rs b/esp32c3/src/system/cpu_intr_from_cpu_0.rs
index ae23a4c934..114fe192e0 100644
--- a/esp32c3/src/system/cpu_intr_from_cpu_0.rs
+++ b/esp32c3/src/system/cpu_intr_from_cpu_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_0")
-            .field(
-                "cpu_intr_from_cpu_0",
-                &format_args!("{}", self.cpu_intr_from_cpu_0().bit()),
-            )
+            .field("cpu_intr_from_cpu_0", &self.cpu_intr_from_cpu_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_cpu_intr_from_cpu_0"]
     #[inline(always)]
diff --git a/esp32c3/src/system/cpu_intr_from_cpu_1.rs b/esp32c3/src/system/cpu_intr_from_cpu_1.rs
index 96492a9fee..49803f3483 100644
--- a/esp32c3/src/system/cpu_intr_from_cpu_1.rs
+++ b/esp32c3/src/system/cpu_intr_from_cpu_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_1")
-            .field(
-                "cpu_intr_from_cpu_1",
-                &format_args!("{}", self.cpu_intr_from_cpu_1().bit()),
-            )
+            .field("cpu_intr_from_cpu_1", &self.cpu_intr_from_cpu_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_cpu_intr_from_cpu_1"]
     #[inline(always)]
diff --git a/esp32c3/src/system/cpu_intr_from_cpu_2.rs b/esp32c3/src/system/cpu_intr_from_cpu_2.rs
index a106046dca..86462d740b 100644
--- a/esp32c3/src/system/cpu_intr_from_cpu_2.rs
+++ b/esp32c3/src/system/cpu_intr_from_cpu_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_2")
-            .field(
-                "cpu_intr_from_cpu_2",
-                &format_args!("{}", self.cpu_intr_from_cpu_2().bit()),
-            )
+            .field("cpu_intr_from_cpu_2", &self.cpu_intr_from_cpu_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_cpu_intr_from_cpu_2"]
     #[inline(always)]
diff --git a/esp32c3/src/system/cpu_intr_from_cpu_3.rs b/esp32c3/src/system/cpu_intr_from_cpu_3.rs
index 5d098d8e1a..d91f61b664 100644
--- a/esp32c3/src/system/cpu_intr_from_cpu_3.rs
+++ b/esp32c3/src/system/cpu_intr_from_cpu_3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_3")
-            .field(
-                "cpu_intr_from_cpu_3",
-                &format_args!("{}", self.cpu_intr_from_cpu_3().bit()),
-            )
+            .field("cpu_intr_from_cpu_3", &self.cpu_intr_from_cpu_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_cpu_intr_from_cpu_3"]
     #[inline(always)]
diff --git a/esp32c3/src/system/cpu_per_conf.rs b/esp32c3/src/system/cpu_per_conf.rs
index ca13998ed8..ac99ddb520 100644
--- a/esp32c3/src/system/cpu_per_conf.rs
+++ b/esp32c3/src/system/cpu_per_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PER_CONF")
-            .field(
-                "cpuperiod_sel",
-                &format_args!("{}", self.cpuperiod_sel().bits()),
-            )
-            .field(
-                "pll_freq_sel",
-                &format_args!("{}", self.pll_freq_sel().bit()),
-            )
-            .field(
-                "cpu_wait_mode_force_on",
-                &format_args!("{}", self.cpu_wait_mode_force_on().bit()),
-            )
-            .field(
-                "cpu_waiti_delay_num",
-                &format_args!("{}", self.cpu_waiti_delay_num().bits()),
-            )
+            .field("cpuperiod_sel", &self.cpuperiod_sel())
+            .field("pll_freq_sel", &self.pll_freq_sel())
+            .field("cpu_wait_mode_force_on", &self.cpu_wait_mode_force_on())
+            .field("cpu_waiti_delay_num", &self.cpu_waiti_delay_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PER_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reg_cpuperiod_sel"]
     #[inline(always)]
diff --git a/esp32c3/src/system/cpu_peri_clk_en.rs b/esp32c3/src/system/cpu_peri_clk_en.rs
index fe1f806b15..77b12230b1 100644
--- a/esp32c3/src/system/cpu_peri_clk_en.rs
+++ b/esp32c3/src/system/cpu_peri_clk_en.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERI_CLK_EN")
-            .field(
-                "clk_en_assist_debug",
-                &format_args!("{}", self.clk_en_assist_debug().bit()),
-            )
-            .field(
-                "clk_en_dedicated_gpio",
-                &format_args!("{}", self.clk_en_dedicated_gpio().bit()),
-            )
+            .field("clk_en_assist_debug", &self.clk_en_assist_debug())
+            .field("clk_en_dedicated_gpio", &self.clk_en_dedicated_gpio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - reg_clk_en_assist_debug"]
     #[inline(always)]
diff --git a/esp32c3/src/system/cpu_peri_rst_en.rs b/esp32c3/src/system/cpu_peri_rst_en.rs
index e4e59c37b7..7d05e8cc9a 100644
--- a/esp32c3/src/system/cpu_peri_rst_en.rs
+++ b/esp32c3/src/system/cpu_peri_rst_en.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERI_RST_EN")
-            .field(
-                "rst_en_assist_debug",
-                &format_args!("{}", self.rst_en_assist_debug().bit()),
-            )
-            .field(
-                "rst_en_dedicated_gpio",
-                &format_args!("{}", self.rst_en_dedicated_gpio().bit()),
-            )
+            .field("rst_en_assist_debug", &self.rst_en_assist_debug())
+            .field("rst_en_dedicated_gpio", &self.rst_en_dedicated_gpio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_RST_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - reg_rst_en_assist_debug"]
     #[inline(always)]
diff --git a/esp32c3/src/system/edma_ctrl.rs b/esp32c3/src/system/edma_ctrl.rs
index 5886389453..af16767cf9 100644
--- a/esp32c3/src/system/edma_ctrl.rs
+++ b/esp32c3/src/system/edma_ctrl.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_CTRL")
-            .field("edma_clk_on", &format_args!("{}", self.edma_clk_on().bit()))
-            .field("edma_reset", &format_args!("{}", self.edma_reset().bit()))
+            .field("edma_clk_on", &self.edma_clk_on())
+            .field("edma_reset", &self.edma_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_edma_clk_on"]
     #[inline(always)]
diff --git a/esp32c3/src/system/external_device_encrypt_decrypt_control.rs b/esp32c3/src/system/external_device_encrypt_decrypt_control.rs
index 0df1cbb68b..6c38cef2f8 100644
--- a/esp32c3/src/system/external_device_encrypt_decrypt_control.rs
+++ b/esp32c3/src/system/external_device_encrypt_decrypt_control.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL")
             .field(
                 "enable_spi_manual_encrypt",
-                &format_args!("{}", self.enable_spi_manual_encrypt().bit()),
+                &self.enable_spi_manual_encrypt(),
             )
             .field(
                 "enable_download_db_encrypt",
-                &format_args!("{}", self.enable_download_db_encrypt().bit()),
+                &self.enable_download_db_encrypt(),
             )
             .field(
                 "enable_download_g0cb_decrypt",
-                &format_args!("{}", self.enable_download_g0cb_decrypt().bit()),
+                &self.enable_download_g0cb_decrypt(),
             )
             .field(
                 "enable_download_manual_encrypt",
-                &format_args!("{}", self.enable_download_manual_encrypt().bit()),
+                &self.enable_download_manual_encrypt(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_enable_spi_manual_encrypt"]
     #[inline(always)]
diff --git a/esp32c3/src/system/mem_pd_mask.rs b/esp32c3/src/system/mem_pd_mask.rs
index c4f5aacafb..c9dca7536e 100644
--- a/esp32c3/src/system/mem_pd_mask.rs
+++ b/esp32c3/src/system/mem_pd_mask.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_PD_MASK")
-            .field(
-                "lslp_mem_pd_mask",
-                &format_args!("{}", self.lslp_mem_pd_mask().bit()),
-            )
+            .field("lslp_mem_pd_mask", &self.lslp_mem_pd_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_PD_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_lslp_mem_pd_mask"]
     #[inline(always)]
diff --git a/esp32c3/src/system/mem_pvt.rs b/esp32c3/src/system/mem_pvt.rs
index 8055e22279..fc047f3021 100644
--- a/esp32c3/src/system/mem_pvt.rs
+++ b/esp32c3/src/system/mem_pvt.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_PVT")
-            .field(
-                "mem_path_len",
-                &format_args!("{}", self.mem_path_len().bits()),
-            )
-            .field("monitor_en", &format_args!("{}", self.monitor_en().bit()))
-            .field(
-                "mem_timing_err_cnt",
-                &format_args!("{}", self.mem_timing_err_cnt().bits()),
-            )
-            .field("mem_vt_sel", &format_args!("{}", self.mem_vt_sel().bits()))
+            .field("mem_path_len", &self.mem_path_len())
+            .field("monitor_en", &self.monitor_en())
+            .field("mem_timing_err_cnt", &self.mem_timing_err_cnt())
+            .field("mem_vt_sel", &self.mem_vt_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_PVT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - reg_mem_path_len"]
     #[inline(always)]
diff --git a/esp32c3/src/system/perip_clk_en0.rs b/esp32c3/src/system/perip_clk_en0.rs
index a443195917..1d00417c5d 100644
--- a/esp32c3/src/system/perip_clk_en0.rs
+++ b/esp32c3/src/system/perip_clk_en0.rs
@@ -296,95 +296,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_CLK_EN0")
-            .field(
-                "timers_clk_en",
-                &format_args!("{}", self.timers_clk_en().bit()),
-            )
-            .field(
-                "spi01_clk_en",
-                &format_args!("{}", self.spi01_clk_en().bit()),
-            )
-            .field("uart_clk_en", &format_args!("{}", self.uart_clk_en().bit()))
-            .field("wdg_clk_en", &format_args!("{}", self.wdg_clk_en().bit()))
-            .field("i2s0_clk_en", &format_args!("{}", self.i2s0_clk_en().bit()))
-            .field(
-                "uart1_clk_en",
-                &format_args!("{}", self.uart1_clk_en().bit()),
-            )
-            .field("spi2_clk_en", &format_args!("{}", self.spi2_clk_en().bit()))
-            .field(
-                "i2c_ext0_clk_en",
-                &format_args!("{}", self.i2c_ext0_clk_en().bit()),
-            )
-            .field(
-                "uhci0_clk_en",
-                &format_args!("{}", self.uhci0_clk_en().bit()),
-            )
-            .field("rmt_clk_en", &format_args!("{}", self.rmt_clk_en().bit()))
-            .field("pcnt_clk_en", &format_args!("{}", self.pcnt_clk_en().bit()))
-            .field("ledc_clk_en", &format_args!("{}", self.ledc_clk_en().bit()))
-            .field(
-                "uhci1_clk_en",
-                &format_args!("{}", self.uhci1_clk_en().bit()),
-            )
-            .field(
-                "timergroup_clk_en",
-                &format_args!("{}", self.timergroup_clk_en().bit()),
-            )
-            .field(
-                "efuse_clk_en",
-                &format_args!("{}", self.efuse_clk_en().bit()),
-            )
-            .field(
-                "timergroup1_clk_en",
-                &format_args!("{}", self.timergroup1_clk_en().bit()),
-            )
-            .field("spi3_clk_en", &format_args!("{}", self.spi3_clk_en().bit()))
-            .field("pwm0_clk_en", &format_args!("{}", self.pwm0_clk_en().bit()))
-            .field("ext1_clk_en", &format_args!("{}", self.ext1_clk_en().bit()))
-            .field("twai_clk_en", &format_args!("{}", self.twai_clk_en().bit()))
-            .field("pwm1_clk_en", &format_args!("{}", self.pwm1_clk_en().bit()))
-            .field("i2s1_clk_en", &format_args!("{}", self.i2s1_clk_en().bit()))
-            .field(
-                "spi2_dma_clk_en",
-                &format_args!("{}", self.spi2_dma_clk_en().bit()),
-            )
-            .field(
-                "usb_device_clk_en",
-                &format_args!("{}", self.usb_device_clk_en().bit()),
-            )
-            .field(
-                "uart_mem_clk_en",
-                &format_args!("{}", self.uart_mem_clk_en().bit()),
-            )
-            .field("pwm2_clk_en", &format_args!("{}", self.pwm2_clk_en().bit()))
-            .field("pwm3_clk_en", &format_args!("{}", self.pwm3_clk_en().bit()))
-            .field(
-                "spi3_dma_clk_en",
-                &format_args!("{}", self.spi3_dma_clk_en().bit()),
-            )
-            .field(
-                "apb_saradc_clk_en",
-                &format_args!("{}", self.apb_saradc_clk_en().bit()),
-            )
-            .field(
-                "systimer_clk_en",
-                &format_args!("{}", self.systimer_clk_en().bit()),
-            )
-            .field(
-                "adc2_arb_clk_en",
-                &format_args!("{}", self.adc2_arb_clk_en().bit()),
-            )
-            .field("spi4_clk_en", &format_args!("{}", self.spi4_clk_en().bit()))
+            .field("timers_clk_en", &self.timers_clk_en())
+            .field("spi01_clk_en", &self.spi01_clk_en())
+            .field("uart_clk_en", &self.uart_clk_en())
+            .field("wdg_clk_en", &self.wdg_clk_en())
+            .field("i2s0_clk_en", &self.i2s0_clk_en())
+            .field("uart1_clk_en", &self.uart1_clk_en())
+            .field("spi2_clk_en", &self.spi2_clk_en())
+            .field("i2c_ext0_clk_en", &self.i2c_ext0_clk_en())
+            .field("uhci0_clk_en", &self.uhci0_clk_en())
+            .field("rmt_clk_en", &self.rmt_clk_en())
+            .field("pcnt_clk_en", &self.pcnt_clk_en())
+            .field("ledc_clk_en", &self.ledc_clk_en())
+            .field("uhci1_clk_en", &self.uhci1_clk_en())
+            .field("timergroup_clk_en", &self.timergroup_clk_en())
+            .field("efuse_clk_en", &self.efuse_clk_en())
+            .field("timergroup1_clk_en", &self.timergroup1_clk_en())
+            .field("spi3_clk_en", &self.spi3_clk_en())
+            .field("pwm0_clk_en", &self.pwm0_clk_en())
+            .field("ext1_clk_en", &self.ext1_clk_en())
+            .field("twai_clk_en", &self.twai_clk_en())
+            .field("pwm1_clk_en", &self.pwm1_clk_en())
+            .field("i2s1_clk_en", &self.i2s1_clk_en())
+            .field("spi2_dma_clk_en", &self.spi2_dma_clk_en())
+            .field("usb_device_clk_en", &self.usb_device_clk_en())
+            .field("uart_mem_clk_en", &self.uart_mem_clk_en())
+            .field("pwm2_clk_en", &self.pwm2_clk_en())
+            .field("pwm3_clk_en", &self.pwm3_clk_en())
+            .field("spi3_dma_clk_en", &self.spi3_dma_clk_en())
+            .field("apb_saradc_clk_en", &self.apb_saradc_clk_en())
+            .field("systimer_clk_en", &self.systimer_clk_en())
+            .field("adc2_arb_clk_en", &self.adc2_arb_clk_en())
+            .field("spi4_clk_en", &self.spi4_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_CLK_EN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_timers_clk_en"]
     #[inline(always)]
diff --git a/esp32c3/src/system/perip_clk_en1.rs b/esp32c3/src/system/perip_clk_en1.rs
index b007a006b3..97205a9e09 100644
--- a/esp32c3/src/system/perip_clk_en1.rs
+++ b/esp32c3/src/system/perip_clk_en1.rs
@@ -98,52 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_CLK_EN1")
-            .field(
-                "crypto_aes_clk_en",
-                &format_args!("{}", self.crypto_aes_clk_en().bit()),
-            )
-            .field(
-                "crypto_sha_clk_en",
-                &format_args!("{}", self.crypto_sha_clk_en().bit()),
-            )
-            .field(
-                "crypto_rsa_clk_en",
-                &format_args!("{}", self.crypto_rsa_clk_en().bit()),
-            )
-            .field(
-                "crypto_ds_clk_en",
-                &format_args!("{}", self.crypto_ds_clk_en().bit()),
-            )
-            .field(
-                "crypto_hmac_clk_en",
-                &format_args!("{}", self.crypto_hmac_clk_en().bit()),
-            )
-            .field("dma_clk_en", &format_args!("{}", self.dma_clk_en().bit()))
-            .field(
-                "sdio_host_clk_en",
-                &format_args!("{}", self.sdio_host_clk_en().bit()),
-            )
-            .field(
-                "lcd_cam_clk_en",
-                &format_args!("{}", self.lcd_cam_clk_en().bit()),
-            )
-            .field(
-                "uart2_clk_en",
-                &format_args!("{}", self.uart2_clk_en().bit()),
-            )
-            .field(
-                "tsens_clk_en",
-                &format_args!("{}", self.tsens_clk_en().bit()),
-            )
+            .field("crypto_aes_clk_en", &self.crypto_aes_clk_en())
+            .field("crypto_sha_clk_en", &self.crypto_sha_clk_en())
+            .field("crypto_rsa_clk_en", &self.crypto_rsa_clk_en())
+            .field("crypto_ds_clk_en", &self.crypto_ds_clk_en())
+            .field("crypto_hmac_clk_en", &self.crypto_hmac_clk_en())
+            .field("dma_clk_en", &self.dma_clk_en())
+            .field("sdio_host_clk_en", &self.sdio_host_clk_en())
+            .field("lcd_cam_clk_en", &self.lcd_cam_clk_en())
+            .field("uart2_clk_en", &self.uart2_clk_en())
+            .field("tsens_clk_en", &self.tsens_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_CLK_EN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - reg_crypto_aes_clk_en"]
     #[inline(always)]
diff --git a/esp32c3/src/system/perip_rst_en0.rs b/esp32c3/src/system/perip_rst_en0.rs
index bc55dfe174..acac55e243 100644
--- a/esp32c3/src/system/perip_rst_en0.rs
+++ b/esp32c3/src/system/perip_rst_en0.rs
@@ -296,77 +296,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_RST_EN0")
-            .field("timers_rst", &format_args!("{}", self.timers_rst().bit()))
-            .field("spi01_rst", &format_args!("{}", self.spi01_rst().bit()))
-            .field("uart_rst", &format_args!("{}", self.uart_rst().bit()))
-            .field("wdg_rst", &format_args!("{}", self.wdg_rst().bit()))
-            .field("i2s0_rst", &format_args!("{}", self.i2s0_rst().bit()))
-            .field("uart1_rst", &format_args!("{}", self.uart1_rst().bit()))
-            .field("spi2_rst", &format_args!("{}", self.spi2_rst().bit()))
-            .field(
-                "i2c_ext0_rst",
-                &format_args!("{}", self.i2c_ext0_rst().bit()),
-            )
-            .field("uhci0_rst", &format_args!("{}", self.uhci0_rst().bit()))
-            .field("rmt_rst", &format_args!("{}", self.rmt_rst().bit()))
-            .field("pcnt_rst", &format_args!("{}", self.pcnt_rst().bit()))
-            .field("ledc_rst", &format_args!("{}", self.ledc_rst().bit()))
-            .field("uhci1_rst", &format_args!("{}", self.uhci1_rst().bit()))
-            .field(
-                "timergroup_rst",
-                &format_args!("{}", self.timergroup_rst().bit()),
-            )
-            .field("efuse_rst", &format_args!("{}", self.efuse_rst().bit()))
-            .field(
-                "timergroup1_rst",
-                &format_args!("{}", self.timergroup1_rst().bit()),
-            )
-            .field("spi3_rst", &format_args!("{}", self.spi3_rst().bit()))
-            .field("pwm0_rst", &format_args!("{}", self.pwm0_rst().bit()))
-            .field("ext1_rst", &format_args!("{}", self.ext1_rst().bit()))
-            .field("twai_rst", &format_args!("{}", self.twai_rst().bit()))
-            .field("pwm1_rst", &format_args!("{}", self.pwm1_rst().bit()))
-            .field("i2s1_rst", &format_args!("{}", self.i2s1_rst().bit()))
-            .field(
-                "spi2_dma_rst",
-                &format_args!("{}", self.spi2_dma_rst().bit()),
-            )
-            .field(
-                "usb_device_rst",
-                &format_args!("{}", self.usb_device_rst().bit()),
-            )
-            .field(
-                "uart_mem_rst",
-                &format_args!("{}", self.uart_mem_rst().bit()),
-            )
-            .field("pwm2_rst", &format_args!("{}", self.pwm2_rst().bit()))
-            .field("pwm3_rst", &format_args!("{}", self.pwm3_rst().bit()))
-            .field(
-                "spi3_dma_rst",
-                &format_args!("{}", self.spi3_dma_rst().bit()),
-            )
-            .field(
-                "apb_saradc_rst",
-                &format_args!("{}", self.apb_saradc_rst().bit()),
-            )
-            .field(
-                "systimer_rst",
-                &format_args!("{}", self.systimer_rst().bit()),
-            )
-            .field(
-                "adc2_arb_rst",
-                &format_args!("{}", self.adc2_arb_rst().bit()),
-            )
-            .field("spi4_rst", &format_args!("{}", self.spi4_rst().bit()))
+            .field("timers_rst", &self.timers_rst())
+            .field("spi01_rst", &self.spi01_rst())
+            .field("uart_rst", &self.uart_rst())
+            .field("wdg_rst", &self.wdg_rst())
+            .field("i2s0_rst", &self.i2s0_rst())
+            .field("uart1_rst", &self.uart1_rst())
+            .field("spi2_rst", &self.spi2_rst())
+            .field("i2c_ext0_rst", &self.i2c_ext0_rst())
+            .field("uhci0_rst", &self.uhci0_rst())
+            .field("rmt_rst", &self.rmt_rst())
+            .field("pcnt_rst", &self.pcnt_rst())
+            .field("ledc_rst", &self.ledc_rst())
+            .field("uhci1_rst", &self.uhci1_rst())
+            .field("timergroup_rst", &self.timergroup_rst())
+            .field("efuse_rst", &self.efuse_rst())
+            .field("timergroup1_rst", &self.timergroup1_rst())
+            .field("spi3_rst", &self.spi3_rst())
+            .field("pwm0_rst", &self.pwm0_rst())
+            .field("ext1_rst", &self.ext1_rst())
+            .field("twai_rst", &self.twai_rst())
+            .field("pwm1_rst", &self.pwm1_rst())
+            .field("i2s1_rst", &self.i2s1_rst())
+            .field("spi2_dma_rst", &self.spi2_dma_rst())
+            .field("usb_device_rst", &self.usb_device_rst())
+            .field("uart_mem_rst", &self.uart_mem_rst())
+            .field("pwm2_rst", &self.pwm2_rst())
+            .field("pwm3_rst", &self.pwm3_rst())
+            .field("spi3_dma_rst", &self.spi3_dma_rst())
+            .field("apb_saradc_rst", &self.apb_saradc_rst())
+            .field("systimer_rst", &self.systimer_rst())
+            .field("adc2_arb_rst", &self.adc2_arb_rst())
+            .field("spi4_rst", &self.spi4_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_RST_EN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_timers_rst"]
     #[inline(always)]
diff --git a/esp32c3/src/system/perip_rst_en1.rs b/esp32c3/src/system/perip_rst_en1.rs
index cd2150e864..2dfbb764bc 100644
--- a/esp32c3/src/system/perip_rst_en1.rs
+++ b/esp32c3/src/system/perip_rst_en1.rs
@@ -98,43 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_RST_EN1")
-            .field(
-                "crypto_aes_rst",
-                &format_args!("{}", self.crypto_aes_rst().bit()),
-            )
-            .field(
-                "crypto_sha_rst",
-                &format_args!("{}", self.crypto_sha_rst().bit()),
-            )
-            .field(
-                "crypto_rsa_rst",
-                &format_args!("{}", self.crypto_rsa_rst().bit()),
-            )
-            .field(
-                "crypto_ds_rst",
-                &format_args!("{}", self.crypto_ds_rst().bit()),
-            )
-            .field(
-                "crypto_hmac_rst",
-                &format_args!("{}", self.crypto_hmac_rst().bit()),
-            )
-            .field("dma_rst", &format_args!("{}", self.dma_rst().bit()))
-            .field(
-                "sdio_host_rst",
-                &format_args!("{}", self.sdio_host_rst().bit()),
-            )
-            .field("lcd_cam_rst", &format_args!("{}", self.lcd_cam_rst().bit()))
-            .field("uart2_rst", &format_args!("{}", self.uart2_rst().bit()))
-            .field("tsens_rst", &format_args!("{}", self.tsens_rst().bit()))
+            .field("crypto_aes_rst", &self.crypto_aes_rst())
+            .field("crypto_sha_rst", &self.crypto_sha_rst())
+            .field("crypto_rsa_rst", &self.crypto_rsa_rst())
+            .field("crypto_ds_rst", &self.crypto_ds_rst())
+            .field("crypto_hmac_rst", &self.crypto_hmac_rst())
+            .field("dma_rst", &self.dma_rst())
+            .field("sdio_host_rst", &self.sdio_host_rst())
+            .field("lcd_cam_rst", &self.lcd_cam_rst())
+            .field("uart2_rst", &self.uart2_rst())
+            .field("tsens_rst", &self.tsens_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_RST_EN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - reg_crypto_aes_rst"]
     #[inline(always)]
diff --git a/esp32c3/src/system/redundant_eco_ctrl.rs b/esp32c3/src/system/redundant_eco_ctrl.rs
index f77b0357ec..0460bc2fe7 100644
--- a/esp32c3/src/system/redundant_eco_ctrl.rs
+++ b/esp32c3/src/system/redundant_eco_ctrl.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDUNDANT_ECO_CTRL")
-            .field(
-                "redundant_eco_drive",
-                &format_args!("{}", self.redundant_eco_drive().bit()),
-            )
-            .field(
-                "redundant_eco_result",
-                &format_args!("{}", self.redundant_eco_result().bit()),
-            )
+            .field("redundant_eco_drive", &self.redundant_eco_drive())
+            .field("redundant_eco_result", &self.redundant_eco_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDUNDANT_ECO_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_redundant_eco_drive"]
     #[inline(always)]
diff --git a/esp32c3/src/system/rsa_pd_ctrl.rs b/esp32c3/src/system/rsa_pd_ctrl.rs
index b0fdc40f1d..e8ddc2ba8b 100644
--- a/esp32c3/src/system/rsa_pd_ctrl.rs
+++ b/esp32c3/src/system/rsa_pd_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_PD_CTRL")
-            .field("rsa_mem_pd", &format_args!("{}", self.rsa_mem_pd().bit()))
-            .field(
-                "rsa_mem_force_pu",
-                &format_args!("{}", self.rsa_mem_force_pu().bit()),
-            )
-            .field(
-                "rsa_mem_force_pd",
-                &format_args!("{}", self.rsa_mem_force_pd().bit()),
-            )
+            .field("rsa_mem_pd", &self.rsa_mem_pd())
+            .field("rsa_mem_force_pu", &self.rsa_mem_force_pu())
+            .field("rsa_mem_force_pd", &self.rsa_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_rsa_mem_pd"]
     #[inline(always)]
diff --git a/esp32c3/src/system/rtc_fastmem_config.rs b/esp32c3/src/system/rtc_fastmem_config.rs
index dfde7d1394..8da4d4b8cd 100644
--- a/esp32c3/src/system/rtc_fastmem_config.rs
+++ b/esp32c3/src/system/rtc_fastmem_config.rs
@@ -42,31 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_FASTMEM_CONFIG")
-            .field(
-                "rtc_mem_crc_start",
-                &format_args!("{}", self.rtc_mem_crc_start().bit()),
-            )
-            .field(
-                "rtc_mem_crc_addr",
-                &format_args!("{}", self.rtc_mem_crc_addr().bits()),
-            )
-            .field(
-                "rtc_mem_crc_len",
-                &format_args!("{}", self.rtc_mem_crc_len().bits()),
-            )
-            .field(
-                "rtc_mem_crc_finish",
-                &format_args!("{}", self.rtc_mem_crc_finish().bit()),
-            )
+            .field("rtc_mem_crc_start", &self.rtc_mem_crc_start())
+            .field("rtc_mem_crc_addr", &self.rtc_mem_crc_addr())
+            .field("rtc_mem_crc_len", &self.rtc_mem_crc_len())
+            .field("rtc_mem_crc_finish", &self.rtc_mem_crc_finish())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_FASTMEM_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - reg_rtc_mem_crc_start"]
     #[inline(always)]
diff --git a/esp32c3/src/system/rtc_fastmem_crc.rs b/esp32c3/src/system/rtc_fastmem_crc.rs
index ed38665f37..c25ef64025 100644
--- a/esp32c3/src/system/rtc_fastmem_crc.rs
+++ b/esp32c3/src/system/rtc_fastmem_crc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_FASTMEM_CRC")
-            .field(
-                "rtc_mem_crc_res",
-                &format_args!("{}", self.rtc_mem_crc_res().bits()),
-            )
+            .field("rtc_mem_crc_res", &self.rtc_mem_crc_res())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_FASTMEM_CRC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_fastmem_crc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTC_FASTMEM_CRC_SPEC;
 impl crate::RegisterSpec for RTC_FASTMEM_CRC_SPEC {
diff --git a/esp32c3/src/system/sysclk_conf.rs b/esp32c3/src/system/sysclk_conf.rs
index df0f4ec85a..e3d2dc2faa 100644
--- a/esp32c3/src/system/sysclk_conf.rs
+++ b/esp32c3/src/system/sysclk_conf.rs
@@ -40,28 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSCLK_CONF")
-            .field(
-                "pre_div_cnt",
-                &format_args!("{}", self.pre_div_cnt().bits()),
-            )
-            .field(
-                "soc_clk_sel",
-                &format_args!("{}", self.soc_clk_sel().bits()),
-            )
-            .field(
-                "clk_xtal_freq",
-                &format_args!("{}", self.clk_xtal_freq().bits()),
-            )
-            .field("clk_div_en", &format_args!("{}", self.clk_div_en().bit()))
+            .field("pre_div_cnt", &self.pre_div_cnt())
+            .field("soc_clk_sel", &self.soc_clk_sel())
+            .field("clk_xtal_freq", &self.clk_xtal_freq())
+            .field("clk_div_en", &self.clk_div_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - reg_pre_div_cnt"]
     #[inline(always)]
diff --git a/esp32c3/src/system/system_reg_date.rs b/esp32c3/src/system/system_reg_date.rs
index 68282d44f9..6fa680ff25 100644
--- a/esp32c3/src/system/system_reg_date.rs
+++ b/esp32c3/src/system/system_reg_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTEM_REG_DATE")
-            .field(
-                "system_reg_date",
-                &format_args!("{}", self.system_reg_date().bits()),
-            )
+            .field("system_reg_date", &self.system_reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTEM_REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - reg_system_reg_date"]
     #[inline(always)]
diff --git a/esp32c3/src/systimer/conf.rs b/esp32c3/src/systimer/conf.rs
index 28e29efd0d..fb002fa2c3 100644
--- a/esp32c3/src/systimer/conf.rs
+++ b/esp32c3/src/systimer/conf.rs
@@ -107,56 +107,32 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field(
-                "systimer_clk_fo",
-                &format_args!("{}", self.systimer_clk_fo().bit()),
-            )
-            .field(
-                "target2_work_en",
-                &format_args!("{}", self.target2_work_en().bit()),
-            )
-            .field(
-                "target1_work_en",
-                &format_args!("{}", self.target1_work_en().bit()),
-            )
-            .field(
-                "target0_work_en",
-                &format_args!("{}", self.target0_work_en().bit()),
-            )
+            .field("systimer_clk_fo", &self.systimer_clk_fo())
+            .field("target2_work_en", &self.target2_work_en())
+            .field("target1_work_en", &self.target1_work_en())
+            .field("target0_work_en", &self.target0_work_en())
             .field(
                 "timer_unit1_core1_stall_en",
-                &format_args!("{}", self.timer_unit1_core1_stall_en().bit()),
+                &self.timer_unit1_core1_stall_en(),
             )
             .field(
                 "timer_unit1_core0_stall_en",
-                &format_args!("{}", self.timer_unit1_core0_stall_en().bit()),
+                &self.timer_unit1_core0_stall_en(),
             )
             .field(
                 "timer_unit0_core1_stall_en",
-                &format_args!("{}", self.timer_unit0_core1_stall_en().bit()),
+                &self.timer_unit0_core1_stall_en(),
             )
             .field(
                 "timer_unit0_core0_stall_en",
-                &format_args!("{}", self.timer_unit0_core0_stall_en().bit()),
+                &self.timer_unit0_core0_stall_en(),
             )
-            .field(
-                "timer_unit1_work_en",
-                &format_args!("{}", self.timer_unit1_work_en().bit()),
-            )
-            .field(
-                "timer_unit0_work_en",
-                &format_args!("{}", self.timer_unit0_work_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("timer_unit1_work_en", &self.timer_unit1_work_en())
+            .field("timer_unit0_work_en", &self.timer_unit0_work_en())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - systimer clock force on"]
     #[inline(always)]
diff --git a/esp32c3/src/systimer/date.rs b/esp32c3/src/systimer/date.rs
index 204800733b..e9b0eca697 100644
--- a/esp32c3/src/systimer/date.rs
+++ b/esp32c3/src/systimer/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/systimer/int_ena.rs b/esp32c3/src/systimer/int_ena.rs
index 6cfe508a85..3517d160cb 100644
--- a/esp32c3/src/systimer/int_ena.rs
+++ b/esp32c3/src/systimer/int_ena.rs
@@ -42,18 +42,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "interupt(0-2) enable"]
     #[doc = ""]
diff --git a/esp32c3/src/systimer/int_raw.rs b/esp32c3/src/systimer/int_raw.rs
index 08460edd30..0a821a597f 100644
--- a/esp32c3/src/systimer/int_raw.rs
+++ b/esp32c3/src/systimer/int_raw.rs
@@ -42,18 +42,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "interupt(0-2) raw"]
     #[doc = ""]
diff --git a/esp32c3/src/systimer/int_st.rs b/esp32c3/src/systimer/int_st.rs
index d1936c356e..2f78b2cbc9 100644
--- a/esp32c3/src/systimer/int_st.rs
+++ b/esp32c3/src/systimer/int_st.rs
@@ -38,18 +38,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SYSTIMER_INT_ST.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c3/src/systimer/target_conf.rs b/esp32c3/src/systimer/target_conf.rs
index c6f5155c77..11fe19d61a 100644
--- a/esp32c3/src/systimer/target_conf.rs
+++ b/esp32c3/src/systimer/target_conf.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TARGET_CONF")
-            .field("period", &format_args!("{}", self.period().bits()))
-            .field("period_mode", &format_args!("{}", self.period_mode().bit()))
-            .field(
-                "timer_unit_sel",
-                &format_args!("{}", self.timer_unit_sel().bit()),
-            )
+            .field("period", &self.period())
+            .field("period_mode", &self.period_mode())
+            .field("timer_unit_sel", &self.timer_unit_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TARGET_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - target0 period"]
     #[inline(always)]
diff --git a/esp32c3/src/systimer/trgt/hi.rs b/esp32c3/src/systimer/trgt/hi.rs
index ba53843a24..8522a3b971 100644
--- a/esp32c3/src/systimer/trgt/hi.rs
+++ b/esp32c3/src/systimer/trgt/hi.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/systimer/trgt/lo.rs b/esp32c3/src/systimer/trgt/lo.rs
index e69a59de46..f36f8ea864 100644
--- a/esp32c3/src/systimer/trgt/lo.rs
+++ b/esp32c3/src/systimer/trgt/lo.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/systimer/unit_op.rs b/esp32c3/src/systimer/unit_op.rs
index 1110fab80c..826b459690 100644
--- a/esp32c3/src/systimer/unit_op.rs
+++ b/esp32c3/src/systimer/unit_op.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UNIT_OP")
-            .field("value_valid", &format_args!("{}", self.value_valid().bit()))
+            .field("value_valid", &self.value_valid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UNIT_OP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - update timer_unit0"]
     #[inline(always)]
diff --git a/esp32c3/src/systimer/unit_value/hi.rs b/esp32c3/src/systimer/unit_value/hi.rs
index 3b982af09b..96f8a79eb8 100644
--- a/esp32c3/src/systimer/unit_value/hi.rs
+++ b/esp32c3/src/systimer/unit_value/hi.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HI")
-            .field("value_hi", &format_args!("{}", self.value_hi().bits()))
+            .field("value_hi", &self.value_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SYSTIMER_UNIT0_VALUE_HI.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HI_SPEC;
 impl crate::RegisterSpec for HI_SPEC {
diff --git a/esp32c3/src/systimer/unit_value/lo.rs b/esp32c3/src/systimer/unit_value/lo.rs
index 03ea0929e8..f00009c20d 100644
--- a/esp32c3/src/systimer/unit_value/lo.rs
+++ b/esp32c3/src/systimer/unit_value/lo.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LO")
-            .field("value_lo", &format_args!("{}", self.value_lo().bits()))
+            .field("value_lo", &self.value_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SYSTIMER_UNIT0_VALUE_LO.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LO_SPEC;
 impl crate::RegisterSpec for LO_SPEC {
diff --git a/esp32c3/src/systimer/unitload/hi.rs b/esp32c3/src/systimer/unitload/hi.rs
index 981a1378ff..d637f06519 100644
--- a/esp32c3/src/systimer/unitload/hi.rs
+++ b/esp32c3/src/systimer/unitload/hi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - timer unit0 load high 32 bit"]
     #[inline(always)]
diff --git a/esp32c3/src/systimer/unitload/lo.rs b/esp32c3/src/systimer/unitload/lo.rs
index 73d0fa705c..0a80f845b9 100644
--- a/esp32c3/src/systimer/unitload/lo.rs
+++ b/esp32c3/src/systimer/unitload/lo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - timer unit0 load low 32 bit"]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/int_ena_timers.rs b/esp32c3/src/timg0/int_ena_timers.rs
index e98ffbde35..01402ae44e 100644
--- a/esp32c3/src/timg0/int_ena_timers.rs
+++ b/esp32c3/src/timg0/int_ena_timers.rs
@@ -41,17 +41,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "t(0-0)_int_ena"]
     #[doc = ""]
diff --git a/esp32c3/src/timg0/int_raw_timers.rs b/esp32c3/src/timg0/int_raw_timers.rs
index b12fa4ee8c..949806954f 100644
--- a/esp32c3/src/timg0/int_raw_timers.rs
+++ b/esp32c3/src/timg0/int_raw_timers.rs
@@ -35,17 +35,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "INT_RAW_TIMG_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_TIMERS_SPEC;
 impl crate::RegisterSpec for INT_RAW_TIMERS_SPEC {
diff --git a/esp32c3/src/timg0/int_st_timers.rs b/esp32c3/src/timg0/int_st_timers.rs
index 2bf4955df8..36a003e410 100644
--- a/esp32c3/src/timg0/int_st_timers.rs
+++ b/esp32c3/src/timg0/int_st_timers.rs
@@ -35,17 +35,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "INT_ST_TIMG_REG\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_TIMERS_SPEC;
 impl crate::RegisterSpec for INT_ST_TIMERS_SPEC {
diff --git a/esp32c3/src/timg0/ntimg_date.rs b/esp32c3/src/timg0/ntimg_date.rs
index 73bf2f9410..380f1f755b 100644
--- a/esp32c3/src/timg0/ntimg_date.rs
+++ b/esp32c3/src/timg0/ntimg_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NTIMG_DATE")
-            .field(
-                "ntimgs_date",
-                &format_args!("{}", self.ntimgs_date().bits()),
-            )
+            .field("ntimgs_date", &self.ntimgs_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NTIMG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - reg_ntimers_date."]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/regclk.rs b/esp32c3/src/timg0/regclk.rs
index e9df70f62e..82a5fcfdb6 100644
--- a/esp32c3/src/timg0/regclk.rs
+++ b/esp32c3/src/timg0/regclk.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGCLK")
-            .field(
-                "wdt_clk_is_active",
-                &format_args!("{}", self.wdt_clk_is_active().bit()),
-            )
-            .field(
-                "timer_clk_is_active",
-                &format_args!("{}", self.timer_clk_is_active().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("wdt_clk_is_active", &self.wdt_clk_is_active())
+            .field("timer_clk_is_active", &self.timer_clk_is_active())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 29 - reg_wdt_clk_is_active."]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/rtccalicfg.rs b/esp32c3/src/timg0/rtccalicfg.rs
index f9672a28d3..901a66b9c2 100644
--- a/esp32c3/src/timg0/rtccalicfg.rs
+++ b/esp32c3/src/timg0/rtccalicfg.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG")
-            .field(
-                "rtc_cali_start_cycling",
-                &format_args!("{}", self.rtc_cali_start_cycling().bit()),
-            )
-            .field(
-                "rtc_cali_clk_sel",
-                &format_args!("{}", self.rtc_cali_clk_sel().bits()),
-            )
-            .field(
-                "rtc_cali_rdy",
-                &format_args!("{}", self.rtc_cali_rdy().bit()),
-            )
-            .field(
-                "rtc_cali_max",
-                &format_args!("{}", self.rtc_cali_max().bits()),
-            )
-            .field(
-                "rtc_cali_start",
-                &format_args!("{}", self.rtc_cali_start().bit()),
-            )
+            .field("rtc_cali_start_cycling", &self.rtc_cali_start_cycling())
+            .field("rtc_cali_clk_sel", &self.rtc_cali_clk_sel())
+            .field("rtc_cali_rdy", &self.rtc_cali_rdy())
+            .field("rtc_cali_max", &self.rtc_cali_max())
+            .field("rtc_cali_start", &self.rtc_cali_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - reg_rtc_cali_start_cycling."]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/rtccalicfg1.rs b/esp32c3/src/timg0/rtccalicfg1.rs
index 01fe7c9f74..f1f97c4b9f 100644
--- a/esp32c3/src/timg0/rtccalicfg1.rs
+++ b/esp32c3/src/timg0/rtccalicfg1.rs
@@ -22,21 +22,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("RTCCALICFG1")
             .field(
                 "rtc_cali_cycling_data_vld",
-                &format_args!("{}", self.rtc_cali_cycling_data_vld().bit()),
-            )
-            .field(
-                "rtc_cali_value",
-                &format_args!("{}", self.rtc_cali_value().bits()),
+                &self.rtc_cali_cycling_data_vld(),
             )
+            .field("rtc_cali_value", &self.rtc_cali_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TIMG_RTCCALICFG1_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtccalicfg1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTCCALICFG1_SPEC;
 impl crate::RegisterSpec for RTCCALICFG1_SPEC {
diff --git a/esp32c3/src/timg0/rtccalicfg2.rs b/esp32c3/src/timg0/rtccalicfg2.rs
index 042d356daf..5ed9aa4a5f 100644
--- a/esp32c3/src/timg0/rtccalicfg2.rs
+++ b/esp32c3/src/timg0/rtccalicfg2.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG2")
-            .field(
-                "rtc_cali_timeout",
-                &format_args!("{}", self.rtc_cali_timeout().bit()),
-            )
-            .field(
-                "rtc_cali_timeout_rst_cnt",
-                &format_args!("{}", self.rtc_cali_timeout_rst_cnt().bits()),
-            )
-            .field(
-                "rtc_cali_timeout_thres",
-                &format_args!("{}", self.rtc_cali_timeout_thres().bits()),
-            )
+            .field("rtc_cali_timeout", &self.rtc_cali_timeout())
+            .field("rtc_cali_timeout_rst_cnt", &self.rtc_cali_timeout_rst_cnt())
+            .field("rtc_cali_timeout_thres", &self.rtc_cali_timeout_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:6 - reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset"]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/t/alarmhi.rs b/esp32c3/src/timg0/t/alarmhi.rs
index 177c88cb4a..03d657db6a 100644
--- a/esp32c3/src/timg0/t/alarmhi.rs
+++ b/esp32c3/src/timg0/t/alarmhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMHI")
-            .field("alarm_hi", &format_args!("{}", self.alarm_hi().bits()))
+            .field("alarm_hi", &self.alarm_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - reg_t0_alarm_hi."]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/t/alarmlo.rs b/esp32c3/src/timg0/t/alarmlo.rs
index 2ef42569a7..0bc9da6d84 100644
--- a/esp32c3/src/timg0/t/alarmlo.rs
+++ b/esp32c3/src/timg0/t/alarmlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMLO")
-            .field("alarm_lo", &format_args!("{}", self.alarm_lo().bits()))
+            .field("alarm_lo", &self.alarm_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_t0_alarm_lo."]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/t/config.rs b/esp32c3/src/timg0/t/config.rs
index 1daa7d2e22..57bb4e390f 100644
--- a/esp32c3/src/timg0/t/config.rs
+++ b/esp32c3/src/timg0/t/config.rs
@@ -64,21 +64,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG")
-            .field("use_xtal", &format_args!("{}", self.use_xtal().bit()))
-            .field("alarm_en", &format_args!("{}", self.alarm_en().bit()))
-            .field("divider", &format_args!("{}", self.divider().bits()))
-            .field("autoreload", &format_args!("{}", self.autoreload().bit()))
-            .field("increase", &format_args!("{}", self.increase().bit()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("use_xtal", &self.use_xtal())
+            .field("alarm_en", &self.alarm_en())
+            .field("divider", &self.divider())
+            .field("autoreload", &self.autoreload())
+            .field("increase", &self.increase())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - reg_t0_use_xtal."]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/t/hi.rs b/esp32c3/src/timg0/t/hi.rs
index bfd2cdadea..acff7204f0 100644
--- a/esp32c3/src/timg0/t/hi.rs
+++ b/esp32c3/src/timg0/t/hi.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
     }
 }
 #[doc = "TIMG_T0HI_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c3/src/timg0/t/lo.rs b/esp32c3/src/timg0/t/lo.rs
index 57ff65374e..96bb51c605 100644
--- a/esp32c3/src/timg0/t/lo.rs
+++ b/esp32c3/src/timg0/t/lo.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
     }
 }
 #[doc = "TIMG_T0LO_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c3/src/timg0/t/loadhi.rs b/esp32c3/src/timg0/t/loadhi.rs
index e7c3d44efd..6f4a3cfb60 100644
--- a/esp32c3/src/timg0/t/loadhi.rs
+++ b/esp32c3/src/timg0/t/loadhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADHI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - reg_t0_load_hi."]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/t/loadlo.rs b/esp32c3/src/timg0/t/loadlo.rs
index 1e4a65257f..482b8e3a38 100644
--- a/esp32c3/src/timg0/t/loadlo.rs
+++ b/esp32c3/src/timg0/t/loadlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADLO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_t0_load_lo."]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/t/update.rs b/esp32c3/src/timg0/t/update.rs
index e248994cc9..24927bfe7e 100644
--- a/esp32c3/src/timg0/t/update.rs
+++ b/esp32c3/src/timg0/t/update.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE")
-            .field("update", &format_args!("{}", self.update().bit()))
+            .field("update", &self.update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - t0_update"]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/wdtconfig0.rs b/esp32c3/src/timg0/wdtconfig0.rs
index 6e8dd20ef7..f853181242 100644
--- a/esp32c3/src/timg0/wdtconfig0.rs
+++ b/esp32c3/src/timg0/wdtconfig0.rs
@@ -109,44 +109,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG0")
-            .field(
-                "wdt_appcpu_reset_en",
-                &format_args!("{}", self.wdt_appcpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field(
-                "wdt_use_xtal",
-                &format_args!("{}", self.wdt_use_xtal().bit()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_use_xtal", &self.wdt_use_xtal())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - reg_wdt_appcpu_reset_en."]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/wdtconfig1.rs b/esp32c3/src/timg0/wdtconfig1.rs
index b81b989db7..e438269f43 100644
--- a/esp32c3/src/timg0/wdtconfig1.rs
+++ b/esp32c3/src/timg0/wdtconfig1.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG1")
-            .field(
-                "wdt_clk_prescale",
-                &format_args!("{}", self.wdt_clk_prescale().bits()),
-            )
+            .field("wdt_clk_prescale", &self.wdt_clk_prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_wdt_divcnt_rst."]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/wdtconfig2.rs b/esp32c3/src/timg0/wdtconfig2.rs
index dfa357a329..d13c5bd741 100644
--- a/esp32c3/src/timg0/wdtconfig2.rs
+++ b/esp32c3/src/timg0/wdtconfig2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG2")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_wdt_stg0_hold."]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/wdtconfig3.rs b/esp32c3/src/timg0/wdtconfig3.rs
index 63351520d8..148dead57c 100644
--- a/esp32c3/src/timg0/wdtconfig3.rs
+++ b/esp32c3/src/timg0/wdtconfig3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG3")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_wdt_stg1_hold."]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/wdtconfig4.rs b/esp32c3/src/timg0/wdtconfig4.rs
index 210e15f588..5a5a4e8b63 100644
--- a/esp32c3/src/timg0/wdtconfig4.rs
+++ b/esp32c3/src/timg0/wdtconfig4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG4")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_wdt_stg2_hold."]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/wdtconfig5.rs b/esp32c3/src/timg0/wdtconfig5.rs
index cdf756580c..9f7947c05a 100644
--- a/esp32c3/src/timg0/wdtconfig5.rs
+++ b/esp32c3/src/timg0/wdtconfig5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG5")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_wdt_stg3_hold."]
     #[inline(always)]
diff --git a/esp32c3/src/timg0/wdtwprotect.rs b/esp32c3/src/timg0/wdtwprotect.rs
index 72fe0ddf42..8dd352bfed 100644
--- a/esp32c3/src/timg0/wdtwprotect.rs
+++ b/esp32c3/src/timg0/wdtwprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTWPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTWPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reg_wdt_wkey."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/arb_lost_cap.rs b/esp32c3/src/twai0/arb_lost_cap.rs
index 20ab158c4b..02b4812ac4 100644
--- a/esp32c3/src/twai0/arb_lost_cap.rs
+++ b/esp32c3/src/twai0/arb_lost_cap.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_LOST_CAP")
-            .field(
-                "arb_lost_cap",
-                &format_args!("{}", self.arb_lost_cap().bits()),
-            )
+            .field("arb_lost_cap", &self.arb_lost_cap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_LOST_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Arbitration Lost Capture Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_lost_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ARB_LOST_CAP_SPEC;
 impl crate::RegisterSpec for ARB_LOST_CAP_SPEC {
diff --git a/esp32c3/src/twai0/bus_timing_0.rs b/esp32c3/src/twai0/bus_timing_0.rs
index 4fe29d9648..c26ca19211 100644
--- a/esp32c3/src/twai0/bus_timing_0.rs
+++ b/esp32c3/src/twai0/bus_timing_0.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMING_0")
-            .field("baud_presc", &format_args!("{}", self.baud_presc().bits()))
-            .field(
-                "sync_jump_width",
-                &format_args!("{}", self.sync_jump_width().bits()),
-            )
+            .field("baud_presc", &self.baud_presc())
+            .field("sync_jump_width", &self.sync_jump_width())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMING_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Baud Rate Prescaler, determines the frequency dividing ratio."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/bus_timing_1.rs b/esp32c3/src/twai0/bus_timing_1.rs
index ec698b25b8..89a5dcc905 100644
--- a/esp32c3/src/twai0/bus_timing_1.rs
+++ b/esp32c3/src/twai0/bus_timing_1.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMING_1")
-            .field("time_seg1", &format_args!("{}", self.time_seg1().bits()))
-            .field("time_seg2", &format_args!("{}", self.time_seg2().bits()))
-            .field("time_samp", &format_args!("{}", self.time_samp().bit()))
+            .field("time_seg1", &self.time_seg1())
+            .field("time_seg2", &self.time_seg2())
+            .field("time_samp", &self.time_samp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMING_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The width of PBS1."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/clock_divider.rs b/esp32c3/src/twai0/clock_divider.rs
index 9d5176aca5..3021eab737 100644
--- a/esp32c3/src/twai0/clock_divider.rs
+++ b/esp32c3/src/twai0/clock_divider.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_DIVIDER")
-            .field("cd", &format_args!("{}", self.cd().bits()))
-            .field("clock_off", &format_args!("{}", self.clock_off().bit()))
+            .field("cd", &self.cd())
+            .field("clock_off", &self.clock_off())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_DIVIDER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - These bits are used to configure frequency dividing coefficients of the external CLKOUT pin."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/data_0.rs b/esp32c3/src/twai0/data_0.rs
index 00a1461389..5f957580e7 100644
--- a/esp32c3/src/twai0/data_0.rs
+++ b/esp32c3/src/twai0/data_0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_0")
-            .field("tx_byte_0", &format_args!("{}", self.tx_byte_0().bits()))
+            .field("tx_byte_0", &self.tx_byte_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/data_1.rs b/esp32c3/src/twai0/data_1.rs
index 4ad4852747..e6974e1afd 100644
--- a/esp32c3/src/twai0/data_1.rs
+++ b/esp32c3/src/twai0/data_1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_1")
-            .field("tx_byte_1", &format_args!("{}", self.tx_byte_1().bits()))
+            .field("tx_byte_1", &self.tx_byte_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/data_10.rs b/esp32c3/src/twai0/data_10.rs
index 87ec0e6d1e..37ce8ef039 100644
--- a/esp32c3/src/twai0/data_10.rs
+++ b/esp32c3/src/twai0/data_10.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_10")
-            .field("tx_byte_10", &format_args!("{}", self.tx_byte_10().bits()))
+            .field("tx_byte_10", &self.tx_byte_10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In operation mode, it stores the 10th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/data_11.rs b/esp32c3/src/twai0/data_11.rs
index d2696f566a..08c040056f 100644
--- a/esp32c3/src/twai0/data_11.rs
+++ b/esp32c3/src/twai0/data_11.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_11")
-            .field("tx_byte_11", &format_args!("{}", self.tx_byte_11().bits()))
+            .field("tx_byte_11", &self.tx_byte_11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In operation mode, it stores the 11th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/data_12.rs b/esp32c3/src/twai0/data_12.rs
index a3ca42a795..4b77f30d70 100644
--- a/esp32c3/src/twai0/data_12.rs
+++ b/esp32c3/src/twai0/data_12.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_12")
-            .field("tx_byte_12", &format_args!("{}", self.tx_byte_12().bits()))
+            .field("tx_byte_12", &self.tx_byte_12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In operation mode, it stores the 12th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/data_2.rs b/esp32c3/src/twai0/data_2.rs
index ba7eb5d0e9..3aea82e64d 100644
--- a/esp32c3/src/twai0/data_2.rs
+++ b/esp32c3/src/twai0/data_2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_2")
-            .field("tx_byte_2", &format_args!("{}", self.tx_byte_2().bits()))
+            .field("tx_byte_2", &self.tx_byte_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/data_3.rs b/esp32c3/src/twai0/data_3.rs
index 3621b8f216..937c81e160 100644
--- a/esp32c3/src/twai0/data_3.rs
+++ b/esp32c3/src/twai0/data_3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_3")
-            .field("tx_byte_3", &format_args!("{}", self.tx_byte_3().bits()))
+            .field("tx_byte_3", &self.tx_byte_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/data_4.rs b/esp32c3/src/twai0/data_4.rs
index f20cd12126..9f0442a76f 100644
--- a/esp32c3/src/twai0/data_4.rs
+++ b/esp32c3/src/twai0/data_4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_4")
-            .field("tx_byte_4", &format_args!("{}", self.tx_byte_4().bits()))
+            .field("tx_byte_4", &self.tx_byte_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 4 with R/W Permission. In operation mode, it stores the 4th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/data_5.rs b/esp32c3/src/twai0/data_5.rs
index 798cb7b8e1..9948f656f4 100644
--- a/esp32c3/src/twai0/data_5.rs
+++ b/esp32c3/src/twai0/data_5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_5")
-            .field("tx_byte_5", &format_args!("{}", self.tx_byte_5().bits()))
+            .field("tx_byte_5", &self.tx_byte_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 5 with R/W Permission. In operation mode, it stores the 5th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/data_6.rs b/esp32c3/src/twai0/data_6.rs
index 303986185c..1258bbf48e 100644
--- a/esp32c3/src/twai0/data_6.rs
+++ b/esp32c3/src/twai0/data_6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_6")
-            .field("tx_byte_6", &format_args!("{}", self.tx_byte_6().bits()))
+            .field("tx_byte_6", &self.tx_byte_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 6 with R/W Permission. In operation mode, it stores the 6th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/data_7.rs b/esp32c3/src/twai0/data_7.rs
index c6ef614333..a1cf410137 100644
--- a/esp32c3/src/twai0/data_7.rs
+++ b/esp32c3/src/twai0/data_7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_7")
-            .field("tx_byte_7", &format_args!("{}", self.tx_byte_7().bits()))
+            .field("tx_byte_7", &self.tx_byte_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 7 with R/W Permission. In operation mode, it stores the 7th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/data_8.rs b/esp32c3/src/twai0/data_8.rs
index 21bf863919..43767e85d7 100644
--- a/esp32c3/src/twai0/data_8.rs
+++ b/esp32c3/src/twai0/data_8.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_8")
-            .field("tx_byte_8", &format_args!("{}", self.tx_byte_8().bits()))
+            .field("tx_byte_8", &self.tx_byte_8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In operation mode, it stores the 8th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/data_9.rs b/esp32c3/src/twai0/data_9.rs
index 08e9bdbb10..bcd0c3e54f 100644
--- a/esp32c3/src/twai0/data_9.rs
+++ b/esp32c3/src/twai0/data_9.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_9")
-            .field("tx_byte_9", &format_args!("{}", self.tx_byte_9().bits()))
+            .field("tx_byte_9", &self.tx_byte_9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In operation mode, it stores the 9th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/err_code_cap.rs b/esp32c3/src/twai0/err_code_cap.rs
index 77f4f8b361..f4ce2b4b16 100644
--- a/esp32c3/src/twai0/err_code_cap.rs
+++ b/esp32c3/src/twai0/err_code_cap.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERR_CODE_CAP")
-            .field(
-                "ecc_segment",
-                &format_args!("{}", self.ecc_segment().bits()),
-            )
-            .field(
-                "ecc_direction",
-                &format_args!("{}", self.ecc_direction().bit()),
-            )
-            .field("ecc_type", &format_args!("{}", self.ecc_type().bits()))
+            .field("ecc_segment", &self.ecc_segment())
+            .field("ecc_direction", &self.ecc_direction())
+            .field("ecc_type", &self.ecc_type())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERR_CODE_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Error Code Capture Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_code_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ERR_CODE_CAP_SPEC;
 impl crate::RegisterSpec for ERR_CODE_CAP_SPEC {
diff --git a/esp32c3/src/twai0/err_warning_limit.rs b/esp32c3/src/twai0/err_warning_limit.rs
index eaca9801b5..0197a2df38 100644
--- a/esp32c3/src/twai0/err_warning_limit.rs
+++ b/esp32c3/src/twai0/err_warning_limit.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERR_WARNING_LIMIT")
-            .field(
-                "err_warning_limit",
-                &format_args!("{}", self.err_warning_limit().bits()),
-            )
+            .field("err_warning_limit", &self.err_warning_limit())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERR_WARNING_LIMIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid)."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/int_ena.rs b/esp32c3/src/twai0/int_ena.rs
index 750cc94df5..01ac1eef65 100644
--- a/esp32c3/src/twai0/int_ena.rs
+++ b/esp32c3/src/twai0/int_ena.rs
@@ -71,37 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_int_ena", &format_args!("{}", self.rx_int_ena().bit()))
-            .field("tx_int_ena", &format_args!("{}", self.tx_int_ena().bit()))
-            .field(
-                "err_warn_int_ena",
-                &format_args!("{}", self.err_warn_int_ena().bit()),
-            )
-            .field(
-                "overrun_int_ena",
-                &format_args!("{}", self.overrun_int_ena().bit()),
-            )
-            .field(
-                "err_passive_int_ena",
-                &format_args!("{}", self.err_passive_int_ena().bit()),
-            )
-            .field(
-                "arb_lost_int_ena",
-                &format_args!("{}", self.arb_lost_int_ena().bit()),
-            )
-            .field(
-                "bus_err_int_ena",
-                &format_args!("{}", self.bus_err_int_ena().bit()),
-            )
+            .field("rx_int_ena", &self.rx_int_ena())
+            .field("tx_int_ena", &self.tx_int_ena())
+            .field("err_warn_int_ena", &self.err_warn_int_ena())
+            .field("overrun_int_ena", &self.overrun_int_ena())
+            .field("err_passive_int_ena", &self.err_passive_int_ena())
+            .field("arb_lost_int_ena", &self.arb_lost_int_ena())
+            .field("bus_err_int_ena", &self.bus_err_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable receive interrupt."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/int_raw.rs b/esp32c3/src/twai0/int_raw.rs
index bcb5a07717..fe0b2105a8 100644
--- a/esp32c3/src/twai0/int_raw.rs
+++ b/esp32c3/src/twai0/int_raw.rs
@@ -55,37 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_int_st", &format_args!("{}", self.rx_int_st().bit()))
-            .field("tx_int_st", &format_args!("{}", self.tx_int_st().bit()))
-            .field(
-                "err_warn_int_st",
-                &format_args!("{}", self.err_warn_int_st().bit()),
-            )
-            .field(
-                "overrun_int_st",
-                &format_args!("{}", self.overrun_int_st().bit()),
-            )
-            .field(
-                "err_passive_int_st",
-                &format_args!("{}", self.err_passive_int_st().bit()),
-            )
-            .field(
-                "arb_lost_int_st",
-                &format_args!("{}", self.arb_lost_int_st().bit()),
-            )
-            .field(
-                "bus_err_int_st",
-                &format_args!("{}", self.bus_err_int_st().bit()),
-            )
+            .field("rx_int_st", &self.rx_int_st())
+            .field("tx_int_st", &self.tx_int_st())
+            .field("err_warn_int_st", &self.err_warn_int_st())
+            .field("overrun_int_st", &self.overrun_int_st())
+            .field("err_passive_int_st", &self.err_passive_int_st())
+            .field("arb_lost_int_st", &self.arb_lost_int_st())
+            .field("bus_err_int_st", &self.bus_err_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32c3/src/twai0/mode.rs b/esp32c3/src/twai0/mode.rs
index dc3560c7e3..0d66f9a85c 100644
--- a/esp32c3/src/twai0/mode.rs
+++ b/esp32c3/src/twai0/mode.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODE")
-            .field("reset_mode", &format_args!("{}", self.reset_mode().bit()))
-            .field(
-                "listen_only_mode",
-                &format_args!("{}", self.listen_only_mode().bit()),
-            )
-            .field(
-                "self_test_mode",
-                &format_args!("{}", self.self_test_mode().bit()),
-            )
-            .field(
-                "rx_filter_mode",
-                &format_args!("{}", self.rx_filter_mode().bit()),
-            )
+            .field("reset_mode", &self.reset_mode())
+            .field("listen_only_mode", &self.listen_only_mode())
+            .field("self_test_mode", &self.self_test_mode())
+            .field("rx_filter_mode", &self.rx_filter_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/rx_err_cnt.rs b/esp32c3/src/twai0/rx_err_cnt.rs
index 66bf5c5d52..9c05d16bf3 100644
--- a/esp32c3/src/twai0/rx_err_cnt.rs
+++ b/esp32c3/src/twai0/rx_err_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ERR_CNT")
-            .field("rx_err_cnt", &format_args!("{}", self.rx_err_cnt().bits()))
+            .field("rx_err_cnt", &self.rx_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ERR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The RX error counter register, reflects value changes under reception status."]
     #[inline(always)]
diff --git a/esp32c3/src/twai0/rx_message_cnt.rs b/esp32c3/src/twai0/rx_message_cnt.rs
index 606f9b251e..13ca2f8eb4 100644
--- a/esp32c3/src/twai0/rx_message_cnt.rs
+++ b/esp32c3/src/twai0/rx_message_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_MESSAGE_CNT")
-            .field(
-                "rx_message_counter",
-                &format_args!("{}", self.rx_message_counter().bits()),
-            )
+            .field("rx_message_counter", &self.rx_message_counter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_MESSAGE_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive Message Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_message_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_MESSAGE_CNT_SPEC;
 impl crate::RegisterSpec for RX_MESSAGE_CNT_SPEC {
diff --git a/esp32c3/src/twai0/status.rs b/esp32c3/src/twai0/status.rs
index c9d0dd58e5..9a577030bd 100644
--- a/esp32c3/src/twai0/status.rs
+++ b/esp32c3/src/twai0/status.rs
@@ -69,24 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rx_buf_st", &format_args!("{}", self.rx_buf_st().bit()))
-            .field("overrun_st", &format_args!("{}", self.overrun_st().bit()))
-            .field("tx_buf_st", &format_args!("{}", self.tx_buf_st().bit()))
-            .field("tx_complete", &format_args!("{}", self.tx_complete().bit()))
-            .field("rx_st", &format_args!("{}", self.rx_st().bit()))
-            .field("tx_st", &format_args!("{}", self.tx_st().bit()))
-            .field("err_st", &format_args!("{}", self.err_st().bit()))
-            .field("bus_off_st", &format_args!("{}", self.bus_off_st().bit()))
-            .field("miss_st", &format_args!("{}", self.miss_st().bit()))
+            .field("rx_buf_st", &self.rx_buf_st())
+            .field("overrun_st", &self.overrun_st())
+            .field("tx_buf_st", &self.tx_buf_st())
+            .field("tx_complete", &self.tx_complete())
+            .field("rx_st", &self.rx_st())
+            .field("tx_st", &self.tx_st())
+            .field("err_st", &self.err_st())
+            .field("bus_off_st", &self.bus_off_st())
+            .field("miss_st", &self.miss_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32c3/src/twai0/tx_err_cnt.rs b/esp32c3/src/twai0/tx_err_cnt.rs
index 3fb0a9d0ef..5d5b84441c 100644
--- a/esp32c3/src/twai0/tx_err_cnt.rs
+++ b/esp32c3/src/twai0/tx_err_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_ERR_CNT")
-            .field("tx_err_cnt", &format_args!("{}", self.tx_err_cnt().bits()))
+            .field("tx_err_cnt", &self.tx_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_ERR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The TX error counter register, reflects value changes under transmission status."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/at_cmd_char.rs b/esp32c3/src/uart0/at_cmd_char.rs
index 17e9222fe8..e75e1409cd 100644
--- a/esp32c3/src/uart0/at_cmd_char.rs
+++ b/esp32c3/src/uart0/at_cmd_char.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_CHAR")
-            .field(
-                "at_cmd_char",
-                &format_args!("{}", self.at_cmd_char().bits()),
-            )
-            .field("char_num", &format_args!("{}", self.char_num().bits()))
+            .field("at_cmd_char", &self.at_cmd_char())
+            .field("char_num", &self.char_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_CHAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/at_cmd_gaptout.rs b/esp32c3/src/uart0/at_cmd_gaptout.rs
index c7373436b0..7091ac8125 100644
--- a/esp32c3/src/uart0/at_cmd_gaptout.rs
+++ b/esp32c3/src/uart0/at_cmd_gaptout.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_GAPTOUT")
-            .field(
-                "rx_gap_tout",
-                &format_args!("{}", self.rx_gap_tout().bits()),
-            )
+            .field("rx_gap_tout", &self.rx_gap_tout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_GAPTOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the at_cmd chars."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/at_cmd_postcnt.rs b/esp32c3/src/uart0/at_cmd_postcnt.rs
index 078c4bb6a1..5db8445554 100644
--- a/esp32c3/src/uart0/at_cmd_postcnt.rs
+++ b/esp32c3/src/uart0/at_cmd_postcnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_POSTCNT")
-            .field(
-                "post_idle_num",
-                &format_args!("{}", self.post_idle_num().bits()),
-            )
+            .field("post_idle_num", &self.post_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_POSTCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the last at_cmd and the next data."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/at_cmd_precnt.rs b/esp32c3/src/uart0/at_cmd_precnt.rs
index 9e4a1cc58c..41790b5e67 100644
--- a/esp32c3/src/uart0/at_cmd_precnt.rs
+++ b/esp32c3/src/uart0/at_cmd_precnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_PRECNT")
-            .field(
-                "pre_idle_num",
-                &format_args!("{}", self.pre_idle_num().bits()),
-            )
+            .field("pre_idle_num", &self.pre_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_PRECNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first at_cmd is received by receiver."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/clk_conf.rs b/esp32c3/src/uart0/clk_conf.rs
index 0ddb29638f..9f3c3a3eb2 100644
--- a/esp32c3/src/uart0/clk_conf.rs
+++ b/esp32c3/src/uart0/clk_conf.rs
@@ -98,28 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bits()))
-            .field("sclk_en", &format_args!("{}", self.sclk_en().bit()))
-            .field("rst_core", &format_args!("{}", self.rst_core().bit()))
-            .field("tx_sclk_en", &format_args!("{}", self.tx_sclk_en().bit()))
-            .field("rx_sclk_en", &format_args!("{}", self.rx_sclk_en().bit()))
-            .field("tx_rst_core", &format_args!("{}", self.tx_rst_core().bit()))
-            .field("rx_rst_core", &format_args!("{}", self.rx_rst_core().bit()))
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_en", &self.sclk_en())
+            .field("rst_core", &self.rst_core())
+            .field("tx_sclk_en", &self.tx_sclk_en())
+            .field("rx_sclk_en", &self.rx_sclk_en())
+            .field("tx_rst_core", &self.tx_rst_core())
+            .field("rx_rst_core", &self.rx_rst_core())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/clkdiv.rs b/esp32c3/src/uart0/clkdiv.rs
index c020543f66..0c1138e013 100644
--- a/esp32c3/src/uart0/clkdiv.rs
+++ b/esp32c3/src/uart0/clkdiv.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKDIV")
-            .field("clkdiv", &format_args!("{}", self.clkdiv().bits()))
-            .field("frag", &format_args!("{}", self.frag().bits()))
+            .field("clkdiv", &self.clkdiv())
+            .field("frag", &self.frag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKDIV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/conf0.rs b/esp32c3/src/uart0/conf0.rs
index a2981cbdc7..880c32a12e 100644
--- a/esp32c3/src/uart0/conf0.rs
+++ b/esp32c3/src/uart0/conf0.rs
@@ -251,45 +251,36 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("parity", &format_args!("{}", self.parity().bit()))
-            .field("parity_en", &format_args!("{}", self.parity_en().bit()))
-            .field("bit_num", &format_args!("{}", self.bit_num().bits()))
-            .field(
-                "stop_bit_num",
-                &format_args!("{}", self.stop_bit_num().bits()),
-            )
-            .field("sw_rts", &format_args!("{}", self.sw_rts().bit()))
-            .field("sw_dtr", &format_args!("{}", self.sw_dtr().bit()))
-            .field("txd_brk", &format_args!("{}", self.txd_brk().bit()))
-            .field("irda_dplx", &format_args!("{}", self.irda_dplx().bit()))
-            .field("irda_tx_en", &format_args!("{}", self.irda_tx_en().bit()))
-            .field("irda_wctl", &format_args!("{}", self.irda_wctl().bit()))
-            .field("irda_tx_inv", &format_args!("{}", self.irda_tx_inv().bit()))
-            .field("irda_rx_inv", &format_args!("{}", self.irda_rx_inv().bit()))
-            .field("loopback", &format_args!("{}", self.loopback().bit()))
-            .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit()))
-            .field("irda_en", &format_args!("{}", self.irda_en().bit()))
-            .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit()))
-            .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit()))
-            .field("rxd_inv", &format_args!("{}", self.rxd_inv().bit()))
-            .field("cts_inv", &format_args!("{}", self.cts_inv().bit()))
-            .field("dsr_inv", &format_args!("{}", self.dsr_inv().bit()))
-            .field("txd_inv", &format_args!("{}", self.txd_inv().bit()))
-            .field("rts_inv", &format_args!("{}", self.rts_inv().bit()))
-            .field("dtr_inv", &format_args!("{}", self.dtr_inv().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("err_wr_mask", &format_args!("{}", self.err_wr_mask().bit()))
-            .field("autobaud_en", &format_args!("{}", self.autobaud_en().bit()))
-            .field("mem_clk_en", &format_args!("{}", self.mem_clk_en().bit()))
+            .field("parity", &self.parity())
+            .field("parity_en", &self.parity_en())
+            .field("bit_num", &self.bit_num())
+            .field("stop_bit_num", &self.stop_bit_num())
+            .field("sw_rts", &self.sw_rts())
+            .field("sw_dtr", &self.sw_dtr())
+            .field("txd_brk", &self.txd_brk())
+            .field("irda_dplx", &self.irda_dplx())
+            .field("irda_tx_en", &self.irda_tx_en())
+            .field("irda_wctl", &self.irda_wctl())
+            .field("irda_tx_inv", &self.irda_tx_inv())
+            .field("irda_rx_inv", &self.irda_rx_inv())
+            .field("loopback", &self.loopback())
+            .field("tx_flow_en", &self.tx_flow_en())
+            .field("irda_en", &self.irda_en())
+            .field("rxfifo_rst", &self.rxfifo_rst())
+            .field("txfifo_rst", &self.txfifo_rst())
+            .field("rxd_inv", &self.rxd_inv())
+            .field("cts_inv", &self.cts_inv())
+            .field("dsr_inv", &self.dsr_inv())
+            .field("txd_inv", &self.txd_inv())
+            .field("rts_inv", &self.rts_inv())
+            .field("dtr_inv", &self.dtr_inv())
+            .field("clk_en", &self.clk_en())
+            .field("err_wr_mask", &self.err_wr_mask())
+            .field("autobaud_en", &self.autobaud_en())
+            .field("mem_clk_en", &self.mem_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to configure the parity check mode."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/conf1.rs b/esp32c3/src/uart0/conf1.rs
index b0b2648ed1..e255d104f4 100644
--- a/esp32c3/src/uart0/conf1.rs
+++ b/esp32c3/src/uart0/conf1.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "rxfifo_full_thrhd",
-                &format_args!("{}", self.rxfifo_full_thrhd().bits()),
-            )
-            .field(
-                "txfifo_empty_thrhd",
-                &format_args!("{}", self.txfifo_empty_thrhd().bits()),
-            )
-            .field(
-                "dis_rx_dat_ovf",
-                &format_args!("{}", self.dis_rx_dat_ovf().bit()),
-            )
-            .field(
-                "rx_tout_flow_dis",
-                &format_args!("{}", self.rx_tout_flow_dis().bit()),
-            )
-            .field("rx_flow_en", &format_args!("{}", self.rx_flow_en().bit()))
-            .field("rx_tout_en", &format_args!("{}", self.rx_tout_en().bit()))
+            .field("rxfifo_full_thrhd", &self.rxfifo_full_thrhd())
+            .field("txfifo_empty_thrhd", &self.txfifo_empty_thrhd())
+            .field("dis_rx_dat_ovf", &self.dis_rx_dat_ovf())
+            .field("rx_tout_flow_dis", &self.rx_tout_flow_dis())
+            .field("rx_flow_en", &self.rx_flow_en())
+            .field("rx_tout_en", &self.rx_tout_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/date.rs b/esp32c3/src/uart0/date.rs
index 816469bbff..ac4c156a82 100644
--- a/esp32c3/src/uart0/date.rs
+++ b/esp32c3/src/uart0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/uart0/fifo.rs b/esp32c3/src/uart0/fifo.rs
index 3ea719e7ab..fdc9ee6700 100644
--- a/esp32c3/src/uart0/fifo.rs
+++ b/esp32c3/src/uart0/fifo.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO")
-            .field(
-                "rxfifo_rd_byte",
-                &format_args!("{}", self.rxfifo_rd_byte().bits()),
-            )
+            .field("rxfifo_rd_byte", &self.rxfifo_rd_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - UART 0 accesses FIFO via this register."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/flow_conf.rs b/esp32c3/src/uart0/flow_conf.rs
index f20cf9572e..215821f1b6 100644
--- a/esp32c3/src/uart0/flow_conf.rs
+++ b/esp32c3/src/uart0/flow_conf.rs
@@ -62,24 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLOW_CONF")
-            .field(
-                "sw_flow_con_en",
-                &format_args!("{}", self.sw_flow_con_en().bit()),
-            )
-            .field("xonoff_del", &format_args!("{}", self.xonoff_del().bit()))
-            .field("force_xon", &format_args!("{}", self.force_xon().bit()))
-            .field("force_xoff", &format_args!("{}", self.force_xoff().bit()))
-            .field("send_xon", &format_args!("{}", self.send_xon().bit()))
-            .field("send_xoff", &format_args!("{}", self.send_xoff().bit()))
+            .field("sw_flow_con_en", &self.sw_flow_con_en())
+            .field("xonoff_del", &self.xonoff_del())
+            .field("force_xon", &self.force_xon())
+            .field("force_xoff", &self.force_xoff())
+            .field("send_xon", &self.send_xon())
+            .field("send_xoff", &self.send_xoff())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLOW_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/fsm_status.rs b/esp32c3/src/uart0/fsm_status.rs
index 7e47b06bf6..4088ac153f 100644
--- a/esp32c3/src/uart0/fsm_status.rs
+++ b/esp32c3/src/uart0/fsm_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_STATUS")
-            .field("st_urx_out", &format_args!("{}", self.st_urx_out().bits()))
-            .field("st_utx_out", &format_args!("{}", self.st_utx_out().bits()))
+            .field("st_urx_out", &self.st_urx_out())
+            .field("st_utx_out", &self.st_utx_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART transmit and receive status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FSM_STATUS_SPEC;
 impl crate::RegisterSpec for FSM_STATUS_SPEC {
diff --git a/esp32c3/src/uart0/highpulse.rs b/esp32c3/src/uart0/highpulse.rs
index 2a100f783a..8445906dbf 100644
--- a/esp32c3/src/uart0/highpulse.rs
+++ b/esp32c3/src/uart0/highpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIGHPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIGHPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud minimum high pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`highpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIGHPULSE_SPEC;
 impl crate::RegisterSpec for HIGHPULSE_SPEC {
diff --git a/esp32c3/src/uart0/id.rs b/esp32c3/src/uart0/id.rs
index a379a1b045..d398acf67f 100644
--- a/esp32c3/src/uart0/id.rs
+++ b/esp32c3/src/uart0/id.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ID")
-            .field("id", &format_args!("{}", self.id().bits()))
-            .field("high_speed", &format_args!("{}", self.high_speed().bit()))
-            .field("reg_update", &format_args!("{}", self.reg_update().bit()))
+            .field("id", &self.id())
+            .field("high_speed", &self.high_speed())
+            .field("reg_update", &self.reg_update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - This register is used to configure the uart_id."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/idle_conf.rs b/esp32c3/src/uart0/idle_conf.rs
index bc986732bf..a2f200e19e 100644
--- a/esp32c3/src/uart0/idle_conf.rs
+++ b/esp32c3/src/uart0/idle_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDLE_CONF")
-            .field(
-                "rx_idle_thrhd",
-                &format_args!("{}", self.rx_idle_thrhd().bits()),
-            )
-            .field(
-                "tx_idle_num",
-                &format_args!("{}", self.tx_idle_num().bits()),
-            )
+            .field("rx_idle_thrhd", &self.rx_idle_thrhd())
+            .field("tx_idle_num", &self.tx_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/int_ena.rs b/esp32c3/src/uart0/int_ena.rs
index fea57f25bd..3a8a9f2f95 100644
--- a/esp32c3/src/uart0/int_ena.rs
+++ b/esp32c3/src/uart0/int_ena.rs
@@ -188,50 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/int_raw.rs b/esp32c3/src/uart0/int_raw.rs
index 525414943b..5a2e80fea2 100644
--- a/esp32c3/src/uart0/int_raw.rs
+++ b/esp32c3/src/uart0/int_raw.rs
@@ -188,50 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/int_st.rs b/esp32c3/src/uart0/int_st.rs
index 417bc433a0..c67c7f4b75 100644
--- a/esp32c3/src/uart0/int_st.rs
+++ b/esp32c3/src/uart0/int_st.rs
@@ -146,50 +146,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c3/src/uart0/lowpulse.rs b/esp32c3/src/uart0/lowpulse.rs
index 6736272863..03a2b35c08 100644
--- a/esp32c3/src/uart0/lowpulse.rs
+++ b/esp32c3/src/uart0/lowpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOWPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOWPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud minimum low pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lowpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOWPULSE_SPEC;
 impl crate::RegisterSpec for LOWPULSE_SPEC {
diff --git a/esp32c3/src/uart0/mem_conf.rs b/esp32c3/src/uart0/mem_conf.rs
index 3406996321..95fd5904d1 100644
--- a/esp32c3/src/uart0/mem_conf.rs
+++ b/esp32c3/src/uart0/mem_conf.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field("rx_size", &format_args!("{}", self.rx_size().bits()))
-            .field("tx_size", &format_args!("{}", self.tx_size().bits()))
-            .field(
-                "rx_flow_thrhd",
-                &format_args!("{}", self.rx_flow_thrhd().bits()),
-            )
-            .field(
-                "rx_tout_thrhd",
-                &format_args!("{}", self.rx_tout_thrhd().bits()),
-            )
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
+            .field("rx_size", &self.rx_size())
+            .field("tx_size", &self.tx_size())
+            .field("rx_flow_thrhd", &self.rx_flow_thrhd())
+            .field("rx_tout_thrhd", &self.rx_tout_thrhd())
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 1:3 - This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/mem_rx_status.rs b/esp32c3/src/uart0/mem_rx_status.rs
index 00b4094b66..7820e80b36 100644
--- a/esp32c3/src/uart0/mem_rx_status.rs
+++ b/esp32c3/src/uart0/mem_rx_status.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_RX_STATUS")
-            .field(
-                "apb_rx_raddr",
-                &format_args!("{}", self.apb_rx_raddr().bits()),
-            )
-            .field("rx_waddr", &format_args!("{}", self.rx_waddr().bits()))
+            .field("apb_rx_raddr", &self.apb_rx_raddr())
+            .field("rx_waddr", &self.rx_waddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Rx-FIFO write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_RX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_RX_STATUS_SPEC {
diff --git a/esp32c3/src/uart0/mem_tx_status.rs b/esp32c3/src/uart0/mem_tx_status.rs
index cacd384e62..9ddad52610 100644
--- a/esp32c3/src/uart0/mem_tx_status.rs
+++ b/esp32c3/src/uart0/mem_tx_status.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_TX_STATUS")
-            .field(
-                "apb_tx_waddr",
-                &format_args!("{}", self.apb_tx_waddr().bits()),
-            )
-            .field("tx_raddr", &format_args!("{}", self.tx_raddr().bits()))
+            .field("apb_tx_waddr", &self.apb_tx_waddr())
+            .field("tx_raddr", &self.tx_raddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Tx-FIFO write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_TX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_TX_STATUS_SPEC {
diff --git a/esp32c3/src/uart0/negpulse.rs b/esp32c3/src/uart0/negpulse.rs
index 0daf3b983f..d033b00895 100644
--- a/esp32c3/src/uart0/negpulse.rs
+++ b/esp32c3/src/uart0/negpulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NEGPULSE")
-            .field(
-                "negedge_min_cnt",
-                &format_args!("{}", self.negedge_min_cnt().bits()),
-            )
+            .field("negedge_min_cnt", &self.negedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NEGPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud low pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`negpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NEGPULSE_SPEC;
 impl crate::RegisterSpec for NEGPULSE_SPEC {
diff --git a/esp32c3/src/uart0/pospulse.rs b/esp32c3/src/uart0/pospulse.rs
index 67a98ae05f..acf540a226 100644
--- a/esp32c3/src/uart0/pospulse.rs
+++ b/esp32c3/src/uart0/pospulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POSPULSE")
-            .field(
-                "posedge_min_cnt",
-                &format_args!("{}", self.posedge_min_cnt().bits()),
-            )
+            .field("posedge_min_cnt", &self.posedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POSPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud high pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pospulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct POSPULSE_SPEC;
 impl crate::RegisterSpec for POSPULSE_SPEC {
diff --git a/esp32c3/src/uart0/rs485_conf.rs b/esp32c3/src/uart0/rs485_conf.rs
index 5480b03198..dbf27d91ba 100644
--- a/esp32c3/src/uart0/rs485_conf.rs
+++ b/esp32c3/src/uart0/rs485_conf.rs
@@ -71,34 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RS485_CONF")
-            .field("rs485_en", &format_args!("{}", self.rs485_en().bit()))
-            .field("dl0_en", &format_args!("{}", self.dl0_en().bit()))
-            .field("dl1_en", &format_args!("{}", self.dl1_en().bit()))
-            .field(
-                "rs485tx_rx_en",
-                &format_args!("{}", self.rs485tx_rx_en().bit()),
-            )
-            .field(
-                "rs485rxby_tx_en",
-                &format_args!("{}", self.rs485rxby_tx_en().bit()),
-            )
-            .field(
-                "rs485_rx_dly_num",
-                &format_args!("{}", self.rs485_rx_dly_num().bit()),
-            )
-            .field(
-                "rs485_tx_dly_num",
-                &format_args!("{}", self.rs485_tx_dly_num().bits()),
-            )
+            .field("rs485_en", &self.rs485_en())
+            .field("dl0_en", &self.dl0_en())
+            .field("dl1_en", &self.dl1_en())
+            .field("rs485tx_rx_en", &self.rs485tx_rx_en())
+            .field("rs485rxby_tx_en", &self.rs485rxby_tx_en())
+            .field("rs485_rx_dly_num", &self.rs485_rx_dly_num())
+            .field("rs485_tx_dly_num", &self.rs485_tx_dly_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RS485_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to choose the rs485 mode."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/rx_filt.rs b/esp32c3/src/uart0/rx_filt.rs
index 8b59a9e77a..c19d58140c 100644
--- a/esp32c3/src/uart0/rx_filt.rs
+++ b/esp32c3/src/uart0/rx_filt.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_FILT")
-            .field(
-                "glitch_filt",
-                &format_args!("{}", self.glitch_filt().bits()),
-            )
-            .field(
-                "glitch_filt_en",
-                &format_args!("{}", self.glitch_filt_en().bit()),
-            )
+            .field("glitch_filt", &self.glitch_filt())
+            .field("glitch_filt_en", &self.glitch_filt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_FILT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - when input pulse width is lower than this value, the pulse is ignored."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/rxd_cnt.rs b/esp32c3/src/uart0/rxd_cnt.rs
index f08d5e0323..c3c3052a66 100644
--- a/esp32c3/src/uart0/rxd_cnt.rs
+++ b/esp32c3/src/uart0/rxd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXD_CNT")
-            .field(
-                "rxd_edge_cnt",
-                &format_args!("{}", self.rxd_edge_cnt().bits()),
-            )
+            .field("rxd_edge_cnt", &self.rxd_edge_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud edge change count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXD_CNT_SPEC;
 impl crate::RegisterSpec for RXD_CNT_SPEC {
diff --git a/esp32c3/src/uart0/sleep_conf.rs b/esp32c3/src/uart0/sleep_conf.rs
index 1715cd71a2..bfe6d45eb0 100644
--- a/esp32c3/src/uart0/sleep_conf.rs
+++ b/esp32c3/src/uart0/sleep_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF")
-            .field(
-                "active_threshold",
-                &format_args!("{}", self.active_threshold().bits()),
-            )
+            .field("active_threshold", &self.active_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/status.rs b/esp32c3/src/uart0/status.rs
index 4e1eee73c3..43e7f84e00 100644
--- a/esp32c3/src/uart0/status.rs
+++ b/esp32c3/src/uart0/status.rs
@@ -62,23 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("dsrn", &format_args!("{}", self.dsrn().bit()))
-            .field("ctsn", &format_args!("{}", self.ctsn().bit()))
-            .field("rxd", &format_args!("{}", self.rxd().bit()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field("dtrn", &format_args!("{}", self.dtrn().bit()))
-            .field("rtsn", &format_args!("{}", self.rtsn().bit()))
-            .field("txd", &format_args!("{}", self.txd().bit()))
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("dsrn", &self.dsrn())
+            .field("ctsn", &self.ctsn())
+            .field("rxd", &self.rxd())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("dtrn", &self.dtrn())
+            .field("rtsn", &self.rtsn())
+            .field("txd", &self.txd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32c3/src/uart0/swfc_conf0.rs b/esp32c3/src/uart0/swfc_conf0.rs
index 30f5c56ba0..448e91c539 100644
--- a/esp32c3/src/uart0/swfc_conf0.rs
+++ b/esp32c3/src/uart0/swfc_conf0.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF0")
-            .field(
-                "xoff_threshold",
-                &format_args!("{}", self.xoff_threshold().bits()),
-            )
-            .field("xoff_char", &format_args!("{}", self.xoff_char().bits()))
+            .field("xoff_threshold", &self.xoff_threshold())
+            .field("xoff_char", &self.xoff_char())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/swfc_conf1.rs b/esp32c3/src/uart0/swfc_conf1.rs
index 0a328df376..5dd689e5b0 100644
--- a/esp32c3/src/uart0/swfc_conf1.rs
+++ b/esp32c3/src/uart0/swfc_conf1.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF1")
-            .field(
-                "xon_threshold",
-                &format_args!("{}", self.xon_threshold().bits()),
-            )
-            .field("xon_char", &format_args!("{}", self.xon_char().bits()))
+            .field("xon_threshold", &self.xon_threshold())
+            .field("xon_char", &self.xon_char())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char."]
     #[inline(always)]
diff --git a/esp32c3/src/uart0/txbrk_conf.rs b/esp32c3/src/uart0/txbrk_conf.rs
index bfa2a9b911..65d37271c2 100644
--- a/esp32c3/src/uart0/txbrk_conf.rs
+++ b/esp32c3/src/uart0/txbrk_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXBRK_CONF")
-            .field("tx_brk_num", &format_args!("{}", self.tx_brk_num().bits()))
+            .field("tx_brk_num", &self.tx_brk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXBRK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."]
     #[inline(always)]
diff --git a/esp32c3/src/uhci0/ack_num.rs b/esp32c3/src/uhci0/ack_num.rs
index c9fa123df1..2a53afbf38 100644
--- a/esp32c3/src/uhci0/ack_num.rs
+++ b/esp32c3/src/uhci0/ack_num.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ACK_NUM")
-            .field("ack_num", &format_args!("{}", self.ack_num().bits()))
+            .field("ack_num", &self.ack_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ACK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - a"]
     #[inline(always)]
diff --git a/esp32c3/src/uhci0/conf0.rs b/esp32c3/src/uhci0/conf0.rs
index 39e3fbc5d7..25c6e281e3 100644
--- a/esp32c3/src/uhci0/conf0.rs
+++ b/esp32c3/src/uhci0/conf0.rs
@@ -116,36 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("tx_rst", &format_args!("{}", self.tx_rst().bit()))
-            .field("rx_rst", &format_args!("{}", self.rx_rst().bit()))
-            .field("uart0_ce", &format_args!("{}", self.uart0_ce().bit()))
-            .field("uart1_ce", &format_args!("{}", self.uart1_ce().bit()))
-            .field("seper_en", &format_args!("{}", self.seper_en().bit()))
-            .field("head_en", &format_args!("{}", self.head_en().bit()))
-            .field("crc_rec_en", &format_args!("{}", self.crc_rec_en().bit()))
-            .field(
-                "uart_idle_eof_en",
-                &format_args!("{}", self.uart_idle_eof_en().bit()),
-            )
-            .field("len_eof_en", &format_args!("{}", self.len_eof_en().bit()))
-            .field(
-                "encode_crc_en",
-                &format_args!("{}", self.encode_crc_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "uart_rx_brk_eof_en",
-                &format_args!("{}", self.uart_rx_brk_eof_en().bit()),
-            )
+            .field("tx_rst", &self.tx_rst())
+            .field("rx_rst", &self.rx_rst())
+            .field("uart0_ce", &self.uart0_ce())
+            .field("uart1_ce", &self.uart1_ce())
+            .field("seper_en", &self.seper_en())
+            .field("head_en", &self.head_en())
+            .field("crc_rec_en", &self.crc_rec_en())
+            .field("uart_idle_eof_en", &self.uart_idle_eof_en())
+            .field("len_eof_en", &self.len_eof_en())
+            .field("encode_crc_en", &self.encode_crc_en())
+            .field("clk_en", &self.clk_en())
+            .field("uart_rx_brk_eof_en", &self.uart_rx_brk_eof_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1, then write 0 to this bit to reset decode state machine."]
     #[inline(always)]
diff --git a/esp32c3/src/uhci0/conf1.rs b/esp32c3/src/uhci0/conf1.rs
index 0a4e2098e9..104c0b0488 100644
--- a/esp32c3/src/uhci0/conf1.rs
+++ b/esp32c3/src/uhci0/conf1.rs
@@ -80,38 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "check_sum_en",
-                &format_args!("{}", self.check_sum_en().bit()),
-            )
-            .field(
-                "check_seq_en",
-                &format_args!("{}", self.check_seq_en().bit()),
-            )
-            .field("crc_disable", &format_args!("{}", self.crc_disable().bit()))
-            .field("save_head", &format_args!("{}", self.save_head().bit()))
-            .field(
-                "tx_check_sum_re",
-                &format_args!("{}", self.tx_check_sum_re().bit()),
-            )
-            .field(
-                "tx_ack_num_re",
-                &format_args!("{}", self.tx_ack_num_re().bit()),
-            )
-            .field(
-                "wait_sw_start",
-                &format_args!("{}", self.wait_sw_start().bit()),
-            )
-            .field("sw_start", &format_args!("{}", self.sw_start().bit()))
+            .field("check_sum_en", &self.check_sum_en())
+            .field("check_seq_en", &self.check_seq_en())
+            .field("crc_disable", &self.crc_disable())
+            .field("save_head", &self.save_head())
+            .field("tx_check_sum_re", &self.tx_check_sum_re())
+            .field("tx_ack_num_re", &self.tx_ack_num_re())
+            .field("wait_sw_start", &self.wait_sw_start())
+            .field("sw_start", &self.sw_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - a"]
     #[inline(always)]
diff --git a/esp32c3/src/uhci0/date.rs b/esp32c3/src/uhci0/date.rs
index 9777dab9ff..c2778d521e 100644
--- a/esp32c3/src/uhci0/date.rs
+++ b/esp32c3/src/uhci0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/uhci0/esc_conf.rs b/esp32c3/src/uhci0/esc_conf.rs
index ace9fbdb12..e2470a3ff5 100644
--- a/esp32c3/src/uhci0/esc_conf.rs
+++ b/esp32c3/src/uhci0/esc_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ESC_CONF")
-            .field("seper_char", &format_args!("{}", self.seper_char().bits()))
-            .field(
-                "seper_esc_char0",
-                &format_args!("{}", self.seper_esc_char0().bits()),
-            )
-            .field(
-                "seper_esc_char1",
-                &format_args!("{}", self.seper_esc_char1().bits()),
-            )
+            .field("seper_char", &self.seper_char())
+            .field("seper_esc_char0", &self.seper_esc_char0())
+            .field("seper_esc_char1", &self.seper_esc_char1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ESC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - a"]
     #[inline(always)]
diff --git a/esp32c3/src/uhci0/escape_conf.rs b/esp32c3/src/uhci0/escape_conf.rs
index d6ab085002..54d7bbfa84 100644
--- a/esp32c3/src/uhci0/escape_conf.rs
+++ b/esp32c3/src/uhci0/escape_conf.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ESCAPE_CONF")
-            .field(
-                "tx_c0_esc_en",
-                &format_args!("{}", self.tx_c0_esc_en().bit()),
-            )
-            .field(
-                "tx_db_esc_en",
-                &format_args!("{}", self.tx_db_esc_en().bit()),
-            )
-            .field(
-                "tx_11_esc_en",
-                &format_args!("{}", self.tx_11_esc_en().bit()),
-            )
-            .field(
-                "tx_13_esc_en",
-                &format_args!("{}", self.tx_13_esc_en().bit()),
-            )
-            .field(
-                "rx_c0_esc_en",
-                &format_args!("{}", self.rx_c0_esc_en().bit()),
-            )
-            .field(
-                "rx_db_esc_en",
-                &format_args!("{}", self.rx_db_esc_en().bit()),
-            )
-            .field(
-                "rx_11_esc_en",
-                &format_args!("{}", self.rx_11_esc_en().bit()),
-            )
-            .field(
-                "rx_13_esc_en",
-                &format_args!("{}", self.rx_13_esc_en().bit()),
-            )
+            .field("tx_c0_esc_en", &self.tx_c0_esc_en())
+            .field("tx_db_esc_en", &self.tx_db_esc_en())
+            .field("tx_11_esc_en", &self.tx_11_esc_en())
+            .field("tx_13_esc_en", &self.tx_13_esc_en())
+            .field("rx_c0_esc_en", &self.rx_c0_esc_en())
+            .field("rx_db_esc_en", &self.rx_db_esc_en())
+            .field("rx_11_esc_en", &self.rx_11_esc_en())
+            .field("rx_13_esc_en", &self.rx_13_esc_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ESCAPE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - a"]
     #[inline(always)]
diff --git a/esp32c3/src/uhci0/hung_conf.rs b/esp32c3/src/uhci0/hung_conf.rs
index a6afa4092c..4ec1687c77 100644
--- a/esp32c3/src/uhci0/hung_conf.rs
+++ b/esp32c3/src/uhci0/hung_conf.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HUNG_CONF")
-            .field(
-                "txfifo_timeout",
-                &format_args!("{}", self.txfifo_timeout().bits()),
-            )
-            .field(
-                "txfifo_timeout_shift",
-                &format_args!("{}", self.txfifo_timeout_shift().bits()),
-            )
-            .field(
-                "txfifo_timeout_ena",
-                &format_args!("{}", self.txfifo_timeout_ena().bit()),
-            )
-            .field(
-                "rxfifo_timeout",
-                &format_args!("{}", self.rxfifo_timeout().bits()),
-            )
-            .field(
-                "rxfifo_timeout_shift",
-                &format_args!("{}", self.rxfifo_timeout_shift().bits()),
-            )
-            .field(
-                "rxfifo_timeout_ena",
-                &format_args!("{}", self.rxfifo_timeout_ena().bit()),
-            )
+            .field("txfifo_timeout", &self.txfifo_timeout())
+            .field("txfifo_timeout_shift", &self.txfifo_timeout_shift())
+            .field("txfifo_timeout_ena", &self.txfifo_timeout_ena())
+            .field("rxfifo_timeout", &self.rxfifo_timeout())
+            .field("rxfifo_timeout_shift", &self.rxfifo_timeout_shift())
+            .field("rxfifo_timeout_ena", &self.rxfifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - a"]
     #[inline(always)]
diff --git a/esp32c3/src/uhci0/int_ena.rs b/esp32c3/src/uhci0/int_ena.rs
index f314b3f22a..6a6be4eb1b 100644
--- a/esp32c3/src/uhci0/int_ena.rs
+++ b/esp32c3/src/uhci0/int_ena.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
-            .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - a"]
     #[inline(always)]
diff --git a/esp32c3/src/uhci0/int_raw.rs b/esp32c3/src/uhci0/int_raw.rs
index 445e2170fd..11e0ddbabe 100644
--- a/esp32c3/src/uhci0/int_raw.rs
+++ b/esp32c3/src/uhci0/int_raw.rs
@@ -89,30 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
-            .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("out_eof", &self.out_eof())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - a"]
     #[inline(always)]
diff --git a/esp32c3/src/uhci0/int_st.rs b/esp32c3/src/uhci0/int_st.rs
index 3aa1520031..6178db3316 100644
--- a/esp32c3/src/uhci0/int_st.rs
+++ b/esp32c3/src/uhci0/int_st.rs
@@ -69,33 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
-            .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c3/src/uhci0/pkt_thres.rs b/esp32c3/src/uhci0/pkt_thres.rs
index 90c99b6cf8..78af77cd0e 100644
--- a/esp32c3/src/uhci0/pkt_thres.rs
+++ b/esp32c3/src/uhci0/pkt_thres.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PKT_THRES")
-            .field("pkt_thrs", &format_args!("{}", self.pkt_thrs().bits()))
+            .field("pkt_thrs", &self.pkt_thrs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PKT_THRES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - a"]
     #[inline(always)]
diff --git a/esp32c3/src/uhci0/quick_sent.rs b/esp32c3/src/uhci0/quick_sent.rs
index 23abedc729..a3ac7738a4 100644
--- a/esp32c3/src/uhci0/quick_sent.rs
+++ b/esp32c3/src/uhci0/quick_sent.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUICK_SENT")
-            .field(
-                "single_send_num",
-                &format_args!("{}", self.single_send_num().bits()),
-            )
-            .field(
-                "single_send_en",
-                &format_args!("{}", self.single_send_en().bit()),
-            )
-            .field(
-                "always_send_num",
-                &format_args!("{}", self.always_send_num().bits()),
-            )
-            .field(
-                "always_send_en",
-                &format_args!("{}", self.always_send_en().bit()),
-            )
+            .field("single_send_num", &self.single_send_num())
+            .field("single_send_en", &self.single_send_en())
+            .field("always_send_num", &self.always_send_num())
+            .field("always_send_en", &self.always_send_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUICK_SENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - a"]
     #[inline(always)]
diff --git a/esp32c3/src/uhci0/reg_q/word0.rs b/esp32c3/src/uhci0/reg_q/word0.rs
index 19e9e832f7..ee667218e9 100644
--- a/esp32c3/src/uhci0/reg_q/word0.rs
+++ b/esp32c3/src/uhci0/reg_q/word0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WORD0")
-            .field("send_word", &format_args!("{}", self.send_word().bits()))
+            .field("send_word", &self.send_word())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WORD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - a"]
     #[inline(always)]
diff --git a/esp32c3/src/uhci0/reg_q/word1.rs b/esp32c3/src/uhci0/reg_q/word1.rs
index 8a0df345ba..e300953f09 100644
--- a/esp32c3/src/uhci0/reg_q/word1.rs
+++ b/esp32c3/src/uhci0/reg_q/word1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WORD1")
-            .field("send_word", &format_args!("{}", self.send_word().bits()))
+            .field("send_word", &self.send_word())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WORD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - a"]
     #[inline(always)]
diff --git a/esp32c3/src/uhci0/rx_head.rs b/esp32c3/src/uhci0/rx_head.rs
index 5381387bf9..a0180e5bcc 100644
--- a/esp32c3/src/uhci0/rx_head.rs
+++ b/esp32c3/src/uhci0/rx_head.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_HEAD")
-            .field("rx_head", &format_args!("{}", self.rx_head().bits()))
+            .field("rx_head", &self.rx_head())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_HEAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_head::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_HEAD_SPEC;
 impl crate::RegisterSpec for RX_HEAD_SPEC {
diff --git a/esp32c3/src/uhci0/state0.rs b/esp32c3/src/uhci0/state0.rs
index 0f5fd94f00..6ee8f8c9f1 100644
--- a/esp32c3/src/uhci0/state0.rs
+++ b/esp32c3/src/uhci0/state0.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE0")
-            .field(
-                "rx_err_cause",
-                &format_args!("{}", self.rx_err_cause().bits()),
-            )
-            .field(
-                "decode_state",
-                &format_args!("{}", self.decode_state().bits()),
-            )
+            .field("rx_err_cause", &self.rx_err_cause())
+            .field("decode_state", &self.decode_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE0_SPEC;
 impl crate::RegisterSpec for STATE0_SPEC {
diff --git a/esp32c3/src/uhci0/state1.rs b/esp32c3/src/uhci0/state1.rs
index a33d5b362e..bde625ed00 100644
--- a/esp32c3/src/uhci0/state1.rs
+++ b/esp32c3/src/uhci0/state1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE1")
-            .field(
-                "encode_state",
-                &format_args!("{}", self.encode_state().bits()),
-            )
+            .field("encode_state", &self.encode_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE1_SPEC;
 impl crate::RegisterSpec for STATE1_SPEC {
diff --git a/esp32c3/src/usb_device/conf0.rs b/esp32c3/src/usb_device/conf0.rs
index 9b9ca5ca5d..6ee13180ef 100644
--- a/esp32c3/src/usb_device/conf0.rs
+++ b/esp32c3/src/usb_device/conf0.rs
@@ -125,43 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("phy_sel", &format_args!("{}", self.phy_sel().bit()))
-            .field(
-                "exchg_pins_override",
-                &format_args!("{}", self.exchg_pins_override().bit()),
-            )
-            .field("exchg_pins", &format_args!("{}", self.exchg_pins().bit()))
-            .field("vrefh", &format_args!("{}", self.vrefh().bits()))
-            .field("vrefl", &format_args!("{}", self.vrefl().bits()))
-            .field(
-                "vref_override",
-                &format_args!("{}", self.vref_override().bit()),
-            )
-            .field(
-                "pad_pull_override",
-                &format_args!("{}", self.pad_pull_override().bit()),
-            )
-            .field("dp_pullup", &format_args!("{}", self.dp_pullup().bit()))
-            .field("dp_pulldown", &format_args!("{}", self.dp_pulldown().bit()))
-            .field("dm_pullup", &format_args!("{}", self.dm_pullup().bit()))
-            .field("dm_pulldown", &format_args!("{}", self.dm_pulldown().bit()))
-            .field(
-                "pullup_value",
-                &format_args!("{}", self.pullup_value().bit()),
-            )
-            .field(
-                "usb_pad_enable",
-                &format_args!("{}", self.usb_pad_enable().bit()),
-            )
+            .field("phy_sel", &self.phy_sel())
+            .field("exchg_pins_override", &self.exchg_pins_override())
+            .field("exchg_pins", &self.exchg_pins())
+            .field("vrefh", &self.vrefh())
+            .field("vrefl", &self.vrefl())
+            .field("vref_override", &self.vref_override())
+            .field("pad_pull_override", &self.pad_pull_override())
+            .field("dp_pullup", &self.dp_pullup())
+            .field("dp_pulldown", &self.dp_pulldown())
+            .field("dm_pullup", &self.dm_pullup())
+            .field("dm_pulldown", &self.dm_pulldown())
+            .field("pullup_value", &self.pullup_value())
+            .field("usb_pad_enable", &self.usb_pad_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Select internal/external PHY"]
     #[inline(always)]
diff --git a/esp32c3/src/usb_device/date.rs b/esp32c3/src/usb_device/date.rs
index 4d8fd2e2a4..24be6c7c7a 100644
--- a/esp32c3/src/usb_device/date.rs
+++ b/esp32c3/src/usb_device/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/usb_device/ep1.rs b/esp32c3/src/usb_device/ep1.rs
index 83d2a227c4..2403db71e6 100644
--- a/esp32c3/src/usb_device/ep1.rs
+++ b/esp32c3/src/usb_device/ep1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EP1")
-            .field("rdwr_byte", &format_args!("{}", self.rdwr_byte().bits()))
+            .field("rdwr_byte", &self.rdwr_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO."]
     #[inline(always)]
diff --git a/esp32c3/src/usb_device/ep1_conf.rs b/esp32c3/src/usb_device/ep1_conf.rs
index b21136957a..ec0fcbc7e6 100644
--- a/esp32c3/src/usb_device/ep1_conf.rs
+++ b/esp32c3/src/usb_device/ep1_conf.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EP1_CONF")
-            .field(
-                "serial_in_ep_data_free",
-                &format_args!("{}", self.serial_in_ep_data_free().bit()),
-            )
-            .field(
-                "serial_out_ep_data_avail",
-                &format_args!("{}", self.serial_out_ep_data_avail().bit()),
-            )
+            .field("serial_in_ep_data_free", &self.serial_in_ep_data_free())
+            .field("serial_out_ep_data_avail", &self.serial_out_ep_data_avail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EP1_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to indicate writing byte data to UART Tx FIFO is done."]
     #[inline(always)]
diff --git a/esp32c3/src/usb_device/fram_num.rs b/esp32c3/src/usb_device/fram_num.rs
index a25717f95d..dab7b6f72a 100644
--- a/esp32c3/src/usb_device/fram_num.rs
+++ b/esp32c3/src/usb_device/fram_num.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FRAM_NUM")
-            .field(
-                "sof_frame_index",
-                &format_args!("{}", self.sof_frame_index().bits()),
-            )
+            .field("sof_frame_index", &self.sof_frame_index())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FRAM_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USB_DEVICE_FRAM_NUM_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fram_num::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FRAM_NUM_SPEC;
 impl crate::RegisterSpec for FRAM_NUM_SPEC {
diff --git a/esp32c3/src/usb_device/in_ep0_st.rs b/esp32c3/src/usb_device/in_ep0_st.rs
index df61ca2749..21454351f6 100644
--- a/esp32c3/src/usb_device/in_ep0_st.rs
+++ b/esp32c3/src/usb_device/in_ep0_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP0_ST")
-            .field(
-                "in_ep0_state",
-                &format_args!("{}", self.in_ep0_state().bits()),
-            )
-            .field(
-                "in_ep0_wr_addr",
-                &format_args!("{}", self.in_ep0_wr_addr().bits()),
-            )
-            .field(
-                "in_ep0_rd_addr",
-                &format_args!("{}", self.in_ep0_rd_addr().bits()),
-            )
+            .field("in_ep0_state", &self.in_ep0_state())
+            .field("in_ep0_wr_addr", &self.in_ep0_wr_addr())
+            .field("in_ep0_rd_addr", &self.in_ep0_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP0_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USB_DEVICE_IN_EP0_ST_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep0_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP0_ST_SPEC;
 impl crate::RegisterSpec for IN_EP0_ST_SPEC {
diff --git a/esp32c3/src/usb_device/in_ep1_st.rs b/esp32c3/src/usb_device/in_ep1_st.rs
index 2cc6b31663..f2f608ebe1 100644
--- a/esp32c3/src/usb_device/in_ep1_st.rs
+++ b/esp32c3/src/usb_device/in_ep1_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP1_ST")
-            .field(
-                "in_ep1_state",
-                &format_args!("{}", self.in_ep1_state().bits()),
-            )
-            .field(
-                "in_ep1_wr_addr",
-                &format_args!("{}", self.in_ep1_wr_addr().bits()),
-            )
-            .field(
-                "in_ep1_rd_addr",
-                &format_args!("{}", self.in_ep1_rd_addr().bits()),
-            )
+            .field("in_ep1_state", &self.in_ep1_state())
+            .field("in_ep1_wr_addr", &self.in_ep1_wr_addr())
+            .field("in_ep1_rd_addr", &self.in_ep1_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP1_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USB_DEVICE_IN_EP1_ST_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep1_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP1_ST_SPEC;
 impl crate::RegisterSpec for IN_EP1_ST_SPEC {
diff --git a/esp32c3/src/usb_device/in_ep2_st.rs b/esp32c3/src/usb_device/in_ep2_st.rs
index 0207864633..8b62d4a157 100644
--- a/esp32c3/src/usb_device/in_ep2_st.rs
+++ b/esp32c3/src/usb_device/in_ep2_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP2_ST")
-            .field(
-                "in_ep2_state",
-                &format_args!("{}", self.in_ep2_state().bits()),
-            )
-            .field(
-                "in_ep2_wr_addr",
-                &format_args!("{}", self.in_ep2_wr_addr().bits()),
-            )
-            .field(
-                "in_ep2_rd_addr",
-                &format_args!("{}", self.in_ep2_rd_addr().bits()),
-            )
+            .field("in_ep2_state", &self.in_ep2_state())
+            .field("in_ep2_wr_addr", &self.in_ep2_wr_addr())
+            .field("in_ep2_rd_addr", &self.in_ep2_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP2_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USB_DEVICE_IN_EP2_ST_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep2_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP2_ST_SPEC;
 impl crate::RegisterSpec for IN_EP2_ST_SPEC {
diff --git a/esp32c3/src/usb_device/in_ep3_st.rs b/esp32c3/src/usb_device/in_ep3_st.rs
index 6a8c369182..d1da85859a 100644
--- a/esp32c3/src/usb_device/in_ep3_st.rs
+++ b/esp32c3/src/usb_device/in_ep3_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP3_ST")
-            .field(
-                "in_ep3_state",
-                &format_args!("{}", self.in_ep3_state().bits()),
-            )
-            .field(
-                "in_ep3_wr_addr",
-                &format_args!("{}", self.in_ep3_wr_addr().bits()),
-            )
-            .field(
-                "in_ep3_rd_addr",
-                &format_args!("{}", self.in_ep3_rd_addr().bits()),
-            )
+            .field("in_ep3_state", &self.in_ep3_state())
+            .field("in_ep3_wr_addr", &self.in_ep3_wr_addr())
+            .field("in_ep3_rd_addr", &self.in_ep3_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP3_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USB_DEVICE_IN_EP3_ST_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep3_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP3_ST_SPEC;
 impl crate::RegisterSpec for IN_EP3_ST_SPEC {
diff --git a/esp32c3/src/usb_device/int_ena.rs b/esp32c3/src/usb_device/int_ena.rs
index e7e5d54ea7..ee4dd0e486 100644
--- a/esp32c3/src/usb_device/int_ena.rs
+++ b/esp32c3/src/usb_device/int_ena.rs
@@ -116,48 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "jtag_in_flush",
-                &format_args!("{}", self.jtag_in_flush().bit()),
-            )
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field(
-                "serial_out_recv_pkt",
-                &format_args!("{}", self.serial_out_recv_pkt().bit()),
-            )
-            .field(
-                "serial_in_empty",
-                &format_args!("{}", self.serial_in_empty().bit()),
-            )
-            .field("pid_err", &format_args!("{}", self.pid_err().bit()))
-            .field("crc5_err", &format_args!("{}", self.crc5_err().bit()))
-            .field("crc16_err", &format_args!("{}", self.crc16_err().bit()))
-            .field("stuff_err", &format_args!("{}", self.stuff_err().bit()))
-            .field(
-                "in_token_rec_in_ep1",
-                &format_args!("{}", self.in_token_rec_in_ep1().bit()),
-            )
-            .field(
-                "usb_bus_reset",
-                &format_args!("{}", self.usb_bus_reset().bit()),
-            )
-            .field(
-                "out_ep1_zero_payload",
-                &format_args!("{}", self.out_ep1_zero_payload().bit()),
-            )
-            .field(
-                "out_ep2_zero_payload",
-                &format_args!("{}", self.out_ep2_zero_payload().bit()),
-            )
+            .field("jtag_in_flush", &self.jtag_in_flush())
+            .field("sof", &self.sof())
+            .field("serial_out_recv_pkt", &self.serial_out_recv_pkt())
+            .field("serial_in_empty", &self.serial_in_empty())
+            .field("pid_err", &self.pid_err())
+            .field("crc5_err", &self.crc5_err())
+            .field("crc16_err", &self.crc16_err())
+            .field("stuff_err", &self.stuff_err())
+            .field("in_token_rec_in_ep1", &self.in_token_rec_in_ep1())
+            .field("usb_bus_reset", &self.usb_bus_reset())
+            .field("out_ep1_zero_payload", &self.out_ep1_zero_payload())
+            .field("out_ep2_zero_payload", &self.out_ep2_zero_payload())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c3/src/usb_device/int_raw.rs b/esp32c3/src/usb_device/int_raw.rs
index df1f06b451..dc9960ce0f 100644
--- a/esp32c3/src/usb_device/int_raw.rs
+++ b/esp32c3/src/usb_device/int_raw.rs
@@ -116,48 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "jtag_in_flush",
-                &format_args!("{}", self.jtag_in_flush().bit()),
-            )
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field(
-                "serial_out_recv_pkt",
-                &format_args!("{}", self.serial_out_recv_pkt().bit()),
-            )
-            .field(
-                "serial_in_empty",
-                &format_args!("{}", self.serial_in_empty().bit()),
-            )
-            .field("pid_err", &format_args!("{}", self.pid_err().bit()))
-            .field("crc5_err", &format_args!("{}", self.crc5_err().bit()))
-            .field("crc16_err", &format_args!("{}", self.crc16_err().bit()))
-            .field("stuff_err", &format_args!("{}", self.stuff_err().bit()))
-            .field(
-                "in_token_rec_in_ep1",
-                &format_args!("{}", self.in_token_rec_in_ep1().bit()),
-            )
-            .field(
-                "usb_bus_reset",
-                &format_args!("{}", self.usb_bus_reset().bit()),
-            )
-            .field(
-                "out_ep1_zero_payload",
-                &format_args!("{}", self.out_ep1_zero_payload().bit()),
-            )
-            .field(
-                "out_ep2_zero_payload",
-                &format_args!("{}", self.out_ep2_zero_payload().bit()),
-            )
+            .field("jtag_in_flush", &self.jtag_in_flush())
+            .field("sof", &self.sof())
+            .field("serial_out_recv_pkt", &self.serial_out_recv_pkt())
+            .field("serial_in_empty", &self.serial_in_empty())
+            .field("pid_err", &self.pid_err())
+            .field("crc5_err", &self.crc5_err())
+            .field("crc16_err", &self.crc16_err())
+            .field("stuff_err", &self.stuff_err())
+            .field("in_token_rec_in_ep1", &self.in_token_rec_in_ep1())
+            .field("usb_bus_reset", &self.usb_bus_reset())
+            .field("out_ep1_zero_payload", &self.out_ep1_zero_payload())
+            .field("out_ep2_zero_payload", &self.out_ep2_zero_payload())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG."]
     #[inline(always)]
diff --git a/esp32c3/src/usb_device/int_st.rs b/esp32c3/src/usb_device/int_st.rs
index 90b62d07db..e82f2c77c6 100644
--- a/esp32c3/src/usb_device/int_st.rs
+++ b/esp32c3/src/usb_device/int_st.rs
@@ -90,48 +90,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "jtag_in_flush",
-                &format_args!("{}", self.jtag_in_flush().bit()),
-            )
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field(
-                "serial_out_recv_pkt",
-                &format_args!("{}", self.serial_out_recv_pkt().bit()),
-            )
-            .field(
-                "serial_in_empty",
-                &format_args!("{}", self.serial_in_empty().bit()),
-            )
-            .field("pid_err", &format_args!("{}", self.pid_err().bit()))
-            .field("crc5_err", &format_args!("{}", self.crc5_err().bit()))
-            .field("crc16_err", &format_args!("{}", self.crc16_err().bit()))
-            .field("stuff_err", &format_args!("{}", self.stuff_err().bit()))
-            .field(
-                "in_token_rec_in_ep1",
-                &format_args!("{}", self.in_token_rec_in_ep1().bit()),
-            )
-            .field(
-                "usb_bus_reset",
-                &format_args!("{}", self.usb_bus_reset().bit()),
-            )
-            .field(
-                "out_ep1_zero_payload",
-                &format_args!("{}", self.out_ep1_zero_payload().bit()),
-            )
-            .field(
-                "out_ep2_zero_payload",
-                &format_args!("{}", self.out_ep2_zero_payload().bit()),
-            )
+            .field("jtag_in_flush", &self.jtag_in_flush())
+            .field("sof", &self.sof())
+            .field("serial_out_recv_pkt", &self.serial_out_recv_pkt())
+            .field("serial_in_empty", &self.serial_in_empty())
+            .field("pid_err", &self.pid_err())
+            .field("crc5_err", &self.crc5_err())
+            .field("crc16_err", &self.crc16_err())
+            .field("stuff_err", &self.stuff_err())
+            .field("in_token_rec_in_ep1", &self.in_token_rec_in_ep1())
+            .field("usb_bus_reset", &self.usb_bus_reset())
+            .field("out_ep1_zero_payload", &self.out_ep1_zero_payload())
+            .field("out_ep2_zero_payload", &self.out_ep2_zero_payload())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USB_DEVICE_INT_ST_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c3/src/usb_device/jfifo_st.rs b/esp32c3/src/usb_device/jfifo_st.rs
index 3199ae8584..22b3f7b540 100644
--- a/esp32c3/src/usb_device/jfifo_st.rs
+++ b/esp32c3/src/usb_device/jfifo_st.rs
@@ -68,47 +68,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("JFIFO_ST")
-            .field(
-                "in_fifo_cnt",
-                &format_args!("{}", self.in_fifo_cnt().bits()),
-            )
-            .field(
-                "in_fifo_empty",
-                &format_args!("{}", self.in_fifo_empty().bit()),
-            )
-            .field(
-                "in_fifo_full",
-                &format_args!("{}", self.in_fifo_full().bit()),
-            )
-            .field(
-                "out_fifo_cnt",
-                &format_args!("{}", self.out_fifo_cnt().bits()),
-            )
-            .field(
-                "out_fifo_empty",
-                &format_args!("{}", self.out_fifo_empty().bit()),
-            )
-            .field(
-                "out_fifo_full",
-                &format_args!("{}", self.out_fifo_full().bit()),
-            )
-            .field(
-                "in_fifo_reset",
-                &format_args!("{}", self.in_fifo_reset().bit()),
-            )
-            .field(
-                "out_fifo_reset",
-                &format_args!("{}", self.out_fifo_reset().bit()),
-            )
+            .field("in_fifo_cnt", &self.in_fifo_cnt())
+            .field("in_fifo_empty", &self.in_fifo_empty())
+            .field("in_fifo_full", &self.in_fifo_full())
+            .field("out_fifo_cnt", &self.out_fifo_cnt())
+            .field("out_fifo_empty", &self.out_fifo_empty())
+            .field("out_fifo_full", &self.out_fifo_full())
+            .field("in_fifo_reset", &self.in_fifo_reset())
+            .field("out_fifo_reset", &self.out_fifo_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<JFIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - Write 1 to reset JTAG in fifo."]
     #[inline(always)]
diff --git a/esp32c3/src/usb_device/mem_conf.rs b/esp32c3/src/usb_device/mem_conf.rs
index f3ba315c88..1ba501c6fe 100644
--- a/esp32c3/src/usb_device/mem_conf.rs
+++ b/esp32c3/src/usb_device/mem_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field("usb_mem_pd", &format_args!("{}", self.usb_mem_pd().bit()))
-            .field(
-                "usb_mem_clk_en",
-                &format_args!("{}", self.usb_mem_clk_en().bit()),
-            )
+            .field("usb_mem_pd", &self.usb_mem_pd())
+            .field("usb_mem_clk_en", &self.usb_mem_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: power down usb memory."]
     #[inline(always)]
diff --git a/esp32c3/src/usb_device/misc_conf.rs b/esp32c3/src/usb_device/misc_conf.rs
index 3dce356d2c..1b761aa1d2 100644
--- a/esp32c3/src/usb_device/misc_conf.rs
+++ b/esp32c3/src/usb_device/misc_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC_CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
     #[inline(always)]
diff --git a/esp32c3/src/usb_device/out_ep0_st.rs b/esp32c3/src/usb_device/out_ep0_st.rs
index ee180e01fb..aee081ad31 100644
--- a/esp32c3/src/usb_device/out_ep0_st.rs
+++ b/esp32c3/src/usb_device/out_ep0_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EP0_ST")
-            .field(
-                "out_ep0_state",
-                &format_args!("{}", self.out_ep0_state().bits()),
-            )
-            .field(
-                "out_ep0_wr_addr",
-                &format_args!("{}", self.out_ep0_wr_addr().bits()),
-            )
-            .field(
-                "out_ep0_rd_addr",
-                &format_args!("{}", self.out_ep0_rd_addr().bits()),
-            )
+            .field("out_ep0_state", &self.out_ep0_state())
+            .field("out_ep0_wr_addr", &self.out_ep0_wr_addr())
+            .field("out_ep0_rd_addr", &self.out_ep0_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EP0_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USB_DEVICE_OUT_EP0_ST_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep0_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EP0_ST_SPEC;
 impl crate::RegisterSpec for OUT_EP0_ST_SPEC {
diff --git a/esp32c3/src/usb_device/out_ep1_st.rs b/esp32c3/src/usb_device/out_ep1_st.rs
index 7e28f332dd..837c93baae 100644
--- a/esp32c3/src/usb_device/out_ep1_st.rs
+++ b/esp32c3/src/usb_device/out_ep1_st.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EP1_ST")
-            .field(
-                "out_ep1_state",
-                &format_args!("{}", self.out_ep1_state().bits()),
-            )
-            .field(
-                "out_ep1_wr_addr",
-                &format_args!("{}", self.out_ep1_wr_addr().bits()),
-            )
-            .field(
-                "out_ep1_rd_addr",
-                &format_args!("{}", self.out_ep1_rd_addr().bits()),
-            )
-            .field(
-                "out_ep1_rec_data_cnt",
-                &format_args!("{}", self.out_ep1_rec_data_cnt().bits()),
-            )
+            .field("out_ep1_state", &self.out_ep1_state())
+            .field("out_ep1_wr_addr", &self.out_ep1_wr_addr())
+            .field("out_ep1_rd_addr", &self.out_ep1_rd_addr())
+            .field("out_ep1_rec_data_cnt", &self.out_ep1_rec_data_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EP1_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USB_DEVICE_OUT_EP1_ST_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep1_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EP1_ST_SPEC;
 impl crate::RegisterSpec for OUT_EP1_ST_SPEC {
diff --git a/esp32c3/src/usb_device/out_ep2_st.rs b/esp32c3/src/usb_device/out_ep2_st.rs
index 8dfbd246e4..53cb009a75 100644
--- a/esp32c3/src/usb_device/out_ep2_st.rs
+++ b/esp32c3/src/usb_device/out_ep2_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EP2_ST")
-            .field(
-                "out_ep2_state",
-                &format_args!("{}", self.out_ep2_state().bits()),
-            )
-            .field(
-                "out_ep2_wr_addr",
-                &format_args!("{}", self.out_ep2_wr_addr().bits()),
-            )
-            .field(
-                "out_ep2_rd_addr",
-                &format_args!("{}", self.out_ep2_rd_addr().bits()),
-            )
+            .field("out_ep2_state", &self.out_ep2_state())
+            .field("out_ep2_wr_addr", &self.out_ep2_wr_addr())
+            .field("out_ep2_rd_addr", &self.out_ep2_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EP2_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USB_DEVICE_OUT_EP2_ST_REG.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep2_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EP2_ST_SPEC;
 impl crate::RegisterSpec for OUT_EP2_ST_SPEC {
diff --git a/esp32c3/src/usb_device/test.rs b/esp32c3/src/usb_device/test.rs
index 945758cccd..86f4a96e1a 100644
--- a/esp32c3/src/usb_device/test.rs
+++ b/esp32c3/src/usb_device/test.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEST")
-            .field("enable", &format_args!("{}", self.enable().bit()))
-            .field("usb_oe", &format_args!("{}", self.usb_oe().bit()))
-            .field("tx_dp", &format_args!("{}", self.tx_dp().bit()))
-            .field("tx_dm", &format_args!("{}", self.tx_dm().bit()))
+            .field("enable", &self.enable())
+            .field("usb_oe", &self.usb_oe())
+            .field("tx_dp", &self.tx_dp())
+            .field("tx_dm", &self.tx_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable test of the USB pad"]
     #[inline(always)]
diff --git a/esp32c3/src/xts_aes/date.rs b/esp32c3/src/xts_aes/date.rs
index 06bf4cb620..2eb7ba08c7 100644
--- a/esp32c3/src/xts_aes/date.rs
+++ b/esp32c3/src/xts_aes/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c3/src/xts_aes/destination.rs b/esp32c3/src/xts_aes/destination.rs
index bc69d838ce..1ed3e118bc 100644
--- a/esp32c3/src/xts_aes/destination.rs
+++ b/esp32c3/src/xts_aes/destination.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DESTINATION")
-            .field("destination", &format_args!("{}", self.destination().bit()))
+            .field("destination", &self.destination())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DESTINATION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit stores the destination. 0: flash(default). 1: reserved."]
     #[inline(always)]
diff --git a/esp32c3/src/xts_aes/linesize.rs b/esp32c3/src/xts_aes/linesize.rs
index 63b82089ab..965f433768 100644
--- a/esp32c3/src/xts_aes/linesize.rs
+++ b/esp32c3/src/xts_aes/linesize.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LINESIZE")
-            .field("linesize", &format_args!("{}", self.linesize().bit()))
+            .field("linesize", &self.linesize())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LINESIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit stores the line size parameter. 0: 16Byte, 1: 32Byte."]
     #[inline(always)]
diff --git a/esp32c3/src/xts_aes/physical_address.rs b/esp32c3/src/xts_aes/physical_address.rs
index 5146820356..ff4e5032db 100644
--- a/esp32c3/src/xts_aes/physical_address.rs
+++ b/esp32c3/src/xts_aes/physical_address.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHYSICAL_ADDRESS")
-            .field(
-                "physical_address",
-                &format_args!("{}", self.physical_address().bits()),
-            )
+            .field("physical_address", &self.physical_address())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHYSICAL_ADDRESS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes."]
     #[inline(always)]
diff --git a/esp32c3/src/xts_aes/plain_mem.rs b/esp32c3/src/xts_aes/plain_mem.rs
index d6b012bb1f..1f80f61b9f 100644
--- a/esp32c3/src/xts_aes/plain_mem.rs
+++ b/esp32c3/src/xts_aes/plain_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PLAIN_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores plaintext\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`plain_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`plain_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PLAIN_MEM_SPEC;
diff --git a/esp32c3/src/xts_aes/state.rs b/esp32c3/src/xts_aes/state.rs
index 27302f7c38..8588613069 100644
--- a/esp32c3/src/xts_aes/state.rs
+++ b/esp32c3/src/xts_aes/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("state", &format_args!("{}", self.state().bits()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "XTS-AES status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32c6-lp/src/generic.rs b/esp32c6-lp/src/generic.rs
index a2ae6aa053..45ebed16c4 100644
--- a/esp32c6-lp/src/generic.rs
+++ b/esp32c6-lp/src/generic.rs
@@ -48,7 +48,7 @@ pub trait RegisterSpec {
 #[doc = " Raw field type"]
 pub trait FieldSpec: Sized {
     #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
-    type Ux: Copy + PartialEq + From<Self>;
+    type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
 }
 #[doc = " Marker for fields with fixed values"]
 pub trait IsEnum: FieldSpec {}
@@ -237,6 +237,14 @@ impl<REG: Readable + Writable> Reg<REG> {
         );
     }
 }
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
 #[doc(hidden)]
 pub mod raw;
 #[doc = " Register reader."]
@@ -302,6 +310,11 @@ impl<FI: FieldSpec> FieldReader<FI> {
         self.bits
     }
 }
+impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 impl<FI> PartialEq<FI> for FieldReader<FI>
 where
     FI: FieldSpec + Copy,
@@ -338,10 +351,21 @@ impl<FI> BitReader<FI> {
         self.bit()
     }
 }
+impl<FI> core::fmt::Debug for BitReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 #[doc = " Marker for register/field writers which can take any value of specified width"]
 pub struct Safe;
 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
 pub struct Unsafe;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct Range<const MIN: u64, const MAX: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeFrom<const MIN: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeTo<const MAX: u64>;
 #[doc = " Write field Proxy"]
 pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
     raw::FieldWriter<'a, REG, WI, FI, Safety>;
@@ -393,6 +417,58 @@ where
         unsafe { self.bits(value) }
     }
 }
+impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
+    FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN && value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
 impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
diff --git a/esp32c6-lp/src/lib.rs b/esp32c6-lp/src/lib.rs
index 86bed7bbdb..7f82286377 100644
--- a/esp32c6-lp/src/lib.rs
+++ b/esp32c6-lp/src/lib.rs
@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32-C6-LP microcontrollers (generated using svd2rust v0.33.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32-C6-LP microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
diff --git a/esp32c6-lp/src/lp_ana/bod_mode0_cntl.rs b/esp32c6-lp/src/lp_ana/bod_mode0_cntl.rs
index 4eae1d17a9..51c9ae872d 100644
--- a/esp32c6-lp/src/lp_ana/bod_mode0_cntl.rs
+++ b/esp32c6-lp/src/lp_ana/bod_mode0_cntl.rs
@@ -82,45 +82,18 @@ impl core::fmt::Debug for R {
         f.debug_struct("BOD_MODE0_CNTL")
             .field(
                 "bod_mode0_close_flash_ena",
-                &format_args!("{}", self.bod_mode0_close_flash_ena().bit()),
-            )
-            .field(
-                "bod_mode0_pd_rf_ena",
-                &format_args!("{}", self.bod_mode0_pd_rf_ena().bit()),
-            )
-            .field(
-                "bod_mode0_intr_wait",
-                &format_args!("{}", self.bod_mode0_intr_wait().bits()),
-            )
-            .field(
-                "bod_mode0_reset_wait",
-                &format_args!("{}", self.bod_mode0_reset_wait().bits()),
-            )
-            .field(
-                "bod_mode0_cnt_clr",
-                &format_args!("{}", self.bod_mode0_cnt_clr().bit()),
-            )
-            .field(
-                "bod_mode0_intr_ena",
-                &format_args!("{}", self.bod_mode0_intr_ena().bit()),
-            )
-            .field(
-                "bod_mode0_reset_sel",
-                &format_args!("{}", self.bod_mode0_reset_sel().bit()),
-            )
-            .field(
-                "bod_mode0_reset_ena",
-                &format_args!("{}", self.bod_mode0_reset_ena().bit()),
+                &self.bod_mode0_close_flash_ena(),
             )
+            .field("bod_mode0_pd_rf_ena", &self.bod_mode0_pd_rf_ena())
+            .field("bod_mode0_intr_wait", &self.bod_mode0_intr_wait())
+            .field("bod_mode0_reset_wait", &self.bod_mode0_reset_wait())
+            .field("bod_mode0_cnt_clr", &self.bod_mode0_cnt_clr())
+            .field("bod_mode0_intr_ena", &self.bod_mode0_intr_ena())
+            .field("bod_mode0_reset_sel", &self.bod_mode0_reset_sel())
+            .field("bod_mode0_reset_ena", &self.bod_mode0_reset_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BOD_MODE0_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_ana/bod_mode1_cntl.rs b/esp32c6-lp/src/lp_ana/bod_mode1_cntl.rs
index daab8a45d0..3aa7fe569f 100644
--- a/esp32c6-lp/src/lp_ana/bod_mode1_cntl.rs
+++ b/esp32c6-lp/src/lp_ana/bod_mode1_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BOD_MODE1_CNTL")
-            .field(
-                "bod_mode1_reset_ena",
-                &format_args!("{}", self.bod_mode1_reset_ena().bit()),
-            )
+            .field("bod_mode1_reset_ena", &self.bod_mode1_reset_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BOD_MODE1_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_ana/ck_glitch_cntl.rs b/esp32c6-lp/src/lp_ana/ck_glitch_cntl.rs
index 603bbcf118..e33a2b6db7 100644
--- a/esp32c6-lp/src/lp_ana/ck_glitch_cntl.rs
+++ b/esp32c6-lp/src/lp_ana/ck_glitch_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CK_GLITCH_CNTL")
-            .field(
-                "ck_glitch_reset_ena",
-                &format_args!("{}", self.ck_glitch_reset_ena().bit()),
-            )
+            .field("ck_glitch_reset_ena", &self.ck_glitch_reset_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CK_GLITCH_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_ana/date.rs b/esp32c6-lp/src/lp_ana/date.rs
index 019a29ebac..c7f4235d1c 100644
--- a/esp32c6-lp/src/lp_ana/date.rs
+++ b/esp32c6-lp/src/lp_ana/date.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "lp_ana_date",
-                &format_args!("{}", self.lp_ana_date().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("lp_ana_date", &self.lp_ana_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_ana/fib_enable.rs b/esp32c6-lp/src/lp_ana/fib_enable.rs
index 4b991a5896..e6b9fbc95c 100644
--- a/esp32c6-lp/src/lp_ana/fib_enable.rs
+++ b/esp32c6-lp/src/lp_ana/fib_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIB_ENABLE")
-            .field(
-                "ana_fib_ena",
-                &format_args!("{}", self.ana_fib_ena().bits()),
-            )
+            .field("ana_fib_ena", &self.ana_fib_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIB_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_ana/int_ena.rs b/esp32c6-lp/src/lp_ana/int_ena.rs
index 31a2ee44d7..35d587ca0d 100644
--- a/esp32c6-lp/src/lp_ana/int_ena.rs
+++ b/esp32c6-lp/src/lp_ana/int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_ana/int_raw.rs b/esp32c6-lp/src/lp_ana/int_raw.rs
index e0d8bd0b0e..63d7c84adf 100644
--- a/esp32c6-lp/src/lp_ana/int_raw.rs
+++ b/esp32c6-lp/src/lp_ana/int_raw.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_ana/int_st.rs b/esp32c6-lp/src/lp_ana/int_st.rs
index 9114ca074f..c214cea0ba 100644
--- a/esp32c6-lp/src/lp_ana/int_st.rs
+++ b/esp32c6-lp/src/lp_ana/int_st.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6-lp/src/lp_ana/lp_int_ena.rs b/esp32c6-lp/src/lp_ana/lp_int_ena.rs
index 20c74f7372..044e93357d 100644
--- a/esp32c6-lp/src/lp_ana/lp_int_ena.rs
+++ b/esp32c6-lp/src/lp_ana/lp_int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ENA")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_ana/lp_int_raw.rs b/esp32c6-lp/src/lp_ana/lp_int_raw.rs
index fcbabdea21..dde3b77a5d 100644
--- a/esp32c6-lp/src/lp_ana/lp_int_raw.rs
+++ b/esp32c6-lp/src/lp_ana/lp_int_raw.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_RAW")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_ana/lp_int_st.rs b/esp32c6-lp/src/lp_ana/lp_int_st.rs
index 8516622718..2e393bffab 100644
--- a/esp32c6-lp/src/lp_ana/lp_int_st.rs
+++ b/esp32c6-lp/src/lp_ana/lp_int_st.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ST")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_INT_ST_SPEC;
 impl crate::RegisterSpec for LP_INT_ST_SPEC {
diff --git a/esp32c6-lp/src/lp_aon/cpucore0_cfg.rs b/esp32c6-lp/src/lp_aon/cpucore0_cfg.rs
index 8582b7abe3..b8f00ddbcf 100644
--- a/esp32c6-lp/src/lp_aon/cpucore0_cfg.rs
+++ b/esp32c6-lp/src/lp_aon/cpucore0_cfg.rs
@@ -46,31 +46,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPUCORE0_CFG")
-            .field(
-                "cpu_core0_sw_stall",
-                &format_args!("{}", self.cpu_core0_sw_stall().bits()),
-            )
+            .field("cpu_core0_sw_stall", &self.cpu_core0_sw_stall())
             .field(
                 "cpu_core0_ocd_halt_on_reset",
-                &format_args!("{}", self.cpu_core0_ocd_halt_on_reset().bit()),
+                &self.cpu_core0_ocd_halt_on_reset(),
             )
             .field(
                 "cpu_core0_stat_vector_sel",
-                &format_args!("{}", self.cpu_core0_stat_vector_sel().bit()),
-            )
-            .field(
-                "cpu_core0_dreset_mask",
-                &format_args!("{}", self.cpu_core0_dreset_mask().bit()),
+                &self.cpu_core0_stat_vector_sel(),
             )
+            .field("cpu_core0_dreset_mask", &self.cpu_core0_dreset_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPUCORE0_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/date.rs b/esp32c6-lp/src/lp_aon/date.rs
index 2a59463e6d..80edcb7cad 100644
--- a/esp32c6-lp/src/lp_aon/date.rs
+++ b/esp32c6-lp/src/lp_aon/date.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("date", &self.date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/ext_wakeup_cntl.rs b/esp32c6-lp/src/lp_aon/ext_wakeup_cntl.rs
index d9f39d0a90..0b2d26e41a 100644
--- a/esp32c6-lp/src/lp_aon/ext_wakeup_cntl.rs
+++ b/esp32c6-lp/src/lp_aon/ext_wakeup_cntl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP_CNTL")
-            .field(
-                "ext_wakeup_status",
-                &format_args!("{}", self.ext_wakeup_status().bits()),
-            )
-            .field(
-                "ext_wakeup_sel",
-                &format_args!("{}", self.ext_wakeup_sel().bits()),
-            )
-            .field(
-                "ext_wakeup_lv",
-                &format_args!("{}", self.ext_wakeup_lv().bits()),
-            )
-            .field(
-                "ext_wakeup_filter",
-                &format_args!("{}", self.ext_wakeup_filter().bit()),
-            )
+            .field("ext_wakeup_status", &self.ext_wakeup_status())
+            .field("ext_wakeup_sel", &self.ext_wakeup_sel())
+            .field("ext_wakeup_lv", &self.ext_wakeup_lv())
+            .field("ext_wakeup_filter", &self.ext_wakeup_filter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 14 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/gpio_hold0.rs b/esp32c6-lp/src/lp_aon/gpio_hold0.rs
index b332611022..0fc6ebfa90 100644
--- a/esp32c6-lp/src/lp_aon/gpio_hold0.rs
+++ b/esp32c6-lp/src/lp_aon/gpio_hold0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_HOLD0")
-            .field("gpio_hold0", &format_args!("{}", self.gpio_hold0().bits()))
+            .field("gpio_hold0", &self.gpio_hold0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_HOLD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/gpio_hold1.rs b/esp32c6-lp/src/lp_aon/gpio_hold1.rs
index 46eec62bc5..005befb609 100644
--- a/esp32c6-lp/src/lp_aon/gpio_hold1.rs
+++ b/esp32c6-lp/src/lp_aon/gpio_hold1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_HOLD1")
-            .field("gpio_hold1", &format_args!("{}", self.gpio_hold1().bits()))
+            .field("gpio_hold1", &self.gpio_hold1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_HOLD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/gpio_mux.rs b/esp32c6-lp/src/lp_aon/gpio_mux.rs
index 9455ae5e1e..4977bbe7d6 100644
--- a/esp32c6-lp/src/lp_aon/gpio_mux.rs
+++ b/esp32c6-lp/src/lp_aon/gpio_mux.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_MUX")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_MUX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/io_mux.rs b/esp32c6-lp/src/lp_aon/io_mux.rs
index de059fe1f6..082a0e1e1d 100644
--- a/esp32c6-lp/src/lp_aon/io_mux.rs
+++ b/esp32c6-lp/src/lp_aon/io_mux.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IO_MUX")
-            .field(
-                "reset_disable",
-                &format_args!("{}", self.reset_disable().bit()),
-            )
+            .field("reset_disable", &self.reset_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IO_MUX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/lpbus.rs b/esp32c6-lp/src/lp_aon/lpbus.rs
index 1081be24b2..c2a7be1004 100644
--- a/esp32c6-lp/src/lp_aon/lpbus.rs
+++ b/esp32c6-lp/src/lp_aon/lpbus.rs
@@ -60,39 +60,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPBUS")
-            .field(
-                "fast_mem_wpulse",
-                &format_args!("{}", self.fast_mem_wpulse().bits()),
-            )
-            .field(
-                "fast_mem_wa",
-                &format_args!("{}", self.fast_mem_wa().bits()),
-            )
-            .field(
-                "fast_mem_ra",
-                &format_args!("{}", self.fast_mem_ra().bits()),
-            )
-            .field(
-                "fast_mem_mux_fsm_idle",
-                &format_args!("{}", self.fast_mem_mux_fsm_idle().bit()),
-            )
-            .field(
-                "fast_mem_mux_sel_status",
-                &format_args!("{}", self.fast_mem_mux_sel_status().bit()),
-            )
-            .field(
-                "fast_mem_mux_sel",
-                &format_args!("{}", self.fast_mem_mux_sel().bit()),
-            )
+            .field("fast_mem_wpulse", &self.fast_mem_wpulse())
+            .field("fast_mem_wa", &self.fast_mem_wa())
+            .field("fast_mem_ra", &self.fast_mem_ra())
+            .field("fast_mem_mux_fsm_idle", &self.fast_mem_mux_fsm_idle())
+            .field("fast_mem_mux_sel_status", &self.fast_mem_mux_sel_status())
+            .field("fast_mem_mux_sel", &self.fast_mem_mux_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPBUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:18 - This field controls fast memory WPULSE parameter."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/lpcore.rs b/esp32c6-lp/src/lp_aon/lpcore.rs
index 1530ce66d6..947b244450 100644
--- a/esp32c6-lp/src/lp_aon/lpcore.rs
+++ b/esp32c6-lp/src/lp_aon/lpcore.rs
@@ -28,20 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPCORE")
-            .field(
-                "etm_wakeup_flag",
-                &format_args!("{}", self.etm_wakeup_flag().bit()),
-            )
-            .field("disable", &format_args!("{}", self.disable().bit()))
+            .field("etm_wakeup_flag", &self.etm_wakeup_flag())
+            .field("disable", &self.disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPCORE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/sar_cct.rs b/esp32c6-lp/src/lp_aon/sar_cct.rs
index 305cefc278..bd1e64f8cf 100644
--- a/esp32c6-lp/src/lp_aon/sar_cct.rs
+++ b/esp32c6-lp/src/lp_aon/sar_cct.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_CCT")
-            .field(
-                "sar2_pwdet_cct",
-                &format_args!("{}", self.sar2_pwdet_cct().bits()),
-            )
+            .field("sar2_pwdet_cct", &self.sar2_pwdet_cct())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_CCT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 29:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/sdio_active.rs b/esp32c6-lp/src/lp_aon/sdio_active.rs
index c0a0c8c452..bba850a575 100644
--- a/esp32c6-lp/src/lp_aon/sdio_active.rs
+++ b/esp32c6-lp/src/lp_aon/sdio_active.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_ACTIVE")
-            .field(
-                "sdio_act_dnum",
-                &format_args!("{}", self.sdio_act_dnum().bits()),
-            )
+            .field("sdio_act_dnum", &self.sdio_act_dnum())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_ACTIVE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/store0.rs b/esp32c6-lp/src/lp_aon/store0.rs
index 750dead68d..4045afdfcb 100644
--- a/esp32c6-lp/src/lp_aon/store0.rs
+++ b/esp32c6-lp/src/lp_aon/store0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE0")
-            .field(
-                "lp_aon_store0",
-                &format_args!("{}", self.lp_aon_store0().bits()),
-            )
+            .field("lp_aon_store0", &self.lp_aon_store0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/store1.rs b/esp32c6-lp/src/lp_aon/store1.rs
index 2a79b3c129..81a74039fa 100644
--- a/esp32c6-lp/src/lp_aon/store1.rs
+++ b/esp32c6-lp/src/lp_aon/store1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE1")
-            .field(
-                "lp_aon_store1",
-                &format_args!("{}", self.lp_aon_store1().bits()),
-            )
+            .field("lp_aon_store1", &self.lp_aon_store1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/store2.rs b/esp32c6-lp/src/lp_aon/store2.rs
index 0f6971a297..82b8006008 100644
--- a/esp32c6-lp/src/lp_aon/store2.rs
+++ b/esp32c6-lp/src/lp_aon/store2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE2")
-            .field(
-                "lp_aon_store2",
-                &format_args!("{}", self.lp_aon_store2().bits()),
-            )
+            .field("lp_aon_store2", &self.lp_aon_store2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/store3.rs b/esp32c6-lp/src/lp_aon/store3.rs
index ea9df2e7cb..ebb777ec5f 100644
--- a/esp32c6-lp/src/lp_aon/store3.rs
+++ b/esp32c6-lp/src/lp_aon/store3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE3")
-            .field(
-                "lp_aon_store3",
-                &format_args!("{}", self.lp_aon_store3().bits()),
-            )
+            .field("lp_aon_store3", &self.lp_aon_store3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/store4.rs b/esp32c6-lp/src/lp_aon/store4.rs
index 2021c24b50..488dee70f8 100644
--- a/esp32c6-lp/src/lp_aon/store4.rs
+++ b/esp32c6-lp/src/lp_aon/store4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE4")
-            .field(
-                "lp_aon_store4",
-                &format_args!("{}", self.lp_aon_store4().bits()),
-            )
+            .field("lp_aon_store4", &self.lp_aon_store4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/store5.rs b/esp32c6-lp/src/lp_aon/store5.rs
index 273844ba76..f495df460f 100644
--- a/esp32c6-lp/src/lp_aon/store5.rs
+++ b/esp32c6-lp/src/lp_aon/store5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE5")
-            .field(
-                "lp_aon_store5",
-                &format_args!("{}", self.lp_aon_store5().bits()),
-            )
+            .field("lp_aon_store5", &self.lp_aon_store5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/store6.rs b/esp32c6-lp/src/lp_aon/store6.rs
index 54446a0324..5ad9e73830 100644
--- a/esp32c6-lp/src/lp_aon/store6.rs
+++ b/esp32c6-lp/src/lp_aon/store6.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE6")
-            .field(
-                "lp_aon_store6",
-                &format_args!("{}", self.lp_aon_store6().bits()),
-            )
+            .field("lp_aon_store6", &self.lp_aon_store6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/store7.rs b/esp32c6-lp/src/lp_aon/store7.rs
index b7c4164974..f00bf7f8db 100644
--- a/esp32c6-lp/src/lp_aon/store7.rs
+++ b/esp32c6-lp/src/lp_aon/store7.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE7")
-            .field(
-                "lp_aon_store7",
-                &format_args!("{}", self.lp_aon_store7().bits()),
-            )
+            .field("lp_aon_store7", &self.lp_aon_store7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/store8.rs b/esp32c6-lp/src/lp_aon/store8.rs
index d35122193f..0daf1323bb 100644
--- a/esp32c6-lp/src/lp_aon/store8.rs
+++ b/esp32c6-lp/src/lp_aon/store8.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE8")
-            .field(
-                "lp_aon_store8",
-                &format_args!("{}", self.lp_aon_store8().bits()),
-            )
+            .field("lp_aon_store8", &self.lp_aon_store8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/store9.rs b/esp32c6-lp/src/lp_aon/store9.rs
index 460dd4ac7a..a510c36f12 100644
--- a/esp32c6-lp/src/lp_aon/store9.rs
+++ b/esp32c6-lp/src/lp_aon/store9.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE9")
-            .field(
-                "lp_aon_store9",
-                &format_args!("{}", self.lp_aon_store9().bits()),
-            )
+            .field("lp_aon_store9", &self.lp_aon_store9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/sys_cfg.rs b/esp32c6-lp/src/lp_aon/sys_cfg.rs
index edc95b81e1..a6d6336740 100644
--- a/esp32c6-lp/src/lp_aon/sys_cfg.rs
+++ b/esp32c6-lp/src/lp_aon/sys_cfg.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYS_CFG")
-            .field(
-                "force_download_boot",
-                &format_args!("{}", self.force_download_boot().bit()),
-            )
+            .field("force_download_boot", &self.force_download_boot())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYS_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_aon/usb.rs b/esp32c6-lp/src/lp_aon/usb.rs
index 78395ff8ef..0ffe7bb3d6 100644
--- a/esp32c6-lp/src/lp_aon/usb.rs
+++ b/esp32c6-lp/src/lp_aon/usb.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB")
-            .field(
-                "reset_disable",
-                &format_args!("{}", self.reset_disable().bit()),
-            )
+            .field("reset_disable", &self.reset_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_apm/clock_gate.rs b/esp32c6-lp/src/lp_apm/clock_gate.rs
index 0ea9f4e7a3..0260550609 100644
--- a/esp32c6-lp/src/lp_apm/clock_gate.rs
+++ b/esp32c6-lp/src/lp_apm/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_clk_en"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_apm/date.rs b/esp32c6-lp/src/lp_apm/date.rs
index fb73a9a02f..3825783dcf 100644
--- a/esp32c6-lp/src/lp_apm/date.rs
+++ b/esp32c6-lp/src/lp_apm/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6-lp/src/lp_apm/func_ctrl.rs b/esp32c6-lp/src/lp_apm/func_ctrl.rs
index 7bc45f6559..b2ca69ca9c 100644
--- a/esp32c6-lp/src/lp_apm/func_ctrl.rs
+++ b/esp32c6-lp/src/lp_apm/func_ctrl.rs
@@ -37,23 +37,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_CTRL")
-            .field(
-                "m0_pms_func_en",
-                &format_args!("{}", self.m0_pms_func_en().bit()),
-            )
-            .field(
-                "m1_pms_func_en",
-                &format_args!("{}", self.m1_pms_func_en().bit()),
-            )
+            .field("m0_pms_func_en", &self.m0_pms_func_en())
+            .field("m1_pms_func_en", &self.m1_pms_func_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "PMS M(0-1) function enable"]
     #[doc = ""]
diff --git a/esp32c6-lp/src/lp_apm/int_en.rs b/esp32c6-lp/src/lp_apm/int_en.rs
index 0ed15aee51..7423665485 100644
--- a/esp32c6-lp/src/lp_apm/int_en.rs
+++ b/esp32c6-lp/src/lp_apm/int_en.rs
@@ -37,17 +37,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_EN")
-            .field("m0_apm", &format_args!("{}", self.m0_apm().bit()))
-            .field("m1_apm", &format_args!("{}", self.m1_apm().bit()))
+            .field("m0_apm", &self.m0_apm())
+            .field("m1_apm", &self.m1_apm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "APM M(0-1) interrupt enable"]
     #[doc = ""]
diff --git a/esp32c6-lp/src/lp_apm/m/exception_info0.rs b/esp32c6-lp/src/lp_apm/m/exception_info0.rs
index a0d5dea6f4..2c4b8088fb 100644
--- a/esp32c6-lp/src/lp_apm/m/exception_info0.rs
+++ b/esp32c6-lp/src/lp_apm/m/exception_info0.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXCEPTION_INFO0")
-            .field(
-                "exception_region",
-                &format_args!("{}", self.exception_region().bits()),
-            )
-            .field(
-                "exception_mode",
-                &format_args!("{}", self.exception_mode().bits()),
-            )
-            .field(
-                "exception_id",
-                &format_args!("{}", self.exception_id().bits()),
-            )
+            .field("exception_region", &self.exception_region())
+            .field("exception_mode", &self.exception_mode())
+            .field("exception_id", &self.exception_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXCEPTION_INFO0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 exception_info0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exception_info0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXCEPTION_INFO0_SPEC;
 impl crate::RegisterSpec for EXCEPTION_INFO0_SPEC {
diff --git a/esp32c6-lp/src/lp_apm/m/exception_info1.rs b/esp32c6-lp/src/lp_apm/m/exception_info1.rs
index 1a6977abc5..cb3b39d257 100644
--- a/esp32c6-lp/src/lp_apm/m/exception_info1.rs
+++ b/esp32c6-lp/src/lp_apm/m/exception_info1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXCEPTION_INFO1")
-            .field(
-                "exception_addr",
-                &format_args!("{}", self.exception_addr().bits()),
-            )
+            .field("exception_addr", &self.exception_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXCEPTION_INFO1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 exception_info1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exception_info1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXCEPTION_INFO1_SPEC;
 impl crate::RegisterSpec for EXCEPTION_INFO1_SPEC {
diff --git a/esp32c6-lp/src/lp_apm/m/status.rs b/esp32c6-lp/src/lp_apm/m/status.rs
index 6a5c666bbf..3e275a91ca 100644
--- a/esp32c6-lp/src/lp_apm/m/status.rs
+++ b/esp32c6-lp/src/lp_apm/m/status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field(
-                "exception_status",
-                &format_args!("{}", self.exception_status().bits()),
-            )
+            .field("exception_status", &self.exception_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32c6-lp/src/lp_apm/region/addr_end.rs b/esp32c6-lp/src/lp_apm/region/addr_end.rs
index 8940485f11..db15e1b66a 100644
--- a/esp32c6-lp/src/lp_apm/region/addr_end.rs
+++ b/esp32c6-lp/src/lp_apm/region/addr_end.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR_END")
-            .field("addr_end", &format_args!("{}", self.addr_end().bits()))
+            .field("addr_end", &self.addr_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_END_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - End address of region0"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_apm/region/addr_start.rs b/esp32c6-lp/src/lp_apm/region/addr_start.rs
index 15654e8830..21d743f5e2 100644
--- a/esp32c6-lp/src/lp_apm/region/addr_start.rs
+++ b/esp32c6-lp/src/lp_apm/region/addr_start.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR_START")
-            .field("addr_start", &format_args!("{}", self.addr_start().bits()))
+            .field("addr_start", &self.addr_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_START_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Start address of region0"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_apm/region/pms_attr.rs b/esp32c6-lp/src/lp_apm/region/pms_attr.rs
index 30b2486d8c..a929b05fa9 100644
--- a/esp32c6-lp/src/lp_apm/region/pms_attr.rs
+++ b/esp32c6-lp/src/lp_apm/region/pms_attr.rs
@@ -110,24 +110,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMS_ATTR")
-            .field("r0_pms_x", &format_args!("{}", self.r0_pms_x().bit()))
-            .field("r1_pms_x", &format_args!("{}", self.r1_pms_x().bit()))
-            .field("r2_pms_x", &format_args!("{}", self.r2_pms_x().bit()))
-            .field("r0_pms_w", &format_args!("{}", self.r0_pms_w().bit()))
-            .field("r1_pms_w", &format_args!("{}", self.r1_pms_w().bit()))
-            .field("r2_pms_w", &format_args!("{}", self.r2_pms_w().bit()))
-            .field("r0_pms_r", &format_args!("{}", self.r0_pms_r().bit()))
-            .field("r1_pms_r", &format_args!("{}", self.r1_pms_r().bit()))
-            .field("r2_pms_r", &format_args!("{}", self.r2_pms_r().bit()))
+            .field("r0_pms_x", &self.r0_pms_x())
+            .field("r1_pms_x", &self.r1_pms_x())
+            .field("r2_pms_x", &self.r2_pms_x())
+            .field("r0_pms_w", &self.r0_pms_w())
+            .field("r1_pms_w", &self.r1_pms_w())
+            .field("r2_pms_w", &self.r2_pms_w())
+            .field("r0_pms_r", &self.r0_pms_r())
+            .field("r1_pms_r", &self.r1_pms_r())
+            .field("r2_pms_r", &self.r2_pms_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMS_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Region execute authority in REE_MODE(0-2)"]
     #[doc = ""]
diff --git a/esp32c6-lp/src/lp_apm/region_filter_en.rs b/esp32c6-lp/src/lp_apm/region_filter_en.rs
index 981cf53ed6..d42627a48e 100644
--- a/esp32c6-lp/src/lp_apm/region_filter_en.rs
+++ b/esp32c6-lp/src/lp_apm/region_filter_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGION_FILTER_EN")
-            .field(
-                "region_filter_en",
-                &format_args!("{}", self.region_filter_en().bits()),
-            )
+            .field("region_filter_en", &self.region_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_FILTER_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Region filter enable"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_clkrst/clk_to_hp.rs b/esp32c6-lp/src/lp_clkrst/clk_to_hp.rs
index 901a6280ab..aa35ff4c00 100644
--- a/esp32c6-lp/src/lp_clkrst/clk_to_hp.rs
+++ b/esp32c6-lp/src/lp_clkrst/clk_to_hp.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_TO_HP")
-            .field(
-                "icg_hp_xtal32k",
-                &format_args!("{}", self.icg_hp_xtal32k().bit()),
-            )
-            .field("icg_hp_sosc", &format_args!("{}", self.icg_hp_sosc().bit()))
-            .field(
-                "icg_hp_osc32k",
-                &format_args!("{}", self.icg_hp_osc32k().bit()),
-            )
-            .field("icg_hp_fosc", &format_args!("{}", self.icg_hp_fosc().bit()))
+            .field("icg_hp_xtal32k", &self.icg_hp_xtal32k())
+            .field("icg_hp_sosc", &self.icg_hp_sosc())
+            .field("icg_hp_osc32k", &self.icg_hp_osc32k())
+            .field("icg_hp_fosc", &self.icg_hp_fosc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_TO_HP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_clkrst/cpu_reset.rs b/esp32c6-lp/src/lp_clkrst/cpu_reset.rs
index 5975cda7af..c5e74019c0 100644
--- a/esp32c6-lp/src/lp_clkrst/cpu_reset.rs
+++ b/esp32c6-lp/src/lp_clkrst/cpu_reset.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_RESET")
-            .field(
-                "rtc_wdt_cpu_reset_length",
-                &format_args!("{}", self.rtc_wdt_cpu_reset_length().bits()),
-            )
-            .field(
-                "rtc_wdt_cpu_reset_en",
-                &format_args!("{}", self.rtc_wdt_cpu_reset_en().bit()),
-            )
-            .field(
-                "cpu_stall_wait",
-                &format_args!("{}", self.cpu_stall_wait().bits()),
-            )
-            .field(
-                "cpu_stall_en",
-                &format_args!("{}", self.cpu_stall_en().bit()),
-            )
+            .field("rtc_wdt_cpu_reset_length", &self.rtc_wdt_cpu_reset_length())
+            .field("rtc_wdt_cpu_reset_en", &self.rtc_wdt_cpu_reset_en())
+            .field("cpu_stall_wait", &self.cpu_stall_wait())
+            .field("cpu_stall_en", &self.cpu_stall_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_RESET_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:24 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_clkrst/date.rs b/esp32c6-lp/src/lp_clkrst/date.rs
index 079651ce06..8ab015a495 100644
--- a/esp32c6-lp/src/lp_clkrst/date.rs
+++ b/esp32c6-lp/src/lp_clkrst/date.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "clkrst_date",
-                &format_args!("{}", self.clkrst_date().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clkrst_date", &self.clkrst_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_clkrst/fosc_cntl.rs b/esp32c6-lp/src/lp_clkrst/fosc_cntl.rs
index 04deb50cae..abd5d3eaa3 100644
--- a/esp32c6-lp/src/lp_clkrst/fosc_cntl.rs
+++ b/esp32c6-lp/src/lp_clkrst/fosc_cntl.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FOSC_CNTL")
-            .field("fosc_dfreq", &format_args!("{}", self.fosc_dfreq().bits()))
+            .field("fosc_dfreq", &self.fosc_dfreq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FOSC_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_clkrst/lp_clk_conf.rs b/esp32c6-lp/src/lp_clkrst/lp_clk_conf.rs
index 16eef88e5a..bf8441701a 100644
--- a/esp32c6-lp/src/lp_clkrst/lp_clk_conf.rs
+++ b/esp32c6-lp/src/lp_clkrst/lp_clk_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CLK_CONF")
-            .field(
-                "slow_clk_sel",
-                &format_args!("{}", self.slow_clk_sel().bits()),
-            )
-            .field(
-                "fast_clk_sel",
-                &format_args!("{}", self.fast_clk_sel().bit()),
-            )
-            .field(
-                "lp_peri_div_num",
-                &format_args!("{}", self.lp_peri_div_num().bits()),
-            )
+            .field("slow_clk_sel", &self.slow_clk_sel())
+            .field("fast_clk_sel", &self.fast_clk_sel())
+            .field("lp_peri_div_num", &self.lp_peri_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_clkrst/lp_clk_en.rs b/esp32c6-lp/src/lp_clkrst/lp_clk_en.rs
index 316fc21b67..ec70392c24 100644
--- a/esp32c6-lp/src/lp_clkrst/lp_clk_en.rs
+++ b/esp32c6-lp/src/lp_clkrst/lp_clk_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CLK_EN")
-            .field(
-                "fast_ori_gate",
-                &format_args!("{}", self.fast_ori_gate().bit()),
-            )
+            .field("fast_ori_gate", &self.fast_ori_gate())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_clkrst/lp_clk_po_en.rs b/esp32c6-lp/src/lp_clkrst/lp_clk_po_en.rs
index 287da0bf37..118ba1f140 100644
--- a/esp32c6-lp/src/lp_clkrst/lp_clk_po_en.rs
+++ b/esp32c6-lp/src/lp_clkrst/lp_clk_po_en.rs
@@ -107,35 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CLK_PO_EN")
-            .field(
-                "aon_slow_oen",
-                &format_args!("{}", self.aon_slow_oen().bit()),
-            )
-            .field(
-                "aon_fast_oen",
-                &format_args!("{}", self.aon_fast_oen().bit()),
-            )
-            .field("sosc_oen", &format_args!("{}", self.sosc_oen().bit()))
-            .field("fosc_oen", &format_args!("{}", self.fosc_oen().bit()))
-            .field("osc32k_oen", &format_args!("{}", self.osc32k_oen().bit()))
-            .field("xtal32k_oen", &format_args!("{}", self.xtal32k_oen().bit()))
-            .field(
-                "core_efuse_oen",
-                &format_args!("{}", self.core_efuse_oen().bit()),
-            )
-            .field("slow_oen", &format_args!("{}", self.slow_oen().bit()))
-            .field("fast_oen", &format_args!("{}", self.fast_oen().bit()))
-            .field("rng_oen", &format_args!("{}", self.rng_oen().bit()))
-            .field("lpbus_oen", &format_args!("{}", self.lpbus_oen().bit()))
+            .field("aon_slow_oen", &self.aon_slow_oen())
+            .field("aon_fast_oen", &self.aon_fast_oen())
+            .field("sosc_oen", &self.sosc_oen())
+            .field("fosc_oen", &self.fosc_oen())
+            .field("osc32k_oen", &self.osc32k_oen())
+            .field("xtal32k_oen", &self.xtal32k_oen())
+            .field("core_efuse_oen", &self.core_efuse_oen())
+            .field("slow_oen", &self.slow_oen())
+            .field("fast_oen", &self.fast_oen())
+            .field("rng_oen", &self.rng_oen())
+            .field("lpbus_oen", &self.lpbus_oen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CLK_PO_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_clkrst/lp_rst_en.rs b/esp32c6-lp/src/lp_clkrst/lp_rst_en.rs
index 9147d2f88c..372756979e 100644
--- a/esp32c6-lp/src/lp_clkrst/lp_rst_en.rs
+++ b/esp32c6-lp/src/lp_clkrst/lp_rst_en.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_RST_EN")
-            .field(
-                "aon_efuse_core_reset_en",
-                &format_args!("{}", self.aon_efuse_core_reset_en().bit()),
-            )
-            .field(
-                "lp_timer_reset_en",
-                &format_args!("{}", self.lp_timer_reset_en().bit()),
-            )
-            .field(
-                "wdt_reset_en",
-                &format_args!("{}", self.wdt_reset_en().bit()),
-            )
-            .field(
-                "ana_peri_reset_en",
-                &format_args!("{}", self.ana_peri_reset_en().bit()),
-            )
+            .field("aon_efuse_core_reset_en", &self.aon_efuse_core_reset_en())
+            .field("lp_timer_reset_en", &self.lp_timer_reset_en())
+            .field("wdt_reset_en", &self.wdt_reset_en())
+            .field("ana_peri_reset_en", &self.ana_peri_reset_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_RST_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_clkrst/lpmem_force.rs b/esp32c6-lp/src/lp_clkrst/lpmem_force.rs
index 95a3efd9b8..c164724bb3 100644
--- a/esp32c6-lp/src/lp_clkrst/lpmem_force.rs
+++ b/esp32c6-lp/src/lp_clkrst/lpmem_force.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPMEM_FORCE")
-            .field(
-                "lpmem_clk_force_on",
-                &format_args!("{}", self.lpmem_clk_force_on().bit()),
-            )
+            .field("lpmem_clk_force_on", &self.lpmem_clk_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPMEM_FORCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_clkrst/lpperi.rs b/esp32c6-lp/src/lp_clkrst/lpperi.rs
index 760a54ec0d..92032fef09 100644
--- a/esp32c6-lp/src/lp_clkrst/lpperi.rs
+++ b/esp32c6-lp/src/lp_clkrst/lpperi.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPPERI")
-            .field(
-                "lp_i2c_clk_sel",
-                &format_args!("{}", self.lp_i2c_clk_sel().bit()),
-            )
-            .field(
-                "lp_uart_clk_sel",
-                &format_args!("{}", self.lp_uart_clk_sel().bit()),
-            )
+            .field("lp_i2c_clk_sel", &self.lp_i2c_clk_sel())
+            .field("lp_uart_clk_sel", &self.lp_uart_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPPERI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_clkrst/rc32k_cntl.rs b/esp32c6-lp/src/lp_clkrst/rc32k_cntl.rs
index a7abd1f2ef..50e5c9be91 100644
--- a/esp32c6-lp/src/lp_clkrst/rc32k_cntl.rs
+++ b/esp32c6-lp/src/lp_clkrst/rc32k_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RC32K_CNTL")
-            .field(
-                "rc32k_dfreq",
-                &format_args!("{}", self.rc32k_dfreq().bits()),
-            )
+            .field("rc32k_dfreq", &self.rc32k_dfreq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RC32K_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_clkrst/reset_cause.rs b/esp32c6-lp/src/lp_clkrst/reset_cause.rs
index 8e7da12acf..41cd6b06ce 100644
--- a/esp32c6-lp/src/lp_clkrst/reset_cause.rs
+++ b/esp32c6-lp/src/lp_clkrst/reset_cause.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET_CAUSE")
-            .field(
-                "reset_cause",
-                &format_args!("{}", self.reset_cause().bits()),
-            )
-            .field(
-                "core0_reset_flag",
-                &format_args!("{}", self.core0_reset_flag().bit()),
-            )
+            .field("reset_cause", &self.reset_cause())
+            .field("core0_reset_flag", &self.core0_reset_flag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET_CAUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 29 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_clkrst/xtal32k.rs b/esp32c6-lp/src/lp_clkrst/xtal32k.rs
index 0c231690c7..21734fb527 100644
--- a/esp32c6-lp/src/lp_clkrst/xtal32k.rs
+++ b/esp32c6-lp/src/lp_clkrst/xtal32k.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL32K")
-            .field(
-                "dres_xtal32k",
-                &format_args!("{}", self.dres_xtal32k().bits()),
-            )
-            .field(
-                "dgm_xtal32k",
-                &format_args!("{}", self.dgm_xtal32k().bits()),
-            )
-            .field(
-                "dbuf_xtal32k",
-                &format_args!("{}", self.dbuf_xtal32k().bit()),
-            )
-            .field(
-                "dac_xtal32k",
-                &format_args!("{}", self.dac_xtal32k().bits()),
-            )
+            .field("dres_xtal32k", &self.dres_xtal32k())
+            .field("dgm_xtal32k", &self.dgm_xtal32k())
+            .field("dbuf_xtal32k", &self.dbuf_xtal32k())
+            .field("dac_xtal32k", &self.dac_xtal32k())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL32K_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:24 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/clk_conf.rs b/esp32c6-lp/src/lp_i2c0/clk_conf.rs
index 0c369fb990..8575bb85bf 100644
--- a/esp32c6-lp/src/lp_i2c0/clk_conf.rs
+++ b/esp32c6-lp/src/lp_i2c0/clk_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bit()))
-            .field("sclk_active", &format_args!("{}", self.sclk_active().bit()))
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_active", &self.sclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/comd.rs b/esp32c6-lp/src/lp_i2c0/comd.rs
index 6f909ae304..980d858d87 100644
--- a/esp32c6-lp/src/lp_i2c0/comd.rs
+++ b/esp32c6-lp/src/lp_i2c0/comd.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMD")
-            .field("command", &format_args!("{}", self.command().bits()))
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This is the content of command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/ctr.rs b/esp32c6-lp/src/lp_i2c0/ctr.rs
index 33b3a99b33..5d855d0513 100644
--- a/esp32c6-lp/src/lp_i2c0/ctr.rs
+++ b/esp32c6-lp/src/lp_i2c0/ctr.rs
@@ -86,44 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTR")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field(
-                "sample_scl_level",
-                &format_args!("{}", self.sample_scl_level().bit()),
-            )
-            .field(
-                "rx_full_ack_level",
-                &format_args!("{}", self.rx_full_ack_level().bit()),
-            )
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "arbitration_en",
-                &format_args!("{}", self.arbitration_en().bit()),
-            )
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("sample_scl_level", &self.sample_scl_level())
+            .field("rx_full_ack_level", &self.rx_full_ack_level())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("clk_en", &self.clk_en())
+            .field("arbitration_en", &self.arbitration_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: direct output, 0: open drain output."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/data.rs b/esp32c6-lp/src/lp_i2c0/data.rs
index 098982488f..ffd32b29d3 100644
--- a/esp32c6-lp/src/lp_i2c0/data.rs
+++ b/esp32c6-lp/src/lp_i2c0/data.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field("fifo_rdata", &format_args!("{}", self.fifo_rdata().bits()))
+            .field("fifo_rdata", &self.fifo_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value of rx FIFO read data."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/date.rs b/esp32c6-lp/src/lp_i2c0/date.rs
index e0a952920c..184e093cee 100644
--- a/esp32c6-lp/src/lp_i2c0/date.rs
+++ b/esp32c6-lp/src/lp_i2c0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6-lp/src/lp_i2c0/fifo_conf.rs b/esp32c6-lp/src/lp_i2c0/fifo_conf.rs
index 8d7bcf4e41..765107a861 100644
--- a/esp32c6-lp/src/lp_i2c0/fifo_conf.rs
+++ b/esp32c6-lp/src/lp_i2c0/fifo_conf.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CONF")
-            .field(
-                "rxfifo_wm_thrhd",
-                &format_args!("{}", self.rxfifo_wm_thrhd().bits()),
-            )
-            .field(
-                "txfifo_wm_thrhd",
-                &format_args!("{}", self.txfifo_wm_thrhd().bits()),
-            )
-            .field("nonfifo_en", &format_args!("{}", self.nonfifo_en().bit()))
-            .field("rx_fifo_rst", &format_args!("{}", self.rx_fifo_rst().bit()))
-            .field("tx_fifo_rst", &format_args!("{}", self.tx_fifo_rst().bit()))
-            .field("fifo_prt_en", &format_args!("{}", self.fifo_prt_en().bit()))
+            .field("rxfifo_wm_thrhd", &self.rxfifo_wm_thrhd())
+            .field("txfifo_wm_thrhd", &self.txfifo_wm_thrhd())
+            .field("nonfifo_en", &self.nonfifo_en())
+            .field("rx_fifo_rst", &self.rx_fifo_rst())
+            .field("tx_fifo_rst", &self.tx_fifo_rst())
+            .field("fifo_prt_en", &self.fifo_prt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[3:0\\], reg_rxfifo_wm_int_raw bit will be valid."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/fifo_st.rs b/esp32c6-lp/src/lp_i2c0/fifo_st.rs
index 566d9a1fdb..fda04e5d4d 100644
--- a/esp32c6-lp/src/lp_i2c0/fifo_st.rs
+++ b/esp32c6-lp/src/lp_i2c0/fifo_st.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_ST")
-            .field(
-                "rxfifo_raddr",
-                &format_args!("{}", self.rxfifo_raddr().bits()),
-            )
-            .field(
-                "rxfifo_waddr",
-                &format_args!("{}", self.rxfifo_waddr().bits()),
-            )
-            .field(
-                "txfifo_raddr",
-                &format_args!("{}", self.txfifo_raddr().bits()),
-            )
-            .field(
-                "txfifo_waddr",
-                &format_args!("{}", self.txfifo_waddr().bits()),
-            )
+            .field("rxfifo_raddr", &self.rxfifo_raddr())
+            .field("rxfifo_waddr", &self.rxfifo_waddr())
+            .field("txfifo_raddr", &self.txfifo_raddr())
+            .field("txfifo_waddr", &self.txfifo_waddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "FIFO status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_ST_SPEC;
 impl crate::RegisterSpec for FIFO_ST_SPEC {
diff --git a/esp32c6-lp/src/lp_i2c0/filter_cfg.rs b/esp32c6-lp/src/lp_i2c0/filter_cfg.rs
index b05ae9a4bf..98bdaa5979 100644
--- a/esp32c6-lp/src/lp_i2c0/filter_cfg.rs
+++ b/esp32c6-lp/src/lp_i2c0/filter_cfg.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CFG")
-            .field(
-                "scl_filter_thres",
-                &format_args!("{}", self.scl_filter_thres().bits()),
-            )
-            .field(
-                "sda_filter_thres",
-                &format_args!("{}", self.sda_filter_thres().bits()),
-            )
-            .field(
-                "scl_filter_en",
-                &format_args!("{}", self.scl_filter_en().bit()),
-            )
-            .field(
-                "sda_filter_en",
-                &format_args!("{}", self.sda_filter_en().bit()),
-            )
+            .field("scl_filter_thres", &self.scl_filter_thres())
+            .field("sda_filter_thres", &self.sda_filter_thres())
+            .field("scl_filter_en", &self.scl_filter_en())
+            .field("sda_filter_en", &self.sda_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/int_ena.rs b/esp32c6-lp/src/lp_i2c0/int_ena.rs
index 8accc9e1dd..535b34f92b 100644
--- a/esp32c6-lp/src/lp_i2c0/int_ena.rs
+++ b/esp32c6-lp/src/lp_i2c0/int_ena.rs
@@ -152,46 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/int_raw.rs b/esp32c6-lp/src/lp_i2c0/int_raw.rs
index 1ac9726d40..cd92338ced 100644
--- a/esp32c6-lp/src/lp_i2c0/int_raw.rs
+++ b/esp32c6-lp/src/lp_i2c0/int_raw.rs
@@ -118,46 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32c6-lp/src/lp_i2c0/int_st.rs b/esp32c6-lp/src/lp_i2c0/int_st.rs
index 1ffb4021ac..3ca3ab4a2e 100644
--- a/esp32c6-lp/src/lp_i2c0/int_st.rs
+++ b/esp32c6-lp/src/lp_i2c0/int_st.rs
@@ -118,46 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of captured I2C communication events\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6-lp/src/lp_i2c0/rxfifo_start_addr.rs b/esp32c6-lp/src/lp_i2c0/rxfifo_start_addr.rs
index 634e8c8360..be2fa3cb09 100644
--- a/esp32c6-lp/src/lp_i2c0/rxfifo_start_addr.rs
+++ b/esp32c6-lp/src/lp_i2c0/rxfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXFIFO_START_ADDR")
-            .field(
-                "rxfifo_start_addr",
-                &format_args!("{}", self.rxfifo_start_addr().bits()),
-            )
+            .field("rxfifo_start_addr", &self.rxfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C RXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for RXFIFO_START_ADDR_SPEC {
diff --git a/esp32c6-lp/src/lp_i2c0/scl_high_period.rs b/esp32c6-lp/src/lp_i2c0/scl_high_period.rs
index f8a536137d..d5ba861338 100644
--- a/esp32c6-lp/src/lp_i2c0/scl_high_period.rs
+++ b/esp32c6-lp/src/lp_i2c0/scl_high_period.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH_PERIOD")
-            .field(
-                "scl_high_period",
-                &format_args!("{}", self.scl_high_period().bits()),
-            )
-            .field(
-                "scl_wait_high_period",
-                &format_args!("{}", self.scl_wait_high_period().bits()),
-            )
+            .field("scl_high_period", &self.scl_high_period())
+            .field("scl_wait_high_period", &self.scl_wait_high_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/scl_low_period.rs b/esp32c6-lp/src/lp_i2c0/scl_low_period.rs
index bb4cd05e6d..c75461f0c7 100644
--- a/esp32c6-lp/src/lp_i2c0/scl_low_period.rs
+++ b/esp32c6-lp/src/lp_i2c0/scl_low_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW_PERIOD")
-            .field(
-                "scl_low_period",
-                &format_args!("{}", self.scl_low_period().bits()),
-            )
+            .field("scl_low_period", &self.scl_low_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/scl_main_st_time_out.rs b/esp32c6-lp/src/lp_i2c0/scl_main_st_time_out.rs
index 7c392d273a..99069d3ce8 100644
--- a/esp32c6-lp/src/lp_i2c0/scl_main_st_time_out.rs
+++ b/esp32c6-lp/src/lp_i2c0/scl_main_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_MAIN_ST_TIME_OUT")
-            .field(
-                "scl_main_st_to_i2c",
-                &format_args!("{}", self.scl_main_st_to_i2c().bits()),
-            )
+            .field("scl_main_st_to_i2c", &self.scl_main_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_MAIN_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/scl_rstart_setup.rs b/esp32c6-lp/src/lp_i2c0/scl_rstart_setup.rs
index 5f61d4fc91..63ddddc0f2 100644
--- a/esp32c6-lp/src/lp_i2c0/scl_rstart_setup.rs
+++ b/esp32c6-lp/src/lp_i2c0/scl_rstart_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_RSTART_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_RSTART_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/scl_sp_conf.rs b/esp32c6-lp/src/lp_i2c0/scl_sp_conf.rs
index e3cdc353bf..492452e245 100644
--- a/esp32c6-lp/src/lp_i2c0/scl_sp_conf.rs
+++ b/esp32c6-lp/src/lp_i2c0/scl_sp_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_SP_CONF")
-            .field(
-                "scl_rst_slv_en",
-                &format_args!("{}", self.scl_rst_slv_en().bit()),
-            )
-            .field(
-                "scl_rst_slv_num",
-                &format_args!("{}", self.scl_rst_slv_num().bits()),
-            )
-            .field("scl_pd_en", &format_args!("{}", self.scl_pd_en().bit()))
-            .field("sda_pd_en", &format_args!("{}", self.sda_pd_en().bit()))
+            .field("scl_rst_slv_en", &self.scl_rst_slv_en())
+            .field("scl_rst_slv_num", &self.scl_rst_slv_num())
+            .field("scl_pd_en", &self.scl_pd_en())
+            .field("sda_pd_en", &self.sda_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_SP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/scl_st_time_out.rs b/esp32c6-lp/src/lp_i2c0/scl_st_time_out.rs
index ba02a4a885..e56dd94c72 100644
--- a/esp32c6-lp/src/lp_i2c0/scl_st_time_out.rs
+++ b/esp32c6-lp/src/lp_i2c0/scl_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_ST_TIME_OUT")
-            .field(
-                "scl_st_to_i2c",
-                &format_args!("{}", self.scl_st_to_i2c().bits()),
-            )
+            .field("scl_st_to_i2c", &self.scl_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The threshold value of SCL_FSM state unchanged period. It should be o more than 23"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/scl_start_hold.rs b/esp32c6-lp/src/lp_i2c0/scl_start_hold.rs
index eaa7d6ef78..073d03f4ca 100644
--- a/esp32c6-lp/src/lp_i2c0/scl_start_hold.rs
+++ b/esp32c6-lp/src/lp_i2c0/scl_start_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/scl_stop_hold.rs b/esp32c6-lp/src/lp_i2c0/scl_stop_hold.rs
index edfbb10e29..3a115f7912 100644
--- a/esp32c6-lp/src/lp_i2c0/scl_stop_hold.rs
+++ b/esp32c6-lp/src/lp_i2c0/scl_stop_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the delay after the STOP condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/scl_stop_setup.rs b/esp32c6-lp/src/lp_i2c0/scl_stop_setup.rs
index f231319c28..592044b6a2 100644
--- a/esp32c6-lp/src/lp_i2c0/scl_stop_setup.rs
+++ b/esp32c6-lp/src/lp_i2c0/scl_stop_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/sda_hold.rs b/esp32c6-lp/src/lp_i2c0/sda_hold.rs
index b16485e33b..817872197e 100644
--- a/esp32c6-lp/src/lp_i2c0/sda_hold.rs
+++ b/esp32c6-lp/src/lp_i2c0/sda_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time to hold the data after the negative edge of SCL, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/sda_sample.rs b/esp32c6-lp/src/lp_i2c0/sda_sample.rs
index 5a56fc1aa2..a8bd733614 100644
--- a/esp32c6-lp/src/lp_i2c0/sda_sample.rs
+++ b/esp32c6-lp/src/lp_i2c0/sda_sample.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_SAMPLE")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SDA is sampled, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/sr.rs b/esp32c6-lp/src/lp_i2c0/sr.rs
index b12f9fe5e7..12408b7b23 100644
--- a/esp32c6-lp/src/lp_i2c0/sr.rs
+++ b/esp32c6-lp/src/lp_i2c0/sr.rs
@@ -55,28 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR")
-            .field("resp_rec", &format_args!("{}", self.resp_rec().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field(
-                "scl_main_state_last",
-                &format_args!("{}", self.scl_main_state_last().bits()),
-            )
-            .field(
-                "scl_state_last",
-                &format_args!("{}", self.scl_state_last().bits()),
-            )
+            .field("resp_rec", &self.resp_rec())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("scl_main_state_last", &self.scl_main_state_last())
+            .field("scl_state_last", &self.scl_state_last())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Describe I2C work status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SR_SPEC;
 impl crate::RegisterSpec for SR_SPEC {
diff --git a/esp32c6-lp/src/lp_i2c0/to.rs b/esp32c6-lp/src/lp_i2c0/to.rs
index 92f73cdd2b..cf95ff843d 100644
--- a/esp32c6-lp/src/lp_i2c0/to.rs
+++ b/esp32c6-lp/src/lp_i2c0/to.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO")
-            .field(
-                "time_out_value",
-                &format_args!("{}", self.time_out_value().bits()),
-            )
-            .field("time_out_en", &format_args!("{}", self.time_out_en().bit()))
+            .field("time_out_value", &self.time_out_value())
+            .field("time_out_en", &self.time_out_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to configure the timeout for receiving a data bit in APB clock cycles."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c0/txfifo_start_addr.rs b/esp32c6-lp/src/lp_i2c0/txfifo_start_addr.rs
index 8df0b6828e..c7cd4f0ea5 100644
--- a/esp32c6-lp/src/lp_i2c0/txfifo_start_addr.rs
+++ b/esp32c6-lp/src/lp_i2c0/txfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXFIFO_START_ADDR")
-            .field(
-                "txfifo_start_addr",
-                &format_args!("{}", self.txfifo_start_addr().bits()),
-            )
+            .field("txfifo_start_addr", &self.txfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C TXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for TXFIFO_START_ADDR_SPEC {
diff --git a/esp32c6-lp/src/lp_i2c_ana_mst/ana_conf1.rs b/esp32c6-lp/src/lp_i2c_ana_mst/ana_conf1.rs
index 9efc637cf0..48e8357f03 100644
--- a/esp32c6-lp/src/lp_i2c_ana_mst/ana_conf1.rs
+++ b/esp32c6-lp/src/lp_i2c_ana_mst/ana_conf1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ANA_CONF1")
             .field(
                 "lp_i2c_ana_mast_ana_conf1",
-                &format_args!("{}", self.lp_i2c_ana_mast_ana_conf1().bits()),
+                &self.lp_i2c_ana_mast_ana_conf1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ANA_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c_ana_mst/date.rs b/esp32c6-lp/src/lp_i2c_ana_mst/date.rs
index 7c66e94455..4109f0a3ad 100644
--- a/esp32c6-lp/src/lp_i2c_ana_mst/date.rs
+++ b/esp32c6-lp/src/lp_i2c_ana_mst/date.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("DATE")
             .field(
                 "lp_i2c_ana_mast_i2c_mat_date",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c_mat_date().bits()),
+                &self.lp_i2c_ana_mast_i2c_mat_date(),
             )
             .field(
                 "lp_i2c_ana_mast_i2c_mat_clk_en",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c_mat_clk_en().bit()),
+                &self.lp_i2c_ana_mast_i2c_mat_clk_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c_ana_mst/device_en.rs b/esp32c6-lp/src/lp_i2c_ana_mst/device_en.rs
index c05f64b881..31fe3030d3 100644
--- a/esp32c6-lp/src/lp_i2c_ana_mst/device_en.rs
+++ b/esp32c6-lp/src/lp_i2c_ana_mst/device_en.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DEVICE_EN")
             .field(
                 "lp_i2c_ana_mast_i2c_device_en",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c_device_en().bits()),
+                &self.lp_i2c_ana_mast_i2c_device_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEVICE_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c_ana_mst/i2c0_conf.rs b/esp32c6-lp/src/lp_i2c_ana_mst/i2c0_conf.rs
index c1e1654991..b504d4fc7e 100644
--- a/esp32c6-lp/src/lp_i2c_ana_mst/i2c0_conf.rs
+++ b/esp32c6-lp/src/lp_i2c_ana_mst/i2c0_conf.rs
@@ -26,21 +26,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("I2C0_CONF")
             .field(
                 "lp_i2c_ana_mast_i2c0_conf",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c0_conf().bits()),
+                &self.lp_i2c_ana_mast_i2c0_conf(),
             )
             .field(
                 "lp_i2c_ana_mast_i2c0_status",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c0_status().bits()),
+                &self.lp_i2c_ana_mast_i2c0_status(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C0_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c_ana_mst/i2c0_ctrl.rs b/esp32c6-lp/src/lp_i2c_ana_mst/i2c0_ctrl.rs
index 61a0db6f65..65287a20f8 100644
--- a/esp32c6-lp/src/lp_i2c_ana_mst/i2c0_ctrl.rs
+++ b/esp32c6-lp/src/lp_i2c_ana_mst/i2c0_ctrl.rs
@@ -26,21 +26,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("I2C0_CTRL")
             .field(
                 "lp_i2c_ana_mast_i2c0_ctrl",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c0_ctrl().bits()),
+                &self.lp_i2c_ana_mast_i2c0_ctrl(),
             )
             .field(
                 "lp_i2c_ana_mast_i2c0_busy",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c0_busy().bit()),
+                &self.lp_i2c_ana_mast_i2c0_busy(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C0_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:24 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c_ana_mst/i2c0_data.rs b/esp32c6-lp/src/lp_i2c_ana_mst/i2c0_data.rs
index 07adc6c062..cef2eefbac 100644
--- a/esp32c6-lp/src/lp_i2c_ana_mst/i2c0_data.rs
+++ b/esp32c6-lp/src/lp_i2c_ana_mst/i2c0_data.rs
@@ -35,25 +35,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("I2C0_DATA")
             .field(
                 "lp_i2c_ana_mast_i2c0_rdata",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c0_rdata().bits()),
+                &self.lp_i2c_ana_mast_i2c0_rdata(),
             )
             .field(
                 "lp_i2c_ana_mast_i2c0_clk_sel",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c0_clk_sel().bits()),
+                &self.lp_i2c_ana_mast_i2c0_clk_sel(),
             )
             .field(
                 "lp_i2c_ana_mast_i2c_mst_sel",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c_mst_sel().bit()),
+                &self.lp_i2c_ana_mast_i2c_mst_sel(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C0_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:10 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_i2c_ana_mst/nouse.rs b/esp32c6-lp/src/lp_i2c_ana_mst/nouse.rs
index 1de8eb0a26..55b1fab3cf 100644
--- a/esp32c6-lp/src/lp_i2c_ana_mst/nouse.rs
+++ b/esp32c6-lp/src/lp_i2c_ana_mst/nouse.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("NOUSE")
             .field(
                 "lp_i2c_ana_mast_i2c_mst_nouse",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c_mst_nouse().bits()),
+                &self.lp_i2c_ana_mast_i2c_mst_nouse(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NOUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_io/date.rs b/esp32c6-lp/src/lp_io/date.rs
index 64035685b3..cdfe23b8bb 100644
--- a/esp32c6-lp/src/lp_io/date.rs
+++ b/esp32c6-lp/src/lp_io/date.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("lp_io_date", &format_args!("{}", self.lp_io_date().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("lp_io_date", &self.lp_io_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_io/enable.rs b/esp32c6-lp/src/lp_io/enable.rs
index 7e9bfa5c56..d9bc9b64f9 100644
--- a/esp32c6-lp/src/lp_io/enable.rs
+++ b/esp32c6-lp/src/lp_io/enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE")
-            .field("enable", &format_args!("{}", self.enable().bits()))
+            .field("enable", &self.enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - set lp gpio output data"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_io/gpio.rs b/esp32c6-lp/src/lp_io/gpio.rs
index f38ae32646..a997a3e3c8 100644
--- a/esp32c6-lp/src/lp_io/gpio.rs
+++ b/esp32c6-lp/src/lp_io/gpio.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("fun_sel", &self.fun_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_io/in_.rs b/esp32c6-lp/src/lp_io/in_.rs
index 52e0db6ac2..68c2177b0b 100644
--- a/esp32c6-lp/src/lp_io/in_.rs
+++ b/esp32c6-lp/src/lp_io/in_.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN")
-            .field("data_next", &format_args!("{}", self.data_next().bits()))
+            .field("data_next", &self.data_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SPEC;
 impl crate::RegisterSpec for IN_SPEC {
diff --git a/esp32c6-lp/src/lp_io/out.rs b/esp32c6-lp/src/lp_io/out.rs
index f536d5dfca..eb022776a3 100644
--- a/esp32c6-lp/src/lp_io/out.rs
+++ b/esp32c6-lp/src/lp_io/out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT")
-            .field("out_data", &format_args!("{}", self.out_data().bits()))
+            .field("out_data", &self.out_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - set lp gpio output data"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_io/pin.rs b/esp32c6-lp/src/lp_io/pin.rs
index 87ab4fc614..0848503ab7 100644
--- a/esp32c6-lp/src/lp_io/pin.rs
+++ b/esp32c6-lp/src/lp_io/pin.rs
@@ -55,26 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN")
-            .field(
-                "sync_bypass",
-                &format_args!("{}", self.sync_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("sync_bypass", &self.sync_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - need des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_io/status.rs b/esp32c6-lp/src/lp_io/status.rs
index de8abe30b5..6826e6ffe5 100644
--- a/esp32c6-lp/src/lp_io/status.rs
+++ b/esp32c6-lp/src/lp_io/status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("interrupt", &format_args!("{}", self.interrupt().bits()))
+            .field("interrupt", &self.interrupt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - set lp gpio output data"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_io/status_int.rs b/esp32c6-lp/src/lp_io/status_int.rs
index 41c392e99d..cb2706b59c 100644
--- a/esp32c6-lp/src/lp_io/status_int.rs
+++ b/esp32c6-lp/src/lp_io/status_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_INT")
-            .field("next", &format_args!("{}", self.next().bits()))
+            .field("next", &self.next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_INT_SPEC;
 impl crate::RegisterSpec for STATUS_INT_SPEC {
diff --git a/esp32c6-lp/src/lp_peri/bus_timeout.rs b/esp32c6-lp/src/lp_peri/bus_timeout.rs
index c9162357b7..559e19f4c6 100644
--- a/esp32c6-lp/src/lp_peri/bus_timeout.rs
+++ b/esp32c6-lp/src/lp_peri/bus_timeout.rs
@@ -28,23 +28,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMEOUT")
-            .field(
-                "lp_peri_timeout_thres",
-                &format_args!("{}", self.lp_peri_timeout_thres().bits()),
-            )
+            .field("lp_peri_timeout_thres", &self.lp_peri_timeout_thres())
             .field(
                 "lp_peri_timeout_protect_en",
-                &format_args!("{}", self.lp_peri_timeout_protect_en().bit()),
+                &self.lp_peri_timeout_protect_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMEOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 14:29 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_peri/bus_timeout_addr.rs b/esp32c6-lp/src/lp_peri/bus_timeout_addr.rs
index f90baac504..6527db51bb 100644
--- a/esp32c6-lp/src/lp_peri/bus_timeout_addr.rs
+++ b/esp32c6-lp/src/lp_peri/bus_timeout_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMEOUT_ADDR")
-            .field(
-                "lp_peri_timeout_addr",
-                &format_args!("{}", self.lp_peri_timeout_addr().bits()),
-            )
+            .field("lp_peri_timeout_addr", &self.lp_peri_timeout_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMEOUT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_timeout_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUS_TIMEOUT_ADDR_SPEC;
 impl crate::RegisterSpec for BUS_TIMEOUT_ADDR_SPEC {
diff --git a/esp32c6-lp/src/lp_peri/bus_timeout_uid.rs b/esp32c6-lp/src/lp_peri/bus_timeout_uid.rs
index d8620b1d01..43079dcad0 100644
--- a/esp32c6-lp/src/lp_peri/bus_timeout_uid.rs
+++ b/esp32c6-lp/src/lp_peri/bus_timeout_uid.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMEOUT_UID")
-            .field(
-                "lp_peri_timeout_uid",
-                &format_args!("{}", self.lp_peri_timeout_uid().bits()),
-            )
+            .field("lp_peri_timeout_uid", &self.lp_peri_timeout_uid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMEOUT_UID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_timeout_uid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUS_TIMEOUT_UID_SPEC;
 impl crate::RegisterSpec for BUS_TIMEOUT_UID_SPEC {
diff --git a/esp32c6-lp/src/lp_peri/clk_en.rs b/esp32c6-lp/src/lp_peri/clk_en.rs
index f8eddb7030..371447fbef 100644
--- a/esp32c6-lp/src/lp_peri/clk_en.rs
+++ b/esp32c6-lp/src/lp_peri/clk_en.rs
@@ -89,42 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EN")
-            .field(
-                "lp_touch_ck_en",
-                &format_args!("{}", self.lp_touch_ck_en().bit()),
-            )
-            .field("rng_ck_en", &format_args!("{}", self.rng_ck_en().bit()))
-            .field(
-                "otp_dbg_ck_en",
-                &format_args!("{}", self.otp_dbg_ck_en().bit()),
-            )
-            .field(
-                "lp_uart_ck_en",
-                &format_args!("{}", self.lp_uart_ck_en().bit()),
-            )
-            .field("lp_io_ck_en", &format_args!("{}", self.lp_io_ck_en().bit()))
-            .field(
-                "lp_ext_i2c_ck_en",
-                &format_args!("{}", self.lp_ext_i2c_ck_en().bit()),
-            )
-            .field(
-                "lp_ana_i2c_ck_en",
-                &format_args!("{}", self.lp_ana_i2c_ck_en().bit()),
-            )
-            .field("efuse_ck_en", &format_args!("{}", self.efuse_ck_en().bit()))
-            .field(
-                "lp_cpu_ck_en",
-                &format_args!("{}", self.lp_cpu_ck_en().bit()),
-            )
+            .field("lp_touch_ck_en", &self.lp_touch_ck_en())
+            .field("rng_ck_en", &self.rng_ck_en())
+            .field("otp_dbg_ck_en", &self.otp_dbg_ck_en())
+            .field("lp_uart_ck_en", &self.lp_uart_ck_en())
+            .field("lp_io_ck_en", &self.lp_io_ck_en())
+            .field("lp_ext_i2c_ck_en", &self.lp_ext_i2c_ck_en())
+            .field("lp_ana_i2c_ck_en", &self.lp_ana_i2c_ck_en())
+            .field("efuse_ck_en", &self.efuse_ck_en())
+            .field("lp_cpu_ck_en", &self.lp_cpu_ck_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 23 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_peri/cpu.rs b/esp32c6-lp/src/lp_peri/cpu.rs
index bcb33042d9..ea8c30e62d 100644
--- a/esp32c6-lp/src/lp_peri/cpu.rs
+++ b/esp32c6-lp/src/lp_peri/cpu.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU")
-            .field(
-                "lpcore_dbgm_unavaliable",
-                &format_args!("{}", self.lpcore_dbgm_unavaliable().bit()),
-            )
+            .field("lpcore_dbgm_unavaliable", &self.lpcore_dbgm_unavaliable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_peri/date.rs b/esp32c6-lp/src/lp_peri/date.rs
index 6cd7bea0a5..9e433a72d2 100644
--- a/esp32c6-lp/src/lp_peri/date.rs
+++ b/esp32c6-lp/src/lp_peri/date.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "lpperi_date",
-                &format_args!("{}", self.lpperi_date().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("lpperi_date", &self.lpperi_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_peri/interrupt_source.rs b/esp32c6-lp/src/lp_peri/interrupt_source.rs
index 3a58e713a5..079ad23d59 100644
--- a/esp32c6-lp/src/lp_peri/interrupt_source.rs
+++ b/esp32c6-lp/src/lp_peri/interrupt_source.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT_SOURCE")
-            .field(
-                "lp_interrupt_source",
-                &format_args!("{}", self.lp_interrupt_source().bits()),
-            )
+            .field("lp_interrupt_source", &self.lp_interrupt_source())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_SOURCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt_source::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERRUPT_SOURCE_SPEC;
 impl crate::RegisterSpec for INTERRUPT_SOURCE_SPEC {
diff --git a/esp32c6-lp/src/lp_peri/mem_ctrl.rs b/esp32c6-lp/src/lp_peri/mem_ctrl.rs
index 19f827781a..32a31f41d6 100644
--- a/esp32c6-lp/src/lp_peri/mem_ctrl.rs
+++ b/esp32c6-lp/src/lp_peri/mem_ctrl.rs
@@ -46,31 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CTRL")
-            .field(
-                "uart_wakeup_flag",
-                &format_args!("{}", self.uart_wakeup_flag().bit()),
-            )
-            .field(
-                "uart_wakeup_en",
-                &format_args!("{}", self.uart_wakeup_en().bit()),
-            )
-            .field(
-                "uart_mem_force_pd",
-                &format_args!("{}", self.uart_mem_force_pd().bit()),
-            )
-            .field(
-                "uart_mem_force_pu",
-                &format_args!("{}", self.uart_mem_force_pu().bit()),
-            )
+            .field("uart_wakeup_flag", &self.uart_wakeup_flag())
+            .field("uart_wakeup_en", &self.uart_wakeup_en())
+            .field("uart_mem_force_pd", &self.uart_mem_force_pd())
+            .field("uart_mem_force_pu", &self.uart_mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_peri/reset_en.rs b/esp32c6-lp/src/lp_peri/reset_en.rs
index 37a0056097..a12a5fb0b6 100644
--- a/esp32c6-lp/src/lp_peri/reset_en.rs
+++ b/esp32c6-lp/src/lp_peri/reset_en.rs
@@ -75,43 +75,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET_EN")
-            .field(
-                "lp_touch_reset_en",
-                &format_args!("{}", self.lp_touch_reset_en().bit()),
-            )
-            .field(
-                "otp_dbg_reset_en",
-                &format_args!("{}", self.otp_dbg_reset_en().bit()),
-            )
-            .field(
-                "lp_uart_reset_en",
-                &format_args!("{}", self.lp_uart_reset_en().bit()),
-            )
-            .field(
-                "lp_io_reset_en",
-                &format_args!("{}", self.lp_io_reset_en().bit()),
-            )
-            .field(
-                "lp_ext_i2c_reset_en",
-                &format_args!("{}", self.lp_ext_i2c_reset_en().bit()),
-            )
-            .field(
-                "lp_ana_i2c_reset_en",
-                &format_args!("{}", self.lp_ana_i2c_reset_en().bit()),
-            )
-            .field(
-                "efuse_reset_en",
-                &format_args!("{}", self.efuse_reset_en().bit()),
-            )
+            .field("lp_touch_reset_en", &self.lp_touch_reset_en())
+            .field("otp_dbg_reset_en", &self.otp_dbg_reset_en())
+            .field("lp_uart_reset_en", &self.lp_uart_reset_en())
+            .field("lp_io_reset_en", &self.lp_io_reset_en())
+            .field("lp_ext_i2c_reset_en", &self.lp_ext_i2c_reset_en())
+            .field("lp_ana_i2c_reset_en", &self.lp_ana_i2c_reset_en())
+            .field("efuse_reset_en", &self.efuse_reset_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 23 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_peri/rng_data.rs b/esp32c6-lp/src/lp_peri/rng_data.rs
index 713145ebb6..13f1db3a76 100644
--- a/esp32c6-lp/src/lp_peri/rng_data.rs
+++ b/esp32c6-lp/src/lp_peri/rng_data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RNG_DATA")
-            .field("rnd_data", &format_args!("{}", self.rnd_data().bits()))
+            .field("rnd_data", &self.rnd_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RNG_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RNG_DATA_SPEC;
 impl crate::RegisterSpec for RNG_DATA_SPEC {
diff --git a/esp32c6-lp/src/lp_tee/clock_gate.rs b/esp32c6-lp/src/lp_tee/clock_gate.rs
index b2c147f4a9..0c07ea99d2 100644
--- a/esp32c6-lp/src/lp_tee/clock_gate.rs
+++ b/esp32c6-lp/src/lp_tee/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_clk_en"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_tee/date.rs b/esp32c6-lp/src/lp_tee/date.rs
index add181b414..d755558c2d 100644
--- a/esp32c6-lp/src/lp_tee/date.rs
+++ b/esp32c6-lp/src/lp_tee/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6-lp/src/lp_tee/force_acc_hp.rs b/esp32c6-lp/src/lp_tee/force_acc_hp.rs
index 49422ac57d..fc6756faf1 100644
--- a/esp32c6-lp/src/lp_tee/force_acc_hp.rs
+++ b/esp32c6-lp/src/lp_tee/force_acc_hp.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("FORCE_ACC_HP")
             .field(
                 "lp_aon_force_acc_hpmem_en",
-                &format_args!("{}", self.lp_aon_force_acc_hpmem_en().bit()),
+                &self.lp_aon_force_acc_hpmem_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FORCE_ACC_HP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_tee/m_mode_ctrl.rs b/esp32c6-lp/src/lp_tee/m_mode_ctrl.rs
index 62e16866e7..34a691f102 100644
--- a/esp32c6-lp/src/lp_tee/m_mode_ctrl.rs
+++ b/esp32c6-lp/src/lp_tee/m_mode_ctrl.rs
@@ -100,16 +100,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("M_MODE_CTRL")
-            .field("mode", &format_args!("{}", self.mode().bits()))
+            .field("mode", &self.mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MODE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_timer/date.rs b/esp32c6-lp/src/lp_timer/date.rs
index d47a89ee4b..e9890af6e1 100644
--- a/esp32c6-lp/src/lp_timer/date.rs
+++ b/esp32c6-lp/src/lp_timer/date.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("date", &self.date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_timer/int_ena.rs b/esp32c6-lp/src/lp_timer/int_ena.rs
index 92ce086df1..f27ed7c86e 100644
--- a/esp32c6-lp/src/lp_timer/int_ena.rs
+++ b/esp32c6-lp/src/lp_timer/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("overflow", &format_args!("{}", self.overflow().bit()))
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("overflow", &self.overflow())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_timer/int_raw.rs b/esp32c6-lp/src/lp_timer/int_raw.rs
index a18d0a9b31..a5598fb406 100644
--- a/esp32c6-lp/src/lp_timer/int_raw.rs
+++ b/esp32c6-lp/src/lp_timer/int_raw.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("overflow", &format_args!("{}", self.overflow().bit()))
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("overflow", &self.overflow())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_timer/int_st.rs b/esp32c6-lp/src/lp_timer/int_st.rs
index 101196ba9b..ee18087a3c 100644
--- a/esp32c6-lp/src/lp_timer/int_st.rs
+++ b/esp32c6-lp/src/lp_timer/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("overflow", &format_args!("{}", self.overflow().bit()))
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("overflow", &self.overflow())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6-lp/src/lp_timer/lp_int_ena.rs b/esp32c6-lp/src/lp_timer/lp_int_ena.rs
index 5ea363c710..91e11e2772 100644
--- a/esp32c6-lp/src/lp_timer/lp_int_ena.rs
+++ b/esp32c6-lp/src/lp_timer/lp_int_ena.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ENA")
-            .field(
-                "main_timer_overflow",
-                &format_args!("{}", self.main_timer_overflow().bit()),
-            )
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
+            .field("main_timer_overflow", &self.main_timer_overflow())
+            .field("main_timer", &self.main_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_timer/lp_int_raw.rs b/esp32c6-lp/src/lp_timer/lp_int_raw.rs
index 6df03d55aa..0c01b2cf70 100644
--- a/esp32c6-lp/src/lp_timer/lp_int_raw.rs
+++ b/esp32c6-lp/src/lp_timer/lp_int_raw.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_RAW")
-            .field(
-                "main_timer_overflow",
-                &format_args!("{}", self.main_timer_overflow().bit()),
-            )
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
+            .field("main_timer_overflow", &self.main_timer_overflow())
+            .field("main_timer", &self.main_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_timer/lp_int_st.rs b/esp32c6-lp/src/lp_timer/lp_int_st.rs
index ca21a1cf4d..b109777cd5 100644
--- a/esp32c6-lp/src/lp_timer/lp_int_st.rs
+++ b/esp32c6-lp/src/lp_timer/lp_int_st.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ST")
-            .field(
-                "main_timer_overflow",
-                &format_args!("{}", self.main_timer_overflow().bit()),
-            )
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
+            .field("main_timer_overflow", &self.main_timer_overflow())
+            .field("main_timer", &self.main_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_INT_ST_SPEC;
 impl crate::RegisterSpec for LP_INT_ST_SPEC {
diff --git a/esp32c6-lp/src/lp_timer/main_buf0_high.rs b/esp32c6-lp/src/lp_timer/main_buf0_high.rs
index 7ec6b260aa..4545617b27 100644
--- a/esp32c6-lp/src/lp_timer/main_buf0_high.rs
+++ b/esp32c6-lp/src/lp_timer/main_buf0_high.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF0_HIGH")
-            .field(
-                "main_timer_buf0_high",
-                &format_args!("{}", self.main_timer_buf0_high().bits()),
-            )
+            .field("main_timer_buf0_high", &self.main_timer_buf0_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF0_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf0_high::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF0_HIGH_SPEC;
 impl crate::RegisterSpec for MAIN_BUF0_HIGH_SPEC {
diff --git a/esp32c6-lp/src/lp_timer/main_buf0_low.rs b/esp32c6-lp/src/lp_timer/main_buf0_low.rs
index b3e2efd010..9c176ef6e3 100644
--- a/esp32c6-lp/src/lp_timer/main_buf0_low.rs
+++ b/esp32c6-lp/src/lp_timer/main_buf0_low.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF0_LOW")
-            .field(
-                "main_timer_buf0_low",
-                &format_args!("{}", self.main_timer_buf0_low().bits()),
-            )
+            .field("main_timer_buf0_low", &self.main_timer_buf0_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF0_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf0_low::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF0_LOW_SPEC;
 impl crate::RegisterSpec for MAIN_BUF0_LOW_SPEC {
diff --git a/esp32c6-lp/src/lp_timer/main_buf1_high.rs b/esp32c6-lp/src/lp_timer/main_buf1_high.rs
index 343bec706f..3fd0b05256 100644
--- a/esp32c6-lp/src/lp_timer/main_buf1_high.rs
+++ b/esp32c6-lp/src/lp_timer/main_buf1_high.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF1_HIGH")
-            .field(
-                "main_timer_buf1_high",
-                &format_args!("{}", self.main_timer_buf1_high().bits()),
-            )
+            .field("main_timer_buf1_high", &self.main_timer_buf1_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF1_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf1_high::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF1_HIGH_SPEC;
 impl crate::RegisterSpec for MAIN_BUF1_HIGH_SPEC {
diff --git a/esp32c6-lp/src/lp_timer/main_buf1_low.rs b/esp32c6-lp/src/lp_timer/main_buf1_low.rs
index e9cb954df6..020cfc0659 100644
--- a/esp32c6-lp/src/lp_timer/main_buf1_low.rs
+++ b/esp32c6-lp/src/lp_timer/main_buf1_low.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF1_LOW")
-            .field(
-                "main_timer_buf1_low",
-                &format_args!("{}", self.main_timer_buf1_low().bits()),
-            )
+            .field("main_timer_buf1_low", &self.main_timer_buf1_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF1_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf1_low::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF1_LOW_SPEC;
 impl crate::RegisterSpec for MAIN_BUF1_LOW_SPEC {
diff --git a/esp32c6-lp/src/lp_timer/tar0_high.rs b/esp32c6-lp/src/lp_timer/tar0_high.rs
index ba43f1ec62..abf6de0468 100644
--- a/esp32c6-lp/src/lp_timer/tar0_high.rs
+++ b/esp32c6-lp/src/lp_timer/tar0_high.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TAR0_HIGH")
-            .field(
-                "main_timer_tar_high0",
-                &format_args!("{}", self.main_timer_tar_high0().bits()),
-            )
+            .field("main_timer_tar_high0", &self.main_timer_tar_high0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TAR0_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_timer/tar0_low.rs b/esp32c6-lp/src/lp_timer/tar0_low.rs
index 131d1c04d8..fe2273147d 100644
--- a/esp32c6-lp/src/lp_timer/tar0_low.rs
+++ b/esp32c6-lp/src/lp_timer/tar0_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TAR0_LOW")
-            .field(
-                "main_timer_tar_low0",
-                &format_args!("{}", self.main_timer_tar_low0().bits()),
-            )
+            .field("main_timer_tar_low0", &self.main_timer_tar_low0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TAR0_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_timer/tar1_high.rs b/esp32c6-lp/src/lp_timer/tar1_high.rs
index b3005a0f94..730d601d28 100644
--- a/esp32c6-lp/src/lp_timer/tar1_high.rs
+++ b/esp32c6-lp/src/lp_timer/tar1_high.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TAR1_HIGH")
-            .field(
-                "main_timer_tar_high1",
-                &format_args!("{}", self.main_timer_tar_high1().bits()),
-            )
+            .field("main_timer_tar_high1", &self.main_timer_tar_high1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TAR1_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_timer/tar1_low.rs b/esp32c6-lp/src/lp_timer/tar1_low.rs
index 78226f1ebc..1a74b66e78 100644
--- a/esp32c6-lp/src/lp_timer/tar1_low.rs
+++ b/esp32c6-lp/src/lp_timer/tar1_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TAR1_LOW")
-            .field(
-                "main_timer_tar_low1",
-                &format_args!("{}", self.main_timer_tar_low1().bits()),
-            )
+            .field("main_timer_tar_low1", &self.main_timer_tar_low1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TAR1_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_timer/update.rs b/esp32c6-lp/src/lp_timer/update.rs
index 9f49d41d18..b0cb0a2d30 100644
--- a/esp32c6-lp/src/lp_timer/update.rs
+++ b/esp32c6-lp/src/lp_timer/update.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE")
-            .field(
-                "main_timer_xtal_off",
-                &format_args!("{}", self.main_timer_xtal_off().bit()),
-            )
-            .field(
-                "main_timer_sys_stall",
-                &format_args!("{}", self.main_timer_sys_stall().bit()),
-            )
-            .field(
-                "main_timer_sys_rst",
-                &format_args!("{}", self.main_timer_sys_rst().bit()),
-            )
+            .field("main_timer_xtal_off", &self.main_timer_xtal_off())
+            .field("main_timer_sys_stall", &self.main_timer_sys_stall())
+            .field("main_timer_sys_rst", &self.main_timer_sys_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/afifo_status.rs b/esp32c6-lp/src/lp_uart/afifo_status.rs
index 32a27a7eed..22f55103b7 100644
--- a/esp32c6-lp/src/lp_uart/afifo_status.rs
+++ b/esp32c6-lp/src/lp_uart/afifo_status.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AFIFO_STATUS")
-            .field(
-                "tx_afifo_full",
-                &format_args!("{}", self.tx_afifo_full().bit()),
-            )
-            .field(
-                "tx_afifo_empty",
-                &format_args!("{}", self.tx_afifo_empty().bit()),
-            )
-            .field(
-                "rx_afifo_full",
-                &format_args!("{}", self.rx_afifo_full().bit()),
-            )
-            .field(
-                "rx_afifo_empty",
-                &format_args!("{}", self.rx_afifo_empty().bit()),
-            )
+            .field("tx_afifo_full", &self.tx_afifo_full())
+            .field("tx_afifo_empty", &self.tx_afifo_empty())
+            .field("rx_afifo_full", &self.rx_afifo_full())
+            .field("rx_afifo_empty", &self.rx_afifo_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART AFIFO Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`afifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for AFIFO_STATUS_SPEC {
diff --git a/esp32c6-lp/src/lp_uart/at_cmd_char_sync.rs b/esp32c6-lp/src/lp_uart/at_cmd_char_sync.rs
index 61d6f515b8..73181d6fdd 100644
--- a/esp32c6-lp/src/lp_uart/at_cmd_char_sync.rs
+++ b/esp32c6-lp/src/lp_uart/at_cmd_char_sync.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_CHAR_SYNC")
-            .field(
-                "at_cmd_char",
-                &format_args!("{}", self.at_cmd_char().bits()),
-            )
-            .field("char_num", &format_args!("{}", self.char_num().bits()))
+            .field("at_cmd_char", &self.at_cmd_char())
+            .field("char_num", &self.char_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_CHAR_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/at_cmd_gaptout_sync.rs b/esp32c6-lp/src/lp_uart/at_cmd_gaptout_sync.rs
index 4c3bef3cde..6da82a6678 100644
--- a/esp32c6-lp/src/lp_uart/at_cmd_gaptout_sync.rs
+++ b/esp32c6-lp/src/lp_uart/at_cmd_gaptout_sync.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_GAPTOUT_SYNC")
-            .field(
-                "rx_gap_tout",
-                &format_args!("{}", self.rx_gap_tout().bits()),
-            )
+            .field("rx_gap_tout", &self.rx_gap_tout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_GAPTOUT_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the at_cmd chars."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/at_cmd_postcnt_sync.rs b/esp32c6-lp/src/lp_uart/at_cmd_postcnt_sync.rs
index 7489ff4b31..23ce0ca37d 100644
--- a/esp32c6-lp/src/lp_uart/at_cmd_postcnt_sync.rs
+++ b/esp32c6-lp/src/lp_uart/at_cmd_postcnt_sync.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_POSTCNT_SYNC")
-            .field(
-                "post_idle_num",
-                &format_args!("{}", self.post_idle_num().bits()),
-            )
+            .field("post_idle_num", &self.post_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_POSTCNT_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the last at_cmd and the next data."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/at_cmd_precnt_sync.rs b/esp32c6-lp/src/lp_uart/at_cmd_precnt_sync.rs
index e96ddde6d5..9b4dbd34ae 100644
--- a/esp32c6-lp/src/lp_uart/at_cmd_precnt_sync.rs
+++ b/esp32c6-lp/src/lp_uart/at_cmd_precnt_sync.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_PRECNT_SYNC")
-            .field(
-                "pre_idle_num",
-                &format_args!("{}", self.pre_idle_num().bits()),
-            )
+            .field("pre_idle_num", &self.pre_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_PRECNT_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first at_cmd is received by receiver."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/clk_conf.rs b/esp32c6-lp/src/lp_uart/clk_conf.rs
index f4d58f12dc..15db8ddbda 100644
--- a/esp32c6-lp/src/lp_uart/clk_conf.rs
+++ b/esp32c6-lp/src/lp_uart/clk_conf.rs
@@ -98,28 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bits()))
-            .field("sclk_en", &format_args!("{}", self.sclk_en().bit()))
-            .field("rst_core", &format_args!("{}", self.rst_core().bit()))
-            .field("tx_sclk_en", &format_args!("{}", self.tx_sclk_en().bit()))
-            .field("rx_sclk_en", &format_args!("{}", self.rx_sclk_en().bit()))
-            .field("tx_rst_core", &format_args!("{}", self.tx_rst_core().bit()))
-            .field("rx_rst_core", &format_args!("{}", self.rx_rst_core().bit()))
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_en", &self.sclk_en())
+            .field("rst_core", &self.rst_core())
+            .field("tx_sclk_en", &self.tx_sclk_en())
+            .field("rx_sclk_en", &self.rx_sclk_en())
+            .field("tx_rst_core", &self.tx_rst_core())
+            .field("rx_rst_core", &self.rx_rst_core())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/clkdiv_sync.rs b/esp32c6-lp/src/lp_uart/clkdiv_sync.rs
index 9b5485fec2..7bf406c6e5 100644
--- a/esp32c6-lp/src/lp_uart/clkdiv_sync.rs
+++ b/esp32c6-lp/src/lp_uart/clkdiv_sync.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKDIV_SYNC")
-            .field("clkdiv", &format_args!("{}", self.clkdiv().bits()))
-            .field(
-                "clkdiv_frag",
-                &format_args!("{}", self.clkdiv_frag().bits()),
-            )
+            .field("clkdiv", &self.clkdiv())
+            .field("clkdiv_frag", &self.clkdiv_frag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKDIV_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/conf0_sync.rs b/esp32c6-lp/src/lp_uart/conf0_sync.rs
index 0c0922ef82..d7766dc50e 100644
--- a/esp32c6-lp/src/lp_uart/conf0_sync.rs
+++ b/esp32c6-lp/src/lp_uart/conf0_sync.rs
@@ -143,36 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0_SYNC")
-            .field("parity", &format_args!("{}", self.parity().bit()))
-            .field("parity_en", &format_args!("{}", self.parity_en().bit()))
-            .field("bit_num", &format_args!("{}", self.bit_num().bits()))
-            .field(
-                "stop_bit_num",
-                &format_args!("{}", self.stop_bit_num().bits()),
-            )
-            .field("txd_brk", &format_args!("{}", self.txd_brk().bit()))
-            .field("loopback", &format_args!("{}", self.loopback().bit()))
-            .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit()))
-            .field("rxd_inv", &format_args!("{}", self.rxd_inv().bit()))
-            .field("txd_inv", &format_args!("{}", self.txd_inv().bit()))
-            .field(
-                "dis_rx_dat_ovf",
-                &format_args!("{}", self.dis_rx_dat_ovf().bit()),
-            )
-            .field("err_wr_mask", &format_args!("{}", self.err_wr_mask().bit()))
-            .field("mem_clk_en", &format_args!("{}", self.mem_clk_en().bit()))
-            .field("sw_rts", &format_args!("{}", self.sw_rts().bit()))
-            .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit()))
-            .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit()))
+            .field("parity", &self.parity())
+            .field("parity_en", &self.parity_en())
+            .field("bit_num", &self.bit_num())
+            .field("stop_bit_num", &self.stop_bit_num())
+            .field("txd_brk", &self.txd_brk())
+            .field("loopback", &self.loopback())
+            .field("tx_flow_en", &self.tx_flow_en())
+            .field("rxd_inv", &self.rxd_inv())
+            .field("txd_inv", &self.txd_inv())
+            .field("dis_rx_dat_ovf", &self.dis_rx_dat_ovf())
+            .field("err_wr_mask", &self.err_wr_mask())
+            .field("mem_clk_en", &self.mem_clk_en())
+            .field("sw_rts", &self.sw_rts())
+            .field("rxfifo_rst", &self.rxfifo_rst())
+            .field("txfifo_rst", &self.txfifo_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to configure the parity check mode."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/conf1.rs b/esp32c6-lp/src/lp_uart/conf1.rs
index 1c6045b655..dfab209c1d 100644
--- a/esp32c6-lp/src/lp_uart/conf1.rs
+++ b/esp32c6-lp/src/lp_uart/conf1.rs
@@ -80,29 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "rxfifo_full_thrhd",
-                &format_args!("{}", self.rxfifo_full_thrhd().bits()),
-            )
-            .field(
-                "txfifo_empty_thrhd",
-                &format_args!("{}", self.txfifo_empty_thrhd().bits()),
-            )
-            .field("cts_inv", &format_args!("{}", self.cts_inv().bit()))
-            .field("dsr_inv", &format_args!("{}", self.dsr_inv().bit()))
-            .field("rts_inv", &format_args!("{}", self.rts_inv().bit()))
-            .field("dtr_inv", &format_args!("{}", self.dtr_inv().bit()))
-            .field("sw_dtr", &format_args!("{}", self.sw_dtr().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("rxfifo_full_thrhd", &self.rxfifo_full_thrhd())
+            .field("txfifo_empty_thrhd", &self.txfifo_empty_thrhd())
+            .field("cts_inv", &self.cts_inv())
+            .field("dsr_inv", &self.dsr_inv())
+            .field("rts_inv", &self.rts_inv())
+            .field("dtr_inv", &self.dtr_inv())
+            .field("sw_dtr", &self.sw_dtr())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:7 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/date.rs b/esp32c6-lp/src/lp_uart/date.rs
index a81320d26c..6112a0fc83 100644
--- a/esp32c6-lp/src/lp_uart/date.rs
+++ b/esp32c6-lp/src/lp_uart/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6-lp/src/lp_uart/fifo.rs b/esp32c6-lp/src/lp_uart/fifo.rs
index 3ea719e7ab..fdc9ee6700 100644
--- a/esp32c6-lp/src/lp_uart/fifo.rs
+++ b/esp32c6-lp/src/lp_uart/fifo.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO")
-            .field(
-                "rxfifo_rd_byte",
-                &format_args!("{}", self.rxfifo_rd_byte().bits()),
-            )
+            .field("rxfifo_rd_byte", &self.rxfifo_rd_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - UART 0 accesses FIFO via this register."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/fsm_status.rs b/esp32c6-lp/src/lp_uart/fsm_status.rs
index 7e47b06bf6..4088ac153f 100644
--- a/esp32c6-lp/src/lp_uart/fsm_status.rs
+++ b/esp32c6-lp/src/lp_uart/fsm_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_STATUS")
-            .field("st_urx_out", &format_args!("{}", self.st_urx_out().bits()))
-            .field("st_utx_out", &format_args!("{}", self.st_utx_out().bits()))
+            .field("st_urx_out", &self.st_urx_out())
+            .field("st_utx_out", &self.st_utx_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART transmit and receive status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FSM_STATUS_SPEC;
 impl crate::RegisterSpec for FSM_STATUS_SPEC {
diff --git a/esp32c6-lp/src/lp_uart/hwfc_conf_sync.rs b/esp32c6-lp/src/lp_uart/hwfc_conf_sync.rs
index 0284e7e2da..3ffd3cc4ac 100644
--- a/esp32c6-lp/src/lp_uart/hwfc_conf_sync.rs
+++ b/esp32c6-lp/src/lp_uart/hwfc_conf_sync.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HWFC_CONF_SYNC")
-            .field(
-                "rx_flow_thrhd",
-                &format_args!("{}", self.rx_flow_thrhd().bits()),
-            )
-            .field("rx_flow_en", &format_args!("{}", self.rx_flow_en().bit()))
+            .field("rx_flow_thrhd", &self.rx_flow_thrhd())
+            .field("rx_flow_en", &self.rx_flow_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HWFC_CONF_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:7 - This register is used to configure the maximum amount of data that can be received when hardware flow control works."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/id.rs b/esp32c6-lp/src/lp_uart/id.rs
index 9c8cfa3a6b..670842afd9 100644
--- a/esp32c6-lp/src/lp_uart/id.rs
+++ b/esp32c6-lp/src/lp_uart/id.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("ID")
-            .field("id", &format_args!("{}", self.id().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("ID").field("id", &self.id()).finish()
     }
 }
 impl W {
diff --git a/esp32c6-lp/src/lp_uart/idle_conf_sync.rs b/esp32c6-lp/src/lp_uart/idle_conf_sync.rs
index 9f4f7d07c5..50b7bda9ab 100644
--- a/esp32c6-lp/src/lp_uart/idle_conf_sync.rs
+++ b/esp32c6-lp/src/lp_uart/idle_conf_sync.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDLE_CONF_SYNC")
-            .field(
-                "rx_idle_thrhd",
-                &format_args!("{}", self.rx_idle_thrhd().bits()),
-            )
-            .field(
-                "tx_idle_num",
-                &format_args!("{}", self.tx_idle_num().bits()),
-            )
+            .field("rx_idle_thrhd", &self.rx_idle_thrhd())
+            .field("tx_idle_num", &self.tx_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_CONF_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/int_ena.rs b/esp32c6-lp/src/lp_uart/int_ena.rs
index 3d91b96662..ae4d6f4b24 100644
--- a/esp32c6-lp/src/lp_uart/int_ena.rs
+++ b/esp32c6-lp/src/lp_uart/int_ena.rs
@@ -161,41 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/int_raw.rs b/esp32c6-lp/src/lp_uart/int_raw.rs
index dcfb481c5d..3e2b40190a 100644
--- a/esp32c6-lp/src/lp_uart/int_raw.rs
+++ b/esp32c6-lp/src/lp_uart/int_raw.rs
@@ -161,41 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/int_st.rs b/esp32c6-lp/src/lp_uart/int_st.rs
index 82aaf89509..57e0dc3bd8 100644
--- a/esp32c6-lp/src/lp_uart/int_st.rs
+++ b/esp32c6-lp/src/lp_uart/int_st.rs
@@ -125,41 +125,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6-lp/src/lp_uart/mem_conf.rs b/esp32c6-lp/src/lp_uart/mem_conf.rs
index 8c55da8b47..e930d52fc0 100644
--- a/esp32c6-lp/src/lp_uart/mem_conf.rs
+++ b/esp32c6-lp/src/lp_uart/mem_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - Set this bit to force power down UART memory."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/mem_rx_status.rs b/esp32c6-lp/src/lp_uart/mem_rx_status.rs
index fafe24b358..d7b91a2cef 100644
--- a/esp32c6-lp/src/lp_uart/mem_rx_status.rs
+++ b/esp32c6-lp/src/lp_uart/mem_rx_status.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_RX_STATUS")
-            .field(
-                "rx_sram_raddr",
-                &format_args!("{}", self.rx_sram_raddr().bits()),
-            )
-            .field(
-                "rx_sram_waddr",
-                &format_args!("{}", self.rx_sram_waddr().bits()),
-            )
+            .field("rx_sram_raddr", &self.rx_sram_raddr())
+            .field("rx_sram_waddr", &self.rx_sram_waddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Rx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_RX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_RX_STATUS_SPEC {
diff --git a/esp32c6-lp/src/lp_uart/mem_tx_status.rs b/esp32c6-lp/src/lp_uart/mem_tx_status.rs
index 05d25d084e..1ad31fce44 100644
--- a/esp32c6-lp/src/lp_uart/mem_tx_status.rs
+++ b/esp32c6-lp/src/lp_uart/mem_tx_status.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_TX_STATUS")
-            .field(
-                "tx_sram_waddr",
-                &format_args!("{}", self.tx_sram_waddr().bits()),
-            )
-            .field(
-                "tx_sram_raddr",
-                &format_args!("{}", self.tx_sram_raddr().bits()),
-            )
+            .field("tx_sram_waddr", &self.tx_sram_waddr())
+            .field("tx_sram_raddr", &self.tx_sram_raddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Tx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_TX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_TX_STATUS_SPEC {
diff --git a/esp32c6-lp/src/lp_uart/reg_update.rs b/esp32c6-lp/src/lp_uart/reg_update.rs
index b2e4551f76..441e05815f 100644
--- a/esp32c6-lp/src/lp_uart/reg_update.rs
+++ b/esp32c6-lp/src/lp_uart/reg_update.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_UPDATE")
-            .field("reg_update", &format_args!("{}", self.reg_update().bit()))
+            .field("reg_update", &self.reg_update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/rs485_conf_sync.rs b/esp32c6-lp/src/lp_uart/rs485_conf_sync.rs
index 9dc21e5447..f910bef69a 100644
--- a/esp32c6-lp/src/lp_uart/rs485_conf_sync.rs
+++ b/esp32c6-lp/src/lp_uart/rs485_conf_sync.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RS485_CONF_SYNC")
-            .field("dl0_en", &format_args!("{}", self.dl0_en().bit()))
-            .field("dl1_en", &format_args!("{}", self.dl1_en().bit()))
+            .field("dl0_en", &self.dl0_en())
+            .field("dl1_en", &self.dl1_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RS485_CONF_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set this bit to delay the stop bit by 1 bit."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/rx_filt.rs b/esp32c6-lp/src/lp_uart/rx_filt.rs
index c24c62977e..21576af0e9 100644
--- a/esp32c6-lp/src/lp_uart/rx_filt.rs
+++ b/esp32c6-lp/src/lp_uart/rx_filt.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_FILT")
-            .field(
-                "glitch_filt",
-                &format_args!("{}", self.glitch_filt().bits()),
-            )
-            .field(
-                "glitch_filt_en",
-                &format_args!("{}", self.glitch_filt_en().bit()),
-            )
+            .field("glitch_filt", &self.glitch_filt())
+            .field("glitch_filt_en", &self.glitch_filt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_FILT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - when input pulse width is lower than this value the pulse is ignored."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/sleep_conf0.rs b/esp32c6-lp/src/lp_uart/sleep_conf0.rs
index 1c5c7f7eed..a8481a8783 100644
--- a/esp32c6-lp/src/lp_uart/sleep_conf0.rs
+++ b/esp32c6-lp/src/lp_uart/sleep_conf0.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF0")
-            .field("wk_char1", &format_args!("{}", self.wk_char1().bits()))
-            .field("wk_char2", &format_args!("{}", self.wk_char2().bits()))
-            .field("wk_char3", &format_args!("{}", self.wk_char3().bits()))
-            .field("wk_char4", &format_args!("{}", self.wk_char4().bits()))
+            .field("wk_char1", &self.wk_char1())
+            .field("wk_char2", &self.wk_char2())
+            .field("wk_char3", &self.wk_char3())
+            .field("wk_char4", &self.wk_char4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register restores the specified wake up char1 to wake up"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/sleep_conf1.rs b/esp32c6-lp/src/lp_uart/sleep_conf1.rs
index f9f665a833..bf71699cf5 100644
--- a/esp32c6-lp/src/lp_uart/sleep_conf1.rs
+++ b/esp32c6-lp/src/lp_uart/sleep_conf1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF1")
-            .field("wk_char0", &format_args!("{}", self.wk_char0().bits()))
+            .field("wk_char0", &self.wk_char0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register restores the specified char0 to wake up"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/sleep_conf2.rs b/esp32c6-lp/src/lp_uart/sleep_conf2.rs
index f2fdbaae7f..a32f4c66fd 100644
--- a/esp32c6-lp/src/lp_uart/sleep_conf2.rs
+++ b/esp32c6-lp/src/lp_uart/sleep_conf2.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF2")
-            .field(
-                "active_threshold",
-                &format_args!("{}", self.active_threshold().bits()),
-            )
-            .field(
-                "rx_wake_up_thrhd",
-                &format_args!("{}", self.rx_wake_up_thrhd().bits()),
-            )
-            .field(
-                "wk_char_num",
-                &format_args!("{}", self.wk_char_num().bits()),
-            )
-            .field(
-                "wk_char_mask",
-                &format_args!("{}", self.wk_char_mask().bits()),
-            )
-            .field(
-                "wk_mode_sel",
-                &format_args!("{}", self.wk_mode_sel().bits()),
-            )
+            .field("active_threshold", &self.active_threshold())
+            .field("rx_wake_up_thrhd", &self.rx_wake_up_thrhd())
+            .field("wk_char_num", &self.wk_char_num())
+            .field("wk_char_mask", &self.wk_char_mask())
+            .field("wk_mode_sel", &self.wk_mode_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/status.rs b/esp32c6-lp/src/lp_uart/status.rs
index 50000e82e0..d25c3beb30 100644
--- a/esp32c6-lp/src/lp_uart/status.rs
+++ b/esp32c6-lp/src/lp_uart/status.rs
@@ -62,23 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("dsrn", &format_args!("{}", self.dsrn().bit()))
-            .field("ctsn", &format_args!("{}", self.ctsn().bit()))
-            .field("rxd", &format_args!("{}", self.rxd().bit()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field("dtrn", &format_args!("{}", self.dtrn().bit()))
-            .field("rtsn", &format_args!("{}", self.rtsn().bit()))
-            .field("txd", &format_args!("{}", self.txd().bit()))
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("dsrn", &self.dsrn())
+            .field("ctsn", &self.ctsn())
+            .field("rxd", &self.rxd())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("dtrn", &self.dtrn())
+            .field("rtsn", &self.rtsn())
+            .field("txd", &self.txd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32c6-lp/src/lp_uart/swfc_conf0_sync.rs b/esp32c6-lp/src/lp_uart/swfc_conf0_sync.rs
index e29be79632..3b6b88a494 100644
--- a/esp32c6-lp/src/lp_uart/swfc_conf0_sync.rs
+++ b/esp32c6-lp/src/lp_uart/swfc_conf0_sync.rs
@@ -89,30 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF0_SYNC")
-            .field("xon_char", &format_args!("{}", self.xon_char().bits()))
-            .field("xoff_char", &format_args!("{}", self.xoff_char().bits()))
-            .field(
-                "xon_xoff_still_send",
-                &format_args!("{}", self.xon_xoff_still_send().bit()),
-            )
-            .field(
-                "sw_flow_con_en",
-                &format_args!("{}", self.sw_flow_con_en().bit()),
-            )
-            .field("xonoff_del", &format_args!("{}", self.xonoff_del().bit()))
-            .field("force_xon", &format_args!("{}", self.force_xon().bit()))
-            .field("force_xoff", &format_args!("{}", self.force_xoff().bit()))
-            .field("send_xon", &format_args!("{}", self.send_xon().bit()))
-            .field("send_xoff", &format_args!("{}", self.send_xoff().bit()))
+            .field("xon_char", &self.xon_char())
+            .field("xoff_char", &self.xoff_char())
+            .field("xon_xoff_still_send", &self.xon_xoff_still_send())
+            .field("sw_flow_con_en", &self.sw_flow_con_en())
+            .field("xonoff_del", &self.xonoff_del())
+            .field("force_xon", &self.force_xon())
+            .field("force_xoff", &self.force_xoff())
+            .field("send_xon", &self.send_xon())
+            .field("send_xoff", &self.send_xoff())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF0_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register stores the Xon flow control char."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/swfc_conf1.rs b/esp32c6-lp/src/lp_uart/swfc_conf1.rs
index 253a05d3c6..15050eecf9 100644
--- a/esp32c6-lp/src/lp_uart/swfc_conf1.rs
+++ b/esp32c6-lp/src/lp_uart/swfc_conf1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF1")
-            .field(
-                "xon_threshold",
-                &format_args!("{}", self.xon_threshold().bits()),
-            )
-            .field(
-                "xoff_threshold",
-                &format_args!("{}", self.xoff_threshold().bits()),
-            )
+            .field("xon_threshold", &self.xon_threshold())
+            .field("xoff_threshold", &self.xoff_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:7 - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/tout_conf_sync.rs b/esp32c6-lp/src/lp_uart/tout_conf_sync.rs
index 972d62c52a..11491121e1 100644
--- a/esp32c6-lp/src/lp_uart/tout_conf_sync.rs
+++ b/esp32c6-lp/src/lp_uart/tout_conf_sync.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUT_CONF_SYNC")
-            .field("rx_tout_en", &format_args!("{}", self.rx_tout_en().bit()))
-            .field(
-                "rx_tout_flow_dis",
-                &format_args!("{}", self.rx_tout_flow_dis().bit()),
-            )
-            .field(
-                "rx_tout_thrhd",
-                &format_args!("{}", self.rx_tout_thrhd().bits()),
-            )
+            .field("rx_tout_en", &self.rx_tout_en())
+            .field("rx_tout_flow_dis", &self.rx_tout_flow_dis())
+            .field("rx_tout_thrhd", &self.rx_tout_thrhd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUT_CONF_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enble bit for uart receiver's timeout function."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_uart/txbrk_conf_sync.rs b/esp32c6-lp/src/lp_uart/txbrk_conf_sync.rs
index 5a96901f8a..413d24ce7d 100644
--- a/esp32c6-lp/src/lp_uart/txbrk_conf_sync.rs
+++ b/esp32c6-lp/src/lp_uart/txbrk_conf_sync.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXBRK_CONF_SYNC")
-            .field("tx_brk_num", &format_args!("{}", self.tx_brk_num().bits()))
+            .field("tx_brk_num", &self.tx_brk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXBRK_CONF_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_wdt/config0.rs b/esp32c6-lp/src/lp_wdt/config0.rs
index c07a77295a..59a4cb7788 100644
--- a/esp32c6-lp/src/lp_wdt/config0.rs
+++ b/esp32c6-lp/src/lp_wdt/config0.rs
@@ -125,52 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG0")
-            .field(
-                "wdt_chip_reset_width",
-                &format_args!("{}", self.wdt_chip_reset_width().bits()),
-            )
-            .field(
-                "wdt_chip_reset_en",
-                &format_args!("{}", self.wdt_chip_reset_en().bit()),
-            )
-            .field(
-                "wdt_pause_in_slp",
-                &format_args!("{}", self.wdt_pause_in_slp().bit()),
-            )
-            .field(
-                "wdt_appcpu_reset_en",
-                &format_args!("{}", self.wdt_appcpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_chip_reset_width", &self.wdt_chip_reset_width())
+            .field("wdt_chip_reset_en", &self.wdt_chip_reset_en())
+            .field("wdt_pause_in_slp", &self.wdt_pause_in_slp())
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_wdt/config1.rs b/esp32c6-lp/src/lp_wdt/config1.rs
index 5718bd36a7..cc20f95485 100644
--- a/esp32c6-lp/src/lp_wdt/config1.rs
+++ b/esp32c6-lp/src/lp_wdt/config1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG1")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_wdt/config2.rs b/esp32c6-lp/src/lp_wdt/config2.rs
index a1ed774a2e..1208d49421 100644
--- a/esp32c6-lp/src/lp_wdt/config2.rs
+++ b/esp32c6-lp/src/lp_wdt/config2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG2")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_wdt/config3.rs b/esp32c6-lp/src/lp_wdt/config3.rs
index 51d57fe8f9..41322e4dc9 100644
--- a/esp32c6-lp/src/lp_wdt/config3.rs
+++ b/esp32c6-lp/src/lp_wdt/config3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG3")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_wdt/config4.rs b/esp32c6-lp/src/lp_wdt/config4.rs
index f0857186f5..efe8bb1a07 100644
--- a/esp32c6-lp/src/lp_wdt/config4.rs
+++ b/esp32c6-lp/src/lp_wdt/config4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG4")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_wdt/date.rs b/esp32c6-lp/src/lp_wdt/date.rs
index ad999360f1..c4762f886a 100644
--- a/esp32c6-lp/src/lp_wdt/date.rs
+++ b/esp32c6-lp/src/lp_wdt/date.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "lp_wdt_date",
-                &format_args!("{}", self.lp_wdt_date().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("lp_wdt_date", &self.lp_wdt_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_wdt/int_ena.rs b/esp32c6-lp/src/lp_wdt/int_ena.rs
index 31da42e32e..8fa7730e67 100644
--- a/esp32c6-lp/src/lp_wdt/int_ena.rs
+++ b/esp32c6-lp/src/lp_wdt/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("super_wdt", &format_args!("{}", self.super_wdt().bit()))
-            .field("lp_wdt", &format_args!("{}", self.lp_wdt().bit()))
+            .field("super_wdt", &self.super_wdt())
+            .field("lp_wdt", &self.lp_wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_wdt/int_raw.rs b/esp32c6-lp/src/lp_wdt/int_raw.rs
index c4f12e1d5e..fd7e3c5567 100644
--- a/esp32c6-lp/src/lp_wdt/int_raw.rs
+++ b/esp32c6-lp/src/lp_wdt/int_raw.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("super_wdt", &format_args!("{}", self.super_wdt().bit()))
-            .field("lp_wdt", &format_args!("{}", self.lp_wdt().bit()))
+            .field("super_wdt", &self.super_wdt())
+            .field("lp_wdt", &self.lp_wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_wdt/int_st.rs b/esp32c6-lp/src/lp_wdt/int_st.rs
index 0f1014ca7b..7801732fb2 100644
--- a/esp32c6-lp/src/lp_wdt/int_st.rs
+++ b/esp32c6-lp/src/lp_wdt/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("super_wdt", &format_args!("{}", self.super_wdt().bit()))
-            .field("lp_wdt", &format_args!("{}", self.lp_wdt().bit()))
+            .field("super_wdt", &self.super_wdt())
+            .field("lp_wdt", &self.lp_wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6-lp/src/lp_wdt/swd_config.rs b/esp32c6-lp/src/lp_wdt/swd_config.rs
index edafc084f0..3c3b00ce99 100644
--- a/esp32c6-lp/src/lp_wdt/swd_config.rs
+++ b/esp32c6-lp/src/lp_wdt/swd_config.rs
@@ -46,28 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_CONFIG")
-            .field(
-                "swd_reset_flag",
-                &format_args!("{}", self.swd_reset_flag().bit()),
-            )
-            .field(
-                "swd_auto_feed_en",
-                &format_args!("{}", self.swd_auto_feed_en().bit()),
-            )
-            .field(
-                "swd_signal_width",
-                &format_args!("{}", self.swd_signal_width().bits()),
-            )
-            .field("swd_disable", &format_args!("{}", self.swd_disable().bit()))
+            .field("swd_reset_flag", &self.swd_reset_flag())
+            .field("swd_auto_feed_en", &self.swd_auto_feed_en())
+            .field("swd_signal_width", &self.swd_signal_width())
+            .field("swd_disable", &self.swd_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_wdt/swd_wprotect.rs b/esp32c6-lp/src/lp_wdt/swd_wprotect.rs
index b3d6f51abb..38581d43f4 100644
--- a/esp32c6-lp/src/lp_wdt/swd_wprotect.rs
+++ b/esp32c6-lp/src/lp_wdt/swd_wprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_WPROTECT")
-            .field("swd_wkey", &format_args!("{}", self.swd_wkey().bits()))
+            .field("swd_wkey", &self.swd_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_WPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6-lp/src/lp_wdt/wprotect.rs b/esp32c6-lp/src/lp_wdt/wprotect.rs
index e32763d1d9..fe98108b4e 100644
--- a/esp32c6-lp/src/lp_wdt/wprotect.rs
+++ b/esp32c6-lp/src/lp_wdt/wprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/aes/aad_block_num.rs b/esp32c6/src/aes/aad_block_num.rs
index 75e37b35ae..34160ca226 100644
--- a/esp32c6/src/aes/aad_block_num.rs
+++ b/esp32c6/src/aes/aad_block_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AAD_BLOCK_NUM")
-            .field(
-                "aad_block_num",
-                &format_args!("{}", self.aad_block_num().bits()),
-            )
+            .field("aad_block_num", &self.aad_block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AAD_BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits stores the number of AAD block."]
     #[inline(always)]
diff --git a/esp32c6/src/aes/block_mode.rs b/esp32c6/src/aes/block_mode.rs
index e1da4c4f3c..b2e3b5efc6 100644
--- a/esp32c6/src/aes/block_mode.rs
+++ b/esp32c6/src/aes/block_mode.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLOCK_MODE")
-            .field("block_mode", &format_args!("{}", self.block_mode().bits()))
+            .field("block_mode", &self.block_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLOCK_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved."]
     #[inline(always)]
diff --git a/esp32c6/src/aes/block_num.rs b/esp32c6/src/aes/block_num.rs
index 80e2290bb3..a1897ab822 100644
--- a/esp32c6/src/aes/block_num.rs
+++ b/esp32c6/src/aes/block_num.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLOCK_NUM")
-            .field("block_num", &format_args!("{}", self.block_num().bits()))
+            .field("block_num", &self.block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits stores the number of Plaintext/ciphertext block."]
     #[inline(always)]
diff --git a/esp32c6/src/aes/date.rs b/esp32c6/src/aes/date.rs
index a22c32c101..5e7e48df64 100644
--- a/esp32c6/src/aes/date.rs
+++ b/esp32c6/src/aes/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/aes/dma_enable.rs b/esp32c6/src/aes/dma_enable.rs
index 3fa34abee5..1f5f535a07 100644
--- a/esp32c6/src/aes/dma_enable.rs
+++ b/esp32c6/src/aes/dma_enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_ENABLE")
-            .field("dma_enable", &format_args!("{}", self.dma_enable().bit()))
+            .field("dma_enable", &self.dma_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."]
     #[inline(always)]
diff --git a/esp32c6/src/aes/endian.rs b/esp32c6/src/aes/endian.rs
index e5a3e93efc..30ecf46902 100644
--- a/esp32c6/src/aes/endian.rs
+++ b/esp32c6/src/aes/endian.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENDIAN")
-            .field("endian", &format_args!("{}", self.endian().bits()))
+            .field("endian", &self.endian())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENDIAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - endian. \\[1:0\\] key endian, \\[3:2\\] text_in endian or in_stream endian, \\[5:4\\] text_out endian or out_stream endian"]
     #[inline(always)]
diff --git a/esp32c6/src/aes/h_mem.rs b/esp32c6/src/aes/h_mem.rs
index fcd1d250f9..2e4334ff37 100644
--- a/esp32c6/src/aes/h_mem.rs
+++ b/esp32c6/src/aes/h_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores GCM hash subkey\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct H_MEM_SPEC;
diff --git a/esp32c6/src/aes/inc_sel.rs b/esp32c6/src/aes/inc_sel.rs
index a6665d07ec..69d24607c0 100644
--- a/esp32c6/src/aes/inc_sel.rs
+++ b/esp32c6/src/aes/inc_sel.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INC_SEL")
-            .field("inc_sel", &format_args!("{}", self.inc_sel().bit()))
+            .field("inc_sel", &self.inc_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INC_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit decides the standard incrementing function. 0: INC32. 1: INC128."]
     #[inline(always)]
diff --git a/esp32c6/src/aes/int_ena.rs b/esp32c6/src/aes/int_ena.rs
index ccd96d099f..1abedbe830 100644
--- a/esp32c6/src/aes/int_ena.rs
+++ b/esp32c6/src/aes/int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("int_ena", &format_args!("{}", self.int_ena().bit()))
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable interrupt that occurs when DMA-AES calculation is done."]
     #[inline(always)]
diff --git a/esp32c6/src/aes/iv_mem.rs b/esp32c6/src/aes/iv_mem.rs
index e8b4d332de..20bdbb631b 100644
--- a/esp32c6/src/aes/iv_mem.rs
+++ b/esp32c6/src/aes/iv_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IV_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores initialization vector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iv_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iv_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IV_MEM_SPEC;
diff --git a/esp32c6/src/aes/j0_mem.rs b/esp32c6/src/aes/j0_mem.rs
index a78fdd3452..002c675bfe 100644
--- a/esp32c6/src/aes/j0_mem.rs
+++ b/esp32c6/src/aes/j0_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<J0_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores J0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`j0_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`j0_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct J0_MEM_SPEC;
diff --git a/esp32c6/src/aes/key.rs b/esp32c6/src/aes/key.rs
index 8b2a51282a..c1d2c046ad 100644
--- a/esp32c6/src/aes/key.rs
+++ b/esp32c6/src/aes/key.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("KEY")
-            .field("key", &format_args!("{}", self.key().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<KEY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("KEY").field("key", &self.key()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/aes/mode.rs b/esp32c6/src/aes/mode.rs
index edc4a67756..aa353f24b7 100644
--- a/esp32c6/src/aes/mode.rs
+++ b/esp32c6/src/aes/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/aes/remainder_bit_num.rs b/esp32c6/src/aes/remainder_bit_num.rs
index 330809cbc6..73a3610f09 100644
--- a/esp32c6/src/aes/remainder_bit_num.rs
+++ b/esp32c6/src/aes/remainder_bit_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REMAINDER_BIT_NUM")
-            .field(
-                "remainder_bit_num",
-                &format_args!("{}", self.remainder_bit_num().bits()),
-            )
+            .field("remainder_bit_num", &self.remainder_bit_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REMAINDER_BIT_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Those bits stores the number of remainder bit."]
     #[inline(always)]
diff --git a/esp32c6/src/aes/state.rs b/esp32c6/src/aes/state.rs
index 5a58b13248..8a38798ae3 100644
--- a/esp32c6/src/aes/state.rs
+++ b/esp32c6/src/aes/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("state", &format_args!("{}", self.state().bits()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "AES state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32c6/src/aes/t0_mem.rs b/esp32c6/src/aes/t0_mem.rs
index 1b3fcafdb6..e2445d62f8 100644
--- a/esp32c6/src/aes/t0_mem.rs
+++ b/esp32c6/src/aes/t0_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T0_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores T0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct T0_MEM_SPEC;
diff --git a/esp32c6/src/aes/text_in.rs b/esp32c6/src/aes/text_in.rs
index 71ff18340a..24a5810ee3 100644
--- a/esp32c6/src/aes/text_in.rs
+++ b/esp32c6/src/aes/text_in.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEXT_IN")
-            .field("text_in", &format_args!("{}", self.text_in().bits()))
+            .field("text_in", &self.text_in())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEXT_IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This bits stores text_in_0 that is a part of source text material."]
     #[inline(always)]
diff --git a/esp32c6/src/aes/text_out.rs b/esp32c6/src/aes/text_out.rs
index 4040aae24b..29f631b4b2 100644
--- a/esp32c6/src/aes/text_out.rs
+++ b/esp32c6/src/aes/text_out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEXT_OUT")
-            .field("text_out", &format_args!("{}", self.text_out().bits()))
+            .field("text_out", &self.text_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEXT_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This bits stores text_out_0 that is a part of result text material."]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/arb_ctrl.rs b/esp32c6/src/apb_saradc/arb_ctrl.rs
index de8828334b..51290b0767 100644
--- a/esp32c6/src/apb_saradc/arb_ctrl.rs
+++ b/esp32c6/src/apb_saradc/arb_ctrl.rs
@@ -80,35 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_CTRL")
-            .field("apb_force", &format_args!("{}", self.apb_force().bit()))
-            .field("rtc_force", &format_args!("{}", self.rtc_force().bit()))
-            .field("wifi_force", &format_args!("{}", self.wifi_force().bit()))
-            .field("grant_force", &format_args!("{}", self.grant_force().bit()))
-            .field(
-                "apb_priority",
-                &format_args!("{}", self.apb_priority().bits()),
-            )
-            .field(
-                "rtc_priority",
-                &format_args!("{}", self.rtc_priority().bits()),
-            )
-            .field(
-                "wifi_priority",
-                &format_args!("{}", self.wifi_priority().bits()),
-            )
-            .field(
-                "fix_priority",
-                &format_args!("{}", self.fix_priority().bit()),
-            )
+            .field("apb_force", &self.apb_force())
+            .field("rtc_force", &self.rtc_force())
+            .field("wifi_force", &self.wifi_force())
+            .field("grant_force", &self.grant_force())
+            .field("apb_priority", &self.apb_priority())
+            .field("rtc_priority", &self.rtc_priority())
+            .field("wifi_priority", &self.wifi_priority())
+            .field("fix_priority", &self.fix_priority())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - adc2 arbiter force to enableapb controller"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/cali.rs b/esp32c6/src/apb_saradc/cali.rs
index f8159301ec..4a5f73518e 100644
--- a/esp32c6/src/apb_saradc/cali.rs
+++ b/esp32c6/src/apb_saradc/cali.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CALI")
-            .field("cfg", &format_args!("{}", self.cfg().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CALI").field("cfg", &self.cfg()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/apb_saradc/clkm_conf.rs b/esp32c6/src/apb_saradc/clkm_conf.rs
index 090b7974c0..6d87345504 100644
--- a/esp32c6/src/apb_saradc/clkm_conf.rs
+++ b/esp32c6/src/apb_saradc/clkm_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKM_CONF")
-            .field(
-                "clkm_div_num",
-                &format_args!("{}", self.clkm_div_num().bits()),
-            )
-            .field("clkm_div_b", &format_args!("{}", self.clkm_div_b().bits()))
-            .field("clkm_div_a", &format_args!("{}", self.clkm_div_a().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bits()))
+            .field("clkm_div_num", &self.clkm_div_num())
+            .field("clkm_div_b", &self.clkm_div_b())
+            .field("clkm_div_a", &self.clkm_div_a())
+            .field("clk_en", &self.clk_en())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral I2S clock divider value"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/ctrl.rs b/esp32c6/src/apb_saradc/ctrl.rs
index f3e7955a17..5023dbc902 100644
--- a/esp32c6/src/apb_saradc/ctrl.rs
+++ b/esp32c6/src/apb_saradc/ctrl.rs
@@ -89,45 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("start_force", &format_args!("{}", self.start_force().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field(
-                "sar_clk_gated",
-                &format_args!("{}", self.sar_clk_gated().bit()),
-            )
-            .field(
-                "sar_clk_div",
-                &format_args!("{}", self.sar_clk_div().bits()),
-            )
-            .field(
-                "sar_patt_len",
-                &format_args!("{}", self.sar_patt_len().bits()),
-            )
-            .field(
-                "sar_patt_p_clear",
-                &format_args!("{}", self.sar_patt_p_clear().bit()),
-            )
-            .field(
-                "xpd_sar_force",
-                &format_args!("{}", self.xpd_sar_force().bits()),
-            )
-            .field(
-                "saradc2_pwdet_drv",
-                &format_args!("{}", self.saradc2_pwdet_drv().bit()),
-            )
-            .field(
-                "wait_arb_cycle",
-                &format_args!("{}", self.wait_arb_cycle().bits()),
-            )
+            .field("start_force", &self.start_force())
+            .field("start", &self.start())
+            .field("sar_clk_gated", &self.sar_clk_gated())
+            .field("sar_clk_div", &self.sar_clk_div())
+            .field("sar_patt_len", &self.sar_patt_len())
+            .field("sar_patt_p_clear", &self.sar_patt_p_clear())
+            .field("xpd_sar_force", &self.xpd_sar_force())
+            .field("saradc2_pwdet_drv", &self.saradc2_pwdet_drv())
+            .field("wait_arb_cycle", &self.wait_arb_cycle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - select software enable saradc sample"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/ctrl2.rs b/esp32c6/src/apb_saradc/ctrl2.rs
index 0f067495b8..f8dd029bce 100644
--- a/esp32c6/src/apb_saradc/ctrl2.rs
+++ b/esp32c6/src/apb_saradc/ctrl2.rs
@@ -62,30 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field(
-                "meas_num_limit",
-                &format_args!("{}", self.meas_num_limit().bit()),
-            )
-            .field(
-                "max_meas_num",
-                &format_args!("{}", self.max_meas_num().bits()),
-            )
-            .field("sar1_inv", &format_args!("{}", self.sar1_inv().bit()))
-            .field("sar2_inv", &format_args!("{}", self.sar2_inv().bit()))
-            .field(
-                "timer_target",
-                &format_args!("{}", self.timer_target().bits()),
-            )
-            .field("timer_en", &format_args!("{}", self.timer_en().bit()))
+            .field("meas_num_limit", &self.meas_num_limit())
+            .field("max_meas_num", &self.max_meas_num())
+            .field("sar1_inv", &self.sar1_inv())
+            .field("sar2_inv", &self.sar2_inv())
+            .field("timer_target", &self.timer_target())
+            .field("timer_en", &self.timer_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable max meas num"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/ctrl_date.rs b/esp32c6/src/apb_saradc/ctrl_date.rs
index 9ff2a11ba5..5c42a495e0 100644
--- a/esp32c6/src/apb_saradc/ctrl_date.rs
+++ b/esp32c6/src/apb_saradc/ctrl_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL_DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - version"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/dma_conf.rs b/esp32c6/src/apb_saradc/dma_conf.rs
index f4528f9f98..e8ef94a4b7 100644
--- a/esp32c6/src/apb_saradc/dma_conf.rs
+++ b/esp32c6/src/apb_saradc/dma_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field(
-                "adc_eof_num",
-                &format_args!("{}", self.adc_eof_num().bits()),
-            )
-            .field(
-                "adc_reset_fsm",
-                &format_args!("{}", self.adc_reset_fsm().bit()),
-            )
-            .field("adc_trans", &format_args!("{}", self.adc_trans().bit()))
+            .field("adc_eof_num", &self.adc_eof_num())
+            .field("adc_reset_fsm", &self.adc_reset_fsm())
+            .field("adc_trans", &self.adc_trans())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - the dma_in_suc_eof gen when sample cnt = spi_eof_num"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/filter_ctrl0.rs b/esp32c6/src/apb_saradc/filter_ctrl0.rs
index 17eaaa1fd2..36c2d5446d 100644
--- a/esp32c6/src/apb_saradc/filter_ctrl0.rs
+++ b/esp32c6/src/apb_saradc/filter_ctrl0.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CTRL0")
-            .field(
-                "filter_channel1",
-                &format_args!("{}", self.filter_channel1().bits()),
-            )
-            .field(
-                "filter_channel0",
-                &format_args!("{}", self.filter_channel0().bits()),
-            )
-            .field(
-                "filter_reset",
-                &format_args!("{}", self.filter_reset().bit()),
-            )
+            .field("filter_channel1", &self.filter_channel1())
+            .field("filter_channel0", &self.filter_channel0())
+            .field("filter_reset", &self.filter_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 18:21 - configure filter1 to adc channel"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/filter_ctrl1.rs b/esp32c6/src/apb_saradc/filter_ctrl1.rs
index 5b4e0f3523..9893496ebf 100644
--- a/esp32c6/src/apb_saradc/filter_ctrl1.rs
+++ b/esp32c6/src/apb_saradc/filter_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CTRL1")
-            .field(
-                "filter_factor1",
-                &format_args!("{}", self.filter_factor1().bits()),
-            )
-            .field(
-                "filter_factor0",
-                &format_args!("{}", self.filter_factor0().bits()),
-            )
+            .field("filter_factor1", &self.filter_factor1())
+            .field("filter_factor0", &self.filter_factor0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 26:28 - Factor of saradc filter1"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/fsm_wait.rs b/esp32c6/src/apb_saradc/fsm_wait.rs
index fa4cd82fd6..d100d69e0f 100644
--- a/esp32c6/src/apb_saradc/fsm_wait.rs
+++ b/esp32c6/src/apb_saradc/fsm_wait.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_WAIT")
-            .field("xpd_wait", &format_args!("{}", self.xpd_wait().bits()))
-            .field("rstb_wait", &format_args!("{}", self.rstb_wait().bits()))
-            .field(
-                "standby_wait",
-                &format_args!("{}", self.standby_wait().bits()),
-            )
+            .field("xpd_wait", &self.xpd_wait())
+            .field("rstb_wait", &self.rstb_wait())
+            .field("standby_wait", &self.standby_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_WAIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - saradc_xpd_wait"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/int_ena.rs b/esp32c6/src/apb_saradc/int_ena.rs
index 818483c401..cab97caa9f 100644
--- a/esp32c6/src/apb_saradc/int_ena.rs
+++ b/esp32c6/src/apb_saradc/int_ena.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("tsens", &format_args!("{}", self.tsens().bit()))
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("tsens", &self.tsens())
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - tsens low interrupt enable"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/int_raw.rs b/esp32c6/src/apb_saradc/int_raw.rs
index 640ee93681..7b845e29e0 100644
--- a/esp32c6/src/apb_saradc/int_raw.rs
+++ b/esp32c6/src/apb_saradc/int_raw.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("tsens", &format_args!("{}", self.tsens().bit()))
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("tsens", &self.tsens())
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - saradc tsens interrupt raw"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/int_st.rs b/esp32c6/src/apb_saradc/int_st.rs
index cd1ebbefc6..bddddcc414 100644
--- a/esp32c6/src/apb_saradc/int_st.rs
+++ b/esp32c6/src/apb_saradc/int_st.rs
@@ -55,22 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("tsens", &format_args!("{}", self.tsens().bit()))
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("tsens", &self.tsens())
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc int register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/apb_saradc/onetime_sample.rs b/esp32c6/src/apb_saradc/onetime_sample.rs
index 0c838e5d4d..3e7f7d7c2a 100644
--- a/esp32c6/src/apb_saradc/onetime_sample.rs
+++ b/esp32c6/src/apb_saradc/onetime_sample.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ONETIME_SAMPLE")
-            .field(
-                "onetime_atten",
-                &format_args!("{}", self.onetime_atten().bits()),
-            )
-            .field(
-                "onetime_channel",
-                &format_args!("{}", self.onetime_channel().bits()),
-            )
-            .field(
-                "onetime_start",
-                &format_args!("{}", self.onetime_start().bit()),
-            )
-            .field(
-                "saradc2_onetime_sample",
-                &format_args!("{}", self.saradc2_onetime_sample().bit()),
-            )
-            .field(
-                "saradc1_onetime_sample",
-                &format_args!("{}", self.saradc1_onetime_sample().bit()),
-            )
+            .field("onetime_atten", &self.onetime_atten())
+            .field("onetime_channel", &self.onetime_channel())
+            .field("onetime_start", &self.onetime_start())
+            .field("saradc2_onetime_sample", &self.saradc2_onetime_sample())
+            .field("saradc1_onetime_sample", &self.saradc1_onetime_sample())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ONETIME_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:24 - configure onetime atten"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/sar1_status.rs b/esp32c6/src/apb_saradc/sar1_status.rs
index 9080c76bf7..5982abfbbd 100644
--- a/esp32c6/src/apb_saradc/sar1_status.rs
+++ b/esp32c6/src/apb_saradc/sar1_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_STATUS")
-            .field(
-                "sar1_status",
-                &format_args!("{}", self.sar1_status().bits()),
-            )
+            .field("sar1_status", &self.sar1_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR1_STATUS_SPEC;
 impl crate::RegisterSpec for SAR1_STATUS_SPEC {
diff --git a/esp32c6/src/apb_saradc/sar1data_status.rs b/esp32c6/src/apb_saradc/sar1data_status.rs
index 413ab6231c..8304d75d71 100644
--- a/esp32c6/src/apb_saradc/sar1data_status.rs
+++ b/esp32c6/src/apb_saradc/sar1data_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1DATA_STATUS")
-            .field(
-                "saradc1_data",
-                &format_args!("{}", self.saradc1_data().bits()),
-            )
+            .field("saradc1_data", &self.saradc1_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1DATA_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1data_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR1DATA_STATUS_SPEC;
 impl crate::RegisterSpec for SAR1DATA_STATUS_SPEC {
diff --git a/esp32c6/src/apb_saradc/sar2_status.rs b/esp32c6/src/apb_saradc/sar2_status.rs
index 211fcdd134..09ae8d249b 100644
--- a/esp32c6/src/apb_saradc/sar2_status.rs
+++ b/esp32c6/src/apb_saradc/sar2_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_STATUS")
-            .field(
-                "sar2_status",
-                &format_args!("{}", self.sar2_status().bits()),
-            )
+            .field("sar2_status", &self.sar2_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR2_STATUS_SPEC;
 impl crate::RegisterSpec for SAR2_STATUS_SPEC {
diff --git a/esp32c6/src/apb_saradc/sar2data_status.rs b/esp32c6/src/apb_saradc/sar2data_status.rs
index 9052cd0794..67cd6c6ec5 100644
--- a/esp32c6/src/apb_saradc/sar2data_status.rs
+++ b/esp32c6/src/apb_saradc/sar2data_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2DATA_STATUS")
-            .field(
-                "saradc2_data",
-                &format_args!("{}", self.saradc2_data().bits()),
-            )
+            .field("saradc2_data", &self.saradc2_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2DATA_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2data_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR2DATA_STATUS_SPEC;
 impl crate::RegisterSpec for SAR2DATA_STATUS_SPEC {
diff --git a/esp32c6/src/apb_saradc/sar_patt_tab1.rs b/esp32c6/src/apb_saradc/sar_patt_tab1.rs
index ad981f35f6..e8d275271e 100644
--- a/esp32c6/src/apb_saradc/sar_patt_tab1.rs
+++ b/esp32c6/src/apb_saradc/sar_patt_tab1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_PATT_TAB1")
-            .field(
-                "sar_patt_tab1",
-                &format_args!("{}", self.sar_patt_tab1().bits()),
-            )
+            .field("sar_patt_tab1", &self.sar_patt_tab1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_PATT_TAB1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/sar_patt_tab2.rs b/esp32c6/src/apb_saradc/sar_patt_tab2.rs
index 48390f1cf9..ef0574954e 100644
--- a/esp32c6/src/apb_saradc/sar_patt_tab2.rs
+++ b/esp32c6/src/apb_saradc/sar_patt_tab2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_PATT_TAB2")
-            .field(
-                "sar_patt_tab2",
-                &format_args!("{}", self.sar_patt_tab2().bits()),
-            )
+            .field("sar_patt_tab2", &self.sar_patt_tab2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_PATT_TAB2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/thres0_ctrl.rs b/esp32c6/src/apb_saradc/thres0_ctrl.rs
index 1c7ff5e5c3..3b735155e3 100644
--- a/esp32c6/src/apb_saradc/thres0_ctrl.rs
+++ b/esp32c6/src/apb_saradc/thres0_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES0_CTRL")
-            .field(
-                "thres0_channel",
-                &format_args!("{}", self.thres0_channel().bits()),
-            )
-            .field(
-                "thres0_high",
-                &format_args!("{}", self.thres0_high().bits()),
-            )
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bits()))
+            .field("thres0_channel", &self.thres0_channel())
+            .field("thres0_high", &self.thres0_high())
+            .field("thres0_low", &self.thres0_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES0_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - configure thres0 to adc channel"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/thres1_ctrl.rs b/esp32c6/src/apb_saradc/thres1_ctrl.rs
index 26fb78f9e4..0ae0172e5c 100644
--- a/esp32c6/src/apb_saradc/thres1_ctrl.rs
+++ b/esp32c6/src/apb_saradc/thres1_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES1_CTRL")
-            .field(
-                "thres1_channel",
-                &format_args!("{}", self.thres1_channel().bits()),
-            )
-            .field(
-                "thres1_high",
-                &format_args!("{}", self.thres1_high().bits()),
-            )
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bits()))
+            .field("thres1_channel", &self.thres1_channel())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres1_low", &self.thres1_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES1_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - configure thres1 to adc channel"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/thres_ctrl.rs b/esp32c6/src/apb_saradc/thres_ctrl.rs
index c3d03adf77..040e84e114 100644
--- a/esp32c6/src/apb_saradc/thres_ctrl.rs
+++ b/esp32c6/src/apb_saradc/thres_ctrl.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES_CTRL")
-            .field(
-                "thres_all_en",
-                &format_args!("{}", self.thres_all_en().bit()),
-            )
-            .field("thres1_en", &format_args!("{}", self.thres1_en().bit()))
-            .field("thres0_en", &format_args!("{}", self.thres0_en().bit()))
+            .field("thres_all_en", &self.thres_all_en())
+            .field("thres1_en", &self.thres1_en())
+            .field("thres0_en", &self.thres0_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - enable thres to all channel"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/tsens_ctrl.rs b/esp32c6/src/apb_saradc/tsens_ctrl.rs
index c7b28ab6c1..b6cd198968 100644
--- a/esp32c6/src/apb_saradc/tsens_ctrl.rs
+++ b/esp32c6/src/apb_saradc/tsens_ctrl.rs
@@ -42,19 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSENS_CTRL")
-            .field("out", &format_args!("{}", self.out().bits()))
-            .field("in_inv", &format_args!("{}", self.in_inv().bit()))
-            .field("clk_div", &format_args!("{}", self.clk_div().bits()))
-            .field("pu", &format_args!("{}", self.pu().bit()))
+            .field("out", &self.out())
+            .field("in_inv", &self.in_inv())
+            .field("clk_div", &self.clk_div())
+            .field("pu", &self.pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSENS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - invert temperature sensor data"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/tsens_ctrl2.rs b/esp32c6/src/apb_saradc/tsens_ctrl2.rs
index bd67d42d0e..dd559966b9 100644
--- a/esp32c6/src/apb_saradc/tsens_ctrl2.rs
+++ b/esp32c6/src/apb_saradc/tsens_ctrl2.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSENS_CTRL2")
-            .field("xpd_wait", &format_args!("{}", self.xpd_wait().bits()))
-            .field("xpd_force", &format_args!("{}", self.xpd_force().bits()))
-            .field("clk_inv", &format_args!("{}", self.clk_inv().bit()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bit()))
+            .field("xpd_wait", &self.xpd_wait())
+            .field("xpd_force", &self.xpd_force())
+            .field("clk_inv", &self.clk_inv())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSENS_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - the time that power up tsens need wait"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/tsens_sample.rs b/esp32c6/src/apb_saradc/tsens_sample.rs
index a0a09b8c74..9997e07470 100644
--- a/esp32c6/src/apb_saradc/tsens_sample.rs
+++ b/esp32c6/src/apb_saradc/tsens_sample.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSENS_SAMPLE")
-            .field("rate", &format_args!("{}", self.rate().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("rate", &self.rate())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSENS_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - HW sample rate"]
     #[inline(always)]
diff --git a/esp32c6/src/apb_saradc/tsens_wake.rs b/esp32c6/src/apb_saradc/tsens_wake.rs
index 0e49283226..b1d4300c39 100644
--- a/esp32c6/src/apb_saradc/tsens_wake.rs
+++ b/esp32c6/src/apb_saradc/tsens_wake.rs
@@ -51,29 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSENS_WAKE")
-            .field(
-                "wakeup_th_low",
-                &format_args!("{}", self.wakeup_th_low().bits()),
-            )
-            .field(
-                "wakeup_th_high",
-                &format_args!("{}", self.wakeup_th_high().bits()),
-            )
-            .field(
-                "wakeup_over_upper_th",
-                &format_args!("{}", self.wakeup_over_upper_th().bit()),
-            )
-            .field("wakeup_mode", &format_args!("{}", self.wakeup_mode().bit()))
-            .field("wakeup_en", &format_args!("{}", self.wakeup_en().bit()))
+            .field("wakeup_th_low", &self.wakeup_th_low())
+            .field("wakeup_th_high", &self.wakeup_th_high())
+            .field("wakeup_over_upper_th", &self.wakeup_over_upper_th())
+            .field("wakeup_mode", &self.wakeup_mode())
+            .field("wakeup_en", &self.wakeup_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSENS_WAKE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - reg_wakeup_th_low"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/c0re_0_debug_mode.rs b/esp32c6/src/assist_debug/c0re_0_debug_mode.rs
index 7237343fdc..ed3e7a64c0 100644
--- a/esp32c6/src/assist_debug/c0re_0_debug_mode.rs
+++ b/esp32c6/src/assist_debug/c0re_0_debug_mode.rs
@@ -20,23 +20,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("C0RE_0_DEBUG_MODE")
-            .field(
-                "core_0_debug_mode",
-                &format_args!("{}", self.core_0_debug_mode().bit()),
-            )
+            .field("core_0_debug_mode", &self.core_0_debug_mode())
             .field(
                 "core_0_debug_module_active",
-                &format_args!("{}", self.core_0_debug_module_active().bit()),
+                &self.core_0_debug_module_active(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<C0RE_0_DEBUG_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0re_0_debug_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct C0RE_0_DEBUG_MODE_SPEC;
 impl crate::RegisterSpec for C0RE_0_DEBUG_MODE_SPEC {
diff --git a/esp32c6/src/assist_debug/c0re_0_lastpc_before_exception.rs b/esp32c6/src/assist_debug/c0re_0_lastpc_before_exception.rs
index 9c2b7a9487..1372ab5152 100644
--- a/esp32c6/src/assist_debug/c0re_0_lastpc_before_exception.rs
+++ b/esp32c6/src/assist_debug/c0re_0_lastpc_before_exception.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("C0RE_0_LASTPC_BEFORE_EXCEPTION")
-            .field(
-                "core_0_lastpc_before_exc",
-                &format_args!("{}", self.core_0_lastpc_before_exc().bits()),
-            )
+            .field("core_0_lastpc_before_exc", &self.core_0_lastpc_before_exc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<C0RE_0_LASTPC_BEFORE_EXCEPTION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0re_0_lastpc_before_exception::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct C0RE_0_LASTPC_BEFORE_EXCEPTION_SPEC;
 impl crate::RegisterSpec for C0RE_0_LASTPC_BEFORE_EXCEPTION_SPEC {
diff --git a/esp32c6/src/assist_debug/clock_gate.rs b/esp32c6/src/assist_debug/clock_gate.rs
index e123579679..743c121add 100644
--- a/esp32c6/src/assist_debug/clock_gate.rs
+++ b/esp32c6/src/assist_debug/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 force on the clock gate"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/core_0_area_dram0_0_max.rs b/esp32c6/src/assist_debug/core_0_area_dram0_0_max.rs
index 005d6a6db3..9428c7292a 100644
--- a/esp32c6/src/assist_debug/core_0_area_dram0_0_max.rs
+++ b/esp32c6/src/assist_debug/core_0_area_dram0_0_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_0_MAX")
-            .field(
-                "core_0_area_dram0_0_max",
-                &format_args!("{}", self.core_0_area_dram0_0_max().bits()),
-            )
+            .field("core_0_area_dram0_0_max", &self.core_0_area_dram0_0_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_0_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region0 end addr"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/core_0_area_dram0_0_min.rs b/esp32c6/src/assist_debug/core_0_area_dram0_0_min.rs
index 82ad82fe11..7bbd0597a1 100644
--- a/esp32c6/src/assist_debug/core_0_area_dram0_0_min.rs
+++ b/esp32c6/src/assist_debug/core_0_area_dram0_0_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_0_MIN")
-            .field(
-                "core_0_area_dram0_0_min",
-                &format_args!("{}", self.core_0_area_dram0_0_min().bits()),
-            )
+            .field("core_0_area_dram0_0_min", &self.core_0_area_dram0_0_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_0_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region0 start addr"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/core_0_area_dram0_1_max.rs b/esp32c6/src/assist_debug/core_0_area_dram0_1_max.rs
index 5386b16204..e6dcd4c10a 100644
--- a/esp32c6/src/assist_debug/core_0_area_dram0_1_max.rs
+++ b/esp32c6/src/assist_debug/core_0_area_dram0_1_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_1_MAX")
-            .field(
-                "core_0_area_dram0_1_max",
-                &format_args!("{}", self.core_0_area_dram0_1_max().bits()),
-            )
+            .field("core_0_area_dram0_1_max", &self.core_0_area_dram0_1_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_1_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region1 end addr"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/core_0_area_dram0_1_min.rs b/esp32c6/src/assist_debug/core_0_area_dram0_1_min.rs
index a60f37cb77..9a5ba5db20 100644
--- a/esp32c6/src/assist_debug/core_0_area_dram0_1_min.rs
+++ b/esp32c6/src/assist_debug/core_0_area_dram0_1_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_1_MIN")
-            .field(
-                "core_0_area_dram0_1_min",
-                &format_args!("{}", self.core_0_area_dram0_1_min().bits()),
-            )
+            .field("core_0_area_dram0_1_min", &self.core_0_area_dram0_1_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_1_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region1 start addr"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/core_0_area_pc.rs b/esp32c6/src/assist_debug/core_0_area_pc.rs
index 41c4d55664..ecc0023648 100644
--- a/esp32c6/src/assist_debug/core_0_area_pc.rs
+++ b/esp32c6/src/assist_debug/core_0_area_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PC")
-            .field(
-                "core_0_area_pc",
-                &format_args!("{}", self.core_0_area_pc().bits()),
-            )
+            .field("core_0_area_pc", &self.core_0_area_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 area pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_AREA_PC_SPEC;
 impl crate::RegisterSpec for CORE_0_AREA_PC_SPEC {
diff --git a/esp32c6/src/assist_debug/core_0_area_pif_0_max.rs b/esp32c6/src/assist_debug/core_0_area_pif_0_max.rs
index 272d2c2274..2f0e9bd13c 100644
--- a/esp32c6/src/assist_debug/core_0_area_pif_0_max.rs
+++ b/esp32c6/src/assist_debug/core_0_area_pif_0_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_0_MAX")
-            .field(
-                "core_0_area_pif_0_max",
-                &format_args!("{}", self.core_0_area_pif_0_max().bits()),
-            )
+            .field("core_0_area_pif_0_max", &self.core_0_area_pif_0_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_0_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region0 end addr"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/core_0_area_pif_0_min.rs b/esp32c6/src/assist_debug/core_0_area_pif_0_min.rs
index 6ecf444727..88c0d9e5da 100644
--- a/esp32c6/src/assist_debug/core_0_area_pif_0_min.rs
+++ b/esp32c6/src/assist_debug/core_0_area_pif_0_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_0_MIN")
-            .field(
-                "core_0_area_pif_0_min",
-                &format_args!("{}", self.core_0_area_pif_0_min().bits()),
-            )
+            .field("core_0_area_pif_0_min", &self.core_0_area_pif_0_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_0_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region0 start addr"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/core_0_area_pif_1_max.rs b/esp32c6/src/assist_debug/core_0_area_pif_1_max.rs
index 1d79804931..5a00986603 100644
--- a/esp32c6/src/assist_debug/core_0_area_pif_1_max.rs
+++ b/esp32c6/src/assist_debug/core_0_area_pif_1_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_1_MAX")
-            .field(
-                "core_0_area_pif_1_max",
-                &format_args!("{}", self.core_0_area_pif_1_max().bits()),
-            )
+            .field("core_0_area_pif_1_max", &self.core_0_area_pif_1_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_1_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region1 end addr"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/core_0_area_pif_1_min.rs b/esp32c6/src/assist_debug/core_0_area_pif_1_min.rs
index 7a20c8326f..d75bae477d 100644
--- a/esp32c6/src/assist_debug/core_0_area_pif_1_min.rs
+++ b/esp32c6/src/assist_debug/core_0_area_pif_1_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_1_MIN")
-            .field(
-                "core_0_area_pif_1_min",
-                &format_args!("{}", self.core_0_area_pif_1_min().bits()),
-            )
+            .field("core_0_area_pif_1_min", &self.core_0_area_pif_1_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_1_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region1 start addr"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/core_0_area_sp.rs b/esp32c6/src/assist_debug/core_0_area_sp.rs
index 7f80b9076b..f325b5fbe5 100644
--- a/esp32c6/src/assist_debug/core_0_area_sp.rs
+++ b/esp32c6/src/assist_debug/core_0_area_sp.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_SP")
-            .field(
-                "core_0_area_sp",
-                &format_args!("{}", self.core_0_area_sp().bits()),
-            )
+            .field("core_0_area_sp", &self.core_0_area_sp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_SP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 area sp status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_sp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_AREA_SP_SPEC;
 impl crate::RegisterSpec for CORE_0_AREA_SP_SPEC {
diff --git a/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_0.rs b/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_0.rs
index 8b493eb6d0..c131c93200 100644
--- a/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_0.rs
+++ b/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_0.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_0_dram0_recording_addr_0",
-                &format_args!("{}", self.core_0_dram0_recording_addr_0().bits()),
+                &self.core_0_dram0_recording_addr_0(),
             )
             .field(
                 "core_0_dram0_recording_wr_0",
-                &format_args!("{}", self.core_0_dram0_recording_wr_0().bit()),
+                &self.core_0_dram0_recording_wr_0(),
             )
             .field(
                 "core_0_dram0_recording_byteen_0",
-                &format_args!("{}", self.core_0_dram0_recording_byteen_0().bits()),
+                &self.core_0_dram0_recording_byteen_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC {
diff --git a/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_1.rs b/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_1.rs
index a0d0c537e7..0ecd958fff 100644
--- a/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_1.rs
+++ b/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_0_dram0_recording_pc_0",
-                &format_args!("{}", self.core_0_dram0_recording_pc_0().bits()),
+                &self.core_0_dram0_recording_pc_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC {
diff --git a/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_2.rs b/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_2.rs
index 9a92a1a979..aa220b802b 100644
--- a/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_2.rs
+++ b/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_2.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_2")
             .field(
                 "core_0_dram0_recording_addr_1",
-                &format_args!("{}", self.core_0_dram0_recording_addr_1().bits()),
+                &self.core_0_dram0_recording_addr_1(),
             )
             .field(
                 "core_0_dram0_recording_wr_1",
-                &format_args!("{}", self.core_0_dram0_recording_wr_1().bit()),
+                &self.core_0_dram0_recording_wr_1(),
             )
             .field(
                 "core_0_dram0_recording_byteen_1",
-                &format_args!("{}", self.core_0_dram0_recording_byteen_1().bits()),
+                &self.core_0_dram0_recording_byteen_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC {
diff --git a/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_3.rs b/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_3.rs
index 5533f35db5..cf67b62d88 100644
--- a/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_3.rs
+++ b/esp32c6/src/assist_debug/core_0_dram0_exception_monitor_3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_3")
             .field(
                 "core_0_dram0_recording_pc_1",
-                &format_args!("{}", self.core_0_dram0_recording_pc_1().bits()),
+                &self.core_0_dram0_recording_pc_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC {
diff --git a/esp32c6/src/assist_debug/core_0_intr_ena.rs b/esp32c6/src/assist_debug/core_0_intr_ena.rs
index 91fa6472fa..bc9eaf8e18 100644
--- a/esp32c6/src/assist_debug/core_0_intr_ena.rs
+++ b/esp32c6/src/assist_debug/core_0_intr_ena.rs
@@ -122,61 +122,55 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_INTR_ENA")
             .field(
                 "core_0_area_dram0_0_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_intr_ena().bit()),
+                &self.core_0_area_dram0_0_rd_intr_ena(),
             )
             .field(
                 "core_0_area_dram0_0_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_intr_ena().bit()),
+                &self.core_0_area_dram0_0_wr_intr_ena(),
             )
             .field(
                 "core_0_area_dram0_1_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_intr_ena().bit()),
+                &self.core_0_area_dram0_1_rd_intr_ena(),
             )
             .field(
                 "core_0_area_dram0_1_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_intr_ena().bit()),
+                &self.core_0_area_dram0_1_wr_intr_ena(),
             )
             .field(
                 "core_0_area_pif_0_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_0_rd_intr_ena().bit()),
+                &self.core_0_area_pif_0_rd_intr_ena(),
             )
             .field(
                 "core_0_area_pif_0_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_0_wr_intr_ena().bit()),
+                &self.core_0_area_pif_0_wr_intr_ena(),
             )
             .field(
                 "core_0_area_pif_1_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_1_rd_intr_ena().bit()),
+                &self.core_0_area_pif_1_rd_intr_ena(),
             )
             .field(
                 "core_0_area_pif_1_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_1_wr_intr_ena().bit()),
+                &self.core_0_area_pif_1_wr_intr_ena(),
             )
             .field(
                 "core_0_sp_spill_min_intr_ena",
-                &format_args!("{}", self.core_0_sp_spill_min_intr_ena().bit()),
+                &self.core_0_sp_spill_min_intr_ena(),
             )
             .field(
                 "core_0_sp_spill_max_intr_ena",
-                &format_args!("{}", self.core_0_sp_spill_max_intr_ena().bit()),
+                &self.core_0_sp_spill_max_intr_ena(),
             )
             .field(
                 "core_0_iram0_exception_monitor_intr_ena",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_intr_ena().bit()),
+                &self.core_0_iram0_exception_monitor_intr_ena(),
             )
             .field(
                 "core_0_dram0_exception_monitor_intr_ena",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_intr_ena().bit()),
+                &self.core_0_dram0_exception_monitor_intr_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_INTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt enable"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/core_0_intr_raw.rs b/esp32c6/src/assist_debug/core_0_intr_raw.rs
index 4ae15ba38c..1d30267746 100644
--- a/esp32c6/src/assist_debug/core_0_intr_raw.rs
+++ b/esp32c6/src/assist_debug/core_0_intr_raw.rs
@@ -92,61 +92,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_INTR_RAW")
             .field(
                 "core_0_area_dram0_0_rd_raw",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_raw().bit()),
+                &self.core_0_area_dram0_0_rd_raw(),
             )
             .field(
                 "core_0_area_dram0_0_wr_raw",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_raw().bit()),
+                &self.core_0_area_dram0_0_wr_raw(),
             )
             .field(
                 "core_0_area_dram0_1_rd_raw",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_raw().bit()),
+                &self.core_0_area_dram0_1_rd_raw(),
             )
             .field(
                 "core_0_area_dram0_1_wr_raw",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_rd_raw",
-                &format_args!("{}", self.core_0_area_pif_0_rd_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_wr_raw",
-                &format_args!("{}", self.core_0_area_pif_0_wr_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_rd_raw",
-                &format_args!("{}", self.core_0_area_pif_1_rd_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_wr_raw",
-                &format_args!("{}", self.core_0_area_pif_1_wr_raw().bit()),
-            )
-            .field(
-                "core_0_sp_spill_min_raw",
-                &format_args!("{}", self.core_0_sp_spill_min_raw().bit()),
-            )
-            .field(
-                "core_0_sp_spill_max_raw",
-                &format_args!("{}", self.core_0_sp_spill_max_raw().bit()),
+                &self.core_0_area_dram0_1_wr_raw(),
             )
+            .field("core_0_area_pif_0_rd_raw", &self.core_0_area_pif_0_rd_raw())
+            .field("core_0_area_pif_0_wr_raw", &self.core_0_area_pif_0_wr_raw())
+            .field("core_0_area_pif_1_rd_raw", &self.core_0_area_pif_1_rd_raw())
+            .field("core_0_area_pif_1_wr_raw", &self.core_0_area_pif_1_wr_raw())
+            .field("core_0_sp_spill_min_raw", &self.core_0_sp_spill_min_raw())
+            .field("core_0_sp_spill_max_raw", &self.core_0_sp_spill_max_raw())
             .field(
                 "core_0_iram0_exception_monitor_raw",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_raw().bit()),
+                &self.core_0_iram0_exception_monitor_raw(),
             )
             .field(
                 "core_0_dram0_exception_monitor_raw",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_raw().bit()),
+                &self.core_0_dram0_exception_monitor_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_INTR_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 monitor interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_intr_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_INTR_RAW_SPEC;
 impl crate::RegisterSpec for CORE_0_INTR_RAW_SPEC {
diff --git a/esp32c6/src/assist_debug/core_0_iram0_exception_monitor_0.rs b/esp32c6/src/assist_debug/core_0_iram0_exception_monitor_0.rs
index 5a4ee4189b..b653f3207f 100644
--- a/esp32c6/src/assist_debug/core_0_iram0_exception_monitor_0.rs
+++ b/esp32c6/src/assist_debug/core_0_iram0_exception_monitor_0.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_0_iram0_recording_addr_0",
-                &format_args!("{}", self.core_0_iram0_recording_addr_0().bits()),
+                &self.core_0_iram0_recording_addr_0(),
             )
             .field(
                 "core_0_iram0_recording_wr_0",
-                &format_args!("{}", self.core_0_iram0_recording_wr_0().bit()),
+                &self.core_0_iram0_recording_wr_0(),
             )
             .field(
                 "core_0_iram0_recording_loadstore_0",
-                &format_args!("{}", self.core_0_iram0_recording_loadstore_0().bit()),
+                &self.core_0_iram0_recording_loadstore_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_exception_monitor_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC;
 impl crate::RegisterSpec for CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC {
diff --git a/esp32c6/src/assist_debug/core_0_iram0_exception_monitor_1.rs b/esp32c6/src/assist_debug/core_0_iram0_exception_monitor_1.rs
index 6fef16c53f..015b3f1b8e 100644
--- a/esp32c6/src/assist_debug/core_0_iram0_exception_monitor_1.rs
+++ b/esp32c6/src/assist_debug/core_0_iram0_exception_monitor_1.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_0_iram0_recording_addr_1",
-                &format_args!("{}", self.core_0_iram0_recording_addr_1().bits()),
+                &self.core_0_iram0_recording_addr_1(),
             )
             .field(
                 "core_0_iram0_recording_wr_1",
-                &format_args!("{}", self.core_0_iram0_recording_wr_1().bit()),
+                &self.core_0_iram0_recording_wr_1(),
             )
             .field(
                 "core_0_iram0_recording_loadstore_1",
-                &format_args!("{}", self.core_0_iram0_recording_loadstore_1().bit()),
+                &self.core_0_iram0_recording_loadstore_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_exception_monitor_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC;
 impl crate::RegisterSpec for CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC {
diff --git a/esp32c6/src/assist_debug/core_0_montr_ena.rs b/esp32c6/src/assist_debug/core_0_montr_ena.rs
index fc8ca8d601..90aa60feec 100644
--- a/esp32c6/src/assist_debug/core_0_montr_ena.rs
+++ b/esp32c6/src/assist_debug/core_0_montr_ena.rs
@@ -118,61 +118,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_MONTR_ENA")
             .field(
                 "core_0_area_dram0_0_rd_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_ena().bit()),
+                &self.core_0_area_dram0_0_rd_ena(),
             )
             .field(
                 "core_0_area_dram0_0_wr_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_ena().bit()),
+                &self.core_0_area_dram0_0_wr_ena(),
             )
             .field(
                 "core_0_area_dram0_1_rd_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_ena().bit()),
+                &self.core_0_area_dram0_1_rd_ena(),
             )
             .field(
                 "core_0_area_dram0_1_wr_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_rd_ena",
-                &format_args!("{}", self.core_0_area_pif_0_rd_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_wr_ena",
-                &format_args!("{}", self.core_0_area_pif_0_wr_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_rd_ena",
-                &format_args!("{}", self.core_0_area_pif_1_rd_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_wr_ena",
-                &format_args!("{}", self.core_0_area_pif_1_wr_ena().bit()),
-            )
-            .field(
-                "core_0_sp_spill_min_ena",
-                &format_args!("{}", self.core_0_sp_spill_min_ena().bit()),
-            )
-            .field(
-                "core_0_sp_spill_max_ena",
-                &format_args!("{}", self.core_0_sp_spill_max_ena().bit()),
+                &self.core_0_area_dram0_1_wr_ena(),
             )
+            .field("core_0_area_pif_0_rd_ena", &self.core_0_area_pif_0_rd_ena())
+            .field("core_0_area_pif_0_wr_ena", &self.core_0_area_pif_0_wr_ena())
+            .field("core_0_area_pif_1_rd_ena", &self.core_0_area_pif_1_rd_ena())
+            .field("core_0_area_pif_1_wr_ena", &self.core_0_area_pif_1_wr_ena())
+            .field("core_0_sp_spill_min_ena", &self.core_0_sp_spill_min_ena())
+            .field("core_0_sp_spill_max_ena", &self.core_0_sp_spill_max_ena())
             .field(
                 "core_0_iram0_exception_monitor_ena",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_ena().bit()),
+                &self.core_0_iram0_exception_monitor_ena(),
             )
             .field(
                 "core_0_dram0_exception_monitor_ena",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_ena().bit()),
+                &self.core_0_dram0_exception_monitor_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_MONTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core0 dram0 area0 read monitor enable"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/core_0_rcd_en.rs b/esp32c6/src/assist_debug/core_0_rcd_en.rs
index c32ca92cbc..8a365dc63d 100644
--- a/esp32c6/src/assist_debug/core_0_rcd_en.rs
+++ b/esp32c6/src/assist_debug/core_0_rcd_en.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_EN")
-            .field(
-                "core_0_rcd_recorden",
-                &format_args!("{}", self.core_0_rcd_recorden().bit()),
-            )
-            .field(
-                "core_0_rcd_pdebugen",
-                &format_args!("{}", self.core_0_rcd_pdebugen().bit()),
-            )
+            .field("core_0_rcd_recorden", &self.core_0_rcd_recorden())
+            .field("core_0_rcd_pdebugen", &self.core_0_rcd_pdebugen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable record PC"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/core_0_rcd_pdebugpc.rs b/esp32c6/src/assist_debug/core_0_rcd_pdebugpc.rs
index 57525f3096..f683fc645a 100644
--- a/esp32c6/src/assist_debug/core_0_rcd_pdebugpc.rs
+++ b/esp32c6/src/assist_debug/core_0_rcd_pdebugpc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGPC")
-            .field(
-                "core_0_rcd_pdebugpc",
-                &format_args!("{}", self.core_0_rcd_pdebugpc().bits()),
-            )
+            .field("core_0_rcd_pdebugpc", &self.core_0_rcd_pdebugpc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGPC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugpc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGPC_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGPC_SPEC {
diff --git a/esp32c6/src/assist_debug/core_0_rcd_pdebugsp.rs b/esp32c6/src/assist_debug/core_0_rcd_pdebugsp.rs
index 5299a97c98..acd394b30c 100644
--- a/esp32c6/src/assist_debug/core_0_rcd_pdebugsp.rs
+++ b/esp32c6/src/assist_debug/core_0_rcd_pdebugsp.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGSP")
-            .field(
-                "core_0_rcd_pdebugsp",
-                &format_args!("{}", self.core_0_rcd_pdebugsp().bits()),
-            )
+            .field("core_0_rcd_pdebugsp", &self.core_0_rcd_pdebugsp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGSP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugsp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGSP_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGSP_SPEC {
diff --git a/esp32c6/src/assist_debug/core_0_sp_max.rs b/esp32c6/src/assist_debug/core_0_sp_max.rs
index 551ad6e6e3..33cb4259d1 100644
--- a/esp32c6/src/assist_debug/core_0_sp_max.rs
+++ b/esp32c6/src/assist_debug/core_0_sp_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_MAX")
-            .field(
-                "core_0_sp_max",
-                &format_args!("{}", self.core_0_sp_max().bits()),
-            )
+            .field("core_0_sp_max", &self.core_0_sp_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - core0 sp pc status register"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/core_0_sp_min.rs b/esp32c6/src/assist_debug/core_0_sp_min.rs
index 385b8a1a99..5ab4adde01 100644
--- a/esp32c6/src/assist_debug/core_0_sp_min.rs
+++ b/esp32c6/src/assist_debug/core_0_sp_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_MIN")
-            .field(
-                "core_0_sp_min",
-                &format_args!("{}", self.core_0_sp_min().bits()),
-            )
+            .field("core_0_sp_min", &self.core_0_sp_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - core0 sp region configuration regsiter"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/core_0_sp_pc.rs b/esp32c6/src/assist_debug/core_0_sp_pc.rs
index edb35da31e..a876b3c942 100644
--- a/esp32c6/src/assist_debug/core_0_sp_pc.rs
+++ b/esp32c6/src/assist_debug/core_0_sp_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_PC")
-            .field(
-                "core_0_sp_pc",
-                &format_args!("{}", self.core_0_sp_pc().bits()),
-            )
+            .field("core_0_sp_pc", &self.core_0_sp_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "stack monitor pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_sp_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_SP_PC_SPEC;
 impl crate::RegisterSpec for CORE_0_SP_PC_SPEC {
diff --git a/esp32c6/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs b/esp32c6/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
index 6fa0b6a1fb..e322997eda 100644
--- a/esp32c6/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
+++ b/esp32c6/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_x_iram0_dram0_limit_cycle_0",
-                &format_args!("{}", self.core_x_iram0_dram0_limit_cycle_0().bits()),
+                &self.core_x_iram0_dram0_limit_cycle_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - reg_core_x_iram0_dram0_limit_cycle_0"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs b/esp32c6/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
index 6c13f7a201..ec7f4d4ef5 100644
--- a/esp32c6/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
+++ b/esp32c6/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_x_iram0_dram0_limit_cycle_1",
-                &format_args!("{}", self.core_x_iram0_dram0_limit_cycle_1().bits()),
+                &self.core_x_iram0_dram0_limit_cycle_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - reg_core_x_iram0_dram0_limit_cycle_1"]
     #[inline(always)]
diff --git a/esp32c6/src/assist_debug/date.rs b/esp32c6/src/assist_debug/date.rs
index 38bb1c07f8..3bd016a008 100644
--- a/esp32c6/src/assist_debug/date.rs
+++ b/esp32c6/src/assist_debug/date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "assist_debug_date",
-                &format_args!("{}", self.assist_debug_date().bits()),
-            )
+            .field("assist_debug_date", &self.assist_debug_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - version register"]
     #[inline(always)]
diff --git a/esp32c6/src/atomic/addr_lock.rs b/esp32c6/src/atomic/addr_lock.rs
index 569a04953f..a4ee7da2a1 100644
--- a/esp32c6/src/atomic/addr_lock.rs
+++ b/esp32c6/src/atomic/addr_lock.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR_LOCK")
-            .field("lock", &format_args!("{}", self.lock().bits()))
+            .field("lock", &self.lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - read to acquire hardware lock, write to release hardware lock"]
     #[inline(always)]
diff --git a/esp32c6/src/atomic/counter.rs b/esp32c6/src/atomic/counter.rs
index 047a54918d..6ea740a1da 100644
--- a/esp32c6/src/atomic/counter.rs
+++ b/esp32c6/src/atomic/counter.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COUNTER")
-            .field(
-                "wait_counter",
-                &format_args!("{}", self.wait_counter().bits()),
-            )
+            .field("wait_counter", &self.wait_counter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COUNTER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - delay counter"]
     #[inline(always)]
diff --git a/esp32c6/src/atomic/lock_status.rs b/esp32c6/src/atomic/lock_status.rs
index d0b8c05653..083741517b 100644
--- a/esp32c6/src/atomic/lock_status.rs
+++ b/esp32c6/src/atomic/lock_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOCK_STATUS")
-            .field(
-                "lock_status",
-                &format_args!("{}", self.lock_status().bits()),
-            )
+            .field("lock_status", &self.lock_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOCK_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "lock status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lock_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOCK_STATUS_SPEC;
 impl crate::RegisterSpec for LOCK_STATUS_SPEC {
diff --git a/esp32c6/src/atomic/lr_addr.rs b/esp32c6/src/atomic/lr_addr.rs
index 3740f167ed..1b5b0fe246 100644
--- a/esp32c6/src/atomic/lr_addr.rs
+++ b/esp32c6/src/atomic/lr_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LR_ADDR")
-            .field(
-                "gloable_lr_addr",
-                &format_args!("{}", self.gloable_lr_addr().bits()),
-            )
+            .field("gloable_lr_addr", &self.gloable_lr_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LR_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - backup gloable address"]
     #[inline(always)]
diff --git a/esp32c6/src/atomic/lr_value.rs b/esp32c6/src/atomic/lr_value.rs
index 32cc691d3f..f71b0878c1 100644
--- a/esp32c6/src/atomic/lr_value.rs
+++ b/esp32c6/src/atomic/lr_value.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LR_VALUE")
-            .field(
-                "gloable_lr_value",
-                &format_args!("{}", self.gloable_lr_value().bits()),
-            )
+            .field("gloable_lr_value", &self.gloable_lr_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LR_VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - backup gloable value"]
     #[inline(always)]
diff --git a/esp32c6/src/dma/ahb_test.rs b/esp32c6/src/dma/ahb_test.rs
index 28c330c261..8358a35c42 100644
--- a/esp32c6/src/dma/ahb_test.rs
+++ b/esp32c6/src/dma/ahb_test.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_TEST")
-            .field(
-                "ahb_testmode",
-                &format_args!("{}", self.ahb_testmode().bits()),
-            )
-            .field(
-                "ahb_testaddr",
-                &format_args!("{}", self.ahb_testaddr().bits()),
-            )
+            .field("ahb_testmode", &self.ahb_testmode())
+            .field("ahb_testaddr", &self.ahb_testaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_TEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - reserved"]
     #[inline(always)]
diff --git a/esp32c6/src/dma/ch/in_conf0.rs b/esp32c6/src/dma/ch/in_conf0.rs
index 54509ddb71..297d1f81df 100644
--- a/esp32c6/src/dma/ch/in_conf0.rs
+++ b/esp32c6/src/dma/ch/in_conf0.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF0")
-            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
-            .field(
-                "in_loop_test",
-                &format_args!("{}", self.in_loop_test().bit()),
-            )
-            .field(
-                "indscr_burst_en",
-                &format_args!("{}", self.indscr_burst_en().bit()),
-            )
-            .field(
-                "in_data_burst_en",
-                &format_args!("{}", self.in_data_burst_en().bit()),
-            )
-            .field(
-                "mem_trans_en",
-                &format_args!("{}", self.mem_trans_en().bit()),
-            )
-            .field("in_etm_en", &format_args!("{}", self.in_etm_en().bit()))
+            .field("in_rst", &self.in_rst())
+            .field("in_loop_test", &self.in_loop_test())
+            .field("indscr_burst_en", &self.indscr_burst_en())
+            .field("in_data_burst_en", &self.in_data_burst_en())
+            .field("mem_trans_en", &self.mem_trans_en())
+            .field("in_etm_en", &self.in_etm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
     #[inline(always)]
diff --git a/esp32c6/src/dma/ch/in_conf1.rs b/esp32c6/src/dma/ch/in_conf1.rs
index 1da8b38f0b..d95da0040b 100644
--- a/esp32c6/src/dma/ch/in_conf1.rs
+++ b/esp32c6/src/dma/ch/in_conf1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF1")
-            .field(
-                "in_check_owner",
-                &format_args!("{}", self.in_check_owner().bit()),
-            )
+            .field("in_check_owner", &self.in_check_owner())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
diff --git a/esp32c6/src/dma/ch/in_dscr.rs b/esp32c6/src/dma/ch/in_dscr.rs
index 3d348a76f4..e70d15df66 100644
--- a/esp32c6/src/dma/ch/in_dscr.rs
+++ b/esp32c6/src/dma/ch/in_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR")
-            .field(
-                "inlink_dscr",
-                &format_args!("{}", self.inlink_dscr().bits()),
-            )
+            .field("inlink_dscr", &self.inlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_SPEC;
 impl crate::RegisterSpec for IN_DSCR_SPEC {
diff --git a/esp32c6/src/dma/ch/in_dscr_bf0.rs b/esp32c6/src/dma/ch/in_dscr_bf0.rs
index e3023e2221..fca80e02f8 100644
--- a/esp32c6/src/dma/ch/in_dscr_bf0.rs
+++ b/esp32c6/src/dma/ch/in_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF0")
-            .field(
-                "inlink_dscr_bf0",
-                &format_args!("{}", self.inlink_dscr_bf0().bits()),
-            )
+            .field("inlink_dscr_bf0", &self.inlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for IN_DSCR_BF0_SPEC {
diff --git a/esp32c6/src/dma/ch/in_dscr_bf1.rs b/esp32c6/src/dma/ch/in_dscr_bf1.rs
index 457ee1455f..832bf9b92c 100644
--- a/esp32c6/src/dma/ch/in_dscr_bf1.rs
+++ b/esp32c6/src/dma/ch/in_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF1")
-            .field(
-                "inlink_dscr_bf1",
-                &format_args!("{}", self.inlink_dscr_bf1().bits()),
-            )
+            .field("inlink_dscr_bf1", &self.inlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The second-to-last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for IN_DSCR_BF1_SPEC {
diff --git a/esp32c6/src/dma/ch/in_err_eof_des_addr.rs b/esp32c6/src/dma/ch/in_err_eof_des_addr.rs
index 037171f572..63b8c75ca0 100644
--- a/esp32c6/src/dma/ch/in_err_eof_des_addr.rs
+++ b/esp32c6/src/dma/ch/in_err_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_ERR_EOF_DES_ADDR")
-            .field(
-                "in_err_eof_des_addr",
-                &format_args!("{}", self.in_err_eof_des_addr().bits()),
-            )
+            .field("in_err_eof_des_addr", &self.in_err_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_ERR_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Inlink descriptor address when errors occur of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_ERR_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_SPEC {
diff --git a/esp32c6/src/dma/ch/in_link.rs b/esp32c6/src/dma/ch/in_link.rs
index 493e509190..849449a9b6 100644
--- a/esp32c6/src/dma/ch/in_link.rs
+++ b/esp32c6/src/dma/ch/in_link.rs
@@ -39,24 +39,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_LINK")
-            .field(
-                "inlink_addr",
-                &format_args!("{}", self.inlink_addr().bits()),
-            )
-            .field(
-                "inlink_auto_ret",
-                &format_args!("{}", self.inlink_auto_ret().bit()),
-            )
-            .field("inlink_park", &format_args!("{}", self.inlink_park().bit()))
+            .field("inlink_addr", &self.inlink_addr())
+            .field("inlink_auto_ret", &self.inlink_auto_ret())
+            .field("inlink_park", &self.inlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32c6/src/dma/ch/in_peri_sel.rs b/esp32c6/src/dma/ch/in_peri_sel.rs
index 4f7221716d..9a7f9cc573 100644
--- a/esp32c6/src/dma/ch/in_peri_sel.rs
+++ b/esp32c6/src/dma/ch/in_peri_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_PERI_SEL")
-            .field(
-                "peri_in_sel",
-                &format_args!("{}", self.peri_in_sel().bits()),
-            )
+            .field("peri_in_sel", &self.peri_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_PERI_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy"]
     #[inline(always)]
diff --git a/esp32c6/src/dma/ch/in_pop.rs b/esp32c6/src/dma/ch/in_pop.rs
index b9c87113b1..368276237f 100644
--- a/esp32c6/src/dma/ch/in_pop.rs
+++ b/esp32c6/src/dma/ch/in_pop.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_POP")
-            .field(
-                "infifo_rdata",
-                &format_args!("{}", self.infifo_rdata().bits()),
-            )
+            .field("infifo_rdata", &self.infifo_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_POP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."]
     #[inline(always)]
diff --git a/esp32c6/src/dma/ch/in_pri.rs b/esp32c6/src/dma/ch/in_pri.rs
index 83843e1ff5..1d4409ec1b 100644
--- a/esp32c6/src/dma/ch/in_pri.rs
+++ b/esp32c6/src/dma/ch/in_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_PRI")
-            .field("rx_pri", &format_args!("{}", self.rx_pri().bits()))
+            .field("rx_pri", &self.rx_pri())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value the higher of the priority."]
     #[inline(always)]
diff --git a/esp32c6/src/dma/ch/in_state.rs b/esp32c6/src/dma/ch/in_state.rs
index 6c91ac50d7..83cb3124d8 100644
--- a/esp32c6/src/dma/ch/in_state.rs
+++ b/esp32c6/src/dma/ch/in_state.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_STATE")
-            .field(
-                "inlink_dscr_addr",
-                &format_args!("{}", self.inlink_dscr_addr().bits()),
-            )
-            .field(
-                "in_dscr_state",
-                &format_args!("{}", self.in_dscr_state().bits()),
-            )
-            .field("in_state", &format_args!("{}", self.in_state().bits()))
+            .field("inlink_dscr_addr", &self.inlink_dscr_addr())
+            .field("in_dscr_state", &self.in_dscr_state())
+            .field("in_state", &self.in_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_STATE_SPEC;
 impl crate::RegisterSpec for IN_STATE_SPEC {
diff --git a/esp32c6/src/dma/ch/in_suc_eof_des_addr.rs b/esp32c6/src/dma/ch/in_suc_eof_des_addr.rs
index 2b0b4e378a..bd974ca71c 100644
--- a/esp32c6/src/dma/ch/in_suc_eof_des_addr.rs
+++ b/esp32c6/src/dma/ch/in_suc_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_SUC_EOF_DES_ADDR")
-            .field(
-                "in_suc_eof_des_addr",
-                &format_args!("{}", self.in_suc_eof_des_addr().bits()),
-            )
+            .field("in_suc_eof_des_addr", &self.in_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SUC_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Inlink descriptor address when EOF occurs of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SUC_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_SPEC {
diff --git a/esp32c6/src/dma/ch/infifo_status.rs b/esp32c6/src/dma/ch/infifo_status.rs
index 083b1ccdc7..065cf9f3fe 100644
--- a/esp32c6/src/dma/ch/infifo_status.rs
+++ b/esp32c6/src/dma/ch/infifo_status.rs
@@ -62,41 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INFIFO_STATUS")
-            .field("infifo_full", &format_args!("{}", self.infifo_full().bit()))
-            .field(
-                "infifo_empty",
-                &format_args!("{}", self.infifo_empty().bit()),
-            )
-            .field("infifo_cnt", &format_args!("{}", self.infifo_cnt().bits()))
-            .field(
-                "in_remain_under_1b",
-                &format_args!("{}", self.in_remain_under_1b().bit()),
-            )
-            .field(
-                "in_remain_under_2b",
-                &format_args!("{}", self.in_remain_under_2b().bit()),
-            )
-            .field(
-                "in_remain_under_3b",
-                &format_args!("{}", self.in_remain_under_3b().bit()),
-            )
-            .field(
-                "in_remain_under_4b",
-                &format_args!("{}", self.in_remain_under_4b().bit()),
-            )
-            .field(
-                "in_buf_hungry",
-                &format_args!("{}", self.in_buf_hungry().bit()),
-            )
+            .field("infifo_full", &self.infifo_full())
+            .field("infifo_empty", &self.infifo_empty())
+            .field("infifo_cnt", &self.infifo_cnt())
+            .field("in_remain_under_1b", &self.in_remain_under_1b())
+            .field("in_remain_under_2b", &self.in_remain_under_2b())
+            .field("in_remain_under_3b", &self.in_remain_under_3b())
+            .field("in_remain_under_4b", &self.in_remain_under_4b())
+            .field("in_buf_hungry", &self.in_buf_hungry())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive FIFO status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for INFIFO_STATUS_SPEC {
diff --git a/esp32c6/src/dma/ch/out_conf0.rs b/esp32c6/src/dma/ch/out_conf0.rs
index d92b9bfec5..14a2911000 100644
--- a/esp32c6/src/dma/ch/out_conf0.rs
+++ b/esp32c6/src/dma/ch/out_conf0.rs
@@ -71,37 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CONF0")
-            .field("out_rst", &format_args!("{}", self.out_rst().bit()))
-            .field(
-                "out_loop_test",
-                &format_args!("{}", self.out_loop_test().bit()),
-            )
-            .field(
-                "out_auto_wrback",
-                &format_args!("{}", self.out_auto_wrback().bit()),
-            )
-            .field(
-                "out_eof_mode",
-                &format_args!("{}", self.out_eof_mode().bit()),
-            )
-            .field(
-                "outdscr_burst_en",
-                &format_args!("{}", self.outdscr_burst_en().bit()),
-            )
-            .field(
-                "out_data_burst_en",
-                &format_args!("{}", self.out_data_burst_en().bit()),
-            )
-            .field("out_etm_en", &format_args!("{}", self.out_etm_en().bit()))
+            .field("out_rst", &self.out_rst())
+            .field("out_loop_test", &self.out_loop_test())
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("out_eof_mode", &self.out_eof_mode())
+            .field("outdscr_burst_en", &self.outdscr_burst_en())
+            .field("out_data_burst_en", &self.out_data_burst_en())
+            .field("out_etm_en", &self.out_etm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer."]
     #[inline(always)]
diff --git a/esp32c6/src/dma/ch/out_conf1.rs b/esp32c6/src/dma/ch/out_conf1.rs
index 8d9753a4b9..0ed936f2fa 100644
--- a/esp32c6/src/dma/ch/out_conf1.rs
+++ b/esp32c6/src/dma/ch/out_conf1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CONF1")
-            .field(
-                "out_check_owner",
-                &format_args!("{}", self.out_check_owner().bit()),
-            )
+            .field("out_check_owner", &self.out_check_owner())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
diff --git a/esp32c6/src/dma/ch/out_dscr.rs b/esp32c6/src/dma/ch/out_dscr.rs
index bfbfd6cd82..e64e982337 100644
--- a/esp32c6/src/dma/ch/out_dscr.rs
+++ b/esp32c6/src/dma/ch/out_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR")
-            .field(
-                "outlink_dscr",
-                &format_args!("{}", self.outlink_dscr().bits()),
-            )
+            .field("outlink_dscr", &self.outlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_SPEC {
diff --git a/esp32c6/src/dma/ch/out_dscr_bf0.rs b/esp32c6/src/dma/ch/out_dscr_bf0.rs
index 95ef8f687e..f5fec0ba50 100644
--- a/esp32c6/src/dma/ch/out_dscr_bf0.rs
+++ b/esp32c6/src/dma/ch/out_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR_BF0")
-            .field(
-                "outlink_dscr_bf0",
-                &format_args!("{}", self.outlink_dscr_bf0().bits()),
-            )
+            .field("outlink_dscr_bf0", &self.outlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_BF0_SPEC {
diff --git a/esp32c6/src/dma/ch/out_dscr_bf1.rs b/esp32c6/src/dma/ch/out_dscr_bf1.rs
index f75439c16c..4339b9c9b9 100644
--- a/esp32c6/src/dma/ch/out_dscr_bf1.rs
+++ b/esp32c6/src/dma/ch/out_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR_BF1")
-            .field(
-                "outlink_dscr_bf1",
-                &format_args!("{}", self.outlink_dscr_bf1().bits()),
-            )
+            .field("outlink_dscr_bf1", &self.outlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The second-to-last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_BF1_SPEC {
diff --git a/esp32c6/src/dma/ch/out_eof_bfr_des_addr.rs b/esp32c6/src/dma/ch/out_eof_bfr_des_addr.rs
index 32fea6abcc..08cac753ad 100644
--- a/esp32c6/src/dma/ch/out_eof_bfr_des_addr.rs
+++ b/esp32c6/src/dma/ch/out_eof_bfr_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_BFR_DES_ADDR")
-            .field(
-                "out_eof_bfr_des_addr",
-                &format_args!("{}", self.out_eof_bfr_des_addr().bits()),
-            )
+            .field("out_eof_bfr_des_addr", &self.out_eof_bfr_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_BFR_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The last outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_bfr_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_BFR_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_SPEC {
diff --git a/esp32c6/src/dma/ch/out_eof_des_addr.rs b/esp32c6/src/dma/ch/out_eof_des_addr.rs
index b85ba2ebbd..1049f7aa97 100644
--- a/esp32c6/src/dma/ch/out_eof_des_addr.rs
+++ b/esp32c6/src/dma/ch/out_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_DES_ADDR")
-            .field(
-                "out_eof_des_addr",
-                &format_args!("{}", self.out_eof_des_addr().bits()),
-            )
+            .field("out_eof_des_addr", &self.out_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_DES_ADDR_SPEC {
diff --git a/esp32c6/src/dma/ch/out_link.rs b/esp32c6/src/dma/ch/out_link.rs
index 5ecdbc1ff7..f05d845e6e 100644
--- a/esp32c6/src/dma/ch/out_link.rs
+++ b/esp32c6/src/dma/ch/out_link.rs
@@ -30,23 +30,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_LINK")
-            .field(
-                "outlink_addr",
-                &format_args!("{}", self.outlink_addr().bits()),
-            )
-            .field(
-                "outlink_park",
-                &format_args!("{}", self.outlink_park().bit()),
-            )
+            .field("outlink_addr", &self.outlink_addr())
+            .field("outlink_park", &self.outlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32c6/src/dma/ch/out_peri_sel.rs b/esp32c6/src/dma/ch/out_peri_sel.rs
index 23a7e68422..c7559b2d85 100644
--- a/esp32c6/src/dma/ch/out_peri_sel.rs
+++ b/esp32c6/src/dma/ch/out_peri_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PERI_SEL")
-            .field(
-                "peri_out_sel",
-                &format_args!("{}", self.peri_out_sel().bits()),
-            )
+            .field("peri_out_sel", &self.peri_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PERI_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy"]
     #[inline(always)]
diff --git a/esp32c6/src/dma/ch/out_pri.rs b/esp32c6/src/dma/ch/out_pri.rs
index 7ea88ef349..5397e69678 100644
--- a/esp32c6/src/dma/ch/out_pri.rs
+++ b/esp32c6/src/dma/ch/out_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PRI")
-            .field("tx_pri", &format_args!("{}", self.tx_pri().bits()))
+            .field("tx_pri", &self.tx_pri())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value the higher of the priority."]
     #[inline(always)]
diff --git a/esp32c6/src/dma/ch/out_push.rs b/esp32c6/src/dma/ch/out_push.rs
index 80dba16ac8..bb1e623d52 100644
--- a/esp32c6/src/dma/ch/out_push.rs
+++ b/esp32c6/src/dma/ch/out_push.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PUSH")
-            .field(
-                "outfifo_wdata",
-                &format_args!("{}", self.outfifo_wdata().bits()),
-            )
+            .field("outfifo_wdata", &self.outfifo_wdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PUSH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."]
     #[inline(always)]
diff --git a/esp32c6/src/dma/ch/out_state.rs b/esp32c6/src/dma/ch/out_state.rs
index 32eb3ca4e8..9711790741 100644
--- a/esp32c6/src/dma/ch/out_state.rs
+++ b/esp32c6/src/dma/ch/out_state.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_STATE")
-            .field(
-                "outlink_dscr_addr",
-                &format_args!("{}", self.outlink_dscr_addr().bits()),
-            )
-            .field(
-                "out_dscr_state",
-                &format_args!("{}", self.out_dscr_state().bits()),
-            )
-            .field("out_state", &format_args!("{}", self.out_state().bits()))
+            .field("outlink_dscr_addr", &self.outlink_dscr_addr())
+            .field("out_dscr_state", &self.out_dscr_state())
+            .field("out_state", &self.out_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transmit status of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_STATE_SPEC;
 impl crate::RegisterSpec for OUT_STATE_SPEC {
diff --git a/esp32c6/src/dma/ch/outfifo_status.rs b/esp32c6/src/dma/ch/outfifo_status.rs
index 7bdea07321..dc478ff060 100644
--- a/esp32c6/src/dma/ch/outfifo_status.rs
+++ b/esp32c6/src/dma/ch/outfifo_status.rs
@@ -55,43 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTFIFO_STATUS")
-            .field(
-                "outfifo_full",
-                &format_args!("{}", self.outfifo_full().bit()),
-            )
-            .field(
-                "outfifo_empty",
-                &format_args!("{}", self.outfifo_empty().bit()),
-            )
-            .field(
-                "outfifo_cnt",
-                &format_args!("{}", self.outfifo_cnt().bits()),
-            )
-            .field(
-                "out_remain_under_1b",
-                &format_args!("{}", self.out_remain_under_1b().bit()),
-            )
-            .field(
-                "out_remain_under_2b",
-                &format_args!("{}", self.out_remain_under_2b().bit()),
-            )
-            .field(
-                "out_remain_under_3b",
-                &format_args!("{}", self.out_remain_under_3b().bit()),
-            )
-            .field(
-                "out_remain_under_4b",
-                &format_args!("{}", self.out_remain_under_4b().bit()),
-            )
+            .field("outfifo_full", &self.outfifo_full())
+            .field("outfifo_empty", &self.outfifo_empty())
+            .field("outfifo_cnt", &self.outfifo_cnt())
+            .field("out_remain_under_1b", &self.out_remain_under_1b())
+            .field("out_remain_under_2b", &self.out_remain_under_2b())
+            .field("out_remain_under_3b", &self.out_remain_under_3b())
+            .field("out_remain_under_4b", &self.out_remain_under_4b())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transmit FIFO status of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for OUTFIFO_STATUS_SPEC {
diff --git a/esp32c6/src/dma/date.rs b/esp32c6/src/dma/date.rs
index 0d83c02a03..9bc6685c81 100644
--- a/esp32c6/src/dma/date.rs
+++ b/esp32c6/src/dma/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/dma/in_int_ch/ena.rs b/esp32c6/src/dma/in_int_ch/ena.rs
index f845f9df75..5dcfe467fd 100644
--- a/esp32c6/src/dma/in_int_ch/ena.rs
+++ b/esp32c6/src/dma/in_int_ch/ena.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENA")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c6/src/dma/in_int_ch/raw.rs b/esp32c6/src/dma/in_int_ch/raw.rs
index cbf64a2647..6891a0e659 100644
--- a/esp32c6/src/dma/in_int_ch/raw.rs
+++ b/esp32c6/src/dma/in_int_ch/raw.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RAW")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
     #[inline(always)]
diff --git a/esp32c6/src/dma/in_int_ch/st.rs b/esp32c6/src/dma/in_int_ch/st.rs
index a3bc9f8f8f..0a0bf35524 100644
--- a/esp32c6/src/dma/in_int_ch/st.rs
+++ b/esp32c6/src/dma/in_int_ch/st.rs
@@ -55,25 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ST")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ST_SPEC;
 impl crate::RegisterSpec for ST_SPEC {
diff --git a/esp32c6/src/dma/misc_conf.rs b/esp32c6/src/dma/misc_conf.rs
index 60bc8667fa..7b16c52f7a 100644
--- a/esp32c6/src/dma/misc_conf.rs
+++ b/esp32c6/src/dma/misc_conf.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC_CONF")
-            .field(
-                "ahbm_rst_inter",
-                &format_args!("{}", self.ahbm_rst_inter().bit()),
-            )
-            .field("arb_pri_dis", &format_args!("{}", self.arb_pri_dis().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("ahbm_rst_inter", &self.ahbm_rst_inter())
+            .field("arb_pri_dis", &self.arb_pri_dis())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit then clear this bit to reset the internal ahb FSM."]
     #[inline(always)]
diff --git a/esp32c6/src/dma/out_int_ch/ena.rs b/esp32c6/src/dma/out_int_ch/ena.rs
index 9403656d3a..01a68f37f2 100644
--- a/esp32c6/src/dma/out_int_ch/ena.rs
+++ b/esp32c6/src/dma/out_int_ch/ena.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENA")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c6/src/dma/out_int_ch/raw.rs b/esp32c6/src/dma/out_int_ch/raw.rs
index bfd53406bd..f5979fc55a 100644
--- a/esp32c6/src/dma/out_int_ch/raw.rs
+++ b/esp32c6/src/dma/out_int_ch/raw.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RAW")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
     #[inline(always)]
diff --git a/esp32c6/src/dma/out_int_ch/st.rs b/esp32c6/src/dma/out_int_ch/st.rs
index a10e575b53..fff916b01d 100644
--- a/esp32c6/src/dma/out_int_ch/st.rs
+++ b/esp32c6/src/dma/out_int_ch/st.rs
@@ -48,27 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ST")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ST_SPEC;
 impl crate::RegisterSpec for ST_SPEC {
diff --git a/esp32c6/src/ds/box_mem.rs b/esp32c6/src/ds/box_mem.rs
index cbc5e04146..af6085c630 100644
--- a/esp32c6/src/ds/box_mem.rs
+++ b/esp32c6/src/ds/box_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BOX_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores BOX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`box_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`box_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BOX_MEM_SPEC;
diff --git a/esp32c6/src/ds/date.rs b/esp32c6/src/ds/date.rs
index 0b73492be1..97e7b03565 100644
--- a/esp32c6/src/ds/date.rs
+++ b/esp32c6/src/ds/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/ds/iv_mem.rs b/esp32c6/src/ds/iv_mem.rs
index 3f93dc26b7..5bef1d4a62 100644
--- a/esp32c6/src/ds/iv_mem.rs
+++ b/esp32c6/src/ds/iv_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IV_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores IV\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iv_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iv_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IV_MEM_SPEC;
diff --git a/esp32c6/src/ds/m_mem.rs b/esp32c6/src/ds/m_mem.rs
index feb455544d..34f49f49a5 100644
--- a/esp32c6/src/ds/m_mem.rs
+++ b/esp32c6/src/ds/m_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct M_MEM_SPEC;
diff --git a/esp32c6/src/ds/query_busy.rs b/esp32c6/src/ds/query_busy.rs
index 28c895caf6..ab7489a518 100644
--- a/esp32c6/src/ds/query_busy.rs
+++ b/esp32c6/src/ds/query_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_BUSY")
-            .field("query_busy", &format_args!("{}", self.query_busy().bit()))
+            .field("query_busy", &self.query_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DS query busy register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_BUSY_SPEC;
 impl crate::RegisterSpec for QUERY_BUSY_SPEC {
diff --git a/esp32c6/src/ds/query_check.rs b/esp32c6/src/ds/query_check.rs
index 278370e20f..e1d1c02fe7 100644
--- a/esp32c6/src/ds/query_check.rs
+++ b/esp32c6/src/ds/query_check.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_CHECK")
-            .field("md_error", &format_args!("{}", self.md_error().bit()))
-            .field("padding_bad", &format_args!("{}", self.padding_bad().bit()))
+            .field("md_error", &self.md_error())
+            .field("padding_bad", &self.padding_bad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_CHECK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DS query check result register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_check::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_CHECK_SPEC;
 impl crate::RegisterSpec for QUERY_CHECK_SPEC {
diff --git a/esp32c6/src/ds/query_key_wrong.rs b/esp32c6/src/ds/query_key_wrong.rs
index 30a1e7aae4..7ce4bf99a0 100644
--- a/esp32c6/src/ds/query_key_wrong.rs
+++ b/esp32c6/src/ds/query_key_wrong.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_KEY_WRONG")
-            .field(
-                "query_key_wrong",
-                &format_args!("{}", self.query_key_wrong().bits()),
-            )
+            .field("query_key_wrong", &self.query_key_wrong())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_KEY_WRONG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DS query key-wrong counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_key_wrong::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_KEY_WRONG_SPEC;
 impl crate::RegisterSpec for QUERY_KEY_WRONG_SPEC {
diff --git a/esp32c6/src/ds/rb_mem.rs b/esp32c6/src/ds/rb_mem.rs
index 601da234a3..c7e0a211be 100644
--- a/esp32c6/src/ds/rb_mem.rs
+++ b/esp32c6/src/ds/rb_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RB_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores Rb\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rb_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rb_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RB_MEM_SPEC;
diff --git a/esp32c6/src/ds/x_mem.rs b/esp32c6/src/ds/x_mem.rs
index b018ad10ba..5cfb1f6eb6 100644
--- a/esp32c6/src/ds/x_mem.rs
+++ b/esp32c6/src/ds/x_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<X_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores X\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`x_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`x_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct X_MEM_SPEC;
diff --git a/esp32c6/src/ds/y_mem.rs b/esp32c6/src/ds/y_mem.rs
index 00ad225968..3376d35f4e 100644
--- a/esp32c6/src/ds/y_mem.rs
+++ b/esp32c6/src/ds/y_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Y_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores Y\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Y_MEM_SPEC;
diff --git a/esp32c6/src/ds/z_mem.rs b/esp32c6/src/ds/z_mem.rs
index de03c7e5de..978b2c0d66 100644
--- a/esp32c6/src/ds/z_mem.rs
+++ b/esp32c6/src/ds/z_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Z_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Z_MEM_SPEC;
diff --git a/esp32c6/src/ecc/k_mem.rs b/esp32c6/src/ecc/k_mem.rs
index 0931b81173..8e55d12095 100644
--- a/esp32c6/src/ecc/k_mem.rs
+++ b/esp32c6/src/ecc/k_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<K_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores k.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`k_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`k_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct K_MEM_SPEC;
diff --git a/esp32c6/src/ecc/mult_conf.rs b/esp32c6/src/ecc/mult_conf.rs
index e9d48638ef..3e29648e1c 100644
--- a/esp32c6/src/ecc/mult_conf.rs
+++ b/esp32c6/src/ecc/mult_conf.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_CONF")
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("key_length", &format_args!("{}", self.key_length().bit()))
-            .field(
-                "security_mode",
-                &format_args!("{}", self.security_mode().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("work_mode", &format_args!("{}", self.work_mode().bits()))
-            .field(
-                "verification_result",
-                &format_args!("{}", self.verification_result().bit()),
-            )
-            .field(
-                "mem_clock_gate_force_on",
-                &format_args!("{}", self.mem_clock_gate_force_on().bit()),
-            )
+            .field("start", &self.start())
+            .field("key_length", &self.key_length())
+            .field("security_mode", &self.security_mode())
+            .field("clk_en", &self.clk_en())
+            .field("work_mode", &self.work_mode())
+            .field("verification_result", &self.verification_result())
+            .field("mem_clock_gate_force_on", &self.mem_clock_gate_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done."]
     #[inline(always)]
diff --git a/esp32c6/src/ecc/mult_date.rs b/esp32c6/src/ecc/mult_date.rs
index 57a6975d41..a9c75f8b6e 100644
--- a/esp32c6/src/ecc/mult_date.rs
+++ b/esp32c6/src/ecc/mult_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - ECC mult version control register"]
     #[inline(always)]
diff --git a/esp32c6/src/ecc/mult_int_ena.rs b/esp32c6/src/ecc/mult_int_ena.rs
index 0a756a4618..e98f881175 100644
--- a/esp32c6/src/ecc/mult_int_ena.rs
+++ b/esp32c6/src/ecc/mult_int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_INT_ENA")
-            .field("calc_done", &format_args!("{}", self.calc_done().bit()))
+            .field("calc_done", &self.calc_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the ecc_calc_done_int interrupt"]
     #[inline(always)]
diff --git a/esp32c6/src/ecc/mult_int_raw.rs b/esp32c6/src/ecc/mult_int_raw.rs
index ad5e442a59..0a76f6a144 100644
--- a/esp32c6/src/ecc/mult_int_raw.rs
+++ b/esp32c6/src/ecc/mult_int_raw.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_INT_RAW")
-            .field("calc_done", &format_args!("{}", self.calc_done().bit()))
+            .field("calc_done", &self.calc_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ECC interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MULT_INT_RAW_SPEC;
 impl crate::RegisterSpec for MULT_INT_RAW_SPEC {
diff --git a/esp32c6/src/ecc/mult_int_st.rs b/esp32c6/src/ecc/mult_int_st.rs
index 9fa4c84f14..599cde021a 100644
--- a/esp32c6/src/ecc/mult_int_st.rs
+++ b/esp32c6/src/ecc/mult_int_st.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_INT_ST")
-            .field("calc_done", &format_args!("{}", self.calc_done().bit()))
+            .field("calc_done", &self.calc_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ECC interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MULT_INT_ST_SPEC;
 impl crate::RegisterSpec for MULT_INT_ST_SPEC {
diff --git a/esp32c6/src/ecc/px_mem.rs b/esp32c6/src/ecc/px_mem.rs
index 3a8e843f61..3a24d84d16 100644
--- a/esp32c6/src/ecc/px_mem.rs
+++ b/esp32c6/src/ecc/px_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PX_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores Px.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`px_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`px_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PX_MEM_SPEC;
diff --git a/esp32c6/src/ecc/py_mem.rs b/esp32c6/src/ecc/py_mem.rs
index 8129141315..e5d383ac34 100644
--- a/esp32c6/src/ecc/py_mem.rs
+++ b/esp32c6/src/ecc/py_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PY_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores Py.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`py_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`py_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PY_MEM_SPEC;
diff --git a/esp32c6/src/efuse/clk.rs b/esp32c6/src/efuse/clk.rs
index 94aeed7312..b6041ccf31 100644
--- a/esp32c6/src/efuse/clk.rs
+++ b/esp32c6/src/efuse/clk.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK")
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_clk_force_on",
-                &format_args!("{}", self.mem_clk_force_on().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_clk_force_on", &self.mem_clk_force_on())
+            .field("mem_force_pu", &self.mem_force_pu())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to force eFuse SRAM into power-saving mode."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/cmd.rs b/esp32c6/src/efuse/cmd.rs
index 8dee79bc65..094d443be3 100644
--- a/esp32c6/src/efuse/cmd.rs
+++ b/esp32c6/src/efuse/cmd.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("read_cmd", &format_args!("{}", self.read_cmd().bit()))
-            .field("pgm_cmd", &format_args!("{}", self.pgm_cmd().bit()))
-            .field("blk_num", &format_args!("{}", self.blk_num().bits()))
+            .field("read_cmd", &self.read_cmd())
+            .field("pgm_cmd", &self.pgm_cmd())
+            .field("blk_num", &self.blk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to send read command."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/conf.rs b/esp32c6/src/efuse/conf.rs
index f37f5746e7..98e61dcbe3 100644
--- a/esp32c6/src/efuse/conf.rs
+++ b/esp32c6/src/efuse/conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("op_code", &format_args!("{}", self.op_code().bits()))
+            .field("op_code", &self.op_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - 0x5A5A: programming operation command 0x5AA5: read operation command."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/dac_conf.rs b/esp32c6/src/efuse/dac_conf.rs
index 46081e022e..e9db91d486 100644
--- a/esp32c6/src/efuse/dac_conf.rs
+++ b/esp32c6/src/efuse/dac_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DAC_CONF")
-            .field(
-                "dac_clk_div",
-                &format_args!("{}", self.dac_clk_div().bits()),
-            )
-            .field(
-                "dac_clk_pad_sel",
-                &format_args!("{}", self.dac_clk_pad_sel().bit()),
-            )
-            .field("dac_num", &format_args!("{}", self.dac_num().bits()))
-            .field("oe_clr", &format_args!("{}", self.oe_clr().bit()))
+            .field("dac_clk_div", &self.dac_clk_div())
+            .field("dac_clk_pad_sel", &self.dac_clk_pad_sel())
+            .field("dac_num", &self.dac_num())
+            .field("oe_clr", &self.oe_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DAC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Controls the division factor of the rising clock of the programming voltage."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/date.rs b/esp32c6/src/efuse/date.rs
index 1e4923d409..aeaa4fb92d 100644
--- a/esp32c6/src/efuse/date.rs
+++ b/esp32c6/src/efuse/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/efuse/int_ena.rs b/esp32c6/src/efuse/int_ena.rs
index 6386df2821..0020c7e668 100644
--- a/esp32c6/src/efuse/int_ena.rs
+++ b/esp32c6/src/efuse/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable signal for read_done interrupt."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/int_raw.rs b/esp32c6/src/efuse/int_raw.rs
index b69c288afb..efd8b89205 100644
--- a/esp32c6/src/efuse/int_raw.rs
+++ b/esp32c6/src/efuse/int_raw.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse raw interrupt register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32c6/src/efuse/int_st.rs b/esp32c6/src/efuse/int_st.rs
index 898ceb8e8b..efba508ff2 100644
--- a/esp32c6/src/efuse/int_st.rs
+++ b/esp32c6/src/efuse/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/efuse/pgm_check_value0.rs b/esp32c6/src/efuse/pgm_check_value0.rs
index 663f1a6b52..ab1a0f0553 100644
--- a/esp32c6/src/efuse/pgm_check_value0.rs
+++ b/esp32c6/src/efuse/pgm_check_value0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE0")
-            .field(
-                "pgm_rs_data_0",
-                &format_args!("{}", self.pgm_rs_data_0().bits()),
-            )
+            .field("pgm_rs_data_0", &self.pgm_rs_data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 0th 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/pgm_check_value1.rs b/esp32c6/src/efuse/pgm_check_value1.rs
index d7333c0b68..2190b87db3 100644
--- a/esp32c6/src/efuse/pgm_check_value1.rs
+++ b/esp32c6/src/efuse/pgm_check_value1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE1")
-            .field(
-                "pgm_rs_data_1",
-                &format_args!("{}", self.pgm_rs_data_1().bits()),
-            )
+            .field("pgm_rs_data_1", &self.pgm_rs_data_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 1st 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/pgm_check_value2.rs b/esp32c6/src/efuse/pgm_check_value2.rs
index ea8f275832..9f176182aa 100644
--- a/esp32c6/src/efuse/pgm_check_value2.rs
+++ b/esp32c6/src/efuse/pgm_check_value2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE2")
-            .field(
-                "pgm_rs_data_2",
-                &format_args!("{}", self.pgm_rs_data_2().bits()),
-            )
+            .field("pgm_rs_data_2", &self.pgm_rs_data_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 2nd 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/pgm_data0.rs b/esp32c6/src/efuse/pgm_data0.rs
index 99d1a39f3d..2fa0081de0 100644
--- a/esp32c6/src/efuse/pgm_data0.rs
+++ b/esp32c6/src/efuse/pgm_data0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA0")
-            .field("pgm_data_0", &format_args!("{}", self.pgm_data_0().bits()))
+            .field("pgm_data_0", &self.pgm_data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 0th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/pgm_data1.rs b/esp32c6/src/efuse/pgm_data1.rs
index dd5c818232..1fcd9bb4ec 100644
--- a/esp32c6/src/efuse/pgm_data1.rs
+++ b/esp32c6/src/efuse/pgm_data1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA1")
-            .field("pgm_data_1", &format_args!("{}", self.pgm_data_1().bits()))
+            .field("pgm_data_1", &self.pgm_data_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 1st 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/pgm_data2.rs b/esp32c6/src/efuse/pgm_data2.rs
index 9297097580..07fc1fa3b9 100644
--- a/esp32c6/src/efuse/pgm_data2.rs
+++ b/esp32c6/src/efuse/pgm_data2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA2")
-            .field("pgm_data_2", &format_args!("{}", self.pgm_data_2().bits()))
+            .field("pgm_data_2", &self.pgm_data_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 2nd 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/pgm_data3.rs b/esp32c6/src/efuse/pgm_data3.rs
index beb3114ecf..bf3f5ccec2 100644
--- a/esp32c6/src/efuse/pgm_data3.rs
+++ b/esp32c6/src/efuse/pgm_data3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA3")
-            .field("pgm_data_3", &format_args!("{}", self.pgm_data_3().bits()))
+            .field("pgm_data_3", &self.pgm_data_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 3rd 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/pgm_data4.rs b/esp32c6/src/efuse/pgm_data4.rs
index ab568669b6..8aea0c46cb 100644
--- a/esp32c6/src/efuse/pgm_data4.rs
+++ b/esp32c6/src/efuse/pgm_data4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA4")
-            .field("pgm_data_4", &format_args!("{}", self.pgm_data_4().bits()))
+            .field("pgm_data_4", &self.pgm_data_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 4th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/pgm_data5.rs b/esp32c6/src/efuse/pgm_data5.rs
index a563072d44..c09c8a828a 100644
--- a/esp32c6/src/efuse/pgm_data5.rs
+++ b/esp32c6/src/efuse/pgm_data5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA5")
-            .field("pgm_data_5", &format_args!("{}", self.pgm_data_5().bits()))
+            .field("pgm_data_5", &self.pgm_data_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 5th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/pgm_data6.rs b/esp32c6/src/efuse/pgm_data6.rs
index 3068ec971d..1c9e0c9011 100644
--- a/esp32c6/src/efuse/pgm_data6.rs
+++ b/esp32c6/src/efuse/pgm_data6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA6")
-            .field("pgm_data_6", &format_args!("{}", self.pgm_data_6().bits()))
+            .field("pgm_data_6", &self.pgm_data_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 6th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/pgm_data7.rs b/esp32c6/src/efuse/pgm_data7.rs
index 0087318233..b913c59fad 100644
--- a/esp32c6/src/efuse/pgm_data7.rs
+++ b/esp32c6/src/efuse/pgm_data7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA7")
-            .field("pgm_data_7", &format_args!("{}", self.pgm_data_7().bits()))
+            .field("pgm_data_7", &self.pgm_data_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 7th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/rd_key0_data0.rs b/esp32c6/src/efuse/rd_key0_data0.rs
index b4ee49df3a..66bdc7a995 100644
--- a/esp32c6/src/efuse/rd_key0_data0.rs
+++ b/esp32c6/src/efuse/rd_key0_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA0")
-            .field("key0_data0", &format_args!("{}", self.key0_data0().bits()))
+            .field("key0_data0", &self.key0_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA0_SPEC {
diff --git a/esp32c6/src/efuse/rd_key0_data1.rs b/esp32c6/src/efuse/rd_key0_data1.rs
index 1f8251375b..5efa9fd856 100644
--- a/esp32c6/src/efuse/rd_key0_data1.rs
+++ b/esp32c6/src/efuse/rd_key0_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA1")
-            .field("key0_data1", &format_args!("{}", self.key0_data1().bits()))
+            .field("key0_data1", &self.key0_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA1_SPEC {
diff --git a/esp32c6/src/efuse/rd_key0_data2.rs b/esp32c6/src/efuse/rd_key0_data2.rs
index be8f375983..4a38cbfd42 100644
--- a/esp32c6/src/efuse/rd_key0_data2.rs
+++ b/esp32c6/src/efuse/rd_key0_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA2")
-            .field("key0_data2", &format_args!("{}", self.key0_data2().bits()))
+            .field("key0_data2", &self.key0_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA2_SPEC {
diff --git a/esp32c6/src/efuse/rd_key0_data3.rs b/esp32c6/src/efuse/rd_key0_data3.rs
index 6d2222cda9..736e197bb4 100644
--- a/esp32c6/src/efuse/rd_key0_data3.rs
+++ b/esp32c6/src/efuse/rd_key0_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA3")
-            .field("key0_data3", &format_args!("{}", self.key0_data3().bits()))
+            .field("key0_data3", &self.key0_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA3_SPEC {
diff --git a/esp32c6/src/efuse/rd_key0_data4.rs b/esp32c6/src/efuse/rd_key0_data4.rs
index 5c5d3846a2..f57c6246c0 100644
--- a/esp32c6/src/efuse/rd_key0_data4.rs
+++ b/esp32c6/src/efuse/rd_key0_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA4")
-            .field("key0_data4", &format_args!("{}", self.key0_data4().bits()))
+            .field("key0_data4", &self.key0_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA4_SPEC {
diff --git a/esp32c6/src/efuse/rd_key0_data5.rs b/esp32c6/src/efuse/rd_key0_data5.rs
index e675b726d9..fc6203feb8 100644
--- a/esp32c6/src/efuse/rd_key0_data5.rs
+++ b/esp32c6/src/efuse/rd_key0_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA5")
-            .field("key0_data5", &format_args!("{}", self.key0_data5().bits()))
+            .field("key0_data5", &self.key0_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA5_SPEC {
diff --git a/esp32c6/src/efuse/rd_key0_data6.rs b/esp32c6/src/efuse/rd_key0_data6.rs
index 506e4a1a76..021d664b62 100644
--- a/esp32c6/src/efuse/rd_key0_data6.rs
+++ b/esp32c6/src/efuse/rd_key0_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA6")
-            .field("key0_data6", &format_args!("{}", self.key0_data6().bits()))
+            .field("key0_data6", &self.key0_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA6_SPEC {
diff --git a/esp32c6/src/efuse/rd_key0_data7.rs b/esp32c6/src/efuse/rd_key0_data7.rs
index 97d737135d..a6442fdf78 100644
--- a/esp32c6/src/efuse/rd_key0_data7.rs
+++ b/esp32c6/src/efuse/rd_key0_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA7")
-            .field("key0_data7", &format_args!("{}", self.key0_data7().bits()))
+            .field("key0_data7", &self.key0_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA7_SPEC {
diff --git a/esp32c6/src/efuse/rd_key1_data0.rs b/esp32c6/src/efuse/rd_key1_data0.rs
index c70f6acd7f..6b2431620c 100644
--- a/esp32c6/src/efuse/rd_key1_data0.rs
+++ b/esp32c6/src/efuse/rd_key1_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA0")
-            .field("key1_data0", &format_args!("{}", self.key1_data0().bits()))
+            .field("key1_data0", &self.key1_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA0_SPEC {
diff --git a/esp32c6/src/efuse/rd_key1_data1.rs b/esp32c6/src/efuse/rd_key1_data1.rs
index aae8bcee9a..f231c8b98a 100644
--- a/esp32c6/src/efuse/rd_key1_data1.rs
+++ b/esp32c6/src/efuse/rd_key1_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA1")
-            .field("key1_data1", &format_args!("{}", self.key1_data1().bits()))
+            .field("key1_data1", &self.key1_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA1_SPEC {
diff --git a/esp32c6/src/efuse/rd_key1_data2.rs b/esp32c6/src/efuse/rd_key1_data2.rs
index 1966a996a6..4ededdea0a 100644
--- a/esp32c6/src/efuse/rd_key1_data2.rs
+++ b/esp32c6/src/efuse/rd_key1_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA2")
-            .field("key1_data2", &format_args!("{}", self.key1_data2().bits()))
+            .field("key1_data2", &self.key1_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA2_SPEC {
diff --git a/esp32c6/src/efuse/rd_key1_data3.rs b/esp32c6/src/efuse/rd_key1_data3.rs
index fdd40460e9..d20732a98a 100644
--- a/esp32c6/src/efuse/rd_key1_data3.rs
+++ b/esp32c6/src/efuse/rd_key1_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA3")
-            .field("key1_data3", &format_args!("{}", self.key1_data3().bits()))
+            .field("key1_data3", &self.key1_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA3_SPEC {
diff --git a/esp32c6/src/efuse/rd_key1_data4.rs b/esp32c6/src/efuse/rd_key1_data4.rs
index c786647016..d9e7d57ad6 100644
--- a/esp32c6/src/efuse/rd_key1_data4.rs
+++ b/esp32c6/src/efuse/rd_key1_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA4")
-            .field("key1_data4", &format_args!("{}", self.key1_data4().bits()))
+            .field("key1_data4", &self.key1_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA4_SPEC {
diff --git a/esp32c6/src/efuse/rd_key1_data5.rs b/esp32c6/src/efuse/rd_key1_data5.rs
index 0ea5b95d9f..9def03fecb 100644
--- a/esp32c6/src/efuse/rd_key1_data5.rs
+++ b/esp32c6/src/efuse/rd_key1_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA5")
-            .field("key1_data5", &format_args!("{}", self.key1_data5().bits()))
+            .field("key1_data5", &self.key1_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA5_SPEC {
diff --git a/esp32c6/src/efuse/rd_key1_data6.rs b/esp32c6/src/efuse/rd_key1_data6.rs
index ba8b96a6b3..9d5a3e944d 100644
--- a/esp32c6/src/efuse/rd_key1_data6.rs
+++ b/esp32c6/src/efuse/rd_key1_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA6")
-            .field("key1_data6", &format_args!("{}", self.key1_data6().bits()))
+            .field("key1_data6", &self.key1_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA6_SPEC {
diff --git a/esp32c6/src/efuse/rd_key1_data7.rs b/esp32c6/src/efuse/rd_key1_data7.rs
index ba5ea5e180..4d8d190773 100644
--- a/esp32c6/src/efuse/rd_key1_data7.rs
+++ b/esp32c6/src/efuse/rd_key1_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA7")
-            .field("key1_data7", &format_args!("{}", self.key1_data7().bits()))
+            .field("key1_data7", &self.key1_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA7_SPEC {
diff --git a/esp32c6/src/efuse/rd_key2_data0.rs b/esp32c6/src/efuse/rd_key2_data0.rs
index d090b56943..670f7a9712 100644
--- a/esp32c6/src/efuse/rd_key2_data0.rs
+++ b/esp32c6/src/efuse/rd_key2_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA0")
-            .field("key2_data0", &format_args!("{}", self.key2_data0().bits()))
+            .field("key2_data0", &self.key2_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA0_SPEC {
diff --git a/esp32c6/src/efuse/rd_key2_data1.rs b/esp32c6/src/efuse/rd_key2_data1.rs
index c8d52513bc..653b2d5860 100644
--- a/esp32c6/src/efuse/rd_key2_data1.rs
+++ b/esp32c6/src/efuse/rd_key2_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA1")
-            .field("key2_data1", &format_args!("{}", self.key2_data1().bits()))
+            .field("key2_data1", &self.key2_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA1_SPEC {
diff --git a/esp32c6/src/efuse/rd_key2_data2.rs b/esp32c6/src/efuse/rd_key2_data2.rs
index 594db86d03..ac2ec13773 100644
--- a/esp32c6/src/efuse/rd_key2_data2.rs
+++ b/esp32c6/src/efuse/rd_key2_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA2")
-            .field("key2_data2", &format_args!("{}", self.key2_data2().bits()))
+            .field("key2_data2", &self.key2_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA2_SPEC {
diff --git a/esp32c6/src/efuse/rd_key2_data3.rs b/esp32c6/src/efuse/rd_key2_data3.rs
index 11ef6ae075..347ff260f3 100644
--- a/esp32c6/src/efuse/rd_key2_data3.rs
+++ b/esp32c6/src/efuse/rd_key2_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA3")
-            .field("key2_data3", &format_args!("{}", self.key2_data3().bits()))
+            .field("key2_data3", &self.key2_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA3_SPEC {
diff --git a/esp32c6/src/efuse/rd_key2_data4.rs b/esp32c6/src/efuse/rd_key2_data4.rs
index 4bdb2eb156..cde8d0559c 100644
--- a/esp32c6/src/efuse/rd_key2_data4.rs
+++ b/esp32c6/src/efuse/rd_key2_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA4")
-            .field("key2_data4", &format_args!("{}", self.key2_data4().bits()))
+            .field("key2_data4", &self.key2_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA4_SPEC {
diff --git a/esp32c6/src/efuse/rd_key2_data5.rs b/esp32c6/src/efuse/rd_key2_data5.rs
index d4c08fe8bb..071d63afed 100644
--- a/esp32c6/src/efuse/rd_key2_data5.rs
+++ b/esp32c6/src/efuse/rd_key2_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA5")
-            .field("key2_data5", &format_args!("{}", self.key2_data5().bits()))
+            .field("key2_data5", &self.key2_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA5_SPEC {
diff --git a/esp32c6/src/efuse/rd_key2_data6.rs b/esp32c6/src/efuse/rd_key2_data6.rs
index 5034d53b5d..a7b4b5e111 100644
--- a/esp32c6/src/efuse/rd_key2_data6.rs
+++ b/esp32c6/src/efuse/rd_key2_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA6")
-            .field("key2_data6", &format_args!("{}", self.key2_data6().bits()))
+            .field("key2_data6", &self.key2_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA6_SPEC {
diff --git a/esp32c6/src/efuse/rd_key2_data7.rs b/esp32c6/src/efuse/rd_key2_data7.rs
index 0ce4cdab66..26b73dab0a 100644
--- a/esp32c6/src/efuse/rd_key2_data7.rs
+++ b/esp32c6/src/efuse/rd_key2_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA7")
-            .field("key2_data7", &format_args!("{}", self.key2_data7().bits()))
+            .field("key2_data7", &self.key2_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA7_SPEC {
diff --git a/esp32c6/src/efuse/rd_key3_data0.rs b/esp32c6/src/efuse/rd_key3_data0.rs
index c7874ba60f..324ab8ee6c 100644
--- a/esp32c6/src/efuse/rd_key3_data0.rs
+++ b/esp32c6/src/efuse/rd_key3_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA0")
-            .field("key3_data0", &format_args!("{}", self.key3_data0().bits()))
+            .field("key3_data0", &self.key3_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA0_SPEC {
diff --git a/esp32c6/src/efuse/rd_key3_data1.rs b/esp32c6/src/efuse/rd_key3_data1.rs
index 2dcf03994c..036e846966 100644
--- a/esp32c6/src/efuse/rd_key3_data1.rs
+++ b/esp32c6/src/efuse/rd_key3_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA1")
-            .field("key3_data1", &format_args!("{}", self.key3_data1().bits()))
+            .field("key3_data1", &self.key3_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA1_SPEC {
diff --git a/esp32c6/src/efuse/rd_key3_data2.rs b/esp32c6/src/efuse/rd_key3_data2.rs
index 71a11073a1..a01ccae711 100644
--- a/esp32c6/src/efuse/rd_key3_data2.rs
+++ b/esp32c6/src/efuse/rd_key3_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA2")
-            .field("key3_data2", &format_args!("{}", self.key3_data2().bits()))
+            .field("key3_data2", &self.key3_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA2_SPEC {
diff --git a/esp32c6/src/efuse/rd_key3_data3.rs b/esp32c6/src/efuse/rd_key3_data3.rs
index 521e42b9ac..ccf4f14cc0 100644
--- a/esp32c6/src/efuse/rd_key3_data3.rs
+++ b/esp32c6/src/efuse/rd_key3_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA3")
-            .field("key3_data3", &format_args!("{}", self.key3_data3().bits()))
+            .field("key3_data3", &self.key3_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA3_SPEC {
diff --git a/esp32c6/src/efuse/rd_key3_data4.rs b/esp32c6/src/efuse/rd_key3_data4.rs
index b6cad4ee2d..800a8f1dba 100644
--- a/esp32c6/src/efuse/rd_key3_data4.rs
+++ b/esp32c6/src/efuse/rd_key3_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA4")
-            .field("key3_data4", &format_args!("{}", self.key3_data4().bits()))
+            .field("key3_data4", &self.key3_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA4_SPEC {
diff --git a/esp32c6/src/efuse/rd_key3_data5.rs b/esp32c6/src/efuse/rd_key3_data5.rs
index ba0c41d811..90fc05e6b9 100644
--- a/esp32c6/src/efuse/rd_key3_data5.rs
+++ b/esp32c6/src/efuse/rd_key3_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA5")
-            .field("key3_data5", &format_args!("{}", self.key3_data5().bits()))
+            .field("key3_data5", &self.key3_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA5_SPEC {
diff --git a/esp32c6/src/efuse/rd_key3_data6.rs b/esp32c6/src/efuse/rd_key3_data6.rs
index 3d3c27b27e..97260fcf21 100644
--- a/esp32c6/src/efuse/rd_key3_data6.rs
+++ b/esp32c6/src/efuse/rd_key3_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA6")
-            .field("key3_data6", &format_args!("{}", self.key3_data6().bits()))
+            .field("key3_data6", &self.key3_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA6_SPEC {
diff --git a/esp32c6/src/efuse/rd_key3_data7.rs b/esp32c6/src/efuse/rd_key3_data7.rs
index 13a0d80f7c..78b1712e01 100644
--- a/esp32c6/src/efuse/rd_key3_data7.rs
+++ b/esp32c6/src/efuse/rd_key3_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA7")
-            .field("key3_data7", &format_args!("{}", self.key3_data7().bits()))
+            .field("key3_data7", &self.key3_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA7_SPEC {
diff --git a/esp32c6/src/efuse/rd_key4_data0.rs b/esp32c6/src/efuse/rd_key4_data0.rs
index c7da39c966..49583f118a 100644
--- a/esp32c6/src/efuse/rd_key4_data0.rs
+++ b/esp32c6/src/efuse/rd_key4_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA0")
-            .field("key4_data0", &format_args!("{}", self.key4_data0().bits()))
+            .field("key4_data0", &self.key4_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA0_SPEC {
diff --git a/esp32c6/src/efuse/rd_key4_data1.rs b/esp32c6/src/efuse/rd_key4_data1.rs
index 4e619445d1..2255f15151 100644
--- a/esp32c6/src/efuse/rd_key4_data1.rs
+++ b/esp32c6/src/efuse/rd_key4_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA1")
-            .field("key4_data1", &format_args!("{}", self.key4_data1().bits()))
+            .field("key4_data1", &self.key4_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA1_SPEC {
diff --git a/esp32c6/src/efuse/rd_key4_data2.rs b/esp32c6/src/efuse/rd_key4_data2.rs
index d6bc03916d..cc38532702 100644
--- a/esp32c6/src/efuse/rd_key4_data2.rs
+++ b/esp32c6/src/efuse/rd_key4_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA2")
-            .field("key4_data2", &format_args!("{}", self.key4_data2().bits()))
+            .field("key4_data2", &self.key4_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA2_SPEC {
diff --git a/esp32c6/src/efuse/rd_key4_data3.rs b/esp32c6/src/efuse/rd_key4_data3.rs
index 164f9df5af..2a4cf9b5a6 100644
--- a/esp32c6/src/efuse/rd_key4_data3.rs
+++ b/esp32c6/src/efuse/rd_key4_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA3")
-            .field("key4_data3", &format_args!("{}", self.key4_data3().bits()))
+            .field("key4_data3", &self.key4_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA3_SPEC {
diff --git a/esp32c6/src/efuse/rd_key4_data4.rs b/esp32c6/src/efuse/rd_key4_data4.rs
index e647ac36c7..6a877dc0b6 100644
--- a/esp32c6/src/efuse/rd_key4_data4.rs
+++ b/esp32c6/src/efuse/rd_key4_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA4")
-            .field("key4_data4", &format_args!("{}", self.key4_data4().bits()))
+            .field("key4_data4", &self.key4_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA4_SPEC {
diff --git a/esp32c6/src/efuse/rd_key4_data5.rs b/esp32c6/src/efuse/rd_key4_data5.rs
index ede1293132..20291e45a5 100644
--- a/esp32c6/src/efuse/rd_key4_data5.rs
+++ b/esp32c6/src/efuse/rd_key4_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA5")
-            .field("key4_data5", &format_args!("{}", self.key4_data5().bits()))
+            .field("key4_data5", &self.key4_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA5_SPEC {
diff --git a/esp32c6/src/efuse/rd_key4_data6.rs b/esp32c6/src/efuse/rd_key4_data6.rs
index 2d81ffd6ec..acfc601dab 100644
--- a/esp32c6/src/efuse/rd_key4_data6.rs
+++ b/esp32c6/src/efuse/rd_key4_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA6")
-            .field("key4_data6", &format_args!("{}", self.key4_data6().bits()))
+            .field("key4_data6", &self.key4_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA6_SPEC {
diff --git a/esp32c6/src/efuse/rd_key4_data7.rs b/esp32c6/src/efuse/rd_key4_data7.rs
index 258ed36331..9491ecfa8b 100644
--- a/esp32c6/src/efuse/rd_key4_data7.rs
+++ b/esp32c6/src/efuse/rd_key4_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA7")
-            .field("key4_data7", &format_args!("{}", self.key4_data7().bits()))
+            .field("key4_data7", &self.key4_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA7_SPEC {
diff --git a/esp32c6/src/efuse/rd_key5_data0.rs b/esp32c6/src/efuse/rd_key5_data0.rs
index 30afd98f27..eaa12eb5b5 100644
--- a/esp32c6/src/efuse/rd_key5_data0.rs
+++ b/esp32c6/src/efuse/rd_key5_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA0")
-            .field("key5_data0", &format_args!("{}", self.key5_data0().bits()))
+            .field("key5_data0", &self.key5_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA0_SPEC {
diff --git a/esp32c6/src/efuse/rd_key5_data1.rs b/esp32c6/src/efuse/rd_key5_data1.rs
index e9dce7e94e..ea2b0c5c93 100644
--- a/esp32c6/src/efuse/rd_key5_data1.rs
+++ b/esp32c6/src/efuse/rd_key5_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA1")
-            .field("key5_data1", &format_args!("{}", self.key5_data1().bits()))
+            .field("key5_data1", &self.key5_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA1_SPEC {
diff --git a/esp32c6/src/efuse/rd_key5_data2.rs b/esp32c6/src/efuse/rd_key5_data2.rs
index c689437cdc..f2ea02e234 100644
--- a/esp32c6/src/efuse/rd_key5_data2.rs
+++ b/esp32c6/src/efuse/rd_key5_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA2")
-            .field("key5_data2", &format_args!("{}", self.key5_data2().bits()))
+            .field("key5_data2", &self.key5_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA2_SPEC {
diff --git a/esp32c6/src/efuse/rd_key5_data3.rs b/esp32c6/src/efuse/rd_key5_data3.rs
index bca91c9d37..68a0f3034f 100644
--- a/esp32c6/src/efuse/rd_key5_data3.rs
+++ b/esp32c6/src/efuse/rd_key5_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA3")
-            .field("key5_data3", &format_args!("{}", self.key5_data3().bits()))
+            .field("key5_data3", &self.key5_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA3_SPEC {
diff --git a/esp32c6/src/efuse/rd_key5_data4.rs b/esp32c6/src/efuse/rd_key5_data4.rs
index f3ad10e5b8..9658e4f4b8 100644
--- a/esp32c6/src/efuse/rd_key5_data4.rs
+++ b/esp32c6/src/efuse/rd_key5_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA4")
-            .field("key5_data4", &format_args!("{}", self.key5_data4().bits()))
+            .field("key5_data4", &self.key5_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA4_SPEC {
diff --git a/esp32c6/src/efuse/rd_key5_data5.rs b/esp32c6/src/efuse/rd_key5_data5.rs
index 6d7123a48c..29d27d1c31 100644
--- a/esp32c6/src/efuse/rd_key5_data5.rs
+++ b/esp32c6/src/efuse/rd_key5_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA5")
-            .field("key5_data5", &format_args!("{}", self.key5_data5().bits()))
+            .field("key5_data5", &self.key5_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA5_SPEC {
diff --git a/esp32c6/src/efuse/rd_key5_data6.rs b/esp32c6/src/efuse/rd_key5_data6.rs
index d24ecae9af..cf5b5a4e0a 100644
--- a/esp32c6/src/efuse/rd_key5_data6.rs
+++ b/esp32c6/src/efuse/rd_key5_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA6")
-            .field("key5_data6", &format_args!("{}", self.key5_data6().bits()))
+            .field("key5_data6", &self.key5_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA6_SPEC {
diff --git a/esp32c6/src/efuse/rd_key5_data7.rs b/esp32c6/src/efuse/rd_key5_data7.rs
index 493d96b395..d22882be6d 100644
--- a/esp32c6/src/efuse/rd_key5_data7.rs
+++ b/esp32c6/src/efuse/rd_key5_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA7")
-            .field("key5_data7", &format_args!("{}", self.key5_data7().bits()))
+            .field("key5_data7", &self.key5_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA7_SPEC {
diff --git a/esp32c6/src/efuse/rd_mac_spi_sys_0.rs b/esp32c6/src/efuse/rd_mac_spi_sys_0.rs
index b24e9e94df..ae5be0b4cd 100644
--- a/esp32c6/src/efuse/rd_mac_spi_sys_0.rs
+++ b/esp32c6/src/efuse/rd_mac_spi_sys_0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_0")
-            .field("mac_0", &format_args!("{}", self.mac_0().bits()))
+            .field("mac_0", &self.mac_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_0_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_0_SPEC {
diff --git a/esp32c6/src/efuse/rd_mac_spi_sys_1.rs b/esp32c6/src/efuse/rd_mac_spi_sys_1.rs
index 8ef0fa873d..06b4f0851d 100644
--- a/esp32c6/src/efuse/rd_mac_spi_sys_1.rs
+++ b/esp32c6/src/efuse/rd_mac_spi_sys_1.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_1")
-            .field("mac_1", &format_args!("{}", self.mac_1().bits()))
-            .field("mac_ext", &format_args!("{}", self.mac_ext().bits()))
+            .field("mac_1", &self.mac_1())
+            .field("mac_ext", &self.mac_ext())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_1_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_1_SPEC {
diff --git a/esp32c6/src/efuse/rd_mac_spi_sys_2.rs b/esp32c6/src/efuse/rd_mac_spi_sys_2.rs
index 7cfbd6680c..a62f62d345 100644
--- a/esp32c6/src/efuse/rd_mac_spi_sys_2.rs
+++ b/esp32c6/src/efuse/rd_mac_spi_sys_2.rs
@@ -62,47 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_2")
-            .field(
-                "active_hp_dbias",
-                &format_args!("{}", self.active_hp_dbias().bits()),
-            )
-            .field(
-                "active_lp_dbias",
-                &format_args!("{}", self.active_lp_dbias().bits()),
-            )
-            .field(
-                "lslp_hp_dbg",
-                &format_args!("{}", self.lslp_hp_dbg().bits()),
-            )
-            .field(
-                "lslp_hp_dbias",
-                &format_args!("{}", self.lslp_hp_dbias().bits()),
-            )
-            .field(
-                "dslp_lp_dbg",
-                &format_args!("{}", self.dslp_lp_dbg().bits()),
-            )
-            .field(
-                "dslp_lp_dbias",
-                &format_args!("{}", self.dslp_lp_dbias().bits()),
-            )
-            .field(
-                "dbias_vol_gap",
-                &format_args!("{}", self.dbias_vol_gap().bits()),
-            )
-            .field(
-                "spi_pad_conf_1",
-                &format_args!("{}", self.spi_pad_conf_1().bits()),
-            )
+            .field("active_hp_dbias", &self.active_hp_dbias())
+            .field("active_lp_dbias", &self.active_lp_dbias())
+            .field("lslp_hp_dbg", &self.lslp_hp_dbg())
+            .field("lslp_hp_dbias", &self.lslp_hp_dbias())
+            .field("dslp_lp_dbg", &self.dslp_lp_dbg())
+            .field("dslp_lp_dbias", &self.dslp_lp_dbias())
+            .field("dbias_vol_gap", &self.dbias_vol_gap())
+            .field("spi_pad_conf_1", &self.spi_pad_conf_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_2_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_2_SPEC {
diff --git a/esp32c6/src/efuse/rd_mac_spi_sys_3.rs b/esp32c6/src/efuse/rd_mac_spi_sys_3.rs
index 1839e33f54..8b4fbee2c0 100644
--- a/esp32c6/src/efuse/rd_mac_spi_sys_3.rs
+++ b/esp32c6/src/efuse/rd_mac_spi_sys_3.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_3")
-            .field(
-                "spi_pad_conf_2",
-                &format_args!("{}", self.spi_pad_conf_2().bits()),
-            )
-            .field(
-                "sys_data_part0_0",
-                &format_args!("{}", self.sys_data_part0_0().bits()),
-            )
+            .field("spi_pad_conf_2", &self.spi_pad_conf_2())
+            .field("sys_data_part0_0", &self.sys_data_part0_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_3_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_3_SPEC {
diff --git a/esp32c6/src/efuse/rd_mac_spi_sys_4.rs b/esp32c6/src/efuse/rd_mac_spi_sys_4.rs
index e1f92c65b0..6cc116afdf 100644
--- a/esp32c6/src/efuse/rd_mac_spi_sys_4.rs
+++ b/esp32c6/src/efuse/rd_mac_spi_sys_4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_4")
-            .field(
-                "sys_data_part0_1",
-                &format_args!("{}", self.sys_data_part0_1().bits()),
-            )
+            .field("sys_data_part0_1", &self.sys_data_part0_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_4_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_4_SPEC {
diff --git a/esp32c6/src/efuse/rd_mac_spi_sys_5.rs b/esp32c6/src/efuse/rd_mac_spi_sys_5.rs
index ca976109c7..ccd48e5c7f 100644
--- a/esp32c6/src/efuse/rd_mac_spi_sys_5.rs
+++ b/esp32c6/src/efuse/rd_mac_spi_sys_5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_5")
-            .field(
-                "sys_data_part0_2",
-                &format_args!("{}", self.sys_data_part0_2().bits()),
-            )
+            .field("sys_data_part0_2", &self.sys_data_part0_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_5_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_5_SPEC {
diff --git a/esp32c6/src/efuse/rd_repeat_data0.rs b/esp32c6/src/efuse/rd_repeat_data0.rs
index d24550bd43..907a8fbbf2 100644
--- a/esp32c6/src/efuse/rd_repeat_data0.rs
+++ b/esp32c6/src/efuse/rd_repeat_data0.rs
@@ -146,80 +146,32 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA0")
-            .field("rd_dis", &format_args!("{}", self.rd_dis().bits()))
-            .field(
-                "swap_uart_sdio_en",
-                &format_args!("{}", self.swap_uart_sdio_en().bit()),
-            )
-            .field("dis_icache", &format_args!("{}", self.dis_icache().bit()))
-            .field(
-                "dis_usb_jtag",
-                &format_args!("{}", self.dis_usb_jtag().bit()),
-            )
-            .field(
-                "dis_download_icache",
-                &format_args!("{}", self.dis_download_icache().bit()),
-            )
-            .field(
-                "dis_usb_serial_jtag",
-                &format_args!("{}", self.dis_usb_serial_jtag().bit()),
-            )
-            .field(
-                "dis_force_download",
-                &format_args!("{}", self.dis_force_download().bit()),
-            )
-            .field(
-                "spi_download_mspi_dis",
-                &format_args!("{}", self.spi_download_mspi_dis().bit()),
-            )
-            .field("dis_can", &format_args!("{}", self.dis_can().bit()))
-            .field(
-                "jtag_sel_enable",
-                &format_args!("{}", self.jtag_sel_enable().bit()),
-            )
-            .field(
-                "soft_dis_jtag",
-                &format_args!("{}", self.soft_dis_jtag().bits()),
-            )
-            .field(
-                "dis_pad_jtag",
-                &format_args!("{}", self.dis_pad_jtag().bit()),
-            )
+            .field("rd_dis", &self.rd_dis())
+            .field("swap_uart_sdio_en", &self.swap_uart_sdio_en())
+            .field("dis_icache", &self.dis_icache())
+            .field("dis_usb_jtag", &self.dis_usb_jtag())
+            .field("dis_download_icache", &self.dis_download_icache())
+            .field("dis_usb_serial_jtag", &self.dis_usb_serial_jtag())
+            .field("dis_force_download", &self.dis_force_download())
+            .field("spi_download_mspi_dis", &self.spi_download_mspi_dis())
+            .field("dis_can", &self.dis_can())
+            .field("jtag_sel_enable", &self.jtag_sel_enable())
+            .field("soft_dis_jtag", &self.soft_dis_jtag())
+            .field("dis_pad_jtag", &self.dis_pad_jtag())
             .field(
                 "dis_download_manual_encrypt",
-                &format_args!("{}", self.dis_download_manual_encrypt().bit()),
-            )
-            .field("usb_drefh", &format_args!("{}", self.usb_drefh().bits()))
-            .field("usb_drefl", &format_args!("{}", self.usb_drefl().bits()))
-            .field(
-                "usb_exchg_pins",
-                &format_args!("{}", self.usb_exchg_pins().bit()),
-            )
-            .field(
-                "vdd_spi_as_gpio",
-                &format_args!("{}", self.vdd_spi_as_gpio().bit()),
-            )
-            .field(
-                "rpt4_reserved0_2",
-                &format_args!("{}", self.rpt4_reserved0_2().bits()),
-            )
-            .field(
-                "rpt4_reserved0_1",
-                &format_args!("{}", self.rpt4_reserved0_1().bit()),
-            )
-            .field(
-                "rpt4_reserved0_0",
-                &format_args!("{}", self.rpt4_reserved0_0().bits()),
+                &self.dis_download_manual_encrypt(),
             )
+            .field("usb_drefh", &self.usb_drefh())
+            .field("usb_drefl", &self.usb_drefl())
+            .field("usb_exchg_pins", &self.usb_exchg_pins())
+            .field("vdd_spi_as_gpio", &self.vdd_spi_as_gpio())
+            .field("rpt4_reserved0_2", &self.rpt4_reserved0_2())
+            .field("rpt4_reserved0_1", &self.rpt4_reserved0_1())
+            .field("rpt4_reserved0_0", &self.rpt4_reserved0_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA0_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA0_SPEC {
diff --git a/esp32c6/src/efuse/rd_repeat_data1.rs b/esp32c6/src/efuse/rd_repeat_data1.rs
index d42441bb48..180e073fc0 100644
--- a/esp32c6/src/efuse/rd_repeat_data1.rs
+++ b/esp32c6/src/efuse/rd_repeat_data1.rs
@@ -62,47 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA1")
-            .field(
-                "rpt4_reserved1_0",
-                &format_args!("{}", self.rpt4_reserved1_0().bits()),
-            )
-            .field(
-                "wdt_delay_sel",
-                &format_args!("{}", self.wdt_delay_sel().bits()),
-            )
-            .field(
-                "spi_boot_crypt_cnt",
-                &format_args!("{}", self.spi_boot_crypt_cnt().bits()),
-            )
-            .field(
-                "secure_boot_key_revoke0",
-                &format_args!("{}", self.secure_boot_key_revoke0().bit()),
-            )
-            .field(
-                "secure_boot_key_revoke1",
-                &format_args!("{}", self.secure_boot_key_revoke1().bit()),
-            )
-            .field(
-                "secure_boot_key_revoke2",
-                &format_args!("{}", self.secure_boot_key_revoke2().bit()),
-            )
-            .field(
-                "key_purpose_0",
-                &format_args!("{}", self.key_purpose_0().bits()),
-            )
-            .field(
-                "key_purpose_1",
-                &format_args!("{}", self.key_purpose_1().bits()),
-            )
+            .field("rpt4_reserved1_0", &self.rpt4_reserved1_0())
+            .field("wdt_delay_sel", &self.wdt_delay_sel())
+            .field("spi_boot_crypt_cnt", &self.spi_boot_crypt_cnt())
+            .field("secure_boot_key_revoke0", &self.secure_boot_key_revoke0())
+            .field("secure_boot_key_revoke1", &self.secure_boot_key_revoke1())
+            .field("secure_boot_key_revoke2", &self.secure_boot_key_revoke2())
+            .field("key_purpose_0", &self.key_purpose_0())
+            .field("key_purpose_1", &self.key_purpose_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA1_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA1_SPEC {
diff --git a/esp32c6/src/efuse/rd_repeat_data2.rs b/esp32c6/src/efuse/rd_repeat_data2.rs
index 66e8d56de8..1356d420c4 100644
--- a/esp32c6/src/efuse/rd_repeat_data2.rs
+++ b/esp32c6/src/efuse/rd_repeat_data2.rs
@@ -83,56 +83,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA2")
-            .field(
-                "key_purpose_2",
-                &format_args!("{}", self.key_purpose_2().bits()),
-            )
-            .field(
-                "key_purpose_3",
-                &format_args!("{}", self.key_purpose_3().bits()),
-            )
-            .field(
-                "key_purpose_4",
-                &format_args!("{}", self.key_purpose_4().bits()),
-            )
-            .field(
-                "key_purpose_5",
-                &format_args!("{}", self.key_purpose_5().bits()),
-            )
-            .field(
-                "dpa_sec_level",
-                &format_args!("{}", self.dpa_sec_level().bits()),
-            )
-            .field(
-                "rpt4_reserved2_1",
-                &format_args!("{}", self.rpt4_reserved2_1().bit()),
-            )
-            .field(
-                "crypt_dpa_enable",
-                &format_args!("{}", self.crypt_dpa_enable().bit()),
-            )
-            .field(
-                "secure_boot_en",
-                &format_args!("{}", self.secure_boot_en().bit()),
-            )
+            .field("key_purpose_2", &self.key_purpose_2())
+            .field("key_purpose_3", &self.key_purpose_3())
+            .field("key_purpose_4", &self.key_purpose_4())
+            .field("key_purpose_5", &self.key_purpose_5())
+            .field("dpa_sec_level", &self.dpa_sec_level())
+            .field("rpt4_reserved2_1", &self.rpt4_reserved2_1())
+            .field("crypt_dpa_enable", &self.crypt_dpa_enable())
+            .field("secure_boot_en", &self.secure_boot_en())
             .field(
                 "secure_boot_aggressive_revoke",
-                &format_args!("{}", self.secure_boot_aggressive_revoke().bit()),
+                &self.secure_boot_aggressive_revoke(),
             )
-            .field(
-                "rpt4_reserved2_0",
-                &format_args!("{}", self.rpt4_reserved2_0().bits()),
-            )
-            .field("flash_tpuw", &format_args!("{}", self.flash_tpuw().bits()))
+            .field("rpt4_reserved2_0", &self.rpt4_reserved2_0())
+            .field("flash_tpuw", &self.flash_tpuw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA2_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA2_SPEC {
diff --git a/esp32c6/src/efuse/rd_repeat_data3.rs b/esp32c6/src/efuse/rd_repeat_data3.rs
index 0e6394fa1d..ee01d74dd4 100644
--- a/esp32c6/src/efuse/rd_repeat_data3.rs
+++ b/esp32c6/src/efuse/rd_repeat_data3.rs
@@ -111,75 +111,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA3")
-            .field(
-                "dis_download_mode",
-                &format_args!("{}", self.dis_download_mode().bit()),
-            )
-            .field(
-                "dis_direct_boot",
-                &format_args!("{}", self.dis_direct_boot().bit()),
-            )
-            .field(
-                "dis_usb_print",
-                &format_args!("{}", self.dis_usb_print().bit()),
-            )
-            .field(
-                "rpt4_reserved3_5",
-                &format_args!("{}", self.rpt4_reserved3_5().bit()),
-            )
+            .field("dis_download_mode", &self.dis_download_mode())
+            .field("dis_direct_boot", &self.dis_direct_boot())
+            .field("dis_usb_print", &self.dis_usb_print())
+            .field("rpt4_reserved3_5", &self.rpt4_reserved3_5())
             .field(
                 "dis_usb_serial_jtag_download_mode",
-                &format_args!("{}", self.dis_usb_serial_jtag_download_mode().bit()),
-            )
-            .field(
-                "enable_security_download",
-                &format_args!("{}", self.enable_security_download().bit()),
-            )
-            .field(
-                "uart_print_control",
-                &format_args!("{}", self.uart_print_control().bits()),
-            )
-            .field(
-                "rpt4_reserved3_4",
-                &format_args!("{}", self.rpt4_reserved3_4().bit()),
-            )
-            .field(
-                "rpt4_reserved3_3",
-                &format_args!("{}", self.rpt4_reserved3_3().bit()),
-            )
-            .field(
-                "rpt4_reserved3_2",
-                &format_args!("{}", self.rpt4_reserved3_2().bits()),
-            )
-            .field(
-                "rpt4_reserved3_1",
-                &format_args!("{}", self.rpt4_reserved3_1().bit()),
-            )
-            .field(
-                "force_send_resume",
-                &format_args!("{}", self.force_send_resume().bit()),
-            )
-            .field(
-                "secure_version",
-                &format_args!("{}", self.secure_version().bits()),
+                &self.dis_usb_serial_jtag_download_mode(),
             )
+            .field("enable_security_download", &self.enable_security_download())
+            .field("uart_print_control", &self.uart_print_control())
+            .field("rpt4_reserved3_4", &self.rpt4_reserved3_4())
+            .field("rpt4_reserved3_3", &self.rpt4_reserved3_3())
+            .field("rpt4_reserved3_2", &self.rpt4_reserved3_2())
+            .field("rpt4_reserved3_1", &self.rpt4_reserved3_1())
+            .field("force_send_resume", &self.force_send_resume())
+            .field("secure_version", &self.secure_version())
             .field(
                 "secure_boot_disable_fast_wake",
-                &format_args!("{}", self.secure_boot_disable_fast_wake().bit()),
-            )
-            .field(
-                "rpt4_reserved3_0",
-                &format_args!("{}", self.rpt4_reserved3_0().bit()),
+                &self.secure_boot_disable_fast_wake(),
             )
+            .field("rpt4_reserved3_0", &self.rpt4_reserved3_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA3_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA3_SPEC {
diff --git a/esp32c6/src/efuse/rd_repeat_data4.rs b/esp32c6/src/efuse/rd_repeat_data4.rs
index 5cfd6c67aa..1b136e8e6e 100644
--- a/esp32c6/src/efuse/rd_repeat_data4.rs
+++ b/esp32c6/src/efuse/rd_repeat_data4.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA4")
-            .field(
-                "rpt4_reserved4_1",
-                &format_args!("{}", self.rpt4_reserved4_1().bits()),
-            )
-            .field(
-                "rpt4_reserved4_0",
-                &format_args!("{}", self.rpt4_reserved4_0().bits()),
-            )
+            .field("rpt4_reserved4_1", &self.rpt4_reserved4_1())
+            .field("rpt4_reserved4_0", &self.rpt4_reserved4_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA4_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA4_SPEC {
diff --git a/esp32c6/src/efuse/rd_repeat_err0.rs b/esp32c6/src/efuse/rd_repeat_err0.rs
index 9155937801..028e152579 100644
--- a/esp32c6/src/efuse/rd_repeat_err0.rs
+++ b/esp32c6/src/efuse/rd_repeat_err0.rs
@@ -146,92 +146,35 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR0")
-            .field("rd_dis_err", &format_args!("{}", self.rd_dis_err().bits()))
-            .field(
-                "swap_uart_sdio_en_err",
-                &format_args!("{}", self.swap_uart_sdio_en_err().bit()),
-            )
-            .field(
-                "dis_icache_err",
-                &format_args!("{}", self.dis_icache_err().bit()),
-            )
-            .field(
-                "dis_usb_jtag_err",
-                &format_args!("{}", self.dis_usb_jtag_err().bit()),
-            )
-            .field(
-                "dis_download_icache_err",
-                &format_args!("{}", self.dis_download_icache_err().bit()),
-            )
-            .field(
-                "dis_usb_serial_jtag_err",
-                &format_args!("{}", self.dis_usb_serial_jtag_err().bit()),
-            )
-            .field(
-                "dis_force_download_err",
-                &format_args!("{}", self.dis_force_download_err().bit()),
-            )
+            .field("rd_dis_err", &self.rd_dis_err())
+            .field("swap_uart_sdio_en_err", &self.swap_uart_sdio_en_err())
+            .field("dis_icache_err", &self.dis_icache_err())
+            .field("dis_usb_jtag_err", &self.dis_usb_jtag_err())
+            .field("dis_download_icache_err", &self.dis_download_icache_err())
+            .field("dis_usb_serial_jtag_err", &self.dis_usb_serial_jtag_err())
+            .field("dis_force_download_err", &self.dis_force_download_err())
             .field(
                 "spi_download_mspi_dis_err",
-                &format_args!("{}", self.spi_download_mspi_dis_err().bit()),
-            )
-            .field(
-                "dis_twai_err",
-                &format_args!("{}", self.dis_twai_err().bit()),
-            )
-            .field(
-                "jtag_sel_enable_err",
-                &format_args!("{}", self.jtag_sel_enable_err().bit()),
-            )
-            .field(
-                "soft_dis_jtag_err",
-                &format_args!("{}", self.soft_dis_jtag_err().bits()),
-            )
-            .field(
-                "dis_pad_jtag_err",
-                &format_args!("{}", self.dis_pad_jtag_err().bit()),
+                &self.spi_download_mspi_dis_err(),
             )
+            .field("dis_twai_err", &self.dis_twai_err())
+            .field("jtag_sel_enable_err", &self.jtag_sel_enable_err())
+            .field("soft_dis_jtag_err", &self.soft_dis_jtag_err())
+            .field("dis_pad_jtag_err", &self.dis_pad_jtag_err())
             .field(
                 "dis_download_manual_encrypt_err",
-                &format_args!("{}", self.dis_download_manual_encrypt_err().bit()),
-            )
-            .field(
-                "usb_drefh_err",
-                &format_args!("{}", self.usb_drefh_err().bits()),
-            )
-            .field(
-                "usb_drefl_err",
-                &format_args!("{}", self.usb_drefl_err().bits()),
-            )
-            .field(
-                "usb_exchg_pins_err",
-                &format_args!("{}", self.usb_exchg_pins_err().bit()),
-            )
-            .field(
-                "vdd_spi_as_gpio_err",
-                &format_args!("{}", self.vdd_spi_as_gpio_err().bit()),
-            )
-            .field(
-                "rpt4_reserved0_err_2",
-                &format_args!("{}", self.rpt4_reserved0_err_2().bits()),
-            )
-            .field(
-                "rpt4_reserved0_err_1",
-                &format_args!("{}", self.rpt4_reserved0_err_1().bit()),
-            )
-            .field(
-                "rpt4_reserved0_err_0",
-                &format_args!("{}", self.rpt4_reserved0_err_0().bits()),
-            )
+                &self.dis_download_manual_encrypt_err(),
+            )
+            .field("usb_drefh_err", &self.usb_drefh_err())
+            .field("usb_drefl_err", &self.usb_drefl_err())
+            .field("usb_exchg_pins_err", &self.usb_exchg_pins_err())
+            .field("vdd_spi_as_gpio_err", &self.vdd_spi_as_gpio_err())
+            .field("rpt4_reserved0_err_2", &self.rpt4_reserved0_err_2())
+            .field("rpt4_reserved0_err_1", &self.rpt4_reserved0_err_1())
+            .field("rpt4_reserved0_err_0", &self.rpt4_reserved0_err_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 0 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR0_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR0_SPEC {
diff --git a/esp32c6/src/efuse/rd_repeat_err1.rs b/esp32c6/src/efuse/rd_repeat_err1.rs
index 0e0a7958ad..4d7d31b7f1 100644
--- a/esp32c6/src/efuse/rd_repeat_err1.rs
+++ b/esp32c6/src/efuse/rd_repeat_err1.rs
@@ -62,47 +62,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR1")
-            .field(
-                "rpt4_reserved1_err_0",
-                &format_args!("{}", self.rpt4_reserved1_err_0().bits()),
-            )
-            .field(
-                "wdt_delay_sel_err",
-                &format_args!("{}", self.wdt_delay_sel_err().bits()),
-            )
-            .field(
-                "spi_boot_crypt_cnt_err",
-                &format_args!("{}", self.spi_boot_crypt_cnt_err().bits()),
-            )
+            .field("rpt4_reserved1_err_0", &self.rpt4_reserved1_err_0())
+            .field("wdt_delay_sel_err", &self.wdt_delay_sel_err())
+            .field("spi_boot_crypt_cnt_err", &self.spi_boot_crypt_cnt_err())
             .field(
                 "secure_boot_key_revoke0_err",
-                &format_args!("{}", self.secure_boot_key_revoke0_err().bit()),
+                &self.secure_boot_key_revoke0_err(),
             )
             .field(
                 "secure_boot_key_revoke1_err",
-                &format_args!("{}", self.secure_boot_key_revoke1_err().bit()),
+                &self.secure_boot_key_revoke1_err(),
             )
             .field(
                 "secure_boot_key_revoke2_err",
-                &format_args!("{}", self.secure_boot_key_revoke2_err().bit()),
-            )
-            .field(
-                "key_purpose_0_err",
-                &format_args!("{}", self.key_purpose_0_err().bits()),
-            )
-            .field(
-                "key_purpose_1_err",
-                &format_args!("{}", self.key_purpose_1_err().bits()),
+                &self.secure_boot_key_revoke2_err(),
             )
+            .field("key_purpose_0_err", &self.key_purpose_0_err())
+            .field("key_purpose_1_err", &self.key_purpose_1_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 1 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR1_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR1_SPEC {
diff --git a/esp32c6/src/efuse/rd_repeat_err2.rs b/esp32c6/src/efuse/rd_repeat_err2.rs
index a3667f5af9..b16f3e3b56 100644
--- a/esp32c6/src/efuse/rd_repeat_err2.rs
+++ b/esp32c6/src/efuse/rd_repeat_err2.rs
@@ -83,59 +83,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR2")
-            .field(
-                "key_purpose_2_err",
-                &format_args!("{}", self.key_purpose_2_err().bits()),
-            )
-            .field(
-                "key_purpose_3_err",
-                &format_args!("{}", self.key_purpose_3_err().bits()),
-            )
-            .field(
-                "key_purpose_4_err",
-                &format_args!("{}", self.key_purpose_4_err().bits()),
-            )
-            .field(
-                "key_purpose_5_err",
-                &format_args!("{}", self.key_purpose_5_err().bits()),
-            )
-            .field(
-                "sec_dpa_level_err",
-                &format_args!("{}", self.sec_dpa_level_err().bits()),
-            )
-            .field(
-                "rpt4_reserved2_err_1",
-                &format_args!("{}", self.rpt4_reserved2_err_1().bit()),
-            )
-            .field(
-                "crypt_dpa_enable_err",
-                &format_args!("{}", self.crypt_dpa_enable_err().bit()),
-            )
-            .field(
-                "secure_boot_en_err",
-                &format_args!("{}", self.secure_boot_en_err().bit()),
-            )
+            .field("key_purpose_2_err", &self.key_purpose_2_err())
+            .field("key_purpose_3_err", &self.key_purpose_3_err())
+            .field("key_purpose_4_err", &self.key_purpose_4_err())
+            .field("key_purpose_5_err", &self.key_purpose_5_err())
+            .field("sec_dpa_level_err", &self.sec_dpa_level_err())
+            .field("rpt4_reserved2_err_1", &self.rpt4_reserved2_err_1())
+            .field("crypt_dpa_enable_err", &self.crypt_dpa_enable_err())
+            .field("secure_boot_en_err", &self.secure_boot_en_err())
             .field(
                 "secure_boot_aggressive_revoke_err",
-                &format_args!("{}", self.secure_boot_aggressive_revoke_err().bit()),
-            )
-            .field(
-                "rpt4_reserved2_err_0",
-                &format_args!("{}", self.rpt4_reserved2_err_0().bits()),
-            )
-            .field(
-                "flash_tpuw_err",
-                &format_args!("{}", self.flash_tpuw_err().bits()),
+                &self.secure_boot_aggressive_revoke_err(),
             )
+            .field("rpt4_reserved2_err_0", &self.rpt4_reserved2_err_0())
+            .field("flash_tpuw_err", &self.flash_tpuw_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 2 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR2_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR2_SPEC {
diff --git a/esp32c6/src/efuse/rd_repeat_err3.rs b/esp32c6/src/efuse/rd_repeat_err3.rs
index ad0a49badc..f0947c97f8 100644
--- a/esp32c6/src/efuse/rd_repeat_err3.rs
+++ b/esp32c6/src/efuse/rd_repeat_err3.rs
@@ -104,71 +104,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR3")
-            .field(
-                "dis_download_mode_err",
-                &format_args!("{}", self.dis_download_mode_err().bit()),
-            )
-            .field(
-                "dis_direct_boot_err",
-                &format_args!("{}", self.dis_direct_boot_err().bit()),
-            )
-            .field(
-                "usb_print_err",
-                &format_args!("{}", self.usb_print_err().bit()),
-            )
-            .field(
-                "rpt4_reserved3_err_5",
-                &format_args!("{}", self.rpt4_reserved3_err_5().bit()),
-            )
+            .field("dis_download_mode_err", &self.dis_download_mode_err())
+            .field("dis_direct_boot_err", &self.dis_direct_boot_err())
+            .field("usb_print_err", &self.usb_print_err())
+            .field("rpt4_reserved3_err_5", &self.rpt4_reserved3_err_5())
             .field(
                 "dis_usb_serial_jtag_download_mode_err",
-                &format_args!("{}", self.dis_usb_serial_jtag_download_mode_err().bit()),
+                &self.dis_usb_serial_jtag_download_mode_err(),
             )
             .field(
                 "enable_security_download_err",
-                &format_args!("{}", self.enable_security_download_err().bit()),
-            )
-            .field(
-                "uart_print_control_err",
-                &format_args!("{}", self.uart_print_control_err().bits()),
-            )
-            .field(
-                "rpt4_reserved3_err_4",
-                &format_args!("{}", self.rpt4_reserved3_err_4().bit()),
-            )
-            .field(
-                "rpt4_reserved3_err_3",
-                &format_args!("{}", self.rpt4_reserved3_err_3().bit()),
-            )
-            .field(
-                "rpt4_reserved3_err_2",
-                &format_args!("{}", self.rpt4_reserved3_err_2().bits()),
-            )
-            .field(
-                "rpt4_reserved3_err_1",
-                &format_args!("{}", self.rpt4_reserved3_err_1().bit()),
-            )
-            .field(
-                "force_send_resume_err",
-                &format_args!("{}", self.force_send_resume_err().bit()),
-            )
-            .field(
-                "secure_version_err",
-                &format_args!("{}", self.secure_version_err().bits()),
-            )
-            .field(
-                "rpt4_reserved3_err_0",
-                &format_args!("{}", self.rpt4_reserved3_err_0().bits()),
+                &self.enable_security_download_err(),
             )
+            .field("uart_print_control_err", &self.uart_print_control_err())
+            .field("rpt4_reserved3_err_4", &self.rpt4_reserved3_err_4())
+            .field("rpt4_reserved3_err_3", &self.rpt4_reserved3_err_3())
+            .field("rpt4_reserved3_err_2", &self.rpt4_reserved3_err_2())
+            .field("rpt4_reserved3_err_1", &self.rpt4_reserved3_err_1())
+            .field("force_send_resume_err", &self.force_send_resume_err())
+            .field("secure_version_err", &self.secure_version_err())
+            .field("rpt4_reserved3_err_0", &self.rpt4_reserved3_err_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 3 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR3_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR3_SPEC {
diff --git a/esp32c6/src/efuse/rd_repeat_err4.rs b/esp32c6/src/efuse/rd_repeat_err4.rs
index a6fcb1d857..3db7fc1db8 100644
--- a/esp32c6/src/efuse/rd_repeat_err4.rs
+++ b/esp32c6/src/efuse/rd_repeat_err4.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR4")
-            .field(
-                "rpt4_reserved4_err_1",
-                &format_args!("{}", self.rpt4_reserved4_err_1().bits()),
-            )
-            .field(
-                "rpt4_reserved4_err_0",
-                &format_args!("{}", self.rpt4_reserved4_err_0().bits()),
-            )
+            .field("rpt4_reserved4_err_1", &self.rpt4_reserved4_err_1())
+            .field("rpt4_reserved4_err_0", &self.rpt4_reserved4_err_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 4 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR4_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR4_SPEC {
diff --git a/esp32c6/src/efuse/rd_rs_err0.rs b/esp32c6/src/efuse/rd_rs_err0.rs
index ea7bad6e93..ed5dc386c0 100644
--- a/esp32c6/src/efuse/rd_rs_err0.rs
+++ b/esp32c6/src/efuse/rd_rs_err0.rs
@@ -118,64 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_RS_ERR0")
-            .field(
-                "mac_spi_8m_err_num",
-                &format_args!("{}", self.mac_spi_8m_err_num().bits()),
-            )
-            .field(
-                "mac_spi_8m_fail",
-                &format_args!("{}", self.mac_spi_8m_fail().bit()),
-            )
-            .field(
-                "sys_part1_num",
-                &format_args!("{}", self.sys_part1_num().bits()),
-            )
-            .field(
-                "sys_part1_fail",
-                &format_args!("{}", self.sys_part1_fail().bit()),
-            )
-            .field(
-                "usr_data_err_num",
-                &format_args!("{}", self.usr_data_err_num().bits()),
-            )
-            .field(
-                "usr_data_fail",
-                &format_args!("{}", self.usr_data_fail().bit()),
-            )
-            .field(
-                "key0_err_num",
-                &format_args!("{}", self.key0_err_num().bits()),
-            )
-            .field("key0_fail", &format_args!("{}", self.key0_fail().bit()))
-            .field(
-                "key1_err_num",
-                &format_args!("{}", self.key1_err_num().bits()),
-            )
-            .field("key1_fail", &format_args!("{}", self.key1_fail().bit()))
-            .field(
-                "key2_err_num",
-                &format_args!("{}", self.key2_err_num().bits()),
-            )
-            .field("key2_fail", &format_args!("{}", self.key2_fail().bit()))
-            .field(
-                "key3_err_num",
-                &format_args!("{}", self.key3_err_num().bits()),
-            )
-            .field("key3_fail", &format_args!("{}", self.key3_fail().bit()))
-            .field(
-                "key4_err_num",
-                &format_args!("{}", self.key4_err_num().bits()),
-            )
-            .field("key4_fail", &format_args!("{}", self.key4_fail().bit()))
+            .field("mac_spi_8m_err_num", &self.mac_spi_8m_err_num())
+            .field("mac_spi_8m_fail", &self.mac_spi_8m_fail())
+            .field("sys_part1_num", &self.sys_part1_num())
+            .field("sys_part1_fail", &self.sys_part1_fail())
+            .field("usr_data_err_num", &self.usr_data_err_num())
+            .field("usr_data_fail", &self.usr_data_fail())
+            .field("key0_err_num", &self.key0_err_num())
+            .field("key0_fail", &self.key0_fail())
+            .field("key1_err_num", &self.key1_err_num())
+            .field("key1_fail", &self.key1_fail())
+            .field("key2_err_num", &self.key2_err_num())
+            .field("key2_fail", &self.key2_fail())
+            .field("key3_err_num", &self.key3_err_num())
+            .field("key3_fail", &self.key3_fail())
+            .field("key4_err_num", &self.key4_err_num())
+            .field("key4_fail", &self.key4_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RS_ERR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 0 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RS_ERR0_SPEC;
 impl crate::RegisterSpec for RD_RS_ERR0_SPEC {
diff --git a/esp32c6/src/efuse/rd_rs_err1.rs b/esp32c6/src/efuse/rd_rs_err1.rs
index 04fe9a9db1..188a8b967f 100644
--- a/esp32c6/src/efuse/rd_rs_err1.rs
+++ b/esp32c6/src/efuse/rd_rs_err1.rs
@@ -34,28 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_RS_ERR1")
-            .field(
-                "key5_err_num",
-                &format_args!("{}", self.key5_err_num().bits()),
-            )
-            .field("key5_fail", &format_args!("{}", self.key5_fail().bit()))
-            .field(
-                "sys_part2_err_num",
-                &format_args!("{}", self.sys_part2_err_num().bits()),
-            )
-            .field(
-                "sys_part2_fail",
-                &format_args!("{}", self.sys_part2_fail().bit()),
-            )
+            .field("key5_err_num", &self.key5_err_num())
+            .field("key5_fail", &self.key5_fail())
+            .field("sys_part2_err_num", &self.sys_part2_err_num())
+            .field("sys_part2_fail", &self.sys_part2_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RS_ERR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 1 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RS_ERR1_SPEC;
 impl crate::RegisterSpec for RD_RS_ERR1_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part1_data0.rs b/esp32c6/src/efuse/rd_sys_part1_data0.rs
index f28c3bd2d0..d6b4a065d4 100644
--- a/esp32c6/src/efuse/rd_sys_part1_data0.rs
+++ b/esp32c6/src/efuse/rd_sys_part1_data0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA0")
-            .field(
-                "sys_data_part1_0",
-                &format_args!("{}", self.sys_data_part1_0().bits()),
-            )
+            .field("sys_data_part1_0", &self.sys_data_part1_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA0_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA0_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part1_data1.rs b/esp32c6/src/efuse/rd_sys_part1_data1.rs
index c7345ebcfe..aa8b5a77e1 100644
--- a/esp32c6/src/efuse/rd_sys_part1_data1.rs
+++ b/esp32c6/src/efuse/rd_sys_part1_data1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA1")
-            .field(
-                "sys_data_part1_1",
-                &format_args!("{}", self.sys_data_part1_1().bits()),
-            )
+            .field("sys_data_part1_1", &self.sys_data_part1_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA1_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA1_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part1_data2.rs b/esp32c6/src/efuse/rd_sys_part1_data2.rs
index 00d8eee981..6ce86ab9ea 100644
--- a/esp32c6/src/efuse/rd_sys_part1_data2.rs
+++ b/esp32c6/src/efuse/rd_sys_part1_data2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA2")
-            .field(
-                "sys_data_part1_2",
-                &format_args!("{}", self.sys_data_part1_2().bits()),
-            )
+            .field("sys_data_part1_2", &self.sys_data_part1_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA2_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA2_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part1_data3.rs b/esp32c6/src/efuse/rd_sys_part1_data3.rs
index 1025d41a34..f3c8563223 100644
--- a/esp32c6/src/efuse/rd_sys_part1_data3.rs
+++ b/esp32c6/src/efuse/rd_sys_part1_data3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA3")
-            .field(
-                "sys_data_part1_3",
-                &format_args!("{}", self.sys_data_part1_3().bits()),
-            )
+            .field("sys_data_part1_3", &self.sys_data_part1_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA3_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA3_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part1_data4.rs b/esp32c6/src/efuse/rd_sys_part1_data4.rs
index 11e51eb81d..c3a05173b2 100644
--- a/esp32c6/src/efuse/rd_sys_part1_data4.rs
+++ b/esp32c6/src/efuse/rd_sys_part1_data4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA4")
-            .field(
-                "sys_data_part1_4",
-                &format_args!("{}", self.sys_data_part1_4().bits()),
-            )
+            .field("sys_data_part1_4", &self.sys_data_part1_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA4_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA4_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part1_data5.rs b/esp32c6/src/efuse/rd_sys_part1_data5.rs
index f6e08ae404..06e29f147d 100644
--- a/esp32c6/src/efuse/rd_sys_part1_data5.rs
+++ b/esp32c6/src/efuse/rd_sys_part1_data5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA5")
-            .field(
-                "sys_data_part1_5",
-                &format_args!("{}", self.sys_data_part1_5().bits()),
-            )
+            .field("sys_data_part1_5", &self.sys_data_part1_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA5_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA5_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part1_data6.rs b/esp32c6/src/efuse/rd_sys_part1_data6.rs
index 9065b698dc..3fd9b053a9 100644
--- a/esp32c6/src/efuse/rd_sys_part1_data6.rs
+++ b/esp32c6/src/efuse/rd_sys_part1_data6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA6")
-            .field(
-                "sys_data_part1_6",
-                &format_args!("{}", self.sys_data_part1_6().bits()),
-            )
+            .field("sys_data_part1_6", &self.sys_data_part1_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA6_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA6_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part1_data7.rs b/esp32c6/src/efuse/rd_sys_part1_data7.rs
index cacdcd1f63..c87a01c324 100644
--- a/esp32c6/src/efuse/rd_sys_part1_data7.rs
+++ b/esp32c6/src/efuse/rd_sys_part1_data7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA7")
-            .field(
-                "sys_data_part1_7",
-                &format_args!("{}", self.sys_data_part1_7().bits()),
-            )
+            .field("sys_data_part1_7", &self.sys_data_part1_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA7_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA7_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part2_data0.rs b/esp32c6/src/efuse/rd_sys_part2_data0.rs
index 1feb2a9015..47d38ca228 100644
--- a/esp32c6/src/efuse/rd_sys_part2_data0.rs
+++ b/esp32c6/src/efuse/rd_sys_part2_data0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA0")
-            .field(
-                "sys_data_part2_0",
-                &format_args!("{}", self.sys_data_part2_0().bits()),
-            )
+            .field("sys_data_part2_0", &self.sys_data_part2_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA0_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA0_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part2_data1.rs b/esp32c6/src/efuse/rd_sys_part2_data1.rs
index 3d524a829e..52a84368ae 100644
--- a/esp32c6/src/efuse/rd_sys_part2_data1.rs
+++ b/esp32c6/src/efuse/rd_sys_part2_data1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA1")
-            .field(
-                "sys_data_part2_1",
-                &format_args!("{}", self.sys_data_part2_1().bits()),
-            )
+            .field("sys_data_part2_1", &self.sys_data_part2_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA1_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA1_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part2_data2.rs b/esp32c6/src/efuse/rd_sys_part2_data2.rs
index 011eb41ba8..ae963cb031 100644
--- a/esp32c6/src/efuse/rd_sys_part2_data2.rs
+++ b/esp32c6/src/efuse/rd_sys_part2_data2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA2")
-            .field(
-                "sys_data_part2_2",
-                &format_args!("{}", self.sys_data_part2_2().bits()),
-            )
+            .field("sys_data_part2_2", &self.sys_data_part2_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA2_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA2_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part2_data3.rs b/esp32c6/src/efuse/rd_sys_part2_data3.rs
index 68647c349c..a5d4a31845 100644
--- a/esp32c6/src/efuse/rd_sys_part2_data3.rs
+++ b/esp32c6/src/efuse/rd_sys_part2_data3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA3")
-            .field(
-                "sys_data_part2_3",
-                &format_args!("{}", self.sys_data_part2_3().bits()),
-            )
+            .field("sys_data_part2_3", &self.sys_data_part2_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA3_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA3_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part2_data4.rs b/esp32c6/src/efuse/rd_sys_part2_data4.rs
index 23800044fb..4af91484c2 100644
--- a/esp32c6/src/efuse/rd_sys_part2_data4.rs
+++ b/esp32c6/src/efuse/rd_sys_part2_data4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA4")
-            .field(
-                "sys_data_part2_4",
-                &format_args!("{}", self.sys_data_part2_4().bits()),
-            )
+            .field("sys_data_part2_4", &self.sys_data_part2_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA4_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA4_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part2_data5.rs b/esp32c6/src/efuse/rd_sys_part2_data5.rs
index f90b719995..4008d14046 100644
--- a/esp32c6/src/efuse/rd_sys_part2_data5.rs
+++ b/esp32c6/src/efuse/rd_sys_part2_data5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA5")
-            .field(
-                "sys_data_part2_5",
-                &format_args!("{}", self.sys_data_part2_5().bits()),
-            )
+            .field("sys_data_part2_5", &self.sys_data_part2_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA5_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA5_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part2_data6.rs b/esp32c6/src/efuse/rd_sys_part2_data6.rs
index ae9ccbcd43..b9c78c0f10 100644
--- a/esp32c6/src/efuse/rd_sys_part2_data6.rs
+++ b/esp32c6/src/efuse/rd_sys_part2_data6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA6")
-            .field(
-                "sys_data_part2_6",
-                &format_args!("{}", self.sys_data_part2_6().bits()),
-            )
+            .field("sys_data_part2_6", &self.sys_data_part2_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA6_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA6_SPEC {
diff --git a/esp32c6/src/efuse/rd_sys_part2_data7.rs b/esp32c6/src/efuse/rd_sys_part2_data7.rs
index bed90d73b1..3b790bc9a9 100644
--- a/esp32c6/src/efuse/rd_sys_part2_data7.rs
+++ b/esp32c6/src/efuse/rd_sys_part2_data7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA7")
-            .field(
-                "sys_data_part2_7",
-                &format_args!("{}", self.sys_data_part2_7().bits()),
-            )
+            .field("sys_data_part2_7", &self.sys_data_part2_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA7_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA7_SPEC {
diff --git a/esp32c6/src/efuse/rd_tim_conf.rs b/esp32c6/src/efuse/rd_tim_conf.rs
index a1e9390839..a2e9f53a46 100644
--- a/esp32c6/src/efuse/rd_tim_conf.rs
+++ b/esp32c6/src/efuse/rd_tim_conf.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_TIM_CONF")
-            .field("thr_a", &format_args!("{}", self.thr_a().bits()))
-            .field("trd", &format_args!("{}", self.trd().bits()))
-            .field("tsur_a", &format_args!("{}", self.tsur_a().bits()))
-            .field(
-                "read_init_num",
-                &format_args!("{}", self.read_init_num().bits()),
-            )
+            .field("thr_a", &self.thr_a())
+            .field("trd", &self.trd())
+            .field("tsur_a", &self.tsur_a())
+            .field("read_init_num", &self.read_init_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_TIM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures the read hold time."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/rd_usr_data0.rs b/esp32c6/src/efuse/rd_usr_data0.rs
index 4e204bad47..28f2066b68 100644
--- a/esp32c6/src/efuse/rd_usr_data0.rs
+++ b/esp32c6/src/efuse/rd_usr_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA0")
-            .field("usr_data0", &format_args!("{}", self.usr_data0().bits()))
+            .field("usr_data0", &self.usr_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA0_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA0_SPEC {
diff --git a/esp32c6/src/efuse/rd_usr_data1.rs b/esp32c6/src/efuse/rd_usr_data1.rs
index d7c72fc40c..9477844df7 100644
--- a/esp32c6/src/efuse/rd_usr_data1.rs
+++ b/esp32c6/src/efuse/rd_usr_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA1")
-            .field("usr_data1", &format_args!("{}", self.usr_data1().bits()))
+            .field("usr_data1", &self.usr_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA1_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA1_SPEC {
diff --git a/esp32c6/src/efuse/rd_usr_data2.rs b/esp32c6/src/efuse/rd_usr_data2.rs
index 8169877859..aab23fdcd6 100644
--- a/esp32c6/src/efuse/rd_usr_data2.rs
+++ b/esp32c6/src/efuse/rd_usr_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA2")
-            .field("usr_data2", &format_args!("{}", self.usr_data2().bits()))
+            .field("usr_data2", &self.usr_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA2_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA2_SPEC {
diff --git a/esp32c6/src/efuse/rd_usr_data3.rs b/esp32c6/src/efuse/rd_usr_data3.rs
index 287031c261..a60ac76725 100644
--- a/esp32c6/src/efuse/rd_usr_data3.rs
+++ b/esp32c6/src/efuse/rd_usr_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA3")
-            .field("usr_data3", &format_args!("{}", self.usr_data3().bits()))
+            .field("usr_data3", &self.usr_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA3_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA3_SPEC {
diff --git a/esp32c6/src/efuse/rd_usr_data4.rs b/esp32c6/src/efuse/rd_usr_data4.rs
index 59455cc92b..2c176b3b03 100644
--- a/esp32c6/src/efuse/rd_usr_data4.rs
+++ b/esp32c6/src/efuse/rd_usr_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA4")
-            .field("usr_data4", &format_args!("{}", self.usr_data4().bits()))
+            .field("usr_data4", &self.usr_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA4_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA4_SPEC {
diff --git a/esp32c6/src/efuse/rd_usr_data5.rs b/esp32c6/src/efuse/rd_usr_data5.rs
index 497253e518..23dcc42bfc 100644
--- a/esp32c6/src/efuse/rd_usr_data5.rs
+++ b/esp32c6/src/efuse/rd_usr_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA5")
-            .field("usr_data5", &format_args!("{}", self.usr_data5().bits()))
+            .field("usr_data5", &self.usr_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA5_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA5_SPEC {
diff --git a/esp32c6/src/efuse/rd_usr_data6.rs b/esp32c6/src/efuse/rd_usr_data6.rs
index ca48ef1451..3191eb6699 100644
--- a/esp32c6/src/efuse/rd_usr_data6.rs
+++ b/esp32c6/src/efuse/rd_usr_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA6")
-            .field("usr_data6", &format_args!("{}", self.usr_data6().bits()))
+            .field("usr_data6", &self.usr_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA6_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA6_SPEC {
diff --git a/esp32c6/src/efuse/rd_usr_data7.rs b/esp32c6/src/efuse/rd_usr_data7.rs
index 794da1f32e..58df0ecfa5 100644
--- a/esp32c6/src/efuse/rd_usr_data7.rs
+++ b/esp32c6/src/efuse/rd_usr_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA7")
-            .field("usr_data7", &format_args!("{}", self.usr_data7().bits()))
+            .field("usr_data7", &self.usr_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA7_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA7_SPEC {
diff --git a/esp32c6/src/efuse/rd_wr_dis.rs b/esp32c6/src/efuse/rd_wr_dis.rs
index cd942a2900..6dc46e09a0 100644
--- a/esp32c6/src/efuse/rd_wr_dis.rs
+++ b/esp32c6/src/efuse/rd_wr_dis.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_WR_DIS")
-            .field("wr_dis", &format_args!("{}", self.wr_dis().bits()))
+            .field("wr_dis", &self.wr_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_WR_DIS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_wr_dis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_WR_DIS_SPEC;
 impl crate::RegisterSpec for RD_WR_DIS_SPEC {
diff --git a/esp32c6/src/efuse/status.rs b/esp32c6/src/efuse/status.rs
index 7b9d4da2a7..b5e6515c6a 100644
--- a/esp32c6/src/efuse/status.rs
+++ b/esp32c6/src/efuse/status.rs
@@ -62,38 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field("otp_load_sw", &format_args!("{}", self.otp_load_sw().bit()))
-            .field(
-                "otp_vddq_c_sync2",
-                &format_args!("{}", self.otp_vddq_c_sync2().bit()),
-            )
-            .field(
-                "otp_strobe_sw",
-                &format_args!("{}", self.otp_strobe_sw().bit()),
-            )
-            .field("otp_csb_sw", &format_args!("{}", self.otp_csb_sw().bit()))
-            .field(
-                "otp_pgenb_sw",
-                &format_args!("{}", self.otp_pgenb_sw().bit()),
-            )
-            .field(
-                "otp_vddq_is_sw",
-                &format_args!("{}", self.otp_vddq_is_sw().bit()),
-            )
-            .field(
-                "blk0_valid_bit_cnt",
-                &format_args!("{}", self.blk0_valid_bit_cnt().bits()),
-            )
+            .field("state", &self.state())
+            .field("otp_load_sw", &self.otp_load_sw())
+            .field("otp_vddq_c_sync2", &self.otp_vddq_c_sync2())
+            .field("otp_strobe_sw", &self.otp_strobe_sw())
+            .field("otp_csb_sw", &self.otp_csb_sw())
+            .field("otp_pgenb_sw", &self.otp_pgenb_sw())
+            .field("otp_vddq_is_sw", &self.otp_vddq_is_sw())
+            .field("blk0_valid_bit_cnt", &self.blk0_valid_bit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32c6/src/efuse/wr_tim_conf0_rs_bypass.rs b/esp32c6/src/efuse/wr_tim_conf0_rs_bypass.rs
index f460ea6d75..9085305267 100644
--- a/esp32c6/src/efuse/wr_tim_conf0_rs_bypass.rs
+++ b/esp32c6/src/efuse/wr_tim_conf0_rs_bypass.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF0_RS_BYPASS")
-            .field(
-                "bypass_rs_correction",
-                &format_args!("{}", self.bypass_rs_correction().bit()),
-            )
-            .field(
-                "bypass_rs_blk_num",
-                &format_args!("{}", self.bypass_rs_blk_num().bits()),
-            )
-            .field(
-                "tpgm_inactive",
-                &format_args!("{}", self.tpgm_inactive().bits()),
-            )
+            .field("bypass_rs_correction", &self.bypass_rs_correction())
+            .field("bypass_rs_blk_num", &self.bypass_rs_blk_num())
+            .field("tpgm_inactive", &self.tpgm_inactive())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF0_RS_BYPASS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to bypass reed solomon correction step."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/wr_tim_conf1.rs b/esp32c6/src/efuse/wr_tim_conf1.rs
index ccecffe15b..0a9fb5b7bf 100644
--- a/esp32c6/src/efuse/wr_tim_conf1.rs
+++ b/esp32c6/src/efuse/wr_tim_conf1.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF1")
-            .field("tsup_a", &format_args!("{}", self.tsup_a().bits()))
-            .field("pwr_on_num", &format_args!("{}", self.pwr_on_num().bits()))
-            .field("thp_a", &format_args!("{}", self.thp_a().bits()))
+            .field("tsup_a", &self.tsup_a())
+            .field("pwr_on_num", &self.pwr_on_num())
+            .field("thp_a", &self.thp_a())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures the programming setup time."]
     #[inline(always)]
diff --git a/esp32c6/src/efuse/wr_tim_conf2.rs b/esp32c6/src/efuse/wr_tim_conf2.rs
index 5493c22379..d6fd0b688b 100644
--- a/esp32c6/src/efuse/wr_tim_conf2.rs
+++ b/esp32c6/src/efuse/wr_tim_conf2.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF2")
-            .field(
-                "pwr_off_num",
-                &format_args!("{}", self.pwr_off_num().bits()),
-            )
-            .field("tpgm", &format_args!("{}", self.tpgm().bits()))
+            .field("pwr_off_num", &self.pwr_off_num())
+            .field("tpgm", &self.tpgm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures the power outage time for VDDQ."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/cache_lock_addr.rs b/esp32c6/src/extmem/cache_lock_addr.rs
index 73d459daa4..c302c60633 100644
--- a/esp32c6/src/extmem/cache_lock_addr.rs
+++ b/esp32c6/src/extmem/cache_lock_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_LOCK_ADDR")
-            .field(
-                "cache_lock_addr",
-                &format_args!("{}", self.cache_lock_addr().bits()),
-            )
+            .field("cache_lock_addr", &self.cache_lock_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_LOCK_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/cache_lock_ctrl.rs b/esp32c6/src/extmem/cache_lock_ctrl.rs
index 38ea6cc775..db5c7c46b3 100644
--- a/esp32c6/src/extmem/cache_lock_ctrl.rs
+++ b/esp32c6/src/extmem/cache_lock_ctrl.rs
@@ -40,31 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_LOCK_CTRL")
-            .field(
-                "cache_lock_ena",
-                &format_args!("{}", self.cache_lock_ena().bit()),
-            )
-            .field(
-                "cache_unlock_ena",
-                &format_args!("{}", self.cache_unlock_ena().bit()),
-            )
-            .field(
-                "cache_lock_done",
-                &format_args!("{}", self.cache_lock_done().bit()),
-            )
-            .field(
-                "cache_lock_rgid",
-                &format_args!("{}", self.cache_lock_rgid().bits()),
-            )
+            .field("cache_lock_ena", &self.cache_lock_ena())
+            .field("cache_unlock_ena", &self.cache_unlock_ena())
+            .field("cache_lock_done", &self.cache_lock_done())
+            .field("cache_lock_rgid", &self.cache_lock_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_LOCK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done"]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/cache_lock_map.rs b/esp32c6/src/extmem/cache_lock_map.rs
index 70cc5c299c..9c54543558 100644
--- a/esp32c6/src/extmem/cache_lock_map.rs
+++ b/esp32c6/src/extmem/cache_lock_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_LOCK_MAP")
-            .field(
-                "cache_lock_map",
-                &format_args!("{}", self.cache_lock_map().bits()),
-            )
+            .field("cache_lock_map", &self.cache_lock_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_LOCK_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. \\[4\\]: L1-Cache"]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/cache_lock_size.rs b/esp32c6/src/extmem/cache_lock_size.rs
index 292d39164a..e4b77ae39c 100644
--- a/esp32c6/src/extmem/cache_lock_size.rs
+++ b/esp32c6/src/extmem/cache_lock_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_LOCK_SIZE")
-            .field(
-                "cache_lock_size",
-                &format_args!("{}", self.cache_lock_size().bits()),
-            )
+            .field("cache_lock_size", &self.cache_lock_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_LOCK_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/cache_sync_addr.rs b/esp32c6/src/extmem/cache_sync_addr.rs
index f87792ae15..6c89313b01 100644
--- a/esp32c6/src/extmem/cache_sync_addr.rs
+++ b/esp32c6/src/extmem/cache_sync_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_SYNC_ADDR")
-            .field(
-                "cache_sync_addr",
-                &format_args!("{}", self.cache_sync_addr().bits()),
-            )
+            .field("cache_sync_addr", &self.cache_sync_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_SYNC_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/cache_sync_ctrl.rs b/esp32c6/src/extmem/cache_sync_ctrl.rs
index be2543f537..7d13854276 100644
--- a/esp32c6/src/extmem/cache_sync_ctrl.rs
+++ b/esp32c6/src/extmem/cache_sync_ctrl.rs
@@ -58,39 +58,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_SYNC_CTRL")
-            .field(
-                "cache_invalidate_ena",
-                &format_args!("{}", self.cache_invalidate_ena().bit()),
-            )
-            .field(
-                "cache_clean_ena",
-                &format_args!("{}", self.cache_clean_ena().bit()),
-            )
-            .field(
-                "cache_writeback_ena",
-                &format_args!("{}", self.cache_writeback_ena().bit()),
-            )
+            .field("cache_invalidate_ena", &self.cache_invalidate_ena())
+            .field("cache_clean_ena", &self.cache_clean_ena())
+            .field("cache_writeback_ena", &self.cache_writeback_ena())
             .field(
                 "cache_writeback_invalidate_ena",
-                &format_args!("{}", self.cache_writeback_invalidate_ena().bit()),
-            )
-            .field(
-                "cache_sync_done",
-                &format_args!("{}", self.cache_sync_done().bit()),
-            )
-            .field(
-                "cache_sync_rgid",
-                &format_args!("{}", self.cache_sync_rgid().bits()),
+                &self.cache_writeback_invalidate_ena(),
             )
+            .field("cache_sync_done", &self.cache_sync_done())
+            .field("cache_sync_rgid", &self.cache_sync_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_SYNC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/cache_sync_map.rs b/esp32c6/src/extmem/cache_sync_map.rs
index a7e3813516..78caec59f1 100644
--- a/esp32c6/src/extmem/cache_sync_map.rs
+++ b/esp32c6/src/extmem/cache_sync_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_SYNC_MAP")
-            .field(
-                "cache_sync_map",
-                &format_args!("{}", self.cache_sync_map().bits()),
-            )
+            .field("cache_sync_map", &self.cache_sync_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_SYNC_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation. \\[4\\]: L1-Cache"]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/cache_sync_size.rs b/esp32c6/src/extmem/cache_sync_size.rs
index d1bd2e82fe..ebfc296ef8 100644
--- a/esp32c6/src/extmem/cache_sync_size.rs
+++ b/esp32c6/src/extmem/cache_sync_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_SYNC_SIZE")
-            .field(
-                "cache_sync_size",
-                &format_args!("{}", self.cache_sync_size().bits()),
-            )
+            .field("cache_sync_size", &self.cache_sync_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_SYNC_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/clock_gate.rs b/esp32c6/src/extmem/clock_gate.rs
index 9396387567..1798054b1a 100644
--- a/esp32c6/src/extmem/clock_gate.rs
+++ b/esp32c6/src/extmem/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable clock gate when access all registers in this module."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/date.rs b/esp32c6/src/extmem/date.rs
index fc5a6ba796..9e1ecdff7d 100644
--- a/esp32c6/src/extmem/date.rs
+++ b/esp32c6/src/extmem/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/extmem/l1_bus0_acs_conflict_cnt.rs b/esp32c6/src/extmem/l1_bus0_acs_conflict_cnt.rs
index 39055b346f..1d49f3aff2 100644
--- a/esp32c6/src/extmem/l1_bus0_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l1_bus0_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_BUS0_ACS_CONFLICT_CNT")
-            .field(
-                "l1_bus0_conflict_cnt",
-                &format_args!("{}", self.l1_bus0_conflict_cnt().bits()),
-            )
+            .field("l1_bus0_conflict_cnt", &self.l1_bus0_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_BUS0_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_bus0_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_BUS0_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_BUS0_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_bus0_acs_hit_cnt.rs b/esp32c6/src/extmem/l1_bus0_acs_hit_cnt.rs
index e30393b61a..4eb6f96c51 100644
--- a/esp32c6/src/extmem/l1_bus0_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l1_bus0_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_BUS0_ACS_HIT_CNT")
-            .field(
-                "l1_bus0_hit_cnt",
-                &format_args!("{}", self.l1_bus0_hit_cnt().bits()),
-            )
+            .field("l1_bus0_hit_cnt", &self.l1_bus0_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_BUS0_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_bus0_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_BUS0_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_BUS0_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_bus0_acs_miss_cnt.rs b/esp32c6/src/extmem/l1_bus0_acs_miss_cnt.rs
index bb00291dcf..47f18138e2 100644
--- a/esp32c6/src/extmem/l1_bus0_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l1_bus0_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_BUS0_ACS_MISS_CNT")
-            .field(
-                "l1_bus0_miss_cnt",
-                &format_args!("{}", self.l1_bus0_miss_cnt().bits()),
-            )
+            .field("l1_bus0_miss_cnt", &self.l1_bus0_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_BUS0_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_bus0_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_BUS0_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_BUS0_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_bus0_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l1_bus0_acs_nxtlvl_cnt.rs
index 31630a0a06..33613253aa 100644
--- a/esp32c6/src/extmem/l1_bus0_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l1_bus0_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_BUS0_ACS_NXTLVL_CNT")
-            .field(
-                "l1_bus0_nxtlvl_cnt",
-                &format_args!("{}", self.l1_bus0_nxtlvl_cnt().bits()),
-            )
+            .field("l1_bus0_nxtlvl_cnt", &self.l1_bus0_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_BUS0_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_bus0_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_BUS0_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L1_BUS0_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_bus1_acs_conflict_cnt.rs b/esp32c6/src/extmem/l1_bus1_acs_conflict_cnt.rs
index b0d1867a27..24aea8625c 100644
--- a/esp32c6/src/extmem/l1_bus1_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l1_bus1_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_BUS1_ACS_CONFLICT_CNT")
-            .field(
-                "l1_bus1_conflict_cnt",
-                &format_args!("{}", self.l1_bus1_conflict_cnt().bits()),
-            )
+            .field("l1_bus1_conflict_cnt", &self.l1_bus1_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_BUS1_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_bus1_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_BUS1_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_BUS1_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_bus1_acs_hit_cnt.rs b/esp32c6/src/extmem/l1_bus1_acs_hit_cnt.rs
index f50c939072..fbefad990f 100644
--- a/esp32c6/src/extmem/l1_bus1_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l1_bus1_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_BUS1_ACS_HIT_CNT")
-            .field(
-                "l1_bus1_hit_cnt",
-                &format_args!("{}", self.l1_bus1_hit_cnt().bits()),
-            )
+            .field("l1_bus1_hit_cnt", &self.l1_bus1_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_BUS1_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_bus1_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_BUS1_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_BUS1_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_bus1_acs_miss_cnt.rs b/esp32c6/src/extmem/l1_bus1_acs_miss_cnt.rs
index 9a126dd23b..142664ff86 100644
--- a/esp32c6/src/extmem/l1_bus1_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l1_bus1_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_BUS1_ACS_MISS_CNT")
-            .field(
-                "l1_bus1_miss_cnt",
-                &format_args!("{}", self.l1_bus1_miss_cnt().bits()),
-            )
+            .field("l1_bus1_miss_cnt", &self.l1_bus1_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_BUS1_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_bus1_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_BUS1_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_BUS1_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_bus1_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l1_bus1_acs_nxtlvl_cnt.rs
index c53dec3892..2a812c97f7 100644
--- a/esp32c6/src/extmem/l1_bus1_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l1_bus1_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_BUS1_ACS_NXTLVL_CNT")
-            .field(
-                "l1_bus1_nxtlvl_cnt",
-                &format_args!("{}", self.l1_bus1_nxtlvl_cnt().bits()),
-            )
+            .field("l1_bus1_nxtlvl_cnt", &self.l1_bus1_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_BUS1_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_bus1_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_BUS1_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L1_BUS1_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_bypass_cache_conf.rs b/esp32c6/src/extmem/l1_bypass_cache_conf.rs
index dec0ae7221..7d6dd1c6af 100644
--- a/esp32c6/src/extmem/l1_bypass_cache_conf.rs
+++ b/esp32c6/src/extmem/l1_bypass_cache_conf.rs
@@ -41,35 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_BYPASS_CACHE_CONF")
-            .field(
-                "bypass_l1_icache0_en",
-                &format_args!("{}", self.bypass_l1_icache0_en().bit()),
-            )
-            .field(
-                "bypass_l1_icache1_en",
-                &format_args!("{}", self.bypass_l1_icache1_en().bit()),
-            )
-            .field(
-                "bypass_l1_icache2_en",
-                &format_args!("{}", self.bypass_l1_icache2_en().bit()),
-            )
-            .field(
-                "bypass_l1_icache3_en",
-                &format_args!("{}", self.bypass_l1_icache3_en().bit()),
-            )
-            .field(
-                "bypass_l1_dcache_en",
-                &format_args!("{}", self.bypass_l1_dcache_en().bit()),
-            )
+            .field("bypass_l1_icache0_en", &self.bypass_l1_icache0_en())
+            .field("bypass_l1_icache1_en", &self.bypass_l1_icache1_en())
+            .field("bypass_l1_icache2_en", &self.bypass_l1_icache2_en())
+            .field("bypass_l1_icache3_en", &self.bypass_l1_icache3_en())
+            .field("bypass_l1_dcache_en", &self.bypass_l1_dcache_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_BYPASS_CACHE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Bypass Cache configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_bypass_cache_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_BYPASS_CACHE_CONF_SPEC;
 impl crate::RegisterSpec for L1_BYPASS_CACHE_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l1_cache_acs_cnt_ctrl.rs b/esp32c6/src/extmem/l1_cache_acs_cnt_ctrl.rs
index 7c7ca85845..09a878f8ef 100644
--- a/esp32c6/src/extmem/l1_cache_acs_cnt_ctrl.rs
+++ b/esp32c6/src/extmem/l1_cache_acs_cnt_ctrl.rs
@@ -114,71 +114,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_CNT_CTRL")
-            .field(
-                "l1_ibus0_cnt_ena",
-                &format_args!("{}", self.l1_ibus0_cnt_ena().bit()),
-            )
-            .field(
-                "l1_ibus1_cnt_ena",
-                &format_args!("{}", self.l1_ibus1_cnt_ena().bit()),
-            )
-            .field(
-                "l1_ibus2_cnt_ena",
-                &format_args!("{}", self.l1_ibus2_cnt_ena().bit()),
-            )
-            .field(
-                "l1_ibus3_cnt_ena",
-                &format_args!("{}", self.l1_ibus3_cnt_ena().bit()),
-            )
-            .field(
-                "l1_bus0_cnt_ena",
-                &format_args!("{}", self.l1_bus0_cnt_ena().bit()),
-            )
-            .field(
-                "l1_bus1_cnt_ena",
-                &format_args!("{}", self.l1_bus1_cnt_ena().bit()),
-            )
-            .field(
-                "l1_dbus2_cnt_ena",
-                &format_args!("{}", self.l1_dbus2_cnt_ena().bit()),
-            )
-            .field(
-                "l1_dbus3_cnt_ena",
-                &format_args!("{}", self.l1_dbus3_cnt_ena().bit()),
-            )
-            .field(
-                "l1_ibus0_cnt_clr",
-                &format_args!("{}", self.l1_ibus0_cnt_clr().bit()),
-            )
-            .field(
-                "l1_ibus1_cnt_clr",
-                &format_args!("{}", self.l1_ibus1_cnt_clr().bit()),
-            )
-            .field(
-                "l1_ibus2_cnt_clr",
-                &format_args!("{}", self.l1_ibus2_cnt_clr().bit()),
-            )
-            .field(
-                "l1_ibus3_cnt_clr",
-                &format_args!("{}", self.l1_ibus3_cnt_clr().bit()),
-            )
-            .field(
-                "l1_dbus2_cnt_clr",
-                &format_args!("{}", self.l1_dbus2_cnt_clr().bit()),
-            )
-            .field(
-                "l1_dbus3_cnt_clr",
-                &format_args!("{}", self.l1_dbus3_cnt_clr().bit()),
-            )
+            .field("l1_ibus0_cnt_ena", &self.l1_ibus0_cnt_ena())
+            .field("l1_ibus1_cnt_ena", &self.l1_ibus1_cnt_ena())
+            .field("l1_ibus2_cnt_ena", &self.l1_ibus2_cnt_ena())
+            .field("l1_ibus3_cnt_ena", &self.l1_ibus3_cnt_ena())
+            .field("l1_bus0_cnt_ena", &self.l1_bus0_cnt_ena())
+            .field("l1_bus1_cnt_ena", &self.l1_bus1_cnt_ena())
+            .field("l1_dbus2_cnt_ena", &self.l1_dbus2_cnt_ena())
+            .field("l1_dbus3_cnt_ena", &self.l1_dbus3_cnt_ena())
+            .field("l1_ibus0_cnt_clr", &self.l1_ibus0_cnt_clr())
+            .field("l1_ibus1_cnt_clr", &self.l1_ibus1_cnt_clr())
+            .field("l1_ibus2_cnt_clr", &self.l1_ibus2_cnt_clr())
+            .field("l1_ibus3_cnt_clr", &self.l1_ibus3_cnt_clr())
+            .field("l1_dbus2_cnt_clr", &self.l1_dbus2_cnt_clr())
+            .field("l1_dbus3_cnt_clr", &self.l1_dbus3_cnt_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_CNT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - The bit is used to enable dbus0 counter in L1-DCache."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_acs_cnt_int_clr.rs b/esp32c6/src/extmem/l1_cache_acs_cnt_int_clr.rs
index 9657152993..a0b78e0154 100644
--- a/esp32c6/src/extmem/l1_cache_acs_cnt_int_clr.rs
+++ b/esp32c6/src/extmem/l1_cache_acs_cnt_int_clr.rs
@@ -54,39 +54,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_CNT_INT_CLR")
-            .field(
-                "l1_ibus0_ovf_int_clr",
-                &format_args!("{}", self.l1_ibus0_ovf_int_clr().bit()),
-            )
-            .field(
-                "l1_ibus1_ovf_int_clr",
-                &format_args!("{}", self.l1_ibus1_ovf_int_clr().bit()),
-            )
-            .field(
-                "l1_ibus2_ovf_int_clr",
-                &format_args!("{}", self.l1_ibus2_ovf_int_clr().bit()),
-            )
-            .field(
-                "l1_ibus3_ovf_int_clr",
-                &format_args!("{}", self.l1_ibus3_ovf_int_clr().bit()),
-            )
-            .field(
-                "l1_dbus2_ovf_int_clr",
-                &format_args!("{}", self.l1_dbus2_ovf_int_clr().bit()),
-            )
-            .field(
-                "l1_dbus3_ovf_int_clr",
-                &format_args!("{}", self.l1_dbus3_ovf_int_clr().bit()),
-            )
+            .field("l1_ibus0_ovf_int_clr", &self.l1_ibus0_ovf_int_clr())
+            .field("l1_ibus1_ovf_int_clr", &self.l1_ibus1_ovf_int_clr())
+            .field("l1_ibus2_ovf_int_clr", &self.l1_ibus2_ovf_int_clr())
+            .field("l1_ibus3_ovf_int_clr", &self.l1_ibus3_ovf_int_clr())
+            .field("l1_dbus2_ovf_int_clr", &self.l1_dbus2_ovf_int_clr())
+            .field("l1_dbus3_ovf_int_clr", &self.l1_dbus3_ovf_int_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_CNT_INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus0 accesses L1-DCache."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_acs_cnt_int_ena.rs b/esp32c6/src/extmem/l1_cache_acs_cnt_int_ena.rs
index 3dd4fe48c9..f7bb6e4870 100644
--- a/esp32c6/src/extmem/l1_cache_acs_cnt_int_ena.rs
+++ b/esp32c6/src/extmem/l1_cache_acs_cnt_int_ena.rs
@@ -68,47 +68,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_CNT_INT_ENA")
-            .field(
-                "l1_ibus0_ovf_int_ena",
-                &format_args!("{}", self.l1_ibus0_ovf_int_ena().bit()),
-            )
-            .field(
-                "l1_ibus1_ovf_int_ena",
-                &format_args!("{}", self.l1_ibus1_ovf_int_ena().bit()),
-            )
-            .field(
-                "l1_ibus2_ovf_int_ena",
-                &format_args!("{}", self.l1_ibus2_ovf_int_ena().bit()),
-            )
-            .field(
-                "l1_ibus3_ovf_int_ena",
-                &format_args!("{}", self.l1_ibus3_ovf_int_ena().bit()),
-            )
-            .field(
-                "l1_bus0_ovf_int_ena",
-                &format_args!("{}", self.l1_bus0_ovf_int_ena().bit()),
-            )
-            .field(
-                "l1_bus1_ovf_int_ena",
-                &format_args!("{}", self.l1_bus1_ovf_int_ena().bit()),
-            )
-            .field(
-                "l1_dbus2_ovf_int_ena",
-                &format_args!("{}", self.l1_dbus2_ovf_int_ena().bit()),
-            )
-            .field(
-                "l1_dbus3_ovf_int_ena",
-                &format_args!("{}", self.l1_dbus3_ovf_int_ena().bit()),
-            )
+            .field("l1_ibus0_ovf_int_ena", &self.l1_ibus0_ovf_int_ena())
+            .field("l1_ibus1_ovf_int_ena", &self.l1_ibus1_ovf_int_ena())
+            .field("l1_ibus2_ovf_int_ena", &self.l1_ibus2_ovf_int_ena())
+            .field("l1_ibus3_ovf_int_ena", &self.l1_ibus3_ovf_int_ena())
+            .field("l1_bus0_ovf_int_ena", &self.l1_bus0_ovf_int_ena())
+            .field("l1_bus1_ovf_int_ena", &self.l1_bus1_ovf_int_ena())
+            .field("l1_dbus2_ovf_int_ena", &self.l1_dbus2_ovf_int_ena())
+            .field("l1_dbus3_ovf_int_ena", &self.l1_dbus3_ovf_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_CNT_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_acs_cnt_int_raw.rs b/esp32c6/src/extmem/l1_cache_acs_cnt_int_raw.rs
index eb5e08d648..e8fa34f108 100644
--- a/esp32c6/src/extmem/l1_cache_acs_cnt_int_raw.rs
+++ b/esp32c6/src/extmem/l1_cache_acs_cnt_int_raw.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_CNT_INT_RAW")
-            .field(
-                "l1_ibus0_ovf_int_raw",
-                &format_args!("{}", self.l1_ibus0_ovf_int_raw().bit()),
-            )
-            .field(
-                "l1_ibus1_ovf_int_raw",
-                &format_args!("{}", self.l1_ibus1_ovf_int_raw().bit()),
-            )
-            .field(
-                "l1_ibus2_ovf_int_raw",
-                &format_args!("{}", self.l1_ibus2_ovf_int_raw().bit()),
-            )
-            .field(
-                "l1_ibus3_ovf_int_raw",
-                &format_args!("{}", self.l1_ibus3_ovf_int_raw().bit()),
-            )
-            .field(
-                "l1_bus0_ovf_int_raw",
-                &format_args!("{}", self.l1_bus0_ovf_int_raw().bit()),
-            )
-            .field(
-                "l1_bus1_ovf_int_raw",
-                &format_args!("{}", self.l1_bus1_ovf_int_raw().bit()),
-            )
-            .field(
-                "l1_dbus2_ovf_int_raw",
-                &format_args!("{}", self.l1_dbus2_ovf_int_raw().bit()),
-            )
-            .field(
-                "l1_dbus3_ovf_int_raw",
-                &format_args!("{}", self.l1_dbus3_ovf_int_raw().bit()),
-            )
+            .field("l1_ibus0_ovf_int_raw", &self.l1_ibus0_ovf_int_raw())
+            .field("l1_ibus1_ovf_int_raw", &self.l1_ibus1_ovf_int_raw())
+            .field("l1_ibus2_ovf_int_raw", &self.l1_ibus2_ovf_int_raw())
+            .field("l1_ibus3_ovf_int_raw", &self.l1_ibus3_ovf_int_raw())
+            .field("l1_bus0_ovf_int_raw", &self.l1_bus0_ovf_int_raw())
+            .field("l1_bus1_ovf_int_raw", &self.l1_bus1_ovf_int_raw())
+            .field("l1_dbus2_ovf_int_raw", &self.l1_dbus2_ovf_int_raw())
+            .field("l1_dbus3_ovf_int_raw", &self.l1_dbus3_ovf_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_CNT_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_acs_cnt_int_st.rs b/esp32c6/src/extmem/l1_cache_acs_cnt_int_st.rs
index 2af93660e7..0471d18916 100644
--- a/esp32c6/src/extmem/l1_cache_acs_cnt_int_st.rs
+++ b/esp32c6/src/extmem/l1_cache_acs_cnt_int_st.rs
@@ -62,47 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_CNT_INT_ST")
-            .field(
-                "l1_ibus0_ovf_int_st",
-                &format_args!("{}", self.l1_ibus0_ovf_int_st().bit()),
-            )
-            .field(
-                "l1_ibus1_ovf_int_st",
-                &format_args!("{}", self.l1_ibus1_ovf_int_st().bit()),
-            )
-            .field(
-                "l1_ibus2_ovf_int_st",
-                &format_args!("{}", self.l1_ibus2_ovf_int_st().bit()),
-            )
-            .field(
-                "l1_ibus3_ovf_int_st",
-                &format_args!("{}", self.l1_ibus3_ovf_int_st().bit()),
-            )
-            .field(
-                "l1_bus0_ovf_int_st",
-                &format_args!("{}", self.l1_bus0_ovf_int_st().bit()),
-            )
-            .field(
-                "l1_bus1_ovf_int_st",
-                &format_args!("{}", self.l1_bus1_ovf_int_st().bit()),
-            )
-            .field(
-                "l1_dbus2_ovf_int_st",
-                &format_args!("{}", self.l1_dbus2_ovf_int_st().bit()),
-            )
-            .field(
-                "l1_dbus3_ovf_int_st",
-                &format_args!("{}", self.l1_dbus3_ovf_int_st().bit()),
-            )
+            .field("l1_ibus0_ovf_int_st", &self.l1_ibus0_ovf_int_st())
+            .field("l1_ibus1_ovf_int_st", &self.l1_ibus1_ovf_int_st())
+            .field("l1_ibus2_ovf_int_st", &self.l1_ibus2_ovf_int_st())
+            .field("l1_ibus3_ovf_int_st", &self.l1_ibus3_ovf_int_st())
+            .field("l1_bus0_ovf_int_st", &self.l1_bus0_ovf_int_st())
+            .field("l1_bus1_ovf_int_st", &self.l1_bus1_ovf_int_st())
+            .field("l1_dbus2_ovf_int_st", &self.l1_dbus2_ovf_int_st())
+            .field("l1_dbus3_ovf_int_st", &self.l1_dbus3_ovf_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_CNT_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Access Counter Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_CACHE_ACS_CNT_INT_ST_SPEC;
 impl crate::RegisterSpec for L1_CACHE_ACS_CNT_INT_ST_SPEC {
diff --git a/esp32c6/src/extmem/l1_cache_acs_fail_id_attr.rs b/esp32c6/src/extmem/l1_cache_acs_fail_id_attr.rs
index 88f5fd6b25..36bfff9ab8 100644
--- a/esp32c6/src/extmem/l1_cache_acs_fail_id_attr.rs
+++ b/esp32c6/src/extmem/l1_cache_acs_fail_id_attr.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_FAIL_ID_ATTR")
-            .field(
-                "l1_cache_fail_id",
-                &format_args!("{}", self.l1_cache_fail_id().bits()),
-            )
-            .field(
-                "l1_cache_fail_attr",
-                &format_args!("{}", self.l1_cache_fail_attr().bits()),
-            )
+            .field("l1_cache_fail_id", &self.l1_cache_fail_id())
+            .field("l1_cache_fail_attr", &self.l1_cache_fail_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_FAIL_ID_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_id_attr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_CACHE_ACS_FAIL_ID_ATTR_SPEC;
 impl crate::RegisterSpec for L1_CACHE_ACS_FAIL_ID_ATTR_SPEC {
diff --git a/esp32c6/src/extmem/l1_cache_acs_fail_int_clr.rs b/esp32c6/src/extmem/l1_cache_acs_fail_int_clr.rs
index 928803a89b..75dfa3905a 100644
--- a/esp32c6/src/extmem/l1_cache_acs_fail_int_clr.rs
+++ b/esp32c6/src/extmem/l1_cache_acs_fail_int_clr.rs
@@ -38,31 +38,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_FAIL_INT_CLR")
-            .field(
-                "l1_icache0_fail_int_clr",
-                &format_args!("{}", self.l1_icache0_fail_int_clr().bit()),
-            )
-            .field(
-                "l1_icache1_fail_int_clr",
-                &format_args!("{}", self.l1_icache1_fail_int_clr().bit()),
-            )
-            .field(
-                "l1_icache2_fail_int_clr",
-                &format_args!("{}", self.l1_icache2_fail_int_clr().bit()),
-            )
-            .field(
-                "l1_icache3_fail_int_clr",
-                &format_args!("{}", self.l1_icache3_fail_int_clr().bit()),
-            )
+            .field("l1_icache0_fail_int_clr", &self.l1_icache0_fail_int_clr())
+            .field("l1_icache1_fail_int_clr", &self.l1_icache1_fail_int_clr())
+            .field("l1_icache2_fail_int_clr", &self.l1_icache2_fail_int_clr())
+            .field("l1_icache3_fail_int_clr", &self.l1_icache3_fail_int_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_FAIL_INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_acs_fail_int_ena.rs b/esp32c6/src/extmem/l1_cache_acs_fail_int_ena.rs
index d6dfa9cb3f..4cf178dfda 100644
--- a/esp32c6/src/extmem/l1_cache_acs_fail_int_ena.rs
+++ b/esp32c6/src/extmem/l1_cache_acs_fail_int_ena.rs
@@ -45,35 +45,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_FAIL_INT_ENA")
-            .field(
-                "l1_icache0_fail_int_ena",
-                &format_args!("{}", self.l1_icache0_fail_int_ena().bit()),
-            )
-            .field(
-                "l1_icache1_fail_int_ena",
-                &format_args!("{}", self.l1_icache1_fail_int_ena().bit()),
-            )
-            .field(
-                "l1_icache2_fail_int_ena",
-                &format_args!("{}", self.l1_icache2_fail_int_ena().bit()),
-            )
-            .field(
-                "l1_icache3_fail_int_ena",
-                &format_args!("{}", self.l1_icache3_fail_int_ena().bit()),
-            )
-            .field(
-                "l1_cache_fail_int_ena",
-                &format_args!("{}", self.l1_cache_fail_int_ena().bit()),
-            )
+            .field("l1_icache0_fail_int_ena", &self.l1_icache0_fail_int_ena())
+            .field("l1_icache1_fail_int_ena", &self.l1_icache1_fail_int_ena())
+            .field("l1_icache2_fail_int_ena", &self.l1_icache2_fail_int_ena())
+            .field("l1_icache3_fail_int_ena", &self.l1_icache3_fail_int_ena())
+            .field("l1_cache_fail_int_ena", &self.l1_cache_fail_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_FAIL_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_acs_fail_int_raw.rs b/esp32c6/src/extmem/l1_cache_acs_fail_int_raw.rs
index ca501782ff..fba63c096a 100644
--- a/esp32c6/src/extmem/l1_cache_acs_fail_int_raw.rs
+++ b/esp32c6/src/extmem/l1_cache_acs_fail_int_raw.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_FAIL_INT_RAW")
-            .field(
-                "l1_icache0_fail_int_raw",
-                &format_args!("{}", self.l1_icache0_fail_int_raw().bit()),
-            )
-            .field(
-                "l1_icache1_fail_int_raw",
-                &format_args!("{}", self.l1_icache1_fail_int_raw().bit()),
-            )
-            .field(
-                "l1_icache2_fail_int_raw",
-                &format_args!("{}", self.l1_icache2_fail_int_raw().bit()),
-            )
-            .field(
-                "l1_icache3_fail_int_raw",
-                &format_args!("{}", self.l1_icache3_fail_int_raw().bit()),
-            )
-            .field(
-                "l1_cache_fail_int_raw",
-                &format_args!("{}", self.l1_cache_fail_int_raw().bit()),
-            )
+            .field("l1_icache0_fail_int_raw", &self.l1_icache0_fail_int_raw())
+            .field("l1_icache1_fail_int_raw", &self.l1_icache1_fail_int_raw())
+            .field("l1_icache2_fail_int_raw", &self.l1_icache2_fail_int_raw())
+            .field("l1_icache3_fail_int_raw", &self.l1_icache3_fail_int_raw())
+            .field("l1_cache_fail_int_raw", &self.l1_cache_fail_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_FAIL_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw bit of the interrupt of access fail that occurs in L1-ICache0."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_acs_fail_int_st.rs b/esp32c6/src/extmem/l1_cache_acs_fail_int_st.rs
index f9dd952ce7..efcd8d3c89 100644
--- a/esp32c6/src/extmem/l1_cache_acs_fail_int_st.rs
+++ b/esp32c6/src/extmem/l1_cache_acs_fail_int_st.rs
@@ -41,35 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_FAIL_INT_ST")
-            .field(
-                "l1_icache0_fail_int_st",
-                &format_args!("{}", self.l1_icache0_fail_int_st().bit()),
-            )
-            .field(
-                "l1_icache1_fail_int_st",
-                &format_args!("{}", self.l1_icache1_fail_int_st().bit()),
-            )
-            .field(
-                "l1_icache2_fail_int_st",
-                &format_args!("{}", self.l1_icache2_fail_int_st().bit()),
-            )
-            .field(
-                "l1_icache3_fail_int_st",
-                &format_args!("{}", self.l1_icache3_fail_int_st().bit()),
-            )
-            .field(
-                "l1_cache_fail_int_st",
-                &format_args!("{}", self.l1_cache_fail_int_st().bit()),
-            )
+            .field("l1_icache0_fail_int_st", &self.l1_icache0_fail_int_st())
+            .field("l1_icache1_fail_int_st", &self.l1_icache1_fail_int_st())
+            .field("l1_icache2_fail_int_st", &self.l1_icache2_fail_int_st())
+            .field("l1_icache3_fail_int_st", &self.l1_icache3_fail_int_st())
+            .field("l1_cache_fail_int_st", &self.l1_cache_fail_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_FAIL_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_CACHE_ACS_FAIL_INT_ST_SPEC;
 impl crate::RegisterSpec for L1_CACHE_ACS_FAIL_INT_ST_SPEC {
diff --git a/esp32c6/src/extmem/l1_cache_atomic_conf.rs b/esp32c6/src/extmem/l1_cache_atomic_conf.rs
index f68720eb9b..31306b9b36 100644
--- a/esp32c6/src/extmem/l1_cache_atomic_conf.rs
+++ b/esp32c6/src/extmem/l1_cache_atomic_conf.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ATOMIC_CONF")
-            .field(
-                "l1_cache_atomic_en",
-                &format_args!("{}", self.l1_cache_atomic_en().bit()),
-            )
+            .field("l1_cache_atomic_en", &self.l1_cache_atomic_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ATOMIC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 Cache atomic feature configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_atomic_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_CACHE_ATOMIC_CONF_SPEC;
 impl crate::RegisterSpec for L1_CACHE_ATOMIC_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l1_cache_autoload_buf_clr_ctrl.rs b/esp32c6/src/extmem/l1_cache_autoload_buf_clr_ctrl.rs
index 4df4a59f83..1a82880ebd 100644
--- a/esp32c6/src/extmem/l1_cache_autoload_buf_clr_ctrl.rs
+++ b/esp32c6/src/extmem/l1_cache_autoload_buf_clr_ctrl.rs
@@ -45,35 +45,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_AUTOLOAD_BUF_CLR_CTRL")
-            .field(
-                "l1_icache0_ald_buf_clr",
-                &format_args!("{}", self.l1_icache0_ald_buf_clr().bit()),
-            )
-            .field(
-                "l1_icache1_ald_buf_clr",
-                &format_args!("{}", self.l1_icache1_ald_buf_clr().bit()),
-            )
-            .field(
-                "l1_icache2_ald_buf_clr",
-                &format_args!("{}", self.l1_icache2_ald_buf_clr().bit()),
-            )
-            .field(
-                "l1_icache3_ald_buf_clr",
-                &format_args!("{}", self.l1_icache3_ald_buf_clr().bit()),
-            )
-            .field(
-                "l1_cache_ald_buf_clr",
-                &format_args!("{}", self.l1_cache_ald_buf_clr().bit()),
-            )
+            .field("l1_icache0_ald_buf_clr", &self.l1_icache0_ald_buf_clr())
+            .field("l1_icache1_ald_buf_clr", &self.l1_icache1_ald_buf_clr())
+            .field("l1_icache2_ald_buf_clr", &self.l1_icache2_ald_buf_clr())
+            .field("l1_icache3_ald_buf_clr", &self.l1_icache3_ald_buf_clr())
+            .field("l1_cache_ald_buf_clr", &self.l1_cache_ald_buf_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, autoload will not work in L1-Cache. This bit should not be active when autoload works in L1-Cache."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_autoload_ctrl.rs b/esp32c6/src/extmem/l1_cache_autoload_ctrl.rs
index 5c4fe47605..d8eae59e74 100644
--- a/esp32c6/src/extmem/l1_cache_autoload_ctrl.rs
+++ b/esp32c6/src/extmem/l1_cache_autoload_ctrl.rs
@@ -81,51 +81,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_AUTOLOAD_CTRL")
-            .field(
-                "l1_cache_autoload_ena",
-                &format_args!("{}", self.l1_cache_autoload_ena().bit()),
-            )
-            .field(
-                "l1_cache_autoload_done",
-                &format_args!("{}", self.l1_cache_autoload_done().bit()),
-            )
-            .field(
-                "l1_cache_autoload_order",
-                &format_args!("{}", self.l1_cache_autoload_order().bit()),
-            )
+            .field("l1_cache_autoload_ena", &self.l1_cache_autoload_ena())
+            .field("l1_cache_autoload_done", &self.l1_cache_autoload_done())
+            .field("l1_cache_autoload_order", &self.l1_cache_autoload_order())
             .field(
                 "l1_cache_autoload_trigger_mode",
-                &format_args!("{}", self.l1_cache_autoload_trigger_mode().bits()),
+                &self.l1_cache_autoload_trigger_mode(),
             )
             .field(
                 "l1_cache_autoload_sct0_ena",
-                &format_args!("{}", self.l1_cache_autoload_sct0_ena().bit()),
+                &self.l1_cache_autoload_sct0_ena(),
             )
             .field(
                 "l1_cache_autoload_sct1_ena",
-                &format_args!("{}", self.l1_cache_autoload_sct1_ena().bit()),
+                &self.l1_cache_autoload_sct1_ena(),
             )
             .field(
                 "l1_cache_autoload_sct2_ena",
-                &format_args!("{}", self.l1_cache_autoload_sct2_ena().bit()),
+                &self.l1_cache_autoload_sct2_ena(),
             )
             .field(
                 "l1_cache_autoload_sct3_ena",
-                &format_args!("{}", self.l1_cache_autoload_sct3_ena().bit()),
-            )
-            .field(
-                "l1_cache_autoload_rgid",
-                &format_args!("{}", self.l1_cache_autoload_rgid().bits()),
+                &self.l1_cache_autoload_sct3_ena(),
             )
+            .field("l1_cache_autoload_rgid", &self.l1_cache_autoload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_AUTOLOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, 0: disable."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_autoload_sct0_addr.rs b/esp32c6/src/extmem/l1_cache_autoload_sct0_addr.rs
index d19ffdff70..7405fb1ee1 100644
--- a/esp32c6/src/extmem/l1_cache_autoload_sct0_addr.rs
+++ b/esp32c6/src/extmem/l1_cache_autoload_sct0_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_AUTOLOAD_SCT0_ADDR")
             .field(
                 "l1_cache_autoload_sct0_addr",
-                &format_args!("{}", self.l1_cache_autoload_sct0_addr().bits()),
+                &self.l1_cache_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_AUTOLOAD_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_autoload_sct0_size.rs b/esp32c6/src/extmem/l1_cache_autoload_sct0_size.rs
index 0c5a132b28..e8f6ea3cf8 100644
--- a/esp32c6/src/extmem/l1_cache_autoload_sct0_size.rs
+++ b/esp32c6/src/extmem/l1_cache_autoload_sct0_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_AUTOLOAD_SCT0_SIZE")
             .field(
                 "l1_cache_autoload_sct0_size",
-                &format_args!("{}", self.l1_cache_autoload_sct0_size().bits()),
+                &self.l1_cache_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_AUTOLOAD_SCT0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Those bits are used to configure the size of the first section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_autoload_sct1_addr.rs b/esp32c6/src/extmem/l1_cache_autoload_sct1_addr.rs
index 80aedb4664..e1c5328110 100644
--- a/esp32c6/src/extmem/l1_cache_autoload_sct1_addr.rs
+++ b/esp32c6/src/extmem/l1_cache_autoload_sct1_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_AUTOLOAD_SCT1_ADDR")
             .field(
                 "l1_cache_autoload_sct1_addr",
-                &format_args!("{}", self.l1_cache_autoload_sct1_addr().bits()),
+                &self.l1_cache_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_AUTOLOAD_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_autoload_sct1_size.rs b/esp32c6/src/extmem/l1_cache_autoload_sct1_size.rs
index 7e86822a90..48a8d253f2 100644
--- a/esp32c6/src/extmem/l1_cache_autoload_sct1_size.rs
+++ b/esp32c6/src/extmem/l1_cache_autoload_sct1_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_AUTOLOAD_SCT1_SIZE")
             .field(
                 "l1_cache_autoload_sct1_size",
-                &format_args!("{}", self.l1_cache_autoload_sct1_size().bits()),
+                &self.l1_cache_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_AUTOLOAD_SCT1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Those bits are used to configure the size of the second section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_autoload_sct2_addr.rs b/esp32c6/src/extmem/l1_cache_autoload_sct2_addr.rs
index 9dfcda786d..2579046cc3 100644
--- a/esp32c6/src/extmem/l1_cache_autoload_sct2_addr.rs
+++ b/esp32c6/src/extmem/l1_cache_autoload_sct2_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_AUTOLOAD_SCT2_ADDR")
             .field(
                 "l1_cache_autoload_sct2_addr",
-                &format_args!("{}", self.l1_cache_autoload_sct2_addr().bits()),
+                &self.l1_cache_autoload_sct2_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_AUTOLOAD_SCT2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 Cache autoload section 2 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_autoload_sct2_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_CACHE_AUTOLOAD_SCT2_ADDR_SPEC;
 impl crate::RegisterSpec for L1_CACHE_AUTOLOAD_SCT2_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_cache_autoload_sct2_size.rs b/esp32c6/src/extmem/l1_cache_autoload_sct2_size.rs
index c5fbc427ce..4b30821090 100644
--- a/esp32c6/src/extmem/l1_cache_autoload_sct2_size.rs
+++ b/esp32c6/src/extmem/l1_cache_autoload_sct2_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_AUTOLOAD_SCT2_SIZE")
             .field(
                 "l1_cache_autoload_sct2_size",
-                &format_args!("{}", self.l1_cache_autoload_sct2_size().bits()),
+                &self.l1_cache_autoload_sct2_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_AUTOLOAD_SCT2_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 Cache autoload section 2 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_autoload_sct2_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_CACHE_AUTOLOAD_SCT2_SIZE_SPEC;
 impl crate::RegisterSpec for L1_CACHE_AUTOLOAD_SCT2_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_cache_autoload_sct3_addr.rs b/esp32c6/src/extmem/l1_cache_autoload_sct3_addr.rs
index d8e9abde56..3c6047be4d 100644
--- a/esp32c6/src/extmem/l1_cache_autoload_sct3_addr.rs
+++ b/esp32c6/src/extmem/l1_cache_autoload_sct3_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_AUTOLOAD_SCT3_ADDR")
             .field(
                 "l1_cache_autoload_sct3_addr",
-                &format_args!("{}", self.l1_cache_autoload_sct3_addr().bits()),
+                &self.l1_cache_autoload_sct3_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_AUTOLOAD_SCT3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 Cache autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_autoload_sct3_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_CACHE_AUTOLOAD_SCT3_ADDR_SPEC;
 impl crate::RegisterSpec for L1_CACHE_AUTOLOAD_SCT3_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_cache_autoload_sct3_size.rs b/esp32c6/src/extmem/l1_cache_autoload_sct3_size.rs
index 37e017d8a7..87f04a1e06 100644
--- a/esp32c6/src/extmem/l1_cache_autoload_sct3_size.rs
+++ b/esp32c6/src/extmem/l1_cache_autoload_sct3_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_AUTOLOAD_SCT3_SIZE")
             .field(
                 "l1_cache_autoload_sct3_size",
-                &format_args!("{}", self.l1_cache_autoload_sct3_size().bits()),
+                &self.l1_cache_autoload_sct3_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_AUTOLOAD_SCT3_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 Cache autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_autoload_sct3_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_CACHE_AUTOLOAD_SCT3_SIZE_SPEC;
 impl crate::RegisterSpec for L1_CACHE_AUTOLOAD_SCT3_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_cache_blocksize_conf.rs b/esp32c6/src/extmem/l1_cache_blocksize_conf.rs
index 1b8dbb23c1..dfc25e3bfc 100644
--- a/esp32c6/src/extmem/l1_cache_blocksize_conf.rs
+++ b/esp32c6/src/extmem/l1_cache_blocksize_conf.rs
@@ -48,39 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_BLOCKSIZE_CONF")
-            .field(
-                "l1_cache_blocksize_8",
-                &format_args!("{}", self.l1_cache_blocksize_8().bit()),
-            )
-            .field(
-                "l1_cache_blocksize_16",
-                &format_args!("{}", self.l1_cache_blocksize_16().bit()),
-            )
-            .field(
-                "l1_cache_blocksize_32",
-                &format_args!("{}", self.l1_cache_blocksize_32().bit()),
-            )
-            .field(
-                "l1_cache_blocksize_64",
-                &format_args!("{}", self.l1_cache_blocksize_64().bit()),
-            )
-            .field(
-                "l1_cache_blocksize_128",
-                &format_args!("{}", self.l1_cache_blocksize_128().bit()),
-            )
-            .field(
-                "l1_cache_blocksize_256",
-                &format_args!("{}", self.l1_cache_blocksize_256().bit()),
-            )
+            .field("l1_cache_blocksize_8", &self.l1_cache_blocksize_8())
+            .field("l1_cache_blocksize_16", &self.l1_cache_blocksize_16())
+            .field("l1_cache_blocksize_32", &self.l1_cache_blocksize_32())
+            .field("l1_cache_blocksize_64", &self.l1_cache_blocksize_64())
+            .field("l1_cache_blocksize_128", &self.l1_cache_blocksize_128())
+            .field("l1_cache_blocksize_256", &self.l1_cache_blocksize_256())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_BLOCKSIZE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 data Cache BlockSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_blocksize_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_CACHE_BLOCKSIZE_CONF_SPEC;
 impl crate::RegisterSpec for L1_CACHE_BLOCKSIZE_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l1_cache_cachesize_conf.rs b/esp32c6/src/extmem/l1_cache_cachesize_conf.rs
index b45dae0d13..2fde48e941 100644
--- a/esp32c6/src/extmem/l1_cache_cachesize_conf.rs
+++ b/esp32c6/src/extmem/l1_cache_cachesize_conf.rs
@@ -97,67 +97,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_CACHESIZE_CONF")
-            .field(
-                "l1_cache_cachesize_1k",
-                &format_args!("{}", self.l1_cache_cachesize_1k().bit()),
-            )
-            .field(
-                "l1_cache_cachesize_2k",
-                &format_args!("{}", self.l1_cache_cachesize_2k().bit()),
-            )
-            .field(
-                "l1_cache_cachesize_4k",
-                &format_args!("{}", self.l1_cache_cachesize_4k().bit()),
-            )
-            .field(
-                "l1_cache_cachesize_8k",
-                &format_args!("{}", self.l1_cache_cachesize_8k().bit()),
-            )
-            .field(
-                "l1_cache_cachesize_16k",
-                &format_args!("{}", self.l1_cache_cachesize_16k().bit()),
-            )
-            .field(
-                "l1_cache_cachesize_32k",
-                &format_args!("{}", self.l1_cache_cachesize_32k().bit()),
-            )
-            .field(
-                "l1_cache_cachesize_64k",
-                &format_args!("{}", self.l1_cache_cachesize_64k().bit()),
-            )
-            .field(
-                "l1_cache_cachesize_128k",
-                &format_args!("{}", self.l1_cache_cachesize_128k().bit()),
-            )
-            .field(
-                "l1_cache_cachesize_256k",
-                &format_args!("{}", self.l1_cache_cachesize_256k().bit()),
-            )
-            .field(
-                "l1_cache_cachesize_512k",
-                &format_args!("{}", self.l1_cache_cachesize_512k().bit()),
-            )
-            .field(
-                "l1_cache_cachesize_1024k",
-                &format_args!("{}", self.l1_cache_cachesize_1024k().bit()),
-            )
-            .field(
-                "l1_cache_cachesize_2048k",
-                &format_args!("{}", self.l1_cache_cachesize_2048k().bit()),
-            )
-            .field(
-                "l1_cache_cachesize_4096k",
-                &format_args!("{}", self.l1_cache_cachesize_4096k().bit()),
-            )
+            .field("l1_cache_cachesize_1k", &self.l1_cache_cachesize_1k())
+            .field("l1_cache_cachesize_2k", &self.l1_cache_cachesize_2k())
+            .field("l1_cache_cachesize_4k", &self.l1_cache_cachesize_4k())
+            .field("l1_cache_cachesize_8k", &self.l1_cache_cachesize_8k())
+            .field("l1_cache_cachesize_16k", &self.l1_cache_cachesize_16k())
+            .field("l1_cache_cachesize_32k", &self.l1_cache_cachesize_32k())
+            .field("l1_cache_cachesize_64k", &self.l1_cache_cachesize_64k())
+            .field("l1_cache_cachesize_128k", &self.l1_cache_cachesize_128k())
+            .field("l1_cache_cachesize_256k", &self.l1_cache_cachesize_256k())
+            .field("l1_cache_cachesize_512k", &self.l1_cache_cachesize_512k())
+            .field("l1_cache_cachesize_1024k", &self.l1_cache_cachesize_1024k())
+            .field("l1_cache_cachesize_2048k", &self.l1_cache_cachesize_2048k())
+            .field("l1_cache_cachesize_4096k", &self.l1_cache_cachesize_4096k())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_CACHESIZE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 data Cache CacheSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_cachesize_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_CACHE_CACHESIZE_CONF_SPEC;
 impl crate::RegisterSpec for L1_CACHE_CACHESIZE_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l1_cache_ctrl.rs b/esp32c6/src/extmem/l1_cache_ctrl.rs
index ce5aa158ec..5cbe82eb4a 100644
--- a/esp32c6/src/extmem/l1_cache_ctrl.rs
+++ b/esp32c6/src/extmem/l1_cache_ctrl.rs
@@ -56,39 +56,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_CTRL")
-            .field(
-                "l1_cache_shut_bus0",
-                &format_args!("{}", self.l1_cache_shut_bus0().bit()),
-            )
-            .field(
-                "l1_cache_shut_bus1",
-                &format_args!("{}", self.l1_cache_shut_bus1().bit()),
-            )
-            .field(
-                "l1_cache_shut_dbus2",
-                &format_args!("{}", self.l1_cache_shut_dbus2().bit()),
-            )
-            .field(
-                "l1_cache_shut_dbus3",
-                &format_args!("{}", self.l1_cache_shut_dbus3().bit()),
-            )
-            .field(
-                "l1_cache_shut_dma",
-                &format_args!("{}", self.l1_cache_shut_dma().bit()),
-            )
-            .field(
-                "l1_cache_undef_op",
-                &format_args!("{}", self.l1_cache_undef_op().bits()),
-            )
+            .field("l1_cache_shut_bus0", &self.l1_cache_shut_bus0())
+            .field("l1_cache_shut_bus1", &self.l1_cache_shut_bus1())
+            .field("l1_cache_shut_dbus2", &self.l1_cache_shut_dbus2())
+            .field("l1_cache_shut_dbus3", &self.l1_cache_shut_dbus3())
+            .field("l1_cache_shut_dma", &self.l1_cache_shut_dma())
+            .field("l1_cache_undef_op", &self.l1_cache_undef_op())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable"]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_data_mem_acs_conf.rs b/esp32c6/src/extmem/l1_cache_data_mem_acs_conf.rs
index 8edf257808..b174472cdc 100644
--- a/esp32c6/src/extmem/l1_cache_data_mem_acs_conf.rs
+++ b/esp32c6/src/extmem/l1_cache_data_mem_acs_conf.rs
@@ -84,53 +84,41 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_DATA_MEM_ACS_CONF")
             .field(
                 "l1_icache0_data_mem_rd_en",
-                &format_args!("{}", self.l1_icache0_data_mem_rd_en().bit()),
+                &self.l1_icache0_data_mem_rd_en(),
             )
             .field(
                 "l1_icache0_data_mem_wr_en",
-                &format_args!("{}", self.l1_icache0_data_mem_wr_en().bit()),
+                &self.l1_icache0_data_mem_wr_en(),
             )
             .field(
                 "l1_icache1_data_mem_rd_en",
-                &format_args!("{}", self.l1_icache1_data_mem_rd_en().bit()),
+                &self.l1_icache1_data_mem_rd_en(),
             )
             .field(
                 "l1_icache1_data_mem_wr_en",
-                &format_args!("{}", self.l1_icache1_data_mem_wr_en().bit()),
+                &self.l1_icache1_data_mem_wr_en(),
             )
             .field(
                 "l1_icache2_data_mem_rd_en",
-                &format_args!("{}", self.l1_icache2_data_mem_rd_en().bit()),
+                &self.l1_icache2_data_mem_rd_en(),
             )
             .field(
                 "l1_icache2_data_mem_wr_en",
-                &format_args!("{}", self.l1_icache2_data_mem_wr_en().bit()),
+                &self.l1_icache2_data_mem_wr_en(),
             )
             .field(
                 "l1_icache3_data_mem_rd_en",
-                &format_args!("{}", self.l1_icache3_data_mem_rd_en().bit()),
+                &self.l1_icache3_data_mem_rd_en(),
             )
             .field(
                 "l1_icache3_data_mem_wr_en",
-                &format_args!("{}", self.l1_icache3_data_mem_wr_en().bit()),
-            )
-            .field(
-                "l1_cache_data_mem_rd_en",
-                &format_args!("{}", self.l1_cache_data_mem_rd_en().bit()),
-            )
-            .field(
-                "l1_cache_data_mem_wr_en",
-                &format_args!("{}", self.l1_cache_data_mem_wr_en().bit()),
+                &self.l1_icache3_data_mem_wr_en(),
             )
+            .field("l1_cache_data_mem_rd_en", &self.l1_cache_data_mem_rd_en())
+            .field("l1_cache_data_mem_wr_en", &self.l1_cache_data_mem_wr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_DATA_MEM_ACS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16 - The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: enable."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_data_mem_power_ctrl.rs b/esp32c6/src/extmem/l1_cache_data_mem_power_ctrl.rs
index a708186b56..7f6ed074a7 100644
--- a/esp32c6/src/extmem/l1_cache_data_mem_power_ctrl.rs
+++ b/esp32c6/src/extmem/l1_cache_data_mem_power_ctrl.rs
@@ -121,73 +121,67 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_DATA_MEM_POWER_CTRL")
             .field(
                 "l1_icache0_data_mem_force_on",
-                &format_args!("{}", self.l1_icache0_data_mem_force_on().bit()),
+                &self.l1_icache0_data_mem_force_on(),
             )
             .field(
                 "l1_icache0_data_mem_force_pd",
-                &format_args!("{}", self.l1_icache0_data_mem_force_pd().bit()),
+                &self.l1_icache0_data_mem_force_pd(),
             )
             .field(
                 "l1_icache0_data_mem_force_pu",
-                &format_args!("{}", self.l1_icache0_data_mem_force_pu().bit()),
+                &self.l1_icache0_data_mem_force_pu(),
             )
             .field(
                 "l1_icache1_data_mem_force_on",
-                &format_args!("{}", self.l1_icache1_data_mem_force_on().bit()),
+                &self.l1_icache1_data_mem_force_on(),
             )
             .field(
                 "l1_icache1_data_mem_force_pd",
-                &format_args!("{}", self.l1_icache1_data_mem_force_pd().bit()),
+                &self.l1_icache1_data_mem_force_pd(),
             )
             .field(
                 "l1_icache1_data_mem_force_pu",
-                &format_args!("{}", self.l1_icache1_data_mem_force_pu().bit()),
+                &self.l1_icache1_data_mem_force_pu(),
             )
             .field(
                 "l1_icache2_data_mem_force_on",
-                &format_args!("{}", self.l1_icache2_data_mem_force_on().bit()),
+                &self.l1_icache2_data_mem_force_on(),
             )
             .field(
                 "l1_icache2_data_mem_force_pd",
-                &format_args!("{}", self.l1_icache2_data_mem_force_pd().bit()),
+                &self.l1_icache2_data_mem_force_pd(),
             )
             .field(
                 "l1_icache2_data_mem_force_pu",
-                &format_args!("{}", self.l1_icache2_data_mem_force_pu().bit()),
+                &self.l1_icache2_data_mem_force_pu(),
             )
             .field(
                 "l1_icache3_data_mem_force_on",
-                &format_args!("{}", self.l1_icache3_data_mem_force_on().bit()),
+                &self.l1_icache3_data_mem_force_on(),
             )
             .field(
                 "l1_icache3_data_mem_force_pd",
-                &format_args!("{}", self.l1_icache3_data_mem_force_pd().bit()),
+                &self.l1_icache3_data_mem_force_pd(),
             )
             .field(
                 "l1_icache3_data_mem_force_pu",
-                &format_args!("{}", self.l1_icache3_data_mem_force_pu().bit()),
+                &self.l1_icache3_data_mem_force_pu(),
             )
             .field(
                 "l1_cache_data_mem_force_on",
-                &format_args!("{}", self.l1_cache_data_mem_force_on().bit()),
+                &self.l1_cache_data_mem_force_on(),
             )
             .field(
                 "l1_cache_data_mem_force_pd",
-                &format_args!("{}", self.l1_cache_data_mem_force_pd().bit()),
+                &self.l1_cache_data_mem_force_pd(),
             )
             .field(
                 "l1_cache_data_mem_force_pu",
-                &format_args!("{}", self.l1_cache_data_mem_force_pu().bit()),
+                &self.l1_cache_data_mem_force_pu(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_DATA_MEM_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16 - The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_debug_bus.rs b/esp32c6/src/extmem/l1_cache_debug_bus.rs
index 9f69176f5a..b26810050a 100644
--- a/esp32c6/src/extmem/l1_cache_debug_bus.rs
+++ b/esp32c6/src/extmem/l1_cache_debug_bus.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_DEBUG_BUS")
-            .field(
-                "l1_cache_debug_bus",
-                &format_args!("{}", self.l1_cache_debug_bus().bits()),
-            )
+            .field("l1_cache_debug_bus", &self.l1_cache_debug_bus())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_DEBUG_BUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_freeze_ctrl.rs b/esp32c6/src/extmem/l1_cache_freeze_ctrl.rs
index 1fd350c5f2..563c1461a8 100644
--- a/esp32c6/src/extmem/l1_cache_freeze_ctrl.rs
+++ b/esp32c6/src/extmem/l1_cache_freeze_ctrl.rs
@@ -117,75 +117,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_FREEZE_CTRL")
-            .field(
-                "l1_icache0_freeze_en",
-                &format_args!("{}", self.l1_icache0_freeze_en().bit()),
-            )
-            .field(
-                "l1_icache0_freeze_mode",
-                &format_args!("{}", self.l1_icache0_freeze_mode().bit()),
-            )
-            .field(
-                "l1_icache0_freeze_done",
-                &format_args!("{}", self.l1_icache0_freeze_done().bit()),
-            )
-            .field(
-                "l1_icache1_freeze_en",
-                &format_args!("{}", self.l1_icache1_freeze_en().bit()),
-            )
-            .field(
-                "l1_icache1_freeze_mode",
-                &format_args!("{}", self.l1_icache1_freeze_mode().bit()),
-            )
-            .field(
-                "l1_icache1_freeze_done",
-                &format_args!("{}", self.l1_icache1_freeze_done().bit()),
-            )
-            .field(
-                "l1_icache2_freeze_en",
-                &format_args!("{}", self.l1_icache2_freeze_en().bit()),
-            )
-            .field(
-                "l1_icache2_freeze_mode",
-                &format_args!("{}", self.l1_icache2_freeze_mode().bit()),
-            )
-            .field(
-                "l1_icache2_freeze_done",
-                &format_args!("{}", self.l1_icache2_freeze_done().bit()),
-            )
-            .field(
-                "l1_icache3_freeze_en",
-                &format_args!("{}", self.l1_icache3_freeze_en().bit()),
-            )
-            .field(
-                "l1_icache3_freeze_mode",
-                &format_args!("{}", self.l1_icache3_freeze_mode().bit()),
-            )
-            .field(
-                "l1_icache3_freeze_done",
-                &format_args!("{}", self.l1_icache3_freeze_done().bit()),
-            )
-            .field(
-                "l1_cache_freeze_en",
-                &format_args!("{}", self.l1_cache_freeze_en().bit()),
-            )
-            .field(
-                "l1_cache_freeze_mode",
-                &format_args!("{}", self.l1_cache_freeze_mode().bit()),
-            )
-            .field(
-                "l1_cache_freeze_done",
-                &format_args!("{}", self.l1_cache_freeze_done().bit()),
-            )
+            .field("l1_icache0_freeze_en", &self.l1_icache0_freeze_en())
+            .field("l1_icache0_freeze_mode", &self.l1_icache0_freeze_mode())
+            .field("l1_icache0_freeze_done", &self.l1_icache0_freeze_done())
+            .field("l1_icache1_freeze_en", &self.l1_icache1_freeze_en())
+            .field("l1_icache1_freeze_mode", &self.l1_icache1_freeze_mode())
+            .field("l1_icache1_freeze_done", &self.l1_icache1_freeze_done())
+            .field("l1_icache2_freeze_en", &self.l1_icache2_freeze_en())
+            .field("l1_icache2_freeze_mode", &self.l1_icache2_freeze_mode())
+            .field("l1_icache2_freeze_done", &self.l1_icache2_freeze_done())
+            .field("l1_icache3_freeze_en", &self.l1_icache3_freeze_en())
+            .field("l1_icache3_freeze_mode", &self.l1_icache3_freeze_mode())
+            .field("l1_icache3_freeze_done", &self.l1_icache3_freeze_done())
+            .field("l1_cache_freeze_en", &self.l1_cache_freeze_en())
+            .field("l1_cache_freeze_mode", &self.l1_cache_freeze_mode())
+            .field("l1_cache_freeze_done", &self.l1_cache_freeze_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_FREEZE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16 - The bit is used to enable freeze operation on L1-Cache. It can be cleared by software."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_object_ctrl.rs b/esp32c6/src/extmem/l1_cache_object_ctrl.rs
index f78b15a7d9..4b6c03c09d 100644
--- a/esp32c6/src/extmem/l1_cache_object_ctrl.rs
+++ b/esp32c6/src/extmem/l1_cache_object_ctrl.rs
@@ -82,55 +82,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_OBJECT_CTRL")
-            .field(
-                "l1_icache0_tag_object",
-                &format_args!("{}", self.l1_icache0_tag_object().bit()),
-            )
-            .field(
-                "l1_icache1_tag_object",
-                &format_args!("{}", self.l1_icache1_tag_object().bit()),
-            )
-            .field(
-                "l1_icache2_tag_object",
-                &format_args!("{}", self.l1_icache2_tag_object().bit()),
-            )
-            .field(
-                "l1_icache3_tag_object",
-                &format_args!("{}", self.l1_icache3_tag_object().bit()),
-            )
-            .field(
-                "l1_cache_tag_object",
-                &format_args!("{}", self.l1_cache_tag_object().bit()),
-            )
-            .field(
-                "l1_icache0_mem_object",
-                &format_args!("{}", self.l1_icache0_mem_object().bit()),
-            )
-            .field(
-                "l1_icache1_mem_object",
-                &format_args!("{}", self.l1_icache1_mem_object().bit()),
-            )
-            .field(
-                "l1_icache2_mem_object",
-                &format_args!("{}", self.l1_icache2_mem_object().bit()),
-            )
-            .field(
-                "l1_icache3_mem_object",
-                &format_args!("{}", self.l1_icache3_mem_object().bit()),
-            )
-            .field(
-                "l1_cache_mem_object",
-                &format_args!("{}", self.l1_cache_mem_object().bit()),
-            )
+            .field("l1_icache0_tag_object", &self.l1_icache0_tag_object())
+            .field("l1_icache1_tag_object", &self.l1_icache1_tag_object())
+            .field("l1_icache2_tag_object", &self.l1_icache2_tag_object())
+            .field("l1_icache3_tag_object", &self.l1_icache3_tag_object())
+            .field("l1_cache_tag_object", &self.l1_cache_tag_object())
+            .field("l1_icache0_mem_object", &self.l1_icache0_mem_object())
+            .field("l1_icache1_mem_object", &self.l1_icache1_mem_object())
+            .field("l1_icache2_mem_object", &self.l1_icache2_mem_object())
+            .field("l1_icache3_mem_object", &self.l1_icache3_mem_object())
+            .field("l1_cache_mem_object", &self.l1_cache_mem_object())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_OBJECT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - Set this bit to set L1-Cache tag memory as object. This bit should be onehot with the others fields inside this register."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_preload_ctrl.rs b/esp32c6/src/extmem/l1_cache_preload_ctrl.rs
index 2b163ffc06..2618bd9d09 100644
--- a/esp32c6/src/extmem/l1_cache_preload_ctrl.rs
+++ b/esp32c6/src/extmem/l1_cache_preload_ctrl.rs
@@ -40,31 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_PRELOAD_CTRL")
-            .field(
-                "l1_cache_preload_ena",
-                &format_args!("{}", self.l1_cache_preload_ena().bit()),
-            )
-            .field(
-                "l1_cache_preload_done",
-                &format_args!("{}", self.l1_cache_preload_done().bit()),
-            )
-            .field(
-                "l1_cache_preload_order",
-                &format_args!("{}", self.l1_cache_preload_order().bit()),
-            )
-            .field(
-                "l1_cache_preload_rgid",
-                &format_args!("{}", self.l1_cache_preload_rgid().bits()),
-            )
+            .field("l1_cache_preload_ena", &self.l1_cache_preload_ena())
+            .field("l1_cache_preload_done", &self.l1_cache_preload_done())
+            .field("l1_cache_preload_order", &self.l1_cache_preload_order())
+            .field("l1_cache_preload_rgid", &self.l1_cache_preload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_PRELOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable preload operation on L1-Cache. It will be cleared by hardware automatically after preload operation is done."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_preload_rst_ctrl.rs b/esp32c6/src/extmem/l1_cache_preload_rst_ctrl.rs
index f45ed1a9ad..361715dfde 100644
--- a/esp32c6/src/extmem/l1_cache_preload_rst_ctrl.rs
+++ b/esp32c6/src/extmem/l1_cache_preload_rst_ctrl.rs
@@ -45,35 +45,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_PRELOAD_RST_CTRL")
-            .field(
-                "l1_icache0_pld_rst",
-                &format_args!("{}", self.l1_icache0_pld_rst().bit()),
-            )
-            .field(
-                "l1_icache1_pld_rst",
-                &format_args!("{}", self.l1_icache1_pld_rst().bit()),
-            )
-            .field(
-                "l1_icache2_pld_rst",
-                &format_args!("{}", self.l1_icache2_pld_rst().bit()),
-            )
-            .field(
-                "l1_icache3_pld_rst",
-                &format_args!("{}", self.l1_icache3_pld_rst().bit()),
-            )
-            .field(
-                "l1_cache_pld_rst",
-                &format_args!("{}", self.l1_cache_pld_rst().bit()),
-            )
+            .field("l1_icache0_pld_rst", &self.l1_icache0_pld_rst())
+            .field("l1_icache1_pld_rst", &self.l1_icache1_pld_rst())
+            .field("l1_icache2_pld_rst", &self.l1_icache2_pld_rst())
+            .field("l1_icache3_pld_rst", &self.l1_icache3_pld_rst())
+            .field("l1_cache_pld_rst", &self.l1_cache_pld_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_PRELOAD_RST_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - set this bit to reset preload-logic inside L1-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_prelock_conf.rs b/esp32c6/src/extmem/l1_cache_prelock_conf.rs
index c30934a064..66065f2968 100644
--- a/esp32c6/src/extmem/l1_cache_prelock_conf.rs
+++ b/esp32c6/src/extmem/l1_cache_prelock_conf.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_PRELOCK_CONF")
-            .field(
-                "l1_cache_prelock_sct0_en",
-                &format_args!("{}", self.l1_cache_prelock_sct0_en().bit()),
-            )
-            .field(
-                "l1_cache_prelock_sct1_en",
-                &format_args!("{}", self.l1_cache_prelock_sct1_en().bit()),
-            )
-            .field(
-                "l1_cache_prelock_rgid",
-                &format_args!("{}", self.l1_cache_prelock_rgid().bits()),
-            )
+            .field("l1_cache_prelock_sct0_en", &self.l1_cache_prelock_sct0_en())
+            .field("l1_cache_prelock_sct1_en", &self.l1_cache_prelock_sct1_en())
+            .field("l1_cache_prelock_rgid", &self.l1_cache_prelock_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_PRELOCK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable the first section of prelock function on L1-Cache."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_prelock_sct0_addr.rs b/esp32c6/src/extmem/l1_cache_prelock_sct0_addr.rs
index 91a91b9965..19fe353e6c 100644
--- a/esp32c6/src/extmem/l1_cache_prelock_sct0_addr.rs
+++ b/esp32c6/src/extmem/l1_cache_prelock_sct0_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_PRELOCK_SCT0_ADDR")
             .field(
                 "l1_cache_prelock_sct0_addr",
-                &format_args!("{}", self.l1_cache_prelock_sct0_addr().bits()),
+                &self.l1_cache_prelock_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_PRELOCK_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_sync_preload_exception.rs b/esp32c6/src/extmem/l1_cache_sync_preload_exception.rs
index 609fcc4b6f..91c5b6fcc3 100644
--- a/esp32c6/src/extmem/l1_cache_sync_preload_exception.rs
+++ b/esp32c6/src/extmem/l1_cache_sync_preload_exception.rs
@@ -48,39 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_SYNC_PRELOAD_EXCEPTION")
-            .field(
-                "l1_icache0_pld_err_code",
-                &format_args!("{}", self.l1_icache0_pld_err_code().bits()),
-            )
-            .field(
-                "l1_icache1_pld_err_code",
-                &format_args!("{}", self.l1_icache1_pld_err_code().bits()),
-            )
-            .field(
-                "l1_icache2_pld_err_code",
-                &format_args!("{}", self.l1_icache2_pld_err_code().bits()),
-            )
-            .field(
-                "l1_icache3_pld_err_code",
-                &format_args!("{}", self.l1_icache3_pld_err_code().bits()),
-            )
-            .field(
-                "l1_cache_pld_err_code",
-                &format_args!("{}", self.l1_cache_pld_err_code().bits()),
-            )
-            .field(
-                "cache_sync_err_code",
-                &format_args!("{}", self.cache_sync_err_code().bits()),
-            )
+            .field("l1_icache0_pld_err_code", &self.l1_icache0_pld_err_code())
+            .field("l1_icache1_pld_err_code", &self.l1_icache1_pld_err_code())
+            .field("l1_icache2_pld_err_code", &self.l1_icache2_pld_err_code())
+            .field("l1_icache3_pld_err_code", &self.l1_icache3_pld_err_code())
+            .field("l1_cache_pld_err_code", &self.l1_cache_pld_err_code())
+            .field("cache_sync_err_code", &self.cache_sync_err_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Sync/Preload Operation exception register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_sync_preload_exception::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC;
 impl crate::RegisterSpec for L1_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC {
diff --git a/esp32c6/src/extmem/l1_cache_sync_preload_int_clr.rs b/esp32c6/src/extmem/l1_cache_sync_preload_int_clr.rs
index c9b89f234a..6f636130cf 100644
--- a/esp32c6/src/extmem/l1_cache_sync_preload_int_clr.rs
+++ b/esp32c6/src/extmem/l1_cache_sync_preload_int_clr.rs
@@ -74,45 +74,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_SYNC_PRELOAD_INT_CLR")
             .field(
                 "l1_icache0_pld_done_int_clr",
-                &format_args!("{}", self.l1_icache0_pld_done_int_clr().bit()),
+                &self.l1_icache0_pld_done_int_clr(),
             )
             .field(
                 "l1_icache1_pld_done_int_clr",
-                &format_args!("{}", self.l1_icache1_pld_done_int_clr().bit()),
+                &self.l1_icache1_pld_done_int_clr(),
             )
             .field(
                 "l1_icache2_pld_done_int_clr",
-                &format_args!("{}", self.l1_icache2_pld_done_int_clr().bit()),
+                &self.l1_icache2_pld_done_int_clr(),
             )
             .field(
                 "l1_icache3_pld_done_int_clr",
-                &format_args!("{}", self.l1_icache3_pld_done_int_clr().bit()),
+                &self.l1_icache3_pld_done_int_clr(),
             )
             .field(
                 "l1_icache0_pld_err_int_clr",
-                &format_args!("{}", self.l1_icache0_pld_err_int_clr().bit()),
+                &self.l1_icache0_pld_err_int_clr(),
             )
             .field(
                 "l1_icache1_pld_err_int_clr",
-                &format_args!("{}", self.l1_icache1_pld_err_int_clr().bit()),
+                &self.l1_icache1_pld_err_int_clr(),
             )
             .field(
                 "l1_icache2_pld_err_int_clr",
-                &format_args!("{}", self.l1_icache2_pld_err_int_clr().bit()),
+                &self.l1_icache2_pld_err_int_clr(),
             )
             .field(
                 "l1_icache3_pld_err_int_clr",
-                &format_args!("{}", self.l1_icache3_pld_err_int_clr().bit()),
+                &self.l1_icache3_pld_err_int_clr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_SYNC_PRELOAD_INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - The bit is used to clear interrupt that occurs only when L1-Cache preload-operation is done."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_sync_preload_int_ena.rs b/esp32c6/src/extmem/l1_cache_sync_preload_int_ena.rs
index 023ed07c5f..93778f1cae 100644
--- a/esp32c6/src/extmem/l1_cache_sync_preload_int_ena.rs
+++ b/esp32c6/src/extmem/l1_cache_sync_preload_int_ena.rs
@@ -102,61 +102,46 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_SYNC_PRELOAD_INT_ENA")
             .field(
                 "l1_icache0_pld_done_int_ena",
-                &format_args!("{}", self.l1_icache0_pld_done_int_ena().bit()),
+                &self.l1_icache0_pld_done_int_ena(),
             )
             .field(
                 "l1_icache1_pld_done_int_ena",
-                &format_args!("{}", self.l1_icache1_pld_done_int_ena().bit()),
+                &self.l1_icache1_pld_done_int_ena(),
             )
             .field(
                 "l1_icache2_pld_done_int_ena",
-                &format_args!("{}", self.l1_icache2_pld_done_int_ena().bit()),
+                &self.l1_icache2_pld_done_int_ena(),
             )
             .field(
                 "l1_icache3_pld_done_int_ena",
-                &format_args!("{}", self.l1_icache3_pld_done_int_ena().bit()),
+                &self.l1_icache3_pld_done_int_ena(),
             )
             .field(
                 "l1_cache_pld_done_int_ena",
-                &format_args!("{}", self.l1_cache_pld_done_int_ena().bit()),
-            )
-            .field(
-                "cache_sync_done_int_ena",
-                &format_args!("{}", self.cache_sync_done_int_ena().bit()),
+                &self.l1_cache_pld_done_int_ena(),
             )
+            .field("cache_sync_done_int_ena", &self.cache_sync_done_int_ena())
             .field(
                 "l1_icache0_pld_err_int_ena",
-                &format_args!("{}", self.l1_icache0_pld_err_int_ena().bit()),
+                &self.l1_icache0_pld_err_int_ena(),
             )
             .field(
                 "l1_icache1_pld_err_int_ena",
-                &format_args!("{}", self.l1_icache1_pld_err_int_ena().bit()),
+                &self.l1_icache1_pld_err_int_ena(),
             )
             .field(
                 "l1_icache2_pld_err_int_ena",
-                &format_args!("{}", self.l1_icache2_pld_err_int_ena().bit()),
+                &self.l1_icache2_pld_err_int_ena(),
             )
             .field(
                 "l1_icache3_pld_err_int_ena",
-                &format_args!("{}", self.l1_icache3_pld_err_int_ena().bit()),
-            )
-            .field(
-                "l1_cache_pld_err_int_ena",
-                &format_args!("{}", self.l1_cache_pld_err_int_ena().bit()),
-            )
-            .field(
-                "cache_sync_err_int_ena",
-                &format_args!("{}", self.cache_sync_err_int_ena().bit()),
+                &self.l1_icache3_pld_err_int_ena(),
             )
+            .field("l1_cache_pld_err_int_ena", &self.l1_cache_pld_err_int_ena())
+            .field("cache_sync_err_int_ena", &self.cache_sync_err_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_SYNC_PRELOAD_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - The bit is used to enable interrupt of L1-Cache preload-operation. If preload operation is done, interrupt occurs."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_sync_preload_int_raw.rs b/esp32c6/src/extmem/l1_cache_sync_preload_int_raw.rs
index e4b6867a28..897be8e62c 100644
--- a/esp32c6/src/extmem/l1_cache_sync_preload_int_raw.rs
+++ b/esp32c6/src/extmem/l1_cache_sync_preload_int_raw.rs
@@ -118,61 +118,46 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_SYNC_PRELOAD_INT_RAW")
             .field(
                 "l1_icache0_pld_done_int_raw",
-                &format_args!("{}", self.l1_icache0_pld_done_int_raw().bit()),
+                &self.l1_icache0_pld_done_int_raw(),
             )
             .field(
                 "l1_icache1_pld_done_int_raw",
-                &format_args!("{}", self.l1_icache1_pld_done_int_raw().bit()),
+                &self.l1_icache1_pld_done_int_raw(),
             )
             .field(
                 "l1_icache2_pld_done_int_raw",
-                &format_args!("{}", self.l1_icache2_pld_done_int_raw().bit()),
+                &self.l1_icache2_pld_done_int_raw(),
             )
             .field(
                 "l1_icache3_pld_done_int_raw",
-                &format_args!("{}", self.l1_icache3_pld_done_int_raw().bit()),
+                &self.l1_icache3_pld_done_int_raw(),
             )
             .field(
                 "l1_cache_pld_done_int_raw",
-                &format_args!("{}", self.l1_cache_pld_done_int_raw().bit()),
-            )
-            .field(
-                "cache_sync_done_int_raw",
-                &format_args!("{}", self.cache_sync_done_int_raw().bit()),
+                &self.l1_cache_pld_done_int_raw(),
             )
+            .field("cache_sync_done_int_raw", &self.cache_sync_done_int_raw())
             .field(
                 "l1_icache0_pld_err_int_raw",
-                &format_args!("{}", self.l1_icache0_pld_err_int_raw().bit()),
+                &self.l1_icache0_pld_err_int_raw(),
             )
             .field(
                 "l1_icache1_pld_err_int_raw",
-                &format_args!("{}", self.l1_icache1_pld_err_int_raw().bit()),
+                &self.l1_icache1_pld_err_int_raw(),
             )
             .field(
                 "l1_icache2_pld_err_int_raw",
-                &format_args!("{}", self.l1_icache2_pld_err_int_raw().bit()),
+                &self.l1_icache2_pld_err_int_raw(),
             )
             .field(
                 "l1_icache3_pld_err_int_raw",
-                &format_args!("{}", self.l1_icache3_pld_err_int_raw().bit()),
-            )
-            .field(
-                "l1_cache_pld_err_int_raw",
-                &format_args!("{}", self.l1_cache_pld_err_int_raw().bit()),
-            )
-            .field(
-                "cache_sync_err_int_raw",
-                &format_args!("{}", self.cache_sync_err_int_raw().bit()),
+                &self.l1_icache3_pld_err_int_raw(),
             )
+            .field("l1_cache_pld_err_int_raw", &self.l1_cache_pld_err_int_raw())
+            .field("cache_sync_err_int_raw", &self.cache_sync_err_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_SYNC_PRELOAD_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_sync_preload_int_st.rs b/esp32c6/src/extmem/l1_cache_sync_preload_int_st.rs
index 8fb98c4459..a22d29e2ae 100644
--- a/esp32c6/src/extmem/l1_cache_sync_preload_int_st.rs
+++ b/esp32c6/src/extmem/l1_cache_sync_preload_int_st.rs
@@ -92,61 +92,43 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_SYNC_PRELOAD_INT_ST")
             .field(
                 "l1_icache0_pld_done_int_st",
-                &format_args!("{}", self.l1_icache0_pld_done_int_st().bit()),
+                &self.l1_icache0_pld_done_int_st(),
             )
             .field(
                 "l1_icache1_pld_done_int_st",
-                &format_args!("{}", self.l1_icache1_pld_done_int_st().bit()),
+                &self.l1_icache1_pld_done_int_st(),
             )
             .field(
                 "l1_icache2_pld_done_int_st",
-                &format_args!("{}", self.l1_icache2_pld_done_int_st().bit()),
+                &self.l1_icache2_pld_done_int_st(),
             )
             .field(
                 "l1_icache3_pld_done_int_st",
-                &format_args!("{}", self.l1_icache3_pld_done_int_st().bit()),
-            )
-            .field(
-                "l1_cache_pld_done_int_st",
-                &format_args!("{}", self.l1_cache_pld_done_int_st().bit()),
-            )
-            .field(
-                "cache_sync_done_int_st",
-                &format_args!("{}", self.cache_sync_done_int_st().bit()),
+                &self.l1_icache3_pld_done_int_st(),
             )
+            .field("l1_cache_pld_done_int_st", &self.l1_cache_pld_done_int_st())
+            .field("cache_sync_done_int_st", &self.cache_sync_done_int_st())
             .field(
                 "l1_icache0_pld_err_int_st",
-                &format_args!("{}", self.l1_icache0_pld_err_int_st().bit()),
+                &self.l1_icache0_pld_err_int_st(),
             )
             .field(
                 "l1_icache1_pld_err_int_st",
-                &format_args!("{}", self.l1_icache1_pld_err_int_st().bit()),
+                &self.l1_icache1_pld_err_int_st(),
             )
             .field(
                 "l1_icache2_pld_err_int_st",
-                &format_args!("{}", self.l1_icache2_pld_err_int_st().bit()),
+                &self.l1_icache2_pld_err_int_st(),
             )
             .field(
                 "l1_icache3_pld_err_int_st",
-                &format_args!("{}", self.l1_icache3_pld_err_int_st().bit()),
-            )
-            .field(
-                "l1_cache_pld_err_int_st",
-                &format_args!("{}", self.l1_cache_pld_err_int_st().bit()),
-            )
-            .field(
-                "cache_sync_err_int_st",
-                &format_args!("{}", self.cache_sync_err_int_st().bit()),
+                &self.l1_icache3_pld_err_int_st(),
             )
+            .field("l1_cache_pld_err_int_st", &self.l1_cache_pld_err_int_st())
+            .field("cache_sync_err_int_st", &self.cache_sync_err_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_SYNC_PRELOAD_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_sync_preload_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_CACHE_SYNC_PRELOAD_INT_ST_SPEC;
 impl crate::RegisterSpec for L1_CACHE_SYNC_PRELOAD_INT_ST_SPEC {
diff --git a/esp32c6/src/extmem/l1_cache_sync_rst_ctrl.rs b/esp32c6/src/extmem/l1_cache_sync_rst_ctrl.rs
index e6a9c27994..ea0302734f 100644
--- a/esp32c6/src/extmem/l1_cache_sync_rst_ctrl.rs
+++ b/esp32c6/src/extmem/l1_cache_sync_rst_ctrl.rs
@@ -45,35 +45,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_SYNC_RST_CTRL")
-            .field(
-                "l1_icache0_sync_rst",
-                &format_args!("{}", self.l1_icache0_sync_rst().bit()),
-            )
-            .field(
-                "l1_icache1_sync_rst",
-                &format_args!("{}", self.l1_icache1_sync_rst().bit()),
-            )
-            .field(
-                "l1_icache2_sync_rst",
-                &format_args!("{}", self.l1_icache2_sync_rst().bit()),
-            )
-            .field(
-                "l1_icache3_sync_rst",
-                &format_args!("{}", self.l1_icache3_sync_rst().bit()),
-            )
-            .field(
-                "l1_cache_sync_rst",
-                &format_args!("{}", self.l1_cache_sync_rst().bit()),
-            )
+            .field("l1_icache0_sync_rst", &self.l1_icache0_sync_rst())
+            .field("l1_icache1_sync_rst", &self.l1_icache1_sync_rst())
+            .field("l1_icache2_sync_rst", &self.l1_icache2_sync_rst())
+            .field("l1_icache3_sync_rst", &self.l1_icache3_sync_rst())
+            .field("l1_cache_sync_rst", &self.l1_cache_sync_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_SYNC_RST_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - set this bit to reset sync-logic inside L1-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_tag_mem_acs_conf.rs b/esp32c6/src/extmem/l1_cache_tag_mem_acs_conf.rs
index 3437f36a75..5daa7b33f6 100644
--- a/esp32c6/src/extmem/l1_cache_tag_mem_acs_conf.rs
+++ b/esp32c6/src/extmem/l1_cache_tag_mem_acs_conf.rs
@@ -82,55 +82,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_TAG_MEM_ACS_CONF")
-            .field(
-                "l1_icache0_tag_mem_rd_en",
-                &format_args!("{}", self.l1_icache0_tag_mem_rd_en().bit()),
-            )
-            .field(
-                "l1_icache0_tag_mem_wr_en",
-                &format_args!("{}", self.l1_icache0_tag_mem_wr_en().bit()),
-            )
-            .field(
-                "l1_icache1_tag_mem_rd_en",
-                &format_args!("{}", self.l1_icache1_tag_mem_rd_en().bit()),
-            )
-            .field(
-                "l1_icache1_tag_mem_wr_en",
-                &format_args!("{}", self.l1_icache1_tag_mem_wr_en().bit()),
-            )
-            .field(
-                "l1_icache2_tag_mem_rd_en",
-                &format_args!("{}", self.l1_icache2_tag_mem_rd_en().bit()),
-            )
-            .field(
-                "l1_icache2_tag_mem_wr_en",
-                &format_args!("{}", self.l1_icache2_tag_mem_wr_en().bit()),
-            )
-            .field(
-                "l1_icache3_tag_mem_rd_en",
-                &format_args!("{}", self.l1_icache3_tag_mem_rd_en().bit()),
-            )
-            .field(
-                "l1_icache3_tag_mem_wr_en",
-                &format_args!("{}", self.l1_icache3_tag_mem_wr_en().bit()),
-            )
-            .field(
-                "l1_cache_tag_mem_rd_en",
-                &format_args!("{}", self.l1_cache_tag_mem_rd_en().bit()),
-            )
-            .field(
-                "l1_cache_tag_mem_wr_en",
-                &format_args!("{}", self.l1_cache_tag_mem_wr_en().bit()),
-            )
+            .field("l1_icache0_tag_mem_rd_en", &self.l1_icache0_tag_mem_rd_en())
+            .field("l1_icache0_tag_mem_wr_en", &self.l1_icache0_tag_mem_wr_en())
+            .field("l1_icache1_tag_mem_rd_en", &self.l1_icache1_tag_mem_rd_en())
+            .field("l1_icache1_tag_mem_wr_en", &self.l1_icache1_tag_mem_wr_en())
+            .field("l1_icache2_tag_mem_rd_en", &self.l1_icache2_tag_mem_rd_en())
+            .field("l1_icache2_tag_mem_wr_en", &self.l1_icache2_tag_mem_wr_en())
+            .field("l1_icache3_tag_mem_rd_en", &self.l1_icache3_tag_mem_rd_en())
+            .field("l1_icache3_tag_mem_wr_en", &self.l1_icache3_tag_mem_wr_en())
+            .field("l1_cache_tag_mem_rd_en", &self.l1_cache_tag_mem_rd_en())
+            .field("l1_cache_tag_mem_wr_en", &self.l1_cache_tag_mem_wr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_TAG_MEM_ACS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16 - The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: enable."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_tag_mem_power_ctrl.rs b/esp32c6/src/extmem/l1_cache_tag_mem_power_ctrl.rs
index 4d1d0074bf..b155a98506 100644
--- a/esp32c6/src/extmem/l1_cache_tag_mem_power_ctrl.rs
+++ b/esp32c6/src/extmem/l1_cache_tag_mem_power_ctrl.rs
@@ -121,73 +121,67 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_TAG_MEM_POWER_CTRL")
             .field(
                 "l1_icache0_tag_mem_force_on",
-                &format_args!("{}", self.l1_icache0_tag_mem_force_on().bit()),
+                &self.l1_icache0_tag_mem_force_on(),
             )
             .field(
                 "l1_icache0_tag_mem_force_pd",
-                &format_args!("{}", self.l1_icache0_tag_mem_force_pd().bit()),
+                &self.l1_icache0_tag_mem_force_pd(),
             )
             .field(
                 "l1_icache0_tag_mem_force_pu",
-                &format_args!("{}", self.l1_icache0_tag_mem_force_pu().bit()),
+                &self.l1_icache0_tag_mem_force_pu(),
             )
             .field(
                 "l1_icache1_tag_mem_force_on",
-                &format_args!("{}", self.l1_icache1_tag_mem_force_on().bit()),
+                &self.l1_icache1_tag_mem_force_on(),
             )
             .field(
                 "l1_icache1_tag_mem_force_pd",
-                &format_args!("{}", self.l1_icache1_tag_mem_force_pd().bit()),
+                &self.l1_icache1_tag_mem_force_pd(),
             )
             .field(
                 "l1_icache1_tag_mem_force_pu",
-                &format_args!("{}", self.l1_icache1_tag_mem_force_pu().bit()),
+                &self.l1_icache1_tag_mem_force_pu(),
             )
             .field(
                 "l1_icache2_tag_mem_force_on",
-                &format_args!("{}", self.l1_icache2_tag_mem_force_on().bit()),
+                &self.l1_icache2_tag_mem_force_on(),
             )
             .field(
                 "l1_icache2_tag_mem_force_pd",
-                &format_args!("{}", self.l1_icache2_tag_mem_force_pd().bit()),
+                &self.l1_icache2_tag_mem_force_pd(),
             )
             .field(
                 "l1_icache2_tag_mem_force_pu",
-                &format_args!("{}", self.l1_icache2_tag_mem_force_pu().bit()),
+                &self.l1_icache2_tag_mem_force_pu(),
             )
             .field(
                 "l1_icache3_tag_mem_force_on",
-                &format_args!("{}", self.l1_icache3_tag_mem_force_on().bit()),
+                &self.l1_icache3_tag_mem_force_on(),
             )
             .field(
                 "l1_icache3_tag_mem_force_pd",
-                &format_args!("{}", self.l1_icache3_tag_mem_force_pd().bit()),
+                &self.l1_icache3_tag_mem_force_pd(),
             )
             .field(
                 "l1_icache3_tag_mem_force_pu",
-                &format_args!("{}", self.l1_icache3_tag_mem_force_pu().bit()),
+                &self.l1_icache3_tag_mem_force_pu(),
             )
             .field(
                 "l1_cache_tag_mem_force_on",
-                &format_args!("{}", self.l1_cache_tag_mem_force_on().bit()),
+                &self.l1_cache_tag_mem_force_on(),
             )
             .field(
                 "l1_cache_tag_mem_force_pd",
-                &format_args!("{}", self.l1_cache_tag_mem_force_pd().bit()),
+                &self.l1_cache_tag_mem_force_pd(),
             )
             .field(
                 "l1_cache_tag_mem_force_pu",
-                &format_args!("{}", self.l1_cache_tag_mem_force_pu().bit()),
+                &self.l1_cache_tag_mem_force_pu(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_TAG_MEM_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16 - The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_vaddr.rs b/esp32c6/src/extmem/l1_cache_vaddr.rs
index 2321a99217..d362a76b45 100644
--- a/esp32c6/src/extmem/l1_cache_vaddr.rs
+++ b/esp32c6/src/extmem/l1_cache_vaddr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_VADDR")
-            .field(
-                "l1_cache_vaddr",
-                &format_args!("{}", self.l1_cache_vaddr().bits()),
-            )
+            .field("l1_cache_vaddr", &self.l1_cache_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_way_object.rs b/esp32c6/src/extmem/l1_cache_way_object.rs
index ab7140af30..74f4f759ca 100644
--- a/esp32c6/src/extmem/l1_cache_way_object.rs
+++ b/esp32c6/src/extmem/l1_cache_way_object.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_WAY_OBJECT")
-            .field(
-                "l1_cache_way_object",
-                &format_args!("{}", self.l1_cache_way_object().bits()),
-            )
+            .field("l1_cache_way_object", &self.l1_cache_way_object())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_WAY_OBJECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_cache_wrap_around_ctrl.rs b/esp32c6/src/extmem/l1_cache_wrap_around_ctrl.rs
index 74fc9910c8..545611ac37 100644
--- a/esp32c6/src/extmem/l1_cache_wrap_around_ctrl.rs
+++ b/esp32c6/src/extmem/l1_cache_wrap_around_ctrl.rs
@@ -45,35 +45,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_WRAP_AROUND_CTRL")
-            .field(
-                "l1_icache0_wrap",
-                &format_args!("{}", self.l1_icache0_wrap().bit()),
-            )
-            .field(
-                "l1_icache1_wrap",
-                &format_args!("{}", self.l1_icache1_wrap().bit()),
-            )
-            .field(
-                "l1_icache2_wrap",
-                &format_args!("{}", self.l1_icache2_wrap().bit()),
-            )
-            .field(
-                "l1_icache3_wrap",
-                &format_args!("{}", self.l1_icache3_wrap().bit()),
-            )
-            .field(
-                "l1_cache_wrap",
-                &format_args!("{}", self.l1_cache_wrap().bit()),
-            )
+            .field("l1_icache0_wrap", &self.l1_icache0_wrap())
+            .field("l1_icache1_wrap", &self.l1_icache1_wrap())
+            .field("l1_icache2_wrap", &self.l1_icache2_wrap())
+            .field("l1_icache3_wrap", &self.l1_icache3_wrap())
+            .field("l1_cache_wrap", &self.l1_cache_wrap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_WRAP_AROUND_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - Set this bit as 1 to enable L1-DCache wrap around mode."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_dbus2_acs_conflict_cnt.rs b/esp32c6/src/extmem/l1_dbus2_acs_conflict_cnt.rs
index ae4033a778..a3f4c8c9b5 100644
--- a/esp32c6/src/extmem/l1_dbus2_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l1_dbus2_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS2_ACS_CONFLICT_CNT")
-            .field(
-                "l1_dbus2_conflict_cnt",
-                &format_args!("{}", self.l1_dbus2_conflict_cnt().bits()),
-            )
+            .field("l1_dbus2_conflict_cnt", &self.l1_dbus2_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS2_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS2_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS2_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_dbus2_acs_hit_cnt.rs b/esp32c6/src/extmem/l1_dbus2_acs_hit_cnt.rs
index 5b523cf5f4..8eb631c5ce 100644
--- a/esp32c6/src/extmem/l1_dbus2_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l1_dbus2_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS2_ACS_HIT_CNT")
-            .field(
-                "l1_dbus2_hit_cnt",
-                &format_args!("{}", self.l1_dbus2_hit_cnt().bits()),
-            )
+            .field("l1_dbus2_hit_cnt", &self.l1_dbus2_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS2_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS2_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS2_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_dbus2_acs_miss_cnt.rs b/esp32c6/src/extmem/l1_dbus2_acs_miss_cnt.rs
index 39d1435858..adba0195f0 100644
--- a/esp32c6/src/extmem/l1_dbus2_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l1_dbus2_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS2_ACS_MISS_CNT")
-            .field(
-                "l1_dbus2_miss_cnt",
-                &format_args!("{}", self.l1_dbus2_miss_cnt().bits()),
-            )
+            .field("l1_dbus2_miss_cnt", &self.l1_dbus2_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS2_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS2_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS2_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_dbus2_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l1_dbus2_acs_nxtlvl_cnt.rs
index 7fa9ce93ed..eddcca1385 100644
--- a/esp32c6/src/extmem/l1_dbus2_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l1_dbus2_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS2_ACS_NXTLVL_CNT")
-            .field(
-                "l1_dbus2_nxtlvl_cnt",
-                &format_args!("{}", self.l1_dbus2_nxtlvl_cnt().bits()),
-            )
+            .field("l1_dbus2_nxtlvl_cnt", &self.l1_dbus2_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS2_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS2_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS2_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_dbus3_acs_conflict_cnt.rs b/esp32c6/src/extmem/l1_dbus3_acs_conflict_cnt.rs
index c4aa3941ef..27671e7815 100644
--- a/esp32c6/src/extmem/l1_dbus3_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l1_dbus3_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS3_ACS_CONFLICT_CNT")
-            .field(
-                "l1_dbus3_conflict_cnt",
-                &format_args!("{}", self.l1_dbus3_conflict_cnt().bits()),
-            )
+            .field("l1_dbus3_conflict_cnt", &self.l1_dbus3_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS3_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS3_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS3_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_dbus3_acs_hit_cnt.rs b/esp32c6/src/extmem/l1_dbus3_acs_hit_cnt.rs
index 00c237c9fe..5e27051463 100644
--- a/esp32c6/src/extmem/l1_dbus3_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l1_dbus3_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS3_ACS_HIT_CNT")
-            .field(
-                "l1_dbus3_hit_cnt",
-                &format_args!("{}", self.l1_dbus3_hit_cnt().bits()),
-            )
+            .field("l1_dbus3_hit_cnt", &self.l1_dbus3_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS3_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS3_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS3_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_dbus3_acs_miss_cnt.rs b/esp32c6/src/extmem/l1_dbus3_acs_miss_cnt.rs
index 7076ced3a0..dc66fc6166 100644
--- a/esp32c6/src/extmem/l1_dbus3_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l1_dbus3_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS3_ACS_MISS_CNT")
-            .field(
-                "l1_dbus3_miss_cnt",
-                &format_args!("{}", self.l1_dbus3_miss_cnt().bits()),
-            )
+            .field("l1_dbus3_miss_cnt", &self.l1_dbus3_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS3_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS3_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS3_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_dbus3_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l1_dbus3_acs_nxtlvl_cnt.rs
index 044cc659d9..ea6f2af08e 100644
--- a/esp32c6/src/extmem/l1_dbus3_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l1_dbus3_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS3_ACS_NXTLVL_CNT")
-            .field(
-                "l1_dbus3_nxtlvl_cnt",
-                &format_args!("{}", self.l1_dbus3_nxtlvl_cnt().bits()),
-            )
+            .field("l1_dbus3_nxtlvl_cnt", &self.l1_dbus3_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS3_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS3_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS3_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_dcache_acs_fail_addr.rs b/esp32c6/src/extmem/l1_dcache_acs_fail_addr.rs
index bf5d7c8ef7..41b122e926 100644
--- a/esp32c6/src/extmem/l1_dcache_acs_fail_addr.rs
+++ b/esp32c6/src/extmem/l1_dcache_acs_fail_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DCACHE_ACS_FAIL_ADDR")
-            .field(
-                "l1_cache_fail_addr",
-                &format_args!("{}", self.l1_cache_fail_addr().bits()),
-            )
+            .field("l1_cache_fail_addr", &self.l1_cache_fail_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_ACS_FAIL_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_acs_fail_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DCACHE_ACS_FAIL_ADDR_SPEC;
 impl crate::RegisterSpec for L1_DCACHE_ACS_FAIL_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_dcache_preload_addr.rs b/esp32c6/src/extmem/l1_dcache_preload_addr.rs
index 8d76713827..aed6b2d0fd 100644
--- a/esp32c6/src/extmem/l1_dcache_preload_addr.rs
+++ b/esp32c6/src/extmem/l1_dcache_preload_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DCACHE_PRELOAD_ADDR")
-            .field(
-                "l1_cache_preload_addr",
-                &format_args!("{}", self.l1_cache_preload_addr().bits()),
-            )
+            .field("l1_cache_preload_addr", &self.l1_cache_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L1-Cache, which should be used together with L1_CACHE_PRELOAD_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_dcache_preload_size.rs b/esp32c6/src/extmem/l1_dcache_preload_size.rs
index 2e9b5e6706..0775161c9f 100644
--- a/esp32c6/src/extmem/l1_dcache_preload_size.rs
+++ b/esp32c6/src/extmem/l1_dcache_preload_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DCACHE_PRELOAD_SIZE")
-            .field(
-                "l1_cache_preload_size",
-                &format_args!("{}", self.l1_cache_preload_size().bits()),
-            )
+            .field("l1_cache_preload_size", &self.l1_cache_preload_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_dcache_prelock_sct1_addr.rs b/esp32c6/src/extmem/l1_dcache_prelock_sct1_addr.rs
index b784133ced..2eff8719bf 100644
--- a/esp32c6/src/extmem/l1_dcache_prelock_sct1_addr.rs
+++ b/esp32c6/src/extmem/l1_dcache_prelock_sct1_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_DCACHE_PRELOCK_SCT1_ADDR")
             .field(
                 "l1_cache_prelock_sct1_addr",
-                &format_args!("{}", self.l1_cache_prelock_sct1_addr().bits()),
+                &self.l1_cache_prelock_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_PRELOCK_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_dcache_prelock_sct_size.rs b/esp32c6/src/extmem/l1_dcache_prelock_sct_size.rs
index b995e58a0d..6735be85d4 100644
--- a/esp32c6/src/extmem/l1_dcache_prelock_sct_size.rs
+++ b/esp32c6/src/extmem/l1_dcache_prelock_sct_size.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_DCACHE_PRELOCK_SCT_SIZE")
             .field(
                 "l1_cache_prelock_sct0_size",
-                &format_args!("{}", self.l1_cache_prelock_sct0_size().bits()),
+                &self.l1_cache_prelock_sct0_size(),
             )
             .field(
                 "l1_cache_prelock_sct1_size",
-                &format_args!("{}", self.l1_cache_prelock_sct1_size().bits()),
+                &self.l1_cache_prelock_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_PRELOCK_SCT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_ibus0_acs_conflict_cnt.rs b/esp32c6/src/extmem/l1_ibus0_acs_conflict_cnt.rs
index cdb8c10bf6..048cf9b9c6 100644
--- a/esp32c6/src/extmem/l1_ibus0_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus0_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS0_ACS_CONFLICT_CNT")
-            .field(
-                "l1_ibus0_conflict_cnt",
-                &format_args!("{}", self.l1_ibus0_conflict_cnt().bits()),
-            )
+            .field("l1_ibus0_conflict_cnt", &self.l1_ibus0_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS0_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS0_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS0_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_ibus0_acs_hit_cnt.rs b/esp32c6/src/extmem/l1_ibus0_acs_hit_cnt.rs
index c6e13acf60..975cb67efe 100644
--- a/esp32c6/src/extmem/l1_ibus0_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus0_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS0_ACS_HIT_CNT")
-            .field(
-                "l1_ibus0_hit_cnt",
-                &format_args!("{}", self.l1_ibus0_hit_cnt().bits()),
-            )
+            .field("l1_ibus0_hit_cnt", &self.l1_ibus0_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS0_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS0_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS0_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_ibus0_acs_miss_cnt.rs b/esp32c6/src/extmem/l1_ibus0_acs_miss_cnt.rs
index 136d269135..dd9fa0be9b 100644
--- a/esp32c6/src/extmem/l1_ibus0_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus0_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS0_ACS_MISS_CNT")
-            .field(
-                "l1_ibus0_miss_cnt",
-                &format_args!("{}", self.l1_ibus0_miss_cnt().bits()),
-            )
+            .field("l1_ibus0_miss_cnt", &self.l1_ibus0_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS0_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS0_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS0_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_ibus0_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l1_ibus0_acs_nxtlvl_cnt.rs
index e549c4787c..b889774ff7 100644
--- a/esp32c6/src/extmem/l1_ibus0_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus0_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS0_ACS_NXTLVL_CNT")
-            .field(
-                "l1_ibus0_nxtlvl_cnt",
-                &format_args!("{}", self.l1_ibus0_nxtlvl_cnt().bits()),
-            )
+            .field("l1_ibus0_nxtlvl_cnt", &self.l1_ibus0_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS0_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS0_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS0_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_ibus1_acs_conflict_cnt.rs b/esp32c6/src/extmem/l1_ibus1_acs_conflict_cnt.rs
index 11e192a441..c38bdeb92a 100644
--- a/esp32c6/src/extmem/l1_ibus1_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus1_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS1_ACS_CONFLICT_CNT")
-            .field(
-                "l1_ibus1_conflict_cnt",
-                &format_args!("{}", self.l1_ibus1_conflict_cnt().bits()),
-            )
+            .field("l1_ibus1_conflict_cnt", &self.l1_ibus1_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS1_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS1_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS1_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_ibus1_acs_hit_cnt.rs b/esp32c6/src/extmem/l1_ibus1_acs_hit_cnt.rs
index 843ad25984..9561601492 100644
--- a/esp32c6/src/extmem/l1_ibus1_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus1_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS1_ACS_HIT_CNT")
-            .field(
-                "l1_ibus1_hit_cnt",
-                &format_args!("{}", self.l1_ibus1_hit_cnt().bits()),
-            )
+            .field("l1_ibus1_hit_cnt", &self.l1_ibus1_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS1_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS1_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS1_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_ibus1_acs_miss_cnt.rs b/esp32c6/src/extmem/l1_ibus1_acs_miss_cnt.rs
index 443036644f..bca4e76059 100644
--- a/esp32c6/src/extmem/l1_ibus1_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus1_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS1_ACS_MISS_CNT")
-            .field(
-                "l1_ibus1_miss_cnt",
-                &format_args!("{}", self.l1_ibus1_miss_cnt().bits()),
-            )
+            .field("l1_ibus1_miss_cnt", &self.l1_ibus1_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS1_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS1_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS1_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_ibus1_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l1_ibus1_acs_nxtlvl_cnt.rs
index 413e84abec..8f139e4490 100644
--- a/esp32c6/src/extmem/l1_ibus1_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus1_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS1_ACS_NXTLVL_CNT")
-            .field(
-                "l1_ibus1_nxtlvl_cnt",
-                &format_args!("{}", self.l1_ibus1_nxtlvl_cnt().bits()),
-            )
+            .field("l1_ibus1_nxtlvl_cnt", &self.l1_ibus1_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS1_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS1_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS1_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_ibus2_acs_conflict_cnt.rs b/esp32c6/src/extmem/l1_ibus2_acs_conflict_cnt.rs
index 5cbb888ea1..341fed9f0b 100644
--- a/esp32c6/src/extmem/l1_ibus2_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus2_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS2_ACS_CONFLICT_CNT")
-            .field(
-                "l1_ibus2_conflict_cnt",
-                &format_args!("{}", self.l1_ibus2_conflict_cnt().bits()),
-            )
+            .field("l1_ibus2_conflict_cnt", &self.l1_ibus2_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS2_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS2_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS2_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_ibus2_acs_hit_cnt.rs b/esp32c6/src/extmem/l1_ibus2_acs_hit_cnt.rs
index 6461e705b6..2199318015 100644
--- a/esp32c6/src/extmem/l1_ibus2_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus2_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS2_ACS_HIT_CNT")
-            .field(
-                "l1_ibus2_hit_cnt",
-                &format_args!("{}", self.l1_ibus2_hit_cnt().bits()),
-            )
+            .field("l1_ibus2_hit_cnt", &self.l1_ibus2_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS2_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS2_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS2_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_ibus2_acs_miss_cnt.rs b/esp32c6/src/extmem/l1_ibus2_acs_miss_cnt.rs
index c697c8b065..9e9667f961 100644
--- a/esp32c6/src/extmem/l1_ibus2_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus2_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS2_ACS_MISS_CNT")
-            .field(
-                "l1_ibus2_miss_cnt",
-                &format_args!("{}", self.l1_ibus2_miss_cnt().bits()),
-            )
+            .field("l1_ibus2_miss_cnt", &self.l1_ibus2_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS2_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS2_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS2_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_ibus2_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l1_ibus2_acs_nxtlvl_cnt.rs
index 7ad7e4b5fb..ca661a0b29 100644
--- a/esp32c6/src/extmem/l1_ibus2_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus2_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS2_ACS_NXTLVL_CNT")
-            .field(
-                "l1_ibus2_nxtlvl_cnt",
-                &format_args!("{}", self.l1_ibus2_nxtlvl_cnt().bits()),
-            )
+            .field("l1_ibus2_nxtlvl_cnt", &self.l1_ibus2_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS2_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS2_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS2_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_ibus3_acs_conflict_cnt.rs b/esp32c6/src/extmem/l1_ibus3_acs_conflict_cnt.rs
index 4ba34f96cd..80e19e1cac 100644
--- a/esp32c6/src/extmem/l1_ibus3_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus3_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS3_ACS_CONFLICT_CNT")
-            .field(
-                "l1_ibus3_conflict_cnt",
-                &format_args!("{}", self.l1_ibus3_conflict_cnt().bits()),
-            )
+            .field("l1_ibus3_conflict_cnt", &self.l1_ibus3_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS3_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS3_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS3_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_ibus3_acs_hit_cnt.rs b/esp32c6/src/extmem/l1_ibus3_acs_hit_cnt.rs
index c5f1f42786..8d50fd89f9 100644
--- a/esp32c6/src/extmem/l1_ibus3_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus3_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS3_ACS_HIT_CNT")
-            .field(
-                "l1_ibus3_hit_cnt",
-                &format_args!("{}", self.l1_ibus3_hit_cnt().bits()),
-            )
+            .field("l1_ibus3_hit_cnt", &self.l1_ibus3_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS3_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS3_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS3_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_ibus3_acs_miss_cnt.rs b/esp32c6/src/extmem/l1_ibus3_acs_miss_cnt.rs
index 923ef006b8..d9cae2fdf3 100644
--- a/esp32c6/src/extmem/l1_ibus3_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus3_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS3_ACS_MISS_CNT")
-            .field(
-                "l1_ibus3_miss_cnt",
-                &format_args!("{}", self.l1_ibus3_miss_cnt().bits()),
-            )
+            .field("l1_ibus3_miss_cnt", &self.l1_ibus3_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS3_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS3_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS3_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_ibus3_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l1_ibus3_acs_nxtlvl_cnt.rs
index 547631fd68..963330d284 100644
--- a/esp32c6/src/extmem/l1_ibus3_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l1_ibus3_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS3_ACS_NXTLVL_CNT")
-            .field(
-                "l1_ibus3_nxtlvl_cnt",
-                &format_args!("{}", self.l1_ibus3_nxtlvl_cnt().bits()),
-            )
+            .field("l1_ibus3_nxtlvl_cnt", &self.l1_ibus3_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS3_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS3_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS3_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache0_acs_fail_addr.rs b/esp32c6/src/extmem/l1_icache0_acs_fail_addr.rs
index 9debe070ce..132d59b7c7 100644
--- a/esp32c6/src/extmem/l1_icache0_acs_fail_addr.rs
+++ b/esp32c6/src/extmem/l1_icache0_acs_fail_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE0_ACS_FAIL_ADDR")
-            .field(
-                "l1_icache0_fail_addr",
-                &format_args!("{}", self.l1_icache0_fail_addr().bits()),
-            )
+            .field("l1_icache0_fail_addr", &self.l1_icache0_fail_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_ACS_FAIL_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_acs_fail_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE0_ACS_FAIL_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE0_ACS_FAIL_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache0_acs_fail_id_attr.rs b/esp32c6/src/extmem/l1_icache0_acs_fail_id_attr.rs
index e77c05f059..11ff193c0d 100644
--- a/esp32c6/src/extmem/l1_icache0_acs_fail_id_attr.rs
+++ b/esp32c6/src/extmem/l1_icache0_acs_fail_id_attr.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE0_ACS_FAIL_ID_ATTR")
-            .field(
-                "l1_icache0_fail_id",
-                &format_args!("{}", self.l1_icache0_fail_id().bits()),
-            )
-            .field(
-                "l1_icache0_fail_attr",
-                &format_args!("{}", self.l1_icache0_fail_attr().bits()),
-            )
+            .field("l1_icache0_fail_id", &self.l1_icache0_fail_id())
+            .field("l1_icache0_fail_attr", &self.l1_icache0_fail_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_ACS_FAIL_ID_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_acs_fail_id_attr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE0_ACS_FAIL_ID_ATTR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE0_ACS_FAIL_ID_ATTR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache0_autoload_ctrl.rs b/esp32c6/src/extmem/l1_icache0_autoload_ctrl.rs
index de9cdd5fe1..b39a0560be 100644
--- a/esp32c6/src/extmem/l1_icache0_autoload_ctrl.rs
+++ b/esp32c6/src/extmem/l1_icache0_autoload_ctrl.rs
@@ -55,43 +55,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE0_AUTOLOAD_CTRL")
-            .field(
-                "l1_icache0_autoload_ena",
-                &format_args!("{}", self.l1_icache0_autoload_ena().bit()),
-            )
-            .field(
-                "l1_icache0_autoload_done",
-                &format_args!("{}", self.l1_icache0_autoload_done().bit()),
-            )
+            .field("l1_icache0_autoload_ena", &self.l1_icache0_autoload_ena())
+            .field("l1_icache0_autoload_done", &self.l1_icache0_autoload_done())
             .field(
                 "l1_icache0_autoload_order",
-                &format_args!("{}", self.l1_icache0_autoload_order().bit()),
+                &self.l1_icache0_autoload_order(),
             )
             .field(
                 "l1_icache0_autoload_trigger_mode",
-                &format_args!("{}", self.l1_icache0_autoload_trigger_mode().bits()),
+                &self.l1_icache0_autoload_trigger_mode(),
             )
             .field(
                 "l1_icache0_autoload_sct0_ena",
-                &format_args!("{}", self.l1_icache0_autoload_sct0_ena().bit()),
+                &self.l1_icache0_autoload_sct0_ena(),
             )
             .field(
                 "l1_icache0_autoload_sct1_ena",
-                &format_args!("{}", self.l1_icache0_autoload_sct1_ena().bit()),
-            )
-            .field(
-                "l1_icache0_autoload_rgid",
-                &format_args!("{}", self.l1_icache0_autoload_rgid().bits()),
+                &self.l1_icache0_autoload_sct1_ena(),
             )
+            .field("l1_icache0_autoload_rgid", &self.l1_icache0_autoload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_AUTOLOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 0 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE0_AUTOLOAD_CTRL_SPEC;
 impl crate::RegisterSpec for L1_ICACHE0_AUTOLOAD_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache0_autoload_sct0_addr.rs b/esp32c6/src/extmem/l1_icache0_autoload_sct0_addr.rs
index b464610abf..5cd2155909 100644
--- a/esp32c6/src/extmem/l1_icache0_autoload_sct0_addr.rs
+++ b/esp32c6/src/extmem/l1_icache0_autoload_sct0_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_AUTOLOAD_SCT0_ADDR")
             .field(
                 "l1_icache0_autoload_sct0_addr",
-                &format_args!("{}", self.l1_icache0_autoload_sct0_addr().bits()),
+                &self.l1_icache0_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_AUTOLOAD_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 0 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct0_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE0_AUTOLOAD_SCT0_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE0_AUTOLOAD_SCT0_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache0_autoload_sct0_size.rs b/esp32c6/src/extmem/l1_icache0_autoload_sct0_size.rs
index bcbced7fb6..16cef3b58d 100644
--- a/esp32c6/src/extmem/l1_icache0_autoload_sct0_size.rs
+++ b/esp32c6/src/extmem/l1_icache0_autoload_sct0_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_AUTOLOAD_SCT0_SIZE")
             .field(
                 "l1_icache0_autoload_sct0_size",
-                &format_args!("{}", self.l1_icache0_autoload_sct0_size().bits()),
+                &self.l1_icache0_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_AUTOLOAD_SCT0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 0 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct0_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE0_AUTOLOAD_SCT0_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE0_AUTOLOAD_SCT0_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache0_autoload_sct1_addr.rs b/esp32c6/src/extmem/l1_icache0_autoload_sct1_addr.rs
index e76ee12c26..cdf52da30c 100644
--- a/esp32c6/src/extmem/l1_icache0_autoload_sct1_addr.rs
+++ b/esp32c6/src/extmem/l1_icache0_autoload_sct1_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_AUTOLOAD_SCT1_ADDR")
             .field(
                 "l1_icache0_autoload_sct1_addr",
-                &format_args!("{}", self.l1_icache0_autoload_sct1_addr().bits()),
+                &self.l1_icache0_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_AUTOLOAD_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 0 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct1_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE0_AUTOLOAD_SCT1_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE0_AUTOLOAD_SCT1_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache0_autoload_sct1_size.rs b/esp32c6/src/extmem/l1_icache0_autoload_sct1_size.rs
index 70eaaed3b5..d3a1abca17 100644
--- a/esp32c6/src/extmem/l1_icache0_autoload_sct1_size.rs
+++ b/esp32c6/src/extmem/l1_icache0_autoload_sct1_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_AUTOLOAD_SCT1_SIZE")
             .field(
                 "l1_icache0_autoload_sct1_size",
-                &format_args!("{}", self.l1_icache0_autoload_sct1_size().bits()),
+                &self.l1_icache0_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_AUTOLOAD_SCT1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 0 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_autoload_sct1_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE0_AUTOLOAD_SCT1_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE0_AUTOLOAD_SCT1_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache0_preload_addr.rs b/esp32c6/src/extmem/l1_icache0_preload_addr.rs
index 6208911146..eb0493aff1 100644
--- a/esp32c6/src/extmem/l1_icache0_preload_addr.rs
+++ b/esp32c6/src/extmem/l1_icache0_preload_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE0_PRELOAD_ADDR")
-            .field(
-                "l1_icache0_preload_addr",
-                &format_args!("{}", self.l1_icache0_preload_addr().bits()),
-            )
+            .field("l1_icache0_preload_addr", &self.l1_icache0_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 0 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_preload_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE0_PRELOAD_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE0_PRELOAD_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache0_preload_ctrl.rs b/esp32c6/src/extmem/l1_icache0_preload_ctrl.rs
index 6cc0c4fa3a..f7351e3bec 100644
--- a/esp32c6/src/extmem/l1_icache0_preload_ctrl.rs
+++ b/esp32c6/src/extmem/l1_icache0_preload_ctrl.rs
@@ -38,31 +38,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE0_PRELOAD_CTRL")
-            .field(
-                "l1_icache0_preload_ena",
-                &format_args!("{}", self.l1_icache0_preload_ena().bit()),
-            )
-            .field(
-                "l1_icache0_preload_done",
-                &format_args!("{}", self.l1_icache0_preload_done().bit()),
-            )
-            .field(
-                "l1_icache0_preload_order",
-                &format_args!("{}", self.l1_icache0_preload_order().bit()),
-            )
-            .field(
-                "l1_icache0_preload_rgid",
-                &format_args!("{}", self.l1_icache0_preload_rgid().bits()),
-            )
+            .field("l1_icache0_preload_ena", &self.l1_icache0_preload_ena())
+            .field("l1_icache0_preload_done", &self.l1_icache0_preload_done())
+            .field("l1_icache0_preload_order", &self.l1_icache0_preload_order())
+            .field("l1_icache0_preload_rgid", &self.l1_icache0_preload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_PRELOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_icache0_preload_size.rs b/esp32c6/src/extmem/l1_icache0_preload_size.rs
index 78d6211816..5eb482e21c 100644
--- a/esp32c6/src/extmem/l1_icache0_preload_size.rs
+++ b/esp32c6/src/extmem/l1_icache0_preload_size.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE0_PRELOAD_SIZE")
-            .field(
-                "l1_icache0_preload_size",
-                &format_args!("{}", self.l1_icache0_preload_size().bits()),
-            )
+            .field("l1_icache0_preload_size", &self.l1_icache0_preload_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 0 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_preload_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE0_PRELOAD_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE0_PRELOAD_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache0_prelock_conf.rs b/esp32c6/src/extmem/l1_icache0_prelock_conf.rs
index e401c93367..6b6ed2b3c5 100644
--- a/esp32c6/src/extmem/l1_icache0_prelock_conf.rs
+++ b/esp32c6/src/extmem/l1_icache0_prelock_conf.rs
@@ -29,25 +29,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_PRELOCK_CONF")
             .field(
                 "l1_icache0_prelock_sct0_en",
-                &format_args!("{}", self.l1_icache0_prelock_sct0_en().bit()),
+                &self.l1_icache0_prelock_sct0_en(),
             )
             .field(
                 "l1_icache0_prelock_sct1_en",
-                &format_args!("{}", self.l1_icache0_prelock_sct1_en().bit()),
-            )
-            .field(
-                "l1_icache0_prelock_rgid",
-                &format_args!("{}", self.l1_icache0_prelock_rgid().bits()),
+                &self.l1_icache0_prelock_sct1_en(),
             )
+            .field("l1_icache0_prelock_rgid", &self.l1_icache0_prelock_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_PRELOCK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 0 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE0_PRELOCK_CONF_SPEC;
 impl crate::RegisterSpec for L1_ICACHE0_PRELOCK_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache0_prelock_sct0_addr.rs b/esp32c6/src/extmem/l1_icache0_prelock_sct0_addr.rs
index ad291a74df..97d6667b19 100644
--- a/esp32c6/src/extmem/l1_icache0_prelock_sct0_addr.rs
+++ b/esp32c6/src/extmem/l1_icache0_prelock_sct0_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_PRELOCK_SCT0_ADDR")
             .field(
                 "l1_icache0_prelock_sct0_addr",
-                &format_args!("{}", self.l1_icache0_prelock_sct0_addr().bits()),
+                &self.l1_icache0_prelock_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_PRELOCK_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 0 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_sct0_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE0_PRELOCK_SCT0_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE0_PRELOCK_SCT0_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache0_prelock_sct1_addr.rs b/esp32c6/src/extmem/l1_icache0_prelock_sct1_addr.rs
index 7afdda1e0f..978421744f 100644
--- a/esp32c6/src/extmem/l1_icache0_prelock_sct1_addr.rs
+++ b/esp32c6/src/extmem/l1_icache0_prelock_sct1_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_PRELOCK_SCT1_ADDR")
             .field(
                 "l1_icache0_prelock_sct1_addr",
-                &format_args!("{}", self.l1_icache0_prelock_sct1_addr().bits()),
+                &self.l1_icache0_prelock_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_PRELOCK_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 0 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_sct1_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE0_PRELOCK_SCT1_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE0_PRELOCK_SCT1_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache0_prelock_sct_size.rs b/esp32c6/src/extmem/l1_icache0_prelock_sct_size.rs
index 0e861eab87..32be3e0a2e 100644
--- a/esp32c6/src/extmem/l1_icache0_prelock_sct_size.rs
+++ b/esp32c6/src/extmem/l1_icache0_prelock_sct_size.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_PRELOCK_SCT_SIZE")
             .field(
                 "l1_icache0_prelock_sct0_size",
-                &format_args!("{}", self.l1_icache0_prelock_sct0_size().bits()),
+                &self.l1_icache0_prelock_sct0_size(),
             )
             .field(
                 "l1_icache0_prelock_sct1_size",
-                &format_args!("{}", self.l1_icache0_prelock_sct1_size().bits()),
+                &self.l1_icache0_prelock_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_PRELOCK_SCT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 0 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_prelock_sct_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE0_PRELOCK_SCT_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE0_PRELOCK_SCT_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache1_acs_fail_addr.rs b/esp32c6/src/extmem/l1_icache1_acs_fail_addr.rs
index 62b90876e6..63430ea03f 100644
--- a/esp32c6/src/extmem/l1_icache1_acs_fail_addr.rs
+++ b/esp32c6/src/extmem/l1_icache1_acs_fail_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE1_ACS_FAIL_ADDR")
-            .field(
-                "l1_icache1_fail_addr",
-                &format_args!("{}", self.l1_icache1_fail_addr().bits()),
-            )
+            .field("l1_icache1_fail_addr", &self.l1_icache1_fail_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_ACS_FAIL_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_acs_fail_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE1_ACS_FAIL_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE1_ACS_FAIL_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache1_acs_fail_id_attr.rs b/esp32c6/src/extmem/l1_icache1_acs_fail_id_attr.rs
index dc9f7aa925..2876240d70 100644
--- a/esp32c6/src/extmem/l1_icache1_acs_fail_id_attr.rs
+++ b/esp32c6/src/extmem/l1_icache1_acs_fail_id_attr.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE1_ACS_FAIL_ID_ATTR")
-            .field(
-                "l1_icache1_fail_id",
-                &format_args!("{}", self.l1_icache1_fail_id().bits()),
-            )
-            .field(
-                "l1_icache1_fail_attr",
-                &format_args!("{}", self.l1_icache1_fail_attr().bits()),
-            )
+            .field("l1_icache1_fail_id", &self.l1_icache1_fail_id())
+            .field("l1_icache1_fail_attr", &self.l1_icache1_fail_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_ACS_FAIL_ID_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_acs_fail_id_attr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE1_ACS_FAIL_ID_ATTR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE1_ACS_FAIL_ID_ATTR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache1_autoload_ctrl.rs b/esp32c6/src/extmem/l1_icache1_autoload_ctrl.rs
index db71f20b2b..a0e4af7c4e 100644
--- a/esp32c6/src/extmem/l1_icache1_autoload_ctrl.rs
+++ b/esp32c6/src/extmem/l1_icache1_autoload_ctrl.rs
@@ -55,43 +55,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE1_AUTOLOAD_CTRL")
-            .field(
-                "l1_icache1_autoload_ena",
-                &format_args!("{}", self.l1_icache1_autoload_ena().bit()),
-            )
-            .field(
-                "l1_icache1_autoload_done",
-                &format_args!("{}", self.l1_icache1_autoload_done().bit()),
-            )
+            .field("l1_icache1_autoload_ena", &self.l1_icache1_autoload_ena())
+            .field("l1_icache1_autoload_done", &self.l1_icache1_autoload_done())
             .field(
                 "l1_icache1_autoload_order",
-                &format_args!("{}", self.l1_icache1_autoload_order().bit()),
+                &self.l1_icache1_autoload_order(),
             )
             .field(
                 "l1_icache1_autoload_trigger_mode",
-                &format_args!("{}", self.l1_icache1_autoload_trigger_mode().bits()),
+                &self.l1_icache1_autoload_trigger_mode(),
             )
             .field(
                 "l1_icache1_autoload_sct0_ena",
-                &format_args!("{}", self.l1_icache1_autoload_sct0_ena().bit()),
+                &self.l1_icache1_autoload_sct0_ena(),
             )
             .field(
                 "l1_icache1_autoload_sct1_ena",
-                &format_args!("{}", self.l1_icache1_autoload_sct1_ena().bit()),
-            )
-            .field(
-                "l1_icache1_autoload_rgid",
-                &format_args!("{}", self.l1_icache1_autoload_rgid().bits()),
+                &self.l1_icache1_autoload_sct1_ena(),
             )
+            .field("l1_icache1_autoload_rgid", &self.l1_icache1_autoload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_AUTOLOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 1 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE1_AUTOLOAD_CTRL_SPEC;
 impl crate::RegisterSpec for L1_ICACHE1_AUTOLOAD_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache1_autoload_sct0_addr.rs b/esp32c6/src/extmem/l1_icache1_autoload_sct0_addr.rs
index 84ebff5dcb..3b80a0b863 100644
--- a/esp32c6/src/extmem/l1_icache1_autoload_sct0_addr.rs
+++ b/esp32c6/src/extmem/l1_icache1_autoload_sct0_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_AUTOLOAD_SCT0_ADDR")
             .field(
                 "l1_icache1_autoload_sct0_addr",
-                &format_args!("{}", self.l1_icache1_autoload_sct0_addr().bits()),
+                &self.l1_icache1_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_AUTOLOAD_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 1 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct0_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE1_AUTOLOAD_SCT0_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE1_AUTOLOAD_SCT0_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache1_autoload_sct0_size.rs b/esp32c6/src/extmem/l1_icache1_autoload_sct0_size.rs
index be5a96d846..8c5b0e6de3 100644
--- a/esp32c6/src/extmem/l1_icache1_autoload_sct0_size.rs
+++ b/esp32c6/src/extmem/l1_icache1_autoload_sct0_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_AUTOLOAD_SCT0_SIZE")
             .field(
                 "l1_icache1_autoload_sct0_size",
-                &format_args!("{}", self.l1_icache1_autoload_sct0_size().bits()),
+                &self.l1_icache1_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_AUTOLOAD_SCT0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 1 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct0_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE1_AUTOLOAD_SCT0_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE1_AUTOLOAD_SCT0_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache1_autoload_sct1_addr.rs b/esp32c6/src/extmem/l1_icache1_autoload_sct1_addr.rs
index 61a0420e06..5f40bb4bd3 100644
--- a/esp32c6/src/extmem/l1_icache1_autoload_sct1_addr.rs
+++ b/esp32c6/src/extmem/l1_icache1_autoload_sct1_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_AUTOLOAD_SCT1_ADDR")
             .field(
                 "l1_icache1_autoload_sct1_addr",
-                &format_args!("{}", self.l1_icache1_autoload_sct1_addr().bits()),
+                &self.l1_icache1_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_AUTOLOAD_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 1 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct1_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE1_AUTOLOAD_SCT1_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE1_AUTOLOAD_SCT1_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache1_autoload_sct1_size.rs b/esp32c6/src/extmem/l1_icache1_autoload_sct1_size.rs
index bbd03631ec..85929c820a 100644
--- a/esp32c6/src/extmem/l1_icache1_autoload_sct1_size.rs
+++ b/esp32c6/src/extmem/l1_icache1_autoload_sct1_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_AUTOLOAD_SCT1_SIZE")
             .field(
                 "l1_icache1_autoload_sct1_size",
-                &format_args!("{}", self.l1_icache1_autoload_sct1_size().bits()),
+                &self.l1_icache1_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_AUTOLOAD_SCT1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 1 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_autoload_sct1_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE1_AUTOLOAD_SCT1_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE1_AUTOLOAD_SCT1_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache1_preload_addr.rs b/esp32c6/src/extmem/l1_icache1_preload_addr.rs
index b9581684cb..c3b726b78a 100644
--- a/esp32c6/src/extmem/l1_icache1_preload_addr.rs
+++ b/esp32c6/src/extmem/l1_icache1_preload_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE1_PRELOAD_ADDR")
-            .field(
-                "l1_icache1_preload_addr",
-                &format_args!("{}", self.l1_icache1_preload_addr().bits()),
-            )
+            .field("l1_icache1_preload_addr", &self.l1_icache1_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 1 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_preload_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE1_PRELOAD_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE1_PRELOAD_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache1_preload_ctrl.rs b/esp32c6/src/extmem/l1_icache1_preload_ctrl.rs
index 8a14033373..6dd31b0964 100644
--- a/esp32c6/src/extmem/l1_icache1_preload_ctrl.rs
+++ b/esp32c6/src/extmem/l1_icache1_preload_ctrl.rs
@@ -38,31 +38,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE1_PRELOAD_CTRL")
-            .field(
-                "l1_icache1_preload_ena",
-                &format_args!("{}", self.l1_icache1_preload_ena().bit()),
-            )
-            .field(
-                "l1_icache1_preload_done",
-                &format_args!("{}", self.l1_icache1_preload_done().bit()),
-            )
-            .field(
-                "l1_icache1_preload_order",
-                &format_args!("{}", self.l1_icache1_preload_order().bit()),
-            )
-            .field(
-                "l1_icache1_preload_rgid",
-                &format_args!("{}", self.l1_icache1_preload_rgid().bits()),
-            )
+            .field("l1_icache1_preload_ena", &self.l1_icache1_preload_ena())
+            .field("l1_icache1_preload_done", &self.l1_icache1_preload_done())
+            .field("l1_icache1_preload_order", &self.l1_icache1_preload_order())
+            .field("l1_icache1_preload_rgid", &self.l1_icache1_preload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_PRELOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_icache1_preload_size.rs b/esp32c6/src/extmem/l1_icache1_preload_size.rs
index 76d548b8ea..6f82650797 100644
--- a/esp32c6/src/extmem/l1_icache1_preload_size.rs
+++ b/esp32c6/src/extmem/l1_icache1_preload_size.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE1_PRELOAD_SIZE")
-            .field(
-                "l1_icache1_preload_size",
-                &format_args!("{}", self.l1_icache1_preload_size().bits()),
-            )
+            .field("l1_icache1_preload_size", &self.l1_icache1_preload_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 1 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_preload_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE1_PRELOAD_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE1_PRELOAD_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache1_prelock_conf.rs b/esp32c6/src/extmem/l1_icache1_prelock_conf.rs
index 7e7210d316..e62781fea5 100644
--- a/esp32c6/src/extmem/l1_icache1_prelock_conf.rs
+++ b/esp32c6/src/extmem/l1_icache1_prelock_conf.rs
@@ -29,25 +29,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_PRELOCK_CONF")
             .field(
                 "l1_icache1_prelock_sct0_en",
-                &format_args!("{}", self.l1_icache1_prelock_sct0_en().bit()),
+                &self.l1_icache1_prelock_sct0_en(),
             )
             .field(
                 "l1_icache1_prelock_sct1_en",
-                &format_args!("{}", self.l1_icache1_prelock_sct1_en().bit()),
-            )
-            .field(
-                "l1_icache1_prelock_rgid",
-                &format_args!("{}", self.l1_icache1_prelock_rgid().bits()),
+                &self.l1_icache1_prelock_sct1_en(),
             )
+            .field("l1_icache1_prelock_rgid", &self.l1_icache1_prelock_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_PRELOCK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 1 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE1_PRELOCK_CONF_SPEC;
 impl crate::RegisterSpec for L1_ICACHE1_PRELOCK_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache1_prelock_sct0_addr.rs b/esp32c6/src/extmem/l1_icache1_prelock_sct0_addr.rs
index 1047af9dff..bb07b2c6a0 100644
--- a/esp32c6/src/extmem/l1_icache1_prelock_sct0_addr.rs
+++ b/esp32c6/src/extmem/l1_icache1_prelock_sct0_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_PRELOCK_SCT0_ADDR")
             .field(
                 "l1_icache1_prelock_sct0_addr",
-                &format_args!("{}", self.l1_icache1_prelock_sct0_addr().bits()),
+                &self.l1_icache1_prelock_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_PRELOCK_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 1 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_sct0_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE1_PRELOCK_SCT0_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE1_PRELOCK_SCT0_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache1_prelock_sct1_addr.rs b/esp32c6/src/extmem/l1_icache1_prelock_sct1_addr.rs
index a6af79a554..7ca99fb9b2 100644
--- a/esp32c6/src/extmem/l1_icache1_prelock_sct1_addr.rs
+++ b/esp32c6/src/extmem/l1_icache1_prelock_sct1_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_PRELOCK_SCT1_ADDR")
             .field(
                 "l1_icache1_prelock_sct1_addr",
-                &format_args!("{}", self.l1_icache1_prelock_sct1_addr().bits()),
+                &self.l1_icache1_prelock_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_PRELOCK_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 1 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_sct1_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE1_PRELOCK_SCT1_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE1_PRELOCK_SCT1_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache1_prelock_sct_size.rs b/esp32c6/src/extmem/l1_icache1_prelock_sct_size.rs
index cf883a1807..5a16be0709 100644
--- a/esp32c6/src/extmem/l1_icache1_prelock_sct_size.rs
+++ b/esp32c6/src/extmem/l1_icache1_prelock_sct_size.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_PRELOCK_SCT_SIZE")
             .field(
                 "l1_icache1_prelock_sct0_size",
-                &format_args!("{}", self.l1_icache1_prelock_sct0_size().bits()),
+                &self.l1_icache1_prelock_sct0_size(),
             )
             .field(
                 "l1_icache1_prelock_sct1_size",
-                &format_args!("{}", self.l1_icache1_prelock_sct1_size().bits()),
+                &self.l1_icache1_prelock_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_PRELOCK_SCT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 1 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_prelock_sct_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE1_PRELOCK_SCT_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE1_PRELOCK_SCT_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache2_acs_fail_addr.rs b/esp32c6/src/extmem/l1_icache2_acs_fail_addr.rs
index 975bbbec52..80b58ecd90 100644
--- a/esp32c6/src/extmem/l1_icache2_acs_fail_addr.rs
+++ b/esp32c6/src/extmem/l1_icache2_acs_fail_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE2_ACS_FAIL_ADDR")
-            .field(
-                "l1_icache2_fail_addr",
-                &format_args!("{}", self.l1_icache2_fail_addr().bits()),
-            )
+            .field("l1_icache2_fail_addr", &self.l1_icache2_fail_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_ACS_FAIL_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_acs_fail_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_ACS_FAIL_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_ACS_FAIL_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache2_acs_fail_id_attr.rs b/esp32c6/src/extmem/l1_icache2_acs_fail_id_attr.rs
index 761d49ad02..93527c533c 100644
--- a/esp32c6/src/extmem/l1_icache2_acs_fail_id_attr.rs
+++ b/esp32c6/src/extmem/l1_icache2_acs_fail_id_attr.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE2_ACS_FAIL_ID_ATTR")
-            .field(
-                "l1_icache2_fail_id",
-                &format_args!("{}", self.l1_icache2_fail_id().bits()),
-            )
-            .field(
-                "l1_icache2_fail_attr",
-                &format_args!("{}", self.l1_icache2_fail_attr().bits()),
-            )
+            .field("l1_icache2_fail_id", &self.l1_icache2_fail_id())
+            .field("l1_icache2_fail_attr", &self.l1_icache2_fail_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_ACS_FAIL_ID_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_acs_fail_id_attr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_ACS_FAIL_ID_ATTR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_ACS_FAIL_ID_ATTR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache2_autoload_ctrl.rs b/esp32c6/src/extmem/l1_icache2_autoload_ctrl.rs
index 4d19422b05..2a7c317129 100644
--- a/esp32c6/src/extmem/l1_icache2_autoload_ctrl.rs
+++ b/esp32c6/src/extmem/l1_icache2_autoload_ctrl.rs
@@ -55,43 +55,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE2_AUTOLOAD_CTRL")
-            .field(
-                "l1_icache2_autoload_ena",
-                &format_args!("{}", self.l1_icache2_autoload_ena().bit()),
-            )
-            .field(
-                "l1_icache2_autoload_done",
-                &format_args!("{}", self.l1_icache2_autoload_done().bit()),
-            )
+            .field("l1_icache2_autoload_ena", &self.l1_icache2_autoload_ena())
+            .field("l1_icache2_autoload_done", &self.l1_icache2_autoload_done())
             .field(
                 "l1_icache2_autoload_order",
-                &format_args!("{}", self.l1_icache2_autoload_order().bit()),
+                &self.l1_icache2_autoload_order(),
             )
             .field(
                 "l1_icache2_autoload_trigger_mode",
-                &format_args!("{}", self.l1_icache2_autoload_trigger_mode().bits()),
+                &self.l1_icache2_autoload_trigger_mode(),
             )
             .field(
                 "l1_icache2_autoload_sct0_ena",
-                &format_args!("{}", self.l1_icache2_autoload_sct0_ena().bit()),
+                &self.l1_icache2_autoload_sct0_ena(),
             )
             .field(
                 "l1_icache2_autoload_sct1_ena",
-                &format_args!("{}", self.l1_icache2_autoload_sct1_ena().bit()),
-            )
-            .field(
-                "l1_icache2_autoload_rgid",
-                &format_args!("{}", self.l1_icache2_autoload_rgid().bits()),
+                &self.l1_icache2_autoload_sct1_ena(),
             )
+            .field("l1_icache2_autoload_rgid", &self.l1_icache2_autoload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_AUTOLOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_AUTOLOAD_CTRL_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_AUTOLOAD_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache2_autoload_sct0_addr.rs b/esp32c6/src/extmem/l1_icache2_autoload_sct0_addr.rs
index ef732ab4d9..3260abf5b8 100644
--- a/esp32c6/src/extmem/l1_icache2_autoload_sct0_addr.rs
+++ b/esp32c6/src/extmem/l1_icache2_autoload_sct0_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_AUTOLOAD_SCT0_ADDR")
             .field(
                 "l1_icache2_autoload_sct0_addr",
-                &format_args!("{}", self.l1_icache2_autoload_sct0_addr().bits()),
+                &self.l1_icache2_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_AUTOLOAD_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct0_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_AUTOLOAD_SCT0_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_AUTOLOAD_SCT0_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache2_autoload_sct0_size.rs b/esp32c6/src/extmem/l1_icache2_autoload_sct0_size.rs
index d1d013efdb..4406852e2b 100644
--- a/esp32c6/src/extmem/l1_icache2_autoload_sct0_size.rs
+++ b/esp32c6/src/extmem/l1_icache2_autoload_sct0_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_AUTOLOAD_SCT0_SIZE")
             .field(
                 "l1_icache2_autoload_sct0_size",
-                &format_args!("{}", self.l1_icache2_autoload_sct0_size().bits()),
+                &self.l1_icache2_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_AUTOLOAD_SCT0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct0_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_AUTOLOAD_SCT0_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_AUTOLOAD_SCT0_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache2_autoload_sct1_addr.rs b/esp32c6/src/extmem/l1_icache2_autoload_sct1_addr.rs
index 382b428cf6..fec04ac3b6 100644
--- a/esp32c6/src/extmem/l1_icache2_autoload_sct1_addr.rs
+++ b/esp32c6/src/extmem/l1_icache2_autoload_sct1_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_AUTOLOAD_SCT1_ADDR")
             .field(
                 "l1_icache2_autoload_sct1_addr",
-                &format_args!("{}", self.l1_icache2_autoload_sct1_addr().bits()),
+                &self.l1_icache2_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_AUTOLOAD_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct1_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_AUTOLOAD_SCT1_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_AUTOLOAD_SCT1_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache2_autoload_sct1_size.rs b/esp32c6/src/extmem/l1_icache2_autoload_sct1_size.rs
index 9c0559d830..16a7fba9bc 100644
--- a/esp32c6/src/extmem/l1_icache2_autoload_sct1_size.rs
+++ b/esp32c6/src/extmem/l1_icache2_autoload_sct1_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_AUTOLOAD_SCT1_SIZE")
             .field(
                 "l1_icache2_autoload_sct1_size",
-                &format_args!("{}", self.l1_icache2_autoload_sct1_size().bits()),
+                &self.l1_icache2_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_AUTOLOAD_SCT1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct1_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_AUTOLOAD_SCT1_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_AUTOLOAD_SCT1_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache2_preload_addr.rs b/esp32c6/src/extmem/l1_icache2_preload_addr.rs
index 3980a1cfb4..f336c9769e 100644
--- a/esp32c6/src/extmem/l1_icache2_preload_addr.rs
+++ b/esp32c6/src/extmem/l1_icache2_preload_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE2_PRELOAD_ADDR")
-            .field(
-                "l1_icache2_preload_addr",
-                &format_args!("{}", self.l1_icache2_preload_addr().bits()),
-            )
+            .field("l1_icache2_preload_addr", &self.l1_icache2_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_preload_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_PRELOAD_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_PRELOAD_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache2_preload_ctrl.rs b/esp32c6/src/extmem/l1_icache2_preload_ctrl.rs
index 417c5b5b37..c8d5784ca1 100644
--- a/esp32c6/src/extmem/l1_icache2_preload_ctrl.rs
+++ b/esp32c6/src/extmem/l1_icache2_preload_ctrl.rs
@@ -38,31 +38,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE2_PRELOAD_CTRL")
-            .field(
-                "l1_icache2_preload_ena",
-                &format_args!("{}", self.l1_icache2_preload_ena().bit()),
-            )
-            .field(
-                "l1_icache2_preload_done",
-                &format_args!("{}", self.l1_icache2_preload_done().bit()),
-            )
-            .field(
-                "l1_icache2_preload_order",
-                &format_args!("{}", self.l1_icache2_preload_order().bit()),
-            )
-            .field(
-                "l1_icache2_preload_rgid",
-                &format_args!("{}", self.l1_icache2_preload_rgid().bits()),
-            )
+            .field("l1_icache2_preload_ena", &self.l1_icache2_preload_ena())
+            .field("l1_icache2_preload_done", &self.l1_icache2_preload_done())
+            .field("l1_icache2_preload_order", &self.l1_icache2_preload_order())
+            .field("l1_icache2_preload_rgid", &self.l1_icache2_preload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_PRELOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_icache2_preload_size.rs b/esp32c6/src/extmem/l1_icache2_preload_size.rs
index 88acf1b2bf..943a4fa27c 100644
--- a/esp32c6/src/extmem/l1_icache2_preload_size.rs
+++ b/esp32c6/src/extmem/l1_icache2_preload_size.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE2_PRELOAD_SIZE")
-            .field(
-                "l1_icache2_preload_size",
-                &format_args!("{}", self.l1_icache2_preload_size().bits()),
-            )
+            .field("l1_icache2_preload_size", &self.l1_icache2_preload_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_preload_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_PRELOAD_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_PRELOAD_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache2_prelock_conf.rs b/esp32c6/src/extmem/l1_icache2_prelock_conf.rs
index 1430c72fae..c1c84f05db 100644
--- a/esp32c6/src/extmem/l1_icache2_prelock_conf.rs
+++ b/esp32c6/src/extmem/l1_icache2_prelock_conf.rs
@@ -29,25 +29,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_PRELOCK_CONF")
             .field(
                 "l1_icache2_prelock_sct0_en",
-                &format_args!("{}", self.l1_icache2_prelock_sct0_en().bit()),
+                &self.l1_icache2_prelock_sct0_en(),
             )
             .field(
                 "l1_icache2_prelock_sct1_en",
-                &format_args!("{}", self.l1_icache2_prelock_sct1_en().bit()),
-            )
-            .field(
-                "l1_icache2_prelock_rgid",
-                &format_args!("{}", self.l1_icache2_prelock_rgid().bits()),
+                &self.l1_icache2_prelock_sct1_en(),
             )
+            .field("l1_icache2_prelock_rgid", &self.l1_icache2_prelock_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_PRELOCK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_PRELOCK_CONF_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_PRELOCK_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache2_prelock_sct0_addr.rs b/esp32c6/src/extmem/l1_icache2_prelock_sct0_addr.rs
index 3765a345ba..76d8072bf5 100644
--- a/esp32c6/src/extmem/l1_icache2_prelock_sct0_addr.rs
+++ b/esp32c6/src/extmem/l1_icache2_prelock_sct0_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_PRELOCK_SCT0_ADDR")
             .field(
                 "l1_icache2_prelock_sct0_addr",
-                &format_args!("{}", self.l1_icache2_prelock_sct0_addr().bits()),
+                &self.l1_icache2_prelock_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_PRELOCK_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_sct0_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_PRELOCK_SCT0_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_PRELOCK_SCT0_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache2_prelock_sct1_addr.rs b/esp32c6/src/extmem/l1_icache2_prelock_sct1_addr.rs
index 81b45ce1a1..ea4353ba03 100644
--- a/esp32c6/src/extmem/l1_icache2_prelock_sct1_addr.rs
+++ b/esp32c6/src/extmem/l1_icache2_prelock_sct1_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_PRELOCK_SCT1_ADDR")
             .field(
                 "l1_icache2_prelock_sct1_addr",
-                &format_args!("{}", self.l1_icache2_prelock_sct1_addr().bits()),
+                &self.l1_icache2_prelock_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_PRELOCK_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_sct1_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_PRELOCK_SCT1_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_PRELOCK_SCT1_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache2_prelock_sct_size.rs b/esp32c6/src/extmem/l1_icache2_prelock_sct_size.rs
index 297d69f093..8375bcb15b 100644
--- a/esp32c6/src/extmem/l1_icache2_prelock_sct_size.rs
+++ b/esp32c6/src/extmem/l1_icache2_prelock_sct_size.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_PRELOCK_SCT_SIZE")
             .field(
                 "l1_icache2_prelock_sct0_size",
-                &format_args!("{}", self.l1_icache2_prelock_sct0_size().bits()),
+                &self.l1_icache2_prelock_sct0_size(),
             )
             .field(
                 "l1_icache2_prelock_sct1_size",
-                &format_args!("{}", self.l1_icache2_prelock_sct1_size().bits()),
+                &self.l1_icache2_prelock_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_PRELOCK_SCT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_sct_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_PRELOCK_SCT_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_PRELOCK_SCT_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache3_acs_fail_addr.rs b/esp32c6/src/extmem/l1_icache3_acs_fail_addr.rs
index 7fcdd89ec5..3c7634f83a 100644
--- a/esp32c6/src/extmem/l1_icache3_acs_fail_addr.rs
+++ b/esp32c6/src/extmem/l1_icache3_acs_fail_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE3_ACS_FAIL_ADDR")
-            .field(
-                "l1_icache3_fail_addr",
-                &format_args!("{}", self.l1_icache3_fail_addr().bits()),
-            )
+            .field("l1_icache3_fail_addr", &self.l1_icache3_fail_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_ACS_FAIL_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_acs_fail_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_ACS_FAIL_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_ACS_FAIL_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache3_acs_fail_id_attr.rs b/esp32c6/src/extmem/l1_icache3_acs_fail_id_attr.rs
index 909b5e8650..4827666791 100644
--- a/esp32c6/src/extmem/l1_icache3_acs_fail_id_attr.rs
+++ b/esp32c6/src/extmem/l1_icache3_acs_fail_id_attr.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE3_ACS_FAIL_ID_ATTR")
-            .field(
-                "l1_icache3_fail_id",
-                &format_args!("{}", self.l1_icache3_fail_id().bits()),
-            )
-            .field(
-                "l1_icache3_fail_attr",
-                &format_args!("{}", self.l1_icache3_fail_attr().bits()),
-            )
+            .field("l1_icache3_fail_id", &self.l1_icache3_fail_id())
+            .field("l1_icache3_fail_attr", &self.l1_icache3_fail_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_ACS_FAIL_ID_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_acs_fail_id_attr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_ACS_FAIL_ID_ATTR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_ACS_FAIL_ID_ATTR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache3_autoload_ctrl.rs b/esp32c6/src/extmem/l1_icache3_autoload_ctrl.rs
index 4c4772435a..d888fbfbae 100644
--- a/esp32c6/src/extmem/l1_icache3_autoload_ctrl.rs
+++ b/esp32c6/src/extmem/l1_icache3_autoload_ctrl.rs
@@ -55,43 +55,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE3_AUTOLOAD_CTRL")
-            .field(
-                "l1_icache3_autoload_ena",
-                &format_args!("{}", self.l1_icache3_autoload_ena().bit()),
-            )
-            .field(
-                "l1_icache3_autoload_done",
-                &format_args!("{}", self.l1_icache3_autoload_done().bit()),
-            )
+            .field("l1_icache3_autoload_ena", &self.l1_icache3_autoload_ena())
+            .field("l1_icache3_autoload_done", &self.l1_icache3_autoload_done())
             .field(
                 "l1_icache3_autoload_order",
-                &format_args!("{}", self.l1_icache3_autoload_order().bit()),
+                &self.l1_icache3_autoload_order(),
             )
             .field(
                 "l1_icache3_autoload_trigger_mode",
-                &format_args!("{}", self.l1_icache3_autoload_trigger_mode().bits()),
+                &self.l1_icache3_autoload_trigger_mode(),
             )
             .field(
                 "l1_icache3_autoload_sct0_ena",
-                &format_args!("{}", self.l1_icache3_autoload_sct0_ena().bit()),
+                &self.l1_icache3_autoload_sct0_ena(),
             )
             .field(
                 "l1_icache3_autoload_sct1_ena",
-                &format_args!("{}", self.l1_icache3_autoload_sct1_ena().bit()),
-            )
-            .field(
-                "l1_icache3_autoload_rgid",
-                &format_args!("{}", self.l1_icache3_autoload_rgid().bits()),
+                &self.l1_icache3_autoload_sct1_ena(),
             )
+            .field("l1_icache3_autoload_rgid", &self.l1_icache3_autoload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_AUTOLOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_AUTOLOAD_CTRL_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_AUTOLOAD_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache3_autoload_sct0_addr.rs b/esp32c6/src/extmem/l1_icache3_autoload_sct0_addr.rs
index 8d88a04ff9..830bf6504e 100644
--- a/esp32c6/src/extmem/l1_icache3_autoload_sct0_addr.rs
+++ b/esp32c6/src/extmem/l1_icache3_autoload_sct0_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_AUTOLOAD_SCT0_ADDR")
             .field(
                 "l1_icache3_autoload_sct0_addr",
-                &format_args!("{}", self.l1_icache3_autoload_sct0_addr().bits()),
+                &self.l1_icache3_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_AUTOLOAD_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct0_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_AUTOLOAD_SCT0_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_AUTOLOAD_SCT0_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache3_autoload_sct0_size.rs b/esp32c6/src/extmem/l1_icache3_autoload_sct0_size.rs
index beba0af087..01ccd49849 100644
--- a/esp32c6/src/extmem/l1_icache3_autoload_sct0_size.rs
+++ b/esp32c6/src/extmem/l1_icache3_autoload_sct0_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_AUTOLOAD_SCT0_SIZE")
             .field(
                 "l1_icache3_autoload_sct0_size",
-                &format_args!("{}", self.l1_icache3_autoload_sct0_size().bits()),
+                &self.l1_icache3_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_AUTOLOAD_SCT0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct0_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_AUTOLOAD_SCT0_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_AUTOLOAD_SCT0_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache3_autoload_sct1_addr.rs b/esp32c6/src/extmem/l1_icache3_autoload_sct1_addr.rs
index 22c5cb1197..e162b525a7 100644
--- a/esp32c6/src/extmem/l1_icache3_autoload_sct1_addr.rs
+++ b/esp32c6/src/extmem/l1_icache3_autoload_sct1_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_AUTOLOAD_SCT1_ADDR")
             .field(
                 "l1_icache3_autoload_sct1_addr",
-                &format_args!("{}", self.l1_icache3_autoload_sct1_addr().bits()),
+                &self.l1_icache3_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_AUTOLOAD_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct1_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_AUTOLOAD_SCT1_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_AUTOLOAD_SCT1_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache3_autoload_sct1_size.rs b/esp32c6/src/extmem/l1_icache3_autoload_sct1_size.rs
index 06bcce8e2d..fb08808302 100644
--- a/esp32c6/src/extmem/l1_icache3_autoload_sct1_size.rs
+++ b/esp32c6/src/extmem/l1_icache3_autoload_sct1_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_AUTOLOAD_SCT1_SIZE")
             .field(
                 "l1_icache3_autoload_sct1_size",
-                &format_args!("{}", self.l1_icache3_autoload_sct1_size().bits()),
+                &self.l1_icache3_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_AUTOLOAD_SCT1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct1_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_AUTOLOAD_SCT1_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_AUTOLOAD_SCT1_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache3_preload_addr.rs b/esp32c6/src/extmem/l1_icache3_preload_addr.rs
index e4eff512d2..60f82797a7 100644
--- a/esp32c6/src/extmem/l1_icache3_preload_addr.rs
+++ b/esp32c6/src/extmem/l1_icache3_preload_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE3_PRELOAD_ADDR")
-            .field(
-                "l1_icache3_preload_addr",
-                &format_args!("{}", self.l1_icache3_preload_addr().bits()),
-            )
+            .field("l1_icache3_preload_addr", &self.l1_icache3_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_preload_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_PRELOAD_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_PRELOAD_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache3_preload_ctrl.rs b/esp32c6/src/extmem/l1_icache3_preload_ctrl.rs
index de5b2a8ea0..2af348238e 100644
--- a/esp32c6/src/extmem/l1_icache3_preload_ctrl.rs
+++ b/esp32c6/src/extmem/l1_icache3_preload_ctrl.rs
@@ -38,31 +38,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE3_PRELOAD_CTRL")
-            .field(
-                "l1_icache3_preload_ena",
-                &format_args!("{}", self.l1_icache3_preload_ena().bit()),
-            )
-            .field(
-                "l1_icache3_preload_done",
-                &format_args!("{}", self.l1_icache3_preload_done().bit()),
-            )
-            .field(
-                "l1_icache3_preload_order",
-                &format_args!("{}", self.l1_icache3_preload_order().bit()),
-            )
-            .field(
-                "l1_icache3_preload_rgid",
-                &format_args!("{}", self.l1_icache3_preload_rgid().bits()),
-            )
+            .field("l1_icache3_preload_ena", &self.l1_icache3_preload_ena())
+            .field("l1_icache3_preload_done", &self.l1_icache3_preload_done())
+            .field("l1_icache3_preload_order", &self.l1_icache3_preload_order())
+            .field("l1_icache3_preload_rgid", &self.l1_icache3_preload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_PRELOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable preload operation on L1-ICache3. It will be cleared by hardware automatically after preload operation is done."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l1_icache3_preload_size.rs b/esp32c6/src/extmem/l1_icache3_preload_size.rs
index cc77e54790..bd8f85215a 100644
--- a/esp32c6/src/extmem/l1_icache3_preload_size.rs
+++ b/esp32c6/src/extmem/l1_icache3_preload_size.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE3_PRELOAD_SIZE")
-            .field(
-                "l1_icache3_preload_size",
-                &format_args!("{}", self.l1_icache3_preload_size().bits()),
-            )
+            .field("l1_icache3_preload_size", &self.l1_icache3_preload_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_preload_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_PRELOAD_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_PRELOAD_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache3_prelock_conf.rs b/esp32c6/src/extmem/l1_icache3_prelock_conf.rs
index 58a4126a57..e2c7654494 100644
--- a/esp32c6/src/extmem/l1_icache3_prelock_conf.rs
+++ b/esp32c6/src/extmem/l1_icache3_prelock_conf.rs
@@ -29,25 +29,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_PRELOCK_CONF")
             .field(
                 "l1_icache3_prelock_sct0_en",
-                &format_args!("{}", self.l1_icache3_prelock_sct0_en().bit()),
+                &self.l1_icache3_prelock_sct0_en(),
             )
             .field(
                 "l1_icache3_prelock_sct1_en",
-                &format_args!("{}", self.l1_icache3_prelock_sct1_en().bit()),
-            )
-            .field(
-                "l1_icache3_prelock_rgid",
-                &format_args!("{}", self.l1_icache3_prelock_rgid().bits()),
+                &self.l1_icache3_prelock_sct1_en(),
             )
+            .field("l1_icache3_prelock_rgid", &self.l1_icache3_prelock_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_PRELOCK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_PRELOCK_CONF_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_PRELOCK_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache3_prelock_sct0_addr.rs b/esp32c6/src/extmem/l1_icache3_prelock_sct0_addr.rs
index 95a8794a46..a9854b1ee7 100644
--- a/esp32c6/src/extmem/l1_icache3_prelock_sct0_addr.rs
+++ b/esp32c6/src/extmem/l1_icache3_prelock_sct0_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_PRELOCK_SCT0_ADDR")
             .field(
                 "l1_icache3_prelock_sct0_addr",
-                &format_args!("{}", self.l1_icache3_prelock_sct0_addr().bits()),
+                &self.l1_icache3_prelock_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_PRELOCK_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_sct0_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_PRELOCK_SCT0_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_PRELOCK_SCT0_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache3_prelock_sct1_addr.rs b/esp32c6/src/extmem/l1_icache3_prelock_sct1_addr.rs
index 3d92a27d63..fdf38eb453 100644
--- a/esp32c6/src/extmem/l1_icache3_prelock_sct1_addr.rs
+++ b/esp32c6/src/extmem/l1_icache3_prelock_sct1_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_PRELOCK_SCT1_ADDR")
             .field(
                 "l1_icache3_prelock_sct1_addr",
-                &format_args!("{}", self.l1_icache3_prelock_sct1_addr().bits()),
+                &self.l1_icache3_prelock_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_PRELOCK_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_sct1_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_PRELOCK_SCT1_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_PRELOCK_SCT1_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache3_prelock_sct_size.rs b/esp32c6/src/extmem/l1_icache3_prelock_sct_size.rs
index 60466d4f91..62d929570e 100644
--- a/esp32c6/src/extmem/l1_icache3_prelock_sct_size.rs
+++ b/esp32c6/src/extmem/l1_icache3_prelock_sct_size.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_PRELOCK_SCT_SIZE")
             .field(
                 "l1_icache3_prelock_sct0_size",
-                &format_args!("{}", self.l1_icache3_prelock_sct0_size().bits()),
+                &self.l1_icache3_prelock_sct0_size(),
             )
             .field(
                 "l1_icache3_prelock_sct1_size",
-                &format_args!("{}", self.l1_icache3_prelock_sct1_size().bits()),
+                &self.l1_icache3_prelock_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_PRELOCK_SCT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_sct_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_PRELOCK_SCT_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_PRELOCK_SCT_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache_blocksize_conf.rs b/esp32c6/src/extmem/l1_icache_blocksize_conf.rs
index 41652b589b..000c9ef721 100644
--- a/esp32c6/src/extmem/l1_icache_blocksize_conf.rs
+++ b/esp32c6/src/extmem/l1_icache_blocksize_conf.rs
@@ -48,39 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE_BLOCKSIZE_CONF")
-            .field(
-                "l1_icache_blocksize_8",
-                &format_args!("{}", self.l1_icache_blocksize_8().bit()),
-            )
-            .field(
-                "l1_icache_blocksize_16",
-                &format_args!("{}", self.l1_icache_blocksize_16().bit()),
-            )
-            .field(
-                "l1_icache_blocksize_32",
-                &format_args!("{}", self.l1_icache_blocksize_32().bit()),
-            )
-            .field(
-                "l1_icache_blocksize_64",
-                &format_args!("{}", self.l1_icache_blocksize_64().bit()),
-            )
-            .field(
-                "l1_icache_blocksize_128",
-                &format_args!("{}", self.l1_icache_blocksize_128().bit()),
-            )
-            .field(
-                "l1_icache_blocksize_256",
-                &format_args!("{}", self.l1_icache_blocksize_256().bit()),
-            )
+            .field("l1_icache_blocksize_8", &self.l1_icache_blocksize_8())
+            .field("l1_icache_blocksize_16", &self.l1_icache_blocksize_16())
+            .field("l1_icache_blocksize_32", &self.l1_icache_blocksize_32())
+            .field("l1_icache_blocksize_64", &self.l1_icache_blocksize_64())
+            .field("l1_icache_blocksize_128", &self.l1_icache_blocksize_128())
+            .field("l1_icache_blocksize_256", &self.l1_icache_blocksize_256())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE_BLOCKSIZE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache BlockSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache_blocksize_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE_BLOCKSIZE_CONF_SPEC;
 impl crate::RegisterSpec for L1_ICACHE_BLOCKSIZE_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache_cachesize_conf.rs b/esp32c6/src/extmem/l1_icache_cachesize_conf.rs
index e7e041ba3a..086f43c0d2 100644
--- a/esp32c6/src/extmem/l1_icache_cachesize_conf.rs
+++ b/esp32c6/src/extmem/l1_icache_cachesize_conf.rs
@@ -97,67 +97,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE_CACHESIZE_CONF")
-            .field(
-                "l1_icache_cachesize_1k",
-                &format_args!("{}", self.l1_icache_cachesize_1k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_2k",
-                &format_args!("{}", self.l1_icache_cachesize_2k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_4k",
-                &format_args!("{}", self.l1_icache_cachesize_4k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_8k",
-                &format_args!("{}", self.l1_icache_cachesize_8k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_16k",
-                &format_args!("{}", self.l1_icache_cachesize_16k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_32k",
-                &format_args!("{}", self.l1_icache_cachesize_32k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_64k",
-                &format_args!("{}", self.l1_icache_cachesize_64k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_128k",
-                &format_args!("{}", self.l1_icache_cachesize_128k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_256k",
-                &format_args!("{}", self.l1_icache_cachesize_256k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_512k",
-                &format_args!("{}", self.l1_icache_cachesize_512k().bit()),
-            )
+            .field("l1_icache_cachesize_1k", &self.l1_icache_cachesize_1k())
+            .field("l1_icache_cachesize_2k", &self.l1_icache_cachesize_2k())
+            .field("l1_icache_cachesize_4k", &self.l1_icache_cachesize_4k())
+            .field("l1_icache_cachesize_8k", &self.l1_icache_cachesize_8k())
+            .field("l1_icache_cachesize_16k", &self.l1_icache_cachesize_16k())
+            .field("l1_icache_cachesize_32k", &self.l1_icache_cachesize_32k())
+            .field("l1_icache_cachesize_64k", &self.l1_icache_cachesize_64k())
+            .field("l1_icache_cachesize_128k", &self.l1_icache_cachesize_128k())
+            .field("l1_icache_cachesize_256k", &self.l1_icache_cachesize_256k())
+            .field("l1_icache_cachesize_512k", &self.l1_icache_cachesize_512k())
             .field(
                 "l1_icache_cachesize_1024k",
-                &format_args!("{}", self.l1_icache_cachesize_1024k().bit()),
+                &self.l1_icache_cachesize_1024k(),
             )
             .field(
                 "l1_icache_cachesize_2048k",
-                &format_args!("{}", self.l1_icache_cachesize_2048k().bit()),
+                &self.l1_icache_cachesize_2048k(),
             )
             .field(
                 "l1_icache_cachesize_4096k",
-                &format_args!("{}", self.l1_icache_cachesize_4096k().bit()),
+                &self.l1_icache_cachesize_4096k(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE_CACHESIZE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache CacheSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache_cachesize_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE_CACHESIZE_CONF_SPEC;
 impl crate::RegisterSpec for L1_ICACHE_CACHESIZE_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l1_icache_ctrl.rs b/esp32c6/src/extmem/l1_icache_ctrl.rs
index 295a146667..7957c5a519 100644
--- a/esp32c6/src/extmem/l1_icache_ctrl.rs
+++ b/esp32c6/src/extmem/l1_icache_ctrl.rs
@@ -41,35 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE_CTRL")
-            .field(
-                "l1_icache_shut_ibus0",
-                &format_args!("{}", self.l1_icache_shut_ibus0().bit()),
-            )
-            .field(
-                "l1_icache_shut_ibus1",
-                &format_args!("{}", self.l1_icache_shut_ibus1().bit()),
-            )
-            .field(
-                "l1_icache_shut_ibus2",
-                &format_args!("{}", self.l1_icache_shut_ibus2().bit()),
-            )
-            .field(
-                "l1_icache_shut_ibus3",
-                &format_args!("{}", self.l1_icache_shut_ibus3().bit()),
-            )
-            .field(
-                "l1_icache_undef_op",
-                &format_args!("{}", self.l1_icache_undef_op().bits()),
-            )
+            .field("l1_icache_shut_ibus0", &self.l1_icache_shut_ibus0())
+            .field("l1_icache_shut_ibus1", &self.l1_icache_shut_ibus1())
+            .field("l1_icache_shut_ibus2", &self.l1_icache_shut_ibus2())
+            .field("l1_icache_shut_ibus3", &self.l1_icache_shut_ibus3())
+            .field("l1_icache_undef_op", &self.l1_icache_undef_op())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache(L1-ICache) control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE_CTRL_SPEC;
 impl crate::RegisterSpec for L1_ICACHE_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l1_unallocate_buffer_clear.rs b/esp32c6/src/extmem/l1_unallocate_buffer_clear.rs
index 226ea71984..deb0d4072c 100644
--- a/esp32c6/src/extmem/l1_unallocate_buffer_clear.rs
+++ b/esp32c6/src/extmem/l1_unallocate_buffer_clear.rs
@@ -45,35 +45,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_UNALLOCATE_BUFFER_CLEAR")
-            .field(
-                "l1_icache0_unalloc_clr",
-                &format_args!("{}", self.l1_icache0_unalloc_clr().bit()),
-            )
-            .field(
-                "l1_icache1_unalloc_clr",
-                &format_args!("{}", self.l1_icache1_unalloc_clr().bit()),
-            )
-            .field(
-                "l1_icache2_unalloc_clr",
-                &format_args!("{}", self.l1_icache2_unalloc_clr().bit()),
-            )
-            .field(
-                "l1_icache3_unalloc_clr",
-                &format_args!("{}", self.l1_icache3_unalloc_clr().bit()),
-            )
-            .field(
-                "l1_cache_unalloc_clr",
-                &format_args!("{}", self.l1_cache_unalloc_clr().bit()),
-            )
+            .field("l1_icache0_unalloc_clr", &self.l1_icache0_unalloc_clr())
+            .field("l1_icache1_unalloc_clr", &self.l1_icache1_unalloc_clr())
+            .field("l1_icache2_unalloc_clr", &self.l1_icache2_unalloc_clr())
+            .field("l1_icache3_unalloc_clr", &self.l1_icache3_unalloc_clr())
+            .field("l1_cache_unalloc_clr", &self.l1_cache_unalloc_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_UNALLOCATE_BUFFER_CLEAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - The bit is used to clear the unallocate request buffer of l1 cache where the unallocate request is responsed but not completed."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l2_bypass_cache_conf.rs b/esp32c6/src/extmem/l2_bypass_cache_conf.rs
index b9000d6d86..8d86d8c2d1 100644
--- a/esp32c6/src/extmem/l2_bypass_cache_conf.rs
+++ b/esp32c6/src/extmem/l2_bypass_cache_conf.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_BYPASS_CACHE_CONF")
-            .field(
-                "bypass_l2_cache_en",
-                &format_args!("{}", self.bypass_l2_cache_en().bit()),
-            )
+            .field("bypass_l2_cache_en", &self.bypass_l2_cache_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_BYPASS_CACHE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Bypass Cache configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_bypass_cache_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_BYPASS_CACHE_CONF_SPEC;
 impl crate::RegisterSpec for L2_BYPASS_CACHE_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_access_attr_ctrl.rs b/esp32c6/src/extmem/l2_cache_access_attr_ctrl.rs
index bf1234205f..d3f4116209 100644
--- a/esp32c6/src/extmem/l2_cache_access_attr_ctrl.rs
+++ b/esp32c6/src/extmem/l2_cache_access_attr_ctrl.rs
@@ -34,31 +34,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACCESS_ATTR_CTRL")
-            .field(
-                "l2_cache_access_force_cc",
-                &format_args!("{}", self.l2_cache_access_force_cc().bit()),
-            )
-            .field(
-                "l2_cache_access_force_wb",
-                &format_args!("{}", self.l2_cache_access_force_wb().bit()),
-            )
+            .field("l2_cache_access_force_cc", &self.l2_cache_access_force_cc())
+            .field("l2_cache_access_force_wb", &self.l2_cache_access_force_wb())
             .field(
                 "l2_cache_access_force_wma",
-                &format_args!("{}", self.l2_cache_access_force_wma().bit()),
+                &self.l2_cache_access_force_wma(),
             )
             .field(
                 "l2_cache_access_force_rma",
-                &format_args!("{}", self.l2_cache_access_force_rma().bit()),
+                &self.l2_cache_access_force_rma(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACCESS_ATTR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 Cache access Attribute propagation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_access_attr_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_ACCESS_ATTR_CTRL_SPEC;
 impl crate::RegisterSpec for L2_CACHE_ACCESS_ATTR_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_acs_cnt_ctrl.rs b/esp32c6/src/extmem/l2_cache_acs_cnt_ctrl.rs
index 8d18d36932..f0855632cc 100644
--- a/esp32c6/src/extmem/l2_cache_acs_cnt_ctrl.rs
+++ b/esp32c6/src/extmem/l2_cache_acs_cnt_ctrl.rs
@@ -118,79 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_CNT_CTRL")
-            .field(
-                "l2_ibus0_cnt_ena",
-                &format_args!("{}", self.l2_ibus0_cnt_ena().bit()),
-            )
-            .field(
-                "l2_ibus1_cnt_ena",
-                &format_args!("{}", self.l2_ibus1_cnt_ena().bit()),
-            )
-            .field(
-                "l2_ibus2_cnt_ena",
-                &format_args!("{}", self.l2_ibus2_cnt_ena().bit()),
-            )
-            .field(
-                "l2_ibus3_cnt_ena",
-                &format_args!("{}", self.l2_ibus3_cnt_ena().bit()),
-            )
-            .field(
-                "l2_dbus0_cnt_ena",
-                &format_args!("{}", self.l2_dbus0_cnt_ena().bit()),
-            )
-            .field(
-                "l2_dbus1_cnt_ena",
-                &format_args!("{}", self.l2_dbus1_cnt_ena().bit()),
-            )
-            .field(
-                "l2_dbus2_cnt_ena",
-                &format_args!("{}", self.l2_dbus2_cnt_ena().bit()),
-            )
-            .field(
-                "l2_dbus3_cnt_ena",
-                &format_args!("{}", self.l2_dbus3_cnt_ena().bit()),
-            )
-            .field(
-                "l2_ibus0_cnt_clr",
-                &format_args!("{}", self.l2_ibus0_cnt_clr().bit()),
-            )
-            .field(
-                "l2_ibus1_cnt_clr",
-                &format_args!("{}", self.l2_ibus1_cnt_clr().bit()),
-            )
-            .field(
-                "l2_ibus2_cnt_clr",
-                &format_args!("{}", self.l2_ibus2_cnt_clr().bit()),
-            )
-            .field(
-                "l2_ibus3_cnt_clr",
-                &format_args!("{}", self.l2_ibus3_cnt_clr().bit()),
-            )
-            .field(
-                "l2_dbus0_cnt_clr",
-                &format_args!("{}", self.l2_dbus0_cnt_clr().bit()),
-            )
-            .field(
-                "l2_dbus1_cnt_clr",
-                &format_args!("{}", self.l2_dbus1_cnt_clr().bit()),
-            )
-            .field(
-                "l2_dbus2_cnt_clr",
-                &format_args!("{}", self.l2_dbus2_cnt_clr().bit()),
-            )
-            .field(
-                "l2_dbus3_cnt_clr",
-                &format_args!("{}", self.l2_dbus3_cnt_clr().bit()),
-            )
+            .field("l2_ibus0_cnt_ena", &self.l2_ibus0_cnt_ena())
+            .field("l2_ibus1_cnt_ena", &self.l2_ibus1_cnt_ena())
+            .field("l2_ibus2_cnt_ena", &self.l2_ibus2_cnt_ena())
+            .field("l2_ibus3_cnt_ena", &self.l2_ibus3_cnt_ena())
+            .field("l2_dbus0_cnt_ena", &self.l2_dbus0_cnt_ena())
+            .field("l2_dbus1_cnt_ena", &self.l2_dbus1_cnt_ena())
+            .field("l2_dbus2_cnt_ena", &self.l2_dbus2_cnt_ena())
+            .field("l2_dbus3_cnt_ena", &self.l2_dbus3_cnt_ena())
+            .field("l2_ibus0_cnt_clr", &self.l2_ibus0_cnt_clr())
+            .field("l2_ibus1_cnt_clr", &self.l2_ibus1_cnt_clr())
+            .field("l2_ibus2_cnt_clr", &self.l2_ibus2_cnt_clr())
+            .field("l2_ibus3_cnt_clr", &self.l2_ibus3_cnt_clr())
+            .field("l2_dbus0_cnt_clr", &self.l2_dbus0_cnt_clr())
+            .field("l2_dbus1_cnt_clr", &self.l2_dbus1_cnt_clr())
+            .field("l2_dbus2_cnt_clr", &self.l2_dbus2_cnt_clr())
+            .field("l2_dbus3_cnt_clr", &self.l2_dbus3_cnt_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_CNT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Access Counter enable and clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_ACS_CNT_CTRL_SPEC;
 impl crate::RegisterSpec for L2_CACHE_ACS_CNT_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_acs_cnt_int_clr.rs b/esp32c6/src/extmem/l2_cache_acs_cnt_int_clr.rs
index f4f2a580dd..6c2cf1b2b1 100644
--- a/esp32c6/src/extmem/l2_cache_acs_cnt_int_clr.rs
+++ b/esp32c6/src/extmem/l2_cache_acs_cnt_int_clr.rs
@@ -62,47 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_CNT_INT_CLR")
-            .field(
-                "l2_ibus0_ovf_int_clr",
-                &format_args!("{}", self.l2_ibus0_ovf_int_clr().bit()),
-            )
-            .field(
-                "l2_ibus1_ovf_int_clr",
-                &format_args!("{}", self.l2_ibus1_ovf_int_clr().bit()),
-            )
-            .field(
-                "l2_ibus2_ovf_int_clr",
-                &format_args!("{}", self.l2_ibus2_ovf_int_clr().bit()),
-            )
-            .field(
-                "l2_ibus3_ovf_int_clr",
-                &format_args!("{}", self.l2_ibus3_ovf_int_clr().bit()),
-            )
-            .field(
-                "l2_dbus0_ovf_int_clr",
-                &format_args!("{}", self.l2_dbus0_ovf_int_clr().bit()),
-            )
-            .field(
-                "l2_dbus1_ovf_int_clr",
-                &format_args!("{}", self.l2_dbus1_ovf_int_clr().bit()),
-            )
-            .field(
-                "l2_dbus2_ovf_int_clr",
-                &format_args!("{}", self.l2_dbus2_ovf_int_clr().bit()),
-            )
-            .field(
-                "l2_dbus3_ovf_int_clr",
-                &format_args!("{}", self.l2_dbus3_ovf_int_clr().bit()),
-            )
+            .field("l2_ibus0_ovf_int_clr", &self.l2_ibus0_ovf_int_clr())
+            .field("l2_ibus1_ovf_int_clr", &self.l2_ibus1_ovf_int_clr())
+            .field("l2_ibus2_ovf_int_clr", &self.l2_ibus2_ovf_int_clr())
+            .field("l2_ibus3_ovf_int_clr", &self.l2_ibus3_ovf_int_clr())
+            .field("l2_dbus0_ovf_int_clr", &self.l2_dbus0_ovf_int_clr())
+            .field("l2_dbus1_ovf_int_clr", &self.l2_dbus1_ovf_int_clr())
+            .field("l2_dbus2_ovf_int_clr", &self.l2_dbus2_ovf_int_clr())
+            .field("l2_dbus3_ovf_int_clr", &self.l2_dbus3_ovf_int_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_CNT_INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Access Counter Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_clr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_ACS_CNT_INT_CLR_SPEC;
 impl crate::RegisterSpec for L2_CACHE_ACS_CNT_INT_CLR_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_acs_cnt_int_ena.rs b/esp32c6/src/extmem/l2_cache_acs_cnt_int_ena.rs
index d8ca2935d5..cac3d47d28 100644
--- a/esp32c6/src/extmem/l2_cache_acs_cnt_int_ena.rs
+++ b/esp32c6/src/extmem/l2_cache_acs_cnt_int_ena.rs
@@ -62,47 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_CNT_INT_ENA")
-            .field(
-                "l2_ibus0_ovf_int_ena",
-                &format_args!("{}", self.l2_ibus0_ovf_int_ena().bit()),
-            )
-            .field(
-                "l2_ibus1_ovf_int_ena",
-                &format_args!("{}", self.l2_ibus1_ovf_int_ena().bit()),
-            )
-            .field(
-                "l2_ibus2_ovf_int_ena",
-                &format_args!("{}", self.l2_ibus2_ovf_int_ena().bit()),
-            )
-            .field(
-                "l2_ibus3_ovf_int_ena",
-                &format_args!("{}", self.l2_ibus3_ovf_int_ena().bit()),
-            )
-            .field(
-                "l2_dbus0_ovf_int_ena",
-                &format_args!("{}", self.l2_dbus0_ovf_int_ena().bit()),
-            )
-            .field(
-                "l2_dbus1_ovf_int_ena",
-                &format_args!("{}", self.l2_dbus1_ovf_int_ena().bit()),
-            )
-            .field(
-                "l2_dbus2_ovf_int_ena",
-                &format_args!("{}", self.l2_dbus2_ovf_int_ena().bit()),
-            )
-            .field(
-                "l2_dbus3_ovf_int_ena",
-                &format_args!("{}", self.l2_dbus3_ovf_int_ena().bit()),
-            )
+            .field("l2_ibus0_ovf_int_ena", &self.l2_ibus0_ovf_int_ena())
+            .field("l2_ibus1_ovf_int_ena", &self.l2_ibus1_ovf_int_ena())
+            .field("l2_ibus2_ovf_int_ena", &self.l2_ibus2_ovf_int_ena())
+            .field("l2_ibus3_ovf_int_ena", &self.l2_ibus3_ovf_int_ena())
+            .field("l2_dbus0_ovf_int_ena", &self.l2_dbus0_ovf_int_ena())
+            .field("l2_dbus1_ovf_int_ena", &self.l2_dbus1_ovf_int_ena())
+            .field("l2_dbus2_ovf_int_ena", &self.l2_dbus2_ovf_int_ena())
+            .field("l2_dbus3_ovf_int_ena", &self.l2_dbus3_ovf_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_CNT_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Access Counter Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_ena::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_ACS_CNT_INT_ENA_SPEC;
 impl crate::RegisterSpec for L2_CACHE_ACS_CNT_INT_ENA_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_acs_cnt_int_raw.rs b/esp32c6/src/extmem/l2_cache_acs_cnt_int_raw.rs
index 797894f0c3..4e996ec8b5 100644
--- a/esp32c6/src/extmem/l2_cache_acs_cnt_int_raw.rs
+++ b/esp32c6/src/extmem/l2_cache_acs_cnt_int_raw.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_CNT_INT_RAW")
-            .field(
-                "l2_ibus0_ovf_int_raw",
-                &format_args!("{}", self.l2_ibus0_ovf_int_raw().bit()),
-            )
-            .field(
-                "l2_ibus1_ovf_int_raw",
-                &format_args!("{}", self.l2_ibus1_ovf_int_raw().bit()),
-            )
-            .field(
-                "l2_ibus2_ovf_int_raw",
-                &format_args!("{}", self.l2_ibus2_ovf_int_raw().bit()),
-            )
-            .field(
-                "l2_ibus3_ovf_int_raw",
-                &format_args!("{}", self.l2_ibus3_ovf_int_raw().bit()),
-            )
-            .field(
-                "l2_dbus0_ovf_int_raw",
-                &format_args!("{}", self.l2_dbus0_ovf_int_raw().bit()),
-            )
-            .field(
-                "l2_dbus1_ovf_int_raw",
-                &format_args!("{}", self.l2_dbus1_ovf_int_raw().bit()),
-            )
-            .field(
-                "l2_dbus2_ovf_int_raw",
-                &format_args!("{}", self.l2_dbus2_ovf_int_raw().bit()),
-            )
-            .field(
-                "l2_dbus3_ovf_int_raw",
-                &format_args!("{}", self.l2_dbus3_ovf_int_raw().bit()),
-            )
+            .field("l2_ibus0_ovf_int_raw", &self.l2_ibus0_ovf_int_raw())
+            .field("l2_ibus1_ovf_int_raw", &self.l2_ibus1_ovf_int_raw())
+            .field("l2_ibus2_ovf_int_raw", &self.l2_ibus2_ovf_int_raw())
+            .field("l2_ibus3_ovf_int_raw", &self.l2_ibus3_ovf_int_raw())
+            .field("l2_dbus0_ovf_int_raw", &self.l2_dbus0_ovf_int_raw())
+            .field("l2_dbus1_ovf_int_raw", &self.l2_dbus1_ovf_int_raw())
+            .field("l2_dbus2_ovf_int_raw", &self.l2_dbus2_ovf_int_raw())
+            .field("l2_dbus3_ovf_int_raw", &self.l2_dbus3_ovf_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_CNT_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l2_cache_acs_cnt_int_st.rs b/esp32c6/src/extmem/l2_cache_acs_cnt_int_st.rs
index 1093680c5d..abef66191c 100644
--- a/esp32c6/src/extmem/l2_cache_acs_cnt_int_st.rs
+++ b/esp32c6/src/extmem/l2_cache_acs_cnt_int_st.rs
@@ -62,47 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_CNT_INT_ST")
-            .field(
-                "l2_ibus0_ovf_int_st",
-                &format_args!("{}", self.l2_ibus0_ovf_int_st().bit()),
-            )
-            .field(
-                "l2_ibus1_ovf_int_st",
-                &format_args!("{}", self.l2_ibus1_ovf_int_st().bit()),
-            )
-            .field(
-                "l2_ibus2_ovf_int_st",
-                &format_args!("{}", self.l2_ibus2_ovf_int_st().bit()),
-            )
-            .field(
-                "l2_ibus3_ovf_int_st",
-                &format_args!("{}", self.l2_ibus3_ovf_int_st().bit()),
-            )
-            .field(
-                "l2_dbus0_ovf_int_st",
-                &format_args!("{}", self.l2_dbus0_ovf_int_st().bit()),
-            )
-            .field(
-                "l2_dbus1_ovf_int_st",
-                &format_args!("{}", self.l2_dbus1_ovf_int_st().bit()),
-            )
-            .field(
-                "l2_dbus2_ovf_int_st",
-                &format_args!("{}", self.l2_dbus2_ovf_int_st().bit()),
-            )
-            .field(
-                "l2_dbus3_ovf_int_st",
-                &format_args!("{}", self.l2_dbus3_ovf_int_st().bit()),
-            )
+            .field("l2_ibus0_ovf_int_st", &self.l2_ibus0_ovf_int_st())
+            .field("l2_ibus1_ovf_int_st", &self.l2_ibus1_ovf_int_st())
+            .field("l2_ibus2_ovf_int_st", &self.l2_ibus2_ovf_int_st())
+            .field("l2_ibus3_ovf_int_st", &self.l2_ibus3_ovf_int_st())
+            .field("l2_dbus0_ovf_int_st", &self.l2_dbus0_ovf_int_st())
+            .field("l2_dbus1_ovf_int_st", &self.l2_dbus1_ovf_int_st())
+            .field("l2_dbus2_ovf_int_st", &self.l2_dbus2_ovf_int_st())
+            .field("l2_dbus3_ovf_int_st", &self.l2_dbus3_ovf_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_CNT_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Access Counter Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_ACS_CNT_INT_ST_SPEC;
 impl crate::RegisterSpec for L2_CACHE_ACS_CNT_INT_ST_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_acs_fail_addr.rs b/esp32c6/src/extmem/l2_cache_acs_fail_addr.rs
index b2e7fe8853..4657ca4e74 100644
--- a/esp32c6/src/extmem/l2_cache_acs_fail_addr.rs
+++ b/esp32c6/src/extmem/l2_cache_acs_fail_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_FAIL_ADDR")
-            .field(
-                "l2_cache_fail_addr",
-                &format_args!("{}", self.l2_cache_fail_addr().bits()),
-            )
+            .field("l2_cache_fail_addr", &self.l2_cache_fail_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_FAIL_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_ACS_FAIL_ADDR_SPEC;
 impl crate::RegisterSpec for L2_CACHE_ACS_FAIL_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_acs_fail_id_attr.rs b/esp32c6/src/extmem/l2_cache_acs_fail_id_attr.rs
index af04853018..119d44460f 100644
--- a/esp32c6/src/extmem/l2_cache_acs_fail_id_attr.rs
+++ b/esp32c6/src/extmem/l2_cache_acs_fail_id_attr.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_FAIL_ID_ATTR")
-            .field(
-                "l2_cache_fail_id",
-                &format_args!("{}", self.l2_cache_fail_id().bits()),
-            )
-            .field(
-                "l2_cache_fail_attr",
-                &format_args!("{}", self.l2_cache_fail_attr().bits()),
-            )
+            .field("l2_cache_fail_id", &self.l2_cache_fail_id())
+            .field("l2_cache_fail_attr", &self.l2_cache_fail_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_FAIL_ID_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_id_attr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_ACS_FAIL_ID_ATTR_SPEC;
 impl crate::RegisterSpec for L2_CACHE_ACS_FAIL_ID_ATTR_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_acs_fail_int_clr.rs b/esp32c6/src/extmem/l2_cache_acs_fail_int_clr.rs
index 191d822bb0..fb5fd9a378 100644
--- a/esp32c6/src/extmem/l2_cache_acs_fail_int_clr.rs
+++ b/esp32c6/src/extmem/l2_cache_acs_fail_int_clr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_FAIL_INT_CLR")
-            .field(
-                "l2_cache_fail_int_clr",
-                &format_args!("{}", self.l2_cache_fail_int_clr().bit()),
-            )
+            .field("l2_cache_fail_int_clr", &self.l2_cache_fail_int_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_FAIL_INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache Access Fail Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_int_clr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_ACS_FAIL_INT_CLR_SPEC;
 impl crate::RegisterSpec for L2_CACHE_ACS_FAIL_INT_CLR_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_acs_fail_int_ena.rs b/esp32c6/src/extmem/l2_cache_acs_fail_int_ena.rs
index 305153de16..383b4d21d0 100644
--- a/esp32c6/src/extmem/l2_cache_acs_fail_int_ena.rs
+++ b/esp32c6/src/extmem/l2_cache_acs_fail_int_ena.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_FAIL_INT_ENA")
-            .field(
-                "l2_cache_fail_int_ena",
-                &format_args!("{}", self.l2_cache_fail_int_ena().bit()),
-            )
+            .field("l2_cache_fail_int_ena", &self.l2_cache_fail_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_FAIL_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Access Fail Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_int_ena::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_ACS_FAIL_INT_ENA_SPEC;
 impl crate::RegisterSpec for L2_CACHE_ACS_FAIL_INT_ENA_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_acs_fail_int_raw.rs b/esp32c6/src/extmem/l2_cache_acs_fail_int_raw.rs
index 72775212b1..3a16ca6106 100644
--- a/esp32c6/src/extmem/l2_cache_acs_fail_int_raw.rs
+++ b/esp32c6/src/extmem/l2_cache_acs_fail_int_raw.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_FAIL_INT_RAW")
-            .field(
-                "l2_cache_fail_int_raw",
-                &format_args!("{}", self.l2_cache_fail_int_raw().bit()),
-            )
+            .field("l2_cache_fail_int_raw", &self.l2_cache_fail_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_FAIL_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 5 - The raw bit of the interrupt of access fail that occurs in L2-Cache."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l2_cache_acs_fail_int_st.rs b/esp32c6/src/extmem/l2_cache_acs_fail_int_st.rs
index fa8e8f93ac..94c716e5b1 100644
--- a/esp32c6/src/extmem/l2_cache_acs_fail_int_st.rs
+++ b/esp32c6/src/extmem/l2_cache_acs_fail_int_st.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_FAIL_INT_ST")
-            .field(
-                "l2_cache_fail_int_st",
-                &format_args!("{}", self.l2_cache_fail_int_st().bit()),
-            )
+            .field("l2_cache_fail_int_st", &self.l2_cache_fail_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_FAIL_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_ACS_FAIL_INT_ST_SPEC;
 impl crate::RegisterSpec for L2_CACHE_ACS_FAIL_INT_ST_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_autoload_buf_clr_ctrl.rs b/esp32c6/src/extmem/l2_cache_autoload_buf_clr_ctrl.rs
index ec63370ab7..f4e8f75eca 100644
--- a/esp32c6/src/extmem/l2_cache_autoload_buf_clr_ctrl.rs
+++ b/esp32c6/src/extmem/l2_cache_autoload_buf_clr_ctrl.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_AUTOLOAD_BUF_CLR_CTRL")
-            .field(
-                "l2_cache_ald_buf_clr",
-                &format_args!("{}", self.l2_cache_ald_buf_clr().bit()),
-            )
+            .field("l2_cache_ald_buf_clr", &self.l2_cache_ald_buf_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Autoload buffer clear control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_buf_clr_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC;
 impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_autoload_ctrl.rs b/esp32c6/src/extmem/l2_cache_autoload_ctrl.rs
index 940d2ebe09..271626b8f0 100644
--- a/esp32c6/src/extmem/l2_cache_autoload_ctrl.rs
+++ b/esp32c6/src/extmem/l2_cache_autoload_ctrl.rs
@@ -69,51 +69,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_AUTOLOAD_CTRL")
-            .field(
-                "l2_cache_autoload_ena",
-                &format_args!("{}", self.l2_cache_autoload_ena().bit()),
-            )
-            .field(
-                "l2_cache_autoload_done",
-                &format_args!("{}", self.l2_cache_autoload_done().bit()),
-            )
-            .field(
-                "l2_cache_autoload_order",
-                &format_args!("{}", self.l2_cache_autoload_order().bit()),
-            )
+            .field("l2_cache_autoload_ena", &self.l2_cache_autoload_ena())
+            .field("l2_cache_autoload_done", &self.l2_cache_autoload_done())
+            .field("l2_cache_autoload_order", &self.l2_cache_autoload_order())
             .field(
                 "l2_cache_autoload_trigger_mode",
-                &format_args!("{}", self.l2_cache_autoload_trigger_mode().bits()),
+                &self.l2_cache_autoload_trigger_mode(),
             )
             .field(
                 "l2_cache_autoload_sct0_ena",
-                &format_args!("{}", self.l2_cache_autoload_sct0_ena().bit()),
+                &self.l2_cache_autoload_sct0_ena(),
             )
             .field(
                 "l2_cache_autoload_sct1_ena",
-                &format_args!("{}", self.l2_cache_autoload_sct1_ena().bit()),
+                &self.l2_cache_autoload_sct1_ena(),
             )
             .field(
                 "l2_cache_autoload_sct2_ena",
-                &format_args!("{}", self.l2_cache_autoload_sct2_ena().bit()),
+                &self.l2_cache_autoload_sct2_ena(),
             )
             .field(
                 "l2_cache_autoload_sct3_ena",
-                &format_args!("{}", self.l2_cache_autoload_sct3_ena().bit()),
-            )
-            .field(
-                "l2_cache_autoload_rgid",
-                &format_args!("{}", self.l2_cache_autoload_rgid().bits()),
+                &self.l2_cache_autoload_sct3_ena(),
             )
+            .field("l2_cache_autoload_rgid", &self.l2_cache_autoload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_AUTOLOAD_CTRL_SPEC;
 impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_autoload_sct0_addr.rs b/esp32c6/src/extmem/l2_cache_autoload_sct0_addr.rs
index 74b4de7c54..468e6d973c 100644
--- a/esp32c6/src/extmem/l2_cache_autoload_sct0_addr.rs
+++ b/esp32c6/src/extmem/l2_cache_autoload_sct0_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT0_ADDR")
             .field(
                 "l2_cache_autoload_sct0_addr",
-                &format_args!("{}", self.l2_cache_autoload_sct0_addr().bits()),
+                &self.l2_cache_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct0_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_AUTOLOAD_SCT0_ADDR_SPEC;
 impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT0_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_autoload_sct0_size.rs b/esp32c6/src/extmem/l2_cache_autoload_sct0_size.rs
index 2ea859e5b5..a408341c29 100644
--- a/esp32c6/src/extmem/l2_cache_autoload_sct0_size.rs
+++ b/esp32c6/src/extmem/l2_cache_autoload_sct0_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT0_SIZE")
             .field(
                 "l2_cache_autoload_sct0_size",
-                &format_args!("{}", self.l2_cache_autoload_sct0_size().bits()),
+                &self.l2_cache_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct0_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_AUTOLOAD_SCT0_SIZE_SPEC;
 impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT0_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_autoload_sct1_addr.rs b/esp32c6/src/extmem/l2_cache_autoload_sct1_addr.rs
index b2c43e9435..1cfd206057 100644
--- a/esp32c6/src/extmem/l2_cache_autoload_sct1_addr.rs
+++ b/esp32c6/src/extmem/l2_cache_autoload_sct1_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT1_ADDR")
             .field(
                 "l2_cache_autoload_sct1_addr",
-                &format_args!("{}", self.l2_cache_autoload_sct1_addr().bits()),
+                &self.l2_cache_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct1_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_AUTOLOAD_SCT1_ADDR_SPEC;
 impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT1_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_autoload_sct1_size.rs b/esp32c6/src/extmem/l2_cache_autoload_sct1_size.rs
index a18884e30c..337eeaa56f 100644
--- a/esp32c6/src/extmem/l2_cache_autoload_sct1_size.rs
+++ b/esp32c6/src/extmem/l2_cache_autoload_sct1_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT1_SIZE")
             .field(
                 "l2_cache_autoload_sct1_size",
-                &format_args!("{}", self.l2_cache_autoload_sct1_size().bits()),
+                &self.l2_cache_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct1_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_AUTOLOAD_SCT1_SIZE_SPEC;
 impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT1_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_autoload_sct2_addr.rs b/esp32c6/src/extmem/l2_cache_autoload_sct2_addr.rs
index d0b05932a3..5403ce1727 100644
--- a/esp32c6/src/extmem/l2_cache_autoload_sct2_addr.rs
+++ b/esp32c6/src/extmem/l2_cache_autoload_sct2_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT2_ADDR")
             .field(
                 "l2_cache_autoload_sct2_addr",
-                &format_args!("{}", self.l2_cache_autoload_sct2_addr().bits()),
+                &self.l2_cache_autoload_sct2_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache autoload section 2 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct2_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_AUTOLOAD_SCT2_ADDR_SPEC;
 impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT2_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_autoload_sct2_size.rs b/esp32c6/src/extmem/l2_cache_autoload_sct2_size.rs
index e8ef7ca583..bec4ffbd8a 100644
--- a/esp32c6/src/extmem/l2_cache_autoload_sct2_size.rs
+++ b/esp32c6/src/extmem/l2_cache_autoload_sct2_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT2_SIZE")
             .field(
                 "l2_cache_autoload_sct2_size",
-                &format_args!("{}", self.l2_cache_autoload_sct2_size().bits()),
+                &self.l2_cache_autoload_sct2_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT2_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache autoload section 2 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct2_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_AUTOLOAD_SCT2_SIZE_SPEC;
 impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT2_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_autoload_sct3_addr.rs b/esp32c6/src/extmem/l2_cache_autoload_sct3_addr.rs
index 2d26b0ce51..e436d75eed 100644
--- a/esp32c6/src/extmem/l2_cache_autoload_sct3_addr.rs
+++ b/esp32c6/src/extmem/l2_cache_autoload_sct3_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT3_ADDR")
             .field(
                 "l2_cache_autoload_sct3_addr",
-                &format_args!("{}", self.l2_cache_autoload_sct3_addr().bits()),
+                &self.l2_cache_autoload_sct3_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache autoload section 3 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct3_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_AUTOLOAD_SCT3_ADDR_SPEC;
 impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT3_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_autoload_sct3_size.rs b/esp32c6/src/extmem/l2_cache_autoload_sct3_size.rs
index 41545a4f37..d00b62cf9b 100644
--- a/esp32c6/src/extmem/l2_cache_autoload_sct3_size.rs
+++ b/esp32c6/src/extmem/l2_cache_autoload_sct3_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT3_SIZE")
             .field(
                 "l2_cache_autoload_sct3_size",
-                &format_args!("{}", self.l2_cache_autoload_sct3_size().bits()),
+                &self.l2_cache_autoload_sct3_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT3_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache autoload section 3 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_autoload_sct3_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_AUTOLOAD_SCT3_SIZE_SPEC;
 impl crate::RegisterSpec for L2_CACHE_AUTOLOAD_SCT3_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_blocksize_conf.rs b/esp32c6/src/extmem/l2_cache_blocksize_conf.rs
index 7bcd68cae2..4ecc379754 100644
--- a/esp32c6/src/extmem/l2_cache_blocksize_conf.rs
+++ b/esp32c6/src/extmem/l2_cache_blocksize_conf.rs
@@ -48,39 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_BLOCKSIZE_CONF")
-            .field(
-                "l2_cache_blocksize_8",
-                &format_args!("{}", self.l2_cache_blocksize_8().bit()),
-            )
-            .field(
-                "l2_cache_blocksize_16",
-                &format_args!("{}", self.l2_cache_blocksize_16().bit()),
-            )
-            .field(
-                "l2_cache_blocksize_32",
-                &format_args!("{}", self.l2_cache_blocksize_32().bit()),
-            )
-            .field(
-                "l2_cache_blocksize_64",
-                &format_args!("{}", self.l2_cache_blocksize_64().bit()),
-            )
-            .field(
-                "l2_cache_blocksize_128",
-                &format_args!("{}", self.l2_cache_blocksize_128().bit()),
-            )
-            .field(
-                "l2_cache_blocksize_256",
-                &format_args!("{}", self.l2_cache_blocksize_256().bit()),
-            )
+            .field("l2_cache_blocksize_8", &self.l2_cache_blocksize_8())
+            .field("l2_cache_blocksize_16", &self.l2_cache_blocksize_16())
+            .field("l2_cache_blocksize_32", &self.l2_cache_blocksize_32())
+            .field("l2_cache_blocksize_64", &self.l2_cache_blocksize_64())
+            .field("l2_cache_blocksize_128", &self.l2_cache_blocksize_128())
+            .field("l2_cache_blocksize_256", &self.l2_cache_blocksize_256())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_BLOCKSIZE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache BlockSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_blocksize_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_BLOCKSIZE_CONF_SPEC;
 impl crate::RegisterSpec for L2_CACHE_BLOCKSIZE_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_cachesize_conf.rs b/esp32c6/src/extmem/l2_cache_cachesize_conf.rs
index d620b88b6c..52961dc1b6 100644
--- a/esp32c6/src/extmem/l2_cache_cachesize_conf.rs
+++ b/esp32c6/src/extmem/l2_cache_cachesize_conf.rs
@@ -97,67 +97,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_CACHESIZE_CONF")
-            .field(
-                "l2_cache_cachesize_1k",
-                &format_args!("{}", self.l2_cache_cachesize_1k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_2k",
-                &format_args!("{}", self.l2_cache_cachesize_2k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_4k",
-                &format_args!("{}", self.l2_cache_cachesize_4k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_8k",
-                &format_args!("{}", self.l2_cache_cachesize_8k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_16k",
-                &format_args!("{}", self.l2_cache_cachesize_16k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_32k",
-                &format_args!("{}", self.l2_cache_cachesize_32k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_64k",
-                &format_args!("{}", self.l2_cache_cachesize_64k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_128k",
-                &format_args!("{}", self.l2_cache_cachesize_128k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_256k",
-                &format_args!("{}", self.l2_cache_cachesize_256k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_512k",
-                &format_args!("{}", self.l2_cache_cachesize_512k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_1024k",
-                &format_args!("{}", self.l2_cache_cachesize_1024k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_2048k",
-                &format_args!("{}", self.l2_cache_cachesize_2048k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_4096k",
-                &format_args!("{}", self.l2_cache_cachesize_4096k().bit()),
-            )
+            .field("l2_cache_cachesize_1k", &self.l2_cache_cachesize_1k())
+            .field("l2_cache_cachesize_2k", &self.l2_cache_cachesize_2k())
+            .field("l2_cache_cachesize_4k", &self.l2_cache_cachesize_4k())
+            .field("l2_cache_cachesize_8k", &self.l2_cache_cachesize_8k())
+            .field("l2_cache_cachesize_16k", &self.l2_cache_cachesize_16k())
+            .field("l2_cache_cachesize_32k", &self.l2_cache_cachesize_32k())
+            .field("l2_cache_cachesize_64k", &self.l2_cache_cachesize_64k())
+            .field("l2_cache_cachesize_128k", &self.l2_cache_cachesize_128k())
+            .field("l2_cache_cachesize_256k", &self.l2_cache_cachesize_256k())
+            .field("l2_cache_cachesize_512k", &self.l2_cache_cachesize_512k())
+            .field("l2_cache_cachesize_1024k", &self.l2_cache_cachesize_1024k())
+            .field("l2_cache_cachesize_2048k", &self.l2_cache_cachesize_2048k())
+            .field("l2_cache_cachesize_4096k", &self.l2_cache_cachesize_4096k())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_CACHESIZE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache CacheSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_cachesize_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_CACHESIZE_CONF_SPEC;
 impl crate::RegisterSpec for L2_CACHE_CACHESIZE_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_ctrl.rs b/esp32c6/src/extmem/l2_cache_ctrl.rs
index b678baec41..fb0f389287 100644
--- a/esp32c6/src/extmem/l2_cache_ctrl.rs
+++ b/esp32c6/src/extmem/l2_cache_ctrl.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_CTRL")
-            .field(
-                "l2_cache_shut_dma",
-                &format_args!("{}", self.l2_cache_shut_dma().bit()),
-            )
-            .field(
-                "l2_cache_undef_op",
-                &format_args!("{}", self.l2_cache_undef_op().bits()),
-            )
+            .field("l2_cache_shut_dma", &self.l2_cache_shut_dma())
+            .field("l2_cache_undef_op", &self.l2_cache_undef_op())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache(L2-Cache) control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_CTRL_SPEC;
 impl crate::RegisterSpec for L2_CACHE_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_data_mem_acs_conf.rs b/esp32c6/src/extmem/l2_cache_data_mem_acs_conf.rs
index a22085a5ce..8ffeb5bf9f 100644
--- a/esp32c6/src/extmem/l2_cache_data_mem_acs_conf.rs
+++ b/esp32c6/src/extmem/l2_cache_data_mem_acs_conf.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_DATA_MEM_ACS_CONF")
-            .field(
-                "l2_cache_data_mem_rd_en",
-                &format_args!("{}", self.l2_cache_data_mem_rd_en().bit()),
-            )
-            .field(
-                "l2_cache_data_mem_wr_en",
-                &format_args!("{}", self.l2_cache_data_mem_wr_en().bit()),
-            )
+            .field("l2_cache_data_mem_rd_en", &self.l2_cache_data_mem_rd_en())
+            .field("l2_cache_data_mem_wr_en", &self.l2_cache_data_mem_wr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_DATA_MEM_ACS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache data memory access configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_data_mem_acs_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_DATA_MEM_ACS_CONF_SPEC;
 impl crate::RegisterSpec for L2_CACHE_DATA_MEM_ACS_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_data_mem_power_ctrl.rs b/esp32c6/src/extmem/l2_cache_data_mem_power_ctrl.rs
index ff939ece33..3e33425665 100644
--- a/esp32c6/src/extmem/l2_cache_data_mem_power_ctrl.rs
+++ b/esp32c6/src/extmem/l2_cache_data_mem_power_ctrl.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_DATA_MEM_POWER_CTRL")
             .field(
                 "l2_cache_data_mem_force_on",
-                &format_args!("{}", self.l2_cache_data_mem_force_on().bit()),
+                &self.l2_cache_data_mem_force_on(),
             )
             .field(
                 "l2_cache_data_mem_force_pd",
-                &format_args!("{}", self.l2_cache_data_mem_force_pd().bit()),
+                &self.l2_cache_data_mem_force_pd(),
             )
             .field(
                 "l2_cache_data_mem_force_pu",
-                &format_args!("{}", self.l2_cache_data_mem_force_pu().bit()),
+                &self.l2_cache_data_mem_force_pu(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_DATA_MEM_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache data memory power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_data_mem_power_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_DATA_MEM_POWER_CTRL_SPEC;
 impl crate::RegisterSpec for L2_CACHE_DATA_MEM_POWER_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_debug_bus.rs b/esp32c6/src/extmem/l2_cache_debug_bus.rs
index 2ccfaee1d9..ca3e3f7301 100644
--- a/esp32c6/src/extmem/l2_cache_debug_bus.rs
+++ b/esp32c6/src/extmem/l2_cache_debug_bus.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_DEBUG_BUS")
-            .field(
-                "l2_cache_debug_bus",
-                &format_args!("{}", self.l2_cache_debug_bus().bits()),
-            )
+            .field("l2_cache_debug_bus", &self.l2_cache_debug_bus())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_DEBUG_BUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Tag/data memory content register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_debug_bus::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_DEBUG_BUS_SPEC;
 impl crate::RegisterSpec for L2_CACHE_DEBUG_BUS_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_freeze_ctrl.rs b/esp32c6/src/extmem/l2_cache_freeze_ctrl.rs
index 537375fcbd..a3357039d1 100644
--- a/esp32c6/src/extmem/l2_cache_freeze_ctrl.rs
+++ b/esp32c6/src/extmem/l2_cache_freeze_ctrl.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_FREEZE_CTRL")
-            .field(
-                "l2_cache_freeze_en",
-                &format_args!("{}", self.l2_cache_freeze_en().bit()),
-            )
-            .field(
-                "l2_cache_freeze_mode",
-                &format_args!("{}", self.l2_cache_freeze_mode().bit()),
-            )
-            .field(
-                "l2_cache_freeze_done",
-                &format_args!("{}", self.l2_cache_freeze_done().bit()),
-            )
+            .field("l2_cache_freeze_en", &self.l2_cache_freeze_en())
+            .field("l2_cache_freeze_mode", &self.l2_cache_freeze_mode())
+            .field("l2_cache_freeze_done", &self.l2_cache_freeze_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_FREEZE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Freeze control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_freeze_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_FREEZE_CTRL_SPEC;
 impl crate::RegisterSpec for L2_CACHE_FREEZE_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_object_ctrl.rs b/esp32c6/src/extmem/l2_cache_object_ctrl.rs
index ff34d26185..5454f0cf6a 100644
--- a/esp32c6/src/extmem/l2_cache_object_ctrl.rs
+++ b/esp32c6/src/extmem/l2_cache_object_ctrl.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_OBJECT_CTRL")
-            .field(
-                "l2_cache_tag_object",
-                &format_args!("{}", self.l2_cache_tag_object().bit()),
-            )
-            .field(
-                "l2_cache_mem_object",
-                &format_args!("{}", self.l2_cache_mem_object().bit()),
-            )
+            .field("l2_cache_tag_object", &self.l2_cache_tag_object())
+            .field("l2_cache_mem_object", &self.l2_cache_mem_object())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_OBJECT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Tag and Data memory Object control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_object_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_OBJECT_CTRL_SPEC;
 impl crate::RegisterSpec for L2_CACHE_OBJECT_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_preload_addr.rs b/esp32c6/src/extmem/l2_cache_preload_addr.rs
index 6143fb292b..41a21cb4ed 100644
--- a/esp32c6/src/extmem/l2_cache_preload_addr.rs
+++ b/esp32c6/src/extmem/l2_cache_preload_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_PRELOAD_ADDR")
-            .field(
-                "l2_cache_preload_addr",
-                &format_args!("{}", self.l2_cache_preload_addr().bits()),
-            )
+            .field("l2_cache_preload_addr", &self.l2_cache_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_preload_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_PRELOAD_ADDR_SPEC;
 impl crate::RegisterSpec for L2_CACHE_PRELOAD_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_preload_ctrl.rs b/esp32c6/src/extmem/l2_cache_preload_ctrl.rs
index 6b8ad9e125..09d60152d8 100644
--- a/esp32c6/src/extmem/l2_cache_preload_ctrl.rs
+++ b/esp32c6/src/extmem/l2_cache_preload_ctrl.rs
@@ -38,31 +38,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_PRELOAD_CTRL")
-            .field(
-                "l2_cache_preload_ena",
-                &format_args!("{}", self.l2_cache_preload_ena().bit()),
-            )
-            .field(
-                "l2_cache_preload_done",
-                &format_args!("{}", self.l2_cache_preload_done().bit()),
-            )
-            .field(
-                "l2_cache_preload_order",
-                &format_args!("{}", self.l2_cache_preload_order().bit()),
-            )
-            .field(
-                "l2_cache_preload_rgid",
-                &format_args!("{}", self.l2_cache_preload_rgid().bits()),
-            )
+            .field("l2_cache_preload_ena", &self.l2_cache_preload_ena())
+            .field("l2_cache_preload_done", &self.l2_cache_preload_done())
+            .field("l2_cache_preload_order", &self.l2_cache_preload_order())
+            .field("l2_cache_preload_rgid", &self.l2_cache_preload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l2_cache_preload_rst_ctrl.rs b/esp32c6/src/extmem/l2_cache_preload_rst_ctrl.rs
index c306b1509e..aba8d5b741 100644
--- a/esp32c6/src/extmem/l2_cache_preload_rst_ctrl.rs
+++ b/esp32c6/src/extmem/l2_cache_preload_rst_ctrl.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_PRELOAD_RST_CTRL")
-            .field(
-                "l2_cache_pld_rst",
-                &format_args!("{}", self.l2_cache_pld_rst().bit()),
-            )
+            .field("l2_cache_pld_rst", &self.l2_cache_pld_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOAD_RST_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Preload Reset control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_preload_rst_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_PRELOAD_RST_CTRL_SPEC;
 impl crate::RegisterSpec for L2_CACHE_PRELOAD_RST_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_preload_size.rs b/esp32c6/src/extmem/l2_cache_preload_size.rs
index d223dec151..7ab6a0fa3c 100644
--- a/esp32c6/src/extmem/l2_cache_preload_size.rs
+++ b/esp32c6/src/extmem/l2_cache_preload_size.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_PRELOAD_SIZE")
-            .field(
-                "l2_cache_preload_size",
-                &format_args!("{}", self.l2_cache_preload_size().bits()),
-            )
+            .field("l2_cache_preload_size", &self.l2_cache_preload_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_preload_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_PRELOAD_SIZE_SPEC;
 impl crate::RegisterSpec for L2_CACHE_PRELOAD_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_prelock_conf.rs b/esp32c6/src/extmem/l2_cache_prelock_conf.rs
index 26f1446b8d..2ae51347f2 100644
--- a/esp32c6/src/extmem/l2_cache_prelock_conf.rs
+++ b/esp32c6/src/extmem/l2_cache_prelock_conf.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_PRELOCK_CONF")
-            .field(
-                "l2_cache_prelock_sct0_en",
-                &format_args!("{}", self.l2_cache_prelock_sct0_en().bit()),
-            )
-            .field(
-                "l2_cache_prelock_sct1_en",
-                &format_args!("{}", self.l2_cache_prelock_sct1_en().bit()),
-            )
-            .field(
-                "l2_cache_prelock_rgid",
-                &format_args!("{}", self.l2_cache_prelock_rgid().bits()),
-            )
+            .field("l2_cache_prelock_sct0_en", &self.l2_cache_prelock_sct0_en())
+            .field("l2_cache_prelock_sct1_en", &self.l2_cache_prelock_sct1_en())
+            .field("l2_cache_prelock_rgid", &self.l2_cache_prelock_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOCK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_PRELOCK_CONF_SPEC;
 impl crate::RegisterSpec for L2_CACHE_PRELOCK_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_prelock_sct0_addr.rs b/esp32c6/src/extmem/l2_cache_prelock_sct0_addr.rs
index 18d6d2cd0b..55816c5fa5 100644
--- a/esp32c6/src/extmem/l2_cache_prelock_sct0_addr.rs
+++ b/esp32c6/src/extmem/l2_cache_prelock_sct0_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_PRELOCK_SCT0_ADDR")
             .field(
                 "l2_cache_prelock_sct0_addr",
-                &format_args!("{}", self.l2_cache_prelock_sct0_addr().bits()),
+                &self.l2_cache_prelock_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOCK_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_sct0_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_PRELOCK_SCT0_ADDR_SPEC;
 impl crate::RegisterSpec for L2_CACHE_PRELOCK_SCT0_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_prelock_sct1_addr.rs b/esp32c6/src/extmem/l2_cache_prelock_sct1_addr.rs
index 2ce7e096b9..6a18b26be5 100644
--- a/esp32c6/src/extmem/l2_cache_prelock_sct1_addr.rs
+++ b/esp32c6/src/extmem/l2_cache_prelock_sct1_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_PRELOCK_SCT1_ADDR")
             .field(
                 "l2_cache_prelock_sct1_addr",
-                &format_args!("{}", self.l2_cache_prelock_sct1_addr().bits()),
+                &self.l2_cache_prelock_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOCK_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_sct1_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_PRELOCK_SCT1_ADDR_SPEC;
 impl crate::RegisterSpec for L2_CACHE_PRELOCK_SCT1_ADDR_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_prelock_sct_size.rs b/esp32c6/src/extmem/l2_cache_prelock_sct_size.rs
index df4f4faf12..844c6da3a5 100644
--- a/esp32c6/src/extmem/l2_cache_prelock_sct_size.rs
+++ b/esp32c6/src/extmem/l2_cache_prelock_sct_size.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_PRELOCK_SCT_SIZE")
             .field(
                 "l2_cache_prelock_sct0_size",
-                &format_args!("{}", self.l2_cache_prelock_sct0_size().bits()),
+                &self.l2_cache_prelock_sct0_size(),
             )
             .field(
                 "l2_cache_prelock_sct1_size",
-                &format_args!("{}", self.l2_cache_prelock_sct1_size().bits()),
+                &self.l2_cache_prelock_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOCK_SCT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2 Cache prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_prelock_sct_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_PRELOCK_SCT_SIZE_SPEC;
 impl crate::RegisterSpec for L2_CACHE_PRELOCK_SCT_SIZE_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_sync_preload_exception.rs b/esp32c6/src/extmem/l2_cache_sync_preload_exception.rs
index 4abbabb042..40b97f77cf 100644
--- a/esp32c6/src/extmem/l2_cache_sync_preload_exception.rs
+++ b/esp32c6/src/extmem/l2_cache_sync_preload_exception.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_SYNC_PRELOAD_EXCEPTION")
-            .field(
-                "l2_cache_pld_err_code",
-                &format_args!("{}", self.l2_cache_pld_err_code().bits()),
-            )
+            .field("l2_cache_pld_err_code", &self.l2_cache_pld_err_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Sync/Preload Operation exception register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_exception::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC;
 impl crate::RegisterSpec for L2_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_sync_preload_int_clr.rs b/esp32c6/src/extmem/l2_cache_sync_preload_int_clr.rs
index 6e8c3fb70e..a16766d772 100644
--- a/esp32c6/src/extmem/l2_cache_sync_preload_int_clr.rs
+++ b/esp32c6/src/extmem/l2_cache_sync_preload_int_clr.rs
@@ -22,21 +22,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_SYNC_PRELOAD_INT_CLR")
             .field(
                 "l2_cache_pld_done_int_clr",
-                &format_args!("{}", self.l2_cache_pld_done_int_clr().bit()),
-            )
-            .field(
-                "l2_cache_pld_err_int_clr",
-                &format_args!("{}", self.l2_cache_pld_err_int_clr().bit()),
+                &self.l2_cache_pld_done_int_clr(),
             )
+            .field("l2_cache_pld_err_int_clr", &self.l2_cache_pld_err_int_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_SYNC_PRELOAD_INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Sync Preload operation Interrupt clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_int_clr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_SYNC_PRELOAD_INT_CLR_SPEC;
 impl crate::RegisterSpec for L2_CACHE_SYNC_PRELOAD_INT_CLR_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_sync_preload_int_ena.rs b/esp32c6/src/extmem/l2_cache_sync_preload_int_ena.rs
index 3373f8fd36..46e084ec20 100644
--- a/esp32c6/src/extmem/l2_cache_sync_preload_int_ena.rs
+++ b/esp32c6/src/extmem/l2_cache_sync_preload_int_ena.rs
@@ -22,21 +22,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_SYNC_PRELOAD_INT_ENA")
             .field(
                 "l2_cache_pld_done_int_ena",
-                &format_args!("{}", self.l2_cache_pld_done_int_ena().bit()),
-            )
-            .field(
-                "l2_cache_pld_err_int_ena",
-                &format_args!("{}", self.l2_cache_pld_err_int_ena().bit()),
+                &self.l2_cache_pld_done_int_ena(),
             )
+            .field("l2_cache_pld_err_int_ena", &self.l2_cache_pld_err_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_SYNC_PRELOAD_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache Access Fail Interrupt enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_int_ena::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_SYNC_PRELOAD_INT_ENA_SPEC;
 impl crate::RegisterSpec for L2_CACHE_SYNC_PRELOAD_INT_ENA_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_sync_preload_int_raw.rs b/esp32c6/src/extmem/l2_cache_sync_preload_int_raw.rs
index 0d948e61d0..b1da7ca8e4 100644
--- a/esp32c6/src/extmem/l2_cache_sync_preload_int_raw.rs
+++ b/esp32c6/src/extmem/l2_cache_sync_preload_int_raw.rs
@@ -28,21 +28,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_SYNC_PRELOAD_INT_RAW")
             .field(
                 "l2_cache_pld_done_int_raw",
-                &format_args!("{}", self.l2_cache_pld_done_int_raw().bit()),
-            )
-            .field(
-                "l2_cache_pld_err_int_raw",
-                &format_args!("{}", self.l2_cache_pld_err_int_raw().bit()),
+                &self.l2_cache_pld_done_int_raw(),
             )
+            .field("l2_cache_pld_err_int_raw", &self.l2_cache_pld_err_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 5 - The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/l2_cache_sync_preload_int_st.rs b/esp32c6/src/extmem/l2_cache_sync_preload_int_st.rs
index 801dac1634..4a7ab59b93 100644
--- a/esp32c6/src/extmem/l2_cache_sync_preload_int_st.rs
+++ b/esp32c6/src/extmem/l2_cache_sync_preload_int_st.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_SYNC_PRELOAD_INT_ST")
-            .field(
-                "l2_cache_pld_done_int_st",
-                &format_args!("{}", self.l2_cache_pld_done_int_st().bit()),
-            )
-            .field(
-                "l2_cache_pld_err_int_st",
-                &format_args!("{}", self.l2_cache_pld_err_int_st().bit()),
-            )
+            .field("l2_cache_pld_done_int_st", &self.l2_cache_pld_done_int_st())
+            .field("l2_cache_pld_err_int_st", &self.l2_cache_pld_err_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC;
 impl crate::RegisterSpec for L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_sync_rst_ctrl.rs b/esp32c6/src/extmem/l2_cache_sync_rst_ctrl.rs
index 35fe0759fd..e059e66b3a 100644
--- a/esp32c6/src/extmem/l2_cache_sync_rst_ctrl.rs
+++ b/esp32c6/src/extmem/l2_cache_sync_rst_ctrl.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_SYNC_RST_CTRL")
-            .field(
-                "l2_cache_sync_rst",
-                &format_args!("{}", self.l2_cache_sync_rst().bit()),
-            )
+            .field("l2_cache_sync_rst", &self.l2_cache_sync_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_SYNC_RST_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Sync Reset control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_rst_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_SYNC_RST_CTRL_SPEC;
 impl crate::RegisterSpec for L2_CACHE_SYNC_RST_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_tag_mem_acs_conf.rs b/esp32c6/src/extmem/l2_cache_tag_mem_acs_conf.rs
index 1428005636..3075c1dba5 100644
--- a/esp32c6/src/extmem/l2_cache_tag_mem_acs_conf.rs
+++ b/esp32c6/src/extmem/l2_cache_tag_mem_acs_conf.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_TAG_MEM_ACS_CONF")
-            .field(
-                "l2_cache_tag_mem_rd_en",
-                &format_args!("{}", self.l2_cache_tag_mem_rd_en().bit()),
-            )
-            .field(
-                "l2_cache_tag_mem_wr_en",
-                &format_args!("{}", self.l2_cache_tag_mem_wr_en().bit()),
-            )
+            .field("l2_cache_tag_mem_rd_en", &self.l2_cache_tag_mem_rd_en())
+            .field("l2_cache_tag_mem_wr_en", &self.l2_cache_tag_mem_wr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_TAG_MEM_ACS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache tag memory access configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_tag_mem_acs_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_TAG_MEM_ACS_CONF_SPEC;
 impl crate::RegisterSpec for L2_CACHE_TAG_MEM_ACS_CONF_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_tag_mem_power_ctrl.rs b/esp32c6/src/extmem/l2_cache_tag_mem_power_ctrl.rs
index 78ae8699e7..3818a9628f 100644
--- a/esp32c6/src/extmem/l2_cache_tag_mem_power_ctrl.rs
+++ b/esp32c6/src/extmem/l2_cache_tag_mem_power_ctrl.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_TAG_MEM_POWER_CTRL")
             .field(
                 "l2_cache_tag_mem_force_on",
-                &format_args!("{}", self.l2_cache_tag_mem_force_on().bit()),
+                &self.l2_cache_tag_mem_force_on(),
             )
             .field(
                 "l2_cache_tag_mem_force_pd",
-                &format_args!("{}", self.l2_cache_tag_mem_force_pd().bit()),
+                &self.l2_cache_tag_mem_force_pd(),
             )
             .field(
                 "l2_cache_tag_mem_force_pu",
-                &format_args!("{}", self.l2_cache_tag_mem_force_pu().bit()),
+                &self.l2_cache_tag_mem_force_pu(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_TAG_MEM_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache tag memory power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_tag_mem_power_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_TAG_MEM_POWER_CTRL_SPEC;
 impl crate::RegisterSpec for L2_CACHE_TAG_MEM_POWER_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_vaddr.rs b/esp32c6/src/extmem/l2_cache_vaddr.rs
index ce08f25557..303d9bd757 100644
--- a/esp32c6/src/extmem/l2_cache_vaddr.rs
+++ b/esp32c6/src/extmem/l2_cache_vaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_VADDR")
-            .field(
-                "l2_cache_vaddr",
-                &format_args!("{}", self.l2_cache_vaddr().bits()),
-            )
+            .field("l2_cache_vaddr", &self.l2_cache_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Vaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_vaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_VADDR_SPEC;
 impl crate::RegisterSpec for L2_CACHE_VADDR_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_way_object.rs b/esp32c6/src/extmem/l2_cache_way_object.rs
index 9f5ed61a17..aaa9c6b193 100644
--- a/esp32c6/src/extmem/l2_cache_way_object.rs
+++ b/esp32c6/src/extmem/l2_cache_way_object.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_WAY_OBJECT")
-            .field(
-                "l2_cache_way_object",
-                &format_args!("{}", self.l2_cache_way_object().bits()),
-            )
+            .field("l2_cache_way_object", &self.l2_cache_way_object())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_WAY_OBJECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Tag and Data memory way register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_way_object::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_WAY_OBJECT_SPEC;
 impl crate::RegisterSpec for L2_CACHE_WAY_OBJECT_SPEC {
diff --git a/esp32c6/src/extmem/l2_cache_wrap_around_ctrl.rs b/esp32c6/src/extmem/l2_cache_wrap_around_ctrl.rs
index ef659d3972..41c5a0ff69 100644
--- a/esp32c6/src/extmem/l2_cache_wrap_around_ctrl.rs
+++ b/esp32c6/src/extmem/l2_cache_wrap_around_ctrl.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_WRAP_AROUND_CTRL")
-            .field(
-                "l2_cache_wrap",
-                &format_args!("{}", self.l2_cache_wrap().bit()),
-            )
+            .field("l2_cache_wrap", &self.l2_cache_wrap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_WRAP_AROUND_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache wrap around control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_wrap_around_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_WRAP_AROUND_CTRL_SPEC;
 impl crate::RegisterSpec for L2_CACHE_WRAP_AROUND_CTRL_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus0_acs_conflict_cnt.rs b/esp32c6/src/extmem/l2_dbus0_acs_conflict_cnt.rs
index 6be5e27566..6c33425fb8 100644
--- a/esp32c6/src/extmem/l2_dbus0_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus0_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS0_ACS_CONFLICT_CNT")
-            .field(
-                "l2_dbus0_conflict_cnt",
-                &format_args!("{}", self.l2_dbus0_conflict_cnt().bits()),
-            )
+            .field("l2_dbus0_conflict_cnt", &self.l2_dbus0_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS0_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS0_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS0_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus0_acs_hit_cnt.rs b/esp32c6/src/extmem/l2_dbus0_acs_hit_cnt.rs
index e9b8f9e1b7..60046d72b8 100644
--- a/esp32c6/src/extmem/l2_dbus0_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus0_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS0_ACS_HIT_CNT")
-            .field(
-                "l2_dbus0_hit_cnt",
-                &format_args!("{}", self.l2_dbus0_hit_cnt().bits()),
-            )
+            .field("l2_dbus0_hit_cnt", &self.l2_dbus0_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS0_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS0_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS0_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus0_acs_miss_cnt.rs b/esp32c6/src/extmem/l2_dbus0_acs_miss_cnt.rs
index 3cef0dcd5d..1676075b8d 100644
--- a/esp32c6/src/extmem/l2_dbus0_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus0_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS0_ACS_MISS_CNT")
-            .field(
-                "l2_dbus0_miss_cnt",
-                &format_args!("{}", self.l2_dbus0_miss_cnt().bits()),
-            )
+            .field("l2_dbus0_miss_cnt", &self.l2_dbus0_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS0_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS0_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS0_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus0_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l2_dbus0_acs_nxtlvl_cnt.rs
index e3153c9185..675ebca2bf 100644
--- a/esp32c6/src/extmem/l2_dbus0_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus0_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS0_ACS_NXTLVL_CNT")
-            .field(
-                "l2_dbus0_nxtlvl_cnt",
-                &format_args!("{}", self.l2_dbus0_nxtlvl_cnt().bits()),
-            )
+            .field("l2_dbus0_nxtlvl_cnt", &self.l2_dbus0_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS0_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS0_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS0_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus1_acs_conflict_cnt.rs b/esp32c6/src/extmem/l2_dbus1_acs_conflict_cnt.rs
index 2b32e65fde..601918e7eb 100644
--- a/esp32c6/src/extmem/l2_dbus1_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus1_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS1_ACS_CONFLICT_CNT")
-            .field(
-                "l2_dbus1_conflict_cnt",
-                &format_args!("{}", self.l2_dbus1_conflict_cnt().bits()),
-            )
+            .field("l2_dbus1_conflict_cnt", &self.l2_dbus1_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS1_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS1_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS1_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus1_acs_hit_cnt.rs b/esp32c6/src/extmem/l2_dbus1_acs_hit_cnt.rs
index 5eca591b68..2664395383 100644
--- a/esp32c6/src/extmem/l2_dbus1_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus1_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS1_ACS_HIT_CNT")
-            .field(
-                "l2_dbus1_hit_cnt",
-                &format_args!("{}", self.l2_dbus1_hit_cnt().bits()),
-            )
+            .field("l2_dbus1_hit_cnt", &self.l2_dbus1_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS1_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS1_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS1_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus1_acs_miss_cnt.rs b/esp32c6/src/extmem/l2_dbus1_acs_miss_cnt.rs
index 7c8cc4c16c..c111276a6b 100644
--- a/esp32c6/src/extmem/l2_dbus1_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus1_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS1_ACS_MISS_CNT")
-            .field(
-                "l2_dbus1_miss_cnt",
-                &format_args!("{}", self.l2_dbus1_miss_cnt().bits()),
-            )
+            .field("l2_dbus1_miss_cnt", &self.l2_dbus1_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS1_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS1_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS1_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus1_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l2_dbus1_acs_nxtlvl_cnt.rs
index 360a3e03c6..87fd3de2b9 100644
--- a/esp32c6/src/extmem/l2_dbus1_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus1_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS1_ACS_NXTLVL_CNT")
-            .field(
-                "l2_dbus1_nxtlvl_cnt",
-                &format_args!("{}", self.l2_dbus1_nxtlvl_cnt().bits()),
-            )
+            .field("l2_dbus1_nxtlvl_cnt", &self.l2_dbus1_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS1_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS1_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS1_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus2_acs_conflict_cnt.rs b/esp32c6/src/extmem/l2_dbus2_acs_conflict_cnt.rs
index 923d7bf3cc..53361570e3 100644
--- a/esp32c6/src/extmem/l2_dbus2_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus2_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS2_ACS_CONFLICT_CNT")
-            .field(
-                "l2_dbus2_conflict_cnt",
-                &format_args!("{}", self.l2_dbus2_conflict_cnt().bits()),
-            )
+            .field("l2_dbus2_conflict_cnt", &self.l2_dbus2_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS2_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS2_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS2_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus2_acs_hit_cnt.rs b/esp32c6/src/extmem/l2_dbus2_acs_hit_cnt.rs
index 691174e674..12ce12f831 100644
--- a/esp32c6/src/extmem/l2_dbus2_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus2_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS2_ACS_HIT_CNT")
-            .field(
-                "l2_dbus2_hit_cnt",
-                &format_args!("{}", self.l2_dbus2_hit_cnt().bits()),
-            )
+            .field("l2_dbus2_hit_cnt", &self.l2_dbus2_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS2_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS2_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS2_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus2_acs_miss_cnt.rs b/esp32c6/src/extmem/l2_dbus2_acs_miss_cnt.rs
index 0797d64170..ba7498b6b5 100644
--- a/esp32c6/src/extmem/l2_dbus2_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus2_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS2_ACS_MISS_CNT")
-            .field(
-                "l2_dbus2_miss_cnt",
-                &format_args!("{}", self.l2_dbus2_miss_cnt().bits()),
-            )
+            .field("l2_dbus2_miss_cnt", &self.l2_dbus2_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS2_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS2_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS2_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus2_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l2_dbus2_acs_nxtlvl_cnt.rs
index 08a96d42ca..b485731ef4 100644
--- a/esp32c6/src/extmem/l2_dbus2_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus2_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS2_ACS_NXTLVL_CNT")
-            .field(
-                "l2_dbus2_nxtlvl_cnt",
-                &format_args!("{}", self.l2_dbus2_nxtlvl_cnt().bits()),
-            )
+            .field("l2_dbus2_nxtlvl_cnt", &self.l2_dbus2_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS2_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS2_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS2_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus3_acs_conflict_cnt.rs b/esp32c6/src/extmem/l2_dbus3_acs_conflict_cnt.rs
index 87e82d3987..310ee48c8d 100644
--- a/esp32c6/src/extmem/l2_dbus3_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus3_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS3_ACS_CONFLICT_CNT")
-            .field(
-                "l2_dbus3_conflict_cnt",
-                &format_args!("{}", self.l2_dbus3_conflict_cnt().bits()),
-            )
+            .field("l2_dbus3_conflict_cnt", &self.l2_dbus3_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS3_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS3_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS3_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus3_acs_hit_cnt.rs b/esp32c6/src/extmem/l2_dbus3_acs_hit_cnt.rs
index f8964d3056..447aeaac2d 100644
--- a/esp32c6/src/extmem/l2_dbus3_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus3_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS3_ACS_HIT_CNT")
-            .field(
-                "l2_dbus3_hit_cnt",
-                &format_args!("{}", self.l2_dbus3_hit_cnt().bits()),
-            )
+            .field("l2_dbus3_hit_cnt", &self.l2_dbus3_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS3_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS3_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS3_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus3_acs_miss_cnt.rs b/esp32c6/src/extmem/l2_dbus3_acs_miss_cnt.rs
index 2fe6ed7e7f..5f13779466 100644
--- a/esp32c6/src/extmem/l2_dbus3_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus3_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS3_ACS_MISS_CNT")
-            .field(
-                "l2_dbus3_miss_cnt",
-                &format_args!("{}", self.l2_dbus3_miss_cnt().bits()),
-            )
+            .field("l2_dbus3_miss_cnt", &self.l2_dbus3_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS3_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS3_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS3_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_dbus3_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l2_dbus3_acs_nxtlvl_cnt.rs
index 981e9b07db..59648b36aa 100644
--- a/esp32c6/src/extmem/l2_dbus3_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l2_dbus3_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS3_ACS_NXTLVL_CNT")
-            .field(
-                "l2_dbus3_nxtlvl_cnt",
-                &format_args!("{}", self.l2_dbus3_nxtlvl_cnt().bits()),
-            )
+            .field("l2_dbus3_nxtlvl_cnt", &self.l2_dbus3_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS3_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS3_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS3_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus0_acs_conflict_cnt.rs b/esp32c6/src/extmem/l2_ibus0_acs_conflict_cnt.rs
index d657830c66..3b26e7e69b 100644
--- a/esp32c6/src/extmem/l2_ibus0_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus0_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS0_ACS_CONFLICT_CNT")
-            .field(
-                "l2_ibus0_conflict_cnt",
-                &format_args!("{}", self.l2_ibus0_conflict_cnt().bits()),
-            )
+            .field("l2_ibus0_conflict_cnt", &self.l2_ibus0_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS0_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS0_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS0_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus0_acs_hit_cnt.rs b/esp32c6/src/extmem/l2_ibus0_acs_hit_cnt.rs
index b6f592f10e..6472776972 100644
--- a/esp32c6/src/extmem/l2_ibus0_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus0_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS0_ACS_HIT_CNT")
-            .field(
-                "l2_ibus0_hit_cnt",
-                &format_args!("{}", self.l2_ibus0_hit_cnt().bits()),
-            )
+            .field("l2_ibus0_hit_cnt", &self.l2_ibus0_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS0_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS0_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS0_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus0_acs_miss_cnt.rs b/esp32c6/src/extmem/l2_ibus0_acs_miss_cnt.rs
index 91dd2a4a08..5b8973fa80 100644
--- a/esp32c6/src/extmem/l2_ibus0_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus0_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS0_ACS_MISS_CNT")
-            .field(
-                "l2_ibus0_miss_cnt",
-                &format_args!("{}", self.l2_ibus0_miss_cnt().bits()),
-            )
+            .field("l2_ibus0_miss_cnt", &self.l2_ibus0_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS0_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS0_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS0_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus0_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l2_ibus0_acs_nxtlvl_cnt.rs
index 7d5d255575..ea1bcfb451 100644
--- a/esp32c6/src/extmem/l2_ibus0_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus0_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS0_ACS_NXTLVL_CNT")
-            .field(
-                "l2_ibus0_nxtlvl_cnt",
-                &format_args!("{}", self.l2_ibus0_nxtlvl_cnt().bits()),
-            )
+            .field("l2_ibus0_nxtlvl_cnt", &self.l2_ibus0_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS0_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS0_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS0_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus1_acs_conflict_cnt.rs b/esp32c6/src/extmem/l2_ibus1_acs_conflict_cnt.rs
index b0ca9e9908..b737d25ede 100644
--- a/esp32c6/src/extmem/l2_ibus1_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus1_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS1_ACS_CONFLICT_CNT")
-            .field(
-                "l2_ibus1_conflict_cnt",
-                &format_args!("{}", self.l2_ibus1_conflict_cnt().bits()),
-            )
+            .field("l2_ibus1_conflict_cnt", &self.l2_ibus1_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS1_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS1_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS1_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus1_acs_hit_cnt.rs b/esp32c6/src/extmem/l2_ibus1_acs_hit_cnt.rs
index 1a82b35abf..9d32e633b6 100644
--- a/esp32c6/src/extmem/l2_ibus1_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus1_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS1_ACS_HIT_CNT")
-            .field(
-                "l2_ibus1_hit_cnt",
-                &format_args!("{}", self.l2_ibus1_hit_cnt().bits()),
-            )
+            .field("l2_ibus1_hit_cnt", &self.l2_ibus1_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS1_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS1_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS1_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus1_acs_miss_cnt.rs b/esp32c6/src/extmem/l2_ibus1_acs_miss_cnt.rs
index b13e7bbcf7..eb12226a19 100644
--- a/esp32c6/src/extmem/l2_ibus1_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus1_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS1_ACS_MISS_CNT")
-            .field(
-                "l2_ibus1_miss_cnt",
-                &format_args!("{}", self.l2_ibus1_miss_cnt().bits()),
-            )
+            .field("l2_ibus1_miss_cnt", &self.l2_ibus1_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS1_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS1_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS1_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus1_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l2_ibus1_acs_nxtlvl_cnt.rs
index 8b8826b91a..319d5fe605 100644
--- a/esp32c6/src/extmem/l2_ibus1_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus1_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS1_ACS_NXTLVL_CNT")
-            .field(
-                "l2_ibus1_nxtlvl_cnt",
-                &format_args!("{}", self.l2_ibus1_nxtlvl_cnt().bits()),
-            )
+            .field("l2_ibus1_nxtlvl_cnt", &self.l2_ibus1_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS1_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS1_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS1_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus2_acs_conflict_cnt.rs b/esp32c6/src/extmem/l2_ibus2_acs_conflict_cnt.rs
index a46f4e552c..2bb98c9810 100644
--- a/esp32c6/src/extmem/l2_ibus2_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus2_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS2_ACS_CONFLICT_CNT")
-            .field(
-                "l2_ibus2_conflict_cnt",
-                &format_args!("{}", self.l2_ibus2_conflict_cnt().bits()),
-            )
+            .field("l2_ibus2_conflict_cnt", &self.l2_ibus2_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS2_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS2_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS2_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus2_acs_hit_cnt.rs b/esp32c6/src/extmem/l2_ibus2_acs_hit_cnt.rs
index 763540bd91..2f46154127 100644
--- a/esp32c6/src/extmem/l2_ibus2_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus2_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS2_ACS_HIT_CNT")
-            .field(
-                "l2_ibus2_hit_cnt",
-                &format_args!("{}", self.l2_ibus2_hit_cnt().bits()),
-            )
+            .field("l2_ibus2_hit_cnt", &self.l2_ibus2_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS2_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS2_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS2_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus2_acs_miss_cnt.rs b/esp32c6/src/extmem/l2_ibus2_acs_miss_cnt.rs
index 67ac956597..d86f0d7618 100644
--- a/esp32c6/src/extmem/l2_ibus2_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus2_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS2_ACS_MISS_CNT")
-            .field(
-                "l2_ibus2_miss_cnt",
-                &format_args!("{}", self.l2_ibus2_miss_cnt().bits()),
-            )
+            .field("l2_ibus2_miss_cnt", &self.l2_ibus2_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS2_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS2_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS2_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus2_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l2_ibus2_acs_nxtlvl_cnt.rs
index e431fc7f9b..d739b64035 100644
--- a/esp32c6/src/extmem/l2_ibus2_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus2_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS2_ACS_NXTLVL_CNT")
-            .field(
-                "l2_ibus2_nxtlvl_cnt",
-                &format_args!("{}", self.l2_ibus2_nxtlvl_cnt().bits()),
-            )
+            .field("l2_ibus2_nxtlvl_cnt", &self.l2_ibus2_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS2_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS2_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS2_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus3_acs_conflict_cnt.rs b/esp32c6/src/extmem/l2_ibus3_acs_conflict_cnt.rs
index b06b6ee3ff..5e897b0327 100644
--- a/esp32c6/src/extmem/l2_ibus3_acs_conflict_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus3_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS3_ACS_CONFLICT_CNT")
-            .field(
-                "l2_ibus3_conflict_cnt",
-                &format_args!("{}", self.l2_ibus3_conflict_cnt().bits()),
-            )
+            .field("l2_ibus3_conflict_cnt", &self.l2_ibus3_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS3_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS3_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS3_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus3_acs_hit_cnt.rs b/esp32c6/src/extmem/l2_ibus3_acs_hit_cnt.rs
index 2fa858b5ff..dc047bc4ec 100644
--- a/esp32c6/src/extmem/l2_ibus3_acs_hit_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus3_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS3_ACS_HIT_CNT")
-            .field(
-                "l2_ibus3_hit_cnt",
-                &format_args!("{}", self.l2_ibus3_hit_cnt().bits()),
-            )
+            .field("l2_ibus3_hit_cnt", &self.l2_ibus3_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS3_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS3_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS3_ACS_HIT_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus3_acs_miss_cnt.rs b/esp32c6/src/extmem/l2_ibus3_acs_miss_cnt.rs
index 01bf5919d0..393546ef8a 100644
--- a/esp32c6/src/extmem/l2_ibus3_acs_miss_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus3_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS3_ACS_MISS_CNT")
-            .field(
-                "l2_ibus3_miss_cnt",
-                &format_args!("{}", self.l2_ibus3_miss_cnt().bits()),
-            )
+            .field("l2_ibus3_miss_cnt", &self.l2_ibus3_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS3_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS3_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS3_ACS_MISS_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_ibus3_acs_nxtlvl_cnt.rs b/esp32c6/src/extmem/l2_ibus3_acs_nxtlvl_cnt.rs
index a2c3798ea5..c23e29366b 100644
--- a/esp32c6/src/extmem/l2_ibus3_acs_nxtlvl_cnt.rs
+++ b/esp32c6/src/extmem/l2_ibus3_acs_nxtlvl_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS3_ACS_NXTLVL_CNT")
-            .field(
-                "l2_ibus3_nxtlvl_cnt",
-                &format_args!("{}", self.l2_ibus3_nxtlvl_cnt().bits()),
-            )
+            .field("l2_ibus3_nxtlvl_cnt", &self.l2_ibus3_nxtlvl_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS3_ACS_NXTLVL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_nxtlvl_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS3_ACS_NXTLVL_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS3_ACS_NXTLVL_CNT_SPEC {
diff --git a/esp32c6/src/extmem/l2_unallocate_buffer_clear.rs b/esp32c6/src/extmem/l2_unallocate_buffer_clear.rs
index 86e87aa3a1..0cbcbb69f2 100644
--- a/esp32c6/src/extmem/l2_unallocate_buffer_clear.rs
+++ b/esp32c6/src/extmem/l2_unallocate_buffer_clear.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_UNALLOCATE_BUFFER_CLEAR")
-            .field(
-                "l2_cache_unalloc_clr",
-                &format_args!("{}", self.l2_cache_unalloc_clr().bit()),
-            )
+            .field("l2_cache_unalloc_clr", &self.l2_cache_unalloc_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_UNALLOCATE_BUFFER_CLEAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Unallocate request buffer clear registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_unallocate_buffer_clear::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_UNALLOCATE_BUFFER_CLEAR_SPEC;
 impl crate::RegisterSpec for L2_UNALLOCATE_BUFFER_CLEAR_SPEC {
diff --git a/esp32c6/src/extmem/level_split0.rs b/esp32c6/src/extmem/level_split0.rs
index ca0111fd7c..462d4c0e55 100644
--- a/esp32c6/src/extmem/level_split0.rs
+++ b/esp32c6/src/extmem/level_split0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEVEL_SPLIT0")
-            .field(
-                "level_split0",
-                &format_args!("{}", self.level_split0().bits()),
-            )
+            .field("level_split0", &self.level_split0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEVEL_SPLIT0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USED TO SPLIT L1 CACHE AND L2 CACHE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`level_split0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LEVEL_SPLIT0_SPEC;
 impl crate::RegisterSpec for LEVEL_SPLIT0_SPEC {
diff --git a/esp32c6/src/extmem/level_split1.rs b/esp32c6/src/extmem/level_split1.rs
index bd1b6bfabf..2d34c74f88 100644
--- a/esp32c6/src/extmem/level_split1.rs
+++ b/esp32c6/src/extmem/level_split1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEVEL_SPLIT1")
-            .field(
-                "level_split1",
-                &format_args!("{}", self.level_split1().bits()),
-            )
+            .field("level_split1", &self.level_split1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEVEL_SPLIT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USED TO SPLIT L1 CACHE AND L2 CACHE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`level_split1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LEVEL_SPLIT1_SPEC;
 impl crate::RegisterSpec for LEVEL_SPLIT1_SPEC {
diff --git a/esp32c6/src/extmem/redundancy_sig0.rs b/esp32c6/src/extmem/redundancy_sig0.rs
index 2155817820..71ae9f7c9f 100644
--- a/esp32c6/src/extmem/redundancy_sig0.rs
+++ b/esp32c6/src/extmem/redundancy_sig0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDUNDANCY_SIG0")
-            .field(
-                "cache_redcy_sig0",
-                &format_args!("{}", self.cache_redcy_sig0().bits()),
-            )
+            .field("cache_redcy_sig0", &self.cache_redcy_sig0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDUNDANCY_SIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are prepared for ECO."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/redundancy_sig1.rs b/esp32c6/src/extmem/redundancy_sig1.rs
index a7759ba49a..129396318b 100644
--- a/esp32c6/src/extmem/redundancy_sig1.rs
+++ b/esp32c6/src/extmem/redundancy_sig1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDUNDANCY_SIG1")
-            .field(
-                "cache_redcy_sig1",
-                &format_args!("{}", self.cache_redcy_sig1().bits()),
-            )
+            .field("cache_redcy_sig1", &self.cache_redcy_sig1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDUNDANCY_SIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are prepared for ECO."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/redundancy_sig2.rs b/esp32c6/src/extmem/redundancy_sig2.rs
index 1a529523d2..2e334a8fab 100644
--- a/esp32c6/src/extmem/redundancy_sig2.rs
+++ b/esp32c6/src/extmem/redundancy_sig2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDUNDANCY_SIG2")
-            .field(
-                "cache_redcy_sig2",
-                &format_args!("{}", self.cache_redcy_sig2().bits()),
-            )
+            .field("cache_redcy_sig2", &self.cache_redcy_sig2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDUNDANCY_SIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are prepared for ECO."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/redundancy_sig3.rs b/esp32c6/src/extmem/redundancy_sig3.rs
index 16ee9c208a..a702a530b9 100644
--- a/esp32c6/src/extmem/redundancy_sig3.rs
+++ b/esp32c6/src/extmem/redundancy_sig3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDUNDANCY_SIG3")
-            .field(
-                "cache_redcy_sig3",
-                &format_args!("{}", self.cache_redcy_sig3().bits()),
-            )
+            .field("cache_redcy_sig3", &self.cache_redcy_sig3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDUNDANCY_SIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are prepared for ECO."]
     #[inline(always)]
diff --git a/esp32c6/src/extmem/redundancy_sig4.rs b/esp32c6/src/extmem/redundancy_sig4.rs
index 18583b4ba5..e80dd6fe04 100644
--- a/esp32c6/src/extmem/redundancy_sig4.rs
+++ b/esp32c6/src/extmem/redundancy_sig4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDUNDANCY_SIG4")
-            .field(
-                "cache_redcy_sig4",
-                &format_args!("{}", self.cache_redcy_sig4().bits()),
-            )
+            .field("cache_redcy_sig4", &self.cache_redcy_sig4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDUNDANCY_SIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache redundancy signal 0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REDUNDANCY_SIG4_SPEC;
 impl crate::RegisterSpec for REDUNDANCY_SIG4_SPEC {
diff --git a/esp32c6/src/generic.rs b/esp32c6/src/generic.rs
index a2ae6aa053..45ebed16c4 100644
--- a/esp32c6/src/generic.rs
+++ b/esp32c6/src/generic.rs
@@ -48,7 +48,7 @@ pub trait RegisterSpec {
 #[doc = " Raw field type"]
 pub trait FieldSpec: Sized {
     #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
-    type Ux: Copy + PartialEq + From<Self>;
+    type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
 }
 #[doc = " Marker for fields with fixed values"]
 pub trait IsEnum: FieldSpec {}
@@ -237,6 +237,14 @@ impl<REG: Readable + Writable> Reg<REG> {
         );
     }
 }
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
 #[doc(hidden)]
 pub mod raw;
 #[doc = " Register reader."]
@@ -302,6 +310,11 @@ impl<FI: FieldSpec> FieldReader<FI> {
         self.bits
     }
 }
+impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 impl<FI> PartialEq<FI> for FieldReader<FI>
 where
     FI: FieldSpec + Copy,
@@ -338,10 +351,21 @@ impl<FI> BitReader<FI> {
         self.bit()
     }
 }
+impl<FI> core::fmt::Debug for BitReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 #[doc = " Marker for register/field writers which can take any value of specified width"]
 pub struct Safe;
 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
 pub struct Unsafe;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct Range<const MIN: u64, const MAX: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeFrom<const MIN: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeTo<const MAX: u64>;
 #[doc = " Write field Proxy"]
 pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
     raw::FieldWriter<'a, REG, WI, FI, Safety>;
@@ -393,6 +417,58 @@ where
         unsafe { self.bits(value) }
     }
 }
+impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
+    FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN && value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
 impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
diff --git a/esp32c6/src/gpio/bt_select.rs b/esp32c6/src/gpio/bt_select.rs
index d4bbc43143..d78b414754 100644
--- a/esp32c6/src/gpio/bt_select.rs
+++ b/esp32c6/src/gpio/bt_select.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_SELECT")
-            .field("bt_sel", &format_args!("{}", self.bt_sel().bits()))
+            .field("bt_sel", &self.bt_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_SELECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO bit select register"]
     #[inline(always)]
diff --git a/esp32c6/src/gpio/clock_gate.rs b/esp32c6/src/gpio/clock_gate.rs
index ebd199051e..d2bfefd1b8 100644
--- a/esp32c6/src/gpio/clock_gate.rs
+++ b/esp32c6/src/gpio/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this bit to enable GPIO clock gate"]
     #[inline(always)]
diff --git a/esp32c6/src/gpio/cpusdio_int.rs b/esp32c6/src/gpio/cpusdio_int.rs
index e46e64c2d4..889945a2df 100644
--- a/esp32c6/src/gpio/cpusdio_int.rs
+++ b/esp32c6/src/gpio/cpusdio_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPUSDIO_INT")
-            .field("sdio_int", &format_args!("{}", self.sdio_int().bits()))
+            .field("sdio_int", &self.sdio_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPUSDIO_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO CPUSDIO interrupt status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpusdio_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPUSDIO_INT_SPEC;
 impl crate::RegisterSpec for CPUSDIO_INT_SPEC {
diff --git a/esp32c6/src/gpio/cpusdio_int1.rs b/esp32c6/src/gpio/cpusdio_int1.rs
index 6187a1a50e..e501a8d95c 100644
--- a/esp32c6/src/gpio/cpusdio_int1.rs
+++ b/esp32c6/src/gpio/cpusdio_int1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPUSDIO_INT1")
-            .field("sdio_int1", &format_args!("{}", self.sdio_int1().bits()))
+            .field("sdio_int1", &self.sdio_int1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPUSDIO_INT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO CPUSDIO interrupt status register for GPIO32-34\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpusdio_int1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPUSDIO_INT1_SPEC;
 impl crate::RegisterSpec for CPUSDIO_INT1_SPEC {
diff --git a/esp32c6/src/gpio/date.rs b/esp32c6/src/gpio/date.rs
index 93dc3e03a2..71c97fccd3 100644
--- a/esp32c6/src/gpio/date.rs
+++ b/esp32c6/src/gpio/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/gpio/enable.rs b/esp32c6/src/gpio/enable.rs
index 72557464c3..2dfdd4f50c 100644
--- a/esp32c6/src/gpio/enable.rs
+++ b/esp32c6/src/gpio/enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO output enable register for GPIO0-31"]
     #[inline(always)]
diff --git a/esp32c6/src/gpio/enable1.rs b/esp32c6/src/gpio/enable1.rs
index 0e7a3fd5a8..fafe87ed90 100644
--- a/esp32c6/src/gpio/enable1.rs
+++ b/esp32c6/src/gpio/enable1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE1")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - GPIO output enable register for GPIO32-34"]
     #[inline(always)]
diff --git a/esp32c6/src/gpio/func_in_sel_cfg.rs b/esp32c6/src/gpio/func_in_sel_cfg.rs
index 53110624d6..797eca798d 100644
--- a/esp32c6/src/gpio/func_in_sel_cfg.rs
+++ b/esp32c6/src/gpio/func_in_sel_cfg.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_IN_SEL_CFG")
-            .field("in_sel", &format_args!("{}", self.in_sel().bits()))
-            .field("in_inv_sel", &format_args!("{}", self.in_inv_sel().bit()))
-            .field("sel", &format_args!("{}", self.sel().bit()))
+            .field("in_sel", &self.in_sel())
+            .field("in_inv_sel", &self.in_inv_sel())
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - set this value: s=0-34: connect GPIO\\[s\\] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level."]
     #[inline(always)]
diff --git a/esp32c6/src/gpio/func_out_sel_cfg.rs b/esp32c6/src/gpio/func_out_sel_cfg.rs
index e564007fd4..e7ce5ee25a 100644
--- a/esp32c6/src/gpio/func_out_sel_cfg.rs
+++ b/esp32c6/src/gpio/func_out_sel_cfg.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_OUT_SEL_CFG")
-            .field("out_sel", &format_args!("{}", self.out_sel().bits()))
-            .field("inv_sel", &format_args!("{}", self.inv_sel().bit()))
-            .field("oen_sel", &format_args!("{}", self.oen_sel().bit()))
-            .field("oen_inv_sel", &format_args!("{}", self.oen_inv_sel().bit()))
+            .field("out_sel", &self.out_sel())
+            .field("inv_sel", &self.inv_sel())
+            .field("oen_sel", &self.oen_sel())
+            .field("oen_inv_sel", &self.oen_inv_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-127: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=128: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
     #[inline(always)]
diff --git a/esp32c6/src/gpio/in1.rs b/esp32c6/src/gpio/in1.rs
index 6ebd95b0b9..45add27b3e 100644
--- a/esp32c6/src/gpio/in1.rs
+++ b/esp32c6/src/gpio/in1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN1")
-            .field("data_next", &format_args!("{}", self.data_next().bits()))
+            .field("data_next", &self.data_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO input register for GPIO32-34\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN1_SPEC;
 impl crate::RegisterSpec for IN1_SPEC {
diff --git a/esp32c6/src/gpio/in_.rs b/esp32c6/src/gpio/in_.rs
index d81f4ace22..420433e5b0 100644
--- a/esp32c6/src/gpio/in_.rs
+++ b/esp32c6/src/gpio/in_.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN")
-            .field("data_next", &format_args!("{}", self.data_next().bits()))
+            .field("data_next", &self.data_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO input register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SPEC;
 impl crate::RegisterSpec for IN_SPEC {
diff --git a/esp32c6/src/gpio/out.rs b/esp32c6/src/gpio/out.rs
index 3e77b03d34..2c8f1cfb13 100644
--- a/esp32c6/src/gpio/out.rs
+++ b/esp32c6/src/gpio/out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT")
-            .field("data_orig", &format_args!("{}", self.data_orig().bits()))
+            .field("data_orig", &self.data_orig())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO output register for GPIO0-31"]
     #[inline(always)]
diff --git a/esp32c6/src/gpio/out1.rs b/esp32c6/src/gpio/out1.rs
index 6dbd513919..5b6a8ca9f2 100644
--- a/esp32c6/src/gpio/out1.rs
+++ b/esp32c6/src/gpio/out1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT1")
-            .field("data_orig", &format_args!("{}", self.data_orig().bits()))
+            .field("data_orig", &self.data_orig())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - GPIO output register for GPIO32-34"]
     #[inline(always)]
diff --git a/esp32c6/src/gpio/pcpu_int.rs b/esp32c6/src/gpio/pcpu_int.rs
index b07a90c28e..52727d2345 100644
--- a/esp32c6/src/gpio/pcpu_int.rs
+++ b/esp32c6/src/gpio/pcpu_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_INT")
-            .field("procpu_int", &format_args!("{}", self.procpu_int().bits()))
+            .field("procpu_int", &self.procpu_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO PRO_CPU interrupt status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_INT_SPEC;
 impl crate::RegisterSpec for PCPU_INT_SPEC {
diff --git a/esp32c6/src/gpio/pcpu_int1.rs b/esp32c6/src/gpio/pcpu_int1.rs
index 99a973b1e7..fd4da1c0cc 100644
--- a/esp32c6/src/gpio/pcpu_int1.rs
+++ b/esp32c6/src/gpio/pcpu_int1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_INT1")
-            .field(
-                "procpu_int1",
-                &format_args!("{}", self.procpu_int1().bits()),
-            )
+            .field("procpu_int1", &self.procpu_int1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_INT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO PRO_CPU interrupt status register for GPIO32-34\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_int1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_INT1_SPEC;
 impl crate::RegisterSpec for PCPU_INT1_SPEC {
diff --git a/esp32c6/src/gpio/pcpu_nmi_int.rs b/esp32c6/src/gpio/pcpu_nmi_int.rs
index 6105c42de8..729f48eacd 100644
--- a/esp32c6/src/gpio/pcpu_nmi_int.rs
+++ b/esp32c6/src/gpio/pcpu_nmi_int.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_NMI_INT")
-            .field(
-                "procpu_nmi_int",
-                &format_args!("{}", self.procpu_nmi_int().bits()),
-            )
+            .field("procpu_nmi_int", &self.procpu_nmi_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_NMI_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_nmi_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_NMI_INT_SPEC;
 impl crate::RegisterSpec for PCPU_NMI_INT_SPEC {
diff --git a/esp32c6/src/gpio/pcpu_nmi_int1.rs b/esp32c6/src/gpio/pcpu_nmi_int1.rs
index 213edcc8d3..8755fc09a8 100644
--- a/esp32c6/src/gpio/pcpu_nmi_int1.rs
+++ b/esp32c6/src/gpio/pcpu_nmi_int1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_NMI_INT1")
-            .field(
-                "procpu_nmi_int1",
-                &format_args!("{}", self.procpu_nmi_int1().bits()),
-            )
+            .field("procpu_nmi_int1", &self.procpu_nmi_int1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_NMI_INT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_nmi_int1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_NMI_INT1_SPEC;
 impl crate::RegisterSpec for PCPU_NMI_INT1_SPEC {
diff --git a/esp32c6/src/gpio/pin.rs b/esp32c6/src/gpio/pin.rs
index 582513e76d..37d6329326 100644
--- a/esp32c6/src/gpio/pin.rs
+++ b/esp32c6/src/gpio/pin.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN")
-            .field(
-                "sync2_bypass",
-                &format_args!("{}", self.sync2_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field(
-                "sync1_bypass",
-                &format_args!("{}", self.sync1_bypass().bits()),
-            )
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("config", &format_args!("{}", self.config().bits()))
-            .field("int_ena", &format_args!("{}", self.int_ena().bits()))
+            .field("sync2_bypass", &self.sync2_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("sync1_bypass", &self.sync1_bypass())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("config", &self.config())
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
     #[inline(always)]
diff --git a/esp32c6/src/gpio/sdio_select.rs b/esp32c6/src/gpio/sdio_select.rs
index 0f94b5932d..557422a488 100644
--- a/esp32c6/src/gpio/sdio_select.rs
+++ b/esp32c6/src/gpio/sdio_select.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_SELECT")
-            .field("sdio_sel", &format_args!("{}", self.sdio_sel().bits()))
+            .field("sdio_sel", &self.sdio_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_SELECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - GPIO sdio select register"]
     #[inline(always)]
diff --git a/esp32c6/src/gpio/status.rs b/esp32c6/src/gpio/status.rs
index 349c0cde52..d41f06e1a5 100644
--- a/esp32c6/src/gpio/status.rs
+++ b/esp32c6/src/gpio/status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("interrupt", &format_args!("{}", self.interrupt().bits()))
+            .field("interrupt", &self.interrupt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO interrupt status register for GPIO0-31"]
     #[inline(always)]
diff --git a/esp32c6/src/gpio/status1.rs b/esp32c6/src/gpio/status1.rs
index 631cd45924..1aa3d8beee 100644
--- a/esp32c6/src/gpio/status1.rs
+++ b/esp32c6/src/gpio/status1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS1")
-            .field("interrupt", &format_args!("{}", self.interrupt().bits()))
+            .field("interrupt", &self.interrupt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - GPIO interrupt status register for GPIO32-34"]
     #[inline(always)]
diff --git a/esp32c6/src/gpio/status_next.rs b/esp32c6/src/gpio/status_next.rs
index 9df3402e32..ea7e8832c2 100644
--- a/esp32c6/src/gpio/status_next.rs
+++ b/esp32c6/src/gpio/status_next.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_NEXT")
-            .field(
-                "status_interrupt_next",
-                &format_args!("{}", self.status_interrupt_next().bits()),
-            )
+            .field("status_interrupt_next", &self.status_interrupt_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_NEXT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt source register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_NEXT_SPEC;
 impl crate::RegisterSpec for STATUS_NEXT_SPEC {
diff --git a/esp32c6/src/gpio/status_next1.rs b/esp32c6/src/gpio/status_next1.rs
index 62afecbaee..be79cb948d 100644
--- a/esp32c6/src/gpio/status_next1.rs
+++ b/esp32c6/src/gpio/status_next1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_NEXT1")
-            .field(
-                "status_interrupt_next1",
-                &format_args!("{}", self.status_interrupt_next1().bits()),
-            )
+            .field("status_interrupt_next1", &self.status_interrupt_next1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_NEXT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt source register for GPIO32-34\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_NEXT1_SPEC;
 impl crate::RegisterSpec for STATUS_NEXT1_SPEC {
diff --git a/esp32c6/src/gpio/strap.rs b/esp32c6/src/gpio/strap.rs
index dfc141ecfb..3bc90c4409 100644
--- a/esp32c6/src/gpio/strap.rs
+++ b/esp32c6/src/gpio/strap.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STRAP")
-            .field("strapping", &format_args!("{}", self.strapping().bits()))
+            .field("strapping", &self.strapping())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STRAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "pad strapping register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`strap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STRAP_SPEC;
 impl crate::RegisterSpec for STRAP_SPEC {
diff --git a/esp32c6/src/gpio_sd/clock_gate.rs b/esp32c6/src/gpio_sd/clock_gate.rs
index 8c8f04eacf..13ae2d777d 100644
--- a/esp32c6/src/gpio_sd/clock_gate.rs
+++ b/esp32c6/src/gpio_sd/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Clock enable bit of configuration registers for sigma delta modulation."]
     #[inline(always)]
diff --git a/esp32c6/src/gpio_sd/etm_event_ch_cfg.rs b/esp32c6/src/gpio_sd/etm_event_ch_cfg.rs
index a3cc97ebf5..af7d875ba7 100644
--- a/esp32c6/src/gpio_sd/etm_event_ch_cfg.rs
+++ b/esp32c6/src/gpio_sd/etm_event_ch_cfg.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_EVENT_CH_CFG")
-            .field("event_sel", &format_args!("{}", self.event_sel().bits()))
-            .field("event_en", &format_args!("{}", self.event_en().bit()))
+            .field("event_sel", &self.event_sel())
+            .field("event_en", &self.event_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_EVENT_CH_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Etm event channel select gpio."]
     #[inline(always)]
diff --git a/esp32c6/src/gpio_sd/etm_task_p0_cfg.rs b/esp32c6/src/gpio_sd/etm_task_p0_cfg.rs
index fc1eef97f2..40cb413d0f 100644
--- a/esp32c6/src/gpio_sd/etm_task_p0_cfg.rs
+++ b/esp32c6/src/gpio_sd/etm_task_p0_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P0_CFG")
-            .field("gpio0_en", &format_args!("{}", self.gpio0_en().bit()))
-            .field("gpio1_en", &format_args!("{}", self.gpio1_en().bit()))
-            .field("gpio2_en", &format_args!("{}", self.gpio2_en().bit()))
-            .field("gpio3_en", &format_args!("{}", self.gpio3_en().bit()))
-            .field("gpio0_sel", &format_args!("{}", self.gpio0_sel().bits()))
-            .field("gpio1_sel", &format_args!("{}", self.gpio1_sel().bits()))
-            .field("gpio2_sel", &format_args!("{}", self.gpio2_sel().bits()))
-            .field("gpio3_sel", &format_args!("{}", self.gpio3_sel().bits()))
+            .field("gpio0_en", &self.gpio0_en())
+            .field("gpio1_en", &self.gpio1_en())
+            .field("gpio2_en", &self.gpio2_en())
+            .field("gpio3_en", &self.gpio3_en())
+            .field("gpio0_sel", &self.gpio0_sel())
+            .field("gpio1_sel", &self.gpio1_sel())
+            .field("gpio2_sel", &self.gpio2_sel())
+            .field("gpio3_sel", &self.gpio3_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P0_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32c6/src/gpio_sd/etm_task_p1_cfg.rs b/esp32c6/src/gpio_sd/etm_task_p1_cfg.rs
index e9ace39fdb..3092373081 100644
--- a/esp32c6/src/gpio_sd/etm_task_p1_cfg.rs
+++ b/esp32c6/src/gpio_sd/etm_task_p1_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P1_CFG")
-            .field("gpio4_en", &format_args!("{}", self.gpio4_en().bit()))
-            .field("gpio5_en", &format_args!("{}", self.gpio5_en().bit()))
-            .field("gpio6_en", &format_args!("{}", self.gpio6_en().bit()))
-            .field("gpio7_en", &format_args!("{}", self.gpio7_en().bit()))
-            .field("gpio4_sel", &format_args!("{}", self.gpio4_sel().bits()))
-            .field("gpio5_sel", &format_args!("{}", self.gpio5_sel().bits()))
-            .field("gpio6_sel", &format_args!("{}", self.gpio6_sel().bits()))
-            .field("gpio7_sel", &format_args!("{}", self.gpio7_sel().bits()))
+            .field("gpio4_en", &self.gpio4_en())
+            .field("gpio5_en", &self.gpio5_en())
+            .field("gpio6_en", &self.gpio6_en())
+            .field("gpio7_en", &self.gpio7_en())
+            .field("gpio4_sel", &self.gpio4_sel())
+            .field("gpio5_sel", &self.gpio5_sel())
+            .field("gpio6_sel", &self.gpio6_sel())
+            .field("gpio7_sel", &self.gpio7_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P1_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32c6/src/gpio_sd/etm_task_p2_cfg.rs b/esp32c6/src/gpio_sd/etm_task_p2_cfg.rs
index 82670dabaa..63e355d1a0 100644
--- a/esp32c6/src/gpio_sd/etm_task_p2_cfg.rs
+++ b/esp32c6/src/gpio_sd/etm_task_p2_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P2_CFG")
-            .field("gpio8_en", &format_args!("{}", self.gpio8_en().bit()))
-            .field("gpio9_en", &format_args!("{}", self.gpio9_en().bit()))
-            .field("gpio10_en", &format_args!("{}", self.gpio10_en().bit()))
-            .field("gpio11_en", &format_args!("{}", self.gpio11_en().bit()))
-            .field("gpio8_sel", &format_args!("{}", self.gpio8_sel().bits()))
-            .field("gpio9_sel", &format_args!("{}", self.gpio9_sel().bits()))
-            .field("gpio10_sel", &format_args!("{}", self.gpio10_sel().bits()))
-            .field("gpio11_sel", &format_args!("{}", self.gpio11_sel().bits()))
+            .field("gpio8_en", &self.gpio8_en())
+            .field("gpio9_en", &self.gpio9_en())
+            .field("gpio10_en", &self.gpio10_en())
+            .field("gpio11_en", &self.gpio11_en())
+            .field("gpio8_sel", &self.gpio8_sel())
+            .field("gpio9_sel", &self.gpio9_sel())
+            .field("gpio10_sel", &self.gpio10_sel())
+            .field("gpio11_sel", &self.gpio11_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P2_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32c6/src/gpio_sd/etm_task_p3_cfg.rs b/esp32c6/src/gpio_sd/etm_task_p3_cfg.rs
index f7adf3168b..5289dda5a8 100644
--- a/esp32c6/src/gpio_sd/etm_task_p3_cfg.rs
+++ b/esp32c6/src/gpio_sd/etm_task_p3_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P3_CFG")
-            .field("gpio12_en", &format_args!("{}", self.gpio12_en().bit()))
-            .field("gpio13_en", &format_args!("{}", self.gpio13_en().bit()))
-            .field("gpio14_en", &format_args!("{}", self.gpio14_en().bit()))
-            .field("gpio15_en", &format_args!("{}", self.gpio15_en().bit()))
-            .field("gpio12_sel", &format_args!("{}", self.gpio12_sel().bits()))
-            .field("gpio13_sel", &format_args!("{}", self.gpio13_sel().bits()))
-            .field("gpio14_sel", &format_args!("{}", self.gpio14_sel().bits()))
-            .field("gpio15_sel", &format_args!("{}", self.gpio15_sel().bits()))
+            .field("gpio12_en", &self.gpio12_en())
+            .field("gpio13_en", &self.gpio13_en())
+            .field("gpio14_en", &self.gpio14_en())
+            .field("gpio15_en", &self.gpio15_en())
+            .field("gpio12_sel", &self.gpio12_sel())
+            .field("gpio13_sel", &self.gpio13_sel())
+            .field("gpio14_sel", &self.gpio14_sel())
+            .field("gpio15_sel", &self.gpio15_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P3_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32c6/src/gpio_sd/etm_task_p4_cfg.rs b/esp32c6/src/gpio_sd/etm_task_p4_cfg.rs
index c1bf571c18..6d2e7326f4 100644
--- a/esp32c6/src/gpio_sd/etm_task_p4_cfg.rs
+++ b/esp32c6/src/gpio_sd/etm_task_p4_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P4_CFG")
-            .field("gpio16_en", &format_args!("{}", self.gpio16_en().bit()))
-            .field("gpio17_en", &format_args!("{}", self.gpio17_en().bit()))
-            .field("gpio18_en", &format_args!("{}", self.gpio18_en().bit()))
-            .field("gpio19_en", &format_args!("{}", self.gpio19_en().bit()))
-            .field("gpio16_sel", &format_args!("{}", self.gpio16_sel().bits()))
-            .field("gpio17_sel", &format_args!("{}", self.gpio17_sel().bits()))
-            .field("gpio18_sel", &format_args!("{}", self.gpio18_sel().bits()))
-            .field("gpio19_sel", &format_args!("{}", self.gpio19_sel().bits()))
+            .field("gpio16_en", &self.gpio16_en())
+            .field("gpio17_en", &self.gpio17_en())
+            .field("gpio18_en", &self.gpio18_en())
+            .field("gpio19_en", &self.gpio19_en())
+            .field("gpio16_sel", &self.gpio16_sel())
+            .field("gpio17_sel", &self.gpio17_sel())
+            .field("gpio18_sel", &self.gpio18_sel())
+            .field("gpio19_sel", &self.gpio19_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P4_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32c6/src/gpio_sd/etm_task_p5_cfg.rs b/esp32c6/src/gpio_sd/etm_task_p5_cfg.rs
index 036e404fb1..7c3863c69a 100644
--- a/esp32c6/src/gpio_sd/etm_task_p5_cfg.rs
+++ b/esp32c6/src/gpio_sd/etm_task_p5_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P5_CFG")
-            .field("gpio20_en", &format_args!("{}", self.gpio20_en().bit()))
-            .field("gpio21_en", &format_args!("{}", self.gpio21_en().bit()))
-            .field("gpio22_en", &format_args!("{}", self.gpio22_en().bit()))
-            .field("gpio23_en", &format_args!("{}", self.gpio23_en().bit()))
-            .field("gpio20_sel", &format_args!("{}", self.gpio20_sel().bits()))
-            .field("gpio21_sel", &format_args!("{}", self.gpio21_sel().bits()))
-            .field("gpio22_sel", &format_args!("{}", self.gpio22_sel().bits()))
-            .field("gpio23_sel", &format_args!("{}", self.gpio23_sel().bits()))
+            .field("gpio20_en", &self.gpio20_en())
+            .field("gpio21_en", &self.gpio21_en())
+            .field("gpio22_en", &self.gpio22_en())
+            .field("gpio23_en", &self.gpio23_en())
+            .field("gpio20_sel", &self.gpio20_sel())
+            .field("gpio21_sel", &self.gpio21_sel())
+            .field("gpio22_sel", &self.gpio22_sel())
+            .field("gpio23_sel", &self.gpio23_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P5_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32c6/src/gpio_sd/etm_task_p6_cfg.rs b/esp32c6/src/gpio_sd/etm_task_p6_cfg.rs
index 5a0080ebf9..3a188d2401 100644
--- a/esp32c6/src/gpio_sd/etm_task_p6_cfg.rs
+++ b/esp32c6/src/gpio_sd/etm_task_p6_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P6_CFG")
-            .field("gpio24_en", &format_args!("{}", self.gpio24_en().bit()))
-            .field("gpio25_en", &format_args!("{}", self.gpio25_en().bit()))
-            .field("gpio26_en", &format_args!("{}", self.gpio26_en().bit()))
-            .field("gpio27_en", &format_args!("{}", self.gpio27_en().bit()))
-            .field("gpio24_sel", &format_args!("{}", self.gpio24_sel().bits()))
-            .field("gpio25_sel", &format_args!("{}", self.gpio25_sel().bits()))
-            .field("gpio26_sel", &format_args!("{}", self.gpio26_sel().bits()))
-            .field("gpio27_sel", &format_args!("{}", self.gpio27_sel().bits()))
+            .field("gpio24_en", &self.gpio24_en())
+            .field("gpio25_en", &self.gpio25_en())
+            .field("gpio26_en", &self.gpio26_en())
+            .field("gpio27_en", &self.gpio27_en())
+            .field("gpio24_sel", &self.gpio24_sel())
+            .field("gpio25_sel", &self.gpio25_sel())
+            .field("gpio26_sel", &self.gpio26_sel())
+            .field("gpio27_sel", &self.gpio27_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P6_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32c6/src/gpio_sd/etm_task_p7_cfg.rs b/esp32c6/src/gpio_sd/etm_task_p7_cfg.rs
index 8608b074ca..5871561c26 100644
--- a/esp32c6/src/gpio_sd/etm_task_p7_cfg.rs
+++ b/esp32c6/src/gpio_sd/etm_task_p7_cfg.rs
@@ -76,21 +76,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P7_CFG")
-            .field("gpio28_en", &format_args!("{}", self.gpio28_en().bit()))
-            .field("gpio29_en", &format_args!("{}", self.gpio29_en().bit()))
-            .field("gpio30_en", &format_args!("{}", self.gpio30_en().bit()))
-            .field("gpio28_sel", &format_args!("{}", self.gpio28_sel().bits()))
-            .field("gpio29_sel", &format_args!("{}", self.gpio29_sel().bits()))
-            .field("gpio30_sel", &format_args!("{}", self.gpio30_sel().bits()))
+            .field("gpio28_en", &self.gpio28_en())
+            .field("gpio29_en", &self.gpio29_en())
+            .field("gpio30_en", &self.gpio30_en())
+            .field("gpio28_sel", &self.gpio28_sel())
+            .field("gpio29_sel", &self.gpio29_sel())
+            .field("gpio30_sel", &self.gpio30_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P7_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32c6/src/gpio_sd/glitch_filter_ch.rs b/esp32c6/src/gpio_sd/glitch_filter_ch.rs
index 6058e197b0..fa2b797f10 100644
--- a/esp32c6/src/gpio_sd/glitch_filter_ch.rs
+++ b/esp32c6/src/gpio_sd/glitch_filter_ch.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GLITCH_FILTER_CH")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field(
-                "input_io_num",
-                &format_args!("{}", self.input_io_num().bits()),
-            )
-            .field(
-                "window_thres",
-                &format_args!("{}", self.window_thres().bits()),
-            )
-            .field(
-                "window_width",
-                &format_args!("{}", self.window_width().bits()),
-            )
+            .field("en", &self.en())
+            .field("input_io_num", &self.input_io_num())
+            .field("window_thres", &self.window_thres())
+            .field("window_width", &self.window_width())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GLITCH_FILTER_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Glitch Filter channel enable bit."]
     #[inline(always)]
diff --git a/esp32c6/src/gpio_sd/sigmadelta.rs b/esp32c6/src/gpio_sd/sigmadelta.rs
index 2cb8973865..1d31bcd5d8 100644
--- a/esp32c6/src/gpio_sd/sigmadelta.rs
+++ b/esp32c6/src/gpio_sd/sigmadelta.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SIGMADELTA")
-            .field("in_", &format_args!("{}", self.in_().bits()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
+            .field("in_", &self.in_())
+            .field("prescale", &self.prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SIGMADELTA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."]
     #[inline(always)]
diff --git a/esp32c6/src/gpio_sd/sigmadelta_misc.rs b/esp32c6/src/gpio_sd/sigmadelta_misc.rs
index b0c196b157..973947d549 100644
--- a/esp32c6/src/gpio_sd/sigmadelta_misc.rs
+++ b/esp32c6/src/gpio_sd/sigmadelta_misc.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SIGMADELTA_MISC")
-            .field(
-                "function_clk_en",
-                &format_args!("{}", self.function_clk_en().bit()),
-            )
-            .field("spi_swap", &format_args!("{}", self.spi_swap().bit()))
+            .field("function_clk_en", &self.function_clk_en())
+            .field("spi_swap", &self.spi_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SIGMADELTA_MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - Clock enable bit of sigma delta modulation."]
     #[inline(always)]
diff --git a/esp32c6/src/gpio_sd/version.rs b/esp32c6/src/gpio_sd/version.rs
index 445b15f729..d43d139101 100644
--- a/esp32c6/src/gpio_sd/version.rs
+++ b/esp32c6/src/gpio_sd/version.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field(
-                "gpio_sd_date",
-                &format_args!("{}", self.gpio_sd_date().bits()),
-            )
+            .field("gpio_sd_date", &self.gpio_sd_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register."]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/cfg_data0.rs b/esp32c6/src/hinf/cfg_data0.rs
index 46f31830a4..94d1c0def9 100644
--- a/esp32c6/src/hinf/cfg_data0.rs
+++ b/esp32c6/src/hinf/cfg_data0.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG_DATA0")
-            .field(
-                "device_id_fn1",
-                &format_args!("{}", self.device_id_fn1().bits()),
-            )
-            .field(
-                "user_id_fn1",
-                &format_args!("{}", self.user_id_fn1().bits()),
-            )
+            .field("device_id_fn1", &self.device_id_fn1())
+            .field("user_id_fn1", &self.user_id_fn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - configure device id of function1 in cis"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/cfg_data1.rs b/esp32c6/src/hinf/cfg_data1.rs
index 5ae7c98b76..d5b8712d84 100644
--- a/esp32c6/src/hinf/cfg_data1.rs
+++ b/esp32c6/src/hinf/cfg_data1.rs
@@ -129,51 +129,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG_DATA1")
-            .field("sdio_enable", &format_args!("{}", self.sdio_enable().bit()))
-            .field(
-                "sdio_ioready1",
-                &format_args!("{}", self.sdio_ioready1().bit()),
-            )
-            .field(
-                "highspeed_enable",
-                &format_args!("{}", self.highspeed_enable().bit()),
-            )
-            .field(
-                "highspeed_mode",
-                &format_args!("{}", self.highspeed_mode().bit()),
-            )
-            .field(
-                "sdio_cd_enable",
-                &format_args!("{}", self.sdio_cd_enable().bit()),
-            )
-            .field(
-                "sdio_ioready2",
-                &format_args!("{}", self.sdio_ioready2().bit()),
-            )
-            .field(
-                "sdio_int_mask",
-                &format_args!("{}", self.sdio_int_mask().bit()),
-            )
-            .field("ioenable2", &format_args!("{}", self.ioenable2().bit()))
-            .field("cd_disable", &format_args!("{}", self.cd_disable().bit()))
-            .field("func1_eps", &format_args!("{}", self.func1_eps().bit()))
-            .field("emp", &format_args!("{}", self.emp().bit()))
-            .field("ioenable1", &format_args!("{}", self.ioenable1().bit()))
-            .field("sdio_ver", &format_args!("{}", self.sdio_ver().bits()))
-            .field("func2_eps", &format_args!("{}", self.func2_eps().bit()))
-            .field(
-                "sdio20_conf",
-                &format_args!("{}", self.sdio20_conf().bits()),
-            )
+            .field("sdio_enable", &self.sdio_enable())
+            .field("sdio_ioready1", &self.sdio_ioready1())
+            .field("highspeed_enable", &self.highspeed_enable())
+            .field("highspeed_mode", &self.highspeed_mode())
+            .field("sdio_cd_enable", &self.sdio_cd_enable())
+            .field("sdio_ioready2", &self.sdio_ioready2())
+            .field("sdio_int_mask", &self.sdio_int_mask())
+            .field("ioenable2", &self.ioenable2())
+            .field("cd_disable", &self.cd_disable())
+            .field("func1_eps", &self.func1_eps())
+            .field("emp", &self.emp())
+            .field("ioenable1", &self.ioenable1())
+            .field("sdio_ver", &self.sdio_ver())
+            .field("func2_eps", &self.func2_eps())
+            .field("sdio20_conf", &self.sdio20_conf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Sdio clock enable"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/cfg_data16.rs b/esp32c6/src/hinf/cfg_data16.rs
index 3dfccd2e6c..9f67015e43 100644
--- a/esp32c6/src/hinf/cfg_data16.rs
+++ b/esp32c6/src/hinf/cfg_data16.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG_DATA16")
-            .field(
-                "device_id_fn2",
-                &format_args!("{}", self.device_id_fn2().bits()),
-            )
-            .field(
-                "user_id_fn2",
-                &format_args!("{}", self.user_id_fn2().bits()),
-            )
+            .field("device_id_fn2", &self.device_id_fn2())
+            .field("user_id_fn2", &self.user_id_fn2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG_DATA16_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - configure device id of function2 in cis"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/cfg_data7.rs b/esp32c6/src/hinf/cfg_data7.rs
index ac9a9c4c71..d03cab537e 100644
--- a/esp32c6/src/hinf/cfg_data7.rs
+++ b/esp32c6/src/hinf/cfg_data7.rs
@@ -154,43 +154,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG_DATA7")
-            .field("pin_state", &format_args!("{}", self.pin_state().bits()))
-            .field("chip_state", &format_args!("{}", self.chip_state().bits()))
-            .field("sdio_rst", &format_args!("{}", self.sdio_rst().bit()))
-            .field(
-                "sdio_ioready0",
-                &format_args!("{}", self.sdio_ioready0().bit()),
-            )
-            .field("sdio_mem_pd", &format_args!("{}", self.sdio_mem_pd().bit()))
-            .field(
-                "esdio_data1_int_en",
-                &format_args!("{}", self.esdio_data1_int_en().bit()),
-            )
-            .field(
-                "sdio_switch_volt_sw",
-                &format_args!("{}", self.sdio_switch_volt_sw().bit()),
-            )
-            .field(
-                "ddr50_blk_len_fix_en",
-                &format_args!("{}", self.ddr50_blk_len_fix_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("sddr50", &format_args!("{}", self.sddr50().bit()))
-            .field("ssdr104", &format_args!("{}", self.ssdr104().bit()))
-            .field("ssdr50", &format_args!("{}", self.ssdr50().bit()))
-            .field("sdtd", &format_args!("{}", self.sdtd().bit()))
-            .field("sdta", &format_args!("{}", self.sdta().bit()))
-            .field("sdtc", &format_args!("{}", self.sdtc().bit()))
-            .field("sai", &format_args!("{}", self.sai().bit()))
+            .field("pin_state", &self.pin_state())
+            .field("chip_state", &self.chip_state())
+            .field("sdio_rst", &self.sdio_rst())
+            .field("sdio_ioready0", &self.sdio_ioready0())
+            .field("sdio_mem_pd", &self.sdio_mem_pd())
+            .field("esdio_data1_int_en", &self.esdio_data1_int_en())
+            .field("sdio_switch_volt_sw", &self.sdio_switch_volt_sw())
+            .field("ddr50_blk_len_fix_en", &self.ddr50_blk_len_fix_en())
+            .field("clk_en", &self.clk_en())
+            .field("sddr50", &self.sddr50())
+            .field("ssdr104", &self.ssdr104())
+            .field("ssdr50", &self.ssdr50())
+            .field("sdtd", &self.sdtd())
+            .field("sdta", &self.sdta())
+            .field("sdtc", &self.sdtc())
+            .field("sai", &self.sai())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - configure cis addr 318 and 574"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/cfg_timing.rs b/esp32c6/src/hinf/cfg_timing.rs
index c037bad134..4fdcb8ecc9 100644
--- a/esp32c6/src/hinf/cfg_timing.rs
+++ b/esp32c6/src/hinf/cfg_timing.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG_TIMING")
-            .field("ncrc", &format_args!("{}", self.ncrc().bits()))
-            .field(
-                "pst_end_cmd_low_value",
-                &format_args!("{}", self.pst_end_cmd_low_value().bits()),
-            )
-            .field(
-                "pst_end_data_low_value",
-                &format_args!("{}", self.pst_end_data_low_value().bits()),
-            )
-            .field(
-                "sdclk_stop_thres",
-                &format_args!("{}", self.sdclk_stop_thres().bits()),
-            )
-            .field(
-                "sample_clk_divider",
-                &format_args!("{}", self.sample_clk_divider().bits()),
-            )
+            .field("ncrc", &self.ncrc())
+            .field("pst_end_cmd_low_value", &self.pst_end_cmd_low_value())
+            .field("pst_end_data_low_value", &self.pst_end_data_low_value())
+            .field("sdclk_stop_thres", &self.sdclk_stop_thres())
+            .field("sample_clk_divider", &self.sample_clk_divider())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG_TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - configure Ncrc parameter in sdr50/104 mode, no more than 6."]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/cfg_uhs1_int_mode.rs b/esp32c6/src/hinf/cfg_uhs1_int_mode.rs
index 78cab5496b..d1fdf421dd 100644
--- a/esp32c6/src/hinf/cfg_uhs1_int_mode.rs
+++ b/esp32c6/src/hinf/cfg_uhs1_int_mode.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG_UHS1_INT_MODE")
-            .field(
-                "intoe_end_ahead_mode",
-                &format_args!("{}", self.intoe_end_ahead_mode().bits()),
-            )
-            .field(
-                "int_end_ahead_mode",
-                &format_args!("{}", self.int_end_ahead_mode().bits()),
-            )
-            .field(
-                "intoe_st_ahead_mode",
-                &format_args!("{}", self.intoe_st_ahead_mode().bits()),
-            )
-            .field(
-                "int_st_ahead_mode",
-                &format_args!("{}", self.int_st_ahead_mode().bits()),
-            )
+            .field("intoe_end_ahead_mode", &self.intoe_end_ahead_mode())
+            .field("int_end_ahead_mode", &self.int_end_ahead_mode())
+            .field("intoe_st_ahead_mode", &self.intoe_st_ahead_mode())
+            .field("int_st_ahead_mode", &self.int_st_ahead_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG_UHS1_INT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/cis_conf_w0.rs b/esp32c6/src/hinf/cis_conf_w0.rs
index 72eb38ee05..60e8dccf09 100644
--- a/esp32c6/src/hinf/cis_conf_w0.rs
+++ b/esp32c6/src/hinf/cis_conf_w0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF_W0")
-            .field(
-                "cis_conf_w0",
-                &format_args!("{}", self.cis_conf_w0().bits()),
-            )
+            .field("cis_conf_w0", &self.cis_conf_w0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF_W0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configure cis addr 39~36"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/cis_conf_w1.rs b/esp32c6/src/hinf/cis_conf_w1.rs
index 46baef617a..6551f1153b 100644
--- a/esp32c6/src/hinf/cis_conf_w1.rs
+++ b/esp32c6/src/hinf/cis_conf_w1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF_W1")
-            .field(
-                "cis_conf_w1",
-                &format_args!("{}", self.cis_conf_w1().bits()),
-            )
+            .field("cis_conf_w1", &self.cis_conf_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configure cis addr 43~40"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/cis_conf_w2.rs b/esp32c6/src/hinf/cis_conf_w2.rs
index 65fa48b1a8..691091ec18 100644
--- a/esp32c6/src/hinf/cis_conf_w2.rs
+++ b/esp32c6/src/hinf/cis_conf_w2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF_W2")
-            .field(
-                "cis_conf_w2",
-                &format_args!("{}", self.cis_conf_w2().bits()),
-            )
+            .field("cis_conf_w2", &self.cis_conf_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configure cis addr 47~44"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/cis_conf_w3.rs b/esp32c6/src/hinf/cis_conf_w3.rs
index 9b7e714000..3d9f43cee6 100644
--- a/esp32c6/src/hinf/cis_conf_w3.rs
+++ b/esp32c6/src/hinf/cis_conf_w3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF_W3")
-            .field(
-                "cis_conf_w3",
-                &format_args!("{}", self.cis_conf_w3().bits()),
-            )
+            .field("cis_conf_w3", &self.cis_conf_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configure cis addr 51~48"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/cis_conf_w4.rs b/esp32c6/src/hinf/cis_conf_w4.rs
index 5897d19255..5b6560a638 100644
--- a/esp32c6/src/hinf/cis_conf_w4.rs
+++ b/esp32c6/src/hinf/cis_conf_w4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF_W4")
-            .field(
-                "cis_conf_w4",
-                &format_args!("{}", self.cis_conf_w4().bits()),
-            )
+            .field("cis_conf_w4", &self.cis_conf_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configure cis addr 55~52"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/cis_conf_w5.rs b/esp32c6/src/hinf/cis_conf_w5.rs
index eaf77666b6..44331bdd93 100644
--- a/esp32c6/src/hinf/cis_conf_w5.rs
+++ b/esp32c6/src/hinf/cis_conf_w5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF_W5")
-            .field(
-                "cis_conf_w5",
-                &format_args!("{}", self.cis_conf_w5().bits()),
-            )
+            .field("cis_conf_w5", &self.cis_conf_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configure cis addr 59~56"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/cis_conf_w6.rs b/esp32c6/src/hinf/cis_conf_w6.rs
index f0335e2d24..380b376ed8 100644
--- a/esp32c6/src/hinf/cis_conf_w6.rs
+++ b/esp32c6/src/hinf/cis_conf_w6.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF_W6")
-            .field(
-                "cis_conf_w6",
-                &format_args!("{}", self.cis_conf_w6().bits()),
-            )
+            .field("cis_conf_w6", &self.cis_conf_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configure cis addr 63~60"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/cis_conf_w7.rs b/esp32c6/src/hinf/cis_conf_w7.rs
index fb00366c88..54693de957 100644
--- a/esp32c6/src/hinf/cis_conf_w7.rs
+++ b/esp32c6/src/hinf/cis_conf_w7.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CIS_CONF_W7")
-            .field(
-                "cis_conf_w7",
-                &format_args!("{}", self.cis_conf_w7().bits()),
-            )
+            .field("cis_conf_w7", &self.cis_conf_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CIS_CONF_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configure cis addr 67~64"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/conf_status.rs b/esp32c6/src/hinf/conf_status.rs
index 851e58edc0..1896e98680 100644
--- a/esp32c6/src/hinf/conf_status.rs
+++ b/esp32c6/src/hinf/conf_status.rs
@@ -62,32 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_STATUS")
-            .field(
-                "func0_config0",
-                &format_args!("{}", self.func0_config0().bits()),
-            )
-            .field("sdr25_st", &format_args!("{}", self.sdr25_st().bit()))
-            .field("sdr50_st", &format_args!("{}", self.sdr50_st().bit()))
-            .field("sdr104_st", &format_args!("{}", self.sdr104_st().bit()))
-            .field("ddr50_st", &format_args!("{}", self.ddr50_st().bit()))
-            .field("tune_st", &format_args!("{}", self.tune_st().bits()))
-            .field(
-                "sdio_switch_volt_st",
-                &format_args!("{}", self.sdio_switch_volt_st().bit()),
-            )
-            .field(
-                "sdio_switch_end",
-                &format_args!("{}", self.sdio_switch_end().bit()),
-            )
+            .field("func0_config0", &self.func0_config0())
+            .field("sdr25_st", &self.sdr25_st())
+            .field("sdr50_st", &self.sdr50_st())
+            .field("sdr104_st", &self.sdr104_st())
+            .field("ddr50_st", &self.ddr50_st())
+            .field("tune_st", &self.tune_st())
+            .field("sdio_switch_volt_st", &self.sdio_switch_volt_st())
+            .field("sdio_switch_end", &self.sdio_switch_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "func0 config0 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CONF_STATUS_SPEC;
 impl crate::RegisterSpec for CONF_STATUS_SPEC {
diff --git a/esp32c6/src/hinf/sdio_date.rs b/esp32c6/src/hinf/sdio_date.rs
index 86549c36c5..ca3579c93b 100644
--- a/esp32c6/src/hinf/sdio_date.rs
+++ b/esp32c6/src/hinf/sdio_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_DATE")
-            .field("sdio_date", &format_args!("{}", self.sdio_date().bits()))
+            .field("sdio_date", &self.sdio_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - sdio version date."]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/sdio_slave_eco_conf.rs b/esp32c6/src/hinf/sdio_slave_eco_conf.rs
index 96763713a5..cebde77eb6 100644
--- a/esp32c6/src/hinf/sdio_slave_eco_conf.rs
+++ b/esp32c6/src/hinf/sdio_slave_eco_conf.rs
@@ -56,39 +56,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_SLAVE_ECO_CONF")
-            .field(
-                "sdio_slave_rdn_result",
-                &format_args!("{}", self.sdio_slave_rdn_result().bit()),
-            )
-            .field(
-                "sdio_slave_rdn_ena",
-                &format_args!("{}", self.sdio_slave_rdn_ena().bit()),
-            )
+            .field("sdio_slave_rdn_result", &self.sdio_slave_rdn_result())
+            .field("sdio_slave_rdn_ena", &self.sdio_slave_rdn_ena())
             .field(
                 "sdio_slave_sdio_clk_rdn_result",
-                &format_args!("{}", self.sdio_slave_sdio_clk_rdn_result().bit()),
+                &self.sdio_slave_sdio_clk_rdn_result(),
             )
             .field(
                 "sdio_slave_sdio_clk_rdn_ena",
-                &format_args!("{}", self.sdio_slave_sdio_clk_rdn_ena().bit()),
+                &self.sdio_slave_sdio_clk_rdn_ena(),
             )
             .field(
                 "sdio_slave_sdclk_pad_rdn_result",
-                &format_args!("{}", self.sdio_slave_sdclk_pad_rdn_result().bit()),
+                &self.sdio_slave_sdclk_pad_rdn_result(),
             )
             .field(
                 "sdio_slave_sdclk_pad_rdn_ena",
-                &format_args!("{}", self.sdio_slave_sdclk_pad_rdn_ena().bit()),
+                &self.sdio_slave_sdclk_pad_rdn_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_SLAVE_ECO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - redundant registers for sdio_slave"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/sdio_slave_eco_high.rs b/esp32c6/src/hinf/sdio_slave_eco_high.rs
index ba4e768497..1b0be4ffc1 100644
--- a/esp32c6/src/hinf/sdio_slave_eco_high.rs
+++ b/esp32c6/src/hinf/sdio_slave_eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_SLAVE_ECO_HIGH")
-            .field(
-                "rdn_eco_high",
-                &format_args!("{}", self.rdn_eco_high().bits()),
-            )
+            .field("rdn_eco_high", &self.rdn_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_SLAVE_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - redundant registers for sdio_slave"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/sdio_slave_eco_low.rs b/esp32c6/src/hinf/sdio_slave_eco_low.rs
index 50e158925a..1f2c0291b5 100644
--- a/esp32c6/src/hinf/sdio_slave_eco_low.rs
+++ b/esp32c6/src/hinf/sdio_slave_eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_SLAVE_ECO_LOW")
-            .field(
-                "rdn_eco_low",
-                &format_args!("{}", self.rdn_eco_low().bits()),
-            )
+            .field("rdn_eco_low", &self.rdn_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_SLAVE_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - redundant registers for sdio_slave"]
     #[inline(always)]
diff --git a/esp32c6/src/hinf/sdio_slave_ldo_conf.rs b/esp32c6/src/hinf/sdio_slave_ldo_conf.rs
index aaa3866c38..dff7b4daf8 100644
--- a/esp32c6/src/hinf/sdio_slave_ldo_conf.rs
+++ b/esp32c6/src/hinf/sdio_slave_ldo_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_SLAVE_LDO_CONF")
-            .field(
-                "ldo_ready_ctl_in_en",
-                &format_args!("{}", self.ldo_ready_ctl_in_en().bit()),
-            )
-            .field(
-                "ldo_ready_thres",
-                &format_args!("{}", self.ldo_ready_thres().bits()),
-            )
-            .field(
-                "ldo_ready_ignore_en",
-                &format_args!("{}", self.ldo_ready_ignore_en().bit()),
-            )
+            .field("ldo_ready_ctl_in_en", &self.ldo_ready_ctl_in_en())
+            .field("ldo_ready_thres", &self.ldo_ready_thres())
+            .field("ldo_ready_ignore_en", &self.ldo_ready_ignore_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_SLAVE_LDO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - control ldo ready signal by sdio slave itself"]
     #[inline(always)]
diff --git a/esp32c6/src/hmac/date.rs b/esp32c6/src/hmac/date.rs
index dae408e040..451431dcfa 100644
--- a/esp32c6/src/hmac/date.rs
+++ b/esp32c6/src/hmac/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/hmac/query_busy.rs b/esp32c6/src/hmac/query_busy.rs
index b2162c1fb3..6f817e76f4 100644
--- a/esp32c6/src/hmac/query_busy.rs
+++ b/esp32c6/src/hmac/query_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_BUSY")
-            .field("busy_state", &format_args!("{}", self.busy_state().bit()))
+            .field("busy_state", &self.busy_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Busy register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_BUSY_SPEC;
 impl crate::RegisterSpec for QUERY_BUSY_SPEC {
diff --git a/esp32c6/src/hmac/query_error.rs b/esp32c6/src/hmac/query_error.rs
index dccd8dd32f..8f5b2d284b 100644
--- a/esp32c6/src/hmac/query_error.rs
+++ b/esp32c6/src/hmac/query_error.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_ERROR")
-            .field("query_check", &format_args!("{}", self.query_check().bit()))
+            .field("query_check", &self.query_check())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_ERROR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Error register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_error::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_ERROR_SPEC;
 impl crate::RegisterSpec for QUERY_ERROR_SPEC {
diff --git a/esp32c6/src/hmac/rd_result_mem.rs b/esp32c6/src/hmac/rd_result_mem.rs
index e93fc1892c..15ad43ddc6 100644
--- a/esp32c6/src/hmac/rd_result_mem.rs
+++ b/esp32c6/src/hmac/rd_result_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RESULT_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Result from upstream.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_result_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rd_result_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RESULT_MEM_SPEC;
diff --git a/esp32c6/src/hmac/wr_message_mem.rs b/esp32c6/src/hmac/wr_message_mem.rs
index e4eda3e0e5..2779a44011 100644
--- a/esp32c6/src/hmac/wr_message_mem.rs
+++ b/esp32c6/src/hmac/wr_message_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_MESSAGE_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Message block memory.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_message_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_message_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WR_MESSAGE_MEM_SPEC;
diff --git a/esp32c6/src/hp_apm/clock_gate.rs b/esp32c6/src/hp_apm/clock_gate.rs
index 0ea9f4e7a3..0260550609 100644
--- a/esp32c6/src/hp_apm/clock_gate.rs
+++ b/esp32c6/src/hp_apm/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_clk_en"]
     #[inline(always)]
diff --git a/esp32c6/src/hp_apm/date.rs b/esp32c6/src/hp_apm/date.rs
index fb73a9a02f..3825783dcf 100644
--- a/esp32c6/src/hp_apm/date.rs
+++ b/esp32c6/src/hp_apm/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/hp_apm/func_ctrl.rs b/esp32c6/src/hp_apm/func_ctrl.rs
index aba1980447..18d2d1b15d 100644
--- a/esp32c6/src/hp_apm/func_ctrl.rs
+++ b/esp32c6/src/hp_apm/func_ctrl.rs
@@ -47,31 +47,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_CTRL")
-            .field(
-                "m0_pms_func_en",
-                &format_args!("{}", self.m0_pms_func_en().bit()),
-            )
-            .field(
-                "m1_pms_func_en",
-                &format_args!("{}", self.m1_pms_func_en().bit()),
-            )
-            .field(
-                "m2_pms_func_en",
-                &format_args!("{}", self.m2_pms_func_en().bit()),
-            )
-            .field(
-                "m3_pms_func_en",
-                &format_args!("{}", self.m3_pms_func_en().bit()),
-            )
+            .field("m0_pms_func_en", &self.m0_pms_func_en())
+            .field("m1_pms_func_en", &self.m1_pms_func_en())
+            .field("m2_pms_func_en", &self.m2_pms_func_en())
+            .field("m3_pms_func_en", &self.m3_pms_func_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "PMS M(0-3) function enable"]
     #[doc = ""]
diff --git a/esp32c6/src/hp_apm/int_en.rs b/esp32c6/src/hp_apm/int_en.rs
index 552bed269a..8217d81fd4 100644
--- a/esp32c6/src/hp_apm/int_en.rs
+++ b/esp32c6/src/hp_apm/int_en.rs
@@ -47,19 +47,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_EN")
-            .field("m0_apm", &format_args!("{}", self.m0_apm().bit()))
-            .field("m1_apm", &format_args!("{}", self.m1_apm().bit()))
-            .field("m2_apm", &format_args!("{}", self.m2_apm().bit()))
-            .field("m3_apm", &format_args!("{}", self.m3_apm().bit()))
+            .field("m0_apm", &self.m0_apm())
+            .field("m1_apm", &self.m1_apm())
+            .field("m2_apm", &self.m2_apm())
+            .field("m3_apm", &self.m3_apm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "APM M(0-3) interrupt enable"]
     #[doc = ""]
diff --git a/esp32c6/src/hp_apm/m/exception_info0.rs b/esp32c6/src/hp_apm/m/exception_info0.rs
index e69de2ef75..2d06741a86 100644
--- a/esp32c6/src/hp_apm/m/exception_info0.rs
+++ b/esp32c6/src/hp_apm/m/exception_info0.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXCEPTION_INFO0")
-            .field(
-                "exception_region",
-                &format_args!("{}", self.exception_region().bits()),
-            )
-            .field(
-                "exception_mode",
-                &format_args!("{}", self.exception_mode().bits()),
-            )
-            .field(
-                "exception_id",
-                &format_args!("{}", self.exception_id().bits()),
-            )
+            .field("exception_region", &self.exception_region())
+            .field("exception_mode", &self.exception_mode())
+            .field("exception_id", &self.exception_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXCEPTION_INFO0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 exception_info0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exception_info0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXCEPTION_INFO0_SPEC;
 impl crate::RegisterSpec for EXCEPTION_INFO0_SPEC {
diff --git a/esp32c6/src/hp_apm/m/exception_info1.rs b/esp32c6/src/hp_apm/m/exception_info1.rs
index 1a6977abc5..cb3b39d257 100644
--- a/esp32c6/src/hp_apm/m/exception_info1.rs
+++ b/esp32c6/src/hp_apm/m/exception_info1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXCEPTION_INFO1")
-            .field(
-                "exception_addr",
-                &format_args!("{}", self.exception_addr().bits()),
-            )
+            .field("exception_addr", &self.exception_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXCEPTION_INFO1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 exception_info1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exception_info1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXCEPTION_INFO1_SPEC;
 impl crate::RegisterSpec for EXCEPTION_INFO1_SPEC {
diff --git a/esp32c6/src/hp_apm/m/status.rs b/esp32c6/src/hp_apm/m/status.rs
index 6a5c666bbf..3e275a91ca 100644
--- a/esp32c6/src/hp_apm/m/status.rs
+++ b/esp32c6/src/hp_apm/m/status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field(
-                "exception_status",
-                &format_args!("{}", self.exception_status().bits()),
-            )
+            .field("exception_status", &self.exception_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32c6/src/hp_apm/region/addr_end.rs b/esp32c6/src/hp_apm/region/addr_end.rs
index 8940485f11..db15e1b66a 100644
--- a/esp32c6/src/hp_apm/region/addr_end.rs
+++ b/esp32c6/src/hp_apm/region/addr_end.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR_END")
-            .field("addr_end", &format_args!("{}", self.addr_end().bits()))
+            .field("addr_end", &self.addr_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_END_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - End address of region0"]
     #[inline(always)]
diff --git a/esp32c6/src/hp_apm/region/addr_start.rs b/esp32c6/src/hp_apm/region/addr_start.rs
index 15654e8830..21d743f5e2 100644
--- a/esp32c6/src/hp_apm/region/addr_start.rs
+++ b/esp32c6/src/hp_apm/region/addr_start.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR_START")
-            .field("addr_start", &format_args!("{}", self.addr_start().bits()))
+            .field("addr_start", &self.addr_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_START_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Start address of region0"]
     #[inline(always)]
diff --git a/esp32c6/src/hp_apm/region/pms_attr.rs b/esp32c6/src/hp_apm/region/pms_attr.rs
index 30b2486d8c..a929b05fa9 100644
--- a/esp32c6/src/hp_apm/region/pms_attr.rs
+++ b/esp32c6/src/hp_apm/region/pms_attr.rs
@@ -110,24 +110,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMS_ATTR")
-            .field("r0_pms_x", &format_args!("{}", self.r0_pms_x().bit()))
-            .field("r1_pms_x", &format_args!("{}", self.r1_pms_x().bit()))
-            .field("r2_pms_x", &format_args!("{}", self.r2_pms_x().bit()))
-            .field("r0_pms_w", &format_args!("{}", self.r0_pms_w().bit()))
-            .field("r1_pms_w", &format_args!("{}", self.r1_pms_w().bit()))
-            .field("r2_pms_w", &format_args!("{}", self.r2_pms_w().bit()))
-            .field("r0_pms_r", &format_args!("{}", self.r0_pms_r().bit()))
-            .field("r1_pms_r", &format_args!("{}", self.r1_pms_r().bit()))
-            .field("r2_pms_r", &format_args!("{}", self.r2_pms_r().bit()))
+            .field("r0_pms_x", &self.r0_pms_x())
+            .field("r1_pms_x", &self.r1_pms_x())
+            .field("r2_pms_x", &self.r2_pms_x())
+            .field("r0_pms_w", &self.r0_pms_w())
+            .field("r1_pms_w", &self.r1_pms_w())
+            .field("r2_pms_w", &self.r2_pms_w())
+            .field("r0_pms_r", &self.r0_pms_r())
+            .field("r1_pms_r", &self.r1_pms_r())
+            .field("r2_pms_r", &self.r2_pms_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMS_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Region execute authority in REE_MODE(0-2)"]
     #[doc = ""]
diff --git a/esp32c6/src/hp_apm/region_filter_en.rs b/esp32c6/src/hp_apm/region_filter_en.rs
index 337139e986..b0d863e59e 100644
--- a/esp32c6/src/hp_apm/region_filter_en.rs
+++ b/esp32c6/src/hp_apm/region_filter_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGION_FILTER_EN")
-            .field(
-                "region_filter_en",
-                &format_args!("{}", self.region_filter_en().bits()),
-            )
+            .field("region_filter_en", &self.region_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_FILTER_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Region filter enable"]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/clock_gate.rs b/esp32c6/src/hp_sys/clock_gate.rs
index 8cdc737fd3..eaa719ae00 100644
--- a/esp32c6/src/hp_sys/clock_gate.rs
+++ b/esp32c6/src/hp_sys/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit as 1 to force on clock gating."]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/core_debug_runstall_conf.rs b/esp32c6/src/hp_sys/core_debug_runstall_conf.rs
index 4e6a9bdea4..757d16d6aa 100644
--- a/esp32c6/src/hp_sys/core_debug_runstall_conf.rs
+++ b/esp32c6/src/hp_sys/core_debug_runstall_conf.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_DEBUG_RUNSTALL_CONF")
             .field(
                 "core_debug_runstall_enable",
-                &format_args!("{}", self.core_debug_runstall_enable().bit()),
+                &self.core_debug_runstall_enable(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_DEBUG_RUNSTALL_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this field to 1 to enable debug runstall feature between HP-core and LP-core."]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/cpu_peri_timeout_addr.rs b/esp32c6/src/hp_sys/cpu_peri_timeout_addr.rs
index 743f7e48d1..a6d4ad0443 100644
--- a/esp32c6/src/hp_sys/cpu_peri_timeout_addr.rs
+++ b/esp32c6/src/hp_sys/cpu_peri_timeout_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERI_TIMEOUT_ADDR")
-            .field(
-                "cpu_peri_timeout_addr",
-                &format_args!("{}", self.cpu_peri_timeout_addr().bits()),
-            )
+            .field("cpu_peri_timeout_addr", &self.cpu_peri_timeout_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_TIMEOUT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CPU_PERI_TIMEOUT_ADDR register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_peri_timeout_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPU_PERI_TIMEOUT_ADDR_SPEC;
 impl crate::RegisterSpec for CPU_PERI_TIMEOUT_ADDR_SPEC {
diff --git a/esp32c6/src/hp_sys/cpu_peri_timeout_conf.rs b/esp32c6/src/hp_sys/cpu_peri_timeout_conf.rs
index f9d50fef91..ba455a9773 100644
--- a/esp32c6/src/hp_sys/cpu_peri_timeout_conf.rs
+++ b/esp32c6/src/hp_sys/cpu_peri_timeout_conf.rs
@@ -28,23 +28,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERI_TIMEOUT_CONF")
-            .field(
-                "cpu_peri_timeout_thres",
-                &format_args!("{}", self.cpu_peri_timeout_thres().bits()),
-            )
+            .field("cpu_peri_timeout_thres", &self.cpu_peri_timeout_thres())
             .field(
                 "cpu_peri_timeout_protect_en",
-                &format_args!("{}", self.cpu_peri_timeout_protect_en().bit()),
+                &self.cpu_peri_timeout_protect_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_TIMEOUT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain."]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/cpu_peri_timeout_uid.rs b/esp32c6/src/hp_sys/cpu_peri_timeout_uid.rs
index e7fd7d84d2..d54480baf9 100644
--- a/esp32c6/src/hp_sys/cpu_peri_timeout_uid.rs
+++ b/esp32c6/src/hp_sys/cpu_peri_timeout_uid.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERI_TIMEOUT_UID")
-            .field(
-                "cpu_peri_timeout_uid",
-                &format_args!("{}", self.cpu_peri_timeout_uid().bits()),
-            )
+            .field("cpu_peri_timeout_uid", &self.cpu_peri_timeout_uid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_TIMEOUT_UID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CPU_PERI_TIMEOUT_UID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_peri_timeout_uid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPU_PERI_TIMEOUT_UID_SPEC;
 impl crate::RegisterSpec for CPU_PERI_TIMEOUT_UID_SPEC {
diff --git a/esp32c6/src/hp_sys/date.rs b/esp32c6/src/hp_sys/date.rs
index 87d2305869..9c00189400 100644
--- a/esp32c6/src/hp_sys/date.rs
+++ b/esp32c6/src/hp_sys/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/hp_sys/external_device_encrypt_decrypt_control.rs b/esp32c6/src/hp_sys/external_device_encrypt_decrypt_control.rs
index 1b02ab6020..614786d593 100644
--- a/esp32c6/src/hp_sys/external_device_encrypt_decrypt_control.rs
+++ b/esp32c6/src/hp_sys/external_device_encrypt_decrypt_control.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL")
             .field(
                 "enable_spi_manual_encrypt",
-                &format_args!("{}", self.enable_spi_manual_encrypt().bit()),
+                &self.enable_spi_manual_encrypt(),
             )
             .field(
                 "enable_download_db_encrypt",
-                &format_args!("{}", self.enable_download_db_encrypt().bit()),
+                &self.enable_download_db_encrypt(),
             )
             .field(
                 "enable_download_g0cb_decrypt",
-                &format_args!("{}", self.enable_download_g0cb_decrypt().bit()),
+                &self.enable_download_g0cb_decrypt(),
             )
             .field(
                 "enable_download_manual_encrypt",
-                &format_args!("{}", self.enable_download_manual_encrypt().bit()),
+                &self.enable_download_manual_encrypt(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode."]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/hp_peri_timeout_addr.rs b/esp32c6/src/hp_sys/hp_peri_timeout_addr.rs
index b9f2328aff..8f0dbec847 100644
--- a/esp32c6/src/hp_sys/hp_peri_timeout_addr.rs
+++ b/esp32c6/src/hp_sys/hp_peri_timeout_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_PERI_TIMEOUT_ADDR")
-            .field(
-                "hp_peri_timeout_addr",
-                &format_args!("{}", self.hp_peri_timeout_addr().bits()),
-            )
+            .field("hp_peri_timeout_addr", &self.hp_peri_timeout_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_PERI_TIMEOUT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "HP_PERI_TIMEOUT_ADDR register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_peri_timeout_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HP_PERI_TIMEOUT_ADDR_SPEC;
 impl crate::RegisterSpec for HP_PERI_TIMEOUT_ADDR_SPEC {
diff --git a/esp32c6/src/hp_sys/hp_peri_timeout_conf.rs b/esp32c6/src/hp_sys/hp_peri_timeout_conf.rs
index 996e76f801..6aefa49a65 100644
--- a/esp32c6/src/hp_sys/hp_peri_timeout_conf.rs
+++ b/esp32c6/src/hp_sys/hp_peri_timeout_conf.rs
@@ -28,23 +28,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_PERI_TIMEOUT_CONF")
-            .field(
-                "hp_peri_timeout_thres",
-                &format_args!("{}", self.hp_peri_timeout_thres().bits()),
-            )
+            .field("hp_peri_timeout_thres", &self.hp_peri_timeout_thres())
             .field(
                 "hp_peri_timeout_protect_en",
-                &format_args!("{}", self.hp_peri_timeout_protect_en().bit()),
+                &self.hp_peri_timeout_protect_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_PERI_TIMEOUT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain."]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/hp_peri_timeout_uid.rs b/esp32c6/src/hp_sys/hp_peri_timeout_uid.rs
index 09322dca5a..bf653e4774 100644
--- a/esp32c6/src/hp_sys/hp_peri_timeout_uid.rs
+++ b/esp32c6/src/hp_sys/hp_peri_timeout_uid.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_PERI_TIMEOUT_UID")
-            .field(
-                "hp_peri_timeout_uid",
-                &format_args!("{}", self.hp_peri_timeout_uid().bits()),
-            )
+            .field("hp_peri_timeout_uid", &self.hp_peri_timeout_uid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_PERI_TIMEOUT_UID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "HP_PERI_TIMEOUT_UID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_peri_timeout_uid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HP_PERI_TIMEOUT_UID_SPEC;
 impl crate::RegisterSpec for HP_PERI_TIMEOUT_UID_SPEC {
diff --git a/esp32c6/src/hp_sys/mem_test_conf.rs b/esp32c6/src/hp_sys/mem_test_conf.rs
index 358b3d6ef8..f724dace98 100644
--- a/esp32c6/src/hp_sys/mem_test_conf.rs
+++ b/esp32c6/src/hp_sys/mem_test_conf.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_TEST_CONF")
-            .field(
-                "hp_mem_wpulse",
-                &format_args!("{}", self.hp_mem_wpulse().bits()),
-            )
-            .field("hp_mem_wa", &format_args!("{}", self.hp_mem_wa().bits()))
-            .field("hp_mem_ra", &format_args!("{}", self.hp_mem_ra().bits()))
+            .field("hp_mem_wpulse", &self.hp_mem_wpulse())
+            .field("hp_mem_wa", &self.hp_mem_wa())
+            .field("hp_mem_ra", &self.hp_mem_ra())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_TEST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - This field controls hp system memory WPULSE parameter."]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/modem_peri_timeout_addr.rs b/esp32c6/src/hp_sys/modem_peri_timeout_addr.rs
index ce85e3f79c..dccdd020a9 100644
--- a/esp32c6/src/hp_sys/modem_peri_timeout_addr.rs
+++ b/esp32c6/src/hp_sys/modem_peri_timeout_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODEM_PERI_TIMEOUT_ADDR")
-            .field(
-                "modem_peri_timeout_addr",
-                &format_args!("{}", self.modem_peri_timeout_addr().bits()),
-            )
+            .field("modem_peri_timeout_addr", &self.modem_peri_timeout_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODEM_PERI_TIMEOUT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MODEM_PERI_TIMEOUT_ADDR register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`modem_peri_timeout_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MODEM_PERI_TIMEOUT_ADDR_SPEC;
 impl crate::RegisterSpec for MODEM_PERI_TIMEOUT_ADDR_SPEC {
diff --git a/esp32c6/src/hp_sys/modem_peri_timeout_conf.rs b/esp32c6/src/hp_sys/modem_peri_timeout_conf.rs
index 24fab958b5..66f159bc8a 100644
--- a/esp32c6/src/hp_sys/modem_peri_timeout_conf.rs
+++ b/esp32c6/src/hp_sys/modem_peri_timeout_conf.rs
@@ -28,23 +28,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODEM_PERI_TIMEOUT_CONF")
-            .field(
-                "modem_peri_timeout_thres",
-                &format_args!("{}", self.modem_peri_timeout_thres().bits()),
-            )
+            .field("modem_peri_timeout_thres", &self.modem_peri_timeout_thres())
             .field(
                 "modem_peri_timeout_protect_en",
-                &format_args!("{}", self.modem_peri_timeout_protect_en().bit()),
+                &self.modem_peri_timeout_protect_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODEM_PERI_TIMEOUT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain."]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/modem_peri_timeout_uid.rs b/esp32c6/src/hp_sys/modem_peri_timeout_uid.rs
index 2e34f16c6e..835d84d137 100644
--- a/esp32c6/src/hp_sys/modem_peri_timeout_uid.rs
+++ b/esp32c6/src/hp_sys/modem_peri_timeout_uid.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODEM_PERI_TIMEOUT_UID")
-            .field(
-                "modem_peri_timeout_uid",
-                &format_args!("{}", self.modem_peri_timeout_uid().bits()),
-            )
+            .field("modem_peri_timeout_uid", &self.modem_peri_timeout_uid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODEM_PERI_TIMEOUT_UID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MODEM_PERI_TIMEOUT_UID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`modem_peri_timeout_uid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MODEM_PERI_TIMEOUT_UID_SPEC;
 impl crate::RegisterSpec for MODEM_PERI_TIMEOUT_UID_SPEC {
diff --git a/esp32c6/src/hp_sys/retention_conf.rs b/esp32c6/src/hp_sys/retention_conf.rs
index e5c2fceabe..75bf65154c 100644
--- a/esp32c6/src/hp_sys/retention_conf.rs
+++ b/esp32c6/src/hp_sys/retention_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_CONF")
-            .field(
-                "retention_disable",
-                &format_args!("{}", self.retention_disable().bit()),
-            )
+            .field("retention_disable", &self.retention_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit as 1 to disable retention function. Not disable by default."]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/rnd_eco.rs b/esp32c6/src/hp_sys/rnd_eco.rs
index cf663fec03..3163d9f0b8 100644
--- a/esp32c6/src/hp_sys/rnd_eco.rs
+++ b/esp32c6/src/hp_sys/rnd_eco.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO")
-            .field("redcy_ena", &format_args!("{}", self.redcy_ena().bit()))
-            .field(
-                "redcy_result",
-                &format_args!("{}", self.redcy_result().bit()),
-            )
+            .field("redcy_ena", &self.redcy_ena())
+            .field("redcy_result", &self.redcy_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Only reserved for ECO."]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/rnd_eco_high.rs b/esp32c6/src/hp_sys/rnd_eco_high.rs
index d2138667f2..acb852af6d 100644
--- a/esp32c6/src/hp_sys/rnd_eco_high.rs
+++ b/esp32c6/src/hp_sys/rnd_eco_high.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_HIGH")
-            .field("redcy_high", &format_args!("{}", self.redcy_high().bits()))
+            .field("redcy_high", &self.redcy_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Only reserved for ECO."]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/rnd_eco_low.rs b/esp32c6/src/hp_sys/rnd_eco_low.rs
index 6accf663f9..f3dcb2ff4b 100644
--- a/esp32c6/src/hp_sys/rnd_eco_low.rs
+++ b/esp32c6/src/hp_sys/rnd_eco_low.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_LOW")
-            .field("redcy_low", &format_args!("{}", self.redcy_low().bits()))
+            .field("redcy_low", &self.redcy_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Only reserved for ECO."]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/rom_table.rs b/esp32c6/src/hp_sys/rom_table.rs
index 38b28290c0..1db8b39582 100644
--- a/esp32c6/src/hp_sys/rom_table.rs
+++ b/esp32c6/src/hp_sys/rom_table.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_TABLE")
-            .field("rom_table", &format_args!("{}", self.rom_table().bits()))
+            .field("rom_table", &self.rom_table())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_TABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - XXXX"]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/rom_table_lock.rs b/esp32c6/src/hp_sys/rom_table_lock.rs
index b83bdf0cb9..ea4b9e9375 100644
--- a/esp32c6/src/hp_sys/rom_table_lock.rs
+++ b/esp32c6/src/hp_sys/rom_table_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_TABLE_LOCK")
-            .field(
-                "rom_table_lock",
-                &format_args!("{}", self.rom_table_lock().bit()),
-            )
+            .field("rom_table_lock", &self.rom_table_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_TABLE_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - XXXX"]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/sdio_ctrl.rs b/esp32c6/src/hp_sys/sdio_ctrl.rs
index c46bd632d7..64e2739889 100644
--- a/esp32c6/src/hp_sys/sdio_ctrl.rs
+++ b/esp32c6/src/hp_sys/sdio_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_CTRL")
-            .field(
-                "dis_sdio_prob",
-                &format_args!("{}", self.dis_sdio_prob().bit()),
-            )
-            .field(
-                "sdio_win_access_en",
-                &format_args!("{}", self.sdio_win_access_en().bit()),
-            )
+            .field("dis_sdio_prob", &self.dis_sdio_prob())
+            .field("sdio_win_access_en", &self.sdio_win_access_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit as 1 to disable SDIO_PROB function. disable by default."]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/sec_dpa_conf.rs b/esp32c6/src/hp_sys/sec_dpa_conf.rs
index ecc8448e07..d5b7dbbf25 100644
--- a/esp32c6/src/hp_sys/sec_dpa_conf.rs
+++ b/esp32c6/src/hp_sys/sec_dpa_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_DPA_CONF")
-            .field(
-                "sec_dpa_level",
-                &format_args!("{}", self.sec_dpa_level().bits()),
-            )
-            .field(
-                "sec_dpa_cfg_sel",
-                &format_args!("{}", self.sec_dpa_cfg_sel().bit()),
-            )
+            .field("sec_dpa_level", &self.sec_dpa_level())
+            .field("sec_dpa_cfg_sel", &self.sec_dpa_cfg_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_DPA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger the number, the stronger the ability to resist DPA attacks and the higher the security level, but it will increase the computational overhead of the hardware crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0."]
     #[inline(always)]
diff --git a/esp32c6/src/hp_sys/sram_usage_conf.rs b/esp32c6/src/hp_sys/sram_usage_conf.rs
index fcf7b3872f..a2025712e2 100644
--- a/esp32c6/src/hp_sys/sram_usage_conf.rs
+++ b/esp32c6/src/hp_sys/sram_usage_conf.rs
@@ -33,21 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_USAGE_CONF")
-            .field("cache_usage", &format_args!("{}", self.cache_usage().bit()))
-            .field("sram_usage", &format_args!("{}", self.sram_usage().bits()))
-            .field(
-                "mac_dump_alloc",
-                &format_args!("{}", self.mac_dump_alloc().bit()),
-            )
+            .field("cache_usage", &self.cache_usage())
+            .field("sram_usage", &self.sram_usage())
+            .field("mac_dump_alloc", &self.mac_dump_alloc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_USAGE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:11 - 0: cpu use hp-memory. 1:mac-dump accessing hp-memory."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/clk_conf.rs b/esp32c6/src/i2c0/clk_conf.rs
index 0c369fb990..8575bb85bf 100644
--- a/esp32c6/src/i2c0/clk_conf.rs
+++ b/esp32c6/src/i2c0/clk_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bit()))
-            .field("sclk_active", &format_args!("{}", self.sclk_active().bit()))
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_active", &self.sclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/comd.rs b/esp32c6/src/i2c0/comd.rs
index 6f909ae304..980d858d87 100644
--- a/esp32c6/src/i2c0/comd.rs
+++ b/esp32c6/src/i2c0/comd.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMD")
-            .field("command", &format_args!("{}", self.command().bits()))
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This is the content of command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/ctr.rs b/esp32c6/src/i2c0/ctr.rs
index 3ba4f612c1..4500b14379 100644
--- a/esp32c6/src/i2c0/ctr.rs
+++ b/esp32c6/src/i2c0/ctr.rs
@@ -122,57 +122,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTR")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field(
-                "sample_scl_level",
-                &format_args!("{}", self.sample_scl_level().bit()),
-            )
-            .field(
-                "rx_full_ack_level",
-                &format_args!("{}", self.rx_full_ack_level().bit()),
-            )
-            .field("ms_mode", &format_args!("{}", self.ms_mode().bit()))
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "arbitration_en",
-                &format_args!("{}", self.arbitration_en().bit()),
-            )
-            .field(
-                "slv_tx_auto_start_en",
-                &format_args!("{}", self.slv_tx_auto_start_en().bit()),
-            )
-            .field(
-                "addr_10bit_rw_check_en",
-                &format_args!("{}", self.addr_10bit_rw_check_en().bit()),
-            )
-            .field(
-                "addr_broadcasting_en",
-                &format_args!("{}", self.addr_broadcasting_en().bit()),
-            )
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("sample_scl_level", &self.sample_scl_level())
+            .field("rx_full_ack_level", &self.rx_full_ack_level())
+            .field("ms_mode", &self.ms_mode())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("clk_en", &self.clk_en())
+            .field("arbitration_en", &self.arbitration_en())
+            .field("slv_tx_auto_start_en", &self.slv_tx_auto_start_en())
+            .field("addr_10bit_rw_check_en", &self.addr_10bit_rw_check_en())
+            .field("addr_broadcasting_en", &self.addr_broadcasting_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: direct output, 0: open drain output."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/data.rs b/esp32c6/src/i2c0/data.rs
index 098982488f..ffd32b29d3 100644
--- a/esp32c6/src/i2c0/data.rs
+++ b/esp32c6/src/i2c0/data.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field("fifo_rdata", &format_args!("{}", self.fifo_rdata().bits()))
+            .field("fifo_rdata", &self.fifo_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value of rx FIFO read data."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/date.rs b/esp32c6/src/i2c0/date.rs
index f0a0b291ee..2541eeb94a 100644
--- a/esp32c6/src/i2c0/date.rs
+++ b/esp32c6/src/i2c0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/i2c0/fifo_conf.rs b/esp32c6/src/i2c0/fifo_conf.rs
index a676b90a14..92deed8594 100644
--- a/esp32c6/src/i2c0/fifo_conf.rs
+++ b/esp32c6/src/i2c0/fifo_conf.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CONF")
-            .field(
-                "rxfifo_wm_thrhd",
-                &format_args!("{}", self.rxfifo_wm_thrhd().bits()),
-            )
-            .field(
-                "txfifo_wm_thrhd",
-                &format_args!("{}", self.txfifo_wm_thrhd().bits()),
-            )
-            .field("nonfifo_en", &format_args!("{}", self.nonfifo_en().bit()))
-            .field(
-                "fifo_addr_cfg_en",
-                &format_args!("{}", self.fifo_addr_cfg_en().bit()),
-            )
-            .field("rx_fifo_rst", &format_args!("{}", self.rx_fifo_rst().bit()))
-            .field("tx_fifo_rst", &format_args!("{}", self.tx_fifo_rst().bit()))
-            .field("fifo_prt_en", &format_args!("{}", self.fifo_prt_en().bit()))
+            .field("rxfifo_wm_thrhd", &self.rxfifo_wm_thrhd())
+            .field("txfifo_wm_thrhd", &self.txfifo_wm_thrhd())
+            .field("nonfifo_en", &self.nonfifo_en())
+            .field("fifo_addr_cfg_en", &self.fifo_addr_cfg_en())
+            .field("rx_fifo_rst", &self.rx_fifo_rst())
+            .field("tx_fifo_rst", &self.tx_fifo_rst())
+            .field("fifo_prt_en", &self.fifo_prt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[4:0\\], reg_rxfifo_wm_int_raw bit will be valid."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/fifo_st.rs b/esp32c6/src/i2c0/fifo_st.rs
index 40f2594a2b..03188e5485 100644
--- a/esp32c6/src/i2c0/fifo_st.rs
+++ b/esp32c6/src/i2c0/fifo_st.rs
@@ -41,35 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_ST")
-            .field(
-                "rxfifo_raddr",
-                &format_args!("{}", self.rxfifo_raddr().bits()),
-            )
-            .field(
-                "rxfifo_waddr",
-                &format_args!("{}", self.rxfifo_waddr().bits()),
-            )
-            .field(
-                "txfifo_raddr",
-                &format_args!("{}", self.txfifo_raddr().bits()),
-            )
-            .field(
-                "txfifo_waddr",
-                &format_args!("{}", self.txfifo_waddr().bits()),
-            )
-            .field(
-                "slave_rw_point",
-                &format_args!("{}", self.slave_rw_point().bits()),
-            )
+            .field("rxfifo_raddr", &self.rxfifo_raddr())
+            .field("rxfifo_waddr", &self.rxfifo_waddr())
+            .field("txfifo_raddr", &self.txfifo_raddr())
+            .field("txfifo_waddr", &self.txfifo_waddr())
+            .field("slave_rw_point", &self.slave_rw_point())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "FIFO status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_ST_SPEC;
 impl crate::RegisterSpec for FIFO_ST_SPEC {
diff --git a/esp32c6/src/i2c0/filter_cfg.rs b/esp32c6/src/i2c0/filter_cfg.rs
index b05ae9a4bf..98bdaa5979 100644
--- a/esp32c6/src/i2c0/filter_cfg.rs
+++ b/esp32c6/src/i2c0/filter_cfg.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CFG")
-            .field(
-                "scl_filter_thres",
-                &format_args!("{}", self.scl_filter_thres().bits()),
-            )
-            .field(
-                "sda_filter_thres",
-                &format_args!("{}", self.sda_filter_thres().bits()),
-            )
-            .field(
-                "scl_filter_en",
-                &format_args!("{}", self.scl_filter_en().bit()),
-            )
-            .field(
-                "sda_filter_en",
-                &format_args!("{}", self.sda_filter_en().bit()),
-            )
+            .field("scl_filter_thres", &self.scl_filter_thres())
+            .field("sda_filter_thres", &self.sda_filter_thres())
+            .field("scl_filter_en", &self.scl_filter_en())
+            .field("sda_filter_en", &self.sda_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/int_ena.rs b/esp32c6/src/i2c0/int_ena.rs
index 603538eb38..d4fcbf46ce 100644
--- a/esp32c6/src/i2c0/int_ena.rs
+++ b/esp32c6/src/i2c0/int_ena.rs
@@ -179,58 +179,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
-            .field(
-                "general_call",
-                &format_args!("{}", self.general_call().bit()),
-            )
-            .field(
-                "slave_addr_unmatch",
-                &format_args!("{}", self.slave_addr_unmatch().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
+            .field("general_call", &self.general_call())
+            .field("slave_addr_unmatch", &self.slave_addr_unmatch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/int_raw.rs b/esp32c6/src/i2c0/int_raw.rs
index d6d6eff429..30e6675e53 100644
--- a/esp32c6/src/i2c0/int_raw.rs
+++ b/esp32c6/src/i2c0/int_raw.rs
@@ -139,58 +139,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
-            .field(
-                "general_call",
-                &format_args!("{}", self.general_call().bit()),
-            )
-            .field(
-                "slave_addr_unmatch",
-                &format_args!("{}", self.slave_addr_unmatch().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
+            .field("general_call", &self.general_call())
+            .field("slave_addr_unmatch", &self.slave_addr_unmatch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32c6/src/i2c0/int_st.rs b/esp32c6/src/i2c0/int_st.rs
index 553dd4fdef..6a88399e28 100644
--- a/esp32c6/src/i2c0/int_st.rs
+++ b/esp32c6/src/i2c0/int_st.rs
@@ -139,58 +139,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
-            .field(
-                "general_call",
-                &format_args!("{}", self.general_call().bit()),
-            )
-            .field(
-                "slave_addr_unmatch",
-                &format_args!("{}", self.slave_addr_unmatch().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
+            .field("general_call", &self.general_call())
+            .field("slave_addr_unmatch", &self.slave_addr_unmatch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of captured I2C communication events\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/i2c0/rxfifo_start_addr.rs b/esp32c6/src/i2c0/rxfifo_start_addr.rs
index 634e8c8360..be2fa3cb09 100644
--- a/esp32c6/src/i2c0/rxfifo_start_addr.rs
+++ b/esp32c6/src/i2c0/rxfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXFIFO_START_ADDR")
-            .field(
-                "rxfifo_start_addr",
-                &format_args!("{}", self.rxfifo_start_addr().bits()),
-            )
+            .field("rxfifo_start_addr", &self.rxfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C RXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for RXFIFO_START_ADDR_SPEC {
diff --git a/esp32c6/src/i2c0/scl_high_period.rs b/esp32c6/src/i2c0/scl_high_period.rs
index 2af2564e19..3155621a91 100644
--- a/esp32c6/src/i2c0/scl_high_period.rs
+++ b/esp32c6/src/i2c0/scl_high_period.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH_PERIOD")
-            .field(
-                "scl_high_period",
-                &format_args!("{}", self.scl_high_period().bits()),
-            )
-            .field(
-                "scl_wait_high_period",
-                &format_args!("{}", self.scl_wait_high_period().bits()),
-            )
+            .field("scl_high_period", &self.scl_high_period())
+            .field("scl_wait_high_period", &self.scl_wait_high_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/scl_low_period.rs b/esp32c6/src/i2c0/scl_low_period.rs
index bb4cd05e6d..c75461f0c7 100644
--- a/esp32c6/src/i2c0/scl_low_period.rs
+++ b/esp32c6/src/i2c0/scl_low_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW_PERIOD")
-            .field(
-                "scl_low_period",
-                &format_args!("{}", self.scl_low_period().bits()),
-            )
+            .field("scl_low_period", &self.scl_low_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/scl_main_st_time_out.rs b/esp32c6/src/i2c0/scl_main_st_time_out.rs
index 7c392d273a..99069d3ce8 100644
--- a/esp32c6/src/i2c0/scl_main_st_time_out.rs
+++ b/esp32c6/src/i2c0/scl_main_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_MAIN_ST_TIME_OUT")
-            .field(
-                "scl_main_st_to_i2c",
-                &format_args!("{}", self.scl_main_st_to_i2c().bits()),
-            )
+            .field("scl_main_st_to_i2c", &self.scl_main_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_MAIN_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23"]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/scl_rstart_setup.rs b/esp32c6/src/i2c0/scl_rstart_setup.rs
index 5f61d4fc91..63ddddc0f2 100644
--- a/esp32c6/src/i2c0/scl_rstart_setup.rs
+++ b/esp32c6/src/i2c0/scl_rstart_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_RSTART_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_RSTART_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/scl_sp_conf.rs b/esp32c6/src/i2c0/scl_sp_conf.rs
index e3cdc353bf..492452e245 100644
--- a/esp32c6/src/i2c0/scl_sp_conf.rs
+++ b/esp32c6/src/i2c0/scl_sp_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_SP_CONF")
-            .field(
-                "scl_rst_slv_en",
-                &format_args!("{}", self.scl_rst_slv_en().bit()),
-            )
-            .field(
-                "scl_rst_slv_num",
-                &format_args!("{}", self.scl_rst_slv_num().bits()),
-            )
-            .field("scl_pd_en", &format_args!("{}", self.scl_pd_en().bit()))
-            .field("sda_pd_en", &format_args!("{}", self.sda_pd_en().bit()))
+            .field("scl_rst_slv_en", &self.scl_rst_slv_en())
+            .field("scl_rst_slv_num", &self.scl_rst_slv_num())
+            .field("scl_pd_en", &self.scl_pd_en())
+            .field("sda_pd_en", &self.sda_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_SP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/scl_st_time_out.rs b/esp32c6/src/i2c0/scl_st_time_out.rs
index ba02a4a885..e56dd94c72 100644
--- a/esp32c6/src/i2c0/scl_st_time_out.rs
+++ b/esp32c6/src/i2c0/scl_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_ST_TIME_OUT")
-            .field(
-                "scl_st_to_i2c",
-                &format_args!("{}", self.scl_st_to_i2c().bits()),
-            )
+            .field("scl_st_to_i2c", &self.scl_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The threshold value of SCL_FSM state unchanged period. It should be o more than 23"]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/scl_start_hold.rs b/esp32c6/src/i2c0/scl_start_hold.rs
index eaa7d6ef78..073d03f4ca 100644
--- a/esp32c6/src/i2c0/scl_start_hold.rs
+++ b/esp32c6/src/i2c0/scl_start_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/scl_stop_hold.rs b/esp32c6/src/i2c0/scl_stop_hold.rs
index edfbb10e29..3a115f7912 100644
--- a/esp32c6/src/i2c0/scl_stop_hold.rs
+++ b/esp32c6/src/i2c0/scl_stop_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the delay after the STOP condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/scl_stop_setup.rs b/esp32c6/src/i2c0/scl_stop_setup.rs
index f231319c28..592044b6a2 100644
--- a/esp32c6/src/i2c0/scl_stop_setup.rs
+++ b/esp32c6/src/i2c0/scl_stop_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/scl_stretch_conf.rs b/esp32c6/src/i2c0/scl_stretch_conf.rs
index 41ef0b914c..541e31a624 100644
--- a/esp32c6/src/i2c0/scl_stretch_conf.rs
+++ b/esp32c6/src/i2c0/scl_stretch_conf.rs
@@ -46,31 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STRETCH_CONF")
-            .field(
-                "stretch_protect_num",
-                &format_args!("{}", self.stretch_protect_num().bits()),
-            )
-            .field(
-                "slave_scl_stretch_en",
-                &format_args!("{}", self.slave_scl_stretch_en().bit()),
-            )
-            .field(
-                "slave_byte_ack_ctl_en",
-                &format_args!("{}", self.slave_byte_ack_ctl_en().bit()),
-            )
-            .field(
-                "slave_byte_ack_lvl",
-                &format_args!("{}", self.slave_byte_ack_lvl().bit()),
-            )
+            .field("stretch_protect_num", &self.stretch_protect_num())
+            .field("slave_scl_stretch_en", &self.slave_scl_stretch_en())
+            .field("slave_byte_ack_ctl_en", &self.slave_byte_ack_ctl_en())
+            .field("slave_byte_ack_lvl", &self.slave_byte_ack_lvl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STRETCH_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - Configure the period of I2C slave stretching SCL line."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/sda_hold.rs b/esp32c6/src/i2c0/sda_hold.rs
index b16485e33b..817872197e 100644
--- a/esp32c6/src/i2c0/sda_hold.rs
+++ b/esp32c6/src/i2c0/sda_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time to hold the data after the negative edge of SCL, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/sda_sample.rs b/esp32c6/src/i2c0/sda_sample.rs
index 5a56fc1aa2..a8bd733614 100644
--- a/esp32c6/src/i2c0/sda_sample.rs
+++ b/esp32c6/src/i2c0/sda_sample.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_SAMPLE")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SDA is sampled, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/slave_addr.rs b/esp32c6/src/i2c0/slave_addr.rs
index 004dabd9bb..04cdd14f36 100644
--- a/esp32c6/src/i2c0/slave_addr.rs
+++ b/esp32c6/src/i2c0/slave_addr.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE_ADDR")
-            .field("slave_addr", &format_args!("{}", self.slave_addr().bits()))
-            .field(
-                "addr_10bit_en",
-                &format_args!("{}", self.addr_10bit_en().bit()),
-            )
+            .field("slave_addr", &self.slave_addr())
+            .field("addr_10bit_en", &self.addr_10bit_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - When configured as an I2C Slave, this field is used to configure the slave address."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/sr.rs b/esp32c6/src/i2c0/sr.rs
index 17b1957f57..bcd6b76f37 100644
--- a/esp32c6/src/i2c0/sr.rs
+++ b/esp32c6/src/i2c0/sr.rs
@@ -76,37 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR")
-            .field("resp_rec", &format_args!("{}", self.resp_rec().bit()))
-            .field("slave_rw", &format_args!("{}", self.slave_rw().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field(
-                "slave_addressed",
-                &format_args!("{}", self.slave_addressed().bit()),
-            )
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field(
-                "stretch_cause",
-                &format_args!("{}", self.stretch_cause().bits()),
-            )
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field(
-                "scl_main_state_last",
-                &format_args!("{}", self.scl_main_state_last().bits()),
-            )
-            .field(
-                "scl_state_last",
-                &format_args!("{}", self.scl_state_last().bits()),
-            )
+            .field("resp_rec", &self.resp_rec())
+            .field("slave_rw", &self.slave_rw())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("slave_addressed", &self.slave_addressed())
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("stretch_cause", &self.stretch_cause())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("scl_main_state_last", &self.scl_main_state_last())
+            .field("scl_state_last", &self.scl_state_last())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Describe I2C work status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SR_SPEC;
 impl crate::RegisterSpec for SR_SPEC {
diff --git a/esp32c6/src/i2c0/to.rs b/esp32c6/src/i2c0/to.rs
index 92f73cdd2b..cf95ff843d 100644
--- a/esp32c6/src/i2c0/to.rs
+++ b/esp32c6/src/i2c0/to.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO")
-            .field(
-                "time_out_value",
-                &format_args!("{}", self.time_out_value().bits()),
-            )
-            .field("time_out_en", &format_args!("{}", self.time_out_en().bit()))
+            .field("time_out_value", &self.time_out_value())
+            .field("time_out_en", &self.time_out_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to configure the timeout for receiving a data bit in APB clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/i2c0/txfifo_start_addr.rs b/esp32c6/src/i2c0/txfifo_start_addr.rs
index 8df0b6828e..c7cd4f0ea5 100644
--- a/esp32c6/src/i2c0/txfifo_start_addr.rs
+++ b/esp32c6/src/i2c0/txfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXFIFO_START_ADDR")
-            .field(
-                "txfifo_start_addr",
-                &format_args!("{}", self.txfifo_start_addr().bits()),
-            )
+            .field("txfifo_start_addr", &self.txfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C TXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for TXFIFO_START_ADDR_SPEC {
diff --git a/esp32c6/src/i2s0/conf_sigle_data.rs b/esp32c6/src/i2s0/conf_sigle_data.rs
index f979345988..3c75f59255 100644
--- a/esp32c6/src/i2s0/conf_sigle_data.rs
+++ b/esp32c6/src/i2s0/conf_sigle_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_SIGLE_DATA")
-            .field(
-                "single_data",
-                &format_args!("{}", self.single_data().bits()),
-            )
+            .field("single_data", &self.single_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SIGLE_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The configured constant channel data to be sent out."]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/date.rs b/esp32c6/src/i2s0/date.rs
index 7dea6876da..9281f1275b 100644
--- a/esp32c6/src/i2s0/date.rs
+++ b/esp32c6/src/i2s0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/i2s0/etm_conf.rs b/esp32c6/src/i2s0/etm_conf.rs
index ba87038a24..456f1152f9 100644
--- a/esp32c6/src/i2s0/etm_conf.rs
+++ b/esp32c6/src/i2s0/etm_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_CONF")
-            .field(
-                "etm_tx_send_word_num",
-                &format_args!("{}", self.etm_tx_send_word_num().bits()),
-            )
-            .field(
-                "etm_rx_receive_word_num",
-                &format_args!("{}", self.etm_rx_receive_word_num().bits()),
-            )
+            .field("etm_tx_send_word_num", &self.etm_tx_send_word_num())
+            .field("etm_rx_receive_word_num", &self.etm_rx_receive_word_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num\\[9:0\\], i2s will trigger an etm event."]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/int_ena.rs b/esp32c6/src/i2s0/int_ena.rs
index ffbc92bacc..0a538b90e5 100644
--- a/esp32c6/src/i2s0/int_ena.rs
+++ b/esp32c6/src/i2s0/int_ena.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/int_raw.rs b/esp32c6/src/i2s0/int_raw.rs
index 7ec2d42cfd..e69602c0be 100644
--- a/esp32c6/src/i2s0/int_raw.rs
+++ b/esp32c6/src/i2s0/int_raw.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32c6/src/i2s0/int_st.rs b/esp32c6/src/i2s0/int_st.rs
index 5eac7b9c9d..ddf72a352e 100644
--- a/esp32c6/src/i2s0/int_st.rs
+++ b/esp32c6/src/i2s0/int_st.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/i2s0/lc_hung_conf.rs b/esp32c6/src/i2s0/lc_hung_conf.rs
index 060b1cdb60..71f0c84fa7 100644
--- a/esp32c6/src/i2s0/lc_hung_conf.rs
+++ b/esp32c6/src/i2s0/lc_hung_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_HUNG_CONF")
-            .field(
-                "lc_fifo_timeout",
-                &format_args!("{}", self.lc_fifo_timeout().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_shift",
-                &format_args!("{}", self.lc_fifo_timeout_shift().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_ena",
-                &format_args!("{}", self.lc_fifo_timeout_ena().bit()),
-            )
+            .field("lc_fifo_timeout", &self.lc_fifo_timeout())
+            .field("lc_fifo_timeout_shift", &self.lc_fifo_timeout_shift())
+            .field("lc_fifo_timeout_ena", &self.lc_fifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/rx_clkm_conf.rs b/esp32c6/src/i2s0/rx_clkm_conf.rs
index 79ff9b2470..5bbb7a360a 100644
--- a/esp32c6/src/i2s0/rx_clkm_conf.rs
+++ b/esp32c6/src/i2s0/rx_clkm_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CLKM_CONF")
-            .field(
-                "rx_clkm_div_num",
-                &format_args!("{}", self.rx_clkm_div_num().bits()),
-            )
-            .field(
-                "rx_clk_active",
-                &format_args!("{}", self.rx_clk_active().bit()),
-            )
-            .field("rx_clk_sel", &format_args!("{}", self.rx_clk_sel().bits()))
-            .field("mclk_sel", &format_args!("{}", self.mclk_sel().bit()))
+            .field("rx_clkm_div_num", &self.rx_clkm_div_num())
+            .field("rx_clk_active", &self.rx_clk_active())
+            .field("rx_clk_sel", &self.rx_clk_sel())
+            .field("mclk_sel", &self.mclk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral I2S clock divider value"]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/rx_clkm_div_conf.rs b/esp32c6/src/i2s0/rx_clkm_div_conf.rs
index 9dc32721ed..d4f0ee53bc 100644
--- a/esp32c6/src/i2s0/rx_clkm_div_conf.rs
+++ b/esp32c6/src/i2s0/rx_clkm_div_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CLKM_DIV_CONF")
-            .field(
-                "rx_clkm_div_z",
-                &format_args!("{}", self.rx_clkm_div_z().bits()),
-            )
-            .field(
-                "rx_clkm_div_y",
-                &format_args!("{}", self.rx_clkm_div_y().bits()),
-            )
-            .field(
-                "rx_clkm_div_x",
-                &format_args!("{}", self.rx_clkm_div_x().bits()),
-            )
-            .field(
-                "rx_clkm_div_yn1",
-                &format_args!("{}", self.rx_clkm_div_yn1().bit()),
-            )
+            .field("rx_clkm_div_z", &self.rx_clkm_div_z())
+            .field("rx_clkm_div_y", &self.rx_clkm_div_y())
+            .field("rx_clkm_div_x", &self.rx_clkm_div_x())
+            .field("rx_clkm_div_yn1", &self.rx_clkm_div_yn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CLKM_DIV_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/rx_conf.rs b/esp32c6/src/i2s0/rx_conf.rs
index 87a73e205b..bc22e600af 100644
--- a/esp32c6/src/i2s0/rx_conf.rs
+++ b/esp32c6/src/i2s0/rx_conf.rs
@@ -147,60 +147,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CONF")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field(
-                "rx_slave_mod",
-                &format_args!("{}", self.rx_slave_mod().bit()),
-            )
-            .field("rx_mono", &format_args!("{}", self.rx_mono().bit()))
-            .field(
-                "rx_big_endian",
-                &format_args!("{}", self.rx_big_endian().bit()),
-            )
-            .field("rx_update", &format_args!("{}", self.rx_update().bit()))
-            .field(
-                "rx_mono_fst_vld",
-                &format_args!("{}", self.rx_mono_fst_vld().bit()),
-            )
-            .field(
-                "rx_pcm_conf",
-                &format_args!("{}", self.rx_pcm_conf().bits()),
-            )
-            .field(
-                "rx_pcm_bypass",
-                &format_args!("{}", self.rx_pcm_bypass().bit()),
-            )
-            .field(
-                "rx_stop_mode",
-                &format_args!("{}", self.rx_stop_mode().bits()),
-            )
-            .field(
-                "rx_left_align",
-                &format_args!("{}", self.rx_left_align().bit()),
-            )
-            .field(
-                "rx_24_fill_en",
-                &format_args!("{}", self.rx_24_fill_en().bit()),
-            )
-            .field(
-                "rx_ws_idle_pol",
-                &format_args!("{}", self.rx_ws_idle_pol().bit()),
-            )
-            .field(
-                "rx_bit_order",
-                &format_args!("{}", self.rx_bit_order().bit()),
-            )
-            .field("rx_tdm_en", &format_args!("{}", self.rx_tdm_en().bit()))
-            .field("rx_pdm_en", &format_args!("{}", self.rx_pdm_en().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("rx_slave_mod", &self.rx_slave_mod())
+            .field("rx_mono", &self.rx_mono())
+            .field("rx_big_endian", &self.rx_big_endian())
+            .field("rx_update", &self.rx_update())
+            .field("rx_mono_fst_vld", &self.rx_mono_fst_vld())
+            .field("rx_pcm_conf", &self.rx_pcm_conf())
+            .field("rx_pcm_bypass", &self.rx_pcm_bypass())
+            .field("rx_stop_mode", &self.rx_stop_mode())
+            .field("rx_left_align", &self.rx_left_align())
+            .field("rx_24_fill_en", &self.rx_24_fill_en())
+            .field("rx_ws_idle_pol", &self.rx_ws_idle_pol())
+            .field("rx_bit_order", &self.rx_bit_order())
+            .field("rx_tdm_en", &self.rx_tdm_en())
+            .field("rx_pdm_en", &self.rx_pdm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset receiver"]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/rx_conf1.rs b/esp32c6/src/i2s0/rx_conf1.rs
index 24c13494fb..31fa7a1f88 100644
--- a/esp32c6/src/i2s0/rx_conf1.rs
+++ b/esp32c6/src/i2s0/rx_conf1.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CONF1")
-            .field(
-                "rx_tdm_ws_width",
-                &format_args!("{}", self.rx_tdm_ws_width().bits()),
-            )
-            .field(
-                "rx_bck_div_num",
-                &format_args!("{}", self.rx_bck_div_num().bits()),
-            )
-            .field(
-                "rx_bits_mod",
-                &format_args!("{}", self.rx_bits_mod().bits()),
-            )
-            .field(
-                "rx_half_sample_bits",
-                &format_args!("{}", self.rx_half_sample_bits().bits()),
-            )
-            .field(
-                "rx_tdm_chan_bits",
-                &format_args!("{}", self.rx_tdm_chan_bits().bits()),
-            )
-            .field(
-                "rx_msb_shift",
-                &format_args!("{}", self.rx_msb_shift().bit()),
-            )
+            .field("rx_tdm_ws_width", &self.rx_tdm_ws_width())
+            .field("rx_bck_div_num", &self.rx_bck_div_num())
+            .field("rx_bits_mod", &self.rx_bits_mod())
+            .field("rx_half_sample_bits", &self.rx_half_sample_bits())
+            .field("rx_tdm_chan_bits", &self.rx_tdm_chan_bits())
+            .field("rx_msb_shift", &self.rx_msb_shift())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/rx_tdm_ctrl.rs b/esp32c6/src/i2s0/rx_tdm_ctrl.rs
index fe01f97aeb..0d18f522f2 100644
--- a/esp32c6/src/i2s0/rx_tdm_ctrl.rs
+++ b/esp32c6/src/i2s0/rx_tdm_ctrl.rs
@@ -161,83 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_TDM_CTRL")
-            .field(
-                "rx_tdm_pdm_chan0_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan0_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan1_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan1_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan2_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan2_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan3_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan3_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan4_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan4_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan5_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan5_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan6_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan6_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan7_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan7_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan8_en",
-                &format_args!("{}", self.rx_tdm_chan8_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan9_en",
-                &format_args!("{}", self.rx_tdm_chan9_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan10_en",
-                &format_args!("{}", self.rx_tdm_chan10_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan11_en",
-                &format_args!("{}", self.rx_tdm_chan11_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan12_en",
-                &format_args!("{}", self.rx_tdm_chan12_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan13_en",
-                &format_args!("{}", self.rx_tdm_chan13_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan14_en",
-                &format_args!("{}", self.rx_tdm_chan14_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan15_en",
-                &format_args!("{}", self.rx_tdm_chan15_en().bit()),
-            )
-            .field(
-                "rx_tdm_tot_chan_num",
-                &format_args!("{}", self.rx_tdm_tot_chan_num().bits()),
-            )
+            .field("rx_tdm_pdm_chan0_en", &self.rx_tdm_pdm_chan0_en())
+            .field("rx_tdm_pdm_chan1_en", &self.rx_tdm_pdm_chan1_en())
+            .field("rx_tdm_pdm_chan2_en", &self.rx_tdm_pdm_chan2_en())
+            .field("rx_tdm_pdm_chan3_en", &self.rx_tdm_pdm_chan3_en())
+            .field("rx_tdm_pdm_chan4_en", &self.rx_tdm_pdm_chan4_en())
+            .field("rx_tdm_pdm_chan5_en", &self.rx_tdm_pdm_chan5_en())
+            .field("rx_tdm_pdm_chan6_en", &self.rx_tdm_pdm_chan6_en())
+            .field("rx_tdm_pdm_chan7_en", &self.rx_tdm_pdm_chan7_en())
+            .field("rx_tdm_chan8_en", &self.rx_tdm_chan8_en())
+            .field("rx_tdm_chan9_en", &self.rx_tdm_chan9_en())
+            .field("rx_tdm_chan10_en", &self.rx_tdm_chan10_en())
+            .field("rx_tdm_chan11_en", &self.rx_tdm_chan11_en())
+            .field("rx_tdm_chan12_en", &self.rx_tdm_chan12_en())
+            .field("rx_tdm_chan13_en", &self.rx_tdm_chan13_en())
+            .field("rx_tdm_chan14_en", &self.rx_tdm_chan14_en())
+            .field("rx_tdm_chan15_en", &self.rx_tdm_chan15_en())
+            .field("rx_tdm_tot_chan_num", &self.rx_tdm_tot_chan_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_TDM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/rx_timing.rs b/esp32c6/src/i2s0/rx_timing.rs
index 66daf81e08..fe227b5840 100644
--- a/esp32c6/src/i2s0/rx_timing.rs
+++ b/esp32c6/src/i2s0/rx_timing.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_TIMING")
-            .field(
-                "rx_sd_in_dm",
-                &format_args!("{}", self.rx_sd_in_dm().bits()),
-            )
-            .field(
-                "rx_ws_out_dm",
-                &format_args!("{}", self.rx_ws_out_dm().bits()),
-            )
-            .field(
-                "rx_bck_out_dm",
-                &format_args!("{}", self.rx_bck_out_dm().bits()),
-            )
-            .field(
-                "rx_ws_in_dm",
-                &format_args!("{}", self.rx_ws_in_dm().bits()),
-            )
-            .field(
-                "rx_bck_in_dm",
-                &format_args!("{}", self.rx_bck_in_dm().bits()),
-            )
+            .field("rx_sd_in_dm", &self.rx_sd_in_dm())
+            .field("rx_ws_out_dm", &self.rx_ws_out_dm())
+            .field("rx_bck_out_dm", &self.rx_bck_out_dm())
+            .field("rx_ws_in_dm", &self.rx_ws_in_dm())
+            .field("rx_bck_in_dm", &self.rx_bck_in_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/rxeof_num.rs b/esp32c6/src/i2s0/rxeof_num.rs
index 06f6d22ff0..b9674d5891 100644
--- a/esp32c6/src/i2s0/rxeof_num.rs
+++ b/esp32c6/src/i2s0/rxeof_num.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXEOF_NUM")
-            .field("rx_eof_num", &format_args!("{}", self.rx_eof_num().bits()))
+            .field("rx_eof_num", &self.rx_eof_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXEOF_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/state.rs b/esp32c6/src/i2s0/state.rs
index 7988d4067c..d16247a40d 100644
--- a/esp32c6/src/i2s0/state.rs
+++ b/esp32c6/src/i2s0/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("tx_idle", &format_args!("{}", self.tx_idle().bit()))
+            .field("tx_idle", &self.tx_idle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S TX status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32c6/src/i2s0/tx_clkm_conf.rs b/esp32c6/src/i2s0/tx_clkm_conf.rs
index ef82d04116..2584244722 100644
--- a/esp32c6/src/i2s0/tx_clkm_conf.rs
+++ b/esp32c6/src/i2s0/tx_clkm_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CLKM_CONF")
-            .field(
-                "tx_clkm_div_num",
-                &format_args!("{}", self.tx_clkm_div_num().bits()),
-            )
-            .field(
-                "tx_clk_active",
-                &format_args!("{}", self.tx_clk_active().bit()),
-            )
-            .field("tx_clk_sel", &format_args!("{}", self.tx_clk_sel().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("tx_clkm_div_num", &self.tx_clkm_div_num())
+            .field("tx_clk_active", &self.tx_clk_active())
+            .field("tx_clk_sel", &self.tx_clk_sel())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b &lt;= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/tx_clkm_div_conf.rs b/esp32c6/src/i2s0/tx_clkm_div_conf.rs
index eb02e39a99..8421d21999 100644
--- a/esp32c6/src/i2s0/tx_clkm_div_conf.rs
+++ b/esp32c6/src/i2s0/tx_clkm_div_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CLKM_DIV_CONF")
-            .field(
-                "tx_clkm_div_z",
-                &format_args!("{}", self.tx_clkm_div_z().bits()),
-            )
-            .field(
-                "tx_clkm_div_y",
-                &format_args!("{}", self.tx_clkm_div_y().bits()),
-            )
-            .field(
-                "tx_clkm_div_x",
-                &format_args!("{}", self.tx_clkm_div_x().bits()),
-            )
-            .field(
-                "tx_clkm_div_yn1",
-                &format_args!("{}", self.tx_clkm_div_yn1().bit()),
-            )
+            .field("tx_clkm_div_z", &self.tx_clkm_div_z())
+            .field("tx_clkm_div_y", &self.tx_clkm_div_y())
+            .field("tx_clkm_div_x", &self.tx_clkm_div_x())
+            .field("tx_clkm_div_yn1", &self.tx_clkm_div_yn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CLKM_DIV_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/tx_conf.rs b/esp32c6/src/i2s0/tx_conf.rs
index b10d6ccc62..83a890333d 100644
--- a/esp32c6/src/i2s0/tx_conf.rs
+++ b/esp32c6/src/i2s0/tx_conf.rs
@@ -174,69 +174,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CONF")
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field(
-                "tx_slave_mod",
-                &format_args!("{}", self.tx_slave_mod().bit()),
-            )
-            .field("tx_mono", &format_args!("{}", self.tx_mono().bit()))
-            .field(
-                "tx_chan_equal",
-                &format_args!("{}", self.tx_chan_equal().bit()),
-            )
-            .field(
-                "tx_big_endian",
-                &format_args!("{}", self.tx_big_endian().bit()),
-            )
-            .field("tx_update", &format_args!("{}", self.tx_update().bit()))
-            .field(
-                "tx_mono_fst_vld",
-                &format_args!("{}", self.tx_mono_fst_vld().bit()),
-            )
-            .field(
-                "tx_pcm_conf",
-                &format_args!("{}", self.tx_pcm_conf().bits()),
-            )
-            .field(
-                "tx_pcm_bypass",
-                &format_args!("{}", self.tx_pcm_bypass().bit()),
-            )
-            .field("tx_stop_en", &format_args!("{}", self.tx_stop_en().bit()))
-            .field(
-                "tx_left_align",
-                &format_args!("{}", self.tx_left_align().bit()),
-            )
-            .field(
-                "tx_24_fill_en",
-                &format_args!("{}", self.tx_24_fill_en().bit()),
-            )
-            .field(
-                "tx_ws_idle_pol",
-                &format_args!("{}", self.tx_ws_idle_pol().bit()),
-            )
-            .field(
-                "tx_bit_order",
-                &format_args!("{}", self.tx_bit_order().bit()),
-            )
-            .field("tx_tdm_en", &format_args!("{}", self.tx_tdm_en().bit()))
-            .field("tx_pdm_en", &format_args!("{}", self.tx_pdm_en().bit()))
-            .field(
-                "tx_chan_mod",
-                &format_args!("{}", self.tx_chan_mod().bits()),
-            )
-            .field(
-                "sig_loopback",
-                &format_args!("{}", self.sig_loopback().bit()),
-            )
+            .field("tx_start", &self.tx_start())
+            .field("tx_slave_mod", &self.tx_slave_mod())
+            .field("tx_mono", &self.tx_mono())
+            .field("tx_chan_equal", &self.tx_chan_equal())
+            .field("tx_big_endian", &self.tx_big_endian())
+            .field("tx_update", &self.tx_update())
+            .field("tx_mono_fst_vld", &self.tx_mono_fst_vld())
+            .field("tx_pcm_conf", &self.tx_pcm_conf())
+            .field("tx_pcm_bypass", &self.tx_pcm_bypass())
+            .field("tx_stop_en", &self.tx_stop_en())
+            .field("tx_left_align", &self.tx_left_align())
+            .field("tx_24_fill_en", &self.tx_24_fill_en())
+            .field("tx_ws_idle_pol", &self.tx_ws_idle_pol())
+            .field("tx_bit_order", &self.tx_bit_order())
+            .field("tx_tdm_en", &self.tx_tdm_en())
+            .field("tx_pdm_en", &self.tx_pdm_en())
+            .field("tx_chan_mod", &self.tx_chan_mod())
+            .field("sig_loopback", &self.sig_loopback())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset transmitter"]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/tx_conf1.rs b/esp32c6/src/i2s0/tx_conf1.rs
index 736705832c..8d70da3870 100644
--- a/esp32c6/src/i2s0/tx_conf1.rs
+++ b/esp32c6/src/i2s0/tx_conf1.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CONF1")
-            .field(
-                "tx_tdm_ws_width",
-                &format_args!("{}", self.tx_tdm_ws_width().bits()),
-            )
-            .field(
-                "tx_bck_div_num",
-                &format_args!("{}", self.tx_bck_div_num().bits()),
-            )
-            .field(
-                "tx_bits_mod",
-                &format_args!("{}", self.tx_bits_mod().bits()),
-            )
-            .field(
-                "tx_half_sample_bits",
-                &format_args!("{}", self.tx_half_sample_bits().bits()),
-            )
-            .field(
-                "tx_tdm_chan_bits",
-                &format_args!("{}", self.tx_tdm_chan_bits().bits()),
-            )
-            .field(
-                "tx_msb_shift",
-                &format_args!("{}", self.tx_msb_shift().bit()),
-            )
-            .field(
-                "tx_bck_no_dly",
-                &format_args!("{}", self.tx_bck_no_dly().bit()),
-            )
+            .field("tx_tdm_ws_width", &self.tx_tdm_ws_width())
+            .field("tx_bck_div_num", &self.tx_bck_div_num())
+            .field("tx_bits_mod", &self.tx_bits_mod())
+            .field("tx_half_sample_bits", &self.tx_half_sample_bits())
+            .field("tx_tdm_chan_bits", &self.tx_tdm_chan_bits())
+            .field("tx_msb_shift", &self.tx_msb_shift())
+            .field("tx_bck_no_dly", &self.tx_bck_no_dly())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/tx_pcm2pdm_conf.rs b/esp32c6/src/i2s0/tx_pcm2pdm_conf.rs
index f361f43fa5..833a737465 100644
--- a/esp32c6/src/i2s0/tx_pcm2pdm_conf.rs
+++ b/esp32c6/src/i2s0/tx_pcm2pdm_conf.rs
@@ -116,63 +116,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_PCM2PDM_CONF")
-            .field(
-                "tx_pdm_hp_bypass",
-                &format_args!("{}", self.tx_pdm_hp_bypass().bit()),
-            )
-            .field(
-                "tx_pdm_sinc_osr2",
-                &format_args!("{}", self.tx_pdm_sinc_osr2().bits()),
-            )
-            .field(
-                "tx_pdm_prescale",
-                &format_args!("{}", self.tx_pdm_prescale().bits()),
-            )
-            .field(
-                "tx_pdm_hp_in_shift",
-                &format_args!("{}", self.tx_pdm_hp_in_shift().bits()),
-            )
-            .field(
-                "tx_pdm_lp_in_shift",
-                &format_args!("{}", self.tx_pdm_lp_in_shift().bits()),
-            )
-            .field(
-                "tx_pdm_sinc_in_shift",
-                &format_args!("{}", self.tx_pdm_sinc_in_shift().bits()),
-            )
+            .field("tx_pdm_hp_bypass", &self.tx_pdm_hp_bypass())
+            .field("tx_pdm_sinc_osr2", &self.tx_pdm_sinc_osr2())
+            .field("tx_pdm_prescale", &self.tx_pdm_prescale())
+            .field("tx_pdm_hp_in_shift", &self.tx_pdm_hp_in_shift())
+            .field("tx_pdm_lp_in_shift", &self.tx_pdm_lp_in_shift())
+            .field("tx_pdm_sinc_in_shift", &self.tx_pdm_sinc_in_shift())
             .field(
                 "tx_pdm_sigmadelta_in_shift",
-                &format_args!("{}", self.tx_pdm_sigmadelta_in_shift().bits()),
+                &self.tx_pdm_sigmadelta_in_shift(),
             )
             .field(
                 "tx_pdm_sigmadelta_dither2",
-                &format_args!("{}", self.tx_pdm_sigmadelta_dither2().bit()),
-            )
-            .field(
-                "tx_pdm_sigmadelta_dither",
-                &format_args!("{}", self.tx_pdm_sigmadelta_dither().bit()),
-            )
-            .field(
-                "tx_pdm_dac_2out_en",
-                &format_args!("{}", self.tx_pdm_dac_2out_en().bit()),
-            )
-            .field(
-                "tx_pdm_dac_mode_en",
-                &format_args!("{}", self.tx_pdm_dac_mode_en().bit()),
-            )
-            .field(
-                "pcm2pdm_conv_en",
-                &format_args!("{}", self.pcm2pdm_conv_en().bit()),
+                &self.tx_pdm_sigmadelta_dither2(),
             )
+            .field("tx_pdm_sigmadelta_dither", &self.tx_pdm_sigmadelta_dither())
+            .field("tx_pdm_dac_2out_en", &self.tx_pdm_dac_2out_en())
+            .field("tx_pdm_dac_mode_en", &self.tx_pdm_dac_mode_en())
+            .field("pcm2pdm_conv_en", &self.pcm2pdm_conv_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_PCM2PDM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - I2S TX PDM bypass hp filter or not. The option has been removed."]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/tx_pcm2pdm_conf1.rs b/esp32c6/src/i2s0/tx_pcm2pdm_conf1.rs
index dfcd334df0..48c460dc25 100644
--- a/esp32c6/src/i2s0/tx_pcm2pdm_conf1.rs
+++ b/esp32c6/src/i2s0/tx_pcm2pdm_conf1.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_PCM2PDM_CONF1")
-            .field("tx_pdm_fp", &format_args!("{}", self.tx_pdm_fp().bits()))
-            .field("tx_pdm_fs", &format_args!("{}", self.tx_pdm_fs().bits()))
-            .field(
-                "tx_iir_hp_mult12_5",
-                &format_args!("{}", self.tx_iir_hp_mult12_5().bits()),
-            )
-            .field(
-                "tx_iir_hp_mult12_0",
-                &format_args!("{}", self.tx_iir_hp_mult12_0().bits()),
-            )
+            .field("tx_pdm_fp", &self.tx_pdm_fp())
+            .field("tx_pdm_fs", &self.tx_pdm_fs())
+            .field("tx_iir_hp_mult12_5", &self.tx_iir_hp_mult12_5())
+            .field("tx_iir_hp_mult12_0", &self.tx_iir_hp_mult12_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_PCM2PDM_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - I2S TX PDM Fp"]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/tx_tdm_ctrl.rs b/esp32c6/src/i2s0/tx_tdm_ctrl.rs
index a6511fa2f9..8b06e96c6c 100644
--- a/esp32c6/src/i2s0/tx_tdm_ctrl.rs
+++ b/esp32c6/src/i2s0/tx_tdm_ctrl.rs
@@ -170,87 +170,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_TDM_CTRL")
-            .field(
-                "tx_tdm_chan0_en",
-                &format_args!("{}", self.tx_tdm_chan0_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan1_en",
-                &format_args!("{}", self.tx_tdm_chan1_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan2_en",
-                &format_args!("{}", self.tx_tdm_chan2_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan3_en",
-                &format_args!("{}", self.tx_tdm_chan3_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan4_en",
-                &format_args!("{}", self.tx_tdm_chan4_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan5_en",
-                &format_args!("{}", self.tx_tdm_chan5_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan6_en",
-                &format_args!("{}", self.tx_tdm_chan6_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan7_en",
-                &format_args!("{}", self.tx_tdm_chan7_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan8_en",
-                &format_args!("{}", self.tx_tdm_chan8_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan9_en",
-                &format_args!("{}", self.tx_tdm_chan9_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan10_en",
-                &format_args!("{}", self.tx_tdm_chan10_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan11_en",
-                &format_args!("{}", self.tx_tdm_chan11_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan12_en",
-                &format_args!("{}", self.tx_tdm_chan12_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan13_en",
-                &format_args!("{}", self.tx_tdm_chan13_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan14_en",
-                &format_args!("{}", self.tx_tdm_chan14_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan15_en",
-                &format_args!("{}", self.tx_tdm_chan15_en().bit()),
-            )
-            .field(
-                "tx_tdm_tot_chan_num",
-                &format_args!("{}", self.tx_tdm_tot_chan_num().bits()),
-            )
-            .field(
-                "tx_tdm_skip_msk_en",
-                &format_args!("{}", self.tx_tdm_skip_msk_en().bit()),
-            )
+            .field("tx_tdm_chan0_en", &self.tx_tdm_chan0_en())
+            .field("tx_tdm_chan1_en", &self.tx_tdm_chan1_en())
+            .field("tx_tdm_chan2_en", &self.tx_tdm_chan2_en())
+            .field("tx_tdm_chan3_en", &self.tx_tdm_chan3_en())
+            .field("tx_tdm_chan4_en", &self.tx_tdm_chan4_en())
+            .field("tx_tdm_chan5_en", &self.tx_tdm_chan5_en())
+            .field("tx_tdm_chan6_en", &self.tx_tdm_chan6_en())
+            .field("tx_tdm_chan7_en", &self.tx_tdm_chan7_en())
+            .field("tx_tdm_chan8_en", &self.tx_tdm_chan8_en())
+            .field("tx_tdm_chan9_en", &self.tx_tdm_chan9_en())
+            .field("tx_tdm_chan10_en", &self.tx_tdm_chan10_en())
+            .field("tx_tdm_chan11_en", &self.tx_tdm_chan11_en())
+            .field("tx_tdm_chan12_en", &self.tx_tdm_chan12_en())
+            .field("tx_tdm_chan13_en", &self.tx_tdm_chan13_en())
+            .field("tx_tdm_chan14_en", &self.tx_tdm_chan14_en())
+            .field("tx_tdm_chan15_en", &self.tx_tdm_chan15_en())
+            .field("tx_tdm_tot_chan_num", &self.tx_tdm_tot_chan_num())
+            .field("tx_tdm_skip_msk_en", &self.tx_tdm_skip_msk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_TDM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
diff --git a/esp32c6/src/i2s0/tx_timing.rs b/esp32c6/src/i2s0/tx_timing.rs
index 90d44db432..550930d1b6 100644
--- a/esp32c6/src/i2s0/tx_timing.rs
+++ b/esp32c6/src/i2s0/tx_timing.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_TIMING")
-            .field(
-                "tx_sd_out_dm",
-                &format_args!("{}", self.tx_sd_out_dm().bits()),
-            )
-            .field(
-                "tx_sd1_out_dm",
-                &format_args!("{}", self.tx_sd1_out_dm().bits()),
-            )
-            .field(
-                "tx_ws_out_dm",
-                &format_args!("{}", self.tx_ws_out_dm().bits()),
-            )
-            .field(
-                "tx_bck_out_dm",
-                &format_args!("{}", self.tx_bck_out_dm().bits()),
-            )
-            .field(
-                "tx_ws_in_dm",
-                &format_args!("{}", self.tx_ws_in_dm().bits()),
-            )
-            .field(
-                "tx_bck_in_dm",
-                &format_args!("{}", self.tx_bck_in_dm().bits()),
-            )
+            .field("tx_sd_out_dm", &self.tx_sd_out_dm())
+            .field("tx_sd1_out_dm", &self.tx_sd1_out_dm())
+            .field("tx_ws_out_dm", &self.tx_ws_out_dm())
+            .field("tx_bck_out_dm", &self.tx_bck_out_dm())
+            .field("tx_ws_in_dm", &self.tx_ws_in_dm())
+            .field("tx_bck_in_dm", &self.tx_bck_in_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/ack_frame_pending_en.rs b/esp32c6/src/ieee802154/ack_frame_pending_en.rs
index e97e5031f0..99fc481d79 100644
--- a/esp32c6/src/ieee802154/ack_frame_pending_en.rs
+++ b/esp32c6/src/ieee802154/ack_frame_pending_en.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ACK_FRAME_PENDING_EN")
-            .field(
-                "ack_frame_pending_en",
-                &format_args!("{}", self.ack_frame_pending_en().bit()),
-            )
-            .field(
-                "ack_tx_ack_timeout",
-                &format_args!("{}", self.ack_tx_ack_timeout().bits()),
-            )
+            .field("ack_frame_pending_en", &self.ack_frame_pending_en())
+            .field("ack_tx_ack_timeout", &self.ack_tx_ack_timeout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ACK_FRAME_PENDING_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/ack_timeout.rs b/esp32c6/src/ieee802154/ack_timeout.rs
index 64b5055ec3..e7aeb4fc1f 100644
--- a/esp32c6/src/ieee802154/ack_timeout.rs
+++ b/esp32c6/src/ieee802154/ack_timeout.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ACK_TIMEOUT")
-            .field(
-                "ack_timeout",
-                &format_args!("{}", self.ack_timeout().bits()),
-            )
+            .field("ack_timeout", &self.ack_timeout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ACK_TIMEOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/bb_clk.rs b/esp32c6/src/ieee802154/bb_clk.rs
index 09628bc4f1..88283253cf 100644
--- a/esp32c6/src/ieee802154/bb_clk.rs
+++ b/esp32c6/src/ieee802154/bb_clk.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BB_CLK")
-            .field(
-                "freq_minus_1",
-                &format_args!("{}", self.freq_minus_1().bits()),
-            )
+            .field("freq_minus_1", &self.freq_minus_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BB_CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/cca_busy_cnt.rs b/esp32c6/src/ieee802154/cca_busy_cnt.rs
index 802cdba43d..868197ae52 100644
--- a/esp32c6/src/ieee802154/cca_busy_cnt.rs
+++ b/esp32c6/src/ieee802154/cca_busy_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CCA_BUSY_CNT")
-            .field(
-                "cca_busy_cnt",
-                &format_args!("{}", self.cca_busy_cnt().bits()),
-            )
+            .field("cca_busy_cnt", &self.cca_busy_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CCA_BUSY_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/cca_fail_cnt.rs b/esp32c6/src/ieee802154/cca_fail_cnt.rs
index 4e5a5ab9a3..7d541aa290 100644
--- a/esp32c6/src/ieee802154/cca_fail_cnt.rs
+++ b/esp32c6/src/ieee802154/cca_fail_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CCA_FAIL_CNT")
-            .field(
-                "cca_fail_cnt",
-                &format_args!("{}", self.cca_fail_cnt().bits()),
-            )
+            .field("cca_fail_cnt", &self.cca_fail_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CCA_FAIL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/channel.rs b/esp32c6/src/ieee802154/channel.rs
index f66d5aeaff..c9bfd524b0 100644
--- a/esp32c6/src/ieee802154/channel.rs
+++ b/esp32c6/src/ieee802154/channel.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CHANNEL")
-            .field("hop", &format_args!("{}", self.hop().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHANNEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CHANNEL").field("hop", &self.hop()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/ieee802154/clk_counter.rs b/esp32c6/src/ieee802154/clk_counter.rs
index 08f3b726f8..0616970a84 100644
--- a/esp32c6/src/ieee802154/clk_counter.rs
+++ b/esp32c6/src/ieee802154/clk_counter.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_COUNTER")
-            .field(
-                "clk_625us_cnt",
-                &format_args!("{}", self.clk_625us_cnt().bits()),
-            )
+            .field("clk_625us_cnt", &self.clk_625us_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_COUNTER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/clk_counter_match_val.rs b/esp32c6/src/ieee802154/clk_counter_match_val.rs
index 2ff54615d1..3b02085d56 100644
--- a/esp32c6/src/ieee802154/clk_counter_match_val.rs
+++ b/esp32c6/src/ieee802154/clk_counter_match_val.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_COUNTER_MATCH_VAL")
-            .field(
-                "clk_count_match_val",
-                &format_args!("{}", self.clk_count_match_val().bits()),
-            )
+            .field("clk_count_match_val", &self.clk_count_match_val())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_COUNTER_MATCH_VAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/coex_pti.rs b/esp32c6/src/ieee802154/coex_pti.rs
index f6645b5596..37dc111e19 100644
--- a/esp32c6/src/ieee802154/coex_pti.rs
+++ b/esp32c6/src/ieee802154/coex_pti.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COEX_PTI")
-            .field("coex_pti", &format_args!("{}", self.coex_pti().bits()))
-            .field(
-                "coex_ack_pti",
-                &format_args!("{}", self.coex_ack_pti().bits()),
-            )
-            .field(
-                "close_rf_sel",
-                &format_args!("{}", self.close_rf_sel().bit()),
-            )
+            .field("coex_pti", &self.coex_pti())
+            .field("coex_ack_pti", &self.coex_ack_pti())
+            .field("close_rf_sel", &self.close_rf_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COEX_PTI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/command.rs b/esp32c6/src/ieee802154/command.rs
index 098fba6571..2e4003d258 100644
--- a/esp32c6/src/ieee802154/command.rs
+++ b/esp32c6/src/ieee802154/command.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMMAND")
-            .field("opcode", &format_args!("{}", self.opcode().bits()))
+            .field("opcode", &self.opcode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMMAND_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/cont_rx_delay.rs b/esp32c6/src/ieee802154/cont_rx_delay.rs
index 49885b4453..deeb70955a 100644
--- a/esp32c6/src/ieee802154/cont_rx_delay.rs
+++ b/esp32c6/src/ieee802154/cont_rx_delay.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONT_RX_DELAY")
-            .field(
-                "cont_rx_delay",
-                &format_args!("{}", self.cont_rx_delay().bits()),
-            )
+            .field("cont_rx_delay", &self.cont_rx_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONT_RX_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/core_dummy_data.rs b/esp32c6/src/ieee802154/core_dummy_data.rs
index e426d7fe67..847c8843d4 100644
--- a/esp32c6/src/ieee802154/core_dummy_data.rs
+++ b/esp32c6/src/ieee802154/core_dummy_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_DUMMY_DATA")
-            .field(
-                "core_dummy_data",
-                &format_args!("{}", self.core_dummy_data().bits()),
-            )
+            .field("core_dummy_data", &self.core_dummy_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_DUMMY_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/core_gck_cfg.rs b/esp32c6/src/ieee802154/core_gck_cfg.rs
index 5f9b39d6c3..dea2e43a93 100644
--- a/esp32c6/src/ieee802154/core_gck_cfg.rs
+++ b/esp32c6/src/ieee802154/core_gck_cfg.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_GCK_CFG")
-            .field("dis_pkt_gck", &format_args!("{}", self.dis_pkt_gck().bit()))
-            .field(
-                "dis_ctrl_gck",
-                &format_args!("{}", self.dis_ctrl_gck().bit()),
-            )
+            .field("dis_pkt_gck", &self.dis_pkt_gck())
+            .field("dis_ctrl_gck", &self.dis_ctrl_gck())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_GCK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/crc_error_cnt.rs b/esp32c6/src/ieee802154/crc_error_cnt.rs
index a85c26ddc8..b68644847b 100644
--- a/esp32c6/src/ieee802154/crc_error_cnt.rs
+++ b/esp32c6/src/ieee802154/crc_error_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CRC_ERROR_CNT")
-            .field(
-                "crc_error_cnt",
-                &format_args!("{}", self.crc_error_cnt().bits()),
-            )
+            .field("crc_error_cnt", &self.crc_error_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CRC_ERROR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/ctrl_cfg.rs b/esp32c6/src/ieee802154/ctrl_cfg.rs
index 4035706643..565ed9f92f 100644
--- a/esp32c6/src/ieee802154/ctrl_cfg.rs
+++ b/esp32c6/src/ieee802154/ctrl_cfg.rs
@@ -170,84 +170,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL_CFG")
-            .field(
-                "hw_auto_ack_tx_en",
-                &format_args!("{}", self.hw_auto_ack_tx_en().bit()),
-            )
-            .field(
-                "hw_enhance_ack_tx_en",
-                &format_args!("{}", self.hw_enhance_ack_tx_en().bit()),
-            )
-            .field(
-                "hw_auto_ack_rx_en",
-                &format_args!("{}", self.hw_auto_ack_rx_en().bit()),
-            )
-            .field(
-                "dis_ifs_control",
-                &format_args!("{}", self.dis_ifs_control().bit()),
-            )
-            .field(
-                "pan_coordinator",
-                &format_args!("{}", self.pan_coordinator().bit()),
-            )
-            .field(
-                "promiscuous_mode",
-                &format_args!("{}", self.promiscuous_mode().bit()),
-            )
+            .field("hw_auto_ack_tx_en", &self.hw_auto_ack_tx_en())
+            .field("hw_enhance_ack_tx_en", &self.hw_enhance_ack_tx_en())
+            .field("hw_auto_ack_rx_en", &self.hw_auto_ack_rx_en())
+            .field("dis_ifs_control", &self.dis_ifs_control())
+            .field("pan_coordinator", &self.pan_coordinator())
+            .field("promiscuous_mode", &self.promiscuous_mode())
             .field(
                 "dis_frame_version_rsv_filter",
-                &format_args!("{}", self.dis_frame_version_rsv_filter().bit()),
-            )
-            .field(
-                "autopend_enhance",
-                &format_args!("{}", self.autopend_enhance().bit()),
-            )
-            .field(
-                "filter_enhance",
-                &format_args!("{}", self.filter_enhance().bit()),
-            )
-            .field(
-                "coex_arb_delay",
-                &format_args!("{}", self.coex_arb_delay().bits()),
-            )
-            .field("bit_order", &format_args!("{}", self.bit_order().bit()))
-            .field(
-                "no_rss_trk_enb",
-                &format_args!("{}", self.no_rss_trk_enb().bit()),
-            )
-            .field(
-                "force_rx_enb",
-                &format_args!("{}", self.force_rx_enb().bit()),
-            )
-            .field(
-                "rx_done_trigger_idle",
-                &format_args!("{}", self.rx_done_trigger_idle().bit()),
-            )
-            .field(
-                "mac_inf0_enable",
-                &format_args!("{}", self.mac_inf0_enable().bit()),
-            )
-            .field(
-                "mac_inf1_enable",
-                &format_args!("{}", self.mac_inf1_enable().bit()),
-            )
-            .field(
-                "mac_inf2_enable",
-                &format_args!("{}", self.mac_inf2_enable().bit()),
-            )
-            .field(
-                "mac_inf3_enable",
-                &format_args!("{}", self.mac_inf3_enable().bit()),
+                &self.dis_frame_version_rsv_filter(),
             )
+            .field("autopend_enhance", &self.autopend_enhance())
+            .field("filter_enhance", &self.filter_enhance())
+            .field("coex_arb_delay", &self.coex_arb_delay())
+            .field("bit_order", &self.bit_order())
+            .field("no_rss_trk_enb", &self.no_rss_trk_enb())
+            .field("force_rx_enb", &self.force_rx_enb())
+            .field("rx_done_trigger_idle", &self.rx_done_trigger_idle())
+            .field("mac_inf0_enable", &self.mac_inf0_enable())
+            .field("mac_inf1_enable", &self.mac_inf1_enable())
+            .field("mac_inf2_enable", &self.mac_inf2_enable())
+            .field("mac_inf3_enable", &self.mac_inf3_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/dcdc_ctrl.rs b/esp32c6/src/ieee802154/dcdc_ctrl.rs
index 70ffe156cd..5168c20d91 100644
--- a/esp32c6/src/ieee802154/dcdc_ctrl.rs
+++ b/esp32c6/src/ieee802154/dcdc_ctrl.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCDC_CTRL")
-            .field(
-                "dcdc_pre_up_delay",
-                &format_args!("{}", self.dcdc_pre_up_delay().bits()),
-            )
-            .field(
-                "dcdc_down_delay",
-                &format_args!("{}", self.dcdc_down_delay().bits()),
-            )
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("tx_dcdc_up", &format_args!("{}", self.tx_dcdc_up().bit()))
+            .field("dcdc_pre_up_delay", &self.dcdc_pre_up_delay())
+            .field("dcdc_down_delay", &self.dcdc_down_delay())
+            .field("en", &self.en())
+            .field("tx_dcdc_up", &self.tx_dcdc_up())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCDC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/debug_ctrl.rs b/esp32c6/src/ieee802154/debug_ctrl.rs
index 182a6cae69..91568ca9e9 100644
--- a/esp32c6/src/ieee802154/debug_ctrl.rs
+++ b/esp32c6/src/ieee802154/debug_ctrl.rs
@@ -71,43 +71,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEBUG_CTRL")
-            .field(
-                "debug_signal_sel",
-                &format_args!("{}", self.debug_signal_sel().bits()),
-            )
+            .field("debug_signal_sel", &self.debug_signal_sel())
             .field(
                 "debug_trigger_state_select",
-                &format_args!("{}", self.debug_trigger_state_select().bits()),
-            )
-            .field(
-                "debug_ser_debug_sel",
-                &format_args!("{}", self.debug_ser_debug_sel().bits()),
+                &self.debug_trigger_state_select(),
             )
+            .field("debug_ser_debug_sel", &self.debug_ser_debug_sel())
             .field(
                 "debug_trigger_state_match_value",
-                &format_args!("{}", self.debug_trigger_state_match_value().bits()),
+                &self.debug_trigger_state_match_value(),
             )
             .field(
                 "debug_trigger_pulse_select",
-                &format_args!("{}", self.debug_trigger_pulse_select().bits()),
+                &self.debug_trigger_pulse_select(),
             )
             .field(
                 "debug_state_match_dump_en",
-                &format_args!("{}", self.debug_state_match_dump_en().bit()),
-            )
-            .field(
-                "debug_trigger_dump_en",
-                &format_args!("{}", self.debug_trigger_dump_en().bit()),
+                &self.debug_state_match_dump_en(),
             )
+            .field("debug_trigger_dump_en", &self.debug_trigger_dump_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBUG_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/dma_dummy.rs b/esp32c6/src/ieee802154/dma_dummy.rs
index 12ae8e7af9..192dc0c201 100644
--- a/esp32c6/src/ieee802154/dma_dummy.rs
+++ b/esp32c6/src/ieee802154/dma_dummy.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_DUMMY")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_DUMMY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/dma_gck_cfg.rs b/esp32c6/src/ieee802154/dma_gck_cfg.rs
index 02b2c5ae4e..626c1ca6b1 100644
--- a/esp32c6/src/ieee802154/dma_gck_cfg.rs
+++ b/esp32c6/src/ieee802154/dma_gck_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_GCK_CFG")
-            .field("dma_gck_cfg", &format_args!("{}", self.dma_gck_cfg().bit()))
+            .field("dma_gck_cfg", &self.dma_gck_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_GCK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/dtm_config.rs b/esp32c6/src/ieee802154/dtm_config.rs
index 1910cf9ae7..b45b51b238 100644
--- a/esp32c6/src/ieee802154/dtm_config.rs
+++ b/esp32c6/src/ieee802154/dtm_config.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DTM_CONFIG")
-            .field(
-                "dtmch_tx_length",
-                &format_args!("{}", self.dtmch_tx_length().bits()),
-            )
-            .field(
-                "dtm_tx_pld_type",
-                &format_args!("{}", self.dtm_tx_pld_type().bits()),
-            )
-            .field(
-                "dtm_hop_freq",
-                &format_args!("{}", self.dtm_hop_freq().bits()),
-            )
-            .field(
-                "dtm_contrx_en",
-                &format_args!("{}", self.dtm_contrx_en().bit()),
-            )
-            .field("dtm_on", &format_args!("{}", self.dtm_on().bit()))
+            .field("dtmch_tx_length", &self.dtmch_tx_length())
+            .field("dtm_tx_pld_type", &self.dtm_tx_pld_type())
+            .field("dtm_hop_freq", &self.dtm_hop_freq())
+            .field("dtm_contrx_en", &self.dtm_contrx_en())
+            .field("dtm_on", &self.dtm_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DTM_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/dtm_pkt_counter.rs b/esp32c6/src/ieee802154/dtm_pkt_counter.rs
index 78af4f5eab..c883c06c29 100644
--- a/esp32c6/src/ieee802154/dtm_pkt_counter.rs
+++ b/esp32c6/src/ieee802154/dtm_pkt_counter.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DTM_PKT_COUNTER")
-            .field(
-                "dtm_txrx_pkt_count",
-                &format_args!("{}", self.dtm_txrx_pkt_count().bits()),
-            )
-            .field(
-                "dtm_crc_err_pkt_count",
-                &format_args!("{}", self.dtm_crc_err_pkt_count().bits()),
-            )
+            .field("dtm_txrx_pkt_count", &self.dtm_txrx_pkt_count())
+            .field("dtm_crc_err_pkt_count", &self.dtm_crc_err_pkt_count())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DTM_PKT_COUNTER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/dtm_tx_pkt_config.rs b/esp32c6/src/ieee802154/dtm_tx_pkt_config.rs
index 34496d5b6a..5d3a9541ca 100644
--- a/esp32c6/src/ieee802154/dtm_tx_pkt_config.rs
+++ b/esp32c6/src/ieee802154/dtm_tx_pkt_config.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DTM_TX_PKT_CONFIG")
-            .field(
-                "dtm_tx_pkt_threshold",
-                &format_args!("{}", self.dtm_tx_pkt_threshold().bits()),
-            )
+            .field("dtm_tx_pkt_threshold", &self.dtm_tx_pkt_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DTM_TX_PKT_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/ed_abort_cnt.rs b/esp32c6/src/ieee802154/ed_abort_cnt.rs
index ca5c73d89a..1f06edc663 100644
--- a/esp32c6/src/ieee802154/ed_abort_cnt.rs
+++ b/esp32c6/src/ieee802154/ed_abort_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ED_ABORT_CNT")
-            .field(
-                "ed_abort_cnt",
-                &format_args!("{}", self.ed_abort_cnt().bits()),
-            )
+            .field("ed_abort_cnt", &self.ed_abort_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ED_ABORT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/ed_scan_cfg.rs b/esp32c6/src/ieee802154/ed_scan_cfg.rs
index fa9bf031c6..888c4525ad 100644
--- a/esp32c6/src/ieee802154/ed_scan_cfg.rs
+++ b/esp32c6/src/ieee802154/ed_scan_cfg.rs
@@ -62,30 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ED_SCAN_CFG")
-            .field(
-                "cca_ed_threshold",
-                &format_args!("{}", self.cca_ed_threshold().bits()),
-            )
-            .field(
-                "ed_sample_mode",
-                &format_args!("{}", self.ed_sample_mode().bits()),
-            )
-            .field(
-                "dis_ed_power_sel",
-                &format_args!("{}", self.dis_ed_power_sel().bit()),
-            )
-            .field("cca_mode", &format_args!("{}", self.cca_mode().bits()))
-            .field("ed_rss", &format_args!("{}", self.ed_rss().bits()))
-            .field("cca_busy", &format_args!("{}", self.cca_busy().bit()))
+            .field("cca_ed_threshold", &self.cca_ed_threshold())
+            .field("ed_sample_mode", &self.ed_sample_mode())
+            .field("dis_ed_power_sel", &self.dis_ed_power_sel())
+            .field("cca_mode", &self.cca_mode())
+            .field("ed_rss", &self.ed_rss())
+            .field("cca_busy", &self.cca_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ED_SCAN_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/ed_scan_coex_cnt.rs b/esp32c6/src/ieee802154/ed_scan_coex_cnt.rs
index a513b9b15a..d3b55c8c4e 100644
--- a/esp32c6/src/ieee802154/ed_scan_coex_cnt.rs
+++ b/esp32c6/src/ieee802154/ed_scan_coex_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ED_SCAN_COEX_CNT")
-            .field(
-                "ed_scan_coex_cnt",
-                &format_args!("{}", self.ed_scan_coex_cnt().bits()),
-            )
+            .field("ed_scan_coex_cnt", &self.ed_scan_coex_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ED_SCAN_COEX_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/ed_scan_duration.rs b/esp32c6/src/ieee802154/ed_scan_duration.rs
index 3cec1e1c01..c0122aa4e7 100644
--- a/esp32c6/src/ieee802154/ed_scan_duration.rs
+++ b/esp32c6/src/ieee802154/ed_scan_duration.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ED_SCAN_DURATION")
-            .field(
-                "ed_scan_duration",
-                &format_args!("{}", self.ed_scan_duration().bits()),
-            )
-            .field(
-                "ed_scan_wait_dly",
-                &format_args!("{}", self.ed_scan_wait_dly().bits()),
-            )
+            .field("ed_scan_duration", &self.ed_scan_duration())
+            .field("ed_scan_wait_dly", &self.ed_scan_wait_dly())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ED_SCAN_DURATION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/enhance_ack_cfg.rs b/esp32c6/src/ieee802154/enhance_ack_cfg.rs
index 1726262510..5c40773c29 100644
--- a/esp32c6/src/ieee802154/enhance_ack_cfg.rs
+++ b/esp32c6/src/ieee802154/enhance_ack_cfg.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ENHANCE_ACK_CFG")
             .field(
                 "tx_enh_ack_generate_done_notify",
-                &format_args!("{}", self.tx_enh_ack_generate_done_notify().bits()),
+                &self.tx_enh_ack_generate_done_notify(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENHANCE_ACK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/error_cnt_clear.rs b/esp32c6/src/ieee802154/error_cnt_clear.rs
index e15bb4e889..9e4c04b6b2 100644
--- a/esp32c6/src/ieee802154/error_cnt_clear.rs
+++ b/esp32c6/src/ieee802154/error_cnt_clear.rs
@@ -143,75 +143,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERROR_CNT_CLEAR")
-            .field(
-                "cca_busy_cnt_clear",
-                &format_args!("{}", self.cca_busy_cnt_clear().bit()),
-            )
+            .field("cca_busy_cnt_clear", &self.cca_busy_cnt_clear())
             .field(
                 "tx_security_error_cnt_clear",
-                &format_args!("{}", self.tx_security_error_cnt_clear().bit()),
-            )
-            .field(
-                "tx_break_coex_cnt_clear",
-                &format_args!("{}", self.tx_break_coex_cnt_clear().bit()),
-            )
-            .field(
-                "rx_ack_timeout_cnt_clear",
-                &format_args!("{}", self.rx_ack_timeout_cnt_clear().bit()),
+                &self.tx_security_error_cnt_clear(),
             )
+            .field("tx_break_coex_cnt_clear", &self.tx_break_coex_cnt_clear())
+            .field("rx_ack_timeout_cnt_clear", &self.rx_ack_timeout_cnt_clear())
             .field(
                 "rx_ack_abort_coex_cnt_clear",
-                &format_args!("{}", self.rx_ack_abort_coex_cnt_clear().bit()),
-            )
-            .field(
-                "ed_scan_coex_cnt_clear",
-                &format_args!("{}", self.ed_scan_coex_cnt_clear().bit()),
+                &self.rx_ack_abort_coex_cnt_clear(),
             )
+            .field("ed_scan_coex_cnt_clear", &self.ed_scan_coex_cnt_clear())
             .field(
                 "tx_ack_abort_coex_cnt_clear",
-                &format_args!("{}", self.tx_ack_abort_coex_cnt_clear().bit()),
-            )
-            .field(
-                "rx_restart_cnt_clear",
-                &format_args!("{}", self.rx_restart_cnt_clear().bit()),
-            )
-            .field(
-                "rx_abort_coex_cnt_clear",
-                &format_args!("{}", self.rx_abort_coex_cnt_clear().bit()),
-            )
-            .field(
-                "no_rss_detect_cnt_clear",
-                &format_args!("{}", self.no_rss_detect_cnt_clear().bit()),
-            )
-            .field(
-                "rx_filter_fail_cnt_clear",
-                &format_args!("{}", self.rx_filter_fail_cnt_clear().bit()),
-            )
-            .field(
-                "cca_fail_cnt_clear",
-                &format_args!("{}", self.cca_fail_cnt_clear().bit()),
-            )
-            .field(
-                "ed_abort_cnt_clear",
-                &format_args!("{}", self.ed_abort_cnt_clear().bit()),
-            )
-            .field(
-                "crc_error_cnt_clear",
-                &format_args!("{}", self.crc_error_cnt_clear().bit()),
-            )
-            .field(
-                "sfd_timeout_cnt_clear",
-                &format_args!("{}", self.sfd_timeout_cnt_clear().bit()),
+                &self.tx_ack_abort_coex_cnt_clear(),
             )
+            .field("rx_restart_cnt_clear", &self.rx_restart_cnt_clear())
+            .field("rx_abort_coex_cnt_clear", &self.rx_abort_coex_cnt_clear())
+            .field("no_rss_detect_cnt_clear", &self.no_rss_detect_cnt_clear())
+            .field("rx_filter_fail_cnt_clear", &self.rx_filter_fail_cnt_clear())
+            .field("cca_fail_cnt_clear", &self.cca_fail_cnt_clear())
+            .field("ed_abort_cnt_clear", &self.ed_abort_cnt_clear())
+            .field("crc_error_cnt_clear", &self.crc_error_cnt_clear())
+            .field("sfd_timeout_cnt_clear", &self.sfd_timeout_cnt_clear())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERROR_CNT_CLEAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/event_en.rs b/esp32c6/src/ieee802154/event_en.rs
index 882575b675..f15edeb72f 100644
--- a/esp32c6/src/ieee802154/event_en.rs
+++ b/esp32c6/src/ieee802154/event_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVENT_EN")
-            .field("event_en", &format_args!("{}", self.event_en().bits()))
+            .field("event_en", &self.event_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVENT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/event_status.rs b/esp32c6/src/ieee802154/event_status.rs
index c0cc0658e8..cdf1600a4e 100644
--- a/esp32c6/src/ieee802154/event_status.rs
+++ b/esp32c6/src/ieee802154/event_status.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVENT_STATUS")
-            .field(
-                "event_status",
-                &format_args!("{}", self.event_status().bits()),
-            )
+            .field("event_status", &self.event_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVENT_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/ifs.rs b/esp32c6/src/ieee802154/ifs.rs
index 3cffb146c9..89aa1000ed 100644
--- a/esp32c6/src/ieee802154/ifs.rs
+++ b/esp32c6/src/ieee802154/ifs.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IFS")
-            .field("sifs", &format_args!("{}", self.sifs().bits()))
-            .field("lifs", &format_args!("{}", self.lifs().bits()))
+            .field("sifs", &self.sifs())
+            .field("lifs", &self.lifs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IFS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/ifs_counter.rs b/esp32c6/src/ieee802154/ifs_counter.rs
index 9bc0520ead..08f7849433 100644
--- a/esp32c6/src/ieee802154/ifs_counter.rs
+++ b/esp32c6/src/ieee802154/ifs_counter.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IFS_COUNTER")
-            .field(
-                "ifs_counter",
-                &format_args!("{}", self.ifs_counter().bits()),
-            )
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("ifs_counter", &self.ifs_counter())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IFS_COUNTER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf0_extend_addr0.rs b/esp32c6/src/ieee802154/inf0_extend_addr0.rs
index d5daf06551..14c7fa2b4a 100644
--- a/esp32c6/src/ieee802154/inf0_extend_addr0.rs
+++ b/esp32c6/src/ieee802154/inf0_extend_addr0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF0_EXTEND_ADDR0")
-            .field(
-                "mac_inf0_extend_addr0",
-                &format_args!("{}", self.mac_inf0_extend_addr0().bits()),
-            )
+            .field("mac_inf0_extend_addr0", &self.mac_inf0_extend_addr0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF0_EXTEND_ADDR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf0_extend_addr1.rs b/esp32c6/src/ieee802154/inf0_extend_addr1.rs
index c3620d8d70..269e6b75b3 100644
--- a/esp32c6/src/ieee802154/inf0_extend_addr1.rs
+++ b/esp32c6/src/ieee802154/inf0_extend_addr1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF0_EXTEND_ADDR1")
-            .field(
-                "mac_inf0_extend_addr1",
-                &format_args!("{}", self.mac_inf0_extend_addr1().bits()),
-            )
+            .field("mac_inf0_extend_addr1", &self.mac_inf0_extend_addr1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF0_EXTEND_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf0_pan_id.rs b/esp32c6/src/ieee802154/inf0_pan_id.rs
index b9cdabc6a7..df03bec0c9 100644
--- a/esp32c6/src/ieee802154/inf0_pan_id.rs
+++ b/esp32c6/src/ieee802154/inf0_pan_id.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF0_PAN_ID")
-            .field(
-                "mac_inf0_pan_id",
-                &format_args!("{}", self.mac_inf0_pan_id().bits()),
-            )
+            .field("mac_inf0_pan_id", &self.mac_inf0_pan_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF0_PAN_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf0_short_addr.rs b/esp32c6/src/ieee802154/inf0_short_addr.rs
index eccee8dfb7..43949e1b8e 100644
--- a/esp32c6/src/ieee802154/inf0_short_addr.rs
+++ b/esp32c6/src/ieee802154/inf0_short_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF0_SHORT_ADDR")
-            .field(
-                "mac_inf0_short_addr",
-                &format_args!("{}", self.mac_inf0_short_addr().bits()),
-            )
+            .field("mac_inf0_short_addr", &self.mac_inf0_short_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF0_SHORT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf1_extend_addr0.rs b/esp32c6/src/ieee802154/inf1_extend_addr0.rs
index d40dae7c13..161a99a504 100644
--- a/esp32c6/src/ieee802154/inf1_extend_addr0.rs
+++ b/esp32c6/src/ieee802154/inf1_extend_addr0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF1_EXTEND_ADDR0")
-            .field(
-                "mac_inf1_extend_addr0",
-                &format_args!("{}", self.mac_inf1_extend_addr0().bits()),
-            )
+            .field("mac_inf1_extend_addr0", &self.mac_inf1_extend_addr0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF1_EXTEND_ADDR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf1_extend_addr1.rs b/esp32c6/src/ieee802154/inf1_extend_addr1.rs
index a65de5ea3b..622d8b0c3c 100644
--- a/esp32c6/src/ieee802154/inf1_extend_addr1.rs
+++ b/esp32c6/src/ieee802154/inf1_extend_addr1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF1_EXTEND_ADDR1")
-            .field(
-                "mac_inf1_extend_addr1",
-                &format_args!("{}", self.mac_inf1_extend_addr1().bits()),
-            )
+            .field("mac_inf1_extend_addr1", &self.mac_inf1_extend_addr1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF1_EXTEND_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf1_pan_id.rs b/esp32c6/src/ieee802154/inf1_pan_id.rs
index 446bbde96d..d92a995164 100644
--- a/esp32c6/src/ieee802154/inf1_pan_id.rs
+++ b/esp32c6/src/ieee802154/inf1_pan_id.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF1_PAN_ID")
-            .field(
-                "mac_inf1_pan_id",
-                &format_args!("{}", self.mac_inf1_pan_id().bits()),
-            )
+            .field("mac_inf1_pan_id", &self.mac_inf1_pan_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF1_PAN_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf1_short_addr.rs b/esp32c6/src/ieee802154/inf1_short_addr.rs
index c4591d8c7c..3a8260b757 100644
--- a/esp32c6/src/ieee802154/inf1_short_addr.rs
+++ b/esp32c6/src/ieee802154/inf1_short_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF1_SHORT_ADDR")
-            .field(
-                "mac_inf1_short_addr",
-                &format_args!("{}", self.mac_inf1_short_addr().bits()),
-            )
+            .field("mac_inf1_short_addr", &self.mac_inf1_short_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF1_SHORT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf2_extend_addr0.rs b/esp32c6/src/ieee802154/inf2_extend_addr0.rs
index b67a30a491..16209ac6cf 100644
--- a/esp32c6/src/ieee802154/inf2_extend_addr0.rs
+++ b/esp32c6/src/ieee802154/inf2_extend_addr0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF2_EXTEND_ADDR0")
-            .field(
-                "mac_inf2_extend_addr0",
-                &format_args!("{}", self.mac_inf2_extend_addr0().bits()),
-            )
+            .field("mac_inf2_extend_addr0", &self.mac_inf2_extend_addr0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF2_EXTEND_ADDR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf2_extend_addr1.rs b/esp32c6/src/ieee802154/inf2_extend_addr1.rs
index a7c70b708b..ebf9837339 100644
--- a/esp32c6/src/ieee802154/inf2_extend_addr1.rs
+++ b/esp32c6/src/ieee802154/inf2_extend_addr1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF2_EXTEND_ADDR1")
-            .field(
-                "mac_inf2_extend_addr1",
-                &format_args!("{}", self.mac_inf2_extend_addr1().bits()),
-            )
+            .field("mac_inf2_extend_addr1", &self.mac_inf2_extend_addr1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF2_EXTEND_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf2_pan_id.rs b/esp32c6/src/ieee802154/inf2_pan_id.rs
index 006e3020b0..6272f0d0e1 100644
--- a/esp32c6/src/ieee802154/inf2_pan_id.rs
+++ b/esp32c6/src/ieee802154/inf2_pan_id.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF2_PAN_ID")
-            .field(
-                "mac_inf2_pan_id",
-                &format_args!("{}", self.mac_inf2_pan_id().bits()),
-            )
+            .field("mac_inf2_pan_id", &self.mac_inf2_pan_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF2_PAN_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf2_short_addr.rs b/esp32c6/src/ieee802154/inf2_short_addr.rs
index e49c3b11b8..b9de1efaaa 100644
--- a/esp32c6/src/ieee802154/inf2_short_addr.rs
+++ b/esp32c6/src/ieee802154/inf2_short_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF2_SHORT_ADDR")
-            .field(
-                "mac_inf2_short_addr",
-                &format_args!("{}", self.mac_inf2_short_addr().bits()),
-            )
+            .field("mac_inf2_short_addr", &self.mac_inf2_short_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF2_SHORT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf3_extend_addr0.rs b/esp32c6/src/ieee802154/inf3_extend_addr0.rs
index 7d34864f0b..02da5ac83b 100644
--- a/esp32c6/src/ieee802154/inf3_extend_addr0.rs
+++ b/esp32c6/src/ieee802154/inf3_extend_addr0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF3_EXTEND_ADDR0")
-            .field(
-                "mac_inf3_extend_addr0",
-                &format_args!("{}", self.mac_inf3_extend_addr0().bits()),
-            )
+            .field("mac_inf3_extend_addr0", &self.mac_inf3_extend_addr0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF3_EXTEND_ADDR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf3_extend_addr1.rs b/esp32c6/src/ieee802154/inf3_extend_addr1.rs
index 68a13eff7d..65c8b21024 100644
--- a/esp32c6/src/ieee802154/inf3_extend_addr1.rs
+++ b/esp32c6/src/ieee802154/inf3_extend_addr1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF3_EXTEND_ADDR1")
-            .field(
-                "mac_inf3_extend_addr1",
-                &format_args!("{}", self.mac_inf3_extend_addr1().bits()),
-            )
+            .field("mac_inf3_extend_addr1", &self.mac_inf3_extend_addr1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF3_EXTEND_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf3_pan_id.rs b/esp32c6/src/ieee802154/inf3_pan_id.rs
index 4e65ecf31f..abe913e716 100644
--- a/esp32c6/src/ieee802154/inf3_pan_id.rs
+++ b/esp32c6/src/ieee802154/inf3_pan_id.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF3_PAN_ID")
-            .field(
-                "mac_inf3_pan_id",
-                &format_args!("{}", self.mac_inf3_pan_id().bits()),
-            )
+            .field("mac_inf3_pan_id", &self.mac_inf3_pan_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF3_PAN_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/inf3_short_addr.rs b/esp32c6/src/ieee802154/inf3_short_addr.rs
index aacca01029..39d7231acb 100644
--- a/esp32c6/src/ieee802154/inf3_short_addr.rs
+++ b/esp32c6/src/ieee802154/inf3_short_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF3_SHORT_ADDR")
-            .field(
-                "mac_inf3_short_addr",
-                &format_args!("{}", self.mac_inf3_short_addr().bits()),
-            )
+            .field("mac_inf3_short_addr", &self.mac_inf3_short_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF3_SHORT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/mac_date.rs b/esp32c6/src/ieee802154/mac_date.rs
index 3280d36252..423244aba5 100644
--- a/esp32c6/src/ieee802154/mac_date.rs
+++ b/esp32c6/src/ieee802154/mac_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAC_DATE")
-            .field("mac_date", &format_args!("{}", self.mac_date().bits()))
+            .field("mac_date", &self.mac_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAC_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/no_rss_detect_cnt.rs b/esp32c6/src/ieee802154/no_rss_detect_cnt.rs
index 68947fab03..a25e47e151 100644
--- a/esp32c6/src/ieee802154/no_rss_detect_cnt.rs
+++ b/esp32c6/src/ieee802154/no_rss_detect_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NO_RSS_DETECT_CNT")
-            .field(
-                "no_rss_detect_cnt",
-                &format_args!("{}", self.no_rss_detect_cnt().bits()),
-            )
+            .field("no_rss_detect_cnt", &self.no_rss_detect_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NO_RSS_DETECT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/paon_delay.rs b/esp32c6/src/ieee802154/paon_delay.rs
index b908f6fe3f..f080065b18 100644
--- a/esp32c6/src/ieee802154/paon_delay.rs
+++ b/esp32c6/src/ieee802154/paon_delay.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAON_DELAY")
-            .field("paon_delay", &format_args!("{}", self.paon_delay().bits()))
+            .field("paon_delay", &self.paon_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAON_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/rx_abort_coex_cnt.rs b/esp32c6/src/ieee802154/rx_abort_coex_cnt.rs
index 4beacb0a13..e275ae73bf 100644
--- a/esp32c6/src/ieee802154/rx_abort_coex_cnt.rs
+++ b/esp32c6/src/ieee802154/rx_abort_coex_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ABORT_COEX_CNT")
-            .field(
-                "rx_abort_coex_cnt",
-                &format_args!("{}", self.rx_abort_coex_cnt().bits()),
-            )
+            .field("rx_abort_coex_cnt", &self.rx_abort_coex_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ABORT_COEX_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/rx_abort_intr_ctrl.rs b/esp32c6/src/ieee802154/rx_abort_intr_ctrl.rs
index d26980ed4d..b0fb9a221e 100644
--- a/esp32c6/src/ieee802154/rx_abort_intr_ctrl.rs
+++ b/esp32c6/src/ieee802154/rx_abort_intr_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ABORT_INTR_CTRL")
-            .field(
-                "rx_abort_intr_ctrl",
-                &format_args!("{}", self.rx_abort_intr_ctrl().bits()),
-            )
+            .field("rx_abort_intr_ctrl", &self.rx_abort_intr_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ABORT_INTR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/rx_ack_abort_coex_cnt.rs b/esp32c6/src/ieee802154/rx_ack_abort_coex_cnt.rs
index 80887b5c5c..949dea2ff9 100644
--- a/esp32c6/src/ieee802154/rx_ack_abort_coex_cnt.rs
+++ b/esp32c6/src/ieee802154/rx_ack_abort_coex_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ACK_ABORT_COEX_CNT")
-            .field(
-                "rx_ack_abort_coex_cnt",
-                &format_args!("{}", self.rx_ack_abort_coex_cnt().bits()),
-            )
+            .field("rx_ack_abort_coex_cnt", &self.rx_ack_abort_coex_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ACK_ABORT_COEX_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/rx_ack_timeout_cnt.rs b/esp32c6/src/ieee802154/rx_ack_timeout_cnt.rs
index b14a4862b2..11d598f61d 100644
--- a/esp32c6/src/ieee802154/rx_ack_timeout_cnt.rs
+++ b/esp32c6/src/ieee802154/rx_ack_timeout_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ACK_TIMEOUT_CNT")
-            .field(
-                "rx_ack_timeout_cnt",
-                &format_args!("{}", self.rx_ack_timeout_cnt().bits()),
-            )
+            .field("rx_ack_timeout_cnt", &self.rx_ack_timeout_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ACK_TIMEOUT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/rx_filter_fail_cnt.rs b/esp32c6/src/ieee802154/rx_filter_fail_cnt.rs
index 524fb2834a..e23abed76b 100644
--- a/esp32c6/src/ieee802154/rx_filter_fail_cnt.rs
+++ b/esp32c6/src/ieee802154/rx_filter_fail_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_FILTER_FAIL_CNT")
-            .field(
-                "rx_filter_fail_cnt",
-                &format_args!("{}", self.rx_filter_fail_cnt().bits()),
-            )
+            .field("rx_filter_fail_cnt", &self.rx_filter_fail_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_FILTER_FAIL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/rx_length.rs b/esp32c6/src/ieee802154/rx_length.rs
index d6dafb7ef6..f44d5c1008 100644
--- a/esp32c6/src/ieee802154/rx_length.rs
+++ b/esp32c6/src/ieee802154/rx_length.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_LENGTH")
-            .field("rx_length", &format_args!("{}", self.rx_length().bits()))
+            .field("rx_length", &self.rx_length())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_LENGTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/rx_restart_cnt.rs b/esp32c6/src/ieee802154/rx_restart_cnt.rs
index d5c1dae943..b0a8edb7a0 100644
--- a/esp32c6/src/ieee802154/rx_restart_cnt.rs
+++ b/esp32c6/src/ieee802154/rx_restart_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_RESTART_CNT")
-            .field(
-                "rx_restart_cnt",
-                &format_args!("{}", self.rx_restart_cnt().bits()),
-            )
+            .field("rx_restart_cnt", &self.rx_restart_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_RESTART_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/rx_status.rs b/esp32c6/src/ieee802154/rx_status.rs
index d15dde1ace..05d8570751 100644
--- a/esp32c6/src/ieee802154/rx_status.rs
+++ b/esp32c6/src/ieee802154/rx_status.rs
@@ -53,29 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_STATUS")
-            .field(
-                "filter_fail_status",
-                &format_args!("{}", self.filter_fail_status().bits()),
-            )
-            .field(
-                "rx_abort_status",
-                &format_args!("{}", self.rx_abort_status().bits()),
-            )
-            .field("rx_state", &format_args!("{}", self.rx_state().bits()))
-            .field(
-                "preamble_match",
-                &format_args!("{}", self.preamble_match().bit()),
-            )
-            .field("sfd_match", &format_args!("{}", self.sfd_match().bit()))
+            .field("filter_fail_status", &self.filter_fail_status())
+            .field("rx_abort_status", &self.rx_abort_status())
+            .field("rx_state", &self.rx_state())
+            .field("preamble_match", &self.preamble_match())
+            .field("sfd_match", &self.sfd_match())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/rxdma_addr.rs b/esp32c6/src/ieee802154/rxdma_addr.rs
index 0f1507832b..72e1b65151 100644
--- a/esp32c6/src/ieee802154/rxdma_addr.rs
+++ b/esp32c6/src/ieee802154/rxdma_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXDMA_ADDR")
-            .field("rxdma_addr", &format_args!("{}", self.rxdma_addr().bits()))
+            .field("rxdma_addr", &self.rxdma_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXDMA_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/rxdma_ctrl_state.rs b/esp32c6/src/ieee802154/rxdma_ctrl_state.rs
index 793edb2b19..b73a0c2ad0 100644
--- a/esp32c6/src/ieee802154/rxdma_ctrl_state.rs
+++ b/esp32c6/src/ieee802154/rxdma_ctrl_state.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXDMA_CTRL_STATE")
-            .field(
-                "rxdma_water_level",
-                &format_args!("{}", self.rxdma_water_level().bits()),
-            )
-            .field(
-                "rxdma_state",
-                &format_args!("{}", self.rxdma_state().bits()),
-            )
-            .field(
-                "rxdma_append_lqi_offset",
-                &format_args!("{}", self.rxdma_append_lqi_offset().bit()),
-            )
-            .field(
-                "rxdma_append_freq_offset",
-                &format_args!("{}", self.rxdma_append_freq_offset().bit()),
-            )
+            .field("rxdma_water_level", &self.rxdma_water_level())
+            .field("rxdma_state", &self.rxdma_state())
+            .field("rxdma_append_lqi_offset", &self.rxdma_append_lqi_offset())
+            .field("rxdma_append_freq_offset", &self.rxdma_append_freq_offset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXDMA_CTRL_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/rxdma_err.rs b/esp32c6/src/ieee802154/rxdma_err.rs
index 0e68599be1..9bd706d127 100644
--- a/esp32c6/src/ieee802154/rxdma_err.rs
+++ b/esp32c6/src/ieee802154/rxdma_err.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXDMA_ERR")
-            .field("rxdma_err", &format_args!("{}", self.rxdma_err().bits()))
+            .field("rxdma_err", &self.rxdma_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXDMA_ERR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/rxon_delay.rs b/esp32c6/src/ieee802154/rxon_delay.rs
index 59f8efb54c..82c64cadcd 100644
--- a/esp32c6/src/ieee802154/rxon_delay.rs
+++ b/esp32c6/src/ieee802154/rxon_delay.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXON_DELAY")
-            .field("rxon_delay", &format_args!("{}", self.rxon_delay().bits()))
+            .field("rxon_delay", &self.rxon_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXON_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/sec_ctrl.rs b/esp32c6/src/ieee802154/sec_ctrl.rs
index ce7a71f964..a06ca1b830 100644
--- a/esp32c6/src/ieee802154/sec_ctrl.rs
+++ b/esp32c6/src/ieee802154/sec_ctrl.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_CTRL")
-            .field("sec_en", &format_args!("{}", self.sec_en().bit()))
-            .field(
-                "sec_payload_offset",
-                &format_args!("{}", self.sec_payload_offset().bits()),
-            )
+            .field("sec_en", &self.sec_en())
+            .field("sec_payload_offset", &self.sec_payload_offset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/sec_extend_address0.rs b/esp32c6/src/ieee802154/sec_extend_address0.rs
index bcf15ee455..5ad42e9475 100644
--- a/esp32c6/src/ieee802154/sec_extend_address0.rs
+++ b/esp32c6/src/ieee802154/sec_extend_address0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_EXTEND_ADDRESS0")
-            .field(
-                "sec_extend_address0",
-                &format_args!("{}", self.sec_extend_address0().bits()),
-            )
+            .field("sec_extend_address0", &self.sec_extend_address0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_EXTEND_ADDRESS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/sec_extend_address1.rs b/esp32c6/src/ieee802154/sec_extend_address1.rs
index 5980c5a2a9..1c5284c7d1 100644
--- a/esp32c6/src/ieee802154/sec_extend_address1.rs
+++ b/esp32c6/src/ieee802154/sec_extend_address1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_EXTEND_ADDRESS1")
-            .field(
-                "sec_extend_address1",
-                &format_args!("{}", self.sec_extend_address1().bits()),
-            )
+            .field("sec_extend_address1", &self.sec_extend_address1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_EXTEND_ADDRESS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/sec_key0.rs b/esp32c6/src/ieee802154/sec_key0.rs
index f77ab23cc8..d35e2796cc 100644
--- a/esp32c6/src/ieee802154/sec_key0.rs
+++ b/esp32c6/src/ieee802154/sec_key0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_KEY0")
-            .field("sec_key0", &format_args!("{}", self.sec_key0().bits()))
+            .field("sec_key0", &self.sec_key0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_KEY0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/sec_key1.rs b/esp32c6/src/ieee802154/sec_key1.rs
index c23b34df06..e9a5c7109b 100644
--- a/esp32c6/src/ieee802154/sec_key1.rs
+++ b/esp32c6/src/ieee802154/sec_key1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_KEY1")
-            .field("sec_key1", &format_args!("{}", self.sec_key1().bits()))
+            .field("sec_key1", &self.sec_key1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_KEY1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/sec_key2.rs b/esp32c6/src/ieee802154/sec_key2.rs
index ac36dd0427..e1c8f22aba 100644
--- a/esp32c6/src/ieee802154/sec_key2.rs
+++ b/esp32c6/src/ieee802154/sec_key2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_KEY2")
-            .field("sec_key2", &format_args!("{}", self.sec_key2().bits()))
+            .field("sec_key2", &self.sec_key2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_KEY2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/sec_key3.rs b/esp32c6/src/ieee802154/sec_key3.rs
index 314e3c4cbd..4c99eac556 100644
--- a/esp32c6/src/ieee802154/sec_key3.rs
+++ b/esp32c6/src/ieee802154/sec_key3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_KEY3")
-            .field("sec_key3", &format_args!("{}", self.sec_key3().bits()))
+            .field("sec_key3", &self.sec_key3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_KEY3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/sfd_timeout_cnt.rs b/esp32c6/src/ieee802154/sfd_timeout_cnt.rs
index 1a3b328cfe..40025100e1 100644
--- a/esp32c6/src/ieee802154/sfd_timeout_cnt.rs
+++ b/esp32c6/src/ieee802154/sfd_timeout_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SFD_TIMEOUT_CNT")
-            .field(
-                "sfd_timeout_cnt",
-                &format_args!("{}", self.sfd_timeout_cnt().bits()),
-            )
+            .field("sfd_timeout_cnt", &self.sfd_timeout_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SFD_TIMEOUT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/sfd_wait_symbol.rs b/esp32c6/src/ieee802154/sfd_wait_symbol.rs
index 47feb148ce..5701663176 100644
--- a/esp32c6/src/ieee802154/sfd_wait_symbol.rs
+++ b/esp32c6/src/ieee802154/sfd_wait_symbol.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SFD_WAIT_SYMBOL")
-            .field("num", &format_args!("{}", self.num().bits()))
+            .field("num", &self.num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SFD_WAIT_SYMBOL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/test_control.rs b/esp32c6/src/ieee802154/test_control.rs
index 35d829b741..674080aaa0 100644
--- a/esp32c6/src/ieee802154/test_control.rs
+++ b/esp32c6/src/ieee802154/test_control.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEST_CONTROL")
-            .field("wrong_crc", &format_args!("{}", self.wrong_crc().bit()))
+            .field("wrong_crc", &self.wrong_crc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEST_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/time0_threshold.rs b/esp32c6/src/ieee802154/time0_threshold.rs
index 22e4126848..86d7e6c4d4 100644
--- a/esp32c6/src/ieee802154/time0_threshold.rs
+++ b/esp32c6/src/ieee802154/time0_threshold.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME0_THRESHOLD")
-            .field(
-                "timer0_threshold",
-                &format_args!("{}", self.timer0_threshold().bits()),
-            )
+            .field("timer0_threshold", &self.timer0_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME0_THRESHOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/time0_value.rs b/esp32c6/src/ieee802154/time0_value.rs
index 8e97397a2f..3f0f680851 100644
--- a/esp32c6/src/ieee802154/time0_value.rs
+++ b/esp32c6/src/ieee802154/time0_value.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME0_VALUE")
-            .field(
-                "timer0_value",
-                &format_args!("{}", self.timer0_value().bits()),
-            )
+            .field("timer0_value", &self.timer0_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME0_VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/time1_threshold.rs b/esp32c6/src/ieee802154/time1_threshold.rs
index acd0a23999..f68f9cb850 100644
--- a/esp32c6/src/ieee802154/time1_threshold.rs
+++ b/esp32c6/src/ieee802154/time1_threshold.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME1_THRESHOLD")
-            .field(
-                "timer1_threshold",
-                &format_args!("{}", self.timer1_threshold().bits()),
-            )
+            .field("timer1_threshold", &self.timer1_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME1_THRESHOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/time1_value.rs b/esp32c6/src/ieee802154/time1_value.rs
index fb643f1ee1..e36b50b51e 100644
--- a/esp32c6/src/ieee802154/time1_value.rs
+++ b/esp32c6/src/ieee802154/time1_value.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME1_VALUE")
-            .field(
-                "timer1_value",
-                &format_args!("{}", self.timer1_value().bits()),
-            )
+            .field("timer1_value", &self.timer1_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME1_VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/tx_abort_interrupt_control.rs b/esp32c6/src/ieee802154/tx_abort_interrupt_control.rs
index b7cda5f1de..ceb6cee0bb 100644
--- a/esp32c6/src/ieee802154/tx_abort_interrupt_control.rs
+++ b/esp32c6/src/ieee802154/tx_abort_interrupt_control.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("TX_ABORT_INTERRUPT_CONTROL")
             .field(
                 "tx_abort_interrupt_control",
-                &format_args!("{}", self.tx_abort_interrupt_control().bits()),
+                &self.tx_abort_interrupt_control(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_ABORT_INTERRUPT_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/tx_ack_abort_coex_cnt.rs b/esp32c6/src/ieee802154/tx_ack_abort_coex_cnt.rs
index 5e94e74a34..bc802a5131 100644
--- a/esp32c6/src/ieee802154/tx_ack_abort_coex_cnt.rs
+++ b/esp32c6/src/ieee802154/tx_ack_abort_coex_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_ACK_ABORT_COEX_CNT")
-            .field(
-                "tx_ack_abort_coex_cnt",
-                &format_args!("{}", self.tx_ack_abort_coex_cnt().bits()),
-            )
+            .field("tx_ack_abort_coex_cnt", &self.tx_ack_abort_coex_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_ACK_ABORT_COEX_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/tx_break_coex_cnt.rs b/esp32c6/src/ieee802154/tx_break_coex_cnt.rs
index af2d907cc3..fd4d555105 100644
--- a/esp32c6/src/ieee802154/tx_break_coex_cnt.rs
+++ b/esp32c6/src/ieee802154/tx_break_coex_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_BREAK_COEX_CNT")
-            .field(
-                "tx_break_coex_cnt",
-                &format_args!("{}", self.tx_break_coex_cnt().bits()),
-            )
+            .field("tx_break_coex_cnt", &self.tx_break_coex_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_BREAK_COEX_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/tx_ccm_schedule_status.rs b/esp32c6/src/ieee802154/tx_ccm_schedule_status.rs
index 3ccff89786..4df53e5c0a 100644
--- a/esp32c6/src/ieee802154/tx_ccm_schedule_status.rs
+++ b/esp32c6/src/ieee802154/tx_ccm_schedule_status.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CCM_SCHEDULE_STATUS")
-            .field(
-                "tx_ccm_schedule_status",
-                &format_args!("{}", self.tx_ccm_schedule_status().bits()),
-            )
+            .field("tx_ccm_schedule_status", &self.tx_ccm_schedule_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CCM_SCHEDULE_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/tx_power.rs b/esp32c6/src/ieee802154/tx_power.rs
index e70db2a041..8a7f29f818 100644
--- a/esp32c6/src/ieee802154/tx_power.rs
+++ b/esp32c6/src/ieee802154/tx_power.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_POWER")
-            .field("tx_power", &format_args!("{}", self.tx_power().bits()))
+            .field("tx_power", &self.tx_power())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/tx_security_error_cnt.rs b/esp32c6/src/ieee802154/tx_security_error_cnt.rs
index ca8d85ad86..ddf9e39309 100644
--- a/esp32c6/src/ieee802154/tx_security_error_cnt.rs
+++ b/esp32c6/src/ieee802154/tx_security_error_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_SECURITY_ERROR_CNT")
-            .field(
-                "tx_security_error_cnt",
-                &format_args!("{}", self.tx_security_error_cnt().bits()),
-            )
+            .field("tx_security_error_cnt", &self.tx_security_error_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_SECURITY_ERROR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/tx_status.rs b/esp32c6/src/ieee802154/tx_status.rs
index fda7601748..b8d8b68e30 100644
--- a/esp32c6/src/ieee802154/tx_status.rs
+++ b/esp32c6/src/ieee802154/tx_status.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_STATUS")
-            .field("tx_state", &format_args!("{}", self.tx_state().bits()))
-            .field(
-                "tx_abort_status",
-                &format_args!("{}", self.tx_abort_status().bits()),
-            )
-            .field(
-                "tx_sec_error_code",
-                &format_args!("{}", self.tx_sec_error_code().bits()),
-            )
+            .field("tx_state", &self.tx_state())
+            .field("tx_abort_status", &self.tx_abort_status())
+            .field("tx_sec_error_code", &self.tx_sec_error_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/txdma_addr.rs b/esp32c6/src/ieee802154/txdma_addr.rs
index 2b5c73f46d..486e3af98c 100644
--- a/esp32c6/src/ieee802154/txdma_addr.rs
+++ b/esp32c6/src/ieee802154/txdma_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXDMA_ADDR")
-            .field("txdma_addr", &format_args!("{}", self.txdma_addr().bits()))
+            .field("txdma_addr", &self.txdma_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXDMA_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/txdma_ctrl_state.rs b/esp32c6/src/ieee802154/txdma_ctrl_state.rs
index 0edaf10fe7..5b927f11e9 100644
--- a/esp32c6/src/ieee802154/txdma_ctrl_state.rs
+++ b/esp32c6/src/ieee802154/txdma_ctrl_state.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXDMA_CTRL_STATE")
-            .field(
-                "txdma_water_level",
-                &format_args!("{}", self.txdma_water_level().bits()),
-            )
-            .field(
-                "txdma_fill_entry",
-                &format_args!("{}", self.txdma_fill_entry().bits()),
-            )
-            .field(
-                "txdma_state",
-                &format_args!("{}", self.txdma_state().bits()),
-            )
-            .field(
-                "txdma_fetch_byte_cnt",
-                &format_args!("{}", self.txdma_fetch_byte_cnt().bits()),
-            )
+            .field("txdma_water_level", &self.txdma_water_level())
+            .field("txdma_fill_entry", &self.txdma_fill_entry())
+            .field("txdma_state", &self.txdma_state())
+            .field("txdma_fetch_byte_cnt", &self.txdma_fetch_byte_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXDMA_CTRL_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/txdma_err.rs b/esp32c6/src/ieee802154/txdma_err.rs
index c67edb2c9c..1a4ce416fb 100644
--- a/esp32c6/src/ieee802154/txdma_err.rs
+++ b/esp32c6/src/ieee802154/txdma_err.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXDMA_ERR")
-            .field("txdma_err", &format_args!("{}", self.txdma_err().bits()))
+            .field("txdma_err", &self.txdma_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXDMA_ERR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/txen_stop_delay.rs b/esp32c6/src/ieee802154/txen_stop_delay.rs
index df6e617df6..56290991f3 100644
--- a/esp32c6/src/ieee802154/txen_stop_delay.rs
+++ b/esp32c6/src/ieee802154/txen_stop_delay.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXEN_STOP_DELAY")
-            .field(
-                "txen_stop_dly",
-                &format_args!("{}", self.txen_stop_dly().bits()),
-            )
+            .field("txen_stop_dly", &self.txen_stop_dly())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXEN_STOP_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/txoff_delay.rs b/esp32c6/src/ieee802154/txoff_delay.rs
index bc396e4c4b..8dcc2a6ece 100644
--- a/esp32c6/src/ieee802154/txoff_delay.rs
+++ b/esp32c6/src/ieee802154/txoff_delay.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXOFF_DELAY")
-            .field(
-                "txoff_delay",
-                &format_args!("{}", self.txoff_delay().bits()),
-            )
+            .field("txoff_delay", &self.txoff_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXOFF_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/txon_delay.rs b/esp32c6/src/ieee802154/txon_delay.rs
index 9c8aac2b08..eb3d4ee152 100644
--- a/esp32c6/src/ieee802154/txon_delay.rs
+++ b/esp32c6/src/ieee802154/txon_delay.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXON_DELAY")
-            .field("txon_delay", &format_args!("{}", self.txon_delay().bits()))
+            .field("txon_delay", &self.txon_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXON_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/txrx_path_delay.rs b/esp32c6/src/ieee802154/txrx_path_delay.rs
index a4f0fc8ffb..e89d13b844 100644
--- a/esp32c6/src/ieee802154/txrx_path_delay.rs
+++ b/esp32c6/src/ieee802154/txrx_path_delay.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXRX_PATH_DELAY")
-            .field(
-                "tx_path_delay",
-                &format_args!("{}", self.tx_path_delay().bits()),
-            )
-            .field(
-                "rx_path_delay",
-                &format_args!("{}", self.rx_path_delay().bits()),
-            )
+            .field("tx_path_delay", &self.tx_path_delay())
+            .field("rx_path_delay", &self.rx_path_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXRX_PATH_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/txrx_status.rs b/esp32c6/src/ieee802154/txrx_status.rs
index aad8f52f7a..91584dd592 100644
--- a/esp32c6/src/ieee802154/txrx_status.rs
+++ b/esp32c6/src/ieee802154/txrx_status.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXRX_STATUS")
-            .field("txrx_state", &format_args!("{}", self.txrx_state().bits()))
-            .field("tx_proc", &format_args!("{}", self.tx_proc().bit()))
-            .field("rx_proc", &format_args!("{}", self.rx_proc().bit()))
-            .field("ed_proc", &format_args!("{}", self.ed_proc().bit()))
-            .field(
-                "ed_trigger_tx_proc",
-                &format_args!("{}", self.ed_trigger_tx_proc().bit()),
-            )
-            .field(
-                "rf_ctrl_state",
-                &format_args!("{}", self.rf_ctrl_state().bits()),
-            )
+            .field("txrx_state", &self.txrx_state())
+            .field("tx_proc", &self.tx_proc())
+            .field("rx_proc", &self.rx_proc())
+            .field("ed_proc", &self.ed_proc())
+            .field("ed_trigger_tx_proc", &self.ed_trigger_tx_proc())
+            .field("rf_ctrl_state", &self.rf_ctrl_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXRX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32c6/src/ieee802154/txrx_switch_delay.rs b/esp32c6/src/ieee802154/txrx_switch_delay.rs
index bb39a9a8c6..92ccc395e0 100644
--- a/esp32c6/src/ieee802154/txrx_switch_delay.rs
+++ b/esp32c6/src/ieee802154/txrx_switch_delay.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXRX_SWITCH_DELAY")
-            .field(
-                "txrx_switch_delay",
-                &format_args!("{}", self.txrx_switch_delay().bits()),
-            )
+            .field("txrx_switch_delay", &self.txrx_switch_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXRX_SWITCH_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/aes_intr_map.rs b/esp32c6/src/interrupt_core0/aes_intr_map.rs
index 6c6e7e8315..d160afa3a7 100644
--- a/esp32c6/src/interrupt_core0/aes_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/aes_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AES_INTR_MAP")
-            .field(
-                "aes_intr_map",
-                &format_args!("{}", self.aes_intr_map().bits()),
-            )
+            .field("aes_intr_map", &self.aes_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AES_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/apb_adc_intr_map.rs b/esp32c6/src/interrupt_core0/apb_adc_intr_map.rs
index d66baf9e67..ff1fddde3f 100644
--- a/esp32c6/src/interrupt_core0/apb_adc_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/apb_adc_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_ADC_INTR_MAP")
-            .field(
-                "apb_adc_intr_map",
-                &format_args!("{}", self.apb_adc_intr_map().bits()),
-            )
+            .field("apb_adc_intr_map", &self.apb_adc_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_ADC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/assist_debug_intr_map.rs b/esp32c6/src/interrupt_core0/assist_debug_intr_map.rs
index 076077ee3c..0bb44517d8 100644
--- a/esp32c6/src/interrupt_core0/assist_debug_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/assist_debug_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ASSIST_DEBUG_INTR_MAP")
-            .field(
-                "assist_debug_intr_map",
-                &format_args!("{}", self.assist_debug_intr_map().bits()),
-            )
+            .field("assist_debug_intr_map", &self.assist_debug_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ASSIST_DEBUG_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/ble_sec_intr_map.rs b/esp32c6/src/interrupt_core0/ble_sec_intr_map.rs
index 62ffc296f9..3cffdd1c9b 100644
--- a/esp32c6/src/interrupt_core0/ble_sec_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/ble_sec_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLE_SEC_INTR_MAP")
-            .field(
-                "ble_sec_intr_map",
-                &format_args!("{}", self.ble_sec_intr_map().bits()),
-            )
+            .field("ble_sec_intr_map", &self.ble_sec_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLE_SEC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/ble_timer_intr_map.rs b/esp32c6/src/interrupt_core0/ble_timer_intr_map.rs
index e132ad09ff..586fef0978 100644
--- a/esp32c6/src/interrupt_core0/ble_timer_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/ble_timer_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLE_TIMER_INTR_MAP")
-            .field(
-                "ble_timer_intr_map",
-                &format_args!("{}", self.ble_timer_intr_map().bits()),
-            )
+            .field("ble_timer_intr_map", &self.ble_timer_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLE_TIMER_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/bt_bb_intr_map.rs b/esp32c6/src/interrupt_core0/bt_bb_intr_map.rs
index 0ec68bb5a7..d8b210184a 100644
--- a/esp32c6/src/interrupt_core0/bt_bb_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/bt_bb_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_BB_INTR_MAP")
-            .field(
-                "bt_bb_intr_map",
-                &format_args!("{}", self.bt_bb_intr_map().bits()),
-            )
+            .field("bt_bb_intr_map", &self.bt_bb_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_BB_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/bt_bb_nmi_map.rs b/esp32c6/src/interrupt_core0/bt_bb_nmi_map.rs
index bb82782f07..ed8c9bec71 100644
--- a/esp32c6/src/interrupt_core0/bt_bb_nmi_map.rs
+++ b/esp32c6/src/interrupt_core0/bt_bb_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_BB_NMI_MAP")
-            .field(
-                "bt_bb_nmi_map",
-                &format_args!("{}", self.bt_bb_nmi_map().bits()),
-            )
+            .field("bt_bb_nmi_map", &self.bt_bb_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_BB_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/bt_mac_intr_map.rs b/esp32c6/src/interrupt_core0/bt_mac_intr_map.rs
index e9ff08c933..a396e1e0ee 100644
--- a/esp32c6/src/interrupt_core0/bt_mac_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/bt_mac_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_MAC_INTR_MAP")
-            .field(
-                "bt_mac_intr_map",
-                &format_args!("{}", self.bt_mac_intr_map().bits()),
-            )
+            .field("bt_mac_intr_map", &self.bt_mac_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_MAC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/cache_intr_map.rs b/esp32c6/src/interrupt_core0/cache_intr_map.rs
index fced7b7088..d9f26ce8ee 100644
--- a/esp32c6/src/interrupt_core0/cache_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/cache_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_INTR_MAP")
-            .field(
-                "cache_intr_map",
-                &format_args!("{}", self.cache_intr_map().bits()),
-            )
+            .field("cache_intr_map", &self.cache_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/can0_intr_map.rs b/esp32c6/src/interrupt_core0/can0_intr_map.rs
index adef475958..1095e1bef7 100644
--- a/esp32c6/src/interrupt_core0/can0_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/can0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAN0_INTR_MAP")
-            .field(
-                "can0_intr_map",
-                &format_args!("{}", self.can0_intr_map().bits()),
-            )
+            .field("can0_intr_map", &self.can0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAN0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/can1_intr_map.rs b/esp32c6/src/interrupt_core0/can1_intr_map.rs
index f81619ba0e..3f692b6ea5 100644
--- a/esp32c6/src/interrupt_core0/can1_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/can1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAN1_INTR_MAP")
-            .field(
-                "can1_intr_map",
-                &format_args!("{}", self.can1_intr_map().bits()),
-            )
+            .field("can1_intr_map", &self.can1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAN1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/clock_gate.rs b/esp32c6/src/interrupt_core0/clock_gate.rs
index 57e612f429..f275565282 100644
--- a/esp32c6/src/interrupt_core0/clock_gate.rs
+++ b/esp32c6/src/interrupt_core0/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("reg_clk_en", &format_args!("{}", self.reg_clk_en().bit()))
+            .field("reg_clk_en", &self.reg_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/coex_intr_map.rs b/esp32c6/src/interrupt_core0/coex_intr_map.rs
index 88cf991ee3..a84c9fcf3f 100644
--- a/esp32c6/src/interrupt_core0/coex_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/coex_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COEX_INTR_MAP")
-            .field(
-                "coex_intr_map",
-                &format_args!("{}", self.coex_intr_map().bits()),
-            )
+            .field("coex_intr_map", &self.coex_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COEX_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs b/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
index b13234a40f..7f50bfcac5 100644
--- a/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
+++ b/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_0_MAP")
-            .field(
-                "cpu_intr_from_cpu_0_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_0_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_0_map", &self.cpu_intr_from_cpu_0_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_0_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs b/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
index bb2fe4df7d..112775d93f 100644
--- a/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
+++ b/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_1_MAP")
-            .field(
-                "cpu_intr_from_cpu_1_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_1_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_1_map", &self.cpu_intr_from_cpu_1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs b/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
index eb3d17f93c..dd39cdc18f 100644
--- a/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
+++ b/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_2_MAP")
-            .field(
-                "cpu_intr_from_cpu_2_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_2_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_2_map", &self.cpu_intr_from_cpu_2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs b/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
index 2cff0addd2..4aebdf5186 100644
--- a/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
+++ b/esp32c6/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_3_MAP")
-            .field(
-                "cpu_intr_from_cpu_3_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_3_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_3_map", &self.cpu_intr_from_cpu_3_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/cpu_peri_timeout_intr_map.rs b/esp32c6/src/interrupt_core0/cpu_peri_timeout_intr_map.rs
index 9e0243c5de..3d885e384d 100644
--- a/esp32c6/src/interrupt_core0/cpu_peri_timeout_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/cpu_peri_timeout_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CPU_PERI_TIMEOUT_INTR_MAP")
             .field(
                 "cpu_peri_timeout_intr_map",
-                &format_args!("{}", self.cpu_peri_timeout_intr_map().bits()),
+                &self.cpu_peri_timeout_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_TIMEOUT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/dma_in_ch0_intr_map.rs b/esp32c6/src/interrupt_core0/dma_in_ch0_intr_map.rs
index 62ef1a9c5b..9555cf0c38 100644
--- a/esp32c6/src/interrupt_core0/dma_in_ch0_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/dma_in_ch0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH0_INTR_MAP")
-            .field(
-                "dma_in_ch0_intr_map",
-                &format_args!("{}", self.dma_in_ch0_intr_map().bits()),
-            )
+            .field("dma_in_ch0_intr_map", &self.dma_in_ch0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/dma_in_ch1_intr_map.rs b/esp32c6/src/interrupt_core0/dma_in_ch1_intr_map.rs
index 021c6118d0..3996f00d56 100644
--- a/esp32c6/src/interrupt_core0/dma_in_ch1_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/dma_in_ch1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH1_INTR_MAP")
-            .field(
-                "dma_in_ch1_intr_map",
-                &format_args!("{}", self.dma_in_ch1_intr_map().bits()),
-            )
+            .field("dma_in_ch1_intr_map", &self.dma_in_ch1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/dma_in_ch2_intr_map.rs b/esp32c6/src/interrupt_core0/dma_in_ch2_intr_map.rs
index 34973c4367..efa1a3f1cb 100644
--- a/esp32c6/src/interrupt_core0/dma_in_ch2_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/dma_in_ch2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH2_INTR_MAP")
-            .field(
-                "dma_in_ch2_intr_map",
-                &format_args!("{}", self.dma_in_ch2_intr_map().bits()),
-            )
+            .field("dma_in_ch2_intr_map", &self.dma_in_ch2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/dma_out_ch0_intr_map.rs b/esp32c6/src/interrupt_core0/dma_out_ch0_intr_map.rs
index ee4ab9e738..d795bc7362 100644
--- a/esp32c6/src/interrupt_core0/dma_out_ch0_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/dma_out_ch0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH0_INTR_MAP")
-            .field(
-                "dma_out_ch0_intr_map",
-                &format_args!("{}", self.dma_out_ch0_intr_map().bits()),
-            )
+            .field("dma_out_ch0_intr_map", &self.dma_out_ch0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/dma_out_ch1_intr_map.rs b/esp32c6/src/interrupt_core0/dma_out_ch1_intr_map.rs
index e66add3d55..f19212e0f1 100644
--- a/esp32c6/src/interrupt_core0/dma_out_ch1_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/dma_out_ch1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH1_INTR_MAP")
-            .field(
-                "dma_out_ch1_intr_map",
-                &format_args!("{}", self.dma_out_ch1_intr_map().bits()),
-            )
+            .field("dma_out_ch1_intr_map", &self.dma_out_ch1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/dma_out_ch2_intr_map.rs b/esp32c6/src/interrupt_core0/dma_out_ch2_intr_map.rs
index 93c58571db..7bb1124653 100644
--- a/esp32c6/src/interrupt_core0/dma_out_ch2_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/dma_out_ch2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH2_INTR_MAP")
-            .field(
-                "dma_out_ch2_intr_map",
-                &format_args!("{}", self.dma_out_ch2_intr_map().bits()),
-            )
+            .field("dma_out_ch2_intr_map", &self.dma_out_ch2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/ecc_intr_map.rs b/esp32c6/src/interrupt_core0/ecc_intr_map.rs
index 8b64aa9368..b20a68f4dd 100644
--- a/esp32c6/src/interrupt_core0/ecc_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/ecc_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_INTR_MAP")
-            .field(
-                "ecc_intr_map",
-                &format_args!("{}", self.ecc_intr_map().bits()),
-            )
+            .field("ecc_intr_map", &self.ecc_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/efuse_intr_map.rs b/esp32c6/src/interrupt_core0/efuse_intr_map.rs
index 2c9ffe0bf3..69bef44640 100644
--- a/esp32c6/src/interrupt_core0/efuse_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/efuse_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EFUSE_INTR_MAP")
-            .field(
-                "efuse_intr_map",
-                &format_args!("{}", self.efuse_intr_map().bits()),
-            )
+            .field("efuse_intr_map", &self.efuse_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EFUSE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/gpio_interrupt_pro_map.rs b/esp32c6/src/interrupt_core0/gpio_interrupt_pro_map.rs
index a793a47730..022da9106e 100644
--- a/esp32c6/src/interrupt_core0/gpio_interrupt_pro_map.rs
+++ b/esp32c6/src/interrupt_core0/gpio_interrupt_pro_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INTERRUPT_PRO_MAP")
-            .field(
-                "gpio_interrupt_pro_map",
-                &format_args!("{}", self.gpio_interrupt_pro_map().bits()),
-            )
+            .field("gpio_interrupt_pro_map", &self.gpio_interrupt_pro_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_PRO_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs b/esp32c6/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
index a946ff6d89..76820b70f0 100644
--- a/esp32c6/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
+++ b/esp32c6/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("GPIO_INTERRUPT_PRO_NMI_MAP")
             .field(
                 "gpio_interrupt_pro_nmi_map",
-                &format_args!("{}", self.gpio_interrupt_pro_nmi_map().bits()),
+                &self.gpio_interrupt_pro_nmi_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_PRO_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/gpspi2_intr_map.rs b/esp32c6/src/interrupt_core0/gpspi2_intr_map.rs
index f68c5ffae0..57a0bba415 100644
--- a/esp32c6/src/interrupt_core0/gpspi2_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/gpspi2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPSPI2_INTR_MAP")
-            .field(
-                "gpspi2_intr_map",
-                &format_args!("{}", self.gpspi2_intr_map().bits()),
-            )
+            .field("gpspi2_intr_map", &self.gpspi2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPSPI2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/hp_apm_m0_intr_map.rs b/esp32c6/src/interrupt_core0/hp_apm_m0_intr_map.rs
index f36199d70e..13ec757b99 100644
--- a/esp32c6/src/interrupt_core0/hp_apm_m0_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/hp_apm_m0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_APM_M0_INTR_MAP")
-            .field(
-                "hp_apm_m0_intr_map",
-                &format_args!("{}", self.hp_apm_m0_intr_map().bits()),
-            )
+            .field("hp_apm_m0_intr_map", &self.hp_apm_m0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_APM_M0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/hp_apm_m1_intr_map.rs b/esp32c6/src/interrupt_core0/hp_apm_m1_intr_map.rs
index b5d6e57057..442bce4885 100644
--- a/esp32c6/src/interrupt_core0/hp_apm_m1_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/hp_apm_m1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_APM_M1_INTR_MAP")
-            .field(
-                "hp_apm_m1_intr_map",
-                &format_args!("{}", self.hp_apm_m1_intr_map().bits()),
-            )
+            .field("hp_apm_m1_intr_map", &self.hp_apm_m1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_APM_M1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/hp_apm_m2_intr_map.rs b/esp32c6/src/interrupt_core0/hp_apm_m2_intr_map.rs
index 4e3d32dee1..0018465abe 100644
--- a/esp32c6/src/interrupt_core0/hp_apm_m2_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/hp_apm_m2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_APM_M2_INTR_MAP")
-            .field(
-                "hp_apm_m2_intr_map",
-                &format_args!("{}", self.hp_apm_m2_intr_map().bits()),
-            )
+            .field("hp_apm_m2_intr_map", &self.hp_apm_m2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_APM_M2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/hp_apm_m3_intr_map.rs b/esp32c6/src/interrupt_core0/hp_apm_m3_intr_map.rs
index 3f0c57779c..9e7a42aa2a 100644
--- a/esp32c6/src/interrupt_core0/hp_apm_m3_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/hp_apm_m3_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_APM_M3_INTR_MAP")
-            .field(
-                "hp_apm_m3_intr_map",
-                &format_args!("{}", self.hp_apm_m3_intr_map().bits()),
-            )
+            .field("hp_apm_m3_intr_map", &self.hp_apm_m3_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_APM_M3_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/hp_peri_timeout_intr_map.rs b/esp32c6/src/interrupt_core0/hp_peri_timeout_intr_map.rs
index 33e58d196a..a15b5cde90 100644
--- a/esp32c6/src/interrupt_core0/hp_peri_timeout_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/hp_peri_timeout_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_PERI_TIMEOUT_INTR_MAP")
-            .field(
-                "hp_peri_timeout_intr_map",
-                &format_args!("{}", self.hp_peri_timeout_intr_map().bits()),
-            )
+            .field("hp_peri_timeout_intr_map", &self.hp_peri_timeout_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_PERI_TIMEOUT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/i2c_ext0_intr_map.rs b/esp32c6/src/interrupt_core0/i2c_ext0_intr_map.rs
index 7cb40c692a..812e727ab2 100644
--- a/esp32c6/src/interrupt_core0/i2c_ext0_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/i2c_ext0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_EXT0_INTR_MAP")
-            .field(
-                "i2c_ext0_intr_map",
-                &format_args!("{}", self.i2c_ext0_intr_map().bits()),
-            )
+            .field("i2c_ext0_intr_map", &self.i2c_ext0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_EXT0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/i2c_mst_intr_map.rs b/esp32c6/src/interrupt_core0/i2c_mst_intr_map.rs
index 9fb08fed87..c43b21a043 100644
--- a/esp32c6/src/interrupt_core0/i2c_mst_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/i2c_mst_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_MST_INTR_MAP")
-            .field(
-                "i2c_mst_intr_map",
-                &format_args!("{}", self.i2c_mst_intr_map().bits()),
-            )
+            .field("i2c_mst_intr_map", &self.i2c_mst_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_MST_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/i2s1_intr_map.rs b/esp32c6/src/interrupt_core0/i2s1_intr_map.rs
index 456b46911d..ab3b6574ef 100644
--- a/esp32c6/src/interrupt_core0/i2s1_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/i2s1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S1_INTR_MAP")
-            .field(
-                "i2s1_intr_map",
-                &format_args!("{}", self.i2s1_intr_map().bits()),
-            )
+            .field("i2s1_intr_map", &self.i2s1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/int_status_reg_2.rs b/esp32c6/src/interrupt_core0/int_status_reg_2.rs
index 5f11d3dbbf..823787cb41 100644
--- a/esp32c6/src/interrupt_core0/int_status_reg_2.rs
+++ b/esp32c6/src/interrupt_core0/int_status_reg_2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_STATUS_REG_2")
-            .field(
-                "int_status_2",
-                &format_args!("{}", self.int_status_2().bits()),
-            )
+            .field("int_status_2", &self.int_status_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_STATUS_REG_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_status_reg_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_STATUS_REG_2_SPEC;
 impl crate::RegisterSpec for INT_STATUS_REG_2_SPEC {
diff --git a/esp32c6/src/interrupt_core0/interrupt_reg_date.rs b/esp32c6/src/interrupt_core0/interrupt_reg_date.rs
index c6b717140d..5cd5dcca51 100644
--- a/esp32c6/src/interrupt_core0/interrupt_reg_date.rs
+++ b/esp32c6/src/interrupt_core0/interrupt_reg_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT_REG_DATE")
-            .field(
-                "interrupt_reg_date",
-                &format_args!("{}", self.interrupt_reg_date().bits()),
-            )
+            .field("interrupt_reg_date", &self.interrupt_reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/intr_status_reg_0.rs b/esp32c6/src/interrupt_core0/intr_status_reg_0.rs
index cc8075d962..89b267af7a 100644
--- a/esp32c6/src/interrupt_core0/intr_status_reg_0.rs
+++ b/esp32c6/src/interrupt_core0/intr_status_reg_0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_0")
-            .field(
-                "intr_status_0",
-                &format_args!("{}", self.intr_status_0().bits()),
-            )
+            .field("intr_status_0", &self.intr_status_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_0_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_0_SPEC {
diff --git a/esp32c6/src/interrupt_core0/intr_status_reg_1.rs b/esp32c6/src/interrupt_core0/intr_status_reg_1.rs
index 2ba3ae0e12..1b93576572 100644
--- a/esp32c6/src/interrupt_core0/intr_status_reg_1.rs
+++ b/esp32c6/src/interrupt_core0/intr_status_reg_1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_1")
-            .field(
-                "intr_status_1",
-                &format_args!("{}", self.intr_status_1().bits()),
-            )
+            .field("intr_status_1", &self.intr_status_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_1_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_1_SPEC {
diff --git a/esp32c6/src/interrupt_core0/ledc_intr_map.rs b/esp32c6/src/interrupt_core0/ledc_intr_map.rs
index c664eb3d64..16ed96e4aa 100644
--- a/esp32c6/src/interrupt_core0/ledc_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/ledc_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEDC_INTR_MAP")
-            .field(
-                "ledc_intr_map",
-                &format_args!("{}", self.ledc_intr_map().bits()),
-            )
+            .field("ledc_intr_map", &self.ledc_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEDC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/lp_apm0_intr_map.rs b/esp32c6/src/interrupt_core0/lp_apm0_intr_map.rs
index 100e8c7620..d425becbed 100644
--- a/esp32c6/src/interrupt_core0/lp_apm0_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/lp_apm0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_APM0_INTR_MAP")
-            .field(
-                "lp_apm0_intr_map",
-                &format_args!("{}", self.lp_apm0_intr_map().bits()),
-            )
+            .field("lp_apm0_intr_map", &self.lp_apm0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_APM0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/lp_apm_m0_intr_map.rs b/esp32c6/src/interrupt_core0/lp_apm_m0_intr_map.rs
index 80aed9105c..f8de93a52d 100644
--- a/esp32c6/src/interrupt_core0/lp_apm_m0_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/lp_apm_m0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_APM_M0_INTR_MAP")
-            .field(
-                "lp_apm_m0_intr_map",
-                &format_args!("{}", self.lp_apm_m0_intr_map().bits()),
-            )
+            .field("lp_apm_m0_intr_map", &self.lp_apm_m0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_APM_M0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/lp_apm_m1_intr_map.rs b/esp32c6/src/interrupt_core0/lp_apm_m1_intr_map.rs
index 3317520a61..3b785eac1d 100644
--- a/esp32c6/src/interrupt_core0/lp_apm_m1_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/lp_apm_m1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_APM_M1_INTR_MAP")
-            .field(
-                "lp_apm_m1_intr_map",
-                &format_args!("{}", self.lp_apm_m1_intr_map().bits()),
-            )
+            .field("lp_apm_m1_intr_map", &self.lp_apm_m1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_APM_M1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/lp_i2c_intr_map.rs b/esp32c6/src/interrupt_core0/lp_i2c_intr_map.rs
index 353f69bacc..600a6ff6fd 100644
--- a/esp32c6/src/interrupt_core0/lp_i2c_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/lp_i2c_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_I2C_INTR_MAP")
-            .field(
-                "lp_i2c_intr_map",
-                &format_args!("{}", self.lp_i2c_intr_map().bits()),
-            )
+            .field("lp_i2c_intr_map", &self.lp_i2c_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_I2C_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/lp_peri_timeout_intr_map.rs b/esp32c6/src/interrupt_core0/lp_peri_timeout_intr_map.rs
index 223807ec4a..b407e9eba3 100644
--- a/esp32c6/src/interrupt_core0/lp_peri_timeout_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/lp_peri_timeout_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_PERI_TIMEOUT_INTR_MAP")
-            .field(
-                "lp_peri_timeout_intr_map",
-                &format_args!("{}", self.lp_peri_timeout_intr_map().bits()),
-            )
+            .field("lp_peri_timeout_intr_map", &self.lp_peri_timeout_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_PERI_TIMEOUT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/lp_rtc_timer_intr_map.rs b/esp32c6/src/interrupt_core0/lp_rtc_timer_intr_map.rs
index 6bf5df25d1..f182508ca8 100644
--- a/esp32c6/src/interrupt_core0/lp_rtc_timer_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/lp_rtc_timer_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_RTC_TIMER_INTR_MAP")
-            .field(
-                "lp_rtc_timer_intr_map",
-                &format_args!("{}", self.lp_rtc_timer_intr_map().bits()),
-            )
+            .field("lp_rtc_timer_intr_map", &self.lp_rtc_timer_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_RTC_TIMER_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/lp_timer_intr_map.rs b/esp32c6/src/interrupt_core0/lp_timer_intr_map.rs
index 6dd980b3de..3331ff4956 100644
--- a/esp32c6/src/interrupt_core0/lp_timer_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/lp_timer_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_TIMER_INTR_MAP")
-            .field(
-                "lp_timer_intr_map",
-                &format_args!("{}", self.lp_timer_intr_map().bits()),
-            )
+            .field("lp_timer_intr_map", &self.lp_timer_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TIMER_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/lp_uart_intr_map.rs b/esp32c6/src/interrupt_core0/lp_uart_intr_map.rs
index 8da6fa9f86..cb1329f2cb 100644
--- a/esp32c6/src/interrupt_core0/lp_uart_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/lp_uart_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_UART_INTR_MAP")
-            .field(
-                "lp_uart_intr_map",
-                &format_args!("{}", self.lp_uart_intr_map().bits()),
-            )
+            .field("lp_uart_intr_map", &self.lp_uart_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_UART_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/lp_wdt_intr_map.rs b/esp32c6/src/interrupt_core0/lp_wdt_intr_map.rs
index 56ca63fb35..7e30b5e88b 100644
--- a/esp32c6/src/interrupt_core0/lp_wdt_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/lp_wdt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_WDT_INTR_MAP")
-            .field(
-                "lp_wdt_intr_map",
-                &format_args!("{}", self.lp_wdt_intr_map().bits()),
-            )
+            .field("lp_wdt_intr_map", &self.lp_wdt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_WDT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/modem_peri_timeout_intr_map.rs b/esp32c6/src/interrupt_core0/modem_peri_timeout_intr_map.rs
index 4132276ea4..b2e207ad9f 100644
--- a/esp32c6/src/interrupt_core0/modem_peri_timeout_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/modem_peri_timeout_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("MODEM_PERI_TIMEOUT_INTR_MAP")
             .field(
                 "modem_peri_timeout_intr_map",
-                &format_args!("{}", self.modem_peri_timeout_intr_map().bits()),
+                &self.modem_peri_timeout_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODEM_PERI_TIMEOUT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/mspi_intr_map.rs b/esp32c6/src/interrupt_core0/mspi_intr_map.rs
index 4c7ede7b8b..dbdf6df34a 100644
--- a/esp32c6/src/interrupt_core0/mspi_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/mspi_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MSPI_INTR_MAP")
-            .field(
-                "mspi_intr_map",
-                &format_args!("{}", self.mspi_intr_map().bits()),
-            )
+            .field("mspi_intr_map", &self.mspi_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MSPI_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/parl_io_intr_map.rs b/esp32c6/src/interrupt_core0/parl_io_intr_map.rs
index fa8c6e5891..73cf0ec626 100644
--- a/esp32c6/src/interrupt_core0/parl_io_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/parl_io_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PARL_IO_INTR_MAP")
-            .field(
-                "parl_io_intr_map",
-                &format_args!("{}", self.parl_io_intr_map().bits()),
-            )
+            .field("parl_io_intr_map", &self.parl_io_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PARL_IO_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/pau_intr_map.rs b/esp32c6/src/interrupt_core0/pau_intr_map.rs
index d9bd6c6d13..c5aad10885 100644
--- a/esp32c6/src/interrupt_core0/pau_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/pau_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAU_INTR_MAP")
-            .field(
-                "pau_intr_map",
-                &format_args!("{}", self.pau_intr_map().bits()),
-            )
+            .field("pau_intr_map", &self.pau_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAU_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/pcnt_intr_map.rs b/esp32c6/src/interrupt_core0/pcnt_intr_map.rs
index c54fa9951e..19bc8dc1ad 100644
--- a/esp32c6/src/interrupt_core0/pcnt_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/pcnt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCNT_INTR_MAP")
-            .field(
-                "pcnt_intr_map",
-                &format_args!("{}", self.pcnt_intr_map().bits()),
-            )
+            .field("pcnt_intr_map", &self.pcnt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCNT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/pmu_intr_map.rs b/esp32c6/src/interrupt_core0/pmu_intr_map.rs
index fe79459443..482d2d6318 100644
--- a/esp32c6/src/interrupt_core0/pmu_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/pmu_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMU_INTR_MAP")
-            .field(
-                "pmu_intr_map",
-                &format_args!("{}", self.pmu_intr_map().bits()),
-            )
+            .field("pmu_intr_map", &self.pmu_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMU_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/pwm_intr_map.rs b/esp32c6/src/interrupt_core0/pwm_intr_map.rs
index d018ace099..225cc48bb6 100644
--- a/esp32c6/src/interrupt_core0/pwm_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/pwm_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM_INTR_MAP")
-            .field(
-                "pwm_intr_map",
-                &format_args!("{}", self.pwm_intr_map().bits()),
-            )
+            .field("pwm_intr_map", &self.pwm_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/rmt_intr_map.rs b/esp32c6/src/interrupt_core0/rmt_intr_map.rs
index 09a41d6297..2157e8bef1 100644
--- a/esp32c6/src/interrupt_core0/rmt_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/rmt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RMT_INTR_MAP")
-            .field(
-                "rmt_intr_map",
-                &format_args!("{}", self.rmt_intr_map().bits()),
-            )
+            .field("rmt_intr_map", &self.rmt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RMT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/rsa_intr_map.rs b/esp32c6/src/interrupt_core0/rsa_intr_map.rs
index 9daae9ddd9..0e71526cdf 100644
--- a/esp32c6/src/interrupt_core0/rsa_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/rsa_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_INTR_MAP")
-            .field(
-                "rsa_intr_map",
-                &format_args!("{}", self.rsa_intr_map().bits()),
-            )
+            .field("rsa_intr_map", &self.rsa_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/sha_intr_map.rs b/esp32c6/src/interrupt_core0/sha_intr_map.rs
index d68441648f..cb6a93e0e3 100644
--- a/esp32c6/src/interrupt_core0/sha_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/sha_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA_INTR_MAP")
-            .field(
-                "sha_intr_map",
-                &format_args!("{}", self.sha_intr_map().bits()),
-            )
+            .field("sha_intr_map", &self.sha_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/slc0_intr_map.rs b/esp32c6/src/interrupt_core0/slc0_intr_map.rs
index 01e7dd4c8f..e78e9adb93 100644
--- a/esp32c6/src/interrupt_core0/slc0_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/slc0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC0_INTR_MAP")
-            .field(
-                "slc0_intr_map",
-                &format_args!("{}", self.slc0_intr_map().bits()),
-            )
+            .field("slc0_intr_map", &self.slc0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/slc1_intr_map.rs b/esp32c6/src/interrupt_core0/slc1_intr_map.rs
index c3e3fa50ab..f79fa39fbd 100644
--- a/esp32c6/src/interrupt_core0/slc1_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/slc1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC1_INTR_MAP")
-            .field(
-                "slc1_intr_map",
-                &format_args!("{}", self.slc1_intr_map().bits()),
-            )
+            .field("slc1_intr_map", &self.slc1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/systimer_target0_intr_map.rs b/esp32c6/src/interrupt_core0/systimer_target0_intr_map.rs
index 287d7e4287..7222090e13 100644
--- a/esp32c6/src/interrupt_core0/systimer_target0_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/systimer_target0_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYSTIMER_TARGET0_INTR_MAP")
             .field(
                 "systimer_target0_intr_map",
-                &format_args!("{}", self.systimer_target0_intr_map().bits()),
+                &self.systimer_target0_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/systimer_target1_intr_map.rs b/esp32c6/src/interrupt_core0/systimer_target1_intr_map.rs
index eade50af6a..d5dc3616f4 100644
--- a/esp32c6/src/interrupt_core0/systimer_target1_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/systimer_target1_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYSTIMER_TARGET1_INTR_MAP")
             .field(
                 "systimer_target1_intr_map",
-                &format_args!("{}", self.systimer_target1_intr_map().bits()),
+                &self.systimer_target1_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/systimer_target2_intr_map.rs b/esp32c6/src/interrupt_core0/systimer_target2_intr_map.rs
index 08751eb62b..1d2a2ffeb3 100644
--- a/esp32c6/src/interrupt_core0/systimer_target2_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/systimer_target2_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYSTIMER_TARGET2_INTR_MAP")
             .field(
                 "systimer_target2_intr_map",
-                &format_args!("{}", self.systimer_target2_intr_map().bits()),
+                &self.systimer_target2_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/tg0_t0_intr_map.rs b/esp32c6/src/interrupt_core0/tg0_t0_intr_map.rs
index 7435771514..bebed1dcee 100644
--- a/esp32c6/src/interrupt_core0/tg0_t0_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/tg0_t0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG0_T0_INTR_MAP")
-            .field(
-                "tg0_t0_intr_map",
-                &format_args!("{}", self.tg0_t0_intr_map().bits()),
-            )
+            .field("tg0_t0_intr_map", &self.tg0_t0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG0_T0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/tg0_t1_intr_map.rs b/esp32c6/src/interrupt_core0/tg0_t1_intr_map.rs
index e429346261..03ea1bb3ea 100644
--- a/esp32c6/src/interrupt_core0/tg0_t1_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/tg0_t1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG0_T1_INTR_MAP")
-            .field(
-                "tg0_t1_intr_map",
-                &format_args!("{}", self.tg0_t1_intr_map().bits()),
-            )
+            .field("tg0_t1_intr_map", &self.tg0_t1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG0_T1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/tg0_wdt_intr_map.rs b/esp32c6/src/interrupt_core0/tg0_wdt_intr_map.rs
index 4ea0dd3399..e880de1013 100644
--- a/esp32c6/src/interrupt_core0/tg0_wdt_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/tg0_wdt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG0_WDT_INTR_MAP")
-            .field(
-                "tg0_wdt_intr_map",
-                &format_args!("{}", self.tg0_wdt_intr_map().bits()),
-            )
+            .field("tg0_wdt_intr_map", &self.tg0_wdt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG0_WDT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/tg1_t0_intr_map.rs b/esp32c6/src/interrupt_core0/tg1_t0_intr_map.rs
index 902aea12a1..85ad97dfcf 100644
--- a/esp32c6/src/interrupt_core0/tg1_t0_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/tg1_t0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG1_T0_INTR_MAP")
-            .field(
-                "tg1_t0_intr_map",
-                &format_args!("{}", self.tg1_t0_intr_map().bits()),
-            )
+            .field("tg1_t0_intr_map", &self.tg1_t0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG1_T0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/tg1_t1_intr_map.rs b/esp32c6/src/interrupt_core0/tg1_t1_intr_map.rs
index e4145c49b7..1303a2f3cd 100644
--- a/esp32c6/src/interrupt_core0/tg1_t1_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/tg1_t1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG1_T1_INTR_MAP")
-            .field(
-                "tg1_t1_intr_map",
-                &format_args!("{}", self.tg1_t1_intr_map().bits()),
-            )
+            .field("tg1_t1_intr_map", &self.tg1_t1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG1_T1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/tg1_wdt_intr_map.rs b/esp32c6/src/interrupt_core0/tg1_wdt_intr_map.rs
index 5434cad1b1..adb035ce06 100644
--- a/esp32c6/src/interrupt_core0/tg1_wdt_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/tg1_wdt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG1_WDT_INTR_MAP")
-            .field(
-                "tg1_wdt_intr_map",
-                &format_args!("{}", self.tg1_wdt_intr_map().bits()),
-            )
+            .field("tg1_wdt_intr_map", &self.tg1_wdt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG1_WDT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/trace_intr_map.rs b/esp32c6/src/interrupt_core0/trace_intr_map.rs
index e30f50ea28..11dee24738 100644
--- a/esp32c6/src/interrupt_core0/trace_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/trace_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TRACE_INTR_MAP")
-            .field(
-                "trace_intr_map",
-                &format_args!("{}", self.trace_intr_map().bits()),
-            )
+            .field("trace_intr_map", &self.trace_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TRACE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/uart0_intr_map.rs b/esp32c6/src/interrupt_core0/uart0_intr_map.rs
index 4b3ec7db5d..817383d02f 100644
--- a/esp32c6/src/interrupt_core0/uart0_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/uart0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART0_INTR_MAP")
-            .field(
-                "uart0_intr_map",
-                &format_args!("{}", self.uart0_intr_map().bits()),
-            )
+            .field("uart0_intr_map", &self.uart0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/uart1_intr_map.rs b/esp32c6/src/interrupt_core0/uart1_intr_map.rs
index b19f64d061..992884832c 100644
--- a/esp32c6/src/interrupt_core0/uart1_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/uart1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART1_INTR_MAP")
-            .field(
-                "uart1_intr_map",
-                &format_args!("{}", self.uart1_intr_map().bits()),
-            )
+            .field("uart1_intr_map", &self.uart1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/uhci0_intr_map.rs b/esp32c6/src/interrupt_core0/uhci0_intr_map.rs
index 804eca17fb..012bf9cc43 100644
--- a/esp32c6/src/interrupt_core0/uhci0_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/uhci0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UHCI0_INTR_MAP")
-            .field(
-                "uhci0_intr_map",
-                &format_args!("{}", self.uhci0_intr_map().bits()),
-            )
+            .field("uhci0_intr_map", &self.uhci0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UHCI0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/usb_intr_map.rs b/esp32c6/src/interrupt_core0/usb_intr_map.rs
index 6c523aebe5..70af439c40 100644
--- a/esp32c6/src/interrupt_core0/usb_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/usb_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_INTR_MAP")
-            .field(
-                "usb_intr_map",
-                &format_args!("{}", self.usb_intr_map().bits()),
-            )
+            .field("usb_intr_map", &self.usb_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/wifi_bb_intr_map.rs b/esp32c6/src/interrupt_core0/wifi_bb_intr_map.rs
index 61b422ef64..7e846598d6 100644
--- a/esp32c6/src/interrupt_core0/wifi_bb_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/wifi_bb_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_BB_INTR_MAP")
-            .field(
-                "wifi_bb_intr_map",
-                &format_args!("{}", self.wifi_bb_intr_map().bits()),
-            )
+            .field("wifi_bb_intr_map", &self.wifi_bb_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_BB_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/wifi_mac_intr_map.rs b/esp32c6/src/interrupt_core0/wifi_mac_intr_map.rs
index d57632ff82..857ceafa95 100644
--- a/esp32c6/src/interrupt_core0/wifi_mac_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/wifi_mac_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_MAC_INTR_MAP")
-            .field(
-                "wifi_mac_intr_map",
-                &format_args!("{}", self.wifi_mac_intr_map().bits()),
-            )
+            .field("wifi_mac_intr_map", &self.wifi_mac_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_MAC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/wifi_mac_nmi_map.rs b/esp32c6/src/interrupt_core0/wifi_mac_nmi_map.rs
index 1ff2b63854..72b9cb1f93 100644
--- a/esp32c6/src/interrupt_core0/wifi_mac_nmi_map.rs
+++ b/esp32c6/src/interrupt_core0/wifi_mac_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_MAC_NMI_MAP")
-            .field(
-                "wifi_mac_nmi_map",
-                &format_args!("{}", self.wifi_mac_nmi_map().bits()),
-            )
+            .field("wifi_mac_nmi_map", &self.wifi_mac_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_MAC_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/wifi_pwr_intr_map.rs b/esp32c6/src/interrupt_core0/wifi_pwr_intr_map.rs
index 7f1a7a1f46..f23debdb99 100644
--- a/esp32c6/src/interrupt_core0/wifi_pwr_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/wifi_pwr_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_PWR_INTR_MAP")
-            .field(
-                "wifi_pwr_intr_map",
-                &format_args!("{}", self.wifi_pwr_intr_map().bits()),
-            )
+            .field("wifi_pwr_intr_map", &self.wifi_pwr_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_PWR_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/interrupt_core0/zb_mac_intr_map.rs b/esp32c6/src/interrupt_core0/zb_mac_intr_map.rs
index fe5125cfea..14b3cea99c 100644
--- a/esp32c6/src/interrupt_core0/zb_mac_intr_map.rs
+++ b/esp32c6/src/interrupt_core0/zb_mac_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ZB_MAC_INTR_MAP")
-            .field(
-                "zb_mac_intr_map",
-                &format_args!("{}", self.zb_mac_intr_map().bits()),
-            )
+            .field("zb_mac_intr_map", &self.zb_mac_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ZB_MAC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/intpri/clock_gate.rs b/esp32c6/src/intpri/clock_gate.rs
index 8f6f21be25..b4f346377e 100644
--- a/esp32c6/src/intpri/clock_gate.rs
+++ b/esp32c6/src/intpri/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/intpri/cpu_int_clear.rs b/esp32c6/src/intpri/cpu_int_clear.rs
index b9912b3374..cbc49231c0 100644
--- a/esp32c6/src/intpri/cpu_int_clear.rs
+++ b/esp32c6/src/intpri/cpu_int_clear.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_CLEAR")
-            .field(
-                "cpu_int_clear",
-                &format_args!("{}", self.cpu_int_clear().bits()),
-            )
+            .field("cpu_int_clear", &self.cpu_int_clear())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_CLEAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/intpri/cpu_int_eip_status.rs b/esp32c6/src/intpri/cpu_int_eip_status.rs
index b7ee1aaed5..1f188e92e8 100644
--- a/esp32c6/src/intpri/cpu_int_eip_status.rs
+++ b/esp32c6/src/intpri/cpu_int_eip_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_EIP_STATUS")
-            .field(
-                "cpu_int_eip_status",
-                &format_args!("{}", self.cpu_int_eip_status().bits()),
-            )
+            .field("cpu_int_eip_status", &self.cpu_int_eip_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_EIP_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_eip_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPU_INT_EIP_STATUS_SPEC;
 impl crate::RegisterSpec for CPU_INT_EIP_STATUS_SPEC {
diff --git a/esp32c6/src/intpri/cpu_int_enable.rs b/esp32c6/src/intpri/cpu_int_enable.rs
index f25a329e68..64ed8c3e2c 100644
--- a/esp32c6/src/intpri/cpu_int_enable.rs
+++ b/esp32c6/src/intpri/cpu_int_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_ENABLE")
-            .field(
-                "cpu_int_enable",
-                &format_args!("{}", self.cpu_int_enable().bits()),
-            )
+            .field("cpu_int_enable", &self.cpu_int_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/intpri/cpu_int_pri.rs b/esp32c6/src/intpri/cpu_int_pri.rs
index 1554f14e1a..cb451abfa9 100644
--- a/esp32c6/src/intpri/cpu_int_pri.rs
+++ b/esp32c6/src/intpri/cpu_int_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_PRI")
-            .field("map", &format_args!("{}", self.map().bits()))
+            .field("map", &self.map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/intpri/cpu_int_thresh.rs b/esp32c6/src/intpri/cpu_int_thresh.rs
index 9c6bba61ca..8cf1416d50 100644
--- a/esp32c6/src/intpri/cpu_int_thresh.rs
+++ b/esp32c6/src/intpri/cpu_int_thresh.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_THRESH")
-            .field(
-                "cpu_int_thresh",
-                &format_args!("{}", self.cpu_int_thresh().bits()),
-            )
+            .field("cpu_int_thresh", &self.cpu_int_thresh())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_THRESH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/intpri/cpu_int_type.rs b/esp32c6/src/intpri/cpu_int_type.rs
index 7582423a54..89be1b6343 100644
--- a/esp32c6/src/intpri/cpu_int_type.rs
+++ b/esp32c6/src/intpri/cpu_int_type.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_TYPE")
-            .field(
-                "cpu_int_type",
-                &format_args!("{}", self.cpu_int_type().bits()),
-            )
+            .field("cpu_int_type", &self.cpu_int_type())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_TYPE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/intpri/cpu_intr_from_cpu_0.rs b/esp32c6/src/intpri/cpu_intr_from_cpu_0.rs
index 36e224d1dd..773faf6f48 100644
--- a/esp32c6/src/intpri/cpu_intr_from_cpu_0.rs
+++ b/esp32c6/src/intpri/cpu_intr_from_cpu_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_0")
-            .field(
-                "cpu_intr_from_cpu_0",
-                &format_args!("{}", self.cpu_intr_from_cpu_0().bit()),
-            )
+            .field("cpu_intr_from_cpu_0", &self.cpu_intr_from_cpu_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/intpri/cpu_intr_from_cpu_1.rs b/esp32c6/src/intpri/cpu_intr_from_cpu_1.rs
index 673f836671..be1befc8e4 100644
--- a/esp32c6/src/intpri/cpu_intr_from_cpu_1.rs
+++ b/esp32c6/src/intpri/cpu_intr_from_cpu_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_1")
-            .field(
-                "cpu_intr_from_cpu_1",
-                &format_args!("{}", self.cpu_intr_from_cpu_1().bit()),
-            )
+            .field("cpu_intr_from_cpu_1", &self.cpu_intr_from_cpu_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/intpri/cpu_intr_from_cpu_2.rs b/esp32c6/src/intpri/cpu_intr_from_cpu_2.rs
index 59fc42668c..da0b42a361 100644
--- a/esp32c6/src/intpri/cpu_intr_from_cpu_2.rs
+++ b/esp32c6/src/intpri/cpu_intr_from_cpu_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_2")
-            .field(
-                "cpu_intr_from_cpu_2",
-                &format_args!("{}", self.cpu_intr_from_cpu_2().bit()),
-            )
+            .field("cpu_intr_from_cpu_2", &self.cpu_intr_from_cpu_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/intpri/cpu_intr_from_cpu_3.rs b/esp32c6/src/intpri/cpu_intr_from_cpu_3.rs
index 966685ec1f..842300cffb 100644
--- a/esp32c6/src/intpri/cpu_intr_from_cpu_3.rs
+++ b/esp32c6/src/intpri/cpu_intr_from_cpu_3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_3")
-            .field(
-                "cpu_intr_from_cpu_3",
-                &format_args!("{}", self.cpu_intr_from_cpu_3().bit()),
-            )
+            .field("cpu_intr_from_cpu_3", &self.cpu_intr_from_cpu_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32c6/src/intpri/date.rs b/esp32c6/src/intpri/date.rs
index 4e7cad74b8..8693e9ea9f 100644
--- a/esp32c6/src/intpri/date.rs
+++ b/esp32c6/src/intpri/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/intpri/rnd_eco.rs b/esp32c6/src/intpri/rnd_eco.rs
index cf663fec03..3163d9f0b8 100644
--- a/esp32c6/src/intpri/rnd_eco.rs
+++ b/esp32c6/src/intpri/rnd_eco.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO")
-            .field("redcy_ena", &format_args!("{}", self.redcy_ena().bit()))
-            .field(
-                "redcy_result",
-                &format_args!("{}", self.redcy_result().bit()),
-            )
+            .field("redcy_ena", &self.redcy_ena())
+            .field("redcy_result", &self.redcy_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Only reserved for ECO."]
     #[inline(always)]
diff --git a/esp32c6/src/intpri/rnd_eco_high.rs b/esp32c6/src/intpri/rnd_eco_high.rs
index d2138667f2..acb852af6d 100644
--- a/esp32c6/src/intpri/rnd_eco_high.rs
+++ b/esp32c6/src/intpri/rnd_eco_high.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_HIGH")
-            .field("redcy_high", &format_args!("{}", self.redcy_high().bits()))
+            .field("redcy_high", &self.redcy_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Only reserved for ECO."]
     #[inline(always)]
diff --git a/esp32c6/src/intpri/rnd_eco_low.rs b/esp32c6/src/intpri/rnd_eco_low.rs
index 6accf663f9..f3dcb2ff4b 100644
--- a/esp32c6/src/intpri/rnd_eco_low.rs
+++ b/esp32c6/src/intpri/rnd_eco_low.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_LOW")
-            .field("redcy_low", &format_args!("{}", self.redcy_low().bits()))
+            .field("redcy_low", &self.redcy_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Only reserved for ECO."]
     #[inline(always)]
diff --git a/esp32c6/src/io_mux/date.rs b/esp32c6/src/io_mux/date.rs
index e1a8837f18..d29afced03 100644
--- a/esp32c6/src/io_mux/date.rs
+++ b/esp32c6/src/io_mux/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("reg_date", &format_args!("{}", self.reg_date().bits()))
+            .field("reg_date", &self.reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
diff --git a/esp32c6/src/io_mux/gpio.rs b/esp32c6/src/io_mux/gpio.rs
index 922d4b4be7..cc5477b4e5 100644
--- a/esp32c6/src/io_mux/gpio.rs
+++ b/esp32c6/src/io_mux/gpio.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled."]
     #[inline(always)]
diff --git a/esp32c6/src/io_mux/modem_diag_en.rs b/esp32c6/src/io_mux/modem_diag_en.rs
index 0b9e880bc8..55347e4b1b 100644
--- a/esp32c6/src/io_mux/modem_diag_en.rs
+++ b/esp32c6/src/io_mux/modem_diag_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODEM_DIAG_EN")
-            .field(
-                "modem_diag_en",
-                &format_args!("{}", self.modem_diag_en().bits()),
-            )
+            .field("modem_diag_en", &self.modem_diag_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODEM_DIAG_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - bit i to enable modem_diag\\[i\\] into gpio matrix. 1:enable modem_diag\\[i\\] into gpio matrix. 0:enable other signals into gpio matrix"]
     #[inline(always)]
diff --git a/esp32c6/src/io_mux/pin_ctrl.rs b/esp32c6/src/io_mux/pin_ctrl.rs
index 0d00e79f0f..d53c6ba7f6 100644
--- a/esp32c6/src/io_mux/pin_ctrl.rs
+++ b/esp32c6/src/io_mux/pin_ctrl.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN_CTRL")
-            .field("clk_out1", &format_args!("{}", self.clk_out1().bits()))
-            .field("clk_out2", &format_args!("{}", self.clk_out2().bits()))
-            .field("clk_out3", &format_args!("{}", self.clk_out3().bits()))
+            .field("clk_out1", &self.clk_out1())
+            .field("clk_out2", &self.clk_out2())
+            .field("clk_out3", &self.clk_out3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals."]
     #[inline(always)]
diff --git a/esp32c6/src/ledc/ch/conf0.rs b/esp32c6/src/ledc/ch/conf0.rs
index 75e709aeae..3e3620eb0f 100644
--- a/esp32c6/src/ledc/ch/conf0.rs
+++ b/esp32c6/src/ledc/ch/conf0.rs
@@ -57,20 +57,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("timer_sel", &format_args!("{}", self.timer_sel().bits()))
-            .field("sig_out_en", &format_args!("{}", self.sig_out_en().bit()))
-            .field("idle_lv", &format_args!("{}", self.idle_lv().bit()))
-            .field("ovf_num", &format_args!("{}", self.ovf_num().bits()))
-            .field("ovf_cnt_en", &format_args!("{}", self.ovf_cnt_en().bit()))
+            .field("timer_sel", &self.timer_sel())
+            .field("sig_out_en", &self.sig_out_en())
+            .field("idle_lv", &self.idle_lv())
+            .field("ovf_num", &self.ovf_num())
+            .field("ovf_cnt_en", &self.ovf_cnt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to select one of timers for channel %s. 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3"]
     #[inline(always)]
diff --git a/esp32c6/src/ledc/ch/conf1.rs b/esp32c6/src/ledc/ch/conf1.rs
index 7d7c11116b..51ebd704af 100644
--- a/esp32c6/src/ledc/ch/conf1.rs
+++ b/esp32c6/src/ledc/ch/conf1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field("duty_start", &format_args!("{}", self.duty_start().bit()))
+            .field("duty_start", &self.duty_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1."]
     #[inline(always)]
diff --git a/esp32c6/src/ledc/ch/duty.rs b/esp32c6/src/ledc/ch/duty.rs
index 4c7bf4a186..7494af0c54 100644
--- a/esp32c6/src/ledc/ch/duty.rs
+++ b/esp32c6/src/ledc/ch/duty.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DUTY")
-            .field("duty", &format_args!("{}", self.duty().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DUTY").field("duty", &self.duty()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/ledc/ch/duty_r.rs b/esp32c6/src/ledc/ch/duty_r.rs
index f14b8a4d90..a3b6ad8523 100644
--- a/esp32c6/src/ledc/ch/duty_r.rs
+++ b/esp32c6/src/ledc/ch/duty_r.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DUTY_R")
-            .field("duty_r", &format_args!("{}", self.duty_r().bits()))
+            .field("duty_r", &self.duty_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_R_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current duty cycle for channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`duty_r::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DUTY_R_SPEC;
 impl crate::RegisterSpec for DUTY_R_SPEC {
diff --git a/esp32c6/src/ledc/ch/hpoint.rs b/esp32c6/src/ledc/ch/hpoint.rs
index 5167d38a55..f98ee1970f 100644
--- a/esp32c6/src/ledc/ch/hpoint.rs
+++ b/esp32c6/src/ledc/ch/hpoint.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPOINT")
-            .field("hpoint", &format_args!("{}", self.hpoint().bits()))
+            .field("hpoint", &self.hpoint())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPOINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - The output value changes to high when the selected timers has reached the value specified by this register."]
     #[inline(always)]
diff --git a/esp32c6/src/ledc/ch_gamma_conf.rs b/esp32c6/src/ledc/ch_gamma_conf.rs
index 6af9564680..28251b1fe6 100644
--- a/esp32c6/src/ledc/ch_gamma_conf.rs
+++ b/esp32c6/src/ledc/ch_gamma_conf.rs
@@ -21,19 +21,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_GAMMA_CONF")
-            .field(
-                "ch_gamma_entry_num",
-                &format_args!("{}", self.ch_gamma_entry_num().bits()),
-            )
+            .field("ch_gamma_entry_num", &self.ch_gamma_entry_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_GAMMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Ledc ch%s gamma entry num."]
     #[inline(always)]
diff --git a/esp32c6/src/ledc/ch_gamma_rd_addr.rs b/esp32c6/src/ledc/ch_gamma_rd_addr.rs
index 22800ad736..62a261fc9e 100644
--- a/esp32c6/src/ledc/ch_gamma_rd_addr.rs
+++ b/esp32c6/src/ledc/ch_gamma_rd_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_GAMMA_RD_ADDR")
-            .field(
-                "ch_gamma_rd_addr",
-                &format_args!("{}", self.ch_gamma_rd_addr().bits()),
-            )
+            .field("ch_gamma_rd_addr", &self.ch_gamma_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_GAMMA_RD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Ledc ch%s gamma ram read address."]
     #[inline(always)]
diff --git a/esp32c6/src/ledc/ch_gamma_rd_data.rs b/esp32c6/src/ledc/ch_gamma_rd_data.rs
index 4ec4d1e45e..b6bb1301ff 100644
--- a/esp32c6/src/ledc/ch_gamma_rd_data.rs
+++ b/esp32c6/src/ledc/ch_gamma_rd_data.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_GAMMA_RD_DATA")
-            .field(
-                "ch_gamma_rd_data",
-                &format_args!("{}", self.ch_gamma_rd_data().bits()),
-            )
+            .field("ch_gamma_rd_data", &self.ch_gamma_rd_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_GAMMA_RD_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Ledc ch%s gamma ram read data register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_gamma_rd_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_GAMMA_RD_DATA_SPEC;
 impl crate::RegisterSpec for CH_GAMMA_RD_DATA_SPEC {
diff --git a/esp32c6/src/ledc/ch_gamma_wr.rs b/esp32c6/src/ledc/ch_gamma_wr.rs
index 3446d2b56f..fb55130bd3 100644
--- a/esp32c6/src/ledc/ch_gamma_wr.rs
+++ b/esp32c6/src/ledc/ch_gamma_wr.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_GAMMA_WR")
-            .field(
-                "ch_gamma_duty_inc",
-                &format_args!("{}", self.ch_gamma_duty_inc().bit()),
-            )
-            .field(
-                "ch_gamma_duty_cycle",
-                &format_args!("{}", self.ch_gamma_duty_cycle().bits()),
-            )
-            .field(
-                "ch_gamma_scale",
-                &format_args!("{}", self.ch_gamma_scale().bits()),
-            )
-            .field(
-                "ch_gamma_duty_num",
-                &format_args!("{}", self.ch_gamma_duty_num().bits()),
-            )
+            .field("ch_gamma_duty_inc", &self.ch_gamma_duty_inc())
+            .field("ch_gamma_duty_cycle", &self.ch_gamma_duty_cycle())
+            .field("ch_gamma_scale", &self.ch_gamma_scale())
+            .field("ch_gamma_duty_num", &self.ch_gamma_duty_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_GAMMA_WR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Ledc ch%s gamma duty inc of current ram write address.This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase 0: Decrease."]
     #[inline(always)]
diff --git a/esp32c6/src/ledc/ch_gamma_wr_addr.rs b/esp32c6/src/ledc/ch_gamma_wr_addr.rs
index a339036095..8a8141e060 100644
--- a/esp32c6/src/ledc/ch_gamma_wr_addr.rs
+++ b/esp32c6/src/ledc/ch_gamma_wr_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_GAMMA_WR_ADDR")
-            .field(
-                "ch_gamma_wr_addr",
-                &format_args!("{}", self.ch_gamma_wr_addr().bits()),
-            )
+            .field("ch_gamma_wr_addr", &self.ch_gamma_wr_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_GAMMA_WR_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Ledc ch%s gamma ram write address."]
     #[inline(always)]
diff --git a/esp32c6/src/ledc/conf.rs b/esp32c6/src/ledc/conf.rs
index 456a31a619..89cc715a69 100644
--- a/esp32c6/src/ledc/conf.rs
+++ b/esp32c6/src/ledc/conf.rs
@@ -80,44 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field(
-                "apb_clk_sel",
-                &format_args!("{}", self.apb_clk_sel().bits()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch0",
-                &format_args!("{}", self.gamma_ram_clk_en_ch0().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch1",
-                &format_args!("{}", self.gamma_ram_clk_en_ch1().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch2",
-                &format_args!("{}", self.gamma_ram_clk_en_ch2().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch3",
-                &format_args!("{}", self.gamma_ram_clk_en_ch3().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch4",
-                &format_args!("{}", self.gamma_ram_clk_en_ch4().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch5",
-                &format_args!("{}", self.gamma_ram_clk_en_ch5().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("apb_clk_sel", &self.apb_clk_sel())
+            .field("gamma_ram_clk_en_ch0", &self.gamma_ram_clk_en_ch0())
+            .field("gamma_ram_clk_en_ch1", &self.gamma_ram_clk_en_ch1())
+            .field("gamma_ram_clk_en_ch2", &self.gamma_ram_clk_en_ch2())
+            .field("gamma_ram_clk_en_ch3", &self.gamma_ram_clk_en_ch3())
+            .field("gamma_ram_clk_en_ch4", &self.gamma_ram_clk_en_ch4())
+            .field("gamma_ram_clk_en_ch5", &self.gamma_ram_clk_en_ch5())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This bit is used to select clock source for the 4 timers . 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK"]
     #[inline(always)]
diff --git a/esp32c6/src/ledc/date.rs b/esp32c6/src/ledc/date.rs
index 30a5b4ffff..de5a7a8661 100644
--- a/esp32c6/src/ledc/date.rs
+++ b/esp32c6/src/ledc/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("ledc_date", &format_args!("{}", self.ledc_date().bits()))
+            .field("ledc_date", &self.ledc_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - This is the version control register."]
     #[inline(always)]
diff --git a/esp32c6/src/ledc/evt_task_en0.rs b/esp32c6/src/ledc/evt_task_en0.rs
index efc0e38bd2..ef7bef4a44 100644
--- a/esp32c6/src/ledc/evt_task_en0.rs
+++ b/esp32c6/src/ledc/evt_task_en0.rs
@@ -242,119 +242,53 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVT_TASK_EN0")
-            .field(
-                "evt_duty_chng_end_ch0_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch0_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch1_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch1_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch2_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch2_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch3_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch3_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch4_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch4_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch5_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch5_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch0_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch0_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch1_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch1_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch2_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch2_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch3_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch3_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch4_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch4_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch5_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch5_en().bit()),
-            )
-            .field(
-                "evt_time_ovf_timer0_en",
-                &format_args!("{}", self.evt_time_ovf_timer0_en().bit()),
-            )
-            .field(
-                "evt_time_ovf_timer1_en",
-                &format_args!("{}", self.evt_time_ovf_timer1_en().bit()),
-            )
-            .field(
-                "evt_time_ovf_timer2_en",
-                &format_args!("{}", self.evt_time_ovf_timer2_en().bit()),
-            )
-            .field(
-                "evt_time_ovf_timer3_en",
-                &format_args!("{}", self.evt_time_ovf_timer3_en().bit()),
-            )
-            .field(
-                "evt_time0_cmp_en",
-                &format_args!("{}", self.evt_time0_cmp_en().bit()),
-            )
-            .field(
-                "evt_time1_cmp_en",
-                &format_args!("{}", self.evt_time1_cmp_en().bit()),
-            )
-            .field(
-                "evt_time2_cmp_en",
-                &format_args!("{}", self.evt_time2_cmp_en().bit()),
-            )
-            .field(
-                "evt_time3_cmp_en",
-                &format_args!("{}", self.evt_time3_cmp_en().bit()),
-            )
+            .field("evt_duty_chng_end_ch0_en", &self.evt_duty_chng_end_ch0_en())
+            .field("evt_duty_chng_end_ch1_en", &self.evt_duty_chng_end_ch1_en())
+            .field("evt_duty_chng_end_ch2_en", &self.evt_duty_chng_end_ch2_en())
+            .field("evt_duty_chng_end_ch3_en", &self.evt_duty_chng_end_ch3_en())
+            .field("evt_duty_chng_end_ch4_en", &self.evt_duty_chng_end_ch4_en())
+            .field("evt_duty_chng_end_ch5_en", &self.evt_duty_chng_end_ch5_en())
+            .field("evt_ovf_cnt_pls_ch0_en", &self.evt_ovf_cnt_pls_ch0_en())
+            .field("evt_ovf_cnt_pls_ch1_en", &self.evt_ovf_cnt_pls_ch1_en())
+            .field("evt_ovf_cnt_pls_ch2_en", &self.evt_ovf_cnt_pls_ch2_en())
+            .field("evt_ovf_cnt_pls_ch3_en", &self.evt_ovf_cnt_pls_ch3_en())
+            .field("evt_ovf_cnt_pls_ch4_en", &self.evt_ovf_cnt_pls_ch4_en())
+            .field("evt_ovf_cnt_pls_ch5_en", &self.evt_ovf_cnt_pls_ch5_en())
+            .field("evt_time_ovf_timer0_en", &self.evt_time_ovf_timer0_en())
+            .field("evt_time_ovf_timer1_en", &self.evt_time_ovf_timer1_en())
+            .field("evt_time_ovf_timer2_en", &self.evt_time_ovf_timer2_en())
+            .field("evt_time_ovf_timer3_en", &self.evt_time_ovf_timer3_en())
+            .field("evt_time0_cmp_en", &self.evt_time0_cmp_en())
+            .field("evt_time1_cmp_en", &self.evt_time1_cmp_en())
+            .field("evt_time2_cmp_en", &self.evt_time2_cmp_en())
+            .field("evt_time3_cmp_en", &self.evt_time3_cmp_en())
             .field(
                 "task_duty_scale_update_ch0_en",
-                &format_args!("{}", self.task_duty_scale_update_ch0_en().bit()),
+                &self.task_duty_scale_update_ch0_en(),
             )
             .field(
                 "task_duty_scale_update_ch1_en",
-                &format_args!("{}", self.task_duty_scale_update_ch1_en().bit()),
+                &self.task_duty_scale_update_ch1_en(),
             )
             .field(
                 "task_duty_scale_update_ch2_en",
-                &format_args!("{}", self.task_duty_scale_update_ch2_en().bit()),
+                &self.task_duty_scale_update_ch2_en(),
             )
             .field(
                 "task_duty_scale_update_ch3_en",
-                &format_args!("{}", self.task_duty_scale_update_ch3_en().bit()),
+                &self.task_duty_scale_update_ch3_en(),
             )
             .field(
                 "task_duty_scale_update_ch4_en",
-                &format_args!("{}", self.task_duty_scale_update_ch4_en().bit()),
+                &self.task_duty_scale_update_ch4_en(),
             )
             .field(
                 "task_duty_scale_update_ch5_en",
-                &format_args!("{}", self.task_duty_scale_update_ch5_en().bit()),
+                &self.task_duty_scale_update_ch5_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_TASK_EN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Ledc ch0 duty change end event enable register, write 1 to enable this event."]
     #[inline(always)]
diff --git a/esp32c6/src/ledc/evt_task_en1.rs b/esp32c6/src/ledc/evt_task_en1.rs
index c280c82c92..38b6535dd6 100644
--- a/esp32c6/src/ledc/evt_task_en1.rs
+++ b/esp32c6/src/ledc/evt_task_en1.rs
@@ -262,125 +262,59 @@ impl core::fmt::Debug for R {
         f.debug_struct("EVT_TASK_EN1")
             .field(
                 "task_timer0_res_update_en",
-                &format_args!("{}", self.task_timer0_res_update_en().bit()),
+                &self.task_timer0_res_update_en(),
             )
             .field(
                 "task_timer1_res_update_en",
-                &format_args!("{}", self.task_timer1_res_update_en().bit()),
+                &self.task_timer1_res_update_en(),
             )
             .field(
                 "task_timer2_res_update_en",
-                &format_args!("{}", self.task_timer2_res_update_en().bit()),
+                &self.task_timer2_res_update_en(),
             )
             .field(
                 "task_timer3_res_update_en",
-                &format_args!("{}", self.task_timer3_res_update_en().bit()),
-            )
-            .field(
-                "task_timer0_cap_en",
-                &format_args!("{}", self.task_timer0_cap_en().bit()),
-            )
-            .field(
-                "task_timer1_cap_en",
-                &format_args!("{}", self.task_timer1_cap_en().bit()),
-            )
-            .field(
-                "task_timer2_cap_en",
-                &format_args!("{}", self.task_timer2_cap_en().bit()),
-            )
-            .field(
-                "task_timer3_cap_en",
-                &format_args!("{}", self.task_timer3_cap_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch0_en",
-                &format_args!("{}", self.task_sig_out_dis_ch0_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch1_en",
-                &format_args!("{}", self.task_sig_out_dis_ch1_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch2_en",
-                &format_args!("{}", self.task_sig_out_dis_ch2_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch3_en",
-                &format_args!("{}", self.task_sig_out_dis_ch3_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch4_en",
-                &format_args!("{}", self.task_sig_out_dis_ch4_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch5_en",
-                &format_args!("{}", self.task_sig_out_dis_ch5_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch0_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch0_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch1_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch1_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch2_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch2_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch3_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch3_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch4_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch4_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch5_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch5_en().bit()),
-            )
-            .field(
-                "task_timer0_rst_en",
-                &format_args!("{}", self.task_timer0_rst_en().bit()),
-            )
-            .field(
-                "task_timer1_rst_en",
-                &format_args!("{}", self.task_timer1_rst_en().bit()),
-            )
-            .field(
-                "task_timer2_rst_en",
-                &format_args!("{}", self.task_timer2_rst_en().bit()),
-            )
-            .field(
-                "task_timer3_rst_en",
-                &format_args!("{}", self.task_timer3_rst_en().bit()),
+                &self.task_timer3_res_update_en(),
             )
+            .field("task_timer0_cap_en", &self.task_timer0_cap_en())
+            .field("task_timer1_cap_en", &self.task_timer1_cap_en())
+            .field("task_timer2_cap_en", &self.task_timer2_cap_en())
+            .field("task_timer3_cap_en", &self.task_timer3_cap_en())
+            .field("task_sig_out_dis_ch0_en", &self.task_sig_out_dis_ch0_en())
+            .field("task_sig_out_dis_ch1_en", &self.task_sig_out_dis_ch1_en())
+            .field("task_sig_out_dis_ch2_en", &self.task_sig_out_dis_ch2_en())
+            .field("task_sig_out_dis_ch3_en", &self.task_sig_out_dis_ch3_en())
+            .field("task_sig_out_dis_ch4_en", &self.task_sig_out_dis_ch4_en())
+            .field("task_sig_out_dis_ch5_en", &self.task_sig_out_dis_ch5_en())
+            .field("task_ovf_cnt_rst_ch0_en", &self.task_ovf_cnt_rst_ch0_en())
+            .field("task_ovf_cnt_rst_ch1_en", &self.task_ovf_cnt_rst_ch1_en())
+            .field("task_ovf_cnt_rst_ch2_en", &self.task_ovf_cnt_rst_ch2_en())
+            .field("task_ovf_cnt_rst_ch3_en", &self.task_ovf_cnt_rst_ch3_en())
+            .field("task_ovf_cnt_rst_ch4_en", &self.task_ovf_cnt_rst_ch4_en())
+            .field("task_ovf_cnt_rst_ch5_en", &self.task_ovf_cnt_rst_ch5_en())
+            .field("task_timer0_rst_en", &self.task_timer0_rst_en())
+            .field("task_timer1_rst_en", &self.task_timer1_rst_en())
+            .field("task_timer2_rst_en", &self.task_timer2_rst_en())
+            .field("task_timer3_rst_en", &self.task_timer3_rst_en())
             .field(
                 "task_timer0_pause_resume_en",
-                &format_args!("{}", self.task_timer0_pause_resume_en().bit()),
+                &self.task_timer0_pause_resume_en(),
             )
             .field(
                 "task_timer1_pause_resume_en",
-                &format_args!("{}", self.task_timer1_pause_resume_en().bit()),
+                &self.task_timer1_pause_resume_en(),
             )
             .field(
                 "task_timer2_pause_resume_en",
-                &format_args!("{}", self.task_timer2_pause_resume_en().bit()),
+                &self.task_timer2_pause_resume_en(),
             )
             .field(
                 "task_timer3_pause_resume_en",
-                &format_args!("{}", self.task_timer3_pause_resume_en().bit()),
+                &self.task_timer3_pause_resume_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_TASK_EN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Ledc timer0 res update task enable register, write 1 to enable this task."]
     #[inline(always)]
diff --git a/esp32c6/src/ledc/evt_task_en2.rs b/esp32c6/src/ledc/evt_task_en2.rs
index 854ef2967f..0d920579b4 100644
--- a/esp32c6/src/ledc/evt_task_en2.rs
+++ b/esp32c6/src/ledc/evt_task_en2.rs
@@ -172,85 +172,43 @@ impl core::fmt::Debug for R {
         f.debug_struct("EVT_TASK_EN2")
             .field(
                 "task_gamma_restart_ch0_en",
-                &format_args!("{}", self.task_gamma_restart_ch0_en().bit()),
+                &self.task_gamma_restart_ch0_en(),
             )
             .field(
                 "task_gamma_restart_ch1_en",
-                &format_args!("{}", self.task_gamma_restart_ch1_en().bit()),
+                &self.task_gamma_restart_ch1_en(),
             )
             .field(
                 "task_gamma_restart_ch2_en",
-                &format_args!("{}", self.task_gamma_restart_ch2_en().bit()),
+                &self.task_gamma_restart_ch2_en(),
             )
             .field(
                 "task_gamma_restart_ch3_en",
-                &format_args!("{}", self.task_gamma_restart_ch3_en().bit()),
+                &self.task_gamma_restart_ch3_en(),
             )
             .field(
                 "task_gamma_restart_ch4_en",
-                &format_args!("{}", self.task_gamma_restart_ch4_en().bit()),
+                &self.task_gamma_restart_ch4_en(),
             )
             .field(
                 "task_gamma_restart_ch5_en",
-                &format_args!("{}", self.task_gamma_restart_ch5_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch0_en",
-                &format_args!("{}", self.task_gamma_pause_ch0_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch1_en",
-                &format_args!("{}", self.task_gamma_pause_ch1_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch2_en",
-                &format_args!("{}", self.task_gamma_pause_ch2_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch3_en",
-                &format_args!("{}", self.task_gamma_pause_ch3_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch4_en",
-                &format_args!("{}", self.task_gamma_pause_ch4_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch5_en",
-                &format_args!("{}", self.task_gamma_pause_ch5_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch0_en",
-                &format_args!("{}", self.task_gamma_resume_ch0_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch1_en",
-                &format_args!("{}", self.task_gamma_resume_ch1_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch2_en",
-                &format_args!("{}", self.task_gamma_resume_ch2_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch3_en",
-                &format_args!("{}", self.task_gamma_resume_ch3_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch4_en",
-                &format_args!("{}", self.task_gamma_resume_ch4_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch5_en",
-                &format_args!("{}", self.task_gamma_resume_ch5_en().bit()),
+                &self.task_gamma_restart_ch5_en(),
             )
+            .field("task_gamma_pause_ch0_en", &self.task_gamma_pause_ch0_en())
+            .field("task_gamma_pause_ch1_en", &self.task_gamma_pause_ch1_en())
+            .field("task_gamma_pause_ch2_en", &self.task_gamma_pause_ch2_en())
+            .field("task_gamma_pause_ch3_en", &self.task_gamma_pause_ch3_en())
+            .field("task_gamma_pause_ch4_en", &self.task_gamma_pause_ch4_en())
+            .field("task_gamma_pause_ch5_en", &self.task_gamma_pause_ch5_en())
+            .field("task_gamma_resume_ch0_en", &self.task_gamma_resume_ch0_en())
+            .field("task_gamma_resume_ch1_en", &self.task_gamma_resume_ch1_en())
+            .field("task_gamma_resume_ch2_en", &self.task_gamma_resume_ch2_en())
+            .field("task_gamma_resume_ch3_en", &self.task_gamma_resume_ch3_en())
+            .field("task_gamma_resume_ch4_en", &self.task_gamma_resume_ch4_en())
+            .field("task_gamma_resume_ch5_en", &self.task_gamma_resume_ch5_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_TASK_EN2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Ledc ch0 gamma restart task enable register, write 1 to enable this task."]
     #[inline(always)]
diff --git a/esp32c6/src/ledc/int_ena.rs b/esp32c6/src/ledc/int_ena.rs
index b9a4a96b44..faa3849af3 100644
--- a/esp32c6/src/ledc/int_ena.rs
+++ b/esp32c6/src/ledc/int_ena.rs
@@ -145,49 +145,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the TIMER(0-3)_OVF interrupt."]
     #[doc = ""]
diff --git a/esp32c6/src/ledc/int_raw.rs b/esp32c6/src/ledc/int_raw.rs
index 5268b7ffc5..ef2455717c 100644
--- a/esp32c6/src/ledc/int_raw.rs
+++ b/esp32c6/src/ledc/int_raw.rs
@@ -145,49 +145,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Triggered when the timer(0-3) has reached its maximum counter value."]
     #[doc = ""]
diff --git a/esp32c6/src/ledc/int_st.rs b/esp32c6/src/ledc/int_st.rs
index 32fc7886ec..61b6043bab 100644
--- a/esp32c6/src/ledc/int_st.rs
+++ b/esp32c6/src/ledc/int_st.rs
@@ -137,49 +137,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/ledc/timer/conf.rs b/esp32c6/src/ledc/timer/conf.rs
index 65e571f33d..0b29b0dbf4 100644
--- a/esp32c6/src/ledc/timer/conf.rs
+++ b/esp32c6/src/ledc/timer/conf.rs
@@ -55,20 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("duty_res", &format_args!("{}", self.duty_res().bits()))
-            .field("clk_div", &format_args!("{}", self.clk_div().bits()))
-            .field("pause", &format_args!("{}", self.pause().bit()))
-            .field("rst", &format_args!("{}", self.rst().bit()))
-            .field("tick_sel", &format_args!("{}", self.tick_sel().bit()))
+            .field("duty_res", &self.duty_res())
+            .field("clk_div", &self.clk_div())
+            .field("pause", &self.pause())
+            .field("rst", &self.rst())
+            .field("tick_sel", &self.tick_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to control the range of the counter in timer %s."]
     #[inline(always)]
diff --git a/esp32c6/src/ledc/timer/value.rs b/esp32c6/src/ledc/timer/value.rs
index 0a29a10a74..b694c379b1 100644
--- a/esp32c6/src/ledc/timer/value.rs
+++ b/esp32c6/src/ledc/timer/value.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("VALUE")
-            .field("cnt", &format_args!("{}", self.cnt().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("VALUE").field("cnt", &self.cnt()).finish()
     }
 }
 #[doc = "Timer 0 current counter value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c6/src/ledc/timer_cmp.rs b/esp32c6/src/ledc/timer_cmp.rs
index adffb5f9a9..ebcea1539c 100644
--- a/esp32c6/src/ledc/timer_cmp.rs
+++ b/esp32c6/src/ledc/timer_cmp.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_CMP")
-            .field("timer_cmp", &format_args!("{}", self.timer_cmp().bits()))
+            .field("timer_cmp", &self.timer_cmp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_CMP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register stores ledc timer%s compare value."]
     #[inline(always)]
diff --git a/esp32c6/src/ledc/timer_cnt_cap.rs b/esp32c6/src/ledc/timer_cnt_cap.rs
index 1554e17d25..225284dd8c 100644
--- a/esp32c6/src/ledc/timer_cnt_cap.rs
+++ b/esp32c6/src/ledc/timer_cnt_cap.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_CNT_CAP")
-            .field(
-                "timer_cnt_cap",
-                &format_args!("{}", self.timer_cnt_cap().bits()),
-            )
+            .field("timer_cnt_cap", &self.timer_cnt_cap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_CNT_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Ledc timer%s count value capture register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_cnt_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMER_CNT_CAP_SPEC;
 impl crate::RegisterSpec for TIMER_CNT_CAP_SPEC {
diff --git a/esp32c6/src/lib.rs b/esp32c6/src/lib.rs
index fe96f36c7a..63e62cdb88 100644
--- a/esp32c6/src/lib.rs
+++ b/esp32c6/src/lib.rs
@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32-C6 microcontrollers (generated using svd2rust v0.33.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32-C6 microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
diff --git a/esp32c6/src/lp_ana/bod_mode0_cntl.rs b/esp32c6/src/lp_ana/bod_mode0_cntl.rs
index 4eae1d17a9..51c9ae872d 100644
--- a/esp32c6/src/lp_ana/bod_mode0_cntl.rs
+++ b/esp32c6/src/lp_ana/bod_mode0_cntl.rs
@@ -82,45 +82,18 @@ impl core::fmt::Debug for R {
         f.debug_struct("BOD_MODE0_CNTL")
             .field(
                 "bod_mode0_close_flash_ena",
-                &format_args!("{}", self.bod_mode0_close_flash_ena().bit()),
-            )
-            .field(
-                "bod_mode0_pd_rf_ena",
-                &format_args!("{}", self.bod_mode0_pd_rf_ena().bit()),
-            )
-            .field(
-                "bod_mode0_intr_wait",
-                &format_args!("{}", self.bod_mode0_intr_wait().bits()),
-            )
-            .field(
-                "bod_mode0_reset_wait",
-                &format_args!("{}", self.bod_mode0_reset_wait().bits()),
-            )
-            .field(
-                "bod_mode0_cnt_clr",
-                &format_args!("{}", self.bod_mode0_cnt_clr().bit()),
-            )
-            .field(
-                "bod_mode0_intr_ena",
-                &format_args!("{}", self.bod_mode0_intr_ena().bit()),
-            )
-            .field(
-                "bod_mode0_reset_sel",
-                &format_args!("{}", self.bod_mode0_reset_sel().bit()),
-            )
-            .field(
-                "bod_mode0_reset_ena",
-                &format_args!("{}", self.bod_mode0_reset_ena().bit()),
+                &self.bod_mode0_close_flash_ena(),
             )
+            .field("bod_mode0_pd_rf_ena", &self.bod_mode0_pd_rf_ena())
+            .field("bod_mode0_intr_wait", &self.bod_mode0_intr_wait())
+            .field("bod_mode0_reset_wait", &self.bod_mode0_reset_wait())
+            .field("bod_mode0_cnt_clr", &self.bod_mode0_cnt_clr())
+            .field("bod_mode0_intr_ena", &self.bod_mode0_intr_ena())
+            .field("bod_mode0_reset_sel", &self.bod_mode0_reset_sel())
+            .field("bod_mode0_reset_ena", &self.bod_mode0_reset_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BOD_MODE0_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_ana/bod_mode1_cntl.rs b/esp32c6/src/lp_ana/bod_mode1_cntl.rs
index daab8a45d0..3aa7fe569f 100644
--- a/esp32c6/src/lp_ana/bod_mode1_cntl.rs
+++ b/esp32c6/src/lp_ana/bod_mode1_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BOD_MODE1_CNTL")
-            .field(
-                "bod_mode1_reset_ena",
-                &format_args!("{}", self.bod_mode1_reset_ena().bit()),
-            )
+            .field("bod_mode1_reset_ena", &self.bod_mode1_reset_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BOD_MODE1_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_ana/ck_glitch_cntl.rs b/esp32c6/src/lp_ana/ck_glitch_cntl.rs
index 603bbcf118..e33a2b6db7 100644
--- a/esp32c6/src/lp_ana/ck_glitch_cntl.rs
+++ b/esp32c6/src/lp_ana/ck_glitch_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CK_GLITCH_CNTL")
-            .field(
-                "ck_glitch_reset_ena",
-                &format_args!("{}", self.ck_glitch_reset_ena().bit()),
-            )
+            .field("ck_glitch_reset_ena", &self.ck_glitch_reset_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CK_GLITCH_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_ana/date.rs b/esp32c6/src/lp_ana/date.rs
index 019a29ebac..c7f4235d1c 100644
--- a/esp32c6/src/lp_ana/date.rs
+++ b/esp32c6/src/lp_ana/date.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "lp_ana_date",
-                &format_args!("{}", self.lp_ana_date().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("lp_ana_date", &self.lp_ana_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_ana/fib_enable.rs b/esp32c6/src/lp_ana/fib_enable.rs
index 4b991a5896..e6b9fbc95c 100644
--- a/esp32c6/src/lp_ana/fib_enable.rs
+++ b/esp32c6/src/lp_ana/fib_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIB_ENABLE")
-            .field(
-                "ana_fib_ena",
-                &format_args!("{}", self.ana_fib_ena().bits()),
-            )
+            .field("ana_fib_ena", &self.ana_fib_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIB_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_ana/int_ena.rs b/esp32c6/src/lp_ana/int_ena.rs
index 31a2ee44d7..35d587ca0d 100644
--- a/esp32c6/src/lp_ana/int_ena.rs
+++ b/esp32c6/src/lp_ana/int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_ana/int_raw.rs b/esp32c6/src/lp_ana/int_raw.rs
index e0d8bd0b0e..63d7c84adf 100644
--- a/esp32c6/src/lp_ana/int_raw.rs
+++ b/esp32c6/src/lp_ana/int_raw.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_ana/int_st.rs b/esp32c6/src/lp_ana/int_st.rs
index 9114ca074f..c214cea0ba 100644
--- a/esp32c6/src/lp_ana/int_st.rs
+++ b/esp32c6/src/lp_ana/int_st.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/lp_ana/lp_int_ena.rs b/esp32c6/src/lp_ana/lp_int_ena.rs
index 20c74f7372..044e93357d 100644
--- a/esp32c6/src/lp_ana/lp_int_ena.rs
+++ b/esp32c6/src/lp_ana/lp_int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ENA")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_ana/lp_int_raw.rs b/esp32c6/src/lp_ana/lp_int_raw.rs
index fcbabdea21..dde3b77a5d 100644
--- a/esp32c6/src/lp_ana/lp_int_raw.rs
+++ b/esp32c6/src/lp_ana/lp_int_raw.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_RAW")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_ana/lp_int_st.rs b/esp32c6/src/lp_ana/lp_int_st.rs
index 8516622718..2e393bffab 100644
--- a/esp32c6/src/lp_ana/lp_int_st.rs
+++ b/esp32c6/src/lp_ana/lp_int_st.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ST")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_INT_ST_SPEC;
 impl crate::RegisterSpec for LP_INT_ST_SPEC {
diff --git a/esp32c6/src/lp_aon/cpucore0_cfg.rs b/esp32c6/src/lp_aon/cpucore0_cfg.rs
index 8582b7abe3..b8f00ddbcf 100644
--- a/esp32c6/src/lp_aon/cpucore0_cfg.rs
+++ b/esp32c6/src/lp_aon/cpucore0_cfg.rs
@@ -46,31 +46,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPUCORE0_CFG")
-            .field(
-                "cpu_core0_sw_stall",
-                &format_args!("{}", self.cpu_core0_sw_stall().bits()),
-            )
+            .field("cpu_core0_sw_stall", &self.cpu_core0_sw_stall())
             .field(
                 "cpu_core0_ocd_halt_on_reset",
-                &format_args!("{}", self.cpu_core0_ocd_halt_on_reset().bit()),
+                &self.cpu_core0_ocd_halt_on_reset(),
             )
             .field(
                 "cpu_core0_stat_vector_sel",
-                &format_args!("{}", self.cpu_core0_stat_vector_sel().bit()),
-            )
-            .field(
-                "cpu_core0_dreset_mask",
-                &format_args!("{}", self.cpu_core0_dreset_mask().bit()),
+                &self.cpu_core0_stat_vector_sel(),
             )
+            .field("cpu_core0_dreset_mask", &self.cpu_core0_dreset_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPUCORE0_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/date.rs b/esp32c6/src/lp_aon/date.rs
index 2a59463e6d..80edcb7cad 100644
--- a/esp32c6/src/lp_aon/date.rs
+++ b/esp32c6/src/lp_aon/date.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("date", &self.date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/ext_wakeup_cntl.rs b/esp32c6/src/lp_aon/ext_wakeup_cntl.rs
index d9f39d0a90..0b2d26e41a 100644
--- a/esp32c6/src/lp_aon/ext_wakeup_cntl.rs
+++ b/esp32c6/src/lp_aon/ext_wakeup_cntl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP_CNTL")
-            .field(
-                "ext_wakeup_status",
-                &format_args!("{}", self.ext_wakeup_status().bits()),
-            )
-            .field(
-                "ext_wakeup_sel",
-                &format_args!("{}", self.ext_wakeup_sel().bits()),
-            )
-            .field(
-                "ext_wakeup_lv",
-                &format_args!("{}", self.ext_wakeup_lv().bits()),
-            )
-            .field(
-                "ext_wakeup_filter",
-                &format_args!("{}", self.ext_wakeup_filter().bit()),
-            )
+            .field("ext_wakeup_status", &self.ext_wakeup_status())
+            .field("ext_wakeup_sel", &self.ext_wakeup_sel())
+            .field("ext_wakeup_lv", &self.ext_wakeup_lv())
+            .field("ext_wakeup_filter", &self.ext_wakeup_filter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 14 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/gpio_hold0.rs b/esp32c6/src/lp_aon/gpio_hold0.rs
index b332611022..0fc6ebfa90 100644
--- a/esp32c6/src/lp_aon/gpio_hold0.rs
+++ b/esp32c6/src/lp_aon/gpio_hold0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_HOLD0")
-            .field("gpio_hold0", &format_args!("{}", self.gpio_hold0().bits()))
+            .field("gpio_hold0", &self.gpio_hold0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_HOLD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/gpio_hold1.rs b/esp32c6/src/lp_aon/gpio_hold1.rs
index 46eec62bc5..005befb609 100644
--- a/esp32c6/src/lp_aon/gpio_hold1.rs
+++ b/esp32c6/src/lp_aon/gpio_hold1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_HOLD1")
-            .field("gpio_hold1", &format_args!("{}", self.gpio_hold1().bits()))
+            .field("gpio_hold1", &self.gpio_hold1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_HOLD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/gpio_mux.rs b/esp32c6/src/lp_aon/gpio_mux.rs
index 9455ae5e1e..4977bbe7d6 100644
--- a/esp32c6/src/lp_aon/gpio_mux.rs
+++ b/esp32c6/src/lp_aon/gpio_mux.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_MUX")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_MUX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/io_mux.rs b/esp32c6/src/lp_aon/io_mux.rs
index de059fe1f6..082a0e1e1d 100644
--- a/esp32c6/src/lp_aon/io_mux.rs
+++ b/esp32c6/src/lp_aon/io_mux.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IO_MUX")
-            .field(
-                "reset_disable",
-                &format_args!("{}", self.reset_disable().bit()),
-            )
+            .field("reset_disable", &self.reset_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IO_MUX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/lpbus.rs b/esp32c6/src/lp_aon/lpbus.rs
index 1081be24b2..c2a7be1004 100644
--- a/esp32c6/src/lp_aon/lpbus.rs
+++ b/esp32c6/src/lp_aon/lpbus.rs
@@ -60,39 +60,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPBUS")
-            .field(
-                "fast_mem_wpulse",
-                &format_args!("{}", self.fast_mem_wpulse().bits()),
-            )
-            .field(
-                "fast_mem_wa",
-                &format_args!("{}", self.fast_mem_wa().bits()),
-            )
-            .field(
-                "fast_mem_ra",
-                &format_args!("{}", self.fast_mem_ra().bits()),
-            )
-            .field(
-                "fast_mem_mux_fsm_idle",
-                &format_args!("{}", self.fast_mem_mux_fsm_idle().bit()),
-            )
-            .field(
-                "fast_mem_mux_sel_status",
-                &format_args!("{}", self.fast_mem_mux_sel_status().bit()),
-            )
-            .field(
-                "fast_mem_mux_sel",
-                &format_args!("{}", self.fast_mem_mux_sel().bit()),
-            )
+            .field("fast_mem_wpulse", &self.fast_mem_wpulse())
+            .field("fast_mem_wa", &self.fast_mem_wa())
+            .field("fast_mem_ra", &self.fast_mem_ra())
+            .field("fast_mem_mux_fsm_idle", &self.fast_mem_mux_fsm_idle())
+            .field("fast_mem_mux_sel_status", &self.fast_mem_mux_sel_status())
+            .field("fast_mem_mux_sel", &self.fast_mem_mux_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPBUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:18 - This field controls fast memory WPULSE parameter."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/lpcore.rs b/esp32c6/src/lp_aon/lpcore.rs
index 1530ce66d6..947b244450 100644
--- a/esp32c6/src/lp_aon/lpcore.rs
+++ b/esp32c6/src/lp_aon/lpcore.rs
@@ -28,20 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPCORE")
-            .field(
-                "etm_wakeup_flag",
-                &format_args!("{}", self.etm_wakeup_flag().bit()),
-            )
-            .field("disable", &format_args!("{}", self.disable().bit()))
+            .field("etm_wakeup_flag", &self.etm_wakeup_flag())
+            .field("disable", &self.disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPCORE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/sar_cct.rs b/esp32c6/src/lp_aon/sar_cct.rs
index 305cefc278..bd1e64f8cf 100644
--- a/esp32c6/src/lp_aon/sar_cct.rs
+++ b/esp32c6/src/lp_aon/sar_cct.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_CCT")
-            .field(
-                "sar2_pwdet_cct",
-                &format_args!("{}", self.sar2_pwdet_cct().bits()),
-            )
+            .field("sar2_pwdet_cct", &self.sar2_pwdet_cct())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_CCT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 29:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/sdio_active.rs b/esp32c6/src/lp_aon/sdio_active.rs
index c0a0c8c452..bba850a575 100644
--- a/esp32c6/src/lp_aon/sdio_active.rs
+++ b/esp32c6/src/lp_aon/sdio_active.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_ACTIVE")
-            .field(
-                "sdio_act_dnum",
-                &format_args!("{}", self.sdio_act_dnum().bits()),
-            )
+            .field("sdio_act_dnum", &self.sdio_act_dnum())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_ACTIVE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/store0.rs b/esp32c6/src/lp_aon/store0.rs
index 750dead68d..4045afdfcb 100644
--- a/esp32c6/src/lp_aon/store0.rs
+++ b/esp32c6/src/lp_aon/store0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE0")
-            .field(
-                "lp_aon_store0",
-                &format_args!("{}", self.lp_aon_store0().bits()),
-            )
+            .field("lp_aon_store0", &self.lp_aon_store0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/store1.rs b/esp32c6/src/lp_aon/store1.rs
index 2a79b3c129..81a74039fa 100644
--- a/esp32c6/src/lp_aon/store1.rs
+++ b/esp32c6/src/lp_aon/store1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE1")
-            .field(
-                "lp_aon_store1",
-                &format_args!("{}", self.lp_aon_store1().bits()),
-            )
+            .field("lp_aon_store1", &self.lp_aon_store1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/store2.rs b/esp32c6/src/lp_aon/store2.rs
index 0f6971a297..82b8006008 100644
--- a/esp32c6/src/lp_aon/store2.rs
+++ b/esp32c6/src/lp_aon/store2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE2")
-            .field(
-                "lp_aon_store2",
-                &format_args!("{}", self.lp_aon_store2().bits()),
-            )
+            .field("lp_aon_store2", &self.lp_aon_store2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/store3.rs b/esp32c6/src/lp_aon/store3.rs
index ea9df2e7cb..ebb777ec5f 100644
--- a/esp32c6/src/lp_aon/store3.rs
+++ b/esp32c6/src/lp_aon/store3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE3")
-            .field(
-                "lp_aon_store3",
-                &format_args!("{}", self.lp_aon_store3().bits()),
-            )
+            .field("lp_aon_store3", &self.lp_aon_store3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/store4.rs b/esp32c6/src/lp_aon/store4.rs
index 2021c24b50..488dee70f8 100644
--- a/esp32c6/src/lp_aon/store4.rs
+++ b/esp32c6/src/lp_aon/store4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE4")
-            .field(
-                "lp_aon_store4",
-                &format_args!("{}", self.lp_aon_store4().bits()),
-            )
+            .field("lp_aon_store4", &self.lp_aon_store4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/store5.rs b/esp32c6/src/lp_aon/store5.rs
index 273844ba76..f495df460f 100644
--- a/esp32c6/src/lp_aon/store5.rs
+++ b/esp32c6/src/lp_aon/store5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE5")
-            .field(
-                "lp_aon_store5",
-                &format_args!("{}", self.lp_aon_store5().bits()),
-            )
+            .field("lp_aon_store5", &self.lp_aon_store5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/store6.rs b/esp32c6/src/lp_aon/store6.rs
index 54446a0324..5ad9e73830 100644
--- a/esp32c6/src/lp_aon/store6.rs
+++ b/esp32c6/src/lp_aon/store6.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE6")
-            .field(
-                "lp_aon_store6",
-                &format_args!("{}", self.lp_aon_store6().bits()),
-            )
+            .field("lp_aon_store6", &self.lp_aon_store6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/store7.rs b/esp32c6/src/lp_aon/store7.rs
index b7c4164974..f00bf7f8db 100644
--- a/esp32c6/src/lp_aon/store7.rs
+++ b/esp32c6/src/lp_aon/store7.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE7")
-            .field(
-                "lp_aon_store7",
-                &format_args!("{}", self.lp_aon_store7().bits()),
-            )
+            .field("lp_aon_store7", &self.lp_aon_store7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/store8.rs b/esp32c6/src/lp_aon/store8.rs
index d35122193f..0daf1323bb 100644
--- a/esp32c6/src/lp_aon/store8.rs
+++ b/esp32c6/src/lp_aon/store8.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE8")
-            .field(
-                "lp_aon_store8",
-                &format_args!("{}", self.lp_aon_store8().bits()),
-            )
+            .field("lp_aon_store8", &self.lp_aon_store8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/store9.rs b/esp32c6/src/lp_aon/store9.rs
index 460dd4ac7a..a510c36f12 100644
--- a/esp32c6/src/lp_aon/store9.rs
+++ b/esp32c6/src/lp_aon/store9.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE9")
-            .field(
-                "lp_aon_store9",
-                &format_args!("{}", self.lp_aon_store9().bits()),
-            )
+            .field("lp_aon_store9", &self.lp_aon_store9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/sys_cfg.rs b/esp32c6/src/lp_aon/sys_cfg.rs
index edc95b81e1..a6d6336740 100644
--- a/esp32c6/src/lp_aon/sys_cfg.rs
+++ b/esp32c6/src/lp_aon/sys_cfg.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYS_CFG")
-            .field(
-                "force_download_boot",
-                &format_args!("{}", self.force_download_boot().bit()),
-            )
+            .field("force_download_boot", &self.force_download_boot())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYS_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_aon/usb.rs b/esp32c6/src/lp_aon/usb.rs
index 78395ff8ef..0ffe7bb3d6 100644
--- a/esp32c6/src/lp_aon/usb.rs
+++ b/esp32c6/src/lp_aon/usb.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB")
-            .field(
-                "reset_disable",
-                &format_args!("{}", self.reset_disable().bit()),
-            )
+            .field("reset_disable", &self.reset_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_apm/clock_gate.rs b/esp32c6/src/lp_apm/clock_gate.rs
index 0ea9f4e7a3..0260550609 100644
--- a/esp32c6/src/lp_apm/clock_gate.rs
+++ b/esp32c6/src/lp_apm/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_clk_en"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_apm/date.rs b/esp32c6/src/lp_apm/date.rs
index fb73a9a02f..3825783dcf 100644
--- a/esp32c6/src/lp_apm/date.rs
+++ b/esp32c6/src/lp_apm/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/lp_apm/func_ctrl.rs b/esp32c6/src/lp_apm/func_ctrl.rs
index 7bc45f6559..b2ca69ca9c 100644
--- a/esp32c6/src/lp_apm/func_ctrl.rs
+++ b/esp32c6/src/lp_apm/func_ctrl.rs
@@ -37,23 +37,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_CTRL")
-            .field(
-                "m0_pms_func_en",
-                &format_args!("{}", self.m0_pms_func_en().bit()),
-            )
-            .field(
-                "m1_pms_func_en",
-                &format_args!("{}", self.m1_pms_func_en().bit()),
-            )
+            .field("m0_pms_func_en", &self.m0_pms_func_en())
+            .field("m1_pms_func_en", &self.m1_pms_func_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "PMS M(0-1) function enable"]
     #[doc = ""]
diff --git a/esp32c6/src/lp_apm/int_en.rs b/esp32c6/src/lp_apm/int_en.rs
index 0ed15aee51..7423665485 100644
--- a/esp32c6/src/lp_apm/int_en.rs
+++ b/esp32c6/src/lp_apm/int_en.rs
@@ -37,17 +37,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_EN")
-            .field("m0_apm", &format_args!("{}", self.m0_apm().bit()))
-            .field("m1_apm", &format_args!("{}", self.m1_apm().bit()))
+            .field("m0_apm", &self.m0_apm())
+            .field("m1_apm", &self.m1_apm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "APM M(0-1) interrupt enable"]
     #[doc = ""]
diff --git a/esp32c6/src/lp_apm/m/exception_info0.rs b/esp32c6/src/lp_apm/m/exception_info0.rs
index a0d5dea6f4..2c4b8088fb 100644
--- a/esp32c6/src/lp_apm/m/exception_info0.rs
+++ b/esp32c6/src/lp_apm/m/exception_info0.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXCEPTION_INFO0")
-            .field(
-                "exception_region",
-                &format_args!("{}", self.exception_region().bits()),
-            )
-            .field(
-                "exception_mode",
-                &format_args!("{}", self.exception_mode().bits()),
-            )
-            .field(
-                "exception_id",
-                &format_args!("{}", self.exception_id().bits()),
-            )
+            .field("exception_region", &self.exception_region())
+            .field("exception_mode", &self.exception_mode())
+            .field("exception_id", &self.exception_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXCEPTION_INFO0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 exception_info0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exception_info0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXCEPTION_INFO0_SPEC;
 impl crate::RegisterSpec for EXCEPTION_INFO0_SPEC {
diff --git a/esp32c6/src/lp_apm/m/exception_info1.rs b/esp32c6/src/lp_apm/m/exception_info1.rs
index 1a6977abc5..cb3b39d257 100644
--- a/esp32c6/src/lp_apm/m/exception_info1.rs
+++ b/esp32c6/src/lp_apm/m/exception_info1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXCEPTION_INFO1")
-            .field(
-                "exception_addr",
-                &format_args!("{}", self.exception_addr().bits()),
-            )
+            .field("exception_addr", &self.exception_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXCEPTION_INFO1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 exception_info1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exception_info1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXCEPTION_INFO1_SPEC;
 impl crate::RegisterSpec for EXCEPTION_INFO1_SPEC {
diff --git a/esp32c6/src/lp_apm/m/status.rs b/esp32c6/src/lp_apm/m/status.rs
index 6a5c666bbf..3e275a91ca 100644
--- a/esp32c6/src/lp_apm/m/status.rs
+++ b/esp32c6/src/lp_apm/m/status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field(
-                "exception_status",
-                &format_args!("{}", self.exception_status().bits()),
-            )
+            .field("exception_status", &self.exception_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32c6/src/lp_apm/region/addr_end.rs b/esp32c6/src/lp_apm/region/addr_end.rs
index 8940485f11..db15e1b66a 100644
--- a/esp32c6/src/lp_apm/region/addr_end.rs
+++ b/esp32c6/src/lp_apm/region/addr_end.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR_END")
-            .field("addr_end", &format_args!("{}", self.addr_end().bits()))
+            .field("addr_end", &self.addr_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_END_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - End address of region0"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_apm/region/addr_start.rs b/esp32c6/src/lp_apm/region/addr_start.rs
index 15654e8830..21d743f5e2 100644
--- a/esp32c6/src/lp_apm/region/addr_start.rs
+++ b/esp32c6/src/lp_apm/region/addr_start.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR_START")
-            .field("addr_start", &format_args!("{}", self.addr_start().bits()))
+            .field("addr_start", &self.addr_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_START_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Start address of region0"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_apm/region/pms_attr.rs b/esp32c6/src/lp_apm/region/pms_attr.rs
index 30b2486d8c..a929b05fa9 100644
--- a/esp32c6/src/lp_apm/region/pms_attr.rs
+++ b/esp32c6/src/lp_apm/region/pms_attr.rs
@@ -110,24 +110,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMS_ATTR")
-            .field("r0_pms_x", &format_args!("{}", self.r0_pms_x().bit()))
-            .field("r1_pms_x", &format_args!("{}", self.r1_pms_x().bit()))
-            .field("r2_pms_x", &format_args!("{}", self.r2_pms_x().bit()))
-            .field("r0_pms_w", &format_args!("{}", self.r0_pms_w().bit()))
-            .field("r1_pms_w", &format_args!("{}", self.r1_pms_w().bit()))
-            .field("r2_pms_w", &format_args!("{}", self.r2_pms_w().bit()))
-            .field("r0_pms_r", &format_args!("{}", self.r0_pms_r().bit()))
-            .field("r1_pms_r", &format_args!("{}", self.r1_pms_r().bit()))
-            .field("r2_pms_r", &format_args!("{}", self.r2_pms_r().bit()))
+            .field("r0_pms_x", &self.r0_pms_x())
+            .field("r1_pms_x", &self.r1_pms_x())
+            .field("r2_pms_x", &self.r2_pms_x())
+            .field("r0_pms_w", &self.r0_pms_w())
+            .field("r1_pms_w", &self.r1_pms_w())
+            .field("r2_pms_w", &self.r2_pms_w())
+            .field("r0_pms_r", &self.r0_pms_r())
+            .field("r1_pms_r", &self.r1_pms_r())
+            .field("r2_pms_r", &self.r2_pms_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMS_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Region execute authority in REE_MODE(0-2)"]
     #[doc = ""]
diff --git a/esp32c6/src/lp_apm/region_filter_en.rs b/esp32c6/src/lp_apm/region_filter_en.rs
index 981cf53ed6..d42627a48e 100644
--- a/esp32c6/src/lp_apm/region_filter_en.rs
+++ b/esp32c6/src/lp_apm/region_filter_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGION_FILTER_EN")
-            .field(
-                "region_filter_en",
-                &format_args!("{}", self.region_filter_en().bits()),
-            )
+            .field("region_filter_en", &self.region_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_FILTER_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Region filter enable"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_apm0/clock_gate.rs b/esp32c6/src/lp_apm0/clock_gate.rs
index 0ea9f4e7a3..0260550609 100644
--- a/esp32c6/src/lp_apm0/clock_gate.rs
+++ b/esp32c6/src/lp_apm0/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_clk_en"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_apm0/date.rs b/esp32c6/src/lp_apm0/date.rs
index fb73a9a02f..3825783dcf 100644
--- a/esp32c6/src/lp_apm0/date.rs
+++ b/esp32c6/src/lp_apm0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/lp_apm0/func_ctrl.rs b/esp32c6/src/lp_apm0/func_ctrl.rs
index 22fe19e812..bb1f6a4c17 100644
--- a/esp32c6/src/lp_apm0/func_ctrl.rs
+++ b/esp32c6/src/lp_apm0/func_ctrl.rs
@@ -32,19 +32,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_CTRL")
-            .field(
-                "m0_pms_func_en",
-                &format_args!("{}", self.m0_pms_func_en().bit()),
-            )
+            .field("m0_pms_func_en", &self.m0_pms_func_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "PMS M(0-0) function enable"]
     #[doc = ""]
diff --git a/esp32c6/src/lp_apm0/int_en.rs b/esp32c6/src/lp_apm0/int_en.rs
index de9d889823..e42f05e065 100644
--- a/esp32c6/src/lp_apm0/int_en.rs
+++ b/esp32c6/src/lp_apm0/int_en.rs
@@ -32,16 +32,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_EN")
-            .field("m0_apm", &format_args!("{}", self.m0_apm().bit()))
+            .field("m0_apm", &self.m0_apm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "APM M(0-0) interrupt enable"]
     #[doc = ""]
diff --git a/esp32c6/src/lp_apm0/m/exception_info0.rs b/esp32c6/src/lp_apm0/m/exception_info0.rs
index a0d5dea6f4..2c4b8088fb 100644
--- a/esp32c6/src/lp_apm0/m/exception_info0.rs
+++ b/esp32c6/src/lp_apm0/m/exception_info0.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXCEPTION_INFO0")
-            .field(
-                "exception_region",
-                &format_args!("{}", self.exception_region().bits()),
-            )
-            .field(
-                "exception_mode",
-                &format_args!("{}", self.exception_mode().bits()),
-            )
-            .field(
-                "exception_id",
-                &format_args!("{}", self.exception_id().bits()),
-            )
+            .field("exception_region", &self.exception_region())
+            .field("exception_mode", &self.exception_mode())
+            .field("exception_id", &self.exception_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXCEPTION_INFO0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 exception_info0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exception_info0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXCEPTION_INFO0_SPEC;
 impl crate::RegisterSpec for EXCEPTION_INFO0_SPEC {
diff --git a/esp32c6/src/lp_apm0/m/exception_info1.rs b/esp32c6/src/lp_apm0/m/exception_info1.rs
index 1a6977abc5..cb3b39d257 100644
--- a/esp32c6/src/lp_apm0/m/exception_info1.rs
+++ b/esp32c6/src/lp_apm0/m/exception_info1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXCEPTION_INFO1")
-            .field(
-                "exception_addr",
-                &format_args!("{}", self.exception_addr().bits()),
-            )
+            .field("exception_addr", &self.exception_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXCEPTION_INFO1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 exception_info1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exception_info1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXCEPTION_INFO1_SPEC;
 impl crate::RegisterSpec for EXCEPTION_INFO1_SPEC {
diff --git a/esp32c6/src/lp_apm0/m/status.rs b/esp32c6/src/lp_apm0/m/status.rs
index 6a5c666bbf..3e275a91ca 100644
--- a/esp32c6/src/lp_apm0/m/status.rs
+++ b/esp32c6/src/lp_apm0/m/status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field(
-                "exception_status",
-                &format_args!("{}", self.exception_status().bits()),
-            )
+            .field("exception_status", &self.exception_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32c6/src/lp_apm0/region/addr_end.rs b/esp32c6/src/lp_apm0/region/addr_end.rs
index 8940485f11..db15e1b66a 100644
--- a/esp32c6/src/lp_apm0/region/addr_end.rs
+++ b/esp32c6/src/lp_apm0/region/addr_end.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR_END")
-            .field("addr_end", &format_args!("{}", self.addr_end().bits()))
+            .field("addr_end", &self.addr_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_END_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - End address of region0"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_apm0/region/addr_start.rs b/esp32c6/src/lp_apm0/region/addr_start.rs
index 15654e8830..21d743f5e2 100644
--- a/esp32c6/src/lp_apm0/region/addr_start.rs
+++ b/esp32c6/src/lp_apm0/region/addr_start.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR_START")
-            .field("addr_start", &format_args!("{}", self.addr_start().bits()))
+            .field("addr_start", &self.addr_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_START_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Start address of region0"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_apm0/region/pms_attr.rs b/esp32c6/src/lp_apm0/region/pms_attr.rs
index 30b2486d8c..a929b05fa9 100644
--- a/esp32c6/src/lp_apm0/region/pms_attr.rs
+++ b/esp32c6/src/lp_apm0/region/pms_attr.rs
@@ -110,24 +110,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMS_ATTR")
-            .field("r0_pms_x", &format_args!("{}", self.r0_pms_x().bit()))
-            .field("r1_pms_x", &format_args!("{}", self.r1_pms_x().bit()))
-            .field("r2_pms_x", &format_args!("{}", self.r2_pms_x().bit()))
-            .field("r0_pms_w", &format_args!("{}", self.r0_pms_w().bit()))
-            .field("r1_pms_w", &format_args!("{}", self.r1_pms_w().bit()))
-            .field("r2_pms_w", &format_args!("{}", self.r2_pms_w().bit()))
-            .field("r0_pms_r", &format_args!("{}", self.r0_pms_r().bit()))
-            .field("r1_pms_r", &format_args!("{}", self.r1_pms_r().bit()))
-            .field("r2_pms_r", &format_args!("{}", self.r2_pms_r().bit()))
+            .field("r0_pms_x", &self.r0_pms_x())
+            .field("r1_pms_x", &self.r1_pms_x())
+            .field("r2_pms_x", &self.r2_pms_x())
+            .field("r0_pms_w", &self.r0_pms_w())
+            .field("r1_pms_w", &self.r1_pms_w())
+            .field("r2_pms_w", &self.r2_pms_w())
+            .field("r0_pms_r", &self.r0_pms_r())
+            .field("r1_pms_r", &self.r1_pms_r())
+            .field("r2_pms_r", &self.r2_pms_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMS_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Region execute authority in REE_MODE(0-2)"]
     #[doc = ""]
diff --git a/esp32c6/src/lp_apm0/region_filter_en.rs b/esp32c6/src/lp_apm0/region_filter_en.rs
index 981cf53ed6..d42627a48e 100644
--- a/esp32c6/src/lp_apm0/region_filter_en.rs
+++ b/esp32c6/src/lp_apm0/region_filter_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGION_FILTER_EN")
-            .field(
-                "region_filter_en",
-                &format_args!("{}", self.region_filter_en().bits()),
-            )
+            .field("region_filter_en", &self.region_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_FILTER_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Region filter enable"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_clkrst/clk_to_hp.rs b/esp32c6/src/lp_clkrst/clk_to_hp.rs
index 901a6280ab..aa35ff4c00 100644
--- a/esp32c6/src/lp_clkrst/clk_to_hp.rs
+++ b/esp32c6/src/lp_clkrst/clk_to_hp.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_TO_HP")
-            .field(
-                "icg_hp_xtal32k",
-                &format_args!("{}", self.icg_hp_xtal32k().bit()),
-            )
-            .field("icg_hp_sosc", &format_args!("{}", self.icg_hp_sosc().bit()))
-            .field(
-                "icg_hp_osc32k",
-                &format_args!("{}", self.icg_hp_osc32k().bit()),
-            )
-            .field("icg_hp_fosc", &format_args!("{}", self.icg_hp_fosc().bit()))
+            .field("icg_hp_xtal32k", &self.icg_hp_xtal32k())
+            .field("icg_hp_sosc", &self.icg_hp_sosc())
+            .field("icg_hp_osc32k", &self.icg_hp_osc32k())
+            .field("icg_hp_fosc", &self.icg_hp_fosc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_TO_HP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_clkrst/cpu_reset.rs b/esp32c6/src/lp_clkrst/cpu_reset.rs
index 5975cda7af..c5e74019c0 100644
--- a/esp32c6/src/lp_clkrst/cpu_reset.rs
+++ b/esp32c6/src/lp_clkrst/cpu_reset.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_RESET")
-            .field(
-                "rtc_wdt_cpu_reset_length",
-                &format_args!("{}", self.rtc_wdt_cpu_reset_length().bits()),
-            )
-            .field(
-                "rtc_wdt_cpu_reset_en",
-                &format_args!("{}", self.rtc_wdt_cpu_reset_en().bit()),
-            )
-            .field(
-                "cpu_stall_wait",
-                &format_args!("{}", self.cpu_stall_wait().bits()),
-            )
-            .field(
-                "cpu_stall_en",
-                &format_args!("{}", self.cpu_stall_en().bit()),
-            )
+            .field("rtc_wdt_cpu_reset_length", &self.rtc_wdt_cpu_reset_length())
+            .field("rtc_wdt_cpu_reset_en", &self.rtc_wdt_cpu_reset_en())
+            .field("cpu_stall_wait", &self.cpu_stall_wait())
+            .field("cpu_stall_en", &self.cpu_stall_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_RESET_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:24 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_clkrst/date.rs b/esp32c6/src/lp_clkrst/date.rs
index 079651ce06..8ab015a495 100644
--- a/esp32c6/src/lp_clkrst/date.rs
+++ b/esp32c6/src/lp_clkrst/date.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "clkrst_date",
-                &format_args!("{}", self.clkrst_date().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clkrst_date", &self.clkrst_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_clkrst/fosc_cntl.rs b/esp32c6/src/lp_clkrst/fosc_cntl.rs
index 04deb50cae..abd5d3eaa3 100644
--- a/esp32c6/src/lp_clkrst/fosc_cntl.rs
+++ b/esp32c6/src/lp_clkrst/fosc_cntl.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FOSC_CNTL")
-            .field("fosc_dfreq", &format_args!("{}", self.fosc_dfreq().bits()))
+            .field("fosc_dfreq", &self.fosc_dfreq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FOSC_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_clkrst/lp_clk_conf.rs b/esp32c6/src/lp_clkrst/lp_clk_conf.rs
index 16eef88e5a..bf8441701a 100644
--- a/esp32c6/src/lp_clkrst/lp_clk_conf.rs
+++ b/esp32c6/src/lp_clkrst/lp_clk_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CLK_CONF")
-            .field(
-                "slow_clk_sel",
-                &format_args!("{}", self.slow_clk_sel().bits()),
-            )
-            .field(
-                "fast_clk_sel",
-                &format_args!("{}", self.fast_clk_sel().bit()),
-            )
-            .field(
-                "lp_peri_div_num",
-                &format_args!("{}", self.lp_peri_div_num().bits()),
-            )
+            .field("slow_clk_sel", &self.slow_clk_sel())
+            .field("fast_clk_sel", &self.fast_clk_sel())
+            .field("lp_peri_div_num", &self.lp_peri_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_clkrst/lp_clk_en.rs b/esp32c6/src/lp_clkrst/lp_clk_en.rs
index 316fc21b67..ec70392c24 100644
--- a/esp32c6/src/lp_clkrst/lp_clk_en.rs
+++ b/esp32c6/src/lp_clkrst/lp_clk_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CLK_EN")
-            .field(
-                "fast_ori_gate",
-                &format_args!("{}", self.fast_ori_gate().bit()),
-            )
+            .field("fast_ori_gate", &self.fast_ori_gate())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_clkrst/lp_clk_po_en.rs b/esp32c6/src/lp_clkrst/lp_clk_po_en.rs
index 287da0bf37..118ba1f140 100644
--- a/esp32c6/src/lp_clkrst/lp_clk_po_en.rs
+++ b/esp32c6/src/lp_clkrst/lp_clk_po_en.rs
@@ -107,35 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CLK_PO_EN")
-            .field(
-                "aon_slow_oen",
-                &format_args!("{}", self.aon_slow_oen().bit()),
-            )
-            .field(
-                "aon_fast_oen",
-                &format_args!("{}", self.aon_fast_oen().bit()),
-            )
-            .field("sosc_oen", &format_args!("{}", self.sosc_oen().bit()))
-            .field("fosc_oen", &format_args!("{}", self.fosc_oen().bit()))
-            .field("osc32k_oen", &format_args!("{}", self.osc32k_oen().bit()))
-            .field("xtal32k_oen", &format_args!("{}", self.xtal32k_oen().bit()))
-            .field(
-                "core_efuse_oen",
-                &format_args!("{}", self.core_efuse_oen().bit()),
-            )
-            .field("slow_oen", &format_args!("{}", self.slow_oen().bit()))
-            .field("fast_oen", &format_args!("{}", self.fast_oen().bit()))
-            .field("rng_oen", &format_args!("{}", self.rng_oen().bit()))
-            .field("lpbus_oen", &format_args!("{}", self.lpbus_oen().bit()))
+            .field("aon_slow_oen", &self.aon_slow_oen())
+            .field("aon_fast_oen", &self.aon_fast_oen())
+            .field("sosc_oen", &self.sosc_oen())
+            .field("fosc_oen", &self.fosc_oen())
+            .field("osc32k_oen", &self.osc32k_oen())
+            .field("xtal32k_oen", &self.xtal32k_oen())
+            .field("core_efuse_oen", &self.core_efuse_oen())
+            .field("slow_oen", &self.slow_oen())
+            .field("fast_oen", &self.fast_oen())
+            .field("rng_oen", &self.rng_oen())
+            .field("lpbus_oen", &self.lpbus_oen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CLK_PO_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_clkrst/lp_rst_en.rs b/esp32c6/src/lp_clkrst/lp_rst_en.rs
index 9147d2f88c..372756979e 100644
--- a/esp32c6/src/lp_clkrst/lp_rst_en.rs
+++ b/esp32c6/src/lp_clkrst/lp_rst_en.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_RST_EN")
-            .field(
-                "aon_efuse_core_reset_en",
-                &format_args!("{}", self.aon_efuse_core_reset_en().bit()),
-            )
-            .field(
-                "lp_timer_reset_en",
-                &format_args!("{}", self.lp_timer_reset_en().bit()),
-            )
-            .field(
-                "wdt_reset_en",
-                &format_args!("{}", self.wdt_reset_en().bit()),
-            )
-            .field(
-                "ana_peri_reset_en",
-                &format_args!("{}", self.ana_peri_reset_en().bit()),
-            )
+            .field("aon_efuse_core_reset_en", &self.aon_efuse_core_reset_en())
+            .field("lp_timer_reset_en", &self.lp_timer_reset_en())
+            .field("wdt_reset_en", &self.wdt_reset_en())
+            .field("ana_peri_reset_en", &self.ana_peri_reset_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_RST_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_clkrst/lpmem_force.rs b/esp32c6/src/lp_clkrst/lpmem_force.rs
index 95a3efd9b8..c164724bb3 100644
--- a/esp32c6/src/lp_clkrst/lpmem_force.rs
+++ b/esp32c6/src/lp_clkrst/lpmem_force.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPMEM_FORCE")
-            .field(
-                "lpmem_clk_force_on",
-                &format_args!("{}", self.lpmem_clk_force_on().bit()),
-            )
+            .field("lpmem_clk_force_on", &self.lpmem_clk_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPMEM_FORCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_clkrst/lpperi.rs b/esp32c6/src/lp_clkrst/lpperi.rs
index 760a54ec0d..92032fef09 100644
--- a/esp32c6/src/lp_clkrst/lpperi.rs
+++ b/esp32c6/src/lp_clkrst/lpperi.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPPERI")
-            .field(
-                "lp_i2c_clk_sel",
-                &format_args!("{}", self.lp_i2c_clk_sel().bit()),
-            )
-            .field(
-                "lp_uart_clk_sel",
-                &format_args!("{}", self.lp_uart_clk_sel().bit()),
-            )
+            .field("lp_i2c_clk_sel", &self.lp_i2c_clk_sel())
+            .field("lp_uart_clk_sel", &self.lp_uart_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPPERI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_clkrst/rc32k_cntl.rs b/esp32c6/src/lp_clkrst/rc32k_cntl.rs
index a7abd1f2ef..50e5c9be91 100644
--- a/esp32c6/src/lp_clkrst/rc32k_cntl.rs
+++ b/esp32c6/src/lp_clkrst/rc32k_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RC32K_CNTL")
-            .field(
-                "rc32k_dfreq",
-                &format_args!("{}", self.rc32k_dfreq().bits()),
-            )
+            .field("rc32k_dfreq", &self.rc32k_dfreq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RC32K_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_clkrst/reset_cause.rs b/esp32c6/src/lp_clkrst/reset_cause.rs
index 8e7da12acf..41cd6b06ce 100644
--- a/esp32c6/src/lp_clkrst/reset_cause.rs
+++ b/esp32c6/src/lp_clkrst/reset_cause.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET_CAUSE")
-            .field(
-                "reset_cause",
-                &format_args!("{}", self.reset_cause().bits()),
-            )
-            .field(
-                "core0_reset_flag",
-                &format_args!("{}", self.core0_reset_flag().bit()),
-            )
+            .field("reset_cause", &self.reset_cause())
+            .field("core0_reset_flag", &self.core0_reset_flag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET_CAUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 29 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_clkrst/xtal32k.rs b/esp32c6/src/lp_clkrst/xtal32k.rs
index 0c231690c7..21734fb527 100644
--- a/esp32c6/src/lp_clkrst/xtal32k.rs
+++ b/esp32c6/src/lp_clkrst/xtal32k.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL32K")
-            .field(
-                "dres_xtal32k",
-                &format_args!("{}", self.dres_xtal32k().bits()),
-            )
-            .field(
-                "dgm_xtal32k",
-                &format_args!("{}", self.dgm_xtal32k().bits()),
-            )
-            .field(
-                "dbuf_xtal32k",
-                &format_args!("{}", self.dbuf_xtal32k().bit()),
-            )
-            .field(
-                "dac_xtal32k",
-                &format_args!("{}", self.dac_xtal32k().bits()),
-            )
+            .field("dres_xtal32k", &self.dres_xtal32k())
+            .field("dgm_xtal32k", &self.dgm_xtal32k())
+            .field("dbuf_xtal32k", &self.dbuf_xtal32k())
+            .field("dac_xtal32k", &self.dac_xtal32k())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL32K_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:24 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/clk_conf.rs b/esp32c6/src/lp_i2c0/clk_conf.rs
index 0c369fb990..8575bb85bf 100644
--- a/esp32c6/src/lp_i2c0/clk_conf.rs
+++ b/esp32c6/src/lp_i2c0/clk_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bit()))
-            .field("sclk_active", &format_args!("{}", self.sclk_active().bit()))
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_active", &self.sclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/comd.rs b/esp32c6/src/lp_i2c0/comd.rs
index 6f909ae304..980d858d87 100644
--- a/esp32c6/src/lp_i2c0/comd.rs
+++ b/esp32c6/src/lp_i2c0/comd.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMD")
-            .field("command", &format_args!("{}", self.command().bits()))
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This is the content of command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/ctr.rs b/esp32c6/src/lp_i2c0/ctr.rs
index 33b3a99b33..5d855d0513 100644
--- a/esp32c6/src/lp_i2c0/ctr.rs
+++ b/esp32c6/src/lp_i2c0/ctr.rs
@@ -86,44 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTR")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field(
-                "sample_scl_level",
-                &format_args!("{}", self.sample_scl_level().bit()),
-            )
-            .field(
-                "rx_full_ack_level",
-                &format_args!("{}", self.rx_full_ack_level().bit()),
-            )
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "arbitration_en",
-                &format_args!("{}", self.arbitration_en().bit()),
-            )
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("sample_scl_level", &self.sample_scl_level())
+            .field("rx_full_ack_level", &self.rx_full_ack_level())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("clk_en", &self.clk_en())
+            .field("arbitration_en", &self.arbitration_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: direct output, 0: open drain output."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/data.rs b/esp32c6/src/lp_i2c0/data.rs
index 098982488f..ffd32b29d3 100644
--- a/esp32c6/src/lp_i2c0/data.rs
+++ b/esp32c6/src/lp_i2c0/data.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field("fifo_rdata", &format_args!("{}", self.fifo_rdata().bits()))
+            .field("fifo_rdata", &self.fifo_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value of rx FIFO read data."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/date.rs b/esp32c6/src/lp_i2c0/date.rs
index e0a952920c..184e093cee 100644
--- a/esp32c6/src/lp_i2c0/date.rs
+++ b/esp32c6/src/lp_i2c0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/lp_i2c0/fifo_conf.rs b/esp32c6/src/lp_i2c0/fifo_conf.rs
index 8d7bcf4e41..765107a861 100644
--- a/esp32c6/src/lp_i2c0/fifo_conf.rs
+++ b/esp32c6/src/lp_i2c0/fifo_conf.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CONF")
-            .field(
-                "rxfifo_wm_thrhd",
-                &format_args!("{}", self.rxfifo_wm_thrhd().bits()),
-            )
-            .field(
-                "txfifo_wm_thrhd",
-                &format_args!("{}", self.txfifo_wm_thrhd().bits()),
-            )
-            .field("nonfifo_en", &format_args!("{}", self.nonfifo_en().bit()))
-            .field("rx_fifo_rst", &format_args!("{}", self.rx_fifo_rst().bit()))
-            .field("tx_fifo_rst", &format_args!("{}", self.tx_fifo_rst().bit()))
-            .field("fifo_prt_en", &format_args!("{}", self.fifo_prt_en().bit()))
+            .field("rxfifo_wm_thrhd", &self.rxfifo_wm_thrhd())
+            .field("txfifo_wm_thrhd", &self.txfifo_wm_thrhd())
+            .field("nonfifo_en", &self.nonfifo_en())
+            .field("rx_fifo_rst", &self.rx_fifo_rst())
+            .field("tx_fifo_rst", &self.tx_fifo_rst())
+            .field("fifo_prt_en", &self.fifo_prt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[3:0\\], reg_rxfifo_wm_int_raw bit will be valid."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/fifo_st.rs b/esp32c6/src/lp_i2c0/fifo_st.rs
index 566d9a1fdb..fda04e5d4d 100644
--- a/esp32c6/src/lp_i2c0/fifo_st.rs
+++ b/esp32c6/src/lp_i2c0/fifo_st.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_ST")
-            .field(
-                "rxfifo_raddr",
-                &format_args!("{}", self.rxfifo_raddr().bits()),
-            )
-            .field(
-                "rxfifo_waddr",
-                &format_args!("{}", self.rxfifo_waddr().bits()),
-            )
-            .field(
-                "txfifo_raddr",
-                &format_args!("{}", self.txfifo_raddr().bits()),
-            )
-            .field(
-                "txfifo_waddr",
-                &format_args!("{}", self.txfifo_waddr().bits()),
-            )
+            .field("rxfifo_raddr", &self.rxfifo_raddr())
+            .field("rxfifo_waddr", &self.rxfifo_waddr())
+            .field("txfifo_raddr", &self.txfifo_raddr())
+            .field("txfifo_waddr", &self.txfifo_waddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "FIFO status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_ST_SPEC;
 impl crate::RegisterSpec for FIFO_ST_SPEC {
diff --git a/esp32c6/src/lp_i2c0/filter_cfg.rs b/esp32c6/src/lp_i2c0/filter_cfg.rs
index b05ae9a4bf..98bdaa5979 100644
--- a/esp32c6/src/lp_i2c0/filter_cfg.rs
+++ b/esp32c6/src/lp_i2c0/filter_cfg.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CFG")
-            .field(
-                "scl_filter_thres",
-                &format_args!("{}", self.scl_filter_thres().bits()),
-            )
-            .field(
-                "sda_filter_thres",
-                &format_args!("{}", self.sda_filter_thres().bits()),
-            )
-            .field(
-                "scl_filter_en",
-                &format_args!("{}", self.scl_filter_en().bit()),
-            )
-            .field(
-                "sda_filter_en",
-                &format_args!("{}", self.sda_filter_en().bit()),
-            )
+            .field("scl_filter_thres", &self.scl_filter_thres())
+            .field("sda_filter_thres", &self.sda_filter_thres())
+            .field("scl_filter_en", &self.scl_filter_en())
+            .field("sda_filter_en", &self.sda_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/int_ena.rs b/esp32c6/src/lp_i2c0/int_ena.rs
index 8accc9e1dd..535b34f92b 100644
--- a/esp32c6/src/lp_i2c0/int_ena.rs
+++ b/esp32c6/src/lp_i2c0/int_ena.rs
@@ -152,46 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/int_raw.rs b/esp32c6/src/lp_i2c0/int_raw.rs
index 1ac9726d40..cd92338ced 100644
--- a/esp32c6/src/lp_i2c0/int_raw.rs
+++ b/esp32c6/src/lp_i2c0/int_raw.rs
@@ -118,46 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32c6/src/lp_i2c0/int_st.rs b/esp32c6/src/lp_i2c0/int_st.rs
index 1ffb4021ac..3ca3ab4a2e 100644
--- a/esp32c6/src/lp_i2c0/int_st.rs
+++ b/esp32c6/src/lp_i2c0/int_st.rs
@@ -118,46 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of captured I2C communication events\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/lp_i2c0/rxfifo_start_addr.rs b/esp32c6/src/lp_i2c0/rxfifo_start_addr.rs
index 634e8c8360..be2fa3cb09 100644
--- a/esp32c6/src/lp_i2c0/rxfifo_start_addr.rs
+++ b/esp32c6/src/lp_i2c0/rxfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXFIFO_START_ADDR")
-            .field(
-                "rxfifo_start_addr",
-                &format_args!("{}", self.rxfifo_start_addr().bits()),
-            )
+            .field("rxfifo_start_addr", &self.rxfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C RXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for RXFIFO_START_ADDR_SPEC {
diff --git a/esp32c6/src/lp_i2c0/scl_high_period.rs b/esp32c6/src/lp_i2c0/scl_high_period.rs
index f8a536137d..d5ba861338 100644
--- a/esp32c6/src/lp_i2c0/scl_high_period.rs
+++ b/esp32c6/src/lp_i2c0/scl_high_period.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH_PERIOD")
-            .field(
-                "scl_high_period",
-                &format_args!("{}", self.scl_high_period().bits()),
-            )
-            .field(
-                "scl_wait_high_period",
-                &format_args!("{}", self.scl_wait_high_period().bits()),
-            )
+            .field("scl_high_period", &self.scl_high_period())
+            .field("scl_wait_high_period", &self.scl_wait_high_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/scl_low_period.rs b/esp32c6/src/lp_i2c0/scl_low_period.rs
index bb4cd05e6d..c75461f0c7 100644
--- a/esp32c6/src/lp_i2c0/scl_low_period.rs
+++ b/esp32c6/src/lp_i2c0/scl_low_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW_PERIOD")
-            .field(
-                "scl_low_period",
-                &format_args!("{}", self.scl_low_period().bits()),
-            )
+            .field("scl_low_period", &self.scl_low_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/scl_main_st_time_out.rs b/esp32c6/src/lp_i2c0/scl_main_st_time_out.rs
index 7c392d273a..99069d3ce8 100644
--- a/esp32c6/src/lp_i2c0/scl_main_st_time_out.rs
+++ b/esp32c6/src/lp_i2c0/scl_main_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_MAIN_ST_TIME_OUT")
-            .field(
-                "scl_main_st_to_i2c",
-                &format_args!("{}", self.scl_main_st_to_i2c().bits()),
-            )
+            .field("scl_main_st_to_i2c", &self.scl_main_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_MAIN_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/scl_rstart_setup.rs b/esp32c6/src/lp_i2c0/scl_rstart_setup.rs
index 5f61d4fc91..63ddddc0f2 100644
--- a/esp32c6/src/lp_i2c0/scl_rstart_setup.rs
+++ b/esp32c6/src/lp_i2c0/scl_rstart_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_RSTART_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_RSTART_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/scl_sp_conf.rs b/esp32c6/src/lp_i2c0/scl_sp_conf.rs
index e3cdc353bf..492452e245 100644
--- a/esp32c6/src/lp_i2c0/scl_sp_conf.rs
+++ b/esp32c6/src/lp_i2c0/scl_sp_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_SP_CONF")
-            .field(
-                "scl_rst_slv_en",
-                &format_args!("{}", self.scl_rst_slv_en().bit()),
-            )
-            .field(
-                "scl_rst_slv_num",
-                &format_args!("{}", self.scl_rst_slv_num().bits()),
-            )
-            .field("scl_pd_en", &format_args!("{}", self.scl_pd_en().bit()))
-            .field("sda_pd_en", &format_args!("{}", self.sda_pd_en().bit()))
+            .field("scl_rst_slv_en", &self.scl_rst_slv_en())
+            .field("scl_rst_slv_num", &self.scl_rst_slv_num())
+            .field("scl_pd_en", &self.scl_pd_en())
+            .field("sda_pd_en", &self.sda_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_SP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/scl_st_time_out.rs b/esp32c6/src/lp_i2c0/scl_st_time_out.rs
index ba02a4a885..e56dd94c72 100644
--- a/esp32c6/src/lp_i2c0/scl_st_time_out.rs
+++ b/esp32c6/src/lp_i2c0/scl_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_ST_TIME_OUT")
-            .field(
-                "scl_st_to_i2c",
-                &format_args!("{}", self.scl_st_to_i2c().bits()),
-            )
+            .field("scl_st_to_i2c", &self.scl_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The threshold value of SCL_FSM state unchanged period. It should be o more than 23"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/scl_start_hold.rs b/esp32c6/src/lp_i2c0/scl_start_hold.rs
index eaa7d6ef78..073d03f4ca 100644
--- a/esp32c6/src/lp_i2c0/scl_start_hold.rs
+++ b/esp32c6/src/lp_i2c0/scl_start_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/scl_stop_hold.rs b/esp32c6/src/lp_i2c0/scl_stop_hold.rs
index edfbb10e29..3a115f7912 100644
--- a/esp32c6/src/lp_i2c0/scl_stop_hold.rs
+++ b/esp32c6/src/lp_i2c0/scl_stop_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the delay after the STOP condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/scl_stop_setup.rs b/esp32c6/src/lp_i2c0/scl_stop_setup.rs
index f231319c28..592044b6a2 100644
--- a/esp32c6/src/lp_i2c0/scl_stop_setup.rs
+++ b/esp32c6/src/lp_i2c0/scl_stop_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/sda_hold.rs b/esp32c6/src/lp_i2c0/sda_hold.rs
index b16485e33b..817872197e 100644
--- a/esp32c6/src/lp_i2c0/sda_hold.rs
+++ b/esp32c6/src/lp_i2c0/sda_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time to hold the data after the negative edge of SCL, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/sda_sample.rs b/esp32c6/src/lp_i2c0/sda_sample.rs
index 5a56fc1aa2..a8bd733614 100644
--- a/esp32c6/src/lp_i2c0/sda_sample.rs
+++ b/esp32c6/src/lp_i2c0/sda_sample.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_SAMPLE")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SDA is sampled, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/sr.rs b/esp32c6/src/lp_i2c0/sr.rs
index b12f9fe5e7..12408b7b23 100644
--- a/esp32c6/src/lp_i2c0/sr.rs
+++ b/esp32c6/src/lp_i2c0/sr.rs
@@ -55,28 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR")
-            .field("resp_rec", &format_args!("{}", self.resp_rec().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field(
-                "scl_main_state_last",
-                &format_args!("{}", self.scl_main_state_last().bits()),
-            )
-            .field(
-                "scl_state_last",
-                &format_args!("{}", self.scl_state_last().bits()),
-            )
+            .field("resp_rec", &self.resp_rec())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("scl_main_state_last", &self.scl_main_state_last())
+            .field("scl_state_last", &self.scl_state_last())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Describe I2C work status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SR_SPEC;
 impl crate::RegisterSpec for SR_SPEC {
diff --git a/esp32c6/src/lp_i2c0/to.rs b/esp32c6/src/lp_i2c0/to.rs
index 92f73cdd2b..cf95ff843d 100644
--- a/esp32c6/src/lp_i2c0/to.rs
+++ b/esp32c6/src/lp_i2c0/to.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO")
-            .field(
-                "time_out_value",
-                &format_args!("{}", self.time_out_value().bits()),
-            )
-            .field("time_out_en", &format_args!("{}", self.time_out_en().bit()))
+            .field("time_out_value", &self.time_out_value())
+            .field("time_out_en", &self.time_out_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to configure the timeout for receiving a data bit in APB clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c0/txfifo_start_addr.rs b/esp32c6/src/lp_i2c0/txfifo_start_addr.rs
index 8df0b6828e..c7cd4f0ea5 100644
--- a/esp32c6/src/lp_i2c0/txfifo_start_addr.rs
+++ b/esp32c6/src/lp_i2c0/txfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXFIFO_START_ADDR")
-            .field(
-                "txfifo_start_addr",
-                &format_args!("{}", self.txfifo_start_addr().bits()),
-            )
+            .field("txfifo_start_addr", &self.txfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C TXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for TXFIFO_START_ADDR_SPEC {
diff --git a/esp32c6/src/lp_i2c_ana_mst/ana_conf1.rs b/esp32c6/src/lp_i2c_ana_mst/ana_conf1.rs
index 9efc637cf0..48e8357f03 100644
--- a/esp32c6/src/lp_i2c_ana_mst/ana_conf1.rs
+++ b/esp32c6/src/lp_i2c_ana_mst/ana_conf1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ANA_CONF1")
             .field(
                 "lp_i2c_ana_mast_ana_conf1",
-                &format_args!("{}", self.lp_i2c_ana_mast_ana_conf1().bits()),
+                &self.lp_i2c_ana_mast_ana_conf1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ANA_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c_ana_mst/date.rs b/esp32c6/src/lp_i2c_ana_mst/date.rs
index 7c66e94455..4109f0a3ad 100644
--- a/esp32c6/src/lp_i2c_ana_mst/date.rs
+++ b/esp32c6/src/lp_i2c_ana_mst/date.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("DATE")
             .field(
                 "lp_i2c_ana_mast_i2c_mat_date",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c_mat_date().bits()),
+                &self.lp_i2c_ana_mast_i2c_mat_date(),
             )
             .field(
                 "lp_i2c_ana_mast_i2c_mat_clk_en",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c_mat_clk_en().bit()),
+                &self.lp_i2c_ana_mast_i2c_mat_clk_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c_ana_mst/device_en.rs b/esp32c6/src/lp_i2c_ana_mst/device_en.rs
index c05f64b881..31fe3030d3 100644
--- a/esp32c6/src/lp_i2c_ana_mst/device_en.rs
+++ b/esp32c6/src/lp_i2c_ana_mst/device_en.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DEVICE_EN")
             .field(
                 "lp_i2c_ana_mast_i2c_device_en",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c_device_en().bits()),
+                &self.lp_i2c_ana_mast_i2c_device_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEVICE_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c_ana_mst/i2c0_conf.rs b/esp32c6/src/lp_i2c_ana_mst/i2c0_conf.rs
index c1e1654991..b504d4fc7e 100644
--- a/esp32c6/src/lp_i2c_ana_mst/i2c0_conf.rs
+++ b/esp32c6/src/lp_i2c_ana_mst/i2c0_conf.rs
@@ -26,21 +26,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("I2C0_CONF")
             .field(
                 "lp_i2c_ana_mast_i2c0_conf",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c0_conf().bits()),
+                &self.lp_i2c_ana_mast_i2c0_conf(),
             )
             .field(
                 "lp_i2c_ana_mast_i2c0_status",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c0_status().bits()),
+                &self.lp_i2c_ana_mast_i2c0_status(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C0_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c_ana_mst/i2c0_ctrl.rs b/esp32c6/src/lp_i2c_ana_mst/i2c0_ctrl.rs
index 61a0db6f65..65287a20f8 100644
--- a/esp32c6/src/lp_i2c_ana_mst/i2c0_ctrl.rs
+++ b/esp32c6/src/lp_i2c_ana_mst/i2c0_ctrl.rs
@@ -26,21 +26,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("I2C0_CTRL")
             .field(
                 "lp_i2c_ana_mast_i2c0_ctrl",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c0_ctrl().bits()),
+                &self.lp_i2c_ana_mast_i2c0_ctrl(),
             )
             .field(
                 "lp_i2c_ana_mast_i2c0_busy",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c0_busy().bit()),
+                &self.lp_i2c_ana_mast_i2c0_busy(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C0_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:24 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c_ana_mst/i2c0_data.rs b/esp32c6/src/lp_i2c_ana_mst/i2c0_data.rs
index 07adc6c062..cef2eefbac 100644
--- a/esp32c6/src/lp_i2c_ana_mst/i2c0_data.rs
+++ b/esp32c6/src/lp_i2c_ana_mst/i2c0_data.rs
@@ -35,25 +35,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("I2C0_DATA")
             .field(
                 "lp_i2c_ana_mast_i2c0_rdata",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c0_rdata().bits()),
+                &self.lp_i2c_ana_mast_i2c0_rdata(),
             )
             .field(
                 "lp_i2c_ana_mast_i2c0_clk_sel",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c0_clk_sel().bits()),
+                &self.lp_i2c_ana_mast_i2c0_clk_sel(),
             )
             .field(
                 "lp_i2c_ana_mast_i2c_mst_sel",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c_mst_sel().bit()),
+                &self.lp_i2c_ana_mast_i2c_mst_sel(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C0_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:10 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_i2c_ana_mst/nouse.rs b/esp32c6/src/lp_i2c_ana_mst/nouse.rs
index 1de8eb0a26..55b1fab3cf 100644
--- a/esp32c6/src/lp_i2c_ana_mst/nouse.rs
+++ b/esp32c6/src/lp_i2c_ana_mst/nouse.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("NOUSE")
             .field(
                 "lp_i2c_ana_mast_i2c_mst_nouse",
-                &format_args!("{}", self.lp_i2c_ana_mast_i2c_mst_nouse().bits()),
+                &self.lp_i2c_ana_mast_i2c_mst_nouse(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NOUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/date.rs b/esp32c6/src/lp_io/date.rs
index 64035685b3..cdfe23b8bb 100644
--- a/esp32c6/src/lp_io/date.rs
+++ b/esp32c6/src/lp_io/date.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("lp_io_date", &format_args!("{}", self.lp_io_date().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("lp_io_date", &self.lp_io_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/debug_sel0.rs b/esp32c6/src/lp_io/debug_sel0.rs
index 409771c4ac..eb8c8b8270 100644
--- a/esp32c6/src/lp_io/debug_sel0.rs
+++ b/esp32c6/src/lp_io/debug_sel0.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEBUG_SEL0")
-            .field(
-                "lp_debug_sel0",
-                &format_args!("{}", self.lp_debug_sel0().bits()),
-            )
-            .field(
-                "lp_debug_sel1",
-                &format_args!("{}", self.lp_debug_sel1().bits()),
-            )
-            .field(
-                "lp_debug_sel2",
-                &format_args!("{}", self.lp_debug_sel2().bits()),
-            )
-            .field(
-                "lp_debug_sel3",
-                &format_args!("{}", self.lp_debug_sel3().bits()),
-            )
+            .field("lp_debug_sel0", &self.lp_debug_sel0())
+            .field("lp_debug_sel1", &self.lp_debug_sel1())
+            .field("lp_debug_sel2", &self.lp_debug_sel2())
+            .field("lp_debug_sel3", &self.lp_debug_sel3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBUG_SEL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/debug_sel1.rs b/esp32c6/src/lp_io/debug_sel1.rs
index 19dbe12821..b57ff3f36c 100644
--- a/esp32c6/src/lp_io/debug_sel1.rs
+++ b/esp32c6/src/lp_io/debug_sel1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEBUG_SEL1")
-            .field(
-                "lp_debug_sel4",
-                &format_args!("{}", self.lp_debug_sel4().bits()),
-            )
+            .field("lp_debug_sel4", &self.lp_debug_sel4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBUG_SEL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/gpio0.rs b/esp32c6/src/lp_io/gpio0.rs
index 706f1d9b2c..1b1af063d6 100644
--- a/esp32c6/src/lp_io/gpio0.rs
+++ b/esp32c6/src/lp_io/gpio0.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO0")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/gpio1.rs b/esp32c6/src/lp_io/gpio1.rs
index 261dcdbffc..9a620934c4 100644
--- a/esp32c6/src/lp_io/gpio1.rs
+++ b/esp32c6/src/lp_io/gpio1.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO1")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/gpio2.rs b/esp32c6/src/lp_io/gpio2.rs
index a89cda7229..1fc7ea5157 100644
--- a/esp32c6/src/lp_io/gpio2.rs
+++ b/esp32c6/src/lp_io/gpio2.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO2")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/gpio3.rs b/esp32c6/src/lp_io/gpio3.rs
index 44d0c9a62b..b00fbe55be 100644
--- a/esp32c6/src/lp_io/gpio3.rs
+++ b/esp32c6/src/lp_io/gpio3.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO3")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/gpio4.rs b/esp32c6/src/lp_io/gpio4.rs
index 10acff52ad..58226d62bb 100644
--- a/esp32c6/src/lp_io/gpio4.rs
+++ b/esp32c6/src/lp_io/gpio4.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO4")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/gpio5.rs b/esp32c6/src/lp_io/gpio5.rs
index 29e31574e5..75e462b779 100644
--- a/esp32c6/src/lp_io/gpio5.rs
+++ b/esp32c6/src/lp_io/gpio5.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO5")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/gpio6.rs b/esp32c6/src/lp_io/gpio6.rs
index 7ae5270135..7d760a5334 100644
--- a/esp32c6/src/lp_io/gpio6.rs
+++ b/esp32c6/src/lp_io/gpio6.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO6")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/gpio7.rs b/esp32c6/src/lp_io/gpio7.rs
index 3419bd2e71..52ccb41590 100644
--- a/esp32c6/src/lp_io/gpio7.rs
+++ b/esp32c6/src/lp_io/gpio7.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO7")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/in_.rs b/esp32c6/src/lp_io/in_.rs
index 52e0db6ac2..68c2177b0b 100644
--- a/esp32c6/src/lp_io/in_.rs
+++ b/esp32c6/src/lp_io/in_.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN")
-            .field("data_next", &format_args!("{}", self.data_next().bits()))
+            .field("data_next", &self.data_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SPEC;
 impl crate::RegisterSpec for IN_SPEC {
diff --git a/esp32c6/src/lp_io/lpi2c.rs b/esp32c6/src/lp_io/lpi2c.rs
index 5cf1617b4d..cc2a1335c6 100644
--- a/esp32c6/src/lp_io/lpi2c.rs
+++ b/esp32c6/src/lp_io/lpi2c.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPI2C")
-            .field(
-                "lp_i2c_sda_ie",
-                &format_args!("{}", self.lp_i2c_sda_ie().bit()),
-            )
-            .field(
-                "lp_i2c_scl_ie",
-                &format_args!("{}", self.lp_i2c_scl_ie().bit()),
-            )
+            .field("lp_i2c_sda_ie", &self.lp_i2c_sda_ie())
+            .field("lp_i2c_scl_ie", &self.lp_i2c_scl_ie())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPI2C_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/out_data.rs b/esp32c6/src/lp_io/out_data.rs
index 710fe1317f..cd1a1e3ae2 100644
--- a/esp32c6/src/lp_io/out_data.rs
+++ b/esp32c6/src/lp_io/out_data.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DATA")
-            .field("out_data", &format_args!("{}", self.out_data().bits()))
+            .field("out_data", &self.out_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - set lp gpio output data"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/out_enable.rs b/esp32c6/src/lp_io/out_enable.rs
index 6b88b8b426..f6e6fcba71 100644
--- a/esp32c6/src/lp_io/out_enable.rs
+++ b/esp32c6/src/lp_io/out_enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_ENABLE")
-            .field("enable", &format_args!("{}", self.enable().bits()))
+            .field("enable", &self.enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - set lp gpio output data"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/pin0.rs b/esp32c6/src/lp_io/pin0.rs
index b6732be9d4..758e3cbb4b 100644
--- a/esp32c6/src/lp_io/pin0.rs
+++ b/esp32c6/src/lp_io/pin0.rs
@@ -55,26 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN0")
-            .field(
-                "sync_bypass",
-                &format_args!("{}", self.sync_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("sync_bypass", &self.sync_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/pin1.rs b/esp32c6/src/lp_io/pin1.rs
index f7aaf589a4..fac9b465d9 100644
--- a/esp32c6/src/lp_io/pin1.rs
+++ b/esp32c6/src/lp_io/pin1.rs
@@ -55,26 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN1")
-            .field(
-                "sync_bypass",
-                &format_args!("{}", self.sync_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("sync_bypass", &self.sync_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/pin2.rs b/esp32c6/src/lp_io/pin2.rs
index 5ad3e542ee..44b1844756 100644
--- a/esp32c6/src/lp_io/pin2.rs
+++ b/esp32c6/src/lp_io/pin2.rs
@@ -55,26 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN2")
-            .field(
-                "sync_bypass",
-                &format_args!("{}", self.sync_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("sync_bypass", &self.sync_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/pin3.rs b/esp32c6/src/lp_io/pin3.rs
index 3711080343..28e74e1dd4 100644
--- a/esp32c6/src/lp_io/pin3.rs
+++ b/esp32c6/src/lp_io/pin3.rs
@@ -55,26 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN3")
-            .field(
-                "sync_bypass",
-                &format_args!("{}", self.sync_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("sync_bypass", &self.sync_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/pin4.rs b/esp32c6/src/lp_io/pin4.rs
index bd6d916c56..1411f07a3b 100644
--- a/esp32c6/src/lp_io/pin4.rs
+++ b/esp32c6/src/lp_io/pin4.rs
@@ -55,26 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN4")
-            .field(
-                "sync_bypass",
-                &format_args!("{}", self.sync_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("sync_bypass", &self.sync_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/pin5.rs b/esp32c6/src/lp_io/pin5.rs
index 28260e111c..6836a8ef94 100644
--- a/esp32c6/src/lp_io/pin5.rs
+++ b/esp32c6/src/lp_io/pin5.rs
@@ -55,26 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN5")
-            .field(
-                "sync_bypass",
-                &format_args!("{}", self.sync_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("sync_bypass", &self.sync_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/pin6.rs b/esp32c6/src/lp_io/pin6.rs
index dee1ebbdfe..009d0c878c 100644
--- a/esp32c6/src/lp_io/pin6.rs
+++ b/esp32c6/src/lp_io/pin6.rs
@@ -55,26 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN6")
-            .field(
-                "sync_bypass",
-                &format_args!("{}", self.sync_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("sync_bypass", &self.sync_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/pin7.rs b/esp32c6/src/lp_io/pin7.rs
index ff96a92969..3a4c2972fe 100644
--- a/esp32c6/src/lp_io/pin7.rs
+++ b/esp32c6/src/lp_io/pin7.rs
@@ -55,26 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN7")
-            .field(
-                "sync_bypass",
-                &format_args!("{}", self.sync_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("sync_bypass", &self.sync_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - need des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/status.rs b/esp32c6/src/lp_io/status.rs
index de8abe30b5..6826e6ffe5 100644
--- a/esp32c6/src/lp_io/status.rs
+++ b/esp32c6/src/lp_io/status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("interrupt", &format_args!("{}", self.interrupt().bits()))
+            .field("interrupt", &self.interrupt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - set lp gpio output data"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_io/status_interrupt.rs b/esp32c6/src/lp_io/status_interrupt.rs
index 4ca1d50859..3c10862ac7 100644
--- a/esp32c6/src/lp_io/status_interrupt.rs
+++ b/esp32c6/src/lp_io/status_interrupt.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_INTERRUPT")
-            .field("next", &format_args!("{}", self.next().bits()))
+            .field("next", &self.next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_INTERRUPT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_interrupt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_INTERRUPT_SPEC;
 impl crate::RegisterSpec for STATUS_INTERRUPT_SPEC {
diff --git a/esp32c6/src/lp_peri/bus_timeout.rs b/esp32c6/src/lp_peri/bus_timeout.rs
index c9162357b7..559e19f4c6 100644
--- a/esp32c6/src/lp_peri/bus_timeout.rs
+++ b/esp32c6/src/lp_peri/bus_timeout.rs
@@ -28,23 +28,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMEOUT")
-            .field(
-                "lp_peri_timeout_thres",
-                &format_args!("{}", self.lp_peri_timeout_thres().bits()),
-            )
+            .field("lp_peri_timeout_thres", &self.lp_peri_timeout_thres())
             .field(
                 "lp_peri_timeout_protect_en",
-                &format_args!("{}", self.lp_peri_timeout_protect_en().bit()),
+                &self.lp_peri_timeout_protect_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMEOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 14:29 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_peri/bus_timeout_addr.rs b/esp32c6/src/lp_peri/bus_timeout_addr.rs
index f90baac504..6527db51bb 100644
--- a/esp32c6/src/lp_peri/bus_timeout_addr.rs
+++ b/esp32c6/src/lp_peri/bus_timeout_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMEOUT_ADDR")
-            .field(
-                "lp_peri_timeout_addr",
-                &format_args!("{}", self.lp_peri_timeout_addr().bits()),
-            )
+            .field("lp_peri_timeout_addr", &self.lp_peri_timeout_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMEOUT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_timeout_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUS_TIMEOUT_ADDR_SPEC;
 impl crate::RegisterSpec for BUS_TIMEOUT_ADDR_SPEC {
diff --git a/esp32c6/src/lp_peri/bus_timeout_uid.rs b/esp32c6/src/lp_peri/bus_timeout_uid.rs
index d8620b1d01..43079dcad0 100644
--- a/esp32c6/src/lp_peri/bus_timeout_uid.rs
+++ b/esp32c6/src/lp_peri/bus_timeout_uid.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMEOUT_UID")
-            .field(
-                "lp_peri_timeout_uid",
-                &format_args!("{}", self.lp_peri_timeout_uid().bits()),
-            )
+            .field("lp_peri_timeout_uid", &self.lp_peri_timeout_uid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMEOUT_UID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_timeout_uid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUS_TIMEOUT_UID_SPEC;
 impl crate::RegisterSpec for BUS_TIMEOUT_UID_SPEC {
diff --git a/esp32c6/src/lp_peri/clk_en.rs b/esp32c6/src/lp_peri/clk_en.rs
index f8eddb7030..371447fbef 100644
--- a/esp32c6/src/lp_peri/clk_en.rs
+++ b/esp32c6/src/lp_peri/clk_en.rs
@@ -89,42 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EN")
-            .field(
-                "lp_touch_ck_en",
-                &format_args!("{}", self.lp_touch_ck_en().bit()),
-            )
-            .field("rng_ck_en", &format_args!("{}", self.rng_ck_en().bit()))
-            .field(
-                "otp_dbg_ck_en",
-                &format_args!("{}", self.otp_dbg_ck_en().bit()),
-            )
-            .field(
-                "lp_uart_ck_en",
-                &format_args!("{}", self.lp_uart_ck_en().bit()),
-            )
-            .field("lp_io_ck_en", &format_args!("{}", self.lp_io_ck_en().bit()))
-            .field(
-                "lp_ext_i2c_ck_en",
-                &format_args!("{}", self.lp_ext_i2c_ck_en().bit()),
-            )
-            .field(
-                "lp_ana_i2c_ck_en",
-                &format_args!("{}", self.lp_ana_i2c_ck_en().bit()),
-            )
-            .field("efuse_ck_en", &format_args!("{}", self.efuse_ck_en().bit()))
-            .field(
-                "lp_cpu_ck_en",
-                &format_args!("{}", self.lp_cpu_ck_en().bit()),
-            )
+            .field("lp_touch_ck_en", &self.lp_touch_ck_en())
+            .field("rng_ck_en", &self.rng_ck_en())
+            .field("otp_dbg_ck_en", &self.otp_dbg_ck_en())
+            .field("lp_uart_ck_en", &self.lp_uart_ck_en())
+            .field("lp_io_ck_en", &self.lp_io_ck_en())
+            .field("lp_ext_i2c_ck_en", &self.lp_ext_i2c_ck_en())
+            .field("lp_ana_i2c_ck_en", &self.lp_ana_i2c_ck_en())
+            .field("efuse_ck_en", &self.efuse_ck_en())
+            .field("lp_cpu_ck_en", &self.lp_cpu_ck_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 23 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_peri/cpu.rs b/esp32c6/src/lp_peri/cpu.rs
index bcb33042d9..ea8c30e62d 100644
--- a/esp32c6/src/lp_peri/cpu.rs
+++ b/esp32c6/src/lp_peri/cpu.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU")
-            .field(
-                "lpcore_dbgm_unavaliable",
-                &format_args!("{}", self.lpcore_dbgm_unavaliable().bit()),
-            )
+            .field("lpcore_dbgm_unavaliable", &self.lpcore_dbgm_unavaliable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_peri/date.rs b/esp32c6/src/lp_peri/date.rs
index 6cd7bea0a5..9e433a72d2 100644
--- a/esp32c6/src/lp_peri/date.rs
+++ b/esp32c6/src/lp_peri/date.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "lpperi_date",
-                &format_args!("{}", self.lpperi_date().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("lpperi_date", &self.lpperi_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_peri/interrupt_source.rs b/esp32c6/src/lp_peri/interrupt_source.rs
index 3a58e713a5..079ad23d59 100644
--- a/esp32c6/src/lp_peri/interrupt_source.rs
+++ b/esp32c6/src/lp_peri/interrupt_source.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT_SOURCE")
-            .field(
-                "lp_interrupt_source",
-                &format_args!("{}", self.lp_interrupt_source().bits()),
-            )
+            .field("lp_interrupt_source", &self.lp_interrupt_source())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_SOURCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt_source::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERRUPT_SOURCE_SPEC;
 impl crate::RegisterSpec for INTERRUPT_SOURCE_SPEC {
diff --git a/esp32c6/src/lp_peri/mem_ctrl.rs b/esp32c6/src/lp_peri/mem_ctrl.rs
index 19f827781a..32a31f41d6 100644
--- a/esp32c6/src/lp_peri/mem_ctrl.rs
+++ b/esp32c6/src/lp_peri/mem_ctrl.rs
@@ -46,31 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CTRL")
-            .field(
-                "uart_wakeup_flag",
-                &format_args!("{}", self.uart_wakeup_flag().bit()),
-            )
-            .field(
-                "uart_wakeup_en",
-                &format_args!("{}", self.uart_wakeup_en().bit()),
-            )
-            .field(
-                "uart_mem_force_pd",
-                &format_args!("{}", self.uart_mem_force_pd().bit()),
-            )
-            .field(
-                "uart_mem_force_pu",
-                &format_args!("{}", self.uart_mem_force_pu().bit()),
-            )
+            .field("uart_wakeup_flag", &self.uart_wakeup_flag())
+            .field("uart_wakeup_en", &self.uart_wakeup_en())
+            .field("uart_mem_force_pd", &self.uart_mem_force_pd())
+            .field("uart_mem_force_pu", &self.uart_mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_peri/reset_en.rs b/esp32c6/src/lp_peri/reset_en.rs
index 37a0056097..a12a5fb0b6 100644
--- a/esp32c6/src/lp_peri/reset_en.rs
+++ b/esp32c6/src/lp_peri/reset_en.rs
@@ -75,43 +75,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET_EN")
-            .field(
-                "lp_touch_reset_en",
-                &format_args!("{}", self.lp_touch_reset_en().bit()),
-            )
-            .field(
-                "otp_dbg_reset_en",
-                &format_args!("{}", self.otp_dbg_reset_en().bit()),
-            )
-            .field(
-                "lp_uart_reset_en",
-                &format_args!("{}", self.lp_uart_reset_en().bit()),
-            )
-            .field(
-                "lp_io_reset_en",
-                &format_args!("{}", self.lp_io_reset_en().bit()),
-            )
-            .field(
-                "lp_ext_i2c_reset_en",
-                &format_args!("{}", self.lp_ext_i2c_reset_en().bit()),
-            )
-            .field(
-                "lp_ana_i2c_reset_en",
-                &format_args!("{}", self.lp_ana_i2c_reset_en().bit()),
-            )
-            .field(
-                "efuse_reset_en",
-                &format_args!("{}", self.efuse_reset_en().bit()),
-            )
+            .field("lp_touch_reset_en", &self.lp_touch_reset_en())
+            .field("otp_dbg_reset_en", &self.otp_dbg_reset_en())
+            .field("lp_uart_reset_en", &self.lp_uart_reset_en())
+            .field("lp_io_reset_en", &self.lp_io_reset_en())
+            .field("lp_ext_i2c_reset_en", &self.lp_ext_i2c_reset_en())
+            .field("lp_ana_i2c_reset_en", &self.lp_ana_i2c_reset_en())
+            .field("efuse_reset_en", &self.efuse_reset_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 23 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_peri/rng_data.rs b/esp32c6/src/lp_peri/rng_data.rs
index 713145ebb6..13f1db3a76 100644
--- a/esp32c6/src/lp_peri/rng_data.rs
+++ b/esp32c6/src/lp_peri/rng_data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RNG_DATA")
-            .field("rnd_data", &format_args!("{}", self.rnd_data().bits()))
+            .field("rnd_data", &self.rnd_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RNG_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RNG_DATA_SPEC;
 impl crate::RegisterSpec for RNG_DATA_SPEC {
diff --git a/esp32c6/src/lp_tee/clock_gate.rs b/esp32c6/src/lp_tee/clock_gate.rs
index b2c147f4a9..0c07ea99d2 100644
--- a/esp32c6/src/lp_tee/clock_gate.rs
+++ b/esp32c6/src/lp_tee/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_clk_en"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_tee/date.rs b/esp32c6/src/lp_tee/date.rs
index add181b414..d755558c2d 100644
--- a/esp32c6/src/lp_tee/date.rs
+++ b/esp32c6/src/lp_tee/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/lp_tee/force_acc_hp.rs b/esp32c6/src/lp_tee/force_acc_hp.rs
index 49422ac57d..fc6756faf1 100644
--- a/esp32c6/src/lp_tee/force_acc_hp.rs
+++ b/esp32c6/src/lp_tee/force_acc_hp.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("FORCE_ACC_HP")
             .field(
                 "lp_aon_force_acc_hpmem_en",
-                &format_args!("{}", self.lp_aon_force_acc_hpmem_en().bit()),
+                &self.lp_aon_force_acc_hpmem_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FORCE_ACC_HP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_tee/m_mode_ctrl.rs b/esp32c6/src/lp_tee/m_mode_ctrl.rs
index 62e16866e7..34a691f102 100644
--- a/esp32c6/src/lp_tee/m_mode_ctrl.rs
+++ b/esp32c6/src/lp_tee/m_mode_ctrl.rs
@@ -100,16 +100,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("M_MODE_CTRL")
-            .field("mode", &format_args!("{}", self.mode().bits()))
+            .field("mode", &self.mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MODE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_timer/date.rs b/esp32c6/src/lp_timer/date.rs
index d47a89ee4b..e9890af6e1 100644
--- a/esp32c6/src/lp_timer/date.rs
+++ b/esp32c6/src/lp_timer/date.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("date", &self.date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_timer/int_ena.rs b/esp32c6/src/lp_timer/int_ena.rs
index 92ce086df1..f27ed7c86e 100644
--- a/esp32c6/src/lp_timer/int_ena.rs
+++ b/esp32c6/src/lp_timer/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("overflow", &format_args!("{}", self.overflow().bit()))
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("overflow", &self.overflow())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_timer/int_raw.rs b/esp32c6/src/lp_timer/int_raw.rs
index a18d0a9b31..a5598fb406 100644
--- a/esp32c6/src/lp_timer/int_raw.rs
+++ b/esp32c6/src/lp_timer/int_raw.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("overflow", &format_args!("{}", self.overflow().bit()))
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("overflow", &self.overflow())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_timer/int_st.rs b/esp32c6/src/lp_timer/int_st.rs
index 101196ba9b..ee18087a3c 100644
--- a/esp32c6/src/lp_timer/int_st.rs
+++ b/esp32c6/src/lp_timer/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("overflow", &format_args!("{}", self.overflow().bit()))
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("overflow", &self.overflow())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/lp_timer/lp_int_ena.rs b/esp32c6/src/lp_timer/lp_int_ena.rs
index 5ea363c710..91e11e2772 100644
--- a/esp32c6/src/lp_timer/lp_int_ena.rs
+++ b/esp32c6/src/lp_timer/lp_int_ena.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ENA")
-            .field(
-                "main_timer_overflow",
-                &format_args!("{}", self.main_timer_overflow().bit()),
-            )
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
+            .field("main_timer_overflow", &self.main_timer_overflow())
+            .field("main_timer", &self.main_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_timer/lp_int_raw.rs b/esp32c6/src/lp_timer/lp_int_raw.rs
index 6df03d55aa..0c01b2cf70 100644
--- a/esp32c6/src/lp_timer/lp_int_raw.rs
+++ b/esp32c6/src/lp_timer/lp_int_raw.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_RAW")
-            .field(
-                "main_timer_overflow",
-                &format_args!("{}", self.main_timer_overflow().bit()),
-            )
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
+            .field("main_timer_overflow", &self.main_timer_overflow())
+            .field("main_timer", &self.main_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_timer/lp_int_st.rs b/esp32c6/src/lp_timer/lp_int_st.rs
index ca21a1cf4d..b109777cd5 100644
--- a/esp32c6/src/lp_timer/lp_int_st.rs
+++ b/esp32c6/src/lp_timer/lp_int_st.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ST")
-            .field(
-                "main_timer_overflow",
-                &format_args!("{}", self.main_timer_overflow().bit()),
-            )
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
+            .field("main_timer_overflow", &self.main_timer_overflow())
+            .field("main_timer", &self.main_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_INT_ST_SPEC;
 impl crate::RegisterSpec for LP_INT_ST_SPEC {
diff --git a/esp32c6/src/lp_timer/main_buf0_high.rs b/esp32c6/src/lp_timer/main_buf0_high.rs
index 7ec6b260aa..4545617b27 100644
--- a/esp32c6/src/lp_timer/main_buf0_high.rs
+++ b/esp32c6/src/lp_timer/main_buf0_high.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF0_HIGH")
-            .field(
-                "main_timer_buf0_high",
-                &format_args!("{}", self.main_timer_buf0_high().bits()),
-            )
+            .field("main_timer_buf0_high", &self.main_timer_buf0_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF0_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf0_high::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF0_HIGH_SPEC;
 impl crate::RegisterSpec for MAIN_BUF0_HIGH_SPEC {
diff --git a/esp32c6/src/lp_timer/main_buf0_low.rs b/esp32c6/src/lp_timer/main_buf0_low.rs
index b3e2efd010..9c176ef6e3 100644
--- a/esp32c6/src/lp_timer/main_buf0_low.rs
+++ b/esp32c6/src/lp_timer/main_buf0_low.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF0_LOW")
-            .field(
-                "main_timer_buf0_low",
-                &format_args!("{}", self.main_timer_buf0_low().bits()),
-            )
+            .field("main_timer_buf0_low", &self.main_timer_buf0_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF0_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf0_low::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF0_LOW_SPEC;
 impl crate::RegisterSpec for MAIN_BUF0_LOW_SPEC {
diff --git a/esp32c6/src/lp_timer/main_buf1_high.rs b/esp32c6/src/lp_timer/main_buf1_high.rs
index 343bec706f..3fd0b05256 100644
--- a/esp32c6/src/lp_timer/main_buf1_high.rs
+++ b/esp32c6/src/lp_timer/main_buf1_high.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF1_HIGH")
-            .field(
-                "main_timer_buf1_high",
-                &format_args!("{}", self.main_timer_buf1_high().bits()),
-            )
+            .field("main_timer_buf1_high", &self.main_timer_buf1_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF1_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf1_high::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF1_HIGH_SPEC;
 impl crate::RegisterSpec for MAIN_BUF1_HIGH_SPEC {
diff --git a/esp32c6/src/lp_timer/main_buf1_low.rs b/esp32c6/src/lp_timer/main_buf1_low.rs
index e9cb954df6..020cfc0659 100644
--- a/esp32c6/src/lp_timer/main_buf1_low.rs
+++ b/esp32c6/src/lp_timer/main_buf1_low.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF1_LOW")
-            .field(
-                "main_timer_buf1_low",
-                &format_args!("{}", self.main_timer_buf1_low().bits()),
-            )
+            .field("main_timer_buf1_low", &self.main_timer_buf1_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF1_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf1_low::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF1_LOW_SPEC;
 impl crate::RegisterSpec for MAIN_BUF1_LOW_SPEC {
diff --git a/esp32c6/src/lp_timer/tar0_high.rs b/esp32c6/src/lp_timer/tar0_high.rs
index ba43f1ec62..abf6de0468 100644
--- a/esp32c6/src/lp_timer/tar0_high.rs
+++ b/esp32c6/src/lp_timer/tar0_high.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TAR0_HIGH")
-            .field(
-                "main_timer_tar_high0",
-                &format_args!("{}", self.main_timer_tar_high0().bits()),
-            )
+            .field("main_timer_tar_high0", &self.main_timer_tar_high0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TAR0_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_timer/tar0_low.rs b/esp32c6/src/lp_timer/tar0_low.rs
index 131d1c04d8..fe2273147d 100644
--- a/esp32c6/src/lp_timer/tar0_low.rs
+++ b/esp32c6/src/lp_timer/tar0_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TAR0_LOW")
-            .field(
-                "main_timer_tar_low0",
-                &format_args!("{}", self.main_timer_tar_low0().bits()),
-            )
+            .field("main_timer_tar_low0", &self.main_timer_tar_low0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TAR0_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_timer/tar1_high.rs b/esp32c6/src/lp_timer/tar1_high.rs
index b3005a0f94..730d601d28 100644
--- a/esp32c6/src/lp_timer/tar1_high.rs
+++ b/esp32c6/src/lp_timer/tar1_high.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TAR1_HIGH")
-            .field(
-                "main_timer_tar_high1",
-                &format_args!("{}", self.main_timer_tar_high1().bits()),
-            )
+            .field("main_timer_tar_high1", &self.main_timer_tar_high1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TAR1_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_timer/tar1_low.rs b/esp32c6/src/lp_timer/tar1_low.rs
index 78226f1ebc..1a74b66e78 100644
--- a/esp32c6/src/lp_timer/tar1_low.rs
+++ b/esp32c6/src/lp_timer/tar1_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TAR1_LOW")
-            .field(
-                "main_timer_tar_low1",
-                &format_args!("{}", self.main_timer_tar_low1().bits()),
-            )
+            .field("main_timer_tar_low1", &self.main_timer_tar_low1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TAR1_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_timer/update.rs b/esp32c6/src/lp_timer/update.rs
index 9f49d41d18..b0cb0a2d30 100644
--- a/esp32c6/src/lp_timer/update.rs
+++ b/esp32c6/src/lp_timer/update.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE")
-            .field(
-                "main_timer_xtal_off",
-                &format_args!("{}", self.main_timer_xtal_off().bit()),
-            )
-            .field(
-                "main_timer_sys_stall",
-                &format_args!("{}", self.main_timer_sys_stall().bit()),
-            )
-            .field(
-                "main_timer_sys_rst",
-                &format_args!("{}", self.main_timer_sys_rst().bit()),
-            )
+            .field("main_timer_xtal_off", &self.main_timer_xtal_off())
+            .field("main_timer_sys_stall", &self.main_timer_sys_stall())
+            .field("main_timer_sys_rst", &self.main_timer_sys_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/afifo_status.rs b/esp32c6/src/lp_uart/afifo_status.rs
index 32a27a7eed..22f55103b7 100644
--- a/esp32c6/src/lp_uart/afifo_status.rs
+++ b/esp32c6/src/lp_uart/afifo_status.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AFIFO_STATUS")
-            .field(
-                "tx_afifo_full",
-                &format_args!("{}", self.tx_afifo_full().bit()),
-            )
-            .field(
-                "tx_afifo_empty",
-                &format_args!("{}", self.tx_afifo_empty().bit()),
-            )
-            .field(
-                "rx_afifo_full",
-                &format_args!("{}", self.rx_afifo_full().bit()),
-            )
-            .field(
-                "rx_afifo_empty",
-                &format_args!("{}", self.rx_afifo_empty().bit()),
-            )
+            .field("tx_afifo_full", &self.tx_afifo_full())
+            .field("tx_afifo_empty", &self.tx_afifo_empty())
+            .field("rx_afifo_full", &self.rx_afifo_full())
+            .field("rx_afifo_empty", &self.rx_afifo_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART AFIFO Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`afifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for AFIFO_STATUS_SPEC {
diff --git a/esp32c6/src/lp_uart/at_cmd_char.rs b/esp32c6/src/lp_uart/at_cmd_char.rs
index 17e9222fe8..e75e1409cd 100644
--- a/esp32c6/src/lp_uart/at_cmd_char.rs
+++ b/esp32c6/src/lp_uart/at_cmd_char.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_CHAR")
-            .field(
-                "at_cmd_char",
-                &format_args!("{}", self.at_cmd_char().bits()),
-            )
-            .field("char_num", &format_args!("{}", self.char_num().bits()))
+            .field("at_cmd_char", &self.at_cmd_char())
+            .field("char_num", &self.char_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_CHAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/at_cmd_gaptout.rs b/esp32c6/src/lp_uart/at_cmd_gaptout.rs
index c7373436b0..7091ac8125 100644
--- a/esp32c6/src/lp_uart/at_cmd_gaptout.rs
+++ b/esp32c6/src/lp_uart/at_cmd_gaptout.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_GAPTOUT")
-            .field(
-                "rx_gap_tout",
-                &format_args!("{}", self.rx_gap_tout().bits()),
-            )
+            .field("rx_gap_tout", &self.rx_gap_tout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_GAPTOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the at_cmd chars."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/at_cmd_postcnt.rs b/esp32c6/src/lp_uart/at_cmd_postcnt.rs
index 078c4bb6a1..5db8445554 100644
--- a/esp32c6/src/lp_uart/at_cmd_postcnt.rs
+++ b/esp32c6/src/lp_uart/at_cmd_postcnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_POSTCNT")
-            .field(
-                "post_idle_num",
-                &format_args!("{}", self.post_idle_num().bits()),
-            )
+            .field("post_idle_num", &self.post_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_POSTCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the last at_cmd and the next data."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/at_cmd_precnt.rs b/esp32c6/src/lp_uart/at_cmd_precnt.rs
index 9e4a1cc58c..41790b5e67 100644
--- a/esp32c6/src/lp_uart/at_cmd_precnt.rs
+++ b/esp32c6/src/lp_uart/at_cmd_precnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_PRECNT")
-            .field(
-                "pre_idle_num",
-                &format_args!("{}", self.pre_idle_num().bits()),
-            )
+            .field("pre_idle_num", &self.pre_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_PRECNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first at_cmd is received by receiver."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/clk_conf.rs b/esp32c6/src/lp_uart/clk_conf.rs
index f4d58f12dc..15db8ddbda 100644
--- a/esp32c6/src/lp_uart/clk_conf.rs
+++ b/esp32c6/src/lp_uart/clk_conf.rs
@@ -98,28 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bits()))
-            .field("sclk_en", &format_args!("{}", self.sclk_en().bit()))
-            .field("rst_core", &format_args!("{}", self.rst_core().bit()))
-            .field("tx_sclk_en", &format_args!("{}", self.tx_sclk_en().bit()))
-            .field("rx_sclk_en", &format_args!("{}", self.rx_sclk_en().bit()))
-            .field("tx_rst_core", &format_args!("{}", self.tx_rst_core().bit()))
-            .field("rx_rst_core", &format_args!("{}", self.rx_rst_core().bit()))
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_en", &self.sclk_en())
+            .field("rst_core", &self.rst_core())
+            .field("tx_sclk_en", &self.tx_sclk_en())
+            .field("rx_sclk_en", &self.rx_sclk_en())
+            .field("tx_rst_core", &self.tx_rst_core())
+            .field("rx_rst_core", &self.rx_rst_core())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/clkdiv.rs b/esp32c6/src/lp_uart/clkdiv.rs
index c020543f66..0c1138e013 100644
--- a/esp32c6/src/lp_uart/clkdiv.rs
+++ b/esp32c6/src/lp_uart/clkdiv.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKDIV")
-            .field("clkdiv", &format_args!("{}", self.clkdiv().bits()))
-            .field("frag", &format_args!("{}", self.frag().bits()))
+            .field("clkdiv", &self.clkdiv())
+            .field("frag", &self.frag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKDIV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/conf0.rs b/esp32c6/src/lp_uart/conf0.rs
index 38788d5d05..09fe2e37b7 100644
--- a/esp32c6/src/lp_uart/conf0.rs
+++ b/esp32c6/src/lp_uart/conf0.rs
@@ -143,36 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("parity", &format_args!("{}", self.parity().bit()))
-            .field("parity_en", &format_args!("{}", self.parity_en().bit()))
-            .field("bit_num", &format_args!("{}", self.bit_num().bits()))
-            .field(
-                "stop_bit_num",
-                &format_args!("{}", self.stop_bit_num().bits()),
-            )
-            .field("txd_brk", &format_args!("{}", self.txd_brk().bit()))
-            .field("loopback", &format_args!("{}", self.loopback().bit()))
-            .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit()))
-            .field("rxd_inv", &format_args!("{}", self.rxd_inv().bit()))
-            .field("txd_inv", &format_args!("{}", self.txd_inv().bit()))
-            .field(
-                "dis_rx_dat_ovf",
-                &format_args!("{}", self.dis_rx_dat_ovf().bit()),
-            )
-            .field("err_wr_mask", &format_args!("{}", self.err_wr_mask().bit()))
-            .field("mem_clk_en", &format_args!("{}", self.mem_clk_en().bit()))
-            .field("sw_rts", &format_args!("{}", self.sw_rts().bit()))
-            .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit()))
-            .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit()))
+            .field("parity", &self.parity())
+            .field("parity_en", &self.parity_en())
+            .field("bit_num", &self.bit_num())
+            .field("stop_bit_num", &self.stop_bit_num())
+            .field("txd_brk", &self.txd_brk())
+            .field("loopback", &self.loopback())
+            .field("tx_flow_en", &self.tx_flow_en())
+            .field("rxd_inv", &self.rxd_inv())
+            .field("txd_inv", &self.txd_inv())
+            .field("dis_rx_dat_ovf", &self.dis_rx_dat_ovf())
+            .field("err_wr_mask", &self.err_wr_mask())
+            .field("mem_clk_en", &self.mem_clk_en())
+            .field("sw_rts", &self.sw_rts())
+            .field("rxfifo_rst", &self.rxfifo_rst())
+            .field("txfifo_rst", &self.txfifo_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to configure the parity check mode."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/conf1.rs b/esp32c6/src/lp_uart/conf1.rs
index 1c6045b655..dfab209c1d 100644
--- a/esp32c6/src/lp_uart/conf1.rs
+++ b/esp32c6/src/lp_uart/conf1.rs
@@ -80,29 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "rxfifo_full_thrhd",
-                &format_args!("{}", self.rxfifo_full_thrhd().bits()),
-            )
-            .field(
-                "txfifo_empty_thrhd",
-                &format_args!("{}", self.txfifo_empty_thrhd().bits()),
-            )
-            .field("cts_inv", &format_args!("{}", self.cts_inv().bit()))
-            .field("dsr_inv", &format_args!("{}", self.dsr_inv().bit()))
-            .field("rts_inv", &format_args!("{}", self.rts_inv().bit()))
-            .field("dtr_inv", &format_args!("{}", self.dtr_inv().bit()))
-            .field("sw_dtr", &format_args!("{}", self.sw_dtr().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("rxfifo_full_thrhd", &self.rxfifo_full_thrhd())
+            .field("txfifo_empty_thrhd", &self.txfifo_empty_thrhd())
+            .field("cts_inv", &self.cts_inv())
+            .field("dsr_inv", &self.dsr_inv())
+            .field("rts_inv", &self.rts_inv())
+            .field("dtr_inv", &self.dtr_inv())
+            .field("sw_dtr", &self.sw_dtr())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:7 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/date.rs b/esp32c6/src/lp_uart/date.rs
index a81320d26c..6112a0fc83 100644
--- a/esp32c6/src/lp_uart/date.rs
+++ b/esp32c6/src/lp_uart/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/lp_uart/fifo.rs b/esp32c6/src/lp_uart/fifo.rs
index 3ea719e7ab..fdc9ee6700 100644
--- a/esp32c6/src/lp_uart/fifo.rs
+++ b/esp32c6/src/lp_uart/fifo.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO")
-            .field(
-                "rxfifo_rd_byte",
-                &format_args!("{}", self.rxfifo_rd_byte().bits()),
-            )
+            .field("rxfifo_rd_byte", &self.rxfifo_rd_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - UART 0 accesses FIFO via this register."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/fsm_status.rs b/esp32c6/src/lp_uart/fsm_status.rs
index 7e47b06bf6..4088ac153f 100644
--- a/esp32c6/src/lp_uart/fsm_status.rs
+++ b/esp32c6/src/lp_uart/fsm_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_STATUS")
-            .field("st_urx_out", &format_args!("{}", self.st_urx_out().bits()))
-            .field("st_utx_out", &format_args!("{}", self.st_utx_out().bits()))
+            .field("st_urx_out", &self.st_urx_out())
+            .field("st_utx_out", &self.st_utx_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART transmit and receive status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FSM_STATUS_SPEC;
 impl crate::RegisterSpec for FSM_STATUS_SPEC {
diff --git a/esp32c6/src/lp_uart/hwfc_conf.rs b/esp32c6/src/lp_uart/hwfc_conf.rs
index 457f38a167..4eef5ecaab 100644
--- a/esp32c6/src/lp_uart/hwfc_conf.rs
+++ b/esp32c6/src/lp_uart/hwfc_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HWFC_CONF")
-            .field(
-                "rx_flow_thrhd",
-                &format_args!("{}", self.rx_flow_thrhd().bits()),
-            )
-            .field("rx_flow_en", &format_args!("{}", self.rx_flow_en().bit()))
+            .field("rx_flow_thrhd", &self.rx_flow_thrhd())
+            .field("rx_flow_en", &self.rx_flow_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HWFC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:7 - This register is used to configure the maximum amount of data that can be received when hardware flow control works."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/id.rs b/esp32c6/src/lp_uart/id.rs
index 9c8cfa3a6b..670842afd9 100644
--- a/esp32c6/src/lp_uart/id.rs
+++ b/esp32c6/src/lp_uart/id.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("ID")
-            .field("id", &format_args!("{}", self.id().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("ID").field("id", &self.id()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/lp_uart/idle_conf.rs b/esp32c6/src/lp_uart/idle_conf.rs
index bc986732bf..a2f200e19e 100644
--- a/esp32c6/src/lp_uart/idle_conf.rs
+++ b/esp32c6/src/lp_uart/idle_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDLE_CONF")
-            .field(
-                "rx_idle_thrhd",
-                &format_args!("{}", self.rx_idle_thrhd().bits()),
-            )
-            .field(
-                "tx_idle_num",
-                &format_args!("{}", self.tx_idle_num().bits()),
-            )
+            .field("rx_idle_thrhd", &self.rx_idle_thrhd())
+            .field("tx_idle_num", &self.tx_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/int_ena.rs b/esp32c6/src/lp_uart/int_ena.rs
index 3d91b96662..ae4d6f4b24 100644
--- a/esp32c6/src/lp_uart/int_ena.rs
+++ b/esp32c6/src/lp_uart/int_ena.rs
@@ -161,41 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/int_raw.rs b/esp32c6/src/lp_uart/int_raw.rs
index dcfb481c5d..3e2b40190a 100644
--- a/esp32c6/src/lp_uart/int_raw.rs
+++ b/esp32c6/src/lp_uart/int_raw.rs
@@ -161,41 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/int_st.rs b/esp32c6/src/lp_uart/int_st.rs
index 82aaf89509..57e0dc3bd8 100644
--- a/esp32c6/src/lp_uart/int_st.rs
+++ b/esp32c6/src/lp_uart/int_st.rs
@@ -125,41 +125,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/lp_uart/mem_conf.rs b/esp32c6/src/lp_uart/mem_conf.rs
index 8c55da8b47..e930d52fc0 100644
--- a/esp32c6/src/lp_uart/mem_conf.rs
+++ b/esp32c6/src/lp_uart/mem_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - Set this bit to force power down UART memory."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/mem_rx_status.rs b/esp32c6/src/lp_uart/mem_rx_status.rs
index fafe24b358..d7b91a2cef 100644
--- a/esp32c6/src/lp_uart/mem_rx_status.rs
+++ b/esp32c6/src/lp_uart/mem_rx_status.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_RX_STATUS")
-            .field(
-                "rx_sram_raddr",
-                &format_args!("{}", self.rx_sram_raddr().bits()),
-            )
-            .field(
-                "rx_sram_waddr",
-                &format_args!("{}", self.rx_sram_waddr().bits()),
-            )
+            .field("rx_sram_raddr", &self.rx_sram_raddr())
+            .field("rx_sram_waddr", &self.rx_sram_waddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Rx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_RX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_RX_STATUS_SPEC {
diff --git a/esp32c6/src/lp_uart/mem_tx_status.rs b/esp32c6/src/lp_uart/mem_tx_status.rs
index 05d25d084e..1ad31fce44 100644
--- a/esp32c6/src/lp_uart/mem_tx_status.rs
+++ b/esp32c6/src/lp_uart/mem_tx_status.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_TX_STATUS")
-            .field(
-                "tx_sram_waddr",
-                &format_args!("{}", self.tx_sram_waddr().bits()),
-            )
-            .field(
-                "tx_sram_raddr",
-                &format_args!("{}", self.tx_sram_raddr().bits()),
-            )
+            .field("tx_sram_waddr", &self.tx_sram_waddr())
+            .field("tx_sram_raddr", &self.tx_sram_raddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Tx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_TX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_TX_STATUS_SPEC {
diff --git a/esp32c6/src/lp_uart/reg_update.rs b/esp32c6/src/lp_uart/reg_update.rs
index b2e4551f76..441e05815f 100644
--- a/esp32c6/src/lp_uart/reg_update.rs
+++ b/esp32c6/src/lp_uart/reg_update.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_UPDATE")
-            .field("reg_update", &format_args!("{}", self.reg_update().bit()))
+            .field("reg_update", &self.reg_update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/rs485_conf.rs b/esp32c6/src/lp_uart/rs485_conf.rs
index f8b0cba6c8..04bd61209f 100644
--- a/esp32c6/src/lp_uart/rs485_conf.rs
+++ b/esp32c6/src/lp_uart/rs485_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RS485_CONF")
-            .field("dl0_en", &format_args!("{}", self.dl0_en().bit()))
-            .field("dl1_en", &format_args!("{}", self.dl1_en().bit()))
+            .field("dl0_en", &self.dl0_en())
+            .field("dl1_en", &self.dl1_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RS485_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set this bit to delay the stop bit by 1 bit."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/rx_filt.rs b/esp32c6/src/lp_uart/rx_filt.rs
index c24c62977e..21576af0e9 100644
--- a/esp32c6/src/lp_uart/rx_filt.rs
+++ b/esp32c6/src/lp_uart/rx_filt.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_FILT")
-            .field(
-                "glitch_filt",
-                &format_args!("{}", self.glitch_filt().bits()),
-            )
-            .field(
-                "glitch_filt_en",
-                &format_args!("{}", self.glitch_filt_en().bit()),
-            )
+            .field("glitch_filt", &self.glitch_filt())
+            .field("glitch_filt_en", &self.glitch_filt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_FILT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - when input pulse width is lower than this value the pulse is ignored."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/sleep_conf0.rs b/esp32c6/src/lp_uart/sleep_conf0.rs
index 1c5c7f7eed..a8481a8783 100644
--- a/esp32c6/src/lp_uart/sleep_conf0.rs
+++ b/esp32c6/src/lp_uart/sleep_conf0.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF0")
-            .field("wk_char1", &format_args!("{}", self.wk_char1().bits()))
-            .field("wk_char2", &format_args!("{}", self.wk_char2().bits()))
-            .field("wk_char3", &format_args!("{}", self.wk_char3().bits()))
-            .field("wk_char4", &format_args!("{}", self.wk_char4().bits()))
+            .field("wk_char1", &self.wk_char1())
+            .field("wk_char2", &self.wk_char2())
+            .field("wk_char3", &self.wk_char3())
+            .field("wk_char4", &self.wk_char4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register restores the specified wake up char1 to wake up"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/sleep_conf1.rs b/esp32c6/src/lp_uart/sleep_conf1.rs
index f9f665a833..bf71699cf5 100644
--- a/esp32c6/src/lp_uart/sleep_conf1.rs
+++ b/esp32c6/src/lp_uart/sleep_conf1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF1")
-            .field("wk_char0", &format_args!("{}", self.wk_char0().bits()))
+            .field("wk_char0", &self.wk_char0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register restores the specified char0 to wake up"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/sleep_conf2.rs b/esp32c6/src/lp_uart/sleep_conf2.rs
index f2fdbaae7f..a32f4c66fd 100644
--- a/esp32c6/src/lp_uart/sleep_conf2.rs
+++ b/esp32c6/src/lp_uart/sleep_conf2.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF2")
-            .field(
-                "active_threshold",
-                &format_args!("{}", self.active_threshold().bits()),
-            )
-            .field(
-                "rx_wake_up_thrhd",
-                &format_args!("{}", self.rx_wake_up_thrhd().bits()),
-            )
-            .field(
-                "wk_char_num",
-                &format_args!("{}", self.wk_char_num().bits()),
-            )
-            .field(
-                "wk_char_mask",
-                &format_args!("{}", self.wk_char_mask().bits()),
-            )
-            .field(
-                "wk_mode_sel",
-                &format_args!("{}", self.wk_mode_sel().bits()),
-            )
+            .field("active_threshold", &self.active_threshold())
+            .field("rx_wake_up_thrhd", &self.rx_wake_up_thrhd())
+            .field("wk_char_num", &self.wk_char_num())
+            .field("wk_char_mask", &self.wk_char_mask())
+            .field("wk_mode_sel", &self.wk_mode_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/status.rs b/esp32c6/src/lp_uart/status.rs
index 50000e82e0..d25c3beb30 100644
--- a/esp32c6/src/lp_uart/status.rs
+++ b/esp32c6/src/lp_uart/status.rs
@@ -62,23 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("dsrn", &format_args!("{}", self.dsrn().bit()))
-            .field("ctsn", &format_args!("{}", self.ctsn().bit()))
-            .field("rxd", &format_args!("{}", self.rxd().bit()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field("dtrn", &format_args!("{}", self.dtrn().bit()))
-            .field("rtsn", &format_args!("{}", self.rtsn().bit()))
-            .field("txd", &format_args!("{}", self.txd().bit()))
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("dsrn", &self.dsrn())
+            .field("ctsn", &self.ctsn())
+            .field("rxd", &self.rxd())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("dtrn", &self.dtrn())
+            .field("rtsn", &self.rtsn())
+            .field("txd", &self.txd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32c6/src/lp_uart/swfc_conf0.rs b/esp32c6/src/lp_uart/swfc_conf0.rs
index 341967dafc..bbbea9d9e5 100644
--- a/esp32c6/src/lp_uart/swfc_conf0.rs
+++ b/esp32c6/src/lp_uart/swfc_conf0.rs
@@ -89,30 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF0")
-            .field("xon_char", &format_args!("{}", self.xon_char().bits()))
-            .field("xoff_char", &format_args!("{}", self.xoff_char().bits()))
-            .field(
-                "xon_xoff_still_send",
-                &format_args!("{}", self.xon_xoff_still_send().bit()),
-            )
-            .field(
-                "sw_flow_con_en",
-                &format_args!("{}", self.sw_flow_con_en().bit()),
-            )
-            .field("xonoff_del", &format_args!("{}", self.xonoff_del().bit()))
-            .field("force_xon", &format_args!("{}", self.force_xon().bit()))
-            .field("force_xoff", &format_args!("{}", self.force_xoff().bit()))
-            .field("send_xon", &format_args!("{}", self.send_xon().bit()))
-            .field("send_xoff", &format_args!("{}", self.send_xoff().bit()))
+            .field("xon_char", &self.xon_char())
+            .field("xoff_char", &self.xoff_char())
+            .field("xon_xoff_still_send", &self.xon_xoff_still_send())
+            .field("sw_flow_con_en", &self.sw_flow_con_en())
+            .field("xonoff_del", &self.xonoff_del())
+            .field("force_xon", &self.force_xon())
+            .field("force_xoff", &self.force_xoff())
+            .field("send_xon", &self.send_xon())
+            .field("send_xoff", &self.send_xoff())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register stores the Xon flow control char."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/swfc_conf1.rs b/esp32c6/src/lp_uart/swfc_conf1.rs
index 253a05d3c6..15050eecf9 100644
--- a/esp32c6/src/lp_uart/swfc_conf1.rs
+++ b/esp32c6/src/lp_uart/swfc_conf1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF1")
-            .field(
-                "xon_threshold",
-                &format_args!("{}", self.xon_threshold().bits()),
-            )
-            .field(
-                "xoff_threshold",
-                &format_args!("{}", self.xoff_threshold().bits()),
-            )
+            .field("xon_threshold", &self.xon_threshold())
+            .field("xoff_threshold", &self.xoff_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:7 - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/tout_conf.rs b/esp32c6/src/lp_uart/tout_conf.rs
index 92fe213cbb..908b3e6b17 100644
--- a/esp32c6/src/lp_uart/tout_conf.rs
+++ b/esp32c6/src/lp_uart/tout_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUT_CONF")
-            .field("rx_tout_en", &format_args!("{}", self.rx_tout_en().bit()))
-            .field(
-                "rx_tout_flow_dis",
-                &format_args!("{}", self.rx_tout_flow_dis().bit()),
-            )
-            .field(
-                "rx_tout_thrhd",
-                &format_args!("{}", self.rx_tout_thrhd().bits()),
-            )
+            .field("rx_tout_en", &self.rx_tout_en())
+            .field("rx_tout_flow_dis", &self.rx_tout_flow_dis())
+            .field("rx_tout_thrhd", &self.rx_tout_thrhd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enble bit for uart receiver's timeout function."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_uart/txbrk_conf.rs b/esp32c6/src/lp_uart/txbrk_conf.rs
index bfa2a9b911..65d37271c2 100644
--- a/esp32c6/src/lp_uart/txbrk_conf.rs
+++ b/esp32c6/src/lp_uart/txbrk_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXBRK_CONF")
-            .field("tx_brk_num", &format_args!("{}", self.tx_brk_num().bits()))
+            .field("tx_brk_num", &self.tx_brk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXBRK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."]
     #[inline(always)]
diff --git a/esp32c6/src/lp_wdt/config1.rs b/esp32c6/src/lp_wdt/config1.rs
index 5718bd36a7..cc20f95485 100644
--- a/esp32c6/src/lp_wdt/config1.rs
+++ b/esp32c6/src/lp_wdt/config1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG1")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_wdt/config2.rs b/esp32c6/src/lp_wdt/config2.rs
index a1ed774a2e..1208d49421 100644
--- a/esp32c6/src/lp_wdt/config2.rs
+++ b/esp32c6/src/lp_wdt/config2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG2")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_wdt/config3.rs b/esp32c6/src/lp_wdt/config3.rs
index 51d57fe8f9..41322e4dc9 100644
--- a/esp32c6/src/lp_wdt/config3.rs
+++ b/esp32c6/src/lp_wdt/config3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG3")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_wdt/config4.rs b/esp32c6/src/lp_wdt/config4.rs
index f0857186f5..efe8bb1a07 100644
--- a/esp32c6/src/lp_wdt/config4.rs
+++ b/esp32c6/src/lp_wdt/config4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG4")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_wdt/date.rs b/esp32c6/src/lp_wdt/date.rs
index ad999360f1..c4762f886a 100644
--- a/esp32c6/src/lp_wdt/date.rs
+++ b/esp32c6/src/lp_wdt/date.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "lp_wdt_date",
-                &format_args!("{}", self.lp_wdt_date().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("lp_wdt_date", &self.lp_wdt_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_wdt/int_ena.rs b/esp32c6/src/lp_wdt/int_ena.rs
index fb695587d4..e9dcd83f54 100644
--- a/esp32c6/src/lp_wdt/int_ena.rs
+++ b/esp32c6/src/lp_wdt/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("super_wdt", &format_args!("{}", self.super_wdt().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("super_wdt", &self.super_wdt())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_wdt/int_raw.rs b/esp32c6/src/lp_wdt/int_raw.rs
index c4f12e1d5e..fd7e3c5567 100644
--- a/esp32c6/src/lp_wdt/int_raw.rs
+++ b/esp32c6/src/lp_wdt/int_raw.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("super_wdt", &format_args!("{}", self.super_wdt().bit()))
-            .field("lp_wdt", &format_args!("{}", self.lp_wdt().bit()))
+            .field("super_wdt", &self.super_wdt())
+            .field("lp_wdt", &self.lp_wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_wdt/int_st.rs b/esp32c6/src/lp_wdt/int_st.rs
index 760d8cfb84..1f265e1b3d 100644
--- a/esp32c6/src/lp_wdt/int_st.rs
+++ b/esp32c6/src/lp_wdt/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("super_wdt", &format_args!("{}", self.super_wdt().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("super_wdt", &self.super_wdt())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/lp_wdt/swd_conf.rs b/esp32c6/src/lp_wdt/swd_conf.rs
index 4b4a276a30..233972cea9 100644
--- a/esp32c6/src/lp_wdt/swd_conf.rs
+++ b/esp32c6/src/lp_wdt/swd_conf.rs
@@ -46,28 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_CONF")
-            .field(
-                "swd_reset_flag",
-                &format_args!("{}", self.swd_reset_flag().bit()),
-            )
-            .field(
-                "swd_auto_feed_en",
-                &format_args!("{}", self.swd_auto_feed_en().bit()),
-            )
-            .field(
-                "swd_signal_width",
-                &format_args!("{}", self.swd_signal_width().bits()),
-            )
-            .field("swd_disable", &format_args!("{}", self.swd_disable().bit()))
+            .field("swd_reset_flag", &self.swd_reset_flag())
+            .field("swd_auto_feed_en", &self.swd_auto_feed_en())
+            .field("swd_signal_width", &self.swd_signal_width())
+            .field("swd_disable", &self.swd_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_wdt/swd_wprotect.rs b/esp32c6/src/lp_wdt/swd_wprotect.rs
index b3d6f51abb..38581d43f4 100644
--- a/esp32c6/src/lp_wdt/swd_wprotect.rs
+++ b/esp32c6/src/lp_wdt/swd_wprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_WPROTECT")
-            .field("swd_wkey", &format_args!("{}", self.swd_wkey().bits()))
+            .field("swd_wkey", &self.swd_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_WPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_wdt/wdtconfig0.rs b/esp32c6/src/lp_wdt/wdtconfig0.rs
index c7f7c520e5..278a5d82b2 100644
--- a/esp32c6/src/lp_wdt/wdtconfig0.rs
+++ b/esp32c6/src/lp_wdt/wdtconfig0.rs
@@ -125,52 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG0")
-            .field(
-                "wdt_chip_reset_width",
-                &format_args!("{}", self.wdt_chip_reset_width().bits()),
-            )
-            .field(
-                "wdt_chip_reset_en",
-                &format_args!("{}", self.wdt_chip_reset_en().bit()),
-            )
-            .field(
-                "wdt_pause_in_slp",
-                &format_args!("{}", self.wdt_pause_in_slp().bit()),
-            )
-            .field(
-                "wdt_appcpu_reset_en",
-                &format_args!("{}", self.wdt_appcpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_chip_reset_width", &self.wdt_chip_reset_width())
+            .field("wdt_chip_reset_en", &self.wdt_chip_reset_en())
+            .field("wdt_pause_in_slp", &self.wdt_pause_in_slp())
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/lp_wdt/wdtwprotect.rs b/esp32c6/src/lp_wdt/wdtwprotect.rs
index b71af238cf..51457307f2 100644
--- a/esp32c6/src/lp_wdt/wdtwprotect.rs
+++ b/esp32c6/src/lp_wdt/wdtwprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTWPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTWPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/cap_ch.rs b/esp32c6/src/mcpwm0/cap_ch.rs
index c65d337a76..ffa38ba07f 100644
--- a/esp32c6/src/mcpwm0/cap_ch.rs
+++ b/esp32c6/src/mcpwm0/cap_ch.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_CH")
-            .field("value", &format_args!("{}", self.value().bits()))
+            .field("value", &self.value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Value of last capture on channel %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_ch::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CAP_CH_SPEC;
 impl crate::RegisterSpec for CAP_CH_SPEC {
diff --git a/esp32c6/src/mcpwm0/cap_ch_cfg.rs b/esp32c6/src/mcpwm0/cap_ch_cfg.rs
index 625f867b5d..27980b8a1d 100644
--- a/esp32c6/src/mcpwm0/cap_ch_cfg.rs
+++ b/esp32c6/src/mcpwm0/cap_ch_cfg.rs
@@ -46,19 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_CH_CFG")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
-            .field("in_invert", &format_args!("{}", self.in_invert().bit()))
+            .field("en", &self.en())
+            .field("mode", &self.mode())
+            .field("prescale", &self.prescale())
+            .field("in_invert", &self.in_invert())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_CH_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, capture on channel 0 is enabled"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/cap_status.rs b/esp32c6/src/mcpwm0/cap_status.rs
index bc686ac57a..24aafdc56e 100644
--- a/esp32c6/src/mcpwm0/cap_status.rs
+++ b/esp32c6/src/mcpwm0/cap_status.rs
@@ -27,18 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_STATUS")
-            .field("cap0_edge", &format_args!("{}", self.cap0_edge().bit()))
-            .field("cap1_edge", &format_args!("{}", self.cap1_edge().bit()))
-            .field("cap2_edge", &format_args!("{}", self.cap2_edge().bit()))
+            .field("cap0_edge", &self.cap0_edge())
+            .field("cap1_edge", &self.cap1_edge())
+            .field("cap2_edge", &self.cap2_edge())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Edge of last capture trigger\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CAP_STATUS_SPEC;
 impl crate::RegisterSpec for CAP_STATUS_SPEC {
diff --git a/esp32c6/src/mcpwm0/cap_timer_cfg.rs b/esp32c6/src/mcpwm0/cap_timer_cfg.rs
index 81a189d50f..124d285e52 100644
--- a/esp32c6/src/mcpwm0/cap_timer_cfg.rs
+++ b/esp32c6/src/mcpwm0/cap_timer_cfg.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_TIMER_CFG")
-            .field(
-                "cap_timer_en",
-                &format_args!("{}", self.cap_timer_en().bit()),
-            )
-            .field(
-                "cap_synci_en",
-                &format_args!("{}", self.cap_synci_en().bit()),
-            )
-            .field(
-                "cap_synci_sel",
-                &format_args!("{}", self.cap_synci_sel().bits()),
-            )
+            .field("cap_timer_en", &self.cap_timer_en())
+            .field("cap_synci_en", &self.cap_synci_en())
+            .field("cap_synci_sel", &self.cap_synci_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_TIMER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, capture timer incrementing under APB_clk is enabled."]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/cap_timer_phase.rs b/esp32c6/src/mcpwm0/cap_timer_phase.rs
index c476ea129f..4a1f0aea4a 100644
--- a/esp32c6/src/mcpwm0/cap_timer_phase.rs
+++ b/esp32c6/src/mcpwm0/cap_timer_phase.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_TIMER_PHASE")
-            .field("cap_phase", &format_args!("{}", self.cap_phase().bits()))
+            .field("cap_phase", &self.cap_phase())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_TIMER_PHASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Phase value for capture timer sync operation."]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/ch/carrier_cfg.rs b/esp32c6/src/mcpwm0/ch/carrier_cfg.rs
index 52e906ba7a..1c7ffd7384 100644
--- a/esp32c6/src/mcpwm0/ch/carrier_cfg.rs
+++ b/esp32c6/src/mcpwm0/ch/carrier_cfg.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CARRIER_CFG")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
-            .field("duty", &format_args!("{}", self.duty().bits()))
-            .field("oshtwth", &format_args!("{}", self.oshtwth().bits()))
-            .field("out_invert", &format_args!("{}", self.out_invert().bit()))
-            .field("in_invert", &format_args!("{}", self.in_invert().bit()))
+            .field("en", &self.en())
+            .field("prescale", &self.prescale())
+            .field("duty", &self.duty())
+            .field("oshtwth", &self.oshtwth())
+            .field("out_invert", &self.out_invert())
+            .field("in_invert", &self.in_invert())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CARRIER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/ch/dt_cfg.rs b/esp32c6/src/mcpwm0/ch/dt_cfg.rs
index 1826d8ec55..9d677b5a64 100644
--- a/esp32c6/src/mcpwm0/ch/dt_cfg.rs
+++ b/esp32c6/src/mcpwm0/ch/dt_cfg.rs
@@ -116,39 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DT_CFG")
-            .field(
-                "fed_upmethod",
-                &format_args!("{}", self.fed_upmethod().bits()),
-            )
-            .field(
-                "red_upmethod",
-                &format_args!("{}", self.red_upmethod().bits()),
-            )
-            .field("deb_mode", &format_args!("{}", self.deb_mode().bit()))
-            .field("a_outswap", &format_args!("{}", self.a_outswap().bit()))
-            .field("b_outswap", &format_args!("{}", self.b_outswap().bit()))
-            .field("red_insel", &format_args!("{}", self.red_insel().bit()))
-            .field("fed_insel", &format_args!("{}", self.fed_insel().bit()))
-            .field(
-                "red_outinvert",
-                &format_args!("{}", self.red_outinvert().bit()),
-            )
-            .field(
-                "fed_outinvert",
-                &format_args!("{}", self.fed_outinvert().bit()),
-            )
-            .field("a_outbypass", &format_args!("{}", self.a_outbypass().bit()))
-            .field("b_outbypass", &format_args!("{}", self.b_outbypass().bit()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bit()))
+            .field("fed_upmethod", &self.fed_upmethod())
+            .field("red_upmethod", &self.red_upmethod())
+            .field("deb_mode", &self.deb_mode())
+            .field("a_outswap", &self.a_outswap())
+            .field("b_outswap", &self.b_outswap())
+            .field("red_insel", &self.red_insel())
+            .field("fed_insel", &self.fed_insel())
+            .field("red_outinvert", &self.red_outinvert())
+            .field("fed_outinvert", &self.fed_outinvert())
+            .field("a_outbypass", &self.a_outbypass())
+            .field("b_outbypass", &self.b_outbypass())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DT_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/ch/dt_fed_cfg.rs b/esp32c6/src/mcpwm0/ch/dt_fed_cfg.rs
index 32a5d442af..26a2a9235a 100644
--- a/esp32c6/src/mcpwm0/ch/dt_fed_cfg.rs
+++ b/esp32c6/src/mcpwm0/ch/dt_fed_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DT_FED_CFG")
-            .field("fed", &format_args!("{}", self.fed().bits()))
+            .field("fed", &self.fed())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DT_FED_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Shadow register for FED"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/ch/dt_red_cfg.rs b/esp32c6/src/mcpwm0/ch/dt_red_cfg.rs
index cbd50cd7b4..d2f4e5d496 100644
--- a/esp32c6/src/mcpwm0/ch/dt_red_cfg.rs
+++ b/esp32c6/src/mcpwm0/ch/dt_red_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DT_RED_CFG")
-            .field("red", &format_args!("{}", self.red().bits()))
+            .field("red", &self.red())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DT_RED_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Shadow register for RED"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/ch/fh_cfg0.rs b/esp32c6/src/mcpwm0/ch/fh_cfg0.rs
index 16bf20dc2c..32865deb0b 100644
--- a/esp32c6/src/mcpwm0/ch/fh_cfg0.rs
+++ b/esp32c6/src/mcpwm0/ch/fh_cfg0.rs
@@ -152,31 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FH_CFG0")
-            .field("sw_cbc", &format_args!("{}", self.sw_cbc().bit()))
-            .field("f2_cbc", &format_args!("{}", self.f2_cbc().bit()))
-            .field("f1_cbc", &format_args!("{}", self.f1_cbc().bit()))
-            .field("f0_cbc", &format_args!("{}", self.f0_cbc().bit()))
-            .field("sw_ost", &format_args!("{}", self.sw_ost().bit()))
-            .field("f2_ost", &format_args!("{}", self.f2_ost().bit()))
-            .field("f1_ost", &format_args!("{}", self.f1_ost().bit()))
-            .field("f0_ost", &format_args!("{}", self.f0_ost().bit()))
-            .field("a_cbc_d", &format_args!("{}", self.a_cbc_d().bits()))
-            .field("a_cbc_u", &format_args!("{}", self.a_cbc_u().bits()))
-            .field("a_ost_d", &format_args!("{}", self.a_ost_d().bits()))
-            .field("a_ost_u", &format_args!("{}", self.a_ost_u().bits()))
-            .field("b_cbc_d", &format_args!("{}", self.b_cbc_d().bits()))
-            .field("b_cbc_u", &format_args!("{}", self.b_cbc_u().bits()))
-            .field("b_ost_d", &format_args!("{}", self.b_ost_d().bits()))
-            .field("b_ost_u", &format_args!("{}", self.b_ost_u().bits()))
+            .field("sw_cbc", &self.sw_cbc())
+            .field("f2_cbc", &self.f2_cbc())
+            .field("f1_cbc", &self.f1_cbc())
+            .field("f0_cbc", &self.f0_cbc())
+            .field("sw_ost", &self.sw_ost())
+            .field("f2_ost", &self.f2_ost())
+            .field("f1_ost", &self.f1_ost())
+            .field("f0_ost", &self.f0_ost())
+            .field("a_cbc_d", &self.a_cbc_d())
+            .field("a_cbc_u", &self.a_cbc_u())
+            .field("a_ost_d", &self.a_ost_d())
+            .field("a_ost_u", &self.a_ost_u())
+            .field("b_cbc_d", &self.b_cbc_d())
+            .field("b_cbc_u", &self.b_cbc_u())
+            .field("b_ost_d", &self.b_ost_d())
+            .field("b_ost_u", &self.b_ost_u())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FH_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/ch/fh_cfg1.rs b/esp32c6/src/mcpwm0/ch/fh_cfg1.rs
index 01221dba64..422ad1a496 100644
--- a/esp32c6/src/mcpwm0/ch/fh_cfg1.rs
+++ b/esp32c6/src/mcpwm0/ch/fh_cfg1.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FH_CFG1")
-            .field("clr_ost", &format_args!("{}", self.clr_ost().bit()))
-            .field("cbcpulse", &format_args!("{}", self.cbcpulse().bits()))
-            .field("force_cbc", &format_args!("{}", self.force_cbc().bit()))
-            .field("force_ost", &format_args!("{}", self.force_ost().bit()))
+            .field("clr_ost", &self.clr_ost())
+            .field("cbcpulse", &self.cbcpulse())
+            .field("force_cbc", &self.force_cbc())
+            .field("force_ost", &self.force_ost())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FH_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - a rising edge will clear on going one-shot mode action"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/ch/fh_status.rs b/esp32c6/src/mcpwm0/ch/fh_status.rs
index 6c5fc8920f..5b2963a2e1 100644
--- a/esp32c6/src/mcpwm0/ch/fh_status.rs
+++ b/esp32c6/src/mcpwm0/ch/fh_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FH_STATUS")
-            .field("cbc_on", &format_args!("{}", self.cbc_on().bit()))
-            .field("ost_on", &format_args!("{}", self.ost_on().bit()))
+            .field("cbc_on", &self.cbc_on())
+            .field("ost_on", &self.ost_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FH_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of fault events.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FH_STATUS_SPEC;
 impl crate::RegisterSpec for FH_STATUS_SPEC {
diff --git a/esp32c6/src/mcpwm0/ch/gen.rs b/esp32c6/src/mcpwm0/ch/gen.rs
index 5d8addc59e..0d27bbd1b8 100644
--- a/esp32c6/src/mcpwm0/ch/gen.rs
+++ b/esp32c6/src/mcpwm0/ch/gen.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN")
-            .field("utez", &format_args!("{}", self.utez().bits()))
-            .field("utep", &format_args!("{}", self.utep().bits()))
-            .field("utea", &format_args!("{}", self.utea().bits()))
-            .field("uteb", &format_args!("{}", self.uteb().bits()))
-            .field("ut0", &format_args!("{}", self.ut0().bits()))
-            .field("ut1", &format_args!("{}", self.ut1().bits()))
-            .field("dtez", &format_args!("{}", self.dtez().bits()))
-            .field("dtep", &format_args!("{}", self.dtep().bits()))
-            .field("dtea", &format_args!("{}", self.dtea().bits()))
-            .field("dteb", &format_args!("{}", self.dteb().bits()))
-            .field("dt0", &format_args!("{}", self.dt0().bits()))
-            .field("dt1", &format_args!("{}", self.dt1().bits()))
+            .field("utez", &self.utez())
+            .field("utep", &self.utep())
+            .field("utea", &self.utea())
+            .field("uteb", &self.uteb())
+            .field("ut0", &self.ut0())
+            .field("ut1", &self.ut1())
+            .field("dtez", &self.dtez())
+            .field("dtep", &self.dtep())
+            .field("dtea", &self.dtea())
+            .field("dteb", &self.dteb())
+            .field("dt0", &self.dt0())
+            .field("dt1", &self.dt1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Action on PWM0A triggered by event TEZ when timer increasing"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/ch/gen_cfg0.rs b/esp32c6/src/mcpwm0/ch/gen_cfg0.rs
index 75032323fa..2f5827870c 100644
--- a/esp32c6/src/mcpwm0/ch/gen_cfg0.rs
+++ b/esp32c6/src/mcpwm0/ch/gen_cfg0.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_CFG0")
-            .field(
-                "cfg_upmethod",
-                &format_args!("{}", self.cfg_upmethod().bits()),
-            )
-            .field("t0_sel", &format_args!("{}", self.t0_sel().bits()))
-            .field("t1_sel", &format_args!("{}", self.t1_sel().bits()))
+            .field("cfg_upmethod", &self.cfg_upmethod())
+            .field("t0_sel", &self.t0_sel())
+            .field("t1_sel", &self.t1_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/ch/gen_force.rs b/esp32c6/src/mcpwm0/ch/gen_force.rs
index 3fcb77525c..a6a8be6844 100644
--- a/esp32c6/src/mcpwm0/ch/gen_force.rs
+++ b/esp32c6/src/mcpwm0/ch/gen_force.rs
@@ -71,37 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_FORCE")
-            .field(
-                "cntuforce_upmethod",
-                &format_args!("{}", self.cntuforce_upmethod().bits()),
-            )
-            .field(
-                "a_cntuforce_mode",
-                &format_args!("{}", self.a_cntuforce_mode().bits()),
-            )
-            .field(
-                "b_cntuforce_mode",
-                &format_args!("{}", self.b_cntuforce_mode().bits()),
-            )
-            .field("a_nciforce", &format_args!("{}", self.a_nciforce().bit()))
-            .field(
-                "a_nciforce_mode",
-                &format_args!("{}", self.a_nciforce_mode().bits()),
-            )
-            .field("b_nciforce", &format_args!("{}", self.b_nciforce().bit()))
-            .field(
-                "b_nciforce_mode",
-                &format_args!("{}", self.b_nciforce_mode().bits()),
-            )
+            .field("cntuforce_upmethod", &self.cntuforce_upmethod())
+            .field("a_cntuforce_mode", &self.a_cntuforce_mode())
+            .field("b_cntuforce_mode", &self.b_cntuforce_mode())
+            .field("a_nciforce", &self.a_nciforce())
+            .field("a_nciforce_mode", &self.a_nciforce_mode())
+            .field("b_nciforce", &self.b_nciforce())
+            .field("b_nciforce_mode", &self.b_nciforce_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_FORCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/ch/gen_stmp_cfg.rs b/esp32c6/src/mcpwm0/ch/gen_stmp_cfg.rs
index c8006017b2..29d78031d4 100644
--- a/esp32c6/src/mcpwm0/ch/gen_stmp_cfg.rs
+++ b/esp32c6/src/mcpwm0/ch/gen_stmp_cfg.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_STMP_CFG")
-            .field("a_upmethod", &format_args!("{}", self.a_upmethod().bits()))
-            .field("b_upmethod", &format_args!("{}", self.b_upmethod().bits()))
-            .field("a_shdw_full", &format_args!("{}", self.a_shdw_full().bit()))
-            .field("b_shdw_full", &format_args!("{}", self.b_shdw_full().bit()))
+            .field("a_upmethod", &self.a_upmethod())
+            .field("b_upmethod", &self.b_upmethod())
+            .field("a_shdw_full", &self.a_shdw_full())
+            .field("b_shdw_full", &self.b_shdw_full())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_STMP_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/ch/gen_tstmp_a.rs b/esp32c6/src/mcpwm0/ch/gen_tstmp_a.rs
index 1dd337661a..7fdbc1e7d1 100644
--- a/esp32c6/src/mcpwm0/ch/gen_tstmp_a.rs
+++ b/esp32c6/src/mcpwm0/ch/gen_tstmp_a.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("GEN_TSTMP_A")
-            .field("a", &format_args!("{}", self.a().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_TSTMP_A_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("GEN_TSTMP_A").field("a", &self.a()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/mcpwm0/ch/gen_tstmp_b.rs b/esp32c6/src/mcpwm0/ch/gen_tstmp_b.rs
index 1d128d47ed..6f8486d5a0 100644
--- a/esp32c6/src/mcpwm0/ch/gen_tstmp_b.rs
+++ b/esp32c6/src/mcpwm0/ch/gen_tstmp_b.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("GEN_TSTMP_B")
-            .field("b", &format_args!("{}", self.b().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_TSTMP_B_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("GEN_TSTMP_B").field("b", &self.b()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/mcpwm0/clk.rs b/esp32c6/src/mcpwm0/clk.rs
index 806dbb6cad..6df7d05643 100644
--- a/esp32c6/src/mcpwm0/clk.rs
+++ b/esp32c6/src/mcpwm0/clk.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CLK")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CLK").field("en", &self.en()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/mcpwm0/clk_cfg.rs b/esp32c6/src/mcpwm0/clk_cfg.rs
index 387991fe50..dfca5315ac 100644
--- a/esp32c6/src/mcpwm0/clk_cfg.rs
+++ b/esp32c6/src/mcpwm0/clk_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CFG")
-            .field(
-                "clk_prescale",
-                &format_args!("{}", self.clk_prescale().bits()),
-            )
+            .field("clk_prescale", &self.clk_prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/evt_en.rs b/esp32c6/src/mcpwm0/evt_en.rs
index e973be0d27..36a4aa698e 100644
--- a/esp32c6/src/mcpwm0/evt_en.rs
+++ b/esp32c6/src/mcpwm0/evt_en.rs
@@ -278,117 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVT_EN")
-            .field(
-                "evt_timer0_stop_en",
-                &format_args!("{}", self.evt_timer0_stop_en().bit()),
-            )
-            .field(
-                "evt_timer1_stop_en",
-                &format_args!("{}", self.evt_timer1_stop_en().bit()),
-            )
-            .field(
-                "evt_timer2_stop_en",
-                &format_args!("{}", self.evt_timer2_stop_en().bit()),
-            )
-            .field(
-                "evt_timer0_tez_en",
-                &format_args!("{}", self.evt_timer0_tez_en().bit()),
-            )
-            .field(
-                "evt_timer1_tez_en",
-                &format_args!("{}", self.evt_timer1_tez_en().bit()),
-            )
-            .field(
-                "evt_timer2_tez_en",
-                &format_args!("{}", self.evt_timer2_tez_en().bit()),
-            )
-            .field(
-                "evt_timer0_tep_en",
-                &format_args!("{}", self.evt_timer0_tep_en().bit()),
-            )
-            .field(
-                "evt_timer1_tep_en",
-                &format_args!("{}", self.evt_timer1_tep_en().bit()),
-            )
-            .field(
-                "evt_timer2_tep_en",
-                &format_args!("{}", self.evt_timer2_tep_en().bit()),
-            )
-            .field(
-                "evt_op0_tea_en",
-                &format_args!("{}", self.evt_op0_tea_en().bit()),
-            )
-            .field(
-                "evt_op1_tea_en",
-                &format_args!("{}", self.evt_op1_tea_en().bit()),
-            )
-            .field(
-                "evt_op2_tea_en",
-                &format_args!("{}", self.evt_op2_tea_en().bit()),
-            )
-            .field(
-                "evt_op0_teb_en",
-                &format_args!("{}", self.evt_op0_teb_en().bit()),
-            )
-            .field(
-                "evt_op1_teb_en",
-                &format_args!("{}", self.evt_op1_teb_en().bit()),
-            )
-            .field(
-                "evt_op2_teb_en",
-                &format_args!("{}", self.evt_op2_teb_en().bit()),
-            )
-            .field("evt_f0_en", &format_args!("{}", self.evt_f0_en().bit()))
-            .field("evt_f1_en", &format_args!("{}", self.evt_f1_en().bit()))
-            .field("evt_f2_en", &format_args!("{}", self.evt_f2_en().bit()))
-            .field(
-                "evt_f0_clr_en",
-                &format_args!("{}", self.evt_f0_clr_en().bit()),
-            )
-            .field(
-                "evt_f1_clr_en",
-                &format_args!("{}", self.evt_f1_clr_en().bit()),
-            )
-            .field(
-                "evt_f2_clr_en",
-                &format_args!("{}", self.evt_f2_clr_en().bit()),
-            )
-            .field(
-                "evt_tz0_cbc_en",
-                &format_args!("{}", self.evt_tz0_cbc_en().bit()),
-            )
-            .field(
-                "evt_tz1_cbc_en",
-                &format_args!("{}", self.evt_tz1_cbc_en().bit()),
-            )
-            .field(
-                "evt_tz2_cbc_en",
-                &format_args!("{}", self.evt_tz2_cbc_en().bit()),
-            )
-            .field(
-                "evt_tz0_ost_en",
-                &format_args!("{}", self.evt_tz0_ost_en().bit()),
-            )
-            .field(
-                "evt_tz1_ost_en",
-                &format_args!("{}", self.evt_tz1_ost_en().bit()),
-            )
-            .field(
-                "evt_tz2_ost_en",
-                &format_args!("{}", self.evt_tz2_ost_en().bit()),
-            )
-            .field("evt_cap0_en", &format_args!("{}", self.evt_cap0_en().bit()))
-            .field("evt_cap1_en", &format_args!("{}", self.evt_cap1_en().bit()))
-            .field("evt_cap2_en", &format_args!("{}", self.evt_cap2_en().bit()))
+            .field("evt_timer0_stop_en", &self.evt_timer0_stop_en())
+            .field("evt_timer1_stop_en", &self.evt_timer1_stop_en())
+            .field("evt_timer2_stop_en", &self.evt_timer2_stop_en())
+            .field("evt_timer0_tez_en", &self.evt_timer0_tez_en())
+            .field("evt_timer1_tez_en", &self.evt_timer1_tez_en())
+            .field("evt_timer2_tez_en", &self.evt_timer2_tez_en())
+            .field("evt_timer0_tep_en", &self.evt_timer0_tep_en())
+            .field("evt_timer1_tep_en", &self.evt_timer1_tep_en())
+            .field("evt_timer2_tep_en", &self.evt_timer2_tep_en())
+            .field("evt_op0_tea_en", &self.evt_op0_tea_en())
+            .field("evt_op1_tea_en", &self.evt_op1_tea_en())
+            .field("evt_op2_tea_en", &self.evt_op2_tea_en())
+            .field("evt_op0_teb_en", &self.evt_op0_teb_en())
+            .field("evt_op1_teb_en", &self.evt_op1_teb_en())
+            .field("evt_op2_teb_en", &self.evt_op2_teb_en())
+            .field("evt_f0_en", &self.evt_f0_en())
+            .field("evt_f1_en", &self.evt_f1_en())
+            .field("evt_f2_en", &self.evt_f2_en())
+            .field("evt_f0_clr_en", &self.evt_f0_clr_en())
+            .field("evt_f1_clr_en", &self.evt_f1_clr_en())
+            .field("evt_f2_clr_en", &self.evt_f2_clr_en())
+            .field("evt_tz0_cbc_en", &self.evt_tz0_cbc_en())
+            .field("evt_tz1_cbc_en", &self.evt_tz1_cbc_en())
+            .field("evt_tz2_cbc_en", &self.evt_tz2_cbc_en())
+            .field("evt_tz0_ost_en", &self.evt_tz0_ost_en())
+            .field("evt_tz1_ost_en", &self.evt_tz1_ost_en())
+            .field("evt_tz2_ost_en", &self.evt_tz2_ost_en())
+            .field("evt_cap0_en", &self.evt_cap0_en())
+            .field("evt_cap1_en", &self.evt_cap1_en())
+            .field("evt_cap2_en", &self.evt_cap2_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this bit high to enable timer0 stop event generate"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/fault_detect.rs b/esp32c6/src/mcpwm0/fault_detect.rs
index 52af954abd..1b5edb56d6 100644
--- a/esp32c6/src/mcpwm0/fault_detect.rs
+++ b/esp32c6/src/mcpwm0/fault_detect.rs
@@ -83,24 +83,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FAULT_DETECT")
-            .field("f0_en", &format_args!("{}", self.f0_en().bit()))
-            .field("f1_en", &format_args!("{}", self.f1_en().bit()))
-            .field("f2_en", &format_args!("{}", self.f2_en().bit()))
-            .field("f0_pole", &format_args!("{}", self.f0_pole().bit()))
-            .field("f1_pole", &format_args!("{}", self.f1_pole().bit()))
-            .field("f2_pole", &format_args!("{}", self.f2_pole().bit()))
-            .field("event_f0", &format_args!("{}", self.event_f0().bit()))
-            .field("event_f1", &format_args!("{}", self.event_f1().bit()))
-            .field("event_f2", &format_args!("{}", self.event_f2().bit()))
+            .field("f0_en", &self.f0_en())
+            .field("f1_en", &self.f1_en())
+            .field("f2_en", &self.f2_en())
+            .field("f0_pole", &self.f0_pole())
+            .field("f1_pole", &self.f1_pole())
+            .field("f2_pole", &self.f2_pole())
+            .field("event_f0", &self.event_f0())
+            .field("event_f1", &self.event_f1())
+            .field("event_f2", &self.event_f2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FAULT_DETECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, event_f0 generation is enabled"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/int_ena.rs b/esp32c6/src/mcpwm0/int_ena.rs
index 529d6f4a20..dab6312c95 100644
--- a/esp32c6/src/mcpwm0/int_ena.rs
+++ b/esp32c6/src/mcpwm0/int_ena.rs
@@ -278,45 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("fault0", &format_args!("{}", self.fault0().bit()))
-            .field("fault1", &format_args!("{}", self.fault1().bit()))
-            .field("fault2", &format_args!("{}", self.fault2().bit()))
-            .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
-            .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
-            .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
-            .field("cmpr0_tea", &format_args!("{}", self.cmpr0_tea().bit()))
-            .field("cmpr1_tea", &format_args!("{}", self.cmpr1_tea().bit()))
-            .field("cmpr2_tea", &format_args!("{}", self.cmpr2_tea().bit()))
-            .field("cmpr0_teb", &format_args!("{}", self.cmpr0_teb().bit()))
-            .field("cmpr1_teb", &format_args!("{}", self.cmpr1_teb().bit()))
-            .field("cmpr2_teb", &format_args!("{}", self.cmpr2_teb().bit()))
-            .field("tz0_cbc", &format_args!("{}", self.tz0_cbc().bit()))
-            .field("tz1_cbc", &format_args!("{}", self.tz1_cbc().bit()))
-            .field("tz2_cbc", &format_args!("{}", self.tz2_cbc().bit()))
-            .field("tz0_ost", &format_args!("{}", self.tz0_ost().bit()))
-            .field("tz1_ost", &format_args!("{}", self.tz1_ost().bit()))
-            .field("tz2_ost", &format_args!("{}", self.tz2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for the interrupt triggered when the timer 0 stops."]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/int_raw.rs b/esp32c6/src/mcpwm0/int_raw.rs
index b45523dcdc..447b1d86a2 100644
--- a/esp32c6/src/mcpwm0/int_raw.rs
+++ b/esp32c6/src/mcpwm0/int_raw.rs
@@ -278,45 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("fault0", &format_args!("{}", self.fault0().bit()))
-            .field("fault1", &format_args!("{}", self.fault1().bit()))
-            .field("fault2", &format_args!("{}", self.fault2().bit()))
-            .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
-            .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
-            .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
-            .field("cmpr0_tea", &format_args!("{}", self.cmpr0_tea().bit()))
-            .field("cmpr1_tea", &format_args!("{}", self.cmpr1_tea().bit()))
-            .field("cmpr2_tea", &format_args!("{}", self.cmpr2_tea().bit()))
-            .field("cmpr0_teb", &format_args!("{}", self.cmpr0_teb().bit()))
-            .field("cmpr1_teb", &format_args!("{}", self.cmpr1_teb().bit()))
-            .field("cmpr2_teb", &format_args!("{}", self.cmpr2_teb().bit()))
-            .field("tz0_cbc", &format_args!("{}", self.tz0_cbc().bit()))
-            .field("tz1_cbc", &format_args!("{}", self.tz1_cbc().bit()))
-            .field("tz2_cbc", &format_args!("{}", self.tz2_cbc().bit()))
-            .field("tz0_ost", &format_args!("{}", self.tz0_ost().bit()))
-            .field("tz1_ost", &format_args!("{}", self.tz1_ost().bit()))
-            .field("tz2_ost", &format_args!("{}", self.tz2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw status bit for the interrupt triggered when the timer 0 stops."]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/int_st.rs b/esp32c6/src/mcpwm0/int_st.rs
index 8627093497..dff68bd8dd 100644
--- a/esp32c6/src/mcpwm0/int_st.rs
+++ b/esp32c6/src/mcpwm0/int_st.rs
@@ -216,45 +216,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("fault0", &format_args!("{}", self.fault0().bit()))
-            .field("fault1", &format_args!("{}", self.fault1().bit()))
-            .field("fault2", &format_args!("{}", self.fault2().bit()))
-            .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
-            .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
-            .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
-            .field("cmpr0_tea", &format_args!("{}", self.cmpr0_tea().bit()))
-            .field("cmpr1_tea", &format_args!("{}", self.cmpr1_tea().bit()))
-            .field("cmpr2_tea", &format_args!("{}", self.cmpr2_tea().bit()))
-            .field("cmpr0_teb", &format_args!("{}", self.cmpr0_teb().bit()))
-            .field("cmpr1_teb", &format_args!("{}", self.cmpr1_teb().bit()))
-            .field("cmpr2_teb", &format_args!("{}", self.cmpr2_teb().bit()))
-            .field("tz0_cbc", &format_args!("{}", self.tz0_cbc().bit()))
-            .field("tz1_cbc", &format_args!("{}", self.tz1_cbc().bit()))
-            .field("tz2_cbc", &format_args!("{}", self.tz2_cbc().bit()))
-            .field("tz0_ost", &format_args!("{}", self.tz0_ost().bit()))
-            .field("tz1_ost", &format_args!("{}", self.tz1_ost().bit()))
-            .field("tz2_ost", &format_args!("{}", self.tz2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/mcpwm0/operator_timersel.rs b/esp32c6/src/mcpwm0/operator_timersel.rs
index a9fa9acb15..55e9d23758 100644
--- a/esp32c6/src/mcpwm0/operator_timersel.rs
+++ b/esp32c6/src/mcpwm0/operator_timersel.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OPERATOR_TIMERSEL")
-            .field(
-                "operator0_timersel",
-                &format_args!("{}", self.operator0_timersel().bits()),
-            )
-            .field(
-                "operator1_timersel",
-                &format_args!("{}", self.operator1_timersel().bits()),
-            )
-            .field(
-                "operator2_timersel",
-                &format_args!("{}", self.operator2_timersel().bits()),
-            )
+            .field("operator0_timersel", &self.operator0_timersel())
+            .field("operator1_timersel", &self.operator1_timersel())
+            .field("operator2_timersel", &self.operator2_timersel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OPERATOR_TIMERSEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/task_en.rs b/esp32c6/src/mcpwm0/task_en.rs
index ffc1f2e5a2..70561af014 100644
--- a/esp32c6/src/mcpwm0/task_en.rs
+++ b/esp32c6/src/mcpwm0/task_en.rs
@@ -206,103 +206,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TASK_EN")
-            .field(
-                "task_cmpr0_a_up_en",
-                &format_args!("{}", self.task_cmpr0_a_up_en().bit()),
-            )
-            .field(
-                "task_cmpr1_a_up_en",
-                &format_args!("{}", self.task_cmpr1_a_up_en().bit()),
-            )
-            .field(
-                "task_cmpr2_a_up_en",
-                &format_args!("{}", self.task_cmpr2_a_up_en().bit()),
-            )
-            .field(
-                "task_cmpr0_b_up_en",
-                &format_args!("{}", self.task_cmpr0_b_up_en().bit()),
-            )
-            .field(
-                "task_cmpr1_b_up_en",
-                &format_args!("{}", self.task_cmpr1_b_up_en().bit()),
-            )
-            .field(
-                "task_cmpr2_b_up_en",
-                &format_args!("{}", self.task_cmpr2_b_up_en().bit()),
-            )
-            .field(
-                "task_gen_stop_en",
-                &format_args!("{}", self.task_gen_stop_en().bit()),
-            )
-            .field(
-                "task_timer0_sync_en",
-                &format_args!("{}", self.task_timer0_sync_en().bit()),
-            )
-            .field(
-                "task_timer1_sync_en",
-                &format_args!("{}", self.task_timer1_sync_en().bit()),
-            )
-            .field(
-                "task_timer2_sync_en",
-                &format_args!("{}", self.task_timer2_sync_en().bit()),
-            )
-            .field(
-                "task_timer0_period_up_en",
-                &format_args!("{}", self.task_timer0_period_up_en().bit()),
-            )
-            .field(
-                "task_timer1_period_up_en",
-                &format_args!("{}", self.task_timer1_period_up_en().bit()),
-            )
-            .field(
-                "task_timer2_period_up_en",
-                &format_args!("{}", self.task_timer2_period_up_en().bit()),
-            )
-            .field(
-                "task_tz0_ost_en",
-                &format_args!("{}", self.task_tz0_ost_en().bit()),
-            )
-            .field(
-                "task_tz1_ost_en",
-                &format_args!("{}", self.task_tz1_ost_en().bit()),
-            )
-            .field(
-                "task_tz2_ost_en",
-                &format_args!("{}", self.task_tz2_ost_en().bit()),
-            )
-            .field(
-                "task_clr0_ost_en",
-                &format_args!("{}", self.task_clr0_ost_en().bit()),
-            )
-            .field(
-                "task_clr1_ost_en",
-                &format_args!("{}", self.task_clr1_ost_en().bit()),
-            )
-            .field(
-                "task_clr2_ost_en",
-                &format_args!("{}", self.task_clr2_ost_en().bit()),
-            )
-            .field(
-                "task_cap0_en",
-                &format_args!("{}", self.task_cap0_en().bit()),
-            )
-            .field(
-                "task_cap1_en",
-                &format_args!("{}", self.task_cap1_en().bit()),
-            )
-            .field(
-                "task_cap2_en",
-                &format_args!("{}", self.task_cap2_en().bit()),
-            )
+            .field("task_cmpr0_a_up_en", &self.task_cmpr0_a_up_en())
+            .field("task_cmpr1_a_up_en", &self.task_cmpr1_a_up_en())
+            .field("task_cmpr2_a_up_en", &self.task_cmpr2_a_up_en())
+            .field("task_cmpr0_b_up_en", &self.task_cmpr0_b_up_en())
+            .field("task_cmpr1_b_up_en", &self.task_cmpr1_b_up_en())
+            .field("task_cmpr2_b_up_en", &self.task_cmpr2_b_up_en())
+            .field("task_gen_stop_en", &self.task_gen_stop_en())
+            .field("task_timer0_sync_en", &self.task_timer0_sync_en())
+            .field("task_timer1_sync_en", &self.task_timer1_sync_en())
+            .field("task_timer2_sync_en", &self.task_timer2_sync_en())
+            .field("task_timer0_period_up_en", &self.task_timer0_period_up_en())
+            .field("task_timer1_period_up_en", &self.task_timer1_period_up_en())
+            .field("task_timer2_period_up_en", &self.task_timer2_period_up_en())
+            .field("task_tz0_ost_en", &self.task_tz0_ost_en())
+            .field("task_tz1_ost_en", &self.task_tz1_ost_en())
+            .field("task_tz2_ost_en", &self.task_tz2_ost_en())
+            .field("task_clr0_ost_en", &self.task_clr0_ost_en())
+            .field("task_clr1_ost_en", &self.task_clr1_ost_en())
+            .field("task_clr2_ost_en", &self.task_clr2_ost_en())
+            .field("task_cap0_en", &self.task_cap0_en())
+            .field("task_cap1_en", &self.task_cap1_en())
+            .field("task_cap2_en", &self.task_cap2_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TASK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this bit high to enable PWM generator0 timer stamp A's shadow register update task receive"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/timer/cfg0.rs b/esp32c6/src/mcpwm0/timer/cfg0.rs
index 904a515549..9fb25841a5 100644
--- a/esp32c6/src/mcpwm0/timer/cfg0.rs
+++ b/esp32c6/src/mcpwm0/timer/cfg0.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG0")
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
-            .field("period", &format_args!("{}", self.period().bits()))
-            .field(
-                "period_upmethod",
-                &format_args!("{}", self.period_upmethod().bits()),
-            )
+            .field("prescale", &self.prescale())
+            .field("period", &self.period())
+            .field("period_upmethod", &self.period_upmethod())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/timer/cfg1.rs b/esp32c6/src/mcpwm0/timer/cfg1.rs
index 086070d09e..92bed8f96a 100644
--- a/esp32c6/src/mcpwm0/timer/cfg1.rs
+++ b/esp32c6/src/mcpwm0/timer/cfg1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG1")
-            .field("start", &format_args!("{}", self.start().bits()))
-            .field("mod_", &format_args!("{}", self.mod_().bits()))
+            .field("start", &self.start())
+            .field("mod_", &self.mod_())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/timer/status.rs b/esp32c6/src/mcpwm0/timer/status.rs
index 576e1198f5..5dd843bac9 100644
--- a/esp32c6/src/mcpwm0/timer/status.rs
+++ b/esp32c6/src/mcpwm0/timer/status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("value", &format_args!("{}", self.value().bits()))
-            .field("direction", &format_args!("{}", self.direction().bit()))
+            .field("value", &self.value())
+            .field("direction", &self.direction())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "PWM TIMERx status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32c6/src/mcpwm0/timer/sync.rs b/esp32c6/src/mcpwm0/timer/sync.rs
index b629b45d15..b36d435ba9 100644
--- a/esp32c6/src/mcpwm0/timer/sync.rs
+++ b/esp32c6/src/mcpwm0/timer/sync.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYNC")
-            .field("synci_en", &format_args!("{}", self.synci_en().bit()))
-            .field("sw", &format_args!("{}", self.sw().bit()))
-            .field("synco_sel", &format_args!("{}", self.synco_sel().bits()))
-            .field("phase", &format_args!("{}", self.phase().bits()))
-            .field(
-                "phase_direction",
-                &format_args!("{}", self.phase_direction().bit()),
-            )
+            .field("synci_en", &self.synci_en())
+            .field("sw", &self.sw())
+            .field("synco_sel", &self.synco_sel())
+            .field("phase", &self.phase())
+            .field("phase_direction", &self.phase_direction())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, timer reloading with phase on sync input event is enabled."]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/timer_synci_cfg.rs b/esp32c6/src/mcpwm0/timer_synci_cfg.rs
index e532121427..2f7f399404 100644
--- a/esp32c6/src/mcpwm0/timer_synci_cfg.rs
+++ b/esp32c6/src/mcpwm0/timer_synci_cfg.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_SYNCI_CFG")
-            .field(
-                "timer0_syncisel",
-                &format_args!("{}", self.timer0_syncisel().bits()),
-            )
-            .field(
-                "timer1_syncisel",
-                &format_args!("{}", self.timer1_syncisel().bits()),
-            )
-            .field(
-                "timer2_syncisel",
-                &format_args!("{}", self.timer2_syncisel().bits()),
-            )
-            .field(
-                "external_synci0_invert",
-                &format_args!("{}", self.external_synci0_invert().bit()),
-            )
-            .field(
-                "external_synci1_invert",
-                &format_args!("{}", self.external_synci1_invert().bit()),
-            )
-            .field(
-                "external_synci2_invert",
-                &format_args!("{}", self.external_synci2_invert().bit()),
-            )
+            .field("timer0_syncisel", &self.timer0_syncisel())
+            .field("timer1_syncisel", &self.timer1_syncisel())
+            .field("timer2_syncisel", &self.timer2_syncisel())
+            .field("external_synci0_invert", &self.external_synci0_invert())
+            .field("external_synci1_invert", &self.external_synci1_invert())
+            .field("external_synci2_invert", &self.external_synci2_invert())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_SYNCI_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/update_cfg.rs b/esp32c6/src/mcpwm0/update_cfg.rs
index 07aa2a6a04..f5179c7fbc 100644
--- a/esp32c6/src/mcpwm0/update_cfg.rs
+++ b/esp32c6/src/mcpwm0/update_cfg.rs
@@ -80,38 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE_CFG")
-            .field(
-                "global_up_en",
-                &format_args!("{}", self.global_up_en().bit()),
-            )
-            .field(
-                "global_force_up",
-                &format_args!("{}", self.global_force_up().bit()),
-            )
-            .field("op0_up_en", &format_args!("{}", self.op0_up_en().bit()))
-            .field(
-                "op0_force_up",
-                &format_args!("{}", self.op0_force_up().bit()),
-            )
-            .field("op1_up_en", &format_args!("{}", self.op1_up_en().bit()))
-            .field(
-                "op1_force_up",
-                &format_args!("{}", self.op1_force_up().bit()),
-            )
-            .field("op2_up_en", &format_args!("{}", self.op2_up_en().bit()))
-            .field(
-                "op2_force_up",
-                &format_args!("{}", self.op2_force_up().bit()),
-            )
+            .field("global_up_en", &self.global_up_en())
+            .field("global_force_up", &self.global_force_up())
+            .field("op0_up_en", &self.op0_up_en())
+            .field("op0_force_up", &self.op0_force_up())
+            .field("op1_up_en", &self.op1_up_en())
+            .field("op1_force_up", &self.op1_force_up())
+            .field("op2_up_en", &self.op2_up_en())
+            .field("op2_force_up", &self.op2_force_up())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The global enable of update of all active registers in MCPWM module"]
     #[inline(always)]
diff --git a/esp32c6/src/mcpwm0/version.rs b/esp32c6/src/mcpwm0/version.rs
index b0efd350d5..aef0e5edd2 100644
--- a/esp32c6/src/mcpwm0/version.rs
+++ b/esp32c6/src/mcpwm0/version.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version of this register file"]
     #[inline(always)]
diff --git a/esp32c6/src/mem_monitor/clock_gate.rs b/esp32c6/src/mem_monitor/clock_gate.rs
index 41f38a3640..20414e3a4d 100644
--- a/esp32c6/src/mem_monitor/clock_gate.rs
+++ b/esp32c6/src/mem_monitor/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to force on the clk of mem_monitor register"]
     #[inline(always)]
diff --git a/esp32c6/src/mem_monitor/date.rs b/esp32c6/src/mem_monitor/date.rs
index 1790e90a70..2e5dbe01c7 100644
--- a/esp32c6/src/mem_monitor/date.rs
+++ b/esp32c6/src/mem_monitor/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/mem_monitor/log_check_data.rs b/esp32c6/src/mem_monitor/log_check_data.rs
index 4c387f085b..a0ec3bd836 100644
--- a/esp32c6/src/mem_monitor/log_check_data.rs
+++ b/esp32c6/src/mem_monitor/log_check_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_CHECK_DATA")
-            .field(
-                "log_check_data",
-                &format_args!("{}", self.log_check_data().bits()),
-            )
+            .field("log_check_data", &self.log_check_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_CHECK_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The special check data, when write this special data, it will trigger logging."]
     #[inline(always)]
diff --git a/esp32c6/src/mem_monitor/log_data_mask.rs b/esp32c6/src/mem_monitor/log_data_mask.rs
index 581d53ba4d..94cb25cd6e 100644
--- a/esp32c6/src/mem_monitor/log_data_mask.rs
+++ b/esp32c6/src/mem_monitor/log_data_mask.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_DATA_MASK")
-            .field(
-                "log_data_mask",
-                &format_args!("{}", self.log_data_mask().bits()),
-            )
+            .field("log_data_mask", &self.log_data_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_DATA_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 mask second byte, and so on."]
     #[inline(always)]
diff --git a/esp32c6/src/mem_monitor/log_max.rs b/esp32c6/src/mem_monitor/log_max.rs
index 4576677667..536c7de8c0 100644
--- a/esp32c6/src/mem_monitor/log_max.rs
+++ b/esp32c6/src/mem_monitor/log_max.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MAX")
-            .field("log_max", &format_args!("{}", self.log_max().bits()))
+            .field("log_max", &self.log_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - the max address of log range"]
     #[inline(always)]
diff --git a/esp32c6/src/mem_monitor/log_mem_current_addr.rs b/esp32c6/src/mem_monitor/log_mem_current_addr.rs
index 0b384d7203..4e8fa98fd0 100644
--- a/esp32c6/src/mem_monitor/log_mem_current_addr.rs
+++ b/esp32c6/src/mem_monitor/log_mem_current_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_CURRENT_ADDR")
-            .field(
-                "log_mem_current_addr",
-                &format_args!("{}", self.log_mem_current_addr().bits()),
-            )
+            .field("log_mem_current_addr", &self.log_mem_current_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_CURRENT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "current writing address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`log_mem_current_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOG_MEM_CURRENT_ADDR_SPEC;
 impl crate::RegisterSpec for LOG_MEM_CURRENT_ADDR_SPEC {
diff --git a/esp32c6/src/mem_monitor/log_mem_end.rs b/esp32c6/src/mem_monitor/log_mem_end.rs
index db04d1a955..d19a4b9b47 100644
--- a/esp32c6/src/mem_monitor/log_mem_end.rs
+++ b/esp32c6/src/mem_monitor/log_mem_end.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_END")
-            .field(
-                "log_mem_end",
-                &format_args!("{}", self.log_mem_end().bits()),
-            )
+            .field("log_mem_end", &self.log_mem_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_END_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - the end address of writing logging message"]
     #[inline(always)]
diff --git a/esp32c6/src/mem_monitor/log_mem_full_flag.rs b/esp32c6/src/mem_monitor/log_mem_full_flag.rs
index a9067171cf..32eac4e396 100644
--- a/esp32c6/src/mem_monitor/log_mem_full_flag.rs
+++ b/esp32c6/src/mem_monitor/log_mem_full_flag.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_FULL_FLAG")
-            .field(
-                "log_mem_full_flag",
-                &format_args!("{}", self.log_mem_full_flag().bit()),
-            )
+            .field("log_mem_full_flag", &self.log_mem_full_flag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_FULL_FLAG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG"]
     #[inline(always)]
diff --git a/esp32c6/src/mem_monitor/log_mem_start.rs b/esp32c6/src/mem_monitor/log_mem_start.rs
index 41cb69417b..80997cea12 100644
--- a/esp32c6/src/mem_monitor/log_mem_start.rs
+++ b/esp32c6/src/mem_monitor/log_mem_start.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_START")
-            .field(
-                "log_mem_start",
-                &format_args!("{}", self.log_mem_start().bits()),
-            )
+            .field("log_mem_start", &self.log_mem_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_START_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - the start address of writing logging message"]
     #[inline(always)]
diff --git a/esp32c6/src/mem_monitor/log_min.rs b/esp32c6/src/mem_monitor/log_min.rs
index 4c4a2fc050..cd8bed7509 100644
--- a/esp32c6/src/mem_monitor/log_min.rs
+++ b/esp32c6/src/mem_monitor/log_min.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MIN")
-            .field("log_min", &format_args!("{}", self.log_min().bits()))
+            .field("log_min", &self.log_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - the min address of log range"]
     #[inline(always)]
diff --git a/esp32c6/src/mem_monitor/log_setting.rs b/esp32c6/src/mem_monitor/log_setting.rs
index 18960f1521..905347aa2c 100644
--- a/esp32c6/src/mem_monitor/log_setting.rs
+++ b/esp32c6/src/mem_monitor/log_setting.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_SETTING")
-            .field("log_ena", &format_args!("{}", self.log_ena().bits()))
-            .field("log_mode", &format_args!("{}", self.log_mode().bits()))
-            .field(
-                "log_mem_loop_enable",
-                &format_args!("{}", self.log_mem_loop_enable().bit()),
-            )
+            .field("log_ena", &self.log_ena())
+            .field("log_mode", &self.log_mode())
+            .field("log_mem_loop_enable", &self.log_mem_loop_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_SETTING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA."]
     #[inline(always)]
diff --git a/esp32c6/src/modem_lpcon/clk_conf.rs b/esp32c6/src/modem_lpcon/clk_conf.rs
index 7b12613402..1141466e64 100644
--- a/esp32c6/src/modem_lpcon/clk_conf.rs
+++ b/esp32c6/src/modem_lpcon/clk_conf.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field(
-                "clk_wifipwr_en",
-                &format_args!("{}", self.clk_wifipwr_en().bit()),
-            )
-            .field("clk_coex_en", &format_args!("{}", self.clk_coex_en().bit()))
-            .field(
-                "clk_i2c_mst_en",
-                &format_args!("{}", self.clk_i2c_mst_en().bit()),
-            )
-            .field(
-                "clk_lp_timer_en",
-                &format_args!("{}", self.clk_lp_timer_en().bit()),
-            )
+            .field("clk_wifipwr_en", &self.clk_wifipwr_en())
+            .field("clk_coex_en", &self.clk_coex_en())
+            .field("clk_i2c_mst_en", &self.clk_i2c_mst_en())
+            .field("clk_lp_timer_en", &self.clk_lp_timer_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_lpcon/clk_conf_force_on.rs b/esp32c6/src/modem_lpcon/clk_conf_force_on.rs
index 9b5dc7c931..d6da636070 100644
--- a/esp32c6/src/modem_lpcon/clk_conf_force_on.rs
+++ b/esp32c6/src/modem_lpcon/clk_conf_force_on.rs
@@ -98,52 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF_FORCE_ON")
-            .field(
-                "clk_wifipwr_fo",
-                &format_args!("{}", self.clk_wifipwr_fo().bit()),
-            )
-            .field("clk_coex_fo", &format_args!("{}", self.clk_coex_fo().bit()))
-            .field(
-                "clk_i2c_mst_fo",
-                &format_args!("{}", self.clk_i2c_mst_fo().bit()),
-            )
-            .field(
-                "clk_lp_timer_fo",
-                &format_args!("{}", self.clk_lp_timer_fo().bit()),
-            )
-            .field(
-                "clk_bcmem_fo",
-                &format_args!("{}", self.clk_bcmem_fo().bit()),
-            )
-            .field(
-                "clk_i2c_mst_mem_fo",
-                &format_args!("{}", self.clk_i2c_mst_mem_fo().bit()),
-            )
-            .field(
-                "clk_chan_freq_mem_fo",
-                &format_args!("{}", self.clk_chan_freq_mem_fo().bit()),
-            )
-            .field(
-                "clk_pbus_mem_fo",
-                &format_args!("{}", self.clk_pbus_mem_fo().bit()),
-            )
-            .field(
-                "clk_agc_mem_fo",
-                &format_args!("{}", self.clk_agc_mem_fo().bit()),
-            )
-            .field(
-                "clk_dc_mem_fo",
-                &format_args!("{}", self.clk_dc_mem_fo().bit()),
-            )
+            .field("clk_wifipwr_fo", &self.clk_wifipwr_fo())
+            .field("clk_coex_fo", &self.clk_coex_fo())
+            .field("clk_i2c_mst_fo", &self.clk_i2c_mst_fo())
+            .field("clk_lp_timer_fo", &self.clk_lp_timer_fo())
+            .field("clk_bcmem_fo", &self.clk_bcmem_fo())
+            .field("clk_i2c_mst_mem_fo", &self.clk_i2c_mst_mem_fo())
+            .field("clk_chan_freq_mem_fo", &self.clk_chan_freq_mem_fo())
+            .field("clk_pbus_mem_fo", &self.clk_pbus_mem_fo())
+            .field("clk_agc_mem_fo", &self.clk_agc_mem_fo())
+            .field("clk_dc_mem_fo", &self.clk_dc_mem_fo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_FORCE_ON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_lpcon/clk_conf_power_st.rs b/esp32c6/src/modem_lpcon/clk_conf_power_st.rs
index 7d391c55bc..ebeef15eb2 100644
--- a/esp32c6/src/modem_lpcon/clk_conf_power_st.rs
+++ b/esp32c6/src/modem_lpcon/clk_conf_power_st.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF_POWER_ST")
-            .field(
-                "clk_wifipwr_st_map",
-                &format_args!("{}", self.clk_wifipwr_st_map().bits()),
-            )
-            .field(
-                "clk_coex_st_map",
-                &format_args!("{}", self.clk_coex_st_map().bits()),
-            )
-            .field(
-                "clk_i2c_mst_st_map",
-                &format_args!("{}", self.clk_i2c_mst_st_map().bits()),
-            )
-            .field(
-                "clk_lp_apb_st_map",
-                &format_args!("{}", self.clk_lp_apb_st_map().bits()),
-            )
+            .field("clk_wifipwr_st_map", &self.clk_wifipwr_st_map())
+            .field("clk_coex_st_map", &self.clk_coex_st_map())
+            .field("clk_i2c_mst_st_map", &self.clk_i2c_mst_st_map())
+            .field("clk_lp_apb_st_map", &self.clk_lp_apb_st_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_POWER_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:19"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_lpcon/coex_lp_clk_conf.rs b/esp32c6/src/modem_lpcon/coex_lp_clk_conf.rs
index bc48d3f96a..2f600a7b43 100644
--- a/esp32c6/src/modem_lpcon/coex_lp_clk_conf.rs
+++ b/esp32c6/src/modem_lpcon/coex_lp_clk_conf.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COEX_LP_CLK_CONF")
-            .field(
-                "clk_coex_lp_sel_osc_slow",
-                &format_args!("{}", self.clk_coex_lp_sel_osc_slow().bit()),
-            )
-            .field(
-                "clk_coex_lp_sel_osc_fast",
-                &format_args!("{}", self.clk_coex_lp_sel_osc_fast().bit()),
-            )
-            .field(
-                "clk_coex_lp_sel_xtal",
-                &format_args!("{}", self.clk_coex_lp_sel_xtal().bit()),
-            )
-            .field(
-                "clk_coex_lp_sel_xtal32k",
-                &format_args!("{}", self.clk_coex_lp_sel_xtal32k().bit()),
-            )
-            .field(
-                "clk_coex_lp_div_num",
-                &format_args!("{}", self.clk_coex_lp_div_num().bits()),
-            )
+            .field("clk_coex_lp_sel_osc_slow", &self.clk_coex_lp_sel_osc_slow())
+            .field("clk_coex_lp_sel_osc_fast", &self.clk_coex_lp_sel_osc_fast())
+            .field("clk_coex_lp_sel_xtal", &self.clk_coex_lp_sel_xtal())
+            .field("clk_coex_lp_sel_xtal32k", &self.clk_coex_lp_sel_xtal32k())
+            .field("clk_coex_lp_div_num", &self.clk_coex_lp_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COEX_LP_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_lpcon/date.rs b/esp32c6/src/modem_lpcon/date.rs
index df761d3d48..ed6ba85a53 100644
--- a/esp32c6/src/modem_lpcon/date.rs
+++ b/esp32c6/src/modem_lpcon/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/modem_lpcon/i2c_mst_clk_conf.rs b/esp32c6/src/modem_lpcon/i2c_mst_clk_conf.rs
index 15358053a5..3354f9134a 100644
--- a/esp32c6/src/modem_lpcon/i2c_mst_clk_conf.rs
+++ b/esp32c6/src/modem_lpcon/i2c_mst_clk_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_MST_CLK_CONF")
-            .field(
-                "clk_i2c_mst_sel_160m",
-                &format_args!("{}", self.clk_i2c_mst_sel_160m().bit()),
-            )
+            .field("clk_i2c_mst_sel_160m", &self.clk_i2c_mst_sel_160m())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_MST_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_lpcon/lp_timer_conf.rs b/esp32c6/src/modem_lpcon/lp_timer_conf.rs
index c9a95dfe2f..6bfae10ed9 100644
--- a/esp32c6/src/modem_lpcon/lp_timer_conf.rs
+++ b/esp32c6/src/modem_lpcon/lp_timer_conf.rs
@@ -55,33 +55,18 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_TIMER_CONF")
             .field(
                 "clk_lp_timer_sel_osc_slow",
-                &format_args!("{}", self.clk_lp_timer_sel_osc_slow().bit()),
+                &self.clk_lp_timer_sel_osc_slow(),
             )
             .field(
                 "clk_lp_timer_sel_osc_fast",
-                &format_args!("{}", self.clk_lp_timer_sel_osc_fast().bit()),
-            )
-            .field(
-                "clk_lp_timer_sel_xtal",
-                &format_args!("{}", self.clk_lp_timer_sel_xtal().bit()),
-            )
-            .field(
-                "clk_lp_timer_sel_xtal32k",
-                &format_args!("{}", self.clk_lp_timer_sel_xtal32k().bit()),
-            )
-            .field(
-                "clk_lp_timer_div_num",
-                &format_args!("{}", self.clk_lp_timer_div_num().bits()),
+                &self.clk_lp_timer_sel_osc_fast(),
             )
+            .field("clk_lp_timer_sel_xtal", &self.clk_lp_timer_sel_xtal())
+            .field("clk_lp_timer_sel_xtal32k", &self.clk_lp_timer_sel_xtal32k())
+            .field("clk_lp_timer_div_num", &self.clk_lp_timer_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TIMER_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_lpcon/mem_conf.rs b/esp32c6/src/modem_lpcon/mem_conf.rs
index 4e86e73a86..d81180021e 100644
--- a/esp32c6/src/modem_lpcon/mem_conf.rs
+++ b/esp32c6/src/modem_lpcon/mem_conf.rs
@@ -143,75 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field(
-                "dc_mem_force_pu",
-                &format_args!("{}", self.dc_mem_force_pu().bit()),
-            )
-            .field(
-                "dc_mem_force_pd",
-                &format_args!("{}", self.dc_mem_force_pd().bit()),
-            )
-            .field(
-                "agc_mem_force_pu",
-                &format_args!("{}", self.agc_mem_force_pu().bit()),
-            )
-            .field(
-                "agc_mem_force_pd",
-                &format_args!("{}", self.agc_mem_force_pd().bit()),
-            )
-            .field(
-                "pbus_mem_force_pu",
-                &format_args!("{}", self.pbus_mem_force_pu().bit()),
-            )
-            .field(
-                "pbus_mem_force_pd",
-                &format_args!("{}", self.pbus_mem_force_pd().bit()),
-            )
-            .field(
-                "bc_mem_force_pu",
-                &format_args!("{}", self.bc_mem_force_pu().bit()),
-            )
-            .field(
-                "bc_mem_force_pd",
-                &format_args!("{}", self.bc_mem_force_pd().bit()),
-            )
-            .field(
-                "i2c_mst_mem_force_pu",
-                &format_args!("{}", self.i2c_mst_mem_force_pu().bit()),
-            )
-            .field(
-                "i2c_mst_mem_force_pd",
-                &format_args!("{}", self.i2c_mst_mem_force_pd().bit()),
-            )
-            .field(
-                "chan_freq_mem_force_pu",
-                &format_args!("{}", self.chan_freq_mem_force_pu().bit()),
-            )
-            .field(
-                "chan_freq_mem_force_pd",
-                &format_args!("{}", self.chan_freq_mem_force_pd().bit()),
-            )
-            .field(
-                "modem_pwr_mem_wp",
-                &format_args!("{}", self.modem_pwr_mem_wp().bits()),
-            )
-            .field(
-                "modem_pwr_mem_wa",
-                &format_args!("{}", self.modem_pwr_mem_wa().bits()),
-            )
-            .field(
-                "modem_pwr_mem_ra",
-                &format_args!("{}", self.modem_pwr_mem_ra().bits()),
-            )
+            .field("dc_mem_force_pu", &self.dc_mem_force_pu())
+            .field("dc_mem_force_pd", &self.dc_mem_force_pd())
+            .field("agc_mem_force_pu", &self.agc_mem_force_pu())
+            .field("agc_mem_force_pd", &self.agc_mem_force_pd())
+            .field("pbus_mem_force_pu", &self.pbus_mem_force_pu())
+            .field("pbus_mem_force_pd", &self.pbus_mem_force_pd())
+            .field("bc_mem_force_pu", &self.bc_mem_force_pu())
+            .field("bc_mem_force_pd", &self.bc_mem_force_pd())
+            .field("i2c_mst_mem_force_pu", &self.i2c_mst_mem_force_pu())
+            .field("i2c_mst_mem_force_pd", &self.i2c_mst_mem_force_pd())
+            .field("chan_freq_mem_force_pu", &self.chan_freq_mem_force_pu())
+            .field("chan_freq_mem_force_pd", &self.chan_freq_mem_force_pd())
+            .field("modem_pwr_mem_wp", &self.modem_pwr_mem_wp())
+            .field("modem_pwr_mem_wa", &self.modem_pwr_mem_wa())
+            .field("modem_pwr_mem_ra", &self.modem_pwr_mem_ra())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_lpcon/modem_32k_clk_conf.rs b/esp32c6/src/modem_lpcon/modem_32k_clk_conf.rs
index c6717fd858..05375f7493 100644
--- a/esp32c6/src/modem_lpcon/modem_32k_clk_conf.rs
+++ b/esp32c6/src/modem_lpcon/modem_32k_clk_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODEM_32K_CLK_CONF")
-            .field(
-                "clk_modem_32k_sel",
-                &format_args!("{}", self.clk_modem_32k_sel().bits()),
-            )
+            .field("clk_modem_32k_sel", &self.clk_modem_32k_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODEM_32K_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_lpcon/test_conf.rs b/esp32c6/src/modem_lpcon/test_conf.rs
index 8c6131e811..e4ff365587 100644
--- a/esp32c6/src/modem_lpcon/test_conf.rs
+++ b/esp32c6/src/modem_lpcon/test_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEST_CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "clk_debug_ena",
-                &format_args!("{}", self.clk_debug_ena().bit()),
-            )
+            .field("clk_en", &self.clk_en())
+            .field("clk_debug_ena", &self.clk_debug_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_lpcon/wifi_lp_clk_conf.rs b/esp32c6/src/modem_lpcon/wifi_lp_clk_conf.rs
index 19d3071cd6..af4f9f7581 100644
--- a/esp32c6/src/modem_lpcon/wifi_lp_clk_conf.rs
+++ b/esp32c6/src/modem_lpcon/wifi_lp_clk_conf.rs
@@ -55,33 +55,21 @@ impl core::fmt::Debug for R {
         f.debug_struct("WIFI_LP_CLK_CONF")
             .field(
                 "clk_wifipwr_lp_sel_osc_slow",
-                &format_args!("{}", self.clk_wifipwr_lp_sel_osc_slow().bit()),
+                &self.clk_wifipwr_lp_sel_osc_slow(),
             )
             .field(
                 "clk_wifipwr_lp_sel_osc_fast",
-                &format_args!("{}", self.clk_wifipwr_lp_sel_osc_fast().bit()),
-            )
-            .field(
-                "clk_wifipwr_lp_sel_xtal",
-                &format_args!("{}", self.clk_wifipwr_lp_sel_xtal().bit()),
+                &self.clk_wifipwr_lp_sel_osc_fast(),
             )
+            .field("clk_wifipwr_lp_sel_xtal", &self.clk_wifipwr_lp_sel_xtal())
             .field(
                 "clk_wifipwr_lp_sel_xtal32k",
-                &format_args!("{}", self.clk_wifipwr_lp_sel_xtal32k().bit()),
-            )
-            .field(
-                "clk_wifipwr_lp_div_num",
-                &format_args!("{}", self.clk_wifipwr_lp_div_num().bits()),
+                &self.clk_wifipwr_lp_sel_xtal32k(),
             )
+            .field("clk_wifipwr_lp_div_num", &self.clk_wifipwr_lp_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_LP_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_syscon/clk_conf.rs b/esp32c6/src/modem_syscon/clk_conf.rs
index 4cd4b25607..67a7bcba5f 100644
--- a/esp32c6/src/modem_syscon/clk_conf.rs
+++ b/esp32c6/src/modem_syscon/clk_conf.rs
@@ -107,56 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field(
-                "clk_data_dump_mux",
-                &format_args!("{}", self.clk_data_dump_mux().bit()),
-            )
-            .field("clk_etm_en", &format_args!("{}", self.clk_etm_en().bit()))
-            .field(
-                "clk_zb_apb_en",
-                &format_args!("{}", self.clk_zb_apb_en().bit()),
-            )
-            .field(
-                "clk_zb_mac_en",
-                &format_args!("{}", self.clk_zb_mac_en().bit()),
-            )
-            .field(
-                "clk_modem_sec_ecb_en",
-                &format_args!("{}", self.clk_modem_sec_ecb_en().bit()),
-            )
-            .field(
-                "clk_modem_sec_ccm_en",
-                &format_args!("{}", self.clk_modem_sec_ccm_en().bit()),
-            )
-            .field(
-                "clk_modem_sec_bah_en",
-                &format_args!("{}", self.clk_modem_sec_bah_en().bit()),
-            )
-            .field(
-                "clk_modem_sec_apb_en",
-                &format_args!("{}", self.clk_modem_sec_apb_en().bit()),
-            )
-            .field(
-                "clk_modem_sec_en",
-                &format_args!("{}", self.clk_modem_sec_en().bit()),
-            )
-            .field(
-                "clk_ble_timer_en",
-                &format_args!("{}", self.clk_ble_timer_en().bit()),
-            )
-            .field(
-                "clk_data_dump_en",
-                &format_args!("{}", self.clk_data_dump_en().bit()),
-            )
+            .field("clk_data_dump_mux", &self.clk_data_dump_mux())
+            .field("clk_etm_en", &self.clk_etm_en())
+            .field("clk_zb_apb_en", &self.clk_zb_apb_en())
+            .field("clk_zb_mac_en", &self.clk_zb_mac_en())
+            .field("clk_modem_sec_ecb_en", &self.clk_modem_sec_ecb_en())
+            .field("clk_modem_sec_ccm_en", &self.clk_modem_sec_ccm_en())
+            .field("clk_modem_sec_bah_en", &self.clk_modem_sec_bah_en())
+            .field("clk_modem_sec_apb_en", &self.clk_modem_sec_apb_en())
+            .field("clk_modem_sec_en", &self.clk_modem_sec_en())
+            .field("clk_ble_timer_en", &self.clk_ble_timer_en())
+            .field("clk_data_dump_en", &self.clk_data_dump_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_syscon/clk_conf1.rs b/esp32c6/src/modem_syscon/clk_conf1.rs
index 3b131363f5..b6bedbadbb 100644
--- a/esp32c6/src/modem_syscon/clk_conf1.rs
+++ b/esp32c6/src/modem_syscon/clk_conf1.rs
@@ -224,108 +224,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF1")
-            .field(
-                "clk_wifibb_22m_en",
-                &format_args!("{}", self.clk_wifibb_22m_en().bit()),
-            )
-            .field(
-                "clk_wifibb_40m_en",
-                &format_args!("{}", self.clk_wifibb_40m_en().bit()),
-            )
-            .field(
-                "clk_wifibb_44m_en",
-                &format_args!("{}", self.clk_wifibb_44m_en().bit()),
-            )
-            .field(
-                "clk_wifibb_80m_en",
-                &format_args!("{}", self.clk_wifibb_80m_en().bit()),
-            )
-            .field(
-                "clk_wifibb_40x_en",
-                &format_args!("{}", self.clk_wifibb_40x_en().bit()),
-            )
-            .field(
-                "clk_wifibb_80x_en",
-                &format_args!("{}", self.clk_wifibb_80x_en().bit()),
-            )
-            .field(
-                "clk_wifibb_40x1_en",
-                &format_args!("{}", self.clk_wifibb_40x1_en().bit()),
-            )
-            .field(
-                "clk_wifibb_80x1_en",
-                &format_args!("{}", self.clk_wifibb_80x1_en().bit()),
-            )
-            .field(
-                "clk_wifibb_160x1_en",
-                &format_args!("{}", self.clk_wifibb_160x1_en().bit()),
-            )
-            .field(
-                "clk_wifimac_en",
-                &format_args!("{}", self.clk_wifimac_en().bit()),
-            )
-            .field(
-                "clk_wifi_apb_en",
-                &format_args!("{}", self.clk_wifi_apb_en().bit()),
-            )
-            .field(
-                "clk_fe_20m_en",
-                &format_args!("{}", self.clk_fe_20m_en().bit()),
-            )
-            .field(
-                "clk_fe_40m_en",
-                &format_args!("{}", self.clk_fe_40m_en().bit()),
-            )
-            .field(
-                "clk_fe_80m_en",
-                &format_args!("{}", self.clk_fe_80m_en().bit()),
-            )
-            .field(
-                "clk_fe_160m_en",
-                &format_args!("{}", self.clk_fe_160m_en().bit()),
-            )
-            .field(
-                "clk_fe_cal_160m_en",
-                &format_args!("{}", self.clk_fe_cal_160m_en().bit()),
-            )
-            .field(
-                "clk_fe_apb_en",
-                &format_args!("{}", self.clk_fe_apb_en().bit()),
-            )
-            .field(
-                "clk_bt_apb_en",
-                &format_args!("{}", self.clk_bt_apb_en().bit()),
-            )
-            .field("clk_bt_en", &format_args!("{}", self.clk_bt_en().bit()))
-            .field(
-                "clk_wifibb_480m_en",
-                &format_args!("{}", self.clk_wifibb_480m_en().bit()),
-            )
-            .field(
-                "clk_fe_480m_en",
-                &format_args!("{}", self.clk_fe_480m_en().bit()),
-            )
-            .field(
-                "clk_fe_anamode_40m_en",
-                &format_args!("{}", self.clk_fe_anamode_40m_en().bit()),
-            )
-            .field(
-                "clk_fe_anamode_80m_en",
-                &format_args!("{}", self.clk_fe_anamode_80m_en().bit()),
-            )
-            .field(
-                "clk_fe_anamode_160m_en",
-                &format_args!("{}", self.clk_fe_anamode_160m_en().bit()),
-            )
+            .field("clk_wifibb_22m_en", &self.clk_wifibb_22m_en())
+            .field("clk_wifibb_40m_en", &self.clk_wifibb_40m_en())
+            .field("clk_wifibb_44m_en", &self.clk_wifibb_44m_en())
+            .field("clk_wifibb_80m_en", &self.clk_wifibb_80m_en())
+            .field("clk_wifibb_40x_en", &self.clk_wifibb_40x_en())
+            .field("clk_wifibb_80x_en", &self.clk_wifibb_80x_en())
+            .field("clk_wifibb_40x1_en", &self.clk_wifibb_40x1_en())
+            .field("clk_wifibb_80x1_en", &self.clk_wifibb_80x1_en())
+            .field("clk_wifibb_160x1_en", &self.clk_wifibb_160x1_en())
+            .field("clk_wifimac_en", &self.clk_wifimac_en())
+            .field("clk_wifi_apb_en", &self.clk_wifi_apb_en())
+            .field("clk_fe_20m_en", &self.clk_fe_20m_en())
+            .field("clk_fe_40m_en", &self.clk_fe_40m_en())
+            .field("clk_fe_80m_en", &self.clk_fe_80m_en())
+            .field("clk_fe_160m_en", &self.clk_fe_160m_en())
+            .field("clk_fe_cal_160m_en", &self.clk_fe_cal_160m_en())
+            .field("clk_fe_apb_en", &self.clk_fe_apb_en())
+            .field("clk_bt_apb_en", &self.clk_bt_apb_en())
+            .field("clk_bt_en", &self.clk_bt_en())
+            .field("clk_wifibb_480m_en", &self.clk_wifibb_480m_en())
+            .field("clk_fe_480m_en", &self.clk_fe_480m_en())
+            .field("clk_fe_anamode_40m_en", &self.clk_fe_anamode_40m_en())
+            .field("clk_fe_anamode_80m_en", &self.clk_fe_anamode_80m_en())
+            .field("clk_fe_anamode_160m_en", &self.clk_fe_anamode_160m_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_syscon/clk_conf1_force_on.rs b/esp32c6/src/modem_syscon/clk_conf1_force_on.rs
index dd1017bc10..538756a088 100644
--- a/esp32c6/src/modem_syscon/clk_conf1_force_on.rs
+++ b/esp32c6/src/modem_syscon/clk_conf1_force_on.rs
@@ -224,108 +224,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF1_FORCE_ON")
-            .field(
-                "clk_wifibb_22m_fo",
-                &format_args!("{}", self.clk_wifibb_22m_fo().bit()),
-            )
-            .field(
-                "clk_wifibb_40m_fo",
-                &format_args!("{}", self.clk_wifibb_40m_fo().bit()),
-            )
-            .field(
-                "clk_wifibb_44m_fo",
-                &format_args!("{}", self.clk_wifibb_44m_fo().bit()),
-            )
-            .field(
-                "clk_wifibb_80m_fo",
-                &format_args!("{}", self.clk_wifibb_80m_fo().bit()),
-            )
-            .field(
-                "clk_wifibb_40x_fo",
-                &format_args!("{}", self.clk_wifibb_40x_fo().bit()),
-            )
-            .field(
-                "clk_wifibb_80x_fo",
-                &format_args!("{}", self.clk_wifibb_80x_fo().bit()),
-            )
-            .field(
-                "clk_wifibb_40x1_fo",
-                &format_args!("{}", self.clk_wifibb_40x1_fo().bit()),
-            )
-            .field(
-                "clk_wifibb_80x1_fo",
-                &format_args!("{}", self.clk_wifibb_80x1_fo().bit()),
-            )
-            .field(
-                "clk_wifibb_160x1_fo",
-                &format_args!("{}", self.clk_wifibb_160x1_fo().bit()),
-            )
-            .field(
-                "clk_wifimac_fo",
-                &format_args!("{}", self.clk_wifimac_fo().bit()),
-            )
-            .field(
-                "clk_wifi_apb_fo",
-                &format_args!("{}", self.clk_wifi_apb_fo().bit()),
-            )
-            .field(
-                "clk_fe_20m_fo",
-                &format_args!("{}", self.clk_fe_20m_fo().bit()),
-            )
-            .field(
-                "clk_fe_40m_fo",
-                &format_args!("{}", self.clk_fe_40m_fo().bit()),
-            )
-            .field(
-                "clk_fe_80m_fo",
-                &format_args!("{}", self.clk_fe_80m_fo().bit()),
-            )
-            .field(
-                "clk_fe_160m_fo",
-                &format_args!("{}", self.clk_fe_160m_fo().bit()),
-            )
-            .field(
-                "clk_fe_cal_160m_fo",
-                &format_args!("{}", self.clk_fe_cal_160m_fo().bit()),
-            )
-            .field(
-                "clk_fe_apb_fo",
-                &format_args!("{}", self.clk_fe_apb_fo().bit()),
-            )
-            .field(
-                "clk_bt_apb_fo",
-                &format_args!("{}", self.clk_bt_apb_fo().bit()),
-            )
-            .field("clk_bt_fo", &format_args!("{}", self.clk_bt_fo().bit()))
-            .field(
-                "clk_wifibb_480m_fo",
-                &format_args!("{}", self.clk_wifibb_480m_fo().bit()),
-            )
-            .field(
-                "clk_fe_480m_fo",
-                &format_args!("{}", self.clk_fe_480m_fo().bit()),
-            )
-            .field(
-                "clk_fe_anamode_40m_fo",
-                &format_args!("{}", self.clk_fe_anamode_40m_fo().bit()),
-            )
-            .field(
-                "clk_fe_anamode_80m_fo",
-                &format_args!("{}", self.clk_fe_anamode_80m_fo().bit()),
-            )
-            .field(
-                "clk_fe_anamode_160m_fo",
-                &format_args!("{}", self.clk_fe_anamode_160m_fo().bit()),
-            )
+            .field("clk_wifibb_22m_fo", &self.clk_wifibb_22m_fo())
+            .field("clk_wifibb_40m_fo", &self.clk_wifibb_40m_fo())
+            .field("clk_wifibb_44m_fo", &self.clk_wifibb_44m_fo())
+            .field("clk_wifibb_80m_fo", &self.clk_wifibb_80m_fo())
+            .field("clk_wifibb_40x_fo", &self.clk_wifibb_40x_fo())
+            .field("clk_wifibb_80x_fo", &self.clk_wifibb_80x_fo())
+            .field("clk_wifibb_40x1_fo", &self.clk_wifibb_40x1_fo())
+            .field("clk_wifibb_80x1_fo", &self.clk_wifibb_80x1_fo())
+            .field("clk_wifibb_160x1_fo", &self.clk_wifibb_160x1_fo())
+            .field("clk_wifimac_fo", &self.clk_wifimac_fo())
+            .field("clk_wifi_apb_fo", &self.clk_wifi_apb_fo())
+            .field("clk_fe_20m_fo", &self.clk_fe_20m_fo())
+            .field("clk_fe_40m_fo", &self.clk_fe_40m_fo())
+            .field("clk_fe_80m_fo", &self.clk_fe_80m_fo())
+            .field("clk_fe_160m_fo", &self.clk_fe_160m_fo())
+            .field("clk_fe_cal_160m_fo", &self.clk_fe_cal_160m_fo())
+            .field("clk_fe_apb_fo", &self.clk_fe_apb_fo())
+            .field("clk_bt_apb_fo", &self.clk_bt_apb_fo())
+            .field("clk_bt_fo", &self.clk_bt_fo())
+            .field("clk_wifibb_480m_fo", &self.clk_wifibb_480m_fo())
+            .field("clk_fe_480m_fo", &self.clk_fe_480m_fo())
+            .field("clk_fe_anamode_40m_fo", &self.clk_fe_anamode_40m_fo())
+            .field("clk_fe_anamode_80m_fo", &self.clk_fe_anamode_80m_fo())
+            .field("clk_fe_anamode_160m_fo", &self.clk_fe_anamode_160m_fo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF1_FORCE_ON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_syscon/clk_conf_force_on.rs b/esp32c6/src/modem_syscon/clk_conf_force_on.rs
index 3d8dcaf417..dd81883311 100644
--- a/esp32c6/src/modem_syscon/clk_conf_force_on.rs
+++ b/esp32c6/src/modem_syscon/clk_conf_force_on.rs
@@ -98,52 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF_FORCE_ON")
-            .field("clk_etm_fo", &format_args!("{}", self.clk_etm_fo().bit()))
-            .field(
-                "clk_zb_apb_fo",
-                &format_args!("{}", self.clk_zb_apb_fo().bit()),
-            )
-            .field(
-                "clk_zb_mac_fo",
-                &format_args!("{}", self.clk_zb_mac_fo().bit()),
-            )
-            .field(
-                "clk_modem_sec_ecb_fo",
-                &format_args!("{}", self.clk_modem_sec_ecb_fo().bit()),
-            )
-            .field(
-                "clk_modem_sec_ccm_fo",
-                &format_args!("{}", self.clk_modem_sec_ccm_fo().bit()),
-            )
-            .field(
-                "clk_modem_sec_bah_fo",
-                &format_args!("{}", self.clk_modem_sec_bah_fo().bit()),
-            )
-            .field(
-                "clk_modem_sec_apb_fo",
-                &format_args!("{}", self.clk_modem_sec_apb_fo().bit()),
-            )
-            .field(
-                "clk_modem_sec_fo",
-                &format_args!("{}", self.clk_modem_sec_fo().bit()),
-            )
-            .field(
-                "clk_ble_timer_fo",
-                &format_args!("{}", self.clk_ble_timer_fo().bit()),
-            )
-            .field(
-                "clk_data_dump_fo",
-                &format_args!("{}", self.clk_data_dump_fo().bit()),
-            )
+            .field("clk_etm_fo", &self.clk_etm_fo())
+            .field("clk_zb_apb_fo", &self.clk_zb_apb_fo())
+            .field("clk_zb_mac_fo", &self.clk_zb_mac_fo())
+            .field("clk_modem_sec_ecb_fo", &self.clk_modem_sec_ecb_fo())
+            .field("clk_modem_sec_ccm_fo", &self.clk_modem_sec_ccm_fo())
+            .field("clk_modem_sec_bah_fo", &self.clk_modem_sec_bah_fo())
+            .field("clk_modem_sec_apb_fo", &self.clk_modem_sec_apb_fo())
+            .field("clk_modem_sec_fo", &self.clk_modem_sec_fo())
+            .field("clk_ble_timer_fo", &self.clk_ble_timer_fo())
+            .field("clk_data_dump_fo", &self.clk_data_dump_fo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_FORCE_ON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 22"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_syscon/clk_conf_power_st.rs b/esp32c6/src/modem_syscon/clk_conf_power_st.rs
index b742a14d38..e7d1a05cd2 100644
--- a/esp32c6/src/modem_syscon/clk_conf_power_st.rs
+++ b/esp32c6/src/modem_syscon/clk_conf_power_st.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF_POWER_ST")
-            .field(
-                "clk_zb_st_map",
-                &format_args!("{}", self.clk_zb_st_map().bits()),
-            )
-            .field(
-                "clk_fe_st_map",
-                &format_args!("{}", self.clk_fe_st_map().bits()),
-            )
-            .field(
-                "clk_bt_st_map",
-                &format_args!("{}", self.clk_bt_st_map().bits()),
-            )
-            .field(
-                "clk_wifi_st_map",
-                &format_args!("{}", self.clk_wifi_st_map().bits()),
-            )
-            .field(
-                "clk_modem_peri_st_map",
-                &format_args!("{}", self.clk_modem_peri_st_map().bits()),
-            )
-            .field(
-                "clk_modem_apb_st_map",
-                &format_args!("{}", self.clk_modem_apb_st_map().bits()),
-            )
+            .field("clk_zb_st_map", &self.clk_zb_st_map())
+            .field("clk_fe_st_map", &self.clk_fe_st_map())
+            .field("clk_bt_st_map", &self.clk_bt_st_map())
+            .field("clk_wifi_st_map", &self.clk_wifi_st_map())
+            .field("clk_modem_peri_st_map", &self.clk_modem_peri_st_map())
+            .field("clk_modem_apb_st_map", &self.clk_modem_apb_st_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_POWER_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:11"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_syscon/date.rs b/esp32c6/src/modem_syscon/date.rs
index 761747a019..97bdb3d41d 100644
--- a/esp32c6/src/modem_syscon/date.rs
+++ b/esp32c6/src/modem_syscon/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/modem_syscon/mem_conf.rs b/esp32c6/src/modem_syscon/mem_conf.rs
index 776db486ac..fd9f18e9b7 100644
--- a/esp32c6/src/modem_syscon/mem_conf.rs
+++ b/esp32c6/src/modem_syscon/mem_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field(
-                "modem_mem_wp",
-                &format_args!("{}", self.modem_mem_wp().bits()),
-            )
-            .field(
-                "modem_mem_wa",
-                &format_args!("{}", self.modem_mem_wa().bits()),
-            )
-            .field(
-                "modem_mem_ra",
-                &format_args!("{}", self.modem_mem_ra().bits()),
-            )
+            .field("modem_mem_wp", &self.modem_mem_wp())
+            .field("modem_mem_wa", &self.modem_mem_wa())
+            .field("modem_mem_ra", &self.modem_mem_ra())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_syscon/modem_rst_conf.rs b/esp32c6/src/modem_syscon/modem_rst_conf.rs
index 556364fdf6..c577e9c836 100644
--- a/esp32c6/src/modem_syscon/modem_rst_conf.rs
+++ b/esp32c6/src/modem_syscon/modem_rst_conf.rs
@@ -143,54 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODEM_RST_CONF")
-            .field("rst_wifibb", &format_args!("{}", self.rst_wifibb().bit()))
-            .field("rst_wifimac", &format_args!("{}", self.rst_wifimac().bit()))
-            .field("rst_fe", &format_args!("{}", self.rst_fe().bit()))
-            .field(
-                "rst_btmac_apb",
-                &format_args!("{}", self.rst_btmac_apb().bit()),
-            )
-            .field("rst_btmac", &format_args!("{}", self.rst_btmac().bit()))
-            .field(
-                "rst_btbb_apb",
-                &format_args!("{}", self.rst_btbb_apb().bit()),
-            )
-            .field("rst_btbb", &format_args!("{}", self.rst_btbb().bit()))
-            .field("rst_etm", &format_args!("{}", self.rst_etm().bit()))
-            .field("rst_zbmac", &format_args!("{}", self.rst_zbmac().bit()))
-            .field(
-                "rst_modem_ecb",
-                &format_args!("{}", self.rst_modem_ecb().bit()),
-            )
-            .field(
-                "rst_modem_ccm",
-                &format_args!("{}", self.rst_modem_ccm().bit()),
-            )
-            .field(
-                "rst_modem_bah",
-                &format_args!("{}", self.rst_modem_bah().bit()),
-            )
-            .field(
-                "rst_modem_sec",
-                &format_args!("{}", self.rst_modem_sec().bit()),
-            )
-            .field(
-                "rst_ble_timer",
-                &format_args!("{}", self.rst_ble_timer().bit()),
-            )
-            .field(
-                "rst_data_dump",
-                &format_args!("{}", self.rst_data_dump().bit()),
-            )
+            .field("rst_wifibb", &self.rst_wifibb())
+            .field("rst_wifimac", &self.rst_wifimac())
+            .field("rst_fe", &self.rst_fe())
+            .field("rst_btmac_apb", &self.rst_btmac_apb())
+            .field("rst_btmac", &self.rst_btmac())
+            .field("rst_btbb_apb", &self.rst_btbb_apb())
+            .field("rst_btbb", &self.rst_btbb())
+            .field("rst_etm", &self.rst_etm())
+            .field("rst_zbmac", &self.rst_zbmac())
+            .field("rst_modem_ecb", &self.rst_modem_ecb())
+            .field("rst_modem_ccm", &self.rst_modem_ccm())
+            .field("rst_modem_bah", &self.rst_modem_bah())
+            .field("rst_modem_sec", &self.rst_modem_sec())
+            .field("rst_ble_timer", &self.rst_ble_timer())
+            .field("rst_data_dump", &self.rst_data_dump())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODEM_RST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_syscon/test_conf.rs b/esp32c6/src/modem_syscon/test_conf.rs
index b63a855383..c43a494741 100644
--- a/esp32c6/src/modem_syscon/test_conf.rs
+++ b/esp32c6/src/modem_syscon/test_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEST_CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32c6/src/modem_syscon/wifi_bb_cfg.rs b/esp32c6/src/modem_syscon/wifi_bb_cfg.rs
index add5c8d9d1..484f9dd15b 100644
--- a/esp32c6/src/modem_syscon/wifi_bb_cfg.rs
+++ b/esp32c6/src/modem_syscon/wifi_bb_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_BB_CFG")
-            .field(
-                "wifi_bb_cfg",
-                &format_args!("{}", self.wifi_bb_cfg().bits()),
-            )
+            .field("wifi_bb_cfg", &self.wifi_bb_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_BB_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32c6/src/otp_debug/apb2otp_en.rs b/esp32c6/src/otp_debug/apb2otp_en.rs
index 71db776175..f3345951d1 100644
--- a/esp32c6/src/otp_debug/apb2otp_en.rs
+++ b/esp32c6/src/otp_debug/apb2otp_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_EN")
-            .field("apb2otp_en", &format_args!("{}", self.apb2otp_en().bit()))
+            .field("apb2otp_en", &self.apb2otp_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Debug mode enable signal."]
     #[inline(always)]
diff --git a/esp32c6/src/otp_debug/blk0_backup1_w1.rs b/esp32c6/src/otp_debug/blk0_backup1_w1.rs
index bb690710ea..0b717aaf40 100644
--- a/esp32c6/src/otp_debug/blk0_backup1_w1.rs
+++ b/esp32c6/src/otp_debug/blk0_backup1_w1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP1_W1")
             .field(
                 "otp_bebug_block0_backup1_w1",
-                &format_args!("{}", self.otp_bebug_block0_backup1_w1().bits()),
+                &self.otp_bebug_block0_backup1_w1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP1_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup1_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP1_W1_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP1_W1_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup1_w2.rs b/esp32c6/src/otp_debug/blk0_backup1_w2.rs
index 4bdf71768a..6975d666bb 100644
--- a/esp32c6/src/otp_debug/blk0_backup1_w2.rs
+++ b/esp32c6/src/otp_debug/blk0_backup1_w2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP1_W2")
             .field(
                 "otp_bebug_block0_backup1_w2",
-                &format_args!("{}", self.otp_bebug_block0_backup1_w2().bits()),
+                &self.otp_bebug_block0_backup1_w2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP1_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup1_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP1_W2_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP1_W2_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup1_w3.rs b/esp32c6/src/otp_debug/blk0_backup1_w3.rs
index a8bdfa79ec..a5c0f3efb4 100644
--- a/esp32c6/src/otp_debug/blk0_backup1_w3.rs
+++ b/esp32c6/src/otp_debug/blk0_backup1_w3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP1_W3")
             .field(
                 "otp_bebug_block0_backup1_w3",
-                &format_args!("{}", self.otp_bebug_block0_backup1_w3().bits()),
+                &self.otp_bebug_block0_backup1_w3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP1_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup1_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP1_W3_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP1_W3_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup1_w4.rs b/esp32c6/src/otp_debug/blk0_backup1_w4.rs
index 023e7ab5d6..12c11d397f 100644
--- a/esp32c6/src/otp_debug/blk0_backup1_w4.rs
+++ b/esp32c6/src/otp_debug/blk0_backup1_w4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP1_W4")
             .field(
                 "otp_bebug_block0_backup1_w4",
-                &format_args!("{}", self.otp_bebug_block0_backup1_w4().bits()),
+                &self.otp_bebug_block0_backup1_w4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP1_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup1_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP1_W4_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP1_W4_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup1_w5.rs b/esp32c6/src/otp_debug/blk0_backup1_w5.rs
index e1f0ef2a77..e59a6e28c1 100644
--- a/esp32c6/src/otp_debug/blk0_backup1_w5.rs
+++ b/esp32c6/src/otp_debug/blk0_backup1_w5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP1_W5")
             .field(
                 "otp_bebug_block0_backup1_w5",
-                &format_args!("{}", self.otp_bebug_block0_backup1_w5().bits()),
+                &self.otp_bebug_block0_backup1_w5(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP1_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup1_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP1_W5_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP1_W5_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup2_w1.rs b/esp32c6/src/otp_debug/blk0_backup2_w1.rs
index d1f1636d37..f41383b39e 100644
--- a/esp32c6/src/otp_debug/blk0_backup2_w1.rs
+++ b/esp32c6/src/otp_debug/blk0_backup2_w1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP2_W1")
             .field(
                 "otp_bebug_block0_backup2_w1",
-                &format_args!("{}", self.otp_bebug_block0_backup2_w1().bits()),
+                &self.otp_bebug_block0_backup2_w1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP2_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup2_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP2_W1_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP2_W1_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup2_w2.rs b/esp32c6/src/otp_debug/blk0_backup2_w2.rs
index ec80a6e9ae..6ba3fd7286 100644
--- a/esp32c6/src/otp_debug/blk0_backup2_w2.rs
+++ b/esp32c6/src/otp_debug/blk0_backup2_w2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP2_W2")
             .field(
                 "otp_bebug_block0_backup2_w2",
-                &format_args!("{}", self.otp_bebug_block0_backup2_w2().bits()),
+                &self.otp_bebug_block0_backup2_w2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP2_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup2_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP2_W2_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP2_W2_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup2_w3.rs b/esp32c6/src/otp_debug/blk0_backup2_w3.rs
index 11f0f144ea..e9986929de 100644
--- a/esp32c6/src/otp_debug/blk0_backup2_w3.rs
+++ b/esp32c6/src/otp_debug/blk0_backup2_w3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP2_W3")
             .field(
                 "otp_bebug_block0_backup2_w3",
-                &format_args!("{}", self.otp_bebug_block0_backup2_w3().bits()),
+                &self.otp_bebug_block0_backup2_w3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP2_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup2_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP2_W3_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP2_W3_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup2_w4.rs b/esp32c6/src/otp_debug/blk0_backup2_w4.rs
index c605e28011..f653cc13ef 100644
--- a/esp32c6/src/otp_debug/blk0_backup2_w4.rs
+++ b/esp32c6/src/otp_debug/blk0_backup2_w4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP2_W4")
             .field(
                 "otp_bebug_block0_backup2_w4",
-                &format_args!("{}", self.otp_bebug_block0_backup2_w4().bits()),
+                &self.otp_bebug_block0_backup2_w4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP2_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup2_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP2_W4_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP2_W4_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup2_w5.rs b/esp32c6/src/otp_debug/blk0_backup2_w5.rs
index 9b432673f7..001059fe6c 100644
--- a/esp32c6/src/otp_debug/blk0_backup2_w5.rs
+++ b/esp32c6/src/otp_debug/blk0_backup2_w5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP2_W5")
             .field(
                 "otp_bebug_block0_backup2_w5",
-                &format_args!("{}", self.otp_bebug_block0_backup2_w5().bits()),
+                &self.otp_bebug_block0_backup2_w5(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP2_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup2_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP2_W5_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP2_W5_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup3_w1.rs b/esp32c6/src/otp_debug/blk0_backup3_w1.rs
index 98b3d5a981..6e6bc21e78 100644
--- a/esp32c6/src/otp_debug/blk0_backup3_w1.rs
+++ b/esp32c6/src/otp_debug/blk0_backup3_w1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP3_W1")
             .field(
                 "otp_bebug_block0_backup3_w1",
-                &format_args!("{}", self.otp_bebug_block0_backup3_w1().bits()),
+                &self.otp_bebug_block0_backup3_w1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP3_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register12.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup3_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP3_W1_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP3_W1_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup3_w2.rs b/esp32c6/src/otp_debug/blk0_backup3_w2.rs
index e1c8dd4fff..c470d2d3fe 100644
--- a/esp32c6/src/otp_debug/blk0_backup3_w2.rs
+++ b/esp32c6/src/otp_debug/blk0_backup3_w2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP3_W2")
             .field(
                 "otp_bebug_block0_backup3_w2",
-                &format_args!("{}", self.otp_bebug_block0_backup3_w2().bits()),
+                &self.otp_bebug_block0_backup3_w2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP3_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register13.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup3_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP3_W2_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP3_W2_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup3_w3.rs b/esp32c6/src/otp_debug/blk0_backup3_w3.rs
index a21af93fa2..5e6b817596 100644
--- a/esp32c6/src/otp_debug/blk0_backup3_w3.rs
+++ b/esp32c6/src/otp_debug/blk0_backup3_w3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP3_W3")
             .field(
                 "otp_bebug_block0_backup3_w3",
-                &format_args!("{}", self.otp_bebug_block0_backup3_w3().bits()),
+                &self.otp_bebug_block0_backup3_w3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP3_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register14.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup3_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP3_W3_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP3_W3_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup3_w4.rs b/esp32c6/src/otp_debug/blk0_backup3_w4.rs
index 0d6cb57263..f4eabb25c6 100644
--- a/esp32c6/src/otp_debug/blk0_backup3_w4.rs
+++ b/esp32c6/src/otp_debug/blk0_backup3_w4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP3_W4")
             .field(
                 "otp_bebug_block0_backup3_w4",
-                &format_args!("{}", self.otp_bebug_block0_backup3_w4().bits()),
+                &self.otp_bebug_block0_backup3_w4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP3_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register15.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup3_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP3_W4_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP3_W4_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup3_w5.rs b/esp32c6/src/otp_debug/blk0_backup3_w5.rs
index 2fcf502f55..acebb2ce90 100644
--- a/esp32c6/src/otp_debug/blk0_backup3_w5.rs
+++ b/esp32c6/src/otp_debug/blk0_backup3_w5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP3_W5")
             .field(
                 "otp_bebug_block0_backup3_w5",
-                &format_args!("{}", self.otp_bebug_block0_backup3_w5().bits()),
+                &self.otp_bebug_block0_backup3_w5(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP3_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register16.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup3_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP3_W5_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP3_W5_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup4_w1.rs b/esp32c6/src/otp_debug/blk0_backup4_w1.rs
index 480b7dfaee..3d5df84fc7 100644
--- a/esp32c6/src/otp_debug/blk0_backup4_w1.rs
+++ b/esp32c6/src/otp_debug/blk0_backup4_w1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP4_W1")
             .field(
                 "otp_bebug_block0_backup4_w1",
-                &format_args!("{}", self.otp_bebug_block0_backup4_w1().bits()),
+                &self.otp_bebug_block0_backup4_w1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP4_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register17.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup4_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP4_W1_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP4_W1_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup4_w2.rs b/esp32c6/src/otp_debug/blk0_backup4_w2.rs
index 662b662a52..09f621fc56 100644
--- a/esp32c6/src/otp_debug/blk0_backup4_w2.rs
+++ b/esp32c6/src/otp_debug/blk0_backup4_w2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP4_W2")
             .field(
                 "otp_bebug_block0_backup4_w2",
-                &format_args!("{}", self.otp_bebug_block0_backup4_w2().bits()),
+                &self.otp_bebug_block0_backup4_w2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP4_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register18.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup4_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP4_W2_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP4_W2_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup4_w3.rs b/esp32c6/src/otp_debug/blk0_backup4_w3.rs
index 43ccd5ab27..e33fc540d5 100644
--- a/esp32c6/src/otp_debug/blk0_backup4_w3.rs
+++ b/esp32c6/src/otp_debug/blk0_backup4_w3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP4_W3")
             .field(
                 "otp_bebug_block0_backup4_w3",
-                &format_args!("{}", self.otp_bebug_block0_backup4_w3().bits()),
+                &self.otp_bebug_block0_backup4_w3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP4_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register19.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup4_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP4_W3_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP4_W3_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup4_w4.rs b/esp32c6/src/otp_debug/blk0_backup4_w4.rs
index 8a2f5fccc4..5af390b1c4 100644
--- a/esp32c6/src/otp_debug/blk0_backup4_w4.rs
+++ b/esp32c6/src/otp_debug/blk0_backup4_w4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP4_W4")
             .field(
                 "otp_bebug_block0_backup4_w4",
-                &format_args!("{}", self.otp_bebug_block0_backup4_w4().bits()),
+                &self.otp_bebug_block0_backup4_w4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP4_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register20.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup4_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP4_W4_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP4_W4_SPEC {
diff --git a/esp32c6/src/otp_debug/blk0_backup4_w5.rs b/esp32c6/src/otp_debug/blk0_backup4_w5.rs
index 0707eb46ff..2ed46520ea 100644
--- a/esp32c6/src/otp_debug/blk0_backup4_w5.rs
+++ b/esp32c6/src/otp_debug/blk0_backup4_w5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP4_W5")
             .field(
                 "otp_bebug_block0_backup4_w5",
-                &format_args!("{}", self.otp_bebug_block0_backup4_w5().bits()),
+                &self.otp_bebug_block0_backup4_w5(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP4_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register21.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup4_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP4_W5_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP4_W5_SPEC {
diff --git a/esp32c6/src/otp_debug/blk10_w1.rs b/esp32c6/src/otp_debug/blk10_w1.rs
index 98cf693df2..7229a0497d 100644
--- a/esp32c6/src/otp_debug/blk10_w1.rs
+++ b/esp32c6/src/otp_debug/blk10_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W1")
-            .field("block10_w1", &format_args!("{}", self.block10_w1().bits()))
+            .field("block10_w1", &self.block10_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W1_SPEC;
 impl crate::RegisterSpec for BLK10_W1_SPEC {
diff --git a/esp32c6/src/otp_debug/blk10_w10.rs b/esp32c6/src/otp_debug/blk10_w10.rs
index eb9915b767..cc48585332 100644
--- a/esp32c6/src/otp_debug/blk10_w10.rs
+++ b/esp32c6/src/otp_debug/blk10_w10.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W10")
-            .field(
-                "block19_w10",
-                &format_args!("{}", self.block19_w10().bits()),
-            )
+            .field("block19_w10", &self.block19_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W10_SPEC;
 impl crate::RegisterSpec for BLK10_W10_SPEC {
diff --git a/esp32c6/src/otp_debug/blk10_w11.rs b/esp32c6/src/otp_debug/blk10_w11.rs
index f019dea81b..cabf753006 100644
--- a/esp32c6/src/otp_debug/blk10_w11.rs
+++ b/esp32c6/src/otp_debug/blk10_w11.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W11")
-            .field(
-                "block10_w11",
-                &format_args!("{}", self.block10_w11().bits()),
-            )
+            .field("block10_w11", &self.block10_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W11_SPEC;
 impl crate::RegisterSpec for BLK10_W11_SPEC {
diff --git a/esp32c6/src/otp_debug/blk10_w2.rs b/esp32c6/src/otp_debug/blk10_w2.rs
index 61c39a9f94..06835e9708 100644
--- a/esp32c6/src/otp_debug/blk10_w2.rs
+++ b/esp32c6/src/otp_debug/blk10_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W2")
-            .field("block10_w2", &format_args!("{}", self.block10_w2().bits()))
+            .field("block10_w2", &self.block10_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W2_SPEC;
 impl crate::RegisterSpec for BLK10_W2_SPEC {
diff --git a/esp32c6/src/otp_debug/blk10_w3.rs b/esp32c6/src/otp_debug/blk10_w3.rs
index 739f43ceae..383028ffd1 100644
--- a/esp32c6/src/otp_debug/blk10_w3.rs
+++ b/esp32c6/src/otp_debug/blk10_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W3")
-            .field("block10_w3", &format_args!("{}", self.block10_w3().bits()))
+            .field("block10_w3", &self.block10_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W3_SPEC;
 impl crate::RegisterSpec for BLK10_W3_SPEC {
diff --git a/esp32c6/src/otp_debug/blk10_w4.rs b/esp32c6/src/otp_debug/blk10_w4.rs
index ee094acb6e..fd0d59110a 100644
--- a/esp32c6/src/otp_debug/blk10_w4.rs
+++ b/esp32c6/src/otp_debug/blk10_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W4")
-            .field("block10_w4", &format_args!("{}", self.block10_w4().bits()))
+            .field("block10_w4", &self.block10_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W4_SPEC;
 impl crate::RegisterSpec for BLK10_W4_SPEC {
diff --git a/esp32c6/src/otp_debug/blk10_w5.rs b/esp32c6/src/otp_debug/blk10_w5.rs
index c25230180d..1289e89f36 100644
--- a/esp32c6/src/otp_debug/blk10_w5.rs
+++ b/esp32c6/src/otp_debug/blk10_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W5")
-            .field("block10_w5", &format_args!("{}", self.block10_w5().bits()))
+            .field("block10_w5", &self.block10_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W5_SPEC;
 impl crate::RegisterSpec for BLK10_W5_SPEC {
diff --git a/esp32c6/src/otp_debug/blk10_w6.rs b/esp32c6/src/otp_debug/blk10_w6.rs
index 1f64df8f53..8837441fb1 100644
--- a/esp32c6/src/otp_debug/blk10_w6.rs
+++ b/esp32c6/src/otp_debug/blk10_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W6")
-            .field("block10_w6", &format_args!("{}", self.block10_w6().bits()))
+            .field("block10_w6", &self.block10_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W6_SPEC;
 impl crate::RegisterSpec for BLK10_W6_SPEC {
diff --git a/esp32c6/src/otp_debug/blk10_w7.rs b/esp32c6/src/otp_debug/blk10_w7.rs
index d62ebceefb..35a6c9adc8 100644
--- a/esp32c6/src/otp_debug/blk10_w7.rs
+++ b/esp32c6/src/otp_debug/blk10_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W7")
-            .field("block10_w7", &format_args!("{}", self.block10_w7().bits()))
+            .field("block10_w7", &self.block10_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W7_SPEC;
 impl crate::RegisterSpec for BLK10_W7_SPEC {
diff --git a/esp32c6/src/otp_debug/blk10_w8.rs b/esp32c6/src/otp_debug/blk10_w8.rs
index 1994aeaaf6..5f610a854a 100644
--- a/esp32c6/src/otp_debug/blk10_w8.rs
+++ b/esp32c6/src/otp_debug/blk10_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W8")
-            .field("block10_w8", &format_args!("{}", self.block10_w8().bits()))
+            .field("block10_w8", &self.block10_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W8_SPEC;
 impl crate::RegisterSpec for BLK10_W8_SPEC {
diff --git a/esp32c6/src/otp_debug/blk10_w9.rs b/esp32c6/src/otp_debug/blk10_w9.rs
index c818c2ae7e..9021e8ce16 100644
--- a/esp32c6/src/otp_debug/blk10_w9.rs
+++ b/esp32c6/src/otp_debug/blk10_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W9")
-            .field("block10_w9", &format_args!("{}", self.block10_w9().bits()))
+            .field("block10_w9", &self.block10_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W9_SPEC;
 impl crate::RegisterSpec for BLK10_W9_SPEC {
diff --git a/esp32c6/src/otp_debug/blk1_w1.rs b/esp32c6/src/otp_debug/blk1_w1.rs
index 1e40d5d948..19925de656 100644
--- a/esp32c6/src/otp_debug/blk1_w1.rs
+++ b/esp32c6/src/otp_debug/blk1_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W1")
-            .field("block1_w1", &format_args!("{}", self.block1_w1().bits()))
+            .field("block1_w1", &self.block1_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W1_SPEC;
 impl crate::RegisterSpec for BLK1_W1_SPEC {
diff --git a/esp32c6/src/otp_debug/blk1_w2.rs b/esp32c6/src/otp_debug/blk1_w2.rs
index c9c12a5045..a4daa9baf3 100644
--- a/esp32c6/src/otp_debug/blk1_w2.rs
+++ b/esp32c6/src/otp_debug/blk1_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W2")
-            .field("block1_w2", &format_args!("{}", self.block1_w2().bits()))
+            .field("block1_w2", &self.block1_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W2_SPEC;
 impl crate::RegisterSpec for BLK1_W2_SPEC {
diff --git a/esp32c6/src/otp_debug/blk1_w3.rs b/esp32c6/src/otp_debug/blk1_w3.rs
index b8aef24df2..ee8503456c 100644
--- a/esp32c6/src/otp_debug/blk1_w3.rs
+++ b/esp32c6/src/otp_debug/blk1_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W3")
-            .field("block1_w3", &format_args!("{}", self.block1_w3().bits()))
+            .field("block1_w3", &self.block1_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W3_SPEC;
 impl crate::RegisterSpec for BLK1_W3_SPEC {
diff --git a/esp32c6/src/otp_debug/blk1_w4.rs b/esp32c6/src/otp_debug/blk1_w4.rs
index b91be23212..88dd803000 100644
--- a/esp32c6/src/otp_debug/blk1_w4.rs
+++ b/esp32c6/src/otp_debug/blk1_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W4")
-            .field("block1_w4", &format_args!("{}", self.block1_w4().bits()))
+            .field("block1_w4", &self.block1_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W4_SPEC;
 impl crate::RegisterSpec for BLK1_W4_SPEC {
diff --git a/esp32c6/src/otp_debug/blk1_w5.rs b/esp32c6/src/otp_debug/blk1_w5.rs
index 8bf9cfe91a..998abcbb34 100644
--- a/esp32c6/src/otp_debug/blk1_w5.rs
+++ b/esp32c6/src/otp_debug/blk1_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W5")
-            .field("block1_w5", &format_args!("{}", self.block1_w5().bits()))
+            .field("block1_w5", &self.block1_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W5_SPEC;
 impl crate::RegisterSpec for BLK1_W5_SPEC {
diff --git a/esp32c6/src/otp_debug/blk1_w6.rs b/esp32c6/src/otp_debug/blk1_w6.rs
index 04168bf573..a8870c0f42 100644
--- a/esp32c6/src/otp_debug/blk1_w6.rs
+++ b/esp32c6/src/otp_debug/blk1_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W6")
-            .field("block1_w6", &format_args!("{}", self.block1_w6().bits()))
+            .field("block1_w6", &self.block1_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W6_SPEC;
 impl crate::RegisterSpec for BLK1_W6_SPEC {
diff --git a/esp32c6/src/otp_debug/blk1_w7.rs b/esp32c6/src/otp_debug/blk1_w7.rs
index ecd0297b7e..4394c8dca2 100644
--- a/esp32c6/src/otp_debug/blk1_w7.rs
+++ b/esp32c6/src/otp_debug/blk1_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W7")
-            .field("block1_w7", &format_args!("{}", self.block1_w7().bits()))
+            .field("block1_w7", &self.block1_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W7_SPEC;
 impl crate::RegisterSpec for BLK1_W7_SPEC {
diff --git a/esp32c6/src/otp_debug/blk1_w8.rs b/esp32c6/src/otp_debug/blk1_w8.rs
index 213df188d8..bb5f995f4f 100644
--- a/esp32c6/src/otp_debug/blk1_w8.rs
+++ b/esp32c6/src/otp_debug/blk1_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W8")
-            .field("block1_w8", &format_args!("{}", self.block1_w8().bits()))
+            .field("block1_w8", &self.block1_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W8_SPEC;
 impl crate::RegisterSpec for BLK1_W8_SPEC {
diff --git a/esp32c6/src/otp_debug/blk1_w9.rs b/esp32c6/src/otp_debug/blk1_w9.rs
index d3f28503e2..4ffe29d3d8 100644
--- a/esp32c6/src/otp_debug/blk1_w9.rs
+++ b/esp32c6/src/otp_debug/blk1_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W9")
-            .field("block1_w9", &format_args!("{}", self.block1_w9().bits()))
+            .field("block1_w9", &self.block1_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W9_SPEC;
 impl crate::RegisterSpec for BLK1_W9_SPEC {
diff --git a/esp32c6/src/otp_debug/blk2_w1.rs b/esp32c6/src/otp_debug/blk2_w1.rs
index 6473f28b40..26dab78b9b 100644
--- a/esp32c6/src/otp_debug/blk2_w1.rs
+++ b/esp32c6/src/otp_debug/blk2_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W1")
-            .field("block2_w1", &format_args!("{}", self.block2_w1().bits()))
+            .field("block2_w1", &self.block2_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W1_SPEC;
 impl crate::RegisterSpec for BLK2_W1_SPEC {
diff --git a/esp32c6/src/otp_debug/blk2_w10.rs b/esp32c6/src/otp_debug/blk2_w10.rs
index 64cfa633b4..ecacf275a6 100644
--- a/esp32c6/src/otp_debug/blk2_w10.rs
+++ b/esp32c6/src/otp_debug/blk2_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W10")
-            .field("block2_w10", &format_args!("{}", self.block2_w10().bits()))
+            .field("block2_w10", &self.block2_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W10_SPEC;
 impl crate::RegisterSpec for BLK2_W10_SPEC {
diff --git a/esp32c6/src/otp_debug/blk2_w11.rs b/esp32c6/src/otp_debug/blk2_w11.rs
index c417e18cfd..f55c8acaa1 100644
--- a/esp32c6/src/otp_debug/blk2_w11.rs
+++ b/esp32c6/src/otp_debug/blk2_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W11")
-            .field("block2_w11", &format_args!("{}", self.block2_w11().bits()))
+            .field("block2_w11", &self.block2_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W11_SPEC;
 impl crate::RegisterSpec for BLK2_W11_SPEC {
diff --git a/esp32c6/src/otp_debug/blk2_w2.rs b/esp32c6/src/otp_debug/blk2_w2.rs
index 00b2046c1c..8dfc697f5b 100644
--- a/esp32c6/src/otp_debug/blk2_w2.rs
+++ b/esp32c6/src/otp_debug/blk2_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W2")
-            .field("block2_w2", &format_args!("{}", self.block2_w2().bits()))
+            .field("block2_w2", &self.block2_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W2_SPEC;
 impl crate::RegisterSpec for BLK2_W2_SPEC {
diff --git a/esp32c6/src/otp_debug/blk2_w3.rs b/esp32c6/src/otp_debug/blk2_w3.rs
index 6ada7f82ed..4af8c1a54e 100644
--- a/esp32c6/src/otp_debug/blk2_w3.rs
+++ b/esp32c6/src/otp_debug/blk2_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W3")
-            .field("block2_w3", &format_args!("{}", self.block2_w3().bits()))
+            .field("block2_w3", &self.block2_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W3_SPEC;
 impl crate::RegisterSpec for BLK2_W3_SPEC {
diff --git a/esp32c6/src/otp_debug/blk2_w4.rs b/esp32c6/src/otp_debug/blk2_w4.rs
index a20fd7353a..e25c6dc8d1 100644
--- a/esp32c6/src/otp_debug/blk2_w4.rs
+++ b/esp32c6/src/otp_debug/blk2_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W4")
-            .field("block2_w4", &format_args!("{}", self.block2_w4().bits()))
+            .field("block2_w4", &self.block2_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W4_SPEC;
 impl crate::RegisterSpec for BLK2_W4_SPEC {
diff --git a/esp32c6/src/otp_debug/blk2_w5.rs b/esp32c6/src/otp_debug/blk2_w5.rs
index a3b63748c6..038314b1da 100644
--- a/esp32c6/src/otp_debug/blk2_w5.rs
+++ b/esp32c6/src/otp_debug/blk2_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W5")
-            .field("block2_w5", &format_args!("{}", self.block2_w5().bits()))
+            .field("block2_w5", &self.block2_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W5_SPEC;
 impl crate::RegisterSpec for BLK2_W5_SPEC {
diff --git a/esp32c6/src/otp_debug/blk2_w6.rs b/esp32c6/src/otp_debug/blk2_w6.rs
index 27ca05b93b..750f2329e9 100644
--- a/esp32c6/src/otp_debug/blk2_w6.rs
+++ b/esp32c6/src/otp_debug/blk2_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W6")
-            .field("block2_w6", &format_args!("{}", self.block2_w6().bits()))
+            .field("block2_w6", &self.block2_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W6_SPEC;
 impl crate::RegisterSpec for BLK2_W6_SPEC {
diff --git a/esp32c6/src/otp_debug/blk2_w7.rs b/esp32c6/src/otp_debug/blk2_w7.rs
index 18b136a0a2..7bc7d5bc83 100644
--- a/esp32c6/src/otp_debug/blk2_w7.rs
+++ b/esp32c6/src/otp_debug/blk2_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W7")
-            .field("block2_w7", &format_args!("{}", self.block2_w7().bits()))
+            .field("block2_w7", &self.block2_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W7_SPEC;
 impl crate::RegisterSpec for BLK2_W7_SPEC {
diff --git a/esp32c6/src/otp_debug/blk2_w8.rs b/esp32c6/src/otp_debug/blk2_w8.rs
index 0bfcd982c7..c25622a085 100644
--- a/esp32c6/src/otp_debug/blk2_w8.rs
+++ b/esp32c6/src/otp_debug/blk2_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W8")
-            .field("block2_w8", &format_args!("{}", self.block2_w8().bits()))
+            .field("block2_w8", &self.block2_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W8_SPEC;
 impl crate::RegisterSpec for BLK2_W8_SPEC {
diff --git a/esp32c6/src/otp_debug/blk2_w9.rs b/esp32c6/src/otp_debug/blk2_w9.rs
index 064198d0bc..53b4d92f84 100644
--- a/esp32c6/src/otp_debug/blk2_w9.rs
+++ b/esp32c6/src/otp_debug/blk2_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W9")
-            .field("block2_w9", &format_args!("{}", self.block2_w9().bits()))
+            .field("block2_w9", &self.block2_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W9_SPEC;
 impl crate::RegisterSpec for BLK2_W9_SPEC {
diff --git a/esp32c6/src/otp_debug/blk3_w1.rs b/esp32c6/src/otp_debug/blk3_w1.rs
index 488a9fb483..ce86b475fc 100644
--- a/esp32c6/src/otp_debug/blk3_w1.rs
+++ b/esp32c6/src/otp_debug/blk3_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W1")
-            .field("block3_w1", &format_args!("{}", self.block3_w1().bits()))
+            .field("block3_w1", &self.block3_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W1_SPEC;
 impl crate::RegisterSpec for BLK3_W1_SPEC {
diff --git a/esp32c6/src/otp_debug/blk3_w10.rs b/esp32c6/src/otp_debug/blk3_w10.rs
index eb0ee64853..77628ad844 100644
--- a/esp32c6/src/otp_debug/blk3_w10.rs
+++ b/esp32c6/src/otp_debug/blk3_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W10")
-            .field("block3_w10", &format_args!("{}", self.block3_w10().bits()))
+            .field("block3_w10", &self.block3_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W10_SPEC;
 impl crate::RegisterSpec for BLK3_W10_SPEC {
diff --git a/esp32c6/src/otp_debug/blk3_w11.rs b/esp32c6/src/otp_debug/blk3_w11.rs
index 3e691ed90c..2d26724d29 100644
--- a/esp32c6/src/otp_debug/blk3_w11.rs
+++ b/esp32c6/src/otp_debug/blk3_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W11")
-            .field("block3_w11", &format_args!("{}", self.block3_w11().bits()))
+            .field("block3_w11", &self.block3_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W11_SPEC;
 impl crate::RegisterSpec for BLK3_W11_SPEC {
diff --git a/esp32c6/src/otp_debug/blk3_w2.rs b/esp32c6/src/otp_debug/blk3_w2.rs
index dc98b45db5..8964a221f4 100644
--- a/esp32c6/src/otp_debug/blk3_w2.rs
+++ b/esp32c6/src/otp_debug/blk3_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W2")
-            .field("block3_w2", &format_args!("{}", self.block3_w2().bits()))
+            .field("block3_w2", &self.block3_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W2_SPEC;
 impl crate::RegisterSpec for BLK3_W2_SPEC {
diff --git a/esp32c6/src/otp_debug/blk3_w3.rs b/esp32c6/src/otp_debug/blk3_w3.rs
index 457c7b2b08..48cafb6aa0 100644
--- a/esp32c6/src/otp_debug/blk3_w3.rs
+++ b/esp32c6/src/otp_debug/blk3_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W3")
-            .field("block3_w3", &format_args!("{}", self.block3_w3().bits()))
+            .field("block3_w3", &self.block3_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W3_SPEC;
 impl crate::RegisterSpec for BLK3_W3_SPEC {
diff --git a/esp32c6/src/otp_debug/blk3_w4.rs b/esp32c6/src/otp_debug/blk3_w4.rs
index b9e2de9f9e..416da42195 100644
--- a/esp32c6/src/otp_debug/blk3_w4.rs
+++ b/esp32c6/src/otp_debug/blk3_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W4")
-            .field("block3_w4", &format_args!("{}", self.block3_w4().bits()))
+            .field("block3_w4", &self.block3_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W4_SPEC;
 impl crate::RegisterSpec for BLK3_W4_SPEC {
diff --git a/esp32c6/src/otp_debug/blk3_w5.rs b/esp32c6/src/otp_debug/blk3_w5.rs
index 5c817869a9..2be3abd5f2 100644
--- a/esp32c6/src/otp_debug/blk3_w5.rs
+++ b/esp32c6/src/otp_debug/blk3_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W5")
-            .field("block3_w5", &format_args!("{}", self.block3_w5().bits()))
+            .field("block3_w5", &self.block3_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W5_SPEC;
 impl crate::RegisterSpec for BLK3_W5_SPEC {
diff --git a/esp32c6/src/otp_debug/blk3_w6.rs b/esp32c6/src/otp_debug/blk3_w6.rs
index c5a10e7814..ad8d08166d 100644
--- a/esp32c6/src/otp_debug/blk3_w6.rs
+++ b/esp32c6/src/otp_debug/blk3_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W6")
-            .field("block3_w6", &format_args!("{}", self.block3_w6().bits()))
+            .field("block3_w6", &self.block3_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W6_SPEC;
 impl crate::RegisterSpec for BLK3_W6_SPEC {
diff --git a/esp32c6/src/otp_debug/blk3_w7.rs b/esp32c6/src/otp_debug/blk3_w7.rs
index 464d1dbd3d..a04b785e95 100644
--- a/esp32c6/src/otp_debug/blk3_w7.rs
+++ b/esp32c6/src/otp_debug/blk3_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W7")
-            .field("block3_w7", &format_args!("{}", self.block3_w7().bits()))
+            .field("block3_w7", &self.block3_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W7_SPEC;
 impl crate::RegisterSpec for BLK3_W7_SPEC {
diff --git a/esp32c6/src/otp_debug/blk3_w8.rs b/esp32c6/src/otp_debug/blk3_w8.rs
index e3d7140795..29d1fc0ea0 100644
--- a/esp32c6/src/otp_debug/blk3_w8.rs
+++ b/esp32c6/src/otp_debug/blk3_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W8")
-            .field("block3_w8", &format_args!("{}", self.block3_w8().bits()))
+            .field("block3_w8", &self.block3_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W8_SPEC;
 impl crate::RegisterSpec for BLK3_W8_SPEC {
diff --git a/esp32c6/src/otp_debug/blk3_w9.rs b/esp32c6/src/otp_debug/blk3_w9.rs
index a1a73eac44..a0cac36b88 100644
--- a/esp32c6/src/otp_debug/blk3_w9.rs
+++ b/esp32c6/src/otp_debug/blk3_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W9")
-            .field("block3_w9", &format_args!("{}", self.block3_w9().bits()))
+            .field("block3_w9", &self.block3_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W9_SPEC;
 impl crate::RegisterSpec for BLK3_W9_SPEC {
diff --git a/esp32c6/src/otp_debug/blk4_w1.rs b/esp32c6/src/otp_debug/blk4_w1.rs
index 9299cfd5dc..8b55ec57e6 100644
--- a/esp32c6/src/otp_debug/blk4_w1.rs
+++ b/esp32c6/src/otp_debug/blk4_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W1")
-            .field("block4_w1", &format_args!("{}", self.block4_w1().bits()))
+            .field("block4_w1", &self.block4_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W1_SPEC;
 impl crate::RegisterSpec for BLK4_W1_SPEC {
diff --git a/esp32c6/src/otp_debug/blk4_w10.rs b/esp32c6/src/otp_debug/blk4_w10.rs
index 728bb54228..52c55ba06a 100644
--- a/esp32c6/src/otp_debug/blk4_w10.rs
+++ b/esp32c6/src/otp_debug/blk4_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W10")
-            .field("block4_w10", &format_args!("{}", self.block4_w10().bits()))
+            .field("block4_w10", &self.block4_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data registe10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W10_SPEC;
 impl crate::RegisterSpec for BLK4_W10_SPEC {
diff --git a/esp32c6/src/otp_debug/blk4_w11.rs b/esp32c6/src/otp_debug/blk4_w11.rs
index 4f241693f4..60c4166fe7 100644
--- a/esp32c6/src/otp_debug/blk4_w11.rs
+++ b/esp32c6/src/otp_debug/blk4_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W11")
-            .field("block4_w11", &format_args!("{}", self.block4_w11().bits()))
+            .field("block4_w11", &self.block4_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W11_SPEC;
 impl crate::RegisterSpec for BLK4_W11_SPEC {
diff --git a/esp32c6/src/otp_debug/blk4_w2.rs b/esp32c6/src/otp_debug/blk4_w2.rs
index 882038dea2..3184daaf8d 100644
--- a/esp32c6/src/otp_debug/blk4_w2.rs
+++ b/esp32c6/src/otp_debug/blk4_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W2")
-            .field("block4_w2", &format_args!("{}", self.block4_w2().bits()))
+            .field("block4_w2", &self.block4_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W2_SPEC;
 impl crate::RegisterSpec for BLK4_W2_SPEC {
diff --git a/esp32c6/src/otp_debug/blk4_w3.rs b/esp32c6/src/otp_debug/blk4_w3.rs
index fb29e09670..15422542d5 100644
--- a/esp32c6/src/otp_debug/blk4_w3.rs
+++ b/esp32c6/src/otp_debug/blk4_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W3")
-            .field("block4_w3", &format_args!("{}", self.block4_w3().bits()))
+            .field("block4_w3", &self.block4_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W3_SPEC;
 impl crate::RegisterSpec for BLK4_W3_SPEC {
diff --git a/esp32c6/src/otp_debug/blk4_w4.rs b/esp32c6/src/otp_debug/blk4_w4.rs
index c53db9e4f7..d8a728ae53 100644
--- a/esp32c6/src/otp_debug/blk4_w4.rs
+++ b/esp32c6/src/otp_debug/blk4_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W4")
-            .field("block4_w4", &format_args!("{}", self.block4_w4().bits()))
+            .field("block4_w4", &self.block4_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W4_SPEC;
 impl crate::RegisterSpec for BLK4_W4_SPEC {
diff --git a/esp32c6/src/otp_debug/blk4_w5.rs b/esp32c6/src/otp_debug/blk4_w5.rs
index 9f5649dcde..561674c4ad 100644
--- a/esp32c6/src/otp_debug/blk4_w5.rs
+++ b/esp32c6/src/otp_debug/blk4_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W5")
-            .field("block4_w5", &format_args!("{}", self.block4_w5().bits()))
+            .field("block4_w5", &self.block4_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W5_SPEC;
 impl crate::RegisterSpec for BLK4_W5_SPEC {
diff --git a/esp32c6/src/otp_debug/blk4_w6.rs b/esp32c6/src/otp_debug/blk4_w6.rs
index 917a665253..b53f2ec328 100644
--- a/esp32c6/src/otp_debug/blk4_w6.rs
+++ b/esp32c6/src/otp_debug/blk4_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W6")
-            .field("block4_w6", &format_args!("{}", self.block4_w6().bits()))
+            .field("block4_w6", &self.block4_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W6_SPEC;
 impl crate::RegisterSpec for BLK4_W6_SPEC {
diff --git a/esp32c6/src/otp_debug/blk4_w7.rs b/esp32c6/src/otp_debug/blk4_w7.rs
index 71f15cf4e8..98315eef38 100644
--- a/esp32c6/src/otp_debug/blk4_w7.rs
+++ b/esp32c6/src/otp_debug/blk4_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W7")
-            .field("block4_w7", &format_args!("{}", self.block4_w7().bits()))
+            .field("block4_w7", &self.block4_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W7_SPEC;
 impl crate::RegisterSpec for BLK4_W7_SPEC {
diff --git a/esp32c6/src/otp_debug/blk4_w8.rs b/esp32c6/src/otp_debug/blk4_w8.rs
index 4d91ca1e90..580bfb5569 100644
--- a/esp32c6/src/otp_debug/blk4_w8.rs
+++ b/esp32c6/src/otp_debug/blk4_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W8")
-            .field("block4_w8", &format_args!("{}", self.block4_w8().bits()))
+            .field("block4_w8", &self.block4_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W8_SPEC;
 impl crate::RegisterSpec for BLK4_W8_SPEC {
diff --git a/esp32c6/src/otp_debug/blk4_w9.rs b/esp32c6/src/otp_debug/blk4_w9.rs
index f3983eca39..082293cd06 100644
--- a/esp32c6/src/otp_debug/blk4_w9.rs
+++ b/esp32c6/src/otp_debug/blk4_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W9")
-            .field("block4_w9", &format_args!("{}", self.block4_w9().bits()))
+            .field("block4_w9", &self.block4_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W9_SPEC;
 impl crate::RegisterSpec for BLK4_W9_SPEC {
diff --git a/esp32c6/src/otp_debug/blk5_w1.rs b/esp32c6/src/otp_debug/blk5_w1.rs
index e6989f7cae..31d5bed004 100644
--- a/esp32c6/src/otp_debug/blk5_w1.rs
+++ b/esp32c6/src/otp_debug/blk5_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W1")
-            .field("block5_w1", &format_args!("{}", self.block5_w1().bits()))
+            .field("block5_w1", &self.block5_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W1_SPEC;
 impl crate::RegisterSpec for BLK5_W1_SPEC {
diff --git a/esp32c6/src/otp_debug/blk5_w10.rs b/esp32c6/src/otp_debug/blk5_w10.rs
index 436b0412e3..b0024572db 100644
--- a/esp32c6/src/otp_debug/blk5_w10.rs
+++ b/esp32c6/src/otp_debug/blk5_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W10")
-            .field("block5_w10", &format_args!("{}", self.block5_w10().bits()))
+            .field("block5_w10", &self.block5_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W10_SPEC;
 impl crate::RegisterSpec for BLK5_W10_SPEC {
diff --git a/esp32c6/src/otp_debug/blk5_w11.rs b/esp32c6/src/otp_debug/blk5_w11.rs
index 38a852001a..6103533027 100644
--- a/esp32c6/src/otp_debug/blk5_w11.rs
+++ b/esp32c6/src/otp_debug/blk5_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W11")
-            .field("block5_w11", &format_args!("{}", self.block5_w11().bits()))
+            .field("block5_w11", &self.block5_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W11_SPEC;
 impl crate::RegisterSpec for BLK5_W11_SPEC {
diff --git a/esp32c6/src/otp_debug/blk5_w2.rs b/esp32c6/src/otp_debug/blk5_w2.rs
index fcead77a8e..6f09c96c12 100644
--- a/esp32c6/src/otp_debug/blk5_w2.rs
+++ b/esp32c6/src/otp_debug/blk5_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W2")
-            .field("block5_w2", &format_args!("{}", self.block5_w2().bits()))
+            .field("block5_w2", &self.block5_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W2_SPEC;
 impl crate::RegisterSpec for BLK5_W2_SPEC {
diff --git a/esp32c6/src/otp_debug/blk5_w3.rs b/esp32c6/src/otp_debug/blk5_w3.rs
index c1079d0c46..4017bdd56d 100644
--- a/esp32c6/src/otp_debug/blk5_w3.rs
+++ b/esp32c6/src/otp_debug/blk5_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W3")
-            .field("block5_w3", &format_args!("{}", self.block5_w3().bits()))
+            .field("block5_w3", &self.block5_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W3_SPEC;
 impl crate::RegisterSpec for BLK5_W3_SPEC {
diff --git a/esp32c6/src/otp_debug/blk5_w4.rs b/esp32c6/src/otp_debug/blk5_w4.rs
index 38f91f647e..e8d5b74e71 100644
--- a/esp32c6/src/otp_debug/blk5_w4.rs
+++ b/esp32c6/src/otp_debug/blk5_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W4")
-            .field("block5_w4", &format_args!("{}", self.block5_w4().bits()))
+            .field("block5_w4", &self.block5_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W4_SPEC;
 impl crate::RegisterSpec for BLK5_W4_SPEC {
diff --git a/esp32c6/src/otp_debug/blk5_w5.rs b/esp32c6/src/otp_debug/blk5_w5.rs
index f3bf48f23c..b44ae493db 100644
--- a/esp32c6/src/otp_debug/blk5_w5.rs
+++ b/esp32c6/src/otp_debug/blk5_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W5")
-            .field("block5_w5", &format_args!("{}", self.block5_w5().bits()))
+            .field("block5_w5", &self.block5_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W5_SPEC;
 impl crate::RegisterSpec for BLK5_W5_SPEC {
diff --git a/esp32c6/src/otp_debug/blk5_w6.rs b/esp32c6/src/otp_debug/blk5_w6.rs
index 46623f1591..c538b4313e 100644
--- a/esp32c6/src/otp_debug/blk5_w6.rs
+++ b/esp32c6/src/otp_debug/blk5_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W6")
-            .field("block5_w6", &format_args!("{}", self.block5_w6().bits()))
+            .field("block5_w6", &self.block5_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W6_SPEC;
 impl crate::RegisterSpec for BLK5_W6_SPEC {
diff --git a/esp32c6/src/otp_debug/blk5_w7.rs b/esp32c6/src/otp_debug/blk5_w7.rs
index 105c530f5a..dbf5d69798 100644
--- a/esp32c6/src/otp_debug/blk5_w7.rs
+++ b/esp32c6/src/otp_debug/blk5_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W7")
-            .field("block5_w7", &format_args!("{}", self.block5_w7().bits()))
+            .field("block5_w7", &self.block5_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W7_SPEC;
 impl crate::RegisterSpec for BLK5_W7_SPEC {
diff --git a/esp32c6/src/otp_debug/blk5_w8.rs b/esp32c6/src/otp_debug/blk5_w8.rs
index 68ed1fe83a..f9c8303bc3 100644
--- a/esp32c6/src/otp_debug/blk5_w8.rs
+++ b/esp32c6/src/otp_debug/blk5_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W8")
-            .field("block5_w8", &format_args!("{}", self.block5_w8().bits()))
+            .field("block5_w8", &self.block5_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W8_SPEC;
 impl crate::RegisterSpec for BLK5_W8_SPEC {
diff --git a/esp32c6/src/otp_debug/blk5_w9.rs b/esp32c6/src/otp_debug/blk5_w9.rs
index 3a34129f31..3dbea1f968 100644
--- a/esp32c6/src/otp_debug/blk5_w9.rs
+++ b/esp32c6/src/otp_debug/blk5_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W9")
-            .field("block5_w9", &format_args!("{}", self.block5_w9().bits()))
+            .field("block5_w9", &self.block5_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W9_SPEC;
 impl crate::RegisterSpec for BLK5_W9_SPEC {
diff --git a/esp32c6/src/otp_debug/blk6_w1.rs b/esp32c6/src/otp_debug/blk6_w1.rs
index e9453208fd..343e3e92a4 100644
--- a/esp32c6/src/otp_debug/blk6_w1.rs
+++ b/esp32c6/src/otp_debug/blk6_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W1")
-            .field("block6_w1", &format_args!("{}", self.block6_w1().bits()))
+            .field("block6_w1", &self.block6_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W1_SPEC;
 impl crate::RegisterSpec for BLK6_W1_SPEC {
diff --git a/esp32c6/src/otp_debug/blk6_w10.rs b/esp32c6/src/otp_debug/blk6_w10.rs
index 7825b4acb8..625b8d134d 100644
--- a/esp32c6/src/otp_debug/blk6_w10.rs
+++ b/esp32c6/src/otp_debug/blk6_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W10")
-            .field("block6_w10", &format_args!("{}", self.block6_w10().bits()))
+            .field("block6_w10", &self.block6_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W10_SPEC;
 impl crate::RegisterSpec for BLK6_W10_SPEC {
diff --git a/esp32c6/src/otp_debug/blk6_w11.rs b/esp32c6/src/otp_debug/blk6_w11.rs
index 193bf513fa..fb791c1e6a 100644
--- a/esp32c6/src/otp_debug/blk6_w11.rs
+++ b/esp32c6/src/otp_debug/blk6_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W11")
-            .field("block6_w11", &format_args!("{}", self.block6_w11().bits()))
+            .field("block6_w11", &self.block6_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W11_SPEC;
 impl crate::RegisterSpec for BLK6_W11_SPEC {
diff --git a/esp32c6/src/otp_debug/blk6_w2.rs b/esp32c6/src/otp_debug/blk6_w2.rs
index 60a60f18ce..af4a9733d9 100644
--- a/esp32c6/src/otp_debug/blk6_w2.rs
+++ b/esp32c6/src/otp_debug/blk6_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W2")
-            .field("block6_w2", &format_args!("{}", self.block6_w2().bits()))
+            .field("block6_w2", &self.block6_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W2_SPEC;
 impl crate::RegisterSpec for BLK6_W2_SPEC {
diff --git a/esp32c6/src/otp_debug/blk6_w3.rs b/esp32c6/src/otp_debug/blk6_w3.rs
index 566e5baad2..24472421f2 100644
--- a/esp32c6/src/otp_debug/blk6_w3.rs
+++ b/esp32c6/src/otp_debug/blk6_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W3")
-            .field("block6_w3", &format_args!("{}", self.block6_w3().bits()))
+            .field("block6_w3", &self.block6_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W3_SPEC;
 impl crate::RegisterSpec for BLK6_W3_SPEC {
diff --git a/esp32c6/src/otp_debug/blk6_w4.rs b/esp32c6/src/otp_debug/blk6_w4.rs
index 358c27b0c8..3264bb4c66 100644
--- a/esp32c6/src/otp_debug/blk6_w4.rs
+++ b/esp32c6/src/otp_debug/blk6_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W4")
-            .field("block6_w4", &format_args!("{}", self.block6_w4().bits()))
+            .field("block6_w4", &self.block6_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W4_SPEC;
 impl crate::RegisterSpec for BLK6_W4_SPEC {
diff --git a/esp32c6/src/otp_debug/blk6_w5.rs b/esp32c6/src/otp_debug/blk6_w5.rs
index 10cefed773..acd1b40103 100644
--- a/esp32c6/src/otp_debug/blk6_w5.rs
+++ b/esp32c6/src/otp_debug/blk6_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W5")
-            .field("block6_w5", &format_args!("{}", self.block6_w5().bits()))
+            .field("block6_w5", &self.block6_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W5_SPEC;
 impl crate::RegisterSpec for BLK6_W5_SPEC {
diff --git a/esp32c6/src/otp_debug/blk6_w6.rs b/esp32c6/src/otp_debug/blk6_w6.rs
index 4cf1db7bde..f6e8bc051b 100644
--- a/esp32c6/src/otp_debug/blk6_w6.rs
+++ b/esp32c6/src/otp_debug/blk6_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W6")
-            .field("block6_w6", &format_args!("{}", self.block6_w6().bits()))
+            .field("block6_w6", &self.block6_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W6_SPEC;
 impl crate::RegisterSpec for BLK6_W6_SPEC {
diff --git a/esp32c6/src/otp_debug/blk6_w7.rs b/esp32c6/src/otp_debug/blk6_w7.rs
index 56faec9876..07e11cb4ae 100644
--- a/esp32c6/src/otp_debug/blk6_w7.rs
+++ b/esp32c6/src/otp_debug/blk6_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W7")
-            .field("block6_w7", &format_args!("{}", self.block6_w7().bits()))
+            .field("block6_w7", &self.block6_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W7_SPEC;
 impl crate::RegisterSpec for BLK6_W7_SPEC {
diff --git a/esp32c6/src/otp_debug/blk6_w8.rs b/esp32c6/src/otp_debug/blk6_w8.rs
index 6be9f9605a..2e437a5ddd 100644
--- a/esp32c6/src/otp_debug/blk6_w8.rs
+++ b/esp32c6/src/otp_debug/blk6_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W8")
-            .field("block6_w8", &format_args!("{}", self.block6_w8().bits()))
+            .field("block6_w8", &self.block6_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W8_SPEC;
 impl crate::RegisterSpec for BLK6_W8_SPEC {
diff --git a/esp32c6/src/otp_debug/blk6_w9.rs b/esp32c6/src/otp_debug/blk6_w9.rs
index 7facf7ee7a..171b61a72c 100644
--- a/esp32c6/src/otp_debug/blk6_w9.rs
+++ b/esp32c6/src/otp_debug/blk6_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W9")
-            .field("block6_w9", &format_args!("{}", self.block6_w9().bits()))
+            .field("block6_w9", &self.block6_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W9_SPEC;
 impl crate::RegisterSpec for BLK6_W9_SPEC {
diff --git a/esp32c6/src/otp_debug/blk7_w1.rs b/esp32c6/src/otp_debug/blk7_w1.rs
index 80485b44e1..953f022635 100644
--- a/esp32c6/src/otp_debug/blk7_w1.rs
+++ b/esp32c6/src/otp_debug/blk7_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W1")
-            .field("block7_w1", &format_args!("{}", self.block7_w1().bits()))
+            .field("block7_w1", &self.block7_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W1_SPEC;
 impl crate::RegisterSpec for BLK7_W1_SPEC {
diff --git a/esp32c6/src/otp_debug/blk7_w10.rs b/esp32c6/src/otp_debug/blk7_w10.rs
index 214f492311..706ebfaf45 100644
--- a/esp32c6/src/otp_debug/blk7_w10.rs
+++ b/esp32c6/src/otp_debug/blk7_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W10")
-            .field("block7_w10", &format_args!("{}", self.block7_w10().bits()))
+            .field("block7_w10", &self.block7_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W10_SPEC;
 impl crate::RegisterSpec for BLK7_W10_SPEC {
diff --git a/esp32c6/src/otp_debug/blk7_w11.rs b/esp32c6/src/otp_debug/blk7_w11.rs
index b3f3460741..2eabab4d9b 100644
--- a/esp32c6/src/otp_debug/blk7_w11.rs
+++ b/esp32c6/src/otp_debug/blk7_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W11")
-            .field("block7_w11", &format_args!("{}", self.block7_w11().bits()))
+            .field("block7_w11", &self.block7_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W11_SPEC;
 impl crate::RegisterSpec for BLK7_W11_SPEC {
diff --git a/esp32c6/src/otp_debug/blk7_w2.rs b/esp32c6/src/otp_debug/blk7_w2.rs
index 9e07a04cf8..fe5222fc76 100644
--- a/esp32c6/src/otp_debug/blk7_w2.rs
+++ b/esp32c6/src/otp_debug/blk7_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W2")
-            .field("block7_w2", &format_args!("{}", self.block7_w2().bits()))
+            .field("block7_w2", &self.block7_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W2_SPEC;
 impl crate::RegisterSpec for BLK7_W2_SPEC {
diff --git a/esp32c6/src/otp_debug/blk7_w3.rs b/esp32c6/src/otp_debug/blk7_w3.rs
index 3e91589aa2..b6b342544a 100644
--- a/esp32c6/src/otp_debug/blk7_w3.rs
+++ b/esp32c6/src/otp_debug/blk7_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W3")
-            .field("block7_w3", &format_args!("{}", self.block7_w3().bits()))
+            .field("block7_w3", &self.block7_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W3_SPEC;
 impl crate::RegisterSpec for BLK7_W3_SPEC {
diff --git a/esp32c6/src/otp_debug/blk7_w4.rs b/esp32c6/src/otp_debug/blk7_w4.rs
index e2e86f8a1d..1c12561404 100644
--- a/esp32c6/src/otp_debug/blk7_w4.rs
+++ b/esp32c6/src/otp_debug/blk7_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W4")
-            .field("block7_w4", &format_args!("{}", self.block7_w4().bits()))
+            .field("block7_w4", &self.block7_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W4_SPEC;
 impl crate::RegisterSpec for BLK7_W4_SPEC {
diff --git a/esp32c6/src/otp_debug/blk7_w5.rs b/esp32c6/src/otp_debug/blk7_w5.rs
index a1ce038db9..985a92fc34 100644
--- a/esp32c6/src/otp_debug/blk7_w5.rs
+++ b/esp32c6/src/otp_debug/blk7_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W5")
-            .field("block7_w5", &format_args!("{}", self.block7_w5().bits()))
+            .field("block7_w5", &self.block7_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W5_SPEC;
 impl crate::RegisterSpec for BLK7_W5_SPEC {
diff --git a/esp32c6/src/otp_debug/blk7_w6.rs b/esp32c6/src/otp_debug/blk7_w6.rs
index 1d953fee1b..6e2d3618c4 100644
--- a/esp32c6/src/otp_debug/blk7_w6.rs
+++ b/esp32c6/src/otp_debug/blk7_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W6")
-            .field("block7_w6", &format_args!("{}", self.block7_w6().bits()))
+            .field("block7_w6", &self.block7_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W6_SPEC;
 impl crate::RegisterSpec for BLK7_W6_SPEC {
diff --git a/esp32c6/src/otp_debug/blk7_w7.rs b/esp32c6/src/otp_debug/blk7_w7.rs
index 920a0c91e8..d7a4aadd41 100644
--- a/esp32c6/src/otp_debug/blk7_w7.rs
+++ b/esp32c6/src/otp_debug/blk7_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W7")
-            .field("block7_w7", &format_args!("{}", self.block7_w7().bits()))
+            .field("block7_w7", &self.block7_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W7_SPEC;
 impl crate::RegisterSpec for BLK7_W7_SPEC {
diff --git a/esp32c6/src/otp_debug/blk7_w8.rs b/esp32c6/src/otp_debug/blk7_w8.rs
index 5bba8ed30f..faab2a5a36 100644
--- a/esp32c6/src/otp_debug/blk7_w8.rs
+++ b/esp32c6/src/otp_debug/blk7_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W8")
-            .field("block7_w8", &format_args!("{}", self.block7_w8().bits()))
+            .field("block7_w8", &self.block7_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W8_SPEC;
 impl crate::RegisterSpec for BLK7_W8_SPEC {
diff --git a/esp32c6/src/otp_debug/blk7_w9.rs b/esp32c6/src/otp_debug/blk7_w9.rs
index a22a4d8605..a033967560 100644
--- a/esp32c6/src/otp_debug/blk7_w9.rs
+++ b/esp32c6/src/otp_debug/blk7_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W9")
-            .field("block7_w9", &format_args!("{}", self.block7_w9().bits()))
+            .field("block7_w9", &self.block7_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W9_SPEC;
 impl crate::RegisterSpec for BLK7_W9_SPEC {
diff --git a/esp32c6/src/otp_debug/blk8_w1.rs b/esp32c6/src/otp_debug/blk8_w1.rs
index 0af67c78d4..4e79d971fd 100644
--- a/esp32c6/src/otp_debug/blk8_w1.rs
+++ b/esp32c6/src/otp_debug/blk8_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W1")
-            .field("block8_w1", &format_args!("{}", self.block8_w1().bits()))
+            .field("block8_w1", &self.block8_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W1_SPEC;
 impl crate::RegisterSpec for BLK8_W1_SPEC {
diff --git a/esp32c6/src/otp_debug/blk8_w10.rs b/esp32c6/src/otp_debug/blk8_w10.rs
index ba08b40c1e..1381edc72c 100644
--- a/esp32c6/src/otp_debug/blk8_w10.rs
+++ b/esp32c6/src/otp_debug/blk8_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W10")
-            .field("block8_w10", &format_args!("{}", self.block8_w10().bits()))
+            .field("block8_w10", &self.block8_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W10_SPEC;
 impl crate::RegisterSpec for BLK8_W10_SPEC {
diff --git a/esp32c6/src/otp_debug/blk8_w11.rs b/esp32c6/src/otp_debug/blk8_w11.rs
index 949f8e12a1..e5be523d13 100644
--- a/esp32c6/src/otp_debug/blk8_w11.rs
+++ b/esp32c6/src/otp_debug/blk8_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W11")
-            .field("block8_w11", &format_args!("{}", self.block8_w11().bits()))
+            .field("block8_w11", &self.block8_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W11_SPEC;
 impl crate::RegisterSpec for BLK8_W11_SPEC {
diff --git a/esp32c6/src/otp_debug/blk8_w2.rs b/esp32c6/src/otp_debug/blk8_w2.rs
index bf021534a5..d4d5a69b8e 100644
--- a/esp32c6/src/otp_debug/blk8_w2.rs
+++ b/esp32c6/src/otp_debug/blk8_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W2")
-            .field("block8_w2", &format_args!("{}", self.block8_w2().bits()))
+            .field("block8_w2", &self.block8_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W2_SPEC;
 impl crate::RegisterSpec for BLK8_W2_SPEC {
diff --git a/esp32c6/src/otp_debug/blk8_w3.rs b/esp32c6/src/otp_debug/blk8_w3.rs
index 523bf87329..103e7a673c 100644
--- a/esp32c6/src/otp_debug/blk8_w3.rs
+++ b/esp32c6/src/otp_debug/blk8_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W3")
-            .field("block8_w3", &format_args!("{}", self.block8_w3().bits()))
+            .field("block8_w3", &self.block8_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W3_SPEC;
 impl crate::RegisterSpec for BLK8_W3_SPEC {
diff --git a/esp32c6/src/otp_debug/blk8_w4.rs b/esp32c6/src/otp_debug/blk8_w4.rs
index f92c4bb25b..2e63831f7c 100644
--- a/esp32c6/src/otp_debug/blk8_w4.rs
+++ b/esp32c6/src/otp_debug/blk8_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W4")
-            .field("block8_w4", &format_args!("{}", self.block8_w4().bits()))
+            .field("block8_w4", &self.block8_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W4_SPEC;
 impl crate::RegisterSpec for BLK8_W4_SPEC {
diff --git a/esp32c6/src/otp_debug/blk8_w5.rs b/esp32c6/src/otp_debug/blk8_w5.rs
index 7f85b35cf8..a5bc28e17e 100644
--- a/esp32c6/src/otp_debug/blk8_w5.rs
+++ b/esp32c6/src/otp_debug/blk8_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W5")
-            .field("block8_w5", &format_args!("{}", self.block8_w5().bits()))
+            .field("block8_w5", &self.block8_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W5_SPEC;
 impl crate::RegisterSpec for BLK8_W5_SPEC {
diff --git a/esp32c6/src/otp_debug/blk8_w6.rs b/esp32c6/src/otp_debug/blk8_w6.rs
index 2765e910f5..68370cf265 100644
--- a/esp32c6/src/otp_debug/blk8_w6.rs
+++ b/esp32c6/src/otp_debug/blk8_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W6")
-            .field("block8_w6", &format_args!("{}", self.block8_w6().bits()))
+            .field("block8_w6", &self.block8_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W6_SPEC;
 impl crate::RegisterSpec for BLK8_W6_SPEC {
diff --git a/esp32c6/src/otp_debug/blk8_w7.rs b/esp32c6/src/otp_debug/blk8_w7.rs
index ce91180a22..b83a3e6494 100644
--- a/esp32c6/src/otp_debug/blk8_w7.rs
+++ b/esp32c6/src/otp_debug/blk8_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W7")
-            .field("block8_w7", &format_args!("{}", self.block8_w7().bits()))
+            .field("block8_w7", &self.block8_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W7_SPEC;
 impl crate::RegisterSpec for BLK8_W7_SPEC {
diff --git a/esp32c6/src/otp_debug/blk8_w8.rs b/esp32c6/src/otp_debug/blk8_w8.rs
index 436f9e02fa..e4085f8d27 100644
--- a/esp32c6/src/otp_debug/blk8_w8.rs
+++ b/esp32c6/src/otp_debug/blk8_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W8")
-            .field("block8_w8", &format_args!("{}", self.block8_w8().bits()))
+            .field("block8_w8", &self.block8_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W8_SPEC;
 impl crate::RegisterSpec for BLK8_W8_SPEC {
diff --git a/esp32c6/src/otp_debug/blk8_w9.rs b/esp32c6/src/otp_debug/blk8_w9.rs
index 9ade621239..dbada70184 100644
--- a/esp32c6/src/otp_debug/blk8_w9.rs
+++ b/esp32c6/src/otp_debug/blk8_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W9")
-            .field("block8_w9", &format_args!("{}", self.block8_w9().bits()))
+            .field("block8_w9", &self.block8_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W9_SPEC;
 impl crate::RegisterSpec for BLK8_W9_SPEC {
diff --git a/esp32c6/src/otp_debug/blk9_w1.rs b/esp32c6/src/otp_debug/blk9_w1.rs
index acca201d3b..d013ce0d24 100644
--- a/esp32c6/src/otp_debug/blk9_w1.rs
+++ b/esp32c6/src/otp_debug/blk9_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W1")
-            .field("block9_w1", &format_args!("{}", self.block9_w1().bits()))
+            .field("block9_w1", &self.block9_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W1_SPEC;
 impl crate::RegisterSpec for BLK9_W1_SPEC {
diff --git a/esp32c6/src/otp_debug/blk9_w10.rs b/esp32c6/src/otp_debug/blk9_w10.rs
index aa47b611b6..00055c838d 100644
--- a/esp32c6/src/otp_debug/blk9_w10.rs
+++ b/esp32c6/src/otp_debug/blk9_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W10")
-            .field("block9_w10", &format_args!("{}", self.block9_w10().bits()))
+            .field("block9_w10", &self.block9_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W10_SPEC;
 impl crate::RegisterSpec for BLK9_W10_SPEC {
diff --git a/esp32c6/src/otp_debug/blk9_w11.rs b/esp32c6/src/otp_debug/blk9_w11.rs
index 6b2faa3d5a..9c2dd39808 100644
--- a/esp32c6/src/otp_debug/blk9_w11.rs
+++ b/esp32c6/src/otp_debug/blk9_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W11")
-            .field("block9_w11", &format_args!("{}", self.block9_w11().bits()))
+            .field("block9_w11", &self.block9_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W11_SPEC;
 impl crate::RegisterSpec for BLK9_W11_SPEC {
diff --git a/esp32c6/src/otp_debug/blk9_w2.rs b/esp32c6/src/otp_debug/blk9_w2.rs
index 915520083d..25cb9ef088 100644
--- a/esp32c6/src/otp_debug/blk9_w2.rs
+++ b/esp32c6/src/otp_debug/blk9_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W2")
-            .field("block9_w2", &format_args!("{}", self.block9_w2().bits()))
+            .field("block9_w2", &self.block9_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W2_SPEC;
 impl crate::RegisterSpec for BLK9_W2_SPEC {
diff --git a/esp32c6/src/otp_debug/blk9_w3.rs b/esp32c6/src/otp_debug/blk9_w3.rs
index 548d780f66..7eacf6c029 100644
--- a/esp32c6/src/otp_debug/blk9_w3.rs
+++ b/esp32c6/src/otp_debug/blk9_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W3")
-            .field("block9_w3", &format_args!("{}", self.block9_w3().bits()))
+            .field("block9_w3", &self.block9_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W3_SPEC;
 impl crate::RegisterSpec for BLK9_W3_SPEC {
diff --git a/esp32c6/src/otp_debug/blk9_w4.rs b/esp32c6/src/otp_debug/blk9_w4.rs
index eff6ebfd0c..82cefd4210 100644
--- a/esp32c6/src/otp_debug/blk9_w4.rs
+++ b/esp32c6/src/otp_debug/blk9_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W4")
-            .field("block9_w4", &format_args!("{}", self.block9_w4().bits()))
+            .field("block9_w4", &self.block9_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W4_SPEC;
 impl crate::RegisterSpec for BLK9_W4_SPEC {
diff --git a/esp32c6/src/otp_debug/blk9_w5.rs b/esp32c6/src/otp_debug/blk9_w5.rs
index 5b09ef7a05..1acfee20c5 100644
--- a/esp32c6/src/otp_debug/blk9_w5.rs
+++ b/esp32c6/src/otp_debug/blk9_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W5")
-            .field("block9_w5", &format_args!("{}", self.block9_w5().bits()))
+            .field("block9_w5", &self.block9_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W5_SPEC;
 impl crate::RegisterSpec for BLK9_W5_SPEC {
diff --git a/esp32c6/src/otp_debug/blk9_w6.rs b/esp32c6/src/otp_debug/blk9_w6.rs
index f63889fd3e..ca6c901a32 100644
--- a/esp32c6/src/otp_debug/blk9_w6.rs
+++ b/esp32c6/src/otp_debug/blk9_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W6")
-            .field("block9_w6", &format_args!("{}", self.block9_w6().bits()))
+            .field("block9_w6", &self.block9_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W6_SPEC;
 impl crate::RegisterSpec for BLK9_W6_SPEC {
diff --git a/esp32c6/src/otp_debug/blk9_w7.rs b/esp32c6/src/otp_debug/blk9_w7.rs
index 754d05ce7f..bbea29fee2 100644
--- a/esp32c6/src/otp_debug/blk9_w7.rs
+++ b/esp32c6/src/otp_debug/blk9_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W7")
-            .field("block9_w7", &format_args!("{}", self.block9_w7().bits()))
+            .field("block9_w7", &self.block9_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W7_SPEC;
 impl crate::RegisterSpec for BLK9_W7_SPEC {
diff --git a/esp32c6/src/otp_debug/blk9_w8.rs b/esp32c6/src/otp_debug/blk9_w8.rs
index 9c831a26fb..e76368eea3 100644
--- a/esp32c6/src/otp_debug/blk9_w8.rs
+++ b/esp32c6/src/otp_debug/blk9_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W8")
-            .field("block9_w8", &format_args!("{}", self.block9_w8().bits()))
+            .field("block9_w8", &self.block9_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W8_SPEC;
 impl crate::RegisterSpec for BLK9_W8_SPEC {
diff --git a/esp32c6/src/otp_debug/blk9_w9.rs b/esp32c6/src/otp_debug/blk9_w9.rs
index 76b68ee02d..d195ede687 100644
--- a/esp32c6/src/otp_debug/blk9_w9.rs
+++ b/esp32c6/src/otp_debug/blk9_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W9")
-            .field("block9_w9", &format_args!("{}", self.block9_w9().bits()))
+            .field("block9_w9", &self.block9_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W9_SPEC;
 impl crate::RegisterSpec for BLK9_W9_SPEC {
diff --git a/esp32c6/src/otp_debug/clk.rs b/esp32c6/src/otp_debug/clk.rs
index cd8a296128..91629e6db5 100644
--- a/esp32c6/src/otp_debug/clk.rs
+++ b/esp32c6/src/otp_debug/clk.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CLK")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CLK").field("en", &self.en()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/otp_debug/date.rs b/esp32c6/src/otp_debug/date.rs
index acdf609e44..f2efcdc72d 100644
--- a/esp32c6/src/otp_debug/date.rs
+++ b/esp32c6/src/otp_debug/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/otp_debug/wr_dis.rs b/esp32c6/src/otp_debug/wr_dis.rs
index ea6ee4f522..2cd94211cf 100644
--- a/esp32c6/src/otp_debug/wr_dis.rs
+++ b/esp32c6/src/otp_debug/wr_dis.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_DIS")
-            .field(
-                "block0_wr_dis",
-                &format_args!("{}", self.block0_wr_dis().bits()),
-            )
+            .field("block0_wr_dis", &self.block0_wr_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_DIS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_dis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WR_DIS_SPEC;
 impl crate::RegisterSpec for WR_DIS_SPEC {
diff --git a/esp32c6/src/parl_io/clk.rs b/esp32c6/src/parl_io/clk.rs
index 1c5d1b4b4e..3f256ee6a0 100644
--- a/esp32c6/src/parl_io/clk.rs
+++ b/esp32c6/src/parl_io/clk.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CLK")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CLK").field("en", &self.en()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/parl_io/int_ena.rs b/esp32c6/src/parl_io/int_ena.rs
index ee39d6eced..84a4998b20 100644
--- a/esp32c6/src/parl_io/int_ena.rs
+++ b/esp32c6/src/parl_io/int_ena.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "tx_fifo_rempty",
-                &format_args!("{}", self.tx_fifo_rempty().bit()),
-            )
-            .field(
-                "rx_fifo_wovf",
-                &format_args!("{}", self.rx_fifo_wovf().bit()),
-            )
-            .field("tx_eof", &format_args!("{}", self.tx_eof().bit()))
+            .field("tx_fifo_rempty", &self.tx_fifo_rempty())
+            .field("rx_fifo_wovf", &self.rx_fifo_wovf())
+            .field("tx_eof", &self.tx_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to enable TX_FIFO_REMPTY_INTR."]
     #[inline(always)]
diff --git a/esp32c6/src/parl_io/int_raw.rs b/esp32c6/src/parl_io/int_raw.rs
index e2d3533586..cbb26be5de 100644
--- a/esp32c6/src/parl_io/int_raw.rs
+++ b/esp32c6/src/parl_io/int_raw.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "tx_fifo_rempty",
-                &format_args!("{}", self.tx_fifo_rempty().bit()),
-            )
-            .field(
-                "rx_fifo_wovf",
-                &format_args!("{}", self.rx_fifo_wovf().bit()),
-            )
-            .field("tx_eof", &format_args!("{}", self.tx_eof().bit()))
+            .field("tx_fifo_rempty", &self.tx_fifo_rempty())
+            .field("rx_fifo_wovf", &self.rx_fifo_wovf())
+            .field("tx_eof", &self.tx_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt status of TX_FIFO_REMPTY_INTR."]
     #[inline(always)]
diff --git a/esp32c6/src/parl_io/int_st.rs b/esp32c6/src/parl_io/int_st.rs
index e8b8cdf619..4df7be663d 100644
--- a/esp32c6/src/parl_io/int_st.rs
+++ b/esp32c6/src/parl_io/int_st.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "tx_fifo_rempty",
-                &format_args!("{}", self.tx_fifo_rempty().bit()),
-            )
-            .field(
-                "rx_fifo_wovf",
-                &format_args!("{}", self.rx_fifo_wovf().bit()),
-            )
-            .field("tx_eof", &format_args!("{}", self.tx_eof().bit()))
+            .field("tx_fifo_rempty", &self.tx_fifo_rempty())
+            .field("rx_fifo_wovf", &self.rx_fifo_wovf())
+            .field("tx_eof", &self.tx_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Parallel IO interrupt singal status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/parl_io/rx_cfg0.rs b/esp32c6/src/parl_io/rx_cfg0.rs
index 31fc647931..8356d44f9f 100644
--- a/esp32c6/src/parl_io/rx_cfg0.rs
+++ b/esp32c6/src/parl_io/rx_cfg0.rs
@@ -107,53 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CFG0")
-            .field(
-                "rx_eof_gen_sel",
-                &format_args!("{}", self.rx_eof_gen_sel().bit()),
-            )
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field(
-                "rx_data_bytelen",
-                &format_args!("{}", self.rx_data_bytelen().bits()),
-            )
-            .field("rx_sw_en", &format_args!("{}", self.rx_sw_en().bit()))
-            .field(
-                "rx_pulse_submode_sel",
-                &format_args!("{}", self.rx_pulse_submode_sel().bits()),
-            )
-            .field(
-                "rx_level_submode_sel",
-                &format_args!("{}", self.rx_level_submode_sel().bit()),
-            )
-            .field(
-                "rx_smp_mode_sel",
-                &format_args!("{}", self.rx_smp_mode_sel().bits()),
-            )
-            .field(
-                "rx_clk_edge_sel",
-                &format_args!("{}", self.rx_clk_edge_sel().bit()),
-            )
-            .field(
-                "rx_bit_pack_order",
-                &format_args!("{}", self.rx_bit_pack_order().bit()),
-            )
-            .field(
-                "rx_bus_wid_sel",
-                &format_args!("{}", self.rx_bus_wid_sel().bits()),
-            )
-            .field(
-                "rx_fifo_srst",
-                &format_args!("{}", self.rx_fifo_srst().bit()),
-            )
+            .field("rx_eof_gen_sel", &self.rx_eof_gen_sel())
+            .field("rx_start", &self.rx_start())
+            .field("rx_data_bytelen", &self.rx_data_bytelen())
+            .field("rx_sw_en", &self.rx_sw_en())
+            .field("rx_pulse_submode_sel", &self.rx_pulse_submode_sel())
+            .field("rx_level_submode_sel", &self.rx_level_submode_sel())
+            .field("rx_smp_mode_sel", &self.rx_smp_mode_sel())
+            .field("rx_clk_edge_sel", &self.rx_clk_edge_sel())
+            .field("rx_bit_pack_order", &self.rx_bit_pack_order())
+            .field("rx_bus_wid_sel", &self.rx_bus_wid_sel())
+            .field("rx_fifo_srst", &self.rx_fifo_srst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 0 to select eof generated manchnism by configured data byte length. Write 1 to select eof generated manchnism by external enable signal."]
     #[inline(always)]
diff --git a/esp32c6/src/parl_io/rx_cfg1.rs b/esp32c6/src/parl_io/rx_cfg1.rs
index 87eaf642dc..f2fc014e51 100644
--- a/esp32c6/src/parl_io/rx_cfg1.rs
+++ b/esp32c6/src/parl_io/rx_cfg1.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CFG1")
-            .field(
-                "rx_timeout_en",
-                &format_args!("{}", self.rx_timeout_en().bit()),
-            )
-            .field(
-                "rx_ext_en_sel",
-                &format_args!("{}", self.rx_ext_en_sel().bits()),
-            )
-            .field(
-                "rx_timeout_threshold",
-                &format_args!("{}", self.rx_timeout_threshold().bits()),
-            )
+            .field("rx_timeout_en", &self.rx_timeout_en())
+            .field("rx_ext_en_sel", &self.rx_ext_en_sel())
+            .field("rx_timeout_threshold", &self.rx_timeout_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - Write 1 to update rx register configuration signals."]
     #[inline(always)]
diff --git a/esp32c6/src/parl_io/st.rs b/esp32c6/src/parl_io/st.rs
index a75e27cac8..0c790f5b12 100644
--- a/esp32c6/src/parl_io/st.rs
+++ b/esp32c6/src/parl_io/st.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ST")
-            .field("tx_ready", &format_args!("{}", self.tx_ready().bit()))
+            .field("tx_ready", &self.tx_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Parallel IO module status register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ST_SPEC;
 impl crate::RegisterSpec for ST_SPEC {
diff --git a/esp32c6/src/parl_io/tx_cfg0.rs b/esp32c6/src/parl_io/tx_cfg0.rs
index 66b864f10b..d596ed4c1b 100644
--- a/esp32c6/src/parl_io/tx_cfg0.rs
+++ b/esp32c6/src/parl_io/tx_cfg0.rs
@@ -80,41 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CFG0")
-            .field("tx_bytelen", &format_args!("{}", self.tx_bytelen().bits()))
-            .field(
-                "tx_gating_en",
-                &format_args!("{}", self.tx_gating_en().bit()),
-            )
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field(
-                "tx_hw_valid_en",
-                &format_args!("{}", self.tx_hw_valid_en().bit()),
-            )
-            .field(
-                "tx_smp_edge_sel",
-                &format_args!("{}", self.tx_smp_edge_sel().bit()),
-            )
-            .field(
-                "tx_bit_unpack_order",
-                &format_args!("{}", self.tx_bit_unpack_order().bit()),
-            )
-            .field(
-                "tx_bus_wid_sel",
-                &format_args!("{}", self.tx_bus_wid_sel().bits()),
-            )
-            .field(
-                "tx_fifo_srst",
-                &format_args!("{}", self.tx_fifo_srst().bit()),
-            )
+            .field("tx_bytelen", &self.tx_bytelen())
+            .field("tx_gating_en", &self.tx_gating_en())
+            .field("tx_start", &self.tx_start())
+            .field("tx_hw_valid_en", &self.tx_hw_valid_en())
+            .field("tx_smp_edge_sel", &self.tx_smp_edge_sel())
+            .field("tx_bit_unpack_order", &self.tx_bit_unpack_order())
+            .field("tx_bus_wid_sel", &self.tx_bus_wid_sel())
+            .field("tx_fifo_srst", &self.tx_fifo_srst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 2:17 - Configures tx sending data byte length."]
     #[inline(always)]
diff --git a/esp32c6/src/parl_io/tx_cfg1.rs b/esp32c6/src/parl_io/tx_cfg1.rs
index bfb5df6f97..00338b90f6 100644
--- a/esp32c6/src/parl_io/tx_cfg1.rs
+++ b/esp32c6/src/parl_io/tx_cfg1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CFG1")
-            .field(
-                "tx_idle_value",
-                &format_args!("{}", self.tx_idle_value().bits()),
-            )
+            .field("tx_idle_value", &self.tx_idle_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Configures data value on tx bus when IDLE state."]
     #[inline(always)]
diff --git a/esp32c6/src/parl_io/version.rs b/esp32c6/src/parl_io/version.rs
index 71d59534b3..b1c3e4ac42 100644
--- a/esp32c6/src/parl_io/version.rs
+++ b/esp32c6/src/parl_io/version.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version of this register file"]
     #[inline(always)]
diff --git a/esp32c6/src/pau/date.rs b/esp32c6/src/pau/date.rs
index 3b18bdc4fe..0b7173416e 100644
--- a/esp32c6/src/pau/date.rs
+++ b/esp32c6/src/pau/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/pau/int_ena.rs b/esp32c6/src/pau/int_ena.rs
index a424ba5145..011fec4c81 100644
--- a/esp32c6/src/pau/int_ena.rs
+++ b/esp32c6/src/pau/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("error", &format_args!("{}", self.error().bit()))
+            .field("done", &self.done())
+            .field("error", &self.error())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - backup done flag"]
     #[inline(always)]
diff --git a/esp32c6/src/pau/int_raw.rs b/esp32c6/src/pau/int_raw.rs
index d0b1838f1a..1003c8ece8 100644
--- a/esp32c6/src/pau/int_raw.rs
+++ b/esp32c6/src/pau/int_raw.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("error", &format_args!("{}", self.error().bit()))
+            .field("done", &self.done())
+            .field("error", &self.error())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - backup done flag"]
     #[inline(always)]
diff --git a/esp32c6/src/pau/int_st.rs b/esp32c6/src/pau/int_st.rs
index 8a0bf89170..d6834ae88d 100644
--- a/esp32c6/src/pau/int_st.rs
+++ b/esp32c6/src/pau/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("error", &format_args!("{}", self.error().bit()))
+            .field("done", &self.done())
+            .field("error", &self.error())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read only register for error and done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/pau/regdma_backup_addr.rs b/esp32c6/src/pau/regdma_backup_addr.rs
index 3789b97494..06640e6e76 100644
--- a/esp32c6/src/pau/regdma_backup_addr.rs
+++ b/esp32c6/src/pau/regdma_backup_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_BACKUP_ADDR")
-            .field(
-                "backup_addr",
-                &format_args!("{}", self.backup_addr().bits()),
-            )
+            .field("backup_addr", &self.backup_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_BACKUP_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Backup addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_backup_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REGDMA_BACKUP_ADDR_SPEC;
 impl crate::RegisterSpec for REGDMA_BACKUP_ADDR_SPEC {
diff --git a/esp32c6/src/pau/regdma_bkp_conf.rs b/esp32c6/src/pau/regdma_bkp_conf.rs
index b373fb172b..e25f46eba5 100644
--- a/esp32c6/src/pau/regdma_bkp_conf.rs
+++ b/esp32c6/src/pau/regdma_bkp_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_BKP_CONF")
-            .field(
-                "read_interval",
-                &format_args!("{}", self.read_interval().bits()),
-            )
-            .field(
-                "link_tout_thres",
-                &format_args!("{}", self.link_tout_thres().bits()),
-            )
-            .field(
-                "burst_limit",
-                &format_args!("{}", self.burst_limit().bits()),
-            )
-            .field(
-                "backup_tout_thres",
-                &format_args!("{}", self.backup_tout_thres().bits()),
-            )
+            .field("read_interval", &self.read_interval())
+            .field("link_tout_thres", &self.link_tout_thres())
+            .field("burst_limit", &self.burst_limit())
+            .field("backup_tout_thres", &self.backup_tout_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_BKP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Link read_interval"]
     #[inline(always)]
diff --git a/esp32c6/src/pau/regdma_clk_conf.rs b/esp32c6/src/pau/regdma_clk_conf.rs
index c61741bd1f..fec6254df5 100644
--- a/esp32c6/src/pau/regdma_clk_conf.rs
+++ b/esp32c6/src/pau/regdma_clk_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_CLK_CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - clock enable"]
     #[inline(always)]
diff --git a/esp32c6/src/pau/regdma_conf.rs b/esp32c6/src/pau/regdma_conf.rs
index ea713cee3a..676f794539 100644
--- a/esp32c6/src/pau/regdma_conf.rs
+++ b/esp32c6/src/pau/regdma_conf.rs
@@ -55,20 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_CONF")
-            .field("flow_err", &format_args!("{}", self.flow_err().bits()))
-            .field("to_mem", &format_args!("{}", self.to_mem().bit()))
-            .field("link_sel", &format_args!("{}", self.link_sel().bits()))
-            .field("to_mem_mac", &format_args!("{}", self.to_mem_mac().bit()))
-            .field("sel_mac", &format_args!("{}", self.sel_mac().bit()))
+            .field("flow_err", &self.flow_err())
+            .field("to_mem", &self.to_mem())
+            .field("link_sel", &self.link_sel())
+            .field("to_mem_mac", &self.to_mem_mac())
+            .field("sel_mac", &self.sel_mac())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - backup start signal"]
     #[inline(always)]
diff --git a/esp32c6/src/pau/regdma_current_link_addr.rs b/esp32c6/src/pau/regdma_current_link_addr.rs
index 4ca2373a2b..7e5133b489 100644
--- a/esp32c6/src/pau/regdma_current_link_addr.rs
+++ b/esp32c6/src/pau/regdma_current_link_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_CURRENT_LINK_ADDR")
-            .field(
-                "current_link_addr",
-                &format_args!("{}", self.current_link_addr().bits()),
-            )
+            .field("current_link_addr", &self.current_link_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_CURRENT_LINK_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "current link addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_current_link_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REGDMA_CURRENT_LINK_ADDR_SPEC;
 impl crate::RegisterSpec for REGDMA_CURRENT_LINK_ADDR_SPEC {
diff --git a/esp32c6/src/pau/regdma_link_0_addr.rs b/esp32c6/src/pau/regdma_link_0_addr.rs
index f415b2ede1..64d3ebfd0a 100644
--- a/esp32c6/src/pau/regdma_link_0_addr.rs
+++ b/esp32c6/src/pau/regdma_link_0_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_LINK_0_ADDR")
-            .field(
-                "link_addr_0",
-                &format_args!("{}", self.link_addr_0().bits()),
-            )
+            .field("link_addr_0", &self.link_addr_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - link_0_addr reg"]
     #[inline(always)]
diff --git a/esp32c6/src/pau/regdma_link_1_addr.rs b/esp32c6/src/pau/regdma_link_1_addr.rs
index 2974370620..c0d1614d2e 100644
--- a/esp32c6/src/pau/regdma_link_1_addr.rs
+++ b/esp32c6/src/pau/regdma_link_1_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_LINK_1_ADDR")
-            .field(
-                "link_addr_1",
-                &format_args!("{}", self.link_addr_1().bits()),
-            )
+            .field("link_addr_1", &self.link_addr_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Link_1_addr reg"]
     #[inline(always)]
diff --git a/esp32c6/src/pau/regdma_link_2_addr.rs b/esp32c6/src/pau/regdma_link_2_addr.rs
index dc5d14f41e..913a395db9 100644
--- a/esp32c6/src/pau/regdma_link_2_addr.rs
+++ b/esp32c6/src/pau/regdma_link_2_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_LINK_2_ADDR")
-            .field(
-                "link_addr_2",
-                &format_args!("{}", self.link_addr_2().bits()),
-            )
+            .field("link_addr_2", &self.link_addr_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Link_2_addr reg"]
     #[inline(always)]
diff --git a/esp32c6/src/pau/regdma_link_3_addr.rs b/esp32c6/src/pau/regdma_link_3_addr.rs
index d8840a9794..1a77662e9c 100644
--- a/esp32c6/src/pau/regdma_link_3_addr.rs
+++ b/esp32c6/src/pau/regdma_link_3_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_LINK_3_ADDR")
-            .field(
-                "link_addr_3",
-                &format_args!("{}", self.link_addr_3().bits()),
-            )
+            .field("link_addr_3", &self.link_addr_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Link_3_addr reg"]
     #[inline(always)]
diff --git a/esp32c6/src/pau/regdma_link_mac_addr.rs b/esp32c6/src/pau/regdma_link_mac_addr.rs
index 9e524ad211..0781e7a9a0 100644
--- a/esp32c6/src/pau/regdma_link_mac_addr.rs
+++ b/esp32c6/src/pau/regdma_link_mac_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_LINK_MAC_ADDR")
-            .field(
-                "link_addr_mac",
-                &format_args!("{}", self.link_addr_mac().bits()),
-            )
+            .field("link_addr_mac", &self.link_addr_mac())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_MAC_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Link_mac_addr reg"]
     #[inline(always)]
diff --git a/esp32c6/src/pau/regdma_mem_addr.rs b/esp32c6/src/pau/regdma_mem_addr.rs
index b6fa3aa6d7..417bf965b3 100644
--- a/esp32c6/src/pau/regdma_mem_addr.rs
+++ b/esp32c6/src/pau/regdma_mem_addr.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_MEM_ADDR")
-            .field("mem_addr", &format_args!("{}", self.mem_addr().bits()))
+            .field("mem_addr", &self.mem_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_MEM_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_mem_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REGDMA_MEM_ADDR_SPEC;
 impl crate::RegisterSpec for REGDMA_MEM_ADDR_SPEC {
diff --git a/esp32c6/src/pau/retention_cfg.rs b/esp32c6/src/pau/retention_cfg.rs
index 3065e11d78..33850d9486 100644
--- a/esp32c6/src/pau/retention_cfg.rs
+++ b/esp32c6/src/pau/retention_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_CFG")
-            .field(
-                "ret_inv_cfg",
-                &format_args!("{}", self.ret_inv_cfg().bits()),
-            )
+            .field("ret_inv_cfg", &self.ret_inv_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - retention inv scan out"]
     #[inline(always)]
diff --git a/esp32c6/src/pau/retention_link_base.rs b/esp32c6/src/pau/retention_link_base.rs
index 4991b8f7b0..a1728a51c3 100644
--- a/esp32c6/src/pau/retention_link_base.rs
+++ b/esp32c6/src/pau/retention_link_base.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_LINK_BASE")
-            .field(
-                "link_base_addr",
-                &format_args!("{}", self.link_base_addr().bits()),
-            )
+            .field("link_base_addr", &self.link_base_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_LINK_BASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:26 - retention dma link base"]
     #[inline(always)]
diff --git a/esp32c6/src/pcnt/ctrl.rs b/esp32c6/src/pcnt/ctrl.rs
index 366f491032..5c3a942e13 100644
--- a/esp32c6/src/pcnt/ctrl.rs
+++ b/esp32c6/src/pcnt/ctrl.rs
@@ -95,36 +95,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("cnt_rst_u0", &format_args!("{}", self.cnt_rst_u0().bit()))
-            .field("cnt_rst_u1", &format_args!("{}", self.cnt_rst_u1().bit()))
-            .field("cnt_rst_u2", &format_args!("{}", self.cnt_rst_u2().bit()))
-            .field("cnt_rst_u3", &format_args!("{}", self.cnt_rst_u3().bit()))
-            .field(
-                "cnt_pause_u0",
-                &format_args!("{}", self.cnt_pause_u0().bit()),
-            )
-            .field(
-                "cnt_pause_u1",
-                &format_args!("{}", self.cnt_pause_u1().bit()),
-            )
-            .field(
-                "cnt_pause_u2",
-                &format_args!("{}", self.cnt_pause_u2().bit()),
-            )
-            .field(
-                "cnt_pause_u3",
-                &format_args!("{}", self.cnt_pause_u3().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("cnt_rst_u0", &self.cnt_rst_u0())
+            .field("cnt_rst_u1", &self.cnt_rst_u1())
+            .field("cnt_rst_u2", &self.cnt_rst_u2())
+            .field("cnt_rst_u3", &self.cnt_rst_u3())
+            .field("cnt_pause_u0", &self.cnt_pause_u0())
+            .field("cnt_pause_u1", &self.cnt_pause_u1())
+            .field("cnt_pause_u2", &self.cnt_pause_u2())
+            .field("cnt_pause_u3", &self.cnt_pause_u3())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Set this bit to clear unit(0-3)'s counter."]
     #[doc = ""]
diff --git a/esp32c6/src/pcnt/date.rs b/esp32c6/src/pcnt/date.rs
index daef1d7bcf..5a80a19072 100644
--- a/esp32c6/src/pcnt/date.rs
+++ b/esp32c6/src/pcnt/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/pcnt/int_ena.rs b/esp32c6/src/pcnt/int_ena.rs
index 4423a16c83..7372693fe3 100644
--- a/esp32c6/src/pcnt/int_ena.rs
+++ b/esp32c6/src/pcnt/int_ena.rs
@@ -47,31 +47,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
     #[doc = ""]
diff --git a/esp32c6/src/pcnt/int_raw.rs b/esp32c6/src/pcnt/int_raw.rs
index bd68f6891b..0e4e8347cf 100644
--- a/esp32c6/src/pcnt/int_raw.rs
+++ b/esp32c6/src/pcnt/int_raw.rs
@@ -43,31 +43,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt raw status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32c6/src/pcnt/int_st.rs b/esp32c6/src/pcnt/int_st.rs
index d1a59c1bf3..870d7ad253 100644
--- a/esp32c6/src/pcnt/int_st.rs
+++ b/esp32c6/src/pcnt/int_st.rs
@@ -43,31 +43,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/pcnt/u_cnt.rs b/esp32c6/src/pcnt/u_cnt.rs
index 34bef2c06c..7a45c58a0d 100644
--- a/esp32c6/src/pcnt/u_cnt.rs
+++ b/esp32c6/src/pcnt/u_cnt.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("U_CNT")
-            .field("cnt", &format_args!("{}", self.cnt().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("U_CNT").field("cnt", &self.cnt()).finish()
     }
 }
 #[doc = "Counter value for unit %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c6/src/pcnt/u_status.rs b/esp32c6/src/pcnt/u_status.rs
index 408d450824..9d516e2c99 100644
--- a/esp32c6/src/pcnt/u_status.rs
+++ b/esp32c6/src/pcnt/u_status.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("U_STATUS")
-            .field("zero_mode", &format_args!("{}", self.zero_mode().bits()))
-            .field("thres1", &format_args!("{}", self.thres1().bit()))
-            .field("thres0", &format_args!("{}", self.thres0().bit()))
-            .field("l_lim", &format_args!("{}", self.l_lim().bit()))
-            .field("h_lim", &format_args!("{}", self.h_lim().bit()))
-            .field("zero", &format_args!("{}", self.zero().bit()))
+            .field("zero_mode", &self.zero_mode())
+            .field("thres1", &self.thres1())
+            .field("thres0", &self.thres0())
+            .field("l_lim", &self.l_lim())
+            .field("h_lim", &self.h_lim())
+            .field("zero", &self.zero())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "PNCT UNIT%s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct U_STATUS_SPEC;
 impl crate::RegisterSpec for U_STATUS_SPEC {
diff --git a/esp32c6/src/pcnt/unit/conf0.rs b/esp32c6/src/pcnt/unit/conf0.rs
index 7be65a378c..a66e892dfa 100644
--- a/esp32c6/src/pcnt/unit/conf0.rs
+++ b/esp32c6/src/pcnt/unit/conf0.rs
@@ -325,69 +325,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field(
-                "filter_thres",
-                &format_args!("{}", self.filter_thres().bits()),
-            )
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
-            .field("thr_zero_en", &format_args!("{}", self.thr_zero_en().bit()))
-            .field(
-                "thr_h_lim_en",
-                &format_args!("{}", self.thr_h_lim_en().bit()),
-            )
-            .field(
-                "thr_l_lim_en",
-                &format_args!("{}", self.thr_l_lim_en().bit()),
-            )
-            .field(
-                "thr_thres0_en",
-                &format_args!("{}", self.thr_thres0_en().bit()),
-            )
-            .field(
-                "thr_thres1_en",
-                &format_args!("{}", self.thr_thres1_en().bit()),
-            )
-            .field(
-                "ch0_neg_mode",
-                &format_args!("{}", self.ch0_neg_mode().bits()),
-            )
-            .field(
-                "ch1_neg_mode",
-                &format_args!("{}", self.ch1_neg_mode().bits()),
-            )
-            .field(
-                "ch0_pos_mode",
-                &format_args!("{}", self.ch0_pos_mode().bits()),
-            )
-            .field(
-                "ch1_pos_mode",
-                &format_args!("{}", self.ch1_pos_mode().bits()),
-            )
-            .field(
-                "ch0_hctrl_mode",
-                &format_args!("{}", self.ch0_hctrl_mode().bits()),
-            )
-            .field(
-                "ch1_hctrl_mode",
-                &format_args!("{}", self.ch1_hctrl_mode().bits()),
-            )
-            .field(
-                "ch0_lctrl_mode",
-                &format_args!("{}", self.ch0_lctrl_mode().bits()),
-            )
-            .field(
-                "ch1_lctrl_mode",
-                &format_args!("{}", self.ch1_lctrl_mode().bits()),
-            )
+            .field("filter_thres", &self.filter_thres())
+            .field("filter_en", &self.filter_en())
+            .field("thr_zero_en", &self.thr_zero_en())
+            .field("thr_h_lim_en", &self.thr_h_lim_en())
+            .field("thr_l_lim_en", &self.thr_l_lim_en())
+            .field("thr_thres0_en", &self.thr_thres0_en())
+            .field("thr_thres1_en", &self.thr_thres1_en())
+            .field("ch0_neg_mode", &self.ch0_neg_mode())
+            .field("ch1_neg_mode", &self.ch1_neg_mode())
+            .field("ch0_pos_mode", &self.ch0_pos_mode())
+            .field("ch1_pos_mode", &self.ch1_pos_mode())
+            .field("ch0_hctrl_mode", &self.ch0_hctrl_mode())
+            .field("ch1_hctrl_mode", &self.ch1_hctrl_mode())
+            .field("ch0_lctrl_mode", &self.ch0_lctrl_mode())
+            .field("ch1_lctrl_mode", &self.ch1_lctrl_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
     #[inline(always)]
diff --git a/esp32c6/src/pcnt/unit/conf1.rs b/esp32c6/src/pcnt/unit/conf1.rs
index 62e92aa446..d516d127e6 100644
--- a/esp32c6/src/pcnt/unit/conf1.rs
+++ b/esp32c6/src/pcnt/unit/conf1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field("cnt_thres0", &format_args!("{}", self.cnt_thres0().bits()))
-            .field("cnt_thres1", &format_args!("{}", self.cnt_thres1().bits()))
+            .field("cnt_thres0", &self.cnt_thres0())
+            .field("cnt_thres1", &self.cnt_thres1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the thres0 value for unit %s."]
     #[inline(always)]
diff --git a/esp32c6/src/pcnt/unit/conf2.rs b/esp32c6/src/pcnt/unit/conf2.rs
index 85e906ae09..25118d3c9c 100644
--- a/esp32c6/src/pcnt/unit/conf2.rs
+++ b/esp32c6/src/pcnt/unit/conf2.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF2")
-            .field("cnt_h_lim", &format_args!("{}", self.cnt_h_lim().bits()))
-            .field("cnt_l_lim", &format_args!("{}", self.cnt_l_lim().bits()))
+            .field("cnt_h_lim", &self.cnt_h_lim())
+            .field("cnt_l_lim", &self.cnt_l_lim())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the thr_h_lim value for unit %s."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/aes_conf.rs b/esp32c6/src/pcr/aes_conf.rs
index 6cecde374f..3598a54eff 100644
--- a/esp32c6/src/pcr/aes_conf.rs
+++ b/esp32c6/src/pcr/aes_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AES_CONF")
-            .field("aes_clk_en", &format_args!("{}", self.aes_clk_en().bit()))
-            .field("aes_rst_en", &format_args!("{}", self.aes_rst_en().bit()))
+            .field("aes_clk_en", &self.aes_clk_en())
+            .field("aes_rst_en", &self.aes_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AES_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable aes clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/ahb_freq_conf.rs b/esp32c6/src/pcr/ahb_freq_conf.rs
index 86f511f76e..4fbec43c42 100644
--- a/esp32c6/src/pcr/ahb_freq_conf.rs
+++ b/esp32c6/src/pcr/ahb_freq_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_FREQ_CONF")
-            .field(
-                "ahb_ls_div_num",
-                &format_args!("{}", self.ahb_ls_div_num().bits()),
-            )
-            .field(
-                "ahb_hs_div_num",
-                &format_args!("{}", self.ahb_hs_div_num().bits()),
-            )
+            .field("ahb_ls_div_num", &self.ahb_ls_div_num())
+            .field("ahb_hs_div_num", &self.ahb_hs_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_FREQ_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_CPU_LS_DIV_NUM."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/apb_freq_conf.rs b/esp32c6/src/pcr/apb_freq_conf.rs
index 937861ac1f..d9c02223bc 100644
--- a/esp32c6/src/pcr/apb_freq_conf.rs
+++ b/esp32c6/src/pcr/apb_freq_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_FREQ_CONF")
-            .field(
-                "apb_decrease_div_num",
-                &format_args!("{}", self.apb_decrease_div_num().bits()),
-            )
-            .field(
-                "apb_div_num",
-                &format_args!("{}", self.apb_div_num().bits()),
-            )
+            .field("apb_decrease_div_num", &self.apb_decrease_div_num())
+            .field("apb_div_num", &self.apb_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_FREQ_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be automatically down to clk_apb_decrease only when no access is on apb-bus, and will recover to the previous frequency when a new access appears on apb-bus. Set as one within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note that enable this function will reduce performance. Users can set this field as zero to disable the auto-decrease-apb-freq function. By default, this function is disable."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/assist_conf.rs b/esp32c6/src/pcr/assist_conf.rs
index dfefe1f759..f4eaf39249 100644
--- a/esp32c6/src/pcr/assist_conf.rs
+++ b/esp32c6/src/pcr/assist_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ASSIST_CONF")
-            .field(
-                "assist_clk_en",
-                &format_args!("{}", self.assist_clk_en().bit()),
-            )
-            .field(
-                "assist_rst_en",
-                &format_args!("{}", self.assist_rst_en().bit()),
-            )
+            .field("assist_clk_en", &self.assist_clk_en())
+            .field("assist_rst_en", &self.assist_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ASSIST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable assist clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/cache_conf.rs b/esp32c6/src/pcr/cache_conf.rs
index c914a11bc1..7f7b220aa0 100644
--- a/esp32c6/src/pcr/cache_conf.rs
+++ b/esp32c6/src/pcr/cache_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_CONF")
-            .field(
-                "cache_clk_en",
-                &format_args!("{}", self.cache_clk_en().bit()),
-            )
-            .field(
-                "cache_rst_en",
-                &format_args!("{}", self.cache_rst_en().bit()),
-            )
+            .field("cache_clk_en", &self.cache_clk_en())
+            .field("cache_rst_en", &self.cache_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable cache clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/clock_gate.rs b/esp32c6/src/pcr/clock_gate.rs
index 8a69245aaa..2106d9ac93 100644
--- a/esp32c6/src/pcr/clock_gate.rs
+++ b/esp32c6/src/pcr/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit as 1 to force on clock gating."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/cpu_freq_conf.rs b/esp32c6/src/pcr/cpu_freq_conf.rs
index b6f42a4a9a..538ede2019 100644
--- a/esp32c6/src/pcr/cpu_freq_conf.rs
+++ b/esp32c6/src/pcr/cpu_freq_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_FREQ_CONF")
-            .field(
-                "cpu_ls_div_num",
-                &format_args!("{}", self.cpu_ls_div_num().bits()),
-            )
-            .field(
-                "cpu_hs_div_num",
-                &format_args!("{}", self.cpu_hs_div_num().bits()),
-            )
-            .field(
-                "cpu_hs_120m_force",
-                &format_args!("{}", self.cpu_hs_120m_force().bit()),
-            )
+            .field("cpu_ls_div_num", &self.cpu_ls_div_num())
+            .field("cpu_hs_div_num", &self.cpu_hs_div_num())
+            .field("cpu_hs_120m_force", &self.cpu_hs_120m_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_FREQ_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/cpu_waiti_conf.rs b/esp32c6/src/pcr/cpu_waiti_conf.rs
index 621ec2ad47..d637710b2c 100644
--- a/esp32c6/src/pcr/cpu_waiti_conf.rs
+++ b/esp32c6/src/pcr/cpu_waiti_conf.rs
@@ -40,31 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_WAITI_CONF")
-            .field(
-                "cpuperiod_sel",
-                &format_args!("{}", self.cpuperiod_sel().bits()),
-            )
-            .field(
-                "pll_freq_sel",
-                &format_args!("{}", self.pll_freq_sel().bit()),
-            )
-            .field(
-                "cpu_wait_mode_force_on",
-                &format_args!("{}", self.cpu_wait_mode_force_on().bit()),
-            )
-            .field(
-                "cpu_waiti_delay_num",
-                &format_args!("{}", self.cpu_waiti_delay_num().bits()),
-            )
+            .field("cpuperiod_sel", &self.cpuperiod_sel())
+            .field("pll_freq_sel", &self.pll_freq_sel())
+            .field("cpu_wait_mode_force_on", &self.cpu_wait_mode_force_on())
+            .field("cpu_waiti_delay_num", &self.cpu_waiti_delay_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_WAITI_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - Set 1 to force cpu_waiti_clk enable."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/ctrl_32k_conf.rs b/esp32c6/src/pcr/ctrl_32k_conf.rs
index daa149ab39..d4df9ba886 100644
--- a/esp32c6/src/pcr/ctrl_32k_conf.rs
+++ b/esp32c6/src/pcr/ctrl_32k_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL_32K_CONF")
-            .field(
-                "clk_32k_sel",
-                &format_args!("{}", self.clk_32k_sel().bits()),
-            )
+            .field("clk_32k_sel", &self.clk_32k_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_32K_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/ctrl_clk_out_en.rs b/esp32c6/src/pcr/ctrl_clk_out_en.rs
index acbdc29726..bcd39b3dc3 100644
--- a/esp32c6/src/pcr/ctrl_clk_out_en.rs
+++ b/esp32c6/src/pcr/ctrl_clk_out_en.rs
@@ -107,41 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL_CLK_OUT_EN")
-            .field("clk20_oen", &format_args!("{}", self.clk20_oen().bit()))
-            .field("clk22_oen", &format_args!("{}", self.clk22_oen().bit()))
-            .field("clk44_oen", &format_args!("{}", self.clk44_oen().bit()))
-            .field("clk_bb_oen", &format_args!("{}", self.clk_bb_oen().bit()))
-            .field("clk80_oen", &format_args!("{}", self.clk80_oen().bit()))
-            .field("clk160_oen", &format_args!("{}", self.clk160_oen().bit()))
-            .field(
-                "clk_320m_oen",
-                &format_args!("{}", self.clk_320m_oen().bit()),
-            )
-            .field(
-                "clk_adc_inf_oen",
-                &format_args!("{}", self.clk_adc_inf_oen().bit()),
-            )
-            .field(
-                "clk_dac_cpu_oen",
-                &format_args!("{}", self.clk_dac_cpu_oen().bit()),
-            )
-            .field(
-                "clk40x_bb_oen",
-                &format_args!("{}", self.clk40x_bb_oen().bit()),
-            )
-            .field(
-                "clk_xtal_oen",
-                &format_args!("{}", self.clk_xtal_oen().bit()),
-            )
+            .field("clk20_oen", &self.clk20_oen())
+            .field("clk22_oen", &self.clk22_oen())
+            .field("clk44_oen", &self.clk44_oen())
+            .field("clk_bb_oen", &self.clk_bb_oen())
+            .field("clk80_oen", &self.clk80_oen())
+            .field("clk160_oen", &self.clk160_oen())
+            .field("clk_320m_oen", &self.clk_320m_oen())
+            .field("clk_adc_inf_oen", &self.clk_adc_inf_oen())
+            .field("clk_dac_cpu_oen", &self.clk_dac_cpu_oen())
+            .field("clk40x_bb_oen", &self.clk40x_bb_oen())
+            .field("clk_xtal_oen", &self.clk_xtal_oen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_CLK_OUT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable 20m clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/ctrl_tick_conf.rs b/esp32c6/src/pcr/ctrl_tick_conf.rs
index 6cbc05356e..6d3f575c0e 100644
--- a/esp32c6/src/pcr/ctrl_tick_conf.rs
+++ b/esp32c6/src/pcr/ctrl_tick_conf.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL_TICK_CONF")
-            .field(
-                "xtal_tick_num",
-                &format_args!("{}", self.xtal_tick_num().bits()),
-            )
-            .field(
-                "fosc_tick_num",
-                &format_args!("{}", self.fosc_tick_num().bits()),
-            )
-            .field("tick_enable", &format_args!("{}", self.tick_enable().bit()))
-            .field(
-                "rst_tick_cnt",
-                &format_args!("{}", self.rst_tick_cnt().bit()),
-            )
+            .field("xtal_tick_num", &self.xtal_tick_num())
+            .field("fosc_tick_num", &self.fosc_tick_num())
+            .field("tick_enable", &self.tick_enable())
+            .field("rst_tick_cnt", &self.rst_tick_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_TICK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/date.rs b/esp32c6/src/pcr/date.rs
index 6d8ec41aee..6f6fe874ff 100644
--- a/esp32c6/src/pcr/date.rs
+++ b/esp32c6/src/pcr/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/pcr/ds_conf.rs b/esp32c6/src/pcr/ds_conf.rs
index e017e7d706..53b0cc04c7 100644
--- a/esp32c6/src/pcr/ds_conf.rs
+++ b/esp32c6/src/pcr/ds_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DS_CONF")
-            .field("ds_clk_en", &format_args!("{}", self.ds_clk_en().bit()))
-            .field("ds_rst_en", &format_args!("{}", self.ds_rst_en().bit()))
+            .field("ds_clk_en", &self.ds_clk_en())
+            .field("ds_rst_en", &self.ds_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable ds clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/ecc_conf.rs b/esp32c6/src/pcr/ecc_conf.rs
index 04cca1a5d7..4e84c074d6 100644
--- a/esp32c6/src/pcr/ecc_conf.rs
+++ b/esp32c6/src/pcr/ecc_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_CONF")
-            .field("ecc_clk_en", &format_args!("{}", self.ecc_clk_en().bit()))
-            .field("ecc_rst_en", &format_args!("{}", self.ecc_rst_en().bit()))
+            .field("ecc_clk_en", &self.ecc_clk_en())
+            .field("ecc_rst_en", &self.ecc_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable ecc clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/ecc_pd_ctrl.rs b/esp32c6/src/pcr/ecc_pd_ctrl.rs
index ca904cb3e1..5a8cbc49e1 100644
--- a/esp32c6/src/pcr/ecc_pd_ctrl.rs
+++ b/esp32c6/src/pcr/ecc_pd_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_PD_CTRL")
-            .field("ecc_mem_pd", &format_args!("{}", self.ecc_mem_pd().bit()))
-            .field(
-                "ecc_mem_force_pu",
-                &format_args!("{}", self.ecc_mem_force_pu().bit()),
-            )
-            .field(
-                "ecc_mem_force_pd",
-                &format_args!("{}", self.ecc_mem_force_pd().bit()),
-            )
+            .field("ecc_mem_pd", &self.ecc_mem_pd())
+            .field("ecc_mem_force_pu", &self.ecc_mem_force_pu())
+            .field("ecc_mem_force_pd", &self.ecc_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to power down ecc internal memory."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/etm_conf.rs b/esp32c6/src/pcr/etm_conf.rs
index f2415d8f59..7af4643424 100644
--- a/esp32c6/src/pcr/etm_conf.rs
+++ b/esp32c6/src/pcr/etm_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_CONF")
-            .field("etm_clk_en", &format_args!("{}", self.etm_clk_en().bit()))
-            .field("etm_rst_en", &format_args!("{}", self.etm_rst_en().bit()))
+            .field("etm_clk_en", &self.etm_clk_en())
+            .field("etm_rst_en", &self.etm_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable etm clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/fpga_debug.rs b/esp32c6/src/pcr/fpga_debug.rs
index 7b2c26deaf..f091892f66 100644
--- a/esp32c6/src/pcr/fpga_debug.rs
+++ b/esp32c6/src/pcr/fpga_debug.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FPGA_DEBUG")
-            .field("fpga_debug", &format_args!("{}", self.fpga_debug().bits()))
+            .field("fpga_debug", &self.fpga_debug())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FPGA_DEBUG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Only used in fpga debug."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/gdma_conf.rs b/esp32c6/src/pcr/gdma_conf.rs
index d56c39e7bb..cb95e81122 100644
--- a/esp32c6/src/pcr/gdma_conf.rs
+++ b/esp32c6/src/pcr/gdma_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GDMA_CONF")
-            .field("gdma_clk_en", &format_args!("{}", self.gdma_clk_en().bit()))
-            .field("gdma_rst_en", &format_args!("{}", self.gdma_rst_en().bit()))
+            .field("gdma_clk_en", &self.gdma_clk_en())
+            .field("gdma_rst_en", &self.gdma_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GDMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable gdma clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/hmac_conf.rs b/esp32c6/src/pcr/hmac_conf.rs
index c9a8012a12..7cbc00f0aa 100644
--- a/esp32c6/src/pcr/hmac_conf.rs
+++ b/esp32c6/src/pcr/hmac_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HMAC_CONF")
-            .field("hmac_clk_en", &format_args!("{}", self.hmac_clk_en().bit()))
-            .field("hmac_rst_en", &format_args!("{}", self.hmac_rst_en().bit()))
+            .field("hmac_clk_en", &self.hmac_clk_en())
+            .field("hmac_rst_en", &self.hmac_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HMAC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable hmac clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/i2c0_conf.rs b/esp32c6/src/pcr/i2c0_conf.rs
index 5102b86e28..c78037eb87 100644
--- a/esp32c6/src/pcr/i2c0_conf.rs
+++ b/esp32c6/src/pcr/i2c0_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C0_CONF")
-            .field("i2c0_clk_en", &format_args!("{}", self.i2c0_clk_en().bit()))
-            .field("i2c0_rst_en", &format_args!("{}", self.i2c0_rst_en().bit()))
+            .field("i2c0_clk_en", &self.i2c0_clk_en())
+            .field("i2c0_rst_en", &self.i2c0_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C0_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable i2c apb clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/i2c_sclk_conf.rs b/esp32c6/src/pcr/i2c_sclk_conf.rs
index 5e39de9eb1..7f38929210 100644
--- a/esp32c6/src/pcr/i2c_sclk_conf.rs
+++ b/esp32c6/src/pcr/i2c_sclk_conf.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_SCLK_CONF")
-            .field(
-                "i2c_sclk_div_a",
-                &format_args!("{}", self.i2c_sclk_div_a().bits()),
-            )
-            .field(
-                "i2c_sclk_div_b",
-                &format_args!("{}", self.i2c_sclk_div_b().bits()),
-            )
-            .field(
-                "i2c_sclk_div_num",
-                &format_args!("{}", self.i2c_sclk_div_num().bits()),
-            )
-            .field(
-                "i2c_sclk_sel",
-                &format_args!("{}", self.i2c_sclk_sel().bit()),
-            )
-            .field("i2c_sclk_en", &format_args!("{}", self.i2c_sclk_en().bit()))
+            .field("i2c_sclk_div_a", &self.i2c_sclk_div_a())
+            .field("i2c_sclk_div_b", &self.i2c_sclk_div_b())
+            .field("i2c_sclk_div_num", &self.i2c_sclk_div_num())
+            .field("i2c_sclk_sel", &self.i2c_sclk_sel())
+            .field("i2c_sclk_en", &self.i2c_sclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_SCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the i2c function clock."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/i2s_conf.rs b/esp32c6/src/pcr/i2s_conf.rs
index ca9c12e5c9..c6897941d7 100644
--- a/esp32c6/src/pcr/i2s_conf.rs
+++ b/esp32c6/src/pcr/i2s_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S_CONF")
-            .field("i2s_clk_en", &format_args!("{}", self.i2s_clk_en().bit()))
-            .field("i2s_rst_en", &format_args!("{}", self.i2s_rst_en().bit()))
+            .field("i2s_clk_en", &self.i2s_clk_en())
+            .field("i2s_rst_en", &self.i2s_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable i2s apb clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/i2s_rx_clkm_conf.rs b/esp32c6/src/pcr/i2s_rx_clkm_conf.rs
index f972604f70..50b583dc4d 100644
--- a/esp32c6/src/pcr/i2s_rx_clkm_conf.rs
+++ b/esp32c6/src/pcr/i2s_rx_clkm_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S_RX_CLKM_CONF")
-            .field(
-                "i2s_rx_clkm_div_num",
-                &format_args!("{}", self.i2s_rx_clkm_div_num().bits()),
-            )
-            .field(
-                "i2s_rx_clkm_sel",
-                &format_args!("{}", self.i2s_rx_clkm_sel().bits()),
-            )
-            .field(
-                "i2s_rx_clkm_en",
-                &format_args!("{}", self.i2s_rx_clkm_en().bit()),
-            )
-            .field(
-                "i2s_mclk_sel",
-                &format_args!("{}", self.i2s_mclk_sel().bit()),
-            )
+            .field("i2s_rx_clkm_div_num", &self.i2s_rx_clkm_div_num())
+            .field("i2s_rx_clkm_sel", &self.i2s_rx_clkm_sel())
+            .field("i2s_rx_clkm_en", &self.i2s_rx_clkm_en())
+            .field("i2s_mclk_sel", &self.i2s_mclk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S_RX_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 12:19 - Integral I2S clock divider value"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/i2s_rx_clkm_div_conf.rs b/esp32c6/src/pcr/i2s_rx_clkm_div_conf.rs
index 6e8d3a6dc5..6bbb998952 100644
--- a/esp32c6/src/pcr/i2s_rx_clkm_div_conf.rs
+++ b/esp32c6/src/pcr/i2s_rx_clkm_div_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S_RX_CLKM_DIV_CONF")
-            .field(
-                "i2s_rx_clkm_div_z",
-                &format_args!("{}", self.i2s_rx_clkm_div_z().bits()),
-            )
-            .field(
-                "i2s_rx_clkm_div_y",
-                &format_args!("{}", self.i2s_rx_clkm_div_y().bits()),
-            )
-            .field(
-                "i2s_rx_clkm_div_x",
-                &format_args!("{}", self.i2s_rx_clkm_div_x().bits()),
-            )
-            .field(
-                "i2s_rx_clkm_div_yn1",
-                &format_args!("{}", self.i2s_rx_clkm_div_yn1().bit()),
-            )
+            .field("i2s_rx_clkm_div_z", &self.i2s_rx_clkm_div_z())
+            .field("i2s_rx_clkm_div_y", &self.i2s_rx_clkm_div_y())
+            .field("i2s_rx_clkm_div_x", &self.i2s_rx_clkm_div_x())
+            .field("i2s_rx_clkm_div_yn1", &self.i2s_rx_clkm_div_yn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S_RX_CLKM_DIV_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/i2s_tx_clkm_conf.rs b/esp32c6/src/pcr/i2s_tx_clkm_conf.rs
index 83d72c6411..a172d428c6 100644
--- a/esp32c6/src/pcr/i2s_tx_clkm_conf.rs
+++ b/esp32c6/src/pcr/i2s_tx_clkm_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S_TX_CLKM_CONF")
-            .field(
-                "i2s_tx_clkm_div_num",
-                &format_args!("{}", self.i2s_tx_clkm_div_num().bits()),
-            )
-            .field(
-                "i2s_tx_clkm_sel",
-                &format_args!("{}", self.i2s_tx_clkm_sel().bits()),
-            )
-            .field(
-                "i2s_tx_clkm_en",
-                &format_args!("{}", self.i2s_tx_clkm_en().bit()),
-            )
+            .field("i2s_tx_clkm_div_num", &self.i2s_tx_clkm_div_num())
+            .field("i2s_tx_clkm_sel", &self.i2s_tx_clkm_sel())
+            .field("i2s_tx_clkm_en", &self.i2s_tx_clkm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S_TX_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 12:19 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b &lt;= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/i2s_tx_clkm_div_conf.rs b/esp32c6/src/pcr/i2s_tx_clkm_div_conf.rs
index 66bbf5a562..f8f3470186 100644
--- a/esp32c6/src/pcr/i2s_tx_clkm_div_conf.rs
+++ b/esp32c6/src/pcr/i2s_tx_clkm_div_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S_TX_CLKM_DIV_CONF")
-            .field(
-                "i2s_tx_clkm_div_z",
-                &format_args!("{}", self.i2s_tx_clkm_div_z().bits()),
-            )
-            .field(
-                "i2s_tx_clkm_div_y",
-                &format_args!("{}", self.i2s_tx_clkm_div_y().bits()),
-            )
-            .field(
-                "i2s_tx_clkm_div_x",
-                &format_args!("{}", self.i2s_tx_clkm_div_x().bits()),
-            )
-            .field(
-                "i2s_tx_clkm_div_yn1",
-                &format_args!("{}", self.i2s_tx_clkm_div_yn1().bit()),
-            )
+            .field("i2s_tx_clkm_div_z", &self.i2s_tx_clkm_div_z())
+            .field("i2s_tx_clkm_div_y", &self.i2s_tx_clkm_div_y())
+            .field("i2s_tx_clkm_div_x", &self.i2s_tx_clkm_div_x())
+            .field("i2s_tx_clkm_div_yn1", &self.i2s_tx_clkm_div_yn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S_TX_CLKM_DIV_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/intmtx_conf.rs b/esp32c6/src/pcr/intmtx_conf.rs
index ebcaa8e8fc..2edd2f5f59 100644
--- a/esp32c6/src/pcr/intmtx_conf.rs
+++ b/esp32c6/src/pcr/intmtx_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTMTX_CONF")
-            .field(
-                "intmtx_clk_en",
-                &format_args!("{}", self.intmtx_clk_en().bit()),
-            )
-            .field(
-                "intmtx_rst_en",
-                &format_args!("{}", self.intmtx_rst_en().bit()),
-            )
+            .field("intmtx_clk_en", &self.intmtx_clk_en())
+            .field("intmtx_rst_en", &self.intmtx_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTMTX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable intmtx clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/iomux_clk_conf.rs b/esp32c6/src/pcr/iomux_clk_conf.rs
index 79d75863d2..e46b27621a 100644
--- a/esp32c6/src/pcr/iomux_clk_conf.rs
+++ b/esp32c6/src/pcr/iomux_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IOMUX_CLK_CONF")
-            .field(
-                "iomux_func_clk_sel",
-                &format_args!("{}", self.iomux_func_clk_sel().bits()),
-            )
-            .field(
-                "iomux_func_clk_en",
-                &format_args!("{}", self.iomux_func_clk_en().bit()),
-            )
+            .field("iomux_func_clk_sel", &self.iomux_func_clk_sel())
+            .field("iomux_func_clk_en", &self.iomux_func_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IOMUX_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/iomux_conf.rs b/esp32c6/src/pcr/iomux_conf.rs
index bc2a9918a5..ada9aa45a9 100644
--- a/esp32c6/src/pcr/iomux_conf.rs
+++ b/esp32c6/src/pcr/iomux_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IOMUX_CONF")
-            .field(
-                "iomux_clk_en",
-                &format_args!("{}", self.iomux_clk_en().bit()),
-            )
-            .field(
-                "iomux_rst_en",
-                &format_args!("{}", self.iomux_rst_en().bit()),
-            )
+            .field("iomux_clk_en", &self.iomux_clk_en())
+            .field("iomux_rst_en", &self.iomux_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IOMUX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable iomux apb clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/ledc_conf.rs b/esp32c6/src/pcr/ledc_conf.rs
index 7267a4473c..f944c16082 100644
--- a/esp32c6/src/pcr/ledc_conf.rs
+++ b/esp32c6/src/pcr/ledc_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEDC_CONF")
-            .field("ledc_clk_en", &format_args!("{}", self.ledc_clk_en().bit()))
-            .field("ledc_rst_en", &format_args!("{}", self.ledc_rst_en().bit()))
+            .field("ledc_clk_en", &self.ledc_clk_en())
+            .field("ledc_rst_en", &self.ledc_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEDC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable ledc apb clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/ledc_sclk_conf.rs b/esp32c6/src/pcr/ledc_sclk_conf.rs
index 21af997d25..32e0c3dced 100644
--- a/esp32c6/src/pcr/ledc_sclk_conf.rs
+++ b/esp32c6/src/pcr/ledc_sclk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEDC_SCLK_CONF")
-            .field(
-                "ledc_sclk_sel",
-                &format_args!("{}", self.ledc_sclk_sel().bits()),
-            )
-            .field(
-                "ledc_sclk_en",
-                &format_args!("{}", self.ledc_sclk_en().bit()),
-            )
+            .field("ledc_sclk_sel", &self.ledc_sclk_sel())
+            .field("ledc_sclk_en", &self.ledc_sclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEDC_SCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:21 - set this field to select clock-source. 0(default): do not select anyone clock, 1: 80MHz, 2: FOSC, 3: XTAL."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/mem_monitor_conf.rs b/esp32c6/src/pcr/mem_monitor_conf.rs
index b764e75083..c5355bfe59 100644
--- a/esp32c6/src/pcr/mem_monitor_conf.rs
+++ b/esp32c6/src/pcr/mem_monitor_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_MONITOR_CONF")
-            .field(
-                "mem_monitor_clk_en",
-                &format_args!("{}", self.mem_monitor_clk_en().bit()),
-            )
-            .field(
-                "mem_monitor_rst_en",
-                &format_args!("{}", self.mem_monitor_rst_en().bit()),
-            )
+            .field("mem_monitor_clk_en", &self.mem_monitor_clk_en())
+            .field("mem_monitor_rst_en", &self.mem_monitor_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_MONITOR_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable mem_monitor clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/modem_apb_conf.rs b/esp32c6/src/pcr/modem_apb_conf.rs
index 1b0a93fb29..d3fd4671af 100644
--- a/esp32c6/src/pcr/modem_apb_conf.rs
+++ b/esp32c6/src/pcr/modem_apb_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODEM_APB_CONF")
-            .field(
-                "modem_apb_clk_en",
-                &format_args!("{}", self.modem_apb_clk_en().bit()),
-            )
-            .field(
-                "modem_rst_en",
-                &format_args!("{}", self.modem_rst_en().bit()),
-            )
+            .field("modem_apb_clk_en", &self.modem_apb_clk_en())
+            .field("modem_rst_en", &self.modem_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODEM_APB_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default)."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/mspi_clk_conf.rs b/esp32c6/src/pcr/mspi_clk_conf.rs
index 1ead8a6f32..8a1ee5e5f4 100644
--- a/esp32c6/src/pcr/mspi_clk_conf.rs
+++ b/esp32c6/src/pcr/mspi_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MSPI_CLK_CONF")
-            .field(
-                "mspi_fast_ls_div_num",
-                &format_args!("{}", self.mspi_fast_ls_div_num().bits()),
-            )
-            .field(
-                "mspi_fast_hs_div_num",
-                &format_args!("{}", self.mspi_fast_hs_div_num().bits()),
-            )
+            .field("mspi_fast_ls_div_num", &self.mspi_fast_ls_div_num())
+            .field("mspi_fast_hs_div_num", &self.mspi_fast_hs_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MSPI_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a low-speed clock-source such as XTAL/FOSC."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/mspi_conf.rs b/esp32c6/src/pcr/mspi_conf.rs
index 1c8cad521d..6abcae2330 100644
--- a/esp32c6/src/pcr/mspi_conf.rs
+++ b/esp32c6/src/pcr/mspi_conf.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MSPI_CONF")
-            .field("mspi_clk_en", &format_args!("{}", self.mspi_clk_en().bit()))
-            .field("mspi_rst_en", &format_args!("{}", self.mspi_rst_en().bit()))
-            .field(
-                "mspi_pll_clk_en",
-                &format_args!("{}", self.mspi_pll_clk_en().bit()),
-            )
+            .field("mspi_clk_en", &self.mspi_clk_en())
+            .field("mspi_rst_en", &self.mspi_rst_en())
+            .field("mspi_pll_clk_en", &self.mspi_pll_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MSPI_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable mspi clock, include mspi pll clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/parl_clk_rx_conf.rs b/esp32c6/src/pcr/parl_clk_rx_conf.rs
index 4ce25c85fd..a715a28898 100644
--- a/esp32c6/src/pcr/parl_clk_rx_conf.rs
+++ b/esp32c6/src/pcr/parl_clk_rx_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PARL_CLK_RX_CONF")
-            .field(
-                "parl_clk_rx_div_num",
-                &format_args!("{}", self.parl_clk_rx_div_num().bits()),
-            )
-            .field(
-                "parl_clk_rx_sel",
-                &format_args!("{}", self.parl_clk_rx_sel().bits()),
-            )
-            .field(
-                "parl_clk_rx_en",
-                &format_args!("{}", self.parl_clk_rx_en().bit()),
-            )
-            .field(
-                "parl_rx_rst_en",
-                &format_args!("{}", self.parl_rx_rst_en().bit()),
-            )
+            .field("parl_clk_rx_div_num", &self.parl_clk_rx_div_num())
+            .field("parl_clk_rx_sel", &self.parl_clk_rx_sel())
+            .field("parl_clk_rx_en", &self.parl_clk_rx_en())
+            .field("parl_rx_rst_en", &self.parl_rx_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PARL_CLK_RX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The integral part of the frequency divider factor of the parl rx clock."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/parl_clk_tx_conf.rs b/esp32c6/src/pcr/parl_clk_tx_conf.rs
index cb37ed41ac..0282110cc9 100644
--- a/esp32c6/src/pcr/parl_clk_tx_conf.rs
+++ b/esp32c6/src/pcr/parl_clk_tx_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PARL_CLK_TX_CONF")
-            .field(
-                "parl_clk_tx_div_num",
-                &format_args!("{}", self.parl_clk_tx_div_num().bits()),
-            )
-            .field(
-                "parl_clk_tx_sel",
-                &format_args!("{}", self.parl_clk_tx_sel().bits()),
-            )
-            .field(
-                "parl_clk_tx_en",
-                &format_args!("{}", self.parl_clk_tx_en().bit()),
-            )
-            .field(
-                "parl_tx_rst_en",
-                &format_args!("{}", self.parl_tx_rst_en().bit()),
-            )
+            .field("parl_clk_tx_div_num", &self.parl_clk_tx_div_num())
+            .field("parl_clk_tx_sel", &self.parl_clk_tx_sel())
+            .field("parl_clk_tx_en", &self.parl_clk_tx_en())
+            .field("parl_tx_rst_en", &self.parl_tx_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PARL_CLK_TX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The integral part of the frequency divider factor of the parl tx clock."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/parl_io_conf.rs b/esp32c6/src/pcr/parl_io_conf.rs
index a3a2614787..2ff23afe84 100644
--- a/esp32c6/src/pcr/parl_io_conf.rs
+++ b/esp32c6/src/pcr/parl_io_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PARL_IO_CONF")
-            .field("parl_clk_en", &format_args!("{}", self.parl_clk_en().bit()))
-            .field("parl_rst_en", &format_args!("{}", self.parl_rst_en().bit()))
+            .field("parl_clk_en", &self.parl_clk_en())
+            .field("parl_rst_en", &self.parl_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PARL_IO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable parl apb clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/pcnt_conf.rs b/esp32c6/src/pcr/pcnt_conf.rs
index b03926dbbb..da1a0d6ac1 100644
--- a/esp32c6/src/pcr/pcnt_conf.rs
+++ b/esp32c6/src/pcr/pcnt_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCNT_CONF")
-            .field("pcnt_clk_en", &format_args!("{}", self.pcnt_clk_en().bit()))
-            .field("pcnt_rst_en", &format_args!("{}", self.pcnt_rst_en().bit()))
+            .field("pcnt_clk_en", &self.pcnt_clk_en())
+            .field("pcnt_rst_en", &self.pcnt_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCNT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable pcnt clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/pll_div_clk_en.rs b/esp32c6/src/pcr/pll_div_clk_en.rs
index f6c1a95b0d..598e0da450 100644
--- a/esp32c6/src/pcr/pll_div_clk_en.rs
+++ b/esp32c6/src/pcr/pll_div_clk_en.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PLL_DIV_CLK_EN")
-            .field(
-                "pll_240m_clk_en",
-                &format_args!("{}", self.pll_240m_clk_en().bit()),
-            )
-            .field(
-                "pll_160m_clk_en",
-                &format_args!("{}", self.pll_160m_clk_en().bit()),
-            )
-            .field(
-                "pll_120m_clk_en",
-                &format_args!("{}", self.pll_120m_clk_en().bit()),
-            )
-            .field(
-                "pll_80m_clk_en",
-                &format_args!("{}", self.pll_80m_clk_en().bit()),
-            )
-            .field(
-                "pll_48m_clk_en",
-                &format_args!("{}", self.pll_48m_clk_en().bit()),
-            )
-            .field(
-                "pll_40m_clk_en",
-                &format_args!("{}", self.pll_40m_clk_en().bit()),
-            )
-            .field(
-                "pll_20m_clk_en",
-                &format_args!("{}", self.pll_20m_clk_en().bit()),
-            )
+            .field("pll_240m_clk_en", &self.pll_240m_clk_en())
+            .field("pll_160m_clk_en", &self.pll_160m_clk_en())
+            .field("pll_120m_clk_en", &self.pll_120m_clk_en())
+            .field("pll_80m_clk_en", &self.pll_80m_clk_en())
+            .field("pll_48m_clk_en", &self.pll_48m_clk_en())
+            .field("pll_40m_clk_en", &self.pll_40m_clk_en())
+            .field("pll_20m_clk_en", &self.pll_20m_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PLL_DIV_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/pvt_monitor_conf.rs b/esp32c6/src/pcr/pvt_monitor_conf.rs
index a9d7da70a3..82faf44026 100644
--- a/esp32c6/src/pcr/pvt_monitor_conf.rs
+++ b/esp32c6/src/pcr/pvt_monitor_conf.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PVT_MONITOR_CONF")
-            .field(
-                "pvt_monitor_clk_en",
-                &format_args!("{}", self.pvt_monitor_clk_en().bit()),
-            )
-            .field(
-                "pvt_monitor_rst_en",
-                &format_args!("{}", self.pvt_monitor_rst_en().bit()),
-            )
-            .field(
-                "pvt_monitor_site1_clk_en",
-                &format_args!("{}", self.pvt_monitor_site1_clk_en().bit()),
-            )
-            .field(
-                "pvt_monitor_site2_clk_en",
-                &format_args!("{}", self.pvt_monitor_site2_clk_en().bit()),
-            )
-            .field(
-                "pvt_monitor_site3_clk_en",
-                &format_args!("{}", self.pvt_monitor_site3_clk_en().bit()),
-            )
+            .field("pvt_monitor_clk_en", &self.pvt_monitor_clk_en())
+            .field("pvt_monitor_rst_en", &self.pvt_monitor_rst_en())
+            .field("pvt_monitor_site1_clk_en", &self.pvt_monitor_site1_clk_en())
+            .field("pvt_monitor_site2_clk_en", &self.pvt_monitor_site2_clk_en())
+            .field("pvt_monitor_site3_clk_en", &self.pvt_monitor_site3_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PVT_MONITOR_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable apb clock of pvt module"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/pvt_monitor_func_clk_conf.rs b/esp32c6/src/pcr/pvt_monitor_func_clk_conf.rs
index 66c402883a..26e5fad8b9 100644
--- a/esp32c6/src/pcr/pvt_monitor_func_clk_conf.rs
+++ b/esp32c6/src/pcr/pvt_monitor_func_clk_conf.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("PVT_MONITOR_FUNC_CLK_CONF")
             .field(
                 "pvt_monitor_func_clk_div_num",
-                &format_args!("{}", self.pvt_monitor_func_clk_div_num().bits()),
-            )
-            .field(
-                "pvt_monitor_func_clk_sel",
-                &format_args!("{}", self.pvt_monitor_func_clk_sel().bit()),
-            )
-            .field(
-                "pvt_monitor_func_clk_en",
-                &format_args!("{}", self.pvt_monitor_func_clk_en().bit()),
+                &self.pvt_monitor_func_clk_div_num(),
             )
+            .field("pvt_monitor_func_clk_sel", &self.pvt_monitor_func_clk_sel())
+            .field("pvt_monitor_func_clk_en", &self.pvt_monitor_func_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PVT_MONITOR_FUNC_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The integral part of the frequency divider factor of the pvt_monitor function clock."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/pwm_clk_conf.rs b/esp32c6/src/pcr/pwm_clk_conf.rs
index fe27525ecc..b064b83950 100644
--- a/esp32c6/src/pcr/pwm_clk_conf.rs
+++ b/esp32c6/src/pcr/pwm_clk_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM_CLK_CONF")
-            .field(
-                "pwm_div_num",
-                &format_args!("{}", self.pwm_div_num().bits()),
-            )
-            .field(
-                "pwm_clkm_sel",
-                &format_args!("{}", self.pwm_clkm_sel().bits()),
-            )
-            .field("pwm_clkm_en", &format_args!("{}", self.pwm_clkm_en().bit()))
+            .field("pwm_div_num", &self.pwm_div_num())
+            .field("pwm_clkm_sel", &self.pwm_clkm_sel())
+            .field("pwm_clkm_en", &self.pwm_clkm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the pwm function clock."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/pwm_conf.rs b/esp32c6/src/pcr/pwm_conf.rs
index 7d31fa48a0..5fe3be0954 100644
--- a/esp32c6/src/pcr/pwm_conf.rs
+++ b/esp32c6/src/pcr/pwm_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM_CONF")
-            .field("pwm_clk_en", &format_args!("{}", self.pwm_clk_en().bit()))
-            .field("pwm_rst_en", &format_args!("{}", self.pwm_rst_en().bit()))
+            .field("pwm_clk_en", &self.pwm_clk_en())
+            .field("pwm_rst_en", &self.pwm_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable pwm clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/regdma_conf.rs b/esp32c6/src/pcr/regdma_conf.rs
index d539eef0c4..b5d6c4568a 100644
--- a/esp32c6/src/pcr/regdma_conf.rs
+++ b/esp32c6/src/pcr/regdma_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_CONF")
-            .field(
-                "regdma_clk_en",
-                &format_args!("{}", self.regdma_clk_en().bit()),
-            )
-            .field(
-                "regdma_rst_en",
-                &format_args!("{}", self.regdma_rst_en().bit()),
-            )
+            .field("regdma_clk_en", &self.regdma_clk_en())
+            .field("regdma_rst_en", &self.regdma_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable regdma clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/reset_event_bypass.rs b/esp32c6/src/pcr/reset_event_bypass.rs
index 6c10dc4fde..8f1f6354b3 100644
--- a/esp32c6/src/pcr/reset_event_bypass.rs
+++ b/esp32c6/src/pcr/reset_event_bypass.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET_EVENT_BYPASS")
-            .field("apm", &format_args!("{}", self.apm().bit()))
-            .field(
-                "reset_event_bypass",
-                &format_args!("{}", self.reset_event_bypass().bit()),
-            )
+            .field("apm", &self.apm())
+            .field("reset_event_bypass", &self.reset_event_bypass())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET_EVENT_BYPASS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This field is used to control reset event relationship for tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset, but also some reset event."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/retention_conf.rs b/esp32c6/src/pcr/retention_conf.rs
index 9878e308d1..61f6838f6e 100644
--- a/esp32c6/src/pcr/retention_conf.rs
+++ b/esp32c6/src/pcr/retention_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_CONF")
-            .field(
-                "retention_clk_en",
-                &format_args!("{}", self.retention_clk_en().bit()),
-            )
-            .field(
-                "retention_rst_en",
-                &format_args!("{}", self.retention_rst_en().bit()),
-            )
+            .field("retention_clk_en", &self.retention_clk_en())
+            .field("retention_rst_en", &self.retention_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable retention clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/rmt_conf.rs b/esp32c6/src/pcr/rmt_conf.rs
index ae774ad949..98d3e9b2e1 100644
--- a/esp32c6/src/pcr/rmt_conf.rs
+++ b/esp32c6/src/pcr/rmt_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RMT_CONF")
-            .field("rmt_clk_en", &format_args!("{}", self.rmt_clk_en().bit()))
-            .field("rmt_rst_en", &format_args!("{}", self.rmt_rst_en().bit()))
+            .field("rmt_clk_en", &self.rmt_clk_en())
+            .field("rmt_rst_en", &self.rmt_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RMT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable rmt apb clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/rmt_sclk_conf.rs b/esp32c6/src/pcr/rmt_sclk_conf.rs
index b6ff3590d9..f125e75e89 100644
--- a/esp32c6/src/pcr/rmt_sclk_conf.rs
+++ b/esp32c6/src/pcr/rmt_sclk_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RMT_SCLK_CONF")
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bits()))
-            .field("sclk_en", &format_args!("{}", self.sclk_en().bit()))
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_en", &self.sclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RMT_SCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the rmt function clock."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/rsa_conf.rs b/esp32c6/src/pcr/rsa_conf.rs
index bee75994e9..60ae20303c 100644
--- a/esp32c6/src/pcr/rsa_conf.rs
+++ b/esp32c6/src/pcr/rsa_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_CONF")
-            .field("rsa_clk_en", &format_args!("{}", self.rsa_clk_en().bit()))
-            .field("rsa_rst_en", &format_args!("{}", self.rsa_rst_en().bit()))
+            .field("rsa_clk_en", &self.rsa_clk_en())
+            .field("rsa_rst_en", &self.rsa_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable rsa clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/rsa_pd_ctrl.rs b/esp32c6/src/pcr/rsa_pd_ctrl.rs
index 65c3c38561..208c8218fa 100644
--- a/esp32c6/src/pcr/rsa_pd_ctrl.rs
+++ b/esp32c6/src/pcr/rsa_pd_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_PD_CTRL")
-            .field("rsa_mem_pd", &format_args!("{}", self.rsa_mem_pd().bit()))
-            .field(
-                "rsa_mem_force_pu",
-                &format_args!("{}", self.rsa_mem_force_pu().bit()),
-            )
-            .field(
-                "rsa_mem_force_pd",
-                &format_args!("{}", self.rsa_mem_force_pd().bit()),
-            )
+            .field("rsa_mem_pd", &self.rsa_mem_pd())
+            .field("rsa_mem_force_pu", &self.rsa_mem_force_pu())
+            .field("rsa_mem_force_pd", &self.rsa_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to power down rsa internal memory."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/saradc_clkm_conf.rs b/esp32c6/src/pcr/saradc_clkm_conf.rs
index e666233027..25579664e8 100644
--- a/esp32c6/src/pcr/saradc_clkm_conf.rs
+++ b/esp32c6/src/pcr/saradc_clkm_conf.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SARADC_CLKM_CONF")
-            .field(
-                "saradc_clkm_div_a",
-                &format_args!("{}", self.saradc_clkm_div_a().bits()),
-            )
-            .field(
-                "saradc_clkm_div_b",
-                &format_args!("{}", self.saradc_clkm_div_b().bits()),
-            )
-            .field(
-                "saradc_clkm_div_num",
-                &format_args!("{}", self.saradc_clkm_div_num().bits()),
-            )
-            .field(
-                "saradc_clkm_sel",
-                &format_args!("{}", self.saradc_clkm_sel().bits()),
-            )
-            .field(
-                "saradc_clkm_en",
-                &format_args!("{}", self.saradc_clkm_en().bit()),
-            )
+            .field("saradc_clkm_div_a", &self.saradc_clkm_div_a())
+            .field("saradc_clkm_div_b", &self.saradc_clkm_div_b())
+            .field("saradc_clkm_div_num", &self.saradc_clkm_div_num())
+            .field("saradc_clkm_sel", &self.saradc_clkm_sel())
+            .field("saradc_clkm_en", &self.saradc_clkm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SARADC_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the saradc function clock."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/saradc_conf.rs b/esp32c6/src/pcr/saradc_conf.rs
index c98b622760..8915aa864d 100644
--- a/esp32c6/src/pcr/saradc_conf.rs
+++ b/esp32c6/src/pcr/saradc_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SARADC_CONF")
-            .field(
-                "saradc_clk_en",
-                &format_args!("{}", self.saradc_clk_en().bit()),
-            )
-            .field(
-                "saradc_rst_en",
-                &format_args!("{}", self.saradc_rst_en().bit()),
-            )
-            .field(
-                "saradc_reg_clk_en",
-                &format_args!("{}", self.saradc_reg_clk_en().bit()),
-            )
-            .field(
-                "saradc_reg_rst_en",
-                &format_args!("{}", self.saradc_reg_rst_en().bit()),
-            )
+            .field("saradc_clk_en", &self.saradc_clk_en())
+            .field("saradc_rst_en", &self.saradc_rst_en())
+            .field("saradc_reg_clk_en", &self.saradc_reg_clk_en())
+            .field("saradc_reg_rst_en", &self.saradc_reg_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SARADC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - no use"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/sdio_slave_conf.rs b/esp32c6/src/pcr/sdio_slave_conf.rs
index b64fa2b761..2242f5dcf0 100644
--- a/esp32c6/src/pcr/sdio_slave_conf.rs
+++ b/esp32c6/src/pcr/sdio_slave_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_SLAVE_CONF")
-            .field(
-                "sdio_slave_clk_en",
-                &format_args!("{}", self.sdio_slave_clk_en().bit()),
-            )
-            .field(
-                "sdio_slave_rst_en",
-                &format_args!("{}", self.sdio_slave_rst_en().bit()),
-            )
+            .field("sdio_slave_clk_en", &self.sdio_slave_clk_en())
+            .field("sdio_slave_rst_en", &self.sdio_slave_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_SLAVE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable sdio_slave clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/sha_conf.rs b/esp32c6/src/pcr/sha_conf.rs
index b08b326b5a..91046ed38c 100644
--- a/esp32c6/src/pcr/sha_conf.rs
+++ b/esp32c6/src/pcr/sha_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA_CONF")
-            .field("sha_clk_en", &format_args!("{}", self.sha_clk_en().bit()))
-            .field("sha_rst_en", &format_args!("{}", self.sha_rst_en().bit()))
+            .field("sha_clk_en", &self.sha_clk_en())
+            .field("sha_rst_en", &self.sha_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable sha clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/spi2_clkm_conf.rs b/esp32c6/src/pcr/spi2_clkm_conf.rs
index 5fac9885f8..60b461d7ad 100644
--- a/esp32c6/src/pcr/spi2_clkm_conf.rs
+++ b/esp32c6/src/pcr/spi2_clkm_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI2_CLKM_CONF")
-            .field(
-                "spi2_clkm_sel",
-                &format_args!("{}", self.spi2_clkm_sel().bits()),
-            )
-            .field(
-                "spi2_clkm_en",
-                &format_args!("{}", self.spi2_clkm_en().bit()),
-            )
+            .field("spi2_clkm_sel", &self.spi2_clkm_sel())
+            .field("spi2_clkm_en", &self.spi2_clkm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI2_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:21 - set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/spi2_conf.rs b/esp32c6/src/pcr/spi2_conf.rs
index e718836181..9be81c3147 100644
--- a/esp32c6/src/pcr/spi2_conf.rs
+++ b/esp32c6/src/pcr/spi2_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI2_CONF")
-            .field("spi2_clk_en", &format_args!("{}", self.spi2_clk_en().bit()))
-            .field("spi2_rst_en", &format_args!("{}", self.spi2_rst_en().bit()))
+            .field("spi2_clk_en", &self.spi2_clk_en())
+            .field("spi2_rst_en", &self.spi2_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI2_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable spi2 apb clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/sram_power_conf.rs b/esp32c6/src/pcr/sram_power_conf.rs
index 7c55d095c0..e87c3a4139 100644
--- a/esp32c6/src/pcr/sram_power_conf.rs
+++ b/esp32c6/src/pcr/sram_power_conf.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_POWER_CONF")
-            .field(
-                "sram_force_pu",
-                &format_args!("{}", self.sram_force_pu().bits()),
-            )
-            .field(
-                "sram_force_pd",
-                &format_args!("{}", self.sram_force_pd().bits()),
-            )
-            .field(
-                "sram_clkgate_force_on",
-                &format_args!("{}", self.sram_clkgate_force_on().bits()),
-            )
-            .field(
-                "rom_force_pu",
-                &format_args!("{}", self.rom_force_pu().bits()),
-            )
-            .field(
-                "rom_force_pd",
-                &format_args!("{}", self.rom_force_pd().bits()),
-            )
-            .field(
-                "rom_clkgate_force_on",
-                &format_args!("{}", self.rom_clkgate_force_on().bits()),
-            )
+            .field("sram_force_pu", &self.sram_force_pu())
+            .field("sram_force_pd", &self.sram_force_pd())
+            .field("sram_clkgate_force_on", &self.sram_clkgate_force_on())
+            .field("rom_force_pu", &self.rom_force_pu())
+            .field("rom_force_pd", &self.rom_force_pd())
+            .field("rom_clkgate_force_on", &self.rom_clkgate_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_POWER_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Set this bit to force power up SRAM"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/sysclk_conf.rs b/esp32c6/src/pcr/sysclk_conf.rs
index fd43a4a267..c14dbf4a81 100644
--- a/esp32c6/src/pcr/sysclk_conf.rs
+++ b/esp32c6/src/pcr/sysclk_conf.rs
@@ -38,25 +38,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSCLK_CONF")
-            .field("ls_div_num", &format_args!("{}", self.ls_div_num().bits()))
-            .field("hs_div_num", &format_args!("{}", self.hs_div_num().bits()))
-            .field(
-                "soc_clk_sel",
-                &format_args!("{}", self.soc_clk_sel().bits()),
-            )
-            .field(
-                "clk_xtal_freq",
-                &format_args!("{}", self.clk_xtal_freq().bits()),
-            )
+            .field("ls_div_num", &self.ls_div_num())
+            .field("hs_div_num", &self.hs_div_num())
+            .field("soc_clk_sel", &self.soc_clk_sel())
+            .field("clk_xtal_freq", &self.clk_xtal_freq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:17 - This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/sysclk_freq_query_0.rs b/esp32c6/src/pcr/sysclk_freq_query_0.rs
index 88febe50d9..3cf83dd7e4 100644
--- a/esp32c6/src/pcr/sysclk_freq_query_0.rs
+++ b/esp32c6/src/pcr/sysclk_freq_query_0.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSCLK_FREQ_QUERY_0")
-            .field("fosc_freq", &format_args!("{}", self.fosc_freq().bits()))
-            .field("pll_freq", &format_args!("{}", self.pll_freq().bits()))
+            .field("fosc_freq", &self.fosc_freq())
+            .field("pll_freq", &self.pll_freq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSCLK_FREQ_QUERY_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SYSCLK frequency query 0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysclk_freq_query_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SYSCLK_FREQ_QUERY_0_SPEC;
 impl crate::RegisterSpec for SYSCLK_FREQ_QUERY_0_SPEC {
diff --git a/esp32c6/src/pcr/systimer_conf.rs b/esp32c6/src/pcr/systimer_conf.rs
index 482bfaf0a2..e19a7b8a96 100644
--- a/esp32c6/src/pcr/systimer_conf.rs
+++ b/esp32c6/src/pcr/systimer_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_CONF")
-            .field(
-                "systimer_clk_en",
-                &format_args!("{}", self.systimer_clk_en().bit()),
-            )
-            .field(
-                "systimer_rst_en",
-                &format_args!("{}", self.systimer_rst_en().bit()),
-            )
+            .field("systimer_clk_en", &self.systimer_clk_en())
+            .field("systimer_rst_en", &self.systimer_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable systimer apb clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/systimer_func_clk_conf.rs b/esp32c6/src/pcr/systimer_func_clk_conf.rs
index 21e7778980..4f6ae2cfae 100644
--- a/esp32c6/src/pcr/systimer_func_clk_conf.rs
+++ b/esp32c6/src/pcr/systimer_func_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_FUNC_CLK_CONF")
-            .field(
-                "systimer_func_clk_sel",
-                &format_args!("{}", self.systimer_func_clk_sel().bit()),
-            )
-            .field(
-                "systimer_func_clk_en",
-                &format_args!("{}", self.systimer_func_clk_en().bit()),
-            )
+            .field("systimer_func_clk_sel", &self.systimer_func_clk_sel())
+            .field("systimer_func_clk_en", &self.systimer_func_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_FUNC_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - set this field to select clock-source. 0(default): XTAL, 1: FOSC."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/timeout_conf.rs b/esp32c6/src/pcr/timeout_conf.rs
index d46b025844..6e39c5c662 100644
--- a/esp32c6/src/pcr/timeout_conf.rs
+++ b/esp32c6/src/pcr/timeout_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMEOUT_CONF")
-            .field(
-                "cpu_timeout_rst_en",
-                &format_args!("{}", self.cpu_timeout_rst_en().bit()),
-            )
-            .field(
-                "hp_timeout_rst_en",
-                &format_args!("{}", self.hp_timeout_rst_en().bit()),
-            )
+            .field("cpu_timeout_rst_en", &self.cpu_timeout_rst_en())
+            .field("hp_timeout_rst_en", &self.hp_timeout_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMEOUT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set 0 to reset cpu_peri timeout module"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/timergroup0_conf.rs b/esp32c6/src/pcr/timergroup0_conf.rs
index fd886cb91f..7cc0c451a6 100644
--- a/esp32c6/src/pcr/timergroup0_conf.rs
+++ b/esp32c6/src/pcr/timergroup0_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMERGROUP0_CONF")
-            .field("tg0_clk_en", &format_args!("{}", self.tg0_clk_en().bit()))
-            .field("tg0_rst_en", &format_args!("{}", self.tg0_rst_en().bit()))
+            .field("tg0_clk_en", &self.tg0_clk_en())
+            .field("tg0_rst_en", &self.tg0_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGROUP0_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable timer_group0 apb clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/timergroup0_timer_clk_conf.rs b/esp32c6/src/pcr/timergroup0_timer_clk_conf.rs
index 17ad2c7fdc..a76f065abb 100644
--- a/esp32c6/src/pcr/timergroup0_timer_clk_conf.rs
+++ b/esp32c6/src/pcr/timergroup0_timer_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMERGROUP0_TIMER_CLK_CONF")
-            .field(
-                "tg0_timer_clk_sel",
-                &format_args!("{}", self.tg0_timer_clk_sel().bits()),
-            )
-            .field(
-                "tg0_timer_clk_en",
-                &format_args!("{}", self.tg0_timer_clk_en().bit()),
-            )
+            .field("tg0_timer_clk_sel", &self.tg0_timer_clk_sel())
+            .field("tg0_timer_clk_en", &self.tg0_timer_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGROUP0_TIMER_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:21 - set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/timergroup0_wdt_clk_conf.rs b/esp32c6/src/pcr/timergroup0_wdt_clk_conf.rs
index d3cff23a67..1e2ec0d9d7 100644
--- a/esp32c6/src/pcr/timergroup0_wdt_clk_conf.rs
+++ b/esp32c6/src/pcr/timergroup0_wdt_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMERGROUP0_WDT_CLK_CONF")
-            .field(
-                "tg0_wdt_clk_sel",
-                &format_args!("{}", self.tg0_wdt_clk_sel().bits()),
-            )
-            .field(
-                "tg0_wdt_clk_en",
-                &format_args!("{}", self.tg0_wdt_clk_en().bit()),
-            )
+            .field("tg0_wdt_clk_sel", &self.tg0_wdt_clk_sel())
+            .field("tg0_wdt_clk_en", &self.tg0_wdt_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGROUP0_WDT_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:21 - set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/timergroup1_conf.rs b/esp32c6/src/pcr/timergroup1_conf.rs
index 8f8b8f05f5..4081ea6eea 100644
--- a/esp32c6/src/pcr/timergroup1_conf.rs
+++ b/esp32c6/src/pcr/timergroup1_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMERGROUP1_CONF")
-            .field("tg1_clk_en", &format_args!("{}", self.tg1_clk_en().bit()))
-            .field("tg1_rst_en", &format_args!("{}", self.tg1_rst_en().bit()))
+            .field("tg1_clk_en", &self.tg1_clk_en())
+            .field("tg1_rst_en", &self.tg1_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGROUP1_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable timer_group1 apb clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/timergroup1_timer_clk_conf.rs b/esp32c6/src/pcr/timergroup1_timer_clk_conf.rs
index 94014734a9..f7144b76b6 100644
--- a/esp32c6/src/pcr/timergroup1_timer_clk_conf.rs
+++ b/esp32c6/src/pcr/timergroup1_timer_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMERGROUP1_TIMER_CLK_CONF")
-            .field(
-                "tg1_timer_clk_sel",
-                &format_args!("{}", self.tg1_timer_clk_sel().bits()),
-            )
-            .field(
-                "tg1_timer_clk_en",
-                &format_args!("{}", self.tg1_timer_clk_en().bit()),
-            )
+            .field("tg1_timer_clk_sel", &self.tg1_timer_clk_sel())
+            .field("tg1_timer_clk_en", &self.tg1_timer_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGROUP1_TIMER_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:21 - set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/timergroup1_wdt_clk_conf.rs b/esp32c6/src/pcr/timergroup1_wdt_clk_conf.rs
index 163f9dd9fe..6d4aa1b598 100644
--- a/esp32c6/src/pcr/timergroup1_wdt_clk_conf.rs
+++ b/esp32c6/src/pcr/timergroup1_wdt_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMERGROUP1_WDT_CLK_CONF")
-            .field(
-                "tg1_wdt_clk_sel",
-                &format_args!("{}", self.tg1_wdt_clk_sel().bits()),
-            )
-            .field(
-                "tg1_wdt_clk_en",
-                &format_args!("{}", self.tg1_wdt_clk_en().bit()),
-            )
+            .field("tg1_wdt_clk_sel", &self.tg1_wdt_clk_sel())
+            .field("tg1_wdt_clk_en", &self.tg1_wdt_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGROUP1_WDT_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:21 - set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/trace_conf.rs b/esp32c6/src/pcr/trace_conf.rs
index 3923e26075..52110676fe 100644
--- a/esp32c6/src/pcr/trace_conf.rs
+++ b/esp32c6/src/pcr/trace_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TRACE_CONF")
-            .field(
-                "trace_clk_en",
-                &format_args!("{}", self.trace_clk_en().bit()),
-            )
-            .field(
-                "trace_rst_en",
-                &format_args!("{}", self.trace_rst_en().bit()),
-            )
+            .field("trace_clk_en", &self.trace_clk_en())
+            .field("trace_rst_en", &self.trace_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TRACE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable trace clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/tsens_clk_conf.rs b/esp32c6/src/pcr/tsens_clk_conf.rs
index b96d6bdd66..b7a1417ca2 100644
--- a/esp32c6/src/pcr/tsens_clk_conf.rs
+++ b/esp32c6/src/pcr/tsens_clk_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSENS_CLK_CONF")
-            .field(
-                "tsens_clk_sel",
-                &format_args!("{}", self.tsens_clk_sel().bit()),
-            )
-            .field(
-                "tsens_clk_en",
-                &format_args!("{}", self.tsens_clk_en().bit()),
-            )
-            .field(
-                "tsens_rst_en",
-                &format_args!("{}", self.tsens_rst_en().bit()),
-            )
+            .field("tsens_clk_sel", &self.tsens_clk_sel())
+            .field("tsens_clk_en", &self.tsens_clk_en())
+            .field("tsens_rst_en", &self.tsens_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSENS_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - set this field to select clock-source. 0(default): FOSC, 1: XTAL."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/twai0_conf.rs b/esp32c6/src/pcr/twai0_conf.rs
index f97d4ea1f4..6494f70680 100644
--- a/esp32c6/src/pcr/twai0_conf.rs
+++ b/esp32c6/src/pcr/twai0_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TWAI0_CONF")
-            .field(
-                "twai0_clk_en",
-                &format_args!("{}", self.twai0_clk_en().bit()),
-            )
-            .field(
-                "twai0_rst_en",
-                &format_args!("{}", self.twai0_rst_en().bit()),
-            )
+            .field("twai0_clk_en", &self.twai0_clk_en())
+            .field("twai0_rst_en", &self.twai0_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TWAI0_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable twai0 apb clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/twai0_func_clk_conf.rs b/esp32c6/src/pcr/twai0_func_clk_conf.rs
index 54bb98ba94..c283410b4e 100644
--- a/esp32c6/src/pcr/twai0_func_clk_conf.rs
+++ b/esp32c6/src/pcr/twai0_func_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TWAI0_FUNC_CLK_CONF")
-            .field(
-                "twai0_func_clk_sel",
-                &format_args!("{}", self.twai0_func_clk_sel().bit()),
-            )
-            .field(
-                "twai0_func_clk_en",
-                &format_args!("{}", self.twai0_func_clk_en().bit()),
-            )
+            .field("twai0_func_clk_sel", &self.twai0_func_clk_sel())
+            .field("twai0_func_clk_en", &self.twai0_func_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TWAI0_FUNC_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - set this field to select clock-source. 0(default): XTAL, 1: FOSC."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/twai1_conf.rs b/esp32c6/src/pcr/twai1_conf.rs
index f2613bbf98..01810e3a9d 100644
--- a/esp32c6/src/pcr/twai1_conf.rs
+++ b/esp32c6/src/pcr/twai1_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TWAI1_CONF")
-            .field(
-                "twai1_clk_en",
-                &format_args!("{}", self.twai1_clk_en().bit()),
-            )
-            .field(
-                "twai1_rst_en",
-                &format_args!("{}", self.twai1_rst_en().bit()),
-            )
+            .field("twai1_clk_en", &self.twai1_clk_en())
+            .field("twai1_rst_en", &self.twai1_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TWAI1_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable twai1 apb clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/twai1_func_clk_conf.rs b/esp32c6/src/pcr/twai1_func_clk_conf.rs
index 3a3e727d66..909b4ce0c9 100644
--- a/esp32c6/src/pcr/twai1_func_clk_conf.rs
+++ b/esp32c6/src/pcr/twai1_func_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TWAI1_FUNC_CLK_CONF")
-            .field(
-                "twai1_func_clk_sel",
-                &format_args!("{}", self.twai1_func_clk_sel().bit()),
-            )
-            .field(
-                "twai1_func_clk_en",
-                &format_args!("{}", self.twai1_func_clk_en().bit()),
-            )
+            .field("twai1_func_clk_sel", &self.twai1_func_clk_sel())
+            .field("twai1_func_clk_en", &self.twai1_func_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TWAI1_FUNC_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - set this field to select clock-source. 0(default): XTAL, 1: FOSC."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/uart0_conf.rs b/esp32c6/src/pcr/uart0_conf.rs
index 8c58dcc49f..d01d51dc81 100644
--- a/esp32c6/src/pcr/uart0_conf.rs
+++ b/esp32c6/src/pcr/uart0_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART0_CONF")
-            .field(
-                "uart0_clk_en",
-                &format_args!("{}", self.uart0_clk_en().bit()),
-            )
-            .field(
-                "uart0_rst_en",
-                &format_args!("{}", self.uart0_rst_en().bit()),
-            )
+            .field("uart0_clk_en", &self.uart0_clk_en())
+            .field("uart0_rst_en", &self.uart0_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART0_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable uart0 apb clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/uart0_pd_ctrl.rs b/esp32c6/src/pcr/uart0_pd_ctrl.rs
index bdde57841f..6d9f4aa063 100644
--- a/esp32c6/src/pcr/uart0_pd_ctrl.rs
+++ b/esp32c6/src/pcr/uart0_pd_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART0_PD_CTRL")
-            .field(
-                "uart0_mem_force_pu",
-                &format_args!("{}", self.uart0_mem_force_pu().bit()),
-            )
-            .field(
-                "uart0_mem_force_pd",
-                &format_args!("{}", self.uart0_mem_force_pd().bit()),
-            )
+            .field("uart0_mem_force_pu", &self.uart0_mem_force_pu())
+            .field("uart0_mem_force_pd", &self.uart0_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART0_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set this bit to force power down UART0 memory."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/uart0_sclk_conf.rs b/esp32c6/src/pcr/uart0_sclk_conf.rs
index 1d4f6cb5b5..5e229850d0 100644
--- a/esp32c6/src/pcr/uart0_sclk_conf.rs
+++ b/esp32c6/src/pcr/uart0_sclk_conf.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART0_SCLK_CONF")
-            .field(
-                "uart0_sclk_div_a",
-                &format_args!("{}", self.uart0_sclk_div_a().bits()),
-            )
-            .field(
-                "uart0_sclk_div_b",
-                &format_args!("{}", self.uart0_sclk_div_b().bits()),
-            )
-            .field(
-                "uart0_sclk_div_num",
-                &format_args!("{}", self.uart0_sclk_div_num().bits()),
-            )
-            .field(
-                "uart0_sclk_sel",
-                &format_args!("{}", self.uart0_sclk_sel().bits()),
-            )
-            .field(
-                "uart0_sclk_en",
-                &format_args!("{}", self.uart0_sclk_en().bit()),
-            )
+            .field("uart0_sclk_div_a", &self.uart0_sclk_div_a())
+            .field("uart0_sclk_div_b", &self.uart0_sclk_div_b())
+            .field("uart0_sclk_div_num", &self.uart0_sclk_div_num())
+            .field("uart0_sclk_sel", &self.uart0_sclk_sel())
+            .field("uart0_sclk_en", &self.uart0_sclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART0_SCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart0 function clock."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/uart1_conf.rs b/esp32c6/src/pcr/uart1_conf.rs
index 29ad678227..5bbe1988a5 100644
--- a/esp32c6/src/pcr/uart1_conf.rs
+++ b/esp32c6/src/pcr/uart1_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART1_CONF")
-            .field(
-                "uart1_clk_en",
-                &format_args!("{}", self.uart1_clk_en().bit()),
-            )
-            .field(
-                "uart1_rst_en",
-                &format_args!("{}", self.uart1_rst_en().bit()),
-            )
+            .field("uart1_clk_en", &self.uart1_clk_en())
+            .field("uart1_rst_en", &self.uart1_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART1_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable uart1 apb clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/uart1_pd_ctrl.rs b/esp32c6/src/pcr/uart1_pd_ctrl.rs
index 8c53db3baf..fde1bc2bf7 100644
--- a/esp32c6/src/pcr/uart1_pd_ctrl.rs
+++ b/esp32c6/src/pcr/uart1_pd_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART1_PD_CTRL")
-            .field(
-                "uart1_mem_force_pu",
-                &format_args!("{}", self.uart1_mem_force_pu().bit()),
-            )
-            .field(
-                "uart1_mem_force_pd",
-                &format_args!("{}", self.uart1_mem_force_pd().bit()),
-            )
+            .field("uart1_mem_force_pu", &self.uart1_mem_force_pu())
+            .field("uart1_mem_force_pd", &self.uart1_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART1_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set this bit to force power down UART1 memory."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/uart1_sclk_conf.rs b/esp32c6/src/pcr/uart1_sclk_conf.rs
index 39dca3f2bc..bb5e30e41d 100644
--- a/esp32c6/src/pcr/uart1_sclk_conf.rs
+++ b/esp32c6/src/pcr/uart1_sclk_conf.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART1_SCLK_CONF")
-            .field(
-                "uart1_sclk_div_a",
-                &format_args!("{}", self.uart1_sclk_div_a().bits()),
-            )
-            .field(
-                "uart1_sclk_div_b",
-                &format_args!("{}", self.uart1_sclk_div_b().bits()),
-            )
-            .field(
-                "uart1_sclk_div_num",
-                &format_args!("{}", self.uart1_sclk_div_num().bits()),
-            )
-            .field(
-                "uart1_sclk_sel",
-                &format_args!("{}", self.uart1_sclk_sel().bits()),
-            )
-            .field(
-                "uart1_sclk_en",
-                &format_args!("{}", self.uart1_sclk_en().bit()),
-            )
+            .field("uart1_sclk_div_a", &self.uart1_sclk_div_a())
+            .field("uart1_sclk_div_b", &self.uart1_sclk_div_b())
+            .field("uart1_sclk_div_num", &self.uart1_sclk_div_num())
+            .field("uart1_sclk_sel", &self.uart1_sclk_sel())
+            .field("uart1_sclk_en", &self.uart1_sclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART1_SCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart1 function clock."]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/uhci_conf.rs b/esp32c6/src/pcr/uhci_conf.rs
index 9a961b8c73..b9c4d723d4 100644
--- a/esp32c6/src/pcr/uhci_conf.rs
+++ b/esp32c6/src/pcr/uhci_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UHCI_CONF")
-            .field("uhci_clk_en", &format_args!("{}", self.uhci_clk_en().bit()))
-            .field("uhci_rst_en", &format_args!("{}", self.uhci_rst_en().bit()))
+            .field("uhci_clk_en", &self.uhci_clk_en())
+            .field("uhci_rst_en", &self.uhci_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UHCI_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable uhci clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pcr/usb_device_conf.rs b/esp32c6/src/pcr/usb_device_conf.rs
index f01a53b495..f6a4480edb 100644
--- a/esp32c6/src/pcr/usb_device_conf.rs
+++ b/esp32c6/src/pcr/usb_device_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_DEVICE_CONF")
-            .field(
-                "usb_device_clk_en",
-                &format_args!("{}", self.usb_device_clk_en().bit()),
-            )
-            .field(
-                "usb_device_rst_en",
-                &format_args!("{}", self.usb_device_rst_en().bit()),
-            )
+            .field("usb_device_clk_en", &self.usb_device_clk_en())
+            .field("usb_device_rst_en", &self.usb_device_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_DEVICE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable usb_device clock"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/backup_cfg.rs b/esp32c6/src/pmu/backup_cfg.rs
index e503db6afd..c2d51cd862 100644
--- a/esp32c6/src/pmu/backup_cfg.rs
+++ b/esp32c6/src/pmu/backup_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BACKUP_CFG")
-            .field(
-                "backup_sys_clk_no_div",
-                &format_args!("{}", self.backup_sys_clk_no_div().bit()),
-            )
+            .field("backup_sys_clk_no_div", &self.backup_sys_clk_no_div())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/clk_state0.rs b/esp32c6/src/pmu/clk_state0.rs
index baf19828d4..908319a1da 100644
--- a/esp32c6/src/pmu/clk_state0.rs
+++ b/esp32c6/src/pmu/clk_state0.rs
@@ -125,83 +125,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_STATE0")
-            .field(
-                "stable_xpd_bbpll_state",
-                &format_args!("{}", self.stable_xpd_bbpll_state().bit()),
-            )
-            .field(
-                "stable_xpd_xtal_state",
-                &format_args!("{}", self.stable_xpd_xtal_state().bit()),
-            )
-            .field(
-                "sys_clk_slp_sel_state",
-                &format_args!("{}", self.sys_clk_slp_sel_state().bit()),
-            )
-            .field(
-                "sys_clk_sel_state",
-                &format_args!("{}", self.sys_clk_sel_state().bits()),
-            )
-            .field(
-                "sys_clk_no_div_state",
-                &format_args!("{}", self.sys_clk_no_div_state().bit()),
-            )
-            .field(
-                "icg_sys_clk_en_state",
-                &format_args!("{}", self.icg_sys_clk_en_state().bit()),
-            )
-            .field(
-                "icg_modem_switch_state",
-                &format_args!("{}", self.icg_modem_switch_state().bit()),
-            )
-            .field(
-                "icg_modem_code_state",
-                &format_args!("{}", self.icg_modem_code_state().bits()),
-            )
-            .field(
-                "icg_slp_sel_state",
-                &format_args!("{}", self.icg_slp_sel_state().bit()),
-            )
-            .field(
-                "icg_global_xtal_state",
-                &format_args!("{}", self.icg_global_xtal_state().bit()),
-            )
-            .field(
-                "icg_global_pll_state",
-                &format_args!("{}", self.icg_global_pll_state().bit()),
-            )
-            .field(
-                "ana_i2c_iso_en_state",
-                &format_args!("{}", self.ana_i2c_iso_en_state().bit()),
-            )
-            .field(
-                "ana_i2c_retention_state",
-                &format_args!("{}", self.ana_i2c_retention_state().bit()),
-            )
-            .field(
-                "ana_xpd_bb_i2c_state",
-                &format_args!("{}", self.ana_xpd_bb_i2c_state().bit()),
-            )
-            .field(
-                "ana_xpd_bbpll_i2c_state",
-                &format_args!("{}", self.ana_xpd_bbpll_i2c_state().bit()),
-            )
-            .field(
-                "ana_xpd_bbpll_state",
-                &format_args!("{}", self.ana_xpd_bbpll_state().bit()),
-            )
-            .field(
-                "ana_xpd_xtal_state",
-                &format_args!("{}", self.ana_xpd_xtal_state().bit()),
-            )
+            .field("stable_xpd_bbpll_state", &self.stable_xpd_bbpll_state())
+            .field("stable_xpd_xtal_state", &self.stable_xpd_xtal_state())
+            .field("sys_clk_slp_sel_state", &self.sys_clk_slp_sel_state())
+            .field("sys_clk_sel_state", &self.sys_clk_sel_state())
+            .field("sys_clk_no_div_state", &self.sys_clk_no_div_state())
+            .field("icg_sys_clk_en_state", &self.icg_sys_clk_en_state())
+            .field("icg_modem_switch_state", &self.icg_modem_switch_state())
+            .field("icg_modem_code_state", &self.icg_modem_code_state())
+            .field("icg_slp_sel_state", &self.icg_slp_sel_state())
+            .field("icg_global_xtal_state", &self.icg_global_xtal_state())
+            .field("icg_global_pll_state", &self.icg_global_pll_state())
+            .field("ana_i2c_iso_en_state", &self.ana_i2c_iso_en_state())
+            .field("ana_i2c_retention_state", &self.ana_i2c_retention_state())
+            .field("ana_xpd_bb_i2c_state", &self.ana_xpd_bb_i2c_state())
+            .field("ana_xpd_bbpll_i2c_state", &self.ana_xpd_bbpll_i2c_state())
+            .field("ana_xpd_bbpll_state", &self.ana_xpd_bbpll_state())
+            .field("ana_xpd_xtal_state", &self.ana_xpd_xtal_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_state0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_STATE0_SPEC;
 impl crate::RegisterSpec for CLK_STATE0_SPEC {
diff --git a/esp32c6/src/pmu/clk_state1.rs b/esp32c6/src/pmu/clk_state1.rs
index c28cc9c408..65ae7f5c63 100644
--- a/esp32c6/src/pmu/clk_state1.rs
+++ b/esp32c6/src/pmu/clk_state1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_STATE1")
-            .field(
-                "icg_func_en_state",
-                &format_args!("{}", self.icg_func_en_state().bits()),
-            )
+            .field("icg_func_en_state", &self.icg_func_en_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_STATE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_state1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_STATE1_SPEC;
 impl crate::RegisterSpec for CLK_STATE1_SPEC {
diff --git a/esp32c6/src/pmu/clk_state2.rs b/esp32c6/src/pmu/clk_state2.rs
index 2f9e9f476c..41d273164f 100644
--- a/esp32c6/src/pmu/clk_state2.rs
+++ b/esp32c6/src/pmu/clk_state2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_STATE2")
-            .field(
-                "icg_apb_en_state",
-                &format_args!("{}", self.icg_apb_en_state().bits()),
-            )
+            .field("icg_apb_en_state", &self.icg_apb_en_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_STATE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_state2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_STATE2_SPEC;
 impl crate::RegisterSpec for CLK_STATE2_SPEC {
diff --git a/esp32c6/src/pmu/date.rs b/esp32c6/src/pmu/date.rs
index 6c288b2b05..ad99448901 100644
--- a/esp32c6/src/pmu/date.rs
+++ b/esp32c6/src/pmu/date.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("pmu_date", &format_args!("{}", self.pmu_date().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("pmu_date", &self.pmu_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_active_backup.rs b/esp32c6/src/pmu/hp_active_backup.rs
index 62f9dc774b..121423fc4c 100644
--- a/esp32c6/src/pmu/hp_active_backup.rs
+++ b/esp32c6/src/pmu/hp_active_backup.rs
@@ -109,57 +109,48 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_BACKUP")
             .field(
                 "hp_sleep2active_backup_modem_clk_code",
-                &format_args!("{}", self.hp_sleep2active_backup_modem_clk_code().bits()),
+                &self.hp_sleep2active_backup_modem_clk_code(),
             )
             .field(
                 "hp_modem2active_backup_modem_clk_code",
-                &format_args!("{}", self.hp_modem2active_backup_modem_clk_code().bits()),
-            )
-            .field(
-                "hp_active_retention_mode",
-                &format_args!("{}", self.hp_active_retention_mode().bit()),
+                &self.hp_modem2active_backup_modem_clk_code(),
             )
+            .field("hp_active_retention_mode", &self.hp_active_retention_mode())
             .field(
                 "hp_sleep2active_retention_en",
-                &format_args!("{}", self.hp_sleep2active_retention_en().bit()),
+                &self.hp_sleep2active_retention_en(),
             )
             .field(
                 "hp_modem2active_retention_en",
-                &format_args!("{}", self.hp_modem2active_retention_en().bit()),
+                &self.hp_modem2active_retention_en(),
             )
             .field(
                 "hp_sleep2active_backup_clk_sel",
-                &format_args!("{}", self.hp_sleep2active_backup_clk_sel().bits()),
+                &self.hp_sleep2active_backup_clk_sel(),
             )
             .field(
                 "hp_modem2active_backup_clk_sel",
-                &format_args!("{}", self.hp_modem2active_backup_clk_sel().bits()),
+                &self.hp_modem2active_backup_clk_sel(),
             )
             .field(
                 "hp_sleep2active_backup_mode",
-                &format_args!("{}", self.hp_sleep2active_backup_mode().bits()),
+                &self.hp_sleep2active_backup_mode(),
             )
             .field(
                 "hp_modem2active_backup_mode",
-                &format_args!("{}", self.hp_modem2active_backup_mode().bits()),
+                &self.hp_modem2active_backup_mode(),
             )
             .field(
                 "hp_sleep2active_backup_en",
-                &format_args!("{}", self.hp_sleep2active_backup_en().bit()),
+                &self.hp_sleep2active_backup_en(),
             )
             .field(
                 "hp_modem2active_backup_en",
-                &format_args!("{}", self.hp_modem2active_backup_en().bit()),
+                &self.hp_modem2active_backup_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_BACKUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 4:5 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_active_backup_clk.rs b/esp32c6/src/pmu/hp_active_backup_clk.rs
index 263dfe5caa..86da7e6aa1 100644
--- a/esp32c6/src/pmu/hp_active_backup_clk.rs
+++ b/esp32c6/src/pmu/hp_active_backup_clk.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_BACKUP_CLK")
             .field(
                 "hp_active_backup_icg_func_en",
-                &format_args!("{}", self.hp_active_backup_icg_func_en().bits()),
+                &self.hp_active_backup_icg_func_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_BACKUP_CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_active_bias.rs b/esp32c6/src/pmu/hp_active_bias.rs
index 545213ec3e..a93f6d8343 100644
--- a/esp32c6/src/pmu/hp_active_bias.rs
+++ b/esp32c6/src/pmu/hp_active_bias.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_BIAS")
-            .field(
-                "hp_active_xpd_bias",
-                &format_args!("{}", self.hp_active_xpd_bias().bit()),
-            )
-            .field(
-                "hp_active_dbg_atten",
-                &format_args!("{}", self.hp_active_dbg_atten().bits()),
-            )
-            .field(
-                "hp_active_pd_cur",
-                &format_args!("{}", self.hp_active_pd_cur().bit()),
-            )
-            .field("sleep", &format_args!("{}", self.sleep().bit()))
+            .field("hp_active_xpd_bias", &self.hp_active_xpd_bias())
+            .field("hp_active_dbg_atten", &self.hp_active_dbg_atten())
+            .field("hp_active_pd_cur", &self.hp_active_pd_cur())
+            .field("sleep", &self.sleep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_BIAS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_active_dig_power.rs b/esp32c6/src/pmu/hp_active_dig_power.rs
index 51e065fa88..ec5b3e3a42 100644
--- a/esp32c6/src/pmu/hp_active_dig_power.rs
+++ b/esp32c6/src/pmu/hp_active_dig_power.rs
@@ -71,43 +71,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_DIG_POWER")
-            .field(
-                "hp_active_vdd_spi_pd_en",
-                &format_args!("{}", self.hp_active_vdd_spi_pd_en().bit()),
-            )
-            .field(
-                "hp_active_hp_mem_dslp",
-                &format_args!("{}", self.hp_active_hp_mem_dslp().bit()),
-            )
+            .field("hp_active_vdd_spi_pd_en", &self.hp_active_vdd_spi_pd_en())
+            .field("hp_active_hp_mem_dslp", &self.hp_active_hp_mem_dslp())
             .field(
                 "hp_active_pd_hp_mem_pd_en",
-                &format_args!("{}", self.hp_active_pd_hp_mem_pd_en().bits()),
+                &self.hp_active_pd_hp_mem_pd_en(),
             )
             .field(
                 "hp_active_pd_hp_wifi_pd_en",
-                &format_args!("{}", self.hp_active_pd_hp_wifi_pd_en().bit()),
+                &self.hp_active_pd_hp_wifi_pd_en(),
             )
             .field(
                 "hp_active_pd_hp_cpu_pd_en",
-                &format_args!("{}", self.hp_active_pd_hp_cpu_pd_en().bit()),
+                &self.hp_active_pd_hp_cpu_pd_en(),
             )
             .field(
                 "hp_active_pd_hp_aon_pd_en",
-                &format_args!("{}", self.hp_active_pd_hp_aon_pd_en().bit()),
-            )
-            .field(
-                "hp_active_pd_top_pd_en",
-                &format_args!("{}", self.hp_active_pd_top_pd_en().bit()),
+                &self.hp_active_pd_hp_aon_pd_en(),
             )
+            .field("hp_active_pd_top_pd_en", &self.hp_active_pd_top_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_DIG_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_active_hp_ck_power.rs b/esp32c6/src/pmu/hp_active_hp_ck_power.rs
index 85bec26de6..93fdfa3b86 100644
--- a/esp32c6/src/pmu/hp_active_hp_ck_power.rs
+++ b/esp32c6/src/pmu/hp_active_hp_ck_power.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_HP_CK_POWER")
-            .field(
-                "hp_active_i2c_iso_en",
-                &format_args!("{}", self.hp_active_i2c_iso_en().bit()),
-            )
-            .field(
-                "hp_active_i2c_retention",
-                &format_args!("{}", self.hp_active_i2c_retention().bit()),
-            )
-            .field(
-                "hp_active_xpd_bb_i2c",
-                &format_args!("{}", self.hp_active_xpd_bb_i2c().bit()),
-            )
-            .field(
-                "hp_active_xpd_bbpll_i2c",
-                &format_args!("{}", self.hp_active_xpd_bbpll_i2c().bit()),
-            )
-            .field(
-                "hp_active_xpd_bbpll",
-                &format_args!("{}", self.hp_active_xpd_bbpll().bit()),
-            )
+            .field("hp_active_i2c_iso_en", &self.hp_active_i2c_iso_en())
+            .field("hp_active_i2c_retention", &self.hp_active_i2c_retention())
+            .field("hp_active_xpd_bb_i2c", &self.hp_active_xpd_bb_i2c())
+            .field("hp_active_xpd_bbpll_i2c", &self.hp_active_xpd_bbpll_i2c())
+            .field("hp_active_xpd_bbpll", &self.hp_active_xpd_bbpll())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_HP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_active_hp_regulator0.rs b/esp32c6/src/pmu/hp_active_hp_regulator0.rs
index c85c10aa4e..28deda3186 100644
--- a/esp32c6/src/pmu/hp_active_hp_regulator0.rs
+++ b/esp32c6/src/pmu/hp_active_hp_regulator0.rs
@@ -89,51 +89,36 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_HP_REGULATOR0")
-            .field(
-                "lp_dbias_vol",
-                &format_args!("{}", self.lp_dbias_vol().bits()),
-            )
-            .field(
-                "hp_dbias_vol",
-                &format_args!("{}", self.hp_dbias_vol().bits()),
-            )
-            .field(
-                "dig_regulator0_dbias_sel",
-                &format_args!("{}", self.dig_regulator0_dbias_sel().bit()),
-            )
+            .field("lp_dbias_vol", &self.lp_dbias_vol())
+            .field("hp_dbias_vol", &self.hp_dbias_vol())
+            .field("dig_regulator0_dbias_sel", &self.dig_regulator0_dbias_sel())
             .field(
                 "hp_active_hp_regulator_slp_mem_xpd",
-                &format_args!("{}", self.hp_active_hp_regulator_slp_mem_xpd().bit()),
+                &self.hp_active_hp_regulator_slp_mem_xpd(),
             )
             .field(
                 "hp_active_hp_regulator_slp_logic_xpd",
-                &format_args!("{}", self.hp_active_hp_regulator_slp_logic_xpd().bit()),
+                &self.hp_active_hp_regulator_slp_logic_xpd(),
             )
             .field(
                 "hp_active_hp_regulator_xpd",
-                &format_args!("{}", self.hp_active_hp_regulator_xpd().bit()),
+                &self.hp_active_hp_regulator_xpd(),
             )
             .field(
                 "hp_active_hp_regulator_slp_mem_dbias",
-                &format_args!("{}", self.hp_active_hp_regulator_slp_mem_dbias().bits()),
+                &self.hp_active_hp_regulator_slp_mem_dbias(),
             )
             .field(
                 "hp_active_hp_regulator_slp_logic_dbias",
-                &format_args!("{}", self.hp_active_hp_regulator_slp_logic_dbias().bits()),
+                &self.hp_active_hp_regulator_slp_logic_dbias(),
             )
             .field(
                 "hp_active_hp_regulator_dbias",
-                &format_args!("{}", self.hp_active_hp_regulator_dbias().bits()),
+                &self.hp_active_hp_regulator_dbias(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_HP_REGULATOR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 14 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_active_hp_regulator1.rs b/esp32c6/src/pmu/hp_active_hp_regulator1.rs
index c5919ecbe3..81ee1a76d8 100644
--- a/esp32c6/src/pmu/hp_active_hp_regulator1.rs
+++ b/esp32c6/src/pmu/hp_active_hp_regulator1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_HP_REGULATOR1")
             .field(
                 "hp_active_hp_regulator_drv_b",
-                &format_args!("{}", self.hp_active_hp_regulator_drv_b().bits()),
+                &self.hp_active_hp_regulator_drv_b(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_HP_REGULATOR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_active_hp_sys_cntl.rs b/esp32c6/src/pmu/hp_active_hp_sys_cntl.rs
index 8cfe8b271d..e2bf7341ab 100644
--- a/esp32c6/src/pmu/hp_active_hp_sys_cntl.rs
+++ b/esp32c6/src/pmu/hp_active_hp_sys_cntl.rs
@@ -62,39 +62,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_HP_SYS_CNTL")
-            .field(
-                "hp_active_uart_wakeup_en",
-                &format_args!("{}", self.hp_active_uart_wakeup_en().bit()),
-            )
+            .field("hp_active_uart_wakeup_en", &self.hp_active_uart_wakeup_en())
             .field(
                 "hp_active_lp_pad_hold_all",
-                &format_args!("{}", self.hp_active_lp_pad_hold_all().bit()),
+                &self.hp_active_lp_pad_hold_all(),
             )
             .field(
                 "hp_active_hp_pad_hold_all",
-                &format_args!("{}", self.hp_active_hp_pad_hold_all().bit()),
+                &self.hp_active_hp_pad_hold_all(),
             )
             .field(
                 "hp_active_dig_pad_slp_sel",
-                &format_args!("{}", self.hp_active_dig_pad_slp_sel().bit()),
-            )
-            .field(
-                "hp_active_dig_pause_wdt",
-                &format_args!("{}", self.hp_active_dig_pause_wdt().bit()),
-            )
-            .field(
-                "hp_active_dig_cpu_stall",
-                &format_args!("{}", self.hp_active_dig_cpu_stall().bit()),
+                &self.hp_active_dig_pad_slp_sel(),
             )
+            .field("hp_active_dig_pause_wdt", &self.hp_active_dig_pause_wdt())
+            .field("hp_active_dig_cpu_stall", &self.hp_active_dig_cpu_stall())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_HP_SYS_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_active_icg_hp_apb.rs b/esp32c6/src/pmu/hp_active_icg_hp_apb.rs
index 6f5c572621..bce128b876 100644
--- a/esp32c6/src/pmu/hp_active_icg_hp_apb.rs
+++ b/esp32c6/src/pmu/hp_active_icg_hp_apb.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_ICG_HP_APB")
-            .field(
-                "hp_active_dig_icg_apb_en",
-                &format_args!("{}", self.hp_active_dig_icg_apb_en().bits()),
-            )
+            .field("hp_active_dig_icg_apb_en", &self.hp_active_dig_icg_apb_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_ICG_HP_APB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_active_icg_hp_func.rs b/esp32c6/src/pmu/hp_active_icg_hp_func.rs
index 66f7bfc1cc..9702957d41 100644
--- a/esp32c6/src/pmu/hp_active_icg_hp_func.rs
+++ b/esp32c6/src/pmu/hp_active_icg_hp_func.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_ICG_HP_FUNC")
             .field(
                 "hp_active_dig_icg_func_en",
-                &format_args!("{}", self.hp_active_dig_icg_func_en().bits()),
+                &self.hp_active_dig_icg_func_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_ICG_HP_FUNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_active_icg_modem.rs b/esp32c6/src/pmu/hp_active_icg_modem.rs
index 6bec45bec6..191bc539f8 100644
--- a/esp32c6/src/pmu/hp_active_icg_modem.rs
+++ b/esp32c6/src/pmu/hp_active_icg_modem.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_ICG_MODEM")
             .field(
                 "hp_active_dig_icg_modem_code",
-                &format_args!("{}", self.hp_active_dig_icg_modem_code().bits()),
+                &self.hp_active_dig_icg_modem_code(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_ICG_MODEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 30:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_active_sysclk.rs b/esp32c6/src/pmu/hp_active_sysclk.rs
index 6c8183a1a1..210c9638ed 100644
--- a/esp32c6/src/pmu/hp_active_sysclk.rs
+++ b/esp32c6/src/pmu/hp_active_sysclk.rs
@@ -55,33 +55,24 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_SYSCLK")
             .field(
                 "hp_active_dig_sys_clk_no_div",
-                &format_args!("{}", self.hp_active_dig_sys_clk_no_div().bit()),
+                &self.hp_active_dig_sys_clk_no_div(),
             )
             .field(
                 "hp_active_icg_sys_clock_en",
-                &format_args!("{}", self.hp_active_icg_sys_clock_en().bit()),
+                &self.hp_active_icg_sys_clock_en(),
             )
             .field(
                 "hp_active_sys_clk_slp_sel",
-                &format_args!("{}", self.hp_active_sys_clk_slp_sel().bit()),
-            )
-            .field(
-                "hp_active_icg_slp_sel",
-                &format_args!("{}", self.hp_active_icg_slp_sel().bit()),
+                &self.hp_active_sys_clk_slp_sel(),
             )
+            .field("hp_active_icg_slp_sel", &self.hp_active_icg_slp_sel())
             .field(
                 "hp_active_dig_sys_clk_sel",
-                &format_args!("{}", self.hp_active_dig_sys_clk_sel().bits()),
+                &self.hp_active_dig_sys_clk_sel(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_SYSCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_active_xtal.rs b/esp32c6/src/pmu/hp_active_xtal.rs
index 2bee4e63fa..9a8de33501 100644
--- a/esp32c6/src/pmu/hp_active_xtal.rs
+++ b/esp32c6/src/pmu/hp_active_xtal.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_XTAL")
-            .field(
-                "hp_active_xpd_xtal",
-                &format_args!("{}", self.hp_active_xpd_xtal().bit()),
-            )
+            .field("hp_active_xpd_xtal", &self.hp_active_xpd_xtal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_XTAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_ck_cntl.rs b/esp32c6/src/pmu/hp_ck_cntl.rs
index 324311fa38..a85fe2cf77 100644
--- a/esp32c6/src/pmu/hp_ck_cntl.rs
+++ b/esp32c6/src/pmu/hp_ck_cntl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_CK_CNTL")
-            .field(
-                "modify_icg_cntl_wait",
-                &format_args!("{}", self.modify_icg_cntl_wait().bits()),
-            )
-            .field(
-                "switch_icg_cntl_wait",
-                &format_args!("{}", self.switch_icg_cntl_wait().bits()),
-            )
+            .field("modify_icg_cntl_wait", &self.modify_icg_cntl_wait())
+            .field("switch_icg_cntl_wait", &self.switch_icg_cntl_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_CK_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_ck_poweron.rs b/esp32c6/src/pmu/hp_ck_poweron.rs
index 294f83088c..4242d0c588 100644
--- a/esp32c6/src/pmu/hp_ck_poweron.rs
+++ b/esp32c6/src/pmu/hp_ck_poweron.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_CK_POWERON")
-            .field(
-                "i2c_por_wait_target",
-                &format_args!("{}", self.i2c_por_wait_target().bits()),
-            )
+            .field("i2c_por_wait_target", &self.i2c_por_wait_target())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_CK_POWERON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_modem_backup.rs b/esp32c6/src/pmu/hp_modem_backup.rs
index 46730163af..9bc9527ee3 100644
--- a/esp32c6/src/pmu/hp_modem_backup.rs
+++ b/esp32c6/src/pmu/hp_modem_backup.rs
@@ -64,37 +64,25 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_MODEM_BACKUP")
             .field(
                 "hp_sleep2modem_backup_modem_clk_code",
-                &format_args!("{}", self.hp_sleep2modem_backup_modem_clk_code().bits()),
-            )
-            .field(
-                "hp_modem_retention_mode",
-                &format_args!("{}", self.hp_modem_retention_mode().bit()),
+                &self.hp_sleep2modem_backup_modem_clk_code(),
             )
+            .field("hp_modem_retention_mode", &self.hp_modem_retention_mode())
             .field(
                 "hp_sleep2modem_retention_en",
-                &format_args!("{}", self.hp_sleep2modem_retention_en().bit()),
+                &self.hp_sleep2modem_retention_en(),
             )
             .field(
                 "hp_sleep2modem_backup_clk_sel",
-                &format_args!("{}", self.hp_sleep2modem_backup_clk_sel().bits()),
+                &self.hp_sleep2modem_backup_clk_sel(),
             )
             .field(
                 "hp_sleep2modem_backup_mode",
-                &format_args!("{}", self.hp_sleep2modem_backup_mode().bits()),
-            )
-            .field(
-                "hp_sleep2modem_backup_en",
-                &format_args!("{}", self.hp_sleep2modem_backup_en().bit()),
+                &self.hp_sleep2modem_backup_mode(),
             )
+            .field("hp_sleep2modem_backup_en", &self.hp_sleep2modem_backup_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_BACKUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 4:5 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_modem_backup_clk.rs b/esp32c6/src/pmu/hp_modem_backup_clk.rs
index a84a7f4ffa..6aeeb8d754 100644
--- a/esp32c6/src/pmu/hp_modem_backup_clk.rs
+++ b/esp32c6/src/pmu/hp_modem_backup_clk.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_MODEM_BACKUP_CLK")
             .field(
                 "hp_modem_backup_icg_func_en",
-                &format_args!("{}", self.hp_modem_backup_icg_func_en().bits()),
+                &self.hp_modem_backup_icg_func_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_BACKUP_CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_modem_bias.rs b/esp32c6/src/pmu/hp_modem_bias.rs
index a10d4314ec..866683fe6c 100644
--- a/esp32c6/src/pmu/hp_modem_bias.rs
+++ b/esp32c6/src/pmu/hp_modem_bias.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_MODEM_BIAS")
-            .field(
-                "hp_modem_xpd_bias",
-                &format_args!("{}", self.hp_modem_xpd_bias().bit()),
-            )
-            .field(
-                "hp_modem_dbg_atten",
-                &format_args!("{}", self.hp_modem_dbg_atten().bits()),
-            )
-            .field(
-                "hp_modem_pd_cur",
-                &format_args!("{}", self.hp_modem_pd_cur().bit()),
-            )
-            .field("sleep", &format_args!("{}", self.sleep().bit()))
+            .field("hp_modem_xpd_bias", &self.hp_modem_xpd_bias())
+            .field("hp_modem_dbg_atten", &self.hp_modem_dbg_atten())
+            .field("hp_modem_pd_cur", &self.hp_modem_pd_cur())
+            .field("sleep", &self.sleep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_BIAS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_modem_dig_power.rs b/esp32c6/src/pmu/hp_modem_dig_power.rs
index b22961e778..3534688e3e 100644
--- a/esp32c6/src/pmu/hp_modem_dig_power.rs
+++ b/esp32c6/src/pmu/hp_modem_dig_power.rs
@@ -71,43 +71,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_MODEM_DIG_POWER")
-            .field(
-                "hp_modem_vdd_spi_pd_en",
-                &format_args!("{}", self.hp_modem_vdd_spi_pd_en().bit()),
-            )
-            .field(
-                "hp_modem_hp_mem_dslp",
-                &format_args!("{}", self.hp_modem_hp_mem_dslp().bit()),
-            )
-            .field(
-                "hp_modem_pd_hp_mem_pd_en",
-                &format_args!("{}", self.hp_modem_pd_hp_mem_pd_en().bits()),
-            )
+            .field("hp_modem_vdd_spi_pd_en", &self.hp_modem_vdd_spi_pd_en())
+            .field("hp_modem_hp_mem_dslp", &self.hp_modem_hp_mem_dslp())
+            .field("hp_modem_pd_hp_mem_pd_en", &self.hp_modem_pd_hp_mem_pd_en())
             .field(
                 "hp_modem_pd_hp_wifi_pd_en",
-                &format_args!("{}", self.hp_modem_pd_hp_wifi_pd_en().bit()),
-            )
-            .field(
-                "hp_modem_pd_hp_cpu_pd_en",
-                &format_args!("{}", self.hp_modem_pd_hp_cpu_pd_en().bit()),
-            )
-            .field(
-                "hp_modem_pd_hp_aon_pd_en",
-                &format_args!("{}", self.hp_modem_pd_hp_aon_pd_en().bit()),
-            )
-            .field(
-                "hp_modem_pd_top_pd_en",
-                &format_args!("{}", self.hp_modem_pd_top_pd_en().bit()),
+                &self.hp_modem_pd_hp_wifi_pd_en(),
             )
+            .field("hp_modem_pd_hp_cpu_pd_en", &self.hp_modem_pd_hp_cpu_pd_en())
+            .field("hp_modem_pd_hp_aon_pd_en", &self.hp_modem_pd_hp_aon_pd_en())
+            .field("hp_modem_pd_top_pd_en", &self.hp_modem_pd_top_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_DIG_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_modem_hp_ck_power.rs b/esp32c6/src/pmu/hp_modem_hp_ck_power.rs
index 411a015316..ebb6d6c06b 100644
--- a/esp32c6/src/pmu/hp_modem_hp_ck_power.rs
+++ b/esp32c6/src/pmu/hp_modem_hp_ck_power.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_MODEM_HP_CK_POWER")
-            .field(
-                "hp_modem_i2c_iso_en",
-                &format_args!("{}", self.hp_modem_i2c_iso_en().bit()),
-            )
-            .field(
-                "hp_modem_i2c_retention",
-                &format_args!("{}", self.hp_modem_i2c_retention().bit()),
-            )
-            .field(
-                "hp_modem_xpd_bb_i2c",
-                &format_args!("{}", self.hp_modem_xpd_bb_i2c().bit()),
-            )
-            .field(
-                "hp_modem_xpd_bbpll_i2c",
-                &format_args!("{}", self.hp_modem_xpd_bbpll_i2c().bit()),
-            )
-            .field(
-                "hp_modem_xpd_bbpll",
-                &format_args!("{}", self.hp_modem_xpd_bbpll().bit()),
-            )
+            .field("hp_modem_i2c_iso_en", &self.hp_modem_i2c_iso_en())
+            .field("hp_modem_i2c_retention", &self.hp_modem_i2c_retention())
+            .field("hp_modem_xpd_bb_i2c", &self.hp_modem_xpd_bb_i2c())
+            .field("hp_modem_xpd_bbpll_i2c", &self.hp_modem_xpd_bbpll_i2c())
+            .field("hp_modem_xpd_bbpll", &self.hp_modem_xpd_bbpll())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_HP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_modem_hp_regulator0.rs b/esp32c6/src/pmu/hp_modem_hp_regulator0.rs
index da3d9f7fb1..f928897014 100644
--- a/esp32c6/src/pmu/hp_modem_hp_regulator0.rs
+++ b/esp32c6/src/pmu/hp_modem_hp_regulator0.rs
@@ -64,37 +64,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_MODEM_HP_REGULATOR0")
             .field(
                 "hp_modem_hp_regulator_slp_mem_xpd",
-                &format_args!("{}", self.hp_modem_hp_regulator_slp_mem_xpd().bit()),
+                &self.hp_modem_hp_regulator_slp_mem_xpd(),
             )
             .field(
                 "hp_modem_hp_regulator_slp_logic_xpd",
-                &format_args!("{}", self.hp_modem_hp_regulator_slp_logic_xpd().bit()),
+                &self.hp_modem_hp_regulator_slp_logic_xpd(),
             )
             .field(
                 "hp_modem_hp_regulator_xpd",
-                &format_args!("{}", self.hp_modem_hp_regulator_xpd().bit()),
+                &self.hp_modem_hp_regulator_xpd(),
             )
             .field(
                 "hp_modem_hp_regulator_slp_mem_dbias",
-                &format_args!("{}", self.hp_modem_hp_regulator_slp_mem_dbias().bits()),
+                &self.hp_modem_hp_regulator_slp_mem_dbias(),
             )
             .field(
                 "hp_modem_hp_regulator_slp_logic_dbias",
-                &format_args!("{}", self.hp_modem_hp_regulator_slp_logic_dbias().bits()),
+                &self.hp_modem_hp_regulator_slp_logic_dbias(),
             )
             .field(
                 "hp_modem_hp_regulator_dbias",
-                &format_args!("{}", self.hp_modem_hp_regulator_dbias().bits()),
+                &self.hp_modem_hp_regulator_dbias(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_HP_REGULATOR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_modem_hp_regulator1.rs b/esp32c6/src/pmu/hp_modem_hp_regulator1.rs
index d9fd7c3fa5..a4b0092260 100644
--- a/esp32c6/src/pmu/hp_modem_hp_regulator1.rs
+++ b/esp32c6/src/pmu/hp_modem_hp_regulator1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_MODEM_HP_REGULATOR1")
             .field(
                 "hp_modem_hp_regulator_drv_b",
-                &format_args!("{}", self.hp_modem_hp_regulator_drv_b().bits()),
+                &self.hp_modem_hp_regulator_drv_b(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_HP_REGULATOR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_modem_hp_sys_cntl.rs b/esp32c6/src/pmu/hp_modem_hp_sys_cntl.rs
index b4d65d6c5d..25d1a4223a 100644
--- a/esp32c6/src/pmu/hp_modem_hp_sys_cntl.rs
+++ b/esp32c6/src/pmu/hp_modem_hp_sys_cntl.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_MODEM_HP_SYS_CNTL")
-            .field(
-                "hp_modem_uart_wakeup_en",
-                &format_args!("{}", self.hp_modem_uart_wakeup_en().bit()),
-            )
-            .field(
-                "hp_modem_lp_pad_hold_all",
-                &format_args!("{}", self.hp_modem_lp_pad_hold_all().bit()),
-            )
-            .field(
-                "hp_modem_hp_pad_hold_all",
-                &format_args!("{}", self.hp_modem_hp_pad_hold_all().bit()),
-            )
-            .field(
-                "hp_modem_dig_pad_slp_sel",
-                &format_args!("{}", self.hp_modem_dig_pad_slp_sel().bit()),
-            )
-            .field(
-                "hp_modem_dig_pause_wdt",
-                &format_args!("{}", self.hp_modem_dig_pause_wdt().bit()),
-            )
-            .field(
-                "hp_modem_dig_cpu_stall",
-                &format_args!("{}", self.hp_modem_dig_cpu_stall().bit()),
-            )
+            .field("hp_modem_uart_wakeup_en", &self.hp_modem_uart_wakeup_en())
+            .field("hp_modem_lp_pad_hold_all", &self.hp_modem_lp_pad_hold_all())
+            .field("hp_modem_hp_pad_hold_all", &self.hp_modem_hp_pad_hold_all())
+            .field("hp_modem_dig_pad_slp_sel", &self.hp_modem_dig_pad_slp_sel())
+            .field("hp_modem_dig_pause_wdt", &self.hp_modem_dig_pause_wdt())
+            .field("hp_modem_dig_cpu_stall", &self.hp_modem_dig_cpu_stall())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_HP_SYS_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_modem_icg_hp_apb.rs b/esp32c6/src/pmu/hp_modem_icg_hp_apb.rs
index 850650ded0..610fe204cf 100644
--- a/esp32c6/src/pmu/hp_modem_icg_hp_apb.rs
+++ b/esp32c6/src/pmu/hp_modem_icg_hp_apb.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_MODEM_ICG_HP_APB")
-            .field(
-                "hp_modem_dig_icg_apb_en",
-                &format_args!("{}", self.hp_modem_dig_icg_apb_en().bits()),
-            )
+            .field("hp_modem_dig_icg_apb_en", &self.hp_modem_dig_icg_apb_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_ICG_HP_APB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_modem_icg_hp_func.rs b/esp32c6/src/pmu/hp_modem_icg_hp_func.rs
index 38fafe4e08..5a6a31133d 100644
--- a/esp32c6/src/pmu/hp_modem_icg_hp_func.rs
+++ b/esp32c6/src/pmu/hp_modem_icg_hp_func.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_MODEM_ICG_HP_FUNC")
-            .field(
-                "hp_modem_dig_icg_func_en",
-                &format_args!("{}", self.hp_modem_dig_icg_func_en().bits()),
-            )
+            .field("hp_modem_dig_icg_func_en", &self.hp_modem_dig_icg_func_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_ICG_HP_FUNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_modem_icg_modem.rs b/esp32c6/src/pmu/hp_modem_icg_modem.rs
index 1ef4824b3f..95a50ae840 100644
--- a/esp32c6/src/pmu/hp_modem_icg_modem.rs
+++ b/esp32c6/src/pmu/hp_modem_icg_modem.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_MODEM_ICG_MODEM")
             .field(
                 "hp_modem_dig_icg_modem_code",
-                &format_args!("{}", self.hp_modem_dig_icg_modem_code().bits()),
+                &self.hp_modem_dig_icg_modem_code(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_ICG_MODEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 30:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_modem_sysclk.rs b/esp32c6/src/pmu/hp_modem_sysclk.rs
index a906195c4e..b7a54e1344 100644
--- a/esp32c6/src/pmu/hp_modem_sysclk.rs
+++ b/esp32c6/src/pmu/hp_modem_sysclk.rs
@@ -55,33 +55,18 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_MODEM_SYSCLK")
             .field(
                 "hp_modem_dig_sys_clk_no_div",
-                &format_args!("{}", self.hp_modem_dig_sys_clk_no_div().bit()),
+                &self.hp_modem_dig_sys_clk_no_div(),
             )
             .field(
                 "hp_modem_icg_sys_clock_en",
-                &format_args!("{}", self.hp_modem_icg_sys_clock_en().bit()),
-            )
-            .field(
-                "hp_modem_sys_clk_slp_sel",
-                &format_args!("{}", self.hp_modem_sys_clk_slp_sel().bit()),
-            )
-            .field(
-                "hp_modem_icg_slp_sel",
-                &format_args!("{}", self.hp_modem_icg_slp_sel().bit()),
-            )
-            .field(
-                "hp_modem_dig_sys_clk_sel",
-                &format_args!("{}", self.hp_modem_dig_sys_clk_sel().bits()),
+                &self.hp_modem_icg_sys_clock_en(),
             )
+            .field("hp_modem_sys_clk_slp_sel", &self.hp_modem_sys_clk_slp_sel())
+            .field("hp_modem_icg_slp_sel", &self.hp_modem_icg_slp_sel())
+            .field("hp_modem_dig_sys_clk_sel", &self.hp_modem_dig_sys_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_SYSCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_modem_xtal.rs b/esp32c6/src/pmu/hp_modem_xtal.rs
index 5d5d17c9d1..86aec785c3 100644
--- a/esp32c6/src/pmu/hp_modem_xtal.rs
+++ b/esp32c6/src/pmu/hp_modem_xtal.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_MODEM_XTAL")
-            .field(
-                "hp_modem_xpd_xtal",
-                &format_args!("{}", self.hp_modem_xpd_xtal().bit()),
-            )
+            .field("hp_modem_xpd_xtal", &self.hp_modem_xpd_xtal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_XTAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_regulator_cfg.rs b/esp32c6/src/pmu/hp_regulator_cfg.rs
index ad2910e8f2..d97579a523 100644
--- a/esp32c6/src/pmu/hp_regulator_cfg.rs
+++ b/esp32c6/src/pmu/hp_regulator_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_REGULATOR_CFG")
-            .field(
-                "dig_regulator_en_cal",
-                &format_args!("{}", self.dig_regulator_en_cal().bit()),
-            )
+            .field("dig_regulator_en_cal", &self.dig_regulator_en_cal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_REGULATOR_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_backup.rs b/esp32c6/src/pmu/hp_sleep_backup.rs
index 7f86bbd960..aa2cc24f40 100644
--- a/esp32c6/src/pmu/hp_sleep_backup.rs
+++ b/esp32c6/src/pmu/hp_sleep_backup.rs
@@ -109,57 +109,45 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_BACKUP")
             .field(
                 "hp_modem2sleep_backup_modem_clk_code",
-                &format_args!("{}", self.hp_modem2sleep_backup_modem_clk_code().bits()),
+                &self.hp_modem2sleep_backup_modem_clk_code(),
             )
             .field(
                 "hp_active2sleep_backup_modem_clk_code",
-                &format_args!("{}", self.hp_active2sleep_backup_modem_clk_code().bits()),
-            )
-            .field(
-                "hp_sleep_retention_mode",
-                &format_args!("{}", self.hp_sleep_retention_mode().bit()),
+                &self.hp_active2sleep_backup_modem_clk_code(),
             )
+            .field("hp_sleep_retention_mode", &self.hp_sleep_retention_mode())
             .field(
                 "hp_modem2sleep_retention_en",
-                &format_args!("{}", self.hp_modem2sleep_retention_en().bit()),
+                &self.hp_modem2sleep_retention_en(),
             )
             .field(
                 "hp_active2sleep_retention_en",
-                &format_args!("{}", self.hp_active2sleep_retention_en().bit()),
+                &self.hp_active2sleep_retention_en(),
             )
             .field(
                 "hp_modem2sleep_backup_clk_sel",
-                &format_args!("{}", self.hp_modem2sleep_backup_clk_sel().bits()),
+                &self.hp_modem2sleep_backup_clk_sel(),
             )
             .field(
                 "hp_active2sleep_backup_clk_sel",
-                &format_args!("{}", self.hp_active2sleep_backup_clk_sel().bits()),
+                &self.hp_active2sleep_backup_clk_sel(),
             )
             .field(
                 "hp_modem2sleep_backup_mode",
-                &format_args!("{}", self.hp_modem2sleep_backup_mode().bits()),
+                &self.hp_modem2sleep_backup_mode(),
             )
             .field(
                 "hp_active2sleep_backup_mode",
-                &format_args!("{}", self.hp_active2sleep_backup_mode().bits()),
-            )
-            .field(
-                "hp_modem2sleep_backup_en",
-                &format_args!("{}", self.hp_modem2sleep_backup_en().bit()),
+                &self.hp_active2sleep_backup_mode(),
             )
+            .field("hp_modem2sleep_backup_en", &self.hp_modem2sleep_backup_en())
             .field(
                 "hp_active2sleep_backup_en",
-                &format_args!("{}", self.hp_active2sleep_backup_en().bit()),
+                &self.hp_active2sleep_backup_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_BACKUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 6:7 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_backup_clk.rs b/esp32c6/src/pmu/hp_sleep_backup_clk.rs
index 614a958d65..e0fccffe56 100644
--- a/esp32c6/src/pmu/hp_sleep_backup_clk.rs
+++ b/esp32c6/src/pmu/hp_sleep_backup_clk.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_BACKUP_CLK")
             .field(
                 "hp_sleep_backup_icg_func_en",
-                &format_args!("{}", self.hp_sleep_backup_icg_func_en().bits()),
+                &self.hp_sleep_backup_icg_func_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_BACKUP_CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_bias.rs b/esp32c6/src/pmu/hp_sleep_bias.rs
index 83f0b774af..fbace117cb 100644
--- a/esp32c6/src/pmu/hp_sleep_bias.rs
+++ b/esp32c6/src/pmu/hp_sleep_bias.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_BIAS")
-            .field(
-                "hp_sleep_xpd_bias",
-                &format_args!("{}", self.hp_sleep_xpd_bias().bit()),
-            )
-            .field(
-                "hp_sleep_dbg_atten",
-                &format_args!("{}", self.hp_sleep_dbg_atten().bits()),
-            )
-            .field(
-                "hp_sleep_pd_cur",
-                &format_args!("{}", self.hp_sleep_pd_cur().bit()),
-            )
-            .field("sleep", &format_args!("{}", self.sleep().bit()))
+            .field("hp_sleep_xpd_bias", &self.hp_sleep_xpd_bias())
+            .field("hp_sleep_dbg_atten", &self.hp_sleep_dbg_atten())
+            .field("hp_sleep_pd_cur", &self.hp_sleep_pd_cur())
+            .field("sleep", &self.sleep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_BIAS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_dig_power.rs b/esp32c6/src/pmu/hp_sleep_dig_power.rs
index a63e50a28b..9949a71150 100644
--- a/esp32c6/src/pmu/hp_sleep_dig_power.rs
+++ b/esp32c6/src/pmu/hp_sleep_dig_power.rs
@@ -71,43 +71,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_DIG_POWER")
-            .field(
-                "hp_sleep_vdd_spi_pd_en",
-                &format_args!("{}", self.hp_sleep_vdd_spi_pd_en().bit()),
-            )
-            .field(
-                "hp_sleep_hp_mem_dslp",
-                &format_args!("{}", self.hp_sleep_hp_mem_dslp().bit()),
-            )
-            .field(
-                "hp_sleep_pd_hp_mem_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_hp_mem_pd_en().bits()),
-            )
+            .field("hp_sleep_vdd_spi_pd_en", &self.hp_sleep_vdd_spi_pd_en())
+            .field("hp_sleep_hp_mem_dslp", &self.hp_sleep_hp_mem_dslp())
+            .field("hp_sleep_pd_hp_mem_pd_en", &self.hp_sleep_pd_hp_mem_pd_en())
             .field(
                 "hp_sleep_pd_hp_wifi_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_hp_wifi_pd_en().bit()),
-            )
-            .field(
-                "hp_sleep_pd_hp_cpu_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_hp_cpu_pd_en().bit()),
-            )
-            .field(
-                "hp_sleep_pd_hp_aon_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_hp_aon_pd_en().bit()),
-            )
-            .field(
-                "hp_sleep_pd_top_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_top_pd_en().bit()),
+                &self.hp_sleep_pd_hp_wifi_pd_en(),
             )
+            .field("hp_sleep_pd_hp_cpu_pd_en", &self.hp_sleep_pd_hp_cpu_pd_en())
+            .field("hp_sleep_pd_hp_aon_pd_en", &self.hp_sleep_pd_hp_aon_pd_en())
+            .field("hp_sleep_pd_top_pd_en", &self.hp_sleep_pd_top_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_DIG_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_hp_ck_power.rs b/esp32c6/src/pmu/hp_sleep_hp_ck_power.rs
index cc7e3b4592..bdf67ed4c6 100644
--- a/esp32c6/src/pmu/hp_sleep_hp_ck_power.rs
+++ b/esp32c6/src/pmu/hp_sleep_hp_ck_power.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_HP_CK_POWER")
-            .field(
-                "hp_sleep_i2c_iso_en",
-                &format_args!("{}", self.hp_sleep_i2c_iso_en().bit()),
-            )
-            .field(
-                "hp_sleep_i2c_retention",
-                &format_args!("{}", self.hp_sleep_i2c_retention().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_bb_i2c",
-                &format_args!("{}", self.hp_sleep_xpd_bb_i2c().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_bbpll_i2c",
-                &format_args!("{}", self.hp_sleep_xpd_bbpll_i2c().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_bbpll",
-                &format_args!("{}", self.hp_sleep_xpd_bbpll().bit()),
-            )
+            .field("hp_sleep_i2c_iso_en", &self.hp_sleep_i2c_iso_en())
+            .field("hp_sleep_i2c_retention", &self.hp_sleep_i2c_retention())
+            .field("hp_sleep_xpd_bb_i2c", &self.hp_sleep_xpd_bb_i2c())
+            .field("hp_sleep_xpd_bbpll_i2c", &self.hp_sleep_xpd_bbpll_i2c())
+            .field("hp_sleep_xpd_bbpll", &self.hp_sleep_xpd_bbpll())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_HP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_hp_regulator0.rs b/esp32c6/src/pmu/hp_sleep_hp_regulator0.rs
index 84b261f38a..0d75042e74 100644
--- a/esp32c6/src/pmu/hp_sleep_hp_regulator0.rs
+++ b/esp32c6/src/pmu/hp_sleep_hp_regulator0.rs
@@ -64,37 +64,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_HP_REGULATOR0")
             .field(
                 "hp_sleep_hp_regulator_slp_mem_xpd",
-                &format_args!("{}", self.hp_sleep_hp_regulator_slp_mem_xpd().bit()),
+                &self.hp_sleep_hp_regulator_slp_mem_xpd(),
             )
             .field(
                 "hp_sleep_hp_regulator_slp_logic_xpd",
-                &format_args!("{}", self.hp_sleep_hp_regulator_slp_logic_xpd().bit()),
+                &self.hp_sleep_hp_regulator_slp_logic_xpd(),
             )
             .field(
                 "hp_sleep_hp_regulator_xpd",
-                &format_args!("{}", self.hp_sleep_hp_regulator_xpd().bit()),
+                &self.hp_sleep_hp_regulator_xpd(),
             )
             .field(
                 "hp_sleep_hp_regulator_slp_mem_dbias",
-                &format_args!("{}", self.hp_sleep_hp_regulator_slp_mem_dbias().bits()),
+                &self.hp_sleep_hp_regulator_slp_mem_dbias(),
             )
             .field(
                 "hp_sleep_hp_regulator_slp_logic_dbias",
-                &format_args!("{}", self.hp_sleep_hp_regulator_slp_logic_dbias().bits()),
+                &self.hp_sleep_hp_regulator_slp_logic_dbias(),
             )
             .field(
                 "hp_sleep_hp_regulator_dbias",
-                &format_args!("{}", self.hp_sleep_hp_regulator_dbias().bits()),
+                &self.hp_sleep_hp_regulator_dbias(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_HP_REGULATOR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_hp_regulator1.rs b/esp32c6/src/pmu/hp_sleep_hp_regulator1.rs
index f352c326a5..2cd4fc5a1f 100644
--- a/esp32c6/src/pmu/hp_sleep_hp_regulator1.rs
+++ b/esp32c6/src/pmu/hp_sleep_hp_regulator1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_HP_REGULATOR1")
             .field(
                 "hp_sleep_hp_regulator_drv_b",
-                &format_args!("{}", self.hp_sleep_hp_regulator_drv_b().bits()),
+                &self.hp_sleep_hp_regulator_drv_b(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_HP_REGULATOR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_hp_sys_cntl.rs b/esp32c6/src/pmu/hp_sleep_hp_sys_cntl.rs
index 9656f07128..af773a1876 100644
--- a/esp32c6/src/pmu/hp_sleep_hp_sys_cntl.rs
+++ b/esp32c6/src/pmu/hp_sleep_hp_sys_cntl.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_HP_SYS_CNTL")
-            .field(
-                "hp_sleep_uart_wakeup_en",
-                &format_args!("{}", self.hp_sleep_uart_wakeup_en().bit()),
-            )
-            .field(
-                "hp_sleep_lp_pad_hold_all",
-                &format_args!("{}", self.hp_sleep_lp_pad_hold_all().bit()),
-            )
-            .field(
-                "hp_sleep_hp_pad_hold_all",
-                &format_args!("{}", self.hp_sleep_hp_pad_hold_all().bit()),
-            )
-            .field(
-                "hp_sleep_dig_pad_slp_sel",
-                &format_args!("{}", self.hp_sleep_dig_pad_slp_sel().bit()),
-            )
-            .field(
-                "hp_sleep_dig_pause_wdt",
-                &format_args!("{}", self.hp_sleep_dig_pause_wdt().bit()),
-            )
-            .field(
-                "hp_sleep_dig_cpu_stall",
-                &format_args!("{}", self.hp_sleep_dig_cpu_stall().bit()),
-            )
+            .field("hp_sleep_uart_wakeup_en", &self.hp_sleep_uart_wakeup_en())
+            .field("hp_sleep_lp_pad_hold_all", &self.hp_sleep_lp_pad_hold_all())
+            .field("hp_sleep_hp_pad_hold_all", &self.hp_sleep_hp_pad_hold_all())
+            .field("hp_sleep_dig_pad_slp_sel", &self.hp_sleep_dig_pad_slp_sel())
+            .field("hp_sleep_dig_pause_wdt", &self.hp_sleep_dig_pause_wdt())
+            .field("hp_sleep_dig_cpu_stall", &self.hp_sleep_dig_cpu_stall())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_HP_SYS_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_icg_hp_apb.rs b/esp32c6/src/pmu/hp_sleep_icg_hp_apb.rs
index f88b25a3ef..528420839b 100644
--- a/esp32c6/src/pmu/hp_sleep_icg_hp_apb.rs
+++ b/esp32c6/src/pmu/hp_sleep_icg_hp_apb.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_ICG_HP_APB")
-            .field(
-                "hp_sleep_dig_icg_apb_en",
-                &format_args!("{}", self.hp_sleep_dig_icg_apb_en().bits()),
-            )
+            .field("hp_sleep_dig_icg_apb_en", &self.hp_sleep_dig_icg_apb_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_ICG_HP_APB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_icg_hp_func.rs b/esp32c6/src/pmu/hp_sleep_icg_hp_func.rs
index 7c25582392..a78d413e13 100644
--- a/esp32c6/src/pmu/hp_sleep_icg_hp_func.rs
+++ b/esp32c6/src/pmu/hp_sleep_icg_hp_func.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_ICG_HP_FUNC")
-            .field(
-                "hp_sleep_dig_icg_func_en",
-                &format_args!("{}", self.hp_sleep_dig_icg_func_en().bits()),
-            )
+            .field("hp_sleep_dig_icg_func_en", &self.hp_sleep_dig_icg_func_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_ICG_HP_FUNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_icg_modem.rs b/esp32c6/src/pmu/hp_sleep_icg_modem.rs
index 28d2bd644e..43fc5f1da0 100644
--- a/esp32c6/src/pmu/hp_sleep_icg_modem.rs
+++ b/esp32c6/src/pmu/hp_sleep_icg_modem.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_ICG_MODEM")
             .field(
                 "hp_sleep_dig_icg_modem_code",
-                &format_args!("{}", self.hp_sleep_dig_icg_modem_code().bits()),
+                &self.hp_sleep_dig_icg_modem_code(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_ICG_MODEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 30:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_lp_ck_power.rs b/esp32c6/src/pmu/hp_sleep_lp_ck_power.rs
index db994520c0..9a5c6045b4 100644
--- a/esp32c6/src/pmu/hp_sleep_lp_ck_power.rs
+++ b/esp32c6/src/pmu/hp_sleep_lp_ck_power.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_LP_CK_POWER")
-            .field(
-                "hp_sleep_xpd_xtal32k",
-                &format_args!("{}", self.hp_sleep_xpd_xtal32k().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_rc32k",
-                &format_args!("{}", self.hp_sleep_xpd_rc32k().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_fosc_clk",
-                &format_args!("{}", self.hp_sleep_xpd_fosc_clk().bit()),
-            )
-            .field(
-                "hp_sleep_pd_osc_clk",
-                &format_args!("{}", self.hp_sleep_pd_osc_clk().bit()),
-            )
+            .field("hp_sleep_xpd_xtal32k", &self.hp_sleep_xpd_xtal32k())
+            .field("hp_sleep_xpd_rc32k", &self.hp_sleep_xpd_rc32k())
+            .field("hp_sleep_xpd_fosc_clk", &self.hp_sleep_xpd_fosc_clk())
+            .field("hp_sleep_pd_osc_clk", &self.hp_sleep_pd_osc_clk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_LP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_lp_dig_power.rs b/esp32c6/src/pmu/hp_sleep_lp_dig_power.rs
index 7130f60905..3e83ca5788 100644
--- a/esp32c6/src/pmu/hp_sleep_lp_dig_power.rs
+++ b/esp32c6/src/pmu/hp_sleep_lp_dig_power.rs
@@ -26,23 +26,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_LP_DIG_POWER")
-            .field(
-                "hp_sleep_lp_mem_dslp",
-                &format_args!("{}", self.hp_sleep_lp_mem_dslp().bit()),
-            )
+            .field("hp_sleep_lp_mem_dslp", &self.hp_sleep_lp_mem_dslp())
             .field(
                 "hp_sleep_pd_lp_peri_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_lp_peri_pd_en().bit()),
+                &self.hp_sleep_pd_lp_peri_pd_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_LP_DIG_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_lp_regulator0.rs b/esp32c6/src/pmu/hp_sleep_lp_regulator0.rs
index e4546dcb5d..f924dd5e5c 100644
--- a/esp32c6/src/pmu/hp_sleep_lp_regulator0.rs
+++ b/esp32c6/src/pmu/hp_sleep_lp_regulator0.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_LP_REGULATOR0")
             .field(
                 "hp_sleep_lp_regulator_slp_xpd",
-                &format_args!("{}", self.hp_sleep_lp_regulator_slp_xpd().bit()),
+                &self.hp_sleep_lp_regulator_slp_xpd(),
             )
             .field(
                 "hp_sleep_lp_regulator_xpd",
-                &format_args!("{}", self.hp_sleep_lp_regulator_xpd().bit()),
+                &self.hp_sleep_lp_regulator_xpd(),
             )
             .field(
                 "hp_sleep_lp_regulator_slp_dbias",
-                &format_args!("{}", self.hp_sleep_lp_regulator_slp_dbias().bits()),
+                &self.hp_sleep_lp_regulator_slp_dbias(),
             )
             .field(
                 "hp_sleep_lp_regulator_dbias",
-                &format_args!("{}", self.hp_sleep_lp_regulator_dbias().bits()),
+                &self.hp_sleep_lp_regulator_dbias(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_LP_REGULATOR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_lp_regulator1.rs b/esp32c6/src/pmu/hp_sleep_lp_regulator1.rs
index 39c41cbe94..2ed52079d4 100644
--- a/esp32c6/src/pmu/hp_sleep_lp_regulator1.rs
+++ b/esp32c6/src/pmu/hp_sleep_lp_regulator1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_LP_REGULATOR1")
             .field(
                 "hp_sleep_lp_regulator_drv_b",
-                &format_args!("{}", self.hp_sleep_lp_regulator_drv_b().bits()),
+                &self.hp_sleep_lp_regulator_drv_b(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_LP_REGULATOR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 28:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_sysclk.rs b/esp32c6/src/pmu/hp_sleep_sysclk.rs
index 747f40e916..774ea4245c 100644
--- a/esp32c6/src/pmu/hp_sleep_sysclk.rs
+++ b/esp32c6/src/pmu/hp_sleep_sysclk.rs
@@ -55,33 +55,18 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_SYSCLK")
             .field(
                 "hp_sleep_dig_sys_clk_no_div",
-                &format_args!("{}", self.hp_sleep_dig_sys_clk_no_div().bit()),
+                &self.hp_sleep_dig_sys_clk_no_div(),
             )
             .field(
                 "hp_sleep_icg_sys_clock_en",
-                &format_args!("{}", self.hp_sleep_icg_sys_clock_en().bit()),
-            )
-            .field(
-                "hp_sleep_sys_clk_slp_sel",
-                &format_args!("{}", self.hp_sleep_sys_clk_slp_sel().bit()),
-            )
-            .field(
-                "hp_sleep_icg_slp_sel",
-                &format_args!("{}", self.hp_sleep_icg_slp_sel().bit()),
-            )
-            .field(
-                "hp_sleep_dig_sys_clk_sel",
-                &format_args!("{}", self.hp_sleep_dig_sys_clk_sel().bits()),
+                &self.hp_sleep_icg_sys_clock_en(),
             )
+            .field("hp_sleep_sys_clk_slp_sel", &self.hp_sleep_sys_clk_slp_sel())
+            .field("hp_sleep_icg_slp_sel", &self.hp_sleep_icg_slp_sel())
+            .field("hp_sleep_dig_sys_clk_sel", &self.hp_sleep_dig_sys_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_SYSCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/hp_sleep_xtal.rs b/esp32c6/src/pmu/hp_sleep_xtal.rs
index 6a54e1ef0a..f1e6e47a01 100644
--- a/esp32c6/src/pmu/hp_sleep_xtal.rs
+++ b/esp32c6/src/pmu/hp_sleep_xtal.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_XTAL")
-            .field(
-                "hp_sleep_xpd_xtal",
-                &format_args!("{}", self.hp_sleep_xpd_xtal().bit()),
-            )
+            .field("hp_sleep_xpd_xtal", &self.hp_sleep_xpd_xtal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_XTAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/imm_hp_ck_power.rs b/esp32c6/src/pmu/imm_hp_ck_power.rs
index 864dbe022d..89700a58a4 100644
--- a/esp32c6/src/pmu/imm_hp_ck_power.rs
+++ b/esp32c6/src/pmu/imm_hp_ck_power.rs
@@ -36,12 +36,6 @@ impl core::fmt::Debug for R {
         f.debug_struct("IMM_HP_CK_POWER").finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMM_HP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/int_ena.rs b/esp32c6/src/pmu/int_ena.rs
index 6b7e43e73c..b9ff7e126e 100644
--- a/esp32c6/src/pmu/int_ena.rs
+++ b/esp32c6/src/pmu/int_ena.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("lp_cpu_exc", &format_args!("{}", self.lp_cpu_exc().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("sw", &format_args!("{}", self.sw().bit()))
-            .field(
-                "soc_sleep_reject",
-                &format_args!("{}", self.soc_sleep_reject().bit()),
-            )
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("lp_cpu_exc", &self.lp_cpu_exc())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("sw", &self.sw())
+            .field("soc_sleep_reject", &self.soc_sleep_reject())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/int_raw.rs b/esp32c6/src/pmu/int_raw.rs
index e18ddad1b9..2889e9c973 100644
--- a/esp32c6/src/pmu/int_raw.rs
+++ b/esp32c6/src/pmu/int_raw.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("lp_cpu_exc", &format_args!("{}", self.lp_cpu_exc().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("sw", &format_args!("{}", self.sw().bit()))
-            .field(
-                "soc_sleep_reject",
-                &format_args!("{}", self.soc_sleep_reject().bit()),
-            )
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("lp_cpu_exc", &self.lp_cpu_exc())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("sw", &self.sw())
+            .field("soc_sleep_reject", &self.soc_sleep_reject())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/int_st.rs b/esp32c6/src/pmu/int_st.rs
index e041d3bf92..d3927f8a2d 100644
--- a/esp32c6/src/pmu/int_st.rs
+++ b/esp32c6/src/pmu/int_st.rs
@@ -41,23 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("lp_cpu_exc", &format_args!("{}", self.lp_cpu_exc().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("sw", &format_args!("{}", self.sw().bit()))
-            .field(
-                "soc_sleep_reject",
-                &format_args!("{}", self.soc_sleep_reject().bit()),
-            )
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("lp_cpu_exc", &self.lp_cpu_exc())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("sw", &self.sw())
+            .field("soc_sleep_reject", &self.soc_sleep_reject())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/pmu/lp_cpu_pwr0.rs b/esp32c6/src/pmu/lp_cpu_pwr0.rs
index 7147a7513f..0d670be9e5 100644
--- a/esp32c6/src/pmu/lp_cpu_pwr0.rs
+++ b/esp32c6/src/pmu/lp_cpu_pwr0.rs
@@ -85,51 +85,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CPU_PWR0")
-            .field(
-                "lp_cpu_waiti_rdy",
-                &format_args!("{}", self.lp_cpu_waiti_rdy().bit()),
-            )
-            .field(
-                "lp_cpu_stall_rdy",
-                &format_args!("{}", self.lp_cpu_stall_rdy().bit()),
-            )
-            .field(
-                "lp_cpu_force_stall",
-                &format_args!("{}", self.lp_cpu_force_stall().bit()),
-            )
-            .field(
-                "lp_cpu_slp_waiti_flag_en",
-                &format_args!("{}", self.lp_cpu_slp_waiti_flag_en().bit()),
-            )
-            .field(
-                "lp_cpu_slp_stall_flag_en",
-                &format_args!("{}", self.lp_cpu_slp_stall_flag_en().bit()),
-            )
-            .field(
-                "lp_cpu_slp_stall_wait",
-                &format_args!("{}", self.lp_cpu_slp_stall_wait().bits()),
-            )
-            .field(
-                "lp_cpu_slp_stall_en",
-                &format_args!("{}", self.lp_cpu_slp_stall_en().bit()),
-            )
-            .field(
-                "lp_cpu_slp_reset_en",
-                &format_args!("{}", self.lp_cpu_slp_reset_en().bit()),
-            )
+            .field("lp_cpu_waiti_rdy", &self.lp_cpu_waiti_rdy())
+            .field("lp_cpu_stall_rdy", &self.lp_cpu_stall_rdy())
+            .field("lp_cpu_force_stall", &self.lp_cpu_force_stall())
+            .field("lp_cpu_slp_waiti_flag_en", &self.lp_cpu_slp_waiti_flag_en())
+            .field("lp_cpu_slp_stall_flag_en", &self.lp_cpu_slp_stall_flag_en())
+            .field("lp_cpu_slp_stall_wait", &self.lp_cpu_slp_stall_wait())
+            .field("lp_cpu_slp_stall_en", &self.lp_cpu_slp_stall_en())
+            .field("lp_cpu_slp_reset_en", &self.lp_cpu_slp_reset_en())
             .field(
                 "lp_cpu_slp_bypass_intr_en",
-                &format_args!("{}", self.lp_cpu_slp_bypass_intr_en().bit()),
+                &self.lp_cpu_slp_bypass_intr_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CPU_PWR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/lp_cpu_pwr1.rs b/esp32c6/src/pmu/lp_cpu_pwr1.rs
index 9c51108972..0a98bd82dc 100644
--- a/esp32c6/src/pmu/lp_cpu_pwr1.rs
+++ b/esp32c6/src/pmu/lp_cpu_pwr1.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CPU_PWR1")
-            .field(
-                "lp_cpu_wakeup_en",
-                &format_args!("{}", self.lp_cpu_wakeup_en().bits()),
-            )
+            .field("lp_cpu_wakeup_en", &self.lp_cpu_wakeup_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CPU_PWR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/lp_int_ena.rs b/esp32c6/src/pmu/lp_int_ena.rs
index 5b122e6ab5..18a334fbb5 100644
--- a/esp32c6/src/pmu/lp_int_ena.rs
+++ b/esp32c6/src/pmu/lp_int_ena.rs
@@ -116,63 +116,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ENA")
-            .field(
-                "lp_cpu_wakeup",
-                &format_args!("{}", self.lp_cpu_wakeup().bit()),
-            )
-            .field(
-                "modem_switch_active_end",
-                &format_args!("{}", self.modem_switch_active_end().bit()),
-            )
-            .field(
-                "sleep_switch_active_end",
-                &format_args!("{}", self.sleep_switch_active_end().bit()),
-            )
-            .field(
-                "sleep_switch_modem_end",
-                &format_args!("{}", self.sleep_switch_modem_end().bit()),
-            )
-            .field(
-                "modem_switch_sleep_end",
-                &format_args!("{}", self.modem_switch_sleep_end().bit()),
-            )
-            .field(
-                "active_switch_sleep_end",
-                &format_args!("{}", self.active_switch_sleep_end().bit()),
-            )
+            .field("lp_cpu_wakeup", &self.lp_cpu_wakeup())
+            .field("modem_switch_active_end", &self.modem_switch_active_end())
+            .field("sleep_switch_active_end", &self.sleep_switch_active_end())
+            .field("sleep_switch_modem_end", &self.sleep_switch_modem_end())
+            .field("modem_switch_sleep_end", &self.modem_switch_sleep_end())
+            .field("active_switch_sleep_end", &self.active_switch_sleep_end())
             .field(
                 "modem_switch_active_start",
-                &format_args!("{}", self.modem_switch_active_start().bit()),
+                &self.modem_switch_active_start(),
             )
             .field(
                 "sleep_switch_active_start",
-                &format_args!("{}", self.sleep_switch_active_start().bit()),
-            )
-            .field(
-                "sleep_switch_modem_start",
-                &format_args!("{}", self.sleep_switch_modem_start().bit()),
-            )
-            .field(
-                "modem_switch_sleep_start",
-                &format_args!("{}", self.modem_switch_sleep_start().bit()),
+                &self.sleep_switch_active_start(),
             )
+            .field("sleep_switch_modem_start", &self.sleep_switch_modem_start())
+            .field("modem_switch_sleep_start", &self.modem_switch_sleep_start())
             .field(
                 "active_switch_sleep_start",
-                &format_args!("{}", self.active_switch_sleep_start().bit()),
-            )
-            .field(
-                "hp_sw_trigger",
-                &format_args!("{}", self.hp_sw_trigger().bit()),
+                &self.active_switch_sleep_start(),
             )
+            .field("hp_sw_trigger", &self.hp_sw_trigger())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/lp_int_raw.rs b/esp32c6/src/pmu/lp_int_raw.rs
index 69bebde980..b5a4ac446b 100644
--- a/esp32c6/src/pmu/lp_int_raw.rs
+++ b/esp32c6/src/pmu/lp_int_raw.rs
@@ -116,63 +116,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_RAW")
-            .field(
-                "lp_cpu_wakeup",
-                &format_args!("{}", self.lp_cpu_wakeup().bit()),
-            )
-            .field(
-                "modem_switch_active_end",
-                &format_args!("{}", self.modem_switch_active_end().bit()),
-            )
-            .field(
-                "sleep_switch_active_end",
-                &format_args!("{}", self.sleep_switch_active_end().bit()),
-            )
-            .field(
-                "sleep_switch_modem_end",
-                &format_args!("{}", self.sleep_switch_modem_end().bit()),
-            )
-            .field(
-                "modem_switch_sleep_end",
-                &format_args!("{}", self.modem_switch_sleep_end().bit()),
-            )
-            .field(
-                "active_switch_sleep_end",
-                &format_args!("{}", self.active_switch_sleep_end().bit()),
-            )
+            .field("lp_cpu_wakeup", &self.lp_cpu_wakeup())
+            .field("modem_switch_active_end", &self.modem_switch_active_end())
+            .field("sleep_switch_active_end", &self.sleep_switch_active_end())
+            .field("sleep_switch_modem_end", &self.sleep_switch_modem_end())
+            .field("modem_switch_sleep_end", &self.modem_switch_sleep_end())
+            .field("active_switch_sleep_end", &self.active_switch_sleep_end())
             .field(
                 "modem_switch_active_start",
-                &format_args!("{}", self.modem_switch_active_start().bit()),
+                &self.modem_switch_active_start(),
             )
             .field(
                 "sleep_switch_active_start",
-                &format_args!("{}", self.sleep_switch_active_start().bit()),
-            )
-            .field(
-                "sleep_switch_modem_start",
-                &format_args!("{}", self.sleep_switch_modem_start().bit()),
-            )
-            .field(
-                "modem_switch_sleep_start",
-                &format_args!("{}", self.modem_switch_sleep_start().bit()),
+                &self.sleep_switch_active_start(),
             )
+            .field("sleep_switch_modem_start", &self.sleep_switch_modem_start())
+            .field("modem_switch_sleep_start", &self.modem_switch_sleep_start())
             .field(
                 "active_switch_sleep_start",
-                &format_args!("{}", self.active_switch_sleep_start().bit()),
-            )
-            .field(
-                "hp_sw_trigger",
-                &format_args!("{}", self.hp_sw_trigger().bit()),
+                &self.active_switch_sleep_start(),
             )
+            .field("hp_sw_trigger", &self.hp_sw_trigger())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/lp_int_st.rs b/esp32c6/src/pmu/lp_int_st.rs
index f0248a2958..4d5b520ec0 100644
--- a/esp32c6/src/pmu/lp_int_st.rs
+++ b/esp32c6/src/pmu/lp_int_st.rs
@@ -90,63 +90,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ST")
-            .field(
-                "lp_cpu_wakeup",
-                &format_args!("{}", self.lp_cpu_wakeup().bit()),
-            )
-            .field(
-                "modem_switch_active_end",
-                &format_args!("{}", self.modem_switch_active_end().bit()),
-            )
-            .field(
-                "sleep_switch_active_end",
-                &format_args!("{}", self.sleep_switch_active_end().bit()),
-            )
-            .field(
-                "sleep_switch_modem_end",
-                &format_args!("{}", self.sleep_switch_modem_end().bit()),
-            )
-            .field(
-                "modem_switch_sleep_end",
-                &format_args!("{}", self.modem_switch_sleep_end().bit()),
-            )
-            .field(
-                "active_switch_sleep_end",
-                &format_args!("{}", self.active_switch_sleep_end().bit()),
-            )
+            .field("lp_cpu_wakeup", &self.lp_cpu_wakeup())
+            .field("modem_switch_active_end", &self.modem_switch_active_end())
+            .field("sleep_switch_active_end", &self.sleep_switch_active_end())
+            .field("sleep_switch_modem_end", &self.sleep_switch_modem_end())
+            .field("modem_switch_sleep_end", &self.modem_switch_sleep_end())
+            .field("active_switch_sleep_end", &self.active_switch_sleep_end())
             .field(
                 "modem_switch_active_start",
-                &format_args!("{}", self.modem_switch_active_start().bit()),
+                &self.modem_switch_active_start(),
             )
             .field(
                 "sleep_switch_active_start",
-                &format_args!("{}", self.sleep_switch_active_start().bit()),
-            )
-            .field(
-                "sleep_switch_modem_start",
-                &format_args!("{}", self.sleep_switch_modem_start().bit()),
-            )
-            .field(
-                "modem_switch_sleep_start",
-                &format_args!("{}", self.modem_switch_sleep_start().bit()),
+                &self.sleep_switch_active_start(),
             )
+            .field("sleep_switch_modem_start", &self.sleep_switch_modem_start())
+            .field("modem_switch_sleep_start", &self.modem_switch_sleep_start())
             .field(
                 "active_switch_sleep_start",
-                &format_args!("{}", self.active_switch_sleep_start().bit()),
-            )
-            .field(
-                "hp_sw_trigger",
-                &format_args!("{}", self.hp_sw_trigger().bit()),
+                &self.active_switch_sleep_start(),
             )
+            .field("hp_sw_trigger", &self.hp_sw_trigger())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_INT_ST_SPEC;
 impl crate::RegisterSpec for LP_INT_ST_SPEC {
diff --git a/esp32c6/src/pmu/lp_sleep_bias.rs b/esp32c6/src/pmu/lp_sleep_bias.rs
index a5b438dea0..52b4077b44 100644
--- a/esp32c6/src/pmu/lp_sleep_bias.rs
+++ b/esp32c6/src/pmu/lp_sleep_bias.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SLEEP_BIAS")
-            .field(
-                "lp_sleep_xpd_bias",
-                &format_args!("{}", self.lp_sleep_xpd_bias().bit()),
-            )
-            .field(
-                "lp_sleep_dbg_atten",
-                &format_args!("{}", self.lp_sleep_dbg_atten().bits()),
-            )
-            .field(
-                "lp_sleep_pd_cur",
-                &format_args!("{}", self.lp_sleep_pd_cur().bit()),
-            )
-            .field("sleep", &format_args!("{}", self.sleep().bit()))
+            .field("lp_sleep_xpd_bias", &self.lp_sleep_xpd_bias())
+            .field("lp_sleep_dbg_atten", &self.lp_sleep_dbg_atten())
+            .field("lp_sleep_pd_cur", &self.lp_sleep_pd_cur())
+            .field("sleep", &self.sleep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_BIAS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/lp_sleep_lp_ck_power.rs b/esp32c6/src/pmu/lp_sleep_lp_ck_power.rs
index ce49407ac0..633004fe4b 100644
--- a/esp32c6/src/pmu/lp_sleep_lp_ck_power.rs
+++ b/esp32c6/src/pmu/lp_sleep_lp_ck_power.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SLEEP_LP_CK_POWER")
-            .field(
-                "lp_sleep_xpd_xtal32k",
-                &format_args!("{}", self.lp_sleep_xpd_xtal32k().bit()),
-            )
-            .field(
-                "lp_sleep_xpd_rc32k",
-                &format_args!("{}", self.lp_sleep_xpd_rc32k().bit()),
-            )
-            .field(
-                "lp_sleep_xpd_fosc_clk",
-                &format_args!("{}", self.lp_sleep_xpd_fosc_clk().bit()),
-            )
-            .field(
-                "lp_sleep_pd_osc_clk",
-                &format_args!("{}", self.lp_sleep_pd_osc_clk().bit()),
-            )
+            .field("lp_sleep_xpd_xtal32k", &self.lp_sleep_xpd_xtal32k())
+            .field("lp_sleep_xpd_rc32k", &self.lp_sleep_xpd_rc32k())
+            .field("lp_sleep_xpd_fosc_clk", &self.lp_sleep_xpd_fosc_clk())
+            .field("lp_sleep_pd_osc_clk", &self.lp_sleep_pd_osc_clk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_LP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/lp_sleep_lp_dig_power.rs b/esp32c6/src/pmu/lp_sleep_lp_dig_power.rs
index e2fcf3899a..879b962fab 100644
--- a/esp32c6/src/pmu/lp_sleep_lp_dig_power.rs
+++ b/esp32c6/src/pmu/lp_sleep_lp_dig_power.rs
@@ -26,23 +26,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SLEEP_LP_DIG_POWER")
-            .field(
-                "lp_sleep_lp_mem_dslp",
-                &format_args!("{}", self.lp_sleep_lp_mem_dslp().bit()),
-            )
+            .field("lp_sleep_lp_mem_dslp", &self.lp_sleep_lp_mem_dslp())
             .field(
                 "lp_sleep_pd_lp_peri_pd_en",
-                &format_args!("{}", self.lp_sleep_pd_lp_peri_pd_en().bit()),
+                &self.lp_sleep_pd_lp_peri_pd_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_LP_DIG_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/lp_sleep_lp_regulator0.rs b/esp32c6/src/pmu/lp_sleep_lp_regulator0.rs
index 931f46ac78..3705814cf1 100644
--- a/esp32c6/src/pmu/lp_sleep_lp_regulator0.rs
+++ b/esp32c6/src/pmu/lp_sleep_lp_regulator0.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_SLEEP_LP_REGULATOR0")
             .field(
                 "lp_sleep_lp_regulator_slp_xpd",
-                &format_args!("{}", self.lp_sleep_lp_regulator_slp_xpd().bit()),
+                &self.lp_sleep_lp_regulator_slp_xpd(),
             )
             .field(
                 "lp_sleep_lp_regulator_xpd",
-                &format_args!("{}", self.lp_sleep_lp_regulator_xpd().bit()),
+                &self.lp_sleep_lp_regulator_xpd(),
             )
             .field(
                 "lp_sleep_lp_regulator_slp_dbias",
-                &format_args!("{}", self.lp_sleep_lp_regulator_slp_dbias().bits()),
+                &self.lp_sleep_lp_regulator_slp_dbias(),
             )
             .field(
                 "lp_sleep_lp_regulator_dbias",
-                &format_args!("{}", self.lp_sleep_lp_regulator_dbias().bits()),
+                &self.lp_sleep_lp_regulator_dbias(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_LP_REGULATOR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/lp_sleep_lp_regulator1.rs b/esp32c6/src/pmu/lp_sleep_lp_regulator1.rs
index 3e0fde22f0..29f95fd5f3 100644
--- a/esp32c6/src/pmu/lp_sleep_lp_regulator1.rs
+++ b/esp32c6/src/pmu/lp_sleep_lp_regulator1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_SLEEP_LP_REGULATOR1")
             .field(
                 "lp_sleep_lp_regulator_drv_b",
-                &format_args!("{}", self.lp_sleep_lp_regulator_drv_b().bits()),
+                &self.lp_sleep_lp_regulator_drv_b(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_LP_REGULATOR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 28:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/lp_sleep_xtal.rs b/esp32c6/src/pmu/lp_sleep_xtal.rs
index bae4466d7d..cc7e2ac036 100644
--- a/esp32c6/src/pmu/lp_sleep_xtal.rs
+++ b/esp32c6/src/pmu/lp_sleep_xtal.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SLEEP_XTAL")
-            .field(
-                "lp_sleep_xpd_xtal",
-                &format_args!("{}", self.lp_sleep_xpd_xtal().bit()),
-            )
+            .field("lp_sleep_xpd_xtal", &self.lp_sleep_xpd_xtal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_XTAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/main_state.rs b/esp32c6/src/pmu/main_state.rs
index 35b059b8ee..f71881eaf6 100644
--- a/esp32c6/src/pmu/main_state.rs
+++ b/esp32c6/src/pmu/main_state.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_STATE")
-            .field(
-                "main_last_st_state",
-                &format_args!("{}", self.main_last_st_state().bits()),
-            )
-            .field(
-                "main_tar_st_state",
-                &format_args!("{}", self.main_tar_st_state().bits()),
-            )
-            .field(
-                "main_cur_st_state",
-                &format_args!("{}", self.main_cur_st_state().bits()),
-            )
+            .field("main_last_st_state", &self.main_last_st_state())
+            .field("main_tar_st_state", &self.main_tar_st_state())
+            .field("main_cur_st_state", &self.main_cur_st_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_STATE_SPEC;
 impl crate::RegisterSpec for MAIN_STATE_SPEC {
diff --git a/esp32c6/src/pmu/por_status.rs b/esp32c6/src/pmu/por_status.rs
index eb68c0356d..1625236680 100644
--- a/esp32c6/src/pmu/por_status.rs
+++ b/esp32c6/src/pmu/por_status.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POR_STATUS")
-            .field("por_done", &format_args!("{}", self.por_done().bit()))
+            .field("por_done", &self.por_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POR_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`por_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct POR_STATUS_SPEC;
 impl crate::RegisterSpec for POR_STATUS_SPEC {
diff --git a/esp32c6/src/pmu/power_ck_wait_cntl.rs b/esp32c6/src/pmu/power_ck_wait_cntl.rs
index 18c01ff3d4..0b335ec4d2 100644
--- a/esp32c6/src/pmu/power_ck_wait_cntl.rs
+++ b/esp32c6/src/pmu/power_ck_wait_cntl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_CK_WAIT_CNTL")
-            .field(
-                "wait_xtl_stable",
-                &format_args!("{}", self.wait_xtl_stable().bits()),
-            )
-            .field(
-                "wait_pll_stable",
-                &format_args!("{}", self.wait_pll_stable().bits()),
-            )
+            .field("wait_xtl_stable", &self.wait_xtl_stable())
+            .field("wait_pll_stable", &self.wait_pll_stable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_CK_WAIT_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/power_hp_pad.rs b/esp32c6/src/pmu/power_hp_pad.rs
index c28d331333..b339bbef5d 100644
--- a/esp32c6/src/pmu/power_hp_pad.rs
+++ b/esp32c6/src/pmu/power_hp_pad.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_HP_PAD")
-            .field(
-                "force_hp_pad_no_iso_all",
-                &format_args!("{}", self.force_hp_pad_no_iso_all().bit()),
-            )
-            .field(
-                "force_hp_pad_iso_all",
-                &format_args!("{}", self.force_hp_pad_iso_all().bit()),
-            )
+            .field("force_hp_pad_no_iso_all", &self.force_hp_pad_no_iso_all())
+            .field("force_hp_pad_iso_all", &self.force_hp_pad_iso_all())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_HP_PAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/power_pd_hpaon_cntl.rs b/esp32c6/src/pmu/power_pd_hpaon_cntl.rs
index a4ac0554a9..bb42f2229c 100644
--- a/esp32c6/src/pmu/power_pd_hpaon_cntl.rs
+++ b/esp32c6/src/pmu/power_pd_hpaon_cntl.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_HPAON_CNTL")
-            .field(
-                "force_hp_aon_reset",
-                &format_args!("{}", self.force_hp_aon_reset().bit()),
-            )
-            .field(
-                "force_hp_aon_iso",
-                &format_args!("{}", self.force_hp_aon_iso().bit()),
-            )
-            .field(
-                "force_hp_aon_pu",
-                &format_args!("{}", self.force_hp_aon_pu().bit()),
-            )
-            .field(
-                "force_hp_aon_no_reset",
-                &format_args!("{}", self.force_hp_aon_no_reset().bit()),
-            )
-            .field(
-                "force_hp_aon_no_iso",
-                &format_args!("{}", self.force_hp_aon_no_iso().bit()),
-            )
-            .field(
-                "force_hp_aon_pd",
-                &format_args!("{}", self.force_hp_aon_pd().bit()),
-            )
-            .field(
-                "pd_hp_aon_mask",
-                &format_args!("{}", self.pd_hp_aon_mask().bits()),
-            )
-            .field(
-                "pd_hp_aon_pd_mask",
-                &format_args!("{}", self.pd_hp_aon_pd_mask().bits()),
-            )
+            .field("force_hp_aon_reset", &self.force_hp_aon_reset())
+            .field("force_hp_aon_iso", &self.force_hp_aon_iso())
+            .field("force_hp_aon_pu", &self.force_hp_aon_pu())
+            .field("force_hp_aon_no_reset", &self.force_hp_aon_no_reset())
+            .field("force_hp_aon_no_iso", &self.force_hp_aon_no_iso())
+            .field("force_hp_aon_pd", &self.force_hp_aon_pd())
+            .field("pd_hp_aon_mask", &self.pd_hp_aon_mask())
+            .field("pd_hp_aon_pd_mask", &self.pd_hp_aon_pd_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_HPAON_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/power_pd_hpcpu_cntl.rs b/esp32c6/src/pmu/power_pd_hpcpu_cntl.rs
index 2c7e4d97ee..9bd4d5df8d 100644
--- a/esp32c6/src/pmu/power_pd_hpcpu_cntl.rs
+++ b/esp32c6/src/pmu/power_pd_hpcpu_cntl.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_HPCPU_CNTL")
-            .field(
-                "force_hp_cpu_reset",
-                &format_args!("{}", self.force_hp_cpu_reset().bit()),
-            )
-            .field(
-                "force_hp_cpu_iso",
-                &format_args!("{}", self.force_hp_cpu_iso().bit()),
-            )
-            .field(
-                "force_hp_cpu_pu",
-                &format_args!("{}", self.force_hp_cpu_pu().bit()),
-            )
-            .field(
-                "force_hp_cpu_no_reset",
-                &format_args!("{}", self.force_hp_cpu_no_reset().bit()),
-            )
-            .field(
-                "force_hp_cpu_no_iso",
-                &format_args!("{}", self.force_hp_cpu_no_iso().bit()),
-            )
-            .field(
-                "force_hp_cpu_pd",
-                &format_args!("{}", self.force_hp_cpu_pd().bit()),
-            )
-            .field(
-                "pd_hp_cpu_mask",
-                &format_args!("{}", self.pd_hp_cpu_mask().bits()),
-            )
-            .field(
-                "pd_hp_cpu_pd_mask",
-                &format_args!("{}", self.pd_hp_cpu_pd_mask().bits()),
-            )
+            .field("force_hp_cpu_reset", &self.force_hp_cpu_reset())
+            .field("force_hp_cpu_iso", &self.force_hp_cpu_iso())
+            .field("force_hp_cpu_pu", &self.force_hp_cpu_pu())
+            .field("force_hp_cpu_no_reset", &self.force_hp_cpu_no_reset())
+            .field("force_hp_cpu_no_iso", &self.force_hp_cpu_no_iso())
+            .field("force_hp_cpu_pd", &self.force_hp_cpu_pd())
+            .field("pd_hp_cpu_mask", &self.pd_hp_cpu_mask())
+            .field("pd_hp_cpu_pd_mask", &self.pd_hp_cpu_pd_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_HPCPU_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/power_pd_hpwifi_cntl.rs b/esp32c6/src/pmu/power_pd_hpwifi_cntl.rs
index b1f7743055..d89bf9d7e2 100644
--- a/esp32c6/src/pmu/power_pd_hpwifi_cntl.rs
+++ b/esp32c6/src/pmu/power_pd_hpwifi_cntl.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_HPWIFI_CNTL")
-            .field(
-                "force_hp_wifi_reset",
-                &format_args!("{}", self.force_hp_wifi_reset().bit()),
-            )
-            .field(
-                "force_hp_wifi_iso",
-                &format_args!("{}", self.force_hp_wifi_iso().bit()),
-            )
-            .field(
-                "force_hp_wifi_pu",
-                &format_args!("{}", self.force_hp_wifi_pu().bit()),
-            )
-            .field(
-                "force_hp_wifi_no_reset",
-                &format_args!("{}", self.force_hp_wifi_no_reset().bit()),
-            )
-            .field(
-                "force_hp_wifi_no_iso",
-                &format_args!("{}", self.force_hp_wifi_no_iso().bit()),
-            )
-            .field(
-                "force_hp_wifi_pd",
-                &format_args!("{}", self.force_hp_wifi_pd().bit()),
-            )
-            .field(
-                "pd_hp_wifi_mask",
-                &format_args!("{}", self.pd_hp_wifi_mask().bits()),
-            )
-            .field(
-                "pd_hp_wifi_pd_mask",
-                &format_args!("{}", self.pd_hp_wifi_pd_mask().bits()),
-            )
+            .field("force_hp_wifi_reset", &self.force_hp_wifi_reset())
+            .field("force_hp_wifi_iso", &self.force_hp_wifi_iso())
+            .field("force_hp_wifi_pu", &self.force_hp_wifi_pu())
+            .field("force_hp_wifi_no_reset", &self.force_hp_wifi_no_reset())
+            .field("force_hp_wifi_no_iso", &self.force_hp_wifi_no_iso())
+            .field("force_hp_wifi_pd", &self.force_hp_wifi_pd())
+            .field("pd_hp_wifi_mask", &self.pd_hp_wifi_mask())
+            .field("pd_hp_wifi_pd_mask", &self.pd_hp_wifi_pd_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_HPWIFI_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/power_pd_lpperi_cntl.rs b/esp32c6/src/pmu/power_pd_lpperi_cntl.rs
index 6f27fae0e2..f1a688639c 100644
--- a/esp32c6/src/pmu/power_pd_lpperi_cntl.rs
+++ b/esp32c6/src/pmu/power_pd_lpperi_cntl.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_LPPERI_CNTL")
-            .field(
-                "force_lp_peri_reset",
-                &format_args!("{}", self.force_lp_peri_reset().bit()),
-            )
-            .field(
-                "force_lp_peri_iso",
-                &format_args!("{}", self.force_lp_peri_iso().bit()),
-            )
-            .field(
-                "force_lp_peri_pu",
-                &format_args!("{}", self.force_lp_peri_pu().bit()),
-            )
-            .field(
-                "force_lp_peri_no_reset",
-                &format_args!("{}", self.force_lp_peri_no_reset().bit()),
-            )
-            .field(
-                "force_lp_peri_no_iso",
-                &format_args!("{}", self.force_lp_peri_no_iso().bit()),
-            )
-            .field(
-                "force_lp_peri_pd",
-                &format_args!("{}", self.force_lp_peri_pd().bit()),
-            )
+            .field("force_lp_peri_reset", &self.force_lp_peri_reset())
+            .field("force_lp_peri_iso", &self.force_lp_peri_iso())
+            .field("force_lp_peri_pu", &self.force_lp_peri_pu())
+            .field("force_lp_peri_no_reset", &self.force_lp_peri_no_reset())
+            .field("force_lp_peri_no_iso", &self.force_lp_peri_no_iso())
+            .field("force_lp_peri_pd", &self.force_lp_peri_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_LPPERI_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/power_pd_mem_cntl.rs b/esp32c6/src/pmu/power_pd_mem_cntl.rs
index 81314bf2a5..6297526aa0 100644
--- a/esp32c6/src/pmu/power_pd_mem_cntl.rs
+++ b/esp32c6/src/pmu/power_pd_mem_cntl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_MEM_CNTL")
-            .field(
-                "force_hp_mem_iso",
-                &format_args!("{}", self.force_hp_mem_iso().bits()),
-            )
-            .field(
-                "force_hp_mem_pd",
-                &format_args!("{}", self.force_hp_mem_pd().bits()),
-            )
-            .field(
-                "force_hp_mem_no_iso",
-                &format_args!("{}", self.force_hp_mem_no_iso().bits()),
-            )
-            .field(
-                "force_hp_mem_pu",
-                &format_args!("{}", self.force_hp_mem_pu().bits()),
-            )
+            .field("force_hp_mem_iso", &self.force_hp_mem_iso())
+            .field("force_hp_mem_pd", &self.force_hp_mem_pd())
+            .field("force_hp_mem_no_iso", &self.force_hp_mem_no_iso())
+            .field("force_hp_mem_pu", &self.force_hp_mem_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_MEM_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/power_pd_mem_mask.rs b/esp32c6/src/pmu/power_pd_mem_mask.rs
index 9ea2a97a10..ea6fa14c62 100644
--- a/esp32c6/src/pmu/power_pd_mem_mask.rs
+++ b/esp32c6/src/pmu/power_pd_mem_mask.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_MEM_MASK")
-            .field(
-                "pd_hp_mem2_pd_mask",
-                &format_args!("{}", self.pd_hp_mem2_pd_mask().bits()),
-            )
-            .field(
-                "pd_hp_mem1_pd_mask",
-                &format_args!("{}", self.pd_hp_mem1_pd_mask().bits()),
-            )
-            .field(
-                "pd_hp_mem0_pd_mask",
-                &format_args!("{}", self.pd_hp_mem0_pd_mask().bits()),
-            )
-            .field(
-                "pd_hp_mem2_mask",
-                &format_args!("{}", self.pd_hp_mem2_mask().bits()),
-            )
-            .field(
-                "pd_hp_mem1_mask",
-                &format_args!("{}", self.pd_hp_mem1_mask().bits()),
-            )
-            .field(
-                "pd_hp_mem0_mask",
-                &format_args!("{}", self.pd_hp_mem0_mask().bits()),
-            )
+            .field("pd_hp_mem2_pd_mask", &self.pd_hp_mem2_pd_mask())
+            .field("pd_hp_mem1_pd_mask", &self.pd_hp_mem1_pd_mask())
+            .field("pd_hp_mem0_pd_mask", &self.pd_hp_mem0_pd_mask())
+            .field("pd_hp_mem2_mask", &self.pd_hp_mem2_mask())
+            .field("pd_hp_mem1_mask", &self.pd_hp_mem1_mask())
+            .field("pd_hp_mem0_mask", &self.pd_hp_mem0_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_MEM_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/power_pd_top_cntl.rs b/esp32c6/src/pmu/power_pd_top_cntl.rs
index 4beb2e1b2b..e753fe5a3b 100644
--- a/esp32c6/src/pmu/power_pd_top_cntl.rs
+++ b/esp32c6/src/pmu/power_pd_top_cntl.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_TOP_CNTL")
-            .field(
-                "force_top_reset",
-                &format_args!("{}", self.force_top_reset().bit()),
-            )
-            .field(
-                "force_top_iso",
-                &format_args!("{}", self.force_top_iso().bit()),
-            )
-            .field(
-                "force_top_pu",
-                &format_args!("{}", self.force_top_pu().bit()),
-            )
-            .field(
-                "force_top_no_reset",
-                &format_args!("{}", self.force_top_no_reset().bit()),
-            )
-            .field(
-                "force_top_no_iso",
-                &format_args!("{}", self.force_top_no_iso().bit()),
-            )
-            .field(
-                "force_top_pd",
-                &format_args!("{}", self.force_top_pd().bit()),
-            )
-            .field(
-                "pd_top_mask",
-                &format_args!("{}", self.pd_top_mask().bits()),
-            )
-            .field(
-                "pd_top_pd_mask",
-                &format_args!("{}", self.pd_top_pd_mask().bits()),
-            )
+            .field("force_top_reset", &self.force_top_reset())
+            .field("force_top_iso", &self.force_top_iso())
+            .field("force_top_pu", &self.force_top_pu())
+            .field("force_top_no_reset", &self.force_top_no_reset())
+            .field("force_top_no_iso", &self.force_top_no_iso())
+            .field("force_top_pd", &self.force_top_pd())
+            .field("pd_top_mask", &self.pd_top_mask())
+            .field("pd_top_pd_mask", &self.pd_top_pd_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_TOP_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/power_vdd_spi_cntl.rs b/esp32c6/src/pmu/power_vdd_spi_cntl.rs
index ba88db2c4a..baf42e1726 100644
--- a/esp32c6/src/pmu/power_vdd_spi_cntl.rs
+++ b/esp32c6/src/pmu/power_vdd_spi_cntl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_VDD_SPI_CNTL")
-            .field(
-                "vdd_spi_pwr_wait",
-                &format_args!("{}", self.vdd_spi_pwr_wait().bits()),
-            )
-            .field(
-                "vdd_spi_pwr_sw",
-                &format_args!("{}", self.vdd_spi_pwr_sw().bits()),
-            )
-            .field(
-                "vdd_spi_pwr_sel_sw",
-                &format_args!("{}", self.vdd_spi_pwr_sel_sw().bit()),
-            )
+            .field("vdd_spi_pwr_wait", &self.vdd_spi_pwr_wait())
+            .field("vdd_spi_pwr_sw", &self.vdd_spi_pwr_sw())
+            .field("vdd_spi_pwr_sel_sw", &self.vdd_spi_pwr_sel_sw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_VDD_SPI_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 18:28 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/power_wait_timer0.rs b/esp32c6/src/pmu/power_wait_timer0.rs
index 30802f3fd5..b3cf314033 100644
--- a/esp32c6/src/pmu/power_wait_timer0.rs
+++ b/esp32c6/src/pmu/power_wait_timer0.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_WAIT_TIMER0")
-            .field(
-                "dg_hp_powerdown_timer",
-                &format_args!("{}", self.dg_hp_powerdown_timer().bits()),
-            )
-            .field(
-                "dg_hp_powerup_timer",
-                &format_args!("{}", self.dg_hp_powerup_timer().bits()),
-            )
-            .field(
-                "dg_hp_wait_timer",
-                &format_args!("{}", self.dg_hp_wait_timer().bits()),
-            )
+            .field("dg_hp_powerdown_timer", &self.dg_hp_powerdown_timer())
+            .field("dg_hp_powerup_timer", &self.dg_hp_powerup_timer())
+            .field("dg_hp_wait_timer", &self.dg_hp_wait_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_WAIT_TIMER0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 5:13 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/power_wait_timer1.rs b/esp32c6/src/pmu/power_wait_timer1.rs
index 877451923f..af896ee3a5 100644
--- a/esp32c6/src/pmu/power_wait_timer1.rs
+++ b/esp32c6/src/pmu/power_wait_timer1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_WAIT_TIMER1")
-            .field(
-                "dg_lp_powerdown_timer",
-                &format_args!("{}", self.dg_lp_powerdown_timer().bits()),
-            )
-            .field(
-                "dg_lp_powerup_timer",
-                &format_args!("{}", self.dg_lp_powerup_timer().bits()),
-            )
-            .field(
-                "dg_lp_wait_timer",
-                &format_args!("{}", self.dg_lp_wait_timer().bits()),
-            )
+            .field("dg_lp_powerdown_timer", &self.dg_lp_powerdown_timer())
+            .field("dg_lp_powerup_timer", &self.dg_lp_powerup_timer())
+            .field("dg_lp_wait_timer", &self.dg_lp_wait_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_WAIT_TIMER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 9:15 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/pwr_state.rs b/esp32c6/src/pmu/pwr_state.rs
index 70a9b5f028..372452f2d2 100644
--- a/esp32c6/src/pmu/pwr_state.rs
+++ b/esp32c6/src/pmu/pwr_state.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWR_STATE")
-            .field(
-                "backup_st_state",
-                &format_args!("{}", self.backup_st_state().bits()),
-            )
-            .field(
-                "lp_pwr_st_state",
-                &format_args!("{}", self.lp_pwr_st_state().bits()),
-            )
-            .field(
-                "hp_pwr_st_state",
-                &format_args!("{}", self.hp_pwr_st_state().bits()),
-            )
+            .field("backup_st_state", &self.backup_st_state())
+            .field("lp_pwr_st_state", &self.lp_pwr_st_state())
+            .field("hp_pwr_st_state", &self.hp_pwr_st_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWR_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwr_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PWR_STATE_SPEC;
 impl crate::RegisterSpec for PWR_STATE_SPEC {
diff --git a/esp32c6/src/pmu/rf_pwc.rs b/esp32c6/src/pmu/rf_pwc.rs
index 03ce0f616d..90262ef5ae 100644
--- a/esp32c6/src/pmu/rf_pwc.rs
+++ b/esp32c6/src/pmu/rf_pwc.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RF_PWC")
-            .field(
-                "perif_i2c_rstb",
-                &format_args!("{}", self.perif_i2c_rstb().bit()),
-            )
-            .field(
-                "xpd_perif_i2c",
-                &format_args!("{}", self.xpd_perif_i2c().bit()),
-            )
-            .field(
-                "xpd_txrf_i2c",
-                &format_args!("{}", self.xpd_txrf_i2c().bit()),
-            )
-            .field(
-                "xpd_rfrx_pbus",
-                &format_args!("{}", self.xpd_rfrx_pbus().bit()),
-            )
-            .field(
-                "xpd_ckgen_i2c",
-                &format_args!("{}", self.xpd_ckgen_i2c().bit()),
-            )
-            .field("xpd_pll_i2c", &format_args!("{}", self.xpd_pll_i2c().bit()))
+            .field("perif_i2c_rstb", &self.perif_i2c_rstb())
+            .field("xpd_perif_i2c", &self.xpd_perif_i2c())
+            .field("xpd_txrf_i2c", &self.xpd_txrf_i2c())
+            .field("xpd_rfrx_pbus", &self.xpd_rfrx_pbus())
+            .field("xpd_ckgen_i2c", &self.xpd_ckgen_i2c())
+            .field("xpd_pll_i2c", &self.xpd_pll_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RF_PWC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/slp_wakeup_cntl1.rs b/esp32c6/src/pmu/slp_wakeup_cntl1.rs
index b5813a7699..0211531bff 100644
--- a/esp32c6/src/pmu/slp_wakeup_cntl1.rs
+++ b/esp32c6/src/pmu/slp_wakeup_cntl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL1")
-            .field(
-                "sleep_reject_ena",
-                &format_args!("{}", self.sleep_reject_ena().bits()),
-            )
-            .field(
-                "slp_reject_en",
-                &format_args!("{}", self.slp_reject_en().bit()),
-            )
+            .field("sleep_reject_ena", &self.sleep_reject_ena())
+            .field("slp_reject_en", &self.slp_reject_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/slp_wakeup_cntl2.rs b/esp32c6/src/pmu/slp_wakeup_cntl2.rs
index 96c4e3f3a8..da7355e764 100644
--- a/esp32c6/src/pmu/slp_wakeup_cntl2.rs
+++ b/esp32c6/src/pmu/slp_wakeup_cntl2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL2")
-            .field("wakeup_ena", &format_args!("{}", self.wakeup_ena().bits()))
+            .field("wakeup_ena", &self.wakeup_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/slp_wakeup_cntl3.rs b/esp32c6/src/pmu/slp_wakeup_cntl3.rs
index b9fcfe21ca..dcde09eb3a 100644
--- a/esp32c6/src/pmu/slp_wakeup_cntl3.rs
+++ b/esp32c6/src/pmu/slp_wakeup_cntl3.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL3")
-            .field(
-                "lp_min_slp_val",
-                &format_args!("{}", self.lp_min_slp_val().bits()),
-            )
-            .field(
-                "hp_min_slp_val",
-                &format_args!("{}", self.hp_min_slp_val().bits()),
-            )
-            .field(
-                "sleep_prt_sel",
-                &format_args!("{}", self.sleep_prt_sel().bits()),
-            )
+            .field("lp_min_slp_val", &self.lp_min_slp_val())
+            .field("hp_min_slp_val", &self.hp_min_slp_val())
+            .field("sleep_prt_sel", &self.sleep_prt_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/slp_wakeup_cntl5.rs b/esp32c6/src/pmu/slp_wakeup_cntl5.rs
index 0073fbaa70..6022a5a3ee 100644
--- a/esp32c6/src/pmu/slp_wakeup_cntl5.rs
+++ b/esp32c6/src/pmu/slp_wakeup_cntl5.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL5")
-            .field(
-                "modem_wait_target",
-                &format_args!("{}", self.modem_wait_target().bits()),
-            )
-            .field(
-                "lp_ana_wait_target",
-                &format_args!("{}", self.lp_ana_wait_target().bits()),
-            )
+            .field("modem_wait_target", &self.modem_wait_target())
+            .field("lp_ana_wait_target", &self.lp_ana_wait_target())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/slp_wakeup_cntl6.rs b/esp32c6/src/pmu/slp_wakeup_cntl6.rs
index 30e86accf3..9aff65cbae 100644
--- a/esp32c6/src/pmu/slp_wakeup_cntl6.rs
+++ b/esp32c6/src/pmu/slp_wakeup_cntl6.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL6")
-            .field(
-                "soc_wakeup_wait",
-                &format_args!("{}", self.soc_wakeup_wait().bits()),
-            )
-            .field(
-                "soc_wakeup_wait_cfg",
-                &format_args!("{}", self.soc_wakeup_wait_cfg().bits()),
-            )
+            .field("soc_wakeup_wait", &self.soc_wakeup_wait())
+            .field("soc_wakeup_wait_cfg", &self.soc_wakeup_wait_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/slp_wakeup_cntl7.rs b/esp32c6/src/pmu/slp_wakeup_cntl7.rs
index 811e157fd8..ec649cb9a4 100644
--- a/esp32c6/src/pmu/slp_wakeup_cntl7.rs
+++ b/esp32c6/src/pmu/slp_wakeup_cntl7.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL7")
-            .field(
-                "ana_wait_target",
-                &format_args!("{}", self.ana_wait_target().bits()),
-            )
+            .field("ana_wait_target", &self.ana_wait_target())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - need_des"]
     #[inline(always)]
diff --git a/esp32c6/src/pmu/slp_wakeup_status0.rs b/esp32c6/src/pmu/slp_wakeup_status0.rs
index 46f04f39ac..ae53203367 100644
--- a/esp32c6/src/pmu/slp_wakeup_status0.rs
+++ b/esp32c6/src/pmu/slp_wakeup_status0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_STATUS0")
-            .field(
-                "wakeup_cause",
-                &format_args!("{}", self.wakeup_cause().bits()),
-            )
+            .field("wakeup_cause", &self.wakeup_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_STATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_status0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLP_WAKEUP_STATUS0_SPEC;
 impl crate::RegisterSpec for SLP_WAKEUP_STATUS0_SPEC {
diff --git a/esp32c6/src/pmu/slp_wakeup_status1.rs b/esp32c6/src/pmu/slp_wakeup_status1.rs
index 5f8f7be6a4..154f1b1e52 100644
--- a/esp32c6/src/pmu/slp_wakeup_status1.rs
+++ b/esp32c6/src/pmu/slp_wakeup_status1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_STATUS1")
-            .field(
-                "reject_cause",
-                &format_args!("{}", self.reject_cause().bits()),
-            )
+            .field("reject_cause", &self.reject_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_status1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLP_WAKEUP_STATUS1_SPEC;
 impl crate::RegisterSpec for SLP_WAKEUP_STATUS1_SPEC {
diff --git a/esp32c6/src/pmu/vdd_spi_status.rs b/esp32c6/src/pmu/vdd_spi_status.rs
index 7ac300b44e..95d0f5daf6 100644
--- a/esp32c6/src/pmu/vdd_spi_status.rs
+++ b/esp32c6/src/pmu/vdd_spi_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VDD_SPI_STATUS")
-            .field(
-                "stable_vdd_spi_pwr_drv",
-                &format_args!("{}", self.stable_vdd_spi_pwr_drv().bit()),
-            )
+            .field("stable_vdd_spi_pwr_drv", &self.stable_vdd_spi_pwr_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VDD_SPI_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vdd_spi_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VDD_SPI_STATUS_SPEC;
 impl crate::RegisterSpec for VDD_SPI_STATUS_SPEC {
diff --git a/esp32c6/src/rmt/ch_rx_carrier_rm.rs b/esp32c6/src/rmt/ch_rx_carrier_rm.rs
index 110fc179a3..d55c19dbf1 100644
--- a/esp32c6/src/rmt/ch_rx_carrier_rm.rs
+++ b/esp32c6/src/rmt/ch_rx_carrier_rm.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_CARRIER_RM")
-            .field(
-                "carrier_low_thres",
-                &format_args!("{}", self.carrier_low_thres().bits()),
-            )
-            .field(
-                "carrier_high_thres",
-                &format_args!("{}", self.carrier_high_thres().bits()),
-            )
+            .field("carrier_low_thres", &self.carrier_low_thres())
+            .field("carrier_high_thres", &self.carrier_high_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_CARRIER_RM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s."]
     #[inline(always)]
diff --git a/esp32c6/src/rmt/ch_rx_conf0.rs b/esp32c6/src/rmt/ch_rx_conf0.rs
index 0e3417b062..1e9b83cc9d 100644
--- a/esp32c6/src/rmt/ch_rx_conf0.rs
+++ b/esp32c6/src/rmt/ch_rx_conf0.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_CONF0")
-            .field("div_cnt", &format_args!("{}", self.div_cnt().bits()))
-            .field("idle_thres", &format_args!("{}", self.idle_thres().bits()))
-            .field("mem_size", &format_args!("{}", self.mem_size().bits()))
-            .field("carrier_en", &format_args!("{}", self.carrier_en().bit()))
-            .field(
-                "carrier_out_lv",
-                &format_args!("{}", self.carrier_out_lv().bit()),
-            )
+            .field("div_cnt", &self.div_cnt())
+            .field("idle_thres", &self.idle_thres())
+            .field("mem_size", &self.mem_size())
+            .field("carrier_en", &self.carrier_en())
+            .field("carrier_out_lv", &self.carrier_out_lv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the divider for clock of CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32c6/src/rmt/ch_rx_conf1.rs b/esp32c6/src/rmt/ch_rx_conf1.rs
index 4d32c964bc..7e8199c2e3 100644
--- a/esp32c6/src/rmt/ch_rx_conf1.rs
+++ b/esp32c6/src/rmt/ch_rx_conf1.rs
@@ -61,29 +61,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_CONF1")
-            .field("rx_en", &format_args!("{}", self.rx_en().bit()))
-            .field("mem_owner", &format_args!("{}", self.mem_owner().bit()))
-            .field(
-                "rx_filter_en",
-                &format_args!("{}", self.rx_filter_en().bit()),
-            )
-            .field(
-                "rx_filter_thres",
-                &format_args!("{}", self.rx_filter_thres().bits()),
-            )
-            .field(
-                "mem_rx_wrap_en",
-                &format_args!("{}", self.mem_rx_wrap_en().bit()),
-            )
+            .field("rx_en", &self.rx_en())
+            .field("mem_owner", &self.mem_owner())
+            .field("rx_filter_en", &self.rx_filter_en())
+            .field("rx_filter_thres", &self.rx_filter_thres())
+            .field("mem_rx_wrap_en", &self.mem_rx_wrap_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable receiver to receive data on CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32c6/src/rmt/ch_rx_lim.rs b/esp32c6/src/rmt/ch_rx_lim.rs
index 0d2391cf05..8d5fe9e952 100644
--- a/esp32c6/src/rmt/ch_rx_lim.rs
+++ b/esp32c6/src/rmt/ch_rx_lim.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_LIM")
-            .field("rmt_rx_lim", &format_args!("{}", self.rmt_rx_lim().bits()))
+            .field("rmt_rx_lim", &self.rmt_rx_lim())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_LIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can receive."]
     #[inline(always)]
diff --git a/esp32c6/src/rmt/ch_rx_status.rs b/esp32c6/src/rmt/ch_rx_status.rs
index 0147918bf4..b4778d0d10 100644
--- a/esp32c6/src/rmt/ch_rx_status.rs
+++ b/esp32c6/src/rmt/ch_rx_status.rs
@@ -48,33 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_STATUS")
-            .field(
-                "mem_waddr_ex",
-                &format_args!("{}", self.mem_waddr_ex().bits()),
-            )
-            .field(
-                "apb_mem_raddr",
-                &format_args!("{}", self.apb_mem_raddr().bits()),
-            )
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field(
-                "mem_owner_err",
-                &format_args!("{}", self.mem_owner_err().bit()),
-            )
-            .field("mem_full", &format_args!("{}", self.mem_full().bit()))
-            .field(
-                "apb_mem_rd_err",
-                &format_args!("{}", self.apb_mem_rd_err().bit()),
-            )
+            .field("mem_waddr_ex", &self.mem_waddr_ex())
+            .field("apb_mem_raddr", &self.apb_mem_raddr())
+            .field("state", &self.state())
+            .field("mem_owner_err", &self.mem_owner_err())
+            .field("mem_full", &self.mem_full())
+            .field("apb_mem_rd_err", &self.apb_mem_rd_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Channel %s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_RX_STATUS_SPEC;
 impl crate::RegisterSpec for CH_RX_STATUS_SPEC {
diff --git a/esp32c6/src/rmt/ch_tx_conf0.rs b/esp32c6/src/rmt/ch_tx_conf0.rs
index b86c765934..f1d6b5bea8 100644
--- a/esp32c6/src/rmt/ch_tx_conf0.rs
+++ b/esp32c6/src/rmt/ch_tx_conf0.rs
@@ -108,37 +108,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_TX_CONF0")
-            .field(
-                "tx_conti_mode",
-                &format_args!("{}", self.tx_conti_mode().bit()),
-            )
-            .field(
-                "mem_tx_wrap_en",
-                &format_args!("{}", self.mem_tx_wrap_en().bit()),
-            )
-            .field("idle_out_lv", &format_args!("{}", self.idle_out_lv().bit()))
-            .field("idle_out_en", &format_args!("{}", self.idle_out_en().bit()))
-            .field("tx_stop", &format_args!("{}", self.tx_stop().bit()))
-            .field("div_cnt", &format_args!("{}", self.div_cnt().bits()))
-            .field("mem_size", &format_args!("{}", self.mem_size().bits()))
-            .field(
-                "carrier_eff_en",
-                &format_args!("{}", self.carrier_eff_en().bit()),
-            )
-            .field("carrier_en", &format_args!("{}", self.carrier_en().bit()))
-            .field(
-                "carrier_out_lv",
-                &format_args!("{}", self.carrier_out_lv().bit()),
-            )
+            .field("tx_conti_mode", &self.tx_conti_mode())
+            .field("mem_tx_wrap_en", &self.mem_tx_wrap_en())
+            .field("idle_out_lv", &self.idle_out_lv())
+            .field("idle_out_en", &self.idle_out_en())
+            .field("tx_stop", &self.tx_stop())
+            .field("div_cnt", &self.div_cnt())
+            .field("mem_size", &self.mem_size())
+            .field("carrier_eff_en", &self.carrier_eff_en())
+            .field("carrier_en", &self.carrier_en())
+            .field("carrier_out_lv", &self.carrier_out_lv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_TX_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to start sending data on CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32c6/src/rmt/ch_tx_lim.rs b/esp32c6/src/rmt/ch_tx_lim.rs
index 8102018dc9..774de58471 100644
--- a/esp32c6/src/rmt/ch_tx_lim.rs
+++ b/esp32c6/src/rmt/ch_tx_lim.rs
@@ -46,28 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_TX_LIM")
-            .field("tx_lim", &format_args!("{}", self.tx_lim().bits()))
-            .field(
-                "tx_loop_num",
-                &format_args!("{}", self.tx_loop_num().bits()),
-            )
-            .field(
-                "tx_loop_cnt_en",
-                &format_args!("{}", self.tx_loop_cnt_en().bit()),
-            )
-            .field(
-                "loop_stop_en",
-                &format_args!("{}", self.loop_stop_en().bit()),
-            )
+            .field("tx_lim", &self.tx_lim())
+            .field("tx_loop_num", &self.tx_loop_num())
+            .field("tx_loop_cnt_en", &self.tx_loop_cnt_en())
+            .field("loop_stop_en", &self.loop_stop_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_TX_LIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can send out."]
     #[inline(always)]
diff --git a/esp32c6/src/rmt/ch_tx_status.rs b/esp32c6/src/rmt/ch_tx_status.rs
index d53bd94532..b7506c352a 100644
--- a/esp32c6/src/rmt/ch_tx_status.rs
+++ b/esp32c6/src/rmt/ch_tx_status.rs
@@ -55,37 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_TX_STATUS")
-            .field(
-                "mem_raddr_ex",
-                &format_args!("{}", self.mem_raddr_ex().bits()),
-            )
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field(
-                "apb_mem_waddr",
-                &format_args!("{}", self.apb_mem_waddr().bits()),
-            )
-            .field(
-                "apb_mem_rd_err",
-                &format_args!("{}", self.apb_mem_rd_err().bit()),
-            )
-            .field("mem_empty", &format_args!("{}", self.mem_empty().bit()))
-            .field(
-                "apb_mem_wr_err",
-                &format_args!("{}", self.apb_mem_wr_err().bit()),
-            )
-            .field(
-                "apb_mem_raddr",
-                &format_args!("{}", self.apb_mem_raddr().bits()),
-            )
+            .field("mem_raddr_ex", &self.mem_raddr_ex())
+            .field("state", &self.state())
+            .field("apb_mem_waddr", &self.apb_mem_waddr())
+            .field("apb_mem_rd_err", &self.apb_mem_rd_err())
+            .field("mem_empty", &self.mem_empty())
+            .field("apb_mem_wr_err", &self.apb_mem_wr_err())
+            .field("apb_mem_raddr", &self.apb_mem_raddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Channel %s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_TX_STATUS_SPEC;
 impl crate::RegisterSpec for CH_TX_STATUS_SPEC {
diff --git a/esp32c6/src/rmt/chcarrier_duty.rs b/esp32c6/src/rmt/chcarrier_duty.rs
index a3f3981bc9..ffed06d8c2 100644
--- a/esp32c6/src/rmt/chcarrier_duty.rs
+++ b/esp32c6/src/rmt/chcarrier_duty.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHCARRIER_DUTY")
-            .field(
-                "carrier_low",
-                &format_args!("{}", self.carrier_low().bits()),
-            )
-            .field(
-                "carrier_high",
-                &format_args!("{}", self.carrier_high().bits()),
-            )
+            .field("carrier_low", &self.carrier_low())
+            .field("carrier_high", &self.carrier_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHCARRIER_DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure carrier wave 's low level clock period for CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32c6/src/rmt/chdata.rs b/esp32c6/src/rmt/chdata.rs
index 8efd5cd2c1..5e6da546a9 100644
--- a/esp32c6/src/rmt/chdata.rs
+++ b/esp32c6/src/rmt/chdata.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHDATA")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Read and write data for channel %s via APB FIFO."]
     #[inline(always)]
diff --git a/esp32c6/src/rmt/date.rs b/esp32c6/src/rmt/date.rs
index ae2f20e76a..ce972b08ee 100644
--- a/esp32c6/src/rmt/date.rs
+++ b/esp32c6/src/rmt/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("rmt_date", &format_args!("{}", self.rmt_date().bits()))
+            .field("rmt_date", &self.rmt_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - This is the version register."]
     #[inline(always)]
diff --git a/esp32c6/src/rmt/int_ena.rs b/esp32c6/src/rmt/int_ena.rs
index 3e121d4288..971b09544d 100644
--- a/esp32c6/src/rmt/int_ena.rs
+++ b/esp32c6/src/rmt/int_ena.rs
@@ -211,41 +211,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_rx_end", &format_args!("{}", self.ch2_rx_end().bit()))
-            .field("ch3_rx_end", &format_args!("{}", self.ch3_rx_end().bit()))
-            .field("ch0_tx_err", &format_args!("{}", self.ch0_tx_err().bit()))
-            .field("ch1_tx_err", &format_args!("{}", self.ch1_tx_err().bit()))
-            .field("ch2_rx_err", &format_args!("{}", self.ch2_rx_err().bit()))
-            .field("ch3_rx_err", &format_args!("{}", self.ch3_rx_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_rx_thr_event",
-                &format_args!("{}", self.ch2_rx_thr_event().bit()),
-            )
-            .field(
-                "ch3_rx_thr_event",
-                &format_args!("{}", self.ch3_rx_thr_event().bit()),
-            )
-            .field("ch0_x_loop", &format_args!("{}", self.ch0_x_loop().bit()))
-            .field("ch1_x_loop", &format_args!("{}", self.ch1_x_loop().bit()))
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_rx_end", &self.ch2_rx_end())
+            .field("ch3_rx_end", &self.ch3_rx_end())
+            .field("ch0_tx_err", &self.ch0_tx_err())
+            .field("ch1_tx_err", &self.ch1_tx_err())
+            .field("ch2_rx_err", &self.ch2_rx_err())
+            .field("ch3_rx_err", &self.ch3_rx_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_rx_thr_event", &self.ch2_rx_thr_event())
+            .field("ch3_rx_thr_event", &self.ch3_rx_thr_event())
+            .field("ch0_x_loop", &self.ch0_x_loop())
+            .field("ch1_x_loop", &self.ch1_x_loop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for CH(0-1)_TX_END_INT."]
     #[doc = ""]
diff --git a/esp32c6/src/rmt/int_raw.rs b/esp32c6/src/rmt/int_raw.rs
index eb7363c2c9..f47e065dc2 100644
--- a/esp32c6/src/rmt/int_raw.rs
+++ b/esp32c6/src/rmt/int_raw.rs
@@ -211,41 +211,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_rx_end", &format_args!("{}", self.ch2_rx_end().bit()))
-            .field("ch3_rx_end", &format_args!("{}", self.ch3_rx_end().bit()))
-            .field("ch0_tx_err", &format_args!("{}", self.ch0_tx_err().bit()))
-            .field("ch1_tx_err", &format_args!("{}", self.ch1_tx_err().bit()))
-            .field("ch2_rx_err", &format_args!("{}", self.ch2_rx_err().bit()))
-            .field("ch3_rx_err", &format_args!("{}", self.ch3_rx_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_rx_thr_event",
-                &format_args!("{}", self.ch2_rx_thr_event().bit()),
-            )
-            .field(
-                "ch3_rx_thr_event",
-                &format_args!("{}", self.ch3_rx_thr_event().bit()),
-            )
-            .field("ch0_tx_loop", &format_args!("{}", self.ch0_tx_loop().bit()))
-            .field("ch1_tx_loop", &format_args!("{}", self.ch1_tx_loop().bit()))
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_rx_end", &self.ch2_rx_end())
+            .field("ch3_rx_end", &self.ch3_rx_end())
+            .field("ch0_tx_err", &self.ch0_tx_err())
+            .field("ch1_tx_err", &self.ch1_tx_err())
+            .field("ch2_rx_err", &self.ch2_rx_err())
+            .field("ch3_rx_err", &self.ch3_rx_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_rx_thr_event", &self.ch2_rx_thr_event())
+            .field("ch3_rx_thr_event", &self.ch3_rx_thr_event())
+            .field("ch0_tx_loop", &self.ch0_tx_loop())
+            .field("ch1_tx_loop", &self.ch1_tx_loop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt raw bit for CHANNEL(0-1). Triggered when transmission done."]
     #[doc = ""]
diff --git a/esp32c6/src/rmt/int_st.rs b/esp32c6/src/rmt/int_st.rs
index 44f452b415..a6bddc6f16 100644
--- a/esp32c6/src/rmt/int_st.rs
+++ b/esp32c6/src/rmt/int_st.rs
@@ -195,41 +195,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_rx_end", &format_args!("{}", self.ch2_rx_end().bit()))
-            .field("ch3_rx_end", &format_args!("{}", self.ch3_rx_end().bit()))
-            .field("ch0_tx_err", &format_args!("{}", self.ch0_tx_err().bit()))
-            .field("ch1_tx_err", &format_args!("{}", self.ch1_tx_err().bit()))
-            .field("ch2_rx_err", &format_args!("{}", self.ch2_rx_err().bit()))
-            .field("ch3_rx_err", &format_args!("{}", self.ch3_rx_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_rx_thr_event",
-                &format_args!("{}", self.ch2_rx_thr_event().bit()),
-            )
-            .field(
-                "ch3_rx_thr_event",
-                &format_args!("{}", self.ch3_rx_thr_event().bit()),
-            )
-            .field("ch0_x_loop", &format_args!("{}", self.ch0_x_loop().bit()))
-            .field("ch1_x_loop", &format_args!("{}", self.ch1_x_loop().bit()))
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_rx_end", &self.ch2_rx_end())
+            .field("ch3_rx_end", &self.ch3_rx_end())
+            .field("ch0_tx_err", &self.ch0_tx_err())
+            .field("ch1_tx_err", &self.ch1_tx_err())
+            .field("ch2_rx_err", &self.ch2_rx_err())
+            .field("ch3_rx_err", &self.ch3_rx_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_rx_thr_event", &self.ch2_rx_thr_event())
+            .field("ch3_rx_thr_event", &self.ch3_rx_thr_event())
+            .field("ch0_x_loop", &self.ch0_x_loop())
+            .field("ch1_x_loop", &self.ch1_x_loop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/rmt/sys_conf.rs b/esp32c6/src/rmt/sys_conf.rs
index 4efb4c0d04..c754deecee 100644
--- a/esp32c6/src/rmt/sys_conf.rs
+++ b/esp32c6/src/rmt/sys_conf.rs
@@ -98,40 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYS_CONF")
-            .field(
-                "apb_fifo_mask",
-                &format_args!("{}", self.apb_fifo_mask().bit()),
-            )
-            .field(
-                "mem_clk_force_on",
-                &format_args!("{}", self.mem_clk_force_on().bit()),
-            )
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bits()))
-            .field("sclk_active", &format_args!("{}", self.sclk_active().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("apb_fifo_mask", &self.apb_fifo_mask())
+            .field("mem_clk_force_on", &self.mem_clk_force_on())
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_active", &self.sclk_active())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'h1: access memory directly. 1'h0: access memory by FIFO."]
     #[inline(always)]
diff --git a/esp32c6/src/rmt/tx_sim.rs b/esp32c6/src/rmt/tx_sim.rs
index 784b1e1b34..821cb3607f 100644
--- a/esp32c6/src/rmt/tx_sim.rs
+++ b/esp32c6/src/rmt/tx_sim.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_SIM")
-            .field("ch0", &format_args!("{}", self.ch0().bit()))
-            .field("ch1", &format_args!("{}", self.ch1().bit()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("ch0", &self.ch0())
+            .field("ch1", &self.ch1())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_SIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels."]
     #[inline(always)]
diff --git a/esp32c6/src/rng/data.rs b/esp32c6/src/rng/data.rs
index 016046274d..4d812a63aa 100644
--- a/esp32c6/src/rng/data.rs
+++ b/esp32c6/src/rng/data.rs
@@ -6,12 +6,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Random number data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DATA_SPEC;
 impl crate::RegisterSpec for DATA_SPEC {
diff --git a/esp32c6/src/rsa/constant_time.rs b/esp32c6/src/rsa/constant_time.rs
index 1218a4629e..48a70f00c6 100644
--- a/esp32c6/src/rsa/constant_time.rs
+++ b/esp32c6/src/rsa/constant_time.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONSTANT_TIME")
-            .field(
-                "constant_time",
-                &format_args!("{}", self.constant_time().bit()),
-            )
+            .field("constant_time", &self.constant_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONSTANT_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut)."]
     #[inline(always)]
diff --git a/esp32c6/src/rsa/date.rs b/esp32c6/src/rsa/date.rs
index 257c27a30f..2104bd74f2 100644
--- a/esp32c6/src/rsa/date.rs
+++ b/esp32c6/src/rsa/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/rsa/int_ena.rs b/esp32c6/src/rsa/int_ena.rs
index ee0342e223..54ca8aba4a 100644
--- a/esp32c6/src/rsa/int_ena.rs
+++ b/esp32c6/src/rsa/int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("int_ena", &format_args!("{}", self.int_ena().bit()))
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default)."]
     #[inline(always)]
diff --git a/esp32c6/src/rsa/m_mem.rs b/esp32c6/src/rsa/m_mem.rs
index 88b032f702..c11e96b5b6 100644
--- a/esp32c6/src/rsa/m_mem.rs
+++ b/esp32c6/src/rsa/m_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct M_MEM_SPEC;
diff --git a/esp32c6/src/rsa/m_prime.rs b/esp32c6/src/rsa/m_prime.rs
index dd91ab2b36..7dced3affe 100644
--- a/esp32c6/src/rsa/m_prime.rs
+++ b/esp32c6/src/rsa/m_prime.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("M_PRIME")
-            .field("m_prime", &format_args!("{}", self.m_prime().bits()))
+            .field("m_prime", &self.m_prime())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_PRIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits stores m'"]
     #[inline(always)]
diff --git a/esp32c6/src/rsa/mode.rs b/esp32c6/src/rsa/mode.rs
index 9d2802c4ed..96daa5a1d3 100644
--- a/esp32c6/src/rsa/mode.rs
+++ b/esp32c6/src/rsa/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/rsa/query_clean.rs b/esp32c6/src/rsa/query_clean.rs
index cf0e470a9d..5aa0a3e027 100644
--- a/esp32c6/src/rsa/query_clean.rs
+++ b/esp32c6/src/rsa/query_clean.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_CLEAN")
-            .field("query_clean", &format_args!("{}", self.query_clean().bit()))
+            .field("query_clean", &self.query_clean())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_CLEAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RSA query clean register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_clean::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_CLEAN_SPEC;
 impl crate::RegisterSpec for QUERY_CLEAN_SPEC {
diff --git a/esp32c6/src/rsa/query_idle.rs b/esp32c6/src/rsa/query_idle.rs
index 77327c1e08..7daf803404 100644
--- a/esp32c6/src/rsa/query_idle.rs
+++ b/esp32c6/src/rsa/query_idle.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_IDLE")
-            .field("query_idle", &format_args!("{}", self.query_idle().bit()))
+            .field("query_idle", &self.query_idle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_IDLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RSA query idle register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_idle::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_IDLE_SPEC;
 impl crate::RegisterSpec for QUERY_IDLE_SPEC {
diff --git a/esp32c6/src/rsa/search_enable.rs b/esp32c6/src/rsa/search_enable.rs
index c6b830fb9d..06926facc7 100644
--- a/esp32c6/src/rsa/search_enable.rs
+++ b/esp32c6/src/rsa/search_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEARCH_ENABLE")
-            .field(
-                "search_enable",
-                &format_args!("{}", self.search_enable().bit()),
-            )
+            .field("search_enable", &self.search_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEARCH_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS."]
     #[inline(always)]
diff --git a/esp32c6/src/rsa/search_pos.rs b/esp32c6/src/rsa/search_pos.rs
index ba9c95915e..829c6fd704 100644
--- a/esp32c6/src/rsa/search_pos.rs
+++ b/esp32c6/src/rsa/search_pos.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEARCH_POS")
-            .field("search_pos", &format_args!("{}", self.search_pos().bits()))
+            .field("search_pos", &self.search_pos())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEARCH_POS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high."]
     #[inline(always)]
diff --git a/esp32c6/src/rsa/x_mem.rs b/esp32c6/src/rsa/x_mem.rs
index 1b86313bff..f13f895113 100644
--- a/esp32c6/src/rsa/x_mem.rs
+++ b/esp32c6/src/rsa/x_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<X_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores X\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`x_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`x_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct X_MEM_SPEC;
diff --git a/esp32c6/src/rsa/y_mem.rs b/esp32c6/src/rsa/y_mem.rs
index a4cf622a6e..608abec954 100644
--- a/esp32c6/src/rsa/y_mem.rs
+++ b/esp32c6/src/rsa/y_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Y_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores Y\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Y_MEM_SPEC;
diff --git a/esp32c6/src/rsa/z_mem.rs b/esp32c6/src/rsa/z_mem.rs
index b590e91783..0e9e81e6de 100644
--- a/esp32c6/src/rsa/z_mem.rs
+++ b/esp32c6/src/rsa/z_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Z_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Z_MEM_SPEC;
diff --git a/esp32c6/src/sha/busy.rs b/esp32c6/src/sha/busy.rs
index d586138364..ec4ecab687 100644
--- a/esp32c6/src/sha/busy.rs
+++ b/esp32c6/src/sha/busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUSY")
-            .field("state", &format_args!("{}", self.state().bit()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Busy register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUSY_SPEC;
 impl crate::RegisterSpec for BUSY_SPEC {
diff --git a/esp32c6/src/sha/date.rs b/esp32c6/src/sha/date.rs
index fea49bfb0c..9d86578ecf 100644
--- a/esp32c6/src/sha/date.rs
+++ b/esp32c6/src/sha/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/sha/dma_block_num.rs b/esp32c6/src/sha/dma_block_num.rs
index 235679368f..be8854254d 100644
--- a/esp32c6/src/sha/dma_block_num.rs
+++ b/esp32c6/src/sha/dma_block_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_BLOCK_NUM")
-            .field(
-                "dma_block_num",
-                &format_args!("{}", self.dma_block_num().bits()),
-            )
+            .field("dma_block_num", &self.dma_block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Dma-sha block number."]
     #[inline(always)]
diff --git a/esp32c6/src/sha/h_mem.rs b/esp32c6/src/sha/h_mem.rs
index e0865c92c6..13a6f95266 100644
--- a/esp32c6/src/sha/h_mem.rs
+++ b/esp32c6/src/sha/h_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Sha H memory which contains intermediate hash or finial hash.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct H_MEM_SPEC;
diff --git a/esp32c6/src/sha/irq_ena.rs b/esp32c6/src/sha/irq_ena.rs
index 8d61ac4aae..725a0f2641 100644
--- a/esp32c6/src/sha/irq_ena.rs
+++ b/esp32c6/src/sha/irq_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IRQ_ENA")
-            .field(
-                "interrupt_ena",
-                &format_args!("{}", self.interrupt_ena().bit()),
-            )
+            .field("interrupt_ena", &self.interrupt_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IRQ_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable."]
     #[inline(always)]
diff --git a/esp32c6/src/sha/m_mem.rs b/esp32c6/src/sha/m_mem.rs
index ccac5e7d71..7418659e89 100644
--- a/esp32c6/src/sha/m_mem.rs
+++ b/esp32c6/src/sha/m_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Sha M memory which contains message.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct M_MEM_SPEC;
diff --git a/esp32c6/src/sha/mode.rs b/esp32c6/src/sha/mode.rs
index 2b849314d6..ab2c8b2b20 100644
--- a/esp32c6/src/sha/mode.rs
+++ b/esp32c6/src/sha/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/sha/t_length.rs b/esp32c6/src/sha/t_length.rs
index 523a021805..845f709a89 100644
--- a/esp32c6/src/sha/t_length.rs
+++ b/esp32c6/src/sha/t_length.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T_LENGTH")
-            .field("t_length", &format_args!("{}", self.t_length().bits()))
+            .field("t_length", &self.t_length())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T_LENGTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Sha t_length (used if and only if mode == SHA_512/t)."]
     #[inline(always)]
diff --git a/esp32c6/src/sha/t_string.rs b/esp32c6/src/sha/t_string.rs
index db1093db4b..c533a0e0d5 100644
--- a/esp32c6/src/sha/t_string.rs
+++ b/esp32c6/src/sha/t_string.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T_STRING")
-            .field("t_string", &format_args!("{}", self.t_string().bits()))
+            .field("t_string", &self.t_string())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T_STRING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Sha t_string (used if and only if mode == SHA_512/t)."]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/check_sum0.rs b/esp32c6/src/slchost/check_sum0.rs
index 69ae84cfc9..2170414193 100644
--- a/esp32c6/src/slchost/check_sum0.rs
+++ b/esp32c6/src/slchost/check_sum0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHECK_SUM0")
-            .field(
-                "slchost_check_sum0",
-                &format_args!("{}", self.slchost_check_sum0().bits()),
-            )
+            .field("slchost_check_sum0", &self.slchost_check_sum0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHECK_SUM0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`check_sum0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CHECK_SUM0_SPEC;
 impl crate::RegisterSpec for CHECK_SUM0_SPEC {
diff --git a/esp32c6/src/slchost/check_sum1.rs b/esp32c6/src/slchost/check_sum1.rs
index e444dfa3f4..d6d251ebb7 100644
--- a/esp32c6/src/slchost/check_sum1.rs
+++ b/esp32c6/src/slchost/check_sum1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHECK_SUM1")
-            .field(
-                "slchost_check_sum1",
-                &format_args!("{}", self.slchost_check_sum1().bits()),
-            )
+            .field("slchost_check_sum1", &self.slchost_check_sum1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHECK_SUM1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`check_sum1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CHECK_SUM1_SPEC;
 impl crate::RegisterSpec for CHECK_SUM1_SPEC {
diff --git a/esp32c6/src/slchost/conf.rs b/esp32c6/src/slchost/conf.rs
index 18cc3febed..087a723b41 100644
--- a/esp32c6/src/slchost/conf.rs
+++ b/esp32c6/src/slchost/conf.rs
@@ -80,41 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("frc_sdio11", &format_args!("{}", self.frc_sdio11().bits()))
-            .field("frc_sdio20", &format_args!("{}", self.frc_sdio20().bits()))
-            .field(
-                "frc_neg_samp",
-                &format_args!("{}", self.frc_neg_samp().bits()),
-            )
-            .field(
-                "frc_pos_samp",
-                &format_args!("{}", self.frc_pos_samp().bits()),
-            )
-            .field(
-                "frc_quick_in",
-                &format_args!("{}", self.frc_quick_in().bits()),
-            )
-            .field(
-                "sdio20_int_delay",
-                &format_args!("{}", self.sdio20_int_delay().bit()),
-            )
-            .field(
-                "sdio_pad_pullup",
-                &format_args!("{}", self.sdio_pad_pullup().bit()),
-            )
-            .field(
-                "hspeed_con_en",
-                &format_args!("{}", self.hspeed_con_en().bit()),
-            )
+            .field("frc_sdio11", &self.frc_sdio11())
+            .field("frc_sdio20", &self.frc_sdio20())
+            .field("frc_neg_samp", &self.frc_neg_samp())
+            .field("frc_pos_samp", &self.frc_pos_samp())
+            .field("frc_quick_in", &self.frc_quick_in())
+            .field("sdio20_int_delay", &self.sdio20_int_delay())
+            .field("sdio_pad_pullup", &self.sdio_pad_pullup())
+            .field("hspeed_con_en", &self.hspeed_con_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w0.rs b/esp32c6/src/slchost/conf_w0.rs
index ff08c67182..e18f765ff5 100644
--- a/esp32c6/src/slchost/conf_w0.rs
+++ b/esp32c6/src/slchost/conf_w0.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W0")
-            .field(
-                "slchost_conf0",
-                &format_args!("{}", self.slchost_conf0().bits()),
-            )
-            .field(
-                "slchost_conf1",
-                &format_args!("{}", self.slchost_conf1().bits()),
-            )
-            .field(
-                "slchost_conf2",
-                &format_args!("{}", self.slchost_conf2().bits()),
-            )
-            .field(
-                "slchost_conf3",
-                &format_args!("{}", self.slchost_conf3().bits()),
-            )
+            .field("slchost_conf0", &self.slchost_conf0())
+            .field("slchost_conf1", &self.slchost_conf1())
+            .field("slchost_conf2", &self.slchost_conf2())
+            .field("slchost_conf3", &self.slchost_conf3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w1.rs b/esp32c6/src/slchost/conf_w1.rs
index 2be9641f7f..94834b9e34 100644
--- a/esp32c6/src/slchost/conf_w1.rs
+++ b/esp32c6/src/slchost/conf_w1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W1")
-            .field(
-                "slchost_conf4",
-                &format_args!("{}", self.slchost_conf4().bits()),
-            )
-            .field(
-                "slchost_conf5",
-                &format_args!("{}", self.slchost_conf5().bits()),
-            )
-            .field(
-                "slchost_conf6",
-                &format_args!("{}", self.slchost_conf6().bits()),
-            )
-            .field(
-                "slchost_conf7",
-                &format_args!("{}", self.slchost_conf7().bits()),
-            )
+            .field("slchost_conf4", &self.slchost_conf4())
+            .field("slchost_conf5", &self.slchost_conf5())
+            .field("slchost_conf6", &self.slchost_conf6())
+            .field("slchost_conf7", &self.slchost_conf7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w10.rs b/esp32c6/src/slchost/conf_w10.rs
index 539cb32781..b2034bab88 100644
--- a/esp32c6/src/slchost/conf_w10.rs
+++ b/esp32c6/src/slchost/conf_w10.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W10")
-            .field(
-                "slchost_conf40",
-                &format_args!("{}", self.slchost_conf40().bits()),
-            )
-            .field(
-                "slchost_conf41",
-                &format_args!("{}", self.slchost_conf41().bits()),
-            )
-            .field(
-                "slchost_conf42",
-                &format_args!("{}", self.slchost_conf42().bits()),
-            )
-            .field(
-                "slchost_conf43",
-                &format_args!("{}", self.slchost_conf43().bits()),
-            )
+            .field("slchost_conf40", &self.slchost_conf40())
+            .field("slchost_conf41", &self.slchost_conf41())
+            .field("slchost_conf42", &self.slchost_conf42())
+            .field("slchost_conf43", &self.slchost_conf43())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w11.rs b/esp32c6/src/slchost/conf_w11.rs
index 7753675991..0b2e4fc25c 100644
--- a/esp32c6/src/slchost/conf_w11.rs
+++ b/esp32c6/src/slchost/conf_w11.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W11")
-            .field(
-                "slchost_conf44",
-                &format_args!("{}", self.slchost_conf44().bits()),
-            )
-            .field(
-                "slchost_conf45",
-                &format_args!("{}", self.slchost_conf45().bits()),
-            )
-            .field(
-                "slchost_conf46",
-                &format_args!("{}", self.slchost_conf46().bits()),
-            )
-            .field(
-                "slchost_conf47",
-                &format_args!("{}", self.slchost_conf47().bits()),
-            )
+            .field("slchost_conf44", &self.slchost_conf44())
+            .field("slchost_conf45", &self.slchost_conf45())
+            .field("slchost_conf46", &self.slchost_conf46())
+            .field("slchost_conf47", &self.slchost_conf47())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w12.rs b/esp32c6/src/slchost/conf_w12.rs
index 1ff47a6d5c..6abf486b43 100644
--- a/esp32c6/src/slchost/conf_w12.rs
+++ b/esp32c6/src/slchost/conf_w12.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W12")
-            .field(
-                "slchost_conf48",
-                &format_args!("{}", self.slchost_conf48().bits()),
-            )
-            .field(
-                "slchost_conf49",
-                &format_args!("{}", self.slchost_conf49().bits()),
-            )
-            .field(
-                "slchost_conf50",
-                &format_args!("{}", self.slchost_conf50().bits()),
-            )
-            .field(
-                "slchost_conf51",
-                &format_args!("{}", self.slchost_conf51().bits()),
-            )
+            .field("slchost_conf48", &self.slchost_conf48())
+            .field("slchost_conf49", &self.slchost_conf49())
+            .field("slchost_conf50", &self.slchost_conf50())
+            .field("slchost_conf51", &self.slchost_conf51())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w13.rs b/esp32c6/src/slchost/conf_w13.rs
index f4f7fd29fa..bd6b4827be 100644
--- a/esp32c6/src/slchost/conf_w13.rs
+++ b/esp32c6/src/slchost/conf_w13.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W13")
-            .field(
-                "slchost_conf52",
-                &format_args!("{}", self.slchost_conf52().bits()),
-            )
-            .field(
-                "slchost_conf53",
-                &format_args!("{}", self.slchost_conf53().bits()),
-            )
-            .field(
-                "slchost_conf54",
-                &format_args!("{}", self.slchost_conf54().bits()),
-            )
-            .field(
-                "slchost_conf55",
-                &format_args!("{}", self.slchost_conf55().bits()),
-            )
+            .field("slchost_conf52", &self.slchost_conf52())
+            .field("slchost_conf53", &self.slchost_conf53())
+            .field("slchost_conf54", &self.slchost_conf54())
+            .field("slchost_conf55", &self.slchost_conf55())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w14.rs b/esp32c6/src/slchost/conf_w14.rs
index 9598e930d9..1984010a69 100644
--- a/esp32c6/src/slchost/conf_w14.rs
+++ b/esp32c6/src/slchost/conf_w14.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W14")
-            .field(
-                "slchost_conf56",
-                &format_args!("{}", self.slchost_conf56().bits()),
-            )
-            .field(
-                "slchost_conf57",
-                &format_args!("{}", self.slchost_conf57().bits()),
-            )
-            .field(
-                "slchost_conf58",
-                &format_args!("{}", self.slchost_conf58().bits()),
-            )
-            .field(
-                "slchost_conf59",
-                &format_args!("{}", self.slchost_conf59().bits()),
-            )
+            .field("slchost_conf56", &self.slchost_conf56())
+            .field("slchost_conf57", &self.slchost_conf57())
+            .field("slchost_conf58", &self.slchost_conf58())
+            .field("slchost_conf59", &self.slchost_conf59())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w15.rs b/esp32c6/src/slchost/conf_w15.rs
index 86e322e28f..4e936da240 100644
--- a/esp32c6/src/slchost/conf_w15.rs
+++ b/esp32c6/src/slchost/conf_w15.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W15")
-            .field(
-                "slchost_conf60",
-                &format_args!("{}", self.slchost_conf60().bits()),
-            )
-            .field(
-                "slchost_conf61",
-                &format_args!("{}", self.slchost_conf61().bits()),
-            )
-            .field(
-                "slchost_conf62",
-                &format_args!("{}", self.slchost_conf62().bits()),
-            )
-            .field(
-                "slchost_conf63",
-                &format_args!("{}", self.slchost_conf63().bits()),
-            )
+            .field("slchost_conf60", &self.slchost_conf60())
+            .field("slchost_conf61", &self.slchost_conf61())
+            .field("slchost_conf62", &self.slchost_conf62())
+            .field("slchost_conf63", &self.slchost_conf63())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w2.rs b/esp32c6/src/slchost/conf_w2.rs
index b93e3e7b2f..d0b42db567 100644
--- a/esp32c6/src/slchost/conf_w2.rs
+++ b/esp32c6/src/slchost/conf_w2.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W2")
-            .field(
-                "slchost_conf8",
-                &format_args!("{}", self.slchost_conf8().bits()),
-            )
-            .field(
-                "slchost_conf9",
-                &format_args!("{}", self.slchost_conf9().bits()),
-            )
-            .field(
-                "slchost_conf10",
-                &format_args!("{}", self.slchost_conf10().bits()),
-            )
-            .field(
-                "slchost_conf11",
-                &format_args!("{}", self.slchost_conf11().bits()),
-            )
+            .field("slchost_conf8", &self.slchost_conf8())
+            .field("slchost_conf9", &self.slchost_conf9())
+            .field("slchost_conf10", &self.slchost_conf10())
+            .field("slchost_conf11", &self.slchost_conf11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w3.rs b/esp32c6/src/slchost/conf_w3.rs
index 5effb8c695..7b58925989 100644
--- a/esp32c6/src/slchost/conf_w3.rs
+++ b/esp32c6/src/slchost/conf_w3.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W3")
-            .field(
-                "slchost_conf12",
-                &format_args!("{}", self.slchost_conf12().bits()),
-            )
-            .field(
-                "slchost_conf13",
-                &format_args!("{}", self.slchost_conf13().bits()),
-            )
-            .field(
-                "slchost_conf14",
-                &format_args!("{}", self.slchost_conf14().bits()),
-            )
-            .field(
-                "slchost_conf15",
-                &format_args!("{}", self.slchost_conf15().bits()),
-            )
+            .field("slchost_conf12", &self.slchost_conf12())
+            .field("slchost_conf13", &self.slchost_conf13())
+            .field("slchost_conf14", &self.slchost_conf14())
+            .field("slchost_conf15", &self.slchost_conf15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w4.rs b/esp32c6/src/slchost/conf_w4.rs
index 6899639954..d4aaea88ba 100644
--- a/esp32c6/src/slchost/conf_w4.rs
+++ b/esp32c6/src/slchost/conf_w4.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W4")
-            .field(
-                "slchost_conf16",
-                &format_args!("{}", self.slchost_conf16().bits()),
-            )
-            .field(
-                "slchost_conf17",
-                &format_args!("{}", self.slchost_conf17().bits()),
-            )
-            .field(
-                "slchost_conf18",
-                &format_args!("{}", self.slchost_conf18().bits()),
-            )
-            .field(
-                "slchost_conf19",
-                &format_args!("{}", self.slchost_conf19().bits()),
-            )
+            .field("slchost_conf16", &self.slchost_conf16())
+            .field("slchost_conf17", &self.slchost_conf17())
+            .field("slchost_conf18", &self.slchost_conf18())
+            .field("slchost_conf19", &self.slchost_conf19())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w5.rs b/esp32c6/src/slchost/conf_w5.rs
index 8dcee6641c..8719d3f02c 100644
--- a/esp32c6/src/slchost/conf_w5.rs
+++ b/esp32c6/src/slchost/conf_w5.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W5")
-            .field(
-                "slchost_conf20",
-                &format_args!("{}", self.slchost_conf20().bits()),
-            )
-            .field(
-                "slchost_conf21",
-                &format_args!("{}", self.slchost_conf21().bits()),
-            )
-            .field(
-                "slchost_conf22",
-                &format_args!("{}", self.slchost_conf22().bits()),
-            )
-            .field(
-                "slchost_conf23",
-                &format_args!("{}", self.slchost_conf23().bits()),
-            )
+            .field("slchost_conf20", &self.slchost_conf20())
+            .field("slchost_conf21", &self.slchost_conf21())
+            .field("slchost_conf22", &self.slchost_conf22())
+            .field("slchost_conf23", &self.slchost_conf23())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w6.rs b/esp32c6/src/slchost/conf_w6.rs
index 4657bfa1df..356594f095 100644
--- a/esp32c6/src/slchost/conf_w6.rs
+++ b/esp32c6/src/slchost/conf_w6.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W6")
-            .field(
-                "slchost_conf24",
-                &format_args!("{}", self.slchost_conf24().bits()),
-            )
-            .field(
-                "slchost_conf25",
-                &format_args!("{}", self.slchost_conf25().bits()),
-            )
-            .field(
-                "slchost_conf26",
-                &format_args!("{}", self.slchost_conf26().bits()),
-            )
-            .field(
-                "slchost_conf27",
-                &format_args!("{}", self.slchost_conf27().bits()),
-            )
+            .field("slchost_conf24", &self.slchost_conf24())
+            .field("slchost_conf25", &self.slchost_conf25())
+            .field("slchost_conf26", &self.slchost_conf26())
+            .field("slchost_conf27", &self.slchost_conf27())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w7.rs b/esp32c6/src/slchost/conf_w7.rs
index b5df4ef513..b12ddfa291 100644
--- a/esp32c6/src/slchost/conf_w7.rs
+++ b/esp32c6/src/slchost/conf_w7.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W7")
-            .field(
-                "slchost_conf28",
-                &format_args!("{}", self.slchost_conf28().bits()),
-            )
-            .field(
-                "slchost_conf29",
-                &format_args!("{}", self.slchost_conf29().bits()),
-            )
-            .field(
-                "slchost_conf30",
-                &format_args!("{}", self.slchost_conf30().bits()),
-            )
-            .field(
-                "slchost_conf31",
-                &format_args!("{}", self.slchost_conf31().bits()),
-            )
+            .field("slchost_conf28", &self.slchost_conf28())
+            .field("slchost_conf29", &self.slchost_conf29())
+            .field("slchost_conf30", &self.slchost_conf30())
+            .field("slchost_conf31", &self.slchost_conf31())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w8.rs b/esp32c6/src/slchost/conf_w8.rs
index dc0a239b12..df055b8df3 100644
--- a/esp32c6/src/slchost/conf_w8.rs
+++ b/esp32c6/src/slchost/conf_w8.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W8")
-            .field(
-                "slchost_conf32",
-                &format_args!("{}", self.slchost_conf32().bits()),
-            )
-            .field(
-                "slchost_conf33",
-                &format_args!("{}", self.slchost_conf33().bits()),
-            )
-            .field(
-                "slchost_conf34",
-                &format_args!("{}", self.slchost_conf34().bits()),
-            )
-            .field(
-                "slchost_conf35",
-                &format_args!("{}", self.slchost_conf35().bits()),
-            )
+            .field("slchost_conf32", &self.slchost_conf32())
+            .field("slchost_conf33", &self.slchost_conf33())
+            .field("slchost_conf34", &self.slchost_conf34())
+            .field("slchost_conf35", &self.slchost_conf35())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/conf_w9.rs b/esp32c6/src/slchost/conf_w9.rs
index 029ef84bad..6288088023 100644
--- a/esp32c6/src/slchost/conf_w9.rs
+++ b/esp32c6/src/slchost/conf_w9.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_W9")
-            .field(
-                "slchost_conf36",
-                &format_args!("{}", self.slchost_conf36().bits()),
-            )
-            .field(
-                "slchost_conf37",
-                &format_args!("{}", self.slchost_conf37().bits()),
-            )
-            .field(
-                "slchost_conf38",
-                &format_args!("{}", self.slchost_conf38().bits()),
-            )
-            .field(
-                "slchost_conf39",
-                &format_args!("{}", self.slchost_conf39().bits()),
-            )
+            .field("slchost_conf36", &self.slchost_conf36())
+            .field("slchost_conf37", &self.slchost_conf37())
+            .field("slchost_conf38", &self.slchost_conf38())
+            .field("slchost_conf39", &self.slchost_conf39())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/func2_0.rs b/esp32c6/src/slchost/func2_0.rs
index 7106326904..a5acdd6af4 100644
--- a/esp32c6/src/slchost/func2_0.rs
+++ b/esp32c6/src/slchost/func2_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC2_0")
-            .field(
-                "slc_func2_int",
-                &format_args!("{}", self.slc_func2_int().bit()),
-            )
+            .field("slc_func2_int", &self.slc_func2_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC2_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/func2_1.rs b/esp32c6/src/slchost/func2_1.rs
index c884ee7d4b..cb6908c356 100644
--- a/esp32c6/src/slchost/func2_1.rs
+++ b/esp32c6/src/slchost/func2_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC2_1")
-            .field(
-                "slc_func2_int_en",
-                &format_args!("{}", self.slc_func2_int_en().bit()),
-            )
+            .field("slc_func2_int_en", &self.slc_func2_int_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC2_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/func2_2.rs b/esp32c6/src/slchost/func2_2.rs
index b4500f9815..f0504e97b7 100644
--- a/esp32c6/src/slchost/func2_2.rs
+++ b/esp32c6/src/slchost/func2_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC2_2")
-            .field(
-                "slc_func1_mdstat",
-                &format_args!("{}", self.slc_func1_mdstat().bit()),
-            )
+            .field("slc_func1_mdstat", &self.slc_func1_mdstat())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC2_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/gpio_in0.rs b/esp32c6/src/slchost/gpio_in0.rs
index d3077fdc2a..aa788012af 100644
--- a/esp32c6/src/slchost/gpio_in0.rs
+++ b/esp32c6/src/slchost/gpio_in0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_IN0")
-            .field(
-                "gpio_sdio_in0",
-                &format_args!("{}", self.gpio_sdio_in0().bits()),
-            )
+            .field("gpio_sdio_in0", &self.gpio_sdio_in0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_IN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_in0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_IN0_SPEC;
 impl crate::RegisterSpec for GPIO_IN0_SPEC {
diff --git a/esp32c6/src/slchost/gpio_in1.rs b/esp32c6/src/slchost/gpio_in1.rs
index e25598af54..5eab078daf 100644
--- a/esp32c6/src/slchost/gpio_in1.rs
+++ b/esp32c6/src/slchost/gpio_in1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_IN1")
-            .field(
-                "gpio_sdio_in1",
-                &format_args!("{}", self.gpio_sdio_in1().bits()),
-            )
+            .field("gpio_sdio_in1", &self.gpio_sdio_in1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_IN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_in1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_IN1_SPEC;
 impl crate::RegisterSpec for GPIO_IN1_SPEC {
diff --git a/esp32c6/src/slchost/gpio_status0.rs b/esp32c6/src/slchost/gpio_status0.rs
index 12f4786b30..90399bdf90 100644
--- a/esp32c6/src/slchost/gpio_status0.rs
+++ b/esp32c6/src/slchost/gpio_status0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_STATUS0")
-            .field(
-                "gpio_sdio_int0",
-                &format_args!("{}", self.gpio_sdio_int0().bits()),
-            )
+            .field("gpio_sdio_int0", &self.gpio_sdio_int0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_STATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_status0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_STATUS0_SPEC;
 impl crate::RegisterSpec for GPIO_STATUS0_SPEC {
diff --git a/esp32c6/src/slchost/gpio_status1.rs b/esp32c6/src/slchost/gpio_status1.rs
index 2634fd3649..5e6b160738 100644
--- a/esp32c6/src/slchost/gpio_status1.rs
+++ b/esp32c6/src/slchost/gpio_status1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_STATUS1")
-            .field(
-                "gpio_sdio_int1",
-                &format_args!("{}", self.gpio_sdio_int1().bits()),
-            )
+            .field("gpio_sdio_int1", &self.gpio_sdio_int1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpio_status1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_STATUS1_SPEC;
 impl crate::RegisterSpec for GPIO_STATUS1_SPEC {
diff --git a/esp32c6/src/slchost/inf_st.rs b/esp32c6/src/slchost/inf_st.rs
index 9f0664616f..f776969dc2 100644
--- a/esp32c6/src/slchost/inf_st.rs
+++ b/esp32c6/src/slchost/inf_st.rs
@@ -65,31 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF_ST")
-            .field(
-                "sdio20_mode",
-                &format_args!("{}", self.sdio20_mode().bits()),
-            )
-            .field(
-                "sdio_neg_samp",
-                &format_args!("{}", self.sdio_neg_samp().bits()),
-            )
-            .field(
-                "sdio_quick_in",
-                &format_args!("{}", self.sdio_quick_in().bits()),
-            )
-            .field("dll_on_sw", &format_args!("{}", self.dll_on_sw().bit()))
-            .field("dll_on", &format_args!("{}", self.dll_on().bit()))
-            .field("clk_mode_sw", &format_args!("{}", self.clk_mode_sw().bit()))
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
+            .field("sdio20_mode", &self.sdio20_mode())
+            .field("sdio_neg_samp", &self.sdio_neg_samp())
+            .field("sdio_quick_in", &self.sdio_quick_in())
+            .field("dll_on_sw", &self.dll_on_sw())
+            .field("dll_on", &self.dll_on())
+            .field("clk_mode_sw", &self.clk_mode_sw())
+            .field("clk_mode", &self.clk_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 15 - dll is controlled by software"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/pkt_len.rs b/esp32c6/src/slchost/pkt_len.rs
index 9bd275d274..853b60da58 100644
--- a/esp32c6/src/slchost/pkt_len.rs
+++ b/esp32c6/src/slchost/pkt_len.rs
@@ -20,23 +20,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PKT_LEN")
-            .field(
-                "hostslchost_slc0_len",
-                &format_args!("{}", self.hostslchost_slc0_len().bits()),
-            )
+            .field("hostslchost_slc0_len", &self.hostslchost_slc0_len())
             .field(
                 "hostslchost_slc0_len_check",
-                &format_args!("{}", self.hostslchost_slc0_len_check().bits()),
+                &self.hostslchost_slc0_len_check(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PKT_LEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pkt_len::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PKT_LEN_SPEC;
 impl crate::RegisterSpec for PKT_LEN_SPEC {
diff --git a/esp32c6/src/slchost/pkt_len0.rs b/esp32c6/src/slchost/pkt_len0.rs
index 6d0ef3d50b..a3d3ea5159 100644
--- a/esp32c6/src/slchost/pkt_len0.rs
+++ b/esp32c6/src/slchost/pkt_len0.rs
@@ -20,23 +20,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PKT_LEN0")
-            .field(
-                "hostslchost_slc0_len0",
-                &format_args!("{}", self.hostslchost_slc0_len0().bits()),
-            )
+            .field("hostslchost_slc0_len0", &self.hostslchost_slc0_len0())
             .field(
                 "hostslchost_slc0_len0_check",
-                &format_args!("{}", self.hostslchost_slc0_len0_check().bits()),
+                &self.hostslchost_slc0_len0_check(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PKT_LEN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pkt_len0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PKT_LEN0_SPEC;
 impl crate::RegisterSpec for PKT_LEN0_SPEC {
diff --git a/esp32c6/src/slchost/pkt_len1.rs b/esp32c6/src/slchost/pkt_len1.rs
index 8c9a8b9a8f..84c90ce985 100644
--- a/esp32c6/src/slchost/pkt_len1.rs
+++ b/esp32c6/src/slchost/pkt_len1.rs
@@ -20,23 +20,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PKT_LEN1")
-            .field(
-                "hostslchost_slc0_len1",
-                &format_args!("{}", self.hostslchost_slc0_len1().bits()),
-            )
+            .field("hostslchost_slc0_len1", &self.hostslchost_slc0_len1())
             .field(
                 "hostslchost_slc0_len1_check",
-                &format_args!("{}", self.hostslchost_slc0_len1_check().bits()),
+                &self.hostslchost_slc0_len1_check(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PKT_LEN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pkt_len1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PKT_LEN1_SPEC;
 impl crate::RegisterSpec for PKT_LEN1_SPEC {
diff --git a/esp32c6/src/slchost/pkt_len2.rs b/esp32c6/src/slchost/pkt_len2.rs
index 7014ff2c28..d4575b5593 100644
--- a/esp32c6/src/slchost/pkt_len2.rs
+++ b/esp32c6/src/slchost/pkt_len2.rs
@@ -20,23 +20,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PKT_LEN2")
-            .field(
-                "hostslchost_slc0_len2",
-                &format_args!("{}", self.hostslchost_slc0_len2().bits()),
-            )
+            .field("hostslchost_slc0_len2", &self.hostslchost_slc0_len2())
             .field(
                 "hostslchost_slc0_len2_check",
-                &format_args!("{}", self.hostslchost_slc0_len2_check().bits()),
+                &self.hostslchost_slc0_len2_check(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PKT_LEN2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pkt_len2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PKT_LEN2_SPEC;
 impl crate::RegisterSpec for PKT_LEN2_SPEC {
diff --git a/esp32c6/src/slchost/rdclr0.rs b/esp32c6/src/slchost/rdclr0.rs
index 1a40109241..c8de5c757c 100644
--- a/esp32c6/src/slchost/rdclr0.rs
+++ b/esp32c6/src/slchost/rdclr0.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("RDCLR0")
             .field(
                 "slchost_slc0_bit7_clraddr",
-                &format_args!("{}", self.slchost_slc0_bit7_clraddr().bits()),
+                &self.slchost_slc0_bit7_clraddr(),
             )
             .field(
                 "slchost_slc0_bit6_clraddr",
-                &format_args!("{}", self.slchost_slc0_bit6_clraddr().bits()),
+                &self.slchost_slc0_bit6_clraddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDCLR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/rdclr1.rs b/esp32c6/src/slchost/rdclr1.rs
index 8f385f280a..bc6c8ce569 100644
--- a/esp32c6/src/slchost/rdclr1.rs
+++ b/esp32c6/src/slchost/rdclr1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("RDCLR1")
             .field(
                 "slchost_slc1_bit7_clraddr",
-                &format_args!("{}", self.slchost_slc1_bit7_clraddr().bits()),
+                &self.slchost_slc1_bit7_clraddr(),
             )
             .field(
                 "slchost_slc1_bit6_clraddr",
-                &format_args!("{}", self.slchost_slc1_bit6_clraddr().bits()),
+                &self.slchost_slc1_bit6_clraddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDCLR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc0_host_pf.rs b/esp32c6/src/slchost/slc0_host_pf.rs
index 28bf87d7a5..9fdf2ec212 100644
--- a/esp32c6/src/slchost/slc0_host_pf.rs
+++ b/esp32c6/src/slchost/slc0_host_pf.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC0_HOST_PF")
-            .field(
-                "slc0_pf_data",
-                &format_args!("{}", self.slc0_pf_data().bits()),
-            )
+            .field("slc0_pf_data", &self.slc0_pf_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC0_HOST_PF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc0_host_pf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLC0_HOST_PF_SPEC;
 impl crate::RegisterSpec for SLC0_HOST_PF_SPEC {
diff --git a/esp32c6/src/slchost/slc0host_func1_int_ena.rs b/esp32c6/src/slchost/slc0host_func1_int_ena.rs
index bb3fc982e5..22eb85685c 100644
--- a/esp32c6/src/slchost/slc0host_func1_int_ena.rs
+++ b/esp32c6/src/slchost/slc0host_func1_int_ena.rs
@@ -244,117 +244,102 @@ impl core::fmt::Debug for R {
         f.debug_struct("SLC0HOST_FUNC1_INT_ENA")
             .field(
                 "fn1_slc0_tohost_bit0_int_ena",
-                &format_args!("{}", self.fn1_slc0_tohost_bit0_int_ena().bit()),
+                &self.fn1_slc0_tohost_bit0_int_ena(),
             )
             .field(
                 "fn1_slc0_tohost_bit1_int_ena",
-                &format_args!("{}", self.fn1_slc0_tohost_bit1_int_ena().bit()),
+                &self.fn1_slc0_tohost_bit1_int_ena(),
             )
             .field(
                 "fn1_slc0_tohost_bit2_int_ena",
-                &format_args!("{}", self.fn1_slc0_tohost_bit2_int_ena().bit()),
+                &self.fn1_slc0_tohost_bit2_int_ena(),
             )
             .field(
                 "fn1_slc0_tohost_bit3_int_ena",
-                &format_args!("{}", self.fn1_slc0_tohost_bit3_int_ena().bit()),
+                &self.fn1_slc0_tohost_bit3_int_ena(),
             )
             .field(
                 "fn1_slc0_tohost_bit4_int_ena",
-                &format_args!("{}", self.fn1_slc0_tohost_bit4_int_ena().bit()),
+                &self.fn1_slc0_tohost_bit4_int_ena(),
             )
             .field(
                 "fn1_slc0_tohost_bit5_int_ena",
-                &format_args!("{}", self.fn1_slc0_tohost_bit5_int_ena().bit()),
+                &self.fn1_slc0_tohost_bit5_int_ena(),
             )
             .field(
                 "fn1_slc0_tohost_bit6_int_ena",
-                &format_args!("{}", self.fn1_slc0_tohost_bit6_int_ena().bit()),
+                &self.fn1_slc0_tohost_bit6_int_ena(),
             )
             .field(
                 "fn1_slc0_tohost_bit7_int_ena",
-                &format_args!("{}", self.fn1_slc0_tohost_bit7_int_ena().bit()),
+                &self.fn1_slc0_tohost_bit7_int_ena(),
             )
             .field(
                 "fn1_slc0_token0_1to0_int_ena",
-                &format_args!("{}", self.fn1_slc0_token0_1to0_int_ena().bit()),
+                &self.fn1_slc0_token0_1to0_int_ena(),
             )
             .field(
                 "fn1_slc0_token1_1to0_int_ena",
-                &format_args!("{}", self.fn1_slc0_token1_1to0_int_ena().bit()),
+                &self.fn1_slc0_token1_1to0_int_ena(),
             )
             .field(
                 "fn1_slc0_token0_0to1_int_ena",
-                &format_args!("{}", self.fn1_slc0_token0_0to1_int_ena().bit()),
+                &self.fn1_slc0_token0_0to1_int_ena(),
             )
             .field(
                 "fn1_slc0_token1_0to1_int_ena",
-                &format_args!("{}", self.fn1_slc0_token1_0to1_int_ena().bit()),
+                &self.fn1_slc0_token1_0to1_int_ena(),
             )
             .field(
                 "fn1_slc0host_rx_sof_int_ena",
-                &format_args!("{}", self.fn1_slc0host_rx_sof_int_ena().bit()),
+                &self.fn1_slc0host_rx_sof_int_ena(),
             )
             .field(
                 "fn1_slc0host_rx_eof_int_ena",
-                &format_args!("{}", self.fn1_slc0host_rx_eof_int_ena().bit()),
+                &self.fn1_slc0host_rx_eof_int_ena(),
             )
             .field(
                 "fn1_slc0host_rx_start_int_ena",
-                &format_args!("{}", self.fn1_slc0host_rx_start_int_ena().bit()),
+                &self.fn1_slc0host_rx_start_int_ena(),
             )
             .field(
                 "fn1_slc0host_tx_start_int_ena",
-                &format_args!("{}", self.fn1_slc0host_tx_start_int_ena().bit()),
-            )
-            .field(
-                "fn1_slc0_rx_udf_int_ena",
-                &format_args!("{}", self.fn1_slc0_rx_udf_int_ena().bit()),
-            )
-            .field(
-                "fn1_slc0_tx_ovf_int_ena",
-                &format_args!("{}", self.fn1_slc0_tx_ovf_int_ena().bit()),
+                &self.fn1_slc0host_tx_start_int_ena(),
             )
+            .field("fn1_slc0_rx_udf_int_ena", &self.fn1_slc0_rx_udf_int_ena())
+            .field("fn1_slc0_tx_ovf_int_ena", &self.fn1_slc0_tx_ovf_int_ena())
             .field(
                 "fn1_slc0_rx_pf_valid_int_ena",
-                &format_args!("{}", self.fn1_slc0_rx_pf_valid_int_ena().bit()),
+                &self.fn1_slc0_rx_pf_valid_int_ena(),
             )
             .field(
                 "fn1_slc0_ext_bit0_int_ena",
-                &format_args!("{}", self.fn1_slc0_ext_bit0_int_ena().bit()),
+                &self.fn1_slc0_ext_bit0_int_ena(),
             )
             .field(
                 "fn1_slc0_ext_bit1_int_ena",
-                &format_args!("{}", self.fn1_slc0_ext_bit1_int_ena().bit()),
+                &self.fn1_slc0_ext_bit1_int_ena(),
             )
             .field(
                 "fn1_slc0_ext_bit2_int_ena",
-                &format_args!("{}", self.fn1_slc0_ext_bit2_int_ena().bit()),
+                &self.fn1_slc0_ext_bit2_int_ena(),
             )
             .field(
                 "fn1_slc0_ext_bit3_int_ena",
-                &format_args!("{}", self.fn1_slc0_ext_bit3_int_ena().bit()),
+                &self.fn1_slc0_ext_bit3_int_ena(),
             )
             .field(
                 "fn1_slc0_rx_new_packet_int_ena",
-                &format_args!("{}", self.fn1_slc0_rx_new_packet_int_ena().bit()),
+                &self.fn1_slc0_rx_new_packet_int_ena(),
             )
             .field(
                 "fn1_slc0_host_rd_retry_int_ena",
-                &format_args!("{}", self.fn1_slc0_host_rd_retry_int_ena().bit()),
-            )
-            .field(
-                "fn1_gpio_sdio_int_ena",
-                &format_args!("{}", self.fn1_gpio_sdio_int_ena().bit()),
+                &self.fn1_slc0_host_rd_retry_int_ena(),
             )
+            .field("fn1_gpio_sdio_int_ena", &self.fn1_gpio_sdio_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC0HOST_FUNC1_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc0host_func2_int_ena.rs b/esp32c6/src/slchost/slc0host_func2_int_ena.rs
index de52b8799d..ae04916dad 100644
--- a/esp32c6/src/slchost/slc0host_func2_int_ena.rs
+++ b/esp32c6/src/slchost/slc0host_func2_int_ena.rs
@@ -244,117 +244,102 @@ impl core::fmt::Debug for R {
         f.debug_struct("SLC0HOST_FUNC2_INT_ENA")
             .field(
                 "fn2_slc0_tohost_bit0_int_ena",
-                &format_args!("{}", self.fn2_slc0_tohost_bit0_int_ena().bit()),
+                &self.fn2_slc0_tohost_bit0_int_ena(),
             )
             .field(
                 "fn2_slc0_tohost_bit1_int_ena",
-                &format_args!("{}", self.fn2_slc0_tohost_bit1_int_ena().bit()),
+                &self.fn2_slc0_tohost_bit1_int_ena(),
             )
             .field(
                 "fn2_slc0_tohost_bit2_int_ena",
-                &format_args!("{}", self.fn2_slc0_tohost_bit2_int_ena().bit()),
+                &self.fn2_slc0_tohost_bit2_int_ena(),
             )
             .field(
                 "fn2_slc0_tohost_bit3_int_ena",
-                &format_args!("{}", self.fn2_slc0_tohost_bit3_int_ena().bit()),
+                &self.fn2_slc0_tohost_bit3_int_ena(),
             )
             .field(
                 "fn2_slc0_tohost_bit4_int_ena",
-                &format_args!("{}", self.fn2_slc0_tohost_bit4_int_ena().bit()),
+                &self.fn2_slc0_tohost_bit4_int_ena(),
             )
             .field(
                 "fn2_slc0_tohost_bit5_int_ena",
-                &format_args!("{}", self.fn2_slc0_tohost_bit5_int_ena().bit()),
+                &self.fn2_slc0_tohost_bit5_int_ena(),
             )
             .field(
                 "fn2_slc0_tohost_bit6_int_ena",
-                &format_args!("{}", self.fn2_slc0_tohost_bit6_int_ena().bit()),
+                &self.fn2_slc0_tohost_bit6_int_ena(),
             )
             .field(
                 "fn2_slc0_tohost_bit7_int_ena",
-                &format_args!("{}", self.fn2_slc0_tohost_bit7_int_ena().bit()),
+                &self.fn2_slc0_tohost_bit7_int_ena(),
             )
             .field(
                 "fn2_slc0_token0_1to0_int_ena",
-                &format_args!("{}", self.fn2_slc0_token0_1to0_int_ena().bit()),
+                &self.fn2_slc0_token0_1to0_int_ena(),
             )
             .field(
                 "fn2_slc0_token1_1to0_int_ena",
-                &format_args!("{}", self.fn2_slc0_token1_1to0_int_ena().bit()),
+                &self.fn2_slc0_token1_1to0_int_ena(),
             )
             .field(
                 "fn2_slc0_token0_0to1_int_ena",
-                &format_args!("{}", self.fn2_slc0_token0_0to1_int_ena().bit()),
+                &self.fn2_slc0_token0_0to1_int_ena(),
             )
             .field(
                 "fn2_slc0_token1_0to1_int_ena",
-                &format_args!("{}", self.fn2_slc0_token1_0to1_int_ena().bit()),
+                &self.fn2_slc0_token1_0to1_int_ena(),
             )
             .field(
                 "fn2_slc0host_rx_sof_int_ena",
-                &format_args!("{}", self.fn2_slc0host_rx_sof_int_ena().bit()),
+                &self.fn2_slc0host_rx_sof_int_ena(),
             )
             .field(
                 "fn2_slc0host_rx_eof_int_ena",
-                &format_args!("{}", self.fn2_slc0host_rx_eof_int_ena().bit()),
+                &self.fn2_slc0host_rx_eof_int_ena(),
             )
             .field(
                 "fn2_slc0host_rx_start_int_ena",
-                &format_args!("{}", self.fn2_slc0host_rx_start_int_ena().bit()),
+                &self.fn2_slc0host_rx_start_int_ena(),
             )
             .field(
                 "fn2_slc0host_tx_start_int_ena",
-                &format_args!("{}", self.fn2_slc0host_tx_start_int_ena().bit()),
-            )
-            .field(
-                "fn2_slc0_rx_udf_int_ena",
-                &format_args!("{}", self.fn2_slc0_rx_udf_int_ena().bit()),
-            )
-            .field(
-                "fn2_slc0_tx_ovf_int_ena",
-                &format_args!("{}", self.fn2_slc0_tx_ovf_int_ena().bit()),
+                &self.fn2_slc0host_tx_start_int_ena(),
             )
+            .field("fn2_slc0_rx_udf_int_ena", &self.fn2_slc0_rx_udf_int_ena())
+            .field("fn2_slc0_tx_ovf_int_ena", &self.fn2_slc0_tx_ovf_int_ena())
             .field(
                 "fn2_slc0_rx_pf_valid_int_ena",
-                &format_args!("{}", self.fn2_slc0_rx_pf_valid_int_ena().bit()),
+                &self.fn2_slc0_rx_pf_valid_int_ena(),
             )
             .field(
                 "fn2_slc0_ext_bit0_int_ena",
-                &format_args!("{}", self.fn2_slc0_ext_bit0_int_ena().bit()),
+                &self.fn2_slc0_ext_bit0_int_ena(),
             )
             .field(
                 "fn2_slc0_ext_bit1_int_ena",
-                &format_args!("{}", self.fn2_slc0_ext_bit1_int_ena().bit()),
+                &self.fn2_slc0_ext_bit1_int_ena(),
             )
             .field(
                 "fn2_slc0_ext_bit2_int_ena",
-                &format_args!("{}", self.fn2_slc0_ext_bit2_int_ena().bit()),
+                &self.fn2_slc0_ext_bit2_int_ena(),
             )
             .field(
                 "fn2_slc0_ext_bit3_int_ena",
-                &format_args!("{}", self.fn2_slc0_ext_bit3_int_ena().bit()),
+                &self.fn2_slc0_ext_bit3_int_ena(),
             )
             .field(
                 "fn2_slc0_rx_new_packet_int_ena",
-                &format_args!("{}", self.fn2_slc0_rx_new_packet_int_ena().bit()),
+                &self.fn2_slc0_rx_new_packet_int_ena(),
             )
             .field(
                 "fn2_slc0_host_rd_retry_int_ena",
-                &format_args!("{}", self.fn2_slc0_host_rd_retry_int_ena().bit()),
-            )
-            .field(
-                "fn2_gpio_sdio_int_ena",
-                &format_args!("{}", self.fn2_gpio_sdio_int_ena().bit()),
+                &self.fn2_slc0_host_rd_retry_int_ena(),
             )
+            .field("fn2_gpio_sdio_int_ena", &self.fn2_gpio_sdio_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC0HOST_FUNC2_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc0host_int_ena.rs b/esp32c6/src/slchost/slc0host_int_ena.rs
index d9c73a3e92..fd7060c6b6 100644
--- a/esp32c6/src/slchost/slc0host_int_ena.rs
+++ b/esp32c6/src/slchost/slc0host_int_ena.rs
@@ -242,119 +242,47 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC0HOST_INT_ENA")
-            .field(
-                "slc0_tohost_bit0_int_ena",
-                &format_args!("{}", self.slc0_tohost_bit0_int_ena().bit()),
-            )
-            .field(
-                "slc0_tohost_bit1_int_ena",
-                &format_args!("{}", self.slc0_tohost_bit1_int_ena().bit()),
-            )
-            .field(
-                "slc0_tohost_bit2_int_ena",
-                &format_args!("{}", self.slc0_tohost_bit2_int_ena().bit()),
-            )
-            .field(
-                "slc0_tohost_bit3_int_ena",
-                &format_args!("{}", self.slc0_tohost_bit3_int_ena().bit()),
-            )
-            .field(
-                "slc0_tohost_bit4_int_ena",
-                &format_args!("{}", self.slc0_tohost_bit4_int_ena().bit()),
-            )
-            .field(
-                "slc0_tohost_bit5_int_ena",
-                &format_args!("{}", self.slc0_tohost_bit5_int_ena().bit()),
-            )
-            .field(
-                "slc0_tohost_bit6_int_ena",
-                &format_args!("{}", self.slc0_tohost_bit6_int_ena().bit()),
-            )
-            .field(
-                "slc0_tohost_bit7_int_ena",
-                &format_args!("{}", self.slc0_tohost_bit7_int_ena().bit()),
-            )
-            .field(
-                "slc0_token0_1to0_int_ena",
-                &format_args!("{}", self.slc0_token0_1to0_int_ena().bit()),
-            )
-            .field(
-                "slc0_token1_1to0_int_ena",
-                &format_args!("{}", self.slc0_token1_1to0_int_ena().bit()),
-            )
-            .field(
-                "slc0_token0_0to1_int_ena",
-                &format_args!("{}", self.slc0_token0_0to1_int_ena().bit()),
-            )
-            .field(
-                "slc0_token1_0to1_int_ena",
-                &format_args!("{}", self.slc0_token1_0to1_int_ena().bit()),
-            )
-            .field(
-                "slc0host_rx_sof_int_ena",
-                &format_args!("{}", self.slc0host_rx_sof_int_ena().bit()),
-            )
-            .field(
-                "slc0host_rx_eof_int_ena",
-                &format_args!("{}", self.slc0host_rx_eof_int_ena().bit()),
-            )
+            .field("slc0_tohost_bit0_int_ena", &self.slc0_tohost_bit0_int_ena())
+            .field("slc0_tohost_bit1_int_ena", &self.slc0_tohost_bit1_int_ena())
+            .field("slc0_tohost_bit2_int_ena", &self.slc0_tohost_bit2_int_ena())
+            .field("slc0_tohost_bit3_int_ena", &self.slc0_tohost_bit3_int_ena())
+            .field("slc0_tohost_bit4_int_ena", &self.slc0_tohost_bit4_int_ena())
+            .field("slc0_tohost_bit5_int_ena", &self.slc0_tohost_bit5_int_ena())
+            .field("slc0_tohost_bit6_int_ena", &self.slc0_tohost_bit6_int_ena())
+            .field("slc0_tohost_bit7_int_ena", &self.slc0_tohost_bit7_int_ena())
+            .field("slc0_token0_1to0_int_ena", &self.slc0_token0_1to0_int_ena())
+            .field("slc0_token1_1to0_int_ena", &self.slc0_token1_1to0_int_ena())
+            .field("slc0_token0_0to1_int_ena", &self.slc0_token0_0to1_int_ena())
+            .field("slc0_token1_0to1_int_ena", &self.slc0_token1_0to1_int_ena())
+            .field("slc0host_rx_sof_int_ena", &self.slc0host_rx_sof_int_ena())
+            .field("slc0host_rx_eof_int_ena", &self.slc0host_rx_eof_int_ena())
             .field(
                 "slc0host_rx_start_int_ena",
-                &format_args!("{}", self.slc0host_rx_start_int_ena().bit()),
+                &self.slc0host_rx_start_int_ena(),
             )
             .field(
                 "slc0host_tx_start_int_ena",
-                &format_args!("{}", self.slc0host_tx_start_int_ena().bit()),
-            )
-            .field(
-                "slc0_rx_udf_int_ena",
-                &format_args!("{}", self.slc0_rx_udf_int_ena().bit()),
-            )
-            .field(
-                "slc0_tx_ovf_int_ena",
-                &format_args!("{}", self.slc0_tx_ovf_int_ena().bit()),
-            )
-            .field(
-                "slc0_rx_pf_valid_int_ena",
-                &format_args!("{}", self.slc0_rx_pf_valid_int_ena().bit()),
-            )
-            .field(
-                "slc0_ext_bit0_int_ena",
-                &format_args!("{}", self.slc0_ext_bit0_int_ena().bit()),
-            )
-            .field(
-                "slc0_ext_bit1_int_ena",
-                &format_args!("{}", self.slc0_ext_bit1_int_ena().bit()),
-            )
-            .field(
-                "slc0_ext_bit2_int_ena",
-                &format_args!("{}", self.slc0_ext_bit2_int_ena().bit()),
-            )
-            .field(
-                "slc0_ext_bit3_int_ena",
-                &format_args!("{}", self.slc0_ext_bit3_int_ena().bit()),
+                &self.slc0host_tx_start_int_ena(),
             )
+            .field("slc0_rx_udf_int_ena", &self.slc0_rx_udf_int_ena())
+            .field("slc0_tx_ovf_int_ena", &self.slc0_tx_ovf_int_ena())
+            .field("slc0_rx_pf_valid_int_ena", &self.slc0_rx_pf_valid_int_ena())
+            .field("slc0_ext_bit0_int_ena", &self.slc0_ext_bit0_int_ena())
+            .field("slc0_ext_bit1_int_ena", &self.slc0_ext_bit1_int_ena())
+            .field("slc0_ext_bit2_int_ena", &self.slc0_ext_bit2_int_ena())
+            .field("slc0_ext_bit3_int_ena", &self.slc0_ext_bit3_int_ena())
             .field(
                 "slc0_rx_new_packet_int_ena",
-                &format_args!("{}", self.slc0_rx_new_packet_int_ena().bit()),
+                &self.slc0_rx_new_packet_int_ena(),
             )
             .field(
                 "slc0_host_rd_retry_int_ena",
-                &format_args!("{}", self.slc0_host_rd_retry_int_ena().bit()),
-            )
-            .field(
-                "gpio_sdio_int_ena",
-                &format_args!("{}", self.gpio_sdio_int_ena().bit()),
+                &self.slc0_host_rd_retry_int_ena(),
             )
+            .field("gpio_sdio_int_ena", &self.gpio_sdio_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC0HOST_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc0host_int_ena1.rs b/esp32c6/src/slchost/slc0host_int_ena1.rs
index 9928b25704..8a40ae456d 100644
--- a/esp32c6/src/slchost/slc0host_int_ena1.rs
+++ b/esp32c6/src/slchost/slc0host_int_ena1.rs
@@ -244,117 +244,84 @@ impl core::fmt::Debug for R {
         f.debug_struct("SLC0HOST_INT_ENA1")
             .field(
                 "slc0_tohost_bit0_int_ena1",
-                &format_args!("{}", self.slc0_tohost_bit0_int_ena1().bit()),
+                &self.slc0_tohost_bit0_int_ena1(),
             )
             .field(
                 "slc0_tohost_bit1_int_ena1",
-                &format_args!("{}", self.slc0_tohost_bit1_int_ena1().bit()),
+                &self.slc0_tohost_bit1_int_ena1(),
             )
             .field(
                 "slc0_tohost_bit2_int_ena1",
-                &format_args!("{}", self.slc0_tohost_bit2_int_ena1().bit()),
+                &self.slc0_tohost_bit2_int_ena1(),
             )
             .field(
                 "slc0_tohost_bit3_int_ena1",
-                &format_args!("{}", self.slc0_tohost_bit3_int_ena1().bit()),
+                &self.slc0_tohost_bit3_int_ena1(),
             )
             .field(
                 "slc0_tohost_bit4_int_ena1",
-                &format_args!("{}", self.slc0_tohost_bit4_int_ena1().bit()),
+                &self.slc0_tohost_bit4_int_ena1(),
             )
             .field(
                 "slc0_tohost_bit5_int_ena1",
-                &format_args!("{}", self.slc0_tohost_bit5_int_ena1().bit()),
+                &self.slc0_tohost_bit5_int_ena1(),
             )
             .field(
                 "slc0_tohost_bit6_int_ena1",
-                &format_args!("{}", self.slc0_tohost_bit6_int_ena1().bit()),
+                &self.slc0_tohost_bit6_int_ena1(),
             )
             .field(
                 "slc0_tohost_bit7_int_ena1",
-                &format_args!("{}", self.slc0_tohost_bit7_int_ena1().bit()),
+                &self.slc0_tohost_bit7_int_ena1(),
             )
             .field(
                 "slc0_token0_1to0_int_ena1",
-                &format_args!("{}", self.slc0_token0_1to0_int_ena1().bit()),
+                &self.slc0_token0_1to0_int_ena1(),
             )
             .field(
                 "slc0_token1_1to0_int_ena1",
-                &format_args!("{}", self.slc0_token1_1to0_int_ena1().bit()),
+                &self.slc0_token1_1to0_int_ena1(),
             )
             .field(
                 "slc0_token0_0to1_int_ena1",
-                &format_args!("{}", self.slc0_token0_0to1_int_ena1().bit()),
+                &self.slc0_token0_0to1_int_ena1(),
             )
             .field(
                 "slc0_token1_0to1_int_ena1",
-                &format_args!("{}", self.slc0_token1_0to1_int_ena1().bit()),
-            )
-            .field(
-                "slc0host_rx_sof_int_ena1",
-                &format_args!("{}", self.slc0host_rx_sof_int_ena1().bit()),
-            )
-            .field(
-                "slc0host_rx_eof_int_ena1",
-                &format_args!("{}", self.slc0host_rx_eof_int_ena1().bit()),
+                &self.slc0_token1_0to1_int_ena1(),
             )
+            .field("slc0host_rx_sof_int_ena1", &self.slc0host_rx_sof_int_ena1())
+            .field("slc0host_rx_eof_int_ena1", &self.slc0host_rx_eof_int_ena1())
             .field(
                 "slc0host_rx_start_int_ena1",
-                &format_args!("{}", self.slc0host_rx_start_int_ena1().bit()),
+                &self.slc0host_rx_start_int_ena1(),
             )
             .field(
                 "slc0host_tx_start_int_ena1",
-                &format_args!("{}", self.slc0host_tx_start_int_ena1().bit()),
-            )
-            .field(
-                "slc0_rx_udf_int_ena1",
-                &format_args!("{}", self.slc0_rx_udf_int_ena1().bit()),
-            )
-            .field(
-                "slc0_tx_ovf_int_ena1",
-                &format_args!("{}", self.slc0_tx_ovf_int_ena1().bit()),
+                &self.slc0host_tx_start_int_ena1(),
             )
+            .field("slc0_rx_udf_int_ena1", &self.slc0_rx_udf_int_ena1())
+            .field("slc0_tx_ovf_int_ena1", &self.slc0_tx_ovf_int_ena1())
             .field(
                 "slc0_rx_pf_valid_int_ena1",
-                &format_args!("{}", self.slc0_rx_pf_valid_int_ena1().bit()),
-            )
-            .field(
-                "slc0_ext_bit0_int_ena1",
-                &format_args!("{}", self.slc0_ext_bit0_int_ena1().bit()),
-            )
-            .field(
-                "slc0_ext_bit1_int_ena1",
-                &format_args!("{}", self.slc0_ext_bit1_int_ena1().bit()),
-            )
-            .field(
-                "slc0_ext_bit2_int_ena1",
-                &format_args!("{}", self.slc0_ext_bit2_int_ena1().bit()),
-            )
-            .field(
-                "slc0_ext_bit3_int_ena1",
-                &format_args!("{}", self.slc0_ext_bit3_int_ena1().bit()),
+                &self.slc0_rx_pf_valid_int_ena1(),
             )
+            .field("slc0_ext_bit0_int_ena1", &self.slc0_ext_bit0_int_ena1())
+            .field("slc0_ext_bit1_int_ena1", &self.slc0_ext_bit1_int_ena1())
+            .field("slc0_ext_bit2_int_ena1", &self.slc0_ext_bit2_int_ena1())
+            .field("slc0_ext_bit3_int_ena1", &self.slc0_ext_bit3_int_ena1())
             .field(
                 "slc0_rx_new_packet_int_ena1",
-                &format_args!("{}", self.slc0_rx_new_packet_int_ena1().bit()),
+                &self.slc0_rx_new_packet_int_ena1(),
             )
             .field(
                 "slc0_host_rd_retry_int_ena1",
-                &format_args!("{}", self.slc0_host_rd_retry_int_ena1().bit()),
-            )
-            .field(
-                "gpio_sdio_int_ena1",
-                &format_args!("{}", self.gpio_sdio_int_ena1().bit()),
+                &self.slc0_host_rd_retry_int_ena1(),
             )
+            .field("gpio_sdio_int_ena1", &self.gpio_sdio_int_ena1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC0HOST_INT_ENA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc0host_int_raw.rs b/esp32c6/src/slchost/slc0host_int_raw.rs
index e8e0adb288..ff8dbfcc02 100644
--- a/esp32c6/src/slchost/slc0host_int_raw.rs
+++ b/esp32c6/src/slchost/slc0host_int_raw.rs
@@ -242,119 +242,47 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC0HOST_INT_RAW")
-            .field(
-                "slc0_tohost_bit0_int_raw",
-                &format_args!("{}", self.slc0_tohost_bit0_int_raw().bit()),
-            )
-            .field(
-                "slc0_tohost_bit1_int_raw",
-                &format_args!("{}", self.slc0_tohost_bit1_int_raw().bit()),
-            )
-            .field(
-                "slc0_tohost_bit2_int_raw",
-                &format_args!("{}", self.slc0_tohost_bit2_int_raw().bit()),
-            )
-            .field(
-                "slc0_tohost_bit3_int_raw",
-                &format_args!("{}", self.slc0_tohost_bit3_int_raw().bit()),
-            )
-            .field(
-                "slc0_tohost_bit4_int_raw",
-                &format_args!("{}", self.slc0_tohost_bit4_int_raw().bit()),
-            )
-            .field(
-                "slc0_tohost_bit5_int_raw",
-                &format_args!("{}", self.slc0_tohost_bit5_int_raw().bit()),
-            )
-            .field(
-                "slc0_tohost_bit6_int_raw",
-                &format_args!("{}", self.slc0_tohost_bit6_int_raw().bit()),
-            )
-            .field(
-                "slc0_tohost_bit7_int_raw",
-                &format_args!("{}", self.slc0_tohost_bit7_int_raw().bit()),
-            )
-            .field(
-                "slc0_token0_1to0_int_raw",
-                &format_args!("{}", self.slc0_token0_1to0_int_raw().bit()),
-            )
-            .field(
-                "slc0_token1_1to0_int_raw",
-                &format_args!("{}", self.slc0_token1_1to0_int_raw().bit()),
-            )
-            .field(
-                "slc0_token0_0to1_int_raw",
-                &format_args!("{}", self.slc0_token0_0to1_int_raw().bit()),
-            )
-            .field(
-                "slc0_token1_0to1_int_raw",
-                &format_args!("{}", self.slc0_token1_0to1_int_raw().bit()),
-            )
-            .field(
-                "slc0host_rx_sof_int_raw",
-                &format_args!("{}", self.slc0host_rx_sof_int_raw().bit()),
-            )
-            .field(
-                "slc0host_rx_eof_int_raw",
-                &format_args!("{}", self.slc0host_rx_eof_int_raw().bit()),
-            )
+            .field("slc0_tohost_bit0_int_raw", &self.slc0_tohost_bit0_int_raw())
+            .field("slc0_tohost_bit1_int_raw", &self.slc0_tohost_bit1_int_raw())
+            .field("slc0_tohost_bit2_int_raw", &self.slc0_tohost_bit2_int_raw())
+            .field("slc0_tohost_bit3_int_raw", &self.slc0_tohost_bit3_int_raw())
+            .field("slc0_tohost_bit4_int_raw", &self.slc0_tohost_bit4_int_raw())
+            .field("slc0_tohost_bit5_int_raw", &self.slc0_tohost_bit5_int_raw())
+            .field("slc0_tohost_bit6_int_raw", &self.slc0_tohost_bit6_int_raw())
+            .field("slc0_tohost_bit7_int_raw", &self.slc0_tohost_bit7_int_raw())
+            .field("slc0_token0_1to0_int_raw", &self.slc0_token0_1to0_int_raw())
+            .field("slc0_token1_1to0_int_raw", &self.slc0_token1_1to0_int_raw())
+            .field("slc0_token0_0to1_int_raw", &self.slc0_token0_0to1_int_raw())
+            .field("slc0_token1_0to1_int_raw", &self.slc0_token1_0to1_int_raw())
+            .field("slc0host_rx_sof_int_raw", &self.slc0host_rx_sof_int_raw())
+            .field("slc0host_rx_eof_int_raw", &self.slc0host_rx_eof_int_raw())
             .field(
                 "slc0host_rx_start_int_raw",
-                &format_args!("{}", self.slc0host_rx_start_int_raw().bit()),
+                &self.slc0host_rx_start_int_raw(),
             )
             .field(
                 "slc0host_tx_start_int_raw",
-                &format_args!("{}", self.slc0host_tx_start_int_raw().bit()),
-            )
-            .field(
-                "slc0_rx_udf_int_raw",
-                &format_args!("{}", self.slc0_rx_udf_int_raw().bit()),
-            )
-            .field(
-                "slc0_tx_ovf_int_raw",
-                &format_args!("{}", self.slc0_tx_ovf_int_raw().bit()),
-            )
-            .field(
-                "slc0_rx_pf_valid_int_raw",
-                &format_args!("{}", self.slc0_rx_pf_valid_int_raw().bit()),
-            )
-            .field(
-                "slc0_ext_bit0_int_raw",
-                &format_args!("{}", self.slc0_ext_bit0_int_raw().bit()),
-            )
-            .field(
-                "slc0_ext_bit1_int_raw",
-                &format_args!("{}", self.slc0_ext_bit1_int_raw().bit()),
-            )
-            .field(
-                "slc0_ext_bit2_int_raw",
-                &format_args!("{}", self.slc0_ext_bit2_int_raw().bit()),
-            )
-            .field(
-                "slc0_ext_bit3_int_raw",
-                &format_args!("{}", self.slc0_ext_bit3_int_raw().bit()),
+                &self.slc0host_tx_start_int_raw(),
             )
+            .field("slc0_rx_udf_int_raw", &self.slc0_rx_udf_int_raw())
+            .field("slc0_tx_ovf_int_raw", &self.slc0_tx_ovf_int_raw())
+            .field("slc0_rx_pf_valid_int_raw", &self.slc0_rx_pf_valid_int_raw())
+            .field("slc0_ext_bit0_int_raw", &self.slc0_ext_bit0_int_raw())
+            .field("slc0_ext_bit1_int_raw", &self.slc0_ext_bit1_int_raw())
+            .field("slc0_ext_bit2_int_raw", &self.slc0_ext_bit2_int_raw())
+            .field("slc0_ext_bit3_int_raw", &self.slc0_ext_bit3_int_raw())
             .field(
                 "slc0_rx_new_packet_int_raw",
-                &format_args!("{}", self.slc0_rx_new_packet_int_raw().bit()),
+                &self.slc0_rx_new_packet_int_raw(),
             )
             .field(
                 "slc0_host_rd_retry_int_raw",
-                &format_args!("{}", self.slc0_host_rd_retry_int_raw().bit()),
-            )
-            .field(
-                "gpio_sdio_int_raw",
-                &format_args!("{}", self.gpio_sdio_int_raw().bit()),
+                &self.slc0_host_rd_retry_int_raw(),
             )
+            .field("gpio_sdio_int_raw", &self.gpio_sdio_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC0HOST_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc0host_int_st.rs b/esp32c6/src/slchost/slc0host_int_st.rs
index 0c1020f667..2215a41b08 100644
--- a/esp32c6/src/slchost/slc0host_int_st.rs
+++ b/esp32c6/src/slchost/slc0host_int_st.rs
@@ -188,119 +188,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC0HOST_INT_ST")
-            .field(
-                "slc0_tohost_bit0_int_st",
-                &format_args!("{}", self.slc0_tohost_bit0_int_st().bit()),
-            )
-            .field(
-                "slc0_tohost_bit1_int_st",
-                &format_args!("{}", self.slc0_tohost_bit1_int_st().bit()),
-            )
-            .field(
-                "slc0_tohost_bit2_int_st",
-                &format_args!("{}", self.slc0_tohost_bit2_int_st().bit()),
-            )
-            .field(
-                "slc0_tohost_bit3_int_st",
-                &format_args!("{}", self.slc0_tohost_bit3_int_st().bit()),
-            )
-            .field(
-                "slc0_tohost_bit4_int_st",
-                &format_args!("{}", self.slc0_tohost_bit4_int_st().bit()),
-            )
-            .field(
-                "slc0_tohost_bit5_int_st",
-                &format_args!("{}", self.slc0_tohost_bit5_int_st().bit()),
-            )
-            .field(
-                "slc0_tohost_bit6_int_st",
-                &format_args!("{}", self.slc0_tohost_bit6_int_st().bit()),
-            )
-            .field(
-                "slc0_tohost_bit7_int_st",
-                &format_args!("{}", self.slc0_tohost_bit7_int_st().bit()),
-            )
-            .field(
-                "slc0_token0_1to0_int_st",
-                &format_args!("{}", self.slc0_token0_1to0_int_st().bit()),
-            )
-            .field(
-                "slc0_token1_1to0_int_st",
-                &format_args!("{}", self.slc0_token1_1to0_int_st().bit()),
-            )
-            .field(
-                "slc0_token0_0to1_int_st",
-                &format_args!("{}", self.slc0_token0_0to1_int_st().bit()),
-            )
-            .field(
-                "slc0_token1_0to1_int_st",
-                &format_args!("{}", self.slc0_token1_0to1_int_st().bit()),
-            )
-            .field(
-                "slc0host_rx_sof_int_st",
-                &format_args!("{}", self.slc0host_rx_sof_int_st().bit()),
-            )
-            .field(
-                "slc0host_rx_eof_int_st",
-                &format_args!("{}", self.slc0host_rx_eof_int_st().bit()),
-            )
-            .field(
-                "slc0host_rx_start_int_st",
-                &format_args!("{}", self.slc0host_rx_start_int_st().bit()),
-            )
-            .field(
-                "slc0host_tx_start_int_st",
-                &format_args!("{}", self.slc0host_tx_start_int_st().bit()),
-            )
-            .field(
-                "slc0_rx_udf_int_st",
-                &format_args!("{}", self.slc0_rx_udf_int_st().bit()),
-            )
-            .field(
-                "slc0_tx_ovf_int_st",
-                &format_args!("{}", self.slc0_tx_ovf_int_st().bit()),
-            )
-            .field(
-                "slc0_rx_pf_valid_int_st",
-                &format_args!("{}", self.slc0_rx_pf_valid_int_st().bit()),
-            )
-            .field(
-                "slc0_ext_bit0_int_st",
-                &format_args!("{}", self.slc0_ext_bit0_int_st().bit()),
-            )
-            .field(
-                "slc0_ext_bit1_int_st",
-                &format_args!("{}", self.slc0_ext_bit1_int_st().bit()),
-            )
-            .field(
-                "slc0_ext_bit2_int_st",
-                &format_args!("{}", self.slc0_ext_bit2_int_st().bit()),
-            )
-            .field(
-                "slc0_ext_bit3_int_st",
-                &format_args!("{}", self.slc0_ext_bit3_int_st().bit()),
-            )
+            .field("slc0_tohost_bit0_int_st", &self.slc0_tohost_bit0_int_st())
+            .field("slc0_tohost_bit1_int_st", &self.slc0_tohost_bit1_int_st())
+            .field("slc0_tohost_bit2_int_st", &self.slc0_tohost_bit2_int_st())
+            .field("slc0_tohost_bit3_int_st", &self.slc0_tohost_bit3_int_st())
+            .field("slc0_tohost_bit4_int_st", &self.slc0_tohost_bit4_int_st())
+            .field("slc0_tohost_bit5_int_st", &self.slc0_tohost_bit5_int_st())
+            .field("slc0_tohost_bit6_int_st", &self.slc0_tohost_bit6_int_st())
+            .field("slc0_tohost_bit7_int_st", &self.slc0_tohost_bit7_int_st())
+            .field("slc0_token0_1to0_int_st", &self.slc0_token0_1to0_int_st())
+            .field("slc0_token1_1to0_int_st", &self.slc0_token1_1to0_int_st())
+            .field("slc0_token0_0to1_int_st", &self.slc0_token0_0to1_int_st())
+            .field("slc0_token1_0to1_int_st", &self.slc0_token1_0to1_int_st())
+            .field("slc0host_rx_sof_int_st", &self.slc0host_rx_sof_int_st())
+            .field("slc0host_rx_eof_int_st", &self.slc0host_rx_eof_int_st())
+            .field("slc0host_rx_start_int_st", &self.slc0host_rx_start_int_st())
+            .field("slc0host_tx_start_int_st", &self.slc0host_tx_start_int_st())
+            .field("slc0_rx_udf_int_st", &self.slc0_rx_udf_int_st())
+            .field("slc0_tx_ovf_int_st", &self.slc0_tx_ovf_int_st())
+            .field("slc0_rx_pf_valid_int_st", &self.slc0_rx_pf_valid_int_st())
+            .field("slc0_ext_bit0_int_st", &self.slc0_ext_bit0_int_st())
+            .field("slc0_ext_bit1_int_st", &self.slc0_ext_bit1_int_st())
+            .field("slc0_ext_bit2_int_st", &self.slc0_ext_bit2_int_st())
+            .field("slc0_ext_bit3_int_st", &self.slc0_ext_bit3_int_st())
             .field(
                 "slc0_rx_new_packet_int_st",
-                &format_args!("{}", self.slc0_rx_new_packet_int_st().bit()),
+                &self.slc0_rx_new_packet_int_st(),
             )
             .field(
                 "slc0_host_rd_retry_int_st",
-                &format_args!("{}", self.slc0_host_rd_retry_int_st().bit()),
-            )
-            .field(
-                "gpio_sdio_int_st",
-                &format_args!("{}", self.gpio_sdio_int_st().bit()),
+                &self.slc0_host_rd_retry_int_st(),
             )
+            .field("gpio_sdio_int_st", &self.gpio_sdio_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC0HOST_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc0host_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLC0HOST_INT_ST_SPEC;
 impl crate::RegisterSpec for SLC0HOST_INT_ST_SPEC {
diff --git a/esp32c6/src/slchost/slc0host_len_wd.rs b/esp32c6/src/slchost/slc0host_len_wd.rs
index bddafc7e4e..5794519881 100644
--- a/esp32c6/src/slchost/slc0host_len_wd.rs
+++ b/esp32c6/src/slchost/slc0host_len_wd.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC0HOST_LEN_WD")
-            .field(
-                "slc0host_len_wd",
-                &format_args!("{}", self.slc0host_len_wd().bits()),
-            )
+            .field("slc0host_len_wd", &self.slc0host_len_wd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC0HOST_LEN_WD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc0host_rx_infor.rs b/esp32c6/src/slchost/slc0host_rx_infor.rs
index c296c750ef..8b3fa35a3b 100644
--- a/esp32c6/src/slchost/slc0host_rx_infor.rs
+++ b/esp32c6/src/slchost/slc0host_rx_infor.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC0HOST_RX_INFOR")
-            .field(
-                "slc0host_rx_infor",
-                &format_args!("{}", self.slc0host_rx_infor().bits()),
-            )
+            .field("slc0host_rx_infor", &self.slc0host_rx_infor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC0HOST_RX_INFOR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc0host_token_rdata.rs b/esp32c6/src/slchost/slc0host_token_rdata.rs
index 90b67315dc..076682b2bb 100644
--- a/esp32c6/src/slchost/slc0host_token_rdata.rs
+++ b/esp32c6/src/slchost/slc0host_token_rdata.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC0HOST_TOKEN_RDATA")
-            .field(
-                "slc0_token0",
-                &format_args!("{}", self.slc0_token0().bits()),
-            )
-            .field(
-                "slc0_rx_pf_valid",
-                &format_args!("{}", self.slc0_rx_pf_valid().bit()),
-            )
-            .field(
-                "hostslchost_slc0_token1",
-                &format_args!("{}", self.hostslchost_slc0_token1().bits()),
-            )
-            .field(
-                "slc0_rx_pf_eof",
-                &format_args!("{}", self.slc0_rx_pf_eof().bits()),
-            )
+            .field("slc0_token0", &self.slc0_token0())
+            .field("slc0_rx_pf_valid", &self.slc0_rx_pf_valid())
+            .field("hostslchost_slc0_token1", &self.hostslchost_slc0_token1())
+            .field("slc0_rx_pf_eof", &self.slc0_rx_pf_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC0HOST_TOKEN_RDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc0host_token_rdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLC0HOST_TOKEN_RDATA_SPEC;
 impl crate::RegisterSpec for SLC0HOST_TOKEN_RDATA_SPEC {
diff --git a/esp32c6/src/slchost/slc0host_token_wdata.rs b/esp32c6/src/slchost/slc0host_token_wdata.rs
index 40ae8aa42e..220b01b6da 100644
--- a/esp32c6/src/slchost/slc0host_token_wdata.rs
+++ b/esp32c6/src/slchost/slc0host_token_wdata.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC0HOST_TOKEN_WDATA")
-            .field(
-                "slc0host_token0_wd",
-                &format_args!("{}", self.slc0host_token0_wd().bits()),
-            )
-            .field(
-                "slc0host_token1_wd",
-                &format_args!("{}", self.slc0host_token1_wd().bits()),
-            )
+            .field("slc0host_token0_wd", &self.slc0host_token0_wd())
+            .field("slc0host_token1_wd", &self.slc0host_token1_wd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC0HOST_TOKEN_WDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc1_host_pf.rs b/esp32c6/src/slchost/slc1_host_pf.rs
index 15336055d9..64a0474972 100644
--- a/esp32c6/src/slchost/slc1_host_pf.rs
+++ b/esp32c6/src/slchost/slc1_host_pf.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC1_HOST_PF")
-            .field(
-                "slc1_pf_data",
-                &format_args!("{}", self.slc1_pf_data().bits()),
-            )
+            .field("slc1_pf_data", &self.slc1_pf_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC1_HOST_PF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc1_host_pf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLC1_HOST_PF_SPEC;
 impl crate::RegisterSpec for SLC1_HOST_PF_SPEC {
diff --git a/esp32c6/src/slchost/slc1host_func1_int_ena.rs b/esp32c6/src/slchost/slc1host_func1_int_ena.rs
index 753863ea79..bcdc942d45 100644
--- a/esp32c6/src/slchost/slc1host_func1_int_ena.rs
+++ b/esp32c6/src/slchost/slc1host_func1_int_ena.rs
@@ -244,117 +244,105 @@ impl core::fmt::Debug for R {
         f.debug_struct("SLC1HOST_FUNC1_INT_ENA")
             .field(
                 "fn1_slc1_tohost_bit0_int_ena",
-                &format_args!("{}", self.fn1_slc1_tohost_bit0_int_ena().bit()),
+                &self.fn1_slc1_tohost_bit0_int_ena(),
             )
             .field(
                 "fn1_slc1_tohost_bit1_int_ena",
-                &format_args!("{}", self.fn1_slc1_tohost_bit1_int_ena().bit()),
+                &self.fn1_slc1_tohost_bit1_int_ena(),
             )
             .field(
                 "fn1_slc1_tohost_bit2_int_ena",
-                &format_args!("{}", self.fn1_slc1_tohost_bit2_int_ena().bit()),
+                &self.fn1_slc1_tohost_bit2_int_ena(),
             )
             .field(
                 "fn1_slc1_tohost_bit3_int_ena",
-                &format_args!("{}", self.fn1_slc1_tohost_bit3_int_ena().bit()),
+                &self.fn1_slc1_tohost_bit3_int_ena(),
             )
             .field(
                 "fn1_slc1_tohost_bit4_int_ena",
-                &format_args!("{}", self.fn1_slc1_tohost_bit4_int_ena().bit()),
+                &self.fn1_slc1_tohost_bit4_int_ena(),
             )
             .field(
                 "fn1_slc1_tohost_bit5_int_ena",
-                &format_args!("{}", self.fn1_slc1_tohost_bit5_int_ena().bit()),
+                &self.fn1_slc1_tohost_bit5_int_ena(),
             )
             .field(
                 "fn1_slc1_tohost_bit6_int_ena",
-                &format_args!("{}", self.fn1_slc1_tohost_bit6_int_ena().bit()),
+                &self.fn1_slc1_tohost_bit6_int_ena(),
             )
             .field(
                 "fn1_slc1_tohost_bit7_int_ena",
-                &format_args!("{}", self.fn1_slc1_tohost_bit7_int_ena().bit()),
+                &self.fn1_slc1_tohost_bit7_int_ena(),
             )
             .field(
                 "fn1_slc1_token0_1to0_int_ena",
-                &format_args!("{}", self.fn1_slc1_token0_1to0_int_ena().bit()),
+                &self.fn1_slc1_token0_1to0_int_ena(),
             )
             .field(
                 "fn1_slc1_token1_1to0_int_ena",
-                &format_args!("{}", self.fn1_slc1_token1_1to0_int_ena().bit()),
+                &self.fn1_slc1_token1_1to0_int_ena(),
             )
             .field(
                 "fn1_slc1_token0_0to1_int_ena",
-                &format_args!("{}", self.fn1_slc1_token0_0to1_int_ena().bit()),
+                &self.fn1_slc1_token0_0to1_int_ena(),
             )
             .field(
                 "fn1_slc1_token1_0to1_int_ena",
-                &format_args!("{}", self.fn1_slc1_token1_0to1_int_ena().bit()),
+                &self.fn1_slc1_token1_0to1_int_ena(),
             )
             .field(
                 "fn1_slc1host_rx_sof_int_ena",
-                &format_args!("{}", self.fn1_slc1host_rx_sof_int_ena().bit()),
+                &self.fn1_slc1host_rx_sof_int_ena(),
             )
             .field(
                 "fn1_slc1host_rx_eof_int_ena",
-                &format_args!("{}", self.fn1_slc1host_rx_eof_int_ena().bit()),
+                &self.fn1_slc1host_rx_eof_int_ena(),
             )
             .field(
                 "fn1_slc1host_rx_start_int_ena",
-                &format_args!("{}", self.fn1_slc1host_rx_start_int_ena().bit()),
+                &self.fn1_slc1host_rx_start_int_ena(),
             )
             .field(
                 "fn1_slc1host_tx_start_int_ena",
-                &format_args!("{}", self.fn1_slc1host_tx_start_int_ena().bit()),
-            )
-            .field(
-                "fn1_slc1_rx_udf_int_ena",
-                &format_args!("{}", self.fn1_slc1_rx_udf_int_ena().bit()),
-            )
-            .field(
-                "fn1_slc1_tx_ovf_int_ena",
-                &format_args!("{}", self.fn1_slc1_tx_ovf_int_ena().bit()),
+                &self.fn1_slc1host_tx_start_int_ena(),
             )
+            .field("fn1_slc1_rx_udf_int_ena", &self.fn1_slc1_rx_udf_int_ena())
+            .field("fn1_slc1_tx_ovf_int_ena", &self.fn1_slc1_tx_ovf_int_ena())
             .field(
                 "fn1_slc1_rx_pf_valid_int_ena",
-                &format_args!("{}", self.fn1_slc1_rx_pf_valid_int_ena().bit()),
+                &self.fn1_slc1_rx_pf_valid_int_ena(),
             )
             .field(
                 "fn1_slc1_ext_bit0_int_ena",
-                &format_args!("{}", self.fn1_slc1_ext_bit0_int_ena().bit()),
+                &self.fn1_slc1_ext_bit0_int_ena(),
             )
             .field(
                 "fn1_slc1_ext_bit1_int_ena",
-                &format_args!("{}", self.fn1_slc1_ext_bit1_int_ena().bit()),
+                &self.fn1_slc1_ext_bit1_int_ena(),
             )
             .field(
                 "fn1_slc1_ext_bit2_int_ena",
-                &format_args!("{}", self.fn1_slc1_ext_bit2_int_ena().bit()),
+                &self.fn1_slc1_ext_bit2_int_ena(),
             )
             .field(
                 "fn1_slc1_ext_bit3_int_ena",
-                &format_args!("{}", self.fn1_slc1_ext_bit3_int_ena().bit()),
+                &self.fn1_slc1_ext_bit3_int_ena(),
             )
             .field(
                 "fn1_slc1_wifi_rx_new_packet_int_ena",
-                &format_args!("{}", self.fn1_slc1_wifi_rx_new_packet_int_ena().bit()),
+                &self.fn1_slc1_wifi_rx_new_packet_int_ena(),
             )
             .field(
                 "fn1_slc1_host_rd_retry_int_ena",
-                &format_args!("{}", self.fn1_slc1_host_rd_retry_int_ena().bit()),
+                &self.fn1_slc1_host_rd_retry_int_ena(),
             )
             .field(
                 "fn1_slc1_bt_rx_new_packet_int_ena",
-                &format_args!("{}", self.fn1_slc1_bt_rx_new_packet_int_ena().bit()),
+                &self.fn1_slc1_bt_rx_new_packet_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC1HOST_FUNC1_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc1host_func2_int_ena.rs b/esp32c6/src/slchost/slc1host_func2_int_ena.rs
index 35af39250d..ccfe221b8d 100644
--- a/esp32c6/src/slchost/slc1host_func2_int_ena.rs
+++ b/esp32c6/src/slchost/slc1host_func2_int_ena.rs
@@ -244,117 +244,105 @@ impl core::fmt::Debug for R {
         f.debug_struct("SLC1HOST_FUNC2_INT_ENA")
             .field(
                 "fn2_slc1_tohost_bit0_int_ena",
-                &format_args!("{}", self.fn2_slc1_tohost_bit0_int_ena().bit()),
+                &self.fn2_slc1_tohost_bit0_int_ena(),
             )
             .field(
                 "fn2_slc1_tohost_bit1_int_ena",
-                &format_args!("{}", self.fn2_slc1_tohost_bit1_int_ena().bit()),
+                &self.fn2_slc1_tohost_bit1_int_ena(),
             )
             .field(
                 "fn2_slc1_tohost_bit2_int_ena",
-                &format_args!("{}", self.fn2_slc1_tohost_bit2_int_ena().bit()),
+                &self.fn2_slc1_tohost_bit2_int_ena(),
             )
             .field(
                 "fn2_slc1_tohost_bit3_int_ena",
-                &format_args!("{}", self.fn2_slc1_tohost_bit3_int_ena().bit()),
+                &self.fn2_slc1_tohost_bit3_int_ena(),
             )
             .field(
                 "fn2_slc1_tohost_bit4_int_ena",
-                &format_args!("{}", self.fn2_slc1_tohost_bit4_int_ena().bit()),
+                &self.fn2_slc1_tohost_bit4_int_ena(),
             )
             .field(
                 "fn2_slc1_tohost_bit5_int_ena",
-                &format_args!("{}", self.fn2_slc1_tohost_bit5_int_ena().bit()),
+                &self.fn2_slc1_tohost_bit5_int_ena(),
             )
             .field(
                 "fn2_slc1_tohost_bit6_int_ena",
-                &format_args!("{}", self.fn2_slc1_tohost_bit6_int_ena().bit()),
+                &self.fn2_slc1_tohost_bit6_int_ena(),
             )
             .field(
                 "fn2_slc1_tohost_bit7_int_ena",
-                &format_args!("{}", self.fn2_slc1_tohost_bit7_int_ena().bit()),
+                &self.fn2_slc1_tohost_bit7_int_ena(),
             )
             .field(
                 "fn2_slc1_token0_1to0_int_ena",
-                &format_args!("{}", self.fn2_slc1_token0_1to0_int_ena().bit()),
+                &self.fn2_slc1_token0_1to0_int_ena(),
             )
             .field(
                 "fn2_slc1_token1_1to0_int_ena",
-                &format_args!("{}", self.fn2_slc1_token1_1to0_int_ena().bit()),
+                &self.fn2_slc1_token1_1to0_int_ena(),
             )
             .field(
                 "fn2_slc1_token0_0to1_int_ena",
-                &format_args!("{}", self.fn2_slc1_token0_0to1_int_ena().bit()),
+                &self.fn2_slc1_token0_0to1_int_ena(),
             )
             .field(
                 "fn2_slc1_token1_0to1_int_ena",
-                &format_args!("{}", self.fn2_slc1_token1_0to1_int_ena().bit()),
+                &self.fn2_slc1_token1_0to1_int_ena(),
             )
             .field(
                 "fn2_slc1host_rx_sof_int_ena",
-                &format_args!("{}", self.fn2_slc1host_rx_sof_int_ena().bit()),
+                &self.fn2_slc1host_rx_sof_int_ena(),
             )
             .field(
                 "fn2_slc1host_rx_eof_int_ena",
-                &format_args!("{}", self.fn2_slc1host_rx_eof_int_ena().bit()),
+                &self.fn2_slc1host_rx_eof_int_ena(),
             )
             .field(
                 "fn2_slc1host_rx_start_int_ena",
-                &format_args!("{}", self.fn2_slc1host_rx_start_int_ena().bit()),
+                &self.fn2_slc1host_rx_start_int_ena(),
             )
             .field(
                 "fn2_slc1host_tx_start_int_ena",
-                &format_args!("{}", self.fn2_slc1host_tx_start_int_ena().bit()),
-            )
-            .field(
-                "fn2_slc1_rx_udf_int_ena",
-                &format_args!("{}", self.fn2_slc1_rx_udf_int_ena().bit()),
-            )
-            .field(
-                "fn2_slc1_tx_ovf_int_ena",
-                &format_args!("{}", self.fn2_slc1_tx_ovf_int_ena().bit()),
+                &self.fn2_slc1host_tx_start_int_ena(),
             )
+            .field("fn2_slc1_rx_udf_int_ena", &self.fn2_slc1_rx_udf_int_ena())
+            .field("fn2_slc1_tx_ovf_int_ena", &self.fn2_slc1_tx_ovf_int_ena())
             .field(
                 "fn2_slc1_rx_pf_valid_int_ena",
-                &format_args!("{}", self.fn2_slc1_rx_pf_valid_int_ena().bit()),
+                &self.fn2_slc1_rx_pf_valid_int_ena(),
             )
             .field(
                 "fn2_slc1_ext_bit0_int_ena",
-                &format_args!("{}", self.fn2_slc1_ext_bit0_int_ena().bit()),
+                &self.fn2_slc1_ext_bit0_int_ena(),
             )
             .field(
                 "fn2_slc1_ext_bit1_int_ena",
-                &format_args!("{}", self.fn2_slc1_ext_bit1_int_ena().bit()),
+                &self.fn2_slc1_ext_bit1_int_ena(),
             )
             .field(
                 "fn2_slc1_ext_bit2_int_ena",
-                &format_args!("{}", self.fn2_slc1_ext_bit2_int_ena().bit()),
+                &self.fn2_slc1_ext_bit2_int_ena(),
             )
             .field(
                 "fn2_slc1_ext_bit3_int_ena",
-                &format_args!("{}", self.fn2_slc1_ext_bit3_int_ena().bit()),
+                &self.fn2_slc1_ext_bit3_int_ena(),
             )
             .field(
                 "fn2_slc1_wifi_rx_new_packet_int_ena",
-                &format_args!("{}", self.fn2_slc1_wifi_rx_new_packet_int_ena().bit()),
+                &self.fn2_slc1_wifi_rx_new_packet_int_ena(),
             )
             .field(
                 "fn2_slc1_host_rd_retry_int_ena",
-                &format_args!("{}", self.fn2_slc1_host_rd_retry_int_ena().bit()),
+                &self.fn2_slc1_host_rd_retry_int_ena(),
             )
             .field(
                 "fn2_slc1_bt_rx_new_packet_int_ena",
-                &format_args!("{}", self.fn2_slc1_bt_rx_new_packet_int_ena().bit()),
+                &self.fn2_slc1_bt_rx_new_packet_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC1HOST_FUNC2_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc1host_int_ena.rs b/esp32c6/src/slchost/slc1host_int_ena.rs
index 9d9d6af8d0..35176f5b5b 100644
--- a/esp32c6/src/slchost/slc1host_int_ena.rs
+++ b/esp32c6/src/slchost/slc1host_int_ena.rs
@@ -242,119 +242,50 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC1HOST_INT_ENA")
-            .field(
-                "slc1_tohost_bit0_int_ena",
-                &format_args!("{}", self.slc1_tohost_bit0_int_ena().bit()),
-            )
-            .field(
-                "slc1_tohost_bit1_int_ena",
-                &format_args!("{}", self.slc1_tohost_bit1_int_ena().bit()),
-            )
-            .field(
-                "slc1_tohost_bit2_int_ena",
-                &format_args!("{}", self.slc1_tohost_bit2_int_ena().bit()),
-            )
-            .field(
-                "slc1_tohost_bit3_int_ena",
-                &format_args!("{}", self.slc1_tohost_bit3_int_ena().bit()),
-            )
-            .field(
-                "slc1_tohost_bit4_int_ena",
-                &format_args!("{}", self.slc1_tohost_bit4_int_ena().bit()),
-            )
-            .field(
-                "slc1_tohost_bit5_int_ena",
-                &format_args!("{}", self.slc1_tohost_bit5_int_ena().bit()),
-            )
-            .field(
-                "slc1_tohost_bit6_int_ena",
-                &format_args!("{}", self.slc1_tohost_bit6_int_ena().bit()),
-            )
-            .field(
-                "slc1_tohost_bit7_int_ena",
-                &format_args!("{}", self.slc1_tohost_bit7_int_ena().bit()),
-            )
-            .field(
-                "slc1_token0_1to0_int_ena",
-                &format_args!("{}", self.slc1_token0_1to0_int_ena().bit()),
-            )
-            .field(
-                "slc1_token1_1to0_int_ena",
-                &format_args!("{}", self.slc1_token1_1to0_int_ena().bit()),
-            )
-            .field(
-                "slc1_token0_0to1_int_ena",
-                &format_args!("{}", self.slc1_token0_0to1_int_ena().bit()),
-            )
-            .field(
-                "slc1_token1_0to1_int_ena",
-                &format_args!("{}", self.slc1_token1_0to1_int_ena().bit()),
-            )
-            .field(
-                "slc1host_rx_sof_int_ena",
-                &format_args!("{}", self.slc1host_rx_sof_int_ena().bit()),
-            )
-            .field(
-                "slc1host_rx_eof_int_ena",
-                &format_args!("{}", self.slc1host_rx_eof_int_ena().bit()),
-            )
+            .field("slc1_tohost_bit0_int_ena", &self.slc1_tohost_bit0_int_ena())
+            .field("slc1_tohost_bit1_int_ena", &self.slc1_tohost_bit1_int_ena())
+            .field("slc1_tohost_bit2_int_ena", &self.slc1_tohost_bit2_int_ena())
+            .field("slc1_tohost_bit3_int_ena", &self.slc1_tohost_bit3_int_ena())
+            .field("slc1_tohost_bit4_int_ena", &self.slc1_tohost_bit4_int_ena())
+            .field("slc1_tohost_bit5_int_ena", &self.slc1_tohost_bit5_int_ena())
+            .field("slc1_tohost_bit6_int_ena", &self.slc1_tohost_bit6_int_ena())
+            .field("slc1_tohost_bit7_int_ena", &self.slc1_tohost_bit7_int_ena())
+            .field("slc1_token0_1to0_int_ena", &self.slc1_token0_1to0_int_ena())
+            .field("slc1_token1_1to0_int_ena", &self.slc1_token1_1to0_int_ena())
+            .field("slc1_token0_0to1_int_ena", &self.slc1_token0_0to1_int_ena())
+            .field("slc1_token1_0to1_int_ena", &self.slc1_token1_0to1_int_ena())
+            .field("slc1host_rx_sof_int_ena", &self.slc1host_rx_sof_int_ena())
+            .field("slc1host_rx_eof_int_ena", &self.slc1host_rx_eof_int_ena())
             .field(
                 "slc1host_rx_start_int_ena",
-                &format_args!("{}", self.slc1host_rx_start_int_ena().bit()),
+                &self.slc1host_rx_start_int_ena(),
             )
             .field(
                 "slc1host_tx_start_int_ena",
-                &format_args!("{}", self.slc1host_tx_start_int_ena().bit()),
-            )
-            .field(
-                "slc1_rx_udf_int_ena",
-                &format_args!("{}", self.slc1_rx_udf_int_ena().bit()),
-            )
-            .field(
-                "slc1_tx_ovf_int_ena",
-                &format_args!("{}", self.slc1_tx_ovf_int_ena().bit()),
-            )
-            .field(
-                "slc1_rx_pf_valid_int_ena",
-                &format_args!("{}", self.slc1_rx_pf_valid_int_ena().bit()),
-            )
-            .field(
-                "slc1_ext_bit0_int_ena",
-                &format_args!("{}", self.slc1_ext_bit0_int_ena().bit()),
-            )
-            .field(
-                "slc1_ext_bit1_int_ena",
-                &format_args!("{}", self.slc1_ext_bit1_int_ena().bit()),
-            )
-            .field(
-                "slc1_ext_bit2_int_ena",
-                &format_args!("{}", self.slc1_ext_bit2_int_ena().bit()),
-            )
-            .field(
-                "slc1_ext_bit3_int_ena",
-                &format_args!("{}", self.slc1_ext_bit3_int_ena().bit()),
+                &self.slc1host_tx_start_int_ena(),
             )
+            .field("slc1_rx_udf_int_ena", &self.slc1_rx_udf_int_ena())
+            .field("slc1_tx_ovf_int_ena", &self.slc1_tx_ovf_int_ena())
+            .field("slc1_rx_pf_valid_int_ena", &self.slc1_rx_pf_valid_int_ena())
+            .field("slc1_ext_bit0_int_ena", &self.slc1_ext_bit0_int_ena())
+            .field("slc1_ext_bit1_int_ena", &self.slc1_ext_bit1_int_ena())
+            .field("slc1_ext_bit2_int_ena", &self.slc1_ext_bit2_int_ena())
+            .field("slc1_ext_bit3_int_ena", &self.slc1_ext_bit3_int_ena())
             .field(
                 "slc1_wifi_rx_new_packet_int_ena",
-                &format_args!("{}", self.slc1_wifi_rx_new_packet_int_ena().bit()),
+                &self.slc1_wifi_rx_new_packet_int_ena(),
             )
             .field(
                 "slc1_host_rd_retry_int_ena",
-                &format_args!("{}", self.slc1_host_rd_retry_int_ena().bit()),
+                &self.slc1_host_rd_retry_int_ena(),
             )
             .field(
                 "slc1_bt_rx_new_packet_int_ena",
-                &format_args!("{}", self.slc1_bt_rx_new_packet_int_ena().bit()),
+                &self.slc1_bt_rx_new_packet_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC1HOST_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc1host_int_ena1.rs b/esp32c6/src/slchost/slc1host_int_ena1.rs
index e189187f15..bd07e5cb5e 100644
--- a/esp32c6/src/slchost/slc1host_int_ena1.rs
+++ b/esp32c6/src/slchost/slc1host_int_ena1.rs
@@ -244,117 +244,87 @@ impl core::fmt::Debug for R {
         f.debug_struct("SLC1HOST_INT_ENA1")
             .field(
                 "slc1_tohost_bit0_int_ena1",
-                &format_args!("{}", self.slc1_tohost_bit0_int_ena1().bit()),
+                &self.slc1_tohost_bit0_int_ena1(),
             )
             .field(
                 "slc1_tohost_bit1_int_ena1",
-                &format_args!("{}", self.slc1_tohost_bit1_int_ena1().bit()),
+                &self.slc1_tohost_bit1_int_ena1(),
             )
             .field(
                 "slc1_tohost_bit2_int_ena1",
-                &format_args!("{}", self.slc1_tohost_bit2_int_ena1().bit()),
+                &self.slc1_tohost_bit2_int_ena1(),
             )
             .field(
                 "slc1_tohost_bit3_int_ena1",
-                &format_args!("{}", self.slc1_tohost_bit3_int_ena1().bit()),
+                &self.slc1_tohost_bit3_int_ena1(),
             )
             .field(
                 "slc1_tohost_bit4_int_ena1",
-                &format_args!("{}", self.slc1_tohost_bit4_int_ena1().bit()),
+                &self.slc1_tohost_bit4_int_ena1(),
             )
             .field(
                 "slc1_tohost_bit5_int_ena1",
-                &format_args!("{}", self.slc1_tohost_bit5_int_ena1().bit()),
+                &self.slc1_tohost_bit5_int_ena1(),
             )
             .field(
                 "slc1_tohost_bit6_int_ena1",
-                &format_args!("{}", self.slc1_tohost_bit6_int_ena1().bit()),
+                &self.slc1_tohost_bit6_int_ena1(),
             )
             .field(
                 "slc1_tohost_bit7_int_ena1",
-                &format_args!("{}", self.slc1_tohost_bit7_int_ena1().bit()),
+                &self.slc1_tohost_bit7_int_ena1(),
             )
             .field(
                 "slc1_token0_1to0_int_ena1",
-                &format_args!("{}", self.slc1_token0_1to0_int_ena1().bit()),
+                &self.slc1_token0_1to0_int_ena1(),
             )
             .field(
                 "slc1_token1_1to0_int_ena1",
-                &format_args!("{}", self.slc1_token1_1to0_int_ena1().bit()),
+                &self.slc1_token1_1to0_int_ena1(),
             )
             .field(
                 "slc1_token0_0to1_int_ena1",
-                &format_args!("{}", self.slc1_token0_0to1_int_ena1().bit()),
+                &self.slc1_token0_0to1_int_ena1(),
             )
             .field(
                 "slc1_token1_0to1_int_ena1",
-                &format_args!("{}", self.slc1_token1_0to1_int_ena1().bit()),
-            )
-            .field(
-                "slc1host_rx_sof_int_ena1",
-                &format_args!("{}", self.slc1host_rx_sof_int_ena1().bit()),
-            )
-            .field(
-                "slc1host_rx_eof_int_ena1",
-                &format_args!("{}", self.slc1host_rx_eof_int_ena1().bit()),
+                &self.slc1_token1_0to1_int_ena1(),
             )
+            .field("slc1host_rx_sof_int_ena1", &self.slc1host_rx_sof_int_ena1())
+            .field("slc1host_rx_eof_int_ena1", &self.slc1host_rx_eof_int_ena1())
             .field(
                 "slc1host_rx_start_int_ena1",
-                &format_args!("{}", self.slc1host_rx_start_int_ena1().bit()),
+                &self.slc1host_rx_start_int_ena1(),
             )
             .field(
                 "slc1host_tx_start_int_ena1",
-                &format_args!("{}", self.slc1host_tx_start_int_ena1().bit()),
-            )
-            .field(
-                "slc1_rx_udf_int_ena1",
-                &format_args!("{}", self.slc1_rx_udf_int_ena1().bit()),
-            )
-            .field(
-                "slc1_tx_ovf_int_ena1",
-                &format_args!("{}", self.slc1_tx_ovf_int_ena1().bit()),
+                &self.slc1host_tx_start_int_ena1(),
             )
+            .field("slc1_rx_udf_int_ena1", &self.slc1_rx_udf_int_ena1())
+            .field("slc1_tx_ovf_int_ena1", &self.slc1_tx_ovf_int_ena1())
             .field(
                 "slc1_rx_pf_valid_int_ena1",
-                &format_args!("{}", self.slc1_rx_pf_valid_int_ena1().bit()),
-            )
-            .field(
-                "slc1_ext_bit0_int_ena1",
-                &format_args!("{}", self.slc1_ext_bit0_int_ena1().bit()),
-            )
-            .field(
-                "slc1_ext_bit1_int_ena1",
-                &format_args!("{}", self.slc1_ext_bit1_int_ena1().bit()),
-            )
-            .field(
-                "slc1_ext_bit2_int_ena1",
-                &format_args!("{}", self.slc1_ext_bit2_int_ena1().bit()),
-            )
-            .field(
-                "slc1_ext_bit3_int_ena1",
-                &format_args!("{}", self.slc1_ext_bit3_int_ena1().bit()),
+                &self.slc1_rx_pf_valid_int_ena1(),
             )
+            .field("slc1_ext_bit0_int_ena1", &self.slc1_ext_bit0_int_ena1())
+            .field("slc1_ext_bit1_int_ena1", &self.slc1_ext_bit1_int_ena1())
+            .field("slc1_ext_bit2_int_ena1", &self.slc1_ext_bit2_int_ena1())
+            .field("slc1_ext_bit3_int_ena1", &self.slc1_ext_bit3_int_ena1())
             .field(
                 "slc1_wifi_rx_new_packet_int_ena1",
-                &format_args!("{}", self.slc1_wifi_rx_new_packet_int_ena1().bit()),
+                &self.slc1_wifi_rx_new_packet_int_ena1(),
             )
             .field(
                 "slc1_host_rd_retry_int_ena1",
-                &format_args!("{}", self.slc1_host_rd_retry_int_ena1().bit()),
+                &self.slc1_host_rd_retry_int_ena1(),
             )
             .field(
                 "slc1_bt_rx_new_packet_int_ena1",
-                &format_args!("{}", self.slc1_bt_rx_new_packet_int_ena1().bit()),
+                &self.slc1_bt_rx_new_packet_int_ena1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC1HOST_INT_ENA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc1host_int_raw.rs b/esp32c6/src/slchost/slc1host_int_raw.rs
index 92224f7638..f773b425b4 100644
--- a/esp32c6/src/slchost/slc1host_int_raw.rs
+++ b/esp32c6/src/slchost/slc1host_int_raw.rs
@@ -242,119 +242,50 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC1HOST_INT_RAW")
-            .field(
-                "slc1_tohost_bit0_int_raw",
-                &format_args!("{}", self.slc1_tohost_bit0_int_raw().bit()),
-            )
-            .field(
-                "slc1_tohost_bit1_int_raw",
-                &format_args!("{}", self.slc1_tohost_bit1_int_raw().bit()),
-            )
-            .field(
-                "slc1_tohost_bit2_int_raw",
-                &format_args!("{}", self.slc1_tohost_bit2_int_raw().bit()),
-            )
-            .field(
-                "slc1_tohost_bit3_int_raw",
-                &format_args!("{}", self.slc1_tohost_bit3_int_raw().bit()),
-            )
-            .field(
-                "slc1_tohost_bit4_int_raw",
-                &format_args!("{}", self.slc1_tohost_bit4_int_raw().bit()),
-            )
-            .field(
-                "slc1_tohost_bit5_int_raw",
-                &format_args!("{}", self.slc1_tohost_bit5_int_raw().bit()),
-            )
-            .field(
-                "slc1_tohost_bit6_int_raw",
-                &format_args!("{}", self.slc1_tohost_bit6_int_raw().bit()),
-            )
-            .field(
-                "slc1_tohost_bit7_int_raw",
-                &format_args!("{}", self.slc1_tohost_bit7_int_raw().bit()),
-            )
-            .field(
-                "slc1_token0_1to0_int_raw",
-                &format_args!("{}", self.slc1_token0_1to0_int_raw().bit()),
-            )
-            .field(
-                "slc1_token1_1to0_int_raw",
-                &format_args!("{}", self.slc1_token1_1to0_int_raw().bit()),
-            )
-            .field(
-                "slc1_token0_0to1_int_raw",
-                &format_args!("{}", self.slc1_token0_0to1_int_raw().bit()),
-            )
-            .field(
-                "slc1_token1_0to1_int_raw",
-                &format_args!("{}", self.slc1_token1_0to1_int_raw().bit()),
-            )
-            .field(
-                "slc1host_rx_sof_int_raw",
-                &format_args!("{}", self.slc1host_rx_sof_int_raw().bit()),
-            )
-            .field(
-                "slc1host_rx_eof_int_raw",
-                &format_args!("{}", self.slc1host_rx_eof_int_raw().bit()),
-            )
+            .field("slc1_tohost_bit0_int_raw", &self.slc1_tohost_bit0_int_raw())
+            .field("slc1_tohost_bit1_int_raw", &self.slc1_tohost_bit1_int_raw())
+            .field("slc1_tohost_bit2_int_raw", &self.slc1_tohost_bit2_int_raw())
+            .field("slc1_tohost_bit3_int_raw", &self.slc1_tohost_bit3_int_raw())
+            .field("slc1_tohost_bit4_int_raw", &self.slc1_tohost_bit4_int_raw())
+            .field("slc1_tohost_bit5_int_raw", &self.slc1_tohost_bit5_int_raw())
+            .field("slc1_tohost_bit6_int_raw", &self.slc1_tohost_bit6_int_raw())
+            .field("slc1_tohost_bit7_int_raw", &self.slc1_tohost_bit7_int_raw())
+            .field("slc1_token0_1to0_int_raw", &self.slc1_token0_1to0_int_raw())
+            .field("slc1_token1_1to0_int_raw", &self.slc1_token1_1to0_int_raw())
+            .field("slc1_token0_0to1_int_raw", &self.slc1_token0_0to1_int_raw())
+            .field("slc1_token1_0to1_int_raw", &self.slc1_token1_0to1_int_raw())
+            .field("slc1host_rx_sof_int_raw", &self.slc1host_rx_sof_int_raw())
+            .field("slc1host_rx_eof_int_raw", &self.slc1host_rx_eof_int_raw())
             .field(
                 "slc1host_rx_start_int_raw",
-                &format_args!("{}", self.slc1host_rx_start_int_raw().bit()),
+                &self.slc1host_rx_start_int_raw(),
             )
             .field(
                 "slc1host_tx_start_int_raw",
-                &format_args!("{}", self.slc1host_tx_start_int_raw().bit()),
-            )
-            .field(
-                "slc1_rx_udf_int_raw",
-                &format_args!("{}", self.slc1_rx_udf_int_raw().bit()),
-            )
-            .field(
-                "slc1_tx_ovf_int_raw",
-                &format_args!("{}", self.slc1_tx_ovf_int_raw().bit()),
-            )
-            .field(
-                "slc1_rx_pf_valid_int_raw",
-                &format_args!("{}", self.slc1_rx_pf_valid_int_raw().bit()),
-            )
-            .field(
-                "slc1_ext_bit0_int_raw",
-                &format_args!("{}", self.slc1_ext_bit0_int_raw().bit()),
-            )
-            .field(
-                "slc1_ext_bit1_int_raw",
-                &format_args!("{}", self.slc1_ext_bit1_int_raw().bit()),
-            )
-            .field(
-                "slc1_ext_bit2_int_raw",
-                &format_args!("{}", self.slc1_ext_bit2_int_raw().bit()),
-            )
-            .field(
-                "slc1_ext_bit3_int_raw",
-                &format_args!("{}", self.slc1_ext_bit3_int_raw().bit()),
+                &self.slc1host_tx_start_int_raw(),
             )
+            .field("slc1_rx_udf_int_raw", &self.slc1_rx_udf_int_raw())
+            .field("slc1_tx_ovf_int_raw", &self.slc1_tx_ovf_int_raw())
+            .field("slc1_rx_pf_valid_int_raw", &self.slc1_rx_pf_valid_int_raw())
+            .field("slc1_ext_bit0_int_raw", &self.slc1_ext_bit0_int_raw())
+            .field("slc1_ext_bit1_int_raw", &self.slc1_ext_bit1_int_raw())
+            .field("slc1_ext_bit2_int_raw", &self.slc1_ext_bit2_int_raw())
+            .field("slc1_ext_bit3_int_raw", &self.slc1_ext_bit3_int_raw())
             .field(
                 "slc1_wifi_rx_new_packet_int_raw",
-                &format_args!("{}", self.slc1_wifi_rx_new_packet_int_raw().bit()),
+                &self.slc1_wifi_rx_new_packet_int_raw(),
             )
             .field(
                 "slc1_host_rd_retry_int_raw",
-                &format_args!("{}", self.slc1_host_rd_retry_int_raw().bit()),
+                &self.slc1_host_rd_retry_int_raw(),
             )
             .field(
                 "slc1_bt_rx_new_packet_int_raw",
-                &format_args!("{}", self.slc1_bt_rx_new_packet_int_raw().bit()),
+                &self.slc1_bt_rx_new_packet_int_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC1HOST_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc1host_int_st.rs b/esp32c6/src/slchost/slc1host_int_st.rs
index abc9c74d70..6694f770f3 100644
--- a/esp32c6/src/slchost/slc1host_int_st.rs
+++ b/esp32c6/src/slchost/slc1host_int_st.rs
@@ -188,119 +188,44 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC1HOST_INT_ST")
-            .field(
-                "slc1_tohost_bit0_int_st",
-                &format_args!("{}", self.slc1_tohost_bit0_int_st().bit()),
-            )
-            .field(
-                "slc1_tohost_bit1_int_st",
-                &format_args!("{}", self.slc1_tohost_bit1_int_st().bit()),
-            )
-            .field(
-                "slc1_tohost_bit2_int_st",
-                &format_args!("{}", self.slc1_tohost_bit2_int_st().bit()),
-            )
-            .field(
-                "slc1_tohost_bit3_int_st",
-                &format_args!("{}", self.slc1_tohost_bit3_int_st().bit()),
-            )
-            .field(
-                "slc1_tohost_bit4_int_st",
-                &format_args!("{}", self.slc1_tohost_bit4_int_st().bit()),
-            )
-            .field(
-                "slc1_tohost_bit5_int_st",
-                &format_args!("{}", self.slc1_tohost_bit5_int_st().bit()),
-            )
-            .field(
-                "slc1_tohost_bit6_int_st",
-                &format_args!("{}", self.slc1_tohost_bit6_int_st().bit()),
-            )
-            .field(
-                "slc1_tohost_bit7_int_st",
-                &format_args!("{}", self.slc1_tohost_bit7_int_st().bit()),
-            )
-            .field(
-                "slc1_token0_1to0_int_st",
-                &format_args!("{}", self.slc1_token0_1to0_int_st().bit()),
-            )
-            .field(
-                "slc1_token1_1to0_int_st",
-                &format_args!("{}", self.slc1_token1_1to0_int_st().bit()),
-            )
-            .field(
-                "slc1_token0_0to1_int_st",
-                &format_args!("{}", self.slc1_token0_0to1_int_st().bit()),
-            )
-            .field(
-                "slc1_token1_0to1_int_st",
-                &format_args!("{}", self.slc1_token1_0to1_int_st().bit()),
-            )
-            .field(
-                "slc1host_rx_sof_int_st",
-                &format_args!("{}", self.slc1host_rx_sof_int_st().bit()),
-            )
-            .field(
-                "slc1host_rx_eof_int_st",
-                &format_args!("{}", self.slc1host_rx_eof_int_st().bit()),
-            )
-            .field(
-                "slc1host_rx_start_int_st",
-                &format_args!("{}", self.slc1host_rx_start_int_st().bit()),
-            )
-            .field(
-                "slc1host_tx_start_int_st",
-                &format_args!("{}", self.slc1host_tx_start_int_st().bit()),
-            )
-            .field(
-                "slc1_rx_udf_int_st",
-                &format_args!("{}", self.slc1_rx_udf_int_st().bit()),
-            )
-            .field(
-                "slc1_tx_ovf_int_st",
-                &format_args!("{}", self.slc1_tx_ovf_int_st().bit()),
-            )
-            .field(
-                "slc1_rx_pf_valid_int_st",
-                &format_args!("{}", self.slc1_rx_pf_valid_int_st().bit()),
-            )
-            .field(
-                "slc1_ext_bit0_int_st",
-                &format_args!("{}", self.slc1_ext_bit0_int_st().bit()),
-            )
-            .field(
-                "slc1_ext_bit1_int_st",
-                &format_args!("{}", self.slc1_ext_bit1_int_st().bit()),
-            )
-            .field(
-                "slc1_ext_bit2_int_st",
-                &format_args!("{}", self.slc1_ext_bit2_int_st().bit()),
-            )
-            .field(
-                "slc1_ext_bit3_int_st",
-                &format_args!("{}", self.slc1_ext_bit3_int_st().bit()),
-            )
+            .field("slc1_tohost_bit0_int_st", &self.slc1_tohost_bit0_int_st())
+            .field("slc1_tohost_bit1_int_st", &self.slc1_tohost_bit1_int_st())
+            .field("slc1_tohost_bit2_int_st", &self.slc1_tohost_bit2_int_st())
+            .field("slc1_tohost_bit3_int_st", &self.slc1_tohost_bit3_int_st())
+            .field("slc1_tohost_bit4_int_st", &self.slc1_tohost_bit4_int_st())
+            .field("slc1_tohost_bit5_int_st", &self.slc1_tohost_bit5_int_st())
+            .field("slc1_tohost_bit6_int_st", &self.slc1_tohost_bit6_int_st())
+            .field("slc1_tohost_bit7_int_st", &self.slc1_tohost_bit7_int_st())
+            .field("slc1_token0_1to0_int_st", &self.slc1_token0_1to0_int_st())
+            .field("slc1_token1_1to0_int_st", &self.slc1_token1_1to0_int_st())
+            .field("slc1_token0_0to1_int_st", &self.slc1_token0_0to1_int_st())
+            .field("slc1_token1_0to1_int_st", &self.slc1_token1_0to1_int_st())
+            .field("slc1host_rx_sof_int_st", &self.slc1host_rx_sof_int_st())
+            .field("slc1host_rx_eof_int_st", &self.slc1host_rx_eof_int_st())
+            .field("slc1host_rx_start_int_st", &self.slc1host_rx_start_int_st())
+            .field("slc1host_tx_start_int_st", &self.slc1host_tx_start_int_st())
+            .field("slc1_rx_udf_int_st", &self.slc1_rx_udf_int_st())
+            .field("slc1_tx_ovf_int_st", &self.slc1_tx_ovf_int_st())
+            .field("slc1_rx_pf_valid_int_st", &self.slc1_rx_pf_valid_int_st())
+            .field("slc1_ext_bit0_int_st", &self.slc1_ext_bit0_int_st())
+            .field("slc1_ext_bit1_int_st", &self.slc1_ext_bit1_int_st())
+            .field("slc1_ext_bit2_int_st", &self.slc1_ext_bit2_int_st())
+            .field("slc1_ext_bit3_int_st", &self.slc1_ext_bit3_int_st())
             .field(
                 "slc1_wifi_rx_new_packet_int_st",
-                &format_args!("{}", self.slc1_wifi_rx_new_packet_int_st().bit()),
+                &self.slc1_wifi_rx_new_packet_int_st(),
             )
             .field(
                 "slc1_host_rd_retry_int_st",
-                &format_args!("{}", self.slc1_host_rd_retry_int_st().bit()),
+                &self.slc1_host_rd_retry_int_st(),
             )
             .field(
                 "slc1_bt_rx_new_packet_int_st",
-                &format_args!("{}", self.slc1_bt_rx_new_packet_int_st().bit()),
+                &self.slc1_bt_rx_new_packet_int_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC1HOST_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc1host_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLC1HOST_INT_ST_SPEC;
 impl crate::RegisterSpec for SLC1HOST_INT_ST_SPEC {
diff --git a/esp32c6/src/slchost/slc1host_rx_infor.rs b/esp32c6/src/slchost/slc1host_rx_infor.rs
index 917317e536..5e0ecb905f 100644
--- a/esp32c6/src/slchost/slc1host_rx_infor.rs
+++ b/esp32c6/src/slchost/slc1host_rx_infor.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC1HOST_RX_INFOR")
-            .field(
-                "slc1host_rx_infor",
-                &format_args!("{}", self.slc1host_rx_infor().bits()),
-            )
+            .field("slc1host_rx_infor", &self.slc1host_rx_infor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC1HOST_RX_INFOR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc1host_token_rdata.rs b/esp32c6/src/slchost/slc1host_token_rdata.rs
index c05a95f4fd..feaf90fd33 100644
--- a/esp32c6/src/slchost/slc1host_token_rdata.rs
+++ b/esp32c6/src/slchost/slc1host_token_rdata.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC1HOST_TOKEN_RDATA")
-            .field(
-                "slc1_token0",
-                &format_args!("{}", self.slc1_token0().bits()),
-            )
-            .field(
-                "slc1_rx_pf_valid",
-                &format_args!("{}", self.slc1_rx_pf_valid().bit()),
-            )
-            .field(
-                "hostslchost_slc1_token1",
-                &format_args!("{}", self.hostslchost_slc1_token1().bits()),
-            )
-            .field(
-                "slc1_rx_pf_eof",
-                &format_args!("{}", self.slc1_rx_pf_eof().bits()),
-            )
+            .field("slc1_token0", &self.slc1_token0())
+            .field("slc1_rx_pf_valid", &self.slc1_rx_pf_valid())
+            .field("hostslchost_slc1_token1", &self.hostslchost_slc1_token1())
+            .field("slc1_rx_pf_eof", &self.slc1_rx_pf_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC1HOST_TOKEN_RDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc1host_token_rdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLC1HOST_TOKEN_RDATA_SPEC;
 impl crate::RegisterSpec for SLC1HOST_TOKEN_RDATA_SPEC {
diff --git a/esp32c6/src/slchost/slc1host_token_wdata.rs b/esp32c6/src/slchost/slc1host_token_wdata.rs
index 9904c2fec2..76d9318dcd 100644
--- a/esp32c6/src/slchost/slc1host_token_wdata.rs
+++ b/esp32c6/src/slchost/slc1host_token_wdata.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC1HOST_TOKEN_WDATA")
-            .field(
-                "slc1host_token0_wd",
-                &format_args!("{}", self.slc1host_token0_wd().bits()),
-            )
-            .field(
-                "slc1host_token1_wd",
-                &format_args!("{}", self.slc1host_token1_wd().bits()),
-            )
+            .field("slc1host_token0_wd", &self.slc1host_token0_wd())
+            .field("slc1host_token1_wd", &self.slc1host_token1_wd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC1HOST_TOKEN_WDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc_apbwin_conf.rs b/esp32c6/src/slchost/slc_apbwin_conf.rs
index 5d88d67284..46f1de7357 100644
--- a/esp32c6/src/slchost/slc_apbwin_conf.rs
+++ b/esp32c6/src/slchost/slc_apbwin_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC_APBWIN_CONF")
-            .field(
-                "slc_apbwin_addr",
-                &format_args!("{}", self.slc_apbwin_addr().bits()),
-            )
-            .field(
-                "slc_apbwin_wr",
-                &format_args!("{}", self.slc_apbwin_wr().bit()),
-            )
-            .field(
-                "slc_apbwin_start",
-                &format_args!("{}", self.slc_apbwin_start().bit()),
-            )
+            .field("slc_apbwin_addr", &self.slc_apbwin_addr())
+            .field("slc_apbwin_wr", &self.slc_apbwin_wr())
+            .field("slc_apbwin_start", &self.slc_apbwin_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC_APBWIN_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slc_apbwin_rdata.rs b/esp32c6/src/slchost/slc_apbwin_rdata.rs
index f76dc1308a..b0c8a584b6 100644
--- a/esp32c6/src/slchost/slc_apbwin_rdata.rs
+++ b/esp32c6/src/slchost/slc_apbwin_rdata.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC_APBWIN_RDATA")
-            .field(
-                "slc_apbwin_rdata",
-                &format_args!("{}", self.slc_apbwin_rdata().bits()),
-            )
+            .field("slc_apbwin_rdata", &self.slc_apbwin_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC_APBWIN_RDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slc_apbwin_rdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLC_APBWIN_RDATA_SPEC;
 impl crate::RegisterSpec for SLC_APBWIN_RDATA_SPEC {
diff --git a/esp32c6/src/slchost/slc_apbwin_wdata.rs b/esp32c6/src/slchost/slc_apbwin_wdata.rs
index 57d8f4f1fa..f345b2bf50 100644
--- a/esp32c6/src/slchost/slc_apbwin_wdata.rs
+++ b/esp32c6/src/slchost/slc_apbwin_wdata.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC_APBWIN_WDATA")
-            .field(
-                "slc_apbwin_wdata",
-                &format_args!("{}", self.slc_apbwin_wdata().bits()),
-            )
+            .field("slc_apbwin_wdata", &self.slc_apbwin_wdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC_APBWIN_WDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slchostdate.rs b/esp32c6/src/slchost/slchostdate.rs
index c35449d797..d69170e5d7 100644
--- a/esp32c6/src/slchost/slchostdate.rs
+++ b/esp32c6/src/slchost/slchostdate.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLCHOSTDATE")
-            .field(
-                "slchost_date",
-                &format_args!("{}", self.slchost_date().bits()),
-            )
+            .field("slchost_date", &self.slchost_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLCHOSTDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/slchostid.rs b/esp32c6/src/slchost/slchostid.rs
index e08e7d680c..9082907983 100644
--- a/esp32c6/src/slchost/slchostid.rs
+++ b/esp32c6/src/slchost/slchostid.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLCHOSTID")
-            .field("slchost_id", &format_args!("{}", self.slchost_id().bits()))
+            .field("slchost_id", &self.slchost_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLCHOSTID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/slchost/state_w0.rs b/esp32c6/src/slchost/state_w0.rs
index 0e0a1908b4..e62e7f4f09 100644
--- a/esp32c6/src/slchost/state_w0.rs
+++ b/esp32c6/src/slchost/state_w0.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE_W0")
-            .field(
-                "slchost_state0",
-                &format_args!("{}", self.slchost_state0().bits()),
-            )
-            .field(
-                "slchost_state1",
-                &format_args!("{}", self.slchost_state1().bits()),
-            )
-            .field(
-                "slchost_state2",
-                &format_args!("{}", self.slchost_state2().bits()),
-            )
-            .field(
-                "slchost_state3",
-                &format_args!("{}", self.slchost_state3().bits()),
-            )
+            .field("slchost_state0", &self.slchost_state0())
+            .field("slchost_state1", &self.slchost_state1())
+            .field("slchost_state2", &self.slchost_state2())
+            .field("slchost_state3", &self.slchost_state3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_W0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state_w0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_W0_SPEC;
 impl crate::RegisterSpec for STATE_W0_SPEC {
diff --git a/esp32c6/src/slchost/state_w1.rs b/esp32c6/src/slchost/state_w1.rs
index c7380391d5..99cc506958 100644
--- a/esp32c6/src/slchost/state_w1.rs
+++ b/esp32c6/src/slchost/state_w1.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE_W1")
-            .field(
-                "slchost_state4",
-                &format_args!("{}", self.slchost_state4().bits()),
-            )
-            .field(
-                "slchost_state5",
-                &format_args!("{}", self.slchost_state5().bits()),
-            )
-            .field(
-                "slchost_state6",
-                &format_args!("{}", self.slchost_state6().bits()),
-            )
-            .field(
-                "slchost_state7",
-                &format_args!("{}", self.slchost_state7().bits()),
-            )
+            .field("slchost_state4", &self.slchost_state4())
+            .field("slchost_state5", &self.slchost_state5())
+            .field("slchost_state6", &self.slchost_state6())
+            .field("slchost_state7", &self.slchost_state7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "*******Description***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_W1_SPEC;
 impl crate::RegisterSpec for STATE_W1_SPEC {
diff --git a/esp32c6/src/slchost/win_cmd.rs b/esp32c6/src/slchost/win_cmd.rs
index 681c7fd288..03198cea0d 100644
--- a/esp32c6/src/slchost/win_cmd.rs
+++ b/esp32c6/src/slchost/win_cmd.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIN_CMD")
-            .field(
-                "slchost_win_cmd",
-                &format_args!("{}", self.slchost_win_cmd().bits()),
-            )
+            .field("slchost_win_cmd", &self.slchost_win_cmd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIN_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - *******Description***********"]
     #[inline(always)]
diff --git a/esp32c6/src/soc_etm/ch/evt_id.rs b/esp32c6/src/soc_etm/ch/evt_id.rs
index 0835c04224..20e43e78e9 100644
--- a/esp32c6/src/soc_etm/ch/evt_id.rs
+++ b/esp32c6/src/soc_etm/ch/evt_id.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVT_ID")
-            .field("evt_id", &format_args!("{}", self.evt_id().bits()))
+            .field("evt_id", &self.evt_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - ch0_evt_id"]
     #[inline(always)]
diff --git a/esp32c6/src/soc_etm/ch/task_id.rs b/esp32c6/src/soc_etm/ch/task_id.rs
index d59784f09b..e4f4ed148a 100644
--- a/esp32c6/src/soc_etm/ch/task_id.rs
+++ b/esp32c6/src/soc_etm/ch/task_id.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TASK_ID")
-            .field("task_id", &format_args!("{}", self.task_id().bits()))
+            .field("task_id", &self.task_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TASK_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - ch0_task_id"]
     #[inline(always)]
diff --git a/esp32c6/src/soc_etm/ch_ena_ad0.rs b/esp32c6/src/soc_etm/ch_ena_ad0.rs
index 562f39333c..00481c5e06 100644
--- a/esp32c6/src/soc_etm/ch_ena_ad0.rs
+++ b/esp32c6/src/soc_etm/ch_ena_ad0.rs
@@ -187,47 +187,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_ENA_AD0")
-            .field("ch_ena0", &format_args!("{}", self.ch_ena0().bit()))
-            .field("ch_ena1", &format_args!("{}", self.ch_ena1().bit()))
-            .field("ch_ena2", &format_args!("{}", self.ch_ena2().bit()))
-            .field("ch_ena3", &format_args!("{}", self.ch_ena3().bit()))
-            .field("ch_ena4", &format_args!("{}", self.ch_ena4().bit()))
-            .field("ch_ena5", &format_args!("{}", self.ch_ena5().bit()))
-            .field("ch_ena6", &format_args!("{}", self.ch_ena6().bit()))
-            .field("ch_ena7", &format_args!("{}", self.ch_ena7().bit()))
-            .field("ch_ena8", &format_args!("{}", self.ch_ena8().bit()))
-            .field("ch_ena9", &format_args!("{}", self.ch_ena9().bit()))
-            .field("ch_ena10", &format_args!("{}", self.ch_ena10().bit()))
-            .field("ch_ena11", &format_args!("{}", self.ch_ena11().bit()))
-            .field("ch_ena12", &format_args!("{}", self.ch_ena12().bit()))
-            .field("ch_ena13", &format_args!("{}", self.ch_ena13().bit()))
-            .field("ch_ena14", &format_args!("{}", self.ch_ena14().bit()))
-            .field("ch_ena15", &format_args!("{}", self.ch_ena15().bit()))
-            .field("ch_ena16", &format_args!("{}", self.ch_ena16().bit()))
-            .field("ch_ena17", &format_args!("{}", self.ch_ena17().bit()))
-            .field("ch_ena18", &format_args!("{}", self.ch_ena18().bit()))
-            .field("ch_ena19", &format_args!("{}", self.ch_ena19().bit()))
-            .field("ch_ena20", &format_args!("{}", self.ch_ena20().bit()))
-            .field("ch_ena21", &format_args!("{}", self.ch_ena21().bit()))
-            .field("ch_ena22", &format_args!("{}", self.ch_ena22().bit()))
-            .field("ch_ena23", &format_args!("{}", self.ch_ena23().bit()))
-            .field("ch_ena24", &format_args!("{}", self.ch_ena24().bit()))
-            .field("ch_ena25", &format_args!("{}", self.ch_ena25().bit()))
-            .field("ch_ena26", &format_args!("{}", self.ch_ena26().bit()))
-            .field("ch_ena27", &format_args!("{}", self.ch_ena27().bit()))
-            .field("ch_ena28", &format_args!("{}", self.ch_ena28().bit()))
-            .field("ch_ena29", &format_args!("{}", self.ch_ena29().bit()))
-            .field("ch_ena30", &format_args!("{}", self.ch_ena30().bit()))
-            .field("ch_ena31", &format_args!("{}", self.ch_ena31().bit()))
+            .field("ch_ena0", &self.ch_ena0())
+            .field("ch_ena1", &self.ch_ena1())
+            .field("ch_ena2", &self.ch_ena2())
+            .field("ch_ena3", &self.ch_ena3())
+            .field("ch_ena4", &self.ch_ena4())
+            .field("ch_ena5", &self.ch_ena5())
+            .field("ch_ena6", &self.ch_ena6())
+            .field("ch_ena7", &self.ch_ena7())
+            .field("ch_ena8", &self.ch_ena8())
+            .field("ch_ena9", &self.ch_ena9())
+            .field("ch_ena10", &self.ch_ena10())
+            .field("ch_ena11", &self.ch_ena11())
+            .field("ch_ena12", &self.ch_ena12())
+            .field("ch_ena13", &self.ch_ena13())
+            .field("ch_ena14", &self.ch_ena14())
+            .field("ch_ena15", &self.ch_ena15())
+            .field("ch_ena16", &self.ch_ena16())
+            .field("ch_ena17", &self.ch_ena17())
+            .field("ch_ena18", &self.ch_ena18())
+            .field("ch_ena19", &self.ch_ena19())
+            .field("ch_ena20", &self.ch_ena20())
+            .field("ch_ena21", &self.ch_ena21())
+            .field("ch_ena22", &self.ch_ena22())
+            .field("ch_ena23", &self.ch_ena23())
+            .field("ch_ena24", &self.ch_ena24())
+            .field("ch_ena25", &self.ch_ena25())
+            .field("ch_ena26", &self.ch_ena26())
+            .field("ch_ena27", &self.ch_ena27())
+            .field("ch_ena28", &self.ch_ena28())
+            .field("ch_ena29", &self.ch_ena29())
+            .field("ch_ena30", &self.ch_ena30())
+            .field("ch_ena31", &self.ch_ena31())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_ENA_AD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "ch(0-31) enable"]
     #[doc = ""]
diff --git a/esp32c6/src/soc_etm/ch_ena_ad1.rs b/esp32c6/src/soc_etm/ch_ena_ad1.rs
index 81e2dc0d87..b25116a051 100644
--- a/esp32c6/src/soc_etm/ch_ena_ad1.rs
+++ b/esp32c6/src/soc_etm/ch_ena_ad1.rs
@@ -117,33 +117,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_ENA_AD1")
-            .field("ch_ena32", &format_args!("{}", self.ch_ena32().bit()))
-            .field("ch_ena33", &format_args!("{}", self.ch_ena33().bit()))
-            .field("ch_ena34", &format_args!("{}", self.ch_ena34().bit()))
-            .field("ch_ena35", &format_args!("{}", self.ch_ena35().bit()))
-            .field("ch_ena36", &format_args!("{}", self.ch_ena36().bit()))
-            .field("ch_ena37", &format_args!("{}", self.ch_ena37().bit()))
-            .field("ch_ena38", &format_args!("{}", self.ch_ena38().bit()))
-            .field("ch_ena39", &format_args!("{}", self.ch_ena39().bit()))
-            .field("ch_ena40", &format_args!("{}", self.ch_ena40().bit()))
-            .field("ch_ena41", &format_args!("{}", self.ch_ena41().bit()))
-            .field("ch_ena42", &format_args!("{}", self.ch_ena42().bit()))
-            .field("ch_ena43", &format_args!("{}", self.ch_ena43().bit()))
-            .field("ch_ena44", &format_args!("{}", self.ch_ena44().bit()))
-            .field("ch_ena45", &format_args!("{}", self.ch_ena45().bit()))
-            .field("ch_ena46", &format_args!("{}", self.ch_ena46().bit()))
-            .field("ch_ena47", &format_args!("{}", self.ch_ena47().bit()))
-            .field("ch_ena48", &format_args!("{}", self.ch_ena48().bit()))
-            .field("ch_ena49", &format_args!("{}", self.ch_ena49().bit()))
+            .field("ch_ena32", &self.ch_ena32())
+            .field("ch_ena33", &self.ch_ena33())
+            .field("ch_ena34", &self.ch_ena34())
+            .field("ch_ena35", &self.ch_ena35())
+            .field("ch_ena36", &self.ch_ena36())
+            .field("ch_ena37", &self.ch_ena37())
+            .field("ch_ena38", &self.ch_ena38())
+            .field("ch_ena39", &self.ch_ena39())
+            .field("ch_ena40", &self.ch_ena40())
+            .field("ch_ena41", &self.ch_ena41())
+            .field("ch_ena42", &self.ch_ena42())
+            .field("ch_ena43", &self.ch_ena43())
+            .field("ch_ena44", &self.ch_ena44())
+            .field("ch_ena45", &self.ch_ena45())
+            .field("ch_ena46", &self.ch_ena46())
+            .field("ch_ena47", &self.ch_ena47())
+            .field("ch_ena48", &self.ch_ena48())
+            .field("ch_ena49", &self.ch_ena49())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_ENA_AD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "ch(32-49) enable"]
     #[doc = ""]
diff --git a/esp32c6/src/soc_etm/clk_en.rs b/esp32c6/src/soc_etm/clk_en.rs
index 5275163e95..939c6095e7 100644
--- a/esp32c6/src/soc_etm/clk_en.rs
+++ b/esp32c6/src/soc_etm/clk_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EN")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - clock enable"]
     #[inline(always)]
diff --git a/esp32c6/src/soc_etm/date.rs b/esp32c6/src/soc_etm/date.rs
index dbea0ac5e8..02f22a3bad 100644
--- a/esp32c6/src/soc_etm/date.rs
+++ b/esp32c6/src/soc_etm/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/spi0/axi_err_addr.rs b/esp32c6/src/spi0/axi_err_addr.rs
index 9561f5ebcc..cdc77ddb01 100644
--- a/esp32c6/src/spi0/axi_err_addr.rs
+++ b/esp32c6/src/spi0/axi_err_addr.rs
@@ -55,43 +55,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AXI_ERR_ADDR")
-            .field(
-                "axi_err_addr",
-                &format_args!("{}", self.axi_err_addr().bits()),
-            )
-            .field(
-                "all_fifo_empty",
-                &format_args!("{}", self.all_fifo_empty().bit()),
-            )
-            .field(
-                "spi_rdata_afifo_rempty",
-                &format_args!("{}", self.spi_rdata_afifo_rempty().bit()),
-            )
-            .field(
-                "spi_raddr_afifo_rempty",
-                &format_args!("{}", self.spi_raddr_afifo_rempty().bit()),
-            )
-            .field(
-                "spi_wdata_afifo_rempty",
-                &format_args!("{}", self.spi_wdata_afifo_rempty().bit()),
-            )
-            .field(
-                "spi_wblen_afifo_rempty",
-                &format_args!("{}", self.spi_wblen_afifo_rempty().bit()),
-            )
+            .field("axi_err_addr", &self.axi_err_addr())
+            .field("all_fifo_empty", &self.all_fifo_empty())
+            .field("spi_rdata_afifo_rempty", &self.spi_rdata_afifo_rempty())
+            .field("spi_raddr_afifo_rempty", &self.spi_raddr_afifo_rempty())
+            .field("spi_wdata_afifo_rempty", &self.spi_wdata_afifo_rempty())
+            .field("spi_wblen_afifo_rempty", &self.spi_wblen_afifo_rempty())
             .field(
                 "spi_all_axi_trans_afifo_empty",
-                &format_args!("{}", self.spi_all_axi_trans_afifo_empty().bit()),
+                &self.spi_all_axi_trans_afifo_empty(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_ERR_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 AXI request error address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_err_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AXI_ERR_ADDR_SPEC;
 impl crate::RegisterSpec for AXI_ERR_ADDR_SPEC {
diff --git a/esp32c6/src/spi0/cache_fctrl.rs b/esp32c6/src/spi0/cache_fctrl.rs
index 02807bcced..ab183e09a4 100644
--- a/esp32c6/src/spi0/cache_fctrl.rs
+++ b/esp32c6/src/spi0/cache_fctrl.rs
@@ -105,38 +105,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_FCTRL")
-            .field("axi_req_en", &format_args!("{}", self.axi_req_en().bit()))
-            .field(
-                "cache_usr_addr_4byte",
-                &format_args!("{}", self.cache_usr_addr_4byte().bit()),
-            )
-            .field(
-                "cache_flash_usr_cmd",
-                &format_args!("{}", self.cache_flash_usr_cmd().bit()),
-            )
-            .field("fdin_dual", &format_args!("{}", self.fdin_dual().bit()))
-            .field("fdout_dual", &format_args!("{}", self.fdout_dual().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("fdin_quad", &format_args!("{}", self.fdin_quad().bit()))
-            .field("fdout_quad", &format_args!("{}", self.fdout_quad().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
+            .field("axi_req_en", &self.axi_req_en())
+            .field("cache_usr_addr_4byte", &self.cache_usr_addr_4byte())
+            .field("cache_flash_usr_cmd", &self.cache_flash_usr_cmd())
+            .field("fdin_dual", &self.fdin_dual())
+            .field("fdout_dual", &self.fdout_dual())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("fdin_quad", &self.fdin_quad())
+            .field("fdout_quad", &self.fdout_quad())
+            .field("faddr_quad", &self.faddr_quad())
             .field(
                 "spi_same_aw_ar_addr_chk_en",
-                &format_args!("{}", self.spi_same_aw_ar_addr_chk_en().bit()),
-            )
-            .field(
-                "spi_close_axi_inf_en",
-                &format_args!("{}", self.spi_close_axi_inf_en().bit()),
+                &self.spi_same_aw_ar_addr_chk_en(),
             )
+            .field("spi_close_axi_inf_en", &self.spi_close_axi_inf_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_FCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - For SPI0, AXI master access enable, 1: enable, 0:disable."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/cache_sctrl.rs b/esp32c6/src/spi0/cache_sctrl.rs
index f1dd755783..62f6a51682 100644
--- a/esp32c6/src/spi0/cache_sctrl.rs
+++ b/esp32c6/src/spi0/cache_sctrl.rs
@@ -83,56 +83,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_SCTRL")
-            .field(
-                "cache_usr_saddr_4byte",
-                &format_args!("{}", self.cache_usr_saddr_4byte().bit()),
-            )
-            .field(
-                "usr_sram_dio",
-                &format_args!("{}", self.usr_sram_dio().bit()),
-            )
-            .field(
-                "usr_sram_qio",
-                &format_args!("{}", self.usr_sram_qio().bit()),
-            )
-            .field(
-                "usr_wr_sram_dummy",
-                &format_args!("{}", self.usr_wr_sram_dummy().bit()),
-            )
-            .field(
-                "usr_rd_sram_dummy",
-                &format_args!("{}", self.usr_rd_sram_dummy().bit()),
-            )
-            .field(
-                "cache_sram_usr_rcmd",
-                &format_args!("{}", self.cache_sram_usr_rcmd().bit()),
-            )
-            .field(
-                "sram_rdummy_cyclelen",
-                &format_args!("{}", self.sram_rdummy_cyclelen().bits()),
-            )
-            .field(
-                "sram_addr_bitlen",
-                &format_args!("{}", self.sram_addr_bitlen().bits()),
-            )
-            .field(
-                "cache_sram_usr_wcmd",
-                &format_args!("{}", self.cache_sram_usr_wcmd().bit()),
-            )
-            .field("sram_oct", &format_args!("{}", self.sram_oct().bit()))
-            .field(
-                "sram_wdummy_cyclelen",
-                &format_args!("{}", self.sram_wdummy_cyclelen().bits()),
-            )
+            .field("cache_usr_saddr_4byte", &self.cache_usr_saddr_4byte())
+            .field("usr_sram_dio", &self.usr_sram_dio())
+            .field("usr_sram_qio", &self.usr_sram_qio())
+            .field("usr_wr_sram_dummy", &self.usr_wr_sram_dummy())
+            .field("usr_rd_sram_dummy", &self.usr_rd_sram_dummy())
+            .field("cache_sram_usr_rcmd", &self.cache_sram_usr_rcmd())
+            .field("sram_rdummy_cyclelen", &self.sram_rdummy_cyclelen())
+            .field("sram_addr_bitlen", &self.sram_addr_bitlen())
+            .field("cache_sram_usr_wcmd", &self.cache_sram_usr_wcmd())
+            .field("sram_oct", &self.sram_oct())
+            .field("sram_wdummy_cyclelen", &self.sram_wdummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_SCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 external RAM control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_sctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_SCTRL_SPEC;
 impl crate::RegisterSpec for CACHE_SCTRL_SPEC {
diff --git a/esp32c6/src/spi0/clock.rs b/esp32c6/src/spi0/clock.rs
index e44e658046..5adc5d874b 100644
--- a/esp32c6/src/spi0/clock.rs
+++ b/esp32c6/src/spi0/clock.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/clock_gate.rs b/esp32c6/src/spi0/clock_gate.rs
index 9e3dcbf652..eede18e876 100644
--- a/esp32c6/src/spi0/clock_gate.rs
+++ b/esp32c6/src/spi0/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("spi_clk_en", &format_args!("{}", self.spi_clk_en().bit()))
+            .field("spi_clk_en", &self.spi_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/cmd.rs b/esp32c6/src/spi0/cmd.rs
index 668e900c12..1b01eda873 100644
--- a/esp32c6/src/spi0/cmd.rs
+++ b/esp32c6/src/spi0/cmd.rs
@@ -27,18 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("mst_st", &format_args!("{}", self.mst_st().bits()))
-            .field("slv_st", &format_args!("{}", self.slv_st().bits()))
-            .field("usr", &format_args!("{}", self.usr().bit()))
+            .field("mst_st", &self.mst_st())
+            .field("slv_st", &self.slv_st())
+            .field("usr", &self.usr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 FSM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CMD_SPEC;
 impl crate::RegisterSpec for CMD_SPEC {
diff --git a/esp32c6/src/spi0/ctrl.rs b/esp32c6/src/spi0/ctrl.rs
index 63b351dd2a..4301347f6d 100644
--- a/esp32c6/src/spi0/ctrl.rs
+++ b/esp32c6/src/spi0/ctrl.rs
@@ -167,46 +167,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field(
-                "wdummy_dqs_always_out",
-                &format_args!("{}", self.wdummy_dqs_always_out().bit()),
-            )
-            .field(
-                "wdummy_always_out",
-                &format_args!("{}", self.wdummy_always_out().bit()),
-            )
-            .field("fdummy_rin", &format_args!("{}", self.fdummy_rin().bit()))
-            .field("fdummy_wout", &format_args!("{}", self.fdummy_wout().bit()))
-            .field("fdout_oct", &format_args!("{}", self.fdout_oct().bit()))
-            .field("fdin_oct", &format_args!("{}", self.fdin_oct().bit()))
-            .field("faddr_oct", &format_args!("{}", self.faddr_oct().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcmd_oct", &format_args!("{}", self.fcmd_oct().bit()))
-            .field("fastrd_mode", &format_args!("{}", self.fastrd_mode().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("wp", &format_args!("{}", self.wp().bit()))
-            .field("fread_dio", &format_args!("{}", self.fread_dio().bit()))
-            .field("fread_qio", &format_args!("{}", self.fread_qio().bit()))
-            .field(
-                "dqs_ie_always_on",
-                &format_args!("{}", self.dqs_ie_always_on().bit()),
-            )
-            .field(
-                "data_ie_always_on",
-                &format_args!("{}", self.data_ie_always_on().bit()),
-            )
+            .field("wdummy_dqs_always_out", &self.wdummy_dqs_always_out())
+            .field("wdummy_always_out", &self.wdummy_always_out())
+            .field("fdummy_rin", &self.fdummy_rin())
+            .field("fdummy_wout", &self.fdummy_wout())
+            .field("fdout_oct", &self.fdout_oct())
+            .field("fdin_oct", &self.fdin_oct())
+            .field("faddr_oct", &self.faddr_oct())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcmd_oct", &self.fcmd_oct())
+            .field("fastrd_mode", &self.fastrd_mode())
+            .field("fread_dual", &self.fread_dual())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("fread_quad", &self.fread_quad())
+            .field("wp", &self.wp())
+            .field("fread_dio", &self.fread_dio())
+            .field("fread_qio", &self.fread_qio())
+            .field("dqs_ie_always_on", &self.dqs_ie_always_on())
+            .field("data_ie_always_on", &self.data_ie_always_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/ctrl1.rs b/esp32c6/src/spi0/ctrl1.rs
index b7851d168e..01095aee39 100644
--- a/esp32c6/src/spi0/ctrl1.rs
+++ b/esp32c6/src/spi0/ctrl1.rs
@@ -92,46 +92,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL1")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
+            .field("clk_mode", &self.clk_mode())
             .field(
                 "spi_ar_size0_1_support_en",
-                &format_args!("{}", self.spi_ar_size0_1_support_en().bit()),
+                &self.spi_ar_size0_1_support_en(),
             )
             .field(
                 "spi_aw_size0_1_support_en",
-                &format_args!("{}", self.spi_aw_size0_1_support_en().bit()),
-            )
-            .field(
-                "spi_axi_rdata_back_fast",
-                &format_args!("{}", self.spi_axi_rdata_back_fast().bit()),
-            )
-            .field(
-                "rresp_ecc_err_en",
-                &format_args!("{}", self.rresp_ecc_err_en().bit()),
-            )
-            .field(
-                "ar_splice_en",
-                &format_args!("{}", self.ar_splice_en().bit()),
-            )
-            .field(
-                "aw_splice_en",
-                &format_args!("{}", self.aw_splice_en().bit()),
-            )
-            .field("ram0_en", &format_args!("{}", self.ram0_en().bit()))
-            .field("dual_ram_en", &format_args!("{}", self.dual_ram_en().bit()))
-            .field(
-                "fast_write_en",
-                &format_args!("{}", self.fast_write_en().bit()),
+                &self.spi_aw_size0_1_support_en(),
             )
+            .field("spi_axi_rdata_back_fast", &self.spi_axi_rdata_back_fast())
+            .field("rresp_ecc_err_en", &self.rresp_ecc_err_en())
+            .field("ar_splice_en", &self.ar_splice_en())
+            .field("aw_splice_en", &self.aw_splice_en())
+            .field("ram0_en", &self.ram0_en())
+            .field("dual_ram_en", &self.dual_ram_en())
+            .field("fast_write_en", &self.fast_write_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/ctrl2.rs b/esp32c6/src/spi0/ctrl2.rs
index 40825c52ab..3792399b33 100644
--- a/esp32c6/src/spi0/ctrl2.rs
+++ b/esp32c6/src/spi0/ctrl2.rs
@@ -65,43 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field(
-                "cs_setup_time",
-                &format_args!("{}", self.cs_setup_time().bits()),
-            )
-            .field(
-                "cs_hold_time",
-                &format_args!("{}", self.cs_hold_time().bits()),
-            )
-            .field(
-                "ecc_cs_hold_time",
-                &format_args!("{}", self.ecc_cs_hold_time().bits()),
-            )
-            .field(
-                "ecc_skip_page_corner",
-                &format_args!("{}", self.ecc_skip_page_corner().bit()),
-            )
-            .field(
-                "ecc_16to18_byte_en",
-                &format_args!("{}", self.ecc_16to18_byte_en().bit()),
-            )
-            .field(
-                "split_trans_en",
-                &format_args!("{}", self.split_trans_en().bit()),
-            )
-            .field(
-                "cs_hold_delay",
-                &format_args!("{}", self.cs_hold_delay().bits()),
-            )
+            .field("cs_setup_time", &self.cs_setup_time())
+            .field("cs_hold_time", &self.cs_hold_time())
+            .field("ecc_cs_hold_time", &self.ecc_cs_hold_time())
+            .field("ecc_skip_page_corner", &self.ecc_skip_page_corner())
+            .field("ecc_16to18_byte_en", &self.ecc_16to18_byte_en())
+            .field("split_trans_en", &self.split_trans_en())
+            .field("cs_hold_delay", &self.cs_hold_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/date.rs b/esp32c6/src/spi0/date.rs
index 389e77e677..a96e4beb1b 100644
--- a/esp32c6/src/spi0/date.rs
+++ b/esp32c6/src/spi0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/spi0/ddr.rs b/esp32c6/src/spi0/ddr.rs
index 2a5f5afdb2..f57439109f 100644
--- a/esp32c6/src/spi0/ddr.rs
+++ b/esp32c6/src/spi0/ddr.rs
@@ -118,79 +118,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DDR")
-            .field(
-                "spi_fmem_ddr_en",
-                &format_args!("{}", self.spi_fmem_ddr_en().bit()),
-            )
-            .field(
-                "spi_fmem_var_dummy",
-                &format_args!("{}", self.spi_fmem_var_dummy().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_rdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_rdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_wdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_wdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_cmd_dis",
-                &format_args!("{}", self.spi_fmem_ddr_cmd_dis().bit()),
-            )
-            .field(
-                "spi_fmem_outminbytelen",
-                &format_args!("{}", self.spi_fmem_outminbytelen().bits()),
-            )
-            .field(
-                "spi_fmem_tx_ddr_msk_en",
-                &format_args!("{}", self.spi_fmem_tx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_fmem_rx_ddr_msk_en",
-                &format_args!("{}", self.spi_fmem_rx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_fmem_usr_ddr_dqs_thd",
-                &format_args!("{}", self.spi_fmem_usr_ddr_dqs_thd().bits()),
-            )
-            .field(
-                "spi_fmem_ddr_dqs_loop",
-                &format_args!("{}", self.spi_fmem_ddr_dqs_loop().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_en",
-                &format_args!("{}", self.spi_fmem_clk_diff_en().bit()),
-            )
-            .field(
-                "spi_fmem_dqs_ca_in",
-                &format_args!("{}", self.spi_fmem_dqs_ca_in().bit()),
-            )
+            .field("spi_fmem_ddr_en", &self.spi_fmem_ddr_en())
+            .field("spi_fmem_var_dummy", &self.spi_fmem_var_dummy())
+            .field("spi_fmem_ddr_rdat_swp", &self.spi_fmem_ddr_rdat_swp())
+            .field("spi_fmem_ddr_wdat_swp", &self.spi_fmem_ddr_wdat_swp())
+            .field("spi_fmem_ddr_cmd_dis", &self.spi_fmem_ddr_cmd_dis())
+            .field("spi_fmem_outminbytelen", &self.spi_fmem_outminbytelen())
+            .field("spi_fmem_tx_ddr_msk_en", &self.spi_fmem_tx_ddr_msk_en())
+            .field("spi_fmem_rx_ddr_msk_en", &self.spi_fmem_rx_ddr_msk_en())
+            .field("spi_fmem_usr_ddr_dqs_thd", &self.spi_fmem_usr_ddr_dqs_thd())
+            .field("spi_fmem_ddr_dqs_loop", &self.spi_fmem_ddr_dqs_loop())
+            .field("spi_fmem_clk_diff_en", &self.spi_fmem_clk_diff_en())
+            .field("spi_fmem_dqs_ca_in", &self.spi_fmem_dqs_ca_in())
             .field(
                 "spi_fmem_hyperbus_dummy_2x",
-                &format_args!("{}", self.spi_fmem_hyperbus_dummy_2x().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_inv",
-                &format_args!("{}", self.spi_fmem_clk_diff_inv().bit()),
-            )
-            .field(
-                "spi_fmem_octa_ram_addr",
-                &format_args!("{}", self.spi_fmem_octa_ram_addr().bit()),
-            )
-            .field(
-                "spi_fmem_hyperbus_ca",
-                &format_args!("{}", self.spi_fmem_hyperbus_ca().bit()),
+                &self.spi_fmem_hyperbus_dummy_2x(),
             )
+            .field("spi_fmem_clk_diff_inv", &self.spi_fmem_clk_diff_inv())
+            .field("spi_fmem_octa_ram_addr", &self.spi_fmem_octa_ram_addr())
+            .field("spi_fmem_hyperbus_ca", &self.spi_fmem_hyperbus_ca())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 flash DDR mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DDR_SPEC;
 impl crate::RegisterSpec for DDR_SPEC {
diff --git a/esp32c6/src/spi0/din_mode.rs b/esp32c6/src/spi0/din_mode.rs
index 90d7b5a3fd..dfc428573f 100644
--- a/esp32c6/src/spi0/din_mode.rs
+++ b/esp32c6/src/spi0/din_mode.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_MODE")
-            .field("din0_mode", &format_args!("{}", self.din0_mode().bits()))
-            .field("din1_mode", &format_args!("{}", self.din1_mode().bits()))
-            .field("din2_mode", &format_args!("{}", self.din2_mode().bits()))
-            .field("din3_mode", &format_args!("{}", self.din3_mode().bits()))
-            .field("din4_mode", &format_args!("{}", self.din4_mode().bits()))
-            .field("din5_mode", &format_args!("{}", self.din5_mode().bits()))
-            .field("din6_mode", &format_args!("{}", self.din6_mode().bits()))
-            .field("din7_mode", &format_args!("{}", self.din7_mode().bits()))
-            .field("dins_mode", &format_args!("{}", self.dins_mode().bits()))
+            .field("din0_mode", &self.din0_mode())
+            .field("din1_mode", &self.din1_mode())
+            .field("din2_mode", &self.din2_mode())
+            .field("din3_mode", &self.din3_mode())
+            .field("din4_mode", &self.din4_mode())
+            .field("din5_mode", &self.din5_mode())
+            .field("din6_mode", &self.din6_mode())
+            .field("din7_mode", &self.din7_mode())
+            .field("dins_mode", &self.dins_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/din_num.rs b/esp32c6/src/spi0/din_num.rs
index 2ee1addcc8..e349d63599 100644
--- a/esp32c6/src/spi0/din_num.rs
+++ b/esp32c6/src/spi0/din_num.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_NUM")
-            .field("din0_num", &format_args!("{}", self.din0_num().bits()))
-            .field("din1_num", &format_args!("{}", self.din1_num().bits()))
-            .field("din2_num", &format_args!("{}", self.din2_num().bits()))
-            .field("din3_num", &format_args!("{}", self.din3_num().bits()))
-            .field("din4_num", &format_args!("{}", self.din4_num().bits()))
-            .field("din5_num", &format_args!("{}", self.din5_num().bits()))
-            .field("din6_num", &format_args!("{}", self.din6_num().bits()))
-            .field("din7_num", &format_args!("{}", self.din7_num().bits()))
-            .field("dins_num", &format_args!("{}", self.dins_num().bits()))
+            .field("din0_num", &self.din0_num())
+            .field("din1_num", &self.din1_num())
+            .field("din2_num", &self.din2_num())
+            .field("din3_num", &self.din3_num())
+            .field("din4_num", &self.din4_num())
+            .field("din5_num", &self.din5_num())
+            .field("din6_num", &self.din6_num())
+            .field("din7_num", &self.din7_num())
+            .field("dins_num", &self.dins_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/dout_mode.rs b/esp32c6/src/spi0/dout_mode.rs
index fa50bdd69a..e426b2bf23 100644
--- a/esp32c6/src/spi0/dout_mode.rs
+++ b/esp32c6/src/spi0/dout_mode.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOUT_MODE")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bit()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bit()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bit()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bit()))
-            .field("dout4_mode", &format_args!("{}", self.dout4_mode().bit()))
-            .field("dout5_mode", &format_args!("{}", self.dout5_mode().bit()))
-            .field("dout6_mode", &format_args!("{}", self.dout6_mode().bit()))
-            .field("dout7_mode", &format_args!("{}", self.dout7_mode().bit()))
-            .field("douts_mode", &format_args!("{}", self.douts_mode().bit()))
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
+            .field("dout4_mode", &self.dout4_mode())
+            .field("dout5_mode", &self.dout5_mode())
+            .field("dout6_mode", &self.dout6_mode())
+            .field("dout7_mode", &self.dout7_mode())
+            .field("douts_mode", &self.douts_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/dpa_ctrl.rs b/esp32c6/src/spi0/dpa_ctrl.rs
index 36adf8a2a3..aea7e042b7 100644
--- a/esp32c6/src/spi0/dpa_ctrl.rs
+++ b/esp32c6/src/spi0/dpa_ctrl.rs
@@ -35,27 +35,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPA_CTRL")
-            .field(
-                "spi_crypt_security_level",
-                &format_args!("{}", self.spi_crypt_security_level().bits()),
-            )
-            .field(
-                "spi_crypt_calc_d_dpa_en",
-                &format_args!("{}", self.spi_crypt_calc_d_dpa_en().bit()),
-            )
+            .field("spi_crypt_security_level", &self.spi_crypt_security_level())
+            .field("spi_crypt_calc_d_dpa_en", &self.spi_crypt_calc_d_dpa_en())
             .field(
                 "spi_crypt_dpa_select_register",
-                &format_args!("{}", self.spi_crypt_dpa_select_register().bit()),
+                &self.spi_crypt_dpa_select_register(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPA_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)"]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/ecc_ctrl.rs b/esp32c6/src/spi0/ecc_ctrl.rs
index cd96e78e81..522907e1ab 100644
--- a/esp32c6/src/spi0/ecc_ctrl.rs
+++ b/esp32c6/src/spi0/ecc_ctrl.rs
@@ -59,43 +59,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_CTRL")
-            .field(
-                "spi_fmem_ecc_err_int_num",
-                &format_args!("{}", self.spi_fmem_ecc_err_int_num().bits()),
-            )
-            .field(
-                "spi_fmem_ecc_err_int_en",
-                &format_args!("{}", self.spi_fmem_ecc_err_int_en().bit()),
-            )
-            .field(
-                "spi_fmem_page_size",
-                &format_args!("{}", self.spi_fmem_page_size().bits()),
-            )
-            .field(
-                "spi_fmem_ecc_addr_en",
-                &format_args!("{}", self.spi_fmem_ecc_addr_en().bit()),
-            )
-            .field(
-                "usr_ecc_addr_en",
-                &format_args!("{}", self.usr_ecc_addr_en().bit()),
-            )
+            .field("spi_fmem_ecc_err_int_num", &self.spi_fmem_ecc_err_int_num())
+            .field("spi_fmem_ecc_err_int_en", &self.spi_fmem_ecc_err_int_en())
+            .field("spi_fmem_page_size", &self.spi_fmem_page_size())
+            .field("spi_fmem_ecc_addr_en", &self.spi_fmem_ecc_addr_en())
+            .field("usr_ecc_addr_en", &self.usr_ecc_addr_en())
             .field(
                 "ecc_continue_record_err_en",
-                &format_args!("{}", self.ecc_continue_record_err_en().bit()),
-            )
-            .field(
-                "ecc_err_bits",
-                &format_args!("{}", self.ecc_err_bits().bits()),
+                &self.ecc_continue_record_err_en(),
             )
+            .field("ecc_err_bits", &self.ecc_err_bits())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 18:19 - Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/ecc_err_addr.rs b/esp32c6/src/spi0/ecc_err_addr.rs
index 1ddfb7145a..f5450cb8be 100644
--- a/esp32c6/src/spi0/ecc_err_addr.rs
+++ b/esp32c6/src/spi0/ecc_err_addr.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_ERR_ADDR")
-            .field(
-                "ecc_err_addr",
-                &format_args!("{}", self.ecc_err_addr().bits()),
-            )
-            .field(
-                "ecc_err_cnt",
-                &format_args!("{}", self.ecc_err_cnt().bits()),
-            )
+            .field("ecc_err_addr", &self.ecc_err_addr())
+            .field("ecc_err_cnt", &self.ecc_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_ERR_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI ECC error address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecc_err_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ECC_ERR_ADDR_SPEC;
 impl crate::RegisterSpec for ECC_ERR_ADDR_SPEC {
diff --git a/esp32c6/src/spi0/fsm.rs b/esp32c6/src/spi0/fsm.rs
index 54045ebf4f..ed0f815e8e 100644
--- a/esp32c6/src/spi0/fsm.rs
+++ b/esp32c6/src/spi0/fsm.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM")
-            .field(
-                "lock_delay_time",
-                &format_args!("{}", self.lock_delay_time().bits()),
-            )
+            .field("lock_delay_time", &self.lock_delay_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 7:11 - The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/int_clr.rs b/esp32c6/src/spi0/int_clr.rs
index c0fba58847..9bec767d37 100644
--- a/esp32c6/src/spi0/int_clr.rs
+++ b/esp32c6/src/spi0/int_clr.rs
@@ -37,24 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_CLR")
-            .field("ecc_err", &format_args!("{}", self.ecc_err().bit()))
-            .field(
-                "axi_wr_flash_err",
-                &format_args!("{}", self.axi_wr_flash_err().bit()),
-            )
-            .field(
-                "axi_waddr_err",
-                &format_args!("{}", self.axi_waddr_err().bit()),
-            )
+            .field("ecc_err", &self.ecc_err())
+            .field("axi_wr_flash_err", &self.axi_wr_flash_err())
+            .field("axi_waddr_err", &self.axi_waddr_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - The clear bit for SPI_MEM_SLV_ST_END_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/int_ena.rs b/esp32c6/src/spi0/int_ena.rs
index f284bcdab8..5abefbc3e8 100644
--- a/esp32c6/src/spi0/int_ena.rs
+++ b/esp32c6/src/spi0/int_ena.rs
@@ -65,31 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("ecc_err", &format_args!("{}", self.ecc_err().bit()))
-            .field("pms_reject", &format_args!("{}", self.pms_reject().bit()))
-            .field(
-                "axi_raddr_err",
-                &format_args!("{}", self.axi_raddr_err().bit()),
-            )
-            .field(
-                "axi_wr_flash_err",
-                &format_args!("{}", self.axi_wr_flash_err().bit()),
-            )
-            .field(
-                "axi_waddr_err_int__ena",
-                &format_args!("{}", self.axi_waddr_err_int__ena().bit()),
-            )
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("ecc_err", &self.ecc_err())
+            .field("pms_reject", &self.pms_reject())
+            .field("axi_raddr_err", &self.axi_raddr_err())
+            .field("axi_wr_flash_err", &self.axi_wr_flash_err())
+            .field("axi_waddr_err_int__ena", &self.axi_waddr_err_int__ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/int_raw.rs b/esp32c6/src/spi0/int_raw.rs
index 3f1a3ac78d..7343156220 100644
--- a/esp32c6/src/spi0/int_raw.rs
+++ b/esp32c6/src/spi0/int_raw.rs
@@ -65,31 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("ecc_err", &format_args!("{}", self.ecc_err().bit()))
-            .field("pms_reject", &format_args!("{}", self.pms_reject().bit()))
-            .field(
-                "axi_raddr_err",
-                &format_args!("{}", self.axi_raddr_err().bit()),
-            )
-            .field(
-                "axi_wr_flash_err",
-                &format_args!("{}", self.axi_wr_flash_err().bit()),
-            )
-            .field(
-                "axi_waddr_err",
-                &format_args!("{}", self.axi_waddr_err().bit()),
-            )
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("ecc_err", &self.ecc_err())
+            .field("pms_reject", &self.pms_reject())
+            .field("axi_raddr_err", &self.axi_raddr_err())
+            .field("axi_wr_flash_err", &self.axi_wr_flash_err())
+            .field("axi_waddr_err", &self.axi_waddr_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/int_st.rs b/esp32c6/src/spi0/int_st.rs
index 5ef07ec7f3..cb894ae699 100644
--- a/esp32c6/src/spi0/int_st.rs
+++ b/esp32c6/src/spi0/int_st.rs
@@ -55,31 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("ecc_err", &format_args!("{}", self.ecc_err().bit()))
-            .field("pms_reject", &format_args!("{}", self.pms_reject().bit()))
-            .field(
-                "axi_raddr_err",
-                &format_args!("{}", self.axi_raddr_err().bit()),
-            )
-            .field(
-                "axi_wr_flash_err",
-                &format_args!("{}", self.axi_wr_flash_err().bit()),
-            )
-            .field(
-                "axi_waddr_err",
-                &format_args!("{}", self.axi_waddr_err().bit()),
-            )
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("ecc_err", &self.ecc_err())
+            .field("pms_reject", &self.pms_reject())
+            .field("axi_raddr_err", &self.axi_raddr_err())
+            .field("axi_wr_flash_err", &self.axi_wr_flash_err())
+            .field("axi_waddr_err", &self.axi_waddr_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/spi0/misc.rs b/esp32c6/src/spi0/misc.rs
index b421faf0c1..f87ca4dc57 100644
--- a/esp32c6/src/spi0/misc.rs
+++ b/esp32c6/src/spi0/misc.rs
@@ -40,25 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("fsub_pin", &format_args!("{}", self.fsub_pin().bit()))
-            .field("ssub_pin", &format_args!("{}", self.ssub_pin().bit()))
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
+            .field("fsub_pin", &self.fsub_pin())
+            .field("ssub_pin", &self.ssub_pin())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - 1: SPI_CLK line is high when idle 0: spi clk line is low when idle"]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/mmu_item_content.rs b/esp32c6/src/spi0/mmu_item_content.rs
index 543a1fc5db..a3898f8b78 100644
--- a/esp32c6/src/spi0/mmu_item_content.rs
+++ b/esp32c6/src/spi0/mmu_item_content.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MMU_ITEM_CONTENT")
-            .field(
-                "spi_mmu_item_content",
-                &format_args!("{}", self.spi_mmu_item_content().bits()),
-            )
+            .field("spi_mmu_item_content", &self.spi_mmu_item_content())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MMU_ITEM_CONTENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - MSPI-MMU item content"]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/mmu_item_index.rs b/esp32c6/src/spi0/mmu_item_index.rs
index 9b421e3af3..3cdaed760f 100644
--- a/esp32c6/src/spi0/mmu_item_index.rs
+++ b/esp32c6/src/spi0/mmu_item_index.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MMU_ITEM_INDEX")
-            .field(
-                "spi_mmu_item_index",
-                &format_args!("{}", self.spi_mmu_item_index().bits()),
-            )
+            .field("spi_mmu_item_index", &self.spi_mmu_item_index())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MMU_ITEM_INDEX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - MSPI-MMU item index"]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/mmu_power_ctrl.rs b/esp32c6/src/spi0/mmu_power_ctrl.rs
index 83302e4c4e..8b461b6042 100644
--- a/esp32c6/src/spi0/mmu_power_ctrl.rs
+++ b/esp32c6/src/spi0/mmu_power_ctrl.rs
@@ -65,34 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MMU_POWER_CTRL")
-            .field(
-                "spi_mmu_mem_force_on",
-                &format_args!("{}", self.spi_mmu_mem_force_on().bit()),
-            )
-            .field(
-                "spi_mmu_mem_force_pd",
-                &format_args!("{}", self.spi_mmu_mem_force_pd().bit()),
-            )
-            .field(
-                "spi_mmu_mem_force_pu",
-                &format_args!("{}", self.spi_mmu_mem_force_pu().bit()),
-            )
-            .field(
-                "spi_mmu_page_size",
-                &format_args!("{}", self.spi_mmu_page_size().bits()),
-            )
-            .field("aux_ctrl", &format_args!("{}", self.aux_ctrl().bits()))
-            .field("rdn_ena", &format_args!("{}", self.rdn_ena().bit()))
-            .field("rdn_result", &format_args!("{}", self.rdn_result().bit()))
+            .field("spi_mmu_mem_force_on", &self.spi_mmu_mem_force_on())
+            .field("spi_mmu_mem_force_pd", &self.spi_mmu_mem_force_pd())
+            .field("spi_mmu_mem_force_pu", &self.spi_mmu_mem_force_pu())
+            .field("spi_mmu_page_size", &self.spi_mmu_page_size())
+            .field("aux_ctrl", &self.aux_ctrl())
+            .field("rdn_ena", &self.rdn_ena())
+            .field("rdn_result", &self.rdn_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MMU_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable mmu-memory clock force on"]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/pms_reject.rs b/esp32c6/src/spi0/pms_reject.rs
index db8ec870f6..bcf8e5de2b 100644
--- a/esp32c6/src/spi0/pms_reject.rs
+++ b/esp32c6/src/spi0/pms_reject.rs
@@ -52,27 +52,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMS_REJECT")
-            .field(
-                "reject_addr",
-                &format_args!("{}", self.reject_addr().bits()),
-            )
-            .field("pm_en", &format_args!("{}", self.pm_en().bit()))
-            .field("pms_ld", &format_args!("{}", self.pms_ld().bit()))
-            .field("pms_st", &format_args!("{}", self.pms_st().bit()))
-            .field(
-                "pms_multi_hit",
-                &format_args!("{}", self.pms_multi_hit().bit()),
-            )
-            .field("pms_ivd", &format_args!("{}", self.pms_ivd().bit()))
+            .field("reject_addr", &self.reject_addr())
+            .field("pm_en", &self.pm_en())
+            .field("pms_ld", &self.pms_ld())
+            .field("pms_st", &self.pms_st())
+            .field("pms_multi_hit", &self.pms_multi_hit())
+            .field("pms_ivd", &self.pms_ivd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMS_REJECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - Set this bit to enable SPI0/1 transfer permission control function."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/rd_status.rs b/esp32c6/src/spi0/rd_status.rs
index f0916ef916..ce4af380ee 100644
--- a/esp32c6/src/spi0/rd_status.rs
+++ b/esp32c6/src/spi0/rd_status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_STATUS")
-            .field("wb_mode", &format_args!("{}", self.wb_mode().bits()))
+            .field("wb_mode", &self.wb_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:23 - Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/registerrnd_eco_high.rs b/esp32c6/src/spi0/registerrnd_eco_high.rs
index a9db8065fc..6ff3607a30 100644
--- a/esp32c6/src/spi0/registerrnd_eco_high.rs
+++ b/esp32c6/src/spi0/registerrnd_eco_high.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGISTERRND_ECO_HIGH")
-            .field(
-                "registerrnd_eco_high",
-                &format_args!("{}", self.registerrnd_eco_high().bits()),
-            )
+            .field("registerrnd_eco_high", &self.registerrnd_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGISTERRND_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI ECO high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`registerrnd_eco_high::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REGISTERRND_ECO_HIGH_SPEC;
 impl crate::RegisterSpec for REGISTERRND_ECO_HIGH_SPEC {
diff --git a/esp32c6/src/spi0/registerrnd_eco_low.rs b/esp32c6/src/spi0/registerrnd_eco_low.rs
index 1486744d81..bcf399dab2 100644
--- a/esp32c6/src/spi0/registerrnd_eco_low.rs
+++ b/esp32c6/src/spi0/registerrnd_eco_low.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGISTERRND_ECO_LOW")
-            .field(
-                "registerrnd_eco_low",
-                &format_args!("{}", self.registerrnd_eco_low().bits()),
-            )
+            .field("registerrnd_eco_low", &self.registerrnd_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGISTERRND_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI ECO low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`registerrnd_eco_low::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REGISTERRND_ECO_LOW_SPEC;
 impl crate::RegisterSpec for REGISTERRND_ECO_LOW_SPEC {
diff --git a/esp32c6/src/spi0/spi_fmem_pms_addr.rs b/esp32c6/src/spi0/spi_fmem_pms_addr.rs
index 42fdc3fef2..0722040416 100644
--- a/esp32c6/src/spi0/spi_fmem_pms_addr.rs
+++ b/esp32c6/src/spi0/spi_fmem_pms_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_FMEM_PMS_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_FMEM_PMS_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - SPI1 flash ACE section %s start address value"]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/spi_fmem_pms_attr.rs b/esp32c6/src/spi0/spi_fmem_pms_attr.rs
index 5d9eb0f37f..f4c7afcc2b 100644
--- a/esp32c6/src/spi0/spi_fmem_pms_attr.rs
+++ b/esp32c6/src/spi0/spi_fmem_pms_attr.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_FMEM_PMS_ATTR")
-            .field(
-                "spi_fmem_pms_rd_attr",
-                &format_args!("{}", self.spi_fmem_pms_rd_attr().bit()),
-            )
-            .field(
-                "spi_fmem_pms_wr_attr",
-                &format_args!("{}", self.spi_fmem_pms_wr_attr().bit()),
-            )
-            .field(
-                "spi_fmem_pms_ecc",
-                &format_args!("{}", self.spi_fmem_pms_ecc().bit()),
-            )
+            .field("spi_fmem_pms_rd_attr", &self.spi_fmem_pms_rd_attr())
+            .field("spi_fmem_pms_wr_attr", &self.spi_fmem_pms_wr_attr())
+            .field("spi_fmem_pms_ecc", &self.spi_fmem_pms_ecc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_FMEM_PMS_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: SPI1 flash ACE section %s read accessible. 0: Not allowed."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/spi_fmem_pms_size.rs b/esp32c6/src/spi0/spi_fmem_pms_size.rs
index e0755a7a1a..a159e5b088 100644
--- a/esp32c6/src/spi0/spi_fmem_pms_size.rs
+++ b/esp32c6/src/spi0/spi_fmem_pms_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_FMEM_PMS_SIZE")
-            .field(
-                "spi_fmem_pms_size",
-                &format_args!("{}", self.spi_fmem_pms_size().bits()),
-            )
+            .field("spi_fmem_pms_size", &self.spi_fmem_pms_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_FMEM_PMS_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - SPI1 flash ACE section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE)"]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/spi_smem_ac.rs b/esp32c6/src/spi0/spi_smem_ac.rs
index 3c2ce3350a..ca29407860 100644
--- a/esp32c6/src/spi0/spi_smem_ac.rs
+++ b/esp32c6/src/spi0/spi_smem_ac.rs
@@ -69,51 +69,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_AC")
-            .field(
-                "spi_smem_cs_setup",
-                &format_args!("{}", self.spi_smem_cs_setup().bit()),
-            )
-            .field(
-                "spi_smem_cs_hold",
-                &format_args!("{}", self.spi_smem_cs_hold().bit()),
-            )
-            .field(
-                "spi_smem_cs_setup_time",
-                &format_args!("{}", self.spi_smem_cs_setup_time().bits()),
-            )
-            .field(
-                "spi_smem_cs_hold_time",
-                &format_args!("{}", self.spi_smem_cs_hold_time().bits()),
-            )
+            .field("spi_smem_cs_setup", &self.spi_smem_cs_setup())
+            .field("spi_smem_cs_hold", &self.spi_smem_cs_hold())
+            .field("spi_smem_cs_setup_time", &self.spi_smem_cs_setup_time())
+            .field("spi_smem_cs_hold_time", &self.spi_smem_cs_hold_time())
             .field(
                 "spi_smem_ecc_cs_hold_time",
-                &format_args!("{}", self.spi_smem_ecc_cs_hold_time().bits()),
+                &self.spi_smem_ecc_cs_hold_time(),
             )
             .field(
                 "spi_smem_ecc_skip_page_corner",
-                &format_args!("{}", self.spi_smem_ecc_skip_page_corner().bit()),
+                &self.spi_smem_ecc_skip_page_corner(),
             )
             .field(
                 "spi_smem_ecc_16to18_byte_en",
-                &format_args!("{}", self.spi_smem_ecc_16to18_byte_en().bit()),
-            )
-            .field(
-                "spi_smem_cs_hold_delay",
-                &format_args!("{}", self.spi_smem_cs_hold_delay().bits()),
-            )
-            .field(
-                "spi_smem_split_trans_en",
-                &format_args!("{}", self.spi_smem_split_trans_en().bit()),
+                &self.spi_smem_ecc_16to18_byte_en(),
             )
+            .field("spi_smem_cs_hold_delay", &self.spi_smem_cs_hold_delay())
+            .field("spi_smem_split_trans_en", &self.spi_smem_split_trans_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_AC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI external RAM ECC and SPI CS timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_ac::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_SMEM_AC_SPEC;
 impl crate::RegisterSpec for SPI_SMEM_AC_SPEC {
diff --git a/esp32c6/src/spi0/spi_smem_ddr.rs b/esp32c6/src/spi0/spi_smem_ddr.rs
index f761796c63..4ff1b77e74 100644
--- a/esp32c6/src/spi0/spi_smem_ddr.rs
+++ b/esp32c6/src/spi0/spi_smem_ddr.rs
@@ -118,64 +118,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DDR")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field(
-                "spi_smem_var_dummy",
-                &format_args!("{}", self.spi_smem_var_dummy().bit()),
-            )
-            .field("rdat_swp", &format_args!("{}", self.rdat_swp().bit()))
-            .field("wdat_swp", &format_args!("{}", self.wdat_swp().bit()))
-            .field("cmd_dis", &format_args!("{}", self.cmd_dis().bit()))
-            .field(
-                "spi_smem_outminbytelen",
-                &format_args!("{}", self.spi_smem_outminbytelen().bits()),
-            )
-            .field(
-                "spi_smem_tx_ddr_msk_en",
-                &format_args!("{}", self.spi_smem_tx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_smem_rx_ddr_msk_en",
-                &format_args!("{}", self.spi_smem_rx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_smem_usr_ddr_dqs_thd",
-                &format_args!("{}", self.spi_smem_usr_ddr_dqs_thd().bits()),
-            )
-            .field("dqs_loop", &format_args!("{}", self.dqs_loop().bit()))
-            .field(
-                "spi_smem_clk_diff_en",
-                &format_args!("{}", self.spi_smem_clk_diff_en().bit()),
-            )
-            .field(
-                "spi_smem_dqs_ca_in",
-                &format_args!("{}", self.spi_smem_dqs_ca_in().bit()),
-            )
+            .field("en", &self.en())
+            .field("spi_smem_var_dummy", &self.spi_smem_var_dummy())
+            .field("rdat_swp", &self.rdat_swp())
+            .field("wdat_swp", &self.wdat_swp())
+            .field("cmd_dis", &self.cmd_dis())
+            .field("spi_smem_outminbytelen", &self.spi_smem_outminbytelen())
+            .field("spi_smem_tx_ddr_msk_en", &self.spi_smem_tx_ddr_msk_en())
+            .field("spi_smem_rx_ddr_msk_en", &self.spi_smem_rx_ddr_msk_en())
+            .field("spi_smem_usr_ddr_dqs_thd", &self.spi_smem_usr_ddr_dqs_thd())
+            .field("dqs_loop", &self.dqs_loop())
+            .field("spi_smem_clk_diff_en", &self.spi_smem_clk_diff_en())
+            .field("spi_smem_dqs_ca_in", &self.spi_smem_dqs_ca_in())
             .field(
                 "spi_smem_hyperbus_dummy_2x",
-                &format_args!("{}", self.spi_smem_hyperbus_dummy_2x().bit()),
-            )
-            .field(
-                "spi_smem_clk_diff_inv",
-                &format_args!("{}", self.spi_smem_clk_diff_inv().bit()),
-            )
-            .field(
-                "spi_smem_octa_ram_addr",
-                &format_args!("{}", self.spi_smem_octa_ram_addr().bit()),
-            )
-            .field(
-                "spi_smem_hyperbus_ca",
-                &format_args!("{}", self.spi_smem_hyperbus_ca().bit()),
+                &self.spi_smem_hyperbus_dummy_2x(),
             )
+            .field("spi_smem_clk_diff_inv", &self.spi_smem_clk_diff_inv())
+            .field("spi_smem_octa_ram_addr", &self.spi_smem_octa_ram_addr())
+            .field("spi_smem_hyperbus_ca", &self.spi_smem_hyperbus_ca())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 external RAM DDR mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_ddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_SMEM_DDR_SPEC;
 impl crate::RegisterSpec for SPI_SMEM_DDR_SPEC {
diff --git a/esp32c6/src/spi0/spi_smem_din_mode.rs b/esp32c6/src/spi0/spi_smem_din_mode.rs
index 3fc274762b..56436fb48c 100644
--- a/esp32c6/src/spi0/spi_smem_din_mode.rs
+++ b/esp32c6/src/spi0/spi_smem_din_mode.rs
@@ -69,51 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DIN_MODE")
-            .field(
-                "spi_smem_din0_mode",
-                &format_args!("{}", self.spi_smem_din0_mode().bits()),
-            )
-            .field(
-                "spi_smem_din1_mode",
-                &format_args!("{}", self.spi_smem_din1_mode().bits()),
-            )
-            .field(
-                "spi_smem_din2_mode",
-                &format_args!("{}", self.spi_smem_din2_mode().bits()),
-            )
-            .field(
-                "spi_smem_din3_mode",
-                &format_args!("{}", self.spi_smem_din3_mode().bits()),
-            )
-            .field(
-                "spi_smem_din4_mode",
-                &format_args!("{}", self.spi_smem_din4_mode().bits()),
-            )
-            .field(
-                "spi_smem_din5_mode",
-                &format_args!("{}", self.spi_smem_din5_mode().bits()),
-            )
-            .field(
-                "spi_smem_din6_mode",
-                &format_args!("{}", self.spi_smem_din6_mode().bits()),
-            )
-            .field(
-                "spi_smem_din7_mode",
-                &format_args!("{}", self.spi_smem_din7_mode().bits()),
-            )
-            .field(
-                "spi_smem_dins_mode",
-                &format_args!("{}", self.spi_smem_dins_mode().bits()),
-            )
+            .field("spi_smem_din0_mode", &self.spi_smem_din0_mode())
+            .field("spi_smem_din1_mode", &self.spi_smem_din1_mode())
+            .field("spi_smem_din2_mode", &self.spi_smem_din2_mode())
+            .field("spi_smem_din3_mode", &self.spi_smem_din3_mode())
+            .field("spi_smem_din4_mode", &self.spi_smem_din4_mode())
+            .field("spi_smem_din5_mode", &self.spi_smem_din5_mode())
+            .field("spi_smem_din6_mode", &self.spi_smem_din6_mode())
+            .field("spi_smem_din7_mode", &self.spi_smem_din7_mode())
+            .field("spi_smem_dins_mode", &self.spi_smem_dins_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI external RAM input timing delay mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_din_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_SMEM_DIN_MODE_SPEC;
 impl crate::RegisterSpec for SPI_SMEM_DIN_MODE_SPEC {
diff --git a/esp32c6/src/spi0/spi_smem_din_num.rs b/esp32c6/src/spi0/spi_smem_din_num.rs
index 1c87741917..8fbfd95535 100644
--- a/esp32c6/src/spi0/spi_smem_din_num.rs
+++ b/esp32c6/src/spi0/spi_smem_din_num.rs
@@ -69,51 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DIN_NUM")
-            .field(
-                "spi_smem_din0_num",
-                &format_args!("{}", self.spi_smem_din0_num().bits()),
-            )
-            .field(
-                "spi_smem_din1_num",
-                &format_args!("{}", self.spi_smem_din1_num().bits()),
-            )
-            .field(
-                "spi_smem_din2_num",
-                &format_args!("{}", self.spi_smem_din2_num().bits()),
-            )
-            .field(
-                "spi_smem_din3_num",
-                &format_args!("{}", self.spi_smem_din3_num().bits()),
-            )
-            .field(
-                "spi_smem_din4_num",
-                &format_args!("{}", self.spi_smem_din4_num().bits()),
-            )
-            .field(
-                "spi_smem_din5_num",
-                &format_args!("{}", self.spi_smem_din5_num().bits()),
-            )
-            .field(
-                "spi_smem_din6_num",
-                &format_args!("{}", self.spi_smem_din6_num().bits()),
-            )
-            .field(
-                "spi_smem_din7_num",
-                &format_args!("{}", self.spi_smem_din7_num().bits()),
-            )
-            .field(
-                "spi_smem_dins_num",
-                &format_args!("{}", self.spi_smem_dins_num().bits()),
-            )
+            .field("spi_smem_din0_num", &self.spi_smem_din0_num())
+            .field("spi_smem_din1_num", &self.spi_smem_din1_num())
+            .field("spi_smem_din2_num", &self.spi_smem_din2_num())
+            .field("spi_smem_din3_num", &self.spi_smem_din3_num())
+            .field("spi_smem_din4_num", &self.spi_smem_din4_num())
+            .field("spi_smem_din5_num", &self.spi_smem_din5_num())
+            .field("spi_smem_din6_num", &self.spi_smem_din6_num())
+            .field("spi_smem_din7_num", &self.spi_smem_din7_num())
+            .field("spi_smem_dins_num", &self.spi_smem_dins_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI external RAM input timing delay number control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_din_num::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_SMEM_DIN_NUM_SPEC;
 impl crate::RegisterSpec for SPI_SMEM_DIN_NUM_SPEC {
diff --git a/esp32c6/src/spi0/spi_smem_dout_mode.rs b/esp32c6/src/spi0/spi_smem_dout_mode.rs
index 145845bc2e..e00992c610 100644
--- a/esp32c6/src/spi0/spi_smem_dout_mode.rs
+++ b/esp32c6/src/spi0/spi_smem_dout_mode.rs
@@ -69,51 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DOUT_MODE")
-            .field(
-                "spi_smem_dout0_mode",
-                &format_args!("{}", self.spi_smem_dout0_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout1_mode",
-                &format_args!("{}", self.spi_smem_dout1_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout2_mode",
-                &format_args!("{}", self.spi_smem_dout2_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout3_mode",
-                &format_args!("{}", self.spi_smem_dout3_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout4_mode",
-                &format_args!("{}", self.spi_smem_dout4_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout5_mode",
-                &format_args!("{}", self.spi_smem_dout5_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout6_mode",
-                &format_args!("{}", self.spi_smem_dout6_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout7_mode",
-                &format_args!("{}", self.spi_smem_dout7_mode().bit()),
-            )
-            .field(
-                "spi_smem_douts_mode",
-                &format_args!("{}", self.spi_smem_douts_mode().bit()),
-            )
+            .field("spi_smem_dout0_mode", &self.spi_smem_dout0_mode())
+            .field("spi_smem_dout1_mode", &self.spi_smem_dout1_mode())
+            .field("spi_smem_dout2_mode", &self.spi_smem_dout2_mode())
+            .field("spi_smem_dout3_mode", &self.spi_smem_dout3_mode())
+            .field("spi_smem_dout4_mode", &self.spi_smem_dout4_mode())
+            .field("spi_smem_dout5_mode", &self.spi_smem_dout5_mode())
+            .field("spi_smem_dout6_mode", &self.spi_smem_dout6_mode())
+            .field("spi_smem_dout7_mode", &self.spi_smem_dout7_mode())
+            .field("spi_smem_douts_mode", &self.spi_smem_douts_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI external RAM output timing adjustment control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_dout_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_SMEM_DOUT_MODE_SPEC;
 impl crate::RegisterSpec for SPI_SMEM_DOUT_MODE_SPEC {
diff --git a/esp32c6/src/spi0/spi_smem_ecc_ctrl.rs b/esp32c6/src/spi0/spi_smem_ecc_ctrl.rs
index 24b8d624ce..75e2629ea1 100644
--- a/esp32c6/src/spi0/spi_smem_ecc_ctrl.rs
+++ b/esp32c6/src/spi0/spi_smem_ecc_ctrl.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_ECC_CTRL")
-            .field(
-                "spi_smem_ecc_err_int_en",
-                &format_args!("{}", self.spi_smem_ecc_err_int_en().bit()),
-            )
-            .field(
-                "spi_smem_page_size",
-                &format_args!("{}", self.spi_smem_page_size().bits()),
-            )
-            .field(
-                "spi_smem_ecc_addr_en",
-                &format_args!("{}", self.spi_smem_ecc_addr_en().bit()),
-            )
+            .field("spi_smem_ecc_err_int_en", &self.spi_smem_ecc_err_int_en())
+            .field("spi_smem_page_size", &self.spi_smem_page_size())
+            .field("spi_smem_ecc_addr_en", &self.spi_smem_ecc_addr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_ECC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI ECC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_ecc_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_SMEM_ECC_CTRL_SPEC;
 impl crate::RegisterSpec for SPI_SMEM_ECC_CTRL_SPEC {
diff --git a/esp32c6/src/spi0/spi_smem_pms_addr.rs b/esp32c6/src/spi0/spi_smem_pms_addr.rs
index 732e3af257..d69094798b 100644
--- a/esp32c6/src/spi0/spi_smem_pms_addr.rs
+++ b/esp32c6/src/spi0/spi_smem_pms_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_PMS_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_PMS_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - SPI1 external RAM ACE section %s start address value"]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/spi_smem_pms_attr.rs b/esp32c6/src/spi0/spi_smem_pms_attr.rs
index 7564b4c3f6..99daf67d7a 100644
--- a/esp32c6/src/spi0/spi_smem_pms_attr.rs
+++ b/esp32c6/src/spi0/spi_smem_pms_attr.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_PMS_ATTR")
-            .field(
-                "spi_smem_pms_rd_attr",
-                &format_args!("{}", self.spi_smem_pms_rd_attr().bit()),
-            )
-            .field(
-                "spi_smem_pms_wr_attr",
-                &format_args!("{}", self.spi_smem_pms_wr_attr().bit()),
-            )
-            .field(
-                "spi_smem_pms_ecc",
-                &format_args!("{}", self.spi_smem_pms_ecc().bit()),
-            )
+            .field("spi_smem_pms_rd_attr", &self.spi_smem_pms_rd_attr())
+            .field("spi_smem_pms_wr_attr", &self.spi_smem_pms_wr_attr())
+            .field("spi_smem_pms_ecc", &self.spi_smem_pms_ecc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_PMS_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: SPI1 external RAM ACE section %s read accessible. 0: Not allowed."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/spi_smem_pms_size.rs b/esp32c6/src/spi0/spi_smem_pms_size.rs
index aabfb0b96d..0ddc5b8234 100644
--- a/esp32c6/src/spi0/spi_smem_pms_size.rs
+++ b/esp32c6/src/spi0/spi_smem_pms_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_PMS_SIZE")
-            .field(
-                "spi_smem_pms_size",
-                &format_args!("{}", self.spi_smem_pms_size().bits()),
-            )
+            .field("spi_smem_pms_size", &self.spi_smem_pms_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_PMS_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - SPI1 external RAM ACE section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE)"]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/spi_smem_timing_cali.rs b/esp32c6/src/spi0/spi_smem_timing_cali.rs
index ed3778583c..8f140177c4 100644
--- a/esp32c6/src/spi0/spi_smem_timing_cali.rs
+++ b/esp32c6/src/spi0/spi_smem_timing_cali.rs
@@ -34,31 +34,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_TIMING_CALI")
-            .field(
-                "spi_smem_timing_clk_ena",
-                &format_args!("{}", self.spi_smem_timing_clk_ena().bit()),
-            )
-            .field(
-                "spi_smem_timing_cali",
-                &format_args!("{}", self.spi_smem_timing_cali().bit()),
-            )
+            .field("spi_smem_timing_clk_ena", &self.spi_smem_timing_clk_ena())
+            .field("spi_smem_timing_cali", &self.spi_smem_timing_cali())
             .field(
                 "spi_smem_extra_dummy_cyclelen",
-                &format_args!("{}", self.spi_smem_extra_dummy_cyclelen().bits()),
-            )
-            .field(
-                "spi_smem_dll_timing_cali",
-                &format_args!("{}", self.spi_smem_dll_timing_cali().bit()),
+                &self.spi_smem_extra_dummy_cyclelen(),
             )
+            .field("spi_smem_dll_timing_cali", &self.spi_smem_dll_timing_cali())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI external RAM timing calibration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_timing_cali::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_SMEM_TIMING_CALI_SPEC;
 impl crate::RegisterSpec for SPI_SMEM_TIMING_CALI_SPEC {
diff --git a/esp32c6/src/spi0/sram_clk.rs b/esp32c6/src/spi0/sram_clk.rs
index 10a0c605b0..e8649fcb40 100644
--- a/esp32c6/src/spi0/sram_clk.rs
+++ b/esp32c6/src/spi0/sram_clk.rs
@@ -34,22 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_CLK")
-            .field("sclkcnt_l", &format_args!("{}", self.sclkcnt_l().bits()))
-            .field("sclkcnt_h", &format_args!("{}", self.sclkcnt_h().bits()))
-            .field("sclkcnt_n", &format_args!("{}", self.sclkcnt_n().bits()))
-            .field(
-                "sclk_equ_sysclk",
-                &format_args!("{}", self.sclk_equ_sysclk().bit()),
-            )
+            .field("sclkcnt_l", &self.sclkcnt_l())
+            .field("sclkcnt_h", &self.sclkcnt_h())
+            .field("sclkcnt_n", &self.sclkcnt_n())
+            .field("sclk_equ_sysclk", &self.sclk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 external RAM clock control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_clk::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SRAM_CLK_SPEC;
 impl crate::RegisterSpec for SRAM_CLK_SPEC {
diff --git a/esp32c6/src/spi0/sram_cmd.rs b/esp32c6/src/spi0/sram_cmd.rs
index 3b89fc06c0..d0e6e70406 100644
--- a/esp32c6/src/spi0/sram_cmd.rs
+++ b/esp32c6/src/spi0/sram_cmd.rs
@@ -143,46 +143,40 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_CMD")
-            .field("sclk_mode", &format_args!("{}", self.sclk_mode().bits()))
-            .field("swb_mode", &format_args!("{}", self.swb_mode().bits()))
-            .field("sdin_dual", &format_args!("{}", self.sdin_dual().bit()))
-            .field("sdout_dual", &format_args!("{}", self.sdout_dual().bit()))
-            .field("saddr_dual", &format_args!("{}", self.saddr_dual().bit()))
-            .field("sdin_quad", &format_args!("{}", self.sdin_quad().bit()))
-            .field("sdout_quad", &format_args!("{}", self.sdout_quad().bit()))
-            .field("saddr_quad", &format_args!("{}", self.saddr_quad().bit()))
-            .field("scmd_quad", &format_args!("{}", self.scmd_quad().bit()))
-            .field("sdin_oct", &format_args!("{}", self.sdin_oct().bit()))
-            .field("sdout_oct", &format_args!("{}", self.sdout_oct().bit()))
-            .field("saddr_oct", &format_args!("{}", self.saddr_oct().bit()))
-            .field("scmd_oct", &format_args!("{}", self.scmd_oct().bit()))
-            .field("sdummy_rin", &format_args!("{}", self.sdummy_rin().bit()))
-            .field("sdummy_wout", &format_args!("{}", self.sdummy_wout().bit()))
+            .field("sclk_mode", &self.sclk_mode())
+            .field("swb_mode", &self.swb_mode())
+            .field("sdin_dual", &self.sdin_dual())
+            .field("sdout_dual", &self.sdout_dual())
+            .field("saddr_dual", &self.saddr_dual())
+            .field("sdin_quad", &self.sdin_quad())
+            .field("sdout_quad", &self.sdout_quad())
+            .field("saddr_quad", &self.saddr_quad())
+            .field("scmd_quad", &self.scmd_quad())
+            .field("sdin_oct", &self.sdin_oct())
+            .field("sdout_oct", &self.sdout_oct())
+            .field("saddr_oct", &self.saddr_oct())
+            .field("scmd_oct", &self.scmd_oct())
+            .field("sdummy_rin", &self.sdummy_rin())
+            .field("sdummy_wout", &self.sdummy_wout())
             .field(
                 "spi_smem_wdummy_dqs_always_out",
-                &format_args!("{}", self.spi_smem_wdummy_dqs_always_out().bit()),
+                &self.spi_smem_wdummy_dqs_always_out(),
             )
             .field(
                 "spi_smem_wdummy_always_out",
-                &format_args!("{}", self.spi_smem_wdummy_always_out().bit()),
+                &self.spi_smem_wdummy_always_out(),
             )
             .field(
                 "spi_smem_dqs_ie_always_on",
-                &format_args!("{}", self.spi_smem_dqs_ie_always_on().bit()),
+                &self.spi_smem_dqs_ie_always_on(),
             )
             .field(
                 "spi_smem_data_ie_always_on",
-                &format_args!("{}", self.spi_smem_data_ie_always_on().bit()),
+                &self.spi_smem_data_ie_always_on(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 22 - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/sram_drd_cmd.rs b/esp32c6/src/spi0/sram_drd_cmd.rs
index 05c7b20972..915d474d5c 100644
--- a/esp32c6/src/spi0/sram_drd_cmd.rs
+++ b/esp32c6/src/spi0/sram_drd_cmd.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("SRAM_DRD_CMD")
             .field(
                 "cache_sram_usr_rd_cmd_value",
-                &format_args!("{}", self.cache_sram_usr_rd_cmd_value().bits()),
+                &self.cache_sram_usr_rd_cmd_value(),
             )
             .field(
                 "cache_sram_usr_rd_cmd_bitlen",
-                &format_args!("{}", self.cache_sram_usr_rd_cmd_bitlen().bits()),
+                &self.cache_sram_usr_rd_cmd_bitlen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_DRD_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 external RAM DDR read command control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_drd_cmd::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SRAM_DRD_CMD_SPEC;
 impl crate::RegisterSpec for SRAM_DRD_CMD_SPEC {
diff --git a/esp32c6/src/spi0/sram_dwr_cmd.rs b/esp32c6/src/spi0/sram_dwr_cmd.rs
index 5173dc72f8..3e8ea90163 100644
--- a/esp32c6/src/spi0/sram_dwr_cmd.rs
+++ b/esp32c6/src/spi0/sram_dwr_cmd.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("SRAM_DWR_CMD")
             .field(
                 "cache_sram_usr_wr_cmd_value",
-                &format_args!("{}", self.cache_sram_usr_wr_cmd_value().bits()),
+                &self.cache_sram_usr_wr_cmd_value(),
             )
             .field(
                 "cache_sram_usr_wr_cmd_bitlen",
-                &format_args!("{}", self.cache_sram_usr_wr_cmd_bitlen().bits()),
+                &self.cache_sram_usr_wr_cmd_bitlen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_DWR_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 external RAM DDR write command control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_dwr_cmd::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SRAM_DWR_CMD_SPEC;
 impl crate::RegisterSpec for SRAM_DWR_CMD_SPEC {
diff --git a/esp32c6/src/spi0/timing_cali.rs b/esp32c6/src/spi0/timing_cali.rs
index 7e0f42b794..12d673f8b4 100644
--- a/esp32c6/src/spi0/timing_cali.rs
+++ b/esp32c6/src/spi0/timing_cali.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMING_CALI")
-            .field(
-                "timing_clk_ena",
-                &format_args!("{}", self.timing_clk_ena().bit()),
-            )
-            .field("timing_cali", &format_args!("{}", self.timing_cali().bit()))
-            .field(
-                "extra_dummy_cyclelen",
-                &format_args!("{}", self.extra_dummy_cyclelen().bits()),
-            )
-            .field(
-                "dll_timing_cali",
-                &format_args!("{}", self.dll_timing_cali().bit()),
-            )
+            .field("timing_clk_ena", &self.timing_clk_ena())
+            .field("timing_cali", &self.timing_cali())
+            .field("extra_dummy_cyclelen", &self.extra_dummy_cyclelen())
+            .field("dll_timing_cali", &self.dll_timing_cali())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable timing adjust clock for all reading operations."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/user.rs b/esp32c6/src/spi0/user.rs
index 3af8b9a5f6..7c1da8336d 100644
--- a/esp32c6/src/spi0/user.rs
+++ b/esp32c6/src/spi0/user.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
-            .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
+            .field("cs_hold", &self.cs_hold())
+            .field("cs_setup", &self.cs_setup())
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_dummy", &self.usr_dummy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/user1.rs b/esp32c6/src/spi0/user1.rs
index 7261a1c0de..a951f31e26 100644
--- a/esp32c6/src/spi0/user1.rs
+++ b/esp32c6/src/spi0/user1.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "usr_dbytelen",
-                &format_args!("{}", self.usr_dbytelen().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("usr_dbytelen", &self.usr_dbytelen())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/user2.rs b/esp32c6/src/spi0/user2.rs
index 801f605c21..d0bf1413f5 100644
--- a/esp32c6/src/spi0/user2.rs
+++ b/esp32c6/src/spi0/user2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/xts_date.rs b/esp32c6/src/spi0/xts_date.rs
index f4626fb790..6a76691ffc 100644
--- a/esp32c6/src/spi0/xts_date.rs
+++ b/esp32c6/src/spi0/xts_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_DATE")
-            .field(
-                "spi_xts_date",
-                &format_args!("{}", self.spi_xts_date().bits()),
-            )
+            .field("spi_xts_date", &self.spi_xts_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - This bits stores the last modified-time of manual encryption feature."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/xts_destination.rs b/esp32c6/src/spi0/xts_destination.rs
index b892575ff3..53d1dc0664 100644
--- a/esp32c6/src/spi0/xts_destination.rs
+++ b/esp32c6/src/spi0/xts_destination.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_DESTINATION")
-            .field(
-                "spi_xts_destination",
-                &format_args!("{}", self.spi_xts_destination().bit()),
-            )
+            .field("spi_xts_destination", &self.spi_xts_destination())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_DESTINATION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/xts_linesize.rs b/esp32c6/src/spi0/xts_linesize.rs
index 69dda9b934..026adf4932 100644
--- a/esp32c6/src/spi0/xts_linesize.rs
+++ b/esp32c6/src/spi0/xts_linesize.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_LINESIZE")
-            .field(
-                "spi_xts_linesize",
-                &format_args!("{}", self.spi_xts_linesize().bits()),
-            )
+            .field("spi_xts_linesize", &self.spi_xts_linesize())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_LINESIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/xts_physical_address.rs b/esp32c6/src/spi0/xts_physical_address.rs
index 1c5e63ce4a..0bf10b2a3d 100644
--- a/esp32c6/src/spi0/xts_physical_address.rs
+++ b/esp32c6/src/spi0/xts_physical_address.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_PHYSICAL_ADDRESS")
-            .field(
-                "spi_xts_physical_address",
-                &format_args!("{}", self.spi_xts_physical_address().bits()),
-            )
+            .field("spi_xts_physical_address", &self.spi_xts_physical_address())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_PHYSICAL_ADDRESS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/xts_plain_base.rs b/esp32c6/src/spi0/xts_plain_base.rs
index 576a75225c..b411736db1 100644
--- a/esp32c6/src/spi0/xts_plain_base.rs
+++ b/esp32c6/src/spi0/xts_plain_base.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_PLAIN_BASE")
-            .field(
-                "spi_xts_plain",
-                &format_args!("{}", self.spi_xts_plain().bits()),
-            )
+            .field("spi_xts_plain", &self.spi_xts_plain())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_PLAIN_BASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This field is only used to generate include file in c case. This field is useless. Please do not use this field."]
     #[inline(always)]
diff --git a/esp32c6/src/spi0/xts_state.rs b/esp32c6/src/spi0/xts_state.rs
index f60c84f30c..7ce2fd6e44 100644
--- a/esp32c6/src/spi0/xts_state.rs
+++ b/esp32c6/src/spi0/xts_state.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_STATE")
-            .field(
-                "spi_xts_state",
-                &format_args!("{}", self.spi_xts_state().bits()),
-            )
+            .field("spi_xts_state", &self.spi_xts_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Manual Encryption physical address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xts_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct XTS_STATE_SPEC;
 impl crate::RegisterSpec for XTS_STATE_SPEC {
diff --git a/esp32c6/src/spi1/addr.rs b/esp32c6/src/spi1/addr.rs
index 565e7916d4..cc9a0e1b42 100644
--- a/esp32c6/src/spi1/addr.rs
+++ b/esp32c6/src/spi1/addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR")
-            .field(
-                "usr_addr_value",
-                &format_args!("{}", self.usr_addr_value().bits()),
-            )
+            .field("usr_addr_value", &self.usr_addr_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/cache_fctrl.rs b/esp32c6/src/spi1/cache_fctrl.rs
index c8eafade55..3a22f1f847 100644
--- a/esp32c6/src/spi1/cache_fctrl.rs
+++ b/esp32c6/src/spi1/cache_fctrl.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_FCTRL")
-            .field(
-                "cache_usr_addr_4byte",
-                &format_args!("{}", self.cache_usr_addr_4byte().bit()),
-            )
-            .field("fdin_dual", &format_args!("{}", self.fdin_dual().bit()))
-            .field("fdout_dual", &format_args!("{}", self.fdout_dual().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("fdin_quad", &format_args!("{}", self.fdin_quad().bit()))
-            .field("fdout_quad", &format_args!("{}", self.fdout_quad().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
+            .field("cache_usr_addr_4byte", &self.cache_usr_addr_4byte())
+            .field("fdin_dual", &self.fdin_dual())
+            .field("fdout_dual", &self.fdout_dual())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("fdin_quad", &self.fdin_quad())
+            .field("fdout_quad", &self.fdout_quad())
+            .field("faddr_quad", &self.faddr_quad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_FCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/clock.rs b/esp32c6/src/spi1/clock.rs
index 250a0c660f..ec805aad92 100644
--- a/esp32c6/src/spi1/clock.rs
+++ b/esp32c6/src/spi1/clock.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/clock_gate.rs b/esp32c6/src/spi1/clock_gate.rs
index c60d396767..69477e9842 100644
--- a/esp32c6/src/spi1/clock_gate.rs
+++ b/esp32c6/src/spi1/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/cmd.rs b/esp32c6/src/spi1/cmd.rs
index 8c3307af4a..6cb80f8502 100644
--- a/esp32c6/src/spi1/cmd.rs
+++ b/esp32c6/src/spi1/cmd.rs
@@ -157,32 +157,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("mst_st", &format_args!("{}", self.mst_st().bits()))
-            .field("slv_st", &format_args!("{}", self.slv_st().bits()))
-            .field("flash_pe", &format_args!("{}", self.flash_pe().bit()))
-            .field("usr", &format_args!("{}", self.usr().bit()))
-            .field("flash_hpm", &format_args!("{}", self.flash_hpm().bit()))
-            .field("flash_res", &format_args!("{}", self.flash_res().bit()))
-            .field("flash_dp", &format_args!("{}", self.flash_dp().bit()))
-            .field("flash_ce", &format_args!("{}", self.flash_ce().bit()))
-            .field("flash_be", &format_args!("{}", self.flash_be().bit()))
-            .field("flash_se", &format_args!("{}", self.flash_se().bit()))
-            .field("flash_pp", &format_args!("{}", self.flash_pp().bit()))
-            .field("flash_wrsr", &format_args!("{}", self.flash_wrsr().bit()))
-            .field("flash_rdsr", &format_args!("{}", self.flash_rdsr().bit()))
-            .field("flash_rdid", &format_args!("{}", self.flash_rdid().bit()))
-            .field("flash_wrdi", &format_args!("{}", self.flash_wrdi().bit()))
-            .field("flash_wren", &format_args!("{}", self.flash_wren().bit()))
-            .field("flash_read", &format_args!("{}", self.flash_read().bit()))
+            .field("mst_st", &self.mst_st())
+            .field("slv_st", &self.slv_st())
+            .field("flash_pe", &self.flash_pe())
+            .field("usr", &self.usr())
+            .field("flash_hpm", &self.flash_hpm())
+            .field("flash_res", &self.flash_res())
+            .field("flash_dp", &self.flash_dp())
+            .field("flash_ce", &self.flash_ce())
+            .field("flash_be", &self.flash_be())
+            .field("flash_se", &self.flash_se())
+            .field("flash_pp", &self.flash_pp())
+            .field("flash_wrsr", &self.flash_wrsr())
+            .field("flash_rdsr", &self.flash_rdsr())
+            .field("flash_rdid", &self.flash_rdid())
+            .field("flash_wrdi", &self.flash_wrdi())
+            .field("flash_wren", &self.flash_wren())
+            .field("flash_read", &self.flash_read())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/ctrl.rs b/esp32c6/src/spi1/ctrl.rs
index 9e276f4048..d86fde47c2 100644
--- a/esp32c6/src/spi1/ctrl.rs
+++ b/esp32c6/src/spi1/ctrl.rs
@@ -167,34 +167,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("fdummy_rin", &format_args!("{}", self.fdummy_rin().bit()))
-            .field("fdummy_wout", &format_args!("{}", self.fdummy_wout().bit()))
-            .field("fdout_oct", &format_args!("{}", self.fdout_oct().bit()))
-            .field("fdin_oct", &format_args!("{}", self.fdin_oct().bit()))
-            .field("faddr_oct", &format_args!("{}", self.faddr_oct().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcmd_oct", &format_args!("{}", self.fcmd_oct().bit()))
-            .field("fcs_crc_en", &format_args!("{}", self.fcs_crc_en().bit()))
-            .field("tx_crc_en", &format_args!("{}", self.tx_crc_en().bit()))
-            .field("fastrd_mode", &format_args!("{}", self.fastrd_mode().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("resandres", &format_args!("{}", self.resandres().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("wp", &format_args!("{}", self.wp().bit()))
-            .field("wrsr_2b", &format_args!("{}", self.wrsr_2b().bit()))
-            .field("fread_dio", &format_args!("{}", self.fread_dio().bit()))
-            .field("fread_qio", &format_args!("{}", self.fread_qio().bit()))
+            .field("fdummy_rin", &self.fdummy_rin())
+            .field("fdummy_wout", &self.fdummy_wout())
+            .field("fdout_oct", &self.fdout_oct())
+            .field("fdin_oct", &self.fdin_oct())
+            .field("faddr_oct", &self.faddr_oct())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcmd_oct", &self.fcmd_oct())
+            .field("fcs_crc_en", &self.fcs_crc_en())
+            .field("tx_crc_en", &self.tx_crc_en())
+            .field("fastrd_mode", &self.fastrd_mode())
+            .field("fread_dual", &self.fread_dual())
+            .field("resandres", &self.resandres())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("fread_quad", &self.fread_quad())
+            .field("wp", &self.wp())
+            .field("wrsr_2b", &self.wrsr_2b())
+            .field("fread_dio", &self.fread_dio())
+            .field("fread_qio", &self.fread_qio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/ctrl1.rs b/esp32c6/src/spi1/ctrl1.rs
index 72546d185b..bde8ad35ad 100644
--- a/esp32c6/src/spi1/ctrl1.rs
+++ b/esp32c6/src/spi1/ctrl1.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL1")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
-            .field(
-                "cs_hold_dly_res",
-                &format_args!("{}", self.cs_hold_dly_res().bits()),
-            )
+            .field("clk_mode", &self.clk_mode())
+            .field("cs_hold_dly_res", &self.cs_hold_dly_res())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/date.rs b/esp32c6/src/spi1/date.rs
index b06afaf3a2..451ac1b171 100644
--- a/esp32c6/src/spi1/date.rs
+++ b/esp32c6/src/spi1/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/spi1/ddr.rs b/esp32c6/src/spi1/ddr.rs
index cc9e90d9b5..2c342b9cda 100644
--- a/esp32c6/src/spi1/ddr.rs
+++ b/esp32c6/src/spi1/ddr.rs
@@ -104,71 +104,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DDR")
-            .field(
-                "spi_fmem_ddr_en",
-                &format_args!("{}", self.spi_fmem_ddr_en().bit()),
-            )
-            .field(
-                "spi_fmem_var_dummy",
-                &format_args!("{}", self.spi_fmem_var_dummy().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_rdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_rdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_wdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_wdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_cmd_dis",
-                &format_args!("{}", self.spi_fmem_ddr_cmd_dis().bit()),
-            )
-            .field(
-                "spi_fmem_outminbytelen",
-                &format_args!("{}", self.spi_fmem_outminbytelen().bits()),
-            )
-            .field(
-                "spi_fmem_usr_ddr_dqs_thd",
-                &format_args!("{}", self.spi_fmem_usr_ddr_dqs_thd().bits()),
-            )
-            .field(
-                "spi_fmem_ddr_dqs_loop",
-                &format_args!("{}", self.spi_fmem_ddr_dqs_loop().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_en",
-                &format_args!("{}", self.spi_fmem_clk_diff_en().bit()),
-            )
-            .field(
-                "spi_fmem_dqs_ca_in",
-                &format_args!("{}", self.spi_fmem_dqs_ca_in().bit()),
-            )
+            .field("spi_fmem_ddr_en", &self.spi_fmem_ddr_en())
+            .field("spi_fmem_var_dummy", &self.spi_fmem_var_dummy())
+            .field("spi_fmem_ddr_rdat_swp", &self.spi_fmem_ddr_rdat_swp())
+            .field("spi_fmem_ddr_wdat_swp", &self.spi_fmem_ddr_wdat_swp())
+            .field("spi_fmem_ddr_cmd_dis", &self.spi_fmem_ddr_cmd_dis())
+            .field("spi_fmem_outminbytelen", &self.spi_fmem_outminbytelen())
+            .field("spi_fmem_usr_ddr_dqs_thd", &self.spi_fmem_usr_ddr_dqs_thd())
+            .field("spi_fmem_ddr_dqs_loop", &self.spi_fmem_ddr_dqs_loop())
+            .field("spi_fmem_clk_diff_en", &self.spi_fmem_clk_diff_en())
+            .field("spi_fmem_dqs_ca_in", &self.spi_fmem_dqs_ca_in())
             .field(
                 "spi_fmem_hyperbus_dummy_2x",
-                &format_args!("{}", self.spi_fmem_hyperbus_dummy_2x().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_inv",
-                &format_args!("{}", self.spi_fmem_clk_diff_inv().bit()),
-            )
-            .field(
-                "spi_fmem_octa_ram_addr",
-                &format_args!("{}", self.spi_fmem_octa_ram_addr().bit()),
-            )
-            .field(
-                "spi_fmem_hyperbus_ca",
-                &format_args!("{}", self.spi_fmem_hyperbus_ca().bit()),
+                &self.spi_fmem_hyperbus_dummy_2x(),
             )
+            .field("spi_fmem_clk_diff_inv", &self.spi_fmem_clk_diff_inv())
+            .field("spi_fmem_octa_ram_addr", &self.spi_fmem_octa_ram_addr())
+            .field("spi_fmem_hyperbus_ca", &self.spi_fmem_hyperbus_ca())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 DDR control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DDR_SPEC;
 impl crate::RegisterSpec for DDR_SPEC {
diff --git a/esp32c6/src/spi1/flash_sus_cmd.rs b/esp32c6/src/spi1/flash_sus_cmd.rs
index 7d99bea28f..7ad88afb97 100644
--- a/esp32c6/src/spi1/flash_sus_cmd.rs
+++ b/esp32c6/src/spi1/flash_sus_cmd.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_SUS_CMD")
-            .field(
-                "flash_pes_command",
-                &format_args!("{}", self.flash_pes_command().bits()),
-            )
-            .field(
-                "wait_pesr_command",
-                &format_args!("{}", self.wait_pesr_command().bits()),
-            )
+            .field("flash_pes_command", &self.flash_pes_command())
+            .field("wait_pesr_command", &self.wait_pesr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_SUS_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Program/Erase suspend command."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/flash_sus_ctrl.rs b/esp32c6/src/spi1/flash_sus_ctrl.rs
index 187f971488..1f8d0298dd 100644
--- a/esp32c6/src/spi1/flash_sus_ctrl.rs
+++ b/esp32c6/src/spi1/flash_sus_ctrl.rs
@@ -107,44 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_SUS_CTRL")
-            .field("flash_per", &format_args!("{}", self.flash_per().bit()))
-            .field("flash_pes", &format_args!("{}", self.flash_pes().bit()))
-            .field(
-                "flash_per_wait_en",
-                &format_args!("{}", self.flash_per_wait_en().bit()),
-            )
-            .field(
-                "flash_pes_wait_en",
-                &format_args!("{}", self.flash_pes_wait_en().bit()),
-            )
-            .field("pes_per_en", &format_args!("{}", self.pes_per_en().bit()))
-            .field(
-                "flash_pes_en",
-                &format_args!("{}", self.flash_pes_en().bit()),
-            )
-            .field(
-                "pesr_end_msk",
-                &format_args!("{}", self.pesr_end_msk().bits()),
-            )
-            .field(
-                "spi_fmem_rd_sus_2b",
-                &format_args!("{}", self.spi_fmem_rd_sus_2b().bit()),
-            )
-            .field("per_end_en", &format_args!("{}", self.per_end_en().bit()))
-            .field("pes_end_en", &format_args!("{}", self.pes_end_en().bit()))
-            .field(
-                "sus_timeout_cnt",
-                &format_args!("{}", self.sus_timeout_cnt().bits()),
-            )
+            .field("flash_per", &self.flash_per())
+            .field("flash_pes", &self.flash_pes())
+            .field("flash_per_wait_en", &self.flash_per_wait_en())
+            .field("flash_pes_wait_en", &self.flash_pes_wait_en())
+            .field("pes_per_en", &self.pes_per_en())
+            .field("flash_pes_en", &self.flash_pes_en())
+            .field("pesr_end_msk", &self.pesr_end_msk())
+            .field("spi_fmem_rd_sus_2b", &self.spi_fmem_rd_sus_2b())
+            .field("per_end_en", &self.per_end_en())
+            .field("pes_end_en", &self.pes_end_en())
+            .field("sus_timeout_cnt", &self.sus_timeout_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_SUS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/flash_waiti_ctrl.rs b/esp32c6/src/spi1/flash_waiti_ctrl.rs
index 324fe5b02e..d41f29aa1b 100644
--- a/esp32c6/src/spi1/flash_waiti_ctrl.rs
+++ b/esp32c6/src/spi1/flash_waiti_ctrl.rs
@@ -71,34 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_WAITI_CTRL")
-            .field("waiti_en", &format_args!("{}", self.waiti_en().bit()))
-            .field("waiti_dummy", &format_args!("{}", self.waiti_dummy().bit()))
-            .field(
-                "waiti_addr_en",
-                &format_args!("{}", self.waiti_addr_en().bit()),
-            )
-            .field(
-                "waiti_addr_cyclelen",
-                &format_args!("{}", self.waiti_addr_cyclelen().bits()),
-            )
-            .field(
-                "waiti_cmd_2b",
-                &format_args!("{}", self.waiti_cmd_2b().bit()),
-            )
-            .field(
-                "waiti_dummy_cyclelen",
-                &format_args!("{}", self.waiti_dummy_cyclelen().bits()),
-            )
-            .field("waiti_cmd", &format_args!("{}", self.waiti_cmd().bits()))
+            .field("waiti_en", &self.waiti_en())
+            .field("waiti_dummy", &self.waiti_dummy())
+            .field("waiti_addr_en", &self.waiti_addr_en())
+            .field("waiti_addr_cyclelen", &self.waiti_addr_cyclelen())
+            .field("waiti_cmd_2b", &self.waiti_cmd_2b())
+            .field("waiti_dummy_cyclelen", &self.waiti_dummy_cyclelen())
+            .field("waiti_cmd", &self.waiti_cmd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_WAITI_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/int_ena.rs b/esp32c6/src/spi1/int_ena.rs
index bbd8af0e24..48dff931c1 100644
--- a/esp32c6/src/spi1/int_ena.rs
+++ b/esp32c6/src/spi1/int_ena.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("wpe_end", &self.wpe_end())
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("brown_out", &self.brown_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for SPI_MEM_PER_END_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/int_raw.rs b/esp32c6/src/spi1/int_raw.rs
index ae2ed7bc65..f67b50c6c6 100644
--- a/esp32c6/src/spi1/int_raw.rs
+++ b/esp32c6/src/spi1/int_raw.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("wpe_end", &self.wpe_end())
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("brown_out", &self.brown_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/int_st.rs b/esp32c6/src/spi1/int_st.rs
index b0d692f153..10cf1a6c2d 100644
--- a/esp32c6/src/spi1/int_st.rs
+++ b/esp32c6/src/spi1/int_st.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("wpe_end", &self.wpe_end())
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("brown_out", &self.brown_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/spi1/misc.rs b/esp32c6/src/spi1/misc.rs
index 980afa45ae..7c1f213c28 100644
--- a/esp32c6/src/spi1/misc.rs
+++ b/esp32c6/src/spi1/misc.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
-            .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/miso_dlen.rs b/esp32c6/src/spi1/miso_dlen.rs
index 737f493c8c..6813af19b3 100644
--- a/esp32c6/src/spi1/miso_dlen.rs
+++ b/esp32c6/src/spi1/miso_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISO_DLEN")
-            .field(
-                "usr_miso_dbitlen",
-                &format_args!("{}", self.usr_miso_dbitlen().bits()),
-            )
+            .field("usr_miso_dbitlen", &self.usr_miso_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISO_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The length in bits of read-data. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/mosi_dlen.rs b/esp32c6/src/spi1/mosi_dlen.rs
index b21b936f88..5cd5d155af 100644
--- a/esp32c6/src/spi1/mosi_dlen.rs
+++ b/esp32c6/src/spi1/mosi_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MOSI_DLEN")
-            .field(
-                "usr_mosi_dbitlen",
-                &format_args!("{}", self.usr_mosi_dbitlen().bits()),
-            )
+            .field("usr_mosi_dbitlen", &self.usr_mosi_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MOSI_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The length in bits of write-data. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/rd_status.rs b/esp32c6/src/spi1/rd_status.rs
index 6088e50d21..7368a19e92 100644
--- a/esp32c6/src/spi1/rd_status.rs
+++ b/esp32c6/src/spi1/rd_status.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_STATUS")
-            .field("status", &format_args!("{}", self.status().bits()))
-            .field("wb_mode", &format_args!("{}", self.wb_mode().bits()))
+            .field("status", &self.status())
+            .field("wb_mode", &self.wb_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/sus_status.rs b/esp32c6/src/spi1/sus_status.rs
index 80d580228b..8ad4de6524 100644
--- a/esp32c6/src/spi1/sus_status.rs
+++ b/esp32c6/src/spi1/sus_status.rs
@@ -98,52 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SUS_STATUS")
-            .field("flash_sus", &format_args!("{}", self.flash_sus().bit()))
-            .field(
-                "wait_pesr_cmd_2b",
-                &format_args!("{}", self.wait_pesr_cmd_2b().bit()),
-            )
-            .field(
-                "flash_hpm_dly_128",
-                &format_args!("{}", self.flash_hpm_dly_128().bit()),
-            )
-            .field(
-                "flash_res_dly_128",
-                &format_args!("{}", self.flash_res_dly_128().bit()),
-            )
-            .field(
-                "flash_dp_dly_128",
-                &format_args!("{}", self.flash_dp_dly_128().bit()),
-            )
-            .field(
-                "flash_per_dly_128",
-                &format_args!("{}", self.flash_per_dly_128().bit()),
-            )
-            .field(
-                "flash_pes_dly_128",
-                &format_args!("{}", self.flash_pes_dly_128().bit()),
-            )
-            .field(
-                "spi0_lock_en",
-                &format_args!("{}", self.spi0_lock_en().bit()),
-            )
-            .field(
-                "flash_pesr_cmd_2b",
-                &format_args!("{}", self.flash_pesr_cmd_2b().bit()),
-            )
-            .field(
-                "flash_per_command",
-                &format_args!("{}", self.flash_per_command().bits()),
-            )
+            .field("flash_sus", &self.flash_sus())
+            .field("wait_pesr_cmd_2b", &self.wait_pesr_cmd_2b())
+            .field("flash_hpm_dly_128", &self.flash_hpm_dly_128())
+            .field("flash_res_dly_128", &self.flash_res_dly_128())
+            .field("flash_dp_dly_128", &self.flash_dp_dly_128())
+            .field("flash_per_dly_128", &self.flash_per_dly_128())
+            .field("flash_pes_dly_128", &self.flash_pes_dly_128())
+            .field("spi0_lock_en", &self.spi0_lock_en())
+            .field("flash_pesr_cmd_2b", &self.flash_pesr_cmd_2b())
+            .field("flash_per_command", &self.flash_per_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SUS_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The status of flash suspend, only used in SPI1."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/timing_cali.rs b/esp32c6/src/spi1/timing_cali.rs
index 507064ae31..c6a30a5847 100644
--- a/esp32c6/src/spi1/timing_cali.rs
+++ b/esp32c6/src/spi1/timing_cali.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMING_CALI")
-            .field("timing_cali", &format_args!("{}", self.timing_cali().bit()))
-            .field(
-                "extra_dummy_cyclelen",
-                &format_args!("{}", self.extra_dummy_cyclelen().bits()),
-            )
+            .field("timing_cali", &self.timing_cali())
+            .field("extra_dummy_cyclelen", &self.extra_dummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/tx_crc.rs b/esp32c6/src/spi1/tx_crc.rs
index 9faa1c440d..253fff1be1 100644
--- a/esp32c6/src/spi1/tx_crc.rs
+++ b/esp32c6/src/spi1/tx_crc.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 TX CRC data register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TX_CRC_SPEC;
 impl crate::RegisterSpec for TX_CRC_SPEC {
diff --git a/esp32c6/src/spi1/user.rs b/esp32c6/src/spi1/user.rs
index 0ed8d7294f..9515db9c89 100644
--- a/esp32c6/src/spi1/user.rs
+++ b/esp32c6/src/spi1/user.rs
@@ -121,37 +121,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
-            .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
-            .field("fwrite_dio", &format_args!("{}", self.fwrite_dio().bit()))
-            .field("fwrite_qio", &format_args!("{}", self.fwrite_qio().bit()))
-            .field(
-                "usr_miso_highpart",
-                &format_args!("{}", self.usr_miso_highpart().bit()),
-            )
-            .field(
-                "usr_mosi_highpart",
-                &format_args!("{}", self.usr_mosi_highpart().bit()),
-            )
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
-            .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
-            .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
-            .field("usr_command", &format_args!("{}", self.usr_command().bit()))
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("fwrite_dual", &self.fwrite_dual())
+            .field("fwrite_quad", &self.fwrite_quad())
+            .field("fwrite_dio", &self.fwrite_dio())
+            .field("fwrite_qio", &self.fwrite_qio())
+            .field("usr_miso_highpart", &self.usr_miso_highpart())
+            .field("usr_mosi_highpart", &self.usr_mosi_highpart())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_mosi", &self.usr_mosi())
+            .field("usr_miso", &self.usr_miso())
+            .field("usr_dummy", &self.usr_dummy())
+            .field("usr_addr", &self.usr_addr())
+            .field("usr_command", &self.usr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/user1.rs b/esp32c6/src/spi1/user1.rs
index 4b36bbf30d..8f28ca2ba4 100644
--- a/esp32c6/src/spi1/user1.rs
+++ b/esp32c6/src/spi1/user1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/user2.rs b/esp32c6/src/spi1/user2.rs
index 382c76224c..4bd67c802f 100644
--- a/esp32c6/src/spi1/user2.rs
+++ b/esp32c6/src/spi1/user2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command."]
     #[inline(always)]
diff --git a/esp32c6/src/spi1/w.rs b/esp32c6/src/spi1/w.rs
index 319a8e0611..43137019f7 100644
--- a/esp32c6/src/spi1/w.rs
+++ b/esp32c6/src/spi1/w.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("W")
-            .field("buf", &format_args!("{}", self.buf().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<W_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("W").field("buf", &self.buf()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/spi2/addr.rs b/esp32c6/src/spi2/addr.rs
index 0429f136d3..a43f100c19 100644
--- a/esp32c6/src/spi2/addr.rs
+++ b/esp32c6/src/spi2/addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR")
-            .field(
-                "usr_addr_value",
-                &format_args!("{}", self.usr_addr_value().bits()),
-            )
+            .field("usr_addr_value", &self.usr_addr_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Address to slave. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/clk_gate.rs b/esp32c6/src/spi2/clk_gate.rs
index c690702c68..c633026011 100644
--- a/esp32c6/src/spi2/clk_gate.rs
+++ b/esp32c6/src/spi2/clk_gate.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "mst_clk_active",
-                &format_args!("{}", self.mst_clk_active().bit()),
-            )
-            .field("mst_clk_sel", &format_args!("{}", self.mst_clk_sel().bit()))
+            .field("clk_en", &self.clk_en())
+            .field("mst_clk_active", &self.mst_clk_active())
+            .field("mst_clk_sel", &self.mst_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable clk gate"]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/clock.rs b/esp32c6/src/spi2/clock.rs
index a980aa1ac0..336dc15885 100644
--- a/esp32c6/src/spi2/clock.rs
+++ b/esp32c6/src/spi2/clock.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field("clkdiv_pre", &format_args!("{}", self.clkdiv_pre().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clkdiv_pre", &self.clkdiv_pre())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/cmd.rs b/esp32c6/src/spi2/cmd.rs
index d9c54a966c..8d8333ec63 100644
--- a/esp32c6/src/spi2/cmd.rs
+++ b/esp32c6/src/spi2/cmd.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field(
-                "conf_bitlen",
-                &format_args!("{}", self.conf_bitlen().bits()),
-            )
-            .field("update", &format_args!("{}", self.update().bit()))
-            .field("usr", &format_args!("{}", self.usr().bit()))
+            .field("conf_bitlen", &self.conf_bitlen())
+            .field("update", &self.update())
+            .field("usr", &self.usr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - Define the APB cycles of SPI_CONF state. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/ctrl.rs b/esp32c6/src/spi2/ctrl.rs
index 13c41ae699..88e92d9320 100644
--- a/esp32c6/src/spi2/ctrl.rs
+++ b/esp32c6/src/spi2/ctrl.rs
@@ -146,37 +146,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("dummy_out", &format_args!("{}", self.dummy_out().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
-            .field("faddr_oct", &format_args!("{}", self.faddr_oct().bit()))
-            .field("fcmd_dual", &format_args!("{}", self.fcmd_dual().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcmd_oct", &format_args!("{}", self.fcmd_oct().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("fread_oct", &format_args!("{}", self.fread_oct().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("hold_pol", &format_args!("{}", self.hold_pol().bit()))
-            .field("wp_pol", &format_args!("{}", self.wp_pol().bit()))
-            .field(
-                "rd_bit_order",
-                &format_args!("{}", self.rd_bit_order().bits()),
-            )
-            .field(
-                "wr_bit_order",
-                &format_args!("{}", self.wr_bit_order().bits()),
-            )
+            .field("dummy_out", &self.dummy_out())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("faddr_quad", &self.faddr_quad())
+            .field("faddr_oct", &self.faddr_oct())
+            .field("fcmd_dual", &self.fcmd_dual())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcmd_oct", &self.fcmd_oct())
+            .field("fread_dual", &self.fread_dual())
+            .field("fread_quad", &self.fread_quad())
+            .field("fread_oct", &self.fread_oct())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("hold_pol", &self.hold_pol())
+            .field("wp_pol", &self.wp_pol())
+            .field("rd_bit_order", &self.rd_bit_order())
+            .field("wr_bit_order", &self.wr_bit_order())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/date.rs b/esp32c6/src/spi2/date.rs
index dfac83b005..9eee534b72 100644
--- a/esp32c6/src/spi2/date.rs
+++ b/esp32c6/src/spi2/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/spi2/din_mode.rs b/esp32c6/src/spi2/din_mode.rs
index 0b4fc0888a..10bf944240 100644
--- a/esp32c6/src/spi2/din_mode.rs
+++ b/esp32c6/src/spi2/din_mode.rs
@@ -81,27 +81,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_MODE")
-            .field("din0_mode", &format_args!("{}", self.din0_mode().bits()))
-            .field("din1_mode", &format_args!("{}", self.din1_mode().bits()))
-            .field("din2_mode", &format_args!("{}", self.din2_mode().bits()))
-            .field("din3_mode", &format_args!("{}", self.din3_mode().bits()))
-            .field("din4_mode", &format_args!("{}", self.din4_mode().bits()))
-            .field("din5_mode", &format_args!("{}", self.din5_mode().bits()))
-            .field("din6_mode", &format_args!("{}", self.din6_mode().bits()))
-            .field("din7_mode", &format_args!("{}", self.din7_mode().bits()))
-            .field(
-                "timing_hclk_active",
-                &format_args!("{}", self.timing_hclk_active().bit()),
-            )
+            .field("din0_mode", &self.din0_mode())
+            .field("din1_mode", &self.din1_mode())
+            .field("din2_mode", &self.din2_mode())
+            .field("din3_mode", &self.din3_mode())
+            .field("din4_mode", &self.din4_mode())
+            .field("din5_mode", &self.din5_mode())
+            .field("din6_mode", &self.din6_mode())
+            .field("din7_mode", &self.din7_mode())
+            .field("timing_hclk_active", &self.timing_hclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/din_num.rs b/esp32c6/src/spi2/din_num.rs
index a9b821a628..56a0d30639 100644
--- a/esp32c6/src/spi2/din_num.rs
+++ b/esp32c6/src/spi2/din_num.rs
@@ -72,23 +72,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_NUM")
-            .field("din0_num", &format_args!("{}", self.din0_num().bits()))
-            .field("din1_num", &format_args!("{}", self.din1_num().bits()))
-            .field("din2_num", &format_args!("{}", self.din2_num().bits()))
-            .field("din3_num", &format_args!("{}", self.din3_num().bits()))
-            .field("din4_num", &format_args!("{}", self.din4_num().bits()))
-            .field("din5_num", &format_args!("{}", self.din5_num().bits()))
-            .field("din6_num", &format_args!("{}", self.din6_num().bits()))
-            .field("din7_num", &format_args!("{}", self.din7_num().bits()))
+            .field("din0_num", &self.din0_num())
+            .field("din1_num", &self.din1_num())
+            .field("din2_num", &self.din2_num())
+            .field("din3_num", &self.din3_num())
+            .field("din4_num", &self.din4_num())
+            .field("din5_num", &self.din5_num())
+            .field("din6_num", &self.din6_num())
+            .field("din7_num", &self.din7_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/dma_conf.rs b/esp32c6/src/spi2/dma_conf.rs
index 2c8ad8198f..573e0e214e 100644
--- a/esp32c6/src/spi2/dma_conf.rs
+++ b/esp32c6/src/spi2/dma_conf.rs
@@ -82,38 +82,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field(
-                "dma_outfifo_empty",
-                &format_args!("{}", self.dma_outfifo_empty().bit()),
-            )
-            .field(
-                "dma_infifo_full",
-                &format_args!("{}", self.dma_infifo_full().bit()),
-            )
-            .field(
-                "dma_slv_seg_trans_en",
-                &format_args!("{}", self.dma_slv_seg_trans_en().bit()),
-            )
-            .field(
-                "slv_rx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_rx_seg_trans_clr_en().bit()),
-            )
-            .field(
-                "slv_tx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_tx_seg_trans_clr_en().bit()),
-            )
-            .field("rx_eof_en", &format_args!("{}", self.rx_eof_en().bit()))
-            .field("dma_rx_ena", &format_args!("{}", self.dma_rx_ena().bit()))
-            .field("dma_tx_ena", &format_args!("{}", self.dma_tx_ena().bit()))
+            .field("dma_outfifo_empty", &self.dma_outfifo_empty())
+            .field("dma_infifo_full", &self.dma_infifo_full())
+            .field("dma_slv_seg_trans_en", &self.dma_slv_seg_trans_en())
+            .field("slv_rx_seg_trans_clr_en", &self.slv_rx_seg_trans_clr_en())
+            .field("slv_tx_seg_trans_clr_en", &self.slv_tx_seg_trans_clr_en())
+            .field("rx_eof_en", &self.rx_eof_en())
+            .field("dma_rx_ena", &self.dma_rx_ena())
+            .field("dma_tx_ena", &self.dma_tx_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/dma_int_ena.rs b/esp32c6/src/spi2/dma_int_ena.rs
index 5a2520a556..57d74d21ae 100644
--- a/esp32c6/src/spi2/dma_int_ena.rs
+++ b/esp32c6/src/spi2/dma_int_ena.rs
@@ -197,69 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ENA")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/dma_int_raw.rs b/esp32c6/src/spi2/dma_int_raw.rs
index 4e27e4ae69..c8e69e9935 100644
--- a/esp32c6/src/spi2/dma_int_raw.rs
+++ b/esp32c6/src/spi2/dma_int_raw.rs
@@ -197,69 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_RAW")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/dma_int_st.rs b/esp32c6/src/spi2/dma_int_st.rs
index 424ec36870..5143fbdd5e 100644
--- a/esp32c6/src/spi2/dma_int_st.rs
+++ b/esp32c6/src/spi2/dma_int_st.rs
@@ -153,69 +153,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ST")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_INT_ST_SPEC;
 impl crate::RegisterSpec for DMA_INT_ST_SPEC {
diff --git a/esp32c6/src/spi2/dout_mode.rs b/esp32c6/src/spi2/dout_mode.rs
index 8de08decf3..87a510d71b 100644
--- a/esp32c6/src/spi2/dout_mode.rs
+++ b/esp32c6/src/spi2/dout_mode.rs
@@ -79,24 +79,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOUT_MODE")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bit()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bit()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bit()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bit()))
-            .field("dout4_mode", &format_args!("{}", self.dout4_mode().bit()))
-            .field("dout5_mode", &format_args!("{}", self.dout5_mode().bit()))
-            .field("dout6_mode", &format_args!("{}", self.dout6_mode().bit()))
-            .field("dout7_mode", &format_args!("{}", self.dout7_mode().bit()))
-            .field("d_dqs_mode", &format_args!("{}", self.d_dqs_mode().bit()))
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
+            .field("dout4_mode", &self.dout4_mode())
+            .field("dout5_mode", &self.dout5_mode())
+            .field("dout6_mode", &self.dout6_mode())
+            .field("dout7_mode", &self.dout7_mode())
+            .field("d_dqs_mode", &self.d_dqs_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/misc.rs b/esp32c6/src/spi2/misc.rs
index 1537a1ca6c..1a2a256246 100644
--- a/esp32c6/src/spi2/misc.rs
+++ b/esp32c6/src/spi2/misc.rs
@@ -151,53 +151,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
-            .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
-            .field("cs2_dis", &format_args!("{}", self.cs2_dis().bit()))
-            .field("cs3_dis", &format_args!("{}", self.cs3_dis().bit()))
-            .field("cs4_dis", &format_args!("{}", self.cs4_dis().bit()))
-            .field("cs5_dis", &format_args!("{}", self.cs5_dis().bit()))
-            .field("ck_dis", &format_args!("{}", self.ck_dis().bit()))
-            .field(
-                "master_cs_pol",
-                &format_args!("{}", self.master_cs_pol().bits()),
-            )
-            .field(
-                "clk_data_dtr_en",
-                &format_args!("{}", self.clk_data_dtr_en().bit()),
-            )
-            .field("data_dtr_en", &format_args!("{}", self.data_dtr_en().bit()))
-            .field("addr_dtr_en", &format_args!("{}", self.addr_dtr_en().bit()))
-            .field("cmd_dtr_en", &format_args!("{}", self.cmd_dtr_en().bit()))
-            .field(
-                "slave_cs_pol",
-                &format_args!("{}", self.slave_cs_pol().bit()),
-            )
-            .field(
-                "dqs_idle_edge",
-                &format_args!("{}", self.dqs_idle_edge().bit()),
-            )
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
-            .field(
-                "quad_din_pin_swap",
-                &format_args!("{}", self.quad_din_pin_swap().bit()),
-            )
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("cs2_dis", &self.cs2_dis())
+            .field("cs3_dis", &self.cs3_dis())
+            .field("cs4_dis", &self.cs4_dis())
+            .field("cs5_dis", &self.cs5_dis())
+            .field("ck_dis", &self.ck_dis())
+            .field("master_cs_pol", &self.master_cs_pol())
+            .field("clk_data_dtr_en", &self.clk_data_dtr_en())
+            .field("data_dtr_en", &self.data_dtr_en())
+            .field("addr_dtr_en", &self.addr_dtr_en())
+            .field("cmd_dtr_en", &self.cmd_dtr_en())
+            .field("slave_cs_pol", &self.slave_cs_pol())
+            .field("dqs_idle_edge", &self.dqs_idle_edge())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
+            .field("quad_din_pin_swap", &self.quad_din_pin_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/ms_dlen.rs b/esp32c6/src/spi2/ms_dlen.rs
index 116939582c..94a2915785 100644
--- a/esp32c6/src/spi2/ms_dlen.rs
+++ b/esp32c6/src/spi2/ms_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MS_DLEN")
-            .field(
-                "ms_data_bitlen",
-                &format_args!("{}", self.ms_data_bitlen().bits()),
-            )
+            .field("ms_data_bitlen", &self.ms_data_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MS_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/slave.rs b/esp32c6/src/spi2/slave.rs
index 5b32454807..3e663dd072 100644
--- a/esp32c6/src/spi2/slave.rs
+++ b/esp32c6/src/spi2/slave.rs
@@ -109,47 +109,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
-            .field("clk_mode_13", &format_args!("{}", self.clk_mode_13().bit()))
-            .field(
-                "rsck_data_out",
-                &format_args!("{}", self.rsck_data_out().bit()),
-            )
-            .field(
-                "slv_rddma_bitlen_en",
-                &format_args!("{}", self.slv_rddma_bitlen_en().bit()),
-            )
-            .field(
-                "slv_wrdma_bitlen_en",
-                &format_args!("{}", self.slv_wrdma_bitlen_en().bit()),
-            )
-            .field(
-                "slv_rdbuf_bitlen_en",
-                &format_args!("{}", self.slv_rdbuf_bitlen_en().bit()),
-            )
-            .field(
-                "slv_wrbuf_bitlen_en",
-                &format_args!("{}", self.slv_wrbuf_bitlen_en().bit()),
-            )
-            .field(
-                "dma_seg_magic_value",
-                &format_args!("{}", self.dma_seg_magic_value().bits()),
-            )
-            .field("mode", &format_args!("{}", self.mode().bit()))
-            .field("usr_conf", &format_args!("{}", self.usr_conf().bit()))
-            .field(
-                "mst_fd_wait_dma_tx_data",
-                &format_args!("{}", self.mst_fd_wait_dma_tx_data().bit()),
-            )
+            .field("clk_mode", &self.clk_mode())
+            .field("clk_mode_13", &self.clk_mode_13())
+            .field("rsck_data_out", &self.rsck_data_out())
+            .field("slv_rddma_bitlen_en", &self.slv_rddma_bitlen_en())
+            .field("slv_wrdma_bitlen_en", &self.slv_wrdma_bitlen_en())
+            .field("slv_rdbuf_bitlen_en", &self.slv_rdbuf_bitlen_en())
+            .field("slv_wrbuf_bitlen_en", &self.slv_wrbuf_bitlen_en())
+            .field("dma_seg_magic_value", &self.dma_seg_magic_value())
+            .field("mode", &self.mode())
+            .field("usr_conf", &self.usr_conf())
+            .field("mst_fd_wait_dma_tx_data", &self.mst_fd_wait_dma_tx_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/slave1.rs b/esp32c6/src/spi2/slave1.rs
index 7e216d9f86..98ad1b4b32 100644
--- a/esp32c6/src/spi2/slave1.rs
+++ b/esp32c6/src/spi2/slave1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE1")
-            .field(
-                "slv_data_bitlen",
-                &format_args!("{}", self.slv_data_bitlen().bits()),
-            )
-            .field(
-                "slv_last_command",
-                &format_args!("{}", self.slv_last_command().bits()),
-            )
-            .field(
-                "slv_last_addr",
-                &format_args!("{}", self.slv_last_addr().bits()),
-            )
+            .field("slv_data_bitlen", &self.slv_data_bitlen())
+            .field("slv_last_command", &self.slv_last_command())
+            .field("slv_last_addr", &self.slv_last_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - The transferred data bit length in SPI slave FD and HD mode."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/user.rs b/esp32c6/src/spi2/user.rs
index 61f673a063..e5405195fb 100644
--- a/esp32c6/src/spi2/user.rs
+++ b/esp32c6/src/spi2/user.rs
@@ -193,48 +193,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("doutdin", &format_args!("{}", self.doutdin().bit()))
-            .field("qpi_mode", &format_args!("{}", self.qpi_mode().bit()))
-            .field("opi_mode", &format_args!("{}", self.opi_mode().bit()))
-            .field("tsck_i_edge", &format_args!("{}", self.tsck_i_edge().bit()))
-            .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
-            .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
-            .field("rsck_i_edge", &format_args!("{}", self.rsck_i_edge().bit()))
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
-            .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
-            .field("fwrite_oct", &format_args!("{}", self.fwrite_oct().bit()))
-            .field(
-                "usr_conf_nxt",
-                &format_args!("{}", self.usr_conf_nxt().bit()),
-            )
-            .field("sio", &format_args!("{}", self.sio().bit()))
-            .field(
-                "usr_miso_highpart",
-                &format_args!("{}", self.usr_miso_highpart().bit()),
-            )
-            .field(
-                "usr_mosi_highpart",
-                &format_args!("{}", self.usr_mosi_highpart().bit()),
-            )
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
-            .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
-            .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
-            .field("usr_command", &format_args!("{}", self.usr_command().bit()))
+            .field("doutdin", &self.doutdin())
+            .field("qpi_mode", &self.qpi_mode())
+            .field("opi_mode", &self.opi_mode())
+            .field("tsck_i_edge", &self.tsck_i_edge())
+            .field("cs_hold", &self.cs_hold())
+            .field("cs_setup", &self.cs_setup())
+            .field("rsck_i_edge", &self.rsck_i_edge())
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("fwrite_dual", &self.fwrite_dual())
+            .field("fwrite_quad", &self.fwrite_quad())
+            .field("fwrite_oct", &self.fwrite_oct())
+            .field("usr_conf_nxt", &self.usr_conf_nxt())
+            .field("sio", &self.sio())
+            .field("usr_miso_highpart", &self.usr_miso_highpart())
+            .field("usr_mosi_highpart", &self.usr_mosi_highpart())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_mosi", &self.usr_mosi())
+            .field("usr_miso", &self.usr_miso())
+            .field("usr_dummy", &self.usr_dummy())
+            .field("usr_addr", &self.usr_addr())
+            .field("usr_command", &self.usr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/user1.rs b/esp32c6/src/spi2/user1.rs
index acb564ca07..1dd612d409 100644
--- a/esp32c6/src/spi2/user1.rs
+++ b/esp32c6/src/spi2/user1.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "mst_wfull_err_end_en",
-                &format_args!("{}", self.mst_wfull_err_end_en().bit()),
-            )
-            .field(
-                "cs_setup_time",
-                &format_args!("{}", self.cs_setup_time().bits()),
-            )
-            .field(
-                "cs_hold_time",
-                &format_args!("{}", self.cs_hold_time().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("mst_wfull_err_end_en", &self.mst_wfull_err_end_en())
+            .field("cs_setup_time", &self.cs_setup_time())
+            .field("cs_hold_time", &self.cs_hold_time())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/user2.rs b/esp32c6/src/spi2/user2.rs
index 065c536363..c2d5092cd2 100644
--- a/esp32c6/src/spi2/user2.rs
+++ b/esp32c6/src/spi2/user2.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "mst_rempty_err_end_en",
-                &format_args!("{}", self.mst_rempty_err_end_en().bit()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("mst_rempty_err_end_en", &self.mst_rempty_err_end_en())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32c6/src/spi2/w.rs b/esp32c6/src/spi2/w.rs
index bd1588a6f2..016fb59d7c 100644
--- a/esp32c6/src/spi2/w.rs
+++ b/esp32c6/src/spi2/w.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("W")
-            .field("buf", &format_args!("{}", self.buf().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<W_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("W").field("buf", &self.buf()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/systimer/conf.rs b/esp32c6/src/systimer/conf.rs
index dc9795ba23..8824e41e55 100644
--- a/esp32c6/src/systimer/conf.rs
+++ b/esp32c6/src/systimer/conf.rs
@@ -116,57 +116,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field(
-                "systimer_clk_fo",
-                &format_args!("{}", self.systimer_clk_fo().bit()),
-            )
-            .field("etm_en", &format_args!("{}", self.etm_en().bit()))
-            .field(
-                "target2_work_en",
-                &format_args!("{}", self.target2_work_en().bit()),
-            )
-            .field(
-                "target1_work_en",
-                &format_args!("{}", self.target1_work_en().bit()),
-            )
-            .field(
-                "target0_work_en",
-                &format_args!("{}", self.target0_work_en().bit()),
-            )
+            .field("systimer_clk_fo", &self.systimer_clk_fo())
+            .field("etm_en", &self.etm_en())
+            .field("target2_work_en", &self.target2_work_en())
+            .field("target1_work_en", &self.target1_work_en())
+            .field("target0_work_en", &self.target0_work_en())
             .field(
                 "timer_unit1_core1_stall_en",
-                &format_args!("{}", self.timer_unit1_core1_stall_en().bit()),
+                &self.timer_unit1_core1_stall_en(),
             )
             .field(
                 "timer_unit1_core0_stall_en",
-                &format_args!("{}", self.timer_unit1_core0_stall_en().bit()),
+                &self.timer_unit1_core0_stall_en(),
             )
             .field(
                 "timer_unit0_core1_stall_en",
-                &format_args!("{}", self.timer_unit0_core1_stall_en().bit()),
+                &self.timer_unit0_core1_stall_en(),
             )
             .field(
                 "timer_unit0_core0_stall_en",
-                &format_args!("{}", self.timer_unit0_core0_stall_en().bit()),
+                &self.timer_unit0_core0_stall_en(),
             )
-            .field(
-                "timer_unit1_work_en",
-                &format_args!("{}", self.timer_unit1_work_en().bit()),
-            )
-            .field(
-                "timer_unit0_work_en",
-                &format_args!("{}", self.timer_unit0_work_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("timer_unit1_work_en", &self.timer_unit1_work_en())
+            .field("timer_unit0_work_en", &self.timer_unit0_work_en())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - systimer clock force on"]
     #[inline(always)]
diff --git a/esp32c6/src/systimer/date.rs b/esp32c6/src/systimer/date.rs
index 9e89ffaebb..629d8212a8 100644
--- a/esp32c6/src/systimer/date.rs
+++ b/esp32c6/src/systimer/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/systimer/int_ena.rs b/esp32c6/src/systimer/int_ena.rs
index 9afbd67324..bf39753584 100644
--- a/esp32c6/src/systimer/int_ena.rs
+++ b/esp32c6/src/systimer/int_ena.rs
@@ -42,18 +42,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "interupt(0-2) enable"]
     #[doc = ""]
diff --git a/esp32c6/src/systimer/int_raw.rs b/esp32c6/src/systimer/int_raw.rs
index 9487c30025..395cb8187f 100644
--- a/esp32c6/src/systimer/int_raw.rs
+++ b/esp32c6/src/systimer/int_raw.rs
@@ -42,18 +42,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "interupt(0-2) raw"]
     #[doc = ""]
diff --git a/esp32c6/src/systimer/int_st.rs b/esp32c6/src/systimer/int_st.rs
index 4c4d3c12f8..1dc503012b 100644
--- a/esp32c6/src/systimer/int_st.rs
+++ b/esp32c6/src/systimer/int_st.rs
@@ -38,18 +38,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "systimer interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/systimer/real_target/hi.rs b/esp32c6/src/systimer/real_target/hi.rs
index e37661f89a..10d4966ea0 100644
--- a/esp32c6/src/systimer/real_target/hi.rs
+++ b/esp32c6/src/systimer/real_target/hi.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi_ro", &format_args!("{}", self.hi_ro().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi_ro", &self.hi_ro()).finish()
     }
 }
 #[doc = "system timer comp0 actual target value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c6/src/systimer/real_target/lo.rs b/esp32c6/src/systimer/real_target/lo.rs
index 6ba16447eb..2a8623e63b 100644
--- a/esp32c6/src/systimer/real_target/lo.rs
+++ b/esp32c6/src/systimer/real_target/lo.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo_ro", &format_args!("{}", self.lo_ro().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo_ro", &self.lo_ro()).finish()
     }
 }
 #[doc = "system timer comp0 actual target value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c6/src/systimer/target_conf.rs b/esp32c6/src/systimer/target_conf.rs
index 351218e2ba..48184bd1f3 100644
--- a/esp32c6/src/systimer/target_conf.rs
+++ b/esp32c6/src/systimer/target_conf.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TARGET_CONF")
-            .field("period", &format_args!("{}", self.period().bits()))
-            .field("period_mode", &format_args!("{}", self.period_mode().bit()))
-            .field(
-                "timer_unit_sel",
-                &format_args!("{}", self.timer_unit_sel().bit()),
-            )
+            .field("period", &self.period())
+            .field("period_mode", &self.period_mode())
+            .field("timer_unit_sel", &self.timer_unit_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TARGET_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - target0 period"]
     #[inline(always)]
diff --git a/esp32c6/src/systimer/trgt/hi.rs b/esp32c6/src/systimer/trgt/hi.rs
index 9ba19aedd7..1bbcc8532f 100644
--- a/esp32c6/src/systimer/trgt/hi.rs
+++ b/esp32c6/src/systimer/trgt/hi.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/systimer/trgt/lo.rs b/esp32c6/src/systimer/trgt/lo.rs
index cf5618b115..870fcb7923 100644
--- a/esp32c6/src/systimer/trgt/lo.rs
+++ b/esp32c6/src/systimer/trgt/lo.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/systimer/unit_op.rs b/esp32c6/src/systimer/unit_op.rs
index 161504c169..5a004338a8 100644
--- a/esp32c6/src/systimer/unit_op.rs
+++ b/esp32c6/src/systimer/unit_op.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UNIT_OP")
-            .field("value_valid", &format_args!("{}", self.value_valid().bit()))
+            .field("value_valid", &self.value_valid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UNIT_OP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - update timer_unit0"]
     #[inline(always)]
diff --git a/esp32c6/src/systimer/unit_value/hi.rs b/esp32c6/src/systimer/unit_value/hi.rs
index 3cd25b4d55..10523f249f 100644
--- a/esp32c6/src/systimer/unit_value/hi.rs
+++ b/esp32c6/src/systimer/unit_value/hi.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HI")
-            .field("value_hi", &format_args!("{}", self.value_hi().bits()))
+            .field("value_hi", &self.value_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "system timer unit0 value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HI_SPEC;
 impl crate::RegisterSpec for HI_SPEC {
diff --git a/esp32c6/src/systimer/unit_value/lo.rs b/esp32c6/src/systimer/unit_value/lo.rs
index a60743963d..92c3f4e991 100644
--- a/esp32c6/src/systimer/unit_value/lo.rs
+++ b/esp32c6/src/systimer/unit_value/lo.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LO")
-            .field("value_lo", &format_args!("{}", self.value_lo().bits()))
+            .field("value_lo", &self.value_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "system timer unit0 value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LO_SPEC;
 impl crate::RegisterSpec for LO_SPEC {
diff --git a/esp32c6/src/systimer/unitload/hi.rs b/esp32c6/src/systimer/unitload/hi.rs
index 3d663b8225..a758293265 100644
--- a/esp32c6/src/systimer/unitload/hi.rs
+++ b/esp32c6/src/systimer/unitload/hi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - timer unit0 load high 20 bits"]
     #[inline(always)]
diff --git a/esp32c6/src/systimer/unitload/lo.rs b/esp32c6/src/systimer/unitload/lo.rs
index 15e267cf3c..e01c2efb83 100644
--- a/esp32c6/src/systimer/unitload/lo.rs
+++ b/esp32c6/src/systimer/unitload/lo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - timer unit0 load low 32 bits"]
     #[inline(always)]
diff --git a/esp32c6/src/tee/clock_gate.rs b/esp32c6/src/tee/clock_gate.rs
index b2c147f4a9..0c07ea99d2 100644
--- a/esp32c6/src/tee/clock_gate.rs
+++ b/esp32c6/src/tee/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_clk_en"]
     #[inline(always)]
diff --git a/esp32c6/src/tee/date.rs b/esp32c6/src/tee/date.rs
index 4b1f6a075c..dba4e88829 100644
--- a/esp32c6/src/tee/date.rs
+++ b/esp32c6/src/tee/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/tee/m_mode_ctrl.rs b/esp32c6/src/tee/m_mode_ctrl.rs
index d67dc483be..59ebfc27ec 100644
--- a/esp32c6/src/tee/m_mode_ctrl.rs
+++ b/esp32c6/src/tee/m_mode_ctrl.rs
@@ -100,16 +100,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("M_MODE_CTRL")
-            .field("mode", &format_args!("{}", self.mode().bits()))
+            .field("mode", &self.mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MODE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode"]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/int_ena_timers.rs b/esp32c6/src/timg0/int_ena_timers.rs
index 8171c5599d..851aed4658 100644
--- a/esp32c6/src/timg0/int_ena_timers.rs
+++ b/esp32c6/src/timg0/int_ena_timers.rs
@@ -41,17 +41,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the TIMG_T(0-0)_INT interrupt."]
     #[doc = ""]
diff --git a/esp32c6/src/timg0/int_raw_timers.rs b/esp32c6/src/timg0/int_raw_timers.rs
index b0a2087cba..4774f3725d 100644
--- a/esp32c6/src/timg0/int_raw_timers.rs
+++ b/esp32c6/src/timg0/int_raw_timers.rs
@@ -35,17 +35,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_TIMERS_SPEC;
 impl crate::RegisterSpec for INT_RAW_TIMERS_SPEC {
diff --git a/esp32c6/src/timg0/int_st_timers.rs b/esp32c6/src/timg0/int_st_timers.rs
index f79f0e92cf..81866103ca 100644
--- a/esp32c6/src/timg0/int_st_timers.rs
+++ b/esp32c6/src/timg0/int_st_timers.rs
@@ -35,17 +35,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_TIMERS_SPEC;
 impl crate::RegisterSpec for INT_ST_TIMERS_SPEC {
diff --git a/esp32c6/src/timg0/ntimers_date.rs b/esp32c6/src/timg0/ntimers_date.rs
index b2ff41af46..8945775cb4 100644
--- a/esp32c6/src/timg0/ntimers_date.rs
+++ b/esp32c6/src/timg0/ntimers_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NTIMERS_DATE")
-            .field(
-                "ntimgs_date",
-                &format_args!("{}", self.ntimgs_date().bits()),
-            )
+            .field("ntimgs_date", &self.ntimgs_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NTIMERS_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Timer version control register"]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/regclk.rs b/esp32c6/src/timg0/regclk.rs
index 0f90e1dc73..7449dd5019 100644
--- a/esp32c6/src/timg0/regclk.rs
+++ b/esp32c6/src/timg0/regclk.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGCLK")
-            .field("etm_en", &format_args!("{}", self.etm_en().bit()))
-            .field(
-                "wdt_clk_is_active",
-                &format_args!("{}", self.wdt_clk_is_active().bit()),
-            )
-            .field(
-                "timer_clk_is_active",
-                &format_args!("{}", self.timer_clk_is_active().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("etm_en", &self.etm_en())
+            .field("wdt_clk_is_active", &self.wdt_clk_is_active())
+            .field("timer_clk_is_active", &self.timer_clk_is_active())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - enable timer's etm task and event"]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/rtccalicfg.rs b/esp32c6/src/timg0/rtccalicfg.rs
index 25a598caa6..cac5ef6711 100644
--- a/esp32c6/src/timg0/rtccalicfg.rs
+++ b/esp32c6/src/timg0/rtccalicfg.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG")
-            .field(
-                "rtc_cali_start_cycling",
-                &format_args!("{}", self.rtc_cali_start_cycling().bit()),
-            )
-            .field(
-                "rtc_cali_clk_sel",
-                &format_args!("{}", self.rtc_cali_clk_sel().bits()),
-            )
-            .field(
-                "rtc_cali_rdy",
-                &format_args!("{}", self.rtc_cali_rdy().bit()),
-            )
-            .field(
-                "rtc_cali_max",
-                &format_args!("{}", self.rtc_cali_max().bits()),
-            )
-            .field(
-                "rtc_cali_start",
-                &format_args!("{}", self.rtc_cali_start().bit()),
-            )
+            .field("rtc_cali_start_cycling", &self.rtc_cali_start_cycling())
+            .field("rtc_cali_clk_sel", &self.rtc_cali_clk_sel())
+            .field("rtc_cali_rdy", &self.rtc_cali_rdy())
+            .field("rtc_cali_max", &self.rtc_cali_max())
+            .field("rtc_cali_start", &self.rtc_cali_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - 0: one-shot frequency calculation,1: periodic frequency calculation,"]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/rtccalicfg1.rs b/esp32c6/src/timg0/rtccalicfg1.rs
index 318e8b0ff7..fc1a1dee84 100644
--- a/esp32c6/src/timg0/rtccalicfg1.rs
+++ b/esp32c6/src/timg0/rtccalicfg1.rs
@@ -22,21 +22,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("RTCCALICFG1")
             .field(
                 "rtc_cali_cycling_data_vld",
-                &format_args!("{}", self.rtc_cali_cycling_data_vld().bit()),
-            )
-            .field(
-                "rtc_cali_value",
-                &format_args!("{}", self.rtc_cali_value().bits()),
+                &self.rtc_cali_cycling_data_vld(),
             )
+            .field("rtc_cali_value", &self.rtc_cali_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC calibration configure1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtccalicfg1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTCCALICFG1_SPEC;
 impl crate::RegisterSpec for RTCCALICFG1_SPEC {
diff --git a/esp32c6/src/timg0/rtccalicfg2.rs b/esp32c6/src/timg0/rtccalicfg2.rs
index a0ea39a67b..2142857b29 100644
--- a/esp32c6/src/timg0/rtccalicfg2.rs
+++ b/esp32c6/src/timg0/rtccalicfg2.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG2")
-            .field(
-                "rtc_cali_timeout",
-                &format_args!("{}", self.rtc_cali_timeout().bit()),
-            )
-            .field(
-                "rtc_cali_timeout_rst_cnt",
-                &format_args!("{}", self.rtc_cali_timeout_rst_cnt().bits()),
-            )
-            .field(
-                "rtc_cali_timeout_thres",
-                &format_args!("{}", self.rtc_cali_timeout_thres().bits()),
-            )
+            .field("rtc_cali_timeout", &self.rtc_cali_timeout())
+            .field("rtc_cali_timeout_rst_cnt", &self.rtc_cali_timeout_rst_cnt())
+            .field("rtc_cali_timeout_thres", &self.rtc_cali_timeout_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:6 - Cycles that release calibration timeout reset"]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/t/alarmhi.rs b/esp32c6/src/timg0/t/alarmhi.rs
index edd0b2a2a2..fcba374986 100644
--- a/esp32c6/src/timg0/t/alarmhi.rs
+++ b/esp32c6/src/timg0/t/alarmhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMHI")
-            .field("alarm_hi", &format_args!("{}", self.alarm_hi().bits()))
+            .field("alarm_hi", &self.alarm_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Timer %s alarm trigger time-base counter value, high 22 bits."]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/t/alarmlo.rs b/esp32c6/src/timg0/t/alarmlo.rs
index 498db1e4af..49ecd50884 100644
--- a/esp32c6/src/timg0/t/alarmlo.rs
+++ b/esp32c6/src/timg0/t/alarmlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMLO")
-            .field("alarm_lo", &format_args!("{}", self.alarm_lo().bits()))
+            .field("alarm_lo", &self.alarm_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Timer %s alarm trigger time-base counter value, low 32 bits."]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/t/config.rs b/esp32c6/src/timg0/t/config.rs
index 4f94cffd85..498be19d87 100644
--- a/esp32c6/src/timg0/t/config.rs
+++ b/esp32c6/src/timg0/t/config.rs
@@ -64,21 +64,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG")
-            .field("use_xtal", &format_args!("{}", self.use_xtal().bit()))
-            .field("alarm_en", &format_args!("{}", self.alarm_en().bit()))
-            .field("divider", &format_args!("{}", self.divider().bits()))
-            .field("autoreload", &format_args!("{}", self.autoreload().bit()))
-            .field("increase", &format_args!("{}", self.increase().bit()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("use_xtal", &self.use_xtal())
+            .field("alarm_en", &self.alarm_en())
+            .field("divider", &self.divider())
+            .field("autoreload", &self.autoreload())
+            .field("increase", &self.increase())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/t/hi.rs b/esp32c6/src/timg0/t/hi.rs
index 0a24b62b63..7bf96de0ea 100644
--- a/esp32c6/src/timg0/t/hi.rs
+++ b/esp32c6/src/timg0/t/hi.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
     }
 }
 #[doc = "Timer %s current value, high 22 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c6/src/timg0/t/lo.rs b/esp32c6/src/timg0/t/lo.rs
index 973812bd12..40cb61bb7b 100644
--- a/esp32c6/src/timg0/t/lo.rs
+++ b/esp32c6/src/timg0/t/lo.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
     }
 }
 #[doc = "Timer %s current value, low 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32c6/src/timg0/t/loadhi.rs b/esp32c6/src/timg0/t/loadhi.rs
index a069a77d70..14ce76e51c 100644
--- a/esp32c6/src/timg0/t/loadhi.rs
+++ b/esp32c6/src/timg0/t/loadhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADHI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - High 22 bits of the value that a reload will load onto timer %s time-base counter."]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/t/loadlo.rs b/esp32c6/src/timg0/t/loadlo.rs
index cd932cce0b..ed74e0c51d 100644
--- a/esp32c6/src/timg0/t/loadlo.rs
+++ b/esp32c6/src/timg0/t/loadlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADLO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Low 32 bits of the value that a reload will load onto timer %s time-base Counter."]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/t/update.rs b/esp32c6/src/timg0/t/update.rs
index dda84cfacc..bff3589c08 100644
--- a/esp32c6/src/timg0/t/update.rs
+++ b/esp32c6/src/timg0/t/update.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE")
-            .field("update", &format_args!("{}", self.update().bit()))
+            .field("update", &self.update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched."]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/wdtconfig0.rs b/esp32c6/src/timg0/wdtconfig0.rs
index e45eea5e24..e8c89534d7 100644
--- a/esp32c6/src/timg0/wdtconfig0.rs
+++ b/esp32c6/src/timg0/wdtconfig0.rs
@@ -109,44 +109,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG0")
-            .field(
-                "wdt_appcpu_reset_en",
-                &format_args!("{}", self.wdt_appcpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field(
-                "wdt_use_xtal",
-                &format_args!("{}", self.wdt_use_xtal().bit()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_use_xtal", &self.wdt_use_xtal())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - WDT reset CPU enable."]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/wdtconfig1.rs b/esp32c6/src/timg0/wdtconfig1.rs
index 29740ede70..225f2e7355 100644
--- a/esp32c6/src/timg0/wdtconfig1.rs
+++ b/esp32c6/src/timg0/wdtconfig1.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG1")
-            .field(
-                "wdt_clk_prescale",
-                &format_args!("{}", self.wdt_clk_prescale().bits()),
-            )
+            .field("wdt_clk_prescale", &self.wdt_clk_prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, WDT 's clock divider counter will be reset."]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/wdtconfig2.rs b/esp32c6/src/timg0/wdtconfig2.rs
index f6646544fa..70947ea581 100644
--- a/esp32c6/src/timg0/wdtconfig2.rs
+++ b/esp32c6/src/timg0/wdtconfig2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG2")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 0 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/wdtconfig3.rs b/esp32c6/src/timg0/wdtconfig3.rs
index da0cf49ce2..63b4ed60f6 100644
--- a/esp32c6/src/timg0/wdtconfig3.rs
+++ b/esp32c6/src/timg0/wdtconfig3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG3")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 1 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/wdtconfig4.rs b/esp32c6/src/timg0/wdtconfig4.rs
index 2bbbc5bfe8..d132842f1f 100644
--- a/esp32c6/src/timg0/wdtconfig4.rs
+++ b/esp32c6/src/timg0/wdtconfig4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG4")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 2 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/wdtconfig5.rs b/esp32c6/src/timg0/wdtconfig5.rs
index 661482c54b..d101561533 100644
--- a/esp32c6/src/timg0/wdtconfig5.rs
+++ b/esp32c6/src/timg0/wdtconfig5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG5")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 3 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32c6/src/timg0/wdtwprotect.rs b/esp32c6/src/timg0/wdtwprotect.rs
index 44efc107f3..ca73442322 100644
--- a/esp32c6/src/timg0/wdtwprotect.rs
+++ b/esp32c6/src/timg0/wdtwprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTWPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTWPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - If the register contains a different value than its reset value, write protection is enabled."]
     #[inline(always)]
diff --git a/esp32c6/src/trace/clock_gate.rs b/esp32c6/src/trace/clock_gate.rs
index 9396387567..1798054b1a 100644
--- a/esp32c6/src/trace/clock_gate.rs
+++ b/esp32c6/src/trace/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable clock gate when access all registers in this module."]
     #[inline(always)]
diff --git a/esp32c6/src/trace/date.rs b/esp32c6/src/trace/date.rs
index 222105ff2e..f4068dc68f 100644
--- a/esp32c6/src/trace/date.rs
+++ b/esp32c6/src/trace/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/trace/fifo_status.rs b/esp32c6/src/trace/fifo_status.rs
index ac231abf3f..3729545fa7 100644
--- a/esp32c6/src/trace/fifo_status.rs
+++ b/esp32c6/src/trace/fifo_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_STATUS")
-            .field("fifo_empty", &format_args!("{}", self.fifo_empty().bit()))
-            .field("work_status", &format_args!("{}", self.work_status().bit()))
+            .field("fifo_empty", &self.fifo_empty())
+            .field("work_status", &self.work_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "fifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_STATUS_SPEC;
 impl crate::RegisterSpec for FIFO_STATUS_SPEC {
diff --git a/esp32c6/src/trace/intr_ena.rs b/esp32c6/src/trace/intr_ena.rs
index b5a4e078fe..e225fd8298 100644
--- a/esp32c6/src/trace/intr_ena.rs
+++ b/esp32c6/src/trace/intr_ena.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_ENA")
-            .field(
-                "fifo_overflow_intr_ena",
-                &format_args!("{}", self.fifo_overflow_intr_ena().bit()),
-            )
-            .field(
-                "mem_full_intr_ena",
-                &format_args!("{}", self.mem_full_intr_ena().bit()),
-            )
+            .field("fifo_overflow_intr_ena", &self.fifo_overflow_intr_ena())
+            .field("mem_full_intr_ena", &self.mem_full_intr_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 enable fifo_overflow interrupt"]
     #[inline(always)]
diff --git a/esp32c6/src/trace/intr_raw.rs b/esp32c6/src/trace/intr_raw.rs
index 83cb40c5ec..1393d7f17a 100644
--- a/esp32c6/src/trace/intr_raw.rs
+++ b/esp32c6/src/trace/intr_raw.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_RAW")
-            .field(
-                "fifo_overflow_intr_raw",
-                &format_args!("{}", self.fifo_overflow_intr_raw().bit()),
-            )
-            .field(
-                "mem_full_intr_raw",
-                &format_args!("{}", self.mem_full_intr_raw().bit()),
-            )
+            .field("fifo_overflow_intr_raw", &self.fifo_overflow_intr_raw())
+            .field("mem_full_intr_raw", &self.mem_full_intr_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_RAW_SPEC;
 impl crate::RegisterSpec for INTR_RAW_SPEC {
diff --git a/esp32c6/src/trace/mem_current_addr.rs b/esp32c6/src/trace/mem_current_addr.rs
index 854038cd82..611af268e9 100644
--- a/esp32c6/src/trace/mem_current_addr.rs
+++ b/esp32c6/src/trace/mem_current_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CURRENT_ADDR")
-            .field(
-                "mem_current_addr",
-                &format_args!("{}", self.mem_current_addr().bits()),
-            )
+            .field("mem_current_addr", &self.mem_current_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CURRENT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem current addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_current_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_CURRENT_ADDR_SPEC;
 impl crate::RegisterSpec for MEM_CURRENT_ADDR_SPEC {
diff --git a/esp32c6/src/trace/mem_end_addr.rs b/esp32c6/src/trace/mem_end_addr.rs
index 78675b80a6..de089e6fdb 100644
--- a/esp32c6/src/trace/mem_end_addr.rs
+++ b/esp32c6/src/trace/mem_end_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_END_ADDR")
-            .field(
-                "mem_end_addr",
-                &format_args!("{}", self.mem_end_addr().bits()),
-            )
+            .field("mem_end_addr", &self.mem_end_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_END_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The end address of trace memory"]
     #[inline(always)]
diff --git a/esp32c6/src/trace/mem_start_addr.rs b/esp32c6/src/trace/mem_start_addr.rs
index 4528e0e3df..f6b8320336 100644
--- a/esp32c6/src/trace/mem_start_addr.rs
+++ b/esp32c6/src/trace/mem_start_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_START_ADDR")
-            .field(
-                "mem_start_addr",
-                &format_args!("{}", self.mem_start_addr().bits()),
-            )
+            .field("mem_start_addr", &self.mem_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The start address of trace memory"]
     #[inline(always)]
diff --git a/esp32c6/src/trace/resync_prolonged.rs b/esp32c6/src/trace/resync_prolonged.rs
index 039a306aa7..dbe51e2e69 100644
--- a/esp32c6/src/trace/resync_prolonged.rs
+++ b/esp32c6/src/trace/resync_prolonged.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESYNC_PROLONGED")
-            .field(
-                "resync_prolonged",
-                &format_args!("{}", self.resync_prolonged().bits()),
-            )
-            .field("resync_mode", &format_args!("{}", self.resync_mode().bit()))
+            .field("resync_prolonged", &self.resync_prolonged())
+            .field("resync_mode", &self.resync_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESYNC_PROLONGED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - count number, when count to this value, send a sync package"]
     #[inline(always)]
diff --git a/esp32c6/src/trace/trigger.rs b/esp32c6/src/trace/trigger.rs
index cadb5527f4..9c724804b5 100644
--- a/esp32c6/src/trace/trigger.rs
+++ b/esp32c6/src/trace/trigger.rs
@@ -30,17 +30,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TRIGGER")
-            .field("mem_loop", &format_args!("{}", self.mem_loop().bit()))
-            .field("restart_ena", &format_args!("{}", self.restart_ena().bit()))
+            .field("mem_loop", &self.mem_loop())
+            .field("restart_ena", &self.restart_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TRIGGER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 0\\] set 1 start trace."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/arb_lost_cap.rs b/esp32c6/src/twai0/arb_lost_cap.rs
index 0e326e937c..edf5c834a7 100644
--- a/esp32c6/src/twai0/arb_lost_cap.rs
+++ b/esp32c6/src/twai0/arb_lost_cap.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_LOST_CAP")
-            .field(
-                "arbitration_lost_capture",
-                &format_args!("{}", self.arbitration_lost_capture().bits()),
-            )
+            .field("arbitration_lost_capture", &self.arbitration_lost_capture())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_LOST_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TWAI arbiter lost capture register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_lost_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ARB_LOST_CAP_SPEC;
 impl crate::RegisterSpec for ARB_LOST_CAP_SPEC {
diff --git a/esp32c6/src/twai0/bus_timing_0.rs b/esp32c6/src/twai0/bus_timing_0.rs
index 114b14ed9f..d416d38de6 100644
--- a/esp32c6/src/twai0/bus_timing_0.rs
+++ b/esp32c6/src/twai0/bus_timing_0.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMING_0")
-            .field("baud_presc", &format_args!("{}", self.baud_presc().bits()))
-            .field(
-                "sync_jump_width",
-                &format_args!("{}", self.sync_jump_width().bits()),
-            )
+            .field("baud_presc", &self.baud_presc())
+            .field("sync_jump_width", &self.sync_jump_width())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMING_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/bus_timing_1.rs b/esp32c6/src/twai0/bus_timing_1.rs
index 9ae19a0e35..caf2d91800 100644
--- a/esp32c6/src/twai0/bus_timing_1.rs
+++ b/esp32c6/src/twai0/bus_timing_1.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMING_1")
-            .field("time_seg1", &format_args!("{}", self.time_seg1().bits()))
-            .field("time_seg2", &format_args!("{}", self.time_seg2().bits()))
-            .field("time_samp", &format_args!("{}", self.time_samp().bit()))
+            .field("time_seg1", &self.time_seg1())
+            .field("time_seg2", &self.time_seg2())
+            .field("time_samp", &self.time_samp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMING_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/clock_divider.rs b/esp32c6/src/twai0/clock_divider.rs
index f5e7eb3181..e505a254ad 100644
--- a/esp32c6/src/twai0/clock_divider.rs
+++ b/esp32c6/src/twai0/clock_divider.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_DIVIDER")
-            .field("cd", &format_args!("{}", self.cd().bits()))
-            .field("clock_off", &format_args!("{}", self.clock_off().bit()))
+            .field("cd", &self.cd())
+            .field("clock_off", &self.clock_off())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_DIVIDER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - These bits are used to define the frequency at the external CLKOUT pin."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/data_0.rs b/esp32c6/src/twai0/data_0.rs
index e8196950d7..fa26d91abc 100644
--- a/esp32c6/src/twai0/data_0.rs
+++ b/esp32c6/src/twai0/data_0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_0")
-            .field("tx_byte_0", &format_args!("{}", self.tx_byte_0().bits()))
+            .field("tx_byte_0", &self.tx_byte_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/data_1.rs b/esp32c6/src/twai0/data_1.rs
index 923271d63e..2f62cfd10c 100644
--- a/esp32c6/src/twai0/data_1.rs
+++ b/esp32c6/src/twai0/data_1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_1")
-            .field("tx_byte_1", &format_args!("{}", self.tx_byte_1().bits()))
+            .field("tx_byte_1", &self.tx_byte_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/data_10.rs b/esp32c6/src/twai0/data_10.rs
index 940b00514c..a37b7fabbd 100644
--- a/esp32c6/src/twai0/data_10.rs
+++ b/esp32c6/src/twai0/data_10.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_10")
-            .field("tx_byte_10", &format_args!("{}", self.tx_byte_10().bits()))
+            .field("tx_byte_10", &self.tx_byte_10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/data_11.rs b/esp32c6/src/twai0/data_11.rs
index c862405bb0..d9b4bfe1b3 100644
--- a/esp32c6/src/twai0/data_11.rs
+++ b/esp32c6/src/twai0/data_11.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_11")
-            .field("tx_byte_11", &format_args!("{}", self.tx_byte_11().bits()))
+            .field("tx_byte_11", &self.tx_byte_11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/data_12.rs b/esp32c6/src/twai0/data_12.rs
index 9a4ad84336..3db488d13f 100644
--- a/esp32c6/src/twai0/data_12.rs
+++ b/esp32c6/src/twai0/data_12.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_12")
-            .field("tx_byte_12", &format_args!("{}", self.tx_byte_12().bits()))
+            .field("tx_byte_12", &self.tx_byte_12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/data_2.rs b/esp32c6/src/twai0/data_2.rs
index 6b6513eb15..1da66f7dfd 100644
--- a/esp32c6/src/twai0/data_2.rs
+++ b/esp32c6/src/twai0/data_2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_2")
-            .field("tx_byte_2", &format_args!("{}", self.tx_byte_2().bits()))
+            .field("tx_byte_2", &self.tx_byte_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/data_3.rs b/esp32c6/src/twai0/data_3.rs
index a859f35788..1afe43898b 100644
--- a/esp32c6/src/twai0/data_3.rs
+++ b/esp32c6/src/twai0/data_3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_3")
-            .field("tx_byte_3", &format_args!("{}", self.tx_byte_3().bits()))
+            .field("tx_byte_3", &self.tx_byte_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/data_4.rs b/esp32c6/src/twai0/data_4.rs
index 0ca09120f6..b4ecde3be3 100644
--- a/esp32c6/src/twai0/data_4.rs
+++ b/esp32c6/src/twai0/data_4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_4")
-            .field("tx_byte_4", &format_args!("{}", self.tx_byte_4().bits()))
+            .field("tx_byte_4", &self.tx_byte_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/data_5.rs b/esp32c6/src/twai0/data_5.rs
index 92d292f07c..eeb176fc6e 100644
--- a/esp32c6/src/twai0/data_5.rs
+++ b/esp32c6/src/twai0/data_5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_5")
-            .field("tx_byte_5", &format_args!("{}", self.tx_byte_5().bits()))
+            .field("tx_byte_5", &self.tx_byte_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/data_6.rs b/esp32c6/src/twai0/data_6.rs
index 76ce4f79b4..d698884c88 100644
--- a/esp32c6/src/twai0/data_6.rs
+++ b/esp32c6/src/twai0/data_6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_6")
-            .field("tx_byte_6", &format_args!("{}", self.tx_byte_6().bits()))
+            .field("tx_byte_6", &self.tx_byte_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/data_7.rs b/esp32c6/src/twai0/data_7.rs
index ce96ddfd73..9fa633d1b7 100644
--- a/esp32c6/src/twai0/data_7.rs
+++ b/esp32c6/src/twai0/data_7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_7")
-            .field("tx_byte_7", &format_args!("{}", self.tx_byte_7().bits()))
+            .field("tx_byte_7", &self.tx_byte_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/data_8.rs b/esp32c6/src/twai0/data_8.rs
index b419274e19..e2108471cc 100644
--- a/esp32c6/src/twai0/data_8.rs
+++ b/esp32c6/src/twai0/data_8.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_8")
-            .field("tx_byte_8", &format_args!("{}", self.tx_byte_8().bits()))
+            .field("tx_byte_8", &self.tx_byte_8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/data_9.rs b/esp32c6/src/twai0/data_9.rs
index 0f633f55b7..419137bd6f 100644
--- a/esp32c6/src/twai0/data_9.rs
+++ b/esp32c6/src/twai0/data_9.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_9")
-            .field("data_9", &format_args!("{}", self.data_9().bits()))
+            .field("data_9", &self.data_9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/eco_cfg.rs b/esp32c6/src/twai0/eco_cfg.rs
index 7928138cdb..2174ebda7d 100644
--- a/esp32c6/src/twai0/eco_cfg.rs
+++ b/esp32c6/src/twai0/eco_cfg.rs
@@ -24,17 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_CFG")
-            .field("rdn_ena", &format_args!("{}", self.rdn_ena().bit()))
-            .field("rdn_result", &format_args!("{}", self.rdn_result().bit()))
+            .field("rdn_ena", &self.rdn_ena())
+            .field("rdn_result", &self.rdn_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable eco module."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/err_code_cap.rs b/esp32c6/src/twai0/err_code_cap.rs
index b32b4db0e1..189911898e 100644
--- a/esp32c6/src/twai0/err_code_cap.rs
+++ b/esp32c6/src/twai0/err_code_cap.rs
@@ -27,27 +27,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERR_CODE_CAP")
-            .field(
-                "err_capture_code_segment",
-                &format_args!("{}", self.err_capture_code_segment().bits()),
-            )
+            .field("err_capture_code_segment", &self.err_capture_code_segment())
             .field(
                 "err_capture_code_direction",
-                &format_args!("{}", self.err_capture_code_direction().bit()),
-            )
-            .field(
-                "err_capture_code_type",
-                &format_args!("{}", self.err_capture_code_type().bits()),
+                &self.err_capture_code_direction(),
             )
+            .field("err_capture_code_type", &self.err_capture_code_type())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERR_CODE_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TWAI error info capture register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_code_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ERR_CODE_CAP_SPEC;
 impl crate::RegisterSpec for ERR_CODE_CAP_SPEC {
diff --git a/esp32c6/src/twai0/err_warning_limit.rs b/esp32c6/src/twai0/err_warning_limit.rs
index c3d6ab8f2f..9c78f60158 100644
--- a/esp32c6/src/twai0/err_warning_limit.rs
+++ b/esp32c6/src/twai0/err_warning_limit.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERR_WARNING_LIMIT")
-            .field(
-                "err_warning_limit",
-                &format_args!("{}", self.err_warning_limit().bits()),
-            )
+            .field("err_warning_limit", &self.err_warning_limit())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERR_WARNING_LIMIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/hw_cfg.rs b/esp32c6/src/twai0/hw_cfg.rs
index d4b499209c..4f7c21ba6b 100644
--- a/esp32c6/src/twai0/hw_cfg.rs
+++ b/esp32c6/src/twai0/hw_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HW_CFG")
-            .field(
-                "hw_standby_en",
-                &format_args!("{}", self.hw_standby_en().bit()),
-            )
+            .field("hw_standby_en", &self.hw_standby_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HW_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable function that hardware control standby pin."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/hw_standby_cnt.rs b/esp32c6/src/twai0/hw_standby_cnt.rs
index 1aabc9964c..a41e6ee631 100644
--- a/esp32c6/src/twai0/hw_standby_cnt.rs
+++ b/esp32c6/src/twai0/hw_standby_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HW_STANDBY_CNT")
-            .field(
-                "standby_wait_cnt",
-                &format_args!("{}", self.standby_wait_cnt().bits()),
-            )
+            .field("standby_wait_cnt", &self.standby_wait_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HW_STANDBY_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/idle_intr_cnt.rs b/esp32c6/src/twai0/idle_intr_cnt.rs
index 9a4baf45b7..444052985e 100644
--- a/esp32c6/src/twai0/idle_intr_cnt.rs
+++ b/esp32c6/src/twai0/idle_intr_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDLE_INTR_CNT")
-            .field(
-                "idle_intr_cnt",
-                &format_args!("{}", self.idle_intr_cnt().bits()),
-            )
+            .field("idle_intr_cnt", &self.idle_intr_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_INTR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configure the number of cycles before triggering idle interrupt."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/interrupt.rs b/esp32c6/src/twai0/interrupt.rs
index 66fce19eca..77a31f9184 100644
--- a/esp32c6/src/twai0/interrupt.rs
+++ b/esp32c6/src/twai0/interrupt.rs
@@ -62,44 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT")
-            .field(
-                "receive_int_st",
-                &format_args!("{}", self.receive_int_st().bit()),
-            )
-            .field(
-                "transmit_int_st",
-                &format_args!("{}", self.transmit_int_st().bit()),
-            )
-            .field(
-                "err_warning_int_st",
-                &format_args!("{}", self.err_warning_int_st().bit()),
-            )
-            .field(
-                "data_overrun_int_st",
-                &format_args!("{}", self.data_overrun_int_st().bit()),
-            )
-            .field(
-                "err_passive_int_st",
-                &format_args!("{}", self.err_passive_int_st().bit()),
-            )
-            .field(
-                "arbitration_lost_int_st",
-                &format_args!("{}", self.arbitration_lost_int_st().bit()),
-            )
-            .field(
-                "bus_err_int_st",
-                &format_args!("{}", self.bus_err_int_st().bit()),
-            )
-            .field("idle_int_st", &format_args!("{}", self.idle_int_st().bit()))
+            .field("receive_int_st", &self.receive_int_st())
+            .field("transmit_int_st", &self.transmit_int_st())
+            .field("err_warning_int_st", &self.err_warning_int_st())
+            .field("data_overrun_int_st", &self.data_overrun_int_st())
+            .field("err_passive_int_st", &self.err_passive_int_st())
+            .field("arbitration_lost_int_st", &self.arbitration_lost_int_st())
+            .field("bus_err_int_st", &self.bus_err_int_st())
+            .field("idle_int_st", &self.idle_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt signals' register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERRUPT_SPEC;
 impl crate::RegisterSpec for INTERRUPT_SPEC {
diff --git a/esp32c6/src/twai0/interrupt_enable.rs b/esp32c6/src/twai0/interrupt_enable.rs
index 0d6f6fe8aa..e3554e69eb 100644
--- a/esp32c6/src/twai0/interrupt_enable.rs
+++ b/esp32c6/src/twai0/interrupt_enable.rs
@@ -78,47 +78,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT_ENABLE")
-            .field(
-                "ext_receive_int_ena",
-                &format_args!("{}", self.ext_receive_int_ena().bit()),
-            )
-            .field(
-                "ext_transmit_int_ena",
-                &format_args!("{}", self.ext_transmit_int_ena().bit()),
-            )
-            .field(
-                "ext_err_warning_int_ena",
-                &format_args!("{}", self.ext_err_warning_int_ena().bit()),
-            )
-            .field(
-                "ext_data_overrun_int_ena",
-                &format_args!("{}", self.ext_data_overrun_int_ena().bit()),
-            )
-            .field(
-                "err_passive_int_ena",
-                &format_args!("{}", self.err_passive_int_ena().bit()),
-            )
-            .field(
-                "arbitration_lost_int_ena",
-                &format_args!("{}", self.arbitration_lost_int_ena().bit()),
-            )
-            .field(
-                "bus_err_int_ena",
-                &format_args!("{}", self.bus_err_int_ena().bit()),
-            )
-            .field(
-                "idle_int_ena",
-                &format_args!("{}", self.idle_int_ena().bit()),
-            )
+            .field("ext_receive_int_ena", &self.ext_receive_int_ena())
+            .field("ext_transmit_int_ena", &self.ext_transmit_int_ena())
+            .field("ext_err_warning_int_ena", &self.ext_err_warning_int_ena())
+            .field("ext_data_overrun_int_ena", &self.ext_data_overrun_int_ena())
+            .field("err_passive_int_ena", &self.err_passive_int_ena())
+            .field("arbitration_lost_int_ena", &self.arbitration_lost_int_ena())
+            .field("bus_err_int_ena", &self.bus_err_int_ena())
+            .field("idle_int_ena", &self.idle_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable"]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/mode.rs b/esp32c6/src/twai0/mode.rs
index 2619ae327d..6ca205ae27 100644
--- a/esp32c6/src/twai0/mode.rs
+++ b/esp32c6/src/twai0/mode.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODE")
-            .field("reset_mode", &format_args!("{}", self.reset_mode().bit()))
-            .field(
-                "listen_only_mode",
-                &format_args!("{}", self.listen_only_mode().bit()),
-            )
-            .field(
-                "self_test_mode",
-                &format_args!("{}", self.self_test_mode().bit()),
-            )
-            .field(
-                "rx_filter_mode",
-                &format_args!("{}", self.rx_filter_mode().bit()),
-            )
+            .field("reset_mode", &self.reset_mode())
+            .field("listen_only_mode", &self.listen_only_mode())
+            .field("self_test_mode", &self.self_test_mode())
+            .field("rx_filter_mode", &self.rx_filter_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/rx_err_cnt.rs b/esp32c6/src/twai0/rx_err_cnt.rs
index 6c17a3b1b8..8919de4888 100644
--- a/esp32c6/src/twai0/rx_err_cnt.rs
+++ b/esp32c6/src/twai0/rx_err_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ERR_CNT")
-            .field("rx_err_cnt", &format_args!("{}", self.rx_err_cnt().bits()))
+            .field("rx_err_cnt", &self.rx_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ERR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/rx_message_cnt.rs b/esp32c6/src/twai0/rx_message_cnt.rs
index 7d99338e06..c5339669bd 100644
--- a/esp32c6/src/twai0/rx_message_cnt.rs
+++ b/esp32c6/src/twai0/rx_message_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_MESSAGE_CNT")
-            .field(
-                "rx_message_counter",
-                &format_args!("{}", self.rx_message_counter().bits()),
-            )
+            .field("rx_message_counter", &self.rx_message_counter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_MESSAGE_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Received message counter register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_message_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_MESSAGE_CNT_SPEC;
 impl crate::RegisterSpec for RX_MESSAGE_CNT_SPEC {
diff --git a/esp32c6/src/twai0/status.rs b/esp32c6/src/twai0/status.rs
index 530b818372..bff646e955 100644
--- a/esp32c6/src/twai0/status.rs
+++ b/esp32c6/src/twai0/status.rs
@@ -69,27 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rx_buf_st", &format_args!("{}", self.rx_buf_st().bit()))
-            .field("overrun", &format_args!("{}", self.overrun().bit()))
-            .field("tx_buf_st", &format_args!("{}", self.tx_buf_st().bit()))
-            .field(
-                "transmission_complete",
-                &format_args!("{}", self.transmission_complete().bit()),
-            )
-            .field("receive", &format_args!("{}", self.receive().bit()))
-            .field("transmit", &format_args!("{}", self.transmit().bit()))
-            .field("err", &format_args!("{}", self.err().bit()))
-            .field("bus_off_st", &format_args!("{}", self.bus_off_st().bit()))
-            .field("miss_st", &format_args!("{}", self.miss_st().bit()))
+            .field("rx_buf_st", &self.rx_buf_st())
+            .field("overrun", &self.overrun())
+            .field("tx_buf_st", &self.tx_buf_st())
+            .field("transmission_complete", &self.transmission_complete())
+            .field("receive", &self.receive())
+            .field("transmit", &self.transmit())
+            .field("err", &self.err())
+            .field("bus_off_st", &self.bus_off_st())
+            .field("miss_st", &self.miss_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TWAI status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32c6/src/twai0/sw_standby_cfg.rs b/esp32c6/src/twai0/sw_standby_cfg.rs
index 77eacb6cc3..7842ae7587 100644
--- a/esp32c6/src/twai0/sw_standby_cfg.rs
+++ b/esp32c6/src/twai0/sw_standby_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SW_STANDBY_CFG")
-            .field(
-                "sw_standby_en",
-                &format_args!("{}", self.sw_standby_en().bit()),
-            )
-            .field(
-                "sw_standby_clr",
-                &format_args!("{}", self.sw_standby_clr().bit()),
-            )
+            .field("sw_standby_en", &self.sw_standby_en())
+            .field("sw_standby_clr", &self.sw_standby_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SW_STANDBY_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable standby pin."]
     #[inline(always)]
diff --git a/esp32c6/src/twai0/tx_err_cnt.rs b/esp32c6/src/twai0/tx_err_cnt.rs
index 465da715b0..077faba61d 100644
--- a/esp32c6/src/twai0/tx_err_cnt.rs
+++ b/esp32c6/src/twai0/tx_err_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_ERR_CNT")
-            .field("tx_err_cnt", &format_args!("{}", self.tx_err_cnt().bits()))
+            .field("tx_err_cnt", &self.tx_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_ERR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/afifo_status.rs b/esp32c6/src/uart0/afifo_status.rs
index 32a27a7eed..22f55103b7 100644
--- a/esp32c6/src/uart0/afifo_status.rs
+++ b/esp32c6/src/uart0/afifo_status.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AFIFO_STATUS")
-            .field(
-                "tx_afifo_full",
-                &format_args!("{}", self.tx_afifo_full().bit()),
-            )
-            .field(
-                "tx_afifo_empty",
-                &format_args!("{}", self.tx_afifo_empty().bit()),
-            )
-            .field(
-                "rx_afifo_full",
-                &format_args!("{}", self.rx_afifo_full().bit()),
-            )
-            .field(
-                "rx_afifo_empty",
-                &format_args!("{}", self.rx_afifo_empty().bit()),
-            )
+            .field("tx_afifo_full", &self.tx_afifo_full())
+            .field("tx_afifo_empty", &self.tx_afifo_empty())
+            .field("rx_afifo_full", &self.rx_afifo_full())
+            .field("rx_afifo_empty", &self.rx_afifo_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART AFIFO Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`afifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for AFIFO_STATUS_SPEC {
diff --git a/esp32c6/src/uart0/at_cmd_char.rs b/esp32c6/src/uart0/at_cmd_char.rs
index 17e9222fe8..e75e1409cd 100644
--- a/esp32c6/src/uart0/at_cmd_char.rs
+++ b/esp32c6/src/uart0/at_cmd_char.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_CHAR")
-            .field(
-                "at_cmd_char",
-                &format_args!("{}", self.at_cmd_char().bits()),
-            )
-            .field("char_num", &format_args!("{}", self.char_num().bits()))
+            .field("at_cmd_char", &self.at_cmd_char())
+            .field("char_num", &self.char_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_CHAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/at_cmd_gaptout.rs b/esp32c6/src/uart0/at_cmd_gaptout.rs
index c7373436b0..7091ac8125 100644
--- a/esp32c6/src/uart0/at_cmd_gaptout.rs
+++ b/esp32c6/src/uart0/at_cmd_gaptout.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_GAPTOUT")
-            .field(
-                "rx_gap_tout",
-                &format_args!("{}", self.rx_gap_tout().bits()),
-            )
+            .field("rx_gap_tout", &self.rx_gap_tout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_GAPTOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the at_cmd chars."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/at_cmd_postcnt.rs b/esp32c6/src/uart0/at_cmd_postcnt.rs
index 078c4bb6a1..5db8445554 100644
--- a/esp32c6/src/uart0/at_cmd_postcnt.rs
+++ b/esp32c6/src/uart0/at_cmd_postcnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_POSTCNT")
-            .field(
-                "post_idle_num",
-                &format_args!("{}", self.post_idle_num().bits()),
-            )
+            .field("post_idle_num", &self.post_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_POSTCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the last at_cmd and the next data."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/at_cmd_precnt.rs b/esp32c6/src/uart0/at_cmd_precnt.rs
index 9e4a1cc58c..41790b5e67 100644
--- a/esp32c6/src/uart0/at_cmd_precnt.rs
+++ b/esp32c6/src/uart0/at_cmd_precnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_PRECNT")
-            .field(
-                "pre_idle_num",
-                &format_args!("{}", self.pre_idle_num().bits()),
-            )
+            .field("pre_idle_num", &self.pre_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_PRECNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first at_cmd is received by receiver."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/clk_conf.rs b/esp32c6/src/uart0/clk_conf.rs
index f4d58f12dc..15db8ddbda 100644
--- a/esp32c6/src/uart0/clk_conf.rs
+++ b/esp32c6/src/uart0/clk_conf.rs
@@ -98,28 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bits()))
-            .field("sclk_en", &format_args!("{}", self.sclk_en().bit()))
-            .field("rst_core", &format_args!("{}", self.rst_core().bit()))
-            .field("tx_sclk_en", &format_args!("{}", self.tx_sclk_en().bit()))
-            .field("rx_sclk_en", &format_args!("{}", self.rx_sclk_en().bit()))
-            .field("tx_rst_core", &format_args!("{}", self.tx_rst_core().bit()))
-            .field("rx_rst_core", &format_args!("{}", self.rx_rst_core().bit()))
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_en", &self.sclk_en())
+            .field("rst_core", &self.rst_core())
+            .field("tx_sclk_en", &self.tx_sclk_en())
+            .field("rx_sclk_en", &self.rx_sclk_en())
+            .field("tx_rst_core", &self.tx_rst_core())
+            .field("rx_rst_core", &self.rx_rst_core())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/clkdiv.rs b/esp32c6/src/uart0/clkdiv.rs
index c020543f66..0c1138e013 100644
--- a/esp32c6/src/uart0/clkdiv.rs
+++ b/esp32c6/src/uart0/clkdiv.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKDIV")
-            .field("clkdiv", &format_args!("{}", self.clkdiv().bits()))
-            .field("frag", &format_args!("{}", self.frag().bits()))
+            .field("clkdiv", &self.clkdiv())
+            .field("frag", &self.frag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKDIV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/conf0.rs b/esp32c6/src/uart0/conf0.rs
index 65ff6a9991..46ada52338 100644
--- a/esp32c6/src/uart0/conf0.rs
+++ b/esp32c6/src/uart0/conf0.rs
@@ -206,43 +206,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("parity", &format_args!("{}", self.parity().bit()))
-            .field("parity_en", &format_args!("{}", self.parity_en().bit()))
-            .field("bit_num", &format_args!("{}", self.bit_num().bits()))
-            .field(
-                "stop_bit_num",
-                &format_args!("{}", self.stop_bit_num().bits()),
-            )
-            .field("txd_brk", &format_args!("{}", self.txd_brk().bit()))
-            .field("irda_dplx", &format_args!("{}", self.irda_dplx().bit()))
-            .field("irda_tx_en", &format_args!("{}", self.irda_tx_en().bit()))
-            .field("irda_wctl", &format_args!("{}", self.irda_wctl().bit()))
-            .field("irda_tx_inv", &format_args!("{}", self.irda_tx_inv().bit()))
-            .field("irda_rx_inv", &format_args!("{}", self.irda_rx_inv().bit()))
-            .field("loopback", &format_args!("{}", self.loopback().bit()))
-            .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit()))
-            .field("irda_en", &format_args!("{}", self.irda_en().bit()))
-            .field("rxd_inv", &format_args!("{}", self.rxd_inv().bit()))
-            .field("txd_inv", &format_args!("{}", self.txd_inv().bit()))
-            .field(
-                "dis_rx_dat_ovf",
-                &format_args!("{}", self.dis_rx_dat_ovf().bit()),
-            )
-            .field("err_wr_mask", &format_args!("{}", self.err_wr_mask().bit()))
-            .field("autobaud_en", &format_args!("{}", self.autobaud_en().bit()))
-            .field("mem_clk_en", &format_args!("{}", self.mem_clk_en().bit()))
-            .field("sw_rts", &format_args!("{}", self.sw_rts().bit()))
-            .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit()))
-            .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit()))
+            .field("parity", &self.parity())
+            .field("parity_en", &self.parity_en())
+            .field("bit_num", &self.bit_num())
+            .field("stop_bit_num", &self.stop_bit_num())
+            .field("txd_brk", &self.txd_brk())
+            .field("irda_dplx", &self.irda_dplx())
+            .field("irda_tx_en", &self.irda_tx_en())
+            .field("irda_wctl", &self.irda_wctl())
+            .field("irda_tx_inv", &self.irda_tx_inv())
+            .field("irda_rx_inv", &self.irda_rx_inv())
+            .field("loopback", &self.loopback())
+            .field("tx_flow_en", &self.tx_flow_en())
+            .field("irda_en", &self.irda_en())
+            .field("rxd_inv", &self.rxd_inv())
+            .field("txd_inv", &self.txd_inv())
+            .field("dis_rx_dat_ovf", &self.dis_rx_dat_ovf())
+            .field("err_wr_mask", &self.err_wr_mask())
+            .field("autobaud_en", &self.autobaud_en())
+            .field("mem_clk_en", &self.mem_clk_en())
+            .field("sw_rts", &self.sw_rts())
+            .field("rxfifo_rst", &self.rxfifo_rst())
+            .field("txfifo_rst", &self.txfifo_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to configure the parity check mode."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/conf1.rs b/esp32c6/src/uart0/conf1.rs
index 9b3521035b..88d452abe5 100644
--- a/esp32c6/src/uart0/conf1.rs
+++ b/esp32c6/src/uart0/conf1.rs
@@ -80,29 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "rxfifo_full_thrhd",
-                &format_args!("{}", self.rxfifo_full_thrhd().bits()),
-            )
-            .field(
-                "txfifo_empty_thrhd",
-                &format_args!("{}", self.txfifo_empty_thrhd().bits()),
-            )
-            .field("cts_inv", &format_args!("{}", self.cts_inv().bit()))
-            .field("dsr_inv", &format_args!("{}", self.dsr_inv().bit()))
-            .field("rts_inv", &format_args!("{}", self.rts_inv().bit()))
-            .field("dtr_inv", &format_args!("{}", self.dtr_inv().bit()))
-            .field("sw_dtr", &format_args!("{}", self.sw_dtr().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("rxfifo_full_thrhd", &self.rxfifo_full_thrhd())
+            .field("txfifo_empty_thrhd", &self.txfifo_empty_thrhd())
+            .field("cts_inv", &self.cts_inv())
+            .field("dsr_inv", &self.dsr_inv())
+            .field("rts_inv", &self.rts_inv())
+            .field("dtr_inv", &self.dtr_inv())
+            .field("sw_dtr", &self.sw_dtr())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/date.rs b/esp32c6/src/uart0/date.rs
index a81320d26c..6112a0fc83 100644
--- a/esp32c6/src/uart0/date.rs
+++ b/esp32c6/src/uart0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/uart0/fifo.rs b/esp32c6/src/uart0/fifo.rs
index 3ea719e7ab..fdc9ee6700 100644
--- a/esp32c6/src/uart0/fifo.rs
+++ b/esp32c6/src/uart0/fifo.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO")
-            .field(
-                "rxfifo_rd_byte",
-                &format_args!("{}", self.rxfifo_rd_byte().bits()),
-            )
+            .field("rxfifo_rd_byte", &self.rxfifo_rd_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - UART 0 accesses FIFO via this register."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/fsm_status.rs b/esp32c6/src/uart0/fsm_status.rs
index 7e47b06bf6..4088ac153f 100644
--- a/esp32c6/src/uart0/fsm_status.rs
+++ b/esp32c6/src/uart0/fsm_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_STATUS")
-            .field("st_urx_out", &format_args!("{}", self.st_urx_out().bits()))
-            .field("st_utx_out", &format_args!("{}", self.st_utx_out().bits()))
+            .field("st_urx_out", &self.st_urx_out())
+            .field("st_utx_out", &self.st_utx_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART transmit and receive status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FSM_STATUS_SPEC;
 impl crate::RegisterSpec for FSM_STATUS_SPEC {
diff --git a/esp32c6/src/uart0/highpulse.rs b/esp32c6/src/uart0/highpulse.rs
index 2a100f783a..8445906dbf 100644
--- a/esp32c6/src/uart0/highpulse.rs
+++ b/esp32c6/src/uart0/highpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIGHPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIGHPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud minimum high pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`highpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIGHPULSE_SPEC;
 impl crate::RegisterSpec for HIGHPULSE_SPEC {
diff --git a/esp32c6/src/uart0/hwfc_conf.rs b/esp32c6/src/uart0/hwfc_conf.rs
index c5bcb05208..f9a6aadfb8 100644
--- a/esp32c6/src/uart0/hwfc_conf.rs
+++ b/esp32c6/src/uart0/hwfc_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HWFC_CONF")
-            .field(
-                "rx_flow_thrhd",
-                &format_args!("{}", self.rx_flow_thrhd().bits()),
-            )
-            .field("rx_flow_en", &format_args!("{}", self.rx_flow_en().bit()))
+            .field("rx_flow_thrhd", &self.rx_flow_thrhd())
+            .field("rx_flow_en", &self.rx_flow_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HWFC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the maximum amount of data that can be received when hardware flow control works."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/id.rs b/esp32c6/src/uart0/id.rs
index 9c8cfa3a6b..670842afd9 100644
--- a/esp32c6/src/uart0/id.rs
+++ b/esp32c6/src/uart0/id.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("ID")
-            .field("id", &format_args!("{}", self.id().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("ID").field("id", &self.id()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/uart0/idle_conf.rs b/esp32c6/src/uart0/idle_conf.rs
index bc986732bf..a2f200e19e 100644
--- a/esp32c6/src/uart0/idle_conf.rs
+++ b/esp32c6/src/uart0/idle_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDLE_CONF")
-            .field(
-                "rx_idle_thrhd",
-                &format_args!("{}", self.rx_idle_thrhd().bits()),
-            )
-            .field(
-                "tx_idle_num",
-                &format_args!("{}", self.tx_idle_num().bits()),
-            )
+            .field("rx_idle_thrhd", &self.rx_idle_thrhd())
+            .field("tx_idle_num", &self.tx_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/int_ena.rs b/esp32c6/src/uart0/int_ena.rs
index fea57f25bd..3a8a9f2f95 100644
--- a/esp32c6/src/uart0/int_ena.rs
+++ b/esp32c6/src/uart0/int_ena.rs
@@ -188,50 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/int_raw.rs b/esp32c6/src/uart0/int_raw.rs
index 7c0c628adc..d47f4c54f2 100644
--- a/esp32c6/src/uart0/int_raw.rs
+++ b/esp32c6/src/uart0/int_raw.rs
@@ -188,50 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/int_st.rs b/esp32c6/src/uart0/int_st.rs
index 417bc433a0..c67c7f4b75 100644
--- a/esp32c6/src/uart0/int_st.rs
+++ b/esp32c6/src/uart0/int_st.rs
@@ -146,50 +146,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/uart0/lowpulse.rs b/esp32c6/src/uart0/lowpulse.rs
index 6736272863..03a2b35c08 100644
--- a/esp32c6/src/uart0/lowpulse.rs
+++ b/esp32c6/src/uart0/lowpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOWPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOWPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud minimum low pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lowpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOWPULSE_SPEC;
 impl crate::RegisterSpec for LOWPULSE_SPEC {
diff --git a/esp32c6/src/uart0/mem_conf.rs b/esp32c6/src/uart0/mem_conf.rs
index 8c55da8b47..e930d52fc0 100644
--- a/esp32c6/src/uart0/mem_conf.rs
+++ b/esp32c6/src/uart0/mem_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - Set this bit to force power down UART memory."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/mem_rx_status.rs b/esp32c6/src/uart0/mem_rx_status.rs
index 0a126a60b0..99d13455c6 100644
--- a/esp32c6/src/uart0/mem_rx_status.rs
+++ b/esp32c6/src/uart0/mem_rx_status.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_RX_STATUS")
-            .field(
-                "rx_sram_raddr",
-                &format_args!("{}", self.rx_sram_raddr().bits()),
-            )
-            .field(
-                "rx_sram_waddr",
-                &format_args!("{}", self.rx_sram_waddr().bits()),
-            )
+            .field("rx_sram_raddr", &self.rx_sram_raddr())
+            .field("rx_sram_waddr", &self.rx_sram_waddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Rx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_RX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_RX_STATUS_SPEC {
diff --git a/esp32c6/src/uart0/mem_tx_status.rs b/esp32c6/src/uart0/mem_tx_status.rs
index 8b947846b3..328cfcccd6 100644
--- a/esp32c6/src/uart0/mem_tx_status.rs
+++ b/esp32c6/src/uart0/mem_tx_status.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_TX_STATUS")
-            .field(
-                "tx_sram_waddr",
-                &format_args!("{}", self.tx_sram_waddr().bits()),
-            )
-            .field(
-                "tx_sram_raddr",
-                &format_args!("{}", self.tx_sram_raddr().bits()),
-            )
+            .field("tx_sram_waddr", &self.tx_sram_waddr())
+            .field("tx_sram_raddr", &self.tx_sram_raddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Tx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_TX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_TX_STATUS_SPEC {
diff --git a/esp32c6/src/uart0/negpulse.rs b/esp32c6/src/uart0/negpulse.rs
index 0daf3b983f..d033b00895 100644
--- a/esp32c6/src/uart0/negpulse.rs
+++ b/esp32c6/src/uart0/negpulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NEGPULSE")
-            .field(
-                "negedge_min_cnt",
-                &format_args!("{}", self.negedge_min_cnt().bits()),
-            )
+            .field("negedge_min_cnt", &self.negedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NEGPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud low pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`negpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NEGPULSE_SPEC;
 impl crate::RegisterSpec for NEGPULSE_SPEC {
diff --git a/esp32c6/src/uart0/pospulse.rs b/esp32c6/src/uart0/pospulse.rs
index 67a98ae05f..acf540a226 100644
--- a/esp32c6/src/uart0/pospulse.rs
+++ b/esp32c6/src/uart0/pospulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POSPULSE")
-            .field(
-                "posedge_min_cnt",
-                &format_args!("{}", self.posedge_min_cnt().bits()),
-            )
+            .field("posedge_min_cnt", &self.posedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POSPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud high pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pospulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct POSPULSE_SPEC;
 impl crate::RegisterSpec for POSPULSE_SPEC {
diff --git a/esp32c6/src/uart0/reg_update.rs b/esp32c6/src/uart0/reg_update.rs
index b2e4551f76..441e05815f 100644
--- a/esp32c6/src/uart0/reg_update.rs
+++ b/esp32c6/src/uart0/reg_update.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_UPDATE")
-            .field("reg_update", &format_args!("{}", self.reg_update().bit()))
+            .field("reg_update", &self.reg_update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/rs485_conf.rs b/esp32c6/src/uart0/rs485_conf.rs
index 5480b03198..dbf27d91ba 100644
--- a/esp32c6/src/uart0/rs485_conf.rs
+++ b/esp32c6/src/uart0/rs485_conf.rs
@@ -71,34 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RS485_CONF")
-            .field("rs485_en", &format_args!("{}", self.rs485_en().bit()))
-            .field("dl0_en", &format_args!("{}", self.dl0_en().bit()))
-            .field("dl1_en", &format_args!("{}", self.dl1_en().bit()))
-            .field(
-                "rs485tx_rx_en",
-                &format_args!("{}", self.rs485tx_rx_en().bit()),
-            )
-            .field(
-                "rs485rxby_tx_en",
-                &format_args!("{}", self.rs485rxby_tx_en().bit()),
-            )
-            .field(
-                "rs485_rx_dly_num",
-                &format_args!("{}", self.rs485_rx_dly_num().bit()),
-            )
-            .field(
-                "rs485_tx_dly_num",
-                &format_args!("{}", self.rs485_tx_dly_num().bits()),
-            )
+            .field("rs485_en", &self.rs485_en())
+            .field("dl0_en", &self.dl0_en())
+            .field("dl1_en", &self.dl1_en())
+            .field("rs485tx_rx_en", &self.rs485tx_rx_en())
+            .field("rs485rxby_tx_en", &self.rs485rxby_tx_en())
+            .field("rs485_rx_dly_num", &self.rs485_rx_dly_num())
+            .field("rs485_tx_dly_num", &self.rs485_tx_dly_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RS485_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to choose the rs485 mode."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/rx_filt.rs b/esp32c6/src/uart0/rx_filt.rs
index c24c62977e..21576af0e9 100644
--- a/esp32c6/src/uart0/rx_filt.rs
+++ b/esp32c6/src/uart0/rx_filt.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_FILT")
-            .field(
-                "glitch_filt",
-                &format_args!("{}", self.glitch_filt().bits()),
-            )
-            .field(
-                "glitch_filt_en",
-                &format_args!("{}", self.glitch_filt_en().bit()),
-            )
+            .field("glitch_filt", &self.glitch_filt())
+            .field("glitch_filt_en", &self.glitch_filt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_FILT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - when input pulse width is lower than this value the pulse is ignored."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/rxd_cnt.rs b/esp32c6/src/uart0/rxd_cnt.rs
index f08d5e0323..c3c3052a66 100644
--- a/esp32c6/src/uart0/rxd_cnt.rs
+++ b/esp32c6/src/uart0/rxd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXD_CNT")
-            .field(
-                "rxd_edge_cnt",
-                &format_args!("{}", self.rxd_edge_cnt().bits()),
-            )
+            .field("rxd_edge_cnt", &self.rxd_edge_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud edge change count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXD_CNT_SPEC;
 impl crate::RegisterSpec for RXD_CNT_SPEC {
diff --git a/esp32c6/src/uart0/sleep_conf0.rs b/esp32c6/src/uart0/sleep_conf0.rs
index 1c5c7f7eed..a8481a8783 100644
--- a/esp32c6/src/uart0/sleep_conf0.rs
+++ b/esp32c6/src/uart0/sleep_conf0.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF0")
-            .field("wk_char1", &format_args!("{}", self.wk_char1().bits()))
-            .field("wk_char2", &format_args!("{}", self.wk_char2().bits()))
-            .field("wk_char3", &format_args!("{}", self.wk_char3().bits()))
-            .field("wk_char4", &format_args!("{}", self.wk_char4().bits()))
+            .field("wk_char1", &self.wk_char1())
+            .field("wk_char2", &self.wk_char2())
+            .field("wk_char3", &self.wk_char3())
+            .field("wk_char4", &self.wk_char4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register restores the specified wake up char1 to wake up"]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/sleep_conf1.rs b/esp32c6/src/uart0/sleep_conf1.rs
index f9f665a833..bf71699cf5 100644
--- a/esp32c6/src/uart0/sleep_conf1.rs
+++ b/esp32c6/src/uart0/sleep_conf1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF1")
-            .field("wk_char0", &format_args!("{}", self.wk_char0().bits()))
+            .field("wk_char0", &self.wk_char0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register restores the specified char0 to wake up"]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/sleep_conf2.rs b/esp32c6/src/uart0/sleep_conf2.rs
index 4ba2a7a251..06e8c23f14 100644
--- a/esp32c6/src/uart0/sleep_conf2.rs
+++ b/esp32c6/src/uart0/sleep_conf2.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF2")
-            .field(
-                "active_threshold",
-                &format_args!("{}", self.active_threshold().bits()),
-            )
-            .field(
-                "rx_wake_up_thrhd",
-                &format_args!("{}", self.rx_wake_up_thrhd().bits()),
-            )
-            .field(
-                "wk_char_num",
-                &format_args!("{}", self.wk_char_num().bits()),
-            )
-            .field(
-                "wk_char_mask",
-                &format_args!("{}", self.wk_char_mask().bits()),
-            )
-            .field(
-                "wk_mode_sel",
-                &format_args!("{}", self.wk_mode_sel().bits()),
-            )
+            .field("active_threshold", &self.active_threshold())
+            .field("rx_wake_up_thrhd", &self.rx_wake_up_thrhd())
+            .field("wk_char_num", &self.wk_char_num())
+            .field("wk_char_mask", &self.wk_char_mask())
+            .field("wk_mode_sel", &self.wk_mode_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/status.rs b/esp32c6/src/uart0/status.rs
index c6f8b87e2e..b94bda636c 100644
--- a/esp32c6/src/uart0/status.rs
+++ b/esp32c6/src/uart0/status.rs
@@ -62,23 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("dsrn", &format_args!("{}", self.dsrn().bit()))
-            .field("ctsn", &format_args!("{}", self.ctsn().bit()))
-            .field("rxd", &format_args!("{}", self.rxd().bit()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field("dtrn", &format_args!("{}", self.dtrn().bit()))
-            .field("rtsn", &format_args!("{}", self.rtsn().bit()))
-            .field("txd", &format_args!("{}", self.txd().bit()))
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("dsrn", &self.dsrn())
+            .field("ctsn", &self.ctsn())
+            .field("rxd", &self.rxd())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("dtrn", &self.dtrn())
+            .field("rtsn", &self.rtsn())
+            .field("txd", &self.txd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32c6/src/uart0/swfc_conf0.rs b/esp32c6/src/uart0/swfc_conf0.rs
index 341967dafc..bbbea9d9e5 100644
--- a/esp32c6/src/uart0/swfc_conf0.rs
+++ b/esp32c6/src/uart0/swfc_conf0.rs
@@ -89,30 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF0")
-            .field("xon_char", &format_args!("{}", self.xon_char().bits()))
-            .field("xoff_char", &format_args!("{}", self.xoff_char().bits()))
-            .field(
-                "xon_xoff_still_send",
-                &format_args!("{}", self.xon_xoff_still_send().bit()),
-            )
-            .field(
-                "sw_flow_con_en",
-                &format_args!("{}", self.sw_flow_con_en().bit()),
-            )
-            .field("xonoff_del", &format_args!("{}", self.xonoff_del().bit()))
-            .field("force_xon", &format_args!("{}", self.force_xon().bit()))
-            .field("force_xoff", &format_args!("{}", self.force_xoff().bit()))
-            .field("send_xon", &format_args!("{}", self.send_xon().bit()))
-            .field("send_xoff", &format_args!("{}", self.send_xoff().bit()))
+            .field("xon_char", &self.xon_char())
+            .field("xoff_char", &self.xoff_char())
+            .field("xon_xoff_still_send", &self.xon_xoff_still_send())
+            .field("sw_flow_con_en", &self.sw_flow_con_en())
+            .field("xonoff_del", &self.xonoff_del())
+            .field("force_xon", &self.force_xon())
+            .field("force_xoff", &self.force_xoff())
+            .field("send_xon", &self.send_xon())
+            .field("send_xoff", &self.send_xoff())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register stores the Xon flow control char."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/swfc_conf1.rs b/esp32c6/src/uart0/swfc_conf1.rs
index f747b693ec..d7558a5286 100644
--- a/esp32c6/src/uart0/swfc_conf1.rs
+++ b/esp32c6/src/uart0/swfc_conf1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF1")
-            .field(
-                "xon_threshold",
-                &format_args!("{}", self.xon_threshold().bits()),
-            )
-            .field(
-                "xoff_threshold",
-                &format_args!("{}", self.xoff_threshold().bits()),
-            )
+            .field("xon_threshold", &self.xon_threshold())
+            .field("xoff_threshold", &self.xoff_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/tout_conf.rs b/esp32c6/src/uart0/tout_conf.rs
index 92fe213cbb..908b3e6b17 100644
--- a/esp32c6/src/uart0/tout_conf.rs
+++ b/esp32c6/src/uart0/tout_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUT_CONF")
-            .field("rx_tout_en", &format_args!("{}", self.rx_tout_en().bit()))
-            .field(
-                "rx_tout_flow_dis",
-                &format_args!("{}", self.rx_tout_flow_dis().bit()),
-            )
-            .field(
-                "rx_tout_thrhd",
-                &format_args!("{}", self.rx_tout_thrhd().bits()),
-            )
+            .field("rx_tout_en", &self.rx_tout_en())
+            .field("rx_tout_flow_dis", &self.rx_tout_flow_dis())
+            .field("rx_tout_thrhd", &self.rx_tout_thrhd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enble bit for uart receiver's timeout function."]
     #[inline(always)]
diff --git a/esp32c6/src/uart0/txbrk_conf.rs b/esp32c6/src/uart0/txbrk_conf.rs
index bfa2a9b911..65d37271c2 100644
--- a/esp32c6/src/uart0/txbrk_conf.rs
+++ b/esp32c6/src/uart0/txbrk_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXBRK_CONF")
-            .field("tx_brk_num", &format_args!("{}", self.tx_brk_num().bits()))
+            .field("tx_brk_num", &self.tx_brk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXBRK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."]
     #[inline(always)]
diff --git a/esp32c6/src/uhci0/ack_num.rs b/esp32c6/src/uhci0/ack_num.rs
index b766a5b42b..05022428cc 100644
--- a/esp32c6/src/uhci0/ack_num.rs
+++ b/esp32c6/src/uhci0/ack_num.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ACK_NUM")
-            .field("ack_num", &format_args!("{}", self.ack_num().bits()))
+            .field("ack_num", &self.ack_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ACK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Indicates the ACK number during software flow control."]
     #[inline(always)]
diff --git a/esp32c6/src/uhci0/conf0.rs b/esp32c6/src/uhci0/conf0.rs
index 8e5312e796..c285d47f45 100644
--- a/esp32c6/src/uhci0/conf0.rs
+++ b/esp32c6/src/uhci0/conf0.rs
@@ -116,36 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("tx_rst", &format_args!("{}", self.tx_rst().bit()))
-            .field("rx_rst", &format_args!("{}", self.rx_rst().bit()))
-            .field("uart0_ce", &format_args!("{}", self.uart0_ce().bit()))
-            .field("uart1_ce", &format_args!("{}", self.uart1_ce().bit()))
-            .field("seper_en", &format_args!("{}", self.seper_en().bit()))
-            .field("head_en", &format_args!("{}", self.head_en().bit()))
-            .field("crc_rec_en", &format_args!("{}", self.crc_rec_en().bit()))
-            .field(
-                "uart_idle_eof_en",
-                &format_args!("{}", self.uart_idle_eof_en().bit()),
-            )
-            .field("len_eof_en", &format_args!("{}", self.len_eof_en().bit()))
-            .field(
-                "encode_crc_en",
-                &format_args!("{}", self.encode_crc_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "uart_rx_brk_eof_en",
-                &format_args!("{}", self.uart_rx_brk_eof_en().bit()),
-            )
+            .field("tx_rst", &self.tx_rst())
+            .field("rx_rst", &self.rx_rst())
+            .field("uart0_ce", &self.uart0_ce())
+            .field("uart1_ce", &self.uart1_ce())
+            .field("seper_en", &self.seper_en())
+            .field("head_en", &self.head_en())
+            .field("crc_rec_en", &self.crc_rec_en())
+            .field("uart_idle_eof_en", &self.uart_idle_eof_en())
+            .field("len_eof_en", &self.len_eof_en())
+            .field("encode_crc_en", &self.encode_crc_en())
+            .field("clk_en", &self.clk_en())
+            .field("uart_rx_brk_eof_en", &self.uart_rx_brk_eof_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 then write 0 to this bit to reset decode state machine."]
     #[inline(always)]
diff --git a/esp32c6/src/uhci0/conf1.rs b/esp32c6/src/uhci0/conf1.rs
index b4ee4f1a42..f5ee721368 100644
--- a/esp32c6/src/uhci0/conf1.rs
+++ b/esp32c6/src/uhci0/conf1.rs
@@ -73,37 +73,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "check_sum_en",
-                &format_args!("{}", self.check_sum_en().bit()),
-            )
-            .field(
-                "check_seq_en",
-                &format_args!("{}", self.check_seq_en().bit()),
-            )
-            .field("crc_disable", &format_args!("{}", self.crc_disable().bit()))
-            .field("save_head", &format_args!("{}", self.save_head().bit()))
-            .field(
-                "tx_check_sum_re",
-                &format_args!("{}", self.tx_check_sum_re().bit()),
-            )
-            .field(
-                "tx_ack_num_re",
-                &format_args!("{}", self.tx_ack_num_re().bit()),
-            )
-            .field(
-                "wait_sw_start",
-                &format_args!("{}", self.wait_sw_start().bit()),
-            )
+            .field("check_sum_en", &self.check_sum_en())
+            .field("check_seq_en", &self.check_seq_en())
+            .field("crc_disable", &self.crc_disable())
+            .field("save_head", &self.save_head())
+            .field("tx_check_sum_re", &self.tx_check_sum_re())
+            .field("tx_ack_num_re", &self.tx_ack_num_re())
+            .field("wait_sw_start", &self.wait_sw_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable head checksum check when receiving."]
     #[inline(always)]
diff --git a/esp32c6/src/uhci0/date.rs b/esp32c6/src/uhci0/date.rs
index b1c29fb247..157a787b5f 100644
--- a/esp32c6/src/uhci0/date.rs
+++ b/esp32c6/src/uhci0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/uhci0/esc_conf.rs b/esp32c6/src/uhci0/esc_conf.rs
index 91511d3359..9c2ddd50ed 100644
--- a/esp32c6/src/uhci0/esc_conf.rs
+++ b/esp32c6/src/uhci0/esc_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ESC_CONF")
-            .field("seper_char", &format_args!("{}", self.seper_char().bits()))
-            .field(
-                "seper_esc_char0",
-                &format_args!("{}", self.seper_esc_char0().bits()),
-            )
-            .field(
-                "seper_esc_char1",
-                &format_args!("{}", self.seper_esc_char1().bits()),
-            )
+            .field("seper_char", &self.seper_char())
+            .field("seper_esc_char0", &self.seper_esc_char0())
+            .field("seper_esc_char1", &self.seper_esc_char1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ESC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures the delimiter for encoding, default value is 0xC0."]
     #[inline(always)]
diff --git a/esp32c6/src/uhci0/escape_conf.rs b/esp32c6/src/uhci0/escape_conf.rs
index 33710ca4d7..3b753424c9 100644
--- a/esp32c6/src/uhci0/escape_conf.rs
+++ b/esp32c6/src/uhci0/escape_conf.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ESCAPE_CONF")
-            .field(
-                "tx_c0_esc_en",
-                &format_args!("{}", self.tx_c0_esc_en().bit()),
-            )
-            .field(
-                "tx_db_esc_en",
-                &format_args!("{}", self.tx_db_esc_en().bit()),
-            )
-            .field(
-                "tx_11_esc_en",
-                &format_args!("{}", self.tx_11_esc_en().bit()),
-            )
-            .field(
-                "tx_13_esc_en",
-                &format_args!("{}", self.tx_13_esc_en().bit()),
-            )
-            .field(
-                "rx_c0_esc_en",
-                &format_args!("{}", self.rx_c0_esc_en().bit()),
-            )
-            .field(
-                "rx_db_esc_en",
-                &format_args!("{}", self.rx_db_esc_en().bit()),
-            )
-            .field(
-                "rx_11_esc_en",
-                &format_args!("{}", self.rx_11_esc_en().bit()),
-            )
-            .field(
-                "rx_13_esc_en",
-                &format_args!("{}", self.rx_13_esc_en().bit()),
-            )
+            .field("tx_c0_esc_en", &self.tx_c0_esc_en())
+            .field("tx_db_esc_en", &self.tx_db_esc_en())
+            .field("tx_11_esc_en", &self.tx_11_esc_en())
+            .field("tx_13_esc_en", &self.tx_13_esc_en())
+            .field("rx_c0_esc_en", &self.rx_c0_esc_en())
+            .field("rx_db_esc_en", &self.rx_db_esc_en())
+            .field("rx_11_esc_en", &self.rx_11_esc_en())
+            .field("rx_13_esc_en", &self.rx_13_esc_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ESCAPE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable resolve char 0xC0 when DMA receiving data."]
     #[inline(always)]
diff --git a/esp32c6/src/uhci0/hung_conf.rs b/esp32c6/src/uhci0/hung_conf.rs
index f0d90d8564..20cd44a030 100644
--- a/esp32c6/src/uhci0/hung_conf.rs
+++ b/esp32c6/src/uhci0/hung_conf.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HUNG_CONF")
-            .field(
-                "txfifo_timeout",
-                &format_args!("{}", self.txfifo_timeout().bits()),
-            )
-            .field(
-                "txfifo_timeout_shift",
-                &format_args!("{}", self.txfifo_timeout_shift().bits()),
-            )
-            .field(
-                "txfifo_timeout_ena",
-                &format_args!("{}", self.txfifo_timeout_ena().bit()),
-            )
-            .field(
-                "rxfifo_timeout",
-                &format_args!("{}", self.rxfifo_timeout().bits()),
-            )
-            .field(
-                "rxfifo_timeout_shift",
-                &format_args!("{}", self.rxfifo_timeout_shift().bits()),
-            )
-            .field(
-                "rxfifo_timeout_ena",
-                &format_args!("{}", self.rxfifo_timeout_ena().bit()),
-            )
+            .field("txfifo_timeout", &self.txfifo_timeout())
+            .field("txfifo_timeout_shift", &self.txfifo_timeout_shift())
+            .field("txfifo_timeout_ena", &self.txfifo_timeout_ena())
+            .field("rxfifo_timeout", &self.rxfifo_timeout())
+            .field("rxfifo_timeout_shift", &self.rxfifo_timeout_shift())
+            .field("rxfifo_timeout_ena", &self.rxfifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving data."]
     #[inline(always)]
diff --git a/esp32c6/src/uhci0/int_ena.rs b/esp32c6/src/uhci0/int_ena.rs
index 10d05b5816..89c8b00078 100644
--- a/esp32c6/src/uhci0/int_ena.rs
+++ b/esp32c6/src/uhci0/int_ena.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
-            .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable the interrupt of UHCI_RX_START_INT."]
     #[inline(always)]
diff --git a/esp32c6/src/uhci0/int_raw.rs b/esp32c6/src/uhci0/int_raw.rs
index 24f110aaa0..47771a616d 100644
--- a/esp32c6/src/uhci0/int_raw.rs
+++ b/esp32c6/src/uhci0/int_raw.rs
@@ -89,30 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
-            .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("out_eof", &self.out_eof())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when delimiter is sent successfully."]
     #[inline(always)]
diff --git a/esp32c6/src/uhci0/int_st.rs b/esp32c6/src/uhci0/int_st.rs
index e02ff60b01..07481b4367 100644
--- a/esp32c6/src/uhci0/int_st.rs
+++ b/esp32c6/src/uhci0/int_st.rs
@@ -69,33 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
-            .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UHCI Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/uhci0/pkt_thres.rs b/esp32c6/src/uhci0/pkt_thres.rs
index 9619b17d53..ada0d1f6da 100644
--- a/esp32c6/src/uhci0/pkt_thres.rs
+++ b/esp32c6/src/uhci0/pkt_thres.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PKT_THRES")
-            .field("pkt_thrs", &format_args!("{}", self.pkt_thrs().bits()))
+            .field("pkt_thrs", &self.pkt_thrs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PKT_THRES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - Configures the data packet's maximum length when UHCI_HEAD_EN is 0."]
     #[inline(always)]
diff --git a/esp32c6/src/uhci0/quick_sent.rs b/esp32c6/src/uhci0/quick_sent.rs
index 486de96911..9e8e78feab 100644
--- a/esp32c6/src/uhci0/quick_sent.rs
+++ b/esp32c6/src/uhci0/quick_sent.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUICK_SENT")
-            .field(
-                "single_send_num",
-                &format_args!("{}", self.single_send_num().bits()),
-            )
-            .field(
-                "always_send_num",
-                &format_args!("{}", self.always_send_num().bits()),
-            )
-            .field(
-                "always_send_en",
-                &format_args!("{}", self.always_send_en().bit()),
-            )
+            .field("single_send_num", &self.single_send_num())
+            .field("always_send_num", &self.always_send_num())
+            .field("always_send_en", &self.always_send_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUICK_SENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Configures single_send mode."]
     #[inline(always)]
diff --git a/esp32c6/src/uhci0/reg_q/word0.rs b/esp32c6/src/uhci0/reg_q/word0.rs
index 625b5f8670..e449869777 100644
--- a/esp32c6/src/uhci0/reg_q/word0.rs
+++ b/esp32c6/src/uhci0/reg_q/word0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WORD0")
-            .field("send_word", &format_args!("{}", self.send_word().bits()))
+            .field("send_word", &self.send_word())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WORD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
     #[inline(always)]
diff --git a/esp32c6/src/uhci0/reg_q/word1.rs b/esp32c6/src/uhci0/reg_q/word1.rs
index b8dfb313c3..7239fdf4ad 100644
--- a/esp32c6/src/uhci0/reg_q/word1.rs
+++ b/esp32c6/src/uhci0/reg_q/word1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WORD1")
-            .field("send_word", &format_args!("{}", self.send_word().bits()))
+            .field("send_word", &self.send_word())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WORD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
     #[inline(always)]
diff --git a/esp32c6/src/uhci0/rx_head.rs b/esp32c6/src/uhci0/rx_head.rs
index afdf07a90c..f28c2d648a 100644
--- a/esp32c6/src/uhci0/rx_head.rs
+++ b/esp32c6/src/uhci0/rx_head.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_HEAD")
-            .field("rx_head", &format_args!("{}", self.rx_head().bits()))
+            .field("rx_head", &self.rx_head())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_HEAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UHCI Head Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_head::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_HEAD_SPEC;
 impl crate::RegisterSpec for RX_HEAD_SPEC {
diff --git a/esp32c6/src/uhci0/state0.rs b/esp32c6/src/uhci0/state0.rs
index 1c5b38008b..23e54cd08a 100644
--- a/esp32c6/src/uhci0/state0.rs
+++ b/esp32c6/src/uhci0/state0.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE0")
-            .field(
-                "rx_err_cause",
-                &format_args!("{}", self.rx_err_cause().bits()),
-            )
-            .field(
-                "decode_state",
-                &format_args!("{}", self.decode_state().bits()),
-            )
+            .field("rx_err_cause", &self.rx_err_cause())
+            .field("decode_state", &self.decode_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UHCI Receive Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE0_SPEC;
 impl crate::RegisterSpec for STATE0_SPEC {
diff --git a/esp32c6/src/uhci0/state1.rs b/esp32c6/src/uhci0/state1.rs
index 2daade578f..23f3c88dd3 100644
--- a/esp32c6/src/uhci0/state1.rs
+++ b/esp32c6/src/uhci0/state1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE1")
-            .field(
-                "encode_state",
-                &format_args!("{}", self.encode_state().bits()),
-            )
+            .field("encode_state", &self.encode_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UHCI Transmit Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE1_SPEC;
 impl crate::RegisterSpec for STATE1_SPEC {
diff --git a/esp32c6/src/usb_device/bus_reset_st.rs b/esp32c6/src/usb_device/bus_reset_st.rs
index 9b463d08d3..3c2d490751 100644
--- a/esp32c6/src/usb_device/bus_reset_st.rs
+++ b/esp32c6/src/usb_device/bus_reset_st.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_RESET_ST")
-            .field(
-                "usb_bus_reset_st",
-                &format_args!("{}", self.usb_bus_reset_st().bit()),
-            )
+            .field("usb_bus_reset_st", &self.usb_bus_reset_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_RESET_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USB Bus reset status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_reset_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUS_RESET_ST_SPEC;
 impl crate::RegisterSpec for BUS_RESET_ST_SPEC {
diff --git a/esp32c6/src/usb_device/chip_rst.rs b/esp32c6/src/usb_device/chip_rst.rs
index f66590e261..3773555886 100644
--- a/esp32c6/src/usb_device/chip_rst.rs
+++ b/esp32c6/src/usb_device/chip_rst.rs
@@ -31,21 +31,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHIP_RST")
-            .field("rts", &format_args!("{}", self.rts().bit()))
-            .field("dtr", &format_args!("{}", self.dtr().bit()))
-            .field(
-                "usb_uart_chip_rst_dis",
-                &format_args!("{}", self.usb_uart_chip_rst_dis().bit()),
-            )
+            .field("rts", &self.rts())
+            .field("dtr", &self.dtr())
+            .field("usb_uart_chip_rst_dis", &self.usb_uart_chip_rst_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHIP_RST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - Set this bit to disable chip reset from usb serial channel to reset chip."]
     #[inline(always)]
diff --git a/esp32c6/src/usb_device/conf0.rs b/esp32c6/src/usb_device/conf0.rs
index d3e851d8f0..fc639deb91 100644
--- a/esp32c6/src/usb_device/conf0.rs
+++ b/esp32c6/src/usb_device/conf0.rs
@@ -134,47 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("phy_sel", &format_args!("{}", self.phy_sel().bit()))
-            .field(
-                "exchg_pins_override",
-                &format_args!("{}", self.exchg_pins_override().bit()),
-            )
-            .field("exchg_pins", &format_args!("{}", self.exchg_pins().bit()))
-            .field("vrefh", &format_args!("{}", self.vrefh().bits()))
-            .field("vrefl", &format_args!("{}", self.vrefl().bits()))
-            .field(
-                "vref_override",
-                &format_args!("{}", self.vref_override().bit()),
-            )
-            .field(
-                "pad_pull_override",
-                &format_args!("{}", self.pad_pull_override().bit()),
-            )
-            .field("dp_pullup", &format_args!("{}", self.dp_pullup().bit()))
-            .field("dp_pulldown", &format_args!("{}", self.dp_pulldown().bit()))
-            .field("dm_pullup", &format_args!("{}", self.dm_pullup().bit()))
-            .field("dm_pulldown", &format_args!("{}", self.dm_pulldown().bit()))
-            .field(
-                "pullup_value",
-                &format_args!("{}", self.pullup_value().bit()),
-            )
-            .field(
-                "usb_pad_enable",
-                &format_args!("{}", self.usb_pad_enable().bit()),
-            )
-            .field(
-                "usb_jtag_bridge_en",
-                &format_args!("{}", self.usb_jtag_bridge_en().bit()),
-            )
+            .field("phy_sel", &self.phy_sel())
+            .field("exchg_pins_override", &self.exchg_pins_override())
+            .field("exchg_pins", &self.exchg_pins())
+            .field("vrefh", &self.vrefh())
+            .field("vrefl", &self.vrefl())
+            .field("vref_override", &self.vref_override())
+            .field("pad_pull_override", &self.pad_pull_override())
+            .field("dp_pullup", &self.dp_pullup())
+            .field("dp_pulldown", &self.dp_pulldown())
+            .field("dm_pullup", &self.dm_pullup())
+            .field("dm_pulldown", &self.dm_pulldown())
+            .field("pullup_value", &self.pullup_value())
+            .field("usb_pad_enable", &self.usb_pad_enable())
+            .field("usb_jtag_bridge_en", &self.usb_jtag_bridge_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Select internal/external PHY"]
     #[inline(always)]
diff --git a/esp32c6/src/usb_device/date.rs b/esp32c6/src/usb_device/date.rs
index 1c49da5683..4c12755e22 100644
--- a/esp32c6/src/usb_device/date.rs
+++ b/esp32c6/src/usb_device/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32c6/src/usb_device/ep1.rs b/esp32c6/src/usb_device/ep1.rs
index 92bed9b30d..d6030184bd 100644
--- a/esp32c6/src/usb_device/ep1.rs
+++ b/esp32c6/src/usb_device/ep1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EP1")
-            .field("rdwr_byte", &format_args!("{}", self.rdwr_byte().bits()))
+            .field("rdwr_byte", &self.rdwr_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO."]
     #[inline(always)]
diff --git a/esp32c6/src/usb_device/ep1_conf.rs b/esp32c6/src/usb_device/ep1_conf.rs
index c99b3b08f6..3534449ebc 100644
--- a/esp32c6/src/usb_device/ep1_conf.rs
+++ b/esp32c6/src/usb_device/ep1_conf.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EP1_CONF")
-            .field(
-                "serial_in_ep_data_free",
-                &format_args!("{}", self.serial_in_ep_data_free().bit()),
-            )
-            .field(
-                "serial_out_ep_data_avail",
-                &format_args!("{}", self.serial_out_ep_data_avail().bit()),
-            )
+            .field("serial_in_ep_data_free", &self.serial_in_ep_data_free())
+            .field("serial_out_ep_data_avail", &self.serial_out_ep_data_avail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EP1_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to indicate writing byte data to UART Tx FIFO is done."]
     #[inline(always)]
diff --git a/esp32c6/src/usb_device/fram_num.rs b/esp32c6/src/usb_device/fram_num.rs
index ee7832b94b..555f25c409 100644
--- a/esp32c6/src/usb_device/fram_num.rs
+++ b/esp32c6/src/usb_device/fram_num.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FRAM_NUM")
-            .field(
-                "sof_frame_index",
-                &format_args!("{}", self.sof_frame_index().bits()),
-            )
+            .field("sof_frame_index", &self.sof_frame_index())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FRAM_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Last received SOF frame index register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fram_num::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FRAM_NUM_SPEC;
 impl crate::RegisterSpec for FRAM_NUM_SPEC {
diff --git a/esp32c6/src/usb_device/get_line_code_w0.rs b/esp32c6/src/usb_device/get_line_code_w0.rs
index d4deae05f4..374fc89555 100644
--- a/esp32c6/src/usb_device/get_line_code_w0.rs
+++ b/esp32c6/src/usb_device/get_line_code_w0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GET_LINE_CODE_W0")
-            .field(
-                "get_dw_dte_rate",
-                &format_args!("{}", self.get_dw_dte_rate().bits()),
-            )
+            .field("get_dw_dte_rate", &self.get_dw_dte_rate())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GET_LINE_CODE_W0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The value of dwDTERate set by software which is requested by GET_LINE_CODING command."]
     #[inline(always)]
diff --git a/esp32c6/src/usb_device/get_line_code_w1.rs b/esp32c6/src/usb_device/get_line_code_w1.rs
index 5ad3080523..d7ae6488a4 100644
--- a/esp32c6/src/usb_device/get_line_code_w1.rs
+++ b/esp32c6/src/usb_device/get_line_code_w1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GET_LINE_CODE_W1")
-            .field(
-                "get_bdata_bits",
-                &format_args!("{}", self.get_bdata_bits().bits()),
-            )
-            .field(
-                "get_bparity_type",
-                &format_args!("{}", self.get_bparity_type().bits()),
-            )
-            .field(
-                "get_bchar_format",
-                &format_args!("{}", self.get_bchar_format().bits()),
-            )
+            .field("get_bdata_bits", &self.get_bdata_bits())
+            .field("get_bparity_type", &self.get_bparity_type())
+            .field("get_bchar_format", &self.get_bchar_format())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GET_LINE_CODE_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value of bCharFormat set by software which is requested by GET_LINE_CODING command."]
     #[inline(always)]
diff --git a/esp32c6/src/usb_device/in_ep0_st.rs b/esp32c6/src/usb_device/in_ep0_st.rs
index cdba70f4ca..5e23d52fee 100644
--- a/esp32c6/src/usb_device/in_ep0_st.rs
+++ b/esp32c6/src/usb_device/in_ep0_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP0_ST")
-            .field(
-                "in_ep0_state",
-                &format_args!("{}", self.in_ep0_state().bits()),
-            )
-            .field(
-                "in_ep0_wr_addr",
-                &format_args!("{}", self.in_ep0_wr_addr().bits()),
-            )
-            .field(
-                "in_ep0_rd_addr",
-                &format_args!("{}", self.in_ep0_rd_addr().bits()),
-            )
+            .field("in_ep0_state", &self.in_ep0_state())
+            .field("in_ep0_wr_addr", &self.in_ep0_wr_addr())
+            .field("in_ep0_rd_addr", &self.in_ep0_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP0_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Control IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep0_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP0_ST_SPEC;
 impl crate::RegisterSpec for IN_EP0_ST_SPEC {
diff --git a/esp32c6/src/usb_device/in_ep1_st.rs b/esp32c6/src/usb_device/in_ep1_st.rs
index c4bbb2bf6b..c1350a8ce8 100644
--- a/esp32c6/src/usb_device/in_ep1_st.rs
+++ b/esp32c6/src/usb_device/in_ep1_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP1_ST")
-            .field(
-                "in_ep1_state",
-                &format_args!("{}", self.in_ep1_state().bits()),
-            )
-            .field(
-                "in_ep1_wr_addr",
-                &format_args!("{}", self.in_ep1_wr_addr().bits()),
-            )
-            .field(
-                "in_ep1_rd_addr",
-                &format_args!("{}", self.in_ep1_rd_addr().bits()),
-            )
+            .field("in_ep1_state", &self.in_ep1_state())
+            .field("in_ep1_wr_addr", &self.in_ep1_wr_addr())
+            .field("in_ep1_rd_addr", &self.in_ep1_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP1_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CDC-ACM IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep1_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP1_ST_SPEC;
 impl crate::RegisterSpec for IN_EP1_ST_SPEC {
diff --git a/esp32c6/src/usb_device/in_ep2_st.rs b/esp32c6/src/usb_device/in_ep2_st.rs
index d7dd32917d..15d0dbaa8d 100644
--- a/esp32c6/src/usb_device/in_ep2_st.rs
+++ b/esp32c6/src/usb_device/in_ep2_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP2_ST")
-            .field(
-                "in_ep2_state",
-                &format_args!("{}", self.in_ep2_state().bits()),
-            )
-            .field(
-                "in_ep2_wr_addr",
-                &format_args!("{}", self.in_ep2_wr_addr().bits()),
-            )
-            .field(
-                "in_ep2_rd_addr",
-                &format_args!("{}", self.in_ep2_rd_addr().bits()),
-            )
+            .field("in_ep2_state", &self.in_ep2_state())
+            .field("in_ep2_wr_addr", &self.in_ep2_wr_addr())
+            .field("in_ep2_rd_addr", &self.in_ep2_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP2_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CDC-ACM interrupt IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep2_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP2_ST_SPEC;
 impl crate::RegisterSpec for IN_EP2_ST_SPEC {
diff --git a/esp32c6/src/usb_device/in_ep3_st.rs b/esp32c6/src/usb_device/in_ep3_st.rs
index c36ea05f61..943dbe3d1c 100644
--- a/esp32c6/src/usb_device/in_ep3_st.rs
+++ b/esp32c6/src/usb_device/in_ep3_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP3_ST")
-            .field(
-                "in_ep3_state",
-                &format_args!("{}", self.in_ep3_state().bits()),
-            )
-            .field(
-                "in_ep3_wr_addr",
-                &format_args!("{}", self.in_ep3_wr_addr().bits()),
-            )
-            .field(
-                "in_ep3_rd_addr",
-                &format_args!("{}", self.in_ep3_rd_addr().bits()),
-            )
+            .field("in_ep3_state", &self.in_ep3_state())
+            .field("in_ep3_wr_addr", &self.in_ep3_wr_addr())
+            .field("in_ep3_rd_addr", &self.in_ep3_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP3_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "JTAG IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep3_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP3_ST_SPEC;
 impl crate::RegisterSpec for IN_EP3_ST_SPEC {
diff --git a/esp32c6/src/usb_device/int_ena.rs b/esp32c6/src/usb_device/int_ena.rs
index 7ed38f620a..e3d498b167 100644
--- a/esp32c6/src/usb_device/int_ena.rs
+++ b/esp32c6/src/usb_device/int_ena.rs
@@ -152,58 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "jtag_in_flush",
-                &format_args!("{}", self.jtag_in_flush().bit()),
-            )
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field(
-                "serial_out_recv_pkt",
-                &format_args!("{}", self.serial_out_recv_pkt().bit()),
-            )
-            .field(
-                "serial_in_empty",
-                &format_args!("{}", self.serial_in_empty().bit()),
-            )
-            .field("pid_err", &format_args!("{}", self.pid_err().bit()))
-            .field("crc5_err", &format_args!("{}", self.crc5_err().bit()))
-            .field("crc16_err", &format_args!("{}", self.crc16_err().bit()))
-            .field("stuff_err", &format_args!("{}", self.stuff_err().bit()))
-            .field(
-                "in_token_rec_in_ep1",
-                &format_args!("{}", self.in_token_rec_in_ep1().bit()),
-            )
-            .field(
-                "usb_bus_reset",
-                &format_args!("{}", self.usb_bus_reset().bit()),
-            )
-            .field(
-                "out_ep1_zero_payload",
-                &format_args!("{}", self.out_ep1_zero_payload().bit()),
-            )
-            .field(
-                "out_ep2_zero_payload",
-                &format_args!("{}", self.out_ep2_zero_payload().bit()),
-            )
-            .field("rts_chg", &format_args!("{}", self.rts_chg().bit()))
-            .field("dtr_chg", &format_args!("{}", self.dtr_chg().bit()))
-            .field(
-                "get_line_code",
-                &format_args!("{}", self.get_line_code().bit()),
-            )
-            .field(
-                "set_line_code",
-                &format_args!("{}", self.set_line_code().bit()),
-            )
+            .field("jtag_in_flush", &self.jtag_in_flush())
+            .field("sof", &self.sof())
+            .field("serial_out_recv_pkt", &self.serial_out_recv_pkt())
+            .field("serial_in_empty", &self.serial_in_empty())
+            .field("pid_err", &self.pid_err())
+            .field("crc5_err", &self.crc5_err())
+            .field("crc16_err", &self.crc16_err())
+            .field("stuff_err", &self.stuff_err())
+            .field("in_token_rec_in_ep1", &self.in_token_rec_in_ep1())
+            .field("usb_bus_reset", &self.usb_bus_reset())
+            .field("out_ep1_zero_payload", &self.out_ep1_zero_payload())
+            .field("out_ep2_zero_payload", &self.out_ep2_zero_payload())
+            .field("rts_chg", &self.rts_chg())
+            .field("dtr_chg", &self.dtr_chg())
+            .field("get_line_code", &self.get_line_code())
+            .field("set_line_code", &self.set_line_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32c6/src/usb_device/int_raw.rs b/esp32c6/src/usb_device/int_raw.rs
index fcb2db63ff..bc22e1a795 100644
--- a/esp32c6/src/usb_device/int_raw.rs
+++ b/esp32c6/src/usb_device/int_raw.rs
@@ -152,58 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "jtag_in_flush",
-                &format_args!("{}", self.jtag_in_flush().bit()),
-            )
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field(
-                "serial_out_recv_pkt",
-                &format_args!("{}", self.serial_out_recv_pkt().bit()),
-            )
-            .field(
-                "serial_in_empty",
-                &format_args!("{}", self.serial_in_empty().bit()),
-            )
-            .field("pid_err", &format_args!("{}", self.pid_err().bit()))
-            .field("crc5_err", &format_args!("{}", self.crc5_err().bit()))
-            .field("crc16_err", &format_args!("{}", self.crc16_err().bit()))
-            .field("stuff_err", &format_args!("{}", self.stuff_err().bit()))
-            .field(
-                "in_token_rec_in_ep1",
-                &format_args!("{}", self.in_token_rec_in_ep1().bit()),
-            )
-            .field(
-                "usb_bus_reset",
-                &format_args!("{}", self.usb_bus_reset().bit()),
-            )
-            .field(
-                "out_ep1_zero_payload",
-                &format_args!("{}", self.out_ep1_zero_payload().bit()),
-            )
-            .field(
-                "out_ep2_zero_payload",
-                &format_args!("{}", self.out_ep2_zero_payload().bit()),
-            )
-            .field("rts_chg", &format_args!("{}", self.rts_chg().bit()))
-            .field("dtr_chg", &format_args!("{}", self.dtr_chg().bit()))
-            .field(
-                "get_line_code",
-                &format_args!("{}", self.get_line_code().bit()),
-            )
-            .field(
-                "set_line_code",
-                &format_args!("{}", self.set_line_code().bit()),
-            )
+            .field("jtag_in_flush", &self.jtag_in_flush())
+            .field("sof", &self.sof())
+            .field("serial_out_recv_pkt", &self.serial_out_recv_pkt())
+            .field("serial_in_empty", &self.serial_in_empty())
+            .field("pid_err", &self.pid_err())
+            .field("crc5_err", &self.crc5_err())
+            .field("crc16_err", &self.crc16_err())
+            .field("stuff_err", &self.stuff_err())
+            .field("in_token_rec_in_ep1", &self.in_token_rec_in_ep1())
+            .field("usb_bus_reset", &self.usb_bus_reset())
+            .field("out_ep1_zero_payload", &self.out_ep1_zero_payload())
+            .field("out_ep2_zero_payload", &self.out_ep2_zero_payload())
+            .field("rts_chg", &self.rts_chg())
+            .field("dtr_chg", &self.dtr_chg())
+            .field("get_line_code", &self.get_line_code())
+            .field("set_line_code", &self.set_line_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG."]
     #[inline(always)]
diff --git a/esp32c6/src/usb_device/int_st.rs b/esp32c6/src/usb_device/int_st.rs
index ec83c07732..d968a2587e 100644
--- a/esp32c6/src/usb_device/int_st.rs
+++ b/esp32c6/src/usb_device/int_st.rs
@@ -118,58 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "jtag_in_flush",
-                &format_args!("{}", self.jtag_in_flush().bit()),
-            )
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field(
-                "serial_out_recv_pkt",
-                &format_args!("{}", self.serial_out_recv_pkt().bit()),
-            )
-            .field(
-                "serial_in_empty",
-                &format_args!("{}", self.serial_in_empty().bit()),
-            )
-            .field("pid_err", &format_args!("{}", self.pid_err().bit()))
-            .field("crc5_err", &format_args!("{}", self.crc5_err().bit()))
-            .field("crc16_err", &format_args!("{}", self.crc16_err().bit()))
-            .field("stuff_err", &format_args!("{}", self.stuff_err().bit()))
-            .field(
-                "in_token_rec_in_ep1",
-                &format_args!("{}", self.in_token_rec_in_ep1().bit()),
-            )
-            .field(
-                "usb_bus_reset",
-                &format_args!("{}", self.usb_bus_reset().bit()),
-            )
-            .field(
-                "out_ep1_zero_payload",
-                &format_args!("{}", self.out_ep1_zero_payload().bit()),
-            )
-            .field(
-                "out_ep2_zero_payload",
-                &format_args!("{}", self.out_ep2_zero_payload().bit()),
-            )
-            .field("rts_chg", &format_args!("{}", self.rts_chg().bit()))
-            .field("dtr_chg", &format_args!("{}", self.dtr_chg().bit()))
-            .field(
-                "get_line_code",
-                &format_args!("{}", self.get_line_code().bit()),
-            )
-            .field(
-                "set_line_code",
-                &format_args!("{}", self.set_line_code().bit()),
-            )
+            .field("jtag_in_flush", &self.jtag_in_flush())
+            .field("sof", &self.sof())
+            .field("serial_out_recv_pkt", &self.serial_out_recv_pkt())
+            .field("serial_in_empty", &self.serial_in_empty())
+            .field("pid_err", &self.pid_err())
+            .field("crc5_err", &self.crc5_err())
+            .field("crc16_err", &self.crc16_err())
+            .field("stuff_err", &self.stuff_err())
+            .field("in_token_rec_in_ep1", &self.in_token_rec_in_ep1())
+            .field("usb_bus_reset", &self.usb_bus_reset())
+            .field("out_ep1_zero_payload", &self.out_ep1_zero_payload())
+            .field("out_ep2_zero_payload", &self.out_ep2_zero_payload())
+            .field("rts_chg", &self.rts_chg())
+            .field("dtr_chg", &self.dtr_chg())
+            .field("get_line_code", &self.get_line_code())
+            .field("set_line_code", &self.set_line_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32c6/src/usb_device/jfifo_st.rs b/esp32c6/src/usb_device/jfifo_st.rs
index 09ed48770d..810e3b4bec 100644
--- a/esp32c6/src/usb_device/jfifo_st.rs
+++ b/esp32c6/src/usb_device/jfifo_st.rs
@@ -68,47 +68,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("JFIFO_ST")
-            .field(
-                "in_fifo_cnt",
-                &format_args!("{}", self.in_fifo_cnt().bits()),
-            )
-            .field(
-                "in_fifo_empty",
-                &format_args!("{}", self.in_fifo_empty().bit()),
-            )
-            .field(
-                "in_fifo_full",
-                &format_args!("{}", self.in_fifo_full().bit()),
-            )
-            .field(
-                "out_fifo_cnt",
-                &format_args!("{}", self.out_fifo_cnt().bits()),
-            )
-            .field(
-                "out_fifo_empty",
-                &format_args!("{}", self.out_fifo_empty().bit()),
-            )
-            .field(
-                "out_fifo_full",
-                &format_args!("{}", self.out_fifo_full().bit()),
-            )
-            .field(
-                "in_fifo_reset",
-                &format_args!("{}", self.in_fifo_reset().bit()),
-            )
-            .field(
-                "out_fifo_reset",
-                &format_args!("{}", self.out_fifo_reset().bit()),
-            )
+            .field("in_fifo_cnt", &self.in_fifo_cnt())
+            .field("in_fifo_empty", &self.in_fifo_empty())
+            .field("in_fifo_full", &self.in_fifo_full())
+            .field("out_fifo_cnt", &self.out_fifo_cnt())
+            .field("out_fifo_empty", &self.out_fifo_empty())
+            .field("out_fifo_full", &self.out_fifo_full())
+            .field("in_fifo_reset", &self.in_fifo_reset())
+            .field("out_fifo_reset", &self.out_fifo_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<JFIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - Write 1 to reset JTAG in fifo."]
     #[inline(always)]
diff --git a/esp32c6/src/usb_device/mem_conf.rs b/esp32c6/src/usb_device/mem_conf.rs
index 682d7c5986..b96d8a21a7 100644
--- a/esp32c6/src/usb_device/mem_conf.rs
+++ b/esp32c6/src/usb_device/mem_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field("usb_mem_pd", &format_args!("{}", self.usb_mem_pd().bit()))
-            .field(
-                "usb_mem_clk_en",
-                &format_args!("{}", self.usb_mem_clk_en().bit()),
-            )
+            .field("usb_mem_pd", &self.usb_mem_pd())
+            .field("usb_mem_clk_en", &self.usb_mem_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: power down usb memory."]
     #[inline(always)]
diff --git a/esp32c6/src/usb_device/misc_conf.rs b/esp32c6/src/usb_device/misc_conf.rs
index 22aeb01318..096db71403 100644
--- a/esp32c6/src/usb_device/misc_conf.rs
+++ b/esp32c6/src/usb_device/misc_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC_CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
     #[inline(always)]
diff --git a/esp32c6/src/usb_device/out_ep0_st.rs b/esp32c6/src/usb_device/out_ep0_st.rs
index beccea168f..9778c6853e 100644
--- a/esp32c6/src/usb_device/out_ep0_st.rs
+++ b/esp32c6/src/usb_device/out_ep0_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EP0_ST")
-            .field(
-                "out_ep0_state",
-                &format_args!("{}", self.out_ep0_state().bits()),
-            )
-            .field(
-                "out_ep0_wr_addr",
-                &format_args!("{}", self.out_ep0_wr_addr().bits()),
-            )
-            .field(
-                "out_ep0_rd_addr",
-                &format_args!("{}", self.out_ep0_rd_addr().bits()),
-            )
+            .field("out_ep0_state", &self.out_ep0_state())
+            .field("out_ep0_wr_addr", &self.out_ep0_wr_addr())
+            .field("out_ep0_rd_addr", &self.out_ep0_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EP0_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Control OUT endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep0_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EP0_ST_SPEC;
 impl crate::RegisterSpec for OUT_EP0_ST_SPEC {
diff --git a/esp32c6/src/usb_device/out_ep1_st.rs b/esp32c6/src/usb_device/out_ep1_st.rs
index 81d1afe476..d1fdcebd8e 100644
--- a/esp32c6/src/usb_device/out_ep1_st.rs
+++ b/esp32c6/src/usb_device/out_ep1_st.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EP1_ST")
-            .field(
-                "out_ep1_state",
-                &format_args!("{}", self.out_ep1_state().bits()),
-            )
-            .field(
-                "out_ep1_wr_addr",
-                &format_args!("{}", self.out_ep1_wr_addr().bits()),
-            )
-            .field(
-                "out_ep1_rd_addr",
-                &format_args!("{}", self.out_ep1_rd_addr().bits()),
-            )
-            .field(
-                "out_ep1_rec_data_cnt",
-                &format_args!("{}", self.out_ep1_rec_data_cnt().bits()),
-            )
+            .field("out_ep1_state", &self.out_ep1_state())
+            .field("out_ep1_wr_addr", &self.out_ep1_wr_addr())
+            .field("out_ep1_rd_addr", &self.out_ep1_rd_addr())
+            .field("out_ep1_rec_data_cnt", &self.out_ep1_rec_data_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EP1_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CDC-ACM OUT endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep1_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EP1_ST_SPEC;
 impl crate::RegisterSpec for OUT_EP1_ST_SPEC {
diff --git a/esp32c6/src/usb_device/out_ep2_st.rs b/esp32c6/src/usb_device/out_ep2_st.rs
index 8e7c84db34..f4bfad5198 100644
--- a/esp32c6/src/usb_device/out_ep2_st.rs
+++ b/esp32c6/src/usb_device/out_ep2_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EP2_ST")
-            .field(
-                "out_ep2_state",
-                &format_args!("{}", self.out_ep2_state().bits()),
-            )
-            .field(
-                "out_ep2_wr_addr",
-                &format_args!("{}", self.out_ep2_wr_addr().bits()),
-            )
-            .field(
-                "out_ep2_rd_addr",
-                &format_args!("{}", self.out_ep2_rd_addr().bits()),
-            )
+            .field("out_ep2_state", &self.out_ep2_state())
+            .field("out_ep2_wr_addr", &self.out_ep2_wr_addr())
+            .field("out_ep2_rd_addr", &self.out_ep2_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EP2_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "JTAG OUT endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep2_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EP2_ST_SPEC;
 impl crate::RegisterSpec for OUT_EP2_ST_SPEC {
diff --git a/esp32c6/src/usb_device/ser_afifo_config.rs b/esp32c6/src/usb_device/ser_afifo_config.rs
index f1fd3f981b..dad03c2716 100644
--- a/esp32c6/src/usb_device/ser_afifo_config.rs
+++ b/esp32c6/src/usb_device/ser_afifo_config.rs
@@ -58,39 +58,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SER_AFIFO_CONFIG")
-            .field(
-                "serial_in_afifo_reset_wr",
-                &format_args!("{}", self.serial_in_afifo_reset_wr().bit()),
-            )
-            .field(
-                "serial_in_afifo_reset_rd",
-                &format_args!("{}", self.serial_in_afifo_reset_rd().bit()),
-            )
+            .field("serial_in_afifo_reset_wr", &self.serial_in_afifo_reset_wr())
+            .field("serial_in_afifo_reset_rd", &self.serial_in_afifo_reset_rd())
             .field(
                 "serial_out_afifo_reset_wr",
-                &format_args!("{}", self.serial_out_afifo_reset_wr().bit()),
+                &self.serial_out_afifo_reset_wr(),
             )
             .field(
                 "serial_out_afifo_reset_rd",
-                &format_args!("{}", self.serial_out_afifo_reset_rd().bit()),
-            )
-            .field(
-                "serial_out_afifo_rempty",
-                &format_args!("{}", self.serial_out_afifo_rempty().bit()),
-            )
-            .field(
-                "serial_in_afifo_wfull",
-                &format_args!("{}", self.serial_in_afifo_wfull().bit()),
+                &self.serial_out_afifo_reset_rd(),
             )
+            .field("serial_out_afifo_rempty", &self.serial_out_afifo_rempty())
+            .field("serial_in_afifo_wfull", &self.serial_in_afifo_wfull())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SER_AFIFO_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to reset CDC_ACM IN async FIFO write clock domain."]
     #[inline(always)]
diff --git a/esp32c6/src/usb_device/set_line_code_w0.rs b/esp32c6/src/usb_device/set_line_code_w0.rs
index c604ef35cd..5fbf6698b5 100644
--- a/esp32c6/src/usb_device/set_line_code_w0.rs
+++ b/esp32c6/src/usb_device/set_line_code_w0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SET_LINE_CODE_W0")
-            .field(
-                "dw_dte_rate",
-                &format_args!("{}", self.dw_dte_rate().bits()),
-            )
+            .field("dw_dte_rate", &self.dw_dte_rate())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SET_LINE_CODE_W0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "W0 of SET_LINE_CODING command.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set_line_code_w0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SET_LINE_CODE_W0_SPEC;
 impl crate::RegisterSpec for SET_LINE_CODE_W0_SPEC {
diff --git a/esp32c6/src/usb_device/set_line_code_w1.rs b/esp32c6/src/usb_device/set_line_code_w1.rs
index 0af91af4b5..214022604e 100644
--- a/esp32c6/src/usb_device/set_line_code_w1.rs
+++ b/esp32c6/src/usb_device/set_line_code_w1.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SET_LINE_CODE_W1")
-            .field(
-                "bchar_format",
-                &format_args!("{}", self.bchar_format().bits()),
-            )
-            .field(
-                "bparity_type",
-                &format_args!("{}", self.bparity_type().bits()),
-            )
-            .field("bdata_bits", &format_args!("{}", self.bdata_bits().bits()))
+            .field("bchar_format", &self.bchar_format())
+            .field("bparity_type", &self.bparity_type())
+            .field("bdata_bits", &self.bdata_bits())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SET_LINE_CODE_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "W1 of SET_LINE_CODING command.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set_line_code_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SET_LINE_CODE_W1_SPEC;
 impl crate::RegisterSpec for SET_LINE_CODE_W1_SPEC {
diff --git a/esp32c6/src/usb_device/test.rs b/esp32c6/src/usb_device/test.rs
index 031148c329..10c7308a91 100644
--- a/esp32c6/src/usb_device/test.rs
+++ b/esp32c6/src/usb_device/test.rs
@@ -65,22 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEST")
-            .field("test_enable", &format_args!("{}", self.test_enable().bit()))
-            .field("test_usb_oe", &format_args!("{}", self.test_usb_oe().bit()))
-            .field("test_tx_dp", &format_args!("{}", self.test_tx_dp().bit()))
-            .field("test_tx_dm", &format_args!("{}", self.test_tx_dm().bit()))
-            .field("test_rx_rcv", &format_args!("{}", self.test_rx_rcv().bit()))
-            .field("test_rx_dp", &format_args!("{}", self.test_rx_dp().bit()))
-            .field("test_rx_dm", &format_args!("{}", self.test_rx_dm().bit()))
+            .field("test_enable", &self.test_enable())
+            .field("test_usb_oe", &self.test_usb_oe())
+            .field("test_tx_dp", &self.test_tx_dp())
+            .field("test_tx_dm", &self.test_tx_dm())
+            .field("test_rx_rcv", &self.test_rx_rcv())
+            .field("test_rx_dp", &self.test_rx_dp())
+            .field("test_rx_dm", &self.test_rx_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable test of the USB pad"]
     #[inline(always)]
diff --git a/esp32h2/src/aes/aad_block_num.rs b/esp32h2/src/aes/aad_block_num.rs
index 75e37b35ae..34160ca226 100644
--- a/esp32h2/src/aes/aad_block_num.rs
+++ b/esp32h2/src/aes/aad_block_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AAD_BLOCK_NUM")
-            .field(
-                "aad_block_num",
-                &format_args!("{}", self.aad_block_num().bits()),
-            )
+            .field("aad_block_num", &self.aad_block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AAD_BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits stores the number of AAD block."]
     #[inline(always)]
diff --git a/esp32h2/src/aes/block_mode.rs b/esp32h2/src/aes/block_mode.rs
index e1da4c4f3c..b2e3b5efc6 100644
--- a/esp32h2/src/aes/block_mode.rs
+++ b/esp32h2/src/aes/block_mode.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLOCK_MODE")
-            .field("block_mode", &format_args!("{}", self.block_mode().bits()))
+            .field("block_mode", &self.block_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLOCK_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved."]
     #[inline(always)]
diff --git a/esp32h2/src/aes/block_num.rs b/esp32h2/src/aes/block_num.rs
index 80e2290bb3..a1897ab822 100644
--- a/esp32h2/src/aes/block_num.rs
+++ b/esp32h2/src/aes/block_num.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLOCK_NUM")
-            .field("block_num", &format_args!("{}", self.block_num().bits()))
+            .field("block_num", &self.block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits stores the number of Plaintext/ciphertext block."]
     #[inline(always)]
diff --git a/esp32h2/src/aes/date.rs b/esp32h2/src/aes/date.rs
index a22c32c101..5e7e48df64 100644
--- a/esp32h2/src/aes/date.rs
+++ b/esp32h2/src/aes/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/aes/dma_enable.rs b/esp32h2/src/aes/dma_enable.rs
index 3fa34abee5..1f5f535a07 100644
--- a/esp32h2/src/aes/dma_enable.rs
+++ b/esp32h2/src/aes/dma_enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_ENABLE")
-            .field("dma_enable", &format_args!("{}", self.dma_enable().bit()))
+            .field("dma_enable", &self.dma_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."]
     #[inline(always)]
diff --git a/esp32h2/src/aes/endian.rs b/esp32h2/src/aes/endian.rs
index e5a3e93efc..30ecf46902 100644
--- a/esp32h2/src/aes/endian.rs
+++ b/esp32h2/src/aes/endian.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENDIAN")
-            .field("endian", &format_args!("{}", self.endian().bits()))
+            .field("endian", &self.endian())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENDIAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - endian. \\[1:0\\] key endian, \\[3:2\\] text_in endian or in_stream endian, \\[5:4\\] text_out endian or out_stream endian"]
     #[inline(always)]
diff --git a/esp32h2/src/aes/h_mem.rs b/esp32h2/src/aes/h_mem.rs
index fcd1d250f9..2e4334ff37 100644
--- a/esp32h2/src/aes/h_mem.rs
+++ b/esp32h2/src/aes/h_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores GCM hash subkey\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct H_MEM_SPEC;
diff --git a/esp32h2/src/aes/inc_sel.rs b/esp32h2/src/aes/inc_sel.rs
index a6665d07ec..69d24607c0 100644
--- a/esp32h2/src/aes/inc_sel.rs
+++ b/esp32h2/src/aes/inc_sel.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INC_SEL")
-            .field("inc_sel", &format_args!("{}", self.inc_sel().bit()))
+            .field("inc_sel", &self.inc_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INC_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit decides the standard incrementing function. 0: INC32. 1: INC128."]
     #[inline(always)]
diff --git a/esp32h2/src/aes/int_ena.rs b/esp32h2/src/aes/int_ena.rs
index ccd96d099f..1abedbe830 100644
--- a/esp32h2/src/aes/int_ena.rs
+++ b/esp32h2/src/aes/int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("int_ena", &format_args!("{}", self.int_ena().bit()))
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable interrupt that occurs when DMA-AES calculation is done."]
     #[inline(always)]
diff --git a/esp32h2/src/aes/iv_mem.rs b/esp32h2/src/aes/iv_mem.rs
index e8b4d332de..20bdbb631b 100644
--- a/esp32h2/src/aes/iv_mem.rs
+++ b/esp32h2/src/aes/iv_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IV_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores initialization vector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iv_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iv_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IV_MEM_SPEC;
diff --git a/esp32h2/src/aes/j0_mem.rs b/esp32h2/src/aes/j0_mem.rs
index a78fdd3452..002c675bfe 100644
--- a/esp32h2/src/aes/j0_mem.rs
+++ b/esp32h2/src/aes/j0_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<J0_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores J0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`j0_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`j0_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct J0_MEM_SPEC;
diff --git a/esp32h2/src/aes/key.rs b/esp32h2/src/aes/key.rs
index 8b2a51282a..c1d2c046ad 100644
--- a/esp32h2/src/aes/key.rs
+++ b/esp32h2/src/aes/key.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("KEY")
-            .field("key", &format_args!("{}", self.key().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<KEY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("KEY").field("key", &self.key()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/aes/mode.rs b/esp32h2/src/aes/mode.rs
index edc4a67756..aa353f24b7 100644
--- a/esp32h2/src/aes/mode.rs
+++ b/esp32h2/src/aes/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/aes/remainder_bit_num.rs b/esp32h2/src/aes/remainder_bit_num.rs
index 330809cbc6..73a3610f09 100644
--- a/esp32h2/src/aes/remainder_bit_num.rs
+++ b/esp32h2/src/aes/remainder_bit_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REMAINDER_BIT_NUM")
-            .field(
-                "remainder_bit_num",
-                &format_args!("{}", self.remainder_bit_num().bits()),
-            )
+            .field("remainder_bit_num", &self.remainder_bit_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REMAINDER_BIT_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Those bits stores the number of remainder bit."]
     #[inline(always)]
diff --git a/esp32h2/src/aes/state.rs b/esp32h2/src/aes/state.rs
index 5a58b13248..8a38798ae3 100644
--- a/esp32h2/src/aes/state.rs
+++ b/esp32h2/src/aes/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("state", &format_args!("{}", self.state().bits()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "AES state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32h2/src/aes/t0_mem.rs b/esp32h2/src/aes/t0_mem.rs
index 1b3fcafdb6..e2445d62f8 100644
--- a/esp32h2/src/aes/t0_mem.rs
+++ b/esp32h2/src/aes/t0_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T0_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores T0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct T0_MEM_SPEC;
diff --git a/esp32h2/src/aes/text_in.rs b/esp32h2/src/aes/text_in.rs
index 71ff18340a..24a5810ee3 100644
--- a/esp32h2/src/aes/text_in.rs
+++ b/esp32h2/src/aes/text_in.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEXT_IN")
-            .field("text_in", &format_args!("{}", self.text_in().bits()))
+            .field("text_in", &self.text_in())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEXT_IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This bits stores text_in_0 that is a part of source text material."]
     #[inline(always)]
diff --git a/esp32h2/src/aes/text_out.rs b/esp32h2/src/aes/text_out.rs
index 4040aae24b..29f631b4b2 100644
--- a/esp32h2/src/aes/text_out.rs
+++ b/esp32h2/src/aes/text_out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEXT_OUT")
-            .field("text_out", &format_args!("{}", self.text_out().bits()))
+            .field("text_out", &self.text_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEXT_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This bits stores text_out_0 that is a part of result text material."]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/arb_ctrl.rs b/esp32h2/src/apb_saradc/arb_ctrl.rs
index de8828334b..51290b0767 100644
--- a/esp32h2/src/apb_saradc/arb_ctrl.rs
+++ b/esp32h2/src/apb_saradc/arb_ctrl.rs
@@ -80,35 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_CTRL")
-            .field("apb_force", &format_args!("{}", self.apb_force().bit()))
-            .field("rtc_force", &format_args!("{}", self.rtc_force().bit()))
-            .field("wifi_force", &format_args!("{}", self.wifi_force().bit()))
-            .field("grant_force", &format_args!("{}", self.grant_force().bit()))
-            .field(
-                "apb_priority",
-                &format_args!("{}", self.apb_priority().bits()),
-            )
-            .field(
-                "rtc_priority",
-                &format_args!("{}", self.rtc_priority().bits()),
-            )
-            .field(
-                "wifi_priority",
-                &format_args!("{}", self.wifi_priority().bits()),
-            )
-            .field(
-                "fix_priority",
-                &format_args!("{}", self.fix_priority().bit()),
-            )
+            .field("apb_force", &self.apb_force())
+            .field("rtc_force", &self.rtc_force())
+            .field("wifi_force", &self.wifi_force())
+            .field("grant_force", &self.grant_force())
+            .field("apb_priority", &self.apb_priority())
+            .field("rtc_priority", &self.rtc_priority())
+            .field("wifi_priority", &self.wifi_priority())
+            .field("fix_priority", &self.fix_priority())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - adc2 arbiter force to enableapb controller"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/cali.rs b/esp32h2/src/apb_saradc/cali.rs
index f8159301ec..4a5f73518e 100644
--- a/esp32h2/src/apb_saradc/cali.rs
+++ b/esp32h2/src/apb_saradc/cali.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CALI")
-            .field("cfg", &format_args!("{}", self.cfg().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CALI").field("cfg", &self.cfg()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/apb_saradc/clkm_conf.rs b/esp32h2/src/apb_saradc/clkm_conf.rs
index 090b7974c0..6d87345504 100644
--- a/esp32h2/src/apb_saradc/clkm_conf.rs
+++ b/esp32h2/src/apb_saradc/clkm_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKM_CONF")
-            .field(
-                "clkm_div_num",
-                &format_args!("{}", self.clkm_div_num().bits()),
-            )
-            .field("clkm_div_b", &format_args!("{}", self.clkm_div_b().bits()))
-            .field("clkm_div_a", &format_args!("{}", self.clkm_div_a().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bits()))
+            .field("clkm_div_num", &self.clkm_div_num())
+            .field("clkm_div_b", &self.clkm_div_b())
+            .field("clkm_div_a", &self.clkm_div_a())
+            .field("clk_en", &self.clk_en())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral I2S clock divider value"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/ctrl.rs b/esp32h2/src/apb_saradc/ctrl.rs
index f3e7955a17..5023dbc902 100644
--- a/esp32h2/src/apb_saradc/ctrl.rs
+++ b/esp32h2/src/apb_saradc/ctrl.rs
@@ -89,45 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("start_force", &format_args!("{}", self.start_force().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field(
-                "sar_clk_gated",
-                &format_args!("{}", self.sar_clk_gated().bit()),
-            )
-            .field(
-                "sar_clk_div",
-                &format_args!("{}", self.sar_clk_div().bits()),
-            )
-            .field(
-                "sar_patt_len",
-                &format_args!("{}", self.sar_patt_len().bits()),
-            )
-            .field(
-                "sar_patt_p_clear",
-                &format_args!("{}", self.sar_patt_p_clear().bit()),
-            )
-            .field(
-                "xpd_sar_force",
-                &format_args!("{}", self.xpd_sar_force().bits()),
-            )
-            .field(
-                "saradc2_pwdet_drv",
-                &format_args!("{}", self.saradc2_pwdet_drv().bit()),
-            )
-            .field(
-                "wait_arb_cycle",
-                &format_args!("{}", self.wait_arb_cycle().bits()),
-            )
+            .field("start_force", &self.start_force())
+            .field("start", &self.start())
+            .field("sar_clk_gated", &self.sar_clk_gated())
+            .field("sar_clk_div", &self.sar_clk_div())
+            .field("sar_patt_len", &self.sar_patt_len())
+            .field("sar_patt_p_clear", &self.sar_patt_p_clear())
+            .field("xpd_sar_force", &self.xpd_sar_force())
+            .field("saradc2_pwdet_drv", &self.saradc2_pwdet_drv())
+            .field("wait_arb_cycle", &self.wait_arb_cycle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - select software enable saradc sample"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/ctrl2.rs b/esp32h2/src/apb_saradc/ctrl2.rs
index 0f067495b8..f8dd029bce 100644
--- a/esp32h2/src/apb_saradc/ctrl2.rs
+++ b/esp32h2/src/apb_saradc/ctrl2.rs
@@ -62,30 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field(
-                "meas_num_limit",
-                &format_args!("{}", self.meas_num_limit().bit()),
-            )
-            .field(
-                "max_meas_num",
-                &format_args!("{}", self.max_meas_num().bits()),
-            )
-            .field("sar1_inv", &format_args!("{}", self.sar1_inv().bit()))
-            .field("sar2_inv", &format_args!("{}", self.sar2_inv().bit()))
-            .field(
-                "timer_target",
-                &format_args!("{}", self.timer_target().bits()),
-            )
-            .field("timer_en", &format_args!("{}", self.timer_en().bit()))
+            .field("meas_num_limit", &self.meas_num_limit())
+            .field("max_meas_num", &self.max_meas_num())
+            .field("sar1_inv", &self.sar1_inv())
+            .field("sar2_inv", &self.sar2_inv())
+            .field("timer_target", &self.timer_target())
+            .field("timer_en", &self.timer_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable max meas num"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/ctrl_date.rs b/esp32h2/src/apb_saradc/ctrl_date.rs
index 9ff2a11ba5..5c42a495e0 100644
--- a/esp32h2/src/apb_saradc/ctrl_date.rs
+++ b/esp32h2/src/apb_saradc/ctrl_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL_DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - version"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/dma_conf.rs b/esp32h2/src/apb_saradc/dma_conf.rs
index f4528f9f98..e8ef94a4b7 100644
--- a/esp32h2/src/apb_saradc/dma_conf.rs
+++ b/esp32h2/src/apb_saradc/dma_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field(
-                "adc_eof_num",
-                &format_args!("{}", self.adc_eof_num().bits()),
-            )
-            .field(
-                "adc_reset_fsm",
-                &format_args!("{}", self.adc_reset_fsm().bit()),
-            )
-            .field("adc_trans", &format_args!("{}", self.adc_trans().bit()))
+            .field("adc_eof_num", &self.adc_eof_num())
+            .field("adc_reset_fsm", &self.adc_reset_fsm())
+            .field("adc_trans", &self.adc_trans())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - the dma_in_suc_eof gen when sample cnt = spi_eof_num"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/filter_ctrl0.rs b/esp32h2/src/apb_saradc/filter_ctrl0.rs
index 17eaaa1fd2..36c2d5446d 100644
--- a/esp32h2/src/apb_saradc/filter_ctrl0.rs
+++ b/esp32h2/src/apb_saradc/filter_ctrl0.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CTRL0")
-            .field(
-                "filter_channel1",
-                &format_args!("{}", self.filter_channel1().bits()),
-            )
-            .field(
-                "filter_channel0",
-                &format_args!("{}", self.filter_channel0().bits()),
-            )
-            .field(
-                "filter_reset",
-                &format_args!("{}", self.filter_reset().bit()),
-            )
+            .field("filter_channel1", &self.filter_channel1())
+            .field("filter_channel0", &self.filter_channel0())
+            .field("filter_reset", &self.filter_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 18:21 - configure filter1 to adc channel"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/filter_ctrl1.rs b/esp32h2/src/apb_saradc/filter_ctrl1.rs
index 5b4e0f3523..9893496ebf 100644
--- a/esp32h2/src/apb_saradc/filter_ctrl1.rs
+++ b/esp32h2/src/apb_saradc/filter_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CTRL1")
-            .field(
-                "filter_factor1",
-                &format_args!("{}", self.filter_factor1().bits()),
-            )
-            .field(
-                "filter_factor0",
-                &format_args!("{}", self.filter_factor0().bits()),
-            )
+            .field("filter_factor1", &self.filter_factor1())
+            .field("filter_factor0", &self.filter_factor0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 26:28 - Factor of saradc filter1"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/fsm_wait.rs b/esp32h2/src/apb_saradc/fsm_wait.rs
index fa4cd82fd6..d100d69e0f 100644
--- a/esp32h2/src/apb_saradc/fsm_wait.rs
+++ b/esp32h2/src/apb_saradc/fsm_wait.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_WAIT")
-            .field("xpd_wait", &format_args!("{}", self.xpd_wait().bits()))
-            .field("rstb_wait", &format_args!("{}", self.rstb_wait().bits()))
-            .field(
-                "standby_wait",
-                &format_args!("{}", self.standby_wait().bits()),
-            )
+            .field("xpd_wait", &self.xpd_wait())
+            .field("rstb_wait", &self.rstb_wait())
+            .field("standby_wait", &self.standby_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_WAIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - saradc_xpd_wait"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/int_ena.rs b/esp32h2/src/apb_saradc/int_ena.rs
index 818483c401..cab97caa9f 100644
--- a/esp32h2/src/apb_saradc/int_ena.rs
+++ b/esp32h2/src/apb_saradc/int_ena.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("tsens", &format_args!("{}", self.tsens().bit()))
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("tsens", &self.tsens())
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - tsens low interrupt enable"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/int_raw.rs b/esp32h2/src/apb_saradc/int_raw.rs
index 640ee93681..7b845e29e0 100644
--- a/esp32h2/src/apb_saradc/int_raw.rs
+++ b/esp32h2/src/apb_saradc/int_raw.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("tsens", &format_args!("{}", self.tsens().bit()))
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("tsens", &self.tsens())
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - saradc tsens interrupt raw"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/int_st.rs b/esp32h2/src/apb_saradc/int_st.rs
index cd1ebbefc6..bddddcc414 100644
--- a/esp32h2/src/apb_saradc/int_st.rs
+++ b/esp32h2/src/apb_saradc/int_st.rs
@@ -55,22 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("tsens", &format_args!("{}", self.tsens().bit()))
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("tsens", &self.tsens())
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc int register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/apb_saradc/onetime_sample.rs b/esp32h2/src/apb_saradc/onetime_sample.rs
index 0c838e5d4d..3e7f7d7c2a 100644
--- a/esp32h2/src/apb_saradc/onetime_sample.rs
+++ b/esp32h2/src/apb_saradc/onetime_sample.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ONETIME_SAMPLE")
-            .field(
-                "onetime_atten",
-                &format_args!("{}", self.onetime_atten().bits()),
-            )
-            .field(
-                "onetime_channel",
-                &format_args!("{}", self.onetime_channel().bits()),
-            )
-            .field(
-                "onetime_start",
-                &format_args!("{}", self.onetime_start().bit()),
-            )
-            .field(
-                "saradc2_onetime_sample",
-                &format_args!("{}", self.saradc2_onetime_sample().bit()),
-            )
-            .field(
-                "saradc1_onetime_sample",
-                &format_args!("{}", self.saradc1_onetime_sample().bit()),
-            )
+            .field("onetime_atten", &self.onetime_atten())
+            .field("onetime_channel", &self.onetime_channel())
+            .field("onetime_start", &self.onetime_start())
+            .field("saradc2_onetime_sample", &self.saradc2_onetime_sample())
+            .field("saradc1_onetime_sample", &self.saradc1_onetime_sample())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ONETIME_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:24 - configure onetime atten"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/sar1_status.rs b/esp32h2/src/apb_saradc/sar1_status.rs
index 9080c76bf7..5982abfbbd 100644
--- a/esp32h2/src/apb_saradc/sar1_status.rs
+++ b/esp32h2/src/apb_saradc/sar1_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_STATUS")
-            .field(
-                "sar1_status",
-                &format_args!("{}", self.sar1_status().bits()),
-            )
+            .field("sar1_status", &self.sar1_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR1_STATUS_SPEC;
 impl crate::RegisterSpec for SAR1_STATUS_SPEC {
diff --git a/esp32h2/src/apb_saradc/sar1data_status.rs b/esp32h2/src/apb_saradc/sar1data_status.rs
index 413ab6231c..8304d75d71 100644
--- a/esp32h2/src/apb_saradc/sar1data_status.rs
+++ b/esp32h2/src/apb_saradc/sar1data_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1DATA_STATUS")
-            .field(
-                "saradc1_data",
-                &format_args!("{}", self.saradc1_data().bits()),
-            )
+            .field("saradc1_data", &self.saradc1_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1DATA_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1data_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR1DATA_STATUS_SPEC;
 impl crate::RegisterSpec for SAR1DATA_STATUS_SPEC {
diff --git a/esp32h2/src/apb_saradc/sar2_status.rs b/esp32h2/src/apb_saradc/sar2_status.rs
index 211fcdd134..09ae8d249b 100644
--- a/esp32h2/src/apb_saradc/sar2_status.rs
+++ b/esp32h2/src/apb_saradc/sar2_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_STATUS")
-            .field(
-                "sar2_status",
-                &format_args!("{}", self.sar2_status().bits()),
-            )
+            .field("sar2_status", &self.sar2_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR2_STATUS_SPEC;
 impl crate::RegisterSpec for SAR2_STATUS_SPEC {
diff --git a/esp32h2/src/apb_saradc/sar2data_status.rs b/esp32h2/src/apb_saradc/sar2data_status.rs
index 9052cd0794..67cd6c6ec5 100644
--- a/esp32h2/src/apb_saradc/sar2data_status.rs
+++ b/esp32h2/src/apb_saradc/sar2data_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2DATA_STATUS")
-            .field(
-                "saradc2_data",
-                &format_args!("{}", self.saradc2_data().bits()),
-            )
+            .field("saradc2_data", &self.saradc2_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2DATA_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital saradc configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2data_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR2DATA_STATUS_SPEC;
 impl crate::RegisterSpec for SAR2DATA_STATUS_SPEC {
diff --git a/esp32h2/src/apb_saradc/sar_patt_tab1.rs b/esp32h2/src/apb_saradc/sar_patt_tab1.rs
index ad981f35f6..e8d275271e 100644
--- a/esp32h2/src/apb_saradc/sar_patt_tab1.rs
+++ b/esp32h2/src/apb_saradc/sar_patt_tab1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_PATT_TAB1")
-            .field(
-                "sar_patt_tab1",
-                &format_args!("{}", self.sar_patt_tab1().bits()),
-            )
+            .field("sar_patt_tab1", &self.sar_patt_tab1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_PATT_TAB1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/sar_patt_tab2.rs b/esp32h2/src/apb_saradc/sar_patt_tab2.rs
index 48390f1cf9..ef0574954e 100644
--- a/esp32h2/src/apb_saradc/sar_patt_tab2.rs
+++ b/esp32h2/src/apb_saradc/sar_patt_tab2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_PATT_TAB2")
-            .field(
-                "sar_patt_tab2",
-                &format_args!("{}", self.sar_patt_tab2().bits()),
-            )
+            .field("sar_patt_tab2", &self.sar_patt_tab2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_PATT_TAB2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/thres0_ctrl.rs b/esp32h2/src/apb_saradc/thres0_ctrl.rs
index 1c7ff5e5c3..3b735155e3 100644
--- a/esp32h2/src/apb_saradc/thres0_ctrl.rs
+++ b/esp32h2/src/apb_saradc/thres0_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES0_CTRL")
-            .field(
-                "thres0_channel",
-                &format_args!("{}", self.thres0_channel().bits()),
-            )
-            .field(
-                "thres0_high",
-                &format_args!("{}", self.thres0_high().bits()),
-            )
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bits()))
+            .field("thres0_channel", &self.thres0_channel())
+            .field("thres0_high", &self.thres0_high())
+            .field("thres0_low", &self.thres0_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES0_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - configure thres0 to adc channel"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/thres1_ctrl.rs b/esp32h2/src/apb_saradc/thres1_ctrl.rs
index 26fb78f9e4..0ae0172e5c 100644
--- a/esp32h2/src/apb_saradc/thres1_ctrl.rs
+++ b/esp32h2/src/apb_saradc/thres1_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES1_CTRL")
-            .field(
-                "thres1_channel",
-                &format_args!("{}", self.thres1_channel().bits()),
-            )
-            .field(
-                "thres1_high",
-                &format_args!("{}", self.thres1_high().bits()),
-            )
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bits()))
+            .field("thres1_channel", &self.thres1_channel())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres1_low", &self.thres1_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES1_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - configure thres1 to adc channel"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/thres_ctrl.rs b/esp32h2/src/apb_saradc/thres_ctrl.rs
index c3d03adf77..040e84e114 100644
--- a/esp32h2/src/apb_saradc/thres_ctrl.rs
+++ b/esp32h2/src/apb_saradc/thres_ctrl.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES_CTRL")
-            .field(
-                "thres_all_en",
-                &format_args!("{}", self.thres_all_en().bit()),
-            )
-            .field("thres1_en", &format_args!("{}", self.thres1_en().bit()))
-            .field("thres0_en", &format_args!("{}", self.thres0_en().bit()))
+            .field("thres_all_en", &self.thres_all_en())
+            .field("thres1_en", &self.thres1_en())
+            .field("thres0_en", &self.thres0_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - enable thres to all channel"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/tsens_ctrl.rs b/esp32h2/src/apb_saradc/tsens_ctrl.rs
index c7b28ab6c1..b6cd198968 100644
--- a/esp32h2/src/apb_saradc/tsens_ctrl.rs
+++ b/esp32h2/src/apb_saradc/tsens_ctrl.rs
@@ -42,19 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSENS_CTRL")
-            .field("out", &format_args!("{}", self.out().bits()))
-            .field("in_inv", &format_args!("{}", self.in_inv().bit()))
-            .field("clk_div", &format_args!("{}", self.clk_div().bits()))
-            .field("pu", &format_args!("{}", self.pu().bit()))
+            .field("out", &self.out())
+            .field("in_inv", &self.in_inv())
+            .field("clk_div", &self.clk_div())
+            .field("pu", &self.pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSENS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - invert temperature sensor data"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/tsens_ctrl2.rs b/esp32h2/src/apb_saradc/tsens_ctrl2.rs
index bd67d42d0e..dd559966b9 100644
--- a/esp32h2/src/apb_saradc/tsens_ctrl2.rs
+++ b/esp32h2/src/apb_saradc/tsens_ctrl2.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSENS_CTRL2")
-            .field("xpd_wait", &format_args!("{}", self.xpd_wait().bits()))
-            .field("xpd_force", &format_args!("{}", self.xpd_force().bits()))
-            .field("clk_inv", &format_args!("{}", self.clk_inv().bit()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bit()))
+            .field("xpd_wait", &self.xpd_wait())
+            .field("xpd_force", &self.xpd_force())
+            .field("clk_inv", &self.clk_inv())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSENS_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - the time that power up tsens need wait"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/tsens_sample.rs b/esp32h2/src/apb_saradc/tsens_sample.rs
index a0a09b8c74..9997e07470 100644
--- a/esp32h2/src/apb_saradc/tsens_sample.rs
+++ b/esp32h2/src/apb_saradc/tsens_sample.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSENS_SAMPLE")
-            .field("rate", &format_args!("{}", self.rate().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("rate", &self.rate())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSENS_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - HW sample rate"]
     #[inline(always)]
diff --git a/esp32h2/src/apb_saradc/tsens_wake.rs b/esp32h2/src/apb_saradc/tsens_wake.rs
index 0e49283226..b1d4300c39 100644
--- a/esp32h2/src/apb_saradc/tsens_wake.rs
+++ b/esp32h2/src/apb_saradc/tsens_wake.rs
@@ -51,29 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSENS_WAKE")
-            .field(
-                "wakeup_th_low",
-                &format_args!("{}", self.wakeup_th_low().bits()),
-            )
-            .field(
-                "wakeup_th_high",
-                &format_args!("{}", self.wakeup_th_high().bits()),
-            )
-            .field(
-                "wakeup_over_upper_th",
-                &format_args!("{}", self.wakeup_over_upper_th().bit()),
-            )
-            .field("wakeup_mode", &format_args!("{}", self.wakeup_mode().bit()))
-            .field("wakeup_en", &format_args!("{}", self.wakeup_en().bit()))
+            .field("wakeup_th_low", &self.wakeup_th_low())
+            .field("wakeup_th_high", &self.wakeup_th_high())
+            .field("wakeup_over_upper_th", &self.wakeup_over_upper_th())
+            .field("wakeup_mode", &self.wakeup_mode())
+            .field("wakeup_en", &self.wakeup_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSENS_WAKE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - reg_wakeup_th_low"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/c0re_0_debug_mode.rs b/esp32h2/src/assist_debug/c0re_0_debug_mode.rs
index 7237343fdc..ed3e7a64c0 100644
--- a/esp32h2/src/assist_debug/c0re_0_debug_mode.rs
+++ b/esp32h2/src/assist_debug/c0re_0_debug_mode.rs
@@ -20,23 +20,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("C0RE_0_DEBUG_MODE")
-            .field(
-                "core_0_debug_mode",
-                &format_args!("{}", self.core_0_debug_mode().bit()),
-            )
+            .field("core_0_debug_mode", &self.core_0_debug_mode())
             .field(
                 "core_0_debug_module_active",
-                &format_args!("{}", self.core_0_debug_module_active().bit()),
+                &self.core_0_debug_module_active(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<C0RE_0_DEBUG_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0re_0_debug_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct C0RE_0_DEBUG_MODE_SPEC;
 impl crate::RegisterSpec for C0RE_0_DEBUG_MODE_SPEC {
diff --git a/esp32h2/src/assist_debug/c0re_0_lastpc_before_exception.rs b/esp32h2/src/assist_debug/c0re_0_lastpc_before_exception.rs
index 9c2b7a9487..1372ab5152 100644
--- a/esp32h2/src/assist_debug/c0re_0_lastpc_before_exception.rs
+++ b/esp32h2/src/assist_debug/c0re_0_lastpc_before_exception.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("C0RE_0_LASTPC_BEFORE_EXCEPTION")
-            .field(
-                "core_0_lastpc_before_exc",
-                &format_args!("{}", self.core_0_lastpc_before_exc().bits()),
-            )
+            .field("core_0_lastpc_before_exc", &self.core_0_lastpc_before_exc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<C0RE_0_LASTPC_BEFORE_EXCEPTION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c0re_0_lastpc_before_exception::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct C0RE_0_LASTPC_BEFORE_EXCEPTION_SPEC;
 impl crate::RegisterSpec for C0RE_0_LASTPC_BEFORE_EXCEPTION_SPEC {
diff --git a/esp32h2/src/assist_debug/clock_gate.rs b/esp32h2/src/assist_debug/clock_gate.rs
index e123579679..743c121add 100644
--- a/esp32h2/src/assist_debug/clock_gate.rs
+++ b/esp32h2/src/assist_debug/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 force on the clock gate"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/core_0_area_dram0_0_max.rs b/esp32h2/src/assist_debug/core_0_area_dram0_0_max.rs
index 005d6a6db3..9428c7292a 100644
--- a/esp32h2/src/assist_debug/core_0_area_dram0_0_max.rs
+++ b/esp32h2/src/assist_debug/core_0_area_dram0_0_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_0_MAX")
-            .field(
-                "core_0_area_dram0_0_max",
-                &format_args!("{}", self.core_0_area_dram0_0_max().bits()),
-            )
+            .field("core_0_area_dram0_0_max", &self.core_0_area_dram0_0_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_0_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region0 end addr"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/core_0_area_dram0_0_min.rs b/esp32h2/src/assist_debug/core_0_area_dram0_0_min.rs
index 82ad82fe11..7bbd0597a1 100644
--- a/esp32h2/src/assist_debug/core_0_area_dram0_0_min.rs
+++ b/esp32h2/src/assist_debug/core_0_area_dram0_0_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_0_MIN")
-            .field(
-                "core_0_area_dram0_0_min",
-                &format_args!("{}", self.core_0_area_dram0_0_min().bits()),
-            )
+            .field("core_0_area_dram0_0_min", &self.core_0_area_dram0_0_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_0_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region0 start addr"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/core_0_area_dram0_1_max.rs b/esp32h2/src/assist_debug/core_0_area_dram0_1_max.rs
index 5386b16204..e6dcd4c10a 100644
--- a/esp32h2/src/assist_debug/core_0_area_dram0_1_max.rs
+++ b/esp32h2/src/assist_debug/core_0_area_dram0_1_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_1_MAX")
-            .field(
-                "core_0_area_dram0_1_max",
-                &format_args!("{}", self.core_0_area_dram0_1_max().bits()),
-            )
+            .field("core_0_area_dram0_1_max", &self.core_0_area_dram0_1_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_1_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region1 end addr"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/core_0_area_dram0_1_min.rs b/esp32h2/src/assist_debug/core_0_area_dram0_1_min.rs
index a60f37cb77..9a5ba5db20 100644
--- a/esp32h2/src/assist_debug/core_0_area_dram0_1_min.rs
+++ b/esp32h2/src/assist_debug/core_0_area_dram0_1_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_1_MIN")
-            .field(
-                "core_0_area_dram0_1_min",
-                &format_args!("{}", self.core_0_area_dram0_1_min().bits()),
-            )
+            .field("core_0_area_dram0_1_min", &self.core_0_area_dram0_1_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_1_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region1 start addr"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/core_0_area_pc.rs b/esp32h2/src/assist_debug/core_0_area_pc.rs
index 41c4d55664..ecc0023648 100644
--- a/esp32h2/src/assist_debug/core_0_area_pc.rs
+++ b/esp32h2/src/assist_debug/core_0_area_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PC")
-            .field(
-                "core_0_area_pc",
-                &format_args!("{}", self.core_0_area_pc().bits()),
-            )
+            .field("core_0_area_pc", &self.core_0_area_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 area pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_AREA_PC_SPEC;
 impl crate::RegisterSpec for CORE_0_AREA_PC_SPEC {
diff --git a/esp32h2/src/assist_debug/core_0_area_pif_0_max.rs b/esp32h2/src/assist_debug/core_0_area_pif_0_max.rs
index 272d2c2274..2f0e9bd13c 100644
--- a/esp32h2/src/assist_debug/core_0_area_pif_0_max.rs
+++ b/esp32h2/src/assist_debug/core_0_area_pif_0_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_0_MAX")
-            .field(
-                "core_0_area_pif_0_max",
-                &format_args!("{}", self.core_0_area_pif_0_max().bits()),
-            )
+            .field("core_0_area_pif_0_max", &self.core_0_area_pif_0_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_0_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region0 end addr"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/core_0_area_pif_0_min.rs b/esp32h2/src/assist_debug/core_0_area_pif_0_min.rs
index 6ecf444727..88c0d9e5da 100644
--- a/esp32h2/src/assist_debug/core_0_area_pif_0_min.rs
+++ b/esp32h2/src/assist_debug/core_0_area_pif_0_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_0_MIN")
-            .field(
-                "core_0_area_pif_0_min",
-                &format_args!("{}", self.core_0_area_pif_0_min().bits()),
-            )
+            .field("core_0_area_pif_0_min", &self.core_0_area_pif_0_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_0_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region0 start addr"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/core_0_area_pif_1_max.rs b/esp32h2/src/assist_debug/core_0_area_pif_1_max.rs
index 1d79804931..5a00986603 100644
--- a/esp32h2/src/assist_debug/core_0_area_pif_1_max.rs
+++ b/esp32h2/src/assist_debug/core_0_area_pif_1_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_1_MAX")
-            .field(
-                "core_0_area_pif_1_max",
-                &format_args!("{}", self.core_0_area_pif_1_max().bits()),
-            )
+            .field("core_0_area_pif_1_max", &self.core_0_area_pif_1_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_1_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region1 end addr"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/core_0_area_pif_1_min.rs b/esp32h2/src/assist_debug/core_0_area_pif_1_min.rs
index 7a20c8326f..d75bae477d 100644
--- a/esp32h2/src/assist_debug/core_0_area_pif_1_min.rs
+++ b/esp32h2/src/assist_debug/core_0_area_pif_1_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_1_MIN")
-            .field(
-                "core_0_area_pif_1_min",
-                &format_args!("{}", self.core_0_area_pif_1_min().bits()),
-            )
+            .field("core_0_area_pif_1_min", &self.core_0_area_pif_1_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_1_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region1 start addr"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/core_0_area_sp.rs b/esp32h2/src/assist_debug/core_0_area_sp.rs
index 7f80b9076b..f325b5fbe5 100644
--- a/esp32h2/src/assist_debug/core_0_area_sp.rs
+++ b/esp32h2/src/assist_debug/core_0_area_sp.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_SP")
-            .field(
-                "core_0_area_sp",
-                &format_args!("{}", self.core_0_area_sp().bits()),
-            )
+            .field("core_0_area_sp", &self.core_0_area_sp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_SP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 area sp status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_sp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_AREA_SP_SPEC;
 impl crate::RegisterSpec for CORE_0_AREA_SP_SPEC {
diff --git a/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_0.rs b/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_0.rs
index 8b493eb6d0..c131c93200 100644
--- a/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_0.rs
+++ b/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_0.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_0_dram0_recording_addr_0",
-                &format_args!("{}", self.core_0_dram0_recording_addr_0().bits()),
+                &self.core_0_dram0_recording_addr_0(),
             )
             .field(
                 "core_0_dram0_recording_wr_0",
-                &format_args!("{}", self.core_0_dram0_recording_wr_0().bit()),
+                &self.core_0_dram0_recording_wr_0(),
             )
             .field(
                 "core_0_dram0_recording_byteen_0",
-                &format_args!("{}", self.core_0_dram0_recording_byteen_0().bits()),
+                &self.core_0_dram0_recording_byteen_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC {
diff --git a/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_1.rs b/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_1.rs
index a0d0c537e7..0ecd958fff 100644
--- a/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_1.rs
+++ b/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_0_dram0_recording_pc_0",
-                &format_args!("{}", self.core_0_dram0_recording_pc_0().bits()),
+                &self.core_0_dram0_recording_pc_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC {
diff --git a/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_2.rs b/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_2.rs
index 9a92a1a979..aa220b802b 100644
--- a/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_2.rs
+++ b/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_2.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_2")
             .field(
                 "core_0_dram0_recording_addr_1",
-                &format_args!("{}", self.core_0_dram0_recording_addr_1().bits()),
+                &self.core_0_dram0_recording_addr_1(),
             )
             .field(
                 "core_0_dram0_recording_wr_1",
-                &format_args!("{}", self.core_0_dram0_recording_wr_1().bit()),
+                &self.core_0_dram0_recording_wr_1(),
             )
             .field(
                 "core_0_dram0_recording_byteen_1",
-                &format_args!("{}", self.core_0_dram0_recording_byteen_1().bits()),
+                &self.core_0_dram0_recording_byteen_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC {
diff --git a/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_3.rs b/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_3.rs
index 5533f35db5..cf67b62d88 100644
--- a/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_3.rs
+++ b/esp32h2/src/assist_debug/core_0_dram0_exception_monitor_3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_3")
             .field(
                 "core_0_dram0_recording_pc_1",
-                &format_args!("{}", self.core_0_dram0_recording_pc_1().bits()),
+                &self.core_0_dram0_recording_pc_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC {
diff --git a/esp32h2/src/assist_debug/core_0_intr_ena.rs b/esp32h2/src/assist_debug/core_0_intr_ena.rs
index 91fa6472fa..bc9eaf8e18 100644
--- a/esp32h2/src/assist_debug/core_0_intr_ena.rs
+++ b/esp32h2/src/assist_debug/core_0_intr_ena.rs
@@ -122,61 +122,55 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_INTR_ENA")
             .field(
                 "core_0_area_dram0_0_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_intr_ena().bit()),
+                &self.core_0_area_dram0_0_rd_intr_ena(),
             )
             .field(
                 "core_0_area_dram0_0_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_intr_ena().bit()),
+                &self.core_0_area_dram0_0_wr_intr_ena(),
             )
             .field(
                 "core_0_area_dram0_1_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_intr_ena().bit()),
+                &self.core_0_area_dram0_1_rd_intr_ena(),
             )
             .field(
                 "core_0_area_dram0_1_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_intr_ena().bit()),
+                &self.core_0_area_dram0_1_wr_intr_ena(),
             )
             .field(
                 "core_0_area_pif_0_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_0_rd_intr_ena().bit()),
+                &self.core_0_area_pif_0_rd_intr_ena(),
             )
             .field(
                 "core_0_area_pif_0_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_0_wr_intr_ena().bit()),
+                &self.core_0_area_pif_0_wr_intr_ena(),
             )
             .field(
                 "core_0_area_pif_1_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_1_rd_intr_ena().bit()),
+                &self.core_0_area_pif_1_rd_intr_ena(),
             )
             .field(
                 "core_0_area_pif_1_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_1_wr_intr_ena().bit()),
+                &self.core_0_area_pif_1_wr_intr_ena(),
             )
             .field(
                 "core_0_sp_spill_min_intr_ena",
-                &format_args!("{}", self.core_0_sp_spill_min_intr_ena().bit()),
+                &self.core_0_sp_spill_min_intr_ena(),
             )
             .field(
                 "core_0_sp_spill_max_intr_ena",
-                &format_args!("{}", self.core_0_sp_spill_max_intr_ena().bit()),
+                &self.core_0_sp_spill_max_intr_ena(),
             )
             .field(
                 "core_0_iram0_exception_monitor_intr_ena",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_intr_ena().bit()),
+                &self.core_0_iram0_exception_monitor_intr_ena(),
             )
             .field(
                 "core_0_dram0_exception_monitor_intr_ena",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_intr_ena().bit()),
+                &self.core_0_dram0_exception_monitor_intr_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_INTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt enable"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/core_0_intr_raw.rs b/esp32h2/src/assist_debug/core_0_intr_raw.rs
index 4ae15ba38c..1d30267746 100644
--- a/esp32h2/src/assist_debug/core_0_intr_raw.rs
+++ b/esp32h2/src/assist_debug/core_0_intr_raw.rs
@@ -92,61 +92,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_INTR_RAW")
             .field(
                 "core_0_area_dram0_0_rd_raw",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_raw().bit()),
+                &self.core_0_area_dram0_0_rd_raw(),
             )
             .field(
                 "core_0_area_dram0_0_wr_raw",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_raw().bit()),
+                &self.core_0_area_dram0_0_wr_raw(),
             )
             .field(
                 "core_0_area_dram0_1_rd_raw",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_raw().bit()),
+                &self.core_0_area_dram0_1_rd_raw(),
             )
             .field(
                 "core_0_area_dram0_1_wr_raw",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_rd_raw",
-                &format_args!("{}", self.core_0_area_pif_0_rd_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_wr_raw",
-                &format_args!("{}", self.core_0_area_pif_0_wr_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_rd_raw",
-                &format_args!("{}", self.core_0_area_pif_1_rd_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_wr_raw",
-                &format_args!("{}", self.core_0_area_pif_1_wr_raw().bit()),
-            )
-            .field(
-                "core_0_sp_spill_min_raw",
-                &format_args!("{}", self.core_0_sp_spill_min_raw().bit()),
-            )
-            .field(
-                "core_0_sp_spill_max_raw",
-                &format_args!("{}", self.core_0_sp_spill_max_raw().bit()),
+                &self.core_0_area_dram0_1_wr_raw(),
             )
+            .field("core_0_area_pif_0_rd_raw", &self.core_0_area_pif_0_rd_raw())
+            .field("core_0_area_pif_0_wr_raw", &self.core_0_area_pif_0_wr_raw())
+            .field("core_0_area_pif_1_rd_raw", &self.core_0_area_pif_1_rd_raw())
+            .field("core_0_area_pif_1_wr_raw", &self.core_0_area_pif_1_wr_raw())
+            .field("core_0_sp_spill_min_raw", &self.core_0_sp_spill_min_raw())
+            .field("core_0_sp_spill_max_raw", &self.core_0_sp_spill_max_raw())
             .field(
                 "core_0_iram0_exception_monitor_raw",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_raw().bit()),
+                &self.core_0_iram0_exception_monitor_raw(),
             )
             .field(
                 "core_0_dram0_exception_monitor_raw",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_raw().bit()),
+                &self.core_0_dram0_exception_monitor_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_INTR_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 monitor interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_intr_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_INTR_RAW_SPEC;
 impl crate::RegisterSpec for CORE_0_INTR_RAW_SPEC {
diff --git a/esp32h2/src/assist_debug/core_0_iram0_exception_monitor_0.rs b/esp32h2/src/assist_debug/core_0_iram0_exception_monitor_0.rs
index 5a4ee4189b..b653f3207f 100644
--- a/esp32h2/src/assist_debug/core_0_iram0_exception_monitor_0.rs
+++ b/esp32h2/src/assist_debug/core_0_iram0_exception_monitor_0.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_0_iram0_recording_addr_0",
-                &format_args!("{}", self.core_0_iram0_recording_addr_0().bits()),
+                &self.core_0_iram0_recording_addr_0(),
             )
             .field(
                 "core_0_iram0_recording_wr_0",
-                &format_args!("{}", self.core_0_iram0_recording_wr_0().bit()),
+                &self.core_0_iram0_recording_wr_0(),
             )
             .field(
                 "core_0_iram0_recording_loadstore_0",
-                &format_args!("{}", self.core_0_iram0_recording_loadstore_0().bit()),
+                &self.core_0_iram0_recording_loadstore_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_exception_monitor_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC;
 impl crate::RegisterSpec for CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC {
diff --git a/esp32h2/src/assist_debug/core_0_iram0_exception_monitor_1.rs b/esp32h2/src/assist_debug/core_0_iram0_exception_monitor_1.rs
index 6fef16c53f..015b3f1b8e 100644
--- a/esp32h2/src/assist_debug/core_0_iram0_exception_monitor_1.rs
+++ b/esp32h2/src/assist_debug/core_0_iram0_exception_monitor_1.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_0_iram0_recording_addr_1",
-                &format_args!("{}", self.core_0_iram0_recording_addr_1().bits()),
+                &self.core_0_iram0_recording_addr_1(),
             )
             .field(
                 "core_0_iram0_recording_wr_1",
-                &format_args!("{}", self.core_0_iram0_recording_wr_1().bit()),
+                &self.core_0_iram0_recording_wr_1(),
             )
             .field(
                 "core_0_iram0_recording_loadstore_1",
-                &format_args!("{}", self.core_0_iram0_recording_loadstore_1().bit()),
+                &self.core_0_iram0_recording_loadstore_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_exception_monitor_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC;
 impl crate::RegisterSpec for CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC {
diff --git a/esp32h2/src/assist_debug/core_0_montr_ena.rs b/esp32h2/src/assist_debug/core_0_montr_ena.rs
index fc8ca8d601..90aa60feec 100644
--- a/esp32h2/src/assist_debug/core_0_montr_ena.rs
+++ b/esp32h2/src/assist_debug/core_0_montr_ena.rs
@@ -118,61 +118,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_MONTR_ENA")
             .field(
                 "core_0_area_dram0_0_rd_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_ena().bit()),
+                &self.core_0_area_dram0_0_rd_ena(),
             )
             .field(
                 "core_0_area_dram0_0_wr_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_ena().bit()),
+                &self.core_0_area_dram0_0_wr_ena(),
             )
             .field(
                 "core_0_area_dram0_1_rd_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_ena().bit()),
+                &self.core_0_area_dram0_1_rd_ena(),
             )
             .field(
                 "core_0_area_dram0_1_wr_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_rd_ena",
-                &format_args!("{}", self.core_0_area_pif_0_rd_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_wr_ena",
-                &format_args!("{}", self.core_0_area_pif_0_wr_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_rd_ena",
-                &format_args!("{}", self.core_0_area_pif_1_rd_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_wr_ena",
-                &format_args!("{}", self.core_0_area_pif_1_wr_ena().bit()),
-            )
-            .field(
-                "core_0_sp_spill_min_ena",
-                &format_args!("{}", self.core_0_sp_spill_min_ena().bit()),
-            )
-            .field(
-                "core_0_sp_spill_max_ena",
-                &format_args!("{}", self.core_0_sp_spill_max_ena().bit()),
+                &self.core_0_area_dram0_1_wr_ena(),
             )
+            .field("core_0_area_pif_0_rd_ena", &self.core_0_area_pif_0_rd_ena())
+            .field("core_0_area_pif_0_wr_ena", &self.core_0_area_pif_0_wr_ena())
+            .field("core_0_area_pif_1_rd_ena", &self.core_0_area_pif_1_rd_ena())
+            .field("core_0_area_pif_1_wr_ena", &self.core_0_area_pif_1_wr_ena())
+            .field("core_0_sp_spill_min_ena", &self.core_0_sp_spill_min_ena())
+            .field("core_0_sp_spill_max_ena", &self.core_0_sp_spill_max_ena())
             .field(
                 "core_0_iram0_exception_monitor_ena",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_ena().bit()),
+                &self.core_0_iram0_exception_monitor_ena(),
             )
             .field(
                 "core_0_dram0_exception_monitor_ena",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_ena().bit()),
+                &self.core_0_dram0_exception_monitor_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_MONTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core0 dram0 area0 read monitor enable"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/core_0_rcd_en.rs b/esp32h2/src/assist_debug/core_0_rcd_en.rs
index c32ca92cbc..8a365dc63d 100644
--- a/esp32h2/src/assist_debug/core_0_rcd_en.rs
+++ b/esp32h2/src/assist_debug/core_0_rcd_en.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_EN")
-            .field(
-                "core_0_rcd_recorden",
-                &format_args!("{}", self.core_0_rcd_recorden().bit()),
-            )
-            .field(
-                "core_0_rcd_pdebugen",
-                &format_args!("{}", self.core_0_rcd_pdebugen().bit()),
-            )
+            .field("core_0_rcd_recorden", &self.core_0_rcd_recorden())
+            .field("core_0_rcd_pdebugen", &self.core_0_rcd_pdebugen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable record PC"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/core_0_rcd_pdebugpc.rs b/esp32h2/src/assist_debug/core_0_rcd_pdebugpc.rs
index 57525f3096..f683fc645a 100644
--- a/esp32h2/src/assist_debug/core_0_rcd_pdebugpc.rs
+++ b/esp32h2/src/assist_debug/core_0_rcd_pdebugpc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGPC")
-            .field(
-                "core_0_rcd_pdebugpc",
-                &format_args!("{}", self.core_0_rcd_pdebugpc().bits()),
-            )
+            .field("core_0_rcd_pdebugpc", &self.core_0_rcd_pdebugpc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGPC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugpc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGPC_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGPC_SPEC {
diff --git a/esp32h2/src/assist_debug/core_0_rcd_pdebugsp.rs b/esp32h2/src/assist_debug/core_0_rcd_pdebugsp.rs
index 5299a97c98..acd394b30c 100644
--- a/esp32h2/src/assist_debug/core_0_rcd_pdebugsp.rs
+++ b/esp32h2/src/assist_debug/core_0_rcd_pdebugsp.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGSP")
-            .field(
-                "core_0_rcd_pdebugsp",
-                &format_args!("{}", self.core_0_rcd_pdebugsp().bits()),
-            )
+            .field("core_0_rcd_pdebugsp", &self.core_0_rcd_pdebugsp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGSP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugsp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGSP_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGSP_SPEC {
diff --git a/esp32h2/src/assist_debug/core_0_sp_max.rs b/esp32h2/src/assist_debug/core_0_sp_max.rs
index 551ad6e6e3..33cb4259d1 100644
--- a/esp32h2/src/assist_debug/core_0_sp_max.rs
+++ b/esp32h2/src/assist_debug/core_0_sp_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_MAX")
-            .field(
-                "core_0_sp_max",
-                &format_args!("{}", self.core_0_sp_max().bits()),
-            )
+            .field("core_0_sp_max", &self.core_0_sp_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - core0 sp pc status register"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/core_0_sp_min.rs b/esp32h2/src/assist_debug/core_0_sp_min.rs
index 385b8a1a99..5ab4adde01 100644
--- a/esp32h2/src/assist_debug/core_0_sp_min.rs
+++ b/esp32h2/src/assist_debug/core_0_sp_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_MIN")
-            .field(
-                "core_0_sp_min",
-                &format_args!("{}", self.core_0_sp_min().bits()),
-            )
+            .field("core_0_sp_min", &self.core_0_sp_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - core0 sp region configuration regsiter"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/core_0_sp_pc.rs b/esp32h2/src/assist_debug/core_0_sp_pc.rs
index edb35da31e..a876b3c942 100644
--- a/esp32h2/src/assist_debug/core_0_sp_pc.rs
+++ b/esp32h2/src/assist_debug/core_0_sp_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_PC")
-            .field(
-                "core_0_sp_pc",
-                &format_args!("{}", self.core_0_sp_pc().bits()),
-            )
+            .field("core_0_sp_pc", &self.core_0_sp_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "stack monitor pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_sp_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_SP_PC_SPEC;
 impl crate::RegisterSpec for CORE_0_SP_PC_SPEC {
diff --git a/esp32h2/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs b/esp32h2/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
index 6fa0b6a1fb..e322997eda 100644
--- a/esp32h2/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
+++ b/esp32h2/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_x_iram0_dram0_limit_cycle_0",
-                &format_args!("{}", self.core_x_iram0_dram0_limit_cycle_0().bits()),
+                &self.core_x_iram0_dram0_limit_cycle_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - reg_core_x_iram0_dram0_limit_cycle_0"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs b/esp32h2/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
index 6c13f7a201..ec7f4d4ef5 100644
--- a/esp32h2/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
+++ b/esp32h2/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_x_iram0_dram0_limit_cycle_1",
-                &format_args!("{}", self.core_x_iram0_dram0_limit_cycle_1().bits()),
+                &self.core_x_iram0_dram0_limit_cycle_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - reg_core_x_iram0_dram0_limit_cycle_1"]
     #[inline(always)]
diff --git a/esp32h2/src/assist_debug/date.rs b/esp32h2/src/assist_debug/date.rs
index 38bb1c07f8..3bd016a008 100644
--- a/esp32h2/src/assist_debug/date.rs
+++ b/esp32h2/src/assist_debug/date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "assist_debug_date",
-                &format_args!("{}", self.assist_debug_date().bits()),
-            )
+            .field("assist_debug_date", &self.assist_debug_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - version register"]
     #[inline(always)]
diff --git a/esp32h2/src/dma/ahb_test.rs b/esp32h2/src/dma/ahb_test.rs
index 28c330c261..8358a35c42 100644
--- a/esp32h2/src/dma/ahb_test.rs
+++ b/esp32h2/src/dma/ahb_test.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_TEST")
-            .field(
-                "ahb_testmode",
-                &format_args!("{}", self.ahb_testmode().bits()),
-            )
-            .field(
-                "ahb_testaddr",
-                &format_args!("{}", self.ahb_testaddr().bits()),
-            )
+            .field("ahb_testmode", &self.ahb_testmode())
+            .field("ahb_testaddr", &self.ahb_testaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_TEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - reserved"]
     #[inline(always)]
diff --git a/esp32h2/src/dma/ch/in_conf0.rs b/esp32h2/src/dma/ch/in_conf0.rs
index 54509ddb71..297d1f81df 100644
--- a/esp32h2/src/dma/ch/in_conf0.rs
+++ b/esp32h2/src/dma/ch/in_conf0.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF0")
-            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
-            .field(
-                "in_loop_test",
-                &format_args!("{}", self.in_loop_test().bit()),
-            )
-            .field(
-                "indscr_burst_en",
-                &format_args!("{}", self.indscr_burst_en().bit()),
-            )
-            .field(
-                "in_data_burst_en",
-                &format_args!("{}", self.in_data_burst_en().bit()),
-            )
-            .field(
-                "mem_trans_en",
-                &format_args!("{}", self.mem_trans_en().bit()),
-            )
-            .field("in_etm_en", &format_args!("{}", self.in_etm_en().bit()))
+            .field("in_rst", &self.in_rst())
+            .field("in_loop_test", &self.in_loop_test())
+            .field("indscr_burst_en", &self.indscr_burst_en())
+            .field("in_data_burst_en", &self.in_data_burst_en())
+            .field("mem_trans_en", &self.mem_trans_en())
+            .field("in_etm_en", &self.in_etm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
     #[inline(always)]
diff --git a/esp32h2/src/dma/ch/in_conf1.rs b/esp32h2/src/dma/ch/in_conf1.rs
index 1da8b38f0b..d95da0040b 100644
--- a/esp32h2/src/dma/ch/in_conf1.rs
+++ b/esp32h2/src/dma/ch/in_conf1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF1")
-            .field(
-                "in_check_owner",
-                &format_args!("{}", self.in_check_owner().bit()),
-            )
+            .field("in_check_owner", &self.in_check_owner())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
diff --git a/esp32h2/src/dma/ch/in_dscr.rs b/esp32h2/src/dma/ch/in_dscr.rs
index 3d348a76f4..e70d15df66 100644
--- a/esp32h2/src/dma/ch/in_dscr.rs
+++ b/esp32h2/src/dma/ch/in_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR")
-            .field(
-                "inlink_dscr",
-                &format_args!("{}", self.inlink_dscr().bits()),
-            )
+            .field("inlink_dscr", &self.inlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_SPEC;
 impl crate::RegisterSpec for IN_DSCR_SPEC {
diff --git a/esp32h2/src/dma/ch/in_dscr_bf0.rs b/esp32h2/src/dma/ch/in_dscr_bf0.rs
index e3023e2221..fca80e02f8 100644
--- a/esp32h2/src/dma/ch/in_dscr_bf0.rs
+++ b/esp32h2/src/dma/ch/in_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF0")
-            .field(
-                "inlink_dscr_bf0",
-                &format_args!("{}", self.inlink_dscr_bf0().bits()),
-            )
+            .field("inlink_dscr_bf0", &self.inlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for IN_DSCR_BF0_SPEC {
diff --git a/esp32h2/src/dma/ch/in_dscr_bf1.rs b/esp32h2/src/dma/ch/in_dscr_bf1.rs
index 457ee1455f..832bf9b92c 100644
--- a/esp32h2/src/dma/ch/in_dscr_bf1.rs
+++ b/esp32h2/src/dma/ch/in_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF1")
-            .field(
-                "inlink_dscr_bf1",
-                &format_args!("{}", self.inlink_dscr_bf1().bits()),
-            )
+            .field("inlink_dscr_bf1", &self.inlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The second-to-last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for IN_DSCR_BF1_SPEC {
diff --git a/esp32h2/src/dma/ch/in_err_eof_des_addr.rs b/esp32h2/src/dma/ch/in_err_eof_des_addr.rs
index 037171f572..63b8c75ca0 100644
--- a/esp32h2/src/dma/ch/in_err_eof_des_addr.rs
+++ b/esp32h2/src/dma/ch/in_err_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_ERR_EOF_DES_ADDR")
-            .field(
-                "in_err_eof_des_addr",
-                &format_args!("{}", self.in_err_eof_des_addr().bits()),
-            )
+            .field("in_err_eof_des_addr", &self.in_err_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_ERR_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Inlink descriptor address when errors occur of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_ERR_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_SPEC {
diff --git a/esp32h2/src/dma/ch/in_link.rs b/esp32h2/src/dma/ch/in_link.rs
index 493e509190..849449a9b6 100644
--- a/esp32h2/src/dma/ch/in_link.rs
+++ b/esp32h2/src/dma/ch/in_link.rs
@@ -39,24 +39,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_LINK")
-            .field(
-                "inlink_addr",
-                &format_args!("{}", self.inlink_addr().bits()),
-            )
-            .field(
-                "inlink_auto_ret",
-                &format_args!("{}", self.inlink_auto_ret().bit()),
-            )
-            .field("inlink_park", &format_args!("{}", self.inlink_park().bit()))
+            .field("inlink_addr", &self.inlink_addr())
+            .field("inlink_auto_ret", &self.inlink_auto_ret())
+            .field("inlink_park", &self.inlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32h2/src/dma/ch/in_peri_sel.rs b/esp32h2/src/dma/ch/in_peri_sel.rs
index 4f7221716d..9a7f9cc573 100644
--- a/esp32h2/src/dma/ch/in_peri_sel.rs
+++ b/esp32h2/src/dma/ch/in_peri_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_PERI_SEL")
-            .field(
-                "peri_in_sel",
-                &format_args!("{}", self.peri_in_sel().bits()),
-            )
+            .field("peri_in_sel", &self.peri_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_PERI_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy"]
     #[inline(always)]
diff --git a/esp32h2/src/dma/ch/in_pop.rs b/esp32h2/src/dma/ch/in_pop.rs
index b9c87113b1..368276237f 100644
--- a/esp32h2/src/dma/ch/in_pop.rs
+++ b/esp32h2/src/dma/ch/in_pop.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_POP")
-            .field(
-                "infifo_rdata",
-                &format_args!("{}", self.infifo_rdata().bits()),
-            )
+            .field("infifo_rdata", &self.infifo_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_POP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."]
     #[inline(always)]
diff --git a/esp32h2/src/dma/ch/in_pri.rs b/esp32h2/src/dma/ch/in_pri.rs
index 83843e1ff5..1d4409ec1b 100644
--- a/esp32h2/src/dma/ch/in_pri.rs
+++ b/esp32h2/src/dma/ch/in_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_PRI")
-            .field("rx_pri", &format_args!("{}", self.rx_pri().bits()))
+            .field("rx_pri", &self.rx_pri())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value the higher of the priority."]
     #[inline(always)]
diff --git a/esp32h2/src/dma/ch/in_state.rs b/esp32h2/src/dma/ch/in_state.rs
index 6c91ac50d7..83cb3124d8 100644
--- a/esp32h2/src/dma/ch/in_state.rs
+++ b/esp32h2/src/dma/ch/in_state.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_STATE")
-            .field(
-                "inlink_dscr_addr",
-                &format_args!("{}", self.inlink_dscr_addr().bits()),
-            )
-            .field(
-                "in_dscr_state",
-                &format_args!("{}", self.in_dscr_state().bits()),
-            )
-            .field("in_state", &format_args!("{}", self.in_state().bits()))
+            .field("inlink_dscr_addr", &self.inlink_dscr_addr())
+            .field("in_dscr_state", &self.in_dscr_state())
+            .field("in_state", &self.in_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_STATE_SPEC;
 impl crate::RegisterSpec for IN_STATE_SPEC {
diff --git a/esp32h2/src/dma/ch/in_suc_eof_des_addr.rs b/esp32h2/src/dma/ch/in_suc_eof_des_addr.rs
index 2b0b4e378a..bd974ca71c 100644
--- a/esp32h2/src/dma/ch/in_suc_eof_des_addr.rs
+++ b/esp32h2/src/dma/ch/in_suc_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_SUC_EOF_DES_ADDR")
-            .field(
-                "in_suc_eof_des_addr",
-                &format_args!("{}", self.in_suc_eof_des_addr().bits()),
-            )
+            .field("in_suc_eof_des_addr", &self.in_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SUC_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Inlink descriptor address when EOF occurs of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SUC_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_SPEC {
diff --git a/esp32h2/src/dma/ch/infifo_status.rs b/esp32h2/src/dma/ch/infifo_status.rs
index 083b1ccdc7..065cf9f3fe 100644
--- a/esp32h2/src/dma/ch/infifo_status.rs
+++ b/esp32h2/src/dma/ch/infifo_status.rs
@@ -62,41 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INFIFO_STATUS")
-            .field("infifo_full", &format_args!("{}", self.infifo_full().bit()))
-            .field(
-                "infifo_empty",
-                &format_args!("{}", self.infifo_empty().bit()),
-            )
-            .field("infifo_cnt", &format_args!("{}", self.infifo_cnt().bits()))
-            .field(
-                "in_remain_under_1b",
-                &format_args!("{}", self.in_remain_under_1b().bit()),
-            )
-            .field(
-                "in_remain_under_2b",
-                &format_args!("{}", self.in_remain_under_2b().bit()),
-            )
-            .field(
-                "in_remain_under_3b",
-                &format_args!("{}", self.in_remain_under_3b().bit()),
-            )
-            .field(
-                "in_remain_under_4b",
-                &format_args!("{}", self.in_remain_under_4b().bit()),
-            )
-            .field(
-                "in_buf_hungry",
-                &format_args!("{}", self.in_buf_hungry().bit()),
-            )
+            .field("infifo_full", &self.infifo_full())
+            .field("infifo_empty", &self.infifo_empty())
+            .field("infifo_cnt", &self.infifo_cnt())
+            .field("in_remain_under_1b", &self.in_remain_under_1b())
+            .field("in_remain_under_2b", &self.in_remain_under_2b())
+            .field("in_remain_under_3b", &self.in_remain_under_3b())
+            .field("in_remain_under_4b", &self.in_remain_under_4b())
+            .field("in_buf_hungry", &self.in_buf_hungry())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive FIFO status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for INFIFO_STATUS_SPEC {
diff --git a/esp32h2/src/dma/ch/out_conf0.rs b/esp32h2/src/dma/ch/out_conf0.rs
index d92b9bfec5..14a2911000 100644
--- a/esp32h2/src/dma/ch/out_conf0.rs
+++ b/esp32h2/src/dma/ch/out_conf0.rs
@@ -71,37 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CONF0")
-            .field("out_rst", &format_args!("{}", self.out_rst().bit()))
-            .field(
-                "out_loop_test",
-                &format_args!("{}", self.out_loop_test().bit()),
-            )
-            .field(
-                "out_auto_wrback",
-                &format_args!("{}", self.out_auto_wrback().bit()),
-            )
-            .field(
-                "out_eof_mode",
-                &format_args!("{}", self.out_eof_mode().bit()),
-            )
-            .field(
-                "outdscr_burst_en",
-                &format_args!("{}", self.outdscr_burst_en().bit()),
-            )
-            .field(
-                "out_data_burst_en",
-                &format_args!("{}", self.out_data_burst_en().bit()),
-            )
-            .field("out_etm_en", &format_args!("{}", self.out_etm_en().bit()))
+            .field("out_rst", &self.out_rst())
+            .field("out_loop_test", &self.out_loop_test())
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("out_eof_mode", &self.out_eof_mode())
+            .field("outdscr_burst_en", &self.outdscr_burst_en())
+            .field("out_data_burst_en", &self.out_data_burst_en())
+            .field("out_etm_en", &self.out_etm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer."]
     #[inline(always)]
diff --git a/esp32h2/src/dma/ch/out_conf1.rs b/esp32h2/src/dma/ch/out_conf1.rs
index 8d9753a4b9..0ed936f2fa 100644
--- a/esp32h2/src/dma/ch/out_conf1.rs
+++ b/esp32h2/src/dma/ch/out_conf1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CONF1")
-            .field(
-                "out_check_owner",
-                &format_args!("{}", self.out_check_owner().bit()),
-            )
+            .field("out_check_owner", &self.out_check_owner())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
diff --git a/esp32h2/src/dma/ch/out_dscr.rs b/esp32h2/src/dma/ch/out_dscr.rs
index bfbfd6cd82..e64e982337 100644
--- a/esp32h2/src/dma/ch/out_dscr.rs
+++ b/esp32h2/src/dma/ch/out_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR")
-            .field(
-                "outlink_dscr",
-                &format_args!("{}", self.outlink_dscr().bits()),
-            )
+            .field("outlink_dscr", &self.outlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_SPEC {
diff --git a/esp32h2/src/dma/ch/out_dscr_bf0.rs b/esp32h2/src/dma/ch/out_dscr_bf0.rs
index 95ef8f687e..f5fec0ba50 100644
--- a/esp32h2/src/dma/ch/out_dscr_bf0.rs
+++ b/esp32h2/src/dma/ch/out_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR_BF0")
-            .field(
-                "outlink_dscr_bf0",
-                &format_args!("{}", self.outlink_dscr_bf0().bits()),
-            )
+            .field("outlink_dscr_bf0", &self.outlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_BF0_SPEC {
diff --git a/esp32h2/src/dma/ch/out_dscr_bf1.rs b/esp32h2/src/dma/ch/out_dscr_bf1.rs
index f75439c16c..4339b9c9b9 100644
--- a/esp32h2/src/dma/ch/out_dscr_bf1.rs
+++ b/esp32h2/src/dma/ch/out_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR_BF1")
-            .field(
-                "outlink_dscr_bf1",
-                &format_args!("{}", self.outlink_dscr_bf1().bits()),
-            )
+            .field("outlink_dscr_bf1", &self.outlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The second-to-last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_BF1_SPEC {
diff --git a/esp32h2/src/dma/ch/out_eof_bfr_des_addr.rs b/esp32h2/src/dma/ch/out_eof_bfr_des_addr.rs
index 32fea6abcc..08cac753ad 100644
--- a/esp32h2/src/dma/ch/out_eof_bfr_des_addr.rs
+++ b/esp32h2/src/dma/ch/out_eof_bfr_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_BFR_DES_ADDR")
-            .field(
-                "out_eof_bfr_des_addr",
-                &format_args!("{}", self.out_eof_bfr_des_addr().bits()),
-            )
+            .field("out_eof_bfr_des_addr", &self.out_eof_bfr_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_BFR_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The last outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_bfr_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_BFR_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_SPEC {
diff --git a/esp32h2/src/dma/ch/out_eof_des_addr.rs b/esp32h2/src/dma/ch/out_eof_des_addr.rs
index b85ba2ebbd..1049f7aa97 100644
--- a/esp32h2/src/dma/ch/out_eof_des_addr.rs
+++ b/esp32h2/src/dma/ch/out_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_DES_ADDR")
-            .field(
-                "out_eof_des_addr",
-                &format_args!("{}", self.out_eof_des_addr().bits()),
-            )
+            .field("out_eof_des_addr", &self.out_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_DES_ADDR_SPEC {
diff --git a/esp32h2/src/dma/ch/out_link.rs b/esp32h2/src/dma/ch/out_link.rs
index 5ecdbc1ff7..f05d845e6e 100644
--- a/esp32h2/src/dma/ch/out_link.rs
+++ b/esp32h2/src/dma/ch/out_link.rs
@@ -30,23 +30,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_LINK")
-            .field(
-                "outlink_addr",
-                &format_args!("{}", self.outlink_addr().bits()),
-            )
-            .field(
-                "outlink_park",
-                &format_args!("{}", self.outlink_park().bit()),
-            )
+            .field("outlink_addr", &self.outlink_addr())
+            .field("outlink_park", &self.outlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32h2/src/dma/ch/out_peri_sel.rs b/esp32h2/src/dma/ch/out_peri_sel.rs
index 23a7e68422..c7559b2d85 100644
--- a/esp32h2/src/dma/ch/out_peri_sel.rs
+++ b/esp32h2/src/dma/ch/out_peri_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PERI_SEL")
-            .field(
-                "peri_out_sel",
-                &format_args!("{}", self.peri_out_sel().bits()),
-            )
+            .field("peri_out_sel", &self.peri_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PERI_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy"]
     #[inline(always)]
diff --git a/esp32h2/src/dma/ch/out_pri.rs b/esp32h2/src/dma/ch/out_pri.rs
index 7ea88ef349..5397e69678 100644
--- a/esp32h2/src/dma/ch/out_pri.rs
+++ b/esp32h2/src/dma/ch/out_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PRI")
-            .field("tx_pri", &format_args!("{}", self.tx_pri().bits()))
+            .field("tx_pri", &self.tx_pri())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value the higher of the priority."]
     #[inline(always)]
diff --git a/esp32h2/src/dma/ch/out_push.rs b/esp32h2/src/dma/ch/out_push.rs
index 80dba16ac8..bb1e623d52 100644
--- a/esp32h2/src/dma/ch/out_push.rs
+++ b/esp32h2/src/dma/ch/out_push.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PUSH")
-            .field(
-                "outfifo_wdata",
-                &format_args!("{}", self.outfifo_wdata().bits()),
-            )
+            .field("outfifo_wdata", &self.outfifo_wdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PUSH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."]
     #[inline(always)]
diff --git a/esp32h2/src/dma/ch/out_state.rs b/esp32h2/src/dma/ch/out_state.rs
index 32eb3ca4e8..9711790741 100644
--- a/esp32h2/src/dma/ch/out_state.rs
+++ b/esp32h2/src/dma/ch/out_state.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_STATE")
-            .field(
-                "outlink_dscr_addr",
-                &format_args!("{}", self.outlink_dscr_addr().bits()),
-            )
-            .field(
-                "out_dscr_state",
-                &format_args!("{}", self.out_dscr_state().bits()),
-            )
-            .field("out_state", &format_args!("{}", self.out_state().bits()))
+            .field("outlink_dscr_addr", &self.outlink_dscr_addr())
+            .field("out_dscr_state", &self.out_dscr_state())
+            .field("out_state", &self.out_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transmit status of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_STATE_SPEC;
 impl crate::RegisterSpec for OUT_STATE_SPEC {
diff --git a/esp32h2/src/dma/ch/outfifo_status.rs b/esp32h2/src/dma/ch/outfifo_status.rs
index 7bdea07321..dc478ff060 100644
--- a/esp32h2/src/dma/ch/outfifo_status.rs
+++ b/esp32h2/src/dma/ch/outfifo_status.rs
@@ -55,43 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTFIFO_STATUS")
-            .field(
-                "outfifo_full",
-                &format_args!("{}", self.outfifo_full().bit()),
-            )
-            .field(
-                "outfifo_empty",
-                &format_args!("{}", self.outfifo_empty().bit()),
-            )
-            .field(
-                "outfifo_cnt",
-                &format_args!("{}", self.outfifo_cnt().bits()),
-            )
-            .field(
-                "out_remain_under_1b",
-                &format_args!("{}", self.out_remain_under_1b().bit()),
-            )
-            .field(
-                "out_remain_under_2b",
-                &format_args!("{}", self.out_remain_under_2b().bit()),
-            )
-            .field(
-                "out_remain_under_3b",
-                &format_args!("{}", self.out_remain_under_3b().bit()),
-            )
-            .field(
-                "out_remain_under_4b",
-                &format_args!("{}", self.out_remain_under_4b().bit()),
-            )
+            .field("outfifo_full", &self.outfifo_full())
+            .field("outfifo_empty", &self.outfifo_empty())
+            .field("outfifo_cnt", &self.outfifo_cnt())
+            .field("out_remain_under_1b", &self.out_remain_under_1b())
+            .field("out_remain_under_2b", &self.out_remain_under_2b())
+            .field("out_remain_under_3b", &self.out_remain_under_3b())
+            .field("out_remain_under_4b", &self.out_remain_under_4b())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transmit FIFO status of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for OUTFIFO_STATUS_SPEC {
diff --git a/esp32h2/src/dma/date.rs b/esp32h2/src/dma/date.rs
index 0d83c02a03..9bc6685c81 100644
--- a/esp32h2/src/dma/date.rs
+++ b/esp32h2/src/dma/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/dma/in_int_ch/ena.rs b/esp32h2/src/dma/in_int_ch/ena.rs
index f845f9df75..5dcfe467fd 100644
--- a/esp32h2/src/dma/in_int_ch/ena.rs
+++ b/esp32h2/src/dma/in_int_ch/ena.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENA")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32h2/src/dma/in_int_ch/raw.rs b/esp32h2/src/dma/in_int_ch/raw.rs
index cbf64a2647..6891a0e659 100644
--- a/esp32h2/src/dma/in_int_ch/raw.rs
+++ b/esp32h2/src/dma/in_int_ch/raw.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RAW")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
     #[inline(always)]
diff --git a/esp32h2/src/dma/in_int_ch/st.rs b/esp32h2/src/dma/in_int_ch/st.rs
index a3bc9f8f8f..0a0bf35524 100644
--- a/esp32h2/src/dma/in_int_ch/st.rs
+++ b/esp32h2/src/dma/in_int_ch/st.rs
@@ -55,25 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ST")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ST_SPEC;
 impl crate::RegisterSpec for ST_SPEC {
diff --git a/esp32h2/src/dma/misc_conf.rs b/esp32h2/src/dma/misc_conf.rs
index 60bc8667fa..7b16c52f7a 100644
--- a/esp32h2/src/dma/misc_conf.rs
+++ b/esp32h2/src/dma/misc_conf.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC_CONF")
-            .field(
-                "ahbm_rst_inter",
-                &format_args!("{}", self.ahbm_rst_inter().bit()),
-            )
-            .field("arb_pri_dis", &format_args!("{}", self.arb_pri_dis().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("ahbm_rst_inter", &self.ahbm_rst_inter())
+            .field("arb_pri_dis", &self.arb_pri_dis())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit then clear this bit to reset the internal ahb FSM."]
     #[inline(always)]
diff --git a/esp32h2/src/dma/out_int_ch/ena.rs b/esp32h2/src/dma/out_int_ch/ena.rs
index 9403656d3a..01a68f37f2 100644
--- a/esp32h2/src/dma/out_int_ch/ena.rs
+++ b/esp32h2/src/dma/out_int_ch/ena.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENA")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32h2/src/dma/out_int_ch/raw.rs b/esp32h2/src/dma/out_int_ch/raw.rs
index bfd53406bd..f5979fc55a 100644
--- a/esp32h2/src/dma/out_int_ch/raw.rs
+++ b/esp32h2/src/dma/out_int_ch/raw.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RAW")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
     #[inline(always)]
diff --git a/esp32h2/src/dma/out_int_ch/st.rs b/esp32h2/src/dma/out_int_ch/st.rs
index a10e575b53..fff916b01d 100644
--- a/esp32h2/src/dma/out_int_ch/st.rs
+++ b/esp32h2/src/dma/out_int_ch/st.rs
@@ -48,27 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ST")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ST_SPEC;
 impl crate::RegisterSpec for ST_SPEC {
diff --git a/esp32h2/src/ds/box_mem.rs b/esp32h2/src/ds/box_mem.rs
index cbc5e04146..af6085c630 100644
--- a/esp32h2/src/ds/box_mem.rs
+++ b/esp32h2/src/ds/box_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BOX_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores BOX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`box_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`box_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BOX_MEM_SPEC;
diff --git a/esp32h2/src/ds/date.rs b/esp32h2/src/ds/date.rs
index 0b73492be1..97e7b03565 100644
--- a/esp32h2/src/ds/date.rs
+++ b/esp32h2/src/ds/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/ds/iv_mem.rs b/esp32h2/src/ds/iv_mem.rs
index 3f93dc26b7..5bef1d4a62 100644
--- a/esp32h2/src/ds/iv_mem.rs
+++ b/esp32h2/src/ds/iv_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IV_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores IV\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iv_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iv_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IV_MEM_SPEC;
diff --git a/esp32h2/src/ds/m_mem.rs b/esp32h2/src/ds/m_mem.rs
index feb455544d..34f49f49a5 100644
--- a/esp32h2/src/ds/m_mem.rs
+++ b/esp32h2/src/ds/m_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct M_MEM_SPEC;
diff --git a/esp32h2/src/ds/query_busy.rs b/esp32h2/src/ds/query_busy.rs
index 28c895caf6..ab7489a518 100644
--- a/esp32h2/src/ds/query_busy.rs
+++ b/esp32h2/src/ds/query_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_BUSY")
-            .field("query_busy", &format_args!("{}", self.query_busy().bit()))
+            .field("query_busy", &self.query_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DS query busy register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_BUSY_SPEC;
 impl crate::RegisterSpec for QUERY_BUSY_SPEC {
diff --git a/esp32h2/src/ds/query_check.rs b/esp32h2/src/ds/query_check.rs
index 278370e20f..e1d1c02fe7 100644
--- a/esp32h2/src/ds/query_check.rs
+++ b/esp32h2/src/ds/query_check.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_CHECK")
-            .field("md_error", &format_args!("{}", self.md_error().bit()))
-            .field("padding_bad", &format_args!("{}", self.padding_bad().bit()))
+            .field("md_error", &self.md_error())
+            .field("padding_bad", &self.padding_bad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_CHECK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DS query check result register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_check::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_CHECK_SPEC;
 impl crate::RegisterSpec for QUERY_CHECK_SPEC {
diff --git a/esp32h2/src/ds/query_key_wrong.rs b/esp32h2/src/ds/query_key_wrong.rs
index 30a1e7aae4..7ce4bf99a0 100644
--- a/esp32h2/src/ds/query_key_wrong.rs
+++ b/esp32h2/src/ds/query_key_wrong.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_KEY_WRONG")
-            .field(
-                "query_key_wrong",
-                &format_args!("{}", self.query_key_wrong().bits()),
-            )
+            .field("query_key_wrong", &self.query_key_wrong())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_KEY_WRONG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DS query key-wrong counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_key_wrong::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_KEY_WRONG_SPEC;
 impl crate::RegisterSpec for QUERY_KEY_WRONG_SPEC {
diff --git a/esp32h2/src/ds/rb_mem.rs b/esp32h2/src/ds/rb_mem.rs
index 601da234a3..c7e0a211be 100644
--- a/esp32h2/src/ds/rb_mem.rs
+++ b/esp32h2/src/ds/rb_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RB_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores Rb\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rb_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rb_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RB_MEM_SPEC;
diff --git a/esp32h2/src/ds/x_mem.rs b/esp32h2/src/ds/x_mem.rs
index b018ad10ba..5cfb1f6eb6 100644
--- a/esp32h2/src/ds/x_mem.rs
+++ b/esp32h2/src/ds/x_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<X_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores X\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`x_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`x_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct X_MEM_SPEC;
diff --git a/esp32h2/src/ds/y_mem.rs b/esp32h2/src/ds/y_mem.rs
index 00ad225968..3376d35f4e 100644
--- a/esp32h2/src/ds/y_mem.rs
+++ b/esp32h2/src/ds/y_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Y_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores Y\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Y_MEM_SPEC;
diff --git a/esp32h2/src/ds/z_mem.rs b/esp32h2/src/ds/z_mem.rs
index de03c7e5de..978b2c0d66 100644
--- a/esp32h2/src/ds/z_mem.rs
+++ b/esp32h2/src/ds/z_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Z_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Z_MEM_SPEC;
diff --git a/esp32h2/src/ecc/k_mem.rs b/esp32h2/src/ecc/k_mem.rs
index 0931b81173..8e55d12095 100644
--- a/esp32h2/src/ecc/k_mem.rs
+++ b/esp32h2/src/ecc/k_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<K_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores k.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`k_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`k_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct K_MEM_SPEC;
diff --git a/esp32h2/src/ecc/mult_conf.rs b/esp32h2/src/ecc/mult_conf.rs
index b1868723e2..1095f08720 100644
--- a/esp32h2/src/ecc/mult_conf.rs
+++ b/esp32h2/src/ecc/mult_conf.rs
@@ -80,32 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_CONF")
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("key_length", &format_args!("{}", self.key_length().bit()))
-            .field("mod_base", &format_args!("{}", self.mod_base().bit()))
-            .field("work_mode", &format_args!("{}", self.work_mode().bits()))
-            .field(
-                "security_mode",
-                &format_args!("{}", self.security_mode().bit()),
-            )
-            .field(
-                "verification_result",
-                &format_args!("{}", self.verification_result().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "mem_clock_gate_force_on",
-                &format_args!("{}", self.mem_clock_gate_force_on().bit()),
-            )
+            .field("start", &self.start())
+            .field("key_length", &self.key_length())
+            .field("mod_base", &self.mod_base())
+            .field("work_mode", &self.work_mode())
+            .field("security_mode", &self.security_mode())
+            .field("verification_result", &self.verification_result())
+            .field("clk_en", &self.clk_en())
+            .field("mem_clock_gate_force_on", &self.mem_clock_gate_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done."]
     #[inline(always)]
diff --git a/esp32h2/src/ecc/mult_date.rs b/esp32h2/src/ecc/mult_date.rs
index ac94da5d1a..136b35429c 100644
--- a/esp32h2/src/ecc/mult_date.rs
+++ b/esp32h2/src/ecc/mult_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - ECC mult version control register"]
     #[inline(always)]
diff --git a/esp32h2/src/ecc/mult_int_ena.rs b/esp32h2/src/ecc/mult_int_ena.rs
index 0a756a4618..e98f881175 100644
--- a/esp32h2/src/ecc/mult_int_ena.rs
+++ b/esp32h2/src/ecc/mult_int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_INT_ENA")
-            .field("calc_done", &format_args!("{}", self.calc_done().bit()))
+            .field("calc_done", &self.calc_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the ecc_calc_done_int interrupt"]
     #[inline(always)]
diff --git a/esp32h2/src/ecc/mult_int_raw.rs b/esp32h2/src/ecc/mult_int_raw.rs
index ad5e442a59..0a76f6a144 100644
--- a/esp32h2/src/ecc/mult_int_raw.rs
+++ b/esp32h2/src/ecc/mult_int_raw.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_INT_RAW")
-            .field("calc_done", &format_args!("{}", self.calc_done().bit()))
+            .field("calc_done", &self.calc_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ECC interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MULT_INT_RAW_SPEC;
 impl crate::RegisterSpec for MULT_INT_RAW_SPEC {
diff --git a/esp32h2/src/ecc/mult_int_st.rs b/esp32h2/src/ecc/mult_int_st.rs
index 9fa4c84f14..599cde021a 100644
--- a/esp32h2/src/ecc/mult_int_st.rs
+++ b/esp32h2/src/ecc/mult_int_st.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_INT_ST")
-            .field("calc_done", &format_args!("{}", self.calc_done().bit()))
+            .field("calc_done", &self.calc_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ECC interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MULT_INT_ST_SPEC;
 impl crate::RegisterSpec for MULT_INT_ST_SPEC {
diff --git a/esp32h2/src/ecc/px_mem.rs b/esp32h2/src/ecc/px_mem.rs
index 3a8e843f61..3a24d84d16 100644
--- a/esp32h2/src/ecc/px_mem.rs
+++ b/esp32h2/src/ecc/px_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PX_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores Px.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`px_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`px_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PX_MEM_SPEC;
diff --git a/esp32h2/src/ecc/py_mem.rs b/esp32h2/src/ecc/py_mem.rs
index 8129141315..e5d383ac34 100644
--- a/esp32h2/src/ecc/py_mem.rs
+++ b/esp32h2/src/ecc/py_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PY_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores Py.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`py_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`py_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PY_MEM_SPEC;
diff --git a/esp32h2/src/ecc/qx_mem.rs b/esp32h2/src/ecc/qx_mem.rs
index eed7133f6a..0a62e8b48f 100644
--- a/esp32h2/src/ecc/qx_mem.rs
+++ b/esp32h2/src/ecc/qx_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QX_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores Qx\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`qx_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`qx_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QX_MEM_SPEC;
diff --git a/esp32h2/src/ecc/qy_mem.rs b/esp32h2/src/ecc/qy_mem.rs
index 7d8929ece9..dd8c58abdc 100644
--- a/esp32h2/src/ecc/qy_mem.rs
+++ b/esp32h2/src/ecc/qy_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QY_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores Qy\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`qy_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`qy_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QY_MEM_SPEC;
diff --git a/esp32h2/src/ecc/qz_mem.rs b/esp32h2/src/ecc/qz_mem.rs
index adb25cf2b5..035f8b7dd7 100644
--- a/esp32h2/src/ecc/qz_mem.rs
+++ b/esp32h2/src/ecc/qz_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QZ_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores Qz\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`qz_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`qz_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QZ_MEM_SPEC;
diff --git a/esp32h2/src/efuse/clk.rs b/esp32h2/src/efuse/clk.rs
index 94aeed7312..b6041ccf31 100644
--- a/esp32h2/src/efuse/clk.rs
+++ b/esp32h2/src/efuse/clk.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK")
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_clk_force_on",
-                &format_args!("{}", self.mem_clk_force_on().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_clk_force_on", &self.mem_clk_force_on())
+            .field("mem_force_pu", &self.mem_force_pu())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to force eFuse SRAM into power-saving mode."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/cmd.rs b/esp32h2/src/efuse/cmd.rs
index 8dee79bc65..094d443be3 100644
--- a/esp32h2/src/efuse/cmd.rs
+++ b/esp32h2/src/efuse/cmd.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("read_cmd", &format_args!("{}", self.read_cmd().bit()))
-            .field("pgm_cmd", &format_args!("{}", self.pgm_cmd().bit()))
-            .field("blk_num", &format_args!("{}", self.blk_num().bits()))
+            .field("read_cmd", &self.read_cmd())
+            .field("pgm_cmd", &self.pgm_cmd())
+            .field("blk_num", &self.blk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to send read command."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/conf.rs b/esp32h2/src/efuse/conf.rs
index 65fd73616a..7236cc41ce 100644
--- a/esp32h2/src/efuse/conf.rs
+++ b/esp32h2/src/efuse/conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("op_code", &format_args!("{}", self.op_code().bits()))
-            .field(
-                "cfg_ecdsa_blk",
-                &format_args!("{}", self.cfg_ecdsa_blk().bits()),
-            )
+            .field("op_code", &self.op_code())
+            .field("cfg_ecdsa_blk", &self.cfg_ecdsa_blk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - 0x5A5A: programming operation command 0x5AA5: read operation command."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/dac_conf.rs b/esp32h2/src/efuse/dac_conf.rs
index 857103d692..815994bb58 100644
--- a/esp32h2/src/efuse/dac_conf.rs
+++ b/esp32h2/src/efuse/dac_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DAC_CONF")
-            .field(
-                "dac_clk_div",
-                &format_args!("{}", self.dac_clk_div().bits()),
-            )
-            .field(
-                "dac_clk_pad_sel",
-                &format_args!("{}", self.dac_clk_pad_sel().bit()),
-            )
-            .field("dac_num", &format_args!("{}", self.dac_num().bits()))
-            .field("oe_clr", &format_args!("{}", self.oe_clr().bit()))
+            .field("dac_clk_div", &self.dac_clk_div())
+            .field("dac_clk_pad_sel", &self.dac_clk_pad_sel())
+            .field("dac_num", &self.dac_num())
+            .field("oe_clr", &self.oe_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DAC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Controls the division factor of the rising clock of the programming voltage."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/date.rs b/esp32h2/src/efuse/date.rs
index 599ddff747..3db6a71604 100644
--- a/esp32h2/src/efuse/date.rs
+++ b/esp32h2/src/efuse/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/efuse/int_ena.rs b/esp32h2/src/efuse/int_ena.rs
index 6386df2821..0020c7e668 100644
--- a/esp32h2/src/efuse/int_ena.rs
+++ b/esp32h2/src/efuse/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable signal for read_done interrupt."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/int_raw.rs b/esp32h2/src/efuse/int_raw.rs
index b69c288afb..efd8b89205 100644
--- a/esp32h2/src/efuse/int_raw.rs
+++ b/esp32h2/src/efuse/int_raw.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse raw interrupt register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32h2/src/efuse/int_st.rs b/esp32h2/src/efuse/int_st.rs
index 898ceb8e8b..efba508ff2 100644
--- a/esp32h2/src/efuse/int_st.rs
+++ b/esp32h2/src/efuse/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/efuse/pgm_check_value0.rs b/esp32h2/src/efuse/pgm_check_value0.rs
index 663f1a6b52..ab1a0f0553 100644
--- a/esp32h2/src/efuse/pgm_check_value0.rs
+++ b/esp32h2/src/efuse/pgm_check_value0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE0")
-            .field(
-                "pgm_rs_data_0",
-                &format_args!("{}", self.pgm_rs_data_0().bits()),
-            )
+            .field("pgm_rs_data_0", &self.pgm_rs_data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 0th 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/pgm_check_value1.rs b/esp32h2/src/efuse/pgm_check_value1.rs
index d7333c0b68..2190b87db3 100644
--- a/esp32h2/src/efuse/pgm_check_value1.rs
+++ b/esp32h2/src/efuse/pgm_check_value1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE1")
-            .field(
-                "pgm_rs_data_1",
-                &format_args!("{}", self.pgm_rs_data_1().bits()),
-            )
+            .field("pgm_rs_data_1", &self.pgm_rs_data_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 1st 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/pgm_check_value2.rs b/esp32h2/src/efuse/pgm_check_value2.rs
index ea8f275832..9f176182aa 100644
--- a/esp32h2/src/efuse/pgm_check_value2.rs
+++ b/esp32h2/src/efuse/pgm_check_value2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE2")
-            .field(
-                "pgm_rs_data_2",
-                &format_args!("{}", self.pgm_rs_data_2().bits()),
-            )
+            .field("pgm_rs_data_2", &self.pgm_rs_data_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 2nd 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/pgm_data0.rs b/esp32h2/src/efuse/pgm_data0.rs
index 99d1a39f3d..2fa0081de0 100644
--- a/esp32h2/src/efuse/pgm_data0.rs
+++ b/esp32h2/src/efuse/pgm_data0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA0")
-            .field("pgm_data_0", &format_args!("{}", self.pgm_data_0().bits()))
+            .field("pgm_data_0", &self.pgm_data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 0th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/pgm_data1.rs b/esp32h2/src/efuse/pgm_data1.rs
index dd5c818232..1fcd9bb4ec 100644
--- a/esp32h2/src/efuse/pgm_data1.rs
+++ b/esp32h2/src/efuse/pgm_data1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA1")
-            .field("pgm_data_1", &format_args!("{}", self.pgm_data_1().bits()))
+            .field("pgm_data_1", &self.pgm_data_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 1st 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/pgm_data2.rs b/esp32h2/src/efuse/pgm_data2.rs
index 9297097580..07fc1fa3b9 100644
--- a/esp32h2/src/efuse/pgm_data2.rs
+++ b/esp32h2/src/efuse/pgm_data2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA2")
-            .field("pgm_data_2", &format_args!("{}", self.pgm_data_2().bits()))
+            .field("pgm_data_2", &self.pgm_data_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 2nd 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/pgm_data3.rs b/esp32h2/src/efuse/pgm_data3.rs
index beb3114ecf..bf3f5ccec2 100644
--- a/esp32h2/src/efuse/pgm_data3.rs
+++ b/esp32h2/src/efuse/pgm_data3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA3")
-            .field("pgm_data_3", &format_args!("{}", self.pgm_data_3().bits()))
+            .field("pgm_data_3", &self.pgm_data_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 3rd 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/pgm_data4.rs b/esp32h2/src/efuse/pgm_data4.rs
index ab568669b6..8aea0c46cb 100644
--- a/esp32h2/src/efuse/pgm_data4.rs
+++ b/esp32h2/src/efuse/pgm_data4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA4")
-            .field("pgm_data_4", &format_args!("{}", self.pgm_data_4().bits()))
+            .field("pgm_data_4", &self.pgm_data_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 4th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/pgm_data5.rs b/esp32h2/src/efuse/pgm_data5.rs
index a563072d44..c09c8a828a 100644
--- a/esp32h2/src/efuse/pgm_data5.rs
+++ b/esp32h2/src/efuse/pgm_data5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA5")
-            .field("pgm_data_5", &format_args!("{}", self.pgm_data_5().bits()))
+            .field("pgm_data_5", &self.pgm_data_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 5th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/pgm_data6.rs b/esp32h2/src/efuse/pgm_data6.rs
index 3068ec971d..1c9e0c9011 100644
--- a/esp32h2/src/efuse/pgm_data6.rs
+++ b/esp32h2/src/efuse/pgm_data6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA6")
-            .field("pgm_data_6", &format_args!("{}", self.pgm_data_6().bits()))
+            .field("pgm_data_6", &self.pgm_data_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 6th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/pgm_data7.rs b/esp32h2/src/efuse/pgm_data7.rs
index 0087318233..b913c59fad 100644
--- a/esp32h2/src/efuse/pgm_data7.rs
+++ b/esp32h2/src/efuse/pgm_data7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA7")
-            .field("pgm_data_7", &format_args!("{}", self.pgm_data_7().bits()))
+            .field("pgm_data_7", &self.pgm_data_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 7th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/rd_key0_data0.rs b/esp32h2/src/efuse/rd_key0_data0.rs
index b4ee49df3a..66bdc7a995 100644
--- a/esp32h2/src/efuse/rd_key0_data0.rs
+++ b/esp32h2/src/efuse/rd_key0_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA0")
-            .field("key0_data0", &format_args!("{}", self.key0_data0().bits()))
+            .field("key0_data0", &self.key0_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA0_SPEC {
diff --git a/esp32h2/src/efuse/rd_key0_data1.rs b/esp32h2/src/efuse/rd_key0_data1.rs
index 1f8251375b..5efa9fd856 100644
--- a/esp32h2/src/efuse/rd_key0_data1.rs
+++ b/esp32h2/src/efuse/rd_key0_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA1")
-            .field("key0_data1", &format_args!("{}", self.key0_data1().bits()))
+            .field("key0_data1", &self.key0_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA1_SPEC {
diff --git a/esp32h2/src/efuse/rd_key0_data2.rs b/esp32h2/src/efuse/rd_key0_data2.rs
index be8f375983..4a38cbfd42 100644
--- a/esp32h2/src/efuse/rd_key0_data2.rs
+++ b/esp32h2/src/efuse/rd_key0_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA2")
-            .field("key0_data2", &format_args!("{}", self.key0_data2().bits()))
+            .field("key0_data2", &self.key0_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA2_SPEC {
diff --git a/esp32h2/src/efuse/rd_key0_data3.rs b/esp32h2/src/efuse/rd_key0_data3.rs
index 6d2222cda9..736e197bb4 100644
--- a/esp32h2/src/efuse/rd_key0_data3.rs
+++ b/esp32h2/src/efuse/rd_key0_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA3")
-            .field("key0_data3", &format_args!("{}", self.key0_data3().bits()))
+            .field("key0_data3", &self.key0_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA3_SPEC {
diff --git a/esp32h2/src/efuse/rd_key0_data4.rs b/esp32h2/src/efuse/rd_key0_data4.rs
index 5c5d3846a2..f57c6246c0 100644
--- a/esp32h2/src/efuse/rd_key0_data4.rs
+++ b/esp32h2/src/efuse/rd_key0_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA4")
-            .field("key0_data4", &format_args!("{}", self.key0_data4().bits()))
+            .field("key0_data4", &self.key0_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA4_SPEC {
diff --git a/esp32h2/src/efuse/rd_key0_data5.rs b/esp32h2/src/efuse/rd_key0_data5.rs
index e675b726d9..fc6203feb8 100644
--- a/esp32h2/src/efuse/rd_key0_data5.rs
+++ b/esp32h2/src/efuse/rd_key0_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA5")
-            .field("key0_data5", &format_args!("{}", self.key0_data5().bits()))
+            .field("key0_data5", &self.key0_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA5_SPEC {
diff --git a/esp32h2/src/efuse/rd_key0_data6.rs b/esp32h2/src/efuse/rd_key0_data6.rs
index 506e4a1a76..021d664b62 100644
--- a/esp32h2/src/efuse/rd_key0_data6.rs
+++ b/esp32h2/src/efuse/rd_key0_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA6")
-            .field("key0_data6", &format_args!("{}", self.key0_data6().bits()))
+            .field("key0_data6", &self.key0_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA6_SPEC {
diff --git a/esp32h2/src/efuse/rd_key0_data7.rs b/esp32h2/src/efuse/rd_key0_data7.rs
index 97d737135d..a6442fdf78 100644
--- a/esp32h2/src/efuse/rd_key0_data7.rs
+++ b/esp32h2/src/efuse/rd_key0_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA7")
-            .field("key0_data7", &format_args!("{}", self.key0_data7().bits()))
+            .field("key0_data7", &self.key0_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA7_SPEC {
diff --git a/esp32h2/src/efuse/rd_key1_data0.rs b/esp32h2/src/efuse/rd_key1_data0.rs
index c70f6acd7f..6b2431620c 100644
--- a/esp32h2/src/efuse/rd_key1_data0.rs
+++ b/esp32h2/src/efuse/rd_key1_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA0")
-            .field("key1_data0", &format_args!("{}", self.key1_data0().bits()))
+            .field("key1_data0", &self.key1_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA0_SPEC {
diff --git a/esp32h2/src/efuse/rd_key1_data1.rs b/esp32h2/src/efuse/rd_key1_data1.rs
index aae8bcee9a..f231c8b98a 100644
--- a/esp32h2/src/efuse/rd_key1_data1.rs
+++ b/esp32h2/src/efuse/rd_key1_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA1")
-            .field("key1_data1", &format_args!("{}", self.key1_data1().bits()))
+            .field("key1_data1", &self.key1_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA1_SPEC {
diff --git a/esp32h2/src/efuse/rd_key1_data2.rs b/esp32h2/src/efuse/rd_key1_data2.rs
index 1966a996a6..4ededdea0a 100644
--- a/esp32h2/src/efuse/rd_key1_data2.rs
+++ b/esp32h2/src/efuse/rd_key1_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA2")
-            .field("key1_data2", &format_args!("{}", self.key1_data2().bits()))
+            .field("key1_data2", &self.key1_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA2_SPEC {
diff --git a/esp32h2/src/efuse/rd_key1_data3.rs b/esp32h2/src/efuse/rd_key1_data3.rs
index fdd40460e9..d20732a98a 100644
--- a/esp32h2/src/efuse/rd_key1_data3.rs
+++ b/esp32h2/src/efuse/rd_key1_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA3")
-            .field("key1_data3", &format_args!("{}", self.key1_data3().bits()))
+            .field("key1_data3", &self.key1_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA3_SPEC {
diff --git a/esp32h2/src/efuse/rd_key1_data4.rs b/esp32h2/src/efuse/rd_key1_data4.rs
index c786647016..d9e7d57ad6 100644
--- a/esp32h2/src/efuse/rd_key1_data4.rs
+++ b/esp32h2/src/efuse/rd_key1_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA4")
-            .field("key1_data4", &format_args!("{}", self.key1_data4().bits()))
+            .field("key1_data4", &self.key1_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA4_SPEC {
diff --git a/esp32h2/src/efuse/rd_key1_data5.rs b/esp32h2/src/efuse/rd_key1_data5.rs
index 0ea5b95d9f..9def03fecb 100644
--- a/esp32h2/src/efuse/rd_key1_data5.rs
+++ b/esp32h2/src/efuse/rd_key1_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA5")
-            .field("key1_data5", &format_args!("{}", self.key1_data5().bits()))
+            .field("key1_data5", &self.key1_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA5_SPEC {
diff --git a/esp32h2/src/efuse/rd_key1_data6.rs b/esp32h2/src/efuse/rd_key1_data6.rs
index ba8b96a6b3..9d5a3e944d 100644
--- a/esp32h2/src/efuse/rd_key1_data6.rs
+++ b/esp32h2/src/efuse/rd_key1_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA6")
-            .field("key1_data6", &format_args!("{}", self.key1_data6().bits()))
+            .field("key1_data6", &self.key1_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA6_SPEC {
diff --git a/esp32h2/src/efuse/rd_key1_data7.rs b/esp32h2/src/efuse/rd_key1_data7.rs
index ba5ea5e180..4d8d190773 100644
--- a/esp32h2/src/efuse/rd_key1_data7.rs
+++ b/esp32h2/src/efuse/rd_key1_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA7")
-            .field("key1_data7", &format_args!("{}", self.key1_data7().bits()))
+            .field("key1_data7", &self.key1_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA7_SPEC {
diff --git a/esp32h2/src/efuse/rd_key2_data0.rs b/esp32h2/src/efuse/rd_key2_data0.rs
index d090b56943..670f7a9712 100644
--- a/esp32h2/src/efuse/rd_key2_data0.rs
+++ b/esp32h2/src/efuse/rd_key2_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA0")
-            .field("key2_data0", &format_args!("{}", self.key2_data0().bits()))
+            .field("key2_data0", &self.key2_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA0_SPEC {
diff --git a/esp32h2/src/efuse/rd_key2_data1.rs b/esp32h2/src/efuse/rd_key2_data1.rs
index c8d52513bc..653b2d5860 100644
--- a/esp32h2/src/efuse/rd_key2_data1.rs
+++ b/esp32h2/src/efuse/rd_key2_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA1")
-            .field("key2_data1", &format_args!("{}", self.key2_data1().bits()))
+            .field("key2_data1", &self.key2_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA1_SPEC {
diff --git a/esp32h2/src/efuse/rd_key2_data2.rs b/esp32h2/src/efuse/rd_key2_data2.rs
index 594db86d03..ac2ec13773 100644
--- a/esp32h2/src/efuse/rd_key2_data2.rs
+++ b/esp32h2/src/efuse/rd_key2_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA2")
-            .field("key2_data2", &format_args!("{}", self.key2_data2().bits()))
+            .field("key2_data2", &self.key2_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA2_SPEC {
diff --git a/esp32h2/src/efuse/rd_key2_data3.rs b/esp32h2/src/efuse/rd_key2_data3.rs
index 11ef6ae075..347ff260f3 100644
--- a/esp32h2/src/efuse/rd_key2_data3.rs
+++ b/esp32h2/src/efuse/rd_key2_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA3")
-            .field("key2_data3", &format_args!("{}", self.key2_data3().bits()))
+            .field("key2_data3", &self.key2_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA3_SPEC {
diff --git a/esp32h2/src/efuse/rd_key2_data4.rs b/esp32h2/src/efuse/rd_key2_data4.rs
index 4bdb2eb156..cde8d0559c 100644
--- a/esp32h2/src/efuse/rd_key2_data4.rs
+++ b/esp32h2/src/efuse/rd_key2_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA4")
-            .field("key2_data4", &format_args!("{}", self.key2_data4().bits()))
+            .field("key2_data4", &self.key2_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA4_SPEC {
diff --git a/esp32h2/src/efuse/rd_key2_data5.rs b/esp32h2/src/efuse/rd_key2_data5.rs
index d4c08fe8bb..071d63afed 100644
--- a/esp32h2/src/efuse/rd_key2_data5.rs
+++ b/esp32h2/src/efuse/rd_key2_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA5")
-            .field("key2_data5", &format_args!("{}", self.key2_data5().bits()))
+            .field("key2_data5", &self.key2_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA5_SPEC {
diff --git a/esp32h2/src/efuse/rd_key2_data6.rs b/esp32h2/src/efuse/rd_key2_data6.rs
index 5034d53b5d..a7b4b5e111 100644
--- a/esp32h2/src/efuse/rd_key2_data6.rs
+++ b/esp32h2/src/efuse/rd_key2_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA6")
-            .field("key2_data6", &format_args!("{}", self.key2_data6().bits()))
+            .field("key2_data6", &self.key2_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA6_SPEC {
diff --git a/esp32h2/src/efuse/rd_key2_data7.rs b/esp32h2/src/efuse/rd_key2_data7.rs
index 0ce4cdab66..26b73dab0a 100644
--- a/esp32h2/src/efuse/rd_key2_data7.rs
+++ b/esp32h2/src/efuse/rd_key2_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA7")
-            .field("key2_data7", &format_args!("{}", self.key2_data7().bits()))
+            .field("key2_data7", &self.key2_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA7_SPEC {
diff --git a/esp32h2/src/efuse/rd_key3_data0.rs b/esp32h2/src/efuse/rd_key3_data0.rs
index c7874ba60f..324ab8ee6c 100644
--- a/esp32h2/src/efuse/rd_key3_data0.rs
+++ b/esp32h2/src/efuse/rd_key3_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA0")
-            .field("key3_data0", &format_args!("{}", self.key3_data0().bits()))
+            .field("key3_data0", &self.key3_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA0_SPEC {
diff --git a/esp32h2/src/efuse/rd_key3_data1.rs b/esp32h2/src/efuse/rd_key3_data1.rs
index 2dcf03994c..036e846966 100644
--- a/esp32h2/src/efuse/rd_key3_data1.rs
+++ b/esp32h2/src/efuse/rd_key3_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA1")
-            .field("key3_data1", &format_args!("{}", self.key3_data1().bits()))
+            .field("key3_data1", &self.key3_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA1_SPEC {
diff --git a/esp32h2/src/efuse/rd_key3_data2.rs b/esp32h2/src/efuse/rd_key3_data2.rs
index 71a11073a1..a01ccae711 100644
--- a/esp32h2/src/efuse/rd_key3_data2.rs
+++ b/esp32h2/src/efuse/rd_key3_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA2")
-            .field("key3_data2", &format_args!("{}", self.key3_data2().bits()))
+            .field("key3_data2", &self.key3_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA2_SPEC {
diff --git a/esp32h2/src/efuse/rd_key3_data3.rs b/esp32h2/src/efuse/rd_key3_data3.rs
index 521e42b9ac..ccf4f14cc0 100644
--- a/esp32h2/src/efuse/rd_key3_data3.rs
+++ b/esp32h2/src/efuse/rd_key3_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA3")
-            .field("key3_data3", &format_args!("{}", self.key3_data3().bits()))
+            .field("key3_data3", &self.key3_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA3_SPEC {
diff --git a/esp32h2/src/efuse/rd_key3_data4.rs b/esp32h2/src/efuse/rd_key3_data4.rs
index b6cad4ee2d..800a8f1dba 100644
--- a/esp32h2/src/efuse/rd_key3_data4.rs
+++ b/esp32h2/src/efuse/rd_key3_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA4")
-            .field("key3_data4", &format_args!("{}", self.key3_data4().bits()))
+            .field("key3_data4", &self.key3_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA4_SPEC {
diff --git a/esp32h2/src/efuse/rd_key3_data5.rs b/esp32h2/src/efuse/rd_key3_data5.rs
index ba0c41d811..90fc05e6b9 100644
--- a/esp32h2/src/efuse/rd_key3_data5.rs
+++ b/esp32h2/src/efuse/rd_key3_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA5")
-            .field("key3_data5", &format_args!("{}", self.key3_data5().bits()))
+            .field("key3_data5", &self.key3_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA5_SPEC {
diff --git a/esp32h2/src/efuse/rd_key3_data6.rs b/esp32h2/src/efuse/rd_key3_data6.rs
index 3d3c27b27e..97260fcf21 100644
--- a/esp32h2/src/efuse/rd_key3_data6.rs
+++ b/esp32h2/src/efuse/rd_key3_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA6")
-            .field("key3_data6", &format_args!("{}", self.key3_data6().bits()))
+            .field("key3_data6", &self.key3_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA6_SPEC {
diff --git a/esp32h2/src/efuse/rd_key3_data7.rs b/esp32h2/src/efuse/rd_key3_data7.rs
index 13a0d80f7c..78b1712e01 100644
--- a/esp32h2/src/efuse/rd_key3_data7.rs
+++ b/esp32h2/src/efuse/rd_key3_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA7")
-            .field("key3_data7", &format_args!("{}", self.key3_data7().bits()))
+            .field("key3_data7", &self.key3_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA7_SPEC {
diff --git a/esp32h2/src/efuse/rd_key4_data0.rs b/esp32h2/src/efuse/rd_key4_data0.rs
index c7da39c966..49583f118a 100644
--- a/esp32h2/src/efuse/rd_key4_data0.rs
+++ b/esp32h2/src/efuse/rd_key4_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA0")
-            .field("key4_data0", &format_args!("{}", self.key4_data0().bits()))
+            .field("key4_data0", &self.key4_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA0_SPEC {
diff --git a/esp32h2/src/efuse/rd_key4_data1.rs b/esp32h2/src/efuse/rd_key4_data1.rs
index 4e619445d1..2255f15151 100644
--- a/esp32h2/src/efuse/rd_key4_data1.rs
+++ b/esp32h2/src/efuse/rd_key4_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA1")
-            .field("key4_data1", &format_args!("{}", self.key4_data1().bits()))
+            .field("key4_data1", &self.key4_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA1_SPEC {
diff --git a/esp32h2/src/efuse/rd_key4_data2.rs b/esp32h2/src/efuse/rd_key4_data2.rs
index d6bc03916d..cc38532702 100644
--- a/esp32h2/src/efuse/rd_key4_data2.rs
+++ b/esp32h2/src/efuse/rd_key4_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA2")
-            .field("key4_data2", &format_args!("{}", self.key4_data2().bits()))
+            .field("key4_data2", &self.key4_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA2_SPEC {
diff --git a/esp32h2/src/efuse/rd_key4_data3.rs b/esp32h2/src/efuse/rd_key4_data3.rs
index 164f9df5af..2a4cf9b5a6 100644
--- a/esp32h2/src/efuse/rd_key4_data3.rs
+++ b/esp32h2/src/efuse/rd_key4_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA3")
-            .field("key4_data3", &format_args!("{}", self.key4_data3().bits()))
+            .field("key4_data3", &self.key4_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA3_SPEC {
diff --git a/esp32h2/src/efuse/rd_key4_data4.rs b/esp32h2/src/efuse/rd_key4_data4.rs
index e647ac36c7..6a877dc0b6 100644
--- a/esp32h2/src/efuse/rd_key4_data4.rs
+++ b/esp32h2/src/efuse/rd_key4_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA4")
-            .field("key4_data4", &format_args!("{}", self.key4_data4().bits()))
+            .field("key4_data4", &self.key4_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA4_SPEC {
diff --git a/esp32h2/src/efuse/rd_key4_data5.rs b/esp32h2/src/efuse/rd_key4_data5.rs
index ede1293132..20291e45a5 100644
--- a/esp32h2/src/efuse/rd_key4_data5.rs
+++ b/esp32h2/src/efuse/rd_key4_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA5")
-            .field("key4_data5", &format_args!("{}", self.key4_data5().bits()))
+            .field("key4_data5", &self.key4_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA5_SPEC {
diff --git a/esp32h2/src/efuse/rd_key4_data6.rs b/esp32h2/src/efuse/rd_key4_data6.rs
index 2d81ffd6ec..acfc601dab 100644
--- a/esp32h2/src/efuse/rd_key4_data6.rs
+++ b/esp32h2/src/efuse/rd_key4_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA6")
-            .field("key4_data6", &format_args!("{}", self.key4_data6().bits()))
+            .field("key4_data6", &self.key4_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA6_SPEC {
diff --git a/esp32h2/src/efuse/rd_key4_data7.rs b/esp32h2/src/efuse/rd_key4_data7.rs
index 258ed36331..9491ecfa8b 100644
--- a/esp32h2/src/efuse/rd_key4_data7.rs
+++ b/esp32h2/src/efuse/rd_key4_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA7")
-            .field("key4_data7", &format_args!("{}", self.key4_data7().bits()))
+            .field("key4_data7", &self.key4_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA7_SPEC {
diff --git a/esp32h2/src/efuse/rd_key5_data0.rs b/esp32h2/src/efuse/rd_key5_data0.rs
index 30afd98f27..eaa12eb5b5 100644
--- a/esp32h2/src/efuse/rd_key5_data0.rs
+++ b/esp32h2/src/efuse/rd_key5_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA0")
-            .field("key5_data0", &format_args!("{}", self.key5_data0().bits()))
+            .field("key5_data0", &self.key5_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA0_SPEC {
diff --git a/esp32h2/src/efuse/rd_key5_data1.rs b/esp32h2/src/efuse/rd_key5_data1.rs
index e9dce7e94e..ea2b0c5c93 100644
--- a/esp32h2/src/efuse/rd_key5_data1.rs
+++ b/esp32h2/src/efuse/rd_key5_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA1")
-            .field("key5_data1", &format_args!("{}", self.key5_data1().bits()))
+            .field("key5_data1", &self.key5_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA1_SPEC {
diff --git a/esp32h2/src/efuse/rd_key5_data2.rs b/esp32h2/src/efuse/rd_key5_data2.rs
index c689437cdc..f2ea02e234 100644
--- a/esp32h2/src/efuse/rd_key5_data2.rs
+++ b/esp32h2/src/efuse/rd_key5_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA2")
-            .field("key5_data2", &format_args!("{}", self.key5_data2().bits()))
+            .field("key5_data2", &self.key5_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA2_SPEC {
diff --git a/esp32h2/src/efuse/rd_key5_data3.rs b/esp32h2/src/efuse/rd_key5_data3.rs
index bca91c9d37..68a0f3034f 100644
--- a/esp32h2/src/efuse/rd_key5_data3.rs
+++ b/esp32h2/src/efuse/rd_key5_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA3")
-            .field("key5_data3", &format_args!("{}", self.key5_data3().bits()))
+            .field("key5_data3", &self.key5_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA3_SPEC {
diff --git a/esp32h2/src/efuse/rd_key5_data4.rs b/esp32h2/src/efuse/rd_key5_data4.rs
index f3ad10e5b8..9658e4f4b8 100644
--- a/esp32h2/src/efuse/rd_key5_data4.rs
+++ b/esp32h2/src/efuse/rd_key5_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA4")
-            .field("key5_data4", &format_args!("{}", self.key5_data4().bits()))
+            .field("key5_data4", &self.key5_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA4_SPEC {
diff --git a/esp32h2/src/efuse/rd_key5_data5.rs b/esp32h2/src/efuse/rd_key5_data5.rs
index 6d7123a48c..29d27d1c31 100644
--- a/esp32h2/src/efuse/rd_key5_data5.rs
+++ b/esp32h2/src/efuse/rd_key5_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA5")
-            .field("key5_data5", &format_args!("{}", self.key5_data5().bits()))
+            .field("key5_data5", &self.key5_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA5_SPEC {
diff --git a/esp32h2/src/efuse/rd_key5_data6.rs b/esp32h2/src/efuse/rd_key5_data6.rs
index d24ecae9af..cf5b5a4e0a 100644
--- a/esp32h2/src/efuse/rd_key5_data6.rs
+++ b/esp32h2/src/efuse/rd_key5_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA6")
-            .field("key5_data6", &format_args!("{}", self.key5_data6().bits()))
+            .field("key5_data6", &self.key5_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA6_SPEC {
diff --git a/esp32h2/src/efuse/rd_key5_data7.rs b/esp32h2/src/efuse/rd_key5_data7.rs
index 493d96b395..d22882be6d 100644
--- a/esp32h2/src/efuse/rd_key5_data7.rs
+++ b/esp32h2/src/efuse/rd_key5_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA7")
-            .field("key5_data7", &format_args!("{}", self.key5_data7().bits()))
+            .field("key5_data7", &self.key5_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA7_SPEC {
diff --git a/esp32h2/src/efuse/rd_mac_sys_0.rs b/esp32h2/src/efuse/rd_mac_sys_0.rs
index 2cdbd542b8..da3c646e9f 100644
--- a/esp32h2/src/efuse/rd_mac_sys_0.rs
+++ b/esp32h2/src/efuse/rd_mac_sys_0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SYS_0")
-            .field("mac_0", &format_args!("{}", self.mac_0().bits()))
+            .field("mac_0", &self.mac_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SYS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SYS_0_SPEC;
 impl crate::RegisterSpec for RD_MAC_SYS_0_SPEC {
diff --git a/esp32h2/src/efuse/rd_mac_sys_1.rs b/esp32h2/src/efuse/rd_mac_sys_1.rs
index adb9c73fc3..0e9b75a9f9 100644
--- a/esp32h2/src/efuse/rd_mac_sys_1.rs
+++ b/esp32h2/src/efuse/rd_mac_sys_1.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SYS_1")
-            .field("mac_1", &format_args!("{}", self.mac_1().bits()))
-            .field("mac_ext", &format_args!("{}", self.mac_ext().bits()))
+            .field("mac_1", &self.mac_1())
+            .field("mac_ext", &self.mac_ext())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SYS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SYS_1_SPEC;
 impl crate::RegisterSpec for RD_MAC_SYS_1_SPEC {
diff --git a/esp32h2/src/efuse/rd_mac_sys_2.rs b/esp32h2/src/efuse/rd_mac_sys_2.rs
index db55fff1a8..2c83171a4c 100644
--- a/esp32h2/src/efuse/rd_mac_sys_2.rs
+++ b/esp32h2/src/efuse/rd_mac_sys_2.rs
@@ -55,34 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SYS_2")
-            .field(
-                "rxiq_version",
-                &format_args!("{}", self.rxiq_version().bits()),
-            )
-            .field("rxiq_0", &format_args!("{}", self.rxiq_0().bits()))
-            .field("rxiq_1", &format_args!("{}", self.rxiq_1().bits()))
-            .field(
-                "active_hp_dbias",
-                &format_args!("{}", self.active_hp_dbias().bits()),
-            )
-            .field(
-                "active_lp_dbias",
-                &format_args!("{}", self.active_lp_dbias().bits()),
-            )
-            .field("dslp_dbias", &format_args!("{}", self.dslp_dbias().bits()))
-            .field(
-                "dbias_vol_gap_value1",
-                &format_args!("{}", self.dbias_vol_gap_value1().bit()),
-            )
+            .field("rxiq_version", &self.rxiq_version())
+            .field("rxiq_0", &self.rxiq_0())
+            .field("rxiq_1", &self.rxiq_1())
+            .field("active_hp_dbias", &self.active_hp_dbias())
+            .field("active_lp_dbias", &self.active_lp_dbias())
+            .field("dslp_dbias", &self.dslp_dbias())
+            .field("dbias_vol_gap_value1", &self.dbias_vol_gap_value1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SYS_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SYS_2_SPEC;
 impl crate::RegisterSpec for RD_MAC_SYS_2_SPEC {
diff --git a/esp32h2/src/efuse/rd_mac_sys_3.rs b/esp32h2/src/efuse/rd_mac_sys_3.rs
index 6af9118bd0..d121f7a2c7 100644
--- a/esp32h2/src/efuse/rd_mac_sys_3.rs
+++ b/esp32h2/src/efuse/rd_mac_sys_3.rs
@@ -69,45 +69,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SYS_3")
-            .field(
-                "dbias_vol_gap_value2",
-                &format_args!("{}", self.dbias_vol_gap_value2().bits()),
-            )
-            .field(
-                "dbias_vol_gap_sign",
-                &format_args!("{}", self.dbias_vol_gap_sign().bit()),
-            )
-            .field(
-                "mac_reserved_2",
-                &format_args!("{}", self.mac_reserved_2().bits()),
-            )
-            .field(
-                "wafer_version_minor",
-                &format_args!("{}", self.wafer_version_minor().bits()),
-            )
-            .field(
-                "wafer_version_major",
-                &format_args!("{}", self.wafer_version_major().bits()),
-            )
+            .field("dbias_vol_gap_value2", &self.dbias_vol_gap_value2())
+            .field("dbias_vol_gap_sign", &self.dbias_vol_gap_sign())
+            .field("mac_reserved_2", &self.mac_reserved_2())
+            .field("wafer_version_minor", &self.wafer_version_minor())
+            .field("wafer_version_major", &self.wafer_version_major())
             .field(
                 "disable_wafer_version_major",
-                &format_args!("{}", self.disable_wafer_version_major().bit()),
-            )
-            .field("flash_cap", &format_args!("{}", self.flash_cap().bits()))
-            .field("flash_temp", &format_args!("{}", self.flash_temp().bits()))
-            .field(
-                "flash_vendor",
-                &format_args!("{}", self.flash_vendor().bits()),
+                &self.disable_wafer_version_major(),
             )
+            .field("flash_cap", &self.flash_cap())
+            .field("flash_temp", &self.flash_temp())
+            .field("flash_vendor", &self.flash_vendor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SYS_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SYS_3_SPEC;
 impl crate::RegisterSpec for RD_MAC_SYS_3_SPEC {
diff --git a/esp32h2/src/efuse/rd_mac_sys_4.rs b/esp32h2/src/efuse/rd_mac_sys_4.rs
index 81106abfab..dc617221e2 100644
--- a/esp32h2/src/efuse/rd_mac_sys_4.rs
+++ b/esp32h2/src/efuse/rd_mac_sys_4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SYS_4")
-            .field(
-                "sys_data_part0_1",
-                &format_args!("{}", self.sys_data_part0_1().bits()),
-            )
+            .field("sys_data_part0_1", &self.sys_data_part0_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SYS_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SYS_4_SPEC;
 impl crate::RegisterSpec for RD_MAC_SYS_4_SPEC {
diff --git a/esp32h2/src/efuse/rd_mac_sys_5.rs b/esp32h2/src/efuse/rd_mac_sys_5.rs
index 643e48e480..a3ff86e6f6 100644
--- a/esp32h2/src/efuse/rd_mac_sys_5.rs
+++ b/esp32h2/src/efuse/rd_mac_sys_5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SYS_5")
-            .field(
-                "sys_data_part0_2",
-                &format_args!("{}", self.sys_data_part0_2().bits()),
-            )
+            .field("sys_data_part0_2", &self.sys_data_part0_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SYS_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SYS_5_SPEC;
 impl crate::RegisterSpec for RD_MAC_SYS_5_SPEC {
diff --git a/esp32h2/src/efuse/rd_repeat_data0.rs b/esp32h2/src/efuse/rd_repeat_data0.rs
index 310b26eff1..f9bcad94be 100644
--- a/esp32h2/src/efuse/rd_repeat_data0.rs
+++ b/esp32h2/src/efuse/rd_repeat_data0.rs
@@ -146,80 +146,32 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA0")
-            .field("rd_dis", &format_args!("{}", self.rd_dis().bits()))
-            .field(
-                "rpt4_reserved0_4",
-                &format_args!("{}", self.rpt4_reserved0_4().bit()),
-            )
-            .field("dis_icache", &format_args!("{}", self.dis_icache().bit()))
-            .field(
-                "dis_usb_jtag",
-                &format_args!("{}", self.dis_usb_jtag().bit()),
-            )
-            .field(
-                "powerglitch_en",
-                &format_args!("{}", self.powerglitch_en().bit()),
-            )
-            .field(
-                "dis_usb_serial_jtag",
-                &format_args!("{}", self.dis_usb_serial_jtag().bit()),
-            )
-            .field(
-                "dis_force_download",
-                &format_args!("{}", self.dis_force_download().bit()),
-            )
-            .field(
-                "spi_download_mspi_dis",
-                &format_args!("{}", self.spi_download_mspi_dis().bit()),
-            )
-            .field("dis_can", &format_args!("{}", self.dis_can().bit()))
-            .field(
-                "jtag_sel_enable",
-                &format_args!("{}", self.jtag_sel_enable().bit()),
-            )
-            .field(
-                "soft_dis_jtag",
-                &format_args!("{}", self.soft_dis_jtag().bits()),
-            )
-            .field(
-                "dis_pad_jtag",
-                &format_args!("{}", self.dis_pad_jtag().bit()),
-            )
+            .field("rd_dis", &self.rd_dis())
+            .field("rpt4_reserved0_4", &self.rpt4_reserved0_4())
+            .field("dis_icache", &self.dis_icache())
+            .field("dis_usb_jtag", &self.dis_usb_jtag())
+            .field("powerglitch_en", &self.powerglitch_en())
+            .field("dis_usb_serial_jtag", &self.dis_usb_serial_jtag())
+            .field("dis_force_download", &self.dis_force_download())
+            .field("spi_download_mspi_dis", &self.spi_download_mspi_dis())
+            .field("dis_can", &self.dis_can())
+            .field("jtag_sel_enable", &self.jtag_sel_enable())
+            .field("soft_dis_jtag", &self.soft_dis_jtag())
+            .field("dis_pad_jtag", &self.dis_pad_jtag())
             .field(
                 "dis_download_manual_encrypt",
-                &format_args!("{}", self.dis_download_manual_encrypt().bit()),
-            )
-            .field("usb_drefh", &format_args!("{}", self.usb_drefh().bits()))
-            .field("usb_drefl", &format_args!("{}", self.usb_drefl().bits()))
-            .field(
-                "usb_exchg_pins",
-                &format_args!("{}", self.usb_exchg_pins().bit()),
-            )
-            .field(
-                "vdd_spi_as_gpio",
-                &format_args!("{}", self.vdd_spi_as_gpio().bit()),
-            )
-            .field(
-                "rpt4_reserved0_2",
-                &format_args!("{}", self.rpt4_reserved0_2().bits()),
-            )
-            .field(
-                "rpt4_reserved0_1",
-                &format_args!("{}", self.rpt4_reserved0_1().bit()),
-            )
-            .field(
-                "rpt4_reserved0_0",
-                &format_args!("{}", self.rpt4_reserved0_0().bits()),
+                &self.dis_download_manual_encrypt(),
             )
+            .field("usb_drefh", &self.usb_drefh())
+            .field("usb_drefl", &self.usb_drefl())
+            .field("usb_exchg_pins", &self.usb_exchg_pins())
+            .field("vdd_spi_as_gpio", &self.vdd_spi_as_gpio())
+            .field("rpt4_reserved0_2", &self.rpt4_reserved0_2())
+            .field("rpt4_reserved0_1", &self.rpt4_reserved0_1())
+            .field("rpt4_reserved0_0", &self.rpt4_reserved0_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA0_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA0_SPEC {
diff --git a/esp32h2/src/efuse/rd_repeat_data1.rs b/esp32h2/src/efuse/rd_repeat_data1.rs
index e319c93448..9e3595a84e 100644
--- a/esp32h2/src/efuse/rd_repeat_data1.rs
+++ b/esp32h2/src/efuse/rd_repeat_data1.rs
@@ -62,47 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA1")
-            .field(
-                "rpt4_reserved1_1",
-                &format_args!("{}", self.rpt4_reserved1_1().bits()),
-            )
-            .field(
-                "wdt_delay_sel",
-                &format_args!("{}", self.wdt_delay_sel().bits()),
-            )
-            .field(
-                "spi_boot_crypt_cnt",
-                &format_args!("{}", self.spi_boot_crypt_cnt().bits()),
-            )
-            .field(
-                "secure_boot_key_revoke0",
-                &format_args!("{}", self.secure_boot_key_revoke0().bit()),
-            )
-            .field(
-                "secure_boot_key_revoke1",
-                &format_args!("{}", self.secure_boot_key_revoke1().bit()),
-            )
-            .field(
-                "secure_boot_key_revoke2",
-                &format_args!("{}", self.secure_boot_key_revoke2().bit()),
-            )
-            .field(
-                "key_purpose_0",
-                &format_args!("{}", self.key_purpose_0().bits()),
-            )
-            .field(
-                "key_purpose_1",
-                &format_args!("{}", self.key_purpose_1().bits()),
-            )
+            .field("rpt4_reserved1_1", &self.rpt4_reserved1_1())
+            .field("wdt_delay_sel", &self.wdt_delay_sel())
+            .field("spi_boot_crypt_cnt", &self.spi_boot_crypt_cnt())
+            .field("secure_boot_key_revoke0", &self.secure_boot_key_revoke0())
+            .field("secure_boot_key_revoke1", &self.secure_boot_key_revoke1())
+            .field("secure_boot_key_revoke2", &self.secure_boot_key_revoke2())
+            .field("key_purpose_0", &self.key_purpose_0())
+            .field("key_purpose_1", &self.key_purpose_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA1_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA1_SPEC {
diff --git a/esp32h2/src/efuse/rd_repeat_data2.rs b/esp32h2/src/efuse/rd_repeat_data2.rs
index 4d052f8077..f0755ce8f7 100644
--- a/esp32h2/src/efuse/rd_repeat_data2.rs
+++ b/esp32h2/src/efuse/rd_repeat_data2.rs
@@ -83,56 +83,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA2")
-            .field(
-                "key_purpose_2",
-                &format_args!("{}", self.key_purpose_2().bits()),
-            )
-            .field(
-                "key_purpose_3",
-                &format_args!("{}", self.key_purpose_3().bits()),
-            )
-            .field(
-                "key_purpose_4",
-                &format_args!("{}", self.key_purpose_4().bits()),
-            )
-            .field(
-                "key_purpose_5",
-                &format_args!("{}", self.key_purpose_5().bits()),
-            )
-            .field(
-                "sec_dpa_level",
-                &format_args!("{}", self.sec_dpa_level().bits()),
-            )
+            .field("key_purpose_2", &self.key_purpose_2())
+            .field("key_purpose_3", &self.key_purpose_3())
+            .field("key_purpose_4", &self.key_purpose_4())
+            .field("key_purpose_5", &self.key_purpose_5())
+            .field("sec_dpa_level", &self.sec_dpa_level())
             .field(
                 "ecdsa_force_use_hardware_k",
-                &format_args!("{}", self.ecdsa_force_use_hardware_k().bit()),
-            )
-            .field(
-                "crypt_dpa_enable",
-                &format_args!("{}", self.crypt_dpa_enable().bit()),
-            )
-            .field(
-                "secure_boot_en",
-                &format_args!("{}", self.secure_boot_en().bit()),
+                &self.ecdsa_force_use_hardware_k(),
             )
+            .field("crypt_dpa_enable", &self.crypt_dpa_enable())
+            .field("secure_boot_en", &self.secure_boot_en())
             .field(
                 "secure_boot_aggressive_revoke",
-                &format_args!("{}", self.secure_boot_aggressive_revoke().bit()),
+                &self.secure_boot_aggressive_revoke(),
             )
-            .field(
-                "rpt4_reserved2_0",
-                &format_args!("{}", self.rpt4_reserved2_0().bits()),
-            )
-            .field("flash_tpuw", &format_args!("{}", self.flash_tpuw().bits()))
+            .field("rpt4_reserved2_0", &self.rpt4_reserved2_0())
+            .field("flash_tpuw", &self.flash_tpuw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA2_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA2_SPEC {
diff --git a/esp32h2/src/efuse/rd_repeat_data3.rs b/esp32h2/src/efuse/rd_repeat_data3.rs
index c1e3cab418..60565d19e2 100644
--- a/esp32h2/src/efuse/rd_repeat_data3.rs
+++ b/esp32h2/src/efuse/rd_repeat_data3.rs
@@ -83,59 +83,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA3")
-            .field(
-                "dis_download_mode",
-                &format_args!("{}", self.dis_download_mode().bit()),
-            )
-            .field(
-                "dis_direct_boot",
-                &format_args!("{}", self.dis_direct_boot().bit()),
-            )
-            .field(
-                "dis_usb_print",
-                &format_args!("{}", self.dis_usb_print().bit()),
-            )
-            .field(
-                "rpt4_reserved3_5",
-                &format_args!("{}", self.rpt4_reserved3_5().bit()),
-            )
+            .field("dis_download_mode", &self.dis_download_mode())
+            .field("dis_direct_boot", &self.dis_direct_boot())
+            .field("dis_usb_print", &self.dis_usb_print())
+            .field("rpt4_reserved3_5", &self.rpt4_reserved3_5())
             .field(
                 "dis_usb_serial_jtag_download_mode",
-                &format_args!("{}", self.dis_usb_serial_jtag_download_mode().bit()),
-            )
-            .field(
-                "enable_security_download",
-                &format_args!("{}", self.enable_security_download().bit()),
-            )
-            .field(
-                "uart_print_control",
-                &format_args!("{}", self.uart_print_control().bits()),
-            )
-            .field(
-                "force_send_resume",
-                &format_args!("{}", self.force_send_resume().bit()),
-            )
-            .field(
-                "secure_version",
-                &format_args!("{}", self.secure_version().bits()),
+                &self.dis_usb_serial_jtag_download_mode(),
             )
+            .field("enable_security_download", &self.enable_security_download())
+            .field("uart_print_control", &self.uart_print_control())
+            .field("force_send_resume", &self.force_send_resume())
+            .field("secure_version", &self.secure_version())
             .field(
                 "secure_boot_disable_fast_wake",
-                &format_args!("{}", self.secure_boot_disable_fast_wake().bit()),
-            )
-            .field(
-                "hys_en_pad0",
-                &format_args!("{}", self.hys_en_pad0().bits()),
+                &self.secure_boot_disable_fast_wake(),
             )
+            .field("hys_en_pad0", &self.hys_en_pad0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA3_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA3_SPEC {
diff --git a/esp32h2/src/efuse/rd_repeat_data4.rs b/esp32h2/src/efuse/rd_repeat_data4.rs
index 44547e723b..57ab064777 100644
--- a/esp32h2/src/efuse/rd_repeat_data4.rs
+++ b/esp32h2/src/efuse/rd_repeat_data4.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA4")
-            .field(
-                "hys_en_pad1",
-                &format_args!("{}", self.hys_en_pad1().bits()),
-            )
-            .field(
-                "rpt4_reserved4_1",
-                &format_args!("{}", self.rpt4_reserved4_1().bits()),
-            )
-            .field(
-                "rpt4_reserved4_0",
-                &format_args!("{}", self.rpt4_reserved4_0().bits()),
-            )
+            .field("hys_en_pad1", &self.hys_en_pad1())
+            .field("rpt4_reserved4_1", &self.rpt4_reserved4_1())
+            .field("rpt4_reserved4_0", &self.rpt4_reserved4_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA4_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA4_SPEC {
diff --git a/esp32h2/src/efuse/rd_repeat_err0.rs b/esp32h2/src/efuse/rd_repeat_err0.rs
index d92c7365f4..38a2782f27 100644
--- a/esp32h2/src/efuse/rd_repeat_err0.rs
+++ b/esp32h2/src/efuse/rd_repeat_err0.rs
@@ -146,92 +146,35 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR0")
-            .field("rd_dis_err", &format_args!("{}", self.rd_dis_err().bits()))
-            .field(
-                "rpt4_reserved0_err_4",
-                &format_args!("{}", self.rpt4_reserved0_err_4().bit()),
-            )
-            .field(
-                "dis_icache_err",
-                &format_args!("{}", self.dis_icache_err().bit()),
-            )
-            .field(
-                "dis_usb_jtag_err",
-                &format_args!("{}", self.dis_usb_jtag_err().bit()),
-            )
-            .field(
-                "powerglitch_en_err",
-                &format_args!("{}", self.powerglitch_en_err().bit()),
-            )
-            .field(
-                "dis_usb_serial_jtag_err",
-                &format_args!("{}", self.dis_usb_serial_jtag_err().bit()),
-            )
-            .field(
-                "dis_force_download_err",
-                &format_args!("{}", self.dis_force_download_err().bit()),
-            )
+            .field("rd_dis_err", &self.rd_dis_err())
+            .field("rpt4_reserved0_err_4", &self.rpt4_reserved0_err_4())
+            .field("dis_icache_err", &self.dis_icache_err())
+            .field("dis_usb_jtag_err", &self.dis_usb_jtag_err())
+            .field("powerglitch_en_err", &self.powerglitch_en_err())
+            .field("dis_usb_serial_jtag_err", &self.dis_usb_serial_jtag_err())
+            .field("dis_force_download_err", &self.dis_force_download_err())
             .field(
                 "spi_download_mspi_dis_err",
-                &format_args!("{}", self.spi_download_mspi_dis_err().bit()),
-            )
-            .field(
-                "dis_twai_err",
-                &format_args!("{}", self.dis_twai_err().bit()),
-            )
-            .field(
-                "jtag_sel_enable_err",
-                &format_args!("{}", self.jtag_sel_enable_err().bit()),
-            )
-            .field(
-                "soft_dis_jtag_err",
-                &format_args!("{}", self.soft_dis_jtag_err().bits()),
-            )
-            .field(
-                "dis_pad_jtag_err",
-                &format_args!("{}", self.dis_pad_jtag_err().bit()),
+                &self.spi_download_mspi_dis_err(),
             )
+            .field("dis_twai_err", &self.dis_twai_err())
+            .field("jtag_sel_enable_err", &self.jtag_sel_enable_err())
+            .field("soft_dis_jtag_err", &self.soft_dis_jtag_err())
+            .field("dis_pad_jtag_err", &self.dis_pad_jtag_err())
             .field(
                 "dis_download_manual_encrypt_err",
-                &format_args!("{}", self.dis_download_manual_encrypt_err().bit()),
-            )
-            .field(
-                "usb_drefh_err",
-                &format_args!("{}", self.usb_drefh_err().bits()),
-            )
-            .field(
-                "usb_drefl_err",
-                &format_args!("{}", self.usb_drefl_err().bits()),
-            )
-            .field(
-                "usb_exchg_pins_err",
-                &format_args!("{}", self.usb_exchg_pins_err().bit()),
-            )
-            .field(
-                "vdd_spi_as_gpio_err",
-                &format_args!("{}", self.vdd_spi_as_gpio_err().bit()),
-            )
-            .field(
-                "rpt4_reserved0_err_2",
-                &format_args!("{}", self.rpt4_reserved0_err_2().bits()),
-            )
-            .field(
-                "rpt4_reserved0_err_1",
-                &format_args!("{}", self.rpt4_reserved0_err_1().bit()),
-            )
-            .field(
-                "rpt4_reserved0_err_0",
-                &format_args!("{}", self.rpt4_reserved0_err_0().bits()),
-            )
+                &self.dis_download_manual_encrypt_err(),
+            )
+            .field("usb_drefh_err", &self.usb_drefh_err())
+            .field("usb_drefl_err", &self.usb_drefl_err())
+            .field("usb_exchg_pins_err", &self.usb_exchg_pins_err())
+            .field("vdd_spi_as_gpio_err", &self.vdd_spi_as_gpio_err())
+            .field("rpt4_reserved0_err_2", &self.rpt4_reserved0_err_2())
+            .field("rpt4_reserved0_err_1", &self.rpt4_reserved0_err_1())
+            .field("rpt4_reserved0_err_0", &self.rpt4_reserved0_err_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 0 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR0_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR0_SPEC {
diff --git a/esp32h2/src/efuse/rd_repeat_err1.rs b/esp32h2/src/efuse/rd_repeat_err1.rs
index 0e0a7958ad..4d7d31b7f1 100644
--- a/esp32h2/src/efuse/rd_repeat_err1.rs
+++ b/esp32h2/src/efuse/rd_repeat_err1.rs
@@ -62,47 +62,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR1")
-            .field(
-                "rpt4_reserved1_err_0",
-                &format_args!("{}", self.rpt4_reserved1_err_0().bits()),
-            )
-            .field(
-                "wdt_delay_sel_err",
-                &format_args!("{}", self.wdt_delay_sel_err().bits()),
-            )
-            .field(
-                "spi_boot_crypt_cnt_err",
-                &format_args!("{}", self.spi_boot_crypt_cnt_err().bits()),
-            )
+            .field("rpt4_reserved1_err_0", &self.rpt4_reserved1_err_0())
+            .field("wdt_delay_sel_err", &self.wdt_delay_sel_err())
+            .field("spi_boot_crypt_cnt_err", &self.spi_boot_crypt_cnt_err())
             .field(
                 "secure_boot_key_revoke0_err",
-                &format_args!("{}", self.secure_boot_key_revoke0_err().bit()),
+                &self.secure_boot_key_revoke0_err(),
             )
             .field(
                 "secure_boot_key_revoke1_err",
-                &format_args!("{}", self.secure_boot_key_revoke1_err().bit()),
+                &self.secure_boot_key_revoke1_err(),
             )
             .field(
                 "secure_boot_key_revoke2_err",
-                &format_args!("{}", self.secure_boot_key_revoke2_err().bit()),
-            )
-            .field(
-                "key_purpose_0_err",
-                &format_args!("{}", self.key_purpose_0_err().bits()),
-            )
-            .field(
-                "key_purpose_1_err",
-                &format_args!("{}", self.key_purpose_1_err().bits()),
+                &self.secure_boot_key_revoke2_err(),
             )
+            .field("key_purpose_0_err", &self.key_purpose_0_err())
+            .field("key_purpose_1_err", &self.key_purpose_1_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 1 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR1_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR1_SPEC {
diff --git a/esp32h2/src/efuse/rd_repeat_err2.rs b/esp32h2/src/efuse/rd_repeat_err2.rs
index a3667f5af9..b16f3e3b56 100644
--- a/esp32h2/src/efuse/rd_repeat_err2.rs
+++ b/esp32h2/src/efuse/rd_repeat_err2.rs
@@ -83,59 +83,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR2")
-            .field(
-                "key_purpose_2_err",
-                &format_args!("{}", self.key_purpose_2_err().bits()),
-            )
-            .field(
-                "key_purpose_3_err",
-                &format_args!("{}", self.key_purpose_3_err().bits()),
-            )
-            .field(
-                "key_purpose_4_err",
-                &format_args!("{}", self.key_purpose_4_err().bits()),
-            )
-            .field(
-                "key_purpose_5_err",
-                &format_args!("{}", self.key_purpose_5_err().bits()),
-            )
-            .field(
-                "sec_dpa_level_err",
-                &format_args!("{}", self.sec_dpa_level_err().bits()),
-            )
-            .field(
-                "rpt4_reserved2_err_1",
-                &format_args!("{}", self.rpt4_reserved2_err_1().bit()),
-            )
-            .field(
-                "crypt_dpa_enable_err",
-                &format_args!("{}", self.crypt_dpa_enable_err().bit()),
-            )
-            .field(
-                "secure_boot_en_err",
-                &format_args!("{}", self.secure_boot_en_err().bit()),
-            )
+            .field("key_purpose_2_err", &self.key_purpose_2_err())
+            .field("key_purpose_3_err", &self.key_purpose_3_err())
+            .field("key_purpose_4_err", &self.key_purpose_4_err())
+            .field("key_purpose_5_err", &self.key_purpose_5_err())
+            .field("sec_dpa_level_err", &self.sec_dpa_level_err())
+            .field("rpt4_reserved2_err_1", &self.rpt4_reserved2_err_1())
+            .field("crypt_dpa_enable_err", &self.crypt_dpa_enable_err())
+            .field("secure_boot_en_err", &self.secure_boot_en_err())
             .field(
                 "secure_boot_aggressive_revoke_err",
-                &format_args!("{}", self.secure_boot_aggressive_revoke_err().bit()),
-            )
-            .field(
-                "rpt4_reserved2_err_0",
-                &format_args!("{}", self.rpt4_reserved2_err_0().bits()),
-            )
-            .field(
-                "flash_tpuw_err",
-                &format_args!("{}", self.flash_tpuw_err().bits()),
+                &self.secure_boot_aggressive_revoke_err(),
             )
+            .field("rpt4_reserved2_err_0", &self.rpt4_reserved2_err_0())
+            .field("flash_tpuw_err", &self.flash_tpuw_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 2 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR2_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR2_SPEC {
diff --git a/esp32h2/src/efuse/rd_repeat_err3.rs b/esp32h2/src/efuse/rd_repeat_err3.rs
index 78f80130ff..800b535132 100644
--- a/esp32h2/src/efuse/rd_repeat_err3.rs
+++ b/esp32h2/src/efuse/rd_repeat_err3.rs
@@ -83,59 +83,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR3")
-            .field(
-                "dis_download_mode_err",
-                &format_args!("{}", self.dis_download_mode_err().bit()),
-            )
-            .field(
-                "dis_direct_boot_err",
-                &format_args!("{}", self.dis_direct_boot_err().bit()),
-            )
-            .field(
-                "usb_print_err",
-                &format_args!("{}", self.usb_print_err().bit()),
-            )
-            .field(
-                "rpt4_reserved3_err_5",
-                &format_args!("{}", self.rpt4_reserved3_err_5().bit()),
-            )
+            .field("dis_download_mode_err", &self.dis_download_mode_err())
+            .field("dis_direct_boot_err", &self.dis_direct_boot_err())
+            .field("usb_print_err", &self.usb_print_err())
+            .field("rpt4_reserved3_err_5", &self.rpt4_reserved3_err_5())
             .field(
                 "dis_usb_serial_jtag_download_mode_err",
-                &format_args!("{}", self.dis_usb_serial_jtag_download_mode_err().bit()),
+                &self.dis_usb_serial_jtag_download_mode_err(),
             )
             .field(
                 "enable_security_download_err",
-                &format_args!("{}", self.enable_security_download_err().bit()),
-            )
-            .field(
-                "uart_print_control_err",
-                &format_args!("{}", self.uart_print_control_err().bits()),
-            )
-            .field(
-                "force_send_resume_err",
-                &format_args!("{}", self.force_send_resume_err().bit()),
-            )
-            .field(
-                "secure_version_err",
-                &format_args!("{}", self.secure_version_err().bits()),
+                &self.enable_security_download_err(),
             )
+            .field("uart_print_control_err", &self.uart_print_control_err())
+            .field("force_send_resume_err", &self.force_send_resume_err())
+            .field("secure_version_err", &self.secure_version_err())
             .field(
                 "secure_boot_disable_fast_wake_err",
-                &format_args!("{}", self.secure_boot_disable_fast_wake_err().bit()),
-            )
-            .field(
-                "hys_en_pad0_err",
-                &format_args!("{}", self.hys_en_pad0_err().bits()),
+                &self.secure_boot_disable_fast_wake_err(),
             )
+            .field("hys_en_pad0_err", &self.hys_en_pad0_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 3 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR3_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR3_SPEC {
diff --git a/esp32h2/src/efuse/rd_repeat_err4.rs b/esp32h2/src/efuse/rd_repeat_err4.rs
index 4ebae0aee2..4a60e78513 100644
--- a/esp32h2/src/efuse/rd_repeat_err4.rs
+++ b/esp32h2/src/efuse/rd_repeat_err4.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR4")
-            .field(
-                "hys_en_pad1_err",
-                &format_args!("{}", self.hys_en_pad1_err().bits()),
-            )
-            .field(
-                "rpt4_reserved4_err_1",
-                &format_args!("{}", self.rpt4_reserved4_err_1().bits()),
-            )
-            .field(
-                "rpt4_reserved4_err_0",
-                &format_args!("{}", self.rpt4_reserved4_err_0().bits()),
-            )
+            .field("hys_en_pad1_err", &self.hys_en_pad1_err())
+            .field("rpt4_reserved4_err_1", &self.rpt4_reserved4_err_1())
+            .field("rpt4_reserved4_err_0", &self.rpt4_reserved4_err_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 4 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR4_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR4_SPEC {
diff --git a/esp32h2/src/efuse/rd_rs_err0.rs b/esp32h2/src/efuse/rd_rs_err0.rs
index ea7bad6e93..ed5dc386c0 100644
--- a/esp32h2/src/efuse/rd_rs_err0.rs
+++ b/esp32h2/src/efuse/rd_rs_err0.rs
@@ -118,64 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_RS_ERR0")
-            .field(
-                "mac_spi_8m_err_num",
-                &format_args!("{}", self.mac_spi_8m_err_num().bits()),
-            )
-            .field(
-                "mac_spi_8m_fail",
-                &format_args!("{}", self.mac_spi_8m_fail().bit()),
-            )
-            .field(
-                "sys_part1_num",
-                &format_args!("{}", self.sys_part1_num().bits()),
-            )
-            .field(
-                "sys_part1_fail",
-                &format_args!("{}", self.sys_part1_fail().bit()),
-            )
-            .field(
-                "usr_data_err_num",
-                &format_args!("{}", self.usr_data_err_num().bits()),
-            )
-            .field(
-                "usr_data_fail",
-                &format_args!("{}", self.usr_data_fail().bit()),
-            )
-            .field(
-                "key0_err_num",
-                &format_args!("{}", self.key0_err_num().bits()),
-            )
-            .field("key0_fail", &format_args!("{}", self.key0_fail().bit()))
-            .field(
-                "key1_err_num",
-                &format_args!("{}", self.key1_err_num().bits()),
-            )
-            .field("key1_fail", &format_args!("{}", self.key1_fail().bit()))
-            .field(
-                "key2_err_num",
-                &format_args!("{}", self.key2_err_num().bits()),
-            )
-            .field("key2_fail", &format_args!("{}", self.key2_fail().bit()))
-            .field(
-                "key3_err_num",
-                &format_args!("{}", self.key3_err_num().bits()),
-            )
-            .field("key3_fail", &format_args!("{}", self.key3_fail().bit()))
-            .field(
-                "key4_err_num",
-                &format_args!("{}", self.key4_err_num().bits()),
-            )
-            .field("key4_fail", &format_args!("{}", self.key4_fail().bit()))
+            .field("mac_spi_8m_err_num", &self.mac_spi_8m_err_num())
+            .field("mac_spi_8m_fail", &self.mac_spi_8m_fail())
+            .field("sys_part1_num", &self.sys_part1_num())
+            .field("sys_part1_fail", &self.sys_part1_fail())
+            .field("usr_data_err_num", &self.usr_data_err_num())
+            .field("usr_data_fail", &self.usr_data_fail())
+            .field("key0_err_num", &self.key0_err_num())
+            .field("key0_fail", &self.key0_fail())
+            .field("key1_err_num", &self.key1_err_num())
+            .field("key1_fail", &self.key1_fail())
+            .field("key2_err_num", &self.key2_err_num())
+            .field("key2_fail", &self.key2_fail())
+            .field("key3_err_num", &self.key3_err_num())
+            .field("key3_fail", &self.key3_fail())
+            .field("key4_err_num", &self.key4_err_num())
+            .field("key4_fail", &self.key4_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RS_ERR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 0 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RS_ERR0_SPEC;
 impl crate::RegisterSpec for RD_RS_ERR0_SPEC {
diff --git a/esp32h2/src/efuse/rd_rs_err1.rs b/esp32h2/src/efuse/rd_rs_err1.rs
index 04fe9a9db1..188a8b967f 100644
--- a/esp32h2/src/efuse/rd_rs_err1.rs
+++ b/esp32h2/src/efuse/rd_rs_err1.rs
@@ -34,28 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_RS_ERR1")
-            .field(
-                "key5_err_num",
-                &format_args!("{}", self.key5_err_num().bits()),
-            )
-            .field("key5_fail", &format_args!("{}", self.key5_fail().bit()))
-            .field(
-                "sys_part2_err_num",
-                &format_args!("{}", self.sys_part2_err_num().bits()),
-            )
-            .field(
-                "sys_part2_fail",
-                &format_args!("{}", self.sys_part2_fail().bit()),
-            )
+            .field("key5_err_num", &self.key5_err_num())
+            .field("key5_fail", &self.key5_fail())
+            .field("sys_part2_err_num", &self.sys_part2_err_num())
+            .field("sys_part2_fail", &self.sys_part2_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RS_ERR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 1 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RS_ERR1_SPEC;
 impl crate::RegisterSpec for RD_RS_ERR1_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part1_data0.rs b/esp32h2/src/efuse/rd_sys_part1_data0.rs
index f28c3bd2d0..d6b4a065d4 100644
--- a/esp32h2/src/efuse/rd_sys_part1_data0.rs
+++ b/esp32h2/src/efuse/rd_sys_part1_data0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA0")
-            .field(
-                "sys_data_part1_0",
-                &format_args!("{}", self.sys_data_part1_0().bits()),
-            )
+            .field("sys_data_part1_0", &self.sys_data_part1_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA0_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA0_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part1_data1.rs b/esp32h2/src/efuse/rd_sys_part1_data1.rs
index c7345ebcfe..aa8b5a77e1 100644
--- a/esp32h2/src/efuse/rd_sys_part1_data1.rs
+++ b/esp32h2/src/efuse/rd_sys_part1_data1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA1")
-            .field(
-                "sys_data_part1_1",
-                &format_args!("{}", self.sys_data_part1_1().bits()),
-            )
+            .field("sys_data_part1_1", &self.sys_data_part1_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA1_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA1_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part1_data2.rs b/esp32h2/src/efuse/rd_sys_part1_data2.rs
index 00d8eee981..6ce86ab9ea 100644
--- a/esp32h2/src/efuse/rd_sys_part1_data2.rs
+++ b/esp32h2/src/efuse/rd_sys_part1_data2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA2")
-            .field(
-                "sys_data_part1_2",
-                &format_args!("{}", self.sys_data_part1_2().bits()),
-            )
+            .field("sys_data_part1_2", &self.sys_data_part1_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA2_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA2_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part1_data3.rs b/esp32h2/src/efuse/rd_sys_part1_data3.rs
index 1025d41a34..f3c8563223 100644
--- a/esp32h2/src/efuse/rd_sys_part1_data3.rs
+++ b/esp32h2/src/efuse/rd_sys_part1_data3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA3")
-            .field(
-                "sys_data_part1_3",
-                &format_args!("{}", self.sys_data_part1_3().bits()),
-            )
+            .field("sys_data_part1_3", &self.sys_data_part1_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA3_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA3_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part1_data4.rs b/esp32h2/src/efuse/rd_sys_part1_data4.rs
index 11e51eb81d..c3a05173b2 100644
--- a/esp32h2/src/efuse/rd_sys_part1_data4.rs
+++ b/esp32h2/src/efuse/rd_sys_part1_data4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA4")
-            .field(
-                "sys_data_part1_4",
-                &format_args!("{}", self.sys_data_part1_4().bits()),
-            )
+            .field("sys_data_part1_4", &self.sys_data_part1_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA4_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA4_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part1_data5.rs b/esp32h2/src/efuse/rd_sys_part1_data5.rs
index f6e08ae404..06e29f147d 100644
--- a/esp32h2/src/efuse/rd_sys_part1_data5.rs
+++ b/esp32h2/src/efuse/rd_sys_part1_data5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA5")
-            .field(
-                "sys_data_part1_5",
-                &format_args!("{}", self.sys_data_part1_5().bits()),
-            )
+            .field("sys_data_part1_5", &self.sys_data_part1_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA5_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA5_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part1_data6.rs b/esp32h2/src/efuse/rd_sys_part1_data6.rs
index 9065b698dc..3fd9b053a9 100644
--- a/esp32h2/src/efuse/rd_sys_part1_data6.rs
+++ b/esp32h2/src/efuse/rd_sys_part1_data6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA6")
-            .field(
-                "sys_data_part1_6",
-                &format_args!("{}", self.sys_data_part1_6().bits()),
-            )
+            .field("sys_data_part1_6", &self.sys_data_part1_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA6_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA6_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part1_data7.rs b/esp32h2/src/efuse/rd_sys_part1_data7.rs
index cacdcd1f63..c87a01c324 100644
--- a/esp32h2/src/efuse/rd_sys_part1_data7.rs
+++ b/esp32h2/src/efuse/rd_sys_part1_data7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA7")
-            .field(
-                "sys_data_part1_7",
-                &format_args!("{}", self.sys_data_part1_7().bits()),
-            )
+            .field("sys_data_part1_7", &self.sys_data_part1_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA7_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA7_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part2_data0.rs b/esp32h2/src/efuse/rd_sys_part2_data0.rs
index 1feb2a9015..47d38ca228 100644
--- a/esp32h2/src/efuse/rd_sys_part2_data0.rs
+++ b/esp32h2/src/efuse/rd_sys_part2_data0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA0")
-            .field(
-                "sys_data_part2_0",
-                &format_args!("{}", self.sys_data_part2_0().bits()),
-            )
+            .field("sys_data_part2_0", &self.sys_data_part2_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA0_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA0_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part2_data1.rs b/esp32h2/src/efuse/rd_sys_part2_data1.rs
index 3d524a829e..52a84368ae 100644
--- a/esp32h2/src/efuse/rd_sys_part2_data1.rs
+++ b/esp32h2/src/efuse/rd_sys_part2_data1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA1")
-            .field(
-                "sys_data_part2_1",
-                &format_args!("{}", self.sys_data_part2_1().bits()),
-            )
+            .field("sys_data_part2_1", &self.sys_data_part2_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA1_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA1_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part2_data2.rs b/esp32h2/src/efuse/rd_sys_part2_data2.rs
index 011eb41ba8..ae963cb031 100644
--- a/esp32h2/src/efuse/rd_sys_part2_data2.rs
+++ b/esp32h2/src/efuse/rd_sys_part2_data2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA2")
-            .field(
-                "sys_data_part2_2",
-                &format_args!("{}", self.sys_data_part2_2().bits()),
-            )
+            .field("sys_data_part2_2", &self.sys_data_part2_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA2_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA2_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part2_data3.rs b/esp32h2/src/efuse/rd_sys_part2_data3.rs
index 68647c349c..a5d4a31845 100644
--- a/esp32h2/src/efuse/rd_sys_part2_data3.rs
+++ b/esp32h2/src/efuse/rd_sys_part2_data3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA3")
-            .field(
-                "sys_data_part2_3",
-                &format_args!("{}", self.sys_data_part2_3().bits()),
-            )
+            .field("sys_data_part2_3", &self.sys_data_part2_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA3_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA3_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part2_data4.rs b/esp32h2/src/efuse/rd_sys_part2_data4.rs
index 23800044fb..4af91484c2 100644
--- a/esp32h2/src/efuse/rd_sys_part2_data4.rs
+++ b/esp32h2/src/efuse/rd_sys_part2_data4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA4")
-            .field(
-                "sys_data_part2_4",
-                &format_args!("{}", self.sys_data_part2_4().bits()),
-            )
+            .field("sys_data_part2_4", &self.sys_data_part2_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA4_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA4_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part2_data5.rs b/esp32h2/src/efuse/rd_sys_part2_data5.rs
index f90b719995..4008d14046 100644
--- a/esp32h2/src/efuse/rd_sys_part2_data5.rs
+++ b/esp32h2/src/efuse/rd_sys_part2_data5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA5")
-            .field(
-                "sys_data_part2_5",
-                &format_args!("{}", self.sys_data_part2_5().bits()),
-            )
+            .field("sys_data_part2_5", &self.sys_data_part2_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA5_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA5_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part2_data6.rs b/esp32h2/src/efuse/rd_sys_part2_data6.rs
index ae9ccbcd43..b9c78c0f10 100644
--- a/esp32h2/src/efuse/rd_sys_part2_data6.rs
+++ b/esp32h2/src/efuse/rd_sys_part2_data6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA6")
-            .field(
-                "sys_data_part2_6",
-                &format_args!("{}", self.sys_data_part2_6().bits()),
-            )
+            .field("sys_data_part2_6", &self.sys_data_part2_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA6_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA6_SPEC {
diff --git a/esp32h2/src/efuse/rd_sys_part2_data7.rs b/esp32h2/src/efuse/rd_sys_part2_data7.rs
index bed90d73b1..3b790bc9a9 100644
--- a/esp32h2/src/efuse/rd_sys_part2_data7.rs
+++ b/esp32h2/src/efuse/rd_sys_part2_data7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA7")
-            .field(
-                "sys_data_part2_7",
-                &format_args!("{}", self.sys_data_part2_7().bits()),
-            )
+            .field("sys_data_part2_7", &self.sys_data_part2_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA7_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA7_SPEC {
diff --git a/esp32h2/src/efuse/rd_tim_conf.rs b/esp32h2/src/efuse/rd_tim_conf.rs
index cf5db0d2ad..0af5a4ac87 100644
--- a/esp32h2/src/efuse/rd_tim_conf.rs
+++ b/esp32h2/src/efuse/rd_tim_conf.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_TIM_CONF")
-            .field("thr_a", &format_args!("{}", self.thr_a().bits()))
-            .field("trd", &format_args!("{}", self.trd().bits()))
-            .field("tsur_a", &format_args!("{}", self.tsur_a().bits()))
-            .field(
-                "read_init_num",
-                &format_args!("{}", self.read_init_num().bits()),
-            )
+            .field("thr_a", &self.thr_a())
+            .field("trd", &self.trd())
+            .field("tsur_a", &self.tsur_a())
+            .field("read_init_num", &self.read_init_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_TIM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures the read hold time."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/rd_usr_data0.rs b/esp32h2/src/efuse/rd_usr_data0.rs
index 4e204bad47..28f2066b68 100644
--- a/esp32h2/src/efuse/rd_usr_data0.rs
+++ b/esp32h2/src/efuse/rd_usr_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA0")
-            .field("usr_data0", &format_args!("{}", self.usr_data0().bits()))
+            .field("usr_data0", &self.usr_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA0_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA0_SPEC {
diff --git a/esp32h2/src/efuse/rd_usr_data1.rs b/esp32h2/src/efuse/rd_usr_data1.rs
index d7c72fc40c..9477844df7 100644
--- a/esp32h2/src/efuse/rd_usr_data1.rs
+++ b/esp32h2/src/efuse/rd_usr_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA1")
-            .field("usr_data1", &format_args!("{}", self.usr_data1().bits()))
+            .field("usr_data1", &self.usr_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA1_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA1_SPEC {
diff --git a/esp32h2/src/efuse/rd_usr_data2.rs b/esp32h2/src/efuse/rd_usr_data2.rs
index 8169877859..aab23fdcd6 100644
--- a/esp32h2/src/efuse/rd_usr_data2.rs
+++ b/esp32h2/src/efuse/rd_usr_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA2")
-            .field("usr_data2", &format_args!("{}", self.usr_data2().bits()))
+            .field("usr_data2", &self.usr_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA2_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA2_SPEC {
diff --git a/esp32h2/src/efuse/rd_usr_data3.rs b/esp32h2/src/efuse/rd_usr_data3.rs
index 287031c261..a60ac76725 100644
--- a/esp32h2/src/efuse/rd_usr_data3.rs
+++ b/esp32h2/src/efuse/rd_usr_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA3")
-            .field("usr_data3", &format_args!("{}", self.usr_data3().bits()))
+            .field("usr_data3", &self.usr_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA3_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA3_SPEC {
diff --git a/esp32h2/src/efuse/rd_usr_data4.rs b/esp32h2/src/efuse/rd_usr_data4.rs
index 59455cc92b..2c176b3b03 100644
--- a/esp32h2/src/efuse/rd_usr_data4.rs
+++ b/esp32h2/src/efuse/rd_usr_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA4")
-            .field("usr_data4", &format_args!("{}", self.usr_data4().bits()))
+            .field("usr_data4", &self.usr_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA4_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA4_SPEC {
diff --git a/esp32h2/src/efuse/rd_usr_data5.rs b/esp32h2/src/efuse/rd_usr_data5.rs
index 497253e518..23dcc42bfc 100644
--- a/esp32h2/src/efuse/rd_usr_data5.rs
+++ b/esp32h2/src/efuse/rd_usr_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA5")
-            .field("usr_data5", &format_args!("{}", self.usr_data5().bits()))
+            .field("usr_data5", &self.usr_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA5_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA5_SPEC {
diff --git a/esp32h2/src/efuse/rd_usr_data6.rs b/esp32h2/src/efuse/rd_usr_data6.rs
index ca48ef1451..3191eb6699 100644
--- a/esp32h2/src/efuse/rd_usr_data6.rs
+++ b/esp32h2/src/efuse/rd_usr_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA6")
-            .field("usr_data6", &format_args!("{}", self.usr_data6().bits()))
+            .field("usr_data6", &self.usr_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA6_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA6_SPEC {
diff --git a/esp32h2/src/efuse/rd_usr_data7.rs b/esp32h2/src/efuse/rd_usr_data7.rs
index 794da1f32e..58df0ecfa5 100644
--- a/esp32h2/src/efuse/rd_usr_data7.rs
+++ b/esp32h2/src/efuse/rd_usr_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA7")
-            .field("usr_data7", &format_args!("{}", self.usr_data7().bits()))
+            .field("usr_data7", &self.usr_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA7_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA7_SPEC {
diff --git a/esp32h2/src/efuse/rd_wr_dis.rs b/esp32h2/src/efuse/rd_wr_dis.rs
index cd942a2900..6dc46e09a0 100644
--- a/esp32h2/src/efuse/rd_wr_dis.rs
+++ b/esp32h2/src/efuse/rd_wr_dis.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_WR_DIS")
-            .field("wr_dis", &format_args!("{}", self.wr_dis().bits()))
+            .field("wr_dis", &self.wr_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_WR_DIS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_wr_dis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_WR_DIS_SPEC;
 impl crate::RegisterSpec for RD_WR_DIS_SPEC {
diff --git a/esp32h2/src/efuse/status.rs b/esp32h2/src/efuse/status.rs
index dbb83cbf32..d88a17411d 100644
--- a/esp32h2/src/efuse/status.rs
+++ b/esp32h2/src/efuse/status.rs
@@ -69,42 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field("otp_load_sw", &format_args!("{}", self.otp_load_sw().bit()))
-            .field(
-                "otp_vddq_c_sync2",
-                &format_args!("{}", self.otp_vddq_c_sync2().bit()),
-            )
-            .field(
-                "otp_strobe_sw",
-                &format_args!("{}", self.otp_strobe_sw().bit()),
-            )
-            .field("otp_csb_sw", &format_args!("{}", self.otp_csb_sw().bit()))
-            .field(
-                "otp_pgenb_sw",
-                &format_args!("{}", self.otp_pgenb_sw().bit()),
-            )
-            .field(
-                "otp_vddq_is_sw",
-                &format_args!("{}", self.otp_vddq_is_sw().bit()),
-            )
-            .field(
-                "blk0_valid_bit_cnt",
-                &format_args!("{}", self.blk0_valid_bit_cnt().bits()),
-            )
-            .field(
-                "cur_ecdsa_blk",
-                &format_args!("{}", self.cur_ecdsa_blk().bits()),
-            )
+            .field("state", &self.state())
+            .field("otp_load_sw", &self.otp_load_sw())
+            .field("otp_vddq_c_sync2", &self.otp_vddq_c_sync2())
+            .field("otp_strobe_sw", &self.otp_strobe_sw())
+            .field("otp_csb_sw", &self.otp_csb_sw())
+            .field("otp_pgenb_sw", &self.otp_pgenb_sw())
+            .field("otp_vddq_is_sw", &self.otp_vddq_is_sw())
+            .field("blk0_valid_bit_cnt", &self.blk0_valid_bit_cnt())
+            .field("cur_ecdsa_blk", &self.cur_ecdsa_blk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32h2/src/efuse/wr_tim_conf0_rs_bypass.rs b/esp32h2/src/efuse/wr_tim_conf0_rs_bypass.rs
index f460ea6d75..9085305267 100644
--- a/esp32h2/src/efuse/wr_tim_conf0_rs_bypass.rs
+++ b/esp32h2/src/efuse/wr_tim_conf0_rs_bypass.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF0_RS_BYPASS")
-            .field(
-                "bypass_rs_correction",
-                &format_args!("{}", self.bypass_rs_correction().bit()),
-            )
-            .field(
-                "bypass_rs_blk_num",
-                &format_args!("{}", self.bypass_rs_blk_num().bits()),
-            )
-            .field(
-                "tpgm_inactive",
-                &format_args!("{}", self.tpgm_inactive().bits()),
-            )
+            .field("bypass_rs_correction", &self.bypass_rs_correction())
+            .field("bypass_rs_blk_num", &self.bypass_rs_blk_num())
+            .field("tpgm_inactive", &self.tpgm_inactive())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF0_RS_BYPASS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to bypass reed solomon correction step."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/wr_tim_conf1.rs b/esp32h2/src/efuse/wr_tim_conf1.rs
index 8dd4a82158..1a50b07633 100644
--- a/esp32h2/src/efuse/wr_tim_conf1.rs
+++ b/esp32h2/src/efuse/wr_tim_conf1.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF1")
-            .field("tsup_a", &format_args!("{}", self.tsup_a().bits()))
-            .field("pwr_on_num", &format_args!("{}", self.pwr_on_num().bits()))
-            .field("thp_a", &format_args!("{}", self.thp_a().bits()))
+            .field("tsup_a", &self.tsup_a())
+            .field("pwr_on_num", &self.pwr_on_num())
+            .field("thp_a", &self.thp_a())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures the programming setup time."]
     #[inline(always)]
diff --git a/esp32h2/src/efuse/wr_tim_conf2.rs b/esp32h2/src/efuse/wr_tim_conf2.rs
index d9c7035316..a89714c107 100644
--- a/esp32h2/src/efuse/wr_tim_conf2.rs
+++ b/esp32h2/src/efuse/wr_tim_conf2.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF2")
-            .field(
-                "pwr_off_num",
-                &format_args!("{}", self.pwr_off_num().bits()),
-            )
-            .field("tpgm", &format_args!("{}", self.tpgm().bits()))
+            .field("pwr_off_num", &self.pwr_off_num())
+            .field("tpgm", &self.tpgm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures the power outage time for VDDQ."]
     #[inline(always)]
diff --git a/esp32h2/src/generic.rs b/esp32h2/src/generic.rs
index a2ae6aa053..45ebed16c4 100644
--- a/esp32h2/src/generic.rs
+++ b/esp32h2/src/generic.rs
@@ -48,7 +48,7 @@ pub trait RegisterSpec {
 #[doc = " Raw field type"]
 pub trait FieldSpec: Sized {
     #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
-    type Ux: Copy + PartialEq + From<Self>;
+    type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
 }
 #[doc = " Marker for fields with fixed values"]
 pub trait IsEnum: FieldSpec {}
@@ -237,6 +237,14 @@ impl<REG: Readable + Writable> Reg<REG> {
         );
     }
 }
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
 #[doc(hidden)]
 pub mod raw;
 #[doc = " Register reader."]
@@ -302,6 +310,11 @@ impl<FI: FieldSpec> FieldReader<FI> {
         self.bits
     }
 }
+impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 impl<FI> PartialEq<FI> for FieldReader<FI>
 where
     FI: FieldSpec + Copy,
@@ -338,10 +351,21 @@ impl<FI> BitReader<FI> {
         self.bit()
     }
 }
+impl<FI> core::fmt::Debug for BitReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 #[doc = " Marker for register/field writers which can take any value of specified width"]
 pub struct Safe;
 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
 pub struct Unsafe;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct Range<const MIN: u64, const MAX: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeFrom<const MIN: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeTo<const MAX: u64>;
 #[doc = " Write field Proxy"]
 pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
     raw::FieldWriter<'a, REG, WI, FI, Safety>;
@@ -393,6 +417,58 @@ where
         unsafe { self.bits(value) }
     }
 }
+impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
+    FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN && value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
 impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
diff --git a/esp32h2/src/gpio/bt_select.rs b/esp32h2/src/gpio/bt_select.rs
index d4bbc43143..d78b414754 100644
--- a/esp32h2/src/gpio/bt_select.rs
+++ b/esp32h2/src/gpio/bt_select.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_SELECT")
-            .field("bt_sel", &format_args!("{}", self.bt_sel().bits()))
+            .field("bt_sel", &self.bt_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_SELECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO bit select register"]
     #[inline(always)]
diff --git a/esp32h2/src/gpio/clock_gate.rs b/esp32h2/src/gpio/clock_gate.rs
index ebd199051e..d2bfefd1b8 100644
--- a/esp32h2/src/gpio/clock_gate.rs
+++ b/esp32h2/src/gpio/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this bit to enable GPIO clock gate"]
     #[inline(always)]
diff --git a/esp32h2/src/gpio/cpusdio_int.rs b/esp32h2/src/gpio/cpusdio_int.rs
index e46e64c2d4..889945a2df 100644
--- a/esp32h2/src/gpio/cpusdio_int.rs
+++ b/esp32h2/src/gpio/cpusdio_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPUSDIO_INT")
-            .field("sdio_int", &format_args!("{}", self.sdio_int().bits()))
+            .field("sdio_int", &self.sdio_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPUSDIO_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO CPUSDIO interrupt status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpusdio_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPUSDIO_INT_SPEC;
 impl crate::RegisterSpec for CPUSDIO_INT_SPEC {
diff --git a/esp32h2/src/gpio/date.rs b/esp32h2/src/gpio/date.rs
index 93dc3e03a2..71c97fccd3 100644
--- a/esp32h2/src/gpio/date.rs
+++ b/esp32h2/src/gpio/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/gpio/enable.rs b/esp32h2/src/gpio/enable.rs
index 72557464c3..2dfdd4f50c 100644
--- a/esp32h2/src/gpio/enable.rs
+++ b/esp32h2/src/gpio/enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO output enable register for GPIO0-31"]
     #[inline(always)]
diff --git a/esp32h2/src/gpio/func_in_sel_cfg.rs b/esp32h2/src/gpio/func_in_sel_cfg.rs
index 53110624d6..797eca798d 100644
--- a/esp32h2/src/gpio/func_in_sel_cfg.rs
+++ b/esp32h2/src/gpio/func_in_sel_cfg.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_IN_SEL_CFG")
-            .field("in_sel", &format_args!("{}", self.in_sel().bits()))
-            .field("in_inv_sel", &format_args!("{}", self.in_inv_sel().bit()))
-            .field("sel", &format_args!("{}", self.sel().bit()))
+            .field("in_sel", &self.in_sel())
+            .field("in_inv_sel", &self.in_inv_sel())
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - set this value: s=0-34: connect GPIO\\[s\\] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level."]
     #[inline(always)]
diff --git a/esp32h2/src/gpio/func_out_sel_cfg.rs b/esp32h2/src/gpio/func_out_sel_cfg.rs
index e564007fd4..e7ce5ee25a 100644
--- a/esp32h2/src/gpio/func_out_sel_cfg.rs
+++ b/esp32h2/src/gpio/func_out_sel_cfg.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_OUT_SEL_CFG")
-            .field("out_sel", &format_args!("{}", self.out_sel().bits()))
-            .field("inv_sel", &format_args!("{}", self.inv_sel().bit()))
-            .field("oen_sel", &format_args!("{}", self.oen_sel().bit()))
-            .field("oen_inv_sel", &format_args!("{}", self.oen_inv_sel().bit()))
+            .field("out_sel", &self.out_sel())
+            .field("inv_sel", &self.inv_sel())
+            .field("oen_sel", &self.oen_sel())
+            .field("oen_inv_sel", &self.oen_inv_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-127: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=128: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
     #[inline(always)]
diff --git a/esp32h2/src/gpio/in_.rs b/esp32h2/src/gpio/in_.rs
index d81f4ace22..420433e5b0 100644
--- a/esp32h2/src/gpio/in_.rs
+++ b/esp32h2/src/gpio/in_.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN")
-            .field("data_next", &format_args!("{}", self.data_next().bits()))
+            .field("data_next", &self.data_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO input register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SPEC;
 impl crate::RegisterSpec for IN_SPEC {
diff --git a/esp32h2/src/gpio/out.rs b/esp32h2/src/gpio/out.rs
index 3e77b03d34..2c8f1cfb13 100644
--- a/esp32h2/src/gpio/out.rs
+++ b/esp32h2/src/gpio/out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT")
-            .field("data_orig", &format_args!("{}", self.data_orig().bits()))
+            .field("data_orig", &self.data_orig())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO output register for GPIO0-31"]
     #[inline(always)]
diff --git a/esp32h2/src/gpio/pcpu_int.rs b/esp32h2/src/gpio/pcpu_int.rs
index b07a90c28e..52727d2345 100644
--- a/esp32h2/src/gpio/pcpu_int.rs
+++ b/esp32h2/src/gpio/pcpu_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_INT")
-            .field("procpu_int", &format_args!("{}", self.procpu_int().bits()))
+            .field("procpu_int", &self.procpu_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO PRO_CPU interrupt status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_INT_SPEC;
 impl crate::RegisterSpec for PCPU_INT_SPEC {
diff --git a/esp32h2/src/gpio/pcpu_nmi_int.rs b/esp32h2/src/gpio/pcpu_nmi_int.rs
index 6105c42de8..729f48eacd 100644
--- a/esp32h2/src/gpio/pcpu_nmi_int.rs
+++ b/esp32h2/src/gpio/pcpu_nmi_int.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_NMI_INT")
-            .field(
-                "procpu_nmi_int",
-                &format_args!("{}", self.procpu_nmi_int().bits()),
-            )
+            .field("procpu_nmi_int", &self.procpu_nmi_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_NMI_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_nmi_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_NMI_INT_SPEC;
 impl crate::RegisterSpec for PCPU_NMI_INT_SPEC {
diff --git a/esp32h2/src/gpio/pin.rs b/esp32h2/src/gpio/pin.rs
index 582513e76d..37d6329326 100644
--- a/esp32h2/src/gpio/pin.rs
+++ b/esp32h2/src/gpio/pin.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN")
-            .field(
-                "sync2_bypass",
-                &format_args!("{}", self.sync2_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field(
-                "sync1_bypass",
-                &format_args!("{}", self.sync1_bypass().bits()),
-            )
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("config", &format_args!("{}", self.config().bits()))
-            .field("int_ena", &format_args!("{}", self.int_ena().bits()))
+            .field("sync2_bypass", &self.sync2_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("sync1_bypass", &self.sync1_bypass())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("config", &self.config())
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
     #[inline(always)]
diff --git a/esp32h2/src/gpio/sdio_select.rs b/esp32h2/src/gpio/sdio_select.rs
index 0f94b5932d..557422a488 100644
--- a/esp32h2/src/gpio/sdio_select.rs
+++ b/esp32h2/src/gpio/sdio_select.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_SELECT")
-            .field("sdio_sel", &format_args!("{}", self.sdio_sel().bits()))
+            .field("sdio_sel", &self.sdio_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_SELECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - GPIO sdio select register"]
     #[inline(always)]
diff --git a/esp32h2/src/gpio/status.rs b/esp32h2/src/gpio/status.rs
index 349c0cde52..d41f06e1a5 100644
--- a/esp32h2/src/gpio/status.rs
+++ b/esp32h2/src/gpio/status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("interrupt", &format_args!("{}", self.interrupt().bits()))
+            .field("interrupt", &self.interrupt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO interrupt status register for GPIO0-31"]
     #[inline(always)]
diff --git a/esp32h2/src/gpio/status_next.rs b/esp32h2/src/gpio/status_next.rs
index 9df3402e32..ea7e8832c2 100644
--- a/esp32h2/src/gpio/status_next.rs
+++ b/esp32h2/src/gpio/status_next.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_NEXT")
-            .field(
-                "status_interrupt_next",
-                &format_args!("{}", self.status_interrupt_next().bits()),
-            )
+            .field("status_interrupt_next", &self.status_interrupt_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_NEXT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt source register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_NEXT_SPEC;
 impl crate::RegisterSpec for STATUS_NEXT_SPEC {
diff --git a/esp32h2/src/gpio/strap.rs b/esp32h2/src/gpio/strap.rs
index dfc141ecfb..3bc90c4409 100644
--- a/esp32h2/src/gpio/strap.rs
+++ b/esp32h2/src/gpio/strap.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STRAP")
-            .field("strapping", &format_args!("{}", self.strapping().bits()))
+            .field("strapping", &self.strapping())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STRAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "pad strapping register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`strap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STRAP_SPEC;
 impl crate::RegisterSpec for STRAP_SPEC {
diff --git a/esp32h2/src/gpio_sd/clock_gate.rs b/esp32h2/src/gpio_sd/clock_gate.rs
index 8c8f04eacf..13ae2d777d 100644
--- a/esp32h2/src/gpio_sd/clock_gate.rs
+++ b/esp32h2/src/gpio_sd/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Clock enable bit of configuration registers for sigma delta modulation."]
     #[inline(always)]
diff --git a/esp32h2/src/gpio_sd/etm_event_ch_cfg.rs b/esp32h2/src/gpio_sd/etm_event_ch_cfg.rs
index a3cc97ebf5..af7d875ba7 100644
--- a/esp32h2/src/gpio_sd/etm_event_ch_cfg.rs
+++ b/esp32h2/src/gpio_sd/etm_event_ch_cfg.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_EVENT_CH_CFG")
-            .field("event_sel", &format_args!("{}", self.event_sel().bits()))
-            .field("event_en", &format_args!("{}", self.event_en().bit()))
+            .field("event_sel", &self.event_sel())
+            .field("event_en", &self.event_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_EVENT_CH_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Etm event channel select gpio."]
     #[inline(always)]
diff --git a/esp32h2/src/gpio_sd/etm_task_p0_cfg.rs b/esp32h2/src/gpio_sd/etm_task_p0_cfg.rs
index fc1eef97f2..40cb413d0f 100644
--- a/esp32h2/src/gpio_sd/etm_task_p0_cfg.rs
+++ b/esp32h2/src/gpio_sd/etm_task_p0_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P0_CFG")
-            .field("gpio0_en", &format_args!("{}", self.gpio0_en().bit()))
-            .field("gpio1_en", &format_args!("{}", self.gpio1_en().bit()))
-            .field("gpio2_en", &format_args!("{}", self.gpio2_en().bit()))
-            .field("gpio3_en", &format_args!("{}", self.gpio3_en().bit()))
-            .field("gpio0_sel", &format_args!("{}", self.gpio0_sel().bits()))
-            .field("gpio1_sel", &format_args!("{}", self.gpio1_sel().bits()))
-            .field("gpio2_sel", &format_args!("{}", self.gpio2_sel().bits()))
-            .field("gpio3_sel", &format_args!("{}", self.gpio3_sel().bits()))
+            .field("gpio0_en", &self.gpio0_en())
+            .field("gpio1_en", &self.gpio1_en())
+            .field("gpio2_en", &self.gpio2_en())
+            .field("gpio3_en", &self.gpio3_en())
+            .field("gpio0_sel", &self.gpio0_sel())
+            .field("gpio1_sel", &self.gpio1_sel())
+            .field("gpio2_sel", &self.gpio2_sel())
+            .field("gpio3_sel", &self.gpio3_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P0_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32h2/src/gpio_sd/etm_task_p1_cfg.rs b/esp32h2/src/gpio_sd/etm_task_p1_cfg.rs
index e9ace39fdb..3092373081 100644
--- a/esp32h2/src/gpio_sd/etm_task_p1_cfg.rs
+++ b/esp32h2/src/gpio_sd/etm_task_p1_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P1_CFG")
-            .field("gpio4_en", &format_args!("{}", self.gpio4_en().bit()))
-            .field("gpio5_en", &format_args!("{}", self.gpio5_en().bit()))
-            .field("gpio6_en", &format_args!("{}", self.gpio6_en().bit()))
-            .field("gpio7_en", &format_args!("{}", self.gpio7_en().bit()))
-            .field("gpio4_sel", &format_args!("{}", self.gpio4_sel().bits()))
-            .field("gpio5_sel", &format_args!("{}", self.gpio5_sel().bits()))
-            .field("gpio6_sel", &format_args!("{}", self.gpio6_sel().bits()))
-            .field("gpio7_sel", &format_args!("{}", self.gpio7_sel().bits()))
+            .field("gpio4_en", &self.gpio4_en())
+            .field("gpio5_en", &self.gpio5_en())
+            .field("gpio6_en", &self.gpio6_en())
+            .field("gpio7_en", &self.gpio7_en())
+            .field("gpio4_sel", &self.gpio4_sel())
+            .field("gpio5_sel", &self.gpio5_sel())
+            .field("gpio6_sel", &self.gpio6_sel())
+            .field("gpio7_sel", &self.gpio7_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P1_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32h2/src/gpio_sd/etm_task_p2_cfg.rs b/esp32h2/src/gpio_sd/etm_task_p2_cfg.rs
index 82670dabaa..63e355d1a0 100644
--- a/esp32h2/src/gpio_sd/etm_task_p2_cfg.rs
+++ b/esp32h2/src/gpio_sd/etm_task_p2_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P2_CFG")
-            .field("gpio8_en", &format_args!("{}", self.gpio8_en().bit()))
-            .field("gpio9_en", &format_args!("{}", self.gpio9_en().bit()))
-            .field("gpio10_en", &format_args!("{}", self.gpio10_en().bit()))
-            .field("gpio11_en", &format_args!("{}", self.gpio11_en().bit()))
-            .field("gpio8_sel", &format_args!("{}", self.gpio8_sel().bits()))
-            .field("gpio9_sel", &format_args!("{}", self.gpio9_sel().bits()))
-            .field("gpio10_sel", &format_args!("{}", self.gpio10_sel().bits()))
-            .field("gpio11_sel", &format_args!("{}", self.gpio11_sel().bits()))
+            .field("gpio8_en", &self.gpio8_en())
+            .field("gpio9_en", &self.gpio9_en())
+            .field("gpio10_en", &self.gpio10_en())
+            .field("gpio11_en", &self.gpio11_en())
+            .field("gpio8_sel", &self.gpio8_sel())
+            .field("gpio9_sel", &self.gpio9_sel())
+            .field("gpio10_sel", &self.gpio10_sel())
+            .field("gpio11_sel", &self.gpio11_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P2_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32h2/src/gpio_sd/etm_task_p3_cfg.rs b/esp32h2/src/gpio_sd/etm_task_p3_cfg.rs
index f7adf3168b..5289dda5a8 100644
--- a/esp32h2/src/gpio_sd/etm_task_p3_cfg.rs
+++ b/esp32h2/src/gpio_sd/etm_task_p3_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P3_CFG")
-            .field("gpio12_en", &format_args!("{}", self.gpio12_en().bit()))
-            .field("gpio13_en", &format_args!("{}", self.gpio13_en().bit()))
-            .field("gpio14_en", &format_args!("{}", self.gpio14_en().bit()))
-            .field("gpio15_en", &format_args!("{}", self.gpio15_en().bit()))
-            .field("gpio12_sel", &format_args!("{}", self.gpio12_sel().bits()))
-            .field("gpio13_sel", &format_args!("{}", self.gpio13_sel().bits()))
-            .field("gpio14_sel", &format_args!("{}", self.gpio14_sel().bits()))
-            .field("gpio15_sel", &format_args!("{}", self.gpio15_sel().bits()))
+            .field("gpio12_en", &self.gpio12_en())
+            .field("gpio13_en", &self.gpio13_en())
+            .field("gpio14_en", &self.gpio14_en())
+            .field("gpio15_en", &self.gpio15_en())
+            .field("gpio12_sel", &self.gpio12_sel())
+            .field("gpio13_sel", &self.gpio13_sel())
+            .field("gpio14_sel", &self.gpio14_sel())
+            .field("gpio15_sel", &self.gpio15_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P3_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32h2/src/gpio_sd/etm_task_p4_cfg.rs b/esp32h2/src/gpio_sd/etm_task_p4_cfg.rs
index c1bf571c18..6d2e7326f4 100644
--- a/esp32h2/src/gpio_sd/etm_task_p4_cfg.rs
+++ b/esp32h2/src/gpio_sd/etm_task_p4_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P4_CFG")
-            .field("gpio16_en", &format_args!("{}", self.gpio16_en().bit()))
-            .field("gpio17_en", &format_args!("{}", self.gpio17_en().bit()))
-            .field("gpio18_en", &format_args!("{}", self.gpio18_en().bit()))
-            .field("gpio19_en", &format_args!("{}", self.gpio19_en().bit()))
-            .field("gpio16_sel", &format_args!("{}", self.gpio16_sel().bits()))
-            .field("gpio17_sel", &format_args!("{}", self.gpio17_sel().bits()))
-            .field("gpio18_sel", &format_args!("{}", self.gpio18_sel().bits()))
-            .field("gpio19_sel", &format_args!("{}", self.gpio19_sel().bits()))
+            .field("gpio16_en", &self.gpio16_en())
+            .field("gpio17_en", &self.gpio17_en())
+            .field("gpio18_en", &self.gpio18_en())
+            .field("gpio19_en", &self.gpio19_en())
+            .field("gpio16_sel", &self.gpio16_sel())
+            .field("gpio17_sel", &self.gpio17_sel())
+            .field("gpio18_sel", &self.gpio18_sel())
+            .field("gpio19_sel", &self.gpio19_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P4_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32h2/src/gpio_sd/etm_task_p5_cfg.rs b/esp32h2/src/gpio_sd/etm_task_p5_cfg.rs
index 036e404fb1..7c3863c69a 100644
--- a/esp32h2/src/gpio_sd/etm_task_p5_cfg.rs
+++ b/esp32h2/src/gpio_sd/etm_task_p5_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P5_CFG")
-            .field("gpio20_en", &format_args!("{}", self.gpio20_en().bit()))
-            .field("gpio21_en", &format_args!("{}", self.gpio21_en().bit()))
-            .field("gpio22_en", &format_args!("{}", self.gpio22_en().bit()))
-            .field("gpio23_en", &format_args!("{}", self.gpio23_en().bit()))
-            .field("gpio20_sel", &format_args!("{}", self.gpio20_sel().bits()))
-            .field("gpio21_sel", &format_args!("{}", self.gpio21_sel().bits()))
-            .field("gpio22_sel", &format_args!("{}", self.gpio22_sel().bits()))
-            .field("gpio23_sel", &format_args!("{}", self.gpio23_sel().bits()))
+            .field("gpio20_en", &self.gpio20_en())
+            .field("gpio21_en", &self.gpio21_en())
+            .field("gpio22_en", &self.gpio22_en())
+            .field("gpio23_en", &self.gpio23_en())
+            .field("gpio20_sel", &self.gpio20_sel())
+            .field("gpio21_sel", &self.gpio21_sel())
+            .field("gpio22_sel", &self.gpio22_sel())
+            .field("gpio23_sel", &self.gpio23_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P5_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32h2/src/gpio_sd/etm_task_p6_cfg.rs b/esp32h2/src/gpio_sd/etm_task_p6_cfg.rs
index 5a0080ebf9..3a188d2401 100644
--- a/esp32h2/src/gpio_sd/etm_task_p6_cfg.rs
+++ b/esp32h2/src/gpio_sd/etm_task_p6_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P6_CFG")
-            .field("gpio24_en", &format_args!("{}", self.gpio24_en().bit()))
-            .field("gpio25_en", &format_args!("{}", self.gpio25_en().bit()))
-            .field("gpio26_en", &format_args!("{}", self.gpio26_en().bit()))
-            .field("gpio27_en", &format_args!("{}", self.gpio27_en().bit()))
-            .field("gpio24_sel", &format_args!("{}", self.gpio24_sel().bits()))
-            .field("gpio25_sel", &format_args!("{}", self.gpio25_sel().bits()))
-            .field("gpio26_sel", &format_args!("{}", self.gpio26_sel().bits()))
-            .field("gpio27_sel", &format_args!("{}", self.gpio27_sel().bits()))
+            .field("gpio24_en", &self.gpio24_en())
+            .field("gpio25_en", &self.gpio25_en())
+            .field("gpio26_en", &self.gpio26_en())
+            .field("gpio27_en", &self.gpio27_en())
+            .field("gpio24_sel", &self.gpio24_sel())
+            .field("gpio25_sel", &self.gpio25_sel())
+            .field("gpio26_sel", &self.gpio26_sel())
+            .field("gpio27_sel", &self.gpio27_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P6_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32h2/src/gpio_sd/glitch_filter_ch.rs b/esp32h2/src/gpio_sd/glitch_filter_ch.rs
index 6058e197b0..fa2b797f10 100644
--- a/esp32h2/src/gpio_sd/glitch_filter_ch.rs
+++ b/esp32h2/src/gpio_sd/glitch_filter_ch.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GLITCH_FILTER_CH")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field(
-                "input_io_num",
-                &format_args!("{}", self.input_io_num().bits()),
-            )
-            .field(
-                "window_thres",
-                &format_args!("{}", self.window_thres().bits()),
-            )
-            .field(
-                "window_width",
-                &format_args!("{}", self.window_width().bits()),
-            )
+            .field("en", &self.en())
+            .field("input_io_num", &self.input_io_num())
+            .field("window_thres", &self.window_thres())
+            .field("window_width", &self.window_width())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GLITCH_FILTER_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Glitch Filter channel enable bit."]
     #[inline(always)]
diff --git a/esp32h2/src/gpio_sd/int_ena.rs b/esp32h2/src/gpio_sd/int_ena.rs
index 9ccee653db..93b452018b 100644
--- a/esp32h2/src/gpio_sd/int_ena.rs
+++ b/esp32h2/src/gpio_sd/int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("pad_comp", &format_args!("{}", self.pad_comp().bit()))
+            .field("pad_comp", &self.pad_comp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Pad compare interrupt enable"]
     #[inline(always)]
diff --git a/esp32h2/src/gpio_sd/int_raw.rs b/esp32h2/src/gpio_sd/int_raw.rs
index a3c7371f74..de6a879671 100644
--- a/esp32h2/src/gpio_sd/int_raw.rs
+++ b/esp32h2/src/gpio_sd/int_raw.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("pad_comp", &format_args!("{}", self.pad_comp().bit()))
+            .field("pad_comp", &self.pad_comp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIOSD interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32h2/src/gpio_sd/int_st.rs b/esp32h2/src/gpio_sd/int_st.rs
index fa4a938b5f..f41e36b6e6 100644
--- a/esp32h2/src/gpio_sd/int_st.rs
+++ b/esp32h2/src/gpio_sd/int_st.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("pad_comp", &format_args!("{}", self.pad_comp().bit()))
+            .field("pad_comp", &self.pad_comp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIOSD interrupt masked register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/gpio_sd/pad_comp_config.rs b/esp32h2/src/gpio_sd/pad_comp_config.rs
index 2e8e3b4d23..0da3c386a5 100644
--- a/esp32h2/src/gpio_sd/pad_comp_config.rs
+++ b/esp32h2/src/gpio_sd/pad_comp_config.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_COMP_CONFIG")
-            .field("xpd_comp", &format_args!("{}", self.xpd_comp().bit()))
-            .field("mode_comp", &format_args!("{}", self.mode_comp().bit()))
-            .field("dref_comp", &format_args!("{}", self.dref_comp().bits()))
-            .field(
-                "zero_det_mode",
-                &format_args!("{}", self.zero_det_mode().bits()),
-            )
+            .field("xpd_comp", &self.xpd_comp())
+            .field("mode_comp", &self.mode_comp())
+            .field("dref_comp", &self.dref_comp())
+            .field("zero_det_mode", &self.zero_det_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_COMP_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Pad compare enable bit."]
     #[inline(always)]
diff --git a/esp32h2/src/gpio_sd/pad_comp_filter.rs b/esp32h2/src/gpio_sd/pad_comp_filter.rs
index 8be559778f..875b5f8baa 100644
--- a/esp32h2/src/gpio_sd/pad_comp_filter.rs
+++ b/esp32h2/src/gpio_sd/pad_comp_filter.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_COMP_FILTER")
-            .field(
-                "zero_det_filter_cnt",
-                &format_args!("{}", self.zero_det_filter_cnt().bits()),
-            )
+            .field("zero_det_filter_cnt", &self.zero_det_filter_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_COMP_FILTER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Zero Detect filter cycle length"]
     #[inline(always)]
diff --git a/esp32h2/src/gpio_sd/sigmadelta.rs b/esp32h2/src/gpio_sd/sigmadelta.rs
index 2cb8973865..1d31bcd5d8 100644
--- a/esp32h2/src/gpio_sd/sigmadelta.rs
+++ b/esp32h2/src/gpio_sd/sigmadelta.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SIGMADELTA")
-            .field("in_", &format_args!("{}", self.in_().bits()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
+            .field("in_", &self.in_())
+            .field("prescale", &self.prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SIGMADELTA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."]
     #[inline(always)]
diff --git a/esp32h2/src/gpio_sd/sigmadelta_misc.rs b/esp32h2/src/gpio_sd/sigmadelta_misc.rs
index b0c196b157..973947d549 100644
--- a/esp32h2/src/gpio_sd/sigmadelta_misc.rs
+++ b/esp32h2/src/gpio_sd/sigmadelta_misc.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SIGMADELTA_MISC")
-            .field(
-                "function_clk_en",
-                &format_args!("{}", self.function_clk_en().bit()),
-            )
-            .field("spi_swap", &format_args!("{}", self.spi_swap().bit()))
+            .field("function_clk_en", &self.function_clk_en())
+            .field("spi_swap", &self.spi_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SIGMADELTA_MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - Clock enable bit of sigma delta modulation."]
     #[inline(always)]
diff --git a/esp32h2/src/gpio_sd/version.rs b/esp32h2/src/gpio_sd/version.rs
index b1369f9a9c..a16affd757 100644
--- a/esp32h2/src/gpio_sd/version.rs
+++ b/esp32h2/src/gpio_sd/version.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field(
-                "gpio_sd_date",
-                &format_args!("{}", self.gpio_sd_date().bits()),
-            )
+            .field("gpio_sd_date", &self.gpio_sd_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register."]
     #[inline(always)]
diff --git a/esp32h2/src/hmac/date.rs b/esp32h2/src/hmac/date.rs
index dae408e040..451431dcfa 100644
--- a/esp32h2/src/hmac/date.rs
+++ b/esp32h2/src/hmac/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/hmac/query_busy.rs b/esp32h2/src/hmac/query_busy.rs
index b2162c1fb3..6f817e76f4 100644
--- a/esp32h2/src/hmac/query_busy.rs
+++ b/esp32h2/src/hmac/query_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_BUSY")
-            .field("busy_state", &format_args!("{}", self.busy_state().bit()))
+            .field("busy_state", &self.busy_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Busy register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_BUSY_SPEC;
 impl crate::RegisterSpec for QUERY_BUSY_SPEC {
diff --git a/esp32h2/src/hmac/query_error.rs b/esp32h2/src/hmac/query_error.rs
index dccd8dd32f..8f5b2d284b 100644
--- a/esp32h2/src/hmac/query_error.rs
+++ b/esp32h2/src/hmac/query_error.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_ERROR")
-            .field("query_check", &format_args!("{}", self.query_check().bit()))
+            .field("query_check", &self.query_check())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_ERROR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Error register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_error::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_ERROR_SPEC;
 impl crate::RegisterSpec for QUERY_ERROR_SPEC {
diff --git a/esp32h2/src/hmac/rd_result_mem.rs b/esp32h2/src/hmac/rd_result_mem.rs
index e93fc1892c..15ad43ddc6 100644
--- a/esp32h2/src/hmac/rd_result_mem.rs
+++ b/esp32h2/src/hmac/rd_result_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RESULT_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Result from upstream.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_result_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rd_result_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RESULT_MEM_SPEC;
diff --git a/esp32h2/src/hmac/wr_message_mem.rs b/esp32h2/src/hmac/wr_message_mem.rs
index e4eda3e0e5..2779a44011 100644
--- a/esp32h2/src/hmac/wr_message_mem.rs
+++ b/esp32h2/src/hmac/wr_message_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_MESSAGE_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Message block memory.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_message_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_message_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WR_MESSAGE_MEM_SPEC;
diff --git a/esp32h2/src/hp_apm/clock_gate.rs b/esp32h2/src/hp_apm/clock_gate.rs
index 0ea9f4e7a3..0260550609 100644
--- a/esp32h2/src/hp_apm/clock_gate.rs
+++ b/esp32h2/src/hp_apm/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_clk_en"]
     #[inline(always)]
diff --git a/esp32h2/src/hp_apm/date.rs b/esp32h2/src/hp_apm/date.rs
index fb73a9a02f..3825783dcf 100644
--- a/esp32h2/src/hp_apm/date.rs
+++ b/esp32h2/src/hp_apm/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/hp_apm/func_ctrl.rs b/esp32h2/src/hp_apm/func_ctrl.rs
index aba1980447..18d2d1b15d 100644
--- a/esp32h2/src/hp_apm/func_ctrl.rs
+++ b/esp32h2/src/hp_apm/func_ctrl.rs
@@ -47,31 +47,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_CTRL")
-            .field(
-                "m0_pms_func_en",
-                &format_args!("{}", self.m0_pms_func_en().bit()),
-            )
-            .field(
-                "m1_pms_func_en",
-                &format_args!("{}", self.m1_pms_func_en().bit()),
-            )
-            .field(
-                "m2_pms_func_en",
-                &format_args!("{}", self.m2_pms_func_en().bit()),
-            )
-            .field(
-                "m3_pms_func_en",
-                &format_args!("{}", self.m3_pms_func_en().bit()),
-            )
+            .field("m0_pms_func_en", &self.m0_pms_func_en())
+            .field("m1_pms_func_en", &self.m1_pms_func_en())
+            .field("m2_pms_func_en", &self.m2_pms_func_en())
+            .field("m3_pms_func_en", &self.m3_pms_func_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "PMS M(0-3) function enable"]
     #[doc = ""]
diff --git a/esp32h2/src/hp_apm/int_en.rs b/esp32h2/src/hp_apm/int_en.rs
index 552bed269a..8217d81fd4 100644
--- a/esp32h2/src/hp_apm/int_en.rs
+++ b/esp32h2/src/hp_apm/int_en.rs
@@ -47,19 +47,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_EN")
-            .field("m0_apm", &format_args!("{}", self.m0_apm().bit()))
-            .field("m1_apm", &format_args!("{}", self.m1_apm().bit()))
-            .field("m2_apm", &format_args!("{}", self.m2_apm().bit()))
-            .field("m3_apm", &format_args!("{}", self.m3_apm().bit()))
+            .field("m0_apm", &self.m0_apm())
+            .field("m1_apm", &self.m1_apm())
+            .field("m2_apm", &self.m2_apm())
+            .field("m3_apm", &self.m3_apm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "APM M(0-3) interrupt enable"]
     #[doc = ""]
diff --git a/esp32h2/src/hp_apm/m/exception_info0.rs b/esp32h2/src/hp_apm/m/exception_info0.rs
index e69de2ef75..2d06741a86 100644
--- a/esp32h2/src/hp_apm/m/exception_info0.rs
+++ b/esp32h2/src/hp_apm/m/exception_info0.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXCEPTION_INFO0")
-            .field(
-                "exception_region",
-                &format_args!("{}", self.exception_region().bits()),
-            )
-            .field(
-                "exception_mode",
-                &format_args!("{}", self.exception_mode().bits()),
-            )
-            .field(
-                "exception_id",
-                &format_args!("{}", self.exception_id().bits()),
-            )
+            .field("exception_region", &self.exception_region())
+            .field("exception_mode", &self.exception_mode())
+            .field("exception_id", &self.exception_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXCEPTION_INFO0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 exception_info0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exception_info0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXCEPTION_INFO0_SPEC;
 impl crate::RegisterSpec for EXCEPTION_INFO0_SPEC {
diff --git a/esp32h2/src/hp_apm/m/exception_info1.rs b/esp32h2/src/hp_apm/m/exception_info1.rs
index 1a6977abc5..cb3b39d257 100644
--- a/esp32h2/src/hp_apm/m/exception_info1.rs
+++ b/esp32h2/src/hp_apm/m/exception_info1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXCEPTION_INFO1")
-            .field(
-                "exception_addr",
-                &format_args!("{}", self.exception_addr().bits()),
-            )
+            .field("exception_addr", &self.exception_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXCEPTION_INFO1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 exception_info1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exception_info1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXCEPTION_INFO1_SPEC;
 impl crate::RegisterSpec for EXCEPTION_INFO1_SPEC {
diff --git a/esp32h2/src/hp_apm/m/status.rs b/esp32h2/src/hp_apm/m/status.rs
index 6a5c666bbf..3e275a91ca 100644
--- a/esp32h2/src/hp_apm/m/status.rs
+++ b/esp32h2/src/hp_apm/m/status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field(
-                "exception_status",
-                &format_args!("{}", self.exception_status().bits()),
-            )
+            .field("exception_status", &self.exception_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32h2/src/hp_apm/region/addr_end.rs b/esp32h2/src/hp_apm/region/addr_end.rs
index 8940485f11..db15e1b66a 100644
--- a/esp32h2/src/hp_apm/region/addr_end.rs
+++ b/esp32h2/src/hp_apm/region/addr_end.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR_END")
-            .field("addr_end", &format_args!("{}", self.addr_end().bits()))
+            .field("addr_end", &self.addr_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_END_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - End address of region0"]
     #[inline(always)]
diff --git a/esp32h2/src/hp_apm/region/addr_start.rs b/esp32h2/src/hp_apm/region/addr_start.rs
index 15654e8830..21d743f5e2 100644
--- a/esp32h2/src/hp_apm/region/addr_start.rs
+++ b/esp32h2/src/hp_apm/region/addr_start.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR_START")
-            .field("addr_start", &format_args!("{}", self.addr_start().bits()))
+            .field("addr_start", &self.addr_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_START_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Start address of region0"]
     #[inline(always)]
diff --git a/esp32h2/src/hp_apm/region/pms_attr.rs b/esp32h2/src/hp_apm/region/pms_attr.rs
index 30b2486d8c..a929b05fa9 100644
--- a/esp32h2/src/hp_apm/region/pms_attr.rs
+++ b/esp32h2/src/hp_apm/region/pms_attr.rs
@@ -110,24 +110,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMS_ATTR")
-            .field("r0_pms_x", &format_args!("{}", self.r0_pms_x().bit()))
-            .field("r1_pms_x", &format_args!("{}", self.r1_pms_x().bit()))
-            .field("r2_pms_x", &format_args!("{}", self.r2_pms_x().bit()))
-            .field("r0_pms_w", &format_args!("{}", self.r0_pms_w().bit()))
-            .field("r1_pms_w", &format_args!("{}", self.r1_pms_w().bit()))
-            .field("r2_pms_w", &format_args!("{}", self.r2_pms_w().bit()))
-            .field("r0_pms_r", &format_args!("{}", self.r0_pms_r().bit()))
-            .field("r1_pms_r", &format_args!("{}", self.r1_pms_r().bit()))
-            .field("r2_pms_r", &format_args!("{}", self.r2_pms_r().bit()))
+            .field("r0_pms_x", &self.r0_pms_x())
+            .field("r1_pms_x", &self.r1_pms_x())
+            .field("r2_pms_x", &self.r2_pms_x())
+            .field("r0_pms_w", &self.r0_pms_w())
+            .field("r1_pms_w", &self.r1_pms_w())
+            .field("r2_pms_w", &self.r2_pms_w())
+            .field("r0_pms_r", &self.r0_pms_r())
+            .field("r1_pms_r", &self.r1_pms_r())
+            .field("r2_pms_r", &self.r2_pms_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMS_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Region execute authority in REE_MODE(0-2)"]
     #[doc = ""]
diff --git a/esp32h2/src/hp_apm/region_filter_en.rs b/esp32h2/src/hp_apm/region_filter_en.rs
index 337139e986..b0d863e59e 100644
--- a/esp32h2/src/hp_apm/region_filter_en.rs
+++ b/esp32h2/src/hp_apm/region_filter_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGION_FILTER_EN")
-            .field(
-                "region_filter_en",
-                &format_args!("{}", self.region_filter_en().bits()),
-            )
+            .field("region_filter_en", &self.region_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_FILTER_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Region filter enable"]
     #[inline(always)]
diff --git a/esp32h2/src/hp_sys/clock_gate.rs b/esp32h2/src/hp_sys/clock_gate.rs
index 8cdc737fd3..eaa719ae00 100644
--- a/esp32h2/src/hp_sys/clock_gate.rs
+++ b/esp32h2/src/hp_sys/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit as 1 to force on clock gating."]
     #[inline(always)]
diff --git a/esp32h2/src/hp_sys/cpu_peri_timeout_addr.rs b/esp32h2/src/hp_sys/cpu_peri_timeout_addr.rs
index 743f7e48d1..a6d4ad0443 100644
--- a/esp32h2/src/hp_sys/cpu_peri_timeout_addr.rs
+++ b/esp32h2/src/hp_sys/cpu_peri_timeout_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERI_TIMEOUT_ADDR")
-            .field(
-                "cpu_peri_timeout_addr",
-                &format_args!("{}", self.cpu_peri_timeout_addr().bits()),
-            )
+            .field("cpu_peri_timeout_addr", &self.cpu_peri_timeout_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_TIMEOUT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CPU_PERI_TIMEOUT_ADDR register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_peri_timeout_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPU_PERI_TIMEOUT_ADDR_SPEC;
 impl crate::RegisterSpec for CPU_PERI_TIMEOUT_ADDR_SPEC {
diff --git a/esp32h2/src/hp_sys/cpu_peri_timeout_conf.rs b/esp32h2/src/hp_sys/cpu_peri_timeout_conf.rs
index f9d50fef91..ba455a9773 100644
--- a/esp32h2/src/hp_sys/cpu_peri_timeout_conf.rs
+++ b/esp32h2/src/hp_sys/cpu_peri_timeout_conf.rs
@@ -28,23 +28,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERI_TIMEOUT_CONF")
-            .field(
-                "cpu_peri_timeout_thres",
-                &format_args!("{}", self.cpu_peri_timeout_thres().bits()),
-            )
+            .field("cpu_peri_timeout_thres", &self.cpu_peri_timeout_thres())
             .field(
                 "cpu_peri_timeout_protect_en",
-                &format_args!("{}", self.cpu_peri_timeout_protect_en().bit()),
+                &self.cpu_peri_timeout_protect_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_TIMEOUT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain."]
     #[inline(always)]
diff --git a/esp32h2/src/hp_sys/cpu_peri_timeout_uid.rs b/esp32h2/src/hp_sys/cpu_peri_timeout_uid.rs
index e7fd7d84d2..d54480baf9 100644
--- a/esp32h2/src/hp_sys/cpu_peri_timeout_uid.rs
+++ b/esp32h2/src/hp_sys/cpu_peri_timeout_uid.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERI_TIMEOUT_UID")
-            .field(
-                "cpu_peri_timeout_uid",
-                &format_args!("{}", self.cpu_peri_timeout_uid().bits()),
-            )
+            .field("cpu_peri_timeout_uid", &self.cpu_peri_timeout_uid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_TIMEOUT_UID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CPU_PERI_TIMEOUT_UID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_peri_timeout_uid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPU_PERI_TIMEOUT_UID_SPEC;
 impl crate::RegisterSpec for CPU_PERI_TIMEOUT_UID_SPEC {
diff --git a/esp32h2/src/hp_sys/date.rs b/esp32h2/src/hp_sys/date.rs
index 0c86bde82c..ba76ea3397 100644
--- a/esp32h2/src/hp_sys/date.rs
+++ b/esp32h2/src/hp_sys/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/hp_sys/external_device_encrypt_decrypt_control.rs b/esp32h2/src/hp_sys/external_device_encrypt_decrypt_control.rs
index 40172694c9..db0f9f8016 100644
--- a/esp32h2/src/hp_sys/external_device_encrypt_decrypt_control.rs
+++ b/esp32h2/src/hp_sys/external_device_encrypt_decrypt_control.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL")
             .field(
                 "enable_spi_manual_encrypt",
-                &format_args!("{}", self.enable_spi_manual_encrypt().bit()),
+                &self.enable_spi_manual_encrypt(),
             )
             .field(
                 "enable_download_db_encrypt",
-                &format_args!("{}", self.enable_download_db_encrypt().bit()),
+                &self.enable_download_db_encrypt(),
             )
             .field(
                 "enable_download_g0cb_decrypt",
-                &format_args!("{}", self.enable_download_g0cb_decrypt().bit()),
+                &self.enable_download_g0cb_decrypt(),
             )
             .field(
                 "enable_download_manual_encrypt",
-                &format_args!("{}", self.enable_download_manual_encrypt().bit()),
+                &self.enable_download_manual_encrypt(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode."]
     #[inline(always)]
diff --git a/esp32h2/src/hp_sys/hp_peri_timeout_addr.rs b/esp32h2/src/hp_sys/hp_peri_timeout_addr.rs
index b9f2328aff..8f0dbec847 100644
--- a/esp32h2/src/hp_sys/hp_peri_timeout_addr.rs
+++ b/esp32h2/src/hp_sys/hp_peri_timeout_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_PERI_TIMEOUT_ADDR")
-            .field(
-                "hp_peri_timeout_addr",
-                &format_args!("{}", self.hp_peri_timeout_addr().bits()),
-            )
+            .field("hp_peri_timeout_addr", &self.hp_peri_timeout_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_PERI_TIMEOUT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "HP_PERI_TIMEOUT_ADDR register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_peri_timeout_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HP_PERI_TIMEOUT_ADDR_SPEC;
 impl crate::RegisterSpec for HP_PERI_TIMEOUT_ADDR_SPEC {
diff --git a/esp32h2/src/hp_sys/hp_peri_timeout_conf.rs b/esp32h2/src/hp_sys/hp_peri_timeout_conf.rs
index 996e76f801..6aefa49a65 100644
--- a/esp32h2/src/hp_sys/hp_peri_timeout_conf.rs
+++ b/esp32h2/src/hp_sys/hp_peri_timeout_conf.rs
@@ -28,23 +28,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_PERI_TIMEOUT_CONF")
-            .field(
-                "hp_peri_timeout_thres",
-                &format_args!("{}", self.hp_peri_timeout_thres().bits()),
-            )
+            .field("hp_peri_timeout_thres", &self.hp_peri_timeout_thres())
             .field(
                 "hp_peri_timeout_protect_en",
-                &format_args!("{}", self.hp_peri_timeout_protect_en().bit()),
+                &self.hp_peri_timeout_protect_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_PERI_TIMEOUT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain."]
     #[inline(always)]
diff --git a/esp32h2/src/hp_sys/hp_peri_timeout_uid.rs b/esp32h2/src/hp_sys/hp_peri_timeout_uid.rs
index 09322dca5a..bf653e4774 100644
--- a/esp32h2/src/hp_sys/hp_peri_timeout_uid.rs
+++ b/esp32h2/src/hp_sys/hp_peri_timeout_uid.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_PERI_TIMEOUT_UID")
-            .field(
-                "hp_peri_timeout_uid",
-                &format_args!("{}", self.hp_peri_timeout_uid().bits()),
-            )
+            .field("hp_peri_timeout_uid", &self.hp_peri_timeout_uid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_PERI_TIMEOUT_UID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "HP_PERI_TIMEOUT_UID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hp_peri_timeout_uid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HP_PERI_TIMEOUT_UID_SPEC;
 impl crate::RegisterSpec for HP_PERI_TIMEOUT_UID_SPEC {
diff --git a/esp32h2/src/hp_sys/mem_test_conf.rs b/esp32h2/src/hp_sys/mem_test_conf.rs
index ab20d50671..34a3bfdfa3 100644
--- a/esp32h2/src/hp_sys/mem_test_conf.rs
+++ b/esp32h2/src/hp_sys/mem_test_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_TEST_CONF")
-            .field(
-                "hp_mem_wpulse",
-                &format_args!("{}", self.hp_mem_wpulse().bits()),
-            )
-            .field("hp_mem_wa", &format_args!("{}", self.hp_mem_wa().bits()))
-            .field("hp_mem_ra", &format_args!("{}", self.hp_mem_ra().bits()))
-            .field("hp_mem_rm", &format_args!("{}", self.hp_mem_rm().bits()))
-            .field("rom_rm", &format_args!("{}", self.rom_rm().bits()))
+            .field("hp_mem_wpulse", &self.hp_mem_wpulse())
+            .field("hp_mem_wa", &self.hp_mem_wa())
+            .field("hp_mem_ra", &self.hp_mem_ra())
+            .field("hp_mem_rm", &self.hp_mem_rm())
+            .field("rom_rm", &self.rom_rm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_TEST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - This field controls hp system memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V operating Voltage."]
     #[inline(always)]
diff --git a/esp32h2/src/hp_sys/rnd_eco.rs b/esp32h2/src/hp_sys/rnd_eco.rs
index cf663fec03..3163d9f0b8 100644
--- a/esp32h2/src/hp_sys/rnd_eco.rs
+++ b/esp32h2/src/hp_sys/rnd_eco.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO")
-            .field("redcy_ena", &format_args!("{}", self.redcy_ena().bit()))
-            .field(
-                "redcy_result",
-                &format_args!("{}", self.redcy_result().bit()),
-            )
+            .field("redcy_ena", &self.redcy_ena())
+            .field("redcy_result", &self.redcy_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Only reserved for ECO."]
     #[inline(always)]
diff --git a/esp32h2/src/hp_sys/rnd_eco_high.rs b/esp32h2/src/hp_sys/rnd_eco_high.rs
index d2138667f2..acb852af6d 100644
--- a/esp32h2/src/hp_sys/rnd_eco_high.rs
+++ b/esp32h2/src/hp_sys/rnd_eco_high.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_HIGH")
-            .field("redcy_high", &format_args!("{}", self.redcy_high().bits()))
+            .field("redcy_high", &self.redcy_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Only reserved for ECO."]
     #[inline(always)]
diff --git a/esp32h2/src/hp_sys/rnd_eco_low.rs b/esp32h2/src/hp_sys/rnd_eco_low.rs
index 6accf663f9..f3dcb2ff4b 100644
--- a/esp32h2/src/hp_sys/rnd_eco_low.rs
+++ b/esp32h2/src/hp_sys/rnd_eco_low.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_LOW")
-            .field("redcy_low", &format_args!("{}", self.redcy_low().bits()))
+            .field("redcy_low", &self.redcy_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Only reserved for ECO."]
     #[inline(always)]
diff --git a/esp32h2/src/hp_sys/rom_table.rs b/esp32h2/src/hp_sys/rom_table.rs
index 38b28290c0..1db8b39582 100644
--- a/esp32h2/src/hp_sys/rom_table.rs
+++ b/esp32h2/src/hp_sys/rom_table.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_TABLE")
-            .field("rom_table", &format_args!("{}", self.rom_table().bits()))
+            .field("rom_table", &self.rom_table())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_TABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - XXXX"]
     #[inline(always)]
diff --git a/esp32h2/src/hp_sys/rom_table_lock.rs b/esp32h2/src/hp_sys/rom_table_lock.rs
index b83bdf0cb9..ea4b9e9375 100644
--- a/esp32h2/src/hp_sys/rom_table_lock.rs
+++ b/esp32h2/src/hp_sys/rom_table_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_TABLE_LOCK")
-            .field(
-                "rom_table_lock",
-                &format_args!("{}", self.rom_table_lock().bit()),
-            )
+            .field("rom_table_lock", &self.rom_table_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_TABLE_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - XXXX"]
     #[inline(always)]
diff --git a/esp32h2/src/hp_sys/sec_dpa_conf.rs b/esp32h2/src/hp_sys/sec_dpa_conf.rs
index ecc8448e07..d5b7dbbf25 100644
--- a/esp32h2/src/hp_sys/sec_dpa_conf.rs
+++ b/esp32h2/src/hp_sys/sec_dpa_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_DPA_CONF")
-            .field(
-                "sec_dpa_level",
-                &format_args!("{}", self.sec_dpa_level().bits()),
-            )
-            .field(
-                "sec_dpa_cfg_sel",
-                &format_args!("{}", self.sec_dpa_cfg_sel().bit()),
-            )
+            .field("sec_dpa_level", &self.sec_dpa_level())
+            .field("sec_dpa_cfg_sel", &self.sec_dpa_cfg_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_DPA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger the number, the stronger the ability to resist DPA attacks and the higher the security level, but it will increase the computational overhead of the hardware crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0."]
     #[inline(always)]
diff --git a/esp32h2/src/hp_sys/sram_usage_conf.rs b/esp32h2/src/hp_sys/sram_usage_conf.rs
index 6f011c6944..62f0f11471 100644
--- a/esp32h2/src/hp_sys/sram_usage_conf.rs
+++ b/esp32h2/src/hp_sys/sram_usage_conf.rs
@@ -33,21 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_USAGE_CONF")
-            .field("sram_usage", &format_args!("{}", self.sram_usage().bits()))
-            .field(
-                "mac_dump_alloc",
-                &format_args!("{}", self.mac_dump_alloc().bits()),
-            )
-            .field("cache_usage", &format_args!("{}", self.cache_usage().bit()))
+            .field("sram_usage", &self.sram_usage())
+            .field("mac_dump_alloc", &self.mac_dump_alloc())
+            .field("cache_usage", &self.cache_usage())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_USAGE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 10:14 - 0: cpu use hp-memory. 1: mac-dump accessing hp-memory."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/clk_conf.rs b/esp32h2/src/i2c0/clk_conf.rs
index 0c369fb990..8575bb85bf 100644
--- a/esp32h2/src/i2c0/clk_conf.rs
+++ b/esp32h2/src/i2c0/clk_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bit()))
-            .field("sclk_active", &format_args!("{}", self.sclk_active().bit()))
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_active", &self.sclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/comd.rs b/esp32h2/src/i2c0/comd.rs
index 6f909ae304..980d858d87 100644
--- a/esp32h2/src/i2c0/comd.rs
+++ b/esp32h2/src/i2c0/comd.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMD")
-            .field("command", &format_args!("{}", self.command().bits()))
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This is the content of command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/ctr.rs b/esp32h2/src/i2c0/ctr.rs
index 3ba4f612c1..4500b14379 100644
--- a/esp32h2/src/i2c0/ctr.rs
+++ b/esp32h2/src/i2c0/ctr.rs
@@ -122,57 +122,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTR")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field(
-                "sample_scl_level",
-                &format_args!("{}", self.sample_scl_level().bit()),
-            )
-            .field(
-                "rx_full_ack_level",
-                &format_args!("{}", self.rx_full_ack_level().bit()),
-            )
-            .field("ms_mode", &format_args!("{}", self.ms_mode().bit()))
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "arbitration_en",
-                &format_args!("{}", self.arbitration_en().bit()),
-            )
-            .field(
-                "slv_tx_auto_start_en",
-                &format_args!("{}", self.slv_tx_auto_start_en().bit()),
-            )
-            .field(
-                "addr_10bit_rw_check_en",
-                &format_args!("{}", self.addr_10bit_rw_check_en().bit()),
-            )
-            .field(
-                "addr_broadcasting_en",
-                &format_args!("{}", self.addr_broadcasting_en().bit()),
-            )
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("sample_scl_level", &self.sample_scl_level())
+            .field("rx_full_ack_level", &self.rx_full_ack_level())
+            .field("ms_mode", &self.ms_mode())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("clk_en", &self.clk_en())
+            .field("arbitration_en", &self.arbitration_en())
+            .field("slv_tx_auto_start_en", &self.slv_tx_auto_start_en())
+            .field("addr_10bit_rw_check_en", &self.addr_10bit_rw_check_en())
+            .field("addr_broadcasting_en", &self.addr_broadcasting_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: direct output, 0: open drain output."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/data.rs b/esp32h2/src/i2c0/data.rs
index 098982488f..ffd32b29d3 100644
--- a/esp32h2/src/i2c0/data.rs
+++ b/esp32h2/src/i2c0/data.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field("fifo_rdata", &format_args!("{}", self.fifo_rdata().bits()))
+            .field("fifo_rdata", &self.fifo_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value of rx FIFO read data."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/date.rs b/esp32h2/src/i2c0/date.rs
index f0a0b291ee..2541eeb94a 100644
--- a/esp32h2/src/i2c0/date.rs
+++ b/esp32h2/src/i2c0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/i2c0/fifo_conf.rs b/esp32h2/src/i2c0/fifo_conf.rs
index a676b90a14..92deed8594 100644
--- a/esp32h2/src/i2c0/fifo_conf.rs
+++ b/esp32h2/src/i2c0/fifo_conf.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CONF")
-            .field(
-                "rxfifo_wm_thrhd",
-                &format_args!("{}", self.rxfifo_wm_thrhd().bits()),
-            )
-            .field(
-                "txfifo_wm_thrhd",
-                &format_args!("{}", self.txfifo_wm_thrhd().bits()),
-            )
-            .field("nonfifo_en", &format_args!("{}", self.nonfifo_en().bit()))
-            .field(
-                "fifo_addr_cfg_en",
-                &format_args!("{}", self.fifo_addr_cfg_en().bit()),
-            )
-            .field("rx_fifo_rst", &format_args!("{}", self.rx_fifo_rst().bit()))
-            .field("tx_fifo_rst", &format_args!("{}", self.tx_fifo_rst().bit()))
-            .field("fifo_prt_en", &format_args!("{}", self.fifo_prt_en().bit()))
+            .field("rxfifo_wm_thrhd", &self.rxfifo_wm_thrhd())
+            .field("txfifo_wm_thrhd", &self.txfifo_wm_thrhd())
+            .field("nonfifo_en", &self.nonfifo_en())
+            .field("fifo_addr_cfg_en", &self.fifo_addr_cfg_en())
+            .field("rx_fifo_rst", &self.rx_fifo_rst())
+            .field("tx_fifo_rst", &self.tx_fifo_rst())
+            .field("fifo_prt_en", &self.fifo_prt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[4:0\\], reg_rxfifo_wm_int_raw bit will be valid."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/fifo_st.rs b/esp32h2/src/i2c0/fifo_st.rs
index 40f2594a2b..03188e5485 100644
--- a/esp32h2/src/i2c0/fifo_st.rs
+++ b/esp32h2/src/i2c0/fifo_st.rs
@@ -41,35 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_ST")
-            .field(
-                "rxfifo_raddr",
-                &format_args!("{}", self.rxfifo_raddr().bits()),
-            )
-            .field(
-                "rxfifo_waddr",
-                &format_args!("{}", self.rxfifo_waddr().bits()),
-            )
-            .field(
-                "txfifo_raddr",
-                &format_args!("{}", self.txfifo_raddr().bits()),
-            )
-            .field(
-                "txfifo_waddr",
-                &format_args!("{}", self.txfifo_waddr().bits()),
-            )
-            .field(
-                "slave_rw_point",
-                &format_args!("{}", self.slave_rw_point().bits()),
-            )
+            .field("rxfifo_raddr", &self.rxfifo_raddr())
+            .field("rxfifo_waddr", &self.rxfifo_waddr())
+            .field("txfifo_raddr", &self.txfifo_raddr())
+            .field("txfifo_waddr", &self.txfifo_waddr())
+            .field("slave_rw_point", &self.slave_rw_point())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "FIFO status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_ST_SPEC;
 impl crate::RegisterSpec for FIFO_ST_SPEC {
diff --git a/esp32h2/src/i2c0/filter_cfg.rs b/esp32h2/src/i2c0/filter_cfg.rs
index b05ae9a4bf..98bdaa5979 100644
--- a/esp32h2/src/i2c0/filter_cfg.rs
+++ b/esp32h2/src/i2c0/filter_cfg.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CFG")
-            .field(
-                "scl_filter_thres",
-                &format_args!("{}", self.scl_filter_thres().bits()),
-            )
-            .field(
-                "sda_filter_thres",
-                &format_args!("{}", self.sda_filter_thres().bits()),
-            )
-            .field(
-                "scl_filter_en",
-                &format_args!("{}", self.scl_filter_en().bit()),
-            )
-            .field(
-                "sda_filter_en",
-                &format_args!("{}", self.sda_filter_en().bit()),
-            )
+            .field("scl_filter_thres", &self.scl_filter_thres())
+            .field("sda_filter_thres", &self.sda_filter_thres())
+            .field("scl_filter_en", &self.scl_filter_en())
+            .field("sda_filter_en", &self.sda_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/int_ena.rs b/esp32h2/src/i2c0/int_ena.rs
index 603538eb38..d4fcbf46ce 100644
--- a/esp32h2/src/i2c0/int_ena.rs
+++ b/esp32h2/src/i2c0/int_ena.rs
@@ -179,58 +179,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
-            .field(
-                "general_call",
-                &format_args!("{}", self.general_call().bit()),
-            )
-            .field(
-                "slave_addr_unmatch",
-                &format_args!("{}", self.slave_addr_unmatch().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
+            .field("general_call", &self.general_call())
+            .field("slave_addr_unmatch", &self.slave_addr_unmatch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/int_raw.rs b/esp32h2/src/i2c0/int_raw.rs
index d6d6eff429..30e6675e53 100644
--- a/esp32h2/src/i2c0/int_raw.rs
+++ b/esp32h2/src/i2c0/int_raw.rs
@@ -139,58 +139,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
-            .field(
-                "general_call",
-                &format_args!("{}", self.general_call().bit()),
-            )
-            .field(
-                "slave_addr_unmatch",
-                &format_args!("{}", self.slave_addr_unmatch().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
+            .field("general_call", &self.general_call())
+            .field("slave_addr_unmatch", &self.slave_addr_unmatch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32h2/src/i2c0/int_st.rs b/esp32h2/src/i2c0/int_st.rs
index 553dd4fdef..6a88399e28 100644
--- a/esp32h2/src/i2c0/int_st.rs
+++ b/esp32h2/src/i2c0/int_st.rs
@@ -139,58 +139,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
-            .field(
-                "general_call",
-                &format_args!("{}", self.general_call().bit()),
-            )
-            .field(
-                "slave_addr_unmatch",
-                &format_args!("{}", self.slave_addr_unmatch().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
+            .field("general_call", &self.general_call())
+            .field("slave_addr_unmatch", &self.slave_addr_unmatch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of captured I2C communication events\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/i2c0/rxfifo_start_addr.rs b/esp32h2/src/i2c0/rxfifo_start_addr.rs
index 634e8c8360..be2fa3cb09 100644
--- a/esp32h2/src/i2c0/rxfifo_start_addr.rs
+++ b/esp32h2/src/i2c0/rxfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXFIFO_START_ADDR")
-            .field(
-                "rxfifo_start_addr",
-                &format_args!("{}", self.rxfifo_start_addr().bits()),
-            )
+            .field("rxfifo_start_addr", &self.rxfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C RXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for RXFIFO_START_ADDR_SPEC {
diff --git a/esp32h2/src/i2c0/scl_high_period.rs b/esp32h2/src/i2c0/scl_high_period.rs
index 2af2564e19..3155621a91 100644
--- a/esp32h2/src/i2c0/scl_high_period.rs
+++ b/esp32h2/src/i2c0/scl_high_period.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH_PERIOD")
-            .field(
-                "scl_high_period",
-                &format_args!("{}", self.scl_high_period().bits()),
-            )
-            .field(
-                "scl_wait_high_period",
-                &format_args!("{}", self.scl_wait_high_period().bits()),
-            )
+            .field("scl_high_period", &self.scl_high_period())
+            .field("scl_wait_high_period", &self.scl_wait_high_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/scl_low_period.rs b/esp32h2/src/i2c0/scl_low_period.rs
index bb4cd05e6d..c75461f0c7 100644
--- a/esp32h2/src/i2c0/scl_low_period.rs
+++ b/esp32h2/src/i2c0/scl_low_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW_PERIOD")
-            .field(
-                "scl_low_period",
-                &format_args!("{}", self.scl_low_period().bits()),
-            )
+            .field("scl_low_period", &self.scl_low_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/scl_main_st_time_out.rs b/esp32h2/src/i2c0/scl_main_st_time_out.rs
index 7c392d273a..99069d3ce8 100644
--- a/esp32h2/src/i2c0/scl_main_st_time_out.rs
+++ b/esp32h2/src/i2c0/scl_main_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_MAIN_ST_TIME_OUT")
-            .field(
-                "scl_main_st_to_i2c",
-                &format_args!("{}", self.scl_main_st_to_i2c().bits()),
-            )
+            .field("scl_main_st_to_i2c", &self.scl_main_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_MAIN_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23"]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/scl_rstart_setup.rs b/esp32h2/src/i2c0/scl_rstart_setup.rs
index 5f61d4fc91..63ddddc0f2 100644
--- a/esp32h2/src/i2c0/scl_rstart_setup.rs
+++ b/esp32h2/src/i2c0/scl_rstart_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_RSTART_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_RSTART_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/scl_sp_conf.rs b/esp32h2/src/i2c0/scl_sp_conf.rs
index e3cdc353bf..492452e245 100644
--- a/esp32h2/src/i2c0/scl_sp_conf.rs
+++ b/esp32h2/src/i2c0/scl_sp_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_SP_CONF")
-            .field(
-                "scl_rst_slv_en",
-                &format_args!("{}", self.scl_rst_slv_en().bit()),
-            )
-            .field(
-                "scl_rst_slv_num",
-                &format_args!("{}", self.scl_rst_slv_num().bits()),
-            )
-            .field("scl_pd_en", &format_args!("{}", self.scl_pd_en().bit()))
-            .field("sda_pd_en", &format_args!("{}", self.sda_pd_en().bit()))
+            .field("scl_rst_slv_en", &self.scl_rst_slv_en())
+            .field("scl_rst_slv_num", &self.scl_rst_slv_num())
+            .field("scl_pd_en", &self.scl_pd_en())
+            .field("sda_pd_en", &self.sda_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_SP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/scl_st_time_out.rs b/esp32h2/src/i2c0/scl_st_time_out.rs
index ba02a4a885..e56dd94c72 100644
--- a/esp32h2/src/i2c0/scl_st_time_out.rs
+++ b/esp32h2/src/i2c0/scl_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_ST_TIME_OUT")
-            .field(
-                "scl_st_to_i2c",
-                &format_args!("{}", self.scl_st_to_i2c().bits()),
-            )
+            .field("scl_st_to_i2c", &self.scl_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The threshold value of SCL_FSM state unchanged period. It should be o more than 23"]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/scl_start_hold.rs b/esp32h2/src/i2c0/scl_start_hold.rs
index eaa7d6ef78..073d03f4ca 100644
--- a/esp32h2/src/i2c0/scl_start_hold.rs
+++ b/esp32h2/src/i2c0/scl_start_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/scl_stop_hold.rs b/esp32h2/src/i2c0/scl_stop_hold.rs
index edfbb10e29..3a115f7912 100644
--- a/esp32h2/src/i2c0/scl_stop_hold.rs
+++ b/esp32h2/src/i2c0/scl_stop_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the delay after the STOP condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/scl_stop_setup.rs b/esp32h2/src/i2c0/scl_stop_setup.rs
index f231319c28..592044b6a2 100644
--- a/esp32h2/src/i2c0/scl_stop_setup.rs
+++ b/esp32h2/src/i2c0/scl_stop_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/scl_stretch_conf.rs b/esp32h2/src/i2c0/scl_stretch_conf.rs
index 41ef0b914c..541e31a624 100644
--- a/esp32h2/src/i2c0/scl_stretch_conf.rs
+++ b/esp32h2/src/i2c0/scl_stretch_conf.rs
@@ -46,31 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STRETCH_CONF")
-            .field(
-                "stretch_protect_num",
-                &format_args!("{}", self.stretch_protect_num().bits()),
-            )
-            .field(
-                "slave_scl_stretch_en",
-                &format_args!("{}", self.slave_scl_stretch_en().bit()),
-            )
-            .field(
-                "slave_byte_ack_ctl_en",
-                &format_args!("{}", self.slave_byte_ack_ctl_en().bit()),
-            )
-            .field(
-                "slave_byte_ack_lvl",
-                &format_args!("{}", self.slave_byte_ack_lvl().bit()),
-            )
+            .field("stretch_protect_num", &self.stretch_protect_num())
+            .field("slave_scl_stretch_en", &self.slave_scl_stretch_en())
+            .field("slave_byte_ack_ctl_en", &self.slave_byte_ack_ctl_en())
+            .field("slave_byte_ack_lvl", &self.slave_byte_ack_lvl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STRETCH_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - Configure the period of I2C slave stretching SCL line."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/sda_hold.rs b/esp32h2/src/i2c0/sda_hold.rs
index b16485e33b..817872197e 100644
--- a/esp32h2/src/i2c0/sda_hold.rs
+++ b/esp32h2/src/i2c0/sda_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time to hold the data after the negative edge of SCL, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/sda_sample.rs b/esp32h2/src/i2c0/sda_sample.rs
index 5a56fc1aa2..a8bd733614 100644
--- a/esp32h2/src/i2c0/sda_sample.rs
+++ b/esp32h2/src/i2c0/sda_sample.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_SAMPLE")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SDA is sampled, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/slave_addr.rs b/esp32h2/src/i2c0/slave_addr.rs
index 004dabd9bb..04cdd14f36 100644
--- a/esp32h2/src/i2c0/slave_addr.rs
+++ b/esp32h2/src/i2c0/slave_addr.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE_ADDR")
-            .field("slave_addr", &format_args!("{}", self.slave_addr().bits()))
-            .field(
-                "addr_10bit_en",
-                &format_args!("{}", self.addr_10bit_en().bit()),
-            )
+            .field("slave_addr", &self.slave_addr())
+            .field("addr_10bit_en", &self.addr_10bit_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - When configured as an I2C Slave, this field is used to configure the slave address."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/sr.rs b/esp32h2/src/i2c0/sr.rs
index 17b1957f57..bcd6b76f37 100644
--- a/esp32h2/src/i2c0/sr.rs
+++ b/esp32h2/src/i2c0/sr.rs
@@ -76,37 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR")
-            .field("resp_rec", &format_args!("{}", self.resp_rec().bit()))
-            .field("slave_rw", &format_args!("{}", self.slave_rw().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field(
-                "slave_addressed",
-                &format_args!("{}", self.slave_addressed().bit()),
-            )
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field(
-                "stretch_cause",
-                &format_args!("{}", self.stretch_cause().bits()),
-            )
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field(
-                "scl_main_state_last",
-                &format_args!("{}", self.scl_main_state_last().bits()),
-            )
-            .field(
-                "scl_state_last",
-                &format_args!("{}", self.scl_state_last().bits()),
-            )
+            .field("resp_rec", &self.resp_rec())
+            .field("slave_rw", &self.slave_rw())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("slave_addressed", &self.slave_addressed())
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("stretch_cause", &self.stretch_cause())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("scl_main_state_last", &self.scl_main_state_last())
+            .field("scl_state_last", &self.scl_state_last())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Describe I2C work status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SR_SPEC;
 impl crate::RegisterSpec for SR_SPEC {
diff --git a/esp32h2/src/i2c0/to.rs b/esp32h2/src/i2c0/to.rs
index 92f73cdd2b..cf95ff843d 100644
--- a/esp32h2/src/i2c0/to.rs
+++ b/esp32h2/src/i2c0/to.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO")
-            .field(
-                "time_out_value",
-                &format_args!("{}", self.time_out_value().bits()),
-            )
-            .field("time_out_en", &format_args!("{}", self.time_out_en().bit()))
+            .field("time_out_value", &self.time_out_value())
+            .field("time_out_en", &self.time_out_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to configure the timeout for receiving a data bit in APB clock cycles."]
     #[inline(always)]
diff --git a/esp32h2/src/i2c0/txfifo_start_addr.rs b/esp32h2/src/i2c0/txfifo_start_addr.rs
index 8df0b6828e..c7cd4f0ea5 100644
--- a/esp32h2/src/i2c0/txfifo_start_addr.rs
+++ b/esp32h2/src/i2c0/txfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXFIFO_START_ADDR")
-            .field(
-                "txfifo_start_addr",
-                &format_args!("{}", self.txfifo_start_addr().bits()),
-            )
+            .field("txfifo_start_addr", &self.txfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C TXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for TXFIFO_START_ADDR_SPEC {
diff --git a/esp32h2/src/i2s0/conf_sigle_data.rs b/esp32h2/src/i2s0/conf_sigle_data.rs
index f979345988..3c75f59255 100644
--- a/esp32h2/src/i2s0/conf_sigle_data.rs
+++ b/esp32h2/src/i2s0/conf_sigle_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_SIGLE_DATA")
-            .field(
-                "single_data",
-                &format_args!("{}", self.single_data().bits()),
-            )
+            .field("single_data", &self.single_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SIGLE_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The configured constant channel data to be sent out."]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/date.rs b/esp32h2/src/i2s0/date.rs
index b02d6f3a3f..2d62ce346d 100644
--- a/esp32h2/src/i2s0/date.rs
+++ b/esp32h2/src/i2s0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/i2s0/etm_conf.rs b/esp32h2/src/i2s0/etm_conf.rs
index ba87038a24..456f1152f9 100644
--- a/esp32h2/src/i2s0/etm_conf.rs
+++ b/esp32h2/src/i2s0/etm_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_CONF")
-            .field(
-                "etm_tx_send_word_num",
-                &format_args!("{}", self.etm_tx_send_word_num().bits()),
-            )
-            .field(
-                "etm_rx_receive_word_num",
-                &format_args!("{}", self.etm_rx_receive_word_num().bits()),
-            )
+            .field("etm_tx_send_word_num", &self.etm_tx_send_word_num())
+            .field("etm_rx_receive_word_num", &self.etm_rx_receive_word_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num\\[9:0\\], i2s will trigger an etm event."]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/int_ena.rs b/esp32h2/src/i2s0/int_ena.rs
index ffbc92bacc..0a538b90e5 100644
--- a/esp32h2/src/i2s0/int_ena.rs
+++ b/esp32h2/src/i2s0/int_ena.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/int_raw.rs b/esp32h2/src/i2s0/int_raw.rs
index 7ec2d42cfd..e69602c0be 100644
--- a/esp32h2/src/i2s0/int_raw.rs
+++ b/esp32h2/src/i2s0/int_raw.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32h2/src/i2s0/int_st.rs b/esp32h2/src/i2s0/int_st.rs
index 5eac7b9c9d..ddf72a352e 100644
--- a/esp32h2/src/i2s0/int_st.rs
+++ b/esp32h2/src/i2s0/int_st.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/i2s0/lc_hung_conf.rs b/esp32h2/src/i2s0/lc_hung_conf.rs
index 060b1cdb60..71f0c84fa7 100644
--- a/esp32h2/src/i2s0/lc_hung_conf.rs
+++ b/esp32h2/src/i2s0/lc_hung_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_HUNG_CONF")
-            .field(
-                "lc_fifo_timeout",
-                &format_args!("{}", self.lc_fifo_timeout().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_shift",
-                &format_args!("{}", self.lc_fifo_timeout_shift().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_ena",
-                &format_args!("{}", self.lc_fifo_timeout_ena().bit()),
-            )
+            .field("lc_fifo_timeout", &self.lc_fifo_timeout())
+            .field("lc_fifo_timeout_shift", &self.lc_fifo_timeout_shift())
+            .field("lc_fifo_timeout_ena", &self.lc_fifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/rx_clkm_conf.rs b/esp32h2/src/i2s0/rx_clkm_conf.rs
index 79ff9b2470..5bbb7a360a 100644
--- a/esp32h2/src/i2s0/rx_clkm_conf.rs
+++ b/esp32h2/src/i2s0/rx_clkm_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CLKM_CONF")
-            .field(
-                "rx_clkm_div_num",
-                &format_args!("{}", self.rx_clkm_div_num().bits()),
-            )
-            .field(
-                "rx_clk_active",
-                &format_args!("{}", self.rx_clk_active().bit()),
-            )
-            .field("rx_clk_sel", &format_args!("{}", self.rx_clk_sel().bits()))
-            .field("mclk_sel", &format_args!("{}", self.mclk_sel().bit()))
+            .field("rx_clkm_div_num", &self.rx_clkm_div_num())
+            .field("rx_clk_active", &self.rx_clk_active())
+            .field("rx_clk_sel", &self.rx_clk_sel())
+            .field("mclk_sel", &self.mclk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral I2S clock divider value"]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/rx_clkm_div_conf.rs b/esp32h2/src/i2s0/rx_clkm_div_conf.rs
index 9dc32721ed..d4f0ee53bc 100644
--- a/esp32h2/src/i2s0/rx_clkm_div_conf.rs
+++ b/esp32h2/src/i2s0/rx_clkm_div_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CLKM_DIV_CONF")
-            .field(
-                "rx_clkm_div_z",
-                &format_args!("{}", self.rx_clkm_div_z().bits()),
-            )
-            .field(
-                "rx_clkm_div_y",
-                &format_args!("{}", self.rx_clkm_div_y().bits()),
-            )
-            .field(
-                "rx_clkm_div_x",
-                &format_args!("{}", self.rx_clkm_div_x().bits()),
-            )
-            .field(
-                "rx_clkm_div_yn1",
-                &format_args!("{}", self.rx_clkm_div_yn1().bit()),
-            )
+            .field("rx_clkm_div_z", &self.rx_clkm_div_z())
+            .field("rx_clkm_div_y", &self.rx_clkm_div_y())
+            .field("rx_clkm_div_x", &self.rx_clkm_div_x())
+            .field("rx_clkm_div_yn1", &self.rx_clkm_div_yn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CLKM_DIV_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/rx_conf.rs b/esp32h2/src/i2s0/rx_conf.rs
index 5bb25c8d6b..243dbee06f 100644
--- a/esp32h2/src/i2s0/rx_conf.rs
+++ b/esp32h2/src/i2s0/rx_conf.rs
@@ -165,68 +165,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CONF")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field(
-                "rx_slave_mod",
-                &format_args!("{}", self.rx_slave_mod().bit()),
-            )
-            .field(
-                "rx_stop_mode",
-                &format_args!("{}", self.rx_stop_mode().bits()),
-            )
-            .field("rx_mono", &format_args!("{}", self.rx_mono().bit()))
-            .field(
-                "rx_big_endian",
-                &format_args!("{}", self.rx_big_endian().bit()),
-            )
-            .field("rx_update", &format_args!("{}", self.rx_update().bit()))
-            .field(
-                "rx_mono_fst_vld",
-                &format_args!("{}", self.rx_mono_fst_vld().bit()),
-            )
-            .field(
-                "rx_pcm_conf",
-                &format_args!("{}", self.rx_pcm_conf().bits()),
-            )
-            .field(
-                "rx_pcm_bypass",
-                &format_args!("{}", self.rx_pcm_bypass().bit()),
-            )
-            .field(
-                "rx_msb_shift",
-                &format_args!("{}", self.rx_msb_shift().bit()),
-            )
-            .field(
-                "rx_left_align",
-                &format_args!("{}", self.rx_left_align().bit()),
-            )
-            .field(
-                "rx_24_fill_en",
-                &format_args!("{}", self.rx_24_fill_en().bit()),
-            )
-            .field(
-                "rx_ws_idle_pol",
-                &format_args!("{}", self.rx_ws_idle_pol().bit()),
-            )
-            .field(
-                "rx_bit_order",
-                &format_args!("{}", self.rx_bit_order().bit()),
-            )
-            .field("rx_tdm_en", &format_args!("{}", self.rx_tdm_en().bit()))
-            .field("rx_pdm_en", &format_args!("{}", self.rx_pdm_en().bit()))
-            .field(
-                "rx_bck_div_num",
-                &format_args!("{}", self.rx_bck_div_num().bits()),
-            )
+            .field("rx_start", &self.rx_start())
+            .field("rx_slave_mod", &self.rx_slave_mod())
+            .field("rx_stop_mode", &self.rx_stop_mode())
+            .field("rx_mono", &self.rx_mono())
+            .field("rx_big_endian", &self.rx_big_endian())
+            .field("rx_update", &self.rx_update())
+            .field("rx_mono_fst_vld", &self.rx_mono_fst_vld())
+            .field("rx_pcm_conf", &self.rx_pcm_conf())
+            .field("rx_pcm_bypass", &self.rx_pcm_bypass())
+            .field("rx_msb_shift", &self.rx_msb_shift())
+            .field("rx_left_align", &self.rx_left_align())
+            .field("rx_24_fill_en", &self.rx_24_fill_en())
+            .field("rx_ws_idle_pol", &self.rx_ws_idle_pol())
+            .field("rx_bit_order", &self.rx_bit_order())
+            .field("rx_tdm_en", &self.rx_tdm_en())
+            .field("rx_pdm_en", &self.rx_pdm_en())
+            .field("rx_bck_div_num", &self.rx_bck_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset receiver"]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/rx_conf1.rs b/esp32h2/src/i2s0/rx_conf1.rs
index 898003bcab..a4e0fc2df4 100644
--- a/esp32h2/src/i2s0/rx_conf1.rs
+++ b/esp32h2/src/i2s0/rx_conf1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CONF1")
-            .field(
-                "rx_tdm_ws_width",
-                &format_args!("{}", self.rx_tdm_ws_width().bits()),
-            )
-            .field(
-                "rx_bits_mod",
-                &format_args!("{}", self.rx_bits_mod().bits()),
-            )
-            .field(
-                "rx_half_sample_bits",
-                &format_args!("{}", self.rx_half_sample_bits().bits()),
-            )
-            .field(
-                "rx_tdm_chan_bits",
-                &format_args!("{}", self.rx_tdm_chan_bits().bits()),
-            )
+            .field("rx_tdm_ws_width", &self.rx_tdm_ws_width())
+            .field("rx_bits_mod", &self.rx_bits_mod())
+            .field("rx_half_sample_bits", &self.rx_half_sample_bits())
+            .field("rx_tdm_chan_bits", &self.rx_tdm_chan_bits())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[8:0\\] +1) * T_bck"]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/rx_tdm_ctrl.rs b/esp32h2/src/i2s0/rx_tdm_ctrl.rs
index fe01f97aeb..0d18f522f2 100644
--- a/esp32h2/src/i2s0/rx_tdm_ctrl.rs
+++ b/esp32h2/src/i2s0/rx_tdm_ctrl.rs
@@ -161,83 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_TDM_CTRL")
-            .field(
-                "rx_tdm_pdm_chan0_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan0_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan1_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan1_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan2_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan2_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan3_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan3_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan4_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan4_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan5_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan5_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan6_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan6_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan7_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan7_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan8_en",
-                &format_args!("{}", self.rx_tdm_chan8_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan9_en",
-                &format_args!("{}", self.rx_tdm_chan9_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan10_en",
-                &format_args!("{}", self.rx_tdm_chan10_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan11_en",
-                &format_args!("{}", self.rx_tdm_chan11_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan12_en",
-                &format_args!("{}", self.rx_tdm_chan12_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan13_en",
-                &format_args!("{}", self.rx_tdm_chan13_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan14_en",
-                &format_args!("{}", self.rx_tdm_chan14_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan15_en",
-                &format_args!("{}", self.rx_tdm_chan15_en().bit()),
-            )
-            .field(
-                "rx_tdm_tot_chan_num",
-                &format_args!("{}", self.rx_tdm_tot_chan_num().bits()),
-            )
+            .field("rx_tdm_pdm_chan0_en", &self.rx_tdm_pdm_chan0_en())
+            .field("rx_tdm_pdm_chan1_en", &self.rx_tdm_pdm_chan1_en())
+            .field("rx_tdm_pdm_chan2_en", &self.rx_tdm_pdm_chan2_en())
+            .field("rx_tdm_pdm_chan3_en", &self.rx_tdm_pdm_chan3_en())
+            .field("rx_tdm_pdm_chan4_en", &self.rx_tdm_pdm_chan4_en())
+            .field("rx_tdm_pdm_chan5_en", &self.rx_tdm_pdm_chan5_en())
+            .field("rx_tdm_pdm_chan6_en", &self.rx_tdm_pdm_chan6_en())
+            .field("rx_tdm_pdm_chan7_en", &self.rx_tdm_pdm_chan7_en())
+            .field("rx_tdm_chan8_en", &self.rx_tdm_chan8_en())
+            .field("rx_tdm_chan9_en", &self.rx_tdm_chan9_en())
+            .field("rx_tdm_chan10_en", &self.rx_tdm_chan10_en())
+            .field("rx_tdm_chan11_en", &self.rx_tdm_chan11_en())
+            .field("rx_tdm_chan12_en", &self.rx_tdm_chan12_en())
+            .field("rx_tdm_chan13_en", &self.rx_tdm_chan13_en())
+            .field("rx_tdm_chan14_en", &self.rx_tdm_chan14_en())
+            .field("rx_tdm_chan15_en", &self.rx_tdm_chan15_en())
+            .field("rx_tdm_tot_chan_num", &self.rx_tdm_tot_chan_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_TDM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/rx_timing.rs b/esp32h2/src/i2s0/rx_timing.rs
index 66daf81e08..fe227b5840 100644
--- a/esp32h2/src/i2s0/rx_timing.rs
+++ b/esp32h2/src/i2s0/rx_timing.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_TIMING")
-            .field(
-                "rx_sd_in_dm",
-                &format_args!("{}", self.rx_sd_in_dm().bits()),
-            )
-            .field(
-                "rx_ws_out_dm",
-                &format_args!("{}", self.rx_ws_out_dm().bits()),
-            )
-            .field(
-                "rx_bck_out_dm",
-                &format_args!("{}", self.rx_bck_out_dm().bits()),
-            )
-            .field(
-                "rx_ws_in_dm",
-                &format_args!("{}", self.rx_ws_in_dm().bits()),
-            )
-            .field(
-                "rx_bck_in_dm",
-                &format_args!("{}", self.rx_bck_in_dm().bits()),
-            )
+            .field("rx_sd_in_dm", &self.rx_sd_in_dm())
+            .field("rx_ws_out_dm", &self.rx_ws_out_dm())
+            .field("rx_bck_out_dm", &self.rx_bck_out_dm())
+            .field("rx_ws_in_dm", &self.rx_ws_in_dm())
+            .field("rx_bck_in_dm", &self.rx_bck_in_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/rxeof_num.rs b/esp32h2/src/i2s0/rxeof_num.rs
index 06f6d22ff0..b9674d5891 100644
--- a/esp32h2/src/i2s0/rxeof_num.rs
+++ b/esp32h2/src/i2s0/rxeof_num.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXEOF_NUM")
-            .field("rx_eof_num", &format_args!("{}", self.rx_eof_num().bits()))
+            .field("rx_eof_num", &self.rx_eof_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXEOF_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/state.rs b/esp32h2/src/i2s0/state.rs
index 7988d4067c..d16247a40d 100644
--- a/esp32h2/src/i2s0/state.rs
+++ b/esp32h2/src/i2s0/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("tx_idle", &format_args!("{}", self.tx_idle().bit()))
+            .field("tx_idle", &self.tx_idle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S TX status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32h2/src/i2s0/tx_clkm_conf.rs b/esp32h2/src/i2s0/tx_clkm_conf.rs
index ef82d04116..2584244722 100644
--- a/esp32h2/src/i2s0/tx_clkm_conf.rs
+++ b/esp32h2/src/i2s0/tx_clkm_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CLKM_CONF")
-            .field(
-                "tx_clkm_div_num",
-                &format_args!("{}", self.tx_clkm_div_num().bits()),
-            )
-            .field(
-                "tx_clk_active",
-                &format_args!("{}", self.tx_clk_active().bit()),
-            )
-            .field("tx_clk_sel", &format_args!("{}", self.tx_clk_sel().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("tx_clkm_div_num", &self.tx_clkm_div_num())
+            .field("tx_clk_active", &self.tx_clk_active())
+            .field("tx_clk_sel", &self.tx_clk_sel())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b &lt;= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/tx_clkm_div_conf.rs b/esp32h2/src/i2s0/tx_clkm_div_conf.rs
index eb02e39a99..8421d21999 100644
--- a/esp32h2/src/i2s0/tx_clkm_div_conf.rs
+++ b/esp32h2/src/i2s0/tx_clkm_div_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CLKM_DIV_CONF")
-            .field(
-                "tx_clkm_div_z",
-                &format_args!("{}", self.tx_clkm_div_z().bits()),
-            )
-            .field(
-                "tx_clkm_div_y",
-                &format_args!("{}", self.tx_clkm_div_y().bits()),
-            )
-            .field(
-                "tx_clkm_div_x",
-                &format_args!("{}", self.tx_clkm_div_x().bits()),
-            )
-            .field(
-                "tx_clkm_div_yn1",
-                &format_args!("{}", self.tx_clkm_div_yn1().bit()),
-            )
+            .field("tx_clkm_div_z", &self.tx_clkm_div_z())
+            .field("tx_clkm_div_y", &self.tx_clkm_div_y())
+            .field("tx_clkm_div_x", &self.tx_clkm_div_x())
+            .field("tx_clkm_div_yn1", &self.tx_clkm_div_yn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CLKM_DIV_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/tx_conf.rs b/esp32h2/src/i2s0/tx_conf.rs
index f8247c5f9c..84ddc2d9bf 100644
--- a/esp32h2/src/i2s0/tx_conf.rs
+++ b/esp32h2/src/i2s0/tx_conf.rs
@@ -201,81 +201,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CONF")
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field(
-                "tx_slave_mod",
-                &format_args!("{}", self.tx_slave_mod().bit()),
-            )
-            .field("tx_stop_en", &format_args!("{}", self.tx_stop_en().bit()))
-            .field(
-                "tx_chan_equal",
-                &format_args!("{}", self.tx_chan_equal().bit()),
-            )
-            .field("tx_mono", &format_args!("{}", self.tx_mono().bit()))
-            .field(
-                "tx_big_endian",
-                &format_args!("{}", self.tx_big_endian().bit()),
-            )
-            .field("tx_update", &format_args!("{}", self.tx_update().bit()))
-            .field(
-                "tx_mono_fst_vld",
-                &format_args!("{}", self.tx_mono_fst_vld().bit()),
-            )
-            .field(
-                "tx_pcm_conf",
-                &format_args!("{}", self.tx_pcm_conf().bits()),
-            )
-            .field(
-                "tx_pcm_bypass",
-                &format_args!("{}", self.tx_pcm_bypass().bit()),
-            )
-            .field(
-                "tx_msb_shift",
-                &format_args!("{}", self.tx_msb_shift().bit()),
-            )
-            .field(
-                "tx_bck_no_dly",
-                &format_args!("{}", self.tx_bck_no_dly().bit()),
-            )
-            .field(
-                "tx_left_align",
-                &format_args!("{}", self.tx_left_align().bit()),
-            )
-            .field(
-                "tx_24_fill_en",
-                &format_args!("{}", self.tx_24_fill_en().bit()),
-            )
-            .field(
-                "tx_ws_idle_pol",
-                &format_args!("{}", self.tx_ws_idle_pol().bit()),
-            )
-            .field(
-                "tx_bit_order",
-                &format_args!("{}", self.tx_bit_order().bit()),
-            )
-            .field("tx_tdm_en", &format_args!("{}", self.tx_tdm_en().bit()))
-            .field("tx_pdm_en", &format_args!("{}", self.tx_pdm_en().bit()))
-            .field(
-                "tx_bck_div_num",
-                &format_args!("{}", self.tx_bck_div_num().bits()),
-            )
-            .field(
-                "tx_chan_mod",
-                &format_args!("{}", self.tx_chan_mod().bits()),
-            )
-            .field(
-                "sig_loopback",
-                &format_args!("{}", self.sig_loopback().bit()),
-            )
+            .field("tx_start", &self.tx_start())
+            .field("tx_slave_mod", &self.tx_slave_mod())
+            .field("tx_stop_en", &self.tx_stop_en())
+            .field("tx_chan_equal", &self.tx_chan_equal())
+            .field("tx_mono", &self.tx_mono())
+            .field("tx_big_endian", &self.tx_big_endian())
+            .field("tx_update", &self.tx_update())
+            .field("tx_mono_fst_vld", &self.tx_mono_fst_vld())
+            .field("tx_pcm_conf", &self.tx_pcm_conf())
+            .field("tx_pcm_bypass", &self.tx_pcm_bypass())
+            .field("tx_msb_shift", &self.tx_msb_shift())
+            .field("tx_bck_no_dly", &self.tx_bck_no_dly())
+            .field("tx_left_align", &self.tx_left_align())
+            .field("tx_24_fill_en", &self.tx_24_fill_en())
+            .field("tx_ws_idle_pol", &self.tx_ws_idle_pol())
+            .field("tx_bit_order", &self.tx_bit_order())
+            .field("tx_tdm_en", &self.tx_tdm_en())
+            .field("tx_pdm_en", &self.tx_pdm_en())
+            .field("tx_bck_div_num", &self.tx_bck_div_num())
+            .field("tx_chan_mod", &self.tx_chan_mod())
+            .field("sig_loopback", &self.sig_loopback())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset transmitter"]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/tx_conf1.rs b/esp32h2/src/i2s0/tx_conf1.rs
index 6a076d5334..580fa1b86c 100644
--- a/esp32h2/src/i2s0/tx_conf1.rs
+++ b/esp32h2/src/i2s0/tx_conf1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CONF1")
-            .field(
-                "tx_tdm_ws_width",
-                &format_args!("{}", self.tx_tdm_ws_width().bits()),
-            )
-            .field(
-                "tx_bits_mod",
-                &format_args!("{}", self.tx_bits_mod().bits()),
-            )
-            .field(
-                "tx_half_sample_bits",
-                &format_args!("{}", self.tx_half_sample_bits().bits()),
-            )
-            .field(
-                "tx_tdm_chan_bits",
-                &format_args!("{}", self.tx_tdm_chan_bits().bits()),
-            )
+            .field("tx_tdm_ws_width", &self.tx_tdm_ws_width())
+            .field("tx_bits_mod", &self.tx_bits_mod())
+            .field("tx_half_sample_bits", &self.tx_half_sample_bits())
+            .field("tx_tdm_chan_bits", &self.tx_tdm_chan_bits())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[8:0\\] +1) * T_bck"]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/tx_pcm2pdm_conf.rs b/esp32h2/src/i2s0/tx_pcm2pdm_conf.rs
index f361f43fa5..833a737465 100644
--- a/esp32h2/src/i2s0/tx_pcm2pdm_conf.rs
+++ b/esp32h2/src/i2s0/tx_pcm2pdm_conf.rs
@@ -116,63 +116,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_PCM2PDM_CONF")
-            .field(
-                "tx_pdm_hp_bypass",
-                &format_args!("{}", self.tx_pdm_hp_bypass().bit()),
-            )
-            .field(
-                "tx_pdm_sinc_osr2",
-                &format_args!("{}", self.tx_pdm_sinc_osr2().bits()),
-            )
-            .field(
-                "tx_pdm_prescale",
-                &format_args!("{}", self.tx_pdm_prescale().bits()),
-            )
-            .field(
-                "tx_pdm_hp_in_shift",
-                &format_args!("{}", self.tx_pdm_hp_in_shift().bits()),
-            )
-            .field(
-                "tx_pdm_lp_in_shift",
-                &format_args!("{}", self.tx_pdm_lp_in_shift().bits()),
-            )
-            .field(
-                "tx_pdm_sinc_in_shift",
-                &format_args!("{}", self.tx_pdm_sinc_in_shift().bits()),
-            )
+            .field("tx_pdm_hp_bypass", &self.tx_pdm_hp_bypass())
+            .field("tx_pdm_sinc_osr2", &self.tx_pdm_sinc_osr2())
+            .field("tx_pdm_prescale", &self.tx_pdm_prescale())
+            .field("tx_pdm_hp_in_shift", &self.tx_pdm_hp_in_shift())
+            .field("tx_pdm_lp_in_shift", &self.tx_pdm_lp_in_shift())
+            .field("tx_pdm_sinc_in_shift", &self.tx_pdm_sinc_in_shift())
             .field(
                 "tx_pdm_sigmadelta_in_shift",
-                &format_args!("{}", self.tx_pdm_sigmadelta_in_shift().bits()),
+                &self.tx_pdm_sigmadelta_in_shift(),
             )
             .field(
                 "tx_pdm_sigmadelta_dither2",
-                &format_args!("{}", self.tx_pdm_sigmadelta_dither2().bit()),
-            )
-            .field(
-                "tx_pdm_sigmadelta_dither",
-                &format_args!("{}", self.tx_pdm_sigmadelta_dither().bit()),
-            )
-            .field(
-                "tx_pdm_dac_2out_en",
-                &format_args!("{}", self.tx_pdm_dac_2out_en().bit()),
-            )
-            .field(
-                "tx_pdm_dac_mode_en",
-                &format_args!("{}", self.tx_pdm_dac_mode_en().bit()),
-            )
-            .field(
-                "pcm2pdm_conv_en",
-                &format_args!("{}", self.pcm2pdm_conv_en().bit()),
+                &self.tx_pdm_sigmadelta_dither2(),
             )
+            .field("tx_pdm_sigmadelta_dither", &self.tx_pdm_sigmadelta_dither())
+            .field("tx_pdm_dac_2out_en", &self.tx_pdm_dac_2out_en())
+            .field("tx_pdm_dac_mode_en", &self.tx_pdm_dac_mode_en())
+            .field("pcm2pdm_conv_en", &self.pcm2pdm_conv_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_PCM2PDM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - I2S TX PDM bypass hp filter or not. The option has been removed."]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/tx_pcm2pdm_conf1.rs b/esp32h2/src/i2s0/tx_pcm2pdm_conf1.rs
index dfcd334df0..48c460dc25 100644
--- a/esp32h2/src/i2s0/tx_pcm2pdm_conf1.rs
+++ b/esp32h2/src/i2s0/tx_pcm2pdm_conf1.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_PCM2PDM_CONF1")
-            .field("tx_pdm_fp", &format_args!("{}", self.tx_pdm_fp().bits()))
-            .field("tx_pdm_fs", &format_args!("{}", self.tx_pdm_fs().bits()))
-            .field(
-                "tx_iir_hp_mult12_5",
-                &format_args!("{}", self.tx_iir_hp_mult12_5().bits()),
-            )
-            .field(
-                "tx_iir_hp_mult12_0",
-                &format_args!("{}", self.tx_iir_hp_mult12_0().bits()),
-            )
+            .field("tx_pdm_fp", &self.tx_pdm_fp())
+            .field("tx_pdm_fs", &self.tx_pdm_fs())
+            .field("tx_iir_hp_mult12_5", &self.tx_iir_hp_mult12_5())
+            .field("tx_iir_hp_mult12_0", &self.tx_iir_hp_mult12_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_PCM2PDM_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - I2S TX PDM Fp"]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/tx_tdm_ctrl.rs b/esp32h2/src/i2s0/tx_tdm_ctrl.rs
index a6511fa2f9..8b06e96c6c 100644
--- a/esp32h2/src/i2s0/tx_tdm_ctrl.rs
+++ b/esp32h2/src/i2s0/tx_tdm_ctrl.rs
@@ -170,87 +170,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_TDM_CTRL")
-            .field(
-                "tx_tdm_chan0_en",
-                &format_args!("{}", self.tx_tdm_chan0_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan1_en",
-                &format_args!("{}", self.tx_tdm_chan1_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan2_en",
-                &format_args!("{}", self.tx_tdm_chan2_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan3_en",
-                &format_args!("{}", self.tx_tdm_chan3_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan4_en",
-                &format_args!("{}", self.tx_tdm_chan4_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan5_en",
-                &format_args!("{}", self.tx_tdm_chan5_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan6_en",
-                &format_args!("{}", self.tx_tdm_chan6_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan7_en",
-                &format_args!("{}", self.tx_tdm_chan7_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan8_en",
-                &format_args!("{}", self.tx_tdm_chan8_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan9_en",
-                &format_args!("{}", self.tx_tdm_chan9_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan10_en",
-                &format_args!("{}", self.tx_tdm_chan10_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan11_en",
-                &format_args!("{}", self.tx_tdm_chan11_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan12_en",
-                &format_args!("{}", self.tx_tdm_chan12_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan13_en",
-                &format_args!("{}", self.tx_tdm_chan13_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan14_en",
-                &format_args!("{}", self.tx_tdm_chan14_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan15_en",
-                &format_args!("{}", self.tx_tdm_chan15_en().bit()),
-            )
-            .field(
-                "tx_tdm_tot_chan_num",
-                &format_args!("{}", self.tx_tdm_tot_chan_num().bits()),
-            )
-            .field(
-                "tx_tdm_skip_msk_en",
-                &format_args!("{}", self.tx_tdm_skip_msk_en().bit()),
-            )
+            .field("tx_tdm_chan0_en", &self.tx_tdm_chan0_en())
+            .field("tx_tdm_chan1_en", &self.tx_tdm_chan1_en())
+            .field("tx_tdm_chan2_en", &self.tx_tdm_chan2_en())
+            .field("tx_tdm_chan3_en", &self.tx_tdm_chan3_en())
+            .field("tx_tdm_chan4_en", &self.tx_tdm_chan4_en())
+            .field("tx_tdm_chan5_en", &self.tx_tdm_chan5_en())
+            .field("tx_tdm_chan6_en", &self.tx_tdm_chan6_en())
+            .field("tx_tdm_chan7_en", &self.tx_tdm_chan7_en())
+            .field("tx_tdm_chan8_en", &self.tx_tdm_chan8_en())
+            .field("tx_tdm_chan9_en", &self.tx_tdm_chan9_en())
+            .field("tx_tdm_chan10_en", &self.tx_tdm_chan10_en())
+            .field("tx_tdm_chan11_en", &self.tx_tdm_chan11_en())
+            .field("tx_tdm_chan12_en", &self.tx_tdm_chan12_en())
+            .field("tx_tdm_chan13_en", &self.tx_tdm_chan13_en())
+            .field("tx_tdm_chan14_en", &self.tx_tdm_chan14_en())
+            .field("tx_tdm_chan15_en", &self.tx_tdm_chan15_en())
+            .field("tx_tdm_tot_chan_num", &self.tx_tdm_tot_chan_num())
+            .field("tx_tdm_skip_msk_en", &self.tx_tdm_skip_msk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_TDM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
diff --git a/esp32h2/src/i2s0/tx_timing.rs b/esp32h2/src/i2s0/tx_timing.rs
index 90d44db432..550930d1b6 100644
--- a/esp32h2/src/i2s0/tx_timing.rs
+++ b/esp32h2/src/i2s0/tx_timing.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_TIMING")
-            .field(
-                "tx_sd_out_dm",
-                &format_args!("{}", self.tx_sd_out_dm().bits()),
-            )
-            .field(
-                "tx_sd1_out_dm",
-                &format_args!("{}", self.tx_sd1_out_dm().bits()),
-            )
-            .field(
-                "tx_ws_out_dm",
-                &format_args!("{}", self.tx_ws_out_dm().bits()),
-            )
-            .field(
-                "tx_bck_out_dm",
-                &format_args!("{}", self.tx_bck_out_dm().bits()),
-            )
-            .field(
-                "tx_ws_in_dm",
-                &format_args!("{}", self.tx_ws_in_dm().bits()),
-            )
-            .field(
-                "tx_bck_in_dm",
-                &format_args!("{}", self.tx_bck_in_dm().bits()),
-            )
+            .field("tx_sd_out_dm", &self.tx_sd_out_dm())
+            .field("tx_sd1_out_dm", &self.tx_sd1_out_dm())
+            .field("tx_ws_out_dm", &self.tx_ws_out_dm())
+            .field("tx_bck_out_dm", &self.tx_bck_out_dm())
+            .field("tx_ws_in_dm", &self.tx_ws_in_dm())
+            .field("tx_bck_in_dm", &self.tx_bck_in_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/ack_frame_pending_en.rs b/esp32h2/src/ieee802154/ack_frame_pending_en.rs
index e97e5031f0..99fc481d79 100644
--- a/esp32h2/src/ieee802154/ack_frame_pending_en.rs
+++ b/esp32h2/src/ieee802154/ack_frame_pending_en.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ACK_FRAME_PENDING_EN")
-            .field(
-                "ack_frame_pending_en",
-                &format_args!("{}", self.ack_frame_pending_en().bit()),
-            )
-            .field(
-                "ack_tx_ack_timeout",
-                &format_args!("{}", self.ack_tx_ack_timeout().bits()),
-            )
+            .field("ack_frame_pending_en", &self.ack_frame_pending_en())
+            .field("ack_tx_ack_timeout", &self.ack_tx_ack_timeout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ACK_FRAME_PENDING_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/ack_timeout.rs b/esp32h2/src/ieee802154/ack_timeout.rs
index 64b5055ec3..e7aeb4fc1f 100644
--- a/esp32h2/src/ieee802154/ack_timeout.rs
+++ b/esp32h2/src/ieee802154/ack_timeout.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ACK_TIMEOUT")
-            .field(
-                "ack_timeout",
-                &format_args!("{}", self.ack_timeout().bits()),
-            )
+            .field("ack_timeout", &self.ack_timeout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ACK_TIMEOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/bb_clk.rs b/esp32h2/src/ieee802154/bb_clk.rs
index 09628bc4f1..88283253cf 100644
--- a/esp32h2/src/ieee802154/bb_clk.rs
+++ b/esp32h2/src/ieee802154/bb_clk.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BB_CLK")
-            .field(
-                "freq_minus_1",
-                &format_args!("{}", self.freq_minus_1().bits()),
-            )
+            .field("freq_minus_1", &self.freq_minus_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BB_CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/cca_busy_cnt.rs b/esp32h2/src/ieee802154/cca_busy_cnt.rs
index 802cdba43d..868197ae52 100644
--- a/esp32h2/src/ieee802154/cca_busy_cnt.rs
+++ b/esp32h2/src/ieee802154/cca_busy_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CCA_BUSY_CNT")
-            .field(
-                "cca_busy_cnt",
-                &format_args!("{}", self.cca_busy_cnt().bits()),
-            )
+            .field("cca_busy_cnt", &self.cca_busy_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CCA_BUSY_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/cca_fail_cnt.rs b/esp32h2/src/ieee802154/cca_fail_cnt.rs
index 4e5a5ab9a3..7d541aa290 100644
--- a/esp32h2/src/ieee802154/cca_fail_cnt.rs
+++ b/esp32h2/src/ieee802154/cca_fail_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CCA_FAIL_CNT")
-            .field(
-                "cca_fail_cnt",
-                &format_args!("{}", self.cca_fail_cnt().bits()),
-            )
+            .field("cca_fail_cnt", &self.cca_fail_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CCA_FAIL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/channel.rs b/esp32h2/src/ieee802154/channel.rs
index f66d5aeaff..c9bfd524b0 100644
--- a/esp32h2/src/ieee802154/channel.rs
+++ b/esp32h2/src/ieee802154/channel.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CHANNEL")
-            .field("hop", &format_args!("{}", self.hop().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHANNEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CHANNEL").field("hop", &self.hop()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/ieee802154/clk_counter.rs b/esp32h2/src/ieee802154/clk_counter.rs
index 08f3b726f8..0616970a84 100644
--- a/esp32h2/src/ieee802154/clk_counter.rs
+++ b/esp32h2/src/ieee802154/clk_counter.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_COUNTER")
-            .field(
-                "clk_625us_cnt",
-                &format_args!("{}", self.clk_625us_cnt().bits()),
-            )
+            .field("clk_625us_cnt", &self.clk_625us_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_COUNTER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/clk_counter_match_val.rs b/esp32h2/src/ieee802154/clk_counter_match_val.rs
index 2ff54615d1..3b02085d56 100644
--- a/esp32h2/src/ieee802154/clk_counter_match_val.rs
+++ b/esp32h2/src/ieee802154/clk_counter_match_val.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_COUNTER_MATCH_VAL")
-            .field(
-                "clk_count_match_val",
-                &format_args!("{}", self.clk_count_match_val().bits()),
-            )
+            .field("clk_count_match_val", &self.clk_count_match_val())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_COUNTER_MATCH_VAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/coex_pti.rs b/esp32h2/src/ieee802154/coex_pti.rs
index f6645b5596..37dc111e19 100644
--- a/esp32h2/src/ieee802154/coex_pti.rs
+++ b/esp32h2/src/ieee802154/coex_pti.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COEX_PTI")
-            .field("coex_pti", &format_args!("{}", self.coex_pti().bits()))
-            .field(
-                "coex_ack_pti",
-                &format_args!("{}", self.coex_ack_pti().bits()),
-            )
-            .field(
-                "close_rf_sel",
-                &format_args!("{}", self.close_rf_sel().bit()),
-            )
+            .field("coex_pti", &self.coex_pti())
+            .field("coex_ack_pti", &self.coex_ack_pti())
+            .field("close_rf_sel", &self.close_rf_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COEX_PTI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/command.rs b/esp32h2/src/ieee802154/command.rs
index 098fba6571..2e4003d258 100644
--- a/esp32h2/src/ieee802154/command.rs
+++ b/esp32h2/src/ieee802154/command.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMMAND")
-            .field("opcode", &format_args!("{}", self.opcode().bits()))
+            .field("opcode", &self.opcode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMMAND_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/cont_rx_delay.rs b/esp32h2/src/ieee802154/cont_rx_delay.rs
index 49885b4453..deeb70955a 100644
--- a/esp32h2/src/ieee802154/cont_rx_delay.rs
+++ b/esp32h2/src/ieee802154/cont_rx_delay.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONT_RX_DELAY")
-            .field(
-                "cont_rx_delay",
-                &format_args!("{}", self.cont_rx_delay().bits()),
-            )
+            .field("cont_rx_delay", &self.cont_rx_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONT_RX_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/core_dummy_data.rs b/esp32h2/src/ieee802154/core_dummy_data.rs
index e426d7fe67..847c8843d4 100644
--- a/esp32h2/src/ieee802154/core_dummy_data.rs
+++ b/esp32h2/src/ieee802154/core_dummy_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_DUMMY_DATA")
-            .field(
-                "core_dummy_data",
-                &format_args!("{}", self.core_dummy_data().bits()),
-            )
+            .field("core_dummy_data", &self.core_dummy_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_DUMMY_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/core_gck_cfg.rs b/esp32h2/src/ieee802154/core_gck_cfg.rs
index 5f9b39d6c3..dea2e43a93 100644
--- a/esp32h2/src/ieee802154/core_gck_cfg.rs
+++ b/esp32h2/src/ieee802154/core_gck_cfg.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_GCK_CFG")
-            .field("dis_pkt_gck", &format_args!("{}", self.dis_pkt_gck().bit()))
-            .field(
-                "dis_ctrl_gck",
-                &format_args!("{}", self.dis_ctrl_gck().bit()),
-            )
+            .field("dis_pkt_gck", &self.dis_pkt_gck())
+            .field("dis_ctrl_gck", &self.dis_ctrl_gck())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_GCK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/crc_error_cnt.rs b/esp32h2/src/ieee802154/crc_error_cnt.rs
index a85c26ddc8..b68644847b 100644
--- a/esp32h2/src/ieee802154/crc_error_cnt.rs
+++ b/esp32h2/src/ieee802154/crc_error_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CRC_ERROR_CNT")
-            .field(
-                "crc_error_cnt",
-                &format_args!("{}", self.crc_error_cnt().bits()),
-            )
+            .field("crc_error_cnt", &self.crc_error_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CRC_ERROR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/ctrl_cfg.rs b/esp32h2/src/ieee802154/ctrl_cfg.rs
index 4035706643..565ed9f92f 100644
--- a/esp32h2/src/ieee802154/ctrl_cfg.rs
+++ b/esp32h2/src/ieee802154/ctrl_cfg.rs
@@ -170,84 +170,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL_CFG")
-            .field(
-                "hw_auto_ack_tx_en",
-                &format_args!("{}", self.hw_auto_ack_tx_en().bit()),
-            )
-            .field(
-                "hw_enhance_ack_tx_en",
-                &format_args!("{}", self.hw_enhance_ack_tx_en().bit()),
-            )
-            .field(
-                "hw_auto_ack_rx_en",
-                &format_args!("{}", self.hw_auto_ack_rx_en().bit()),
-            )
-            .field(
-                "dis_ifs_control",
-                &format_args!("{}", self.dis_ifs_control().bit()),
-            )
-            .field(
-                "pan_coordinator",
-                &format_args!("{}", self.pan_coordinator().bit()),
-            )
-            .field(
-                "promiscuous_mode",
-                &format_args!("{}", self.promiscuous_mode().bit()),
-            )
+            .field("hw_auto_ack_tx_en", &self.hw_auto_ack_tx_en())
+            .field("hw_enhance_ack_tx_en", &self.hw_enhance_ack_tx_en())
+            .field("hw_auto_ack_rx_en", &self.hw_auto_ack_rx_en())
+            .field("dis_ifs_control", &self.dis_ifs_control())
+            .field("pan_coordinator", &self.pan_coordinator())
+            .field("promiscuous_mode", &self.promiscuous_mode())
             .field(
                 "dis_frame_version_rsv_filter",
-                &format_args!("{}", self.dis_frame_version_rsv_filter().bit()),
-            )
-            .field(
-                "autopend_enhance",
-                &format_args!("{}", self.autopend_enhance().bit()),
-            )
-            .field(
-                "filter_enhance",
-                &format_args!("{}", self.filter_enhance().bit()),
-            )
-            .field(
-                "coex_arb_delay",
-                &format_args!("{}", self.coex_arb_delay().bits()),
-            )
-            .field("bit_order", &format_args!("{}", self.bit_order().bit()))
-            .field(
-                "no_rss_trk_enb",
-                &format_args!("{}", self.no_rss_trk_enb().bit()),
-            )
-            .field(
-                "force_rx_enb",
-                &format_args!("{}", self.force_rx_enb().bit()),
-            )
-            .field(
-                "rx_done_trigger_idle",
-                &format_args!("{}", self.rx_done_trigger_idle().bit()),
-            )
-            .field(
-                "mac_inf0_enable",
-                &format_args!("{}", self.mac_inf0_enable().bit()),
-            )
-            .field(
-                "mac_inf1_enable",
-                &format_args!("{}", self.mac_inf1_enable().bit()),
-            )
-            .field(
-                "mac_inf2_enable",
-                &format_args!("{}", self.mac_inf2_enable().bit()),
-            )
-            .field(
-                "mac_inf3_enable",
-                &format_args!("{}", self.mac_inf3_enable().bit()),
+                &self.dis_frame_version_rsv_filter(),
             )
+            .field("autopend_enhance", &self.autopend_enhance())
+            .field("filter_enhance", &self.filter_enhance())
+            .field("coex_arb_delay", &self.coex_arb_delay())
+            .field("bit_order", &self.bit_order())
+            .field("no_rss_trk_enb", &self.no_rss_trk_enb())
+            .field("force_rx_enb", &self.force_rx_enb())
+            .field("rx_done_trigger_idle", &self.rx_done_trigger_idle())
+            .field("mac_inf0_enable", &self.mac_inf0_enable())
+            .field("mac_inf1_enable", &self.mac_inf1_enable())
+            .field("mac_inf2_enable", &self.mac_inf2_enable())
+            .field("mac_inf3_enable", &self.mac_inf3_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/dcdc_ctrl.rs b/esp32h2/src/ieee802154/dcdc_ctrl.rs
index 70ffe156cd..5168c20d91 100644
--- a/esp32h2/src/ieee802154/dcdc_ctrl.rs
+++ b/esp32h2/src/ieee802154/dcdc_ctrl.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCDC_CTRL")
-            .field(
-                "dcdc_pre_up_delay",
-                &format_args!("{}", self.dcdc_pre_up_delay().bits()),
-            )
-            .field(
-                "dcdc_down_delay",
-                &format_args!("{}", self.dcdc_down_delay().bits()),
-            )
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("tx_dcdc_up", &format_args!("{}", self.tx_dcdc_up().bit()))
+            .field("dcdc_pre_up_delay", &self.dcdc_pre_up_delay())
+            .field("dcdc_down_delay", &self.dcdc_down_delay())
+            .field("en", &self.en())
+            .field("tx_dcdc_up", &self.tx_dcdc_up())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCDC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/debug_ctrl.rs b/esp32h2/src/ieee802154/debug_ctrl.rs
index 182a6cae69..91568ca9e9 100644
--- a/esp32h2/src/ieee802154/debug_ctrl.rs
+++ b/esp32h2/src/ieee802154/debug_ctrl.rs
@@ -71,43 +71,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEBUG_CTRL")
-            .field(
-                "debug_signal_sel",
-                &format_args!("{}", self.debug_signal_sel().bits()),
-            )
+            .field("debug_signal_sel", &self.debug_signal_sel())
             .field(
                 "debug_trigger_state_select",
-                &format_args!("{}", self.debug_trigger_state_select().bits()),
-            )
-            .field(
-                "debug_ser_debug_sel",
-                &format_args!("{}", self.debug_ser_debug_sel().bits()),
+                &self.debug_trigger_state_select(),
             )
+            .field("debug_ser_debug_sel", &self.debug_ser_debug_sel())
             .field(
                 "debug_trigger_state_match_value",
-                &format_args!("{}", self.debug_trigger_state_match_value().bits()),
+                &self.debug_trigger_state_match_value(),
             )
             .field(
                 "debug_trigger_pulse_select",
-                &format_args!("{}", self.debug_trigger_pulse_select().bits()),
+                &self.debug_trigger_pulse_select(),
             )
             .field(
                 "debug_state_match_dump_en",
-                &format_args!("{}", self.debug_state_match_dump_en().bit()),
-            )
-            .field(
-                "debug_trigger_dump_en",
-                &format_args!("{}", self.debug_trigger_dump_en().bit()),
+                &self.debug_state_match_dump_en(),
             )
+            .field("debug_trigger_dump_en", &self.debug_trigger_dump_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBUG_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/debug_sel_cfg0.rs b/esp32h2/src/ieee802154/debug_sel_cfg0.rs
index 3802f7a5e2..da4d25b423 100644
--- a/esp32h2/src/ieee802154/debug_sel_cfg0.rs
+++ b/esp32h2/src/ieee802154/debug_sel_cfg0.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEBUG_SEL_CFG0")
-            .field(
-                "debug_field0_sel",
-                &format_args!("{}", self.debug_field0_sel().bits()),
-            )
-            .field(
-                "debug_field1_sel",
-                &format_args!("{}", self.debug_field1_sel().bits()),
-            )
-            .field(
-                "debug_field2_sel",
-                &format_args!("{}", self.debug_field2_sel().bits()),
-            )
-            .field(
-                "debug_field3_sel",
-                &format_args!("{}", self.debug_field3_sel().bits()),
-            )
+            .field("debug_field0_sel", &self.debug_field0_sel())
+            .field("debug_field1_sel", &self.debug_field1_sel())
+            .field("debug_field2_sel", &self.debug_field2_sel())
+            .field("debug_field3_sel", &self.debug_field3_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBUG_SEL_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/debug_sel_cfg1.rs b/esp32h2/src/ieee802154/debug_sel_cfg1.rs
index b5e5841361..5a5a18e938 100644
--- a/esp32h2/src/ieee802154/debug_sel_cfg1.rs
+++ b/esp32h2/src/ieee802154/debug_sel_cfg1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEBUG_SEL_CFG1")
-            .field(
-                "debug_field4_sel",
-                &format_args!("{}", self.debug_field4_sel().bits()),
-            )
-            .field(
-                "debug_field5_sel",
-                &format_args!("{}", self.debug_field5_sel().bits()),
-            )
-            .field(
-                "debug_field6_sel",
-                &format_args!("{}", self.debug_field6_sel().bits()),
-            )
-            .field(
-                "debug_field7_sel",
-                &format_args!("{}", self.debug_field7_sel().bits()),
-            )
+            .field("debug_field4_sel", &self.debug_field4_sel())
+            .field("debug_field5_sel", &self.debug_field5_sel())
+            .field("debug_field6_sel", &self.debug_field6_sel())
+            .field("debug_field7_sel", &self.debug_field7_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBUG_SEL_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/dma_dummy.rs b/esp32h2/src/ieee802154/dma_dummy.rs
index 12ae8e7af9..192dc0c201 100644
--- a/esp32h2/src/ieee802154/dma_dummy.rs
+++ b/esp32h2/src/ieee802154/dma_dummy.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_DUMMY")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_DUMMY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/dma_gck_cfg.rs b/esp32h2/src/ieee802154/dma_gck_cfg.rs
index 02b2c5ae4e..626c1ca6b1 100644
--- a/esp32h2/src/ieee802154/dma_gck_cfg.rs
+++ b/esp32h2/src/ieee802154/dma_gck_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_GCK_CFG")
-            .field("dma_gck_cfg", &format_args!("{}", self.dma_gck_cfg().bit()))
+            .field("dma_gck_cfg", &self.dma_gck_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_GCK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/dtm_config.rs b/esp32h2/src/ieee802154/dtm_config.rs
index 1910cf9ae7..b45b51b238 100644
--- a/esp32h2/src/ieee802154/dtm_config.rs
+++ b/esp32h2/src/ieee802154/dtm_config.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DTM_CONFIG")
-            .field(
-                "dtmch_tx_length",
-                &format_args!("{}", self.dtmch_tx_length().bits()),
-            )
-            .field(
-                "dtm_tx_pld_type",
-                &format_args!("{}", self.dtm_tx_pld_type().bits()),
-            )
-            .field(
-                "dtm_hop_freq",
-                &format_args!("{}", self.dtm_hop_freq().bits()),
-            )
-            .field(
-                "dtm_contrx_en",
-                &format_args!("{}", self.dtm_contrx_en().bit()),
-            )
-            .field("dtm_on", &format_args!("{}", self.dtm_on().bit()))
+            .field("dtmch_tx_length", &self.dtmch_tx_length())
+            .field("dtm_tx_pld_type", &self.dtm_tx_pld_type())
+            .field("dtm_hop_freq", &self.dtm_hop_freq())
+            .field("dtm_contrx_en", &self.dtm_contrx_en())
+            .field("dtm_on", &self.dtm_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DTM_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/dtm_pkt_counter.rs b/esp32h2/src/ieee802154/dtm_pkt_counter.rs
index 78af4f5eab..c883c06c29 100644
--- a/esp32h2/src/ieee802154/dtm_pkt_counter.rs
+++ b/esp32h2/src/ieee802154/dtm_pkt_counter.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DTM_PKT_COUNTER")
-            .field(
-                "dtm_txrx_pkt_count",
-                &format_args!("{}", self.dtm_txrx_pkt_count().bits()),
-            )
-            .field(
-                "dtm_crc_err_pkt_count",
-                &format_args!("{}", self.dtm_crc_err_pkt_count().bits()),
-            )
+            .field("dtm_txrx_pkt_count", &self.dtm_txrx_pkt_count())
+            .field("dtm_crc_err_pkt_count", &self.dtm_crc_err_pkt_count())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DTM_PKT_COUNTER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/dtm_tx_pkt_config.rs b/esp32h2/src/ieee802154/dtm_tx_pkt_config.rs
index 34496d5b6a..5d3a9541ca 100644
--- a/esp32h2/src/ieee802154/dtm_tx_pkt_config.rs
+++ b/esp32h2/src/ieee802154/dtm_tx_pkt_config.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DTM_TX_PKT_CONFIG")
-            .field(
-                "dtm_tx_pkt_threshold",
-                &format_args!("{}", self.dtm_tx_pkt_threshold().bits()),
-            )
+            .field("dtm_tx_pkt_threshold", &self.dtm_tx_pkt_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DTM_TX_PKT_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/ed_abort_cnt.rs b/esp32h2/src/ieee802154/ed_abort_cnt.rs
index ca5c73d89a..1f06edc663 100644
--- a/esp32h2/src/ieee802154/ed_abort_cnt.rs
+++ b/esp32h2/src/ieee802154/ed_abort_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ED_ABORT_CNT")
-            .field(
-                "ed_abort_cnt",
-                &format_args!("{}", self.ed_abort_cnt().bits()),
-            )
+            .field("ed_abort_cnt", &self.ed_abort_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ED_ABORT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/ed_scan_cfg.rs b/esp32h2/src/ieee802154/ed_scan_cfg.rs
index fa9bf031c6..888c4525ad 100644
--- a/esp32h2/src/ieee802154/ed_scan_cfg.rs
+++ b/esp32h2/src/ieee802154/ed_scan_cfg.rs
@@ -62,30 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ED_SCAN_CFG")
-            .field(
-                "cca_ed_threshold",
-                &format_args!("{}", self.cca_ed_threshold().bits()),
-            )
-            .field(
-                "ed_sample_mode",
-                &format_args!("{}", self.ed_sample_mode().bits()),
-            )
-            .field(
-                "dis_ed_power_sel",
-                &format_args!("{}", self.dis_ed_power_sel().bit()),
-            )
-            .field("cca_mode", &format_args!("{}", self.cca_mode().bits()))
-            .field("ed_rss", &format_args!("{}", self.ed_rss().bits()))
-            .field("cca_busy", &format_args!("{}", self.cca_busy().bit()))
+            .field("cca_ed_threshold", &self.cca_ed_threshold())
+            .field("ed_sample_mode", &self.ed_sample_mode())
+            .field("dis_ed_power_sel", &self.dis_ed_power_sel())
+            .field("cca_mode", &self.cca_mode())
+            .field("ed_rss", &self.ed_rss())
+            .field("cca_busy", &self.cca_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ED_SCAN_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/ed_scan_coex_cnt.rs b/esp32h2/src/ieee802154/ed_scan_coex_cnt.rs
index a513b9b15a..d3b55c8c4e 100644
--- a/esp32h2/src/ieee802154/ed_scan_coex_cnt.rs
+++ b/esp32h2/src/ieee802154/ed_scan_coex_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ED_SCAN_COEX_CNT")
-            .field(
-                "ed_scan_coex_cnt",
-                &format_args!("{}", self.ed_scan_coex_cnt().bits()),
-            )
+            .field("ed_scan_coex_cnt", &self.ed_scan_coex_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ED_SCAN_COEX_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/ed_scan_duration.rs b/esp32h2/src/ieee802154/ed_scan_duration.rs
index 3cec1e1c01..c0122aa4e7 100644
--- a/esp32h2/src/ieee802154/ed_scan_duration.rs
+++ b/esp32h2/src/ieee802154/ed_scan_duration.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ED_SCAN_DURATION")
-            .field(
-                "ed_scan_duration",
-                &format_args!("{}", self.ed_scan_duration().bits()),
-            )
-            .field(
-                "ed_scan_wait_dly",
-                &format_args!("{}", self.ed_scan_wait_dly().bits()),
-            )
+            .field("ed_scan_duration", &self.ed_scan_duration())
+            .field("ed_scan_wait_dly", &self.ed_scan_wait_dly())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ED_SCAN_DURATION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/enhance_ack_cfg.rs b/esp32h2/src/ieee802154/enhance_ack_cfg.rs
index 1726262510..5c40773c29 100644
--- a/esp32h2/src/ieee802154/enhance_ack_cfg.rs
+++ b/esp32h2/src/ieee802154/enhance_ack_cfg.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ENHANCE_ACK_CFG")
             .field(
                 "tx_enh_ack_generate_done_notify",
-                &format_args!("{}", self.tx_enh_ack_generate_done_notify().bits()),
+                &self.tx_enh_ack_generate_done_notify(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENHANCE_ACK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/error_cnt_clear.rs b/esp32h2/src/ieee802154/error_cnt_clear.rs
index e15bb4e889..9e4c04b6b2 100644
--- a/esp32h2/src/ieee802154/error_cnt_clear.rs
+++ b/esp32h2/src/ieee802154/error_cnt_clear.rs
@@ -143,75 +143,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERROR_CNT_CLEAR")
-            .field(
-                "cca_busy_cnt_clear",
-                &format_args!("{}", self.cca_busy_cnt_clear().bit()),
-            )
+            .field("cca_busy_cnt_clear", &self.cca_busy_cnt_clear())
             .field(
                 "tx_security_error_cnt_clear",
-                &format_args!("{}", self.tx_security_error_cnt_clear().bit()),
-            )
-            .field(
-                "tx_break_coex_cnt_clear",
-                &format_args!("{}", self.tx_break_coex_cnt_clear().bit()),
-            )
-            .field(
-                "rx_ack_timeout_cnt_clear",
-                &format_args!("{}", self.rx_ack_timeout_cnt_clear().bit()),
+                &self.tx_security_error_cnt_clear(),
             )
+            .field("tx_break_coex_cnt_clear", &self.tx_break_coex_cnt_clear())
+            .field("rx_ack_timeout_cnt_clear", &self.rx_ack_timeout_cnt_clear())
             .field(
                 "rx_ack_abort_coex_cnt_clear",
-                &format_args!("{}", self.rx_ack_abort_coex_cnt_clear().bit()),
-            )
-            .field(
-                "ed_scan_coex_cnt_clear",
-                &format_args!("{}", self.ed_scan_coex_cnt_clear().bit()),
+                &self.rx_ack_abort_coex_cnt_clear(),
             )
+            .field("ed_scan_coex_cnt_clear", &self.ed_scan_coex_cnt_clear())
             .field(
                 "tx_ack_abort_coex_cnt_clear",
-                &format_args!("{}", self.tx_ack_abort_coex_cnt_clear().bit()),
-            )
-            .field(
-                "rx_restart_cnt_clear",
-                &format_args!("{}", self.rx_restart_cnt_clear().bit()),
-            )
-            .field(
-                "rx_abort_coex_cnt_clear",
-                &format_args!("{}", self.rx_abort_coex_cnt_clear().bit()),
-            )
-            .field(
-                "no_rss_detect_cnt_clear",
-                &format_args!("{}", self.no_rss_detect_cnt_clear().bit()),
-            )
-            .field(
-                "rx_filter_fail_cnt_clear",
-                &format_args!("{}", self.rx_filter_fail_cnt_clear().bit()),
-            )
-            .field(
-                "cca_fail_cnt_clear",
-                &format_args!("{}", self.cca_fail_cnt_clear().bit()),
-            )
-            .field(
-                "ed_abort_cnt_clear",
-                &format_args!("{}", self.ed_abort_cnt_clear().bit()),
-            )
-            .field(
-                "crc_error_cnt_clear",
-                &format_args!("{}", self.crc_error_cnt_clear().bit()),
-            )
-            .field(
-                "sfd_timeout_cnt_clear",
-                &format_args!("{}", self.sfd_timeout_cnt_clear().bit()),
+                &self.tx_ack_abort_coex_cnt_clear(),
             )
+            .field("rx_restart_cnt_clear", &self.rx_restart_cnt_clear())
+            .field("rx_abort_coex_cnt_clear", &self.rx_abort_coex_cnt_clear())
+            .field("no_rss_detect_cnt_clear", &self.no_rss_detect_cnt_clear())
+            .field("rx_filter_fail_cnt_clear", &self.rx_filter_fail_cnt_clear())
+            .field("cca_fail_cnt_clear", &self.cca_fail_cnt_clear())
+            .field("ed_abort_cnt_clear", &self.ed_abort_cnt_clear())
+            .field("crc_error_cnt_clear", &self.crc_error_cnt_clear())
+            .field("sfd_timeout_cnt_clear", &self.sfd_timeout_cnt_clear())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERROR_CNT_CLEAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/event_en.rs b/esp32h2/src/ieee802154/event_en.rs
index 882575b675..f15edeb72f 100644
--- a/esp32h2/src/ieee802154/event_en.rs
+++ b/esp32h2/src/ieee802154/event_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVENT_EN")
-            .field("event_en", &format_args!("{}", self.event_en().bits()))
+            .field("event_en", &self.event_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVENT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/event_status.rs b/esp32h2/src/ieee802154/event_status.rs
index c0cc0658e8..cdf1600a4e 100644
--- a/esp32h2/src/ieee802154/event_status.rs
+++ b/esp32h2/src/ieee802154/event_status.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVENT_STATUS")
-            .field(
-                "event_status",
-                &format_args!("{}", self.event_status().bits()),
-            )
+            .field("event_status", &self.event_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVENT_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/ifs.rs b/esp32h2/src/ieee802154/ifs.rs
index 3cffb146c9..89aa1000ed 100644
--- a/esp32h2/src/ieee802154/ifs.rs
+++ b/esp32h2/src/ieee802154/ifs.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IFS")
-            .field("sifs", &format_args!("{}", self.sifs().bits()))
-            .field("lifs", &format_args!("{}", self.lifs().bits()))
+            .field("sifs", &self.sifs())
+            .field("lifs", &self.lifs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IFS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/ifs_counter.rs b/esp32h2/src/ieee802154/ifs_counter.rs
index 9bc0520ead..08f7849433 100644
--- a/esp32h2/src/ieee802154/ifs_counter.rs
+++ b/esp32h2/src/ieee802154/ifs_counter.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IFS_COUNTER")
-            .field(
-                "ifs_counter",
-                &format_args!("{}", self.ifs_counter().bits()),
-            )
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("ifs_counter", &self.ifs_counter())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IFS_COUNTER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf0_extend_addr0.rs b/esp32h2/src/ieee802154/inf0_extend_addr0.rs
index d5daf06551..14c7fa2b4a 100644
--- a/esp32h2/src/ieee802154/inf0_extend_addr0.rs
+++ b/esp32h2/src/ieee802154/inf0_extend_addr0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF0_EXTEND_ADDR0")
-            .field(
-                "mac_inf0_extend_addr0",
-                &format_args!("{}", self.mac_inf0_extend_addr0().bits()),
-            )
+            .field("mac_inf0_extend_addr0", &self.mac_inf0_extend_addr0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF0_EXTEND_ADDR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf0_extend_addr1.rs b/esp32h2/src/ieee802154/inf0_extend_addr1.rs
index c3620d8d70..269e6b75b3 100644
--- a/esp32h2/src/ieee802154/inf0_extend_addr1.rs
+++ b/esp32h2/src/ieee802154/inf0_extend_addr1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF0_EXTEND_ADDR1")
-            .field(
-                "mac_inf0_extend_addr1",
-                &format_args!("{}", self.mac_inf0_extend_addr1().bits()),
-            )
+            .field("mac_inf0_extend_addr1", &self.mac_inf0_extend_addr1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF0_EXTEND_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf0_pan_id.rs b/esp32h2/src/ieee802154/inf0_pan_id.rs
index b9cdabc6a7..df03bec0c9 100644
--- a/esp32h2/src/ieee802154/inf0_pan_id.rs
+++ b/esp32h2/src/ieee802154/inf0_pan_id.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF0_PAN_ID")
-            .field(
-                "mac_inf0_pan_id",
-                &format_args!("{}", self.mac_inf0_pan_id().bits()),
-            )
+            .field("mac_inf0_pan_id", &self.mac_inf0_pan_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF0_PAN_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf0_short_addr.rs b/esp32h2/src/ieee802154/inf0_short_addr.rs
index eccee8dfb7..43949e1b8e 100644
--- a/esp32h2/src/ieee802154/inf0_short_addr.rs
+++ b/esp32h2/src/ieee802154/inf0_short_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF0_SHORT_ADDR")
-            .field(
-                "mac_inf0_short_addr",
-                &format_args!("{}", self.mac_inf0_short_addr().bits()),
-            )
+            .field("mac_inf0_short_addr", &self.mac_inf0_short_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF0_SHORT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf1_extend_addr0.rs b/esp32h2/src/ieee802154/inf1_extend_addr0.rs
index d40dae7c13..161a99a504 100644
--- a/esp32h2/src/ieee802154/inf1_extend_addr0.rs
+++ b/esp32h2/src/ieee802154/inf1_extend_addr0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF1_EXTEND_ADDR0")
-            .field(
-                "mac_inf1_extend_addr0",
-                &format_args!("{}", self.mac_inf1_extend_addr0().bits()),
-            )
+            .field("mac_inf1_extend_addr0", &self.mac_inf1_extend_addr0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF1_EXTEND_ADDR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf1_extend_addr1.rs b/esp32h2/src/ieee802154/inf1_extend_addr1.rs
index a65de5ea3b..622d8b0c3c 100644
--- a/esp32h2/src/ieee802154/inf1_extend_addr1.rs
+++ b/esp32h2/src/ieee802154/inf1_extend_addr1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF1_EXTEND_ADDR1")
-            .field(
-                "mac_inf1_extend_addr1",
-                &format_args!("{}", self.mac_inf1_extend_addr1().bits()),
-            )
+            .field("mac_inf1_extend_addr1", &self.mac_inf1_extend_addr1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF1_EXTEND_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf1_pan_id.rs b/esp32h2/src/ieee802154/inf1_pan_id.rs
index 446bbde96d..d92a995164 100644
--- a/esp32h2/src/ieee802154/inf1_pan_id.rs
+++ b/esp32h2/src/ieee802154/inf1_pan_id.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF1_PAN_ID")
-            .field(
-                "mac_inf1_pan_id",
-                &format_args!("{}", self.mac_inf1_pan_id().bits()),
-            )
+            .field("mac_inf1_pan_id", &self.mac_inf1_pan_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF1_PAN_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf1_short_addr.rs b/esp32h2/src/ieee802154/inf1_short_addr.rs
index c4591d8c7c..3a8260b757 100644
--- a/esp32h2/src/ieee802154/inf1_short_addr.rs
+++ b/esp32h2/src/ieee802154/inf1_short_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF1_SHORT_ADDR")
-            .field(
-                "mac_inf1_short_addr",
-                &format_args!("{}", self.mac_inf1_short_addr().bits()),
-            )
+            .field("mac_inf1_short_addr", &self.mac_inf1_short_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF1_SHORT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf2_extend_addr0.rs b/esp32h2/src/ieee802154/inf2_extend_addr0.rs
index b67a30a491..16209ac6cf 100644
--- a/esp32h2/src/ieee802154/inf2_extend_addr0.rs
+++ b/esp32h2/src/ieee802154/inf2_extend_addr0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF2_EXTEND_ADDR0")
-            .field(
-                "mac_inf2_extend_addr0",
-                &format_args!("{}", self.mac_inf2_extend_addr0().bits()),
-            )
+            .field("mac_inf2_extend_addr0", &self.mac_inf2_extend_addr0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF2_EXTEND_ADDR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf2_extend_addr1.rs b/esp32h2/src/ieee802154/inf2_extend_addr1.rs
index a7c70b708b..ebf9837339 100644
--- a/esp32h2/src/ieee802154/inf2_extend_addr1.rs
+++ b/esp32h2/src/ieee802154/inf2_extend_addr1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF2_EXTEND_ADDR1")
-            .field(
-                "mac_inf2_extend_addr1",
-                &format_args!("{}", self.mac_inf2_extend_addr1().bits()),
-            )
+            .field("mac_inf2_extend_addr1", &self.mac_inf2_extend_addr1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF2_EXTEND_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf2_pan_id.rs b/esp32h2/src/ieee802154/inf2_pan_id.rs
index 006e3020b0..6272f0d0e1 100644
--- a/esp32h2/src/ieee802154/inf2_pan_id.rs
+++ b/esp32h2/src/ieee802154/inf2_pan_id.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF2_PAN_ID")
-            .field(
-                "mac_inf2_pan_id",
-                &format_args!("{}", self.mac_inf2_pan_id().bits()),
-            )
+            .field("mac_inf2_pan_id", &self.mac_inf2_pan_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF2_PAN_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf2_short_addr.rs b/esp32h2/src/ieee802154/inf2_short_addr.rs
index e49c3b11b8..b9de1efaaa 100644
--- a/esp32h2/src/ieee802154/inf2_short_addr.rs
+++ b/esp32h2/src/ieee802154/inf2_short_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF2_SHORT_ADDR")
-            .field(
-                "mac_inf2_short_addr",
-                &format_args!("{}", self.mac_inf2_short_addr().bits()),
-            )
+            .field("mac_inf2_short_addr", &self.mac_inf2_short_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF2_SHORT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf3_extend_addr0.rs b/esp32h2/src/ieee802154/inf3_extend_addr0.rs
index 7d34864f0b..02da5ac83b 100644
--- a/esp32h2/src/ieee802154/inf3_extend_addr0.rs
+++ b/esp32h2/src/ieee802154/inf3_extend_addr0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF3_EXTEND_ADDR0")
-            .field(
-                "mac_inf3_extend_addr0",
-                &format_args!("{}", self.mac_inf3_extend_addr0().bits()),
-            )
+            .field("mac_inf3_extend_addr0", &self.mac_inf3_extend_addr0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF3_EXTEND_ADDR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf3_extend_addr1.rs b/esp32h2/src/ieee802154/inf3_extend_addr1.rs
index 68a13eff7d..65c8b21024 100644
--- a/esp32h2/src/ieee802154/inf3_extend_addr1.rs
+++ b/esp32h2/src/ieee802154/inf3_extend_addr1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF3_EXTEND_ADDR1")
-            .field(
-                "mac_inf3_extend_addr1",
-                &format_args!("{}", self.mac_inf3_extend_addr1().bits()),
-            )
+            .field("mac_inf3_extend_addr1", &self.mac_inf3_extend_addr1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF3_EXTEND_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf3_pan_id.rs b/esp32h2/src/ieee802154/inf3_pan_id.rs
index 4e65ecf31f..abe913e716 100644
--- a/esp32h2/src/ieee802154/inf3_pan_id.rs
+++ b/esp32h2/src/ieee802154/inf3_pan_id.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF3_PAN_ID")
-            .field(
-                "mac_inf3_pan_id",
-                &format_args!("{}", self.mac_inf3_pan_id().bits()),
-            )
+            .field("mac_inf3_pan_id", &self.mac_inf3_pan_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF3_PAN_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/inf3_short_addr.rs b/esp32h2/src/ieee802154/inf3_short_addr.rs
index aacca01029..39d7231acb 100644
--- a/esp32h2/src/ieee802154/inf3_short_addr.rs
+++ b/esp32h2/src/ieee802154/inf3_short_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INF3_SHORT_ADDR")
-            .field(
-                "mac_inf3_short_addr",
-                &format_args!("{}", self.mac_inf3_short_addr().bits()),
-            )
+            .field("mac_inf3_short_addr", &self.mac_inf3_short_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INF3_SHORT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/mac_date.rs b/esp32h2/src/ieee802154/mac_date.rs
index 3280d36252..423244aba5 100644
--- a/esp32h2/src/ieee802154/mac_date.rs
+++ b/esp32h2/src/ieee802154/mac_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAC_DATE")
-            .field("mac_date", &format_args!("{}", self.mac_date().bits()))
+            .field("mac_date", &self.mac_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAC_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/no_rss_detect_cnt.rs b/esp32h2/src/ieee802154/no_rss_detect_cnt.rs
index 68947fab03..a25e47e151 100644
--- a/esp32h2/src/ieee802154/no_rss_detect_cnt.rs
+++ b/esp32h2/src/ieee802154/no_rss_detect_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NO_RSS_DETECT_CNT")
-            .field(
-                "no_rss_detect_cnt",
-                &format_args!("{}", self.no_rss_detect_cnt().bits()),
-            )
+            .field("no_rss_detect_cnt", &self.no_rss_detect_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NO_RSS_DETECT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/paon_delay.rs b/esp32h2/src/ieee802154/paon_delay.rs
index b908f6fe3f..f080065b18 100644
--- a/esp32h2/src/ieee802154/paon_delay.rs
+++ b/esp32h2/src/ieee802154/paon_delay.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAON_DELAY")
-            .field("paon_delay", &format_args!("{}", self.paon_delay().bits()))
+            .field("paon_delay", &self.paon_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAON_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/rx_abort_coex_cnt.rs b/esp32h2/src/ieee802154/rx_abort_coex_cnt.rs
index 4beacb0a13..e275ae73bf 100644
--- a/esp32h2/src/ieee802154/rx_abort_coex_cnt.rs
+++ b/esp32h2/src/ieee802154/rx_abort_coex_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ABORT_COEX_CNT")
-            .field(
-                "rx_abort_coex_cnt",
-                &format_args!("{}", self.rx_abort_coex_cnt().bits()),
-            )
+            .field("rx_abort_coex_cnt", &self.rx_abort_coex_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ABORT_COEX_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/rx_abort_intr_ctrl.rs b/esp32h2/src/ieee802154/rx_abort_intr_ctrl.rs
index d26980ed4d..b0fb9a221e 100644
--- a/esp32h2/src/ieee802154/rx_abort_intr_ctrl.rs
+++ b/esp32h2/src/ieee802154/rx_abort_intr_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ABORT_INTR_CTRL")
-            .field(
-                "rx_abort_intr_ctrl",
-                &format_args!("{}", self.rx_abort_intr_ctrl().bits()),
-            )
+            .field("rx_abort_intr_ctrl", &self.rx_abort_intr_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ABORT_INTR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/rx_ack_abort_coex_cnt.rs b/esp32h2/src/ieee802154/rx_ack_abort_coex_cnt.rs
index 80887b5c5c..949dea2ff9 100644
--- a/esp32h2/src/ieee802154/rx_ack_abort_coex_cnt.rs
+++ b/esp32h2/src/ieee802154/rx_ack_abort_coex_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ACK_ABORT_COEX_CNT")
-            .field(
-                "rx_ack_abort_coex_cnt",
-                &format_args!("{}", self.rx_ack_abort_coex_cnt().bits()),
-            )
+            .field("rx_ack_abort_coex_cnt", &self.rx_ack_abort_coex_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ACK_ABORT_COEX_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/rx_ack_timeout_cnt.rs b/esp32h2/src/ieee802154/rx_ack_timeout_cnt.rs
index b14a4862b2..11d598f61d 100644
--- a/esp32h2/src/ieee802154/rx_ack_timeout_cnt.rs
+++ b/esp32h2/src/ieee802154/rx_ack_timeout_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ACK_TIMEOUT_CNT")
-            .field(
-                "rx_ack_timeout_cnt",
-                &format_args!("{}", self.rx_ack_timeout_cnt().bits()),
-            )
+            .field("rx_ack_timeout_cnt", &self.rx_ack_timeout_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ACK_TIMEOUT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/rx_filter_fail_cnt.rs b/esp32h2/src/ieee802154/rx_filter_fail_cnt.rs
index 524fb2834a..e23abed76b 100644
--- a/esp32h2/src/ieee802154/rx_filter_fail_cnt.rs
+++ b/esp32h2/src/ieee802154/rx_filter_fail_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_FILTER_FAIL_CNT")
-            .field(
-                "rx_filter_fail_cnt",
-                &format_args!("{}", self.rx_filter_fail_cnt().bits()),
-            )
+            .field("rx_filter_fail_cnt", &self.rx_filter_fail_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_FILTER_FAIL_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/rx_length.rs b/esp32h2/src/ieee802154/rx_length.rs
index d6dafb7ef6..f44d5c1008 100644
--- a/esp32h2/src/ieee802154/rx_length.rs
+++ b/esp32h2/src/ieee802154/rx_length.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_LENGTH")
-            .field("rx_length", &format_args!("{}", self.rx_length().bits()))
+            .field("rx_length", &self.rx_length())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_LENGTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/rx_restart_cnt.rs b/esp32h2/src/ieee802154/rx_restart_cnt.rs
index d5c1dae943..b0a8edb7a0 100644
--- a/esp32h2/src/ieee802154/rx_restart_cnt.rs
+++ b/esp32h2/src/ieee802154/rx_restart_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_RESTART_CNT")
-            .field(
-                "rx_restart_cnt",
-                &format_args!("{}", self.rx_restart_cnt().bits()),
-            )
+            .field("rx_restart_cnt", &self.rx_restart_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_RESTART_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/rx_status.rs b/esp32h2/src/ieee802154/rx_status.rs
index d15dde1ace..05d8570751 100644
--- a/esp32h2/src/ieee802154/rx_status.rs
+++ b/esp32h2/src/ieee802154/rx_status.rs
@@ -53,29 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_STATUS")
-            .field(
-                "filter_fail_status",
-                &format_args!("{}", self.filter_fail_status().bits()),
-            )
-            .field(
-                "rx_abort_status",
-                &format_args!("{}", self.rx_abort_status().bits()),
-            )
-            .field("rx_state", &format_args!("{}", self.rx_state().bits()))
-            .field(
-                "preamble_match",
-                &format_args!("{}", self.preamble_match().bit()),
-            )
-            .field("sfd_match", &format_args!("{}", self.sfd_match().bit()))
+            .field("filter_fail_status", &self.filter_fail_status())
+            .field("rx_abort_status", &self.rx_abort_status())
+            .field("rx_state", &self.rx_state())
+            .field("preamble_match", &self.preamble_match())
+            .field("sfd_match", &self.sfd_match())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/rxdma_addr.rs b/esp32h2/src/ieee802154/rxdma_addr.rs
index 0f1507832b..72e1b65151 100644
--- a/esp32h2/src/ieee802154/rxdma_addr.rs
+++ b/esp32h2/src/ieee802154/rxdma_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXDMA_ADDR")
-            .field("rxdma_addr", &format_args!("{}", self.rxdma_addr().bits()))
+            .field("rxdma_addr", &self.rxdma_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXDMA_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/rxdma_ctrl_state.rs b/esp32h2/src/ieee802154/rxdma_ctrl_state.rs
index 793edb2b19..b73a0c2ad0 100644
--- a/esp32h2/src/ieee802154/rxdma_ctrl_state.rs
+++ b/esp32h2/src/ieee802154/rxdma_ctrl_state.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXDMA_CTRL_STATE")
-            .field(
-                "rxdma_water_level",
-                &format_args!("{}", self.rxdma_water_level().bits()),
-            )
-            .field(
-                "rxdma_state",
-                &format_args!("{}", self.rxdma_state().bits()),
-            )
-            .field(
-                "rxdma_append_lqi_offset",
-                &format_args!("{}", self.rxdma_append_lqi_offset().bit()),
-            )
-            .field(
-                "rxdma_append_freq_offset",
-                &format_args!("{}", self.rxdma_append_freq_offset().bit()),
-            )
+            .field("rxdma_water_level", &self.rxdma_water_level())
+            .field("rxdma_state", &self.rxdma_state())
+            .field("rxdma_append_lqi_offset", &self.rxdma_append_lqi_offset())
+            .field("rxdma_append_freq_offset", &self.rxdma_append_freq_offset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXDMA_CTRL_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/rxdma_err.rs b/esp32h2/src/ieee802154/rxdma_err.rs
index 0e68599be1..9bd706d127 100644
--- a/esp32h2/src/ieee802154/rxdma_err.rs
+++ b/esp32h2/src/ieee802154/rxdma_err.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXDMA_ERR")
-            .field("rxdma_err", &format_args!("{}", self.rxdma_err().bits()))
+            .field("rxdma_err", &self.rxdma_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXDMA_ERR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/rxon_delay.rs b/esp32h2/src/ieee802154/rxon_delay.rs
index 59f8efb54c..82c64cadcd 100644
--- a/esp32h2/src/ieee802154/rxon_delay.rs
+++ b/esp32h2/src/ieee802154/rxon_delay.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXON_DELAY")
-            .field("rxon_delay", &format_args!("{}", self.rxon_delay().bits()))
+            .field("rxon_delay", &self.rxon_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXON_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/sec_ctrl.rs b/esp32h2/src/ieee802154/sec_ctrl.rs
index ce7a71f964..a06ca1b830 100644
--- a/esp32h2/src/ieee802154/sec_ctrl.rs
+++ b/esp32h2/src/ieee802154/sec_ctrl.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_CTRL")
-            .field("sec_en", &format_args!("{}", self.sec_en().bit()))
-            .field(
-                "sec_payload_offset",
-                &format_args!("{}", self.sec_payload_offset().bits()),
-            )
+            .field("sec_en", &self.sec_en())
+            .field("sec_payload_offset", &self.sec_payload_offset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/sec_extend_address0.rs b/esp32h2/src/ieee802154/sec_extend_address0.rs
index bcf15ee455..5ad42e9475 100644
--- a/esp32h2/src/ieee802154/sec_extend_address0.rs
+++ b/esp32h2/src/ieee802154/sec_extend_address0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_EXTEND_ADDRESS0")
-            .field(
-                "sec_extend_address0",
-                &format_args!("{}", self.sec_extend_address0().bits()),
-            )
+            .field("sec_extend_address0", &self.sec_extend_address0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_EXTEND_ADDRESS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/sec_extend_address1.rs b/esp32h2/src/ieee802154/sec_extend_address1.rs
index 5980c5a2a9..1c5284c7d1 100644
--- a/esp32h2/src/ieee802154/sec_extend_address1.rs
+++ b/esp32h2/src/ieee802154/sec_extend_address1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_EXTEND_ADDRESS1")
-            .field(
-                "sec_extend_address1",
-                &format_args!("{}", self.sec_extend_address1().bits()),
-            )
+            .field("sec_extend_address1", &self.sec_extend_address1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_EXTEND_ADDRESS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/sec_key0.rs b/esp32h2/src/ieee802154/sec_key0.rs
index f77ab23cc8..d35e2796cc 100644
--- a/esp32h2/src/ieee802154/sec_key0.rs
+++ b/esp32h2/src/ieee802154/sec_key0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_KEY0")
-            .field("sec_key0", &format_args!("{}", self.sec_key0().bits()))
+            .field("sec_key0", &self.sec_key0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_KEY0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/sec_key1.rs b/esp32h2/src/ieee802154/sec_key1.rs
index c23b34df06..e9a5c7109b 100644
--- a/esp32h2/src/ieee802154/sec_key1.rs
+++ b/esp32h2/src/ieee802154/sec_key1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_KEY1")
-            .field("sec_key1", &format_args!("{}", self.sec_key1().bits()))
+            .field("sec_key1", &self.sec_key1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_KEY1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/sec_key2.rs b/esp32h2/src/ieee802154/sec_key2.rs
index ac36dd0427..e1c8f22aba 100644
--- a/esp32h2/src/ieee802154/sec_key2.rs
+++ b/esp32h2/src/ieee802154/sec_key2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_KEY2")
-            .field("sec_key2", &format_args!("{}", self.sec_key2().bits()))
+            .field("sec_key2", &self.sec_key2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_KEY2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/sec_key3.rs b/esp32h2/src/ieee802154/sec_key3.rs
index 314e3c4cbd..4c99eac556 100644
--- a/esp32h2/src/ieee802154/sec_key3.rs
+++ b/esp32h2/src/ieee802154/sec_key3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_KEY3")
-            .field("sec_key3", &format_args!("{}", self.sec_key3().bits()))
+            .field("sec_key3", &self.sec_key3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_KEY3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/sfd_timeout_cnt.rs b/esp32h2/src/ieee802154/sfd_timeout_cnt.rs
index 1a3b328cfe..40025100e1 100644
--- a/esp32h2/src/ieee802154/sfd_timeout_cnt.rs
+++ b/esp32h2/src/ieee802154/sfd_timeout_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SFD_TIMEOUT_CNT")
-            .field(
-                "sfd_timeout_cnt",
-                &format_args!("{}", self.sfd_timeout_cnt().bits()),
-            )
+            .field("sfd_timeout_cnt", &self.sfd_timeout_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SFD_TIMEOUT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/sfd_wait_symbol.rs b/esp32h2/src/ieee802154/sfd_wait_symbol.rs
index 47feb148ce..5701663176 100644
--- a/esp32h2/src/ieee802154/sfd_wait_symbol.rs
+++ b/esp32h2/src/ieee802154/sfd_wait_symbol.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SFD_WAIT_SYMBOL")
-            .field("num", &format_args!("{}", self.num().bits()))
+            .field("num", &self.num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SFD_WAIT_SYMBOL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/test_control.rs b/esp32h2/src/ieee802154/test_control.rs
index 35d829b741..674080aaa0 100644
--- a/esp32h2/src/ieee802154/test_control.rs
+++ b/esp32h2/src/ieee802154/test_control.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEST_CONTROL")
-            .field("wrong_crc", &format_args!("{}", self.wrong_crc().bit()))
+            .field("wrong_crc", &self.wrong_crc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEST_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/time0_threshold.rs b/esp32h2/src/ieee802154/time0_threshold.rs
index 22e4126848..86d7e6c4d4 100644
--- a/esp32h2/src/ieee802154/time0_threshold.rs
+++ b/esp32h2/src/ieee802154/time0_threshold.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME0_THRESHOLD")
-            .field(
-                "timer0_threshold",
-                &format_args!("{}", self.timer0_threshold().bits()),
-            )
+            .field("timer0_threshold", &self.timer0_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME0_THRESHOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/time0_value.rs b/esp32h2/src/ieee802154/time0_value.rs
index 8e97397a2f..3f0f680851 100644
--- a/esp32h2/src/ieee802154/time0_value.rs
+++ b/esp32h2/src/ieee802154/time0_value.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME0_VALUE")
-            .field(
-                "timer0_value",
-                &format_args!("{}", self.timer0_value().bits()),
-            )
+            .field("timer0_value", &self.timer0_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME0_VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/time1_threshold.rs b/esp32h2/src/ieee802154/time1_threshold.rs
index acd0a23999..f68f9cb850 100644
--- a/esp32h2/src/ieee802154/time1_threshold.rs
+++ b/esp32h2/src/ieee802154/time1_threshold.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME1_THRESHOLD")
-            .field(
-                "timer1_threshold",
-                &format_args!("{}", self.timer1_threshold().bits()),
-            )
+            .field("timer1_threshold", &self.timer1_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME1_THRESHOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/time1_value.rs b/esp32h2/src/ieee802154/time1_value.rs
index fb643f1ee1..e36b50b51e 100644
--- a/esp32h2/src/ieee802154/time1_value.rs
+++ b/esp32h2/src/ieee802154/time1_value.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME1_VALUE")
-            .field(
-                "timer1_value",
-                &format_args!("{}", self.timer1_value().bits()),
-            )
+            .field("timer1_value", &self.timer1_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME1_VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/tx_abort_interrupt_control.rs b/esp32h2/src/ieee802154/tx_abort_interrupt_control.rs
index b7cda5f1de..ceb6cee0bb 100644
--- a/esp32h2/src/ieee802154/tx_abort_interrupt_control.rs
+++ b/esp32h2/src/ieee802154/tx_abort_interrupt_control.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("TX_ABORT_INTERRUPT_CONTROL")
             .field(
                 "tx_abort_interrupt_control",
-                &format_args!("{}", self.tx_abort_interrupt_control().bits()),
+                &self.tx_abort_interrupt_control(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_ABORT_INTERRUPT_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/tx_ack_abort_coex_cnt.rs b/esp32h2/src/ieee802154/tx_ack_abort_coex_cnt.rs
index 5e94e74a34..bc802a5131 100644
--- a/esp32h2/src/ieee802154/tx_ack_abort_coex_cnt.rs
+++ b/esp32h2/src/ieee802154/tx_ack_abort_coex_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_ACK_ABORT_COEX_CNT")
-            .field(
-                "tx_ack_abort_coex_cnt",
-                &format_args!("{}", self.tx_ack_abort_coex_cnt().bits()),
-            )
+            .field("tx_ack_abort_coex_cnt", &self.tx_ack_abort_coex_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_ACK_ABORT_COEX_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/tx_break_coex_cnt.rs b/esp32h2/src/ieee802154/tx_break_coex_cnt.rs
index af2d907cc3..fd4d555105 100644
--- a/esp32h2/src/ieee802154/tx_break_coex_cnt.rs
+++ b/esp32h2/src/ieee802154/tx_break_coex_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_BREAK_COEX_CNT")
-            .field(
-                "tx_break_coex_cnt",
-                &format_args!("{}", self.tx_break_coex_cnt().bits()),
-            )
+            .field("tx_break_coex_cnt", &self.tx_break_coex_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_BREAK_COEX_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/tx_ccm_schedule_status.rs b/esp32h2/src/ieee802154/tx_ccm_schedule_status.rs
index 3ccff89786..4df53e5c0a 100644
--- a/esp32h2/src/ieee802154/tx_ccm_schedule_status.rs
+++ b/esp32h2/src/ieee802154/tx_ccm_schedule_status.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CCM_SCHEDULE_STATUS")
-            .field(
-                "tx_ccm_schedule_status",
-                &format_args!("{}", self.tx_ccm_schedule_status().bits()),
-            )
+            .field("tx_ccm_schedule_status", &self.tx_ccm_schedule_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CCM_SCHEDULE_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/tx_power.rs b/esp32h2/src/ieee802154/tx_power.rs
index e70db2a041..8a7f29f818 100644
--- a/esp32h2/src/ieee802154/tx_power.rs
+++ b/esp32h2/src/ieee802154/tx_power.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_POWER")
-            .field("tx_power", &format_args!("{}", self.tx_power().bits()))
+            .field("tx_power", &self.tx_power())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/tx_security_error_cnt.rs b/esp32h2/src/ieee802154/tx_security_error_cnt.rs
index ca8d85ad86..ddf9e39309 100644
--- a/esp32h2/src/ieee802154/tx_security_error_cnt.rs
+++ b/esp32h2/src/ieee802154/tx_security_error_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_SECURITY_ERROR_CNT")
-            .field(
-                "tx_security_error_cnt",
-                &format_args!("{}", self.tx_security_error_cnt().bits()),
-            )
+            .field("tx_security_error_cnt", &self.tx_security_error_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_SECURITY_ERROR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/tx_status.rs b/esp32h2/src/ieee802154/tx_status.rs
index fda7601748..b8d8b68e30 100644
--- a/esp32h2/src/ieee802154/tx_status.rs
+++ b/esp32h2/src/ieee802154/tx_status.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_STATUS")
-            .field("tx_state", &format_args!("{}", self.tx_state().bits()))
-            .field(
-                "tx_abort_status",
-                &format_args!("{}", self.tx_abort_status().bits()),
-            )
-            .field(
-                "tx_sec_error_code",
-                &format_args!("{}", self.tx_sec_error_code().bits()),
-            )
+            .field("tx_state", &self.tx_state())
+            .field("tx_abort_status", &self.tx_abort_status())
+            .field("tx_sec_error_code", &self.tx_sec_error_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/txdma_addr.rs b/esp32h2/src/ieee802154/txdma_addr.rs
index 2b5c73f46d..486e3af98c 100644
--- a/esp32h2/src/ieee802154/txdma_addr.rs
+++ b/esp32h2/src/ieee802154/txdma_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXDMA_ADDR")
-            .field("txdma_addr", &format_args!("{}", self.txdma_addr().bits()))
+            .field("txdma_addr", &self.txdma_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXDMA_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/txdma_ctrl_state.rs b/esp32h2/src/ieee802154/txdma_ctrl_state.rs
index 0edaf10fe7..5b927f11e9 100644
--- a/esp32h2/src/ieee802154/txdma_ctrl_state.rs
+++ b/esp32h2/src/ieee802154/txdma_ctrl_state.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXDMA_CTRL_STATE")
-            .field(
-                "txdma_water_level",
-                &format_args!("{}", self.txdma_water_level().bits()),
-            )
-            .field(
-                "txdma_fill_entry",
-                &format_args!("{}", self.txdma_fill_entry().bits()),
-            )
-            .field(
-                "txdma_state",
-                &format_args!("{}", self.txdma_state().bits()),
-            )
-            .field(
-                "txdma_fetch_byte_cnt",
-                &format_args!("{}", self.txdma_fetch_byte_cnt().bits()),
-            )
+            .field("txdma_water_level", &self.txdma_water_level())
+            .field("txdma_fill_entry", &self.txdma_fill_entry())
+            .field("txdma_state", &self.txdma_state())
+            .field("txdma_fetch_byte_cnt", &self.txdma_fetch_byte_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXDMA_CTRL_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/txdma_err.rs b/esp32h2/src/ieee802154/txdma_err.rs
index c67edb2c9c..1a4ce416fb 100644
--- a/esp32h2/src/ieee802154/txdma_err.rs
+++ b/esp32h2/src/ieee802154/txdma_err.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXDMA_ERR")
-            .field("txdma_err", &format_args!("{}", self.txdma_err().bits()))
+            .field("txdma_err", &self.txdma_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXDMA_ERR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/txen_stop_delay.rs b/esp32h2/src/ieee802154/txen_stop_delay.rs
index df6e617df6..56290991f3 100644
--- a/esp32h2/src/ieee802154/txen_stop_delay.rs
+++ b/esp32h2/src/ieee802154/txen_stop_delay.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXEN_STOP_DELAY")
-            .field(
-                "txen_stop_dly",
-                &format_args!("{}", self.txen_stop_dly().bits()),
-            )
+            .field("txen_stop_dly", &self.txen_stop_dly())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXEN_STOP_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/txoff_delay.rs b/esp32h2/src/ieee802154/txoff_delay.rs
index bc396e4c4b..8dcc2a6ece 100644
--- a/esp32h2/src/ieee802154/txoff_delay.rs
+++ b/esp32h2/src/ieee802154/txoff_delay.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXOFF_DELAY")
-            .field(
-                "txoff_delay",
-                &format_args!("{}", self.txoff_delay().bits()),
-            )
+            .field("txoff_delay", &self.txoff_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXOFF_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/txon_delay.rs b/esp32h2/src/ieee802154/txon_delay.rs
index 9c8aac2b08..eb3d4ee152 100644
--- a/esp32h2/src/ieee802154/txon_delay.rs
+++ b/esp32h2/src/ieee802154/txon_delay.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXON_DELAY")
-            .field("txon_delay", &format_args!("{}", self.txon_delay().bits()))
+            .field("txon_delay", &self.txon_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXON_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/txrx_path_delay.rs b/esp32h2/src/ieee802154/txrx_path_delay.rs
index a4f0fc8ffb..e89d13b844 100644
--- a/esp32h2/src/ieee802154/txrx_path_delay.rs
+++ b/esp32h2/src/ieee802154/txrx_path_delay.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXRX_PATH_DELAY")
-            .field(
-                "tx_path_delay",
-                &format_args!("{}", self.tx_path_delay().bits()),
-            )
-            .field(
-                "rx_path_delay",
-                &format_args!("{}", self.rx_path_delay().bits()),
-            )
+            .field("tx_path_delay", &self.tx_path_delay())
+            .field("rx_path_delay", &self.rx_path_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXRX_PATH_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/txrx_status.rs b/esp32h2/src/ieee802154/txrx_status.rs
index aad8f52f7a..91584dd592 100644
--- a/esp32h2/src/ieee802154/txrx_status.rs
+++ b/esp32h2/src/ieee802154/txrx_status.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXRX_STATUS")
-            .field("txrx_state", &format_args!("{}", self.txrx_state().bits()))
-            .field("tx_proc", &format_args!("{}", self.tx_proc().bit()))
-            .field("rx_proc", &format_args!("{}", self.rx_proc().bit()))
-            .field("ed_proc", &format_args!("{}", self.ed_proc().bit()))
-            .field(
-                "ed_trigger_tx_proc",
-                &format_args!("{}", self.ed_trigger_tx_proc().bit()),
-            )
-            .field(
-                "rf_ctrl_state",
-                &format_args!("{}", self.rf_ctrl_state().bits()),
-            )
+            .field("txrx_state", &self.txrx_state())
+            .field("tx_proc", &self.tx_proc())
+            .field("rx_proc", &self.rx_proc())
+            .field("ed_proc", &self.ed_proc())
+            .field("ed_trigger_tx_proc", &self.ed_trigger_tx_proc())
+            .field("rf_ctrl_state", &self.rf_ctrl_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXRX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32h2/src/ieee802154/txrx_switch_delay.rs b/esp32h2/src/ieee802154/txrx_switch_delay.rs
index bb39a9a8c6..92ccc395e0 100644
--- a/esp32h2/src/ieee802154/txrx_switch_delay.rs
+++ b/esp32h2/src/ieee802154/txrx_switch_delay.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXRX_SWITCH_DELAY")
-            .field(
-                "txrx_switch_delay",
-                &format_args!("{}", self.txrx_switch_delay().bits()),
-            )
+            .field("txrx_switch_delay", &self.txrx_switch_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXRX_SWITCH_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/aes_intr_map.rs b/esp32h2/src/interrupt_core0/aes_intr_map.rs
index 19152e87aa..17a8c16668 100644
--- a/esp32h2/src/interrupt_core0/aes_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/aes_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AES_INTR_MAP")
-            .field(
-                "aes_intr_map",
-                &format_args!("{}", self.aes_intr_map().bits()),
-            )
+            .field("aes_intr_map", &self.aes_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AES_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_AES_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/apb_adc_intr_map.rs b/esp32h2/src/interrupt_core0/apb_adc_intr_map.rs
index f751474a25..bdfcfc84fa 100644
--- a/esp32h2/src/interrupt_core0/apb_adc_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/apb_adc_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_ADC_INTR_MAP")
-            .field(
-                "apb_adc_intr_map",
-                &format_args!("{}", self.apb_adc_intr_map().bits()),
-            )
+            .field("apb_adc_intr_map", &self.apb_adc_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_ADC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_APB_ADC_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/assist_debug_intr_map.rs b/esp32h2/src/interrupt_core0/assist_debug_intr_map.rs
index 65c613c04d..b054a634a6 100644
--- a/esp32h2/src/interrupt_core0/assist_debug_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/assist_debug_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ASSIST_DEBUG_INTR_MAP")
-            .field(
-                "assist_debug_intr_map",
-                &format_args!("{}", self.assist_debug_intr_map().bits()),
-            )
+            .field("assist_debug_intr_map", &self.assist_debug_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ASSIST_DEBUG_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_ASSIST_DEBUG_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/ble_sec_intr_map.rs b/esp32h2/src/interrupt_core0/ble_sec_intr_map.rs
index b1a59c6907..cfe6c92504 100644
--- a/esp32h2/src/interrupt_core0/ble_sec_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/ble_sec_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLE_SEC_INTR_MAP")
-            .field(
-                "ble_sec_intr_map",
-                &format_args!("{}", self.ble_sec_intr_map().bits()),
-            )
+            .field("ble_sec_intr_map", &self.ble_sec_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLE_SEC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_BLE_SEC_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/ble_timer_intr_map.rs b/esp32h2/src/interrupt_core0/ble_timer_intr_map.rs
index f5f8f950ca..da513b4ac9 100644
--- a/esp32h2/src/interrupt_core0/ble_timer_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/ble_timer_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLE_TIMER_INTR_MAP")
-            .field(
-                "ble_timer_intr_map",
-                &format_args!("{}", self.ble_timer_intr_map().bits()),
-            )
+            .field("ble_timer_intr_map", &self.ble_timer_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLE_TIMER_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_BLE_TIMER_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/bt_bb_intr_map.rs b/esp32h2/src/interrupt_core0/bt_bb_intr_map.rs
index 33c64de865..e6bc19e5bc 100644
--- a/esp32h2/src/interrupt_core0/bt_bb_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/bt_bb_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_BB_INTR_MAP")
-            .field(
-                "bt_bb_intr_map",
-                &format_args!("{}", self.bt_bb_intr_map().bits()),
-            )
+            .field("bt_bb_intr_map", &self.bt_bb_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_BB_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_BT_BB_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/bt_bb_nmi_map.rs b/esp32h2/src/interrupt_core0/bt_bb_nmi_map.rs
index 1499eae7bb..2c2df02e7b 100644
--- a/esp32h2/src/interrupt_core0/bt_bb_nmi_map.rs
+++ b/esp32h2/src/interrupt_core0/bt_bb_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_BB_NMI_MAP")
-            .field(
-                "bt_bb_nmi_map",
-                &format_args!("{}", self.bt_bb_nmi_map().bits()),
-            )
+            .field("bt_bb_nmi_map", &self.bt_bb_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_BB_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_BT_BB_NMI mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/bt_mac_intr_map.rs b/esp32h2/src/interrupt_core0/bt_mac_intr_map.rs
index 033badc524..2514c24b66 100644
--- a/esp32h2/src/interrupt_core0/bt_mac_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/bt_mac_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_MAC_INTR_MAP")
-            .field(
-                "bt_mac_intr_map",
-                &format_args!("{}", self.bt_mac_intr_map().bits()),
-            )
+            .field("bt_mac_intr_map", &self.bt_mac_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_MAC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_BT_MAC_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/cache_intr_map.rs b/esp32h2/src/interrupt_core0/cache_intr_map.rs
index 22d358a95d..40096ee41b 100644
--- a/esp32h2/src/interrupt_core0/cache_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/cache_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_INTR_MAP")
-            .field(
-                "cache_intr_map",
-                &format_args!("{}", self.cache_intr_map().bits()),
-            )
+            .field("cache_intr_map", &self.cache_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_CACHE_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/can0_intr_map.rs b/esp32h2/src/interrupt_core0/can0_intr_map.rs
index ef151c22b7..e6276fd78e 100644
--- a/esp32h2/src/interrupt_core0/can0_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/can0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAN0_INTR_MAP")
-            .field(
-                "can0_intr_map",
-                &format_args!("{}", self.can0_intr_map().bits()),
-            )
+            .field("can0_intr_map", &self.can0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAN0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_CAN0_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/clock_gate.rs b/esp32h2/src/interrupt_core0/clock_gate.rs
index dcac81f83e..4cc572f75d 100644
--- a/esp32h2/src/interrupt_core0/clock_gate.rs
+++ b/esp32h2/src/interrupt_core0/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("reg_clk_en", &format_args!("{}", self.reg_clk_en().bit()))
+            .field("reg_clk_en", &self.reg_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Clock register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/coex_intr_map.rs b/esp32h2/src/interrupt_core0/coex_intr_map.rs
index 29839f3782..20b0cc4fe2 100644
--- a/esp32h2/src/interrupt_core0/coex_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/coex_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COEX_INTR_MAP")
-            .field(
-                "coex_intr_map",
-                &format_args!("{}", self.coex_intr_map().bits()),
-            )
+            .field("coex_intr_map", &self.coex_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COEX_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_COEX_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs b/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
index 915d5c5829..7c1df82de1 100644
--- a/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
+++ b/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_0_MAP")
-            .field(
-                "cpu_intr_from_cpu_0_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_0_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_0_map", &self.cpu_intr_from_cpu_0_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_0_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_CPU_INTR_FROM_CPU_0 mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs b/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
index 556b7af682..39e30196a8 100644
--- a/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
+++ b/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_1_MAP")
-            .field(
-                "cpu_intr_from_cpu_1_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_1_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_1_map", &self.cpu_intr_from_cpu_1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_CPU_INTR_FROM_CPU_1 mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs b/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
index ee256cb7e8..8a54f1a1ea 100644
--- a/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
+++ b/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_2_MAP")
-            .field(
-                "cpu_intr_from_cpu_2_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_2_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_2_map", &self.cpu_intr_from_cpu_2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_CPU_INTR_FROM_CPU_2 mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs b/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
index 97db9dac34..9950916bc3 100644
--- a/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
+++ b/esp32h2/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_3_MAP")
-            .field(
-                "cpu_intr_from_cpu_3_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_3_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_3_map", &self.cpu_intr_from_cpu_3_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_CPU_INTR_FROM_CPU_3 mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/cpu_peri_timeout_intr_map.rs b/esp32h2/src/interrupt_core0/cpu_peri_timeout_intr_map.rs
index 333a578b47..b898068830 100644
--- a/esp32h2/src/interrupt_core0/cpu_peri_timeout_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/cpu_peri_timeout_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CPU_PERI_TIMEOUT_INTR_MAP")
             .field(
                 "cpu_peri_timeout_intr_map",
-                &format_args!("{}", self.cpu_peri_timeout_intr_map().bits()),
+                &self.cpu_peri_timeout_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_TIMEOUT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_CPU_PERI_TIMEOUT_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/dma_in_ch0_intr_map.rs b/esp32h2/src/interrupt_core0/dma_in_ch0_intr_map.rs
index 069ff138c9..907169146d 100644
--- a/esp32h2/src/interrupt_core0/dma_in_ch0_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/dma_in_ch0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH0_INTR_MAP")
-            .field(
-                "dma_in_ch0_intr_map",
-                &format_args!("{}", self.dma_in_ch0_intr_map().bits()),
-            )
+            .field("dma_in_ch0_intr_map", &self.dma_in_ch0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_DMA_IN_CH0_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/dma_in_ch1_intr_map.rs b/esp32h2/src/interrupt_core0/dma_in_ch1_intr_map.rs
index f9d1f9055e..e8a45ab0f3 100644
--- a/esp32h2/src/interrupt_core0/dma_in_ch1_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/dma_in_ch1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH1_INTR_MAP")
-            .field(
-                "dma_in_ch1_intr_map",
-                &format_args!("{}", self.dma_in_ch1_intr_map().bits()),
-            )
+            .field("dma_in_ch1_intr_map", &self.dma_in_ch1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_DMA_IN_CH1_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/dma_in_ch2_intr_map.rs b/esp32h2/src/interrupt_core0/dma_in_ch2_intr_map.rs
index 0dd5f11577..c2447fc2f8 100644
--- a/esp32h2/src/interrupt_core0/dma_in_ch2_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/dma_in_ch2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH2_INTR_MAP")
-            .field(
-                "dma_in_ch2_intr_map",
-                &format_args!("{}", self.dma_in_ch2_intr_map().bits()),
-            )
+            .field("dma_in_ch2_intr_map", &self.dma_in_ch2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_DMA_IN_CH2_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/dma_out_ch0_intr_map.rs b/esp32h2/src/interrupt_core0/dma_out_ch0_intr_map.rs
index 659536737d..04944f524d 100644
--- a/esp32h2/src/interrupt_core0/dma_out_ch0_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/dma_out_ch0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH0_INTR_MAP")
-            .field(
-                "dma_out_ch0_intr_map",
-                &format_args!("{}", self.dma_out_ch0_intr_map().bits()),
-            )
+            .field("dma_out_ch0_intr_map", &self.dma_out_ch0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_DMA_OUT_CH0_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/dma_out_ch1_intr_map.rs b/esp32h2/src/interrupt_core0/dma_out_ch1_intr_map.rs
index 5f4836a23c..c47ac81d68 100644
--- a/esp32h2/src/interrupt_core0/dma_out_ch1_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/dma_out_ch1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH1_INTR_MAP")
-            .field(
-                "dma_out_ch1_intr_map",
-                &format_args!("{}", self.dma_out_ch1_intr_map().bits()),
-            )
+            .field("dma_out_ch1_intr_map", &self.dma_out_ch1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_DMA_OUT_CH1_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/dma_out_ch2_intr_map.rs b/esp32h2/src/interrupt_core0/dma_out_ch2_intr_map.rs
index 2fb2400708..aa1b627082 100644
--- a/esp32h2/src/interrupt_core0/dma_out_ch2_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/dma_out_ch2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH2_INTR_MAP")
-            .field(
-                "dma_out_ch2_intr_map",
-                &format_args!("{}", self.dma_out_ch2_intr_map().bits()),
-            )
+            .field("dma_out_ch2_intr_map", &self.dma_out_ch2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_DMA_OUT_CH2_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/ecc_intr_map.rs b/esp32h2/src/interrupt_core0/ecc_intr_map.rs
index cef152d7a2..a4b3fe4360 100644
--- a/esp32h2/src/interrupt_core0/ecc_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/ecc_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_INTR_MAP")
-            .field(
-                "ecc_intr_map",
-                &format_args!("{}", self.ecc_intr_map().bits()),
-            )
+            .field("ecc_intr_map", &self.ecc_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_ECC_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/ecdsa_intr_map.rs b/esp32h2/src/interrupt_core0/ecdsa_intr_map.rs
index c3c6bb855e..29371cc01e 100644
--- a/esp32h2/src/interrupt_core0/ecdsa_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/ecdsa_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECDSA_INTR_MAP")
-            .field(
-                "ecdsa_intr_map",
-                &format_args!("{}", self.ecdsa_intr_map().bits()),
-            )
+            .field("ecdsa_intr_map", &self.ecdsa_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECDSA_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_ECDSA_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/efuse_intr_map.rs b/esp32h2/src/interrupt_core0/efuse_intr_map.rs
index 92e602eebe..195dad8b20 100644
--- a/esp32h2/src/interrupt_core0/efuse_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/efuse_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EFUSE_INTR_MAP")
-            .field(
-                "efuse_intr_map",
-                &format_args!("{}", self.efuse_intr_map().bits()),
-            )
+            .field("efuse_intr_map", &self.efuse_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EFUSE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_EFUSE_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/gpio_interrupt_pro_map.rs b/esp32h2/src/interrupt_core0/gpio_interrupt_pro_map.rs
index bb7277d0e1..5beb28c512 100644
--- a/esp32h2/src/interrupt_core0/gpio_interrupt_pro_map.rs
+++ b/esp32h2/src/interrupt_core0/gpio_interrupt_pro_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INTERRUPT_PRO_MAP")
-            .field(
-                "gpio_interrupt_pro_map",
-                &format_args!("{}", self.gpio_interrupt_pro_map().bits()),
-            )
+            .field("gpio_interrupt_pro_map", &self.gpio_interrupt_pro_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_PRO_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_GPIO_INTERRUPT_PRO mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs b/esp32h2/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
index aa9e28f73a..af76b77a80 100644
--- a/esp32h2/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
+++ b/esp32h2/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("GPIO_INTERRUPT_PRO_NMI_MAP")
             .field(
                 "gpio_interrupt_pro_nmi_map",
-                &format_args!("{}", self.gpio_interrupt_pro_nmi_map().bits()),
+                &self.gpio_interrupt_pro_nmi_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_PRO_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_GPIO_INTERRUPT_PRO_NMI mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/gpspi2_intr_map.rs b/esp32h2/src/interrupt_core0/gpspi2_intr_map.rs
index b2d73bf802..95f1b52b5e 100644
--- a/esp32h2/src/interrupt_core0/gpspi2_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/gpspi2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPSPI2_INTR_MAP")
-            .field(
-                "gpspi2_intr_map",
-                &format_args!("{}", self.gpspi2_intr_map().bits()),
-            )
+            .field("gpspi2_intr_map", &self.gpspi2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPSPI2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_GPSPI2_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/hp_apm_m0_intr_map.rs b/esp32h2/src/interrupt_core0/hp_apm_m0_intr_map.rs
index 42b5341c5f..35def8585f 100644
--- a/esp32h2/src/interrupt_core0/hp_apm_m0_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/hp_apm_m0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_APM_M0_INTR_MAP")
-            .field(
-                "hp_apm_m0_intr_map",
-                &format_args!("{}", self.hp_apm_m0_intr_map().bits()),
-            )
+            .field("hp_apm_m0_intr_map", &self.hp_apm_m0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_APM_M0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_HP_APM_M0_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/hp_apm_m1_intr_map.rs b/esp32h2/src/interrupt_core0/hp_apm_m1_intr_map.rs
index 5ab682c573..c8b1fafcb4 100644
--- a/esp32h2/src/interrupt_core0/hp_apm_m1_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/hp_apm_m1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_APM_M1_INTR_MAP")
-            .field(
-                "hp_apm_m1_intr_map",
-                &format_args!("{}", self.hp_apm_m1_intr_map().bits()),
-            )
+            .field("hp_apm_m1_intr_map", &self.hp_apm_m1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_APM_M1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_HP_APM_M1_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/hp_apm_m2_intr_map.rs b/esp32h2/src/interrupt_core0/hp_apm_m2_intr_map.rs
index 14b902d145..66062eb2fc 100644
--- a/esp32h2/src/interrupt_core0/hp_apm_m2_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/hp_apm_m2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_APM_M2_INTR_MAP")
-            .field(
-                "hp_apm_m2_intr_map",
-                &format_args!("{}", self.hp_apm_m2_intr_map().bits()),
-            )
+            .field("hp_apm_m2_intr_map", &self.hp_apm_m2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_APM_M2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_HP_APM_M2_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/hp_apm_m3_intr_map.rs b/esp32h2/src/interrupt_core0/hp_apm_m3_intr_map.rs
index 0fb87e8c18..c0f9c5d68d 100644
--- a/esp32h2/src/interrupt_core0/hp_apm_m3_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/hp_apm_m3_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_APM_M3_INTR_MAP")
-            .field(
-                "hp_apm_m3_intr_map",
-                &format_args!("{}", self.hp_apm_m3_intr_map().bits()),
-            )
+            .field("hp_apm_m3_intr_map", &self.hp_apm_m3_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_APM_M3_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_HP_APM_M3_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/hp_peri_timeout_intr_map.rs b/esp32h2/src/interrupt_core0/hp_peri_timeout_intr_map.rs
index 935996f4f3..46a1c19700 100644
--- a/esp32h2/src/interrupt_core0/hp_peri_timeout_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/hp_peri_timeout_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_PERI_TIMEOUT_INTR_MAP")
-            .field(
-                "hp_peri_timeout_intr_map",
-                &format_args!("{}", self.hp_peri_timeout_intr_map().bits()),
-            )
+            .field("hp_peri_timeout_intr_map", &self.hp_peri_timeout_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_PERI_TIMEOUT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_HP_PERI_TIMEOUT_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/i2c_ext0_intr_map.rs b/esp32h2/src/interrupt_core0/i2c_ext0_intr_map.rs
index 6b0d6111c6..d38a68e7a5 100644
--- a/esp32h2/src/interrupt_core0/i2c_ext0_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/i2c_ext0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_EXT0_INTR_MAP")
-            .field(
-                "i2c_ext0_intr_map",
-                &format_args!("{}", self.i2c_ext0_intr_map().bits()),
-            )
+            .field("i2c_ext0_intr_map", &self.i2c_ext0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_EXT0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_I2C_EXT0_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/i2c_ext1_intr_map.rs b/esp32h2/src/interrupt_core0/i2c_ext1_intr_map.rs
index 566a8e20f5..fc3ea889d5 100644
--- a/esp32h2/src/interrupt_core0/i2c_ext1_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/i2c_ext1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_EXT1_INTR_MAP")
-            .field(
-                "i2c_ext1_intr_map",
-                &format_args!("{}", self.i2c_ext1_intr_map().bits()),
-            )
+            .field("i2c_ext1_intr_map", &self.i2c_ext1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_EXT1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_I2C_EXT1_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/i2s1_intr_map.rs b/esp32h2/src/interrupt_core0/i2s1_intr_map.rs
index cd24eac7dc..a3449df115 100644
--- a/esp32h2/src/interrupt_core0/i2s1_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/i2s1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S1_INTR_MAP")
-            .field(
-                "i2s1_intr_map",
-                &format_args!("{}", self.i2s1_intr_map().bits()),
-            )
+            .field("i2s1_intr_map", &self.i2s1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_I2S1_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/int_status_reg_2.rs b/esp32h2/src/interrupt_core0/int_status_reg_2.rs
index 17c523e930..ec05f4306e 100644
--- a/esp32h2/src/interrupt_core0/int_status_reg_2.rs
+++ b/esp32h2/src/interrupt_core0/int_status_reg_2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_STATUS_REG_2")
-            .field(
-                "int_status_2",
-                &format_args!("{}", self.int_status_2().bits()),
-            )
+            .field("int_status_2", &self.int_status_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_STATUS_REG_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_status_reg_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_STATUS_REG_2_SPEC;
 impl crate::RegisterSpec for INT_STATUS_REG_2_SPEC {
diff --git a/esp32h2/src/interrupt_core0/interrupt_reg_date.rs b/esp32h2/src/interrupt_core0/interrupt_reg_date.rs
index 55bad7be8f..dbdaeafef9 100644
--- a/esp32h2/src/interrupt_core0/interrupt_reg_date.rs
+++ b/esp32h2/src/interrupt_core0/interrupt_reg_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT_REG_DATE")
-            .field(
-                "interrupt_reg_date",
-                &format_args!("{}", self.interrupt_reg_date().bits()),
-            )
+            .field("interrupt_reg_date", &self.interrupt_reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/intr_status_reg_0.rs b/esp32h2/src/interrupt_core0/intr_status_reg_0.rs
index 0b29c83ba7..507d98b69d 100644
--- a/esp32h2/src/interrupt_core0/intr_status_reg_0.rs
+++ b/esp32h2/src/interrupt_core0/intr_status_reg_0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_0")
-            .field(
-                "intr_status_0",
-                &format_args!("{}", self.intr_status_0().bits()),
-            )
+            .field("intr_status_0", &self.intr_status_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_0_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_0_SPEC {
diff --git a/esp32h2/src/interrupt_core0/intr_status_reg_1.rs b/esp32h2/src/interrupt_core0/intr_status_reg_1.rs
index 2e1feca83d..cf8623d61f 100644
--- a/esp32h2/src/interrupt_core0/intr_status_reg_1.rs
+++ b/esp32h2/src/interrupt_core0/intr_status_reg_1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_1")
-            .field(
-                "intr_status_1",
-                &format_args!("{}", self.intr_status_1().bits()),
-            )
+            .field("intr_status_1", &self.intr_status_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_1_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_1_SPEC {
diff --git a/esp32h2/src/interrupt_core0/ledc_intr_map.rs b/esp32h2/src/interrupt_core0/ledc_intr_map.rs
index 3cfcc89af8..a7e5664220 100644
--- a/esp32h2/src/interrupt_core0/ledc_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/ledc_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEDC_INTR_MAP")
-            .field(
-                "ledc_intr_map",
-                &format_args!("{}", self.ledc_intr_map().bits()),
-            )
+            .field("ledc_intr_map", &self.ledc_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEDC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_LEDC_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/lp_apm_m0_intr_map.rs b/esp32h2/src/interrupt_core0/lp_apm_m0_intr_map.rs
index 2f68a35c74..dd917d213b 100644
--- a/esp32h2/src/interrupt_core0/lp_apm_m0_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/lp_apm_m0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_APM_M0_INTR_MAP")
-            .field(
-                "lp_apm_m0_intr_map",
-                &format_args!("{}", self.lp_apm_m0_intr_map().bits()),
-            )
+            .field("lp_apm_m0_intr_map", &self.lp_apm_m0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_APM_M0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_LP_APM_M0_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/lp_ble_timer_intr_map.rs b/esp32h2/src/interrupt_core0/lp_ble_timer_intr_map.rs
index d9401eed32..8d591d845f 100644
--- a/esp32h2/src/interrupt_core0/lp_ble_timer_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/lp_ble_timer_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_BLE_TIMER_INTR_MAP")
-            .field(
-                "lp_ble_timer_intr_map",
-                &format_args!("{}", self.lp_ble_timer_intr_map().bits()),
-            )
+            .field("lp_ble_timer_intr_map", &self.lp_ble_timer_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_BLE_TIMER_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_LP_BLE_TIMER_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/lp_peri_timeout_intr_map.rs b/esp32h2/src/interrupt_core0/lp_peri_timeout_intr_map.rs
index e408801285..92c5a3951e 100644
--- a/esp32h2/src/interrupt_core0/lp_peri_timeout_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/lp_peri_timeout_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_PERI_TIMEOUT_INTR_MAP")
-            .field(
-                "lp_peri_timeout_intr_map",
-                &format_args!("{}", self.lp_peri_timeout_intr_map().bits()),
-            )
+            .field("lp_peri_timeout_intr_map", &self.lp_peri_timeout_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_PERI_TIMEOUT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_LP_PERI_TIMEOUT_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/lp_rtc_timer_intr_map.rs b/esp32h2/src/interrupt_core0/lp_rtc_timer_intr_map.rs
index 3ac584ff66..8fec7c9b4e 100644
--- a/esp32h2/src/interrupt_core0/lp_rtc_timer_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/lp_rtc_timer_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_RTC_TIMER_INTR_MAP")
-            .field(
-                "lp_rtc_timer_intr_map",
-                &format_args!("{}", self.lp_rtc_timer_intr_map().bits()),
-            )
+            .field("lp_rtc_timer_intr_map", &self.lp_rtc_timer_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_RTC_TIMER_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_LP_RTC_TIMER_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/lp_wdt_intr_map.rs b/esp32h2/src/interrupt_core0/lp_wdt_intr_map.rs
index 60b821e00f..345175d980 100644
--- a/esp32h2/src/interrupt_core0/lp_wdt_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/lp_wdt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_WDT_INTR_MAP")
-            .field(
-                "lp_wdt_intr_map",
-                &format_args!("{}", self.lp_wdt_intr_map().bits()),
-            )
+            .field("lp_wdt_intr_map", &self.lp_wdt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_WDT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_LP_WDT_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/mspi_intr_map.rs b/esp32h2/src/interrupt_core0/mspi_intr_map.rs
index 0c556f5e5d..80d3a16cf3 100644
--- a/esp32h2/src/interrupt_core0/mspi_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/mspi_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MSPI_INTR_MAP")
-            .field(
-                "mspi_intr_map",
-                &format_args!("{}", self.mspi_intr_map().bits()),
-            )
+            .field("mspi_intr_map", &self.mspi_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MSPI_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_MSPI_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/parl_io_rx_intr_map.rs b/esp32h2/src/interrupt_core0/parl_io_rx_intr_map.rs
index f1a765a4f1..ba65ee22c2 100644
--- a/esp32h2/src/interrupt_core0/parl_io_rx_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/parl_io_rx_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PARL_IO_RX_INTR_MAP")
-            .field(
-                "parl_io_rx_intr_map",
-                &format_args!("{}", self.parl_io_rx_intr_map().bits()),
-            )
+            .field("parl_io_rx_intr_map", &self.parl_io_rx_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PARL_IO_RX_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_PARL_IO_RX_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/parl_io_tx_intr_map.rs b/esp32h2/src/interrupt_core0/parl_io_tx_intr_map.rs
index 06b002bcae..1707523975 100644
--- a/esp32h2/src/interrupt_core0/parl_io_tx_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/parl_io_tx_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PARL_IO_TX_INTR_MAP")
-            .field(
-                "parl_io_tx_intr_map",
-                &format_args!("{}", self.parl_io_tx_intr_map().bits()),
-            )
+            .field("parl_io_tx_intr_map", &self.parl_io_tx_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PARL_IO_TX_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_PARL_IO_TX_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/pau_intr_map.rs b/esp32h2/src/interrupt_core0/pau_intr_map.rs
index 59b19db195..65ff9fa172 100644
--- a/esp32h2/src/interrupt_core0/pau_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/pau_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAU_INTR_MAP")
-            .field(
-                "pau_intr_map",
-                &format_args!("{}", self.pau_intr_map().bits()),
-            )
+            .field("pau_intr_map", &self.pau_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAU_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_PAU_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/pcnt_intr_map.rs b/esp32h2/src/interrupt_core0/pcnt_intr_map.rs
index 00d412b805..9eef7952de 100644
--- a/esp32h2/src/interrupt_core0/pcnt_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/pcnt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCNT_INTR_MAP")
-            .field(
-                "pcnt_intr_map",
-                &format_args!("{}", self.pcnt_intr_map().bits()),
-            )
+            .field("pcnt_intr_map", &self.pcnt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCNT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_PCNT_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/pmu_intr_map.rs b/esp32h2/src/interrupt_core0/pmu_intr_map.rs
index 19e3bb5d73..d52678de52 100644
--- a/esp32h2/src/interrupt_core0/pmu_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/pmu_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMU_INTR_MAP")
-            .field(
-                "pmu_intr_map",
-                &format_args!("{}", self.pmu_intr_map().bits()),
-            )
+            .field("pmu_intr_map", &self.pmu_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMU_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_PMU_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/pwm_intr_map.rs b/esp32h2/src/interrupt_core0/pwm_intr_map.rs
index f65fb10ddc..cdbf3a892c 100644
--- a/esp32h2/src/interrupt_core0/pwm_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/pwm_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM_INTR_MAP")
-            .field(
-                "pwm_intr_map",
-                &format_args!("{}", self.pwm_intr_map().bits()),
-            )
+            .field("pwm_intr_map", &self.pwm_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_PWM_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/rmt_intr_map.rs b/esp32h2/src/interrupt_core0/rmt_intr_map.rs
index 176430240f..ac19b9fd33 100644
--- a/esp32h2/src/interrupt_core0/rmt_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/rmt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RMT_INTR_MAP")
-            .field(
-                "rmt_intr_map",
-                &format_args!("{}", self.rmt_intr_map().bits()),
-            )
+            .field("rmt_intr_map", &self.rmt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RMT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_RMT_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/rsa_intr_map.rs b/esp32h2/src/interrupt_core0/rsa_intr_map.rs
index b42ffdf0d3..d96047f05c 100644
--- a/esp32h2/src/interrupt_core0/rsa_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/rsa_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_INTR_MAP")
-            .field(
-                "rsa_intr_map",
-                &format_args!("{}", self.rsa_intr_map().bits()),
-            )
+            .field("rsa_intr_map", &self.rsa_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_RSA_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/sha_intr_map.rs b/esp32h2/src/interrupt_core0/sha_intr_map.rs
index f89f176096..295270da3b 100644
--- a/esp32h2/src/interrupt_core0/sha_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/sha_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA_INTR_MAP")
-            .field(
-                "sha_intr_map",
-                &format_args!("{}", self.sha_intr_map().bits()),
-            )
+            .field("sha_intr_map", &self.sha_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_SHA_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/systimer_target0_intr_map.rs b/esp32h2/src/interrupt_core0/systimer_target0_intr_map.rs
index 3b7a47b063..c224afa731 100644
--- a/esp32h2/src/interrupt_core0/systimer_target0_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/systimer_target0_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYSTIMER_TARGET0_INTR_MAP")
             .field(
                 "systimer_target0_intr_map",
-                &format_args!("{}", self.systimer_target0_intr_map().bits()),
+                &self.systimer_target0_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_SYSTIMER_TARGET0_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/systimer_target1_intr_map.rs b/esp32h2/src/interrupt_core0/systimer_target1_intr_map.rs
index d184d7dcb7..85b4394024 100644
--- a/esp32h2/src/interrupt_core0/systimer_target1_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/systimer_target1_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYSTIMER_TARGET1_INTR_MAP")
             .field(
                 "systimer_target1_intr_map",
-                &format_args!("{}", self.systimer_target1_intr_map().bits()),
+                &self.systimer_target1_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_SYSTIMER_TARGET1_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/systimer_target2_intr_map.rs b/esp32h2/src/interrupt_core0/systimer_target2_intr_map.rs
index 885370aa0a..5103708664 100644
--- a/esp32h2/src/interrupt_core0/systimer_target2_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/systimer_target2_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYSTIMER_TARGET2_INTR_MAP")
             .field(
                 "systimer_target2_intr_map",
-                &format_args!("{}", self.systimer_target2_intr_map().bits()),
+                &self.systimer_target2_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_SYSTIMER_TARGET2_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/tg0_t0_intr_map.rs b/esp32h2/src/interrupt_core0/tg0_t0_intr_map.rs
index 55c06e4a6b..2114b502e9 100644
--- a/esp32h2/src/interrupt_core0/tg0_t0_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/tg0_t0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG0_T0_INTR_MAP")
-            .field(
-                "tg0_t0_intr_map",
-                &format_args!("{}", self.tg0_t0_intr_map().bits()),
-            )
+            .field("tg0_t0_intr_map", &self.tg0_t0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG0_T0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_TG0_T0_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/tg0_wdt_intr_map.rs b/esp32h2/src/interrupt_core0/tg0_wdt_intr_map.rs
index da95fba6b1..8a138675e0 100644
--- a/esp32h2/src/interrupt_core0/tg0_wdt_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/tg0_wdt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG0_WDT_INTR_MAP")
-            .field(
-                "tg0_wdt_intr_map",
-                &format_args!("{}", self.tg0_wdt_intr_map().bits()),
-            )
+            .field("tg0_wdt_intr_map", &self.tg0_wdt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG0_WDT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_TG0_WDT_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/tg1_t0_intr_map.rs b/esp32h2/src/interrupt_core0/tg1_t0_intr_map.rs
index a660337b67..042d404f36 100644
--- a/esp32h2/src/interrupt_core0/tg1_t0_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/tg1_t0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG1_T0_INTR_MAP")
-            .field(
-                "tg1_t0_intr_map",
-                &format_args!("{}", self.tg1_t0_intr_map().bits()),
-            )
+            .field("tg1_t0_intr_map", &self.tg1_t0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG1_T0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_TG1_T0_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/tg1_wdt_intr_map.rs b/esp32h2/src/interrupt_core0/tg1_wdt_intr_map.rs
index 3792f4b9f8..a6c7112fdd 100644
--- a/esp32h2/src/interrupt_core0/tg1_wdt_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/tg1_wdt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG1_WDT_INTR_MAP")
-            .field(
-                "tg1_wdt_intr_map",
-                &format_args!("{}", self.tg1_wdt_intr_map().bits()),
-            )
+            .field("tg1_wdt_intr_map", &self.tg1_wdt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG1_WDT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_TG1_WDT_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/trace_intr_map.rs b/esp32h2/src/interrupt_core0/trace_intr_map.rs
index 29836ec6f3..c4e2e483ee 100644
--- a/esp32h2/src/interrupt_core0/trace_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/trace_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TRACE_INTR_MAP")
-            .field(
-                "trace_intr_map",
-                &format_args!("{}", self.trace_intr_map().bits()),
-            )
+            .field("trace_intr_map", &self.trace_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TRACE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_TRACE_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/uart0_intr_map.rs b/esp32h2/src/interrupt_core0/uart0_intr_map.rs
index b2a42fcd16..ea7bc0310f 100644
--- a/esp32h2/src/interrupt_core0/uart0_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/uart0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART0_INTR_MAP")
-            .field(
-                "uart0_intr_map",
-                &format_args!("{}", self.uart0_intr_map().bits()),
-            )
+            .field("uart0_intr_map", &self.uart0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_UART0_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/uart1_intr_map.rs b/esp32h2/src/interrupt_core0/uart1_intr_map.rs
index 493326c5ab..44acc12314 100644
--- a/esp32h2/src/interrupt_core0/uart1_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/uart1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART1_INTR_MAP")
-            .field(
-                "uart1_intr_map",
-                &format_args!("{}", self.uart1_intr_map().bits()),
-            )
+            .field("uart1_intr_map", &self.uart1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_UART1_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/uhci0_intr_map.rs b/esp32h2/src/interrupt_core0/uhci0_intr_map.rs
index 8f06f6e71d..987d106d67 100644
--- a/esp32h2/src/interrupt_core0/uhci0_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/uhci0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UHCI0_INTR_MAP")
-            .field(
-                "uhci0_intr_map",
-                &format_args!("{}", self.uhci0_intr_map().bits()),
-            )
+            .field("uhci0_intr_map", &self.uhci0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UHCI0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_UHCI0_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/usb_intr_map.rs b/esp32h2/src/interrupt_core0/usb_intr_map.rs
index f1aa2acf56..94e6221b61 100644
--- a/esp32h2/src/interrupt_core0/usb_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/usb_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_INTR_MAP")
-            .field(
-                "usb_intr_map",
-                &format_args!("{}", self.usb_intr_map().bits()),
-            )
+            .field("usb_intr_map", &self.usb_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_USB_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/interrupt_core0/zb_mac_intr_map.rs b/esp32h2/src/interrupt_core0/zb_mac_intr_map.rs
index 20c88742e2..e71ee8f388 100644
--- a/esp32h2/src/interrupt_core0/zb_mac_intr_map.rs
+++ b/esp32h2/src/interrupt_core0/zb_mac_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ZB_MAC_INTR_MAP")
-            .field(
-                "zb_mac_intr_map",
-                &format_args!("{}", self.zb_mac_intr_map().bits()),
-            )
+            .field("zb_mac_intr_map", &self.zb_mac_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ZB_MAC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - CORE0_ZB_MAC_INTR mapping register"]
     #[inline(always)]
diff --git a/esp32h2/src/intpri/clock_gate.rs b/esp32h2/src/intpri/clock_gate.rs
index 8f6f21be25..b4f346377e 100644
--- a/esp32h2/src/intpri/clock_gate.rs
+++ b/esp32h2/src/intpri/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32h2/src/intpri/cpu_int_clear.rs b/esp32h2/src/intpri/cpu_int_clear.rs
index b9912b3374..cbc49231c0 100644
--- a/esp32h2/src/intpri/cpu_int_clear.rs
+++ b/esp32h2/src/intpri/cpu_int_clear.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_CLEAR")
-            .field(
-                "cpu_int_clear",
-                &format_args!("{}", self.cpu_int_clear().bits()),
-            )
+            .field("cpu_int_clear", &self.cpu_int_clear())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_CLEAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add description"]
     #[inline(always)]
diff --git a/esp32h2/src/intpri/cpu_int_eip_status.rs b/esp32h2/src/intpri/cpu_int_eip_status.rs
index b7ee1aaed5..1f188e92e8 100644
--- a/esp32h2/src/intpri/cpu_int_eip_status.rs
+++ b/esp32h2/src/intpri/cpu_int_eip_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_EIP_STATUS")
-            .field(
-                "cpu_int_eip_status",
-                &format_args!("{}", self.cpu_int_eip_status().bits()),
-            )
+            .field("cpu_int_eip_status", &self.cpu_int_eip_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_EIP_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_int_eip_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPU_INT_EIP_STATUS_SPEC;
 impl crate::RegisterSpec for CPU_INT_EIP_STATUS_SPEC {
diff --git a/esp32h2/src/intpri/cpu_int_enable.rs b/esp32h2/src/intpri/cpu_int_enable.rs
index f25a329e68..64ed8c3e2c 100644
--- a/esp32h2/src/intpri/cpu_int_enable.rs
+++ b/esp32h2/src/intpri/cpu_int_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_ENABLE")
-            .field(
-                "cpu_int_enable",
-                &format_args!("{}", self.cpu_int_enable().bits()),
-            )
+            .field("cpu_int_enable", &self.cpu_int_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add description"]
     #[inline(always)]
diff --git a/esp32h2/src/intpri/cpu_int_pri.rs b/esp32h2/src/intpri/cpu_int_pri.rs
index 1554f14e1a..cb451abfa9 100644
--- a/esp32h2/src/intpri/cpu_int_pri.rs
+++ b/esp32h2/src/intpri/cpu_int_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_PRI")
-            .field("map", &format_args!("{}", self.map().bits()))
+            .field("map", &self.map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Need add description"]
     #[inline(always)]
diff --git a/esp32h2/src/intpri/cpu_int_thresh.rs b/esp32h2/src/intpri/cpu_int_thresh.rs
index 9c6bba61ca..8cf1416d50 100644
--- a/esp32h2/src/intpri/cpu_int_thresh.rs
+++ b/esp32h2/src/intpri/cpu_int_thresh.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_THRESH")
-            .field(
-                "cpu_int_thresh",
-                &format_args!("{}", self.cpu_int_thresh().bits()),
-            )
+            .field("cpu_int_thresh", &self.cpu_int_thresh())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_THRESH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Need add description"]
     #[inline(always)]
diff --git a/esp32h2/src/intpri/cpu_int_type.rs b/esp32h2/src/intpri/cpu_int_type.rs
index 7582423a54..89be1b6343 100644
--- a/esp32h2/src/intpri/cpu_int_type.rs
+++ b/esp32h2/src/intpri/cpu_int_type.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INT_TYPE")
-            .field(
-                "cpu_int_type",
-                &format_args!("{}", self.cpu_int_type().bits()),
-            )
+            .field("cpu_int_type", &self.cpu_int_type())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_TYPE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Need add description"]
     #[inline(always)]
diff --git a/esp32h2/src/intpri/cpu_intr_from_cpu_0.rs b/esp32h2/src/intpri/cpu_intr_from_cpu_0.rs
index 36e224d1dd..773faf6f48 100644
--- a/esp32h2/src/intpri/cpu_intr_from_cpu_0.rs
+++ b/esp32h2/src/intpri/cpu_intr_from_cpu_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_0")
-            .field(
-                "cpu_intr_from_cpu_0",
-                &format_args!("{}", self.cpu_intr_from_cpu_0().bit()),
-            )
+            .field("cpu_intr_from_cpu_0", &self.cpu_intr_from_cpu_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32h2/src/intpri/cpu_intr_from_cpu_1.rs b/esp32h2/src/intpri/cpu_intr_from_cpu_1.rs
index 673f836671..be1befc8e4 100644
--- a/esp32h2/src/intpri/cpu_intr_from_cpu_1.rs
+++ b/esp32h2/src/intpri/cpu_intr_from_cpu_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_1")
-            .field(
-                "cpu_intr_from_cpu_1",
-                &format_args!("{}", self.cpu_intr_from_cpu_1().bit()),
-            )
+            .field("cpu_intr_from_cpu_1", &self.cpu_intr_from_cpu_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32h2/src/intpri/cpu_intr_from_cpu_2.rs b/esp32h2/src/intpri/cpu_intr_from_cpu_2.rs
index 59fc42668c..da0b42a361 100644
--- a/esp32h2/src/intpri/cpu_intr_from_cpu_2.rs
+++ b/esp32h2/src/intpri/cpu_intr_from_cpu_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_2")
-            .field(
-                "cpu_intr_from_cpu_2",
-                &format_args!("{}", self.cpu_intr_from_cpu_2().bit()),
-            )
+            .field("cpu_intr_from_cpu_2", &self.cpu_intr_from_cpu_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32h2/src/intpri/cpu_intr_from_cpu_3.rs b/esp32h2/src/intpri/cpu_intr_from_cpu_3.rs
index 966685ec1f..842300cffb 100644
--- a/esp32h2/src/intpri/cpu_intr_from_cpu_3.rs
+++ b/esp32h2/src/intpri/cpu_intr_from_cpu_3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_3")
-            .field(
-                "cpu_intr_from_cpu_3",
-                &format_args!("{}", self.cpu_intr_from_cpu_3().bit()),
-            )
+            .field("cpu_intr_from_cpu_3", &self.cpu_intr_from_cpu_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Need add description"]
     #[inline(always)]
diff --git a/esp32h2/src/intpri/date.rs b/esp32h2/src/intpri/date.rs
index 4e7cad74b8..8693e9ea9f 100644
--- a/esp32h2/src/intpri/date.rs
+++ b/esp32h2/src/intpri/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/intpri/rnd_eco.rs b/esp32h2/src/intpri/rnd_eco.rs
index cf663fec03..3163d9f0b8 100644
--- a/esp32h2/src/intpri/rnd_eco.rs
+++ b/esp32h2/src/intpri/rnd_eco.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO")
-            .field("redcy_ena", &format_args!("{}", self.redcy_ena().bit()))
-            .field(
-                "redcy_result",
-                &format_args!("{}", self.redcy_result().bit()),
-            )
+            .field("redcy_ena", &self.redcy_ena())
+            .field("redcy_result", &self.redcy_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Only reserved for ECO."]
     #[inline(always)]
diff --git a/esp32h2/src/intpri/rnd_eco_high.rs b/esp32h2/src/intpri/rnd_eco_high.rs
index d2138667f2..acb852af6d 100644
--- a/esp32h2/src/intpri/rnd_eco_high.rs
+++ b/esp32h2/src/intpri/rnd_eco_high.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_HIGH")
-            .field("redcy_high", &format_args!("{}", self.redcy_high().bits()))
+            .field("redcy_high", &self.redcy_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Only reserved for ECO."]
     #[inline(always)]
diff --git a/esp32h2/src/intpri/rnd_eco_low.rs b/esp32h2/src/intpri/rnd_eco_low.rs
index 6accf663f9..f3dcb2ff4b 100644
--- a/esp32h2/src/intpri/rnd_eco_low.rs
+++ b/esp32h2/src/intpri/rnd_eco_low.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_LOW")
-            .field("redcy_low", &format_args!("{}", self.redcy_low().bits()))
+            .field("redcy_low", &self.redcy_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Only reserved for ECO."]
     #[inline(always)]
diff --git a/esp32h2/src/io_mux/date.rs b/esp32h2/src/io_mux/date.rs
index 2a2044956c..b242b0e554 100644
--- a/esp32h2/src/io_mux/date.rs
+++ b/esp32h2/src/io_mux/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("reg_date", &format_args!("{}", self.reg_date().bits()))
+            .field("reg_date", &self.reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
diff --git a/esp32h2/src/io_mux/gpio.rs b/esp32h2/src/io_mux/gpio.rs
index e444a17567..3e245bce40 100644
--- a/esp32h2/src/io_mux/gpio.rs
+++ b/esp32h2/src/io_mux/gpio.rs
@@ -134,29 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
-            .field("hys_en", &format_args!("{}", self.hys_en().bit()))
-            .field("hys_sel", &format_args!("{}", self.hys_sel().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
+            .field("hys_en", &self.hys_en())
+            .field("hys_sel", &self.hys_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled."]
     #[inline(always)]
diff --git a/esp32h2/src/io_mux/modem_diag_en.rs b/esp32h2/src/io_mux/modem_diag_en.rs
index 0b9e880bc8..55347e4b1b 100644
--- a/esp32h2/src/io_mux/modem_diag_en.rs
+++ b/esp32h2/src/io_mux/modem_diag_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODEM_DIAG_EN")
-            .field(
-                "modem_diag_en",
-                &format_args!("{}", self.modem_diag_en().bits()),
-            )
+            .field("modem_diag_en", &self.modem_diag_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODEM_DIAG_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - bit i to enable modem_diag\\[i\\] into gpio matrix. 1:enable modem_diag\\[i\\] into gpio matrix. 0:enable other signals into gpio matrix"]
     #[inline(always)]
diff --git a/esp32h2/src/io_mux/pin_ctrl.rs b/esp32h2/src/io_mux/pin_ctrl.rs
index 0d00e79f0f..d53c6ba7f6 100644
--- a/esp32h2/src/io_mux/pin_ctrl.rs
+++ b/esp32h2/src/io_mux/pin_ctrl.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN_CTRL")
-            .field("clk_out1", &format_args!("{}", self.clk_out1().bits()))
-            .field("clk_out2", &format_args!("{}", self.clk_out2().bits()))
-            .field("clk_out3", &format_args!("{}", self.clk_out3().bits()))
+            .field("clk_out1", &self.clk_out1())
+            .field("clk_out2", &self.clk_out2())
+            .field("clk_out3", &self.clk_out3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals."]
     #[inline(always)]
diff --git a/esp32h2/src/ledc/ch/conf0.rs b/esp32h2/src/ledc/ch/conf0.rs
index 75e709aeae..3e3620eb0f 100644
--- a/esp32h2/src/ledc/ch/conf0.rs
+++ b/esp32h2/src/ledc/ch/conf0.rs
@@ -57,20 +57,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("timer_sel", &format_args!("{}", self.timer_sel().bits()))
-            .field("sig_out_en", &format_args!("{}", self.sig_out_en().bit()))
-            .field("idle_lv", &format_args!("{}", self.idle_lv().bit()))
-            .field("ovf_num", &format_args!("{}", self.ovf_num().bits()))
-            .field("ovf_cnt_en", &format_args!("{}", self.ovf_cnt_en().bit()))
+            .field("timer_sel", &self.timer_sel())
+            .field("sig_out_en", &self.sig_out_en())
+            .field("idle_lv", &self.idle_lv())
+            .field("ovf_num", &self.ovf_num())
+            .field("ovf_cnt_en", &self.ovf_cnt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to select one of timers for channel %s. 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3"]
     #[inline(always)]
diff --git a/esp32h2/src/ledc/ch/conf1.rs b/esp32h2/src/ledc/ch/conf1.rs
index 7d7c11116b..51ebd704af 100644
--- a/esp32h2/src/ledc/ch/conf1.rs
+++ b/esp32h2/src/ledc/ch/conf1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field("duty_start", &format_args!("{}", self.duty_start().bit()))
+            .field("duty_start", &self.duty_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1."]
     #[inline(always)]
diff --git a/esp32h2/src/ledc/ch/duty.rs b/esp32h2/src/ledc/ch/duty.rs
index 4c7bf4a186..7494af0c54 100644
--- a/esp32h2/src/ledc/ch/duty.rs
+++ b/esp32h2/src/ledc/ch/duty.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DUTY")
-            .field("duty", &format_args!("{}", self.duty().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DUTY").field("duty", &self.duty()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/ledc/ch/duty_r.rs b/esp32h2/src/ledc/ch/duty_r.rs
index f14b8a4d90..a3b6ad8523 100644
--- a/esp32h2/src/ledc/ch/duty_r.rs
+++ b/esp32h2/src/ledc/ch/duty_r.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DUTY_R")
-            .field("duty_r", &format_args!("{}", self.duty_r().bits()))
+            .field("duty_r", &self.duty_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_R_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current duty cycle for channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`duty_r::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DUTY_R_SPEC;
 impl crate::RegisterSpec for DUTY_R_SPEC {
diff --git a/esp32h2/src/ledc/ch/hpoint.rs b/esp32h2/src/ledc/ch/hpoint.rs
index 5167d38a55..f98ee1970f 100644
--- a/esp32h2/src/ledc/ch/hpoint.rs
+++ b/esp32h2/src/ledc/ch/hpoint.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPOINT")
-            .field("hpoint", &format_args!("{}", self.hpoint().bits()))
+            .field("hpoint", &self.hpoint())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPOINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - The output value changes to high when the selected timers has reached the value specified by this register."]
     #[inline(always)]
diff --git a/esp32h2/src/ledc/ch_gamma_conf.rs b/esp32h2/src/ledc/ch_gamma_conf.rs
index 6af9564680..28251b1fe6 100644
--- a/esp32h2/src/ledc/ch_gamma_conf.rs
+++ b/esp32h2/src/ledc/ch_gamma_conf.rs
@@ -21,19 +21,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_GAMMA_CONF")
-            .field(
-                "ch_gamma_entry_num",
-                &format_args!("{}", self.ch_gamma_entry_num().bits()),
-            )
+            .field("ch_gamma_entry_num", &self.ch_gamma_entry_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_GAMMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Ledc ch%s gamma entry num."]
     #[inline(always)]
diff --git a/esp32h2/src/ledc/ch_gamma_rd_addr.rs b/esp32h2/src/ledc/ch_gamma_rd_addr.rs
index 22800ad736..62a261fc9e 100644
--- a/esp32h2/src/ledc/ch_gamma_rd_addr.rs
+++ b/esp32h2/src/ledc/ch_gamma_rd_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_GAMMA_RD_ADDR")
-            .field(
-                "ch_gamma_rd_addr",
-                &format_args!("{}", self.ch_gamma_rd_addr().bits()),
-            )
+            .field("ch_gamma_rd_addr", &self.ch_gamma_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_GAMMA_RD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Ledc ch%s gamma ram read address."]
     #[inline(always)]
diff --git a/esp32h2/src/ledc/ch_gamma_rd_data.rs b/esp32h2/src/ledc/ch_gamma_rd_data.rs
index 4ec4d1e45e..b6bb1301ff 100644
--- a/esp32h2/src/ledc/ch_gamma_rd_data.rs
+++ b/esp32h2/src/ledc/ch_gamma_rd_data.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_GAMMA_RD_DATA")
-            .field(
-                "ch_gamma_rd_data",
-                &format_args!("{}", self.ch_gamma_rd_data().bits()),
-            )
+            .field("ch_gamma_rd_data", &self.ch_gamma_rd_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_GAMMA_RD_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Ledc ch%s gamma ram read data register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_gamma_rd_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_GAMMA_RD_DATA_SPEC;
 impl crate::RegisterSpec for CH_GAMMA_RD_DATA_SPEC {
diff --git a/esp32h2/src/ledc/ch_gamma_wr.rs b/esp32h2/src/ledc/ch_gamma_wr.rs
index 3446d2b56f..fb55130bd3 100644
--- a/esp32h2/src/ledc/ch_gamma_wr.rs
+++ b/esp32h2/src/ledc/ch_gamma_wr.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_GAMMA_WR")
-            .field(
-                "ch_gamma_duty_inc",
-                &format_args!("{}", self.ch_gamma_duty_inc().bit()),
-            )
-            .field(
-                "ch_gamma_duty_cycle",
-                &format_args!("{}", self.ch_gamma_duty_cycle().bits()),
-            )
-            .field(
-                "ch_gamma_scale",
-                &format_args!("{}", self.ch_gamma_scale().bits()),
-            )
-            .field(
-                "ch_gamma_duty_num",
-                &format_args!("{}", self.ch_gamma_duty_num().bits()),
-            )
+            .field("ch_gamma_duty_inc", &self.ch_gamma_duty_inc())
+            .field("ch_gamma_duty_cycle", &self.ch_gamma_duty_cycle())
+            .field("ch_gamma_scale", &self.ch_gamma_scale())
+            .field("ch_gamma_duty_num", &self.ch_gamma_duty_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_GAMMA_WR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Ledc ch%s gamma duty inc of current ram write address.This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase 0: Decrease."]
     #[inline(always)]
diff --git a/esp32h2/src/ledc/ch_gamma_wr_addr.rs b/esp32h2/src/ledc/ch_gamma_wr_addr.rs
index a339036095..8a8141e060 100644
--- a/esp32h2/src/ledc/ch_gamma_wr_addr.rs
+++ b/esp32h2/src/ledc/ch_gamma_wr_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_GAMMA_WR_ADDR")
-            .field(
-                "ch_gamma_wr_addr",
-                &format_args!("{}", self.ch_gamma_wr_addr().bits()),
-            )
+            .field("ch_gamma_wr_addr", &self.ch_gamma_wr_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_GAMMA_WR_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Ledc ch%s gamma ram write address."]
     #[inline(always)]
diff --git a/esp32h2/src/ledc/conf.rs b/esp32h2/src/ledc/conf.rs
index 456a31a619..89cc715a69 100644
--- a/esp32h2/src/ledc/conf.rs
+++ b/esp32h2/src/ledc/conf.rs
@@ -80,44 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field(
-                "apb_clk_sel",
-                &format_args!("{}", self.apb_clk_sel().bits()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch0",
-                &format_args!("{}", self.gamma_ram_clk_en_ch0().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch1",
-                &format_args!("{}", self.gamma_ram_clk_en_ch1().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch2",
-                &format_args!("{}", self.gamma_ram_clk_en_ch2().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch3",
-                &format_args!("{}", self.gamma_ram_clk_en_ch3().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch4",
-                &format_args!("{}", self.gamma_ram_clk_en_ch4().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch5",
-                &format_args!("{}", self.gamma_ram_clk_en_ch5().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("apb_clk_sel", &self.apb_clk_sel())
+            .field("gamma_ram_clk_en_ch0", &self.gamma_ram_clk_en_ch0())
+            .field("gamma_ram_clk_en_ch1", &self.gamma_ram_clk_en_ch1())
+            .field("gamma_ram_clk_en_ch2", &self.gamma_ram_clk_en_ch2())
+            .field("gamma_ram_clk_en_ch3", &self.gamma_ram_clk_en_ch3())
+            .field("gamma_ram_clk_en_ch4", &self.gamma_ram_clk_en_ch4())
+            .field("gamma_ram_clk_en_ch5", &self.gamma_ram_clk_en_ch5())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This bit is used to select clock source for the 4 timers . 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK"]
     #[inline(always)]
diff --git a/esp32h2/src/ledc/date.rs b/esp32h2/src/ledc/date.rs
index 30a5b4ffff..de5a7a8661 100644
--- a/esp32h2/src/ledc/date.rs
+++ b/esp32h2/src/ledc/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("ledc_date", &format_args!("{}", self.ledc_date().bits()))
+            .field("ledc_date", &self.ledc_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - This is the version control register."]
     #[inline(always)]
diff --git a/esp32h2/src/ledc/evt_task_en0.rs b/esp32h2/src/ledc/evt_task_en0.rs
index efc0e38bd2..ef7bef4a44 100644
--- a/esp32h2/src/ledc/evt_task_en0.rs
+++ b/esp32h2/src/ledc/evt_task_en0.rs
@@ -242,119 +242,53 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVT_TASK_EN0")
-            .field(
-                "evt_duty_chng_end_ch0_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch0_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch1_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch1_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch2_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch2_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch3_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch3_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch4_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch4_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch5_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch5_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch0_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch0_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch1_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch1_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch2_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch2_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch3_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch3_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch4_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch4_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch5_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch5_en().bit()),
-            )
-            .field(
-                "evt_time_ovf_timer0_en",
-                &format_args!("{}", self.evt_time_ovf_timer0_en().bit()),
-            )
-            .field(
-                "evt_time_ovf_timer1_en",
-                &format_args!("{}", self.evt_time_ovf_timer1_en().bit()),
-            )
-            .field(
-                "evt_time_ovf_timer2_en",
-                &format_args!("{}", self.evt_time_ovf_timer2_en().bit()),
-            )
-            .field(
-                "evt_time_ovf_timer3_en",
-                &format_args!("{}", self.evt_time_ovf_timer3_en().bit()),
-            )
-            .field(
-                "evt_time0_cmp_en",
-                &format_args!("{}", self.evt_time0_cmp_en().bit()),
-            )
-            .field(
-                "evt_time1_cmp_en",
-                &format_args!("{}", self.evt_time1_cmp_en().bit()),
-            )
-            .field(
-                "evt_time2_cmp_en",
-                &format_args!("{}", self.evt_time2_cmp_en().bit()),
-            )
-            .field(
-                "evt_time3_cmp_en",
-                &format_args!("{}", self.evt_time3_cmp_en().bit()),
-            )
+            .field("evt_duty_chng_end_ch0_en", &self.evt_duty_chng_end_ch0_en())
+            .field("evt_duty_chng_end_ch1_en", &self.evt_duty_chng_end_ch1_en())
+            .field("evt_duty_chng_end_ch2_en", &self.evt_duty_chng_end_ch2_en())
+            .field("evt_duty_chng_end_ch3_en", &self.evt_duty_chng_end_ch3_en())
+            .field("evt_duty_chng_end_ch4_en", &self.evt_duty_chng_end_ch4_en())
+            .field("evt_duty_chng_end_ch5_en", &self.evt_duty_chng_end_ch5_en())
+            .field("evt_ovf_cnt_pls_ch0_en", &self.evt_ovf_cnt_pls_ch0_en())
+            .field("evt_ovf_cnt_pls_ch1_en", &self.evt_ovf_cnt_pls_ch1_en())
+            .field("evt_ovf_cnt_pls_ch2_en", &self.evt_ovf_cnt_pls_ch2_en())
+            .field("evt_ovf_cnt_pls_ch3_en", &self.evt_ovf_cnt_pls_ch3_en())
+            .field("evt_ovf_cnt_pls_ch4_en", &self.evt_ovf_cnt_pls_ch4_en())
+            .field("evt_ovf_cnt_pls_ch5_en", &self.evt_ovf_cnt_pls_ch5_en())
+            .field("evt_time_ovf_timer0_en", &self.evt_time_ovf_timer0_en())
+            .field("evt_time_ovf_timer1_en", &self.evt_time_ovf_timer1_en())
+            .field("evt_time_ovf_timer2_en", &self.evt_time_ovf_timer2_en())
+            .field("evt_time_ovf_timer3_en", &self.evt_time_ovf_timer3_en())
+            .field("evt_time0_cmp_en", &self.evt_time0_cmp_en())
+            .field("evt_time1_cmp_en", &self.evt_time1_cmp_en())
+            .field("evt_time2_cmp_en", &self.evt_time2_cmp_en())
+            .field("evt_time3_cmp_en", &self.evt_time3_cmp_en())
             .field(
                 "task_duty_scale_update_ch0_en",
-                &format_args!("{}", self.task_duty_scale_update_ch0_en().bit()),
+                &self.task_duty_scale_update_ch0_en(),
             )
             .field(
                 "task_duty_scale_update_ch1_en",
-                &format_args!("{}", self.task_duty_scale_update_ch1_en().bit()),
+                &self.task_duty_scale_update_ch1_en(),
             )
             .field(
                 "task_duty_scale_update_ch2_en",
-                &format_args!("{}", self.task_duty_scale_update_ch2_en().bit()),
+                &self.task_duty_scale_update_ch2_en(),
             )
             .field(
                 "task_duty_scale_update_ch3_en",
-                &format_args!("{}", self.task_duty_scale_update_ch3_en().bit()),
+                &self.task_duty_scale_update_ch3_en(),
             )
             .field(
                 "task_duty_scale_update_ch4_en",
-                &format_args!("{}", self.task_duty_scale_update_ch4_en().bit()),
+                &self.task_duty_scale_update_ch4_en(),
             )
             .field(
                 "task_duty_scale_update_ch5_en",
-                &format_args!("{}", self.task_duty_scale_update_ch5_en().bit()),
+                &self.task_duty_scale_update_ch5_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_TASK_EN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Ledc ch0 duty change end event enable register, write 1 to enable this event."]
     #[inline(always)]
diff --git a/esp32h2/src/ledc/evt_task_en1.rs b/esp32h2/src/ledc/evt_task_en1.rs
index c280c82c92..38b6535dd6 100644
--- a/esp32h2/src/ledc/evt_task_en1.rs
+++ b/esp32h2/src/ledc/evt_task_en1.rs
@@ -262,125 +262,59 @@ impl core::fmt::Debug for R {
         f.debug_struct("EVT_TASK_EN1")
             .field(
                 "task_timer0_res_update_en",
-                &format_args!("{}", self.task_timer0_res_update_en().bit()),
+                &self.task_timer0_res_update_en(),
             )
             .field(
                 "task_timer1_res_update_en",
-                &format_args!("{}", self.task_timer1_res_update_en().bit()),
+                &self.task_timer1_res_update_en(),
             )
             .field(
                 "task_timer2_res_update_en",
-                &format_args!("{}", self.task_timer2_res_update_en().bit()),
+                &self.task_timer2_res_update_en(),
             )
             .field(
                 "task_timer3_res_update_en",
-                &format_args!("{}", self.task_timer3_res_update_en().bit()),
-            )
-            .field(
-                "task_timer0_cap_en",
-                &format_args!("{}", self.task_timer0_cap_en().bit()),
-            )
-            .field(
-                "task_timer1_cap_en",
-                &format_args!("{}", self.task_timer1_cap_en().bit()),
-            )
-            .field(
-                "task_timer2_cap_en",
-                &format_args!("{}", self.task_timer2_cap_en().bit()),
-            )
-            .field(
-                "task_timer3_cap_en",
-                &format_args!("{}", self.task_timer3_cap_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch0_en",
-                &format_args!("{}", self.task_sig_out_dis_ch0_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch1_en",
-                &format_args!("{}", self.task_sig_out_dis_ch1_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch2_en",
-                &format_args!("{}", self.task_sig_out_dis_ch2_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch3_en",
-                &format_args!("{}", self.task_sig_out_dis_ch3_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch4_en",
-                &format_args!("{}", self.task_sig_out_dis_ch4_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch5_en",
-                &format_args!("{}", self.task_sig_out_dis_ch5_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch0_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch0_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch1_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch1_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch2_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch2_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch3_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch3_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch4_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch4_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch5_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch5_en().bit()),
-            )
-            .field(
-                "task_timer0_rst_en",
-                &format_args!("{}", self.task_timer0_rst_en().bit()),
-            )
-            .field(
-                "task_timer1_rst_en",
-                &format_args!("{}", self.task_timer1_rst_en().bit()),
-            )
-            .field(
-                "task_timer2_rst_en",
-                &format_args!("{}", self.task_timer2_rst_en().bit()),
-            )
-            .field(
-                "task_timer3_rst_en",
-                &format_args!("{}", self.task_timer3_rst_en().bit()),
+                &self.task_timer3_res_update_en(),
             )
+            .field("task_timer0_cap_en", &self.task_timer0_cap_en())
+            .field("task_timer1_cap_en", &self.task_timer1_cap_en())
+            .field("task_timer2_cap_en", &self.task_timer2_cap_en())
+            .field("task_timer3_cap_en", &self.task_timer3_cap_en())
+            .field("task_sig_out_dis_ch0_en", &self.task_sig_out_dis_ch0_en())
+            .field("task_sig_out_dis_ch1_en", &self.task_sig_out_dis_ch1_en())
+            .field("task_sig_out_dis_ch2_en", &self.task_sig_out_dis_ch2_en())
+            .field("task_sig_out_dis_ch3_en", &self.task_sig_out_dis_ch3_en())
+            .field("task_sig_out_dis_ch4_en", &self.task_sig_out_dis_ch4_en())
+            .field("task_sig_out_dis_ch5_en", &self.task_sig_out_dis_ch5_en())
+            .field("task_ovf_cnt_rst_ch0_en", &self.task_ovf_cnt_rst_ch0_en())
+            .field("task_ovf_cnt_rst_ch1_en", &self.task_ovf_cnt_rst_ch1_en())
+            .field("task_ovf_cnt_rst_ch2_en", &self.task_ovf_cnt_rst_ch2_en())
+            .field("task_ovf_cnt_rst_ch3_en", &self.task_ovf_cnt_rst_ch3_en())
+            .field("task_ovf_cnt_rst_ch4_en", &self.task_ovf_cnt_rst_ch4_en())
+            .field("task_ovf_cnt_rst_ch5_en", &self.task_ovf_cnt_rst_ch5_en())
+            .field("task_timer0_rst_en", &self.task_timer0_rst_en())
+            .field("task_timer1_rst_en", &self.task_timer1_rst_en())
+            .field("task_timer2_rst_en", &self.task_timer2_rst_en())
+            .field("task_timer3_rst_en", &self.task_timer3_rst_en())
             .field(
                 "task_timer0_pause_resume_en",
-                &format_args!("{}", self.task_timer0_pause_resume_en().bit()),
+                &self.task_timer0_pause_resume_en(),
             )
             .field(
                 "task_timer1_pause_resume_en",
-                &format_args!("{}", self.task_timer1_pause_resume_en().bit()),
+                &self.task_timer1_pause_resume_en(),
             )
             .field(
                 "task_timer2_pause_resume_en",
-                &format_args!("{}", self.task_timer2_pause_resume_en().bit()),
+                &self.task_timer2_pause_resume_en(),
             )
             .field(
                 "task_timer3_pause_resume_en",
-                &format_args!("{}", self.task_timer3_pause_resume_en().bit()),
+                &self.task_timer3_pause_resume_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_TASK_EN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Ledc timer0 res update task enable register, write 1 to enable this task."]
     #[inline(always)]
diff --git a/esp32h2/src/ledc/evt_task_en2.rs b/esp32h2/src/ledc/evt_task_en2.rs
index 854ef2967f..0d920579b4 100644
--- a/esp32h2/src/ledc/evt_task_en2.rs
+++ b/esp32h2/src/ledc/evt_task_en2.rs
@@ -172,85 +172,43 @@ impl core::fmt::Debug for R {
         f.debug_struct("EVT_TASK_EN2")
             .field(
                 "task_gamma_restart_ch0_en",
-                &format_args!("{}", self.task_gamma_restart_ch0_en().bit()),
+                &self.task_gamma_restart_ch0_en(),
             )
             .field(
                 "task_gamma_restart_ch1_en",
-                &format_args!("{}", self.task_gamma_restart_ch1_en().bit()),
+                &self.task_gamma_restart_ch1_en(),
             )
             .field(
                 "task_gamma_restart_ch2_en",
-                &format_args!("{}", self.task_gamma_restart_ch2_en().bit()),
+                &self.task_gamma_restart_ch2_en(),
             )
             .field(
                 "task_gamma_restart_ch3_en",
-                &format_args!("{}", self.task_gamma_restart_ch3_en().bit()),
+                &self.task_gamma_restart_ch3_en(),
             )
             .field(
                 "task_gamma_restart_ch4_en",
-                &format_args!("{}", self.task_gamma_restart_ch4_en().bit()),
+                &self.task_gamma_restart_ch4_en(),
             )
             .field(
                 "task_gamma_restart_ch5_en",
-                &format_args!("{}", self.task_gamma_restart_ch5_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch0_en",
-                &format_args!("{}", self.task_gamma_pause_ch0_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch1_en",
-                &format_args!("{}", self.task_gamma_pause_ch1_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch2_en",
-                &format_args!("{}", self.task_gamma_pause_ch2_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch3_en",
-                &format_args!("{}", self.task_gamma_pause_ch3_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch4_en",
-                &format_args!("{}", self.task_gamma_pause_ch4_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch5_en",
-                &format_args!("{}", self.task_gamma_pause_ch5_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch0_en",
-                &format_args!("{}", self.task_gamma_resume_ch0_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch1_en",
-                &format_args!("{}", self.task_gamma_resume_ch1_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch2_en",
-                &format_args!("{}", self.task_gamma_resume_ch2_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch3_en",
-                &format_args!("{}", self.task_gamma_resume_ch3_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch4_en",
-                &format_args!("{}", self.task_gamma_resume_ch4_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch5_en",
-                &format_args!("{}", self.task_gamma_resume_ch5_en().bit()),
+                &self.task_gamma_restart_ch5_en(),
             )
+            .field("task_gamma_pause_ch0_en", &self.task_gamma_pause_ch0_en())
+            .field("task_gamma_pause_ch1_en", &self.task_gamma_pause_ch1_en())
+            .field("task_gamma_pause_ch2_en", &self.task_gamma_pause_ch2_en())
+            .field("task_gamma_pause_ch3_en", &self.task_gamma_pause_ch3_en())
+            .field("task_gamma_pause_ch4_en", &self.task_gamma_pause_ch4_en())
+            .field("task_gamma_pause_ch5_en", &self.task_gamma_pause_ch5_en())
+            .field("task_gamma_resume_ch0_en", &self.task_gamma_resume_ch0_en())
+            .field("task_gamma_resume_ch1_en", &self.task_gamma_resume_ch1_en())
+            .field("task_gamma_resume_ch2_en", &self.task_gamma_resume_ch2_en())
+            .field("task_gamma_resume_ch3_en", &self.task_gamma_resume_ch3_en())
+            .field("task_gamma_resume_ch4_en", &self.task_gamma_resume_ch4_en())
+            .field("task_gamma_resume_ch5_en", &self.task_gamma_resume_ch5_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_TASK_EN2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Ledc ch0 gamma restart task enable register, write 1 to enable this task."]
     #[inline(always)]
diff --git a/esp32h2/src/ledc/int_ena.rs b/esp32h2/src/ledc/int_ena.rs
index b9a4a96b44..faa3849af3 100644
--- a/esp32h2/src/ledc/int_ena.rs
+++ b/esp32h2/src/ledc/int_ena.rs
@@ -145,49 +145,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the TIMER(0-3)_OVF interrupt."]
     #[doc = ""]
diff --git a/esp32h2/src/ledc/int_raw.rs b/esp32h2/src/ledc/int_raw.rs
index 5268b7ffc5..ef2455717c 100644
--- a/esp32h2/src/ledc/int_raw.rs
+++ b/esp32h2/src/ledc/int_raw.rs
@@ -145,49 +145,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Triggered when the timer(0-3) has reached its maximum counter value."]
     #[doc = ""]
diff --git a/esp32h2/src/ledc/int_st.rs b/esp32h2/src/ledc/int_st.rs
index 32fc7886ec..61b6043bab 100644
--- a/esp32h2/src/ledc/int_st.rs
+++ b/esp32h2/src/ledc/int_st.rs
@@ -137,49 +137,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/ledc/timer/conf.rs b/esp32h2/src/ledc/timer/conf.rs
index 65e571f33d..0b29b0dbf4 100644
--- a/esp32h2/src/ledc/timer/conf.rs
+++ b/esp32h2/src/ledc/timer/conf.rs
@@ -55,20 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("duty_res", &format_args!("{}", self.duty_res().bits()))
-            .field("clk_div", &format_args!("{}", self.clk_div().bits()))
-            .field("pause", &format_args!("{}", self.pause().bit()))
-            .field("rst", &format_args!("{}", self.rst().bit()))
-            .field("tick_sel", &format_args!("{}", self.tick_sel().bit()))
+            .field("duty_res", &self.duty_res())
+            .field("clk_div", &self.clk_div())
+            .field("pause", &self.pause())
+            .field("rst", &self.rst())
+            .field("tick_sel", &self.tick_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to control the range of the counter in timer %s."]
     #[inline(always)]
diff --git a/esp32h2/src/ledc/timer/value.rs b/esp32h2/src/ledc/timer/value.rs
index 0a29a10a74..b694c379b1 100644
--- a/esp32h2/src/ledc/timer/value.rs
+++ b/esp32h2/src/ledc/timer/value.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("VALUE")
-            .field("cnt", &format_args!("{}", self.cnt().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("VALUE").field("cnt", &self.cnt()).finish()
     }
 }
 #[doc = "Timer 0 current counter value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32h2/src/ledc/timer_cmp.rs b/esp32h2/src/ledc/timer_cmp.rs
index adffb5f9a9..ebcea1539c 100644
--- a/esp32h2/src/ledc/timer_cmp.rs
+++ b/esp32h2/src/ledc/timer_cmp.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_CMP")
-            .field("timer_cmp", &format_args!("{}", self.timer_cmp().bits()))
+            .field("timer_cmp", &self.timer_cmp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_CMP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register stores ledc timer%s compare value."]
     #[inline(always)]
diff --git a/esp32h2/src/ledc/timer_cnt_cap.rs b/esp32h2/src/ledc/timer_cnt_cap.rs
index 1554e17d25..225284dd8c 100644
--- a/esp32h2/src/ledc/timer_cnt_cap.rs
+++ b/esp32h2/src/ledc/timer_cnt_cap.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_CNT_CAP")
-            .field(
-                "timer_cnt_cap",
-                &format_args!("{}", self.timer_cnt_cap().bits()),
-            )
+            .field("timer_cnt_cap", &self.timer_cnt_cap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_CNT_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Ledc timer%s count value capture register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_cnt_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMER_CNT_CAP_SPEC;
 impl crate::RegisterSpec for TIMER_CNT_CAP_SPEC {
diff --git a/esp32h2/src/lib.rs b/esp32h2/src/lib.rs
index 3178df7598..58253202ae 100644
--- a/esp32h2/src/lib.rs
+++ b/esp32h2/src/lib.rs
@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32-H2 microcontrollers (generated using svd2rust v0.33.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32-H2 microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
diff --git a/esp32h2/src/lp_ana/bod_mode0_cntl.rs b/esp32h2/src/lp_ana/bod_mode0_cntl.rs
index 4eae1d17a9..51c9ae872d 100644
--- a/esp32h2/src/lp_ana/bod_mode0_cntl.rs
+++ b/esp32h2/src/lp_ana/bod_mode0_cntl.rs
@@ -82,45 +82,18 @@ impl core::fmt::Debug for R {
         f.debug_struct("BOD_MODE0_CNTL")
             .field(
                 "bod_mode0_close_flash_ena",
-                &format_args!("{}", self.bod_mode0_close_flash_ena().bit()),
-            )
-            .field(
-                "bod_mode0_pd_rf_ena",
-                &format_args!("{}", self.bod_mode0_pd_rf_ena().bit()),
-            )
-            .field(
-                "bod_mode0_intr_wait",
-                &format_args!("{}", self.bod_mode0_intr_wait().bits()),
-            )
-            .field(
-                "bod_mode0_reset_wait",
-                &format_args!("{}", self.bod_mode0_reset_wait().bits()),
-            )
-            .field(
-                "bod_mode0_cnt_clr",
-                &format_args!("{}", self.bod_mode0_cnt_clr().bit()),
-            )
-            .field(
-                "bod_mode0_intr_ena",
-                &format_args!("{}", self.bod_mode0_intr_ena().bit()),
-            )
-            .field(
-                "bod_mode0_reset_sel",
-                &format_args!("{}", self.bod_mode0_reset_sel().bit()),
-            )
-            .field(
-                "bod_mode0_reset_ena",
-                &format_args!("{}", self.bod_mode0_reset_ena().bit()),
+                &self.bod_mode0_close_flash_ena(),
             )
+            .field("bod_mode0_pd_rf_ena", &self.bod_mode0_pd_rf_ena())
+            .field("bod_mode0_intr_wait", &self.bod_mode0_intr_wait())
+            .field("bod_mode0_reset_wait", &self.bod_mode0_reset_wait())
+            .field("bod_mode0_cnt_clr", &self.bod_mode0_cnt_clr())
+            .field("bod_mode0_intr_ena", &self.bod_mode0_intr_ena())
+            .field("bod_mode0_reset_sel", &self.bod_mode0_reset_sel())
+            .field("bod_mode0_reset_ena", &self.bod_mode0_reset_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BOD_MODE0_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_ana/bod_mode1_cntl.rs b/esp32h2/src/lp_ana/bod_mode1_cntl.rs
index daab8a45d0..3aa7fe569f 100644
--- a/esp32h2/src/lp_ana/bod_mode1_cntl.rs
+++ b/esp32h2/src/lp_ana/bod_mode1_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BOD_MODE1_CNTL")
-            .field(
-                "bod_mode1_reset_ena",
-                &format_args!("{}", self.bod_mode1_reset_ena().bit()),
-            )
+            .field("bod_mode1_reset_ena", &self.bod_mode1_reset_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BOD_MODE1_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_ana/ck_glitch_cntl.rs b/esp32h2/src/lp_ana/ck_glitch_cntl.rs
index 603bbcf118..e33a2b6db7 100644
--- a/esp32h2/src/lp_ana/ck_glitch_cntl.rs
+++ b/esp32h2/src/lp_ana/ck_glitch_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CK_GLITCH_CNTL")
-            .field(
-                "ck_glitch_reset_ena",
-                &format_args!("{}", self.ck_glitch_reset_ena().bit()),
-            )
+            .field("ck_glitch_reset_ena", &self.ck_glitch_reset_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CK_GLITCH_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_ana/date.rs b/esp32h2/src/lp_ana/date.rs
index 9773c81699..65fb6e9f94 100644
--- a/esp32h2/src/lp_ana/date.rs
+++ b/esp32h2/src/lp_ana/date.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "lp_ana_date",
-                &format_args!("{}", self.lp_ana_date().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("lp_ana_date", &self.lp_ana_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_ana/fib_enable.rs b/esp32h2/src/lp_ana/fib_enable.rs
index 4b991a5896..e6b9fbc95c 100644
--- a/esp32h2/src/lp_ana/fib_enable.rs
+++ b/esp32h2/src/lp_ana/fib_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIB_ENABLE")
-            .field(
-                "ana_fib_ena",
-                &format_args!("{}", self.ana_fib_ena().bits()),
-            )
+            .field("ana_fib_ena", &self.ana_fib_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIB_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_ana/int_ena.rs b/esp32h2/src/lp_ana/int_ena.rs
index 124fd27b7b..f7bc20cc03 100644
--- a/esp32h2/src/lp_ana/int_ena.rs
+++ b/esp32h2/src/lp_ana/int_ena.rs
@@ -53,32 +53,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "vddbat_charge_upvoltage",
-                &format_args!("{}", self.vddbat_charge_upvoltage().bit()),
-            )
+            .field("vddbat_charge_upvoltage", &self.vddbat_charge_upvoltage())
             .field(
                 "vddbat_charge_undervoltage",
-                &format_args!("{}", self.vddbat_charge_undervoltage().bit()),
+                &self.vddbat_charge_undervoltage(),
             )
-            .field(
-                "vddbat_upvoltage",
-                &format_args!("{}", self.vddbat_upvoltage().bit()),
-            )
-            .field(
-                "vddbat_undervoltage",
-                &format_args!("{}", self.vddbat_undervoltage().bit()),
-            )
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("vddbat_upvoltage", &self.vddbat_upvoltage())
+            .field("vddbat_undervoltage", &self.vddbat_undervoltage())
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_ana/int_raw.rs b/esp32h2/src/lp_ana/int_raw.rs
index 7b62d3b106..9bdc535bcc 100644
--- a/esp32h2/src/lp_ana/int_raw.rs
+++ b/esp32h2/src/lp_ana/int_raw.rs
@@ -53,32 +53,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "vddbat_charge_upvoltage",
-                &format_args!("{}", self.vddbat_charge_upvoltage().bit()),
-            )
+            .field("vddbat_charge_upvoltage", &self.vddbat_charge_upvoltage())
             .field(
                 "vddbat_charge_undervoltage",
-                &format_args!("{}", self.vddbat_charge_undervoltage().bit()),
+                &self.vddbat_charge_undervoltage(),
             )
-            .field(
-                "vddbat_upvoltage",
-                &format_args!("{}", self.vddbat_upvoltage().bit()),
-            )
-            .field(
-                "vddbat_undervoltage",
-                &format_args!("{}", self.vddbat_undervoltage().bit()),
-            )
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("vddbat_upvoltage", &self.vddbat_upvoltage())
+            .field("vddbat_undervoltage", &self.vddbat_undervoltage())
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_ana/int_st.rs b/esp32h2/src/lp_ana/int_st.rs
index 3d16eefff5..a7176f7ab7 100644
--- a/esp32h2/src/lp_ana/int_st.rs
+++ b/esp32h2/src/lp_ana/int_st.rs
@@ -41,32 +41,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "vddbat_charge_upvoltage",
-                &format_args!("{}", self.vddbat_charge_upvoltage().bit()),
-            )
+            .field("vddbat_charge_upvoltage", &self.vddbat_charge_upvoltage())
             .field(
                 "vddbat_charge_undervoltage",
-                &format_args!("{}", self.vddbat_charge_undervoltage().bit()),
+                &self.vddbat_charge_undervoltage(),
             )
-            .field(
-                "vddbat_upvoltage",
-                &format_args!("{}", self.vddbat_upvoltage().bit()),
-            )
-            .field(
-                "vddbat_undervoltage",
-                &format_args!("{}", self.vddbat_undervoltage().bit()),
-            )
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("vddbat_upvoltage", &self.vddbat_upvoltage())
+            .field("vddbat_undervoltage", &self.vddbat_undervoltage())
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/lp_ana/lp_int_ena.rs b/esp32h2/src/lp_ana/lp_int_ena.rs
index 20c74f7372..044e93357d 100644
--- a/esp32h2/src/lp_ana/lp_int_ena.rs
+++ b/esp32h2/src/lp_ana/lp_int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ENA")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_ana/lp_int_raw.rs b/esp32h2/src/lp_ana/lp_int_raw.rs
index fcbabdea21..dde3b77a5d 100644
--- a/esp32h2/src/lp_ana/lp_int_raw.rs
+++ b/esp32h2/src/lp_ana/lp_int_raw.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_RAW")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_ana/lp_int_st.rs b/esp32h2/src/lp_ana/lp_int_st.rs
index 8516622718..2e393bffab 100644
--- a/esp32h2/src/lp_ana/lp_int_st.rs
+++ b/esp32h2/src/lp_ana/lp_int_st.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ST")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_INT_ST_SPEC;
 impl crate::RegisterSpec for LP_INT_ST_SPEC {
diff --git a/esp32h2/src/lp_ana/pg_glitch_cntl.rs b/esp32h2/src/lp_ana/pg_glitch_cntl.rs
index 19b273019e..747b98374c 100644
--- a/esp32h2/src/lp_ana/pg_glitch_cntl.rs
+++ b/esp32h2/src/lp_ana/pg_glitch_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PG_GLITCH_CNTL")
-            .field(
-                "power_glitch_reset_ena",
-                &format_args!("{}", self.power_glitch_reset_ena().bit()),
-            )
+            .field("power_glitch_reset_ena", &self.power_glitch_reset_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PG_GLITCH_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_ana/vdd_source_cntl.rs b/esp32h2/src/lp_ana/vdd_source_cntl.rs
index 1ecbb2d162..5d407afd57 100644
--- a/esp32h2/src/lp_ana/vdd_source_cntl.rs
+++ b/esp32h2/src/lp_ana/vdd_source_cntl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VDD_SOURCE_CNTL")
-            .field(
-                "detmode_sel",
-                &format_args!("{}", self.detmode_sel().bits()),
-            )
-            .field(
-                "vgood_event_record",
-                &format_args!("{}", self.vgood_event_record().bits()),
-            )
-            .field(
-                "bod_source_ena",
-                &format_args!("{}", self.bod_source_ena().bits()),
-            )
+            .field("detmode_sel", &self.detmode_sel())
+            .field("vgood_event_record", &self.vgood_event_record())
+            .field("bod_source_ena", &self.bod_source_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VDD_SOURCE_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_ana/vddbat_bod_cntl.rs b/esp32h2/src/lp_ana/vddbat_bod_cntl.rs
index b246574595..3f51154a37 100644
--- a/esp32h2/src/lp_ana/vddbat_bod_cntl.rs
+++ b/esp32h2/src/lp_ana/vddbat_bod_cntl.rs
@@ -51,35 +51,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VDDBAT_BOD_CNTL")
-            .field(
-                "vddbat_undervoltage_flag",
-                &format_args!("{}", self.vddbat_undervoltage_flag().bit()),
-            )
-            .field(
-                "vddbat_charger",
-                &format_args!("{}", self.vddbat_charger().bit()),
-            )
-            .field(
-                "vddbat_cnt_clr",
-                &format_args!("{}", self.vddbat_cnt_clr().bit()),
-            )
-            .field(
-                "vddbat_upvoltage_target",
-                &format_args!("{}", self.vddbat_upvoltage_target().bits()),
-            )
+            .field("vddbat_undervoltage_flag", &self.vddbat_undervoltage_flag())
+            .field("vddbat_charger", &self.vddbat_charger())
+            .field("vddbat_cnt_clr", &self.vddbat_cnt_clr())
+            .field("vddbat_upvoltage_target", &self.vddbat_upvoltage_target())
             .field(
                 "vddbat_undervoltage_target",
-                &format_args!("{}", self.vddbat_undervoltage_target().bits()),
+                &self.vddbat_undervoltage_target(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VDDBAT_BOD_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 10 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_ana/vddbat_charge_cntl.rs b/esp32h2/src/lp_ana/vddbat_charge_cntl.rs
index 0d3c6367e5..063631ba31 100644
--- a/esp32h2/src/lp_ana/vddbat_charge_cntl.rs
+++ b/esp32h2/src/lp_ana/vddbat_charge_cntl.rs
@@ -53,33 +53,21 @@ impl core::fmt::Debug for R {
         f.debug_struct("VDDBAT_CHARGE_CNTL")
             .field(
                 "vddbat_charge_undervoltage_flag",
-                &format_args!("{}", self.vddbat_charge_undervoltage_flag().bit()),
-            )
-            .field(
-                "vddbat_charge_charger",
-                &format_args!("{}", self.vddbat_charge_charger().bit()),
-            )
-            .field(
-                "vddbat_charge_cnt_clr",
-                &format_args!("{}", self.vddbat_charge_cnt_clr().bit()),
+                &self.vddbat_charge_undervoltage_flag(),
             )
+            .field("vddbat_charge_charger", &self.vddbat_charge_charger())
+            .field("vddbat_charge_cnt_clr", &self.vddbat_charge_cnt_clr())
             .field(
                 "vddbat_charge_upvoltage_target",
-                &format_args!("{}", self.vddbat_charge_upvoltage_target().bits()),
+                &self.vddbat_charge_upvoltage_target(),
             )
             .field(
                 "vddbat_charge_undervoltage_target",
-                &format_args!("{}", self.vddbat_charge_undervoltage_target().bits()),
+                &self.vddbat_charge_undervoltage_target(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VDDBAT_CHARGE_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 10 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/cpucore0_cfg.rs b/esp32h2/src/lp_aon/cpucore0_cfg.rs
index 8582b7abe3..b8f00ddbcf 100644
--- a/esp32h2/src/lp_aon/cpucore0_cfg.rs
+++ b/esp32h2/src/lp_aon/cpucore0_cfg.rs
@@ -46,31 +46,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPUCORE0_CFG")
-            .field(
-                "cpu_core0_sw_stall",
-                &format_args!("{}", self.cpu_core0_sw_stall().bits()),
-            )
+            .field("cpu_core0_sw_stall", &self.cpu_core0_sw_stall())
             .field(
                 "cpu_core0_ocd_halt_on_reset",
-                &format_args!("{}", self.cpu_core0_ocd_halt_on_reset().bit()),
+                &self.cpu_core0_ocd_halt_on_reset(),
             )
             .field(
                 "cpu_core0_stat_vector_sel",
-                &format_args!("{}", self.cpu_core0_stat_vector_sel().bit()),
-            )
-            .field(
-                "cpu_core0_dreset_mask",
-                &format_args!("{}", self.cpu_core0_dreset_mask().bit()),
+                &self.cpu_core0_stat_vector_sel(),
             )
+            .field("cpu_core0_dreset_mask", &self.cpu_core0_dreset_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPUCORE0_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/date.rs b/esp32h2/src/lp_aon/date.rs
index 994be02d31..6cfe21da6f 100644
--- a/esp32h2/src/lp_aon/date.rs
+++ b/esp32h2/src/lp_aon/date.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("date", &self.date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/ext_wakeup_cntl.rs b/esp32h2/src/lp_aon/ext_wakeup_cntl.rs
index d9f39d0a90..0b2d26e41a 100644
--- a/esp32h2/src/lp_aon/ext_wakeup_cntl.rs
+++ b/esp32h2/src/lp_aon/ext_wakeup_cntl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP_CNTL")
-            .field(
-                "ext_wakeup_status",
-                &format_args!("{}", self.ext_wakeup_status().bits()),
-            )
-            .field(
-                "ext_wakeup_sel",
-                &format_args!("{}", self.ext_wakeup_sel().bits()),
-            )
-            .field(
-                "ext_wakeup_lv",
-                &format_args!("{}", self.ext_wakeup_lv().bits()),
-            )
-            .field(
-                "ext_wakeup_filter",
-                &format_args!("{}", self.ext_wakeup_filter().bit()),
-            )
+            .field("ext_wakeup_status", &self.ext_wakeup_status())
+            .field("ext_wakeup_sel", &self.ext_wakeup_sel())
+            .field("ext_wakeup_lv", &self.ext_wakeup_lv())
+            .field("ext_wakeup_filter", &self.ext_wakeup_filter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 14 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/gpio_hold0.rs b/esp32h2/src/lp_aon/gpio_hold0.rs
index b332611022..0fc6ebfa90 100644
--- a/esp32h2/src/lp_aon/gpio_hold0.rs
+++ b/esp32h2/src/lp_aon/gpio_hold0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_HOLD0")
-            .field("gpio_hold0", &format_args!("{}", self.gpio_hold0().bits()))
+            .field("gpio_hold0", &self.gpio_hold0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_HOLD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/gpio_hold1.rs b/esp32h2/src/lp_aon/gpio_hold1.rs
index 46eec62bc5..005befb609 100644
--- a/esp32h2/src/lp_aon/gpio_hold1.rs
+++ b/esp32h2/src/lp_aon/gpio_hold1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_HOLD1")
-            .field("gpio_hold1", &format_args!("{}", self.gpio_hold1().bits()))
+            .field("gpio_hold1", &self.gpio_hold1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_HOLD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/gpio_mux.rs b/esp32h2/src/lp_aon/gpio_mux.rs
index 9455ae5e1e..4977bbe7d6 100644
--- a/esp32h2/src/lp_aon/gpio_mux.rs
+++ b/esp32h2/src/lp_aon/gpio_mux.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_MUX")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_MUX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/io_mux.rs b/esp32h2/src/lp_aon/io_mux.rs
index ee30add016..fb8c31c594 100644
--- a/esp32h2/src/lp_aon/io_mux.rs
+++ b/esp32h2/src/lp_aon/io_mux.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IO_MUX")
-            .field("pull_ldo", &format_args!("{}", self.pull_ldo().bits()))
-            .field(
-                "reset_disable",
-                &format_args!("{}", self.reset_disable().bit()),
-            )
+            .field("pull_ldo", &self.pull_ldo())
+            .field("reset_disable", &self.reset_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IO_MUX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 28:30 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/jtag_sel.rs b/esp32h2/src/lp_aon/jtag_sel.rs
index cc77d37aad..c1741d1f6d 100644
--- a/esp32h2/src/lp_aon/jtag_sel.rs
+++ b/esp32h2/src/lp_aon/jtag_sel.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("JTAG_SEL")
-            .field("soft", &format_args!("{}", self.soft().bit()))
+            .field("soft", &self.soft())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<JTAG_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - If strapping_sel_jtag feature is disabled by efuse, and if neither pad_jtag or usb_jtag is disabled by efuse, this field determines which one jtag between usb_jtag and pad_jtag will be used. 1'b1(default): usb_jtag, 1'b0: pad_jtag."]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/lpbus.rs b/esp32h2/src/lp_aon/lpbus.rs
index 2e6632492b..a3ac96f6c1 100644
--- a/esp32h2/src/lp_aon/lpbus.rs
+++ b/esp32h2/src/lp_aon/lpbus.rs
@@ -72,47 +72,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPBUS")
-            .field(
-                "fast_mem_wpulse",
-                &format_args!("{}", self.fast_mem_wpulse().bits()),
-            )
-            .field(
-                "fast_mem_wa",
-                &format_args!("{}", self.fast_mem_wa().bits()),
-            )
-            .field(
-                "fast_mem_ra",
-                &format_args!("{}", self.fast_mem_ra().bits()),
-            )
-            .field(
-                "fast_mem_rm",
-                &format_args!("{}", self.fast_mem_rm().bits()),
-            )
-            .field(
-                "fast_mem_mux_fsm_idle",
-                &format_args!("{}", self.fast_mem_mux_fsm_idle().bit()),
-            )
-            .field(
-                "fast_mem_mux_sel_status",
-                &format_args!("{}", self.fast_mem_mux_sel_status().bit()),
-            )
-            .field(
-                "fast_mem_mux_sel_update",
-                &format_args!("{}", self.fast_mem_mux_sel_update().bit()),
-            )
-            .field(
-                "fast_mem_mux_sel",
-                &format_args!("{}", self.fast_mem_mux_sel().bit()),
-            )
+            .field("fast_mem_wpulse", &self.fast_mem_wpulse())
+            .field("fast_mem_wa", &self.fast_mem_wa())
+            .field("fast_mem_ra", &self.fast_mem_ra())
+            .field("fast_mem_rm", &self.fast_mem_rm())
+            .field("fast_mem_mux_fsm_idle", &self.fast_mem_mux_fsm_idle())
+            .field("fast_mem_mux_sel_status", &self.fast_mem_mux_sel_status())
+            .field("fast_mem_mux_sel_update", &self.fast_mem_mux_sel_update())
+            .field("fast_mem_mux_sel", &self.fast_mem_mux_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPBUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:18 - This field controls fast memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V operating Voltage."]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/lpcore.rs b/esp32h2/src/lp_aon/lpcore.rs
index 1530ce66d6..947b244450 100644
--- a/esp32h2/src/lp_aon/lpcore.rs
+++ b/esp32h2/src/lp_aon/lpcore.rs
@@ -28,20 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPCORE")
-            .field(
-                "etm_wakeup_flag",
-                &format_args!("{}", self.etm_wakeup_flag().bit()),
-            )
-            .field("disable", &format_args!("{}", self.disable().bit()))
+            .field("etm_wakeup_flag", &self.etm_wakeup_flag())
+            .field("disable", &self.disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPCORE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/sar_cct.rs b/esp32h2/src/lp_aon/sar_cct.rs
index 305cefc278..bd1e64f8cf 100644
--- a/esp32h2/src/lp_aon/sar_cct.rs
+++ b/esp32h2/src/lp_aon/sar_cct.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_CCT")
-            .field(
-                "sar2_pwdet_cct",
-                &format_args!("{}", self.sar2_pwdet_cct().bits()),
-            )
+            .field("sar2_pwdet_cct", &self.sar2_pwdet_cct())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_CCT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 29:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/sdio_active.rs b/esp32h2/src/lp_aon/sdio_active.rs
index c0a0c8c452..bba850a575 100644
--- a/esp32h2/src/lp_aon/sdio_active.rs
+++ b/esp32h2/src/lp_aon/sdio_active.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_ACTIVE")
-            .field(
-                "sdio_act_dnum",
-                &format_args!("{}", self.sdio_act_dnum().bits()),
-            )
+            .field("sdio_act_dnum", &self.sdio_act_dnum())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_ACTIVE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/store0.rs b/esp32h2/src/lp_aon/store0.rs
index 750dead68d..4045afdfcb 100644
--- a/esp32h2/src/lp_aon/store0.rs
+++ b/esp32h2/src/lp_aon/store0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE0")
-            .field(
-                "lp_aon_store0",
-                &format_args!("{}", self.lp_aon_store0().bits()),
-            )
+            .field("lp_aon_store0", &self.lp_aon_store0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/store1.rs b/esp32h2/src/lp_aon/store1.rs
index 2a79b3c129..81a74039fa 100644
--- a/esp32h2/src/lp_aon/store1.rs
+++ b/esp32h2/src/lp_aon/store1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE1")
-            .field(
-                "lp_aon_store1",
-                &format_args!("{}", self.lp_aon_store1().bits()),
-            )
+            .field("lp_aon_store1", &self.lp_aon_store1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/store2.rs b/esp32h2/src/lp_aon/store2.rs
index 0f6971a297..82b8006008 100644
--- a/esp32h2/src/lp_aon/store2.rs
+++ b/esp32h2/src/lp_aon/store2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE2")
-            .field(
-                "lp_aon_store2",
-                &format_args!("{}", self.lp_aon_store2().bits()),
-            )
+            .field("lp_aon_store2", &self.lp_aon_store2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/store3.rs b/esp32h2/src/lp_aon/store3.rs
index ea9df2e7cb..ebb777ec5f 100644
--- a/esp32h2/src/lp_aon/store3.rs
+++ b/esp32h2/src/lp_aon/store3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE3")
-            .field(
-                "lp_aon_store3",
-                &format_args!("{}", self.lp_aon_store3().bits()),
-            )
+            .field("lp_aon_store3", &self.lp_aon_store3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/store4.rs b/esp32h2/src/lp_aon/store4.rs
index 2021c24b50..488dee70f8 100644
--- a/esp32h2/src/lp_aon/store4.rs
+++ b/esp32h2/src/lp_aon/store4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE4")
-            .field(
-                "lp_aon_store4",
-                &format_args!("{}", self.lp_aon_store4().bits()),
-            )
+            .field("lp_aon_store4", &self.lp_aon_store4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/store5.rs b/esp32h2/src/lp_aon/store5.rs
index 273844ba76..f495df460f 100644
--- a/esp32h2/src/lp_aon/store5.rs
+++ b/esp32h2/src/lp_aon/store5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE5")
-            .field(
-                "lp_aon_store5",
-                &format_args!("{}", self.lp_aon_store5().bits()),
-            )
+            .field("lp_aon_store5", &self.lp_aon_store5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/store6.rs b/esp32h2/src/lp_aon/store6.rs
index 54446a0324..5ad9e73830 100644
--- a/esp32h2/src/lp_aon/store6.rs
+++ b/esp32h2/src/lp_aon/store6.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE6")
-            .field(
-                "lp_aon_store6",
-                &format_args!("{}", self.lp_aon_store6().bits()),
-            )
+            .field("lp_aon_store6", &self.lp_aon_store6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/store7.rs b/esp32h2/src/lp_aon/store7.rs
index b7c4164974..f00bf7f8db 100644
--- a/esp32h2/src/lp_aon/store7.rs
+++ b/esp32h2/src/lp_aon/store7.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE7")
-            .field(
-                "lp_aon_store7",
-                &format_args!("{}", self.lp_aon_store7().bits()),
-            )
+            .field("lp_aon_store7", &self.lp_aon_store7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/store8.rs b/esp32h2/src/lp_aon/store8.rs
index d35122193f..0daf1323bb 100644
--- a/esp32h2/src/lp_aon/store8.rs
+++ b/esp32h2/src/lp_aon/store8.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE8")
-            .field(
-                "lp_aon_store8",
-                &format_args!("{}", self.lp_aon_store8().bits()),
-            )
+            .field("lp_aon_store8", &self.lp_aon_store8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/store9.rs b/esp32h2/src/lp_aon/store9.rs
index 460dd4ac7a..a510c36f12 100644
--- a/esp32h2/src/lp_aon/store9.rs
+++ b/esp32h2/src/lp_aon/store9.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE9")
-            .field(
-                "lp_aon_store9",
-                &format_args!("{}", self.lp_aon_store9().bits()),
-            )
+            .field("lp_aon_store9", &self.lp_aon_store9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/sys_cfg.rs b/esp32h2/src/lp_aon/sys_cfg.rs
index ed106312db..3a5480ebfa 100644
--- a/esp32h2/src/lp_aon/sys_cfg.rs
+++ b/esp32h2/src/lp_aon/sys_cfg.rs
@@ -40,31 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYS_CFG")
-            .field(
-                "ana_fib_swd_enable",
-                &format_args!("{}", self.ana_fib_swd_enable().bit()),
-            )
-            .field(
-                "ana_fib_ck_glitch_enable",
-                &format_args!("{}", self.ana_fib_ck_glitch_enable().bit()),
-            )
-            .field(
-                "ana_fib_bod_enable",
-                &format_args!("{}", self.ana_fib_bod_enable().bit()),
-            )
-            .field(
-                "force_download_boot",
-                &format_args!("{}", self.force_download_boot().bit()),
-            )
+            .field("ana_fib_swd_enable", &self.ana_fib_swd_enable())
+            .field("ana_fib_ck_glitch_enable", &self.ana_fib_ck_glitch_enable())
+            .field("ana_fib_bod_enable", &self.ana_fib_bod_enable())
+            .field("force_download_boot", &self.force_download_boot())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYS_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_aon/usb.rs b/esp32h2/src/lp_aon/usb.rs
index 78395ff8ef..0ffe7bb3d6 100644
--- a/esp32h2/src/lp_aon/usb.rs
+++ b/esp32h2/src/lp_aon/usb.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB")
-            .field(
-                "reset_disable",
-                &format_args!("{}", self.reset_disable().bit()),
-            )
+            .field("reset_disable", &self.reset_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_apm/clock_gate.rs b/esp32h2/src/lp_apm/clock_gate.rs
index 0ea9f4e7a3..0260550609 100644
--- a/esp32h2/src/lp_apm/clock_gate.rs
+++ b/esp32h2/src/lp_apm/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_clk_en"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_apm/date.rs b/esp32h2/src/lp_apm/date.rs
index 3aab694787..6eccc68587 100644
--- a/esp32h2/src/lp_apm/date.rs
+++ b/esp32h2/src/lp_apm/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/lp_apm/func_ctrl.rs b/esp32h2/src/lp_apm/func_ctrl.rs
index 22fe19e812..bb1f6a4c17 100644
--- a/esp32h2/src/lp_apm/func_ctrl.rs
+++ b/esp32h2/src/lp_apm/func_ctrl.rs
@@ -32,19 +32,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_CTRL")
-            .field(
-                "m0_pms_func_en",
-                &format_args!("{}", self.m0_pms_func_en().bit()),
-            )
+            .field("m0_pms_func_en", &self.m0_pms_func_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "PMS M(0-0) function enable"]
     #[doc = ""]
diff --git a/esp32h2/src/lp_apm/int_en.rs b/esp32h2/src/lp_apm/int_en.rs
index de9d889823..e42f05e065 100644
--- a/esp32h2/src/lp_apm/int_en.rs
+++ b/esp32h2/src/lp_apm/int_en.rs
@@ -32,16 +32,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_EN")
-            .field("m0_apm", &format_args!("{}", self.m0_apm().bit()))
+            .field("m0_apm", &self.m0_apm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "APM M(0-0) interrupt enable"]
     #[doc = ""]
diff --git a/esp32h2/src/lp_apm/m/exception_info0.rs b/esp32h2/src/lp_apm/m/exception_info0.rs
index 1e5032ad6a..44bf2792be 100644
--- a/esp32h2/src/lp_apm/m/exception_info0.rs
+++ b/esp32h2/src/lp_apm/m/exception_info0.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXCEPTION_INFO0")
-            .field(
-                "exception_region",
-                &format_args!("{}", self.exception_region().bits()),
-            )
-            .field(
-                "exception_mode",
-                &format_args!("{}", self.exception_mode().bits()),
-            )
-            .field(
-                "exception_id",
-                &format_args!("{}", self.exception_id().bits()),
-            )
+            .field("exception_region", &self.exception_region())
+            .field("exception_mode", &self.exception_mode())
+            .field("exception_id", &self.exception_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXCEPTION_INFO0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 exception_info0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exception_info0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXCEPTION_INFO0_SPEC;
 impl crate::RegisterSpec for EXCEPTION_INFO0_SPEC {
diff --git a/esp32h2/src/lp_apm/m/exception_info1.rs b/esp32h2/src/lp_apm/m/exception_info1.rs
index 1a6977abc5..cb3b39d257 100644
--- a/esp32h2/src/lp_apm/m/exception_info1.rs
+++ b/esp32h2/src/lp_apm/m/exception_info1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXCEPTION_INFO1")
-            .field(
-                "exception_addr",
-                &format_args!("{}", self.exception_addr().bits()),
-            )
+            .field("exception_addr", &self.exception_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXCEPTION_INFO1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 exception_info1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exception_info1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXCEPTION_INFO1_SPEC;
 impl crate::RegisterSpec for EXCEPTION_INFO1_SPEC {
diff --git a/esp32h2/src/lp_apm/m/status.rs b/esp32h2/src/lp_apm/m/status.rs
index 6a5c666bbf..3e275a91ca 100644
--- a/esp32h2/src/lp_apm/m/status.rs
+++ b/esp32h2/src/lp_apm/m/status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field(
-                "exception_status",
-                &format_args!("{}", self.exception_status().bits()),
-            )
+            .field("exception_status", &self.exception_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "M0 status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32h2/src/lp_apm/region/addr_end.rs b/esp32h2/src/lp_apm/region/addr_end.rs
index 8940485f11..db15e1b66a 100644
--- a/esp32h2/src/lp_apm/region/addr_end.rs
+++ b/esp32h2/src/lp_apm/region/addr_end.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR_END")
-            .field("addr_end", &format_args!("{}", self.addr_end().bits()))
+            .field("addr_end", &self.addr_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_END_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - End address of region0"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_apm/region/addr_start.rs b/esp32h2/src/lp_apm/region/addr_start.rs
index 15654e8830..21d743f5e2 100644
--- a/esp32h2/src/lp_apm/region/addr_start.rs
+++ b/esp32h2/src/lp_apm/region/addr_start.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR_START")
-            .field("addr_start", &format_args!("{}", self.addr_start().bits()))
+            .field("addr_start", &self.addr_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_START_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Start address of region0"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_apm/region/pms_attr.rs b/esp32h2/src/lp_apm/region/pms_attr.rs
index 30b2486d8c..a929b05fa9 100644
--- a/esp32h2/src/lp_apm/region/pms_attr.rs
+++ b/esp32h2/src/lp_apm/region/pms_attr.rs
@@ -110,24 +110,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMS_ATTR")
-            .field("r0_pms_x", &format_args!("{}", self.r0_pms_x().bit()))
-            .field("r1_pms_x", &format_args!("{}", self.r1_pms_x().bit()))
-            .field("r2_pms_x", &format_args!("{}", self.r2_pms_x().bit()))
-            .field("r0_pms_w", &format_args!("{}", self.r0_pms_w().bit()))
-            .field("r1_pms_w", &format_args!("{}", self.r1_pms_w().bit()))
-            .field("r2_pms_w", &format_args!("{}", self.r2_pms_w().bit()))
-            .field("r0_pms_r", &format_args!("{}", self.r0_pms_r().bit()))
-            .field("r1_pms_r", &format_args!("{}", self.r1_pms_r().bit()))
-            .field("r2_pms_r", &format_args!("{}", self.r2_pms_r().bit()))
+            .field("r0_pms_x", &self.r0_pms_x())
+            .field("r1_pms_x", &self.r1_pms_x())
+            .field("r2_pms_x", &self.r2_pms_x())
+            .field("r0_pms_w", &self.r0_pms_w())
+            .field("r1_pms_w", &self.r1_pms_w())
+            .field("r2_pms_w", &self.r2_pms_w())
+            .field("r0_pms_r", &self.r0_pms_r())
+            .field("r1_pms_r", &self.r1_pms_r())
+            .field("r2_pms_r", &self.r2_pms_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMS_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Region execute authority in REE_MODE(0-2)"]
     #[doc = ""]
diff --git a/esp32h2/src/lp_apm/region_filter_en.rs b/esp32h2/src/lp_apm/region_filter_en.rs
index fdb68f35fc..658fe78944 100644
--- a/esp32h2/src/lp_apm/region_filter_en.rs
+++ b/esp32h2/src/lp_apm/region_filter_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGION_FILTER_EN")
-            .field(
-                "region_filter_en",
-                &format_args!("{}", self.region_filter_en().bits()),
-            )
+            .field("region_filter_en", &self.region_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGION_FILTER_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Region filter enable"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_clkrst/clk_to_hp.rs b/esp32h2/src/lp_clkrst/clk_to_hp.rs
index 901a6280ab..aa35ff4c00 100644
--- a/esp32h2/src/lp_clkrst/clk_to_hp.rs
+++ b/esp32h2/src/lp_clkrst/clk_to_hp.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_TO_HP")
-            .field(
-                "icg_hp_xtal32k",
-                &format_args!("{}", self.icg_hp_xtal32k().bit()),
-            )
-            .field("icg_hp_sosc", &format_args!("{}", self.icg_hp_sosc().bit()))
-            .field(
-                "icg_hp_osc32k",
-                &format_args!("{}", self.icg_hp_osc32k().bit()),
-            )
-            .field("icg_hp_fosc", &format_args!("{}", self.icg_hp_fosc().bit()))
+            .field("icg_hp_xtal32k", &self.icg_hp_xtal32k())
+            .field("icg_hp_sosc", &self.icg_hp_sosc())
+            .field("icg_hp_osc32k", &self.icg_hp_osc32k())
+            .field("icg_hp_fosc", &self.icg_hp_fosc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_TO_HP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_clkrst/cpu_reset.rs b/esp32h2/src/lp_clkrst/cpu_reset.rs
index 5975cda7af..c5e74019c0 100644
--- a/esp32h2/src/lp_clkrst/cpu_reset.rs
+++ b/esp32h2/src/lp_clkrst/cpu_reset.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_RESET")
-            .field(
-                "rtc_wdt_cpu_reset_length",
-                &format_args!("{}", self.rtc_wdt_cpu_reset_length().bits()),
-            )
-            .field(
-                "rtc_wdt_cpu_reset_en",
-                &format_args!("{}", self.rtc_wdt_cpu_reset_en().bit()),
-            )
-            .field(
-                "cpu_stall_wait",
-                &format_args!("{}", self.cpu_stall_wait().bits()),
-            )
-            .field(
-                "cpu_stall_en",
-                &format_args!("{}", self.cpu_stall_en().bit()),
-            )
+            .field("rtc_wdt_cpu_reset_length", &self.rtc_wdt_cpu_reset_length())
+            .field("rtc_wdt_cpu_reset_en", &self.rtc_wdt_cpu_reset_en())
+            .field("cpu_stall_wait", &self.cpu_stall_wait())
+            .field("cpu_stall_en", &self.cpu_stall_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_RESET_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:24 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_clkrst/date.rs b/esp32h2/src/lp_clkrst/date.rs
index 7fc29639ea..a0d913faf3 100644
--- a/esp32h2/src/lp_clkrst/date.rs
+++ b/esp32h2/src/lp_clkrst/date.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "clkrst_date",
-                &format_args!("{}", self.clkrst_date().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clkrst_date", &self.clkrst_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_clkrst/fosc_cntl.rs b/esp32h2/src/lp_clkrst/fosc_cntl.rs
index cac5f913c6..4e60d19d6b 100644
--- a/esp32h2/src/lp_clkrst/fosc_cntl.rs
+++ b/esp32h2/src/lp_clkrst/fosc_cntl.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FOSC_CNTL")
-            .field("fosc_dfreq", &format_args!("{}", self.fosc_dfreq().bits()))
+            .field("fosc_dfreq", &self.fosc_dfreq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FOSC_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_clkrst/lp_clk_conf.rs b/esp32h2/src/lp_clkrst/lp_clk_conf.rs
index 48d68dcf62..31cbfbd129 100644
--- a/esp32h2/src/lp_clkrst/lp_clk_conf.rs
+++ b/esp32h2/src/lp_clkrst/lp_clk_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CLK_CONF")
-            .field(
-                "slow_clk_sel",
-                &format_args!("{}", self.slow_clk_sel().bits()),
-            )
-            .field(
-                "fast_clk_sel",
-                &format_args!("{}", self.fast_clk_sel().bits()),
-            )
-            .field(
-                "lp_peri_div_num",
-                &format_args!("{}", self.lp_peri_div_num().bits()),
-            )
+            .field("slow_clk_sel", &self.slow_clk_sel())
+            .field("fast_clk_sel", &self.fast_clk_sel())
+            .field("lp_peri_div_num", &self.lp_peri_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_clkrst/lp_clk_en.rs b/esp32h2/src/lp_clkrst/lp_clk_en.rs
index 316fc21b67..ec70392c24 100644
--- a/esp32h2/src/lp_clkrst/lp_clk_en.rs
+++ b/esp32h2/src/lp_clkrst/lp_clk_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CLK_EN")
-            .field(
-                "fast_ori_gate",
-                &format_args!("{}", self.fast_ori_gate().bit()),
-            )
+            .field("fast_ori_gate", &self.fast_ori_gate())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_clkrst/lp_clk_po_en.rs b/esp32h2/src/lp_clkrst/lp_clk_po_en.rs
index 287da0bf37..118ba1f140 100644
--- a/esp32h2/src/lp_clkrst/lp_clk_po_en.rs
+++ b/esp32h2/src/lp_clkrst/lp_clk_po_en.rs
@@ -107,35 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CLK_PO_EN")
-            .field(
-                "aon_slow_oen",
-                &format_args!("{}", self.aon_slow_oen().bit()),
-            )
-            .field(
-                "aon_fast_oen",
-                &format_args!("{}", self.aon_fast_oen().bit()),
-            )
-            .field("sosc_oen", &format_args!("{}", self.sosc_oen().bit()))
-            .field("fosc_oen", &format_args!("{}", self.fosc_oen().bit()))
-            .field("osc32k_oen", &format_args!("{}", self.osc32k_oen().bit()))
-            .field("xtal32k_oen", &format_args!("{}", self.xtal32k_oen().bit()))
-            .field(
-                "core_efuse_oen",
-                &format_args!("{}", self.core_efuse_oen().bit()),
-            )
-            .field("slow_oen", &format_args!("{}", self.slow_oen().bit()))
-            .field("fast_oen", &format_args!("{}", self.fast_oen().bit()))
-            .field("rng_oen", &format_args!("{}", self.rng_oen().bit()))
-            .field("lpbus_oen", &format_args!("{}", self.lpbus_oen().bit()))
+            .field("aon_slow_oen", &self.aon_slow_oen())
+            .field("aon_fast_oen", &self.aon_fast_oen())
+            .field("sosc_oen", &self.sosc_oen())
+            .field("fosc_oen", &self.fosc_oen())
+            .field("osc32k_oen", &self.osc32k_oen())
+            .field("xtal32k_oen", &self.xtal32k_oen())
+            .field("core_efuse_oen", &self.core_efuse_oen())
+            .field("slow_oen", &self.slow_oen())
+            .field("fast_oen", &self.fast_oen())
+            .field("rng_oen", &self.rng_oen())
+            .field("lpbus_oen", &self.lpbus_oen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CLK_PO_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_clkrst/lp_rst_en.rs b/esp32h2/src/lp_clkrst/lp_rst_en.rs
index 9147d2f88c..372756979e 100644
--- a/esp32h2/src/lp_clkrst/lp_rst_en.rs
+++ b/esp32h2/src/lp_clkrst/lp_rst_en.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_RST_EN")
-            .field(
-                "aon_efuse_core_reset_en",
-                &format_args!("{}", self.aon_efuse_core_reset_en().bit()),
-            )
-            .field(
-                "lp_timer_reset_en",
-                &format_args!("{}", self.lp_timer_reset_en().bit()),
-            )
-            .field(
-                "wdt_reset_en",
-                &format_args!("{}", self.wdt_reset_en().bit()),
-            )
-            .field(
-                "ana_peri_reset_en",
-                &format_args!("{}", self.ana_peri_reset_en().bit()),
-            )
+            .field("aon_efuse_core_reset_en", &self.aon_efuse_core_reset_en())
+            .field("lp_timer_reset_en", &self.lp_timer_reset_en())
+            .field("wdt_reset_en", &self.wdt_reset_en())
+            .field("ana_peri_reset_en", &self.ana_peri_reset_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_RST_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_clkrst/lpmem_force.rs b/esp32h2/src/lp_clkrst/lpmem_force.rs
index 95a3efd9b8..c164724bb3 100644
--- a/esp32h2/src/lp_clkrst/lpmem_force.rs
+++ b/esp32h2/src/lp_clkrst/lpmem_force.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPMEM_FORCE")
-            .field(
-                "lpmem_clk_force_on",
-                &format_args!("{}", self.lpmem_clk_force_on().bit()),
-            )
+            .field("lpmem_clk_force_on", &self.lpmem_clk_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPMEM_FORCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_clkrst/lpperi.rs b/esp32h2/src/lp_clkrst/lpperi.rs
index 8df2247b9e..0dfe09b975 100644
--- a/esp32h2/src/lp_clkrst/lpperi.rs
+++ b/esp32h2/src/lp_clkrst/lpperi.rs
@@ -80,44 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPPERI")
-            .field(
-                "lp_bletimer_div_num",
-                &format_args!("{}", self.lp_bletimer_div_num().bits()),
-            )
-            .field(
-                "lp_bletimer_32k_sel",
-                &format_args!("{}", self.lp_bletimer_32k_sel().bits()),
-            )
-            .field(
-                "lp_sel_osc_slow",
-                &format_args!("{}", self.lp_sel_osc_slow().bit()),
-            )
-            .field(
-                "lp_sel_osc_fast",
-                &format_args!("{}", self.lp_sel_osc_fast().bit()),
-            )
-            .field("lp_sel_xtal", &format_args!("{}", self.lp_sel_xtal().bit()))
-            .field(
-                "lp_sel_xtal32k",
-                &format_args!("{}", self.lp_sel_xtal32k().bit()),
-            )
-            .field(
-                "lp_i2c_clk_sel",
-                &format_args!("{}", self.lp_i2c_clk_sel().bit()),
-            )
-            .field(
-                "lp_uart_clk_sel",
-                &format_args!("{}", self.lp_uart_clk_sel().bit()),
-            )
+            .field("lp_bletimer_div_num", &self.lp_bletimer_div_num())
+            .field("lp_bletimer_32k_sel", &self.lp_bletimer_32k_sel())
+            .field("lp_sel_osc_slow", &self.lp_sel_osc_slow())
+            .field("lp_sel_osc_fast", &self.lp_sel_osc_fast())
+            .field("lp_sel_xtal", &self.lp_sel_xtal())
+            .field("lp_sel_xtal32k", &self.lp_sel_xtal32k())
+            .field("lp_i2c_clk_sel", &self.lp_i2c_clk_sel())
+            .field("lp_uart_clk_sel", &self.lp_uart_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPPERI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 12:23 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_clkrst/rc32k_cntl.rs b/esp32h2/src/lp_clkrst/rc32k_cntl.rs
index 4deb621f69..273908d3e0 100644
--- a/esp32h2/src/lp_clkrst/rc32k_cntl.rs
+++ b/esp32h2/src/lp_clkrst/rc32k_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RC32K_CNTL")
-            .field(
-                "rc32k_dfreq",
-                &format_args!("{}", self.rc32k_dfreq().bits()),
-            )
+            .field("rc32k_dfreq", &self.rc32k_dfreq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RC32K_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_clkrst/reset_cause.rs b/esp32h2/src/lp_clkrst/reset_cause.rs
index 8e7da12acf..41cd6b06ce 100644
--- a/esp32h2/src/lp_clkrst/reset_cause.rs
+++ b/esp32h2/src/lp_clkrst/reset_cause.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET_CAUSE")
-            .field(
-                "reset_cause",
-                &format_args!("{}", self.reset_cause().bits()),
-            )
-            .field(
-                "core0_reset_flag",
-                &format_args!("{}", self.core0_reset_flag().bit()),
-            )
+            .field("reset_cause", &self.reset_cause())
+            .field("core0_reset_flag", &self.core0_reset_flag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET_CAUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 29 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_clkrst/xtal32k.rs b/esp32h2/src/lp_clkrst/xtal32k.rs
index 0c231690c7..21734fb527 100644
--- a/esp32h2/src/lp_clkrst/xtal32k.rs
+++ b/esp32h2/src/lp_clkrst/xtal32k.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL32K")
-            .field(
-                "dres_xtal32k",
-                &format_args!("{}", self.dres_xtal32k().bits()),
-            )
-            .field(
-                "dgm_xtal32k",
-                &format_args!("{}", self.dgm_xtal32k().bits()),
-            )
-            .field(
-                "dbuf_xtal32k",
-                &format_args!("{}", self.dbuf_xtal32k().bit()),
-            )
-            .field(
-                "dac_xtal32k",
-                &format_args!("{}", self.dac_xtal32k().bits()),
-            )
+            .field("dres_xtal32k", &self.dres_xtal32k())
+            .field("dgm_xtal32k", &self.dgm_xtal32k())
+            .field("dbuf_xtal32k", &self.dbuf_xtal32k())
+            .field("dac_xtal32k", &self.dac_xtal32k())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL32K_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:24 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_peri/bus_timeout.rs b/esp32h2/src/lp_peri/bus_timeout.rs
index c9162357b7..559e19f4c6 100644
--- a/esp32h2/src/lp_peri/bus_timeout.rs
+++ b/esp32h2/src/lp_peri/bus_timeout.rs
@@ -28,23 +28,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMEOUT")
-            .field(
-                "lp_peri_timeout_thres",
-                &format_args!("{}", self.lp_peri_timeout_thres().bits()),
-            )
+            .field("lp_peri_timeout_thres", &self.lp_peri_timeout_thres())
             .field(
                 "lp_peri_timeout_protect_en",
-                &format_args!("{}", self.lp_peri_timeout_protect_en().bit()),
+                &self.lp_peri_timeout_protect_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMEOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 14:29 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_peri/bus_timeout_addr.rs b/esp32h2/src/lp_peri/bus_timeout_addr.rs
index f90baac504..6527db51bb 100644
--- a/esp32h2/src/lp_peri/bus_timeout_addr.rs
+++ b/esp32h2/src/lp_peri/bus_timeout_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMEOUT_ADDR")
-            .field(
-                "lp_peri_timeout_addr",
-                &format_args!("{}", self.lp_peri_timeout_addr().bits()),
-            )
+            .field("lp_peri_timeout_addr", &self.lp_peri_timeout_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMEOUT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_timeout_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUS_TIMEOUT_ADDR_SPEC;
 impl crate::RegisterSpec for BUS_TIMEOUT_ADDR_SPEC {
diff --git a/esp32h2/src/lp_peri/bus_timeout_uid.rs b/esp32h2/src/lp_peri/bus_timeout_uid.rs
index d8620b1d01..43079dcad0 100644
--- a/esp32h2/src/lp_peri/bus_timeout_uid.rs
+++ b/esp32h2/src/lp_peri/bus_timeout_uid.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMEOUT_UID")
-            .field(
-                "lp_peri_timeout_uid",
-                &format_args!("{}", self.lp_peri_timeout_uid().bits()),
-            )
+            .field("lp_peri_timeout_uid", &self.lp_peri_timeout_uid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMEOUT_UID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_timeout_uid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUS_TIMEOUT_UID_SPEC;
 impl crate::RegisterSpec for BUS_TIMEOUT_UID_SPEC {
diff --git a/esp32h2/src/lp_peri/clk_en.rs b/esp32h2/src/lp_peri/clk_en.rs
index afac9ed9a5..f8ebc598c9 100644
--- a/esp32h2/src/lp_peri/clk_en.rs
+++ b/esp32h2/src/lp_peri/clk_en.rs
@@ -80,38 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EN")
-            .field("rng_ck_en", &format_args!("{}", self.rng_ck_en().bit()))
-            .field(
-                "otp_dbg_ck_en",
-                &format_args!("{}", self.otp_dbg_ck_en().bit()),
-            )
-            .field(
-                "lp_uart_ck_en",
-                &format_args!("{}", self.lp_uart_ck_en().bit()),
-            )
-            .field("lp_io_ck_en", &format_args!("{}", self.lp_io_ck_en().bit()))
-            .field(
-                "lp_ext_i2c_ck_en",
-                &format_args!("{}", self.lp_ext_i2c_ck_en().bit()),
-            )
-            .field(
-                "lp_ana_i2c_ck_en",
-                &format_args!("{}", self.lp_ana_i2c_ck_en().bit()),
-            )
-            .field("efuse_ck_en", &format_args!("{}", self.efuse_ck_en().bit()))
-            .field(
-                "lp_cpu_ck_en",
-                &format_args!("{}", self.lp_cpu_ck_en().bit()),
-            )
+            .field("rng_ck_en", &self.rng_ck_en())
+            .field("otp_dbg_ck_en", &self.otp_dbg_ck_en())
+            .field("lp_uart_ck_en", &self.lp_uart_ck_en())
+            .field("lp_io_ck_en", &self.lp_io_ck_en())
+            .field("lp_ext_i2c_ck_en", &self.lp_ext_i2c_ck_en())
+            .field("lp_ana_i2c_ck_en", &self.lp_ana_i2c_ck_en())
+            .field("efuse_ck_en", &self.efuse_ck_en())
+            .field("lp_cpu_ck_en", &self.lp_cpu_ck_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_peri/cpu.rs b/esp32h2/src/lp_peri/cpu.rs
index bcb33042d9..ea8c30e62d 100644
--- a/esp32h2/src/lp_peri/cpu.rs
+++ b/esp32h2/src/lp_peri/cpu.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU")
-            .field(
-                "lpcore_dbgm_unavaliable",
-                &format_args!("{}", self.lpcore_dbgm_unavaliable().bit()),
-            )
+            .field("lpcore_dbgm_unavaliable", &self.lpcore_dbgm_unavaliable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_peri/date.rs b/esp32h2/src/lp_peri/date.rs
index 6cd7bea0a5..9e433a72d2 100644
--- a/esp32h2/src/lp_peri/date.rs
+++ b/esp32h2/src/lp_peri/date.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "lpperi_date",
-                &format_args!("{}", self.lpperi_date().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("lpperi_date", &self.lpperi_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_peri/debug_sel0.rs b/esp32h2/src/lp_peri/debug_sel0.rs
index 6605b61c23..886fb6980b 100644
--- a/esp32h2/src/lp_peri/debug_sel0.rs
+++ b/esp32h2/src/lp_peri/debug_sel0.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEBUG_SEL0")
-            .field("debug_sel0", &format_args!("{}", self.debug_sel0().bits()))
-            .field("debug_sel1", &format_args!("{}", self.debug_sel1().bits()))
-            .field("debug_sel2", &format_args!("{}", self.debug_sel2().bits()))
-            .field("debug_sel3", &format_args!("{}", self.debug_sel3().bits()))
+            .field("debug_sel0", &self.debug_sel0())
+            .field("debug_sel1", &self.debug_sel1())
+            .field("debug_sel2", &self.debug_sel2())
+            .field("debug_sel3", &self.debug_sel3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBUG_SEL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - need des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_peri/debug_sel1.rs b/esp32h2/src/lp_peri/debug_sel1.rs
index d68e57d9f3..135791b3e0 100644
--- a/esp32h2/src/lp_peri/debug_sel1.rs
+++ b/esp32h2/src/lp_peri/debug_sel1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEBUG_SEL1")
-            .field("debug_sel4", &format_args!("{}", self.debug_sel4().bits()))
+            .field("debug_sel4", &self.debug_sel4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBUG_SEL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - need des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_peri/interrupt_source.rs b/esp32h2/src/lp_peri/interrupt_source.rs
index 3a58e713a5..079ad23d59 100644
--- a/esp32h2/src/lp_peri/interrupt_source.rs
+++ b/esp32h2/src/lp_peri/interrupt_source.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT_SOURCE")
-            .field(
-                "lp_interrupt_source",
-                &format_args!("{}", self.lp_interrupt_source().bits()),
-            )
+            .field("lp_interrupt_source", &self.lp_interrupt_source())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_SOURCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt_source::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERRUPT_SOURCE_SPEC;
 impl crate::RegisterSpec for INTERRUPT_SOURCE_SPEC {
diff --git a/esp32h2/src/lp_peri/mem_ctrl.rs b/esp32h2/src/lp_peri/mem_ctrl.rs
index 19f827781a..32a31f41d6 100644
--- a/esp32h2/src/lp_peri/mem_ctrl.rs
+++ b/esp32h2/src/lp_peri/mem_ctrl.rs
@@ -46,31 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CTRL")
-            .field(
-                "uart_wakeup_flag",
-                &format_args!("{}", self.uart_wakeup_flag().bit()),
-            )
-            .field(
-                "uart_wakeup_en",
-                &format_args!("{}", self.uart_wakeup_en().bit()),
-            )
-            .field(
-                "uart_mem_force_pd",
-                &format_args!("{}", self.uart_mem_force_pd().bit()),
-            )
-            .field(
-                "uart_mem_force_pu",
-                &format_args!("{}", self.uart_mem_force_pu().bit()),
-            )
+            .field("uart_wakeup_flag", &self.uart_wakeup_flag())
+            .field("uart_wakeup_en", &self.uart_wakeup_en())
+            .field("uart_mem_force_pd", &self.uart_mem_force_pd())
+            .field("uart_mem_force_pu", &self.uart_mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_peri/reset_en.rs b/esp32h2/src/lp_peri/reset_en.rs
index 13fd67de7a..54971069a2 100644
--- a/esp32h2/src/lp_peri/reset_en.rs
+++ b/esp32h2/src/lp_peri/reset_en.rs
@@ -75,43 +75,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET_EN")
-            .field(
-                "lp_ble_timer_reset_en",
-                &format_args!("{}", self.lp_ble_timer_reset_en().bit()),
-            )
-            .field(
-                "otp_dbg_reset_en",
-                &format_args!("{}", self.otp_dbg_reset_en().bit()),
-            )
-            .field(
-                "lp_uart_reset_en",
-                &format_args!("{}", self.lp_uart_reset_en().bit()),
-            )
-            .field(
-                "lp_io_reset_en",
-                &format_args!("{}", self.lp_io_reset_en().bit()),
-            )
-            .field(
-                "lp_ext_i2c_reset_en",
-                &format_args!("{}", self.lp_ext_i2c_reset_en().bit()),
-            )
-            .field(
-                "lp_ana_i2c_reset_en",
-                &format_args!("{}", self.lp_ana_i2c_reset_en().bit()),
-            )
-            .field(
-                "efuse_reset_en",
-                &format_args!("{}", self.efuse_reset_en().bit()),
-            )
+            .field("lp_ble_timer_reset_en", &self.lp_ble_timer_reset_en())
+            .field("otp_dbg_reset_en", &self.otp_dbg_reset_en())
+            .field("lp_uart_reset_en", &self.lp_uart_reset_en())
+            .field("lp_io_reset_en", &self.lp_io_reset_en())
+            .field("lp_ext_i2c_reset_en", &self.lp_ext_i2c_reset_en())
+            .field("lp_ana_i2c_reset_en", &self.lp_ana_i2c_reset_en())
+            .field("efuse_reset_en", &self.efuse_reset_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 23 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_peri/rng_data.rs b/esp32h2/src/lp_peri/rng_data.rs
index 713145ebb6..13f1db3a76 100644
--- a/esp32h2/src/lp_peri/rng_data.rs
+++ b/esp32h2/src/lp_peri/rng_data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RNG_DATA")
-            .field("rnd_data", &format_args!("{}", self.rnd_data().bits()))
+            .field("rnd_data", &self.rnd_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RNG_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RNG_DATA_SPEC;
 impl crate::RegisterSpec for RNG_DATA_SPEC {
diff --git a/esp32h2/src/lp_timer/date.rs b/esp32h2/src/lp_timer/date.rs
index d47a89ee4b..e9890af6e1 100644
--- a/esp32h2/src/lp_timer/date.rs
+++ b/esp32h2/src/lp_timer/date.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("date", &self.date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_timer/int_ena.rs b/esp32h2/src/lp_timer/int_ena.rs
index a172892f46..6f4c762b5a 100644
--- a/esp32h2/src/lp_timer/int_ena.rs
+++ b/esp32h2/src/lp_timer/int_ena.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "overflow_ena",
-                &format_args!("{}", self.overflow_ena().bit()),
-            )
-            .field(
-                "soc_wakeup_int_ena",
-                &format_args!("{}", self.soc_wakeup_int_ena().bit()),
-            )
+            .field("overflow_ena", &self.overflow_ena())
+            .field("soc_wakeup_int_ena", &self.soc_wakeup_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_timer/int_raw.rs b/esp32h2/src/lp_timer/int_raw.rs
index 8255f8e5da..777b91090a 100644
--- a/esp32h2/src/lp_timer/int_raw.rs
+++ b/esp32h2/src/lp_timer/int_raw.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "overflow_raw",
-                &format_args!("{}", self.overflow_raw().bit()),
-            )
-            .field(
-                "soc_wakeup_int_raw",
-                &format_args!("{}", self.soc_wakeup_int_raw().bit()),
-            )
+            .field("overflow_raw", &self.overflow_raw())
+            .field("soc_wakeup_int_raw", &self.soc_wakeup_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_timer/int_st.rs b/esp32h2/src/lp_timer/int_st.rs
index fc436c8715..a67f0223d8 100644
--- a/esp32h2/src/lp_timer/int_st.rs
+++ b/esp32h2/src/lp_timer/int_st.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("overflow_st", &format_args!("{}", self.overflow_st().bit()))
-            .field(
-                "soc_wakeup_int_st",
-                &format_args!("{}", self.soc_wakeup_int_st().bit()),
-            )
+            .field("overflow_st", &self.overflow_st())
+            .field("soc_wakeup_int_st", &self.soc_wakeup_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/lp_timer/main_buf0_high.rs b/esp32h2/src/lp_timer/main_buf0_high.rs
index 7ec6b260aa..4545617b27 100644
--- a/esp32h2/src/lp_timer/main_buf0_high.rs
+++ b/esp32h2/src/lp_timer/main_buf0_high.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF0_HIGH")
-            .field(
-                "main_timer_buf0_high",
-                &format_args!("{}", self.main_timer_buf0_high().bits()),
-            )
+            .field("main_timer_buf0_high", &self.main_timer_buf0_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF0_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf0_high::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF0_HIGH_SPEC;
 impl crate::RegisterSpec for MAIN_BUF0_HIGH_SPEC {
diff --git a/esp32h2/src/lp_timer/main_buf0_low.rs b/esp32h2/src/lp_timer/main_buf0_low.rs
index b3e2efd010..9c176ef6e3 100644
--- a/esp32h2/src/lp_timer/main_buf0_low.rs
+++ b/esp32h2/src/lp_timer/main_buf0_low.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF0_LOW")
-            .field(
-                "main_timer_buf0_low",
-                &format_args!("{}", self.main_timer_buf0_low().bits()),
-            )
+            .field("main_timer_buf0_low", &self.main_timer_buf0_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF0_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf0_low::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF0_LOW_SPEC;
 impl crate::RegisterSpec for MAIN_BUF0_LOW_SPEC {
diff --git a/esp32h2/src/lp_timer/main_buf1_high.rs b/esp32h2/src/lp_timer/main_buf1_high.rs
index 343bec706f..3fd0b05256 100644
--- a/esp32h2/src/lp_timer/main_buf1_high.rs
+++ b/esp32h2/src/lp_timer/main_buf1_high.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF1_HIGH")
-            .field(
-                "main_timer_buf1_high",
-                &format_args!("{}", self.main_timer_buf1_high().bits()),
-            )
+            .field("main_timer_buf1_high", &self.main_timer_buf1_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF1_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf1_high::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF1_HIGH_SPEC;
 impl crate::RegisterSpec for MAIN_BUF1_HIGH_SPEC {
diff --git a/esp32h2/src/lp_timer/main_buf1_low.rs b/esp32h2/src/lp_timer/main_buf1_low.rs
index e9cb954df6..020cfc0659 100644
--- a/esp32h2/src/lp_timer/main_buf1_low.rs
+++ b/esp32h2/src/lp_timer/main_buf1_low.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF1_LOW")
-            .field(
-                "main_timer_buf1_low",
-                &format_args!("{}", self.main_timer_buf1_low().bits()),
-            )
+            .field("main_timer_buf1_low", &self.main_timer_buf1_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF1_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf1_low::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF1_LOW_SPEC;
 impl crate::RegisterSpec for MAIN_BUF1_LOW_SPEC {
diff --git a/esp32h2/src/lp_timer/tar0_high.rs b/esp32h2/src/lp_timer/tar0_high.rs
index ba43f1ec62..abf6de0468 100644
--- a/esp32h2/src/lp_timer/tar0_high.rs
+++ b/esp32h2/src/lp_timer/tar0_high.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TAR0_HIGH")
-            .field(
-                "main_timer_tar_high0",
-                &format_args!("{}", self.main_timer_tar_high0().bits()),
-            )
+            .field("main_timer_tar_high0", &self.main_timer_tar_high0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TAR0_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_timer/tar0_low.rs b/esp32h2/src/lp_timer/tar0_low.rs
index 131d1c04d8..fe2273147d 100644
--- a/esp32h2/src/lp_timer/tar0_low.rs
+++ b/esp32h2/src/lp_timer/tar0_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TAR0_LOW")
-            .field(
-                "main_timer_tar_low0",
-                &format_args!("{}", self.main_timer_tar_low0().bits()),
-            )
+            .field("main_timer_tar_low0", &self.main_timer_tar_low0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TAR0_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_timer/update.rs b/esp32h2/src/lp_timer/update.rs
index 9f49d41d18..b0cb0a2d30 100644
--- a/esp32h2/src/lp_timer/update.rs
+++ b/esp32h2/src/lp_timer/update.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE")
-            .field(
-                "main_timer_xtal_off",
-                &format_args!("{}", self.main_timer_xtal_off().bit()),
-            )
-            .field(
-                "main_timer_sys_stall",
-                &format_args!("{}", self.main_timer_sys_stall().bit()),
-            )
-            .field(
-                "main_timer_sys_rst",
-                &format_args!("{}", self.main_timer_sys_rst().bit()),
-            )
+            .field("main_timer_xtal_off", &self.main_timer_xtal_off())
+            .field("main_timer_sys_stall", &self.main_timer_sys_stall())
+            .field("main_timer_sys_rst", &self.main_timer_sys_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_wdt/config1.rs b/esp32h2/src/lp_wdt/config1.rs
index 5718bd36a7..cc20f95485 100644
--- a/esp32h2/src/lp_wdt/config1.rs
+++ b/esp32h2/src/lp_wdt/config1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG1")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_wdt/config2.rs b/esp32h2/src/lp_wdt/config2.rs
index a1ed774a2e..1208d49421 100644
--- a/esp32h2/src/lp_wdt/config2.rs
+++ b/esp32h2/src/lp_wdt/config2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG2")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_wdt/config3.rs b/esp32h2/src/lp_wdt/config3.rs
index 51d57fe8f9..41322e4dc9 100644
--- a/esp32h2/src/lp_wdt/config3.rs
+++ b/esp32h2/src/lp_wdt/config3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG3")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_wdt/config4.rs b/esp32h2/src/lp_wdt/config4.rs
index f0857186f5..efe8bb1a07 100644
--- a/esp32h2/src/lp_wdt/config4.rs
+++ b/esp32h2/src/lp_wdt/config4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG4")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_wdt/config5.rs b/esp32h2/src/lp_wdt/config5.rs
index 8288f8e268..b9aaee50d9 100644
--- a/esp32h2/src/lp_wdt/config5.rs
+++ b/esp32h2/src/lp_wdt/config5.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG5")
-            .field(
-                "chip_reset_target",
-                &format_args!("{}", self.chip_reset_target().bits()),
-            )
-            .field(
-                "chip_reset_en",
-                &format_args!("{}", self.chip_reset_en().bit()),
-            )
-            .field(
-                "chip_reset_key",
-                &format_args!("{}", self.chip_reset_key().bits()),
-            )
+            .field("chip_reset_target", &self.chip_reset_target())
+            .field("chip_reset_en", &self.chip_reset_en())
+            .field("chip_reset_key", &self.chip_reset_key())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_wdt/date.rs b/esp32h2/src/lp_wdt/date.rs
index ad999360f1..c4762f886a 100644
--- a/esp32h2/src/lp_wdt/date.rs
+++ b/esp32h2/src/lp_wdt/date.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "lp_wdt_date",
-                &format_args!("{}", self.lp_wdt_date().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("lp_wdt_date", &self.lp_wdt_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_wdt/int_ena.rs b/esp32h2/src/lp_wdt/int_ena.rs
index fb695587d4..e9dcd83f54 100644
--- a/esp32h2/src/lp_wdt/int_ena.rs
+++ b/esp32h2/src/lp_wdt/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("super_wdt", &format_args!("{}", self.super_wdt().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("super_wdt", &self.super_wdt())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_wdt/int_raw.rs b/esp32h2/src/lp_wdt/int_raw.rs
index c4f12e1d5e..fd7e3c5567 100644
--- a/esp32h2/src/lp_wdt/int_raw.rs
+++ b/esp32h2/src/lp_wdt/int_raw.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("super_wdt", &format_args!("{}", self.super_wdt().bit()))
-            .field("lp_wdt", &format_args!("{}", self.lp_wdt().bit()))
+            .field("super_wdt", &self.super_wdt())
+            .field("lp_wdt", &self.lp_wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_wdt/int_st.rs b/esp32h2/src/lp_wdt/int_st.rs
index 760d8cfb84..1f265e1b3d 100644
--- a/esp32h2/src/lp_wdt/int_st.rs
+++ b/esp32h2/src/lp_wdt/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("super_wdt", &format_args!("{}", self.super_wdt().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("super_wdt", &self.super_wdt())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/lp_wdt/swd_conf.rs b/esp32h2/src/lp_wdt/swd_conf.rs
index 4b4a276a30..233972cea9 100644
--- a/esp32h2/src/lp_wdt/swd_conf.rs
+++ b/esp32h2/src/lp_wdt/swd_conf.rs
@@ -46,28 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_CONF")
-            .field(
-                "swd_reset_flag",
-                &format_args!("{}", self.swd_reset_flag().bit()),
-            )
-            .field(
-                "swd_auto_feed_en",
-                &format_args!("{}", self.swd_auto_feed_en().bit()),
-            )
-            .field(
-                "swd_signal_width",
-                &format_args!("{}", self.swd_signal_width().bits()),
-            )
-            .field("swd_disable", &format_args!("{}", self.swd_disable().bit()))
+            .field("swd_reset_flag", &self.swd_reset_flag())
+            .field("swd_auto_feed_en", &self.swd_auto_feed_en())
+            .field("swd_signal_width", &self.swd_signal_width())
+            .field("swd_disable", &self.swd_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_wdt/swd_wprotect.rs b/esp32h2/src/lp_wdt/swd_wprotect.rs
index b3d6f51abb..38581d43f4 100644
--- a/esp32h2/src/lp_wdt/swd_wprotect.rs
+++ b/esp32h2/src/lp_wdt/swd_wprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_WPROTECT")
-            .field("swd_wkey", &format_args!("{}", self.swd_wkey().bits()))
+            .field("swd_wkey", &self.swd_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_WPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_wdt/wdtconfig0.rs b/esp32h2/src/lp_wdt/wdtconfig0.rs
index 61abec16ae..66c1b14812 100644
--- a/esp32h2/src/lp_wdt/wdtconfig0.rs
+++ b/esp32h2/src/lp_wdt/wdtconfig0.rs
@@ -107,44 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG0")
-            .field(
-                "wdt_pause_in_slp",
-                &format_args!("{}", self.wdt_pause_in_slp().bit()),
-            )
-            .field(
-                "wdt_appcpu_reset_en",
-                &format_args!("{}", self.wdt_appcpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_pause_in_slp", &self.wdt_pause_in_slp())
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/lp_wdt/wdtwprotect.rs b/esp32h2/src/lp_wdt/wdtwprotect.rs
index b71af238cf..51457307f2 100644
--- a/esp32h2/src/lp_wdt/wdtwprotect.rs
+++ b/esp32h2/src/lp_wdt/wdtwprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTWPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTWPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/cap_ch.rs b/esp32h2/src/mcpwm0/cap_ch.rs
index c65d337a76..ffa38ba07f 100644
--- a/esp32h2/src/mcpwm0/cap_ch.rs
+++ b/esp32h2/src/mcpwm0/cap_ch.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_CH")
-            .field("value", &format_args!("{}", self.value().bits()))
+            .field("value", &self.value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Value of last capture on channel %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_ch::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CAP_CH_SPEC;
 impl crate::RegisterSpec for CAP_CH_SPEC {
diff --git a/esp32h2/src/mcpwm0/cap_ch_cfg.rs b/esp32h2/src/mcpwm0/cap_ch_cfg.rs
index 625f867b5d..27980b8a1d 100644
--- a/esp32h2/src/mcpwm0/cap_ch_cfg.rs
+++ b/esp32h2/src/mcpwm0/cap_ch_cfg.rs
@@ -46,19 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_CH_CFG")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
-            .field("in_invert", &format_args!("{}", self.in_invert().bit()))
+            .field("en", &self.en())
+            .field("mode", &self.mode())
+            .field("prescale", &self.prescale())
+            .field("in_invert", &self.in_invert())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_CH_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, capture on channel 0 is enabled"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/cap_status.rs b/esp32h2/src/mcpwm0/cap_status.rs
index bc686ac57a..24aafdc56e 100644
--- a/esp32h2/src/mcpwm0/cap_status.rs
+++ b/esp32h2/src/mcpwm0/cap_status.rs
@@ -27,18 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_STATUS")
-            .field("cap0_edge", &format_args!("{}", self.cap0_edge().bit()))
-            .field("cap1_edge", &format_args!("{}", self.cap1_edge().bit()))
-            .field("cap2_edge", &format_args!("{}", self.cap2_edge().bit()))
+            .field("cap0_edge", &self.cap0_edge())
+            .field("cap1_edge", &self.cap1_edge())
+            .field("cap2_edge", &self.cap2_edge())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Edge of last capture trigger\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CAP_STATUS_SPEC;
 impl crate::RegisterSpec for CAP_STATUS_SPEC {
diff --git a/esp32h2/src/mcpwm0/cap_timer_cfg.rs b/esp32h2/src/mcpwm0/cap_timer_cfg.rs
index 81a189d50f..124d285e52 100644
--- a/esp32h2/src/mcpwm0/cap_timer_cfg.rs
+++ b/esp32h2/src/mcpwm0/cap_timer_cfg.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_TIMER_CFG")
-            .field(
-                "cap_timer_en",
-                &format_args!("{}", self.cap_timer_en().bit()),
-            )
-            .field(
-                "cap_synci_en",
-                &format_args!("{}", self.cap_synci_en().bit()),
-            )
-            .field(
-                "cap_synci_sel",
-                &format_args!("{}", self.cap_synci_sel().bits()),
-            )
+            .field("cap_timer_en", &self.cap_timer_en())
+            .field("cap_synci_en", &self.cap_synci_en())
+            .field("cap_synci_sel", &self.cap_synci_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_TIMER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, capture timer incrementing under APB_clk is enabled."]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/cap_timer_phase.rs b/esp32h2/src/mcpwm0/cap_timer_phase.rs
index c476ea129f..4a1f0aea4a 100644
--- a/esp32h2/src/mcpwm0/cap_timer_phase.rs
+++ b/esp32h2/src/mcpwm0/cap_timer_phase.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_TIMER_PHASE")
-            .field("cap_phase", &format_args!("{}", self.cap_phase().bits()))
+            .field("cap_phase", &self.cap_phase())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_TIMER_PHASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Phase value for capture timer sync operation."]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/ch/carrier_cfg.rs b/esp32h2/src/mcpwm0/ch/carrier_cfg.rs
index 52e906ba7a..1c7ffd7384 100644
--- a/esp32h2/src/mcpwm0/ch/carrier_cfg.rs
+++ b/esp32h2/src/mcpwm0/ch/carrier_cfg.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CARRIER_CFG")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
-            .field("duty", &format_args!("{}", self.duty().bits()))
-            .field("oshtwth", &format_args!("{}", self.oshtwth().bits()))
-            .field("out_invert", &format_args!("{}", self.out_invert().bit()))
-            .field("in_invert", &format_args!("{}", self.in_invert().bit()))
+            .field("en", &self.en())
+            .field("prescale", &self.prescale())
+            .field("duty", &self.duty())
+            .field("oshtwth", &self.oshtwth())
+            .field("out_invert", &self.out_invert())
+            .field("in_invert", &self.in_invert())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CARRIER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/ch/dt_cfg.rs b/esp32h2/src/mcpwm0/ch/dt_cfg.rs
index 1826d8ec55..9d677b5a64 100644
--- a/esp32h2/src/mcpwm0/ch/dt_cfg.rs
+++ b/esp32h2/src/mcpwm0/ch/dt_cfg.rs
@@ -116,39 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DT_CFG")
-            .field(
-                "fed_upmethod",
-                &format_args!("{}", self.fed_upmethod().bits()),
-            )
-            .field(
-                "red_upmethod",
-                &format_args!("{}", self.red_upmethod().bits()),
-            )
-            .field("deb_mode", &format_args!("{}", self.deb_mode().bit()))
-            .field("a_outswap", &format_args!("{}", self.a_outswap().bit()))
-            .field("b_outswap", &format_args!("{}", self.b_outswap().bit()))
-            .field("red_insel", &format_args!("{}", self.red_insel().bit()))
-            .field("fed_insel", &format_args!("{}", self.fed_insel().bit()))
-            .field(
-                "red_outinvert",
-                &format_args!("{}", self.red_outinvert().bit()),
-            )
-            .field(
-                "fed_outinvert",
-                &format_args!("{}", self.fed_outinvert().bit()),
-            )
-            .field("a_outbypass", &format_args!("{}", self.a_outbypass().bit()))
-            .field("b_outbypass", &format_args!("{}", self.b_outbypass().bit()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bit()))
+            .field("fed_upmethod", &self.fed_upmethod())
+            .field("red_upmethod", &self.red_upmethod())
+            .field("deb_mode", &self.deb_mode())
+            .field("a_outswap", &self.a_outswap())
+            .field("b_outswap", &self.b_outswap())
+            .field("red_insel", &self.red_insel())
+            .field("fed_insel", &self.fed_insel())
+            .field("red_outinvert", &self.red_outinvert())
+            .field("fed_outinvert", &self.fed_outinvert())
+            .field("a_outbypass", &self.a_outbypass())
+            .field("b_outbypass", &self.b_outbypass())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DT_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/ch/dt_fed_cfg.rs b/esp32h2/src/mcpwm0/ch/dt_fed_cfg.rs
index 32a5d442af..26a2a9235a 100644
--- a/esp32h2/src/mcpwm0/ch/dt_fed_cfg.rs
+++ b/esp32h2/src/mcpwm0/ch/dt_fed_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DT_FED_CFG")
-            .field("fed", &format_args!("{}", self.fed().bits()))
+            .field("fed", &self.fed())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DT_FED_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Shadow register for FED"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/ch/dt_red_cfg.rs b/esp32h2/src/mcpwm0/ch/dt_red_cfg.rs
index cbd50cd7b4..d2f4e5d496 100644
--- a/esp32h2/src/mcpwm0/ch/dt_red_cfg.rs
+++ b/esp32h2/src/mcpwm0/ch/dt_red_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DT_RED_CFG")
-            .field("red", &format_args!("{}", self.red().bits()))
+            .field("red", &self.red())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DT_RED_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Shadow register for RED"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/ch/fh_cfg0.rs b/esp32h2/src/mcpwm0/ch/fh_cfg0.rs
index 16bf20dc2c..32865deb0b 100644
--- a/esp32h2/src/mcpwm0/ch/fh_cfg0.rs
+++ b/esp32h2/src/mcpwm0/ch/fh_cfg0.rs
@@ -152,31 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FH_CFG0")
-            .field("sw_cbc", &format_args!("{}", self.sw_cbc().bit()))
-            .field("f2_cbc", &format_args!("{}", self.f2_cbc().bit()))
-            .field("f1_cbc", &format_args!("{}", self.f1_cbc().bit()))
-            .field("f0_cbc", &format_args!("{}", self.f0_cbc().bit()))
-            .field("sw_ost", &format_args!("{}", self.sw_ost().bit()))
-            .field("f2_ost", &format_args!("{}", self.f2_ost().bit()))
-            .field("f1_ost", &format_args!("{}", self.f1_ost().bit()))
-            .field("f0_ost", &format_args!("{}", self.f0_ost().bit()))
-            .field("a_cbc_d", &format_args!("{}", self.a_cbc_d().bits()))
-            .field("a_cbc_u", &format_args!("{}", self.a_cbc_u().bits()))
-            .field("a_ost_d", &format_args!("{}", self.a_ost_d().bits()))
-            .field("a_ost_u", &format_args!("{}", self.a_ost_u().bits()))
-            .field("b_cbc_d", &format_args!("{}", self.b_cbc_d().bits()))
-            .field("b_cbc_u", &format_args!("{}", self.b_cbc_u().bits()))
-            .field("b_ost_d", &format_args!("{}", self.b_ost_d().bits()))
-            .field("b_ost_u", &format_args!("{}", self.b_ost_u().bits()))
+            .field("sw_cbc", &self.sw_cbc())
+            .field("f2_cbc", &self.f2_cbc())
+            .field("f1_cbc", &self.f1_cbc())
+            .field("f0_cbc", &self.f0_cbc())
+            .field("sw_ost", &self.sw_ost())
+            .field("f2_ost", &self.f2_ost())
+            .field("f1_ost", &self.f1_ost())
+            .field("f0_ost", &self.f0_ost())
+            .field("a_cbc_d", &self.a_cbc_d())
+            .field("a_cbc_u", &self.a_cbc_u())
+            .field("a_ost_d", &self.a_ost_d())
+            .field("a_ost_u", &self.a_ost_u())
+            .field("b_cbc_d", &self.b_cbc_d())
+            .field("b_cbc_u", &self.b_cbc_u())
+            .field("b_ost_d", &self.b_ost_d())
+            .field("b_ost_u", &self.b_ost_u())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FH_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/ch/fh_cfg1.rs b/esp32h2/src/mcpwm0/ch/fh_cfg1.rs
index 01221dba64..422ad1a496 100644
--- a/esp32h2/src/mcpwm0/ch/fh_cfg1.rs
+++ b/esp32h2/src/mcpwm0/ch/fh_cfg1.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FH_CFG1")
-            .field("clr_ost", &format_args!("{}", self.clr_ost().bit()))
-            .field("cbcpulse", &format_args!("{}", self.cbcpulse().bits()))
-            .field("force_cbc", &format_args!("{}", self.force_cbc().bit()))
-            .field("force_ost", &format_args!("{}", self.force_ost().bit()))
+            .field("clr_ost", &self.clr_ost())
+            .field("cbcpulse", &self.cbcpulse())
+            .field("force_cbc", &self.force_cbc())
+            .field("force_ost", &self.force_ost())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FH_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - a rising edge will clear on going one-shot mode action"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/ch/fh_status.rs b/esp32h2/src/mcpwm0/ch/fh_status.rs
index 6c5fc8920f..5b2963a2e1 100644
--- a/esp32h2/src/mcpwm0/ch/fh_status.rs
+++ b/esp32h2/src/mcpwm0/ch/fh_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FH_STATUS")
-            .field("cbc_on", &format_args!("{}", self.cbc_on().bit()))
-            .field("ost_on", &format_args!("{}", self.ost_on().bit()))
+            .field("cbc_on", &self.cbc_on())
+            .field("ost_on", &self.ost_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FH_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of fault events.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FH_STATUS_SPEC;
 impl crate::RegisterSpec for FH_STATUS_SPEC {
diff --git a/esp32h2/src/mcpwm0/ch/gen.rs b/esp32h2/src/mcpwm0/ch/gen.rs
index 5d8addc59e..0d27bbd1b8 100644
--- a/esp32h2/src/mcpwm0/ch/gen.rs
+++ b/esp32h2/src/mcpwm0/ch/gen.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN")
-            .field("utez", &format_args!("{}", self.utez().bits()))
-            .field("utep", &format_args!("{}", self.utep().bits()))
-            .field("utea", &format_args!("{}", self.utea().bits()))
-            .field("uteb", &format_args!("{}", self.uteb().bits()))
-            .field("ut0", &format_args!("{}", self.ut0().bits()))
-            .field("ut1", &format_args!("{}", self.ut1().bits()))
-            .field("dtez", &format_args!("{}", self.dtez().bits()))
-            .field("dtep", &format_args!("{}", self.dtep().bits()))
-            .field("dtea", &format_args!("{}", self.dtea().bits()))
-            .field("dteb", &format_args!("{}", self.dteb().bits()))
-            .field("dt0", &format_args!("{}", self.dt0().bits()))
-            .field("dt1", &format_args!("{}", self.dt1().bits()))
+            .field("utez", &self.utez())
+            .field("utep", &self.utep())
+            .field("utea", &self.utea())
+            .field("uteb", &self.uteb())
+            .field("ut0", &self.ut0())
+            .field("ut1", &self.ut1())
+            .field("dtez", &self.dtez())
+            .field("dtep", &self.dtep())
+            .field("dtea", &self.dtea())
+            .field("dteb", &self.dteb())
+            .field("dt0", &self.dt0())
+            .field("dt1", &self.dt1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Action on PWM0A triggered by event TEZ when timer increasing"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/ch/gen_cfg0.rs b/esp32h2/src/mcpwm0/ch/gen_cfg0.rs
index 75032323fa..2f5827870c 100644
--- a/esp32h2/src/mcpwm0/ch/gen_cfg0.rs
+++ b/esp32h2/src/mcpwm0/ch/gen_cfg0.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_CFG0")
-            .field(
-                "cfg_upmethod",
-                &format_args!("{}", self.cfg_upmethod().bits()),
-            )
-            .field("t0_sel", &format_args!("{}", self.t0_sel().bits()))
-            .field("t1_sel", &format_args!("{}", self.t1_sel().bits()))
+            .field("cfg_upmethod", &self.cfg_upmethod())
+            .field("t0_sel", &self.t0_sel())
+            .field("t1_sel", &self.t1_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/ch/gen_force.rs b/esp32h2/src/mcpwm0/ch/gen_force.rs
index 3fcb77525c..a6a8be6844 100644
--- a/esp32h2/src/mcpwm0/ch/gen_force.rs
+++ b/esp32h2/src/mcpwm0/ch/gen_force.rs
@@ -71,37 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_FORCE")
-            .field(
-                "cntuforce_upmethod",
-                &format_args!("{}", self.cntuforce_upmethod().bits()),
-            )
-            .field(
-                "a_cntuforce_mode",
-                &format_args!("{}", self.a_cntuforce_mode().bits()),
-            )
-            .field(
-                "b_cntuforce_mode",
-                &format_args!("{}", self.b_cntuforce_mode().bits()),
-            )
-            .field("a_nciforce", &format_args!("{}", self.a_nciforce().bit()))
-            .field(
-                "a_nciforce_mode",
-                &format_args!("{}", self.a_nciforce_mode().bits()),
-            )
-            .field("b_nciforce", &format_args!("{}", self.b_nciforce().bit()))
-            .field(
-                "b_nciforce_mode",
-                &format_args!("{}", self.b_nciforce_mode().bits()),
-            )
+            .field("cntuforce_upmethod", &self.cntuforce_upmethod())
+            .field("a_cntuforce_mode", &self.a_cntuforce_mode())
+            .field("b_cntuforce_mode", &self.b_cntuforce_mode())
+            .field("a_nciforce", &self.a_nciforce())
+            .field("a_nciforce_mode", &self.a_nciforce_mode())
+            .field("b_nciforce", &self.b_nciforce())
+            .field("b_nciforce_mode", &self.b_nciforce_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_FORCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/ch/gen_stmp_cfg.rs b/esp32h2/src/mcpwm0/ch/gen_stmp_cfg.rs
index c8006017b2..29d78031d4 100644
--- a/esp32h2/src/mcpwm0/ch/gen_stmp_cfg.rs
+++ b/esp32h2/src/mcpwm0/ch/gen_stmp_cfg.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_STMP_CFG")
-            .field("a_upmethod", &format_args!("{}", self.a_upmethod().bits()))
-            .field("b_upmethod", &format_args!("{}", self.b_upmethod().bits()))
-            .field("a_shdw_full", &format_args!("{}", self.a_shdw_full().bit()))
-            .field("b_shdw_full", &format_args!("{}", self.b_shdw_full().bit()))
+            .field("a_upmethod", &self.a_upmethod())
+            .field("b_upmethod", &self.b_upmethod())
+            .field("a_shdw_full", &self.a_shdw_full())
+            .field("b_shdw_full", &self.b_shdw_full())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_STMP_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/ch/gen_tstmp_a.rs b/esp32h2/src/mcpwm0/ch/gen_tstmp_a.rs
index 1dd337661a..7fdbc1e7d1 100644
--- a/esp32h2/src/mcpwm0/ch/gen_tstmp_a.rs
+++ b/esp32h2/src/mcpwm0/ch/gen_tstmp_a.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("GEN_TSTMP_A")
-            .field("a", &format_args!("{}", self.a().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_TSTMP_A_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("GEN_TSTMP_A").field("a", &self.a()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/mcpwm0/ch/gen_tstmp_b.rs b/esp32h2/src/mcpwm0/ch/gen_tstmp_b.rs
index 1d128d47ed..6f8486d5a0 100644
--- a/esp32h2/src/mcpwm0/ch/gen_tstmp_b.rs
+++ b/esp32h2/src/mcpwm0/ch/gen_tstmp_b.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("GEN_TSTMP_B")
-            .field("b", &format_args!("{}", self.b().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_TSTMP_B_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("GEN_TSTMP_B").field("b", &self.b()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/mcpwm0/clk.rs b/esp32h2/src/mcpwm0/clk.rs
index 806dbb6cad..6df7d05643 100644
--- a/esp32h2/src/mcpwm0/clk.rs
+++ b/esp32h2/src/mcpwm0/clk.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CLK")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CLK").field("en", &self.en()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/mcpwm0/clk_cfg.rs b/esp32h2/src/mcpwm0/clk_cfg.rs
index 387991fe50..dfca5315ac 100644
--- a/esp32h2/src/mcpwm0/clk_cfg.rs
+++ b/esp32h2/src/mcpwm0/clk_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CFG")
-            .field(
-                "clk_prescale",
-                &format_args!("{}", self.clk_prescale().bits()),
-            )
+            .field("clk_prescale", &self.clk_prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/evt_en.rs b/esp32h2/src/mcpwm0/evt_en.rs
index e973be0d27..36a4aa698e 100644
--- a/esp32h2/src/mcpwm0/evt_en.rs
+++ b/esp32h2/src/mcpwm0/evt_en.rs
@@ -278,117 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVT_EN")
-            .field(
-                "evt_timer0_stop_en",
-                &format_args!("{}", self.evt_timer0_stop_en().bit()),
-            )
-            .field(
-                "evt_timer1_stop_en",
-                &format_args!("{}", self.evt_timer1_stop_en().bit()),
-            )
-            .field(
-                "evt_timer2_stop_en",
-                &format_args!("{}", self.evt_timer2_stop_en().bit()),
-            )
-            .field(
-                "evt_timer0_tez_en",
-                &format_args!("{}", self.evt_timer0_tez_en().bit()),
-            )
-            .field(
-                "evt_timer1_tez_en",
-                &format_args!("{}", self.evt_timer1_tez_en().bit()),
-            )
-            .field(
-                "evt_timer2_tez_en",
-                &format_args!("{}", self.evt_timer2_tez_en().bit()),
-            )
-            .field(
-                "evt_timer0_tep_en",
-                &format_args!("{}", self.evt_timer0_tep_en().bit()),
-            )
-            .field(
-                "evt_timer1_tep_en",
-                &format_args!("{}", self.evt_timer1_tep_en().bit()),
-            )
-            .field(
-                "evt_timer2_tep_en",
-                &format_args!("{}", self.evt_timer2_tep_en().bit()),
-            )
-            .field(
-                "evt_op0_tea_en",
-                &format_args!("{}", self.evt_op0_tea_en().bit()),
-            )
-            .field(
-                "evt_op1_tea_en",
-                &format_args!("{}", self.evt_op1_tea_en().bit()),
-            )
-            .field(
-                "evt_op2_tea_en",
-                &format_args!("{}", self.evt_op2_tea_en().bit()),
-            )
-            .field(
-                "evt_op0_teb_en",
-                &format_args!("{}", self.evt_op0_teb_en().bit()),
-            )
-            .field(
-                "evt_op1_teb_en",
-                &format_args!("{}", self.evt_op1_teb_en().bit()),
-            )
-            .field(
-                "evt_op2_teb_en",
-                &format_args!("{}", self.evt_op2_teb_en().bit()),
-            )
-            .field("evt_f0_en", &format_args!("{}", self.evt_f0_en().bit()))
-            .field("evt_f1_en", &format_args!("{}", self.evt_f1_en().bit()))
-            .field("evt_f2_en", &format_args!("{}", self.evt_f2_en().bit()))
-            .field(
-                "evt_f0_clr_en",
-                &format_args!("{}", self.evt_f0_clr_en().bit()),
-            )
-            .field(
-                "evt_f1_clr_en",
-                &format_args!("{}", self.evt_f1_clr_en().bit()),
-            )
-            .field(
-                "evt_f2_clr_en",
-                &format_args!("{}", self.evt_f2_clr_en().bit()),
-            )
-            .field(
-                "evt_tz0_cbc_en",
-                &format_args!("{}", self.evt_tz0_cbc_en().bit()),
-            )
-            .field(
-                "evt_tz1_cbc_en",
-                &format_args!("{}", self.evt_tz1_cbc_en().bit()),
-            )
-            .field(
-                "evt_tz2_cbc_en",
-                &format_args!("{}", self.evt_tz2_cbc_en().bit()),
-            )
-            .field(
-                "evt_tz0_ost_en",
-                &format_args!("{}", self.evt_tz0_ost_en().bit()),
-            )
-            .field(
-                "evt_tz1_ost_en",
-                &format_args!("{}", self.evt_tz1_ost_en().bit()),
-            )
-            .field(
-                "evt_tz2_ost_en",
-                &format_args!("{}", self.evt_tz2_ost_en().bit()),
-            )
-            .field("evt_cap0_en", &format_args!("{}", self.evt_cap0_en().bit()))
-            .field("evt_cap1_en", &format_args!("{}", self.evt_cap1_en().bit()))
-            .field("evt_cap2_en", &format_args!("{}", self.evt_cap2_en().bit()))
+            .field("evt_timer0_stop_en", &self.evt_timer0_stop_en())
+            .field("evt_timer1_stop_en", &self.evt_timer1_stop_en())
+            .field("evt_timer2_stop_en", &self.evt_timer2_stop_en())
+            .field("evt_timer0_tez_en", &self.evt_timer0_tez_en())
+            .field("evt_timer1_tez_en", &self.evt_timer1_tez_en())
+            .field("evt_timer2_tez_en", &self.evt_timer2_tez_en())
+            .field("evt_timer0_tep_en", &self.evt_timer0_tep_en())
+            .field("evt_timer1_tep_en", &self.evt_timer1_tep_en())
+            .field("evt_timer2_tep_en", &self.evt_timer2_tep_en())
+            .field("evt_op0_tea_en", &self.evt_op0_tea_en())
+            .field("evt_op1_tea_en", &self.evt_op1_tea_en())
+            .field("evt_op2_tea_en", &self.evt_op2_tea_en())
+            .field("evt_op0_teb_en", &self.evt_op0_teb_en())
+            .field("evt_op1_teb_en", &self.evt_op1_teb_en())
+            .field("evt_op2_teb_en", &self.evt_op2_teb_en())
+            .field("evt_f0_en", &self.evt_f0_en())
+            .field("evt_f1_en", &self.evt_f1_en())
+            .field("evt_f2_en", &self.evt_f2_en())
+            .field("evt_f0_clr_en", &self.evt_f0_clr_en())
+            .field("evt_f1_clr_en", &self.evt_f1_clr_en())
+            .field("evt_f2_clr_en", &self.evt_f2_clr_en())
+            .field("evt_tz0_cbc_en", &self.evt_tz0_cbc_en())
+            .field("evt_tz1_cbc_en", &self.evt_tz1_cbc_en())
+            .field("evt_tz2_cbc_en", &self.evt_tz2_cbc_en())
+            .field("evt_tz0_ost_en", &self.evt_tz0_ost_en())
+            .field("evt_tz1_ost_en", &self.evt_tz1_ost_en())
+            .field("evt_tz2_ost_en", &self.evt_tz2_ost_en())
+            .field("evt_cap0_en", &self.evt_cap0_en())
+            .field("evt_cap1_en", &self.evt_cap1_en())
+            .field("evt_cap2_en", &self.evt_cap2_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this bit high to enable timer0 stop event generate"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/fault_detect.rs b/esp32h2/src/mcpwm0/fault_detect.rs
index 52af954abd..1b5edb56d6 100644
--- a/esp32h2/src/mcpwm0/fault_detect.rs
+++ b/esp32h2/src/mcpwm0/fault_detect.rs
@@ -83,24 +83,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FAULT_DETECT")
-            .field("f0_en", &format_args!("{}", self.f0_en().bit()))
-            .field("f1_en", &format_args!("{}", self.f1_en().bit()))
-            .field("f2_en", &format_args!("{}", self.f2_en().bit()))
-            .field("f0_pole", &format_args!("{}", self.f0_pole().bit()))
-            .field("f1_pole", &format_args!("{}", self.f1_pole().bit()))
-            .field("f2_pole", &format_args!("{}", self.f2_pole().bit()))
-            .field("event_f0", &format_args!("{}", self.event_f0().bit()))
-            .field("event_f1", &format_args!("{}", self.event_f1().bit()))
-            .field("event_f2", &format_args!("{}", self.event_f2().bit()))
+            .field("f0_en", &self.f0_en())
+            .field("f1_en", &self.f1_en())
+            .field("f2_en", &self.f2_en())
+            .field("f0_pole", &self.f0_pole())
+            .field("f1_pole", &self.f1_pole())
+            .field("f2_pole", &self.f2_pole())
+            .field("event_f0", &self.event_f0())
+            .field("event_f1", &self.event_f1())
+            .field("event_f2", &self.event_f2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FAULT_DETECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, event_f0 generation is enabled"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/int_ena.rs b/esp32h2/src/mcpwm0/int_ena.rs
index 529d6f4a20..dab6312c95 100644
--- a/esp32h2/src/mcpwm0/int_ena.rs
+++ b/esp32h2/src/mcpwm0/int_ena.rs
@@ -278,45 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("fault0", &format_args!("{}", self.fault0().bit()))
-            .field("fault1", &format_args!("{}", self.fault1().bit()))
-            .field("fault2", &format_args!("{}", self.fault2().bit()))
-            .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
-            .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
-            .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
-            .field("cmpr0_tea", &format_args!("{}", self.cmpr0_tea().bit()))
-            .field("cmpr1_tea", &format_args!("{}", self.cmpr1_tea().bit()))
-            .field("cmpr2_tea", &format_args!("{}", self.cmpr2_tea().bit()))
-            .field("cmpr0_teb", &format_args!("{}", self.cmpr0_teb().bit()))
-            .field("cmpr1_teb", &format_args!("{}", self.cmpr1_teb().bit()))
-            .field("cmpr2_teb", &format_args!("{}", self.cmpr2_teb().bit()))
-            .field("tz0_cbc", &format_args!("{}", self.tz0_cbc().bit()))
-            .field("tz1_cbc", &format_args!("{}", self.tz1_cbc().bit()))
-            .field("tz2_cbc", &format_args!("{}", self.tz2_cbc().bit()))
-            .field("tz0_ost", &format_args!("{}", self.tz0_ost().bit()))
-            .field("tz1_ost", &format_args!("{}", self.tz1_ost().bit()))
-            .field("tz2_ost", &format_args!("{}", self.tz2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for the interrupt triggered when the timer 0 stops."]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/int_raw.rs b/esp32h2/src/mcpwm0/int_raw.rs
index b45523dcdc..447b1d86a2 100644
--- a/esp32h2/src/mcpwm0/int_raw.rs
+++ b/esp32h2/src/mcpwm0/int_raw.rs
@@ -278,45 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("fault0", &format_args!("{}", self.fault0().bit()))
-            .field("fault1", &format_args!("{}", self.fault1().bit()))
-            .field("fault2", &format_args!("{}", self.fault2().bit()))
-            .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
-            .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
-            .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
-            .field("cmpr0_tea", &format_args!("{}", self.cmpr0_tea().bit()))
-            .field("cmpr1_tea", &format_args!("{}", self.cmpr1_tea().bit()))
-            .field("cmpr2_tea", &format_args!("{}", self.cmpr2_tea().bit()))
-            .field("cmpr0_teb", &format_args!("{}", self.cmpr0_teb().bit()))
-            .field("cmpr1_teb", &format_args!("{}", self.cmpr1_teb().bit()))
-            .field("cmpr2_teb", &format_args!("{}", self.cmpr2_teb().bit()))
-            .field("tz0_cbc", &format_args!("{}", self.tz0_cbc().bit()))
-            .field("tz1_cbc", &format_args!("{}", self.tz1_cbc().bit()))
-            .field("tz2_cbc", &format_args!("{}", self.tz2_cbc().bit()))
-            .field("tz0_ost", &format_args!("{}", self.tz0_ost().bit()))
-            .field("tz1_ost", &format_args!("{}", self.tz1_ost().bit()))
-            .field("tz2_ost", &format_args!("{}", self.tz2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw status bit for the interrupt triggered when the timer 0 stops."]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/int_st.rs b/esp32h2/src/mcpwm0/int_st.rs
index 8627093497..dff68bd8dd 100644
--- a/esp32h2/src/mcpwm0/int_st.rs
+++ b/esp32h2/src/mcpwm0/int_st.rs
@@ -216,45 +216,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("fault0", &format_args!("{}", self.fault0().bit()))
-            .field("fault1", &format_args!("{}", self.fault1().bit()))
-            .field("fault2", &format_args!("{}", self.fault2().bit()))
-            .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
-            .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
-            .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
-            .field("cmpr0_tea", &format_args!("{}", self.cmpr0_tea().bit()))
-            .field("cmpr1_tea", &format_args!("{}", self.cmpr1_tea().bit()))
-            .field("cmpr2_tea", &format_args!("{}", self.cmpr2_tea().bit()))
-            .field("cmpr0_teb", &format_args!("{}", self.cmpr0_teb().bit()))
-            .field("cmpr1_teb", &format_args!("{}", self.cmpr1_teb().bit()))
-            .field("cmpr2_teb", &format_args!("{}", self.cmpr2_teb().bit()))
-            .field("tz0_cbc", &format_args!("{}", self.tz0_cbc().bit()))
-            .field("tz1_cbc", &format_args!("{}", self.tz1_cbc().bit()))
-            .field("tz2_cbc", &format_args!("{}", self.tz2_cbc().bit()))
-            .field("tz0_ost", &format_args!("{}", self.tz0_ost().bit()))
-            .field("tz1_ost", &format_args!("{}", self.tz1_ost().bit()))
-            .field("tz2_ost", &format_args!("{}", self.tz2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/mcpwm0/operator_timersel.rs b/esp32h2/src/mcpwm0/operator_timersel.rs
index a9fa9acb15..55e9d23758 100644
--- a/esp32h2/src/mcpwm0/operator_timersel.rs
+++ b/esp32h2/src/mcpwm0/operator_timersel.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OPERATOR_TIMERSEL")
-            .field(
-                "operator0_timersel",
-                &format_args!("{}", self.operator0_timersel().bits()),
-            )
-            .field(
-                "operator1_timersel",
-                &format_args!("{}", self.operator1_timersel().bits()),
-            )
-            .field(
-                "operator2_timersel",
-                &format_args!("{}", self.operator2_timersel().bits()),
-            )
+            .field("operator0_timersel", &self.operator0_timersel())
+            .field("operator1_timersel", &self.operator1_timersel())
+            .field("operator2_timersel", &self.operator2_timersel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OPERATOR_TIMERSEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/task_en.rs b/esp32h2/src/mcpwm0/task_en.rs
index ffc1f2e5a2..70561af014 100644
--- a/esp32h2/src/mcpwm0/task_en.rs
+++ b/esp32h2/src/mcpwm0/task_en.rs
@@ -206,103 +206,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TASK_EN")
-            .field(
-                "task_cmpr0_a_up_en",
-                &format_args!("{}", self.task_cmpr0_a_up_en().bit()),
-            )
-            .field(
-                "task_cmpr1_a_up_en",
-                &format_args!("{}", self.task_cmpr1_a_up_en().bit()),
-            )
-            .field(
-                "task_cmpr2_a_up_en",
-                &format_args!("{}", self.task_cmpr2_a_up_en().bit()),
-            )
-            .field(
-                "task_cmpr0_b_up_en",
-                &format_args!("{}", self.task_cmpr0_b_up_en().bit()),
-            )
-            .field(
-                "task_cmpr1_b_up_en",
-                &format_args!("{}", self.task_cmpr1_b_up_en().bit()),
-            )
-            .field(
-                "task_cmpr2_b_up_en",
-                &format_args!("{}", self.task_cmpr2_b_up_en().bit()),
-            )
-            .field(
-                "task_gen_stop_en",
-                &format_args!("{}", self.task_gen_stop_en().bit()),
-            )
-            .field(
-                "task_timer0_sync_en",
-                &format_args!("{}", self.task_timer0_sync_en().bit()),
-            )
-            .field(
-                "task_timer1_sync_en",
-                &format_args!("{}", self.task_timer1_sync_en().bit()),
-            )
-            .field(
-                "task_timer2_sync_en",
-                &format_args!("{}", self.task_timer2_sync_en().bit()),
-            )
-            .field(
-                "task_timer0_period_up_en",
-                &format_args!("{}", self.task_timer0_period_up_en().bit()),
-            )
-            .field(
-                "task_timer1_period_up_en",
-                &format_args!("{}", self.task_timer1_period_up_en().bit()),
-            )
-            .field(
-                "task_timer2_period_up_en",
-                &format_args!("{}", self.task_timer2_period_up_en().bit()),
-            )
-            .field(
-                "task_tz0_ost_en",
-                &format_args!("{}", self.task_tz0_ost_en().bit()),
-            )
-            .field(
-                "task_tz1_ost_en",
-                &format_args!("{}", self.task_tz1_ost_en().bit()),
-            )
-            .field(
-                "task_tz2_ost_en",
-                &format_args!("{}", self.task_tz2_ost_en().bit()),
-            )
-            .field(
-                "task_clr0_ost_en",
-                &format_args!("{}", self.task_clr0_ost_en().bit()),
-            )
-            .field(
-                "task_clr1_ost_en",
-                &format_args!("{}", self.task_clr1_ost_en().bit()),
-            )
-            .field(
-                "task_clr2_ost_en",
-                &format_args!("{}", self.task_clr2_ost_en().bit()),
-            )
-            .field(
-                "task_cap0_en",
-                &format_args!("{}", self.task_cap0_en().bit()),
-            )
-            .field(
-                "task_cap1_en",
-                &format_args!("{}", self.task_cap1_en().bit()),
-            )
-            .field(
-                "task_cap2_en",
-                &format_args!("{}", self.task_cap2_en().bit()),
-            )
+            .field("task_cmpr0_a_up_en", &self.task_cmpr0_a_up_en())
+            .field("task_cmpr1_a_up_en", &self.task_cmpr1_a_up_en())
+            .field("task_cmpr2_a_up_en", &self.task_cmpr2_a_up_en())
+            .field("task_cmpr0_b_up_en", &self.task_cmpr0_b_up_en())
+            .field("task_cmpr1_b_up_en", &self.task_cmpr1_b_up_en())
+            .field("task_cmpr2_b_up_en", &self.task_cmpr2_b_up_en())
+            .field("task_gen_stop_en", &self.task_gen_stop_en())
+            .field("task_timer0_sync_en", &self.task_timer0_sync_en())
+            .field("task_timer1_sync_en", &self.task_timer1_sync_en())
+            .field("task_timer2_sync_en", &self.task_timer2_sync_en())
+            .field("task_timer0_period_up_en", &self.task_timer0_period_up_en())
+            .field("task_timer1_period_up_en", &self.task_timer1_period_up_en())
+            .field("task_timer2_period_up_en", &self.task_timer2_period_up_en())
+            .field("task_tz0_ost_en", &self.task_tz0_ost_en())
+            .field("task_tz1_ost_en", &self.task_tz1_ost_en())
+            .field("task_tz2_ost_en", &self.task_tz2_ost_en())
+            .field("task_clr0_ost_en", &self.task_clr0_ost_en())
+            .field("task_clr1_ost_en", &self.task_clr1_ost_en())
+            .field("task_clr2_ost_en", &self.task_clr2_ost_en())
+            .field("task_cap0_en", &self.task_cap0_en())
+            .field("task_cap1_en", &self.task_cap1_en())
+            .field("task_cap2_en", &self.task_cap2_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TASK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this bit high to enable PWM generator0 timer stamp A's shadow register update task receive"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/timer/cfg0.rs b/esp32h2/src/mcpwm0/timer/cfg0.rs
index 904a515549..9fb25841a5 100644
--- a/esp32h2/src/mcpwm0/timer/cfg0.rs
+++ b/esp32h2/src/mcpwm0/timer/cfg0.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG0")
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
-            .field("period", &format_args!("{}", self.period().bits()))
-            .field(
-                "period_upmethod",
-                &format_args!("{}", self.period_upmethod().bits()),
-            )
+            .field("prescale", &self.prescale())
+            .field("period", &self.period())
+            .field("period_upmethod", &self.period_upmethod())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/timer/cfg1.rs b/esp32h2/src/mcpwm0/timer/cfg1.rs
index 086070d09e..92bed8f96a 100644
--- a/esp32h2/src/mcpwm0/timer/cfg1.rs
+++ b/esp32h2/src/mcpwm0/timer/cfg1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG1")
-            .field("start", &format_args!("{}", self.start().bits()))
-            .field("mod_", &format_args!("{}", self.mod_().bits()))
+            .field("start", &self.start())
+            .field("mod_", &self.mod_())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/timer/status.rs b/esp32h2/src/mcpwm0/timer/status.rs
index 576e1198f5..5dd843bac9 100644
--- a/esp32h2/src/mcpwm0/timer/status.rs
+++ b/esp32h2/src/mcpwm0/timer/status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("value", &format_args!("{}", self.value().bits()))
-            .field("direction", &format_args!("{}", self.direction().bit()))
+            .field("value", &self.value())
+            .field("direction", &self.direction())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "PWM TIMERx status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32h2/src/mcpwm0/timer/sync.rs b/esp32h2/src/mcpwm0/timer/sync.rs
index b629b45d15..b36d435ba9 100644
--- a/esp32h2/src/mcpwm0/timer/sync.rs
+++ b/esp32h2/src/mcpwm0/timer/sync.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYNC")
-            .field("synci_en", &format_args!("{}", self.synci_en().bit()))
-            .field("sw", &format_args!("{}", self.sw().bit()))
-            .field("synco_sel", &format_args!("{}", self.synco_sel().bits()))
-            .field("phase", &format_args!("{}", self.phase().bits()))
-            .field(
-                "phase_direction",
-                &format_args!("{}", self.phase_direction().bit()),
-            )
+            .field("synci_en", &self.synci_en())
+            .field("sw", &self.sw())
+            .field("synco_sel", &self.synco_sel())
+            .field("phase", &self.phase())
+            .field("phase_direction", &self.phase_direction())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, timer reloading with phase on sync input event is enabled."]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/timer_synci_cfg.rs b/esp32h2/src/mcpwm0/timer_synci_cfg.rs
index e532121427..2f7f399404 100644
--- a/esp32h2/src/mcpwm0/timer_synci_cfg.rs
+++ b/esp32h2/src/mcpwm0/timer_synci_cfg.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_SYNCI_CFG")
-            .field(
-                "timer0_syncisel",
-                &format_args!("{}", self.timer0_syncisel().bits()),
-            )
-            .field(
-                "timer1_syncisel",
-                &format_args!("{}", self.timer1_syncisel().bits()),
-            )
-            .field(
-                "timer2_syncisel",
-                &format_args!("{}", self.timer2_syncisel().bits()),
-            )
-            .field(
-                "external_synci0_invert",
-                &format_args!("{}", self.external_synci0_invert().bit()),
-            )
-            .field(
-                "external_synci1_invert",
-                &format_args!("{}", self.external_synci1_invert().bit()),
-            )
-            .field(
-                "external_synci2_invert",
-                &format_args!("{}", self.external_synci2_invert().bit()),
-            )
+            .field("timer0_syncisel", &self.timer0_syncisel())
+            .field("timer1_syncisel", &self.timer1_syncisel())
+            .field("timer2_syncisel", &self.timer2_syncisel())
+            .field("external_synci0_invert", &self.external_synci0_invert())
+            .field("external_synci1_invert", &self.external_synci1_invert())
+            .field("external_synci2_invert", &self.external_synci2_invert())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_SYNCI_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/update_cfg.rs b/esp32h2/src/mcpwm0/update_cfg.rs
index 07aa2a6a04..f5179c7fbc 100644
--- a/esp32h2/src/mcpwm0/update_cfg.rs
+++ b/esp32h2/src/mcpwm0/update_cfg.rs
@@ -80,38 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE_CFG")
-            .field(
-                "global_up_en",
-                &format_args!("{}", self.global_up_en().bit()),
-            )
-            .field(
-                "global_force_up",
-                &format_args!("{}", self.global_force_up().bit()),
-            )
-            .field("op0_up_en", &format_args!("{}", self.op0_up_en().bit()))
-            .field(
-                "op0_force_up",
-                &format_args!("{}", self.op0_force_up().bit()),
-            )
-            .field("op1_up_en", &format_args!("{}", self.op1_up_en().bit()))
-            .field(
-                "op1_force_up",
-                &format_args!("{}", self.op1_force_up().bit()),
-            )
-            .field("op2_up_en", &format_args!("{}", self.op2_up_en().bit()))
-            .field(
-                "op2_force_up",
-                &format_args!("{}", self.op2_force_up().bit()),
-            )
+            .field("global_up_en", &self.global_up_en())
+            .field("global_force_up", &self.global_force_up())
+            .field("op0_up_en", &self.op0_up_en())
+            .field("op0_force_up", &self.op0_force_up())
+            .field("op1_up_en", &self.op1_up_en())
+            .field("op1_force_up", &self.op1_force_up())
+            .field("op2_up_en", &self.op2_up_en())
+            .field("op2_force_up", &self.op2_force_up())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The global enable of update of all active registers in MCPWM module"]
     #[inline(always)]
diff --git a/esp32h2/src/mcpwm0/version.rs b/esp32h2/src/mcpwm0/version.rs
index b0efd350d5..aef0e5edd2 100644
--- a/esp32h2/src/mcpwm0/version.rs
+++ b/esp32h2/src/mcpwm0/version.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version of this register file"]
     #[inline(always)]
diff --git a/esp32h2/src/mem_monitor/clock_gate.rs b/esp32h2/src/mem_monitor/clock_gate.rs
index 41f38a3640..20414e3a4d 100644
--- a/esp32h2/src/mem_monitor/clock_gate.rs
+++ b/esp32h2/src/mem_monitor/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to force on the clk of mem_monitor register"]
     #[inline(always)]
diff --git a/esp32h2/src/mem_monitor/date.rs b/esp32h2/src/mem_monitor/date.rs
index 1790e90a70..2e5dbe01c7 100644
--- a/esp32h2/src/mem_monitor/date.rs
+++ b/esp32h2/src/mem_monitor/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/mem_monitor/log_check_data.rs b/esp32h2/src/mem_monitor/log_check_data.rs
index 4c387f085b..a0ec3bd836 100644
--- a/esp32h2/src/mem_monitor/log_check_data.rs
+++ b/esp32h2/src/mem_monitor/log_check_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_CHECK_DATA")
-            .field(
-                "log_check_data",
-                &format_args!("{}", self.log_check_data().bits()),
-            )
+            .field("log_check_data", &self.log_check_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_CHECK_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The special check data, when write this special data, it will trigger logging."]
     #[inline(always)]
diff --git a/esp32h2/src/mem_monitor/log_data_mask.rs b/esp32h2/src/mem_monitor/log_data_mask.rs
index 581d53ba4d..94cb25cd6e 100644
--- a/esp32h2/src/mem_monitor/log_data_mask.rs
+++ b/esp32h2/src/mem_monitor/log_data_mask.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_DATA_MASK")
-            .field(
-                "log_data_mask",
-                &format_args!("{}", self.log_data_mask().bits()),
-            )
+            .field("log_data_mask", &self.log_data_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_DATA_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 mask second byte, and so on."]
     #[inline(always)]
diff --git a/esp32h2/src/mem_monitor/log_max.rs b/esp32h2/src/mem_monitor/log_max.rs
index 4576677667..536c7de8c0 100644
--- a/esp32h2/src/mem_monitor/log_max.rs
+++ b/esp32h2/src/mem_monitor/log_max.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MAX")
-            .field("log_max", &format_args!("{}", self.log_max().bits()))
+            .field("log_max", &self.log_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - the max address of log range"]
     #[inline(always)]
diff --git a/esp32h2/src/mem_monitor/log_mem_current_addr.rs b/esp32h2/src/mem_monitor/log_mem_current_addr.rs
index 0b384d7203..4e8fa98fd0 100644
--- a/esp32h2/src/mem_monitor/log_mem_current_addr.rs
+++ b/esp32h2/src/mem_monitor/log_mem_current_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_CURRENT_ADDR")
-            .field(
-                "log_mem_current_addr",
-                &format_args!("{}", self.log_mem_current_addr().bits()),
-            )
+            .field("log_mem_current_addr", &self.log_mem_current_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_CURRENT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "current writing address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`log_mem_current_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOG_MEM_CURRENT_ADDR_SPEC;
 impl crate::RegisterSpec for LOG_MEM_CURRENT_ADDR_SPEC {
diff --git a/esp32h2/src/mem_monitor/log_mem_end.rs b/esp32h2/src/mem_monitor/log_mem_end.rs
index db04d1a955..d19a4b9b47 100644
--- a/esp32h2/src/mem_monitor/log_mem_end.rs
+++ b/esp32h2/src/mem_monitor/log_mem_end.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_END")
-            .field(
-                "log_mem_end",
-                &format_args!("{}", self.log_mem_end().bits()),
-            )
+            .field("log_mem_end", &self.log_mem_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_END_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - the end address of writing logging message"]
     #[inline(always)]
diff --git a/esp32h2/src/mem_monitor/log_mem_full_flag.rs b/esp32h2/src/mem_monitor/log_mem_full_flag.rs
index a9067171cf..32eac4e396 100644
--- a/esp32h2/src/mem_monitor/log_mem_full_flag.rs
+++ b/esp32h2/src/mem_monitor/log_mem_full_flag.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_FULL_FLAG")
-            .field(
-                "log_mem_full_flag",
-                &format_args!("{}", self.log_mem_full_flag().bit()),
-            )
+            .field("log_mem_full_flag", &self.log_mem_full_flag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_FULL_FLAG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG"]
     #[inline(always)]
diff --git a/esp32h2/src/mem_monitor/log_mem_start.rs b/esp32h2/src/mem_monitor/log_mem_start.rs
index 41cb69417b..80997cea12 100644
--- a/esp32h2/src/mem_monitor/log_mem_start.rs
+++ b/esp32h2/src/mem_monitor/log_mem_start.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_START")
-            .field(
-                "log_mem_start",
-                &format_args!("{}", self.log_mem_start().bits()),
-            )
+            .field("log_mem_start", &self.log_mem_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_START_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - the start address of writing logging message"]
     #[inline(always)]
diff --git a/esp32h2/src/mem_monitor/log_min.rs b/esp32h2/src/mem_monitor/log_min.rs
index 4c4a2fc050..cd8bed7509 100644
--- a/esp32h2/src/mem_monitor/log_min.rs
+++ b/esp32h2/src/mem_monitor/log_min.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MIN")
-            .field("log_min", &format_args!("{}", self.log_min().bits()))
+            .field("log_min", &self.log_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - the min address of log range"]
     #[inline(always)]
diff --git a/esp32h2/src/mem_monitor/log_setting.rs b/esp32h2/src/mem_monitor/log_setting.rs
index 16d8b3101d..24ed494a79 100644
--- a/esp32h2/src/mem_monitor/log_setting.rs
+++ b/esp32h2/src/mem_monitor/log_setting.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_SETTING")
-            .field("log_ena", &format_args!("{}", self.log_ena().bits()))
-            .field("log_mode", &format_args!("{}", self.log_mode().bits()))
-            .field(
-                "log_mem_loop_enable",
-                &format_args!("{}", self.log_mem_loop_enable().bit()),
-            )
+            .field("log_ena", &self.log_ena())
+            .field("log_mode", &self.log_mode())
+            .field("log_mem_loop_enable", &self.log_mem_loop_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_SETTING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.823 don't support lp-cpu"]
     #[inline(always)]
diff --git a/esp32h2/src/modem_lpcon/clk_conf.rs b/esp32h2/src/modem_lpcon/clk_conf.rs
index 850748bf8a..e5b6c0c27f 100644
--- a/esp32h2/src/modem_lpcon/clk_conf.rs
+++ b/esp32h2/src/modem_lpcon/clk_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field("clk_coex_en", &format_args!("{}", self.clk_coex_en().bit()))
-            .field(
-                "clk_i2c_mst_en",
-                &format_args!("{}", self.clk_i2c_mst_en().bit()),
-            )
-            .field(
-                "clk_fe_mem_en",
-                &format_args!("{}", self.clk_fe_mem_en().bit()),
-            )
+            .field("clk_coex_en", &self.clk_coex_en())
+            .field("clk_i2c_mst_en", &self.clk_i2c_mst_en())
+            .field("clk_fe_mem_en", &self.clk_fe_mem_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
diff --git a/esp32h2/src/modem_lpcon/clk_conf_force_on.rs b/esp32h2/src/modem_lpcon/clk_conf_force_on.rs
index 5b94c46b4d..2f0c7ee62a 100644
--- a/esp32h2/src/modem_lpcon/clk_conf_force_on.rs
+++ b/esp32h2/src/modem_lpcon/clk_conf_force_on.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF_FORCE_ON")
-            .field("clk_coex_fo", &format_args!("{}", self.clk_coex_fo().bit()))
-            .field(
-                "clk_i2c_mst_fo",
-                &format_args!("{}", self.clk_i2c_mst_fo().bit()),
-            )
-            .field(
-                "clk_fe_mem_fo",
-                &format_args!("{}", self.clk_fe_mem_fo().bit()),
-            )
+            .field("clk_coex_fo", &self.clk_coex_fo())
+            .field("clk_i2c_mst_fo", &self.clk_i2c_mst_fo())
+            .field("clk_fe_mem_fo", &self.clk_fe_mem_fo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_FORCE_ON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
diff --git a/esp32h2/src/modem_lpcon/coex_lp_clk_conf.rs b/esp32h2/src/modem_lpcon/coex_lp_clk_conf.rs
index bc48d3f96a..2f600a7b43 100644
--- a/esp32h2/src/modem_lpcon/coex_lp_clk_conf.rs
+++ b/esp32h2/src/modem_lpcon/coex_lp_clk_conf.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COEX_LP_CLK_CONF")
-            .field(
-                "clk_coex_lp_sel_osc_slow",
-                &format_args!("{}", self.clk_coex_lp_sel_osc_slow().bit()),
-            )
-            .field(
-                "clk_coex_lp_sel_osc_fast",
-                &format_args!("{}", self.clk_coex_lp_sel_osc_fast().bit()),
-            )
-            .field(
-                "clk_coex_lp_sel_xtal",
-                &format_args!("{}", self.clk_coex_lp_sel_xtal().bit()),
-            )
-            .field(
-                "clk_coex_lp_sel_xtal32k",
-                &format_args!("{}", self.clk_coex_lp_sel_xtal32k().bit()),
-            )
-            .field(
-                "clk_coex_lp_div_num",
-                &format_args!("{}", self.clk_coex_lp_div_num().bits()),
-            )
+            .field("clk_coex_lp_sel_osc_slow", &self.clk_coex_lp_sel_osc_slow())
+            .field("clk_coex_lp_sel_osc_fast", &self.clk_coex_lp_sel_osc_fast())
+            .field("clk_coex_lp_sel_xtal", &self.clk_coex_lp_sel_xtal())
+            .field("clk_coex_lp_sel_xtal32k", &self.clk_coex_lp_sel_xtal32k())
+            .field("clk_coex_lp_div_num", &self.clk_coex_lp_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COEX_LP_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32h2/src/modem_lpcon/date.rs b/esp32h2/src/modem_lpcon/date.rs
index 114d9d52e8..8a38888ff9 100644
--- a/esp32h2/src/modem_lpcon/date.rs
+++ b/esp32h2/src/modem_lpcon/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/modem_lpcon/mem_conf.rs b/esp32h2/src/modem_lpcon/mem_conf.rs
index 8e1397606d..ad13ff3492 100644
--- a/esp32h2/src/modem_lpcon/mem_conf.rs
+++ b/esp32h2/src/modem_lpcon/mem_conf.rs
@@ -116,63 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field(
-                "agc_mem_force_pu",
-                &format_args!("{}", self.agc_mem_force_pu().bit()),
-            )
-            .field(
-                "agc_mem_force_pd",
-                &format_args!("{}", self.agc_mem_force_pd().bit()),
-            )
-            .field(
-                "pbus_mem_force_pu",
-                &format_args!("{}", self.pbus_mem_force_pu().bit()),
-            )
-            .field(
-                "pbus_mem_force_pd",
-                &format_args!("{}", self.pbus_mem_force_pd().bit()),
-            )
-            .field(
-                "i2c_mst_mem_force_pu",
-                &format_args!("{}", self.i2c_mst_mem_force_pu().bit()),
-            )
-            .field(
-                "i2c_mst_mem_force_pd",
-                &format_args!("{}", self.i2c_mst_mem_force_pd().bit()),
-            )
-            .field(
-                "chan_freq_mem_force_pu",
-                &format_args!("{}", self.chan_freq_mem_force_pu().bit()),
-            )
-            .field(
-                "chan_freq_mem_force_pd",
-                &format_args!("{}", self.chan_freq_mem_force_pd().bit()),
-            )
-            .field(
-                "modem_pwr_mem_wp",
-                &format_args!("{}", self.modem_pwr_mem_wp().bits()),
-            )
-            .field(
-                "modem_pwr_mem_wa",
-                &format_args!("{}", self.modem_pwr_mem_wa().bits()),
-            )
-            .field(
-                "modem_pwr_mem_ra",
-                &format_args!("{}", self.modem_pwr_mem_ra().bits()),
-            )
-            .field(
-                "modem_pwr_mem_rm",
-                &format_args!("{}", self.modem_pwr_mem_rm().bits()),
-            )
+            .field("agc_mem_force_pu", &self.agc_mem_force_pu())
+            .field("agc_mem_force_pd", &self.agc_mem_force_pd())
+            .field("pbus_mem_force_pu", &self.pbus_mem_force_pu())
+            .field("pbus_mem_force_pd", &self.pbus_mem_force_pd())
+            .field("i2c_mst_mem_force_pu", &self.i2c_mst_mem_force_pu())
+            .field("i2c_mst_mem_force_pd", &self.i2c_mst_mem_force_pd())
+            .field("chan_freq_mem_force_pu", &self.chan_freq_mem_force_pu())
+            .field("chan_freq_mem_force_pd", &self.chan_freq_mem_force_pd())
+            .field("modem_pwr_mem_wp", &self.modem_pwr_mem_wp())
+            .field("modem_pwr_mem_wa", &self.modem_pwr_mem_wa())
+            .field("modem_pwr_mem_ra", &self.modem_pwr_mem_ra())
+            .field("modem_pwr_mem_rm", &self.modem_pwr_mem_rm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
diff --git a/esp32h2/src/modem_lpcon/test_conf.rs b/esp32h2/src/modem_lpcon/test_conf.rs
index b63a855383..c43a494741 100644
--- a/esp32h2/src/modem_lpcon/test_conf.rs
+++ b/esp32h2/src/modem_lpcon/test_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEST_CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32h2/src/modem_lpcon/tick_conf.rs b/esp32h2/src/modem_lpcon/tick_conf.rs
index 01dda35772..e4a900fe47 100644
--- a/esp32h2/src/modem_lpcon/tick_conf.rs
+++ b/esp32h2/src/modem_lpcon/tick_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TICK_CONF")
-            .field(
-                "pwr_tick_target",
-                &format_args!("{}", self.pwr_tick_target().bits()),
-            )
+            .field("pwr_tick_target", &self.pwr_tick_target())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TICK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
diff --git a/esp32h2/src/modem_syscon/clk_conf.rs b/esp32h2/src/modem_syscon/clk_conf.rs
index 501ec9e9f2..9e6e36552d 100644
--- a/esp32h2/src/modem_syscon/clk_conf.rs
+++ b/esp32h2/src/modem_syscon/clk_conf.rs
@@ -107,56 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field("clk_etm_en", &format_args!("{}", self.clk_etm_en().bit()))
-            .field(
-                "clk_zb_apb_en",
-                &format_args!("{}", self.clk_zb_apb_en().bit()),
-            )
-            .field(
-                "clk_zb_mac_en",
-                &format_args!("{}", self.clk_zb_mac_en().bit()),
-            )
-            .field(
-                "clk_modem_sec_ecb_en",
-                &format_args!("{}", self.clk_modem_sec_ecb_en().bit()),
-            )
-            .field(
-                "clk_modem_sec_ccm_en",
-                &format_args!("{}", self.clk_modem_sec_ccm_en().bit()),
-            )
-            .field(
-                "clk_modem_sec_bah_en",
-                &format_args!("{}", self.clk_modem_sec_bah_en().bit()),
-            )
-            .field(
-                "clk_modem_sec_apb_en",
-                &format_args!("{}", self.clk_modem_sec_apb_en().bit()),
-            )
-            .field(
-                "clk_modem_sec_en",
-                &format_args!("{}", self.clk_modem_sec_en().bit()),
-            )
-            .field(
-                "clk_ble_timer_apb_en",
-                &format_args!("{}", self.clk_ble_timer_apb_en().bit()),
-            )
-            .field(
-                "clk_ble_timer_en",
-                &format_args!("{}", self.clk_ble_timer_en().bit()),
-            )
-            .field(
-                "clk_data_dump_en",
-                &format_args!("{}", self.clk_data_dump_en().bit()),
-            )
+            .field("clk_etm_en", &self.clk_etm_en())
+            .field("clk_zb_apb_en", &self.clk_zb_apb_en())
+            .field("clk_zb_mac_en", &self.clk_zb_mac_en())
+            .field("clk_modem_sec_ecb_en", &self.clk_modem_sec_ecb_en())
+            .field("clk_modem_sec_ccm_en", &self.clk_modem_sec_ccm_en())
+            .field("clk_modem_sec_bah_en", &self.clk_modem_sec_bah_en())
+            .field("clk_modem_sec_apb_en", &self.clk_modem_sec_apb_en())
+            .field("clk_modem_sec_en", &self.clk_modem_sec_en())
+            .field("clk_ble_timer_apb_en", &self.clk_ble_timer_apb_en())
+            .field("clk_ble_timer_en", &self.clk_ble_timer_en())
+            .field("clk_data_dump_en", &self.clk_data_dump_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21"]
     #[inline(always)]
diff --git a/esp32h2/src/modem_syscon/clk_conf1.rs b/esp32h2/src/modem_syscon/clk_conf1.rs
index f1920b9619..e5183ddada 100644
--- a/esp32h2/src/modem_syscon/clk_conf1.rs
+++ b/esp32h2/src/modem_syscon/clk_conf1.rs
@@ -71,40 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF1")
-            .field(
-                "clk_fe_16m_en",
-                &format_args!("{}", self.clk_fe_16m_en().bit()),
-            )
-            .field(
-                "clk_fe_32m_en",
-                &format_args!("{}", self.clk_fe_32m_en().bit()),
-            )
-            .field(
-                "clk_fe_sdm_en",
-                &format_args!("{}", self.clk_fe_sdm_en().bit()),
-            )
-            .field(
-                "clk_fe_adc_en",
-                &format_args!("{}", self.clk_fe_adc_en().bit()),
-            )
-            .field(
-                "clk_fe_apb_en",
-                &format_args!("{}", self.clk_fe_apb_en().bit()),
-            )
-            .field(
-                "clk_bt_apb_en",
-                &format_args!("{}", self.clk_bt_apb_en().bit()),
-            )
-            .field("clk_bt_en", &format_args!("{}", self.clk_bt_en().bit()))
+            .field("clk_fe_16m_en", &self.clk_fe_16m_en())
+            .field("clk_fe_32m_en", &self.clk_fe_32m_en())
+            .field("clk_fe_sdm_en", &self.clk_fe_sdm_en())
+            .field("clk_fe_adc_en", &self.clk_fe_adc_en())
+            .field("clk_fe_apb_en", &self.clk_fe_apb_en())
+            .field("clk_bt_apb_en", &self.clk_bt_apb_en())
+            .field("clk_bt_en", &self.clk_bt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12"]
     #[inline(always)]
diff --git a/esp32h2/src/modem_syscon/clk_conf1_force_on.rs b/esp32h2/src/modem_syscon/clk_conf1_force_on.rs
index d9988c3106..5de706e9be 100644
--- a/esp32h2/src/modem_syscon/clk_conf1_force_on.rs
+++ b/esp32h2/src/modem_syscon/clk_conf1_force_on.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF1_FORCE_ON")
-            .field("clk_fe_fo", &format_args!("{}", self.clk_fe_fo().bit()))
-            .field("clk_bt_fo", &format_args!("{}", self.clk_bt_fo().bit()))
+            .field("clk_fe_fo", &self.clk_fe_fo())
+            .field("clk_bt_fo", &self.clk_bt_fo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF1_FORCE_ON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16"]
     #[inline(always)]
diff --git a/esp32h2/src/modem_syscon/clk_conf_force_on.rs b/esp32h2/src/modem_syscon/clk_conf_force_on.rs
index ff4a94970e..6af66e319e 100644
--- a/esp32h2/src/modem_syscon/clk_conf_force_on.rs
+++ b/esp32h2/src/modem_syscon/clk_conf_force_on.rs
@@ -53,29 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF_FORCE_ON")
-            .field("clk_etm_fo", &format_args!("{}", self.clk_etm_fo().bit()))
-            .field("clk_zb_fo", &format_args!("{}", self.clk_zb_fo().bit()))
-            .field(
-                "clk_modem_sec_fo",
-                &format_args!("{}", self.clk_modem_sec_fo().bit()),
-            )
-            .field(
-                "clk_ble_timer_fo",
-                &format_args!("{}", self.clk_ble_timer_fo().bit()),
-            )
-            .field(
-                "clk_data_dump_fo",
-                &format_args!("{}", self.clk_data_dump_fo().bit()),
-            )
+            .field("clk_etm_fo", &self.clk_etm_fo())
+            .field("clk_zb_fo", &self.clk_zb_fo())
+            .field("clk_modem_sec_fo", &self.clk_modem_sec_fo())
+            .field("clk_ble_timer_fo", &self.clk_ble_timer_fo())
+            .field("clk_data_dump_fo", &self.clk_data_dump_fo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_FORCE_ON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 22"]
     #[inline(always)]
diff --git a/esp32h2/src/modem_syscon/date.rs b/esp32h2/src/modem_syscon/date.rs
index d2073d425b..f5e9ecdc03 100644
--- a/esp32h2/src/modem_syscon/date.rs
+++ b/esp32h2/src/modem_syscon/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/modem_syscon/mem_conf.rs b/esp32h2/src/modem_syscon/mem_conf.rs
index 776db486ac..fd9f18e9b7 100644
--- a/esp32h2/src/modem_syscon/mem_conf.rs
+++ b/esp32h2/src/modem_syscon/mem_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field(
-                "modem_mem_wp",
-                &format_args!("{}", self.modem_mem_wp().bits()),
-            )
-            .field(
-                "modem_mem_wa",
-                &format_args!("{}", self.modem_mem_wa().bits()),
-            )
-            .field(
-                "modem_mem_ra",
-                &format_args!("{}", self.modem_mem_ra().bits()),
-            )
+            .field("modem_mem_wp", &self.modem_mem_wp())
+            .field("modem_mem_wa", &self.modem_mem_wa())
+            .field("modem_mem_ra", &self.modem_mem_ra())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32h2/src/modem_syscon/modem_rst_conf.rs b/esp32h2/src/modem_syscon/modem_rst_conf.rs
index 99a24b333f..96a7e54f09 100644
--- a/esp32h2/src/modem_syscon/modem_rst_conf.rs
+++ b/esp32h2/src/modem_syscon/modem_rst_conf.rs
@@ -125,52 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODEM_RST_CONF")
-            .field("rst_fe", &format_args!("{}", self.rst_fe().bit()))
-            .field(
-                "rst_btmac_apb",
-                &format_args!("{}", self.rst_btmac_apb().bit()),
-            )
-            .field("rst_btmac", &format_args!("{}", self.rst_btmac().bit()))
-            .field(
-                "rst_btbb_apb",
-                &format_args!("{}", self.rst_btbb_apb().bit()),
-            )
-            .field("rst_btbb", &format_args!("{}", self.rst_btbb().bit()))
-            .field("rst_etm", &format_args!("{}", self.rst_etm().bit()))
-            .field("rst_zbmac", &format_args!("{}", self.rst_zbmac().bit()))
-            .field(
-                "rst_modem_ecb",
-                &format_args!("{}", self.rst_modem_ecb().bit()),
-            )
-            .field(
-                "rst_modem_ccm",
-                &format_args!("{}", self.rst_modem_ccm().bit()),
-            )
-            .field(
-                "rst_modem_bah",
-                &format_args!("{}", self.rst_modem_bah().bit()),
-            )
-            .field(
-                "rst_modem_sec",
-                &format_args!("{}", self.rst_modem_sec().bit()),
-            )
-            .field(
-                "rst_ble_timer",
-                &format_args!("{}", self.rst_ble_timer().bit()),
-            )
-            .field(
-                "rst_data_dump",
-                &format_args!("{}", self.rst_data_dump().bit()),
-            )
+            .field("rst_fe", &self.rst_fe())
+            .field("rst_btmac_apb", &self.rst_btmac_apb())
+            .field("rst_btmac", &self.rst_btmac())
+            .field("rst_btbb_apb", &self.rst_btbb_apb())
+            .field("rst_btbb", &self.rst_btbb())
+            .field("rst_etm", &self.rst_etm())
+            .field("rst_zbmac", &self.rst_zbmac())
+            .field("rst_modem_ecb", &self.rst_modem_ecb())
+            .field("rst_modem_ccm", &self.rst_modem_ccm())
+            .field("rst_modem_bah", &self.rst_modem_bah())
+            .field("rst_modem_sec", &self.rst_modem_sec())
+            .field("rst_ble_timer", &self.rst_ble_timer())
+            .field("rst_data_dump", &self.rst_data_dump())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODEM_RST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 14"]
     #[inline(always)]
diff --git a/esp32h2/src/modem_syscon/test_conf.rs b/esp32h2/src/modem_syscon/test_conf.rs
index b63a855383..c43a494741 100644
--- a/esp32h2/src/modem_syscon/test_conf.rs
+++ b/esp32h2/src/modem_syscon/test_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEST_CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32h2/src/otp_debug/apb2otp_en.rs b/esp32h2/src/otp_debug/apb2otp_en.rs
index 71db776175..f3345951d1 100644
--- a/esp32h2/src/otp_debug/apb2otp_en.rs
+++ b/esp32h2/src/otp_debug/apb2otp_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_EN")
-            .field("apb2otp_en", &format_args!("{}", self.apb2otp_en().bit()))
+            .field("apb2otp_en", &self.apb2otp_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Debug mode enable signal."]
     #[inline(always)]
diff --git a/esp32h2/src/otp_debug/blk0_backup1_w1.rs b/esp32h2/src/otp_debug/blk0_backup1_w1.rs
index bb690710ea..0b717aaf40 100644
--- a/esp32h2/src/otp_debug/blk0_backup1_w1.rs
+++ b/esp32h2/src/otp_debug/blk0_backup1_w1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP1_W1")
             .field(
                 "otp_bebug_block0_backup1_w1",
-                &format_args!("{}", self.otp_bebug_block0_backup1_w1().bits()),
+                &self.otp_bebug_block0_backup1_w1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP1_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup1_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP1_W1_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP1_W1_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup1_w2.rs b/esp32h2/src/otp_debug/blk0_backup1_w2.rs
index 4bdf71768a..6975d666bb 100644
--- a/esp32h2/src/otp_debug/blk0_backup1_w2.rs
+++ b/esp32h2/src/otp_debug/blk0_backup1_w2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP1_W2")
             .field(
                 "otp_bebug_block0_backup1_w2",
-                &format_args!("{}", self.otp_bebug_block0_backup1_w2().bits()),
+                &self.otp_bebug_block0_backup1_w2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP1_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup1_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP1_W2_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP1_W2_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup1_w3.rs b/esp32h2/src/otp_debug/blk0_backup1_w3.rs
index a8bdfa79ec..a5c0f3efb4 100644
--- a/esp32h2/src/otp_debug/blk0_backup1_w3.rs
+++ b/esp32h2/src/otp_debug/blk0_backup1_w3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP1_W3")
             .field(
                 "otp_bebug_block0_backup1_w3",
-                &format_args!("{}", self.otp_bebug_block0_backup1_w3().bits()),
+                &self.otp_bebug_block0_backup1_w3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP1_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup1_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP1_W3_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP1_W3_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup1_w4.rs b/esp32h2/src/otp_debug/blk0_backup1_w4.rs
index 023e7ab5d6..12c11d397f 100644
--- a/esp32h2/src/otp_debug/blk0_backup1_w4.rs
+++ b/esp32h2/src/otp_debug/blk0_backup1_w4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP1_W4")
             .field(
                 "otp_bebug_block0_backup1_w4",
-                &format_args!("{}", self.otp_bebug_block0_backup1_w4().bits()),
+                &self.otp_bebug_block0_backup1_w4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP1_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup1_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP1_W4_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP1_W4_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup1_w5.rs b/esp32h2/src/otp_debug/blk0_backup1_w5.rs
index e1f0ef2a77..e59a6e28c1 100644
--- a/esp32h2/src/otp_debug/blk0_backup1_w5.rs
+++ b/esp32h2/src/otp_debug/blk0_backup1_w5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP1_W5")
             .field(
                 "otp_bebug_block0_backup1_w5",
-                &format_args!("{}", self.otp_bebug_block0_backup1_w5().bits()),
+                &self.otp_bebug_block0_backup1_w5(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP1_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup1_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP1_W5_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP1_W5_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup2_w1.rs b/esp32h2/src/otp_debug/blk0_backup2_w1.rs
index d1f1636d37..f41383b39e 100644
--- a/esp32h2/src/otp_debug/blk0_backup2_w1.rs
+++ b/esp32h2/src/otp_debug/blk0_backup2_w1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP2_W1")
             .field(
                 "otp_bebug_block0_backup2_w1",
-                &format_args!("{}", self.otp_bebug_block0_backup2_w1().bits()),
+                &self.otp_bebug_block0_backup2_w1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP2_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup2_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP2_W1_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP2_W1_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup2_w2.rs b/esp32h2/src/otp_debug/blk0_backup2_w2.rs
index ec80a6e9ae..6ba3fd7286 100644
--- a/esp32h2/src/otp_debug/blk0_backup2_w2.rs
+++ b/esp32h2/src/otp_debug/blk0_backup2_w2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP2_W2")
             .field(
                 "otp_bebug_block0_backup2_w2",
-                &format_args!("{}", self.otp_bebug_block0_backup2_w2().bits()),
+                &self.otp_bebug_block0_backup2_w2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP2_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup2_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP2_W2_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP2_W2_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup2_w3.rs b/esp32h2/src/otp_debug/blk0_backup2_w3.rs
index 11f0f144ea..e9986929de 100644
--- a/esp32h2/src/otp_debug/blk0_backup2_w3.rs
+++ b/esp32h2/src/otp_debug/blk0_backup2_w3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP2_W3")
             .field(
                 "otp_bebug_block0_backup2_w3",
-                &format_args!("{}", self.otp_bebug_block0_backup2_w3().bits()),
+                &self.otp_bebug_block0_backup2_w3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP2_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup2_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP2_W3_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP2_W3_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup2_w4.rs b/esp32h2/src/otp_debug/blk0_backup2_w4.rs
index c605e28011..f653cc13ef 100644
--- a/esp32h2/src/otp_debug/blk0_backup2_w4.rs
+++ b/esp32h2/src/otp_debug/blk0_backup2_w4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP2_W4")
             .field(
                 "otp_bebug_block0_backup2_w4",
-                &format_args!("{}", self.otp_bebug_block0_backup2_w4().bits()),
+                &self.otp_bebug_block0_backup2_w4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP2_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup2_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP2_W4_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP2_W4_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup2_w5.rs b/esp32h2/src/otp_debug/blk0_backup2_w5.rs
index 9b432673f7..001059fe6c 100644
--- a/esp32h2/src/otp_debug/blk0_backup2_w5.rs
+++ b/esp32h2/src/otp_debug/blk0_backup2_w5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP2_W5")
             .field(
                 "otp_bebug_block0_backup2_w5",
-                &format_args!("{}", self.otp_bebug_block0_backup2_w5().bits()),
+                &self.otp_bebug_block0_backup2_w5(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP2_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup2_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP2_W5_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP2_W5_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup3_w1.rs b/esp32h2/src/otp_debug/blk0_backup3_w1.rs
index 98b3d5a981..6e6bc21e78 100644
--- a/esp32h2/src/otp_debug/blk0_backup3_w1.rs
+++ b/esp32h2/src/otp_debug/blk0_backup3_w1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP3_W1")
             .field(
                 "otp_bebug_block0_backup3_w1",
-                &format_args!("{}", self.otp_bebug_block0_backup3_w1().bits()),
+                &self.otp_bebug_block0_backup3_w1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP3_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register12.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup3_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP3_W1_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP3_W1_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup3_w2.rs b/esp32h2/src/otp_debug/blk0_backup3_w2.rs
index e1c8dd4fff..c470d2d3fe 100644
--- a/esp32h2/src/otp_debug/blk0_backup3_w2.rs
+++ b/esp32h2/src/otp_debug/blk0_backup3_w2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP3_W2")
             .field(
                 "otp_bebug_block0_backup3_w2",
-                &format_args!("{}", self.otp_bebug_block0_backup3_w2().bits()),
+                &self.otp_bebug_block0_backup3_w2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP3_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register13.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup3_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP3_W2_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP3_W2_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup3_w3.rs b/esp32h2/src/otp_debug/blk0_backup3_w3.rs
index a21af93fa2..5e6b817596 100644
--- a/esp32h2/src/otp_debug/blk0_backup3_w3.rs
+++ b/esp32h2/src/otp_debug/blk0_backup3_w3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP3_W3")
             .field(
                 "otp_bebug_block0_backup3_w3",
-                &format_args!("{}", self.otp_bebug_block0_backup3_w3().bits()),
+                &self.otp_bebug_block0_backup3_w3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP3_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register14.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup3_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP3_W3_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP3_W3_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup3_w4.rs b/esp32h2/src/otp_debug/blk0_backup3_w4.rs
index 0d6cb57263..f4eabb25c6 100644
--- a/esp32h2/src/otp_debug/blk0_backup3_w4.rs
+++ b/esp32h2/src/otp_debug/blk0_backup3_w4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP3_W4")
             .field(
                 "otp_bebug_block0_backup3_w4",
-                &format_args!("{}", self.otp_bebug_block0_backup3_w4().bits()),
+                &self.otp_bebug_block0_backup3_w4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP3_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register15.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup3_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP3_W4_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP3_W4_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup3_w5.rs b/esp32h2/src/otp_debug/blk0_backup3_w5.rs
index 2fcf502f55..acebb2ce90 100644
--- a/esp32h2/src/otp_debug/blk0_backup3_w5.rs
+++ b/esp32h2/src/otp_debug/blk0_backup3_w5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP3_W5")
             .field(
                 "otp_bebug_block0_backup3_w5",
-                &format_args!("{}", self.otp_bebug_block0_backup3_w5().bits()),
+                &self.otp_bebug_block0_backup3_w5(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP3_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register16.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup3_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP3_W5_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP3_W5_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup4_w1.rs b/esp32h2/src/otp_debug/blk0_backup4_w1.rs
index 480b7dfaee..3d5df84fc7 100644
--- a/esp32h2/src/otp_debug/blk0_backup4_w1.rs
+++ b/esp32h2/src/otp_debug/blk0_backup4_w1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP4_W1")
             .field(
                 "otp_bebug_block0_backup4_w1",
-                &format_args!("{}", self.otp_bebug_block0_backup4_w1().bits()),
+                &self.otp_bebug_block0_backup4_w1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP4_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register17.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup4_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP4_W1_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP4_W1_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup4_w2.rs b/esp32h2/src/otp_debug/blk0_backup4_w2.rs
index 662b662a52..09f621fc56 100644
--- a/esp32h2/src/otp_debug/blk0_backup4_w2.rs
+++ b/esp32h2/src/otp_debug/blk0_backup4_w2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP4_W2")
             .field(
                 "otp_bebug_block0_backup4_w2",
-                &format_args!("{}", self.otp_bebug_block0_backup4_w2().bits()),
+                &self.otp_bebug_block0_backup4_w2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP4_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register18.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup4_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP4_W2_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP4_W2_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup4_w3.rs b/esp32h2/src/otp_debug/blk0_backup4_w3.rs
index 43ccd5ab27..e33fc540d5 100644
--- a/esp32h2/src/otp_debug/blk0_backup4_w3.rs
+++ b/esp32h2/src/otp_debug/blk0_backup4_w3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP4_W3")
             .field(
                 "otp_bebug_block0_backup4_w3",
-                &format_args!("{}", self.otp_bebug_block0_backup4_w3().bits()),
+                &self.otp_bebug_block0_backup4_w3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP4_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register19.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup4_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP4_W3_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP4_W3_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup4_w4.rs b/esp32h2/src/otp_debug/blk0_backup4_w4.rs
index 8a2f5fccc4..5af390b1c4 100644
--- a/esp32h2/src/otp_debug/blk0_backup4_w4.rs
+++ b/esp32h2/src/otp_debug/blk0_backup4_w4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP4_W4")
             .field(
                 "otp_bebug_block0_backup4_w4",
-                &format_args!("{}", self.otp_bebug_block0_backup4_w4().bits()),
+                &self.otp_bebug_block0_backup4_w4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP4_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register20.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup4_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP4_W4_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP4_W4_SPEC {
diff --git a/esp32h2/src/otp_debug/blk0_backup4_w5.rs b/esp32h2/src/otp_debug/blk0_backup4_w5.rs
index 0707eb46ff..2ed46520ea 100644
--- a/esp32h2/src/otp_debug/blk0_backup4_w5.rs
+++ b/esp32h2/src/otp_debug/blk0_backup4_w5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BLK0_BACKUP4_W5")
             .field(
                 "otp_bebug_block0_backup4_w5",
-                &format_args!("{}", self.otp_bebug_block0_backup4_w5().bits()),
+                &self.otp_bebug_block0_backup4_w5(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK0_BACKUP4_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register21.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk0_backup4_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK0_BACKUP4_W5_SPEC;
 impl crate::RegisterSpec for BLK0_BACKUP4_W5_SPEC {
diff --git a/esp32h2/src/otp_debug/blk10_w1.rs b/esp32h2/src/otp_debug/blk10_w1.rs
index 98cf693df2..7229a0497d 100644
--- a/esp32h2/src/otp_debug/blk10_w1.rs
+++ b/esp32h2/src/otp_debug/blk10_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W1")
-            .field("block10_w1", &format_args!("{}", self.block10_w1().bits()))
+            .field("block10_w1", &self.block10_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W1_SPEC;
 impl crate::RegisterSpec for BLK10_W1_SPEC {
diff --git a/esp32h2/src/otp_debug/blk10_w10.rs b/esp32h2/src/otp_debug/blk10_w10.rs
index eb9915b767..cc48585332 100644
--- a/esp32h2/src/otp_debug/blk10_w10.rs
+++ b/esp32h2/src/otp_debug/blk10_w10.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W10")
-            .field(
-                "block19_w10",
-                &format_args!("{}", self.block19_w10().bits()),
-            )
+            .field("block19_w10", &self.block19_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W10_SPEC;
 impl crate::RegisterSpec for BLK10_W10_SPEC {
diff --git a/esp32h2/src/otp_debug/blk10_w11.rs b/esp32h2/src/otp_debug/blk10_w11.rs
index f019dea81b..cabf753006 100644
--- a/esp32h2/src/otp_debug/blk10_w11.rs
+++ b/esp32h2/src/otp_debug/blk10_w11.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W11")
-            .field(
-                "block10_w11",
-                &format_args!("{}", self.block10_w11().bits()),
-            )
+            .field("block10_w11", &self.block10_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W11_SPEC;
 impl crate::RegisterSpec for BLK10_W11_SPEC {
diff --git a/esp32h2/src/otp_debug/blk10_w2.rs b/esp32h2/src/otp_debug/blk10_w2.rs
index 61c39a9f94..06835e9708 100644
--- a/esp32h2/src/otp_debug/blk10_w2.rs
+++ b/esp32h2/src/otp_debug/blk10_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W2")
-            .field("block10_w2", &format_args!("{}", self.block10_w2().bits()))
+            .field("block10_w2", &self.block10_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W2_SPEC;
 impl crate::RegisterSpec for BLK10_W2_SPEC {
diff --git a/esp32h2/src/otp_debug/blk10_w3.rs b/esp32h2/src/otp_debug/blk10_w3.rs
index 739f43ceae..383028ffd1 100644
--- a/esp32h2/src/otp_debug/blk10_w3.rs
+++ b/esp32h2/src/otp_debug/blk10_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W3")
-            .field("block10_w3", &format_args!("{}", self.block10_w3().bits()))
+            .field("block10_w3", &self.block10_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W3_SPEC;
 impl crate::RegisterSpec for BLK10_W3_SPEC {
diff --git a/esp32h2/src/otp_debug/blk10_w4.rs b/esp32h2/src/otp_debug/blk10_w4.rs
index ee094acb6e..fd0d59110a 100644
--- a/esp32h2/src/otp_debug/blk10_w4.rs
+++ b/esp32h2/src/otp_debug/blk10_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W4")
-            .field("block10_w4", &format_args!("{}", self.block10_w4().bits()))
+            .field("block10_w4", &self.block10_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W4_SPEC;
 impl crate::RegisterSpec for BLK10_W4_SPEC {
diff --git a/esp32h2/src/otp_debug/blk10_w5.rs b/esp32h2/src/otp_debug/blk10_w5.rs
index c25230180d..1289e89f36 100644
--- a/esp32h2/src/otp_debug/blk10_w5.rs
+++ b/esp32h2/src/otp_debug/blk10_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W5")
-            .field("block10_w5", &format_args!("{}", self.block10_w5().bits()))
+            .field("block10_w5", &self.block10_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W5_SPEC;
 impl crate::RegisterSpec for BLK10_W5_SPEC {
diff --git a/esp32h2/src/otp_debug/blk10_w6.rs b/esp32h2/src/otp_debug/blk10_w6.rs
index 1f64df8f53..8837441fb1 100644
--- a/esp32h2/src/otp_debug/blk10_w6.rs
+++ b/esp32h2/src/otp_debug/blk10_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W6")
-            .field("block10_w6", &format_args!("{}", self.block10_w6().bits()))
+            .field("block10_w6", &self.block10_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W6_SPEC;
 impl crate::RegisterSpec for BLK10_W6_SPEC {
diff --git a/esp32h2/src/otp_debug/blk10_w7.rs b/esp32h2/src/otp_debug/blk10_w7.rs
index d62ebceefb..35a6c9adc8 100644
--- a/esp32h2/src/otp_debug/blk10_w7.rs
+++ b/esp32h2/src/otp_debug/blk10_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W7")
-            .field("block10_w7", &format_args!("{}", self.block10_w7().bits()))
+            .field("block10_w7", &self.block10_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W7_SPEC;
 impl crate::RegisterSpec for BLK10_W7_SPEC {
diff --git a/esp32h2/src/otp_debug/blk10_w8.rs b/esp32h2/src/otp_debug/blk10_w8.rs
index 1994aeaaf6..5f610a854a 100644
--- a/esp32h2/src/otp_debug/blk10_w8.rs
+++ b/esp32h2/src/otp_debug/blk10_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W8")
-            .field("block10_w8", &format_args!("{}", self.block10_w8().bits()))
+            .field("block10_w8", &self.block10_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W8_SPEC;
 impl crate::RegisterSpec for BLK10_W8_SPEC {
diff --git a/esp32h2/src/otp_debug/blk10_w9.rs b/esp32h2/src/otp_debug/blk10_w9.rs
index c818c2ae7e..9021e8ce16 100644
--- a/esp32h2/src/otp_debug/blk10_w9.rs
+++ b/esp32h2/src/otp_debug/blk10_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK10_W9")
-            .field("block10_w9", &format_args!("{}", self.block10_w9().bits()))
+            .field("block10_w9", &self.block10_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK10_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block10 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk10_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK10_W9_SPEC;
 impl crate::RegisterSpec for BLK10_W9_SPEC {
diff --git a/esp32h2/src/otp_debug/blk1_w1.rs b/esp32h2/src/otp_debug/blk1_w1.rs
index 1e40d5d948..19925de656 100644
--- a/esp32h2/src/otp_debug/blk1_w1.rs
+++ b/esp32h2/src/otp_debug/blk1_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W1")
-            .field("block1_w1", &format_args!("{}", self.block1_w1().bits()))
+            .field("block1_w1", &self.block1_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W1_SPEC;
 impl crate::RegisterSpec for BLK1_W1_SPEC {
diff --git a/esp32h2/src/otp_debug/blk1_w2.rs b/esp32h2/src/otp_debug/blk1_w2.rs
index c9c12a5045..a4daa9baf3 100644
--- a/esp32h2/src/otp_debug/blk1_w2.rs
+++ b/esp32h2/src/otp_debug/blk1_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W2")
-            .field("block1_w2", &format_args!("{}", self.block1_w2().bits()))
+            .field("block1_w2", &self.block1_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W2_SPEC;
 impl crate::RegisterSpec for BLK1_W2_SPEC {
diff --git a/esp32h2/src/otp_debug/blk1_w3.rs b/esp32h2/src/otp_debug/blk1_w3.rs
index b8aef24df2..ee8503456c 100644
--- a/esp32h2/src/otp_debug/blk1_w3.rs
+++ b/esp32h2/src/otp_debug/blk1_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W3")
-            .field("block1_w3", &format_args!("{}", self.block1_w3().bits()))
+            .field("block1_w3", &self.block1_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W3_SPEC;
 impl crate::RegisterSpec for BLK1_W3_SPEC {
diff --git a/esp32h2/src/otp_debug/blk1_w4.rs b/esp32h2/src/otp_debug/blk1_w4.rs
index b91be23212..88dd803000 100644
--- a/esp32h2/src/otp_debug/blk1_w4.rs
+++ b/esp32h2/src/otp_debug/blk1_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W4")
-            .field("block1_w4", &format_args!("{}", self.block1_w4().bits()))
+            .field("block1_w4", &self.block1_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W4_SPEC;
 impl crate::RegisterSpec for BLK1_W4_SPEC {
diff --git a/esp32h2/src/otp_debug/blk1_w5.rs b/esp32h2/src/otp_debug/blk1_w5.rs
index 8bf9cfe91a..998abcbb34 100644
--- a/esp32h2/src/otp_debug/blk1_w5.rs
+++ b/esp32h2/src/otp_debug/blk1_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W5")
-            .field("block1_w5", &format_args!("{}", self.block1_w5().bits()))
+            .field("block1_w5", &self.block1_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W5_SPEC;
 impl crate::RegisterSpec for BLK1_W5_SPEC {
diff --git a/esp32h2/src/otp_debug/blk1_w6.rs b/esp32h2/src/otp_debug/blk1_w6.rs
index 04168bf573..a8870c0f42 100644
--- a/esp32h2/src/otp_debug/blk1_w6.rs
+++ b/esp32h2/src/otp_debug/blk1_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W6")
-            .field("block1_w6", &format_args!("{}", self.block1_w6().bits()))
+            .field("block1_w6", &self.block1_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W6_SPEC;
 impl crate::RegisterSpec for BLK1_W6_SPEC {
diff --git a/esp32h2/src/otp_debug/blk1_w7.rs b/esp32h2/src/otp_debug/blk1_w7.rs
index ecd0297b7e..4394c8dca2 100644
--- a/esp32h2/src/otp_debug/blk1_w7.rs
+++ b/esp32h2/src/otp_debug/blk1_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W7")
-            .field("block1_w7", &format_args!("{}", self.block1_w7().bits()))
+            .field("block1_w7", &self.block1_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W7_SPEC;
 impl crate::RegisterSpec for BLK1_W7_SPEC {
diff --git a/esp32h2/src/otp_debug/blk1_w8.rs b/esp32h2/src/otp_debug/blk1_w8.rs
index 213df188d8..bb5f995f4f 100644
--- a/esp32h2/src/otp_debug/blk1_w8.rs
+++ b/esp32h2/src/otp_debug/blk1_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W8")
-            .field("block1_w8", &format_args!("{}", self.block1_w8().bits()))
+            .field("block1_w8", &self.block1_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W8_SPEC;
 impl crate::RegisterSpec for BLK1_W8_SPEC {
diff --git a/esp32h2/src/otp_debug/blk1_w9.rs b/esp32h2/src/otp_debug/blk1_w9.rs
index d3f28503e2..4ffe29d3d8 100644
--- a/esp32h2/src/otp_debug/blk1_w9.rs
+++ b/esp32h2/src/otp_debug/blk1_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK1_W9")
-            .field("block1_w9", &format_args!("{}", self.block1_w9().bits()))
+            .field("block1_w9", &self.block1_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK1_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block1 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk1_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK1_W9_SPEC;
 impl crate::RegisterSpec for BLK1_W9_SPEC {
diff --git a/esp32h2/src/otp_debug/blk2_w1.rs b/esp32h2/src/otp_debug/blk2_w1.rs
index 6473f28b40..26dab78b9b 100644
--- a/esp32h2/src/otp_debug/blk2_w1.rs
+++ b/esp32h2/src/otp_debug/blk2_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W1")
-            .field("block2_w1", &format_args!("{}", self.block2_w1().bits()))
+            .field("block2_w1", &self.block2_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W1_SPEC;
 impl crate::RegisterSpec for BLK2_W1_SPEC {
diff --git a/esp32h2/src/otp_debug/blk2_w10.rs b/esp32h2/src/otp_debug/blk2_w10.rs
index 64cfa633b4..ecacf275a6 100644
--- a/esp32h2/src/otp_debug/blk2_w10.rs
+++ b/esp32h2/src/otp_debug/blk2_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W10")
-            .field("block2_w10", &format_args!("{}", self.block2_w10().bits()))
+            .field("block2_w10", &self.block2_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W10_SPEC;
 impl crate::RegisterSpec for BLK2_W10_SPEC {
diff --git a/esp32h2/src/otp_debug/blk2_w11.rs b/esp32h2/src/otp_debug/blk2_w11.rs
index c417e18cfd..f55c8acaa1 100644
--- a/esp32h2/src/otp_debug/blk2_w11.rs
+++ b/esp32h2/src/otp_debug/blk2_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W11")
-            .field("block2_w11", &format_args!("{}", self.block2_w11().bits()))
+            .field("block2_w11", &self.block2_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W11_SPEC;
 impl crate::RegisterSpec for BLK2_W11_SPEC {
diff --git a/esp32h2/src/otp_debug/blk2_w2.rs b/esp32h2/src/otp_debug/blk2_w2.rs
index 00b2046c1c..8dfc697f5b 100644
--- a/esp32h2/src/otp_debug/blk2_w2.rs
+++ b/esp32h2/src/otp_debug/blk2_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W2")
-            .field("block2_w2", &format_args!("{}", self.block2_w2().bits()))
+            .field("block2_w2", &self.block2_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W2_SPEC;
 impl crate::RegisterSpec for BLK2_W2_SPEC {
diff --git a/esp32h2/src/otp_debug/blk2_w3.rs b/esp32h2/src/otp_debug/blk2_w3.rs
index 6ada7f82ed..4af8c1a54e 100644
--- a/esp32h2/src/otp_debug/blk2_w3.rs
+++ b/esp32h2/src/otp_debug/blk2_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W3")
-            .field("block2_w3", &format_args!("{}", self.block2_w3().bits()))
+            .field("block2_w3", &self.block2_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W3_SPEC;
 impl crate::RegisterSpec for BLK2_W3_SPEC {
diff --git a/esp32h2/src/otp_debug/blk2_w4.rs b/esp32h2/src/otp_debug/blk2_w4.rs
index a20fd7353a..e25c6dc8d1 100644
--- a/esp32h2/src/otp_debug/blk2_w4.rs
+++ b/esp32h2/src/otp_debug/blk2_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W4")
-            .field("block2_w4", &format_args!("{}", self.block2_w4().bits()))
+            .field("block2_w4", &self.block2_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W4_SPEC;
 impl crate::RegisterSpec for BLK2_W4_SPEC {
diff --git a/esp32h2/src/otp_debug/blk2_w5.rs b/esp32h2/src/otp_debug/blk2_w5.rs
index a3b63748c6..038314b1da 100644
--- a/esp32h2/src/otp_debug/blk2_w5.rs
+++ b/esp32h2/src/otp_debug/blk2_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W5")
-            .field("block2_w5", &format_args!("{}", self.block2_w5().bits()))
+            .field("block2_w5", &self.block2_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W5_SPEC;
 impl crate::RegisterSpec for BLK2_W5_SPEC {
diff --git a/esp32h2/src/otp_debug/blk2_w6.rs b/esp32h2/src/otp_debug/blk2_w6.rs
index 27ca05b93b..750f2329e9 100644
--- a/esp32h2/src/otp_debug/blk2_w6.rs
+++ b/esp32h2/src/otp_debug/blk2_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W6")
-            .field("block2_w6", &format_args!("{}", self.block2_w6().bits()))
+            .field("block2_w6", &self.block2_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W6_SPEC;
 impl crate::RegisterSpec for BLK2_W6_SPEC {
diff --git a/esp32h2/src/otp_debug/blk2_w7.rs b/esp32h2/src/otp_debug/blk2_w7.rs
index 18b136a0a2..7bc7d5bc83 100644
--- a/esp32h2/src/otp_debug/blk2_w7.rs
+++ b/esp32h2/src/otp_debug/blk2_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W7")
-            .field("block2_w7", &format_args!("{}", self.block2_w7().bits()))
+            .field("block2_w7", &self.block2_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W7_SPEC;
 impl crate::RegisterSpec for BLK2_W7_SPEC {
diff --git a/esp32h2/src/otp_debug/blk2_w8.rs b/esp32h2/src/otp_debug/blk2_w8.rs
index 0bfcd982c7..c25622a085 100644
--- a/esp32h2/src/otp_debug/blk2_w8.rs
+++ b/esp32h2/src/otp_debug/blk2_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W8")
-            .field("block2_w8", &format_args!("{}", self.block2_w8().bits()))
+            .field("block2_w8", &self.block2_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W8_SPEC;
 impl crate::RegisterSpec for BLK2_W8_SPEC {
diff --git a/esp32h2/src/otp_debug/blk2_w9.rs b/esp32h2/src/otp_debug/blk2_w9.rs
index 064198d0bc..53b4d92f84 100644
--- a/esp32h2/src/otp_debug/blk2_w9.rs
+++ b/esp32h2/src/otp_debug/blk2_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK2_W9")
-            .field("block2_w9", &format_args!("{}", self.block2_w9().bits()))
+            .field("block2_w9", &self.block2_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK2_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block2 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk2_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK2_W9_SPEC;
 impl crate::RegisterSpec for BLK2_W9_SPEC {
diff --git a/esp32h2/src/otp_debug/blk3_w1.rs b/esp32h2/src/otp_debug/blk3_w1.rs
index 488a9fb483..ce86b475fc 100644
--- a/esp32h2/src/otp_debug/blk3_w1.rs
+++ b/esp32h2/src/otp_debug/blk3_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W1")
-            .field("block3_w1", &format_args!("{}", self.block3_w1().bits()))
+            .field("block3_w1", &self.block3_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W1_SPEC;
 impl crate::RegisterSpec for BLK3_W1_SPEC {
diff --git a/esp32h2/src/otp_debug/blk3_w10.rs b/esp32h2/src/otp_debug/blk3_w10.rs
index eb0ee64853..77628ad844 100644
--- a/esp32h2/src/otp_debug/blk3_w10.rs
+++ b/esp32h2/src/otp_debug/blk3_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W10")
-            .field("block3_w10", &format_args!("{}", self.block3_w10().bits()))
+            .field("block3_w10", &self.block3_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W10_SPEC;
 impl crate::RegisterSpec for BLK3_W10_SPEC {
diff --git a/esp32h2/src/otp_debug/blk3_w11.rs b/esp32h2/src/otp_debug/blk3_w11.rs
index 3e691ed90c..2d26724d29 100644
--- a/esp32h2/src/otp_debug/blk3_w11.rs
+++ b/esp32h2/src/otp_debug/blk3_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W11")
-            .field("block3_w11", &format_args!("{}", self.block3_w11().bits()))
+            .field("block3_w11", &self.block3_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W11_SPEC;
 impl crate::RegisterSpec for BLK3_W11_SPEC {
diff --git a/esp32h2/src/otp_debug/blk3_w2.rs b/esp32h2/src/otp_debug/blk3_w2.rs
index dc98b45db5..8964a221f4 100644
--- a/esp32h2/src/otp_debug/blk3_w2.rs
+++ b/esp32h2/src/otp_debug/blk3_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W2")
-            .field("block3_w2", &format_args!("{}", self.block3_w2().bits()))
+            .field("block3_w2", &self.block3_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W2_SPEC;
 impl crate::RegisterSpec for BLK3_W2_SPEC {
diff --git a/esp32h2/src/otp_debug/blk3_w3.rs b/esp32h2/src/otp_debug/blk3_w3.rs
index 457c7b2b08..48cafb6aa0 100644
--- a/esp32h2/src/otp_debug/blk3_w3.rs
+++ b/esp32h2/src/otp_debug/blk3_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W3")
-            .field("block3_w3", &format_args!("{}", self.block3_w3().bits()))
+            .field("block3_w3", &self.block3_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W3_SPEC;
 impl crate::RegisterSpec for BLK3_W3_SPEC {
diff --git a/esp32h2/src/otp_debug/blk3_w4.rs b/esp32h2/src/otp_debug/blk3_w4.rs
index b9e2de9f9e..416da42195 100644
--- a/esp32h2/src/otp_debug/blk3_w4.rs
+++ b/esp32h2/src/otp_debug/blk3_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W4")
-            .field("block3_w4", &format_args!("{}", self.block3_w4().bits()))
+            .field("block3_w4", &self.block3_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W4_SPEC;
 impl crate::RegisterSpec for BLK3_W4_SPEC {
diff --git a/esp32h2/src/otp_debug/blk3_w5.rs b/esp32h2/src/otp_debug/blk3_w5.rs
index 5c817869a9..2be3abd5f2 100644
--- a/esp32h2/src/otp_debug/blk3_w5.rs
+++ b/esp32h2/src/otp_debug/blk3_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W5")
-            .field("block3_w5", &format_args!("{}", self.block3_w5().bits()))
+            .field("block3_w5", &self.block3_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W5_SPEC;
 impl crate::RegisterSpec for BLK3_W5_SPEC {
diff --git a/esp32h2/src/otp_debug/blk3_w6.rs b/esp32h2/src/otp_debug/blk3_w6.rs
index c5a10e7814..ad8d08166d 100644
--- a/esp32h2/src/otp_debug/blk3_w6.rs
+++ b/esp32h2/src/otp_debug/blk3_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W6")
-            .field("block3_w6", &format_args!("{}", self.block3_w6().bits()))
+            .field("block3_w6", &self.block3_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W6_SPEC;
 impl crate::RegisterSpec for BLK3_W6_SPEC {
diff --git a/esp32h2/src/otp_debug/blk3_w7.rs b/esp32h2/src/otp_debug/blk3_w7.rs
index 464d1dbd3d..a04b785e95 100644
--- a/esp32h2/src/otp_debug/blk3_w7.rs
+++ b/esp32h2/src/otp_debug/blk3_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W7")
-            .field("block3_w7", &format_args!("{}", self.block3_w7().bits()))
+            .field("block3_w7", &self.block3_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W7_SPEC;
 impl crate::RegisterSpec for BLK3_W7_SPEC {
diff --git a/esp32h2/src/otp_debug/blk3_w8.rs b/esp32h2/src/otp_debug/blk3_w8.rs
index e3d7140795..29d1fc0ea0 100644
--- a/esp32h2/src/otp_debug/blk3_w8.rs
+++ b/esp32h2/src/otp_debug/blk3_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W8")
-            .field("block3_w8", &format_args!("{}", self.block3_w8().bits()))
+            .field("block3_w8", &self.block3_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W8_SPEC;
 impl crate::RegisterSpec for BLK3_W8_SPEC {
diff --git a/esp32h2/src/otp_debug/blk3_w9.rs b/esp32h2/src/otp_debug/blk3_w9.rs
index a1a73eac44..a0cac36b88 100644
--- a/esp32h2/src/otp_debug/blk3_w9.rs
+++ b/esp32h2/src/otp_debug/blk3_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK3_W9")
-            .field("block3_w9", &format_args!("{}", self.block3_w9().bits()))
+            .field("block3_w9", &self.block3_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK3_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block3 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk3_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK3_W9_SPEC;
 impl crate::RegisterSpec for BLK3_W9_SPEC {
diff --git a/esp32h2/src/otp_debug/blk4_w1.rs b/esp32h2/src/otp_debug/blk4_w1.rs
index 9299cfd5dc..8b55ec57e6 100644
--- a/esp32h2/src/otp_debug/blk4_w1.rs
+++ b/esp32h2/src/otp_debug/blk4_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W1")
-            .field("block4_w1", &format_args!("{}", self.block4_w1().bits()))
+            .field("block4_w1", &self.block4_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W1_SPEC;
 impl crate::RegisterSpec for BLK4_W1_SPEC {
diff --git a/esp32h2/src/otp_debug/blk4_w10.rs b/esp32h2/src/otp_debug/blk4_w10.rs
index 728bb54228..52c55ba06a 100644
--- a/esp32h2/src/otp_debug/blk4_w10.rs
+++ b/esp32h2/src/otp_debug/blk4_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W10")
-            .field("block4_w10", &format_args!("{}", self.block4_w10().bits()))
+            .field("block4_w10", &self.block4_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data registe10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W10_SPEC;
 impl crate::RegisterSpec for BLK4_W10_SPEC {
diff --git a/esp32h2/src/otp_debug/blk4_w11.rs b/esp32h2/src/otp_debug/blk4_w11.rs
index 4f241693f4..60c4166fe7 100644
--- a/esp32h2/src/otp_debug/blk4_w11.rs
+++ b/esp32h2/src/otp_debug/blk4_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W11")
-            .field("block4_w11", &format_args!("{}", self.block4_w11().bits()))
+            .field("block4_w11", &self.block4_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W11_SPEC;
 impl crate::RegisterSpec for BLK4_W11_SPEC {
diff --git a/esp32h2/src/otp_debug/blk4_w2.rs b/esp32h2/src/otp_debug/blk4_w2.rs
index 882038dea2..3184daaf8d 100644
--- a/esp32h2/src/otp_debug/blk4_w2.rs
+++ b/esp32h2/src/otp_debug/blk4_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W2")
-            .field("block4_w2", &format_args!("{}", self.block4_w2().bits()))
+            .field("block4_w2", &self.block4_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W2_SPEC;
 impl crate::RegisterSpec for BLK4_W2_SPEC {
diff --git a/esp32h2/src/otp_debug/blk4_w3.rs b/esp32h2/src/otp_debug/blk4_w3.rs
index fb29e09670..15422542d5 100644
--- a/esp32h2/src/otp_debug/blk4_w3.rs
+++ b/esp32h2/src/otp_debug/blk4_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W3")
-            .field("block4_w3", &format_args!("{}", self.block4_w3().bits()))
+            .field("block4_w3", &self.block4_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W3_SPEC;
 impl crate::RegisterSpec for BLK4_W3_SPEC {
diff --git a/esp32h2/src/otp_debug/blk4_w4.rs b/esp32h2/src/otp_debug/blk4_w4.rs
index c53db9e4f7..d8a728ae53 100644
--- a/esp32h2/src/otp_debug/blk4_w4.rs
+++ b/esp32h2/src/otp_debug/blk4_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W4")
-            .field("block4_w4", &format_args!("{}", self.block4_w4().bits()))
+            .field("block4_w4", &self.block4_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W4_SPEC;
 impl crate::RegisterSpec for BLK4_W4_SPEC {
diff --git a/esp32h2/src/otp_debug/blk4_w5.rs b/esp32h2/src/otp_debug/blk4_w5.rs
index 9f5649dcde..561674c4ad 100644
--- a/esp32h2/src/otp_debug/blk4_w5.rs
+++ b/esp32h2/src/otp_debug/blk4_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W5")
-            .field("block4_w5", &format_args!("{}", self.block4_w5().bits()))
+            .field("block4_w5", &self.block4_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W5_SPEC;
 impl crate::RegisterSpec for BLK4_W5_SPEC {
diff --git a/esp32h2/src/otp_debug/blk4_w6.rs b/esp32h2/src/otp_debug/blk4_w6.rs
index 917a665253..b53f2ec328 100644
--- a/esp32h2/src/otp_debug/blk4_w6.rs
+++ b/esp32h2/src/otp_debug/blk4_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W6")
-            .field("block4_w6", &format_args!("{}", self.block4_w6().bits()))
+            .field("block4_w6", &self.block4_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W6_SPEC;
 impl crate::RegisterSpec for BLK4_W6_SPEC {
diff --git a/esp32h2/src/otp_debug/blk4_w7.rs b/esp32h2/src/otp_debug/blk4_w7.rs
index 71f15cf4e8..98315eef38 100644
--- a/esp32h2/src/otp_debug/blk4_w7.rs
+++ b/esp32h2/src/otp_debug/blk4_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W7")
-            .field("block4_w7", &format_args!("{}", self.block4_w7().bits()))
+            .field("block4_w7", &self.block4_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W7_SPEC;
 impl crate::RegisterSpec for BLK4_W7_SPEC {
diff --git a/esp32h2/src/otp_debug/blk4_w8.rs b/esp32h2/src/otp_debug/blk4_w8.rs
index 4d91ca1e90..580bfb5569 100644
--- a/esp32h2/src/otp_debug/blk4_w8.rs
+++ b/esp32h2/src/otp_debug/blk4_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W8")
-            .field("block4_w8", &format_args!("{}", self.block4_w8().bits()))
+            .field("block4_w8", &self.block4_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W8_SPEC;
 impl crate::RegisterSpec for BLK4_W8_SPEC {
diff --git a/esp32h2/src/otp_debug/blk4_w9.rs b/esp32h2/src/otp_debug/blk4_w9.rs
index f3983eca39..082293cd06 100644
--- a/esp32h2/src/otp_debug/blk4_w9.rs
+++ b/esp32h2/src/otp_debug/blk4_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK4_W9")
-            .field("block4_w9", &format_args!("{}", self.block4_w9().bits()))
+            .field("block4_w9", &self.block4_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK4_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block4 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk4_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK4_W9_SPEC;
 impl crate::RegisterSpec for BLK4_W9_SPEC {
diff --git a/esp32h2/src/otp_debug/blk5_w1.rs b/esp32h2/src/otp_debug/blk5_w1.rs
index e6989f7cae..31d5bed004 100644
--- a/esp32h2/src/otp_debug/blk5_w1.rs
+++ b/esp32h2/src/otp_debug/blk5_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W1")
-            .field("block5_w1", &format_args!("{}", self.block5_w1().bits()))
+            .field("block5_w1", &self.block5_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W1_SPEC;
 impl crate::RegisterSpec for BLK5_W1_SPEC {
diff --git a/esp32h2/src/otp_debug/blk5_w10.rs b/esp32h2/src/otp_debug/blk5_w10.rs
index 436b0412e3..b0024572db 100644
--- a/esp32h2/src/otp_debug/blk5_w10.rs
+++ b/esp32h2/src/otp_debug/blk5_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W10")
-            .field("block5_w10", &format_args!("{}", self.block5_w10().bits()))
+            .field("block5_w10", &self.block5_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W10_SPEC;
 impl crate::RegisterSpec for BLK5_W10_SPEC {
diff --git a/esp32h2/src/otp_debug/blk5_w11.rs b/esp32h2/src/otp_debug/blk5_w11.rs
index 38a852001a..6103533027 100644
--- a/esp32h2/src/otp_debug/blk5_w11.rs
+++ b/esp32h2/src/otp_debug/blk5_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W11")
-            .field("block5_w11", &format_args!("{}", self.block5_w11().bits()))
+            .field("block5_w11", &self.block5_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W11_SPEC;
 impl crate::RegisterSpec for BLK5_W11_SPEC {
diff --git a/esp32h2/src/otp_debug/blk5_w2.rs b/esp32h2/src/otp_debug/blk5_w2.rs
index fcead77a8e..6f09c96c12 100644
--- a/esp32h2/src/otp_debug/blk5_w2.rs
+++ b/esp32h2/src/otp_debug/blk5_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W2")
-            .field("block5_w2", &format_args!("{}", self.block5_w2().bits()))
+            .field("block5_w2", &self.block5_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W2_SPEC;
 impl crate::RegisterSpec for BLK5_W2_SPEC {
diff --git a/esp32h2/src/otp_debug/blk5_w3.rs b/esp32h2/src/otp_debug/blk5_w3.rs
index c1079d0c46..4017bdd56d 100644
--- a/esp32h2/src/otp_debug/blk5_w3.rs
+++ b/esp32h2/src/otp_debug/blk5_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W3")
-            .field("block5_w3", &format_args!("{}", self.block5_w3().bits()))
+            .field("block5_w3", &self.block5_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W3_SPEC;
 impl crate::RegisterSpec for BLK5_W3_SPEC {
diff --git a/esp32h2/src/otp_debug/blk5_w4.rs b/esp32h2/src/otp_debug/blk5_w4.rs
index 38f91f647e..e8d5b74e71 100644
--- a/esp32h2/src/otp_debug/blk5_w4.rs
+++ b/esp32h2/src/otp_debug/blk5_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W4")
-            .field("block5_w4", &format_args!("{}", self.block5_w4().bits()))
+            .field("block5_w4", &self.block5_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W4_SPEC;
 impl crate::RegisterSpec for BLK5_W4_SPEC {
diff --git a/esp32h2/src/otp_debug/blk5_w5.rs b/esp32h2/src/otp_debug/blk5_w5.rs
index f3bf48f23c..b44ae493db 100644
--- a/esp32h2/src/otp_debug/blk5_w5.rs
+++ b/esp32h2/src/otp_debug/blk5_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W5")
-            .field("block5_w5", &format_args!("{}", self.block5_w5().bits()))
+            .field("block5_w5", &self.block5_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W5_SPEC;
 impl crate::RegisterSpec for BLK5_W5_SPEC {
diff --git a/esp32h2/src/otp_debug/blk5_w6.rs b/esp32h2/src/otp_debug/blk5_w6.rs
index 46623f1591..c538b4313e 100644
--- a/esp32h2/src/otp_debug/blk5_w6.rs
+++ b/esp32h2/src/otp_debug/blk5_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W6")
-            .field("block5_w6", &format_args!("{}", self.block5_w6().bits()))
+            .field("block5_w6", &self.block5_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W6_SPEC;
 impl crate::RegisterSpec for BLK5_W6_SPEC {
diff --git a/esp32h2/src/otp_debug/blk5_w7.rs b/esp32h2/src/otp_debug/blk5_w7.rs
index 105c530f5a..dbf5d69798 100644
--- a/esp32h2/src/otp_debug/blk5_w7.rs
+++ b/esp32h2/src/otp_debug/blk5_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W7")
-            .field("block5_w7", &format_args!("{}", self.block5_w7().bits()))
+            .field("block5_w7", &self.block5_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W7_SPEC;
 impl crate::RegisterSpec for BLK5_W7_SPEC {
diff --git a/esp32h2/src/otp_debug/blk5_w8.rs b/esp32h2/src/otp_debug/blk5_w8.rs
index 68ed1fe83a..f9c8303bc3 100644
--- a/esp32h2/src/otp_debug/blk5_w8.rs
+++ b/esp32h2/src/otp_debug/blk5_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W8")
-            .field("block5_w8", &format_args!("{}", self.block5_w8().bits()))
+            .field("block5_w8", &self.block5_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W8_SPEC;
 impl crate::RegisterSpec for BLK5_W8_SPEC {
diff --git a/esp32h2/src/otp_debug/blk5_w9.rs b/esp32h2/src/otp_debug/blk5_w9.rs
index 3a34129f31..3dbea1f968 100644
--- a/esp32h2/src/otp_debug/blk5_w9.rs
+++ b/esp32h2/src/otp_debug/blk5_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK5_W9")
-            .field("block5_w9", &format_args!("{}", self.block5_w9().bits()))
+            .field("block5_w9", &self.block5_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK5_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block5 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk5_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK5_W9_SPEC;
 impl crate::RegisterSpec for BLK5_W9_SPEC {
diff --git a/esp32h2/src/otp_debug/blk6_w1.rs b/esp32h2/src/otp_debug/blk6_w1.rs
index e9453208fd..343e3e92a4 100644
--- a/esp32h2/src/otp_debug/blk6_w1.rs
+++ b/esp32h2/src/otp_debug/blk6_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W1")
-            .field("block6_w1", &format_args!("{}", self.block6_w1().bits()))
+            .field("block6_w1", &self.block6_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W1_SPEC;
 impl crate::RegisterSpec for BLK6_W1_SPEC {
diff --git a/esp32h2/src/otp_debug/blk6_w10.rs b/esp32h2/src/otp_debug/blk6_w10.rs
index 7825b4acb8..625b8d134d 100644
--- a/esp32h2/src/otp_debug/blk6_w10.rs
+++ b/esp32h2/src/otp_debug/blk6_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W10")
-            .field("block6_w10", &format_args!("{}", self.block6_w10().bits()))
+            .field("block6_w10", &self.block6_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W10_SPEC;
 impl crate::RegisterSpec for BLK6_W10_SPEC {
diff --git a/esp32h2/src/otp_debug/blk6_w11.rs b/esp32h2/src/otp_debug/blk6_w11.rs
index 193bf513fa..fb791c1e6a 100644
--- a/esp32h2/src/otp_debug/blk6_w11.rs
+++ b/esp32h2/src/otp_debug/blk6_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W11")
-            .field("block6_w11", &format_args!("{}", self.block6_w11().bits()))
+            .field("block6_w11", &self.block6_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W11_SPEC;
 impl crate::RegisterSpec for BLK6_W11_SPEC {
diff --git a/esp32h2/src/otp_debug/blk6_w2.rs b/esp32h2/src/otp_debug/blk6_w2.rs
index 60a60f18ce..af4a9733d9 100644
--- a/esp32h2/src/otp_debug/blk6_w2.rs
+++ b/esp32h2/src/otp_debug/blk6_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W2")
-            .field("block6_w2", &format_args!("{}", self.block6_w2().bits()))
+            .field("block6_w2", &self.block6_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W2_SPEC;
 impl crate::RegisterSpec for BLK6_W2_SPEC {
diff --git a/esp32h2/src/otp_debug/blk6_w3.rs b/esp32h2/src/otp_debug/blk6_w3.rs
index 566e5baad2..24472421f2 100644
--- a/esp32h2/src/otp_debug/blk6_w3.rs
+++ b/esp32h2/src/otp_debug/blk6_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W3")
-            .field("block6_w3", &format_args!("{}", self.block6_w3().bits()))
+            .field("block6_w3", &self.block6_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W3_SPEC;
 impl crate::RegisterSpec for BLK6_W3_SPEC {
diff --git a/esp32h2/src/otp_debug/blk6_w4.rs b/esp32h2/src/otp_debug/blk6_w4.rs
index 358c27b0c8..3264bb4c66 100644
--- a/esp32h2/src/otp_debug/blk6_w4.rs
+++ b/esp32h2/src/otp_debug/blk6_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W4")
-            .field("block6_w4", &format_args!("{}", self.block6_w4().bits()))
+            .field("block6_w4", &self.block6_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W4_SPEC;
 impl crate::RegisterSpec for BLK6_W4_SPEC {
diff --git a/esp32h2/src/otp_debug/blk6_w5.rs b/esp32h2/src/otp_debug/blk6_w5.rs
index 10cefed773..acd1b40103 100644
--- a/esp32h2/src/otp_debug/blk6_w5.rs
+++ b/esp32h2/src/otp_debug/blk6_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W5")
-            .field("block6_w5", &format_args!("{}", self.block6_w5().bits()))
+            .field("block6_w5", &self.block6_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W5_SPEC;
 impl crate::RegisterSpec for BLK6_W5_SPEC {
diff --git a/esp32h2/src/otp_debug/blk6_w6.rs b/esp32h2/src/otp_debug/blk6_w6.rs
index 4cf1db7bde..f6e8bc051b 100644
--- a/esp32h2/src/otp_debug/blk6_w6.rs
+++ b/esp32h2/src/otp_debug/blk6_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W6")
-            .field("block6_w6", &format_args!("{}", self.block6_w6().bits()))
+            .field("block6_w6", &self.block6_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W6_SPEC;
 impl crate::RegisterSpec for BLK6_W6_SPEC {
diff --git a/esp32h2/src/otp_debug/blk6_w7.rs b/esp32h2/src/otp_debug/blk6_w7.rs
index 56faec9876..07e11cb4ae 100644
--- a/esp32h2/src/otp_debug/blk6_w7.rs
+++ b/esp32h2/src/otp_debug/blk6_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W7")
-            .field("block6_w7", &format_args!("{}", self.block6_w7().bits()))
+            .field("block6_w7", &self.block6_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W7_SPEC;
 impl crate::RegisterSpec for BLK6_W7_SPEC {
diff --git a/esp32h2/src/otp_debug/blk6_w8.rs b/esp32h2/src/otp_debug/blk6_w8.rs
index 6be9f9605a..2e437a5ddd 100644
--- a/esp32h2/src/otp_debug/blk6_w8.rs
+++ b/esp32h2/src/otp_debug/blk6_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W8")
-            .field("block6_w8", &format_args!("{}", self.block6_w8().bits()))
+            .field("block6_w8", &self.block6_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W8_SPEC;
 impl crate::RegisterSpec for BLK6_W8_SPEC {
diff --git a/esp32h2/src/otp_debug/blk6_w9.rs b/esp32h2/src/otp_debug/blk6_w9.rs
index 7facf7ee7a..171b61a72c 100644
--- a/esp32h2/src/otp_debug/blk6_w9.rs
+++ b/esp32h2/src/otp_debug/blk6_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK6_W9")
-            .field("block6_w9", &format_args!("{}", self.block6_w9().bits()))
+            .field("block6_w9", &self.block6_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK6_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block6 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk6_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK6_W9_SPEC;
 impl crate::RegisterSpec for BLK6_W9_SPEC {
diff --git a/esp32h2/src/otp_debug/blk7_w1.rs b/esp32h2/src/otp_debug/blk7_w1.rs
index 80485b44e1..953f022635 100644
--- a/esp32h2/src/otp_debug/blk7_w1.rs
+++ b/esp32h2/src/otp_debug/blk7_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W1")
-            .field("block7_w1", &format_args!("{}", self.block7_w1().bits()))
+            .field("block7_w1", &self.block7_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W1_SPEC;
 impl crate::RegisterSpec for BLK7_W1_SPEC {
diff --git a/esp32h2/src/otp_debug/blk7_w10.rs b/esp32h2/src/otp_debug/blk7_w10.rs
index 214f492311..706ebfaf45 100644
--- a/esp32h2/src/otp_debug/blk7_w10.rs
+++ b/esp32h2/src/otp_debug/blk7_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W10")
-            .field("block7_w10", &format_args!("{}", self.block7_w10().bits()))
+            .field("block7_w10", &self.block7_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W10_SPEC;
 impl crate::RegisterSpec for BLK7_W10_SPEC {
diff --git a/esp32h2/src/otp_debug/blk7_w11.rs b/esp32h2/src/otp_debug/blk7_w11.rs
index b3f3460741..2eabab4d9b 100644
--- a/esp32h2/src/otp_debug/blk7_w11.rs
+++ b/esp32h2/src/otp_debug/blk7_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W11")
-            .field("block7_w11", &format_args!("{}", self.block7_w11().bits()))
+            .field("block7_w11", &self.block7_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W11_SPEC;
 impl crate::RegisterSpec for BLK7_W11_SPEC {
diff --git a/esp32h2/src/otp_debug/blk7_w2.rs b/esp32h2/src/otp_debug/blk7_w2.rs
index 9e07a04cf8..fe5222fc76 100644
--- a/esp32h2/src/otp_debug/blk7_w2.rs
+++ b/esp32h2/src/otp_debug/blk7_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W2")
-            .field("block7_w2", &format_args!("{}", self.block7_w2().bits()))
+            .field("block7_w2", &self.block7_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W2_SPEC;
 impl crate::RegisterSpec for BLK7_W2_SPEC {
diff --git a/esp32h2/src/otp_debug/blk7_w3.rs b/esp32h2/src/otp_debug/blk7_w3.rs
index 3e91589aa2..b6b342544a 100644
--- a/esp32h2/src/otp_debug/blk7_w3.rs
+++ b/esp32h2/src/otp_debug/blk7_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W3")
-            .field("block7_w3", &format_args!("{}", self.block7_w3().bits()))
+            .field("block7_w3", &self.block7_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W3_SPEC;
 impl crate::RegisterSpec for BLK7_W3_SPEC {
diff --git a/esp32h2/src/otp_debug/blk7_w4.rs b/esp32h2/src/otp_debug/blk7_w4.rs
index e2e86f8a1d..1c12561404 100644
--- a/esp32h2/src/otp_debug/blk7_w4.rs
+++ b/esp32h2/src/otp_debug/blk7_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W4")
-            .field("block7_w4", &format_args!("{}", self.block7_w4().bits()))
+            .field("block7_w4", &self.block7_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W4_SPEC;
 impl crate::RegisterSpec for BLK7_W4_SPEC {
diff --git a/esp32h2/src/otp_debug/blk7_w5.rs b/esp32h2/src/otp_debug/blk7_w5.rs
index a1ce038db9..985a92fc34 100644
--- a/esp32h2/src/otp_debug/blk7_w5.rs
+++ b/esp32h2/src/otp_debug/blk7_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W5")
-            .field("block7_w5", &format_args!("{}", self.block7_w5().bits()))
+            .field("block7_w5", &self.block7_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W5_SPEC;
 impl crate::RegisterSpec for BLK7_W5_SPEC {
diff --git a/esp32h2/src/otp_debug/blk7_w6.rs b/esp32h2/src/otp_debug/blk7_w6.rs
index 1d953fee1b..6e2d3618c4 100644
--- a/esp32h2/src/otp_debug/blk7_w6.rs
+++ b/esp32h2/src/otp_debug/blk7_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W6")
-            .field("block7_w6", &format_args!("{}", self.block7_w6().bits()))
+            .field("block7_w6", &self.block7_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W6_SPEC;
 impl crate::RegisterSpec for BLK7_W6_SPEC {
diff --git a/esp32h2/src/otp_debug/blk7_w7.rs b/esp32h2/src/otp_debug/blk7_w7.rs
index 920a0c91e8..d7a4aadd41 100644
--- a/esp32h2/src/otp_debug/blk7_w7.rs
+++ b/esp32h2/src/otp_debug/blk7_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W7")
-            .field("block7_w7", &format_args!("{}", self.block7_w7().bits()))
+            .field("block7_w7", &self.block7_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W7_SPEC;
 impl crate::RegisterSpec for BLK7_W7_SPEC {
diff --git a/esp32h2/src/otp_debug/blk7_w8.rs b/esp32h2/src/otp_debug/blk7_w8.rs
index 5bba8ed30f..faab2a5a36 100644
--- a/esp32h2/src/otp_debug/blk7_w8.rs
+++ b/esp32h2/src/otp_debug/blk7_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W8")
-            .field("block7_w8", &format_args!("{}", self.block7_w8().bits()))
+            .field("block7_w8", &self.block7_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W8_SPEC;
 impl crate::RegisterSpec for BLK7_W8_SPEC {
diff --git a/esp32h2/src/otp_debug/blk7_w9.rs b/esp32h2/src/otp_debug/blk7_w9.rs
index a22a4d8605..a033967560 100644
--- a/esp32h2/src/otp_debug/blk7_w9.rs
+++ b/esp32h2/src/otp_debug/blk7_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK7_W9")
-            .field("block7_w9", &format_args!("{}", self.block7_w9().bits()))
+            .field("block7_w9", &self.block7_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK7_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block7 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk7_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK7_W9_SPEC;
 impl crate::RegisterSpec for BLK7_W9_SPEC {
diff --git a/esp32h2/src/otp_debug/blk8_w1.rs b/esp32h2/src/otp_debug/blk8_w1.rs
index 0af67c78d4..4e79d971fd 100644
--- a/esp32h2/src/otp_debug/blk8_w1.rs
+++ b/esp32h2/src/otp_debug/blk8_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W1")
-            .field("block8_w1", &format_args!("{}", self.block8_w1().bits()))
+            .field("block8_w1", &self.block8_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W1_SPEC;
 impl crate::RegisterSpec for BLK8_W1_SPEC {
diff --git a/esp32h2/src/otp_debug/blk8_w10.rs b/esp32h2/src/otp_debug/blk8_w10.rs
index ba08b40c1e..1381edc72c 100644
--- a/esp32h2/src/otp_debug/blk8_w10.rs
+++ b/esp32h2/src/otp_debug/blk8_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W10")
-            .field("block8_w10", &format_args!("{}", self.block8_w10().bits()))
+            .field("block8_w10", &self.block8_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W10_SPEC;
 impl crate::RegisterSpec for BLK8_W10_SPEC {
diff --git a/esp32h2/src/otp_debug/blk8_w11.rs b/esp32h2/src/otp_debug/blk8_w11.rs
index 949f8e12a1..e5be523d13 100644
--- a/esp32h2/src/otp_debug/blk8_w11.rs
+++ b/esp32h2/src/otp_debug/blk8_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W11")
-            .field("block8_w11", &format_args!("{}", self.block8_w11().bits()))
+            .field("block8_w11", &self.block8_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W11_SPEC;
 impl crate::RegisterSpec for BLK8_W11_SPEC {
diff --git a/esp32h2/src/otp_debug/blk8_w2.rs b/esp32h2/src/otp_debug/blk8_w2.rs
index bf021534a5..d4d5a69b8e 100644
--- a/esp32h2/src/otp_debug/blk8_w2.rs
+++ b/esp32h2/src/otp_debug/blk8_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W2")
-            .field("block8_w2", &format_args!("{}", self.block8_w2().bits()))
+            .field("block8_w2", &self.block8_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W2_SPEC;
 impl crate::RegisterSpec for BLK8_W2_SPEC {
diff --git a/esp32h2/src/otp_debug/blk8_w3.rs b/esp32h2/src/otp_debug/blk8_w3.rs
index 523bf87329..103e7a673c 100644
--- a/esp32h2/src/otp_debug/blk8_w3.rs
+++ b/esp32h2/src/otp_debug/blk8_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W3")
-            .field("block8_w3", &format_args!("{}", self.block8_w3().bits()))
+            .field("block8_w3", &self.block8_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W3_SPEC;
 impl crate::RegisterSpec for BLK8_W3_SPEC {
diff --git a/esp32h2/src/otp_debug/blk8_w4.rs b/esp32h2/src/otp_debug/blk8_w4.rs
index f92c4bb25b..2e63831f7c 100644
--- a/esp32h2/src/otp_debug/blk8_w4.rs
+++ b/esp32h2/src/otp_debug/blk8_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W4")
-            .field("block8_w4", &format_args!("{}", self.block8_w4().bits()))
+            .field("block8_w4", &self.block8_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W4_SPEC;
 impl crate::RegisterSpec for BLK8_W4_SPEC {
diff --git a/esp32h2/src/otp_debug/blk8_w5.rs b/esp32h2/src/otp_debug/blk8_w5.rs
index 7f85b35cf8..a5bc28e17e 100644
--- a/esp32h2/src/otp_debug/blk8_w5.rs
+++ b/esp32h2/src/otp_debug/blk8_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W5")
-            .field("block8_w5", &format_args!("{}", self.block8_w5().bits()))
+            .field("block8_w5", &self.block8_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W5_SPEC;
 impl crate::RegisterSpec for BLK8_W5_SPEC {
diff --git a/esp32h2/src/otp_debug/blk8_w6.rs b/esp32h2/src/otp_debug/blk8_w6.rs
index 2765e910f5..68370cf265 100644
--- a/esp32h2/src/otp_debug/blk8_w6.rs
+++ b/esp32h2/src/otp_debug/blk8_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W6")
-            .field("block8_w6", &format_args!("{}", self.block8_w6().bits()))
+            .field("block8_w6", &self.block8_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W6_SPEC;
 impl crate::RegisterSpec for BLK8_W6_SPEC {
diff --git a/esp32h2/src/otp_debug/blk8_w7.rs b/esp32h2/src/otp_debug/blk8_w7.rs
index ce91180a22..b83a3e6494 100644
--- a/esp32h2/src/otp_debug/blk8_w7.rs
+++ b/esp32h2/src/otp_debug/blk8_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W7")
-            .field("block8_w7", &format_args!("{}", self.block8_w7().bits()))
+            .field("block8_w7", &self.block8_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W7_SPEC;
 impl crate::RegisterSpec for BLK8_W7_SPEC {
diff --git a/esp32h2/src/otp_debug/blk8_w8.rs b/esp32h2/src/otp_debug/blk8_w8.rs
index 436f9e02fa..e4085f8d27 100644
--- a/esp32h2/src/otp_debug/blk8_w8.rs
+++ b/esp32h2/src/otp_debug/blk8_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W8")
-            .field("block8_w8", &format_args!("{}", self.block8_w8().bits()))
+            .field("block8_w8", &self.block8_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W8_SPEC;
 impl crate::RegisterSpec for BLK8_W8_SPEC {
diff --git a/esp32h2/src/otp_debug/blk8_w9.rs b/esp32h2/src/otp_debug/blk8_w9.rs
index 9ade621239..dbada70184 100644
--- a/esp32h2/src/otp_debug/blk8_w9.rs
+++ b/esp32h2/src/otp_debug/blk8_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK8_W9")
-            .field("block8_w9", &format_args!("{}", self.block8_w9().bits()))
+            .field("block8_w9", &self.block8_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK8_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block8 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk8_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK8_W9_SPEC;
 impl crate::RegisterSpec for BLK8_W9_SPEC {
diff --git a/esp32h2/src/otp_debug/blk9_w1.rs b/esp32h2/src/otp_debug/blk9_w1.rs
index acca201d3b..d013ce0d24 100644
--- a/esp32h2/src/otp_debug/blk9_w1.rs
+++ b/esp32h2/src/otp_debug/blk9_w1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W1")
-            .field("block9_w1", &format_args!("{}", self.block9_w1().bits()))
+            .field("block9_w1", &self.block9_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W1_SPEC;
 impl crate::RegisterSpec for BLK9_W1_SPEC {
diff --git a/esp32h2/src/otp_debug/blk9_w10.rs b/esp32h2/src/otp_debug/blk9_w10.rs
index aa47b611b6..00055c838d 100644
--- a/esp32h2/src/otp_debug/blk9_w10.rs
+++ b/esp32h2/src/otp_debug/blk9_w10.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W10")
-            .field("block9_w10", &format_args!("{}", self.block9_w10().bits()))
+            .field("block9_w10", &self.block9_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W10_SPEC;
 impl crate::RegisterSpec for BLK9_W10_SPEC {
diff --git a/esp32h2/src/otp_debug/blk9_w11.rs b/esp32h2/src/otp_debug/blk9_w11.rs
index 6b2faa3d5a..9c2dd39808 100644
--- a/esp32h2/src/otp_debug/blk9_w11.rs
+++ b/esp32h2/src/otp_debug/blk9_w11.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W11")
-            .field("block9_w11", &format_args!("{}", self.block9_w11().bits()))
+            .field("block9_w11", &self.block9_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W11_SPEC;
 impl crate::RegisterSpec for BLK9_W11_SPEC {
diff --git a/esp32h2/src/otp_debug/blk9_w2.rs b/esp32h2/src/otp_debug/blk9_w2.rs
index 915520083d..25cb9ef088 100644
--- a/esp32h2/src/otp_debug/blk9_w2.rs
+++ b/esp32h2/src/otp_debug/blk9_w2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W2")
-            .field("block9_w2", &format_args!("{}", self.block9_w2().bits()))
+            .field("block9_w2", &self.block9_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W2_SPEC;
 impl crate::RegisterSpec for BLK9_W2_SPEC {
diff --git a/esp32h2/src/otp_debug/blk9_w3.rs b/esp32h2/src/otp_debug/blk9_w3.rs
index 548d780f66..7eacf6c029 100644
--- a/esp32h2/src/otp_debug/blk9_w3.rs
+++ b/esp32h2/src/otp_debug/blk9_w3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W3")
-            .field("block9_w3", &format_args!("{}", self.block9_w3().bits()))
+            .field("block9_w3", &self.block9_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W3_SPEC;
 impl crate::RegisterSpec for BLK9_W3_SPEC {
diff --git a/esp32h2/src/otp_debug/blk9_w4.rs b/esp32h2/src/otp_debug/blk9_w4.rs
index eff6ebfd0c..82cefd4210 100644
--- a/esp32h2/src/otp_debug/blk9_w4.rs
+++ b/esp32h2/src/otp_debug/blk9_w4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W4")
-            .field("block9_w4", &format_args!("{}", self.block9_w4().bits()))
+            .field("block9_w4", &self.block9_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W4_SPEC;
 impl crate::RegisterSpec for BLK9_W4_SPEC {
diff --git a/esp32h2/src/otp_debug/blk9_w5.rs b/esp32h2/src/otp_debug/blk9_w5.rs
index 5b09ef7a05..1acfee20c5 100644
--- a/esp32h2/src/otp_debug/blk9_w5.rs
+++ b/esp32h2/src/otp_debug/blk9_w5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W5")
-            .field("block9_w5", &format_args!("{}", self.block9_w5().bits()))
+            .field("block9_w5", &self.block9_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W5_SPEC;
 impl crate::RegisterSpec for BLK9_W5_SPEC {
diff --git a/esp32h2/src/otp_debug/blk9_w6.rs b/esp32h2/src/otp_debug/blk9_w6.rs
index f63889fd3e..ca6c901a32 100644
--- a/esp32h2/src/otp_debug/blk9_w6.rs
+++ b/esp32h2/src/otp_debug/blk9_w6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W6")
-            .field("block9_w6", &format_args!("{}", self.block9_w6().bits()))
+            .field("block9_w6", &self.block9_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W6_SPEC;
 impl crate::RegisterSpec for BLK9_W6_SPEC {
diff --git a/esp32h2/src/otp_debug/blk9_w7.rs b/esp32h2/src/otp_debug/blk9_w7.rs
index 754d05ce7f..bbea29fee2 100644
--- a/esp32h2/src/otp_debug/blk9_w7.rs
+++ b/esp32h2/src/otp_debug/blk9_w7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W7")
-            .field("block9_w7", &format_args!("{}", self.block9_w7().bits()))
+            .field("block9_w7", &self.block9_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W7_SPEC;
 impl crate::RegisterSpec for BLK9_W7_SPEC {
diff --git a/esp32h2/src/otp_debug/blk9_w8.rs b/esp32h2/src/otp_debug/blk9_w8.rs
index 9c831a26fb..e76368eea3 100644
--- a/esp32h2/src/otp_debug/blk9_w8.rs
+++ b/esp32h2/src/otp_debug/blk9_w8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W8")
-            .field("block9_w8", &format_args!("{}", self.block9_w8().bits()))
+            .field("block9_w8", &self.block9_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W8_SPEC;
 impl crate::RegisterSpec for BLK9_W8_SPEC {
diff --git a/esp32h2/src/otp_debug/blk9_w9.rs b/esp32h2/src/otp_debug/blk9_w9.rs
index 76b68ee02d..d195ede687 100644
--- a/esp32h2/src/otp_debug/blk9_w9.rs
+++ b/esp32h2/src/otp_debug/blk9_w9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK9_W9")
-            .field("block9_w9", &format_args!("{}", self.block9_w9().bits()))
+            .field("block9_w9", &self.block9_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK9_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block9 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blk9_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLK9_W9_SPEC;
 impl crate::RegisterSpec for BLK9_W9_SPEC {
diff --git a/esp32h2/src/otp_debug/clk.rs b/esp32h2/src/otp_debug/clk.rs
index cd8a296128..91629e6db5 100644
--- a/esp32h2/src/otp_debug/clk.rs
+++ b/esp32h2/src/otp_debug/clk.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CLK")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CLK").field("en", &self.en()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/otp_debug/date.rs b/esp32h2/src/otp_debug/date.rs
index acdf609e44..f2efcdc72d 100644
--- a/esp32h2/src/otp_debug/date.rs
+++ b/esp32h2/src/otp_debug/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/otp_debug/wr_dis.rs b/esp32h2/src/otp_debug/wr_dis.rs
index ea6ee4f522..2cd94211cf 100644
--- a/esp32h2/src/otp_debug/wr_dis.rs
+++ b/esp32h2/src/otp_debug/wr_dis.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_DIS")
-            .field(
-                "block0_wr_dis",
-                &format_args!("{}", self.block0_wr_dis().bits()),
-            )
+            .field("block0_wr_dis", &self.block0_wr_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_DIS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Otp debuger block0 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_dis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WR_DIS_SPEC;
 impl crate::RegisterSpec for WR_DIS_SPEC {
diff --git a/esp32h2/src/parl_io/clk.rs b/esp32h2/src/parl_io/clk.rs
index e4708b2032..60f6e7929d 100644
--- a/esp32h2/src/parl_io/clk.rs
+++ b/esp32h2/src/parl_io/clk.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CLK")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CLK").field("en", &self.en()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/parl_io/fifo_cfg.rs b/esp32h2/src/parl_io/fifo_cfg.rs
index 005b5e1292..b248788cca 100644
--- a/esp32h2/src/parl_io/fifo_cfg.rs
+++ b/esp32h2/src/parl_io/fifo_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CFG")
-            .field(
-                "tx_fifo_srst",
-                &format_args!("{}", self.tx_fifo_srst().bit()),
-            )
-            .field(
-                "rx_fifo_srst",
-                &format_args!("{}", self.rx_fifo_srst().bit()),
-            )
+            .field("tx_fifo_srst", &self.tx_fifo_srst())
+            .field("rx_fifo_srst", &self.rx_fifo_srst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - Set this bit to reset async fifo in tx module."]
     #[inline(always)]
diff --git a/esp32h2/src/parl_io/int_ena.rs b/esp32h2/src/parl_io/int_ena.rs
index 305aeb2eda..426fde28df 100644
--- a/esp32h2/src/parl_io/int_ena.rs
+++ b/esp32h2/src/parl_io/int_ena.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "tx_fifo_rempty",
-                &format_args!("{}", self.tx_fifo_rempty().bit()),
-            )
-            .field(
-                "rx_fifo_wovf",
-                &format_args!("{}", self.rx_fifo_wovf().bit()),
-            )
-            .field("tx_eof", &format_args!("{}", self.tx_eof().bit()))
+            .field("tx_fifo_rempty", &self.tx_fifo_rempty())
+            .field("rx_fifo_wovf", &self.rx_fifo_wovf())
+            .field("tx_eof", &self.tx_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable TX_FIFO_REMPTY_INT."]
     #[inline(always)]
diff --git a/esp32h2/src/parl_io/int_raw.rs b/esp32h2/src/parl_io/int_raw.rs
index a49950cddd..0b62801757 100644
--- a/esp32h2/src/parl_io/int_raw.rs
+++ b/esp32h2/src/parl_io/int_raw.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "tx_fifo_rempty",
-                &format_args!("{}", self.tx_fifo_rempty().bit()),
-            )
-            .field(
-                "rx_fifo_wovf",
-                &format_args!("{}", self.rx_fifo_wovf().bit()),
-            )
-            .field("tx_eof", &format_args!("{}", self.tx_eof().bit()))
+            .field("tx_fifo_rempty", &self.tx_fifo_rempty())
+            .field("rx_fifo_wovf", &self.rx_fifo_wovf())
+            .field("tx_eof", &self.tx_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt status of TX_FIFO_REMPTY_INT."]
     #[inline(always)]
diff --git a/esp32h2/src/parl_io/int_st.rs b/esp32h2/src/parl_io/int_st.rs
index e3459c434c..f0a02381dc 100644
--- a/esp32h2/src/parl_io/int_st.rs
+++ b/esp32h2/src/parl_io/int_st.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "tx_fifo_rempty",
-                &format_args!("{}", self.tx_fifo_rempty().bit()),
-            )
-            .field(
-                "rx_fifo_wovf",
-                &format_args!("{}", self.rx_fifo_wovf().bit()),
-            )
-            .field("tx_eof", &format_args!("{}", self.tx_eof().bit()))
+            .field("tx_fifo_rempty", &self.tx_fifo_rempty())
+            .field("rx_fifo_wovf", &self.rx_fifo_wovf())
+            .field("tx_eof", &self.tx_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Parallel IO interrupt singal status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/parl_io/rx_clk_cfg.rs b/esp32h2/src/parl_io/rx_clk_cfg.rs
index 41d97f4f41..5b1df21c96 100644
--- a/esp32h2/src/parl_io/rx_clk_cfg.rs
+++ b/esp32h2/src/parl_io/rx_clk_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CLK_CFG")
-            .field(
-                "rx_clk_i_inv",
-                &format_args!("{}", self.rx_clk_i_inv().bit()),
-            )
-            .field(
-                "rx_clk_o_inv",
-                &format_args!("{}", self.rx_clk_o_inv().bit()),
-            )
+            .field("rx_clk_i_inv", &self.rx_clk_i_inv())
+            .field("rx_clk_o_inv", &self.rx_clk_o_inv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CLK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - Set this bit to invert the input Rx core clock."]
     #[inline(always)]
diff --git a/esp32h2/src/parl_io/rx_data_cfg.rs b/esp32h2/src/parl_io/rx_data_cfg.rs
index 782441df10..1df2b7993f 100644
--- a/esp32h2/src/parl_io/rx_data_cfg.rs
+++ b/esp32h2/src/parl_io/rx_data_cfg.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_DATA_CFG")
-            .field("rx_bitlen", &format_args!("{}", self.rx_bitlen().bits()))
-            .field(
-                "rx_data_order_inv",
-                &format_args!("{}", self.rx_data_order_inv().bit()),
-            )
-            .field(
-                "rx_bus_wid_sel",
-                &format_args!("{}", self.rx_bus_wid_sel().bits()),
-            )
+            .field("rx_bitlen", &self.rx_bitlen())
+            .field("rx_data_order_inv", &self.rx_data_order_inv())
+            .field("rx_bus_wid_sel", &self.rx_bus_wid_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_DATA_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 9:27 - Configures expected byte number of received data."]
     #[inline(always)]
diff --git a/esp32h2/src/parl_io/rx_genrl_cfg.rs b/esp32h2/src/parl_io/rx_genrl_cfg.rs
index 558b0ede9b..95330fa4f1 100644
--- a/esp32h2/src/parl_io/rx_genrl_cfg.rs
+++ b/esp32h2/src/parl_io/rx_genrl_cfg.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_GENRL_CFG")
-            .field(
-                "rx_gating_en",
-                &format_args!("{}", self.rx_gating_en().bit()),
-            )
-            .field(
-                "rx_timeout_thres",
-                &format_args!("{}", self.rx_timeout_thres().bits()),
-            )
-            .field(
-                "rx_timeout_en",
-                &format_args!("{}", self.rx_timeout_en().bit()),
-            )
-            .field(
-                "rx_eof_gen_sel",
-                &format_args!("{}", self.rx_eof_gen_sel().bit()),
-            )
+            .field("rx_gating_en", &self.rx_gating_en())
+            .field("rx_timeout_thres", &self.rx_timeout_thres())
+            .field("rx_timeout_en", &self.rx_timeout_en())
+            .field("rx_eof_gen_sel", &self.rx_eof_gen_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_GENRL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to enable the clock gating of output rx clock."]
     #[inline(always)]
diff --git a/esp32h2/src/parl_io/rx_mode_cfg.rs b/esp32h2/src/parl_io/rx_mode_cfg.rs
index 9cc0e559dd..20f1277bb8 100644
--- a/esp32h2/src/parl_io/rx_mode_cfg.rs
+++ b/esp32h2/src/parl_io/rx_mode_cfg.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_MODE_CFG")
-            .field(
-                "rx_ext_en_sel",
-                &format_args!("{}", self.rx_ext_en_sel().bits()),
-            )
-            .field("rx_sw_en", &format_args!("{}", self.rx_sw_en().bit()))
-            .field(
-                "rx_ext_en_inv",
-                &format_args!("{}", self.rx_ext_en_inv().bit()),
-            )
-            .field(
-                "rx_pulse_submode_sel",
-                &format_args!("{}", self.rx_pulse_submode_sel().bits()),
-            )
-            .field(
-                "rx_smp_mode_sel",
-                &format_args!("{}", self.rx_smp_mode_sel().bits()),
-            )
+            .field("rx_ext_en_sel", &self.rx_ext_en_sel())
+            .field("rx_sw_en", &self.rx_sw_en())
+            .field("rx_ext_en_inv", &self.rx_ext_en_inv())
+            .field("rx_pulse_submode_sel", &self.rx_pulse_submode_sel())
+            .field("rx_smp_mode_sel", &self.rx_smp_mode_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_MODE_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 21:24 - Configures rx external enable signal selection from IO PAD."]
     #[inline(always)]
diff --git a/esp32h2/src/parl_io/rx_st0.rs b/esp32h2/src/parl_io/rx_st0.rs
index 85fb526119..b902d61397 100644
--- a/esp32h2/src/parl_io/rx_st0.rs
+++ b/esp32h2/src/parl_io/rx_st0.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ST0")
-            .field("rx_cnt", &format_args!("{}", self.rx_cnt().bits()))
-            .field(
-                "rx_fifo_wr_bit_cnt",
-                &format_args!("{}", self.rx_fifo_wr_bit_cnt().bits()),
-            )
+            .field("rx_cnt", &self.rx_cnt())
+            .field("rx_fifo_wr_bit_cnt", &self.rx_fifo_wr_bit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ST0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Parallel IO RX status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_st0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_ST0_SPEC;
 impl crate::RegisterSpec for RX_ST0_SPEC {
diff --git a/esp32h2/src/parl_io/rx_st1.rs b/esp32h2/src/parl_io/rx_st1.rs
index f53d69a2fc..eb31daa2e2 100644
--- a/esp32h2/src/parl_io/rx_st1.rs
+++ b/esp32h2/src/parl_io/rx_st1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ST1")
-            .field(
-                "rx_fifo_rd_bit_cnt",
-                &format_args!("{}", self.rx_fifo_rd_bit_cnt().bits()),
-            )
+            .field("rx_fifo_rd_bit_cnt", &self.rx_fifo_rd_bit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ST1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Parallel IO RX status register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_st1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_ST1_SPEC;
 impl crate::RegisterSpec for RX_ST1_SPEC {
diff --git a/esp32h2/src/parl_io/rx_start_cfg.rs b/esp32h2/src/parl_io/rx_start_cfg.rs
index 2c998c6bf1..08d5d2193c 100644
--- a/esp32h2/src/parl_io/rx_start_cfg.rs
+++ b/esp32h2/src/parl_io/rx_start_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_START_CFG")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
+            .field("rx_start", &self.rx_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_START_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Set this bit to start rx data sampling."]
     #[inline(always)]
diff --git a/esp32h2/src/parl_io/st.rs b/esp32h2/src/parl_io/st.rs
index 18b48fe330..728d6ffa71 100644
--- a/esp32h2/src/parl_io/st.rs
+++ b/esp32h2/src/parl_io/st.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ST")
-            .field("tx_ready", &format_args!("{}", self.tx_ready().bit()))
+            .field("tx_ready", &self.tx_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Parallel IO module status register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ST_SPEC;
 impl crate::RegisterSpec for ST_SPEC {
diff --git a/esp32h2/src/parl_io/tx_clk_cfg.rs b/esp32h2/src/parl_io/tx_clk_cfg.rs
index 411ab4a196..2b14ef91a6 100644
--- a/esp32h2/src/parl_io/tx_clk_cfg.rs
+++ b/esp32h2/src/parl_io/tx_clk_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CLK_CFG")
-            .field(
-                "tx_clk_i_inv",
-                &format_args!("{}", self.tx_clk_i_inv().bit()),
-            )
-            .field(
-                "tx_clk_o_inv",
-                &format_args!("{}", self.tx_clk_o_inv().bit()),
-            )
+            .field("tx_clk_i_inv", &self.tx_clk_i_inv())
+            .field("tx_clk_o_inv", &self.tx_clk_o_inv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CLK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - Set this bit to invert the input Tx core clock."]
     #[inline(always)]
diff --git a/esp32h2/src/parl_io/tx_data_cfg.rs b/esp32h2/src/parl_io/tx_data_cfg.rs
index dc0e1063bd..e3c0e5c8cb 100644
--- a/esp32h2/src/parl_io/tx_data_cfg.rs
+++ b/esp32h2/src/parl_io/tx_data_cfg.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_DATA_CFG")
-            .field("tx_bitlen", &format_args!("{}", self.tx_bitlen().bits()))
-            .field(
-                "tx_data_order_inv",
-                &format_args!("{}", self.tx_data_order_inv().bit()),
-            )
-            .field(
-                "tx_bus_wid_sel",
-                &format_args!("{}", self.tx_bus_wid_sel().bits()),
-            )
+            .field("tx_bitlen", &self.tx_bitlen())
+            .field("tx_data_order_inv", &self.tx_data_order_inv())
+            .field("tx_bus_wid_sel", &self.tx_bus_wid_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_DATA_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 9:27 - Configures expected byte number of sent data."]
     #[inline(always)]
diff --git a/esp32h2/src/parl_io/tx_genrl_cfg.rs b/esp32h2/src/parl_io/tx_genrl_cfg.rs
index eed25dfdb1..819b53474f 100644
--- a/esp32h2/src/parl_io/tx_genrl_cfg.rs
+++ b/esp32h2/src/parl_io/tx_genrl_cfg.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_GENRL_CFG")
-            .field(
-                "tx_idle_value",
-                &format_args!("{}", self.tx_idle_value().bits()),
-            )
-            .field(
-                "tx_gating_en",
-                &format_args!("{}", self.tx_gating_en().bit()),
-            )
-            .field(
-                "tx_valid_output_en",
-                &format_args!("{}", self.tx_valid_output_en().bit()),
-            )
+            .field("tx_idle_value", &self.tx_idle_value())
+            .field("tx_gating_en", &self.tx_gating_en())
+            .field("tx_valid_output_en", &self.tx_valid_output_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_GENRL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 14:29 - Configures bus value of transmitter in IDLE state."]
     #[inline(always)]
diff --git a/esp32h2/src/parl_io/tx_st0.rs b/esp32h2/src/parl_io/tx_st0.rs
index ef866a2ae3..e3b75faa64 100644
--- a/esp32h2/src/parl_io/tx_st0.rs
+++ b/esp32h2/src/parl_io/tx_st0.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_ST0")
-            .field("tx_cnt", &format_args!("{}", self.tx_cnt().bits()))
-            .field(
-                "tx_fifo_rd_bit_cnt",
-                &format_args!("{}", self.tx_fifo_rd_bit_cnt().bits()),
-            )
+            .field("tx_cnt", &self.tx_cnt())
+            .field("tx_fifo_rd_bit_cnt", &self.tx_fifo_rd_bit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_ST0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Parallel IO TX status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_st0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TX_ST0_SPEC;
 impl crate::RegisterSpec for TX_ST0_SPEC {
diff --git a/esp32h2/src/parl_io/tx_start_cfg.rs b/esp32h2/src/parl_io/tx_start_cfg.rs
index fa2341b17a..fd377658e8 100644
--- a/esp32h2/src/parl_io/tx_start_cfg.rs
+++ b/esp32h2/src/parl_io/tx_start_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_START_CFG")
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
+            .field("tx_start", &self.tx_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_START_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Set this bit to start tx data transmit."]
     #[inline(always)]
diff --git a/esp32h2/src/parl_io/version.rs b/esp32h2/src/parl_io/version.rs
index b5a365001a..6640671dfb 100644
--- a/esp32h2/src/parl_io/version.rs
+++ b/esp32h2/src/parl_io/version.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version of this register file"]
     #[inline(always)]
diff --git a/esp32h2/src/pau/date.rs b/esp32h2/src/pau/date.rs
index 3b18bdc4fe..0b7173416e 100644
--- a/esp32h2/src/pau/date.rs
+++ b/esp32h2/src/pau/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/pau/int_ena.rs b/esp32h2/src/pau/int_ena.rs
index a424ba5145..011fec4c81 100644
--- a/esp32h2/src/pau/int_ena.rs
+++ b/esp32h2/src/pau/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("error", &format_args!("{}", self.error().bit()))
+            .field("done", &self.done())
+            .field("error", &self.error())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - backup done flag"]
     #[inline(always)]
diff --git a/esp32h2/src/pau/int_raw.rs b/esp32h2/src/pau/int_raw.rs
index d0b1838f1a..1003c8ece8 100644
--- a/esp32h2/src/pau/int_raw.rs
+++ b/esp32h2/src/pau/int_raw.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("error", &format_args!("{}", self.error().bit()))
+            .field("done", &self.done())
+            .field("error", &self.error())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - backup done flag"]
     #[inline(always)]
diff --git a/esp32h2/src/pau/int_st.rs b/esp32h2/src/pau/int_st.rs
index 8a0bf89170..d6834ae88d 100644
--- a/esp32h2/src/pau/int_st.rs
+++ b/esp32h2/src/pau/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("error", &format_args!("{}", self.error().bit()))
+            .field("done", &self.done())
+            .field("error", &self.error())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read only register for error and done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/pau/regdma_backup_addr.rs b/esp32h2/src/pau/regdma_backup_addr.rs
index 3789b97494..06640e6e76 100644
--- a/esp32h2/src/pau/regdma_backup_addr.rs
+++ b/esp32h2/src/pau/regdma_backup_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_BACKUP_ADDR")
-            .field(
-                "backup_addr",
-                &format_args!("{}", self.backup_addr().bits()),
-            )
+            .field("backup_addr", &self.backup_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_BACKUP_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Backup addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_backup_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REGDMA_BACKUP_ADDR_SPEC;
 impl crate::RegisterSpec for REGDMA_BACKUP_ADDR_SPEC {
diff --git a/esp32h2/src/pau/regdma_bkp_conf.rs b/esp32h2/src/pau/regdma_bkp_conf.rs
index b373fb172b..e25f46eba5 100644
--- a/esp32h2/src/pau/regdma_bkp_conf.rs
+++ b/esp32h2/src/pau/regdma_bkp_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_BKP_CONF")
-            .field(
-                "read_interval",
-                &format_args!("{}", self.read_interval().bits()),
-            )
-            .field(
-                "link_tout_thres",
-                &format_args!("{}", self.link_tout_thres().bits()),
-            )
-            .field(
-                "burst_limit",
-                &format_args!("{}", self.burst_limit().bits()),
-            )
-            .field(
-                "backup_tout_thres",
-                &format_args!("{}", self.backup_tout_thres().bits()),
-            )
+            .field("read_interval", &self.read_interval())
+            .field("link_tout_thres", &self.link_tout_thres())
+            .field("burst_limit", &self.burst_limit())
+            .field("backup_tout_thres", &self.backup_tout_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_BKP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Link read_interval"]
     #[inline(always)]
diff --git a/esp32h2/src/pau/regdma_clk_conf.rs b/esp32h2/src/pau/regdma_clk_conf.rs
index c61741bd1f..fec6254df5 100644
--- a/esp32h2/src/pau/regdma_clk_conf.rs
+++ b/esp32h2/src/pau/regdma_clk_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_CLK_CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - clock enable"]
     #[inline(always)]
diff --git a/esp32h2/src/pau/regdma_conf.rs b/esp32h2/src/pau/regdma_conf.rs
index ea713cee3a..676f794539 100644
--- a/esp32h2/src/pau/regdma_conf.rs
+++ b/esp32h2/src/pau/regdma_conf.rs
@@ -55,20 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_CONF")
-            .field("flow_err", &format_args!("{}", self.flow_err().bits()))
-            .field("to_mem", &format_args!("{}", self.to_mem().bit()))
-            .field("link_sel", &format_args!("{}", self.link_sel().bits()))
-            .field("to_mem_mac", &format_args!("{}", self.to_mem_mac().bit()))
-            .field("sel_mac", &format_args!("{}", self.sel_mac().bit()))
+            .field("flow_err", &self.flow_err())
+            .field("to_mem", &self.to_mem())
+            .field("link_sel", &self.link_sel())
+            .field("to_mem_mac", &self.to_mem_mac())
+            .field("sel_mac", &self.sel_mac())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - backup start signal"]
     #[inline(always)]
diff --git a/esp32h2/src/pau/regdma_current_link_addr.rs b/esp32h2/src/pau/regdma_current_link_addr.rs
index 4ca2373a2b..7e5133b489 100644
--- a/esp32h2/src/pau/regdma_current_link_addr.rs
+++ b/esp32h2/src/pau/regdma_current_link_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_CURRENT_LINK_ADDR")
-            .field(
-                "current_link_addr",
-                &format_args!("{}", self.current_link_addr().bits()),
-            )
+            .field("current_link_addr", &self.current_link_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_CURRENT_LINK_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "current link addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_current_link_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REGDMA_CURRENT_LINK_ADDR_SPEC;
 impl crate::RegisterSpec for REGDMA_CURRENT_LINK_ADDR_SPEC {
diff --git a/esp32h2/src/pau/regdma_link_0_addr.rs b/esp32h2/src/pau/regdma_link_0_addr.rs
index f415b2ede1..64d3ebfd0a 100644
--- a/esp32h2/src/pau/regdma_link_0_addr.rs
+++ b/esp32h2/src/pau/regdma_link_0_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_LINK_0_ADDR")
-            .field(
-                "link_addr_0",
-                &format_args!("{}", self.link_addr_0().bits()),
-            )
+            .field("link_addr_0", &self.link_addr_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - link_0_addr reg"]
     #[inline(always)]
diff --git a/esp32h2/src/pau/regdma_link_1_addr.rs b/esp32h2/src/pau/regdma_link_1_addr.rs
index 2974370620..c0d1614d2e 100644
--- a/esp32h2/src/pau/regdma_link_1_addr.rs
+++ b/esp32h2/src/pau/regdma_link_1_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_LINK_1_ADDR")
-            .field(
-                "link_addr_1",
-                &format_args!("{}", self.link_addr_1().bits()),
-            )
+            .field("link_addr_1", &self.link_addr_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Link_1_addr reg"]
     #[inline(always)]
diff --git a/esp32h2/src/pau/regdma_link_2_addr.rs b/esp32h2/src/pau/regdma_link_2_addr.rs
index dc5d14f41e..913a395db9 100644
--- a/esp32h2/src/pau/regdma_link_2_addr.rs
+++ b/esp32h2/src/pau/regdma_link_2_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_LINK_2_ADDR")
-            .field(
-                "link_addr_2",
-                &format_args!("{}", self.link_addr_2().bits()),
-            )
+            .field("link_addr_2", &self.link_addr_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Link_2_addr reg"]
     #[inline(always)]
diff --git a/esp32h2/src/pau/regdma_link_3_addr.rs b/esp32h2/src/pau/regdma_link_3_addr.rs
index d8840a9794..1a77662e9c 100644
--- a/esp32h2/src/pau/regdma_link_3_addr.rs
+++ b/esp32h2/src/pau/regdma_link_3_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_LINK_3_ADDR")
-            .field(
-                "link_addr_3",
-                &format_args!("{}", self.link_addr_3().bits()),
-            )
+            .field("link_addr_3", &self.link_addr_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Link_3_addr reg"]
     #[inline(always)]
diff --git a/esp32h2/src/pau/regdma_link_mac_addr.rs b/esp32h2/src/pau/regdma_link_mac_addr.rs
index 9e524ad211..0781e7a9a0 100644
--- a/esp32h2/src/pau/regdma_link_mac_addr.rs
+++ b/esp32h2/src/pau/regdma_link_mac_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_LINK_MAC_ADDR")
-            .field(
-                "link_addr_mac",
-                &format_args!("{}", self.link_addr_mac().bits()),
-            )
+            .field("link_addr_mac", &self.link_addr_mac())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_MAC_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Link_mac_addr reg"]
     #[inline(always)]
diff --git a/esp32h2/src/pau/regdma_mem_addr.rs b/esp32h2/src/pau/regdma_mem_addr.rs
index b6fa3aa6d7..417bf965b3 100644
--- a/esp32h2/src/pau/regdma_mem_addr.rs
+++ b/esp32h2/src/pau/regdma_mem_addr.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_MEM_ADDR")
-            .field("mem_addr", &format_args!("{}", self.mem_addr().bits()))
+            .field("mem_addr", &self.mem_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_MEM_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_mem_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REGDMA_MEM_ADDR_SPEC;
 impl crate::RegisterSpec for REGDMA_MEM_ADDR_SPEC {
diff --git a/esp32h2/src/pau/retention_cfg.rs b/esp32h2/src/pau/retention_cfg.rs
index 3065e11d78..33850d9486 100644
--- a/esp32h2/src/pau/retention_cfg.rs
+++ b/esp32h2/src/pau/retention_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_CFG")
-            .field(
-                "ret_inv_cfg",
-                &format_args!("{}", self.ret_inv_cfg().bits()),
-            )
+            .field("ret_inv_cfg", &self.ret_inv_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - retention inv scan out"]
     #[inline(always)]
diff --git a/esp32h2/src/pau/retention_link_base.rs b/esp32h2/src/pau/retention_link_base.rs
index 4991b8f7b0..a1728a51c3 100644
--- a/esp32h2/src/pau/retention_link_base.rs
+++ b/esp32h2/src/pau/retention_link_base.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_LINK_BASE")
-            .field(
-                "link_base_addr",
-                &format_args!("{}", self.link_base_addr().bits()),
-            )
+            .field("link_base_addr", &self.link_base_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_LINK_BASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:26 - retention dma link base"]
     #[inline(always)]
diff --git a/esp32h2/src/pcnt/ctrl.rs b/esp32h2/src/pcnt/ctrl.rs
index 366f491032..5c3a942e13 100644
--- a/esp32h2/src/pcnt/ctrl.rs
+++ b/esp32h2/src/pcnt/ctrl.rs
@@ -95,36 +95,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("cnt_rst_u0", &format_args!("{}", self.cnt_rst_u0().bit()))
-            .field("cnt_rst_u1", &format_args!("{}", self.cnt_rst_u1().bit()))
-            .field("cnt_rst_u2", &format_args!("{}", self.cnt_rst_u2().bit()))
-            .field("cnt_rst_u3", &format_args!("{}", self.cnt_rst_u3().bit()))
-            .field(
-                "cnt_pause_u0",
-                &format_args!("{}", self.cnt_pause_u0().bit()),
-            )
-            .field(
-                "cnt_pause_u1",
-                &format_args!("{}", self.cnt_pause_u1().bit()),
-            )
-            .field(
-                "cnt_pause_u2",
-                &format_args!("{}", self.cnt_pause_u2().bit()),
-            )
-            .field(
-                "cnt_pause_u3",
-                &format_args!("{}", self.cnt_pause_u3().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("cnt_rst_u0", &self.cnt_rst_u0())
+            .field("cnt_rst_u1", &self.cnt_rst_u1())
+            .field("cnt_rst_u2", &self.cnt_rst_u2())
+            .field("cnt_rst_u3", &self.cnt_rst_u3())
+            .field("cnt_pause_u0", &self.cnt_pause_u0())
+            .field("cnt_pause_u1", &self.cnt_pause_u1())
+            .field("cnt_pause_u2", &self.cnt_pause_u2())
+            .field("cnt_pause_u3", &self.cnt_pause_u3())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Set this bit to clear unit(0-3)'s counter."]
     #[doc = ""]
diff --git a/esp32h2/src/pcnt/date.rs b/esp32h2/src/pcnt/date.rs
index a897bc894c..de06812323 100644
--- a/esp32h2/src/pcnt/date.rs
+++ b/esp32h2/src/pcnt/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/pcnt/int_ena.rs b/esp32h2/src/pcnt/int_ena.rs
index 4423a16c83..7372693fe3 100644
--- a/esp32h2/src/pcnt/int_ena.rs
+++ b/esp32h2/src/pcnt/int_ena.rs
@@ -47,31 +47,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
     #[doc = ""]
diff --git a/esp32h2/src/pcnt/int_raw.rs b/esp32h2/src/pcnt/int_raw.rs
index 9730ee9237..1c6db4c12b 100644
--- a/esp32h2/src/pcnt/int_raw.rs
+++ b/esp32h2/src/pcnt/int_raw.rs
@@ -47,31 +47,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
     #[doc = ""]
diff --git a/esp32h2/src/pcnt/int_st.rs b/esp32h2/src/pcnt/int_st.rs
index d1a59c1bf3..870d7ad253 100644
--- a/esp32h2/src/pcnt/int_st.rs
+++ b/esp32h2/src/pcnt/int_st.rs
@@ -43,31 +43,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/pcnt/u_cnt.rs b/esp32h2/src/pcnt/u_cnt.rs
index 34bef2c06c..7a45c58a0d 100644
--- a/esp32h2/src/pcnt/u_cnt.rs
+++ b/esp32h2/src/pcnt/u_cnt.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("U_CNT")
-            .field("cnt", &format_args!("{}", self.cnt().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("U_CNT").field("cnt", &self.cnt()).finish()
     }
 }
 #[doc = "Counter value for unit %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32h2/src/pcnt/u_status.rs b/esp32h2/src/pcnt/u_status.rs
index 408d450824..9d516e2c99 100644
--- a/esp32h2/src/pcnt/u_status.rs
+++ b/esp32h2/src/pcnt/u_status.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("U_STATUS")
-            .field("zero_mode", &format_args!("{}", self.zero_mode().bits()))
-            .field("thres1", &format_args!("{}", self.thres1().bit()))
-            .field("thres0", &format_args!("{}", self.thres0().bit()))
-            .field("l_lim", &format_args!("{}", self.l_lim().bit()))
-            .field("h_lim", &format_args!("{}", self.h_lim().bit()))
-            .field("zero", &format_args!("{}", self.zero().bit()))
+            .field("zero_mode", &self.zero_mode())
+            .field("thres1", &self.thres1())
+            .field("thres0", &self.thres0())
+            .field("l_lim", &self.l_lim())
+            .field("h_lim", &self.h_lim())
+            .field("zero", &self.zero())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "PNCT UNIT%s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct U_STATUS_SPEC;
 impl crate::RegisterSpec for U_STATUS_SPEC {
diff --git a/esp32h2/src/pcnt/unit/conf0.rs b/esp32h2/src/pcnt/unit/conf0.rs
index 96f657d7f6..11e74f3113 100644
--- a/esp32h2/src/pcnt/unit/conf0.rs
+++ b/esp32h2/src/pcnt/unit/conf0.rs
@@ -325,69 +325,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field(
-                "filter_thres",
-                &format_args!("{}", self.filter_thres().bits()),
-            )
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
-            .field("thr_zero_en", &format_args!("{}", self.thr_zero_en().bit()))
-            .field(
-                "thr_h_lim_en",
-                &format_args!("{}", self.thr_h_lim_en().bit()),
-            )
-            .field(
-                "thr_l_lim_en",
-                &format_args!("{}", self.thr_l_lim_en().bit()),
-            )
-            .field(
-                "thr_thres0_en",
-                &format_args!("{}", self.thr_thres0_en().bit()),
-            )
-            .field(
-                "thr_thres1_en",
-                &format_args!("{}", self.thr_thres1_en().bit()),
-            )
-            .field(
-                "ch0_neg_mode",
-                &format_args!("{}", self.ch0_neg_mode().bits()),
-            )
-            .field(
-                "ch1_neg_mode",
-                &format_args!("{}", self.ch1_neg_mode().bits()),
-            )
-            .field(
-                "ch0_pos_mode",
-                &format_args!("{}", self.ch0_pos_mode().bits()),
-            )
-            .field(
-                "ch1_pos_mode",
-                &format_args!("{}", self.ch1_pos_mode().bits()),
-            )
-            .field(
-                "ch0_hctrl_mode",
-                &format_args!("{}", self.ch0_hctrl_mode().bits()),
-            )
-            .field(
-                "ch1_hctrl_mode",
-                &format_args!("{}", self.ch1_hctrl_mode().bits()),
-            )
-            .field(
-                "ch0_lctrl_mode",
-                &format_args!("{}", self.ch0_lctrl_mode().bits()),
-            )
-            .field(
-                "ch1_lctrl_mode",
-                &format_args!("{}", self.ch1_lctrl_mode().bits()),
-            )
+            .field("filter_thres", &self.filter_thres())
+            .field("filter_en", &self.filter_en())
+            .field("thr_zero_en", &self.thr_zero_en())
+            .field("thr_h_lim_en", &self.thr_h_lim_en())
+            .field("thr_l_lim_en", &self.thr_l_lim_en())
+            .field("thr_thres0_en", &self.thr_thres0_en())
+            .field("thr_thres1_en", &self.thr_thres1_en())
+            .field("ch0_neg_mode", &self.ch0_neg_mode())
+            .field("ch1_neg_mode", &self.ch1_neg_mode())
+            .field("ch0_pos_mode", &self.ch0_pos_mode())
+            .field("ch1_pos_mode", &self.ch1_pos_mode())
+            .field("ch0_hctrl_mode", &self.ch0_hctrl_mode())
+            .field("ch1_hctrl_mode", &self.ch1_hctrl_mode())
+            .field("ch0_lctrl_mode", &self.ch0_lctrl_mode())
+            .field("ch1_lctrl_mode", &self.ch1_lctrl_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
     #[inline(always)]
diff --git a/esp32h2/src/pcnt/unit/conf1.rs b/esp32h2/src/pcnt/unit/conf1.rs
index 62e92aa446..d516d127e6 100644
--- a/esp32h2/src/pcnt/unit/conf1.rs
+++ b/esp32h2/src/pcnt/unit/conf1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field("cnt_thres0", &format_args!("{}", self.cnt_thres0().bits()))
-            .field("cnt_thres1", &format_args!("{}", self.cnt_thres1().bits()))
+            .field("cnt_thres0", &self.cnt_thres0())
+            .field("cnt_thres1", &self.cnt_thres1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the thres0 value for unit %s."]
     #[inline(always)]
diff --git a/esp32h2/src/pcnt/unit/conf2.rs b/esp32h2/src/pcnt/unit/conf2.rs
index d397f194e8..71732001d5 100644
--- a/esp32h2/src/pcnt/unit/conf2.rs
+++ b/esp32h2/src/pcnt/unit/conf2.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF2")
-            .field("cnt_h_lim", &format_args!("{}", self.cnt_h_lim().bits()))
-            .field("cnt_l_lim", &format_args!("{}", self.cnt_l_lim().bits()))
+            .field("cnt_h_lim", &self.cnt_h_lim())
+            .field("cnt_l_lim", &self.cnt_l_lim())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the thr_h_lim value for unit %s. When pluse_cnt reaches this value, the counter will be cleared to 0."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/adc_inv_phase_conf.rs b/esp32h2/src/pcr/adc_inv_phase_conf.rs
index 70792fc83b..97a465d65f 100644
--- a/esp32h2/src/pcr/adc_inv_phase_conf.rs
+++ b/esp32h2/src/pcr/adc_inv_phase_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADC_INV_PHASE_CONF")
-            .field(
-                "clk_adc_inv_phase_ena",
-                &format_args!("{}", self.clk_adc_inv_phase_ena().bit()),
-            )
+            .field("clk_adc_inv_phase_ena", &self.clk_adc_inv_phase_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADC_INV_PHASE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - xxxx"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/aes_conf.rs b/esp32h2/src/pcr/aes_conf.rs
index 9d4c62eaf1..653728d6cf 100644
--- a/esp32h2/src/pcr/aes_conf.rs
+++ b/esp32h2/src/pcr/aes_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AES_CONF")
-            .field("aes_clk_en", &format_args!("{}", self.aes_clk_en().bit()))
-            .field("aes_rst_en", &format_args!("{}", self.aes_rst_en().bit()))
-            .field("aes_ready", &format_args!("{}", self.aes_ready().bit()))
+            .field("aes_clk_en", &self.aes_clk_en())
+            .field("aes_rst_en", &self.aes_rst_en())
+            .field("aes_ready", &self.aes_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AES_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable aes clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/ahb_freq_conf.rs b/esp32h2/src/pcr/ahb_freq_conf.rs
index 76394b77b5..7c1a07c469 100644
--- a/esp32h2/src/pcr/ahb_freq_conf.rs
+++ b/esp32h2/src/pcr/ahb_freq_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_FREQ_CONF")
-            .field(
-                "ahb_div_num",
-                &format_args!("{}", self.ahb_div_num().bits()),
-            )
+            .field("ahb_div_num", &self.ahb_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_FREQ_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_CPU_DIV_NUM."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/apb_freq_conf.rs b/esp32h2/src/pcr/apb_freq_conf.rs
index 937861ac1f..d9c02223bc 100644
--- a/esp32h2/src/pcr/apb_freq_conf.rs
+++ b/esp32h2/src/pcr/apb_freq_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_FREQ_CONF")
-            .field(
-                "apb_decrease_div_num",
-                &format_args!("{}", self.apb_decrease_div_num().bits()),
-            )
-            .field(
-                "apb_div_num",
-                &format_args!("{}", self.apb_div_num().bits()),
-            )
+            .field("apb_decrease_div_num", &self.apb_decrease_div_num())
+            .field("apb_div_num", &self.apb_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_FREQ_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be automatically down to clk_apb_decrease only when no access is on apb-bus, and will recover to the previous frequency when a new access appears on apb-bus. Set as one within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note that enable this function will reduce performance. Users can set this field as zero to disable the auto-decrease-apb-freq function. By default, this function is disable."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/assist_conf.rs b/esp32h2/src/pcr/assist_conf.rs
index dfefe1f759..f4eaf39249 100644
--- a/esp32h2/src/pcr/assist_conf.rs
+++ b/esp32h2/src/pcr/assist_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ASSIST_CONF")
-            .field(
-                "assist_clk_en",
-                &format_args!("{}", self.assist_clk_en().bit()),
-            )
-            .field(
-                "assist_rst_en",
-                &format_args!("{}", self.assist_rst_en().bit()),
-            )
+            .field("assist_clk_en", &self.assist_clk_en())
+            .field("assist_rst_en", &self.assist_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ASSIST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable assist clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/bus_clk_update.rs b/esp32h2/src/pcr/bus_clk_update.rs
index f3c7940501..1adaf38c6e 100644
--- a/esp32h2/src/pcr/bus_clk_update.rs
+++ b/esp32h2/src/pcr/bus_clk_update.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_CLK_UPDATE")
-            .field(
-                "bus_clock_update",
-                &format_args!("{}", self.bus_clock_update().bit()),
-            )
+            .field("bus_clock_update", &self.bus_clock_update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_CLK_UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - xxxx"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/cache_conf.rs b/esp32h2/src/pcr/cache_conf.rs
index c914a11bc1..7f7b220aa0 100644
--- a/esp32h2/src/pcr/cache_conf.rs
+++ b/esp32h2/src/pcr/cache_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_CONF")
-            .field(
-                "cache_clk_en",
-                &format_args!("{}", self.cache_clk_en().bit()),
-            )
-            .field(
-                "cache_rst_en",
-                &format_args!("{}", self.cache_rst_en().bit()),
-            )
+            .field("cache_clk_en", &self.cache_clk_en())
+            .field("cache_rst_en", &self.cache_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable cache clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/clock_gate.rs b/esp32h2/src/pcr/clock_gate.rs
index 8a69245aaa..2106d9ac93 100644
--- a/esp32h2/src/pcr/clock_gate.rs
+++ b/esp32h2/src/pcr/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit as 1 to force on clock gating."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/cpu_freq_conf.rs b/esp32h2/src/pcr/cpu_freq_conf.rs
index 1d2ef1a9c6..d5fb9c216b 100644
--- a/esp32h2/src/pcr/cpu_freq_conf.rs
+++ b/esp32h2/src/pcr/cpu_freq_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_FREQ_CONF")
-            .field(
-                "cpu_div_num",
-                &format_args!("{}", self.cpu_div_num().bits()),
-            )
+            .field("cpu_div_num", &self.cpu_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_FREQ_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/cpu_waiti_conf.rs b/esp32h2/src/pcr/cpu_waiti_conf.rs
index 9940c6dbcc..f75157c733 100644
--- a/esp32h2/src/pcr/cpu_waiti_conf.rs
+++ b/esp32h2/src/pcr/cpu_waiti_conf.rs
@@ -40,31 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_WAITI_CONF")
-            .field(
-                "cpuperiod_sel",
-                &format_args!("{}", self.cpuperiod_sel().bits()),
-            )
-            .field(
-                "pll_freq_sel",
-                &format_args!("{}", self.pll_freq_sel().bit()),
-            )
-            .field(
-                "cpu_wait_mode_force_on",
-                &format_args!("{}", self.cpu_wait_mode_force_on().bit()),
-            )
-            .field(
-                "cpu_waiti_delay_num",
-                &format_args!("{}", self.cpu_waiti_delay_num().bits()),
-            )
+            .field("cpuperiod_sel", &self.cpuperiod_sel())
+            .field("pll_freq_sel", &self.pll_freq_sel())
+            .field("cpu_wait_mode_force_on", &self.cpu_wait_mode_force_on())
+            .field("cpu_waiti_delay_num", &self.cpu_waiti_delay_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_WAITI_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - Set 1 to force cpu_waiti_clk enable."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/ctrl_32k_conf.rs b/esp32h2/src/pcr/ctrl_32k_conf.rs
index 40debb2e91..f25a6e4923 100644
--- a/esp32h2/src/pcr/ctrl_32k_conf.rs
+++ b/esp32h2/src/pcr/ctrl_32k_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL_32K_CONF")
-            .field(
-                "clk_32k_sel",
-                &format_args!("{}", self.clk_32k_sel().bits()),
-            )
-            .field(
-                "_32k_modem_sel",
-                &format_args!("{}", self._32k_modem_sel().bits()),
-            )
+            .field("clk_32k_sel", &self.clk_32k_sel())
+            .field("_32k_modem_sel", &self._32k_modem_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_32K_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field indicates which one 32KHz clock will be used by timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/ctrl_clk_out_en.rs b/esp32h2/src/pcr/ctrl_clk_out_en.rs
index 176e382f0d..e4347bc66d 100644
--- a/esp32h2/src/pcr/ctrl_clk_out_en.rs
+++ b/esp32h2/src/pcr/ctrl_clk_out_en.rs
@@ -71,34 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL_CLK_OUT_EN")
-            .field("clk8_oen", &format_args!("{}", self.clk8_oen().bit()))
-            .field("clk16_oen", &format_args!("{}", self.clk16_oen().bit()))
-            .field("clk32_oen", &format_args!("{}", self.clk32_oen().bit()))
-            .field(
-                "clk_adc_inf_oen",
-                &format_args!("{}", self.clk_adc_inf_oen().bit()),
-            )
-            .field(
-                "clk_dfm_inf_oen",
-                &format_args!("{}", self.clk_dfm_inf_oen().bit()),
-            )
-            .field(
-                "clk_sdm_mod_oen",
-                &format_args!("{}", self.clk_sdm_mod_oen().bit()),
-            )
-            .field(
-                "clk_xtal_oen",
-                &format_args!("{}", self.clk_xtal_oen().bit()),
-            )
+            .field("clk8_oen", &self.clk8_oen())
+            .field("clk16_oen", &self.clk16_oen())
+            .field("clk32_oen", &self.clk32_oen())
+            .field("clk_adc_inf_oen", &self.clk_adc_inf_oen())
+            .field("clk_dfm_inf_oen", &self.clk_dfm_inf_oen())
+            .field("clk_sdm_mod_oen", &self.clk_sdm_mod_oen())
+            .field("clk_xtal_oen", &self.clk_xtal_oen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_CLK_OUT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable 8m clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/ctrl_tick_conf.rs b/esp32h2/src/pcr/ctrl_tick_conf.rs
index 6cbc05356e..6d3f575c0e 100644
--- a/esp32h2/src/pcr/ctrl_tick_conf.rs
+++ b/esp32h2/src/pcr/ctrl_tick_conf.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL_TICK_CONF")
-            .field(
-                "xtal_tick_num",
-                &format_args!("{}", self.xtal_tick_num().bits()),
-            )
-            .field(
-                "fosc_tick_num",
-                &format_args!("{}", self.fosc_tick_num().bits()),
-            )
-            .field("tick_enable", &format_args!("{}", self.tick_enable().bit()))
-            .field(
-                "rst_tick_cnt",
-                &format_args!("{}", self.rst_tick_cnt().bit()),
-            )
+            .field("xtal_tick_num", &self.xtal_tick_num())
+            .field("fosc_tick_num", &self.fosc_tick_num())
+            .field("tick_enable", &self.tick_enable())
+            .field("rst_tick_cnt", &self.rst_tick_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_TICK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/date.rs b/esp32h2/src/pcr/date.rs
index fcd4e5e71a..abf578689d 100644
--- a/esp32h2/src/pcr/date.rs
+++ b/esp32h2/src/pcr/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/pcr/ds_conf.rs b/esp32h2/src/pcr/ds_conf.rs
index cf3e1ac9b2..ec19f36322 100644
--- a/esp32h2/src/pcr/ds_conf.rs
+++ b/esp32h2/src/pcr/ds_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DS_CONF")
-            .field("ds_clk_en", &format_args!("{}", self.ds_clk_en().bit()))
-            .field("ds_rst_en", &format_args!("{}", self.ds_rst_en().bit()))
-            .field("ds_ready", &format_args!("{}", self.ds_ready().bit()))
+            .field("ds_clk_en", &self.ds_clk_en())
+            .field("ds_rst_en", &self.ds_rst_en())
+            .field("ds_ready", &self.ds_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable ds clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/ecc_conf.rs b/esp32h2/src/pcr/ecc_conf.rs
index 5809d0a127..3ec9d89a53 100644
--- a/esp32h2/src/pcr/ecc_conf.rs
+++ b/esp32h2/src/pcr/ecc_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_CONF")
-            .field("ecc_clk_en", &format_args!("{}", self.ecc_clk_en().bit()))
-            .field("ecc_rst_en", &format_args!("{}", self.ecc_rst_en().bit()))
-            .field("ecc_ready", &format_args!("{}", self.ecc_ready().bit()))
+            .field("ecc_clk_en", &self.ecc_clk_en())
+            .field("ecc_rst_en", &self.ecc_rst_en())
+            .field("ecc_ready", &self.ecc_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable ecc clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/ecc_pd_ctrl.rs b/esp32h2/src/pcr/ecc_pd_ctrl.rs
index ca904cb3e1..5a8cbc49e1 100644
--- a/esp32h2/src/pcr/ecc_pd_ctrl.rs
+++ b/esp32h2/src/pcr/ecc_pd_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_PD_CTRL")
-            .field("ecc_mem_pd", &format_args!("{}", self.ecc_mem_pd().bit()))
-            .field(
-                "ecc_mem_force_pu",
-                &format_args!("{}", self.ecc_mem_force_pu().bit()),
-            )
-            .field(
-                "ecc_mem_force_pd",
-                &format_args!("{}", self.ecc_mem_force_pd().bit()),
-            )
+            .field("ecc_mem_pd", &self.ecc_mem_pd())
+            .field("ecc_mem_force_pu", &self.ecc_mem_force_pu())
+            .field("ecc_mem_force_pd", &self.ecc_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to power down ecc internal memory."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/ecdsa_conf.rs b/esp32h2/src/pcr/ecdsa_conf.rs
index a8b9d661a2..7ca194017e 100644
--- a/esp32h2/src/pcr/ecdsa_conf.rs
+++ b/esp32h2/src/pcr/ecdsa_conf.rs
@@ -33,24 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECDSA_CONF")
-            .field(
-                "ecdsa_clk_en",
-                &format_args!("{}", self.ecdsa_clk_en().bit()),
-            )
-            .field(
-                "ecdsa_rst_en",
-                &format_args!("{}", self.ecdsa_rst_en().bit()),
-            )
-            .field("ecdsa_ready", &format_args!("{}", self.ecdsa_ready().bit()))
+            .field("ecdsa_clk_en", &self.ecdsa_clk_en())
+            .field("ecdsa_rst_en", &self.ecdsa_rst_en())
+            .field("ecdsa_ready", &self.ecdsa_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECDSA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable ecdsa clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/etm_conf.rs b/esp32h2/src/pcr/etm_conf.rs
index b959abf7d1..e3d9c8f321 100644
--- a/esp32h2/src/pcr/etm_conf.rs
+++ b/esp32h2/src/pcr/etm_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_CONF")
-            .field("etm_clk_en", &format_args!("{}", self.etm_clk_en().bit()))
-            .field("etm_rst_en", &format_args!("{}", self.etm_rst_en().bit()))
-            .field("etm_ready", &format_args!("{}", self.etm_ready().bit()))
+            .field("etm_clk_en", &self.etm_clk_en())
+            .field("etm_rst_en", &self.etm_rst_en())
+            .field("etm_ready", &self.etm_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable etm clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/fpga_debug.rs b/esp32h2/src/pcr/fpga_debug.rs
index 7b2c26deaf..f091892f66 100644
--- a/esp32h2/src/pcr/fpga_debug.rs
+++ b/esp32h2/src/pcr/fpga_debug.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FPGA_DEBUG")
-            .field("fpga_debug", &format_args!("{}", self.fpga_debug().bits()))
+            .field("fpga_debug", &self.fpga_debug())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FPGA_DEBUG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Only used in fpga debug."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/gdma_conf.rs b/esp32h2/src/pcr/gdma_conf.rs
index d56c39e7bb..cb95e81122 100644
--- a/esp32h2/src/pcr/gdma_conf.rs
+++ b/esp32h2/src/pcr/gdma_conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GDMA_CONF")
-            .field("gdma_clk_en", &format_args!("{}", self.gdma_clk_en().bit()))
-            .field("gdma_rst_en", &format_args!("{}", self.gdma_rst_en().bit()))
+            .field("gdma_clk_en", &self.gdma_clk_en())
+            .field("gdma_rst_en", &self.gdma_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GDMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable gdma clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/hmac_conf.rs b/esp32h2/src/pcr/hmac_conf.rs
index cb0049c858..811460d5da 100644
--- a/esp32h2/src/pcr/hmac_conf.rs
+++ b/esp32h2/src/pcr/hmac_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HMAC_CONF")
-            .field("hmac_clk_en", &format_args!("{}", self.hmac_clk_en().bit()))
-            .field("hmac_rst_en", &format_args!("{}", self.hmac_rst_en().bit()))
-            .field("hmac_ready", &format_args!("{}", self.hmac_ready().bit()))
+            .field("hmac_clk_en", &self.hmac_clk_en())
+            .field("hmac_rst_en", &self.hmac_rst_en())
+            .field("hmac_ready", &self.hmac_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HMAC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable hmac clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/i2c0_conf.rs b/esp32h2/src/pcr/i2c0_conf.rs
index e52854059a..8bed2b97c5 100644
--- a/esp32h2/src/pcr/i2c0_conf.rs
+++ b/esp32h2/src/pcr/i2c0_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C0_CONF")
-            .field("i2c0_clk_en", &format_args!("{}", self.i2c0_clk_en().bit()))
-            .field("i2c0_rst_en", &format_args!("{}", self.i2c0_rst_en().bit()))
-            .field("i2c0_ready", &format_args!("{}", self.i2c0_ready().bit()))
+            .field("i2c0_clk_en", &self.i2c0_clk_en())
+            .field("i2c0_rst_en", &self.i2c0_rst_en())
+            .field("i2c0_ready", &self.i2c0_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C0_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable i2c apb clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/i2c0_sclk_conf.rs b/esp32h2/src/pcr/i2c0_sclk_conf.rs
index 1957291dc7..7bb750e273 100644
--- a/esp32h2/src/pcr/i2c0_sclk_conf.rs
+++ b/esp32h2/src/pcr/i2c0_sclk_conf.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C0_SCLK_CONF")
-            .field(
-                "i2c0_sclk_div_a",
-                &format_args!("{}", self.i2c0_sclk_div_a().bits()),
-            )
-            .field(
-                "i2c0_sclk_div_b",
-                &format_args!("{}", self.i2c0_sclk_div_b().bits()),
-            )
-            .field(
-                "i2c0_sclk_div_num",
-                &format_args!("{}", self.i2c0_sclk_div_num().bits()),
-            )
-            .field(
-                "i2c0_sclk_sel",
-                &format_args!("{}", self.i2c0_sclk_sel().bit()),
-            )
-            .field(
-                "i2c0_sclk_en",
-                &format_args!("{}", self.i2c0_sclk_en().bit()),
-            )
+            .field("i2c0_sclk_div_a", &self.i2c0_sclk_div_a())
+            .field("i2c0_sclk_div_b", &self.i2c0_sclk_div_b())
+            .field("i2c0_sclk_div_num", &self.i2c0_sclk_div_num())
+            .field("i2c0_sclk_sel", &self.i2c0_sclk_sel())
+            .field("i2c0_sclk_en", &self.i2c0_sclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C0_SCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the i2c function clock."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/i2c1_conf.rs b/esp32h2/src/pcr/i2c1_conf.rs
index cab651fd83..03542dd0c8 100644
--- a/esp32h2/src/pcr/i2c1_conf.rs
+++ b/esp32h2/src/pcr/i2c1_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C1_CONF")
-            .field("i2c1_clk_en", &format_args!("{}", self.i2c1_clk_en().bit()))
-            .field("i2c1_rst_en", &format_args!("{}", self.i2c1_rst_en().bit()))
-            .field("i2c1_ready", &format_args!("{}", self.i2c1_ready().bit()))
+            .field("i2c1_clk_en", &self.i2c1_clk_en())
+            .field("i2c1_rst_en", &self.i2c1_rst_en())
+            .field("i2c1_ready", &self.i2c1_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C1_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable i2c apb clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/i2c1_sclk_conf.rs b/esp32h2/src/pcr/i2c1_sclk_conf.rs
index 8f64d88717..46ba8a0b04 100644
--- a/esp32h2/src/pcr/i2c1_sclk_conf.rs
+++ b/esp32h2/src/pcr/i2c1_sclk_conf.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C1_SCLK_CONF")
-            .field(
-                "i2c1_sclk_div_a",
-                &format_args!("{}", self.i2c1_sclk_div_a().bits()),
-            )
-            .field(
-                "i2c1_sclk_div_b",
-                &format_args!("{}", self.i2c1_sclk_div_b().bits()),
-            )
-            .field(
-                "i2c1_sclk_div_num",
-                &format_args!("{}", self.i2c1_sclk_div_num().bits()),
-            )
-            .field(
-                "i2c1_sclk_sel",
-                &format_args!("{}", self.i2c1_sclk_sel().bit()),
-            )
-            .field(
-                "i2c1_sclk_en",
-                &format_args!("{}", self.i2c1_sclk_en().bit()),
-            )
+            .field("i2c1_sclk_div_a", &self.i2c1_sclk_div_a())
+            .field("i2c1_sclk_div_b", &self.i2c1_sclk_div_b())
+            .field("i2c1_sclk_div_num", &self.i2c1_sclk_div_num())
+            .field("i2c1_sclk_sel", &self.i2c1_sclk_sel())
+            .field("i2c1_sclk_en", &self.i2c1_sclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C1_SCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the i2c function clock."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/i2s_conf.rs b/esp32h2/src/pcr/i2s_conf.rs
index 1046761304..9efcc671e9 100644
--- a/esp32h2/src/pcr/i2s_conf.rs
+++ b/esp32h2/src/pcr/i2s_conf.rs
@@ -40,25 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S_CONF")
-            .field("i2s_clk_en", &format_args!("{}", self.i2s_clk_en().bit()))
-            .field("i2s_rst_en", &format_args!("{}", self.i2s_rst_en().bit()))
-            .field(
-                "i2s_rx_ready",
-                &format_args!("{}", self.i2s_rx_ready().bit()),
-            )
-            .field(
-                "i2s_tx_ready",
-                &format_args!("{}", self.i2s_tx_ready().bit()),
-            )
+            .field("i2s_clk_en", &self.i2s_clk_en())
+            .field("i2s_rst_en", &self.i2s_rst_en())
+            .field("i2s_rx_ready", &self.i2s_rx_ready())
+            .field("i2s_tx_ready", &self.i2s_tx_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable i2s apb clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/i2s_rx_clkm_conf.rs b/esp32h2/src/pcr/i2s_rx_clkm_conf.rs
index f972604f70..50b583dc4d 100644
--- a/esp32h2/src/pcr/i2s_rx_clkm_conf.rs
+++ b/esp32h2/src/pcr/i2s_rx_clkm_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S_RX_CLKM_CONF")
-            .field(
-                "i2s_rx_clkm_div_num",
-                &format_args!("{}", self.i2s_rx_clkm_div_num().bits()),
-            )
-            .field(
-                "i2s_rx_clkm_sel",
-                &format_args!("{}", self.i2s_rx_clkm_sel().bits()),
-            )
-            .field(
-                "i2s_rx_clkm_en",
-                &format_args!("{}", self.i2s_rx_clkm_en().bit()),
-            )
-            .field(
-                "i2s_mclk_sel",
-                &format_args!("{}", self.i2s_mclk_sel().bit()),
-            )
+            .field("i2s_rx_clkm_div_num", &self.i2s_rx_clkm_div_num())
+            .field("i2s_rx_clkm_sel", &self.i2s_rx_clkm_sel())
+            .field("i2s_rx_clkm_en", &self.i2s_rx_clkm_en())
+            .field("i2s_mclk_sel", &self.i2s_mclk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S_RX_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 12:19 - Integral I2S clock divider value"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/i2s_rx_clkm_div_conf.rs b/esp32h2/src/pcr/i2s_rx_clkm_div_conf.rs
index 6e8d3a6dc5..6bbb998952 100644
--- a/esp32h2/src/pcr/i2s_rx_clkm_div_conf.rs
+++ b/esp32h2/src/pcr/i2s_rx_clkm_div_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S_RX_CLKM_DIV_CONF")
-            .field(
-                "i2s_rx_clkm_div_z",
-                &format_args!("{}", self.i2s_rx_clkm_div_z().bits()),
-            )
-            .field(
-                "i2s_rx_clkm_div_y",
-                &format_args!("{}", self.i2s_rx_clkm_div_y().bits()),
-            )
-            .field(
-                "i2s_rx_clkm_div_x",
-                &format_args!("{}", self.i2s_rx_clkm_div_x().bits()),
-            )
-            .field(
-                "i2s_rx_clkm_div_yn1",
-                &format_args!("{}", self.i2s_rx_clkm_div_yn1().bit()),
-            )
+            .field("i2s_rx_clkm_div_z", &self.i2s_rx_clkm_div_z())
+            .field("i2s_rx_clkm_div_y", &self.i2s_rx_clkm_div_y())
+            .field("i2s_rx_clkm_div_x", &self.i2s_rx_clkm_div_x())
+            .field("i2s_rx_clkm_div_yn1", &self.i2s_rx_clkm_div_yn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S_RX_CLKM_DIV_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/i2s_tx_clkm_conf.rs b/esp32h2/src/pcr/i2s_tx_clkm_conf.rs
index 83d72c6411..a172d428c6 100644
--- a/esp32h2/src/pcr/i2s_tx_clkm_conf.rs
+++ b/esp32h2/src/pcr/i2s_tx_clkm_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S_TX_CLKM_CONF")
-            .field(
-                "i2s_tx_clkm_div_num",
-                &format_args!("{}", self.i2s_tx_clkm_div_num().bits()),
-            )
-            .field(
-                "i2s_tx_clkm_sel",
-                &format_args!("{}", self.i2s_tx_clkm_sel().bits()),
-            )
-            .field(
-                "i2s_tx_clkm_en",
-                &format_args!("{}", self.i2s_tx_clkm_en().bit()),
-            )
+            .field("i2s_tx_clkm_div_num", &self.i2s_tx_clkm_div_num())
+            .field("i2s_tx_clkm_sel", &self.i2s_tx_clkm_sel())
+            .field("i2s_tx_clkm_en", &self.i2s_tx_clkm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S_TX_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 12:19 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b &lt;= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/i2s_tx_clkm_div_conf.rs b/esp32h2/src/pcr/i2s_tx_clkm_div_conf.rs
index 66bbf5a562..f8f3470186 100644
--- a/esp32h2/src/pcr/i2s_tx_clkm_div_conf.rs
+++ b/esp32h2/src/pcr/i2s_tx_clkm_div_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S_TX_CLKM_DIV_CONF")
-            .field(
-                "i2s_tx_clkm_div_z",
-                &format_args!("{}", self.i2s_tx_clkm_div_z().bits()),
-            )
-            .field(
-                "i2s_tx_clkm_div_y",
-                &format_args!("{}", self.i2s_tx_clkm_div_y().bits()),
-            )
-            .field(
-                "i2s_tx_clkm_div_x",
-                &format_args!("{}", self.i2s_tx_clkm_div_x().bits()),
-            )
-            .field(
-                "i2s_tx_clkm_div_yn1",
-                &format_args!("{}", self.i2s_tx_clkm_div_yn1().bit()),
-            )
+            .field("i2s_tx_clkm_div_z", &self.i2s_tx_clkm_div_z())
+            .field("i2s_tx_clkm_div_y", &self.i2s_tx_clkm_div_y())
+            .field("i2s_tx_clkm_div_x", &self.i2s_tx_clkm_div_x())
+            .field("i2s_tx_clkm_div_yn1", &self.i2s_tx_clkm_div_yn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S_TX_CLKM_DIV_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/intmtx_conf.rs b/esp32h2/src/pcr/intmtx_conf.rs
index 2a13b68b55..6595073fae 100644
--- a/esp32h2/src/pcr/intmtx_conf.rs
+++ b/esp32h2/src/pcr/intmtx_conf.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTMTX_CONF")
-            .field(
-                "intmtx_clk_en",
-                &format_args!("{}", self.intmtx_clk_en().bit()),
-            )
-            .field(
-                "intmtx_rst_en",
-                &format_args!("{}", self.intmtx_rst_en().bit()),
-            )
-            .field(
-                "intmtx_ready",
-                &format_args!("{}", self.intmtx_ready().bit()),
-            )
+            .field("intmtx_clk_en", &self.intmtx_clk_en())
+            .field("intmtx_rst_en", &self.intmtx_rst_en())
+            .field("intmtx_ready", &self.intmtx_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTMTX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable intmtx clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/iomux_clk_conf.rs b/esp32h2/src/pcr/iomux_clk_conf.rs
index 5f5176707b..f328e2f898 100644
--- a/esp32h2/src/pcr/iomux_clk_conf.rs
+++ b/esp32h2/src/pcr/iomux_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IOMUX_CLK_CONF")
-            .field(
-                "iomux_func_clk_sel",
-                &format_args!("{}", self.iomux_func_clk_sel().bits()),
-            )
-            .field(
-                "iomux_func_clk_en",
-                &format_args!("{}", self.iomux_func_clk_en().bit()),
-            )
+            .field("iomux_func_clk_sel", &self.iomux_func_clk_sel())
+            .field("iomux_func_clk_en", &self.iomux_func_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IOMUX_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:21 - set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/iomux_conf.rs b/esp32h2/src/pcr/iomux_conf.rs
index bc2a9918a5..ada9aa45a9 100644
--- a/esp32h2/src/pcr/iomux_conf.rs
+++ b/esp32h2/src/pcr/iomux_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IOMUX_CONF")
-            .field(
-                "iomux_clk_en",
-                &format_args!("{}", self.iomux_clk_en().bit()),
-            )
-            .field(
-                "iomux_rst_en",
-                &format_args!("{}", self.iomux_rst_en().bit()),
-            )
+            .field("iomux_clk_en", &self.iomux_clk_en())
+            .field("iomux_rst_en", &self.iomux_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IOMUX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable iomux apb clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/ledc_conf.rs b/esp32h2/src/pcr/ledc_conf.rs
index 4193621be9..3e08276722 100644
--- a/esp32h2/src/pcr/ledc_conf.rs
+++ b/esp32h2/src/pcr/ledc_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEDC_CONF")
-            .field("ledc_clk_en", &format_args!("{}", self.ledc_clk_en().bit()))
-            .field("ledc_rst_en", &format_args!("{}", self.ledc_rst_en().bit()))
-            .field("ledc_ready", &format_args!("{}", self.ledc_ready().bit()))
+            .field("ledc_clk_en", &self.ledc_clk_en())
+            .field("ledc_rst_en", &self.ledc_rst_en())
+            .field("ledc_ready", &self.ledc_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEDC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable ledc apb clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/ledc_sclk_conf.rs b/esp32h2/src/pcr/ledc_sclk_conf.rs
index 21af997d25..32e0c3dced 100644
--- a/esp32h2/src/pcr/ledc_sclk_conf.rs
+++ b/esp32h2/src/pcr/ledc_sclk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEDC_SCLK_CONF")
-            .field(
-                "ledc_sclk_sel",
-                &format_args!("{}", self.ledc_sclk_sel().bits()),
-            )
-            .field(
-                "ledc_sclk_en",
-                &format_args!("{}", self.ledc_sclk_en().bit()),
-            )
+            .field("ledc_sclk_sel", &self.ledc_sclk_sel())
+            .field("ledc_sclk_en", &self.ledc_sclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEDC_SCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:21 - set this field to select clock-source. 0(default): do not select anyone clock, 1: 80MHz, 2: FOSC, 3: XTAL."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/mem_monitor_conf.rs b/esp32h2/src/pcr/mem_monitor_conf.rs
index c5c8c8bbc0..e5c2ec4c15 100644
--- a/esp32h2/src/pcr/mem_monitor_conf.rs
+++ b/esp32h2/src/pcr/mem_monitor_conf.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_MONITOR_CONF")
-            .field(
-                "mem_monitor_clk_en",
-                &format_args!("{}", self.mem_monitor_clk_en().bit()),
-            )
-            .field(
-                "mem_monitor_rst_en",
-                &format_args!("{}", self.mem_monitor_rst_en().bit()),
-            )
-            .field(
-                "mem_monitor_ready",
-                &format_args!("{}", self.mem_monitor_ready().bit()),
-            )
+            .field("mem_monitor_clk_en", &self.mem_monitor_clk_en())
+            .field("mem_monitor_rst_en", &self.mem_monitor_rst_en())
+            .field("mem_monitor_ready", &self.mem_monitor_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_MONITOR_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable mem_monitor clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/modem_conf.rs b/esp32h2/src/pcr/modem_conf.rs
index 5534552238..412ec69f2c 100644
--- a/esp32h2/src/pcr/modem_conf.rs
+++ b/esp32h2/src/pcr/modem_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODEM_CONF")
-            .field(
-                "modem_clk_sel",
-                &format_args!("{}", self.modem_clk_sel().bit()),
-            )
-            .field(
-                "modem_clk_en",
-                &format_args!("{}", self.modem_clk_en().bit()),
-            )
-            .field(
-                "modem_rst_en",
-                &format_args!("{}", self.modem_rst_en().bit()),
-            )
+            .field("modem_clk_sel", &self.modem_clk_sel())
+            .field("modem_clk_en", &self.modem_clk_en())
+            .field("modem_rst_en", &self.modem_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - xxxx"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/mspi_clk_conf.rs b/esp32h2/src/pcr/mspi_clk_conf.rs
index 20cf576602..217779bd4c 100644
--- a/esp32h2/src/pcr/mspi_clk_conf.rs
+++ b/esp32h2/src/pcr/mspi_clk_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MSPI_CLK_CONF")
-            .field(
-                "mspi_fast_div_num",
-                &format_args!("{}", self.mspi_fast_div_num().bits()),
-            )
+            .field("mspi_fast_div_num", &self.mspi_fast_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MSPI_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a low-speed clock-source such as XTAL/FOSC."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/mspi_conf.rs b/esp32h2/src/pcr/mspi_conf.rs
index a1987ace62..221111f9a0 100644
--- a/esp32h2/src/pcr/mspi_conf.rs
+++ b/esp32h2/src/pcr/mspi_conf.rs
@@ -51,26 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MSPI_CONF")
-            .field("mspi_clk_en", &format_args!("{}", self.mspi_clk_en().bit()))
-            .field("mspi_rst_en", &format_args!("{}", self.mspi_rst_en().bit()))
-            .field(
-                "mspi_pll_clk_en",
-                &format_args!("{}", self.mspi_pll_clk_en().bit()),
-            )
-            .field(
-                "mspi_clk_sel",
-                &format_args!("{}", self.mspi_clk_sel().bits()),
-            )
-            .field("mspi_ready", &format_args!("{}", self.mspi_ready().bit()))
+            .field("mspi_clk_en", &self.mspi_clk_en())
+            .field("mspi_rst_en", &self.mspi_rst_en())
+            .field("mspi_pll_clk_en", &self.mspi_pll_clk_en())
+            .field("mspi_clk_sel", &self.mspi_clk_sel())
+            .field("mspi_ready", &self.mspi_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MSPI_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable mspi clock, include mspi pll clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/parl_clk_rx_conf.rs b/esp32h2/src/pcr/parl_clk_rx_conf.rs
index 4ce25c85fd..a715a28898 100644
--- a/esp32h2/src/pcr/parl_clk_rx_conf.rs
+++ b/esp32h2/src/pcr/parl_clk_rx_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PARL_CLK_RX_CONF")
-            .field(
-                "parl_clk_rx_div_num",
-                &format_args!("{}", self.parl_clk_rx_div_num().bits()),
-            )
-            .field(
-                "parl_clk_rx_sel",
-                &format_args!("{}", self.parl_clk_rx_sel().bits()),
-            )
-            .field(
-                "parl_clk_rx_en",
-                &format_args!("{}", self.parl_clk_rx_en().bit()),
-            )
-            .field(
-                "parl_rx_rst_en",
-                &format_args!("{}", self.parl_rx_rst_en().bit()),
-            )
+            .field("parl_clk_rx_div_num", &self.parl_clk_rx_div_num())
+            .field("parl_clk_rx_sel", &self.parl_clk_rx_sel())
+            .field("parl_clk_rx_en", &self.parl_clk_rx_en())
+            .field("parl_rx_rst_en", &self.parl_rx_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PARL_CLK_RX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The integral part of the frequency divider factor of the parl rx clock."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/parl_clk_tx_conf.rs b/esp32h2/src/pcr/parl_clk_tx_conf.rs
index cb37ed41ac..0282110cc9 100644
--- a/esp32h2/src/pcr/parl_clk_tx_conf.rs
+++ b/esp32h2/src/pcr/parl_clk_tx_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PARL_CLK_TX_CONF")
-            .field(
-                "parl_clk_tx_div_num",
-                &format_args!("{}", self.parl_clk_tx_div_num().bits()),
-            )
-            .field(
-                "parl_clk_tx_sel",
-                &format_args!("{}", self.parl_clk_tx_sel().bits()),
-            )
-            .field(
-                "parl_clk_tx_en",
-                &format_args!("{}", self.parl_clk_tx_en().bit()),
-            )
-            .field(
-                "parl_tx_rst_en",
-                &format_args!("{}", self.parl_tx_rst_en().bit()),
-            )
+            .field("parl_clk_tx_div_num", &self.parl_clk_tx_div_num())
+            .field("parl_clk_tx_sel", &self.parl_clk_tx_sel())
+            .field("parl_clk_tx_en", &self.parl_clk_tx_en())
+            .field("parl_tx_rst_en", &self.parl_tx_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PARL_CLK_TX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The integral part of the frequency divider factor of the parl tx clock."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/parl_io_conf.rs b/esp32h2/src/pcr/parl_io_conf.rs
index 323d1bf68e..328a2670a5 100644
--- a/esp32h2/src/pcr/parl_io_conf.rs
+++ b/esp32h2/src/pcr/parl_io_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PARL_IO_CONF")
-            .field("parl_clk_en", &format_args!("{}", self.parl_clk_en().bit()))
-            .field("parl_rst_en", &format_args!("{}", self.parl_rst_en().bit()))
-            .field("parl_ready", &format_args!("{}", self.parl_ready().bit()))
+            .field("parl_clk_en", &self.parl_clk_en())
+            .field("parl_rst_en", &self.parl_rst_en())
+            .field("parl_ready", &self.parl_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PARL_IO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable parl apb clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/pcnt_conf.rs b/esp32h2/src/pcr/pcnt_conf.rs
index 17bcdd27cf..ac27fa02e5 100644
--- a/esp32h2/src/pcr/pcnt_conf.rs
+++ b/esp32h2/src/pcr/pcnt_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCNT_CONF")
-            .field("pcnt_clk_en", &format_args!("{}", self.pcnt_clk_en().bit()))
-            .field("pcnt_rst_en", &format_args!("{}", self.pcnt_rst_en().bit()))
-            .field("pcnt_ready", &format_args!("{}", self.pcnt_ready().bit()))
+            .field("pcnt_clk_en", &self.pcnt_clk_en())
+            .field("pcnt_rst_en", &self.pcnt_rst_en())
+            .field("pcnt_ready", &self.pcnt_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCNT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable pcnt clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/pll_div_clk_en.rs b/esp32h2/src/pcr/pll_div_clk_en.rs
index ace1965fb3..ffd54ac71f 100644
--- a/esp32h2/src/pcr/pll_div_clk_en.rs
+++ b/esp32h2/src/pcr/pll_div_clk_en.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PLL_DIV_CLK_EN")
-            .field(
-                "pll_240m_clk_en",
-                &format_args!("{}", self.pll_240m_clk_en().bit()),
-            )
-            .field(
-                "pll_160m_clk_en",
-                &format_args!("{}", self.pll_160m_clk_en().bit()),
-            )
-            .field(
-                "pll_120m_clk_en",
-                &format_args!("{}", self.pll_120m_clk_en().bit()),
-            )
-            .field(
-                "pll_80m_clk_en",
-                &format_args!("{}", self.pll_80m_clk_en().bit()),
-            )
-            .field(
-                "pll_48m_clk_en",
-                &format_args!("{}", self.pll_48m_clk_en().bit()),
-            )
-            .field(
-                "pll_40m_clk_en",
-                &format_args!("{}", self.pll_40m_clk_en().bit()),
-            )
+            .field("pll_240m_clk_en", &self.pll_240m_clk_en())
+            .field("pll_160m_clk_en", &self.pll_160m_clk_en())
+            .field("pll_120m_clk_en", &self.pll_120m_clk_en())
+            .field("pll_80m_clk_en", &self.pll_80m_clk_en())
+            .field("pll_48m_clk_en", &self.pll_48m_clk_en())
+            .field("pll_40m_clk_en", &self.pll_40m_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PLL_DIV_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This field is used to open 96 MHz clock (SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/pvt_monitor_conf.rs b/esp32h2/src/pcr/pvt_monitor_conf.rs
index a9d7da70a3..82faf44026 100644
--- a/esp32h2/src/pcr/pvt_monitor_conf.rs
+++ b/esp32h2/src/pcr/pvt_monitor_conf.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PVT_MONITOR_CONF")
-            .field(
-                "pvt_monitor_clk_en",
-                &format_args!("{}", self.pvt_monitor_clk_en().bit()),
-            )
-            .field(
-                "pvt_monitor_rst_en",
-                &format_args!("{}", self.pvt_monitor_rst_en().bit()),
-            )
-            .field(
-                "pvt_monitor_site1_clk_en",
-                &format_args!("{}", self.pvt_monitor_site1_clk_en().bit()),
-            )
-            .field(
-                "pvt_monitor_site2_clk_en",
-                &format_args!("{}", self.pvt_monitor_site2_clk_en().bit()),
-            )
-            .field(
-                "pvt_monitor_site3_clk_en",
-                &format_args!("{}", self.pvt_monitor_site3_clk_en().bit()),
-            )
+            .field("pvt_monitor_clk_en", &self.pvt_monitor_clk_en())
+            .field("pvt_monitor_rst_en", &self.pvt_monitor_rst_en())
+            .field("pvt_monitor_site1_clk_en", &self.pvt_monitor_site1_clk_en())
+            .field("pvt_monitor_site2_clk_en", &self.pvt_monitor_site2_clk_en())
+            .field("pvt_monitor_site3_clk_en", &self.pvt_monitor_site3_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PVT_MONITOR_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable apb clock of pvt module"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/pvt_monitor_func_clk_conf.rs b/esp32h2/src/pcr/pvt_monitor_func_clk_conf.rs
index 66c402883a..26e5fad8b9 100644
--- a/esp32h2/src/pcr/pvt_monitor_func_clk_conf.rs
+++ b/esp32h2/src/pcr/pvt_monitor_func_clk_conf.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("PVT_MONITOR_FUNC_CLK_CONF")
             .field(
                 "pvt_monitor_func_clk_div_num",
-                &format_args!("{}", self.pvt_monitor_func_clk_div_num().bits()),
-            )
-            .field(
-                "pvt_monitor_func_clk_sel",
-                &format_args!("{}", self.pvt_monitor_func_clk_sel().bit()),
-            )
-            .field(
-                "pvt_monitor_func_clk_en",
-                &format_args!("{}", self.pvt_monitor_func_clk_en().bit()),
+                &self.pvt_monitor_func_clk_div_num(),
             )
+            .field("pvt_monitor_func_clk_sel", &self.pvt_monitor_func_clk_sel())
+            .field("pvt_monitor_func_clk_en", &self.pvt_monitor_func_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PVT_MONITOR_FUNC_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The integral part of the frequency divider factor of the pvt_monitor function clock."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/pwdet_sar_clk_conf.rs b/esp32h2/src/pcr/pwdet_sar_clk_conf.rs
index ff60c3aec8..146c553d05 100644
--- a/esp32h2/src/pcr/pwdet_sar_clk_conf.rs
+++ b/esp32h2/src/pcr/pwdet_sar_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWDET_SAR_CLK_CONF")
-            .field(
-                "pwdet_sar_clk_div_num",
-                &format_args!("{}", self.pwdet_sar_clk_div_num().bits()),
-            )
-            .field(
-                "pwdet_sar_reader_en",
-                &format_args!("{}", self.pwdet_sar_reader_en().bit()),
-            )
+            .field("pwdet_sar_clk_div_num", &self.pwdet_sar_clk_div_num())
+            .field("pwdet_sar_reader_en", &self.pwdet_sar_reader_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWDET_SAR_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - xxxx"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/pwm_clk_conf.rs b/esp32h2/src/pcr/pwm_clk_conf.rs
index fe27525ecc..b064b83950 100644
--- a/esp32h2/src/pcr/pwm_clk_conf.rs
+++ b/esp32h2/src/pcr/pwm_clk_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM_CLK_CONF")
-            .field(
-                "pwm_div_num",
-                &format_args!("{}", self.pwm_div_num().bits()),
-            )
-            .field(
-                "pwm_clkm_sel",
-                &format_args!("{}", self.pwm_clkm_sel().bits()),
-            )
-            .field("pwm_clkm_en", &format_args!("{}", self.pwm_clkm_en().bit()))
+            .field("pwm_div_num", &self.pwm_div_num())
+            .field("pwm_clkm_sel", &self.pwm_clkm_sel())
+            .field("pwm_clkm_en", &self.pwm_clkm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 12:19 - The integral part of the frequency divider factor of the pwm function clock."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/pwm_conf.rs b/esp32h2/src/pcr/pwm_conf.rs
index 94aecc237a..7d06c9abec 100644
--- a/esp32h2/src/pcr/pwm_conf.rs
+++ b/esp32h2/src/pcr/pwm_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM_CONF")
-            .field("pwm_clk_en", &format_args!("{}", self.pwm_clk_en().bit()))
-            .field("pwm_rst_en", &format_args!("{}", self.pwm_rst_en().bit()))
-            .field("pwm_ready", &format_args!("{}", self.pwm_ready().bit()))
+            .field("pwm_clk_en", &self.pwm_clk_en())
+            .field("pwm_rst_en", &self.pwm_rst_en())
+            .field("pwm_ready", &self.pwm_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable pwm clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/regdma_conf.rs b/esp32h2/src/pcr/regdma_conf.rs
index d539eef0c4..b5d6c4568a 100644
--- a/esp32h2/src/pcr/regdma_conf.rs
+++ b/esp32h2/src/pcr/regdma_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_CONF")
-            .field(
-                "regdma_clk_en",
-                &format_args!("{}", self.regdma_clk_en().bit()),
-            )
-            .field(
-                "regdma_rst_en",
-                &format_args!("{}", self.regdma_rst_en().bit()),
-            )
+            .field("regdma_clk_en", &self.regdma_clk_en())
+            .field("regdma_rst_en", &self.regdma_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable regdma clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/reset_event_bypass.rs b/esp32h2/src/pcr/reset_event_bypass.rs
index 6c10dc4fde..8f1f6354b3 100644
--- a/esp32h2/src/pcr/reset_event_bypass.rs
+++ b/esp32h2/src/pcr/reset_event_bypass.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET_EVENT_BYPASS")
-            .field("apm", &format_args!("{}", self.apm().bit()))
-            .field(
-                "reset_event_bypass",
-                &format_args!("{}", self.reset_event_bypass().bit()),
-            )
+            .field("apm", &self.apm())
+            .field("reset_event_bypass", &self.reset_event_bypass())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET_EVENT_BYPASS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This field is used to control reset event relationship for tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset, but also some reset event."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/rmt_conf.rs b/esp32h2/src/pcr/rmt_conf.rs
index 3c2384761c..07bb1dcb91 100644
--- a/esp32h2/src/pcr/rmt_conf.rs
+++ b/esp32h2/src/pcr/rmt_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RMT_CONF")
-            .field("rmt_clk_en", &format_args!("{}", self.rmt_clk_en().bit()))
-            .field("rmt_rst_en", &format_args!("{}", self.rmt_rst_en().bit()))
-            .field("rmt_ready", &format_args!("{}", self.rmt_ready().bit()))
+            .field("rmt_clk_en", &self.rmt_clk_en())
+            .field("rmt_rst_en", &self.rmt_rst_en())
+            .field("rmt_ready", &self.rmt_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RMT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable rmt apb clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/rmt_sclk_conf.rs b/esp32h2/src/pcr/rmt_sclk_conf.rs
index 01eb02b90b..fe0dcec33c 100644
--- a/esp32h2/src/pcr/rmt_sclk_conf.rs
+++ b/esp32h2/src/pcr/rmt_sclk_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RMT_SCLK_CONF")
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bit()))
-            .field("sclk_en", &format_args!("{}", self.sclk_en().bit()))
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_en", &self.sclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RMT_SCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the rmt function clock."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/rsa_conf.rs b/esp32h2/src/pcr/rsa_conf.rs
index 309154ca35..42f7997e58 100644
--- a/esp32h2/src/pcr/rsa_conf.rs
+++ b/esp32h2/src/pcr/rsa_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_CONF")
-            .field("rsa_clk_en", &format_args!("{}", self.rsa_clk_en().bit()))
-            .field("rsa_rst_en", &format_args!("{}", self.rsa_rst_en().bit()))
-            .field("rsa_ready", &format_args!("{}", self.rsa_ready().bit()))
+            .field("rsa_clk_en", &self.rsa_clk_en())
+            .field("rsa_rst_en", &self.rsa_rst_en())
+            .field("rsa_ready", &self.rsa_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable rsa clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/rsa_pd_ctrl.rs b/esp32h2/src/pcr/rsa_pd_ctrl.rs
index 65c3c38561..208c8218fa 100644
--- a/esp32h2/src/pcr/rsa_pd_ctrl.rs
+++ b/esp32h2/src/pcr/rsa_pd_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_PD_CTRL")
-            .field("rsa_mem_pd", &format_args!("{}", self.rsa_mem_pd().bit()))
-            .field(
-                "rsa_mem_force_pu",
-                &format_args!("{}", self.rsa_mem_force_pu().bit()),
-            )
-            .field(
-                "rsa_mem_force_pd",
-                &format_args!("{}", self.rsa_mem_force_pd().bit()),
-            )
+            .field("rsa_mem_pd", &self.rsa_mem_pd())
+            .field("rsa_mem_force_pu", &self.rsa_mem_force_pu())
+            .field("rsa_mem_force_pd", &self.rsa_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to power down rsa internal memory."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/sar_clk_div.rs b/esp32h2/src/pcr/sar_clk_div.rs
index e3df3bb82d..ccd1fcc63b 100644
--- a/esp32h2/src/pcr/sar_clk_div.rs
+++ b/esp32h2/src/pcr/sar_clk_div.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_CLK_DIV")
-            .field(
-                "sar2_clk_div_num",
-                &format_args!("{}", self.sar2_clk_div_num().bits()),
-            )
-            .field(
-                "sar1_clk_div_num",
-                &format_args!("{}", self.sar1_clk_div_num().bits()),
-            )
+            .field("sar2_clk_div_num", &self.sar2_clk_div_num())
+            .field("sar1_clk_div_num", &self.sar1_clk_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_CLK_DIV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - xxxx"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/saradc_clkm_conf.rs b/esp32h2/src/pcr/saradc_clkm_conf.rs
index e666233027..25579664e8 100644
--- a/esp32h2/src/pcr/saradc_clkm_conf.rs
+++ b/esp32h2/src/pcr/saradc_clkm_conf.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SARADC_CLKM_CONF")
-            .field(
-                "saradc_clkm_div_a",
-                &format_args!("{}", self.saradc_clkm_div_a().bits()),
-            )
-            .field(
-                "saradc_clkm_div_b",
-                &format_args!("{}", self.saradc_clkm_div_b().bits()),
-            )
-            .field(
-                "saradc_clkm_div_num",
-                &format_args!("{}", self.saradc_clkm_div_num().bits()),
-            )
-            .field(
-                "saradc_clkm_sel",
-                &format_args!("{}", self.saradc_clkm_sel().bits()),
-            )
-            .field(
-                "saradc_clkm_en",
-                &format_args!("{}", self.saradc_clkm_en().bit()),
-            )
+            .field("saradc_clkm_div_a", &self.saradc_clkm_div_a())
+            .field("saradc_clkm_div_b", &self.saradc_clkm_div_b())
+            .field("saradc_clkm_div_num", &self.saradc_clkm_div_num())
+            .field("saradc_clkm_sel", &self.saradc_clkm_sel())
+            .field("saradc_clkm_en", &self.saradc_clkm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SARADC_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the saradc function clock."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/saradc_conf.rs b/esp32h2/src/pcr/saradc_conf.rs
index c98b622760..8915aa864d 100644
--- a/esp32h2/src/pcr/saradc_conf.rs
+++ b/esp32h2/src/pcr/saradc_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SARADC_CONF")
-            .field(
-                "saradc_clk_en",
-                &format_args!("{}", self.saradc_clk_en().bit()),
-            )
-            .field(
-                "saradc_rst_en",
-                &format_args!("{}", self.saradc_rst_en().bit()),
-            )
-            .field(
-                "saradc_reg_clk_en",
-                &format_args!("{}", self.saradc_reg_clk_en().bit()),
-            )
-            .field(
-                "saradc_reg_rst_en",
-                &format_args!("{}", self.saradc_reg_rst_en().bit()),
-            )
+            .field("saradc_clk_en", &self.saradc_clk_en())
+            .field("saradc_rst_en", &self.saradc_rst_en())
+            .field("saradc_reg_clk_en", &self.saradc_reg_clk_en())
+            .field("saradc_reg_rst_en", &self.saradc_reg_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SARADC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - no use"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/sdm_inv_phase_conf.rs b/esp32h2/src/pcr/sdm_inv_phase_conf.rs
index 59e7f8f6e8..635ef4402d 100644
--- a/esp32h2/src/pcr/sdm_inv_phase_conf.rs
+++ b/esp32h2/src/pcr/sdm_inv_phase_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDM_INV_PHASE_CONF")
-            .field(
-                "clk_sdm_inv_phase_ena",
-                &format_args!("{}", self.clk_sdm_inv_phase_ena().bit()),
-            )
-            .field(
-                "clk_sdm_inv_phase_sel",
-                &format_args!("{}", self.clk_sdm_inv_phase_sel().bits()),
-            )
+            .field("clk_sdm_inv_phase_ena", &self.clk_sdm_inv_phase_ena())
+            .field("clk_sdm_inv_phase_sel", &self.clk_sdm_inv_phase_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDM_INV_PHASE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - xxxx"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/sec_conf.rs b/esp32h2/src/pcr/sec_conf.rs
index 5d6ebcb213..6fbe6bfcd4 100644
--- a/esp32h2/src/pcr/sec_conf.rs
+++ b/esp32h2/src/pcr/sec_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEC_CONF")
-            .field(
-                "sec_clk_sel",
-                &format_args!("{}", self.sec_clk_sel().bits()),
-            )
+            .field("sec_clk_sel", &self.sec_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - xxxx"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/sha_conf.rs b/esp32h2/src/pcr/sha_conf.rs
index 56a86d4898..974ba9edd4 100644
--- a/esp32h2/src/pcr/sha_conf.rs
+++ b/esp32h2/src/pcr/sha_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA_CONF")
-            .field("sha_clk_en", &format_args!("{}", self.sha_clk_en().bit()))
-            .field("sha_rst_en", &format_args!("{}", self.sha_rst_en().bit()))
-            .field("sha_ready", &format_args!("{}", self.sha_ready().bit()))
+            .field("sha_clk_en", &self.sha_clk_en())
+            .field("sha_rst_en", &self.sha_rst_en())
+            .field("sha_ready", &self.sha_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable sha clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/spi2_clkm_conf.rs b/esp32h2/src/pcr/spi2_clkm_conf.rs
index 5fac9885f8..60b461d7ad 100644
--- a/esp32h2/src/pcr/spi2_clkm_conf.rs
+++ b/esp32h2/src/pcr/spi2_clkm_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI2_CLKM_CONF")
-            .field(
-                "spi2_clkm_sel",
-                &format_args!("{}", self.spi2_clkm_sel().bits()),
-            )
-            .field(
-                "spi2_clkm_en",
-                &format_args!("{}", self.spi2_clkm_en().bit()),
-            )
+            .field("spi2_clkm_sel", &self.spi2_clkm_sel())
+            .field("spi2_clkm_en", &self.spi2_clkm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI2_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:21 - set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/spi2_conf.rs b/esp32h2/src/pcr/spi2_conf.rs
index fe74991613..3ddaf752ca 100644
--- a/esp32h2/src/pcr/spi2_conf.rs
+++ b/esp32h2/src/pcr/spi2_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI2_CONF")
-            .field("spi2_clk_en", &format_args!("{}", self.spi2_clk_en().bit()))
-            .field("spi2_rst_en", &format_args!("{}", self.spi2_rst_en().bit()))
-            .field("spi2_ready", &format_args!("{}", self.spi2_ready().bit()))
+            .field("spi2_clk_en", &self.spi2_clk_en())
+            .field("spi2_rst_en", &self.spi2_rst_en())
+            .field("spi2_ready", &self.spi2_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI2_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable spi2 apb clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/sram_power_conf_0.rs b/esp32h2/src/pcr/sram_power_conf_0.rs
index ee72106e25..a06227e8e3 100644
--- a/esp32h2/src/pcr/sram_power_conf_0.rs
+++ b/esp32h2/src/pcr/sram_power_conf_0.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_POWER_CONF_0")
-            .field(
-                "rom_force_pu",
-                &format_args!("{}", self.rom_force_pu().bits()),
-            )
-            .field(
-                "rom_force_pd",
-                &format_args!("{}", self.rom_force_pd().bits()),
-            )
-            .field(
-                "rom_clkgate_force_on",
-                &format_args!("{}", self.rom_clkgate_force_on().bits()),
-            )
+            .field("rom_force_pu", &self.rom_force_pu())
+            .field("rom_force_pd", &self.rom_force_pd())
+            .field("rom_clkgate_force_on", &self.rom_clkgate_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_POWER_CONF_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 13:14 - Set this bit to force power up ROM"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/sram_power_conf_1.rs b/esp32h2/src/pcr/sram_power_conf_1.rs
index c0e0aab721..2bf77acc15 100644
--- a/esp32h2/src/pcr/sram_power_conf_1.rs
+++ b/esp32h2/src/pcr/sram_power_conf_1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_POWER_CONF_1")
-            .field(
-                "sram_force_pu",
-                &format_args!("{}", self.sram_force_pu().bits()),
-            )
-            .field(
-                "sram_force_pd",
-                &format_args!("{}", self.sram_force_pd().bits()),
-            )
-            .field(
-                "sram_clkgate_force_on",
-                &format_args!("{}", self.sram_clkgate_force_on().bits()),
-            )
+            .field("sram_force_pu", &self.sram_force_pu())
+            .field("sram_force_pd", &self.sram_force_pd())
+            .field("sram_clkgate_force_on", &self.sram_clkgate_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_POWER_CONF_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Set this bit to force power up SRAM"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/sysclk_conf.rs b/esp32h2/src/pcr/sysclk_conf.rs
index a991f826c4..5ad00f376c 100644
--- a/esp32h2/src/pcr/sysclk_conf.rs
+++ b/esp32h2/src/pcr/sysclk_conf.rs
@@ -38,25 +38,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSCLK_CONF")
-            .field("ls_div_num", &format_args!("{}", self.ls_div_num().bits()))
-            .field("hs_div_num", &format_args!("{}", self.hs_div_num().bits()))
-            .field(
-                "soc_clk_sel",
-                &format_args!("{}", self.soc_clk_sel().bits()),
-            )
-            .field(
-                "clk_xtal_freq",
-                &format_args!("{}", self.clk_xtal_freq().bits()),
-            )
+            .field("ls_div_num", &self.ls_div_num())
+            .field("hs_div_num", &self.hs_div_num())
+            .field("soc_clk_sel", &self.soc_clk_sel())
+            .field("clk_xtal_freq", &self.clk_xtal_freq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:17 - This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/sysclk_freq_query_0.rs b/esp32h2/src/pcr/sysclk_freq_query_0.rs
index 816dadd51b..444a173959 100644
--- a/esp32h2/src/pcr/sysclk_freq_query_0.rs
+++ b/esp32h2/src/pcr/sysclk_freq_query_0.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSCLK_FREQ_QUERY_0")
-            .field("fosc_freq", &format_args!("{}", self.fosc_freq().bits()))
-            .field("pll_freq", &format_args!("{}", self.pll_freq().bits()))
+            .field("fosc_freq", &self.fosc_freq())
+            .field("pll_freq", &self.pll_freq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSCLK_FREQ_QUERY_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SYSCLK frequency query 0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysclk_freq_query_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SYSCLK_FREQ_QUERY_0_SPEC;
 impl crate::RegisterSpec for SYSCLK_FREQ_QUERY_0_SPEC {
diff --git a/esp32h2/src/pcr/systimer_conf.rs b/esp32h2/src/pcr/systimer_conf.rs
index 26a0d70deb..cb42cd244a 100644
--- a/esp32h2/src/pcr/systimer_conf.rs
+++ b/esp32h2/src/pcr/systimer_conf.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_CONF")
-            .field(
-                "systimer_clk_en",
-                &format_args!("{}", self.systimer_clk_en().bit()),
-            )
-            .field(
-                "systimer_rst_en",
-                &format_args!("{}", self.systimer_rst_en().bit()),
-            )
-            .field(
-                "systimer_ready",
-                &format_args!("{}", self.systimer_ready().bit()),
-            )
+            .field("systimer_clk_en", &self.systimer_clk_en())
+            .field("systimer_rst_en", &self.systimer_rst_en())
+            .field("systimer_ready", &self.systimer_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable systimer apb clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/systimer_func_clk_conf.rs b/esp32h2/src/pcr/systimer_func_clk_conf.rs
index 21e7778980..4f6ae2cfae 100644
--- a/esp32h2/src/pcr/systimer_func_clk_conf.rs
+++ b/esp32h2/src/pcr/systimer_func_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_FUNC_CLK_CONF")
-            .field(
-                "systimer_func_clk_sel",
-                &format_args!("{}", self.systimer_func_clk_sel().bit()),
-            )
-            .field(
-                "systimer_func_clk_en",
-                &format_args!("{}", self.systimer_func_clk_en().bit()),
-            )
+            .field("systimer_func_clk_sel", &self.systimer_func_clk_sel())
+            .field("systimer_func_clk_en", &self.systimer_func_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_FUNC_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - set this field to select clock-source. 0(default): XTAL, 1: FOSC."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/timeout_conf.rs b/esp32h2/src/pcr/timeout_conf.rs
index d46b025844..6e39c5c662 100644
--- a/esp32h2/src/pcr/timeout_conf.rs
+++ b/esp32h2/src/pcr/timeout_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMEOUT_CONF")
-            .field(
-                "cpu_timeout_rst_en",
-                &format_args!("{}", self.cpu_timeout_rst_en().bit()),
-            )
-            .field(
-                "hp_timeout_rst_en",
-                &format_args!("{}", self.hp_timeout_rst_en().bit()),
-            )
+            .field("cpu_timeout_rst_en", &self.cpu_timeout_rst_en())
+            .field("hp_timeout_rst_en", &self.hp_timeout_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMEOUT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set 0 to reset cpu_peri timeout module"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/timergroup0_conf.rs b/esp32h2/src/pcr/timergroup0_conf.rs
index 8f31f0c8a0..56f65203f0 100644
--- a/esp32h2/src/pcr/timergroup0_conf.rs
+++ b/esp32h2/src/pcr/timergroup0_conf.rs
@@ -47,29 +47,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMERGROUP0_CONF")
-            .field("tg0_clk_en", &format_args!("{}", self.tg0_clk_en().bit()))
-            .field("tg0_rst_en", &format_args!("{}", self.tg0_rst_en().bit()))
-            .field(
-                "tg0_wdt_ready",
-                &format_args!("{}", self.tg0_wdt_ready().bit()),
-            )
-            .field(
-                "tg0_timer0_ready",
-                &format_args!("{}", self.tg0_timer0_ready().bit()),
-            )
-            .field(
-                "tg0_timer1_ready",
-                &format_args!("{}", self.tg0_timer1_ready().bit()),
-            )
+            .field("tg0_clk_en", &self.tg0_clk_en())
+            .field("tg0_rst_en", &self.tg0_rst_en())
+            .field("tg0_wdt_ready", &self.tg0_wdt_ready())
+            .field("tg0_timer0_ready", &self.tg0_timer0_ready())
+            .field("tg0_timer1_ready", &self.tg0_timer1_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGROUP0_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable timer_group0 apb clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/timergroup0_timer_clk_conf.rs b/esp32h2/src/pcr/timergroup0_timer_clk_conf.rs
index 17ad2c7fdc..a76f065abb 100644
--- a/esp32h2/src/pcr/timergroup0_timer_clk_conf.rs
+++ b/esp32h2/src/pcr/timergroup0_timer_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMERGROUP0_TIMER_CLK_CONF")
-            .field(
-                "tg0_timer_clk_sel",
-                &format_args!("{}", self.tg0_timer_clk_sel().bits()),
-            )
-            .field(
-                "tg0_timer_clk_en",
-                &format_args!("{}", self.tg0_timer_clk_en().bit()),
-            )
+            .field("tg0_timer_clk_sel", &self.tg0_timer_clk_sel())
+            .field("tg0_timer_clk_en", &self.tg0_timer_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGROUP0_TIMER_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:21 - set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/timergroup0_wdt_clk_conf.rs b/esp32h2/src/pcr/timergroup0_wdt_clk_conf.rs
index d3cff23a67..1e2ec0d9d7 100644
--- a/esp32h2/src/pcr/timergroup0_wdt_clk_conf.rs
+++ b/esp32h2/src/pcr/timergroup0_wdt_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMERGROUP0_WDT_CLK_CONF")
-            .field(
-                "tg0_wdt_clk_sel",
-                &format_args!("{}", self.tg0_wdt_clk_sel().bits()),
-            )
-            .field(
-                "tg0_wdt_clk_en",
-                &format_args!("{}", self.tg0_wdt_clk_en().bit()),
-            )
+            .field("tg0_wdt_clk_sel", &self.tg0_wdt_clk_sel())
+            .field("tg0_wdt_clk_en", &self.tg0_wdt_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGROUP0_WDT_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:21 - set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/timergroup1_conf.rs b/esp32h2/src/pcr/timergroup1_conf.rs
index 075b27581f..ffffca57d9 100644
--- a/esp32h2/src/pcr/timergroup1_conf.rs
+++ b/esp32h2/src/pcr/timergroup1_conf.rs
@@ -47,29 +47,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMERGROUP1_CONF")
-            .field("tg1_clk_en", &format_args!("{}", self.tg1_clk_en().bit()))
-            .field("tg1_rst_en", &format_args!("{}", self.tg1_rst_en().bit()))
-            .field(
-                "tg1_wdt_ready",
-                &format_args!("{}", self.tg1_wdt_ready().bit()),
-            )
-            .field(
-                "tg1_timer0_ready",
-                &format_args!("{}", self.tg1_timer0_ready().bit()),
-            )
-            .field(
-                "tg1_timer1_ready",
-                &format_args!("{}", self.tg1_timer1_ready().bit()),
-            )
+            .field("tg1_clk_en", &self.tg1_clk_en())
+            .field("tg1_rst_en", &self.tg1_rst_en())
+            .field("tg1_wdt_ready", &self.tg1_wdt_ready())
+            .field("tg1_timer0_ready", &self.tg1_timer0_ready())
+            .field("tg1_timer1_ready", &self.tg1_timer1_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGROUP1_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable timer_group1 apb clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/timergroup1_timer_clk_conf.rs b/esp32h2/src/pcr/timergroup1_timer_clk_conf.rs
index 94014734a9..f7144b76b6 100644
--- a/esp32h2/src/pcr/timergroup1_timer_clk_conf.rs
+++ b/esp32h2/src/pcr/timergroup1_timer_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMERGROUP1_TIMER_CLK_CONF")
-            .field(
-                "tg1_timer_clk_sel",
-                &format_args!("{}", self.tg1_timer_clk_sel().bits()),
-            )
-            .field(
-                "tg1_timer_clk_en",
-                &format_args!("{}", self.tg1_timer_clk_en().bit()),
-            )
+            .field("tg1_timer_clk_sel", &self.tg1_timer_clk_sel())
+            .field("tg1_timer_clk_en", &self.tg1_timer_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGROUP1_TIMER_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:21 - set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/timergroup1_wdt_clk_conf.rs b/esp32h2/src/pcr/timergroup1_wdt_clk_conf.rs
index 163f9dd9fe..6d4aa1b598 100644
--- a/esp32h2/src/pcr/timergroup1_wdt_clk_conf.rs
+++ b/esp32h2/src/pcr/timergroup1_wdt_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMERGROUP1_WDT_CLK_CONF")
-            .field(
-                "tg1_wdt_clk_sel",
-                &format_args!("{}", self.tg1_wdt_clk_sel().bits()),
-            )
-            .field(
-                "tg1_wdt_clk_en",
-                &format_args!("{}", self.tg1_wdt_clk_en().bit()),
-            )
+            .field("tg1_wdt_clk_sel", &self.tg1_wdt_clk_sel())
+            .field("tg1_wdt_clk_en", &self.tg1_wdt_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGROUP1_WDT_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:21 - set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/trace_conf.rs b/esp32h2/src/pcr/trace_conf.rs
index 3923e26075..52110676fe 100644
--- a/esp32h2/src/pcr/trace_conf.rs
+++ b/esp32h2/src/pcr/trace_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TRACE_CONF")
-            .field(
-                "trace_clk_en",
-                &format_args!("{}", self.trace_clk_en().bit()),
-            )
-            .field(
-                "trace_rst_en",
-                &format_args!("{}", self.trace_rst_en().bit()),
-            )
+            .field("trace_clk_en", &self.trace_clk_en())
+            .field("trace_rst_en", &self.trace_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TRACE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable trace clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/tsens_clk_conf.rs b/esp32h2/src/pcr/tsens_clk_conf.rs
index b96d6bdd66..b7a1417ca2 100644
--- a/esp32h2/src/pcr/tsens_clk_conf.rs
+++ b/esp32h2/src/pcr/tsens_clk_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSENS_CLK_CONF")
-            .field(
-                "tsens_clk_sel",
-                &format_args!("{}", self.tsens_clk_sel().bit()),
-            )
-            .field(
-                "tsens_clk_en",
-                &format_args!("{}", self.tsens_clk_en().bit()),
-            )
-            .field(
-                "tsens_rst_en",
-                &format_args!("{}", self.tsens_rst_en().bit()),
-            )
+            .field("tsens_clk_sel", &self.tsens_clk_sel())
+            .field("tsens_clk_en", &self.tsens_clk_en())
+            .field("tsens_rst_en", &self.tsens_rst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSENS_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - set this field to select clock-source. 0(default): FOSC, 1: XTAL."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/twai0_conf.rs b/esp32h2/src/pcr/twai0_conf.rs
index fa3202ea21..915733938b 100644
--- a/esp32h2/src/pcr/twai0_conf.rs
+++ b/esp32h2/src/pcr/twai0_conf.rs
@@ -33,24 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TWAI0_CONF")
-            .field(
-                "twai0_clk_en",
-                &format_args!("{}", self.twai0_clk_en().bit()),
-            )
-            .field(
-                "twai0_rst_en",
-                &format_args!("{}", self.twai0_rst_en().bit()),
-            )
-            .field("twai0_ready", &format_args!("{}", self.twai0_ready().bit()))
+            .field("twai0_clk_en", &self.twai0_clk_en())
+            .field("twai0_rst_en", &self.twai0_rst_en())
+            .field("twai0_ready", &self.twai0_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TWAI0_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable twai0 apb clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/twai0_func_clk_conf.rs b/esp32h2/src/pcr/twai0_func_clk_conf.rs
index 54bb98ba94..c283410b4e 100644
--- a/esp32h2/src/pcr/twai0_func_clk_conf.rs
+++ b/esp32h2/src/pcr/twai0_func_clk_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TWAI0_FUNC_CLK_CONF")
-            .field(
-                "twai0_func_clk_sel",
-                &format_args!("{}", self.twai0_func_clk_sel().bit()),
-            )
-            .field(
-                "twai0_func_clk_en",
-                &format_args!("{}", self.twai0_func_clk_en().bit()),
-            )
+            .field("twai0_func_clk_sel", &self.twai0_func_clk_sel())
+            .field("twai0_func_clk_en", &self.twai0_func_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TWAI0_FUNC_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - set this field to select clock-source. 0(default): XTAL, 1: FOSC."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/uart0_conf.rs b/esp32h2/src/pcr/uart0_conf.rs
index 323462417d..c99afa048d 100644
--- a/esp32h2/src/pcr/uart0_conf.rs
+++ b/esp32h2/src/pcr/uart0_conf.rs
@@ -33,24 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART0_CONF")
-            .field(
-                "uart0_clk_en",
-                &format_args!("{}", self.uart0_clk_en().bit()),
-            )
-            .field(
-                "uart0_rst_en",
-                &format_args!("{}", self.uart0_rst_en().bit()),
-            )
-            .field("uart0_ready", &format_args!("{}", self.uart0_ready().bit()))
+            .field("uart0_clk_en", &self.uart0_clk_en())
+            .field("uart0_rst_en", &self.uart0_rst_en())
+            .field("uart0_ready", &self.uart0_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART0_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable uart0 apb clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/uart0_pd_ctrl.rs b/esp32h2/src/pcr/uart0_pd_ctrl.rs
index bdde57841f..6d9f4aa063 100644
--- a/esp32h2/src/pcr/uart0_pd_ctrl.rs
+++ b/esp32h2/src/pcr/uart0_pd_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART0_PD_CTRL")
-            .field(
-                "uart0_mem_force_pu",
-                &format_args!("{}", self.uart0_mem_force_pu().bit()),
-            )
-            .field(
-                "uart0_mem_force_pd",
-                &format_args!("{}", self.uart0_mem_force_pd().bit()),
-            )
+            .field("uart0_mem_force_pu", &self.uart0_mem_force_pu())
+            .field("uart0_mem_force_pd", &self.uart0_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART0_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set this bit to force power down UART0 memory."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/uart0_sclk_conf.rs b/esp32h2/src/pcr/uart0_sclk_conf.rs
index 1d4f6cb5b5..5e229850d0 100644
--- a/esp32h2/src/pcr/uart0_sclk_conf.rs
+++ b/esp32h2/src/pcr/uart0_sclk_conf.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART0_SCLK_CONF")
-            .field(
-                "uart0_sclk_div_a",
-                &format_args!("{}", self.uart0_sclk_div_a().bits()),
-            )
-            .field(
-                "uart0_sclk_div_b",
-                &format_args!("{}", self.uart0_sclk_div_b().bits()),
-            )
-            .field(
-                "uart0_sclk_div_num",
-                &format_args!("{}", self.uart0_sclk_div_num().bits()),
-            )
-            .field(
-                "uart0_sclk_sel",
-                &format_args!("{}", self.uart0_sclk_sel().bits()),
-            )
-            .field(
-                "uart0_sclk_en",
-                &format_args!("{}", self.uart0_sclk_en().bit()),
-            )
+            .field("uart0_sclk_div_a", &self.uart0_sclk_div_a())
+            .field("uart0_sclk_div_b", &self.uart0_sclk_div_b())
+            .field("uart0_sclk_div_num", &self.uart0_sclk_div_num())
+            .field("uart0_sclk_sel", &self.uart0_sclk_sel())
+            .field("uart0_sclk_en", &self.uart0_sclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART0_SCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart0 function clock."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/uart1_conf.rs b/esp32h2/src/pcr/uart1_conf.rs
index 1b3f019ec0..31b84ed2b2 100644
--- a/esp32h2/src/pcr/uart1_conf.rs
+++ b/esp32h2/src/pcr/uart1_conf.rs
@@ -33,24 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART1_CONF")
-            .field(
-                "uart1_clk_en",
-                &format_args!("{}", self.uart1_clk_en().bit()),
-            )
-            .field(
-                "uart1_rst_en",
-                &format_args!("{}", self.uart1_rst_en().bit()),
-            )
-            .field("uart1_ready", &format_args!("{}", self.uart1_ready().bit()))
+            .field("uart1_clk_en", &self.uart1_clk_en())
+            .field("uart1_rst_en", &self.uart1_rst_en())
+            .field("uart1_ready", &self.uart1_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART1_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable uart1 apb clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/uart1_pd_ctrl.rs b/esp32h2/src/pcr/uart1_pd_ctrl.rs
index 8c53db3baf..fde1bc2bf7 100644
--- a/esp32h2/src/pcr/uart1_pd_ctrl.rs
+++ b/esp32h2/src/pcr/uart1_pd_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART1_PD_CTRL")
-            .field(
-                "uart1_mem_force_pu",
-                &format_args!("{}", self.uart1_mem_force_pu().bit()),
-            )
-            .field(
-                "uart1_mem_force_pd",
-                &format_args!("{}", self.uart1_mem_force_pd().bit()),
-            )
+            .field("uart1_mem_force_pu", &self.uart1_mem_force_pu())
+            .field("uart1_mem_force_pd", &self.uart1_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART1_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set this bit to force power down UART1 memory."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/uart1_sclk_conf.rs b/esp32h2/src/pcr/uart1_sclk_conf.rs
index 39dca3f2bc..bb5e30e41d 100644
--- a/esp32h2/src/pcr/uart1_sclk_conf.rs
+++ b/esp32h2/src/pcr/uart1_sclk_conf.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART1_SCLK_CONF")
-            .field(
-                "uart1_sclk_div_a",
-                &format_args!("{}", self.uart1_sclk_div_a().bits()),
-            )
-            .field(
-                "uart1_sclk_div_b",
-                &format_args!("{}", self.uart1_sclk_div_b().bits()),
-            )
-            .field(
-                "uart1_sclk_div_num",
-                &format_args!("{}", self.uart1_sclk_div_num().bits()),
-            )
-            .field(
-                "uart1_sclk_sel",
-                &format_args!("{}", self.uart1_sclk_sel().bits()),
-            )
-            .field(
-                "uart1_sclk_en",
-                &format_args!("{}", self.uart1_sclk_en().bit()),
-            )
+            .field("uart1_sclk_div_a", &self.uart1_sclk_div_a())
+            .field("uart1_sclk_div_b", &self.uart1_sclk_div_b())
+            .field("uart1_sclk_div_num", &self.uart1_sclk_div_num())
+            .field("uart1_sclk_sel", &self.uart1_sclk_sel())
+            .field("uart1_sclk_en", &self.uart1_sclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART1_SCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor of the uart1 function clock."]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/uhci_conf.rs b/esp32h2/src/pcr/uhci_conf.rs
index 840195ae2e..1a3a4b5d7a 100644
--- a/esp32h2/src/pcr/uhci_conf.rs
+++ b/esp32h2/src/pcr/uhci_conf.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UHCI_CONF")
-            .field("uhci_clk_en", &format_args!("{}", self.uhci_clk_en().bit()))
-            .field("uhci_rst_en", &format_args!("{}", self.uhci_rst_en().bit()))
-            .field("uhci_ready", &format_args!("{}", self.uhci_ready().bit()))
+            .field("uhci_clk_en", &self.uhci_clk_en())
+            .field("uhci_rst_en", &self.uhci_rst_en())
+            .field("uhci_ready", &self.uhci_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UHCI_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable uhci clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pcr/usb_device_conf.rs b/esp32h2/src/pcr/usb_device_conf.rs
index 3f610e335c..2e8096135c 100644
--- a/esp32h2/src/pcr/usb_device_conf.rs
+++ b/esp32h2/src/pcr/usb_device_conf.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_DEVICE_CONF")
-            .field(
-                "usb_device_clk_en",
-                &format_args!("{}", self.usb_device_clk_en().bit()),
-            )
-            .field(
-                "usb_device_rst_en",
-                &format_args!("{}", self.usb_device_rst_en().bit()),
-            )
-            .field(
-                "usb_device_ready",
-                &format_args!("{}", self.usb_device_ready().bit()),
-            )
+            .field("usb_device_clk_en", &self.usb_device_clk_en())
+            .field("usb_device_rst_en", &self.usb_device_rst_en())
+            .field("usb_device_ready", &self.usb_device_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_DEVICE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable usb_device clock"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/backup_cfg.rs b/esp32h2/src/pmu/backup_cfg.rs
index e503db6afd..c2d51cd862 100644
--- a/esp32h2/src/pmu/backup_cfg.rs
+++ b/esp32h2/src/pmu/backup_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BACKUP_CFG")
-            .field(
-                "backup_sys_clk_no_div",
-                &format_args!("{}", self.backup_sys_clk_no_div().bit()),
-            )
+            .field("backup_sys_clk_no_div", &self.backup_sys_clk_no_div())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/clk_state0.rs b/esp32h2/src/pmu/clk_state0.rs
index baf19828d4..908319a1da 100644
--- a/esp32h2/src/pmu/clk_state0.rs
+++ b/esp32h2/src/pmu/clk_state0.rs
@@ -125,83 +125,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_STATE0")
-            .field(
-                "stable_xpd_bbpll_state",
-                &format_args!("{}", self.stable_xpd_bbpll_state().bit()),
-            )
-            .field(
-                "stable_xpd_xtal_state",
-                &format_args!("{}", self.stable_xpd_xtal_state().bit()),
-            )
-            .field(
-                "sys_clk_slp_sel_state",
-                &format_args!("{}", self.sys_clk_slp_sel_state().bit()),
-            )
-            .field(
-                "sys_clk_sel_state",
-                &format_args!("{}", self.sys_clk_sel_state().bits()),
-            )
-            .field(
-                "sys_clk_no_div_state",
-                &format_args!("{}", self.sys_clk_no_div_state().bit()),
-            )
-            .field(
-                "icg_sys_clk_en_state",
-                &format_args!("{}", self.icg_sys_clk_en_state().bit()),
-            )
-            .field(
-                "icg_modem_switch_state",
-                &format_args!("{}", self.icg_modem_switch_state().bit()),
-            )
-            .field(
-                "icg_modem_code_state",
-                &format_args!("{}", self.icg_modem_code_state().bits()),
-            )
-            .field(
-                "icg_slp_sel_state",
-                &format_args!("{}", self.icg_slp_sel_state().bit()),
-            )
-            .field(
-                "icg_global_xtal_state",
-                &format_args!("{}", self.icg_global_xtal_state().bit()),
-            )
-            .field(
-                "icg_global_pll_state",
-                &format_args!("{}", self.icg_global_pll_state().bit()),
-            )
-            .field(
-                "ana_i2c_iso_en_state",
-                &format_args!("{}", self.ana_i2c_iso_en_state().bit()),
-            )
-            .field(
-                "ana_i2c_retention_state",
-                &format_args!("{}", self.ana_i2c_retention_state().bit()),
-            )
-            .field(
-                "ana_xpd_bb_i2c_state",
-                &format_args!("{}", self.ana_xpd_bb_i2c_state().bit()),
-            )
-            .field(
-                "ana_xpd_bbpll_i2c_state",
-                &format_args!("{}", self.ana_xpd_bbpll_i2c_state().bit()),
-            )
-            .field(
-                "ana_xpd_bbpll_state",
-                &format_args!("{}", self.ana_xpd_bbpll_state().bit()),
-            )
-            .field(
-                "ana_xpd_xtal_state",
-                &format_args!("{}", self.ana_xpd_xtal_state().bit()),
-            )
+            .field("stable_xpd_bbpll_state", &self.stable_xpd_bbpll_state())
+            .field("stable_xpd_xtal_state", &self.stable_xpd_xtal_state())
+            .field("sys_clk_slp_sel_state", &self.sys_clk_slp_sel_state())
+            .field("sys_clk_sel_state", &self.sys_clk_sel_state())
+            .field("sys_clk_no_div_state", &self.sys_clk_no_div_state())
+            .field("icg_sys_clk_en_state", &self.icg_sys_clk_en_state())
+            .field("icg_modem_switch_state", &self.icg_modem_switch_state())
+            .field("icg_modem_code_state", &self.icg_modem_code_state())
+            .field("icg_slp_sel_state", &self.icg_slp_sel_state())
+            .field("icg_global_xtal_state", &self.icg_global_xtal_state())
+            .field("icg_global_pll_state", &self.icg_global_pll_state())
+            .field("ana_i2c_iso_en_state", &self.ana_i2c_iso_en_state())
+            .field("ana_i2c_retention_state", &self.ana_i2c_retention_state())
+            .field("ana_xpd_bb_i2c_state", &self.ana_xpd_bb_i2c_state())
+            .field("ana_xpd_bbpll_i2c_state", &self.ana_xpd_bbpll_i2c_state())
+            .field("ana_xpd_bbpll_state", &self.ana_xpd_bbpll_state())
+            .field("ana_xpd_xtal_state", &self.ana_xpd_xtal_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_state0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_STATE0_SPEC;
 impl crate::RegisterSpec for CLK_STATE0_SPEC {
diff --git a/esp32h2/src/pmu/clk_state1.rs b/esp32h2/src/pmu/clk_state1.rs
index c28cc9c408..65ae7f5c63 100644
--- a/esp32h2/src/pmu/clk_state1.rs
+++ b/esp32h2/src/pmu/clk_state1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_STATE1")
-            .field(
-                "icg_func_en_state",
-                &format_args!("{}", self.icg_func_en_state().bits()),
-            )
+            .field("icg_func_en_state", &self.icg_func_en_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_STATE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_state1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_STATE1_SPEC;
 impl crate::RegisterSpec for CLK_STATE1_SPEC {
diff --git a/esp32h2/src/pmu/clk_state2.rs b/esp32h2/src/pmu/clk_state2.rs
index 2f9e9f476c..41d273164f 100644
--- a/esp32h2/src/pmu/clk_state2.rs
+++ b/esp32h2/src/pmu/clk_state2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_STATE2")
-            .field(
-                "icg_apb_en_state",
-                &format_args!("{}", self.icg_apb_en_state().bits()),
-            )
+            .field("icg_apb_en_state", &self.icg_apb_en_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_STATE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_state2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_STATE2_SPEC;
 impl crate::RegisterSpec for CLK_STATE2_SPEC {
diff --git a/esp32h2/src/pmu/date.rs b/esp32h2/src/pmu/date.rs
index cca2101f65..168bb87e82 100644
--- a/esp32h2/src/pmu/date.rs
+++ b/esp32h2/src/pmu/date.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("pmu_date", &format_args!("{}", self.pmu_date().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("pmu_date", &self.pmu_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_active_backup.rs b/esp32h2/src/pmu/hp_active_backup.rs
index 62f9dc774b..121423fc4c 100644
--- a/esp32h2/src/pmu/hp_active_backup.rs
+++ b/esp32h2/src/pmu/hp_active_backup.rs
@@ -109,57 +109,48 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_BACKUP")
             .field(
                 "hp_sleep2active_backup_modem_clk_code",
-                &format_args!("{}", self.hp_sleep2active_backup_modem_clk_code().bits()),
+                &self.hp_sleep2active_backup_modem_clk_code(),
             )
             .field(
                 "hp_modem2active_backup_modem_clk_code",
-                &format_args!("{}", self.hp_modem2active_backup_modem_clk_code().bits()),
-            )
-            .field(
-                "hp_active_retention_mode",
-                &format_args!("{}", self.hp_active_retention_mode().bit()),
+                &self.hp_modem2active_backup_modem_clk_code(),
             )
+            .field("hp_active_retention_mode", &self.hp_active_retention_mode())
             .field(
                 "hp_sleep2active_retention_en",
-                &format_args!("{}", self.hp_sleep2active_retention_en().bit()),
+                &self.hp_sleep2active_retention_en(),
             )
             .field(
                 "hp_modem2active_retention_en",
-                &format_args!("{}", self.hp_modem2active_retention_en().bit()),
+                &self.hp_modem2active_retention_en(),
             )
             .field(
                 "hp_sleep2active_backup_clk_sel",
-                &format_args!("{}", self.hp_sleep2active_backup_clk_sel().bits()),
+                &self.hp_sleep2active_backup_clk_sel(),
             )
             .field(
                 "hp_modem2active_backup_clk_sel",
-                &format_args!("{}", self.hp_modem2active_backup_clk_sel().bits()),
+                &self.hp_modem2active_backup_clk_sel(),
             )
             .field(
                 "hp_sleep2active_backup_mode",
-                &format_args!("{}", self.hp_sleep2active_backup_mode().bits()),
+                &self.hp_sleep2active_backup_mode(),
             )
             .field(
                 "hp_modem2active_backup_mode",
-                &format_args!("{}", self.hp_modem2active_backup_mode().bits()),
+                &self.hp_modem2active_backup_mode(),
             )
             .field(
                 "hp_sleep2active_backup_en",
-                &format_args!("{}", self.hp_sleep2active_backup_en().bit()),
+                &self.hp_sleep2active_backup_en(),
             )
             .field(
                 "hp_modem2active_backup_en",
-                &format_args!("{}", self.hp_modem2active_backup_en().bit()),
+                &self.hp_modem2active_backup_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_BACKUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 4:5 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_active_backup_clk.rs b/esp32h2/src/pmu/hp_active_backup_clk.rs
index 263dfe5caa..86da7e6aa1 100644
--- a/esp32h2/src/pmu/hp_active_backup_clk.rs
+++ b/esp32h2/src/pmu/hp_active_backup_clk.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_BACKUP_CLK")
             .field(
                 "hp_active_backup_icg_func_en",
-                &format_args!("{}", self.hp_active_backup_icg_func_en().bits()),
+                &self.hp_active_backup_icg_func_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_BACKUP_CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_active_bias.rs b/esp32h2/src/pmu/hp_active_bias.rs
index ac578fd16b..1e91a7b9e5 100644
--- a/esp32h2/src/pmu/hp_active_bias.rs
+++ b/esp32h2/src/pmu/hp_active_bias.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_BIAS")
-            .field(
-                "hp_active_xpd_trx",
-                &format_args!("{}", self.hp_active_xpd_trx().bit()),
-            )
-            .field(
-                "hp_active_xpd_bias",
-                &format_args!("{}", self.hp_active_xpd_bias().bit()),
-            )
-            .field(
-                "hp_active_pd_cur",
-                &format_args!("{}", self.hp_active_pd_cur().bit()),
-            )
-            .field("sleep", &format_args!("{}", self.sleep().bit()))
+            .field("hp_active_xpd_trx", &self.hp_active_xpd_trx())
+            .field("hp_active_xpd_bias", &self.hp_active_xpd_bias())
+            .field("hp_active_pd_cur", &self.hp_active_pd_cur())
+            .field("sleep", &self.sleep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_BIAS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_active_dig_power.rs b/esp32h2/src/pmu/hp_active_dig_power.rs
index 51e065fa88..ec5b3e3a42 100644
--- a/esp32h2/src/pmu/hp_active_dig_power.rs
+++ b/esp32h2/src/pmu/hp_active_dig_power.rs
@@ -71,43 +71,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_DIG_POWER")
-            .field(
-                "hp_active_vdd_spi_pd_en",
-                &format_args!("{}", self.hp_active_vdd_spi_pd_en().bit()),
-            )
-            .field(
-                "hp_active_hp_mem_dslp",
-                &format_args!("{}", self.hp_active_hp_mem_dslp().bit()),
-            )
+            .field("hp_active_vdd_spi_pd_en", &self.hp_active_vdd_spi_pd_en())
+            .field("hp_active_hp_mem_dslp", &self.hp_active_hp_mem_dslp())
             .field(
                 "hp_active_pd_hp_mem_pd_en",
-                &format_args!("{}", self.hp_active_pd_hp_mem_pd_en().bits()),
+                &self.hp_active_pd_hp_mem_pd_en(),
             )
             .field(
                 "hp_active_pd_hp_wifi_pd_en",
-                &format_args!("{}", self.hp_active_pd_hp_wifi_pd_en().bit()),
+                &self.hp_active_pd_hp_wifi_pd_en(),
             )
             .field(
                 "hp_active_pd_hp_cpu_pd_en",
-                &format_args!("{}", self.hp_active_pd_hp_cpu_pd_en().bit()),
+                &self.hp_active_pd_hp_cpu_pd_en(),
             )
             .field(
                 "hp_active_pd_hp_aon_pd_en",
-                &format_args!("{}", self.hp_active_pd_hp_aon_pd_en().bit()),
-            )
-            .field(
-                "hp_active_pd_top_pd_en",
-                &format_args!("{}", self.hp_active_pd_top_pd_en().bit()),
+                &self.hp_active_pd_hp_aon_pd_en(),
             )
+            .field("hp_active_pd_top_pd_en", &self.hp_active_pd_top_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_DIG_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_active_hp_ck_power.rs b/esp32h2/src/pmu/hp_active_hp_ck_power.rs
index 85bec26de6..93fdfa3b86 100644
--- a/esp32h2/src/pmu/hp_active_hp_ck_power.rs
+++ b/esp32h2/src/pmu/hp_active_hp_ck_power.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_HP_CK_POWER")
-            .field(
-                "hp_active_i2c_iso_en",
-                &format_args!("{}", self.hp_active_i2c_iso_en().bit()),
-            )
-            .field(
-                "hp_active_i2c_retention",
-                &format_args!("{}", self.hp_active_i2c_retention().bit()),
-            )
-            .field(
-                "hp_active_xpd_bb_i2c",
-                &format_args!("{}", self.hp_active_xpd_bb_i2c().bit()),
-            )
-            .field(
-                "hp_active_xpd_bbpll_i2c",
-                &format_args!("{}", self.hp_active_xpd_bbpll_i2c().bit()),
-            )
-            .field(
-                "hp_active_xpd_bbpll",
-                &format_args!("{}", self.hp_active_xpd_bbpll().bit()),
-            )
+            .field("hp_active_i2c_iso_en", &self.hp_active_i2c_iso_en())
+            .field("hp_active_i2c_retention", &self.hp_active_i2c_retention())
+            .field("hp_active_xpd_bb_i2c", &self.hp_active_xpd_bb_i2c())
+            .field("hp_active_xpd_bbpll_i2c", &self.hp_active_xpd_bbpll_i2c())
+            .field("hp_active_xpd_bbpll", &self.hp_active_xpd_bbpll())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_HP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_active_hp_regulator0.rs b/esp32h2/src/pmu/hp_active_hp_regulator0.rs
index e41a5cf6e4..9f79f8477f 100644
--- a/esp32h2/src/pmu/hp_active_hp_regulator0.rs
+++ b/esp32h2/src/pmu/hp_active_hp_regulator0.rs
@@ -100,53 +100,38 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_HP_REGULATOR0")
             .field(
                 "hp_active_hp_power_det_bypass",
-                &format_args!("{}", self.hp_active_hp_power_det_bypass().bit()),
-            )
-            .field(
-                "lp_dbias_vol",
-                &format_args!("{}", self.lp_dbias_vol().bits()),
-            )
-            .field(
-                "hp_dbias_vol",
-                &format_args!("{}", self.hp_dbias_vol().bits()),
-            )
-            .field(
-                "dig_regulator0_dbias_sel",
-                &format_args!("{}", self.dig_regulator0_dbias_sel().bit()),
+                &self.hp_active_hp_power_det_bypass(),
             )
+            .field("lp_dbias_vol", &self.lp_dbias_vol())
+            .field("hp_dbias_vol", &self.hp_dbias_vol())
+            .field("dig_regulator0_dbias_sel", &self.dig_regulator0_dbias_sel())
             .field(
                 "hp_active_hp_regulator_slp_mem_xpd",
-                &format_args!("{}", self.hp_active_hp_regulator_slp_mem_xpd().bit()),
+                &self.hp_active_hp_regulator_slp_mem_xpd(),
             )
             .field(
                 "hp_active_hp_regulator_slp_logic_xpd",
-                &format_args!("{}", self.hp_active_hp_regulator_slp_logic_xpd().bit()),
+                &self.hp_active_hp_regulator_slp_logic_xpd(),
             )
             .field(
                 "hp_active_hp_regulator_xpd",
-                &format_args!("{}", self.hp_active_hp_regulator_xpd().bit()),
+                &self.hp_active_hp_regulator_xpd(),
             )
             .field(
                 "hp_active_hp_regulator_slp_mem_dbias",
-                &format_args!("{}", self.hp_active_hp_regulator_slp_mem_dbias().bits()),
+                &self.hp_active_hp_regulator_slp_mem_dbias(),
             )
             .field(
                 "hp_active_hp_regulator_slp_logic_dbias",
-                &format_args!("{}", self.hp_active_hp_regulator_slp_logic_dbias().bits()),
+                &self.hp_active_hp_regulator_slp_logic_dbias(),
             )
             .field(
                 "hp_active_hp_regulator_dbias",
-                &format_args!("{}", self.hp_active_hp_regulator_dbias().bits()),
+                &self.hp_active_hp_regulator_dbias(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_HP_REGULATOR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_active_hp_regulator1.rs b/esp32h2/src/pmu/hp_active_hp_regulator1.rs
index c5919ecbe3..81ee1a76d8 100644
--- a/esp32h2/src/pmu/hp_active_hp_regulator1.rs
+++ b/esp32h2/src/pmu/hp_active_hp_regulator1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_HP_REGULATOR1")
             .field(
                 "hp_active_hp_regulator_drv_b",
-                &format_args!("{}", self.hp_active_hp_regulator_drv_b().bits()),
+                &self.hp_active_hp_regulator_drv_b(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_HP_REGULATOR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_active_hp_sys_cntl.rs b/esp32h2/src/pmu/hp_active_hp_sys_cntl.rs
index 8cfe8b271d..e2bf7341ab 100644
--- a/esp32h2/src/pmu/hp_active_hp_sys_cntl.rs
+++ b/esp32h2/src/pmu/hp_active_hp_sys_cntl.rs
@@ -62,39 +62,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_HP_SYS_CNTL")
-            .field(
-                "hp_active_uart_wakeup_en",
-                &format_args!("{}", self.hp_active_uart_wakeup_en().bit()),
-            )
+            .field("hp_active_uart_wakeup_en", &self.hp_active_uart_wakeup_en())
             .field(
                 "hp_active_lp_pad_hold_all",
-                &format_args!("{}", self.hp_active_lp_pad_hold_all().bit()),
+                &self.hp_active_lp_pad_hold_all(),
             )
             .field(
                 "hp_active_hp_pad_hold_all",
-                &format_args!("{}", self.hp_active_hp_pad_hold_all().bit()),
+                &self.hp_active_hp_pad_hold_all(),
             )
             .field(
                 "hp_active_dig_pad_slp_sel",
-                &format_args!("{}", self.hp_active_dig_pad_slp_sel().bit()),
-            )
-            .field(
-                "hp_active_dig_pause_wdt",
-                &format_args!("{}", self.hp_active_dig_pause_wdt().bit()),
-            )
-            .field(
-                "hp_active_dig_cpu_stall",
-                &format_args!("{}", self.hp_active_dig_cpu_stall().bit()),
+                &self.hp_active_dig_pad_slp_sel(),
             )
+            .field("hp_active_dig_pause_wdt", &self.hp_active_dig_pause_wdt())
+            .field("hp_active_dig_cpu_stall", &self.hp_active_dig_cpu_stall())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_HP_SYS_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_active_icg_hp_apb.rs b/esp32h2/src/pmu/hp_active_icg_hp_apb.rs
index 6f5c572621..bce128b876 100644
--- a/esp32h2/src/pmu/hp_active_icg_hp_apb.rs
+++ b/esp32h2/src/pmu/hp_active_icg_hp_apb.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_ICG_HP_APB")
-            .field(
-                "hp_active_dig_icg_apb_en",
-                &format_args!("{}", self.hp_active_dig_icg_apb_en().bits()),
-            )
+            .field("hp_active_dig_icg_apb_en", &self.hp_active_dig_icg_apb_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_ICG_HP_APB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_active_icg_hp_func.rs b/esp32h2/src/pmu/hp_active_icg_hp_func.rs
index 66f7bfc1cc..9702957d41 100644
--- a/esp32h2/src/pmu/hp_active_icg_hp_func.rs
+++ b/esp32h2/src/pmu/hp_active_icg_hp_func.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_ICG_HP_FUNC")
             .field(
                 "hp_active_dig_icg_func_en",
-                &format_args!("{}", self.hp_active_dig_icg_func_en().bits()),
+                &self.hp_active_dig_icg_func_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_ICG_HP_FUNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_active_icg_modem.rs b/esp32h2/src/pmu/hp_active_icg_modem.rs
index 6bec45bec6..191bc539f8 100644
--- a/esp32h2/src/pmu/hp_active_icg_modem.rs
+++ b/esp32h2/src/pmu/hp_active_icg_modem.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_ICG_MODEM")
             .field(
                 "hp_active_dig_icg_modem_code",
-                &format_args!("{}", self.hp_active_dig_icg_modem_code().bits()),
+                &self.hp_active_dig_icg_modem_code(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_ICG_MODEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 30:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_active_sysclk.rs b/esp32h2/src/pmu/hp_active_sysclk.rs
index 6c8183a1a1..210c9638ed 100644
--- a/esp32h2/src/pmu/hp_active_sysclk.rs
+++ b/esp32h2/src/pmu/hp_active_sysclk.rs
@@ -55,33 +55,24 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_SYSCLK")
             .field(
                 "hp_active_dig_sys_clk_no_div",
-                &format_args!("{}", self.hp_active_dig_sys_clk_no_div().bit()),
+                &self.hp_active_dig_sys_clk_no_div(),
             )
             .field(
                 "hp_active_icg_sys_clock_en",
-                &format_args!("{}", self.hp_active_icg_sys_clock_en().bit()),
+                &self.hp_active_icg_sys_clock_en(),
             )
             .field(
                 "hp_active_sys_clk_slp_sel",
-                &format_args!("{}", self.hp_active_sys_clk_slp_sel().bit()),
-            )
-            .field(
-                "hp_active_icg_slp_sel",
-                &format_args!("{}", self.hp_active_icg_slp_sel().bit()),
+                &self.hp_active_sys_clk_slp_sel(),
             )
+            .field("hp_active_icg_slp_sel", &self.hp_active_icg_slp_sel())
             .field(
                 "hp_active_dig_sys_clk_sel",
-                &format_args!("{}", self.hp_active_dig_sys_clk_sel().bits()),
+                &self.hp_active_dig_sys_clk_sel(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_SYSCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_active_xtal.rs b/esp32h2/src/pmu/hp_active_xtal.rs
index 2bee4e63fa..9a8de33501 100644
--- a/esp32h2/src/pmu/hp_active_xtal.rs
+++ b/esp32h2/src/pmu/hp_active_xtal.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_XTAL")
-            .field(
-                "hp_active_xpd_xtal",
-                &format_args!("{}", self.hp_active_xpd_xtal().bit()),
-            )
+            .field("hp_active_xpd_xtal", &self.hp_active_xpd_xtal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_XTAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_ck_cntl.rs b/esp32h2/src/pmu/hp_ck_cntl.rs
index 324311fa38..a85fe2cf77 100644
--- a/esp32h2/src/pmu/hp_ck_cntl.rs
+++ b/esp32h2/src/pmu/hp_ck_cntl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_CK_CNTL")
-            .field(
-                "modify_icg_cntl_wait",
-                &format_args!("{}", self.modify_icg_cntl_wait().bits()),
-            )
-            .field(
-                "switch_icg_cntl_wait",
-                &format_args!("{}", self.switch_icg_cntl_wait().bits()),
-            )
+            .field("modify_icg_cntl_wait", &self.modify_icg_cntl_wait())
+            .field("switch_icg_cntl_wait", &self.switch_icg_cntl_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_CK_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_ck_poweron.rs b/esp32h2/src/pmu/hp_ck_poweron.rs
index 294f83088c..4242d0c588 100644
--- a/esp32h2/src/pmu/hp_ck_poweron.rs
+++ b/esp32h2/src/pmu/hp_ck_poweron.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_CK_POWERON")
-            .field(
-                "i2c_por_wait_target",
-                &format_args!("{}", self.i2c_por_wait_target().bits()),
-            )
+            .field("i2c_por_wait_target", &self.i2c_por_wait_target())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_CK_POWERON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_modem_backup.rs b/esp32h2/src/pmu/hp_modem_backup.rs
index 46730163af..9bc9527ee3 100644
--- a/esp32h2/src/pmu/hp_modem_backup.rs
+++ b/esp32h2/src/pmu/hp_modem_backup.rs
@@ -64,37 +64,25 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_MODEM_BACKUP")
             .field(
                 "hp_sleep2modem_backup_modem_clk_code",
-                &format_args!("{}", self.hp_sleep2modem_backup_modem_clk_code().bits()),
-            )
-            .field(
-                "hp_modem_retention_mode",
-                &format_args!("{}", self.hp_modem_retention_mode().bit()),
+                &self.hp_sleep2modem_backup_modem_clk_code(),
             )
+            .field("hp_modem_retention_mode", &self.hp_modem_retention_mode())
             .field(
                 "hp_sleep2modem_retention_en",
-                &format_args!("{}", self.hp_sleep2modem_retention_en().bit()),
+                &self.hp_sleep2modem_retention_en(),
             )
             .field(
                 "hp_sleep2modem_backup_clk_sel",
-                &format_args!("{}", self.hp_sleep2modem_backup_clk_sel().bits()),
+                &self.hp_sleep2modem_backup_clk_sel(),
             )
             .field(
                 "hp_sleep2modem_backup_mode",
-                &format_args!("{}", self.hp_sleep2modem_backup_mode().bits()),
-            )
-            .field(
-                "hp_sleep2modem_backup_en",
-                &format_args!("{}", self.hp_sleep2modem_backup_en().bit()),
+                &self.hp_sleep2modem_backup_mode(),
             )
+            .field("hp_sleep2modem_backup_en", &self.hp_sleep2modem_backup_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_BACKUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 4:5 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_modem_backup_clk.rs b/esp32h2/src/pmu/hp_modem_backup_clk.rs
index a84a7f4ffa..6aeeb8d754 100644
--- a/esp32h2/src/pmu/hp_modem_backup_clk.rs
+++ b/esp32h2/src/pmu/hp_modem_backup_clk.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_MODEM_BACKUP_CLK")
             .field(
                 "hp_modem_backup_icg_func_en",
-                &format_args!("{}", self.hp_modem_backup_icg_func_en().bits()),
+                &self.hp_modem_backup_icg_func_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_BACKUP_CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_modem_bias.rs b/esp32h2/src/pmu/hp_modem_bias.rs
index 40540597c2..e16f9c5b76 100644
--- a/esp32h2/src/pmu/hp_modem_bias.rs
+++ b/esp32h2/src/pmu/hp_modem_bias.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_MODEM_BIAS")
-            .field(
-                "hp_modem_xpd_trx",
-                &format_args!("{}", self.hp_modem_xpd_trx().bit()),
-            )
-            .field(
-                "hp_modem_xpd_bias",
-                &format_args!("{}", self.hp_modem_xpd_bias().bit()),
-            )
-            .field(
-                "hp_modem_pd_cur",
-                &format_args!("{}", self.hp_modem_pd_cur().bit()),
-            )
-            .field("sleep", &format_args!("{}", self.sleep().bit()))
+            .field("hp_modem_xpd_trx", &self.hp_modem_xpd_trx())
+            .field("hp_modem_xpd_bias", &self.hp_modem_xpd_bias())
+            .field("hp_modem_pd_cur", &self.hp_modem_pd_cur())
+            .field("sleep", &self.sleep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_BIAS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_modem_dig_power.rs b/esp32h2/src/pmu/hp_modem_dig_power.rs
index b22961e778..3534688e3e 100644
--- a/esp32h2/src/pmu/hp_modem_dig_power.rs
+++ b/esp32h2/src/pmu/hp_modem_dig_power.rs
@@ -71,43 +71,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_MODEM_DIG_POWER")
-            .field(
-                "hp_modem_vdd_spi_pd_en",
-                &format_args!("{}", self.hp_modem_vdd_spi_pd_en().bit()),
-            )
-            .field(
-                "hp_modem_hp_mem_dslp",
-                &format_args!("{}", self.hp_modem_hp_mem_dslp().bit()),
-            )
-            .field(
-                "hp_modem_pd_hp_mem_pd_en",
-                &format_args!("{}", self.hp_modem_pd_hp_mem_pd_en().bits()),
-            )
+            .field("hp_modem_vdd_spi_pd_en", &self.hp_modem_vdd_spi_pd_en())
+            .field("hp_modem_hp_mem_dslp", &self.hp_modem_hp_mem_dslp())
+            .field("hp_modem_pd_hp_mem_pd_en", &self.hp_modem_pd_hp_mem_pd_en())
             .field(
                 "hp_modem_pd_hp_wifi_pd_en",
-                &format_args!("{}", self.hp_modem_pd_hp_wifi_pd_en().bit()),
-            )
-            .field(
-                "hp_modem_pd_hp_cpu_pd_en",
-                &format_args!("{}", self.hp_modem_pd_hp_cpu_pd_en().bit()),
-            )
-            .field(
-                "hp_modem_pd_hp_aon_pd_en",
-                &format_args!("{}", self.hp_modem_pd_hp_aon_pd_en().bit()),
-            )
-            .field(
-                "hp_modem_pd_top_pd_en",
-                &format_args!("{}", self.hp_modem_pd_top_pd_en().bit()),
+                &self.hp_modem_pd_hp_wifi_pd_en(),
             )
+            .field("hp_modem_pd_hp_cpu_pd_en", &self.hp_modem_pd_hp_cpu_pd_en())
+            .field("hp_modem_pd_hp_aon_pd_en", &self.hp_modem_pd_hp_aon_pd_en())
+            .field("hp_modem_pd_top_pd_en", &self.hp_modem_pd_top_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_DIG_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_modem_hp_ck_power.rs b/esp32h2/src/pmu/hp_modem_hp_ck_power.rs
index 411a015316..ebb6d6c06b 100644
--- a/esp32h2/src/pmu/hp_modem_hp_ck_power.rs
+++ b/esp32h2/src/pmu/hp_modem_hp_ck_power.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_MODEM_HP_CK_POWER")
-            .field(
-                "hp_modem_i2c_iso_en",
-                &format_args!("{}", self.hp_modem_i2c_iso_en().bit()),
-            )
-            .field(
-                "hp_modem_i2c_retention",
-                &format_args!("{}", self.hp_modem_i2c_retention().bit()),
-            )
-            .field(
-                "hp_modem_xpd_bb_i2c",
-                &format_args!("{}", self.hp_modem_xpd_bb_i2c().bit()),
-            )
-            .field(
-                "hp_modem_xpd_bbpll_i2c",
-                &format_args!("{}", self.hp_modem_xpd_bbpll_i2c().bit()),
-            )
-            .field(
-                "hp_modem_xpd_bbpll",
-                &format_args!("{}", self.hp_modem_xpd_bbpll().bit()),
-            )
+            .field("hp_modem_i2c_iso_en", &self.hp_modem_i2c_iso_en())
+            .field("hp_modem_i2c_retention", &self.hp_modem_i2c_retention())
+            .field("hp_modem_xpd_bb_i2c", &self.hp_modem_xpd_bb_i2c())
+            .field("hp_modem_xpd_bbpll_i2c", &self.hp_modem_xpd_bbpll_i2c())
+            .field("hp_modem_xpd_bbpll", &self.hp_modem_xpd_bbpll())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_HP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_modem_hp_regulator0.rs b/esp32h2/src/pmu/hp_modem_hp_regulator0.rs
index 3b44e55c1f..4e33af0751 100644
--- a/esp32h2/src/pmu/hp_modem_hp_regulator0.rs
+++ b/esp32h2/src/pmu/hp_modem_hp_regulator0.rs
@@ -73,41 +73,35 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_MODEM_HP_REGULATOR0")
             .field(
                 "hp_modem_hp_power_det_bypass",
-                &format_args!("{}", self.hp_modem_hp_power_det_bypass().bit()),
+                &self.hp_modem_hp_power_det_bypass(),
             )
             .field(
                 "hp_modem_hp_regulator_slp_mem_xpd",
-                &format_args!("{}", self.hp_modem_hp_regulator_slp_mem_xpd().bit()),
+                &self.hp_modem_hp_regulator_slp_mem_xpd(),
             )
             .field(
                 "hp_modem_hp_regulator_slp_logic_xpd",
-                &format_args!("{}", self.hp_modem_hp_regulator_slp_logic_xpd().bit()),
+                &self.hp_modem_hp_regulator_slp_logic_xpd(),
             )
             .field(
                 "hp_modem_hp_regulator_xpd",
-                &format_args!("{}", self.hp_modem_hp_regulator_xpd().bit()),
+                &self.hp_modem_hp_regulator_xpd(),
             )
             .field(
                 "hp_modem_hp_regulator_slp_mem_dbias",
-                &format_args!("{}", self.hp_modem_hp_regulator_slp_mem_dbias().bits()),
+                &self.hp_modem_hp_regulator_slp_mem_dbias(),
             )
             .field(
                 "hp_modem_hp_regulator_slp_logic_dbias",
-                &format_args!("{}", self.hp_modem_hp_regulator_slp_logic_dbias().bits()),
+                &self.hp_modem_hp_regulator_slp_logic_dbias(),
             )
             .field(
                 "hp_modem_hp_regulator_dbias",
-                &format_args!("{}", self.hp_modem_hp_regulator_dbias().bits()),
+                &self.hp_modem_hp_regulator_dbias(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_HP_REGULATOR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_modem_hp_regulator1.rs b/esp32h2/src/pmu/hp_modem_hp_regulator1.rs
index d9fd7c3fa5..a4b0092260 100644
--- a/esp32h2/src/pmu/hp_modem_hp_regulator1.rs
+++ b/esp32h2/src/pmu/hp_modem_hp_regulator1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_MODEM_HP_REGULATOR1")
             .field(
                 "hp_modem_hp_regulator_drv_b",
-                &format_args!("{}", self.hp_modem_hp_regulator_drv_b().bits()),
+                &self.hp_modem_hp_regulator_drv_b(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_HP_REGULATOR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_modem_hp_sys_cntl.rs b/esp32h2/src/pmu/hp_modem_hp_sys_cntl.rs
index b4d65d6c5d..25d1a4223a 100644
--- a/esp32h2/src/pmu/hp_modem_hp_sys_cntl.rs
+++ b/esp32h2/src/pmu/hp_modem_hp_sys_cntl.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_MODEM_HP_SYS_CNTL")
-            .field(
-                "hp_modem_uart_wakeup_en",
-                &format_args!("{}", self.hp_modem_uart_wakeup_en().bit()),
-            )
-            .field(
-                "hp_modem_lp_pad_hold_all",
-                &format_args!("{}", self.hp_modem_lp_pad_hold_all().bit()),
-            )
-            .field(
-                "hp_modem_hp_pad_hold_all",
-                &format_args!("{}", self.hp_modem_hp_pad_hold_all().bit()),
-            )
-            .field(
-                "hp_modem_dig_pad_slp_sel",
-                &format_args!("{}", self.hp_modem_dig_pad_slp_sel().bit()),
-            )
-            .field(
-                "hp_modem_dig_pause_wdt",
-                &format_args!("{}", self.hp_modem_dig_pause_wdt().bit()),
-            )
-            .field(
-                "hp_modem_dig_cpu_stall",
-                &format_args!("{}", self.hp_modem_dig_cpu_stall().bit()),
-            )
+            .field("hp_modem_uart_wakeup_en", &self.hp_modem_uart_wakeup_en())
+            .field("hp_modem_lp_pad_hold_all", &self.hp_modem_lp_pad_hold_all())
+            .field("hp_modem_hp_pad_hold_all", &self.hp_modem_hp_pad_hold_all())
+            .field("hp_modem_dig_pad_slp_sel", &self.hp_modem_dig_pad_slp_sel())
+            .field("hp_modem_dig_pause_wdt", &self.hp_modem_dig_pause_wdt())
+            .field("hp_modem_dig_cpu_stall", &self.hp_modem_dig_cpu_stall())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_HP_SYS_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_modem_icg_hp_apb.rs b/esp32h2/src/pmu/hp_modem_icg_hp_apb.rs
index 850650ded0..610fe204cf 100644
--- a/esp32h2/src/pmu/hp_modem_icg_hp_apb.rs
+++ b/esp32h2/src/pmu/hp_modem_icg_hp_apb.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_MODEM_ICG_HP_APB")
-            .field(
-                "hp_modem_dig_icg_apb_en",
-                &format_args!("{}", self.hp_modem_dig_icg_apb_en().bits()),
-            )
+            .field("hp_modem_dig_icg_apb_en", &self.hp_modem_dig_icg_apb_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_ICG_HP_APB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_modem_icg_hp_func.rs b/esp32h2/src/pmu/hp_modem_icg_hp_func.rs
index 38fafe4e08..5a6a31133d 100644
--- a/esp32h2/src/pmu/hp_modem_icg_hp_func.rs
+++ b/esp32h2/src/pmu/hp_modem_icg_hp_func.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_MODEM_ICG_HP_FUNC")
-            .field(
-                "hp_modem_dig_icg_func_en",
-                &format_args!("{}", self.hp_modem_dig_icg_func_en().bits()),
-            )
+            .field("hp_modem_dig_icg_func_en", &self.hp_modem_dig_icg_func_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_ICG_HP_FUNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_modem_icg_modem.rs b/esp32h2/src/pmu/hp_modem_icg_modem.rs
index 1ef4824b3f..95a50ae840 100644
--- a/esp32h2/src/pmu/hp_modem_icg_modem.rs
+++ b/esp32h2/src/pmu/hp_modem_icg_modem.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_MODEM_ICG_MODEM")
             .field(
                 "hp_modem_dig_icg_modem_code",
-                &format_args!("{}", self.hp_modem_dig_icg_modem_code().bits()),
+                &self.hp_modem_dig_icg_modem_code(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_ICG_MODEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 30:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_modem_sysclk.rs b/esp32h2/src/pmu/hp_modem_sysclk.rs
index a906195c4e..b7a54e1344 100644
--- a/esp32h2/src/pmu/hp_modem_sysclk.rs
+++ b/esp32h2/src/pmu/hp_modem_sysclk.rs
@@ -55,33 +55,18 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_MODEM_SYSCLK")
             .field(
                 "hp_modem_dig_sys_clk_no_div",
-                &format_args!("{}", self.hp_modem_dig_sys_clk_no_div().bit()),
+                &self.hp_modem_dig_sys_clk_no_div(),
             )
             .field(
                 "hp_modem_icg_sys_clock_en",
-                &format_args!("{}", self.hp_modem_icg_sys_clock_en().bit()),
-            )
-            .field(
-                "hp_modem_sys_clk_slp_sel",
-                &format_args!("{}", self.hp_modem_sys_clk_slp_sel().bit()),
-            )
-            .field(
-                "hp_modem_icg_slp_sel",
-                &format_args!("{}", self.hp_modem_icg_slp_sel().bit()),
-            )
-            .field(
-                "hp_modem_dig_sys_clk_sel",
-                &format_args!("{}", self.hp_modem_dig_sys_clk_sel().bits()),
+                &self.hp_modem_icg_sys_clock_en(),
             )
+            .field("hp_modem_sys_clk_slp_sel", &self.hp_modem_sys_clk_slp_sel())
+            .field("hp_modem_icg_slp_sel", &self.hp_modem_icg_slp_sel())
+            .field("hp_modem_dig_sys_clk_sel", &self.hp_modem_dig_sys_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_SYSCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_modem_xtal.rs b/esp32h2/src/pmu/hp_modem_xtal.rs
index 5d5d17c9d1..86aec785c3 100644
--- a/esp32h2/src/pmu/hp_modem_xtal.rs
+++ b/esp32h2/src/pmu/hp_modem_xtal.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_MODEM_XTAL")
-            .field(
-                "hp_modem_xpd_xtal",
-                &format_args!("{}", self.hp_modem_xpd_xtal().bit()),
-            )
+            .field("hp_modem_xpd_xtal", &self.hp_modem_xpd_xtal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_XTAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_regulator_cfg.rs b/esp32h2/src/pmu/hp_regulator_cfg.rs
index ad2910e8f2..d97579a523 100644
--- a/esp32h2/src/pmu/hp_regulator_cfg.rs
+++ b/esp32h2/src/pmu/hp_regulator_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_REGULATOR_CFG")
-            .field(
-                "dig_regulator_en_cal",
-                &format_args!("{}", self.dig_regulator_en_cal().bit()),
-            )
+            .field("dig_regulator_en_cal", &self.dig_regulator_en_cal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_REGULATOR_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_backup.rs b/esp32h2/src/pmu/hp_sleep_backup.rs
index 7f86bbd960..aa2cc24f40 100644
--- a/esp32h2/src/pmu/hp_sleep_backup.rs
+++ b/esp32h2/src/pmu/hp_sleep_backup.rs
@@ -109,57 +109,45 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_BACKUP")
             .field(
                 "hp_modem2sleep_backup_modem_clk_code",
-                &format_args!("{}", self.hp_modem2sleep_backup_modem_clk_code().bits()),
+                &self.hp_modem2sleep_backup_modem_clk_code(),
             )
             .field(
                 "hp_active2sleep_backup_modem_clk_code",
-                &format_args!("{}", self.hp_active2sleep_backup_modem_clk_code().bits()),
-            )
-            .field(
-                "hp_sleep_retention_mode",
-                &format_args!("{}", self.hp_sleep_retention_mode().bit()),
+                &self.hp_active2sleep_backup_modem_clk_code(),
             )
+            .field("hp_sleep_retention_mode", &self.hp_sleep_retention_mode())
             .field(
                 "hp_modem2sleep_retention_en",
-                &format_args!("{}", self.hp_modem2sleep_retention_en().bit()),
+                &self.hp_modem2sleep_retention_en(),
             )
             .field(
                 "hp_active2sleep_retention_en",
-                &format_args!("{}", self.hp_active2sleep_retention_en().bit()),
+                &self.hp_active2sleep_retention_en(),
             )
             .field(
                 "hp_modem2sleep_backup_clk_sel",
-                &format_args!("{}", self.hp_modem2sleep_backup_clk_sel().bits()),
+                &self.hp_modem2sleep_backup_clk_sel(),
             )
             .field(
                 "hp_active2sleep_backup_clk_sel",
-                &format_args!("{}", self.hp_active2sleep_backup_clk_sel().bits()),
+                &self.hp_active2sleep_backup_clk_sel(),
             )
             .field(
                 "hp_modem2sleep_backup_mode",
-                &format_args!("{}", self.hp_modem2sleep_backup_mode().bits()),
+                &self.hp_modem2sleep_backup_mode(),
             )
             .field(
                 "hp_active2sleep_backup_mode",
-                &format_args!("{}", self.hp_active2sleep_backup_mode().bits()),
-            )
-            .field(
-                "hp_modem2sleep_backup_en",
-                &format_args!("{}", self.hp_modem2sleep_backup_en().bit()),
+                &self.hp_active2sleep_backup_mode(),
             )
+            .field("hp_modem2sleep_backup_en", &self.hp_modem2sleep_backup_en())
             .field(
                 "hp_active2sleep_backup_en",
-                &format_args!("{}", self.hp_active2sleep_backup_en().bit()),
+                &self.hp_active2sleep_backup_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_BACKUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 6:7 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_backup_clk.rs b/esp32h2/src/pmu/hp_sleep_backup_clk.rs
index 614a958d65..e0fccffe56 100644
--- a/esp32h2/src/pmu/hp_sleep_backup_clk.rs
+++ b/esp32h2/src/pmu/hp_sleep_backup_clk.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_BACKUP_CLK")
             .field(
                 "hp_sleep_backup_icg_func_en",
-                &format_args!("{}", self.hp_sleep_backup_icg_func_en().bits()),
+                &self.hp_sleep_backup_icg_func_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_BACKUP_CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_bias.rs b/esp32h2/src/pmu/hp_sleep_bias.rs
index 95f6aebf7b..141db2540b 100644
--- a/esp32h2/src/pmu/hp_sleep_bias.rs
+++ b/esp32h2/src/pmu/hp_sleep_bias.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_BIAS")
-            .field(
-                "hp_sleep_xpd_trx",
-                &format_args!("{}", self.hp_sleep_xpd_trx().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_bias",
-                &format_args!("{}", self.hp_sleep_xpd_bias().bit()),
-            )
-            .field(
-                "hp_sleep_pd_cur",
-                &format_args!("{}", self.hp_sleep_pd_cur().bit()),
-            )
-            .field("sleep", &format_args!("{}", self.sleep().bit()))
+            .field("hp_sleep_xpd_trx", &self.hp_sleep_xpd_trx())
+            .field("hp_sleep_xpd_bias", &self.hp_sleep_xpd_bias())
+            .field("hp_sleep_pd_cur", &self.hp_sleep_pd_cur())
+            .field("sleep", &self.sleep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_BIAS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_dig_power.rs b/esp32h2/src/pmu/hp_sleep_dig_power.rs
index a63e50a28b..9949a71150 100644
--- a/esp32h2/src/pmu/hp_sleep_dig_power.rs
+++ b/esp32h2/src/pmu/hp_sleep_dig_power.rs
@@ -71,43 +71,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_DIG_POWER")
-            .field(
-                "hp_sleep_vdd_spi_pd_en",
-                &format_args!("{}", self.hp_sleep_vdd_spi_pd_en().bit()),
-            )
-            .field(
-                "hp_sleep_hp_mem_dslp",
-                &format_args!("{}", self.hp_sleep_hp_mem_dslp().bit()),
-            )
-            .field(
-                "hp_sleep_pd_hp_mem_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_hp_mem_pd_en().bits()),
-            )
+            .field("hp_sleep_vdd_spi_pd_en", &self.hp_sleep_vdd_spi_pd_en())
+            .field("hp_sleep_hp_mem_dslp", &self.hp_sleep_hp_mem_dslp())
+            .field("hp_sleep_pd_hp_mem_pd_en", &self.hp_sleep_pd_hp_mem_pd_en())
             .field(
                 "hp_sleep_pd_hp_wifi_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_hp_wifi_pd_en().bit()),
-            )
-            .field(
-                "hp_sleep_pd_hp_cpu_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_hp_cpu_pd_en().bit()),
-            )
-            .field(
-                "hp_sleep_pd_hp_aon_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_hp_aon_pd_en().bit()),
-            )
-            .field(
-                "hp_sleep_pd_top_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_top_pd_en().bit()),
+                &self.hp_sleep_pd_hp_wifi_pd_en(),
             )
+            .field("hp_sleep_pd_hp_cpu_pd_en", &self.hp_sleep_pd_hp_cpu_pd_en())
+            .field("hp_sleep_pd_hp_aon_pd_en", &self.hp_sleep_pd_hp_aon_pd_en())
+            .field("hp_sleep_pd_top_pd_en", &self.hp_sleep_pd_top_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_DIG_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_hp_ck_power.rs b/esp32h2/src/pmu/hp_sleep_hp_ck_power.rs
index cc7e3b4592..bdf67ed4c6 100644
--- a/esp32h2/src/pmu/hp_sleep_hp_ck_power.rs
+++ b/esp32h2/src/pmu/hp_sleep_hp_ck_power.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_HP_CK_POWER")
-            .field(
-                "hp_sleep_i2c_iso_en",
-                &format_args!("{}", self.hp_sleep_i2c_iso_en().bit()),
-            )
-            .field(
-                "hp_sleep_i2c_retention",
-                &format_args!("{}", self.hp_sleep_i2c_retention().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_bb_i2c",
-                &format_args!("{}", self.hp_sleep_xpd_bb_i2c().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_bbpll_i2c",
-                &format_args!("{}", self.hp_sleep_xpd_bbpll_i2c().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_bbpll",
-                &format_args!("{}", self.hp_sleep_xpd_bbpll().bit()),
-            )
+            .field("hp_sleep_i2c_iso_en", &self.hp_sleep_i2c_iso_en())
+            .field("hp_sleep_i2c_retention", &self.hp_sleep_i2c_retention())
+            .field("hp_sleep_xpd_bb_i2c", &self.hp_sleep_xpd_bb_i2c())
+            .field("hp_sleep_xpd_bbpll_i2c", &self.hp_sleep_xpd_bbpll_i2c())
+            .field("hp_sleep_xpd_bbpll", &self.hp_sleep_xpd_bbpll())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_HP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_hp_regulator0.rs b/esp32h2/src/pmu/hp_sleep_hp_regulator0.rs
index 2fad655627..0f5f779f3f 100644
--- a/esp32h2/src/pmu/hp_sleep_hp_regulator0.rs
+++ b/esp32h2/src/pmu/hp_sleep_hp_regulator0.rs
@@ -73,41 +73,35 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_HP_REGULATOR0")
             .field(
                 "hp_sleep_hp_power_det_bypass",
-                &format_args!("{}", self.hp_sleep_hp_power_det_bypass().bit()),
+                &self.hp_sleep_hp_power_det_bypass(),
             )
             .field(
                 "hp_sleep_hp_regulator_slp_mem_xpd",
-                &format_args!("{}", self.hp_sleep_hp_regulator_slp_mem_xpd().bit()),
+                &self.hp_sleep_hp_regulator_slp_mem_xpd(),
             )
             .field(
                 "hp_sleep_hp_regulator_slp_logic_xpd",
-                &format_args!("{}", self.hp_sleep_hp_regulator_slp_logic_xpd().bit()),
+                &self.hp_sleep_hp_regulator_slp_logic_xpd(),
             )
             .field(
                 "hp_sleep_hp_regulator_xpd",
-                &format_args!("{}", self.hp_sleep_hp_regulator_xpd().bit()),
+                &self.hp_sleep_hp_regulator_xpd(),
             )
             .field(
                 "hp_sleep_hp_regulator_slp_mem_dbias",
-                &format_args!("{}", self.hp_sleep_hp_regulator_slp_mem_dbias().bits()),
+                &self.hp_sleep_hp_regulator_slp_mem_dbias(),
             )
             .field(
                 "hp_sleep_hp_regulator_slp_logic_dbias",
-                &format_args!("{}", self.hp_sleep_hp_regulator_slp_logic_dbias().bits()),
+                &self.hp_sleep_hp_regulator_slp_logic_dbias(),
             )
             .field(
                 "hp_sleep_hp_regulator_dbias",
-                &format_args!("{}", self.hp_sleep_hp_regulator_dbias().bits()),
+                &self.hp_sleep_hp_regulator_dbias(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_HP_REGULATOR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_hp_regulator1.rs b/esp32h2/src/pmu/hp_sleep_hp_regulator1.rs
index f352c326a5..2cd4fc5a1f 100644
--- a/esp32h2/src/pmu/hp_sleep_hp_regulator1.rs
+++ b/esp32h2/src/pmu/hp_sleep_hp_regulator1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_HP_REGULATOR1")
             .field(
                 "hp_sleep_hp_regulator_drv_b",
-                &format_args!("{}", self.hp_sleep_hp_regulator_drv_b().bits()),
+                &self.hp_sleep_hp_regulator_drv_b(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_HP_REGULATOR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_hp_sys_cntl.rs b/esp32h2/src/pmu/hp_sleep_hp_sys_cntl.rs
index 9656f07128..af773a1876 100644
--- a/esp32h2/src/pmu/hp_sleep_hp_sys_cntl.rs
+++ b/esp32h2/src/pmu/hp_sleep_hp_sys_cntl.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_HP_SYS_CNTL")
-            .field(
-                "hp_sleep_uart_wakeup_en",
-                &format_args!("{}", self.hp_sleep_uart_wakeup_en().bit()),
-            )
-            .field(
-                "hp_sleep_lp_pad_hold_all",
-                &format_args!("{}", self.hp_sleep_lp_pad_hold_all().bit()),
-            )
-            .field(
-                "hp_sleep_hp_pad_hold_all",
-                &format_args!("{}", self.hp_sleep_hp_pad_hold_all().bit()),
-            )
-            .field(
-                "hp_sleep_dig_pad_slp_sel",
-                &format_args!("{}", self.hp_sleep_dig_pad_slp_sel().bit()),
-            )
-            .field(
-                "hp_sleep_dig_pause_wdt",
-                &format_args!("{}", self.hp_sleep_dig_pause_wdt().bit()),
-            )
-            .field(
-                "hp_sleep_dig_cpu_stall",
-                &format_args!("{}", self.hp_sleep_dig_cpu_stall().bit()),
-            )
+            .field("hp_sleep_uart_wakeup_en", &self.hp_sleep_uart_wakeup_en())
+            .field("hp_sleep_lp_pad_hold_all", &self.hp_sleep_lp_pad_hold_all())
+            .field("hp_sleep_hp_pad_hold_all", &self.hp_sleep_hp_pad_hold_all())
+            .field("hp_sleep_dig_pad_slp_sel", &self.hp_sleep_dig_pad_slp_sel())
+            .field("hp_sleep_dig_pause_wdt", &self.hp_sleep_dig_pause_wdt())
+            .field("hp_sleep_dig_cpu_stall", &self.hp_sleep_dig_cpu_stall())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_HP_SYS_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_icg_hp_apb.rs b/esp32h2/src/pmu/hp_sleep_icg_hp_apb.rs
index f88b25a3ef..528420839b 100644
--- a/esp32h2/src/pmu/hp_sleep_icg_hp_apb.rs
+++ b/esp32h2/src/pmu/hp_sleep_icg_hp_apb.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_ICG_HP_APB")
-            .field(
-                "hp_sleep_dig_icg_apb_en",
-                &format_args!("{}", self.hp_sleep_dig_icg_apb_en().bits()),
-            )
+            .field("hp_sleep_dig_icg_apb_en", &self.hp_sleep_dig_icg_apb_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_ICG_HP_APB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_icg_hp_func.rs b/esp32h2/src/pmu/hp_sleep_icg_hp_func.rs
index 7c25582392..a78d413e13 100644
--- a/esp32h2/src/pmu/hp_sleep_icg_hp_func.rs
+++ b/esp32h2/src/pmu/hp_sleep_icg_hp_func.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_ICG_HP_FUNC")
-            .field(
-                "hp_sleep_dig_icg_func_en",
-                &format_args!("{}", self.hp_sleep_dig_icg_func_en().bits()),
-            )
+            .field("hp_sleep_dig_icg_func_en", &self.hp_sleep_dig_icg_func_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_ICG_HP_FUNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_icg_modem.rs b/esp32h2/src/pmu/hp_sleep_icg_modem.rs
index 28d2bd644e..43fc5f1da0 100644
--- a/esp32h2/src/pmu/hp_sleep_icg_modem.rs
+++ b/esp32h2/src/pmu/hp_sleep_icg_modem.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_ICG_MODEM")
             .field(
                 "hp_sleep_dig_icg_modem_code",
-                &format_args!("{}", self.hp_sleep_dig_icg_modem_code().bits()),
+                &self.hp_sleep_dig_icg_modem_code(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_ICG_MODEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 30:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_lp_ck_power.rs b/esp32h2/src/pmu/hp_sleep_lp_ck_power.rs
index edf7b9db57..cccbc909c2 100644
--- a/esp32h2/src/pmu/hp_sleep_lp_ck_power.rs
+++ b/esp32h2/src/pmu/hp_sleep_lp_ck_power.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_LP_CK_POWER")
-            .field(
-                "hp_sleep_xpd_lppll",
-                &format_args!("{}", self.hp_sleep_xpd_lppll().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_xtal32k",
-                &format_args!("{}", self.hp_sleep_xpd_xtal32k().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_rc32k",
-                &format_args!("{}", self.hp_sleep_xpd_rc32k().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_fosc_clk",
-                &format_args!("{}", self.hp_sleep_xpd_fosc_clk().bit()),
-            )
-            .field(
-                "hp_sleep_pd_osc_clk",
-                &format_args!("{}", self.hp_sleep_pd_osc_clk().bit()),
-            )
+            .field("hp_sleep_xpd_lppll", &self.hp_sleep_xpd_lppll())
+            .field("hp_sleep_xpd_xtal32k", &self.hp_sleep_xpd_xtal32k())
+            .field("hp_sleep_xpd_rc32k", &self.hp_sleep_xpd_rc32k())
+            .field("hp_sleep_xpd_fosc_clk", &self.hp_sleep_xpd_fosc_clk())
+            .field("hp_sleep_pd_osc_clk", &self.hp_sleep_pd_osc_clk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_LP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_lp_dig_power.rs b/esp32h2/src/pmu/hp_sleep_lp_dig_power.rs
index 8a8b3544d6..a19be2cfde 100644
--- a/esp32h2/src/pmu/hp_sleep_lp_dig_power.rs
+++ b/esp32h2/src/pmu/hp_sleep_lp_dig_power.rs
@@ -44,31 +44,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_LP_DIG_POWER")
-            .field(
-                "hp_sleep_bod_source_sel",
-                &format_args!("{}", self.hp_sleep_bod_source_sel().bit()),
-            )
-            .field(
-                "hp_sleep_vddbat_mode",
-                &format_args!("{}", self.hp_sleep_vddbat_mode().bits()),
-            )
-            .field(
-                "hp_sleep_lp_mem_dslp",
-                &format_args!("{}", self.hp_sleep_lp_mem_dslp().bit()),
-            )
+            .field("hp_sleep_bod_source_sel", &self.hp_sleep_bod_source_sel())
+            .field("hp_sleep_vddbat_mode", &self.hp_sleep_vddbat_mode())
+            .field("hp_sleep_lp_mem_dslp", &self.hp_sleep_lp_mem_dslp())
             .field(
                 "hp_sleep_pd_lp_peri_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_lp_peri_pd_en().bit()),
+                &self.hp_sleep_pd_lp_peri_pd_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_LP_DIG_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_lp_regulator0.rs b/esp32h2/src/pmu/hp_sleep_lp_regulator0.rs
index a9ea48f63f..cc8c543e5d 100644
--- a/esp32h2/src/pmu/hp_sleep_lp_regulator0.rs
+++ b/esp32h2/src/pmu/hp_sleep_lp_regulator0.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_LP_REGULATOR0")
             .field(
                 "hp_sleep_lp_regulator_slp_xpd",
-                &format_args!("{}", self.hp_sleep_lp_regulator_slp_xpd().bit()),
+                &self.hp_sleep_lp_regulator_slp_xpd(),
             )
             .field(
                 "hp_sleep_lp_regulator_xpd",
-                &format_args!("{}", self.hp_sleep_lp_regulator_xpd().bit()),
+                &self.hp_sleep_lp_regulator_xpd(),
             )
             .field(
                 "hp_sleep_lp_regulator_slp_dbias",
-                &format_args!("{}", self.hp_sleep_lp_regulator_slp_dbias().bits()),
+                &self.hp_sleep_lp_regulator_slp_dbias(),
             )
             .field(
                 "hp_sleep_lp_regulator_dbias",
-                &format_args!("{}", self.hp_sleep_lp_regulator_dbias().bits()),
+                &self.hp_sleep_lp_regulator_dbias(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_LP_REGULATOR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_lp_regulator1.rs b/esp32h2/src/pmu/hp_sleep_lp_regulator1.rs
index 39c41cbe94..2ed52079d4 100644
--- a/esp32h2/src/pmu/hp_sleep_lp_regulator1.rs
+++ b/esp32h2/src/pmu/hp_sleep_lp_regulator1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_LP_REGULATOR1")
             .field(
                 "hp_sleep_lp_regulator_drv_b",
-                &format_args!("{}", self.hp_sleep_lp_regulator_drv_b().bits()),
+                &self.hp_sleep_lp_regulator_drv_b(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_LP_REGULATOR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 28:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_sysclk.rs b/esp32h2/src/pmu/hp_sleep_sysclk.rs
index 747f40e916..774ea4245c 100644
--- a/esp32h2/src/pmu/hp_sleep_sysclk.rs
+++ b/esp32h2/src/pmu/hp_sleep_sysclk.rs
@@ -55,33 +55,18 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_SYSCLK")
             .field(
                 "hp_sleep_dig_sys_clk_no_div",
-                &format_args!("{}", self.hp_sleep_dig_sys_clk_no_div().bit()),
+                &self.hp_sleep_dig_sys_clk_no_div(),
             )
             .field(
                 "hp_sleep_icg_sys_clock_en",
-                &format_args!("{}", self.hp_sleep_icg_sys_clock_en().bit()),
-            )
-            .field(
-                "hp_sleep_sys_clk_slp_sel",
-                &format_args!("{}", self.hp_sleep_sys_clk_slp_sel().bit()),
-            )
-            .field(
-                "hp_sleep_icg_slp_sel",
-                &format_args!("{}", self.hp_sleep_icg_slp_sel().bit()),
-            )
-            .field(
-                "hp_sleep_dig_sys_clk_sel",
-                &format_args!("{}", self.hp_sleep_dig_sys_clk_sel().bits()),
+                &self.hp_sleep_icg_sys_clock_en(),
             )
+            .field("hp_sleep_sys_clk_slp_sel", &self.hp_sleep_sys_clk_slp_sel())
+            .field("hp_sleep_icg_slp_sel", &self.hp_sleep_icg_slp_sel())
+            .field("hp_sleep_dig_sys_clk_sel", &self.hp_sleep_dig_sys_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_SYSCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/hp_sleep_xtal.rs b/esp32h2/src/pmu/hp_sleep_xtal.rs
index 6a54e1ef0a..f1e6e47a01 100644
--- a/esp32h2/src/pmu/hp_sleep_xtal.rs
+++ b/esp32h2/src/pmu/hp_sleep_xtal.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_XTAL")
-            .field(
-                "hp_sleep_xpd_xtal",
-                &format_args!("{}", self.hp_sleep_xpd_xtal().bit()),
-            )
+            .field("hp_sleep_xpd_xtal", &self.hp_sleep_xpd_xtal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_XTAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/imm_hp_ck_power.rs b/esp32h2/src/pmu/imm_hp_ck_power.rs
index 864dbe022d..89700a58a4 100644
--- a/esp32h2/src/pmu/imm_hp_ck_power.rs
+++ b/esp32h2/src/pmu/imm_hp_ck_power.rs
@@ -36,12 +36,6 @@ impl core::fmt::Debug for R {
         f.debug_struct("IMM_HP_CK_POWER").finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMM_HP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/int_ena.rs b/esp32h2/src/pmu/int_ena.rs
index 6b7e43e73c..b9ff7e126e 100644
--- a/esp32h2/src/pmu/int_ena.rs
+++ b/esp32h2/src/pmu/int_ena.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("lp_cpu_exc", &format_args!("{}", self.lp_cpu_exc().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("sw", &format_args!("{}", self.sw().bit()))
-            .field(
-                "soc_sleep_reject",
-                &format_args!("{}", self.soc_sleep_reject().bit()),
-            )
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("lp_cpu_exc", &self.lp_cpu_exc())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("sw", &self.sw())
+            .field("soc_sleep_reject", &self.soc_sleep_reject())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/int_raw.rs b/esp32h2/src/pmu/int_raw.rs
index e18ddad1b9..2889e9c973 100644
--- a/esp32h2/src/pmu/int_raw.rs
+++ b/esp32h2/src/pmu/int_raw.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("lp_cpu_exc", &format_args!("{}", self.lp_cpu_exc().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("sw", &format_args!("{}", self.sw().bit()))
-            .field(
-                "soc_sleep_reject",
-                &format_args!("{}", self.soc_sleep_reject().bit()),
-            )
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("lp_cpu_exc", &self.lp_cpu_exc())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("sw", &self.sw())
+            .field("soc_sleep_reject", &self.soc_sleep_reject())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/int_st.rs b/esp32h2/src/pmu/int_st.rs
index e041d3bf92..d3927f8a2d 100644
--- a/esp32h2/src/pmu/int_st.rs
+++ b/esp32h2/src/pmu/int_st.rs
@@ -41,23 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("lp_cpu_exc", &format_args!("{}", self.lp_cpu_exc().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("sw", &format_args!("{}", self.sw().bit()))
-            .field(
-                "soc_sleep_reject",
-                &format_args!("{}", self.soc_sleep_reject().bit()),
-            )
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("lp_cpu_exc", &self.lp_cpu_exc())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("sw", &self.sw())
+            .field("soc_sleep_reject", &self.soc_sleep_reject())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/pmu/lp_cpu_pwr0.rs b/esp32h2/src/pmu/lp_cpu_pwr0.rs
index 7147a7513f..0d670be9e5 100644
--- a/esp32h2/src/pmu/lp_cpu_pwr0.rs
+++ b/esp32h2/src/pmu/lp_cpu_pwr0.rs
@@ -85,51 +85,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CPU_PWR0")
-            .field(
-                "lp_cpu_waiti_rdy",
-                &format_args!("{}", self.lp_cpu_waiti_rdy().bit()),
-            )
-            .field(
-                "lp_cpu_stall_rdy",
-                &format_args!("{}", self.lp_cpu_stall_rdy().bit()),
-            )
-            .field(
-                "lp_cpu_force_stall",
-                &format_args!("{}", self.lp_cpu_force_stall().bit()),
-            )
-            .field(
-                "lp_cpu_slp_waiti_flag_en",
-                &format_args!("{}", self.lp_cpu_slp_waiti_flag_en().bit()),
-            )
-            .field(
-                "lp_cpu_slp_stall_flag_en",
-                &format_args!("{}", self.lp_cpu_slp_stall_flag_en().bit()),
-            )
-            .field(
-                "lp_cpu_slp_stall_wait",
-                &format_args!("{}", self.lp_cpu_slp_stall_wait().bits()),
-            )
-            .field(
-                "lp_cpu_slp_stall_en",
-                &format_args!("{}", self.lp_cpu_slp_stall_en().bit()),
-            )
-            .field(
-                "lp_cpu_slp_reset_en",
-                &format_args!("{}", self.lp_cpu_slp_reset_en().bit()),
-            )
+            .field("lp_cpu_waiti_rdy", &self.lp_cpu_waiti_rdy())
+            .field("lp_cpu_stall_rdy", &self.lp_cpu_stall_rdy())
+            .field("lp_cpu_force_stall", &self.lp_cpu_force_stall())
+            .field("lp_cpu_slp_waiti_flag_en", &self.lp_cpu_slp_waiti_flag_en())
+            .field("lp_cpu_slp_stall_flag_en", &self.lp_cpu_slp_stall_flag_en())
+            .field("lp_cpu_slp_stall_wait", &self.lp_cpu_slp_stall_wait())
+            .field("lp_cpu_slp_stall_en", &self.lp_cpu_slp_stall_en())
+            .field("lp_cpu_slp_reset_en", &self.lp_cpu_slp_reset_en())
             .field(
                 "lp_cpu_slp_bypass_intr_en",
-                &format_args!("{}", self.lp_cpu_slp_bypass_intr_en().bit()),
+                &self.lp_cpu_slp_bypass_intr_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CPU_PWR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/lp_cpu_pwr1.rs b/esp32h2/src/pmu/lp_cpu_pwr1.rs
index 9c51108972..0a98bd82dc 100644
--- a/esp32h2/src/pmu/lp_cpu_pwr1.rs
+++ b/esp32h2/src/pmu/lp_cpu_pwr1.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CPU_PWR1")
-            .field(
-                "lp_cpu_wakeup_en",
-                &format_args!("{}", self.lp_cpu_wakeup_en().bits()),
-            )
+            .field("lp_cpu_wakeup_en", &self.lp_cpu_wakeup_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CPU_PWR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/lp_int_ena.rs b/esp32h2/src/pmu/lp_int_ena.rs
index 5b122e6ab5..18a334fbb5 100644
--- a/esp32h2/src/pmu/lp_int_ena.rs
+++ b/esp32h2/src/pmu/lp_int_ena.rs
@@ -116,63 +116,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ENA")
-            .field(
-                "lp_cpu_wakeup",
-                &format_args!("{}", self.lp_cpu_wakeup().bit()),
-            )
-            .field(
-                "modem_switch_active_end",
-                &format_args!("{}", self.modem_switch_active_end().bit()),
-            )
-            .field(
-                "sleep_switch_active_end",
-                &format_args!("{}", self.sleep_switch_active_end().bit()),
-            )
-            .field(
-                "sleep_switch_modem_end",
-                &format_args!("{}", self.sleep_switch_modem_end().bit()),
-            )
-            .field(
-                "modem_switch_sleep_end",
-                &format_args!("{}", self.modem_switch_sleep_end().bit()),
-            )
-            .field(
-                "active_switch_sleep_end",
-                &format_args!("{}", self.active_switch_sleep_end().bit()),
-            )
+            .field("lp_cpu_wakeup", &self.lp_cpu_wakeup())
+            .field("modem_switch_active_end", &self.modem_switch_active_end())
+            .field("sleep_switch_active_end", &self.sleep_switch_active_end())
+            .field("sleep_switch_modem_end", &self.sleep_switch_modem_end())
+            .field("modem_switch_sleep_end", &self.modem_switch_sleep_end())
+            .field("active_switch_sleep_end", &self.active_switch_sleep_end())
             .field(
                 "modem_switch_active_start",
-                &format_args!("{}", self.modem_switch_active_start().bit()),
+                &self.modem_switch_active_start(),
             )
             .field(
                 "sleep_switch_active_start",
-                &format_args!("{}", self.sleep_switch_active_start().bit()),
-            )
-            .field(
-                "sleep_switch_modem_start",
-                &format_args!("{}", self.sleep_switch_modem_start().bit()),
-            )
-            .field(
-                "modem_switch_sleep_start",
-                &format_args!("{}", self.modem_switch_sleep_start().bit()),
+                &self.sleep_switch_active_start(),
             )
+            .field("sleep_switch_modem_start", &self.sleep_switch_modem_start())
+            .field("modem_switch_sleep_start", &self.modem_switch_sleep_start())
             .field(
                 "active_switch_sleep_start",
-                &format_args!("{}", self.active_switch_sleep_start().bit()),
-            )
-            .field(
-                "hp_sw_trigger",
-                &format_args!("{}", self.hp_sw_trigger().bit()),
+                &self.active_switch_sleep_start(),
             )
+            .field("hp_sw_trigger", &self.hp_sw_trigger())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/lp_int_raw.rs b/esp32h2/src/pmu/lp_int_raw.rs
index 69bebde980..b5a4ac446b 100644
--- a/esp32h2/src/pmu/lp_int_raw.rs
+++ b/esp32h2/src/pmu/lp_int_raw.rs
@@ -116,63 +116,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_RAW")
-            .field(
-                "lp_cpu_wakeup",
-                &format_args!("{}", self.lp_cpu_wakeup().bit()),
-            )
-            .field(
-                "modem_switch_active_end",
-                &format_args!("{}", self.modem_switch_active_end().bit()),
-            )
-            .field(
-                "sleep_switch_active_end",
-                &format_args!("{}", self.sleep_switch_active_end().bit()),
-            )
-            .field(
-                "sleep_switch_modem_end",
-                &format_args!("{}", self.sleep_switch_modem_end().bit()),
-            )
-            .field(
-                "modem_switch_sleep_end",
-                &format_args!("{}", self.modem_switch_sleep_end().bit()),
-            )
-            .field(
-                "active_switch_sleep_end",
-                &format_args!("{}", self.active_switch_sleep_end().bit()),
-            )
+            .field("lp_cpu_wakeup", &self.lp_cpu_wakeup())
+            .field("modem_switch_active_end", &self.modem_switch_active_end())
+            .field("sleep_switch_active_end", &self.sleep_switch_active_end())
+            .field("sleep_switch_modem_end", &self.sleep_switch_modem_end())
+            .field("modem_switch_sleep_end", &self.modem_switch_sleep_end())
+            .field("active_switch_sleep_end", &self.active_switch_sleep_end())
             .field(
                 "modem_switch_active_start",
-                &format_args!("{}", self.modem_switch_active_start().bit()),
+                &self.modem_switch_active_start(),
             )
             .field(
                 "sleep_switch_active_start",
-                &format_args!("{}", self.sleep_switch_active_start().bit()),
-            )
-            .field(
-                "sleep_switch_modem_start",
-                &format_args!("{}", self.sleep_switch_modem_start().bit()),
-            )
-            .field(
-                "modem_switch_sleep_start",
-                &format_args!("{}", self.modem_switch_sleep_start().bit()),
+                &self.sleep_switch_active_start(),
             )
+            .field("sleep_switch_modem_start", &self.sleep_switch_modem_start())
+            .field("modem_switch_sleep_start", &self.modem_switch_sleep_start())
             .field(
                 "active_switch_sleep_start",
-                &format_args!("{}", self.active_switch_sleep_start().bit()),
-            )
-            .field(
-                "hp_sw_trigger",
-                &format_args!("{}", self.hp_sw_trigger().bit()),
+                &self.active_switch_sleep_start(),
             )
+            .field("hp_sw_trigger", &self.hp_sw_trigger())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/lp_int_st.rs b/esp32h2/src/pmu/lp_int_st.rs
index f0248a2958..4d5b520ec0 100644
--- a/esp32h2/src/pmu/lp_int_st.rs
+++ b/esp32h2/src/pmu/lp_int_st.rs
@@ -90,63 +90,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ST")
-            .field(
-                "lp_cpu_wakeup",
-                &format_args!("{}", self.lp_cpu_wakeup().bit()),
-            )
-            .field(
-                "modem_switch_active_end",
-                &format_args!("{}", self.modem_switch_active_end().bit()),
-            )
-            .field(
-                "sleep_switch_active_end",
-                &format_args!("{}", self.sleep_switch_active_end().bit()),
-            )
-            .field(
-                "sleep_switch_modem_end",
-                &format_args!("{}", self.sleep_switch_modem_end().bit()),
-            )
-            .field(
-                "modem_switch_sleep_end",
-                &format_args!("{}", self.modem_switch_sleep_end().bit()),
-            )
-            .field(
-                "active_switch_sleep_end",
-                &format_args!("{}", self.active_switch_sleep_end().bit()),
-            )
+            .field("lp_cpu_wakeup", &self.lp_cpu_wakeup())
+            .field("modem_switch_active_end", &self.modem_switch_active_end())
+            .field("sleep_switch_active_end", &self.sleep_switch_active_end())
+            .field("sleep_switch_modem_end", &self.sleep_switch_modem_end())
+            .field("modem_switch_sleep_end", &self.modem_switch_sleep_end())
+            .field("active_switch_sleep_end", &self.active_switch_sleep_end())
             .field(
                 "modem_switch_active_start",
-                &format_args!("{}", self.modem_switch_active_start().bit()),
+                &self.modem_switch_active_start(),
             )
             .field(
                 "sleep_switch_active_start",
-                &format_args!("{}", self.sleep_switch_active_start().bit()),
-            )
-            .field(
-                "sleep_switch_modem_start",
-                &format_args!("{}", self.sleep_switch_modem_start().bit()),
-            )
-            .field(
-                "modem_switch_sleep_start",
-                &format_args!("{}", self.modem_switch_sleep_start().bit()),
+                &self.sleep_switch_active_start(),
             )
+            .field("sleep_switch_modem_start", &self.sleep_switch_modem_start())
+            .field("modem_switch_sleep_start", &self.modem_switch_sleep_start())
             .field(
                 "active_switch_sleep_start",
-                &format_args!("{}", self.active_switch_sleep_start().bit()),
-            )
-            .field(
-                "hp_sw_trigger",
-                &format_args!("{}", self.hp_sw_trigger().bit()),
+                &self.active_switch_sleep_start(),
             )
+            .field("hp_sw_trigger", &self.hp_sw_trigger())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_INT_ST_SPEC;
 impl crate::RegisterSpec for LP_INT_ST_SPEC {
diff --git a/esp32h2/src/pmu/lp_sleep_bias.rs b/esp32h2/src/pmu/lp_sleep_bias.rs
index 0a858104b9..81e7f6f02a 100644
--- a/esp32h2/src/pmu/lp_sleep_bias.rs
+++ b/esp32h2/src/pmu/lp_sleep_bias.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SLEEP_BIAS")
-            .field(
-                "lp_sleep_xpd_bias",
-                &format_args!("{}", self.lp_sleep_xpd_bias().bit()),
-            )
-            .field(
-                "lp_sleep_pd_cur",
-                &format_args!("{}", self.lp_sleep_pd_cur().bit()),
-            )
-            .field("sleep", &format_args!("{}", self.sleep().bit()))
+            .field("lp_sleep_xpd_bias", &self.lp_sleep_xpd_bias())
+            .field("lp_sleep_pd_cur", &self.lp_sleep_pd_cur())
+            .field("sleep", &self.sleep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_BIAS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/lp_sleep_lp_ck_power.rs b/esp32h2/src/pmu/lp_sleep_lp_ck_power.rs
index f91ac6d85b..f398b2de77 100644
--- a/esp32h2/src/pmu/lp_sleep_lp_ck_power.rs
+++ b/esp32h2/src/pmu/lp_sleep_lp_ck_power.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SLEEP_LP_CK_POWER")
-            .field(
-                "lp_sleep_xpd_lppll",
-                &format_args!("{}", self.lp_sleep_xpd_lppll().bit()),
-            )
-            .field(
-                "lp_sleep_xpd_xtal32k",
-                &format_args!("{}", self.lp_sleep_xpd_xtal32k().bit()),
-            )
-            .field(
-                "lp_sleep_xpd_rc32k",
-                &format_args!("{}", self.lp_sleep_xpd_rc32k().bit()),
-            )
-            .field(
-                "lp_sleep_xpd_fosc_clk",
-                &format_args!("{}", self.lp_sleep_xpd_fosc_clk().bit()),
-            )
-            .field(
-                "lp_sleep_pd_osc_clk",
-                &format_args!("{}", self.lp_sleep_pd_osc_clk().bit()),
-            )
+            .field("lp_sleep_xpd_lppll", &self.lp_sleep_xpd_lppll())
+            .field("lp_sleep_xpd_xtal32k", &self.lp_sleep_xpd_xtal32k())
+            .field("lp_sleep_xpd_rc32k", &self.lp_sleep_xpd_rc32k())
+            .field("lp_sleep_xpd_fosc_clk", &self.lp_sleep_xpd_fosc_clk())
+            .field("lp_sleep_pd_osc_clk", &self.lp_sleep_pd_osc_clk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_LP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/lp_sleep_lp_dig_power.rs b/esp32h2/src/pmu/lp_sleep_lp_dig_power.rs
index 0248417a46..a7475d254c 100644
--- a/esp32h2/src/pmu/lp_sleep_lp_dig_power.rs
+++ b/esp32h2/src/pmu/lp_sleep_lp_dig_power.rs
@@ -44,31 +44,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SLEEP_LP_DIG_POWER")
-            .field(
-                "lp_sleep_bod_source_sel",
-                &format_args!("{}", self.lp_sleep_bod_source_sel().bit()),
-            )
-            .field(
-                "lp_sleep_vddbat_mode",
-                &format_args!("{}", self.lp_sleep_vddbat_mode().bits()),
-            )
-            .field(
-                "lp_sleep_lp_mem_dslp",
-                &format_args!("{}", self.lp_sleep_lp_mem_dslp().bit()),
-            )
+            .field("lp_sleep_bod_source_sel", &self.lp_sleep_bod_source_sel())
+            .field("lp_sleep_vddbat_mode", &self.lp_sleep_vddbat_mode())
+            .field("lp_sleep_lp_mem_dslp", &self.lp_sleep_lp_mem_dslp())
             .field(
                 "lp_sleep_pd_lp_peri_pd_en",
-                &format_args!("{}", self.lp_sleep_pd_lp_peri_pd_en().bit()),
+                &self.lp_sleep_pd_lp_peri_pd_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_LP_DIG_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/lp_sleep_lp_regulator0.rs b/esp32h2/src/pmu/lp_sleep_lp_regulator0.rs
index d687a6cf8e..5cbfaac3f7 100644
--- a/esp32h2/src/pmu/lp_sleep_lp_regulator0.rs
+++ b/esp32h2/src/pmu/lp_sleep_lp_regulator0.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_SLEEP_LP_REGULATOR0")
             .field(
                 "lp_sleep_lp_regulator_slp_xpd",
-                &format_args!("{}", self.lp_sleep_lp_regulator_slp_xpd().bit()),
+                &self.lp_sleep_lp_regulator_slp_xpd(),
             )
             .field(
                 "lp_sleep_lp_regulator_xpd",
-                &format_args!("{}", self.lp_sleep_lp_regulator_xpd().bit()),
+                &self.lp_sleep_lp_regulator_xpd(),
             )
             .field(
                 "lp_sleep_lp_regulator_slp_dbias",
-                &format_args!("{}", self.lp_sleep_lp_regulator_slp_dbias().bits()),
+                &self.lp_sleep_lp_regulator_slp_dbias(),
             )
             .field(
                 "lp_sleep_lp_regulator_dbias",
-                &format_args!("{}", self.lp_sleep_lp_regulator_dbias().bits()),
+                &self.lp_sleep_lp_regulator_dbias(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_LP_REGULATOR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/lp_sleep_lp_regulator1.rs b/esp32h2/src/pmu/lp_sleep_lp_regulator1.rs
index 3e0fde22f0..29f95fd5f3 100644
--- a/esp32h2/src/pmu/lp_sleep_lp_regulator1.rs
+++ b/esp32h2/src/pmu/lp_sleep_lp_regulator1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_SLEEP_LP_REGULATOR1")
             .field(
                 "lp_sleep_lp_regulator_drv_b",
-                &format_args!("{}", self.lp_sleep_lp_regulator_drv_b().bits()),
+                &self.lp_sleep_lp_regulator_drv_b(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_LP_REGULATOR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 28:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/lp_sleep_xtal.rs b/esp32h2/src/pmu/lp_sleep_xtal.rs
index bae4466d7d..cc7e2ac036 100644
--- a/esp32h2/src/pmu/lp_sleep_xtal.rs
+++ b/esp32h2/src/pmu/lp_sleep_xtal.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SLEEP_XTAL")
-            .field(
-                "lp_sleep_xpd_xtal",
-                &format_args!("{}", self.lp_sleep_xpd_xtal().bit()),
-            )
+            .field("lp_sleep_xpd_xtal", &self.lp_sleep_xpd_xtal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_XTAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/main_state.rs b/esp32h2/src/pmu/main_state.rs
index 35b059b8ee..f71881eaf6 100644
--- a/esp32h2/src/pmu/main_state.rs
+++ b/esp32h2/src/pmu/main_state.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_STATE")
-            .field(
-                "main_last_st_state",
-                &format_args!("{}", self.main_last_st_state().bits()),
-            )
-            .field(
-                "main_tar_st_state",
-                &format_args!("{}", self.main_tar_st_state().bits()),
-            )
-            .field(
-                "main_cur_st_state",
-                &format_args!("{}", self.main_cur_st_state().bits()),
-            )
+            .field("main_last_st_state", &self.main_last_st_state())
+            .field("main_tar_st_state", &self.main_tar_st_state())
+            .field("main_cur_st_state", &self.main_cur_st_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_STATE_SPEC;
 impl crate::RegisterSpec for MAIN_STATE_SPEC {
diff --git a/esp32h2/src/pmu/por_status.rs b/esp32h2/src/pmu/por_status.rs
index eb68c0356d..1625236680 100644
--- a/esp32h2/src/pmu/por_status.rs
+++ b/esp32h2/src/pmu/por_status.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POR_STATUS")
-            .field("por_done", &format_args!("{}", self.por_done().bit()))
+            .field("por_done", &self.por_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POR_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`por_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct POR_STATUS_SPEC;
 impl crate::RegisterSpec for POR_STATUS_SPEC {
diff --git a/esp32h2/src/pmu/power_ck_wait_cntl.rs b/esp32h2/src/pmu/power_ck_wait_cntl.rs
index 18c01ff3d4..0b335ec4d2 100644
--- a/esp32h2/src/pmu/power_ck_wait_cntl.rs
+++ b/esp32h2/src/pmu/power_ck_wait_cntl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_CK_WAIT_CNTL")
-            .field(
-                "wait_xtl_stable",
-                &format_args!("{}", self.wait_xtl_stable().bits()),
-            )
-            .field(
-                "wait_pll_stable",
-                &format_args!("{}", self.wait_pll_stable().bits()),
-            )
+            .field("wait_xtl_stable", &self.wait_xtl_stable())
+            .field("wait_pll_stable", &self.wait_pll_stable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_CK_WAIT_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/power_hp_pad.rs b/esp32h2/src/pmu/power_hp_pad.rs
index c28d331333..b339bbef5d 100644
--- a/esp32h2/src/pmu/power_hp_pad.rs
+++ b/esp32h2/src/pmu/power_hp_pad.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_HP_PAD")
-            .field(
-                "force_hp_pad_no_iso_all",
-                &format_args!("{}", self.force_hp_pad_no_iso_all().bit()),
-            )
-            .field(
-                "force_hp_pad_iso_all",
-                &format_args!("{}", self.force_hp_pad_iso_all().bit()),
-            )
+            .field("force_hp_pad_no_iso_all", &self.force_hp_pad_no_iso_all())
+            .field("force_hp_pad_iso_all", &self.force_hp_pad_iso_all())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_HP_PAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/power_pd_hpaon_cntl.rs b/esp32h2/src/pmu/power_pd_hpaon_cntl.rs
index a4ac0554a9..bb42f2229c 100644
--- a/esp32h2/src/pmu/power_pd_hpaon_cntl.rs
+++ b/esp32h2/src/pmu/power_pd_hpaon_cntl.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_HPAON_CNTL")
-            .field(
-                "force_hp_aon_reset",
-                &format_args!("{}", self.force_hp_aon_reset().bit()),
-            )
-            .field(
-                "force_hp_aon_iso",
-                &format_args!("{}", self.force_hp_aon_iso().bit()),
-            )
-            .field(
-                "force_hp_aon_pu",
-                &format_args!("{}", self.force_hp_aon_pu().bit()),
-            )
-            .field(
-                "force_hp_aon_no_reset",
-                &format_args!("{}", self.force_hp_aon_no_reset().bit()),
-            )
-            .field(
-                "force_hp_aon_no_iso",
-                &format_args!("{}", self.force_hp_aon_no_iso().bit()),
-            )
-            .field(
-                "force_hp_aon_pd",
-                &format_args!("{}", self.force_hp_aon_pd().bit()),
-            )
-            .field(
-                "pd_hp_aon_mask",
-                &format_args!("{}", self.pd_hp_aon_mask().bits()),
-            )
-            .field(
-                "pd_hp_aon_pd_mask",
-                &format_args!("{}", self.pd_hp_aon_pd_mask().bits()),
-            )
+            .field("force_hp_aon_reset", &self.force_hp_aon_reset())
+            .field("force_hp_aon_iso", &self.force_hp_aon_iso())
+            .field("force_hp_aon_pu", &self.force_hp_aon_pu())
+            .field("force_hp_aon_no_reset", &self.force_hp_aon_no_reset())
+            .field("force_hp_aon_no_iso", &self.force_hp_aon_no_iso())
+            .field("force_hp_aon_pd", &self.force_hp_aon_pd())
+            .field("pd_hp_aon_mask", &self.pd_hp_aon_mask())
+            .field("pd_hp_aon_pd_mask", &self.pd_hp_aon_pd_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_HPAON_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/power_pd_hpcpu_cntl.rs b/esp32h2/src/pmu/power_pd_hpcpu_cntl.rs
index 2c7e4d97ee..9bd4d5df8d 100644
--- a/esp32h2/src/pmu/power_pd_hpcpu_cntl.rs
+++ b/esp32h2/src/pmu/power_pd_hpcpu_cntl.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_HPCPU_CNTL")
-            .field(
-                "force_hp_cpu_reset",
-                &format_args!("{}", self.force_hp_cpu_reset().bit()),
-            )
-            .field(
-                "force_hp_cpu_iso",
-                &format_args!("{}", self.force_hp_cpu_iso().bit()),
-            )
-            .field(
-                "force_hp_cpu_pu",
-                &format_args!("{}", self.force_hp_cpu_pu().bit()),
-            )
-            .field(
-                "force_hp_cpu_no_reset",
-                &format_args!("{}", self.force_hp_cpu_no_reset().bit()),
-            )
-            .field(
-                "force_hp_cpu_no_iso",
-                &format_args!("{}", self.force_hp_cpu_no_iso().bit()),
-            )
-            .field(
-                "force_hp_cpu_pd",
-                &format_args!("{}", self.force_hp_cpu_pd().bit()),
-            )
-            .field(
-                "pd_hp_cpu_mask",
-                &format_args!("{}", self.pd_hp_cpu_mask().bits()),
-            )
-            .field(
-                "pd_hp_cpu_pd_mask",
-                &format_args!("{}", self.pd_hp_cpu_pd_mask().bits()),
-            )
+            .field("force_hp_cpu_reset", &self.force_hp_cpu_reset())
+            .field("force_hp_cpu_iso", &self.force_hp_cpu_iso())
+            .field("force_hp_cpu_pu", &self.force_hp_cpu_pu())
+            .field("force_hp_cpu_no_reset", &self.force_hp_cpu_no_reset())
+            .field("force_hp_cpu_no_iso", &self.force_hp_cpu_no_iso())
+            .field("force_hp_cpu_pd", &self.force_hp_cpu_pd())
+            .field("pd_hp_cpu_mask", &self.pd_hp_cpu_mask())
+            .field("pd_hp_cpu_pd_mask", &self.pd_hp_cpu_pd_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_HPCPU_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/power_pd_hpwifi_cntl.rs b/esp32h2/src/pmu/power_pd_hpwifi_cntl.rs
index b1f7743055..d89bf9d7e2 100644
--- a/esp32h2/src/pmu/power_pd_hpwifi_cntl.rs
+++ b/esp32h2/src/pmu/power_pd_hpwifi_cntl.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_HPWIFI_CNTL")
-            .field(
-                "force_hp_wifi_reset",
-                &format_args!("{}", self.force_hp_wifi_reset().bit()),
-            )
-            .field(
-                "force_hp_wifi_iso",
-                &format_args!("{}", self.force_hp_wifi_iso().bit()),
-            )
-            .field(
-                "force_hp_wifi_pu",
-                &format_args!("{}", self.force_hp_wifi_pu().bit()),
-            )
-            .field(
-                "force_hp_wifi_no_reset",
-                &format_args!("{}", self.force_hp_wifi_no_reset().bit()),
-            )
-            .field(
-                "force_hp_wifi_no_iso",
-                &format_args!("{}", self.force_hp_wifi_no_iso().bit()),
-            )
-            .field(
-                "force_hp_wifi_pd",
-                &format_args!("{}", self.force_hp_wifi_pd().bit()),
-            )
-            .field(
-                "pd_hp_wifi_mask",
-                &format_args!("{}", self.pd_hp_wifi_mask().bits()),
-            )
-            .field(
-                "pd_hp_wifi_pd_mask",
-                &format_args!("{}", self.pd_hp_wifi_pd_mask().bits()),
-            )
+            .field("force_hp_wifi_reset", &self.force_hp_wifi_reset())
+            .field("force_hp_wifi_iso", &self.force_hp_wifi_iso())
+            .field("force_hp_wifi_pu", &self.force_hp_wifi_pu())
+            .field("force_hp_wifi_no_reset", &self.force_hp_wifi_no_reset())
+            .field("force_hp_wifi_no_iso", &self.force_hp_wifi_no_iso())
+            .field("force_hp_wifi_pd", &self.force_hp_wifi_pd())
+            .field("pd_hp_wifi_mask", &self.pd_hp_wifi_mask())
+            .field("pd_hp_wifi_pd_mask", &self.pd_hp_wifi_pd_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_HPWIFI_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/power_pd_lpperi_cntl.rs b/esp32h2/src/pmu/power_pd_lpperi_cntl.rs
index 6f27fae0e2..f1a688639c 100644
--- a/esp32h2/src/pmu/power_pd_lpperi_cntl.rs
+++ b/esp32h2/src/pmu/power_pd_lpperi_cntl.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_LPPERI_CNTL")
-            .field(
-                "force_lp_peri_reset",
-                &format_args!("{}", self.force_lp_peri_reset().bit()),
-            )
-            .field(
-                "force_lp_peri_iso",
-                &format_args!("{}", self.force_lp_peri_iso().bit()),
-            )
-            .field(
-                "force_lp_peri_pu",
-                &format_args!("{}", self.force_lp_peri_pu().bit()),
-            )
-            .field(
-                "force_lp_peri_no_reset",
-                &format_args!("{}", self.force_lp_peri_no_reset().bit()),
-            )
-            .field(
-                "force_lp_peri_no_iso",
-                &format_args!("{}", self.force_lp_peri_no_iso().bit()),
-            )
-            .field(
-                "force_lp_peri_pd",
-                &format_args!("{}", self.force_lp_peri_pd().bit()),
-            )
+            .field("force_lp_peri_reset", &self.force_lp_peri_reset())
+            .field("force_lp_peri_iso", &self.force_lp_peri_iso())
+            .field("force_lp_peri_pu", &self.force_lp_peri_pu())
+            .field("force_lp_peri_no_reset", &self.force_lp_peri_no_reset())
+            .field("force_lp_peri_no_iso", &self.force_lp_peri_no_iso())
+            .field("force_lp_peri_pd", &self.force_lp_peri_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_LPPERI_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/power_pd_mem_cntl.rs b/esp32h2/src/pmu/power_pd_mem_cntl.rs
index 81314bf2a5..6297526aa0 100644
--- a/esp32h2/src/pmu/power_pd_mem_cntl.rs
+++ b/esp32h2/src/pmu/power_pd_mem_cntl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_MEM_CNTL")
-            .field(
-                "force_hp_mem_iso",
-                &format_args!("{}", self.force_hp_mem_iso().bits()),
-            )
-            .field(
-                "force_hp_mem_pd",
-                &format_args!("{}", self.force_hp_mem_pd().bits()),
-            )
-            .field(
-                "force_hp_mem_no_iso",
-                &format_args!("{}", self.force_hp_mem_no_iso().bits()),
-            )
-            .field(
-                "force_hp_mem_pu",
-                &format_args!("{}", self.force_hp_mem_pu().bits()),
-            )
+            .field("force_hp_mem_iso", &self.force_hp_mem_iso())
+            .field("force_hp_mem_pd", &self.force_hp_mem_pd())
+            .field("force_hp_mem_no_iso", &self.force_hp_mem_no_iso())
+            .field("force_hp_mem_pu", &self.force_hp_mem_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_MEM_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/power_pd_mem_mask.rs b/esp32h2/src/pmu/power_pd_mem_mask.rs
index 9ea2a97a10..ea6fa14c62 100644
--- a/esp32h2/src/pmu/power_pd_mem_mask.rs
+++ b/esp32h2/src/pmu/power_pd_mem_mask.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_MEM_MASK")
-            .field(
-                "pd_hp_mem2_pd_mask",
-                &format_args!("{}", self.pd_hp_mem2_pd_mask().bits()),
-            )
-            .field(
-                "pd_hp_mem1_pd_mask",
-                &format_args!("{}", self.pd_hp_mem1_pd_mask().bits()),
-            )
-            .field(
-                "pd_hp_mem0_pd_mask",
-                &format_args!("{}", self.pd_hp_mem0_pd_mask().bits()),
-            )
-            .field(
-                "pd_hp_mem2_mask",
-                &format_args!("{}", self.pd_hp_mem2_mask().bits()),
-            )
-            .field(
-                "pd_hp_mem1_mask",
-                &format_args!("{}", self.pd_hp_mem1_mask().bits()),
-            )
-            .field(
-                "pd_hp_mem0_mask",
-                &format_args!("{}", self.pd_hp_mem0_mask().bits()),
-            )
+            .field("pd_hp_mem2_pd_mask", &self.pd_hp_mem2_pd_mask())
+            .field("pd_hp_mem1_pd_mask", &self.pd_hp_mem1_pd_mask())
+            .field("pd_hp_mem0_pd_mask", &self.pd_hp_mem0_pd_mask())
+            .field("pd_hp_mem2_mask", &self.pd_hp_mem2_mask())
+            .field("pd_hp_mem1_mask", &self.pd_hp_mem1_mask())
+            .field("pd_hp_mem0_mask", &self.pd_hp_mem0_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_MEM_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/power_pd_top_cntl.rs b/esp32h2/src/pmu/power_pd_top_cntl.rs
index 4beb2e1b2b..e753fe5a3b 100644
--- a/esp32h2/src/pmu/power_pd_top_cntl.rs
+++ b/esp32h2/src/pmu/power_pd_top_cntl.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_TOP_CNTL")
-            .field(
-                "force_top_reset",
-                &format_args!("{}", self.force_top_reset().bit()),
-            )
-            .field(
-                "force_top_iso",
-                &format_args!("{}", self.force_top_iso().bit()),
-            )
-            .field(
-                "force_top_pu",
-                &format_args!("{}", self.force_top_pu().bit()),
-            )
-            .field(
-                "force_top_no_reset",
-                &format_args!("{}", self.force_top_no_reset().bit()),
-            )
-            .field(
-                "force_top_no_iso",
-                &format_args!("{}", self.force_top_no_iso().bit()),
-            )
-            .field(
-                "force_top_pd",
-                &format_args!("{}", self.force_top_pd().bit()),
-            )
-            .field(
-                "pd_top_mask",
-                &format_args!("{}", self.pd_top_mask().bits()),
-            )
-            .field(
-                "pd_top_pd_mask",
-                &format_args!("{}", self.pd_top_pd_mask().bits()),
-            )
+            .field("force_top_reset", &self.force_top_reset())
+            .field("force_top_iso", &self.force_top_iso())
+            .field("force_top_pu", &self.force_top_pu())
+            .field("force_top_no_reset", &self.force_top_no_reset())
+            .field("force_top_no_iso", &self.force_top_no_iso())
+            .field("force_top_pd", &self.force_top_pd())
+            .field("pd_top_mask", &self.pd_top_mask())
+            .field("pd_top_pd_mask", &self.pd_top_pd_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_TOP_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/power_vdd_spi_cntl.rs b/esp32h2/src/pmu/power_vdd_spi_cntl.rs
index ba88db2c4a..baf42e1726 100644
--- a/esp32h2/src/pmu/power_vdd_spi_cntl.rs
+++ b/esp32h2/src/pmu/power_vdd_spi_cntl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_VDD_SPI_CNTL")
-            .field(
-                "vdd_spi_pwr_wait",
-                &format_args!("{}", self.vdd_spi_pwr_wait().bits()),
-            )
-            .field(
-                "vdd_spi_pwr_sw",
-                &format_args!("{}", self.vdd_spi_pwr_sw().bits()),
-            )
-            .field(
-                "vdd_spi_pwr_sel_sw",
-                &format_args!("{}", self.vdd_spi_pwr_sel_sw().bit()),
-            )
+            .field("vdd_spi_pwr_wait", &self.vdd_spi_pwr_wait())
+            .field("vdd_spi_pwr_sw", &self.vdd_spi_pwr_sw())
+            .field("vdd_spi_pwr_sel_sw", &self.vdd_spi_pwr_sel_sw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_VDD_SPI_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 18:28 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/power_wait_timer0.rs b/esp32h2/src/pmu/power_wait_timer0.rs
index 30802f3fd5..b3cf314033 100644
--- a/esp32h2/src/pmu/power_wait_timer0.rs
+++ b/esp32h2/src/pmu/power_wait_timer0.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_WAIT_TIMER0")
-            .field(
-                "dg_hp_powerdown_timer",
-                &format_args!("{}", self.dg_hp_powerdown_timer().bits()),
-            )
-            .field(
-                "dg_hp_powerup_timer",
-                &format_args!("{}", self.dg_hp_powerup_timer().bits()),
-            )
-            .field(
-                "dg_hp_wait_timer",
-                &format_args!("{}", self.dg_hp_wait_timer().bits()),
-            )
+            .field("dg_hp_powerdown_timer", &self.dg_hp_powerdown_timer())
+            .field("dg_hp_powerup_timer", &self.dg_hp_powerup_timer())
+            .field("dg_hp_wait_timer", &self.dg_hp_wait_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_WAIT_TIMER0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 5:13 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/power_wait_timer1.rs b/esp32h2/src/pmu/power_wait_timer1.rs
index 877451923f..af896ee3a5 100644
--- a/esp32h2/src/pmu/power_wait_timer1.rs
+++ b/esp32h2/src/pmu/power_wait_timer1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_WAIT_TIMER1")
-            .field(
-                "dg_lp_powerdown_timer",
-                &format_args!("{}", self.dg_lp_powerdown_timer().bits()),
-            )
-            .field(
-                "dg_lp_powerup_timer",
-                &format_args!("{}", self.dg_lp_powerup_timer().bits()),
-            )
-            .field(
-                "dg_lp_wait_timer",
-                &format_args!("{}", self.dg_lp_wait_timer().bits()),
-            )
+            .field("dg_lp_powerdown_timer", &self.dg_lp_powerdown_timer())
+            .field("dg_lp_powerup_timer", &self.dg_lp_powerup_timer())
+            .field("dg_lp_wait_timer", &self.dg_lp_wait_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_WAIT_TIMER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 9:15 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/pwr_state.rs b/esp32h2/src/pmu/pwr_state.rs
index 70a9b5f028..372452f2d2 100644
--- a/esp32h2/src/pmu/pwr_state.rs
+++ b/esp32h2/src/pmu/pwr_state.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWR_STATE")
-            .field(
-                "backup_st_state",
-                &format_args!("{}", self.backup_st_state().bits()),
-            )
-            .field(
-                "lp_pwr_st_state",
-                &format_args!("{}", self.lp_pwr_st_state().bits()),
-            )
-            .field(
-                "hp_pwr_st_state",
-                &format_args!("{}", self.hp_pwr_st_state().bits()),
-            )
+            .field("backup_st_state", &self.backup_st_state())
+            .field("lp_pwr_st_state", &self.lp_pwr_st_state())
+            .field("hp_pwr_st_state", &self.hp_pwr_st_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWR_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwr_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PWR_STATE_SPEC;
 impl crate::RegisterSpec for PWR_STATE_SPEC {
diff --git a/esp32h2/src/pmu/rf_pwc.rs b/esp32h2/src/pmu/rf_pwc.rs
index 9e8dc161c0..5d73cfd21c 100644
--- a/esp32h2/src/pmu/rf_pwc.rs
+++ b/esp32h2/src/pmu/rf_pwc.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RF_PWC")
-            .field(
-                "xpd_perif_i2c",
-                &format_args!("{}", self.xpd_perif_i2c().bit()),
-            )
-            .field(
-                "xpd_rftx_i2c",
-                &format_args!("{}", self.xpd_rftx_i2c().bit()),
-            )
-            .field(
-                "xpd_rfrx_i2c",
-                &format_args!("{}", self.xpd_rfrx_i2c().bit()),
-            )
-            .field("xpd_rfpll", &format_args!("{}", self.xpd_rfpll().bit()))
-            .field(
-                "xpd_force_rfpll",
-                &format_args!("{}", self.xpd_force_rfpll().bit()),
-            )
+            .field("xpd_perif_i2c", &self.xpd_perif_i2c())
+            .field("xpd_rftx_i2c", &self.xpd_rftx_i2c())
+            .field("xpd_rfrx_i2c", &self.xpd_rfrx_i2c())
+            .field("xpd_rfpll", &self.xpd_rfpll())
+            .field("xpd_force_rfpll", &self.xpd_force_rfpll())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RF_PWC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/slp_wakeup_cntl1.rs b/esp32h2/src/pmu/slp_wakeup_cntl1.rs
index b5813a7699..0211531bff 100644
--- a/esp32h2/src/pmu/slp_wakeup_cntl1.rs
+++ b/esp32h2/src/pmu/slp_wakeup_cntl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL1")
-            .field(
-                "sleep_reject_ena",
-                &format_args!("{}", self.sleep_reject_ena().bits()),
-            )
-            .field(
-                "slp_reject_en",
-                &format_args!("{}", self.slp_reject_en().bit()),
-            )
+            .field("sleep_reject_ena", &self.sleep_reject_ena())
+            .field("slp_reject_en", &self.slp_reject_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/slp_wakeup_cntl2.rs b/esp32h2/src/pmu/slp_wakeup_cntl2.rs
index 96c4e3f3a8..da7355e764 100644
--- a/esp32h2/src/pmu/slp_wakeup_cntl2.rs
+++ b/esp32h2/src/pmu/slp_wakeup_cntl2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL2")
-            .field("wakeup_ena", &format_args!("{}", self.wakeup_ena().bits()))
+            .field("wakeup_ena", &self.wakeup_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/slp_wakeup_cntl3.rs b/esp32h2/src/pmu/slp_wakeup_cntl3.rs
index b9fcfe21ca..dcde09eb3a 100644
--- a/esp32h2/src/pmu/slp_wakeup_cntl3.rs
+++ b/esp32h2/src/pmu/slp_wakeup_cntl3.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL3")
-            .field(
-                "lp_min_slp_val",
-                &format_args!("{}", self.lp_min_slp_val().bits()),
-            )
-            .field(
-                "hp_min_slp_val",
-                &format_args!("{}", self.hp_min_slp_val().bits()),
-            )
-            .field(
-                "sleep_prt_sel",
-                &format_args!("{}", self.sleep_prt_sel().bits()),
-            )
+            .field("lp_min_slp_val", &self.lp_min_slp_val())
+            .field("hp_min_slp_val", &self.hp_min_slp_val())
+            .field("sleep_prt_sel", &self.sleep_prt_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/slp_wakeup_cntl5.rs b/esp32h2/src/pmu/slp_wakeup_cntl5.rs
index 0073fbaa70..6022a5a3ee 100644
--- a/esp32h2/src/pmu/slp_wakeup_cntl5.rs
+++ b/esp32h2/src/pmu/slp_wakeup_cntl5.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL5")
-            .field(
-                "modem_wait_target",
-                &format_args!("{}", self.modem_wait_target().bits()),
-            )
-            .field(
-                "lp_ana_wait_target",
-                &format_args!("{}", self.lp_ana_wait_target().bits()),
-            )
+            .field("modem_wait_target", &self.modem_wait_target())
+            .field("lp_ana_wait_target", &self.lp_ana_wait_target())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/slp_wakeup_cntl6.rs b/esp32h2/src/pmu/slp_wakeup_cntl6.rs
index 30e86accf3..9aff65cbae 100644
--- a/esp32h2/src/pmu/slp_wakeup_cntl6.rs
+++ b/esp32h2/src/pmu/slp_wakeup_cntl6.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL6")
-            .field(
-                "soc_wakeup_wait",
-                &format_args!("{}", self.soc_wakeup_wait().bits()),
-            )
-            .field(
-                "soc_wakeup_wait_cfg",
-                &format_args!("{}", self.soc_wakeup_wait_cfg().bits()),
-            )
+            .field("soc_wakeup_wait", &self.soc_wakeup_wait())
+            .field("soc_wakeup_wait_cfg", &self.soc_wakeup_wait_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/slp_wakeup_cntl7.rs b/esp32h2/src/pmu/slp_wakeup_cntl7.rs
index 811e157fd8..ec649cb9a4 100644
--- a/esp32h2/src/pmu/slp_wakeup_cntl7.rs
+++ b/esp32h2/src/pmu/slp_wakeup_cntl7.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL7")
-            .field(
-                "ana_wait_target",
-                &format_args!("{}", self.ana_wait_target().bits()),
-            )
+            .field("ana_wait_target", &self.ana_wait_target())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/pmu/slp_wakeup_status0.rs b/esp32h2/src/pmu/slp_wakeup_status0.rs
index 46f04f39ac..ae53203367 100644
--- a/esp32h2/src/pmu/slp_wakeup_status0.rs
+++ b/esp32h2/src/pmu/slp_wakeup_status0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_STATUS0")
-            .field(
-                "wakeup_cause",
-                &format_args!("{}", self.wakeup_cause().bits()),
-            )
+            .field("wakeup_cause", &self.wakeup_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_STATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_status0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLP_WAKEUP_STATUS0_SPEC;
 impl crate::RegisterSpec for SLP_WAKEUP_STATUS0_SPEC {
diff --git a/esp32h2/src/pmu/slp_wakeup_status1.rs b/esp32h2/src/pmu/slp_wakeup_status1.rs
index 5f8f7be6a4..154f1b1e52 100644
--- a/esp32h2/src/pmu/slp_wakeup_status1.rs
+++ b/esp32h2/src/pmu/slp_wakeup_status1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_STATUS1")
-            .field(
-                "reject_cause",
-                &format_args!("{}", self.reject_cause().bits()),
-            )
+            .field("reject_cause", &self.reject_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_status1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLP_WAKEUP_STATUS1_SPEC;
 impl crate::RegisterSpec for SLP_WAKEUP_STATUS1_SPEC {
diff --git a/esp32h2/src/pmu/vdd_spi_status.rs b/esp32h2/src/pmu/vdd_spi_status.rs
index 7ac300b44e..95d0f5daf6 100644
--- a/esp32h2/src/pmu/vdd_spi_status.rs
+++ b/esp32h2/src/pmu/vdd_spi_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VDD_SPI_STATUS")
-            .field(
-                "stable_vdd_spi_pwr_drv",
-                &format_args!("{}", self.stable_vdd_spi_pwr_drv().bit()),
-            )
+            .field("stable_vdd_spi_pwr_drv", &self.stable_vdd_spi_pwr_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VDD_SPI_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vdd_spi_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VDD_SPI_STATUS_SPEC;
 impl crate::RegisterSpec for VDD_SPI_STATUS_SPEC {
diff --git a/esp32h2/src/pmu/vddbat_cfg.rs b/esp32h2/src/pmu/vddbat_cfg.rs
index 2624036204..5e921509cc 100644
--- a/esp32h2/src/pmu/vddbat_cfg.rs
+++ b/esp32h2/src/pmu/vddbat_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VDDBAT_CFG")
-            .field(
-                "vddbat_mode",
-                &format_args!("{}", self.vddbat_mode().bits()),
-            )
+            .field("vddbat_mode", &self.vddbat_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VDDBAT_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32h2/src/rmt/ch_rx_carrier_rm.rs b/esp32h2/src/rmt/ch_rx_carrier_rm.rs
index 110fc179a3..d55c19dbf1 100644
--- a/esp32h2/src/rmt/ch_rx_carrier_rm.rs
+++ b/esp32h2/src/rmt/ch_rx_carrier_rm.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_CARRIER_RM")
-            .field(
-                "carrier_low_thres",
-                &format_args!("{}", self.carrier_low_thres().bits()),
-            )
-            .field(
-                "carrier_high_thres",
-                &format_args!("{}", self.carrier_high_thres().bits()),
-            )
+            .field("carrier_low_thres", &self.carrier_low_thres())
+            .field("carrier_high_thres", &self.carrier_high_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_CARRIER_RM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s."]
     #[inline(always)]
diff --git a/esp32h2/src/rmt/ch_rx_conf0.rs b/esp32h2/src/rmt/ch_rx_conf0.rs
index 0e3417b062..1e9b83cc9d 100644
--- a/esp32h2/src/rmt/ch_rx_conf0.rs
+++ b/esp32h2/src/rmt/ch_rx_conf0.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_CONF0")
-            .field("div_cnt", &format_args!("{}", self.div_cnt().bits()))
-            .field("idle_thres", &format_args!("{}", self.idle_thres().bits()))
-            .field("mem_size", &format_args!("{}", self.mem_size().bits()))
-            .field("carrier_en", &format_args!("{}", self.carrier_en().bit()))
-            .field(
-                "carrier_out_lv",
-                &format_args!("{}", self.carrier_out_lv().bit()),
-            )
+            .field("div_cnt", &self.div_cnt())
+            .field("idle_thres", &self.idle_thres())
+            .field("mem_size", &self.mem_size())
+            .field("carrier_en", &self.carrier_en())
+            .field("carrier_out_lv", &self.carrier_out_lv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the divider for clock of CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32h2/src/rmt/ch_rx_conf1.rs b/esp32h2/src/rmt/ch_rx_conf1.rs
index 4d32c964bc..7e8199c2e3 100644
--- a/esp32h2/src/rmt/ch_rx_conf1.rs
+++ b/esp32h2/src/rmt/ch_rx_conf1.rs
@@ -61,29 +61,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_CONF1")
-            .field("rx_en", &format_args!("{}", self.rx_en().bit()))
-            .field("mem_owner", &format_args!("{}", self.mem_owner().bit()))
-            .field(
-                "rx_filter_en",
-                &format_args!("{}", self.rx_filter_en().bit()),
-            )
-            .field(
-                "rx_filter_thres",
-                &format_args!("{}", self.rx_filter_thres().bits()),
-            )
-            .field(
-                "mem_rx_wrap_en",
-                &format_args!("{}", self.mem_rx_wrap_en().bit()),
-            )
+            .field("rx_en", &self.rx_en())
+            .field("mem_owner", &self.mem_owner())
+            .field("rx_filter_en", &self.rx_filter_en())
+            .field("rx_filter_thres", &self.rx_filter_thres())
+            .field("mem_rx_wrap_en", &self.mem_rx_wrap_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable receiver to receive data on CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32h2/src/rmt/ch_rx_lim.rs b/esp32h2/src/rmt/ch_rx_lim.rs
index 0d2391cf05..8d5fe9e952 100644
--- a/esp32h2/src/rmt/ch_rx_lim.rs
+++ b/esp32h2/src/rmt/ch_rx_lim.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_LIM")
-            .field("rmt_rx_lim", &format_args!("{}", self.rmt_rx_lim().bits()))
+            .field("rmt_rx_lim", &self.rmt_rx_lim())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_LIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can receive."]
     #[inline(always)]
diff --git a/esp32h2/src/rmt/ch_rx_status.rs b/esp32h2/src/rmt/ch_rx_status.rs
index 0147918bf4..b4778d0d10 100644
--- a/esp32h2/src/rmt/ch_rx_status.rs
+++ b/esp32h2/src/rmt/ch_rx_status.rs
@@ -48,33 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_STATUS")
-            .field(
-                "mem_waddr_ex",
-                &format_args!("{}", self.mem_waddr_ex().bits()),
-            )
-            .field(
-                "apb_mem_raddr",
-                &format_args!("{}", self.apb_mem_raddr().bits()),
-            )
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field(
-                "mem_owner_err",
-                &format_args!("{}", self.mem_owner_err().bit()),
-            )
-            .field("mem_full", &format_args!("{}", self.mem_full().bit()))
-            .field(
-                "apb_mem_rd_err",
-                &format_args!("{}", self.apb_mem_rd_err().bit()),
-            )
+            .field("mem_waddr_ex", &self.mem_waddr_ex())
+            .field("apb_mem_raddr", &self.apb_mem_raddr())
+            .field("state", &self.state())
+            .field("mem_owner_err", &self.mem_owner_err())
+            .field("mem_full", &self.mem_full())
+            .field("apb_mem_rd_err", &self.apb_mem_rd_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Channel %s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_RX_STATUS_SPEC;
 impl crate::RegisterSpec for CH_RX_STATUS_SPEC {
diff --git a/esp32h2/src/rmt/ch_tx_conf0.rs b/esp32h2/src/rmt/ch_tx_conf0.rs
index b86c765934..f1d6b5bea8 100644
--- a/esp32h2/src/rmt/ch_tx_conf0.rs
+++ b/esp32h2/src/rmt/ch_tx_conf0.rs
@@ -108,37 +108,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_TX_CONF0")
-            .field(
-                "tx_conti_mode",
-                &format_args!("{}", self.tx_conti_mode().bit()),
-            )
-            .field(
-                "mem_tx_wrap_en",
-                &format_args!("{}", self.mem_tx_wrap_en().bit()),
-            )
-            .field("idle_out_lv", &format_args!("{}", self.idle_out_lv().bit()))
-            .field("idle_out_en", &format_args!("{}", self.idle_out_en().bit()))
-            .field("tx_stop", &format_args!("{}", self.tx_stop().bit()))
-            .field("div_cnt", &format_args!("{}", self.div_cnt().bits()))
-            .field("mem_size", &format_args!("{}", self.mem_size().bits()))
-            .field(
-                "carrier_eff_en",
-                &format_args!("{}", self.carrier_eff_en().bit()),
-            )
-            .field("carrier_en", &format_args!("{}", self.carrier_en().bit()))
-            .field(
-                "carrier_out_lv",
-                &format_args!("{}", self.carrier_out_lv().bit()),
-            )
+            .field("tx_conti_mode", &self.tx_conti_mode())
+            .field("mem_tx_wrap_en", &self.mem_tx_wrap_en())
+            .field("idle_out_lv", &self.idle_out_lv())
+            .field("idle_out_en", &self.idle_out_en())
+            .field("tx_stop", &self.tx_stop())
+            .field("div_cnt", &self.div_cnt())
+            .field("mem_size", &self.mem_size())
+            .field("carrier_eff_en", &self.carrier_eff_en())
+            .field("carrier_en", &self.carrier_en())
+            .field("carrier_out_lv", &self.carrier_out_lv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_TX_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to start sending data on CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32h2/src/rmt/ch_tx_lim.rs b/esp32h2/src/rmt/ch_tx_lim.rs
index 8102018dc9..774de58471 100644
--- a/esp32h2/src/rmt/ch_tx_lim.rs
+++ b/esp32h2/src/rmt/ch_tx_lim.rs
@@ -46,28 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_TX_LIM")
-            .field("tx_lim", &format_args!("{}", self.tx_lim().bits()))
-            .field(
-                "tx_loop_num",
-                &format_args!("{}", self.tx_loop_num().bits()),
-            )
-            .field(
-                "tx_loop_cnt_en",
-                &format_args!("{}", self.tx_loop_cnt_en().bit()),
-            )
-            .field(
-                "loop_stop_en",
-                &format_args!("{}", self.loop_stop_en().bit()),
-            )
+            .field("tx_lim", &self.tx_lim())
+            .field("tx_loop_num", &self.tx_loop_num())
+            .field("tx_loop_cnt_en", &self.tx_loop_cnt_en())
+            .field("loop_stop_en", &self.loop_stop_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_TX_LIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can send out."]
     #[inline(always)]
diff --git a/esp32h2/src/rmt/ch_tx_status.rs b/esp32h2/src/rmt/ch_tx_status.rs
index d53bd94532..b7506c352a 100644
--- a/esp32h2/src/rmt/ch_tx_status.rs
+++ b/esp32h2/src/rmt/ch_tx_status.rs
@@ -55,37 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_TX_STATUS")
-            .field(
-                "mem_raddr_ex",
-                &format_args!("{}", self.mem_raddr_ex().bits()),
-            )
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field(
-                "apb_mem_waddr",
-                &format_args!("{}", self.apb_mem_waddr().bits()),
-            )
-            .field(
-                "apb_mem_rd_err",
-                &format_args!("{}", self.apb_mem_rd_err().bit()),
-            )
-            .field("mem_empty", &format_args!("{}", self.mem_empty().bit()))
-            .field(
-                "apb_mem_wr_err",
-                &format_args!("{}", self.apb_mem_wr_err().bit()),
-            )
-            .field(
-                "apb_mem_raddr",
-                &format_args!("{}", self.apb_mem_raddr().bits()),
-            )
+            .field("mem_raddr_ex", &self.mem_raddr_ex())
+            .field("state", &self.state())
+            .field("apb_mem_waddr", &self.apb_mem_waddr())
+            .field("apb_mem_rd_err", &self.apb_mem_rd_err())
+            .field("mem_empty", &self.mem_empty())
+            .field("apb_mem_wr_err", &self.apb_mem_wr_err())
+            .field("apb_mem_raddr", &self.apb_mem_raddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Channel %s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_TX_STATUS_SPEC;
 impl crate::RegisterSpec for CH_TX_STATUS_SPEC {
diff --git a/esp32h2/src/rmt/chcarrier_duty.rs b/esp32h2/src/rmt/chcarrier_duty.rs
index a3f3981bc9..ffed06d8c2 100644
--- a/esp32h2/src/rmt/chcarrier_duty.rs
+++ b/esp32h2/src/rmt/chcarrier_duty.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHCARRIER_DUTY")
-            .field(
-                "carrier_low",
-                &format_args!("{}", self.carrier_low().bits()),
-            )
-            .field(
-                "carrier_high",
-                &format_args!("{}", self.carrier_high().bits()),
-            )
+            .field("carrier_low", &self.carrier_low())
+            .field("carrier_high", &self.carrier_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHCARRIER_DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure carrier wave 's low level clock period for CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32h2/src/rmt/chdata.rs b/esp32h2/src/rmt/chdata.rs
index 8efd5cd2c1..5e6da546a9 100644
--- a/esp32h2/src/rmt/chdata.rs
+++ b/esp32h2/src/rmt/chdata.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHDATA")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Read and write data for channel %s via APB FIFO."]
     #[inline(always)]
diff --git a/esp32h2/src/rmt/date.rs b/esp32h2/src/rmt/date.rs
index ae2f20e76a..ce972b08ee 100644
--- a/esp32h2/src/rmt/date.rs
+++ b/esp32h2/src/rmt/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("rmt_date", &format_args!("{}", self.rmt_date().bits()))
+            .field("rmt_date", &self.rmt_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - This is the version register."]
     #[inline(always)]
diff --git a/esp32h2/src/rmt/int_ena.rs b/esp32h2/src/rmt/int_ena.rs
index 3e121d4288..971b09544d 100644
--- a/esp32h2/src/rmt/int_ena.rs
+++ b/esp32h2/src/rmt/int_ena.rs
@@ -211,41 +211,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_rx_end", &format_args!("{}", self.ch2_rx_end().bit()))
-            .field("ch3_rx_end", &format_args!("{}", self.ch3_rx_end().bit()))
-            .field("ch0_tx_err", &format_args!("{}", self.ch0_tx_err().bit()))
-            .field("ch1_tx_err", &format_args!("{}", self.ch1_tx_err().bit()))
-            .field("ch2_rx_err", &format_args!("{}", self.ch2_rx_err().bit()))
-            .field("ch3_rx_err", &format_args!("{}", self.ch3_rx_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_rx_thr_event",
-                &format_args!("{}", self.ch2_rx_thr_event().bit()),
-            )
-            .field(
-                "ch3_rx_thr_event",
-                &format_args!("{}", self.ch3_rx_thr_event().bit()),
-            )
-            .field("ch0_x_loop", &format_args!("{}", self.ch0_x_loop().bit()))
-            .field("ch1_x_loop", &format_args!("{}", self.ch1_x_loop().bit()))
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_rx_end", &self.ch2_rx_end())
+            .field("ch3_rx_end", &self.ch3_rx_end())
+            .field("ch0_tx_err", &self.ch0_tx_err())
+            .field("ch1_tx_err", &self.ch1_tx_err())
+            .field("ch2_rx_err", &self.ch2_rx_err())
+            .field("ch3_rx_err", &self.ch3_rx_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_rx_thr_event", &self.ch2_rx_thr_event())
+            .field("ch3_rx_thr_event", &self.ch3_rx_thr_event())
+            .field("ch0_x_loop", &self.ch0_x_loop())
+            .field("ch1_x_loop", &self.ch1_x_loop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for CH(0-1)_TX_END_INT."]
     #[doc = ""]
diff --git a/esp32h2/src/rmt/int_raw.rs b/esp32h2/src/rmt/int_raw.rs
index eb7363c2c9..f47e065dc2 100644
--- a/esp32h2/src/rmt/int_raw.rs
+++ b/esp32h2/src/rmt/int_raw.rs
@@ -211,41 +211,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_rx_end", &format_args!("{}", self.ch2_rx_end().bit()))
-            .field("ch3_rx_end", &format_args!("{}", self.ch3_rx_end().bit()))
-            .field("ch0_tx_err", &format_args!("{}", self.ch0_tx_err().bit()))
-            .field("ch1_tx_err", &format_args!("{}", self.ch1_tx_err().bit()))
-            .field("ch2_rx_err", &format_args!("{}", self.ch2_rx_err().bit()))
-            .field("ch3_rx_err", &format_args!("{}", self.ch3_rx_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_rx_thr_event",
-                &format_args!("{}", self.ch2_rx_thr_event().bit()),
-            )
-            .field(
-                "ch3_rx_thr_event",
-                &format_args!("{}", self.ch3_rx_thr_event().bit()),
-            )
-            .field("ch0_tx_loop", &format_args!("{}", self.ch0_tx_loop().bit()))
-            .field("ch1_tx_loop", &format_args!("{}", self.ch1_tx_loop().bit()))
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_rx_end", &self.ch2_rx_end())
+            .field("ch3_rx_end", &self.ch3_rx_end())
+            .field("ch0_tx_err", &self.ch0_tx_err())
+            .field("ch1_tx_err", &self.ch1_tx_err())
+            .field("ch2_rx_err", &self.ch2_rx_err())
+            .field("ch3_rx_err", &self.ch3_rx_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_rx_thr_event", &self.ch2_rx_thr_event())
+            .field("ch3_rx_thr_event", &self.ch3_rx_thr_event())
+            .field("ch0_tx_loop", &self.ch0_tx_loop())
+            .field("ch1_tx_loop", &self.ch1_tx_loop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt raw bit for CHANNEL(0-1). Triggered when transmission done."]
     #[doc = ""]
diff --git a/esp32h2/src/rmt/int_st.rs b/esp32h2/src/rmt/int_st.rs
index 44f452b415..a6bddc6f16 100644
--- a/esp32h2/src/rmt/int_st.rs
+++ b/esp32h2/src/rmt/int_st.rs
@@ -195,41 +195,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_rx_end", &format_args!("{}", self.ch2_rx_end().bit()))
-            .field("ch3_rx_end", &format_args!("{}", self.ch3_rx_end().bit()))
-            .field("ch0_tx_err", &format_args!("{}", self.ch0_tx_err().bit()))
-            .field("ch1_tx_err", &format_args!("{}", self.ch1_tx_err().bit()))
-            .field("ch2_rx_err", &format_args!("{}", self.ch2_rx_err().bit()))
-            .field("ch3_rx_err", &format_args!("{}", self.ch3_rx_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_rx_thr_event",
-                &format_args!("{}", self.ch2_rx_thr_event().bit()),
-            )
-            .field(
-                "ch3_rx_thr_event",
-                &format_args!("{}", self.ch3_rx_thr_event().bit()),
-            )
-            .field("ch0_x_loop", &format_args!("{}", self.ch0_x_loop().bit()))
-            .field("ch1_x_loop", &format_args!("{}", self.ch1_x_loop().bit()))
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_rx_end", &self.ch2_rx_end())
+            .field("ch3_rx_end", &self.ch3_rx_end())
+            .field("ch0_tx_err", &self.ch0_tx_err())
+            .field("ch1_tx_err", &self.ch1_tx_err())
+            .field("ch2_rx_err", &self.ch2_rx_err())
+            .field("ch3_rx_err", &self.ch3_rx_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_rx_thr_event", &self.ch2_rx_thr_event())
+            .field("ch3_rx_thr_event", &self.ch3_rx_thr_event())
+            .field("ch0_x_loop", &self.ch0_x_loop())
+            .field("ch1_x_loop", &self.ch1_x_loop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/rmt/sys_conf.rs b/esp32h2/src/rmt/sys_conf.rs
index 4efb4c0d04..c754deecee 100644
--- a/esp32h2/src/rmt/sys_conf.rs
+++ b/esp32h2/src/rmt/sys_conf.rs
@@ -98,40 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYS_CONF")
-            .field(
-                "apb_fifo_mask",
-                &format_args!("{}", self.apb_fifo_mask().bit()),
-            )
-            .field(
-                "mem_clk_force_on",
-                &format_args!("{}", self.mem_clk_force_on().bit()),
-            )
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bits()))
-            .field("sclk_active", &format_args!("{}", self.sclk_active().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("apb_fifo_mask", &self.apb_fifo_mask())
+            .field("mem_clk_force_on", &self.mem_clk_force_on())
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_active", &self.sclk_active())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'h1: access memory directly. 1'h0: access memory by FIFO."]
     #[inline(always)]
diff --git a/esp32h2/src/rmt/tx_sim.rs b/esp32h2/src/rmt/tx_sim.rs
index 784b1e1b34..821cb3607f 100644
--- a/esp32h2/src/rmt/tx_sim.rs
+++ b/esp32h2/src/rmt/tx_sim.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_SIM")
-            .field("ch0", &format_args!("{}", self.ch0().bit()))
-            .field("ch1", &format_args!("{}", self.ch1().bit()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("ch0", &self.ch0())
+            .field("ch1", &self.ch1())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_SIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels."]
     #[inline(always)]
diff --git a/esp32h2/src/rng/data.rs b/esp32h2/src/rng/data.rs
index 016046274d..4d812a63aa 100644
--- a/esp32h2/src/rng/data.rs
+++ b/esp32h2/src/rng/data.rs
@@ -6,12 +6,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Random number data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DATA_SPEC;
 impl crate::RegisterSpec for DATA_SPEC {
diff --git a/esp32h2/src/rsa/constant_time.rs b/esp32h2/src/rsa/constant_time.rs
index 843789ba32..2638b8415a 100644
--- a/esp32h2/src/rsa/constant_time.rs
+++ b/esp32h2/src/rsa/constant_time.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONSTANT_TIME")
-            .field(
-                "constant_time",
-                &format_args!("{}", self.constant_time().bit()),
-            )
+            .field("constant_time", &self.constant_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONSTANT_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures the constant_time option. 0: Acceleration 1: No acceleration (default)"]
     #[inline(always)]
diff --git a/esp32h2/src/rsa/date.rs b/esp32h2/src/rsa/date.rs
index 1eee4833d1..9a33aff7a7 100644
--- a/esp32h2/src/rsa/date.rs
+++ b/esp32h2/src/rsa/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/rsa/int_ena.rs b/esp32h2/src/rsa/int_ena.rs
index f1ce51b819..1782ceda85 100644
--- a/esp32h2/src/rsa/int_ena.rs
+++ b/esp32h2/src/rsa/int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("int_ena", &format_args!("{}", self.int_ena().bit()))
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to enable the RSA interrupt."]
     #[inline(always)]
diff --git a/esp32h2/src/rsa/m_mem.rs b/esp32h2/src/rsa/m_mem.rs
index f889cb91cf..cdddfe42b8 100644
--- a/esp32h2/src/rsa/m_mem.rs
+++ b/esp32h2/src/rsa/m_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Represents M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct M_MEM_SPEC;
diff --git a/esp32h2/src/rsa/m_prime.rs b/esp32h2/src/rsa/m_prime.rs
index 33fae2142f..56f959cc98 100644
--- a/esp32h2/src/rsa/m_prime.rs
+++ b/esp32h2/src/rsa/m_prime.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("M_PRIME")
-            .field("m_prime", &format_args!("{}", self.m_prime().bits()))
+            .field("m_prime", &self.m_prime())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_PRIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Represents M’"]
     #[inline(always)]
diff --git a/esp32h2/src/rsa/mode.rs b/esp32h2/src/rsa/mode.rs
index db479d6a09..7bdd4fe50f 100644
--- a/esp32h2/src/rsa/mode.rs
+++ b/esp32h2/src/rsa/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/rsa/query_clean.rs b/esp32h2/src/rsa/query_clean.rs
index b777d7ed18..200fde38af 100644
--- a/esp32h2/src/rsa/query_clean.rs
+++ b/esp32h2/src/rsa/query_clean.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_CLEAN")
-            .field("query_clean", &format_args!("{}", self.query_clean().bit()))
+            .field("query_clean", &self.query_clean())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_CLEAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RSA clean register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_clean::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_CLEAN_SPEC;
 impl crate::RegisterSpec for QUERY_CLEAN_SPEC {
diff --git a/esp32h2/src/rsa/query_idle.rs b/esp32h2/src/rsa/query_idle.rs
index 494d76973a..0fa4c50db2 100644
--- a/esp32h2/src/rsa/query_idle.rs
+++ b/esp32h2/src/rsa/query_idle.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_IDLE")
-            .field("query_idle", &format_args!("{}", self.query_idle().bit()))
+            .field("query_idle", &self.query_idle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_IDLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Represents the RSA status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_idle::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_IDLE_SPEC;
 impl crate::RegisterSpec for QUERY_IDLE_SPEC {
diff --git a/esp32h2/src/rsa/search_enable.rs b/esp32h2/src/rsa/search_enable.rs
index a08c68f820..1965337ac2 100644
--- a/esp32h2/src/rsa/search_enable.rs
+++ b/esp32h2/src/rsa/search_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEARCH_ENABLE")
-            .field(
-                "search_enable",
-                &format_args!("{}", self.search_enable().bit()),
-            )
+            .field("search_enable", &self.search_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEARCH_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configure the search option. 0: No acceleration (default) 1: Acceleration This option should be used together with RSA_SEARCH_POS."]
     #[inline(always)]
diff --git a/esp32h2/src/rsa/search_pos.rs b/esp32h2/src/rsa/search_pos.rs
index 0f1e4cd9e1..defcfe53d8 100644
--- a/esp32h2/src/rsa/search_pos.rs
+++ b/esp32h2/src/rsa/search_pos.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEARCH_POS")
-            .field("search_pos", &format_args!("{}", self.search_pos().bits()))
+            .field("search_pos", &self.search_pos())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEARCH_POS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high."]
     #[inline(always)]
diff --git a/esp32h2/src/rsa/x_mem.rs b/esp32h2/src/rsa/x_mem.rs
index edcf1cf0c4..122f41e2e1 100644
--- a/esp32h2/src/rsa/x_mem.rs
+++ b/esp32h2/src/rsa/x_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<X_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Represents X\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`x_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`x_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct X_MEM_SPEC;
diff --git a/esp32h2/src/rsa/y_mem.rs b/esp32h2/src/rsa/y_mem.rs
index c687cd0a52..fe33d71507 100644
--- a/esp32h2/src/rsa/y_mem.rs
+++ b/esp32h2/src/rsa/y_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Y_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Represents Y\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Y_MEM_SPEC;
diff --git a/esp32h2/src/rsa/z_mem.rs b/esp32h2/src/rsa/z_mem.rs
index 6826e9d664..5bee6c1785 100644
--- a/esp32h2/src/rsa/z_mem.rs
+++ b/esp32h2/src/rsa/z_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Z_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Represents Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Z_MEM_SPEC;
diff --git a/esp32h2/src/sha/busy.rs b/esp32h2/src/sha/busy.rs
index d586138364..ec4ecab687 100644
--- a/esp32h2/src/sha/busy.rs
+++ b/esp32h2/src/sha/busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUSY")
-            .field("state", &format_args!("{}", self.state().bit()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Busy register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUSY_SPEC;
 impl crate::RegisterSpec for BUSY_SPEC {
diff --git a/esp32h2/src/sha/date.rs b/esp32h2/src/sha/date.rs
index fea49bfb0c..9d86578ecf 100644
--- a/esp32h2/src/sha/date.rs
+++ b/esp32h2/src/sha/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/sha/dma_block_num.rs b/esp32h2/src/sha/dma_block_num.rs
index 235679368f..be8854254d 100644
--- a/esp32h2/src/sha/dma_block_num.rs
+++ b/esp32h2/src/sha/dma_block_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_BLOCK_NUM")
-            .field(
-                "dma_block_num",
-                &format_args!("{}", self.dma_block_num().bits()),
-            )
+            .field("dma_block_num", &self.dma_block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Dma-sha block number."]
     #[inline(always)]
diff --git a/esp32h2/src/sha/h_mem.rs b/esp32h2/src/sha/h_mem.rs
index e0865c92c6..13a6f95266 100644
--- a/esp32h2/src/sha/h_mem.rs
+++ b/esp32h2/src/sha/h_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Sha H memory which contains intermediate hash or finial hash.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct H_MEM_SPEC;
diff --git a/esp32h2/src/sha/irq_ena.rs b/esp32h2/src/sha/irq_ena.rs
index 8d61ac4aae..725a0f2641 100644
--- a/esp32h2/src/sha/irq_ena.rs
+++ b/esp32h2/src/sha/irq_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IRQ_ENA")
-            .field(
-                "interrupt_ena",
-                &format_args!("{}", self.interrupt_ena().bit()),
-            )
+            .field("interrupt_ena", &self.interrupt_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IRQ_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable."]
     #[inline(always)]
diff --git a/esp32h2/src/sha/m_mem.rs b/esp32h2/src/sha/m_mem.rs
index ccac5e7d71..7418659e89 100644
--- a/esp32h2/src/sha/m_mem.rs
+++ b/esp32h2/src/sha/m_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Sha M memory which contains message.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct M_MEM_SPEC;
diff --git a/esp32h2/src/sha/mode.rs b/esp32h2/src/sha/mode.rs
index 2b849314d6..ab2c8b2b20 100644
--- a/esp32h2/src/sha/mode.rs
+++ b/esp32h2/src/sha/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/sha/t_length.rs b/esp32h2/src/sha/t_length.rs
index 523a021805..845f709a89 100644
--- a/esp32h2/src/sha/t_length.rs
+++ b/esp32h2/src/sha/t_length.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T_LENGTH")
-            .field("t_length", &format_args!("{}", self.t_length().bits()))
+            .field("t_length", &self.t_length())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T_LENGTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Sha t_length (used if and only if mode == SHA_512/t)."]
     #[inline(always)]
diff --git a/esp32h2/src/sha/t_string.rs b/esp32h2/src/sha/t_string.rs
index db1093db4b..c533a0e0d5 100644
--- a/esp32h2/src/sha/t_string.rs
+++ b/esp32h2/src/sha/t_string.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T_STRING")
-            .field("t_string", &format_args!("{}", self.t_string().bits()))
+            .field("t_string", &self.t_string())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T_STRING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Sha t_string (used if and only if mode == SHA_512/t)."]
     #[inline(always)]
diff --git a/esp32h2/src/soc_etm/ch/evt_id.rs b/esp32h2/src/soc_etm/ch/evt_id.rs
index 0835c04224..20e43e78e9 100644
--- a/esp32h2/src/soc_etm/ch/evt_id.rs
+++ b/esp32h2/src/soc_etm/ch/evt_id.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVT_ID")
-            .field("evt_id", &format_args!("{}", self.evt_id().bits()))
+            .field("evt_id", &self.evt_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - ch0_evt_id"]
     #[inline(always)]
diff --git a/esp32h2/src/soc_etm/ch/task_id.rs b/esp32h2/src/soc_etm/ch/task_id.rs
index d59784f09b..e4f4ed148a 100644
--- a/esp32h2/src/soc_etm/ch/task_id.rs
+++ b/esp32h2/src/soc_etm/ch/task_id.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TASK_ID")
-            .field("task_id", &format_args!("{}", self.task_id().bits()))
+            .field("task_id", &self.task_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TASK_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - ch0_task_id"]
     #[inline(always)]
diff --git a/esp32h2/src/soc_etm/ch_ena_ad0.rs b/esp32h2/src/soc_etm/ch_ena_ad0.rs
index 562f39333c..00481c5e06 100644
--- a/esp32h2/src/soc_etm/ch_ena_ad0.rs
+++ b/esp32h2/src/soc_etm/ch_ena_ad0.rs
@@ -187,47 +187,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_ENA_AD0")
-            .field("ch_ena0", &format_args!("{}", self.ch_ena0().bit()))
-            .field("ch_ena1", &format_args!("{}", self.ch_ena1().bit()))
-            .field("ch_ena2", &format_args!("{}", self.ch_ena2().bit()))
-            .field("ch_ena3", &format_args!("{}", self.ch_ena3().bit()))
-            .field("ch_ena4", &format_args!("{}", self.ch_ena4().bit()))
-            .field("ch_ena5", &format_args!("{}", self.ch_ena5().bit()))
-            .field("ch_ena6", &format_args!("{}", self.ch_ena6().bit()))
-            .field("ch_ena7", &format_args!("{}", self.ch_ena7().bit()))
-            .field("ch_ena8", &format_args!("{}", self.ch_ena8().bit()))
-            .field("ch_ena9", &format_args!("{}", self.ch_ena9().bit()))
-            .field("ch_ena10", &format_args!("{}", self.ch_ena10().bit()))
-            .field("ch_ena11", &format_args!("{}", self.ch_ena11().bit()))
-            .field("ch_ena12", &format_args!("{}", self.ch_ena12().bit()))
-            .field("ch_ena13", &format_args!("{}", self.ch_ena13().bit()))
-            .field("ch_ena14", &format_args!("{}", self.ch_ena14().bit()))
-            .field("ch_ena15", &format_args!("{}", self.ch_ena15().bit()))
-            .field("ch_ena16", &format_args!("{}", self.ch_ena16().bit()))
-            .field("ch_ena17", &format_args!("{}", self.ch_ena17().bit()))
-            .field("ch_ena18", &format_args!("{}", self.ch_ena18().bit()))
-            .field("ch_ena19", &format_args!("{}", self.ch_ena19().bit()))
-            .field("ch_ena20", &format_args!("{}", self.ch_ena20().bit()))
-            .field("ch_ena21", &format_args!("{}", self.ch_ena21().bit()))
-            .field("ch_ena22", &format_args!("{}", self.ch_ena22().bit()))
-            .field("ch_ena23", &format_args!("{}", self.ch_ena23().bit()))
-            .field("ch_ena24", &format_args!("{}", self.ch_ena24().bit()))
-            .field("ch_ena25", &format_args!("{}", self.ch_ena25().bit()))
-            .field("ch_ena26", &format_args!("{}", self.ch_ena26().bit()))
-            .field("ch_ena27", &format_args!("{}", self.ch_ena27().bit()))
-            .field("ch_ena28", &format_args!("{}", self.ch_ena28().bit()))
-            .field("ch_ena29", &format_args!("{}", self.ch_ena29().bit()))
-            .field("ch_ena30", &format_args!("{}", self.ch_ena30().bit()))
-            .field("ch_ena31", &format_args!("{}", self.ch_ena31().bit()))
+            .field("ch_ena0", &self.ch_ena0())
+            .field("ch_ena1", &self.ch_ena1())
+            .field("ch_ena2", &self.ch_ena2())
+            .field("ch_ena3", &self.ch_ena3())
+            .field("ch_ena4", &self.ch_ena4())
+            .field("ch_ena5", &self.ch_ena5())
+            .field("ch_ena6", &self.ch_ena6())
+            .field("ch_ena7", &self.ch_ena7())
+            .field("ch_ena8", &self.ch_ena8())
+            .field("ch_ena9", &self.ch_ena9())
+            .field("ch_ena10", &self.ch_ena10())
+            .field("ch_ena11", &self.ch_ena11())
+            .field("ch_ena12", &self.ch_ena12())
+            .field("ch_ena13", &self.ch_ena13())
+            .field("ch_ena14", &self.ch_ena14())
+            .field("ch_ena15", &self.ch_ena15())
+            .field("ch_ena16", &self.ch_ena16())
+            .field("ch_ena17", &self.ch_ena17())
+            .field("ch_ena18", &self.ch_ena18())
+            .field("ch_ena19", &self.ch_ena19())
+            .field("ch_ena20", &self.ch_ena20())
+            .field("ch_ena21", &self.ch_ena21())
+            .field("ch_ena22", &self.ch_ena22())
+            .field("ch_ena23", &self.ch_ena23())
+            .field("ch_ena24", &self.ch_ena24())
+            .field("ch_ena25", &self.ch_ena25())
+            .field("ch_ena26", &self.ch_ena26())
+            .field("ch_ena27", &self.ch_ena27())
+            .field("ch_ena28", &self.ch_ena28())
+            .field("ch_ena29", &self.ch_ena29())
+            .field("ch_ena30", &self.ch_ena30())
+            .field("ch_ena31", &self.ch_ena31())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_ENA_AD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "ch(0-31) enable"]
     #[doc = ""]
diff --git a/esp32h2/src/soc_etm/ch_ena_ad1.rs b/esp32h2/src/soc_etm/ch_ena_ad1.rs
index 81e2dc0d87..b25116a051 100644
--- a/esp32h2/src/soc_etm/ch_ena_ad1.rs
+++ b/esp32h2/src/soc_etm/ch_ena_ad1.rs
@@ -117,33 +117,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_ENA_AD1")
-            .field("ch_ena32", &format_args!("{}", self.ch_ena32().bit()))
-            .field("ch_ena33", &format_args!("{}", self.ch_ena33().bit()))
-            .field("ch_ena34", &format_args!("{}", self.ch_ena34().bit()))
-            .field("ch_ena35", &format_args!("{}", self.ch_ena35().bit()))
-            .field("ch_ena36", &format_args!("{}", self.ch_ena36().bit()))
-            .field("ch_ena37", &format_args!("{}", self.ch_ena37().bit()))
-            .field("ch_ena38", &format_args!("{}", self.ch_ena38().bit()))
-            .field("ch_ena39", &format_args!("{}", self.ch_ena39().bit()))
-            .field("ch_ena40", &format_args!("{}", self.ch_ena40().bit()))
-            .field("ch_ena41", &format_args!("{}", self.ch_ena41().bit()))
-            .field("ch_ena42", &format_args!("{}", self.ch_ena42().bit()))
-            .field("ch_ena43", &format_args!("{}", self.ch_ena43().bit()))
-            .field("ch_ena44", &format_args!("{}", self.ch_ena44().bit()))
-            .field("ch_ena45", &format_args!("{}", self.ch_ena45().bit()))
-            .field("ch_ena46", &format_args!("{}", self.ch_ena46().bit()))
-            .field("ch_ena47", &format_args!("{}", self.ch_ena47().bit()))
-            .field("ch_ena48", &format_args!("{}", self.ch_ena48().bit()))
-            .field("ch_ena49", &format_args!("{}", self.ch_ena49().bit()))
+            .field("ch_ena32", &self.ch_ena32())
+            .field("ch_ena33", &self.ch_ena33())
+            .field("ch_ena34", &self.ch_ena34())
+            .field("ch_ena35", &self.ch_ena35())
+            .field("ch_ena36", &self.ch_ena36())
+            .field("ch_ena37", &self.ch_ena37())
+            .field("ch_ena38", &self.ch_ena38())
+            .field("ch_ena39", &self.ch_ena39())
+            .field("ch_ena40", &self.ch_ena40())
+            .field("ch_ena41", &self.ch_ena41())
+            .field("ch_ena42", &self.ch_ena42())
+            .field("ch_ena43", &self.ch_ena43())
+            .field("ch_ena44", &self.ch_ena44())
+            .field("ch_ena45", &self.ch_ena45())
+            .field("ch_ena46", &self.ch_ena46())
+            .field("ch_ena47", &self.ch_ena47())
+            .field("ch_ena48", &self.ch_ena48())
+            .field("ch_ena49", &self.ch_ena49())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_ENA_AD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "ch(32-49) enable"]
     #[doc = ""]
diff --git a/esp32h2/src/soc_etm/clk_en.rs b/esp32h2/src/soc_etm/clk_en.rs
index 5275163e95..939c6095e7 100644
--- a/esp32h2/src/soc_etm/clk_en.rs
+++ b/esp32h2/src/soc_etm/clk_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EN")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - clock enable"]
     #[inline(always)]
diff --git a/esp32h2/src/soc_etm/date.rs b/esp32h2/src/soc_etm/date.rs
index dbea0ac5e8..02f22a3bad 100644
--- a/esp32h2/src/soc_etm/date.rs
+++ b/esp32h2/src/soc_etm/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/spi0/axi_err_addr.rs b/esp32h2/src/spi0/axi_err_addr.rs
index 9561f5ebcc..cdc77ddb01 100644
--- a/esp32h2/src/spi0/axi_err_addr.rs
+++ b/esp32h2/src/spi0/axi_err_addr.rs
@@ -55,43 +55,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AXI_ERR_ADDR")
-            .field(
-                "axi_err_addr",
-                &format_args!("{}", self.axi_err_addr().bits()),
-            )
-            .field(
-                "all_fifo_empty",
-                &format_args!("{}", self.all_fifo_empty().bit()),
-            )
-            .field(
-                "spi_rdata_afifo_rempty",
-                &format_args!("{}", self.spi_rdata_afifo_rempty().bit()),
-            )
-            .field(
-                "spi_raddr_afifo_rempty",
-                &format_args!("{}", self.spi_raddr_afifo_rempty().bit()),
-            )
-            .field(
-                "spi_wdata_afifo_rempty",
-                &format_args!("{}", self.spi_wdata_afifo_rempty().bit()),
-            )
-            .field(
-                "spi_wblen_afifo_rempty",
-                &format_args!("{}", self.spi_wblen_afifo_rempty().bit()),
-            )
+            .field("axi_err_addr", &self.axi_err_addr())
+            .field("all_fifo_empty", &self.all_fifo_empty())
+            .field("spi_rdata_afifo_rempty", &self.spi_rdata_afifo_rempty())
+            .field("spi_raddr_afifo_rempty", &self.spi_raddr_afifo_rempty())
+            .field("spi_wdata_afifo_rempty", &self.spi_wdata_afifo_rempty())
+            .field("spi_wblen_afifo_rempty", &self.spi_wblen_afifo_rempty())
             .field(
                 "spi_all_axi_trans_afifo_empty",
-                &format_args!("{}", self.spi_all_axi_trans_afifo_empty().bit()),
+                &self.spi_all_axi_trans_afifo_empty(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_ERR_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 AXI request error address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_err_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AXI_ERR_ADDR_SPEC;
 impl crate::RegisterSpec for AXI_ERR_ADDR_SPEC {
diff --git a/esp32h2/src/spi0/cache_fctrl.rs b/esp32h2/src/spi0/cache_fctrl.rs
index 02807bcced..ab183e09a4 100644
--- a/esp32h2/src/spi0/cache_fctrl.rs
+++ b/esp32h2/src/spi0/cache_fctrl.rs
@@ -105,38 +105,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_FCTRL")
-            .field("axi_req_en", &format_args!("{}", self.axi_req_en().bit()))
-            .field(
-                "cache_usr_addr_4byte",
-                &format_args!("{}", self.cache_usr_addr_4byte().bit()),
-            )
-            .field(
-                "cache_flash_usr_cmd",
-                &format_args!("{}", self.cache_flash_usr_cmd().bit()),
-            )
-            .field("fdin_dual", &format_args!("{}", self.fdin_dual().bit()))
-            .field("fdout_dual", &format_args!("{}", self.fdout_dual().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("fdin_quad", &format_args!("{}", self.fdin_quad().bit()))
-            .field("fdout_quad", &format_args!("{}", self.fdout_quad().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
+            .field("axi_req_en", &self.axi_req_en())
+            .field("cache_usr_addr_4byte", &self.cache_usr_addr_4byte())
+            .field("cache_flash_usr_cmd", &self.cache_flash_usr_cmd())
+            .field("fdin_dual", &self.fdin_dual())
+            .field("fdout_dual", &self.fdout_dual())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("fdin_quad", &self.fdin_quad())
+            .field("fdout_quad", &self.fdout_quad())
+            .field("faddr_quad", &self.faddr_quad())
             .field(
                 "spi_same_aw_ar_addr_chk_en",
-                &format_args!("{}", self.spi_same_aw_ar_addr_chk_en().bit()),
-            )
-            .field(
-                "spi_close_axi_inf_en",
-                &format_args!("{}", self.spi_close_axi_inf_en().bit()),
+                &self.spi_same_aw_ar_addr_chk_en(),
             )
+            .field("spi_close_axi_inf_en", &self.spi_close_axi_inf_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_FCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - For SPI0, AXI master access enable, 1: enable, 0:disable."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/cache_sctrl.rs b/esp32h2/src/spi0/cache_sctrl.rs
index f1dd755783..62f6a51682 100644
--- a/esp32h2/src/spi0/cache_sctrl.rs
+++ b/esp32h2/src/spi0/cache_sctrl.rs
@@ -83,56 +83,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_SCTRL")
-            .field(
-                "cache_usr_saddr_4byte",
-                &format_args!("{}", self.cache_usr_saddr_4byte().bit()),
-            )
-            .field(
-                "usr_sram_dio",
-                &format_args!("{}", self.usr_sram_dio().bit()),
-            )
-            .field(
-                "usr_sram_qio",
-                &format_args!("{}", self.usr_sram_qio().bit()),
-            )
-            .field(
-                "usr_wr_sram_dummy",
-                &format_args!("{}", self.usr_wr_sram_dummy().bit()),
-            )
-            .field(
-                "usr_rd_sram_dummy",
-                &format_args!("{}", self.usr_rd_sram_dummy().bit()),
-            )
-            .field(
-                "cache_sram_usr_rcmd",
-                &format_args!("{}", self.cache_sram_usr_rcmd().bit()),
-            )
-            .field(
-                "sram_rdummy_cyclelen",
-                &format_args!("{}", self.sram_rdummy_cyclelen().bits()),
-            )
-            .field(
-                "sram_addr_bitlen",
-                &format_args!("{}", self.sram_addr_bitlen().bits()),
-            )
-            .field(
-                "cache_sram_usr_wcmd",
-                &format_args!("{}", self.cache_sram_usr_wcmd().bit()),
-            )
-            .field("sram_oct", &format_args!("{}", self.sram_oct().bit()))
-            .field(
-                "sram_wdummy_cyclelen",
-                &format_args!("{}", self.sram_wdummy_cyclelen().bits()),
-            )
+            .field("cache_usr_saddr_4byte", &self.cache_usr_saddr_4byte())
+            .field("usr_sram_dio", &self.usr_sram_dio())
+            .field("usr_sram_qio", &self.usr_sram_qio())
+            .field("usr_wr_sram_dummy", &self.usr_wr_sram_dummy())
+            .field("usr_rd_sram_dummy", &self.usr_rd_sram_dummy())
+            .field("cache_sram_usr_rcmd", &self.cache_sram_usr_rcmd())
+            .field("sram_rdummy_cyclelen", &self.sram_rdummy_cyclelen())
+            .field("sram_addr_bitlen", &self.sram_addr_bitlen())
+            .field("cache_sram_usr_wcmd", &self.cache_sram_usr_wcmd())
+            .field("sram_oct", &self.sram_oct())
+            .field("sram_wdummy_cyclelen", &self.sram_wdummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_SCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 external RAM control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_sctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_SCTRL_SPEC;
 impl crate::RegisterSpec for CACHE_SCTRL_SPEC {
diff --git a/esp32h2/src/spi0/clock.rs b/esp32h2/src/spi0/clock.rs
index e44e658046..5adc5d874b 100644
--- a/esp32h2/src/spi0/clock.rs
+++ b/esp32h2/src/spi0/clock.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/clock_gate.rs b/esp32h2/src/spi0/clock_gate.rs
index 9e3dcbf652..eede18e876 100644
--- a/esp32h2/src/spi0/clock_gate.rs
+++ b/esp32h2/src/spi0/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("spi_clk_en", &format_args!("{}", self.spi_clk_en().bit()))
+            .field("spi_clk_en", &self.spi_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/cmd.rs b/esp32h2/src/spi0/cmd.rs
index 668e900c12..1b01eda873 100644
--- a/esp32h2/src/spi0/cmd.rs
+++ b/esp32h2/src/spi0/cmd.rs
@@ -27,18 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("mst_st", &format_args!("{}", self.mst_st().bits()))
-            .field("slv_st", &format_args!("{}", self.slv_st().bits()))
-            .field("usr", &format_args!("{}", self.usr().bit()))
+            .field("mst_st", &self.mst_st())
+            .field("slv_st", &self.slv_st())
+            .field("usr", &self.usr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 FSM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CMD_SPEC;
 impl crate::RegisterSpec for CMD_SPEC {
diff --git a/esp32h2/src/spi0/ctrl.rs b/esp32h2/src/spi0/ctrl.rs
index 63b351dd2a..4301347f6d 100644
--- a/esp32h2/src/spi0/ctrl.rs
+++ b/esp32h2/src/spi0/ctrl.rs
@@ -167,46 +167,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field(
-                "wdummy_dqs_always_out",
-                &format_args!("{}", self.wdummy_dqs_always_out().bit()),
-            )
-            .field(
-                "wdummy_always_out",
-                &format_args!("{}", self.wdummy_always_out().bit()),
-            )
-            .field("fdummy_rin", &format_args!("{}", self.fdummy_rin().bit()))
-            .field("fdummy_wout", &format_args!("{}", self.fdummy_wout().bit()))
-            .field("fdout_oct", &format_args!("{}", self.fdout_oct().bit()))
-            .field("fdin_oct", &format_args!("{}", self.fdin_oct().bit()))
-            .field("faddr_oct", &format_args!("{}", self.faddr_oct().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcmd_oct", &format_args!("{}", self.fcmd_oct().bit()))
-            .field("fastrd_mode", &format_args!("{}", self.fastrd_mode().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("wp", &format_args!("{}", self.wp().bit()))
-            .field("fread_dio", &format_args!("{}", self.fread_dio().bit()))
-            .field("fread_qio", &format_args!("{}", self.fread_qio().bit()))
-            .field(
-                "dqs_ie_always_on",
-                &format_args!("{}", self.dqs_ie_always_on().bit()),
-            )
-            .field(
-                "data_ie_always_on",
-                &format_args!("{}", self.data_ie_always_on().bit()),
-            )
+            .field("wdummy_dqs_always_out", &self.wdummy_dqs_always_out())
+            .field("wdummy_always_out", &self.wdummy_always_out())
+            .field("fdummy_rin", &self.fdummy_rin())
+            .field("fdummy_wout", &self.fdummy_wout())
+            .field("fdout_oct", &self.fdout_oct())
+            .field("fdin_oct", &self.fdin_oct())
+            .field("faddr_oct", &self.faddr_oct())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcmd_oct", &self.fcmd_oct())
+            .field("fastrd_mode", &self.fastrd_mode())
+            .field("fread_dual", &self.fread_dual())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("fread_quad", &self.fread_quad())
+            .field("wp", &self.wp())
+            .field("fread_dio", &self.fread_dio())
+            .field("fread_qio", &self.fread_qio())
+            .field("dqs_ie_always_on", &self.dqs_ie_always_on())
+            .field("data_ie_always_on", &self.data_ie_always_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO\\[7:0\\] is output by the MSPI controller."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/ctrl1.rs b/esp32h2/src/spi0/ctrl1.rs
index b7851d168e..01095aee39 100644
--- a/esp32h2/src/spi0/ctrl1.rs
+++ b/esp32h2/src/spi0/ctrl1.rs
@@ -92,46 +92,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL1")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
+            .field("clk_mode", &self.clk_mode())
             .field(
                 "spi_ar_size0_1_support_en",
-                &format_args!("{}", self.spi_ar_size0_1_support_en().bit()),
+                &self.spi_ar_size0_1_support_en(),
             )
             .field(
                 "spi_aw_size0_1_support_en",
-                &format_args!("{}", self.spi_aw_size0_1_support_en().bit()),
-            )
-            .field(
-                "spi_axi_rdata_back_fast",
-                &format_args!("{}", self.spi_axi_rdata_back_fast().bit()),
-            )
-            .field(
-                "rresp_ecc_err_en",
-                &format_args!("{}", self.rresp_ecc_err_en().bit()),
-            )
-            .field(
-                "ar_splice_en",
-                &format_args!("{}", self.ar_splice_en().bit()),
-            )
-            .field(
-                "aw_splice_en",
-                &format_args!("{}", self.aw_splice_en().bit()),
-            )
-            .field("ram0_en", &format_args!("{}", self.ram0_en().bit()))
-            .field("dual_ram_en", &format_args!("{}", self.dual_ram_en().bit()))
-            .field(
-                "fast_write_en",
-                &format_args!("{}", self.fast_write_en().bit()),
+                &self.spi_aw_size0_1_support_en(),
             )
+            .field("spi_axi_rdata_back_fast", &self.spi_axi_rdata_back_fast())
+            .field("rresp_ecc_err_en", &self.rresp_ecc_err_en())
+            .field("ar_splice_en", &self.ar_splice_en())
+            .field("aw_splice_en", &self.aw_splice_en())
+            .field("ram0_en", &self.ram0_en())
+            .field("dual_ram_en", &self.dual_ram_en())
+            .field("fast_write_en", &self.fast_write_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/ctrl2.rs b/esp32h2/src/spi0/ctrl2.rs
index 40825c52ab..3792399b33 100644
--- a/esp32h2/src/spi0/ctrl2.rs
+++ b/esp32h2/src/spi0/ctrl2.rs
@@ -65,43 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field(
-                "cs_setup_time",
-                &format_args!("{}", self.cs_setup_time().bits()),
-            )
-            .field(
-                "cs_hold_time",
-                &format_args!("{}", self.cs_hold_time().bits()),
-            )
-            .field(
-                "ecc_cs_hold_time",
-                &format_args!("{}", self.ecc_cs_hold_time().bits()),
-            )
-            .field(
-                "ecc_skip_page_corner",
-                &format_args!("{}", self.ecc_skip_page_corner().bit()),
-            )
-            .field(
-                "ecc_16to18_byte_en",
-                &format_args!("{}", self.ecc_16to18_byte_en().bit()),
-            )
-            .field(
-                "split_trans_en",
-                &format_args!("{}", self.split_trans_en().bit()),
-            )
-            .field(
-                "cs_hold_delay",
-                &format_args!("{}", self.cs_hold_delay().bits()),
-            )
+            .field("cs_setup_time", &self.cs_setup_time())
+            .field("cs_hold_time", &self.cs_hold_time())
+            .field("ecc_cs_hold_time", &self.ecc_cs_hold_time())
+            .field("ecc_skip_page_corner", &self.ecc_skip_page_corner())
+            .field("ecc_16to18_byte_en", &self.ecc_16to18_byte_en())
+            .field("split_trans_en", &self.split_trans_en())
+            .field("cs_hold_delay", &self.cs_hold_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/date.rs b/esp32h2/src/spi0/date.rs
index 389e77e677..a96e4beb1b 100644
--- a/esp32h2/src/spi0/date.rs
+++ b/esp32h2/src/spi0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/spi0/ddr.rs b/esp32h2/src/spi0/ddr.rs
index 2a5f5afdb2..f57439109f 100644
--- a/esp32h2/src/spi0/ddr.rs
+++ b/esp32h2/src/spi0/ddr.rs
@@ -118,79 +118,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DDR")
-            .field(
-                "spi_fmem_ddr_en",
-                &format_args!("{}", self.spi_fmem_ddr_en().bit()),
-            )
-            .field(
-                "spi_fmem_var_dummy",
-                &format_args!("{}", self.spi_fmem_var_dummy().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_rdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_rdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_wdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_wdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_cmd_dis",
-                &format_args!("{}", self.spi_fmem_ddr_cmd_dis().bit()),
-            )
-            .field(
-                "spi_fmem_outminbytelen",
-                &format_args!("{}", self.spi_fmem_outminbytelen().bits()),
-            )
-            .field(
-                "spi_fmem_tx_ddr_msk_en",
-                &format_args!("{}", self.spi_fmem_tx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_fmem_rx_ddr_msk_en",
-                &format_args!("{}", self.spi_fmem_rx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_fmem_usr_ddr_dqs_thd",
-                &format_args!("{}", self.spi_fmem_usr_ddr_dqs_thd().bits()),
-            )
-            .field(
-                "spi_fmem_ddr_dqs_loop",
-                &format_args!("{}", self.spi_fmem_ddr_dqs_loop().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_en",
-                &format_args!("{}", self.spi_fmem_clk_diff_en().bit()),
-            )
-            .field(
-                "spi_fmem_dqs_ca_in",
-                &format_args!("{}", self.spi_fmem_dqs_ca_in().bit()),
-            )
+            .field("spi_fmem_ddr_en", &self.spi_fmem_ddr_en())
+            .field("spi_fmem_var_dummy", &self.spi_fmem_var_dummy())
+            .field("spi_fmem_ddr_rdat_swp", &self.spi_fmem_ddr_rdat_swp())
+            .field("spi_fmem_ddr_wdat_swp", &self.spi_fmem_ddr_wdat_swp())
+            .field("spi_fmem_ddr_cmd_dis", &self.spi_fmem_ddr_cmd_dis())
+            .field("spi_fmem_outminbytelen", &self.spi_fmem_outminbytelen())
+            .field("spi_fmem_tx_ddr_msk_en", &self.spi_fmem_tx_ddr_msk_en())
+            .field("spi_fmem_rx_ddr_msk_en", &self.spi_fmem_rx_ddr_msk_en())
+            .field("spi_fmem_usr_ddr_dqs_thd", &self.spi_fmem_usr_ddr_dqs_thd())
+            .field("spi_fmem_ddr_dqs_loop", &self.spi_fmem_ddr_dqs_loop())
+            .field("spi_fmem_clk_diff_en", &self.spi_fmem_clk_diff_en())
+            .field("spi_fmem_dqs_ca_in", &self.spi_fmem_dqs_ca_in())
             .field(
                 "spi_fmem_hyperbus_dummy_2x",
-                &format_args!("{}", self.spi_fmem_hyperbus_dummy_2x().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_inv",
-                &format_args!("{}", self.spi_fmem_clk_diff_inv().bit()),
-            )
-            .field(
-                "spi_fmem_octa_ram_addr",
-                &format_args!("{}", self.spi_fmem_octa_ram_addr().bit()),
-            )
-            .field(
-                "spi_fmem_hyperbus_ca",
-                &format_args!("{}", self.spi_fmem_hyperbus_ca().bit()),
+                &self.spi_fmem_hyperbus_dummy_2x(),
             )
+            .field("spi_fmem_clk_diff_inv", &self.spi_fmem_clk_diff_inv())
+            .field("spi_fmem_octa_ram_addr", &self.spi_fmem_octa_ram_addr())
+            .field("spi_fmem_hyperbus_ca", &self.spi_fmem_hyperbus_ca())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 flash DDR mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DDR_SPEC;
 impl crate::RegisterSpec for DDR_SPEC {
diff --git a/esp32h2/src/spi0/din_mode.rs b/esp32h2/src/spi0/din_mode.rs
index 90d7b5a3fd..dfc428573f 100644
--- a/esp32h2/src/spi0/din_mode.rs
+++ b/esp32h2/src/spi0/din_mode.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_MODE")
-            .field("din0_mode", &format_args!("{}", self.din0_mode().bits()))
-            .field("din1_mode", &format_args!("{}", self.din1_mode().bits()))
-            .field("din2_mode", &format_args!("{}", self.din2_mode().bits()))
-            .field("din3_mode", &format_args!("{}", self.din3_mode().bits()))
-            .field("din4_mode", &format_args!("{}", self.din4_mode().bits()))
-            .field("din5_mode", &format_args!("{}", self.din5_mode().bits()))
-            .field("din6_mode", &format_args!("{}", self.din6_mode().bits()))
-            .field("din7_mode", &format_args!("{}", self.din7_mode().bits()))
-            .field("dins_mode", &format_args!("{}", self.dins_mode().bits()))
+            .field("din0_mode", &self.din0_mode())
+            .field("din1_mode", &self.din1_mode())
+            .field("din2_mode", &self.din2_mode())
+            .field("din3_mode", &self.din3_mode())
+            .field("din4_mode", &self.din4_mode())
+            .field("din5_mode", &self.din5_mode())
+            .field("din6_mode", &self.din6_mode())
+            .field("din7_mode", &self.din7_mode())
+            .field("dins_mode", &self.dins_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/din_num.rs b/esp32h2/src/spi0/din_num.rs
index 2ee1addcc8..e349d63599 100644
--- a/esp32h2/src/spi0/din_num.rs
+++ b/esp32h2/src/spi0/din_num.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_NUM")
-            .field("din0_num", &format_args!("{}", self.din0_num().bits()))
-            .field("din1_num", &format_args!("{}", self.din1_num().bits()))
-            .field("din2_num", &format_args!("{}", self.din2_num().bits()))
-            .field("din3_num", &format_args!("{}", self.din3_num().bits()))
-            .field("din4_num", &format_args!("{}", self.din4_num().bits()))
-            .field("din5_num", &format_args!("{}", self.din5_num().bits()))
-            .field("din6_num", &format_args!("{}", self.din6_num().bits()))
-            .field("din7_num", &format_args!("{}", self.din7_num().bits()))
-            .field("dins_num", &format_args!("{}", self.dins_num().bits()))
+            .field("din0_num", &self.din0_num())
+            .field("din1_num", &self.din1_num())
+            .field("din2_num", &self.din2_num())
+            .field("din3_num", &self.din3_num())
+            .field("din4_num", &self.din4_num())
+            .field("din5_num", &self.din5_num())
+            .field("din6_num", &self.din6_num())
+            .field("din7_num", &self.din7_num())
+            .field("dins_num", &self.dins_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/dout_mode.rs b/esp32h2/src/spi0/dout_mode.rs
index fa50bdd69a..e426b2bf23 100644
--- a/esp32h2/src/spi0/dout_mode.rs
+++ b/esp32h2/src/spi0/dout_mode.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOUT_MODE")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bit()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bit()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bit()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bit()))
-            .field("dout4_mode", &format_args!("{}", self.dout4_mode().bit()))
-            .field("dout5_mode", &format_args!("{}", self.dout5_mode().bit()))
-            .field("dout6_mode", &format_args!("{}", self.dout6_mode().bit()))
-            .field("dout7_mode", &format_args!("{}", self.dout7_mode().bit()))
-            .field("douts_mode", &format_args!("{}", self.douts_mode().bit()))
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
+            .field("dout4_mode", &self.dout4_mode())
+            .field("dout5_mode", &self.dout5_mode())
+            .field("dout6_mode", &self.dout6_mode())
+            .field("dout7_mode", &self.dout7_mode())
+            .field("douts_mode", &self.douts_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/dpa_ctrl.rs b/esp32h2/src/spi0/dpa_ctrl.rs
index 36adf8a2a3..aea7e042b7 100644
--- a/esp32h2/src/spi0/dpa_ctrl.rs
+++ b/esp32h2/src/spi0/dpa_ctrl.rs
@@ -35,27 +35,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPA_CTRL")
-            .field(
-                "spi_crypt_security_level",
-                &format_args!("{}", self.spi_crypt_security_level().bits()),
-            )
-            .field(
-                "spi_crypt_calc_d_dpa_en",
-                &format_args!("{}", self.spi_crypt_calc_d_dpa_en().bit()),
-            )
+            .field("spi_crypt_security_level", &self.spi_crypt_security_level())
+            .field("spi_crypt_calc_d_dpa_en", &self.spi_crypt_calc_d_dpa_en())
             .field(
                 "spi_crypt_dpa_select_register",
-                &format_args!("{}", self.spi_crypt_dpa_select_register().bit()),
+                &self.spi_crypt_dpa_select_register(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPA_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)"]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/ecc_ctrl.rs b/esp32h2/src/spi0/ecc_ctrl.rs
index cd96e78e81..522907e1ab 100644
--- a/esp32h2/src/spi0/ecc_ctrl.rs
+++ b/esp32h2/src/spi0/ecc_ctrl.rs
@@ -59,43 +59,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_CTRL")
-            .field(
-                "spi_fmem_ecc_err_int_num",
-                &format_args!("{}", self.spi_fmem_ecc_err_int_num().bits()),
-            )
-            .field(
-                "spi_fmem_ecc_err_int_en",
-                &format_args!("{}", self.spi_fmem_ecc_err_int_en().bit()),
-            )
-            .field(
-                "spi_fmem_page_size",
-                &format_args!("{}", self.spi_fmem_page_size().bits()),
-            )
-            .field(
-                "spi_fmem_ecc_addr_en",
-                &format_args!("{}", self.spi_fmem_ecc_addr_en().bit()),
-            )
-            .field(
-                "usr_ecc_addr_en",
-                &format_args!("{}", self.usr_ecc_addr_en().bit()),
-            )
+            .field("spi_fmem_ecc_err_int_num", &self.spi_fmem_ecc_err_int_num())
+            .field("spi_fmem_ecc_err_int_en", &self.spi_fmem_ecc_err_int_en())
+            .field("spi_fmem_page_size", &self.spi_fmem_page_size())
+            .field("spi_fmem_ecc_addr_en", &self.spi_fmem_ecc_addr_en())
+            .field("usr_ecc_addr_en", &self.usr_ecc_addr_en())
             .field(
                 "ecc_continue_record_err_en",
-                &format_args!("{}", self.ecc_continue_record_err_en().bit()),
-            )
-            .field(
-                "ecc_err_bits",
-                &format_args!("{}", self.ecc_err_bits().bits()),
+                &self.ecc_continue_record_err_en(),
             )
+            .field("ecc_err_bits", &self.ecc_err_bits())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 18:19 - Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/ecc_err_addr.rs b/esp32h2/src/spi0/ecc_err_addr.rs
index 1ddfb7145a..f5450cb8be 100644
--- a/esp32h2/src/spi0/ecc_err_addr.rs
+++ b/esp32h2/src/spi0/ecc_err_addr.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_ERR_ADDR")
-            .field(
-                "ecc_err_addr",
-                &format_args!("{}", self.ecc_err_addr().bits()),
-            )
-            .field(
-                "ecc_err_cnt",
-                &format_args!("{}", self.ecc_err_cnt().bits()),
-            )
+            .field("ecc_err_addr", &self.ecc_err_addr())
+            .field("ecc_err_cnt", &self.ecc_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_ERR_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI ECC error address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecc_err_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ECC_ERR_ADDR_SPEC;
 impl crate::RegisterSpec for ECC_ERR_ADDR_SPEC {
diff --git a/esp32h2/src/spi0/fsm.rs b/esp32h2/src/spi0/fsm.rs
index 54045ebf4f..ed0f815e8e 100644
--- a/esp32h2/src/spi0/fsm.rs
+++ b/esp32h2/src/spi0/fsm.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM")
-            .field(
-                "lock_delay_time",
-                &format_args!("{}", self.lock_delay_time().bits()),
-            )
+            .field("lock_delay_time", &self.lock_delay_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 7:11 - The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/int_clr.rs b/esp32h2/src/spi0/int_clr.rs
index c0fba58847..9bec767d37 100644
--- a/esp32h2/src/spi0/int_clr.rs
+++ b/esp32h2/src/spi0/int_clr.rs
@@ -37,24 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_CLR")
-            .field("ecc_err", &format_args!("{}", self.ecc_err().bit()))
-            .field(
-                "axi_wr_flash_err",
-                &format_args!("{}", self.axi_wr_flash_err().bit()),
-            )
-            .field(
-                "axi_waddr_err",
-                &format_args!("{}", self.axi_waddr_err().bit()),
-            )
+            .field("ecc_err", &self.ecc_err())
+            .field("axi_wr_flash_err", &self.axi_wr_flash_err())
+            .field("axi_waddr_err", &self.axi_waddr_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - The clear bit for SPI_MEM_SLV_ST_END_INT interrupt."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/int_ena.rs b/esp32h2/src/spi0/int_ena.rs
index f284bcdab8..5abefbc3e8 100644
--- a/esp32h2/src/spi0/int_ena.rs
+++ b/esp32h2/src/spi0/int_ena.rs
@@ -65,31 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("ecc_err", &format_args!("{}", self.ecc_err().bit()))
-            .field("pms_reject", &format_args!("{}", self.pms_reject().bit()))
-            .field(
-                "axi_raddr_err",
-                &format_args!("{}", self.axi_raddr_err().bit()),
-            )
-            .field(
-                "axi_wr_flash_err",
-                &format_args!("{}", self.axi_wr_flash_err().bit()),
-            )
-            .field(
-                "axi_waddr_err_int__ena",
-                &format_args!("{}", self.axi_waddr_err_int__ena().bit()),
-            )
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("ecc_err", &self.ecc_err())
+            .field("pms_reject", &self.pms_reject())
+            .field("axi_raddr_err", &self.axi_raddr_err())
+            .field("axi_wr_flash_err", &self.axi_wr_flash_err())
+            .field("axi_waddr_err_int__ena", &self.axi_waddr_err_int__ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/int_raw.rs b/esp32h2/src/spi0/int_raw.rs
index 3f1a3ac78d..7343156220 100644
--- a/esp32h2/src/spi0/int_raw.rs
+++ b/esp32h2/src/spi0/int_raw.rs
@@ -65,31 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("ecc_err", &format_args!("{}", self.ecc_err().bit()))
-            .field("pms_reject", &format_args!("{}", self.pms_reject().bit()))
-            .field(
-                "axi_raddr_err",
-                &format_args!("{}", self.axi_raddr_err().bit()),
-            )
-            .field(
-                "axi_wr_flash_err",
-                &format_args!("{}", self.axi_wr_flash_err().bit()),
-            )
-            .field(
-                "axi_waddr_err",
-                &format_args!("{}", self.axi_waddr_err().bit()),
-            )
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("ecc_err", &self.ecc_err())
+            .field("pms_reject", &self.pms_reject())
+            .field("axi_raddr_err", &self.axi_raddr_err())
+            .field("axi_wr_flash_err", &self.axi_wr_flash_err())
+            .field("axi_waddr_err", &self.axi_waddr_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/int_st.rs b/esp32h2/src/spi0/int_st.rs
index 5ef07ec7f3..cb894ae699 100644
--- a/esp32h2/src/spi0/int_st.rs
+++ b/esp32h2/src/spi0/int_st.rs
@@ -55,31 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("ecc_err", &format_args!("{}", self.ecc_err().bit()))
-            .field("pms_reject", &format_args!("{}", self.pms_reject().bit()))
-            .field(
-                "axi_raddr_err",
-                &format_args!("{}", self.axi_raddr_err().bit()),
-            )
-            .field(
-                "axi_wr_flash_err",
-                &format_args!("{}", self.axi_wr_flash_err().bit()),
-            )
-            .field(
-                "axi_waddr_err",
-                &format_args!("{}", self.axi_waddr_err().bit()),
-            )
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("ecc_err", &self.ecc_err())
+            .field("pms_reject", &self.pms_reject())
+            .field("axi_raddr_err", &self.axi_raddr_err())
+            .field("axi_wr_flash_err", &self.axi_wr_flash_err())
+            .field("axi_waddr_err", &self.axi_waddr_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/spi0/misc.rs b/esp32h2/src/spi0/misc.rs
index b421faf0c1..f87ca4dc57 100644
--- a/esp32h2/src/spi0/misc.rs
+++ b/esp32h2/src/spi0/misc.rs
@@ -40,25 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("fsub_pin", &format_args!("{}", self.fsub_pin().bit()))
-            .field("ssub_pin", &format_args!("{}", self.ssub_pin().bit()))
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
+            .field("fsub_pin", &self.fsub_pin())
+            .field("ssub_pin", &self.ssub_pin())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - 1: SPI_CLK line is high when idle 0: spi clk line is low when idle"]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/mmu_item_content.rs b/esp32h2/src/spi0/mmu_item_content.rs
index 543a1fc5db..a3898f8b78 100644
--- a/esp32h2/src/spi0/mmu_item_content.rs
+++ b/esp32h2/src/spi0/mmu_item_content.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MMU_ITEM_CONTENT")
-            .field(
-                "spi_mmu_item_content",
-                &format_args!("{}", self.spi_mmu_item_content().bits()),
-            )
+            .field("spi_mmu_item_content", &self.spi_mmu_item_content())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MMU_ITEM_CONTENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - MSPI-MMU item content"]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/mmu_item_index.rs b/esp32h2/src/spi0/mmu_item_index.rs
index 9b421e3af3..3cdaed760f 100644
--- a/esp32h2/src/spi0/mmu_item_index.rs
+++ b/esp32h2/src/spi0/mmu_item_index.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MMU_ITEM_INDEX")
-            .field(
-                "spi_mmu_item_index",
-                &format_args!("{}", self.spi_mmu_item_index().bits()),
-            )
+            .field("spi_mmu_item_index", &self.spi_mmu_item_index())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MMU_ITEM_INDEX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - MSPI-MMU item index"]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/mmu_power_ctrl.rs b/esp32h2/src/spi0/mmu_power_ctrl.rs
index 83302e4c4e..8b461b6042 100644
--- a/esp32h2/src/spi0/mmu_power_ctrl.rs
+++ b/esp32h2/src/spi0/mmu_power_ctrl.rs
@@ -65,34 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MMU_POWER_CTRL")
-            .field(
-                "spi_mmu_mem_force_on",
-                &format_args!("{}", self.spi_mmu_mem_force_on().bit()),
-            )
-            .field(
-                "spi_mmu_mem_force_pd",
-                &format_args!("{}", self.spi_mmu_mem_force_pd().bit()),
-            )
-            .field(
-                "spi_mmu_mem_force_pu",
-                &format_args!("{}", self.spi_mmu_mem_force_pu().bit()),
-            )
-            .field(
-                "spi_mmu_page_size",
-                &format_args!("{}", self.spi_mmu_page_size().bits()),
-            )
-            .field("aux_ctrl", &format_args!("{}", self.aux_ctrl().bits()))
-            .field("rdn_ena", &format_args!("{}", self.rdn_ena().bit()))
-            .field("rdn_result", &format_args!("{}", self.rdn_result().bit()))
+            .field("spi_mmu_mem_force_on", &self.spi_mmu_mem_force_on())
+            .field("spi_mmu_mem_force_pd", &self.spi_mmu_mem_force_pd())
+            .field("spi_mmu_mem_force_pu", &self.spi_mmu_mem_force_pu())
+            .field("spi_mmu_page_size", &self.spi_mmu_page_size())
+            .field("aux_ctrl", &self.aux_ctrl())
+            .field("rdn_ena", &self.rdn_ena())
+            .field("rdn_result", &self.rdn_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MMU_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable mmu-memory clock force on"]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/pms_reject.rs b/esp32h2/src/spi0/pms_reject.rs
index db8ec870f6..bcf8e5de2b 100644
--- a/esp32h2/src/spi0/pms_reject.rs
+++ b/esp32h2/src/spi0/pms_reject.rs
@@ -52,27 +52,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMS_REJECT")
-            .field(
-                "reject_addr",
-                &format_args!("{}", self.reject_addr().bits()),
-            )
-            .field("pm_en", &format_args!("{}", self.pm_en().bit()))
-            .field("pms_ld", &format_args!("{}", self.pms_ld().bit()))
-            .field("pms_st", &format_args!("{}", self.pms_st().bit()))
-            .field(
-                "pms_multi_hit",
-                &format_args!("{}", self.pms_multi_hit().bit()),
-            )
-            .field("pms_ivd", &format_args!("{}", self.pms_ivd().bit()))
+            .field("reject_addr", &self.reject_addr())
+            .field("pm_en", &self.pm_en())
+            .field("pms_ld", &self.pms_ld())
+            .field("pms_st", &self.pms_st())
+            .field("pms_multi_hit", &self.pms_multi_hit())
+            .field("pms_ivd", &self.pms_ivd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMS_REJECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - Set this bit to enable SPI0/1 transfer permission control function."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/rd_status.rs b/esp32h2/src/spi0/rd_status.rs
index f0916ef916..ce4af380ee 100644
--- a/esp32h2/src/spi0/rd_status.rs
+++ b/esp32h2/src/spi0/rd_status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_STATUS")
-            .field("wb_mode", &format_args!("{}", self.wb_mode().bits()))
+            .field("wb_mode", &self.wb_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:23 - Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/registerrnd_eco_high.rs b/esp32h2/src/spi0/registerrnd_eco_high.rs
index a9db8065fc..6ff3607a30 100644
--- a/esp32h2/src/spi0/registerrnd_eco_high.rs
+++ b/esp32h2/src/spi0/registerrnd_eco_high.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGISTERRND_ECO_HIGH")
-            .field(
-                "registerrnd_eco_high",
-                &format_args!("{}", self.registerrnd_eco_high().bits()),
-            )
+            .field("registerrnd_eco_high", &self.registerrnd_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGISTERRND_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI ECO high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`registerrnd_eco_high::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REGISTERRND_ECO_HIGH_SPEC;
 impl crate::RegisterSpec for REGISTERRND_ECO_HIGH_SPEC {
diff --git a/esp32h2/src/spi0/registerrnd_eco_low.rs b/esp32h2/src/spi0/registerrnd_eco_low.rs
index 1486744d81..bcf399dab2 100644
--- a/esp32h2/src/spi0/registerrnd_eco_low.rs
+++ b/esp32h2/src/spi0/registerrnd_eco_low.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGISTERRND_ECO_LOW")
-            .field(
-                "registerrnd_eco_low",
-                &format_args!("{}", self.registerrnd_eco_low().bits()),
-            )
+            .field("registerrnd_eco_low", &self.registerrnd_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGISTERRND_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI ECO low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`registerrnd_eco_low::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REGISTERRND_ECO_LOW_SPEC;
 impl crate::RegisterSpec for REGISTERRND_ECO_LOW_SPEC {
diff --git a/esp32h2/src/spi0/spi_fmem_pms_addr.rs b/esp32h2/src/spi0/spi_fmem_pms_addr.rs
index 42fdc3fef2..0722040416 100644
--- a/esp32h2/src/spi0/spi_fmem_pms_addr.rs
+++ b/esp32h2/src/spi0/spi_fmem_pms_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_FMEM_PMS_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_FMEM_PMS_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - SPI1 flash ACE section %s start address value"]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/spi_fmem_pms_attr.rs b/esp32h2/src/spi0/spi_fmem_pms_attr.rs
index 5d9eb0f37f..f4c7afcc2b 100644
--- a/esp32h2/src/spi0/spi_fmem_pms_attr.rs
+++ b/esp32h2/src/spi0/spi_fmem_pms_attr.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_FMEM_PMS_ATTR")
-            .field(
-                "spi_fmem_pms_rd_attr",
-                &format_args!("{}", self.spi_fmem_pms_rd_attr().bit()),
-            )
-            .field(
-                "spi_fmem_pms_wr_attr",
-                &format_args!("{}", self.spi_fmem_pms_wr_attr().bit()),
-            )
-            .field(
-                "spi_fmem_pms_ecc",
-                &format_args!("{}", self.spi_fmem_pms_ecc().bit()),
-            )
+            .field("spi_fmem_pms_rd_attr", &self.spi_fmem_pms_rd_attr())
+            .field("spi_fmem_pms_wr_attr", &self.spi_fmem_pms_wr_attr())
+            .field("spi_fmem_pms_ecc", &self.spi_fmem_pms_ecc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_FMEM_PMS_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: SPI1 flash ACE section %s read accessible. 0: Not allowed."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/spi_fmem_pms_size.rs b/esp32h2/src/spi0/spi_fmem_pms_size.rs
index e0755a7a1a..a159e5b088 100644
--- a/esp32h2/src/spi0/spi_fmem_pms_size.rs
+++ b/esp32h2/src/spi0/spi_fmem_pms_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_FMEM_PMS_SIZE")
-            .field(
-                "spi_fmem_pms_size",
-                &format_args!("{}", self.spi_fmem_pms_size().bits()),
-            )
+            .field("spi_fmem_pms_size", &self.spi_fmem_pms_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_FMEM_PMS_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - SPI1 flash ACE section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE)"]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/spi_smem_ac.rs b/esp32h2/src/spi0/spi_smem_ac.rs
index 3c2ce3350a..ca29407860 100644
--- a/esp32h2/src/spi0/spi_smem_ac.rs
+++ b/esp32h2/src/spi0/spi_smem_ac.rs
@@ -69,51 +69,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_AC")
-            .field(
-                "spi_smem_cs_setup",
-                &format_args!("{}", self.spi_smem_cs_setup().bit()),
-            )
-            .field(
-                "spi_smem_cs_hold",
-                &format_args!("{}", self.spi_smem_cs_hold().bit()),
-            )
-            .field(
-                "spi_smem_cs_setup_time",
-                &format_args!("{}", self.spi_smem_cs_setup_time().bits()),
-            )
-            .field(
-                "spi_smem_cs_hold_time",
-                &format_args!("{}", self.spi_smem_cs_hold_time().bits()),
-            )
+            .field("spi_smem_cs_setup", &self.spi_smem_cs_setup())
+            .field("spi_smem_cs_hold", &self.spi_smem_cs_hold())
+            .field("spi_smem_cs_setup_time", &self.spi_smem_cs_setup_time())
+            .field("spi_smem_cs_hold_time", &self.spi_smem_cs_hold_time())
             .field(
                 "spi_smem_ecc_cs_hold_time",
-                &format_args!("{}", self.spi_smem_ecc_cs_hold_time().bits()),
+                &self.spi_smem_ecc_cs_hold_time(),
             )
             .field(
                 "spi_smem_ecc_skip_page_corner",
-                &format_args!("{}", self.spi_smem_ecc_skip_page_corner().bit()),
+                &self.spi_smem_ecc_skip_page_corner(),
             )
             .field(
                 "spi_smem_ecc_16to18_byte_en",
-                &format_args!("{}", self.spi_smem_ecc_16to18_byte_en().bit()),
-            )
-            .field(
-                "spi_smem_cs_hold_delay",
-                &format_args!("{}", self.spi_smem_cs_hold_delay().bits()),
-            )
-            .field(
-                "spi_smem_split_trans_en",
-                &format_args!("{}", self.spi_smem_split_trans_en().bit()),
+                &self.spi_smem_ecc_16to18_byte_en(),
             )
+            .field("spi_smem_cs_hold_delay", &self.spi_smem_cs_hold_delay())
+            .field("spi_smem_split_trans_en", &self.spi_smem_split_trans_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_AC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI external RAM ECC and SPI CS timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_ac::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_SMEM_AC_SPEC;
 impl crate::RegisterSpec for SPI_SMEM_AC_SPEC {
diff --git a/esp32h2/src/spi0/spi_smem_ddr.rs b/esp32h2/src/spi0/spi_smem_ddr.rs
index f761796c63..4ff1b77e74 100644
--- a/esp32h2/src/spi0/spi_smem_ddr.rs
+++ b/esp32h2/src/spi0/spi_smem_ddr.rs
@@ -118,64 +118,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DDR")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field(
-                "spi_smem_var_dummy",
-                &format_args!("{}", self.spi_smem_var_dummy().bit()),
-            )
-            .field("rdat_swp", &format_args!("{}", self.rdat_swp().bit()))
-            .field("wdat_swp", &format_args!("{}", self.wdat_swp().bit()))
-            .field("cmd_dis", &format_args!("{}", self.cmd_dis().bit()))
-            .field(
-                "spi_smem_outminbytelen",
-                &format_args!("{}", self.spi_smem_outminbytelen().bits()),
-            )
-            .field(
-                "spi_smem_tx_ddr_msk_en",
-                &format_args!("{}", self.spi_smem_tx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_smem_rx_ddr_msk_en",
-                &format_args!("{}", self.spi_smem_rx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_smem_usr_ddr_dqs_thd",
-                &format_args!("{}", self.spi_smem_usr_ddr_dqs_thd().bits()),
-            )
-            .field("dqs_loop", &format_args!("{}", self.dqs_loop().bit()))
-            .field(
-                "spi_smem_clk_diff_en",
-                &format_args!("{}", self.spi_smem_clk_diff_en().bit()),
-            )
-            .field(
-                "spi_smem_dqs_ca_in",
-                &format_args!("{}", self.spi_smem_dqs_ca_in().bit()),
-            )
+            .field("en", &self.en())
+            .field("spi_smem_var_dummy", &self.spi_smem_var_dummy())
+            .field("rdat_swp", &self.rdat_swp())
+            .field("wdat_swp", &self.wdat_swp())
+            .field("cmd_dis", &self.cmd_dis())
+            .field("spi_smem_outminbytelen", &self.spi_smem_outminbytelen())
+            .field("spi_smem_tx_ddr_msk_en", &self.spi_smem_tx_ddr_msk_en())
+            .field("spi_smem_rx_ddr_msk_en", &self.spi_smem_rx_ddr_msk_en())
+            .field("spi_smem_usr_ddr_dqs_thd", &self.spi_smem_usr_ddr_dqs_thd())
+            .field("dqs_loop", &self.dqs_loop())
+            .field("spi_smem_clk_diff_en", &self.spi_smem_clk_diff_en())
+            .field("spi_smem_dqs_ca_in", &self.spi_smem_dqs_ca_in())
             .field(
                 "spi_smem_hyperbus_dummy_2x",
-                &format_args!("{}", self.spi_smem_hyperbus_dummy_2x().bit()),
-            )
-            .field(
-                "spi_smem_clk_diff_inv",
-                &format_args!("{}", self.spi_smem_clk_diff_inv().bit()),
-            )
-            .field(
-                "spi_smem_octa_ram_addr",
-                &format_args!("{}", self.spi_smem_octa_ram_addr().bit()),
-            )
-            .field(
-                "spi_smem_hyperbus_ca",
-                &format_args!("{}", self.spi_smem_hyperbus_ca().bit()),
+                &self.spi_smem_hyperbus_dummy_2x(),
             )
+            .field("spi_smem_clk_diff_inv", &self.spi_smem_clk_diff_inv())
+            .field("spi_smem_octa_ram_addr", &self.spi_smem_octa_ram_addr())
+            .field("spi_smem_hyperbus_ca", &self.spi_smem_hyperbus_ca())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 external RAM DDR mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_ddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_SMEM_DDR_SPEC;
 impl crate::RegisterSpec for SPI_SMEM_DDR_SPEC {
diff --git a/esp32h2/src/spi0/spi_smem_din_mode.rs b/esp32h2/src/spi0/spi_smem_din_mode.rs
index 3fc274762b..56436fb48c 100644
--- a/esp32h2/src/spi0/spi_smem_din_mode.rs
+++ b/esp32h2/src/spi0/spi_smem_din_mode.rs
@@ -69,51 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DIN_MODE")
-            .field(
-                "spi_smem_din0_mode",
-                &format_args!("{}", self.spi_smem_din0_mode().bits()),
-            )
-            .field(
-                "spi_smem_din1_mode",
-                &format_args!("{}", self.spi_smem_din1_mode().bits()),
-            )
-            .field(
-                "spi_smem_din2_mode",
-                &format_args!("{}", self.spi_smem_din2_mode().bits()),
-            )
-            .field(
-                "spi_smem_din3_mode",
-                &format_args!("{}", self.spi_smem_din3_mode().bits()),
-            )
-            .field(
-                "spi_smem_din4_mode",
-                &format_args!("{}", self.spi_smem_din4_mode().bits()),
-            )
-            .field(
-                "spi_smem_din5_mode",
-                &format_args!("{}", self.spi_smem_din5_mode().bits()),
-            )
-            .field(
-                "spi_smem_din6_mode",
-                &format_args!("{}", self.spi_smem_din6_mode().bits()),
-            )
-            .field(
-                "spi_smem_din7_mode",
-                &format_args!("{}", self.spi_smem_din7_mode().bits()),
-            )
-            .field(
-                "spi_smem_dins_mode",
-                &format_args!("{}", self.spi_smem_dins_mode().bits()),
-            )
+            .field("spi_smem_din0_mode", &self.spi_smem_din0_mode())
+            .field("spi_smem_din1_mode", &self.spi_smem_din1_mode())
+            .field("spi_smem_din2_mode", &self.spi_smem_din2_mode())
+            .field("spi_smem_din3_mode", &self.spi_smem_din3_mode())
+            .field("spi_smem_din4_mode", &self.spi_smem_din4_mode())
+            .field("spi_smem_din5_mode", &self.spi_smem_din5_mode())
+            .field("spi_smem_din6_mode", &self.spi_smem_din6_mode())
+            .field("spi_smem_din7_mode", &self.spi_smem_din7_mode())
+            .field("spi_smem_dins_mode", &self.spi_smem_dins_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI external RAM input timing delay mode control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_din_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_SMEM_DIN_MODE_SPEC;
 impl crate::RegisterSpec for SPI_SMEM_DIN_MODE_SPEC {
diff --git a/esp32h2/src/spi0/spi_smem_din_num.rs b/esp32h2/src/spi0/spi_smem_din_num.rs
index 1c87741917..8fbfd95535 100644
--- a/esp32h2/src/spi0/spi_smem_din_num.rs
+++ b/esp32h2/src/spi0/spi_smem_din_num.rs
@@ -69,51 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DIN_NUM")
-            .field(
-                "spi_smem_din0_num",
-                &format_args!("{}", self.spi_smem_din0_num().bits()),
-            )
-            .field(
-                "spi_smem_din1_num",
-                &format_args!("{}", self.spi_smem_din1_num().bits()),
-            )
-            .field(
-                "spi_smem_din2_num",
-                &format_args!("{}", self.spi_smem_din2_num().bits()),
-            )
-            .field(
-                "spi_smem_din3_num",
-                &format_args!("{}", self.spi_smem_din3_num().bits()),
-            )
-            .field(
-                "spi_smem_din4_num",
-                &format_args!("{}", self.spi_smem_din4_num().bits()),
-            )
-            .field(
-                "spi_smem_din5_num",
-                &format_args!("{}", self.spi_smem_din5_num().bits()),
-            )
-            .field(
-                "spi_smem_din6_num",
-                &format_args!("{}", self.spi_smem_din6_num().bits()),
-            )
-            .field(
-                "spi_smem_din7_num",
-                &format_args!("{}", self.spi_smem_din7_num().bits()),
-            )
-            .field(
-                "spi_smem_dins_num",
-                &format_args!("{}", self.spi_smem_dins_num().bits()),
-            )
+            .field("spi_smem_din0_num", &self.spi_smem_din0_num())
+            .field("spi_smem_din1_num", &self.spi_smem_din1_num())
+            .field("spi_smem_din2_num", &self.spi_smem_din2_num())
+            .field("spi_smem_din3_num", &self.spi_smem_din3_num())
+            .field("spi_smem_din4_num", &self.spi_smem_din4_num())
+            .field("spi_smem_din5_num", &self.spi_smem_din5_num())
+            .field("spi_smem_din6_num", &self.spi_smem_din6_num())
+            .field("spi_smem_din7_num", &self.spi_smem_din7_num())
+            .field("spi_smem_dins_num", &self.spi_smem_dins_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI external RAM input timing delay number control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_din_num::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_SMEM_DIN_NUM_SPEC;
 impl crate::RegisterSpec for SPI_SMEM_DIN_NUM_SPEC {
diff --git a/esp32h2/src/spi0/spi_smem_dout_mode.rs b/esp32h2/src/spi0/spi_smem_dout_mode.rs
index 145845bc2e..e00992c610 100644
--- a/esp32h2/src/spi0/spi_smem_dout_mode.rs
+++ b/esp32h2/src/spi0/spi_smem_dout_mode.rs
@@ -69,51 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DOUT_MODE")
-            .field(
-                "spi_smem_dout0_mode",
-                &format_args!("{}", self.spi_smem_dout0_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout1_mode",
-                &format_args!("{}", self.spi_smem_dout1_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout2_mode",
-                &format_args!("{}", self.spi_smem_dout2_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout3_mode",
-                &format_args!("{}", self.spi_smem_dout3_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout4_mode",
-                &format_args!("{}", self.spi_smem_dout4_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout5_mode",
-                &format_args!("{}", self.spi_smem_dout5_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout6_mode",
-                &format_args!("{}", self.spi_smem_dout6_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout7_mode",
-                &format_args!("{}", self.spi_smem_dout7_mode().bit()),
-            )
-            .field(
-                "spi_smem_douts_mode",
-                &format_args!("{}", self.spi_smem_douts_mode().bit()),
-            )
+            .field("spi_smem_dout0_mode", &self.spi_smem_dout0_mode())
+            .field("spi_smem_dout1_mode", &self.spi_smem_dout1_mode())
+            .field("spi_smem_dout2_mode", &self.spi_smem_dout2_mode())
+            .field("spi_smem_dout3_mode", &self.spi_smem_dout3_mode())
+            .field("spi_smem_dout4_mode", &self.spi_smem_dout4_mode())
+            .field("spi_smem_dout5_mode", &self.spi_smem_dout5_mode())
+            .field("spi_smem_dout6_mode", &self.spi_smem_dout6_mode())
+            .field("spi_smem_dout7_mode", &self.spi_smem_dout7_mode())
+            .field("spi_smem_douts_mode", &self.spi_smem_douts_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI external RAM output timing adjustment control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_dout_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_SMEM_DOUT_MODE_SPEC;
 impl crate::RegisterSpec for SPI_SMEM_DOUT_MODE_SPEC {
diff --git a/esp32h2/src/spi0/spi_smem_ecc_ctrl.rs b/esp32h2/src/spi0/spi_smem_ecc_ctrl.rs
index 24b8d624ce..75e2629ea1 100644
--- a/esp32h2/src/spi0/spi_smem_ecc_ctrl.rs
+++ b/esp32h2/src/spi0/spi_smem_ecc_ctrl.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_ECC_CTRL")
-            .field(
-                "spi_smem_ecc_err_int_en",
-                &format_args!("{}", self.spi_smem_ecc_err_int_en().bit()),
-            )
-            .field(
-                "spi_smem_page_size",
-                &format_args!("{}", self.spi_smem_page_size().bits()),
-            )
-            .field(
-                "spi_smem_ecc_addr_en",
-                &format_args!("{}", self.spi_smem_ecc_addr_en().bit()),
-            )
+            .field("spi_smem_ecc_err_int_en", &self.spi_smem_ecc_err_int_en())
+            .field("spi_smem_page_size", &self.spi_smem_page_size())
+            .field("spi_smem_ecc_addr_en", &self.spi_smem_ecc_addr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_ECC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI ECC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_ecc_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_SMEM_ECC_CTRL_SPEC;
 impl crate::RegisterSpec for SPI_SMEM_ECC_CTRL_SPEC {
diff --git a/esp32h2/src/spi0/spi_smem_pms_addr.rs b/esp32h2/src/spi0/spi_smem_pms_addr.rs
index 732e3af257..d69094798b 100644
--- a/esp32h2/src/spi0/spi_smem_pms_addr.rs
+++ b/esp32h2/src/spi0/spi_smem_pms_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_PMS_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_PMS_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - SPI1 external RAM ACE section %s start address value"]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/spi_smem_pms_attr.rs b/esp32h2/src/spi0/spi_smem_pms_attr.rs
index 7564b4c3f6..99daf67d7a 100644
--- a/esp32h2/src/spi0/spi_smem_pms_attr.rs
+++ b/esp32h2/src/spi0/spi_smem_pms_attr.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_PMS_ATTR")
-            .field(
-                "spi_smem_pms_rd_attr",
-                &format_args!("{}", self.spi_smem_pms_rd_attr().bit()),
-            )
-            .field(
-                "spi_smem_pms_wr_attr",
-                &format_args!("{}", self.spi_smem_pms_wr_attr().bit()),
-            )
-            .field(
-                "spi_smem_pms_ecc",
-                &format_args!("{}", self.spi_smem_pms_ecc().bit()),
-            )
+            .field("spi_smem_pms_rd_attr", &self.spi_smem_pms_rd_attr())
+            .field("spi_smem_pms_wr_attr", &self.spi_smem_pms_wr_attr())
+            .field("spi_smem_pms_ecc", &self.spi_smem_pms_ecc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_PMS_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: SPI1 external RAM ACE section %s read accessible. 0: Not allowed."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/spi_smem_pms_size.rs b/esp32h2/src/spi0/spi_smem_pms_size.rs
index aabfb0b96d..0ddc5b8234 100644
--- a/esp32h2/src/spi0/spi_smem_pms_size.rs
+++ b/esp32h2/src/spi0/spi_smem_pms_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_PMS_SIZE")
-            .field(
-                "spi_smem_pms_size",
-                &format_args!("{}", self.spi_smem_pms_size().bits()),
-            )
+            .field("spi_smem_pms_size", &self.spi_smem_pms_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_PMS_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - SPI1 external RAM ACE section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE)"]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/spi_smem_timing_cali.rs b/esp32h2/src/spi0/spi_smem_timing_cali.rs
index ed3778583c..8f140177c4 100644
--- a/esp32h2/src/spi0/spi_smem_timing_cali.rs
+++ b/esp32h2/src/spi0/spi_smem_timing_cali.rs
@@ -34,31 +34,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_TIMING_CALI")
-            .field(
-                "spi_smem_timing_clk_ena",
-                &format_args!("{}", self.spi_smem_timing_clk_ena().bit()),
-            )
-            .field(
-                "spi_smem_timing_cali",
-                &format_args!("{}", self.spi_smem_timing_cali().bit()),
-            )
+            .field("spi_smem_timing_clk_ena", &self.spi_smem_timing_clk_ena())
+            .field("spi_smem_timing_cali", &self.spi_smem_timing_cali())
             .field(
                 "spi_smem_extra_dummy_cyclelen",
-                &format_args!("{}", self.spi_smem_extra_dummy_cyclelen().bits()),
-            )
-            .field(
-                "spi_smem_dll_timing_cali",
-                &format_args!("{}", self.spi_smem_dll_timing_cali().bit()),
+                &self.spi_smem_extra_dummy_cyclelen(),
             )
+            .field("spi_smem_dll_timing_cali", &self.spi_smem_dll_timing_cali())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI external RAM timing calibration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_timing_cali::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_SMEM_TIMING_CALI_SPEC;
 impl crate::RegisterSpec for SPI_SMEM_TIMING_CALI_SPEC {
diff --git a/esp32h2/src/spi0/sram_clk.rs b/esp32h2/src/spi0/sram_clk.rs
index 10a0c605b0..e8649fcb40 100644
--- a/esp32h2/src/spi0/sram_clk.rs
+++ b/esp32h2/src/spi0/sram_clk.rs
@@ -34,22 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_CLK")
-            .field("sclkcnt_l", &format_args!("{}", self.sclkcnt_l().bits()))
-            .field("sclkcnt_h", &format_args!("{}", self.sclkcnt_h().bits()))
-            .field("sclkcnt_n", &format_args!("{}", self.sclkcnt_n().bits()))
-            .field(
-                "sclk_equ_sysclk",
-                &format_args!("{}", self.sclk_equ_sysclk().bit()),
-            )
+            .field("sclkcnt_l", &self.sclkcnt_l())
+            .field("sclkcnt_h", &self.sclkcnt_h())
+            .field("sclkcnt_n", &self.sclkcnt_n())
+            .field("sclk_equ_sysclk", &self.sclk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 external RAM clock control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_clk::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SRAM_CLK_SPEC;
 impl crate::RegisterSpec for SRAM_CLK_SPEC {
diff --git a/esp32h2/src/spi0/sram_cmd.rs b/esp32h2/src/spi0/sram_cmd.rs
index 3b89fc06c0..d0e6e70406 100644
--- a/esp32h2/src/spi0/sram_cmd.rs
+++ b/esp32h2/src/spi0/sram_cmd.rs
@@ -143,46 +143,40 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_CMD")
-            .field("sclk_mode", &format_args!("{}", self.sclk_mode().bits()))
-            .field("swb_mode", &format_args!("{}", self.swb_mode().bits()))
-            .field("sdin_dual", &format_args!("{}", self.sdin_dual().bit()))
-            .field("sdout_dual", &format_args!("{}", self.sdout_dual().bit()))
-            .field("saddr_dual", &format_args!("{}", self.saddr_dual().bit()))
-            .field("sdin_quad", &format_args!("{}", self.sdin_quad().bit()))
-            .field("sdout_quad", &format_args!("{}", self.sdout_quad().bit()))
-            .field("saddr_quad", &format_args!("{}", self.saddr_quad().bit()))
-            .field("scmd_quad", &format_args!("{}", self.scmd_quad().bit()))
-            .field("sdin_oct", &format_args!("{}", self.sdin_oct().bit()))
-            .field("sdout_oct", &format_args!("{}", self.sdout_oct().bit()))
-            .field("saddr_oct", &format_args!("{}", self.saddr_oct().bit()))
-            .field("scmd_oct", &format_args!("{}", self.scmd_oct().bit()))
-            .field("sdummy_rin", &format_args!("{}", self.sdummy_rin().bit()))
-            .field("sdummy_wout", &format_args!("{}", self.sdummy_wout().bit()))
+            .field("sclk_mode", &self.sclk_mode())
+            .field("swb_mode", &self.swb_mode())
+            .field("sdin_dual", &self.sdin_dual())
+            .field("sdout_dual", &self.sdout_dual())
+            .field("saddr_dual", &self.saddr_dual())
+            .field("sdin_quad", &self.sdin_quad())
+            .field("sdout_quad", &self.sdout_quad())
+            .field("saddr_quad", &self.saddr_quad())
+            .field("scmd_quad", &self.scmd_quad())
+            .field("sdin_oct", &self.sdin_oct())
+            .field("sdout_oct", &self.sdout_oct())
+            .field("saddr_oct", &self.saddr_oct())
+            .field("scmd_oct", &self.scmd_oct())
+            .field("sdummy_rin", &self.sdummy_rin())
+            .field("sdummy_wout", &self.sdummy_wout())
             .field(
                 "spi_smem_wdummy_dqs_always_out",
-                &format_args!("{}", self.spi_smem_wdummy_dqs_always_out().bit()),
+                &self.spi_smem_wdummy_dqs_always_out(),
             )
             .field(
                 "spi_smem_wdummy_always_out",
-                &format_args!("{}", self.spi_smem_wdummy_always_out().bit()),
+                &self.spi_smem_wdummy_always_out(),
             )
             .field(
                 "spi_smem_dqs_ie_always_on",
-                &format_args!("{}", self.spi_smem_dqs_ie_always_on().bit()),
+                &self.spi_smem_dqs_ie_always_on(),
             )
             .field(
                 "spi_smem_data_ie_always_on",
-                &format_args!("{}", self.spi_smem_data_ie_always_on().bit()),
+                &self.spi_smem_data_ie_always_on(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 22 - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/sram_drd_cmd.rs b/esp32h2/src/spi0/sram_drd_cmd.rs
index 05c7b20972..915d474d5c 100644
--- a/esp32h2/src/spi0/sram_drd_cmd.rs
+++ b/esp32h2/src/spi0/sram_drd_cmd.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("SRAM_DRD_CMD")
             .field(
                 "cache_sram_usr_rd_cmd_value",
-                &format_args!("{}", self.cache_sram_usr_rd_cmd_value().bits()),
+                &self.cache_sram_usr_rd_cmd_value(),
             )
             .field(
                 "cache_sram_usr_rd_cmd_bitlen",
-                &format_args!("{}", self.cache_sram_usr_rd_cmd_bitlen().bits()),
+                &self.cache_sram_usr_rd_cmd_bitlen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_DRD_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 external RAM DDR read command control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_drd_cmd::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SRAM_DRD_CMD_SPEC;
 impl crate::RegisterSpec for SRAM_DRD_CMD_SPEC {
diff --git a/esp32h2/src/spi0/sram_dwr_cmd.rs b/esp32h2/src/spi0/sram_dwr_cmd.rs
index 5173dc72f8..3e8ea90163 100644
--- a/esp32h2/src/spi0/sram_dwr_cmd.rs
+++ b/esp32h2/src/spi0/sram_dwr_cmd.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("SRAM_DWR_CMD")
             .field(
                 "cache_sram_usr_wr_cmd_value",
-                &format_args!("{}", self.cache_sram_usr_wr_cmd_value().bits()),
+                &self.cache_sram_usr_wr_cmd_value(),
             )
             .field(
                 "cache_sram_usr_wr_cmd_bitlen",
-                &format_args!("{}", self.cache_sram_usr_wr_cmd_bitlen().bits()),
+                &self.cache_sram_usr_wr_cmd_bitlen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_DWR_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 external RAM DDR write command control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sram_dwr_cmd::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SRAM_DWR_CMD_SPEC;
 impl crate::RegisterSpec for SRAM_DWR_CMD_SPEC {
diff --git a/esp32h2/src/spi0/timing_cali.rs b/esp32h2/src/spi0/timing_cali.rs
index 7e0f42b794..12d673f8b4 100644
--- a/esp32h2/src/spi0/timing_cali.rs
+++ b/esp32h2/src/spi0/timing_cali.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMING_CALI")
-            .field(
-                "timing_clk_ena",
-                &format_args!("{}", self.timing_clk_ena().bit()),
-            )
-            .field("timing_cali", &format_args!("{}", self.timing_cali().bit()))
-            .field(
-                "extra_dummy_cyclelen",
-                &format_args!("{}", self.extra_dummy_cyclelen().bits()),
-            )
-            .field(
-                "dll_timing_cali",
-                &format_args!("{}", self.dll_timing_cali().bit()),
-            )
+            .field("timing_clk_ena", &self.timing_clk_ena())
+            .field("timing_cali", &self.timing_cali())
+            .field("extra_dummy_cyclelen", &self.extra_dummy_cyclelen())
+            .field("dll_timing_cali", &self.dll_timing_cali())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable timing adjust clock for all reading operations."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/user.rs b/esp32h2/src/spi0/user.rs
index 3af8b9a5f6..7c1da8336d 100644
--- a/esp32h2/src/spi0/user.rs
+++ b/esp32h2/src/spi0/user.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
-            .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
+            .field("cs_hold", &self.cs_hold())
+            .field("cs_setup", &self.cs_setup())
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_dummy", &self.usr_dummy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/user1.rs b/esp32h2/src/spi0/user1.rs
index 7261a1c0de..a951f31e26 100644
--- a/esp32h2/src/spi0/user1.rs
+++ b/esp32h2/src/spi0/user1.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "usr_dbytelen",
-                &format_args!("{}", self.usr_dbytelen().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("usr_dbytelen", &self.usr_dbytelen())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/user2.rs b/esp32h2/src/spi0/user2.rs
index 801f605c21..d0bf1413f5 100644
--- a/esp32h2/src/spi0/user2.rs
+++ b/esp32h2/src/spi0/user2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/xts_date.rs b/esp32h2/src/spi0/xts_date.rs
index f4626fb790..6a76691ffc 100644
--- a/esp32h2/src/spi0/xts_date.rs
+++ b/esp32h2/src/spi0/xts_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_DATE")
-            .field(
-                "spi_xts_date",
-                &format_args!("{}", self.spi_xts_date().bits()),
-            )
+            .field("spi_xts_date", &self.spi_xts_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - This bits stores the last modified-time of manual encryption feature."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/xts_destination.rs b/esp32h2/src/spi0/xts_destination.rs
index b892575ff3..53d1dc0664 100644
--- a/esp32h2/src/spi0/xts_destination.rs
+++ b/esp32h2/src/spi0/xts_destination.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_DESTINATION")
-            .field(
-                "spi_xts_destination",
-                &format_args!("{}", self.spi_xts_destination().bit()),
-            )
+            .field("spi_xts_destination", &self.spi_xts_destination())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_DESTINATION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/xts_linesize.rs b/esp32h2/src/spi0/xts_linesize.rs
index 69dda9b934..026adf4932 100644
--- a/esp32h2/src/spi0/xts_linesize.rs
+++ b/esp32h2/src/spi0/xts_linesize.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_LINESIZE")
-            .field(
-                "spi_xts_linesize",
-                &format_args!("{}", self.spi_xts_linesize().bits()),
-            )
+            .field("spi_xts_linesize", &self.spi_xts_linesize())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_LINESIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/xts_physical_address.rs b/esp32h2/src/spi0/xts_physical_address.rs
index 1c5e63ce4a..0bf10b2a3d 100644
--- a/esp32h2/src/spi0/xts_physical_address.rs
+++ b/esp32h2/src/spi0/xts_physical_address.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_PHYSICAL_ADDRESS")
-            .field(
-                "spi_xts_physical_address",
-                &format_args!("{}", self.spi_xts_physical_address().bits()),
-            )
+            .field("spi_xts_physical_address", &self.spi_xts_physical_address())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_PHYSICAL_ADDRESS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/xts_plain_base.rs b/esp32h2/src/spi0/xts_plain_base.rs
index 576a75225c..b411736db1 100644
--- a/esp32h2/src/spi0/xts_plain_base.rs
+++ b/esp32h2/src/spi0/xts_plain_base.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_PLAIN_BASE")
-            .field(
-                "spi_xts_plain",
-                &format_args!("{}", self.spi_xts_plain().bits()),
-            )
+            .field("spi_xts_plain", &self.spi_xts_plain())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_PLAIN_BASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This field is only used to generate include file in c case. This field is useless. Please do not use this field."]
     #[inline(always)]
diff --git a/esp32h2/src/spi0/xts_state.rs b/esp32h2/src/spi0/xts_state.rs
index f60c84f30c..7ce2fd6e44 100644
--- a/esp32h2/src/spi0/xts_state.rs
+++ b/esp32h2/src/spi0/xts_state.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_STATE")
-            .field(
-                "spi_xts_state",
-                &format_args!("{}", self.spi_xts_state().bits()),
-            )
+            .field("spi_xts_state", &self.spi_xts_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Manual Encryption physical address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xts_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct XTS_STATE_SPEC;
 impl crate::RegisterSpec for XTS_STATE_SPEC {
diff --git a/esp32h2/src/spi1/addr.rs b/esp32h2/src/spi1/addr.rs
index 565e7916d4..cc9a0e1b42 100644
--- a/esp32h2/src/spi1/addr.rs
+++ b/esp32h2/src/spi1/addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR")
-            .field(
-                "usr_addr_value",
-                &format_args!("{}", self.usr_addr_value().bits()),
-            )
+            .field("usr_addr_value", &self.usr_addr_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/cache_fctrl.rs b/esp32h2/src/spi1/cache_fctrl.rs
index c8eafade55..3a22f1f847 100644
--- a/esp32h2/src/spi1/cache_fctrl.rs
+++ b/esp32h2/src/spi1/cache_fctrl.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_FCTRL")
-            .field(
-                "cache_usr_addr_4byte",
-                &format_args!("{}", self.cache_usr_addr_4byte().bit()),
-            )
-            .field("fdin_dual", &format_args!("{}", self.fdin_dual().bit()))
-            .field("fdout_dual", &format_args!("{}", self.fdout_dual().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("fdin_quad", &format_args!("{}", self.fdin_quad().bit()))
-            .field("fdout_quad", &format_args!("{}", self.fdout_quad().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
+            .field("cache_usr_addr_4byte", &self.cache_usr_addr_4byte())
+            .field("fdin_dual", &self.fdin_dual())
+            .field("fdout_dual", &self.fdout_dual())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("fdin_quad", &self.fdin_quad())
+            .field("fdout_quad", &self.fdout_quad())
+            .field("faddr_quad", &self.faddr_quad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_FCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/clock.rs b/esp32h2/src/spi1/clock.rs
index 250a0c660f..ec805aad92 100644
--- a/esp32h2/src/spi1/clock.rs
+++ b/esp32h2/src/spi1/clock.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/clock_gate.rs b/esp32h2/src/spi1/clock_gate.rs
index c60d396767..69477e9842 100644
--- a/esp32h2/src/spi1/clock_gate.rs
+++ b/esp32h2/src/spi1/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/cmd.rs b/esp32h2/src/spi1/cmd.rs
index 8c3307af4a..6cb80f8502 100644
--- a/esp32h2/src/spi1/cmd.rs
+++ b/esp32h2/src/spi1/cmd.rs
@@ -157,32 +157,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("mst_st", &format_args!("{}", self.mst_st().bits()))
-            .field("slv_st", &format_args!("{}", self.slv_st().bits()))
-            .field("flash_pe", &format_args!("{}", self.flash_pe().bit()))
-            .field("usr", &format_args!("{}", self.usr().bit()))
-            .field("flash_hpm", &format_args!("{}", self.flash_hpm().bit()))
-            .field("flash_res", &format_args!("{}", self.flash_res().bit()))
-            .field("flash_dp", &format_args!("{}", self.flash_dp().bit()))
-            .field("flash_ce", &format_args!("{}", self.flash_ce().bit()))
-            .field("flash_be", &format_args!("{}", self.flash_be().bit()))
-            .field("flash_se", &format_args!("{}", self.flash_se().bit()))
-            .field("flash_pp", &format_args!("{}", self.flash_pp().bit()))
-            .field("flash_wrsr", &format_args!("{}", self.flash_wrsr().bit()))
-            .field("flash_rdsr", &format_args!("{}", self.flash_rdsr().bit()))
-            .field("flash_rdid", &format_args!("{}", self.flash_rdid().bit()))
-            .field("flash_wrdi", &format_args!("{}", self.flash_wrdi().bit()))
-            .field("flash_wren", &format_args!("{}", self.flash_wren().bit()))
-            .field("flash_read", &format_args!("{}", self.flash_read().bit()))
+            .field("mst_st", &self.mst_st())
+            .field("slv_st", &self.slv_st())
+            .field("flash_pe", &self.flash_pe())
+            .field("usr", &self.usr())
+            .field("flash_hpm", &self.flash_hpm())
+            .field("flash_res", &self.flash_res())
+            .field("flash_dp", &self.flash_dp())
+            .field("flash_ce", &self.flash_ce())
+            .field("flash_be", &self.flash_be())
+            .field("flash_se", &self.flash_se())
+            .field("flash_pp", &self.flash_pp())
+            .field("flash_wrsr", &self.flash_wrsr())
+            .field("flash_rdsr", &self.flash_rdsr())
+            .field("flash_rdid", &self.flash_rdid())
+            .field("flash_wrdi", &self.flash_wrdi())
+            .field("flash_wren", &self.flash_wren())
+            .field("flash_read", &self.flash_read())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/ctrl.rs b/esp32h2/src/spi1/ctrl.rs
index 9e276f4048..d86fde47c2 100644
--- a/esp32h2/src/spi1/ctrl.rs
+++ b/esp32h2/src/spi1/ctrl.rs
@@ -167,34 +167,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("fdummy_rin", &format_args!("{}", self.fdummy_rin().bit()))
-            .field("fdummy_wout", &format_args!("{}", self.fdummy_wout().bit()))
-            .field("fdout_oct", &format_args!("{}", self.fdout_oct().bit()))
-            .field("fdin_oct", &format_args!("{}", self.fdin_oct().bit()))
-            .field("faddr_oct", &format_args!("{}", self.faddr_oct().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcmd_oct", &format_args!("{}", self.fcmd_oct().bit()))
-            .field("fcs_crc_en", &format_args!("{}", self.fcs_crc_en().bit()))
-            .field("tx_crc_en", &format_args!("{}", self.tx_crc_en().bit()))
-            .field("fastrd_mode", &format_args!("{}", self.fastrd_mode().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("resandres", &format_args!("{}", self.resandres().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("wp", &format_args!("{}", self.wp().bit()))
-            .field("wrsr_2b", &format_args!("{}", self.wrsr_2b().bit()))
-            .field("fread_dio", &format_args!("{}", self.fread_dio().bit()))
-            .field("fread_qio", &format_args!("{}", self.fread_qio().bit()))
+            .field("fdummy_rin", &self.fdummy_rin())
+            .field("fdummy_wout", &self.fdummy_wout())
+            .field("fdout_oct", &self.fdout_oct())
+            .field("fdin_oct", &self.fdin_oct())
+            .field("faddr_oct", &self.faddr_oct())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcmd_oct", &self.fcmd_oct())
+            .field("fcs_crc_en", &self.fcs_crc_en())
+            .field("tx_crc_en", &self.tx_crc_en())
+            .field("fastrd_mode", &self.fastrd_mode())
+            .field("fread_dual", &self.fread_dual())
+            .field("resandres", &self.resandres())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("fread_quad", &self.fread_quad())
+            .field("wp", &self.wp())
+            .field("wrsr_2b", &self.wrsr_2b())
+            .field("fread_dio", &self.fread_dio())
+            .field("fread_qio", &self.fread_qio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/ctrl1.rs b/esp32h2/src/spi1/ctrl1.rs
index 72546d185b..bde8ad35ad 100644
--- a/esp32h2/src/spi1/ctrl1.rs
+++ b/esp32h2/src/spi1/ctrl1.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL1")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
-            .field(
-                "cs_hold_dly_res",
-                &format_args!("{}", self.cs_hold_dly_res().bits()),
-            )
+            .field("clk_mode", &self.clk_mode())
+            .field("cs_hold_dly_res", &self.cs_hold_dly_res())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/date.rs b/esp32h2/src/spi1/date.rs
index b06afaf3a2..451ac1b171 100644
--- a/esp32h2/src/spi1/date.rs
+++ b/esp32h2/src/spi1/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/spi1/ddr.rs b/esp32h2/src/spi1/ddr.rs
index cc9e90d9b5..2c342b9cda 100644
--- a/esp32h2/src/spi1/ddr.rs
+++ b/esp32h2/src/spi1/ddr.rs
@@ -104,71 +104,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DDR")
-            .field(
-                "spi_fmem_ddr_en",
-                &format_args!("{}", self.spi_fmem_ddr_en().bit()),
-            )
-            .field(
-                "spi_fmem_var_dummy",
-                &format_args!("{}", self.spi_fmem_var_dummy().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_rdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_rdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_wdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_wdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_cmd_dis",
-                &format_args!("{}", self.spi_fmem_ddr_cmd_dis().bit()),
-            )
-            .field(
-                "spi_fmem_outminbytelen",
-                &format_args!("{}", self.spi_fmem_outminbytelen().bits()),
-            )
-            .field(
-                "spi_fmem_usr_ddr_dqs_thd",
-                &format_args!("{}", self.spi_fmem_usr_ddr_dqs_thd().bits()),
-            )
-            .field(
-                "spi_fmem_ddr_dqs_loop",
-                &format_args!("{}", self.spi_fmem_ddr_dqs_loop().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_en",
-                &format_args!("{}", self.spi_fmem_clk_diff_en().bit()),
-            )
-            .field(
-                "spi_fmem_dqs_ca_in",
-                &format_args!("{}", self.spi_fmem_dqs_ca_in().bit()),
-            )
+            .field("spi_fmem_ddr_en", &self.spi_fmem_ddr_en())
+            .field("spi_fmem_var_dummy", &self.spi_fmem_var_dummy())
+            .field("spi_fmem_ddr_rdat_swp", &self.spi_fmem_ddr_rdat_swp())
+            .field("spi_fmem_ddr_wdat_swp", &self.spi_fmem_ddr_wdat_swp())
+            .field("spi_fmem_ddr_cmd_dis", &self.spi_fmem_ddr_cmd_dis())
+            .field("spi_fmem_outminbytelen", &self.spi_fmem_outminbytelen())
+            .field("spi_fmem_usr_ddr_dqs_thd", &self.spi_fmem_usr_ddr_dqs_thd())
+            .field("spi_fmem_ddr_dqs_loop", &self.spi_fmem_ddr_dqs_loop())
+            .field("spi_fmem_clk_diff_en", &self.spi_fmem_clk_diff_en())
+            .field("spi_fmem_dqs_ca_in", &self.spi_fmem_dqs_ca_in())
             .field(
                 "spi_fmem_hyperbus_dummy_2x",
-                &format_args!("{}", self.spi_fmem_hyperbus_dummy_2x().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_inv",
-                &format_args!("{}", self.spi_fmem_clk_diff_inv().bit()),
-            )
-            .field(
-                "spi_fmem_octa_ram_addr",
-                &format_args!("{}", self.spi_fmem_octa_ram_addr().bit()),
-            )
-            .field(
-                "spi_fmem_hyperbus_ca",
-                &format_args!("{}", self.spi_fmem_hyperbus_ca().bit()),
+                &self.spi_fmem_hyperbus_dummy_2x(),
             )
+            .field("spi_fmem_clk_diff_inv", &self.spi_fmem_clk_diff_inv())
+            .field("spi_fmem_octa_ram_addr", &self.spi_fmem_octa_ram_addr())
+            .field("spi_fmem_hyperbus_ca", &self.spi_fmem_hyperbus_ca())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 DDR control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DDR_SPEC;
 impl crate::RegisterSpec for DDR_SPEC {
diff --git a/esp32h2/src/spi1/flash_sus_cmd.rs b/esp32h2/src/spi1/flash_sus_cmd.rs
index 7d99bea28f..7ad88afb97 100644
--- a/esp32h2/src/spi1/flash_sus_cmd.rs
+++ b/esp32h2/src/spi1/flash_sus_cmd.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_SUS_CMD")
-            .field(
-                "flash_pes_command",
-                &format_args!("{}", self.flash_pes_command().bits()),
-            )
-            .field(
-                "wait_pesr_command",
-                &format_args!("{}", self.wait_pesr_command().bits()),
-            )
+            .field("flash_pes_command", &self.flash_pes_command())
+            .field("wait_pesr_command", &self.wait_pesr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_SUS_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Program/Erase suspend command."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/flash_sus_ctrl.rs b/esp32h2/src/spi1/flash_sus_ctrl.rs
index 187f971488..1f8d0298dd 100644
--- a/esp32h2/src/spi1/flash_sus_ctrl.rs
+++ b/esp32h2/src/spi1/flash_sus_ctrl.rs
@@ -107,44 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_SUS_CTRL")
-            .field("flash_per", &format_args!("{}", self.flash_per().bit()))
-            .field("flash_pes", &format_args!("{}", self.flash_pes().bit()))
-            .field(
-                "flash_per_wait_en",
-                &format_args!("{}", self.flash_per_wait_en().bit()),
-            )
-            .field(
-                "flash_pes_wait_en",
-                &format_args!("{}", self.flash_pes_wait_en().bit()),
-            )
-            .field("pes_per_en", &format_args!("{}", self.pes_per_en().bit()))
-            .field(
-                "flash_pes_en",
-                &format_args!("{}", self.flash_pes_en().bit()),
-            )
-            .field(
-                "pesr_end_msk",
-                &format_args!("{}", self.pesr_end_msk().bits()),
-            )
-            .field(
-                "spi_fmem_rd_sus_2b",
-                &format_args!("{}", self.spi_fmem_rd_sus_2b().bit()),
-            )
-            .field("per_end_en", &format_args!("{}", self.per_end_en().bit()))
-            .field("pes_end_en", &format_args!("{}", self.pes_end_en().bit()))
-            .field(
-                "sus_timeout_cnt",
-                &format_args!("{}", self.sus_timeout_cnt().bits()),
-            )
+            .field("flash_per", &self.flash_per())
+            .field("flash_pes", &self.flash_pes())
+            .field("flash_per_wait_en", &self.flash_per_wait_en())
+            .field("flash_pes_wait_en", &self.flash_pes_wait_en())
+            .field("pes_per_en", &self.pes_per_en())
+            .field("flash_pes_en", &self.flash_pes_en())
+            .field("pesr_end_msk", &self.pesr_end_msk())
+            .field("spi_fmem_rd_sus_2b", &self.spi_fmem_rd_sus_2b())
+            .field("per_end_en", &self.per_end_en())
+            .field("pes_end_en", &self.pes_end_en())
+            .field("sus_timeout_cnt", &self.sus_timeout_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_SUS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/flash_waiti_ctrl.rs b/esp32h2/src/spi1/flash_waiti_ctrl.rs
index 324fe5b02e..d41f29aa1b 100644
--- a/esp32h2/src/spi1/flash_waiti_ctrl.rs
+++ b/esp32h2/src/spi1/flash_waiti_ctrl.rs
@@ -71,34 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_WAITI_CTRL")
-            .field("waiti_en", &format_args!("{}", self.waiti_en().bit()))
-            .field("waiti_dummy", &format_args!("{}", self.waiti_dummy().bit()))
-            .field(
-                "waiti_addr_en",
-                &format_args!("{}", self.waiti_addr_en().bit()),
-            )
-            .field(
-                "waiti_addr_cyclelen",
-                &format_args!("{}", self.waiti_addr_cyclelen().bits()),
-            )
-            .field(
-                "waiti_cmd_2b",
-                &format_args!("{}", self.waiti_cmd_2b().bit()),
-            )
-            .field(
-                "waiti_dummy_cyclelen",
-                &format_args!("{}", self.waiti_dummy_cyclelen().bits()),
-            )
-            .field("waiti_cmd", &format_args!("{}", self.waiti_cmd().bits()))
+            .field("waiti_en", &self.waiti_en())
+            .field("waiti_dummy", &self.waiti_dummy())
+            .field("waiti_addr_en", &self.waiti_addr_en())
+            .field("waiti_addr_cyclelen", &self.waiti_addr_cyclelen())
+            .field("waiti_cmd_2b", &self.waiti_cmd_2b())
+            .field("waiti_dummy_cyclelen", &self.waiti_dummy_cyclelen())
+            .field("waiti_cmd", &self.waiti_cmd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_WAITI_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/int_ena.rs b/esp32h2/src/spi1/int_ena.rs
index bbd8af0e24..48dff931c1 100644
--- a/esp32h2/src/spi1/int_ena.rs
+++ b/esp32h2/src/spi1/int_ena.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("wpe_end", &self.wpe_end())
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("brown_out", &self.brown_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for SPI_MEM_PER_END_INT interrupt."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/int_raw.rs b/esp32h2/src/spi1/int_raw.rs
index ae2ed7bc65..f67b50c6c6 100644
--- a/esp32h2/src/spi1/int_raw.rs
+++ b/esp32h2/src/spi1/int_raw.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("wpe_end", &self.wpe_end())
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("brown_out", &self.brown_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/int_st.rs b/esp32h2/src/spi1/int_st.rs
index b0d692f153..10cf1a6c2d 100644
--- a/esp32h2/src/spi1/int_st.rs
+++ b/esp32h2/src/spi1/int_st.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("wpe_end", &self.wpe_end())
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("brown_out", &self.brown_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/spi1/misc.rs b/esp32h2/src/spi1/misc.rs
index 980afa45ae..7c1f213c28 100644
--- a/esp32h2/src/spi1/misc.rs
+++ b/esp32h2/src/spi1/misc.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
-            .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/miso_dlen.rs b/esp32h2/src/spi1/miso_dlen.rs
index 737f493c8c..6813af19b3 100644
--- a/esp32h2/src/spi1/miso_dlen.rs
+++ b/esp32h2/src/spi1/miso_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISO_DLEN")
-            .field(
-                "usr_miso_dbitlen",
-                &format_args!("{}", self.usr_miso_dbitlen().bits()),
-            )
+            .field("usr_miso_dbitlen", &self.usr_miso_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISO_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The length in bits of read-data. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/mosi_dlen.rs b/esp32h2/src/spi1/mosi_dlen.rs
index b21b936f88..5cd5d155af 100644
--- a/esp32h2/src/spi1/mosi_dlen.rs
+++ b/esp32h2/src/spi1/mosi_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MOSI_DLEN")
-            .field(
-                "usr_mosi_dbitlen",
-                &format_args!("{}", self.usr_mosi_dbitlen().bits()),
-            )
+            .field("usr_mosi_dbitlen", &self.usr_mosi_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MOSI_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The length in bits of write-data. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/rd_status.rs b/esp32h2/src/spi1/rd_status.rs
index 6088e50d21..7368a19e92 100644
--- a/esp32h2/src/spi1/rd_status.rs
+++ b/esp32h2/src/spi1/rd_status.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_STATUS")
-            .field("status", &format_args!("{}", self.status().bits()))
-            .field("wb_mode", &format_args!("{}", self.wb_mode().bits()))
+            .field("status", &self.status())
+            .field("wb_mode", &self.wb_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/sus_status.rs b/esp32h2/src/spi1/sus_status.rs
index 80d580228b..8ad4de6524 100644
--- a/esp32h2/src/spi1/sus_status.rs
+++ b/esp32h2/src/spi1/sus_status.rs
@@ -98,52 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SUS_STATUS")
-            .field("flash_sus", &format_args!("{}", self.flash_sus().bit()))
-            .field(
-                "wait_pesr_cmd_2b",
-                &format_args!("{}", self.wait_pesr_cmd_2b().bit()),
-            )
-            .field(
-                "flash_hpm_dly_128",
-                &format_args!("{}", self.flash_hpm_dly_128().bit()),
-            )
-            .field(
-                "flash_res_dly_128",
-                &format_args!("{}", self.flash_res_dly_128().bit()),
-            )
-            .field(
-                "flash_dp_dly_128",
-                &format_args!("{}", self.flash_dp_dly_128().bit()),
-            )
-            .field(
-                "flash_per_dly_128",
-                &format_args!("{}", self.flash_per_dly_128().bit()),
-            )
-            .field(
-                "flash_pes_dly_128",
-                &format_args!("{}", self.flash_pes_dly_128().bit()),
-            )
-            .field(
-                "spi0_lock_en",
-                &format_args!("{}", self.spi0_lock_en().bit()),
-            )
-            .field(
-                "flash_pesr_cmd_2b",
-                &format_args!("{}", self.flash_pesr_cmd_2b().bit()),
-            )
-            .field(
-                "flash_per_command",
-                &format_args!("{}", self.flash_per_command().bits()),
-            )
+            .field("flash_sus", &self.flash_sus())
+            .field("wait_pesr_cmd_2b", &self.wait_pesr_cmd_2b())
+            .field("flash_hpm_dly_128", &self.flash_hpm_dly_128())
+            .field("flash_res_dly_128", &self.flash_res_dly_128())
+            .field("flash_dp_dly_128", &self.flash_dp_dly_128())
+            .field("flash_per_dly_128", &self.flash_per_dly_128())
+            .field("flash_pes_dly_128", &self.flash_pes_dly_128())
+            .field("spi0_lock_en", &self.spi0_lock_en())
+            .field("flash_pesr_cmd_2b", &self.flash_pesr_cmd_2b())
+            .field("flash_per_command", &self.flash_per_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SUS_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The status of flash suspend, only used in SPI1."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/timing_cali.rs b/esp32h2/src/spi1/timing_cali.rs
index 507064ae31..c6a30a5847 100644
--- a/esp32h2/src/spi1/timing_cali.rs
+++ b/esp32h2/src/spi1/timing_cali.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMING_CALI")
-            .field("timing_cali", &format_args!("{}", self.timing_cali().bit()))
-            .field(
-                "extra_dummy_cyclelen",
-                &format_args!("{}", self.extra_dummy_cyclelen().bits()),
-            )
+            .field("timing_cali", &self.timing_cali())
+            .field("extra_dummy_cyclelen", &self.extra_dummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/tx_crc.rs b/esp32h2/src/spi1/tx_crc.rs
index 9faa1c440d..253fff1be1 100644
--- a/esp32h2/src/spi1/tx_crc.rs
+++ b/esp32h2/src/spi1/tx_crc.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 TX CRC data register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TX_CRC_SPEC;
 impl crate::RegisterSpec for TX_CRC_SPEC {
diff --git a/esp32h2/src/spi1/user.rs b/esp32h2/src/spi1/user.rs
index 0ed8d7294f..9515db9c89 100644
--- a/esp32h2/src/spi1/user.rs
+++ b/esp32h2/src/spi1/user.rs
@@ -121,37 +121,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
-            .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
-            .field("fwrite_dio", &format_args!("{}", self.fwrite_dio().bit()))
-            .field("fwrite_qio", &format_args!("{}", self.fwrite_qio().bit()))
-            .field(
-                "usr_miso_highpart",
-                &format_args!("{}", self.usr_miso_highpart().bit()),
-            )
-            .field(
-                "usr_mosi_highpart",
-                &format_args!("{}", self.usr_mosi_highpart().bit()),
-            )
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
-            .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
-            .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
-            .field("usr_command", &format_args!("{}", self.usr_command().bit()))
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("fwrite_dual", &self.fwrite_dual())
+            .field("fwrite_quad", &self.fwrite_quad())
+            .field("fwrite_dio", &self.fwrite_dio())
+            .field("fwrite_qio", &self.fwrite_qio())
+            .field("usr_miso_highpart", &self.usr_miso_highpart())
+            .field("usr_mosi_highpart", &self.usr_mosi_highpart())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_mosi", &self.usr_mosi())
+            .field("usr_miso", &self.usr_miso())
+            .field("usr_dummy", &self.usr_dummy())
+            .field("usr_addr", &self.usr_addr())
+            .field("usr_command", &self.usr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/user1.rs b/esp32h2/src/spi1/user1.rs
index 4b36bbf30d..8f28ca2ba4 100644
--- a/esp32h2/src/spi1/user1.rs
+++ b/esp32h2/src/spi1/user1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/user2.rs b/esp32h2/src/spi1/user2.rs
index 382c76224c..4bd67c802f 100644
--- a/esp32h2/src/spi1/user2.rs
+++ b/esp32h2/src/spi1/user2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command."]
     #[inline(always)]
diff --git a/esp32h2/src/spi1/w.rs b/esp32h2/src/spi1/w.rs
index 319a8e0611..43137019f7 100644
--- a/esp32h2/src/spi1/w.rs
+++ b/esp32h2/src/spi1/w.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("W")
-            .field("buf", &format_args!("{}", self.buf().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<W_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("W").field("buf", &self.buf()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/spi2/addr.rs b/esp32h2/src/spi2/addr.rs
index 0429f136d3..a43f100c19 100644
--- a/esp32h2/src/spi2/addr.rs
+++ b/esp32h2/src/spi2/addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR")
-            .field(
-                "usr_addr_value",
-                &format_args!("{}", self.usr_addr_value().bits()),
-            )
+            .field("usr_addr_value", &self.usr_addr_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Address to slave. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/clk_gate.rs b/esp32h2/src/spi2/clk_gate.rs
index c690702c68..c633026011 100644
--- a/esp32h2/src/spi2/clk_gate.rs
+++ b/esp32h2/src/spi2/clk_gate.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "mst_clk_active",
-                &format_args!("{}", self.mst_clk_active().bit()),
-            )
-            .field("mst_clk_sel", &format_args!("{}", self.mst_clk_sel().bit()))
+            .field("clk_en", &self.clk_en())
+            .field("mst_clk_active", &self.mst_clk_active())
+            .field("mst_clk_sel", &self.mst_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable clk gate"]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/clock.rs b/esp32h2/src/spi2/clock.rs
index a980aa1ac0..336dc15885 100644
--- a/esp32h2/src/spi2/clock.rs
+++ b/esp32h2/src/spi2/clock.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field("clkdiv_pre", &format_args!("{}", self.clkdiv_pre().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clkdiv_pre", &self.clkdiv_pre())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/cmd.rs b/esp32h2/src/spi2/cmd.rs
index d9c54a966c..8d8333ec63 100644
--- a/esp32h2/src/spi2/cmd.rs
+++ b/esp32h2/src/spi2/cmd.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field(
-                "conf_bitlen",
-                &format_args!("{}", self.conf_bitlen().bits()),
-            )
-            .field("update", &format_args!("{}", self.update().bit()))
-            .field("usr", &format_args!("{}", self.usr().bit()))
+            .field("conf_bitlen", &self.conf_bitlen())
+            .field("update", &self.update())
+            .field("usr", &self.usr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - Define the APB cycles of SPI_CONF state. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/ctrl.rs b/esp32h2/src/spi2/ctrl.rs
index 13c41ae699..88e92d9320 100644
--- a/esp32h2/src/spi2/ctrl.rs
+++ b/esp32h2/src/spi2/ctrl.rs
@@ -146,37 +146,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("dummy_out", &format_args!("{}", self.dummy_out().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
-            .field("faddr_oct", &format_args!("{}", self.faddr_oct().bit()))
-            .field("fcmd_dual", &format_args!("{}", self.fcmd_dual().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcmd_oct", &format_args!("{}", self.fcmd_oct().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("fread_oct", &format_args!("{}", self.fread_oct().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("hold_pol", &format_args!("{}", self.hold_pol().bit()))
-            .field("wp_pol", &format_args!("{}", self.wp_pol().bit()))
-            .field(
-                "rd_bit_order",
-                &format_args!("{}", self.rd_bit_order().bits()),
-            )
-            .field(
-                "wr_bit_order",
-                &format_args!("{}", self.wr_bit_order().bits()),
-            )
+            .field("dummy_out", &self.dummy_out())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("faddr_quad", &self.faddr_quad())
+            .field("faddr_oct", &self.faddr_oct())
+            .field("fcmd_dual", &self.fcmd_dual())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcmd_oct", &self.fcmd_oct())
+            .field("fread_dual", &self.fread_dual())
+            .field("fread_quad", &self.fread_quad())
+            .field("fread_oct", &self.fread_oct())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("hold_pol", &self.hold_pol())
+            .field("wp_pol", &self.wp_pol())
+            .field("rd_bit_order", &self.rd_bit_order())
+            .field("wr_bit_order", &self.wr_bit_order())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/date.rs b/esp32h2/src/spi2/date.rs
index dfac83b005..9eee534b72 100644
--- a/esp32h2/src/spi2/date.rs
+++ b/esp32h2/src/spi2/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/spi2/din_mode.rs b/esp32h2/src/spi2/din_mode.rs
index 9e159ac6bc..afec40df37 100644
--- a/esp32h2/src/spi2/din_mode.rs
+++ b/esp32h2/src/spi2/din_mode.rs
@@ -81,27 +81,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_MODE")
-            .field("din0_mode", &format_args!("{}", self.din0_mode().bits()))
-            .field("din1_mode", &format_args!("{}", self.din1_mode().bits()))
-            .field("din2_mode", &format_args!("{}", self.din2_mode().bits()))
-            .field("din3_mode", &format_args!("{}", self.din3_mode().bits()))
-            .field("din4_mode", &format_args!("{}", self.din4_mode().bits()))
-            .field("din5_mode", &format_args!("{}", self.din5_mode().bits()))
-            .field("din6_mode", &format_args!("{}", self.din6_mode().bits()))
-            .field("din7_mode", &format_args!("{}", self.din7_mode().bits()))
-            .field(
-                "timing_hclk_active",
-                &format_args!("{}", self.timing_hclk_active().bit()),
-            )
+            .field("din0_mode", &self.din0_mode())
+            .field("din1_mode", &self.din1_mode())
+            .field("din2_mode", &self.din2_mode())
+            .field("din3_mode", &self.din3_mode())
+            .field("din4_mode", &self.din4_mode())
+            .field("din5_mode", &self.din5_mode())
+            .field("din6_mode", &self.din6_mode())
+            .field("din7_mode", &self.din7_mode())
+            .field("timing_hclk_active", &self.timing_hclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/din_num.rs b/esp32h2/src/spi2/din_num.rs
index a9b821a628..56a0d30639 100644
--- a/esp32h2/src/spi2/din_num.rs
+++ b/esp32h2/src/spi2/din_num.rs
@@ -72,23 +72,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_NUM")
-            .field("din0_num", &format_args!("{}", self.din0_num().bits()))
-            .field("din1_num", &format_args!("{}", self.din1_num().bits()))
-            .field("din2_num", &format_args!("{}", self.din2_num().bits()))
-            .field("din3_num", &format_args!("{}", self.din3_num().bits()))
-            .field("din4_num", &format_args!("{}", self.din4_num().bits()))
-            .field("din5_num", &format_args!("{}", self.din5_num().bits()))
-            .field("din6_num", &format_args!("{}", self.din6_num().bits()))
-            .field("din7_num", &format_args!("{}", self.din7_num().bits()))
+            .field("din0_num", &self.din0_num())
+            .field("din1_num", &self.din1_num())
+            .field("din2_num", &self.din2_num())
+            .field("din3_num", &self.din3_num())
+            .field("din4_num", &self.din4_num())
+            .field("din5_num", &self.din5_num())
+            .field("din6_num", &self.din6_num())
+            .field("din7_num", &self.din7_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/dma_conf.rs b/esp32h2/src/spi2/dma_conf.rs
index 2c8ad8198f..573e0e214e 100644
--- a/esp32h2/src/spi2/dma_conf.rs
+++ b/esp32h2/src/spi2/dma_conf.rs
@@ -82,38 +82,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field(
-                "dma_outfifo_empty",
-                &format_args!("{}", self.dma_outfifo_empty().bit()),
-            )
-            .field(
-                "dma_infifo_full",
-                &format_args!("{}", self.dma_infifo_full().bit()),
-            )
-            .field(
-                "dma_slv_seg_trans_en",
-                &format_args!("{}", self.dma_slv_seg_trans_en().bit()),
-            )
-            .field(
-                "slv_rx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_rx_seg_trans_clr_en().bit()),
-            )
-            .field(
-                "slv_tx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_tx_seg_trans_clr_en().bit()),
-            )
-            .field("rx_eof_en", &format_args!("{}", self.rx_eof_en().bit()))
-            .field("dma_rx_ena", &format_args!("{}", self.dma_rx_ena().bit()))
-            .field("dma_tx_ena", &format_args!("{}", self.dma_tx_ena().bit()))
+            .field("dma_outfifo_empty", &self.dma_outfifo_empty())
+            .field("dma_infifo_full", &self.dma_infifo_full())
+            .field("dma_slv_seg_trans_en", &self.dma_slv_seg_trans_en())
+            .field("slv_rx_seg_trans_clr_en", &self.slv_rx_seg_trans_clr_en())
+            .field("slv_tx_seg_trans_clr_en", &self.slv_tx_seg_trans_clr_en())
+            .field("rx_eof_en", &self.rx_eof_en())
+            .field("dma_rx_ena", &self.dma_rx_ena())
+            .field("dma_tx_ena", &self.dma_tx_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/dma_int_ena.rs b/esp32h2/src/spi2/dma_int_ena.rs
index 5a2520a556..57d74d21ae 100644
--- a/esp32h2/src/spi2/dma_int_ena.rs
+++ b/esp32h2/src/spi2/dma_int_ena.rs
@@ -197,69 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ENA")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/dma_int_raw.rs b/esp32h2/src/spi2/dma_int_raw.rs
index 4e27e4ae69..c8e69e9935 100644
--- a/esp32h2/src/spi2/dma_int_raw.rs
+++ b/esp32h2/src/spi2/dma_int_raw.rs
@@ -197,69 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_RAW")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/dma_int_st.rs b/esp32h2/src/spi2/dma_int_st.rs
index 424ec36870..5143fbdd5e 100644
--- a/esp32h2/src/spi2/dma_int_st.rs
+++ b/esp32h2/src/spi2/dma_int_st.rs
@@ -153,69 +153,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ST")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_INT_ST_SPEC;
 impl crate::RegisterSpec for DMA_INT_ST_SPEC {
diff --git a/esp32h2/src/spi2/dout_mode.rs b/esp32h2/src/spi2/dout_mode.rs
index 8de08decf3..87a510d71b 100644
--- a/esp32h2/src/spi2/dout_mode.rs
+++ b/esp32h2/src/spi2/dout_mode.rs
@@ -79,24 +79,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOUT_MODE")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bit()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bit()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bit()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bit()))
-            .field("dout4_mode", &format_args!("{}", self.dout4_mode().bit()))
-            .field("dout5_mode", &format_args!("{}", self.dout5_mode().bit()))
-            .field("dout6_mode", &format_args!("{}", self.dout6_mode().bit()))
-            .field("dout7_mode", &format_args!("{}", self.dout7_mode().bit()))
-            .field("d_dqs_mode", &format_args!("{}", self.d_dqs_mode().bit()))
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
+            .field("dout4_mode", &self.dout4_mode())
+            .field("dout5_mode", &self.dout5_mode())
+            .field("dout6_mode", &self.dout6_mode())
+            .field("dout7_mode", &self.dout7_mode())
+            .field("d_dqs_mode", &self.d_dqs_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/misc.rs b/esp32h2/src/spi2/misc.rs
index 1537a1ca6c..1a2a256246 100644
--- a/esp32h2/src/spi2/misc.rs
+++ b/esp32h2/src/spi2/misc.rs
@@ -151,53 +151,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
-            .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
-            .field("cs2_dis", &format_args!("{}", self.cs2_dis().bit()))
-            .field("cs3_dis", &format_args!("{}", self.cs3_dis().bit()))
-            .field("cs4_dis", &format_args!("{}", self.cs4_dis().bit()))
-            .field("cs5_dis", &format_args!("{}", self.cs5_dis().bit()))
-            .field("ck_dis", &format_args!("{}", self.ck_dis().bit()))
-            .field(
-                "master_cs_pol",
-                &format_args!("{}", self.master_cs_pol().bits()),
-            )
-            .field(
-                "clk_data_dtr_en",
-                &format_args!("{}", self.clk_data_dtr_en().bit()),
-            )
-            .field("data_dtr_en", &format_args!("{}", self.data_dtr_en().bit()))
-            .field("addr_dtr_en", &format_args!("{}", self.addr_dtr_en().bit()))
-            .field("cmd_dtr_en", &format_args!("{}", self.cmd_dtr_en().bit()))
-            .field(
-                "slave_cs_pol",
-                &format_args!("{}", self.slave_cs_pol().bit()),
-            )
-            .field(
-                "dqs_idle_edge",
-                &format_args!("{}", self.dqs_idle_edge().bit()),
-            )
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
-            .field(
-                "quad_din_pin_swap",
-                &format_args!("{}", self.quad_din_pin_swap().bit()),
-            )
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("cs2_dis", &self.cs2_dis())
+            .field("cs3_dis", &self.cs3_dis())
+            .field("cs4_dis", &self.cs4_dis())
+            .field("cs5_dis", &self.cs5_dis())
+            .field("ck_dis", &self.ck_dis())
+            .field("master_cs_pol", &self.master_cs_pol())
+            .field("clk_data_dtr_en", &self.clk_data_dtr_en())
+            .field("data_dtr_en", &self.data_dtr_en())
+            .field("addr_dtr_en", &self.addr_dtr_en())
+            .field("cmd_dtr_en", &self.cmd_dtr_en())
+            .field("slave_cs_pol", &self.slave_cs_pol())
+            .field("dqs_idle_edge", &self.dqs_idle_edge())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
+            .field("quad_din_pin_swap", &self.quad_din_pin_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/ms_dlen.rs b/esp32h2/src/spi2/ms_dlen.rs
index 116939582c..94a2915785 100644
--- a/esp32h2/src/spi2/ms_dlen.rs
+++ b/esp32h2/src/spi2/ms_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MS_DLEN")
-            .field(
-                "ms_data_bitlen",
-                &format_args!("{}", self.ms_data_bitlen().bits()),
-            )
+            .field("ms_data_bitlen", &self.ms_data_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MS_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/slave.rs b/esp32h2/src/spi2/slave.rs
index 5b32454807..3e663dd072 100644
--- a/esp32h2/src/spi2/slave.rs
+++ b/esp32h2/src/spi2/slave.rs
@@ -109,47 +109,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
-            .field("clk_mode_13", &format_args!("{}", self.clk_mode_13().bit()))
-            .field(
-                "rsck_data_out",
-                &format_args!("{}", self.rsck_data_out().bit()),
-            )
-            .field(
-                "slv_rddma_bitlen_en",
-                &format_args!("{}", self.slv_rddma_bitlen_en().bit()),
-            )
-            .field(
-                "slv_wrdma_bitlen_en",
-                &format_args!("{}", self.slv_wrdma_bitlen_en().bit()),
-            )
-            .field(
-                "slv_rdbuf_bitlen_en",
-                &format_args!("{}", self.slv_rdbuf_bitlen_en().bit()),
-            )
-            .field(
-                "slv_wrbuf_bitlen_en",
-                &format_args!("{}", self.slv_wrbuf_bitlen_en().bit()),
-            )
-            .field(
-                "dma_seg_magic_value",
-                &format_args!("{}", self.dma_seg_magic_value().bits()),
-            )
-            .field("mode", &format_args!("{}", self.mode().bit()))
-            .field("usr_conf", &format_args!("{}", self.usr_conf().bit()))
-            .field(
-                "mst_fd_wait_dma_tx_data",
-                &format_args!("{}", self.mst_fd_wait_dma_tx_data().bit()),
-            )
+            .field("clk_mode", &self.clk_mode())
+            .field("clk_mode_13", &self.clk_mode_13())
+            .field("rsck_data_out", &self.rsck_data_out())
+            .field("slv_rddma_bitlen_en", &self.slv_rddma_bitlen_en())
+            .field("slv_wrdma_bitlen_en", &self.slv_wrdma_bitlen_en())
+            .field("slv_rdbuf_bitlen_en", &self.slv_rdbuf_bitlen_en())
+            .field("slv_wrbuf_bitlen_en", &self.slv_wrbuf_bitlen_en())
+            .field("dma_seg_magic_value", &self.dma_seg_magic_value())
+            .field("mode", &self.mode())
+            .field("usr_conf", &self.usr_conf())
+            .field("mst_fd_wait_dma_tx_data", &self.mst_fd_wait_dma_tx_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/slave1.rs b/esp32h2/src/spi2/slave1.rs
index 7e216d9f86..98ad1b4b32 100644
--- a/esp32h2/src/spi2/slave1.rs
+++ b/esp32h2/src/spi2/slave1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE1")
-            .field(
-                "slv_data_bitlen",
-                &format_args!("{}", self.slv_data_bitlen().bits()),
-            )
-            .field(
-                "slv_last_command",
-                &format_args!("{}", self.slv_last_command().bits()),
-            )
-            .field(
-                "slv_last_addr",
-                &format_args!("{}", self.slv_last_addr().bits()),
-            )
+            .field("slv_data_bitlen", &self.slv_data_bitlen())
+            .field("slv_last_command", &self.slv_last_command())
+            .field("slv_last_addr", &self.slv_last_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - The transferred data bit length in SPI slave FD and HD mode."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/user.rs b/esp32h2/src/spi2/user.rs
index 61f673a063..e5405195fb 100644
--- a/esp32h2/src/spi2/user.rs
+++ b/esp32h2/src/spi2/user.rs
@@ -193,48 +193,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("doutdin", &format_args!("{}", self.doutdin().bit()))
-            .field("qpi_mode", &format_args!("{}", self.qpi_mode().bit()))
-            .field("opi_mode", &format_args!("{}", self.opi_mode().bit()))
-            .field("tsck_i_edge", &format_args!("{}", self.tsck_i_edge().bit()))
-            .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
-            .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
-            .field("rsck_i_edge", &format_args!("{}", self.rsck_i_edge().bit()))
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
-            .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
-            .field("fwrite_oct", &format_args!("{}", self.fwrite_oct().bit()))
-            .field(
-                "usr_conf_nxt",
-                &format_args!("{}", self.usr_conf_nxt().bit()),
-            )
-            .field("sio", &format_args!("{}", self.sio().bit()))
-            .field(
-                "usr_miso_highpart",
-                &format_args!("{}", self.usr_miso_highpart().bit()),
-            )
-            .field(
-                "usr_mosi_highpart",
-                &format_args!("{}", self.usr_mosi_highpart().bit()),
-            )
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
-            .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
-            .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
-            .field("usr_command", &format_args!("{}", self.usr_command().bit()))
+            .field("doutdin", &self.doutdin())
+            .field("qpi_mode", &self.qpi_mode())
+            .field("opi_mode", &self.opi_mode())
+            .field("tsck_i_edge", &self.tsck_i_edge())
+            .field("cs_hold", &self.cs_hold())
+            .field("cs_setup", &self.cs_setup())
+            .field("rsck_i_edge", &self.rsck_i_edge())
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("fwrite_dual", &self.fwrite_dual())
+            .field("fwrite_quad", &self.fwrite_quad())
+            .field("fwrite_oct", &self.fwrite_oct())
+            .field("usr_conf_nxt", &self.usr_conf_nxt())
+            .field("sio", &self.sio())
+            .field("usr_miso_highpart", &self.usr_miso_highpart())
+            .field("usr_mosi_highpart", &self.usr_mosi_highpart())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_mosi", &self.usr_mosi())
+            .field("usr_miso", &self.usr_miso())
+            .field("usr_dummy", &self.usr_dummy())
+            .field("usr_addr", &self.usr_addr())
+            .field("usr_command", &self.usr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/user1.rs b/esp32h2/src/spi2/user1.rs
index acb564ca07..1dd612d409 100644
--- a/esp32h2/src/spi2/user1.rs
+++ b/esp32h2/src/spi2/user1.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "mst_wfull_err_end_en",
-                &format_args!("{}", self.mst_wfull_err_end_en().bit()),
-            )
-            .field(
-                "cs_setup_time",
-                &format_args!("{}", self.cs_setup_time().bits()),
-            )
-            .field(
-                "cs_hold_time",
-                &format_args!("{}", self.cs_hold_time().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("mst_wfull_err_end_en", &self.mst_wfull_err_end_en())
+            .field("cs_setup_time", &self.cs_setup_time())
+            .field("cs_hold_time", &self.cs_hold_time())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/user2.rs b/esp32h2/src/spi2/user2.rs
index 065c536363..c2d5092cd2 100644
--- a/esp32h2/src/spi2/user2.rs
+++ b/esp32h2/src/spi2/user2.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "mst_rempty_err_end_en",
-                &format_args!("{}", self.mst_rempty_err_end_en().bit()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("mst_rempty_err_end_en", &self.mst_rempty_err_end_en())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32h2/src/spi2/w.rs b/esp32h2/src/spi2/w.rs
index bd1588a6f2..016fb59d7c 100644
--- a/esp32h2/src/spi2/w.rs
+++ b/esp32h2/src/spi2/w.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("W")
-            .field("buf", &format_args!("{}", self.buf().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<W_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("W").field("buf", &self.buf()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/systimer/conf.rs b/esp32h2/src/systimer/conf.rs
index dc9795ba23..8824e41e55 100644
--- a/esp32h2/src/systimer/conf.rs
+++ b/esp32h2/src/systimer/conf.rs
@@ -116,57 +116,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field(
-                "systimer_clk_fo",
-                &format_args!("{}", self.systimer_clk_fo().bit()),
-            )
-            .field("etm_en", &format_args!("{}", self.etm_en().bit()))
-            .field(
-                "target2_work_en",
-                &format_args!("{}", self.target2_work_en().bit()),
-            )
-            .field(
-                "target1_work_en",
-                &format_args!("{}", self.target1_work_en().bit()),
-            )
-            .field(
-                "target0_work_en",
-                &format_args!("{}", self.target0_work_en().bit()),
-            )
+            .field("systimer_clk_fo", &self.systimer_clk_fo())
+            .field("etm_en", &self.etm_en())
+            .field("target2_work_en", &self.target2_work_en())
+            .field("target1_work_en", &self.target1_work_en())
+            .field("target0_work_en", &self.target0_work_en())
             .field(
                 "timer_unit1_core1_stall_en",
-                &format_args!("{}", self.timer_unit1_core1_stall_en().bit()),
+                &self.timer_unit1_core1_stall_en(),
             )
             .field(
                 "timer_unit1_core0_stall_en",
-                &format_args!("{}", self.timer_unit1_core0_stall_en().bit()),
+                &self.timer_unit1_core0_stall_en(),
             )
             .field(
                 "timer_unit0_core1_stall_en",
-                &format_args!("{}", self.timer_unit0_core1_stall_en().bit()),
+                &self.timer_unit0_core1_stall_en(),
             )
             .field(
                 "timer_unit0_core0_stall_en",
-                &format_args!("{}", self.timer_unit0_core0_stall_en().bit()),
+                &self.timer_unit0_core0_stall_en(),
             )
-            .field(
-                "timer_unit1_work_en",
-                &format_args!("{}", self.timer_unit1_work_en().bit()),
-            )
-            .field(
-                "timer_unit0_work_en",
-                &format_args!("{}", self.timer_unit0_work_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("timer_unit1_work_en", &self.timer_unit1_work_en())
+            .field("timer_unit0_work_en", &self.timer_unit0_work_en())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - systimer clock force on"]
     #[inline(always)]
diff --git a/esp32h2/src/systimer/date.rs b/esp32h2/src/systimer/date.rs
index 9e89ffaebb..629d8212a8 100644
--- a/esp32h2/src/systimer/date.rs
+++ b/esp32h2/src/systimer/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/systimer/int_ena.rs b/esp32h2/src/systimer/int_ena.rs
index 9afbd67324..bf39753584 100644
--- a/esp32h2/src/systimer/int_ena.rs
+++ b/esp32h2/src/systimer/int_ena.rs
@@ -42,18 +42,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "interupt(0-2) enable"]
     #[doc = ""]
diff --git a/esp32h2/src/systimer/int_raw.rs b/esp32h2/src/systimer/int_raw.rs
index 9487c30025..395cb8187f 100644
--- a/esp32h2/src/systimer/int_raw.rs
+++ b/esp32h2/src/systimer/int_raw.rs
@@ -42,18 +42,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "interupt(0-2) raw"]
     #[doc = ""]
diff --git a/esp32h2/src/systimer/int_st.rs b/esp32h2/src/systimer/int_st.rs
index 4c4d3c12f8..1dc503012b 100644
--- a/esp32h2/src/systimer/int_st.rs
+++ b/esp32h2/src/systimer/int_st.rs
@@ -38,18 +38,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "systimer interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/systimer/real_target/hi.rs b/esp32h2/src/systimer/real_target/hi.rs
index e37661f89a..10d4966ea0 100644
--- a/esp32h2/src/systimer/real_target/hi.rs
+++ b/esp32h2/src/systimer/real_target/hi.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi_ro", &format_args!("{}", self.hi_ro().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi_ro", &self.hi_ro()).finish()
     }
 }
 #[doc = "system timer comp0 actual target value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32h2/src/systimer/real_target/lo.rs b/esp32h2/src/systimer/real_target/lo.rs
index 6ba16447eb..2a8623e63b 100644
--- a/esp32h2/src/systimer/real_target/lo.rs
+++ b/esp32h2/src/systimer/real_target/lo.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo_ro", &format_args!("{}", self.lo_ro().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo_ro", &self.lo_ro()).finish()
     }
 }
 #[doc = "system timer comp0 actual target value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32h2/src/systimer/target_conf.rs b/esp32h2/src/systimer/target_conf.rs
index 351218e2ba..48184bd1f3 100644
--- a/esp32h2/src/systimer/target_conf.rs
+++ b/esp32h2/src/systimer/target_conf.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TARGET_CONF")
-            .field("period", &format_args!("{}", self.period().bits()))
-            .field("period_mode", &format_args!("{}", self.period_mode().bit()))
-            .field(
-                "timer_unit_sel",
-                &format_args!("{}", self.timer_unit_sel().bit()),
-            )
+            .field("period", &self.period())
+            .field("period_mode", &self.period_mode())
+            .field("timer_unit_sel", &self.timer_unit_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TARGET_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - target0 period"]
     #[inline(always)]
diff --git a/esp32h2/src/systimer/trgt/hi.rs b/esp32h2/src/systimer/trgt/hi.rs
index 9ba19aedd7..1bbcc8532f 100644
--- a/esp32h2/src/systimer/trgt/hi.rs
+++ b/esp32h2/src/systimer/trgt/hi.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/systimer/trgt/lo.rs b/esp32h2/src/systimer/trgt/lo.rs
index cf5618b115..870fcb7923 100644
--- a/esp32h2/src/systimer/trgt/lo.rs
+++ b/esp32h2/src/systimer/trgt/lo.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/systimer/unit_op.rs b/esp32h2/src/systimer/unit_op.rs
index 161504c169..5a004338a8 100644
--- a/esp32h2/src/systimer/unit_op.rs
+++ b/esp32h2/src/systimer/unit_op.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UNIT_OP")
-            .field("value_valid", &format_args!("{}", self.value_valid().bit()))
+            .field("value_valid", &self.value_valid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UNIT_OP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - update timer_unit0"]
     #[inline(always)]
diff --git a/esp32h2/src/systimer/unit_value/hi.rs b/esp32h2/src/systimer/unit_value/hi.rs
index 3cd25b4d55..10523f249f 100644
--- a/esp32h2/src/systimer/unit_value/hi.rs
+++ b/esp32h2/src/systimer/unit_value/hi.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HI")
-            .field("value_hi", &format_args!("{}", self.value_hi().bits()))
+            .field("value_hi", &self.value_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "system timer unit0 value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HI_SPEC;
 impl crate::RegisterSpec for HI_SPEC {
diff --git a/esp32h2/src/systimer/unit_value/lo.rs b/esp32h2/src/systimer/unit_value/lo.rs
index a60743963d..92c3f4e991 100644
--- a/esp32h2/src/systimer/unit_value/lo.rs
+++ b/esp32h2/src/systimer/unit_value/lo.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LO")
-            .field("value_lo", &format_args!("{}", self.value_lo().bits()))
+            .field("value_lo", &self.value_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "system timer unit0 value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LO_SPEC;
 impl crate::RegisterSpec for LO_SPEC {
diff --git a/esp32h2/src/systimer/unitload/hi.rs b/esp32h2/src/systimer/unitload/hi.rs
index 3d663b8225..a758293265 100644
--- a/esp32h2/src/systimer/unitload/hi.rs
+++ b/esp32h2/src/systimer/unitload/hi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - timer unit0 load high 20 bits"]
     #[inline(always)]
diff --git a/esp32h2/src/systimer/unitload/lo.rs b/esp32h2/src/systimer/unitload/lo.rs
index 15e267cf3c..e01c2efb83 100644
--- a/esp32h2/src/systimer/unitload/lo.rs
+++ b/esp32h2/src/systimer/unitload/lo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - timer unit0 load low 32 bits"]
     #[inline(always)]
diff --git a/esp32h2/src/tee/clock_gate.rs b/esp32h2/src/tee/clock_gate.rs
index b2c147f4a9..0c07ea99d2 100644
--- a/esp32h2/src/tee/clock_gate.rs
+++ b/esp32h2/src/tee/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_clk_en"]
     #[inline(always)]
diff --git a/esp32h2/src/tee/date.rs b/esp32h2/src/tee/date.rs
index 4b1f6a075c..dba4e88829 100644
--- a/esp32h2/src/tee/date.rs
+++ b/esp32h2/src/tee/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/tee/m_mode_ctrl.rs b/esp32h2/src/tee/m_mode_ctrl.rs
index d67dc483be..59ebfc27ec 100644
--- a/esp32h2/src/tee/m_mode_ctrl.rs
+++ b/esp32h2/src/tee/m_mode_ctrl.rs
@@ -100,16 +100,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("M_MODE_CTRL")
-            .field("mode", &format_args!("{}", self.mode().bits()))
+            .field("mode", &self.mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MODE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode"]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/int_ena_timers.rs b/esp32h2/src/timg0/int_ena_timers.rs
index 8171c5599d..851aed4658 100644
--- a/esp32h2/src/timg0/int_ena_timers.rs
+++ b/esp32h2/src/timg0/int_ena_timers.rs
@@ -41,17 +41,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the TIMG_T(0-0)_INT interrupt."]
     #[doc = ""]
diff --git a/esp32h2/src/timg0/int_raw_timers.rs b/esp32h2/src/timg0/int_raw_timers.rs
index b0a2087cba..4774f3725d 100644
--- a/esp32h2/src/timg0/int_raw_timers.rs
+++ b/esp32h2/src/timg0/int_raw_timers.rs
@@ -35,17 +35,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_TIMERS_SPEC;
 impl crate::RegisterSpec for INT_RAW_TIMERS_SPEC {
diff --git a/esp32h2/src/timg0/int_st_timers.rs b/esp32h2/src/timg0/int_st_timers.rs
index f79f0e92cf..81866103ca 100644
--- a/esp32h2/src/timg0/int_st_timers.rs
+++ b/esp32h2/src/timg0/int_st_timers.rs
@@ -35,17 +35,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_TIMERS_SPEC;
 impl crate::RegisterSpec for INT_ST_TIMERS_SPEC {
diff --git a/esp32h2/src/timg0/ntimers_date.rs b/esp32h2/src/timg0/ntimers_date.rs
index b2ff41af46..8945775cb4 100644
--- a/esp32h2/src/timg0/ntimers_date.rs
+++ b/esp32h2/src/timg0/ntimers_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NTIMERS_DATE")
-            .field(
-                "ntimgs_date",
-                &format_args!("{}", self.ntimgs_date().bits()),
-            )
+            .field("ntimgs_date", &self.ntimgs_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NTIMERS_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Timer version control register"]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/regclk.rs b/esp32h2/src/timg0/regclk.rs
index 0f90e1dc73..7449dd5019 100644
--- a/esp32h2/src/timg0/regclk.rs
+++ b/esp32h2/src/timg0/regclk.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGCLK")
-            .field("etm_en", &format_args!("{}", self.etm_en().bit()))
-            .field(
-                "wdt_clk_is_active",
-                &format_args!("{}", self.wdt_clk_is_active().bit()),
-            )
-            .field(
-                "timer_clk_is_active",
-                &format_args!("{}", self.timer_clk_is_active().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("etm_en", &self.etm_en())
+            .field("wdt_clk_is_active", &self.wdt_clk_is_active())
+            .field("timer_clk_is_active", &self.timer_clk_is_active())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - enable timer's etm task and event"]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/rtccalicfg.rs b/esp32h2/src/timg0/rtccalicfg.rs
index 25a598caa6..cac5ef6711 100644
--- a/esp32h2/src/timg0/rtccalicfg.rs
+++ b/esp32h2/src/timg0/rtccalicfg.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG")
-            .field(
-                "rtc_cali_start_cycling",
-                &format_args!("{}", self.rtc_cali_start_cycling().bit()),
-            )
-            .field(
-                "rtc_cali_clk_sel",
-                &format_args!("{}", self.rtc_cali_clk_sel().bits()),
-            )
-            .field(
-                "rtc_cali_rdy",
-                &format_args!("{}", self.rtc_cali_rdy().bit()),
-            )
-            .field(
-                "rtc_cali_max",
-                &format_args!("{}", self.rtc_cali_max().bits()),
-            )
-            .field(
-                "rtc_cali_start",
-                &format_args!("{}", self.rtc_cali_start().bit()),
-            )
+            .field("rtc_cali_start_cycling", &self.rtc_cali_start_cycling())
+            .field("rtc_cali_clk_sel", &self.rtc_cali_clk_sel())
+            .field("rtc_cali_rdy", &self.rtc_cali_rdy())
+            .field("rtc_cali_max", &self.rtc_cali_max())
+            .field("rtc_cali_start", &self.rtc_cali_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - 0: one-shot frequency calculation,1: periodic frequency calculation,"]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/rtccalicfg1.rs b/esp32h2/src/timg0/rtccalicfg1.rs
index 318e8b0ff7..fc1a1dee84 100644
--- a/esp32h2/src/timg0/rtccalicfg1.rs
+++ b/esp32h2/src/timg0/rtccalicfg1.rs
@@ -22,21 +22,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("RTCCALICFG1")
             .field(
                 "rtc_cali_cycling_data_vld",
-                &format_args!("{}", self.rtc_cali_cycling_data_vld().bit()),
-            )
-            .field(
-                "rtc_cali_value",
-                &format_args!("{}", self.rtc_cali_value().bits()),
+                &self.rtc_cali_cycling_data_vld(),
             )
+            .field("rtc_cali_value", &self.rtc_cali_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC calibration configure1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtccalicfg1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTCCALICFG1_SPEC;
 impl crate::RegisterSpec for RTCCALICFG1_SPEC {
diff --git a/esp32h2/src/timg0/rtccalicfg2.rs b/esp32h2/src/timg0/rtccalicfg2.rs
index a0ea39a67b..2142857b29 100644
--- a/esp32h2/src/timg0/rtccalicfg2.rs
+++ b/esp32h2/src/timg0/rtccalicfg2.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG2")
-            .field(
-                "rtc_cali_timeout",
-                &format_args!("{}", self.rtc_cali_timeout().bit()),
-            )
-            .field(
-                "rtc_cali_timeout_rst_cnt",
-                &format_args!("{}", self.rtc_cali_timeout_rst_cnt().bits()),
-            )
-            .field(
-                "rtc_cali_timeout_thres",
-                &format_args!("{}", self.rtc_cali_timeout_thres().bits()),
-            )
+            .field("rtc_cali_timeout", &self.rtc_cali_timeout())
+            .field("rtc_cali_timeout_rst_cnt", &self.rtc_cali_timeout_rst_cnt())
+            .field("rtc_cali_timeout_thres", &self.rtc_cali_timeout_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:6 - Cycles that release calibration timeout reset"]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/t/alarmhi.rs b/esp32h2/src/timg0/t/alarmhi.rs
index edd0b2a2a2..fcba374986 100644
--- a/esp32h2/src/timg0/t/alarmhi.rs
+++ b/esp32h2/src/timg0/t/alarmhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMHI")
-            .field("alarm_hi", &format_args!("{}", self.alarm_hi().bits()))
+            .field("alarm_hi", &self.alarm_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Timer %s alarm trigger time-base counter value, high 22 bits."]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/t/alarmlo.rs b/esp32h2/src/timg0/t/alarmlo.rs
index 498db1e4af..49ecd50884 100644
--- a/esp32h2/src/timg0/t/alarmlo.rs
+++ b/esp32h2/src/timg0/t/alarmlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMLO")
-            .field("alarm_lo", &format_args!("{}", self.alarm_lo().bits()))
+            .field("alarm_lo", &self.alarm_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Timer %s alarm trigger time-base counter value, low 32 bits."]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/t/config.rs b/esp32h2/src/timg0/t/config.rs
index 4f94cffd85..498be19d87 100644
--- a/esp32h2/src/timg0/t/config.rs
+++ b/esp32h2/src/timg0/t/config.rs
@@ -64,21 +64,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG")
-            .field("use_xtal", &format_args!("{}", self.use_xtal().bit()))
-            .field("alarm_en", &format_args!("{}", self.alarm_en().bit()))
-            .field("divider", &format_args!("{}", self.divider().bits()))
-            .field("autoreload", &format_args!("{}", self.autoreload().bit()))
-            .field("increase", &format_args!("{}", self.increase().bit()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("use_xtal", &self.use_xtal())
+            .field("alarm_en", &self.alarm_en())
+            .field("divider", &self.divider())
+            .field("autoreload", &self.autoreload())
+            .field("increase", &self.increase())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/t/hi.rs b/esp32h2/src/timg0/t/hi.rs
index 0a24b62b63..7bf96de0ea 100644
--- a/esp32h2/src/timg0/t/hi.rs
+++ b/esp32h2/src/timg0/t/hi.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
     }
 }
 #[doc = "Timer %s current value, high 22 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32h2/src/timg0/t/lo.rs b/esp32h2/src/timg0/t/lo.rs
index 973812bd12..40cb61bb7b 100644
--- a/esp32h2/src/timg0/t/lo.rs
+++ b/esp32h2/src/timg0/t/lo.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
     }
 }
 #[doc = "Timer %s current value, low 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32h2/src/timg0/t/loadhi.rs b/esp32h2/src/timg0/t/loadhi.rs
index a069a77d70..14ce76e51c 100644
--- a/esp32h2/src/timg0/t/loadhi.rs
+++ b/esp32h2/src/timg0/t/loadhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADHI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - High 22 bits of the value that a reload will load onto timer %s time-base counter."]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/t/loadlo.rs b/esp32h2/src/timg0/t/loadlo.rs
index cd932cce0b..ed74e0c51d 100644
--- a/esp32h2/src/timg0/t/loadlo.rs
+++ b/esp32h2/src/timg0/t/loadlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADLO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Low 32 bits of the value that a reload will load onto timer %s time-base Counter."]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/t/update.rs b/esp32h2/src/timg0/t/update.rs
index dda84cfacc..bff3589c08 100644
--- a/esp32h2/src/timg0/t/update.rs
+++ b/esp32h2/src/timg0/t/update.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE")
-            .field("update", &format_args!("{}", self.update().bit()))
+            .field("update", &self.update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched."]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/wdtconfig0.rs b/esp32h2/src/timg0/wdtconfig0.rs
index e45eea5e24..e8c89534d7 100644
--- a/esp32h2/src/timg0/wdtconfig0.rs
+++ b/esp32h2/src/timg0/wdtconfig0.rs
@@ -109,44 +109,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG0")
-            .field(
-                "wdt_appcpu_reset_en",
-                &format_args!("{}", self.wdt_appcpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field(
-                "wdt_use_xtal",
-                &format_args!("{}", self.wdt_use_xtal().bit()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_use_xtal", &self.wdt_use_xtal())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - WDT reset CPU enable."]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/wdtconfig1.rs b/esp32h2/src/timg0/wdtconfig1.rs
index 29740ede70..225f2e7355 100644
--- a/esp32h2/src/timg0/wdtconfig1.rs
+++ b/esp32h2/src/timg0/wdtconfig1.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG1")
-            .field(
-                "wdt_clk_prescale",
-                &format_args!("{}", self.wdt_clk_prescale().bits()),
-            )
+            .field("wdt_clk_prescale", &self.wdt_clk_prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, WDT 's clock divider counter will be reset."]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/wdtconfig2.rs b/esp32h2/src/timg0/wdtconfig2.rs
index f6646544fa..70947ea581 100644
--- a/esp32h2/src/timg0/wdtconfig2.rs
+++ b/esp32h2/src/timg0/wdtconfig2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG2")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 0 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/wdtconfig3.rs b/esp32h2/src/timg0/wdtconfig3.rs
index da0cf49ce2..63b4ed60f6 100644
--- a/esp32h2/src/timg0/wdtconfig3.rs
+++ b/esp32h2/src/timg0/wdtconfig3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG3")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 1 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/wdtconfig4.rs b/esp32h2/src/timg0/wdtconfig4.rs
index 2bbbc5bfe8..d132842f1f 100644
--- a/esp32h2/src/timg0/wdtconfig4.rs
+++ b/esp32h2/src/timg0/wdtconfig4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG4")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 2 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/wdtconfig5.rs b/esp32h2/src/timg0/wdtconfig5.rs
index 661482c54b..d101561533 100644
--- a/esp32h2/src/timg0/wdtconfig5.rs
+++ b/esp32h2/src/timg0/wdtconfig5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG5")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 3 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32h2/src/timg0/wdtwprotect.rs b/esp32h2/src/timg0/wdtwprotect.rs
index 44efc107f3..ca73442322 100644
--- a/esp32h2/src/timg0/wdtwprotect.rs
+++ b/esp32h2/src/timg0/wdtwprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTWPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTWPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - If the register contains a different value than its reset value, write protection is enabled."]
     #[inline(always)]
diff --git a/esp32h2/src/trace/clock_gate.rs b/esp32h2/src/trace/clock_gate.rs
index 9396387567..1798054b1a 100644
--- a/esp32h2/src/trace/clock_gate.rs
+++ b/esp32h2/src/trace/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable clock gate when access all registers in this module."]
     #[inline(always)]
diff --git a/esp32h2/src/trace/date.rs b/esp32h2/src/trace/date.rs
index 222105ff2e..f4068dc68f 100644
--- a/esp32h2/src/trace/date.rs
+++ b/esp32h2/src/trace/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/trace/fifo_status.rs b/esp32h2/src/trace/fifo_status.rs
index ac231abf3f..3729545fa7 100644
--- a/esp32h2/src/trace/fifo_status.rs
+++ b/esp32h2/src/trace/fifo_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_STATUS")
-            .field("fifo_empty", &format_args!("{}", self.fifo_empty().bit()))
-            .field("work_status", &format_args!("{}", self.work_status().bit()))
+            .field("fifo_empty", &self.fifo_empty())
+            .field("work_status", &self.work_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "fifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_STATUS_SPEC;
 impl crate::RegisterSpec for FIFO_STATUS_SPEC {
diff --git a/esp32h2/src/trace/intr_ena.rs b/esp32h2/src/trace/intr_ena.rs
index b5a4e078fe..e225fd8298 100644
--- a/esp32h2/src/trace/intr_ena.rs
+++ b/esp32h2/src/trace/intr_ena.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_ENA")
-            .field(
-                "fifo_overflow_intr_ena",
-                &format_args!("{}", self.fifo_overflow_intr_ena().bit()),
-            )
-            .field(
-                "mem_full_intr_ena",
-                &format_args!("{}", self.mem_full_intr_ena().bit()),
-            )
+            .field("fifo_overflow_intr_ena", &self.fifo_overflow_intr_ena())
+            .field("mem_full_intr_ena", &self.mem_full_intr_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 enable fifo_overflow interrupt"]
     #[inline(always)]
diff --git a/esp32h2/src/trace/intr_raw.rs b/esp32h2/src/trace/intr_raw.rs
index 83cb40c5ec..1393d7f17a 100644
--- a/esp32h2/src/trace/intr_raw.rs
+++ b/esp32h2/src/trace/intr_raw.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_RAW")
-            .field(
-                "fifo_overflow_intr_raw",
-                &format_args!("{}", self.fifo_overflow_intr_raw().bit()),
-            )
-            .field(
-                "mem_full_intr_raw",
-                &format_args!("{}", self.mem_full_intr_raw().bit()),
-            )
+            .field("fifo_overflow_intr_raw", &self.fifo_overflow_intr_raw())
+            .field("mem_full_intr_raw", &self.mem_full_intr_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_RAW_SPEC;
 impl crate::RegisterSpec for INTR_RAW_SPEC {
diff --git a/esp32h2/src/trace/mem_current_addr.rs b/esp32h2/src/trace/mem_current_addr.rs
index 854038cd82..611af268e9 100644
--- a/esp32h2/src/trace/mem_current_addr.rs
+++ b/esp32h2/src/trace/mem_current_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CURRENT_ADDR")
-            .field(
-                "mem_current_addr",
-                &format_args!("{}", self.mem_current_addr().bits()),
-            )
+            .field("mem_current_addr", &self.mem_current_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CURRENT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem current addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_current_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_CURRENT_ADDR_SPEC;
 impl crate::RegisterSpec for MEM_CURRENT_ADDR_SPEC {
diff --git a/esp32h2/src/trace/mem_end_addr.rs b/esp32h2/src/trace/mem_end_addr.rs
index 78675b80a6..de089e6fdb 100644
--- a/esp32h2/src/trace/mem_end_addr.rs
+++ b/esp32h2/src/trace/mem_end_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_END_ADDR")
-            .field(
-                "mem_end_addr",
-                &format_args!("{}", self.mem_end_addr().bits()),
-            )
+            .field("mem_end_addr", &self.mem_end_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_END_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The end address of trace memory"]
     #[inline(always)]
diff --git a/esp32h2/src/trace/mem_start_addr.rs b/esp32h2/src/trace/mem_start_addr.rs
index 4528e0e3df..f6b8320336 100644
--- a/esp32h2/src/trace/mem_start_addr.rs
+++ b/esp32h2/src/trace/mem_start_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_START_ADDR")
-            .field(
-                "mem_start_addr",
-                &format_args!("{}", self.mem_start_addr().bits()),
-            )
+            .field("mem_start_addr", &self.mem_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The start address of trace memory"]
     #[inline(always)]
diff --git a/esp32h2/src/trace/resync_prolonged.rs b/esp32h2/src/trace/resync_prolonged.rs
index 039a306aa7..dbe51e2e69 100644
--- a/esp32h2/src/trace/resync_prolonged.rs
+++ b/esp32h2/src/trace/resync_prolonged.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESYNC_PROLONGED")
-            .field(
-                "resync_prolonged",
-                &format_args!("{}", self.resync_prolonged().bits()),
-            )
-            .field("resync_mode", &format_args!("{}", self.resync_mode().bit()))
+            .field("resync_prolonged", &self.resync_prolonged())
+            .field("resync_mode", &self.resync_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESYNC_PROLONGED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - count number, when count to this value, send a sync package"]
     #[inline(always)]
diff --git a/esp32h2/src/trace/trigger.rs b/esp32h2/src/trace/trigger.rs
index cadb5527f4..9c724804b5 100644
--- a/esp32h2/src/trace/trigger.rs
+++ b/esp32h2/src/trace/trigger.rs
@@ -30,17 +30,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TRIGGER")
-            .field("mem_loop", &format_args!("{}", self.mem_loop().bit()))
-            .field("restart_ena", &format_args!("{}", self.restart_ena().bit()))
+            .field("mem_loop", &self.mem_loop())
+            .field("restart_ena", &self.restart_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TRIGGER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 0\\] set 1 start trace."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/arb_lost_cap.rs b/esp32h2/src/twai0/arb_lost_cap.rs
index 0e326e937c..edf5c834a7 100644
--- a/esp32h2/src/twai0/arb_lost_cap.rs
+++ b/esp32h2/src/twai0/arb_lost_cap.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_LOST_CAP")
-            .field(
-                "arbitration_lost_capture",
-                &format_args!("{}", self.arbitration_lost_capture().bits()),
-            )
+            .field("arbitration_lost_capture", &self.arbitration_lost_capture())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_LOST_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TWAI arbiter lost capture register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_lost_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ARB_LOST_CAP_SPEC;
 impl crate::RegisterSpec for ARB_LOST_CAP_SPEC {
diff --git a/esp32h2/src/twai0/bus_timing_0.rs b/esp32h2/src/twai0/bus_timing_0.rs
index 114b14ed9f..d416d38de6 100644
--- a/esp32h2/src/twai0/bus_timing_0.rs
+++ b/esp32h2/src/twai0/bus_timing_0.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMING_0")
-            .field("baud_presc", &format_args!("{}", self.baud_presc().bits()))
-            .field(
-                "sync_jump_width",
-                &format_args!("{}", self.sync_jump_width().bits()),
-            )
+            .field("baud_presc", &self.baud_presc())
+            .field("sync_jump_width", &self.sync_jump_width())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMING_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/bus_timing_1.rs b/esp32h2/src/twai0/bus_timing_1.rs
index 9ae19a0e35..caf2d91800 100644
--- a/esp32h2/src/twai0/bus_timing_1.rs
+++ b/esp32h2/src/twai0/bus_timing_1.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMING_1")
-            .field("time_seg1", &format_args!("{}", self.time_seg1().bits()))
-            .field("time_seg2", &format_args!("{}", self.time_seg2().bits()))
-            .field("time_samp", &format_args!("{}", self.time_samp().bit()))
+            .field("time_seg1", &self.time_seg1())
+            .field("time_seg2", &self.time_seg2())
+            .field("time_samp", &self.time_samp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMING_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/clock_divider.rs b/esp32h2/src/twai0/clock_divider.rs
index f5e7eb3181..e505a254ad 100644
--- a/esp32h2/src/twai0/clock_divider.rs
+++ b/esp32h2/src/twai0/clock_divider.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_DIVIDER")
-            .field("cd", &format_args!("{}", self.cd().bits()))
-            .field("clock_off", &format_args!("{}", self.clock_off().bit()))
+            .field("cd", &self.cd())
+            .field("clock_off", &self.clock_off())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_DIVIDER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - These bits are used to define the frequency at the external CLKOUT pin."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/data_0.rs b/esp32h2/src/twai0/data_0.rs
index e8196950d7..fa26d91abc 100644
--- a/esp32h2/src/twai0/data_0.rs
+++ b/esp32h2/src/twai0/data_0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_0")
-            .field("tx_byte_0", &format_args!("{}", self.tx_byte_0().bits()))
+            .field("tx_byte_0", &self.tx_byte_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/data_1.rs b/esp32h2/src/twai0/data_1.rs
index 923271d63e..2f62cfd10c 100644
--- a/esp32h2/src/twai0/data_1.rs
+++ b/esp32h2/src/twai0/data_1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_1")
-            .field("tx_byte_1", &format_args!("{}", self.tx_byte_1().bits()))
+            .field("tx_byte_1", &self.tx_byte_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/data_10.rs b/esp32h2/src/twai0/data_10.rs
index 940b00514c..a37b7fabbd 100644
--- a/esp32h2/src/twai0/data_10.rs
+++ b/esp32h2/src/twai0/data_10.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_10")
-            .field("tx_byte_10", &format_args!("{}", self.tx_byte_10().bits()))
+            .field("tx_byte_10", &self.tx_byte_10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/data_11.rs b/esp32h2/src/twai0/data_11.rs
index c862405bb0..d9b4bfe1b3 100644
--- a/esp32h2/src/twai0/data_11.rs
+++ b/esp32h2/src/twai0/data_11.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_11")
-            .field("tx_byte_11", &format_args!("{}", self.tx_byte_11().bits()))
+            .field("tx_byte_11", &self.tx_byte_11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/data_12.rs b/esp32h2/src/twai0/data_12.rs
index 9a4ad84336..3db488d13f 100644
--- a/esp32h2/src/twai0/data_12.rs
+++ b/esp32h2/src/twai0/data_12.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_12")
-            .field("tx_byte_12", &format_args!("{}", self.tx_byte_12().bits()))
+            .field("tx_byte_12", &self.tx_byte_12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/data_2.rs b/esp32h2/src/twai0/data_2.rs
index 6b6513eb15..1da66f7dfd 100644
--- a/esp32h2/src/twai0/data_2.rs
+++ b/esp32h2/src/twai0/data_2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_2")
-            .field("tx_byte_2", &format_args!("{}", self.tx_byte_2().bits()))
+            .field("tx_byte_2", &self.tx_byte_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/data_3.rs b/esp32h2/src/twai0/data_3.rs
index a859f35788..1afe43898b 100644
--- a/esp32h2/src/twai0/data_3.rs
+++ b/esp32h2/src/twai0/data_3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_3")
-            .field("tx_byte_3", &format_args!("{}", self.tx_byte_3().bits()))
+            .field("tx_byte_3", &self.tx_byte_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/data_4.rs b/esp32h2/src/twai0/data_4.rs
index 0ca09120f6..b4ecde3be3 100644
--- a/esp32h2/src/twai0/data_4.rs
+++ b/esp32h2/src/twai0/data_4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_4")
-            .field("tx_byte_4", &format_args!("{}", self.tx_byte_4().bits()))
+            .field("tx_byte_4", &self.tx_byte_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/data_5.rs b/esp32h2/src/twai0/data_5.rs
index 92d292f07c..eeb176fc6e 100644
--- a/esp32h2/src/twai0/data_5.rs
+++ b/esp32h2/src/twai0/data_5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_5")
-            .field("tx_byte_5", &format_args!("{}", self.tx_byte_5().bits()))
+            .field("tx_byte_5", &self.tx_byte_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/data_6.rs b/esp32h2/src/twai0/data_6.rs
index 76ce4f79b4..d698884c88 100644
--- a/esp32h2/src/twai0/data_6.rs
+++ b/esp32h2/src/twai0/data_6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_6")
-            .field("tx_byte_6", &format_args!("{}", self.tx_byte_6().bits()))
+            .field("tx_byte_6", &self.tx_byte_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/data_7.rs b/esp32h2/src/twai0/data_7.rs
index ce96ddfd73..9fa633d1b7 100644
--- a/esp32h2/src/twai0/data_7.rs
+++ b/esp32h2/src/twai0/data_7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_7")
-            .field("tx_byte_7", &format_args!("{}", self.tx_byte_7().bits()))
+            .field("tx_byte_7", &self.tx_byte_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/data_8.rs b/esp32h2/src/twai0/data_8.rs
index b419274e19..e2108471cc 100644
--- a/esp32h2/src/twai0/data_8.rs
+++ b/esp32h2/src/twai0/data_8.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_8")
-            .field("tx_byte_8", &format_args!("{}", self.tx_byte_8().bits()))
+            .field("tx_byte_8", &self.tx_byte_8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/data_9.rs b/esp32h2/src/twai0/data_9.rs
index 13e7db3f84..0ef7400896 100644
--- a/esp32h2/src/twai0/data_9.rs
+++ b/esp32h2/src/twai0/data_9.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_9")
-            .field("tx_byte_9", &format_args!("{}", self.tx_byte_9().bits()))
+            .field("tx_byte_9", &self.tx_byte_9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/eco_cfg.rs b/esp32h2/src/twai0/eco_cfg.rs
index 7928138cdb..2174ebda7d 100644
--- a/esp32h2/src/twai0/eco_cfg.rs
+++ b/esp32h2/src/twai0/eco_cfg.rs
@@ -24,17 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_CFG")
-            .field("rdn_ena", &format_args!("{}", self.rdn_ena().bit()))
-            .field("rdn_result", &format_args!("{}", self.rdn_result().bit()))
+            .field("rdn_ena", &self.rdn_ena())
+            .field("rdn_result", &self.rdn_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable eco module."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/err_code_cap.rs b/esp32h2/src/twai0/err_code_cap.rs
index b32b4db0e1..189911898e 100644
--- a/esp32h2/src/twai0/err_code_cap.rs
+++ b/esp32h2/src/twai0/err_code_cap.rs
@@ -27,27 +27,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERR_CODE_CAP")
-            .field(
-                "err_capture_code_segment",
-                &format_args!("{}", self.err_capture_code_segment().bits()),
-            )
+            .field("err_capture_code_segment", &self.err_capture_code_segment())
             .field(
                 "err_capture_code_direction",
-                &format_args!("{}", self.err_capture_code_direction().bit()),
-            )
-            .field(
-                "err_capture_code_type",
-                &format_args!("{}", self.err_capture_code_type().bits()),
+                &self.err_capture_code_direction(),
             )
+            .field("err_capture_code_type", &self.err_capture_code_type())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERR_CODE_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TWAI error info capture register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_code_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ERR_CODE_CAP_SPEC;
 impl crate::RegisterSpec for ERR_CODE_CAP_SPEC {
diff --git a/esp32h2/src/twai0/err_warning_limit.rs b/esp32h2/src/twai0/err_warning_limit.rs
index c3d6ab8f2f..9c78f60158 100644
--- a/esp32h2/src/twai0/err_warning_limit.rs
+++ b/esp32h2/src/twai0/err_warning_limit.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERR_WARNING_LIMIT")
-            .field(
-                "err_warning_limit",
-                &format_args!("{}", self.err_warning_limit().bits()),
-            )
+            .field("err_warning_limit", &self.err_warning_limit())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERR_WARNING_LIMIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/hw_cfg.rs b/esp32h2/src/twai0/hw_cfg.rs
index d4b499209c..4f7c21ba6b 100644
--- a/esp32h2/src/twai0/hw_cfg.rs
+++ b/esp32h2/src/twai0/hw_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HW_CFG")
-            .field(
-                "hw_standby_en",
-                &format_args!("{}", self.hw_standby_en().bit()),
-            )
+            .field("hw_standby_en", &self.hw_standby_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HW_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable function that hardware control standby pin."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/hw_standby_cnt.rs b/esp32h2/src/twai0/hw_standby_cnt.rs
index 1aabc9964c..a41e6ee631 100644
--- a/esp32h2/src/twai0/hw_standby_cnt.rs
+++ b/esp32h2/src/twai0/hw_standby_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HW_STANDBY_CNT")
-            .field(
-                "standby_wait_cnt",
-                &format_args!("{}", self.standby_wait_cnt().bits()),
-            )
+            .field("standby_wait_cnt", &self.standby_wait_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HW_STANDBY_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/idle_intr_cnt.rs b/esp32h2/src/twai0/idle_intr_cnt.rs
index 9a4baf45b7..444052985e 100644
--- a/esp32h2/src/twai0/idle_intr_cnt.rs
+++ b/esp32h2/src/twai0/idle_intr_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDLE_INTR_CNT")
-            .field(
-                "idle_intr_cnt",
-                &format_args!("{}", self.idle_intr_cnt().bits()),
-            )
+            .field("idle_intr_cnt", &self.idle_intr_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_INTR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configure the number of cycles before triggering idle interrupt."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/interrupt.rs b/esp32h2/src/twai0/interrupt.rs
index 66fce19eca..77a31f9184 100644
--- a/esp32h2/src/twai0/interrupt.rs
+++ b/esp32h2/src/twai0/interrupt.rs
@@ -62,44 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT")
-            .field(
-                "receive_int_st",
-                &format_args!("{}", self.receive_int_st().bit()),
-            )
-            .field(
-                "transmit_int_st",
-                &format_args!("{}", self.transmit_int_st().bit()),
-            )
-            .field(
-                "err_warning_int_st",
-                &format_args!("{}", self.err_warning_int_st().bit()),
-            )
-            .field(
-                "data_overrun_int_st",
-                &format_args!("{}", self.data_overrun_int_st().bit()),
-            )
-            .field(
-                "err_passive_int_st",
-                &format_args!("{}", self.err_passive_int_st().bit()),
-            )
-            .field(
-                "arbitration_lost_int_st",
-                &format_args!("{}", self.arbitration_lost_int_st().bit()),
-            )
-            .field(
-                "bus_err_int_st",
-                &format_args!("{}", self.bus_err_int_st().bit()),
-            )
-            .field("idle_int_st", &format_args!("{}", self.idle_int_st().bit()))
+            .field("receive_int_st", &self.receive_int_st())
+            .field("transmit_int_st", &self.transmit_int_st())
+            .field("err_warning_int_st", &self.err_warning_int_st())
+            .field("data_overrun_int_st", &self.data_overrun_int_st())
+            .field("err_passive_int_st", &self.err_passive_int_st())
+            .field("arbitration_lost_int_st", &self.arbitration_lost_int_st())
+            .field("bus_err_int_st", &self.bus_err_int_st())
+            .field("idle_int_st", &self.idle_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt signals' register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERRUPT_SPEC;
 impl crate::RegisterSpec for INTERRUPT_SPEC {
diff --git a/esp32h2/src/twai0/interrupt_enable.rs b/esp32h2/src/twai0/interrupt_enable.rs
index 0d6f6fe8aa..e3554e69eb 100644
--- a/esp32h2/src/twai0/interrupt_enable.rs
+++ b/esp32h2/src/twai0/interrupt_enable.rs
@@ -78,47 +78,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT_ENABLE")
-            .field(
-                "ext_receive_int_ena",
-                &format_args!("{}", self.ext_receive_int_ena().bit()),
-            )
-            .field(
-                "ext_transmit_int_ena",
-                &format_args!("{}", self.ext_transmit_int_ena().bit()),
-            )
-            .field(
-                "ext_err_warning_int_ena",
-                &format_args!("{}", self.ext_err_warning_int_ena().bit()),
-            )
-            .field(
-                "ext_data_overrun_int_ena",
-                &format_args!("{}", self.ext_data_overrun_int_ena().bit()),
-            )
-            .field(
-                "err_passive_int_ena",
-                &format_args!("{}", self.err_passive_int_ena().bit()),
-            )
-            .field(
-                "arbitration_lost_int_ena",
-                &format_args!("{}", self.arbitration_lost_int_ena().bit()),
-            )
-            .field(
-                "bus_err_int_ena",
-                &format_args!("{}", self.bus_err_int_ena().bit()),
-            )
-            .field(
-                "idle_int_ena",
-                &format_args!("{}", self.idle_int_ena().bit()),
-            )
+            .field("ext_receive_int_ena", &self.ext_receive_int_ena())
+            .field("ext_transmit_int_ena", &self.ext_transmit_int_ena())
+            .field("ext_err_warning_int_ena", &self.ext_err_warning_int_ena())
+            .field("ext_data_overrun_int_ena", &self.ext_data_overrun_int_ena())
+            .field("err_passive_int_ena", &self.err_passive_int_ena())
+            .field("arbitration_lost_int_ena", &self.arbitration_lost_int_ena())
+            .field("bus_err_int_ena", &self.bus_err_int_ena())
+            .field("idle_int_ena", &self.idle_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable"]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/mode.rs b/esp32h2/src/twai0/mode.rs
index 2619ae327d..6ca205ae27 100644
--- a/esp32h2/src/twai0/mode.rs
+++ b/esp32h2/src/twai0/mode.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODE")
-            .field("reset_mode", &format_args!("{}", self.reset_mode().bit()))
-            .field(
-                "listen_only_mode",
-                &format_args!("{}", self.listen_only_mode().bit()),
-            )
-            .field(
-                "self_test_mode",
-                &format_args!("{}", self.self_test_mode().bit()),
-            )
-            .field(
-                "rx_filter_mode",
-                &format_args!("{}", self.rx_filter_mode().bit()),
-            )
+            .field("reset_mode", &self.reset_mode())
+            .field("listen_only_mode", &self.listen_only_mode())
+            .field("self_test_mode", &self.self_test_mode())
+            .field("rx_filter_mode", &self.rx_filter_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/rx_err_cnt.rs b/esp32h2/src/twai0/rx_err_cnt.rs
index 6c17a3b1b8..8919de4888 100644
--- a/esp32h2/src/twai0/rx_err_cnt.rs
+++ b/esp32h2/src/twai0/rx_err_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ERR_CNT")
-            .field("rx_err_cnt", &format_args!("{}", self.rx_err_cnt().bits()))
+            .field("rx_err_cnt", &self.rx_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ERR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/rx_message_cnt.rs b/esp32h2/src/twai0/rx_message_cnt.rs
index 7d99338e06..c5339669bd 100644
--- a/esp32h2/src/twai0/rx_message_cnt.rs
+++ b/esp32h2/src/twai0/rx_message_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_MESSAGE_CNT")
-            .field(
-                "rx_message_counter",
-                &format_args!("{}", self.rx_message_counter().bits()),
-            )
+            .field("rx_message_counter", &self.rx_message_counter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_MESSAGE_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Received message counter register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_message_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_MESSAGE_CNT_SPEC;
 impl crate::RegisterSpec for RX_MESSAGE_CNT_SPEC {
diff --git a/esp32h2/src/twai0/status.rs b/esp32h2/src/twai0/status.rs
index 530b818372..bff646e955 100644
--- a/esp32h2/src/twai0/status.rs
+++ b/esp32h2/src/twai0/status.rs
@@ -69,27 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rx_buf_st", &format_args!("{}", self.rx_buf_st().bit()))
-            .field("overrun", &format_args!("{}", self.overrun().bit()))
-            .field("tx_buf_st", &format_args!("{}", self.tx_buf_st().bit()))
-            .field(
-                "transmission_complete",
-                &format_args!("{}", self.transmission_complete().bit()),
-            )
-            .field("receive", &format_args!("{}", self.receive().bit()))
-            .field("transmit", &format_args!("{}", self.transmit().bit()))
-            .field("err", &format_args!("{}", self.err().bit()))
-            .field("bus_off_st", &format_args!("{}", self.bus_off_st().bit()))
-            .field("miss_st", &format_args!("{}", self.miss_st().bit()))
+            .field("rx_buf_st", &self.rx_buf_st())
+            .field("overrun", &self.overrun())
+            .field("tx_buf_st", &self.tx_buf_st())
+            .field("transmission_complete", &self.transmission_complete())
+            .field("receive", &self.receive())
+            .field("transmit", &self.transmit())
+            .field("err", &self.err())
+            .field("bus_off_st", &self.bus_off_st())
+            .field("miss_st", &self.miss_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TWAI status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32h2/src/twai0/sw_standby_cfg.rs b/esp32h2/src/twai0/sw_standby_cfg.rs
index 77eacb6cc3..7842ae7587 100644
--- a/esp32h2/src/twai0/sw_standby_cfg.rs
+++ b/esp32h2/src/twai0/sw_standby_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SW_STANDBY_CFG")
-            .field(
-                "sw_standby_en",
-                &format_args!("{}", self.sw_standby_en().bit()),
-            )
-            .field(
-                "sw_standby_clr",
-                &format_args!("{}", self.sw_standby_clr().bit()),
-            )
+            .field("sw_standby_en", &self.sw_standby_en())
+            .field("sw_standby_clr", &self.sw_standby_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SW_STANDBY_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable standby pin."]
     #[inline(always)]
diff --git a/esp32h2/src/twai0/tx_err_cnt.rs b/esp32h2/src/twai0/tx_err_cnt.rs
index 465da715b0..077faba61d 100644
--- a/esp32h2/src/twai0/tx_err_cnt.rs
+++ b/esp32h2/src/twai0/tx_err_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_ERR_CNT")
-            .field("tx_err_cnt", &format_args!("{}", self.tx_err_cnt().bits()))
+            .field("tx_err_cnt", &self.tx_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_ERR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/afifo_status.rs b/esp32h2/src/uart0/afifo_status.rs
index 32a27a7eed..22f55103b7 100644
--- a/esp32h2/src/uart0/afifo_status.rs
+++ b/esp32h2/src/uart0/afifo_status.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AFIFO_STATUS")
-            .field(
-                "tx_afifo_full",
-                &format_args!("{}", self.tx_afifo_full().bit()),
-            )
-            .field(
-                "tx_afifo_empty",
-                &format_args!("{}", self.tx_afifo_empty().bit()),
-            )
-            .field(
-                "rx_afifo_full",
-                &format_args!("{}", self.rx_afifo_full().bit()),
-            )
-            .field(
-                "rx_afifo_empty",
-                &format_args!("{}", self.rx_afifo_empty().bit()),
-            )
+            .field("tx_afifo_full", &self.tx_afifo_full())
+            .field("tx_afifo_empty", &self.tx_afifo_empty())
+            .field("rx_afifo_full", &self.rx_afifo_full())
+            .field("rx_afifo_empty", &self.rx_afifo_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART AFIFO Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`afifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for AFIFO_STATUS_SPEC {
diff --git a/esp32h2/src/uart0/at_cmd_char.rs b/esp32h2/src/uart0/at_cmd_char.rs
index 17e9222fe8..e75e1409cd 100644
--- a/esp32h2/src/uart0/at_cmd_char.rs
+++ b/esp32h2/src/uart0/at_cmd_char.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_CHAR")
-            .field(
-                "at_cmd_char",
-                &format_args!("{}", self.at_cmd_char().bits()),
-            )
-            .field("char_num", &format_args!("{}", self.char_num().bits()))
+            .field("at_cmd_char", &self.at_cmd_char())
+            .field("char_num", &self.char_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_CHAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/at_cmd_gaptout.rs b/esp32h2/src/uart0/at_cmd_gaptout.rs
index c7373436b0..7091ac8125 100644
--- a/esp32h2/src/uart0/at_cmd_gaptout.rs
+++ b/esp32h2/src/uart0/at_cmd_gaptout.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_GAPTOUT")
-            .field(
-                "rx_gap_tout",
-                &format_args!("{}", self.rx_gap_tout().bits()),
-            )
+            .field("rx_gap_tout", &self.rx_gap_tout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_GAPTOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the at_cmd chars."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/at_cmd_postcnt.rs b/esp32h2/src/uart0/at_cmd_postcnt.rs
index 078c4bb6a1..5db8445554 100644
--- a/esp32h2/src/uart0/at_cmd_postcnt.rs
+++ b/esp32h2/src/uart0/at_cmd_postcnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_POSTCNT")
-            .field(
-                "post_idle_num",
-                &format_args!("{}", self.post_idle_num().bits()),
-            )
+            .field("post_idle_num", &self.post_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_POSTCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the last at_cmd and the next data."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/at_cmd_precnt.rs b/esp32h2/src/uart0/at_cmd_precnt.rs
index 9e4a1cc58c..41790b5e67 100644
--- a/esp32h2/src/uart0/at_cmd_precnt.rs
+++ b/esp32h2/src/uart0/at_cmd_precnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_PRECNT")
-            .field(
-                "pre_idle_num",
-                &format_args!("{}", self.pre_idle_num().bits()),
-            )
+            .field("pre_idle_num", &self.pre_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_PRECNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first at_cmd is received by receiver."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/clk_conf.rs b/esp32h2/src/uart0/clk_conf.rs
index ad1f007ecf..0f1329ea23 100644
--- a/esp32h2/src/uart0/clk_conf.rs
+++ b/esp32h2/src/uart0/clk_conf.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field("tx_sclk_en", &format_args!("{}", self.tx_sclk_en().bit()))
-            .field("sclk_en", &format_args!("{}", self.sclk_en().bit()))
-            .field("tx_rst_core", &format_args!("{}", self.tx_rst_core().bit()))
-            .field("rst_core", &format_args!("{}", self.rst_core().bit()))
+            .field("tx_sclk_en", &self.tx_sclk_en())
+            .field("sclk_en", &self.sclk_en())
+            .field("tx_rst_core", &self.tx_rst_core())
+            .field("rst_core", &self.rst_core())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - Set this bit to enable UART Tx clock."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/clkdiv.rs b/esp32h2/src/uart0/clkdiv.rs
index c020543f66..0c1138e013 100644
--- a/esp32h2/src/uart0/clkdiv.rs
+++ b/esp32h2/src/uart0/clkdiv.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKDIV")
-            .field("clkdiv", &format_args!("{}", self.clkdiv().bits()))
-            .field("frag", &format_args!("{}", self.frag().bits()))
+            .field("clkdiv", &self.clkdiv())
+            .field("frag", &self.frag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKDIV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/conf0.rs b/esp32h2/src/uart0/conf0.rs
index 65ff6a9991..46ada52338 100644
--- a/esp32h2/src/uart0/conf0.rs
+++ b/esp32h2/src/uart0/conf0.rs
@@ -206,43 +206,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("parity", &format_args!("{}", self.parity().bit()))
-            .field("parity_en", &format_args!("{}", self.parity_en().bit()))
-            .field("bit_num", &format_args!("{}", self.bit_num().bits()))
-            .field(
-                "stop_bit_num",
-                &format_args!("{}", self.stop_bit_num().bits()),
-            )
-            .field("txd_brk", &format_args!("{}", self.txd_brk().bit()))
-            .field("irda_dplx", &format_args!("{}", self.irda_dplx().bit()))
-            .field("irda_tx_en", &format_args!("{}", self.irda_tx_en().bit()))
-            .field("irda_wctl", &format_args!("{}", self.irda_wctl().bit()))
-            .field("irda_tx_inv", &format_args!("{}", self.irda_tx_inv().bit()))
-            .field("irda_rx_inv", &format_args!("{}", self.irda_rx_inv().bit()))
-            .field("loopback", &format_args!("{}", self.loopback().bit()))
-            .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit()))
-            .field("irda_en", &format_args!("{}", self.irda_en().bit()))
-            .field("rxd_inv", &format_args!("{}", self.rxd_inv().bit()))
-            .field("txd_inv", &format_args!("{}", self.txd_inv().bit()))
-            .field(
-                "dis_rx_dat_ovf",
-                &format_args!("{}", self.dis_rx_dat_ovf().bit()),
-            )
-            .field("err_wr_mask", &format_args!("{}", self.err_wr_mask().bit()))
-            .field("autobaud_en", &format_args!("{}", self.autobaud_en().bit()))
-            .field("mem_clk_en", &format_args!("{}", self.mem_clk_en().bit()))
-            .field("sw_rts", &format_args!("{}", self.sw_rts().bit()))
-            .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit()))
-            .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit()))
+            .field("parity", &self.parity())
+            .field("parity_en", &self.parity_en())
+            .field("bit_num", &self.bit_num())
+            .field("stop_bit_num", &self.stop_bit_num())
+            .field("txd_brk", &self.txd_brk())
+            .field("irda_dplx", &self.irda_dplx())
+            .field("irda_tx_en", &self.irda_tx_en())
+            .field("irda_wctl", &self.irda_wctl())
+            .field("irda_tx_inv", &self.irda_tx_inv())
+            .field("irda_rx_inv", &self.irda_rx_inv())
+            .field("loopback", &self.loopback())
+            .field("tx_flow_en", &self.tx_flow_en())
+            .field("irda_en", &self.irda_en())
+            .field("rxd_inv", &self.rxd_inv())
+            .field("txd_inv", &self.txd_inv())
+            .field("dis_rx_dat_ovf", &self.dis_rx_dat_ovf())
+            .field("err_wr_mask", &self.err_wr_mask())
+            .field("autobaud_en", &self.autobaud_en())
+            .field("mem_clk_en", &self.mem_clk_en())
+            .field("sw_rts", &self.sw_rts())
+            .field("rxfifo_rst", &self.rxfifo_rst())
+            .field("txfifo_rst", &self.txfifo_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to configure the parity check mode."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/conf1.rs b/esp32h2/src/uart0/conf1.rs
index 9b3521035b..88d452abe5 100644
--- a/esp32h2/src/uart0/conf1.rs
+++ b/esp32h2/src/uart0/conf1.rs
@@ -80,29 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "rxfifo_full_thrhd",
-                &format_args!("{}", self.rxfifo_full_thrhd().bits()),
-            )
-            .field(
-                "txfifo_empty_thrhd",
-                &format_args!("{}", self.txfifo_empty_thrhd().bits()),
-            )
-            .field("cts_inv", &format_args!("{}", self.cts_inv().bit()))
-            .field("dsr_inv", &format_args!("{}", self.dsr_inv().bit()))
-            .field("rts_inv", &format_args!("{}", self.rts_inv().bit()))
-            .field("dtr_inv", &format_args!("{}", self.dtr_inv().bit()))
-            .field("sw_dtr", &format_args!("{}", self.sw_dtr().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("rxfifo_full_thrhd", &self.rxfifo_full_thrhd())
+            .field("txfifo_empty_thrhd", &self.txfifo_empty_thrhd())
+            .field("cts_inv", &self.cts_inv())
+            .field("dsr_inv", &self.dsr_inv())
+            .field("rts_inv", &self.rts_inv())
+            .field("dtr_inv", &self.dtr_inv())
+            .field("sw_dtr", &self.sw_dtr())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/date.rs b/esp32h2/src/uart0/date.rs
index 8c9df1b8f4..cc76677bd0 100644
--- a/esp32h2/src/uart0/date.rs
+++ b/esp32h2/src/uart0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/uart0/fifo.rs b/esp32h2/src/uart0/fifo.rs
index 3ea719e7ab..fdc9ee6700 100644
--- a/esp32h2/src/uart0/fifo.rs
+++ b/esp32h2/src/uart0/fifo.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO")
-            .field(
-                "rxfifo_rd_byte",
-                &format_args!("{}", self.rxfifo_rd_byte().bits()),
-            )
+            .field("rxfifo_rd_byte", &self.rxfifo_rd_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - UART 0 accesses FIFO via this register."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/fsm_status.rs b/esp32h2/src/uart0/fsm_status.rs
index 7e47b06bf6..4088ac153f 100644
--- a/esp32h2/src/uart0/fsm_status.rs
+++ b/esp32h2/src/uart0/fsm_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_STATUS")
-            .field("st_urx_out", &format_args!("{}", self.st_urx_out().bits()))
-            .field("st_utx_out", &format_args!("{}", self.st_utx_out().bits()))
+            .field("st_urx_out", &self.st_urx_out())
+            .field("st_utx_out", &self.st_utx_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART transmit and receive status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FSM_STATUS_SPEC;
 impl crate::RegisterSpec for FSM_STATUS_SPEC {
diff --git a/esp32h2/src/uart0/highpulse.rs b/esp32h2/src/uart0/highpulse.rs
index 2a100f783a..8445906dbf 100644
--- a/esp32h2/src/uart0/highpulse.rs
+++ b/esp32h2/src/uart0/highpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIGHPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIGHPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud minimum high pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`highpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIGHPULSE_SPEC;
 impl crate::RegisterSpec for HIGHPULSE_SPEC {
diff --git a/esp32h2/src/uart0/hwfc_conf.rs b/esp32h2/src/uart0/hwfc_conf.rs
index c5bcb05208..f9a6aadfb8 100644
--- a/esp32h2/src/uart0/hwfc_conf.rs
+++ b/esp32h2/src/uart0/hwfc_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HWFC_CONF")
-            .field(
-                "rx_flow_thrhd",
-                &format_args!("{}", self.rx_flow_thrhd().bits()),
-            )
-            .field("rx_flow_en", &format_args!("{}", self.rx_flow_en().bit()))
+            .field("rx_flow_thrhd", &self.rx_flow_thrhd())
+            .field("rx_flow_en", &self.rx_flow_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HWFC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the maximum amount of data that can be received when hardware flow control works."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/id.rs b/esp32h2/src/uart0/id.rs
index 9c8cfa3a6b..670842afd9 100644
--- a/esp32h2/src/uart0/id.rs
+++ b/esp32h2/src/uart0/id.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("ID")
-            .field("id", &format_args!("{}", self.id().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("ID").field("id", &self.id()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/uart0/idle_conf.rs b/esp32h2/src/uart0/idle_conf.rs
index bc986732bf..a2f200e19e 100644
--- a/esp32h2/src/uart0/idle_conf.rs
+++ b/esp32h2/src/uart0/idle_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDLE_CONF")
-            .field(
-                "rx_idle_thrhd",
-                &format_args!("{}", self.rx_idle_thrhd().bits()),
-            )
-            .field(
-                "tx_idle_num",
-                &format_args!("{}", self.tx_idle_num().bits()),
-            )
+            .field("rx_idle_thrhd", &self.rx_idle_thrhd())
+            .field("tx_idle_num", &self.tx_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/int_ena.rs b/esp32h2/src/uart0/int_ena.rs
index fea57f25bd..3a8a9f2f95 100644
--- a/esp32h2/src/uart0/int_ena.rs
+++ b/esp32h2/src/uart0/int_ena.rs
@@ -188,50 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/int_raw.rs b/esp32h2/src/uart0/int_raw.rs
index 7c0c628adc..d47f4c54f2 100644
--- a/esp32h2/src/uart0/int_raw.rs
+++ b/esp32h2/src/uart0/int_raw.rs
@@ -188,50 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/int_st.rs b/esp32h2/src/uart0/int_st.rs
index 417bc433a0..c67c7f4b75 100644
--- a/esp32h2/src/uart0/int_st.rs
+++ b/esp32h2/src/uart0/int_st.rs
@@ -146,50 +146,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/uart0/lowpulse.rs b/esp32h2/src/uart0/lowpulse.rs
index 6736272863..03a2b35c08 100644
--- a/esp32h2/src/uart0/lowpulse.rs
+++ b/esp32h2/src/uart0/lowpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOWPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOWPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud minimum low pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lowpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOWPULSE_SPEC;
 impl crate::RegisterSpec for LOWPULSE_SPEC {
diff --git a/esp32h2/src/uart0/mem_conf.rs b/esp32h2/src/uart0/mem_conf.rs
index 8c55da8b47..e930d52fc0 100644
--- a/esp32h2/src/uart0/mem_conf.rs
+++ b/esp32h2/src/uart0/mem_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - Set this bit to force power down UART memory."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/mem_rx_status.rs b/esp32h2/src/uart0/mem_rx_status.rs
index 0a126a60b0..99d13455c6 100644
--- a/esp32h2/src/uart0/mem_rx_status.rs
+++ b/esp32h2/src/uart0/mem_rx_status.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_RX_STATUS")
-            .field(
-                "rx_sram_raddr",
-                &format_args!("{}", self.rx_sram_raddr().bits()),
-            )
-            .field(
-                "rx_sram_waddr",
-                &format_args!("{}", self.rx_sram_waddr().bits()),
-            )
+            .field("rx_sram_raddr", &self.rx_sram_raddr())
+            .field("rx_sram_waddr", &self.rx_sram_waddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Rx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_RX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_RX_STATUS_SPEC {
diff --git a/esp32h2/src/uart0/mem_tx_status.rs b/esp32h2/src/uart0/mem_tx_status.rs
index 8b947846b3..328cfcccd6 100644
--- a/esp32h2/src/uart0/mem_tx_status.rs
+++ b/esp32h2/src/uart0/mem_tx_status.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_TX_STATUS")
-            .field(
-                "tx_sram_waddr",
-                &format_args!("{}", self.tx_sram_waddr().bits()),
-            )
-            .field(
-                "tx_sram_raddr",
-                &format_args!("{}", self.tx_sram_raddr().bits()),
-            )
+            .field("tx_sram_waddr", &self.tx_sram_waddr())
+            .field("tx_sram_raddr", &self.tx_sram_raddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Tx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_TX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_TX_STATUS_SPEC {
diff --git a/esp32h2/src/uart0/negpulse.rs b/esp32h2/src/uart0/negpulse.rs
index 0daf3b983f..d033b00895 100644
--- a/esp32h2/src/uart0/negpulse.rs
+++ b/esp32h2/src/uart0/negpulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NEGPULSE")
-            .field(
-                "negedge_min_cnt",
-                &format_args!("{}", self.negedge_min_cnt().bits()),
-            )
+            .field("negedge_min_cnt", &self.negedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NEGPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud low pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`negpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NEGPULSE_SPEC;
 impl crate::RegisterSpec for NEGPULSE_SPEC {
diff --git a/esp32h2/src/uart0/pospulse.rs b/esp32h2/src/uart0/pospulse.rs
index 67a98ae05f..acf540a226 100644
--- a/esp32h2/src/uart0/pospulse.rs
+++ b/esp32h2/src/uart0/pospulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POSPULSE")
-            .field(
-                "posedge_min_cnt",
-                &format_args!("{}", self.posedge_min_cnt().bits()),
-            )
+            .field("posedge_min_cnt", &self.posedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POSPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud high pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pospulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct POSPULSE_SPEC;
 impl crate::RegisterSpec for POSPULSE_SPEC {
diff --git a/esp32h2/src/uart0/reg_update.rs b/esp32h2/src/uart0/reg_update.rs
index b2e4551f76..441e05815f 100644
--- a/esp32h2/src/uart0/reg_update.rs
+++ b/esp32h2/src/uart0/reg_update.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_UPDATE")
-            .field("reg_update", &format_args!("{}", self.reg_update().bit()))
+            .field("reg_update", &self.reg_update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/rs485_conf.rs b/esp32h2/src/uart0/rs485_conf.rs
index 5480b03198..dbf27d91ba 100644
--- a/esp32h2/src/uart0/rs485_conf.rs
+++ b/esp32h2/src/uart0/rs485_conf.rs
@@ -71,34 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RS485_CONF")
-            .field("rs485_en", &format_args!("{}", self.rs485_en().bit()))
-            .field("dl0_en", &format_args!("{}", self.dl0_en().bit()))
-            .field("dl1_en", &format_args!("{}", self.dl1_en().bit()))
-            .field(
-                "rs485tx_rx_en",
-                &format_args!("{}", self.rs485tx_rx_en().bit()),
-            )
-            .field(
-                "rs485rxby_tx_en",
-                &format_args!("{}", self.rs485rxby_tx_en().bit()),
-            )
-            .field(
-                "rs485_rx_dly_num",
-                &format_args!("{}", self.rs485_rx_dly_num().bit()),
-            )
-            .field(
-                "rs485_tx_dly_num",
-                &format_args!("{}", self.rs485_tx_dly_num().bits()),
-            )
+            .field("rs485_en", &self.rs485_en())
+            .field("dl0_en", &self.dl0_en())
+            .field("dl1_en", &self.dl1_en())
+            .field("rs485tx_rx_en", &self.rs485tx_rx_en())
+            .field("rs485rxby_tx_en", &self.rs485rxby_tx_en())
+            .field("rs485_rx_dly_num", &self.rs485_rx_dly_num())
+            .field("rs485_tx_dly_num", &self.rs485_tx_dly_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RS485_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to choose the rs485 mode."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/rx_filt.rs b/esp32h2/src/uart0/rx_filt.rs
index c24c62977e..21576af0e9 100644
--- a/esp32h2/src/uart0/rx_filt.rs
+++ b/esp32h2/src/uart0/rx_filt.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_FILT")
-            .field(
-                "glitch_filt",
-                &format_args!("{}", self.glitch_filt().bits()),
-            )
-            .field(
-                "glitch_filt_en",
-                &format_args!("{}", self.glitch_filt_en().bit()),
-            )
+            .field("glitch_filt", &self.glitch_filt())
+            .field("glitch_filt_en", &self.glitch_filt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_FILT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - when input pulse width is lower than this value the pulse is ignored."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/rxd_cnt.rs b/esp32h2/src/uart0/rxd_cnt.rs
index f08d5e0323..c3c3052a66 100644
--- a/esp32h2/src/uart0/rxd_cnt.rs
+++ b/esp32h2/src/uart0/rxd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXD_CNT")
-            .field(
-                "rxd_edge_cnt",
-                &format_args!("{}", self.rxd_edge_cnt().bits()),
-            )
+            .field("rxd_edge_cnt", &self.rxd_edge_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud edge change count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXD_CNT_SPEC;
 impl crate::RegisterSpec for RXD_CNT_SPEC {
diff --git a/esp32h2/src/uart0/sleep_conf0.rs b/esp32h2/src/uart0/sleep_conf0.rs
index 1c5c7f7eed..a8481a8783 100644
--- a/esp32h2/src/uart0/sleep_conf0.rs
+++ b/esp32h2/src/uart0/sleep_conf0.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF0")
-            .field("wk_char1", &format_args!("{}", self.wk_char1().bits()))
-            .field("wk_char2", &format_args!("{}", self.wk_char2().bits()))
-            .field("wk_char3", &format_args!("{}", self.wk_char3().bits()))
-            .field("wk_char4", &format_args!("{}", self.wk_char4().bits()))
+            .field("wk_char1", &self.wk_char1())
+            .field("wk_char2", &self.wk_char2())
+            .field("wk_char3", &self.wk_char3())
+            .field("wk_char4", &self.wk_char4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register restores the specified wake up char1 to wake up"]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/sleep_conf1.rs b/esp32h2/src/uart0/sleep_conf1.rs
index f9f665a833..bf71699cf5 100644
--- a/esp32h2/src/uart0/sleep_conf1.rs
+++ b/esp32h2/src/uart0/sleep_conf1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF1")
-            .field("wk_char0", &format_args!("{}", self.wk_char0().bits()))
+            .field("wk_char0", &self.wk_char0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register restores the specified char0 to wake up"]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/sleep_conf2.rs b/esp32h2/src/uart0/sleep_conf2.rs
index 4ba2a7a251..06e8c23f14 100644
--- a/esp32h2/src/uart0/sleep_conf2.rs
+++ b/esp32h2/src/uart0/sleep_conf2.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF2")
-            .field(
-                "active_threshold",
-                &format_args!("{}", self.active_threshold().bits()),
-            )
-            .field(
-                "rx_wake_up_thrhd",
-                &format_args!("{}", self.rx_wake_up_thrhd().bits()),
-            )
-            .field(
-                "wk_char_num",
-                &format_args!("{}", self.wk_char_num().bits()),
-            )
-            .field(
-                "wk_char_mask",
-                &format_args!("{}", self.wk_char_mask().bits()),
-            )
-            .field(
-                "wk_mode_sel",
-                &format_args!("{}", self.wk_mode_sel().bits()),
-            )
+            .field("active_threshold", &self.active_threshold())
+            .field("rx_wake_up_thrhd", &self.rx_wake_up_thrhd())
+            .field("wk_char_num", &self.wk_char_num())
+            .field("wk_char_mask", &self.wk_char_mask())
+            .field("wk_mode_sel", &self.wk_mode_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/status.rs b/esp32h2/src/uart0/status.rs
index c6f8b87e2e..b94bda636c 100644
--- a/esp32h2/src/uart0/status.rs
+++ b/esp32h2/src/uart0/status.rs
@@ -62,23 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("dsrn", &format_args!("{}", self.dsrn().bit()))
-            .field("ctsn", &format_args!("{}", self.ctsn().bit()))
-            .field("rxd", &format_args!("{}", self.rxd().bit()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field("dtrn", &format_args!("{}", self.dtrn().bit()))
-            .field("rtsn", &format_args!("{}", self.rtsn().bit()))
-            .field("txd", &format_args!("{}", self.txd().bit()))
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("dsrn", &self.dsrn())
+            .field("ctsn", &self.ctsn())
+            .field("rxd", &self.rxd())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("dtrn", &self.dtrn())
+            .field("rtsn", &self.rtsn())
+            .field("txd", &self.txd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32h2/src/uart0/swfc_conf0.rs b/esp32h2/src/uart0/swfc_conf0.rs
index 341967dafc..bbbea9d9e5 100644
--- a/esp32h2/src/uart0/swfc_conf0.rs
+++ b/esp32h2/src/uart0/swfc_conf0.rs
@@ -89,30 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF0")
-            .field("xon_char", &format_args!("{}", self.xon_char().bits()))
-            .field("xoff_char", &format_args!("{}", self.xoff_char().bits()))
-            .field(
-                "xon_xoff_still_send",
-                &format_args!("{}", self.xon_xoff_still_send().bit()),
-            )
-            .field(
-                "sw_flow_con_en",
-                &format_args!("{}", self.sw_flow_con_en().bit()),
-            )
-            .field("xonoff_del", &format_args!("{}", self.xonoff_del().bit()))
-            .field("force_xon", &format_args!("{}", self.force_xon().bit()))
-            .field("force_xoff", &format_args!("{}", self.force_xoff().bit()))
-            .field("send_xon", &format_args!("{}", self.send_xon().bit()))
-            .field("send_xoff", &format_args!("{}", self.send_xoff().bit()))
+            .field("xon_char", &self.xon_char())
+            .field("xoff_char", &self.xoff_char())
+            .field("xon_xoff_still_send", &self.xon_xoff_still_send())
+            .field("sw_flow_con_en", &self.sw_flow_con_en())
+            .field("xonoff_del", &self.xonoff_del())
+            .field("force_xon", &self.force_xon())
+            .field("force_xoff", &self.force_xoff())
+            .field("send_xon", &self.send_xon())
+            .field("send_xoff", &self.send_xoff())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register stores the Xon flow control char."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/swfc_conf1.rs b/esp32h2/src/uart0/swfc_conf1.rs
index f747b693ec..d7558a5286 100644
--- a/esp32h2/src/uart0/swfc_conf1.rs
+++ b/esp32h2/src/uart0/swfc_conf1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF1")
-            .field(
-                "xon_threshold",
-                &format_args!("{}", self.xon_threshold().bits()),
-            )
-            .field(
-                "xoff_threshold",
-                &format_args!("{}", self.xoff_threshold().bits()),
-            )
+            .field("xon_threshold", &self.xon_threshold())
+            .field("xoff_threshold", &self.xoff_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/tout_conf.rs b/esp32h2/src/uart0/tout_conf.rs
index 92fe213cbb..908b3e6b17 100644
--- a/esp32h2/src/uart0/tout_conf.rs
+++ b/esp32h2/src/uart0/tout_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUT_CONF")
-            .field("rx_tout_en", &format_args!("{}", self.rx_tout_en().bit()))
-            .field(
-                "rx_tout_flow_dis",
-                &format_args!("{}", self.rx_tout_flow_dis().bit()),
-            )
-            .field(
-                "rx_tout_thrhd",
-                &format_args!("{}", self.rx_tout_thrhd().bits()),
-            )
+            .field("rx_tout_en", &self.rx_tout_en())
+            .field("rx_tout_flow_dis", &self.rx_tout_flow_dis())
+            .field("rx_tout_thrhd", &self.rx_tout_thrhd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enble bit for uart receiver's timeout function."]
     #[inline(always)]
diff --git a/esp32h2/src/uart0/txbrk_conf.rs b/esp32h2/src/uart0/txbrk_conf.rs
index bfa2a9b911..65d37271c2 100644
--- a/esp32h2/src/uart0/txbrk_conf.rs
+++ b/esp32h2/src/uart0/txbrk_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXBRK_CONF")
-            .field("tx_brk_num", &format_args!("{}", self.tx_brk_num().bits()))
+            .field("tx_brk_num", &self.tx_brk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXBRK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."]
     #[inline(always)]
diff --git a/esp32h2/src/uhci0/ack_num.rs b/esp32h2/src/uhci0/ack_num.rs
index b1dc6e3065..1dc62df0e7 100644
--- a/esp32h2/src/uhci0/ack_num.rs
+++ b/esp32h2/src/uhci0/ack_num.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ACK_NUM")
-            .field("ack_num", &format_args!("{}", self.ack_num().bits()))
+            .field("ack_num", &self.ack_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ACK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - a"]
     #[inline(always)]
diff --git a/esp32h2/src/uhci0/conf0.rs b/esp32h2/src/uhci0/conf0.rs
index b1b33435f4..2c623af742 100644
--- a/esp32h2/src/uhci0/conf0.rs
+++ b/esp32h2/src/uhci0/conf0.rs
@@ -116,36 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("tx_rst", &format_args!("{}", self.tx_rst().bit()))
-            .field("rx_rst", &format_args!("{}", self.rx_rst().bit()))
-            .field("uart0_ce", &format_args!("{}", self.uart0_ce().bit()))
-            .field("uart1_ce", &format_args!("{}", self.uart1_ce().bit()))
-            .field("seper_en", &format_args!("{}", self.seper_en().bit()))
-            .field("head_en", &format_args!("{}", self.head_en().bit()))
-            .field("crc_rec_en", &format_args!("{}", self.crc_rec_en().bit()))
-            .field(
-                "uart_idle_eof_en",
-                &format_args!("{}", self.uart_idle_eof_en().bit()),
-            )
-            .field("len_eof_en", &format_args!("{}", self.len_eof_en().bit()))
-            .field(
-                "encode_crc_en",
-                &format_args!("{}", self.encode_crc_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "uart_rx_brk_eof_en",
-                &format_args!("{}", self.uart_rx_brk_eof_en().bit()),
-            )
+            .field("tx_rst", &self.tx_rst())
+            .field("rx_rst", &self.rx_rst())
+            .field("uart0_ce", &self.uart0_ce())
+            .field("uart1_ce", &self.uart1_ce())
+            .field("seper_en", &self.seper_en())
+            .field("head_en", &self.head_en())
+            .field("crc_rec_en", &self.crc_rec_en())
+            .field("uart_idle_eof_en", &self.uart_idle_eof_en())
+            .field("len_eof_en", &self.len_eof_en())
+            .field("encode_crc_en", &self.encode_crc_en())
+            .field("clk_en", &self.clk_en())
+            .field("uart_rx_brk_eof_en", &self.uart_rx_brk_eof_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 then write 0 to this bit to reset decode state machine."]
     #[inline(always)]
diff --git a/esp32h2/src/uhci0/conf1.rs b/esp32h2/src/uhci0/conf1.rs
index ca0c9a32ad..63eaac3666 100644
--- a/esp32h2/src/uhci0/conf1.rs
+++ b/esp32h2/src/uhci0/conf1.rs
@@ -73,37 +73,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "check_sum_en",
-                &format_args!("{}", self.check_sum_en().bit()),
-            )
-            .field(
-                "check_seq_en",
-                &format_args!("{}", self.check_seq_en().bit()),
-            )
-            .field("crc_disable", &format_args!("{}", self.crc_disable().bit()))
-            .field("save_head", &format_args!("{}", self.save_head().bit()))
-            .field(
-                "tx_check_sum_re",
-                &format_args!("{}", self.tx_check_sum_re().bit()),
-            )
-            .field(
-                "tx_ack_num_re",
-                &format_args!("{}", self.tx_ack_num_re().bit()),
-            )
-            .field(
-                "wait_sw_start",
-                &format_args!("{}", self.wait_sw_start().bit()),
-            )
+            .field("check_sum_en", &self.check_sum_en())
+            .field("check_seq_en", &self.check_seq_en())
+            .field("crc_disable", &self.crc_disable())
+            .field("save_head", &self.save_head())
+            .field("tx_check_sum_re", &self.tx_check_sum_re())
+            .field("tx_ack_num_re", &self.tx_ack_num_re())
+            .field("wait_sw_start", &self.wait_sw_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - a"]
     #[inline(always)]
diff --git a/esp32h2/src/uhci0/date.rs b/esp32h2/src/uhci0/date.rs
index f70f002c45..0a49399969 100644
--- a/esp32h2/src/uhci0/date.rs
+++ b/esp32h2/src/uhci0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/uhci0/esc_conf.rs b/esp32h2/src/uhci0/esc_conf.rs
index ace9fbdb12..e2470a3ff5 100644
--- a/esp32h2/src/uhci0/esc_conf.rs
+++ b/esp32h2/src/uhci0/esc_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ESC_CONF")
-            .field("seper_char", &format_args!("{}", self.seper_char().bits()))
-            .field(
-                "seper_esc_char0",
-                &format_args!("{}", self.seper_esc_char0().bits()),
-            )
-            .field(
-                "seper_esc_char1",
-                &format_args!("{}", self.seper_esc_char1().bits()),
-            )
+            .field("seper_char", &self.seper_char())
+            .field("seper_esc_char0", &self.seper_esc_char0())
+            .field("seper_esc_char1", &self.seper_esc_char1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ESC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - a"]
     #[inline(always)]
diff --git a/esp32h2/src/uhci0/escape_conf.rs b/esp32h2/src/uhci0/escape_conf.rs
index d6ab085002..54d7bbfa84 100644
--- a/esp32h2/src/uhci0/escape_conf.rs
+++ b/esp32h2/src/uhci0/escape_conf.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ESCAPE_CONF")
-            .field(
-                "tx_c0_esc_en",
-                &format_args!("{}", self.tx_c0_esc_en().bit()),
-            )
-            .field(
-                "tx_db_esc_en",
-                &format_args!("{}", self.tx_db_esc_en().bit()),
-            )
-            .field(
-                "tx_11_esc_en",
-                &format_args!("{}", self.tx_11_esc_en().bit()),
-            )
-            .field(
-                "tx_13_esc_en",
-                &format_args!("{}", self.tx_13_esc_en().bit()),
-            )
-            .field(
-                "rx_c0_esc_en",
-                &format_args!("{}", self.rx_c0_esc_en().bit()),
-            )
-            .field(
-                "rx_db_esc_en",
-                &format_args!("{}", self.rx_db_esc_en().bit()),
-            )
-            .field(
-                "rx_11_esc_en",
-                &format_args!("{}", self.rx_11_esc_en().bit()),
-            )
-            .field(
-                "rx_13_esc_en",
-                &format_args!("{}", self.rx_13_esc_en().bit()),
-            )
+            .field("tx_c0_esc_en", &self.tx_c0_esc_en())
+            .field("tx_db_esc_en", &self.tx_db_esc_en())
+            .field("tx_11_esc_en", &self.tx_11_esc_en())
+            .field("tx_13_esc_en", &self.tx_13_esc_en())
+            .field("rx_c0_esc_en", &self.rx_c0_esc_en())
+            .field("rx_db_esc_en", &self.rx_db_esc_en())
+            .field("rx_11_esc_en", &self.rx_11_esc_en())
+            .field("rx_13_esc_en", &self.rx_13_esc_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ESCAPE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - a"]
     #[inline(always)]
diff --git a/esp32h2/src/uhci0/hung_conf.rs b/esp32h2/src/uhci0/hung_conf.rs
index a6afa4092c..4ec1687c77 100644
--- a/esp32h2/src/uhci0/hung_conf.rs
+++ b/esp32h2/src/uhci0/hung_conf.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HUNG_CONF")
-            .field(
-                "txfifo_timeout",
-                &format_args!("{}", self.txfifo_timeout().bits()),
-            )
-            .field(
-                "txfifo_timeout_shift",
-                &format_args!("{}", self.txfifo_timeout_shift().bits()),
-            )
-            .field(
-                "txfifo_timeout_ena",
-                &format_args!("{}", self.txfifo_timeout_ena().bit()),
-            )
-            .field(
-                "rxfifo_timeout",
-                &format_args!("{}", self.rxfifo_timeout().bits()),
-            )
-            .field(
-                "rxfifo_timeout_shift",
-                &format_args!("{}", self.rxfifo_timeout_shift().bits()),
-            )
-            .field(
-                "rxfifo_timeout_ena",
-                &format_args!("{}", self.rxfifo_timeout_ena().bit()),
-            )
+            .field("txfifo_timeout", &self.txfifo_timeout())
+            .field("txfifo_timeout_shift", &self.txfifo_timeout_shift())
+            .field("txfifo_timeout_ena", &self.txfifo_timeout_ena())
+            .field("rxfifo_timeout", &self.rxfifo_timeout())
+            .field("rxfifo_timeout_shift", &self.rxfifo_timeout_shift())
+            .field("rxfifo_timeout_ena", &self.rxfifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - a"]
     #[inline(always)]
diff --git a/esp32h2/src/uhci0/int_ena.rs b/esp32h2/src/uhci0/int_ena.rs
index f314b3f22a..6a6be4eb1b 100644
--- a/esp32h2/src/uhci0/int_ena.rs
+++ b/esp32h2/src/uhci0/int_ena.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
-            .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - a"]
     #[inline(always)]
diff --git a/esp32h2/src/uhci0/int_raw.rs b/esp32h2/src/uhci0/int_raw.rs
index 445e2170fd..11e0ddbabe 100644
--- a/esp32h2/src/uhci0/int_raw.rs
+++ b/esp32h2/src/uhci0/int_raw.rs
@@ -89,30 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
-            .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("out_eof", &self.out_eof())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - a"]
     #[inline(always)]
diff --git a/esp32h2/src/uhci0/int_st.rs b/esp32h2/src/uhci0/int_st.rs
index 3aa1520031..6178db3316 100644
--- a/esp32h2/src/uhci0/int_st.rs
+++ b/esp32h2/src/uhci0/int_st.rs
@@ -69,33 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
-            .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/uhci0/pkt_thres.rs b/esp32h2/src/uhci0/pkt_thres.rs
index 90c99b6cf8..78af77cd0e 100644
--- a/esp32h2/src/uhci0/pkt_thres.rs
+++ b/esp32h2/src/uhci0/pkt_thres.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PKT_THRES")
-            .field("pkt_thrs", &format_args!("{}", self.pkt_thrs().bits()))
+            .field("pkt_thrs", &self.pkt_thrs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PKT_THRES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - a"]
     #[inline(always)]
diff --git a/esp32h2/src/uhci0/quick_sent.rs b/esp32h2/src/uhci0/quick_sent.rs
index e271ba7f9c..9259b3d84a 100644
--- a/esp32h2/src/uhci0/quick_sent.rs
+++ b/esp32h2/src/uhci0/quick_sent.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUICK_SENT")
-            .field(
-                "single_send_num",
-                &format_args!("{}", self.single_send_num().bits()),
-            )
-            .field(
-                "always_send_num",
-                &format_args!("{}", self.always_send_num().bits()),
-            )
-            .field(
-                "always_send_en",
-                &format_args!("{}", self.always_send_en().bit()),
-            )
+            .field("single_send_num", &self.single_send_num())
+            .field("always_send_num", &self.always_send_num())
+            .field("always_send_en", &self.always_send_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUICK_SENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - a"]
     #[inline(always)]
diff --git a/esp32h2/src/uhci0/reg_q/word0.rs b/esp32h2/src/uhci0/reg_q/word0.rs
index 19e9e832f7..ee667218e9 100644
--- a/esp32h2/src/uhci0/reg_q/word0.rs
+++ b/esp32h2/src/uhci0/reg_q/word0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WORD0")
-            .field("send_word", &format_args!("{}", self.send_word().bits()))
+            .field("send_word", &self.send_word())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WORD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - a"]
     #[inline(always)]
diff --git a/esp32h2/src/uhci0/reg_q/word1.rs b/esp32h2/src/uhci0/reg_q/word1.rs
index 8a0df345ba..e300953f09 100644
--- a/esp32h2/src/uhci0/reg_q/word1.rs
+++ b/esp32h2/src/uhci0/reg_q/word1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WORD1")
-            .field("send_word", &format_args!("{}", self.send_word().bits()))
+            .field("send_word", &self.send_word())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WORD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - a"]
     #[inline(always)]
diff --git a/esp32h2/src/uhci0/rx_head.rs b/esp32h2/src/uhci0/rx_head.rs
index 5381387bf9..a0180e5bcc 100644
--- a/esp32h2/src/uhci0/rx_head.rs
+++ b/esp32h2/src/uhci0/rx_head.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_HEAD")
-            .field("rx_head", &format_args!("{}", self.rx_head().bits()))
+            .field("rx_head", &self.rx_head())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_HEAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_head::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_HEAD_SPEC;
 impl crate::RegisterSpec for RX_HEAD_SPEC {
diff --git a/esp32h2/src/uhci0/state0.rs b/esp32h2/src/uhci0/state0.rs
index 0f5fd94f00..6ee8f8c9f1 100644
--- a/esp32h2/src/uhci0/state0.rs
+++ b/esp32h2/src/uhci0/state0.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE0")
-            .field(
-                "rx_err_cause",
-                &format_args!("{}", self.rx_err_cause().bits()),
-            )
-            .field(
-                "decode_state",
-                &format_args!("{}", self.decode_state().bits()),
-            )
+            .field("rx_err_cause", &self.rx_err_cause())
+            .field("decode_state", &self.decode_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE0_SPEC;
 impl crate::RegisterSpec for STATE0_SPEC {
diff --git a/esp32h2/src/uhci0/state1.rs b/esp32h2/src/uhci0/state1.rs
index a33d5b362e..bde625ed00 100644
--- a/esp32h2/src/uhci0/state1.rs
+++ b/esp32h2/src/uhci0/state1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE1")
-            .field(
-                "encode_state",
-                &format_args!("{}", self.encode_state().bits()),
-            )
+            .field("encode_state", &self.encode_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE1_SPEC;
 impl crate::RegisterSpec for STATE1_SPEC {
diff --git a/esp32h2/src/usb_device/bus_reset_st.rs b/esp32h2/src/usb_device/bus_reset_st.rs
index 9b463d08d3..3c2d490751 100644
--- a/esp32h2/src/usb_device/bus_reset_st.rs
+++ b/esp32h2/src/usb_device/bus_reset_st.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_RESET_ST")
-            .field(
-                "usb_bus_reset_st",
-                &format_args!("{}", self.usb_bus_reset_st().bit()),
-            )
+            .field("usb_bus_reset_st", &self.usb_bus_reset_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_RESET_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USB Bus reset status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_reset_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUS_RESET_ST_SPEC;
 impl crate::RegisterSpec for BUS_RESET_ST_SPEC {
diff --git a/esp32h2/src/usb_device/chip_rst.rs b/esp32h2/src/usb_device/chip_rst.rs
index f66590e261..3773555886 100644
--- a/esp32h2/src/usb_device/chip_rst.rs
+++ b/esp32h2/src/usb_device/chip_rst.rs
@@ -31,21 +31,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHIP_RST")
-            .field("rts", &format_args!("{}", self.rts().bit()))
-            .field("dtr", &format_args!("{}", self.dtr().bit()))
-            .field(
-                "usb_uart_chip_rst_dis",
-                &format_args!("{}", self.usb_uart_chip_rst_dis().bit()),
-            )
+            .field("rts", &self.rts())
+            .field("dtr", &self.dtr())
+            .field("usb_uart_chip_rst_dis", &self.usb_uart_chip_rst_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHIP_RST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - Set this bit to disable chip reset from usb serial channel to reset chip."]
     #[inline(always)]
diff --git a/esp32h2/src/usb_device/conf0.rs b/esp32h2/src/usb_device/conf0.rs
index d3e851d8f0..fc639deb91 100644
--- a/esp32h2/src/usb_device/conf0.rs
+++ b/esp32h2/src/usb_device/conf0.rs
@@ -134,47 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("phy_sel", &format_args!("{}", self.phy_sel().bit()))
-            .field(
-                "exchg_pins_override",
-                &format_args!("{}", self.exchg_pins_override().bit()),
-            )
-            .field("exchg_pins", &format_args!("{}", self.exchg_pins().bit()))
-            .field("vrefh", &format_args!("{}", self.vrefh().bits()))
-            .field("vrefl", &format_args!("{}", self.vrefl().bits()))
-            .field(
-                "vref_override",
-                &format_args!("{}", self.vref_override().bit()),
-            )
-            .field(
-                "pad_pull_override",
-                &format_args!("{}", self.pad_pull_override().bit()),
-            )
-            .field("dp_pullup", &format_args!("{}", self.dp_pullup().bit()))
-            .field("dp_pulldown", &format_args!("{}", self.dp_pulldown().bit()))
-            .field("dm_pullup", &format_args!("{}", self.dm_pullup().bit()))
-            .field("dm_pulldown", &format_args!("{}", self.dm_pulldown().bit()))
-            .field(
-                "pullup_value",
-                &format_args!("{}", self.pullup_value().bit()),
-            )
-            .field(
-                "usb_pad_enable",
-                &format_args!("{}", self.usb_pad_enable().bit()),
-            )
-            .field(
-                "usb_jtag_bridge_en",
-                &format_args!("{}", self.usb_jtag_bridge_en().bit()),
-            )
+            .field("phy_sel", &self.phy_sel())
+            .field("exchg_pins_override", &self.exchg_pins_override())
+            .field("exchg_pins", &self.exchg_pins())
+            .field("vrefh", &self.vrefh())
+            .field("vrefl", &self.vrefl())
+            .field("vref_override", &self.vref_override())
+            .field("pad_pull_override", &self.pad_pull_override())
+            .field("dp_pullup", &self.dp_pullup())
+            .field("dp_pulldown", &self.dp_pulldown())
+            .field("dm_pullup", &self.dm_pullup())
+            .field("dm_pulldown", &self.dm_pulldown())
+            .field("pullup_value", &self.pullup_value())
+            .field("usb_pad_enable", &self.usb_pad_enable())
+            .field("usb_jtag_bridge_en", &self.usb_jtag_bridge_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Select internal/external PHY"]
     #[inline(always)]
diff --git a/esp32h2/src/usb_device/date.rs b/esp32h2/src/usb_device/date.rs
index 1c49da5683..4c12755e22 100644
--- a/esp32h2/src/usb_device/date.rs
+++ b/esp32h2/src/usb_device/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32h2/src/usb_device/ep1.rs b/esp32h2/src/usb_device/ep1.rs
index 92bed9b30d..d6030184bd 100644
--- a/esp32h2/src/usb_device/ep1.rs
+++ b/esp32h2/src/usb_device/ep1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EP1")
-            .field("rdwr_byte", &format_args!("{}", self.rdwr_byte().bits()))
+            .field("rdwr_byte", &self.rdwr_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO."]
     #[inline(always)]
diff --git a/esp32h2/src/usb_device/ep1_conf.rs b/esp32h2/src/usb_device/ep1_conf.rs
index c99b3b08f6..3534449ebc 100644
--- a/esp32h2/src/usb_device/ep1_conf.rs
+++ b/esp32h2/src/usb_device/ep1_conf.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EP1_CONF")
-            .field(
-                "serial_in_ep_data_free",
-                &format_args!("{}", self.serial_in_ep_data_free().bit()),
-            )
-            .field(
-                "serial_out_ep_data_avail",
-                &format_args!("{}", self.serial_out_ep_data_avail().bit()),
-            )
+            .field("serial_in_ep_data_free", &self.serial_in_ep_data_free())
+            .field("serial_out_ep_data_avail", &self.serial_out_ep_data_avail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EP1_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to indicate writing byte data to UART Tx FIFO is done."]
     #[inline(always)]
diff --git a/esp32h2/src/usb_device/fram_num.rs b/esp32h2/src/usb_device/fram_num.rs
index ee7832b94b..555f25c409 100644
--- a/esp32h2/src/usb_device/fram_num.rs
+++ b/esp32h2/src/usb_device/fram_num.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FRAM_NUM")
-            .field(
-                "sof_frame_index",
-                &format_args!("{}", self.sof_frame_index().bits()),
-            )
+            .field("sof_frame_index", &self.sof_frame_index())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FRAM_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Last received SOF frame index register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fram_num::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FRAM_NUM_SPEC;
 impl crate::RegisterSpec for FRAM_NUM_SPEC {
diff --git a/esp32h2/src/usb_device/get_line_code_w0.rs b/esp32h2/src/usb_device/get_line_code_w0.rs
index d4deae05f4..374fc89555 100644
--- a/esp32h2/src/usb_device/get_line_code_w0.rs
+++ b/esp32h2/src/usb_device/get_line_code_w0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GET_LINE_CODE_W0")
-            .field(
-                "get_dw_dte_rate",
-                &format_args!("{}", self.get_dw_dte_rate().bits()),
-            )
+            .field("get_dw_dte_rate", &self.get_dw_dte_rate())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GET_LINE_CODE_W0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The value of dwDTERate set by software which is requested by GET_LINE_CODING command."]
     #[inline(always)]
diff --git a/esp32h2/src/usb_device/get_line_code_w1.rs b/esp32h2/src/usb_device/get_line_code_w1.rs
index 5ad3080523..d7ae6488a4 100644
--- a/esp32h2/src/usb_device/get_line_code_w1.rs
+++ b/esp32h2/src/usb_device/get_line_code_w1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GET_LINE_CODE_W1")
-            .field(
-                "get_bdata_bits",
-                &format_args!("{}", self.get_bdata_bits().bits()),
-            )
-            .field(
-                "get_bparity_type",
-                &format_args!("{}", self.get_bparity_type().bits()),
-            )
-            .field(
-                "get_bchar_format",
-                &format_args!("{}", self.get_bchar_format().bits()),
-            )
+            .field("get_bdata_bits", &self.get_bdata_bits())
+            .field("get_bparity_type", &self.get_bparity_type())
+            .field("get_bchar_format", &self.get_bchar_format())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GET_LINE_CODE_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value of bCharFormat set by software which is requested by GET_LINE_CODING command."]
     #[inline(always)]
diff --git a/esp32h2/src/usb_device/in_ep0_st.rs b/esp32h2/src/usb_device/in_ep0_st.rs
index cdba70f4ca..5e23d52fee 100644
--- a/esp32h2/src/usb_device/in_ep0_st.rs
+++ b/esp32h2/src/usb_device/in_ep0_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP0_ST")
-            .field(
-                "in_ep0_state",
-                &format_args!("{}", self.in_ep0_state().bits()),
-            )
-            .field(
-                "in_ep0_wr_addr",
-                &format_args!("{}", self.in_ep0_wr_addr().bits()),
-            )
-            .field(
-                "in_ep0_rd_addr",
-                &format_args!("{}", self.in_ep0_rd_addr().bits()),
-            )
+            .field("in_ep0_state", &self.in_ep0_state())
+            .field("in_ep0_wr_addr", &self.in_ep0_wr_addr())
+            .field("in_ep0_rd_addr", &self.in_ep0_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP0_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Control IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep0_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP0_ST_SPEC;
 impl crate::RegisterSpec for IN_EP0_ST_SPEC {
diff --git a/esp32h2/src/usb_device/in_ep1_st.rs b/esp32h2/src/usb_device/in_ep1_st.rs
index c4bbb2bf6b..c1350a8ce8 100644
--- a/esp32h2/src/usb_device/in_ep1_st.rs
+++ b/esp32h2/src/usb_device/in_ep1_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP1_ST")
-            .field(
-                "in_ep1_state",
-                &format_args!("{}", self.in_ep1_state().bits()),
-            )
-            .field(
-                "in_ep1_wr_addr",
-                &format_args!("{}", self.in_ep1_wr_addr().bits()),
-            )
-            .field(
-                "in_ep1_rd_addr",
-                &format_args!("{}", self.in_ep1_rd_addr().bits()),
-            )
+            .field("in_ep1_state", &self.in_ep1_state())
+            .field("in_ep1_wr_addr", &self.in_ep1_wr_addr())
+            .field("in_ep1_rd_addr", &self.in_ep1_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP1_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CDC-ACM IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep1_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP1_ST_SPEC;
 impl crate::RegisterSpec for IN_EP1_ST_SPEC {
diff --git a/esp32h2/src/usb_device/in_ep2_st.rs b/esp32h2/src/usb_device/in_ep2_st.rs
index d7dd32917d..15d0dbaa8d 100644
--- a/esp32h2/src/usb_device/in_ep2_st.rs
+++ b/esp32h2/src/usb_device/in_ep2_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP2_ST")
-            .field(
-                "in_ep2_state",
-                &format_args!("{}", self.in_ep2_state().bits()),
-            )
-            .field(
-                "in_ep2_wr_addr",
-                &format_args!("{}", self.in_ep2_wr_addr().bits()),
-            )
-            .field(
-                "in_ep2_rd_addr",
-                &format_args!("{}", self.in_ep2_rd_addr().bits()),
-            )
+            .field("in_ep2_state", &self.in_ep2_state())
+            .field("in_ep2_wr_addr", &self.in_ep2_wr_addr())
+            .field("in_ep2_rd_addr", &self.in_ep2_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP2_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CDC-ACM interrupt IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep2_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP2_ST_SPEC;
 impl crate::RegisterSpec for IN_EP2_ST_SPEC {
diff --git a/esp32h2/src/usb_device/in_ep3_st.rs b/esp32h2/src/usb_device/in_ep3_st.rs
index c36ea05f61..943dbe3d1c 100644
--- a/esp32h2/src/usb_device/in_ep3_st.rs
+++ b/esp32h2/src/usb_device/in_ep3_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP3_ST")
-            .field(
-                "in_ep3_state",
-                &format_args!("{}", self.in_ep3_state().bits()),
-            )
-            .field(
-                "in_ep3_wr_addr",
-                &format_args!("{}", self.in_ep3_wr_addr().bits()),
-            )
-            .field(
-                "in_ep3_rd_addr",
-                &format_args!("{}", self.in_ep3_rd_addr().bits()),
-            )
+            .field("in_ep3_state", &self.in_ep3_state())
+            .field("in_ep3_wr_addr", &self.in_ep3_wr_addr())
+            .field("in_ep3_rd_addr", &self.in_ep3_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP3_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "JTAG IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep3_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP3_ST_SPEC;
 impl crate::RegisterSpec for IN_EP3_ST_SPEC {
diff --git a/esp32h2/src/usb_device/int_ena.rs b/esp32h2/src/usb_device/int_ena.rs
index 7ed38f620a..e3d498b167 100644
--- a/esp32h2/src/usb_device/int_ena.rs
+++ b/esp32h2/src/usb_device/int_ena.rs
@@ -152,58 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "jtag_in_flush",
-                &format_args!("{}", self.jtag_in_flush().bit()),
-            )
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field(
-                "serial_out_recv_pkt",
-                &format_args!("{}", self.serial_out_recv_pkt().bit()),
-            )
-            .field(
-                "serial_in_empty",
-                &format_args!("{}", self.serial_in_empty().bit()),
-            )
-            .field("pid_err", &format_args!("{}", self.pid_err().bit()))
-            .field("crc5_err", &format_args!("{}", self.crc5_err().bit()))
-            .field("crc16_err", &format_args!("{}", self.crc16_err().bit()))
-            .field("stuff_err", &format_args!("{}", self.stuff_err().bit()))
-            .field(
-                "in_token_rec_in_ep1",
-                &format_args!("{}", self.in_token_rec_in_ep1().bit()),
-            )
-            .field(
-                "usb_bus_reset",
-                &format_args!("{}", self.usb_bus_reset().bit()),
-            )
-            .field(
-                "out_ep1_zero_payload",
-                &format_args!("{}", self.out_ep1_zero_payload().bit()),
-            )
-            .field(
-                "out_ep2_zero_payload",
-                &format_args!("{}", self.out_ep2_zero_payload().bit()),
-            )
-            .field("rts_chg", &format_args!("{}", self.rts_chg().bit()))
-            .field("dtr_chg", &format_args!("{}", self.dtr_chg().bit()))
-            .field(
-                "get_line_code",
-                &format_args!("{}", self.get_line_code().bit()),
-            )
-            .field(
-                "set_line_code",
-                &format_args!("{}", self.set_line_code().bit()),
-            )
+            .field("jtag_in_flush", &self.jtag_in_flush())
+            .field("sof", &self.sof())
+            .field("serial_out_recv_pkt", &self.serial_out_recv_pkt())
+            .field("serial_in_empty", &self.serial_in_empty())
+            .field("pid_err", &self.pid_err())
+            .field("crc5_err", &self.crc5_err())
+            .field("crc16_err", &self.crc16_err())
+            .field("stuff_err", &self.stuff_err())
+            .field("in_token_rec_in_ep1", &self.in_token_rec_in_ep1())
+            .field("usb_bus_reset", &self.usb_bus_reset())
+            .field("out_ep1_zero_payload", &self.out_ep1_zero_payload())
+            .field("out_ep2_zero_payload", &self.out_ep2_zero_payload())
+            .field("rts_chg", &self.rts_chg())
+            .field("dtr_chg", &self.dtr_chg())
+            .field("get_line_code", &self.get_line_code())
+            .field("set_line_code", &self.set_line_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32h2/src/usb_device/int_raw.rs b/esp32h2/src/usb_device/int_raw.rs
index fcb2db63ff..bc22e1a795 100644
--- a/esp32h2/src/usb_device/int_raw.rs
+++ b/esp32h2/src/usb_device/int_raw.rs
@@ -152,58 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "jtag_in_flush",
-                &format_args!("{}", self.jtag_in_flush().bit()),
-            )
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field(
-                "serial_out_recv_pkt",
-                &format_args!("{}", self.serial_out_recv_pkt().bit()),
-            )
-            .field(
-                "serial_in_empty",
-                &format_args!("{}", self.serial_in_empty().bit()),
-            )
-            .field("pid_err", &format_args!("{}", self.pid_err().bit()))
-            .field("crc5_err", &format_args!("{}", self.crc5_err().bit()))
-            .field("crc16_err", &format_args!("{}", self.crc16_err().bit()))
-            .field("stuff_err", &format_args!("{}", self.stuff_err().bit()))
-            .field(
-                "in_token_rec_in_ep1",
-                &format_args!("{}", self.in_token_rec_in_ep1().bit()),
-            )
-            .field(
-                "usb_bus_reset",
-                &format_args!("{}", self.usb_bus_reset().bit()),
-            )
-            .field(
-                "out_ep1_zero_payload",
-                &format_args!("{}", self.out_ep1_zero_payload().bit()),
-            )
-            .field(
-                "out_ep2_zero_payload",
-                &format_args!("{}", self.out_ep2_zero_payload().bit()),
-            )
-            .field("rts_chg", &format_args!("{}", self.rts_chg().bit()))
-            .field("dtr_chg", &format_args!("{}", self.dtr_chg().bit()))
-            .field(
-                "get_line_code",
-                &format_args!("{}", self.get_line_code().bit()),
-            )
-            .field(
-                "set_line_code",
-                &format_args!("{}", self.set_line_code().bit()),
-            )
+            .field("jtag_in_flush", &self.jtag_in_flush())
+            .field("sof", &self.sof())
+            .field("serial_out_recv_pkt", &self.serial_out_recv_pkt())
+            .field("serial_in_empty", &self.serial_in_empty())
+            .field("pid_err", &self.pid_err())
+            .field("crc5_err", &self.crc5_err())
+            .field("crc16_err", &self.crc16_err())
+            .field("stuff_err", &self.stuff_err())
+            .field("in_token_rec_in_ep1", &self.in_token_rec_in_ep1())
+            .field("usb_bus_reset", &self.usb_bus_reset())
+            .field("out_ep1_zero_payload", &self.out_ep1_zero_payload())
+            .field("out_ep2_zero_payload", &self.out_ep2_zero_payload())
+            .field("rts_chg", &self.rts_chg())
+            .field("dtr_chg", &self.dtr_chg())
+            .field("get_line_code", &self.get_line_code())
+            .field("set_line_code", &self.set_line_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG."]
     #[inline(always)]
diff --git a/esp32h2/src/usb_device/int_st.rs b/esp32h2/src/usb_device/int_st.rs
index ec83c07732..d968a2587e 100644
--- a/esp32h2/src/usb_device/int_st.rs
+++ b/esp32h2/src/usb_device/int_st.rs
@@ -118,58 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "jtag_in_flush",
-                &format_args!("{}", self.jtag_in_flush().bit()),
-            )
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field(
-                "serial_out_recv_pkt",
-                &format_args!("{}", self.serial_out_recv_pkt().bit()),
-            )
-            .field(
-                "serial_in_empty",
-                &format_args!("{}", self.serial_in_empty().bit()),
-            )
-            .field("pid_err", &format_args!("{}", self.pid_err().bit()))
-            .field("crc5_err", &format_args!("{}", self.crc5_err().bit()))
-            .field("crc16_err", &format_args!("{}", self.crc16_err().bit()))
-            .field("stuff_err", &format_args!("{}", self.stuff_err().bit()))
-            .field(
-                "in_token_rec_in_ep1",
-                &format_args!("{}", self.in_token_rec_in_ep1().bit()),
-            )
-            .field(
-                "usb_bus_reset",
-                &format_args!("{}", self.usb_bus_reset().bit()),
-            )
-            .field(
-                "out_ep1_zero_payload",
-                &format_args!("{}", self.out_ep1_zero_payload().bit()),
-            )
-            .field(
-                "out_ep2_zero_payload",
-                &format_args!("{}", self.out_ep2_zero_payload().bit()),
-            )
-            .field("rts_chg", &format_args!("{}", self.rts_chg().bit()))
-            .field("dtr_chg", &format_args!("{}", self.dtr_chg().bit()))
-            .field(
-                "get_line_code",
-                &format_args!("{}", self.get_line_code().bit()),
-            )
-            .field(
-                "set_line_code",
-                &format_args!("{}", self.set_line_code().bit()),
-            )
+            .field("jtag_in_flush", &self.jtag_in_flush())
+            .field("sof", &self.sof())
+            .field("serial_out_recv_pkt", &self.serial_out_recv_pkt())
+            .field("serial_in_empty", &self.serial_in_empty())
+            .field("pid_err", &self.pid_err())
+            .field("crc5_err", &self.crc5_err())
+            .field("crc16_err", &self.crc16_err())
+            .field("stuff_err", &self.stuff_err())
+            .field("in_token_rec_in_ep1", &self.in_token_rec_in_ep1())
+            .field("usb_bus_reset", &self.usb_bus_reset())
+            .field("out_ep1_zero_payload", &self.out_ep1_zero_payload())
+            .field("out_ep2_zero_payload", &self.out_ep2_zero_payload())
+            .field("rts_chg", &self.rts_chg())
+            .field("dtr_chg", &self.dtr_chg())
+            .field("get_line_code", &self.get_line_code())
+            .field("set_line_code", &self.set_line_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32h2/src/usb_device/jfifo_st.rs b/esp32h2/src/usb_device/jfifo_st.rs
index 09ed48770d..810e3b4bec 100644
--- a/esp32h2/src/usb_device/jfifo_st.rs
+++ b/esp32h2/src/usb_device/jfifo_st.rs
@@ -68,47 +68,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("JFIFO_ST")
-            .field(
-                "in_fifo_cnt",
-                &format_args!("{}", self.in_fifo_cnt().bits()),
-            )
-            .field(
-                "in_fifo_empty",
-                &format_args!("{}", self.in_fifo_empty().bit()),
-            )
-            .field(
-                "in_fifo_full",
-                &format_args!("{}", self.in_fifo_full().bit()),
-            )
-            .field(
-                "out_fifo_cnt",
-                &format_args!("{}", self.out_fifo_cnt().bits()),
-            )
-            .field(
-                "out_fifo_empty",
-                &format_args!("{}", self.out_fifo_empty().bit()),
-            )
-            .field(
-                "out_fifo_full",
-                &format_args!("{}", self.out_fifo_full().bit()),
-            )
-            .field(
-                "in_fifo_reset",
-                &format_args!("{}", self.in_fifo_reset().bit()),
-            )
-            .field(
-                "out_fifo_reset",
-                &format_args!("{}", self.out_fifo_reset().bit()),
-            )
+            .field("in_fifo_cnt", &self.in_fifo_cnt())
+            .field("in_fifo_empty", &self.in_fifo_empty())
+            .field("in_fifo_full", &self.in_fifo_full())
+            .field("out_fifo_cnt", &self.out_fifo_cnt())
+            .field("out_fifo_empty", &self.out_fifo_empty())
+            .field("out_fifo_full", &self.out_fifo_full())
+            .field("in_fifo_reset", &self.in_fifo_reset())
+            .field("out_fifo_reset", &self.out_fifo_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<JFIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - Write 1 to reset JTAG in fifo."]
     #[inline(always)]
diff --git a/esp32h2/src/usb_device/mem_conf.rs b/esp32h2/src/usb_device/mem_conf.rs
index 682d7c5986..b96d8a21a7 100644
--- a/esp32h2/src/usb_device/mem_conf.rs
+++ b/esp32h2/src/usb_device/mem_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field("usb_mem_pd", &format_args!("{}", self.usb_mem_pd().bit()))
-            .field(
-                "usb_mem_clk_en",
-                &format_args!("{}", self.usb_mem_clk_en().bit()),
-            )
+            .field("usb_mem_pd", &self.usb_mem_pd())
+            .field("usb_mem_clk_en", &self.usb_mem_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: power down usb memory."]
     #[inline(always)]
diff --git a/esp32h2/src/usb_device/misc_conf.rs b/esp32h2/src/usb_device/misc_conf.rs
index 22aeb01318..096db71403 100644
--- a/esp32h2/src/usb_device/misc_conf.rs
+++ b/esp32h2/src/usb_device/misc_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC_CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
     #[inline(always)]
diff --git a/esp32h2/src/usb_device/out_ep0_st.rs b/esp32h2/src/usb_device/out_ep0_st.rs
index beccea168f..9778c6853e 100644
--- a/esp32h2/src/usb_device/out_ep0_st.rs
+++ b/esp32h2/src/usb_device/out_ep0_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EP0_ST")
-            .field(
-                "out_ep0_state",
-                &format_args!("{}", self.out_ep0_state().bits()),
-            )
-            .field(
-                "out_ep0_wr_addr",
-                &format_args!("{}", self.out_ep0_wr_addr().bits()),
-            )
-            .field(
-                "out_ep0_rd_addr",
-                &format_args!("{}", self.out_ep0_rd_addr().bits()),
-            )
+            .field("out_ep0_state", &self.out_ep0_state())
+            .field("out_ep0_wr_addr", &self.out_ep0_wr_addr())
+            .field("out_ep0_rd_addr", &self.out_ep0_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EP0_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Control OUT endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep0_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EP0_ST_SPEC;
 impl crate::RegisterSpec for OUT_EP0_ST_SPEC {
diff --git a/esp32h2/src/usb_device/out_ep1_st.rs b/esp32h2/src/usb_device/out_ep1_st.rs
index 81d1afe476..d1fdcebd8e 100644
--- a/esp32h2/src/usb_device/out_ep1_st.rs
+++ b/esp32h2/src/usb_device/out_ep1_st.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EP1_ST")
-            .field(
-                "out_ep1_state",
-                &format_args!("{}", self.out_ep1_state().bits()),
-            )
-            .field(
-                "out_ep1_wr_addr",
-                &format_args!("{}", self.out_ep1_wr_addr().bits()),
-            )
-            .field(
-                "out_ep1_rd_addr",
-                &format_args!("{}", self.out_ep1_rd_addr().bits()),
-            )
-            .field(
-                "out_ep1_rec_data_cnt",
-                &format_args!("{}", self.out_ep1_rec_data_cnt().bits()),
-            )
+            .field("out_ep1_state", &self.out_ep1_state())
+            .field("out_ep1_wr_addr", &self.out_ep1_wr_addr())
+            .field("out_ep1_rd_addr", &self.out_ep1_rd_addr())
+            .field("out_ep1_rec_data_cnt", &self.out_ep1_rec_data_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EP1_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CDC-ACM OUT endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep1_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EP1_ST_SPEC;
 impl crate::RegisterSpec for OUT_EP1_ST_SPEC {
diff --git a/esp32h2/src/usb_device/out_ep2_st.rs b/esp32h2/src/usb_device/out_ep2_st.rs
index 8e7c84db34..f4bfad5198 100644
--- a/esp32h2/src/usb_device/out_ep2_st.rs
+++ b/esp32h2/src/usb_device/out_ep2_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EP2_ST")
-            .field(
-                "out_ep2_state",
-                &format_args!("{}", self.out_ep2_state().bits()),
-            )
-            .field(
-                "out_ep2_wr_addr",
-                &format_args!("{}", self.out_ep2_wr_addr().bits()),
-            )
-            .field(
-                "out_ep2_rd_addr",
-                &format_args!("{}", self.out_ep2_rd_addr().bits()),
-            )
+            .field("out_ep2_state", &self.out_ep2_state())
+            .field("out_ep2_wr_addr", &self.out_ep2_wr_addr())
+            .field("out_ep2_rd_addr", &self.out_ep2_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EP2_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "JTAG OUT endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep2_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EP2_ST_SPEC;
 impl crate::RegisterSpec for OUT_EP2_ST_SPEC {
diff --git a/esp32h2/src/usb_device/ser_afifo_config.rs b/esp32h2/src/usb_device/ser_afifo_config.rs
index f1fd3f981b..dad03c2716 100644
--- a/esp32h2/src/usb_device/ser_afifo_config.rs
+++ b/esp32h2/src/usb_device/ser_afifo_config.rs
@@ -58,39 +58,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SER_AFIFO_CONFIG")
-            .field(
-                "serial_in_afifo_reset_wr",
-                &format_args!("{}", self.serial_in_afifo_reset_wr().bit()),
-            )
-            .field(
-                "serial_in_afifo_reset_rd",
-                &format_args!("{}", self.serial_in_afifo_reset_rd().bit()),
-            )
+            .field("serial_in_afifo_reset_wr", &self.serial_in_afifo_reset_wr())
+            .field("serial_in_afifo_reset_rd", &self.serial_in_afifo_reset_rd())
             .field(
                 "serial_out_afifo_reset_wr",
-                &format_args!("{}", self.serial_out_afifo_reset_wr().bit()),
+                &self.serial_out_afifo_reset_wr(),
             )
             .field(
                 "serial_out_afifo_reset_rd",
-                &format_args!("{}", self.serial_out_afifo_reset_rd().bit()),
-            )
-            .field(
-                "serial_out_afifo_rempty",
-                &format_args!("{}", self.serial_out_afifo_rempty().bit()),
-            )
-            .field(
-                "serial_in_afifo_wfull",
-                &format_args!("{}", self.serial_in_afifo_wfull().bit()),
+                &self.serial_out_afifo_reset_rd(),
             )
+            .field("serial_out_afifo_rempty", &self.serial_out_afifo_rempty())
+            .field("serial_in_afifo_wfull", &self.serial_in_afifo_wfull())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SER_AFIFO_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to reset CDC_ACM IN async FIFO write clock domain."]
     #[inline(always)]
diff --git a/esp32h2/src/usb_device/set_line_code_w0.rs b/esp32h2/src/usb_device/set_line_code_w0.rs
index c604ef35cd..5fbf6698b5 100644
--- a/esp32h2/src/usb_device/set_line_code_w0.rs
+++ b/esp32h2/src/usb_device/set_line_code_w0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SET_LINE_CODE_W0")
-            .field(
-                "dw_dte_rate",
-                &format_args!("{}", self.dw_dte_rate().bits()),
-            )
+            .field("dw_dte_rate", &self.dw_dte_rate())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SET_LINE_CODE_W0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "W0 of SET_LINE_CODING command.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set_line_code_w0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SET_LINE_CODE_W0_SPEC;
 impl crate::RegisterSpec for SET_LINE_CODE_W0_SPEC {
diff --git a/esp32h2/src/usb_device/set_line_code_w1.rs b/esp32h2/src/usb_device/set_line_code_w1.rs
index 0af91af4b5..214022604e 100644
--- a/esp32h2/src/usb_device/set_line_code_w1.rs
+++ b/esp32h2/src/usb_device/set_line_code_w1.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SET_LINE_CODE_W1")
-            .field(
-                "bchar_format",
-                &format_args!("{}", self.bchar_format().bits()),
-            )
-            .field(
-                "bparity_type",
-                &format_args!("{}", self.bparity_type().bits()),
-            )
-            .field("bdata_bits", &format_args!("{}", self.bdata_bits().bits()))
+            .field("bchar_format", &self.bchar_format())
+            .field("bparity_type", &self.bparity_type())
+            .field("bdata_bits", &self.bdata_bits())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SET_LINE_CODE_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "W1 of SET_LINE_CODING command.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set_line_code_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SET_LINE_CODE_W1_SPEC;
 impl crate::RegisterSpec for SET_LINE_CODE_W1_SPEC {
diff --git a/esp32h2/src/usb_device/test.rs b/esp32h2/src/usb_device/test.rs
index 031148c329..10c7308a91 100644
--- a/esp32h2/src/usb_device/test.rs
+++ b/esp32h2/src/usb_device/test.rs
@@ -65,22 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEST")
-            .field("test_enable", &format_args!("{}", self.test_enable().bit()))
-            .field("test_usb_oe", &format_args!("{}", self.test_usb_oe().bit()))
-            .field("test_tx_dp", &format_args!("{}", self.test_tx_dp().bit()))
-            .field("test_tx_dm", &format_args!("{}", self.test_tx_dm().bit()))
-            .field("test_rx_rcv", &format_args!("{}", self.test_rx_rcv().bit()))
-            .field("test_rx_dp", &format_args!("{}", self.test_rx_dp().bit()))
-            .field("test_rx_dm", &format_args!("{}", self.test_rx_dm().bit()))
+            .field("test_enable", &self.test_enable())
+            .field("test_usb_oe", &self.test_usb_oe())
+            .field("test_tx_dp", &self.test_tx_dp())
+            .field("test_tx_dm", &self.test_tx_dm())
+            .field("test_rx_rcv", &self.test_rx_rcv())
+            .field("test_rx_dp", &self.test_rx_dp())
+            .field("test_rx_dm", &self.test_rx_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable test of the USB pad"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/arb_ctrl.rs b/esp32p4/src/adc/arb_ctrl.rs
index 6649ba8a2a..7ae1780099 100644
--- a/esp32p4/src/adc/arb_ctrl.rs
+++ b/esp32p4/src/adc/arb_ctrl.rs
@@ -80,35 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_CTRL")
-            .field("apb_force", &format_args!("{}", self.apb_force().bit()))
-            .field("rtc_force", &format_args!("{}", self.rtc_force().bit()))
-            .field("wifi_force", &format_args!("{}", self.wifi_force().bit()))
-            .field("grant_force", &format_args!("{}", self.grant_force().bit()))
-            .field(
-                "apb_priority",
-                &format_args!("{}", self.apb_priority().bits()),
-            )
-            .field(
-                "rtc_priority",
-                &format_args!("{}", self.rtc_priority().bits()),
-            )
-            .field(
-                "wifi_priority",
-                &format_args!("{}", self.wifi_priority().bits()),
-            )
-            .field(
-                "fix_priority",
-                &format_args!("{}", self.fix_priority().bit()),
-            )
+            .field("apb_force", &self.apb_force())
+            .field("rtc_force", &self.rtc_force())
+            .field("wifi_force", &self.wifi_force())
+            .field("grant_force", &self.grant_force())
+            .field("apb_priority", &self.apb_priority())
+            .field("rtc_priority", &self.rtc_priority())
+            .field("wifi_priority", &self.wifi_priority())
+            .field("fix_priority", &self.fix_priority())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - adc2 arbiter force to enableapb controller"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/cali.rs b/esp32p4/src/adc/cali.rs
index 70c5eb2fbe..9e6ef6c9f0 100644
--- a/esp32p4/src/adc/cali.rs
+++ b/esp32p4/src/adc/cali.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CALI")
-            .field("cfg", &format_args!("{}", self.cfg().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CALI").field("cfg", &self.cfg()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/adc/ctrl.rs b/esp32p4/src/adc/ctrl.rs
index 91cd516fcc..3c49e11324 100644
--- a/esp32p4/src/adc/ctrl.rs
+++ b/esp32p4/src/adc/ctrl.rs
@@ -143,60 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("start_force", &format_args!("{}", self.start_force().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("work_mode", &format_args!("{}", self.work_mode().bits()))
-            .field("sar_sel", &format_args!("{}", self.sar_sel().bit()))
-            .field(
-                "sar_clk_gated",
-                &format_args!("{}", self.sar_clk_gated().bit()),
-            )
-            .field(
-                "sar_clk_div",
-                &format_args!("{}", self.sar_clk_div().bits()),
-            )
-            .field(
-                "sar1_patt_len",
-                &format_args!("{}", self.sar1_patt_len().bits()),
-            )
-            .field(
-                "sar2_patt_len",
-                &format_args!("{}", self.sar2_patt_len().bits()),
-            )
-            .field(
-                "sar1_patt_p_clear",
-                &format_args!("{}", self.sar1_patt_p_clear().bit()),
-            )
-            .field(
-                "sar2_patt_p_clear",
-                &format_args!("{}", self.sar2_patt_p_clear().bit()),
-            )
-            .field(
-                "data_sar_sel",
-                &format_args!("{}", self.data_sar_sel().bit()),
-            )
-            .field("data_to_i2s", &format_args!("{}", self.data_to_i2s().bit()))
-            .field(
-                "xpd_sar1_force",
-                &format_args!("{}", self.xpd_sar1_force().bits()),
-            )
-            .field(
-                "xpd_sar2_force",
-                &format_args!("{}", self.xpd_sar2_force().bits()),
-            )
-            .field(
-                "wait_arb_cycle",
-                &format_args!("{}", self.wait_arb_cycle().bits()),
-            )
+            .field("start_force", &self.start_force())
+            .field("start", &self.start())
+            .field("work_mode", &self.work_mode())
+            .field("sar_sel", &self.sar_sel())
+            .field("sar_clk_gated", &self.sar_clk_gated())
+            .field("sar_clk_div", &self.sar_clk_div())
+            .field("sar1_patt_len", &self.sar1_patt_len())
+            .field("sar2_patt_len", &self.sar2_patt_len())
+            .field("sar1_patt_p_clear", &self.sar1_patt_p_clear())
+            .field("sar2_patt_p_clear", &self.sar2_patt_p_clear())
+            .field("data_sar_sel", &self.data_sar_sel())
+            .field("data_to_i2s", &self.data_to_i2s())
+            .field("xpd_sar1_force", &self.xpd_sar1_force())
+            .field("xpd_sar2_force", &self.xpd_sar2_force())
+            .field("wait_arb_cycle", &self.wait_arb_cycle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/ctrl2.rs b/esp32p4/src/adc/ctrl2.rs
index 9861083eda..6093e9d7b0 100644
--- a/esp32p4/src/adc/ctrl2.rs
+++ b/esp32p4/src/adc/ctrl2.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field(
-                "meas_num_limit",
-                &format_args!("{}", self.meas_num_limit().bit()),
-            )
-            .field(
-                "max_meas_num",
-                &format_args!("{}", self.max_meas_num().bits()),
-            )
-            .field("sar1_inv", &format_args!("{}", self.sar1_inv().bit()))
-            .field("sar2_inv", &format_args!("{}", self.sar2_inv().bit()))
-            .field("timer_sel", &format_args!("{}", self.timer_sel().bit()))
-            .field(
-                "timer_target",
-                &format_args!("{}", self.timer_target().bits()),
-            )
-            .field("timer_en", &format_args!("{}", self.timer_en().bit()))
+            .field("meas_num_limit", &self.meas_num_limit())
+            .field("max_meas_num", &self.max_meas_num())
+            .field("sar1_inv", &self.sar1_inv())
+            .field("sar2_inv", &self.sar2_inv())
+            .field("timer_sel", &self.timer_sel())
+            .field("timer_target", &self.timer_target())
+            .field("timer_en", &self.timer_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/ctrl_date.rs b/esp32p4/src/adc/ctrl_date.rs
index 6c9065223c..776b012ad6 100644
--- a/esp32p4/src/adc/ctrl_date.rs
+++ b/esp32p4/src/adc/ctrl_date.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL_DATE")
-            .field("ctrl_date", &format_args!("{}", self.ctrl_date().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("ctrl_date", &self.ctrl_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/dma_conf.rs b/esp32p4/src/adc/dma_conf.rs
index 29d62fd787..2c40727412 100644
--- a/esp32p4/src/adc/dma_conf.rs
+++ b/esp32p4/src/adc/dma_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field(
-                "adc_eof_num",
-                &format_args!("{}", self.adc_eof_num().bits()),
-            )
-            .field(
-                "adc_reset_fsm",
-                &format_args!("{}", self.adc_reset_fsm().bit()),
-            )
-            .field("adc_trans", &format_args!("{}", self.adc_trans().bit()))
+            .field("adc_eof_num", &self.adc_eof_num())
+            .field("adc_reset_fsm", &self.adc_reset_fsm())
+            .field("adc_trans", &self.adc_trans())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - the dma_in_suc_eof gen when sample cnt = spi_eof_num"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/filter_ctrl0.rs b/esp32p4/src/adc/filter_ctrl0.rs
index 0e386199f9..27f59cb0cc 100644
--- a/esp32p4/src/adc/filter_ctrl0.rs
+++ b/esp32p4/src/adc/filter_ctrl0.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CTRL0")
-            .field(
-                "filter_channel1",
-                &format_args!("{}", self.filter_channel1().bits()),
-            )
-            .field(
-                "filter_channel0",
-                &format_args!("{}", self.filter_channel0().bits()),
-            )
-            .field(
-                "filter_reset",
-                &format_args!("{}", self.filter_reset().bit()),
-            )
+            .field("filter_channel1", &self.filter_channel1())
+            .field("filter_channel0", &self.filter_channel0())
+            .field("filter_reset", &self.filter_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 14:18 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/filter_ctrl1.rs b/esp32p4/src/adc/filter_ctrl1.rs
index be5824e7b8..2e6dae5569 100644
--- a/esp32p4/src/adc/filter_ctrl1.rs
+++ b/esp32p4/src/adc/filter_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CTRL1")
-            .field(
-                "filter_factor1",
-                &format_args!("{}", self.filter_factor1().bits()),
-            )
-            .field(
-                "filter_factor0",
-                &format_args!("{}", self.filter_factor0().bits()),
-            )
+            .field("filter_factor1", &self.filter_factor1())
+            .field("filter_factor0", &self.filter_factor0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 26:28 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/fsm_wait.rs b/esp32p4/src/adc/fsm_wait.rs
index 3a31dd65fb..6c5a9ba5b9 100644
--- a/esp32p4/src/adc/fsm_wait.rs
+++ b/esp32p4/src/adc/fsm_wait.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_WAIT")
-            .field("xpd_wait", &format_args!("{}", self.xpd_wait().bits()))
-            .field("rstb_wait", &format_args!("{}", self.rstb_wait().bits()))
-            .field(
-                "standby_wait",
-                &format_args!("{}", self.standby_wait().bits()),
-            )
+            .field("xpd_wait", &self.xpd_wait())
+            .field("rstb_wait", &self.rstb_wait())
+            .field("standby_wait", &self.standby_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_WAIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/int_ena.rs b/esp32p4/src/adc/int_ena.rs
index 08f1014dd2..d1bacc75ad 100644
--- a/esp32p4/src/adc/int_ena.rs
+++ b/esp32p4/src/adc/int_ena.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/int_raw.rs b/esp32p4/src/adc/int_raw.rs
index fcdeb8a3f3..1222a73957 100644
--- a/esp32p4/src/adc/int_raw.rs
+++ b/esp32p4/src/adc/int_raw.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/int_st.rs b/esp32p4/src/adc/int_st.rs
index f970e6c5df..f56feca665 100644
--- a/esp32p4/src/adc/int_st.rs
+++ b/esp32p4/src/adc/int_st.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/adc/rnd_eco_cs.rs b/esp32p4/src/adc/rnd_eco_cs.rs
index d53c870493..e62ebfd027 100644
--- a/esp32p4/src/adc/rnd_eco_cs.rs
+++ b/esp32p4/src/adc/rnd_eco_cs.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_CS")
-            .field("rnd_eco_en", &format_args!("{}", self.rnd_eco_en().bit()))
-            .field(
-                "rnd_eco_result",
-                &format_args!("{}", self.rnd_eco_result().bit()),
-            )
+            .field("rnd_eco_en", &self.rnd_eco_en())
+            .field("rnd_eco_result", &self.rnd_eco_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_CS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/rnd_eco_high.rs b/esp32p4/src/adc/rnd_eco_high.rs
index e59e5ab12a..acfcaa59e4 100644
--- a/esp32p4/src/adc/rnd_eco_high.rs
+++ b/esp32p4/src/adc/rnd_eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_HIGH")
-            .field(
-                "rnd_eco_high",
-                &format_args!("{}", self.rnd_eco_high().bits()),
-            )
+            .field("rnd_eco_high", &self.rnd_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - rnd eco high"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/rnd_eco_low.rs b/esp32p4/src/adc/rnd_eco_low.rs
index 4904901fd3..ed4bb68fb5 100644
--- a/esp32p4/src/adc/rnd_eco_low.rs
+++ b/esp32p4/src/adc/rnd_eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_LOW")
-            .field(
-                "rnd_eco_low",
-                &format_args!("{}", self.rnd_eco_low().bits()),
-            )
+            .field("rnd_eco_low", &self.rnd_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - rnd eco low"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/sar1_data_status.rs b/esp32p4/src/adc/sar1_data_status.rs
index f4cbdf28a1..d98bd39a2e 100644
--- a/esp32p4/src/adc/sar1_data_status.rs
+++ b/esp32p4/src/adc/sar1_data_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_DATA_STATUS")
-            .field(
-                "apb_saradc1_data",
-                &format_args!("{}", self.apb_saradc1_data().bits()),
-            )
+            .field("apb_saradc1_data", &self.apb_saradc1_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_DATA_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_data_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR1_DATA_STATUS_SPEC;
 impl crate::RegisterSpec for SAR1_DATA_STATUS_SPEC {
diff --git a/esp32p4/src/adc/sar1_patt_tab1.rs b/esp32p4/src/adc/sar1_patt_tab1.rs
index 0ad58c035e..488a704ed6 100644
--- a/esp32p4/src/adc/sar1_patt_tab1.rs
+++ b/esp32p4/src/adc/sar1_patt_tab1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_PATT_TAB1")
-            .field(
-                "sar1_patt_tab1",
-                &format_args!("{}", self.sar1_patt_tab1().bits()),
-            )
+            .field("sar1_patt_tab1", &self.sar1_patt_tab1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_PATT_TAB1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/sar1_patt_tab2.rs b/esp32p4/src/adc/sar1_patt_tab2.rs
index 3be45903b1..dc60214020 100644
--- a/esp32p4/src/adc/sar1_patt_tab2.rs
+++ b/esp32p4/src/adc/sar1_patt_tab2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_PATT_TAB2")
-            .field(
-                "sar1_patt_tab2",
-                &format_args!("{}", self.sar1_patt_tab2().bits()),
-            )
+            .field("sar1_patt_tab2", &self.sar1_patt_tab2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_PATT_TAB2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/sar1_patt_tab3.rs b/esp32p4/src/adc/sar1_patt_tab3.rs
index d9a35edf57..729dffe308 100644
--- a/esp32p4/src/adc/sar1_patt_tab3.rs
+++ b/esp32p4/src/adc/sar1_patt_tab3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_PATT_TAB3")
-            .field(
-                "sar1_patt_tab3",
-                &format_args!("{}", self.sar1_patt_tab3().bits()),
-            )
+            .field("sar1_patt_tab3", &self.sar1_patt_tab3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_PATT_TAB3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/sar1_patt_tab4.rs b/esp32p4/src/adc/sar1_patt_tab4.rs
index 8aca90a50a..394954d3d0 100644
--- a/esp32p4/src/adc/sar1_patt_tab4.rs
+++ b/esp32p4/src/adc/sar1_patt_tab4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_PATT_TAB4")
-            .field(
-                "sar1_patt_tab4",
-                &format_args!("{}", self.sar1_patt_tab4().bits()),
-            )
+            .field("sar1_patt_tab4", &self.sar1_patt_tab4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_PATT_TAB4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/sar1_status.rs b/esp32p4/src/adc/sar1_status.rs
index 9bcbea0a3f..f4c48a2610 100644
--- a/esp32p4/src/adc/sar1_status.rs
+++ b/esp32p4/src/adc/sar1_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_STATUS")
-            .field(
-                "sar1_status",
-                &format_args!("{}", self.sar1_status().bits()),
-            )
+            .field("sar1_status", &self.sar1_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR1_STATUS_SPEC;
 impl crate::RegisterSpec for SAR1_STATUS_SPEC {
diff --git a/esp32p4/src/adc/sar2_data_status.rs b/esp32p4/src/adc/sar2_data_status.rs
index 833756d9f9..d37d846080 100644
--- a/esp32p4/src/adc/sar2_data_status.rs
+++ b/esp32p4/src/adc/sar2_data_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_DATA_STATUS")
-            .field(
-                "apb_saradc2_data",
-                &format_args!("{}", self.apb_saradc2_data().bits()),
-            )
+            .field("apb_saradc2_data", &self.apb_saradc2_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_DATA_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_data_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR2_DATA_STATUS_SPEC;
 impl crate::RegisterSpec for SAR2_DATA_STATUS_SPEC {
diff --git a/esp32p4/src/adc/sar2_patt_tab1.rs b/esp32p4/src/adc/sar2_patt_tab1.rs
index 7213d62ee4..a6c1997f06 100644
--- a/esp32p4/src/adc/sar2_patt_tab1.rs
+++ b/esp32p4/src/adc/sar2_patt_tab1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_PATT_TAB1")
-            .field(
-                "sar2_patt_tab1",
-                &format_args!("{}", self.sar2_patt_tab1().bits()),
-            )
+            .field("sar2_patt_tab1", &self.sar2_patt_tab1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_PATT_TAB1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 2 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/sar2_patt_tab2.rs b/esp32p4/src/adc/sar2_patt_tab2.rs
index ea266ffe47..7e4063a727 100644
--- a/esp32p4/src/adc/sar2_patt_tab2.rs
+++ b/esp32p4/src/adc/sar2_patt_tab2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_PATT_TAB2")
-            .field(
-                "sar2_patt_tab2",
-                &format_args!("{}", self.sar2_patt_tab2().bits()),
-            )
+            .field("sar2_patt_tab2", &self.sar2_patt_tab2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_PATT_TAB2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 2 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/sar2_patt_tab3.rs b/esp32p4/src/adc/sar2_patt_tab3.rs
index 9d7c3af9e1..ad91fd4c6e 100644
--- a/esp32p4/src/adc/sar2_patt_tab3.rs
+++ b/esp32p4/src/adc/sar2_patt_tab3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_PATT_TAB3")
-            .field(
-                "sar2_patt_tab3",
-                &format_args!("{}", self.sar2_patt_tab3().bits()),
-            )
+            .field("sar2_patt_tab3", &self.sar2_patt_tab3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_PATT_TAB3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 2 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/sar2_patt_tab4.rs b/esp32p4/src/adc/sar2_patt_tab4.rs
index 6eb7de1faa..7fa11c55e9 100644
--- a/esp32p4/src/adc/sar2_patt_tab4.rs
+++ b/esp32p4/src/adc/sar2_patt_tab4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_PATT_TAB4")
-            .field(
-                "sar2_patt_tab4",
-                &format_args!("{}", self.sar2_patt_tab4().bits()),
-            )
+            .field("sar2_patt_tab4", &self.sar2_patt_tab4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_PATT_TAB4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 2 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/sar2_status.rs b/esp32p4/src/adc/sar2_status.rs
index 3797aa4045..53eb749a88 100644
--- a/esp32p4/src/adc/sar2_status.rs
+++ b/esp32p4/src/adc/sar2_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_STATUS")
-            .field(
-                "sar2_status",
-                &format_args!("{}", self.sar2_status().bits()),
-            )
+            .field("sar2_status", &self.sar2_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR2_STATUS_SPEC;
 impl crate::RegisterSpec for SAR2_STATUS_SPEC {
diff --git a/esp32p4/src/adc/thres0_ctrl.rs b/esp32p4/src/adc/thres0_ctrl.rs
index 18db53bf57..b0f55dfb56 100644
--- a/esp32p4/src/adc/thres0_ctrl.rs
+++ b/esp32p4/src/adc/thres0_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES0_CTRL")
-            .field(
-                "thres0_channel",
-                &format_args!("{}", self.thres0_channel().bits()),
-            )
-            .field(
-                "thres0_high",
-                &format_args!("{}", self.thres0_high().bits()),
-            )
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bits()))
+            .field("thres0_channel", &self.thres0_channel())
+            .field("thres0_high", &self.thres0_high())
+            .field("thres0_low", &self.thres0_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES0_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/thres1_ctrl.rs b/esp32p4/src/adc/thres1_ctrl.rs
index 8f120c35b1..93e148c3c9 100644
--- a/esp32p4/src/adc/thres1_ctrl.rs
+++ b/esp32p4/src/adc/thres1_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES1_CTRL")
-            .field(
-                "thres1_channel",
-                &format_args!("{}", self.thres1_channel().bits()),
-            )
-            .field(
-                "thres1_high",
-                &format_args!("{}", self.thres1_high().bits()),
-            )
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bits()))
+            .field("thres1_channel", &self.thres1_channel())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres1_low", &self.thres1_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES1_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/adc/thres_ctrl.rs b/esp32p4/src/adc/thres_ctrl.rs
index ead0a2d90e..d6669ffee4 100644
--- a/esp32p4/src/adc/thres_ctrl.rs
+++ b/esp32p4/src/adc/thres_ctrl.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES_CTRL")
-            .field(
-                "thres_all_en",
-                &format_args!("{}", self.thres_all_en().bit()),
-            )
-            .field("thres3_en", &format_args!("{}", self.thres3_en().bit()))
-            .field("thres2_en", &format_args!("{}", self.thres2_en().bit()))
-            .field("thres1_en", &format_args!("{}", self.thres1_en().bit()))
-            .field("thres0_en", &format_args!("{}", self.thres0_en().bit()))
+            .field("thres_all_en", &self.thres_all_en())
+            .field("thres3_en", &self.thres3_en())
+            .field("thres2_en", &self.thres2_en())
+            .field("thres1_en", &self.thres1_en())
+            .field("thres0_en", &self.thres0_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/aes/aad_block_num.rs b/esp32p4/src/aes/aad_block_num.rs
index 75e37b35ae..34160ca226 100644
--- a/esp32p4/src/aes/aad_block_num.rs
+++ b/esp32p4/src/aes/aad_block_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AAD_BLOCK_NUM")
-            .field(
-                "aad_block_num",
-                &format_args!("{}", self.aad_block_num().bits()),
-            )
+            .field("aad_block_num", &self.aad_block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AAD_BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits stores the number of AAD block."]
     #[inline(always)]
diff --git a/esp32p4/src/aes/block_mode.rs b/esp32p4/src/aes/block_mode.rs
index e1da4c4f3c..b2e3b5efc6 100644
--- a/esp32p4/src/aes/block_mode.rs
+++ b/esp32p4/src/aes/block_mode.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLOCK_MODE")
-            .field("block_mode", &format_args!("{}", self.block_mode().bits()))
+            .field("block_mode", &self.block_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLOCK_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved."]
     #[inline(always)]
diff --git a/esp32p4/src/aes/block_num.rs b/esp32p4/src/aes/block_num.rs
index 80e2290bb3..a1897ab822 100644
--- a/esp32p4/src/aes/block_num.rs
+++ b/esp32p4/src/aes/block_num.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLOCK_NUM")
-            .field("block_num", &format_args!("{}", self.block_num().bits()))
+            .field("block_num", &self.block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits stores the number of Plaintext/ciphertext block."]
     #[inline(always)]
diff --git a/esp32p4/src/aes/date.rs b/esp32p4/src/aes/date.rs
index a22c32c101..5e7e48df64 100644
--- a/esp32p4/src/aes/date.rs
+++ b/esp32p4/src/aes/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/aes/dma_enable.rs b/esp32p4/src/aes/dma_enable.rs
index 3fa34abee5..1f5f535a07 100644
--- a/esp32p4/src/aes/dma_enable.rs
+++ b/esp32p4/src/aes/dma_enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_ENABLE")
-            .field("dma_enable", &format_args!("{}", self.dma_enable().bit()))
+            .field("dma_enable", &self.dma_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."]
     #[inline(always)]
diff --git a/esp32p4/src/aes/endian.rs b/esp32p4/src/aes/endian.rs
index e5a3e93efc..30ecf46902 100644
--- a/esp32p4/src/aes/endian.rs
+++ b/esp32p4/src/aes/endian.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENDIAN")
-            .field("endian", &format_args!("{}", self.endian().bits()))
+            .field("endian", &self.endian())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENDIAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - endian. \\[1:0\\] key endian, \\[3:2\\] text_in endian or in_stream endian, \\[5:4\\] text_out endian or out_stream endian"]
     #[inline(always)]
diff --git a/esp32p4/src/aes/h_mem.rs b/esp32p4/src/aes/h_mem.rs
index fcd1d250f9..2e4334ff37 100644
--- a/esp32p4/src/aes/h_mem.rs
+++ b/esp32p4/src/aes/h_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores GCM hash subkey\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct H_MEM_SPEC;
diff --git a/esp32p4/src/aes/inc_sel.rs b/esp32p4/src/aes/inc_sel.rs
index a6665d07ec..69d24607c0 100644
--- a/esp32p4/src/aes/inc_sel.rs
+++ b/esp32p4/src/aes/inc_sel.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INC_SEL")
-            .field("inc_sel", &format_args!("{}", self.inc_sel().bit()))
+            .field("inc_sel", &self.inc_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INC_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit decides the standard incrementing function. 0: INC32. 1: INC128."]
     #[inline(always)]
diff --git a/esp32p4/src/aes/int_ena.rs b/esp32p4/src/aes/int_ena.rs
index ccd96d099f..1abedbe830 100644
--- a/esp32p4/src/aes/int_ena.rs
+++ b/esp32p4/src/aes/int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("int_ena", &format_args!("{}", self.int_ena().bit()))
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable interrupt that occurs when DMA-AES calculation is done."]
     #[inline(always)]
diff --git a/esp32p4/src/aes/iv_mem.rs b/esp32p4/src/aes/iv_mem.rs
index e8b4d332de..20bdbb631b 100644
--- a/esp32p4/src/aes/iv_mem.rs
+++ b/esp32p4/src/aes/iv_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IV_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores initialization vector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iv_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iv_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IV_MEM_SPEC;
diff --git a/esp32p4/src/aes/j0_mem.rs b/esp32p4/src/aes/j0_mem.rs
index a78fdd3452..002c675bfe 100644
--- a/esp32p4/src/aes/j0_mem.rs
+++ b/esp32p4/src/aes/j0_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<J0_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores J0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`j0_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`j0_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct J0_MEM_SPEC;
diff --git a/esp32p4/src/aes/key.rs b/esp32p4/src/aes/key.rs
index 8b2a51282a..c1d2c046ad 100644
--- a/esp32p4/src/aes/key.rs
+++ b/esp32p4/src/aes/key.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("KEY")
-            .field("key", &format_args!("{}", self.key().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<KEY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("KEY").field("key", &self.key()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/aes/mode.rs b/esp32p4/src/aes/mode.rs
index edc4a67756..aa353f24b7 100644
--- a/esp32p4/src/aes/mode.rs
+++ b/esp32p4/src/aes/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/aes/remainder_bit_num.rs b/esp32p4/src/aes/remainder_bit_num.rs
index 330809cbc6..73a3610f09 100644
--- a/esp32p4/src/aes/remainder_bit_num.rs
+++ b/esp32p4/src/aes/remainder_bit_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REMAINDER_BIT_NUM")
-            .field(
-                "remainder_bit_num",
-                &format_args!("{}", self.remainder_bit_num().bits()),
-            )
+            .field("remainder_bit_num", &self.remainder_bit_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REMAINDER_BIT_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Those bits stores the number of remainder bit."]
     #[inline(always)]
diff --git a/esp32p4/src/aes/state.rs b/esp32p4/src/aes/state.rs
index 5a58b13248..8a38798ae3 100644
--- a/esp32p4/src/aes/state.rs
+++ b/esp32p4/src/aes/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("state", &format_args!("{}", self.state().bits()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "AES state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32p4/src/aes/t0_mem.rs b/esp32p4/src/aes/t0_mem.rs
index 1b3fcafdb6..e2445d62f8 100644
--- a/esp32p4/src/aes/t0_mem.rs
+++ b/esp32p4/src/aes/t0_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T0_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores T0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct T0_MEM_SPEC;
diff --git a/esp32p4/src/aes/text_in.rs b/esp32p4/src/aes/text_in.rs
index 71ff18340a..24a5810ee3 100644
--- a/esp32p4/src/aes/text_in.rs
+++ b/esp32p4/src/aes/text_in.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEXT_IN")
-            .field("text_in", &format_args!("{}", self.text_in().bits()))
+            .field("text_in", &self.text_in())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEXT_IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This bits stores text_in_0 that is a part of source text material."]
     #[inline(always)]
diff --git a/esp32p4/src/aes/text_out.rs b/esp32p4/src/aes/text_out.rs
index 4040aae24b..29f631b4b2 100644
--- a/esp32p4/src/aes/text_out.rs
+++ b/esp32p4/src/aes/text_out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEXT_OUT")
-            .field("text_out", &format_args!("{}", self.text_out().bits()))
+            .field("text_out", &self.text_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEXT_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This bits stores text_out_0 that is a part of result text material."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/ahb_test.rs b/esp32p4/src/ahb_dma/ahb_test.rs
index 28c330c261..8358a35c42 100644
--- a/esp32p4/src/ahb_dma/ahb_test.rs
+++ b/esp32p4/src/ahb_dma/ahb_test.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_TEST")
-            .field(
-                "ahb_testmode",
-                &format_args!("{}", self.ahb_testmode().bits()),
-            )
-            .field(
-                "ahb_testaddr",
-                &format_args!("{}", self.ahb_testaddr().bits()),
-            )
+            .field("ahb_testmode", &self.ahb_testmode())
+            .field("ahb_testaddr", &self.ahb_testaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_TEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/arb_timeout_rx.rs b/esp32p4/src/ahb_dma/arb_timeout_rx.rs
index 036973832c..d8bd782083 100644
--- a/esp32p4/src/ahb_dma/arb_timeout_rx.rs
+++ b/esp32p4/src/ahb_dma/arb_timeout_rx.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_TIMEOUT_RX")
-            .field(
-                "arb_timeout_rx",
-                &format_args!("{}", self.arb_timeout_rx().bits()),
-            )
+            .field("arb_timeout_rx", &self.arb_timeout_rx())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_TIMEOUT_RX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to config arbiter time out value"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/arb_timeout_tx.rs b/esp32p4/src/ahb_dma/arb_timeout_tx.rs
index 2fa50e61dc..145cfc9698 100644
--- a/esp32p4/src/ahb_dma/arb_timeout_tx.rs
+++ b/esp32p4/src/ahb_dma/arb_timeout_tx.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_TIMEOUT_TX")
-            .field(
-                "arb_timeout_tx",
-                &format_args!("{}", self.arb_timeout_tx().bits()),
-            )
+            .field("arb_timeout_tx", &self.arb_timeout_tx())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_TIMEOUT_TX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to config arbiter time out value"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/ch/in_conf0.rs b/esp32p4/src/ahb_dma/ch/in_conf0.rs
index ba08421bcf..2e8a286c51 100644
--- a/esp32p4/src/ahb_dma/ch/in_conf0.rs
+++ b/esp32p4/src/ahb_dma/ch/in_conf0.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF0")
-            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
-            .field(
-                "in_loop_test",
-                &format_args!("{}", self.in_loop_test().bit()),
-            )
-            .field(
-                "indscr_burst_en",
-                &format_args!("{}", self.indscr_burst_en().bit()),
-            )
-            .field(
-                "in_data_burst_en",
-                &format_args!("{}", self.in_data_burst_en().bit()),
-            )
-            .field(
-                "mem_trans_en",
-                &format_args!("{}", self.mem_trans_en().bit()),
-            )
-            .field("in_etm_en", &format_args!("{}", self.in_etm_en().bit()))
+            .field("in_rst", &self.in_rst())
+            .field("in_loop_test", &self.in_loop_test())
+            .field("indscr_burst_en", &self.indscr_burst_en())
+            .field("in_data_burst_en", &self.in_data_burst_en())
+            .field("mem_trans_en", &self.mem_trans_en())
+            .field("in_etm_en", &self.in_etm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/ch/in_conf1.rs b/esp32p4/src/ahb_dma/ch/in_conf1.rs
index 1da8b38f0b..d95da0040b 100644
--- a/esp32p4/src/ahb_dma/ch/in_conf1.rs
+++ b/esp32p4/src/ahb_dma/ch/in_conf1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF1")
-            .field(
-                "in_check_owner",
-                &format_args!("{}", self.in_check_owner().bit()),
-            )
+            .field("in_check_owner", &self.in_check_owner())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/ch/in_dscr.rs b/esp32p4/src/ahb_dma/ch/in_dscr.rs
index 3d348a76f4..e70d15df66 100644
--- a/esp32p4/src/ahb_dma/ch/in_dscr.rs
+++ b/esp32p4/src/ahb_dma/ch/in_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR")
-            .field(
-                "inlink_dscr",
-                &format_args!("{}", self.inlink_dscr().bits()),
-            )
+            .field("inlink_dscr", &self.inlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_SPEC;
 impl crate::RegisterSpec for IN_DSCR_SPEC {
diff --git a/esp32p4/src/ahb_dma/ch/in_dscr_bf0.rs b/esp32p4/src/ahb_dma/ch/in_dscr_bf0.rs
index e3023e2221..fca80e02f8 100644
--- a/esp32p4/src/ahb_dma/ch/in_dscr_bf0.rs
+++ b/esp32p4/src/ahb_dma/ch/in_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF0")
-            .field(
-                "inlink_dscr_bf0",
-                &format_args!("{}", self.inlink_dscr_bf0().bits()),
-            )
+            .field("inlink_dscr_bf0", &self.inlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for IN_DSCR_BF0_SPEC {
diff --git a/esp32p4/src/ahb_dma/ch/in_dscr_bf1.rs b/esp32p4/src/ahb_dma/ch/in_dscr_bf1.rs
index 457ee1455f..832bf9b92c 100644
--- a/esp32p4/src/ahb_dma/ch/in_dscr_bf1.rs
+++ b/esp32p4/src/ahb_dma/ch/in_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF1")
-            .field(
-                "inlink_dscr_bf1",
-                &format_args!("{}", self.inlink_dscr_bf1().bits()),
-            )
+            .field("inlink_dscr_bf1", &self.inlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The second-to-last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for IN_DSCR_BF1_SPEC {
diff --git a/esp32p4/src/ahb_dma/ch/in_err_eof_des_addr.rs b/esp32p4/src/ahb_dma/ch/in_err_eof_des_addr.rs
index 037171f572..63b8c75ca0 100644
--- a/esp32p4/src/ahb_dma/ch/in_err_eof_des_addr.rs
+++ b/esp32p4/src/ahb_dma/ch/in_err_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_ERR_EOF_DES_ADDR")
-            .field(
-                "in_err_eof_des_addr",
-                &format_args!("{}", self.in_err_eof_des_addr().bits()),
-            )
+            .field("in_err_eof_des_addr", &self.in_err_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_ERR_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Inlink descriptor address when errors occur of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_ERR_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_SPEC {
diff --git a/esp32p4/src/ahb_dma/ch/in_link.rs b/esp32p4/src/ahb_dma/ch/in_link.rs
index 9d71d7877e..0deb6d8365 100644
--- a/esp32p4/src/ahb_dma/ch/in_link.rs
+++ b/esp32p4/src/ahb_dma/ch/in_link.rs
@@ -30,20 +30,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_LINK")
-            .field(
-                "inlink_auto_ret",
-                &format_args!("{}", self.inlink_auto_ret().bit()),
-            )
-            .field("inlink_park", &format_args!("{}", self.inlink_park().bit()))
+            .field("inlink_auto_ret", &self.inlink_auto_ret())
+            .field("inlink_park", &self.inlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/ch/in_peri_sel.rs b/esp32p4/src/ahb_dma/ch/in_peri_sel.rs
index 2dd1412ae9..591a513f60 100644
--- a/esp32p4/src/ahb_dma/ch/in_peri_sel.rs
+++ b/esp32p4/src/ahb_dma/ch/in_peri_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_PERI_SEL")
-            .field(
-                "peri_in_sel",
-                &format_args!("{}", self.peri_in_sel().bits()),
-            )
+            .field("peri_in_sel", &self.peri_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_PERI_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/ch/in_pop.rs b/esp32p4/src/ahb_dma/ch/in_pop.rs
index ef5649b871..d2cc59b958 100644
--- a/esp32p4/src/ahb_dma/ch/in_pop.rs
+++ b/esp32p4/src/ahb_dma/ch/in_pop.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_POP")
-            .field(
-                "infifo_rdata",
-                &format_args!("{}", self.infifo_rdata().bits()),
-            )
+            .field("infifo_rdata", &self.infifo_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_POP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to pop data from AHB_DMA FIFO."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/ch/in_pri.rs b/esp32p4/src/ahb_dma/ch/in_pri.rs
index 83843e1ff5..1d4409ec1b 100644
--- a/esp32p4/src/ahb_dma/ch/in_pri.rs
+++ b/esp32p4/src/ahb_dma/ch/in_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_PRI")
-            .field("rx_pri", &format_args!("{}", self.rx_pri().bits()))
+            .field("rx_pri", &self.rx_pri())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value the higher of the priority."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/ch/in_state.rs b/esp32p4/src/ahb_dma/ch/in_state.rs
index 6c91ac50d7..83cb3124d8 100644
--- a/esp32p4/src/ahb_dma/ch/in_state.rs
+++ b/esp32p4/src/ahb_dma/ch/in_state.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_STATE")
-            .field(
-                "inlink_dscr_addr",
-                &format_args!("{}", self.inlink_dscr_addr().bits()),
-            )
-            .field(
-                "in_dscr_state",
-                &format_args!("{}", self.in_dscr_state().bits()),
-            )
-            .field("in_state", &format_args!("{}", self.in_state().bits()))
+            .field("inlink_dscr_addr", &self.inlink_dscr_addr())
+            .field("in_dscr_state", &self.in_dscr_state())
+            .field("in_state", &self.in_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_STATE_SPEC;
 impl crate::RegisterSpec for IN_STATE_SPEC {
diff --git a/esp32p4/src/ahb_dma/ch/in_suc_eof_des_addr.rs b/esp32p4/src/ahb_dma/ch/in_suc_eof_des_addr.rs
index 2b0b4e378a..bd974ca71c 100644
--- a/esp32p4/src/ahb_dma/ch/in_suc_eof_des_addr.rs
+++ b/esp32p4/src/ahb_dma/ch/in_suc_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_SUC_EOF_DES_ADDR")
-            .field(
-                "in_suc_eof_des_addr",
-                &format_args!("{}", self.in_suc_eof_des_addr().bits()),
-            )
+            .field("in_suc_eof_des_addr", &self.in_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SUC_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Inlink descriptor address when EOF occurs of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SUC_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_SPEC {
diff --git a/esp32p4/src/ahb_dma/ch/infifo_status.rs b/esp32p4/src/ahb_dma/ch/infifo_status.rs
index 083b1ccdc7..065cf9f3fe 100644
--- a/esp32p4/src/ahb_dma/ch/infifo_status.rs
+++ b/esp32p4/src/ahb_dma/ch/infifo_status.rs
@@ -62,41 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INFIFO_STATUS")
-            .field("infifo_full", &format_args!("{}", self.infifo_full().bit()))
-            .field(
-                "infifo_empty",
-                &format_args!("{}", self.infifo_empty().bit()),
-            )
-            .field("infifo_cnt", &format_args!("{}", self.infifo_cnt().bits()))
-            .field(
-                "in_remain_under_1b",
-                &format_args!("{}", self.in_remain_under_1b().bit()),
-            )
-            .field(
-                "in_remain_under_2b",
-                &format_args!("{}", self.in_remain_under_2b().bit()),
-            )
-            .field(
-                "in_remain_under_3b",
-                &format_args!("{}", self.in_remain_under_3b().bit()),
-            )
-            .field(
-                "in_remain_under_4b",
-                &format_args!("{}", self.in_remain_under_4b().bit()),
-            )
-            .field(
-                "in_buf_hungry",
-                &format_args!("{}", self.in_buf_hungry().bit()),
-            )
+            .field("infifo_full", &self.infifo_full())
+            .field("infifo_empty", &self.infifo_empty())
+            .field("infifo_cnt", &self.infifo_cnt())
+            .field("in_remain_under_1b", &self.in_remain_under_1b())
+            .field("in_remain_under_2b", &self.in_remain_under_2b())
+            .field("in_remain_under_3b", &self.in_remain_under_3b())
+            .field("in_remain_under_4b", &self.in_remain_under_4b())
+            .field("in_buf_hungry", &self.in_buf_hungry())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive FIFO status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for INFIFO_STATUS_SPEC {
diff --git a/esp32p4/src/ahb_dma/ch/out_conf0.rs b/esp32p4/src/ahb_dma/ch/out_conf0.rs
index fc2afd771c..2d8b59b735 100644
--- a/esp32p4/src/ahb_dma/ch/out_conf0.rs
+++ b/esp32p4/src/ahb_dma/ch/out_conf0.rs
@@ -71,37 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CONF0")
-            .field("out_rst", &format_args!("{}", self.out_rst().bit()))
-            .field(
-                "out_loop_test",
-                &format_args!("{}", self.out_loop_test().bit()),
-            )
-            .field(
-                "out_auto_wrback",
-                &format_args!("{}", self.out_auto_wrback().bit()),
-            )
-            .field(
-                "out_eof_mode",
-                &format_args!("{}", self.out_eof_mode().bit()),
-            )
-            .field(
-                "outdscr_burst_en",
-                &format_args!("{}", self.outdscr_burst_en().bit()),
-            )
-            .field(
-                "out_data_burst_en",
-                &format_args!("{}", self.out_data_burst_en().bit()),
-            )
-            .field("out_etm_en", &format_args!("{}", self.out_etm_en().bit()))
+            .field("out_rst", &self.out_rst())
+            .field("out_loop_test", &self.out_loop_test())
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("out_eof_mode", &self.out_eof_mode())
+            .field("outdscr_burst_en", &self.outdscr_burst_en())
+            .field("out_data_burst_en", &self.out_data_burst_en())
+            .field("out_etm_en", &self.out_etm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to reset AHB_DMA channel 1 Tx FSM and Tx FIFO pointer."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/ch/out_conf1.rs b/esp32p4/src/ahb_dma/ch/out_conf1.rs
index 8d9753a4b9..0ed936f2fa 100644
--- a/esp32p4/src/ahb_dma/ch/out_conf1.rs
+++ b/esp32p4/src/ahb_dma/ch/out_conf1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CONF1")
-            .field(
-                "out_check_owner",
-                &format_args!("{}", self.out_check_owner().bit()),
-            )
+            .field("out_check_owner", &self.out_check_owner())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/ch/out_dscr.rs b/esp32p4/src/ahb_dma/ch/out_dscr.rs
index bfbfd6cd82..e64e982337 100644
--- a/esp32p4/src/ahb_dma/ch/out_dscr.rs
+++ b/esp32p4/src/ahb_dma/ch/out_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR")
-            .field(
-                "outlink_dscr",
-                &format_args!("{}", self.outlink_dscr().bits()),
-            )
+            .field("outlink_dscr", &self.outlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_SPEC {
diff --git a/esp32p4/src/ahb_dma/ch/out_dscr_bf0.rs b/esp32p4/src/ahb_dma/ch/out_dscr_bf0.rs
index 95ef8f687e..f5fec0ba50 100644
--- a/esp32p4/src/ahb_dma/ch/out_dscr_bf0.rs
+++ b/esp32p4/src/ahb_dma/ch/out_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR_BF0")
-            .field(
-                "outlink_dscr_bf0",
-                &format_args!("{}", self.outlink_dscr_bf0().bits()),
-            )
+            .field("outlink_dscr_bf0", &self.outlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_BF0_SPEC {
diff --git a/esp32p4/src/ahb_dma/ch/out_dscr_bf1.rs b/esp32p4/src/ahb_dma/ch/out_dscr_bf1.rs
index f75439c16c..4339b9c9b9 100644
--- a/esp32p4/src/ahb_dma/ch/out_dscr_bf1.rs
+++ b/esp32p4/src/ahb_dma/ch/out_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR_BF1")
-            .field(
-                "outlink_dscr_bf1",
-                &format_args!("{}", self.outlink_dscr_bf1().bits()),
-            )
+            .field("outlink_dscr_bf1", &self.outlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The second-to-last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_BF1_SPEC {
diff --git a/esp32p4/src/ahb_dma/ch/out_eof_bfr_des_addr.rs b/esp32p4/src/ahb_dma/ch/out_eof_bfr_des_addr.rs
index 32fea6abcc..08cac753ad 100644
--- a/esp32p4/src/ahb_dma/ch/out_eof_bfr_des_addr.rs
+++ b/esp32p4/src/ahb_dma/ch/out_eof_bfr_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_BFR_DES_ADDR")
-            .field(
-                "out_eof_bfr_des_addr",
-                &format_args!("{}", self.out_eof_bfr_des_addr().bits()),
-            )
+            .field("out_eof_bfr_des_addr", &self.out_eof_bfr_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_BFR_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The last outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_bfr_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_BFR_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_SPEC {
diff --git a/esp32p4/src/ahb_dma/ch/out_eof_des_addr.rs b/esp32p4/src/ahb_dma/ch/out_eof_des_addr.rs
index b85ba2ebbd..1049f7aa97 100644
--- a/esp32p4/src/ahb_dma/ch/out_eof_des_addr.rs
+++ b/esp32p4/src/ahb_dma/ch/out_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_DES_ADDR")
-            .field(
-                "out_eof_des_addr",
-                &format_args!("{}", self.out_eof_des_addr().bits()),
-            )
+            .field("out_eof_des_addr", &self.out_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_DES_ADDR_SPEC {
diff --git a/esp32p4/src/ahb_dma/ch/out_link.rs b/esp32p4/src/ahb_dma/ch/out_link.rs
index 37e0ecfb24..aec9817e4b 100644
--- a/esp32p4/src/ahb_dma/ch/out_link.rs
+++ b/esp32p4/src/ahb_dma/ch/out_link.rs
@@ -21,19 +21,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_LINK")
-            .field(
-                "outlink_park",
-                &format_args!("{}", self.outlink_park().bit()),
-            )
+            .field("outlink_park", &self.outlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to stop dealing with the outlink descriptors."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/ch/out_peri_sel.rs b/esp32p4/src/ahb_dma/ch/out_peri_sel.rs
index f58d416089..5984cea290 100644
--- a/esp32p4/src/ahb_dma/ch/out_peri_sel.rs
+++ b/esp32p4/src/ahb_dma/ch/out_peri_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PERI_SEL")
-            .field(
-                "peri_out_sel",
-                &format_args!("{}", self.peri_out_sel().bits()),
-            )
+            .field("peri_out_sel", &self.peri_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PERI_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/ch/out_pri.rs b/esp32p4/src/ahb_dma/ch/out_pri.rs
index 7ea88ef349..5397e69678 100644
--- a/esp32p4/src/ahb_dma/ch/out_pri.rs
+++ b/esp32p4/src/ahb_dma/ch/out_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PRI")
-            .field("tx_pri", &format_args!("{}", self.tx_pri().bits()))
+            .field("tx_pri", &self.tx_pri())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value the higher of the priority."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/ch/out_push.rs b/esp32p4/src/ahb_dma/ch/out_push.rs
index cc01223be4..ea730d399c 100644
--- a/esp32p4/src/ahb_dma/ch/out_push.rs
+++ b/esp32p4/src/ahb_dma/ch/out_push.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PUSH")
-            .field(
-                "outfifo_wdata",
-                &format_args!("{}", self.outfifo_wdata().bits()),
-            )
+            .field("outfifo_wdata", &self.outfifo_wdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PUSH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register stores the data that need to be pushed into AHB_DMA FIFO."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/ch/out_state.rs b/esp32p4/src/ahb_dma/ch/out_state.rs
index 32eb3ca4e8..9711790741 100644
--- a/esp32p4/src/ahb_dma/ch/out_state.rs
+++ b/esp32p4/src/ahb_dma/ch/out_state.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_STATE")
-            .field(
-                "outlink_dscr_addr",
-                &format_args!("{}", self.outlink_dscr_addr().bits()),
-            )
-            .field(
-                "out_dscr_state",
-                &format_args!("{}", self.out_dscr_state().bits()),
-            )
-            .field("out_state", &format_args!("{}", self.out_state().bits()))
+            .field("outlink_dscr_addr", &self.outlink_dscr_addr())
+            .field("out_dscr_state", &self.out_dscr_state())
+            .field("out_state", &self.out_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transmit status of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_STATE_SPEC;
 impl crate::RegisterSpec for OUT_STATE_SPEC {
diff --git a/esp32p4/src/ahb_dma/ch/outfifo_status.rs b/esp32p4/src/ahb_dma/ch/outfifo_status.rs
index 7bdea07321..dc478ff060 100644
--- a/esp32p4/src/ahb_dma/ch/outfifo_status.rs
+++ b/esp32p4/src/ahb_dma/ch/outfifo_status.rs
@@ -55,43 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTFIFO_STATUS")
-            .field(
-                "outfifo_full",
-                &format_args!("{}", self.outfifo_full().bit()),
-            )
-            .field(
-                "outfifo_empty",
-                &format_args!("{}", self.outfifo_empty().bit()),
-            )
-            .field(
-                "outfifo_cnt",
-                &format_args!("{}", self.outfifo_cnt().bits()),
-            )
-            .field(
-                "out_remain_under_1b",
-                &format_args!("{}", self.out_remain_under_1b().bit()),
-            )
-            .field(
-                "out_remain_under_2b",
-                &format_args!("{}", self.out_remain_under_2b().bit()),
-            )
-            .field(
-                "out_remain_under_3b",
-                &format_args!("{}", self.out_remain_under_3b().bit()),
-            )
-            .field(
-                "out_remain_under_4b",
-                &format_args!("{}", self.out_remain_under_4b().bit()),
-            )
+            .field("outfifo_full", &self.outfifo_full())
+            .field("outfifo_empty", &self.outfifo_empty())
+            .field("outfifo_cnt", &self.outfifo_cnt())
+            .field("out_remain_under_1b", &self.out_remain_under_1b())
+            .field("out_remain_under_2b", &self.out_remain_under_2b())
+            .field("out_remain_under_3b", &self.out_remain_under_3b())
+            .field("out_remain_under_4b", &self.out_remain_under_4b())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transmit FIFO status of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for OUTFIFO_STATUS_SPEC {
diff --git a/esp32p4/src/ahb_dma/date.rs b/esp32p4/src/ahb_dma/date.rs
index 9d378d44d9..f4d1611d56 100644
--- a/esp32p4/src/ahb_dma/date.rs
+++ b/esp32p4/src/ahb_dma/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/ahb_dma/in_crc_ch/in_crc_clear.rs b/esp32p4/src/ahb_dma/in_crc_ch/in_crc_clear.rs
index a0487a76ee..0be2381b8e 100644
--- a/esp32p4/src/ahb_dma/in_crc_ch/in_crc_clear.rs
+++ b/esp32p4/src/ahb_dma/in_crc_ch/in_crc_clear.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CRC_CLEAR")
-            .field(
-                "in_crc_clear",
-                &format_args!("{}", self.in_crc_clear().bit()),
-            )
+            .field("in_crc_clear", &self.in_crc_clear())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CRC_CLEAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to clear ch0 of rx crc result"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/in_crc_ch/in_crc_final_result.rs b/esp32p4/src/ahb_dma/in_crc_ch/in_crc_final_result.rs
index 375df4524a..3c091a3b29 100644
--- a/esp32p4/src/ahb_dma/in_crc_ch/in_crc_final_result.rs
+++ b/esp32p4/src/ahb_dma/in_crc_ch/in_crc_final_result.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CRC_FINAL_RESULT")
-            .field(
-                "in_crc_final_result",
-                &format_args!("{}", self.in_crc_final_result().bits()),
-            )
+            .field("in_crc_final_result", &self.in_crc_final_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CRC_FINAL_RESULT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This register is used to store ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_crc_final_result::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_CRC_FINAL_RESULT_SPEC;
 impl crate::RegisterSpec for IN_CRC_FINAL_RESULT_SPEC {
diff --git a/esp32p4/src/ahb_dma/in_crc_ch/in_crc_init_data.rs b/esp32p4/src/ahb_dma/in_crc_ch/in_crc_init_data.rs
index 1540743bd7..09b5b4c69c 100644
--- a/esp32p4/src/ahb_dma/in_crc_ch/in_crc_init_data.rs
+++ b/esp32p4/src/ahb_dma/in_crc_ch/in_crc_init_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CRC_INIT_DATA")
-            .field(
-                "in_crc_init_data",
-                &format_args!("{}", self.in_crc_init_data().bits()),
-            )
+            .field("in_crc_init_data", &self.in_crc_init_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CRC_INIT_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register is used to config ch0 of rx crc initial value"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/in_crc_ch/rx_arb_weigh_opt_dir.rs b/esp32p4/src/ahb_dma/in_crc_ch/rx_arb_weigh_opt_dir.rs
index e5003aac00..b643d66843 100644
--- a/esp32p4/src/ahb_dma/in_crc_ch/rx_arb_weigh_opt_dir.rs
+++ b/esp32p4/src/ahb_dma/in_crc_ch/rx_arb_weigh_opt_dir.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ARB_WEIGH_OPT_DIR")
-            .field(
-                "rx_arb_weigh_opt_dir",
-                &format_args!("{}", self.rx_arb_weigh_opt_dir().bit()),
-            )
+            .field("rx_arb_weigh_opt_dir", &self.rx_arb_weigh_opt_dir())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ARB_WEIGH_OPT_DIR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/in_crc_ch/rx_ch_arb_weigh.rs b/esp32p4/src/ahb_dma/in_crc_ch/rx_ch_arb_weigh.rs
index e3070c7efb..b387bb5e35 100644
--- a/esp32p4/src/ahb_dma/in_crc_ch/rx_ch_arb_weigh.rs
+++ b/esp32p4/src/ahb_dma/in_crc_ch/rx_ch_arb_weigh.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CH_ARB_WEIGH")
-            .field(
-                "rx_ch_arb_weigh",
-                &format_args!("{}", self.rx_ch_arb_weigh().bits()),
-            )
+            .field("rx_ch_arb_weigh", &self.rx_ch_arb_weigh())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CH_ARB_WEIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_data_en_addr.rs b/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_data_en_addr.rs
index 4e760554ba..755c71f93b 100644
--- a/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_data_en_addr.rs
+++ b/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_data_en_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CRC_DATA_EN_ADDR")
-            .field(
-                "rx_crc_data_en_addr",
-                &format_args!("{}", self.rx_crc_data_en_addr().bits()),
-            )
+            .field("rx_crc_data_en_addr", &self.rx_crc_data_en_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CRC_DATA_EN_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_data_en_wr_data.rs b/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_data_en_wr_data.rs
index 43b1ddd644..e9acd7482c 100644
--- a/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_data_en_wr_data.rs
+++ b/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_data_en_wr_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CRC_DATA_EN_WR_DATA")
-            .field(
-                "rx_crc_data_en_wr_data",
-                &format_args!("{}", self.rx_crc_data_en_wr_data().bits()),
-            )
+            .field("rx_crc_data_en_wr_data", &self.rx_crc_data_en_wr_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CRC_DATA_EN_WR_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_en_addr.rs b/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_en_addr.rs
index f558a8976d..f6235ba94b 100644
--- a/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_en_addr.rs
+++ b/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_en_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CRC_EN_ADDR")
-            .field(
-                "rx_crc_en_addr",
-                &format_args!("{}", self.rx_crc_en_addr().bits()),
-            )
+            .field("rx_crc_en_addr", &self.rx_crc_en_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CRC_EN_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_en_wr_data.rs b/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_en_wr_data.rs
index ec1db1b08e..32713eb302 100644
--- a/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_en_wr_data.rs
+++ b/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_en_wr_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CRC_EN_WR_DATA")
-            .field(
-                "rx_crc_en_wr_data",
-                &format_args!("{}", self.rx_crc_en_wr_data().bits()),
-            )
+            .field("rx_crc_en_wr_data", &self.rx_crc_en_wr_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CRC_EN_WR_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register is used to enable rx ch0 crc 32bit on/off"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_width.rs b/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_width.rs
index 9172cc7f28..9d690b0dcf 100644
--- a/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_width.rs
+++ b/esp32p4/src/ahb_dma/in_crc_ch/rx_crc_width.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CRC_WIDTH")
-            .field(
-                "rx_crc_width",
-                &format_args!("{}", self.rx_crc_width().bits()),
-            )
-            .field(
-                "rx_crc_lautch_flga",
-                &format_args!("{}", self.rx_crc_lautch_flga().bit()),
-            )
+            .field("rx_crc_width", &self.rx_crc_width())
+            .field("rx_crc_lautch_flga", &self.rx_crc_lautch_flga())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CRC_WIDTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/in_int_ch/ena.rs b/esp32p4/src/ahb_dma/in_int_ch/ena.rs
index f845f9df75..5dcfe467fd 100644
--- a/esp32p4/src/ahb_dma/in_int_ch/ena.rs
+++ b/esp32p4/src/ahb_dma/in_int_ch/ena.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENA")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/in_int_ch/raw.rs b/esp32p4/src/ahb_dma/in_int_ch/raw.rs
index cbf64a2647..6891a0e659 100644
--- a/esp32p4/src/ahb_dma/in_int_ch/raw.rs
+++ b/esp32p4/src/ahb_dma/in_int_ch/raw.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RAW")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/in_int_ch/st.rs b/esp32p4/src/ahb_dma/in_int_ch/st.rs
index a3bc9f8f8f..0a0bf35524 100644
--- a/esp32p4/src/ahb_dma/in_int_ch/st.rs
+++ b/esp32p4/src/ahb_dma/in_int_ch/st.rs
@@ -55,25 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ST")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ST_SPEC;
 impl crate::RegisterSpec for ST_SPEC {
diff --git a/esp32p4/src/ahb_dma/in_link_addr_ch.rs b/esp32p4/src/ahb_dma/in_link_addr_ch.rs
index 3c66bb0977..794333a22c 100644
--- a/esp32p4/src/ahb_dma/in_link_addr_ch.rs
+++ b/esp32p4/src/ahb_dma/in_link_addr_ch.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_LINK_ADDR_CH")
-            .field(
-                "inlink_addr",
-                &format_args!("{}", self.inlink_addr().bits()),
-            )
+            .field("inlink_addr", &self.inlink_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_LINK_ADDR_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register stores the 32 least significant bits of the first inlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/intr_mem_end_addr.rs b/esp32p4/src/ahb_dma/intr_mem_end_addr.rs
index 424d995f31..2216e0d226 100644
--- a/esp32p4/src/ahb_dma/intr_mem_end_addr.rs
+++ b/esp32p4/src/ahb_dma/intr_mem_end_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_MEM_END_ADDR")
-            .field(
-                "access_intr_mem_end_addr",
-                &format_args!("{}", self.access_intr_mem_end_addr().bits()),
-            )
+            .field("access_intr_mem_end_addr", &self.access_intr_mem_end_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_MEM_END_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/intr_mem_start_addr.rs b/esp32p4/src/ahb_dma/intr_mem_start_addr.rs
index 14423293b3..ba4485c298 100644
--- a/esp32p4/src/ahb_dma/intr_mem_start_addr.rs
+++ b/esp32p4/src/ahb_dma/intr_mem_start_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTR_MEM_START_ADDR")
             .field(
                 "access_intr_mem_start_addr",
-                &format_args!("{}", self.access_intr_mem_start_addr().bits()),
+                &self.access_intr_mem_start_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_MEM_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The start address of accessible address space."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/misc_conf.rs b/esp32p4/src/ahb_dma/misc_conf.rs
index 60bc8667fa..7b16c52f7a 100644
--- a/esp32p4/src/ahb_dma/misc_conf.rs
+++ b/esp32p4/src/ahb_dma/misc_conf.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC_CONF")
-            .field(
-                "ahbm_rst_inter",
-                &format_args!("{}", self.ahbm_rst_inter().bit()),
-            )
-            .field("arb_pri_dis", &format_args!("{}", self.arb_pri_dis().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("ahbm_rst_inter", &self.ahbm_rst_inter())
+            .field("arb_pri_dis", &self.arb_pri_dis())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit then clear this bit to reset the internal ahb FSM."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/out_crc_ch/out_crc_clear.rs b/esp32p4/src/ahb_dma/out_crc_ch/out_crc_clear.rs
index ecddc616e1..855bf8e69e 100644
--- a/esp32p4/src/ahb_dma/out_crc_ch/out_crc_clear.rs
+++ b/esp32p4/src/ahb_dma/out_crc_ch/out_crc_clear.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CRC_CLEAR")
-            .field(
-                "out_crc_clear",
-                &format_args!("{}", self.out_crc_clear().bit()),
-            )
+            .field("out_crc_clear", &self.out_crc_clear())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CRC_CLEAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to clear ch0 of tx crc result"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/out_crc_ch/out_crc_final_result.rs b/esp32p4/src/ahb_dma/out_crc_ch/out_crc_final_result.rs
index fc709f0109..1a6abf53b4 100644
--- a/esp32p4/src/ahb_dma/out_crc_ch/out_crc_final_result.rs
+++ b/esp32p4/src/ahb_dma/out_crc_ch/out_crc_final_result.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CRC_FINAL_RESULT")
-            .field(
-                "out_crc_final_result",
-                &format_args!("{}", self.out_crc_final_result().bits()),
-            )
+            .field("out_crc_final_result", &self.out_crc_final_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CRC_FINAL_RESULT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This register is used to store ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_crc_final_result::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_CRC_FINAL_RESULT_SPEC;
 impl crate::RegisterSpec for OUT_CRC_FINAL_RESULT_SPEC {
diff --git a/esp32p4/src/ahb_dma/out_crc_ch/out_crc_init_data.rs b/esp32p4/src/ahb_dma/out_crc_ch/out_crc_init_data.rs
index 97af8f7438..5e5fd511a6 100644
--- a/esp32p4/src/ahb_dma/out_crc_ch/out_crc_init_data.rs
+++ b/esp32p4/src/ahb_dma/out_crc_ch/out_crc_init_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CRC_INIT_DATA")
-            .field(
-                "out_crc_init_data",
-                &format_args!("{}", self.out_crc_init_data().bits()),
-            )
+            .field("out_crc_init_data", &self.out_crc_init_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CRC_INIT_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register is used to config ch0 of tx crc initial value"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/out_crc_ch/tx_arb_weigh_opt_dir.rs b/esp32p4/src/ahb_dma/out_crc_ch/tx_arb_weigh_opt_dir.rs
index 5a9f146ac5..48f79eb7eb 100644
--- a/esp32p4/src/ahb_dma/out_crc_ch/tx_arb_weigh_opt_dir.rs
+++ b/esp32p4/src/ahb_dma/out_crc_ch/tx_arb_weigh_opt_dir.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_ARB_WEIGH_OPT_DIR")
-            .field(
-                "tx_arb_weigh_opt_dir",
-                &format_args!("{}", self.tx_arb_weigh_opt_dir().bit()),
-            )
+            .field("tx_arb_weigh_opt_dir", &self.tx_arb_weigh_opt_dir())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_ARB_WEIGH_OPT_DIR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/out_crc_ch/tx_ch_arb_weigh.rs b/esp32p4/src/ahb_dma/out_crc_ch/tx_ch_arb_weigh.rs
index 693f1615bd..95d56ba88c 100644
--- a/esp32p4/src/ahb_dma/out_crc_ch/tx_ch_arb_weigh.rs
+++ b/esp32p4/src/ahb_dma/out_crc_ch/tx_ch_arb_weigh.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CH_ARB_WEIGH")
-            .field(
-                "tx_ch_arb_weigh",
-                &format_args!("{}", self.tx_ch_arb_weigh().bits()),
-            )
+            .field("tx_ch_arb_weigh", &self.tx_ch_arb_weigh())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CH_ARB_WEIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_data_en_addr.rs b/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_data_en_addr.rs
index 5357a93754..d0ebd8afc1 100644
--- a/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_data_en_addr.rs
+++ b/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_data_en_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC_DATA_EN_ADDR")
-            .field(
-                "tx_crc_data_en_addr",
-                &format_args!("{}", self.tx_crc_data_en_addr().bits()),
-            )
+            .field("tx_crc_data_en_addr", &self.tx_crc_data_en_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_DATA_EN_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_data_en_wr_data.rs b/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_data_en_wr_data.rs
index 1058a08c39..fd6e0bc506 100644
--- a/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_data_en_wr_data.rs
+++ b/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_data_en_wr_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC_DATA_EN_WR_DATA")
-            .field(
-                "tx_crc_data_en_wr_data",
-                &format_args!("{}", self.tx_crc_data_en_wr_data().bits()),
-            )
+            .field("tx_crc_data_en_wr_data", &self.tx_crc_data_en_wr_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_DATA_EN_WR_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_en_addr.rs b/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_en_addr.rs
index f2e4faa3f8..bb38c3f154 100644
--- a/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_en_addr.rs
+++ b/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_en_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC_EN_ADDR")
-            .field(
-                "tx_crc_en_addr",
-                &format_args!("{}", self.tx_crc_en_addr().bits()),
-            )
+            .field("tx_crc_en_addr", &self.tx_crc_en_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_EN_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_en_wr_data.rs b/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_en_wr_data.rs
index e6a157eac8..fd96e2b5e0 100644
--- a/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_en_wr_data.rs
+++ b/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_en_wr_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC_EN_WR_DATA")
-            .field(
-                "tx_crc_en_wr_data",
-                &format_args!("{}", self.tx_crc_en_wr_data().bits()),
-            )
+            .field("tx_crc_en_wr_data", &self.tx_crc_en_wr_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_EN_WR_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register is used to enable tx ch0 crc 32bit on/off"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_width.rs b/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_width.rs
index d8a319b60a..d1ea8fbd14 100644
--- a/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_width.rs
+++ b/esp32p4/src/ahb_dma/out_crc_ch/tx_crc_width.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC_WIDTH")
-            .field(
-                "tx_crc_width",
-                &format_args!("{}", self.tx_crc_width().bits()),
-            )
-            .field(
-                "tx_crc_lautch_flga",
-                &format_args!("{}", self.tx_crc_lautch_flga().bit()),
-            )
+            .field("tx_crc_width", &self.tx_crc_width())
+            .field("tx_crc_lautch_flga", &self.tx_crc_lautch_flga())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_WIDTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/out_int_ch/ena.rs b/esp32p4/src/ahb_dma/out_int_ch/ena.rs
index 9403656d3a..01a68f37f2 100644
--- a/esp32p4/src/ahb_dma/out_int_ch/ena.rs
+++ b/esp32p4/src/ahb_dma/out_int_ch/ena.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENA")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/out_int_ch/raw.rs b/esp32p4/src/ahb_dma/out_int_ch/raw.rs
index bfd53406bd..f5979fc55a 100644
--- a/esp32p4/src/ahb_dma/out_int_ch/raw.rs
+++ b/esp32p4/src/ahb_dma/out_int_ch/raw.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RAW")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/out_int_ch/st.rs b/esp32p4/src/ahb_dma/out_int_ch/st.rs
index a10e575b53..fff916b01d 100644
--- a/esp32p4/src/ahb_dma/out_int_ch/st.rs
+++ b/esp32p4/src/ahb_dma/out_int_ch/st.rs
@@ -48,27 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ST")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ST_SPEC;
 impl crate::RegisterSpec for ST_SPEC {
diff --git a/esp32p4/src/ahb_dma/out_link_addr_ch.rs b/esp32p4/src/ahb_dma/out_link_addr_ch.rs
index 1cd0552c15..d66c62f9c5 100644
--- a/esp32p4/src/ahb_dma/out_link_addr_ch.rs
+++ b/esp32p4/src/ahb_dma/out_link_addr_ch.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_LINK_ADDR_CH")
-            .field(
-                "outlink_addr",
-                &format_args!("{}", self.outlink_addr().bits()),
-            )
+            .field("outlink_addr", &self.outlink_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_LINK_ADDR_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register stores the 32 least significant bits of the first outlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/weight_en_rx.rs b/esp32p4/src/ahb_dma/weight_en_rx.rs
index a0038fc330..dcce411753 100644
--- a/esp32p4/src/ahb_dma/weight_en_rx.rs
+++ b/esp32p4/src/ahb_dma/weight_en_rx.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WEIGHT_EN_RX")
-            .field(
-                "weight_en_rx",
-                &format_args!("{}", self.weight_en_rx().bit()),
-            )
+            .field("weight_en_rx", &self.weight_en_rx())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WEIGHT_EN_RX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to config arbiter weight function off/on"]
     #[inline(always)]
diff --git a/esp32p4/src/ahb_dma/weight_en_tx.rs b/esp32p4/src/ahb_dma/weight_en_tx.rs
index bdf8e01f45..b186e596ff 100644
--- a/esp32p4/src/ahb_dma/weight_en_tx.rs
+++ b/esp32p4/src/ahb_dma/weight_en_tx.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WEIGHT_EN_TX")
-            .field(
-                "weight_en_tx",
-                &format_args!("{}", self.weight_en_tx().bit()),
-            )
+            .field("weight_en_tx", &self.weight_en_tx())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WEIGHT_EN_TX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to config arbiter weight function off/on"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/clock_gate.rs b/esp32p4/src/assist_debug/clock_gate.rs
index e123579679..743c121add 100644
--- a/esp32p4/src/assist_debug/clock_gate.rs
+++ b/esp32p4/src/assist_debug/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 force on the clock gate"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_0_area_dram0_0_max.rs b/esp32p4/src/assist_debug/core_0_area_dram0_0_max.rs
index 005d6a6db3..9428c7292a 100644
--- a/esp32p4/src/assist_debug/core_0_area_dram0_0_max.rs
+++ b/esp32p4/src/assist_debug/core_0_area_dram0_0_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_0_MAX")
-            .field(
-                "core_0_area_dram0_0_max",
-                &format_args!("{}", self.core_0_area_dram0_0_max().bits()),
-            )
+            .field("core_0_area_dram0_0_max", &self.core_0_area_dram0_0_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_0_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region0 end addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_0_area_dram0_0_min.rs b/esp32p4/src/assist_debug/core_0_area_dram0_0_min.rs
index 82ad82fe11..7bbd0597a1 100644
--- a/esp32p4/src/assist_debug/core_0_area_dram0_0_min.rs
+++ b/esp32p4/src/assist_debug/core_0_area_dram0_0_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_0_MIN")
-            .field(
-                "core_0_area_dram0_0_min",
-                &format_args!("{}", self.core_0_area_dram0_0_min().bits()),
-            )
+            .field("core_0_area_dram0_0_min", &self.core_0_area_dram0_0_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_0_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region0 start addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_0_area_dram0_1_max.rs b/esp32p4/src/assist_debug/core_0_area_dram0_1_max.rs
index 5386b16204..e6dcd4c10a 100644
--- a/esp32p4/src/assist_debug/core_0_area_dram0_1_max.rs
+++ b/esp32p4/src/assist_debug/core_0_area_dram0_1_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_1_MAX")
-            .field(
-                "core_0_area_dram0_1_max",
-                &format_args!("{}", self.core_0_area_dram0_1_max().bits()),
-            )
+            .field("core_0_area_dram0_1_max", &self.core_0_area_dram0_1_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_1_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region1 end addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_0_area_dram0_1_min.rs b/esp32p4/src/assist_debug/core_0_area_dram0_1_min.rs
index a60f37cb77..9a5ba5db20 100644
--- a/esp32p4/src/assist_debug/core_0_area_dram0_1_min.rs
+++ b/esp32p4/src/assist_debug/core_0_area_dram0_1_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_1_MIN")
-            .field(
-                "core_0_area_dram0_1_min",
-                &format_args!("{}", self.core_0_area_dram0_1_min().bits()),
-            )
+            .field("core_0_area_dram0_1_min", &self.core_0_area_dram0_1_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_1_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region1 start addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_0_area_pc.rs b/esp32p4/src/assist_debug/core_0_area_pc.rs
index 41c4d55664..ecc0023648 100644
--- a/esp32p4/src/assist_debug/core_0_area_pc.rs
+++ b/esp32p4/src/assist_debug/core_0_area_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PC")
-            .field(
-                "core_0_area_pc",
-                &format_args!("{}", self.core_0_area_pc().bits()),
-            )
+            .field("core_0_area_pc", &self.core_0_area_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 area pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_AREA_PC_SPEC;
 impl crate::RegisterSpec for CORE_0_AREA_PC_SPEC {
diff --git a/esp32p4/src/assist_debug/core_0_area_pif_0_max.rs b/esp32p4/src/assist_debug/core_0_area_pif_0_max.rs
index 272d2c2274..2f0e9bd13c 100644
--- a/esp32p4/src/assist_debug/core_0_area_pif_0_max.rs
+++ b/esp32p4/src/assist_debug/core_0_area_pif_0_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_0_MAX")
-            .field(
-                "core_0_area_pif_0_max",
-                &format_args!("{}", self.core_0_area_pif_0_max().bits()),
-            )
+            .field("core_0_area_pif_0_max", &self.core_0_area_pif_0_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_0_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region0 end addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_0_area_pif_0_min.rs b/esp32p4/src/assist_debug/core_0_area_pif_0_min.rs
index 6ecf444727..88c0d9e5da 100644
--- a/esp32p4/src/assist_debug/core_0_area_pif_0_min.rs
+++ b/esp32p4/src/assist_debug/core_0_area_pif_0_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_0_MIN")
-            .field(
-                "core_0_area_pif_0_min",
-                &format_args!("{}", self.core_0_area_pif_0_min().bits()),
-            )
+            .field("core_0_area_pif_0_min", &self.core_0_area_pif_0_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_0_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region0 start addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_0_area_pif_1_max.rs b/esp32p4/src/assist_debug/core_0_area_pif_1_max.rs
index 1d79804931..5a00986603 100644
--- a/esp32p4/src/assist_debug/core_0_area_pif_1_max.rs
+++ b/esp32p4/src/assist_debug/core_0_area_pif_1_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_1_MAX")
-            .field(
-                "core_0_area_pif_1_max",
-                &format_args!("{}", self.core_0_area_pif_1_max().bits()),
-            )
+            .field("core_0_area_pif_1_max", &self.core_0_area_pif_1_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_1_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region1 end addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_0_area_pif_1_min.rs b/esp32p4/src/assist_debug/core_0_area_pif_1_min.rs
index 7a20c8326f..d75bae477d 100644
--- a/esp32p4/src/assist_debug/core_0_area_pif_1_min.rs
+++ b/esp32p4/src/assist_debug/core_0_area_pif_1_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_1_MIN")
-            .field(
-                "core_0_area_pif_1_min",
-                &format_args!("{}", self.core_0_area_pif_1_min().bits()),
-            )
+            .field("core_0_area_pif_1_min", &self.core_0_area_pif_1_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_1_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region1 start addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_0_area_sp.rs b/esp32p4/src/assist_debug/core_0_area_sp.rs
index 7f80b9076b..f325b5fbe5 100644
--- a/esp32p4/src/assist_debug/core_0_area_sp.rs
+++ b/esp32p4/src/assist_debug/core_0_area_sp.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_SP")
-            .field(
-                "core_0_area_sp",
-                &format_args!("{}", self.core_0_area_sp().bits()),
-            )
+            .field("core_0_area_sp", &self.core_0_area_sp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_SP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 area sp status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_sp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_AREA_SP_SPEC;
 impl crate::RegisterSpec for CORE_0_AREA_SP_SPEC {
diff --git a/esp32p4/src/assist_debug/core_0_debug_mode.rs b/esp32p4/src/assist_debug/core_0_debug_mode.rs
index 7936884e12..3c11aaa92f 100644
--- a/esp32p4/src/assist_debug/core_0_debug_mode.rs
+++ b/esp32p4/src/assist_debug/core_0_debug_mode.rs
@@ -20,23 +20,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_DEBUG_MODE")
-            .field(
-                "core_0_debug_mode",
-                &format_args!("{}", self.core_0_debug_mode().bit()),
-            )
+            .field("core_0_debug_mode", &self.core_0_debug_mode())
             .field(
                 "core_0_debug_module_active",
-                &format_args!("{}", self.core_0_debug_module_active().bit()),
+                &self.core_0_debug_module_active(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DEBUG_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_debug_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DEBUG_MODE_SPEC;
 impl crate::RegisterSpec for CORE_0_DEBUG_MODE_SPEC {
diff --git a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_0.rs b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_0.rs
index c4e543328b..5018ae2fb8 100644
--- a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_0.rs
+++ b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_0.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_0_dram0_recording_wr_0",
-                &format_args!("{}", self.core_0_dram0_recording_wr_0().bit()),
+                &self.core_0_dram0_recording_wr_0(),
             )
             .field(
                 "core_0_dram0_recording_byteen_0",
-                &format_args!("{}", self.core_0_dram0_recording_byteen_0().bits()),
+                &self.core_0_dram0_recording_byteen_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC {
diff --git a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_1.rs b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_1.rs
index 8f71672b1b..561c4c5d93 100644
--- a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_1.rs
+++ b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_0_dram0_recording_addr_0",
-                &format_args!("{}", self.core_0_dram0_recording_addr_0().bits()),
+                &self.core_0_dram0_recording_addr_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC {
diff --git a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_2.rs b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_2.rs
index 03d42d806d..47d6008022 100644
--- a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_2.rs
+++ b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_2")
             .field(
                 "core_0_dram0_recording_pc_0",
-                &format_args!("{}", self.core_0_dram0_recording_pc_0().bits()),
+                &self.core_0_dram0_recording_pc_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC {
diff --git a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_3.rs b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_3.rs
index e599ae37c3..8b4e3b9767 100644
--- a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_3.rs
+++ b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_3.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_3")
             .field(
                 "core_0_dram0_recording_wr_1",
-                &format_args!("{}", self.core_0_dram0_recording_wr_1().bit()),
+                &self.core_0_dram0_recording_wr_1(),
             )
             .field(
                 "core_0_dram0_recording_byteen_1",
-                &format_args!("{}", self.core_0_dram0_recording_byteen_1().bits()),
+                &self.core_0_dram0_recording_byteen_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC {
diff --git a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_4.rs b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_4.rs
index f9ae397b0e..621f86dba5 100644
--- a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_4.rs
+++ b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_4")
             .field(
                 "core_0_dram0_recording_addr_1",
-                &format_args!("{}", self.core_0_dram0_recording_addr_1().bits()),
+                &self.core_0_dram0_recording_addr_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC {
diff --git a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_5.rs b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_5.rs
index 2ae50bfdcb..0999f55b52 100644
--- a/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_5.rs
+++ b/esp32p4/src/assist_debug/core_0_dram0_exception_monitor_5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_5")
             .field(
                 "core_0_dram0_recording_pc_1",
-                &format_args!("{}", self.core_0_dram0_recording_pc_1().bits()),
+                &self.core_0_dram0_recording_pc_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC {
diff --git a/esp32p4/src/assist_debug/core_0_intr_ena.rs b/esp32p4/src/assist_debug/core_0_intr_ena.rs
index 6873cfa7c9..298f50326d 100644
--- a/esp32p4/src/assist_debug/core_0_intr_ena.rs
+++ b/esp32p4/src/assist_debug/core_0_intr_ena.rs
@@ -118,61 +118,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_INTR_ENA")
             .field(
                 "core_0_area_dram0_0_rd_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_ena().bit()),
+                &self.core_0_area_dram0_0_rd_ena(),
             )
             .field(
                 "core_0_area_dram0_0_wr_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_ena().bit()),
+                &self.core_0_area_dram0_0_wr_ena(),
             )
             .field(
                 "core_0_area_dram0_1_rd_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_ena().bit()),
+                &self.core_0_area_dram0_1_rd_ena(),
             )
             .field(
                 "core_0_area_dram0_1_wr_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_rd_ena",
-                &format_args!("{}", self.core_0_area_pif_0_rd_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_wr_ena",
-                &format_args!("{}", self.core_0_area_pif_0_wr_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_rd_ena",
-                &format_args!("{}", self.core_0_area_pif_1_rd_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_wr_ena",
-                &format_args!("{}", self.core_0_area_pif_1_wr_ena().bit()),
-            )
-            .field(
-                "core_0_sp_spill_min_ena",
-                &format_args!("{}", self.core_0_sp_spill_min_ena().bit()),
-            )
-            .field(
-                "core_0_sp_spill_max_ena",
-                &format_args!("{}", self.core_0_sp_spill_max_ena().bit()),
+                &self.core_0_area_dram0_1_wr_ena(),
             )
+            .field("core_0_area_pif_0_rd_ena", &self.core_0_area_pif_0_rd_ena())
+            .field("core_0_area_pif_0_wr_ena", &self.core_0_area_pif_0_wr_ena())
+            .field("core_0_area_pif_1_rd_ena", &self.core_0_area_pif_1_rd_ena())
+            .field("core_0_area_pif_1_wr_ena", &self.core_0_area_pif_1_wr_ena())
+            .field("core_0_sp_spill_min_ena", &self.core_0_sp_spill_min_ena())
+            .field("core_0_sp_spill_max_ena", &self.core_0_sp_spill_max_ena())
             .field(
                 "core_0_iram0_exception_monitor_ena",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_ena().bit()),
+                &self.core_0_iram0_exception_monitor_ena(),
             )
             .field(
                 "core_0_dram0_exception_monitor_ena",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_ena().bit()),
+                &self.core_0_dram0_exception_monitor_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_INTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core0 dram0 area0 read monitor enable"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_0_intr_raw.rs b/esp32p4/src/assist_debug/core_0_intr_raw.rs
index 4ae15ba38c..1d30267746 100644
--- a/esp32p4/src/assist_debug/core_0_intr_raw.rs
+++ b/esp32p4/src/assist_debug/core_0_intr_raw.rs
@@ -92,61 +92,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_INTR_RAW")
             .field(
                 "core_0_area_dram0_0_rd_raw",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_raw().bit()),
+                &self.core_0_area_dram0_0_rd_raw(),
             )
             .field(
                 "core_0_area_dram0_0_wr_raw",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_raw().bit()),
+                &self.core_0_area_dram0_0_wr_raw(),
             )
             .field(
                 "core_0_area_dram0_1_rd_raw",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_raw().bit()),
+                &self.core_0_area_dram0_1_rd_raw(),
             )
             .field(
                 "core_0_area_dram0_1_wr_raw",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_rd_raw",
-                &format_args!("{}", self.core_0_area_pif_0_rd_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_wr_raw",
-                &format_args!("{}", self.core_0_area_pif_0_wr_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_rd_raw",
-                &format_args!("{}", self.core_0_area_pif_1_rd_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_wr_raw",
-                &format_args!("{}", self.core_0_area_pif_1_wr_raw().bit()),
-            )
-            .field(
-                "core_0_sp_spill_min_raw",
-                &format_args!("{}", self.core_0_sp_spill_min_raw().bit()),
-            )
-            .field(
-                "core_0_sp_spill_max_raw",
-                &format_args!("{}", self.core_0_sp_spill_max_raw().bit()),
+                &self.core_0_area_dram0_1_wr_raw(),
             )
+            .field("core_0_area_pif_0_rd_raw", &self.core_0_area_pif_0_rd_raw())
+            .field("core_0_area_pif_0_wr_raw", &self.core_0_area_pif_0_wr_raw())
+            .field("core_0_area_pif_1_rd_raw", &self.core_0_area_pif_1_rd_raw())
+            .field("core_0_area_pif_1_wr_raw", &self.core_0_area_pif_1_wr_raw())
+            .field("core_0_sp_spill_min_raw", &self.core_0_sp_spill_min_raw())
+            .field("core_0_sp_spill_max_raw", &self.core_0_sp_spill_max_raw())
             .field(
                 "core_0_iram0_exception_monitor_raw",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_raw().bit()),
+                &self.core_0_iram0_exception_monitor_raw(),
             )
             .field(
                 "core_0_dram0_exception_monitor_raw",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_raw().bit()),
+                &self.core_0_dram0_exception_monitor_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_INTR_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 monitor interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_intr_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_INTR_RAW_SPEC;
 impl crate::RegisterSpec for CORE_0_INTR_RAW_SPEC {
diff --git a/esp32p4/src/assist_debug/core_0_intr_rls.rs b/esp32p4/src/assist_debug/core_0_intr_rls.rs
index 6fd78e55f0..39aca1f688 100644
--- a/esp32p4/src/assist_debug/core_0_intr_rls.rs
+++ b/esp32p4/src/assist_debug/core_0_intr_rls.rs
@@ -118,61 +118,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_INTR_RLS")
             .field(
                 "core_0_area_dram0_0_rd_rls",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_rls().bit()),
+                &self.core_0_area_dram0_0_rd_rls(),
             )
             .field(
                 "core_0_area_dram0_0_wr_rls",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_rls().bit()),
+                &self.core_0_area_dram0_0_wr_rls(),
             )
             .field(
                 "core_0_area_dram0_1_rd_rls",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_rls().bit()),
+                &self.core_0_area_dram0_1_rd_rls(),
             )
             .field(
                 "core_0_area_dram0_1_wr_rls",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_rls().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_rd_rls",
-                &format_args!("{}", self.core_0_area_pif_0_rd_rls().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_wr_rls",
-                &format_args!("{}", self.core_0_area_pif_0_wr_rls().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_rd_rls",
-                &format_args!("{}", self.core_0_area_pif_1_rd_rls().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_wr_rls",
-                &format_args!("{}", self.core_0_area_pif_1_wr_rls().bit()),
-            )
-            .field(
-                "core_0_sp_spill_min_rls",
-                &format_args!("{}", self.core_0_sp_spill_min_rls().bit()),
-            )
-            .field(
-                "core_0_sp_spill_max_rls",
-                &format_args!("{}", self.core_0_sp_spill_max_rls().bit()),
+                &self.core_0_area_dram0_1_wr_rls(),
             )
+            .field("core_0_area_pif_0_rd_rls", &self.core_0_area_pif_0_rd_rls())
+            .field("core_0_area_pif_0_wr_rls", &self.core_0_area_pif_0_wr_rls())
+            .field("core_0_area_pif_1_rd_rls", &self.core_0_area_pif_1_rd_rls())
+            .field("core_0_area_pif_1_wr_rls", &self.core_0_area_pif_1_wr_rls())
+            .field("core_0_sp_spill_min_rls", &self.core_0_sp_spill_min_rls())
+            .field("core_0_sp_spill_max_rls", &self.core_0_sp_spill_max_rls())
             .field(
                 "core_0_iram0_exception_monitor_rls",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_rls().bit()),
+                &self.core_0_iram0_exception_monitor_rls(),
             )
             .field(
                 "core_0_dram0_exception_monitor_rls",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_rls().bit()),
+                &self.core_0_dram0_exception_monitor_rls(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_INTR_RLS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt enable"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_0_iram0_exception_monitor_0.rs b/esp32p4/src/assist_debug/core_0_iram0_exception_monitor_0.rs
index 5a4ee4189b..b653f3207f 100644
--- a/esp32p4/src/assist_debug/core_0_iram0_exception_monitor_0.rs
+++ b/esp32p4/src/assist_debug/core_0_iram0_exception_monitor_0.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_0_iram0_recording_addr_0",
-                &format_args!("{}", self.core_0_iram0_recording_addr_0().bits()),
+                &self.core_0_iram0_recording_addr_0(),
             )
             .field(
                 "core_0_iram0_recording_wr_0",
-                &format_args!("{}", self.core_0_iram0_recording_wr_0().bit()),
+                &self.core_0_iram0_recording_wr_0(),
             )
             .field(
                 "core_0_iram0_recording_loadstore_0",
-                &format_args!("{}", self.core_0_iram0_recording_loadstore_0().bit()),
+                &self.core_0_iram0_recording_loadstore_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_exception_monitor_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC;
 impl crate::RegisterSpec for CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC {
diff --git a/esp32p4/src/assist_debug/core_0_iram0_exception_monitor_1.rs b/esp32p4/src/assist_debug/core_0_iram0_exception_monitor_1.rs
index 6fef16c53f..015b3f1b8e 100644
--- a/esp32p4/src/assist_debug/core_0_iram0_exception_monitor_1.rs
+++ b/esp32p4/src/assist_debug/core_0_iram0_exception_monitor_1.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_0_iram0_recording_addr_1",
-                &format_args!("{}", self.core_0_iram0_recording_addr_1().bits()),
+                &self.core_0_iram0_recording_addr_1(),
             )
             .field(
                 "core_0_iram0_recording_wr_1",
-                &format_args!("{}", self.core_0_iram0_recording_wr_1().bit()),
+                &self.core_0_iram0_recording_wr_1(),
             )
             .field(
                 "core_0_iram0_recording_loadstore_1",
-                &format_args!("{}", self.core_0_iram0_recording_loadstore_1().bit()),
+                &self.core_0_iram0_recording_loadstore_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_exception_monitor_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC;
 impl crate::RegisterSpec for CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC {
diff --git a/esp32p4/src/assist_debug/core_0_lastpc_before_exception.rs b/esp32p4/src/assist_debug/core_0_lastpc_before_exception.rs
index c785394f03..7e8b529461 100644
--- a/esp32p4/src/assist_debug/core_0_lastpc_before_exception.rs
+++ b/esp32p4/src/assist_debug/core_0_lastpc_before_exception.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_LASTPC_BEFORE_EXCEPTION")
-            .field(
-                "core_0_lastpc_before_exc",
-                &format_args!("{}", self.core_0_lastpc_before_exc().bits()),
-            )
+            .field("core_0_lastpc_before_exc", &self.core_0_lastpc_before_exc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_LASTPC_BEFORE_EXCEPTION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_lastpc_before_exception::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_LASTPC_BEFORE_EXCEPTION_SPEC;
 impl crate::RegisterSpec for CORE_0_LASTPC_BEFORE_EXCEPTION_SPEC {
diff --git a/esp32p4/src/assist_debug/core_0_rcd_en.rs b/esp32p4/src/assist_debug/core_0_rcd_en.rs
index c32ca92cbc..8a365dc63d 100644
--- a/esp32p4/src/assist_debug/core_0_rcd_en.rs
+++ b/esp32p4/src/assist_debug/core_0_rcd_en.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_EN")
-            .field(
-                "core_0_rcd_recorden",
-                &format_args!("{}", self.core_0_rcd_recorden().bit()),
-            )
-            .field(
-                "core_0_rcd_pdebugen",
-                &format_args!("{}", self.core_0_rcd_pdebugen().bit()),
-            )
+            .field("core_0_rcd_recorden", &self.core_0_rcd_recorden())
+            .field("core_0_rcd_pdebugen", &self.core_0_rcd_pdebugen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable record PC"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_0_rcd_pdebugpc.rs b/esp32p4/src/assist_debug/core_0_rcd_pdebugpc.rs
index 57525f3096..f683fc645a 100644
--- a/esp32p4/src/assist_debug/core_0_rcd_pdebugpc.rs
+++ b/esp32p4/src/assist_debug/core_0_rcd_pdebugpc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGPC")
-            .field(
-                "core_0_rcd_pdebugpc",
-                &format_args!("{}", self.core_0_rcd_pdebugpc().bits()),
-            )
+            .field("core_0_rcd_pdebugpc", &self.core_0_rcd_pdebugpc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGPC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugpc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGPC_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGPC_SPEC {
diff --git a/esp32p4/src/assist_debug/core_0_rcd_pdebugsp.rs b/esp32p4/src/assist_debug/core_0_rcd_pdebugsp.rs
index 5299a97c98..acd394b30c 100644
--- a/esp32p4/src/assist_debug/core_0_rcd_pdebugsp.rs
+++ b/esp32p4/src/assist_debug/core_0_rcd_pdebugsp.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGSP")
-            .field(
-                "core_0_rcd_pdebugsp",
-                &format_args!("{}", self.core_0_rcd_pdebugsp().bits()),
-            )
+            .field("core_0_rcd_pdebugsp", &self.core_0_rcd_pdebugsp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGSP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugsp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGSP_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGSP_SPEC {
diff --git a/esp32p4/src/assist_debug/core_0_sp_max.rs b/esp32p4/src/assist_debug/core_0_sp_max.rs
index 551ad6e6e3..33cb4259d1 100644
--- a/esp32p4/src/assist_debug/core_0_sp_max.rs
+++ b/esp32p4/src/assist_debug/core_0_sp_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_MAX")
-            .field(
-                "core_0_sp_max",
-                &format_args!("{}", self.core_0_sp_max().bits()),
-            )
+            .field("core_0_sp_max", &self.core_0_sp_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - core0 sp pc status register"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_0_sp_min.rs b/esp32p4/src/assist_debug/core_0_sp_min.rs
index 385b8a1a99..5ab4adde01 100644
--- a/esp32p4/src/assist_debug/core_0_sp_min.rs
+++ b/esp32p4/src/assist_debug/core_0_sp_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_MIN")
-            .field(
-                "core_0_sp_min",
-                &format_args!("{}", self.core_0_sp_min().bits()),
-            )
+            .field("core_0_sp_min", &self.core_0_sp_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - core0 sp region configuration regsiter"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_0_sp_pc.rs b/esp32p4/src/assist_debug/core_0_sp_pc.rs
index edb35da31e..a876b3c942 100644
--- a/esp32p4/src/assist_debug/core_0_sp_pc.rs
+++ b/esp32p4/src/assist_debug/core_0_sp_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_PC")
-            .field(
-                "core_0_sp_pc",
-                &format_args!("{}", self.core_0_sp_pc().bits()),
-            )
+            .field("core_0_sp_pc", &self.core_0_sp_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "stack monitor pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_sp_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_SP_PC_SPEC;
 impl crate::RegisterSpec for CORE_0_SP_PC_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_area_dram0_0_max.rs b/esp32p4/src/assist_debug/core_1_area_dram0_0_max.rs
index e9c64197db..104d743183 100644
--- a/esp32p4/src/assist_debug/core_1_area_dram0_0_max.rs
+++ b/esp32p4/src/assist_debug/core_1_area_dram0_0_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_DRAM0_0_MAX")
-            .field(
-                "core_1_area_dram0_0_max",
-                &format_args!("{}", self.core_1_area_dram0_0_max().bits()),
-            )
+            .field("core_1_area_dram0_0_max", &self.core_1_area_dram0_0_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_DRAM0_0_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 dram0 region0 end addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_1_area_dram0_0_min.rs b/esp32p4/src/assist_debug/core_1_area_dram0_0_min.rs
index bd01e36c36..b90c92ba3a 100644
--- a/esp32p4/src/assist_debug/core_1_area_dram0_0_min.rs
+++ b/esp32p4/src/assist_debug/core_1_area_dram0_0_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_DRAM0_0_MIN")
-            .field(
-                "core_1_area_dram0_0_min",
-                &format_args!("{}", self.core_1_area_dram0_0_min().bits()),
-            )
+            .field("core_1_area_dram0_0_min", &self.core_1_area_dram0_0_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_DRAM0_0_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 dram0 region0 start addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_1_area_dram0_1_max.rs b/esp32p4/src/assist_debug/core_1_area_dram0_1_max.rs
index 3ea4673981..da18d724d7 100644
--- a/esp32p4/src/assist_debug/core_1_area_dram0_1_max.rs
+++ b/esp32p4/src/assist_debug/core_1_area_dram0_1_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_DRAM0_1_MAX")
-            .field(
-                "core_1_area_dram0_1_max",
-                &format_args!("{}", self.core_1_area_dram0_1_max().bits()),
-            )
+            .field("core_1_area_dram0_1_max", &self.core_1_area_dram0_1_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_DRAM0_1_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 dram0 region1 end addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_1_area_dram0_1_min.rs b/esp32p4/src/assist_debug/core_1_area_dram0_1_min.rs
index 545e98aa11..792d71025c 100644
--- a/esp32p4/src/assist_debug/core_1_area_dram0_1_min.rs
+++ b/esp32p4/src/assist_debug/core_1_area_dram0_1_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_DRAM0_1_MIN")
-            .field(
-                "core_1_area_dram0_1_min",
-                &format_args!("{}", self.core_1_area_dram0_1_min().bits()),
-            )
+            .field("core_1_area_dram0_1_min", &self.core_1_area_dram0_1_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_DRAM0_1_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 dram0 region1 start addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_1_area_pc.rs b/esp32p4/src/assist_debug/core_1_area_pc.rs
index 96ca14baf5..0b8dc822a3 100644
--- a/esp32p4/src/assist_debug/core_1_area_pc.rs
+++ b/esp32p4/src/assist_debug/core_1_area_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_PC")
-            .field(
-                "core_1_area_pc",
-                &format_args!("{}", self.core_1_area_pc().bits()),
-            )
+            .field("core_1_area_pc", &self.core_1_area_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core1 area pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_AREA_PC_SPEC;
 impl crate::RegisterSpec for CORE_1_AREA_PC_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_area_pif_0_max.rs b/esp32p4/src/assist_debug/core_1_area_pif_0_max.rs
index 0bbc8b942b..2cb17687d4 100644
--- a/esp32p4/src/assist_debug/core_1_area_pif_0_max.rs
+++ b/esp32p4/src/assist_debug/core_1_area_pif_0_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_PIF_0_MAX")
-            .field(
-                "core_1_area_pif_0_max",
-                &format_args!("{}", self.core_1_area_pif_0_max().bits()),
-            )
+            .field("core_1_area_pif_0_max", &self.core_1_area_pif_0_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_PIF_0_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 PIF region0 end addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_1_area_pif_0_min.rs b/esp32p4/src/assist_debug/core_1_area_pif_0_min.rs
index 929aba9c5b..5bcfb46d16 100644
--- a/esp32p4/src/assist_debug/core_1_area_pif_0_min.rs
+++ b/esp32p4/src/assist_debug/core_1_area_pif_0_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_PIF_0_MIN")
-            .field(
-                "core_1_area_pif_0_min",
-                &format_args!("{}", self.core_1_area_pif_0_min().bits()),
-            )
+            .field("core_1_area_pif_0_min", &self.core_1_area_pif_0_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_PIF_0_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 PIF region0 start addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_1_area_pif_1_max.rs b/esp32p4/src/assist_debug/core_1_area_pif_1_max.rs
index 510c0162eb..350684da60 100644
--- a/esp32p4/src/assist_debug/core_1_area_pif_1_max.rs
+++ b/esp32p4/src/assist_debug/core_1_area_pif_1_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_PIF_1_MAX")
-            .field(
-                "core_1_area_pif_1_max",
-                &format_args!("{}", self.core_1_area_pif_1_max().bits()),
-            )
+            .field("core_1_area_pif_1_max", &self.core_1_area_pif_1_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_PIF_1_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 PIF region1 end addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_1_area_pif_1_min.rs b/esp32p4/src/assist_debug/core_1_area_pif_1_min.rs
index c7ac3d5d90..ab1f56d18b 100644
--- a/esp32p4/src/assist_debug/core_1_area_pif_1_min.rs
+++ b/esp32p4/src/assist_debug/core_1_area_pif_1_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_PIF_1_MIN")
-            .field(
-                "core_1_area_pif_1_min",
-                &format_args!("{}", self.core_1_area_pif_1_min().bits()),
-            )
+            .field("core_1_area_pif_1_min", &self.core_1_area_pif_1_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_PIF_1_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 PIF region1 start addr"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_1_area_sp.rs b/esp32p4/src/assist_debug/core_1_area_sp.rs
index 14931f854f..32b47365dd 100644
--- a/esp32p4/src/assist_debug/core_1_area_sp.rs
+++ b/esp32p4/src/assist_debug/core_1_area_sp.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_SP")
-            .field(
-                "core_1_area_sp",
-                &format_args!("{}", self.core_1_area_sp().bits()),
-            )
+            .field("core_1_area_sp", &self.core_1_area_sp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_SP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core1 area sp status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_sp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_AREA_SP_SPEC;
 impl crate::RegisterSpec for CORE_1_AREA_SP_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_debug_mode.rs b/esp32p4/src/assist_debug/core_1_debug_mode.rs
index 2b9685693c..0b2027aad6 100644
--- a/esp32p4/src/assist_debug/core_1_debug_mode.rs
+++ b/esp32p4/src/assist_debug/core_1_debug_mode.rs
@@ -20,23 +20,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_DEBUG_MODE")
-            .field(
-                "core_1_debug_mode",
-                &format_args!("{}", self.core_1_debug_mode().bit()),
-            )
+            .field("core_1_debug_mode", &self.core_1_debug_mode())
             .field(
                 "core_1_debug_module_active",
-                &format_args!("{}", self.core_1_debug_module_active().bit()),
+                &self.core_1_debug_module_active(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DEBUG_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_debug_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_DEBUG_MODE_SPEC;
 impl crate::RegisterSpec for CORE_1_DEBUG_MODE_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_0.rs b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_0.rs
index 8749118382..ca20e42508 100644
--- a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_0.rs
+++ b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_0.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_1_dram0_recording_wr_0",
-                &format_args!("{}", self.core_1_dram0_recording_wr_0().bit()),
+                &self.core_1_dram0_recording_wr_0(),
             )
             .field(
                 "core_1_dram0_recording_byteen_0",
-                &format_args!("{}", self.core_1_dram0_recording_byteen_0().bits()),
+                &self.core_1_dram0_recording_byteen_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC;
 impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_1.rs b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_1.rs
index 419ef0cb7f..b5d6c262a3 100644
--- a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_1.rs
+++ b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_1_dram0_recording_addr_0",
-                &format_args!("{}", self.core_1_dram0_recording_addr_0().bits()),
+                &self.core_1_dram0_recording_addr_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC;
 impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_2.rs b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_2.rs
index 1058036ef2..f24b050159 100644
--- a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_2.rs
+++ b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_2")
             .field(
                 "core_1_dram0_recording_pc_0",
-                &format_args!("{}", self.core_1_dram0_recording_pc_0().bits()),
+                &self.core_1_dram0_recording_pc_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_3.rs b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_3.rs
index be5441e656..f31c187003 100644
--- a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_3.rs
+++ b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_3.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_3")
             .field(
                 "core_1_dram0_recording_wr_1",
-                &format_args!("{}", self.core_1_dram0_recording_wr_1().bit()),
+                &self.core_1_dram0_recording_wr_1(),
             )
             .field(
                 "core_1_dram0_recording_byteen_1",
-                &format_args!("{}", self.core_1_dram0_recording_byteen_1().bits()),
+                &self.core_1_dram0_recording_byteen_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC;
 impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_4.rs b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_4.rs
index 496d4e5631..e8adff61c9 100644
--- a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_4.rs
+++ b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_4")
             .field(
                 "core_1_dram0_recording_addr_1",
-                &format_args!("{}", self.core_1_dram0_recording_addr_1().bits()),
+                &self.core_1_dram0_recording_addr_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC;
 impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_5.rs b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_5.rs
index 1c79b0be7a..373afdd323 100644
--- a/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_5.rs
+++ b/esp32p4/src/assist_debug/core_1_dram0_exception_monitor_5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_5")
             .field(
                 "core_1_dram0_recording_pc_1",
-                &format_args!("{}", self.core_1_dram0_recording_pc_1().bits()),
+                &self.core_1_dram0_recording_pc_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC;
 impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_intr_ena.rs b/esp32p4/src/assist_debug/core_1_intr_ena.rs
index 3e2109a3d3..0902285f45 100644
--- a/esp32p4/src/assist_debug/core_1_intr_ena.rs
+++ b/esp32p4/src/assist_debug/core_1_intr_ena.rs
@@ -118,61 +118,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_INTR_ENA")
             .field(
                 "core_1_area_dram0_0_rd_ena",
-                &format_args!("{}", self.core_1_area_dram0_0_rd_ena().bit()),
+                &self.core_1_area_dram0_0_rd_ena(),
             )
             .field(
                 "core_1_area_dram0_0_wr_ena",
-                &format_args!("{}", self.core_1_area_dram0_0_wr_ena().bit()),
+                &self.core_1_area_dram0_0_wr_ena(),
             )
             .field(
                 "core_1_area_dram0_1_rd_ena",
-                &format_args!("{}", self.core_1_area_dram0_1_rd_ena().bit()),
+                &self.core_1_area_dram0_1_rd_ena(),
             )
             .field(
                 "core_1_area_dram0_1_wr_ena",
-                &format_args!("{}", self.core_1_area_dram0_1_wr_ena().bit()),
-            )
-            .field(
-                "core_1_area_pif_0_rd_ena",
-                &format_args!("{}", self.core_1_area_pif_0_rd_ena().bit()),
-            )
-            .field(
-                "core_1_area_pif_0_wr_ena",
-                &format_args!("{}", self.core_1_area_pif_0_wr_ena().bit()),
-            )
-            .field(
-                "core_1_area_pif_1_rd_ena",
-                &format_args!("{}", self.core_1_area_pif_1_rd_ena().bit()),
-            )
-            .field(
-                "core_1_area_pif_1_wr_ena",
-                &format_args!("{}", self.core_1_area_pif_1_wr_ena().bit()),
-            )
-            .field(
-                "core_1_sp_spill_min_ena",
-                &format_args!("{}", self.core_1_sp_spill_min_ena().bit()),
-            )
-            .field(
-                "core_1_sp_spill_max_ena",
-                &format_args!("{}", self.core_1_sp_spill_max_ena().bit()),
+                &self.core_1_area_dram0_1_wr_ena(),
             )
+            .field("core_1_area_pif_0_rd_ena", &self.core_1_area_pif_0_rd_ena())
+            .field("core_1_area_pif_0_wr_ena", &self.core_1_area_pif_0_wr_ena())
+            .field("core_1_area_pif_1_rd_ena", &self.core_1_area_pif_1_rd_ena())
+            .field("core_1_area_pif_1_wr_ena", &self.core_1_area_pif_1_wr_ena())
+            .field("core_1_sp_spill_min_ena", &self.core_1_sp_spill_min_ena())
+            .field("core_1_sp_spill_max_ena", &self.core_1_sp_spill_max_ena())
             .field(
                 "core_1_iram0_exception_monitor_ena",
-                &format_args!("{}", self.core_1_iram0_exception_monitor_ena().bit()),
+                &self.core_1_iram0_exception_monitor_ena(),
             )
             .field(
                 "core_1_dram0_exception_monitor_ena",
-                &format_args!("{}", self.core_1_dram0_exception_monitor_ena().bit()),
+                &self.core_1_dram0_exception_monitor_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_INTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core1 dram0 area0 read monitor enable"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_1_intr_raw.rs b/esp32p4/src/assist_debug/core_1_intr_raw.rs
index 5486c68162..f5c787e520 100644
--- a/esp32p4/src/assist_debug/core_1_intr_raw.rs
+++ b/esp32p4/src/assist_debug/core_1_intr_raw.rs
@@ -92,61 +92,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_INTR_RAW")
             .field(
                 "core_1_area_dram0_0_rd_raw",
-                &format_args!("{}", self.core_1_area_dram0_0_rd_raw().bit()),
+                &self.core_1_area_dram0_0_rd_raw(),
             )
             .field(
                 "core_1_area_dram0_0_wr_raw",
-                &format_args!("{}", self.core_1_area_dram0_0_wr_raw().bit()),
+                &self.core_1_area_dram0_0_wr_raw(),
             )
             .field(
                 "core_1_area_dram0_1_rd_raw",
-                &format_args!("{}", self.core_1_area_dram0_1_rd_raw().bit()),
+                &self.core_1_area_dram0_1_rd_raw(),
             )
             .field(
                 "core_1_area_dram0_1_wr_raw",
-                &format_args!("{}", self.core_1_area_dram0_1_wr_raw().bit()),
-            )
-            .field(
-                "core_1_area_pif_0_rd_raw",
-                &format_args!("{}", self.core_1_area_pif_0_rd_raw().bit()),
-            )
-            .field(
-                "core_1_area_pif_0_wr_raw",
-                &format_args!("{}", self.core_1_area_pif_0_wr_raw().bit()),
-            )
-            .field(
-                "core_1_area_pif_1_rd_raw",
-                &format_args!("{}", self.core_1_area_pif_1_rd_raw().bit()),
-            )
-            .field(
-                "core_1_area_pif_1_wr_raw",
-                &format_args!("{}", self.core_1_area_pif_1_wr_raw().bit()),
-            )
-            .field(
-                "core_1_sp_spill_min_raw",
-                &format_args!("{}", self.core_1_sp_spill_min_raw().bit()),
-            )
-            .field(
-                "core_1_sp_spill_max_raw",
-                &format_args!("{}", self.core_1_sp_spill_max_raw().bit()),
+                &self.core_1_area_dram0_1_wr_raw(),
             )
+            .field("core_1_area_pif_0_rd_raw", &self.core_1_area_pif_0_rd_raw())
+            .field("core_1_area_pif_0_wr_raw", &self.core_1_area_pif_0_wr_raw())
+            .field("core_1_area_pif_1_rd_raw", &self.core_1_area_pif_1_rd_raw())
+            .field("core_1_area_pif_1_wr_raw", &self.core_1_area_pif_1_wr_raw())
+            .field("core_1_sp_spill_min_raw", &self.core_1_sp_spill_min_raw())
+            .field("core_1_sp_spill_max_raw", &self.core_1_sp_spill_max_raw())
             .field(
                 "core_1_iram0_exception_monitor_raw",
-                &format_args!("{}", self.core_1_iram0_exception_monitor_raw().bit()),
+                &self.core_1_iram0_exception_monitor_raw(),
             )
             .field(
                 "core_1_dram0_exception_monitor_raw",
-                &format_args!("{}", self.core_1_dram0_exception_monitor_raw().bit()),
+                &self.core_1_dram0_exception_monitor_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_INTR_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core1 monitor interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_intr_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_INTR_RAW_SPEC;
 impl crate::RegisterSpec for CORE_1_INTR_RAW_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_intr_rls.rs b/esp32p4/src/assist_debug/core_1_intr_rls.rs
index e2f93349c8..1f823856fa 100644
--- a/esp32p4/src/assist_debug/core_1_intr_rls.rs
+++ b/esp32p4/src/assist_debug/core_1_intr_rls.rs
@@ -118,61 +118,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_INTR_RLS")
             .field(
                 "core_1_area_dram0_0_rd_rls",
-                &format_args!("{}", self.core_1_area_dram0_0_rd_rls().bit()),
+                &self.core_1_area_dram0_0_rd_rls(),
             )
             .field(
                 "core_1_area_dram0_0_wr_rls",
-                &format_args!("{}", self.core_1_area_dram0_0_wr_rls().bit()),
+                &self.core_1_area_dram0_0_wr_rls(),
             )
             .field(
                 "core_1_area_dram0_1_rd_rls",
-                &format_args!("{}", self.core_1_area_dram0_1_rd_rls().bit()),
+                &self.core_1_area_dram0_1_rd_rls(),
             )
             .field(
                 "core_1_area_dram0_1_wr_rls",
-                &format_args!("{}", self.core_1_area_dram0_1_wr_rls().bit()),
-            )
-            .field(
-                "core_1_area_pif_0_rd_rls",
-                &format_args!("{}", self.core_1_area_pif_0_rd_rls().bit()),
-            )
-            .field(
-                "core_1_area_pif_0_wr_rls",
-                &format_args!("{}", self.core_1_area_pif_0_wr_rls().bit()),
-            )
-            .field(
-                "core_1_area_pif_1_rd_rls",
-                &format_args!("{}", self.core_1_area_pif_1_rd_rls().bit()),
-            )
-            .field(
-                "core_1_area_pif_1_wr_rls",
-                &format_args!("{}", self.core_1_area_pif_1_wr_rls().bit()),
-            )
-            .field(
-                "core_1_sp_spill_min_rls",
-                &format_args!("{}", self.core_1_sp_spill_min_rls().bit()),
-            )
-            .field(
-                "core_1_sp_spill_max_rls",
-                &format_args!("{}", self.core_1_sp_spill_max_rls().bit()),
+                &self.core_1_area_dram0_1_wr_rls(),
             )
+            .field("core_1_area_pif_0_rd_rls", &self.core_1_area_pif_0_rd_rls())
+            .field("core_1_area_pif_0_wr_rls", &self.core_1_area_pif_0_wr_rls())
+            .field("core_1_area_pif_1_rd_rls", &self.core_1_area_pif_1_rd_rls())
+            .field("core_1_area_pif_1_wr_rls", &self.core_1_area_pif_1_wr_rls())
+            .field("core_1_sp_spill_min_rls", &self.core_1_sp_spill_min_rls())
+            .field("core_1_sp_spill_max_rls", &self.core_1_sp_spill_max_rls())
             .field(
                 "core_1_iram0_exception_monitor_rls",
-                &format_args!("{}", self.core_1_iram0_exception_monitor_rls().bit()),
+                &self.core_1_iram0_exception_monitor_rls(),
             )
             .field(
                 "core_1_dram0_exception_monitor_rls",
-                &format_args!("{}", self.core_1_dram0_exception_monitor_rls().bit()),
+                &self.core_1_dram0_exception_monitor_rls(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_INTR_RLS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt enable"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_1_iram0_exception_monitor_0.rs b/esp32p4/src/assist_debug/core_1_iram0_exception_monitor_0.rs
index cc426fb67d..295e14c14b 100644
--- a/esp32p4/src/assist_debug/core_1_iram0_exception_monitor_0.rs
+++ b/esp32p4/src/assist_debug/core_1_iram0_exception_monitor_0.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_IRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_1_iram0_recording_addr_0",
-                &format_args!("{}", self.core_1_iram0_recording_addr_0().bits()),
+                &self.core_1_iram0_recording_addr_0(),
             )
             .field(
                 "core_1_iram0_recording_wr_0",
-                &format_args!("{}", self.core_1_iram0_recording_wr_0().bit()),
+                &self.core_1_iram0_recording_wr_0(),
             )
             .field(
                 "core_1_iram0_recording_loadstore_0",
-                &format_args!("{}", self.core_1_iram0_recording_loadstore_0().bit()),
+                &self.core_1_iram0_recording_loadstore_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_iram0_exception_monitor_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC;
 impl crate::RegisterSpec for CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_iram0_exception_monitor_1.rs b/esp32p4/src/assist_debug/core_1_iram0_exception_monitor_1.rs
index 7b8b164311..ff633d82d3 100644
--- a/esp32p4/src/assist_debug/core_1_iram0_exception_monitor_1.rs
+++ b/esp32p4/src/assist_debug/core_1_iram0_exception_monitor_1.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_IRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_1_iram0_recording_addr_1",
-                &format_args!("{}", self.core_1_iram0_recording_addr_1().bits()),
+                &self.core_1_iram0_recording_addr_1(),
             )
             .field(
                 "core_1_iram0_recording_wr_1",
-                &format_args!("{}", self.core_1_iram0_recording_wr_1().bit()),
+                &self.core_1_iram0_recording_wr_1(),
             )
             .field(
                 "core_1_iram0_recording_loadstore_1",
-                &format_args!("{}", self.core_1_iram0_recording_loadstore_1().bit()),
+                &self.core_1_iram0_recording_loadstore_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exception monitor status register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_iram0_exception_monitor_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC;
 impl crate::RegisterSpec for CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_lastpc_before_exception.rs b/esp32p4/src/assist_debug/core_1_lastpc_before_exception.rs
index 213834191d..c589993f58 100644
--- a/esp32p4/src/assist_debug/core_1_lastpc_before_exception.rs
+++ b/esp32p4/src/assist_debug/core_1_lastpc_before_exception.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_LASTPC_BEFORE_EXCEPTION")
-            .field(
-                "core_1_lastpc_before_exc",
-                &format_args!("{}", self.core_1_lastpc_before_exc().bits()),
-            )
+            .field("core_1_lastpc_before_exc", &self.core_1_lastpc_before_exc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_LASTPC_BEFORE_EXCEPTION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "cpu status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_lastpc_before_exception::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_LASTPC_BEFORE_EXCEPTION_SPEC;
 impl crate::RegisterSpec for CORE_1_LASTPC_BEFORE_EXCEPTION_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_rcd_en.rs b/esp32p4/src/assist_debug/core_1_rcd_en.rs
index d8bc218eb7..36855ab957 100644
--- a/esp32p4/src/assist_debug/core_1_rcd_en.rs
+++ b/esp32p4/src/assist_debug/core_1_rcd_en.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_RCD_EN")
-            .field(
-                "core_1_rcd_recorden",
-                &format_args!("{}", self.core_1_rcd_recorden().bit()),
-            )
-            .field(
-                "core_1_rcd_pdebugen",
-                &format_args!("{}", self.core_1_rcd_pdebugen().bit()),
-            )
+            .field("core_1_rcd_recorden", &self.core_1_rcd_recorden())
+            .field("core_1_rcd_pdebugen", &self.core_1_rcd_pdebugen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_RCD_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable record PC"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_1_rcd_pdebugpc.rs b/esp32p4/src/assist_debug/core_1_rcd_pdebugpc.rs
index 828830c318..371e23fb9b 100644
--- a/esp32p4/src/assist_debug/core_1_rcd_pdebugpc.rs
+++ b/esp32p4/src/assist_debug/core_1_rcd_pdebugpc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_RCD_PDEBUGPC")
-            .field(
-                "core_1_rcd_pdebugpc",
-                &format_args!("{}", self.core_1_rcd_pdebugpc().bits()),
-            )
+            .field("core_1_rcd_pdebugpc", &self.core_1_rcd_pdebugpc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_RCD_PDEBUGPC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_pdebugpc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_RCD_PDEBUGPC_SPEC;
 impl crate::RegisterSpec for CORE_1_RCD_PDEBUGPC_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_rcd_pdebugsp.rs b/esp32p4/src/assist_debug/core_1_rcd_pdebugsp.rs
index fa3dbdd9d5..1a3befb8b1 100644
--- a/esp32p4/src/assist_debug/core_1_rcd_pdebugsp.rs
+++ b/esp32p4/src/assist_debug/core_1_rcd_pdebugsp.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_RCD_PDEBUGSP")
-            .field(
-                "core_1_rcd_pdebugsp",
-                &format_args!("{}", self.core_1_rcd_pdebugsp().bits()),
-            )
+            .field("core_1_rcd_pdebugsp", &self.core_1_rcd_pdebugsp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_RCD_PDEBUGSP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "record status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_pdebugsp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_RCD_PDEBUGSP_SPEC;
 impl crate::RegisterSpec for CORE_1_RCD_PDEBUGSP_SPEC {
diff --git a/esp32p4/src/assist_debug/core_1_sp_max.rs b/esp32p4/src/assist_debug/core_1_sp_max.rs
index 398a949eca..a7e59d672d 100644
--- a/esp32p4/src/assist_debug/core_1_sp_max.rs
+++ b/esp32p4/src/assist_debug/core_1_sp_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_SP_MAX")
-            .field(
-                "core_1_sp_max",
-                &format_args!("{}", self.core_1_sp_max().bits()),
-            )
+            .field("core_1_sp_max", &self.core_1_sp_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_SP_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - core1 sp pc status register"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_1_sp_min.rs b/esp32p4/src/assist_debug/core_1_sp_min.rs
index e78447e539..c114a56d75 100644
--- a/esp32p4/src/assist_debug/core_1_sp_min.rs
+++ b/esp32p4/src/assist_debug/core_1_sp_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_SP_MIN")
-            .field(
-                "core_1_sp_min",
-                &format_args!("{}", self.core_1_sp_min().bits()),
-            )
+            .field("core_1_sp_min", &self.core_1_sp_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_SP_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - core1 sp region configuration regsiter"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_1_sp_pc.rs b/esp32p4/src/assist_debug/core_1_sp_pc.rs
index 5089faae6f..902741c5df 100644
--- a/esp32p4/src/assist_debug/core_1_sp_pc.rs
+++ b/esp32p4/src/assist_debug/core_1_sp_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_SP_PC")
-            .field(
-                "core_1_sp_pc",
-                &format_args!("{}", self.core_1_sp_pc().bits()),
-            )
+            .field("core_1_sp_pc", &self.core_1_sp_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_SP_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "stack monitor pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_sp_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_SP_PC_SPEC;
 impl crate::RegisterSpec for CORE_1_SP_PC_SPEC {
diff --git a/esp32p4/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs b/esp32p4/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
index 6fa0b6a1fb..e322997eda 100644
--- a/esp32p4/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
+++ b/esp32p4/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_x_iram0_dram0_limit_cycle_0",
-                &format_args!("{}", self.core_x_iram0_dram0_limit_cycle_0().bits()),
+                &self.core_x_iram0_dram0_limit_cycle_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - reg_core_x_iram0_dram0_limit_cycle_0"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs b/esp32p4/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
index 6c13f7a201..ec7f4d4ef5 100644
--- a/esp32p4/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
+++ b/esp32p4/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_x_iram0_dram0_limit_cycle_1",
-                &format_args!("{}", self.core_x_iram0_dram0_limit_cycle_1().bits()),
+                &self.core_x_iram0_dram0_limit_cycle_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - reg_core_x_iram0_dram0_limit_cycle_1"]
     #[inline(always)]
diff --git a/esp32p4/src/assist_debug/date.rs b/esp32p4/src/assist_debug/date.rs
index 38bb1c07f8..3bd016a008 100644
--- a/esp32p4/src/assist_debug/date.rs
+++ b/esp32p4/src/assist_debug/date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "assist_debug_date",
-                &format_args!("{}", self.assist_debug_date().bits()),
-            )
+            .field("assist_debug_date", &self.assist_debug_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - version register"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/arb_timeout.rs b/esp32p4/src/axi_dma/arb_timeout.rs
index 68e30bd55b..f98b027138 100644
--- a/esp32p4/src/axi_dma/arb_timeout.rs
+++ b/esp32p4/src/axi_dma/arb_timeout.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_TIMEOUT")
-            .field("tx", &format_args!("{}", self.tx().bits()))
-            .field("rx", &format_args!("{}", self.rx().bits()))
+            .field("tx", &self.tx())
+            .field("rx", &self.rx())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_TIMEOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to config tx arbiter time out value"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/date.rs b/esp32p4/src/axi_dma/date.rs
index 9d378d44d9..f4d1611d56 100644
--- a/esp32p4/src/axi_dma/date.rs
+++ b/esp32p4/src/axi_dma/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/axi_dma/extr_mem_end_addr.rs b/esp32p4/src/axi_dma/extr_mem_end_addr.rs
index 4e23f1b1cd..1214ee29b1 100644
--- a/esp32p4/src/axi_dma/extr_mem_end_addr.rs
+++ b/esp32p4/src/axi_dma/extr_mem_end_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXTR_MEM_END_ADDR")
-            .field(
-                "access_extr_mem_end_addr",
-                &format_args!("{}", self.access_extr_mem_end_addr().bits()),
-            )
+            .field("access_extr_mem_end_addr", &self.access_extr_mem_end_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTR_MEM_END_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/extr_mem_start_addr.rs b/esp32p4/src/axi_dma/extr_mem_start_addr.rs
index 3dceed77fd..d35513a67c 100644
--- a/esp32p4/src/axi_dma/extr_mem_start_addr.rs
+++ b/esp32p4/src/axi_dma/extr_mem_start_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("EXTR_MEM_START_ADDR")
             .field(
                 "access_extr_mem_start_addr",
-                &format_args!("{}", self.access_extr_mem_start_addr().bits()),
+                &self.access_extr_mem_start_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTR_MEM_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The start address of accessible address space."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/crc/in_crc_clear.rs b/esp32p4/src/axi_dma/in_ch/crc/in_crc_clear.rs
index a0487a76ee..0be2381b8e 100644
--- a/esp32p4/src/axi_dma/in_ch/crc/in_crc_clear.rs
+++ b/esp32p4/src/axi_dma/in_ch/crc/in_crc_clear.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CRC_CLEAR")
-            .field(
-                "in_crc_clear",
-                &format_args!("{}", self.in_crc_clear().bit()),
-            )
+            .field("in_crc_clear", &self.in_crc_clear())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CRC_CLEAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to clear ch0 of rx crc result"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/crc/in_crc_final_result.rs b/esp32p4/src/axi_dma/in_ch/crc/in_crc_final_result.rs
index 375df4524a..3c091a3b29 100644
--- a/esp32p4/src/axi_dma/in_ch/crc/in_crc_final_result.rs
+++ b/esp32p4/src/axi_dma/in_ch/crc/in_crc_final_result.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CRC_FINAL_RESULT")
-            .field(
-                "in_crc_final_result",
-                &format_args!("{}", self.in_crc_final_result().bits()),
-            )
+            .field("in_crc_final_result", &self.in_crc_final_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CRC_FINAL_RESULT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This register is used to store ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_crc_final_result::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_CRC_FINAL_RESULT_SPEC;
 impl crate::RegisterSpec for IN_CRC_FINAL_RESULT_SPEC {
diff --git a/esp32p4/src/axi_dma/in_ch/crc/in_crc_init_data.rs b/esp32p4/src/axi_dma/in_ch/crc/in_crc_init_data.rs
index 1540743bd7..09b5b4c69c 100644
--- a/esp32p4/src/axi_dma/in_ch/crc/in_crc_init_data.rs
+++ b/esp32p4/src/axi_dma/in_ch/crc/in_crc_init_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CRC_INIT_DATA")
-            .field(
-                "in_crc_init_data",
-                &format_args!("{}", self.in_crc_init_data().bits()),
-            )
+            .field("in_crc_init_data", &self.in_crc_init_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CRC_INIT_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register is used to config ch0 of rx crc initial value"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/crc/rx_crc_data_en_addr.rs b/esp32p4/src/axi_dma/in_ch/crc/rx_crc_data_en_addr.rs
index 4e760554ba..755c71f93b 100644
--- a/esp32p4/src/axi_dma/in_ch/crc/rx_crc_data_en_addr.rs
+++ b/esp32p4/src/axi_dma/in_ch/crc/rx_crc_data_en_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CRC_DATA_EN_ADDR")
-            .field(
-                "rx_crc_data_en_addr",
-                &format_args!("{}", self.rx_crc_data_en_addr().bits()),
-            )
+            .field("rx_crc_data_en_addr", &self.rx_crc_data_en_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CRC_DATA_EN_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/crc/rx_crc_data_en_wr_data.rs b/esp32p4/src/axi_dma/in_ch/crc/rx_crc_data_en_wr_data.rs
index 5f597b9b32..23bbe183ed 100644
--- a/esp32p4/src/axi_dma/in_ch/crc/rx_crc_data_en_wr_data.rs
+++ b/esp32p4/src/axi_dma/in_ch/crc/rx_crc_data_en_wr_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CRC_DATA_EN_WR_DATA")
-            .field(
-                "rx_crc_data_en_wr_data",
-                &format_args!("{}", self.rx_crc_data_en_wr_data().bits()),
-            )
+            .field("rx_crc_data_en_wr_data", &self.rx_crc_data_en_wr_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CRC_DATA_EN_WR_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/crc/rx_crc_en_addr.rs b/esp32p4/src/axi_dma/in_ch/crc/rx_crc_en_addr.rs
index f558a8976d..f6235ba94b 100644
--- a/esp32p4/src/axi_dma/in_ch/crc/rx_crc_en_addr.rs
+++ b/esp32p4/src/axi_dma/in_ch/crc/rx_crc_en_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CRC_EN_ADDR")
-            .field(
-                "rx_crc_en_addr",
-                &format_args!("{}", self.rx_crc_en_addr().bits()),
-            )
+            .field("rx_crc_en_addr", &self.rx_crc_en_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CRC_EN_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/crc/rx_crc_en_wr_data.rs b/esp32p4/src/axi_dma/in_ch/crc/rx_crc_en_wr_data.rs
index ec1db1b08e..32713eb302 100644
--- a/esp32p4/src/axi_dma/in_ch/crc/rx_crc_en_wr_data.rs
+++ b/esp32p4/src/axi_dma/in_ch/crc/rx_crc_en_wr_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CRC_EN_WR_DATA")
-            .field(
-                "rx_crc_en_wr_data",
-                &format_args!("{}", self.rx_crc_en_wr_data().bits()),
-            )
+            .field("rx_crc_en_wr_data", &self.rx_crc_en_wr_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CRC_EN_WR_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register is used to enable rx ch0 crc 32bit on/off"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/crc/rx_crc_width.rs b/esp32p4/src/axi_dma/in_ch/crc/rx_crc_width.rs
index 9172cc7f28..9d690b0dcf 100644
--- a/esp32p4/src/axi_dma/in_ch/crc/rx_crc_width.rs
+++ b/esp32p4/src/axi_dma/in_ch/crc/rx_crc_width.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CRC_WIDTH")
-            .field(
-                "rx_crc_width",
-                &format_args!("{}", self.rx_crc_width().bits()),
-            )
-            .field(
-                "rx_crc_lautch_flga",
-                &format_args!("{}", self.rx_crc_lautch_flga().bit()),
-            )
+            .field("rx_crc_width", &self.rx_crc_width())
+            .field("rx_crc_lautch_flga", &self.rx_crc_lautch_flga())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CRC_WIDTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/in_conf0.rs b/esp32p4/src/axi_dma/in_ch/in_conf0.rs
index b1664d906f..1e660f4f57 100644
--- a/esp32p4/src/axi_dma/in_ch/in_conf0.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_conf0.rs
@@ -80,41 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF0")
-            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
-            .field(
-                "in_loop_test",
-                &format_args!("{}", self.in_loop_test().bit()),
-            )
-            .field(
-                "mem_trans_en",
-                &format_args!("{}", self.mem_trans_en().bit()),
-            )
-            .field("in_etm_en", &format_args!("{}", self.in_etm_en().bit()))
-            .field(
-                "in_burst_size_sel",
-                &format_args!("{}", self.in_burst_size_sel().bits()),
-            )
-            .field(
-                "in_cmd_disable",
-                &format_args!("{}", self.in_cmd_disable().bit()),
-            )
-            .field(
-                "in_ecc_aec_en",
-                &format_args!("{}", self.in_ecc_aec_en().bit()),
-            )
-            .field(
-                "indscr_burst_en",
-                &format_args!("{}", self.indscr_burst_en().bit()),
-            )
+            .field("in_rst", &self.in_rst())
+            .field("in_loop_test", &self.in_loop_test())
+            .field("mem_trans_en", &self.mem_trans_en())
+            .field("in_etm_en", &self.in_etm_en())
+            .field("in_burst_size_sel", &self.in_burst_size_sel())
+            .field("in_cmd_disable", &self.in_cmd_disable())
+            .field("in_ecc_aec_en", &self.in_ecc_aec_en())
+            .field("indscr_burst_en", &self.indscr_burst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/in_conf1.rs b/esp32p4/src/axi_dma/in_ch/in_conf1.rs
index 1da8b38f0b..d95da0040b 100644
--- a/esp32p4/src/axi_dma/in_ch/in_conf1.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_conf1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF1")
-            .field(
-                "in_check_owner",
-                &format_args!("{}", self.in_check_owner().bit()),
-            )
+            .field("in_check_owner", &self.in_check_owner())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/in_dscr.rs b/esp32p4/src/axi_dma/in_ch/in_dscr.rs
index 3d348a76f4..e70d15df66 100644
--- a/esp32p4/src/axi_dma/in_ch/in_dscr.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR")
-            .field(
-                "inlink_dscr",
-                &format_args!("{}", self.inlink_dscr().bits()),
-            )
+            .field("inlink_dscr", &self.inlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_SPEC;
 impl crate::RegisterSpec for IN_DSCR_SPEC {
diff --git a/esp32p4/src/axi_dma/in_ch/in_dscr_bf0.rs b/esp32p4/src/axi_dma/in_ch/in_dscr_bf0.rs
index e3023e2221..fca80e02f8 100644
--- a/esp32p4/src/axi_dma/in_ch/in_dscr_bf0.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF0")
-            .field(
-                "inlink_dscr_bf0",
-                &format_args!("{}", self.inlink_dscr_bf0().bits()),
-            )
+            .field("inlink_dscr_bf0", &self.inlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for IN_DSCR_BF0_SPEC {
diff --git a/esp32p4/src/axi_dma/in_ch/in_dscr_bf1.rs b/esp32p4/src/axi_dma/in_ch/in_dscr_bf1.rs
index 457ee1455f..832bf9b92c 100644
--- a/esp32p4/src/axi_dma/in_ch/in_dscr_bf1.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF1")
-            .field(
-                "inlink_dscr_bf1",
-                &format_args!("{}", self.inlink_dscr_bf1().bits()),
-            )
+            .field("inlink_dscr_bf1", &self.inlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The second-to-last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for IN_DSCR_BF1_SPEC {
diff --git a/esp32p4/src/axi_dma/in_ch/in_err_eof_des_addr.rs b/esp32p4/src/axi_dma/in_ch/in_err_eof_des_addr.rs
index 037171f572..63b8c75ca0 100644
--- a/esp32p4/src/axi_dma/in_ch/in_err_eof_des_addr.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_err_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_ERR_EOF_DES_ADDR")
-            .field(
-                "in_err_eof_des_addr",
-                &format_args!("{}", self.in_err_eof_des_addr().bits()),
-            )
+            .field("in_err_eof_des_addr", &self.in_err_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_ERR_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Inlink descriptor address when errors occur of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_ERR_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_SPEC {
diff --git a/esp32p4/src/axi_dma/in_ch/in_int/ena.rs b/esp32p4/src/axi_dma/in_ch/in_int/ena.rs
index 2eb1ca30e7..f55decfbdd 100644
--- a/esp32p4/src/axi_dma/in_ch/in_int/ena.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_int/ena.rs
@@ -107,47 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENA")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "infifo_l1_ovf",
-                &format_args!("{}", self.infifo_l1_ovf().bit()),
-            )
-            .field(
-                "infifo_l1_udf",
-                &format_args!("{}", self.infifo_l1_udf().bit()),
-            )
-            .field(
-                "infifo_l2_ovf",
-                &format_args!("{}", self.infifo_l2_ovf().bit()),
-            )
-            .field(
-                "infifo_l2_udf",
-                &format_args!("{}", self.infifo_l2_udf().bit()),
-            )
-            .field(
-                "infifo_l3_ovf",
-                &format_args!("{}", self.infifo_l3_ovf().bit()),
-            )
-            .field(
-                "infifo_l3_udf",
-                &format_args!("{}", self.infifo_l3_udf().bit()),
-            )
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_l1_ovf", &self.infifo_l1_ovf())
+            .field("infifo_l1_udf", &self.infifo_l1_udf())
+            .field("infifo_l2_ovf", &self.infifo_l2_ovf())
+            .field("infifo_l2_udf", &self.infifo_l2_udf())
+            .field("infifo_l3_ovf", &self.infifo_l3_ovf())
+            .field("infifo_l3_udf", &self.infifo_l3_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/in_int/raw.rs b/esp32p4/src/axi_dma/in_ch/in_int/raw.rs
index 5b89871481..fe9aa8001f 100644
--- a/esp32p4/src/axi_dma/in_ch/in_int/raw.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_int/raw.rs
@@ -107,47 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RAW")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "infifo_l1_ovf",
-                &format_args!("{}", self.infifo_l1_ovf().bit()),
-            )
-            .field(
-                "infifo_l1_udf",
-                &format_args!("{}", self.infifo_l1_udf().bit()),
-            )
-            .field(
-                "infifo_l2_ovf",
-                &format_args!("{}", self.infifo_l2_ovf().bit()),
-            )
-            .field(
-                "infifo_l2_udf",
-                &format_args!("{}", self.infifo_l2_udf().bit()),
-            )
-            .field(
-                "infifo_l3_ovf",
-                &format_args!("{}", self.infifo_l3_ovf().bit()),
-            )
-            .field(
-                "infifo_l3_udf",
-                &format_args!("{}", self.infifo_l3_udf().bit()),
-            )
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_l1_ovf", &self.infifo_l1_ovf())
+            .field("infifo_l1_udf", &self.infifo_l1_udf())
+            .field("infifo_l2_ovf", &self.infifo_l2_ovf())
+            .field("infifo_l2_udf", &self.infifo_l2_udf())
+            .field("infifo_l3_ovf", &self.infifo_l3_ovf())
+            .field("infifo_l3_udf", &self.infifo_l3_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/in_int/st.rs b/esp32p4/src/axi_dma/in_ch/in_int/st.rs
index 5da1849772..e84d454793 100644
--- a/esp32p4/src/axi_dma/in_ch/in_int/st.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_int/st.rs
@@ -83,41 +83,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ST")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field("infifo_ovf", &format_args!("{}", self.infifo_ovf().bit()))
-            .field("infifo_udf", &format_args!("{}", self.infifo_udf().bit()))
-            .field(
-                "infifo_l1_ovf",
-                &format_args!("{}", self.infifo_l1_ovf().bit()),
-            )
-            .field(
-                "infifo_l1_udf",
-                &format_args!("{}", self.infifo_l1_udf().bit()),
-            )
-            .field(
-                "infifo_l3_ovf",
-                &format_args!("{}", self.infifo_l3_ovf().bit()),
-            )
-            .field(
-                "infifo_l3_udf",
-                &format_args!("{}", self.infifo_l3_udf().bit()),
-            )
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_ovf", &self.infifo_ovf())
+            .field("infifo_udf", &self.infifo_udf())
+            .field("infifo_l1_ovf", &self.infifo_l1_ovf())
+            .field("infifo_l1_udf", &self.infifo_l1_udf())
+            .field("infifo_l3_ovf", &self.infifo_l3_ovf())
+            .field("infifo_l3_udf", &self.infifo_l3_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt of channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ST_SPEC;
 impl crate::RegisterSpec for ST_SPEC {
diff --git a/esp32p4/src/axi_dma/in_ch/in_link1.rs b/esp32p4/src/axi_dma/in_ch/in_link1.rs
index cfcb996678..887fd0bb12 100644
--- a/esp32p4/src/axi_dma/in_ch/in_link1.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_link1.rs
@@ -30,20 +30,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_LINK1")
-            .field(
-                "inlink_auto_ret",
-                &format_args!("{}", self.inlink_auto_ret().bit()),
-            )
-            .field("inlink_park", &format_args!("{}", self.inlink_park().bit()))
+            .field("inlink_auto_ret", &self.inlink_auto_ret())
+            .field("inlink_park", &self.inlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_LINK1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/in_link2.rs b/esp32p4/src/axi_dma/in_ch/in_link2.rs
index a60a451135..14a6ac6cb3 100644
--- a/esp32p4/src/axi_dma/in_ch/in_link2.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_link2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_LINK2")
-            .field(
-                "inlink_addr",
-                &format_args!("{}", self.inlink_addr().bits()),
-            )
+            .field("inlink_addr", &self.inlink_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_LINK2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register stores the 20 least significant bits of the first inlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/in_peri_sel.rs b/esp32p4/src/axi_dma/in_ch/in_peri_sel.rs
index b2b73ee487..2a520fb11f 100644
--- a/esp32p4/src/axi_dma/in_ch/in_peri_sel.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_peri_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_PERI_SEL")
-            .field(
-                "peri_in_sel",
-                &format_args!("{}", self.peri_in_sel().bits()),
-            )
+            .field("peri_in_sel", &self.peri_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_PERI_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/in_pop.rs b/esp32p4/src/axi_dma/in_ch/in_pop.rs
index e870eb1d82..a23cd1c345 100644
--- a/esp32p4/src/axi_dma/in_ch/in_pop.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_pop.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_POP")
-            .field(
-                "infifo_rdata",
-                &format_args!("{}", self.infifo_rdata().bits()),
-            )
+            .field("infifo_rdata", &self.infifo_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_POP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to pop data from AXI_DMA FIFO."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/in_pri.rs b/esp32p4/src/axi_dma/in_ch/in_pri.rs
index c2a645495c..63c21fabaa 100644
--- a/esp32p4/src/axi_dma/in_ch/in_pri.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_pri.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_PRI")
-            .field("rx_pri", &format_args!("{}", self.rx_pri().bits()))
-            .field(
-                "rx_ch_arb_weigh",
-                &format_args!("{}", self.rx_ch_arb_weigh().bits()),
-            )
-            .field(
-                "rx_arb_weigh_opt_dir",
-                &format_args!("{}", self.rx_arb_weigh_opt_dir().bit()),
-            )
+            .field("rx_pri", &self.rx_pri())
+            .field("rx_ch_arb_weigh", &self.rx_ch_arb_weigh())
+            .field("rx_arb_weigh_opt_dir", &self.rx_arb_weigh_opt_dir())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value the higher of the priority."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_ch/in_state.rs b/esp32p4/src/axi_dma/in_ch/in_state.rs
index 6c91ac50d7..83cb3124d8 100644
--- a/esp32p4/src/axi_dma/in_ch/in_state.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_state.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_STATE")
-            .field(
-                "inlink_dscr_addr",
-                &format_args!("{}", self.inlink_dscr_addr().bits()),
-            )
-            .field(
-                "in_dscr_state",
-                &format_args!("{}", self.in_dscr_state().bits()),
-            )
-            .field("in_state", &format_args!("{}", self.in_state().bits()))
+            .field("inlink_dscr_addr", &self.inlink_dscr_addr())
+            .field("in_dscr_state", &self.in_dscr_state())
+            .field("in_state", &self.in_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_STATE_SPEC;
 impl crate::RegisterSpec for IN_STATE_SPEC {
diff --git a/esp32p4/src/axi_dma/in_ch/in_suc_eof_des_addr.rs b/esp32p4/src/axi_dma/in_ch/in_suc_eof_des_addr.rs
index 2b0b4e378a..bd974ca71c 100644
--- a/esp32p4/src/axi_dma/in_ch/in_suc_eof_des_addr.rs
+++ b/esp32p4/src/axi_dma/in_ch/in_suc_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_SUC_EOF_DES_ADDR")
-            .field(
-                "in_suc_eof_des_addr",
-                &format_args!("{}", self.in_suc_eof_des_addr().bits()),
-            )
+            .field("in_suc_eof_des_addr", &self.in_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SUC_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Inlink descriptor address when EOF occurs of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SUC_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_SPEC {
diff --git a/esp32p4/src/axi_dma/in_ch/infifo_status.rs b/esp32p4/src/axi_dma/in_ch/infifo_status.rs
index 8cb19477da..77a3f69b59 100644
--- a/esp32p4/src/axi_dma/in_ch/infifo_status.rs
+++ b/esp32p4/src/axi_dma/in_ch/infifo_status.rs
@@ -160,103 +160,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INFIFO_STATUS")
-            .field(
-                "infifo_l3_full",
-                &format_args!("{}", self.infifo_l3_full().bit()),
-            )
-            .field(
-                "infifo_l3_empty",
-                &format_args!("{}", self.infifo_l3_empty().bit()),
-            )
-            .field(
-                "infifo_l3_cnt",
-                &format_args!("{}", self.infifo_l3_cnt().bits()),
-            )
-            .field(
-                "infifo_l3_udf",
-                &format_args!("{}", self.infifo_l3_udf().bit()),
-            )
-            .field(
-                "infifo_l3_ovf",
-                &format_args!("{}", self.infifo_l3_ovf().bit()),
-            )
-            .field(
-                "infifo_l1_full",
-                &format_args!("{}", self.infifo_l1_full().bit()),
-            )
-            .field(
-                "infifo_l1_empty",
-                &format_args!("{}", self.infifo_l1_empty().bit()),
-            )
-            .field(
-                "infifo_l1_udf",
-                &format_args!("{}", self.infifo_l1_udf().bit()),
-            )
-            .field(
-                "infifo_l1_ovf",
-                &format_args!("{}", self.infifo_l1_ovf().bit()),
-            )
-            .field(
-                "infifo_l2_full",
-                &format_args!("{}", self.infifo_l2_full().bit()),
-            )
-            .field(
-                "infifo_l2_empty",
-                &format_args!("{}", self.infifo_l2_empty().bit()),
-            )
-            .field(
-                "infifo_l2_udf",
-                &format_args!("{}", self.infifo_l2_udf().bit()),
-            )
-            .field(
-                "infifo_l2_ovf",
-                &format_args!("{}", self.infifo_l2_ovf().bit()),
-            )
-            .field(
-                "in_remain_under_1b",
-                &format_args!("{}", self.in_remain_under_1b().bit()),
-            )
-            .field(
-                "in_remain_under_2b",
-                &format_args!("{}", self.in_remain_under_2b().bit()),
-            )
-            .field(
-                "in_remain_under_3b",
-                &format_args!("{}", self.in_remain_under_3b().bit()),
-            )
-            .field(
-                "in_remain_under_4b",
-                &format_args!("{}", self.in_remain_under_4b().bit()),
-            )
-            .field(
-                "in_remain_under_5b",
-                &format_args!("{}", self.in_remain_under_5b().bit()),
-            )
-            .field(
-                "in_remain_under_6b",
-                &format_args!("{}", self.in_remain_under_6b().bit()),
-            )
-            .field(
-                "in_remain_under_7b",
-                &format_args!("{}", self.in_remain_under_7b().bit()),
-            )
-            .field(
-                "in_remain_under_8b",
-                &format_args!("{}", self.in_remain_under_8b().bit()),
-            )
-            .field(
-                "in_buf_hungry",
-                &format_args!("{}", self.in_buf_hungry().bit()),
-            )
+            .field("infifo_l3_full", &self.infifo_l3_full())
+            .field("infifo_l3_empty", &self.infifo_l3_empty())
+            .field("infifo_l3_cnt", &self.infifo_l3_cnt())
+            .field("infifo_l3_udf", &self.infifo_l3_udf())
+            .field("infifo_l3_ovf", &self.infifo_l3_ovf())
+            .field("infifo_l1_full", &self.infifo_l1_full())
+            .field("infifo_l1_empty", &self.infifo_l1_empty())
+            .field("infifo_l1_udf", &self.infifo_l1_udf())
+            .field("infifo_l1_ovf", &self.infifo_l1_ovf())
+            .field("infifo_l2_full", &self.infifo_l2_full())
+            .field("infifo_l2_empty", &self.infifo_l2_empty())
+            .field("infifo_l2_udf", &self.infifo_l2_udf())
+            .field("infifo_l2_ovf", &self.infifo_l2_ovf())
+            .field("in_remain_under_1b", &self.in_remain_under_1b())
+            .field("in_remain_under_2b", &self.in_remain_under_2b())
+            .field("in_remain_under_3b", &self.in_remain_under_3b())
+            .field("in_remain_under_4b", &self.in_remain_under_4b())
+            .field("in_remain_under_5b", &self.in_remain_under_5b())
+            .field("in_remain_under_6b", &self.in_remain_under_6b())
+            .field("in_remain_under_7b", &self.in_remain_under_7b())
+            .field("in_remain_under_8b", &self.in_remain_under_8b())
+            .field("in_buf_hungry", &self.in_buf_hungry())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive FIFO status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for INFIFO_STATUS_SPEC {
diff --git a/esp32p4/src/axi_dma/in_mem_conf.rs b/esp32p4/src/axi_dma/in_mem_conf.rs
index d730afdd45..60ed85cbe2 100644
--- a/esp32p4/src/axi_dma/in_mem_conf.rs
+++ b/esp32p4/src/axi_dma/in_mem_conf.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_MEM_CONF")
-            .field(
-                "in_mem_clk_force_en",
-                &format_args!("{}", self.in_mem_clk_force_en().bit()),
-            )
-            .field(
-                "in_mem_force_pu",
-                &format_args!("{}", self.in_mem_force_pu().bit()),
-            )
-            .field(
-                "in_mem_force_pd",
-                &format_args!("{}", self.in_mem_force_pd().bit()),
-            )
-            .field(
-                "out_mem_clk_force_en",
-                &format_args!("{}", self.out_mem_clk_force_en().bit()),
-            )
-            .field(
-                "out_mem_force_pu",
-                &format_args!("{}", self.out_mem_force_pu().bit()),
-            )
-            .field(
-                "out_mem_force_pd",
-                &format_args!("{}", self.out_mem_force_pd().bit()),
-            )
+            .field("in_mem_clk_force_en", &self.in_mem_clk_force_en())
+            .field("in_mem_force_pu", &self.in_mem_force_pu())
+            .field("in_mem_force_pd", &self.in_mem_force_pd())
+            .field("out_mem_clk_force_en", &self.out_mem_clk_force_en())
+            .field("out_mem_force_pu", &self.out_mem_force_pu())
+            .field("out_mem_force_pd", &self.out_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/in_reset_avail_ch.rs b/esp32p4/src/axi_dma/in_reset_avail_ch.rs
index cea864c776..2ebfcc3c44 100644
--- a/esp32p4/src/axi_dma/in_reset_avail_ch.rs
+++ b/esp32p4/src/axi_dma/in_reset_avail_ch.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_RESET_AVAIL_CH")
-            .field(
-                "in_reset_avail",
-                &format_args!("{}", self.in_reset_avail().bit()),
-            )
+            .field("in_reset_avail", &self.in_reset_avail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_RESET_AVAIL_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The rx channel 0 reset valid_flag register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_reset_avail_ch::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_RESET_AVAIL_CH_SPEC;
 impl crate::RegisterSpec for IN_RESET_AVAIL_CH_SPEC {
diff --git a/esp32p4/src/axi_dma/infifo_status1_ch.rs b/esp32p4/src/axi_dma/infifo_status1_ch.rs
index c9d104e9e1..d7e7728966 100644
--- a/esp32p4/src/axi_dma/infifo_status1_ch.rs
+++ b/esp32p4/src/axi_dma/infifo_status1_ch.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INFIFO_STATUS1_CH")
-            .field(
-                "l1infifo_cnt",
-                &format_args!("{}", self.l1infifo_cnt().bits()),
-            )
-            .field(
-                "l2infifo_cnt",
-                &format_args!("{}", self.l2infifo_cnt().bits()),
-            )
+            .field("l1infifo_cnt", &self.l1infifo_cnt())
+            .field("l2infifo_cnt", &self.l2infifo_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INFIFO_STATUS1_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive FIFO status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status1_ch::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INFIFO_STATUS1_CH_SPEC;
 impl crate::RegisterSpec for INFIFO_STATUS1_CH_SPEC {
diff --git a/esp32p4/src/axi_dma/intr_mem_end_addr.rs b/esp32p4/src/axi_dma/intr_mem_end_addr.rs
index 4afef1c5cf..d964483b5f 100644
--- a/esp32p4/src/axi_dma/intr_mem_end_addr.rs
+++ b/esp32p4/src/axi_dma/intr_mem_end_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_MEM_END_ADDR")
-            .field(
-                "access_intr_mem_end_addr",
-                &format_args!("{}", self.access_intr_mem_end_addr().bits()),
-            )
+            .field("access_intr_mem_end_addr", &self.access_intr_mem_end_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_MEM_END_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/intr_mem_start_addr.rs b/esp32p4/src/axi_dma/intr_mem_start_addr.rs
index 138f2777af..09d22763a5 100644
--- a/esp32p4/src/axi_dma/intr_mem_start_addr.rs
+++ b/esp32p4/src/axi_dma/intr_mem_start_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTR_MEM_START_ADDR")
             .field(
                 "access_intr_mem_start_addr",
-                &format_args!("{}", self.access_intr_mem_start_addr().bits()),
+                &self.access_intr_mem_start_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_MEM_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The start address of accessible address space."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/misc_conf.rs b/esp32p4/src/axi_dma/misc_conf.rs
index df3602f9f2..e1d789375d 100644
--- a/esp32p4/src/axi_dma/misc_conf.rs
+++ b/esp32p4/src/axi_dma/misc_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC_CONF")
-            .field(
-                "axim_rst_wr_inter",
-                &format_args!("{}", self.axim_rst_wr_inter().bit()),
-            )
-            .field(
-                "axim_rst_rd_inter",
-                &format_args!("{}", self.axim_rst_rd_inter().bit()),
-            )
-            .field("arb_pri_dis", &format_args!("{}", self.arb_pri_dis().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("axim_rst_wr_inter", &self.axim_rst_wr_inter())
+            .field("axim_rst_rd_inter", &self.axim_rst_rd_inter())
+            .field("arb_pri_dis", &self.arb_pri_dis())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit then clear this bit to reset the internal axi_wr FSM."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/crc/out_crc_clear.rs b/esp32p4/src/axi_dma/out_ch/crc/out_crc_clear.rs
index ecddc616e1..855bf8e69e 100644
--- a/esp32p4/src/axi_dma/out_ch/crc/out_crc_clear.rs
+++ b/esp32p4/src/axi_dma/out_ch/crc/out_crc_clear.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CRC_CLEAR")
-            .field(
-                "out_crc_clear",
-                &format_args!("{}", self.out_crc_clear().bit()),
-            )
+            .field("out_crc_clear", &self.out_crc_clear())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CRC_CLEAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to clear ch0 of tx crc result"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/crc/out_crc_final_result.rs b/esp32p4/src/axi_dma/out_ch/crc/out_crc_final_result.rs
index fc709f0109..1a6abf53b4 100644
--- a/esp32p4/src/axi_dma/out_ch/crc/out_crc_final_result.rs
+++ b/esp32p4/src/axi_dma/out_ch/crc/out_crc_final_result.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CRC_FINAL_RESULT")
-            .field(
-                "out_crc_final_result",
-                &format_args!("{}", self.out_crc_final_result().bits()),
-            )
+            .field("out_crc_final_result", &self.out_crc_final_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CRC_FINAL_RESULT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "This register is used to store ch0 crc result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_crc_final_result::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_CRC_FINAL_RESULT_SPEC;
 impl crate::RegisterSpec for OUT_CRC_FINAL_RESULT_SPEC {
diff --git a/esp32p4/src/axi_dma/out_ch/crc/out_crc_init_data.rs b/esp32p4/src/axi_dma/out_ch/crc/out_crc_init_data.rs
index 97af8f7438..5e5fd511a6 100644
--- a/esp32p4/src/axi_dma/out_ch/crc/out_crc_init_data.rs
+++ b/esp32p4/src/axi_dma/out_ch/crc/out_crc_init_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CRC_INIT_DATA")
-            .field(
-                "out_crc_init_data",
-                &format_args!("{}", self.out_crc_init_data().bits()),
-            )
+            .field("out_crc_init_data", &self.out_crc_init_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CRC_INIT_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register is used to config ch0 of tx crc initial value"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/crc/tx_crc_data_en_addr.rs b/esp32p4/src/axi_dma/out_ch/crc/tx_crc_data_en_addr.rs
index 5357a93754..d0ebd8afc1 100644
--- a/esp32p4/src/axi_dma/out_ch/crc/tx_crc_data_en_addr.rs
+++ b/esp32p4/src/axi_dma/out_ch/crc/tx_crc_data_en_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC_DATA_EN_ADDR")
-            .field(
-                "tx_crc_data_en_addr",
-                &format_args!("{}", self.tx_crc_data_en_addr().bits()),
-            )
+            .field("tx_crc_data_en_addr", &self.tx_crc_data_en_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_DATA_EN_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/crc/tx_crc_data_en_wr_data.rs b/esp32p4/src/axi_dma/out_ch/crc/tx_crc_data_en_wr_data.rs
index bcfd00f050..3e11b221de 100644
--- a/esp32p4/src/axi_dma/out_ch/crc/tx_crc_data_en_wr_data.rs
+++ b/esp32p4/src/axi_dma/out_ch/crc/tx_crc_data_en_wr_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC_DATA_EN_WR_DATA")
-            .field(
-                "tx_crc_data_en_wr_data",
-                &format_args!("{}", self.tx_crc_data_en_wr_data().bits()),
-            )
+            .field("tx_crc_data_en_wr_data", &self.tx_crc_data_en_wr_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_DATA_EN_WR_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/crc/tx_crc_en_addr.rs b/esp32p4/src/axi_dma/out_ch/crc/tx_crc_en_addr.rs
index f2e4faa3f8..bb38c3f154 100644
--- a/esp32p4/src/axi_dma/out_ch/crc/tx_crc_en_addr.rs
+++ b/esp32p4/src/axi_dma/out_ch/crc/tx_crc_en_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC_EN_ADDR")
-            .field(
-                "tx_crc_en_addr",
-                &format_args!("{}", self.tx_crc_en_addr().bits()),
-            )
+            .field("tx_crc_en_addr", &self.tx_crc_en_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_EN_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/crc/tx_crc_en_wr_data.rs b/esp32p4/src/axi_dma/out_ch/crc/tx_crc_en_wr_data.rs
index e6a157eac8..fd96e2b5e0 100644
--- a/esp32p4/src/axi_dma/out_ch/crc/tx_crc_en_wr_data.rs
+++ b/esp32p4/src/axi_dma/out_ch/crc/tx_crc_en_wr_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC_EN_WR_DATA")
-            .field(
-                "tx_crc_en_wr_data",
-                &format_args!("{}", self.tx_crc_en_wr_data().bits()),
-            )
+            .field("tx_crc_en_wr_data", &self.tx_crc_en_wr_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_EN_WR_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register is used to enable tx ch0 crc 32bit on/off"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/crc/tx_crc_width.rs b/esp32p4/src/axi_dma/out_ch/crc/tx_crc_width.rs
index d8a319b60a..d1ea8fbd14 100644
--- a/esp32p4/src/axi_dma/out_ch/crc/tx_crc_width.rs
+++ b/esp32p4/src/axi_dma/out_ch/crc/tx_crc_width.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC_WIDTH")
-            .field(
-                "tx_crc_width",
-                &format_args!("{}", self.tx_crc_width().bits()),
-            )
-            .field(
-                "tx_crc_lautch_flga",
-                &format_args!("{}", self.tx_crc_lautch_flga().bit()),
-            )
+            .field("tx_crc_width", &self.tx_crc_width())
+            .field("tx_crc_lautch_flga", &self.tx_crc_lautch_flga())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_WIDTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/out_conf0.rs b/esp32p4/src/axi_dma/out_ch/out_conf0.rs
index 66bcbddf18..5a499ffe53 100644
--- a/esp32p4/src/axi_dma/out_ch/out_conf0.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_conf0.rs
@@ -89,45 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CONF0")
-            .field("out_rst_", &format_args!("{}", self.out_rst_().bit()))
-            .field(
-                "out_loop_test",
-                &format_args!("{}", self.out_loop_test().bit()),
-            )
-            .field(
-                "out_auto_wrback",
-                &format_args!("{}", self.out_auto_wrback().bit()),
-            )
-            .field(
-                "out_eof_mode",
-                &format_args!("{}", self.out_eof_mode().bit()),
-            )
-            .field("out_etm_en", &format_args!("{}", self.out_etm_en().bit()))
-            .field(
-                "out_burst_size_sel",
-                &format_args!("{}", self.out_burst_size_sel().bits()),
-            )
-            .field(
-                "out_cmd_disable",
-                &format_args!("{}", self.out_cmd_disable().bit()),
-            )
-            .field(
-                "out_ecc_aec_en",
-                &format_args!("{}", self.out_ecc_aec_en().bit()),
-            )
-            .field(
-                "outdscr_burst_en",
-                &format_args!("{}", self.outdscr_burst_en().bit()),
-            )
+            .field("out_rst_", &self.out_rst_())
+            .field("out_loop_test", &self.out_loop_test())
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("out_eof_mode", &self.out_eof_mode())
+            .field("out_etm_en", &self.out_etm_en())
+            .field("out_burst_size_sel", &self.out_burst_size_sel())
+            .field("out_cmd_disable", &self.out_cmd_disable())
+            .field("out_ecc_aec_en", &self.out_ecc_aec_en())
+            .field("outdscr_burst_en", &self.outdscr_burst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/out_conf1.rs b/esp32p4/src/axi_dma/out_ch/out_conf1.rs
index 4ef11ad4fa..08b8c0cfc5 100644
--- a/esp32p4/src/axi_dma/out_ch/out_conf1.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_conf1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CONF1")
-            .field(
-                "out_check_owner",
-                &format_args!("{}", self.out_check_owner().bit()),
-            )
+            .field("out_check_owner", &self.out_check_owner())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/out_dscr.rs b/esp32p4/src/axi_dma/out_ch/out_dscr.rs
index 5a7a285a3d..255c2886b6 100644
--- a/esp32p4/src/axi_dma/out_ch/out_dscr.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR")
-            .field(
-                "outlink_dscr",
-                &format_args!("{}", self.outlink_dscr().bits()),
-            )
+            .field("outlink_dscr", &self.outlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current outlink descriptor address of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_SPEC {
diff --git a/esp32p4/src/axi_dma/out_ch/out_dscr_bf0.rs b/esp32p4/src/axi_dma/out_ch/out_dscr_bf0.rs
index b39725e388..5cbb1f714c 100644
--- a/esp32p4/src/axi_dma/out_ch/out_dscr_bf0.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR_BF0")
-            .field(
-                "outlink_dscr_bf0",
-                &format_args!("{}", self.outlink_dscr_bf0().bits()),
-            )
+            .field("outlink_dscr_bf0", &self.outlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The last outlink descriptor address of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_BF0_SPEC {
diff --git a/esp32p4/src/axi_dma/out_ch/out_dscr_bf1.rs b/esp32p4/src/axi_dma/out_ch/out_dscr_bf1.rs
index d0b0f83f2e..e90c83c94c 100644
--- a/esp32p4/src/axi_dma/out_ch/out_dscr_bf1.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR_BF1")
-            .field(
-                "outlink_dscr_bf1",
-                &format_args!("{}", self.outlink_dscr_bf1().bits()),
-            )
+            .field("outlink_dscr_bf1", &self.outlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The second-to-last outlink descriptor address of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_BF1_SPEC {
diff --git a/esp32p4/src/axi_dma/out_ch/out_eof_bfr_des_addr.rs b/esp32p4/src/axi_dma/out_ch/out_eof_bfr_des_addr.rs
index 52bc17143b..8717c4f58a 100644
--- a/esp32p4/src/axi_dma/out_ch/out_eof_bfr_des_addr.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_eof_bfr_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_BFR_DES_ADDR")
-            .field(
-                "out_eof_bfr_des_addr",
-                &format_args!("{}", self.out_eof_bfr_des_addr().bits()),
-            )
+            .field("out_eof_bfr_des_addr", &self.out_eof_bfr_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_BFR_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The last outlink descriptor address when EOF occurs of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_bfr_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_BFR_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_SPEC {
diff --git a/esp32p4/src/axi_dma/out_ch/out_eof_des_addr.rs b/esp32p4/src/axi_dma/out_ch/out_eof_des_addr.rs
index b997ab4991..1f9f6ec291 100644
--- a/esp32p4/src/axi_dma/out_ch/out_eof_des_addr.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_DES_ADDR")
-            .field(
-                "out_eof_des_addr",
-                &format_args!("{}", self.out_eof_des_addr().bits()),
-            )
+            .field("out_eof_des_addr", &self.out_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Outlink descriptor address when EOF occurs of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_DES_ADDR_SPEC {
diff --git a/esp32p4/src/axi_dma/out_ch/out_int/ena.rs b/esp32p4/src/axi_dma/out_ch/out_int/ena.rs
index 7488ada64c..5d077cb486 100644
--- a/esp32p4/src/axi_dma/out_ch/out_int/ena.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_int/ena.rs
@@ -98,49 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENA")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field(
-                "outfifo_l1_ovf",
-                &format_args!("{}", self.outfifo_l1_ovf().bit()),
-            )
-            .field(
-                "outfifo_l1_udf",
-                &format_args!("{}", self.outfifo_l1_udf().bit()),
-            )
-            .field(
-                "outfifo_l2_ovf",
-                &format_args!("{}", self.outfifo_l2_ovf().bit()),
-            )
-            .field(
-                "outfifo_l2_udf",
-                &format_args!("{}", self.outfifo_l2_udf().bit()),
-            )
-            .field(
-                "outfifo_l3_ovf",
-                &format_args!("{}", self.outfifo_l3_ovf().bit()),
-            )
-            .field(
-                "outfifo_l3_udf",
-                &format_args!("{}", self.outfifo_l3_udf().bit()),
-            )
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_l1_ovf", &self.outfifo_l1_ovf())
+            .field("outfifo_l1_udf", &self.outfifo_l1_udf())
+            .field("outfifo_l2_ovf", &self.outfifo_l2_ovf())
+            .field("outfifo_l2_udf", &self.outfifo_l2_udf())
+            .field("outfifo_l3_ovf", &self.outfifo_l3_ovf())
+            .field("outfifo_l3_udf", &self.outfifo_l3_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/out_int/raw.rs b/esp32p4/src/axi_dma/out_ch/out_int/raw.rs
index 9907526613..f9e5423adb 100644
--- a/esp32p4/src/axi_dma/out_ch/out_int/raw.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_int/raw.rs
@@ -98,49 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RAW")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field(
-                "outfifo_l1_ovf",
-                &format_args!("{}", self.outfifo_l1_ovf().bit()),
-            )
-            .field(
-                "outfifo_l1_udf",
-                &format_args!("{}", self.outfifo_l1_udf().bit()),
-            )
-            .field(
-                "outfifo_l2_ovf",
-                &format_args!("{}", self.outfifo_l2_ovf().bit()),
-            )
-            .field(
-                "outfifo_l2_udf",
-                &format_args!("{}", self.outfifo_l2_udf().bit()),
-            )
-            .field(
-                "outfifo_l3_ovf",
-                &format_args!("{}", self.outfifo_l3_ovf().bit()),
-            )
-            .field(
-                "outfifo_l3_udf",
-                &format_args!("{}", self.outfifo_l3_udf().bit()),
-            )
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_l1_ovf", &self.outfifo_l1_ovf())
+            .field("outfifo_l1_udf", &self.outfifo_l1_udf())
+            .field("outfifo_l2_ovf", &self.outfifo_l2_ovf())
+            .field("outfifo_l2_udf", &self.outfifo_l2_udf())
+            .field("outfifo_l3_ovf", &self.outfifo_l3_ovf())
+            .field("outfifo_l3_udf", &self.outfifo_l3_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel0."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/out_int/st.rs b/esp32p4/src/axi_dma/out_ch/out_int/st.rs
index c3c760e2f3..340676ca83 100644
--- a/esp32p4/src/axi_dma/out_ch/out_int/st.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_int/st.rs
@@ -76,43 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ST")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("outfifo_ovf", &format_args!("{}", self.outfifo_ovf().bit()))
-            .field("outfifo_udf", &format_args!("{}", self.outfifo_udf().bit()))
-            .field(
-                "outfifo_l1_ovf",
-                &format_args!("{}", self.outfifo_l1_ovf().bit()),
-            )
-            .field(
-                "outfifo_l1_udf",
-                &format_args!("{}", self.outfifo_l1_udf().bit()),
-            )
-            .field(
-                "outfifo_l3_ovf",
-                &format_args!("{}", self.outfifo_l3_ovf().bit()),
-            )
-            .field(
-                "outfifo_l3_udf",
-                &format_args!("{}", self.outfifo_l3_udf().bit()),
-            )
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf", &self.outfifo_ovf())
+            .field("outfifo_udf", &self.outfifo_udf())
+            .field("outfifo_l1_ovf", &self.outfifo_l1_ovf())
+            .field("outfifo_l1_udf", &self.outfifo_l1_udf())
+            .field("outfifo_l3_ovf", &self.outfifo_l3_ovf())
+            .field("outfifo_l3_udf", &self.outfifo_l3_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt of channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ST_SPEC;
 impl crate::RegisterSpec for ST_SPEC {
diff --git a/esp32p4/src/axi_dma/out_ch/out_link1.rs b/esp32p4/src/axi_dma/out_ch/out_link1.rs
index 0781fbbce7..ea042a170d 100644
--- a/esp32p4/src/axi_dma/out_ch/out_link1.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_link1.rs
@@ -21,19 +21,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_LINK1")
-            .field(
-                "outlink_park",
-                &format_args!("{}", self.outlink_park().bit()),
-            )
+            .field("outlink_park", &self.outlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_LINK1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to stop dealing with the outlink descriptors."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/out_link2.rs b/esp32p4/src/axi_dma/out_ch/out_link2.rs
index 3761b98297..f39d754401 100644
--- a/esp32p4/src/axi_dma/out_ch/out_link2.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_link2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_LINK2")
-            .field(
-                "outlink_addr",
-                &format_args!("{}", self.outlink_addr().bits()),
-            )
+            .field("outlink_addr", &self.outlink_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_LINK2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register stores the 32 least significant bits of the first outlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/out_peri_sel.rs b/esp32p4/src/axi_dma/out_ch/out_peri_sel.rs
index 6db0cb6e3b..acafd1dbe1 100644
--- a/esp32p4/src/axi_dma/out_ch/out_peri_sel.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_peri_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PERI_SEL")
-            .field(
-                "peri_out_sel",
-                &format_args!("{}", self.peri_out_sel().bits()),
-            )
+            .field("peri_out_sel", &self.peri_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PERI_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2. 2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/out_pri.rs b/esp32p4/src/axi_dma/out_ch/out_pri.rs
index 55be88761a..eb367d7f9b 100644
--- a/esp32p4/src/axi_dma/out_ch/out_pri.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_pri.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PRI")
-            .field("tx_pri", &format_args!("{}", self.tx_pri().bits()))
-            .field(
-                "tx_ch_arb_weigh",
-                &format_args!("{}", self.tx_ch_arb_weigh().bits()),
-            )
-            .field(
-                "tx_arb_weigh_opt_dir",
-                &format_args!("{}", self.tx_arb_weigh_opt_dir().bit()),
-            )
+            .field("tx_pri", &self.tx_pri())
+            .field("tx_ch_arb_weigh", &self.tx_ch_arb_weigh())
+            .field("tx_arb_weigh_opt_dir", &self.tx_arb_weigh_opt_dir())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The priority of Tx channel0. The larger of the value the higher of the priority."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/out_push.rs b/esp32p4/src/axi_dma/out_ch/out_push.rs
index df5fb90941..16a1cd05a3 100644
--- a/esp32p4/src/axi_dma/out_ch/out_push.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_push.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PUSH")
-            .field(
-                "outfifo_wdata",
-                &format_args!("{}", self.outfifo_wdata().bits()),
-            )
+            .field("outfifo_wdata", &self.outfifo_wdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PUSH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register stores the data that need to be pushed into AXI_DMA FIFO."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/out_ch/out_state.rs b/esp32p4/src/axi_dma/out_ch/out_state.rs
index 4469e6b337..6abc208a7f 100644
--- a/esp32p4/src/axi_dma/out_ch/out_state.rs
+++ b/esp32p4/src/axi_dma/out_ch/out_state.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_STATE")
-            .field(
-                "outlink_dscr_addr",
-                &format_args!("{}", self.outlink_dscr_addr().bits()),
-            )
-            .field(
-                "out_dscr_state",
-                &format_args!("{}", self.out_dscr_state().bits()),
-            )
-            .field("out_state", &format_args!("{}", self.out_state().bits()))
+            .field("outlink_dscr_addr", &self.outlink_dscr_addr())
+            .field("out_dscr_state", &self.out_dscr_state())
+            .field("out_state", &self.out_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transmit status of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_STATE_SPEC;
 impl crate::RegisterSpec for OUT_STATE_SPEC {
diff --git a/esp32p4/src/axi_dma/out_ch/outfifo_status.rs b/esp32p4/src/axi_dma/out_ch/outfifo_status.rs
index ad23120fe5..8d71e59c32 100644
--- a/esp32p4/src/axi_dma/out_ch/outfifo_status.rs
+++ b/esp32p4/src/axi_dma/out_ch/outfifo_status.rs
@@ -153,99 +153,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTFIFO_STATUS")
-            .field(
-                "outfifo_l3_full",
-                &format_args!("{}", self.outfifo_l3_full().bit()),
-            )
-            .field(
-                "outfifo_l3_empty",
-                &format_args!("{}", self.outfifo_l3_empty().bit()),
-            )
-            .field(
-                "outfifo_l3_cnt",
-                &format_args!("{}", self.outfifo_l3_cnt().bits()),
-            )
-            .field(
-                "outfifo_l3_udf",
-                &format_args!("{}", self.outfifo_l3_udf().bit()),
-            )
-            .field(
-                "outfifo_l3_ovf",
-                &format_args!("{}", self.outfifo_l3_ovf().bit()),
-            )
-            .field(
-                "outfifo_l1_full",
-                &format_args!("{}", self.outfifo_l1_full().bit()),
-            )
-            .field(
-                "outfifo_l1_empty",
-                &format_args!("{}", self.outfifo_l1_empty().bit()),
-            )
-            .field(
-                "outfifo_l1_udf",
-                &format_args!("{}", self.outfifo_l1_udf().bit()),
-            )
-            .field(
-                "outfifo_l1_ovf",
-                &format_args!("{}", self.outfifo_l1_ovf().bit()),
-            )
-            .field(
-                "outfifo_l2_full",
-                &format_args!("{}", self.outfifo_l2_full().bit()),
-            )
-            .field(
-                "outfifo_l2_empty",
-                &format_args!("{}", self.outfifo_l2_empty().bit()),
-            )
-            .field(
-                "outfifo_l2_udf",
-                &format_args!("{}", self.outfifo_l2_udf().bit()),
-            )
-            .field(
-                "outfifo_l2_ovf",
-                &format_args!("{}", self.outfifo_l2_ovf().bit()),
-            )
-            .field(
-                "out_remain_under_1b",
-                &format_args!("{}", self.out_remain_under_1b().bit()),
-            )
-            .field(
-                "out_remain_under_2b",
-                &format_args!("{}", self.out_remain_under_2b().bit()),
-            )
-            .field(
-                "out_remain_under_3b",
-                &format_args!("{}", self.out_remain_under_3b().bit()),
-            )
-            .field(
-                "out_remain_under_4b",
-                &format_args!("{}", self.out_remain_under_4b().bit()),
-            )
-            .field(
-                "out_remain_under_5b",
-                &format_args!("{}", self.out_remain_under_5b().bit()),
-            )
-            .field(
-                "out_remain_under_6b",
-                &format_args!("{}", self.out_remain_under_6b().bit()),
-            )
-            .field(
-                "out_remain_under_7b",
-                &format_args!("{}", self.out_remain_under_7b().bit()),
-            )
-            .field(
-                "out_remain_under_8b",
-                &format_args!("{}", self.out_remain_under_8b().bit()),
-            )
+            .field("outfifo_l3_full", &self.outfifo_l3_full())
+            .field("outfifo_l3_empty", &self.outfifo_l3_empty())
+            .field("outfifo_l3_cnt", &self.outfifo_l3_cnt())
+            .field("outfifo_l3_udf", &self.outfifo_l3_udf())
+            .field("outfifo_l3_ovf", &self.outfifo_l3_ovf())
+            .field("outfifo_l1_full", &self.outfifo_l1_full())
+            .field("outfifo_l1_empty", &self.outfifo_l1_empty())
+            .field("outfifo_l1_udf", &self.outfifo_l1_udf())
+            .field("outfifo_l1_ovf", &self.outfifo_l1_ovf())
+            .field("outfifo_l2_full", &self.outfifo_l2_full())
+            .field("outfifo_l2_empty", &self.outfifo_l2_empty())
+            .field("outfifo_l2_udf", &self.outfifo_l2_udf())
+            .field("outfifo_l2_ovf", &self.outfifo_l2_ovf())
+            .field("out_remain_under_1b", &self.out_remain_under_1b())
+            .field("out_remain_under_2b", &self.out_remain_under_2b())
+            .field("out_remain_under_3b", &self.out_remain_under_3b())
+            .field("out_remain_under_4b", &self.out_remain_under_4b())
+            .field("out_remain_under_5b", &self.out_remain_under_5b())
+            .field("out_remain_under_6b", &self.out_remain_under_6b())
+            .field("out_remain_under_7b", &self.out_remain_under_7b())
+            .field("out_remain_under_8b", &self.out_remain_under_8b())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transmit FIFO status of Tx channel0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for OUTFIFO_STATUS_SPEC {
diff --git a/esp32p4/src/axi_dma/out_reset_avail_ch.rs b/esp32p4/src/axi_dma/out_reset_avail_ch.rs
index e78a73d9bd..0c4c865319 100644
--- a/esp32p4/src/axi_dma/out_reset_avail_ch.rs
+++ b/esp32p4/src/axi_dma/out_reset_avail_ch.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_RESET_AVAIL_CH")
-            .field(
-                "out_reset_avail",
-                &format_args!("{}", self.out_reset_avail().bit()),
-            )
+            .field("out_reset_avail", &self.out_reset_avail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_RESET_AVAIL_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The tx channel 0 reset valid_flag register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_reset_avail_ch::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_RESET_AVAIL_CH_SPEC;
 impl crate::RegisterSpec for OUT_RESET_AVAIL_CH_SPEC {
diff --git a/esp32p4/src/axi_dma/outfifo_status1_ch.rs b/esp32p4/src/axi_dma/outfifo_status1_ch.rs
index 5b614d309c..4ea775ec3f 100644
--- a/esp32p4/src/axi_dma/outfifo_status1_ch.rs
+++ b/esp32p4/src/axi_dma/outfifo_status1_ch.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTFIFO_STATUS1_CH")
-            .field(
-                "l1outfifo_cnt",
-                &format_args!("{}", self.l1outfifo_cnt().bits()),
-            )
-            .field(
-                "l2outfifo_cnt",
-                &format_args!("{}", self.l2outfifo_cnt().bits()),
-            )
+            .field("l1outfifo_cnt", &self.l1outfifo_cnt())
+            .field("l2outfifo_cnt", &self.l2outfifo_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTFIFO_STATUS1_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive FIFO status of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status1_ch::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTFIFO_STATUS1_CH_SPEC;
 impl crate::RegisterSpec for OUTFIFO_STATUS1_CH_SPEC {
diff --git a/esp32p4/src/axi_dma/rdn_eco_high.rs b/esp32p4/src/axi_dma/rdn_eco_high.rs
index a1a25ffdea..5f1d21beb7 100644
--- a/esp32p4/src/axi_dma/rdn_eco_high.rs
+++ b/esp32p4/src/axi_dma/rdn_eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDN_ECO_HIGH")
-            .field(
-                "rdn_eco_high",
-                &format_args!("{}", self.rdn_eco_high().bits()),
-            )
+            .field("rdn_eco_high", &self.rdn_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDN_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The start address of accessible address space."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/rdn_eco_low.rs b/esp32p4/src/axi_dma/rdn_eco_low.rs
index 5c934475e1..efdea4f639 100644
--- a/esp32p4/src/axi_dma/rdn_eco_low.rs
+++ b/esp32p4/src/axi_dma/rdn_eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDN_ECO_LOW")
-            .field(
-                "rdn_eco_low",
-                &format_args!("{}", self.rdn_eco_low().bits()),
-            )
+            .field("rdn_eco_low", &self.rdn_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDN_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The start address of accessible address space."]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/rdn_result.rs b/esp32p4/src/axi_dma/rdn_result.rs
index dd5511cf67..a5ba482a73 100644
--- a/esp32p4/src/axi_dma/rdn_result.rs
+++ b/esp32p4/src/axi_dma/rdn_result.rs
@@ -24,17 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDN_RESULT")
-            .field("rdn_ena", &format_args!("{}", self.rdn_ena().bit()))
-            .field("rdn_result", &format_args!("{}", self.rdn_result().bit()))
+            .field("rdn_ena", &self.rdn_ena())
+            .field("rdn_result", &self.rdn_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDN_RESULT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/rresp_cnt.rs b/esp32p4/src/axi_dma/rresp_cnt.rs
index 94bd148ffc..e20dc44fa3 100644
--- a/esp32p4/src/axi_dma/rresp_cnt.rs
+++ b/esp32p4/src/axi_dma/rresp_cnt.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RRESP_CNT")
-            .field("rresp_cnt", &format_args!("{}", self.rresp_cnt().bits()))
+            .field("rresp_cnt", &self.rresp_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RRESP_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "AXI wr responce cnt register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rresp_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RRESP_CNT_SPEC;
 impl crate::RegisterSpec for RRESP_CNT_SPEC {
diff --git a/esp32p4/src/axi_dma/weight_en.rs b/esp32p4/src/axi_dma/weight_en.rs
index 4ee5f3b822..6f0c1f4678 100644
--- a/esp32p4/src/axi_dma/weight_en.rs
+++ b/esp32p4/src/axi_dma/weight_en.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WEIGHT_EN")
-            .field("tx", &format_args!("{}", self.tx().bit()))
-            .field("rx", &format_args!("{}", self.rx().bit()))
+            .field("tx", &self.tx())
+            .field("rx", &self.rx())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WEIGHT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to config tx arbiter weight function off/on"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_dma/wresp_cnt.rs b/esp32p4/src/axi_dma/wresp_cnt.rs
index 6a64e49036..2533038a91 100644
--- a/esp32p4/src/axi_dma/wresp_cnt.rs
+++ b/esp32p4/src/axi_dma/wresp_cnt.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WRESP_CNT")
-            .field("wresp_cnt", &format_args!("{}", self.wresp_cnt().bits()))
+            .field("wresp_cnt", &self.wresp_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WRESP_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "AXI wr responce cnt register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wresp_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WRESP_CNT_SPEC;
 impl crate::RegisterSpec for WRESP_CNT_SPEC {
diff --git a/esp32p4/src/axi_icm/cmd.rs b/esp32p4/src/axi_icm/cmd.rs
index a99ffa77a9..8f828a1b75 100644
--- a/esp32p4/src/axi_icm/cmd.rs
+++ b/esp32p4/src/axi_icm/cmd.rs
@@ -69,43 +69,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field(
-                "icm_reg_axi_cmd",
-                &format_args!("{}", self.icm_reg_axi_cmd().bits()),
-            )
-            .field(
-                "icm_reg_rd_wr_chan",
-                &format_args!("{}", self.icm_reg_rd_wr_chan().bit()),
-            )
-            .field(
-                "icm_reg_axi_master_port",
-                &format_args!("{}", self.icm_reg_axi_master_port().bits()),
-            )
-            .field(
-                "icm_reg_axi_err_bit",
-                &format_args!("{}", self.icm_reg_axi_err_bit().bit()),
-            )
+            .field("icm_reg_axi_cmd", &self.icm_reg_axi_cmd())
+            .field("icm_reg_rd_wr_chan", &self.icm_reg_rd_wr_chan())
+            .field("icm_reg_axi_master_port", &self.icm_reg_axi_master_port())
+            .field("icm_reg_axi_err_bit", &self.icm_reg_axi_err_bit())
             .field(
                 "icm_reg_axi_soft_reset_bit",
-                &format_args!("{}", self.icm_reg_axi_soft_reset_bit().bit()),
-            )
-            .field(
-                "icm_reg_axi_rd_wr_cmd",
-                &format_args!("{}", self.icm_reg_axi_rd_wr_cmd().bit()),
-            )
-            .field(
-                "icm_reg_axi_cmd_en",
-                &format_args!("{}", self.icm_reg_axi_cmd_en().bit()),
+                &self.icm_reg_axi_soft_reset_bit(),
             )
+            .field("icm_reg_axi_rd_wr_cmd", &self.icm_reg_axi_rd_wr_cmd())
+            .field("icm_reg_axi_cmd_en", &self.icm_reg_axi_cmd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_icm/data.rs b/esp32p4/src/axi_icm/data.rs
index 193f6eaacb..7d36fa4c23 100644
--- a/esp32p4/src/axi_icm/data.rs
+++ b/esp32p4/src/axi_icm/data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field(
-                "icm_reg_data",
-                &format_args!("{}", self.icm_reg_data().bits()),
-            )
+            .field("icm_reg_data", &self.icm_reg_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/axi_icm/hw_cfg.rs b/esp32p4/src/axi_icm/hw_cfg.rs
index d8527127d5..6134b83e28 100644
--- a/esp32p4/src/axi_icm/hw_cfg.rs
+++ b/esp32p4/src/axi_icm/hw_cfg.rs
@@ -85,57 +85,51 @@ impl core::fmt::Debug for R {
         f.debug_struct("HW_CFG")
             .field(
                 "icm_reg_axi_hwcfg_qos_support",
-                &format_args!("{}", self.icm_reg_axi_hwcfg_qos_support().bit()),
+                &self.icm_reg_axi_hwcfg_qos_support(),
             )
             .field(
                 "icm_reg_axi_hwcfg_apb3_support",
-                &format_args!("{}", self.icm_reg_axi_hwcfg_apb3_support().bit()),
+                &self.icm_reg_axi_hwcfg_apb3_support(),
             )
             .field(
                 "icm_reg_axi_hwcfg_axi4_support",
-                &format_args!("{}", self.icm_reg_axi_hwcfg_axi4_support().bit()),
+                &self.icm_reg_axi_hwcfg_axi4_support(),
             )
             .field(
                 "icm_reg_axi_hwcfg_lock_en",
-                &format_args!("{}", self.icm_reg_axi_hwcfg_lock_en().bit()),
+                &self.icm_reg_axi_hwcfg_lock_en(),
             )
             .field(
                 "icm_reg_axi_hwcfg_trust_zone_en",
-                &format_args!("{}", self.icm_reg_axi_hwcfg_trust_zone_en().bit()),
+                &self.icm_reg_axi_hwcfg_trust_zone_en(),
             )
             .field(
                 "icm_reg_axi_hwcfg_decoder_type",
-                &format_args!("{}", self.icm_reg_axi_hwcfg_decoder_type().bit()),
+                &self.icm_reg_axi_hwcfg_decoder_type(),
             )
             .field(
                 "icm_reg_axi_hwcfg_remap_en",
-                &format_args!("{}", self.icm_reg_axi_hwcfg_remap_en().bit()),
+                &self.icm_reg_axi_hwcfg_remap_en(),
             )
             .field(
                 "icm_reg_axi_hwcfg_bi_dir_cmd_en",
-                &format_args!("{}", self.icm_reg_axi_hwcfg_bi_dir_cmd_en().bit()),
+                &self.icm_reg_axi_hwcfg_bi_dir_cmd_en(),
             )
             .field(
                 "icm_reg_axi_hwcfg_low_power_inf_en",
-                &format_args!("{}", self.icm_reg_axi_hwcfg_low_power_inf_en().bit()),
+                &self.icm_reg_axi_hwcfg_low_power_inf_en(),
             )
             .field(
                 "icm_reg_axi_hwcfg_axi_num_masters",
-                &format_args!("{}", self.icm_reg_axi_hwcfg_axi_num_masters().bits()),
+                &self.icm_reg_axi_hwcfg_axi_num_masters(),
             )
             .field(
                 "icm_reg_axi_hwcfg_axi_num_slaves",
-                &format_args!("{}", self.icm_reg_axi_hwcfg_axi_num_slaves().bits()),
+                &self.icm_reg_axi_hwcfg_axi_num_slaves(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HW_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hw_cfg::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HW_CFG_SPEC;
 impl crate::RegisterSpec for HW_CFG_SPEC {
diff --git a/esp32p4/src/axi_icm/verid_fileds.rs b/esp32p4/src/axi_icm/verid_fileds.rs
index 2f6a27fca3..e028a898e3 100644
--- a/esp32p4/src/axi_icm/verid_fileds.rs
+++ b/esp32p4/src/axi_icm/verid_fileds.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERID_FILEDS")
-            .field(
-                "icm_reg_verid",
-                &format_args!("{}", self.icm_reg_verid().bits()),
-            )
+            .field("icm_reg_verid", &self.icm_reg_verid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERID_FILEDS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`verid_fileds::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VERID_FILEDS_SPEC;
 impl crate::RegisterSpec for VERID_FILEDS_SPEC {
diff --git a/esp32p4/src/bitscrambler/rx_ctrl.rs b/esp32p4/src/bitscrambler/rx_ctrl.rs
index e14a844935..c08e9b3969 100644
--- a/esp32p4/src/bitscrambler/rx_ctrl.rs
+++ b/esp32p4/src/bitscrambler/rx_ctrl.rs
@@ -82,32 +82,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CTRL")
-            .field("rx_ena", &format_args!("{}", self.rx_ena().bit()))
-            .field("rx_pause", &format_args!("{}", self.rx_pause().bit()))
-            .field("rx_halt", &format_args!("{}", self.rx_halt().bit()))
-            .field("rx_eof_mode", &format_args!("{}", self.rx_eof_mode().bit()))
-            .field(
-                "rx_cond_mode",
-                &format_args!("{}", self.rx_cond_mode().bit()),
-            )
-            .field(
-                "rx_fetch_mode",
-                &format_args!("{}", self.rx_fetch_mode().bit()),
-            )
-            .field(
-                "rx_halt_mode",
-                &format_args!("{}", self.rx_halt_mode().bit()),
-            )
-            .field("rx_rd_dummy", &format_args!("{}", self.rx_rd_dummy().bit()))
+            .field("rx_ena", &self.rx_ena())
+            .field("rx_pause", &self.rx_pause())
+            .field("rx_halt", &self.rx_halt())
+            .field("rx_eof_mode", &self.rx_eof_mode())
+            .field("rx_cond_mode", &self.rx_cond_mode())
+            .field("rx_fetch_mode", &self.rx_fetch_mode())
+            .field("rx_halt_mode", &self.rx_halt_mode())
+            .field("rx_rd_dummy", &self.rx_rd_dummy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - write this bit to enable the bitscrambler rx"]
     #[inline(always)]
diff --git a/esp32p4/src/bitscrambler/rx_inst_cfg0.rs b/esp32p4/src/bitscrambler/rx_inst_cfg0.rs
index 86c71e6f6d..4587422bbb 100644
--- a/esp32p4/src/bitscrambler/rx_inst_cfg0.rs
+++ b/esp32p4/src/bitscrambler/rx_inst_cfg0.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_INST_CFG0")
-            .field(
-                "rx_inst_idx",
-                &format_args!("{}", self.rx_inst_idx().bits()),
-            )
-            .field(
-                "rx_inst_pos",
-                &format_args!("{}", self.rx_inst_pos().bits()),
-            )
+            .field("rx_inst_idx", &self.rx_inst_idx())
+            .field("rx_inst_pos", &self.rx_inst_pos())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_INST_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - write this bits to specify the one of 8 instruction"]
     #[inline(always)]
diff --git a/esp32p4/src/bitscrambler/rx_inst_cfg1.rs b/esp32p4/src/bitscrambler/rx_inst_cfg1.rs
index 8143ae88f5..e4bf56127a 100644
--- a/esp32p4/src/bitscrambler/rx_inst_cfg1.rs
+++ b/esp32p4/src/bitscrambler/rx_inst_cfg1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_INST_CFG1")
-            .field("rx_inst", &format_args!("{}", self.rx_inst().bits()))
+            .field("rx_inst", &self.rx_inst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_INST_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - write this bits to update instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_RX_INST_CFG0_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/bitscrambler/rx_lut_cfg0.rs b/esp32p4/src/bitscrambler/rx_lut_cfg0.rs
index ece6cb4d75..34925accec 100644
--- a/esp32p4/src/bitscrambler/rx_lut_cfg0.rs
+++ b/esp32p4/src/bitscrambler/rx_lut_cfg0.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_LUT_CFG0")
-            .field("rx_lut_idx", &format_args!("{}", self.rx_lut_idx().bits()))
-            .field(
-                "rx_lut_mode",
-                &format_args!("{}", self.rx_lut_mode().bits()),
-            )
+            .field("rx_lut_idx", &self.rx_lut_idx())
+            .field("rx_lut_mode", &self.rx_lut_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_LUT_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_rx_lut_mode"]
     #[inline(always)]
diff --git a/esp32p4/src/bitscrambler/rx_lut_cfg1.rs b/esp32p4/src/bitscrambler/rx_lut_cfg1.rs
index 8a10877bb6..2c082d89d5 100644
--- a/esp32p4/src/bitscrambler/rx_lut_cfg1.rs
+++ b/esp32p4/src/bitscrambler/rx_lut_cfg1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_LUT_CFG1")
-            .field("rx_lut", &format_args!("{}", self.rx_lut().bits()))
+            .field("rx_lut", &self.rx_lut())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_LUT_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/bitscrambler/rx_state.rs b/esp32p4/src/bitscrambler/rx_state.rs
index b9741fced3..72da6fa221 100644
--- a/esp32p4/src/bitscrambler/rx_state.rs
+++ b/esp32p4/src/bitscrambler/rx_state.rs
@@ -59,31 +59,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_STATE")
-            .field("rx_in_idle", &format_args!("{}", self.rx_in_idle().bit()))
-            .field("rx_in_run", &format_args!("{}", self.rx_in_run().bit()))
-            .field("rx_in_wait", &format_args!("{}", self.rx_in_wait().bit()))
-            .field("rx_in_pause", &format_args!("{}", self.rx_in_pause().bit()))
-            .field(
-                "rx_fifo_full",
-                &format_args!("{}", self.rx_fifo_full().bit()),
-            )
-            .field(
-                "rx_eof_get_cnt",
-                &format_args!("{}", self.rx_eof_get_cnt().bits()),
-            )
-            .field(
-                "rx_eof_overload",
-                &format_args!("{}", self.rx_eof_overload().bit()),
-            )
+            .field("rx_in_idle", &self.rx_in_idle())
+            .field("rx_in_run", &self.rx_in_run())
+            .field("rx_in_wait", &self.rx_in_wait())
+            .field("rx_in_pause", &self.rx_in_pause())
+            .field("rx_fifo_full", &self.rx_fifo_full())
+            .field("rx_eof_get_cnt", &self.rx_eof_get_cnt())
+            .field("rx_eof_overload", &self.rx_eof_overload())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - write this bit to clear reg_bitscrambler_rx_eof_overload and reg_bitscrambler_rx_eof_get_cnt registers"]
     #[inline(always)]
diff --git a/esp32p4/src/bitscrambler/rx_tailing_bits.rs b/esp32p4/src/bitscrambler/rx_tailing_bits.rs
index 6d07af9f13..7c2064fe86 100644
--- a/esp32p4/src/bitscrambler/rx_tailing_bits.rs
+++ b/esp32p4/src/bitscrambler/rx_tailing_bits.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_TAILING_BITS")
-            .field(
-                "rx_tailing_bits",
-                &format_args!("{}", self.rx_tailing_bits().bits()),
-            )
+            .field("rx_tailing_bits", &self.rx_tailing_bits())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_TAILING_BITS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - write this bits to specify the extra data bit length after getting EOF"]
     #[inline(always)]
diff --git a/esp32p4/src/bitscrambler/sys.rs b/esp32p4/src/bitscrambler/sys.rs
index d20f096fb3..6f7b88fd20 100644
--- a/esp32p4/src/bitscrambler/sys.rs
+++ b/esp32p4/src/bitscrambler/sys.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYS")
-            .field("loop_mode", &format_args!("{}", self.loop_mode().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("loop_mode", &self.loop_mode())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - write this bit to set the bitscrambler tx loop back to DMA rx"]
     #[inline(always)]
diff --git a/esp32p4/src/bitscrambler/tx_ctrl.rs b/esp32p4/src/bitscrambler/tx_ctrl.rs
index c8a8ec63b4..6df144cab5 100644
--- a/esp32p4/src/bitscrambler/tx_ctrl.rs
+++ b/esp32p4/src/bitscrambler/tx_ctrl.rs
@@ -82,32 +82,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CTRL")
-            .field("tx_ena", &format_args!("{}", self.tx_ena().bit()))
-            .field("tx_pause", &format_args!("{}", self.tx_pause().bit()))
-            .field("tx_halt", &format_args!("{}", self.tx_halt().bit()))
-            .field("tx_eof_mode", &format_args!("{}", self.tx_eof_mode().bit()))
-            .field(
-                "tx_cond_mode",
-                &format_args!("{}", self.tx_cond_mode().bit()),
-            )
-            .field(
-                "tx_fetch_mode",
-                &format_args!("{}", self.tx_fetch_mode().bit()),
-            )
-            .field(
-                "tx_halt_mode",
-                &format_args!("{}", self.tx_halt_mode().bit()),
-            )
-            .field("tx_rd_dummy", &format_args!("{}", self.tx_rd_dummy().bit()))
+            .field("tx_ena", &self.tx_ena())
+            .field("tx_pause", &self.tx_pause())
+            .field("tx_halt", &self.tx_halt())
+            .field("tx_eof_mode", &self.tx_eof_mode())
+            .field("tx_cond_mode", &self.tx_cond_mode())
+            .field("tx_fetch_mode", &self.tx_fetch_mode())
+            .field("tx_halt_mode", &self.tx_halt_mode())
+            .field("tx_rd_dummy", &self.tx_rd_dummy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - write this bit to enable the bitscrambler tx"]
     #[inline(always)]
diff --git a/esp32p4/src/bitscrambler/tx_inst_cfg0.rs b/esp32p4/src/bitscrambler/tx_inst_cfg0.rs
index e5c077af7e..fb59bbc0d2 100644
--- a/esp32p4/src/bitscrambler/tx_inst_cfg0.rs
+++ b/esp32p4/src/bitscrambler/tx_inst_cfg0.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_INST_CFG0")
-            .field(
-                "tx_inst_idx",
-                &format_args!("{}", self.tx_inst_idx().bits()),
-            )
-            .field(
-                "tx_inst_pos",
-                &format_args!("{}", self.tx_inst_pos().bits()),
-            )
+            .field("tx_inst_idx", &self.tx_inst_idx())
+            .field("tx_inst_pos", &self.tx_inst_pos())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_INST_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - write this bits to specify the one of 8 instruction"]
     #[inline(always)]
diff --git a/esp32p4/src/bitscrambler/tx_inst_cfg1.rs b/esp32p4/src/bitscrambler/tx_inst_cfg1.rs
index c34465c47c..2f07b88b51 100644
--- a/esp32p4/src/bitscrambler/tx_inst_cfg1.rs
+++ b/esp32p4/src/bitscrambler/tx_inst_cfg1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_INST_CFG1")
-            .field("tx_inst", &format_args!("{}", self.tx_inst().bits()))
+            .field("tx_inst", &self.tx_inst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_INST_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - write this bits to update instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by BITSCRAMBLER_TX_INST_CFG0_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/bitscrambler/tx_lut_cfg0.rs b/esp32p4/src/bitscrambler/tx_lut_cfg0.rs
index b6164aac2a..0f81c7a9c8 100644
--- a/esp32p4/src/bitscrambler/tx_lut_cfg0.rs
+++ b/esp32p4/src/bitscrambler/tx_lut_cfg0.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_LUT_CFG0")
-            .field("tx_lut_idx", &format_args!("{}", self.tx_lut_idx().bits()))
-            .field(
-                "tx_lut_mode",
-                &format_args!("{}", self.tx_lut_mode().bits()),
-            )
+            .field("tx_lut_idx", &self.tx_lut_idx())
+            .field("tx_lut_mode", &self.tx_lut_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_LUT_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - write this bits to specify the bytes position of LUT RAM based on reg_bitscrambler_tx_lut_mode"]
     #[inline(always)]
diff --git a/esp32p4/src/bitscrambler/tx_lut_cfg1.rs b/esp32p4/src/bitscrambler/tx_lut_cfg1.rs
index e5a32b79b3..64b95cb5d8 100644
--- a/esp32p4/src/bitscrambler/tx_lut_cfg1.rs
+++ b/esp32p4/src/bitscrambler/tx_lut_cfg1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_LUT_CFG1")
-            .field("tx_lut", &format_args!("{}", self.tx_lut().bits()))
+            .field("tx_lut", &self.tx_lut())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_LUT_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/bitscrambler/tx_state.rs b/esp32p4/src/bitscrambler/tx_state.rs
index f3f3be5089..2f0bf3b07f 100644
--- a/esp32p4/src/bitscrambler/tx_state.rs
+++ b/esp32p4/src/bitscrambler/tx_state.rs
@@ -59,31 +59,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_STATE")
-            .field("tx_in_idle", &format_args!("{}", self.tx_in_idle().bit()))
-            .field("tx_in_run", &format_args!("{}", self.tx_in_run().bit()))
-            .field("tx_in_wait", &format_args!("{}", self.tx_in_wait().bit()))
-            .field("tx_in_pause", &format_args!("{}", self.tx_in_pause().bit()))
-            .field(
-                "tx_fifo_empty",
-                &format_args!("{}", self.tx_fifo_empty().bit()),
-            )
-            .field(
-                "tx_eof_get_cnt",
-                &format_args!("{}", self.tx_eof_get_cnt().bits()),
-            )
-            .field(
-                "tx_eof_overload",
-                &format_args!("{}", self.tx_eof_overload().bit()),
-            )
+            .field("tx_in_idle", &self.tx_in_idle())
+            .field("tx_in_run", &self.tx_in_run())
+            .field("tx_in_wait", &self.tx_in_wait())
+            .field("tx_in_pause", &self.tx_in_pause())
+            .field("tx_fifo_empty", &self.tx_fifo_empty())
+            .field("tx_eof_get_cnt", &self.tx_eof_get_cnt())
+            .field("tx_eof_overload", &self.tx_eof_overload())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - write this bit to clear reg_bitscrambler_tx_eof_overload and reg_bitscrambler_tx_eof_get_cnt registers"]
     #[inline(always)]
diff --git a/esp32p4/src/bitscrambler/tx_tailing_bits.rs b/esp32p4/src/bitscrambler/tx_tailing_bits.rs
index dbbb98b9b8..28d674ae0d 100644
--- a/esp32p4/src/bitscrambler/tx_tailing_bits.rs
+++ b/esp32p4/src/bitscrambler/tx_tailing_bits.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_TAILING_BITS")
-            .field(
-                "tx_tailing_bits",
-                &format_args!("{}", self.tx_tailing_bits().bits()),
-            )
+            .field("tx_tailing_bits", &self.tx_tailing_bits())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_TAILING_BITS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - write this bits to specify the extra data bit length after getting EOF"]
     #[inline(always)]
diff --git a/esp32p4/src/bitscrambler/version.rs b/esp32p4/src/bitscrambler/version.rs
index c7347a0a03..1aae26fd40 100644
--- a/esp32p4/src/bitscrambler/version.rs
+++ b/esp32p4/src/bitscrambler/version.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field(
-                "bitscrambler_ver",
-                &format_args!("{}", self.bitscrambler_ver().bits()),
-            )
+            .field("bitscrambler_ver", &self.bitscrambler_ver())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/clock_gate.rs b/esp32p4/src/cache/clock_gate.rs
index 9396387567..1798054b1a 100644
--- a/esp32p4/src/cache/clock_gate.rs
+++ b/esp32p4/src/cache/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable clock gate when access all registers in this module."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/date.rs b/esp32p4/src/cache/date.rs
index ba0bd097c1..71e2991e1d 100644
--- a/esp32p4/src/cache/date.rs
+++ b/esp32p4/src/cache/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/cache/l1_bypass_cache_conf.rs b/esp32p4/src/cache/l1_bypass_cache_conf.rs
index 700dfb5075..36b987f9f8 100644
--- a/esp32p4/src/cache/l1_bypass_cache_conf.rs
+++ b/esp32p4/src/cache/l1_bypass_cache_conf.rs
@@ -49,35 +49,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_BYPASS_CACHE_CONF")
-            .field(
-                "bypass_l1_icache0_en",
-                &format_args!("{}", self.bypass_l1_icache0_en().bit()),
-            )
-            .field(
-                "bypass_l1_icache1_en",
-                &format_args!("{}", self.bypass_l1_icache1_en().bit()),
-            )
-            .field(
-                "bypass_l1_icache2_en",
-                &format_args!("{}", self.bypass_l1_icache2_en().bit()),
-            )
-            .field(
-                "bypass_l1_icache3_en",
-                &format_args!("{}", self.bypass_l1_icache3_en().bit()),
-            )
-            .field(
-                "bypass_l1_dcache_en",
-                &format_args!("{}", self.bypass_l1_dcache_en().bit()),
-            )
+            .field("bypass_l1_icache0_en", &self.bypass_l1_icache0_en())
+            .field("bypass_l1_icache1_en", &self.bypass_l1_icache1_en())
+            .field("bypass_l1_icache2_en", &self.bypass_l1_icache2_en())
+            .field("bypass_l1_icache3_en", &self.bypass_l1_icache3_en())
+            .field("bypass_l1_dcache_en", &self.bypass_l1_dcache_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_BYPASS_CACHE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_acs_cnt_ctrl.rs b/esp32p4/src/cache/l1_cache_acs_cnt_ctrl.rs
index 68e08639ef..28c9c68d9a 100644
--- a/esp32p4/src/cache/l1_cache_acs_cnt_ctrl.rs
+++ b/esp32p4/src/cache/l1_cache_acs_cnt_ctrl.rs
@@ -108,63 +108,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_CNT_CTRL")
-            .field(
-                "l1_ibus0_cnt_ena",
-                &format_args!("{}", self.l1_ibus0_cnt_ena().bit()),
-            )
-            .field(
-                "l1_ibus1_cnt_ena",
-                &format_args!("{}", self.l1_ibus1_cnt_ena().bit()),
-            )
-            .field(
-                "l1_ibus2_cnt_ena",
-                &format_args!("{}", self.l1_ibus2_cnt_ena().bit()),
-            )
-            .field(
-                "l1_ibus3_cnt_ena",
-                &format_args!("{}", self.l1_ibus3_cnt_ena().bit()),
-            )
-            .field(
-                "l1_dbus0_cnt_ena",
-                &format_args!("{}", self.l1_dbus0_cnt_ena().bit()),
-            )
-            .field(
-                "l1_dbus1_cnt_ena",
-                &format_args!("{}", self.l1_dbus1_cnt_ena().bit()),
-            )
-            .field(
-                "l1_dbus2_cnt_ena",
-                &format_args!("{}", self.l1_dbus2_cnt_ena().bit()),
-            )
-            .field(
-                "l1_dbus3_cnt_ena",
-                &format_args!("{}", self.l1_dbus3_cnt_ena().bit()),
-            )
-            .field(
-                "l1_ibus2_cnt_clr",
-                &format_args!("{}", self.l1_ibus2_cnt_clr().bit()),
-            )
-            .field(
-                "l1_ibus3_cnt_clr",
-                &format_args!("{}", self.l1_ibus3_cnt_clr().bit()),
-            )
-            .field(
-                "l1_dbus2_cnt_clr",
-                &format_args!("{}", self.l1_dbus2_cnt_clr().bit()),
-            )
-            .field(
-                "l1_dbus3_cnt_clr",
-                &format_args!("{}", self.l1_dbus3_cnt_clr().bit()),
-            )
+            .field("l1_ibus0_cnt_ena", &self.l1_ibus0_cnt_ena())
+            .field("l1_ibus1_cnt_ena", &self.l1_ibus1_cnt_ena())
+            .field("l1_ibus2_cnt_ena", &self.l1_ibus2_cnt_ena())
+            .field("l1_ibus3_cnt_ena", &self.l1_ibus3_cnt_ena())
+            .field("l1_dbus0_cnt_ena", &self.l1_dbus0_cnt_ena())
+            .field("l1_dbus1_cnt_ena", &self.l1_dbus1_cnt_ena())
+            .field("l1_dbus2_cnt_ena", &self.l1_dbus2_cnt_ena())
+            .field("l1_dbus3_cnt_ena", &self.l1_dbus3_cnt_ena())
+            .field("l1_ibus2_cnt_clr", &self.l1_ibus2_cnt_clr())
+            .field("l1_ibus3_cnt_clr", &self.l1_ibus3_cnt_clr())
+            .field("l1_dbus2_cnt_clr", &self.l1_dbus2_cnt_clr())
+            .field("l1_dbus3_cnt_clr", &self.l1_dbus3_cnt_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_CNT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable ibus0 counter in L1-ICache0."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_acs_cnt_int_clr.rs b/esp32p4/src/cache/l1_cache_acs_cnt_int_clr.rs
index 0160bd7aef..a68f017e68 100644
--- a/esp32p4/src/cache/l1_cache_acs_cnt_int_clr.rs
+++ b/esp32p4/src/cache/l1_cache_acs_cnt_int_clr.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_CNT_INT_CLR")
-            .field(
-                "l1_ibus2_ovf_int_clr",
-                &format_args!("{}", self.l1_ibus2_ovf_int_clr().bit()),
-            )
-            .field(
-                "l1_ibus3_ovf_int_clr",
-                &format_args!("{}", self.l1_ibus3_ovf_int_clr().bit()),
-            )
-            .field(
-                "l1_dbus2_ovf_int_clr",
-                &format_args!("{}", self.l1_dbus2_ovf_int_clr().bit()),
-            )
-            .field(
-                "l1_dbus3_ovf_int_clr",
-                &format_args!("{}", self.l1_dbus3_ovf_int_clr().bit()),
-            )
+            .field("l1_ibus2_ovf_int_clr", &self.l1_ibus2_ovf_int_clr())
+            .field("l1_ibus3_ovf_int_clr", &self.l1_ibus3_ovf_int_clr())
+            .field("l1_dbus2_ovf_int_clr", &self.l1_dbus2_ovf_int_clr())
+            .field("l1_dbus3_ovf_int_clr", &self.l1_dbus3_ovf_int_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_CNT_INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due to bus0 accesses L1-ICache0."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_acs_cnt_int_ena.rs b/esp32p4/src/cache/l1_cache_acs_cnt_int_ena.rs
index 94c791142e..1f05b668e5 100644
--- a/esp32p4/src/cache/l1_cache_acs_cnt_int_ena.rs
+++ b/esp32p4/src/cache/l1_cache_acs_cnt_int_ena.rs
@@ -72,47 +72,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_CNT_INT_ENA")
-            .field(
-                "l1_ibus0_ovf_int_ena",
-                &format_args!("{}", self.l1_ibus0_ovf_int_ena().bit()),
-            )
-            .field(
-                "l1_ibus1_ovf_int_ena",
-                &format_args!("{}", self.l1_ibus1_ovf_int_ena().bit()),
-            )
-            .field(
-                "l1_ibus2_ovf_int_ena",
-                &format_args!("{}", self.l1_ibus2_ovf_int_ena().bit()),
-            )
-            .field(
-                "l1_ibus3_ovf_int_ena",
-                &format_args!("{}", self.l1_ibus3_ovf_int_ena().bit()),
-            )
-            .field(
-                "l1_dbus0_ovf_int_ena",
-                &format_args!("{}", self.l1_dbus0_ovf_int_ena().bit()),
-            )
-            .field(
-                "l1_dbus1_ovf_int_ena",
-                &format_args!("{}", self.l1_dbus1_ovf_int_ena().bit()),
-            )
-            .field(
-                "l1_dbus2_ovf_int_ena",
-                &format_args!("{}", self.l1_dbus2_ovf_int_ena().bit()),
-            )
-            .field(
-                "l1_dbus3_ovf_int_ena",
-                &format_args!("{}", self.l1_dbus3_ovf_int_ena().bit()),
-            )
+            .field("l1_ibus0_ovf_int_ena", &self.l1_ibus0_ovf_int_ena())
+            .field("l1_ibus1_ovf_int_ena", &self.l1_ibus1_ovf_int_ena())
+            .field("l1_ibus2_ovf_int_ena", &self.l1_ibus2_ovf_int_ena())
+            .field("l1_ibus3_ovf_int_ena", &self.l1_ibus3_ovf_int_ena())
+            .field("l1_dbus0_ovf_int_ena", &self.l1_dbus0_ovf_int_ena())
+            .field("l1_dbus1_ovf_int_ena", &self.l1_dbus1_ovf_int_ena())
+            .field("l1_dbus2_ovf_int_ena", &self.l1_dbus2_ovf_int_ena())
+            .field("l1_dbus3_ovf_int_ena", &self.l1_dbus3_ovf_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_CNT_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_acs_cnt_int_raw.rs b/esp32p4/src/cache/l1_cache_acs_cnt_int_raw.rs
index 5250a0216e..a37f296f16 100644
--- a/esp32p4/src/cache/l1_cache_acs_cnt_int_raw.rs
+++ b/esp32p4/src/cache/l1_cache_acs_cnt_int_raw.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_CNT_INT_RAW")
-            .field(
-                "l1_ibus0_ovf_int_raw",
-                &format_args!("{}", self.l1_ibus0_ovf_int_raw().bit()),
-            )
-            .field(
-                "l1_ibus1_ovf_int_raw",
-                &format_args!("{}", self.l1_ibus1_ovf_int_raw().bit()),
-            )
-            .field(
-                "l1_ibus2_ovf_int_raw",
-                &format_args!("{}", self.l1_ibus2_ovf_int_raw().bit()),
-            )
-            .field(
-                "l1_ibus3_ovf_int_raw",
-                &format_args!("{}", self.l1_ibus3_ovf_int_raw().bit()),
-            )
-            .field(
-                "l1_dbus0_ovf_int_raw",
-                &format_args!("{}", self.l1_dbus0_ovf_int_raw().bit()),
-            )
-            .field(
-                "l1_dbus1_ovf_int_raw",
-                &format_args!("{}", self.l1_dbus1_ovf_int_raw().bit()),
-            )
-            .field(
-                "l1_dbus2_ovf_int_raw",
-                &format_args!("{}", self.l1_dbus2_ovf_int_raw().bit()),
-            )
-            .field(
-                "l1_dbus3_ovf_int_raw",
-                &format_args!("{}", self.l1_dbus3_ovf_int_raw().bit()),
-            )
+            .field("l1_ibus0_ovf_int_raw", &self.l1_ibus0_ovf_int_raw())
+            .field("l1_ibus1_ovf_int_raw", &self.l1_ibus1_ovf_int_raw())
+            .field("l1_ibus2_ovf_int_raw", &self.l1_ibus2_ovf_int_raw())
+            .field("l1_ibus3_ovf_int_raw", &self.l1_ibus3_ovf_int_raw())
+            .field("l1_dbus0_ovf_int_raw", &self.l1_dbus0_ovf_int_raw())
+            .field("l1_dbus1_ovf_int_raw", &self.l1_dbus1_ovf_int_raw())
+            .field("l1_dbus2_ovf_int_raw", &self.l1_dbus2_ovf_int_raw())
+            .field("l1_dbus3_ovf_int_raw", &self.l1_dbus3_ovf_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_CNT_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_acs_cnt_int_st.rs b/esp32p4/src/cache/l1_cache_acs_cnt_int_st.rs
index d5a47f708c..aa93cd73dd 100644
--- a/esp32p4/src/cache/l1_cache_acs_cnt_int_st.rs
+++ b/esp32p4/src/cache/l1_cache_acs_cnt_int_st.rs
@@ -62,47 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_CNT_INT_ST")
-            .field(
-                "l1_ibus0_ovf_int_st",
-                &format_args!("{}", self.l1_ibus0_ovf_int_st().bit()),
-            )
-            .field(
-                "l1_ibus1_ovf_int_st",
-                &format_args!("{}", self.l1_ibus1_ovf_int_st().bit()),
-            )
-            .field(
-                "l1_ibus2_ovf_int_st",
-                &format_args!("{}", self.l1_ibus2_ovf_int_st().bit()),
-            )
-            .field(
-                "l1_ibus3_ovf_int_st",
-                &format_args!("{}", self.l1_ibus3_ovf_int_st().bit()),
-            )
-            .field(
-                "l1_dbus0_ovf_int_st",
-                &format_args!("{}", self.l1_dbus0_ovf_int_st().bit()),
-            )
-            .field(
-                "l1_dbus1_ovf_int_st",
-                &format_args!("{}", self.l1_dbus1_ovf_int_st().bit()),
-            )
-            .field(
-                "l1_dbus2_ovf_int_st",
-                &format_args!("{}", self.l1_dbus2_ovf_int_st().bit()),
-            )
-            .field(
-                "l1_dbus3_ovf_int_st",
-                &format_args!("{}", self.l1_dbus3_ovf_int_st().bit()),
-            )
+            .field("l1_ibus0_ovf_int_st", &self.l1_ibus0_ovf_int_st())
+            .field("l1_ibus1_ovf_int_st", &self.l1_ibus1_ovf_int_st())
+            .field("l1_ibus2_ovf_int_st", &self.l1_ibus2_ovf_int_st())
+            .field("l1_ibus3_ovf_int_st", &self.l1_ibus3_ovf_int_st())
+            .field("l1_dbus0_ovf_int_st", &self.l1_dbus0_ovf_int_st())
+            .field("l1_dbus1_ovf_int_st", &self.l1_dbus1_ovf_int_st())
+            .field("l1_dbus2_ovf_int_st", &self.l1_dbus2_ovf_int_st())
+            .field("l1_dbus3_ovf_int_st", &self.l1_dbus3_ovf_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_CNT_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Access Counter Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_cnt_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_CACHE_ACS_CNT_INT_ST_SPEC;
 impl crate::RegisterSpec for L1_CACHE_ACS_CNT_INT_ST_SPEC {
diff --git a/esp32p4/src/cache/l1_cache_acs_fail_ctrl.rs b/esp32p4/src/cache/l1_cache_acs_fail_ctrl.rs
index d7c850e2a0..8ed2dfc6c3 100644
--- a/esp32p4/src/cache/l1_cache_acs_fail_ctrl.rs
+++ b/esp32p4/src/cache/l1_cache_acs_fail_ctrl.rs
@@ -55,33 +55,27 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_ACS_FAIL_CTRL")
             .field(
                 "l1_icache0_acs_fail_check_mode",
-                &format_args!("{}", self.l1_icache0_acs_fail_check_mode().bit()),
+                &self.l1_icache0_acs_fail_check_mode(),
             )
             .field(
                 "l1_icache1_acs_fail_check_mode",
-                &format_args!("{}", self.l1_icache1_acs_fail_check_mode().bit()),
+                &self.l1_icache1_acs_fail_check_mode(),
             )
             .field(
                 "l1_icache2_acs_fail_check_mode",
-                &format_args!("{}", self.l1_icache2_acs_fail_check_mode().bit()),
+                &self.l1_icache2_acs_fail_check_mode(),
             )
             .field(
                 "l1_icache3_acs_fail_check_mode",
-                &format_args!("{}", self.l1_icache3_acs_fail_check_mode().bit()),
+                &self.l1_icache3_acs_fail_check_mode(),
             )
             .field(
                 "l1_dcache_acs_fail_check_mode",
-                &format_args!("{}", self.l1_dcache_acs_fail_check_mode().bit()),
+                &self.l1_dcache_acs_fail_check_mode(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_FAIL_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to configure l1 icache0 access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_acs_fail_int_clr.rs b/esp32p4/src/cache/l1_cache_acs_fail_int_clr.rs
index 6591996cd7..7ee175d4f7 100644
--- a/esp32p4/src/cache/l1_cache_acs_fail_int_clr.rs
+++ b/esp32p4/src/cache/l1_cache_acs_fail_int_clr.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_FAIL_INT_CLR")
-            .field(
-                "l1_icache2_fail_int_clr",
-                &format_args!("{}", self.l1_icache2_fail_int_clr().bit()),
-            )
-            .field(
-                "l1_icache3_fail_int_clr",
-                &format_args!("{}", self.l1_icache3_fail_int_clr().bit()),
-            )
+            .field("l1_icache2_fail_int_clr", &self.l1_icache2_fail_int_clr())
+            .field("l1_icache3_fail_int_clr", &self.l1_icache3_fail_int_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_FAIL_INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_acs_fail_int_ena.rs b/esp32p4/src/cache/l1_cache_acs_fail_int_ena.rs
index 0378b48e37..12f63617ed 100644
--- a/esp32p4/src/cache/l1_cache_acs_fail_int_ena.rs
+++ b/esp32p4/src/cache/l1_cache_acs_fail_int_ena.rs
@@ -49,35 +49,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_FAIL_INT_ENA")
-            .field(
-                "l1_icache0_fail_int_ena",
-                &format_args!("{}", self.l1_icache0_fail_int_ena().bit()),
-            )
-            .field(
-                "l1_icache1_fail_int_ena",
-                &format_args!("{}", self.l1_icache1_fail_int_ena().bit()),
-            )
-            .field(
-                "l1_icache2_fail_int_ena",
-                &format_args!("{}", self.l1_icache2_fail_int_ena().bit()),
-            )
-            .field(
-                "l1_icache3_fail_int_ena",
-                &format_args!("{}", self.l1_icache3_fail_int_ena().bit()),
-            )
-            .field(
-                "l1_dcache_fail_int_ena",
-                &format_args!("{}", self.l1_dcache_fail_int_ena().bit()),
-            )
+            .field("l1_icache0_fail_int_ena", &self.l1_icache0_fail_int_ena())
+            .field("l1_icache1_fail_int_ena", &self.l1_icache1_fail_int_ena())
+            .field("l1_icache2_fail_int_ena", &self.l1_icache2_fail_int_ena())
+            .field("l1_icache3_fail_int_ena", &self.l1_icache3_fail_int_ena())
+            .field("l1_dcache_fail_int_ena", &self.l1_dcache_fail_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_FAIL_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_acs_fail_int_raw.rs b/esp32p4/src/cache/l1_cache_acs_fail_int_raw.rs
index 7c0a85ebc1..d5b285f0e6 100644
--- a/esp32p4/src/cache/l1_cache_acs_fail_int_raw.rs
+++ b/esp32p4/src/cache/l1_cache_acs_fail_int_raw.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_FAIL_INT_RAW")
-            .field(
-                "l1_icache0_fail_int_raw",
-                &format_args!("{}", self.l1_icache0_fail_int_raw().bit()),
-            )
-            .field(
-                "l1_icache1_fail_int_raw",
-                &format_args!("{}", self.l1_icache1_fail_int_raw().bit()),
-            )
-            .field(
-                "l1_icache2_fail_int_raw",
-                &format_args!("{}", self.l1_icache2_fail_int_raw().bit()),
-            )
-            .field(
-                "l1_icache3_fail_int_raw",
-                &format_args!("{}", self.l1_icache3_fail_int_raw().bit()),
-            )
-            .field(
-                "l1_dcache_fail_int_raw",
-                &format_args!("{}", self.l1_dcache_fail_int_raw().bit()),
-            )
+            .field("l1_icache0_fail_int_raw", &self.l1_icache0_fail_int_raw())
+            .field("l1_icache1_fail_int_raw", &self.l1_icache1_fail_int_raw())
+            .field("l1_icache2_fail_int_raw", &self.l1_icache2_fail_int_raw())
+            .field("l1_icache3_fail_int_raw", &self.l1_icache3_fail_int_raw())
+            .field("l1_dcache_fail_int_raw", &self.l1_dcache_fail_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_FAIL_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw bit of the interrupt of access fail that occurs in L1-ICache0."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_acs_fail_int_st.rs b/esp32p4/src/cache/l1_cache_acs_fail_int_st.rs
index 56c5c94563..3d16090211 100644
--- a/esp32p4/src/cache/l1_cache_acs_fail_int_st.rs
+++ b/esp32p4/src/cache/l1_cache_acs_fail_int_st.rs
@@ -41,35 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ACS_FAIL_INT_ST")
-            .field(
-                "l1_icache0_fail_int_st",
-                &format_args!("{}", self.l1_icache0_fail_int_st().bit()),
-            )
-            .field(
-                "l1_icache1_fail_int_st",
-                &format_args!("{}", self.l1_icache1_fail_int_st().bit()),
-            )
-            .field(
-                "l1_icache2_fail_int_st",
-                &format_args!("{}", self.l1_icache2_fail_int_st().bit()),
-            )
-            .field(
-                "l1_icache3_fail_int_st",
-                &format_args!("{}", self.l1_icache3_fail_int_st().bit()),
-            )
-            .field(
-                "l1_dcache_fail_int_st",
-                &format_args!("{}", self.l1_dcache_fail_int_st().bit()),
-            )
+            .field("l1_icache0_fail_int_st", &self.l1_icache0_fail_int_st())
+            .field("l1_icache1_fail_int_st", &self.l1_icache1_fail_int_st())
+            .field("l1_icache2_fail_int_st", &self.l1_icache2_fail_int_st())
+            .field("l1_icache3_fail_int_st", &self.l1_icache3_fail_int_st())
+            .field("l1_dcache_fail_int_st", &self.l1_dcache_fail_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ACS_FAIL_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_cache_acs_fail_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_CACHE_ACS_FAIL_INT_ST_SPEC;
 impl crate::RegisterSpec for L1_CACHE_ACS_FAIL_INT_ST_SPEC {
diff --git a/esp32p4/src/cache/l1_cache_atomic_conf.rs b/esp32p4/src/cache/l1_cache_atomic_conf.rs
index bebdcf4cea..12dd360e3e 100644
--- a/esp32p4/src/cache/l1_cache_atomic_conf.rs
+++ b/esp32p4/src/cache/l1_cache_atomic_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_ATOMIC_CONF")
-            .field(
-                "l1_dcache_atomic_en",
-                &format_args!("{}", self.l1_dcache_atomic_en().bit()),
-            )
+            .field("l1_dcache_atomic_en", &self.l1_dcache_atomic_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_ATOMIC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable atomic feature on L1-DCache when multiple cores access L1-DCache. 1: disable, 1: enable."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_autoload_buf_clr_ctrl.rs b/esp32p4/src/cache/l1_cache_autoload_buf_clr_ctrl.rs
index 9b9a715842..8490bcbd5c 100644
--- a/esp32p4/src/cache/l1_cache_autoload_buf_clr_ctrl.rs
+++ b/esp32p4/src/cache/l1_cache_autoload_buf_clr_ctrl.rs
@@ -49,35 +49,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_AUTOLOAD_BUF_CLR_CTRL")
-            .field(
-                "l1_icache0_ald_buf_clr",
-                &format_args!("{}", self.l1_icache0_ald_buf_clr().bit()),
-            )
-            .field(
-                "l1_icache1_ald_buf_clr",
-                &format_args!("{}", self.l1_icache1_ald_buf_clr().bit()),
-            )
-            .field(
-                "l1_icache2_ald_buf_clr",
-                &format_args!("{}", self.l1_icache2_ald_buf_clr().bit()),
-            )
-            .field(
-                "l1_icache3_ald_buf_clr",
-                &format_args!("{}", self.l1_icache3_ald_buf_clr().bit()),
-            )
-            .field(
-                "l1_dcache_ald_buf_clr",
-                &format_args!("{}", self.l1_dcache_ald_buf_clr().bit()),
-            )
+            .field("l1_icache0_ald_buf_clr", &self.l1_icache0_ald_buf_clr())
+            .field("l1_icache1_ald_buf_clr", &self.l1_icache1_ald_buf_clr())
+            .field("l1_icache2_ald_buf_clr", &self.l1_icache2_ald_buf_clr())
+            .field("l1_icache3_ald_buf_clr", &self.l1_icache3_ald_buf_clr())
+            .field("l1_dcache_ald_buf_clr", &self.l1_dcache_ald_buf_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, autoload will not work in L1-ICache0. This bit should not be active when autoload works in L1-ICache0."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_data_mem_acs_conf.rs b/esp32p4/src/cache/l1_cache_data_mem_acs_conf.rs
index 328eeca353..9cf83e1207 100644
--- a/esp32p4/src/cache/l1_cache_data_mem_acs_conf.rs
+++ b/esp32p4/src/cache/l1_cache_data_mem_acs_conf.rs
@@ -92,53 +92,41 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_DATA_MEM_ACS_CONF")
             .field(
                 "l1_icache0_data_mem_rd_en",
-                &format_args!("{}", self.l1_icache0_data_mem_rd_en().bit()),
+                &self.l1_icache0_data_mem_rd_en(),
             )
             .field(
                 "l1_icache0_data_mem_wr_en",
-                &format_args!("{}", self.l1_icache0_data_mem_wr_en().bit()),
+                &self.l1_icache0_data_mem_wr_en(),
             )
             .field(
                 "l1_icache1_data_mem_rd_en",
-                &format_args!("{}", self.l1_icache1_data_mem_rd_en().bit()),
+                &self.l1_icache1_data_mem_rd_en(),
             )
             .field(
                 "l1_icache1_data_mem_wr_en",
-                &format_args!("{}", self.l1_icache1_data_mem_wr_en().bit()),
+                &self.l1_icache1_data_mem_wr_en(),
             )
             .field(
                 "l1_icache2_data_mem_rd_en",
-                &format_args!("{}", self.l1_icache2_data_mem_rd_en().bit()),
+                &self.l1_icache2_data_mem_rd_en(),
             )
             .field(
                 "l1_icache2_data_mem_wr_en",
-                &format_args!("{}", self.l1_icache2_data_mem_wr_en().bit()),
+                &self.l1_icache2_data_mem_wr_en(),
             )
             .field(
                 "l1_icache3_data_mem_rd_en",
-                &format_args!("{}", self.l1_icache3_data_mem_rd_en().bit()),
+                &self.l1_icache3_data_mem_rd_en(),
             )
             .field(
                 "l1_icache3_data_mem_wr_en",
-                &format_args!("{}", self.l1_icache3_data_mem_wr_en().bit()),
-            )
-            .field(
-                "l1_dcache_data_mem_rd_en",
-                &format_args!("{}", self.l1_dcache_data_mem_rd_en().bit()),
-            )
-            .field(
-                "l1_dcache_data_mem_wr_en",
-                &format_args!("{}", self.l1_dcache_data_mem_wr_en().bit()),
+                &self.l1_icache3_data_mem_wr_en(),
             )
+            .field("l1_dcache_data_mem_rd_en", &self.l1_dcache_data_mem_rd_en())
+            .field("l1_dcache_data_mem_wr_en", &self.l1_dcache_data_mem_wr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_DATA_MEM_ACS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_data_mem_power_ctrl.rs b/esp32p4/src/cache/l1_cache_data_mem_power_ctrl.rs
index d718a8dfb3..b0c064fdcb 100644
--- a/esp32p4/src/cache/l1_cache_data_mem_power_ctrl.rs
+++ b/esp32p4/src/cache/l1_cache_data_mem_power_ctrl.rs
@@ -133,73 +133,67 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_DATA_MEM_POWER_CTRL")
             .field(
                 "l1_icache0_data_mem_force_on",
-                &format_args!("{}", self.l1_icache0_data_mem_force_on().bit()),
+                &self.l1_icache0_data_mem_force_on(),
             )
             .field(
                 "l1_icache0_data_mem_force_pd",
-                &format_args!("{}", self.l1_icache0_data_mem_force_pd().bit()),
+                &self.l1_icache0_data_mem_force_pd(),
             )
             .field(
                 "l1_icache0_data_mem_force_pu",
-                &format_args!("{}", self.l1_icache0_data_mem_force_pu().bit()),
+                &self.l1_icache0_data_mem_force_pu(),
             )
             .field(
                 "l1_icache1_data_mem_force_on",
-                &format_args!("{}", self.l1_icache1_data_mem_force_on().bit()),
+                &self.l1_icache1_data_mem_force_on(),
             )
             .field(
                 "l1_icache1_data_mem_force_pd",
-                &format_args!("{}", self.l1_icache1_data_mem_force_pd().bit()),
+                &self.l1_icache1_data_mem_force_pd(),
             )
             .field(
                 "l1_icache1_data_mem_force_pu",
-                &format_args!("{}", self.l1_icache1_data_mem_force_pu().bit()),
+                &self.l1_icache1_data_mem_force_pu(),
             )
             .field(
                 "l1_icache2_data_mem_force_on",
-                &format_args!("{}", self.l1_icache2_data_mem_force_on().bit()),
+                &self.l1_icache2_data_mem_force_on(),
             )
             .field(
                 "l1_icache2_data_mem_force_pd",
-                &format_args!("{}", self.l1_icache2_data_mem_force_pd().bit()),
+                &self.l1_icache2_data_mem_force_pd(),
             )
             .field(
                 "l1_icache2_data_mem_force_pu",
-                &format_args!("{}", self.l1_icache2_data_mem_force_pu().bit()),
+                &self.l1_icache2_data_mem_force_pu(),
             )
             .field(
                 "l1_icache3_data_mem_force_on",
-                &format_args!("{}", self.l1_icache3_data_mem_force_on().bit()),
+                &self.l1_icache3_data_mem_force_on(),
             )
             .field(
                 "l1_icache3_data_mem_force_pd",
-                &format_args!("{}", self.l1_icache3_data_mem_force_pd().bit()),
+                &self.l1_icache3_data_mem_force_pd(),
             )
             .field(
                 "l1_icache3_data_mem_force_pu",
-                &format_args!("{}", self.l1_icache3_data_mem_force_pu().bit()),
+                &self.l1_icache3_data_mem_force_pu(),
             )
             .field(
                 "l1_dcache_data_mem_force_on",
-                &format_args!("{}", self.l1_dcache_data_mem_force_on().bit()),
+                &self.l1_dcache_data_mem_force_on(),
             )
             .field(
                 "l1_dcache_data_mem_force_pd",
-                &format_args!("{}", self.l1_dcache_data_mem_force_pd().bit()),
+                &self.l1_dcache_data_mem_force_pd(),
             )
             .field(
                 "l1_dcache_data_mem_force_pu",
-                &format_args!("{}", self.l1_dcache_data_mem_force_pu().bit()),
+                &self.l1_dcache_data_mem_force_pu(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_DATA_MEM_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_debug_bus.rs b/esp32p4/src/cache/l1_cache_debug_bus.rs
index 49ae0dcb0e..934f1e4940 100644
--- a/esp32p4/src/cache/l1_cache_debug_bus.rs
+++ b/esp32p4/src/cache/l1_cache_debug_bus.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_DEBUG_BUS")
-            .field(
-                "l1_cache_debug_bus",
-                &format_args!("{}", self.l1_cache_debug_bus().bits()),
-            )
+            .field("l1_cache_debug_bus", &self.l1_cache_debug_bus())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_DEBUG_BUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_freeze_ctrl.rs b/esp32p4/src/cache/l1_cache_freeze_ctrl.rs
index 1d20b87343..6c6cbd30a2 100644
--- a/esp32p4/src/cache/l1_cache_freeze_ctrl.rs
+++ b/esp32p4/src/cache/l1_cache_freeze_ctrl.rs
@@ -125,75 +125,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_FREEZE_CTRL")
-            .field(
-                "l1_icache0_freeze_en",
-                &format_args!("{}", self.l1_icache0_freeze_en().bit()),
-            )
-            .field(
-                "l1_icache0_freeze_mode",
-                &format_args!("{}", self.l1_icache0_freeze_mode().bit()),
-            )
-            .field(
-                "l1_icache0_freeze_done",
-                &format_args!("{}", self.l1_icache0_freeze_done().bit()),
-            )
-            .field(
-                "l1_icache1_freeze_en",
-                &format_args!("{}", self.l1_icache1_freeze_en().bit()),
-            )
-            .field(
-                "l1_icache1_freeze_mode",
-                &format_args!("{}", self.l1_icache1_freeze_mode().bit()),
-            )
-            .field(
-                "l1_icache1_freeze_done",
-                &format_args!("{}", self.l1_icache1_freeze_done().bit()),
-            )
-            .field(
-                "l1_icache2_freeze_en",
-                &format_args!("{}", self.l1_icache2_freeze_en().bit()),
-            )
-            .field(
-                "l1_icache2_freeze_mode",
-                &format_args!("{}", self.l1_icache2_freeze_mode().bit()),
-            )
-            .field(
-                "l1_icache2_freeze_done",
-                &format_args!("{}", self.l1_icache2_freeze_done().bit()),
-            )
-            .field(
-                "l1_icache3_freeze_en",
-                &format_args!("{}", self.l1_icache3_freeze_en().bit()),
-            )
-            .field(
-                "l1_icache3_freeze_mode",
-                &format_args!("{}", self.l1_icache3_freeze_mode().bit()),
-            )
-            .field(
-                "l1_icache3_freeze_done",
-                &format_args!("{}", self.l1_icache3_freeze_done().bit()),
-            )
-            .field(
-                "l1_dcache_freeze_en",
-                &format_args!("{}", self.l1_dcache_freeze_en().bit()),
-            )
-            .field(
-                "l1_dcache_freeze_mode",
-                &format_args!("{}", self.l1_dcache_freeze_mode().bit()),
-            )
-            .field(
-                "l1_dcache_freeze_done",
-                &format_args!("{}", self.l1_dcache_freeze_done().bit()),
-            )
+            .field("l1_icache0_freeze_en", &self.l1_icache0_freeze_en())
+            .field("l1_icache0_freeze_mode", &self.l1_icache0_freeze_mode())
+            .field("l1_icache0_freeze_done", &self.l1_icache0_freeze_done())
+            .field("l1_icache1_freeze_en", &self.l1_icache1_freeze_en())
+            .field("l1_icache1_freeze_mode", &self.l1_icache1_freeze_mode())
+            .field("l1_icache1_freeze_done", &self.l1_icache1_freeze_done())
+            .field("l1_icache2_freeze_en", &self.l1_icache2_freeze_en())
+            .field("l1_icache2_freeze_mode", &self.l1_icache2_freeze_mode())
+            .field("l1_icache2_freeze_done", &self.l1_icache2_freeze_done())
+            .field("l1_icache3_freeze_en", &self.l1_icache3_freeze_en())
+            .field("l1_icache3_freeze_mode", &self.l1_icache3_freeze_mode())
+            .field("l1_icache3_freeze_done", &self.l1_icache3_freeze_done())
+            .field("l1_dcache_freeze_en", &self.l1_dcache_freeze_en())
+            .field("l1_dcache_freeze_mode", &self.l1_dcache_freeze_mode())
+            .field("l1_dcache_freeze_done", &self.l1_dcache_freeze_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_FREEZE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable freeze operation on L1-ICache0. It can be cleared by software."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_object_ctrl.rs b/esp32p4/src/cache/l1_cache_object_ctrl.rs
index 227748fc34..a3e6b2b0d8 100644
--- a/esp32p4/src/cache/l1_cache_object_ctrl.rs
+++ b/esp32p4/src/cache/l1_cache_object_ctrl.rs
@@ -90,55 +90,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_OBJECT_CTRL")
-            .field(
-                "l1_icache0_tag_object",
-                &format_args!("{}", self.l1_icache0_tag_object().bit()),
-            )
-            .field(
-                "l1_icache1_tag_object",
-                &format_args!("{}", self.l1_icache1_tag_object().bit()),
-            )
-            .field(
-                "l1_icache2_tag_object",
-                &format_args!("{}", self.l1_icache2_tag_object().bit()),
-            )
-            .field(
-                "l1_icache3_tag_object",
-                &format_args!("{}", self.l1_icache3_tag_object().bit()),
-            )
-            .field(
-                "l1_dcache_tag_object",
-                &format_args!("{}", self.l1_dcache_tag_object().bit()),
-            )
-            .field(
-                "l1_icache0_mem_object",
-                &format_args!("{}", self.l1_icache0_mem_object().bit()),
-            )
-            .field(
-                "l1_icache1_mem_object",
-                &format_args!("{}", self.l1_icache1_mem_object().bit()),
-            )
-            .field(
-                "l1_icache2_mem_object",
-                &format_args!("{}", self.l1_icache2_mem_object().bit()),
-            )
-            .field(
-                "l1_icache3_mem_object",
-                &format_args!("{}", self.l1_icache3_mem_object().bit()),
-            )
-            .field(
-                "l1_dcache_mem_object",
-                &format_args!("{}", self.l1_dcache_mem_object().bit()),
-            )
+            .field("l1_icache0_tag_object", &self.l1_icache0_tag_object())
+            .field("l1_icache1_tag_object", &self.l1_icache1_tag_object())
+            .field("l1_icache2_tag_object", &self.l1_icache2_tag_object())
+            .field("l1_icache3_tag_object", &self.l1_icache3_tag_object())
+            .field("l1_dcache_tag_object", &self.l1_dcache_tag_object())
+            .field("l1_icache0_mem_object", &self.l1_icache0_mem_object())
+            .field("l1_icache1_mem_object", &self.l1_icache1_mem_object())
+            .field("l1_icache2_mem_object", &self.l1_icache2_mem_object())
+            .field("l1_icache3_mem_object", &self.l1_icache3_mem_object())
+            .field("l1_dcache_mem_object", &self.l1_dcache_mem_object())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_OBJECT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_preload_rst_ctrl.rs b/esp32p4/src/cache/l1_cache_preload_rst_ctrl.rs
index d7a3f54b2b..532158be3d 100644
--- a/esp32p4/src/cache/l1_cache_preload_rst_ctrl.rs
+++ b/esp32p4/src/cache/l1_cache_preload_rst_ctrl.rs
@@ -49,35 +49,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_PRELOAD_RST_CTRL")
-            .field(
-                "l1_icache0_pld_rst",
-                &format_args!("{}", self.l1_icache0_pld_rst().bit()),
-            )
-            .field(
-                "l1_icache1_pld_rst",
-                &format_args!("{}", self.l1_icache1_pld_rst().bit()),
-            )
-            .field(
-                "l1_icache2_pld_rst",
-                &format_args!("{}", self.l1_icache2_pld_rst().bit()),
-            )
-            .field(
-                "l1_icache3_pld_rst",
-                &format_args!("{}", self.l1_icache3_pld_rst().bit()),
-            )
-            .field(
-                "l1_dcache_pld_rst",
-                &format_args!("{}", self.l1_dcache_pld_rst().bit()),
-            )
+            .field("l1_icache0_pld_rst", &self.l1_icache0_pld_rst())
+            .field("l1_icache1_pld_rst", &self.l1_icache1_pld_rst())
+            .field("l1_icache2_pld_rst", &self.l1_icache2_pld_rst())
+            .field("l1_icache3_pld_rst", &self.l1_icache3_pld_rst())
+            .field("l1_dcache_pld_rst", &self.l1_dcache_pld_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_PRELOAD_RST_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_sync_rst_ctrl.rs b/esp32p4/src/cache/l1_cache_sync_rst_ctrl.rs
index 7e45892fb3..a3232f05de 100644
--- a/esp32p4/src/cache/l1_cache_sync_rst_ctrl.rs
+++ b/esp32p4/src/cache/l1_cache_sync_rst_ctrl.rs
@@ -49,35 +49,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_SYNC_RST_CTRL")
-            .field(
-                "l1_icache0_sync_rst",
-                &format_args!("{}", self.l1_icache0_sync_rst().bit()),
-            )
-            .field(
-                "l1_icache1_sync_rst",
-                &format_args!("{}", self.l1_icache1_sync_rst().bit()),
-            )
-            .field(
-                "l1_icache2_sync_rst",
-                &format_args!("{}", self.l1_icache2_sync_rst().bit()),
-            )
-            .field(
-                "l1_icache3_sync_rst",
-                &format_args!("{}", self.l1_icache3_sync_rst().bit()),
-            )
-            .field(
-                "l1_dcache_sync_rst",
-                &format_args!("{}", self.l1_dcache_sync_rst().bit()),
-            )
+            .field("l1_icache0_sync_rst", &self.l1_icache0_sync_rst())
+            .field("l1_icache1_sync_rst", &self.l1_icache1_sync_rst())
+            .field("l1_icache2_sync_rst", &self.l1_icache2_sync_rst())
+            .field("l1_icache3_sync_rst", &self.l1_icache3_sync_rst())
+            .field("l1_dcache_sync_rst", &self.l1_dcache_sync_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_SYNC_RST_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_tag_mem_acs_conf.rs b/esp32p4/src/cache/l1_cache_tag_mem_acs_conf.rs
index 6aea46188e..b02eb5bd37 100644
--- a/esp32p4/src/cache/l1_cache_tag_mem_acs_conf.rs
+++ b/esp32p4/src/cache/l1_cache_tag_mem_acs_conf.rs
@@ -90,55 +90,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_TAG_MEM_ACS_CONF")
-            .field(
-                "l1_icache0_tag_mem_rd_en",
-                &format_args!("{}", self.l1_icache0_tag_mem_rd_en().bit()),
-            )
-            .field(
-                "l1_icache0_tag_mem_wr_en",
-                &format_args!("{}", self.l1_icache0_tag_mem_wr_en().bit()),
-            )
-            .field(
-                "l1_icache1_tag_mem_rd_en",
-                &format_args!("{}", self.l1_icache1_tag_mem_rd_en().bit()),
-            )
-            .field(
-                "l1_icache1_tag_mem_wr_en",
-                &format_args!("{}", self.l1_icache1_tag_mem_wr_en().bit()),
-            )
-            .field(
-                "l1_icache2_tag_mem_rd_en",
-                &format_args!("{}", self.l1_icache2_tag_mem_rd_en().bit()),
-            )
-            .field(
-                "l1_icache2_tag_mem_wr_en",
-                &format_args!("{}", self.l1_icache2_tag_mem_wr_en().bit()),
-            )
-            .field(
-                "l1_icache3_tag_mem_rd_en",
-                &format_args!("{}", self.l1_icache3_tag_mem_rd_en().bit()),
-            )
-            .field(
-                "l1_icache3_tag_mem_wr_en",
-                &format_args!("{}", self.l1_icache3_tag_mem_wr_en().bit()),
-            )
-            .field(
-                "l1_dcache_tag_mem_rd_en",
-                &format_args!("{}", self.l1_dcache_tag_mem_rd_en().bit()),
-            )
-            .field(
-                "l1_dcache_tag_mem_wr_en",
-                &format_args!("{}", self.l1_dcache_tag_mem_wr_en().bit()),
-            )
+            .field("l1_icache0_tag_mem_rd_en", &self.l1_icache0_tag_mem_rd_en())
+            .field("l1_icache0_tag_mem_wr_en", &self.l1_icache0_tag_mem_wr_en())
+            .field("l1_icache1_tag_mem_rd_en", &self.l1_icache1_tag_mem_rd_en())
+            .field("l1_icache1_tag_mem_wr_en", &self.l1_icache1_tag_mem_wr_en())
+            .field("l1_icache2_tag_mem_rd_en", &self.l1_icache2_tag_mem_rd_en())
+            .field("l1_icache2_tag_mem_wr_en", &self.l1_icache2_tag_mem_wr_en())
+            .field("l1_icache3_tag_mem_rd_en", &self.l1_icache3_tag_mem_rd_en())
+            .field("l1_icache3_tag_mem_wr_en", &self.l1_icache3_tag_mem_wr_en())
+            .field("l1_dcache_tag_mem_rd_en", &self.l1_dcache_tag_mem_rd_en())
+            .field("l1_dcache_tag_mem_wr_en", &self.l1_dcache_tag_mem_wr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_TAG_MEM_ACS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: enable."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_tag_mem_power_ctrl.rs b/esp32p4/src/cache/l1_cache_tag_mem_power_ctrl.rs
index f1a52b1d62..1ed6e61969 100644
--- a/esp32p4/src/cache/l1_cache_tag_mem_power_ctrl.rs
+++ b/esp32p4/src/cache/l1_cache_tag_mem_power_ctrl.rs
@@ -133,73 +133,67 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_CACHE_TAG_MEM_POWER_CTRL")
             .field(
                 "l1_icache0_tag_mem_force_on",
-                &format_args!("{}", self.l1_icache0_tag_mem_force_on().bit()),
+                &self.l1_icache0_tag_mem_force_on(),
             )
             .field(
                 "l1_icache0_tag_mem_force_pd",
-                &format_args!("{}", self.l1_icache0_tag_mem_force_pd().bit()),
+                &self.l1_icache0_tag_mem_force_pd(),
             )
             .field(
                 "l1_icache0_tag_mem_force_pu",
-                &format_args!("{}", self.l1_icache0_tag_mem_force_pu().bit()),
+                &self.l1_icache0_tag_mem_force_pu(),
             )
             .field(
                 "l1_icache1_tag_mem_force_on",
-                &format_args!("{}", self.l1_icache1_tag_mem_force_on().bit()),
+                &self.l1_icache1_tag_mem_force_on(),
             )
             .field(
                 "l1_icache1_tag_mem_force_pd",
-                &format_args!("{}", self.l1_icache1_tag_mem_force_pd().bit()),
+                &self.l1_icache1_tag_mem_force_pd(),
             )
             .field(
                 "l1_icache1_tag_mem_force_pu",
-                &format_args!("{}", self.l1_icache1_tag_mem_force_pu().bit()),
+                &self.l1_icache1_tag_mem_force_pu(),
             )
             .field(
                 "l1_icache2_tag_mem_force_on",
-                &format_args!("{}", self.l1_icache2_tag_mem_force_on().bit()),
+                &self.l1_icache2_tag_mem_force_on(),
             )
             .field(
                 "l1_icache2_tag_mem_force_pd",
-                &format_args!("{}", self.l1_icache2_tag_mem_force_pd().bit()),
+                &self.l1_icache2_tag_mem_force_pd(),
             )
             .field(
                 "l1_icache2_tag_mem_force_pu",
-                &format_args!("{}", self.l1_icache2_tag_mem_force_pu().bit()),
+                &self.l1_icache2_tag_mem_force_pu(),
             )
             .field(
                 "l1_icache3_tag_mem_force_on",
-                &format_args!("{}", self.l1_icache3_tag_mem_force_on().bit()),
+                &self.l1_icache3_tag_mem_force_on(),
             )
             .field(
                 "l1_icache3_tag_mem_force_pd",
-                &format_args!("{}", self.l1_icache3_tag_mem_force_pd().bit()),
+                &self.l1_icache3_tag_mem_force_pd(),
             )
             .field(
                 "l1_icache3_tag_mem_force_pu",
-                &format_args!("{}", self.l1_icache3_tag_mem_force_pu().bit()),
+                &self.l1_icache3_tag_mem_force_pu(),
             )
             .field(
                 "l1_dcache_tag_mem_force_on",
-                &format_args!("{}", self.l1_dcache_tag_mem_force_on().bit()),
+                &self.l1_dcache_tag_mem_force_on(),
             )
             .field(
                 "l1_dcache_tag_mem_force_pd",
-                &format_args!("{}", self.l1_dcache_tag_mem_force_pd().bit()),
+                &self.l1_dcache_tag_mem_force_pd(),
             )
             .field(
                 "l1_dcache_tag_mem_force_pu",
-                &format_args!("{}", self.l1_dcache_tag_mem_force_pu().bit()),
+                &self.l1_dcache_tag_mem_force_pu(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_TAG_MEM_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_vaddr.rs b/esp32p4/src/cache/l1_cache_vaddr.rs
index 2321a99217..d362a76b45 100644
--- a/esp32p4/src/cache/l1_cache_vaddr.rs
+++ b/esp32p4/src/cache/l1_cache_vaddr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_VADDR")
-            .field(
-                "l1_cache_vaddr",
-                &format_args!("{}", self.l1_cache_vaddr().bits()),
-            )
+            .field("l1_cache_vaddr", &self.l1_cache_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_way_object.rs b/esp32p4/src/cache/l1_cache_way_object.rs
index ab7140af30..74f4f759ca 100644
--- a/esp32p4/src/cache/l1_cache_way_object.rs
+++ b/esp32p4/src/cache/l1_cache_way_object.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_WAY_OBJECT")
-            .field(
-                "l1_cache_way_object",
-                &format_args!("{}", self.l1_cache_way_object().bits()),
-            )
+            .field("l1_cache_way_object", &self.l1_cache_way_object())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_WAY_OBJECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_cache_wrap_around_ctrl.rs b/esp32p4/src/cache/l1_cache_wrap_around_ctrl.rs
index d0d9c4a75d..eeda888e46 100644
--- a/esp32p4/src/cache/l1_cache_wrap_around_ctrl.rs
+++ b/esp32p4/src/cache/l1_cache_wrap_around_ctrl.rs
@@ -49,35 +49,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_WRAP_AROUND_CTRL")
-            .field(
-                "l1_icache0_wrap",
-                &format_args!("{}", self.l1_icache0_wrap().bit()),
-            )
-            .field(
-                "l1_icache1_wrap",
-                &format_args!("{}", self.l1_icache1_wrap().bit()),
-            )
-            .field(
-                "l1_icache2_wrap",
-                &format_args!("{}", self.l1_icache2_wrap().bit()),
-            )
-            .field(
-                "l1_icache3_wrap",
-                &format_args!("{}", self.l1_icache3_wrap().bit()),
-            )
-            .field(
-                "l1_dcache_wrap",
-                &format_args!("{}", self.l1_dcache_wrap().bit()),
-            )
+            .field("l1_icache0_wrap", &self.l1_icache0_wrap())
+            .field("l1_icache1_wrap", &self.l1_icache1_wrap())
+            .field("l1_icache2_wrap", &self.l1_icache2_wrap())
+            .field("l1_icache3_wrap", &self.l1_icache3_wrap())
+            .field("l1_dcache_wrap", &self.l1_dcache_wrap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_WRAP_AROUND_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit as 1 to enable L1-ICache0 wrap around mode."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dbus0_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_dbus0_acs_conflict_cnt.rs
index 5f464476e4..3d8fc08cd9 100644
--- a/esp32p4/src/cache/l1_dbus0_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus0_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS0_ACS_CONFLICT_CNT")
-            .field(
-                "l1_dbus0_conflict_cnt",
-                &format_args!("{}", self.l1_dbus0_conflict_cnt().bits()),
-            )
+            .field("l1_dbus0_conflict_cnt", &self.l1_dbus0_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS0_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS0_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS0_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus0_acs_hit_cnt.rs b/esp32p4/src/cache/l1_dbus0_acs_hit_cnt.rs
index a16a81da73..860f0e81be 100644
--- a/esp32p4/src/cache/l1_dbus0_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus0_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS0_ACS_HIT_CNT")
-            .field(
-                "l1_dbus0_hit_cnt",
-                &format_args!("{}", self.l1_dbus0_hit_cnt().bits()),
-            )
+            .field("l1_dbus0_hit_cnt", &self.l1_dbus0_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS0_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS0_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS0_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus0_acs_miss_cnt.rs b/esp32p4/src/cache/l1_dbus0_acs_miss_cnt.rs
index 882558fdff..467e24cd50 100644
--- a/esp32p4/src/cache/l1_dbus0_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus0_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS0_ACS_MISS_CNT")
-            .field(
-                "l1_dbus0_miss_cnt",
-                &format_args!("{}", self.l1_dbus0_miss_cnt().bits()),
-            )
+            .field("l1_dbus0_miss_cnt", &self.l1_dbus0_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS0_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS0_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS0_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus0_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_dbus0_acs_nxtlvl_rd_cnt.rs
index 243218de85..f9f39c9b64 100644
--- a/esp32p4/src/cache/l1_dbus0_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus0_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS0_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l1_dbus0_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l1_dbus0_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l1_dbus0_nxtlvl_rd_cnt", &self.l1_dbus0_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS0_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS0_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS0_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus0_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l1_dbus0_acs_nxtlvl_wr_cnt.rs
index 84777a217b..ef5a7344f3 100644
--- a/esp32p4/src/cache/l1_dbus0_acs_nxtlvl_wr_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus0_acs_nxtlvl_wr_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS0_ACS_NXTLVL_WR_CNT")
-            .field(
-                "l1_dbus0_nxtlvl_wr_cnt",
-                &format_args!("{}", self.l1_dbus0_nxtlvl_wr_cnt().bits()),
-            )
+            .field("l1_dbus0_nxtlvl_wr_cnt", &self.l1_dbus0_nxtlvl_wr_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS0_ACS_NXTLVL_WR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus0 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus0_acs_nxtlvl_wr_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS0_ACS_NXTLVL_WR_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS0_ACS_NXTLVL_WR_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus1_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_dbus1_acs_conflict_cnt.rs
index f2574e2361..2ab61b57c4 100644
--- a/esp32p4/src/cache/l1_dbus1_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus1_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS1_ACS_CONFLICT_CNT")
-            .field(
-                "l1_dbus1_conflict_cnt",
-                &format_args!("{}", self.l1_dbus1_conflict_cnt().bits()),
-            )
+            .field("l1_dbus1_conflict_cnt", &self.l1_dbus1_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS1_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS1_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS1_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus1_acs_hit_cnt.rs b/esp32p4/src/cache/l1_dbus1_acs_hit_cnt.rs
index fe0411ce19..204e7cf97d 100644
--- a/esp32p4/src/cache/l1_dbus1_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus1_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS1_ACS_HIT_CNT")
-            .field(
-                "l1_dbus1_hit_cnt",
-                &format_args!("{}", self.l1_dbus1_hit_cnt().bits()),
-            )
+            .field("l1_dbus1_hit_cnt", &self.l1_dbus1_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS1_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS1_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS1_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus1_acs_miss_cnt.rs b/esp32p4/src/cache/l1_dbus1_acs_miss_cnt.rs
index d4fdb28e19..8f00e212e0 100644
--- a/esp32p4/src/cache/l1_dbus1_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus1_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS1_ACS_MISS_CNT")
-            .field(
-                "l1_dbus1_miss_cnt",
-                &format_args!("{}", self.l1_dbus1_miss_cnt().bits()),
-            )
+            .field("l1_dbus1_miss_cnt", &self.l1_dbus1_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS1_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS1_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS1_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus1_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_dbus1_acs_nxtlvl_rd_cnt.rs
index 9c7f720c75..81d80b972b 100644
--- a/esp32p4/src/cache/l1_dbus1_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus1_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS1_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l1_dbus1_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l1_dbus1_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l1_dbus1_nxtlvl_rd_cnt", &self.l1_dbus1_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS1_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS1_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS1_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus1_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l1_dbus1_acs_nxtlvl_wr_cnt.rs
index a2a20d1510..26d7b65c9d 100644
--- a/esp32p4/src/cache/l1_dbus1_acs_nxtlvl_wr_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus1_acs_nxtlvl_wr_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS1_ACS_NXTLVL_WR_CNT")
-            .field(
-                "l1_dbus1_nxtlvl_wr_cnt",
-                &format_args!("{}", self.l1_dbus1_nxtlvl_wr_cnt().bits()),
-            )
+            .field("l1_dbus1_nxtlvl_wr_cnt", &self.l1_dbus1_nxtlvl_wr_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS1_ACS_NXTLVL_WR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus1 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus1_acs_nxtlvl_wr_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS1_ACS_NXTLVL_WR_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS1_ACS_NXTLVL_WR_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus2_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_dbus2_acs_conflict_cnt.rs
index ae4033a778..a3f4c8c9b5 100644
--- a/esp32p4/src/cache/l1_dbus2_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus2_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS2_ACS_CONFLICT_CNT")
-            .field(
-                "l1_dbus2_conflict_cnt",
-                &format_args!("{}", self.l1_dbus2_conflict_cnt().bits()),
-            )
+            .field("l1_dbus2_conflict_cnt", &self.l1_dbus2_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS2_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS2_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS2_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus2_acs_hit_cnt.rs b/esp32p4/src/cache/l1_dbus2_acs_hit_cnt.rs
index 5b523cf5f4..8eb631c5ce 100644
--- a/esp32p4/src/cache/l1_dbus2_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus2_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS2_ACS_HIT_CNT")
-            .field(
-                "l1_dbus2_hit_cnt",
-                &format_args!("{}", self.l1_dbus2_hit_cnt().bits()),
-            )
+            .field("l1_dbus2_hit_cnt", &self.l1_dbus2_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS2_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS2_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS2_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus2_acs_miss_cnt.rs b/esp32p4/src/cache/l1_dbus2_acs_miss_cnt.rs
index 39d1435858..adba0195f0 100644
--- a/esp32p4/src/cache/l1_dbus2_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus2_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS2_ACS_MISS_CNT")
-            .field(
-                "l1_dbus2_miss_cnt",
-                &format_args!("{}", self.l1_dbus2_miss_cnt().bits()),
-            )
+            .field("l1_dbus2_miss_cnt", &self.l1_dbus2_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS2_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS2_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS2_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus2_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_dbus2_acs_nxtlvl_rd_cnt.rs
index 6f0dcb7255..eccda808d0 100644
--- a/esp32p4/src/cache/l1_dbus2_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus2_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS2_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l1_dbus2_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l1_dbus2_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l1_dbus2_nxtlvl_rd_cnt", &self.l1_dbus2_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS2_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS2_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS2_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus2_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l1_dbus2_acs_nxtlvl_wr_cnt.rs
index 0454fcee19..a788e4c966 100644
--- a/esp32p4/src/cache/l1_dbus2_acs_nxtlvl_wr_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus2_acs_nxtlvl_wr_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS2_ACS_NXTLVL_WR_CNT")
-            .field(
-                "l1_dbus2_nxtlvl_wr_cnt",
-                &format_args!("{}", self.l1_dbus2_nxtlvl_wr_cnt().bits()),
-            )
+            .field("l1_dbus2_nxtlvl_wr_cnt", &self.l1_dbus2_nxtlvl_wr_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS2_ACS_NXTLVL_WR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus2 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus2_acs_nxtlvl_wr_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS2_ACS_NXTLVL_WR_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS2_ACS_NXTLVL_WR_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus3_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_dbus3_acs_conflict_cnt.rs
index c4aa3941ef..27671e7815 100644
--- a/esp32p4/src/cache/l1_dbus3_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus3_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS3_ACS_CONFLICT_CNT")
-            .field(
-                "l1_dbus3_conflict_cnt",
-                &format_args!("{}", self.l1_dbus3_conflict_cnt().bits()),
-            )
+            .field("l1_dbus3_conflict_cnt", &self.l1_dbus3_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS3_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS3_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS3_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus3_acs_hit_cnt.rs b/esp32p4/src/cache/l1_dbus3_acs_hit_cnt.rs
index 00c237c9fe..5e27051463 100644
--- a/esp32p4/src/cache/l1_dbus3_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus3_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS3_ACS_HIT_CNT")
-            .field(
-                "l1_dbus3_hit_cnt",
-                &format_args!("{}", self.l1_dbus3_hit_cnt().bits()),
-            )
+            .field("l1_dbus3_hit_cnt", &self.l1_dbus3_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS3_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS3_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS3_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus3_acs_miss_cnt.rs b/esp32p4/src/cache/l1_dbus3_acs_miss_cnt.rs
index 7076ced3a0..dc66fc6166 100644
--- a/esp32p4/src/cache/l1_dbus3_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus3_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS3_ACS_MISS_CNT")
-            .field(
-                "l1_dbus3_miss_cnt",
-                &format_args!("{}", self.l1_dbus3_miss_cnt().bits()),
-            )
+            .field("l1_dbus3_miss_cnt", &self.l1_dbus3_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS3_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS3_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS3_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus3_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_dbus3_acs_nxtlvl_rd_cnt.rs
index 0549427c62..58db49146b 100644
--- a/esp32p4/src/cache/l1_dbus3_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus3_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS3_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l1_dbus3_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l1_dbus3_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l1_dbus3_nxtlvl_rd_cnt", &self.l1_dbus3_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS3_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS3_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS3_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dbus3_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l1_dbus3_acs_nxtlvl_wr_cnt.rs
index c8e775d9f0..29a2a8270b 100644
--- a/esp32p4/src/cache/l1_dbus3_acs_nxtlvl_wr_cnt.rs
+++ b/esp32p4/src/cache/l1_dbus3_acs_nxtlvl_wr_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DBUS3_ACS_NXTLVL_WR_CNT")
-            .field(
-                "l1_dbus3_nxtlvl_wr_cnt",
-                &format_args!("{}", self.l1_dbus3_nxtlvl_wr_cnt().bits()),
-            )
+            .field("l1_dbus3_nxtlvl_wr_cnt", &self.l1_dbus3_nxtlvl_wr_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DBUS3_ACS_NXTLVL_WR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache bus3 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dbus3_acs_nxtlvl_wr_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DBUS3_ACS_NXTLVL_WR_CNT_SPEC;
 impl crate::RegisterSpec for L1_DBUS3_ACS_NXTLVL_WR_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_dcache_acs_fail_addr.rs b/esp32p4/src/cache/l1_dcache_acs_fail_addr.rs
index 8845c5ac19..66d550bcff 100644
--- a/esp32p4/src/cache/l1_dcache_acs_fail_addr.rs
+++ b/esp32p4/src/cache/l1_dcache_acs_fail_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DCACHE_ACS_FAIL_ADDR")
-            .field(
-                "l1_dcache_fail_addr",
-                &format_args!("{}", self.l1_dcache_fail_addr().bits()),
-            )
+            .field("l1_dcache_fail_addr", &self.l1_dcache_fail_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_ACS_FAIL_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_acs_fail_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DCACHE_ACS_FAIL_ADDR_SPEC;
 impl crate::RegisterSpec for L1_DCACHE_ACS_FAIL_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l1_dcache_acs_fail_id_attr.rs b/esp32p4/src/cache/l1_dcache_acs_fail_id_attr.rs
index aadb0d86b6..51fc88db35 100644
--- a/esp32p4/src/cache/l1_dcache_acs_fail_id_attr.rs
+++ b/esp32p4/src/cache/l1_dcache_acs_fail_id_attr.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DCACHE_ACS_FAIL_ID_ATTR")
-            .field(
-                "l1_dcache_fail_id",
-                &format_args!("{}", self.l1_dcache_fail_id().bits()),
-            )
-            .field(
-                "l1_dcache_fail_attr",
-                &format_args!("{}", self.l1_dcache_fail_attr().bits()),
-            )
+            .field("l1_dcache_fail_id", &self.l1_dcache_fail_id())
+            .field("l1_dcache_fail_attr", &self.l1_dcache_fail_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_ACS_FAIL_ID_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-DCache Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_acs_fail_id_attr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DCACHE_ACS_FAIL_ID_ATTR_SPEC;
 impl crate::RegisterSpec for L1_DCACHE_ACS_FAIL_ID_ATTR_SPEC {
diff --git a/esp32p4/src/cache/l1_dcache_autoload_ctrl.rs b/esp32p4/src/cache/l1_dcache_autoload_ctrl.rs
index fff68c7c58..cd66b312be 100644
--- a/esp32p4/src/cache/l1_dcache_autoload_ctrl.rs
+++ b/esp32p4/src/cache/l1_dcache_autoload_ctrl.rs
@@ -87,51 +87,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DCACHE_AUTOLOAD_CTRL")
-            .field(
-                "l1_dcache_autoload_ena",
-                &format_args!("{}", self.l1_dcache_autoload_ena().bit()),
-            )
-            .field(
-                "l1_dcache_autoload_done",
-                &format_args!("{}", self.l1_dcache_autoload_done().bit()),
-            )
-            .field(
-                "l1_dcache_autoload_order",
-                &format_args!("{}", self.l1_dcache_autoload_order().bit()),
-            )
+            .field("l1_dcache_autoload_ena", &self.l1_dcache_autoload_ena())
+            .field("l1_dcache_autoload_done", &self.l1_dcache_autoload_done())
+            .field("l1_dcache_autoload_order", &self.l1_dcache_autoload_order())
             .field(
                 "l1_dcache_autoload_trigger_mode",
-                &format_args!("{}", self.l1_dcache_autoload_trigger_mode().bits()),
+                &self.l1_dcache_autoload_trigger_mode(),
             )
             .field(
                 "l1_dcache_autoload_sct0_ena",
-                &format_args!("{}", self.l1_dcache_autoload_sct0_ena().bit()),
+                &self.l1_dcache_autoload_sct0_ena(),
             )
             .field(
                 "l1_dcache_autoload_sct1_ena",
-                &format_args!("{}", self.l1_dcache_autoload_sct1_ena().bit()),
+                &self.l1_dcache_autoload_sct1_ena(),
             )
             .field(
                 "l1_dcache_autoload_sct2_ena",
-                &format_args!("{}", self.l1_dcache_autoload_sct2_ena().bit()),
+                &self.l1_dcache_autoload_sct2_ena(),
             )
             .field(
                 "l1_dcache_autoload_sct3_ena",
-                &format_args!("{}", self.l1_dcache_autoload_sct3_ena().bit()),
-            )
-            .field(
-                "l1_dcache_autoload_rgid",
-                &format_args!("{}", self.l1_dcache_autoload_rgid().bits()),
+                &self.l1_dcache_autoload_sct3_ena(),
             )
+            .field("l1_dcache_autoload_rgid", &self.l1_dcache_autoload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_AUTOLOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L1-DCache. 1: enable, 0: disable."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct0_addr.rs b/esp32p4/src/cache/l1_dcache_autoload_sct0_addr.rs
index 0b9a5d45c4..68f97884c1 100644
--- a/esp32p4/src/cache/l1_dcache_autoload_sct0_addr.rs
+++ b/esp32p4/src/cache/l1_dcache_autoload_sct0_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_DCACHE_AUTOLOAD_SCT0_ADDR")
             .field(
                 "l1_dcache_autoload_sct0_addr",
-                &format_args!("{}", self.l1_dcache_autoload_sct0_addr().bits()),
+                &self.l1_dcache_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_AUTOLOAD_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct0_size.rs b/esp32p4/src/cache/l1_dcache_autoload_sct0_size.rs
index 36372b553e..1757dc4506 100644
--- a/esp32p4/src/cache/l1_dcache_autoload_sct0_size.rs
+++ b/esp32p4/src/cache/l1_dcache_autoload_sct0_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_DCACHE_AUTOLOAD_SCT0_SIZE")
             .field(
                 "l1_dcache_autoload_sct0_size",
-                &format_args!("{}", self.l1_dcache_autoload_sct0_size().bits()),
+                &self.l1_dcache_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_AUTOLOAD_SCT0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Those bits are used to configure the size of the first section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct1_addr.rs b/esp32p4/src/cache/l1_dcache_autoload_sct1_addr.rs
index d20f7451e3..1dd5a5a068 100644
--- a/esp32p4/src/cache/l1_dcache_autoload_sct1_addr.rs
+++ b/esp32p4/src/cache/l1_dcache_autoload_sct1_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_DCACHE_AUTOLOAD_SCT1_ADDR")
             .field(
                 "l1_dcache_autoload_sct1_addr",
-                &format_args!("{}", self.l1_dcache_autoload_sct1_addr().bits()),
+                &self.l1_dcache_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_AUTOLOAD_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct1_size.rs b/esp32p4/src/cache/l1_dcache_autoload_sct1_size.rs
index b670351798..eccd2c6290 100644
--- a/esp32p4/src/cache/l1_dcache_autoload_sct1_size.rs
+++ b/esp32p4/src/cache/l1_dcache_autoload_sct1_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_DCACHE_AUTOLOAD_SCT1_SIZE")
             .field(
                 "l1_dcache_autoload_sct1_size",
-                &format_args!("{}", self.l1_dcache_autoload_sct1_size().bits()),
+                &self.l1_dcache_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_AUTOLOAD_SCT1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Those bits are used to configure the size of the second section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct2_addr.rs b/esp32p4/src/cache/l1_dcache_autoload_sct2_addr.rs
index e6558873dc..08694dd862 100644
--- a/esp32p4/src/cache/l1_dcache_autoload_sct2_addr.rs
+++ b/esp32p4/src/cache/l1_dcache_autoload_sct2_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_DCACHE_AUTOLOAD_SCT2_ADDR")
             .field(
                 "l1_dcache_autoload_sct2_addr",
-                &format_args!("{}", self.l1_dcache_autoload_sct2_addr().bits()),
+                &self.l1_dcache_autoload_sct2_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_AUTOLOAD_SCT2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct2_size.rs b/esp32p4/src/cache/l1_dcache_autoload_sct2_size.rs
index 26e7ddd815..ea484d8dcb 100644
--- a/esp32p4/src/cache/l1_dcache_autoload_sct2_size.rs
+++ b/esp32p4/src/cache/l1_dcache_autoload_sct2_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_DCACHE_AUTOLOAD_SCT2_SIZE")
             .field(
                 "l1_dcache_autoload_sct2_size",
-                &format_args!("{}", self.l1_dcache_autoload_sct2_size().bits()),
+                &self.l1_dcache_autoload_sct2_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_AUTOLOAD_SCT2_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Those bits are used to configure the size of the third section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct3_addr.rs b/esp32p4/src/cache/l1_dcache_autoload_sct3_addr.rs
index 79b6f113ba..d59d334e22 100644
--- a/esp32p4/src/cache/l1_dcache_autoload_sct3_addr.rs
+++ b/esp32p4/src/cache/l1_dcache_autoload_sct3_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_DCACHE_AUTOLOAD_SCT3_ADDR")
             .field(
                 "l1_dcache_autoload_sct3_addr",
-                &format_args!("{}", self.l1_dcache_autoload_sct3_addr().bits()),
+                &self.l1_dcache_autoload_sct3_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_AUTOLOAD_SCT3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_autoload_sct3_size.rs b/esp32p4/src/cache/l1_dcache_autoload_sct3_size.rs
index 85e66f89f9..c0fff20689 100644
--- a/esp32p4/src/cache/l1_dcache_autoload_sct3_size.rs
+++ b/esp32p4/src/cache/l1_dcache_autoload_sct3_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_DCACHE_AUTOLOAD_SCT3_SIZE")
             .field(
                 "l1_dcache_autoload_sct3_size",
-                &format_args!("{}", self.l1_dcache_autoload_sct3_size().bits()),
+                &self.l1_dcache_autoload_sct3_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_AUTOLOAD_SCT3_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Those bits are used to configure the size of the fourth section for autoload operation on L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_blocksize_conf.rs b/esp32p4/src/cache/l1_dcache_blocksize_conf.rs
index 3f667fcfcc..8e0e89d2ed 100644
--- a/esp32p4/src/cache/l1_dcache_blocksize_conf.rs
+++ b/esp32p4/src/cache/l1_dcache_blocksize_conf.rs
@@ -48,39 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DCACHE_BLOCKSIZE_CONF")
-            .field(
-                "l1_dcache_blocksize_8",
-                &format_args!("{}", self.l1_dcache_blocksize_8().bit()),
-            )
-            .field(
-                "l1_dcache_blocksize_16",
-                &format_args!("{}", self.l1_dcache_blocksize_16().bit()),
-            )
-            .field(
-                "l1_dcache_blocksize_32",
-                &format_args!("{}", self.l1_dcache_blocksize_32().bit()),
-            )
-            .field(
-                "l1_dcache_blocksize_64",
-                &format_args!("{}", self.l1_dcache_blocksize_64().bit()),
-            )
-            .field(
-                "l1_dcache_blocksize_128",
-                &format_args!("{}", self.l1_dcache_blocksize_128().bit()),
-            )
-            .field(
-                "l1_dcache_blocksize_256",
-                &format_args!("{}", self.l1_dcache_blocksize_256().bit()),
-            )
+            .field("l1_dcache_blocksize_8", &self.l1_dcache_blocksize_8())
+            .field("l1_dcache_blocksize_16", &self.l1_dcache_blocksize_16())
+            .field("l1_dcache_blocksize_32", &self.l1_dcache_blocksize_32())
+            .field("l1_dcache_blocksize_64", &self.l1_dcache_blocksize_64())
+            .field("l1_dcache_blocksize_128", &self.l1_dcache_blocksize_128())
+            .field("l1_dcache_blocksize_256", &self.l1_dcache_blocksize_256())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_BLOCKSIZE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 data Cache BlockSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_blocksize_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DCACHE_BLOCKSIZE_CONF_SPEC;
 impl crate::RegisterSpec for L1_DCACHE_BLOCKSIZE_CONF_SPEC {
diff --git a/esp32p4/src/cache/l1_dcache_cachesize_conf.rs b/esp32p4/src/cache/l1_dcache_cachesize_conf.rs
index e70311cbd5..48e953daa0 100644
--- a/esp32p4/src/cache/l1_dcache_cachesize_conf.rs
+++ b/esp32p4/src/cache/l1_dcache_cachesize_conf.rs
@@ -97,67 +97,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DCACHE_CACHESIZE_CONF")
-            .field(
-                "l1_dcache_cachesize_256",
-                &format_args!("{}", self.l1_dcache_cachesize_256().bit()),
-            )
-            .field(
-                "l1_dcache_cachesize_512",
-                &format_args!("{}", self.l1_dcache_cachesize_512().bit()),
-            )
-            .field(
-                "l1_dcache_cachesize_1k",
-                &format_args!("{}", self.l1_dcache_cachesize_1k().bit()),
-            )
-            .field(
-                "l1_dcache_cachesize_2k",
-                &format_args!("{}", self.l1_dcache_cachesize_2k().bit()),
-            )
-            .field(
-                "l1_dcache_cachesize_4k",
-                &format_args!("{}", self.l1_dcache_cachesize_4k().bit()),
-            )
-            .field(
-                "l1_dcache_cachesize_8k",
-                &format_args!("{}", self.l1_dcache_cachesize_8k().bit()),
-            )
-            .field(
-                "l1_dcache_cachesize_16k",
-                &format_args!("{}", self.l1_dcache_cachesize_16k().bit()),
-            )
-            .field(
-                "l1_dcache_cachesize_32k",
-                &format_args!("{}", self.l1_dcache_cachesize_32k().bit()),
-            )
-            .field(
-                "l1_dcache_cachesize_64k",
-                &format_args!("{}", self.l1_dcache_cachesize_64k().bit()),
-            )
-            .field(
-                "l1_dcache_cachesize_128k",
-                &format_args!("{}", self.l1_dcache_cachesize_128k().bit()),
-            )
-            .field(
-                "l1_dcache_cachesize_256k",
-                &format_args!("{}", self.l1_dcache_cachesize_256k().bit()),
-            )
-            .field(
-                "l1_dcache_cachesize_512k",
-                &format_args!("{}", self.l1_dcache_cachesize_512k().bit()),
-            )
+            .field("l1_dcache_cachesize_256", &self.l1_dcache_cachesize_256())
+            .field("l1_dcache_cachesize_512", &self.l1_dcache_cachesize_512())
+            .field("l1_dcache_cachesize_1k", &self.l1_dcache_cachesize_1k())
+            .field("l1_dcache_cachesize_2k", &self.l1_dcache_cachesize_2k())
+            .field("l1_dcache_cachesize_4k", &self.l1_dcache_cachesize_4k())
+            .field("l1_dcache_cachesize_8k", &self.l1_dcache_cachesize_8k())
+            .field("l1_dcache_cachesize_16k", &self.l1_dcache_cachesize_16k())
+            .field("l1_dcache_cachesize_32k", &self.l1_dcache_cachesize_32k())
+            .field("l1_dcache_cachesize_64k", &self.l1_dcache_cachesize_64k())
+            .field("l1_dcache_cachesize_128k", &self.l1_dcache_cachesize_128k())
+            .field("l1_dcache_cachesize_256k", &self.l1_dcache_cachesize_256k())
+            .field("l1_dcache_cachesize_512k", &self.l1_dcache_cachesize_512k())
             .field(
                 "l1_dcache_cachesize_1024k",
-                &format_args!("{}", self.l1_dcache_cachesize_1024k().bit()),
+                &self.l1_dcache_cachesize_1024k(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_CACHESIZE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 data Cache CacheSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_dcache_cachesize_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_DCACHE_CACHESIZE_CONF_SPEC;
 impl crate::RegisterSpec for L1_DCACHE_CACHESIZE_CONF_SPEC {
diff --git a/esp32p4/src/cache/l1_dcache_ctrl.rs b/esp32p4/src/cache/l1_dcache_ctrl.rs
index b59e42479d..0edd152ea6 100644
--- a/esp32p4/src/cache/l1_dcache_ctrl.rs
+++ b/esp32p4/src/cache/l1_dcache_ctrl.rs
@@ -58,39 +58,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DCACHE_CTRL")
-            .field(
-                "l1_dcache_shut_dbus0",
-                &format_args!("{}", self.l1_dcache_shut_dbus0().bit()),
-            )
-            .field(
-                "l1_dcache_shut_dbus1",
-                &format_args!("{}", self.l1_dcache_shut_dbus1().bit()),
-            )
-            .field(
-                "l1_dcache_shut_dbus2",
-                &format_args!("{}", self.l1_dcache_shut_dbus2().bit()),
-            )
-            .field(
-                "l1_dcache_shut_dbus3",
-                &format_args!("{}", self.l1_dcache_shut_dbus3().bit()),
-            )
-            .field(
-                "l1_dcache_shut_dma",
-                &format_args!("{}", self.l1_dcache_shut_dma().bit()),
-            )
-            .field(
-                "l1_dcache_undef_op",
-                &format_args!("{}", self.l1_dcache_undef_op().bits()),
-            )
+            .field("l1_dcache_shut_dbus0", &self.l1_dcache_shut_dbus0())
+            .field("l1_dcache_shut_dbus1", &self.l1_dcache_shut_dbus1())
+            .field("l1_dcache_shut_dbus2", &self.l1_dcache_shut_dbus2())
+            .field("l1_dcache_shut_dbus3", &self.l1_dcache_shut_dbus3())
+            .field("l1_dcache_shut_dma", &self.l1_dcache_shut_dma())
+            .field("l1_dcache_undef_op", &self.l1_dcache_undef_op())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_preload_addr.rs b/esp32p4/src/cache/l1_dcache_preload_addr.rs
index 401b9d92cc..9010751101 100644
--- a/esp32p4/src/cache/l1_dcache_preload_addr.rs
+++ b/esp32p4/src/cache/l1_dcache_preload_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DCACHE_PRELOAD_ADDR")
-            .field(
-                "l1_dcache_preload_addr",
-                &format_args!("{}", self.l1_dcache_preload_addr().bits()),
-            )
+            .field("l1_dcache_preload_addr", &self.l1_dcache_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_preload_ctrl.rs b/esp32p4/src/cache/l1_dcache_preload_ctrl.rs
index 977420d377..76a2649e76 100644
--- a/esp32p4/src/cache/l1_dcache_preload_ctrl.rs
+++ b/esp32p4/src/cache/l1_dcache_preload_ctrl.rs
@@ -42,31 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DCACHE_PRELOAD_CTRL")
-            .field(
-                "l1_dcache_preload_ena",
-                &format_args!("{}", self.l1_dcache_preload_ena().bit()),
-            )
-            .field(
-                "l1_dcache_preload_done",
-                &format_args!("{}", self.l1_dcache_preload_done().bit()),
-            )
-            .field(
-                "l1_dcache_preload_order",
-                &format_args!("{}", self.l1_dcache_preload_order().bit()),
-            )
-            .field(
-                "l1_dcache_preload_rgid",
-                &format_args!("{}", self.l1_dcache_preload_rgid().bits()),
-            )
+            .field("l1_dcache_preload_ena", &self.l1_dcache_preload_ena())
+            .field("l1_dcache_preload_done", &self.l1_dcache_preload_done())
+            .field("l1_dcache_preload_order", &self.l1_dcache_preload_order())
+            .field("l1_dcache_preload_rgid", &self.l1_dcache_preload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_PRELOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable preload operation on L1-DCache. It will be cleared by hardware automatically after preload operation is done."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_preload_size.rs b/esp32p4/src/cache/l1_dcache_preload_size.rs
index 491e01b1db..abce311905 100644
--- a/esp32p4/src/cache/l1_dcache_preload_size.rs
+++ b/esp32p4/src/cache/l1_dcache_preload_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_DCACHE_PRELOAD_SIZE")
-            .field(
-                "l1_dcache_preload_size",
-                &format_args!("{}", self.l1_dcache_preload_size().bits()),
-            )
+            .field("l1_dcache_preload_size", &self.l1_dcache_preload_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_prelock_conf.rs b/esp32p4/src/cache/l1_dcache_prelock_conf.rs
index 4af55b9272..192664897d 100644
--- a/esp32p4/src/cache/l1_dcache_prelock_conf.rs
+++ b/esp32p4/src/cache/l1_dcache_prelock_conf.rs
@@ -37,25 +37,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_DCACHE_PRELOCK_CONF")
             .field(
                 "l1_dcache_prelock_sct0_en",
-                &format_args!("{}", self.l1_dcache_prelock_sct0_en().bit()),
+                &self.l1_dcache_prelock_sct0_en(),
             )
             .field(
                 "l1_dcache_prelock_sct1_en",
-                &format_args!("{}", self.l1_dcache_prelock_sct1_en().bit()),
-            )
-            .field(
-                "l1_dcache_prelock_rgid",
-                &format_args!("{}", self.l1_dcache_prelock_rgid().bits()),
+                &self.l1_dcache_prelock_sct1_en(),
             )
+            .field("l1_dcache_prelock_rgid", &self.l1_dcache_prelock_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_PRELOCK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable the first section of prelock function on L1-DCache."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_prelock_sct0_addr.rs b/esp32p4/src/cache/l1_dcache_prelock_sct0_addr.rs
index fd80df1e46..5646ffdb43 100644
--- a/esp32p4/src/cache/l1_dcache_prelock_sct0_addr.rs
+++ b/esp32p4/src/cache/l1_dcache_prelock_sct0_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_DCACHE_PRELOCK_SCT0_ADDR")
             .field(
                 "l1_dcache_prelock_sct0_addr",
-                &format_args!("{}", self.l1_dcache_prelock_sct0_addr().bits()),
+                &self.l1_dcache_prelock_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_PRELOCK_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_prelock_sct1_addr.rs b/esp32p4/src/cache/l1_dcache_prelock_sct1_addr.rs
index 97934b3238..8f552768a1 100644
--- a/esp32p4/src/cache/l1_dcache_prelock_sct1_addr.rs
+++ b/esp32p4/src/cache/l1_dcache_prelock_sct1_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_DCACHE_PRELOCK_SCT1_ADDR")
             .field(
                 "l1_dcache_prelock_sct1_addr",
-                &format_args!("{}", self.l1_dcache_prelock_sct1_addr().bits()),
+                &self.l1_dcache_prelock_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_PRELOCK_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_dcache_prelock_sct_size.rs b/esp32p4/src/cache/l1_dcache_prelock_sct_size.rs
index 7bcbebba39..cbe1c0d4d5 100644
--- a/esp32p4/src/cache/l1_dcache_prelock_sct_size.rs
+++ b/esp32p4/src/cache/l1_dcache_prelock_sct_size.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_DCACHE_PRELOCK_SCT_SIZE")
             .field(
                 "l1_dcache_prelock_sct0_size",
-                &format_args!("{}", self.l1_dcache_prelock_sct0_size().bits()),
+                &self.l1_dcache_prelock_sct0_size(),
             )
             .field(
                 "l1_dcache_prelock_sct1_size",
-                &format_args!("{}", self.l1_dcache_prelock_sct1_size().bits()),
+                &self.l1_dcache_prelock_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_DCACHE_PRELOCK_SCT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_ibus0_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_ibus0_acs_conflict_cnt.rs
index cdb8c10bf6..048cf9b9c6 100644
--- a/esp32p4/src/cache/l1_ibus0_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus0_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS0_ACS_CONFLICT_CNT")
-            .field(
-                "l1_ibus0_conflict_cnt",
-                &format_args!("{}", self.l1_ibus0_conflict_cnt().bits()),
-            )
+            .field("l1_ibus0_conflict_cnt", &self.l1_ibus0_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS0_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS0_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS0_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_ibus0_acs_hit_cnt.rs b/esp32p4/src/cache/l1_ibus0_acs_hit_cnt.rs
index c6e13acf60..975cb67efe 100644
--- a/esp32p4/src/cache/l1_ibus0_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus0_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS0_ACS_HIT_CNT")
-            .field(
-                "l1_ibus0_hit_cnt",
-                &format_args!("{}", self.l1_ibus0_hit_cnt().bits()),
-            )
+            .field("l1_ibus0_hit_cnt", &self.l1_ibus0_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS0_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS0_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS0_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_ibus0_acs_miss_cnt.rs b/esp32p4/src/cache/l1_ibus0_acs_miss_cnt.rs
index 136d269135..dd9fa0be9b 100644
--- a/esp32p4/src/cache/l1_ibus0_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus0_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS0_ACS_MISS_CNT")
-            .field(
-                "l1_ibus0_miss_cnt",
-                &format_args!("{}", self.l1_ibus0_miss_cnt().bits()),
-            )
+            .field("l1_ibus0_miss_cnt", &self.l1_ibus0_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS0_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS0_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS0_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_ibus0_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_ibus0_acs_nxtlvl_rd_cnt.rs
index ec1bd8cd99..fe9b94276e 100644
--- a/esp32p4/src/cache/l1_ibus0_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus0_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS0_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l1_ibus0_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l1_ibus0_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l1_ibus0_nxtlvl_rd_cnt", &self.l1_ibus0_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS0_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus0_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS0_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS0_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_ibus1_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_ibus1_acs_conflict_cnt.rs
index 11e192a441..c38bdeb92a 100644
--- a/esp32p4/src/cache/l1_ibus1_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus1_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS1_ACS_CONFLICT_CNT")
-            .field(
-                "l1_ibus1_conflict_cnt",
-                &format_args!("{}", self.l1_ibus1_conflict_cnt().bits()),
-            )
+            .field("l1_ibus1_conflict_cnt", &self.l1_ibus1_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS1_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS1_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS1_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_ibus1_acs_hit_cnt.rs b/esp32p4/src/cache/l1_ibus1_acs_hit_cnt.rs
index 843ad25984..9561601492 100644
--- a/esp32p4/src/cache/l1_ibus1_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus1_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS1_ACS_HIT_CNT")
-            .field(
-                "l1_ibus1_hit_cnt",
-                &format_args!("{}", self.l1_ibus1_hit_cnt().bits()),
-            )
+            .field("l1_ibus1_hit_cnt", &self.l1_ibus1_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS1_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS1_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS1_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_ibus1_acs_miss_cnt.rs b/esp32p4/src/cache/l1_ibus1_acs_miss_cnt.rs
index 443036644f..bca4e76059 100644
--- a/esp32p4/src/cache/l1_ibus1_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus1_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS1_ACS_MISS_CNT")
-            .field(
-                "l1_ibus1_miss_cnt",
-                &format_args!("{}", self.l1_ibus1_miss_cnt().bits()),
-            )
+            .field("l1_ibus1_miss_cnt", &self.l1_ibus1_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS1_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS1_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS1_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_ibus1_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_ibus1_acs_nxtlvl_rd_cnt.rs
index 1d547cb2db..39b7bdacf4 100644
--- a/esp32p4/src/cache/l1_ibus1_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus1_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS1_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l1_ibus1_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l1_ibus1_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l1_ibus1_nxtlvl_rd_cnt", &self.l1_ibus1_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS1_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus1_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS1_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS1_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_ibus2_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_ibus2_acs_conflict_cnt.rs
index 5cbb888ea1..341fed9f0b 100644
--- a/esp32p4/src/cache/l1_ibus2_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus2_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS2_ACS_CONFLICT_CNT")
-            .field(
-                "l1_ibus2_conflict_cnt",
-                &format_args!("{}", self.l1_ibus2_conflict_cnt().bits()),
-            )
+            .field("l1_ibus2_conflict_cnt", &self.l1_ibus2_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS2_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS2_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS2_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_ibus2_acs_hit_cnt.rs b/esp32p4/src/cache/l1_ibus2_acs_hit_cnt.rs
index 6461e705b6..2199318015 100644
--- a/esp32p4/src/cache/l1_ibus2_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus2_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS2_ACS_HIT_CNT")
-            .field(
-                "l1_ibus2_hit_cnt",
-                &format_args!("{}", self.l1_ibus2_hit_cnt().bits()),
-            )
+            .field("l1_ibus2_hit_cnt", &self.l1_ibus2_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS2_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS2_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS2_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_ibus2_acs_miss_cnt.rs b/esp32p4/src/cache/l1_ibus2_acs_miss_cnt.rs
index c697c8b065..9e9667f961 100644
--- a/esp32p4/src/cache/l1_ibus2_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus2_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS2_ACS_MISS_CNT")
-            .field(
-                "l1_ibus2_miss_cnt",
-                &format_args!("{}", self.l1_ibus2_miss_cnt().bits()),
-            )
+            .field("l1_ibus2_miss_cnt", &self.l1_ibus2_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS2_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS2_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS2_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_ibus2_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_ibus2_acs_nxtlvl_rd_cnt.rs
index cb1e287022..3421b19227 100644
--- a/esp32p4/src/cache/l1_ibus2_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus2_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS2_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l1_ibus2_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l1_ibus2_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l1_ibus2_nxtlvl_rd_cnt", &self.l1_ibus2_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS2_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus2_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS2_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS2_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_ibus3_acs_conflict_cnt.rs b/esp32p4/src/cache/l1_ibus3_acs_conflict_cnt.rs
index 4ba34f96cd..80e19e1cac 100644
--- a/esp32p4/src/cache/l1_ibus3_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus3_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS3_ACS_CONFLICT_CNT")
-            .field(
-                "l1_ibus3_conflict_cnt",
-                &format_args!("{}", self.l1_ibus3_conflict_cnt().bits()),
-            )
+            .field("l1_ibus3_conflict_cnt", &self.l1_ibus3_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS3_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS3_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS3_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_ibus3_acs_hit_cnt.rs b/esp32p4/src/cache/l1_ibus3_acs_hit_cnt.rs
index c5f1f42786..8d50fd89f9 100644
--- a/esp32p4/src/cache/l1_ibus3_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus3_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS3_ACS_HIT_CNT")
-            .field(
-                "l1_ibus3_hit_cnt",
-                &format_args!("{}", self.l1_ibus3_hit_cnt().bits()),
-            )
+            .field("l1_ibus3_hit_cnt", &self.l1_ibus3_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS3_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS3_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS3_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_ibus3_acs_miss_cnt.rs b/esp32p4/src/cache/l1_ibus3_acs_miss_cnt.rs
index 923ef006b8..d9cae2fdf3 100644
--- a/esp32p4/src/cache/l1_ibus3_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus3_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS3_ACS_MISS_CNT")
-            .field(
-                "l1_ibus3_miss_cnt",
-                &format_args!("{}", self.l1_ibus3_miss_cnt().bits()),
-            )
+            .field("l1_ibus3_miss_cnt", &self.l1_ibus3_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS3_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS3_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS3_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_ibus3_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l1_ibus3_acs_nxtlvl_rd_cnt.rs
index 63570fe8c4..77c992b0fc 100644
--- a/esp32p4/src/cache/l1_ibus3_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l1_ibus3_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_IBUS3_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l1_ibus3_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l1_ibus3_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l1_ibus3_nxtlvl_rd_cnt", &self.l1_ibus3_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_IBUS3_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_ibus3_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_IBUS3_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L1_IBUS3_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l1_icache0_acs_fail_addr.rs b/esp32p4/src/cache/l1_icache0_acs_fail_addr.rs
index 9debe070ce..132d59b7c7 100644
--- a/esp32p4/src/cache/l1_icache0_acs_fail_addr.rs
+++ b/esp32p4/src/cache/l1_icache0_acs_fail_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE0_ACS_FAIL_ADDR")
-            .field(
-                "l1_icache0_fail_addr",
-                &format_args!("{}", self.l1_icache0_fail_addr().bits()),
-            )
+            .field("l1_icache0_fail_addr", &self.l1_icache0_fail_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_ACS_FAIL_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_acs_fail_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE0_ACS_FAIL_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE0_ACS_FAIL_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache0_acs_fail_id_attr.rs b/esp32p4/src/cache/l1_icache0_acs_fail_id_attr.rs
index e77c05f059..11ff193c0d 100644
--- a/esp32p4/src/cache/l1_icache0_acs_fail_id_attr.rs
+++ b/esp32p4/src/cache/l1_icache0_acs_fail_id_attr.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE0_ACS_FAIL_ID_ATTR")
-            .field(
-                "l1_icache0_fail_id",
-                &format_args!("{}", self.l1_icache0_fail_id().bits()),
-            )
-            .field(
-                "l1_icache0_fail_attr",
-                &format_args!("{}", self.l1_icache0_fail_attr().bits()),
-            )
+            .field("l1_icache0_fail_id", &self.l1_icache0_fail_id())
+            .field("l1_icache0_fail_attr", &self.l1_icache0_fail_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_ACS_FAIL_ID_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache0_acs_fail_id_attr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE0_ACS_FAIL_ID_ATTR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE0_ACS_FAIL_ID_ATTR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache0_autoload_ctrl.rs b/esp32p4/src/cache/l1_icache0_autoload_ctrl.rs
index 2d89d8461d..b2aed97269 100644
--- a/esp32p4/src/cache/l1_icache0_autoload_ctrl.rs
+++ b/esp32p4/src/cache/l1_icache0_autoload_ctrl.rs
@@ -69,43 +69,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE0_AUTOLOAD_CTRL")
-            .field(
-                "l1_icache0_autoload_ena",
-                &format_args!("{}", self.l1_icache0_autoload_ena().bit()),
-            )
-            .field(
-                "l1_icache0_autoload_done",
-                &format_args!("{}", self.l1_icache0_autoload_done().bit()),
-            )
+            .field("l1_icache0_autoload_ena", &self.l1_icache0_autoload_ena())
+            .field("l1_icache0_autoload_done", &self.l1_icache0_autoload_done())
             .field(
                 "l1_icache0_autoload_order",
-                &format_args!("{}", self.l1_icache0_autoload_order().bit()),
+                &self.l1_icache0_autoload_order(),
             )
             .field(
                 "l1_icache0_autoload_trigger_mode",
-                &format_args!("{}", self.l1_icache0_autoload_trigger_mode().bits()),
+                &self.l1_icache0_autoload_trigger_mode(),
             )
             .field(
                 "l1_icache0_autoload_sct0_ena",
-                &format_args!("{}", self.l1_icache0_autoload_sct0_ena().bit()),
+                &self.l1_icache0_autoload_sct0_ena(),
             )
             .field(
                 "l1_icache0_autoload_sct1_ena",
-                &format_args!("{}", self.l1_icache0_autoload_sct1_ena().bit()),
-            )
-            .field(
-                "l1_icache0_autoload_rgid",
-                &format_args!("{}", self.l1_icache0_autoload_rgid().bits()),
+                &self.l1_icache0_autoload_sct1_ena(),
             )
+            .field("l1_icache0_autoload_rgid", &self.l1_icache0_autoload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_AUTOLOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache0_autoload_sct0_addr.rs b/esp32p4/src/cache/l1_icache0_autoload_sct0_addr.rs
index 1e9283f5e3..be2faa6133 100644
--- a/esp32p4/src/cache/l1_icache0_autoload_sct0_addr.rs
+++ b/esp32p4/src/cache/l1_icache0_autoload_sct0_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_AUTOLOAD_SCT0_ADDR")
             .field(
                 "l1_icache0_autoload_sct0_addr",
-                &format_args!("{}", self.l1_icache0_autoload_sct0_addr().bits()),
+                &self.l1_icache0_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_AUTOLOAD_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache0_autoload_sct0_size.rs b/esp32p4/src/cache/l1_icache0_autoload_sct0_size.rs
index ed491ab39e..7f2d1c50b1 100644
--- a/esp32p4/src/cache/l1_icache0_autoload_sct0_size.rs
+++ b/esp32p4/src/cache/l1_icache0_autoload_sct0_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_AUTOLOAD_SCT0_SIZE")
             .field(
                 "l1_icache0_autoload_sct0_size",
-                &format_args!("{}", self.l1_icache0_autoload_sct0_size().bits()),
+                &self.l1_icache0_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_AUTOLOAD_SCT0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Those bits are used to configure the size of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache0_autoload_sct1_addr.rs b/esp32p4/src/cache/l1_icache0_autoload_sct1_addr.rs
index b4a1cc504e..d09f7e7990 100644
--- a/esp32p4/src/cache/l1_icache0_autoload_sct1_addr.rs
+++ b/esp32p4/src/cache/l1_icache0_autoload_sct1_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_AUTOLOAD_SCT1_ADDR")
             .field(
                 "l1_icache0_autoload_sct1_addr",
-                &format_args!("{}", self.l1_icache0_autoload_sct1_addr().bits()),
+                &self.l1_icache0_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_AUTOLOAD_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache0_autoload_sct1_size.rs b/esp32p4/src/cache/l1_icache0_autoload_sct1_size.rs
index 8697c5c358..65b56a345f 100644
--- a/esp32p4/src/cache/l1_icache0_autoload_sct1_size.rs
+++ b/esp32p4/src/cache/l1_icache0_autoload_sct1_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_AUTOLOAD_SCT1_SIZE")
             .field(
                 "l1_icache0_autoload_sct1_size",
-                &format_args!("{}", self.l1_icache0_autoload_sct1_size().bits()),
+                &self.l1_icache0_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_AUTOLOAD_SCT1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Those bits are used to configure the size of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache0_preload_addr.rs b/esp32p4/src/cache/l1_icache0_preload_addr.rs
index c1596831cb..2821f1160d 100644
--- a/esp32p4/src/cache/l1_icache0_preload_addr.rs
+++ b/esp32p4/src/cache/l1_icache0_preload_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE0_PRELOAD_ADDR")
-            .field(
-                "l1_icache0_preload_addr",
-                &format_args!("{}", self.l1_icache0_preload_addr().bits()),
-            )
+            .field("l1_icache0_preload_addr", &self.l1_icache0_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache0_preload_ctrl.rs b/esp32p4/src/cache/l1_icache0_preload_ctrl.rs
index 6738857683..ce5cc83f3a 100644
--- a/esp32p4/src/cache/l1_icache0_preload_ctrl.rs
+++ b/esp32p4/src/cache/l1_icache0_preload_ctrl.rs
@@ -42,31 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE0_PRELOAD_CTRL")
-            .field(
-                "l1_icache0_preload_ena",
-                &format_args!("{}", self.l1_icache0_preload_ena().bit()),
-            )
-            .field(
-                "l1_icache0_preload_done",
-                &format_args!("{}", self.l1_icache0_preload_done().bit()),
-            )
-            .field(
-                "l1_icache0_preload_order",
-                &format_args!("{}", self.l1_icache0_preload_order().bit()),
-            )
-            .field(
-                "l1_icache0_preload_rgid",
-                &format_args!("{}", self.l1_icache0_preload_rgid().bits()),
-            )
+            .field("l1_icache0_preload_ena", &self.l1_icache0_preload_ena())
+            .field("l1_icache0_preload_done", &self.l1_icache0_preload_done())
+            .field("l1_icache0_preload_order", &self.l1_icache0_preload_order())
+            .field("l1_icache0_preload_rgid", &self.l1_icache0_preload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_PRELOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache0_preload_size.rs b/esp32p4/src/cache/l1_icache0_preload_size.rs
index 19436df259..2ec1052532 100644
--- a/esp32p4/src/cache/l1_icache0_preload_size.rs
+++ b/esp32p4/src/cache/l1_icache0_preload_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE0_PRELOAD_SIZE")
-            .field(
-                "l1_icache0_preload_size",
-                &format_args!("{}", self.l1_icache0_preload_size().bits()),
-            )
+            .field("l1_icache0_preload_size", &self.l1_icache0_preload_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache0_prelock_conf.rs b/esp32p4/src/cache/l1_icache0_prelock_conf.rs
index 24fe159d8d..cfb9126413 100644
--- a/esp32p4/src/cache/l1_icache0_prelock_conf.rs
+++ b/esp32p4/src/cache/l1_icache0_prelock_conf.rs
@@ -37,25 +37,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_PRELOCK_CONF")
             .field(
                 "l1_icache0_prelock_sct0_en",
-                &format_args!("{}", self.l1_icache0_prelock_sct0_en().bit()),
+                &self.l1_icache0_prelock_sct0_en(),
             )
             .field(
                 "l1_icache0_prelock_sct1_en",
-                &format_args!("{}", self.l1_icache0_prelock_sct1_en().bit()),
-            )
-            .field(
-                "l1_icache0_prelock_rgid",
-                &format_args!("{}", self.l1_icache0_prelock_rgid().bits()),
+                &self.l1_icache0_prelock_sct1_en(),
             )
+            .field("l1_icache0_prelock_rgid", &self.l1_icache0_prelock_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_PRELOCK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable the first section of prelock function on L1-ICache0."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache0_prelock_sct0_addr.rs b/esp32p4/src/cache/l1_icache0_prelock_sct0_addr.rs
index 84869391e5..ec15c704d4 100644
--- a/esp32p4/src/cache/l1_icache0_prelock_sct0_addr.rs
+++ b/esp32p4/src/cache/l1_icache0_prelock_sct0_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_PRELOCK_SCT0_ADDR")
             .field(
                 "l1_icache0_prelock_sct0_addr",
-                &format_args!("{}", self.l1_icache0_prelock_sct0_addr().bits()),
+                &self.l1_icache0_prelock_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_PRELOCK_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache0_prelock_sct1_addr.rs b/esp32p4/src/cache/l1_icache0_prelock_sct1_addr.rs
index 1d8fbf16e2..9f2d11ebd5 100644
--- a/esp32p4/src/cache/l1_icache0_prelock_sct1_addr.rs
+++ b/esp32p4/src/cache/l1_icache0_prelock_sct1_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_PRELOCK_SCT1_ADDR")
             .field(
                 "l1_icache0_prelock_sct1_addr",
-                &format_args!("{}", self.l1_icache0_prelock_sct1_addr().bits()),
+                &self.l1_icache0_prelock_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_PRELOCK_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache0_prelock_sct_size.rs b/esp32p4/src/cache/l1_icache0_prelock_sct_size.rs
index 1ddae4c0c0..802b424e3e 100644
--- a/esp32p4/src/cache/l1_icache0_prelock_sct_size.rs
+++ b/esp32p4/src/cache/l1_icache0_prelock_sct_size.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE0_PRELOCK_SCT_SIZE")
             .field(
                 "l1_icache0_prelock_sct0_size",
-                &format_args!("{}", self.l1_icache0_prelock_sct0_size().bits()),
+                &self.l1_icache0_prelock_sct0_size(),
             )
             .field(
                 "l1_icache0_prelock_sct1_size",
-                &format_args!("{}", self.l1_icache0_prelock_sct1_size().bits()),
+                &self.l1_icache0_prelock_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE0_PRELOCK_SCT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache1_acs_fail_addr.rs b/esp32p4/src/cache/l1_icache1_acs_fail_addr.rs
index 62b90876e6..63430ea03f 100644
--- a/esp32p4/src/cache/l1_icache1_acs_fail_addr.rs
+++ b/esp32p4/src/cache/l1_icache1_acs_fail_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE1_ACS_FAIL_ADDR")
-            .field(
-                "l1_icache1_fail_addr",
-                &format_args!("{}", self.l1_icache1_fail_addr().bits()),
-            )
+            .field("l1_icache1_fail_addr", &self.l1_icache1_fail_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_ACS_FAIL_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_acs_fail_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE1_ACS_FAIL_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE1_ACS_FAIL_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache1_acs_fail_id_attr.rs b/esp32p4/src/cache/l1_icache1_acs_fail_id_attr.rs
index dc9f7aa925..2876240d70 100644
--- a/esp32p4/src/cache/l1_icache1_acs_fail_id_attr.rs
+++ b/esp32p4/src/cache/l1_icache1_acs_fail_id_attr.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE1_ACS_FAIL_ID_ATTR")
-            .field(
-                "l1_icache1_fail_id",
-                &format_args!("{}", self.l1_icache1_fail_id().bits()),
-            )
-            .field(
-                "l1_icache1_fail_attr",
-                &format_args!("{}", self.l1_icache1_fail_attr().bits()),
-            )
+            .field("l1_icache1_fail_id", &self.l1_icache1_fail_id())
+            .field("l1_icache1_fail_attr", &self.l1_icache1_fail_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_ACS_FAIL_ID_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache1_acs_fail_id_attr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE1_ACS_FAIL_ID_ATTR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE1_ACS_FAIL_ID_ATTR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache1_autoload_ctrl.rs b/esp32p4/src/cache/l1_icache1_autoload_ctrl.rs
index d6fd93543d..ca4a2d976e 100644
--- a/esp32p4/src/cache/l1_icache1_autoload_ctrl.rs
+++ b/esp32p4/src/cache/l1_icache1_autoload_ctrl.rs
@@ -69,43 +69,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE1_AUTOLOAD_CTRL")
-            .field(
-                "l1_icache1_autoload_ena",
-                &format_args!("{}", self.l1_icache1_autoload_ena().bit()),
-            )
-            .field(
-                "l1_icache1_autoload_done",
-                &format_args!("{}", self.l1_icache1_autoload_done().bit()),
-            )
+            .field("l1_icache1_autoload_ena", &self.l1_icache1_autoload_ena())
+            .field("l1_icache1_autoload_done", &self.l1_icache1_autoload_done())
             .field(
                 "l1_icache1_autoload_order",
-                &format_args!("{}", self.l1_icache1_autoload_order().bit()),
+                &self.l1_icache1_autoload_order(),
             )
             .field(
                 "l1_icache1_autoload_trigger_mode",
-                &format_args!("{}", self.l1_icache1_autoload_trigger_mode().bits()),
+                &self.l1_icache1_autoload_trigger_mode(),
             )
             .field(
                 "l1_icache1_autoload_sct0_ena",
-                &format_args!("{}", self.l1_icache1_autoload_sct0_ena().bit()),
+                &self.l1_icache1_autoload_sct0_ena(),
             )
             .field(
                 "l1_icache1_autoload_sct1_ena",
-                &format_args!("{}", self.l1_icache1_autoload_sct1_ena().bit()),
-            )
-            .field(
-                "l1_icache1_autoload_rgid",
-                &format_args!("{}", self.l1_icache1_autoload_rgid().bits()),
+                &self.l1_icache1_autoload_sct1_ena(),
             )
+            .field("l1_icache1_autoload_rgid", &self.l1_icache1_autoload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_AUTOLOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, 0: disable."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache1_autoload_sct0_addr.rs b/esp32p4/src/cache/l1_icache1_autoload_sct0_addr.rs
index 2e9bdc8152..d40f19903d 100644
--- a/esp32p4/src/cache/l1_icache1_autoload_sct0_addr.rs
+++ b/esp32p4/src/cache/l1_icache1_autoload_sct0_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_AUTOLOAD_SCT0_ADDR")
             .field(
                 "l1_icache1_autoload_sct0_addr",
-                &format_args!("{}", self.l1_icache1_autoload_sct0_addr().bits()),
+                &self.l1_icache1_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_AUTOLOAD_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache1_autoload_sct0_size.rs b/esp32p4/src/cache/l1_icache1_autoload_sct0_size.rs
index d627934be0..ab085f66c8 100644
--- a/esp32p4/src/cache/l1_icache1_autoload_sct0_size.rs
+++ b/esp32p4/src/cache/l1_icache1_autoload_sct0_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_AUTOLOAD_SCT0_SIZE")
             .field(
                 "l1_icache1_autoload_sct0_size",
-                &format_args!("{}", self.l1_icache1_autoload_sct0_size().bits()),
+                &self.l1_icache1_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_AUTOLOAD_SCT0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Those bits are used to configure the size of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache1_autoload_sct1_addr.rs b/esp32p4/src/cache/l1_icache1_autoload_sct1_addr.rs
index 7898493cf2..61e825934d 100644
--- a/esp32p4/src/cache/l1_icache1_autoload_sct1_addr.rs
+++ b/esp32p4/src/cache/l1_icache1_autoload_sct1_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_AUTOLOAD_SCT1_ADDR")
             .field(
                 "l1_icache1_autoload_sct1_addr",
-                &format_args!("{}", self.l1_icache1_autoload_sct1_addr().bits()),
+                &self.l1_icache1_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_AUTOLOAD_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache1_autoload_sct1_size.rs b/esp32p4/src/cache/l1_icache1_autoload_sct1_size.rs
index 08a842f9b6..b1dc1c9c05 100644
--- a/esp32p4/src/cache/l1_icache1_autoload_sct1_size.rs
+++ b/esp32p4/src/cache/l1_icache1_autoload_sct1_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_AUTOLOAD_SCT1_SIZE")
             .field(
                 "l1_icache1_autoload_sct1_size",
-                &format_args!("{}", self.l1_icache1_autoload_sct1_size().bits()),
+                &self.l1_icache1_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_AUTOLOAD_SCT1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Those bits are used to configure the size of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache1_preload_addr.rs b/esp32p4/src/cache/l1_icache1_preload_addr.rs
index 00a80cf486..fd62abbe71 100644
--- a/esp32p4/src/cache/l1_icache1_preload_addr.rs
+++ b/esp32p4/src/cache/l1_icache1_preload_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE1_PRELOAD_ADDR")
-            .field(
-                "l1_icache1_preload_addr",
-                &format_args!("{}", self.l1_icache1_preload_addr().bits()),
-            )
+            .field("l1_icache1_preload_addr", &self.l1_icache1_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache1_preload_ctrl.rs b/esp32p4/src/cache/l1_icache1_preload_ctrl.rs
index 0127cf83ae..895074a2cf 100644
--- a/esp32p4/src/cache/l1_icache1_preload_ctrl.rs
+++ b/esp32p4/src/cache/l1_icache1_preload_ctrl.rs
@@ -42,31 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE1_PRELOAD_CTRL")
-            .field(
-                "l1_icache1_preload_ena",
-                &format_args!("{}", self.l1_icache1_preload_ena().bit()),
-            )
-            .field(
-                "l1_icache1_preload_done",
-                &format_args!("{}", self.l1_icache1_preload_done().bit()),
-            )
-            .field(
-                "l1_icache1_preload_order",
-                &format_args!("{}", self.l1_icache1_preload_order().bit()),
-            )
-            .field(
-                "l1_icache1_preload_rgid",
-                &format_args!("{}", self.l1_icache1_preload_rgid().bits()),
-            )
+            .field("l1_icache1_preload_ena", &self.l1_icache1_preload_ena())
+            .field("l1_icache1_preload_done", &self.l1_icache1_preload_done())
+            .field("l1_icache1_preload_order", &self.l1_icache1_preload_order())
+            .field("l1_icache1_preload_rgid", &self.l1_icache1_preload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_PRELOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache1_preload_size.rs b/esp32p4/src/cache/l1_icache1_preload_size.rs
index 66af93be61..b03db071d1 100644
--- a/esp32p4/src/cache/l1_icache1_preload_size.rs
+++ b/esp32p4/src/cache/l1_icache1_preload_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE1_PRELOAD_SIZE")
-            .field(
-                "l1_icache1_preload_size",
-                &format_args!("{}", self.l1_icache1_preload_size().bits()),
-            )
+            .field("l1_icache1_preload_size", &self.l1_icache1_preload_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache1_prelock_conf.rs b/esp32p4/src/cache/l1_icache1_prelock_conf.rs
index 67fb1996c0..791d59a7f4 100644
--- a/esp32p4/src/cache/l1_icache1_prelock_conf.rs
+++ b/esp32p4/src/cache/l1_icache1_prelock_conf.rs
@@ -37,25 +37,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_PRELOCK_CONF")
             .field(
                 "l1_icache1_prelock_sct0_en",
-                &format_args!("{}", self.l1_icache1_prelock_sct0_en().bit()),
+                &self.l1_icache1_prelock_sct0_en(),
             )
             .field(
                 "l1_icache1_prelock_sct1_en",
-                &format_args!("{}", self.l1_icache1_prelock_sct1_en().bit()),
-            )
-            .field(
-                "l1_icache1_prelock_rgid",
-                &format_args!("{}", self.l1_icache1_prelock_rgid().bits()),
+                &self.l1_icache1_prelock_sct1_en(),
             )
+            .field("l1_icache1_prelock_rgid", &self.l1_icache1_prelock_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_PRELOCK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable the first section of prelock function on L1-ICache1."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache1_prelock_sct0_addr.rs b/esp32p4/src/cache/l1_icache1_prelock_sct0_addr.rs
index c0540e5f4a..f4a72cbf4a 100644
--- a/esp32p4/src/cache/l1_icache1_prelock_sct0_addr.rs
+++ b/esp32p4/src/cache/l1_icache1_prelock_sct0_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_PRELOCK_SCT0_ADDR")
             .field(
                 "l1_icache1_prelock_sct0_addr",
-                &format_args!("{}", self.l1_icache1_prelock_sct0_addr().bits()),
+                &self.l1_icache1_prelock_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_PRELOCK_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache1_prelock_sct1_addr.rs b/esp32p4/src/cache/l1_icache1_prelock_sct1_addr.rs
index de507c9fa1..347d595708 100644
--- a/esp32p4/src/cache/l1_icache1_prelock_sct1_addr.rs
+++ b/esp32p4/src/cache/l1_icache1_prelock_sct1_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_PRELOCK_SCT1_ADDR")
             .field(
                 "l1_icache1_prelock_sct1_addr",
-                &format_args!("{}", self.l1_icache1_prelock_sct1_addr().bits()),
+                &self.l1_icache1_prelock_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_PRELOCK_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache1_prelock_sct_size.rs b/esp32p4/src/cache/l1_icache1_prelock_sct_size.rs
index f6a90724a2..5c3630c2cb 100644
--- a/esp32p4/src/cache/l1_icache1_prelock_sct_size.rs
+++ b/esp32p4/src/cache/l1_icache1_prelock_sct_size.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE1_PRELOCK_SCT_SIZE")
             .field(
                 "l1_icache1_prelock_sct0_size",
-                &format_args!("{}", self.l1_icache1_prelock_sct0_size().bits()),
+                &self.l1_icache1_prelock_sct0_size(),
             )
             .field(
                 "l1_icache1_prelock_sct1_size",
-                &format_args!("{}", self.l1_icache1_prelock_sct1_size().bits()),
+                &self.l1_icache1_prelock_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE1_PRELOCK_SCT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_icache2_acs_fail_addr.rs b/esp32p4/src/cache/l1_icache2_acs_fail_addr.rs
index 975bbbec52..80b58ecd90 100644
--- a/esp32p4/src/cache/l1_icache2_acs_fail_addr.rs
+++ b/esp32p4/src/cache/l1_icache2_acs_fail_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE2_ACS_FAIL_ADDR")
-            .field(
-                "l1_icache2_fail_addr",
-                &format_args!("{}", self.l1_icache2_fail_addr().bits()),
-            )
+            .field("l1_icache2_fail_addr", &self.l1_icache2_fail_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_ACS_FAIL_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_acs_fail_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_ACS_FAIL_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_ACS_FAIL_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache2_acs_fail_id_attr.rs b/esp32p4/src/cache/l1_icache2_acs_fail_id_attr.rs
index 761d49ad02..93527c533c 100644
--- a/esp32p4/src/cache/l1_icache2_acs_fail_id_attr.rs
+++ b/esp32p4/src/cache/l1_icache2_acs_fail_id_attr.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE2_ACS_FAIL_ID_ATTR")
-            .field(
-                "l1_icache2_fail_id",
-                &format_args!("{}", self.l1_icache2_fail_id().bits()),
-            )
-            .field(
-                "l1_icache2_fail_attr",
-                &format_args!("{}", self.l1_icache2_fail_attr().bits()),
-            )
+            .field("l1_icache2_fail_id", &self.l1_icache2_fail_id())
+            .field("l1_icache2_fail_attr", &self.l1_icache2_fail_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_ACS_FAIL_ID_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_acs_fail_id_attr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_ACS_FAIL_ID_ATTR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_ACS_FAIL_ID_ATTR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache2_autoload_ctrl.rs b/esp32p4/src/cache/l1_icache2_autoload_ctrl.rs
index 4d19422b05..2a7c317129 100644
--- a/esp32p4/src/cache/l1_icache2_autoload_ctrl.rs
+++ b/esp32p4/src/cache/l1_icache2_autoload_ctrl.rs
@@ -55,43 +55,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE2_AUTOLOAD_CTRL")
-            .field(
-                "l1_icache2_autoload_ena",
-                &format_args!("{}", self.l1_icache2_autoload_ena().bit()),
-            )
-            .field(
-                "l1_icache2_autoload_done",
-                &format_args!("{}", self.l1_icache2_autoload_done().bit()),
-            )
+            .field("l1_icache2_autoload_ena", &self.l1_icache2_autoload_ena())
+            .field("l1_icache2_autoload_done", &self.l1_icache2_autoload_done())
             .field(
                 "l1_icache2_autoload_order",
-                &format_args!("{}", self.l1_icache2_autoload_order().bit()),
+                &self.l1_icache2_autoload_order(),
             )
             .field(
                 "l1_icache2_autoload_trigger_mode",
-                &format_args!("{}", self.l1_icache2_autoload_trigger_mode().bits()),
+                &self.l1_icache2_autoload_trigger_mode(),
             )
             .field(
                 "l1_icache2_autoload_sct0_ena",
-                &format_args!("{}", self.l1_icache2_autoload_sct0_ena().bit()),
+                &self.l1_icache2_autoload_sct0_ena(),
             )
             .field(
                 "l1_icache2_autoload_sct1_ena",
-                &format_args!("{}", self.l1_icache2_autoload_sct1_ena().bit()),
-            )
-            .field(
-                "l1_icache2_autoload_rgid",
-                &format_args!("{}", self.l1_icache2_autoload_rgid().bits()),
+                &self.l1_icache2_autoload_sct1_ena(),
             )
+            .field("l1_icache2_autoload_rgid", &self.l1_icache2_autoload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_AUTOLOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_AUTOLOAD_CTRL_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_AUTOLOAD_CTRL_SPEC {
diff --git a/esp32p4/src/cache/l1_icache2_autoload_sct0_addr.rs b/esp32p4/src/cache/l1_icache2_autoload_sct0_addr.rs
index ef732ab4d9..3260abf5b8 100644
--- a/esp32p4/src/cache/l1_icache2_autoload_sct0_addr.rs
+++ b/esp32p4/src/cache/l1_icache2_autoload_sct0_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_AUTOLOAD_SCT0_ADDR")
             .field(
                 "l1_icache2_autoload_sct0_addr",
-                &format_args!("{}", self.l1_icache2_autoload_sct0_addr().bits()),
+                &self.l1_icache2_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_AUTOLOAD_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct0_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_AUTOLOAD_SCT0_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_AUTOLOAD_SCT0_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache2_autoload_sct0_size.rs b/esp32p4/src/cache/l1_icache2_autoload_sct0_size.rs
index d1d013efdb..4406852e2b 100644
--- a/esp32p4/src/cache/l1_icache2_autoload_sct0_size.rs
+++ b/esp32p4/src/cache/l1_icache2_autoload_sct0_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_AUTOLOAD_SCT0_SIZE")
             .field(
                 "l1_icache2_autoload_sct0_size",
-                &format_args!("{}", self.l1_icache2_autoload_sct0_size().bits()),
+                &self.l1_icache2_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_AUTOLOAD_SCT0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct0_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_AUTOLOAD_SCT0_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_AUTOLOAD_SCT0_SIZE_SPEC {
diff --git a/esp32p4/src/cache/l1_icache2_autoload_sct1_addr.rs b/esp32p4/src/cache/l1_icache2_autoload_sct1_addr.rs
index 382b428cf6..fec04ac3b6 100644
--- a/esp32p4/src/cache/l1_icache2_autoload_sct1_addr.rs
+++ b/esp32p4/src/cache/l1_icache2_autoload_sct1_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_AUTOLOAD_SCT1_ADDR")
             .field(
                 "l1_icache2_autoload_sct1_addr",
-                &format_args!("{}", self.l1_icache2_autoload_sct1_addr().bits()),
+                &self.l1_icache2_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_AUTOLOAD_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct1_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_AUTOLOAD_SCT1_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_AUTOLOAD_SCT1_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache2_autoload_sct1_size.rs b/esp32p4/src/cache/l1_icache2_autoload_sct1_size.rs
index 9c0559d830..16a7fba9bc 100644
--- a/esp32p4/src/cache/l1_icache2_autoload_sct1_size.rs
+++ b/esp32p4/src/cache/l1_icache2_autoload_sct1_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_AUTOLOAD_SCT1_SIZE")
             .field(
                 "l1_icache2_autoload_sct1_size",
-                &format_args!("{}", self.l1_icache2_autoload_sct1_size().bits()),
+                &self.l1_icache2_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_AUTOLOAD_SCT1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_autoload_sct1_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_AUTOLOAD_SCT1_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_AUTOLOAD_SCT1_SIZE_SPEC {
diff --git a/esp32p4/src/cache/l1_icache2_preload_addr.rs b/esp32p4/src/cache/l1_icache2_preload_addr.rs
index 3980a1cfb4..f336c9769e 100644
--- a/esp32p4/src/cache/l1_icache2_preload_addr.rs
+++ b/esp32p4/src/cache/l1_icache2_preload_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE2_PRELOAD_ADDR")
-            .field(
-                "l1_icache2_preload_addr",
-                &format_args!("{}", self.l1_icache2_preload_addr().bits()),
-            )
+            .field("l1_icache2_preload_addr", &self.l1_icache2_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_preload_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_PRELOAD_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_PRELOAD_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache2_preload_ctrl.rs b/esp32p4/src/cache/l1_icache2_preload_ctrl.rs
index 5fa2dccd18..8b096d8701 100644
--- a/esp32p4/src/cache/l1_icache2_preload_ctrl.rs
+++ b/esp32p4/src/cache/l1_icache2_preload_ctrl.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE2_PRELOAD_CTRL")
-            .field(
-                "l1_icache2_preload_ena",
-                &format_args!("{}", self.l1_icache2_preload_ena().bit()),
-            )
-            .field(
-                "l1_icache2_preload_done",
-                &format_args!("{}", self.l1_icache2_preload_done().bit()),
-            )
-            .field(
-                "l1_icache2_preload_order",
-                &format_args!("{}", self.l1_icache2_preload_order().bit()),
-            )
-            .field(
-                "l1_icache2_preload_rgid",
-                &format_args!("{}", self.l1_icache2_preload_rgid().bits()),
-            )
+            .field("l1_icache2_preload_ena", &self.l1_icache2_preload_ena())
+            .field("l1_icache2_preload_done", &self.l1_icache2_preload_done())
+            .field("l1_icache2_preload_order", &self.l1_icache2_preload_order())
+            .field("l1_icache2_preload_rgid", &self.l1_icache2_preload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_PRELOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_preload_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_PRELOAD_CTRL_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_PRELOAD_CTRL_SPEC {
diff --git a/esp32p4/src/cache/l1_icache2_preload_size.rs b/esp32p4/src/cache/l1_icache2_preload_size.rs
index 88acf1b2bf..943a4fa27c 100644
--- a/esp32p4/src/cache/l1_icache2_preload_size.rs
+++ b/esp32p4/src/cache/l1_icache2_preload_size.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE2_PRELOAD_SIZE")
-            .field(
-                "l1_icache2_preload_size",
-                &format_args!("{}", self.l1_icache2_preload_size().bits()),
-            )
+            .field("l1_icache2_preload_size", &self.l1_icache2_preload_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_preload_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_PRELOAD_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_PRELOAD_SIZE_SPEC {
diff --git a/esp32p4/src/cache/l1_icache2_prelock_conf.rs b/esp32p4/src/cache/l1_icache2_prelock_conf.rs
index 1430c72fae..c1c84f05db 100644
--- a/esp32p4/src/cache/l1_icache2_prelock_conf.rs
+++ b/esp32p4/src/cache/l1_icache2_prelock_conf.rs
@@ -29,25 +29,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_PRELOCK_CONF")
             .field(
                 "l1_icache2_prelock_sct0_en",
-                &format_args!("{}", self.l1_icache2_prelock_sct0_en().bit()),
+                &self.l1_icache2_prelock_sct0_en(),
             )
             .field(
                 "l1_icache2_prelock_sct1_en",
-                &format_args!("{}", self.l1_icache2_prelock_sct1_en().bit()),
-            )
-            .field(
-                "l1_icache2_prelock_rgid",
-                &format_args!("{}", self.l1_icache2_prelock_rgid().bits()),
+                &self.l1_icache2_prelock_sct1_en(),
             )
+            .field("l1_icache2_prelock_rgid", &self.l1_icache2_prelock_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_PRELOCK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_PRELOCK_CONF_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_PRELOCK_CONF_SPEC {
diff --git a/esp32p4/src/cache/l1_icache2_prelock_sct0_addr.rs b/esp32p4/src/cache/l1_icache2_prelock_sct0_addr.rs
index 3765a345ba..76d8072bf5 100644
--- a/esp32p4/src/cache/l1_icache2_prelock_sct0_addr.rs
+++ b/esp32p4/src/cache/l1_icache2_prelock_sct0_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_PRELOCK_SCT0_ADDR")
             .field(
                 "l1_icache2_prelock_sct0_addr",
-                &format_args!("{}", self.l1_icache2_prelock_sct0_addr().bits()),
+                &self.l1_icache2_prelock_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_PRELOCK_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_sct0_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_PRELOCK_SCT0_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_PRELOCK_SCT0_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache2_prelock_sct1_addr.rs b/esp32p4/src/cache/l1_icache2_prelock_sct1_addr.rs
index 81b45ce1a1..ea4353ba03 100644
--- a/esp32p4/src/cache/l1_icache2_prelock_sct1_addr.rs
+++ b/esp32p4/src/cache/l1_icache2_prelock_sct1_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_PRELOCK_SCT1_ADDR")
             .field(
                 "l1_icache2_prelock_sct1_addr",
-                &format_args!("{}", self.l1_icache2_prelock_sct1_addr().bits()),
+                &self.l1_icache2_prelock_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_PRELOCK_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_sct1_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_PRELOCK_SCT1_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_PRELOCK_SCT1_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache2_prelock_sct_size.rs b/esp32p4/src/cache/l1_icache2_prelock_sct_size.rs
index 297d69f093..8375bcb15b 100644
--- a/esp32p4/src/cache/l1_icache2_prelock_sct_size.rs
+++ b/esp32p4/src/cache/l1_icache2_prelock_sct_size.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE2_PRELOCK_SCT_SIZE")
             .field(
                 "l1_icache2_prelock_sct0_size",
-                &format_args!("{}", self.l1_icache2_prelock_sct0_size().bits()),
+                &self.l1_icache2_prelock_sct0_size(),
             )
             .field(
                 "l1_icache2_prelock_sct1_size",
-                &format_args!("{}", self.l1_icache2_prelock_sct1_size().bits()),
+                &self.l1_icache2_prelock_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE2_PRELOCK_SCT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 2 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache2_prelock_sct_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE2_PRELOCK_SCT_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE2_PRELOCK_SCT_SIZE_SPEC {
diff --git a/esp32p4/src/cache/l1_icache3_acs_fail_addr.rs b/esp32p4/src/cache/l1_icache3_acs_fail_addr.rs
index 7fcdd89ec5..3c7634f83a 100644
--- a/esp32p4/src/cache/l1_icache3_acs_fail_addr.rs
+++ b/esp32p4/src/cache/l1_icache3_acs_fail_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE3_ACS_FAIL_ADDR")
-            .field(
-                "l1_icache3_fail_addr",
-                &format_args!("{}", self.l1_icache3_fail_addr().bits()),
-            )
+            .field("l1_icache3_fail_addr", &self.l1_icache3_fail_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_ACS_FAIL_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_acs_fail_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_ACS_FAIL_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_ACS_FAIL_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache3_acs_fail_id_attr.rs b/esp32p4/src/cache/l1_icache3_acs_fail_id_attr.rs
index 909b5e8650..4827666791 100644
--- a/esp32p4/src/cache/l1_icache3_acs_fail_id_attr.rs
+++ b/esp32p4/src/cache/l1_icache3_acs_fail_id_attr.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE3_ACS_FAIL_ID_ATTR")
-            .field(
-                "l1_icache3_fail_id",
-                &format_args!("{}", self.l1_icache3_fail_id().bits()),
-            )
-            .field(
-                "l1_icache3_fail_attr",
-                &format_args!("{}", self.l1_icache3_fail_attr().bits()),
-            )
+            .field("l1_icache3_fail_id", &self.l1_icache3_fail_id())
+            .field("l1_icache3_fail_attr", &self.l1_icache3_fail_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_ACS_FAIL_ID_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-ICache0 Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_acs_fail_id_attr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_ACS_FAIL_ID_ATTR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_ACS_FAIL_ID_ATTR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache3_autoload_ctrl.rs b/esp32p4/src/cache/l1_icache3_autoload_ctrl.rs
index 4c4772435a..d888fbfbae 100644
--- a/esp32p4/src/cache/l1_icache3_autoload_ctrl.rs
+++ b/esp32p4/src/cache/l1_icache3_autoload_ctrl.rs
@@ -55,43 +55,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE3_AUTOLOAD_CTRL")
-            .field(
-                "l1_icache3_autoload_ena",
-                &format_args!("{}", self.l1_icache3_autoload_ena().bit()),
-            )
-            .field(
-                "l1_icache3_autoload_done",
-                &format_args!("{}", self.l1_icache3_autoload_done().bit()),
-            )
+            .field("l1_icache3_autoload_ena", &self.l1_icache3_autoload_ena())
+            .field("l1_icache3_autoload_done", &self.l1_icache3_autoload_done())
             .field(
                 "l1_icache3_autoload_order",
-                &format_args!("{}", self.l1_icache3_autoload_order().bit()),
+                &self.l1_icache3_autoload_order(),
             )
             .field(
                 "l1_icache3_autoload_trigger_mode",
-                &format_args!("{}", self.l1_icache3_autoload_trigger_mode().bits()),
+                &self.l1_icache3_autoload_trigger_mode(),
             )
             .field(
                 "l1_icache3_autoload_sct0_ena",
-                &format_args!("{}", self.l1_icache3_autoload_sct0_ena().bit()),
+                &self.l1_icache3_autoload_sct0_ena(),
             )
             .field(
                 "l1_icache3_autoload_sct1_ena",
-                &format_args!("{}", self.l1_icache3_autoload_sct1_ena().bit()),
-            )
-            .field(
-                "l1_icache3_autoload_rgid",
-                &format_args!("{}", self.l1_icache3_autoload_rgid().bits()),
+                &self.l1_icache3_autoload_sct1_ena(),
             )
+            .field("l1_icache3_autoload_rgid", &self.l1_icache3_autoload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_AUTOLOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 autoload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_AUTOLOAD_CTRL_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_AUTOLOAD_CTRL_SPEC {
diff --git a/esp32p4/src/cache/l1_icache3_autoload_sct0_addr.rs b/esp32p4/src/cache/l1_icache3_autoload_sct0_addr.rs
index 8d88a04ff9..830bf6504e 100644
--- a/esp32p4/src/cache/l1_icache3_autoload_sct0_addr.rs
+++ b/esp32p4/src/cache/l1_icache3_autoload_sct0_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_AUTOLOAD_SCT0_ADDR")
             .field(
                 "l1_icache3_autoload_sct0_addr",
-                &format_args!("{}", self.l1_icache3_autoload_sct0_addr().bits()),
+                &self.l1_icache3_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_AUTOLOAD_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 autoload section 0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct0_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_AUTOLOAD_SCT0_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_AUTOLOAD_SCT0_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache3_autoload_sct0_size.rs b/esp32p4/src/cache/l1_icache3_autoload_sct0_size.rs
index beba0af087..01ccd49849 100644
--- a/esp32p4/src/cache/l1_icache3_autoload_sct0_size.rs
+++ b/esp32p4/src/cache/l1_icache3_autoload_sct0_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_AUTOLOAD_SCT0_SIZE")
             .field(
                 "l1_icache3_autoload_sct0_size",
-                &format_args!("{}", self.l1_icache3_autoload_sct0_size().bits()),
+                &self.l1_icache3_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_AUTOLOAD_SCT0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 autoload section 0 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct0_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_AUTOLOAD_SCT0_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_AUTOLOAD_SCT0_SIZE_SPEC {
diff --git a/esp32p4/src/cache/l1_icache3_autoload_sct1_addr.rs b/esp32p4/src/cache/l1_icache3_autoload_sct1_addr.rs
index 22c5cb1197..e162b525a7 100644
--- a/esp32p4/src/cache/l1_icache3_autoload_sct1_addr.rs
+++ b/esp32p4/src/cache/l1_icache3_autoload_sct1_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_AUTOLOAD_SCT1_ADDR")
             .field(
                 "l1_icache3_autoload_sct1_addr",
-                &format_args!("{}", self.l1_icache3_autoload_sct1_addr().bits()),
+                &self.l1_icache3_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_AUTOLOAD_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 autoload section 1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct1_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_AUTOLOAD_SCT1_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_AUTOLOAD_SCT1_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache3_autoload_sct1_size.rs b/esp32p4/src/cache/l1_icache3_autoload_sct1_size.rs
index 06bcce8e2d..fb08808302 100644
--- a/esp32p4/src/cache/l1_icache3_autoload_sct1_size.rs
+++ b/esp32p4/src/cache/l1_icache3_autoload_sct1_size.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_AUTOLOAD_SCT1_SIZE")
             .field(
                 "l1_icache3_autoload_sct1_size",
-                &format_args!("{}", self.l1_icache3_autoload_sct1_size().bits()),
+                &self.l1_icache3_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_AUTOLOAD_SCT1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 autoload section 1 size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_autoload_sct1_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_AUTOLOAD_SCT1_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_AUTOLOAD_SCT1_SIZE_SPEC {
diff --git a/esp32p4/src/cache/l1_icache3_preload_addr.rs b/esp32p4/src/cache/l1_icache3_preload_addr.rs
index e4eff512d2..60f82797a7 100644
--- a/esp32p4/src/cache/l1_icache3_preload_addr.rs
+++ b/esp32p4/src/cache/l1_icache3_preload_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE3_PRELOAD_ADDR")
-            .field(
-                "l1_icache3_preload_addr",
-                &format_args!("{}", self.l1_icache3_preload_addr().bits()),
-            )
+            .field("l1_icache3_preload_addr", &self.l1_icache3_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 preload address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_preload_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_PRELOAD_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_PRELOAD_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache3_preload_ctrl.rs b/esp32p4/src/cache/l1_icache3_preload_ctrl.rs
index 005fd3b7c0..42ae0f6bd4 100644
--- a/esp32p4/src/cache/l1_icache3_preload_ctrl.rs
+++ b/esp32p4/src/cache/l1_icache3_preload_ctrl.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE3_PRELOAD_CTRL")
-            .field(
-                "l1_icache3_preload_ena",
-                &format_args!("{}", self.l1_icache3_preload_ena().bit()),
-            )
-            .field(
-                "l1_icache3_preload_done",
-                &format_args!("{}", self.l1_icache3_preload_done().bit()),
-            )
-            .field(
-                "l1_icache3_preload_order",
-                &format_args!("{}", self.l1_icache3_preload_order().bit()),
-            )
-            .field(
-                "l1_icache3_preload_rgid",
-                &format_args!("{}", self.l1_icache3_preload_rgid().bits()),
-            )
+            .field("l1_icache3_preload_ena", &self.l1_icache3_preload_ena())
+            .field("l1_icache3_preload_done", &self.l1_icache3_preload_done())
+            .field("l1_icache3_preload_order", &self.l1_icache3_preload_order())
+            .field("l1_icache3_preload_rgid", &self.l1_icache3_preload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_PRELOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 preload-operation control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_preload_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_PRELOAD_CTRL_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_PRELOAD_CTRL_SPEC {
diff --git a/esp32p4/src/cache/l1_icache3_preload_size.rs b/esp32p4/src/cache/l1_icache3_preload_size.rs
index cc77e54790..bd8f85215a 100644
--- a/esp32p4/src/cache/l1_icache3_preload_size.rs
+++ b/esp32p4/src/cache/l1_icache3_preload_size.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE3_PRELOAD_SIZE")
-            .field(
-                "l1_icache3_preload_size",
-                &format_args!("{}", self.l1_icache3_preload_size().bits()),
-            )
+            .field("l1_icache3_preload_size", &self.l1_icache3_preload_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 preload size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_preload_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_PRELOAD_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_PRELOAD_SIZE_SPEC {
diff --git a/esp32p4/src/cache/l1_icache3_prelock_conf.rs b/esp32p4/src/cache/l1_icache3_prelock_conf.rs
index 58a4126a57..e2c7654494 100644
--- a/esp32p4/src/cache/l1_icache3_prelock_conf.rs
+++ b/esp32p4/src/cache/l1_icache3_prelock_conf.rs
@@ -29,25 +29,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_PRELOCK_CONF")
             .field(
                 "l1_icache3_prelock_sct0_en",
-                &format_args!("{}", self.l1_icache3_prelock_sct0_en().bit()),
+                &self.l1_icache3_prelock_sct0_en(),
             )
             .field(
                 "l1_icache3_prelock_sct1_en",
-                &format_args!("{}", self.l1_icache3_prelock_sct1_en().bit()),
-            )
-            .field(
-                "l1_icache3_prelock_rgid",
-                &format_args!("{}", self.l1_icache3_prelock_rgid().bits()),
+                &self.l1_icache3_prelock_sct1_en(),
             )
+            .field("l1_icache3_prelock_rgid", &self.l1_icache3_prelock_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_PRELOCK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 prelock configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_PRELOCK_CONF_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_PRELOCK_CONF_SPEC {
diff --git a/esp32p4/src/cache/l1_icache3_prelock_sct0_addr.rs b/esp32p4/src/cache/l1_icache3_prelock_sct0_addr.rs
index 95a8794a46..a9854b1ee7 100644
--- a/esp32p4/src/cache/l1_icache3_prelock_sct0_addr.rs
+++ b/esp32p4/src/cache/l1_icache3_prelock_sct0_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_PRELOCK_SCT0_ADDR")
             .field(
                 "l1_icache3_prelock_sct0_addr",
-                &format_args!("{}", self.l1_icache3_prelock_sct0_addr().bits()),
+                &self.l1_icache3_prelock_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_PRELOCK_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 prelock section0 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_sct0_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_PRELOCK_SCT0_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_PRELOCK_SCT0_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache3_prelock_sct1_addr.rs b/esp32p4/src/cache/l1_icache3_prelock_sct1_addr.rs
index 3d92a27d63..fdf38eb453 100644
--- a/esp32p4/src/cache/l1_icache3_prelock_sct1_addr.rs
+++ b/esp32p4/src/cache/l1_icache3_prelock_sct1_addr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_PRELOCK_SCT1_ADDR")
             .field(
                 "l1_icache3_prelock_sct1_addr",
-                &format_args!("{}", self.l1_icache3_prelock_sct1_addr().bits()),
+                &self.l1_icache3_prelock_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_PRELOCK_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 prelock section1 address configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_sct1_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_PRELOCK_SCT1_ADDR_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_PRELOCK_SCT1_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l1_icache3_prelock_sct_size.rs b/esp32p4/src/cache/l1_icache3_prelock_sct_size.rs
index 60466d4f91..62d929570e 100644
--- a/esp32p4/src/cache/l1_icache3_prelock_sct_size.rs
+++ b/esp32p4/src/cache/l1_icache3_prelock_sct_size.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("L1_ICACHE3_PRELOCK_SCT_SIZE")
             .field(
                 "l1_icache3_prelock_sct0_size",
-                &format_args!("{}", self.l1_icache3_prelock_sct0_size().bits()),
+                &self.l1_icache3_prelock_sct0_size(),
             )
             .field(
                 "l1_icache3_prelock_sct1_size",
-                &format_args!("{}", self.l1_icache3_prelock_sct1_size().bits()),
+                &self.l1_icache3_prelock_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE3_PRELOCK_SCT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache 3 prelock section size configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache3_prelock_sct_size::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE3_PRELOCK_SCT_SIZE_SPEC;
 impl crate::RegisterSpec for L1_ICACHE3_PRELOCK_SCT_SIZE_SPEC {
diff --git a/esp32p4/src/cache/l1_icache_blocksize_conf.rs b/esp32p4/src/cache/l1_icache_blocksize_conf.rs
index 377cad15c2..327a538c64 100644
--- a/esp32p4/src/cache/l1_icache_blocksize_conf.rs
+++ b/esp32p4/src/cache/l1_icache_blocksize_conf.rs
@@ -48,39 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE_BLOCKSIZE_CONF")
-            .field(
-                "l1_icache_blocksize_8",
-                &format_args!("{}", self.l1_icache_blocksize_8().bit()),
-            )
-            .field(
-                "l1_icache_blocksize_16",
-                &format_args!("{}", self.l1_icache_blocksize_16().bit()),
-            )
-            .field(
-                "l1_icache_blocksize_32",
-                &format_args!("{}", self.l1_icache_blocksize_32().bit()),
-            )
-            .field(
-                "l1_icache_blocksize_64",
-                &format_args!("{}", self.l1_icache_blocksize_64().bit()),
-            )
-            .field(
-                "l1_icache_blocksize_128",
-                &format_args!("{}", self.l1_icache_blocksize_128().bit()),
-            )
-            .field(
-                "l1_icache_blocksize_256",
-                &format_args!("{}", self.l1_icache_blocksize_256().bit()),
-            )
+            .field("l1_icache_blocksize_8", &self.l1_icache_blocksize_8())
+            .field("l1_icache_blocksize_16", &self.l1_icache_blocksize_16())
+            .field("l1_icache_blocksize_32", &self.l1_icache_blocksize_32())
+            .field("l1_icache_blocksize_64", &self.l1_icache_blocksize_64())
+            .field("l1_icache_blocksize_128", &self.l1_icache_blocksize_128())
+            .field("l1_icache_blocksize_256", &self.l1_icache_blocksize_256())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE_BLOCKSIZE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache BlockSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache_blocksize_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE_BLOCKSIZE_CONF_SPEC;
 impl crate::RegisterSpec for L1_ICACHE_BLOCKSIZE_CONF_SPEC {
diff --git a/esp32p4/src/cache/l1_icache_cachesize_conf.rs b/esp32p4/src/cache/l1_icache_cachesize_conf.rs
index 93d6cf6301..5112781308 100644
--- a/esp32p4/src/cache/l1_icache_cachesize_conf.rs
+++ b/esp32p4/src/cache/l1_icache_cachesize_conf.rs
@@ -97,67 +97,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE_CACHESIZE_CONF")
-            .field(
-                "l1_icache_cachesize_256",
-                &format_args!("{}", self.l1_icache_cachesize_256().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_512",
-                &format_args!("{}", self.l1_icache_cachesize_512().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_1k",
-                &format_args!("{}", self.l1_icache_cachesize_1k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_2k",
-                &format_args!("{}", self.l1_icache_cachesize_2k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_4k",
-                &format_args!("{}", self.l1_icache_cachesize_4k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_8k",
-                &format_args!("{}", self.l1_icache_cachesize_8k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_16k",
-                &format_args!("{}", self.l1_icache_cachesize_16k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_32k",
-                &format_args!("{}", self.l1_icache_cachesize_32k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_64k",
-                &format_args!("{}", self.l1_icache_cachesize_64k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_128k",
-                &format_args!("{}", self.l1_icache_cachesize_128k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_256k",
-                &format_args!("{}", self.l1_icache_cachesize_256k().bit()),
-            )
-            .field(
-                "l1_icache_cachesize_512k",
-                &format_args!("{}", self.l1_icache_cachesize_512k().bit()),
-            )
+            .field("l1_icache_cachesize_256", &self.l1_icache_cachesize_256())
+            .field("l1_icache_cachesize_512", &self.l1_icache_cachesize_512())
+            .field("l1_icache_cachesize_1k", &self.l1_icache_cachesize_1k())
+            .field("l1_icache_cachesize_2k", &self.l1_icache_cachesize_2k())
+            .field("l1_icache_cachesize_4k", &self.l1_icache_cachesize_4k())
+            .field("l1_icache_cachesize_8k", &self.l1_icache_cachesize_8k())
+            .field("l1_icache_cachesize_16k", &self.l1_icache_cachesize_16k())
+            .field("l1_icache_cachesize_32k", &self.l1_icache_cachesize_32k())
+            .field("l1_icache_cachesize_64k", &self.l1_icache_cachesize_64k())
+            .field("l1_icache_cachesize_128k", &self.l1_icache_cachesize_128k())
+            .field("l1_icache_cachesize_256k", &self.l1_icache_cachesize_256k())
+            .field("l1_icache_cachesize_512k", &self.l1_icache_cachesize_512k())
             .field(
                 "l1_icache_cachesize_1024k",
-                &format_args!("{}", self.l1_icache_cachesize_1024k().bit()),
+                &self.l1_icache_cachesize_1024k(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE_CACHESIZE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1 instruction Cache CacheSize mode configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l1_icache_cachesize_conf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L1_ICACHE_CACHESIZE_CONF_SPEC;
 impl crate::RegisterSpec for L1_ICACHE_CACHESIZE_CONF_SPEC {
diff --git a/esp32p4/src/cache/l1_icache_ctrl.rs b/esp32p4/src/cache/l1_icache_ctrl.rs
index e9c0b0ac59..ddc60d7f24 100644
--- a/esp32p4/src/cache/l1_icache_ctrl.rs
+++ b/esp32p4/src/cache/l1_icache_ctrl.rs
@@ -49,35 +49,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_ICACHE_CTRL")
-            .field(
-                "l1_icache_shut_ibus0",
-                &format_args!("{}", self.l1_icache_shut_ibus0().bit()),
-            )
-            .field(
-                "l1_icache_shut_ibus1",
-                &format_args!("{}", self.l1_icache_shut_ibus1().bit()),
-            )
-            .field(
-                "l1_icache_shut_ibus2",
-                &format_args!("{}", self.l1_icache_shut_ibus2().bit()),
-            )
-            .field(
-                "l1_icache_shut_ibus3",
-                &format_args!("{}", self.l1_icache_shut_ibus3().bit()),
-            )
-            .field(
-                "l1_icache_undef_op",
-                &format_args!("{}", self.l1_icache_undef_op().bits()),
-            )
+            .field("l1_icache_shut_ibus0", &self.l1_icache_shut_ibus0())
+            .field("l1_icache_shut_ibus1", &self.l1_icache_shut_ibus1())
+            .field("l1_icache_shut_ibus2", &self.l1_icache_shut_ibus2())
+            .field("l1_icache_shut_ibus3", &self.l1_icache_shut_ibus3())
+            .field("l1_icache_undef_op", &self.l1_icache_undef_op())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_ICACHE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l1_unallocate_buffer_clear.rs b/esp32p4/src/cache/l1_unallocate_buffer_clear.rs
index 786eb62f35..17abc0217b 100644
--- a/esp32p4/src/cache/l1_unallocate_buffer_clear.rs
+++ b/esp32p4/src/cache/l1_unallocate_buffer_clear.rs
@@ -49,35 +49,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_UNALLOCATE_BUFFER_CLEAR")
-            .field(
-                "l1_icache0_unalloc_clr",
-                &format_args!("{}", self.l1_icache0_unalloc_clr().bit()),
-            )
-            .field(
-                "l1_icache1_unalloc_clr",
-                &format_args!("{}", self.l1_icache1_unalloc_clr().bit()),
-            )
-            .field(
-                "l1_icache2_unalloc_clr",
-                &format_args!("{}", self.l1_icache2_unalloc_clr().bit()),
-            )
-            .field(
-                "l1_icache3_unalloc_clr",
-                &format_args!("{}", self.l1_icache3_unalloc_clr().bit()),
-            )
-            .field(
-                "l1_dcache_unalloc_clr",
-                &format_args!("{}", self.l1_dcache_unalloc_clr().bit()),
-            )
+            .field("l1_icache0_unalloc_clr", &self.l1_icache0_unalloc_clr())
+            .field("l1_icache1_unalloc_clr", &self.l1_icache1_unalloc_clr())
+            .field("l1_icache2_unalloc_clr", &self.l1_icache2_unalloc_clr())
+            .field("l1_icache3_unalloc_clr", &self.l1_icache3_unalloc_clr())
+            .field("l1_dcache_unalloc_clr", &self.l1_dcache_unalloc_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_UNALLOCATE_BUFFER_CLEAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to clear the unallocate request buffer of l1 icache0 where the unallocate request is responsed but not completed."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_bypass_cache_conf.rs b/esp32p4/src/cache/l2_bypass_cache_conf.rs
index 70d3715286..bb68fc3deb 100644
--- a/esp32p4/src/cache/l2_bypass_cache_conf.rs
+++ b/esp32p4/src/cache/l2_bypass_cache_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_BYPASS_CACHE_CONF")
-            .field(
-                "bypass_l2_cache_en",
-                &format_args!("{}", self.bypass_l2_cache_en().bit()),
-            )
+            .field("bypass_l2_cache_en", &self.bypass_l2_cache_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_BYPASS_CACHE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 5 - The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_access_attr_ctrl.rs b/esp32p4/src/cache/l2_cache_access_attr_ctrl.rs
index 319b2b16a9..e61ec270f3 100644
--- a/esp32p4/src/cache/l2_cache_access_attr_ctrl.rs
+++ b/esp32p4/src/cache/l2_cache_access_attr_ctrl.rs
@@ -44,31 +44,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACCESS_ATTR_CTRL")
-            .field(
-                "l2_cache_access_force_cc",
-                &format_args!("{}", self.l2_cache_access_force_cc().bit()),
-            )
-            .field(
-                "l2_cache_access_force_wb",
-                &format_args!("{}", self.l2_cache_access_force_wb().bit()),
-            )
+            .field("l2_cache_access_force_cc", &self.l2_cache_access_force_cc())
+            .field("l2_cache_access_force_wb", &self.l2_cache_access_force_wb())
             .field(
                 "l2_cache_access_force_wma",
-                &format_args!("{}", self.l2_cache_access_force_wma().bit()),
+                &self.l2_cache_access_force_wma(),
             )
             .field(
                 "l2_cache_access_force_rma",
-                &format_args!("{}", self.l2_cache_access_force_rma().bit()),
+                &self.l2_cache_access_force_rma(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACCESS_ATTR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_acs_cnt_ctrl.rs b/esp32p4/src/cache/l2_cache_acs_cnt_ctrl.rs
index cdd110e431..5ea9dba907 100644
--- a/esp32p4/src/cache/l2_cache_acs_cnt_ctrl.rs
+++ b/esp32p4/src/cache/l2_cache_acs_cnt_ctrl.rs
@@ -108,63 +108,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_CNT_CTRL")
-            .field(
-                "l2_ibus0_cnt_ena",
-                &format_args!("{}", self.l2_ibus0_cnt_ena().bit()),
-            )
-            .field(
-                "l2_ibus1_cnt_ena",
-                &format_args!("{}", self.l2_ibus1_cnt_ena().bit()),
-            )
-            .field(
-                "l2_ibus2_cnt_ena",
-                &format_args!("{}", self.l2_ibus2_cnt_ena().bit()),
-            )
-            .field(
-                "l2_ibus3_cnt_ena",
-                &format_args!("{}", self.l2_ibus3_cnt_ena().bit()),
-            )
-            .field(
-                "l2_dbus0_cnt_ena",
-                &format_args!("{}", self.l2_dbus0_cnt_ena().bit()),
-            )
-            .field(
-                "l2_dbus1_cnt_ena",
-                &format_args!("{}", self.l2_dbus1_cnt_ena().bit()),
-            )
-            .field(
-                "l2_dbus2_cnt_ena",
-                &format_args!("{}", self.l2_dbus2_cnt_ena().bit()),
-            )
-            .field(
-                "l2_dbus3_cnt_ena",
-                &format_args!("{}", self.l2_dbus3_cnt_ena().bit()),
-            )
-            .field(
-                "l2_ibus2_cnt_clr",
-                &format_args!("{}", self.l2_ibus2_cnt_clr().bit()),
-            )
-            .field(
-                "l2_ibus3_cnt_clr",
-                &format_args!("{}", self.l2_ibus3_cnt_clr().bit()),
-            )
-            .field(
-                "l2_dbus2_cnt_clr",
-                &format_args!("{}", self.l2_dbus2_cnt_clr().bit()),
-            )
-            .field(
-                "l2_dbus3_cnt_clr",
-                &format_args!("{}", self.l2_dbus3_cnt_clr().bit()),
-            )
+            .field("l2_ibus0_cnt_ena", &self.l2_ibus0_cnt_ena())
+            .field("l2_ibus1_cnt_ena", &self.l2_ibus1_cnt_ena())
+            .field("l2_ibus2_cnt_ena", &self.l2_ibus2_cnt_ena())
+            .field("l2_ibus3_cnt_ena", &self.l2_ibus3_cnt_ena())
+            .field("l2_dbus0_cnt_ena", &self.l2_dbus0_cnt_ena())
+            .field("l2_dbus1_cnt_ena", &self.l2_dbus1_cnt_ena())
+            .field("l2_dbus2_cnt_ena", &self.l2_dbus2_cnt_ena())
+            .field("l2_dbus3_cnt_ena", &self.l2_dbus3_cnt_ena())
+            .field("l2_ibus2_cnt_clr", &self.l2_ibus2_cnt_clr())
+            .field("l2_ibus3_cnt_clr", &self.l2_ibus3_cnt_clr())
+            .field("l2_dbus2_cnt_clr", &self.l2_dbus2_cnt_clr())
+            .field("l2_dbus3_cnt_clr", &self.l2_dbus3_cnt_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_CNT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - The bit is used to enable ibus0 counter in L2-Cache."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_acs_cnt_int_clr.rs b/esp32p4/src/cache/l2_cache_acs_cnt_int_clr.rs
index 2a2680bad2..962795ac70 100644
--- a/esp32p4/src/cache/l2_cache_acs_cnt_int_clr.rs
+++ b/esp32p4/src/cache/l2_cache_acs_cnt_int_clr.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_CNT_INT_CLR")
-            .field(
-                "l2_ibus2_ovf_int_clr",
-                &format_args!("{}", self.l2_ibus2_ovf_int_clr().bit()),
-            )
-            .field(
-                "l2_ibus3_ovf_int_clr",
-                &format_args!("{}", self.l2_ibus3_ovf_int_clr().bit()),
-            )
-            .field(
-                "l2_dbus2_ovf_int_clr",
-                &format_args!("{}", self.l2_dbus2_ovf_int_clr().bit()),
-            )
-            .field(
-                "l2_dbus3_ovf_int_clr",
-                &format_args!("{}", self.l2_dbus3_ovf_int_clr().bit()),
-            )
+            .field("l2_ibus2_ovf_int_clr", &self.l2_ibus2_ovf_int_clr())
+            .field("l2_ibus3_ovf_int_clr", &self.l2_ibus3_ovf_int_clr())
+            .field("l2_dbus2_ovf_int_clr", &self.l2_dbus2_ovf_int_clr())
+            .field("l2_dbus3_ovf_int_clr", &self.l2_dbus3_ovf_int_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_CNT_INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_acs_cnt_int_ena.rs b/esp32p4/src/cache/l2_cache_acs_cnt_int_ena.rs
index b5ec9619cb..9d17450d98 100644
--- a/esp32p4/src/cache/l2_cache_acs_cnt_int_ena.rs
+++ b/esp32p4/src/cache/l2_cache_acs_cnt_int_ena.rs
@@ -72,47 +72,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_CNT_INT_ENA")
-            .field(
-                "l2_ibus0_ovf_int_ena",
-                &format_args!("{}", self.l2_ibus0_ovf_int_ena().bit()),
-            )
-            .field(
-                "l2_ibus1_ovf_int_ena",
-                &format_args!("{}", self.l2_ibus1_ovf_int_ena().bit()),
-            )
-            .field(
-                "l2_ibus2_ovf_int_ena",
-                &format_args!("{}", self.l2_ibus2_ovf_int_ena().bit()),
-            )
-            .field(
-                "l2_ibus3_ovf_int_ena",
-                &format_args!("{}", self.l2_ibus3_ovf_int_ena().bit()),
-            )
-            .field(
-                "l2_dbus0_ovf_int_ena",
-                &format_args!("{}", self.l2_dbus0_ovf_int_ena().bit()),
-            )
-            .field(
-                "l2_dbus1_ovf_int_ena",
-                &format_args!("{}", self.l2_dbus1_ovf_int_ena().bit()),
-            )
-            .field(
-                "l2_dbus2_ovf_int_ena",
-                &format_args!("{}", self.l2_dbus2_ovf_int_ena().bit()),
-            )
-            .field(
-                "l2_dbus3_ovf_int_ena",
-                &format_args!("{}", self.l2_dbus3_ovf_int_ena().bit()),
-            )
+            .field("l2_ibus0_ovf_int_ena", &self.l2_ibus0_ovf_int_ena())
+            .field("l2_ibus1_ovf_int_ena", &self.l2_ibus1_ovf_int_ena())
+            .field("l2_ibus2_ovf_int_ena", &self.l2_ibus2_ovf_int_ena())
+            .field("l2_ibus3_ovf_int_ena", &self.l2_ibus3_ovf_int_ena())
+            .field("l2_dbus0_ovf_int_ena", &self.l2_dbus0_ovf_int_ena())
+            .field("l2_dbus1_ovf_int_ena", &self.l2_dbus1_ovf_int_ena())
+            .field("l2_dbus2_ovf_int_ena", &self.l2_dbus2_ovf_int_ena())
+            .field("l2_dbus3_ovf_int_ena", &self.l2_dbus3_ovf_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_CNT_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_acs_cnt_int_raw.rs b/esp32p4/src/cache/l2_cache_acs_cnt_int_raw.rs
index 797894f0c3..4e996ec8b5 100644
--- a/esp32p4/src/cache/l2_cache_acs_cnt_int_raw.rs
+++ b/esp32p4/src/cache/l2_cache_acs_cnt_int_raw.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_CNT_INT_RAW")
-            .field(
-                "l2_ibus0_ovf_int_raw",
-                &format_args!("{}", self.l2_ibus0_ovf_int_raw().bit()),
-            )
-            .field(
-                "l2_ibus1_ovf_int_raw",
-                &format_args!("{}", self.l2_ibus1_ovf_int_raw().bit()),
-            )
-            .field(
-                "l2_ibus2_ovf_int_raw",
-                &format_args!("{}", self.l2_ibus2_ovf_int_raw().bit()),
-            )
-            .field(
-                "l2_ibus3_ovf_int_raw",
-                &format_args!("{}", self.l2_ibus3_ovf_int_raw().bit()),
-            )
-            .field(
-                "l2_dbus0_ovf_int_raw",
-                &format_args!("{}", self.l2_dbus0_ovf_int_raw().bit()),
-            )
-            .field(
-                "l2_dbus1_ovf_int_raw",
-                &format_args!("{}", self.l2_dbus1_ovf_int_raw().bit()),
-            )
-            .field(
-                "l2_dbus2_ovf_int_raw",
-                &format_args!("{}", self.l2_dbus2_ovf_int_raw().bit()),
-            )
-            .field(
-                "l2_dbus3_ovf_int_raw",
-                &format_args!("{}", self.l2_dbus3_ovf_int_raw().bit()),
-            )
+            .field("l2_ibus0_ovf_int_raw", &self.l2_ibus0_ovf_int_raw())
+            .field("l2_ibus1_ovf_int_raw", &self.l2_ibus1_ovf_int_raw())
+            .field("l2_ibus2_ovf_int_raw", &self.l2_ibus2_ovf_int_raw())
+            .field("l2_ibus3_ovf_int_raw", &self.l2_ibus3_ovf_int_raw())
+            .field("l2_dbus0_ovf_int_raw", &self.l2_dbus0_ovf_int_raw())
+            .field("l2_dbus1_ovf_int_raw", &self.l2_dbus1_ovf_int_raw())
+            .field("l2_dbus2_ovf_int_raw", &self.l2_dbus2_ovf_int_raw())
+            .field("l2_dbus3_ovf_int_raw", &self.l2_dbus3_ovf_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_CNT_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_acs_cnt_int_st.rs b/esp32p4/src/cache/l2_cache_acs_cnt_int_st.rs
index 1093680c5d..abef66191c 100644
--- a/esp32p4/src/cache/l2_cache_acs_cnt_int_st.rs
+++ b/esp32p4/src/cache/l2_cache_acs_cnt_int_st.rs
@@ -62,47 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_CNT_INT_ST")
-            .field(
-                "l2_ibus0_ovf_int_st",
-                &format_args!("{}", self.l2_ibus0_ovf_int_st().bit()),
-            )
-            .field(
-                "l2_ibus1_ovf_int_st",
-                &format_args!("{}", self.l2_ibus1_ovf_int_st().bit()),
-            )
-            .field(
-                "l2_ibus2_ovf_int_st",
-                &format_args!("{}", self.l2_ibus2_ovf_int_st().bit()),
-            )
-            .field(
-                "l2_ibus3_ovf_int_st",
-                &format_args!("{}", self.l2_ibus3_ovf_int_st().bit()),
-            )
-            .field(
-                "l2_dbus0_ovf_int_st",
-                &format_args!("{}", self.l2_dbus0_ovf_int_st().bit()),
-            )
-            .field(
-                "l2_dbus1_ovf_int_st",
-                &format_args!("{}", self.l2_dbus1_ovf_int_st().bit()),
-            )
-            .field(
-                "l2_dbus2_ovf_int_st",
-                &format_args!("{}", self.l2_dbus2_ovf_int_st().bit()),
-            )
-            .field(
-                "l2_dbus3_ovf_int_st",
-                &format_args!("{}", self.l2_dbus3_ovf_int_st().bit()),
-            )
+            .field("l2_ibus0_ovf_int_st", &self.l2_ibus0_ovf_int_st())
+            .field("l2_ibus1_ovf_int_st", &self.l2_ibus1_ovf_int_st())
+            .field("l2_ibus2_ovf_int_st", &self.l2_ibus2_ovf_int_st())
+            .field("l2_ibus3_ovf_int_st", &self.l2_ibus3_ovf_int_st())
+            .field("l2_dbus0_ovf_int_st", &self.l2_dbus0_ovf_int_st())
+            .field("l2_dbus1_ovf_int_st", &self.l2_dbus1_ovf_int_st())
+            .field("l2_dbus2_ovf_int_st", &self.l2_dbus2_ovf_int_st())
+            .field("l2_dbus3_ovf_int_st", &self.l2_dbus3_ovf_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_CNT_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Access Counter Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_cnt_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_ACS_CNT_INT_ST_SPEC;
 impl crate::RegisterSpec for L2_CACHE_ACS_CNT_INT_ST_SPEC {
diff --git a/esp32p4/src/cache/l2_cache_acs_fail_addr.rs b/esp32p4/src/cache/l2_cache_acs_fail_addr.rs
index b2e7fe8853..4657ca4e74 100644
--- a/esp32p4/src/cache/l2_cache_acs_fail_addr.rs
+++ b/esp32p4/src/cache/l2_cache_acs_fail_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_FAIL_ADDR")
-            .field(
-                "l2_cache_fail_addr",
-                &format_args!("{}", self.l2_cache_fail_addr().bits()),
-            )
+            .field("l2_cache_fail_addr", &self.l2_cache_fail_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_FAIL_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache Access Fail Address information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_ACS_FAIL_ADDR_SPEC;
 impl crate::RegisterSpec for L2_CACHE_ACS_FAIL_ADDR_SPEC {
diff --git a/esp32p4/src/cache/l2_cache_acs_fail_ctrl.rs b/esp32p4/src/cache/l2_cache_acs_fail_ctrl.rs
index a7150265df..8b208a86b8 100644
--- a/esp32p4/src/cache/l2_cache_acs_fail_ctrl.rs
+++ b/esp32p4/src/cache/l2_cache_acs_fail_ctrl.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_ACS_FAIL_CTRL")
             .field(
                 "l2_cache_acs_fail_check_mode",
-                &format_args!("{}", self.l2_cache_acs_fail_check_mode().bit()),
+                &self.l2_cache_acs_fail_check_mode(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_FAIL_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to configure l2 cache access fail check mode. 0: the access fail is not propagated to the request, 1: the access fail is propagated to the request"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_acs_fail_id_attr.rs b/esp32p4/src/cache/l2_cache_acs_fail_id_attr.rs
index af04853018..119d44460f 100644
--- a/esp32p4/src/cache/l2_cache_acs_fail_id_attr.rs
+++ b/esp32p4/src/cache/l2_cache_acs_fail_id_attr.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_FAIL_ID_ATTR")
-            .field(
-                "l2_cache_fail_id",
-                &format_args!("{}", self.l2_cache_fail_id().bits()),
-            )
-            .field(
-                "l2_cache_fail_attr",
-                &format_args!("{}", self.l2_cache_fail_attr().bits()),
-            )
+            .field("l2_cache_fail_id", &self.l2_cache_fail_id())
+            .field("l2_cache_fail_attr", &self.l2_cache_fail_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_FAIL_ID_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache Access Fail ID/attribution information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_id_attr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_ACS_FAIL_ID_ATTR_SPEC;
 impl crate::RegisterSpec for L2_CACHE_ACS_FAIL_ID_ATTR_SPEC {
diff --git a/esp32p4/src/cache/l2_cache_acs_fail_int_ena.rs b/esp32p4/src/cache/l2_cache_acs_fail_int_ena.rs
index 32f1582b91..d834b9c0ff 100644
--- a/esp32p4/src/cache/l2_cache_acs_fail_int_ena.rs
+++ b/esp32p4/src/cache/l2_cache_acs_fail_int_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_FAIL_INT_ENA")
-            .field(
-                "l2_cache_fail_int_ena",
-                &format_args!("{}", self.l2_cache_fail_int_ena().bit()),
-            )
+            .field("l2_cache_fail_int_ena", &self.l2_cache_fail_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_FAIL_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 5 - The bit is used to enable interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_acs_fail_int_raw.rs b/esp32p4/src/cache/l2_cache_acs_fail_int_raw.rs
index 72775212b1..3a16ca6106 100644
--- a/esp32p4/src/cache/l2_cache_acs_fail_int_raw.rs
+++ b/esp32p4/src/cache/l2_cache_acs_fail_int_raw.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_FAIL_INT_RAW")
-            .field(
-                "l2_cache_fail_int_raw",
-                &format_args!("{}", self.l2_cache_fail_int_raw().bit()),
-            )
+            .field("l2_cache_fail_int_raw", &self.l2_cache_fail_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_FAIL_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 5 - The raw bit of the interrupt of access fail that occurs in L2-Cache."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_acs_fail_int_st.rs b/esp32p4/src/cache/l2_cache_acs_fail_int_st.rs
index fa8e8f93ac..94c716e5b1 100644
--- a/esp32p4/src/cache/l2_cache_acs_fail_int_st.rs
+++ b/esp32p4/src/cache/l2_cache_acs_fail_int_st.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_ACS_FAIL_INT_ST")
-            .field(
-                "l2_cache_fail_int_st",
-                &format_args!("{}", self.l2_cache_fail_int_st().bit()),
-            )
+            .field("l2_cache_fail_int_st", &self.l2_cache_fail_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_ACS_FAIL_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_acs_fail_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_ACS_FAIL_INT_ST_SPEC;
 impl crate::RegisterSpec for L2_CACHE_ACS_FAIL_INT_ST_SPEC {
diff --git a/esp32p4/src/cache/l2_cache_autoload_buf_clr_ctrl.rs b/esp32p4/src/cache/l2_cache_autoload_buf_clr_ctrl.rs
index 3cff1749c0..999e266f19 100644
--- a/esp32p4/src/cache/l2_cache_autoload_buf_clr_ctrl.rs
+++ b/esp32p4/src/cache/l2_cache_autoload_buf_clr_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_AUTOLOAD_BUF_CLR_CTRL")
-            .field(
-                "l2_cache_ald_buf_clr",
-                &format_args!("{}", self.l2_cache_ald_buf_clr().bit()),
-            )
+            .field("l2_cache_ald_buf_clr", &self.l2_cache_ald_buf_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 5 - set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, autoload will not work in L2-Cache. This bit should not be active when autoload works in L2-Cache."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_autoload_ctrl.rs b/esp32p4/src/cache/l2_cache_autoload_ctrl.rs
index 102058820e..cfe30f9a70 100644
--- a/esp32p4/src/cache/l2_cache_autoload_ctrl.rs
+++ b/esp32p4/src/cache/l2_cache_autoload_ctrl.rs
@@ -87,51 +87,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_AUTOLOAD_CTRL")
-            .field(
-                "l2_cache_autoload_ena",
-                &format_args!("{}", self.l2_cache_autoload_ena().bit()),
-            )
-            .field(
-                "l2_cache_autoload_done",
-                &format_args!("{}", self.l2_cache_autoload_done().bit()),
-            )
-            .field(
-                "l2_cache_autoload_order",
-                &format_args!("{}", self.l2_cache_autoload_order().bit()),
-            )
+            .field("l2_cache_autoload_ena", &self.l2_cache_autoload_ena())
+            .field("l2_cache_autoload_done", &self.l2_cache_autoload_done())
+            .field("l2_cache_autoload_order", &self.l2_cache_autoload_order())
             .field(
                 "l2_cache_autoload_trigger_mode",
-                &format_args!("{}", self.l2_cache_autoload_trigger_mode().bits()),
+                &self.l2_cache_autoload_trigger_mode(),
             )
             .field(
                 "l2_cache_autoload_sct0_ena",
-                &format_args!("{}", self.l2_cache_autoload_sct0_ena().bit()),
+                &self.l2_cache_autoload_sct0_ena(),
             )
             .field(
                 "l2_cache_autoload_sct1_ena",
-                &format_args!("{}", self.l2_cache_autoload_sct1_ena().bit()),
+                &self.l2_cache_autoload_sct1_ena(),
             )
             .field(
                 "l2_cache_autoload_sct2_ena",
-                &format_args!("{}", self.l2_cache_autoload_sct2_ena().bit()),
+                &self.l2_cache_autoload_sct2_ena(),
             )
             .field(
                 "l2_cache_autoload_sct3_ena",
-                &format_args!("{}", self.l2_cache_autoload_sct3_ena().bit()),
-            )
-            .field(
-                "l2_cache_autoload_rgid",
-                &format_args!("{}", self.l2_cache_autoload_rgid().bits()),
+                &self.l2_cache_autoload_sct3_ena(),
             )
+            .field("l2_cache_autoload_rgid", &self.l2_cache_autoload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, 0: disable."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_autoload_sct0_addr.rs b/esp32p4/src/cache/l2_cache_autoload_sct0_addr.rs
index 2257a33d95..99fe5cddd0 100644
--- a/esp32p4/src/cache/l2_cache_autoload_sct0_addr.rs
+++ b/esp32p4/src/cache/l2_cache_autoload_sct0_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT0_ADDR")
             .field(
                 "l2_cache_autoload_sct0_addr",
-                &format_args!("{}", self.l2_cache_autoload_sct0_addr().bits()),
+                &self.l2_cache_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_autoload_sct0_size.rs b/esp32p4/src/cache/l2_cache_autoload_sct0_size.rs
index 2e1c394e39..f14ff9ffdf 100644
--- a/esp32p4/src/cache/l2_cache_autoload_sct0_size.rs
+++ b/esp32p4/src/cache/l2_cache_autoload_sct0_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT0_SIZE")
             .field(
                 "l2_cache_autoload_sct0_size",
-                &format_args!("{}", self.l2_cache_autoload_sct0_size().bits()),
+                &self.l2_cache_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Those bits are used to configure the size of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_autoload_sct1_addr.rs b/esp32p4/src/cache/l2_cache_autoload_sct1_addr.rs
index 7ab57c648a..5a4dcd2c54 100644
--- a/esp32p4/src/cache/l2_cache_autoload_sct1_addr.rs
+++ b/esp32p4/src/cache/l2_cache_autoload_sct1_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT1_ADDR")
             .field(
                 "l2_cache_autoload_sct1_addr",
-                &format_args!("{}", self.l2_cache_autoload_sct1_addr().bits()),
+                &self.l2_cache_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_autoload_sct1_size.rs b/esp32p4/src/cache/l2_cache_autoload_sct1_size.rs
index fad9da0a4a..cc76bb3016 100644
--- a/esp32p4/src/cache/l2_cache_autoload_sct1_size.rs
+++ b/esp32p4/src/cache/l2_cache_autoload_sct1_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT1_SIZE")
             .field(
                 "l2_cache_autoload_sct1_size",
-                &format_args!("{}", self.l2_cache_autoload_sct1_size().bits()),
+                &self.l2_cache_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Those bits are used to configure the size of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_autoload_sct2_addr.rs b/esp32p4/src/cache/l2_cache_autoload_sct2_addr.rs
index 8d0e7bc667..094e475238 100644
--- a/esp32p4/src/cache/l2_cache_autoload_sct2_addr.rs
+++ b/esp32p4/src/cache/l2_cache_autoload_sct2_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT2_ADDR")
             .field(
                 "l2_cache_autoload_sct2_addr",
-                &format_args!("{}", self.l2_cache_autoload_sct2_addr().bits()),
+                &self.l2_cache_autoload_sct2_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_autoload_sct2_size.rs b/esp32p4/src/cache/l2_cache_autoload_sct2_size.rs
index 9e236668fc..6c9260287e 100644
--- a/esp32p4/src/cache/l2_cache_autoload_sct2_size.rs
+++ b/esp32p4/src/cache/l2_cache_autoload_sct2_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT2_SIZE")
             .field(
                 "l2_cache_autoload_sct2_size",
-                &format_args!("{}", self.l2_cache_autoload_sct2_size().bits()),
+                &self.l2_cache_autoload_sct2_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT2_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Those bits are used to configure the size of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_autoload_sct3_addr.rs b/esp32p4/src/cache/l2_cache_autoload_sct3_addr.rs
index a117e03923..f861014af3 100644
--- a/esp32p4/src/cache/l2_cache_autoload_sct3_addr.rs
+++ b/esp32p4/src/cache/l2_cache_autoload_sct3_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT3_ADDR")
             .field(
                 "l2_cache_autoload_sct3_addr",
-                &format_args!("{}", self.l2_cache_autoload_sct3_addr().bits()),
+                &self.l2_cache_autoload_sct3_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_autoload_sct3_size.rs b/esp32p4/src/cache/l2_cache_autoload_sct3_size.rs
index f42c8857ff..84098abcd0 100644
--- a/esp32p4/src/cache/l2_cache_autoload_sct3_size.rs
+++ b/esp32p4/src/cache/l2_cache_autoload_sct3_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_AUTOLOAD_SCT3_SIZE")
             .field(
                 "l2_cache_autoload_sct3_size",
-                &format_args!("{}", self.l2_cache_autoload_sct3_size().bits()),
+                &self.l2_cache_autoload_sct3_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_AUTOLOAD_SCT3_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Those bits are used to configure the size of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_blocksize_conf.rs b/esp32p4/src/cache/l2_cache_blocksize_conf.rs
index baf0ff68eb..365e28cdbd 100644
--- a/esp32p4/src/cache/l2_cache_blocksize_conf.rs
+++ b/esp32p4/src/cache/l2_cache_blocksize_conf.rs
@@ -54,39 +54,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_BLOCKSIZE_CONF")
-            .field(
-                "l2_cache_blocksize_8",
-                &format_args!("{}", self.l2_cache_blocksize_8().bit()),
-            )
-            .field(
-                "l2_cache_blocksize_16",
-                &format_args!("{}", self.l2_cache_blocksize_16().bit()),
-            )
-            .field(
-                "l2_cache_blocksize_32",
-                &format_args!("{}", self.l2_cache_blocksize_32().bit()),
-            )
-            .field(
-                "l2_cache_blocksize_64",
-                &format_args!("{}", self.l2_cache_blocksize_64().bit()),
-            )
-            .field(
-                "l2_cache_blocksize_128",
-                &format_args!("{}", self.l2_cache_blocksize_128().bit()),
-            )
-            .field(
-                "l2_cache_blocksize_256",
-                &format_args!("{}", self.l2_cache_blocksize_256().bit()),
-            )
+            .field("l2_cache_blocksize_8", &self.l2_cache_blocksize_8())
+            .field("l2_cache_blocksize_16", &self.l2_cache_blocksize_16())
+            .field("l2_cache_blocksize_32", &self.l2_cache_blocksize_32())
+            .field("l2_cache_blocksize_64", &self.l2_cache_blocksize_64())
+            .field("l2_cache_blocksize_128", &self.l2_cache_blocksize_128())
+            .field("l2_cache_blocksize_256", &self.l2_cache_blocksize_256())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_BLOCKSIZE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all other fields within this register is onehot."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_cachesize_conf.rs b/esp32p4/src/cache/l2_cache_cachesize_conf.rs
index 877225b6b1..e2ef524e09 100644
--- a/esp32p4/src/cache/l2_cache_cachesize_conf.rs
+++ b/esp32p4/src/cache/l2_cache_cachesize_conf.rs
@@ -105,67 +105,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_CACHESIZE_CONF")
-            .field(
-                "l2_cache_cachesize_256",
-                &format_args!("{}", self.l2_cache_cachesize_256().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_512",
-                &format_args!("{}", self.l2_cache_cachesize_512().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_1k",
-                &format_args!("{}", self.l2_cache_cachesize_1k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_2k",
-                &format_args!("{}", self.l2_cache_cachesize_2k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_4k",
-                &format_args!("{}", self.l2_cache_cachesize_4k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_8k",
-                &format_args!("{}", self.l2_cache_cachesize_8k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_16k",
-                &format_args!("{}", self.l2_cache_cachesize_16k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_32k",
-                &format_args!("{}", self.l2_cache_cachesize_32k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_64k",
-                &format_args!("{}", self.l2_cache_cachesize_64k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_128k",
-                &format_args!("{}", self.l2_cache_cachesize_128k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_256k",
-                &format_args!("{}", self.l2_cache_cachesize_256k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_512k",
-                &format_args!("{}", self.l2_cache_cachesize_512k().bit()),
-            )
-            .field(
-                "l2_cache_cachesize_1024k",
-                &format_args!("{}", self.l2_cache_cachesize_1024k().bit()),
-            )
+            .field("l2_cache_cachesize_256", &self.l2_cache_cachesize_256())
+            .field("l2_cache_cachesize_512", &self.l2_cache_cachesize_512())
+            .field("l2_cache_cachesize_1k", &self.l2_cache_cachesize_1k())
+            .field("l2_cache_cachesize_2k", &self.l2_cache_cachesize_2k())
+            .field("l2_cache_cachesize_4k", &self.l2_cache_cachesize_4k())
+            .field("l2_cache_cachesize_8k", &self.l2_cache_cachesize_8k())
+            .field("l2_cache_cachesize_16k", &self.l2_cache_cachesize_16k())
+            .field("l2_cache_cachesize_32k", &self.l2_cache_cachesize_32k())
+            .field("l2_cache_cachesize_64k", &self.l2_cache_cachesize_64k())
+            .field("l2_cache_cachesize_128k", &self.l2_cache_cachesize_128k())
+            .field("l2_cache_cachesize_256k", &self.l2_cache_cachesize_256k())
+            .field("l2_cache_cachesize_512k", &self.l2_cache_cachesize_512k())
+            .field("l2_cache_cachesize_1024k", &self.l2_cache_cachesize_1024k())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_CACHESIZE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - The field is used to configure cachesize of L2-Cache as 128k bytes. This field and all other fields within this register is onehot."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_ctrl.rs b/esp32p4/src/cache/l2_cache_ctrl.rs
index 734dd4b5f7..204608f4c7 100644
--- a/esp32p4/src/cache/l2_cache_ctrl.rs
+++ b/esp32p4/src/cache/l2_cache_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_CTRL")
-            .field(
-                "l2_cache_shut_dma",
-                &format_args!("{}", self.l2_cache_shut_dma().bit()),
-            )
-            .field(
-                "l2_cache_undef_op",
-                &format_args!("{}", self.l2_cache_undef_op().bits()),
-            )
+            .field("l2_cache_shut_dma", &self.l2_cache_shut_dma())
+            .field("l2_cache_undef_op", &self.l2_cache_undef_op())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_data_mem_acs_conf.rs b/esp32p4/src/cache/l2_cache_data_mem_acs_conf.rs
index 18eb243ab0..22f96b6c02 100644
--- a/esp32p4/src/cache/l2_cache_data_mem_acs_conf.rs
+++ b/esp32p4/src/cache/l2_cache_data_mem_acs_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_DATA_MEM_ACS_CONF")
-            .field(
-                "l2_cache_data_mem_rd_en",
-                &format_args!("{}", self.l2_cache_data_mem_rd_en().bit()),
-            )
-            .field(
-                "l2_cache_data_mem_wr_en",
-                &format_args!("{}", self.l2_cache_data_mem_wr_en().bit()),
-            )
+            .field("l2_cache_data_mem_rd_en", &self.l2_cache_data_mem_rd_en())
+            .field("l2_cache_data_mem_wr_en", &self.l2_cache_data_mem_wr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_DATA_MEM_ACS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: enable."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_data_mem_power_ctrl.rs b/esp32p4/src/cache/l2_cache_data_mem_power_ctrl.rs
index 38dbbf4333..f58b7d370c 100644
--- a/esp32p4/src/cache/l2_cache_data_mem_power_ctrl.rs
+++ b/esp32p4/src/cache/l2_cache_data_mem_power_ctrl.rs
@@ -37,25 +37,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_DATA_MEM_POWER_CTRL")
             .field(
                 "l2_cache_data_mem_force_on",
-                &format_args!("{}", self.l2_cache_data_mem_force_on().bit()),
+                &self.l2_cache_data_mem_force_on(),
             )
             .field(
                 "l2_cache_data_mem_force_pd",
-                &format_args!("{}", self.l2_cache_data_mem_force_pd().bit()),
+                &self.l2_cache_data_mem_force_pd(),
             )
             .field(
                 "l2_cache_data_mem_force_pu",
-                &format_args!("{}", self.l2_cache_data_mem_force_pu().bit()),
+                &self.l2_cache_data_mem_force_pu(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_DATA_MEM_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_debug_bus.rs b/esp32p4/src/cache/l2_cache_debug_bus.rs
index b8fda3f33e..e104532041 100644
--- a/esp32p4/src/cache/l2_cache_debug_bus.rs
+++ b/esp32p4/src/cache/l2_cache_debug_bus.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_DEBUG_BUS")
-            .field(
-                "l2_cache_debug_bus",
-                &format_args!("{}", self.l2_cache_debug_bus().bits()),
-            )
+            .field("l2_cache_debug_bus", &self.l2_cache_debug_bus())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_DEBUG_BUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This is a constant place where we can write data to or read data from the tag/data memory on the specified cache."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_freeze_ctrl.rs b/esp32p4/src/cache/l2_cache_freeze_ctrl.rs
index 8acfe4eb6f..73ee8dbcc8 100644
--- a/esp32p4/src/cache/l2_cache_freeze_ctrl.rs
+++ b/esp32p4/src/cache/l2_cache_freeze_ctrl.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_FREEZE_CTRL")
-            .field(
-                "l2_cache_freeze_en",
-                &format_args!("{}", self.l2_cache_freeze_en().bit()),
-            )
-            .field(
-                "l2_cache_freeze_mode",
-                &format_args!("{}", self.l2_cache_freeze_mode().bit()),
-            )
-            .field(
-                "l2_cache_freeze_done",
-                &format_args!("{}", self.l2_cache_freeze_done().bit()),
-            )
+            .field("l2_cache_freeze_en", &self.l2_cache_freeze_en())
+            .field("l2_cache_freeze_mode", &self.l2_cache_freeze_mode())
+            .field("l2_cache_freeze_done", &self.l2_cache_freeze_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_FREEZE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - The bit is used to enable freeze operation on L2-Cache. It can be cleared by software."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_object_ctrl.rs b/esp32p4/src/cache/l2_cache_object_ctrl.rs
index 594255ee52..1a68ed4576 100644
--- a/esp32p4/src/cache/l2_cache_object_ctrl.rs
+++ b/esp32p4/src/cache/l2_cache_object_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_OBJECT_CTRL")
-            .field(
-                "l2_cache_tag_object",
-                &format_args!("{}", self.l2_cache_tag_object().bit()),
-            )
-            .field(
-                "l2_cache_mem_object",
-                &format_args!("{}", self.l2_cache_mem_object().bit()),
-            )
+            .field("l2_cache_tag_object", &self.l2_cache_tag_object())
+            .field("l2_cache_mem_object", &self.l2_cache_mem_object())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_OBJECT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 5 - Set this bit to set L2-Cache tag memory as object. This bit should be onehot with the others fields inside this register."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_preload_addr.rs b/esp32p4/src/cache/l2_cache_preload_addr.rs
index dcd315e1b3..1c5110d627 100644
--- a/esp32p4/src/cache/l2_cache_preload_addr.rs
+++ b/esp32p4/src/cache/l2_cache_preload_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_PRELOAD_ADDR")
-            .field(
-                "l2_cache_preload_addr",
-                &format_args!("{}", self.l2_cache_preload_addr().bits()),
-            )
+            .field("l2_cache_preload_addr", &self.l2_cache_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L2-Cache, which should be used together with L2_CACHE_PRELOAD_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_preload_ctrl.rs b/esp32p4/src/cache/l2_cache_preload_ctrl.rs
index a7610c5692..cca169a53a 100644
--- a/esp32p4/src/cache/l2_cache_preload_ctrl.rs
+++ b/esp32p4/src/cache/l2_cache_preload_ctrl.rs
@@ -42,31 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_PRELOAD_CTRL")
-            .field(
-                "l2_cache_preload_ena",
-                &format_args!("{}", self.l2_cache_preload_ena().bit()),
-            )
-            .field(
-                "l2_cache_preload_done",
-                &format_args!("{}", self.l2_cache_preload_done().bit()),
-            )
-            .field(
-                "l2_cache_preload_order",
-                &format_args!("{}", self.l2_cache_preload_order().bit()),
-            )
-            .field(
-                "l2_cache_preload_rgid",
-                &format_args!("{}", self.l2_cache_preload_rgid().bits()),
-            )
+            .field("l2_cache_preload_ena", &self.l2_cache_preload_ena())
+            .field("l2_cache_preload_done", &self.l2_cache_preload_done())
+            .field("l2_cache_preload_order", &self.l2_cache_preload_order())
+            .field("l2_cache_preload_rgid", &self.l2_cache_preload_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_preload_rst_ctrl.rs b/esp32p4/src/cache/l2_cache_preload_rst_ctrl.rs
index eff44700bb..9a599d1c81 100644
--- a/esp32p4/src/cache/l2_cache_preload_rst_ctrl.rs
+++ b/esp32p4/src/cache/l2_cache_preload_rst_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_PRELOAD_RST_CTRL")
-            .field(
-                "l2_cache_pld_rst",
-                &format_args!("{}", self.l2_cache_pld_rst().bit()),
-            )
+            .field("l2_cache_pld_rst", &self.l2_cache_pld_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOAD_RST_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 5 - set this bit to reset preload-logic inside L2-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_preload_size.rs b/esp32p4/src/cache/l2_cache_preload_size.rs
index 40f1be0462..d3e7846a0d 100644
--- a/esp32p4/src/cache/l2_cache_preload_size.rs
+++ b/esp32p4/src/cache/l2_cache_preload_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_PRELOAD_SIZE")
-            .field(
-                "l2_cache_preload_size",
-                &format_args!("{}", self.l2_cache_preload_size().bits()),
-            )
+            .field("l2_cache_preload_size", &self.l2_cache_preload_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_prelock_conf.rs b/esp32p4/src/cache/l2_cache_prelock_conf.rs
index 2d0f4aa956..641e5134c8 100644
--- a/esp32p4/src/cache/l2_cache_prelock_conf.rs
+++ b/esp32p4/src/cache/l2_cache_prelock_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_PRELOCK_CONF")
-            .field(
-                "l2_cache_prelock_sct0_en",
-                &format_args!("{}", self.l2_cache_prelock_sct0_en().bit()),
-            )
-            .field(
-                "l2_cache_prelock_sct1_en",
-                &format_args!("{}", self.l2_cache_prelock_sct1_en().bit()),
-            )
-            .field(
-                "l2_cache_prelock_rgid",
-                &format_args!("{}", self.l2_cache_prelock_rgid().bits()),
-            )
+            .field("l2_cache_prelock_sct0_en", &self.l2_cache_prelock_sct0_en())
+            .field("l2_cache_prelock_sct1_en", &self.l2_cache_prelock_sct1_en())
+            .field("l2_cache_prelock_rgid", &self.l2_cache_prelock_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOCK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable the first section of prelock function on L2-Cache."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_prelock_sct0_addr.rs b/esp32p4/src/cache/l2_cache_prelock_sct0_addr.rs
index 543cb96b34..ddef16d758 100644
--- a/esp32p4/src/cache/l2_cache_prelock_sct0_addr.rs
+++ b/esp32p4/src/cache/l2_cache_prelock_sct0_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_PRELOCK_SCT0_ADDR")
             .field(
                 "l2_cache_prelock_sct0_addr",
-                &format_args!("{}", self.l2_cache_prelock_sct0_addr().bits()),
+                &self.l2_cache_prelock_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOCK_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_prelock_sct1_addr.rs b/esp32p4/src/cache/l2_cache_prelock_sct1_addr.rs
index 45fc08303e..9e62c37d1d 100644
--- a/esp32p4/src/cache/l2_cache_prelock_sct1_addr.rs
+++ b/esp32p4/src/cache/l2_cache_prelock_sct1_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_PRELOCK_SCT1_ADDR")
             .field(
                 "l2_cache_prelock_sct1_addr",
-                &format_args!("{}", self.l2_cache_prelock_sct1_addr().bits()),
+                &self.l2_cache_prelock_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOCK_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_prelock_sct_size.rs b/esp32p4/src/cache/l2_cache_prelock_sct_size.rs
index d48e1efa69..bb82a9adb4 100644
--- a/esp32p4/src/cache/l2_cache_prelock_sct_size.rs
+++ b/esp32p4/src/cache/l2_cache_prelock_sct_size.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_PRELOCK_SCT_SIZE")
             .field(
                 "l2_cache_prelock_sct0_size",
-                &format_args!("{}", self.l2_cache_prelock_sct0_size().bits()),
+                &self.l2_cache_prelock_sct0_size(),
             )
             .field(
                 "l2_cache_prelock_sct1_size",
-                &format_args!("{}", self.l2_cache_prelock_sct1_size().bits()),
+                &self.l2_cache_prelock_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PRELOCK_SCT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_sync_preload_exception.rs b/esp32p4/src/cache/l2_cache_sync_preload_exception.rs
index 4abbabb042..40b97f77cf 100644
--- a/esp32p4/src/cache/l2_cache_sync_preload_exception.rs
+++ b/esp32p4/src/cache/l2_cache_sync_preload_exception.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_SYNC_PRELOAD_EXCEPTION")
-            .field(
-                "l2_cache_pld_err_code",
-                &format_args!("{}", self.l2_cache_pld_err_code().bits()),
-            )
+            .field("l2_cache_pld_err_code", &self.l2_cache_pld_err_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Sync/Preload Operation exception register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_exception::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC;
 impl crate::RegisterSpec for L2_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC {
diff --git a/esp32p4/src/cache/l2_cache_sync_preload_int_ena.rs b/esp32p4/src/cache/l2_cache_sync_preload_int_ena.rs
index 9b9fb48596..3385c9e192 100644
--- a/esp32p4/src/cache/l2_cache_sync_preload_int_ena.rs
+++ b/esp32p4/src/cache/l2_cache_sync_preload_int_ena.rs
@@ -28,21 +28,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_SYNC_PRELOAD_INT_ENA")
             .field(
                 "l2_cache_pld_done_int_ena",
-                &format_args!("{}", self.l2_cache_pld_done_int_ena().bit()),
-            )
-            .field(
-                "l2_cache_pld_err_int_ena",
-                &format_args!("{}", self.l2_cache_pld_err_int_ena().bit()),
+                &self.l2_cache_pld_done_int_ena(),
             )
+            .field("l2_cache_pld_err_int_ena", &self.l2_cache_pld_err_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_SYNC_PRELOAD_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 5 - The bit is used to enable interrupt of L2-Cache preload-operation done."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_sync_preload_int_raw.rs b/esp32p4/src/cache/l2_cache_sync_preload_int_raw.rs
index 0d948e61d0..b1da7ca8e4 100644
--- a/esp32p4/src/cache/l2_cache_sync_preload_int_raw.rs
+++ b/esp32p4/src/cache/l2_cache_sync_preload_int_raw.rs
@@ -28,21 +28,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_SYNC_PRELOAD_INT_RAW")
             .field(
                 "l2_cache_pld_done_int_raw",
-                &format_args!("{}", self.l2_cache_pld_done_int_raw().bit()),
-            )
-            .field(
-                "l2_cache_pld_err_int_raw",
-                &format_args!("{}", self.l2_cache_pld_err_int_raw().bit()),
+                &self.l2_cache_pld_done_int_raw(),
             )
+            .field("l2_cache_pld_err_int_raw", &self.l2_cache_pld_err_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 5 - The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_sync_preload_int_st.rs b/esp32p4/src/cache/l2_cache_sync_preload_int_st.rs
index 801dac1634..4a7ab59b93 100644
--- a/esp32p4/src/cache/l2_cache_sync_preload_int_st.rs
+++ b/esp32p4/src/cache/l2_cache_sync_preload_int_st.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_SYNC_PRELOAD_INT_ST")
-            .field(
-                "l2_cache_pld_done_int_st",
-                &format_args!("{}", self.l2_cache_pld_done_int_st().bit()),
-            )
-            .field(
-                "l2_cache_pld_err_int_st",
-                &format_args!("{}", self.l2_cache_pld_err_int_st().bit()),
-            )
+            .field("l2_cache_pld_done_int_st", &self.l2_cache_pld_done_int_st())
+            .field("l2_cache_pld_err_int_st", &self.l2_cache_pld_err_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_cache_sync_preload_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC;
 impl crate::RegisterSpec for L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC {
diff --git a/esp32p4/src/cache/l2_cache_sync_rst_ctrl.rs b/esp32p4/src/cache/l2_cache_sync_rst_ctrl.rs
index c2c53cf08b..d607aab110 100644
--- a/esp32p4/src/cache/l2_cache_sync_rst_ctrl.rs
+++ b/esp32p4/src/cache/l2_cache_sync_rst_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_SYNC_RST_CTRL")
-            .field(
-                "l2_cache_sync_rst",
-                &format_args!("{}", self.l2_cache_sync_rst().bit()),
-            )
+            .field("l2_cache_sync_rst", &self.l2_cache_sync_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_SYNC_RST_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 5 - set this bit to reset sync-logic inside L2-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_tag_mem_acs_conf.rs b/esp32p4/src/cache/l2_cache_tag_mem_acs_conf.rs
index 3839caaba9..f6852ab72b 100644
--- a/esp32p4/src/cache/l2_cache_tag_mem_acs_conf.rs
+++ b/esp32p4/src/cache/l2_cache_tag_mem_acs_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_TAG_MEM_ACS_CONF")
-            .field(
-                "l2_cache_tag_mem_rd_en",
-                &format_args!("{}", self.l2_cache_tag_mem_rd_en().bit()),
-            )
-            .field(
-                "l2_cache_tag_mem_wr_en",
-                &format_args!("{}", self.l2_cache_tag_mem_wr_en().bit()),
-            )
+            .field("l2_cache_tag_mem_rd_en", &self.l2_cache_tag_mem_rd_en())
+            .field("l2_cache_tag_mem_wr_en", &self.l2_cache_tag_mem_wr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_TAG_MEM_ACS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: enable."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_tag_mem_power_ctrl.rs b/esp32p4/src/cache/l2_cache_tag_mem_power_ctrl.rs
index 06d77e2d8b..a5546034a0 100644
--- a/esp32p4/src/cache/l2_cache_tag_mem_power_ctrl.rs
+++ b/esp32p4/src/cache/l2_cache_tag_mem_power_ctrl.rs
@@ -37,25 +37,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_CACHE_TAG_MEM_POWER_CTRL")
             .field(
                 "l2_cache_tag_mem_force_on",
-                &format_args!("{}", self.l2_cache_tag_mem_force_on().bit()),
+                &self.l2_cache_tag_mem_force_on(),
             )
             .field(
                 "l2_cache_tag_mem_force_pd",
-                &format_args!("{}", self.l2_cache_tag_mem_force_pd().bit()),
+                &self.l2_cache_tag_mem_force_pd(),
             )
             .field(
                 "l2_cache_tag_mem_force_pu",
-                &format_args!("{}", self.l2_cache_tag_mem_force_pu().bit()),
+                &self.l2_cache_tag_mem_force_pu(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_TAG_MEM_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_vaddr.rs b/esp32p4/src/cache/l2_cache_vaddr.rs
index 206524b4fe..1c892f4245 100644
--- a/esp32p4/src/cache/l2_cache_vaddr.rs
+++ b/esp32p4/src/cache/l2_cache_vaddr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_VADDR")
-            .field(
-                "l2_cache_vaddr",
-                &format_args!("{}", self.l2_cache_vaddr().bits()),
-            )
+            .field("l2_cache_vaddr", &self.l2_cache_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_way_object.rs b/esp32p4/src/cache/l2_cache_way_object.rs
index ef9b86c7ba..342bfc6793 100644
--- a/esp32p4/src/cache/l2_cache_way_object.rs
+++ b/esp32p4/src/cache/l2_cache_way_object.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_WAY_OBJECT")
-            .field(
-                "l2_cache_way_object",
-                &format_args!("{}", self.l2_cache_way_object().bits()),
-            )
+            .field("l2_cache_way_object", &self.l2_cache_way_object())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_WAY_OBJECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_cache_wrap_around_ctrl.rs b/esp32p4/src/cache/l2_cache_wrap_around_ctrl.rs
index 2173810ac9..2fed19de81 100644
--- a/esp32p4/src/cache/l2_cache_wrap_around_ctrl.rs
+++ b/esp32p4/src/cache/l2_cache_wrap_around_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_WRAP_AROUND_CTRL")
-            .field(
-                "l2_cache_wrap",
-                &format_args!("{}", self.l2_cache_wrap().bit()),
-            )
+            .field("l2_cache_wrap", &self.l2_cache_wrap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_WRAP_AROUND_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 5 - Set this bit as 1 to enable L2-Cache wrap around mode."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/l2_dbus0_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_dbus0_acs_conflict_cnt.rs
index 6be5e27566..6c33425fb8 100644
--- a/esp32p4/src/cache/l2_dbus0_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus0_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS0_ACS_CONFLICT_CNT")
-            .field(
-                "l2_dbus0_conflict_cnt",
-                &format_args!("{}", self.l2_dbus0_conflict_cnt().bits()),
-            )
+            .field("l2_dbus0_conflict_cnt", &self.l2_dbus0_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS0_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS0_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS0_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus0_acs_hit_cnt.rs b/esp32p4/src/cache/l2_dbus0_acs_hit_cnt.rs
index e9b8f9e1b7..60046d72b8 100644
--- a/esp32p4/src/cache/l2_dbus0_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus0_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS0_ACS_HIT_CNT")
-            .field(
-                "l2_dbus0_hit_cnt",
-                &format_args!("{}", self.l2_dbus0_hit_cnt().bits()),
-            )
+            .field("l2_dbus0_hit_cnt", &self.l2_dbus0_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS0_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS0_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS0_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus0_acs_miss_cnt.rs b/esp32p4/src/cache/l2_dbus0_acs_miss_cnt.rs
index 3cef0dcd5d..1676075b8d 100644
--- a/esp32p4/src/cache/l2_dbus0_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus0_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS0_ACS_MISS_CNT")
-            .field(
-                "l2_dbus0_miss_cnt",
-                &format_args!("{}", self.l2_dbus0_miss_cnt().bits()),
-            )
+            .field("l2_dbus0_miss_cnt", &self.l2_dbus0_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS0_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS0_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS0_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus0_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_dbus0_acs_nxtlvl_rd_cnt.rs
index 2ac16d21cb..4a7bf6691a 100644
--- a/esp32p4/src/cache/l2_dbus0_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus0_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS0_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l2_dbus0_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l2_dbus0_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l2_dbus0_nxtlvl_rd_cnt", &self.l2_dbus0_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS0_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS0_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS0_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus0_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l2_dbus0_acs_nxtlvl_wr_cnt.rs
index a0410aa184..81bc526772 100644
--- a/esp32p4/src/cache/l2_dbus0_acs_nxtlvl_wr_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus0_acs_nxtlvl_wr_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS0_ACS_NXTLVL_WR_CNT")
-            .field(
-                "l2_dbus0_nxtlvl_wr_cnt",
-                &format_args!("{}", self.l2_dbus0_nxtlvl_wr_cnt().bits()),
-            )
+            .field("l2_dbus0_nxtlvl_wr_cnt", &self.l2_dbus0_nxtlvl_wr_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS0_ACS_NXTLVL_WR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus0_acs_nxtlvl_wr_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS0_ACS_NXTLVL_WR_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS0_ACS_NXTLVL_WR_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus1_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_dbus1_acs_conflict_cnt.rs
index 2b32e65fde..601918e7eb 100644
--- a/esp32p4/src/cache/l2_dbus1_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus1_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS1_ACS_CONFLICT_CNT")
-            .field(
-                "l2_dbus1_conflict_cnt",
-                &format_args!("{}", self.l2_dbus1_conflict_cnt().bits()),
-            )
+            .field("l2_dbus1_conflict_cnt", &self.l2_dbus1_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS1_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS1_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS1_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus1_acs_hit_cnt.rs b/esp32p4/src/cache/l2_dbus1_acs_hit_cnt.rs
index 5eca591b68..2664395383 100644
--- a/esp32p4/src/cache/l2_dbus1_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus1_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS1_ACS_HIT_CNT")
-            .field(
-                "l2_dbus1_hit_cnt",
-                &format_args!("{}", self.l2_dbus1_hit_cnt().bits()),
-            )
+            .field("l2_dbus1_hit_cnt", &self.l2_dbus1_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS1_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS1_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS1_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus1_acs_miss_cnt.rs b/esp32p4/src/cache/l2_dbus1_acs_miss_cnt.rs
index 7c8cc4c16c..c111276a6b 100644
--- a/esp32p4/src/cache/l2_dbus1_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus1_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS1_ACS_MISS_CNT")
-            .field(
-                "l2_dbus1_miss_cnt",
-                &format_args!("{}", self.l2_dbus1_miss_cnt().bits()),
-            )
+            .field("l2_dbus1_miss_cnt", &self.l2_dbus1_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS1_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS1_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS1_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus1_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_dbus1_acs_nxtlvl_rd_cnt.rs
index 1e82bb0f1e..d465eae69e 100644
--- a/esp32p4/src/cache/l2_dbus1_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus1_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS1_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l2_dbus1_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l2_dbus1_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l2_dbus1_nxtlvl_rd_cnt", &self.l2_dbus1_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS1_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS1_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS1_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus1_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l2_dbus1_acs_nxtlvl_wr_cnt.rs
index 6f18d0c8f0..a0a6bfe609 100644
--- a/esp32p4/src/cache/l2_dbus1_acs_nxtlvl_wr_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus1_acs_nxtlvl_wr_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS1_ACS_NXTLVL_WR_CNT")
-            .field(
-                "l2_dbus1_nxtlvl_wr_cnt",
-                &format_args!("{}", self.l2_dbus1_nxtlvl_wr_cnt().bits()),
-            )
+            .field("l2_dbus1_nxtlvl_wr_cnt", &self.l2_dbus1_nxtlvl_wr_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS1_ACS_NXTLVL_WR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus1_acs_nxtlvl_wr_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS1_ACS_NXTLVL_WR_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS1_ACS_NXTLVL_WR_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus2_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_dbus2_acs_conflict_cnt.rs
index 923d7bf3cc..53361570e3 100644
--- a/esp32p4/src/cache/l2_dbus2_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus2_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS2_ACS_CONFLICT_CNT")
-            .field(
-                "l2_dbus2_conflict_cnt",
-                &format_args!("{}", self.l2_dbus2_conflict_cnt().bits()),
-            )
+            .field("l2_dbus2_conflict_cnt", &self.l2_dbus2_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS2_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS2_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS2_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus2_acs_hit_cnt.rs b/esp32p4/src/cache/l2_dbus2_acs_hit_cnt.rs
index 691174e674..12ce12f831 100644
--- a/esp32p4/src/cache/l2_dbus2_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus2_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS2_ACS_HIT_CNT")
-            .field(
-                "l2_dbus2_hit_cnt",
-                &format_args!("{}", self.l2_dbus2_hit_cnt().bits()),
-            )
+            .field("l2_dbus2_hit_cnt", &self.l2_dbus2_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS2_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS2_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS2_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus2_acs_miss_cnt.rs b/esp32p4/src/cache/l2_dbus2_acs_miss_cnt.rs
index 0797d64170..ba7498b6b5 100644
--- a/esp32p4/src/cache/l2_dbus2_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus2_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS2_ACS_MISS_CNT")
-            .field(
-                "l2_dbus2_miss_cnt",
-                &format_args!("{}", self.l2_dbus2_miss_cnt().bits()),
-            )
+            .field("l2_dbus2_miss_cnt", &self.l2_dbus2_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS2_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS2_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS2_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus2_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_dbus2_acs_nxtlvl_rd_cnt.rs
index 6c0e7dc2e2..fe81d51dc1 100644
--- a/esp32p4/src/cache/l2_dbus2_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus2_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS2_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l2_dbus2_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l2_dbus2_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l2_dbus2_nxtlvl_rd_cnt", &self.l2_dbus2_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS2_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS2_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS2_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus2_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l2_dbus2_acs_nxtlvl_wr_cnt.rs
index a0f47dd22a..d664d0fb96 100644
--- a/esp32p4/src/cache/l2_dbus2_acs_nxtlvl_wr_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus2_acs_nxtlvl_wr_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS2_ACS_NXTLVL_WR_CNT")
-            .field(
-                "l2_dbus2_nxtlvl_wr_cnt",
-                &format_args!("{}", self.l2_dbus2_nxtlvl_wr_cnt().bits()),
-            )
+            .field("l2_dbus2_nxtlvl_wr_cnt", &self.l2_dbus2_nxtlvl_wr_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS2_ACS_NXTLVL_WR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus2_acs_nxtlvl_wr_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS2_ACS_NXTLVL_WR_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS2_ACS_NXTLVL_WR_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus3_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_dbus3_acs_conflict_cnt.rs
index 87e82d3987..310ee48c8d 100644
--- a/esp32p4/src/cache/l2_dbus3_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus3_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS3_ACS_CONFLICT_CNT")
-            .field(
-                "l2_dbus3_conflict_cnt",
-                &format_args!("{}", self.l2_dbus3_conflict_cnt().bits()),
-            )
+            .field("l2_dbus3_conflict_cnt", &self.l2_dbus3_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS3_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS3_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS3_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus3_acs_hit_cnt.rs b/esp32p4/src/cache/l2_dbus3_acs_hit_cnt.rs
index f8964d3056..447aeaac2d 100644
--- a/esp32p4/src/cache/l2_dbus3_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus3_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS3_ACS_HIT_CNT")
-            .field(
-                "l2_dbus3_hit_cnt",
-                &format_args!("{}", self.l2_dbus3_hit_cnt().bits()),
-            )
+            .field("l2_dbus3_hit_cnt", &self.l2_dbus3_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS3_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS3_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS3_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus3_acs_miss_cnt.rs b/esp32p4/src/cache/l2_dbus3_acs_miss_cnt.rs
index 2fe6ed7e7f..5f13779466 100644
--- a/esp32p4/src/cache/l2_dbus3_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus3_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS3_ACS_MISS_CNT")
-            .field(
-                "l2_dbus3_miss_cnt",
-                &format_args!("{}", self.l2_dbus3_miss_cnt().bits()),
-            )
+            .field("l2_dbus3_miss_cnt", &self.l2_dbus3_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS3_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS3_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS3_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus3_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_dbus3_acs_nxtlvl_rd_cnt.rs
index d9a75af352..b38a81b566 100644
--- a/esp32p4/src/cache/l2_dbus3_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus3_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS3_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l2_dbus3_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l2_dbus3_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l2_dbus3_nxtlvl_rd_cnt", &self.l2_dbus3_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS3_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS3_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS3_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_dbus3_acs_nxtlvl_wr_cnt.rs b/esp32p4/src/cache/l2_dbus3_acs_nxtlvl_wr_cnt.rs
index 9393606090..0dfc5102ab 100644
--- a/esp32p4/src/cache/l2_dbus3_acs_nxtlvl_wr_cnt.rs
+++ b/esp32p4/src/cache/l2_dbus3_acs_nxtlvl_wr_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_DBUS3_ACS_NXTLVL_WR_CNT")
-            .field(
-                "l2_dbus3_nxtlvl_wr_cnt",
-                &format_args!("{}", self.l2_dbus3_nxtlvl_wr_cnt().bits()),
-            )
+            .field("l2_dbus3_nxtlvl_wr_cnt", &self.l2_dbus3_nxtlvl_wr_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_DBUS3_ACS_NXTLVL_WR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 WB-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_dbus3_acs_nxtlvl_wr_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_DBUS3_ACS_NXTLVL_WR_CNT_SPEC;
 impl crate::RegisterSpec for L2_DBUS3_ACS_NXTLVL_WR_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus0_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_ibus0_acs_conflict_cnt.rs
index d657830c66..3b26e7e69b 100644
--- a/esp32p4/src/cache/l2_ibus0_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus0_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS0_ACS_CONFLICT_CNT")
-            .field(
-                "l2_ibus0_conflict_cnt",
-                &format_args!("{}", self.l2_ibus0_conflict_cnt().bits()),
-            )
+            .field("l2_ibus0_conflict_cnt", &self.l2_ibus0_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS0_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS0_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS0_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus0_acs_hit_cnt.rs b/esp32p4/src/cache/l2_ibus0_acs_hit_cnt.rs
index b6f592f10e..6472776972 100644
--- a/esp32p4/src/cache/l2_ibus0_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus0_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS0_ACS_HIT_CNT")
-            .field(
-                "l2_ibus0_hit_cnt",
-                &format_args!("{}", self.l2_ibus0_hit_cnt().bits()),
-            )
+            .field("l2_ibus0_hit_cnt", &self.l2_ibus0_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS0_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS0_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS0_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus0_acs_miss_cnt.rs b/esp32p4/src/cache/l2_ibus0_acs_miss_cnt.rs
index 91dd2a4a08..5b8973fa80 100644
--- a/esp32p4/src/cache/l2_ibus0_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus0_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS0_ACS_MISS_CNT")
-            .field(
-                "l2_ibus0_miss_cnt",
-                &format_args!("{}", self.l2_ibus0_miss_cnt().bits()),
-            )
+            .field("l2_ibus0_miss_cnt", &self.l2_ibus0_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS0_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS0_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS0_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus0_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_ibus0_acs_nxtlvl_rd_cnt.rs
index d01af42b28..b8307c8fc3 100644
--- a/esp32p4/src/cache/l2_ibus0_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus0_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS0_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l2_ibus0_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l2_ibus0_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l2_ibus0_nxtlvl_rd_cnt", &self.l2_ibus0_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS0_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus0 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus0_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS0_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS0_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus1_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_ibus1_acs_conflict_cnt.rs
index b0ca9e9908..b737d25ede 100644
--- a/esp32p4/src/cache/l2_ibus1_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus1_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS1_ACS_CONFLICT_CNT")
-            .field(
-                "l2_ibus1_conflict_cnt",
-                &format_args!("{}", self.l2_ibus1_conflict_cnt().bits()),
-            )
+            .field("l2_ibus1_conflict_cnt", &self.l2_ibus1_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS1_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS1_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS1_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus1_acs_hit_cnt.rs b/esp32p4/src/cache/l2_ibus1_acs_hit_cnt.rs
index 1a82b35abf..9d32e633b6 100644
--- a/esp32p4/src/cache/l2_ibus1_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus1_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS1_ACS_HIT_CNT")
-            .field(
-                "l2_ibus1_hit_cnt",
-                &format_args!("{}", self.l2_ibus1_hit_cnt().bits()),
-            )
+            .field("l2_ibus1_hit_cnt", &self.l2_ibus1_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS1_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS1_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS1_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus1_acs_miss_cnt.rs b/esp32p4/src/cache/l2_ibus1_acs_miss_cnt.rs
index b13e7bbcf7..eb12226a19 100644
--- a/esp32p4/src/cache/l2_ibus1_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus1_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS1_ACS_MISS_CNT")
-            .field(
-                "l2_ibus1_miss_cnt",
-                &format_args!("{}", self.l2_ibus1_miss_cnt().bits()),
-            )
+            .field("l2_ibus1_miss_cnt", &self.l2_ibus1_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS1_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS1_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS1_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus1_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_ibus1_acs_nxtlvl_rd_cnt.rs
index cc1d22cef8..fb89f3646e 100644
--- a/esp32p4/src/cache/l2_ibus1_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus1_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS1_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l2_ibus1_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l2_ibus1_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l2_ibus1_nxtlvl_rd_cnt", &self.l2_ibus1_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS1_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus1 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus1_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS1_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS1_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus2_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_ibus2_acs_conflict_cnt.rs
index a46f4e552c..2bb98c9810 100644
--- a/esp32p4/src/cache/l2_ibus2_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus2_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS2_ACS_CONFLICT_CNT")
-            .field(
-                "l2_ibus2_conflict_cnt",
-                &format_args!("{}", self.l2_ibus2_conflict_cnt().bits()),
-            )
+            .field("l2_ibus2_conflict_cnt", &self.l2_ibus2_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS2_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS2_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS2_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus2_acs_hit_cnt.rs b/esp32p4/src/cache/l2_ibus2_acs_hit_cnt.rs
index 763540bd91..2f46154127 100644
--- a/esp32p4/src/cache/l2_ibus2_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus2_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS2_ACS_HIT_CNT")
-            .field(
-                "l2_ibus2_hit_cnt",
-                &format_args!("{}", self.l2_ibus2_hit_cnt().bits()),
-            )
+            .field("l2_ibus2_hit_cnt", &self.l2_ibus2_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS2_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS2_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS2_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus2_acs_miss_cnt.rs b/esp32p4/src/cache/l2_ibus2_acs_miss_cnt.rs
index 67ac956597..d86f0d7618 100644
--- a/esp32p4/src/cache/l2_ibus2_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus2_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS2_ACS_MISS_CNT")
-            .field(
-                "l2_ibus2_miss_cnt",
-                &format_args!("{}", self.l2_ibus2_miss_cnt().bits()),
-            )
+            .field("l2_ibus2_miss_cnt", &self.l2_ibus2_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS2_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS2_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS2_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus2_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_ibus2_acs_nxtlvl_rd_cnt.rs
index 1bce166d41..ed7d1ff584 100644
--- a/esp32p4/src/cache/l2_ibus2_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus2_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS2_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l2_ibus2_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l2_ibus2_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l2_ibus2_nxtlvl_rd_cnt", &self.l2_ibus2_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS2_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus2 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus2_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS2_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS2_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus3_acs_conflict_cnt.rs b/esp32p4/src/cache/l2_ibus3_acs_conflict_cnt.rs
index b06b6ee3ff..5e897b0327 100644
--- a/esp32p4/src/cache/l2_ibus3_acs_conflict_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus3_acs_conflict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS3_ACS_CONFLICT_CNT")
-            .field(
-                "l2_ibus3_conflict_cnt",
-                &format_args!("{}", self.l2_ibus3_conflict_cnt().bits()),
-            )
+            .field("l2_ibus3_conflict_cnt", &self.l2_ibus3_conflict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS3_ACS_CONFLICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Conflict-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_conflict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS3_ACS_CONFLICT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS3_ACS_CONFLICT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus3_acs_hit_cnt.rs b/esp32p4/src/cache/l2_ibus3_acs_hit_cnt.rs
index 2fa858b5ff..dc047bc4ec 100644
--- a/esp32p4/src/cache/l2_ibus3_acs_hit_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus3_acs_hit_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS3_ACS_HIT_CNT")
-            .field(
-                "l2_ibus3_hit_cnt",
-                &format_args!("{}", self.l2_ibus3_hit_cnt().bits()),
-            )
+            .field("l2_ibus3_hit_cnt", &self.l2_ibus3_hit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS3_ACS_HIT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Hit-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_hit_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS3_ACS_HIT_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS3_ACS_HIT_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus3_acs_miss_cnt.rs b/esp32p4/src/cache/l2_ibus3_acs_miss_cnt.rs
index 01bf5919d0..393546ef8a 100644
--- a/esp32p4/src/cache/l2_ibus3_acs_miss_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus3_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS3_ACS_MISS_CNT")
-            .field(
-                "l2_ibus3_miss_cnt",
-                &format_args!("{}", self.l2_ibus3_miss_cnt().bits()),
-            )
+            .field("l2_ibus3_miss_cnt", &self.l2_ibus3_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS3_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Miss-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS3_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS3_ACS_MISS_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_ibus3_acs_nxtlvl_rd_cnt.rs b/esp32p4/src/cache/l2_ibus3_acs_nxtlvl_rd_cnt.rs
index db569ed5c5..0476e87239 100644
--- a/esp32p4/src/cache/l2_ibus3_acs_nxtlvl_rd_cnt.rs
+++ b/esp32p4/src/cache/l2_ibus3_acs_nxtlvl_rd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_IBUS3_ACS_NXTLVL_RD_CNT")
-            .field(
-                "l2_ibus3_nxtlvl_rd_cnt",
-                &format_args!("{}", self.l2_ibus3_nxtlvl_rd_cnt().bits()),
-            )
+            .field("l2_ibus3_nxtlvl_rd_cnt", &self.l2_ibus3_nxtlvl_rd_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_IBUS3_ACS_NXTLVL_RD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L2-Cache bus3 Next-Level-Access Counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_ibus3_acs_nxtlvl_rd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_IBUS3_ACS_NXTLVL_RD_CNT_SPEC;
 impl crate::RegisterSpec for L2_IBUS3_ACS_NXTLVL_RD_CNT_SPEC {
diff --git a/esp32p4/src/cache/l2_unallocate_buffer_clear.rs b/esp32p4/src/cache/l2_unallocate_buffer_clear.rs
index 67c2661c0c..958cd7b4f6 100644
--- a/esp32p4/src/cache/l2_unallocate_buffer_clear.rs
+++ b/esp32p4/src/cache/l2_unallocate_buffer_clear.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_UNALLOCATE_BUFFER_CLEAR")
-            .field(
-                "l2_cache_unalloc_clr",
-                &format_args!("{}", self.l2_cache_unalloc_clr().bit()),
-            )
+            .field("l2_cache_unalloc_clr", &self.l2_cache_unalloc_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_UNALLOCATE_BUFFER_CLEAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 5 - The bit is used to clear the unallocate request buffer of l2 icache where the unallocate request is responsed but not completed."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/level_split0.rs b/esp32p4/src/cache/level_split0.rs
index 6082db315e..c5fba3d3eb 100644
--- a/esp32p4/src/cache/level_split0.rs
+++ b/esp32p4/src/cache/level_split0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEVEL_SPLIT0")
-            .field(
-                "level_split0",
-                &format_args!("{}", self.level_split0().bits()),
-            )
+            .field("level_split0", &self.level_split0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEVEL_SPLIT0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USED TO SPLIT L1 CACHE AND L2 CACHE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`level_split0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LEVEL_SPLIT0_SPEC;
 impl crate::RegisterSpec for LEVEL_SPLIT0_SPEC {
diff --git a/esp32p4/src/cache/level_split1.rs b/esp32p4/src/cache/level_split1.rs
index 7452698a8c..cb64d3d252 100644
--- a/esp32p4/src/cache/level_split1.rs
+++ b/esp32p4/src/cache/level_split1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEVEL_SPLIT1")
-            .field(
-                "level_split1",
-                &format_args!("{}", self.level_split1().bits()),
-            )
+            .field("level_split1", &self.level_split1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEVEL_SPLIT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USED TO SPLIT L1 CACHE AND L2 CACHE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`level_split1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LEVEL_SPLIT1_SPEC;
 impl crate::RegisterSpec for LEVEL_SPLIT1_SPEC {
diff --git a/esp32p4/src/cache/lock_addr.rs b/esp32p4/src/cache/lock_addr.rs
index 5a5ea2c502..bf3a121029 100644
--- a/esp32p4/src/cache/lock_addr.rs
+++ b/esp32p4/src/cache/lock_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOCK_ADDR")
-            .field("lock_addr", &format_args!("{}", self.lock_addr().bits()))
+            .field("lock_addr", &self.lock_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOCK_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/lock_ctrl.rs b/esp32p4/src/cache/lock_ctrl.rs
index 934b8e3e60..532e45e1cb 100644
--- a/esp32p4/src/cache/lock_ctrl.rs
+++ b/esp32p4/src/cache/lock_ctrl.rs
@@ -42,19 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOCK_CTRL")
-            .field("lock_ena", &format_args!("{}", self.lock_ena().bit()))
-            .field("unlock_ena", &format_args!("{}", self.unlock_ena().bit()))
-            .field("lock_done", &format_args!("{}", self.lock_done().bit()))
-            .field("lock_rgid", &format_args!("{}", self.lock_rgid().bits()))
+            .field("lock_ena", &self.lock_ena())
+            .field("unlock_ena", &self.unlock_ena())
+            .field("lock_done", &self.lock_done())
+            .field("lock_rgid", &self.lock_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOCK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive, that is, those bits can not be set to 1 at the same time. (2) lock operation can be applied on LL1-ICache, L1-DCache and L2-Cache."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/lock_map.rs b/esp32p4/src/cache/lock_map.rs
index 0c5ff07541..78c93e04ff 100644
--- a/esp32p4/src/cache/lock_map.rs
+++ b/esp32p4/src/cache/lock_map.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOCK_MAP")
-            .field("lock_map", &format_args!("{}", self.lock_map().bits()))
+            .field("lock_map", &self.lock_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOCK_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. \\[0\\]: L1-ICache0, \\[1\\]: L1-ICache1, \\[2\\]: L1-ICache2, \\[3\\]: L1-ICache3, \\[4\\]: L1-DCache, \\[5\\]: L2-Cache."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/lock_size.rs b/esp32p4/src/cache/lock_size.rs
index cc0c189bbf..82bc3c5fe4 100644
--- a/esp32p4/src/cache/lock_size.rs
+++ b/esp32p4/src/cache/lock_size.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOCK_SIZE")
-            .field("lock_size", &format_args!("{}", self.lock_size().bits()))
+            .field("lock_size", &self.lock_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOCK_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/redundancy_sig0.rs b/esp32p4/src/cache/redundancy_sig0.rs
index acbff11e6a..6c19842e39 100644
--- a/esp32p4/src/cache/redundancy_sig0.rs
+++ b/esp32p4/src/cache/redundancy_sig0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDUNDANCY_SIG0")
-            .field("redcy_sig0", &format_args!("{}", self.redcy_sig0().bits()))
+            .field("redcy_sig0", &self.redcy_sig0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDUNDANCY_SIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are prepared for ECO."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/redundancy_sig1.rs b/esp32p4/src/cache/redundancy_sig1.rs
index 6d3c9691cd..550868759c 100644
--- a/esp32p4/src/cache/redundancy_sig1.rs
+++ b/esp32p4/src/cache/redundancy_sig1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDUNDANCY_SIG1")
-            .field("redcy_sig1", &format_args!("{}", self.redcy_sig1().bits()))
+            .field("redcy_sig1", &self.redcy_sig1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDUNDANCY_SIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are prepared for ECO."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/redundancy_sig2.rs b/esp32p4/src/cache/redundancy_sig2.rs
index 11ba730fa2..8b3e5a3973 100644
--- a/esp32p4/src/cache/redundancy_sig2.rs
+++ b/esp32p4/src/cache/redundancy_sig2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDUNDANCY_SIG2")
-            .field("redcy_sig2", &format_args!("{}", self.redcy_sig2().bits()))
+            .field("redcy_sig2", &self.redcy_sig2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDUNDANCY_SIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are prepared for ECO."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/redundancy_sig3.rs b/esp32p4/src/cache/redundancy_sig3.rs
index 0d1a6434fc..d513d2e42e 100644
--- a/esp32p4/src/cache/redundancy_sig3.rs
+++ b/esp32p4/src/cache/redundancy_sig3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDUNDANCY_SIG3")
-            .field("redcy_sig3", &format_args!("{}", self.redcy_sig3().bits()))
+            .field("redcy_sig3", &self.redcy_sig3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDUNDANCY_SIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are prepared for ECO."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/redundancy_sig4.rs b/esp32p4/src/cache/redundancy_sig4.rs
index 765f8aee05..f3f5ef2c3b 100644
--- a/esp32p4/src/cache/redundancy_sig4.rs
+++ b/esp32p4/src/cache/redundancy_sig4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDUNDANCY_SIG4")
-            .field("redcy_sig4", &format_args!("{}", self.redcy_sig4().bits()))
+            .field("redcy_sig4", &self.redcy_sig4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDUNDANCY_SIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache redundancy signal 0 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`redundancy_sig4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REDUNDANCY_SIG4_SPEC;
 impl crate::RegisterSpec for REDUNDANCY_SIG4_SPEC {
diff --git a/esp32p4/src/cache/sync_addr.rs b/esp32p4/src/cache/sync_addr.rs
index fc4ba3d4e9..da17b66661 100644
--- a/esp32p4/src/cache/sync_addr.rs
+++ b/esp32p4/src/cache/sync_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYNC_ADDR")
-            .field("sync_addr", &format_args!("{}", self.sync_addr().bits()))
+            .field("sync_addr", &self.sync_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYNC_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/cache/sync_ctrl.rs b/esp32p4/src/cache/sync_ctrl.rs
index e58c9c9ade..c7f9f699a9 100644
--- a/esp32p4/src/cache/sync_ctrl.rs
+++ b/esp32p4/src/cache/sync_ctrl.rs
@@ -60,30 +60,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYNC_CTRL")
-            .field(
-                "invalidate_ena",
-                &format_args!("{}", self.invalidate_ena().bit()),
-            )
-            .field("clean_ena", &format_args!("{}", self.clean_ena().bit()))
-            .field(
-                "writeback_ena",
-                &format_args!("{}", self.writeback_ena().bit()),
-            )
-            .field(
-                "writeback_invalidate_ena",
-                &format_args!("{}", self.writeback_invalidate_ena().bit()),
-            )
-            .field("sync_done", &format_args!("{}", self.sync_done().bit()))
-            .field("sync_rgid", &format_args!("{}", self.sync_rgid().bits()))
+            .field("invalidate_ena", &self.invalidate_ena())
+            .field("clean_ena", &self.clean_ena())
+            .field("writeback_ena", &self.writeback_ena())
+            .field("writeback_invalidate_ena", &self.writeback_invalidate_ena())
+            .field("sync_done", &self.sync_done())
+            .field("sync_rgid", &self.sync_rgid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYNC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/sync_l1_cache_preload_exception.rs b/esp32p4/src/cache/sync_l1_cache_preload_exception.rs
index 2c360c973d..15e6eaf89d 100644
--- a/esp32p4/src/cache/sync_l1_cache_preload_exception.rs
+++ b/esp32p4/src/cache/sync_l1_cache_preload_exception.rs
@@ -48,39 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYNC_L1_CACHE_PRELOAD_EXCEPTION")
-            .field(
-                "l1_icache0_pld_err_code",
-                &format_args!("{}", self.l1_icache0_pld_err_code().bits()),
-            )
-            .field(
-                "l1_icache1_pld_err_code",
-                &format_args!("{}", self.l1_icache1_pld_err_code().bits()),
-            )
-            .field(
-                "l1_icache2_pld_err_code",
-                &format_args!("{}", self.l1_icache2_pld_err_code().bits()),
-            )
-            .field(
-                "l1_icache3_pld_err_code",
-                &format_args!("{}", self.l1_icache3_pld_err_code().bits()),
-            )
-            .field(
-                "l1_dcache_pld_err_code",
-                &format_args!("{}", self.l1_dcache_pld_err_code().bits()),
-            )
-            .field(
-                "sync_err_code",
-                &format_args!("{}", self.sync_err_code().bits()),
-            )
+            .field("l1_icache0_pld_err_code", &self.l1_icache0_pld_err_code())
+            .field("l1_icache1_pld_err_code", &self.l1_icache1_pld_err_code())
+            .field("l1_icache2_pld_err_code", &self.l1_icache2_pld_err_code())
+            .field("l1_icache3_pld_err_code", &self.l1_icache3_pld_err_code())
+            .field("l1_dcache_pld_err_code", &self.l1_dcache_pld_err_code())
+            .field("sync_err_code", &self.sync_err_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYNC_L1_CACHE_PRELOAD_EXCEPTION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Cache Sync/Preload Operation exception register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_exception::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SYNC_L1_CACHE_PRELOAD_EXCEPTION_SPEC;
 impl crate::RegisterSpec for SYNC_L1_CACHE_PRELOAD_EXCEPTION_SPEC {
diff --git a/esp32p4/src/cache/sync_l1_cache_preload_int_clr.rs b/esp32p4/src/cache/sync_l1_cache_preload_int_clr.rs
index d4ab9cbe1a..0729d0ab53 100644
--- a/esp32p4/src/cache/sync_l1_cache_preload_int_clr.rs
+++ b/esp32p4/src/cache/sync_l1_cache_preload_int_clr.rs
@@ -54,29 +54,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYNC_L1_CACHE_PRELOAD_INT_CLR")
             .field(
                 "l1_icache2_pld_done_int_clr",
-                &format_args!("{}", self.l1_icache2_pld_done_int_clr().bit()),
+                &self.l1_icache2_pld_done_int_clr(),
             )
             .field(
                 "l1_icache3_pld_done_int_clr",
-                &format_args!("{}", self.l1_icache3_pld_done_int_clr().bit()),
+                &self.l1_icache3_pld_done_int_clr(),
             )
             .field(
                 "l1_icache2_pld_err_int_clr",
-                &format_args!("{}", self.l1_icache2_pld_err_int_clr().bit()),
+                &self.l1_icache2_pld_err_int_clr(),
             )
             .field(
                 "l1_icache3_pld_err_int_clr",
-                &format_args!("{}", self.l1_icache3_pld_err_int_clr().bit()),
+                &self.l1_icache3_pld_err_int_clr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYNC_L1_CACHE_PRELOAD_INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to clear interrupt that occurs only when L1-ICache0 preload-operation is done."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/sync_l1_cache_preload_int_ena.rs b/esp32p4/src/cache/sync_l1_cache_preload_int_ena.rs
index 9990c82011..da77b4d970 100644
--- a/esp32p4/src/cache/sync_l1_cache_preload_int_ena.rs
+++ b/esp32p4/src/cache/sync_l1_cache_preload_int_ena.rs
@@ -110,61 +110,49 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYNC_L1_CACHE_PRELOAD_INT_ENA")
             .field(
                 "l1_icache0_pld_done_int_ena",
-                &format_args!("{}", self.l1_icache0_pld_done_int_ena().bit()),
+                &self.l1_icache0_pld_done_int_ena(),
             )
             .field(
                 "l1_icache1_pld_done_int_ena",
-                &format_args!("{}", self.l1_icache1_pld_done_int_ena().bit()),
+                &self.l1_icache1_pld_done_int_ena(),
             )
             .field(
                 "l1_icache2_pld_done_int_ena",
-                &format_args!("{}", self.l1_icache2_pld_done_int_ena().bit()),
+                &self.l1_icache2_pld_done_int_ena(),
             )
             .field(
                 "l1_icache3_pld_done_int_ena",
-                &format_args!("{}", self.l1_icache3_pld_done_int_ena().bit()),
+                &self.l1_icache3_pld_done_int_ena(),
             )
             .field(
                 "l1_dcache_pld_done_int_ena",
-                &format_args!("{}", self.l1_dcache_pld_done_int_ena().bit()),
-            )
-            .field(
-                "sync_done_int_ena",
-                &format_args!("{}", self.sync_done_int_ena().bit()),
+                &self.l1_dcache_pld_done_int_ena(),
             )
+            .field("sync_done_int_ena", &self.sync_done_int_ena())
             .field(
                 "l1_icache0_pld_err_int_ena",
-                &format_args!("{}", self.l1_icache0_pld_err_int_ena().bit()),
+                &self.l1_icache0_pld_err_int_ena(),
             )
             .field(
                 "l1_icache1_pld_err_int_ena",
-                &format_args!("{}", self.l1_icache1_pld_err_int_ena().bit()),
+                &self.l1_icache1_pld_err_int_ena(),
             )
             .field(
                 "l1_icache2_pld_err_int_ena",
-                &format_args!("{}", self.l1_icache2_pld_err_int_ena().bit()),
+                &self.l1_icache2_pld_err_int_ena(),
             )
             .field(
                 "l1_icache3_pld_err_int_ena",
-                &format_args!("{}", self.l1_icache3_pld_err_int_ena().bit()),
+                &self.l1_icache3_pld_err_int_ena(),
             )
             .field(
                 "l1_dcache_pld_err_int_ena",
-                &format_args!("{}", self.l1_dcache_pld_err_int_ena().bit()),
-            )
-            .field(
-                "sync_err_int_ena",
-                &format_args!("{}", self.sync_err_int_ena().bit()),
+                &self.l1_dcache_pld_err_int_ena(),
             )
+            .field("sync_err_int_ena", &self.sync_err_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYNC_L1_CACHE_PRELOAD_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload operation is done, interrupt occurs."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/sync_l1_cache_preload_int_raw.rs b/esp32p4/src/cache/sync_l1_cache_preload_int_raw.rs
index 2fcb9c5a81..c6a3d93e39 100644
--- a/esp32p4/src/cache/sync_l1_cache_preload_int_raw.rs
+++ b/esp32p4/src/cache/sync_l1_cache_preload_int_raw.rs
@@ -118,61 +118,49 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYNC_L1_CACHE_PRELOAD_INT_RAW")
             .field(
                 "l1_icache0_pld_done_int_raw",
-                &format_args!("{}", self.l1_icache0_pld_done_int_raw().bit()),
+                &self.l1_icache0_pld_done_int_raw(),
             )
             .field(
                 "l1_icache1_pld_done_int_raw",
-                &format_args!("{}", self.l1_icache1_pld_done_int_raw().bit()),
+                &self.l1_icache1_pld_done_int_raw(),
             )
             .field(
                 "l1_icache2_pld_done_int_raw",
-                &format_args!("{}", self.l1_icache2_pld_done_int_raw().bit()),
+                &self.l1_icache2_pld_done_int_raw(),
             )
             .field(
                 "l1_icache3_pld_done_int_raw",
-                &format_args!("{}", self.l1_icache3_pld_done_int_raw().bit()),
+                &self.l1_icache3_pld_done_int_raw(),
             )
             .field(
                 "l1_dcache_pld_done_int_raw",
-                &format_args!("{}", self.l1_dcache_pld_done_int_raw().bit()),
-            )
-            .field(
-                "sync_done_int_raw",
-                &format_args!("{}", self.sync_done_int_raw().bit()),
+                &self.l1_dcache_pld_done_int_raw(),
             )
+            .field("sync_done_int_raw", &self.sync_done_int_raw())
             .field(
                 "l1_icache0_pld_err_int_raw",
-                &format_args!("{}", self.l1_icache0_pld_err_int_raw().bit()),
+                &self.l1_icache0_pld_err_int_raw(),
             )
             .field(
                 "l1_icache1_pld_err_int_raw",
-                &format_args!("{}", self.l1_icache1_pld_err_int_raw().bit()),
+                &self.l1_icache1_pld_err_int_raw(),
             )
             .field(
                 "l1_icache2_pld_err_int_raw",
-                &format_args!("{}", self.l1_icache2_pld_err_int_raw().bit()),
+                &self.l1_icache2_pld_err_int_raw(),
             )
             .field(
                 "l1_icache3_pld_err_int_raw",
-                &format_args!("{}", self.l1_icache3_pld_err_int_raw().bit()),
+                &self.l1_icache3_pld_err_int_raw(),
             )
             .field(
                 "l1_dcache_pld_err_int_raw",
-                &format_args!("{}", self.l1_dcache_pld_err_int_raw().bit()),
-            )
-            .field(
-                "sync_err_int_raw",
-                &format_args!("{}", self.sync_err_int_raw().bit()),
+                &self.l1_dcache_pld_err_int_raw(),
             )
+            .field("sync_err_int_raw", &self.sync_err_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYNC_L1_CACHE_PRELOAD_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/sync_l1_cache_preload_int_st.rs b/esp32p4/src/cache/sync_l1_cache_preload_int_st.rs
index ae4857581a..6e7adca5e7 100644
--- a/esp32p4/src/cache/sync_l1_cache_preload_int_st.rs
+++ b/esp32p4/src/cache/sync_l1_cache_preload_int_st.rs
@@ -92,61 +92,46 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYNC_L1_CACHE_PRELOAD_INT_ST")
             .field(
                 "l1_icache0_pld_done_int_st",
-                &format_args!("{}", self.l1_icache0_pld_done_int_st().bit()),
+                &self.l1_icache0_pld_done_int_st(),
             )
             .field(
                 "l1_icache1_pld_done_int_st",
-                &format_args!("{}", self.l1_icache1_pld_done_int_st().bit()),
+                &self.l1_icache1_pld_done_int_st(),
             )
             .field(
                 "l1_icache2_pld_done_int_st",
-                &format_args!("{}", self.l1_icache2_pld_done_int_st().bit()),
+                &self.l1_icache2_pld_done_int_st(),
             )
             .field(
                 "l1_icache3_pld_done_int_st",
-                &format_args!("{}", self.l1_icache3_pld_done_int_st().bit()),
+                &self.l1_icache3_pld_done_int_st(),
             )
             .field(
                 "l1_dcache_pld_done_int_st",
-                &format_args!("{}", self.l1_dcache_pld_done_int_st().bit()),
-            )
-            .field(
-                "sync_done_int_st",
-                &format_args!("{}", self.sync_done_int_st().bit()),
+                &self.l1_dcache_pld_done_int_st(),
             )
+            .field("sync_done_int_st", &self.sync_done_int_st())
             .field(
                 "l1_icache0_pld_err_int_st",
-                &format_args!("{}", self.l1_icache0_pld_err_int_st().bit()),
+                &self.l1_icache0_pld_err_int_st(),
             )
             .field(
                 "l1_icache1_pld_err_int_st",
-                &format_args!("{}", self.l1_icache1_pld_err_int_st().bit()),
+                &self.l1_icache1_pld_err_int_st(),
             )
             .field(
                 "l1_icache2_pld_err_int_st",
-                &format_args!("{}", self.l1_icache2_pld_err_int_st().bit()),
+                &self.l1_icache2_pld_err_int_st(),
             )
             .field(
                 "l1_icache3_pld_err_int_st",
-                &format_args!("{}", self.l1_icache3_pld_err_int_st().bit()),
-            )
-            .field(
-                "l1_dcache_pld_err_int_st",
-                &format_args!("{}", self.l1_dcache_pld_err_int_st().bit()),
-            )
-            .field(
-                "sync_err_int_st",
-                &format_args!("{}", self.sync_err_int_st().bit()),
+                &self.l1_icache3_pld_err_int_st(),
             )
+            .field("l1_dcache_pld_err_int_st", &self.l1_dcache_pld_err_int_st())
+            .field("sync_err_int_st", &self.sync_err_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYNC_L1_CACHE_PRELOAD_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "L1-Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_l1_cache_preload_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SYNC_L1_CACHE_PRELOAD_INT_ST_SPEC;
 impl crate::RegisterSpec for SYNC_L1_CACHE_PRELOAD_INT_ST_SPEC {
diff --git a/esp32p4/src/cache/sync_map.rs b/esp32p4/src/cache/sync_map.rs
index 9ee08d5c36..adcbd90f34 100644
--- a/esp32p4/src/cache/sync_map.rs
+++ b/esp32p4/src/cache/sync_map.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYNC_MAP")
-            .field("sync_map", &format_args!("{}", self.sync_map().bits()))
+            .field("sync_map", &self.sync_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYNC_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation. \\[0\\]: L1-ICache0, \\[1\\]: L1-ICache1, \\[2\\]: L1-ICache2, \\[3\\]: L1-ICache3, \\[4\\]: L1-DCache, \\[5\\]: L2-Cache."]
     #[inline(always)]
diff --git a/esp32p4/src/cache/sync_size.rs b/esp32p4/src/cache/sync_size.rs
index 77436cc0a5..1ec17b262a 100644
--- a/esp32p4/src/cache/sync_size.rs
+++ b/esp32p4/src/cache/sync_size.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYNC_SIZE")
-            .field("sync_size", &format_args!("{}", self.sync_size().bits()))
+            .field("sync_size", &self.sync_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYNC_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/cfg0.rs b/esp32p4/src/dma/cfg0.rs
index e427180dcf..cde3b4d764 100644
--- a/esp32p4/src/dma/cfg0.rs
+++ b/esp32p4/src/dma/cfg0.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG0")
-            .field("dmac_en", &format_args!("{}", self.dmac_en().bit()))
-            .field("int_en", &format_args!("{}", self.int_en().bit()))
+            .field("dmac_en", &self.dmac_en())
+            .field("int_en", &self.int_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/axi_id0.rs b/esp32p4/src/dma/ch/axi_id0.rs
index 58a3bb1efd..0f7ba88f30 100644
--- a/esp32p4/src/dma/ch/axi_id0.rs
+++ b/esp32p4/src/dma/ch/axi_id0.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AXI_ID0")
-            .field(
-                "ch1_axi_read_id_suffix",
-                &format_args!("{}", self.ch1_axi_read_id_suffix().bit()),
-            )
-            .field(
-                "ch1_axi_write_id_suffix",
-                &format_args!("{}", self.ch1_axi_write_id_suffix().bit()),
-            )
+            .field("ch1_axi_read_id_suffix", &self.ch1_axi_read_id_suffix())
+            .field("ch1_axi_write_id_suffix", &self.ch1_axi_write_id_suffix())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_ID0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/axi_qos0.rs b/esp32p4/src/dma/ch/axi_qos0.rs
index de1c4678ff..f85622071a 100644
--- a/esp32p4/src/dma/ch/axi_qos0.rs
+++ b/esp32p4/src/dma/ch/axi_qos0.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AXI_QOS0")
-            .field(
-                "ch1_axi_awqos",
-                &format_args!("{}", self.ch1_axi_awqos().bits()),
-            )
-            .field(
-                "ch1_axi_arqos",
-                &format_args!("{}", self.ch1_axi_arqos().bits()),
-            )
+            .field("ch1_axi_awqos", &self.ch1_axi_awqos())
+            .field("ch1_axi_arqos", &self.ch1_axi_arqos())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_QOS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/block_ts0.rs b/esp32p4/src/dma/ch/block_ts0.rs
index 78f5c80a75..866c0cda48 100644
--- a/esp32p4/src/dma/ch/block_ts0.rs
+++ b/esp32p4/src/dma/ch/block_ts0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLOCK_TS0")
-            .field(
-                "ch1_block_ts",
-                &format_args!("{}", self.ch1_block_ts().bits()),
-            )
+            .field("ch1_block_ts", &self.ch1_block_ts())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLOCK_TS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/cfg0.rs b/esp32p4/src/dma/ch/cfg0.rs
index b27ca960d4..928d47215f 100644
--- a/esp32p4/src/dma/ch/cfg0.rs
+++ b/esp32p4/src/dma/ch/cfg0.rs
@@ -40,25 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG0")
-            .field(
-                "ch1_src_multblk_type",
-                &format_args!("{}", self.ch1_src_multblk_type().bits()),
-            )
-            .field(
-                "ch1_dst_multblk_type",
-                &format_args!("{}", self.ch1_dst_multblk_type().bits()),
-            )
-            .field("ch1_rd_uid", &format_args!("{}", self.ch1_rd_uid().bits()))
-            .field("ch1_wr_uid", &format_args!("{}", self.ch1_wr_uid().bits()))
+            .field("ch1_src_multblk_type", &self.ch1_src_multblk_type())
+            .field("ch1_dst_multblk_type", &self.ch1_dst_multblk_type())
+            .field("ch1_rd_uid", &self.ch1_rd_uid())
+            .field("ch1_wr_uid", &self.ch1_wr_uid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/cfg1.rs b/esp32p4/src/dma/ch/cfg1.rs
index 586676cd53..bb42fad486 100644
--- a/esp32p4/src/dma/ch/cfg1.rs
+++ b/esp32p4/src/dma/ch/cfg1.rs
@@ -108,57 +108,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG1")
-            .field("ch1_tt_fc", &format_args!("{}", self.ch1_tt_fc().bits()))
-            .field(
-                "ch1_hs_sel_src",
-                &format_args!("{}", self.ch1_hs_sel_src().bit()),
-            )
-            .field(
-                "ch1_hs_sel_dst",
-                &format_args!("{}", self.ch1_hs_sel_dst().bit()),
-            )
-            .field(
-                "ch1_src_hwhs_pol",
-                &format_args!("{}", self.ch1_src_hwhs_pol().bit()),
-            )
-            .field(
-                "ch1_dst_hwhs_pol",
-                &format_args!("{}", self.ch1_dst_hwhs_pol().bit()),
-            )
-            .field(
-                "ch1_src_per",
-                &format_args!("{}", self.ch1_src_per().bits()),
-            )
-            .field(
-                "ch1_dst_per",
-                &format_args!("{}", self.ch1_dst_per().bits()),
-            )
-            .field(
-                "ch1_ch_prior",
-                &format_args!("{}", self.ch1_ch_prior().bits()),
-            )
-            .field("ch1_lock_ch", &format_args!("{}", self.ch1_lock_ch().bit()))
-            .field(
-                "ch1_lock_ch_l",
-                &format_args!("{}", self.ch1_lock_ch_l().bits()),
-            )
-            .field(
-                "ch1_src_osr_lmt",
-                &format_args!("{}", self.ch1_src_osr_lmt().bits()),
-            )
-            .field(
-                "ch1_dst_osr_lmt",
-                &format_args!("{}", self.ch1_dst_osr_lmt().bits()),
-            )
+            .field("ch1_tt_fc", &self.ch1_tt_fc())
+            .field("ch1_hs_sel_src", &self.ch1_hs_sel_src())
+            .field("ch1_hs_sel_dst", &self.ch1_hs_sel_dst())
+            .field("ch1_src_hwhs_pol", &self.ch1_src_hwhs_pol())
+            .field("ch1_dst_hwhs_pol", &self.ch1_dst_hwhs_pol())
+            .field("ch1_src_per", &self.ch1_src_per())
+            .field("ch1_dst_per", &self.ch1_dst_per())
+            .field("ch1_ch_prior", &self.ch1_ch_prior())
+            .field("ch1_lock_ch", &self.ch1_lock_ch())
+            .field("ch1_lock_ch_l", &self.ch1_lock_ch_l())
+            .field("ch1_src_osr_lmt", &self.ch1_src_osr_lmt())
+            .field("ch1_dst_osr_lmt", &self.ch1_dst_osr_lmt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/ctl0.rs b/esp32p4/src/dma/ch/ctl0.rs
index bb96a6235d..c554aca147 100644
--- a/esp32p4/src/dma/ch/ctl0.rs
+++ b/esp32p4/src/dma/ch/ctl0.rs
@@ -107,47 +107,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTL0")
-            .field("ch1_sms", &format_args!("{}", self.ch1_sms().bit()))
-            .field("ch1_dms", &format_args!("{}", self.ch1_dms().bit()))
-            .field("ch1_sinc", &format_args!("{}", self.ch1_sinc().bit()))
-            .field("ch1_dinc", &format_args!("{}", self.ch1_dinc().bit()))
-            .field(
-                "ch1_src_tr_width",
-                &format_args!("{}", self.ch1_src_tr_width().bits()),
-            )
-            .field(
-                "ch1_dst_tr_width",
-                &format_args!("{}", self.ch1_dst_tr_width().bits()),
-            )
-            .field(
-                "ch1_src_msize",
-                &format_args!("{}", self.ch1_src_msize().bits()),
-            )
-            .field(
-                "ch1_dst_msize",
-                &format_args!("{}", self.ch1_dst_msize().bits()),
-            )
-            .field(
-                "ch1_ar_cache",
-                &format_args!("{}", self.ch1_ar_cache().bits()),
-            )
-            .field(
-                "ch1_aw_cache",
-                &format_args!("{}", self.ch1_aw_cache().bits()),
-            )
+            .field("ch1_sms", &self.ch1_sms())
+            .field("ch1_dms", &self.ch1_dms())
+            .field("ch1_sinc", &self.ch1_sinc())
+            .field("ch1_dinc", &self.ch1_dinc())
+            .field("ch1_src_tr_width", &self.ch1_src_tr_width())
+            .field("ch1_dst_tr_width", &self.ch1_dst_tr_width())
+            .field("ch1_src_msize", &self.ch1_src_msize())
+            .field("ch1_dst_msize", &self.ch1_dst_msize())
+            .field("ch1_ar_cache", &self.ch1_ar_cache())
+            .field("ch1_aw_cache", &self.ch1_aw_cache())
             .field(
                 "ch1_nonposted_lastwrite_en",
-                &format_args!("{}", self.ch1_nonposted_lastwrite_en().bit()),
+                &self.ch1_nonposted_lastwrite_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/ctl1.rs b/esp32p4/src/dma/ch/ctl1.rs
index a51fb88343..0cba2913e1 100644
--- a/esp32p4/src/dma/ch/ctl1.rs
+++ b/esp32p4/src/dma/ch/ctl1.rs
@@ -107,53 +107,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTL1")
-            .field(
-                "ch1_ar_prot",
-                &format_args!("{}", self.ch1_ar_prot().bits()),
-            )
-            .field(
-                "ch1_aw_prot",
-                &format_args!("{}", self.ch1_aw_prot().bits()),
-            )
-            .field(
-                "ch1_arlen_en",
-                &format_args!("{}", self.ch1_arlen_en().bit()),
-            )
-            .field("ch1_arlen", &format_args!("{}", self.ch1_arlen().bits()))
-            .field(
-                "ch1_awlen_en",
-                &format_args!("{}", self.ch1_awlen_en().bit()),
-            )
-            .field("ch1_awlen", &format_args!("{}", self.ch1_awlen().bits()))
-            .field(
-                "ch1_src_stat_en",
-                &format_args!("{}", self.ch1_src_stat_en().bit()),
-            )
-            .field(
-                "ch1_dst_stat_en",
-                &format_args!("{}", self.ch1_dst_stat_en().bit()),
-            )
-            .field(
-                "ch1_ioc_blktfr",
-                &format_args!("{}", self.ch1_ioc_blktfr().bit()),
-            )
+            .field("ch1_ar_prot", &self.ch1_ar_prot())
+            .field("ch1_aw_prot", &self.ch1_aw_prot())
+            .field("ch1_arlen_en", &self.ch1_arlen_en())
+            .field("ch1_arlen", &self.ch1_arlen())
+            .field("ch1_awlen_en", &self.ch1_awlen_en())
+            .field("ch1_awlen", &self.ch1_awlen())
+            .field("ch1_src_stat_en", &self.ch1_src_stat_en())
+            .field("ch1_dst_stat_en", &self.ch1_dst_stat_en())
+            .field("ch1_ioc_blktfr", &self.ch1_ioc_blktfr())
             .field(
                 "ch1_shadowreg_or_lli_last",
-                &format_args!("{}", self.ch1_shadowreg_or_lli_last().bit()),
+                &self.ch1_shadowreg_or_lli_last(),
             )
             .field(
                 "ch1_shadowreg_or_lli_valid",
-                &format_args!("{}", self.ch1_shadowreg_or_lli_valid().bit()),
+                &self.ch1_shadowreg_or_lli_valid(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/dar0.rs b/esp32p4/src/dma/ch/dar0.rs
index 1160e52ef8..aded15e423 100644
--- a/esp32p4/src/dma/ch/dar0.rs
+++ b/esp32p4/src/dma/ch/dar0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DAR0")
-            .field("ch1_dar0", &format_args!("{}", self.ch1_dar0().bits()))
+            .field("ch1_dar0", &self.ch1_dar0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DAR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/dar1.rs b/esp32p4/src/dma/ch/dar1.rs
index cb9467917f..ab60b9426f 100644
--- a/esp32p4/src/dma/ch/dar1.rs
+++ b/esp32p4/src/dma/ch/dar1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DAR1")
-            .field("ch1_dar1", &format_args!("{}", self.ch1_dar1().bits()))
+            .field("ch1_dar1", &self.ch1_dar1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DAR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/dstat0.rs b/esp32p4/src/dma/ch/dstat0.rs
index 290383f1b4..c1b2dd2018 100644
--- a/esp32p4/src/dma/ch/dstat0.rs
+++ b/esp32p4/src/dma/ch/dstat0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSTAT0")
-            .field("ch1_dstat", &format_args!("{}", self.ch1_dstat().bits()))
+            .field("ch1_dstat", &self.ch1_dstat())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSTAT0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dstat0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DSTAT0_SPEC;
 impl crate::RegisterSpec for DSTAT0_SPEC {
diff --git a/esp32p4/src/dma/ch/dstatar0.rs b/esp32p4/src/dma/ch/dstatar0.rs
index 8fb27840a8..3476d43a46 100644
--- a/esp32p4/src/dma/ch/dstatar0.rs
+++ b/esp32p4/src/dma/ch/dstatar0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSTATAR0")
-            .field(
-                "ch1_dstatar0",
-                &format_args!("{}", self.ch1_dstatar0().bits()),
-            )
+            .field("ch1_dstatar0", &self.ch1_dstatar0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSTATAR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/dstatar1.rs b/esp32p4/src/dma/ch/dstatar1.rs
index b17c5ff3d7..99c6f98f88 100644
--- a/esp32p4/src/dma/ch/dstatar1.rs
+++ b/esp32p4/src/dma/ch/dstatar1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSTATAR1")
-            .field(
-                "ch1_dstatar1",
-                &format_args!("{}", self.ch1_dstatar1().bits()),
-            )
+            .field("ch1_dstatar1", &self.ch1_dstatar1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSTATAR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/intsignal_enable0.rs b/esp32p4/src/dma/ch/intsignal_enable0.rs
index 02ffaccfb9..78c3a1dc1d 100644
--- a/esp32p4/src/dma/ch/intsignal_enable0.rs
+++ b/esp32p4/src/dma/ch/intsignal_enable0.rs
@@ -254,128 +254,111 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTSIGNAL_ENABLE0")
             .field(
                 "ch1_enable_block_tfr_done_intsignal",
-                &format_args!("{}", self.ch1_enable_block_tfr_done_intsignal().bit()),
+                &self.ch1_enable_block_tfr_done_intsignal(),
             )
             .field(
                 "ch1_enable_dma_tfr_done_intsignal",
-                &format_args!("{}", self.ch1_enable_dma_tfr_done_intsignal().bit()),
+                &self.ch1_enable_dma_tfr_done_intsignal(),
             )
             .field(
                 "ch1_enable_src_transcomp_intsignal",
-                &format_args!("{}", self.ch1_enable_src_transcomp_intsignal().bit()),
+                &self.ch1_enable_src_transcomp_intsignal(),
             )
             .field(
                 "ch1_enable_dst_transcomp_intsignal",
-                &format_args!("{}", self.ch1_enable_dst_transcomp_intsignal().bit()),
+                &self.ch1_enable_dst_transcomp_intsignal(),
             )
             .field(
                 "ch1_enable_src_dec_err_intsignal",
-                &format_args!("{}", self.ch1_enable_src_dec_err_intsignal().bit()),
+                &self.ch1_enable_src_dec_err_intsignal(),
             )
             .field(
                 "ch1_enable_dst_dec_err_intsignal",
-                &format_args!("{}", self.ch1_enable_dst_dec_err_intsignal().bit()),
+                &self.ch1_enable_dst_dec_err_intsignal(),
             )
             .field(
                 "ch1_enable_src_slv_err_intsignal",
-                &format_args!("{}", self.ch1_enable_src_slv_err_intsignal().bit()),
+                &self.ch1_enable_src_slv_err_intsignal(),
             )
             .field(
                 "ch1_enable_dst_slv_err_intsignal",
-                &format_args!("{}", self.ch1_enable_dst_slv_err_intsignal().bit()),
+                &self.ch1_enable_dst_slv_err_intsignal(),
             )
             .field(
                 "ch1_enable_lli_rd_dec_err_intsignal",
-                &format_args!("{}", self.ch1_enable_lli_rd_dec_err_intsignal().bit()),
+                &self.ch1_enable_lli_rd_dec_err_intsignal(),
             )
             .field(
                 "ch1_enable_lli_wr_dec_err_intsignal",
-                &format_args!("{}", self.ch1_enable_lli_wr_dec_err_intsignal().bit()),
+                &self.ch1_enable_lli_wr_dec_err_intsignal(),
             )
             .field(
                 "ch1_enable_lli_rd_slv_err_intsignal",
-                &format_args!("{}", self.ch1_enable_lli_rd_slv_err_intsignal().bit()),
+                &self.ch1_enable_lli_rd_slv_err_intsignal(),
             )
             .field(
                 "ch1_enable_lli_wr_slv_err_intsignal",
-                &format_args!("{}", self.ch1_enable_lli_wr_slv_err_intsignal().bit()),
+                &self.ch1_enable_lli_wr_slv_err_intsignal(),
             )
             .field(
                 "ch1_enable_shadowreg_or_lli_invalid_err_intsignal",
-                &format_args!(
-                    "{}",
-                    self.ch1_enable_shadowreg_or_lli_invalid_err_intsignal()
-                        .bit()
-                ),
+                &self.ch1_enable_shadowreg_or_lli_invalid_err_intsignal(),
             )
             .field(
                 "ch1_enable_slvif_multiblktype_err_intsignal",
-                &format_args!(
-                    "{}",
-                    self.ch1_enable_slvif_multiblktype_err_intsignal().bit()
-                ),
+                &self.ch1_enable_slvif_multiblktype_err_intsignal(),
             )
             .field(
                 "ch1_enable_slvif_dec_err_intsignal",
-                &format_args!("{}", self.ch1_enable_slvif_dec_err_intsignal().bit()),
+                &self.ch1_enable_slvif_dec_err_intsignal(),
             )
             .field(
                 "ch1_enable_slvif_wr2ro_err_intsignal",
-                &format_args!("{}", self.ch1_enable_slvif_wr2ro_err_intsignal().bit()),
+                &self.ch1_enable_slvif_wr2ro_err_intsignal(),
             )
             .field(
                 "ch1_enable_slvif_rd2rwo_err_intsignal",
-                &format_args!("{}", self.ch1_enable_slvif_rd2rwo_err_intsignal().bit()),
+                &self.ch1_enable_slvif_rd2rwo_err_intsignal(),
             )
             .field(
                 "ch1_enable_slvif_wronchen_err_intsignal",
-                &format_args!("{}", self.ch1_enable_slvif_wronchen_err_intsignal().bit()),
+                &self.ch1_enable_slvif_wronchen_err_intsignal(),
             )
             .field(
                 "ch1_enable_slvif_shadowreg_wron_valid_err_intsignal",
-                &format_args!(
-                    "{}",
-                    self.ch1_enable_slvif_shadowreg_wron_valid_err_intsignal()
-                        .bit()
-                ),
+                &self.ch1_enable_slvif_shadowreg_wron_valid_err_intsignal(),
             )
             .field(
                 "ch1_enable_slvif_wronhold_err_intsignal",
-                &format_args!("{}", self.ch1_enable_slvif_wronhold_err_intsignal().bit()),
+                &self.ch1_enable_slvif_wronhold_err_intsignal(),
             )
             .field(
                 "ch1_enable_slvif_wrparity_err_intsignal",
-                &format_args!("{}", self.ch1_enable_slvif_wrparity_err_intsignal().bit()),
+                &self.ch1_enable_slvif_wrparity_err_intsignal(),
             )
             .field(
                 "ch1_enable_ch_lock_cleared_intsignal",
-                &format_args!("{}", self.ch1_enable_ch_lock_cleared_intsignal().bit()),
+                &self.ch1_enable_ch_lock_cleared_intsignal(),
             )
             .field(
                 "ch1_enable_ch_src_suspended_intsignal",
-                &format_args!("{}", self.ch1_enable_ch_src_suspended_intsignal().bit()),
+                &self.ch1_enable_ch_src_suspended_intsignal(),
             )
             .field(
                 "ch1_enable_ch_suspended_intsignal",
-                &format_args!("{}", self.ch1_enable_ch_suspended_intsignal().bit()),
+                &self.ch1_enable_ch_suspended_intsignal(),
             )
             .field(
                 "ch1_enable_ch_disabled_intsignal",
-                &format_args!("{}", self.ch1_enable_ch_disabled_intsignal().bit()),
+                &self.ch1_enable_ch_disabled_intsignal(),
             )
             .field(
                 "ch1_enable_ch_aborted_intsignal",
-                &format_args!("{}", self.ch1_enable_ch_aborted_intsignal().bit()),
+                &self.ch1_enable_ch_aborted_intsignal(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTSIGNAL_ENABLE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/intsignal_enable1.rs b/esp32p4/src/dma/ch/intsignal_enable1.rs
index 0beb0d8cad..651851c41d 100644
--- a/esp32p4/src/dma/ch/intsignal_enable1.rs
+++ b/esp32p4/src/dma/ch/intsignal_enable1.rs
@@ -44,41 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTSIGNAL_ENABLE1")
             .field(
                 "ch1_enable_ecc_prot_chmem_correrr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.ch1_enable_ecc_prot_chmem_correrr_intsignal().bit()
-                ),
+                &self.ch1_enable_ecc_prot_chmem_correrr_intsignal(),
             )
             .field(
                 "ch1_enable_ecc_prot_chmem_uncorrerr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.ch1_enable_ecc_prot_chmem_uncorrerr_intsignal().bit()
-                ),
+                &self.ch1_enable_ecc_prot_chmem_uncorrerr_intsignal(),
             )
             .field(
                 "ch1_enable_ecc_prot_uidmem_correrr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.ch1_enable_ecc_prot_uidmem_correrr_intsignal().bit()
-                ),
+                &self.ch1_enable_ecc_prot_uidmem_correrr_intsignal(),
             )
             .field(
                 "ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal().bit()
-                ),
+                &self.ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTSIGNAL_ENABLE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intsignal_enable1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTSIGNAL_ENABLE1_SPEC;
 impl crate::RegisterSpec for INTSIGNAL_ENABLE1_SPEC {
diff --git a/esp32p4/src/dma/ch/intstatus0.rs b/esp32p4/src/dma/ch/intstatus0.rs
index dd2db6892b..203a6cc364 100644
--- a/esp32p4/src/dma/ch/intstatus0.rs
+++ b/esp32p4/src/dma/ch/intstatus0.rs
@@ -194,120 +194,87 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTSTATUS0")
             .field(
                 "ch1_block_tfr_done_intstat",
-                &format_args!("{}", self.ch1_block_tfr_done_intstat().bit()),
-            )
-            .field(
-                "ch1_dma_tfr_done_intstat",
-                &format_args!("{}", self.ch1_dma_tfr_done_intstat().bit()),
+                &self.ch1_block_tfr_done_intstat(),
             )
+            .field("ch1_dma_tfr_done_intstat", &self.ch1_dma_tfr_done_intstat())
             .field(
                 "ch1_src_transcomp_intstat",
-                &format_args!("{}", self.ch1_src_transcomp_intstat().bit()),
+                &self.ch1_src_transcomp_intstat(),
             )
             .field(
                 "ch1_dst_transcomp_intstat",
-                &format_args!("{}", self.ch1_dst_transcomp_intstat().bit()),
-            )
-            .field(
-                "ch1_src_dec_err_intstat",
-                &format_args!("{}", self.ch1_src_dec_err_intstat().bit()),
-            )
-            .field(
-                "ch1_dst_dec_err_intstat",
-                &format_args!("{}", self.ch1_dst_dec_err_intstat().bit()),
-            )
-            .field(
-                "ch1_src_slv_err_intstat",
-                &format_args!("{}", self.ch1_src_slv_err_intstat().bit()),
-            )
-            .field(
-                "ch1_dst_slv_err_intstat",
-                &format_args!("{}", self.ch1_dst_slv_err_intstat().bit()),
+                &self.ch1_dst_transcomp_intstat(),
             )
+            .field("ch1_src_dec_err_intstat", &self.ch1_src_dec_err_intstat())
+            .field("ch1_dst_dec_err_intstat", &self.ch1_dst_dec_err_intstat())
+            .field("ch1_src_slv_err_intstat", &self.ch1_src_slv_err_intstat())
+            .field("ch1_dst_slv_err_intstat", &self.ch1_dst_slv_err_intstat())
             .field(
                 "ch1_lli_rd_dec_err_intstat",
-                &format_args!("{}", self.ch1_lli_rd_dec_err_intstat().bit()),
+                &self.ch1_lli_rd_dec_err_intstat(),
             )
             .field(
                 "ch1_lli_wr_dec_err_intstat",
-                &format_args!("{}", self.ch1_lli_wr_dec_err_intstat().bit()),
+                &self.ch1_lli_wr_dec_err_intstat(),
             )
             .field(
                 "ch1_lli_rd_slv_err_intstat",
-                &format_args!("{}", self.ch1_lli_rd_slv_err_intstat().bit()),
+                &self.ch1_lli_rd_slv_err_intstat(),
             )
             .field(
                 "ch1_lli_wr_slv_err_intstat",
-                &format_args!("{}", self.ch1_lli_wr_slv_err_intstat().bit()),
+                &self.ch1_lli_wr_slv_err_intstat(),
             )
             .field(
                 "ch1_shadowreg_or_lli_invalid_err_intstat",
-                &format_args!("{}", self.ch1_shadowreg_or_lli_invalid_err_intstat().bit()),
+                &self.ch1_shadowreg_or_lli_invalid_err_intstat(),
             )
             .field(
                 "ch1_slvif_multiblktype_err_intstat",
-                &format_args!("{}", self.ch1_slvif_multiblktype_err_intstat().bit()),
+                &self.ch1_slvif_multiblktype_err_intstat(),
             )
             .field(
                 "ch1_slvif_dec_err_intstat",
-                &format_args!("{}", self.ch1_slvif_dec_err_intstat().bit()),
+                &self.ch1_slvif_dec_err_intstat(),
             )
             .field(
                 "ch1_slvif_wr2ro_err_intstat",
-                &format_args!("{}", self.ch1_slvif_wr2ro_err_intstat().bit()),
+                &self.ch1_slvif_wr2ro_err_intstat(),
             )
             .field(
                 "ch1_slvif_rd2rwo_err_intstat",
-                &format_args!("{}", self.ch1_slvif_rd2rwo_err_intstat().bit()),
+                &self.ch1_slvif_rd2rwo_err_intstat(),
             )
             .field(
                 "ch1_slvif_wronchen_err_intstat",
-                &format_args!("{}", self.ch1_slvif_wronchen_err_intstat().bit()),
+                &self.ch1_slvif_wronchen_err_intstat(),
             )
             .field(
                 "ch1_slvif_shadowreg_wron_valid_err_intstat",
-                &format_args!(
-                    "{}",
-                    self.ch1_slvif_shadowreg_wron_valid_err_intstat().bit()
-                ),
+                &self.ch1_slvif_shadowreg_wron_valid_err_intstat(),
             )
             .field(
                 "ch1_slvif_wronhold_err_intstat",
-                &format_args!("{}", self.ch1_slvif_wronhold_err_intstat().bit()),
+                &self.ch1_slvif_wronhold_err_intstat(),
             )
             .field(
                 "ch1_slvif_wrparity_err_intstat",
-                &format_args!("{}", self.ch1_slvif_wrparity_err_intstat().bit()),
+                &self.ch1_slvif_wrparity_err_intstat(),
             )
             .field(
                 "ch1_ch_lock_cleared_intstat",
-                &format_args!("{}", self.ch1_ch_lock_cleared_intstat().bit()),
+                &self.ch1_ch_lock_cleared_intstat(),
             )
             .field(
                 "ch1_ch_src_suspended_intstat",
-                &format_args!("{}", self.ch1_ch_src_suspended_intstat().bit()),
-            )
-            .field(
-                "ch1_ch_suspended_intstat",
-                &format_args!("{}", self.ch1_ch_suspended_intstat().bit()),
-            )
-            .field(
-                "ch1_ch_disabled_intstat",
-                &format_args!("{}", self.ch1_ch_disabled_intstat().bit()),
-            )
-            .field(
-                "ch1_ch_aborted_intstat",
-                &format_args!("{}", self.ch1_ch_aborted_intstat().bit()),
+                &self.ch1_ch_src_suspended_intstat(),
             )
+            .field("ch1_ch_suspended_intstat", &self.ch1_ch_suspended_intstat())
+            .field("ch1_ch_disabled_intstat", &self.ch1_ch_disabled_intstat())
+            .field("ch1_ch_aborted_intstat", &self.ch1_ch_aborted_intstat())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTSTATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intstatus0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTSTATUS0_SPEC;
 impl crate::RegisterSpec for INTSTATUS0_SPEC {
diff --git a/esp32p4/src/dma/ch/intstatus1.rs b/esp32p4/src/dma/ch/intstatus1.rs
index 3fee2c683a..6663f79ccb 100644
--- a/esp32p4/src/dma/ch/intstatus1.rs
+++ b/esp32p4/src/dma/ch/intstatus1.rs
@@ -36,29 +36,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTSTATUS1")
             .field(
                 "ch1_ecc_prot_chmem_correrr_intstat",
-                &format_args!("{}", self.ch1_ecc_prot_chmem_correrr_intstat().bit()),
+                &self.ch1_ecc_prot_chmem_correrr_intstat(),
             )
             .field(
                 "ch1_ecc_prot_chmem_uncorrerr_intstat",
-                &format_args!("{}", self.ch1_ecc_prot_chmem_uncorrerr_intstat().bit()),
+                &self.ch1_ecc_prot_chmem_uncorrerr_intstat(),
             )
             .field(
                 "ch1_ecc_prot_uidmem_correrr_intstat",
-                &format_args!("{}", self.ch1_ecc_prot_uidmem_correrr_intstat().bit()),
+                &self.ch1_ecc_prot_uidmem_correrr_intstat(),
             )
             .field(
                 "ch1_ecc_prot_uidmem_uncorrerr_intstat",
-                &format_args!("{}", self.ch1_ecc_prot_uidmem_uncorrerr_intstat().bit()),
+                &self.ch1_ecc_prot_uidmem_uncorrerr_intstat(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTSTATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intstatus1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTSTATUS1_SPEC;
 impl crate::RegisterSpec for INTSTATUS1_SPEC {
diff --git a/esp32p4/src/dma/ch/intstatus_enable0.rs b/esp32p4/src/dma/ch/intstatus_enable0.rs
index 4c4bf9b726..2a39186ba6 100644
--- a/esp32p4/src/dma/ch/intstatus_enable0.rs
+++ b/esp32p4/src/dma/ch/intstatus_enable0.rs
@@ -248,124 +248,111 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTSTATUS_ENABLE0")
             .field(
                 "ch1_enable_block_tfr_done_intstat",
-                &format_args!("{}", self.ch1_enable_block_tfr_done_intstat().bit()),
+                &self.ch1_enable_block_tfr_done_intstat(),
             )
             .field(
                 "ch1_enable_dma_tfr_done_intstat",
-                &format_args!("{}", self.ch1_enable_dma_tfr_done_intstat().bit()),
+                &self.ch1_enable_dma_tfr_done_intstat(),
             )
             .field(
                 "ch1_enable_src_transcomp_intstat",
-                &format_args!("{}", self.ch1_enable_src_transcomp_intstat().bit()),
+                &self.ch1_enable_src_transcomp_intstat(),
             )
             .field(
                 "ch1_enable_dst_transcomp_intstat",
-                &format_args!("{}", self.ch1_enable_dst_transcomp_intstat().bit()),
+                &self.ch1_enable_dst_transcomp_intstat(),
             )
             .field(
                 "ch1_enable_src_dec_err_intstat",
-                &format_args!("{}", self.ch1_enable_src_dec_err_intstat().bit()),
+                &self.ch1_enable_src_dec_err_intstat(),
             )
             .field(
                 "ch1_enable_dst_dec_err_intstat",
-                &format_args!("{}", self.ch1_enable_dst_dec_err_intstat().bit()),
+                &self.ch1_enable_dst_dec_err_intstat(),
             )
             .field(
                 "ch1_enable_src_slv_err_intstat",
-                &format_args!("{}", self.ch1_enable_src_slv_err_intstat().bit()),
+                &self.ch1_enable_src_slv_err_intstat(),
             )
             .field(
                 "ch1_enable_dst_slv_err_intstat",
-                &format_args!("{}", self.ch1_enable_dst_slv_err_intstat().bit()),
+                &self.ch1_enable_dst_slv_err_intstat(),
             )
             .field(
                 "ch1_enable_lli_rd_dec_err_intstat",
-                &format_args!("{}", self.ch1_enable_lli_rd_dec_err_intstat().bit()),
+                &self.ch1_enable_lli_rd_dec_err_intstat(),
             )
             .field(
                 "ch1_enable_lli_wr_dec_err_intstat",
-                &format_args!("{}", self.ch1_enable_lli_wr_dec_err_intstat().bit()),
+                &self.ch1_enable_lli_wr_dec_err_intstat(),
             )
             .field(
                 "ch1_enable_lli_rd_slv_err_intstat",
-                &format_args!("{}", self.ch1_enable_lli_rd_slv_err_intstat().bit()),
+                &self.ch1_enable_lli_rd_slv_err_intstat(),
             )
             .field(
                 "ch1_enable_lli_wr_slv_err_intstat",
-                &format_args!("{}", self.ch1_enable_lli_wr_slv_err_intstat().bit()),
+                &self.ch1_enable_lli_wr_slv_err_intstat(),
             )
             .field(
                 "ch1_enable_shadowreg_or_lli_invalid_err_intstat",
-                &format_args!(
-                    "{}",
-                    self.ch1_enable_shadowreg_or_lli_invalid_err_intstat().bit()
-                ),
+                &self.ch1_enable_shadowreg_or_lli_invalid_err_intstat(),
             )
             .field(
                 "ch1_enable_slvif_multiblktype_err_intstat",
-                &format_args!("{}", self.ch1_enable_slvif_multiblktype_err_intstat().bit()),
+                &self.ch1_enable_slvif_multiblktype_err_intstat(),
             )
             .field(
                 "ch1_enable_slvif_dec_err_intstat",
-                &format_args!("{}", self.ch1_enable_slvif_dec_err_intstat().bit()),
+                &self.ch1_enable_slvif_dec_err_intstat(),
             )
             .field(
                 "ch1_enable_slvif_wr2ro_err_intstat",
-                &format_args!("{}", self.ch1_enable_slvif_wr2ro_err_intstat().bit()),
+                &self.ch1_enable_slvif_wr2ro_err_intstat(),
             )
             .field(
                 "ch1_enable_slvif_rd2rwo_err_intstat",
-                &format_args!("{}", self.ch1_enable_slvif_rd2rwo_err_intstat().bit()),
+                &self.ch1_enable_slvif_rd2rwo_err_intstat(),
             )
             .field(
                 "ch1_enable_slvif_wronchen_err_intstat",
-                &format_args!("{}", self.ch1_enable_slvif_wronchen_err_intstat().bit()),
+                &self.ch1_enable_slvif_wronchen_err_intstat(),
             )
             .field(
                 "ch1_enable_slvif_shadowreg_wron_valid_err_intstat",
-                &format_args!(
-                    "{}",
-                    self.ch1_enable_slvif_shadowreg_wron_valid_err_intstat()
-                        .bit()
-                ),
+                &self.ch1_enable_slvif_shadowreg_wron_valid_err_intstat(),
             )
             .field(
                 "ch1_enable_slvif_wronhold_err_intstat",
-                &format_args!("{}", self.ch1_enable_slvif_wronhold_err_intstat().bit()),
+                &self.ch1_enable_slvif_wronhold_err_intstat(),
             )
             .field(
                 "ch1_enable_slvif_wrparity_err_intstat",
-                &format_args!("{}", self.ch1_enable_slvif_wrparity_err_intstat().bit()),
+                &self.ch1_enable_slvif_wrparity_err_intstat(),
             )
             .field(
                 "ch1_enable_ch_lock_cleared_intstat",
-                &format_args!("{}", self.ch1_enable_ch_lock_cleared_intstat().bit()),
+                &self.ch1_enable_ch_lock_cleared_intstat(),
             )
             .field(
                 "ch1_enable_ch_src_suspended_intstat",
-                &format_args!("{}", self.ch1_enable_ch_src_suspended_intstat().bit()),
+                &self.ch1_enable_ch_src_suspended_intstat(),
             )
             .field(
                 "ch1_enable_ch_suspended_intstat",
-                &format_args!("{}", self.ch1_enable_ch_suspended_intstat().bit()),
+                &self.ch1_enable_ch_suspended_intstat(),
             )
             .field(
                 "ch1_enable_ch_disabled_intstat",
-                &format_args!("{}", self.ch1_enable_ch_disabled_intstat().bit()),
+                &self.ch1_enable_ch_disabled_intstat(),
             )
             .field(
                 "ch1_enable_ch_aborted_intstat",
-                &format_args!("{}", self.ch1_enable_ch_aborted_intstat().bit()),
+                &self.ch1_enable_ch_aborted_intstat(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTSTATUS_ENABLE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/intstatus_enable1.rs b/esp32p4/src/dma/ch/intstatus_enable1.rs
index a3be070083..64ef1c34f3 100644
--- a/esp32p4/src/dma/ch/intstatus_enable1.rs
+++ b/esp32p4/src/dma/ch/intstatus_enable1.rs
@@ -44,38 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTSTATUS_ENABLE1")
             .field(
                 "ch1_enable_ecc_prot_chmem_correrr_intstat",
-                &format_args!("{}", self.ch1_enable_ecc_prot_chmem_correrr_intstat().bit()),
+                &self.ch1_enable_ecc_prot_chmem_correrr_intstat(),
             )
             .field(
                 "ch1_enable_ecc_prot_chmem_uncorrerr_intstat",
-                &format_args!(
-                    "{}",
-                    self.ch1_enable_ecc_prot_chmem_uncorrerr_intstat().bit()
-                ),
+                &self.ch1_enable_ecc_prot_chmem_uncorrerr_intstat(),
             )
             .field(
                 "ch1_enable_ecc_prot_uidmem_correrr_intstat",
-                &format_args!(
-                    "{}",
-                    self.ch1_enable_ecc_prot_uidmem_correrr_intstat().bit()
-                ),
+                &self.ch1_enable_ecc_prot_uidmem_correrr_intstat(),
             )
             .field(
                 "ch1_enable_ecc_prot_uidmem_uncorrerr_intstat",
-                &format_args!(
-                    "{}",
-                    self.ch1_enable_ecc_prot_uidmem_uncorrerr_intstat().bit()
-                ),
+                &self.ch1_enable_ecc_prot_uidmem_uncorrerr_intstat(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTSTATUS_ENABLE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intstatus_enable1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTSTATUS_ENABLE1_SPEC;
 impl crate::RegisterSpec for INTSTATUS_ENABLE1_SPEC {
diff --git a/esp32p4/src/dma/ch/llp0.rs b/esp32p4/src/dma/ch/llp0.rs
index 8381c82fcd..1b332778d4 100644
--- a/esp32p4/src/dma/ch/llp0.rs
+++ b/esp32p4/src/dma/ch/llp0.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LLP0")
-            .field("ch1_lms", &format_args!("{}", self.ch1_lms().bit()))
-            .field("ch1_loc0", &format_args!("{}", self.ch1_loc0().bits()))
+            .field("ch1_lms", &self.ch1_lms())
+            .field("ch1_loc0", &self.ch1_loc0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LLP0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/llp1.rs b/esp32p4/src/dma/ch/llp1.rs
index 16c8691aba..b8831ff62b 100644
--- a/esp32p4/src/dma/ch/llp1.rs
+++ b/esp32p4/src/dma/ch/llp1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LLP1")
-            .field("ch1_loc1", &format_args!("{}", self.ch1_loc1().bits()))
+            .field("ch1_loc1", &self.ch1_loc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LLP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/sar0.rs b/esp32p4/src/dma/ch/sar0.rs
index 950d1f2c82..fd743cc181 100644
--- a/esp32p4/src/dma/ch/sar0.rs
+++ b/esp32p4/src/dma/ch/sar0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR0")
-            .field("ch1_sar0", &format_args!("{}", self.ch1_sar0().bits()))
+            .field("ch1_sar0", &self.ch1_sar0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/sar1.rs b/esp32p4/src/dma/ch/sar1.rs
index d352aefb08..78017d308f 100644
--- a/esp32p4/src/dma/ch/sar1.rs
+++ b/esp32p4/src/dma/ch/sar1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1")
-            .field("ch1_sar1", &format_args!("{}", self.ch1_sar1().bits()))
+            .field("ch1_sar1", &self.ch1_sar1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/sstat0.rs b/esp32p4/src/dma/ch/sstat0.rs
index 633c409e47..cc7068dbe0 100644
--- a/esp32p4/src/dma/ch/sstat0.rs
+++ b/esp32p4/src/dma/ch/sstat0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SSTAT0")
-            .field("ch1_sstat", &format_args!("{}", self.ch1_sstat().bits()))
+            .field("ch1_sstat", &self.ch1_sstat())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SSTAT0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sstat0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SSTAT0_SPEC;
 impl crate::RegisterSpec for SSTAT0_SPEC {
diff --git a/esp32p4/src/dma/ch/sstatar0.rs b/esp32p4/src/dma/ch/sstatar0.rs
index 8478c4954e..f20fa87cb1 100644
--- a/esp32p4/src/dma/ch/sstatar0.rs
+++ b/esp32p4/src/dma/ch/sstatar0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SSTATAR0")
-            .field(
-                "ch1_sstatar0",
-                &format_args!("{}", self.ch1_sstatar0().bits()),
-            )
+            .field("ch1_sstatar0", &self.ch1_sstatar0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SSTATAR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/sstatar1.rs b/esp32p4/src/dma/ch/sstatar1.rs
index 4ffeea704a..7ef48102c7 100644
--- a/esp32p4/src/dma/ch/sstatar1.rs
+++ b/esp32p4/src/dma/ch/sstatar1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SSTATAR1")
-            .field(
-                "ch1_sstatar1",
-                &format_args!("{}", self.ch1_sstatar1().bits()),
-            )
+            .field("ch1_sstatar1", &self.ch1_sstatar1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SSTATAR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/status0.rs b/esp32p4/src/dma/ch/status0.rs
index ed4b3f7f74..d6fed27624 100644
--- a/esp32p4/src/dma/ch/status0.rs
+++ b/esp32p4/src/dma/ch/status0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS0")
-            .field(
-                "ch1_cmpltd_blk_tfr_size",
-                &format_args!("{}", self.ch1_cmpltd_blk_tfr_size().bits()),
-            )
+            .field("ch1_cmpltd_blk_tfr_size", &self.ch1_cmpltd_blk_tfr_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS0_SPEC;
 impl crate::RegisterSpec for STATUS0_SPEC {
diff --git a/esp32p4/src/dma/ch/status1.rs b/esp32p4/src/dma/ch/status1.rs
index e87e0d8d04..4a97b2e6f3 100644
--- a/esp32p4/src/dma/ch/status1.rs
+++ b/esp32p4/src/dma/ch/status1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS1")
-            .field(
-                "ch1_data_left_in_fifo",
-                &format_args!("{}", self.ch1_data_left_in_fifo().bits()),
-            )
+            .field("ch1_data_left_in_fifo", &self.ch1_data_left_in_fifo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS1_SPEC;
 impl crate::RegisterSpec for STATUS1_SPEC {
diff --git a/esp32p4/src/dma/ch/swhsdst0.rs b/esp32p4/src/dma/ch/swhsdst0.rs
index b120fe8875..71e3779a16 100644
--- a/esp32p4/src/dma/ch/swhsdst0.rs
+++ b/esp32p4/src/dma/ch/swhsdst0.rs
@@ -41,27 +41,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWHSDST0")
-            .field(
-                "ch1_swhs_req_dst",
-                &format_args!("{}", self.ch1_swhs_req_dst().bit()),
-            )
-            .field(
-                "ch1_swhs_sglreq_dst",
-                &format_args!("{}", self.ch1_swhs_sglreq_dst().bit()),
-            )
-            .field(
-                "ch1_swhs_lst_dst",
-                &format_args!("{}", self.ch1_swhs_lst_dst().bit()),
-            )
+            .field("ch1_swhs_req_dst", &self.ch1_swhs_req_dst())
+            .field("ch1_swhs_sglreq_dst", &self.ch1_swhs_sglreq_dst())
+            .field("ch1_swhs_lst_dst", &self.ch1_swhs_lst_dst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWHSDST0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/ch/swhssrc0.rs b/esp32p4/src/dma/ch/swhssrc0.rs
index 1e06cce52f..8abb00ff16 100644
--- a/esp32p4/src/dma/ch/swhssrc0.rs
+++ b/esp32p4/src/dma/ch/swhssrc0.rs
@@ -41,27 +41,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWHSSRC0")
-            .field(
-                "ch1_swhs_req_src",
-                &format_args!("{}", self.ch1_swhs_req_src().bit()),
-            )
-            .field(
-                "ch1_swhs_sglreq_src",
-                &format_args!("{}", self.ch1_swhs_sglreq_src().bit()),
-            )
-            .field(
-                "ch1_swhs_lst_src",
-                &format_args!("{}", self.ch1_swhs_lst_src().bit()),
-            )
+            .field("ch1_swhs_req_src", &self.ch1_swhs_req_src())
+            .field("ch1_swhs_sglreq_src", &self.ch1_swhs_sglreq_src())
+            .field("ch1_swhs_lst_src", &self.ch1_swhs_lst_src())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWHSSRC0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/chen0.rs b/esp32p4/src/dma/chen0.rs
index cfdf44a696..d2413eebf8 100644
--- a/esp32p4/src/dma/chen0.rs
+++ b/esp32p4/src/dma/chen0.rs
@@ -96,23 +96,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHEN0")
-            .field("ch1_en", &format_args!("{}", self.ch1_en().bit()))
-            .field("ch2_en", &format_args!("{}", self.ch2_en().bit()))
-            .field("ch3_en", &format_args!("{}", self.ch3_en().bit()))
-            .field("ch4_en", &format_args!("{}", self.ch4_en().bit()))
-            .field("ch1_susp", &format_args!("{}", self.ch1_susp().bit()))
-            .field("ch2_susp", &format_args!("{}", self.ch2_susp().bit()))
-            .field("ch3_susp", &format_args!("{}", self.ch3_susp().bit()))
-            .field("ch4_susp", &format_args!("{}", self.ch4_susp().bit()))
+            .field("ch1_en", &self.ch1_en())
+            .field("ch2_en", &self.ch2_en())
+            .field("ch3_en", &self.ch3_en())
+            .field("ch4_en", &self.ch4_en())
+            .field("ch1_susp", &self.ch1_susp())
+            .field("ch2_susp", &self.ch2_susp())
+            .field("ch3_susp", &self.ch3_susp())
+            .field("ch4_susp", &self.ch4_susp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHEN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/chen1.rs b/esp32p4/src/dma/chen1.rs
index e86b38250e..515936ebcf 100644
--- a/esp32p4/src/dma/chen1.rs
+++ b/esp32p4/src/dma/chen1.rs
@@ -52,19 +52,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHEN1")
-            .field("ch1_abort", &format_args!("{}", self.ch1_abort().bit()))
-            .field("ch2_abort", &format_args!("{}", self.ch2_abort().bit()))
-            .field("ch3_abort", &format_args!("{}", self.ch3_abort().bit()))
-            .field("ch4_abort", &format_args!("{}", self.ch4_abort().bit()))
+            .field("ch1_abort", &self.ch1_abort())
+            .field("ch2_abort", &self.ch2_abort())
+            .field("ch3_abort", &self.ch3_abort())
+            .field("ch4_abort", &self.ch4_abort())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHEN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/commonreg_intsignal_enable0.rs b/esp32p4/src/dma/commonreg_intsignal_enable0.rs
index 6942fe1ed3..49756c9fbb 100644
--- a/esp32p4/src/dma/commonreg_intsignal_enable0.rs
+++ b/esp32p4/src/dma/commonreg_intsignal_enable0.rs
@@ -182,136 +182,79 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMMONREG_INTSIGNAL_ENABLE0")
             .field(
                 "enable_slvif_commonreg_dec_err_intsignal",
-                &format_args!("{}", self.enable_slvif_commonreg_dec_err_intsignal().bit()),
+                &self.enable_slvif_commonreg_dec_err_intsignal(),
             )
             .field(
                 "enable_slvif_commonreg_wr2ro_err_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_slvif_commonreg_wr2ro_err_intsignal().bit()
-                ),
+                &self.enable_slvif_commonreg_wr2ro_err_intsignal(),
             )
             .field(
                 "enable_slvif_commonreg_rd2wo_err_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_slvif_commonreg_rd2wo_err_intsignal().bit()
-                ),
+                &self.enable_slvif_commonreg_rd2wo_err_intsignal(),
             )
             .field(
                 "enable_slvif_commonreg_wronhold_err_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_slvif_commonreg_wronhold_err_intsignal().bit()
-                ),
+                &self.enable_slvif_commonreg_wronhold_err_intsignal(),
             )
             .field(
                 "enable_slvif_commonreg_wrparity_err_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_slvif_commonreg_wrparity_err_intsignal().bit()
-                ),
+                &self.enable_slvif_commonreg_wrparity_err_intsignal(),
             )
             .field(
                 "enable_slvif_undefinedreg_dec_err_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_slvif_undefinedreg_dec_err_intsignal().bit()
-                ),
+                &self.enable_slvif_undefinedreg_dec_err_intsignal(),
             )
             .field(
                 "enable_mxif1_rch0_eccprot_correrr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif1_rch0_eccprot_correrr_intsignal().bit()
-                ),
+                &self.enable_mxif1_rch0_eccprot_correrr_intsignal(),
             )
             .field(
                 "enable_mxif1_rch0_eccprot_uncorrerr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif1_rch0_eccprot_uncorrerr_intsignal().bit()
-                ),
+                &self.enable_mxif1_rch0_eccprot_uncorrerr_intsignal(),
             )
             .field(
                 "enable_mxif1_rch1_eccprot_correrr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif1_rch1_eccprot_correrr_intsignal().bit()
-                ),
+                &self.enable_mxif1_rch1_eccprot_correrr_intsignal(),
             )
             .field(
                 "enable_mxif1_rch1_eccprot_uncorrerr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif1_rch1_eccprot_uncorrerr_intsignal().bit()
-                ),
+                &self.enable_mxif1_rch1_eccprot_uncorrerr_intsignal(),
             )
             .field(
                 "enable_mxif1_bch_eccprot_correrr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif1_bch_eccprot_correrr_intsignal().bit()
-                ),
+                &self.enable_mxif1_bch_eccprot_correrr_intsignal(),
             )
             .field(
                 "enable_mxif1_bch_eccprot_uncorrerr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif1_bch_eccprot_uncorrerr_intsignal().bit()
-                ),
+                &self.enable_mxif1_bch_eccprot_uncorrerr_intsignal(),
             )
             .field(
                 "enable_mxif2_rch0_eccprot_correrr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif2_rch0_eccprot_correrr_intsignal().bit()
-                ),
+                &self.enable_mxif2_rch0_eccprot_correrr_intsignal(),
             )
             .field(
                 "enable_mxif2_rch0_eccprot_uncorrerr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif2_rch0_eccprot_uncorrerr_intsignal().bit()
-                ),
+                &self.enable_mxif2_rch0_eccprot_uncorrerr_intsignal(),
             )
             .field(
                 "enable_mxif2_rch1_eccprot_correrr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif2_rch1_eccprot_correrr_intsignal().bit()
-                ),
+                &self.enable_mxif2_rch1_eccprot_correrr_intsignal(),
             )
             .field(
                 "enable_mxif2_rch1_eccprot_uncorrerr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif2_rch1_eccprot_uncorrerr_intsignal().bit()
-                ),
+                &self.enable_mxif2_rch1_eccprot_uncorrerr_intsignal(),
             )
             .field(
                 "enable_mxif2_bch_eccprot_correrr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif2_bch_eccprot_correrr_intsignal().bit()
-                ),
+                &self.enable_mxif2_bch_eccprot_correrr_intsignal(),
             )
             .field(
                 "enable_mxif2_bch_eccprot_uncorrerr_intsignal",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif2_bch_eccprot_uncorrerr_intsignal().bit()
-                ),
+                &self.enable_mxif2_bch_eccprot_uncorrerr_intsignal(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMMONREG_INTSIGNAL_ENABLE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/commonreg_intstatus0.rs b/esp32p4/src/dma/commonreg_intstatus0.rs
index c637ba7be6..2d965cf59c 100644
--- a/esp32p4/src/dma/commonreg_intstatus0.rs
+++ b/esp32p4/src/dma/commonreg_intstatus0.rs
@@ -134,85 +134,79 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMMONREG_INTSTATUS0")
             .field(
                 "slvif_commonreg_dec_err_intstat",
-                &format_args!("{}", self.slvif_commonreg_dec_err_intstat().bit()),
+                &self.slvif_commonreg_dec_err_intstat(),
             )
             .field(
                 "slvif_commonreg_wr2ro_err_intstat",
-                &format_args!("{}", self.slvif_commonreg_wr2ro_err_intstat().bit()),
+                &self.slvif_commonreg_wr2ro_err_intstat(),
             )
             .field(
                 "slvif_commonreg_rd2wo_err_intstat",
-                &format_args!("{}", self.slvif_commonreg_rd2wo_err_intstat().bit()),
+                &self.slvif_commonreg_rd2wo_err_intstat(),
             )
             .field(
                 "slvif_commonreg_wronhold_err_intstat",
-                &format_args!("{}", self.slvif_commonreg_wronhold_err_intstat().bit()),
+                &self.slvif_commonreg_wronhold_err_intstat(),
             )
             .field(
                 "slvif_commonreg_wrparity_err_intstat",
-                &format_args!("{}", self.slvif_commonreg_wrparity_err_intstat().bit()),
+                &self.slvif_commonreg_wrparity_err_intstat(),
             )
             .field(
                 "slvif_undefinedreg_dec_err_intstat",
-                &format_args!("{}", self.slvif_undefinedreg_dec_err_intstat().bit()),
+                &self.slvif_undefinedreg_dec_err_intstat(),
             )
             .field(
                 "mxif1_rch0_eccprot_correrr_intstat",
-                &format_args!("{}", self.mxif1_rch0_eccprot_correrr_intstat().bit()),
+                &self.mxif1_rch0_eccprot_correrr_intstat(),
             )
             .field(
                 "mxif1_rch0_eccprot_uncorrerr_intstat",
-                &format_args!("{}", self.mxif1_rch0_eccprot_uncorrerr_intstat().bit()),
+                &self.mxif1_rch0_eccprot_uncorrerr_intstat(),
             )
             .field(
                 "mxif1_rch1_eccprot_correrr_intstat",
-                &format_args!("{}", self.mxif1_rch1_eccprot_correrr_intstat().bit()),
+                &self.mxif1_rch1_eccprot_correrr_intstat(),
             )
             .field(
                 "mxif1_rch1_eccprot_uncorrerr_intstat",
-                &format_args!("{}", self.mxif1_rch1_eccprot_uncorrerr_intstat().bit()),
+                &self.mxif1_rch1_eccprot_uncorrerr_intstat(),
             )
             .field(
                 "mxif1_bch_eccprot_correrr_intstat",
-                &format_args!("{}", self.mxif1_bch_eccprot_correrr_intstat().bit()),
+                &self.mxif1_bch_eccprot_correrr_intstat(),
             )
             .field(
                 "mxif1_bch_eccprot_uncorrerr_intstat",
-                &format_args!("{}", self.mxif1_bch_eccprot_uncorrerr_intstat().bit()),
+                &self.mxif1_bch_eccprot_uncorrerr_intstat(),
             )
             .field(
                 "mxif2_rch0_eccprot_correrr_intstat",
-                &format_args!("{}", self.mxif2_rch0_eccprot_correrr_intstat().bit()),
+                &self.mxif2_rch0_eccprot_correrr_intstat(),
             )
             .field(
                 "mxif2_rch0_eccprot_uncorrerr_intstat",
-                &format_args!("{}", self.mxif2_rch0_eccprot_uncorrerr_intstat().bit()),
+                &self.mxif2_rch0_eccprot_uncorrerr_intstat(),
             )
             .field(
                 "mxif2_rch1_eccprot_correrr_intstat",
-                &format_args!("{}", self.mxif2_rch1_eccprot_correrr_intstat().bit()),
+                &self.mxif2_rch1_eccprot_correrr_intstat(),
             )
             .field(
                 "mxif2_rch1_eccprot_uncorrerr_intstat",
-                &format_args!("{}", self.mxif2_rch1_eccprot_uncorrerr_intstat().bit()),
+                &self.mxif2_rch1_eccprot_uncorrerr_intstat(),
             )
             .field(
                 "mxif2_bch_eccprot_correrr_intstat",
-                &format_args!("{}", self.mxif2_bch_eccprot_correrr_intstat().bit()),
+                &self.mxif2_bch_eccprot_correrr_intstat(),
             )
             .field(
                 "mxif2_bch_eccprot_uncorrerr_intstat",
-                &format_args!("{}", self.mxif2_bch_eccprot_uncorrerr_intstat().bit()),
+                &self.mxif2_bch_eccprot_uncorrerr_intstat(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMMONREG_INTSTATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`commonreg_intstatus0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMMONREG_INTSTATUS0_SPEC;
 impl crate::RegisterSpec for COMMONREG_INTSTATUS0_SPEC {
diff --git a/esp32p4/src/dma/commonreg_intstatus_enable0.rs b/esp32p4/src/dma/commonreg_intstatus_enable0.rs
index c38d6642b9..d955a6afe4 100644
--- a/esp32p4/src/dma/commonreg_intstatus_enable0.rs
+++ b/esp32p4/src/dma/commonreg_intstatus_enable0.rs
@@ -182,109 +182,79 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMMONREG_INTSTATUS_ENABLE0")
             .field(
                 "enable_slvif_commonreg_dec_err_intstat",
-                &format_args!("{}", self.enable_slvif_commonreg_dec_err_intstat().bit()),
+                &self.enable_slvif_commonreg_dec_err_intstat(),
             )
             .field(
                 "enable_slvif_commonreg_wr2ro_err_intstat",
-                &format_args!("{}", self.enable_slvif_commonreg_wr2ro_err_intstat().bit()),
+                &self.enable_slvif_commonreg_wr2ro_err_intstat(),
             )
             .field(
                 "enable_slvif_commonreg_rd2wo_err_intstat",
-                &format_args!("{}", self.enable_slvif_commonreg_rd2wo_err_intstat().bit()),
+                &self.enable_slvif_commonreg_rd2wo_err_intstat(),
             )
             .field(
                 "enable_slvif_commonreg_wronhold_err_intstat",
-                &format_args!(
-                    "{}",
-                    self.enable_slvif_commonreg_wronhold_err_intstat().bit()
-                ),
+                &self.enable_slvif_commonreg_wronhold_err_intstat(),
             )
             .field(
                 "enable_slvif_commonreg_wrparity_err_intstat",
-                &format_args!(
-                    "{}",
-                    self.enable_slvif_commonreg_wrparity_err_intstat().bit()
-                ),
+                &self.enable_slvif_commonreg_wrparity_err_intstat(),
             )
             .field(
                 "enable_slvif_undefinedreg_dec_err_intstat",
-                &format_args!("{}", self.enable_slvif_undefinedreg_dec_err_intstat().bit()),
+                &self.enable_slvif_undefinedreg_dec_err_intstat(),
             )
             .field(
                 "enable_mxif1_rch0_eccprot_correrr_intstat",
-                &format_args!("{}", self.enable_mxif1_rch0_eccprot_correrr_intstat().bit()),
+                &self.enable_mxif1_rch0_eccprot_correrr_intstat(),
             )
             .field(
                 "enable_mxif1_rch0_eccprot_uncorrerr_intstat",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif1_rch0_eccprot_uncorrerr_intstat().bit()
-                ),
+                &self.enable_mxif1_rch0_eccprot_uncorrerr_intstat(),
             )
             .field(
                 "enable_mxif1_rch1_eccprot_correrr_intstat",
-                &format_args!("{}", self.enable_mxif1_rch1_eccprot_correrr_intstat().bit()),
+                &self.enable_mxif1_rch1_eccprot_correrr_intstat(),
             )
             .field(
                 "enable_mxif1_rch1_eccprot_uncorrerr_intstat",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif1_rch1_eccprot_uncorrerr_intstat().bit()
-                ),
+                &self.enable_mxif1_rch1_eccprot_uncorrerr_intstat(),
             )
             .field(
                 "enable_mxif1_bch_eccprot_correrr_intstat",
-                &format_args!("{}", self.enable_mxif1_bch_eccprot_correrr_intstat().bit()),
+                &self.enable_mxif1_bch_eccprot_correrr_intstat(),
             )
             .field(
                 "enable_mxif1_bch_eccprot_uncorrerr_intstat",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif1_bch_eccprot_uncorrerr_intstat().bit()
-                ),
+                &self.enable_mxif1_bch_eccprot_uncorrerr_intstat(),
             )
             .field(
                 "enable_mxif2_rch0_eccprot_correrr_intstat",
-                &format_args!("{}", self.enable_mxif2_rch0_eccprot_correrr_intstat().bit()),
+                &self.enable_mxif2_rch0_eccprot_correrr_intstat(),
             )
             .field(
                 "enable_mxif2_rch0_eccprot_uncorrerr_intstat",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif2_rch0_eccprot_uncorrerr_intstat().bit()
-                ),
+                &self.enable_mxif2_rch0_eccprot_uncorrerr_intstat(),
             )
             .field(
                 "enable_mxif2_rch1_eccprot_correrr_intstat",
-                &format_args!("{}", self.enable_mxif2_rch1_eccprot_correrr_intstat().bit()),
+                &self.enable_mxif2_rch1_eccprot_correrr_intstat(),
             )
             .field(
                 "enable_mxif2_rch1_eccprot_uncorrerr_intstat",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif2_rch1_eccprot_uncorrerr_intstat().bit()
-                ),
+                &self.enable_mxif2_rch1_eccprot_uncorrerr_intstat(),
             )
             .field(
                 "enable_mxif2_bch_eccprot_correrr_intstat",
-                &format_args!("{}", self.enable_mxif2_bch_eccprot_correrr_intstat().bit()),
+                &self.enable_mxif2_bch_eccprot_correrr_intstat(),
             )
             .field(
                 "enable_mxif2_bch_eccprot_uncorrerr_intstat",
-                &format_args!(
-                    "{}",
-                    self.enable_mxif2_bch_eccprot_uncorrerr_intstat().bit()
-                ),
+                &self.enable_mxif2_bch_eccprot_uncorrerr_intstat(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMMONREG_INTSTATUS_ENABLE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/compver0.rs b/esp32p4/src/dma/compver0.rs
index 68cf90c3f6..b468931fd6 100644
--- a/esp32p4/src/dma/compver0.rs
+++ b/esp32p4/src/dma/compver0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMPVER0")
-            .field(
-                "dmac_compver",
-                &format_args!("{}", self.dmac_compver().bits()),
-            )
+            .field("dmac_compver", &self.dmac_compver())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMPVER0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`compver0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMPVER0_SPEC;
 impl crate::RegisterSpec for COMPVER0_SPEC {
diff --git a/esp32p4/src/dma/id0.rs b/esp32p4/src/dma/id0.rs
index 3d78404abe..4155d1e61d 100644
--- a/esp32p4/src/dma/id0.rs
+++ b/esp32p4/src/dma/id0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ID0")
-            .field("dmac_id", &format_args!("{}", self.dmac_id().bits()))
+            .field("dmac_id", &self.dmac_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ID0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ID0_SPEC;
 impl crate::RegisterSpec for ID0_SPEC {
diff --git a/esp32p4/src/dma/intstatus0.rs b/esp32p4/src/dma/intstatus0.rs
index 578fd18ae5..ed4fedb7b6 100644
--- a/esp32p4/src/dma/intstatus0.rs
+++ b/esp32p4/src/dma/intstatus0.rs
@@ -41,23 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTSTATUS0")
-            .field("ch1_intstat", &format_args!("{}", self.ch1_intstat().bit()))
-            .field("ch2_intstat", &format_args!("{}", self.ch2_intstat().bit()))
-            .field("ch3_intstat", &format_args!("{}", self.ch3_intstat().bit()))
-            .field("ch4_intstat", &format_args!("{}", self.ch4_intstat().bit()))
-            .field(
-                "commonreg_intstat",
-                &format_args!("{}", self.commonreg_intstat().bit()),
-            )
+            .field("ch1_intstat", &self.ch1_intstat())
+            .field("ch2_intstat", &self.ch2_intstat())
+            .field("ch3_intstat", &self.ch3_intstat())
+            .field("ch4_intstat", &self.ch4_intstat())
+            .field("commonreg_intstat", &self.commonreg_intstat())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTSTATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intstatus0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTSTATUS0_SPEC;
 impl crate::RegisterSpec for INTSTATUS0_SPEC {
diff --git a/esp32p4/src/dma/lowpower_cfg0.rs b/esp32p4/src/dma/lowpower_cfg0.rs
index 9ca854519a..8a037c0fd0 100644
--- a/esp32p4/src/dma/lowpower_cfg0.rs
+++ b/esp32p4/src/dma/lowpower_cfg0.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOWPOWER_CFG0")
-            .field("gbl_cslp_en", &format_args!("{}", self.gbl_cslp_en().bit()))
-            .field(
-                "chnl_cslp_en",
-                &format_args!("{}", self.chnl_cslp_en().bit()),
-            )
-            .field(
-                "sbiu_cslp_en",
-                &format_args!("{}", self.sbiu_cslp_en().bit()),
-            )
-            .field(
-                "mxif_cslp_en",
-                &format_args!("{}", self.mxif_cslp_en().bit()),
-            )
+            .field("gbl_cslp_en", &self.gbl_cslp_en())
+            .field("chnl_cslp_en", &self.chnl_cslp_en())
+            .field("sbiu_cslp_en", &self.sbiu_cslp_en())
+            .field("mxif_cslp_en", &self.mxif_cslp_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOWPOWER_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/lowpower_cfg1.rs b/esp32p4/src/dma/lowpower_cfg1.rs
index b952b34c89..423242f817 100644
--- a/esp32p4/src/dma/lowpower_cfg1.rs
+++ b/esp32p4/src/dma/lowpower_cfg1.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOWPOWER_CFG1")
-            .field("glch_lpdly", &format_args!("{}", self.glch_lpdly().bits()))
-            .field("sbiu_lpdly", &format_args!("{}", self.sbiu_lpdly().bits()))
-            .field("mxif_lpdly", &format_args!("{}", self.mxif_lpdly().bits()))
+            .field("glch_lpdly", &self.glch_lpdly())
+            .field("sbiu_lpdly", &self.sbiu_lpdly())
+            .field("mxif_lpdly", &self.mxif_lpdly())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOWPOWER_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/dma/reset0.rs b/esp32p4/src/dma/reset0.rs
index e292f13164..c04113ab02 100644
--- a/esp32p4/src/dma/reset0.rs
+++ b/esp32p4/src/dma/reset0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET0")
-            .field("dmac_rst", &format_args!("{}", self.dmac_rst().bit()))
+            .field("dmac_rst", &self.dmac_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/ds/box_mem.rs b/esp32p4/src/ds/box_mem.rs
index cbc5e04146..af6085c630 100644
--- a/esp32p4/src/ds/box_mem.rs
+++ b/esp32p4/src/ds/box_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BOX_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores BOX\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`box_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`box_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BOX_MEM_SPEC;
diff --git a/esp32p4/src/ds/date.rs b/esp32p4/src/ds/date.rs
index 0b73492be1..97e7b03565 100644
--- a/esp32p4/src/ds/date.rs
+++ b/esp32p4/src/ds/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/ds/iv_mem.rs b/esp32p4/src/ds/iv_mem.rs
index 3f93dc26b7..5bef1d4a62 100644
--- a/esp32p4/src/ds/iv_mem.rs
+++ b/esp32p4/src/ds/iv_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IV_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores IV\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iv_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iv_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IV_MEM_SPEC;
diff --git a/esp32p4/src/ds/m_mem.rs b/esp32p4/src/ds/m_mem.rs
index feb455544d..34f49f49a5 100644
--- a/esp32p4/src/ds/m_mem.rs
+++ b/esp32p4/src/ds/m_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct M_MEM_SPEC;
diff --git a/esp32p4/src/ds/query_busy.rs b/esp32p4/src/ds/query_busy.rs
index 28c895caf6..ab7489a518 100644
--- a/esp32p4/src/ds/query_busy.rs
+++ b/esp32p4/src/ds/query_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_BUSY")
-            .field("query_busy", &format_args!("{}", self.query_busy().bit()))
+            .field("query_busy", &self.query_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DS query busy register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_BUSY_SPEC;
 impl crate::RegisterSpec for QUERY_BUSY_SPEC {
diff --git a/esp32p4/src/ds/query_check.rs b/esp32p4/src/ds/query_check.rs
index 278370e20f..e1d1c02fe7 100644
--- a/esp32p4/src/ds/query_check.rs
+++ b/esp32p4/src/ds/query_check.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_CHECK")
-            .field("md_error", &format_args!("{}", self.md_error().bit()))
-            .field("padding_bad", &format_args!("{}", self.padding_bad().bit()))
+            .field("md_error", &self.md_error())
+            .field("padding_bad", &self.padding_bad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_CHECK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DS query check result register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_check::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_CHECK_SPEC;
 impl crate::RegisterSpec for QUERY_CHECK_SPEC {
diff --git a/esp32p4/src/ds/query_key_wrong.rs b/esp32p4/src/ds/query_key_wrong.rs
index 30a1e7aae4..7ce4bf99a0 100644
--- a/esp32p4/src/ds/query_key_wrong.rs
+++ b/esp32p4/src/ds/query_key_wrong.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_KEY_WRONG")
-            .field(
-                "query_key_wrong",
-                &format_args!("{}", self.query_key_wrong().bits()),
-            )
+            .field("query_key_wrong", &self.query_key_wrong())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_KEY_WRONG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DS query key-wrong counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_key_wrong::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_KEY_WRONG_SPEC;
 impl crate::RegisterSpec for QUERY_KEY_WRONG_SPEC {
diff --git a/esp32p4/src/ds/rb_mem.rs b/esp32p4/src/ds/rb_mem.rs
index 601da234a3..c7e0a211be 100644
--- a/esp32p4/src/ds/rb_mem.rs
+++ b/esp32p4/src/ds/rb_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RB_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores Rb\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rb_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rb_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RB_MEM_SPEC;
diff --git a/esp32p4/src/ds/x_mem.rs b/esp32p4/src/ds/x_mem.rs
index b018ad10ba..5cfb1f6eb6 100644
--- a/esp32p4/src/ds/x_mem.rs
+++ b/esp32p4/src/ds/x_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<X_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores X\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`x_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`x_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct X_MEM_SPEC;
diff --git a/esp32p4/src/ds/y_mem.rs b/esp32p4/src/ds/y_mem.rs
index 00ad225968..3376d35f4e 100644
--- a/esp32p4/src/ds/y_mem.rs
+++ b/esp32p4/src/ds/y_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Y_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores Y\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Y_MEM_SPEC;
diff --git a/esp32p4/src/ds/z_mem.rs b/esp32p4/src/ds/z_mem.rs
index de03c7e5de..978b2c0d66 100644
--- a/esp32p4/src/ds/z_mem.rs
+++ b/esp32p4/src/ds/z_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Z_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory that stores Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Z_MEM_SPEC;
diff --git a/esp32p4/src/ecc/k_mem.rs b/esp32p4/src/ecc/k_mem.rs
index 0931b81173..8e55d12095 100644
--- a/esp32p4/src/ecc/k_mem.rs
+++ b/esp32p4/src/ecc/k_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<K_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores k.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`k_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`k_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct K_MEM_SPEC;
diff --git a/esp32p4/src/ecc/mult_conf.rs b/esp32p4/src/ecc/mult_conf.rs
index a41e749735..af55ceccbc 100644
--- a/esp32p4/src/ecc/mult_conf.rs
+++ b/esp32p4/src/ecc/mult_conf.rs
@@ -80,32 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_CONF")
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("key_length", &format_args!("{}", self.key_length().bit()))
-            .field("mod_base", &format_args!("{}", self.mod_base().bit()))
-            .field("work_mode", &format_args!("{}", self.work_mode().bits()))
-            .field(
-                "security_mode",
-                &format_args!("{}", self.security_mode().bit()),
-            )
-            .field(
-                "verification_result",
-                &format_args!("{}", self.verification_result().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "mem_clock_gate_force_on",
-                &format_args!("{}", self.mem_clock_gate_force_on().bit()),
-            )
+            .field("start", &self.start())
+            .field("key_length", &self.key_length())
+            .field("mod_base", &self.mod_base())
+            .field("work_mode", &self.work_mode())
+            .field("security_mode", &self.security_mode())
+            .field("verification_result", &self.verification_result())
+            .field("clk_en", &self.clk_en())
+            .field("mem_clock_gate_force_on", &self.mem_clock_gate_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done."]
     #[inline(always)]
diff --git a/esp32p4/src/ecc/mult_date.rs b/esp32p4/src/ecc/mult_date.rs
index 04e7a519bd..90bc3f92e5 100644
--- a/esp32p4/src/ecc/mult_date.rs
+++ b/esp32p4/src/ecc/mult_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - ECC mult version control register"]
     #[inline(always)]
diff --git a/esp32p4/src/ecc/mult_int_ena.rs b/esp32p4/src/ecc/mult_int_ena.rs
index 0a756a4618..e98f881175 100644
--- a/esp32p4/src/ecc/mult_int_ena.rs
+++ b/esp32p4/src/ecc/mult_int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_INT_ENA")
-            .field("calc_done", &format_args!("{}", self.calc_done().bit()))
+            .field("calc_done", &self.calc_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the ecc_calc_done_int interrupt"]
     #[inline(always)]
diff --git a/esp32p4/src/ecc/mult_int_raw.rs b/esp32p4/src/ecc/mult_int_raw.rs
index ad5e442a59..0a76f6a144 100644
--- a/esp32p4/src/ecc/mult_int_raw.rs
+++ b/esp32p4/src/ecc/mult_int_raw.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_INT_RAW")
-            .field("calc_done", &format_args!("{}", self.calc_done().bit()))
+            .field("calc_done", &self.calc_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ECC interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MULT_INT_RAW_SPEC;
 impl crate::RegisterSpec for MULT_INT_RAW_SPEC {
diff --git a/esp32p4/src/ecc/mult_int_st.rs b/esp32p4/src/ecc/mult_int_st.rs
index 9fa4c84f14..599cde021a 100644
--- a/esp32p4/src/ecc/mult_int_st.rs
+++ b/esp32p4/src/ecc/mult_int_st.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MULT_INT_ST")
-            .field("calc_done", &format_args!("{}", self.calc_done().bit()))
+            .field("calc_done", &self.calc_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MULT_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ECC interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mult_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MULT_INT_ST_SPEC;
 impl crate::RegisterSpec for MULT_INT_ST_SPEC {
diff --git a/esp32p4/src/ecc/px_mem.rs b/esp32p4/src/ecc/px_mem.rs
index 3a8e843f61..3a24d84d16 100644
--- a/esp32p4/src/ecc/px_mem.rs
+++ b/esp32p4/src/ecc/px_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PX_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores Px.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`px_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`px_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PX_MEM_SPEC;
diff --git a/esp32p4/src/ecc/py_mem.rs b/esp32p4/src/ecc/py_mem.rs
index 8129141315..e5d383ac34 100644
--- a/esp32p4/src/ecc/py_mem.rs
+++ b/esp32p4/src/ecc/py_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PY_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores Py.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`py_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`py_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PY_MEM_SPEC;
diff --git a/esp32p4/src/ecdsa/clk.rs b/esp32p4/src/ecdsa/clk.rs
index 1e5dbe16da..cd143ae80e 100644
--- a/esp32p4/src/ecdsa/clk.rs
+++ b/esp32p4/src/ecdsa/clk.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK")
-            .field(
-                "gate_force_on",
-                &format_args!("{}", self.gate_force_on().bit()),
-            )
+            .field("gate_force_on", &self.gate_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to force on register clock gate."]
     #[inline(always)]
diff --git a/esp32p4/src/ecdsa/conf.rs b/esp32p4/src/ecdsa/conf.rs
index 3124b10e86..7b25a583be 100644
--- a/esp32p4/src/ecdsa/conf.rs
+++ b/esp32p4/src/ecdsa/conf.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("work_mode", &format_args!("{}", self.work_mode().bits()))
-            .field("ecc_curve", &format_args!("{}", self.ecc_curve().bit()))
-            .field(
-                "software_set_k",
-                &format_args!("{}", self.software_set_k().bit()),
-            )
-            .field(
-                "software_set_z",
-                &format_args!("{}", self.software_set_z().bit()),
-            )
-            .field(
-                "deterministic_k",
-                &format_args!("{}", self.deterministic_k().bit()),
-            )
-            .field(
-                "deterministic_loop",
-                &format_args!("{}", self.deterministic_loop().bits()),
-            )
+            .field("work_mode", &self.work_mode())
+            .field("ecc_curve", &self.ecc_curve())
+            .field("software_set_k", &self.software_set_k())
+            .field("software_set_z", &self.software_set_z())
+            .field("deterministic_k", &self.deterministic_k())
+            .field("deterministic_loop", &self.deterministic_loop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature Generate Mode. 2: Export Public Key Mode. 3: invalid."]
     #[inline(always)]
diff --git a/esp32p4/src/ecdsa/date.rs b/esp32p4/src/ecdsa/date.rs
index e9b5fb3813..9a6d4c29a9 100644
--- a/esp32p4/src/ecdsa/date.rs
+++ b/esp32p4/src/ecdsa/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/ecdsa/int_ena.rs b/esp32p4/src/ecdsa/int_ena.rs
index 0e2730bf23..8b48b767f4 100644
--- a/esp32p4/src/ecdsa/int_ena.rs
+++ b/esp32p4/src/ecdsa/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("calc_done", &format_args!("{}", self.calc_done().bit()))
-            .field("sha_release", &format_args!("{}", self.sha_release().bit()))
+            .field("calc_done", &self.calc_done())
+            .field("sha_release", &self.sha_release())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the ecdsa_calc_done_int interrupt"]
     #[inline(always)]
diff --git a/esp32p4/src/ecdsa/int_raw.rs b/esp32p4/src/ecdsa/int_raw.rs
index befd3d48a9..82e94f3a3f 100644
--- a/esp32p4/src/ecdsa/int_raw.rs
+++ b/esp32p4/src/ecdsa/int_raw.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("calc_done", &format_args!("{}", self.calc_done().bit()))
-            .field("sha_release", &format_args!("{}", self.sha_release().bit()))
+            .field("calc_done", &self.calc_done())
+            .field("sha_release", &self.sha_release())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ECDSA interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32p4/src/ecdsa/int_st.rs b/esp32p4/src/ecdsa/int_st.rs
index ae821e5680..fee27af412 100644
--- a/esp32p4/src/ecdsa/int_st.rs
+++ b/esp32p4/src/ecdsa/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("calc_done", &format_args!("{}", self.calc_done().bit()))
-            .field("sha_release", &format_args!("{}", self.sha_release().bit()))
+            .field("calc_done", &self.calc_done())
+            .field("sha_release", &self.sha_release())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ECDSA interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/ecdsa/message_mem.rs b/esp32p4/src/ecdsa/message_mem.rs
index c2b19e3ced..c75678753c 100644
--- a/esp32p4/src/ecdsa/message_mem.rs
+++ b/esp32p4/src/ecdsa/message_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MESSAGE_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores message.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`message_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`message_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MESSAGE_MEM_SPEC;
diff --git a/esp32p4/src/ecdsa/qax_mem.rs b/esp32p4/src/ecdsa/qax_mem.rs
index f4305dcbee..0cb44d7dbd 100644
--- a/esp32p4/src/ecdsa/qax_mem.rs
+++ b/esp32p4/src/ecdsa/qax_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QAX_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores x coordinates of QA or software written k.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`qax_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`qax_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QAX_MEM_SPEC;
diff --git a/esp32p4/src/ecdsa/qay_mem.rs b/esp32p4/src/ecdsa/qay_mem.rs
index 8b79891172..8c016660ef 100644
--- a/esp32p4/src/ecdsa/qay_mem.rs
+++ b/esp32p4/src/ecdsa/qay_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QAY_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores y coordinates of QA.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`qay_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`qay_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QAY_MEM_SPEC;
diff --git a/esp32p4/src/ecdsa/r_mem.rs b/esp32p4/src/ecdsa/r_mem.rs
index 89c8361f44..fca71e53b9 100644
--- a/esp32p4/src/ecdsa/r_mem.rs
+++ b/esp32p4/src/ecdsa/r_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<R_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores r.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct R_MEM_SPEC;
diff --git a/esp32p4/src/ecdsa/result.rs b/esp32p4/src/ecdsa/result.rs
index bc552d3d2c..c98042cdac 100644
--- a/esp32p4/src/ecdsa/result.rs
+++ b/esp32p4/src/ecdsa/result.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESULT")
-            .field(
-                "operation_result",
-                &format_args!("{}", self.operation_result().bit()),
-            )
-            .field(
-                "k_value_warning",
-                &format_args!("{}", self.k_value_warning().bit()),
-            )
+            .field("operation_result", &self.operation_result())
+            .field("k_value_warning", &self.k_value_warning())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESULT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ECDSA result register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`result::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESULT_SPEC;
 impl crate::RegisterSpec for RESULT_SPEC {
diff --git a/esp32p4/src/ecdsa/s_mem.rs b/esp32p4/src/ecdsa/s_mem.rs
index 0105d2e0a5..ee9f310465 100644
--- a/esp32p4/src/ecdsa/s_mem.rs
+++ b/esp32p4/src/ecdsa/s_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<S_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores s.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S_MEM_SPEC;
diff --git a/esp32p4/src/ecdsa/sha_busy.rs b/esp32p4/src/ecdsa/sha_busy.rs
index b6099b1393..f728a46ee7 100644
--- a/esp32p4/src/ecdsa/sha_busy.rs
+++ b/esp32p4/src/ecdsa/sha_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA_BUSY")
-            .field("sha_busy", &format_args!("{}", self.sha_busy().bit()))
+            .field("sha_busy", &self.sha_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ECDSA status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sha_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SHA_BUSY_SPEC;
 impl crate::RegisterSpec for SHA_BUSY_SPEC {
diff --git a/esp32p4/src/ecdsa/sha_mode.rs b/esp32p4/src/ecdsa/sha_mode.rs
index 37e9993dba..d91400439a 100644
--- a/esp32p4/src/ecdsa/sha_mode.rs
+++ b/esp32p4/src/ecdsa/sha_mode.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA_MODE")
-            .field("sha_mode", &format_args!("{}", self.sha_mode().bits()))
+            .field("sha_mode", &self.sha_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. Others: invalid."]
     #[inline(always)]
diff --git a/esp32p4/src/ecdsa/state.rs b/esp32p4/src/ecdsa/state.rs
index 3d74211fcc..d1be89ee21 100644
--- a/esp32p4/src/ecdsa/state.rs
+++ b/esp32p4/src/ecdsa/state.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("STATE")
-            .field("busy", &format_args!("{}", self.busy().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("STATE").field("busy", &self.busy()).finish()
     }
 }
 #[doc = "ECDSA status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32p4/src/ecdsa/z_mem.rs b/esp32p4/src/ecdsa/z_mem.rs
index 1b4ca9ec8d..90788813c0 100644
--- a/esp32p4/src/ecdsa/z_mem.rs
+++ b/esp32p4/src/ecdsa/z_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Z_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores software written z.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Z_MEM_SPEC;
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup1_w1.rs b/esp32p4/src/efuse/apb2otp_blk0_backup1_w1.rs
index 34395f94ed..eaae491d23 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup1_w1.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup1_w1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP1_W1")
             .field(
                 "apb2otp_block0_backup1_w1",
-                &format_args!("{}", self.apb2otp_block0_backup1_w1().bits()),
+                &self.apb2otp_block0_backup1_w1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP1_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup1_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP1_W1_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP1_W1_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup1_w2.rs b/esp32p4/src/efuse/apb2otp_blk0_backup1_w2.rs
index e4a8cf9bb3..e5c3e4feed 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup1_w2.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup1_w2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP1_W2")
             .field(
                 "apb2otp_block0_backup1_w2",
-                &format_args!("{}", self.apb2otp_block0_backup1_w2().bits()),
+                &self.apb2otp_block0_backup1_w2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP1_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup1_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP1_W2_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP1_W2_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup1_w3.rs b/esp32p4/src/efuse/apb2otp_blk0_backup1_w3.rs
index ec5a88f06c..437e69f580 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup1_w3.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup1_w3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP1_W3")
             .field(
                 "apb2otp_block0_backup1_w3",
-                &format_args!("{}", self.apb2otp_block0_backup1_w3().bits()),
+                &self.apb2otp_block0_backup1_w3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP1_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup1_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP1_W3_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP1_W3_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup1_w4.rs b/esp32p4/src/efuse/apb2otp_blk0_backup1_w4.rs
index a183163621..7d2f311f0f 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup1_w4.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup1_w4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP1_W4")
             .field(
                 "apb2otp_block0_backup1_w4",
-                &format_args!("{}", self.apb2otp_block0_backup1_w4().bits()),
+                &self.apb2otp_block0_backup1_w4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP1_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup1_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP1_W4_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP1_W4_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup1_w5.rs b/esp32p4/src/efuse/apb2otp_blk0_backup1_w5.rs
index 3e5f94e9c5..383f297083 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup1_w5.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup1_w5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP1_W5")
             .field(
                 "apb2otp_block0_backup1_w5",
-                &format_args!("{}", self.apb2otp_block0_backup1_w5().bits()),
+                &self.apb2otp_block0_backup1_w5(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP1_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup1_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP1_W5_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP1_W5_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup2_w1.rs b/esp32p4/src/efuse/apb2otp_blk0_backup2_w1.rs
index 7ed07c19b1..c0506841da 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup2_w1.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup2_w1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP2_W1")
             .field(
                 "apb2otp_block0_backup2_w1",
-                &format_args!("{}", self.apb2otp_block0_backup2_w1().bits()),
+                &self.apb2otp_block0_backup2_w1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP2_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup2_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP2_W1_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP2_W1_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup2_w2.rs b/esp32p4/src/efuse/apb2otp_blk0_backup2_w2.rs
index a2eaf37a12..719458a01c 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup2_w2.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup2_w2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP2_W2")
             .field(
                 "apb2otp_block0_backup2_w2",
-                &format_args!("{}", self.apb2otp_block0_backup2_w2().bits()),
+                &self.apb2otp_block0_backup2_w2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP2_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup2_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP2_W2_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP2_W2_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup2_w3.rs b/esp32p4/src/efuse/apb2otp_blk0_backup2_w3.rs
index fa27d694d9..800f1f4399 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup2_w3.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup2_w3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP2_W3")
             .field(
                 "apb2otp_block0_backup2_w3",
-                &format_args!("{}", self.apb2otp_block0_backup2_w3().bits()),
+                &self.apb2otp_block0_backup2_w3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP2_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup2_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP2_W3_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP2_W3_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup2_w4.rs b/esp32p4/src/efuse/apb2otp_blk0_backup2_w4.rs
index 7f7ad4f76c..50da59a023 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup2_w4.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup2_w4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP2_W4")
             .field(
                 "apb2otp_block0_backup2_w4",
-                &format_args!("{}", self.apb2otp_block0_backup2_w4().bits()),
+                &self.apb2otp_block0_backup2_w4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP2_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup2_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP2_W4_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP2_W4_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup2_w5.rs b/esp32p4/src/efuse/apb2otp_blk0_backup2_w5.rs
index 8bf2907fdc..63097c85ee 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup2_w5.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup2_w5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP2_W5")
             .field(
                 "apb2otp_block0_backup2_w5",
-                &format_args!("{}", self.apb2otp_block0_backup2_w5().bits()),
+                &self.apb2otp_block0_backup2_w5(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP2_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup2_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP2_W5_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP2_W5_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup3_w1.rs b/esp32p4/src/efuse/apb2otp_blk0_backup3_w1.rs
index 18223cd66e..646529b45c 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup3_w1.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup3_w1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP3_W1")
             .field(
                 "apb2otp_block0_backup3_w1",
-                &format_args!("{}", self.apb2otp_block0_backup3_w1().bits()),
+                &self.apb2otp_block0_backup3_w1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP3_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register12.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup3_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP3_W1_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP3_W1_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup3_w2.rs b/esp32p4/src/efuse/apb2otp_blk0_backup3_w2.rs
index 3b9c62bfff..a7bacc67b4 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup3_w2.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup3_w2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP3_W2")
             .field(
                 "apb2otp_block0_backup3_w2",
-                &format_args!("{}", self.apb2otp_block0_backup3_w2().bits()),
+                &self.apb2otp_block0_backup3_w2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP3_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register13.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup3_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP3_W2_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP3_W2_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup3_w3.rs b/esp32p4/src/efuse/apb2otp_blk0_backup3_w3.rs
index 9289716a40..64dd542f9c 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup3_w3.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup3_w3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP3_W3")
             .field(
                 "apb2otp_block0_backup3_w3",
-                &format_args!("{}", self.apb2otp_block0_backup3_w3().bits()),
+                &self.apb2otp_block0_backup3_w3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP3_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register14.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup3_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP3_W3_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP3_W3_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup3_w4.rs b/esp32p4/src/efuse/apb2otp_blk0_backup3_w4.rs
index 57b3097758..a49fc987d6 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup3_w4.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup3_w4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP3_W4")
             .field(
                 "apb2otp_block0_backup3_w4",
-                &format_args!("{}", self.apb2otp_block0_backup3_w4().bits()),
+                &self.apb2otp_block0_backup3_w4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP3_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register15.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup3_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP3_W4_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP3_W4_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup3_w5.rs b/esp32p4/src/efuse/apb2otp_blk0_backup3_w5.rs
index 934cee9467..a4a63aa148 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup3_w5.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup3_w5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP3_W5")
             .field(
                 "apb2otp_block0_backup3_w5",
-                &format_args!("{}", self.apb2otp_block0_backup3_w5().bits()),
+                &self.apb2otp_block0_backup3_w5(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP3_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register16.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup3_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP3_W5_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP3_W5_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup4_w1.rs b/esp32p4/src/efuse/apb2otp_blk0_backup4_w1.rs
index 0c04691ec9..b83e367dee 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup4_w1.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup4_w1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP4_W1")
             .field(
                 "apb2otp_block0_backup4_w1",
-                &format_args!("{}", self.apb2otp_block0_backup4_w1().bits()),
+                &self.apb2otp_block0_backup4_w1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP4_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register17.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup4_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP4_W1_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP4_W1_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup4_w2.rs b/esp32p4/src/efuse/apb2otp_blk0_backup4_w2.rs
index 498bd533f4..b108291b6c 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup4_w2.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup4_w2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP4_W2")
             .field(
                 "apb2otp_block0_backup4_w2",
-                &format_args!("{}", self.apb2otp_block0_backup4_w2().bits()),
+                &self.apb2otp_block0_backup4_w2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP4_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register18.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup4_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP4_W2_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP4_W2_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup4_w3.rs b/esp32p4/src/efuse/apb2otp_blk0_backup4_w3.rs
index bf6545fb67..396db08f93 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup4_w3.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup4_w3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP4_W3")
             .field(
                 "apb2otp_block0_backup4_w3",
-                &format_args!("{}", self.apb2otp_block0_backup4_w3().bits()),
+                &self.apb2otp_block0_backup4_w3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP4_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register19.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup4_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP4_W3_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP4_W3_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup4_w4.rs b/esp32p4/src/efuse/apb2otp_blk0_backup4_w4.rs
index e3e2a6ce47..80dc4d30d6 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup4_w4.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup4_w4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP4_W4")
             .field(
                 "apb2otp_block0_backup4_w4",
-                &format_args!("{}", self.apb2otp_block0_backup4_w4().bits()),
+                &self.apb2otp_block0_backup4_w4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP4_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register20.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup4_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP4_W4_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP4_W4_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk0_backup4_w5.rs b/esp32p4/src/efuse/apb2otp_blk0_backup4_w5.rs
index cb064e7c76..a1bcfd4ab0 100644
--- a/esp32p4/src/efuse/apb2otp_blk0_backup4_w5.rs
+++ b/esp32p4/src/efuse/apb2otp_blk0_backup4_w5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB2OTP_BLK0_BACKUP4_W5")
             .field(
                 "apb2otp_block0_backup4_w5",
-                &format_args!("{}", self.apb2otp_block0_backup4_w5().bits()),
+                &self.apb2otp_block0_backup4_w5(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK0_BACKUP4_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register21.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk0_backup4_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK0_BACKUP4_W5_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK0_BACKUP4_W5_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk10_w1.rs b/esp32p4/src/efuse/apb2otp_blk10_w1.rs
index 0927d11067..aff01e7dba 100644
--- a/esp32p4/src/efuse/apb2otp_blk10_w1.rs
+++ b/esp32p4/src/efuse/apb2otp_blk10_w1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK10_W1")
-            .field(
-                "apb2otp_block10_w1",
-                &format_args!("{}", self.apb2otp_block10_w1().bits()),
-            )
+            .field("apb2otp_block10_w1", &self.apb2otp_block10_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK10_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block10 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK10_W1_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK10_W1_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk10_w10.rs b/esp32p4/src/efuse/apb2otp_blk10_w10.rs
index 37b6bb1fe1..c7eb0efe8b 100644
--- a/esp32p4/src/efuse/apb2otp_blk10_w10.rs
+++ b/esp32p4/src/efuse/apb2otp_blk10_w10.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK10_W10")
-            .field(
-                "apb2otp_block19_w10",
-                &format_args!("{}", self.apb2otp_block19_w10().bits()),
-            )
+            .field("apb2otp_block19_w10", &self.apb2otp_block19_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK10_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block10 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK10_W10_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK10_W10_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk10_w11.rs b/esp32p4/src/efuse/apb2otp_blk10_w11.rs
index e152c04eb1..de453a5fcc 100644
--- a/esp32p4/src/efuse/apb2otp_blk10_w11.rs
+++ b/esp32p4/src/efuse/apb2otp_blk10_w11.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK10_W11")
-            .field(
-                "apb2otp_block10_w11",
-                &format_args!("{}", self.apb2otp_block10_w11().bits()),
-            )
+            .field("apb2otp_block10_w11", &self.apb2otp_block10_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK10_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block10 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK10_W11_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK10_W11_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk10_w2.rs b/esp32p4/src/efuse/apb2otp_blk10_w2.rs
index 59ecf4d917..101645aa5d 100644
--- a/esp32p4/src/efuse/apb2otp_blk10_w2.rs
+++ b/esp32p4/src/efuse/apb2otp_blk10_w2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK10_W2")
-            .field(
-                "apb2otp_block10_w2",
-                &format_args!("{}", self.apb2otp_block10_w2().bits()),
-            )
+            .field("apb2otp_block10_w2", &self.apb2otp_block10_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK10_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block10 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK10_W2_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK10_W2_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk10_w3.rs b/esp32p4/src/efuse/apb2otp_blk10_w3.rs
index 41559bb4f9..d425c61400 100644
--- a/esp32p4/src/efuse/apb2otp_blk10_w3.rs
+++ b/esp32p4/src/efuse/apb2otp_blk10_w3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK10_W3")
-            .field(
-                "apb2otp_block10_w3",
-                &format_args!("{}", self.apb2otp_block10_w3().bits()),
-            )
+            .field("apb2otp_block10_w3", &self.apb2otp_block10_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK10_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block10 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK10_W3_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK10_W3_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk10_w4.rs b/esp32p4/src/efuse/apb2otp_blk10_w4.rs
index 044308b41a..36484fc214 100644
--- a/esp32p4/src/efuse/apb2otp_blk10_w4.rs
+++ b/esp32p4/src/efuse/apb2otp_blk10_w4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK10_W4")
-            .field(
-                "apb2otp_block10_w4",
-                &format_args!("{}", self.apb2otp_block10_w4().bits()),
-            )
+            .field("apb2otp_block10_w4", &self.apb2otp_block10_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK10_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block10 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK10_W4_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK10_W4_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk10_w5.rs b/esp32p4/src/efuse/apb2otp_blk10_w5.rs
index 85573c5b9a..ea3611673d 100644
--- a/esp32p4/src/efuse/apb2otp_blk10_w5.rs
+++ b/esp32p4/src/efuse/apb2otp_blk10_w5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK10_W5")
-            .field(
-                "apb2otp_block10_w5",
-                &format_args!("{}", self.apb2otp_block10_w5().bits()),
-            )
+            .field("apb2otp_block10_w5", &self.apb2otp_block10_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK10_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block10 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK10_W5_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK10_W5_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk10_w6.rs b/esp32p4/src/efuse/apb2otp_blk10_w6.rs
index c1a40cfcff..e8cfe7f269 100644
--- a/esp32p4/src/efuse/apb2otp_blk10_w6.rs
+++ b/esp32p4/src/efuse/apb2otp_blk10_w6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK10_W6")
-            .field(
-                "apb2otp_block10_w6",
-                &format_args!("{}", self.apb2otp_block10_w6().bits()),
-            )
+            .field("apb2otp_block10_w6", &self.apb2otp_block10_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK10_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block10 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK10_W6_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK10_W6_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk10_w7.rs b/esp32p4/src/efuse/apb2otp_blk10_w7.rs
index ce33e1b860..6382d0392d 100644
--- a/esp32p4/src/efuse/apb2otp_blk10_w7.rs
+++ b/esp32p4/src/efuse/apb2otp_blk10_w7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK10_W7")
-            .field(
-                "apb2otp_block10_w7",
-                &format_args!("{}", self.apb2otp_block10_w7().bits()),
-            )
+            .field("apb2otp_block10_w7", &self.apb2otp_block10_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK10_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block10 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK10_W7_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK10_W7_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk10_w8.rs b/esp32p4/src/efuse/apb2otp_blk10_w8.rs
index 8a2bb947ea..35bd112f6f 100644
--- a/esp32p4/src/efuse/apb2otp_blk10_w8.rs
+++ b/esp32p4/src/efuse/apb2otp_blk10_w8.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK10_W8")
-            .field(
-                "apb2otp_block10_w8",
-                &format_args!("{}", self.apb2otp_block10_w8().bits()),
-            )
+            .field("apb2otp_block10_w8", &self.apb2otp_block10_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK10_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block10 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK10_W8_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK10_W8_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk10_w9.rs b/esp32p4/src/efuse/apb2otp_blk10_w9.rs
index 4f55c2c1fd..dbd6a3fcfd 100644
--- a/esp32p4/src/efuse/apb2otp_blk10_w9.rs
+++ b/esp32p4/src/efuse/apb2otp_blk10_w9.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK10_W9")
-            .field(
-                "apb2otp_block10_w9",
-                &format_args!("{}", self.apb2otp_block10_w9().bits()),
-            )
+            .field("apb2otp_block10_w9", &self.apb2otp_block10_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK10_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block10 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk10_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK10_W9_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK10_W9_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk1_w1.rs b/esp32p4/src/efuse/apb2otp_blk1_w1.rs
index 4df835df2d..b9b508fe3a 100644
--- a/esp32p4/src/efuse/apb2otp_blk1_w1.rs
+++ b/esp32p4/src/efuse/apb2otp_blk1_w1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK1_W1")
-            .field(
-                "apb2otp_block1_w1",
-                &format_args!("{}", self.apb2otp_block1_w1().bits()),
-            )
+            .field("apb2otp_block1_w1", &self.apb2otp_block1_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK1_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block1 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK1_W1_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK1_W1_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk1_w2.rs b/esp32p4/src/efuse/apb2otp_blk1_w2.rs
index 210ed09593..2cd7e6ad2f 100644
--- a/esp32p4/src/efuse/apb2otp_blk1_w2.rs
+++ b/esp32p4/src/efuse/apb2otp_blk1_w2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK1_W2")
-            .field(
-                "apb2otp_block1_w2",
-                &format_args!("{}", self.apb2otp_block1_w2().bits()),
-            )
+            .field("apb2otp_block1_w2", &self.apb2otp_block1_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK1_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block1 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK1_W2_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK1_W2_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk1_w3.rs b/esp32p4/src/efuse/apb2otp_blk1_w3.rs
index 0cb519220a..1f8e2c6fcc 100644
--- a/esp32p4/src/efuse/apb2otp_blk1_w3.rs
+++ b/esp32p4/src/efuse/apb2otp_blk1_w3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK1_W3")
-            .field(
-                "apb2otp_block1_w3",
-                &format_args!("{}", self.apb2otp_block1_w3().bits()),
-            )
+            .field("apb2otp_block1_w3", &self.apb2otp_block1_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK1_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block1 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK1_W3_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK1_W3_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk1_w4.rs b/esp32p4/src/efuse/apb2otp_blk1_w4.rs
index d12a64fb81..60db6dcd6c 100644
--- a/esp32p4/src/efuse/apb2otp_blk1_w4.rs
+++ b/esp32p4/src/efuse/apb2otp_blk1_w4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK1_W4")
-            .field(
-                "apb2otp_block1_w4",
-                &format_args!("{}", self.apb2otp_block1_w4().bits()),
-            )
+            .field("apb2otp_block1_w4", &self.apb2otp_block1_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK1_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block1 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK1_W4_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK1_W4_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk1_w5.rs b/esp32p4/src/efuse/apb2otp_blk1_w5.rs
index 1f096dc5b8..394ccdce4f 100644
--- a/esp32p4/src/efuse/apb2otp_blk1_w5.rs
+++ b/esp32p4/src/efuse/apb2otp_blk1_w5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK1_W5")
-            .field(
-                "apb2otp_block1_w5",
-                &format_args!("{}", self.apb2otp_block1_w5().bits()),
-            )
+            .field("apb2otp_block1_w5", &self.apb2otp_block1_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK1_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block1 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK1_W5_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK1_W5_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk1_w6.rs b/esp32p4/src/efuse/apb2otp_blk1_w6.rs
index 46c8d7f37a..43e51f6073 100644
--- a/esp32p4/src/efuse/apb2otp_blk1_w6.rs
+++ b/esp32p4/src/efuse/apb2otp_blk1_w6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK1_W6")
-            .field(
-                "apb2otp_block1_w6",
-                &format_args!("{}", self.apb2otp_block1_w6().bits()),
-            )
+            .field("apb2otp_block1_w6", &self.apb2otp_block1_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK1_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block1 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK1_W6_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK1_W6_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk1_w7.rs b/esp32p4/src/efuse/apb2otp_blk1_w7.rs
index 60c3b92caf..f33ae68bcd 100644
--- a/esp32p4/src/efuse/apb2otp_blk1_w7.rs
+++ b/esp32p4/src/efuse/apb2otp_blk1_w7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK1_W7")
-            .field(
-                "apb2otp_block1_w7",
-                &format_args!("{}", self.apb2otp_block1_w7().bits()),
-            )
+            .field("apb2otp_block1_w7", &self.apb2otp_block1_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK1_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block1 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK1_W7_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK1_W7_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk1_w8.rs b/esp32p4/src/efuse/apb2otp_blk1_w8.rs
index 50b05d7dc2..71e739a96a 100644
--- a/esp32p4/src/efuse/apb2otp_blk1_w8.rs
+++ b/esp32p4/src/efuse/apb2otp_blk1_w8.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK1_W8")
-            .field(
-                "apb2otp_block1_w8",
-                &format_args!("{}", self.apb2otp_block1_w8().bits()),
-            )
+            .field("apb2otp_block1_w8", &self.apb2otp_block1_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK1_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block1 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK1_W8_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK1_W8_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk1_w9.rs b/esp32p4/src/efuse/apb2otp_blk1_w9.rs
index caab5023ea..191351555d 100644
--- a/esp32p4/src/efuse/apb2otp_blk1_w9.rs
+++ b/esp32p4/src/efuse/apb2otp_blk1_w9.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK1_W9")
-            .field(
-                "apb2otp_block1_w9",
-                &format_args!("{}", self.apb2otp_block1_w9().bits()),
-            )
+            .field("apb2otp_block1_w9", &self.apb2otp_block1_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK1_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block1 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk1_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK1_W9_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK1_W9_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk2_w1.rs b/esp32p4/src/efuse/apb2otp_blk2_w1.rs
index 01de721e66..024ba7ec94 100644
--- a/esp32p4/src/efuse/apb2otp_blk2_w1.rs
+++ b/esp32p4/src/efuse/apb2otp_blk2_w1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK2_W1")
-            .field(
-                "apb2otp_block2_w1",
-                &format_args!("{}", self.apb2otp_block2_w1().bits()),
-            )
+            .field("apb2otp_block2_w1", &self.apb2otp_block2_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK2_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block2 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK2_W1_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK2_W1_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk2_w10.rs b/esp32p4/src/efuse/apb2otp_blk2_w10.rs
index 85f332f16d..e8b53bdadc 100644
--- a/esp32p4/src/efuse/apb2otp_blk2_w10.rs
+++ b/esp32p4/src/efuse/apb2otp_blk2_w10.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK2_W10")
-            .field(
-                "apb2otp_block2_w10",
-                &format_args!("{}", self.apb2otp_block2_w10().bits()),
-            )
+            .field("apb2otp_block2_w10", &self.apb2otp_block2_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK2_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block2 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK2_W10_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK2_W10_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk2_w11.rs b/esp32p4/src/efuse/apb2otp_blk2_w11.rs
index b1f5b524dc..319bff334a 100644
--- a/esp32p4/src/efuse/apb2otp_blk2_w11.rs
+++ b/esp32p4/src/efuse/apb2otp_blk2_w11.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK2_W11")
-            .field(
-                "apb2otp_block2_w11",
-                &format_args!("{}", self.apb2otp_block2_w11().bits()),
-            )
+            .field("apb2otp_block2_w11", &self.apb2otp_block2_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK2_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block2 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK2_W11_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK2_W11_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk2_w2.rs b/esp32p4/src/efuse/apb2otp_blk2_w2.rs
index d8d2e2d28c..8ff06d0ea8 100644
--- a/esp32p4/src/efuse/apb2otp_blk2_w2.rs
+++ b/esp32p4/src/efuse/apb2otp_blk2_w2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK2_W2")
-            .field(
-                "apb2otp_block2_w2",
-                &format_args!("{}", self.apb2otp_block2_w2().bits()),
-            )
+            .field("apb2otp_block2_w2", &self.apb2otp_block2_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK2_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block2 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK2_W2_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK2_W2_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk2_w3.rs b/esp32p4/src/efuse/apb2otp_blk2_w3.rs
index 25b5201781..12c0cf5a4e 100644
--- a/esp32p4/src/efuse/apb2otp_blk2_w3.rs
+++ b/esp32p4/src/efuse/apb2otp_blk2_w3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK2_W3")
-            .field(
-                "apb2otp_block2_w3",
-                &format_args!("{}", self.apb2otp_block2_w3().bits()),
-            )
+            .field("apb2otp_block2_w3", &self.apb2otp_block2_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK2_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block2 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK2_W3_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK2_W3_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk2_w4.rs b/esp32p4/src/efuse/apb2otp_blk2_w4.rs
index a37f2257a0..0c24b3bb6f 100644
--- a/esp32p4/src/efuse/apb2otp_blk2_w4.rs
+++ b/esp32p4/src/efuse/apb2otp_blk2_w4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK2_W4")
-            .field(
-                "apb2otp_block2_w4",
-                &format_args!("{}", self.apb2otp_block2_w4().bits()),
-            )
+            .field("apb2otp_block2_w4", &self.apb2otp_block2_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK2_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block2 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK2_W4_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK2_W4_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk2_w5.rs b/esp32p4/src/efuse/apb2otp_blk2_w5.rs
index 6c517c9150..6ffff2d73c 100644
--- a/esp32p4/src/efuse/apb2otp_blk2_w5.rs
+++ b/esp32p4/src/efuse/apb2otp_blk2_w5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK2_W5")
-            .field(
-                "apb2otp_block2_w5",
-                &format_args!("{}", self.apb2otp_block2_w5().bits()),
-            )
+            .field("apb2otp_block2_w5", &self.apb2otp_block2_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK2_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block2 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK2_W5_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK2_W5_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk2_w6.rs b/esp32p4/src/efuse/apb2otp_blk2_w6.rs
index 236b38ef14..e3c6512794 100644
--- a/esp32p4/src/efuse/apb2otp_blk2_w6.rs
+++ b/esp32p4/src/efuse/apb2otp_blk2_w6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK2_W6")
-            .field(
-                "apb2otp_block2_w6",
-                &format_args!("{}", self.apb2otp_block2_w6().bits()),
-            )
+            .field("apb2otp_block2_w6", &self.apb2otp_block2_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK2_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block2 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK2_W6_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK2_W6_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk2_w7.rs b/esp32p4/src/efuse/apb2otp_blk2_w7.rs
index 279afddc6d..0f2d88253a 100644
--- a/esp32p4/src/efuse/apb2otp_blk2_w7.rs
+++ b/esp32p4/src/efuse/apb2otp_blk2_w7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK2_W7")
-            .field(
-                "apb2otp_block2_w7",
-                &format_args!("{}", self.apb2otp_block2_w7().bits()),
-            )
+            .field("apb2otp_block2_w7", &self.apb2otp_block2_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK2_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block2 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK2_W7_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK2_W7_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk2_w8.rs b/esp32p4/src/efuse/apb2otp_blk2_w8.rs
index 3899cb33f0..10edd0a128 100644
--- a/esp32p4/src/efuse/apb2otp_blk2_w8.rs
+++ b/esp32p4/src/efuse/apb2otp_blk2_w8.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK2_W8")
-            .field(
-                "apb2otp_block2_w8",
-                &format_args!("{}", self.apb2otp_block2_w8().bits()),
-            )
+            .field("apb2otp_block2_w8", &self.apb2otp_block2_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK2_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block2 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK2_W8_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK2_W8_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk2_w9.rs b/esp32p4/src/efuse/apb2otp_blk2_w9.rs
index 0a980ed971..31a8610953 100644
--- a/esp32p4/src/efuse/apb2otp_blk2_w9.rs
+++ b/esp32p4/src/efuse/apb2otp_blk2_w9.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK2_W9")
-            .field(
-                "apb2otp_block2_w9",
-                &format_args!("{}", self.apb2otp_block2_w9().bits()),
-            )
+            .field("apb2otp_block2_w9", &self.apb2otp_block2_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK2_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block2 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk2_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK2_W9_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK2_W9_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk3_w1.rs b/esp32p4/src/efuse/apb2otp_blk3_w1.rs
index 5ec7a0a1e2..df74661a1e 100644
--- a/esp32p4/src/efuse/apb2otp_blk3_w1.rs
+++ b/esp32p4/src/efuse/apb2otp_blk3_w1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK3_W1")
-            .field(
-                "apb2otp_block3_w1",
-                &format_args!("{}", self.apb2otp_block3_w1().bits()),
-            )
+            .field("apb2otp_block3_w1", &self.apb2otp_block3_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK3_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block3 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK3_W1_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK3_W1_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk3_w10.rs b/esp32p4/src/efuse/apb2otp_blk3_w10.rs
index 1c8b631bb7..e6501fe1b0 100644
--- a/esp32p4/src/efuse/apb2otp_blk3_w10.rs
+++ b/esp32p4/src/efuse/apb2otp_blk3_w10.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK3_W10")
-            .field(
-                "apb2otp_block3_w10",
-                &format_args!("{}", self.apb2otp_block3_w10().bits()),
-            )
+            .field("apb2otp_block3_w10", &self.apb2otp_block3_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK3_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block3 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK3_W10_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK3_W10_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk3_w11.rs b/esp32p4/src/efuse/apb2otp_blk3_w11.rs
index 45c017e066..cc66e47913 100644
--- a/esp32p4/src/efuse/apb2otp_blk3_w11.rs
+++ b/esp32p4/src/efuse/apb2otp_blk3_w11.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK3_W11")
-            .field(
-                "apb2otp_block3_w11",
-                &format_args!("{}", self.apb2otp_block3_w11().bits()),
-            )
+            .field("apb2otp_block3_w11", &self.apb2otp_block3_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK3_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block3 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK3_W11_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK3_W11_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk3_w2.rs b/esp32p4/src/efuse/apb2otp_blk3_w2.rs
index 06601241fb..ea28a48615 100644
--- a/esp32p4/src/efuse/apb2otp_blk3_w2.rs
+++ b/esp32p4/src/efuse/apb2otp_blk3_w2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK3_W2")
-            .field(
-                "apb2otp_block3_w2",
-                &format_args!("{}", self.apb2otp_block3_w2().bits()),
-            )
+            .field("apb2otp_block3_w2", &self.apb2otp_block3_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK3_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block3 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK3_W2_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK3_W2_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk3_w3.rs b/esp32p4/src/efuse/apb2otp_blk3_w3.rs
index 54b8a7e99b..80a44a57df 100644
--- a/esp32p4/src/efuse/apb2otp_blk3_w3.rs
+++ b/esp32p4/src/efuse/apb2otp_blk3_w3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK3_W3")
-            .field(
-                "apb2otp_block3_w3",
-                &format_args!("{}", self.apb2otp_block3_w3().bits()),
-            )
+            .field("apb2otp_block3_w3", &self.apb2otp_block3_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK3_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block3 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK3_W3_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK3_W3_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk3_w4.rs b/esp32p4/src/efuse/apb2otp_blk3_w4.rs
index 66c51e350e..e58ceb8c2c 100644
--- a/esp32p4/src/efuse/apb2otp_blk3_w4.rs
+++ b/esp32p4/src/efuse/apb2otp_blk3_w4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK3_W4")
-            .field(
-                "apb2otp_block3_w4",
-                &format_args!("{}", self.apb2otp_block3_w4().bits()),
-            )
+            .field("apb2otp_block3_w4", &self.apb2otp_block3_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK3_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block3 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK3_W4_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK3_W4_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk3_w5.rs b/esp32p4/src/efuse/apb2otp_blk3_w5.rs
index aefa6e2c49..70a45886aa 100644
--- a/esp32p4/src/efuse/apb2otp_blk3_w5.rs
+++ b/esp32p4/src/efuse/apb2otp_blk3_w5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK3_W5")
-            .field(
-                "apb2otp_block3_w5",
-                &format_args!("{}", self.apb2otp_block3_w5().bits()),
-            )
+            .field("apb2otp_block3_w5", &self.apb2otp_block3_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK3_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block3 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK3_W5_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK3_W5_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk3_w6.rs b/esp32p4/src/efuse/apb2otp_blk3_w6.rs
index 1c80244aa1..780cf5ae08 100644
--- a/esp32p4/src/efuse/apb2otp_blk3_w6.rs
+++ b/esp32p4/src/efuse/apb2otp_blk3_w6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK3_W6")
-            .field(
-                "apb2otp_block3_w6",
-                &format_args!("{}", self.apb2otp_block3_w6().bits()),
-            )
+            .field("apb2otp_block3_w6", &self.apb2otp_block3_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK3_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block3 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK3_W6_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK3_W6_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk3_w7.rs b/esp32p4/src/efuse/apb2otp_blk3_w7.rs
index 086a49dcbe..236093185c 100644
--- a/esp32p4/src/efuse/apb2otp_blk3_w7.rs
+++ b/esp32p4/src/efuse/apb2otp_blk3_w7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK3_W7")
-            .field(
-                "apb2otp_block3_w7",
-                &format_args!("{}", self.apb2otp_block3_w7().bits()),
-            )
+            .field("apb2otp_block3_w7", &self.apb2otp_block3_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK3_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block3 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK3_W7_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK3_W7_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk3_w8.rs b/esp32p4/src/efuse/apb2otp_blk3_w8.rs
index 238c3d8cdb..aca611bf6c 100644
--- a/esp32p4/src/efuse/apb2otp_blk3_w8.rs
+++ b/esp32p4/src/efuse/apb2otp_blk3_w8.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK3_W8")
-            .field(
-                "apb2otp_block3_w8",
-                &format_args!("{}", self.apb2otp_block3_w8().bits()),
-            )
+            .field("apb2otp_block3_w8", &self.apb2otp_block3_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK3_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block3 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK3_W8_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK3_W8_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk3_w9.rs b/esp32p4/src/efuse/apb2otp_blk3_w9.rs
index b73a92878e..c9fd867068 100644
--- a/esp32p4/src/efuse/apb2otp_blk3_w9.rs
+++ b/esp32p4/src/efuse/apb2otp_blk3_w9.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK3_W9")
-            .field(
-                "apb2otp_block3_w9",
-                &format_args!("{}", self.apb2otp_block3_w9().bits()),
-            )
+            .field("apb2otp_block3_w9", &self.apb2otp_block3_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK3_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block3 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk3_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK3_W9_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK3_W9_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk4_w1.rs b/esp32p4/src/efuse/apb2otp_blk4_w1.rs
index deec42965a..a3a65f5a11 100644
--- a/esp32p4/src/efuse/apb2otp_blk4_w1.rs
+++ b/esp32p4/src/efuse/apb2otp_blk4_w1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK4_W1")
-            .field(
-                "apb2otp_block4_w1",
-                &format_args!("{}", self.apb2otp_block4_w1().bits()),
-            )
+            .field("apb2otp_block4_w1", &self.apb2otp_block4_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK4_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block4 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK4_W1_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK4_W1_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk4_w10.rs b/esp32p4/src/efuse/apb2otp_blk4_w10.rs
index d31bcd8608..66f5cd9cf6 100644
--- a/esp32p4/src/efuse/apb2otp_blk4_w10.rs
+++ b/esp32p4/src/efuse/apb2otp_blk4_w10.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK4_W10")
-            .field(
-                "apb2otp_block4_w10",
-                &format_args!("{}", self.apb2otp_block4_w10().bits()),
-            )
+            .field("apb2otp_block4_w10", &self.apb2otp_block4_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK4_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block4 data registe10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK4_W10_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK4_W10_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk4_w11.rs b/esp32p4/src/efuse/apb2otp_blk4_w11.rs
index 2a1c381560..43190a973d 100644
--- a/esp32p4/src/efuse/apb2otp_blk4_w11.rs
+++ b/esp32p4/src/efuse/apb2otp_blk4_w11.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK4_W11")
-            .field(
-                "apb2otp_block4_w11",
-                &format_args!("{}", self.apb2otp_block4_w11().bits()),
-            )
+            .field("apb2otp_block4_w11", &self.apb2otp_block4_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK4_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block4 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK4_W11_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK4_W11_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk4_w2.rs b/esp32p4/src/efuse/apb2otp_blk4_w2.rs
index 5644539a34..8f950da86b 100644
--- a/esp32p4/src/efuse/apb2otp_blk4_w2.rs
+++ b/esp32p4/src/efuse/apb2otp_blk4_w2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK4_W2")
-            .field(
-                "apb2otp_block4_w2",
-                &format_args!("{}", self.apb2otp_block4_w2().bits()),
-            )
+            .field("apb2otp_block4_w2", &self.apb2otp_block4_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK4_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block4 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK4_W2_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK4_W2_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk4_w3.rs b/esp32p4/src/efuse/apb2otp_blk4_w3.rs
index fde154b698..4ea23ead72 100644
--- a/esp32p4/src/efuse/apb2otp_blk4_w3.rs
+++ b/esp32p4/src/efuse/apb2otp_blk4_w3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK4_W3")
-            .field(
-                "apb2otp_block4_w3",
-                &format_args!("{}", self.apb2otp_block4_w3().bits()),
-            )
+            .field("apb2otp_block4_w3", &self.apb2otp_block4_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK4_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block4 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK4_W3_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK4_W3_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk4_w4.rs b/esp32p4/src/efuse/apb2otp_blk4_w4.rs
index 9628502aa5..2d6dd20fd4 100644
--- a/esp32p4/src/efuse/apb2otp_blk4_w4.rs
+++ b/esp32p4/src/efuse/apb2otp_blk4_w4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK4_W4")
-            .field(
-                "apb2otp_block4_w4",
-                &format_args!("{}", self.apb2otp_block4_w4().bits()),
-            )
+            .field("apb2otp_block4_w4", &self.apb2otp_block4_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK4_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block4 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK4_W4_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK4_W4_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk4_w5.rs b/esp32p4/src/efuse/apb2otp_blk4_w5.rs
index 4c4cc69ce6..4da9926249 100644
--- a/esp32p4/src/efuse/apb2otp_blk4_w5.rs
+++ b/esp32p4/src/efuse/apb2otp_blk4_w5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK4_W5")
-            .field(
-                "apb2otp_block4_w5",
-                &format_args!("{}", self.apb2otp_block4_w5().bits()),
-            )
+            .field("apb2otp_block4_w5", &self.apb2otp_block4_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK4_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block4 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK4_W5_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK4_W5_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk4_w6.rs b/esp32p4/src/efuse/apb2otp_blk4_w6.rs
index 5a719e1b72..ba7ef3c41b 100644
--- a/esp32p4/src/efuse/apb2otp_blk4_w6.rs
+++ b/esp32p4/src/efuse/apb2otp_blk4_w6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK4_W6")
-            .field(
-                "apb2otp_block4_w6",
-                &format_args!("{}", self.apb2otp_block4_w6().bits()),
-            )
+            .field("apb2otp_block4_w6", &self.apb2otp_block4_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK4_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block4 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK4_W6_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK4_W6_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk4_w7.rs b/esp32p4/src/efuse/apb2otp_blk4_w7.rs
index 7bc3a37a07..6486dbc979 100644
--- a/esp32p4/src/efuse/apb2otp_blk4_w7.rs
+++ b/esp32p4/src/efuse/apb2otp_blk4_w7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK4_W7")
-            .field(
-                "apb2otp_block4_w7",
-                &format_args!("{}", self.apb2otp_block4_w7().bits()),
-            )
+            .field("apb2otp_block4_w7", &self.apb2otp_block4_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK4_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block4 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK4_W7_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK4_W7_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk4_w8.rs b/esp32p4/src/efuse/apb2otp_blk4_w8.rs
index ea9d7958df..6f4ee3e4bd 100644
--- a/esp32p4/src/efuse/apb2otp_blk4_w8.rs
+++ b/esp32p4/src/efuse/apb2otp_blk4_w8.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK4_W8")
-            .field(
-                "apb2otp_block4_w8",
-                &format_args!("{}", self.apb2otp_block4_w8().bits()),
-            )
+            .field("apb2otp_block4_w8", &self.apb2otp_block4_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK4_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block4 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK4_W8_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK4_W8_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk4_w9.rs b/esp32p4/src/efuse/apb2otp_blk4_w9.rs
index 361e205389..644a09d15c 100644
--- a/esp32p4/src/efuse/apb2otp_blk4_w9.rs
+++ b/esp32p4/src/efuse/apb2otp_blk4_w9.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK4_W9")
-            .field(
-                "apb2otp_block4_w9",
-                &format_args!("{}", self.apb2otp_block4_w9().bits()),
-            )
+            .field("apb2otp_block4_w9", &self.apb2otp_block4_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK4_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block4 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk4_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK4_W9_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK4_W9_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk5_w1.rs b/esp32p4/src/efuse/apb2otp_blk5_w1.rs
index 3868883ea0..40bb72a79f 100644
--- a/esp32p4/src/efuse/apb2otp_blk5_w1.rs
+++ b/esp32p4/src/efuse/apb2otp_blk5_w1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK5_W1")
-            .field(
-                "apb2otp_block5_w1",
-                &format_args!("{}", self.apb2otp_block5_w1().bits()),
-            )
+            .field("apb2otp_block5_w1", &self.apb2otp_block5_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK5_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block5 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK5_W1_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK5_W1_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk5_w10.rs b/esp32p4/src/efuse/apb2otp_blk5_w10.rs
index ee62297a1c..72ebb85fb4 100644
--- a/esp32p4/src/efuse/apb2otp_blk5_w10.rs
+++ b/esp32p4/src/efuse/apb2otp_blk5_w10.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK5_W10")
-            .field(
-                "apb2otp_block5_w10",
-                &format_args!("{}", self.apb2otp_block5_w10().bits()),
-            )
+            .field("apb2otp_block5_w10", &self.apb2otp_block5_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK5_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block5 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK5_W10_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK5_W10_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk5_w11.rs b/esp32p4/src/efuse/apb2otp_blk5_w11.rs
index 8d24621157..bc9e255f1f 100644
--- a/esp32p4/src/efuse/apb2otp_blk5_w11.rs
+++ b/esp32p4/src/efuse/apb2otp_blk5_w11.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK5_W11")
-            .field(
-                "apb2otp_block5_w11",
-                &format_args!("{}", self.apb2otp_block5_w11().bits()),
-            )
+            .field("apb2otp_block5_w11", &self.apb2otp_block5_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK5_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block5 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK5_W11_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK5_W11_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk5_w2.rs b/esp32p4/src/efuse/apb2otp_blk5_w2.rs
index 0551befb03..b66572f105 100644
--- a/esp32p4/src/efuse/apb2otp_blk5_w2.rs
+++ b/esp32p4/src/efuse/apb2otp_blk5_w2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK5_W2")
-            .field(
-                "apb2otp_block5_w2",
-                &format_args!("{}", self.apb2otp_block5_w2().bits()),
-            )
+            .field("apb2otp_block5_w2", &self.apb2otp_block5_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK5_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block5 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK5_W2_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK5_W2_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk5_w3.rs b/esp32p4/src/efuse/apb2otp_blk5_w3.rs
index fabda42f13..35e786d410 100644
--- a/esp32p4/src/efuse/apb2otp_blk5_w3.rs
+++ b/esp32p4/src/efuse/apb2otp_blk5_w3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK5_W3")
-            .field(
-                "apb2otp_block5_w3",
-                &format_args!("{}", self.apb2otp_block5_w3().bits()),
-            )
+            .field("apb2otp_block5_w3", &self.apb2otp_block5_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK5_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block5 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK5_W3_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK5_W3_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk5_w4.rs b/esp32p4/src/efuse/apb2otp_blk5_w4.rs
index f9dcd83cbd..91d1912b7f 100644
--- a/esp32p4/src/efuse/apb2otp_blk5_w4.rs
+++ b/esp32p4/src/efuse/apb2otp_blk5_w4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK5_W4")
-            .field(
-                "apb2otp_block5_w4",
-                &format_args!("{}", self.apb2otp_block5_w4().bits()),
-            )
+            .field("apb2otp_block5_w4", &self.apb2otp_block5_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK5_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block5 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK5_W4_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK5_W4_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk5_w5.rs b/esp32p4/src/efuse/apb2otp_blk5_w5.rs
index 758a69689f..71175c9e6c 100644
--- a/esp32p4/src/efuse/apb2otp_blk5_w5.rs
+++ b/esp32p4/src/efuse/apb2otp_blk5_w5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK5_W5")
-            .field(
-                "apb2otp_block5_w5",
-                &format_args!("{}", self.apb2otp_block5_w5().bits()),
-            )
+            .field("apb2otp_block5_w5", &self.apb2otp_block5_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK5_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block5 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK5_W5_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK5_W5_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk5_w6.rs b/esp32p4/src/efuse/apb2otp_blk5_w6.rs
index 0e6182117f..33dc64a3d5 100644
--- a/esp32p4/src/efuse/apb2otp_blk5_w6.rs
+++ b/esp32p4/src/efuse/apb2otp_blk5_w6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK5_W6")
-            .field(
-                "apb2otp_block5_w6",
-                &format_args!("{}", self.apb2otp_block5_w6().bits()),
-            )
+            .field("apb2otp_block5_w6", &self.apb2otp_block5_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK5_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block5 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK5_W6_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK5_W6_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk5_w7.rs b/esp32p4/src/efuse/apb2otp_blk5_w7.rs
index 5696f2be5b..25f3c54017 100644
--- a/esp32p4/src/efuse/apb2otp_blk5_w7.rs
+++ b/esp32p4/src/efuse/apb2otp_blk5_w7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK5_W7")
-            .field(
-                "apb2otp_block5_w7",
-                &format_args!("{}", self.apb2otp_block5_w7().bits()),
-            )
+            .field("apb2otp_block5_w7", &self.apb2otp_block5_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK5_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block5 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK5_W7_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK5_W7_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk5_w8.rs b/esp32p4/src/efuse/apb2otp_blk5_w8.rs
index 5fc69841d3..08d2f43f50 100644
--- a/esp32p4/src/efuse/apb2otp_blk5_w8.rs
+++ b/esp32p4/src/efuse/apb2otp_blk5_w8.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK5_W8")
-            .field(
-                "apb2otp_block5_w8",
-                &format_args!("{}", self.apb2otp_block5_w8().bits()),
-            )
+            .field("apb2otp_block5_w8", &self.apb2otp_block5_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK5_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block5 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK5_W8_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK5_W8_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk5_w9.rs b/esp32p4/src/efuse/apb2otp_blk5_w9.rs
index a7ee68c70e..5c41595f57 100644
--- a/esp32p4/src/efuse/apb2otp_blk5_w9.rs
+++ b/esp32p4/src/efuse/apb2otp_blk5_w9.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK5_W9")
-            .field(
-                "apb2otp_block5_w9",
-                &format_args!("{}", self.apb2otp_block5_w9().bits()),
-            )
+            .field("apb2otp_block5_w9", &self.apb2otp_block5_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK5_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block5 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk5_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK5_W9_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK5_W9_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk6_w1.rs b/esp32p4/src/efuse/apb2otp_blk6_w1.rs
index 1f9a2b6163..963036311f 100644
--- a/esp32p4/src/efuse/apb2otp_blk6_w1.rs
+++ b/esp32p4/src/efuse/apb2otp_blk6_w1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK6_W1")
-            .field(
-                "apb2otp_block6_w1",
-                &format_args!("{}", self.apb2otp_block6_w1().bits()),
-            )
+            .field("apb2otp_block6_w1", &self.apb2otp_block6_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK6_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block6 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK6_W1_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK6_W1_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk6_w10.rs b/esp32p4/src/efuse/apb2otp_blk6_w10.rs
index 89590df8b7..0661520b1b 100644
--- a/esp32p4/src/efuse/apb2otp_blk6_w10.rs
+++ b/esp32p4/src/efuse/apb2otp_blk6_w10.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK6_W10")
-            .field(
-                "apb2otp_block6_w10",
-                &format_args!("{}", self.apb2otp_block6_w10().bits()),
-            )
+            .field("apb2otp_block6_w10", &self.apb2otp_block6_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK6_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block6 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK6_W10_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK6_W10_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk6_w11.rs b/esp32p4/src/efuse/apb2otp_blk6_w11.rs
index 42254d9c1a..71008f00cf 100644
--- a/esp32p4/src/efuse/apb2otp_blk6_w11.rs
+++ b/esp32p4/src/efuse/apb2otp_blk6_w11.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK6_W11")
-            .field(
-                "apb2otp_block6_w11",
-                &format_args!("{}", self.apb2otp_block6_w11().bits()),
-            )
+            .field("apb2otp_block6_w11", &self.apb2otp_block6_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK6_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block6 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK6_W11_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK6_W11_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk6_w2.rs b/esp32p4/src/efuse/apb2otp_blk6_w2.rs
index f6a93e08da..6b74910730 100644
--- a/esp32p4/src/efuse/apb2otp_blk6_w2.rs
+++ b/esp32p4/src/efuse/apb2otp_blk6_w2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK6_W2")
-            .field(
-                "apb2otp_block6_w2",
-                &format_args!("{}", self.apb2otp_block6_w2().bits()),
-            )
+            .field("apb2otp_block6_w2", &self.apb2otp_block6_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK6_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block6 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK6_W2_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK6_W2_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk6_w3.rs b/esp32p4/src/efuse/apb2otp_blk6_w3.rs
index bf3a20cd2f..015cf1a160 100644
--- a/esp32p4/src/efuse/apb2otp_blk6_w3.rs
+++ b/esp32p4/src/efuse/apb2otp_blk6_w3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK6_W3")
-            .field(
-                "apb2otp_block6_w3",
-                &format_args!("{}", self.apb2otp_block6_w3().bits()),
-            )
+            .field("apb2otp_block6_w3", &self.apb2otp_block6_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK6_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block6 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK6_W3_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK6_W3_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk6_w4.rs b/esp32p4/src/efuse/apb2otp_blk6_w4.rs
index cc1463ca8d..cb810769a6 100644
--- a/esp32p4/src/efuse/apb2otp_blk6_w4.rs
+++ b/esp32p4/src/efuse/apb2otp_blk6_w4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK6_W4")
-            .field(
-                "apb2otp_block6_w4",
-                &format_args!("{}", self.apb2otp_block6_w4().bits()),
-            )
+            .field("apb2otp_block6_w4", &self.apb2otp_block6_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK6_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block6 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK6_W4_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK6_W4_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk6_w5.rs b/esp32p4/src/efuse/apb2otp_blk6_w5.rs
index bf7f6df066..6c931c72b5 100644
--- a/esp32p4/src/efuse/apb2otp_blk6_w5.rs
+++ b/esp32p4/src/efuse/apb2otp_blk6_w5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK6_W5")
-            .field(
-                "apb2otp_block6_w5",
-                &format_args!("{}", self.apb2otp_block6_w5().bits()),
-            )
+            .field("apb2otp_block6_w5", &self.apb2otp_block6_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK6_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block6 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK6_W5_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK6_W5_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk6_w6.rs b/esp32p4/src/efuse/apb2otp_blk6_w6.rs
index d9fab0fcaa..759c541743 100644
--- a/esp32p4/src/efuse/apb2otp_blk6_w6.rs
+++ b/esp32p4/src/efuse/apb2otp_blk6_w6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK6_W6")
-            .field(
-                "apb2otp_block6_w6",
-                &format_args!("{}", self.apb2otp_block6_w6().bits()),
-            )
+            .field("apb2otp_block6_w6", &self.apb2otp_block6_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK6_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block6 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK6_W6_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK6_W6_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk6_w7.rs b/esp32p4/src/efuse/apb2otp_blk6_w7.rs
index 2f1e73daad..8e1a604442 100644
--- a/esp32p4/src/efuse/apb2otp_blk6_w7.rs
+++ b/esp32p4/src/efuse/apb2otp_blk6_w7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK6_W7")
-            .field(
-                "apb2otp_block6_w7",
-                &format_args!("{}", self.apb2otp_block6_w7().bits()),
-            )
+            .field("apb2otp_block6_w7", &self.apb2otp_block6_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK6_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block6 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK6_W7_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK6_W7_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk6_w8.rs b/esp32p4/src/efuse/apb2otp_blk6_w8.rs
index 5aef4646cb..03241bca19 100644
--- a/esp32p4/src/efuse/apb2otp_blk6_w8.rs
+++ b/esp32p4/src/efuse/apb2otp_blk6_w8.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK6_W8")
-            .field(
-                "apb2otp_block6_w8",
-                &format_args!("{}", self.apb2otp_block6_w8().bits()),
-            )
+            .field("apb2otp_block6_w8", &self.apb2otp_block6_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK6_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block6 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK6_W8_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK6_W8_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk6_w9.rs b/esp32p4/src/efuse/apb2otp_blk6_w9.rs
index cdf1ec11db..7169d43f44 100644
--- a/esp32p4/src/efuse/apb2otp_blk6_w9.rs
+++ b/esp32p4/src/efuse/apb2otp_blk6_w9.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK6_W9")
-            .field(
-                "apb2otp_block6_w9",
-                &format_args!("{}", self.apb2otp_block6_w9().bits()),
-            )
+            .field("apb2otp_block6_w9", &self.apb2otp_block6_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK6_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block6 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk6_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK6_W9_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK6_W9_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk7_w1.rs b/esp32p4/src/efuse/apb2otp_blk7_w1.rs
index e280fc30a8..631cbf31d4 100644
--- a/esp32p4/src/efuse/apb2otp_blk7_w1.rs
+++ b/esp32p4/src/efuse/apb2otp_blk7_w1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK7_W1")
-            .field(
-                "apb2otp_block7_w1",
-                &format_args!("{}", self.apb2otp_block7_w1().bits()),
-            )
+            .field("apb2otp_block7_w1", &self.apb2otp_block7_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK7_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block7 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK7_W1_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK7_W1_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk7_w10.rs b/esp32p4/src/efuse/apb2otp_blk7_w10.rs
index c523ead9ab..42d40e9cba 100644
--- a/esp32p4/src/efuse/apb2otp_blk7_w10.rs
+++ b/esp32p4/src/efuse/apb2otp_blk7_w10.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK7_W10")
-            .field(
-                "apb2otp_block7_w10",
-                &format_args!("{}", self.apb2otp_block7_w10().bits()),
-            )
+            .field("apb2otp_block7_w10", &self.apb2otp_block7_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK7_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block7 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK7_W10_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK7_W10_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk7_w11.rs b/esp32p4/src/efuse/apb2otp_blk7_w11.rs
index 7bc6a56e69..a967b84208 100644
--- a/esp32p4/src/efuse/apb2otp_blk7_w11.rs
+++ b/esp32p4/src/efuse/apb2otp_blk7_w11.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK7_W11")
-            .field(
-                "apb2otp_block7_w11",
-                &format_args!("{}", self.apb2otp_block7_w11().bits()),
-            )
+            .field("apb2otp_block7_w11", &self.apb2otp_block7_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK7_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block7 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK7_W11_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK7_W11_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk7_w2.rs b/esp32p4/src/efuse/apb2otp_blk7_w2.rs
index b2c3845451..8a9f1104c5 100644
--- a/esp32p4/src/efuse/apb2otp_blk7_w2.rs
+++ b/esp32p4/src/efuse/apb2otp_blk7_w2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK7_W2")
-            .field(
-                "apb2otp_block7_w2",
-                &format_args!("{}", self.apb2otp_block7_w2().bits()),
-            )
+            .field("apb2otp_block7_w2", &self.apb2otp_block7_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK7_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block7 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK7_W2_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK7_W2_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk7_w3.rs b/esp32p4/src/efuse/apb2otp_blk7_w3.rs
index ab207b6f83..409c1f1571 100644
--- a/esp32p4/src/efuse/apb2otp_blk7_w3.rs
+++ b/esp32p4/src/efuse/apb2otp_blk7_w3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK7_W3")
-            .field(
-                "apb2otp_block7_w3",
-                &format_args!("{}", self.apb2otp_block7_w3().bits()),
-            )
+            .field("apb2otp_block7_w3", &self.apb2otp_block7_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK7_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block7 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK7_W3_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK7_W3_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk7_w4.rs b/esp32p4/src/efuse/apb2otp_blk7_w4.rs
index afa14bf70c..189e2bd230 100644
--- a/esp32p4/src/efuse/apb2otp_blk7_w4.rs
+++ b/esp32p4/src/efuse/apb2otp_blk7_w4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK7_W4")
-            .field(
-                "apb2otp_block7_w4",
-                &format_args!("{}", self.apb2otp_block7_w4().bits()),
-            )
+            .field("apb2otp_block7_w4", &self.apb2otp_block7_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK7_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block7 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK7_W4_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK7_W4_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk7_w5.rs b/esp32p4/src/efuse/apb2otp_blk7_w5.rs
index f5119e27ec..e0d8aa0358 100644
--- a/esp32p4/src/efuse/apb2otp_blk7_w5.rs
+++ b/esp32p4/src/efuse/apb2otp_blk7_w5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK7_W5")
-            .field(
-                "apb2otp_block7_w5",
-                &format_args!("{}", self.apb2otp_block7_w5().bits()),
-            )
+            .field("apb2otp_block7_w5", &self.apb2otp_block7_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK7_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block7 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK7_W5_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK7_W5_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk7_w6.rs b/esp32p4/src/efuse/apb2otp_blk7_w6.rs
index 80f96c308a..4dc9d8d847 100644
--- a/esp32p4/src/efuse/apb2otp_blk7_w6.rs
+++ b/esp32p4/src/efuse/apb2otp_blk7_w6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK7_W6")
-            .field(
-                "apb2otp_block7_w6",
-                &format_args!("{}", self.apb2otp_block7_w6().bits()),
-            )
+            .field("apb2otp_block7_w6", &self.apb2otp_block7_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK7_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block7 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK7_W6_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK7_W6_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk7_w7.rs b/esp32p4/src/efuse/apb2otp_blk7_w7.rs
index 5b13a4f757..c82d288ab6 100644
--- a/esp32p4/src/efuse/apb2otp_blk7_w7.rs
+++ b/esp32p4/src/efuse/apb2otp_blk7_w7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK7_W7")
-            .field(
-                "apb2otp_block7_w7",
-                &format_args!("{}", self.apb2otp_block7_w7().bits()),
-            )
+            .field("apb2otp_block7_w7", &self.apb2otp_block7_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK7_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block7 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK7_W7_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK7_W7_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk7_w8.rs b/esp32p4/src/efuse/apb2otp_blk7_w8.rs
index da470e8b24..6ff34c0f48 100644
--- a/esp32p4/src/efuse/apb2otp_blk7_w8.rs
+++ b/esp32p4/src/efuse/apb2otp_blk7_w8.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK7_W8")
-            .field(
-                "apb2otp_block7_w8",
-                &format_args!("{}", self.apb2otp_block7_w8().bits()),
-            )
+            .field("apb2otp_block7_w8", &self.apb2otp_block7_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK7_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block7 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK7_W8_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK7_W8_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk7_w9.rs b/esp32p4/src/efuse/apb2otp_blk7_w9.rs
index 1821a3cbd7..df3db0774d 100644
--- a/esp32p4/src/efuse/apb2otp_blk7_w9.rs
+++ b/esp32p4/src/efuse/apb2otp_blk7_w9.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK7_W9")
-            .field(
-                "apb2otp_block7_w9",
-                &format_args!("{}", self.apb2otp_block7_w9().bits()),
-            )
+            .field("apb2otp_block7_w9", &self.apb2otp_block7_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK7_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block7 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk7_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK7_W9_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK7_W9_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk8_w1.rs b/esp32p4/src/efuse/apb2otp_blk8_w1.rs
index c35b3a2218..6878e3c305 100644
--- a/esp32p4/src/efuse/apb2otp_blk8_w1.rs
+++ b/esp32p4/src/efuse/apb2otp_blk8_w1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK8_W1")
-            .field(
-                "apb2otp_block8_w1",
-                &format_args!("{}", self.apb2otp_block8_w1().bits()),
-            )
+            .field("apb2otp_block8_w1", &self.apb2otp_block8_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK8_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block8 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK8_W1_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK8_W1_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk8_w10.rs b/esp32p4/src/efuse/apb2otp_blk8_w10.rs
index fbad6db973..96049ae7a3 100644
--- a/esp32p4/src/efuse/apb2otp_blk8_w10.rs
+++ b/esp32p4/src/efuse/apb2otp_blk8_w10.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK8_W10")
-            .field(
-                "apb2otp_block8_w10",
-                &format_args!("{}", self.apb2otp_block8_w10().bits()),
-            )
+            .field("apb2otp_block8_w10", &self.apb2otp_block8_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK8_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block8 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK8_W10_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK8_W10_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk8_w11.rs b/esp32p4/src/efuse/apb2otp_blk8_w11.rs
index 439ea7ce4d..761cbcd9df 100644
--- a/esp32p4/src/efuse/apb2otp_blk8_w11.rs
+++ b/esp32p4/src/efuse/apb2otp_blk8_w11.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK8_W11")
-            .field(
-                "apb2otp_block8_w11",
-                &format_args!("{}", self.apb2otp_block8_w11().bits()),
-            )
+            .field("apb2otp_block8_w11", &self.apb2otp_block8_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK8_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block8 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK8_W11_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK8_W11_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk8_w2.rs b/esp32p4/src/efuse/apb2otp_blk8_w2.rs
index 97da8243b1..1da283142b 100644
--- a/esp32p4/src/efuse/apb2otp_blk8_w2.rs
+++ b/esp32p4/src/efuse/apb2otp_blk8_w2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK8_W2")
-            .field(
-                "apb2otp_block8_w2",
-                &format_args!("{}", self.apb2otp_block8_w2().bits()),
-            )
+            .field("apb2otp_block8_w2", &self.apb2otp_block8_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK8_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block8 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK8_W2_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK8_W2_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk8_w3.rs b/esp32p4/src/efuse/apb2otp_blk8_w3.rs
index 84010b7f3c..9572c132a0 100644
--- a/esp32p4/src/efuse/apb2otp_blk8_w3.rs
+++ b/esp32p4/src/efuse/apb2otp_blk8_w3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK8_W3")
-            .field(
-                "apb2otp_block8_w3",
-                &format_args!("{}", self.apb2otp_block8_w3().bits()),
-            )
+            .field("apb2otp_block8_w3", &self.apb2otp_block8_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK8_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block8 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK8_W3_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK8_W3_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk8_w4.rs b/esp32p4/src/efuse/apb2otp_blk8_w4.rs
index 8169042916..497932ccbe 100644
--- a/esp32p4/src/efuse/apb2otp_blk8_w4.rs
+++ b/esp32p4/src/efuse/apb2otp_blk8_w4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK8_W4")
-            .field(
-                "apb2otp_block8_w4",
-                &format_args!("{}", self.apb2otp_block8_w4().bits()),
-            )
+            .field("apb2otp_block8_w4", &self.apb2otp_block8_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK8_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block8 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK8_W4_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK8_W4_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk8_w5.rs b/esp32p4/src/efuse/apb2otp_blk8_w5.rs
index 872e774435..f3074ac617 100644
--- a/esp32p4/src/efuse/apb2otp_blk8_w5.rs
+++ b/esp32p4/src/efuse/apb2otp_blk8_w5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK8_W5")
-            .field(
-                "apb2otp_block8_w5",
-                &format_args!("{}", self.apb2otp_block8_w5().bits()),
-            )
+            .field("apb2otp_block8_w5", &self.apb2otp_block8_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK8_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block8 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK8_W5_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK8_W5_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk8_w6.rs b/esp32p4/src/efuse/apb2otp_blk8_w6.rs
index 56cf31cf16..76349a1716 100644
--- a/esp32p4/src/efuse/apb2otp_blk8_w6.rs
+++ b/esp32p4/src/efuse/apb2otp_blk8_w6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK8_W6")
-            .field(
-                "apb2otp_block8_w6",
-                &format_args!("{}", self.apb2otp_block8_w6().bits()),
-            )
+            .field("apb2otp_block8_w6", &self.apb2otp_block8_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK8_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block8 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK8_W6_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK8_W6_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk8_w7.rs b/esp32p4/src/efuse/apb2otp_blk8_w7.rs
index e4bf4e4494..a20453ffff 100644
--- a/esp32p4/src/efuse/apb2otp_blk8_w7.rs
+++ b/esp32p4/src/efuse/apb2otp_blk8_w7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK8_W7")
-            .field(
-                "apb2otp_block8_w7",
-                &format_args!("{}", self.apb2otp_block8_w7().bits()),
-            )
+            .field("apb2otp_block8_w7", &self.apb2otp_block8_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK8_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block8 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK8_W7_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK8_W7_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk8_w8.rs b/esp32p4/src/efuse/apb2otp_blk8_w8.rs
index 940b05e265..7b868890bf 100644
--- a/esp32p4/src/efuse/apb2otp_blk8_w8.rs
+++ b/esp32p4/src/efuse/apb2otp_blk8_w8.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK8_W8")
-            .field(
-                "apb2otp_block8_w8",
-                &format_args!("{}", self.apb2otp_block8_w8().bits()),
-            )
+            .field("apb2otp_block8_w8", &self.apb2otp_block8_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK8_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block8 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK8_W8_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK8_W8_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk8_w9.rs b/esp32p4/src/efuse/apb2otp_blk8_w9.rs
index b77631b75e..5ef97f8eeb 100644
--- a/esp32p4/src/efuse/apb2otp_blk8_w9.rs
+++ b/esp32p4/src/efuse/apb2otp_blk8_w9.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK8_W9")
-            .field(
-                "apb2otp_block8_w9",
-                &format_args!("{}", self.apb2otp_block8_w9().bits()),
-            )
+            .field("apb2otp_block8_w9", &self.apb2otp_block8_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK8_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block8 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk8_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK8_W9_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK8_W9_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk9_w1.rs b/esp32p4/src/efuse/apb2otp_blk9_w1.rs
index b196f6474e..f4dcd4e20d 100644
--- a/esp32p4/src/efuse/apb2otp_blk9_w1.rs
+++ b/esp32p4/src/efuse/apb2otp_blk9_w1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK9_W1")
-            .field(
-                "apb2otp_block9_w1",
-                &format_args!("{}", self.apb2otp_block9_w1().bits()),
-            )
+            .field("apb2otp_block9_w1", &self.apb2otp_block9_w1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK9_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block9 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK9_W1_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK9_W1_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk9_w10.rs b/esp32p4/src/efuse/apb2otp_blk9_w10.rs
index 2f8fb587b6..3fb94b5734 100644
--- a/esp32p4/src/efuse/apb2otp_blk9_w10.rs
+++ b/esp32p4/src/efuse/apb2otp_blk9_w10.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK9_W10")
-            .field(
-                "apb2otp_block9_w10",
-                &format_args!("{}", self.apb2otp_block9_w10().bits()),
-            )
+            .field("apb2otp_block9_w10", &self.apb2otp_block9_w10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK9_W10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block9 data register10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK9_W10_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK9_W10_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk9_w11.rs b/esp32p4/src/efuse/apb2otp_blk9_w11.rs
index 5fe3deb306..6b40a55bef 100644
--- a/esp32p4/src/efuse/apb2otp_blk9_w11.rs
+++ b/esp32p4/src/efuse/apb2otp_blk9_w11.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK9_W11")
-            .field(
-                "apb2otp_block9_w11",
-                &format_args!("{}", self.apb2otp_block9_w11().bits()),
-            )
+            .field("apb2otp_block9_w11", &self.apb2otp_block9_w11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK9_W11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block9 data register11.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK9_W11_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK9_W11_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk9_w2.rs b/esp32p4/src/efuse/apb2otp_blk9_w2.rs
index 59fde4eeb7..0000bf57f2 100644
--- a/esp32p4/src/efuse/apb2otp_blk9_w2.rs
+++ b/esp32p4/src/efuse/apb2otp_blk9_w2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK9_W2")
-            .field(
-                "apb2otp_block9_w2",
-                &format_args!("{}", self.apb2otp_block9_w2().bits()),
-            )
+            .field("apb2otp_block9_w2", &self.apb2otp_block9_w2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK9_W2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block9 data register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK9_W2_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK9_W2_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk9_w3.rs b/esp32p4/src/efuse/apb2otp_blk9_w3.rs
index eb31511e8b..a317f205f1 100644
--- a/esp32p4/src/efuse/apb2otp_blk9_w3.rs
+++ b/esp32p4/src/efuse/apb2otp_blk9_w3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK9_W3")
-            .field(
-                "apb2otp_block9_w3",
-                &format_args!("{}", self.apb2otp_block9_w3().bits()),
-            )
+            .field("apb2otp_block9_w3", &self.apb2otp_block9_w3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK9_W3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block9 data register3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK9_W3_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK9_W3_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk9_w4.rs b/esp32p4/src/efuse/apb2otp_blk9_w4.rs
index f2e561011b..54fc5a19c5 100644
--- a/esp32p4/src/efuse/apb2otp_blk9_w4.rs
+++ b/esp32p4/src/efuse/apb2otp_blk9_w4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK9_W4")
-            .field(
-                "apb2otp_block9_w4",
-                &format_args!("{}", self.apb2otp_block9_w4().bits()),
-            )
+            .field("apb2otp_block9_w4", &self.apb2otp_block9_w4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK9_W4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block9 data register4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK9_W4_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK9_W4_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk9_w5.rs b/esp32p4/src/efuse/apb2otp_blk9_w5.rs
index d949547c62..e40d2acd24 100644
--- a/esp32p4/src/efuse/apb2otp_blk9_w5.rs
+++ b/esp32p4/src/efuse/apb2otp_blk9_w5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK9_W5")
-            .field(
-                "apb2otp_block9_w5",
-                &format_args!("{}", self.apb2otp_block9_w5().bits()),
-            )
+            .field("apb2otp_block9_w5", &self.apb2otp_block9_w5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK9_W5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block9 data register5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK9_W5_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK9_W5_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk9_w6.rs b/esp32p4/src/efuse/apb2otp_blk9_w6.rs
index f4dc4e1351..fc5cf9a5be 100644
--- a/esp32p4/src/efuse/apb2otp_blk9_w6.rs
+++ b/esp32p4/src/efuse/apb2otp_blk9_w6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK9_W6")
-            .field(
-                "apb2otp_block9_w6",
-                &format_args!("{}", self.apb2otp_block9_w6().bits()),
-            )
+            .field("apb2otp_block9_w6", &self.apb2otp_block9_w6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK9_W6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block9 data register6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK9_W6_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK9_W6_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk9_w7.rs b/esp32p4/src/efuse/apb2otp_blk9_w7.rs
index cded12894f..c4dbcce131 100644
--- a/esp32p4/src/efuse/apb2otp_blk9_w7.rs
+++ b/esp32p4/src/efuse/apb2otp_blk9_w7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK9_W7")
-            .field(
-                "apb2otp_block9_w7",
-                &format_args!("{}", self.apb2otp_block9_w7().bits()),
-            )
+            .field("apb2otp_block9_w7", &self.apb2otp_block9_w7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK9_W7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block9 data register7.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK9_W7_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK9_W7_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk9_w8.rs b/esp32p4/src/efuse/apb2otp_blk9_w8.rs
index 9ea240bc88..4bef2a4464 100644
--- a/esp32p4/src/efuse/apb2otp_blk9_w8.rs
+++ b/esp32p4/src/efuse/apb2otp_blk9_w8.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK9_W8")
-            .field(
-                "apb2otp_block9_w8",
-                &format_args!("{}", self.apb2otp_block9_w8().bits()),
-            )
+            .field("apb2otp_block9_w8", &self.apb2otp_block9_w8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK9_W8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block9 data register8.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK9_W8_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK9_W8_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_blk9_w9.rs b/esp32p4/src/efuse/apb2otp_blk9_w9.rs
index 4c41e30eba..d211f68e51 100644
--- a/esp32p4/src/efuse/apb2otp_blk9_w9.rs
+++ b/esp32p4/src/efuse/apb2otp_blk9_w9.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_BLK9_W9")
-            .field(
-                "apb2otp_block9_w9",
-                &format_args!("{}", self.apb2otp_block9_w9().bits()),
-            )
+            .field("apb2otp_block9_w9", &self.apb2otp_block9_w9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_BLK9_W9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block9 data register9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_blk9_w9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_BLK9_W9_SPEC;
 impl crate::RegisterSpec for APB2OTP_BLK9_W9_SPEC {
diff --git a/esp32p4/src/efuse/apb2otp_en.rs b/esp32p4/src/efuse/apb2otp_en.rs
index c4becc248f..2f88332b06 100644
--- a/esp32p4/src/efuse/apb2otp_en.rs
+++ b/esp32p4/src/efuse/apb2otp_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_EN")
-            .field(
-                "apb2otp_apb2otp_en",
-                &format_args!("{}", self.apb2otp_apb2otp_en().bit()),
-            )
+            .field("apb2otp_apb2otp_en", &self.apb2otp_apb2otp_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Apb2otp mode enable signal."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/apb2otp_wr_dis.rs b/esp32p4/src/efuse/apb2otp_wr_dis.rs
index 0e8cf7c7e4..84326fcab9 100644
--- a/esp32p4/src/efuse/apb2otp_wr_dis.rs
+++ b/esp32p4/src/efuse/apb2otp_wr_dis.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB2OTP_WR_DIS")
-            .field(
-                "apb2otp_block0_wr_dis",
-                &format_args!("{}", self.apb2otp_block0_wr_dis().bits()),
-            )
+            .field("apb2otp_block0_wr_dis", &self.apb2otp_block0_wr_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB2OTP_WR_DIS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse apb2otp block0 data register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb2otp_wr_dis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB2OTP_WR_DIS_SPEC;
 impl crate::RegisterSpec for APB2OTP_WR_DIS_SPEC {
diff --git a/esp32p4/src/efuse/clk.rs b/esp32p4/src/efuse/clk.rs
index 627ab3ffde..a85bdddc76 100644
--- a/esp32p4/src/efuse/clk.rs
+++ b/esp32p4/src/efuse/clk.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK")
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_clk_force_on",
-                &format_args!("{}", self.mem_clk_force_on().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_clk_force_on", &self.mem_clk_force_on())
+            .field("mem_force_pu", &self.mem_force_pu())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to force eFuse SRAM into power-saving mode."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/cmd.rs b/esp32p4/src/efuse/cmd.rs
index 8dee79bc65..094d443be3 100644
--- a/esp32p4/src/efuse/cmd.rs
+++ b/esp32p4/src/efuse/cmd.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("read_cmd", &format_args!("{}", self.read_cmd().bit()))
-            .field("pgm_cmd", &format_args!("{}", self.pgm_cmd().bit()))
-            .field("blk_num", &format_args!("{}", self.blk_num().bits()))
+            .field("read_cmd", &self.read_cmd())
+            .field("pgm_cmd", &self.pgm_cmd())
+            .field("blk_num", &self.blk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to send read command."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/conf.rs b/esp32p4/src/efuse/conf.rs
index 65fd73616a..7236cc41ce 100644
--- a/esp32p4/src/efuse/conf.rs
+++ b/esp32p4/src/efuse/conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("op_code", &format_args!("{}", self.op_code().bits()))
-            .field(
-                "cfg_ecdsa_blk",
-                &format_args!("{}", self.cfg_ecdsa_blk().bits()),
-            )
+            .field("op_code", &self.op_code())
+            .field("cfg_ecdsa_blk", &self.cfg_ecdsa_blk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - 0x5A5A: programming operation command 0x5AA5: read operation command."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/dac_conf.rs b/esp32p4/src/efuse/dac_conf.rs
index 857103d692..815994bb58 100644
--- a/esp32p4/src/efuse/dac_conf.rs
+++ b/esp32p4/src/efuse/dac_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DAC_CONF")
-            .field(
-                "dac_clk_div",
-                &format_args!("{}", self.dac_clk_div().bits()),
-            )
-            .field(
-                "dac_clk_pad_sel",
-                &format_args!("{}", self.dac_clk_pad_sel().bit()),
-            )
-            .field("dac_num", &format_args!("{}", self.dac_num().bits()))
-            .field("oe_clr", &format_args!("{}", self.oe_clr().bit()))
+            .field("dac_clk_div", &self.dac_clk_div())
+            .field("dac_clk_pad_sel", &self.dac_clk_pad_sel())
+            .field("dac_num", &self.dac_num())
+            .field("oe_clr", &self.oe_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DAC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Controls the division factor of the rising clock of the programming voltage."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/date.rs b/esp32p4/src/efuse/date.rs
index 7897ee161b..6347a6c308 100644
--- a/esp32p4/src/efuse/date.rs
+++ b/esp32p4/src/efuse/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/efuse/int_ena.rs b/esp32p4/src/efuse/int_ena.rs
index 6386df2821..0020c7e668 100644
--- a/esp32p4/src/efuse/int_ena.rs
+++ b/esp32p4/src/efuse/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable signal for read_done interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/int_raw.rs b/esp32p4/src/efuse/int_raw.rs
index b69c288afb..efd8b89205 100644
--- a/esp32p4/src/efuse/int_raw.rs
+++ b/esp32p4/src/efuse/int_raw.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse raw interrupt register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32p4/src/efuse/int_st.rs b/esp32p4/src/efuse/int_st.rs
index 898ceb8e8b..efba508ff2 100644
--- a/esp32p4/src/efuse/int_st.rs
+++ b/esp32p4/src/efuse/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/efuse/pgm_check_value0.rs b/esp32p4/src/efuse/pgm_check_value0.rs
index 663f1a6b52..ab1a0f0553 100644
--- a/esp32p4/src/efuse/pgm_check_value0.rs
+++ b/esp32p4/src/efuse/pgm_check_value0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE0")
-            .field(
-                "pgm_rs_data_0",
-                &format_args!("{}", self.pgm_rs_data_0().bits()),
-            )
+            .field("pgm_rs_data_0", &self.pgm_rs_data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 0th 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/pgm_check_value1.rs b/esp32p4/src/efuse/pgm_check_value1.rs
index d7333c0b68..2190b87db3 100644
--- a/esp32p4/src/efuse/pgm_check_value1.rs
+++ b/esp32p4/src/efuse/pgm_check_value1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE1")
-            .field(
-                "pgm_rs_data_1",
-                &format_args!("{}", self.pgm_rs_data_1().bits()),
-            )
+            .field("pgm_rs_data_1", &self.pgm_rs_data_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 1st 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/pgm_check_value2.rs b/esp32p4/src/efuse/pgm_check_value2.rs
index ea8f275832..9f176182aa 100644
--- a/esp32p4/src/efuse/pgm_check_value2.rs
+++ b/esp32p4/src/efuse/pgm_check_value2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE2")
-            .field(
-                "pgm_rs_data_2",
-                &format_args!("{}", self.pgm_rs_data_2().bits()),
-            )
+            .field("pgm_rs_data_2", &self.pgm_rs_data_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 2nd 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/pgm_data0.rs b/esp32p4/src/efuse/pgm_data0.rs
index 99d1a39f3d..2fa0081de0 100644
--- a/esp32p4/src/efuse/pgm_data0.rs
+++ b/esp32p4/src/efuse/pgm_data0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA0")
-            .field("pgm_data_0", &format_args!("{}", self.pgm_data_0().bits()))
+            .field("pgm_data_0", &self.pgm_data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 0th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/pgm_data1.rs b/esp32p4/src/efuse/pgm_data1.rs
index dd5c818232..1fcd9bb4ec 100644
--- a/esp32p4/src/efuse/pgm_data1.rs
+++ b/esp32p4/src/efuse/pgm_data1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA1")
-            .field("pgm_data_1", &format_args!("{}", self.pgm_data_1().bits()))
+            .field("pgm_data_1", &self.pgm_data_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 1st 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/pgm_data2.rs b/esp32p4/src/efuse/pgm_data2.rs
index 9297097580..07fc1fa3b9 100644
--- a/esp32p4/src/efuse/pgm_data2.rs
+++ b/esp32p4/src/efuse/pgm_data2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA2")
-            .field("pgm_data_2", &format_args!("{}", self.pgm_data_2().bits()))
+            .field("pgm_data_2", &self.pgm_data_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 2nd 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/pgm_data3.rs b/esp32p4/src/efuse/pgm_data3.rs
index beb3114ecf..bf3f5ccec2 100644
--- a/esp32p4/src/efuse/pgm_data3.rs
+++ b/esp32p4/src/efuse/pgm_data3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA3")
-            .field("pgm_data_3", &format_args!("{}", self.pgm_data_3().bits()))
+            .field("pgm_data_3", &self.pgm_data_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 3rd 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/pgm_data4.rs b/esp32p4/src/efuse/pgm_data4.rs
index ab568669b6..8aea0c46cb 100644
--- a/esp32p4/src/efuse/pgm_data4.rs
+++ b/esp32p4/src/efuse/pgm_data4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA4")
-            .field("pgm_data_4", &format_args!("{}", self.pgm_data_4().bits()))
+            .field("pgm_data_4", &self.pgm_data_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 4th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/pgm_data5.rs b/esp32p4/src/efuse/pgm_data5.rs
index a563072d44..c09c8a828a 100644
--- a/esp32p4/src/efuse/pgm_data5.rs
+++ b/esp32p4/src/efuse/pgm_data5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA5")
-            .field("pgm_data_5", &format_args!("{}", self.pgm_data_5().bits()))
+            .field("pgm_data_5", &self.pgm_data_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 5th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/pgm_data6.rs b/esp32p4/src/efuse/pgm_data6.rs
index 3068ec971d..1c9e0c9011 100644
--- a/esp32p4/src/efuse/pgm_data6.rs
+++ b/esp32p4/src/efuse/pgm_data6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA6")
-            .field("pgm_data_6", &format_args!("{}", self.pgm_data_6().bits()))
+            .field("pgm_data_6", &self.pgm_data_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 6th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/pgm_data7.rs b/esp32p4/src/efuse/pgm_data7.rs
index 0087318233..b913c59fad 100644
--- a/esp32p4/src/efuse/pgm_data7.rs
+++ b/esp32p4/src/efuse/pgm_data7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA7")
-            .field("pgm_data_7", &format_args!("{}", self.pgm_data_7().bits()))
+            .field("pgm_data_7", &self.pgm_data_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the 7th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/rd_key0_data0.rs b/esp32p4/src/efuse/rd_key0_data0.rs
index b4ee49df3a..66bdc7a995 100644
--- a/esp32p4/src/efuse/rd_key0_data0.rs
+++ b/esp32p4/src/efuse/rd_key0_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA0")
-            .field("key0_data0", &format_args!("{}", self.key0_data0().bits()))
+            .field("key0_data0", &self.key0_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA0_SPEC {
diff --git a/esp32p4/src/efuse/rd_key0_data1.rs b/esp32p4/src/efuse/rd_key0_data1.rs
index 1f8251375b..5efa9fd856 100644
--- a/esp32p4/src/efuse/rd_key0_data1.rs
+++ b/esp32p4/src/efuse/rd_key0_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA1")
-            .field("key0_data1", &format_args!("{}", self.key0_data1().bits()))
+            .field("key0_data1", &self.key0_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA1_SPEC {
diff --git a/esp32p4/src/efuse/rd_key0_data2.rs b/esp32p4/src/efuse/rd_key0_data2.rs
index be8f375983..4a38cbfd42 100644
--- a/esp32p4/src/efuse/rd_key0_data2.rs
+++ b/esp32p4/src/efuse/rd_key0_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA2")
-            .field("key0_data2", &format_args!("{}", self.key0_data2().bits()))
+            .field("key0_data2", &self.key0_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA2_SPEC {
diff --git a/esp32p4/src/efuse/rd_key0_data3.rs b/esp32p4/src/efuse/rd_key0_data3.rs
index 6d2222cda9..736e197bb4 100644
--- a/esp32p4/src/efuse/rd_key0_data3.rs
+++ b/esp32p4/src/efuse/rd_key0_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA3")
-            .field("key0_data3", &format_args!("{}", self.key0_data3().bits()))
+            .field("key0_data3", &self.key0_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA3_SPEC {
diff --git a/esp32p4/src/efuse/rd_key0_data4.rs b/esp32p4/src/efuse/rd_key0_data4.rs
index 5c5d3846a2..f57c6246c0 100644
--- a/esp32p4/src/efuse/rd_key0_data4.rs
+++ b/esp32p4/src/efuse/rd_key0_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA4")
-            .field("key0_data4", &format_args!("{}", self.key0_data4().bits()))
+            .field("key0_data4", &self.key0_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA4_SPEC {
diff --git a/esp32p4/src/efuse/rd_key0_data5.rs b/esp32p4/src/efuse/rd_key0_data5.rs
index e675b726d9..fc6203feb8 100644
--- a/esp32p4/src/efuse/rd_key0_data5.rs
+++ b/esp32p4/src/efuse/rd_key0_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA5")
-            .field("key0_data5", &format_args!("{}", self.key0_data5().bits()))
+            .field("key0_data5", &self.key0_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA5_SPEC {
diff --git a/esp32p4/src/efuse/rd_key0_data6.rs b/esp32p4/src/efuse/rd_key0_data6.rs
index 506e4a1a76..021d664b62 100644
--- a/esp32p4/src/efuse/rd_key0_data6.rs
+++ b/esp32p4/src/efuse/rd_key0_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA6")
-            .field("key0_data6", &format_args!("{}", self.key0_data6().bits()))
+            .field("key0_data6", &self.key0_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA6_SPEC {
diff --git a/esp32p4/src/efuse/rd_key0_data7.rs b/esp32p4/src/efuse/rd_key0_data7.rs
index 97d737135d..a6442fdf78 100644
--- a/esp32p4/src/efuse/rd_key0_data7.rs
+++ b/esp32p4/src/efuse/rd_key0_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA7")
-            .field("key0_data7", &format_args!("{}", self.key0_data7().bits()))
+            .field("key0_data7", &self.key0_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA7_SPEC {
diff --git a/esp32p4/src/efuse/rd_key1_data0.rs b/esp32p4/src/efuse/rd_key1_data0.rs
index c70f6acd7f..6b2431620c 100644
--- a/esp32p4/src/efuse/rd_key1_data0.rs
+++ b/esp32p4/src/efuse/rd_key1_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA0")
-            .field("key1_data0", &format_args!("{}", self.key1_data0().bits()))
+            .field("key1_data0", &self.key1_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA0_SPEC {
diff --git a/esp32p4/src/efuse/rd_key1_data1.rs b/esp32p4/src/efuse/rd_key1_data1.rs
index aae8bcee9a..f231c8b98a 100644
--- a/esp32p4/src/efuse/rd_key1_data1.rs
+++ b/esp32p4/src/efuse/rd_key1_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA1")
-            .field("key1_data1", &format_args!("{}", self.key1_data1().bits()))
+            .field("key1_data1", &self.key1_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA1_SPEC {
diff --git a/esp32p4/src/efuse/rd_key1_data2.rs b/esp32p4/src/efuse/rd_key1_data2.rs
index 1966a996a6..4ededdea0a 100644
--- a/esp32p4/src/efuse/rd_key1_data2.rs
+++ b/esp32p4/src/efuse/rd_key1_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA2")
-            .field("key1_data2", &format_args!("{}", self.key1_data2().bits()))
+            .field("key1_data2", &self.key1_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA2_SPEC {
diff --git a/esp32p4/src/efuse/rd_key1_data3.rs b/esp32p4/src/efuse/rd_key1_data3.rs
index fdd40460e9..d20732a98a 100644
--- a/esp32p4/src/efuse/rd_key1_data3.rs
+++ b/esp32p4/src/efuse/rd_key1_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA3")
-            .field("key1_data3", &format_args!("{}", self.key1_data3().bits()))
+            .field("key1_data3", &self.key1_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA3_SPEC {
diff --git a/esp32p4/src/efuse/rd_key1_data4.rs b/esp32p4/src/efuse/rd_key1_data4.rs
index c786647016..d9e7d57ad6 100644
--- a/esp32p4/src/efuse/rd_key1_data4.rs
+++ b/esp32p4/src/efuse/rd_key1_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA4")
-            .field("key1_data4", &format_args!("{}", self.key1_data4().bits()))
+            .field("key1_data4", &self.key1_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA4_SPEC {
diff --git a/esp32p4/src/efuse/rd_key1_data5.rs b/esp32p4/src/efuse/rd_key1_data5.rs
index 0ea5b95d9f..9def03fecb 100644
--- a/esp32p4/src/efuse/rd_key1_data5.rs
+++ b/esp32p4/src/efuse/rd_key1_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA5")
-            .field("key1_data5", &format_args!("{}", self.key1_data5().bits()))
+            .field("key1_data5", &self.key1_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA5_SPEC {
diff --git a/esp32p4/src/efuse/rd_key1_data6.rs b/esp32p4/src/efuse/rd_key1_data6.rs
index ba8b96a6b3..9d5a3e944d 100644
--- a/esp32p4/src/efuse/rd_key1_data6.rs
+++ b/esp32p4/src/efuse/rd_key1_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA6")
-            .field("key1_data6", &format_args!("{}", self.key1_data6().bits()))
+            .field("key1_data6", &self.key1_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA6_SPEC {
diff --git a/esp32p4/src/efuse/rd_key1_data7.rs b/esp32p4/src/efuse/rd_key1_data7.rs
index ba5ea5e180..4d8d190773 100644
--- a/esp32p4/src/efuse/rd_key1_data7.rs
+++ b/esp32p4/src/efuse/rd_key1_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA7")
-            .field("key1_data7", &format_args!("{}", self.key1_data7().bits()))
+            .field("key1_data7", &self.key1_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA7_SPEC {
diff --git a/esp32p4/src/efuse/rd_key2_data0.rs b/esp32p4/src/efuse/rd_key2_data0.rs
index d090b56943..670f7a9712 100644
--- a/esp32p4/src/efuse/rd_key2_data0.rs
+++ b/esp32p4/src/efuse/rd_key2_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA0")
-            .field("key2_data0", &format_args!("{}", self.key2_data0().bits()))
+            .field("key2_data0", &self.key2_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA0_SPEC {
diff --git a/esp32p4/src/efuse/rd_key2_data1.rs b/esp32p4/src/efuse/rd_key2_data1.rs
index c8d52513bc..653b2d5860 100644
--- a/esp32p4/src/efuse/rd_key2_data1.rs
+++ b/esp32p4/src/efuse/rd_key2_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA1")
-            .field("key2_data1", &format_args!("{}", self.key2_data1().bits()))
+            .field("key2_data1", &self.key2_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA1_SPEC {
diff --git a/esp32p4/src/efuse/rd_key2_data2.rs b/esp32p4/src/efuse/rd_key2_data2.rs
index 594db86d03..ac2ec13773 100644
--- a/esp32p4/src/efuse/rd_key2_data2.rs
+++ b/esp32p4/src/efuse/rd_key2_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA2")
-            .field("key2_data2", &format_args!("{}", self.key2_data2().bits()))
+            .field("key2_data2", &self.key2_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA2_SPEC {
diff --git a/esp32p4/src/efuse/rd_key2_data3.rs b/esp32p4/src/efuse/rd_key2_data3.rs
index 11ef6ae075..347ff260f3 100644
--- a/esp32p4/src/efuse/rd_key2_data3.rs
+++ b/esp32p4/src/efuse/rd_key2_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA3")
-            .field("key2_data3", &format_args!("{}", self.key2_data3().bits()))
+            .field("key2_data3", &self.key2_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA3_SPEC {
diff --git a/esp32p4/src/efuse/rd_key2_data4.rs b/esp32p4/src/efuse/rd_key2_data4.rs
index 4bdb2eb156..cde8d0559c 100644
--- a/esp32p4/src/efuse/rd_key2_data4.rs
+++ b/esp32p4/src/efuse/rd_key2_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA4")
-            .field("key2_data4", &format_args!("{}", self.key2_data4().bits()))
+            .field("key2_data4", &self.key2_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA4_SPEC {
diff --git a/esp32p4/src/efuse/rd_key2_data5.rs b/esp32p4/src/efuse/rd_key2_data5.rs
index d4c08fe8bb..071d63afed 100644
--- a/esp32p4/src/efuse/rd_key2_data5.rs
+++ b/esp32p4/src/efuse/rd_key2_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA5")
-            .field("key2_data5", &format_args!("{}", self.key2_data5().bits()))
+            .field("key2_data5", &self.key2_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA5_SPEC {
diff --git a/esp32p4/src/efuse/rd_key2_data6.rs b/esp32p4/src/efuse/rd_key2_data6.rs
index 5034d53b5d..a7b4b5e111 100644
--- a/esp32p4/src/efuse/rd_key2_data6.rs
+++ b/esp32p4/src/efuse/rd_key2_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA6")
-            .field("key2_data6", &format_args!("{}", self.key2_data6().bits()))
+            .field("key2_data6", &self.key2_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA6_SPEC {
diff --git a/esp32p4/src/efuse/rd_key2_data7.rs b/esp32p4/src/efuse/rd_key2_data7.rs
index 0ce4cdab66..26b73dab0a 100644
--- a/esp32p4/src/efuse/rd_key2_data7.rs
+++ b/esp32p4/src/efuse/rd_key2_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA7")
-            .field("key2_data7", &format_args!("{}", self.key2_data7().bits()))
+            .field("key2_data7", &self.key2_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA7_SPEC {
diff --git a/esp32p4/src/efuse/rd_key3_data0.rs b/esp32p4/src/efuse/rd_key3_data0.rs
index c7874ba60f..324ab8ee6c 100644
--- a/esp32p4/src/efuse/rd_key3_data0.rs
+++ b/esp32p4/src/efuse/rd_key3_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA0")
-            .field("key3_data0", &format_args!("{}", self.key3_data0().bits()))
+            .field("key3_data0", &self.key3_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA0_SPEC {
diff --git a/esp32p4/src/efuse/rd_key3_data1.rs b/esp32p4/src/efuse/rd_key3_data1.rs
index 2dcf03994c..036e846966 100644
--- a/esp32p4/src/efuse/rd_key3_data1.rs
+++ b/esp32p4/src/efuse/rd_key3_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA1")
-            .field("key3_data1", &format_args!("{}", self.key3_data1().bits()))
+            .field("key3_data1", &self.key3_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA1_SPEC {
diff --git a/esp32p4/src/efuse/rd_key3_data2.rs b/esp32p4/src/efuse/rd_key3_data2.rs
index 71a11073a1..a01ccae711 100644
--- a/esp32p4/src/efuse/rd_key3_data2.rs
+++ b/esp32p4/src/efuse/rd_key3_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA2")
-            .field("key3_data2", &format_args!("{}", self.key3_data2().bits()))
+            .field("key3_data2", &self.key3_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA2_SPEC {
diff --git a/esp32p4/src/efuse/rd_key3_data3.rs b/esp32p4/src/efuse/rd_key3_data3.rs
index 521e42b9ac..ccf4f14cc0 100644
--- a/esp32p4/src/efuse/rd_key3_data3.rs
+++ b/esp32p4/src/efuse/rd_key3_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA3")
-            .field("key3_data3", &format_args!("{}", self.key3_data3().bits()))
+            .field("key3_data3", &self.key3_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA3_SPEC {
diff --git a/esp32p4/src/efuse/rd_key3_data4.rs b/esp32p4/src/efuse/rd_key3_data4.rs
index b6cad4ee2d..800a8f1dba 100644
--- a/esp32p4/src/efuse/rd_key3_data4.rs
+++ b/esp32p4/src/efuse/rd_key3_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA4")
-            .field("key3_data4", &format_args!("{}", self.key3_data4().bits()))
+            .field("key3_data4", &self.key3_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA4_SPEC {
diff --git a/esp32p4/src/efuse/rd_key3_data5.rs b/esp32p4/src/efuse/rd_key3_data5.rs
index ba0c41d811..90fc05e6b9 100644
--- a/esp32p4/src/efuse/rd_key3_data5.rs
+++ b/esp32p4/src/efuse/rd_key3_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA5")
-            .field("key3_data5", &format_args!("{}", self.key3_data5().bits()))
+            .field("key3_data5", &self.key3_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA5_SPEC {
diff --git a/esp32p4/src/efuse/rd_key3_data6.rs b/esp32p4/src/efuse/rd_key3_data6.rs
index 3d3c27b27e..97260fcf21 100644
--- a/esp32p4/src/efuse/rd_key3_data6.rs
+++ b/esp32p4/src/efuse/rd_key3_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA6")
-            .field("key3_data6", &format_args!("{}", self.key3_data6().bits()))
+            .field("key3_data6", &self.key3_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA6_SPEC {
diff --git a/esp32p4/src/efuse/rd_key3_data7.rs b/esp32p4/src/efuse/rd_key3_data7.rs
index 13a0d80f7c..78b1712e01 100644
--- a/esp32p4/src/efuse/rd_key3_data7.rs
+++ b/esp32p4/src/efuse/rd_key3_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA7")
-            .field("key3_data7", &format_args!("{}", self.key3_data7().bits()))
+            .field("key3_data7", &self.key3_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA7_SPEC {
diff --git a/esp32p4/src/efuse/rd_key4_data0.rs b/esp32p4/src/efuse/rd_key4_data0.rs
index c7da39c966..49583f118a 100644
--- a/esp32p4/src/efuse/rd_key4_data0.rs
+++ b/esp32p4/src/efuse/rd_key4_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA0")
-            .field("key4_data0", &format_args!("{}", self.key4_data0().bits()))
+            .field("key4_data0", &self.key4_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA0_SPEC {
diff --git a/esp32p4/src/efuse/rd_key4_data1.rs b/esp32p4/src/efuse/rd_key4_data1.rs
index 4e619445d1..2255f15151 100644
--- a/esp32p4/src/efuse/rd_key4_data1.rs
+++ b/esp32p4/src/efuse/rd_key4_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA1")
-            .field("key4_data1", &format_args!("{}", self.key4_data1().bits()))
+            .field("key4_data1", &self.key4_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA1_SPEC {
diff --git a/esp32p4/src/efuse/rd_key4_data2.rs b/esp32p4/src/efuse/rd_key4_data2.rs
index d6bc03916d..cc38532702 100644
--- a/esp32p4/src/efuse/rd_key4_data2.rs
+++ b/esp32p4/src/efuse/rd_key4_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA2")
-            .field("key4_data2", &format_args!("{}", self.key4_data2().bits()))
+            .field("key4_data2", &self.key4_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA2_SPEC {
diff --git a/esp32p4/src/efuse/rd_key4_data3.rs b/esp32p4/src/efuse/rd_key4_data3.rs
index 164f9df5af..2a4cf9b5a6 100644
--- a/esp32p4/src/efuse/rd_key4_data3.rs
+++ b/esp32p4/src/efuse/rd_key4_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA3")
-            .field("key4_data3", &format_args!("{}", self.key4_data3().bits()))
+            .field("key4_data3", &self.key4_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA3_SPEC {
diff --git a/esp32p4/src/efuse/rd_key4_data4.rs b/esp32p4/src/efuse/rd_key4_data4.rs
index e647ac36c7..6a877dc0b6 100644
--- a/esp32p4/src/efuse/rd_key4_data4.rs
+++ b/esp32p4/src/efuse/rd_key4_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA4")
-            .field("key4_data4", &format_args!("{}", self.key4_data4().bits()))
+            .field("key4_data4", &self.key4_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA4_SPEC {
diff --git a/esp32p4/src/efuse/rd_key4_data5.rs b/esp32p4/src/efuse/rd_key4_data5.rs
index ede1293132..20291e45a5 100644
--- a/esp32p4/src/efuse/rd_key4_data5.rs
+++ b/esp32p4/src/efuse/rd_key4_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA5")
-            .field("key4_data5", &format_args!("{}", self.key4_data5().bits()))
+            .field("key4_data5", &self.key4_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA5_SPEC {
diff --git a/esp32p4/src/efuse/rd_key4_data6.rs b/esp32p4/src/efuse/rd_key4_data6.rs
index 2d81ffd6ec..acfc601dab 100644
--- a/esp32p4/src/efuse/rd_key4_data6.rs
+++ b/esp32p4/src/efuse/rd_key4_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA6")
-            .field("key4_data6", &format_args!("{}", self.key4_data6().bits()))
+            .field("key4_data6", &self.key4_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA6_SPEC {
diff --git a/esp32p4/src/efuse/rd_key4_data7.rs b/esp32p4/src/efuse/rd_key4_data7.rs
index 258ed36331..9491ecfa8b 100644
--- a/esp32p4/src/efuse/rd_key4_data7.rs
+++ b/esp32p4/src/efuse/rd_key4_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA7")
-            .field("key4_data7", &format_args!("{}", self.key4_data7().bits()))
+            .field("key4_data7", &self.key4_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA7_SPEC {
diff --git a/esp32p4/src/efuse/rd_key5_data0.rs b/esp32p4/src/efuse/rd_key5_data0.rs
index 30afd98f27..eaa12eb5b5 100644
--- a/esp32p4/src/efuse/rd_key5_data0.rs
+++ b/esp32p4/src/efuse/rd_key5_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA0")
-            .field("key5_data0", &format_args!("{}", self.key5_data0().bits()))
+            .field("key5_data0", &self.key5_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA0_SPEC {
diff --git a/esp32p4/src/efuse/rd_key5_data1.rs b/esp32p4/src/efuse/rd_key5_data1.rs
index e9dce7e94e..ea2b0c5c93 100644
--- a/esp32p4/src/efuse/rd_key5_data1.rs
+++ b/esp32p4/src/efuse/rd_key5_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA1")
-            .field("key5_data1", &format_args!("{}", self.key5_data1().bits()))
+            .field("key5_data1", &self.key5_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA1_SPEC {
diff --git a/esp32p4/src/efuse/rd_key5_data2.rs b/esp32p4/src/efuse/rd_key5_data2.rs
index c689437cdc..f2ea02e234 100644
--- a/esp32p4/src/efuse/rd_key5_data2.rs
+++ b/esp32p4/src/efuse/rd_key5_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA2")
-            .field("key5_data2", &format_args!("{}", self.key5_data2().bits()))
+            .field("key5_data2", &self.key5_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA2_SPEC {
diff --git a/esp32p4/src/efuse/rd_key5_data3.rs b/esp32p4/src/efuse/rd_key5_data3.rs
index bca91c9d37..68a0f3034f 100644
--- a/esp32p4/src/efuse/rd_key5_data3.rs
+++ b/esp32p4/src/efuse/rd_key5_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA3")
-            .field("key5_data3", &format_args!("{}", self.key5_data3().bits()))
+            .field("key5_data3", &self.key5_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA3_SPEC {
diff --git a/esp32p4/src/efuse/rd_key5_data4.rs b/esp32p4/src/efuse/rd_key5_data4.rs
index f3ad10e5b8..9658e4f4b8 100644
--- a/esp32p4/src/efuse/rd_key5_data4.rs
+++ b/esp32p4/src/efuse/rd_key5_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA4")
-            .field("key5_data4", &format_args!("{}", self.key5_data4().bits()))
+            .field("key5_data4", &self.key5_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA4_SPEC {
diff --git a/esp32p4/src/efuse/rd_key5_data5.rs b/esp32p4/src/efuse/rd_key5_data5.rs
index 6d7123a48c..29d27d1c31 100644
--- a/esp32p4/src/efuse/rd_key5_data5.rs
+++ b/esp32p4/src/efuse/rd_key5_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA5")
-            .field("key5_data5", &format_args!("{}", self.key5_data5().bits()))
+            .field("key5_data5", &self.key5_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA5_SPEC {
diff --git a/esp32p4/src/efuse/rd_key5_data6.rs b/esp32p4/src/efuse/rd_key5_data6.rs
index d24ecae9af..cf5b5a4e0a 100644
--- a/esp32p4/src/efuse/rd_key5_data6.rs
+++ b/esp32p4/src/efuse/rd_key5_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA6")
-            .field("key5_data6", &format_args!("{}", self.key5_data6().bits()))
+            .field("key5_data6", &self.key5_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA6_SPEC {
diff --git a/esp32p4/src/efuse/rd_key5_data7.rs b/esp32p4/src/efuse/rd_key5_data7.rs
index 493d96b395..d22882be6d 100644
--- a/esp32p4/src/efuse/rd_key5_data7.rs
+++ b/esp32p4/src/efuse/rd_key5_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA7")
-            .field("key5_data7", &format_args!("{}", self.key5_data7().bits()))
+            .field("key5_data7", &self.key5_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA7_SPEC {
diff --git a/esp32p4/src/efuse/rd_mac_sys_0.rs b/esp32p4/src/efuse/rd_mac_sys_0.rs
index 2cdbd542b8..da3c646e9f 100644
--- a/esp32p4/src/efuse/rd_mac_sys_0.rs
+++ b/esp32p4/src/efuse/rd_mac_sys_0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SYS_0")
-            .field("mac_0", &format_args!("{}", self.mac_0().bits()))
+            .field("mac_0", &self.mac_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SYS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SYS_0_SPEC;
 impl crate::RegisterSpec for RD_MAC_SYS_0_SPEC {
diff --git a/esp32p4/src/efuse/rd_mac_sys_1.rs b/esp32p4/src/efuse/rd_mac_sys_1.rs
index adb9c73fc3..0e9b75a9f9 100644
--- a/esp32p4/src/efuse/rd_mac_sys_1.rs
+++ b/esp32p4/src/efuse/rd_mac_sys_1.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SYS_1")
-            .field("mac_1", &format_args!("{}", self.mac_1().bits()))
-            .field("mac_ext", &format_args!("{}", self.mac_ext().bits()))
+            .field("mac_1", &self.mac_1())
+            .field("mac_ext", &self.mac_ext())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SYS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SYS_1_SPEC;
 impl crate::RegisterSpec for RD_MAC_SYS_1_SPEC {
diff --git a/esp32p4/src/efuse/rd_mac_sys_2.rs b/esp32p4/src/efuse/rd_mac_sys_2.rs
index 541053c51b..aa28e99c89 100644
--- a/esp32p4/src/efuse/rd_mac_sys_2.rs
+++ b/esp32p4/src/efuse/rd_mac_sys_2.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SYS_2")
-            .field(
-                "mac_reserved_1",
-                &format_args!("{}", self.mac_reserved_1().bits()),
-            )
-            .field(
-                "mac_reserved_0",
-                &format_args!("{}", self.mac_reserved_0().bits()),
-            )
+            .field("mac_reserved_1", &self.mac_reserved_1())
+            .field("mac_reserved_0", &self.mac_reserved_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SYS_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SYS_2_SPEC;
 impl crate::RegisterSpec for RD_MAC_SYS_2_SPEC {
diff --git a/esp32p4/src/efuse/rd_mac_sys_3.rs b/esp32p4/src/efuse/rd_mac_sys_3.rs
index bef94cd671..b5190cbb38 100644
--- a/esp32p4/src/efuse/rd_mac_sys_3.rs
+++ b/esp32p4/src/efuse/rd_mac_sys_3.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SYS_3")
-            .field(
-                "mac_reserved_2",
-                &format_args!("{}", self.mac_reserved_2().bits()),
-            )
-            .field(
-                "sys_data_part0_0",
-                &format_args!("{}", self.sys_data_part0_0().bits()),
-            )
+            .field("mac_reserved_2", &self.mac_reserved_2())
+            .field("sys_data_part0_0", &self.sys_data_part0_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SYS_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SYS_3_SPEC;
 impl crate::RegisterSpec for RD_MAC_SYS_3_SPEC {
diff --git a/esp32p4/src/efuse/rd_mac_sys_4.rs b/esp32p4/src/efuse/rd_mac_sys_4.rs
index 81106abfab..dc617221e2 100644
--- a/esp32p4/src/efuse/rd_mac_sys_4.rs
+++ b/esp32p4/src/efuse/rd_mac_sys_4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SYS_4")
-            .field(
-                "sys_data_part0_1",
-                &format_args!("{}", self.sys_data_part0_1().bits()),
-            )
+            .field("sys_data_part0_1", &self.sys_data_part0_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SYS_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SYS_4_SPEC;
 impl crate::RegisterSpec for RD_MAC_SYS_4_SPEC {
diff --git a/esp32p4/src/efuse/rd_mac_sys_5.rs b/esp32p4/src/efuse/rd_mac_sys_5.rs
index 643e48e480..a3ff86e6f6 100644
--- a/esp32p4/src/efuse/rd_mac_sys_5.rs
+++ b/esp32p4/src/efuse/rd_mac_sys_5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SYS_5")
-            .field(
-                "sys_data_part0_2",
-                &format_args!("{}", self.sys_data_part0_2().bits()),
-            )
+            .field("sys_data_part0_2", &self.sys_data_part0_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SYS_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register $n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_sys_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SYS_5_SPEC;
 impl crate::RegisterSpec for RD_MAC_SYS_5_SPEC {
diff --git a/esp32p4/src/efuse/rd_repeat_data0.rs b/esp32p4/src/efuse/rd_repeat_data0.rs
index 4b75ce63de..281daa46db 100644
--- a/esp32p4/src/efuse/rd_repeat_data0.rs
+++ b/esp32p4/src/efuse/rd_repeat_data0.rs
@@ -125,74 +125,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA0")
-            .field("rd_dis", &format_args!("{}", self.rd_dis().bits()))
-            .field(
-                "usb_device_exchg_pins",
-                &format_args!("{}", self.usb_device_exchg_pins().bit()),
-            )
-            .field(
-                "usb_otg11_exchg_pins",
-                &format_args!("{}", self.usb_otg11_exchg_pins().bit()),
-            )
-            .field(
-                "dis_usb_jtag",
-                &format_args!("{}", self.dis_usb_jtag().bit()),
-            )
-            .field(
-                "powerglitch_en",
-                &format_args!("{}", self.powerglitch_en().bit()),
-            )
-            .field(
-                "dis_usb_serial_jtag",
-                &format_args!("{}", self.dis_usb_serial_jtag().bit()),
-            )
-            .field(
-                "dis_force_download",
-                &format_args!("{}", self.dis_force_download().bit()),
-            )
-            .field(
-                "spi_download_mspi_dis",
-                &format_args!("{}", self.spi_download_mspi_dis().bit()),
-            )
-            .field("dis_twai", &format_args!("{}", self.dis_twai().bit()))
-            .field(
-                "jtag_sel_enable",
-                &format_args!("{}", self.jtag_sel_enable().bit()),
-            )
-            .field(
-                "soft_dis_jtag",
-                &format_args!("{}", self.soft_dis_jtag().bits()),
-            )
-            .field(
-                "dis_pad_jtag",
-                &format_args!("{}", self.dis_pad_jtag().bit()),
-            )
+            .field("rd_dis", &self.rd_dis())
+            .field("usb_device_exchg_pins", &self.usb_device_exchg_pins())
+            .field("usb_otg11_exchg_pins", &self.usb_otg11_exchg_pins())
+            .field("dis_usb_jtag", &self.dis_usb_jtag())
+            .field("powerglitch_en", &self.powerglitch_en())
+            .field("dis_usb_serial_jtag", &self.dis_usb_serial_jtag())
+            .field("dis_force_download", &self.dis_force_download())
+            .field("spi_download_mspi_dis", &self.spi_download_mspi_dis())
+            .field("dis_twai", &self.dis_twai())
+            .field("jtag_sel_enable", &self.jtag_sel_enable())
+            .field("soft_dis_jtag", &self.soft_dis_jtag())
+            .field("dis_pad_jtag", &self.dis_pad_jtag())
             .field(
                 "dis_download_manual_encrypt",
-                &format_args!("{}", self.dis_download_manual_encrypt().bit()),
-            )
-            .field(
-                "usb_device_drefh",
-                &format_args!("{}", self.usb_device_drefh().bits()),
-            )
-            .field(
-                "usb_otg11_drefh",
-                &format_args!("{}", self.usb_otg11_drefh().bits()),
-            )
-            .field("usb_phy_sel", &format_args!("{}", self.usb_phy_sel().bit()))
-            .field(
-                "km_huk_gen_state_low",
-                &format_args!("{}", self.km_huk_gen_state_low().bits()),
+                &self.dis_download_manual_encrypt(),
             )
+            .field("usb_device_drefh", &self.usb_device_drefh())
+            .field("usb_otg11_drefh", &self.usb_otg11_drefh())
+            .field("usb_phy_sel", &self.usb_phy_sel())
+            .field("km_huk_gen_state_low", &self.km_huk_gen_state_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA0_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA0_SPEC {
diff --git a/esp32p4/src/efuse/rd_repeat_data1.rs b/esp32p4/src/efuse/rd_repeat_data1.rs
index 58a9c6cceb..9c41bd47f5 100644
--- a/esp32p4/src/efuse/rd_repeat_data1.rs
+++ b/esp32p4/src/efuse/rd_repeat_data1.rs
@@ -97,67 +97,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA1")
-            .field(
-                "km_huk_gen_state_high",
-                &format_args!("{}", self.km_huk_gen_state_high().bits()),
-            )
-            .field(
-                "km_rnd_switch_cycle",
-                &format_args!("{}", self.km_rnd_switch_cycle().bits()),
-            )
-            .field(
-                "km_deploy_only_once",
-                &format_args!("{}", self.km_deploy_only_once().bits()),
-            )
+            .field("km_huk_gen_state_high", &self.km_huk_gen_state_high())
+            .field("km_rnd_switch_cycle", &self.km_rnd_switch_cycle())
+            .field("km_deploy_only_once", &self.km_deploy_only_once())
             .field(
                 "force_use_key_manager_key",
-                &format_args!("{}", self.force_use_key_manager_key().bits()),
+                &self.force_use_key_manager_key(),
             )
             .field(
                 "force_disable_sw_init_key",
-                &format_args!("{}", self.force_disable_sw_init_key().bit()),
-            )
-            .field(
-                "xts_key_length_256",
-                &format_args!("{}", self.xts_key_length_256().bit()),
-            )
-            .field(
-                "wdt_delay_sel",
-                &format_args!("{}", self.wdt_delay_sel().bits()),
-            )
-            .field(
-                "spi_boot_crypt_cnt",
-                &format_args!("{}", self.spi_boot_crypt_cnt().bits()),
-            )
-            .field(
-                "secure_boot_key_revoke0",
-                &format_args!("{}", self.secure_boot_key_revoke0().bit()),
-            )
-            .field(
-                "secure_boot_key_revoke1",
-                &format_args!("{}", self.secure_boot_key_revoke1().bit()),
-            )
-            .field(
-                "secure_boot_key_revoke2",
-                &format_args!("{}", self.secure_boot_key_revoke2().bit()),
-            )
-            .field(
-                "key_purpose_0",
-                &format_args!("{}", self.key_purpose_0().bits()),
-            )
-            .field(
-                "key_purpose_1",
-                &format_args!("{}", self.key_purpose_1().bits()),
+                &self.force_disable_sw_init_key(),
             )
+            .field("xts_key_length_256", &self.xts_key_length_256())
+            .field("wdt_delay_sel", &self.wdt_delay_sel())
+            .field("spi_boot_crypt_cnt", &self.spi_boot_crypt_cnt())
+            .field("secure_boot_key_revoke0", &self.secure_boot_key_revoke0())
+            .field("secure_boot_key_revoke1", &self.secure_boot_key_revoke1())
+            .field("secure_boot_key_revoke2", &self.secure_boot_key_revoke2())
+            .field("key_purpose_0", &self.key_purpose_0())
+            .field("key_purpose_1", &self.key_purpose_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA1_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA1_SPEC {
diff --git a/esp32p4/src/efuse/rd_repeat_data2.rs b/esp32p4/src/efuse/rd_repeat_data2.rs
index 9cac53f59e..528ce0d2db 100644
--- a/esp32p4/src/efuse/rd_repeat_data2.rs
+++ b/esp32p4/src/efuse/rd_repeat_data2.rs
@@ -104,65 +104,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA2")
-            .field(
-                "key_purpose_2",
-                &format_args!("{}", self.key_purpose_2().bits()),
-            )
-            .field(
-                "key_purpose_3",
-                &format_args!("{}", self.key_purpose_3().bits()),
-            )
-            .field(
-                "key_purpose_4",
-                &format_args!("{}", self.key_purpose_4().bits()),
-            )
-            .field(
-                "key_purpose_5",
-                &format_args!("{}", self.key_purpose_5().bits()),
-            )
-            .field(
-                "sec_dpa_level",
-                &format_args!("{}", self.sec_dpa_level().bits()),
-            )
-            .field(
-                "ecdsa_enable_soft_k",
-                &format_args!("{}", self.ecdsa_enable_soft_k().bit()),
-            )
-            .field(
-                "crypt_dpa_enable",
-                &format_args!("{}", self.crypt_dpa_enable().bit()),
-            )
-            .field(
-                "secure_boot_en",
-                &format_args!("{}", self.secure_boot_en().bit()),
-            )
+            .field("key_purpose_2", &self.key_purpose_2())
+            .field("key_purpose_3", &self.key_purpose_3())
+            .field("key_purpose_4", &self.key_purpose_4())
+            .field("key_purpose_5", &self.key_purpose_5())
+            .field("sec_dpa_level", &self.sec_dpa_level())
+            .field("ecdsa_enable_soft_k", &self.ecdsa_enable_soft_k())
+            .field("crypt_dpa_enable", &self.crypt_dpa_enable())
+            .field("secure_boot_en", &self.secure_boot_en())
             .field(
                 "secure_boot_aggressive_revoke",
-                &format_args!("{}", self.secure_boot_aggressive_revoke().bit()),
-            )
-            .field("flash_type", &format_args!("{}", self.flash_type().bit()))
-            .field(
-                "flash_page_size",
-                &format_args!("{}", self.flash_page_size().bits()),
-            )
-            .field(
-                "flash_ecc_en",
-                &format_args!("{}", self.flash_ecc_en().bit()),
+                &self.secure_boot_aggressive_revoke(),
             )
+            .field("flash_type", &self.flash_type())
+            .field("flash_page_size", &self.flash_page_size())
+            .field("flash_ecc_en", &self.flash_ecc_en())
             .field(
                 "dis_usb_otg_download_mode",
-                &format_args!("{}", self.dis_usb_otg_download_mode().bit()),
+                &self.dis_usb_otg_download_mode(),
             )
-            .field("flash_tpuw", &format_args!("{}", self.flash_tpuw().bits()))
+            .field("flash_tpuw", &self.flash_tpuw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA2_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA2_SPEC {
diff --git a/esp32p4/src/efuse/rd_repeat_data3.rs b/esp32p4/src/efuse/rd_repeat_data3.rs
index 7f2ac830e4..f6da86782b 100644
--- a/esp32p4/src/efuse/rd_repeat_data3.rs
+++ b/esp32p4/src/efuse/rd_repeat_data3.rs
@@ -90,54 +90,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA3")
-            .field(
-                "dis_download_mode",
-                &format_args!("{}", self.dis_download_mode().bit()),
-            )
-            .field(
-                "dis_direct_boot",
-                &format_args!("{}", self.dis_direct_boot().bit()),
-            )
+            .field("dis_download_mode", &self.dis_download_mode())
+            .field("dis_direct_boot", &self.dis_direct_boot())
             .field(
                 "dis_usb_serial_jtag_rom_print",
-                &format_args!("{}", self.dis_usb_serial_jtag_rom_print().bit()),
+                &self.dis_usb_serial_jtag_rom_print(),
             )
-            .field("lock_km_key", &format_args!("{}", self.lock_km_key().bit()))
+            .field("lock_km_key", &self.lock_km_key())
             .field(
                 "dis_usb_serial_jtag_download_mode",
-                &format_args!("{}", self.dis_usb_serial_jtag_download_mode().bit()),
-            )
-            .field(
-                "enable_security_download",
-                &format_args!("{}", self.enable_security_download().bit()),
-            )
-            .field(
-                "uart_print_control",
-                &format_args!("{}", self.uart_print_control().bits()),
-            )
-            .field(
-                "force_send_resume",
-                &format_args!("{}", self.force_send_resume().bit()),
-            )
-            .field(
-                "secure_version",
-                &format_args!("{}", self.secure_version().bits()),
+                &self.dis_usb_serial_jtag_download_mode(),
             )
+            .field("enable_security_download", &self.enable_security_download())
+            .field("uart_print_control", &self.uart_print_control())
+            .field("force_send_resume", &self.force_send_resume())
+            .field("secure_version", &self.secure_version())
             .field(
                 "secure_boot_disable_fast_wake",
-                &format_args!("{}", self.secure_boot_disable_fast_wake().bit()),
+                &self.secure_boot_disable_fast_wake(),
             )
-            .field("hys_en_pad", &format_args!("{}", self.hys_en_pad().bit()))
-            .field("dcdc_vset", &format_args!("{}", self.dcdc_vset().bits()))
+            .field("hys_en_pad", &self.hys_en_pad())
+            .field("dcdc_vset", &self.dcdc_vset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA3_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA3_SPEC {
diff --git a/esp32p4/src/efuse/rd_repeat_data4.rs b/esp32p4/src/efuse/rd_repeat_data4.rs
index 9652a10615..b913344fc7 100644
--- a/esp32p4/src/efuse/rd_repeat_data4.rs
+++ b/esp32p4/src/efuse/rd_repeat_data4.rs
@@ -83,53 +83,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA4")
-            .field(
-                "_0pxa_tieh_sel_0",
-                &format_args!("{}", self._0pxa_tieh_sel_0().bits()),
-            )
-            .field(
-                "_0pxa_tieh_sel_1",
-                &format_args!("{}", self._0pxa_tieh_sel_1().bits()),
-            )
-            .field(
-                "_0pxa_tieh_sel_2",
-                &format_args!("{}", self._0pxa_tieh_sel_2().bits()),
-            )
-            .field(
-                "_0pxa_tieh_sel_3",
-                &format_args!("{}", self._0pxa_tieh_sel_3().bits()),
-            )
-            .field(
-                "km_disable_deploy_mode",
-                &format_args!("{}", self.km_disable_deploy_mode().bits()),
-            )
-            .field(
-                "usb_device_drefl",
-                &format_args!("{}", self.usb_device_drefl().bits()),
-            )
-            .field(
-                "usb_otg11_drefl",
-                &format_args!("{}", self.usb_otg11_drefl().bits()),
-            )
-            .field(
-                "hp_pwr_src_sel",
-                &format_args!("{}", self.hp_pwr_src_sel().bit()),
-            )
-            .field(
-                "dcdc_vset_en",
-                &format_args!("{}", self.dcdc_vset_en().bit()),
-            )
-            .field("dis_wdt", &format_args!("{}", self.dis_wdt().bit()))
-            .field("dis_swd", &format_args!("{}", self.dis_swd().bit()))
+            .field("_0pxa_tieh_sel_0", &self._0pxa_tieh_sel_0())
+            .field("_0pxa_tieh_sel_1", &self._0pxa_tieh_sel_1())
+            .field("_0pxa_tieh_sel_2", &self._0pxa_tieh_sel_2())
+            .field("_0pxa_tieh_sel_3", &self._0pxa_tieh_sel_3())
+            .field("km_disable_deploy_mode", &self.km_disable_deploy_mode())
+            .field("usb_device_drefl", &self.usb_device_drefl())
+            .field("usb_otg11_drefl", &self.usb_otg11_drefl())
+            .field("hp_pwr_src_sel", &self.hp_pwr_src_sel())
+            .field("dcdc_vset_en", &self.dcdc_vset_en())
+            .field("dis_wdt", &self.dis_wdt())
+            .field("dis_swd", &self.dis_swd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA4_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA4_SPEC {
diff --git a/esp32p4/src/efuse/rd_repeat_err0.rs b/esp32p4/src/efuse/rd_repeat_err0.rs
index 3c213aacc4..2a74c15801 100644
--- a/esp32p4/src/efuse/rd_repeat_err0.rs
+++ b/esp32p4/src/efuse/rd_repeat_err0.rs
@@ -125,80 +125,38 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR0")
-            .field("rd_dis_err", &format_args!("{}", self.rd_dis_err().bits()))
+            .field("rd_dis_err", &self.rd_dis_err())
             .field(
                 "dis_usb_device_exchg_pins_err",
-                &format_args!("{}", self.dis_usb_device_exchg_pins_err().bit()),
+                &self.dis_usb_device_exchg_pins_err(),
             )
             .field(
                 "dis_usb_otg11_exchg_pins_err",
-                &format_args!("{}", self.dis_usb_otg11_exchg_pins_err().bit()),
-            )
-            .field(
-                "dis_usb_jtag_err",
-                &format_args!("{}", self.dis_usb_jtag_err().bit()),
-            )
-            .field(
-                "powerglitch_en_err",
-                &format_args!("{}", self.powerglitch_en_err().bit()),
-            )
-            .field(
-                "dis_usb_serial_jtag_err",
-                &format_args!("{}", self.dis_usb_serial_jtag_err().bit()),
-            )
-            .field(
-                "dis_force_download_err",
-                &format_args!("{}", self.dis_force_download_err().bit()),
+                &self.dis_usb_otg11_exchg_pins_err(),
             )
+            .field("dis_usb_jtag_err", &self.dis_usb_jtag_err())
+            .field("powerglitch_en_err", &self.powerglitch_en_err())
+            .field("dis_usb_serial_jtag_err", &self.dis_usb_serial_jtag_err())
+            .field("dis_force_download_err", &self.dis_force_download_err())
             .field(
                 "spi_download_mspi_dis_err",
-                &format_args!("{}", self.spi_download_mspi_dis_err().bit()),
-            )
-            .field(
-                "dis_twai_err",
-                &format_args!("{}", self.dis_twai_err().bit()),
-            )
-            .field(
-                "jtag_sel_enable_err",
-                &format_args!("{}", self.jtag_sel_enable_err().bit()),
-            )
-            .field(
-                "soft_dis_jtag_err",
-                &format_args!("{}", self.soft_dis_jtag_err().bits()),
-            )
-            .field(
-                "dis_pad_jtag_err",
-                &format_args!("{}", self.dis_pad_jtag_err().bit()),
+                &self.spi_download_mspi_dis_err(),
             )
+            .field("dis_twai_err", &self.dis_twai_err())
+            .field("jtag_sel_enable_err", &self.jtag_sel_enable_err())
+            .field("soft_dis_jtag_err", &self.soft_dis_jtag_err())
+            .field("dis_pad_jtag_err", &self.dis_pad_jtag_err())
             .field(
                 "dis_download_manual_encrypt_err",
-                &format_args!("{}", self.dis_download_manual_encrypt_err().bit()),
-            )
-            .field(
-                "usb_device_drefh_err",
-                &format_args!("{}", self.usb_device_drefh_err().bits()),
-            )
-            .field(
-                "usb_otg11_drefh_err",
-                &format_args!("{}", self.usb_otg11_drefh_err().bits()),
-            )
-            .field(
-                "usb_phy_sel_err",
-                &format_args!("{}", self.usb_phy_sel_err().bit()),
-            )
-            .field(
-                "huk_gen_state_low_err",
-                &format_args!("{}", self.huk_gen_state_low_err().bits()),
+                &self.dis_download_manual_encrypt_err(),
             )
+            .field("usb_device_drefh_err", &self.usb_device_drefh_err())
+            .field("usb_otg11_drefh_err", &self.usb_otg11_drefh_err())
+            .field("usb_phy_sel_err", &self.usb_phy_sel_err())
+            .field("huk_gen_state_low_err", &self.huk_gen_state_low_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 0 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR0_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR0_SPEC {
diff --git a/esp32p4/src/efuse/rd_repeat_err1.rs b/esp32p4/src/efuse/rd_repeat_err1.rs
index 78cedaf89b..f04e98f250 100644
--- a/esp32p4/src/efuse/rd_repeat_err1.rs
+++ b/esp32p4/src/efuse/rd_repeat_err1.rs
@@ -99,65 +99,38 @@ impl core::fmt::Debug for R {
         f.debug_struct("RD_REPEAT_ERR1")
             .field(
                 "km_huk_gen_state_high_err",
-                &format_args!("{}", self.km_huk_gen_state_high_err().bits()),
-            )
-            .field(
-                "km_rnd_switch_cycle_err",
-                &format_args!("{}", self.km_rnd_switch_cycle_err().bits()),
-            )
-            .field(
-                "km_deploy_only_once_err",
-                &format_args!("{}", self.km_deploy_only_once_err().bits()),
+                &self.km_huk_gen_state_high_err(),
             )
+            .field("km_rnd_switch_cycle_err", &self.km_rnd_switch_cycle_err())
+            .field("km_deploy_only_once_err", &self.km_deploy_only_once_err())
             .field(
                 "force_use_key_manager_key_err",
-                &format_args!("{}", self.force_use_key_manager_key_err().bits()),
+                &self.force_use_key_manager_key_err(),
             )
             .field(
                 "force_disable_sw_init_key_err",
-                &format_args!("{}", self.force_disable_sw_init_key_err().bit()),
-            )
-            .field(
-                "xts_key_length_256_err",
-                &format_args!("{}", self.xts_key_length_256_err().bit()),
-            )
-            .field(
-                "wdt_delay_sel_err",
-                &format_args!("{}", self.wdt_delay_sel_err().bits()),
-            )
-            .field(
-                "spi_boot_crypt_cnt_err",
-                &format_args!("{}", self.spi_boot_crypt_cnt_err().bits()),
+                &self.force_disable_sw_init_key_err(),
             )
+            .field("xts_key_length_256_err", &self.xts_key_length_256_err())
+            .field("wdt_delay_sel_err", &self.wdt_delay_sel_err())
+            .field("spi_boot_crypt_cnt_err", &self.spi_boot_crypt_cnt_err())
             .field(
                 "secure_boot_key_revoke0_err",
-                &format_args!("{}", self.secure_boot_key_revoke0_err().bit()),
+                &self.secure_boot_key_revoke0_err(),
             )
             .field(
                 "secure_boot_key_revoke1_err",
-                &format_args!("{}", self.secure_boot_key_revoke1_err().bit()),
+                &self.secure_boot_key_revoke1_err(),
             )
             .field(
                 "secure_boot_key_revoke2_err",
-                &format_args!("{}", self.secure_boot_key_revoke2_err().bit()),
-            )
-            .field(
-                "key_purpose_0_err",
-                &format_args!("{}", self.key_purpose_0_err().bits()),
-            )
-            .field(
-                "key_purpose_1_err",
-                &format_args!("{}", self.key_purpose_1_err().bits()),
+                &self.secure_boot_key_revoke2_err(),
             )
+            .field("key_purpose_0_err", &self.key_purpose_0_err())
+            .field("key_purpose_1_err", &self.key_purpose_1_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 1 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR1_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR1_SPEC {
diff --git a/esp32p4/src/efuse/rd_repeat_err2.rs b/esp32p4/src/efuse/rd_repeat_err2.rs
index bf31933110..81862e0941 100644
--- a/esp32p4/src/efuse/rd_repeat_err2.rs
+++ b/esp32p4/src/efuse/rd_repeat_err2.rs
@@ -104,71 +104,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR2")
-            .field(
-                "key_purpose_2_err",
-                &format_args!("{}", self.key_purpose_2_err().bits()),
-            )
-            .field(
-                "key_purpose_3_err",
-                &format_args!("{}", self.key_purpose_3_err().bits()),
-            )
-            .field(
-                "key_purpose_4_err",
-                &format_args!("{}", self.key_purpose_4_err().bits()),
-            )
-            .field(
-                "key_purpose_5_err",
-                &format_args!("{}", self.key_purpose_5_err().bits()),
-            )
-            .field(
-                "sec_dpa_level_err",
-                &format_args!("{}", self.sec_dpa_level_err().bits()),
-            )
-            .field(
-                "ecdsa_enable_soft_k_err",
-                &format_args!("{}", self.ecdsa_enable_soft_k_err().bit()),
-            )
-            .field(
-                "crypt_dpa_enable_err",
-                &format_args!("{}", self.crypt_dpa_enable_err().bit()),
-            )
-            .field(
-                "secure_boot_en_err",
-                &format_args!("{}", self.secure_boot_en_err().bit()),
-            )
+            .field("key_purpose_2_err", &self.key_purpose_2_err())
+            .field("key_purpose_3_err", &self.key_purpose_3_err())
+            .field("key_purpose_4_err", &self.key_purpose_4_err())
+            .field("key_purpose_5_err", &self.key_purpose_5_err())
+            .field("sec_dpa_level_err", &self.sec_dpa_level_err())
+            .field("ecdsa_enable_soft_k_err", &self.ecdsa_enable_soft_k_err())
+            .field("crypt_dpa_enable_err", &self.crypt_dpa_enable_err())
+            .field("secure_boot_en_err", &self.secure_boot_en_err())
             .field(
                 "secure_boot_aggressive_revoke_err",
-                &format_args!("{}", self.secure_boot_aggressive_revoke_err().bit()),
-            )
-            .field(
-                "flash_type_err",
-                &format_args!("{}", self.flash_type_err().bit()),
-            )
-            .field(
-                "flash_page_size_err",
-                &format_args!("{}", self.flash_page_size_err().bits()),
-            )
-            .field(
-                "flash_ecc_en_err",
-                &format_args!("{}", self.flash_ecc_en_err().bit()),
+                &self.secure_boot_aggressive_revoke_err(),
             )
+            .field("flash_type_err", &self.flash_type_err())
+            .field("flash_page_size_err", &self.flash_page_size_err())
+            .field("flash_ecc_en_err", &self.flash_ecc_en_err())
             .field(
                 "dis_usb_otg_download_mode_err",
-                &format_args!("{}", self.dis_usb_otg_download_mode_err().bit()),
-            )
-            .field(
-                "flash_tpuw_err",
-                &format_args!("{}", self.flash_tpuw_err().bits()),
+                &self.dis_usb_otg_download_mode_err(),
             )
+            .field("flash_tpuw_err", &self.flash_tpuw_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 2 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR2_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR2_SPEC {
diff --git a/esp32p4/src/efuse/rd_repeat_err3.rs b/esp32p4/src/efuse/rd_repeat_err3.rs
index 6d665d5f05..74e4581ff5 100644
--- a/esp32p4/src/efuse/rd_repeat_err3.rs
+++ b/esp32p4/src/efuse/rd_repeat_err3.rs
@@ -90,63 +90,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR3")
-            .field(
-                "dis_download_mode_err",
-                &format_args!("{}", self.dis_download_mode_err().bit()),
-            )
-            .field(
-                "dis_direct_boot_err",
-                &format_args!("{}", self.dis_direct_boot_err().bit()),
-            )
+            .field("dis_download_mode_err", &self.dis_download_mode_err())
+            .field("dis_direct_boot_err", &self.dis_direct_boot_err())
             .field(
                 "dis_usb_serial_jtag_rom_print_err",
-                &format_args!("{}", self.dis_usb_serial_jtag_rom_print_err().bit()),
-            )
-            .field(
-                "lock_km_key_err",
-                &format_args!("{}", self.lock_km_key_err().bit()),
+                &self.dis_usb_serial_jtag_rom_print_err(),
             )
+            .field("lock_km_key_err", &self.lock_km_key_err())
             .field(
                 "dis_usb_serial_jtag_download_mode_err",
-                &format_args!("{}", self.dis_usb_serial_jtag_download_mode_err().bit()),
+                &self.dis_usb_serial_jtag_download_mode_err(),
             )
             .field(
                 "enable_security_download_err",
-                &format_args!("{}", self.enable_security_download_err().bit()),
-            )
-            .field(
-                "uart_print_control_err",
-                &format_args!("{}", self.uart_print_control_err().bits()),
-            )
-            .field(
-                "force_send_resume_err",
-                &format_args!("{}", self.force_send_resume_err().bit()),
-            )
-            .field(
-                "secure_version_err",
-                &format_args!("{}", self.secure_version_err().bits()),
+                &self.enable_security_download_err(),
             )
+            .field("uart_print_control_err", &self.uart_print_control_err())
+            .field("force_send_resume_err", &self.force_send_resume_err())
+            .field("secure_version_err", &self.secure_version_err())
             .field(
                 "secure_boot_disable_fast_wake_err",
-                &format_args!("{}", self.secure_boot_disable_fast_wake_err().bit()),
-            )
-            .field(
-                "hys_en_pad_err",
-                &format_args!("{}", self.hys_en_pad_err().bit()),
-            )
-            .field(
-                "dcdc_vset_err",
-                &format_args!("{}", self.dcdc_vset_err().bits()),
+                &self.secure_boot_disable_fast_wake_err(),
             )
+            .field("hys_en_pad_err", &self.hys_en_pad_err())
+            .field("dcdc_vset_err", &self.dcdc_vset_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 3 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR3_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR3_SPEC {
diff --git a/esp32p4/src/efuse/rd_repeat_err4.rs b/esp32p4/src/efuse/rd_repeat_err4.rs
index b63092b1be..f227205735 100644
--- a/esp32p4/src/efuse/rd_repeat_err4.rs
+++ b/esp32p4/src/efuse/rd_repeat_err4.rs
@@ -83,53 +83,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR4")
-            .field(
-                "_0pxa_tieh_sel_0_err",
-                &format_args!("{}", self._0pxa_tieh_sel_0_err().bits()),
-            )
-            .field(
-                "_0pxa_tieh_sel_1_err",
-                &format_args!("{}", self._0pxa_tieh_sel_1_err().bits()),
-            )
-            .field(
-                "_0pxa_tieh_sel_2_err",
-                &format_args!("{}", self._0pxa_tieh_sel_2_err().bits()),
-            )
-            .field(
-                "_0pxa_tieh_sel_3_err",
-                &format_args!("{}", self._0pxa_tieh_sel_3_err().bits()),
-            )
+            .field("_0pxa_tieh_sel_0_err", &self._0pxa_tieh_sel_0_err())
+            .field("_0pxa_tieh_sel_1_err", &self._0pxa_tieh_sel_1_err())
+            .field("_0pxa_tieh_sel_2_err", &self._0pxa_tieh_sel_2_err())
+            .field("_0pxa_tieh_sel_3_err", &self._0pxa_tieh_sel_3_err())
             .field(
                 "km_disable_deploy_mode_err",
-                &format_args!("{}", self.km_disable_deploy_mode_err().bits()),
-            )
-            .field(
-                "usb_device_drefl_err",
-                &format_args!("{}", self.usb_device_drefl_err().bits()),
+                &self.km_disable_deploy_mode_err(),
             )
-            .field(
-                "usb_otg11_drefl_err",
-                &format_args!("{}", self.usb_otg11_drefl_err().bits()),
-            )
-            .field(
-                "hp_pwr_src_sel_err",
-                &format_args!("{}", self.hp_pwr_src_sel_err().bit()),
-            )
-            .field(
-                "dcdc_vset_en_err",
-                &format_args!("{}", self.dcdc_vset_en_err().bit()),
-            )
-            .field("dis_wdt_err", &format_args!("{}", self.dis_wdt_err().bit()))
-            .field("dis_swd_err", &format_args!("{}", self.dis_swd_err().bit()))
+            .field("usb_device_drefl_err", &self.usb_device_drefl_err())
+            .field("usb_otg11_drefl_err", &self.usb_otg11_drefl_err())
+            .field("hp_pwr_src_sel_err", &self.hp_pwr_src_sel_err())
+            .field("dcdc_vset_en_err", &self.dcdc_vset_en_err())
+            .field("dis_wdt_err", &self.dis_wdt_err())
+            .field("dis_swd_err", &self.dis_swd_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 4 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR4_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR4_SPEC {
diff --git a/esp32p4/src/efuse/rd_rs_err0.rs b/esp32p4/src/efuse/rd_rs_err0.rs
index 52e1bdd0e0..c5ea147899 100644
--- a/esp32p4/src/efuse/rd_rs_err0.rs
+++ b/esp32p4/src/efuse/rd_rs_err0.rs
@@ -118,64 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_RS_ERR0")
-            .field(
-                "mac_sys_err_num",
-                &format_args!("{}", self.mac_sys_err_num().bits()),
-            )
-            .field(
-                "mac_sys_fail",
-                &format_args!("{}", self.mac_sys_fail().bit()),
-            )
-            .field(
-                "sys_part1_err_num",
-                &format_args!("{}", self.sys_part1_err_num().bits()),
-            )
-            .field(
-                "sys_part1_fail",
-                &format_args!("{}", self.sys_part1_fail().bit()),
-            )
-            .field(
-                "usr_data_err_num",
-                &format_args!("{}", self.usr_data_err_num().bits()),
-            )
-            .field(
-                "usr_data_fail",
-                &format_args!("{}", self.usr_data_fail().bit()),
-            )
-            .field(
-                "key0_err_num",
-                &format_args!("{}", self.key0_err_num().bits()),
-            )
-            .field("key0_fail", &format_args!("{}", self.key0_fail().bit()))
-            .field(
-                "key1_err_num",
-                &format_args!("{}", self.key1_err_num().bits()),
-            )
-            .field("key1_fail", &format_args!("{}", self.key1_fail().bit()))
-            .field(
-                "key2_err_num",
-                &format_args!("{}", self.key2_err_num().bits()),
-            )
-            .field("key2_fail", &format_args!("{}", self.key2_fail().bit()))
-            .field(
-                "key3_err_num",
-                &format_args!("{}", self.key3_err_num().bits()),
-            )
-            .field("key3_fail", &format_args!("{}", self.key3_fail().bit()))
-            .field(
-                "key4_err_num",
-                &format_args!("{}", self.key4_err_num().bits()),
-            )
-            .field("key4_fail", &format_args!("{}", self.key4_fail().bit()))
+            .field("mac_sys_err_num", &self.mac_sys_err_num())
+            .field("mac_sys_fail", &self.mac_sys_fail())
+            .field("sys_part1_err_num", &self.sys_part1_err_num())
+            .field("sys_part1_fail", &self.sys_part1_fail())
+            .field("usr_data_err_num", &self.usr_data_err_num())
+            .field("usr_data_fail", &self.usr_data_fail())
+            .field("key0_err_num", &self.key0_err_num())
+            .field("key0_fail", &self.key0_fail())
+            .field("key1_err_num", &self.key1_err_num())
+            .field("key1_fail", &self.key1_fail())
+            .field("key2_err_num", &self.key2_err_num())
+            .field("key2_fail", &self.key2_fail())
+            .field("key3_err_num", &self.key3_err_num())
+            .field("key3_fail", &self.key3_fail())
+            .field("key4_err_num", &self.key4_err_num())
+            .field("key4_fail", &self.key4_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RS_ERR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 0 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RS_ERR0_SPEC;
 impl crate::RegisterSpec for RD_RS_ERR0_SPEC {
diff --git a/esp32p4/src/efuse/rd_rs_err1.rs b/esp32p4/src/efuse/rd_rs_err1.rs
index 04fe9a9db1..188a8b967f 100644
--- a/esp32p4/src/efuse/rd_rs_err1.rs
+++ b/esp32p4/src/efuse/rd_rs_err1.rs
@@ -34,28 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_RS_ERR1")
-            .field(
-                "key5_err_num",
-                &format_args!("{}", self.key5_err_num().bits()),
-            )
-            .field("key5_fail", &format_args!("{}", self.key5_fail().bit()))
-            .field(
-                "sys_part2_err_num",
-                &format_args!("{}", self.sys_part2_err_num().bits()),
-            )
-            .field(
-                "sys_part2_fail",
-                &format_args!("{}", self.sys_part2_fail().bit()),
-            )
+            .field("key5_err_num", &self.key5_err_num())
+            .field("key5_fail", &self.key5_fail())
+            .field("sys_part2_err_num", &self.sys_part2_err_num())
+            .field("sys_part2_fail", &self.sys_part2_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RS_ERR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 1 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RS_ERR1_SPEC;
 impl crate::RegisterSpec for RD_RS_ERR1_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part1_data0.rs b/esp32p4/src/efuse/rd_sys_part1_data0.rs
index f28c3bd2d0..d6b4a065d4 100644
--- a/esp32p4/src/efuse/rd_sys_part1_data0.rs
+++ b/esp32p4/src/efuse/rd_sys_part1_data0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA0")
-            .field(
-                "sys_data_part1_0",
-                &format_args!("{}", self.sys_data_part1_0().bits()),
-            )
+            .field("sys_data_part1_0", &self.sys_data_part1_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA0_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA0_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part1_data1.rs b/esp32p4/src/efuse/rd_sys_part1_data1.rs
index c7345ebcfe..aa8b5a77e1 100644
--- a/esp32p4/src/efuse/rd_sys_part1_data1.rs
+++ b/esp32p4/src/efuse/rd_sys_part1_data1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA1")
-            .field(
-                "sys_data_part1_1",
-                &format_args!("{}", self.sys_data_part1_1().bits()),
-            )
+            .field("sys_data_part1_1", &self.sys_data_part1_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA1_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA1_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part1_data2.rs b/esp32p4/src/efuse/rd_sys_part1_data2.rs
index 00d8eee981..6ce86ab9ea 100644
--- a/esp32p4/src/efuse/rd_sys_part1_data2.rs
+++ b/esp32p4/src/efuse/rd_sys_part1_data2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA2")
-            .field(
-                "sys_data_part1_2",
-                &format_args!("{}", self.sys_data_part1_2().bits()),
-            )
+            .field("sys_data_part1_2", &self.sys_data_part1_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA2_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA2_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part1_data3.rs b/esp32p4/src/efuse/rd_sys_part1_data3.rs
index 1025d41a34..f3c8563223 100644
--- a/esp32p4/src/efuse/rd_sys_part1_data3.rs
+++ b/esp32p4/src/efuse/rd_sys_part1_data3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA3")
-            .field(
-                "sys_data_part1_3",
-                &format_args!("{}", self.sys_data_part1_3().bits()),
-            )
+            .field("sys_data_part1_3", &self.sys_data_part1_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA3_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA3_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part1_data4.rs b/esp32p4/src/efuse/rd_sys_part1_data4.rs
index 11e51eb81d..c3a05173b2 100644
--- a/esp32p4/src/efuse/rd_sys_part1_data4.rs
+++ b/esp32p4/src/efuse/rd_sys_part1_data4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA4")
-            .field(
-                "sys_data_part1_4",
-                &format_args!("{}", self.sys_data_part1_4().bits()),
-            )
+            .field("sys_data_part1_4", &self.sys_data_part1_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA4_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA4_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part1_data5.rs b/esp32p4/src/efuse/rd_sys_part1_data5.rs
index f6e08ae404..06e29f147d 100644
--- a/esp32p4/src/efuse/rd_sys_part1_data5.rs
+++ b/esp32p4/src/efuse/rd_sys_part1_data5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA5")
-            .field(
-                "sys_data_part1_5",
-                &format_args!("{}", self.sys_data_part1_5().bits()),
-            )
+            .field("sys_data_part1_5", &self.sys_data_part1_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA5_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA5_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part1_data6.rs b/esp32p4/src/efuse/rd_sys_part1_data6.rs
index 9065b698dc..3fd9b053a9 100644
--- a/esp32p4/src/efuse/rd_sys_part1_data6.rs
+++ b/esp32p4/src/efuse/rd_sys_part1_data6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA6")
-            .field(
-                "sys_data_part1_6",
-                &format_args!("{}", self.sys_data_part1_6().bits()),
-            )
+            .field("sys_data_part1_6", &self.sys_data_part1_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA6_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA6_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part1_data7.rs b/esp32p4/src/efuse/rd_sys_part1_data7.rs
index cacdcd1f63..c87a01c324 100644
--- a/esp32p4/src/efuse/rd_sys_part1_data7.rs
+++ b/esp32p4/src/efuse/rd_sys_part1_data7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA7")
-            .field(
-                "sys_data_part1_7",
-                &format_args!("{}", self.sys_data_part1_7().bits()),
-            )
+            .field("sys_data_part1_7", &self.sys_data_part1_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA7_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA7_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part2_data0.rs b/esp32p4/src/efuse/rd_sys_part2_data0.rs
index 1feb2a9015..47d38ca228 100644
--- a/esp32p4/src/efuse/rd_sys_part2_data0.rs
+++ b/esp32p4/src/efuse/rd_sys_part2_data0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA0")
-            .field(
-                "sys_data_part2_0",
-                &format_args!("{}", self.sys_data_part2_0().bits()),
-            )
+            .field("sys_data_part2_0", &self.sys_data_part2_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA0_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA0_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part2_data1.rs b/esp32p4/src/efuse/rd_sys_part2_data1.rs
index 3d524a829e..52a84368ae 100644
--- a/esp32p4/src/efuse/rd_sys_part2_data1.rs
+++ b/esp32p4/src/efuse/rd_sys_part2_data1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA1")
-            .field(
-                "sys_data_part2_1",
-                &format_args!("{}", self.sys_data_part2_1().bits()),
-            )
+            .field("sys_data_part2_1", &self.sys_data_part2_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA1_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA1_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part2_data2.rs b/esp32p4/src/efuse/rd_sys_part2_data2.rs
index 011eb41ba8..ae963cb031 100644
--- a/esp32p4/src/efuse/rd_sys_part2_data2.rs
+++ b/esp32p4/src/efuse/rd_sys_part2_data2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA2")
-            .field(
-                "sys_data_part2_2",
-                &format_args!("{}", self.sys_data_part2_2().bits()),
-            )
+            .field("sys_data_part2_2", &self.sys_data_part2_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA2_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA2_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part2_data3.rs b/esp32p4/src/efuse/rd_sys_part2_data3.rs
index 68647c349c..a5d4a31845 100644
--- a/esp32p4/src/efuse/rd_sys_part2_data3.rs
+++ b/esp32p4/src/efuse/rd_sys_part2_data3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA3")
-            .field(
-                "sys_data_part2_3",
-                &format_args!("{}", self.sys_data_part2_3().bits()),
-            )
+            .field("sys_data_part2_3", &self.sys_data_part2_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA3_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA3_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part2_data4.rs b/esp32p4/src/efuse/rd_sys_part2_data4.rs
index 23800044fb..4af91484c2 100644
--- a/esp32p4/src/efuse/rd_sys_part2_data4.rs
+++ b/esp32p4/src/efuse/rd_sys_part2_data4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA4")
-            .field(
-                "sys_data_part2_4",
-                &format_args!("{}", self.sys_data_part2_4().bits()),
-            )
+            .field("sys_data_part2_4", &self.sys_data_part2_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA4_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA4_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part2_data5.rs b/esp32p4/src/efuse/rd_sys_part2_data5.rs
index f90b719995..4008d14046 100644
--- a/esp32p4/src/efuse/rd_sys_part2_data5.rs
+++ b/esp32p4/src/efuse/rd_sys_part2_data5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA5")
-            .field(
-                "sys_data_part2_5",
-                &format_args!("{}", self.sys_data_part2_5().bits()),
-            )
+            .field("sys_data_part2_5", &self.sys_data_part2_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA5_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA5_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part2_data6.rs b/esp32p4/src/efuse/rd_sys_part2_data6.rs
index ae9ccbcd43..b9c78c0f10 100644
--- a/esp32p4/src/efuse/rd_sys_part2_data6.rs
+++ b/esp32p4/src/efuse/rd_sys_part2_data6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA6")
-            .field(
-                "sys_data_part2_6",
-                &format_args!("{}", self.sys_data_part2_6().bits()),
-            )
+            .field("sys_data_part2_6", &self.sys_data_part2_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA6_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA6_SPEC {
diff --git a/esp32p4/src/efuse/rd_sys_part2_data7.rs b/esp32p4/src/efuse/rd_sys_part2_data7.rs
index bed90d73b1..3b790bc9a9 100644
--- a/esp32p4/src/efuse/rd_sys_part2_data7.rs
+++ b/esp32p4/src/efuse/rd_sys_part2_data7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA7")
-            .field(
-                "sys_data_part2_7",
-                &format_args!("{}", self.sys_data_part2_7().bits()),
-            )
+            .field("sys_data_part2_7", &self.sys_data_part2_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA7_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA7_SPEC {
diff --git a/esp32p4/src/efuse/rd_tim_conf.rs b/esp32p4/src/efuse/rd_tim_conf.rs
index cf5db0d2ad..0af5a4ac87 100644
--- a/esp32p4/src/efuse/rd_tim_conf.rs
+++ b/esp32p4/src/efuse/rd_tim_conf.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_TIM_CONF")
-            .field("thr_a", &format_args!("{}", self.thr_a().bits()))
-            .field("trd", &format_args!("{}", self.trd().bits()))
-            .field("tsur_a", &format_args!("{}", self.tsur_a().bits()))
-            .field(
-                "read_init_num",
-                &format_args!("{}", self.read_init_num().bits()),
-            )
+            .field("thr_a", &self.thr_a())
+            .field("trd", &self.trd())
+            .field("tsur_a", &self.tsur_a())
+            .field("read_init_num", &self.read_init_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_TIM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures the read hold time."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/rd_usr_data0.rs b/esp32p4/src/efuse/rd_usr_data0.rs
index 4e204bad47..28f2066b68 100644
--- a/esp32p4/src/efuse/rd_usr_data0.rs
+++ b/esp32p4/src/efuse/rd_usr_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA0")
-            .field("usr_data0", &format_args!("{}", self.usr_data0().bits()))
+            .field("usr_data0", &self.usr_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA0_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA0_SPEC {
diff --git a/esp32p4/src/efuse/rd_usr_data1.rs b/esp32p4/src/efuse/rd_usr_data1.rs
index d7c72fc40c..9477844df7 100644
--- a/esp32p4/src/efuse/rd_usr_data1.rs
+++ b/esp32p4/src/efuse/rd_usr_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA1")
-            .field("usr_data1", &format_args!("{}", self.usr_data1().bits()))
+            .field("usr_data1", &self.usr_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA1_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA1_SPEC {
diff --git a/esp32p4/src/efuse/rd_usr_data2.rs b/esp32p4/src/efuse/rd_usr_data2.rs
index 8169877859..aab23fdcd6 100644
--- a/esp32p4/src/efuse/rd_usr_data2.rs
+++ b/esp32p4/src/efuse/rd_usr_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA2")
-            .field("usr_data2", &format_args!("{}", self.usr_data2().bits()))
+            .field("usr_data2", &self.usr_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA2_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA2_SPEC {
diff --git a/esp32p4/src/efuse/rd_usr_data3.rs b/esp32p4/src/efuse/rd_usr_data3.rs
index 287031c261..a60ac76725 100644
--- a/esp32p4/src/efuse/rd_usr_data3.rs
+++ b/esp32p4/src/efuse/rd_usr_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA3")
-            .field("usr_data3", &format_args!("{}", self.usr_data3().bits()))
+            .field("usr_data3", &self.usr_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA3_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA3_SPEC {
diff --git a/esp32p4/src/efuse/rd_usr_data4.rs b/esp32p4/src/efuse/rd_usr_data4.rs
index 59455cc92b..2c176b3b03 100644
--- a/esp32p4/src/efuse/rd_usr_data4.rs
+++ b/esp32p4/src/efuse/rd_usr_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA4")
-            .field("usr_data4", &format_args!("{}", self.usr_data4().bits()))
+            .field("usr_data4", &self.usr_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA4_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA4_SPEC {
diff --git a/esp32p4/src/efuse/rd_usr_data5.rs b/esp32p4/src/efuse/rd_usr_data5.rs
index 497253e518..23dcc42bfc 100644
--- a/esp32p4/src/efuse/rd_usr_data5.rs
+++ b/esp32p4/src/efuse/rd_usr_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA5")
-            .field("usr_data5", &format_args!("{}", self.usr_data5().bits()))
+            .field("usr_data5", &self.usr_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA5_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA5_SPEC {
diff --git a/esp32p4/src/efuse/rd_usr_data6.rs b/esp32p4/src/efuse/rd_usr_data6.rs
index ca48ef1451..3191eb6699 100644
--- a/esp32p4/src/efuse/rd_usr_data6.rs
+++ b/esp32p4/src/efuse/rd_usr_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA6")
-            .field("usr_data6", &format_args!("{}", self.usr_data6().bits()))
+            .field("usr_data6", &self.usr_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA6_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA6_SPEC {
diff --git a/esp32p4/src/efuse/rd_usr_data7.rs b/esp32p4/src/efuse/rd_usr_data7.rs
index 794da1f32e..58df0ecfa5 100644
--- a/esp32p4/src/efuse/rd_usr_data7.rs
+++ b/esp32p4/src/efuse/rd_usr_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA7")
-            .field("usr_data7", &format_args!("{}", self.usr_data7().bits()))
+            .field("usr_data7", &self.usr_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register $n of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA7_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA7_SPEC {
diff --git a/esp32p4/src/efuse/rd_wr_dis.rs b/esp32p4/src/efuse/rd_wr_dis.rs
index cd942a2900..6dc46e09a0 100644
--- a/esp32p4/src/efuse/rd_wr_dis.rs
+++ b/esp32p4/src/efuse/rd_wr_dis.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_WR_DIS")
-            .field("wr_dis", &format_args!("{}", self.wr_dis().bits()))
+            .field("wr_dis", &self.wr_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_WR_DIS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_wr_dis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_WR_DIS_SPEC;
 impl crate::RegisterSpec for RD_WR_DIS_SPEC {
diff --git a/esp32p4/src/efuse/status.rs b/esp32p4/src/efuse/status.rs
index dbb83cbf32..d88a17411d 100644
--- a/esp32p4/src/efuse/status.rs
+++ b/esp32p4/src/efuse/status.rs
@@ -69,42 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field("otp_load_sw", &format_args!("{}", self.otp_load_sw().bit()))
-            .field(
-                "otp_vddq_c_sync2",
-                &format_args!("{}", self.otp_vddq_c_sync2().bit()),
-            )
-            .field(
-                "otp_strobe_sw",
-                &format_args!("{}", self.otp_strobe_sw().bit()),
-            )
-            .field("otp_csb_sw", &format_args!("{}", self.otp_csb_sw().bit()))
-            .field(
-                "otp_pgenb_sw",
-                &format_args!("{}", self.otp_pgenb_sw().bit()),
-            )
-            .field(
-                "otp_vddq_is_sw",
-                &format_args!("{}", self.otp_vddq_is_sw().bit()),
-            )
-            .field(
-                "blk0_valid_bit_cnt",
-                &format_args!("{}", self.blk0_valid_bit_cnt().bits()),
-            )
-            .field(
-                "cur_ecdsa_blk",
-                &format_args!("{}", self.cur_ecdsa_blk().bits()),
-            )
+            .field("state", &self.state())
+            .field("otp_load_sw", &self.otp_load_sw())
+            .field("otp_vddq_c_sync2", &self.otp_vddq_c_sync2())
+            .field("otp_strobe_sw", &self.otp_strobe_sw())
+            .field("otp_csb_sw", &self.otp_csb_sw())
+            .field("otp_pgenb_sw", &self.otp_pgenb_sw())
+            .field("otp_vddq_is_sw", &self.otp_vddq_is_sw())
+            .field("blk0_valid_bit_cnt", &self.blk0_valid_bit_cnt())
+            .field("cur_ecdsa_blk", &self.cur_ecdsa_blk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32p4/src/efuse/wr_tim_conf0_rs_bypass.rs b/esp32p4/src/efuse/wr_tim_conf0_rs_bypass.rs
index f460ea6d75..9085305267 100644
--- a/esp32p4/src/efuse/wr_tim_conf0_rs_bypass.rs
+++ b/esp32p4/src/efuse/wr_tim_conf0_rs_bypass.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF0_RS_BYPASS")
-            .field(
-                "bypass_rs_correction",
-                &format_args!("{}", self.bypass_rs_correction().bit()),
-            )
-            .field(
-                "bypass_rs_blk_num",
-                &format_args!("{}", self.bypass_rs_blk_num().bits()),
-            )
-            .field(
-                "tpgm_inactive",
-                &format_args!("{}", self.tpgm_inactive().bits()),
-            )
+            .field("bypass_rs_correction", &self.bypass_rs_correction())
+            .field("bypass_rs_blk_num", &self.bypass_rs_blk_num())
+            .field("tpgm_inactive", &self.tpgm_inactive())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF0_RS_BYPASS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to bypass reed solomon correction step."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/wr_tim_conf1.rs b/esp32p4/src/efuse/wr_tim_conf1.rs
index 8dd4a82158..1a50b07633 100644
--- a/esp32p4/src/efuse/wr_tim_conf1.rs
+++ b/esp32p4/src/efuse/wr_tim_conf1.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF1")
-            .field("tsup_a", &format_args!("{}", self.tsup_a().bits()))
-            .field("pwr_on_num", &format_args!("{}", self.pwr_on_num().bits()))
-            .field("thp_a", &format_args!("{}", self.thp_a().bits()))
+            .field("tsup_a", &self.tsup_a())
+            .field("pwr_on_num", &self.pwr_on_num())
+            .field("thp_a", &self.thp_a())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures the programming setup time."]
     #[inline(always)]
diff --git a/esp32p4/src/efuse/wr_tim_conf2.rs b/esp32p4/src/efuse/wr_tim_conf2.rs
index d9c7035316..a89714c107 100644
--- a/esp32p4/src/efuse/wr_tim_conf2.rs
+++ b/esp32p4/src/efuse/wr_tim_conf2.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF2")
-            .field(
-                "pwr_off_num",
-                &format_args!("{}", self.pwr_off_num().bits()),
-            )
-            .field("tpgm", &format_args!("{}", self.tpgm().bits()))
+            .field("pwr_off_num", &self.pwr_off_num())
+            .field("tpgm", &self.tpgm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures the power outage time for VDDQ."]
     #[inline(always)]
diff --git a/esp32p4/src/generic.rs b/esp32p4/src/generic.rs
index a2ae6aa053..45ebed16c4 100644
--- a/esp32p4/src/generic.rs
+++ b/esp32p4/src/generic.rs
@@ -48,7 +48,7 @@ pub trait RegisterSpec {
 #[doc = " Raw field type"]
 pub trait FieldSpec: Sized {
     #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
-    type Ux: Copy + PartialEq + From<Self>;
+    type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
 }
 #[doc = " Marker for fields with fixed values"]
 pub trait IsEnum: FieldSpec {}
@@ -237,6 +237,14 @@ impl<REG: Readable + Writable> Reg<REG> {
         );
     }
 }
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
 #[doc(hidden)]
 pub mod raw;
 #[doc = " Register reader."]
@@ -302,6 +310,11 @@ impl<FI: FieldSpec> FieldReader<FI> {
         self.bits
     }
 }
+impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 impl<FI> PartialEq<FI> for FieldReader<FI>
 where
     FI: FieldSpec + Copy,
@@ -338,10 +351,21 @@ impl<FI> BitReader<FI> {
         self.bit()
     }
 }
+impl<FI> core::fmt::Debug for BitReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 #[doc = " Marker for register/field writers which can take any value of specified width"]
 pub struct Safe;
 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
 pub struct Unsafe;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct Range<const MIN: u64, const MAX: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeFrom<const MIN: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeTo<const MAX: u64>;
 #[doc = " Write field Proxy"]
 pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
     raw::FieldWriter<'a, REG, WI, FI, Safety>;
@@ -393,6 +417,58 @@ where
         unsafe { self.bits(value) }
     }
 }
+impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
+    FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN && value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
 impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
diff --git a/esp32p4/src/gpio/bist_ctrl.rs b/esp32p4/src/gpio/bist_ctrl.rs
index 585a3467ab..2e85121aaf 100644
--- a/esp32p4/src/gpio/bist_ctrl.rs
+++ b/esp32p4/src/gpio/bist_ctrl.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BIST_CTRL")
-            .field("bist_pad_oe", &format_args!("{}", self.bist_pad_oe().bit()))
+            .field("bist_pad_oe", &self.bist_pad_oe())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BIST_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - High speed sdio pad bist out pad oe"]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/bistin_sel.rs b/esp32p4/src/gpio/bistin_sel.rs
index 9f8a8e72fe..e003056df9 100644
--- a/esp32p4/src/gpio/bistin_sel.rs
+++ b/esp32p4/src/gpio/bistin_sel.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BISTIN_SEL")
-            .field("bistin_sel", &format_args!("{}", self.bistin_sel().bits()))
+            .field("bistin_sel", &self.bistin_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BISTIN_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - High speed sdio pad bist in pad sel 0:pad39, 1: pad40..."]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/bt_select.rs b/esp32p4/src/gpio/bt_select.rs
index d4bbc43143..d78b414754 100644
--- a/esp32p4/src/gpio/bt_select.rs
+++ b/esp32p4/src/gpio/bt_select.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_SELECT")
-            .field("bt_sel", &format_args!("{}", self.bt_sel().bits()))
+            .field("bt_sel", &self.bt_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_SELECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO bit select register"]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/clock_gate.rs b/esp32p4/src/gpio/clock_gate.rs
index ebd199051e..d2bfefd1b8 100644
--- a/esp32p4/src/gpio/clock_gate.rs
+++ b/esp32p4/src/gpio/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this bit to enable GPIO clock gate"]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/date.rs b/esp32p4/src/gpio/date.rs
index 9c55c976dc..5fd6a6ec38 100644
--- a/esp32p4/src/gpio/date.rs
+++ b/esp32p4/src/gpio/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/gpio/enable.rs b/esp32p4/src/gpio/enable.rs
index 72557464c3..2dfdd4f50c 100644
--- a/esp32p4/src/gpio/enable.rs
+++ b/esp32p4/src/gpio/enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO output enable register for GPIO0-31"]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/enable1.rs b/esp32p4/src/gpio/enable1.rs
index 034ba5d583..3e0d90bdb0 100644
--- a/esp32p4/src/gpio/enable1.rs
+++ b/esp32p4/src/gpio/enable1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE1")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:24 - GPIO output enable register for GPIO32-56"]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/func_in_sel_cfg.rs b/esp32p4/src/gpio/func_in_sel_cfg.rs
index b36add172c..92c2a4dc30 100644
--- a/esp32p4/src/gpio/func_in_sel_cfg.rs
+++ b/esp32p4/src/gpio/func_in_sel_cfg.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_IN_SEL_CFG")
-            .field("in_sel", &format_args!("{}", self.in_sel().bits()))
-            .field("in_inv_sel", &format_args!("{}", self.in_inv_sel().bit()))
-            .field("sel", &format_args!("{}", self.sel().bit()))
+            .field("in_sel", &self.in_sel())
+            .field("in_inv_sel", &self.in_inv_sel())
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - set this value: s=0-56: connect GPIO\\[s\\] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level."]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/func_out_sel_cfg.rs b/esp32p4/src/gpio/func_out_sel_cfg.rs
index 7f97f421a1..2741b8047d 100644
--- a/esp32p4/src/gpio/func_out_sel_cfg.rs
+++ b/esp32p4/src/gpio/func_out_sel_cfg.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_OUT_SEL_CFG")
-            .field("out_sel", &format_args!("{}", self.out_sel().bits()))
-            .field("inv_sel", &format_args!("{}", self.inv_sel().bit()))
-            .field("oen_sel", &format_args!("{}", self.oen_sel().bit()))
-            .field("oen_inv_sel", &format_args!("{}", self.oen_inv_sel().bit()))
+            .field("out_sel", &self.out_sel())
+            .field("inv_sel", &self.inv_sel())
+            .field("oen_sel", &self.oen_sel())
+            .field("oen_inv_sel", &self.oen_inv_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/in1.rs b/esp32p4/src/gpio/in1.rs
index a9a819ec4b..6faa5f93ae 100644
--- a/esp32p4/src/gpio/in1.rs
+++ b/esp32p4/src/gpio/in1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN1")
-            .field("data_next", &format_args!("{}", self.data_next().bits()))
+            .field("data_next", &self.data_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO input register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN1_SPEC;
 impl crate::RegisterSpec for IN1_SPEC {
diff --git a/esp32p4/src/gpio/in_.rs b/esp32p4/src/gpio/in_.rs
index d81f4ace22..420433e5b0 100644
--- a/esp32p4/src/gpio/in_.rs
+++ b/esp32p4/src/gpio/in_.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN")
-            .field("data_next", &format_args!("{}", self.data_next().bits()))
+            .field("data_next", &self.data_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO input register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SPEC;
 impl crate::RegisterSpec for IN_SPEC {
diff --git a/esp32p4/src/gpio/int_ena.rs b/esp32p4/src/gpio/int_ena.rs
index 7c9cad663b..95980d2a11 100644
--- a/esp32p4/src/gpio/int_ena.rs
+++ b/esp32p4/src/gpio/int_ena.rs
@@ -80,23 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("comp0_neg", &format_args!("{}", self.comp0_neg().bit()))
-            .field("comp0_pos", &format_args!("{}", self.comp0_pos().bit()))
-            .field("comp0_all", &format_args!("{}", self.comp0_all().bit()))
-            .field("comp1_neg", &format_args!("{}", self.comp1_neg().bit()))
-            .field("comp1_pos", &format_args!("{}", self.comp1_pos().bit()))
-            .field("comp1_all", &format_args!("{}", self.comp1_all().bit()))
-            .field("bistok", &format_args!("{}", self.bistok().bit()))
-            .field("bistfail", &format_args!("{}", self.bistfail().bit()))
+            .field("comp0_neg", &self.comp0_neg())
+            .field("comp0_pos", &self.comp0_pos())
+            .field("comp0_all", &self.comp0_all())
+            .field("comp1_neg", &self.comp1_neg())
+            .field("comp1_pos", &self.comp1_pos())
+            .field("comp1_all", &self.comp1_all())
+            .field("bistok", &self.bistok())
+            .field("bistfail", &self.bistfail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - analog comparator pos edge interrupt enable"]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/int_raw.rs b/esp32p4/src/gpio/int_raw.rs
index ffa7441525..a7875c47dd 100644
--- a/esp32p4/src/gpio/int_raw.rs
+++ b/esp32p4/src/gpio/int_raw.rs
@@ -80,23 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("comp0_neg", &format_args!("{}", self.comp0_neg().bit()))
-            .field("comp0_pos", &format_args!("{}", self.comp0_pos().bit()))
-            .field("comp0_all", &format_args!("{}", self.comp0_all().bit()))
-            .field("comp1_neg", &format_args!("{}", self.comp1_neg().bit()))
-            .field("comp1_pos", &format_args!("{}", self.comp1_pos().bit()))
-            .field("comp1_all", &format_args!("{}", self.comp1_all().bit()))
-            .field("bistok", &format_args!("{}", self.bistok().bit()))
-            .field("bistfail", &format_args!("{}", self.bistfail().bit()))
+            .field("comp0_neg", &self.comp0_neg())
+            .field("comp0_pos", &self.comp0_pos())
+            .field("comp0_all", &self.comp0_all())
+            .field("comp1_neg", &self.comp1_neg())
+            .field("comp1_pos", &self.comp1_pos())
+            .field("comp1_all", &self.comp1_all())
+            .field("bistok", &self.bistok())
+            .field("bistfail", &self.bistfail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - analog comparator pos edge interrupt raw"]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/int_st.rs b/esp32p4/src/gpio/int_st.rs
index 120a2dd37a..5007daa67b 100644
--- a/esp32p4/src/gpio/int_st.rs
+++ b/esp32p4/src/gpio/int_st.rs
@@ -62,23 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("comp0_neg", &format_args!("{}", self.comp0_neg().bit()))
-            .field("comp0_pos", &format_args!("{}", self.comp0_pos().bit()))
-            .field("comp0_all", &format_args!("{}", self.comp0_all().bit()))
-            .field("comp1_neg", &format_args!("{}", self.comp1_neg().bit()))
-            .field("comp1_pos", &format_args!("{}", self.comp1_pos().bit()))
-            .field("comp1_all", &format_args!("{}", self.comp1_all().bit()))
-            .field("bistok", &format_args!("{}", self.bistok().bit()))
-            .field("bistfail", &format_args!("{}", self.bistfail().bit()))
+            .field("comp0_neg", &self.comp0_neg())
+            .field("comp0_pos", &self.comp0_pos())
+            .field("comp0_all", &self.comp0_all())
+            .field("comp1_neg", &self.comp1_neg())
+            .field("comp1_pos", &self.comp1_pos())
+            .field("comp1_all", &self.comp1_all())
+            .field("bistok", &self.bistok())
+            .field("bistfail", &self.bistfail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "analog comparator interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/gpio/intr1_0.rs b/esp32p4/src/gpio/intr1_0.rs
index f3d3c34091..f4ba7a5a29 100644
--- a/esp32p4/src/gpio/intr1_0.rs
+++ b/esp32p4/src/gpio/intr1_0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR1_0")
-            .field("int1_0", &format_args!("{}", self.int1_0().bits()))
+            .field("int1_0", &self.int1_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR1_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt 0 status register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr1_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR1_0_SPEC;
 impl crate::RegisterSpec for INTR1_0_SPEC {
diff --git a/esp32p4/src/gpio/intr1_1.rs b/esp32p4/src/gpio/intr1_1.rs
index 1cede4a053..a6ae307205 100644
--- a/esp32p4/src/gpio/intr1_1.rs
+++ b/esp32p4/src/gpio/intr1_1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR1_1")
-            .field("int1_1", &format_args!("{}", self.int1_1().bits()))
+            .field("int1_1", &self.int1_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR1_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt 1 status register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr1_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR1_1_SPEC;
 impl crate::RegisterSpec for INTR1_1_SPEC {
diff --git a/esp32p4/src/gpio/intr1_2.rs b/esp32p4/src/gpio/intr1_2.rs
index 73a2ca38c8..5850f4970b 100644
--- a/esp32p4/src/gpio/intr1_2.rs
+++ b/esp32p4/src/gpio/intr1_2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR1_2")
-            .field("int1_2", &format_args!("{}", self.int1_2().bits()))
+            .field("int1_2", &self.int1_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR1_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt 2 status register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr1_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR1_2_SPEC;
 impl crate::RegisterSpec for INTR1_2_SPEC {
diff --git a/esp32p4/src/gpio/intr1_3.rs b/esp32p4/src/gpio/intr1_3.rs
index 78b9a5d9d7..5719d82b5d 100644
--- a/esp32p4/src/gpio/intr1_3.rs
+++ b/esp32p4/src/gpio/intr1_3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR1_3")
-            .field("int1_3", &format_args!("{}", self.int1_3().bits()))
+            .field("int1_3", &self.int1_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR1_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt 3 status register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr1_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR1_3_SPEC;
 impl crate::RegisterSpec for INTR1_3_SPEC {
diff --git a/esp32p4/src/gpio/intr_0.rs b/esp32p4/src/gpio/intr_0.rs
index 68e94d9145..c7bbdc256e 100644
--- a/esp32p4/src/gpio/intr_0.rs
+++ b/esp32p4/src/gpio/intr_0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_0")
-            .field("int_0", &format_args!("{}", self.int_0().bits()))
+            .field("int_0", &self.int_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt 0 status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_0_SPEC;
 impl crate::RegisterSpec for INTR_0_SPEC {
diff --git a/esp32p4/src/gpio/intr_1.rs b/esp32p4/src/gpio/intr_1.rs
index 6a88e2c1d1..4b7455fe44 100644
--- a/esp32p4/src/gpio/intr_1.rs
+++ b/esp32p4/src/gpio/intr_1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_1")
-            .field("int_1", &format_args!("{}", self.int_1().bits()))
+            .field("int_1", &self.int_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt 1 status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_1_SPEC;
 impl crate::RegisterSpec for INTR_1_SPEC {
diff --git a/esp32p4/src/gpio/intr_2.rs b/esp32p4/src/gpio/intr_2.rs
index faaebd2906..88e1fe91f9 100644
--- a/esp32p4/src/gpio/intr_2.rs
+++ b/esp32p4/src/gpio/intr_2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_2")
-            .field("int_2", &format_args!("{}", self.int_2().bits()))
+            .field("int_2", &self.int_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt 2 status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_2_SPEC;
 impl crate::RegisterSpec for INTR_2_SPEC {
diff --git a/esp32p4/src/gpio/intr_3.rs b/esp32p4/src/gpio/intr_3.rs
index a3c02d4234..fab0765d78 100644
--- a/esp32p4/src/gpio/intr_3.rs
+++ b/esp32p4/src/gpio/intr_3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_3")
-            .field("int_3", &format_args!("{}", self.int_3().bits()))
+            .field("int_3", &self.int_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt 3 status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_3_SPEC;
 impl crate::RegisterSpec for INTR_3_SPEC {
diff --git a/esp32p4/src/gpio/out.rs b/esp32p4/src/gpio/out.rs
index 3e77b03d34..2c8f1cfb13 100644
--- a/esp32p4/src/gpio/out.rs
+++ b/esp32p4/src/gpio/out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT")
-            .field("data_orig", &format_args!("{}", self.data_orig().bits()))
+            .field("data_orig", &self.data_orig())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO output register for GPIO0-31"]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/out1.rs b/esp32p4/src/gpio/out1.rs
index 3814cbe48c..f18b03bd83 100644
--- a/esp32p4/src/gpio/out1.rs
+++ b/esp32p4/src/gpio/out1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT1")
-            .field("data_orig", &format_args!("{}", self.data_orig().bits()))
+            .field("data_orig", &self.data_orig())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:24 - GPIO output register for GPIO32-56"]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/pin.rs b/esp32p4/src/gpio/pin.rs
index 582513e76d..37d6329326 100644
--- a/esp32p4/src/gpio/pin.rs
+++ b/esp32p4/src/gpio/pin.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN")
-            .field(
-                "sync2_bypass",
-                &format_args!("{}", self.sync2_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field(
-                "sync1_bypass",
-                &format_args!("{}", self.sync1_bypass().bits()),
-            )
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("config", &format_args!("{}", self.config().bits()))
-            .field("int_ena", &format_args!("{}", self.int_ena().bits()))
+            .field("sync2_bypass", &self.sync2_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("sync1_bypass", &self.sync1_bypass())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("config", &self.config())
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/recive_seq.rs b/esp32p4/src/gpio/recive_seq.rs
index fac3eadd13..0822aa6a6a 100644
--- a/esp32p4/src/gpio/recive_seq.rs
+++ b/esp32p4/src/gpio/recive_seq.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RECIVE_SEQ")
-            .field("recive_seq", &format_args!("{}", self.recive_seq().bits()))
+            .field("recive_seq", &self.recive_seq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RECIVE_SEQ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "High speed sdio pad bist recive sequence\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`recive_seq::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RECIVE_SEQ_SPEC;
 impl crate::RegisterSpec for RECIVE_SEQ_SPEC {
diff --git a/esp32p4/src/gpio/send_seq.rs b/esp32p4/src/gpio/send_seq.rs
index fe3bc8401c..546b312312 100644
--- a/esp32p4/src/gpio/send_seq.rs
+++ b/esp32p4/src/gpio/send_seq.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEND_SEQ")
-            .field("send_seq", &format_args!("{}", self.send_seq().bits()))
+            .field("send_seq", &self.send_seq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEND_SEQ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - High speed sdio pad bist send sequence"]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/status.rs b/esp32p4/src/gpio/status.rs
index 349c0cde52..d41f06e1a5 100644
--- a/esp32p4/src/gpio/status.rs
+++ b/esp32p4/src/gpio/status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("interrupt", &format_args!("{}", self.interrupt().bits()))
+            .field("interrupt", &self.interrupt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO interrupt status register for GPIO0-31"]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/status1.rs b/esp32p4/src/gpio/status1.rs
index 8e8beb63c1..bb6dc5f65d 100644
--- a/esp32p4/src/gpio/status1.rs
+++ b/esp32p4/src/gpio/status1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS1")
-            .field("interrupt", &format_args!("{}", self.interrupt().bits()))
+            .field("interrupt", &self.interrupt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:24 - GPIO interrupt status register for GPIO32-56"]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/status_next.rs b/esp32p4/src/gpio/status_next.rs
index 9df3402e32..ea7e8832c2 100644
--- a/esp32p4/src/gpio/status_next.rs
+++ b/esp32p4/src/gpio/status_next.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_NEXT")
-            .field(
-                "status_interrupt_next",
-                &format_args!("{}", self.status_interrupt_next().bits()),
-            )
+            .field("status_interrupt_next", &self.status_interrupt_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_NEXT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt source register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_NEXT_SPEC;
 impl crate::RegisterSpec for STATUS_NEXT_SPEC {
diff --git a/esp32p4/src/gpio/status_next1.rs b/esp32p4/src/gpio/status_next1.rs
index 5fd8495a29..b452107742 100644
--- a/esp32p4/src/gpio/status_next1.rs
+++ b/esp32p4/src/gpio/status_next1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_NEXT1")
-            .field(
-                "status_interrupt_next1",
-                &format_args!("{}", self.status_interrupt_next1().bits()),
-            )
+            .field("status_interrupt_next1", &self.status_interrupt_next1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_NEXT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt source register for GPIO32-56\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_NEXT1_SPEC;
 impl crate::RegisterSpec for STATUS_NEXT1_SPEC {
diff --git a/esp32p4/src/gpio/strap.rs b/esp32p4/src/gpio/strap.rs
index dfc141ecfb..3bc90c4409 100644
--- a/esp32p4/src/gpio/strap.rs
+++ b/esp32p4/src/gpio/strap.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STRAP")
-            .field("strapping", &format_args!("{}", self.strapping().bits()))
+            .field("strapping", &self.strapping())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STRAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "pad strapping register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`strap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STRAP_SPEC;
 impl crate::RegisterSpec for STRAP_SPEC {
diff --git a/esp32p4/src/gpio/zero_det0_filter_cnt.rs b/esp32p4/src/gpio/zero_det0_filter_cnt.rs
index 7f3042d99f..55230aa148 100644
--- a/esp32p4/src/gpio/zero_det0_filter_cnt.rs
+++ b/esp32p4/src/gpio/zero_det0_filter_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ZERO_DET0_FILTER_CNT")
-            .field(
-                "zero_det0_filter_cnt",
-                &format_args!("{}", self.zero_det0_filter_cnt().bits()),
-            )
+            .field("zero_det0_filter_cnt", &self.zero_det0_filter_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ZERO_DET0_FILTER_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO analog comparator zero detect filter count"]
     #[inline(always)]
diff --git a/esp32p4/src/gpio/zero_det1_filter_cnt.rs b/esp32p4/src/gpio/zero_det1_filter_cnt.rs
index c6c45400b1..e214d0a8fd 100644
--- a/esp32p4/src/gpio/zero_det1_filter_cnt.rs
+++ b/esp32p4/src/gpio/zero_det1_filter_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ZERO_DET1_FILTER_CNT")
-            .field(
-                "zero_det1_filter_cnt",
-                &format_args!("{}", self.zero_det1_filter_cnt().bits()),
-            )
+            .field("zero_det1_filter_cnt", &self.zero_det1_filter_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ZERO_DET1_FILTER_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO analog comparator zero detect filter count"]
     #[inline(always)]
diff --git a/esp32p4/src/gpio_sd/clock_gate.rs b/esp32p4/src/gpio_sd/clock_gate.rs
index 8c8f04eacf..13ae2d777d 100644
--- a/esp32p4/src/gpio_sd/clock_gate.rs
+++ b/esp32p4/src/gpio_sd/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Clock enable bit of configuration registers for sigma delta modulation."]
     #[inline(always)]
diff --git a/esp32p4/src/gpio_sd/etm_event_ch_cfg.rs b/esp32p4/src/gpio_sd/etm_event_ch_cfg.rs
index c1515eac33..42305e52e1 100644
--- a/esp32p4/src/gpio_sd/etm_event_ch_cfg.rs
+++ b/esp32p4/src/gpio_sd/etm_event_ch_cfg.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_EVENT_CH_CFG")
-            .field("event_sel", &format_args!("{}", self.event_sel().bits()))
-            .field("event_en", &format_args!("{}", self.event_en().bit()))
+            .field("event_sel", &self.event_sel())
+            .field("event_en", &self.event_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_EVENT_CH_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Etm event channel select gpio."]
     #[inline(always)]
diff --git a/esp32p4/src/gpio_sd/etm_task_p0_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p0_cfg.rs
index fc1eef97f2..40cb413d0f 100644
--- a/esp32p4/src/gpio_sd/etm_task_p0_cfg.rs
+++ b/esp32p4/src/gpio_sd/etm_task_p0_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P0_CFG")
-            .field("gpio0_en", &format_args!("{}", self.gpio0_en().bit()))
-            .field("gpio1_en", &format_args!("{}", self.gpio1_en().bit()))
-            .field("gpio2_en", &format_args!("{}", self.gpio2_en().bit()))
-            .field("gpio3_en", &format_args!("{}", self.gpio3_en().bit()))
-            .field("gpio0_sel", &format_args!("{}", self.gpio0_sel().bits()))
-            .field("gpio1_sel", &format_args!("{}", self.gpio1_sel().bits()))
-            .field("gpio2_sel", &format_args!("{}", self.gpio2_sel().bits()))
-            .field("gpio3_sel", &format_args!("{}", self.gpio3_sel().bits()))
+            .field("gpio0_en", &self.gpio0_en())
+            .field("gpio1_en", &self.gpio1_en())
+            .field("gpio2_en", &self.gpio2_en())
+            .field("gpio3_en", &self.gpio3_en())
+            .field("gpio0_sel", &self.gpio0_sel())
+            .field("gpio1_sel", &self.gpio1_sel())
+            .field("gpio2_sel", &self.gpio2_sel())
+            .field("gpio3_sel", &self.gpio3_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P0_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32p4/src/gpio_sd/etm_task_p10_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p10_cfg.rs
index c208ac405b..772a6ff995 100644
--- a/esp32p4/src/gpio_sd/etm_task_p10_cfg.rs
+++ b/esp32p4/src/gpio_sd/etm_task_p10_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P10_CFG")
-            .field("gpio40_en", &format_args!("{}", self.gpio40_en().bit()))
-            .field("gpio41_en", &format_args!("{}", self.gpio41_en().bit()))
-            .field("gpio42_en", &format_args!("{}", self.gpio42_en().bit()))
-            .field("gpio43_en", &format_args!("{}", self.gpio43_en().bit()))
-            .field("gpio40_sel", &format_args!("{}", self.gpio40_sel().bits()))
-            .field("gpio41_sel", &format_args!("{}", self.gpio41_sel().bits()))
-            .field("gpio42_sel", &format_args!("{}", self.gpio42_sel().bits()))
-            .field("gpio43_sel", &format_args!("{}", self.gpio43_sel().bits()))
+            .field("gpio40_en", &self.gpio40_en())
+            .field("gpio41_en", &self.gpio41_en())
+            .field("gpio42_en", &self.gpio42_en())
+            .field("gpio43_en", &self.gpio43_en())
+            .field("gpio40_sel", &self.gpio40_sel())
+            .field("gpio41_sel", &self.gpio41_sel())
+            .field("gpio42_sel", &self.gpio42_sel())
+            .field("gpio43_sel", &self.gpio43_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P10_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32p4/src/gpio_sd/etm_task_p11_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p11_cfg.rs
index 858c81c40b..4336ed2e87 100644
--- a/esp32p4/src/gpio_sd/etm_task_p11_cfg.rs
+++ b/esp32p4/src/gpio_sd/etm_task_p11_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P11_CFG")
-            .field("gpio44_en", &format_args!("{}", self.gpio44_en().bit()))
-            .field("gpio45_en", &format_args!("{}", self.gpio45_en().bit()))
-            .field("gpio46_en", &format_args!("{}", self.gpio46_en().bit()))
-            .field("gpio47_en", &format_args!("{}", self.gpio47_en().bit()))
-            .field("gpio44_sel", &format_args!("{}", self.gpio44_sel().bits()))
-            .field("gpio45_sel", &format_args!("{}", self.gpio45_sel().bits()))
-            .field("gpio46_sel", &format_args!("{}", self.gpio46_sel().bits()))
-            .field("gpio47_sel", &format_args!("{}", self.gpio47_sel().bits()))
+            .field("gpio44_en", &self.gpio44_en())
+            .field("gpio45_en", &self.gpio45_en())
+            .field("gpio46_en", &self.gpio46_en())
+            .field("gpio47_en", &self.gpio47_en())
+            .field("gpio44_sel", &self.gpio44_sel())
+            .field("gpio45_sel", &self.gpio45_sel())
+            .field("gpio46_sel", &self.gpio46_sel())
+            .field("gpio47_sel", &self.gpio47_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P11_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32p4/src/gpio_sd/etm_task_p12_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p12_cfg.rs
index 422faa710e..016c9e2022 100644
--- a/esp32p4/src/gpio_sd/etm_task_p12_cfg.rs
+++ b/esp32p4/src/gpio_sd/etm_task_p12_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P12_CFG")
-            .field("gpio48_en", &format_args!("{}", self.gpio48_en().bit()))
-            .field("gpio49_en", &format_args!("{}", self.gpio49_en().bit()))
-            .field("gpio50_en", &format_args!("{}", self.gpio50_en().bit()))
-            .field("gpio51_en", &format_args!("{}", self.gpio51_en().bit()))
-            .field("gpio48_sel", &format_args!("{}", self.gpio48_sel().bits()))
-            .field("gpio49_sel", &format_args!("{}", self.gpio49_sel().bits()))
-            .field("gpio50_sel", &format_args!("{}", self.gpio50_sel().bits()))
-            .field("gpio51_sel", &format_args!("{}", self.gpio51_sel().bits()))
+            .field("gpio48_en", &self.gpio48_en())
+            .field("gpio49_en", &self.gpio49_en())
+            .field("gpio50_en", &self.gpio50_en())
+            .field("gpio51_en", &self.gpio51_en())
+            .field("gpio48_sel", &self.gpio48_sel())
+            .field("gpio49_sel", &self.gpio49_sel())
+            .field("gpio50_sel", &self.gpio50_sel())
+            .field("gpio51_sel", &self.gpio51_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P12_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32p4/src/gpio_sd/etm_task_p13_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p13_cfg.rs
index bf5e8ecd3b..d4135a9e0f 100644
--- a/esp32p4/src/gpio_sd/etm_task_p13_cfg.rs
+++ b/esp32p4/src/gpio_sd/etm_task_p13_cfg.rs
@@ -76,21 +76,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P13_CFG")
-            .field("gpio52_en", &format_args!("{}", self.gpio52_en().bit()))
-            .field("gpio53_en", &format_args!("{}", self.gpio53_en().bit()))
-            .field("gpio54_en", &format_args!("{}", self.gpio54_en().bit()))
-            .field("gpio52_sel", &format_args!("{}", self.gpio52_sel().bits()))
-            .field("gpio53_sel", &format_args!("{}", self.gpio53_sel().bits()))
-            .field("gpio54_sel", &format_args!("{}", self.gpio54_sel().bits()))
+            .field("gpio52_en", &self.gpio52_en())
+            .field("gpio53_en", &self.gpio53_en())
+            .field("gpio54_en", &self.gpio54_en())
+            .field("gpio52_sel", &self.gpio52_sel())
+            .field("gpio53_sel", &self.gpio53_sel())
+            .field("gpio54_sel", &self.gpio54_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P13_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32p4/src/gpio_sd/etm_task_p1_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p1_cfg.rs
index e9ace39fdb..3092373081 100644
--- a/esp32p4/src/gpio_sd/etm_task_p1_cfg.rs
+++ b/esp32p4/src/gpio_sd/etm_task_p1_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P1_CFG")
-            .field("gpio4_en", &format_args!("{}", self.gpio4_en().bit()))
-            .field("gpio5_en", &format_args!("{}", self.gpio5_en().bit()))
-            .field("gpio6_en", &format_args!("{}", self.gpio6_en().bit()))
-            .field("gpio7_en", &format_args!("{}", self.gpio7_en().bit()))
-            .field("gpio4_sel", &format_args!("{}", self.gpio4_sel().bits()))
-            .field("gpio5_sel", &format_args!("{}", self.gpio5_sel().bits()))
-            .field("gpio6_sel", &format_args!("{}", self.gpio6_sel().bits()))
-            .field("gpio7_sel", &format_args!("{}", self.gpio7_sel().bits()))
+            .field("gpio4_en", &self.gpio4_en())
+            .field("gpio5_en", &self.gpio5_en())
+            .field("gpio6_en", &self.gpio6_en())
+            .field("gpio7_en", &self.gpio7_en())
+            .field("gpio4_sel", &self.gpio4_sel())
+            .field("gpio5_sel", &self.gpio5_sel())
+            .field("gpio6_sel", &self.gpio6_sel())
+            .field("gpio7_sel", &self.gpio7_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P1_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32p4/src/gpio_sd/etm_task_p2_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p2_cfg.rs
index 82670dabaa..63e355d1a0 100644
--- a/esp32p4/src/gpio_sd/etm_task_p2_cfg.rs
+++ b/esp32p4/src/gpio_sd/etm_task_p2_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P2_CFG")
-            .field("gpio8_en", &format_args!("{}", self.gpio8_en().bit()))
-            .field("gpio9_en", &format_args!("{}", self.gpio9_en().bit()))
-            .field("gpio10_en", &format_args!("{}", self.gpio10_en().bit()))
-            .field("gpio11_en", &format_args!("{}", self.gpio11_en().bit()))
-            .field("gpio8_sel", &format_args!("{}", self.gpio8_sel().bits()))
-            .field("gpio9_sel", &format_args!("{}", self.gpio9_sel().bits()))
-            .field("gpio10_sel", &format_args!("{}", self.gpio10_sel().bits()))
-            .field("gpio11_sel", &format_args!("{}", self.gpio11_sel().bits()))
+            .field("gpio8_en", &self.gpio8_en())
+            .field("gpio9_en", &self.gpio9_en())
+            .field("gpio10_en", &self.gpio10_en())
+            .field("gpio11_en", &self.gpio11_en())
+            .field("gpio8_sel", &self.gpio8_sel())
+            .field("gpio9_sel", &self.gpio9_sel())
+            .field("gpio10_sel", &self.gpio10_sel())
+            .field("gpio11_sel", &self.gpio11_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P2_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32p4/src/gpio_sd/etm_task_p3_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p3_cfg.rs
index f7adf3168b..5289dda5a8 100644
--- a/esp32p4/src/gpio_sd/etm_task_p3_cfg.rs
+++ b/esp32p4/src/gpio_sd/etm_task_p3_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P3_CFG")
-            .field("gpio12_en", &format_args!("{}", self.gpio12_en().bit()))
-            .field("gpio13_en", &format_args!("{}", self.gpio13_en().bit()))
-            .field("gpio14_en", &format_args!("{}", self.gpio14_en().bit()))
-            .field("gpio15_en", &format_args!("{}", self.gpio15_en().bit()))
-            .field("gpio12_sel", &format_args!("{}", self.gpio12_sel().bits()))
-            .field("gpio13_sel", &format_args!("{}", self.gpio13_sel().bits()))
-            .field("gpio14_sel", &format_args!("{}", self.gpio14_sel().bits()))
-            .field("gpio15_sel", &format_args!("{}", self.gpio15_sel().bits()))
+            .field("gpio12_en", &self.gpio12_en())
+            .field("gpio13_en", &self.gpio13_en())
+            .field("gpio14_en", &self.gpio14_en())
+            .field("gpio15_en", &self.gpio15_en())
+            .field("gpio12_sel", &self.gpio12_sel())
+            .field("gpio13_sel", &self.gpio13_sel())
+            .field("gpio14_sel", &self.gpio14_sel())
+            .field("gpio15_sel", &self.gpio15_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P3_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32p4/src/gpio_sd/etm_task_p4_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p4_cfg.rs
index c1bf571c18..6d2e7326f4 100644
--- a/esp32p4/src/gpio_sd/etm_task_p4_cfg.rs
+++ b/esp32p4/src/gpio_sd/etm_task_p4_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P4_CFG")
-            .field("gpio16_en", &format_args!("{}", self.gpio16_en().bit()))
-            .field("gpio17_en", &format_args!("{}", self.gpio17_en().bit()))
-            .field("gpio18_en", &format_args!("{}", self.gpio18_en().bit()))
-            .field("gpio19_en", &format_args!("{}", self.gpio19_en().bit()))
-            .field("gpio16_sel", &format_args!("{}", self.gpio16_sel().bits()))
-            .field("gpio17_sel", &format_args!("{}", self.gpio17_sel().bits()))
-            .field("gpio18_sel", &format_args!("{}", self.gpio18_sel().bits()))
-            .field("gpio19_sel", &format_args!("{}", self.gpio19_sel().bits()))
+            .field("gpio16_en", &self.gpio16_en())
+            .field("gpio17_en", &self.gpio17_en())
+            .field("gpio18_en", &self.gpio18_en())
+            .field("gpio19_en", &self.gpio19_en())
+            .field("gpio16_sel", &self.gpio16_sel())
+            .field("gpio17_sel", &self.gpio17_sel())
+            .field("gpio18_sel", &self.gpio18_sel())
+            .field("gpio19_sel", &self.gpio19_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P4_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32p4/src/gpio_sd/etm_task_p5_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p5_cfg.rs
index 036e404fb1..7c3863c69a 100644
--- a/esp32p4/src/gpio_sd/etm_task_p5_cfg.rs
+++ b/esp32p4/src/gpio_sd/etm_task_p5_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P5_CFG")
-            .field("gpio20_en", &format_args!("{}", self.gpio20_en().bit()))
-            .field("gpio21_en", &format_args!("{}", self.gpio21_en().bit()))
-            .field("gpio22_en", &format_args!("{}", self.gpio22_en().bit()))
-            .field("gpio23_en", &format_args!("{}", self.gpio23_en().bit()))
-            .field("gpio20_sel", &format_args!("{}", self.gpio20_sel().bits()))
-            .field("gpio21_sel", &format_args!("{}", self.gpio21_sel().bits()))
-            .field("gpio22_sel", &format_args!("{}", self.gpio22_sel().bits()))
-            .field("gpio23_sel", &format_args!("{}", self.gpio23_sel().bits()))
+            .field("gpio20_en", &self.gpio20_en())
+            .field("gpio21_en", &self.gpio21_en())
+            .field("gpio22_en", &self.gpio22_en())
+            .field("gpio23_en", &self.gpio23_en())
+            .field("gpio20_sel", &self.gpio20_sel())
+            .field("gpio21_sel", &self.gpio21_sel())
+            .field("gpio22_sel", &self.gpio22_sel())
+            .field("gpio23_sel", &self.gpio23_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P5_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32p4/src/gpio_sd/etm_task_p6_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p6_cfg.rs
index 5a0080ebf9..3a188d2401 100644
--- a/esp32p4/src/gpio_sd/etm_task_p6_cfg.rs
+++ b/esp32p4/src/gpio_sd/etm_task_p6_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P6_CFG")
-            .field("gpio24_en", &format_args!("{}", self.gpio24_en().bit()))
-            .field("gpio25_en", &format_args!("{}", self.gpio25_en().bit()))
-            .field("gpio26_en", &format_args!("{}", self.gpio26_en().bit()))
-            .field("gpio27_en", &format_args!("{}", self.gpio27_en().bit()))
-            .field("gpio24_sel", &format_args!("{}", self.gpio24_sel().bits()))
-            .field("gpio25_sel", &format_args!("{}", self.gpio25_sel().bits()))
-            .field("gpio26_sel", &format_args!("{}", self.gpio26_sel().bits()))
-            .field("gpio27_sel", &format_args!("{}", self.gpio27_sel().bits()))
+            .field("gpio24_en", &self.gpio24_en())
+            .field("gpio25_en", &self.gpio25_en())
+            .field("gpio26_en", &self.gpio26_en())
+            .field("gpio27_en", &self.gpio27_en())
+            .field("gpio24_sel", &self.gpio24_sel())
+            .field("gpio25_sel", &self.gpio25_sel())
+            .field("gpio26_sel", &self.gpio26_sel())
+            .field("gpio27_sel", &self.gpio27_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P6_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32p4/src/gpio_sd/etm_task_p7_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p7_cfg.rs
index 40aaa1b8f3..bf06dd7f94 100644
--- a/esp32p4/src/gpio_sd/etm_task_p7_cfg.rs
+++ b/esp32p4/src/gpio_sd/etm_task_p7_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P7_CFG")
-            .field("gpio28_en", &format_args!("{}", self.gpio28_en().bit()))
-            .field("gpio29_en", &format_args!("{}", self.gpio29_en().bit()))
-            .field("gpio30_en", &format_args!("{}", self.gpio30_en().bit()))
-            .field("gpio31_en", &format_args!("{}", self.gpio31_en().bit()))
-            .field("gpio28_sel", &format_args!("{}", self.gpio28_sel().bits()))
-            .field("gpio29_sel", &format_args!("{}", self.gpio29_sel().bits()))
-            .field("gpio30_sel", &format_args!("{}", self.gpio30_sel().bits()))
-            .field("gpio31_sel", &format_args!("{}", self.gpio31_sel().bits()))
+            .field("gpio28_en", &self.gpio28_en())
+            .field("gpio29_en", &self.gpio29_en())
+            .field("gpio30_en", &self.gpio30_en())
+            .field("gpio31_en", &self.gpio31_en())
+            .field("gpio28_sel", &self.gpio28_sel())
+            .field("gpio29_sel", &self.gpio29_sel())
+            .field("gpio30_sel", &self.gpio30_sel())
+            .field("gpio31_sel", &self.gpio31_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P7_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32p4/src/gpio_sd/etm_task_p8_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p8_cfg.rs
index 162ebdec28..a061280c1f 100644
--- a/esp32p4/src/gpio_sd/etm_task_p8_cfg.rs
+++ b/esp32p4/src/gpio_sd/etm_task_p8_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P8_CFG")
-            .field("gpio32_en", &format_args!("{}", self.gpio32_en().bit()))
-            .field("gpio33_en", &format_args!("{}", self.gpio33_en().bit()))
-            .field("gpio34_en", &format_args!("{}", self.gpio34_en().bit()))
-            .field("gpio35_en", &format_args!("{}", self.gpio35_en().bit()))
-            .field("gpio32_sel", &format_args!("{}", self.gpio32_sel().bits()))
-            .field("gpio33_sel", &format_args!("{}", self.gpio33_sel().bits()))
-            .field("gpio34_sel", &format_args!("{}", self.gpio34_sel().bits()))
-            .field("gpio35_sel", &format_args!("{}", self.gpio35_sel().bits()))
+            .field("gpio32_en", &self.gpio32_en())
+            .field("gpio33_en", &self.gpio33_en())
+            .field("gpio34_en", &self.gpio34_en())
+            .field("gpio35_en", &self.gpio35_en())
+            .field("gpio32_sel", &self.gpio32_sel())
+            .field("gpio33_sel", &self.gpio33_sel())
+            .field("gpio34_sel", &self.gpio34_sel())
+            .field("gpio35_sel", &self.gpio35_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P8_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32p4/src/gpio_sd/etm_task_p9_cfg.rs b/esp32p4/src/gpio_sd/etm_task_p9_cfg.rs
index 1b409e5050..a6b5908654 100644
--- a/esp32p4/src/gpio_sd/etm_task_p9_cfg.rs
+++ b/esp32p4/src/gpio_sd/etm_task_p9_cfg.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_TASK_P9_CFG")
-            .field("gpio36_en", &format_args!("{}", self.gpio36_en().bit()))
-            .field("gpio37_en", &format_args!("{}", self.gpio37_en().bit()))
-            .field("gpio38_en", &format_args!("{}", self.gpio38_en().bit()))
-            .field("gpio39_en", &format_args!("{}", self.gpio39_en().bit()))
-            .field("gpio36_sel", &format_args!("{}", self.gpio36_sel().bits()))
-            .field("gpio37_sel", &format_args!("{}", self.gpio37_sel().bits()))
-            .field("gpio38_sel", &format_args!("{}", self.gpio38_sel().bits()))
-            .field("gpio39_sel", &format_args!("{}", self.gpio39_sel().bits()))
+            .field("gpio36_en", &self.gpio36_en())
+            .field("gpio37_en", &self.gpio37_en())
+            .field("gpio38_en", &self.gpio38_en())
+            .field("gpio39_en", &self.gpio39_en())
+            .field("gpio36_sel", &self.gpio36_sel())
+            .field("gpio37_sel", &self.gpio37_sel())
+            .field("gpio38_sel", &self.gpio38_sel())
+            .field("gpio39_sel", &self.gpio39_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_TASK_P9_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Enable bit of GPIO response etm task."]
     #[doc = ""]
diff --git a/esp32p4/src/gpio_sd/glitch_filter_ch.rs b/esp32p4/src/gpio_sd/glitch_filter_ch.rs
index 6058e197b0..fa2b797f10 100644
--- a/esp32p4/src/gpio_sd/glitch_filter_ch.rs
+++ b/esp32p4/src/gpio_sd/glitch_filter_ch.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GLITCH_FILTER_CH")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field(
-                "input_io_num",
-                &format_args!("{}", self.input_io_num().bits()),
-            )
-            .field(
-                "window_thres",
-                &format_args!("{}", self.window_thres().bits()),
-            )
-            .field(
-                "window_width",
-                &format_args!("{}", self.window_width().bits()),
-            )
+            .field("en", &self.en())
+            .field("input_io_num", &self.input_io_num())
+            .field("window_thres", &self.window_thres())
+            .field("window_width", &self.window_width())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GLITCH_FILTER_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Glitch Filter channel enable bit."]
     #[inline(always)]
diff --git a/esp32p4/src/gpio_sd/sigmadelta.rs b/esp32p4/src/gpio_sd/sigmadelta.rs
index 2cb8973865..1d31bcd5d8 100644
--- a/esp32p4/src/gpio_sd/sigmadelta.rs
+++ b/esp32p4/src/gpio_sd/sigmadelta.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SIGMADELTA")
-            .field("in_", &format_args!("{}", self.in_().bits()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
+            .field("in_", &self.in_())
+            .field("prescale", &self.prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SIGMADELTA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."]
     #[inline(always)]
diff --git a/esp32p4/src/gpio_sd/sigmadelta_misc.rs b/esp32p4/src/gpio_sd/sigmadelta_misc.rs
index b0c196b157..973947d549 100644
--- a/esp32p4/src/gpio_sd/sigmadelta_misc.rs
+++ b/esp32p4/src/gpio_sd/sigmadelta_misc.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SIGMADELTA_MISC")
-            .field(
-                "function_clk_en",
-                &format_args!("{}", self.function_clk_en().bit()),
-            )
-            .field("spi_swap", &format_args!("{}", self.spi_swap().bit()))
+            .field("function_clk_en", &self.function_clk_en())
+            .field("spi_swap", &self.spi_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SIGMADELTA_MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - Clock enable bit of sigma delta modulation."]
     #[inline(always)]
diff --git a/esp32p4/src/gpio_sd/version.rs b/esp32p4/src/gpio_sd/version.rs
index 445b15f729..d43d139101 100644
--- a/esp32p4/src/gpio_sd/version.rs
+++ b/esp32p4/src/gpio_sd/version.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field(
-                "gpio_sd_date",
-                &format_args!("{}", self.gpio_sd_date().bits()),
-            )
+            .field("gpio_sd_date", &self.gpio_sd_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_db_bypass.rs b/esp32p4/src/h264/a_db_bypass.rs
index 8be2f02cb1..d75ca7c247 100644
--- a/esp32p4/src/h264/a_db_bypass.rs
+++ b/esp32p4/src/h264/a_db_bypass.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_DB_BYPASS")
-            .field(
-                "a_bypass_db_filter",
-                &format_args!("{}", self.a_bypass_db_filter().bit()),
-            )
+            .field("a_bypass_db_filter", &self.a_bypass_db_filter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_DB_BYPASS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to bypass video A deblcoking filter. \\\\0: Open the deblock filter\\\\1: Close the deblock filter"]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_deci_score.rs b/esp32p4/src/h264/a_deci_score.rs
index 91e4fbd8ce..323be90548 100644
--- a/esp32p4/src/h264/a_deci_score.rs
+++ b/esp32p4/src/h264/a_deci_score.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_DECI_SCORE")
-            .field(
-                "a_c_deci_score",
-                &format_args!("{}", self.a_c_deci_score().bits()),
-            )
-            .field(
-                "a_l_deci_score",
-                &format_args!("{}", self.a_l_deci_score().bits()),
-            )
+            .field("a_c_deci_score", &self.a_c_deci_score())
+            .field("a_l_deci_score", &self.a_l_deci_score())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_DECI_SCORE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - Configures video A chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_deci_score_offset.rs b/esp32p4/src/h264/a_deci_score_offset.rs
index d9cb227851..0d56c61073 100644
--- a/esp32p4/src/h264/a_deci_score_offset.rs
+++ b/esp32p4/src/h264/a_deci_score_offset.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("A_DECI_SCORE_OFFSET")
             .field(
                 "a_i16x16_deci_score_offset",
-                &format_args!("{}", self.a_i16x16_deci_score_offset().bits()),
+                &self.a_i16x16_deci_score_offset(),
             )
             .field(
                 "a_i_chroma_deci_score_offset",
-                &format_args!("{}", self.a_i_chroma_deci_score_offset().bits()),
+                &self.a_i_chroma_deci_score_offset(),
             )
             .field(
                 "a_p16x16_deci_score_offset",
-                &format_args!("{}", self.a_p16x16_deci_score_offset().bits()),
+                &self.a_p16x16_deci_score_offset(),
             )
             .field(
                 "a_p_chroma_deci_score_offset",
-                &format_args!("{}", self.a_p_chroma_deci_score_offset().bits()),
+                &self.a_p_chroma_deci_score_offset(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_DECI_SCORE_OFFSET_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Configures video A i16x16 MB decimate score offset. This offset will be added to i16x16 MB score."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_no_roi_region_qp_offset.rs b/esp32p4/src/h264/a_no_roi_region_qp_offset.rs
index fbbd0e9b80..e59087254a 100644
--- a/esp32p4/src/h264/a_no_roi_region_qp_offset.rs
+++ b/esp32p4/src/h264/a_no_roi_region_qp_offset.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_NO_ROI_REGION_QP_OFFSET")
-            .field(
-                "a_no_roi_region_qp",
-                &format_args!("{}", self.a_no_roi_region_qp().bits()),
-            )
+            .field("a_no_roi_region_qp", &self.a_no_roi_region_qp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_NO_ROI_REGION_QP_OFFSET_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configure H264 no region qp in video A, delta qp."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_rc_conf0.rs b/esp32p4/src/h264/a_rc_conf0.rs
index 46483b0883..b977a81780 100644
--- a/esp32p4/src/h264/a_rc_conf0.rs
+++ b/esp32p4/src/h264/a_rc_conf0.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_RC_CONF0")
-            .field("a_qp", &format_args!("{}", self.a_qp().bits()))
-            .field(
-                "a_rate_ctrl_u",
-                &format_args!("{}", self.a_rate_ctrl_u().bits()),
-            )
-            .field(
-                "a_mb_rate_ctrl_en",
-                &format_args!("{}", self.a_mb_rate_ctrl_en().bit()),
-            )
+            .field("a_qp", &self.a_qp())
+            .field("a_rate_ctrl_u", &self.a_rate_ctrl_u())
+            .field("a_mb_rate_ctrl_en", &self.a_mb_rate_ctrl_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_RC_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Configures video A frame level initial luma QP value."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_rc_conf1.rs b/esp32p4/src/h264/a_rc_conf1.rs
index 5ef84ee66d..b435938b2a 100644
--- a/esp32p4/src/h264/a_rc_conf1.rs
+++ b/esp32p4/src/h264/a_rc_conf1.rs
@@ -53,29 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_RC_CONF1")
-            .field(
-                "a_chroma_dc_qp_delta",
-                &format_args!("{}", self.a_chroma_dc_qp_delta().bits()),
-            )
-            .field(
-                "a_chroma_qp_delta",
-                &format_args!("{}", self.a_chroma_qp_delta().bits()),
-            )
-            .field("a_qp_min", &format_args!("{}", self.a_qp_min().bits()))
-            .field("a_qp_max", &format_args!("{}", self.a_qp_max().bits()))
-            .field(
-                "a_mad_frame_pred",
-                &format_args!("{}", self.a_mad_frame_pred().bits()),
-            )
+            .field("a_chroma_dc_qp_delta", &self.a_chroma_dc_qp_delta())
+            .field("a_chroma_qp_delta", &self.a_chroma_qp_delta())
+            .field("a_qp_min", &self.a_qp_min())
+            .field("a_qp_max", &self.a_qp_max())
+            .field("a_mad_frame_pred", &self.a_mad_frame_pred())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_RC_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_roi_config.rs b/esp32p4/src/h264/a_roi_config.rs
index 30b774e35a..63d9436e85 100644
--- a/esp32p4/src/h264/a_roi_config.rs
+++ b/esp32p4/src/h264/a_roi_config.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_ROI_CONFIG")
-            .field("a_roi_en", &format_args!("{}", self.a_roi_en().bit()))
-            .field("a_roi_mode", &format_args!("{}", self.a_roi_mode().bit()))
+            .field("a_roi_en", &self.a_roi_en())
+            .field("a_roi_mode", &self.a_roi_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_ROI_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configure whether or not to enable ROI in video A.\\\\0:not enable ROI\\\\1:enable ROI."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_roi_region0.rs b/esp32p4/src/h264/a_roi_region0.rs
index 3df33dc621..ea8aeecf1d 100644
--- a/esp32p4/src/h264/a_roi_region0.rs
+++ b/esp32p4/src/h264/a_roi_region0.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_ROI_REGION0")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_ROI_REGION0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 0 in Video A."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_roi_region0_3_qp.rs b/esp32p4/src/h264/a_roi_region0_3_qp.rs
index d96a60adbb..bfd60fb4fd 100644
--- a/esp32p4/src/h264/a_roi_region0_3_qp.rs
+++ b/esp32p4/src/h264/a_roi_region0_3_qp.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_ROI_REGION0_3_QP")
-            .field(
-                "a_roi_region0_qp",
-                &format_args!("{}", self.a_roi_region0_qp().bits()),
-            )
-            .field(
-                "a_roi_region1_qp",
-                &format_args!("{}", self.a_roi_region1_qp().bits()),
-            )
-            .field(
-                "a_roi_region2_qp",
-                &format_args!("{}", self.a_roi_region2_qp().bits()),
-            )
-            .field(
-                "a_roi_region3_qp",
-                &format_args!("{}", self.a_roi_region3_qp().bits()),
-            )
+            .field("a_roi_region0_qp", &self.a_roi_region0_qp())
+            .field("a_roi_region1_qp", &self.a_roi_region1_qp())
+            .field("a_roi_region2_qp", &self.a_roi_region2_qp())
+            .field("a_roi_region3_qp", &self.a_roi_region3_qp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_ROI_REGION0_3_QP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configure H264 ROI region0 qp in video A,fixed qp or delta qp."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_roi_region1.rs b/esp32p4/src/h264/a_roi_region1.rs
index b225a8f9b7..1bda41846b 100644
--- a/esp32p4/src/h264/a_roi_region1.rs
+++ b/esp32p4/src/h264/a_roi_region1.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_ROI_REGION1")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_ROI_REGION1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 1 in Video A."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_roi_region2.rs b/esp32p4/src/h264/a_roi_region2.rs
index beaac8c9e7..56f1102af1 100644
--- a/esp32p4/src/h264/a_roi_region2.rs
+++ b/esp32p4/src/h264/a_roi_region2.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_ROI_REGION2")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_ROI_REGION2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 2 in Video A."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_roi_region3.rs b/esp32p4/src/h264/a_roi_region3.rs
index f2d3b9e031..352a837cff 100644
--- a/esp32p4/src/h264/a_roi_region3.rs
+++ b/esp32p4/src/h264/a_roi_region3.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_ROI_REGION3")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_ROI_REGION3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 3 in Video A."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_roi_region4.rs b/esp32p4/src/h264/a_roi_region4.rs
index 92ce4ba2d3..afb8977d7c 100644
--- a/esp32p4/src/h264/a_roi_region4.rs
+++ b/esp32p4/src/h264/a_roi_region4.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_ROI_REGION4")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_ROI_REGION4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 4 in Video A."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_roi_region4_7_qp.rs b/esp32p4/src/h264/a_roi_region4_7_qp.rs
index 08472bafbb..1c8a3f2820 100644
--- a/esp32p4/src/h264/a_roi_region4_7_qp.rs
+++ b/esp32p4/src/h264/a_roi_region4_7_qp.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_ROI_REGION4_7_QP")
-            .field(
-                "a_roi_region4_qp",
-                &format_args!("{}", self.a_roi_region4_qp().bits()),
-            )
-            .field(
-                "a_roi_region5_qp",
-                &format_args!("{}", self.a_roi_region5_qp().bits()),
-            )
-            .field(
-                "a_roi_region6_qp",
-                &format_args!("{}", self.a_roi_region6_qp().bits()),
-            )
-            .field(
-                "a_roi_region7_qp",
-                &format_args!("{}", self.a_roi_region7_qp().bits()),
-            )
+            .field("a_roi_region4_qp", &self.a_roi_region4_qp())
+            .field("a_roi_region5_qp", &self.a_roi_region5_qp())
+            .field("a_roi_region6_qp", &self.a_roi_region6_qp())
+            .field("a_roi_region7_qp", &self.a_roi_region7_qp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_ROI_REGION4_7_QP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configure H264 ROI region4 qp in video A,fixed qp or delta qp."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_roi_region5.rs b/esp32p4/src/h264/a_roi_region5.rs
index 8717bbc2f9..335ce6f3d1 100644
--- a/esp32p4/src/h264/a_roi_region5.rs
+++ b/esp32p4/src/h264/a_roi_region5.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_ROI_REGION5")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_ROI_REGION5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontial start macroblocks of region 5 video A."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_roi_region6.rs b/esp32p4/src/h264/a_roi_region6.rs
index 6f5d84658b..7e80870f02 100644
--- a/esp32p4/src/h264/a_roi_region6.rs
+++ b/esp32p4/src/h264/a_roi_region6.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_ROI_REGION6")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_ROI_REGION6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontial start macroblocks of region 6 video A."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_roi_region7.rs b/esp32p4/src/h264/a_roi_region7.rs
index 9b0f005614..e2e71525cb 100644
--- a/esp32p4/src/h264/a_roi_region7.rs
+++ b/esp32p4/src/h264/a_roi_region7.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_ROI_REGION7")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_ROI_REGION7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 7 in video A."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_sys_conf.rs b/esp32p4/src/h264/a_sys_conf.rs
index 6c350cdc0d..79ca4e8484 100644
--- a/esp32p4/src/h264/a_sys_conf.rs
+++ b/esp32p4/src/h264/a_sys_conf.rs
@@ -37,25 +37,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("A_SYS_CONF")
             .field(
                 "a_db_tmp_ready_trigger_mb_num",
-                &format_args!("{}", self.a_db_tmp_ready_trigger_mb_num().bits()),
+                &self.a_db_tmp_ready_trigger_mb_num(),
             )
             .field(
                 "a_rec_ready_trigger_mb_lines",
-                &format_args!("{}", self.a_rec_ready_trigger_mb_lines().bits()),
-            )
-            .field(
-                "a_intra_cost_cmp_offset",
-                &format_args!("{}", self.a_intra_cost_cmp_offset().bits()),
+                &self.a_rec_ready_trigger_mb_lines(),
             )
+            .field("a_intra_cost_cmp_offset", &self.a_intra_cost_cmp_offset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_SYS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures when to trigger video A H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/a_sys_mb_res.rs b/esp32p4/src/h264/a_sys_mb_res.rs
index 1d75fb71d2..916aa76b42 100644
--- a/esp32p4/src/h264/a_sys_mb_res.rs
+++ b/esp32p4/src/h264/a_sys_mb_res.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("A_SYS_MB_RES")
-            .field(
-                "a_sys_total_mb_y",
-                &format_args!("{}", self.a_sys_total_mb_y().bits()),
-            )
-            .field(
-                "a_sys_total_mb_x",
-                &format_args!("{}", self.a_sys_total_mb_x().bits()),
-            )
+            .field("a_sys_total_mb_y", &self.a_sys_total_mb_y())
+            .field("a_sys_total_mb_x", &self.a_sys_total_mb_x())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<A_SYS_MB_RES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures video A vertical MB resolution."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_db_bypass.rs b/esp32p4/src/h264/b_db_bypass.rs
index 229a22cc24..0c2a4fca66 100644
--- a/esp32p4/src/h264/b_db_bypass.rs
+++ b/esp32p4/src/h264/b_db_bypass.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_DB_BYPASS")
-            .field(
-                "b_bypass_db_filter",
-                &format_args!("{}", self.b_bypass_db_filter().bit()),
-            )
+            .field("b_bypass_db_filter", &self.b_bypass_db_filter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_DB_BYPASS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to bypass video B deblcoking filter. \\\\0: Open the deblock filter\\\\1: Close the deblock filter"]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_deci_score.rs b/esp32p4/src/h264/b_deci_score.rs
index 073e77241d..afb5ccc7e5 100644
--- a/esp32p4/src/h264/b_deci_score.rs
+++ b/esp32p4/src/h264/b_deci_score.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_DECI_SCORE")
-            .field(
-                "b_c_deci_score",
-                &format_args!("{}", self.b_c_deci_score().bits()),
-            )
-            .field(
-                "b_l_deci_score",
-                &format_args!("{}", self.b_l_deci_score().bits()),
-            )
+            .field("b_c_deci_score", &self.b_c_deci_score())
+            .field("b_l_deci_score", &self.b_l_deci_score())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_DECI_SCORE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - Configures video B chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_deci_score_offset.rs b/esp32p4/src/h264/b_deci_score_offset.rs
index 828074eda8..a0b00ebe39 100644
--- a/esp32p4/src/h264/b_deci_score_offset.rs
+++ b/esp32p4/src/h264/b_deci_score_offset.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("B_DECI_SCORE_OFFSET")
             .field(
                 "b_i16x16_deci_score_offset",
-                &format_args!("{}", self.b_i16x16_deci_score_offset().bits()),
+                &self.b_i16x16_deci_score_offset(),
             )
             .field(
                 "b_i_chroma_deci_score_offset",
-                &format_args!("{}", self.b_i_chroma_deci_score_offset().bits()),
+                &self.b_i_chroma_deci_score_offset(),
             )
             .field(
                 "b_p16x16_deci_score_offset",
-                &format_args!("{}", self.b_p16x16_deci_score_offset().bits()),
+                &self.b_p16x16_deci_score_offset(),
             )
             .field(
                 "b_p_chroma_deci_score_offset",
-                &format_args!("{}", self.b_p_chroma_deci_score_offset().bits()),
+                &self.b_p_chroma_deci_score_offset(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_DECI_SCORE_OFFSET_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Configures video B i16x16 MB decimate score offset. This offset will be added to i16x16 MB score."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_no_roi_region_qp_offset.rs b/esp32p4/src/h264/b_no_roi_region_qp_offset.rs
index 8b8ad74642..7fc3fcb739 100644
--- a/esp32p4/src/h264/b_no_roi_region_qp_offset.rs
+++ b/esp32p4/src/h264/b_no_roi_region_qp_offset.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_NO_ROI_REGION_QP_OFFSET")
-            .field(
-                "b_no_roi_region_qp",
-                &format_args!("{}", self.b_no_roi_region_qp().bits()),
-            )
+            .field("b_no_roi_region_qp", &self.b_no_roi_region_qp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_NO_ROI_REGION_QP_OFFSET_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configure H264 no region qp in video B, delta qp."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_rc_conf0.rs b/esp32p4/src/h264/b_rc_conf0.rs
index 58ebf07c76..c01c90abe1 100644
--- a/esp32p4/src/h264/b_rc_conf0.rs
+++ b/esp32p4/src/h264/b_rc_conf0.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_RC_CONF0")
-            .field("b_qp", &format_args!("{}", self.b_qp().bits()))
-            .field(
-                "b_rate_ctrl_u",
-                &format_args!("{}", self.b_rate_ctrl_u().bits()),
-            )
-            .field(
-                "b_mb_rate_ctrl_en",
-                &format_args!("{}", self.b_mb_rate_ctrl_en().bit()),
-            )
+            .field("b_qp", &self.b_qp())
+            .field("b_rate_ctrl_u", &self.b_rate_ctrl_u())
+            .field("b_mb_rate_ctrl_en", &self.b_mb_rate_ctrl_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_RC_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Configures video B frame level initial luma QP value."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_rc_conf1.rs b/esp32p4/src/h264/b_rc_conf1.rs
index 0c17f758cc..8d862c99e6 100644
--- a/esp32p4/src/h264/b_rc_conf1.rs
+++ b/esp32p4/src/h264/b_rc_conf1.rs
@@ -53,29 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_RC_CONF1")
-            .field(
-                "b_chroma_dc_qp_delta",
-                &format_args!("{}", self.b_chroma_dc_qp_delta().bits()),
-            )
-            .field(
-                "b_chroma_qp_delta",
-                &format_args!("{}", self.b_chroma_qp_delta().bits()),
-            )
-            .field("b_qp_min", &format_args!("{}", self.b_qp_min().bits()))
-            .field("b_qp_max", &format_args!("{}", self.b_qp_max().bits()))
-            .field(
-                "b_mad_frame_pred",
-                &format_args!("{}", self.b_mad_frame_pred().bits()),
-            )
+            .field("b_chroma_dc_qp_delta", &self.b_chroma_dc_qp_delta())
+            .field("b_chroma_qp_delta", &self.b_chroma_qp_delta())
+            .field("b_qp_min", &self.b_qp_min())
+            .field("b_qp_max", &self.b_qp_max())
+            .field("b_mad_frame_pred", &self.b_mad_frame_pred())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_RC_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_roi_config.rs b/esp32p4/src/h264/b_roi_config.rs
index 29688a64c8..8768c6ac90 100644
--- a/esp32p4/src/h264/b_roi_config.rs
+++ b/esp32p4/src/h264/b_roi_config.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_ROI_CONFIG")
-            .field("b_roi_en", &format_args!("{}", self.b_roi_en().bit()))
-            .field("b_roi_mode", &format_args!("{}", self.b_roi_mode().bit()))
+            .field("b_roi_en", &self.b_roi_en())
+            .field("b_roi_mode", &self.b_roi_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_ROI_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configure whether or not to enable ROI in video B.\\\\0:not enable ROI\\\\1:enable ROI."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_roi_region0.rs b/esp32p4/src/h264/b_roi_region0.rs
index d3662cb3b6..3577f66916 100644
--- a/esp32p4/src/h264/b_roi_region0.rs
+++ b/esp32p4/src/h264/b_roi_region0.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_ROI_REGION0")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_ROI_REGION0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 0 in Video B."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_roi_region0_3_qp.rs b/esp32p4/src/h264/b_roi_region0_3_qp.rs
index 6591e6a849..619427b8cf 100644
--- a/esp32p4/src/h264/b_roi_region0_3_qp.rs
+++ b/esp32p4/src/h264/b_roi_region0_3_qp.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_ROI_REGION0_3_QP")
-            .field(
-                "b_roi_region0_qp",
-                &format_args!("{}", self.b_roi_region0_qp().bits()),
-            )
-            .field(
-                "b_roi_region1_qp",
-                &format_args!("{}", self.b_roi_region1_qp().bits()),
-            )
-            .field(
-                "b_roi_region2_qp",
-                &format_args!("{}", self.b_roi_region2_qp().bits()),
-            )
-            .field(
-                "b_roi_region3_qp",
-                &format_args!("{}", self.b_roi_region3_qp().bits()),
-            )
+            .field("b_roi_region0_qp", &self.b_roi_region0_qp())
+            .field("b_roi_region1_qp", &self.b_roi_region1_qp())
+            .field("b_roi_region2_qp", &self.b_roi_region2_qp())
+            .field("b_roi_region3_qp", &self.b_roi_region3_qp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_ROI_REGION0_3_QP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configure H264 ROI region0 qp in video B,fixed qp or delta qp."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_roi_region1.rs b/esp32p4/src/h264/b_roi_region1.rs
index 90f004885a..55dd4bf982 100644
--- a/esp32p4/src/h264/b_roi_region1.rs
+++ b/esp32p4/src/h264/b_roi_region1.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_ROI_REGION1")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_ROI_REGION1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 1 in Video B."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_roi_region2.rs b/esp32p4/src/h264/b_roi_region2.rs
index 3a2215b83b..6edb6a8307 100644
--- a/esp32p4/src/h264/b_roi_region2.rs
+++ b/esp32p4/src/h264/b_roi_region2.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_ROI_REGION2")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_ROI_REGION2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 2 in Video B."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_roi_region3.rs b/esp32p4/src/h264/b_roi_region3.rs
index 7ab0289268..c60da119a6 100644
--- a/esp32p4/src/h264/b_roi_region3.rs
+++ b/esp32p4/src/h264/b_roi_region3.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_ROI_REGION3")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_ROI_REGION3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 3 in Video B."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_roi_region4.rs b/esp32p4/src/h264/b_roi_region4.rs
index 5ce12f837a..1447c2eda2 100644
--- a/esp32p4/src/h264/b_roi_region4.rs
+++ b/esp32p4/src/h264/b_roi_region4.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_ROI_REGION4")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_ROI_REGION4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 4 in Video B."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_roi_region4_7_qp.rs b/esp32p4/src/h264/b_roi_region4_7_qp.rs
index 174128b188..dce163073d 100644
--- a/esp32p4/src/h264/b_roi_region4_7_qp.rs
+++ b/esp32p4/src/h264/b_roi_region4_7_qp.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_ROI_REGION4_7_QP")
-            .field(
-                "b_roi_region4_qp",
-                &format_args!("{}", self.b_roi_region4_qp().bits()),
-            )
-            .field(
-                "b_roi_region5_qp",
-                &format_args!("{}", self.b_roi_region5_qp().bits()),
-            )
-            .field(
-                "b_roi_region6_qp",
-                &format_args!("{}", self.b_roi_region6_qp().bits()),
-            )
-            .field(
-                "b_roi_region7_qp",
-                &format_args!("{}", self.b_roi_region7_qp().bits()),
-            )
+            .field("b_roi_region4_qp", &self.b_roi_region4_qp())
+            .field("b_roi_region5_qp", &self.b_roi_region5_qp())
+            .field("b_roi_region6_qp", &self.b_roi_region6_qp())
+            .field("b_roi_region7_qp", &self.b_roi_region7_qp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_ROI_REGION4_7_QP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configure H264 ROI region4 qp in video B,fixed qp or delta qp."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_roi_region5.rs b/esp32p4/src/h264/b_roi_region5.rs
index 3a5ff314f3..2cae8d8abe 100644
--- a/esp32p4/src/h264/b_roi_region5.rs
+++ b/esp32p4/src/h264/b_roi_region5.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_ROI_REGION5")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_ROI_REGION5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontial start macroblocks of region 5 video B."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_roi_region6.rs b/esp32p4/src/h264/b_roi_region6.rs
index bb0def237d..07f16053df 100644
--- a/esp32p4/src/h264/b_roi_region6.rs
+++ b/esp32p4/src/h264/b_roi_region6.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_ROI_REGION6")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_ROI_REGION6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontial start macroblocks of region 6 video B."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_roi_region7.rs b/esp32p4/src/h264/b_roi_region7.rs
index 64cc7e900b..d9a7ef565f 100644
--- a/esp32p4/src/h264/b_roi_region7.rs
+++ b/esp32p4/src/h264/b_roi_region7.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_ROI_REGION7")
-            .field("x", &format_args!("{}", self.x().bits()))
-            .field("y", &format_args!("{}", self.y().bits()))
-            .field("x_len", &format_args!("{}", self.x_len().bits()))
-            .field("y_len", &format_args!("{}", self.y_len().bits()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("x", &self.x())
+            .field("y", &self.y())
+            .field("x_len", &self.x_len())
+            .field("y_len", &self.y_len())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_ROI_REGION7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures the horizontal start macroblocks of region 7 in video B."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_sys_conf.rs b/esp32p4/src/h264/b_sys_conf.rs
index 203f179514..cf3dd0f494 100644
--- a/esp32p4/src/h264/b_sys_conf.rs
+++ b/esp32p4/src/h264/b_sys_conf.rs
@@ -37,25 +37,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("B_SYS_CONF")
             .field(
                 "b_db_tmp_ready_trigger_mb_num",
-                &format_args!("{}", self.b_db_tmp_ready_trigger_mb_num().bits()),
+                &self.b_db_tmp_ready_trigger_mb_num(),
             )
             .field(
                 "b_rec_ready_trigger_mb_lines",
-                &format_args!("{}", self.b_rec_ready_trigger_mb_lines().bits()),
-            )
-            .field(
-                "b_intra_cost_cmp_offset",
-                &format_args!("{}", self.b_intra_cost_cmp_offset().bits()),
+                &self.b_rec_ready_trigger_mb_lines(),
             )
+            .field("b_intra_cost_cmp_offset", &self.b_intra_cost_cmp_offset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_SYS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures when to trigger video B H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/b_sys_mb_res.rs b/esp32p4/src/h264/b_sys_mb_res.rs
index cad28c9d40..d12e0d4640 100644
--- a/esp32p4/src/h264/b_sys_mb_res.rs
+++ b/esp32p4/src/h264/b_sys_mb_res.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("B_SYS_MB_RES")
-            .field(
-                "b_sys_total_mb_y",
-                &format_args!("{}", self.b_sys_total_mb_y().bits()),
-            )
-            .field(
-                "b_sys_total_mb_x",
-                &format_args!("{}", self.b_sys_total_mb_x().bits()),
-            )
+            .field("b_sys_total_mb_y", &self.b_sys_total_mb_y())
+            .field("b_sys_total_mb_x", &self.b_sys_total_mb_x())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<B_SYS_MB_RES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures video B vertical MB resolution."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/bs_threshold.rs b/esp32p4/src/h264/bs_threshold.rs
index 62aab64312..6ed31e05e6 100644
--- a/esp32p4/src/h264/bs_threshold.rs
+++ b/esp32p4/src/h264/bs_threshold.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BS_THRESHOLD")
-            .field(
-                "bs_buffer_threshold",
-                &format_args!("{}", self.bs_buffer_threshold().bits()),
-            )
+            .field("bs_buffer_threshold", &self.bs_buffer_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BS_THRESHOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Configures bitstream buffer overflow threshold. This value should be bigger than the encode bytes of one 4x4 submb."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/conf.rs b/esp32p4/src/h264/conf.rs
index e3f6b77a94..7270404525 100644
--- a/esp32p4/src/h264/conf.rs
+++ b/esp32p4/src/h264/conf.rs
@@ -242,98 +242,35 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "rec_ram_clk_en2",
-                &format_args!("{}", self.rec_ram_clk_en2().bit()),
-            )
-            .field(
-                "rec_ram_clk_en1",
-                &format_args!("{}", self.rec_ram_clk_en1().bit()),
-            )
-            .field(
-                "quant_ram_clk_en2",
-                &format_args!("{}", self.quant_ram_clk_en2().bit()),
-            )
-            .field(
-                "quant_ram_clk_en1",
-                &format_args!("{}", self.quant_ram_clk_en1().bit()),
-            )
-            .field(
-                "pre_ram_clk_en",
-                &format_args!("{}", self.pre_ram_clk_en().bit()),
-            )
-            .field(
-                "mvd_ram_clk_en",
-                &format_args!("{}", self.mvd_ram_clk_en().bit()),
-            )
-            .field(
-                "mc_ram_clk_en",
-                &format_args!("{}", self.mc_ram_clk_en().bit()),
-            )
-            .field(
-                "ref_ram_clk_en",
-                &format_args!("{}", self.ref_ram_clk_en().bit()),
-            )
-            .field(
-                "i4x4_ref_ram_clk_en",
-                &format_args!("{}", self.i4x4_ref_ram_clk_en().bit()),
-            )
-            .field(
-                "ime_ram_clk_en",
-                &format_args!("{}", self.ime_ram_clk_en().bit()),
-            )
-            .field(
-                "fme_ram_clk_en",
-                &format_args!("{}", self.fme_ram_clk_en().bit()),
-            )
-            .field(
-                "fetch_ram_clk_en",
-                &format_args!("{}", self.fetch_ram_clk_en().bit()),
-            )
-            .field(
-                "db_ram_clk_en",
-                &format_args!("{}", self.db_ram_clk_en().bit()),
-            )
-            .field(
-                "cur_mb_ram_clk_en",
-                &format_args!("{}", self.cur_mb_ram_clk_en().bit()),
-            )
-            .field(
-                "cavlc_ram_clk_en",
-                &format_args!("{}", self.cavlc_ram_clk_en().bit()),
-            )
-            .field("ime_clk_en", &format_args!("{}", self.ime_clk_en().bit()))
-            .field("fme_clk_en", &format_args!("{}", self.fme_clk_en().bit()))
-            .field("mc_clk_en", &format_args!("{}", self.mc_clk_en().bit()))
-            .field(
-                "interpolator_clk_en",
-                &format_args!("{}", self.interpolator_clk_en().bit()),
-            )
-            .field("db_clk_en", &format_args!("{}", self.db_clk_en().bit()))
-            .field(
-                "clavlc_clk_en",
-                &format_args!("{}", self.clavlc_clk_en().bit()),
-            )
-            .field(
-                "intra_clk_en",
-                &format_args!("{}", self.intra_clk_en().bit()),
-            )
-            .field("deci_clk_en", &format_args!("{}", self.deci_clk_en().bit()))
-            .field("bs_clk_en", &format_args!("{}", self.bs_clk_en().bit()))
-            .field(
-                "mv_merge_clk_en",
-                &format_args!("{}", self.mv_merge_clk_en().bit()),
-            )
+            .field("clk_en", &self.clk_en())
+            .field("rec_ram_clk_en2", &self.rec_ram_clk_en2())
+            .field("rec_ram_clk_en1", &self.rec_ram_clk_en1())
+            .field("quant_ram_clk_en2", &self.quant_ram_clk_en2())
+            .field("quant_ram_clk_en1", &self.quant_ram_clk_en1())
+            .field("pre_ram_clk_en", &self.pre_ram_clk_en())
+            .field("mvd_ram_clk_en", &self.mvd_ram_clk_en())
+            .field("mc_ram_clk_en", &self.mc_ram_clk_en())
+            .field("ref_ram_clk_en", &self.ref_ram_clk_en())
+            .field("i4x4_ref_ram_clk_en", &self.i4x4_ref_ram_clk_en())
+            .field("ime_ram_clk_en", &self.ime_ram_clk_en())
+            .field("fme_ram_clk_en", &self.fme_ram_clk_en())
+            .field("fetch_ram_clk_en", &self.fetch_ram_clk_en())
+            .field("db_ram_clk_en", &self.db_ram_clk_en())
+            .field("cur_mb_ram_clk_en", &self.cur_mb_ram_clk_en())
+            .field("cavlc_ram_clk_en", &self.cavlc_ram_clk_en())
+            .field("ime_clk_en", &self.ime_clk_en())
+            .field("fme_clk_en", &self.fme_clk_en())
+            .field("mc_clk_en", &self.mc_clk_en())
+            .field("interpolator_clk_en", &self.interpolator_clk_en())
+            .field("db_clk_en", &self.db_clk_en())
+            .field("clavlc_clk_en", &self.clavlc_clk_en())
+            .field("intra_clk_en", &self.intra_clk_en())
+            .field("deci_clk_en", &self.deci_clk_en())
+            .field("bs_clk_en", &self.bs_clk_en())
+            .field("mv_merge_clk_en", &self.mv_merge_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"]
     #[inline(always)]
diff --git a/esp32p4/src/h264/date.rs b/esp32p4/src/h264/date.rs
index 7196e1e598..c97798e5d4 100644
--- a/esp32p4/src/h264/date.rs
+++ b/esp32p4/src/h264/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("ledc_date", &format_args!("{}", self.ledc_date().bits()))
+            .field("ledc_date", &self.ledc_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Configures the version."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/debug_dma_sel.rs b/esp32p4/src/h264/debug_dma_sel.rs
index 97c12e5e1f..80666d82e0 100644
--- a/esp32p4/src/h264/debug_dma_sel.rs
+++ b/esp32p4/src/h264/debug_dma_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEBUG_DMA_SEL")
-            .field(
-                "dbg_dma_sel",
-                &format_args!("{}", self.dbg_dma_sel().bits()),
-            )
+            .field("dbg_dma_sel", &self.dbg_dma_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBUG_DMA_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Every bit represents a dma in h264"]
     #[inline(always)]
diff --git a/esp32p4/src/h264/debug_info0.rs b/esp32p4/src/h264/debug_info0.rs
index 0c1795bc28..037c87d0c6 100644
--- a/esp32p4/src/h264/debug_info0.rs
+++ b/esp32p4/src/h264/debug_info0.rs
@@ -71,49 +71,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DEBUG_INFO0")
             .field(
                 "top_ctrl_inter_debug_state",
-                &format_args!("{}", self.top_ctrl_inter_debug_state().bits()),
+                &self.top_ctrl_inter_debug_state(),
             )
             .field(
                 "top_ctrl_intra_debug_state",
-                &format_args!("{}", self.top_ctrl_intra_debug_state().bits()),
-            )
-            .field(
-                "p_i_cmp_debug_state",
-                &format_args!("{}", self.p_i_cmp_debug_state().bits()),
-            )
-            .field(
-                "mvd_debug_state",
-                &format_args!("{}", self.mvd_debug_state().bits()),
-            )
-            .field(
-                "mc_chroma_ip_debug_state",
-                &format_args!("{}", self.mc_chroma_ip_debug_state().bit()),
+                &self.top_ctrl_intra_debug_state(),
             )
+            .field("p_i_cmp_debug_state", &self.p_i_cmp_debug_state())
+            .field("mvd_debug_state", &self.mvd_debug_state())
+            .field("mc_chroma_ip_debug_state", &self.mc_chroma_ip_debug_state())
             .field(
                 "intra_16x16_chroma_ctrl_debug_state",
-                &format_args!("{}", self.intra_16x16_chroma_ctrl_debug_state().bits()),
+                &self.intra_16x16_chroma_ctrl_debug_state(),
             )
             .field(
                 "intra_4x4_ctrl_debug_state",
-                &format_args!("{}", self.intra_4x4_ctrl_debug_state().bits()),
+                &self.intra_4x4_ctrl_debug_state(),
             )
             .field(
                 "intra_top_ctrl_debug_state",
-                &format_args!("{}", self.intra_top_ctrl_debug_state().bits()),
-            )
-            .field(
-                "ime_ctrl_debug_state",
-                &format_args!("{}", self.ime_ctrl_debug_state().bits()),
+                &self.intra_top_ctrl_debug_state(),
             )
+            .field("ime_ctrl_debug_state", &self.ime_ctrl_debug_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBUG_INFO0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Debug information register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug_info0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEBUG_INFO0_SPEC;
 impl crate::RegisterSpec for DEBUG_INFO0_SPEC {
diff --git a/esp32p4/src/h264/debug_info1.rs b/esp32p4/src/h264/debug_info1.rs
index 2a67c89bc0..444fd65b41 100644
--- a/esp32p4/src/h264/debug_info1.rs
+++ b/esp32p4/src/h264/debug_info1.rs
@@ -55,43 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEBUG_INFO1")
-            .field(
-                "fme_ctrl_debug_state",
-                &format_args!("{}", self.fme_ctrl_debug_state().bits()),
-            )
-            .field(
-                "deci_calc_debug_state",
-                &format_args!("{}", self.deci_calc_debug_state().bits()),
-            )
-            .field(
-                "db_debug_state",
-                &format_args!("{}", self.db_debug_state().bits()),
-            )
-            .field(
-                "cavlc_enc_debug_state",
-                &format_args!("{}", self.cavlc_enc_debug_state().bits()),
-            )
-            .field(
-                "cavlc_scan_debug_state",
-                &format_args!("{}", self.cavlc_scan_debug_state().bits()),
-            )
-            .field(
-                "cavlc_ctrl_debug_state",
-                &format_args!("{}", self.cavlc_ctrl_debug_state().bits()),
-            )
-            .field(
-                "bs_buffer_debug_state",
-                &format_args!("{}", self.bs_buffer_debug_state().bit()),
-            )
+            .field("fme_ctrl_debug_state", &self.fme_ctrl_debug_state())
+            .field("deci_calc_debug_state", &self.deci_calc_debug_state())
+            .field("db_debug_state", &self.db_debug_state())
+            .field("cavlc_enc_debug_state", &self.cavlc_enc_debug_state())
+            .field("cavlc_scan_debug_state", &self.cavlc_scan_debug_state())
+            .field("cavlc_ctrl_debug_state", &self.cavlc_ctrl_debug_state())
+            .field("bs_buffer_debug_state", &self.bs_buffer_debug_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBUG_INFO1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Debug information register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug_info1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEBUG_INFO1_SPEC;
 impl crate::RegisterSpec for DEBUG_INFO1_SPEC {
diff --git a/esp32p4/src/h264/debug_info2.rs b/esp32p4/src/h264/debug_info2.rs
index 081a073b51..a692ac3a73 100644
--- a/esp32p4/src/h264/debug_info2.rs
+++ b/esp32p4/src/h264/debug_info2.rs
@@ -132,87 +132,51 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEBUG_INFO2")
-            .field(
-                "p_rc_done_debug_flag",
-                &format_args!("{}", self.p_rc_done_debug_flag().bit()),
-            )
+            .field("p_rc_done_debug_flag", &self.p_rc_done_debug_flag())
             .field(
                 "p_p_i_cmp_done_debug_flag",
-                &format_args!("{}", self.p_p_i_cmp_done_debug_flag().bit()),
+                &self.p_p_i_cmp_done_debug_flag(),
             )
             .field(
                 "p_mv_merge_done_debug_flag",
-                &format_args!("{}", self.p_mv_merge_done_debug_flag().bit()),
+                &self.p_mv_merge_done_debug_flag(),
             )
             .field(
                 "p_move_ori_done_debug_flag",
-                &format_args!("{}", self.p_move_ori_done_debug_flag().bit()),
-            )
-            .field(
-                "p_mc_done_debug_flag",
-                &format_args!("{}", self.p_mc_done_debug_flag().bit()),
-            )
-            .field(
-                "p_ime_done_debug_flag",
-                &format_args!("{}", self.p_ime_done_debug_flag().bit()),
+                &self.p_move_ori_done_debug_flag(),
             )
+            .field("p_mc_done_debug_flag", &self.p_mc_done_debug_flag())
+            .field("p_ime_done_debug_flag", &self.p_ime_done_debug_flag())
             .field(
                 "p_get_ori_done_debug_flag",
-                &format_args!("{}", self.p_get_ori_done_debug_flag().bit()),
-            )
-            .field(
-                "p_fme_done_debug_flag",
-                &format_args!("{}", self.p_fme_done_debug_flag().bit()),
-            )
-            .field(
-                "p_fetch_done_debug_flag",
-                &format_args!("{}", self.p_fetch_done_debug_flag().bit()),
-            )
-            .field(
-                "p_db_done_debug_flag",
-                &format_args!("{}", self.p_db_done_debug_flag().bit()),
-            )
-            .field(
-                "p_bs_buf_done_debug_flag",
-                &format_args!("{}", self.p_bs_buf_done_debug_flag().bit()),
+                &self.p_get_ori_done_debug_flag(),
             )
+            .field("p_fme_done_debug_flag", &self.p_fme_done_debug_flag())
+            .field("p_fetch_done_debug_flag", &self.p_fetch_done_debug_flag())
+            .field("p_db_done_debug_flag", &self.p_db_done_debug_flag())
+            .field("p_bs_buf_done_debug_flag", &self.p_bs_buf_done_debug_flag())
             .field(
                 "ref_move_2mb_line_done_debug_flag",
-                &format_args!("{}", self.ref_move_2mb_line_done_debug_flag().bit()),
+                &self.ref_move_2mb_line_done_debug_flag(),
             )
             .field(
                 "i_p_i_cmp_done_debug_flag",
-                &format_args!("{}", self.i_p_i_cmp_done_debug_flag().bit()),
+                &self.i_p_i_cmp_done_debug_flag(),
             )
             .field(
                 "i_move_ori_done_debug_flag",
-                &format_args!("{}", self.i_move_ori_done_debug_flag().bit()),
+                &self.i_move_ori_done_debug_flag(),
             )
             .field(
                 "i_get_ori_done_debug_flag",
-                &format_args!("{}", self.i_get_ori_done_debug_flag().bit()),
-            )
-            .field(
-                "i_ec_done_debug_flag",
-                &format_args!("{}", self.i_ec_done_debug_flag().bit()),
-            )
-            .field(
-                "i_db_done_debug_flag",
-                &format_args!("{}", self.i_db_done_debug_flag().bit()),
-            )
-            .field(
-                "i_bs_buf_done_debug_flag",
-                &format_args!("{}", self.i_bs_buf_done_debug_flag().bit()),
+                &self.i_get_ori_done_debug_flag(),
             )
+            .field("i_ec_done_debug_flag", &self.i_ec_done_debug_flag())
+            .field("i_db_done_debug_flag", &self.i_db_done_debug_flag())
+            .field("i_bs_buf_done_debug_flag", &self.i_bs_buf_done_debug_flag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBUG_INFO2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Debug information register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug_info2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEBUG_INFO2_SPEC;
 impl crate::RegisterSpec for DEBUG_INFO2_SPEC {
diff --git a/esp32p4/src/h264/frame_code_length.rs b/esp32p4/src/h264/frame_code_length.rs
index c800f50d1d..0b11eceef6 100644
--- a/esp32p4/src/h264/frame_code_length.rs
+++ b/esp32p4/src/h264/frame_code_length.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FRAME_CODE_LENGTH")
-            .field(
-                "frame_code_length",
-                &format_args!("{}", self.frame_code_length().bits()),
-            )
+            .field("frame_code_length", &self.frame_code_length())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FRAME_CODE_LENGTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Frame code byte length register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frame_code_length::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FRAME_CODE_LENGTH_SPEC;
 impl crate::RegisterSpec for FRAME_CODE_LENGTH_SPEC {
diff --git a/esp32p4/src/h264/gop_conf.rs b/esp32p4/src/h264/gop_conf.rs
index ef46bd4eb8..8f95ab9f68 100644
--- a/esp32p4/src/h264/gop_conf.rs
+++ b/esp32p4/src/h264/gop_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GOP_CONF")
-            .field(
-                "dual_stream_mode",
-                &format_args!("{}", self.dual_stream_mode().bit()),
-            )
-            .field("gop_num", &format_args!("{}", self.gop_num().bits()))
+            .field("dual_stream_mode", &self.dual_stream_mode())
+            .field("gop_num", &self.gop_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GOP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to enable dual stream mode. When this field is set to 1, H264_FRAME_MODE field must be set to 1 too.\\\\0: Normal mode\\\\1: Dual stream mode"]
     #[inline(always)]
diff --git a/esp32p4/src/h264/int_ena.rs b/esp32p4/src/h264/int_ena.rs
index 47356a4e01..7e11d7dc51 100644
--- a/esp32p4/src/h264/int_ena.rs
+++ b/esp32p4/src/h264/int_ena.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "db_tmp_ready",
-                &format_args!("{}", self.db_tmp_ready().bit()),
-            )
-            .field("rec_ready", &format_args!("{}", self.rec_ready().bit()))
-            .field("frame_done", &format_args!("{}", self.frame_done().bit()))
-            .field(
-                "dma_move_2mb_line_done",
-                &format_args!("{}", self.dma_move_2mb_line_done().bit()),
-            )
+            .field("db_tmp_ready", &self.db_tmp_ready())
+            .field("rec_ready", &self.rec_ready())
+            .field("frame_done", &self.frame_done())
+            .field("dma_move_2mb_line_done", &self.dma_move_2mb_line_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to enable H264_DB_TMP_READY_INT."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/int_raw.rs b/esp32p4/src/h264/int_raw.rs
index 7701dcc2e7..5f49fe2e18 100644
--- a/esp32p4/src/h264/int_raw.rs
+++ b/esp32p4/src/h264/int_raw.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "db_tmp_ready",
-                &format_args!("{}", self.db_tmp_ready().bit()),
-            )
-            .field("rec_ready", &format_args!("{}", self.rec_ready().bit()))
-            .field("frame_done", &format_args!("{}", self.frame_done().bit()))
-            .field(
-                "dma_move_2mb_line_done",
-                &format_args!("{}", self.dma_move_2mb_line_done().bit()),
-            )
+            .field("db_tmp_ready", &self.db_tmp_ready())
+            .field("rec_ready", &self.rec_ready())
+            .field("frame_done", &self.frame_done())
+            .field("dma_move_2mb_line_done", &self.dma_move_2mb_line_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Raw status bit: The raw interrupt status of H264_DB_TMP_READY_INT. Triggered when H264 written enough db tmp pixel."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/int_st.rs b/esp32p4/src/h264/int_st.rs
index 78cf37be23..95f27b60ca 100644
--- a/esp32p4/src/h264/int_st.rs
+++ b/esp32p4/src/h264/int_st.rs
@@ -34,25 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "db_tmp_ready",
-                &format_args!("{}", self.db_tmp_ready().bit()),
-            )
-            .field("rec_ready", &format_args!("{}", self.rec_ready().bit()))
-            .field("frame_done", &format_args!("{}", self.frame_done().bit()))
-            .field(
-                "dma_move_2mb_line_done",
-                &format_args!("{}", self.dma_move_2mb_line_done().bit()),
-            )
+            .field("db_tmp_ready", &self.db_tmp_ready())
+            .field("rec_ready", &self.rec_ready())
+            .field("frame_done", &self.frame_done())
+            .field("dma_move_2mb_line_done", &self.dma_move_2mb_line_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt masked status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/h264/mv_merge_config.rs b/esp32p4/src/h264/mv_merge_config.rs
index 2e29f32076..5ae05a8a26 100644
--- a/esp32p4/src/h264/mv_merge_config.rs
+++ b/esp32p4/src/h264/mv_merge_config.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MV_MERGE_CONFIG")
-            .field(
-                "mv_merge_type",
-                &format_args!("{}", self.mv_merge_type().bits()),
-            )
-            .field(
-                "int_mv_out_en",
-                &format_args!("{}", self.int_mv_out_en().bit()),
-            )
-            .field(
-                "a_mv_merge_en",
-                &format_args!("{}", self.a_mv_merge_en().bit()),
-            )
-            .field(
-                "b_mv_merge_en",
-                &format_args!("{}", self.b_mv_merge_en().bit()),
-            )
-            .field(
-                "mb_valid_num",
-                &format_args!("{}", self.mb_valid_num().bits()),
-            )
+            .field("mv_merge_type", &self.mv_merge_type())
+            .field("int_mv_out_en", &self.int_mv_out_en())
+            .field("a_mv_merge_en", &self.a_mv_merge_en())
+            .field("b_mv_merge_en", &self.b_mv_merge_en())
+            .field("mb_valid_num", &self.mb_valid_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MV_MERGE_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Configure mv merge type.\\\\0: merge p16x16 mv\\\\1: merge min mv\\\\2: merge max mv\\\\3: not valid."]
     #[inline(always)]
diff --git a/esp32p4/src/h264/rc_status0.rs b/esp32p4/src/h264/rc_status0.rs
index a751d12b8a..30cc0dde87 100644
--- a/esp32p4/src/h264/rc_status0.rs
+++ b/esp32p4/src/h264/rc_status0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RC_STATUS0")
-            .field(
-                "frame_mad_sum",
-                &format_args!("{}", self.frame_mad_sum().bits()),
-            )
+            .field("frame_mad_sum", &self.frame_mad_sum())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RC_STATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Rate control status register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc_status0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RC_STATUS0_SPEC;
 impl crate::RegisterSpec for RC_STATUS0_SPEC {
diff --git a/esp32p4/src/h264/rc_status1.rs b/esp32p4/src/h264/rc_status1.rs
index b18fddd884..bc23a708fe 100644
--- a/esp32p4/src/h264/rc_status1.rs
+++ b/esp32p4/src/h264/rc_status1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RC_STATUS1")
-            .field(
-                "frame_enc_bits",
-                &format_args!("{}", self.frame_enc_bits().bits()),
-            )
+            .field("frame_enc_bits", &self.frame_enc_bits())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RC_STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Rate control status register1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc_status1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RC_STATUS1_SPEC;
 impl crate::RegisterSpec for RC_STATUS1_SPEC {
diff --git a/esp32p4/src/h264/rc_status2.rs b/esp32p4/src/h264/rc_status2.rs
index 281cb6f32f..40e5a301fd 100644
--- a/esp32p4/src/h264/rc_status2.rs
+++ b/esp32p4/src/h264/rc_status2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RC_STATUS2")
-            .field(
-                "frame_qp_sum",
-                &format_args!("{}", self.frame_qp_sum().bits()),
-            )
+            .field("frame_qp_sum", &self.frame_qp_sum())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RC_STATUS2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Rate control status register2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc_status2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RC_STATUS2_SPEC;
 impl crate::RegisterSpec for RC_STATUS2_SPEC {
diff --git a/esp32p4/src/h264/slice_header_byte0.rs b/esp32p4/src/h264/slice_header_byte0.rs
index 1f2fa39e8a..b1633d393a 100644
--- a/esp32p4/src/h264/slice_header_byte0.rs
+++ b/esp32p4/src/h264/slice_header_byte0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLICE_HEADER_BYTE0")
-            .field(
-                "slice_byte_lsb",
-                &format_args!("{}", self.slice_byte_lsb().bits()),
-            )
+            .field("slice_byte_lsb", &self.slice_byte_lsb())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLICE_HEADER_BYTE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures Slice Header low 32 bit"]
     #[inline(always)]
diff --git a/esp32p4/src/h264/slice_header_byte1.rs b/esp32p4/src/h264/slice_header_byte1.rs
index 0ce3ad4fda..2989748f00 100644
--- a/esp32p4/src/h264/slice_header_byte1.rs
+++ b/esp32p4/src/h264/slice_header_byte1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLICE_HEADER_BYTE1")
-            .field(
-                "slice_byte_msb",
-                &format_args!("{}", self.slice_byte_msb().bits()),
-            )
+            .field("slice_byte_msb", &self.slice_byte_msb())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLICE_HEADER_BYTE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures Slice Header high 32 bit"]
     #[inline(always)]
diff --git a/esp32p4/src/h264/slice_header_byte_length.rs b/esp32p4/src/h264/slice_header_byte_length.rs
index 8e4eff7d7a..37a4bcf587 100644
--- a/esp32p4/src/h264/slice_header_byte_length.rs
+++ b/esp32p4/src/h264/slice_header_byte_length.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLICE_HEADER_BYTE_LENGTH")
-            .field(
-                "slice_byte_length",
-                &format_args!("{}", self.slice_byte_length().bits()),
-            )
+            .field("slice_byte_length", &self.slice_byte_length())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLICE_HEADER_BYTE_LENGTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Configures Slice Header byte number"]
     #[inline(always)]
diff --git a/esp32p4/src/h264/slice_header_remain.rs b/esp32p4/src/h264/slice_header_remain.rs
index 80cf37da70..7c541d71fa 100644
--- a/esp32p4/src/h264/slice_header_remain.rs
+++ b/esp32p4/src/h264/slice_header_remain.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLICE_HEADER_REMAIN")
-            .field(
-                "slice_remain_bitlength",
-                &format_args!("{}", self.slice_remain_bitlength().bits()),
-            )
-            .field(
-                "slice_remain_bit",
-                &format_args!("{}", self.slice_remain_bit().bits()),
-            )
+            .field("slice_remain_bitlength", &self.slice_remain_bitlength())
+            .field("slice_remain_bit", &self.slice_remain_bit())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLICE_HEADER_REMAIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Configures Slice Header remain bit number"]
     #[inline(always)]
diff --git a/esp32p4/src/h264/sys_ctrl.rs b/esp32p4/src/h264/sys_ctrl.rs
index ae0aa65e1b..065f0602c5 100644
--- a/esp32p4/src/h264/sys_ctrl.rs
+++ b/esp32p4/src/h264/sys_ctrl.rs
@@ -23,16 +23,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYS_CTRL")
-            .field("frame_mode", &format_args!("{}", self.frame_mode().bit()))
+            .field("frame_mode", &self.frame_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to start encoding one frame.\\\\0: Invalid. No effect\\\\1: Start encoding one frame"]
     #[inline(always)]
diff --git a/esp32p4/src/h264/sys_status.rs b/esp32p4/src/h264/sys_status.rs
index 998a9662de..3df5c5166d 100644
--- a/esp32p4/src/h264/sys_status.rs
+++ b/esp32p4/src/h264/sys_status.rs
@@ -27,21 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYS_STATUS")
-            .field("frame_num", &format_args!("{}", self.frame_num().bits()))
-            .field(
-                "dual_stream_sel",
-                &format_args!("{}", self.dual_stream_sel().bit()),
-            )
-            .field("intra_flag", &format_args!("{}", self.intra_flag().bit()))
+            .field("frame_num", &self.frame_num())
+            .field("dual_stream_sel", &self.dual_stream_sel())
+            .field("intra_flag", &self.intra_flag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYS_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "System status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SYS_STATUS_SPEC;
 impl crate::RegisterSpec for SYS_STATUS_SPEC {
diff --git a/esp32p4/src/h264_dma/counter_rst.rs b/esp32p4/src/h264_dma/counter_rst.rs
index 77b5a64621..3be20cbe9e 100644
--- a/esp32p4/src/h264_dma/counter_rst.rs
+++ b/esp32p4/src/h264_dma/counter_rst.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COUNTER_RST")
-            .field(
-                "rx_ch0_exter_counter_rst",
-                &format_args!("{}", self.rx_ch0_exter_counter_rst().bit()),
-            )
-            .field(
-                "rx_ch1_exter_counter_rst",
-                &format_args!("{}", self.rx_ch1_exter_counter_rst().bit()),
-            )
-            .field(
-                "rx_ch2_inter_counter_rst",
-                &format_args!("{}", self.rx_ch2_inter_counter_rst().bit()),
-            )
-            .field(
-                "rx_ch5_inter_counter_rst",
-                &format_args!("{}", self.rx_ch5_inter_counter_rst().bit()),
-            )
+            .field("rx_ch0_exter_counter_rst", &self.rx_ch0_exter_counter_rst())
+            .field("rx_ch1_exter_counter_rst", &self.rx_ch1_exter_counter_rst())
+            .field("rx_ch2_inter_counter_rst", &self.rx_ch2_inter_counter_rst())
+            .field("rx_ch5_inter_counter_rst", &self.rx_ch5_inter_counter_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COUNTER_RST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 then write 0 to this bit to reset rx ch0 counter."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/date.rs b/esp32p4/src/h264_dma/date.rs
index 36623dd792..0fa0c8da89 100644
--- a/esp32p4/src/h264_dma/date.rs
+++ b/esp32p4/src/h264_dma/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/h264_dma/exter_axi_err.rs b/esp32p4/src/h264_dma/exter_axi_err.rs
index 9413f39d3c..5461891abd 100644
--- a/esp32p4/src/h264_dma/exter_axi_err.rs
+++ b/esp32p4/src/h264_dma/exter_axi_err.rs
@@ -55,43 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXTER_AXI_ERR")
-            .field(
-                "exter_rid_err_cnt",
-                &format_args!("{}", self.exter_rid_err_cnt().bits()),
-            )
-            .field(
-                "exter_rresp_err_cnt",
-                &format_args!("{}", self.exter_rresp_err_cnt().bits()),
-            )
-            .field(
-                "exter_wresp_err_cnt",
-                &format_args!("{}", self.exter_wresp_err_cnt().bits()),
-            )
-            .field(
-                "exter_rd_fifo_cnt",
-                &format_args!("{}", self.exter_rd_fifo_cnt().bits()),
-            )
-            .field(
-                "exter_rd_bak_fifo_cnt",
-                &format_args!("{}", self.exter_rd_bak_fifo_cnt().bits()),
-            )
-            .field(
-                "exter_wr_fifo_cnt",
-                &format_args!("{}", self.exter_wr_fifo_cnt().bits()),
-            )
-            .field(
-                "exter_wr_bak_fifo_cnt",
-                &format_args!("{}", self.exter_wr_bak_fifo_cnt().bits()),
-            )
+            .field("exter_rid_err_cnt", &self.exter_rid_err_cnt())
+            .field("exter_rresp_err_cnt", &self.exter_rresp_err_cnt())
+            .field("exter_wresp_err_cnt", &self.exter_wresp_err_cnt())
+            .field("exter_rd_fifo_cnt", &self.exter_rd_fifo_cnt())
+            .field("exter_rd_bak_fifo_cnt", &self.exter_rd_bak_fifo_cnt())
+            .field("exter_wr_fifo_cnt", &self.exter_wr_fifo_cnt())
+            .field("exter_wr_bak_fifo_cnt", &self.exter_wr_bak_fifo_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTER_AXI_ERR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "exter memory axi err register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exter_axi_err::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXTER_AXI_ERR_SPEC;
 impl crate::RegisterSpec for EXTER_AXI_ERR_SPEC {
diff --git a/esp32p4/src/h264_dma/exter_mem_end_addr0.rs b/esp32p4/src/h264_dma/exter_mem_end_addr0.rs
index 2ad45a234f..6b3a18e440 100644
--- a/esp32p4/src/h264_dma/exter_mem_end_addr0.rs
+++ b/esp32p4/src/h264_dma/exter_mem_end_addr0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("EXTER_MEM_END_ADDR0")
             .field(
                 "access_exter_mem_end_addr0",
-                &format_args!("{}", self.access_exter_mem_end_addr0().bits()),
+                &self.access_exter_mem_end_addr0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTER_MEM_END_ADDR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/exter_mem_end_addr1.rs b/esp32p4/src/h264_dma/exter_mem_end_addr1.rs
index c94b0467cc..e7b73ba594 100644
--- a/esp32p4/src/h264_dma/exter_mem_end_addr1.rs
+++ b/esp32p4/src/h264_dma/exter_mem_end_addr1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("EXTER_MEM_END_ADDR1")
             .field(
                 "access_exter_mem_end_addr1",
-                &format_args!("{}", self.access_exter_mem_end_addr1().bits()),
+                &self.access_exter_mem_end_addr1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTER_MEM_END_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/exter_mem_start_addr0.rs b/esp32p4/src/h264_dma/exter_mem_start_addr0.rs
index 749902b746..7d206bf55f 100644
--- a/esp32p4/src/h264_dma/exter_mem_start_addr0.rs
+++ b/esp32p4/src/h264_dma/exter_mem_start_addr0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("EXTER_MEM_START_ADDR0")
             .field(
                 "access_exter_mem_start_addr0",
-                &format_args!("{}", self.access_exter_mem_start_addr0().bits()),
+                &self.access_exter_mem_start_addr0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTER_MEM_START_ADDR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The start address of accessible address space."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/exter_mem_start_addr1.rs b/esp32p4/src/h264_dma/exter_mem_start_addr1.rs
index 0ae2342c02..a876eb5aeb 100644
--- a/esp32p4/src/h264_dma/exter_mem_start_addr1.rs
+++ b/esp32p4/src/h264_dma/exter_mem_start_addr1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("EXTER_MEM_START_ADDR1")
             .field(
                 "access_exter_mem_start_addr1",
-                &format_args!("{}", self.access_exter_mem_start_addr1().bits()),
+                &self.access_exter_mem_start_addr1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTER_MEM_START_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The start address of accessible address space."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_arb_config.rs b/esp32p4/src/h264_dma/in_arb_config.rs
index c52b0e1978..a8cae79fb5 100644
--- a/esp32p4/src/h264_dma/in_arb_config.rs
+++ b/esp32p4/src/h264_dma/in_arb_config.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_ARB_CONFIG")
-            .field(
-                "in_arb_timeout_num",
-                &format_args!("{}", self.in_arb_timeout_num().bits()),
-            )
-            .field(
-                "in_weight_en",
-                &format_args!("{}", self.in_weight_en().bit()),
-            )
+            .field("in_arb_timeout_num", &self.in_arb_timeout_num())
+            .field("in_weight_en", &self.in_weight_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_ARB_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Set the max number of timeout count of arbiter"]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch/arb.rs b/esp32p4/src/h264_dma/in_ch/arb.rs
index 0ef8bf167a..4197950d74 100644
--- a/esp32p4/src/h264_dma/in_ch/arb.rs
+++ b/esp32p4/src/h264_dma/in_ch/arb.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB")
-            .field(
-                "in_arb_token_num",
-                &format_args!("{}", self.in_arb_token_num().bits()),
-            )
-            .field(
-                "exter_in_arb_priority",
-                &format_args!("{}", self.exter_in_arb_priority().bits()),
-            )
-            .field(
-                "inter_in_arb_priority",
-                &format_args!("{}", self.inter_in_arb_priority().bits()),
-            )
+            .field("in_arb_token_num", &self.in_arb_token_num())
+            .field("exter_in_arb_priority", &self.exter_in_arb_priority())
+            .field("inter_in_arb_priority", &self.inter_in_arb_priority())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Set the max number of token count of arbiter"]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch/buf_hb_rcv.rs b/esp32p4/src/h264_dma/in_ch/buf_hb_rcv.rs
index af08bc54dd..3b67f03c85 100644
--- a/esp32p4/src/h264_dma/in_ch/buf_hb_rcv.rs
+++ b/esp32p4/src/h264_dma/in_ch/buf_hb_rcv.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUF_HB_RCV")
-            .field(
-                "in_cmdfifo_buf_hb_rcv",
-                &format_args!("{}", self.in_cmdfifo_buf_hb_rcv().bits()),
-            )
+            .field("in_cmdfifo_buf_hb_rcv", &self.in_cmdfifo_buf_hb_rcv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUF_HB_RCV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX CH0 buf len hb rcv register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buf_hb_rcv::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUF_HB_RCV_SPEC;
 impl crate::RegisterSpec for BUF_HB_RCV_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch/conf0.rs b/esp32p4/src/h264_dma/in_ch/conf0.rs
index d97ab6b377..a05a230874 100644
--- a/esp32p4/src/h264_dma/in_ch/conf0.rs
+++ b/esp32p4/src/h264_dma/in_ch/conf0.rs
@@ -80,44 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field(
-                "indscr_burst_en",
-                &format_args!("{}", self.indscr_burst_en().bit()),
-            )
-            .field(
-                "in_ecc_aes_en",
-                &format_args!("{}", self.in_ecc_aes_en().bit()),
-            )
-            .field(
-                "in_check_owner",
-                &format_args!("{}", self.in_check_owner().bit()),
-            )
-            .field(
-                "in_mem_burst_length",
-                &format_args!("{}", self.in_mem_burst_length().bits()),
-            )
-            .field(
-                "in_page_bound_en",
-                &format_args!("{}", self.in_page_bound_en().bit()),
-            )
-            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
-            .field(
-                "in_cmd_disable",
-                &format_args!("{}", self.in_cmd_disable().bit()),
-            )
-            .field(
-                "in_arb_weight_opt_dis",
-                &format_args!("{}", self.in_arb_weight_opt_dis().bit()),
-            )
+            .field("indscr_burst_en", &self.indscr_burst_en())
+            .field("in_ecc_aes_en", &self.in_ecc_aes_en())
+            .field("in_check_owner", &self.in_check_owner())
+            .field("in_mem_burst_length", &self.in_mem_burst_length())
+            .field("in_page_bound_en", &self.in_page_bound_en())
+            .field("in_rst", &self.in_rst())
+            .field("in_cmd_disable", &self.in_cmd_disable())
+            .field("in_arb_weight_opt_dis", &self.in_arb_weight_opt_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch/dscr.rs b/esp32p4/src/h264_dma/in_ch/dscr.rs
index 94534f9d97..94b438cfb4 100644
--- a/esp32p4/src/h264_dma/in_ch/dscr.rs
+++ b/esp32p4/src/h264_dma/in_ch/dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSCR")
-            .field(
-                "inlink_dscr",
-                &format_args!("{}", self.inlink_dscr().bits()),
-            )
+            .field("inlink_dscr", &self.inlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX CHx next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DSCR_SPEC;
 impl crate::RegisterSpec for DSCR_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch/dscr_bf0.rs b/esp32p4/src/h264_dma/in_ch/dscr_bf0.rs
index 8e4ea08b1c..5bd4b3a47c 100644
--- a/esp32p4/src/h264_dma/in_ch/dscr_bf0.rs
+++ b/esp32p4/src/h264_dma/in_ch/dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSCR_BF0")
-            .field(
-                "inlink_dscr_bf0",
-                &format_args!("{}", self.inlink_dscr_bf0().bits()),
-            )
+            .field("inlink_dscr_bf0", &self.inlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX CHx last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DSCR_BF0_SPEC;
 impl crate::RegisterSpec for DSCR_BF0_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch/dscr_bf1.rs b/esp32p4/src/h264_dma/in_ch/dscr_bf1.rs
index 75794bf4be..204ca60919 100644
--- a/esp32p4/src/h264_dma/in_ch/dscr_bf1.rs
+++ b/esp32p4/src/h264_dma/in_ch/dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSCR_BF1")
-            .field(
-                "inlink_dscr_bf1",
-                &format_args!("{}", self.inlink_dscr_bf1().bits()),
-            )
+            .field("inlink_dscr_bf1", &self.inlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX CHx second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DSCR_BF1_SPEC;
 impl crate::RegisterSpec for DSCR_BF1_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch/err_eof_des_addr.rs b/esp32p4/src/h264_dma/in_ch/err_eof_des_addr.rs
index a9b122a75a..43d841419f 100644
--- a/esp32p4/src/h264_dma/in_ch/err_eof_des_addr.rs
+++ b/esp32p4/src/h264_dma/in_ch/err_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERR_EOF_DES_ADDR")
-            .field(
-                "in_err_eof_des_addr",
-                &format_args!("{}", self.in_err_eof_des_addr().bits()),
-            )
+            .field("in_err_eof_des_addr", &self.in_err_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERR_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX CHx err eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ERR_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for ERR_EOF_DES_ADDR_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch/etm_conf.rs b/esp32p4/src/h264_dma/in_ch/etm_conf.rs
index 1337d6c6b2..7754bcd9a8 100644
--- a/esp32p4/src/h264_dma/in_ch/etm_conf.rs
+++ b/esp32p4/src/h264_dma/in_ch/etm_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_CONF")
-            .field("in_etm_en", &format_args!("{}", self.in_etm_en().bit()))
-            .field(
-                "in_etm_loop_en",
-                &format_args!("{}", self.in_etm_loop_en().bit()),
-            )
-            .field(
-                "in_dscr_task_mak",
-                &format_args!("{}", self.in_dscr_task_mak().bits()),
-            )
+            .field("in_etm_en", &self.in_etm_en())
+            .field("in_etm_loop_en", &self.in_etm_loop_en())
+            .field("in_dscr_task_mak", &self.in_dscr_task_mak())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch/fifo_cnt.rs b/esp32p4/src/h264_dma/in_ch/fifo_cnt.rs
index 993e55efee..18c4c17346 100644
--- a/esp32p4/src/h264_dma/in_ch/fifo_cnt.rs
+++ b/esp32p4/src/h264_dma/in_ch/fifo_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CNT")
-            .field(
-                "in_cmdfifo_infifo_cnt",
-                &format_args!("{}", self.in_cmdfifo_infifo_cnt().bits()),
-            )
+            .field("in_cmdfifo_infifo_cnt", &self.in_cmdfifo_infifo_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX CHx fifo cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_CNT_SPEC;
 impl crate::RegisterSpec for FIFO_CNT_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch/fifo_status.rs b/esp32p4/src/h264_dma/in_ch/fifo_status.rs
index 981efd226f..1546154726 100644
--- a/esp32p4/src/h264_dma/in_ch/fifo_status.rs
+++ b/esp32p4/src/h264_dma/in_ch/fifo_status.rs
@@ -69,51 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_STATUS")
-            .field(
-                "infifo_full_l2",
-                &format_args!("{}", self.infifo_full_l2().bit()),
-            )
-            .field(
-                "infifo_empty_l2",
-                &format_args!("{}", self.infifo_empty_l2().bit()),
-            )
-            .field(
-                "infifo_cnt_l2",
-                &format_args!("{}", self.infifo_cnt_l2().bits()),
-            )
-            .field(
-                "infifo_full_l1",
-                &format_args!("{}", self.infifo_full_l1().bit()),
-            )
-            .field(
-                "infifo_empty_l1",
-                &format_args!("{}", self.infifo_empty_l1().bit()),
-            )
-            .field(
-                "infifo_cnt_l1",
-                &format_args!("{}", self.infifo_cnt_l1().bits()),
-            )
-            .field(
-                "infifo_full_l3",
-                &format_args!("{}", self.infifo_full_l3().bit()),
-            )
-            .field(
-                "infifo_empty_l3",
-                &format_args!("{}", self.infifo_empty_l3().bit()),
-            )
-            .field(
-                "infifo_cnt_l3",
-                &format_args!("{}", self.infifo_cnt_l3().bits()),
-            )
+            .field("infifo_full_l2", &self.infifo_full_l2())
+            .field("infifo_empty_l2", &self.infifo_empty_l2())
+            .field("infifo_cnt_l2", &self.infifo_cnt_l2())
+            .field("infifo_full_l1", &self.infifo_full_l1())
+            .field("infifo_empty_l1", &self.infifo_empty_l1())
+            .field("infifo_cnt_l1", &self.infifo_cnt_l1())
+            .field("infifo_full_l3", &self.infifo_full_l3())
+            .field("infifo_empty_l3", &self.infifo_empty_l3())
+            .field("infifo_cnt_l3", &self.infifo_cnt_l3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX CHx INFIFO status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_STATUS_SPEC;
 impl crate::RegisterSpec for FIFO_STATUS_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch/int_ena.rs b/esp32p4/src/h264_dma/in_ch/int_ena.rs
index 44f40e9c0a..c683a70c14 100644
--- a/esp32p4/src/h264_dma/in_ch/int_ena.rs
+++ b/esp32p4/src/h264_dma/in_ch/int_ena.rs
@@ -98,43 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "infifo_ovf_l1",
-                &format_args!("{}", self.infifo_ovf_l1().bit()),
-            )
-            .field(
-                "infifo_udf_l1",
-                &format_args!("{}", self.infifo_udf_l1().bit()),
-            )
-            .field(
-                "infifo_ovf_l2",
-                &format_args!("{}", self.infifo_ovf_l2().bit()),
-            )
-            .field(
-                "infifo_udf_l2",
-                &format_args!("{}", self.infifo_udf_l2().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "in_dscr_task_ovf",
-                &format_args!("{}", self.in_dscr_task_ovf().bit()),
-            )
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("infifo_ovf_l1", &self.infifo_ovf_l1())
+            .field("infifo_udf_l1", &self.infifo_udf_l1())
+            .field("infifo_ovf_l2", &self.infifo_ovf_l2())
+            .field("infifo_udf_l2", &self.infifo_udf_l2())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("in_dscr_task_ovf", &self.in_dscr_task_ovf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch/int_raw.rs b/esp32p4/src/h264_dma/in_ch/int_raw.rs
index 430969d724..f4d9494369 100644
--- a/esp32p4/src/h264_dma/in_ch/int_raw.rs
+++ b/esp32p4/src/h264_dma/in_ch/int_raw.rs
@@ -98,43 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "infifo_ovf_l1",
-                &format_args!("{}", self.infifo_ovf_l1().bit()),
-            )
-            .field(
-                "infifo_udf_l1",
-                &format_args!("{}", self.infifo_udf_l1().bit()),
-            )
-            .field(
-                "infifo_ovf_l2",
-                &format_args!("{}", self.infifo_ovf_l2().bit()),
-            )
-            .field(
-                "infifo_udf_l2",
-                &format_args!("{}", self.infifo_udf_l2().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "in_dscr_task_ovf",
-                &format_args!("{}", self.in_dscr_task_ovf().bit()),
-            )
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("infifo_ovf_l1", &self.infifo_ovf_l1())
+            .field("infifo_udf_l1", &self.infifo_udf_l1())
+            .field("infifo_ovf_l2", &self.infifo_ovf_l2())
+            .field("infifo_udf_l2", &self.infifo_udf_l2())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("in_dscr_task_ovf", &self.in_dscr_task_ovf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 0."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch/int_st.rs b/esp32p4/src/h264_dma/in_ch/int_st.rs
index fd71e8a83b..920e8bd824 100644
--- a/esp32p4/src/h264_dma/in_ch/int_st.rs
+++ b/esp32p4/src/h264_dma/in_ch/int_st.rs
@@ -76,43 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "infifo_ovf_l1",
-                &format_args!("{}", self.infifo_ovf_l1().bit()),
-            )
-            .field(
-                "infifo_udf_l1",
-                &format_args!("{}", self.infifo_udf_l1().bit()),
-            )
-            .field(
-                "infifo_ovf_l2",
-                &format_args!("{}", self.infifo_ovf_l2().bit()),
-            )
-            .field(
-                "infifo_udf_l2",
-                &format_args!("{}", self.infifo_udf_l2().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "in_dscr_task_ovf",
-                &format_args!("{}", self.in_dscr_task_ovf().bit()),
-            )
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("infifo_ovf_l1", &self.infifo_ovf_l1())
+            .field("infifo_udf_l1", &self.infifo_udf_l1())
+            .field("infifo_ovf_l2", &self.infifo_ovf_l2())
+            .field("infifo_udf_l2", &self.infifo_udf_l2())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("in_dscr_task_ovf", &self.in_dscr_task_ovf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX CHx interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch/link_addr.rs b/esp32p4/src/h264_dma/in_ch/link_addr.rs
index 7df196ffa2..3e231958b1 100644
--- a/esp32p4/src/h264_dma/in_ch/link_addr.rs
+++ b/esp32p4/src/h264_dma/in_ch/link_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LINK_ADDR")
-            .field(
-                "inlink_addr",
-                &format_args!("{}", self.inlink_addr().bits()),
-            )
+            .field("inlink_addr", &self.inlink_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LINK_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register stores the first inlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch/link_conf.rs b/esp32p4/src/h264_dma/in_ch/link_conf.rs
index c36645654b..962c4b8014 100644
--- a/esp32p4/src/h264_dma/in_ch/link_conf.rs
+++ b/esp32p4/src/h264_dma/in_ch/link_conf.rs
@@ -51,29 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LINK_CONF")
-            .field(
-                "inlink_auto_ret",
-                &format_args!("{}", self.inlink_auto_ret().bit()),
-            )
-            .field("inlink_stop", &format_args!("{}", self.inlink_stop().bit()))
-            .field(
-                "inlink_start",
-                &format_args!("{}", self.inlink_start().bit()),
-            )
-            .field(
-                "inlink_restart",
-                &format_args!("{}", self.inlink_restart().bit()),
-            )
-            .field("inlink_park", &format_args!("{}", self.inlink_park().bit()))
+            .field("inlink_auto_ret", &self.inlink_auto_ret())
+            .field("inlink_stop", &self.inlink_stop())
+            .field("inlink_start", &self.inlink_start())
+            .field("inlink_restart", &self.inlink_restart())
+            .field("inlink_park", &self.inlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LINK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch/pop.rs b/esp32p4/src/h264_dma/in_ch/pop.rs
index ae92b892a3..0715205520 100644
--- a/esp32p4/src/h264_dma/in_ch/pop.rs
+++ b/esp32p4/src/h264_dma/in_ch/pop.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POP")
-            .field(
-                "infifo_rdata",
-                &format_args!("{}", self.infifo_rdata().bits()),
-            )
-            .field("infifo_pop", &format_args!("{}", self.infifo_pop().bit()))
+            .field("infifo_rdata", &self.infifo_rdata())
+            .field("infifo_pop", &self.infifo_pop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 11 - Set this bit to pop data from DMA Rx FIFO."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch/pop_data_cnt.rs b/esp32p4/src/h264_dma/in_ch/pop_data_cnt.rs
index 6d8a919380..b7ea2cbde6 100644
--- a/esp32p4/src/h264_dma/in_ch/pop_data_cnt.rs
+++ b/esp32p4/src/h264_dma/in_ch/pop_data_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POP_DATA_CNT")
-            .field(
-                "in_cmdfifo_pop_data_cnt",
-                &format_args!("{}", self.in_cmdfifo_pop_data_cnt().bits()),
-            )
+            .field("in_cmdfifo_pop_data_cnt", &self.in_cmdfifo_pop_data_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POP_DATA_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX CHx pop data cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pop_data_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct POP_DATA_CNT_SPEC;
 impl crate::RegisterSpec for POP_DATA_CNT_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch/ro_pd_conf.rs b/esp32p4/src/h264_dma/in_ch/ro_pd_conf.rs
index bb5cb658ca..b6d46cadb5 100644
--- a/esp32p4/src/h264_dma/in_ch/ro_pd_conf.rs
+++ b/esp32p4/src/h264_dma/in_ch/ro_pd_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RO_PD_CONF")
-            .field(
-                "in_ro_ram_clk_fo",
-                &format_args!("{}", self.in_ro_ram_clk_fo().bit()),
-            )
+            .field("in_ro_ram_clk_fo", &self.in_ro_ram_clk_fo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RO_PD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - 1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch/state.rs b/esp32p4/src/h264_dma/in_ch/state.rs
index 2e01a835be..3d9162fbe1 100644
--- a/esp32p4/src/h264_dma/in_ch/state.rs
+++ b/esp32p4/src/h264_dma/in_ch/state.rs
@@ -34,28 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field(
-                "inlink_dscr_addr",
-                &format_args!("{}", self.inlink_dscr_addr().bits()),
-            )
-            .field(
-                "in_dscr_state",
-                &format_args!("{}", self.in_dscr_state().bits()),
-            )
-            .field("in_state", &format_args!("{}", self.in_state().bits()))
-            .field(
-                "in_reset_avail",
-                &format_args!("{}", self.in_reset_avail().bit()),
-            )
+            .field("inlink_dscr_addr", &self.inlink_dscr_addr())
+            .field("in_dscr_state", &self.in_dscr_state())
+            .field("in_state", &self.in_state())
+            .field("in_reset_avail", &self.in_reset_avail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX CHx state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch/suc_eof_des_addr.rs b/esp32p4/src/h264_dma/in_ch/suc_eof_des_addr.rs
index 1fa480066c..7579608a9b 100644
--- a/esp32p4/src/h264_dma/in_ch/suc_eof_des_addr.rs
+++ b/esp32p4/src/h264_dma/in_ch/suc_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SUC_EOF_DES_ADDR")
-            .field(
-                "in_suc_eof_des_addr",
-                &format_args!("{}", self.in_suc_eof_des_addr().bits()),
-            )
+            .field("in_suc_eof_des_addr", &self.in_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SUC_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX CHx eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`suc_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SUC_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for SUC_EOF_DES_ADDR_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch/xaddr.rs b/esp32p4/src/h264_dma/in_ch/xaddr.rs
index a72a91add6..0239f71971 100644
--- a/esp32p4/src/h264_dma/in_ch/xaddr.rs
+++ b/esp32p4/src/h264_dma/in_ch/xaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XADDR")
-            .field(
-                "in_cmdfifo_xaddr",
-                &format_args!("{}", self.in_cmdfifo_xaddr().bits()),
-            )
+            .field("in_cmdfifo_xaddr", &self.in_cmdfifo_xaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX CHx xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct XADDR_SPEC;
 impl crate::RegisterSpec for XADDR_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch5/arb.rs b/esp32p4/src/h264_dma/in_ch5/arb.rs
index d135fd6b5c..5aa80001f4 100644
--- a/esp32p4/src/h264_dma/in_ch5/arb.rs
+++ b/esp32p4/src/h264_dma/in_ch5/arb.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB")
-            .field(
-                "in_arb_token_num",
-                &format_args!("{}", self.in_arb_token_num().bits()),
-            )
-            .field(
-                "inter_in_arb_priority",
-                &format_args!("{}", self.inter_in_arb_priority().bits()),
-            )
+            .field("in_arb_token_num", &self.in_arb_token_num())
+            .field("inter_in_arb_priority", &self.inter_in_arb_priority())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Set the max number of token count of arbiter"]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch5/buf_hb_rcv.rs b/esp32p4/src/h264_dma/in_ch5/buf_hb_rcv.rs
index 924c4e1960..bf7c9517d6 100644
--- a/esp32p4/src/h264_dma/in_ch5/buf_hb_rcv.rs
+++ b/esp32p4/src/h264_dma/in_ch5/buf_hb_rcv.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUF_HB_RCV")
-            .field(
-                "in_cmdfifo_buf_hb_rcv",
-                &format_args!("{}", self.in_cmdfifo_buf_hb_rcv().bits()),
-            )
+            .field("in_cmdfifo_buf_hb_rcv", &self.in_cmdfifo_buf_hb_rcv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUF_HB_RCV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rx CH5 buf len hb rcv register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buf_hb_rcv::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUF_HB_RCV_SPEC;
 impl crate::RegisterSpec for BUF_HB_RCV_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch5/conf0.rs b/esp32p4/src/h264_dma/in_ch5/conf0.rs
index 69b8a80d4f..6e25c04874 100644
--- a/esp32p4/src/h264_dma/in_ch5/conf0.rs
+++ b/esp32p4/src/h264_dma/in_ch5/conf0.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field(
-                "in_ecc_aes_en",
-                &format_args!("{}", self.in_ecc_aes_en().bit()),
-            )
-            .field(
-                "in_mem_burst_length",
-                &format_args!("{}", self.in_mem_burst_length().bits()),
-            )
-            .field(
-                "in_page_bound_en",
-                &format_args!("{}", self.in_page_bound_en().bit()),
-            )
-            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
-            .field(
-                "in_cmd_disable",
-                &format_args!("{}", self.in_cmd_disable().bit()),
-            )
+            .field("in_ecc_aes_en", &self.in_ecc_aes_en())
+            .field("in_mem_burst_length", &self.in_mem_burst_length())
+            .field("in_page_bound_en", &self.in_page_bound_en())
+            .field("in_rst", &self.in_rst())
+            .field("in_cmd_disable", &self.in_cmd_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch5/conf1.rs b/esp32p4/src/h264_dma/in_ch5/conf1.rs
index 34b80afd54..5837ba68b0 100644
--- a/esp32p4/src/h264_dma/in_ch5/conf1.rs
+++ b/esp32p4/src/h264_dma/in_ch5/conf1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "block_start_addr",
-                &format_args!("{}", self.block_start_addr().bits()),
-            )
+            .field("block_start_addr", &self.block_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - RX Channel 5 destination start address"]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch5/conf2.rs b/esp32p4/src/h264_dma/in_ch5/conf2.rs
index 575fba73f4..c33911ffef 100644
--- a/esp32p4/src/h264_dma/in_ch5/conf2.rs
+++ b/esp32p4/src/h264_dma/in_ch5/conf2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF2")
-            .field(
-                "block_row_length_12line",
-                &format_args!("{}", self.block_row_length_12line().bits()),
-            )
-            .field(
-                "block_row_length_4line",
-                &format_args!("{}", self.block_row_length_4line().bits()),
-            )
+            .field("block_row_length_12line", &self.block_row_length_12line())
+            .field("block_row_length_4line", &self.block_row_length_4line())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The number of bytes contained in a row block 12line in RX channel 5"]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch5/conf3.rs b/esp32p4/src/h264_dma/in_ch5/conf3.rs
index e1aafb2c42..3264424735 100644
--- a/esp32p4/src/h264_dma/in_ch5/conf3.rs
+++ b/esp32p4/src/h264_dma/in_ch5/conf3.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF3")
-            .field(
-                "block_length_12line",
-                &format_args!("{}", self.block_length_12line().bits()),
-            )
-            .field(
-                "block_length_4line",
-                &format_args!("{}", self.block_length_4line().bits()),
-            )
+            .field("block_length_12line", &self.block_length_12line())
+            .field("block_length_4line", &self.block_length_4line())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - The number of bytes contained in a block 12line"]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch5/fifo_cnt.rs b/esp32p4/src/h264_dma/in_ch5/fifo_cnt.rs
index 04594cec74..7978ed252d 100644
--- a/esp32p4/src/h264_dma/in_ch5/fifo_cnt.rs
+++ b/esp32p4/src/h264_dma/in_ch5/fifo_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CNT")
-            .field(
-                "in_cmdfifo_infifo_cnt",
-                &format_args!("{}", self.in_cmdfifo_infifo_cnt().bits()),
-            )
+            .field("in_cmdfifo_infifo_cnt", &self.in_cmdfifo_infifo_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rx CH5 fifo cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_CNT_SPEC;
 impl crate::RegisterSpec for FIFO_CNT_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch5/fifo_status.rs b/esp32p4/src/h264_dma/in_ch5/fifo_status.rs
index 005f36ef3d..ecb8b51ef1 100644
--- a/esp32p4/src/h264_dma/in_ch5/fifo_status.rs
+++ b/esp32p4/src/h264_dma/in_ch5/fifo_status.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_STATUS")
-            .field(
-                "infifo_full_l1",
-                &format_args!("{}", self.infifo_full_l1().bit()),
-            )
-            .field(
-                "infifo_empty_l1",
-                &format_args!("{}", self.infifo_empty_l1().bit()),
-            )
-            .field(
-                "infifo_cnt_l1",
-                &format_args!("{}", self.infifo_cnt_l1().bits()),
-            )
+            .field("infifo_full_l1", &self.infifo_full_l1())
+            .field("infifo_empty_l1", &self.infifo_empty_l1())
+            .field("infifo_cnt_l1", &self.infifo_cnt_l1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX CH5 INFIFO status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_STATUS_SPEC;
 impl crate::RegisterSpec for FIFO_STATUS_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch5/int_ena.rs b/esp32p4/src/h264_dma/in_ch5/int_ena.rs
index 3748523dbc..b9283e1b44 100644
--- a/esp32p4/src/h264_dma/in_ch5/int_ena.rs
+++ b/esp32p4/src/h264_dma/in_ch5/int_ena.rs
@@ -53,29 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field(
-                "infifo_ovf_l1",
-                &format_args!("{}", self.infifo_ovf_l1().bit()),
-            )
-            .field(
-                "infifo_udf_l1",
-                &format_args!("{}", self.infifo_udf_l1().bit()),
-            )
-            .field(
-                "fetch_mb_col_cnt_ovf",
-                &format_args!("{}", self.fetch_mb_col_cnt_ovf().bit()),
-            )
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("infifo_ovf_l1", &self.infifo_ovf_l1())
+            .field("infifo_udf_l1", &self.infifo_udf_l1())
+            .field("fetch_mb_col_cnt_ovf", &self.fetch_mb_col_cnt_ovf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch5/int_raw.rs b/esp32p4/src/h264_dma/in_ch5/int_raw.rs
index ff8b48edd3..560f739c35 100644
--- a/esp32p4/src/h264_dma/in_ch5/int_raw.rs
+++ b/esp32p4/src/h264_dma/in_ch5/int_raw.rs
@@ -53,29 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field(
-                "infifo_ovf_l1",
-                &format_args!("{}", self.infifo_ovf_l1().bit()),
-            )
-            .field(
-                "infifo_udf_l1",
-                &format_args!("{}", self.infifo_udf_l1().bit()),
-            )
-            .field(
-                "fetch_mb_col_cnt_ovf",
-                &format_args!("{}", self.fetch_mb_col_cnt_ovf().bit()),
-            )
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("infifo_ovf_l1", &self.infifo_ovf_l1())
+            .field("infifo_udf_l1", &self.infifo_udf_l1())
+            .field("fetch_mb_col_cnt_ovf", &self.fetch_mb_col_cnt_ovf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch5/int_st.rs b/esp32p4/src/h264_dma/in_ch5/int_st.rs
index 0893e8468d..b1ae438f0c 100644
--- a/esp32p4/src/h264_dma/in_ch5/int_st.rs
+++ b/esp32p4/src/h264_dma/in_ch5/int_st.rs
@@ -41,29 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field(
-                "infifo_ovf_l1",
-                &format_args!("{}", self.infifo_ovf_l1().bit()),
-            )
-            .field(
-                "infifo_udf_l1",
-                &format_args!("{}", self.infifo_udf_l1().bit()),
-            )
-            .field(
-                "fetch_mb_col_cnt_ovf",
-                &format_args!("{}", self.fetch_mb_col_cnt_ovf().bit()),
-            )
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("infifo_ovf_l1", &self.infifo_ovf_l1())
+            .field("infifo_udf_l1", &self.infifo_udf_l1())
+            .field("fetch_mb_col_cnt_ovf", &self.fetch_mb_col_cnt_ovf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX CH5 interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch5/pop.rs b/esp32p4/src/h264_dma/in_ch5/pop.rs
index 229d9b7a77..e257ab2d83 100644
--- a/esp32p4/src/h264_dma/in_ch5/pop.rs
+++ b/esp32p4/src/h264_dma/in_ch5/pop.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POP")
-            .field(
-                "infifo_rdata",
-                &format_args!("{}", self.infifo_rdata().bits()),
-            )
-            .field("infifo_pop", &format_args!("{}", self.infifo_pop().bit()))
+            .field("infifo_rdata", &self.infifo_rdata())
+            .field("infifo_pop", &self.infifo_pop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 11 - Set this bit to pop data from DMA Rx FIFO."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/in_ch5/pop_data_cnt.rs b/esp32p4/src/h264_dma/in_ch5/pop_data_cnt.rs
index d2967e6682..f6c7192cc8 100644
--- a/esp32p4/src/h264_dma/in_ch5/pop_data_cnt.rs
+++ b/esp32p4/src/h264_dma/in_ch5/pop_data_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POP_DATA_CNT")
-            .field(
-                "in_cmdfifo_pop_data_cnt",
-                &format_args!("{}", self.in_cmdfifo_pop_data_cnt().bits()),
-            )
+            .field("in_cmdfifo_pop_data_cnt", &self.in_cmdfifo_pop_data_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POP_DATA_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rx CH5 pop data cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pop_data_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct POP_DATA_CNT_SPEC;
 impl crate::RegisterSpec for POP_DATA_CNT_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch5/state.rs b/esp32p4/src/h264_dma/in_ch5/state.rs
index bc2d2ebf83..5beebc9a47 100644
--- a/esp32p4/src/h264_dma/in_ch5/state.rs
+++ b/esp32p4/src/h264_dma/in_ch5/state.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("in_state", &format_args!("{}", self.in_state().bits()))
-            .field(
-                "in_reset_avail",
-                &format_args!("{}", self.in_reset_avail().bit()),
-            )
+            .field("in_state", &self.in_state())
+            .field("in_reset_avail", &self.in_reset_avail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX CH5 state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32p4/src/h264_dma/in_ch5/xaddr.rs b/esp32p4/src/h264_dma/in_ch5/xaddr.rs
index 10360b8694..c9cc8fb2a1 100644
--- a/esp32p4/src/h264_dma/in_ch5/xaddr.rs
+++ b/esp32p4/src/h264_dma/in_ch5/xaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XADDR")
-            .field(
-                "in_cmdfifo_xaddr",
-                &format_args!("{}", self.in_cmdfifo_xaddr().bits()),
-            )
+            .field("in_cmdfifo_xaddr", &self.in_cmdfifo_xaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rx CH5 xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct XADDR_SPEC;
 impl crate::RegisterSpec for XADDR_SPEC {
diff --git a/esp32p4/src/h264_dma/inter_axi_err.rs b/esp32p4/src/h264_dma/inter_axi_err.rs
index 421d3f0abf..6c5a9d3a36 100644
--- a/esp32p4/src/h264_dma/inter_axi_err.rs
+++ b/esp32p4/src/h264_dma/inter_axi_err.rs
@@ -55,43 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTER_AXI_ERR")
-            .field(
-                "inter_rid_err_cnt",
-                &format_args!("{}", self.inter_rid_err_cnt().bits()),
-            )
-            .field(
-                "inter_rresp_err_cnt",
-                &format_args!("{}", self.inter_rresp_err_cnt().bits()),
-            )
-            .field(
-                "inter_wresp_err_cnt",
-                &format_args!("{}", self.inter_wresp_err_cnt().bits()),
-            )
-            .field(
-                "inter_rd_fifo_cnt",
-                &format_args!("{}", self.inter_rd_fifo_cnt().bits()),
-            )
-            .field(
-                "inter_rd_bak_fifo_cnt",
-                &format_args!("{}", self.inter_rd_bak_fifo_cnt().bits()),
-            )
-            .field(
-                "inter_wr_fifo_cnt",
-                &format_args!("{}", self.inter_wr_fifo_cnt().bits()),
-            )
-            .field(
-                "inter_wr_bak_fifo_cnt",
-                &format_args!("{}", self.inter_wr_bak_fifo_cnt().bits()),
-            )
+            .field("inter_rid_err_cnt", &self.inter_rid_err_cnt())
+            .field("inter_rresp_err_cnt", &self.inter_rresp_err_cnt())
+            .field("inter_wresp_err_cnt", &self.inter_wresp_err_cnt())
+            .field("inter_rd_fifo_cnt", &self.inter_rd_fifo_cnt())
+            .field("inter_rd_bak_fifo_cnt", &self.inter_rd_bak_fifo_cnt())
+            .field("inter_wr_fifo_cnt", &self.inter_wr_fifo_cnt())
+            .field("inter_wr_bak_fifo_cnt", &self.inter_wr_bak_fifo_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTER_AXI_ERR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "inter memory axi err register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inter_axi_err::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTER_AXI_ERR_SPEC;
 impl crate::RegisterSpec for INTER_AXI_ERR_SPEC {
diff --git a/esp32p4/src/h264_dma/inter_mem_end_addr0.rs b/esp32p4/src/h264_dma/inter_mem_end_addr0.rs
index f31151ee23..3e3911ab11 100644
--- a/esp32p4/src/h264_dma/inter_mem_end_addr0.rs
+++ b/esp32p4/src/h264_dma/inter_mem_end_addr0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTER_MEM_END_ADDR0")
             .field(
                 "access_inter_mem_end_addr0",
-                &format_args!("{}", self.access_inter_mem_end_addr0().bits()),
+                &self.access_inter_mem_end_addr0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTER_MEM_END_ADDR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/inter_mem_end_addr1.rs b/esp32p4/src/h264_dma/inter_mem_end_addr1.rs
index 05c12bfd33..78bd321d13 100644
--- a/esp32p4/src/h264_dma/inter_mem_end_addr1.rs
+++ b/esp32p4/src/h264_dma/inter_mem_end_addr1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTER_MEM_END_ADDR1")
             .field(
                 "access_inter_mem_end_addr1",
-                &format_args!("{}", self.access_inter_mem_end_addr1().bits()),
+                &self.access_inter_mem_end_addr1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTER_MEM_END_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The end address of accessible address space. The access address beyond this range would lead to descriptor error."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/inter_mem_start_addr0.rs b/esp32p4/src/h264_dma/inter_mem_start_addr0.rs
index 2ce6db0829..47819ed005 100644
--- a/esp32p4/src/h264_dma/inter_mem_start_addr0.rs
+++ b/esp32p4/src/h264_dma/inter_mem_start_addr0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTER_MEM_START_ADDR0")
             .field(
                 "access_inter_mem_start_addr0",
-                &format_args!("{}", self.access_inter_mem_start_addr0().bits()),
+                &self.access_inter_mem_start_addr0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTER_MEM_START_ADDR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The start address of accessible address space."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/inter_mem_start_addr1.rs b/esp32p4/src/h264_dma/inter_mem_start_addr1.rs
index c4e3bc9c2a..b28cf6288e 100644
--- a/esp32p4/src/h264_dma/inter_mem_start_addr1.rs
+++ b/esp32p4/src/h264_dma/inter_mem_start_addr1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTER_MEM_START_ADDR1")
             .field(
                 "access_inter_mem_start_addr1",
-                &format_args!("{}", self.access_inter_mem_start_addr1().bits()),
+                &self.access_inter_mem_start_addr1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTER_MEM_START_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The start address of accessible address space."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/out_arb_config.rs b/esp32p4/src/h264_dma/out_arb_config.rs
index a7d92c2d25..2f37016c7f 100644
--- a/esp32p4/src/h264_dma/out_arb_config.rs
+++ b/esp32p4/src/h264_dma/out_arb_config.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_ARB_CONFIG")
-            .field(
-                "out_arb_timeout_num",
-                &format_args!("{}", self.out_arb_timeout_num().bits()),
-            )
-            .field(
-                "out_weight_en",
-                &format_args!("{}", self.out_weight_en().bit()),
-            )
+            .field("out_arb_timeout_num", &self.out_arb_timeout_num())
+            .field("out_weight_en", &self.out_weight_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_ARB_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Set the max number of timeout count of arbiter"]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/out_ch/arb.rs b/esp32p4/src/h264_dma/out_ch/arb.rs
index 56e35f2fdb..f4ed40ee3d 100644
--- a/esp32p4/src/h264_dma/out_ch/arb.rs
+++ b/esp32p4/src/h264_dma/out_ch/arb.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB")
-            .field(
-                "out_arb_token_num",
-                &format_args!("{}", self.out_arb_token_num().bits()),
-            )
-            .field(
-                "exter_out_arb_priority",
-                &format_args!("{}", self.exter_out_arb_priority().bits()),
-            )
-            .field(
-                "inter_out_arb_priority",
-                &format_args!("{}", self.inter_out_arb_priority().bit()),
-            )
+            .field("out_arb_token_num", &self.out_arb_token_num())
+            .field("exter_out_arb_priority", &self.exter_out_arb_priority())
+            .field("inter_out_arb_priority", &self.inter_out_arb_priority())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Set the max number of token count of arbiter"]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/out_ch/block_buf_len.rs b/esp32p4/src/h264_dma/out_ch/block_buf_len.rs
index fd5fc26995..85da5dfe9a 100644
--- a/esp32p4/src/h264_dma/out_ch/block_buf_len.rs
+++ b/esp32p4/src/h264_dma/out_ch/block_buf_len.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLOCK_BUF_LEN")
-            .field(
-                "out_block_buf_len",
-                &format_args!("{}", self.out_block_buf_len().bits()),
-            )
+            .field("out_block_buf_len", &self.out_block_buf_len())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLOCK_BUF_LEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TX CHx block buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`block_buf_len::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLOCK_BUF_LEN_SPEC;
 impl crate::RegisterSpec for BLOCK_BUF_LEN_SPEC {
diff --git a/esp32p4/src/h264_dma/out_ch/buf_len.rs b/esp32p4/src/h264_dma/out_ch/buf_len.rs
index 1586aa7f69..6d2eda0e6a 100644
--- a/esp32p4/src/h264_dma/out_ch/buf_len.rs
+++ b/esp32p4/src/h264_dma/out_ch/buf_len.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUF_LEN")
-            .field(
-                "out_cmdfifo_buf_len_hb",
-                &format_args!("{}", self.out_cmdfifo_buf_len_hb().bits()),
-            )
+            .field("out_cmdfifo_buf_len_hb", &self.out_cmdfifo_buf_len_hb())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUF_LEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TX CHx buf len register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buf_len::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUF_LEN_SPEC;
 impl crate::RegisterSpec for BUF_LEN_SPEC {
diff --git a/esp32p4/src/h264_dma/out_ch/conf0.rs b/esp32p4/src/h264_dma/out_ch/conf0.rs
index 6d7bafee6c..8d016d5923 100644
--- a/esp32p4/src/h264_dma/out_ch/conf0.rs
+++ b/esp32p4/src/h264_dma/out_ch/conf0.rs
@@ -107,56 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field(
-                "out_auto_wrback",
-                &format_args!("{}", self.out_auto_wrback().bit()),
-            )
-            .field(
-                "out_eof_mode",
-                &format_args!("{}", self.out_eof_mode().bit()),
-            )
-            .field(
-                "outdscr_burst_en",
-                &format_args!("{}", self.outdscr_burst_en().bit()),
-            )
-            .field(
-                "out_ecc_aes_en",
-                &format_args!("{}", self.out_ecc_aes_en().bit()),
-            )
-            .field(
-                "out_check_owner",
-                &format_args!("{}", self.out_check_owner().bit()),
-            )
-            .field(
-                "out_mem_burst_length",
-                &format_args!("{}", self.out_mem_burst_length().bits()),
-            )
-            .field(
-                "out_page_bound_en",
-                &format_args!("{}", self.out_page_bound_en().bit()),
-            )
-            .field(
-                "out_reorder_en",
-                &format_args!("{}", self.out_reorder_en().bit()),
-            )
-            .field("out_rst", &format_args!("{}", self.out_rst().bit()))
-            .field(
-                "out_cmd_disable",
-                &format_args!("{}", self.out_cmd_disable().bit()),
-            )
-            .field(
-                "out_arb_weight_opt_dis",
-                &format_args!("{}", self.out_arb_weight_opt_dis().bit()),
-            )
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("out_eof_mode", &self.out_eof_mode())
+            .field("outdscr_burst_en", &self.outdscr_burst_en())
+            .field("out_ecc_aes_en", &self.out_ecc_aes_en())
+            .field("out_check_owner", &self.out_check_owner())
+            .field("out_mem_burst_length", &self.out_mem_burst_length())
+            .field("out_page_bound_en", &self.out_page_bound_en())
+            .field("out_reorder_en", &self.out_reorder_en())
+            .field("out_rst", &self.out_rst())
+            .field("out_cmd_disable", &self.out_cmd_disable())
+            .field("out_arb_weight_opt_dis", &self.out_arb_weight_opt_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/out_ch/dscr.rs b/esp32p4/src/h264_dma/out_ch/dscr.rs
index f11f97d37b..e5f63eb1cf 100644
--- a/esp32p4/src/h264_dma/out_ch/dscr.rs
+++ b/esp32p4/src/h264_dma/out_ch/dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSCR")
-            .field(
-                "outlink_dscr",
-                &format_args!("{}", self.outlink_dscr().bits()),
-            )
+            .field("outlink_dscr", &self.outlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TX CHx next dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DSCR_SPEC;
 impl crate::RegisterSpec for DSCR_SPEC {
diff --git a/esp32p4/src/h264_dma/out_ch/dscr_bf0.rs b/esp32p4/src/h264_dma/out_ch/dscr_bf0.rs
index 9236bdd281..661e89d757 100644
--- a/esp32p4/src/h264_dma/out_ch/dscr_bf0.rs
+++ b/esp32p4/src/h264_dma/out_ch/dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSCR_BF0")
-            .field(
-                "outlink_dscr_bf0",
-                &format_args!("{}", self.outlink_dscr_bf0().bits()),
-            )
+            .field("outlink_dscr_bf0", &self.outlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TX CHx last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DSCR_BF0_SPEC;
 impl crate::RegisterSpec for DSCR_BF0_SPEC {
diff --git a/esp32p4/src/h264_dma/out_ch/dscr_bf1.rs b/esp32p4/src/h264_dma/out_ch/dscr_bf1.rs
index d1112e892c..7a47b45775 100644
--- a/esp32p4/src/h264_dma/out_ch/dscr_bf1.rs
+++ b/esp32p4/src/h264_dma/out_ch/dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSCR_BF1")
-            .field(
-                "outlink_dscr_bf1",
-                &format_args!("{}", self.outlink_dscr_bf1().bits()),
-            )
+            .field("outlink_dscr_bf1", &self.outlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TX CHx second-to-last dscr addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DSCR_BF1_SPEC;
 impl crate::RegisterSpec for DSCR_BF1_SPEC {
diff --git a/esp32p4/src/h264_dma/out_ch/eof_des_addr.rs b/esp32p4/src/h264_dma/out_ch/eof_des_addr.rs
index bafa4c435b..4500996cbd 100644
--- a/esp32p4/src/h264_dma/out_ch/eof_des_addr.rs
+++ b/esp32p4/src/h264_dma/out_ch/eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EOF_DES_ADDR")
-            .field(
-                "out_eof_des_addr",
-                &format_args!("{}", self.out_eof_des_addr().bits()),
-            )
+            .field("out_eof_des_addr", &self.out_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TX CHx eof des addr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for EOF_DES_ADDR_SPEC {
diff --git a/esp32p4/src/h264_dma/out_ch/etm_conf.rs b/esp32p4/src/h264_dma/out_ch/etm_conf.rs
index 7b36bfc7e2..04039f0c0d 100644
--- a/esp32p4/src/h264_dma/out_ch/etm_conf.rs
+++ b/esp32p4/src/h264_dma/out_ch/etm_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_CONF")
-            .field("out_etm_en", &format_args!("{}", self.out_etm_en().bit()))
-            .field(
-                "out_etm_loop_en",
-                &format_args!("{}", self.out_etm_loop_en().bit()),
-            )
-            .field(
-                "out_dscr_task_mak",
-                &format_args!("{}", self.out_dscr_task_mak().bits()),
-            )
+            .field("out_etm_en", &self.out_etm_en())
+            .field("out_etm_loop_en", &self.out_etm_loop_en())
+            .field("out_dscr_task_mak", &self.out_dscr_task_mak())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable ETM task function"]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/out_ch/fifo_bcnt.rs b/esp32p4/src/h264_dma/out_ch/fifo_bcnt.rs
index 71788eff46..8d1a15e769 100644
--- a/esp32p4/src/h264_dma/out_ch/fifo_bcnt.rs
+++ b/esp32p4/src/h264_dma/out_ch/fifo_bcnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_BCNT")
-            .field(
-                "out_cmdfifo_outfifo_bcnt",
-                &format_args!("{}", self.out_cmdfifo_outfifo_bcnt().bits()),
-            )
+            .field("out_cmdfifo_outfifo_bcnt", &self.out_cmdfifo_outfifo_bcnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_BCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TX CHx fifo byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_bcnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_BCNT_SPEC;
 impl crate::RegisterSpec for FIFO_BCNT_SPEC {
diff --git a/esp32p4/src/h264_dma/out_ch/fifo_status.rs b/esp32p4/src/h264_dma/out_ch/fifo_status.rs
index 980331a301..8371219a71 100644
--- a/esp32p4/src/h264_dma/out_ch/fifo_status.rs
+++ b/esp32p4/src/h264_dma/out_ch/fifo_status.rs
@@ -69,51 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_STATUS")
-            .field(
-                "outfifo_full_l2",
-                &format_args!("{}", self.outfifo_full_l2().bit()),
-            )
-            .field(
-                "outfifo_empty_l2",
-                &format_args!("{}", self.outfifo_empty_l2().bit()),
-            )
-            .field(
-                "outfifo_cnt_l2",
-                &format_args!("{}", self.outfifo_cnt_l2().bits()),
-            )
-            .field(
-                "outfifo_full_l1",
-                &format_args!("{}", self.outfifo_full_l1().bit()),
-            )
-            .field(
-                "outfifo_empty_l1",
-                &format_args!("{}", self.outfifo_empty_l1().bit()),
-            )
-            .field(
-                "outfifo_cnt_l1",
-                &format_args!("{}", self.outfifo_cnt_l1().bits()),
-            )
-            .field(
-                "outfifo_full_l3",
-                &format_args!("{}", self.outfifo_full_l3().bit()),
-            )
-            .field(
-                "outfifo_empty_l3",
-                &format_args!("{}", self.outfifo_empty_l3().bit()),
-            )
-            .field(
-                "outfifo_cnt_l3",
-                &format_args!("{}", self.outfifo_cnt_l3().bits()),
-            )
+            .field("outfifo_full_l2", &self.outfifo_full_l2())
+            .field("outfifo_empty_l2", &self.outfifo_empty_l2())
+            .field("outfifo_cnt_l2", &self.outfifo_cnt_l2())
+            .field("outfifo_full_l1", &self.outfifo_full_l1())
+            .field("outfifo_empty_l1", &self.outfifo_empty_l1())
+            .field("outfifo_cnt_l1", &self.outfifo_cnt_l1())
+            .field("outfifo_full_l3", &self.outfifo_full_l3())
+            .field("outfifo_empty_l3", &self.outfifo_empty_l3())
+            .field("outfifo_cnt_l3", &self.outfifo_cnt_l3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TX CHx outfifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_STATUS_SPEC;
 impl crate::RegisterSpec for FIFO_STATUS_SPEC {
diff --git a/esp32p4/src/h264_dma/out_ch/int_ena.rs b/esp32p4/src/h264_dma/out_ch/int_ena.rs
index 818a3f4629..2038d0e225 100644
--- a/esp32p4/src/h264_dma/out_ch/int_ena.rs
+++ b/esp32p4/src/h264_dma/out_ch/int_ena.rs
@@ -89,45 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field(
-                "outfifo_ovf_l1",
-                &format_args!("{}", self.outfifo_ovf_l1().bit()),
-            )
-            .field(
-                "outfifo_udf_l1",
-                &format_args!("{}", self.outfifo_udf_l1().bit()),
-            )
-            .field(
-                "outfifo_ovf_l2",
-                &format_args!("{}", self.outfifo_ovf_l2().bit()),
-            )
-            .field(
-                "outfifo_udf_l2",
-                &format_args!("{}", self.outfifo_udf_l2().bit()),
-            )
-            .field(
-                "out_dscr_task_ovf",
-                &format_args!("{}", self.out_dscr_task_ovf().bit()),
-            )
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf_l1", &self.outfifo_ovf_l1())
+            .field("outfifo_udf_l1", &self.outfifo_udf_l1())
+            .field("outfifo_ovf_l2", &self.outfifo_ovf_l2())
+            .field("outfifo_udf_l2", &self.outfifo_udf_l2())
+            .field("out_dscr_task_ovf", &self.out_dscr_task_ovf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/out_ch/int_raw.rs b/esp32p4/src/h264_dma/out_ch/int_raw.rs
index fe8bd8ec41..c8d36f4143 100644
--- a/esp32p4/src/h264_dma/out_ch/int_raw.rs
+++ b/esp32p4/src/h264_dma/out_ch/int_raw.rs
@@ -89,45 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field(
-                "outfifo_ovf_l1",
-                &format_args!("{}", self.outfifo_ovf_l1().bit()),
-            )
-            .field(
-                "outfifo_udf_l1",
-                &format_args!("{}", self.outfifo_udf_l1().bit()),
-            )
-            .field(
-                "outfifo_ovf_l2",
-                &format_args!("{}", self.outfifo_ovf_l2().bit()),
-            )
-            .field(
-                "outfifo_udf_l2",
-                &format_args!("{}", self.outfifo_udf_l2().bit()),
-            )
-            .field(
-                "out_dscr_task_ovf",
-                &format_args!("{}", self.out_dscr_task_ovf().bit()),
-            )
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf_l1", &self.outfifo_ovf_l1())
+            .field("outfifo_udf_l1", &self.outfifo_udf_l1())
+            .field("outfifo_ovf_l2", &self.outfifo_ovf_l2())
+            .field("outfifo_udf_l2", &self.outfifo_udf_l2())
+            .field("out_dscr_task_ovf", &self.out_dscr_task_ovf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/out_ch/int_st.rs b/esp32p4/src/h264_dma/out_ch/int_st.rs
index b452bf12ca..80b2cd7a89 100644
--- a/esp32p4/src/h264_dma/out_ch/int_st.rs
+++ b/esp32p4/src/h264_dma/out_ch/int_st.rs
@@ -69,45 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field(
-                "outfifo_ovf_l1",
-                &format_args!("{}", self.outfifo_ovf_l1().bit()),
-            )
-            .field(
-                "outfifo_udf_l1",
-                &format_args!("{}", self.outfifo_udf_l1().bit()),
-            )
-            .field(
-                "outfifo_ovf_l2",
-                &format_args!("{}", self.outfifo_ovf_l2().bit()),
-            )
-            .field(
-                "outfifo_udf_l2",
-                &format_args!("{}", self.outfifo_udf_l2().bit()),
-            )
-            .field(
-                "out_dscr_task_ovf",
-                &format_args!("{}", self.out_dscr_task_ovf().bit()),
-            )
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf_l1", &self.outfifo_ovf_l1())
+            .field("outfifo_udf_l1", &self.outfifo_udf_l1())
+            .field("outfifo_ovf_l2", &self.outfifo_ovf_l2())
+            .field("outfifo_udf_l2", &self.outfifo_udf_l2())
+            .field("out_dscr_task_ovf", &self.out_dscr_task_ovf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TX CHx interrupt st register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/h264_dma/out_ch/link_addr.rs b/esp32p4/src/h264_dma/out_ch/link_addr.rs
index 91f800376b..d002834a2c 100644
--- a/esp32p4/src/h264_dma/out_ch/link_addr.rs
+++ b/esp32p4/src/h264_dma/out_ch/link_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LINK_ADDR")
-            .field(
-                "outlink_addr",
-                &format_args!("{}", self.outlink_addr().bits()),
-            )
+            .field("outlink_addr", &self.outlink_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LINK_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register stores the first outlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/out_ch/link_conf.rs b/esp32p4/src/h264_dma/out_ch/link_conf.rs
index 43af1f34d7..fc31f22e33 100644
--- a/esp32p4/src/h264_dma/out_ch/link_conf.rs
+++ b/esp32p4/src/h264_dma/out_ch/link_conf.rs
@@ -42,31 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LINK_CONF")
-            .field(
-                "outlink_stop",
-                &format_args!("{}", self.outlink_stop().bit()),
-            )
-            .field(
-                "outlink_start",
-                &format_args!("{}", self.outlink_start().bit()),
-            )
-            .field(
-                "outlink_restart",
-                &format_args!("{}", self.outlink_restart().bit()),
-            )
-            .field(
-                "outlink_park",
-                &format_args!("{}", self.outlink_park().bit()),
-            )
+            .field("outlink_stop", &self.outlink_stop())
+            .field("outlink_start", &self.outlink_start())
+            .field("outlink_restart", &self.outlink_restart())
+            .field("outlink_park", &self.outlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LINK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - Set this bit to stop dealing with the outlink descriptors."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/out_ch/mode_enable.rs b/esp32p4/src/h264_dma/out_ch/mode_enable.rs
index e174b4795e..221ec1e9a3 100644
--- a/esp32p4/src/h264_dma/out_ch/mode_enable.rs
+++ b/esp32p4/src/h264_dma/out_ch/mode_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODE_ENABLE")
-            .field(
-                "out_test_mode_enable",
-                &format_args!("{}", self.out_test_mode_enable().bit()),
-            )
+            .field("out_test_mode_enable", &self.out_test_mode_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test mode"]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/out_ch/mode_yuv.rs b/esp32p4/src/h264_dma/out_ch/mode_yuv.rs
index e50da11e81..4d6f9f1f3b 100644
--- a/esp32p4/src/h264_dma/out_ch/mode_yuv.rs
+++ b/esp32p4/src/h264_dma/out_ch/mode_yuv.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODE_YUV")
-            .field(
-                "out_test_y_value",
-                &format_args!("{}", self.out_test_y_value().bits()),
-            )
-            .field(
-                "out_test_u_value",
-                &format_args!("{}", self.out_test_u_value().bits()),
-            )
-            .field(
-                "out_test_v_value",
-                &format_args!("{}", self.out_test_v_value().bits()),
-            )
+            .field("out_test_y_value", &self.out_test_y_value())
+            .field("out_test_u_value", &self.out_test_u_value())
+            .field("out_test_v_value", &self.out_test_v_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_YUV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - tx CH0 test mode y value"]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/out_ch/push.rs b/esp32p4/src/h264_dma/out_ch/push.rs
index 7e2e27362a..243fbc9d70 100644
--- a/esp32p4/src/h264_dma/out_ch/push.rs
+++ b/esp32p4/src/h264_dma/out_ch/push.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PUSH")
-            .field(
-                "outfifo_wdata_ch0",
-                &format_args!("{}", self.outfifo_wdata_ch0().bits()),
-            )
-            .field(
-                "outfifo_push_ch0",
-                &format_args!("{}", self.outfifo_push_ch0().bit()),
-            )
+            .field("outfifo_wdata_ch0", &self.outfifo_wdata_ch0())
+            .field("outfifo_push_ch0", &self.outfifo_push_ch0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PUSH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register stores the data that need to be pushed into DMA Tx FIFO."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/out_ch/push_bytecnt.rs b/esp32p4/src/h264_dma/out_ch/push_bytecnt.rs
index 4441309ae0..1d0c2cb77c 100644
--- a/esp32p4/src/h264_dma/out_ch/push_bytecnt.rs
+++ b/esp32p4/src/h264_dma/out_ch/push_bytecnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PUSH_BYTECNT")
-            .field(
-                "out_cmdfifo_push_bytecnt",
-                &format_args!("{}", self.out_cmdfifo_push_bytecnt().bits()),
-            )
+            .field("out_cmdfifo_push_bytecnt", &self.out_cmdfifo_push_bytecnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PUSH_BYTECNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TX CHx push byte cnt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`push_bytecnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PUSH_BYTECNT_SPEC;
 impl crate::RegisterSpec for PUSH_BYTECNT_SPEC {
diff --git a/esp32p4/src/h264_dma/out_ch/ro_pd_conf.rs b/esp32p4/src/h264_dma/out_ch/ro_pd_conf.rs
index 6e9e071541..e8f3dc2e45 100644
--- a/esp32p4/src/h264_dma/out_ch/ro_pd_conf.rs
+++ b/esp32p4/src/h264_dma/out_ch/ro_pd_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RO_PD_CONF")
-            .field(
-                "out_ro_ram_force_pd",
-                &format_args!("{}", self.out_ro_ram_force_pd().bit()),
-            )
-            .field(
-                "out_ro_ram_force_pu",
-                &format_args!("{}", self.out_ro_ram_force_pu().bit()),
-            )
-            .field(
-                "out_ro_ram_clk_fo",
-                &format_args!("{}", self.out_ro_ram_clk_fo().bit()),
-            )
+            .field("out_ro_ram_force_pd", &self.out_ro_ram_force_pd())
+            .field("out_ro_ram_force_pu", &self.out_ro_ram_force_pu())
+            .field("out_ro_ram_clk_fo", &self.out_ro_ram_clk_fo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RO_PD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - dma reorder ram power down"]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/out_ch/ro_status.rs b/esp32p4/src/h264_dma/out_ch/ro_status.rs
index 7ab195152e..35d746a3a5 100644
--- a/esp32p4/src/h264_dma/out_ch/ro_status.rs
+++ b/esp32p4/src/h264_dma/out_ch/ro_status.rs
@@ -41,35 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RO_STATUS")
-            .field(
-                "outfifo_ro_cnt",
-                &format_args!("{}", self.outfifo_ro_cnt().bits()),
-            )
-            .field(
-                "out_ro_wr_state",
-                &format_args!("{}", self.out_ro_wr_state().bits()),
-            )
-            .field(
-                "out_ro_rd_state",
-                &format_args!("{}", self.out_ro_rd_state().bits()),
-            )
-            .field(
-                "out_pixel_byte",
-                &format_args!("{}", self.out_pixel_byte().bits()),
-            )
-            .field(
-                "out_burst_block_num",
-                &format_args!("{}", self.out_burst_block_num().bits()),
-            )
+            .field("outfifo_ro_cnt", &self.outfifo_ro_cnt())
+            .field("out_ro_wr_state", &self.out_ro_wr_state())
+            .field("out_ro_rd_state", &self.out_ro_rd_state())
+            .field("out_pixel_byte", &self.out_pixel_byte())
+            .field("out_burst_block_num", &self.out_burst_block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TX CHx reorder status register. Available on CH0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ro_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RO_STATUS_SPEC;
 impl crate::RegisterSpec for RO_STATUS_SPEC {
diff --git a/esp32p4/src/h264_dma/out_ch/state.rs b/esp32p4/src/h264_dma/out_ch/state.rs
index 8b2eb64539..448b2bfd09 100644
--- a/esp32p4/src/h264_dma/out_ch/state.rs
+++ b/esp32p4/src/h264_dma/out_ch/state.rs
@@ -34,28 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field(
-                "outlink_dscr_addr",
-                &format_args!("{}", self.outlink_dscr_addr().bits()),
-            )
-            .field(
-                "out_dscr_state",
-                &format_args!("{}", self.out_dscr_state().bits()),
-            )
-            .field("out_state", &format_args!("{}", self.out_state().bits()))
-            .field(
-                "out_reset_avail",
-                &format_args!("{}", self.out_reset_avail().bit()),
-            )
+            .field("outlink_dscr_addr", &self.outlink_dscr_addr())
+            .field("out_dscr_state", &self.out_dscr_state())
+            .field("out_state", &self.out_state())
+            .field("out_reset_avail", &self.out_reset_avail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TX CHx state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32p4/src/h264_dma/out_ch/xaddr.rs b/esp32p4/src/h264_dma/out_ch/xaddr.rs
index 3ba59af8dd..58a4d97680 100644
--- a/esp32p4/src/h264_dma/out_ch/xaddr.rs
+++ b/esp32p4/src/h264_dma/out_ch/xaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XADDR")
-            .field(
-                "out_cmdfifo_xaddr",
-                &format_args!("{}", self.out_cmdfifo_xaddr().bits()),
-            )
+            .field("out_cmdfifo_xaddr", &self.out_cmdfifo_xaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TX CHx xaddr register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct XADDR_SPEC;
 impl crate::RegisterSpec for XADDR_SPEC {
diff --git a/esp32p4/src/h264_dma/rst_conf.rs b/esp32p4/src/h264_dma/rst_conf.rs
index 6cedcbf552..09fe922032 100644
--- a/esp32p4/src/h264_dma/rst_conf.rs
+++ b/esp32p4/src/h264_dma/rst_conf.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RST_CONF")
-            .field(
-                "inter_axim_rd_rst",
-                &format_args!("{}", self.inter_axim_rd_rst().bit()),
-            )
-            .field(
-                "inter_axim_wr_rst",
-                &format_args!("{}", self.inter_axim_wr_rst().bit()),
-            )
-            .field(
-                "exter_axim_rd_rst",
-                &format_args!("{}", self.exter_axim_rd_rst().bit()),
-            )
-            .field(
-                "exter_axim_wr_rst",
-                &format_args!("{}", self.exter_axim_wr_rst().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("inter_axim_rd_rst", &self.inter_axim_rd_rst())
+            .field("inter_axim_wr_rst", &self.inter_axim_wr_rst())
+            .field("exter_axim_rd_rst", &self.exter_axim_rd_rst())
+            .field("exter_axim_wr_rst", &self.exter_axim_wr_rst())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 then write 0 to this bit to reset axi master read data FIFO."]
     #[inline(always)]
diff --git a/esp32p4/src/h264_dma/rx_ch0_counter.rs b/esp32p4/src/h264_dma/rx_ch0_counter.rs
index 6981b5d352..2198e97381 100644
--- a/esp32p4/src/h264_dma/rx_ch0_counter.rs
+++ b/esp32p4/src/h264_dma/rx_ch0_counter.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CH0_COUNTER")
-            .field("rx_ch0_cnt", &format_args!("{}", self.rx_ch0_cnt().bits()))
+            .field("rx_ch0_cnt", &self.rx_ch0_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CH0_COUNTER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rx ch0 counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch0_counter::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_CH0_COUNTER_SPEC;
 impl crate::RegisterSpec for RX_CH0_COUNTER_SPEC {
diff --git a/esp32p4/src/h264_dma/rx_ch1_counter.rs b/esp32p4/src/h264_dma/rx_ch1_counter.rs
index 722a900b69..51431236f9 100644
--- a/esp32p4/src/h264_dma/rx_ch1_counter.rs
+++ b/esp32p4/src/h264_dma/rx_ch1_counter.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CH1_COUNTER")
-            .field("rx_ch1_cnt", &format_args!("{}", self.rx_ch1_cnt().bits()))
+            .field("rx_ch1_cnt", &self.rx_ch1_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CH1_COUNTER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rx ch1 counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch1_counter::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_CH1_COUNTER_SPEC;
 impl crate::RegisterSpec for RX_CH1_COUNTER_SPEC {
diff --git a/esp32p4/src/h264_dma/rx_ch2_counter.rs b/esp32p4/src/h264_dma/rx_ch2_counter.rs
index 3377b02454..f5d6703e97 100644
--- a/esp32p4/src/h264_dma/rx_ch2_counter.rs
+++ b/esp32p4/src/h264_dma/rx_ch2_counter.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CH2_COUNTER")
-            .field("rx_ch2_cnt", &format_args!("{}", self.rx_ch2_cnt().bits()))
+            .field("rx_ch2_cnt", &self.rx_ch2_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CH2_COUNTER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rx ch2 counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch2_counter::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_CH2_COUNTER_SPEC;
 impl crate::RegisterSpec for RX_CH2_COUNTER_SPEC {
diff --git a/esp32p4/src/h264_dma/rx_ch5_counter.rs b/esp32p4/src/h264_dma/rx_ch5_counter.rs
index 151c9c712f..7031d13467 100644
--- a/esp32p4/src/h264_dma/rx_ch5_counter.rs
+++ b/esp32p4/src/h264_dma/rx_ch5_counter.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CH5_COUNTER")
-            .field("rx_ch5_cnt", &format_args!("{}", self.rx_ch5_cnt().bits()))
+            .field("rx_ch5_cnt", &self.rx_ch5_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CH5_COUNTER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rx ch5 counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_ch5_counter::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_CH5_COUNTER_SPEC;
 impl crate::RegisterSpec for RX_CH5_COUNTER_SPEC {
diff --git a/esp32p4/src/hmac/date.rs b/esp32p4/src/hmac/date.rs
index dae408e040..451431dcfa 100644
--- a/esp32p4/src/hmac/date.rs
+++ b/esp32p4/src/hmac/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/hmac/query_busy.rs b/esp32p4/src/hmac/query_busy.rs
index b2162c1fb3..6f817e76f4 100644
--- a/esp32p4/src/hmac/query_busy.rs
+++ b/esp32p4/src/hmac/query_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_BUSY")
-            .field("busy_state", &format_args!("{}", self.busy_state().bit()))
+            .field("busy_state", &self.busy_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Busy register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_BUSY_SPEC;
 impl crate::RegisterSpec for QUERY_BUSY_SPEC {
diff --git a/esp32p4/src/hmac/query_error.rs b/esp32p4/src/hmac/query_error.rs
index dccd8dd32f..8f5b2d284b 100644
--- a/esp32p4/src/hmac/query_error.rs
+++ b/esp32p4/src/hmac/query_error.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_ERROR")
-            .field("query_check", &format_args!("{}", self.query_check().bit()))
+            .field("query_check", &self.query_check())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_ERROR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Error register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_error::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_ERROR_SPEC;
 impl crate::RegisterSpec for QUERY_ERROR_SPEC {
diff --git a/esp32p4/src/hmac/rd_result_mem.rs b/esp32p4/src/hmac/rd_result_mem.rs
index e93fc1892c..15ad43ddc6 100644
--- a/esp32p4/src/hmac/rd_result_mem.rs
+++ b/esp32p4/src/hmac/rd_result_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RESULT_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Result from upstream.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_result_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rd_result_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RESULT_MEM_SPEC;
diff --git a/esp32p4/src/hmac/wr_message_mem.rs b/esp32p4/src/hmac/wr_message_mem.rs
index e4eda3e0e5..2779a44011 100644
--- a/esp32p4/src/hmac/wr_message_mem.rs
+++ b/esp32p4/src/hmac/wr_message_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_MESSAGE_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Message block memory.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_message_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_message_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WR_MESSAGE_MEM_SPEC;
diff --git a/esp32p4/src/hp_sys/ahb2axi_bresp_err_int_ena.rs b/esp32p4/src/hp_sys/ahb2axi_bresp_err_int_ena.rs
index 7fc71f94a7..115437ab56 100644
--- a/esp32p4/src/hp_sys/ahb2axi_bresp_err_int_ena.rs
+++ b/esp32p4/src/hp_sys/ahb2axi_bresp_err_int_ena.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHB2AXI_BRESP_ERR_INT_ENA")
             .field(
                 "cpu_icm_h2x_bresp_err_int_ena",
-                &format_args!("{}", self.cpu_icm_h2x_bresp_err_int_ena().bit()),
+                &self.cpu_icm_h2x_bresp_err_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB2AXI_BRESP_ERR_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Write 1 to enable cpu_icm_h2x_bresp_err int"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/ahb2axi_bresp_err_int_raw.rs b/esp32p4/src/hp_sys/ahb2axi_bresp_err_int_raw.rs
index 6203217730..ef355bce02 100644
--- a/esp32p4/src/hp_sys/ahb2axi_bresp_err_int_raw.rs
+++ b/esp32p4/src/hp_sys/ahb2axi_bresp_err_int_raw.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHB2AXI_BRESP_ERR_INT_RAW")
             .field(
                 "cpu_icm_h2x_bresp_err_int_raw",
-                &format_args!("{}", self.cpu_icm_h2x_bresp_err_int_raw().bit()),
+                &self.cpu_icm_h2x_bresp_err_int_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB2AXI_BRESP_ERR_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi."]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/ahb2axi_bresp_err_int_st.rs b/esp32p4/src/hp_sys/ahb2axi_bresp_err_int_st.rs
index c92b76988a..e420a01197 100644
--- a/esp32p4/src/hp_sys/ahb2axi_bresp_err_int_st.rs
+++ b/esp32p4/src/hp_sys/ahb2axi_bresp_err_int_st.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHB2AXI_BRESP_ERR_INT_ST")
             .field(
                 "cpu_icm_h2x_bresp_err_int_st",
-                &format_args!("{}", self.cpu_icm_h2x_bresp_err_int_st().bit()),
+                &self.cpu_icm_h2x_bresp_err_int_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB2AXI_BRESP_ERR_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb2axi_bresp_err_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AHB2AXI_BRESP_ERR_INT_ST_SPEC;
 impl crate::RegisterSpec for AHB2AXI_BRESP_ERR_INT_ST_SPEC {
diff --git a/esp32p4/src/hp_sys/apb_sync_postw_en.rs b/esp32p4/src/hp_sys/apb_sync_postw_en.rs
index b8023f962a..5b6820f867 100644
--- a/esp32p4/src/hp_sys/apb_sync_postw_en.rs
+++ b/esp32p4/src/hp_sys/apb_sync_postw_en.rs
@@ -44,31 +44,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_SYNC_POSTW_EN")
-            .field(
-                "gmac_apb_postw_en",
-                &format_args!("{}", self.gmac_apb_postw_en().bit()),
-            )
-            .field(
-                "dsi_host_apb_postw_en",
-                &format_args!("{}", self.dsi_host_apb_postw_en().bit()),
-            )
+            .field("gmac_apb_postw_en", &self.gmac_apb_postw_en())
+            .field("dsi_host_apb_postw_en", &self.dsi_host_apb_postw_en())
             .field(
                 "csi_host_apb_sync_postw_en",
-                &format_args!("{}", self.csi_host_apb_sync_postw_en().bit()),
+                &self.csi_host_apb_sync_postw_en(),
             )
             .field(
                 "csi_host_apb_async_postw_en",
-                &format_args!("{}", self.csi_host_apb_async_postw_en().bit()),
+                &self.csi_host_apb_async_postw_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_SYNC_POSTW_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/bitscrambler_peri_sel.rs b/esp32p4/src/hp_sys/bitscrambler_peri_sel.rs
index f7d6a4a9c9..919a7e3cd0 100644
--- a/esp32p4/src/hp_sys/bitscrambler_peri_sel.rs
+++ b/esp32p4/src/hp_sys/bitscrambler_peri_sel.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BITSCRAMBLER_PERI_SEL")
-            .field(
-                "bitscrambler_peri_rx_sel",
-                &format_args!("{}", self.bitscrambler_peri_rx_sel().bits()),
-            )
-            .field(
-                "bitscrambler_peri_tx_sel",
-                &format_args!("{}", self.bitscrambler_peri_tx_sel().bits()),
-            )
+            .field("bitscrambler_peri_rx_sel", &self.bitscrambler_peri_rx_sel())
+            .field("bitscrambler_peri_tx_sel", &self.bitscrambler_peri_tx_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BITSCRAMBLER_PERI_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/cache_apb_postw_en.rs b/esp32p4/src/hp_sys/cache_apb_postw_en.rs
index c4488827b2..b7d1c0c659 100644
--- a/esp32p4/src/hp_sys/cache_apb_postw_en.rs
+++ b/esp32p4/src/hp_sys/cache_apb_postw_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_APB_POSTW_EN")
-            .field(
-                "reg_cache_apb_postw_en",
-                &format_args!("{}", self.reg_cache_apb_postw_en().bit()),
-            )
+            .field("reg_cache_apb_postw_en", &self.reg_cache_apb_postw_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_APB_POSTW_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/cache_clk_config.rs b/esp32p4/src/hp_sys/cache_clk_config.rs
index 3ed454e571..32b45e41f1 100644
--- a/esp32p4/src/hp_sys/cache_clk_config.rs
+++ b/esp32p4/src/hp_sys/cache_clk_config.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_CLK_CONFIG")
-            .field(
-                "reg_l2_cache_clk_on",
-                &format_args!("{}", self.reg_l2_cache_clk_on().bit()),
-            )
-            .field(
-                "reg_l1_d_cache_clk_on",
-                &format_args!("{}", self.reg_l1_d_cache_clk_on().bit()),
-            )
-            .field(
-                "reg_l1_i1_cache_clk_on",
-                &format_args!("{}", self.reg_l1_i1_cache_clk_on().bit()),
-            )
-            .field(
-                "reg_l1_i0_cache_clk_on",
-                &format_args!("{}", self.reg_l1_i0_cache_clk_on().bit()),
-            )
+            .field("reg_l2_cache_clk_on", &self.reg_l2_cache_clk_on())
+            .field("reg_l1_d_cache_clk_on", &self.reg_l1_d_cache_clk_on())
+            .field("reg_l1_i1_cache_clk_on", &self.reg_l1_i1_cache_clk_on())
+            .field("reg_l1_i0_cache_clk_on", &self.reg_l1_i0_cache_clk_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CLK_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - l2 cahce clk enable"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/cache_reset_config.rs b/esp32p4/src/hp_sys/cache_reset_config.rs
index 0696f15cc9..4bf4b141ea 100644
--- a/esp32p4/src/hp_sys/cache_reset_config.rs
+++ b/esp32p4/src/hp_sys/cache_reset_config.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_RESET_CONFIG")
-            .field(
-                "reg_l1_d_cache_reset",
-                &format_args!("{}", self.reg_l1_d_cache_reset().bit()),
-            )
-            .field(
-                "reg_l1_i1_cache_reset",
-                &format_args!("{}", self.reg_l1_i1_cache_reset().bit()),
-            )
-            .field(
-                "reg_l1_i0_cache_reset",
-                &format_args!("{}", self.reg_l1_i0_cache_reset().bit()),
-            )
+            .field("reg_l1_d_cache_reset", &self.reg_l1_d_cache_reset())
+            .field("reg_l1_i1_cache_reset", &self.reg_l1_i1_cache_reset())
+            .field("reg_l1_i0_cache_reset", &self.reg_l1_i0_cache_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_RESET_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - set 1 to reset l1 dcahce"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/clk_en.rs b/esp32p4/src/hp_sys/clk_en.rs
index 6b848cc176..b3a5ea6dee 100644
--- a/esp32p4/src/hp_sys/clk_en.rs
+++ b/esp32p4/src/hp_sys/clk_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EN")
-            .field("reg_clk_en", &format_args!("{}", self.reg_clk_en().bit()))
+            .field("reg_clk_en", &self.reg_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/core_ahb_timeout.rs b/esp32p4/src/hp_sys/core_ahb_timeout.rs
index e5cc9bdf99..8ee4f09157 100644
--- a/esp32p4/src/hp_sys/core_ahb_timeout.rs
+++ b/esp32p4/src/hp_sys/core_ahb_timeout.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_AHB_TIMEOUT")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("thres", &format_args!("{}", self.thres().bits()))
+            .field("en", &self.en())
+            .field("thres", &self.thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_AHB_TIMEOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this field to 1 to enable hp core0&amp;1 ahb timeout handle"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/core_dbus_timeout.rs b/esp32p4/src/hp_sys/core_dbus_timeout.rs
index 605fdc325c..844abdc8ae 100644
--- a/esp32p4/src/hp_sys/core_dbus_timeout.rs
+++ b/esp32p4/src/hp_sys/core_dbus_timeout.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_DBUS_TIMEOUT")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("thres", &format_args!("{}", self.thres().bits()))
+            .field("en", &self.en())
+            .field("thres", &self.thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_DBUS_TIMEOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this field to 1 to enable hp core0&amp;1 dbus timeout handle"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/core_debug_runstall_conf.rs b/esp32p4/src/hp_sys/core_debug_runstall_conf.rs
index 4e6a9bdea4..757d16d6aa 100644
--- a/esp32p4/src/hp_sys/core_debug_runstall_conf.rs
+++ b/esp32p4/src/hp_sys/core_debug_runstall_conf.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_DEBUG_RUNSTALL_CONF")
             .field(
                 "core_debug_runstall_enable",
-                &format_args!("{}", self.core_debug_runstall_enable().bit()),
+                &self.core_debug_runstall_enable(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_DEBUG_RUNSTALL_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this field to 1 to enable debug runstall feature between HP-core and LP-core."]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/core_dmactive_lpcore.rs b/esp32p4/src/hp_sys/core_dmactive_lpcore.rs
index a95bd04976..6709ca4a96 100644
--- a/esp32p4/src/hp_sys/core_dmactive_lpcore.rs
+++ b/esp32p4/src/hp_sys/core_dmactive_lpcore.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_DMACTIVE_LPCORE")
-            .field(
-                "core_dmactive_lpcore",
-                &format_args!("{}", self.core_dmactive_lpcore().bit()),
-            )
+            .field("core_dmactive_lpcore", &self.core_dmactive_lpcore())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_DMACTIVE_LPCORE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_dmactive_lpcore::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_DMACTIVE_LPCORE_SPEC;
 impl crate::RegisterSpec for CORE_DMACTIVE_LPCORE_SPEC {
diff --git a/esp32p4/src/hp_sys/core_err_resp_dis.rs b/esp32p4/src/hp_sys/core_err_resp_dis.rs
index c50d5c5d87..e47148a2a6 100644
--- a/esp32p4/src/hp_sys/core_err_resp_dis.rs
+++ b/esp32p4/src/hp_sys/core_err_resp_dis.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_ERR_RESP_DIS")
-            .field(
-                "core_err_resp_dis",
-                &format_args!("{}", self.core_err_resp_dis().bits()),
-            )
+            .field("core_err_resp_dis", &self.core_err_resp_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_ERR_RESP_DIS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp. Set bit 2 to disable ahb err resp."]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/core_ibus_timeout.rs b/esp32p4/src/hp_sys/core_ibus_timeout.rs
index 19b58af330..d67117f5a8 100644
--- a/esp32p4/src/hp_sys/core_ibus_timeout.rs
+++ b/esp32p4/src/hp_sys/core_ibus_timeout.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_IBUS_TIMEOUT")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("thres", &format_args!("{}", self.thres().bits()))
+            .field("en", &self.en())
+            .field("thres", &self.thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_IBUS_TIMEOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this field to 1 to enable hp core0&amp;1 ibus timeout handle"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/core_timeout_int_ena.rs b/esp32p4/src/hp_sys/core_timeout_int_ena.rs
index a3ee229274..88d9c830c8 100644
--- a/esp32p4/src/hp_sys/core_timeout_int_ena.rs
+++ b/esp32p4/src/hp_sys/core_timeout_int_ena.rs
@@ -64,37 +64,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_TIMEOUT_INT_ENA")
             .field(
                 "core0_ahb_timeout_int_ena",
-                &format_args!("{}", self.core0_ahb_timeout_int_ena().bit()),
+                &self.core0_ahb_timeout_int_ena(),
             )
             .field(
                 "core1_ahb_timeout_int_ena",
-                &format_args!("{}", self.core1_ahb_timeout_int_ena().bit()),
+                &self.core1_ahb_timeout_int_ena(),
             )
             .field(
                 "core0_ibus_timeout_int_ena",
-                &format_args!("{}", self.core0_ibus_timeout_int_ena().bit()),
+                &self.core0_ibus_timeout_int_ena(),
             )
             .field(
                 "core1_ibus_timeout_int_ena",
-                &format_args!("{}", self.core1_ibus_timeout_int_ena().bit()),
+                &self.core1_ibus_timeout_int_ena(),
             )
             .field(
                 "core0_dbus_timeout_int_ena",
-                &format_args!("{}", self.core0_dbus_timeout_int_ena().bit()),
+                &self.core0_dbus_timeout_int_ena(),
             )
             .field(
                 "core1_dbus_timeout_int_ena",
-                &format_args!("{}", self.core1_dbus_timeout_int_ena().bit()),
+                &self.core1_dbus_timeout_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_TIMEOUT_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to enable hp_core0_ahb_timeout int"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/core_timeout_int_raw.rs b/esp32p4/src/hp_sys/core_timeout_int_raw.rs
index af6d98173b..9391c70443 100644
--- a/esp32p4/src/hp_sys/core_timeout_int_raw.rs
+++ b/esp32p4/src/hp_sys/core_timeout_int_raw.rs
@@ -64,37 +64,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_TIMEOUT_INT_RAW")
             .field(
                 "core0_ahb_timeout_int_raw",
-                &format_args!("{}", self.core0_ahb_timeout_int_raw().bit()),
+                &self.core0_ahb_timeout_int_raw(),
             )
             .field(
                 "core1_ahb_timeout_int_raw",
-                &format_args!("{}", self.core1_ahb_timeout_int_raw().bit()),
+                &self.core1_ahb_timeout_int_raw(),
             )
             .field(
                 "core0_ibus_timeout_int_raw",
-                &format_args!("{}", self.core0_ibus_timeout_int_raw().bit()),
+                &self.core0_ibus_timeout_int_raw(),
             )
             .field(
                 "core1_ibus_timeout_int_raw",
-                &format_args!("{}", self.core1_ibus_timeout_int_raw().bit()),
+                &self.core1_ibus_timeout_int_raw(),
             )
             .field(
                 "core0_dbus_timeout_int_raw",
-                &format_args!("{}", self.core0_dbus_timeout_int_raw().bit()),
+                &self.core0_dbus_timeout_int_raw(),
             )
             .field(
                 "core1_dbus_timeout_int_raw",
-                &format_args!("{}", self.core1_dbus_timeout_int_raw().bit()),
+                &self.core1_dbus_timeout_int_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_TIMEOUT_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - the raw interrupt status of hp core0 ahb timeout"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/core_timeout_int_st.rs b/esp32p4/src/hp_sys/core_timeout_int_st.rs
index d3033d0d27..7d8f3170af 100644
--- a/esp32p4/src/hp_sys/core_timeout_int_st.rs
+++ b/esp32p4/src/hp_sys/core_timeout_int_st.rs
@@ -48,39 +48,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_TIMEOUT_INT_ST")
-            .field(
-                "core0_ahb_timeout_int_st",
-                &format_args!("{}", self.core0_ahb_timeout_int_st().bit()),
-            )
-            .field(
-                "core1_ahb_timeout_int_st",
-                &format_args!("{}", self.core1_ahb_timeout_int_st().bit()),
-            )
+            .field("core0_ahb_timeout_int_st", &self.core0_ahb_timeout_int_st())
+            .field("core1_ahb_timeout_int_st", &self.core1_ahb_timeout_int_st())
             .field(
                 "core0_ibus_timeout_int_st",
-                &format_args!("{}", self.core0_ibus_timeout_int_st().bit()),
+                &self.core0_ibus_timeout_int_st(),
             )
             .field(
                 "core1_ibus_timeout_int_st",
-                &format_args!("{}", self.core1_ibus_timeout_int_st().bit()),
+                &self.core1_ibus_timeout_int_st(),
             )
             .field(
                 "core0_dbus_timeout_int_st",
-                &format_args!("{}", self.core0_dbus_timeout_int_st().bit()),
+                &self.core0_dbus_timeout_int_st(),
             )
             .field(
                 "core1_dbus_timeout_int_st",
-                &format_args!("{}", self.core1_dbus_timeout_int_st().bit()),
+                &self.core1_dbus_timeout_int_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_TIMEOUT_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_timeout_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_TIMEOUT_INT_ST_SPEC;
 impl crate::RegisterSpec for CORE_TIMEOUT_INT_ST_SPEC {
diff --git a/esp32p4/src/hp_sys/cpu_corestalled_st.rs b/esp32p4/src/hp_sys/cpu_corestalled_st.rs
index 96cfdb3db6..dd7c07a706 100644
--- a/esp32p4/src/hp_sys/cpu_corestalled_st.rs
+++ b/esp32p4/src/hp_sys/cpu_corestalled_st.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_CORESTALLED_ST")
-            .field(
-                "reg_core0_corestalled_st",
-                &format_args!("{}", self.reg_core0_corestalled_st().bit()),
-            )
-            .field(
-                "reg_core1_corestalled_st",
-                &format_args!("{}", self.reg_core1_corestalled_st().bit()),
-            )
+            .field("reg_core0_corestalled_st", &self.reg_core0_corestalled_st())
+            .field("reg_core1_corestalled_st", &self.reg_core1_corestalled_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_CORESTALLED_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_corestalled_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPU_CORESTALLED_ST_SPEC;
 impl crate::RegisterSpec for CPU_CORESTALLED_ST_SPEC {
diff --git a/esp32p4/src/hp_sys/cpu_intr_from_cpu_0.rs b/esp32p4/src/hp_sys/cpu_intr_from_cpu_0.rs
index 90fce8e7d5..6a9c1e329a 100644
--- a/esp32p4/src/hp_sys/cpu_intr_from_cpu_0.rs
+++ b/esp32p4/src/hp_sys/cpu_intr_from_cpu_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_0")
-            .field(
-                "cpu_intr_from_cpu_0",
-                &format_args!("{}", self.cpu_intr_from_cpu_0().bit()),
-            )
+            .field("cpu_intr_from_cpu_0", &self.cpu_intr_from_cpu_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set 1 will triger a interrupt"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/cpu_intr_from_cpu_1.rs b/esp32p4/src/hp_sys/cpu_intr_from_cpu_1.rs
index 6b9bc094ab..2a4802df92 100644
--- a/esp32p4/src/hp_sys/cpu_intr_from_cpu_1.rs
+++ b/esp32p4/src/hp_sys/cpu_intr_from_cpu_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_1")
-            .field(
-                "cpu_intr_from_cpu_1",
-                &format_args!("{}", self.cpu_intr_from_cpu_1().bit()),
-            )
+            .field("cpu_intr_from_cpu_1", &self.cpu_intr_from_cpu_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set 1 will triger a interrupt"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/cpu_intr_from_cpu_2.rs b/esp32p4/src/hp_sys/cpu_intr_from_cpu_2.rs
index 6b95c1ce65..8b703dd18b 100644
--- a/esp32p4/src/hp_sys/cpu_intr_from_cpu_2.rs
+++ b/esp32p4/src/hp_sys/cpu_intr_from_cpu_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_2")
-            .field(
-                "cpu_intr_from_cpu_2",
-                &format_args!("{}", self.cpu_intr_from_cpu_2().bit()),
-            )
+            .field("cpu_intr_from_cpu_2", &self.cpu_intr_from_cpu_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set 1 will triger a interrupt"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/cpu_intr_from_cpu_3.rs b/esp32p4/src/hp_sys/cpu_intr_from_cpu_3.rs
index c2010abe66..ebafe0756f 100644
--- a/esp32p4/src/hp_sys/cpu_intr_from_cpu_3.rs
+++ b/esp32p4/src/hp_sys/cpu_intr_from_cpu_3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_3")
-            .field(
-                "cpu_intr_from_cpu_3",
-                &format_args!("{}", self.cpu_intr_from_cpu_3().bit()),
-            )
+            .field("cpu_intr_from_cpu_3", &self.cpu_intr_from_cpu_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set 1 will triger a interrupt"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/cpu_waiti_conf.rs b/esp32p4/src/hp_sys/cpu_waiti_conf.rs
index 5a89c7aff1..b4ca3f690d 100644
--- a/esp32p4/src/hp_sys/cpu_waiti_conf.rs
+++ b/esp32p4/src/hp_sys/cpu_waiti_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_WAITI_CONF")
-            .field(
-                "cpu_wait_mode_force_on",
-                &format_args!("{}", self.cpu_wait_mode_force_on().bit()),
-            )
-            .field(
-                "cpu_waiti_delay_num",
-                &format_args!("{}", self.cpu_waiti_delay_num().bits()),
-            )
+            .field("cpu_wait_mode_force_on", &self.cpu_wait_mode_force_on())
+            .field("cpu_waiti_delay_num", &self.cpu_waiti_delay_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_WAITI_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to force cpu_waiti_clk enable."]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/crypto_ctrl.rs b/esp32p4/src/hp_sys/crypto_ctrl.rs
index 117c1fc3a5..69d42a11d9 100644
--- a/esp32p4/src/hp_sys/crypto_ctrl.rs
+++ b/esp32p4/src/hp_sys/crypto_ctrl.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CRYPTO_CTRL")
             .field(
                 "reg_enable_spi_manual_encrypt",
-                &format_args!("{}", self.reg_enable_spi_manual_encrypt().bit()),
+                &self.reg_enable_spi_manual_encrypt(),
             )
             .field(
                 "reg_enable_download_db_encrypt",
-                &format_args!("{}", self.reg_enable_download_db_encrypt().bit()),
+                &self.reg_enable_download_db_encrypt(),
             )
             .field(
                 "reg_enable_download_g0cb_decrypt",
-                &format_args!("{}", self.reg_enable_download_g0cb_decrypt().bit()),
+                &self.reg_enable_download_g0cb_decrypt(),
             )
             .field(
                 "reg_enable_download_manual_encrypt",
-                &format_args!("{}", self.reg_enable_download_manual_encrypt().bit()),
+                &self.reg_enable_download_manual_encrypt(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CRYPTO_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/design_for_verification0.rs b/esp32p4/src/hp_sys/design_for_verification0.rs
index 427ee95f6e..a4a509aa44 100644
--- a/esp32p4/src/hp_sys/design_for_verification0.rs
+++ b/esp32p4/src/hp_sys/design_for_verification0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DESIGN_FOR_VERIFICATION0")
-            .field("dfv0", &format_args!("{}", self.dfv0().bits()))
+            .field("dfv0", &self.dfv0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DESIGN_FOR_VERIFICATION0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - register for DV"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/design_for_verification1.rs b/esp32p4/src/hp_sys/design_for_verification1.rs
index 51cd0d1f0b..3dcfc4bf33 100644
--- a/esp32p4/src/hp_sys/design_for_verification1.rs
+++ b/esp32p4/src/hp_sys/design_for_verification1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DESIGN_FOR_VERIFICATION1")
-            .field("dfv1", &format_args!("{}", self.dfv1().bits()))
+            .field("dfv1", &self.dfv1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DESIGN_FOR_VERIFICATION1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - register for DV"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/dma_addr_ctrl.rs b/esp32p4/src/hp_sys/dma_addr_ctrl.rs
index 27190b5d1e..8d2a005f22 100644
--- a/esp32p4/src/hp_sys/dma_addr_ctrl.rs
+++ b/esp32p4/src/hp_sys/dma_addr_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_ADDR_CTRL")
-            .field(
-                "reg_sys_dma_addr_sel",
-                &format_args!("{}", self.reg_sys_dma_addr_sel().bit()),
-            )
+            .field("reg_sys_dma_addr_sel", &self.reg_sys_dma_addr_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_ADDR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/ecc_pd_ctrl.rs b/esp32p4/src/hp_sys/ecc_pd_ctrl.rs
index ad72b06cc7..57386bd0a0 100644
--- a/esp32p4/src/hp_sys/ecc_pd_ctrl.rs
+++ b/esp32p4/src/hp_sys/ecc_pd_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_PD_CTRL")
-            .field(
-                "ecc_mem_force_pd",
-                &format_args!("{}", self.ecc_mem_force_pd().bit()),
-            )
-            .field(
-                "ecc_mem_force_pu",
-                &format_args!("{}", self.ecc_mem_force_pu().bit()),
-            )
-            .field("ecc_mem_pd", &format_args!("{}", self.ecc_mem_pd().bit()))
+            .field("ecc_mem_force_pd", &self.ecc_mem_force_pd())
+            .field("ecc_mem_force_pu", &self.ecc_mem_force_pu())
+            .field("ecc_mem_pd", &self.ecc_mem_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to power down ecc internal memory."]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/gdma_ctrl.rs b/esp32p4/src/hp_sys/gdma_ctrl.rs
index 81d18d0ee1..8e078aebcc 100644
--- a/esp32p4/src/hp_sys/gdma_ctrl.rs
+++ b/esp32p4/src/hp_sys/gdma_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GDMA_CTRL")
-            .field(
-                "debug_ch_num",
-                &format_args!("{}", self.debug_ch_num().bits()),
-            )
+            .field("debug_ch_num", &self.debug_ch_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GDMA_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/gmac_ctrl0.rs b/esp32p4/src/hp_sys/gmac_ctrl0.rs
index cba01eb369..7cd14e7f32 100644
--- a/esp32p4/src/hp_sys/gmac_ctrl0.rs
+++ b/esp32p4/src/hp_sys/gmac_ctrl0.rs
@@ -56,36 +56,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GMAC_CTRL0")
-            .field("ptp_pps", &format_args!("{}", self.ptp_pps().bit()))
-            .field(
-                "sbd_flowctrl",
-                &format_args!("{}", self.sbd_flowctrl().bit()),
-            )
-            .field(
-                "phy_intf_sel",
-                &format_args!("{}", self.phy_intf_sel().bits()),
-            )
-            .field(
-                "gmac_mem_clk_force_on",
-                &format_args!("{}", self.gmac_mem_clk_force_on().bit()),
-            )
-            .field(
-                "gmac_rst_clk_tx_n",
-                &format_args!("{}", self.gmac_rst_clk_tx_n().bit()),
-            )
-            .field(
-                "gmac_rst_clk_rx_n",
-                &format_args!("{}", self.gmac_rst_clk_rx_n().bit()),
-            )
+            .field("ptp_pps", &self.ptp_pps())
+            .field("sbd_flowctrl", &self.sbd_flowctrl())
+            .field("phy_intf_sel", &self.phy_intf_sel())
+            .field("gmac_mem_clk_force_on", &self.gmac_mem_clk_force_on())
+            .field("gmac_rst_clk_tx_n", &self.gmac_rst_clk_tx_n())
+            .field("gmac_rst_clk_rx_n", &self.gmac_rst_clk_rx_n())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GMAC_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/gmac_ctrl1.rs b/esp32p4/src/hp_sys/gmac_ctrl1.rs
index 5ceeaac396..c72ca99e6c 100644
--- a/esp32p4/src/hp_sys/gmac_ctrl1.rs
+++ b/esp32p4/src/hp_sys/gmac_ctrl1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GMAC_CTRL1")
-            .field(
-                "ptp_timestamp_l",
-                &format_args!("{}", self.ptp_timestamp_l().bits()),
-            )
+            .field("ptp_timestamp_l", &self.ptp_timestamp_l())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GMAC_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac_ctrl1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GMAC_CTRL1_SPEC;
 impl crate::RegisterSpec for GMAC_CTRL1_SPEC {
diff --git a/esp32p4/src/hp_sys/gmac_ctrl2.rs b/esp32p4/src/hp_sys/gmac_ctrl2.rs
index df470cf917..69e4157883 100644
--- a/esp32p4/src/hp_sys/gmac_ctrl2.rs
+++ b/esp32p4/src/hp_sys/gmac_ctrl2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GMAC_CTRL2")
-            .field(
-                "ptp_timestamp_h",
-                &format_args!("{}", self.ptp_timestamp_h().bits()),
-            )
+            .field("ptp_timestamp_h", &self.ptp_timestamp_h())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GMAC_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmac_ctrl2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GMAC_CTRL2_SPEC;
 impl crate::RegisterSpec for GMAC_CTRL2_SPEC {
diff --git a/esp32p4/src/hp_sys/gpio_ded_hold_ctrl.rs b/esp32p4/src/hp_sys/gpio_ded_hold_ctrl.rs
index 5dfc0b871e..500dd5cde5 100644
--- a/esp32p4/src/hp_sys/gpio_ded_hold_ctrl.rs
+++ b/esp32p4/src/hp_sys/gpio_ded_hold_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_DED_HOLD_CTRL")
-            .field(
-                "reg_gpio_ded_hold",
-                &format_args!("{}", self.reg_gpio_ded_hold().bits()),
-            )
+            .field("reg_gpio_ded_hold", &self.reg_gpio_ded_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_DED_HOLD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - hold control for gpio63~56"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/gpio_o_hold_ctrl0.rs b/esp32p4/src/hp_sys/gpio_o_hold_ctrl0.rs
index d2a7ed679e..92ce66a442 100644
--- a/esp32p4/src/hp_sys/gpio_o_hold_ctrl0.rs
+++ b/esp32p4/src/hp_sys/gpio_o_hold_ctrl0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_O_HOLD_CTRL0")
-            .field(
-                "reg_gpio_0_hold_low",
-                &format_args!("{}", self.reg_gpio_0_hold_low().bits()),
-            )
+            .field("reg_gpio_0_hold_low", &self.reg_gpio_0_hold_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_O_HOLD_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - hold control for gpio47~16"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/gpio_o_hold_ctrl1.rs b/esp32p4/src/hp_sys/gpio_o_hold_ctrl1.rs
index 201bca5921..0f562e42d5 100644
--- a/esp32p4/src/hp_sys/gpio_o_hold_ctrl1.rs
+++ b/esp32p4/src/hp_sys/gpio_o_hold_ctrl1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_O_HOLD_CTRL1")
-            .field(
-                "reg_gpio_0_hold_high",
-                &format_args!("{}", self.reg_gpio_0_hold_high().bits()),
-            )
+            .field("reg_gpio_0_hold_high", &self.reg_gpio_0_hold_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_O_HOLD_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - hold control for gpio56~48"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/gpio_o_hys_ctrl0.rs b/esp32p4/src/hp_sys/gpio_o_hys_ctrl0.rs
index f46313f90d..a80db83c47 100644
--- a/esp32p4/src/hp_sys/gpio_o_hys_ctrl0.rs
+++ b/esp32p4/src/hp_sys/gpio_o_hys_ctrl0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_O_HYS_CTRL0")
-            .field(
-                "reg_gpio_0_hys_low",
-                &format_args!("{}", self.reg_gpio_0_hys_low().bits()),
-            )
+            .field("reg_gpio_0_hys_low", &self.reg_gpio_0_hys_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_O_HYS_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - hys control for gpio47~16"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/gpio_o_hys_ctrl1.rs b/esp32p4/src/hp_sys/gpio_o_hys_ctrl1.rs
index 51ceb4c603..f9920c0958 100644
--- a/esp32p4/src/hp_sys/gpio_o_hys_ctrl1.rs
+++ b/esp32p4/src/hp_sys/gpio_o_hys_ctrl1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_O_HYS_CTRL1")
-            .field(
-                "reg_gpio_0_hys_high",
-                &format_args!("{}", self.reg_gpio_0_hys_high().bits()),
-            )
+            .field("reg_gpio_0_hys_high", &self.reg_gpio_0_hys_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_O_HYS_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - hys control for gpio56~48"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/icm_cpu_h2x_cfg.rs b/esp32p4/src/hp_sys/icm_cpu_h2x_cfg.rs
index ebad412724..2b322d6355 100644
--- a/esp32p4/src/hp_sys/icm_cpu_h2x_cfg.rs
+++ b/esp32p4/src/hp_sys/icm_cpu_h2x_cfg.rs
@@ -33,27 +33,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICM_CPU_H2X_CFG")
-            .field(
-                "cpu_icm_h2x_post_wr_en",
-                &format_args!("{}", self.cpu_icm_h2x_post_wr_en().bit()),
-            )
+            .field("cpu_icm_h2x_post_wr_en", &self.cpu_icm_h2x_post_wr_en())
             .field(
                 "cpu_icm_h2x_cut_through_en",
-                &format_args!("{}", self.cpu_icm_h2x_cut_through_en().bit()),
-            )
-            .field(
-                "cpu_icm_h2x_bridge_busy",
-                &format_args!("{}", self.cpu_icm_h2x_bridge_busy().bit()),
+                &self.cpu_icm_h2x_cut_through_en(),
             )
+            .field("cpu_icm_h2x_bridge_busy", &self.cpu_icm_h2x_bridge_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICM_CPU_H2X_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l1_cache_pwr_ctrl.rs b/esp32p4/src/hp_sys/l1_cache_pwr_ctrl.rs
index 2a5486c300..cc3c9637ce 100644
--- a/esp32p4/src/hp_sys/l1_cache_pwr_ctrl.rs
+++ b/esp32p4/src/hp_sys/l1_cache_pwr_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1_CACHE_PWR_CTRL")
-            .field(
-                "reg_l1_cache_mem_fo",
-                &format_args!("{}", self.reg_l1_cache_mem_fo().bits()),
-            )
+            .field("reg_l1_cache_mem_fo", &self.reg_l1_cache_mem_fo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1_CACHE_PWR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l1cache_bus0_id.rs b/esp32p4/src/hp_sys/l1cache_bus0_id.rs
index 764a6b127b..b2e3a40d2a 100644
--- a/esp32p4/src/hp_sys/l1cache_bus0_id.rs
+++ b/esp32p4/src/hp_sys/l1cache_bus0_id.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1CACHE_BUS0_ID")
-            .field(
-                "reg_l1_cache_bus0_id",
-                &format_args!("{}", self.reg_l1_cache_bus0_id().bits()),
-            )
+            .field("reg_l1_cache_bus0_id", &self.reg_l1_cache_bus0_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1CACHE_BUS0_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l1cache_bus1_id.rs b/esp32p4/src/hp_sys/l1cache_bus1_id.rs
index 1affa08a29..04aed76c2e 100644
--- a/esp32p4/src/hp_sys/l1cache_bus1_id.rs
+++ b/esp32p4/src/hp_sys/l1cache_bus1_id.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L1CACHE_BUS1_ID")
-            .field(
-                "reg_l1_cache_bus1_id",
-                &format_args!("{}", self.reg_l1_cache_bus1_id().bits()),
-            )
+            .field("reg_l1_cache_bus1_id", &self.reg_l1_cache_bus1_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L1CACHE_BUS1_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l2_cache_pwr_ctrl.rs b/esp32p4/src/hp_sys/l2_cache_pwr_ctrl.rs
index c8e268195a..8ed72c2a62 100644
--- a/esp32p4/src/hp_sys/l2_cache_pwr_ctrl.rs
+++ b/esp32p4/src/hp_sys/l2_cache_pwr_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_CACHE_PWR_CTRL")
-            .field(
-                "reg_l2_cache_mem_fo",
-                &format_args!("{}", self.reg_l2_cache_mem_fo().bits()),
-            )
+            .field("reg_l2_cache_mem_fo", &self.reg_l2_cache_mem_fo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_CACHE_PWR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l2_mem_ahb_buffer_ctrl.rs b/esp32p4/src/hp_sys/l2_mem_ahb_buffer_ctrl.rs
index f1aa5bc764..7cf65c873c 100644
--- a/esp32p4/src/hp_sys/l2_mem_ahb_buffer_ctrl.rs
+++ b/esp32p4/src/hp_sys/l2_mem_ahb_buffer_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_MEM_AHB_BUFFER_CTRL")
-            .field(
-                "l2_mem_ahb_wrbuffer_en",
-                &format_args!("{}", self.l2_mem_ahb_wrbuffer_en().bit()),
-            )
-            .field(
-                "l2_mem_ahb_rdbuffer_en",
-                &format_args!("{}", self.l2_mem_ahb_rdbuffer_en().bit()),
-            )
+            .field("l2_mem_ahb_wrbuffer_en", &self.l2_mem_ahb_wrbuffer_en())
+            .field("l2_mem_ahb_rdbuffer_en", &self.l2_mem_ahb_rdbuffer_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_AHB_BUFFER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to turn on l2mem ahb wr buffer"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l2_mem_err_resp_ctrl.rs b/esp32p4/src/hp_sys/l2_mem_err_resp_ctrl.rs
index 8499c6c142..7f3a684041 100644
--- a/esp32p4/src/hp_sys/l2_mem_err_resp_ctrl.rs
+++ b/esp32p4/src/hp_sys/l2_mem_err_resp_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_MEM_ERR_RESP_CTRL")
-            .field(
-                "l2_mem_err_resp_en",
-                &format_args!("{}", self.l2_mem_err_resp_en().bit()),
-            )
+            .field("l2_mem_err_resp_en", &self.l2_mem_err_resp_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_ERR_RESP_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to turn on l2mem error response"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l2_mem_int_ena.rs b/esp32p4/src/hp_sys/l2_mem_int_ena.rs
index eba31ff847..1fd560238f 100644
--- a/esp32p4/src/hp_sys/l2_mem_int_ena.rs
+++ b/esp32p4/src/hp_sys/l2_mem_int_ena.rs
@@ -37,25 +37,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_MEM_INT_ENA")
             .field(
                 "reg_l2_mem_ecc_err_int_ena",
-                &format_args!("{}", self.reg_l2_mem_ecc_err_int_ena().bit()),
+                &self.reg_l2_mem_ecc_err_int_ena(),
             )
             .field(
                 "reg_l2_mem_exceed_addr_int_ena",
-                &format_args!("{}", self.reg_l2_mem_exceed_addr_int_ena().bit()),
+                &self.reg_l2_mem_exceed_addr_int_ena(),
             )
             .field(
                 "reg_l2_mem_err_resp_int_ena",
-                &format_args!("{}", self.reg_l2_mem_err_resp_int_ena().bit()),
+                &self.reg_l2_mem_err_resp_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l2_mem_int_raw.rs b/esp32p4/src/hp_sys/l2_mem_int_raw.rs
index cb09c13ee3..9e253c516f 100644
--- a/esp32p4/src/hp_sys/l2_mem_int_raw.rs
+++ b/esp32p4/src/hp_sys/l2_mem_int_raw.rs
@@ -37,25 +37,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_MEM_INT_RAW")
             .field(
                 "reg_l2_mem_ecc_err_int_raw",
-                &format_args!("{}", self.reg_l2_mem_ecc_err_int_raw().bit()),
+                &self.reg_l2_mem_ecc_err_int_raw(),
             )
             .field(
                 "reg_l2_mem_exceed_addr_int_raw",
-                &format_args!("{}", self.reg_l2_mem_exceed_addr_int_raw().bit()),
+                &self.reg_l2_mem_exceed_addr_int_raw(),
             )
             .field(
                 "reg_l2_mem_err_resp_int_raw",
-                &format_args!("{}", self.reg_l2_mem_err_resp_int_raw().bit()),
+                &self.reg_l2_mem_err_resp_int_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - intr triggered when two bit error detected and corrected from ecc"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l2_mem_int_record0.rs b/esp32p4/src/hp_sys/l2_mem_int_record0.rs
index 7d20657781..732416ac0f 100644
--- a/esp32p4/src/hp_sys/l2_mem_int_record0.rs
+++ b/esp32p4/src/hp_sys/l2_mem_int_record0.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_MEM_INT_RECORD0")
             .field(
                 "reg_l2_mem_exceed_addr_int_addr",
-                &format_args!("{}", self.reg_l2_mem_exceed_addr_int_addr().bits()),
+                &self.reg_l2_mem_exceed_addr_int_addr(),
             )
             .field(
                 "reg_l2_mem_exceed_addr_int_we",
-                &format_args!("{}", self.reg_l2_mem_exceed_addr_int_we().bit()),
+                &self.reg_l2_mem_exceed_addr_int_we(),
             )
             .field(
                 "reg_l2_mem_exceed_addr_int_master",
-                &format_args!("{}", self.reg_l2_mem_exceed_addr_int_master().bits()),
+                &self.reg_l2_mem_exceed_addr_int_master(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_INT_RECORD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_mem_int_record0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_MEM_INT_RECORD0_SPEC;
 impl crate::RegisterSpec for L2_MEM_INT_RECORD0_SPEC {
diff --git a/esp32p4/src/hp_sys/l2_mem_int_record1.rs b/esp32p4/src/hp_sys/l2_mem_int_record1.rs
index c773b54faf..6950eae202 100644
--- a/esp32p4/src/hp_sys/l2_mem_int_record1.rs
+++ b/esp32p4/src/hp_sys/l2_mem_int_record1.rs
@@ -43,33 +43,21 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_MEM_INT_RECORD1")
             .field(
                 "reg_l2_mem_ecc_err_int_addr",
-                &format_args!("{}", self.reg_l2_mem_ecc_err_int_addr().bits()),
+                &self.reg_l2_mem_ecc_err_int_addr(),
             )
             .field(
                 "reg_l2_mem_ecc_one_bit_err",
-                &format_args!("{}", self.reg_l2_mem_ecc_one_bit_err().bit()),
+                &self.reg_l2_mem_ecc_one_bit_err(),
             )
             .field(
                 "reg_l2_mem_ecc_two_bit_err",
-                &format_args!("{}", self.reg_l2_mem_ecc_two_bit_err().bit()),
-            )
-            .field(
-                "reg_l2_mem_ecc_err_bit",
-                &format_args!("{}", self.reg_l2_mem_ecc_err_bit().bits()),
-            )
-            .field(
-                "reg_l2_cache_err_bank",
-                &format_args!("{}", self.reg_l2_cache_err_bank().bit()),
+                &self.reg_l2_mem_ecc_two_bit_err(),
             )
+            .field("reg_l2_mem_ecc_err_bit", &self.reg_l2_mem_ecc_err_bit())
+            .field("reg_l2_cache_err_bank", &self.reg_l2_cache_err_bank())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_INT_RECORD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_mem_int_record1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_MEM_INT_RECORD1_SPEC;
 impl crate::RegisterSpec for L2_MEM_INT_RECORD1_SPEC {
diff --git a/esp32p4/src/hp_sys/l2_mem_int_st.rs b/esp32p4/src/hp_sys/l2_mem_int_st.rs
index 2e544cde5d..16999fe12e 100644
--- a/esp32p4/src/hp_sys/l2_mem_int_st.rs
+++ b/esp32p4/src/hp_sys/l2_mem_int_st.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_MEM_INT_ST")
             .field(
                 "reg_l2_mem_ecc_err_int_st",
-                &format_args!("{}", self.reg_l2_mem_ecc_err_int_st().bit()),
+                &self.reg_l2_mem_ecc_err_int_st(),
             )
             .field(
                 "reg_l2_mem_exceed_addr_int_st",
-                &format_args!("{}", self.reg_l2_mem_exceed_addr_int_st().bit()),
+                &self.reg_l2_mem_exceed_addr_int_st(),
             )
             .field(
                 "reg_l2_mem_err_resp_int_st",
-                &format_args!("{}", self.reg_l2_mem_err_resp_int_st().bit()),
+                &self.reg_l2_mem_err_resp_int_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`l2_mem_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct L2_MEM_INT_ST_SPEC;
 impl crate::RegisterSpec for L2_MEM_INT_ST_SPEC {
diff --git a/esp32p4/src/hp_sys/l2_mem_l2_cache_ecc.rs b/esp32p4/src/hp_sys/l2_mem_l2_cache_ecc.rs
index 6387ba75e5..caef147e81 100644
--- a/esp32p4/src/hp_sys/l2_mem_l2_cache_ecc.rs
+++ b/esp32p4/src/hp_sys/l2_mem_l2_cache_ecc.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_MEM_L2_CACHE_ECC")
-            .field(
-                "reg_l2_cache_ecc_en",
-                &format_args!("{}", self.reg_l2_cache_ecc_en().bit()),
-            )
+            .field("reg_l2_cache_ecc_en", &self.reg_l2_cache_ecc_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_L2_CACHE_ECC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l2_mem_l2_ram_ecc.rs b/esp32p4/src/hp_sys/l2_mem_l2_ram_ecc.rs
index 2c24865759..e65288789e 100644
--- a/esp32p4/src/hp_sys/l2_mem_l2_ram_ecc.rs
+++ b/esp32p4/src/hp_sys/l2_mem_l2_ram_ecc.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_MEM_L2_RAM_ECC")
-            .field(
-                "reg_l2_ram_unit0_ecc_en",
-                &format_args!("{}", self.reg_l2_ram_unit0_ecc_en().bit()),
-            )
-            .field(
-                "reg_l2_ram_unit1_ecc_en",
-                &format_args!("{}", self.reg_l2_ram_unit1_ecc_en().bit()),
-            )
-            .field(
-                "reg_l2_ram_unit2_ecc_en",
-                &format_args!("{}", self.reg_l2_ram_unit2_ecc_en().bit()),
-            )
-            .field(
-                "reg_l2_ram_unit3_ecc_en",
-                &format_args!("{}", self.reg_l2_ram_unit3_ecc_en().bit()),
-            )
-            .field(
-                "reg_l2_ram_unit4_ecc_en",
-                &format_args!("{}", self.reg_l2_ram_unit4_ecc_en().bit()),
-            )
-            .field(
-                "reg_l2_ram_unit5_ecc_en",
-                &format_args!("{}", self.reg_l2_ram_unit5_ecc_en().bit()),
-            )
+            .field("reg_l2_ram_unit0_ecc_en", &self.reg_l2_ram_unit0_ecc_en())
+            .field("reg_l2_ram_unit1_ecc_en", &self.reg_l2_ram_unit1_ecc_en())
+            .field("reg_l2_ram_unit2_ecc_en", &self.reg_l2_ram_unit2_ecc_en())
+            .field("reg_l2_ram_unit3_ecc_en", &self.reg_l2_ram_unit3_ecc_en())
+            .field("reg_l2_ram_unit4_ecc_en", &self.reg_l2_ram_unit4_ecc_en())
+            .field("reg_l2_ram_unit5_ecc_en", &self.reg_l2_ram_unit5_ecc_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_L2_RAM_ECC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l2_mem_ram_pwr_ctrl0.rs b/esp32p4/src/hp_sys/l2_mem_ram_pwr_ctrl0.rs
index f1ed94d60b..0b60324608 100644
--- a/esp32p4/src/hp_sys/l2_mem_ram_pwr_ctrl0.rs
+++ b/esp32p4/src/hp_sys/l2_mem_ram_pwr_ctrl0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_MEM_RAM_PWR_CTRL0")
-            .field(
-                "reg_l2_mem_clk_force_on",
-                &format_args!("{}", self.reg_l2_mem_clk_force_on().bit()),
-            )
+            .field("reg_l2_mem_clk_force_on", &self.reg_l2_mem_clk_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_RAM_PWR_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - l2ram clk_gating force on"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l2_mem_rdn_eco_cs.rs b/esp32p4/src/hp_sys/l2_mem_rdn_eco_cs.rs
index f5f885b52b..4472d76e75 100644
--- a/esp32p4/src/hp_sys/l2_mem_rdn_eco_cs.rs
+++ b/esp32p4/src/hp_sys/l2_mem_rdn_eco_cs.rs
@@ -24,23 +24,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_MEM_RDN_ECO_CS")
-            .field(
-                "reg_l2_mem_rdn_eco_en",
-                &format_args!("{}", self.reg_l2_mem_rdn_eco_en().bit()),
-            )
+            .field("reg_l2_mem_rdn_eco_en", &self.reg_l2_mem_rdn_eco_en())
             .field(
                 "reg_l2_mem_rdn_eco_result",
-                &format_args!("{}", self.reg_l2_mem_rdn_eco_result().bit()),
+                &self.reg_l2_mem_rdn_eco_result(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_RDN_ECO_CS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l2_mem_rdn_eco_high.rs b/esp32p4/src/hp_sys/l2_mem_rdn_eco_high.rs
index 65dbd20caf..ea018eb798 100644
--- a/esp32p4/src/hp_sys/l2_mem_rdn_eco_high.rs
+++ b/esp32p4/src/hp_sys/l2_mem_rdn_eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_MEM_RDN_ECO_HIGH")
-            .field(
-                "reg_l2_mem_rdn_eco_high",
-                &format_args!("{}", self.reg_l2_mem_rdn_eco_high().bits()),
-            )
+            .field("reg_l2_mem_rdn_eco_high", &self.reg_l2_mem_rdn_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_RDN_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l2_mem_rdn_eco_low.rs b/esp32p4/src/hp_sys/l2_mem_rdn_eco_low.rs
index 5cdc014c5b..7aff8582c6 100644
--- a/esp32p4/src/hp_sys/l2_mem_rdn_eco_low.rs
+++ b/esp32p4/src/hp_sys/l2_mem_rdn_eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_MEM_RDN_ECO_LOW")
-            .field(
-                "reg_l2_mem_rdn_eco_low",
-                &format_args!("{}", self.reg_l2_mem_rdn_eco_low().bits()),
-            )
+            .field("reg_l2_mem_rdn_eco_low", &self.reg_l2_mem_rdn_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_RDN_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l2_mem_refresh.rs b/esp32p4/src/hp_sys/l2_mem_refresh.rs
index 57382badf3..d1e368bc2a 100644
--- a/esp32p4/src/hp_sys/l2_mem_refresh.rs
+++ b/esp32p4/src/hp_sys/l2_mem_refresh.rs
@@ -115,65 +115,59 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_MEM_REFRESH")
             .field(
                 "reg_l2_mem_unit0_refersh_en",
-                &format_args!("{}", self.reg_l2_mem_unit0_refersh_en().bit()),
+                &self.reg_l2_mem_unit0_refersh_en(),
             )
             .field(
                 "reg_l2_mem_unit1_refersh_en",
-                &format_args!("{}", self.reg_l2_mem_unit1_refersh_en().bit()),
+                &self.reg_l2_mem_unit1_refersh_en(),
             )
             .field(
                 "reg_l2_mem_unit2_refersh_en",
-                &format_args!("{}", self.reg_l2_mem_unit2_refersh_en().bit()),
+                &self.reg_l2_mem_unit2_refersh_en(),
             )
             .field(
                 "reg_l2_mem_unit3_refersh_en",
-                &format_args!("{}", self.reg_l2_mem_unit3_refersh_en().bit()),
+                &self.reg_l2_mem_unit3_refersh_en(),
             )
             .field(
                 "reg_l2_mem_unit4_refersh_en",
-                &format_args!("{}", self.reg_l2_mem_unit4_refersh_en().bit()),
+                &self.reg_l2_mem_unit4_refersh_en(),
             )
             .field(
                 "reg_l2_mem_unit5_refersh_en",
-                &format_args!("{}", self.reg_l2_mem_unit5_refersh_en().bit()),
+                &self.reg_l2_mem_unit5_refersh_en(),
             )
             .field(
                 "reg_l2_mem_refersh_cnt_reset",
-                &format_args!("{}", self.reg_l2_mem_refersh_cnt_reset().bit()),
+                &self.reg_l2_mem_refersh_cnt_reset(),
             )
             .field(
                 "reg_l2_mem_unit0_refresh_done",
-                &format_args!("{}", self.reg_l2_mem_unit0_refresh_done().bit()),
+                &self.reg_l2_mem_unit0_refresh_done(),
             )
             .field(
                 "reg_l2_mem_unit1_refresh_done",
-                &format_args!("{}", self.reg_l2_mem_unit1_refresh_done().bit()),
+                &self.reg_l2_mem_unit1_refresh_done(),
             )
             .field(
                 "reg_l2_mem_unit2_refresh_done",
-                &format_args!("{}", self.reg_l2_mem_unit2_refresh_done().bit()),
+                &self.reg_l2_mem_unit2_refresh_done(),
             )
             .field(
                 "reg_l2_mem_unit3_refresh_done",
-                &format_args!("{}", self.reg_l2_mem_unit3_refresh_done().bit()),
+                &self.reg_l2_mem_unit3_refresh_done(),
             )
             .field(
                 "reg_l2_mem_unit4_refresh_done",
-                &format_args!("{}", self.reg_l2_mem_unit4_refresh_done().bit()),
+                &self.reg_l2_mem_unit4_refresh_done(),
             )
             .field(
                 "reg_l2_mem_unit5_refresh_done",
-                &format_args!("{}", self.reg_l2_mem_unit5_refresh_done().bit()),
+                &self.reg_l2_mem_unit5_refresh_done(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_REFRESH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l2_mem_subsize.rs b/esp32p4/src/hp_sys/l2_mem_subsize.rs
index ecdfa953dd..37863ccac9 100644
--- a/esp32p4/src/hp_sys/l2_mem_subsize.rs
+++ b/esp32p4/src/hp_sys/l2_mem_subsize.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_MEM_SUBSIZE")
-            .field(
-                "reg_l2_mem_sub_blksize",
-                &format_args!("{}", self.reg_l2_mem_sub_blksize().bits()),
-            )
+            .field("reg_l2_mem_sub_blksize", &self.reg_l2_mem_sub_blksize())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_SUBSIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - l2mem sub block size 00=>32 01=>64 10=>128 11=>256"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l2_mem_sw_ecc_bwe_mask.rs b/esp32p4/src/hp_sys/l2_mem_sw_ecc_bwe_mask.rs
index 09bd9a811d..31f4f6bb8a 100644
--- a/esp32p4/src/hp_sys/l2_mem_sw_ecc_bwe_mask.rs
+++ b/esp32p4/src/hp_sys/l2_mem_sw_ecc_bwe_mask.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("L2_MEM_SW_ECC_BWE_MASK")
             .field(
                 "reg_l2_mem_sw_ecc_bwe_mask_ctrl",
-                &format_args!("{}", self.reg_l2_mem_sw_ecc_bwe_mask_ctrl().bit()),
+                &self.reg_l2_mem_sw_ecc_bwe_mask_ctrl(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_MEM_SW_ECC_BWE_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to mask bwe hamming code bit"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/l2_rom_pwr_ctrl0.rs b/esp32p4/src/hp_sys/l2_rom_pwr_ctrl0.rs
index c350e96bed..7225df73a6 100644
--- a/esp32p4/src/hp_sys/l2_rom_pwr_ctrl0.rs
+++ b/esp32p4/src/hp_sys/l2_rom_pwr_ctrl0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("L2_ROM_PWR_CTRL0")
-            .field(
-                "reg_l2_rom_clk_force_on",
-                &format_args!("{}", self.reg_l2_rom_clk_force_on().bit()),
-            )
+            .field("reg_l2_rom_clk_force_on", &self.reg_l2_rom_clk_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<L2_ROM_PWR_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - l2_rom clk gating force on"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/peri1_apb_postw_en.rs b/esp32p4/src/hp_sys/peri1_apb_postw_en.rs
index 19f7ceec43..fcd8d8d9f1 100644
--- a/esp32p4/src/hp_sys/peri1_apb_postw_en.rs
+++ b/esp32p4/src/hp_sys/peri1_apb_postw_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI1_APB_POSTW_EN")
-            .field(
-                "peri1_apb_postw_en",
-                &format_args!("{}", self.peri1_apb_postw_en().bit()),
-            )
+            .field("peri1_apb_postw_en", &self.peri1_apb_postw_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI1_APB_POSTW_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - hp_peri1 apb register interface post write enable, 1 will speed up write, but will take some time to update value to register"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/peri_mem_clk_force_on.rs b/esp32p4/src/hp_sys/peri_mem_clk_force_on.rs
index 3b48f6ef95..2090f8af34 100644
--- a/esp32p4/src/hp_sys/peri_mem_clk_force_on.rs
+++ b/esp32p4/src/hp_sys/peri_mem_clk_force_on.rs
@@ -44,31 +44,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_MEM_CLK_FORCE_ON")
-            .field(
-                "rmt_mem_clk_force_on",
-                &format_args!("{}", self.rmt_mem_clk_force_on().bit()),
-            )
+            .field("rmt_mem_clk_force_on", &self.rmt_mem_clk_force_on())
             .field(
                 "bitscrambler_tx_mem_clk_force_on",
-                &format_args!("{}", self.bitscrambler_tx_mem_clk_force_on().bit()),
+                &self.bitscrambler_tx_mem_clk_force_on(),
             )
             .field(
                 "bitscrambler_rx_mem_clk_force_on",
-                &format_args!("{}", self.bitscrambler_rx_mem_clk_force_on().bit()),
-            )
-            .field(
-                "gdma_mem_clk_force_on",
-                &format_args!("{}", self.gdma_mem_clk_force_on().bit()),
+                &self.bitscrambler_rx_mem_clk_force_on(),
             )
+            .field("gdma_mem_clk_force_on", &self.gdma_mem_clk_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_MEM_CLK_FORCE_ON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to force on mem clk in rmt"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/probe_out.rs b/esp32p4/src/hp_sys/probe_out.rs
index 1f5acc8595..fcafa3f454 100644
--- a/esp32p4/src/hp_sys/probe_out.rs
+++ b/esp32p4/src/hp_sys/probe_out.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PROBE_OUT")
-            .field(
-                "reg_probe_top_out",
-                &format_args!("{}", self.reg_probe_top_out().bits()),
-            )
+            .field("reg_probe_top_out", &self.reg_probe_top_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PROBE_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`probe_out::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROBE_OUT_SPEC;
 impl crate::RegisterSpec for PROBE_OUT_SPEC {
diff --git a/esp32p4/src/hp_sys/probea_ctrl.rs b/esp32p4/src/hp_sys/probea_ctrl.rs
index 41f5e1170a..18eb147488 100644
--- a/esp32p4/src/hp_sys/probea_ctrl.rs
+++ b/esp32p4/src/hp_sys/probea_ctrl.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PROBEA_CTRL")
-            .field(
-                "reg_probe_a_mod_sel",
-                &format_args!("{}", self.reg_probe_a_mod_sel().bits()),
-            )
-            .field(
-                "reg_probe_a_top_sel",
-                &format_args!("{}", self.reg_probe_a_top_sel().bits()),
-            )
-            .field(
-                "reg_probe_l_sel",
-                &format_args!("{}", self.reg_probe_l_sel().bits()),
-            )
-            .field(
-                "reg_probe_h_sel",
-                &format_args!("{}", self.reg_probe_h_sel().bits()),
-            )
-            .field(
-                "reg_probe_global_en",
-                &format_args!("{}", self.reg_probe_global_en().bit()),
-            )
+            .field("reg_probe_a_mod_sel", &self.reg_probe_a_mod_sel())
+            .field("reg_probe_a_top_sel", &self.reg_probe_a_top_sel())
+            .field("reg_probe_l_sel", &self.reg_probe_l_sel())
+            .field("reg_probe_h_sel", &self.reg_probe_h_sel())
+            .field("reg_probe_global_en", &self.reg_probe_global_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PROBEA_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out\\[31:0\\] in a mode"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/probeb_ctrl.rs b/esp32p4/src/hp_sys/probeb_ctrl.rs
index 30b9facf57..ec8b3dc674 100644
--- a/esp32p4/src/hp_sys/probeb_ctrl.rs
+++ b/esp32p4/src/hp_sys/probeb_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PROBEB_CTRL")
-            .field(
-                "reg_probe_b_mod_sel",
-                &format_args!("{}", self.reg_probe_b_mod_sel().bits()),
-            )
-            .field(
-                "reg_probe_b_top_sel",
-                &format_args!("{}", self.reg_probe_b_top_sel().bits()),
-            )
-            .field(
-                "reg_probe_b_en",
-                &format_args!("{}", self.reg_probe_b_en().bit()),
-            )
+            .field("reg_probe_b_mod_sel", &self.reg_probe_b_mod_sel())
+            .field("reg_probe_b_top_sel", &self.reg_probe_b_top_sel())
+            .field("reg_probe_b_en", &self.reg_probe_b_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PROBEB_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out\\[31:0\\] in b mode."]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/psram_flash_addr_interchange.rs b/esp32p4/src/hp_sys/psram_flash_addr_interchange.rs
index a0d16bddee..488f47dcc6 100644
--- a/esp32p4/src/hp_sys/psram_flash_addr_interchange.rs
+++ b/esp32p4/src/hp_sys/psram_flash_addr_interchange.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PSRAM_FLASH_ADDR_INTERCHANGE")
-            .field("cpu", &format_args!("{}", self.cpu().bit()))
-            .field("dma", &format_args!("{}", self.dma().bit()))
+            .field("cpu", &self.cpu())
+            .field("dma", &self.dma())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PSRAM_FLASH_ADDR_INTERCHANGE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/rdn_eco_cs.rs b/esp32p4/src/hp_sys/rdn_eco_cs.rs
index b68b5dc852..6bb2292e0c 100644
--- a/esp32p4/src/hp_sys/rdn_eco_cs.rs
+++ b/esp32p4/src/hp_sys/rdn_eco_cs.rs
@@ -24,23 +24,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDN_ECO_CS")
-            .field(
-                "reg_hp_sys_rdn_eco_en",
-                &format_args!("{}", self.reg_hp_sys_rdn_eco_en().bit()),
-            )
+            .field("reg_hp_sys_rdn_eco_en", &self.reg_hp_sys_rdn_eco_en())
             .field(
                 "reg_hp_sys_rdn_eco_result",
-                &format_args!("{}", self.reg_hp_sys_rdn_eco_result().bit()),
+                &self.reg_hp_sys_rdn_eco_result(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDN_ECO_CS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/rng_cfg.rs b/esp32p4/src/hp_sys/rng_cfg.rs
index 06523a935d..1c8fba138e 100644
--- a/esp32p4/src/hp_sys/rng_cfg.rs
+++ b/esp32p4/src/hp_sys/rng_cfg.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RNG_CFG")
-            .field(
-                "rng_sample_enable",
-                &format_args!("{}", self.rng_sample_enable().bit()),
-            )
-            .field(
-                "rng_chain_clk_div_num",
-                &format_args!("{}", self.rng_chain_clk_div_num().bits()),
-            )
-            .field(
-                "rng_sample_cnt",
-                &format_args!("{}", self.rng_sample_cnt().bits()),
-            )
+            .field("rng_sample_enable", &self.rng_sample_enable())
+            .field("rng_chain_clk_div_num", &self.rng_chain_clk_div_num())
+            .field("rng_sample_cnt", &self.rng_sample_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RNG_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable rng sample chain"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/rsa_pd_ctrl.rs b/esp32p4/src/hp_sys/rsa_pd_ctrl.rs
index fc64987249..82b255b46e 100644
--- a/esp32p4/src/hp_sys/rsa_pd_ctrl.rs
+++ b/esp32p4/src/hp_sys/rsa_pd_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_PD_CTRL")
-            .field(
-                "rsa_mem_force_pd",
-                &format_args!("{}", self.rsa_mem_force_pd().bit()),
-            )
-            .field(
-                "rsa_mem_force_pu",
-                &format_args!("{}", self.rsa_mem_force_pu().bit()),
-            )
-            .field("rsa_mem_pd", &format_args!("{}", self.rsa_mem_pd().bit()))
+            .field("rsa_mem_force_pd", &self.rsa_mem_force_pd())
+            .field("rsa_mem_force_pu", &self.rsa_mem_force_pu())
+            .field("rsa_mem_pd", &self.rsa_mem_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to power down rsa internal memory."]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/tcm_err_resp_ctrl.rs b/esp32p4/src/hp_sys/tcm_err_resp_ctrl.rs
index 5251085390..1d21838469 100644
--- a/esp32p4/src/hp_sys/tcm_err_resp_ctrl.rs
+++ b/esp32p4/src/hp_sys/tcm_err_resp_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TCM_ERR_RESP_CTRL")
-            .field(
-                "tcm_err_resp_en",
-                &format_args!("{}", self.tcm_err_resp_en().bit()),
-            )
+            .field("tcm_err_resp_en", &self.tcm_err_resp_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCM_ERR_RESP_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to turn on tcm error response"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/tcm_init.rs b/esp32p4/src/hp_sys/tcm_init.rs
index 68fc2eb00f..ceee111dfc 100644
--- a/esp32p4/src/hp_sys/tcm_init.rs
+++ b/esp32p4/src/hp_sys/tcm_init.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TCM_INIT")
-            .field(
-                "reg_tcm_init_en",
-                &format_args!("{}", self.reg_tcm_init_en().bit()),
-            )
-            .field(
-                "reg_tcm_init_cnt_reset",
-                &format_args!("{}", self.reg_tcm_init_cnt_reset().bit()),
-            )
-            .field(
-                "reg_tcm_init_done",
-                &format_args!("{}", self.reg_tcm_init_done().bit()),
-            )
+            .field("reg_tcm_init_en", &self.reg_tcm_init_en())
+            .field("reg_tcm_init_cnt_reset", &self.reg_tcm_init_cnt_reset())
+            .field("reg_tcm_init_done", &self.reg_tcm_init_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCM_INIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/tcm_int_ena.rs b/esp32p4/src/hp_sys/tcm_int_ena.rs
index e3f9862acf..5748d0897f 100644
--- a/esp32p4/src/hp_sys/tcm_int_ena.rs
+++ b/esp32p4/src/hp_sys/tcm_int_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TCM_INT_ENA")
-            .field(
-                "tcm_parity_err_int_ena",
-                &format_args!("{}", self.tcm_parity_err_int_ena().bit()),
-            )
+            .field("tcm_parity_err_int_ena", &self.tcm_parity_err_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCM_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/tcm_int_raw.rs b/esp32p4/src/hp_sys/tcm_int_raw.rs
index 36923f4def..ca993b8cde 100644
--- a/esp32p4/src/hp_sys/tcm_int_raw.rs
+++ b/esp32p4/src/hp_sys/tcm_int_raw.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TCM_INT_RAW")
-            .field(
-                "tcm_parity_err_int_raw",
-                &format_args!("{}", self.tcm_parity_err_int_raw().bit()),
-            )
+            .field("tcm_parity_err_int_raw", &self.tcm_parity_err_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCM_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/tcm_int_st.rs b/esp32p4/src/hp_sys/tcm_int_st.rs
index 1e0c3be247..ceca3426a7 100644
--- a/esp32p4/src/hp_sys/tcm_int_st.rs
+++ b/esp32p4/src/hp_sys/tcm_int_st.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TCM_INT_ST")
-            .field(
-                "tcm_parity_err_int_st",
-                &format_args!("{}", self.tcm_parity_err_int_st().bit()),
-            )
+            .field("tcm_parity_err_int_st", &self.tcm_parity_err_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCM_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcm_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TCM_INT_ST_SPEC;
 impl crate::RegisterSpec for TCM_INT_ST_SPEC {
diff --git a/esp32p4/src/hp_sys/tcm_parity_check_ctrl.rs b/esp32p4/src/hp_sys/tcm_parity_check_ctrl.rs
index 7a58d74e5f..d6e94f8687 100644
--- a/esp32p4/src/hp_sys/tcm_parity_check_ctrl.rs
+++ b/esp32p4/src/hp_sys/tcm_parity_check_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TCM_PARITY_CHECK_CTRL")
-            .field(
-                "tcm_parity_check_en",
-                &format_args!("{}", self.tcm_parity_check_en().bit()),
-            )
+            .field("tcm_parity_check_en", &self.tcm_parity_check_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCM_PARITY_CHECK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to turn on tcm parity check"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/tcm_parity_int_record.rs b/esp32p4/src/hp_sys/tcm_parity_int_record.rs
index cc7ac89113..9da1ab8523 100644
--- a/esp32p4/src/hp_sys/tcm_parity_int_record.rs
+++ b/esp32p4/src/hp_sys/tcm_parity_int_record.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TCM_PARITY_INT_RECORD")
-            .field(
-                "tcm_parity_err_int_addr",
-                &format_args!("{}", self.tcm_parity_err_int_addr().bits()),
-            )
+            .field("tcm_parity_err_int_addr", &self.tcm_parity_err_int_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCM_PARITY_INT_RECORD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcm_parity_int_record::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TCM_PARITY_INT_RECORD_SPEC;
 impl crate::RegisterSpec for TCM_PARITY_INT_RECORD_SPEC {
diff --git a/esp32p4/src/hp_sys/tcm_ram_pwr_ctrl0.rs b/esp32p4/src/hp_sys/tcm_ram_pwr_ctrl0.rs
index 7ffee01c2b..db19cf12a3 100644
--- a/esp32p4/src/hp_sys/tcm_ram_pwr_ctrl0.rs
+++ b/esp32p4/src/hp_sys/tcm_ram_pwr_ctrl0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TCM_RAM_PWR_CTRL0")
-            .field(
-                "reg_hp_tcm_clk_force_on",
-                &format_args!("{}", self.reg_hp_tcm_clk_force_on().bit()),
-            )
+            .field("reg_hp_tcm_clk_force_on", &self.reg_hp_tcm_clk_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCM_RAM_PWR_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - hp_tcm clk gatig force on"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/tcm_ram_wrr_config.rs b/esp32p4/src/hp_sys/tcm_ram_wrr_config.rs
index ee27a437d1..1599c1c8c2 100644
--- a/esp32p4/src/hp_sys/tcm_ram_wrr_config.rs
+++ b/esp32p4/src/hp_sys/tcm_ram_wrr_config.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TCM_RAM_WRR_CONFIG")
-            .field(
-                "reg_tcm_ram_ibus0_wt",
-                &format_args!("{}", self.reg_tcm_ram_ibus0_wt().bits()),
-            )
-            .field(
-                "reg_tcm_ram_ibus1_wt",
-                &format_args!("{}", self.reg_tcm_ram_ibus1_wt().bits()),
-            )
-            .field(
-                "reg_tcm_ram_ibus2_wt",
-                &format_args!("{}", self.reg_tcm_ram_ibus2_wt().bits()),
-            )
-            .field(
-                "reg_tcm_ram_ibus3_wt",
-                &format_args!("{}", self.reg_tcm_ram_ibus3_wt().bits()),
-            )
-            .field(
-                "reg_tcm_ram_dbus0_wt",
-                &format_args!("{}", self.reg_tcm_ram_dbus0_wt().bits()),
-            )
-            .field(
-                "reg_tcm_ram_dbus1_wt",
-                &format_args!("{}", self.reg_tcm_ram_dbus1_wt().bits()),
-            )
-            .field(
-                "reg_tcm_ram_dbus2_wt",
-                &format_args!("{}", self.reg_tcm_ram_dbus2_wt().bits()),
-            )
-            .field(
-                "reg_tcm_ram_dbus3_wt",
-                &format_args!("{}", self.reg_tcm_ram_dbus3_wt().bits()),
-            )
-            .field(
-                "reg_tcm_ram_dma_wt",
-                &format_args!("{}", self.reg_tcm_ram_dma_wt().bits()),
-            )
-            .field(
-                "reg_tcm_ram_wrr_high",
-                &format_args!("{}", self.reg_tcm_ram_wrr_high().bit()),
-            )
+            .field("reg_tcm_ram_ibus0_wt", &self.reg_tcm_ram_ibus0_wt())
+            .field("reg_tcm_ram_ibus1_wt", &self.reg_tcm_ram_ibus1_wt())
+            .field("reg_tcm_ram_ibus2_wt", &self.reg_tcm_ram_ibus2_wt())
+            .field("reg_tcm_ram_ibus3_wt", &self.reg_tcm_ram_ibus3_wt())
+            .field("reg_tcm_ram_dbus0_wt", &self.reg_tcm_ram_dbus0_wt())
+            .field("reg_tcm_ram_dbus1_wt", &self.reg_tcm_ram_dbus1_wt())
+            .field("reg_tcm_ram_dbus2_wt", &self.reg_tcm_ram_dbus2_wt())
+            .field("reg_tcm_ram_dbus3_wt", &self.reg_tcm_ram_dbus3_wt())
+            .field("reg_tcm_ram_dma_wt", &self.reg_tcm_ram_dma_wt())
+            .field("reg_tcm_ram_wrr_high", &self.reg_tcm_ram_wrr_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCM_RAM_WRR_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - weight value of ibus0"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/tcm_rdn_eco_cs.rs b/esp32p4/src/hp_sys/tcm_rdn_eco_cs.rs
index e812959077..6c10a17958 100644
--- a/esp32p4/src/hp_sys/tcm_rdn_eco_cs.rs
+++ b/esp32p4/src/hp_sys/tcm_rdn_eco_cs.rs
@@ -24,23 +24,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TCM_RDN_ECO_CS")
-            .field(
-                "reg_hp_tcm_rdn_eco_en",
-                &format_args!("{}", self.reg_hp_tcm_rdn_eco_en().bit()),
-            )
+            .field("reg_hp_tcm_rdn_eco_en", &self.reg_hp_tcm_rdn_eco_en())
             .field(
                 "reg_hp_tcm_rdn_eco_result",
-                &format_args!("{}", self.reg_hp_tcm_rdn_eco_result().bit()),
+                &self.reg_hp_tcm_rdn_eco_result(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCM_RDN_ECO_CS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/tcm_rdn_eco_high.rs b/esp32p4/src/hp_sys/tcm_rdn_eco_high.rs
index b99b49b6cb..7d13e8631d 100644
--- a/esp32p4/src/hp_sys/tcm_rdn_eco_high.rs
+++ b/esp32p4/src/hp_sys/tcm_rdn_eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TCM_RDN_ECO_HIGH")
-            .field(
-                "reg_hp_tcm_rdn_eco_high",
-                &format_args!("{}", self.reg_hp_tcm_rdn_eco_high().bits()),
-            )
+            .field("reg_hp_tcm_rdn_eco_high", &self.reg_hp_tcm_rdn_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCM_RDN_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/tcm_rdn_eco_low.rs b/esp32p4/src/hp_sys/tcm_rdn_eco_low.rs
index 1e33aa5f07..3b5857355b 100644
--- a/esp32p4/src/hp_sys/tcm_rdn_eco_low.rs
+++ b/esp32p4/src/hp_sys/tcm_rdn_eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TCM_RDN_ECO_LOW")
-            .field(
-                "reg_hp_tcm_rdn_eco_low",
-                &format_args!("{}", self.reg_hp_tcm_rdn_eco_low().bits()),
-            )
+            .field("reg_hp_tcm_rdn_eco_low", &self.reg_hp_tcm_rdn_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCM_RDN_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/tcm_sw_parity_bwe_mask.rs b/esp32p4/src/hp_sys/tcm_sw_parity_bwe_mask.rs
index 74932b4a54..21d01eee95 100644
--- a/esp32p4/src/hp_sys/tcm_sw_parity_bwe_mask.rs
+++ b/esp32p4/src/hp_sys/tcm_sw_parity_bwe_mask.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("TCM_SW_PARITY_BWE_MASK")
             .field(
                 "reg_tcm_sw_parity_bwe_mask_ctrl",
-                &format_args!("{}", self.reg_tcm_sw_parity_bwe_mask_ctrl().bit()),
+                &self.reg_tcm_sw_parity_bwe_mask_ctrl(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCM_SW_PARITY_BWE_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to mask tcm bwe parity code bit"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/uart_pd_ctrl.rs b/esp32p4/src/hp_sys/uart_pd_ctrl.rs
index af647a793e..1070185e92 100644
--- a/esp32p4/src/hp_sys/uart_pd_ctrl.rs
+++ b/esp32p4/src/hp_sys/uart_pd_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART_PD_CTRL")
-            .field(
-                "uart_mem_force_pd",
-                &format_args!("{}", self.uart_mem_force_pd().bit()),
-            )
-            .field(
-                "uart_mem_force_pu",
-                &format_args!("{}", self.uart_mem_force_pu().bit()),
-            )
+            .field("uart_mem_force_pd", &self.uart_mem_force_pd())
+            .field("uart_mem_force_pu", &self.uart_mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to power down hp uart internal memory."]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/usb20otg_mem_ctrl.rs b/esp32p4/src/hp_sys/usb20otg_mem_ctrl.rs
index 8766b3d0ef..cd973c4e48 100644
--- a/esp32p4/src/hp_sys/usb20otg_mem_ctrl.rs
+++ b/esp32p4/src/hp_sys/usb20otg_mem_ctrl.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("USB20OTG_MEM_CTRL")
             .field(
                 "reg_usb20_mem_clk_force_on",
-                &format_args!("{}", self.reg_usb20_mem_clk_force_on().bit()),
+                &self.reg_usb20_mem_clk_force_on(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB20OTG_MEM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/usbotg20_ctrl.rs b/esp32p4/src/hp_sys/usbotg20_ctrl.rs
index 005be86d99..cc42a74673 100644
--- a/esp32p4/src/hp_sys/usbotg20_ctrl.rs
+++ b/esp32p4/src/hp_sys/usbotg20_ctrl.rs
@@ -114,57 +114,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USBOTG20_CTRL")
-            .field(
-                "otg_phy_test_done",
-                &format_args!("{}", self.otg_phy_test_done().bit()),
-            )
-            .field(
-                "usb_mem_aux_ctrl",
-                &format_args!("{}", self.usb_mem_aux_ctrl().bits()),
-            )
-            .field(
-                "phy_suspendm",
-                &format_args!("{}", self.phy_suspendm().bit()),
-            )
-            .field(
-                "phy_suspend_force_en",
-                &format_args!("{}", self.phy_suspend_force_en().bit()),
-            )
-            .field("phy_rstn", &format_args!("{}", self.phy_rstn().bit()))
-            .field(
-                "phy_reset_force_en",
-                &format_args!("{}", self.phy_reset_force_en().bit()),
-            )
-            .field(
-                "phy_pll_force_en",
-                &format_args!("{}", self.phy_pll_force_en().bit()),
-            )
-            .field("phy_pll_en", &format_args!("{}", self.phy_pll_en().bit()))
-            .field(
-                "otg_suspendm",
-                &format_args!("{}", self.otg_suspendm().bit()),
-            )
-            .field(
-                "otg_phy_txbitstuff_en",
-                &format_args!("{}", self.otg_phy_txbitstuff_en().bit()),
-            )
-            .field(
-                "otg_phy_refclk_mode",
-                &format_args!("{}", self.otg_phy_refclk_mode().bit()),
-            )
-            .field(
-                "otg_phy_bisten",
-                &format_args!("{}", self.otg_phy_bisten().bit()),
-            )
+            .field("otg_phy_test_done", &self.otg_phy_test_done())
+            .field("usb_mem_aux_ctrl", &self.usb_mem_aux_ctrl())
+            .field("phy_suspendm", &self.phy_suspendm())
+            .field("phy_suspend_force_en", &self.phy_suspend_force_en())
+            .field("phy_rstn", &self.phy_rstn())
+            .field("phy_reset_force_en", &self.phy_reset_force_en())
+            .field("phy_pll_force_en", &self.phy_pll_force_en())
+            .field("phy_pll_en", &self.phy_pll_en())
+            .field("otg_suspendm", &self.otg_suspendm())
+            .field("otg_phy_txbitstuff_en", &self.otg_phy_txbitstuff_en())
+            .field("otg_phy_refclk_mode", &self.otg_phy_refclk_mode())
+            .field("otg_phy_bisten", &self.otg_phy_bisten())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USBOTG20_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 1:14 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/ver_date.rs b/esp32p4/src/hp_sys/ver_date.rs
index 49de418599..722873cb78 100644
--- a/esp32p4/src/hp_sys/ver_date.rs
+++ b/esp32p4/src/hp_sys/ver_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VER_DATE")
-            .field(
-                "reg_ver_date",
-                &format_args!("{}", self.reg_ver_date().bits()),
-            )
+            .field("reg_ver_date", &self.reg_ver_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VER_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys/vpu_ctrl.rs b/esp32p4/src/hp_sys/vpu_ctrl.rs
index fa02c509ed..43143497ed 100644
--- a/esp32p4/src/hp_sys/vpu_ctrl.rs
+++ b/esp32p4/src/hp_sys/vpu_ctrl.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VPU_CTRL")
-            .field(
-                "ppa_lslp_mem_pd",
-                &format_args!("{}", self.ppa_lslp_mem_pd().bit()),
-            )
-            .field(
-                "jpeg_sdslp_mem_pd",
-                &format_args!("{}", self.jpeg_sdslp_mem_pd().bit()),
-            )
-            .field(
-                "jpeg_lslp_mem_pd",
-                &format_args!("{}", self.jpeg_lslp_mem_pd().bit()),
-            )
-            .field(
-                "jpeg_dslp_mem_pd",
-                &format_args!("{}", self.jpeg_dslp_mem_pd().bit()),
-            )
-            .field(
-                "dma2d_lslp_mem_pd",
-                &format_args!("{}", self.dma2d_lslp_mem_pd().bit()),
-            )
+            .field("ppa_lslp_mem_pd", &self.ppa_lslp_mem_pd())
+            .field("jpeg_sdslp_mem_pd", &self.jpeg_sdslp_mem_pd())
+            .field("jpeg_lslp_mem_pd", &self.jpeg_lslp_mem_pd())
+            .field("jpeg_dslp_mem_pd", &self.jpeg_dslp_mem_pd())
+            .field("dma2d_lslp_mem_pd", &self.dma2d_lslp_mem_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VPU_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/ana_pll_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/ana_pll_ctrl0.rs
index 10f482dfca..a1c580ad8c 100644
--- a/esp32p4/src/hp_sys_clkrst/ana_pll_ctrl0.rs
+++ b/esp32p4/src/hp_sys_clkrst/ana_pll_ctrl0.rs
@@ -88,55 +88,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ANA_PLL_CTRL0")
-            .field(
-                "plla_cal_end",
-                &format_args!("{}", self.plla_cal_end().bit()),
-            )
-            .field(
-                "plla_cal_stop",
-                &format_args!("{}", self.plla_cal_stop().bit()),
-            )
-            .field(
-                "cpu_pll_cal_end",
-                &format_args!("{}", self.cpu_pll_cal_end().bit()),
-            )
-            .field(
-                "cpu_pll_cal_stop",
-                &format_args!("{}", self.cpu_pll_cal_stop().bit()),
-            )
-            .field(
-                "sdio_pll_cal_end",
-                &format_args!("{}", self.sdio_pll_cal_end().bit()),
-            )
-            .field(
-                "sdio_pll_cal_stop",
-                &format_args!("{}", self.sdio_pll_cal_stop().bit()),
-            )
-            .field(
-                "sys_pll_cal_end",
-                &format_args!("{}", self.sys_pll_cal_end().bit()),
-            )
-            .field(
-                "sys_pll_cal_stop",
-                &format_args!("{}", self.sys_pll_cal_stop().bit()),
-            )
-            .field(
-                "mspi_cal_end",
-                &format_args!("{}", self.mspi_cal_end().bit()),
-            )
-            .field(
-                "mspi_cal_stop",
-                &format_args!("{}", self.mspi_cal_stop().bit()),
-            )
+            .field("plla_cal_end", &self.plla_cal_end())
+            .field("plla_cal_stop", &self.plla_cal_stop())
+            .field("cpu_pll_cal_end", &self.cpu_pll_cal_end())
+            .field("cpu_pll_cal_stop", &self.cpu_pll_cal_stop())
+            .field("sdio_pll_cal_end", &self.sdio_pll_cal_end())
+            .field("sdio_pll_cal_stop", &self.sdio_pll_cal_stop())
+            .field("sys_pll_cal_end", &self.sys_pll_cal_end())
+            .field("sys_pll_cal_stop", &self.sys_pll_cal_stop())
+            .field("mspi_cal_end", &self.mspi_cal_end())
+            .field("mspi_cal_stop", &self.mspi_cal_stop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ANA_PLL_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/clk_en0.rs b/esp32p4/src/hp_sys_clkrst/clk_en0.rs
index 5f56b8cba1..414bb8a72c 100644
--- a/esp32p4/src/hp_sys_clkrst/clk_en0.rs
+++ b/esp32p4/src/hp_sys_clkrst/clk_en0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EN0")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/clk_force_on_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/clk_force_on_ctrl0.rs
index 80bcc7e174..c2eee5d35e 100644
--- a/esp32p4/src/hp_sys_clkrst/clk_force_on_ctrl0.rs
+++ b/esp32p4/src/hp_sys_clkrst/clk_force_on_ctrl0.rs
@@ -172,85 +172,46 @@ impl core::fmt::Debug for R {
         f.debug_struct("CLK_FORCE_ON_CTRL0")
             .field(
                 "cpuicm_gated_clk_force_on",
-                &format_args!("{}", self.cpuicm_gated_clk_force_on().bit()),
-            )
-            .field(
-                "tcm_cpu_clk_force_on",
-                &format_args!("{}", self.tcm_cpu_clk_force_on().bit()),
-            )
-            .field(
-                "busmon_cpu_clk_force_on",
-                &format_args!("{}", self.busmon_cpu_clk_force_on().bit()),
-            )
-            .field(
-                "l1cache_cpu_clk_force_on",
-                &format_args!("{}", self.l1cache_cpu_clk_force_on().bit()),
+                &self.cpuicm_gated_clk_force_on(),
             )
+            .field("tcm_cpu_clk_force_on", &self.tcm_cpu_clk_force_on())
+            .field("busmon_cpu_clk_force_on", &self.busmon_cpu_clk_force_on())
+            .field("l1cache_cpu_clk_force_on", &self.l1cache_cpu_clk_force_on())
             .field(
                 "l1cache_d_cpu_clk_force_on",
-                &format_args!("{}", self.l1cache_d_cpu_clk_force_on().bit()),
+                &self.l1cache_d_cpu_clk_force_on(),
             )
             .field(
                 "l1cache_i0_cpu_clk_force_on",
-                &format_args!("{}", self.l1cache_i0_cpu_clk_force_on().bit()),
+                &self.l1cache_i0_cpu_clk_force_on(),
             )
             .field(
                 "l1cache_i1_cpu_clk_force_on",
-                &format_args!("{}", self.l1cache_i1_cpu_clk_force_on().bit()),
-            )
-            .field(
-                "trace_cpu_clk_force_on",
-                &format_args!("{}", self.trace_cpu_clk_force_on().bit()),
-            )
-            .field(
-                "trace_sys_clk_force_on",
-                &format_args!("{}", self.trace_sys_clk_force_on().bit()),
-            )
-            .field(
-                "l1cache_mem_clk_force_on",
-                &format_args!("{}", self.l1cache_mem_clk_force_on().bit()),
+                &self.l1cache_i1_cpu_clk_force_on(),
             )
+            .field("trace_cpu_clk_force_on", &self.trace_cpu_clk_force_on())
+            .field("trace_sys_clk_force_on", &self.trace_sys_clk_force_on())
+            .field("l1cache_mem_clk_force_on", &self.l1cache_mem_clk_force_on())
             .field(
                 "l1cache_d_mem_clk_force_on",
-                &format_args!("{}", self.l1cache_d_mem_clk_force_on().bit()),
+                &self.l1cache_d_mem_clk_force_on(),
             )
             .field(
                 "l1cache_i0_mem_clk_force_on",
-                &format_args!("{}", self.l1cache_i0_mem_clk_force_on().bit()),
+                &self.l1cache_i0_mem_clk_force_on(),
             )
             .field(
                 "l1cache_i1_mem_clk_force_on",
-                &format_args!("{}", self.l1cache_i1_mem_clk_force_on().bit()),
-            )
-            .field(
-                "l2cache_mem_clk_force_on",
-                &format_args!("{}", self.l2cache_mem_clk_force_on().bit()),
-            )
-            .field(
-                "l2mem_mem_clk_force_on",
-                &format_args!("{}", self.l2mem_mem_clk_force_on().bit()),
-            )
-            .field(
-                "sar1_clk_force_on",
-                &format_args!("{}", self.sar1_clk_force_on().bit()),
-            )
-            .field(
-                "sar2_clk_force_on",
-                &format_args!("{}", self.sar2_clk_force_on().bit()),
-            )
-            .field(
-                "gmac_tx_clk_force_on",
-                &format_args!("{}", self.gmac_tx_clk_force_on().bit()),
+                &self.l1cache_i1_mem_clk_force_on(),
             )
+            .field("l2cache_mem_clk_force_on", &self.l2cache_mem_clk_force_on())
+            .field("l2mem_mem_clk_force_on", &self.l2mem_mem_clk_force_on())
+            .field("sar1_clk_force_on", &self.sar1_clk_force_on())
+            .field("sar2_clk_force_on", &self.sar2_clk_force_on())
+            .field("gmac_tx_clk_force_on", &self.gmac_tx_clk_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_FORCE_ON_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/cpu_clk_status0.rs b/esp32p4/src/hp_sys_clkrst/cpu_clk_status0.rs
index 2fd5475657..95bf15d9b1 100644
--- a/esp32p4/src/hp_sys_clkrst/cpu_clk_status0.rs
+++ b/esp32p4/src/hp_sys_clkrst/cpu_clk_status0.rs
@@ -48,39 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_CLK_STATUS0")
-            .field(
-                "asic_or_fpga",
-                &format_args!("{}", self.asic_or_fpga().bit()),
-            )
-            .field(
-                "cpu_div_effect",
-                &format_args!("{}", self.cpu_div_effect().bit()),
-            )
-            .field(
-                "cpu_src_is_cpll",
-                &format_args!("{}", self.cpu_src_is_cpll().bit()),
-            )
-            .field(
-                "cpu_div_num_cur",
-                &format_args!("{}", self.cpu_div_num_cur().bits()),
-            )
-            .field(
-                "cpu_div_numerator_cur",
-                &format_args!("{}", self.cpu_div_numerator_cur().bits()),
-            )
-            .field(
-                "cpu_div_denominator_cur",
-                &format_args!("{}", self.cpu_div_denominator_cur().bits()),
-            )
+            .field("asic_or_fpga", &self.asic_or_fpga())
+            .field("cpu_div_effect", &self.cpu_div_effect())
+            .field("cpu_src_is_cpll", &self.cpu_src_is_cpll())
+            .field("cpu_div_num_cur", &self.cpu_div_num_cur())
+            .field("cpu_div_numerator_cur", &self.cpu_div_numerator_cur())
+            .field("cpu_div_denominator_cur", &self.cpu_div_denominator_cur())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_CLK_STATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CPU Clock Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_clk_status0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPU_CLK_STATUS0_SPEC;
 impl crate::RegisterSpec for CPU_CLK_STATUS0_SPEC {
diff --git a/esp32p4/src/hp_sys_clkrst/cpu_src_freq0.rs b/esp32p4/src/hp_sys_clkrst/cpu_src_freq0.rs
index e5524b8500..2a7f670520 100644
--- a/esp32p4/src/hp_sys_clkrst/cpu_src_freq0.rs
+++ b/esp32p4/src/hp_sys_clkrst/cpu_src_freq0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_SRC_FREQ0")
-            .field(
-                "cpu_src_freq",
-                &format_args!("{}", self.cpu_src_freq().bits()),
-            )
+            .field("cpu_src_freq", &self.cpu_src_freq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_SRC_FREQ0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CPU Source Frequency\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_src_freq0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPU_SRC_FREQ0_SPEC;
 impl crate::RegisterSpec for CPU_SRC_FREQ0_SPEC {
diff --git a/esp32p4/src/hp_sys_clkrst/dbg_clk_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/dbg_clk_ctrl0.rs
index 50f3975b8c..8f26b22cdb 100644
--- a/esp32p4/src/hp_sys_clkrst/dbg_clk_ctrl0.rs
+++ b/esp32p4/src/hp_sys_clkrst/dbg_clk_ctrl0.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBG_CLK_CTRL0")
-            .field(
-                "dbg_ch0_sel",
-                &format_args!("{}", self.dbg_ch0_sel().bits()),
-            )
-            .field(
-                "dbg_ch1_sel",
-                &format_args!("{}", self.dbg_ch1_sel().bits()),
-            )
-            .field(
-                "dbg_ch2_sel",
-                &format_args!("{}", self.dbg_ch2_sel().bits()),
-            )
-            .field(
-                "dbg_ch0_div_num",
-                &format_args!("{}", self.dbg_ch0_div_num().bits()),
-            )
+            .field("dbg_ch0_sel", &self.dbg_ch0_sel())
+            .field("dbg_ch1_sel", &self.dbg_ch1_sel())
+            .field("dbg_ch2_sel", &self.dbg_ch2_sel())
+            .field("dbg_ch0_div_num", &self.dbg_ch0_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBG_CLK_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/dbg_clk_ctrl1.rs b/esp32p4/src/hp_sys_clkrst/dbg_clk_ctrl1.rs
index 1b5c374ed7..01885b9bef 100644
--- a/esp32p4/src/hp_sys_clkrst/dbg_clk_ctrl1.rs
+++ b/esp32p4/src/hp_sys_clkrst/dbg_clk_ctrl1.rs
@@ -53,26 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBG_CLK_CTRL1")
-            .field(
-                "dbg_ch1_div_num",
-                &format_args!("{}", self.dbg_ch1_div_num().bits()),
-            )
-            .field(
-                "dbg_ch2_div_num",
-                &format_args!("{}", self.dbg_ch2_div_num().bits()),
-            )
-            .field("dbg_ch0_en", &format_args!("{}", self.dbg_ch0_en().bit()))
-            .field("dbg_ch1_en", &format_args!("{}", self.dbg_ch1_en().bit()))
-            .field("dbg_ch2_en", &format_args!("{}", self.dbg_ch2_en().bit()))
+            .field("dbg_ch1_div_num", &self.dbg_ch1_div_num())
+            .field("dbg_ch2_div_num", &self.dbg_ch2_div_num())
+            .field("dbg_ch0_en", &self.dbg_ch0_en())
+            .field("dbg_ch1_en", &self.dbg_ch1_en())
+            .field("dbg_ch2_en", &self.dbg_ch2_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBG_CLK_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/dpa_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/dpa_ctrl0.rs
index b19982cdf8..c0f3da0a23 100644
--- a/esp32p4/src/hp_sys_clkrst/dpa_ctrl0.rs
+++ b/esp32p4/src/hp_sys_clkrst/dpa_ctrl0.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPA_CTRL0")
-            .field(
-                "sec_dpa_level",
-                &format_args!("{}", self.sec_dpa_level().bits()),
-            )
-            .field(
-                "sec_dpa_cfg_sel",
-                &format_args!("{}", self.sec_dpa_cfg_sel().bit()),
-            )
+            .field("sec_dpa_level", &self.sec_dpa_level())
+            .field("sec_dpa_cfg_sel", &self.sec_dpa_cfg_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPA_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/hp_force_norst0.rs b/esp32p4/src/hp_sys_clkrst/hp_force_norst0.rs
index 5ac2181639..a16afa2ce5 100644
--- a/esp32p4/src/hp_sys_clkrst/hp_force_norst0.rs
+++ b/esp32p4/src/hp_sys_clkrst/hp_force_norst0.rs
@@ -296,143 +296,47 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_FORCE_NORST0")
-            .field(
-                "force_norst_core0",
-                &format_args!("{}", self.force_norst_core0().bit()),
-            )
-            .field(
-                "force_norst_core1",
-                &format_args!("{}", self.force_norst_core1().bit()),
-            )
-            .field(
-                "force_norst_coretrace0",
-                &format_args!("{}", self.force_norst_coretrace0().bit()),
-            )
-            .field(
-                "force_norst_coretrace1",
-                &format_args!("{}", self.force_norst_coretrace1().bit()),
-            )
-            .field(
-                "force_norst_l2memmon",
-                &format_args!("{}", self.force_norst_l2memmon().bit()),
-            )
-            .field(
-                "force_norst_tcmmon",
-                &format_args!("{}", self.force_norst_tcmmon().bit()),
-            )
-            .field(
-                "force_norst_gdma",
-                &format_args!("{}", self.force_norst_gdma().bit()),
-            )
-            .field(
-                "force_norst_mspi_axi",
-                &format_args!("{}", self.force_norst_mspi_axi().bit()),
-            )
+            .field("force_norst_core0", &self.force_norst_core0())
+            .field("force_norst_core1", &self.force_norst_core1())
+            .field("force_norst_coretrace0", &self.force_norst_coretrace0())
+            .field("force_norst_coretrace1", &self.force_norst_coretrace1())
+            .field("force_norst_l2memmon", &self.force_norst_l2memmon())
+            .field("force_norst_tcmmon", &self.force_norst_tcmmon())
+            .field("force_norst_gdma", &self.force_norst_gdma())
+            .field("force_norst_mspi_axi", &self.force_norst_mspi_axi())
             .field(
                 "force_norst_dual_mspi_axi",
-                &format_args!("{}", self.force_norst_dual_mspi_axi().bit()),
-            )
-            .field(
-                "force_norst_mspi_apb",
-                &format_args!("{}", self.force_norst_mspi_apb().bit()),
+                &self.force_norst_dual_mspi_axi(),
             )
+            .field("force_norst_mspi_apb", &self.force_norst_mspi_apb())
             .field(
                 "force_norst_dual_mspi_apb",
-                &format_args!("{}", self.force_norst_dual_mspi_apb().bit()),
-            )
-            .field(
-                "force_norst_dsi_brg",
-                &format_args!("{}", self.force_norst_dsi_brg().bit()),
-            )
-            .field(
-                "force_norst_csi_host",
-                &format_args!("{}", self.force_norst_csi_host().bit()),
-            )
-            .field(
-                "force_norst_csi_brg",
-                &format_args!("{}", self.force_norst_csi_brg().bit()),
-            )
-            .field(
-                "force_norst_isp",
-                &format_args!("{}", self.force_norst_isp().bit()),
-            )
-            .field(
-                "force_norst_jpeg",
-                &format_args!("{}", self.force_norst_jpeg().bit()),
-            )
-            .field(
-                "force_norst_dma2d",
-                &format_args!("{}", self.force_norst_dma2d().bit()),
-            )
-            .field(
-                "force_norst_ppa",
-                &format_args!("{}", self.force_norst_ppa().bit()),
-            )
-            .field(
-                "force_norst_ahb_pdma",
-                &format_args!("{}", self.force_norst_ahb_pdma().bit()),
-            )
-            .field(
-                "force_norst_axi_pdma",
-                &format_args!("{}", self.force_norst_axi_pdma().bit()),
-            )
-            .field(
-                "force_norst_iomux",
-                &format_args!("{}", self.force_norst_iomux().bit()),
-            )
-            .field(
-                "force_norst_padbist",
-                &format_args!("{}", self.force_norst_padbist().bit()),
-            )
-            .field(
-                "force_norst_stimer",
-                &format_args!("{}", self.force_norst_stimer().bit()),
-            )
-            .field(
-                "force_norst_timergrp0",
-                &format_args!("{}", self.force_norst_timergrp0().bit()),
-            )
-            .field(
-                "force_norst_timergrp1",
-                &format_args!("{}", self.force_norst_timergrp1().bit()),
-            )
-            .field(
-                "force_norst_uart0",
-                &format_args!("{}", self.force_norst_uart0().bit()),
-            )
-            .field(
-                "force_norst_uart1",
-                &format_args!("{}", self.force_norst_uart1().bit()),
-            )
-            .field(
-                "force_norst_uart2",
-                &format_args!("{}", self.force_norst_uart2().bit()),
-            )
-            .field(
-                "force_norst_uart3",
-                &format_args!("{}", self.force_norst_uart3().bit()),
-            )
-            .field(
-                "force_norst_uart4",
-                &format_args!("{}", self.force_norst_uart4().bit()),
-            )
-            .field(
-                "force_norst_uhci",
-                &format_args!("{}", self.force_norst_uhci().bit()),
-            )
-            .field(
-                "force_norst_i3cmst",
-                &format_args!("{}", self.force_norst_i3cmst().bit()),
-            )
+                &self.force_norst_dual_mspi_apb(),
+            )
+            .field("force_norst_dsi_brg", &self.force_norst_dsi_brg())
+            .field("force_norst_csi_host", &self.force_norst_csi_host())
+            .field("force_norst_csi_brg", &self.force_norst_csi_brg())
+            .field("force_norst_isp", &self.force_norst_isp())
+            .field("force_norst_jpeg", &self.force_norst_jpeg())
+            .field("force_norst_dma2d", &self.force_norst_dma2d())
+            .field("force_norst_ppa", &self.force_norst_ppa())
+            .field("force_norst_ahb_pdma", &self.force_norst_ahb_pdma())
+            .field("force_norst_axi_pdma", &self.force_norst_axi_pdma())
+            .field("force_norst_iomux", &self.force_norst_iomux())
+            .field("force_norst_padbist", &self.force_norst_padbist())
+            .field("force_norst_stimer", &self.force_norst_stimer())
+            .field("force_norst_timergrp0", &self.force_norst_timergrp0())
+            .field("force_norst_timergrp1", &self.force_norst_timergrp1())
+            .field("force_norst_uart0", &self.force_norst_uart0())
+            .field("force_norst_uart1", &self.force_norst_uart1())
+            .field("force_norst_uart2", &self.force_norst_uart2())
+            .field("force_norst_uart3", &self.force_norst_uart3())
+            .field("force_norst_uart4", &self.force_norst_uart4())
+            .field("force_norst_uhci", &self.force_norst_uhci())
+            .field("force_norst_i3cmst", &self.force_norst_i3cmst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_FORCE_NORST0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/hp_force_norst1.rs b/esp32p4/src/hp_sys_clkrst/hp_force_norst1.rs
index b1a867fcde..dee165402e 100644
--- a/esp32p4/src/hp_sys_clkrst/hp_force_norst1.rs
+++ b/esp32p4/src/hp_sys_clkrst/hp_force_norst1.rs
@@ -251,123 +251,42 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_FORCE_NORST1")
-            .field(
-                "force_norst_i3cslv",
-                &format_args!("{}", self.force_norst_i3cslv().bit()),
-            )
-            .field(
-                "force_norst_i2c1",
-                &format_args!("{}", self.force_norst_i2c1().bit()),
-            )
-            .field(
-                "force_norst_i2c0",
-                &format_args!("{}", self.force_norst_i2c0().bit()),
-            )
-            .field(
-                "force_norst_rmt",
-                &format_args!("{}", self.force_norst_rmt().bit()),
-            )
-            .field(
-                "force_norst_pwm0",
-                &format_args!("{}", self.force_norst_pwm0().bit()),
-            )
-            .field(
-                "force_norst_pwm1",
-                &format_args!("{}", self.force_norst_pwm1().bit()),
-            )
-            .field(
-                "force_norst_can0",
-                &format_args!("{}", self.force_norst_can0().bit()),
-            )
-            .field(
-                "force_norst_can1",
-                &format_args!("{}", self.force_norst_can1().bit()),
-            )
-            .field(
-                "force_norst_can2",
-                &format_args!("{}", self.force_norst_can2().bit()),
-            )
-            .field(
-                "force_norst_ledc",
-                &format_args!("{}", self.force_norst_ledc().bit()),
-            )
-            .field(
-                "force_norst_pcnt",
-                &format_args!("{}", self.force_norst_pcnt().bit()),
-            )
-            .field(
-                "force_norst_etm",
-                &format_args!("{}", self.force_norst_etm().bit()),
-            )
-            .field(
-                "force_norst_intrmtx",
-                &format_args!("{}", self.force_norst_intrmtx().bit()),
-            )
-            .field(
-                "force_norst_parlio",
-                &format_args!("{}", self.force_norst_parlio().bit()),
-            )
-            .field(
-                "force_norst_parlio_rx",
-                &format_args!("{}", self.force_norst_parlio_rx().bit()),
-            )
-            .field(
-                "force_norst_parlio_tx",
-                &format_args!("{}", self.force_norst_parlio_tx().bit()),
-            )
-            .field(
-                "force_norst_i2s0",
-                &format_args!("{}", self.force_norst_i2s0().bit()),
-            )
-            .field(
-                "force_norst_i2s1",
-                &format_args!("{}", self.force_norst_i2s1().bit()),
-            )
-            .field(
-                "force_norst_i2s2",
-                &format_args!("{}", self.force_norst_i2s2().bit()),
-            )
-            .field(
-                "force_norst_spi2",
-                &format_args!("{}", self.force_norst_spi2().bit()),
-            )
-            .field(
-                "force_norst_spi3",
-                &format_args!("{}", self.force_norst_spi3().bit()),
-            )
-            .field(
-                "force_norst_lcdcam",
-                &format_args!("{}", self.force_norst_lcdcam().bit()),
-            )
-            .field(
-                "force_norst_adc",
-                &format_args!("{}", self.force_norst_adc().bit()),
-            )
-            .field(
-                "force_norst_bitsrambler",
-                &format_args!("{}", self.force_norst_bitsrambler().bit()),
-            )
+            .field("force_norst_i3cslv", &self.force_norst_i3cslv())
+            .field("force_norst_i2c1", &self.force_norst_i2c1())
+            .field("force_norst_i2c0", &self.force_norst_i2c0())
+            .field("force_norst_rmt", &self.force_norst_rmt())
+            .field("force_norst_pwm0", &self.force_norst_pwm0())
+            .field("force_norst_pwm1", &self.force_norst_pwm1())
+            .field("force_norst_can0", &self.force_norst_can0())
+            .field("force_norst_can1", &self.force_norst_can1())
+            .field("force_norst_can2", &self.force_norst_can2())
+            .field("force_norst_ledc", &self.force_norst_ledc())
+            .field("force_norst_pcnt", &self.force_norst_pcnt())
+            .field("force_norst_etm", &self.force_norst_etm())
+            .field("force_norst_intrmtx", &self.force_norst_intrmtx())
+            .field("force_norst_parlio", &self.force_norst_parlio())
+            .field("force_norst_parlio_rx", &self.force_norst_parlio_rx())
+            .field("force_norst_parlio_tx", &self.force_norst_parlio_tx())
+            .field("force_norst_i2s0", &self.force_norst_i2s0())
+            .field("force_norst_i2s1", &self.force_norst_i2s1())
+            .field("force_norst_i2s2", &self.force_norst_i2s2())
+            .field("force_norst_spi2", &self.force_norst_spi2())
+            .field("force_norst_spi3", &self.force_norst_spi3())
+            .field("force_norst_lcdcam", &self.force_norst_lcdcam())
+            .field("force_norst_adc", &self.force_norst_adc())
+            .field("force_norst_bitsrambler", &self.force_norst_bitsrambler())
             .field(
                 "force_norst_bitsrambler_rx",
-                &format_args!("{}", self.force_norst_bitsrambler_rx().bit()),
+                &self.force_norst_bitsrambler_rx(),
             )
             .field(
                 "force_norst_bitsrambler_tx",
-                &format_args!("{}", self.force_norst_bitsrambler_tx().bit()),
-            )
-            .field(
-                "force_norst_h264",
-                &format_args!("{}", self.force_norst_h264().bit()),
+                &self.force_norst_bitsrambler_tx(),
             )
+            .field("force_norst_h264", &self.force_norst_h264())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_FORCE_NORST1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/hp_rst_en0.rs b/esp32p4/src/hp_sys_clkrst/hp_rst_en0.rs
index ddd4b01db0..8600ca558d 100644
--- a/esp32p4/src/hp_sys_clkrst/hp_rst_en0.rs
+++ b/esp32p4/src/hp_sys_clkrst/hp_rst_en0.rs
@@ -296,134 +296,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_RST_EN0")
-            .field(
-                "rst_en_corectrl",
-                &format_args!("{}", self.rst_en_corectrl().bit()),
-            )
-            .field(
-                "rst_en_pvt_top",
-                &format_args!("{}", self.rst_en_pvt_top().bit()),
-            )
-            .field(
-                "rst_en_pvt_peri_group1",
-                &format_args!("{}", self.rst_en_pvt_peri_group1().bit()),
-            )
-            .field(
-                "rst_en_pvt_peri_group2",
-                &format_args!("{}", self.rst_en_pvt_peri_group2().bit()),
-            )
-            .field(
-                "rst_en_pvt_peri_group3",
-                &format_args!("{}", self.rst_en_pvt_peri_group3().bit()),
-            )
-            .field(
-                "rst_en_pvt_peri_group4",
-                &format_args!("{}", self.rst_en_pvt_peri_group4().bit()),
-            )
-            .field(
-                "rst_en_regdma",
-                &format_args!("{}", self.rst_en_regdma().bit()),
-            )
-            .field(
-                "rst_en_core0_global",
-                &format_args!("{}", self.rst_en_core0_global().bit()),
-            )
-            .field(
-                "rst_en_core1_global",
-                &format_args!("{}", self.rst_en_core1_global().bit()),
-            )
-            .field(
-                "rst_en_coretrace0",
-                &format_args!("{}", self.rst_en_coretrace0().bit()),
-            )
-            .field(
-                "rst_en_coretrace1",
-                &format_args!("{}", self.rst_en_coretrace1().bit()),
-            )
-            .field(
-                "rst_en_hp_tcm",
-                &format_args!("{}", self.rst_en_hp_tcm().bit()),
-            )
-            .field(
-                "rst_en_hp_cache",
-                &format_args!("{}", self.rst_en_hp_cache().bit()),
-            )
-            .field(
-                "rst_en_l1_i0_cache",
-                &format_args!("{}", self.rst_en_l1_i0_cache().bit()),
-            )
-            .field(
-                "rst_en_l1_i1_cache",
-                &format_args!("{}", self.rst_en_l1_i1_cache().bit()),
-            )
-            .field(
-                "rst_en_l1_d_cache",
-                &format_args!("{}", self.rst_en_l1_d_cache().bit()),
-            )
-            .field(
-                "rst_en_l2_cache",
-                &format_args!("{}", self.rst_en_l2_cache().bit()),
-            )
-            .field(
-                "rst_en_l2_mem",
-                &format_args!("{}", self.rst_en_l2_mem().bit()),
-            )
-            .field(
-                "rst_en_l2memmon",
-                &format_args!("{}", self.rst_en_l2memmon().bit()),
-            )
-            .field(
-                "rst_en_tcmmon",
-                &format_args!("{}", self.rst_en_tcmmon().bit()),
-            )
-            .field(
-                "rst_en_pvt_apb",
-                &format_args!("{}", self.rst_en_pvt_apb().bit()),
-            )
-            .field("rst_en_gdma", &format_args!("{}", self.rst_en_gdma().bit()))
-            .field(
-                "rst_en_mspi_axi",
-                &format_args!("{}", self.rst_en_mspi_axi().bit()),
-            )
-            .field(
-                "rst_en_dual_mspi_axi",
-                &format_args!("{}", self.rst_en_dual_mspi_axi().bit()),
-            )
-            .field(
-                "rst_en_mspi_apb",
-                &format_args!("{}", self.rst_en_mspi_apb().bit()),
-            )
-            .field(
-                "rst_en_dual_mspi_apb",
-                &format_args!("{}", self.rst_en_dual_mspi_apb().bit()),
-            )
-            .field(
-                "rst_en_dsi_brg",
-                &format_args!("{}", self.rst_en_dsi_brg().bit()),
-            )
-            .field(
-                "rst_en_csi_host",
-                &format_args!("{}", self.rst_en_csi_host().bit()),
-            )
-            .field(
-                "rst_en_csi_brg",
-                &format_args!("{}", self.rst_en_csi_brg().bit()),
-            )
-            .field("rst_en_isp", &format_args!("{}", self.rst_en_isp().bit()))
-            .field("rst_en_jpeg", &format_args!("{}", self.rst_en_jpeg().bit()))
-            .field(
-                "rst_en_dma2d",
-                &format_args!("{}", self.rst_en_dma2d().bit()),
-            )
+            .field("rst_en_corectrl", &self.rst_en_corectrl())
+            .field("rst_en_pvt_top", &self.rst_en_pvt_top())
+            .field("rst_en_pvt_peri_group1", &self.rst_en_pvt_peri_group1())
+            .field("rst_en_pvt_peri_group2", &self.rst_en_pvt_peri_group2())
+            .field("rst_en_pvt_peri_group3", &self.rst_en_pvt_peri_group3())
+            .field("rst_en_pvt_peri_group4", &self.rst_en_pvt_peri_group4())
+            .field("rst_en_regdma", &self.rst_en_regdma())
+            .field("rst_en_core0_global", &self.rst_en_core0_global())
+            .field("rst_en_core1_global", &self.rst_en_core1_global())
+            .field("rst_en_coretrace0", &self.rst_en_coretrace0())
+            .field("rst_en_coretrace1", &self.rst_en_coretrace1())
+            .field("rst_en_hp_tcm", &self.rst_en_hp_tcm())
+            .field("rst_en_hp_cache", &self.rst_en_hp_cache())
+            .field("rst_en_l1_i0_cache", &self.rst_en_l1_i0_cache())
+            .field("rst_en_l1_i1_cache", &self.rst_en_l1_i1_cache())
+            .field("rst_en_l1_d_cache", &self.rst_en_l1_d_cache())
+            .field("rst_en_l2_cache", &self.rst_en_l2_cache())
+            .field("rst_en_l2_mem", &self.rst_en_l2_mem())
+            .field("rst_en_l2memmon", &self.rst_en_l2memmon())
+            .field("rst_en_tcmmon", &self.rst_en_tcmmon())
+            .field("rst_en_pvt_apb", &self.rst_en_pvt_apb())
+            .field("rst_en_gdma", &self.rst_en_gdma())
+            .field("rst_en_mspi_axi", &self.rst_en_mspi_axi())
+            .field("rst_en_dual_mspi_axi", &self.rst_en_dual_mspi_axi())
+            .field("rst_en_mspi_apb", &self.rst_en_mspi_apb())
+            .field("rst_en_dual_mspi_apb", &self.rst_en_dual_mspi_apb())
+            .field("rst_en_dsi_brg", &self.rst_en_dsi_brg())
+            .field("rst_en_csi_host", &self.rst_en_csi_host())
+            .field("rst_en_csi_brg", &self.rst_en_csi_brg())
+            .field("rst_en_isp", &self.rst_en_isp())
+            .field("rst_en_jpeg", &self.rst_en_jpeg())
+            .field("rst_en_dma2d", &self.rst_en_dma2d())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_RST_EN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/hp_rst_en1.rs b/esp32p4/src/hp_sys_clkrst/hp_rst_en1.rs
index b15361fd98..1a2dabfc0f 100644
--- a/esp32p4/src/hp_sys_clkrst/hp_rst_en1.rs
+++ b/esp32p4/src/hp_sys_clkrst/hp_rst_en1.rs
@@ -296,104 +296,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_RST_EN1")
-            .field("rst_en_ppa", &format_args!("{}", self.rst_en_ppa().bit()))
-            .field(
-                "rst_en_ahb_pdma",
-                &format_args!("{}", self.rst_en_ahb_pdma().bit()),
-            )
-            .field(
-                "rst_en_axi_pdma",
-                &format_args!("{}", self.rst_en_axi_pdma().bit()),
-            )
-            .field(
-                "rst_en_iomux",
-                &format_args!("{}", self.rst_en_iomux().bit()),
-            )
-            .field(
-                "rst_en_padbist",
-                &format_args!("{}", self.rst_en_padbist().bit()),
-            )
-            .field(
-                "rst_en_stimer",
-                &format_args!("{}", self.rst_en_stimer().bit()),
-            )
-            .field(
-                "rst_en_timergrp0",
-                &format_args!("{}", self.rst_en_timergrp0().bit()),
-            )
-            .field(
-                "rst_en_timergrp1",
-                &format_args!("{}", self.rst_en_timergrp1().bit()),
-            )
-            .field(
-                "rst_en_uart0_core",
-                &format_args!("{}", self.rst_en_uart0_core().bit()),
-            )
-            .field(
-                "rst_en_uart1_core",
-                &format_args!("{}", self.rst_en_uart1_core().bit()),
-            )
-            .field(
-                "rst_en_uart2_core",
-                &format_args!("{}", self.rst_en_uart2_core().bit()),
-            )
-            .field(
-                "rst_en_uart3_core",
-                &format_args!("{}", self.rst_en_uart3_core().bit()),
-            )
-            .field(
-                "rst_en_uart4_core",
-                &format_args!("{}", self.rst_en_uart4_core().bit()),
-            )
-            .field(
-                "rst_en_uart0_apb",
-                &format_args!("{}", self.rst_en_uart0_apb().bit()),
-            )
-            .field(
-                "rst_en_uart1_apb",
-                &format_args!("{}", self.rst_en_uart1_apb().bit()),
-            )
-            .field(
-                "rst_en_uart2_apb",
-                &format_args!("{}", self.rst_en_uart2_apb().bit()),
-            )
-            .field(
-                "rst_en_uart3_apb",
-                &format_args!("{}", self.rst_en_uart3_apb().bit()),
-            )
-            .field(
-                "rst_en_uart4_apb",
-                &format_args!("{}", self.rst_en_uart4_apb().bit()),
-            )
-            .field("rst_en_uhci", &format_args!("{}", self.rst_en_uhci().bit()))
-            .field(
-                "rst_en_i3cmst",
-                &format_args!("{}", self.rst_en_i3cmst().bit()),
-            )
-            .field(
-                "rst_en_i3cslv",
-                &format_args!("{}", self.rst_en_i3cslv().bit()),
-            )
-            .field("rst_en_i2c1", &format_args!("{}", self.rst_en_i2c1().bit()))
-            .field("rst_en_i2c0", &format_args!("{}", self.rst_en_i2c0().bit()))
-            .field("rst_en_rmt", &format_args!("{}", self.rst_en_rmt().bit()))
-            .field("rst_en_pwm0", &format_args!("{}", self.rst_en_pwm0().bit()))
-            .field("rst_en_pwm1", &format_args!("{}", self.rst_en_pwm1().bit()))
-            .field("rst_en_can0", &format_args!("{}", self.rst_en_can0().bit()))
-            .field("rst_en_can1", &format_args!("{}", self.rst_en_can1().bit()))
-            .field("rst_en_can2", &format_args!("{}", self.rst_en_can2().bit()))
-            .field("rst_en_ledc", &format_args!("{}", self.rst_en_ledc().bit()))
-            .field("rst_en_pcnt", &format_args!("{}", self.rst_en_pcnt().bit()))
-            .field("rst_en_etm", &format_args!("{}", self.rst_en_etm().bit()))
+            .field("rst_en_ppa", &self.rst_en_ppa())
+            .field("rst_en_ahb_pdma", &self.rst_en_ahb_pdma())
+            .field("rst_en_axi_pdma", &self.rst_en_axi_pdma())
+            .field("rst_en_iomux", &self.rst_en_iomux())
+            .field("rst_en_padbist", &self.rst_en_padbist())
+            .field("rst_en_stimer", &self.rst_en_stimer())
+            .field("rst_en_timergrp0", &self.rst_en_timergrp0())
+            .field("rst_en_timergrp1", &self.rst_en_timergrp1())
+            .field("rst_en_uart0_core", &self.rst_en_uart0_core())
+            .field("rst_en_uart1_core", &self.rst_en_uart1_core())
+            .field("rst_en_uart2_core", &self.rst_en_uart2_core())
+            .field("rst_en_uart3_core", &self.rst_en_uart3_core())
+            .field("rst_en_uart4_core", &self.rst_en_uart4_core())
+            .field("rst_en_uart0_apb", &self.rst_en_uart0_apb())
+            .field("rst_en_uart1_apb", &self.rst_en_uart1_apb())
+            .field("rst_en_uart2_apb", &self.rst_en_uart2_apb())
+            .field("rst_en_uart3_apb", &self.rst_en_uart3_apb())
+            .field("rst_en_uart4_apb", &self.rst_en_uart4_apb())
+            .field("rst_en_uhci", &self.rst_en_uhci())
+            .field("rst_en_i3cmst", &self.rst_en_i3cmst())
+            .field("rst_en_i3cslv", &self.rst_en_i3cslv())
+            .field("rst_en_i2c1", &self.rst_en_i2c1())
+            .field("rst_en_i2c0", &self.rst_en_i2c0())
+            .field("rst_en_rmt", &self.rst_en_rmt())
+            .field("rst_en_pwm0", &self.rst_en_pwm0())
+            .field("rst_en_pwm1", &self.rst_en_pwm1())
+            .field("rst_en_can0", &self.rst_en_can0())
+            .field("rst_en_can1", &self.rst_en_can1())
+            .field("rst_en_can2", &self.rst_en_can2())
+            .field("rst_en_ledc", &self.rst_en_ledc())
+            .field("rst_en_pcnt", &self.rst_en_pcnt())
+            .field("rst_en_etm", &self.rst_en_etm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_RST_EN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/hp_rst_en2.rs b/esp32p4/src/hp_sys_clkrst/hp_rst_en2.rs
index 62f388a6ad..a2f73c769d 100644
--- a/esp32p4/src/hp_sys_clkrst/hp_rst_en2.rs
+++ b/esp32p4/src/hp_sys_clkrst/hp_rst_en2.rs
@@ -233,79 +233,34 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_RST_EN2")
-            .field(
-                "rst_en_intrmtx",
-                &format_args!("{}", self.rst_en_intrmtx().bit()),
-            )
-            .field(
-                "rst_en_parlio",
-                &format_args!("{}", self.rst_en_parlio().bit()),
-            )
-            .field(
-                "rst_en_parlio_rx",
-                &format_args!("{}", self.rst_en_parlio_rx().bit()),
-            )
-            .field(
-                "rst_en_parlio_tx",
-                &format_args!("{}", self.rst_en_parlio_tx().bit()),
-            )
-            .field(
-                "rst_en_i2s0_apb",
-                &format_args!("{}", self.rst_en_i2s0_apb().bit()),
-            )
-            .field(
-                "rst_en_i2s1_apb",
-                &format_args!("{}", self.rst_en_i2s1_apb().bit()),
-            )
-            .field(
-                "rst_en_i2s2_apb",
-                &format_args!("{}", self.rst_en_i2s2_apb().bit()),
-            )
-            .field("rst_en_spi2", &format_args!("{}", self.rst_en_spi2().bit()))
-            .field("rst_en_spi3", &format_args!("{}", self.rst_en_spi3().bit()))
-            .field(
-                "rst_en_lcdcam",
-                &format_args!("{}", self.rst_en_lcdcam().bit()),
-            )
-            .field("rst_en_adc", &format_args!("{}", self.rst_en_adc().bit()))
-            .field(
-                "rst_en_bitsrambler",
-                &format_args!("{}", self.rst_en_bitsrambler().bit()),
-            )
-            .field(
-                "rst_en_bitsrambler_rx",
-                &format_args!("{}", self.rst_en_bitsrambler_rx().bit()),
-            )
-            .field(
-                "rst_en_bitsrambler_tx",
-                &format_args!("{}", self.rst_en_bitsrambler_tx().bit()),
-            )
-            .field(
-                "rst_en_crypto",
-                &format_args!("{}", self.rst_en_crypto().bit()),
-            )
-            .field("rst_en_sec", &format_args!("{}", self.rst_en_sec().bit()))
-            .field("rst_en_aes", &format_args!("{}", self.rst_en_aes().bit()))
-            .field("rst_en_ds", &format_args!("{}", self.rst_en_ds().bit()))
-            .field("rst_en_sha", &format_args!("{}", self.rst_en_sha().bit()))
-            .field("rst_en_hmac", &format_args!("{}", self.rst_en_hmac().bit()))
-            .field(
-                "rst_en_ecdsa",
-                &format_args!("{}", self.rst_en_ecdsa().bit()),
-            )
-            .field("rst_en_rsa", &format_args!("{}", self.rst_en_rsa().bit()))
-            .field("rst_en_ecc", &format_args!("{}", self.rst_en_ecc().bit()))
-            .field("rst_en_km", &format_args!("{}", self.rst_en_km().bit()))
-            .field("rst_en_h264", &format_args!("{}", self.rst_en_h264().bit()))
+            .field("rst_en_intrmtx", &self.rst_en_intrmtx())
+            .field("rst_en_parlio", &self.rst_en_parlio())
+            .field("rst_en_parlio_rx", &self.rst_en_parlio_rx())
+            .field("rst_en_parlio_tx", &self.rst_en_parlio_tx())
+            .field("rst_en_i2s0_apb", &self.rst_en_i2s0_apb())
+            .field("rst_en_i2s1_apb", &self.rst_en_i2s1_apb())
+            .field("rst_en_i2s2_apb", &self.rst_en_i2s2_apb())
+            .field("rst_en_spi2", &self.rst_en_spi2())
+            .field("rst_en_spi3", &self.rst_en_spi3())
+            .field("rst_en_lcdcam", &self.rst_en_lcdcam())
+            .field("rst_en_adc", &self.rst_en_adc())
+            .field("rst_en_bitsrambler", &self.rst_en_bitsrambler())
+            .field("rst_en_bitsrambler_rx", &self.rst_en_bitsrambler_rx())
+            .field("rst_en_bitsrambler_tx", &self.rst_en_bitsrambler_tx())
+            .field("rst_en_crypto", &self.rst_en_crypto())
+            .field("rst_en_sec", &self.rst_en_sec())
+            .field("rst_en_aes", &self.rst_en_aes())
+            .field("rst_en_ds", &self.rst_en_ds())
+            .field("rst_en_sha", &self.rst_en_sha())
+            .field("rst_en_hmac", &self.rst_en_hmac())
+            .field("rst_en_ecdsa", &self.rst_en_ecdsa())
+            .field("rst_en_rsa", &self.rst_en_rsa())
+            .field("rst_en_ecc", &self.rst_en_ecc())
+            .field("rst_en_km", &self.rst_en_km())
+            .field("rst_en_h264", &self.rst_en_h264())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_RST_EN2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/hpcore_wdt_reset_source0.rs b/esp32p4/src/hp_sys_clkrst/hpcore_wdt_reset_source0.rs
index 1a985aca0f..cf7794afb3 100644
--- a/esp32p4/src/hp_sys_clkrst/hpcore_wdt_reset_source0.rs
+++ b/esp32p4/src/hp_sys_clkrst/hpcore_wdt_reset_source0.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("HPCORE_WDT_RESET_SOURCE0")
             .field(
                 "hpcore0_wdt_reset_source_sel",
-                &format_args!("{}", self.hpcore0_wdt_reset_source_sel().bit()),
+                &self.hpcore0_wdt_reset_source_sel(),
             )
             .field(
                 "hpcore1_wdt_reset_source_sel",
-                &format_args!("{}", self.hpcore1_wdt_reset_source_sel().bit()),
+                &self.hpcore1_wdt_reset_source_sel(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPCORE_WDT_RESET_SOURCE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/hpwdt_core0_rst_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/hpwdt_core0_rst_ctrl0.rs
index d525f2ac7b..273bcaee34 100644
--- a/esp32p4/src/hp_sys_clkrst/hpwdt_core0_rst_ctrl0.rs
+++ b/esp32p4/src/hp_sys_clkrst/hpwdt_core0_rst_ctrl0.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPWDT_CORE0_RST_CTRL0")
-            .field(
-                "hpcore0_stall_en",
-                &format_args!("{}", self.hpcore0_stall_en().bit()),
-            )
-            .field(
-                "hpcore0_stall_wait_num",
-                &format_args!("{}", self.hpcore0_stall_wait_num().bits()),
-            )
-            .field(
-                "wdt_hpcore0_rst_len",
-                &format_args!("{}", self.wdt_hpcore0_rst_len().bits()),
-            )
+            .field("hpcore0_stall_en", &self.hpcore0_stall_en())
+            .field("hpcore0_stall_wait_num", &self.hpcore0_stall_wait_num())
+            .field("wdt_hpcore0_rst_len", &self.wdt_hpcore0_rst_len())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPWDT_CORE0_RST_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/hpwdt_core1_rst_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/hpwdt_core1_rst_ctrl0.rs
index 0268430d7c..0a56d1d60b 100644
--- a/esp32p4/src/hp_sys_clkrst/hpwdt_core1_rst_ctrl0.rs
+++ b/esp32p4/src/hp_sys_clkrst/hpwdt_core1_rst_ctrl0.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPWDT_CORE1_RST_CTRL0")
-            .field(
-                "hpcore1_stall_en",
-                &format_args!("{}", self.hpcore1_stall_en().bit()),
-            )
-            .field(
-                "hpcore1_stall_wait_num",
-                &format_args!("{}", self.hpcore1_stall_wait_num().bits()),
-            )
-            .field(
-                "wdt_hpcore1_rst_len",
-                &format_args!("{}", self.wdt_hpcore1_rst_len().bits()),
-            )
+            .field("hpcore1_stall_en", &self.hpcore1_stall_en())
+            .field("hpcore1_stall_wait_num", &self.hpcore1_stall_wait_num())
+            .field("wdt_hpcore1_rst_len", &self.wdt_hpcore1_rst_len())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPWDT_CORE1_RST_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl00.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl00.rs
index ea867165ff..b0ae7c765a 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl00.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl00.rs
@@ -125,67 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL00")
-            .field(
-                "flash_clk_src_sel",
-                &format_args!("{}", self.flash_clk_src_sel().bits()),
-            )
-            .field(
-                "flash_pll_clk_en",
-                &format_args!("{}", self.flash_pll_clk_en().bit()),
-            )
-            .field(
-                "flash_core_clk_en",
-                &format_args!("{}", self.flash_core_clk_en().bit()),
-            )
-            .field(
-                "flash_core_clk_div_num",
-                &format_args!("{}", self.flash_core_clk_div_num().bits()),
-            )
-            .field(
-                "psram_clk_src_sel",
-                &format_args!("{}", self.psram_clk_src_sel().bits()),
-            )
-            .field(
-                "psram_pll_clk_en",
-                &format_args!("{}", self.psram_pll_clk_en().bit()),
-            )
-            .field(
-                "psram_core_clk_en",
-                &format_args!("{}", self.psram_core_clk_en().bit()),
-            )
-            .field(
-                "psram_core_clk_div_num",
-                &format_args!("{}", self.psram_core_clk_div_num().bits()),
-            )
-            .field(
-                "pad_emac_ref_clk_en",
-                &format_args!("{}", self.pad_emac_ref_clk_en().bit()),
-            )
-            .field(
-                "emac_rmii_clk_src_sel",
-                &format_args!("{}", self.emac_rmii_clk_src_sel().bits()),
-            )
-            .field(
-                "emac_rmii_clk_en",
-                &format_args!("{}", self.emac_rmii_clk_en().bit()),
-            )
-            .field(
-                "emac_rx_clk_src_sel",
-                &format_args!("{}", self.emac_rx_clk_src_sel().bit()),
-            )
-            .field(
-                "emac_rx_clk_en",
-                &format_args!("{}", self.emac_rx_clk_en().bit()),
-            )
+            .field("flash_clk_src_sel", &self.flash_clk_src_sel())
+            .field("flash_pll_clk_en", &self.flash_pll_clk_en())
+            .field("flash_core_clk_en", &self.flash_core_clk_en())
+            .field("flash_core_clk_div_num", &self.flash_core_clk_div_num())
+            .field("psram_clk_src_sel", &self.psram_clk_src_sel())
+            .field("psram_pll_clk_en", &self.psram_pll_clk_en())
+            .field("psram_core_clk_en", &self.psram_core_clk_en())
+            .field("psram_core_clk_div_num", &self.psram_core_clk_div_num())
+            .field("pad_emac_ref_clk_en", &self.pad_emac_ref_clk_en())
+            .field("emac_rmii_clk_src_sel", &self.emac_rmii_clk_src_sel())
+            .field("emac_rmii_clk_en", &self.emac_rmii_clk_en())
+            .field("emac_rx_clk_src_sel", &self.emac_rx_clk_src_sel())
+            .field("emac_rx_clk_en", &self.emac_rx_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL00_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl01.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl01.rs
index e178a9271d..9a07f76fcc 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl01.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl01.rs
@@ -107,59 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL01")
-            .field(
-                "emac_rx_clk_div_num",
-                &format_args!("{}", self.emac_rx_clk_div_num().bits()),
-            )
-            .field(
-                "emac_tx_clk_src_sel",
-                &format_args!("{}", self.emac_tx_clk_src_sel().bit()),
-            )
-            .field(
-                "emac_tx_clk_en",
-                &format_args!("{}", self.emac_tx_clk_en().bit()),
-            )
-            .field(
-                "emac_tx_clk_div_num",
-                &format_args!("{}", self.emac_tx_clk_div_num().bits()),
-            )
-            .field(
-                "emac_ptp_ref_clk_src_sel",
-                &format_args!("{}", self.emac_ptp_ref_clk_src_sel().bit()),
-            )
-            .field(
-                "emac_ptp_ref_clk_en",
-                &format_args!("{}", self.emac_ptp_ref_clk_en().bit()),
-            )
-            .field(
-                "emac_unused0_clk_en",
-                &format_args!("{}", self.emac_unused0_clk_en().bit()),
-            )
-            .field(
-                "emac_unused1_clk_en",
-                &format_args!("{}", self.emac_unused1_clk_en().bit()),
-            )
-            .field(
-                "sdio_hs_mode",
-                &format_args!("{}", self.sdio_hs_mode().bit()),
-            )
-            .field(
-                "sdio_ls_clk_src_sel",
-                &format_args!("{}", self.sdio_ls_clk_src_sel().bit()),
-            )
-            .field(
-                "sdio_ls_clk_en",
-                &format_args!("{}", self.sdio_ls_clk_en().bit()),
-            )
+            .field("emac_rx_clk_div_num", &self.emac_rx_clk_div_num())
+            .field("emac_tx_clk_src_sel", &self.emac_tx_clk_src_sel())
+            .field("emac_tx_clk_en", &self.emac_tx_clk_en())
+            .field("emac_tx_clk_div_num", &self.emac_tx_clk_div_num())
+            .field("emac_ptp_ref_clk_src_sel", &self.emac_ptp_ref_clk_src_sel())
+            .field("emac_ptp_ref_clk_en", &self.emac_ptp_ref_clk_en())
+            .field("emac_unused0_clk_en", &self.emac_unused0_clk_en())
+            .field("emac_unused1_clk_en", &self.emac_unused1_clk_en())
+            .field("sdio_hs_mode", &self.sdio_hs_mode())
+            .field("sdio_ls_clk_src_sel", &self.sdio_ls_clk_src_sel())
+            .field("sdio_ls_clk_en", &self.sdio_ls_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL01_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl02.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl02.rs
index 18432d2a03..2a0aae62ef 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl02.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl02.rs
@@ -109,59 +109,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL02")
-            .field(
-                "sdio_ls_clk_div_num",
-                &format_args!("{}", self.sdio_ls_clk_div_num().bits()),
-            )
-            .field(
-                "sdio_ls_clk_edge_l",
-                &format_args!("{}", self.sdio_ls_clk_edge_l().bits()),
-            )
-            .field(
-                "sdio_ls_clk_edge_h",
-                &format_args!("{}", self.sdio_ls_clk_edge_h().bits()),
-            )
-            .field(
-                "sdio_ls_clk_edge_n",
-                &format_args!("{}", self.sdio_ls_clk_edge_n().bits()),
-            )
-            .field(
-                "sdio_ls_slf_clk_edge_sel",
-                &format_args!("{}", self.sdio_ls_slf_clk_edge_sel().bits()),
-            )
-            .field(
-                "sdio_ls_drv_clk_edge_sel",
-                &format_args!("{}", self.sdio_ls_drv_clk_edge_sel().bits()),
-            )
-            .field(
-                "sdio_ls_sam_clk_edge_sel",
-                &format_args!("{}", self.sdio_ls_sam_clk_edge_sel().bits()),
-            )
-            .field(
-                "sdio_ls_slf_clk_en",
-                &format_args!("{}", self.sdio_ls_slf_clk_en().bit()),
-            )
-            .field(
-                "sdio_ls_drv_clk_en",
-                &format_args!("{}", self.sdio_ls_drv_clk_en().bit()),
-            )
-            .field(
-                "sdio_ls_sam_clk_en",
-                &format_args!("{}", self.sdio_ls_sam_clk_en().bit()),
-            )
+            .field("sdio_ls_clk_div_num", &self.sdio_ls_clk_div_num())
+            .field("sdio_ls_clk_edge_l", &self.sdio_ls_clk_edge_l())
+            .field("sdio_ls_clk_edge_h", &self.sdio_ls_clk_edge_h())
+            .field("sdio_ls_clk_edge_n", &self.sdio_ls_clk_edge_n())
+            .field("sdio_ls_slf_clk_edge_sel", &self.sdio_ls_slf_clk_edge_sel())
+            .field("sdio_ls_drv_clk_edge_sel", &self.sdio_ls_drv_clk_edge_sel())
+            .field("sdio_ls_sam_clk_edge_sel", &self.sdio_ls_sam_clk_edge_sel())
+            .field("sdio_ls_slf_clk_en", &self.sdio_ls_slf_clk_en())
+            .field("sdio_ls_drv_clk_en", &self.sdio_ls_drv_clk_en())
+            .field("sdio_ls_sam_clk_en", &self.sdio_ls_sam_clk_en())
             .field(
                 "mipi_dsi_dphy_clk_src_sel",
-                &format_args!("{}", self.mipi_dsi_dphy_clk_src_sel().bits()),
+                &self.mipi_dsi_dphy_clk_src_sel(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL02_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl03.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl03.rs
index f4179542d0..3073eea2fd 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl03.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl03.rs
@@ -71,43 +71,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL03")
-            .field(
-                "mipi_dsi_dphy_cfg_clk_en",
-                &format_args!("{}", self.mipi_dsi_dphy_cfg_clk_en().bit()),
-            )
+            .field("mipi_dsi_dphy_cfg_clk_en", &self.mipi_dsi_dphy_cfg_clk_en())
             .field(
                 "mipi_dsi_dphy_pll_refclk_en",
-                &format_args!("{}", self.mipi_dsi_dphy_pll_refclk_en().bit()),
+                &self.mipi_dsi_dphy_pll_refclk_en(),
             )
             .field(
                 "mipi_csi_dphy_clk_src_sel",
-                &format_args!("{}", self.mipi_csi_dphy_clk_src_sel().bits()),
-            )
-            .field(
-                "mipi_csi_dphy_cfg_clk_en",
-                &format_args!("{}", self.mipi_csi_dphy_cfg_clk_en().bit()),
-            )
-            .field(
-                "mipi_dsi_dpiclk_src_sel",
-                &format_args!("{}", self.mipi_dsi_dpiclk_src_sel().bits()),
-            )
-            .field(
-                "mipi_dsi_dpiclk_en",
-                &format_args!("{}", self.mipi_dsi_dpiclk_en().bit()),
-            )
-            .field(
-                "mipi_dsi_dpiclk_div_num",
-                &format_args!("{}", self.mipi_dsi_dpiclk_div_num().bits()),
+                &self.mipi_csi_dphy_clk_src_sel(),
             )
+            .field("mipi_csi_dphy_cfg_clk_en", &self.mipi_csi_dphy_cfg_clk_en())
+            .field("mipi_dsi_dpiclk_src_sel", &self.mipi_dsi_dpiclk_src_sel())
+            .field("mipi_dsi_dpiclk_en", &self.mipi_dsi_dpiclk_en())
+            .field("mipi_dsi_dpiclk_div_num", &self.mipi_dsi_dpiclk_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL03_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl10.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl10.rs
index f486245ce2..113ec67b4c 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl10.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl10.rs
@@ -71,37 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL10")
-            .field(
-                "i2c0_clk_src_sel",
-                &format_args!("{}", self.i2c0_clk_src_sel().bit()),
-            )
-            .field("i2c0_clk_en", &format_args!("{}", self.i2c0_clk_en().bit()))
-            .field(
-                "i2c0_clk_div_num",
-                &format_args!("{}", self.i2c0_clk_div_num().bits()),
-            )
-            .field(
-                "i2c0_clk_div_numerator",
-                &format_args!("{}", self.i2c0_clk_div_numerator().bits()),
-            )
-            .field(
-                "i2c0_clk_div_denominator",
-                &format_args!("{}", self.i2c0_clk_div_denominator().bits()),
-            )
-            .field(
-                "i2c1_clk_src_sel",
-                &format_args!("{}", self.i2c1_clk_src_sel().bit()),
-            )
-            .field("i2c1_clk_en", &format_args!("{}", self.i2c1_clk_en().bit()))
+            .field("i2c0_clk_src_sel", &self.i2c0_clk_src_sel())
+            .field("i2c0_clk_en", &self.i2c0_clk_en())
+            .field("i2c0_clk_div_num", &self.i2c0_clk_div_num())
+            .field("i2c0_clk_div_numerator", &self.i2c0_clk_div_numerator())
+            .field("i2c0_clk_div_denominator", &self.i2c0_clk_div_denominator())
+            .field("i2c1_clk_src_sel", &self.i2c1_clk_src_sel())
+            .field("i2c1_clk_en", &self.i2c1_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl11.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl11.rs
index 8916fb2119..54cbb96083 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl11.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl11.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL11")
-            .field(
-                "i2c1_clk_div_num",
-                &format_args!("{}", self.i2c1_clk_div_num().bits()),
-            )
-            .field(
-                "i2c1_clk_div_numerator",
-                &format_args!("{}", self.i2c1_clk_div_numerator().bits()),
-            )
-            .field(
-                "i2c1_clk_div_denominator",
-                &format_args!("{}", self.i2c1_clk_div_denominator().bits()),
-            )
-            .field(
-                "i2s0_rx_clk_en",
-                &format_args!("{}", self.i2s0_rx_clk_en().bit()),
-            )
-            .field(
-                "i2s0_rx_clk_src_sel",
-                &format_args!("{}", self.i2s0_rx_clk_src_sel().bits()),
-            )
+            .field("i2c1_clk_div_num", &self.i2c1_clk_div_num())
+            .field("i2c1_clk_div_numerator", &self.i2c1_clk_div_numerator())
+            .field("i2c1_clk_div_denominator", &self.i2c1_clk_div_denominator())
+            .field("i2s0_rx_clk_en", &self.i2s0_rx_clk_en())
+            .field("i2s0_rx_clk_src_sel", &self.i2s0_rx_clk_src_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl110.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl110.rs
index 13334c8d98..c984e296f3 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl110.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl110.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL110")
-            .field(
-                "lcd_clk_div_num",
-                &format_args!("{}", self.lcd_clk_div_num().bits()),
-            )
-            .field(
-                "lcd_clk_div_numerator",
-                &format_args!("{}", self.lcd_clk_div_numerator().bits()),
-            )
-            .field(
-                "lcd_clk_div_denominator",
-                &format_args!("{}", self.lcd_clk_div_denominator().bits()),
-            )
-            .field(
-                "uart0_clk_src_sel",
-                &format_args!("{}", self.uart0_clk_src_sel().bits()),
-            )
-            .field(
-                "uart0_clk_en",
-                &format_args!("{}", self.uart0_clk_en().bit()),
-            )
+            .field("lcd_clk_div_num", &self.lcd_clk_div_num())
+            .field("lcd_clk_div_numerator", &self.lcd_clk_div_numerator())
+            .field("lcd_clk_div_denominator", &self.lcd_clk_div_denominator())
+            .field("uart0_clk_src_sel", &self.uart0_clk_src_sel())
+            .field("uart0_clk_en", &self.uart0_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL110_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl111.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl111.rs
index f63f69f3ee..338147f24f 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl111.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl111.rs
@@ -53,35 +53,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL111")
-            .field(
-                "uart0_sclk_div_num",
-                &format_args!("{}", self.uart0_sclk_div_num().bits()),
-            )
-            .field(
-                "uart0_sclk_div_numerator",
-                &format_args!("{}", self.uart0_sclk_div_numerator().bits()),
-            )
+            .field("uart0_sclk_div_num", &self.uart0_sclk_div_num())
+            .field("uart0_sclk_div_numerator", &self.uart0_sclk_div_numerator())
             .field(
                 "uart0_sclk_div_denominator",
-                &format_args!("{}", self.uart0_sclk_div_denominator().bits()),
-            )
-            .field(
-                "uart1_clk_src_sel",
-                &format_args!("{}", self.uart1_clk_src_sel().bits()),
-            )
-            .field(
-                "uart1_clk_en",
-                &format_args!("{}", self.uart1_clk_en().bit()),
+                &self.uart0_sclk_div_denominator(),
             )
+            .field("uart1_clk_src_sel", &self.uart1_clk_src_sel())
+            .field("uart1_clk_en", &self.uart1_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL111_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl112.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl112.rs
index 8db9e7c1ff..41a3566b62 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl112.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl112.rs
@@ -53,35 +53,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL112")
-            .field(
-                "uart1_sclk_div_num",
-                &format_args!("{}", self.uart1_sclk_div_num().bits()),
-            )
-            .field(
-                "uart1_sclk_div_numerator",
-                &format_args!("{}", self.uart1_sclk_div_numerator().bits()),
-            )
+            .field("uart1_sclk_div_num", &self.uart1_sclk_div_num())
+            .field("uart1_sclk_div_numerator", &self.uart1_sclk_div_numerator())
             .field(
                 "uart1_sclk_div_denominator",
-                &format_args!("{}", self.uart1_sclk_div_denominator().bits()),
-            )
-            .field(
-                "uart2_clk_src_sel",
-                &format_args!("{}", self.uart2_clk_src_sel().bits()),
-            )
-            .field(
-                "uart2_clk_en",
-                &format_args!("{}", self.uart2_clk_en().bit()),
+                &self.uart1_sclk_div_denominator(),
             )
+            .field("uart2_clk_src_sel", &self.uart2_clk_src_sel())
+            .field("uart2_clk_en", &self.uart2_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL112_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl113.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl113.rs
index ea9e2bdf11..238cde1093 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl113.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl113.rs
@@ -53,35 +53,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL113")
-            .field(
-                "uart2_sclk_div_num",
-                &format_args!("{}", self.uart2_sclk_div_num().bits()),
-            )
-            .field(
-                "uart2_sclk_div_numerator",
-                &format_args!("{}", self.uart2_sclk_div_numerator().bits()),
-            )
+            .field("uart2_sclk_div_num", &self.uart2_sclk_div_num())
+            .field("uart2_sclk_div_numerator", &self.uart2_sclk_div_numerator())
             .field(
                 "uart2_sclk_div_denominator",
-                &format_args!("{}", self.uart2_sclk_div_denominator().bits()),
-            )
-            .field(
-                "uart3_clk_src_sel",
-                &format_args!("{}", self.uart3_clk_src_sel().bits()),
-            )
-            .field(
-                "uart3_clk_en",
-                &format_args!("{}", self.uart3_clk_en().bit()),
+                &self.uart2_sclk_div_denominator(),
             )
+            .field("uart3_clk_src_sel", &self.uart3_clk_src_sel())
+            .field("uart3_clk_en", &self.uart3_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL113_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl114.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl114.rs
index aebd460037..68fda25c31 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl114.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl114.rs
@@ -53,35 +53,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL114")
-            .field(
-                "uart3_sclk_div_num",
-                &format_args!("{}", self.uart3_sclk_div_num().bits()),
-            )
-            .field(
-                "uart3_sclk_div_numerator",
-                &format_args!("{}", self.uart3_sclk_div_numerator().bits()),
-            )
+            .field("uart3_sclk_div_num", &self.uart3_sclk_div_num())
+            .field("uart3_sclk_div_numerator", &self.uart3_sclk_div_numerator())
             .field(
                 "uart3_sclk_div_denominator",
-                &format_args!("{}", self.uart3_sclk_div_denominator().bits()),
-            )
-            .field(
-                "uart4_clk_src_sel",
-                &format_args!("{}", self.uart4_clk_src_sel().bits()),
-            )
-            .field(
-                "uart4_clk_en",
-                &format_args!("{}", self.uart4_clk_en().bit()),
+                &self.uart3_sclk_div_denominator(),
             )
+            .field("uart4_clk_src_sel", &self.uart4_clk_src_sel())
+            .field("uart4_clk_en", &self.uart4_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL114_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl115.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl115.rs
index 2d7c234807..41d1931c1b 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl115.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl115.rs
@@ -89,51 +89,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL115")
-            .field(
-                "uart4_sclk_div_num",
-                &format_args!("{}", self.uart4_sclk_div_num().bits()),
-            )
-            .field(
-                "uart4_sclk_div_numerator",
-                &format_args!("{}", self.uart4_sclk_div_numerator().bits()),
-            )
+            .field("uart4_sclk_div_num", &self.uart4_sclk_div_num())
+            .field("uart4_sclk_div_numerator", &self.uart4_sclk_div_numerator())
             .field(
                 "uart4_sclk_div_denominator",
-                &format_args!("{}", self.uart4_sclk_div_denominator().bits()),
-            )
-            .field(
-                "twai0_clk_src_sel",
-                &format_args!("{}", self.twai0_clk_src_sel().bit()),
-            )
-            .field(
-                "twai0_clk_en",
-                &format_args!("{}", self.twai0_clk_en().bit()),
-            )
-            .field(
-                "twai1_clk_src_sel",
-                &format_args!("{}", self.twai1_clk_src_sel().bit()),
-            )
-            .field(
-                "twai1_clk_en",
-                &format_args!("{}", self.twai1_clk_en().bit()),
-            )
-            .field(
-                "twai2_clk_src_sel",
-                &format_args!("{}", self.twai2_clk_src_sel().bit()),
-            )
-            .field(
-                "twai2_clk_en",
-                &format_args!("{}", self.twai2_clk_en().bit()),
+                &self.uart4_sclk_div_denominator(),
             )
+            .field("twai0_clk_src_sel", &self.twai0_clk_src_sel())
+            .field("twai0_clk_en", &self.twai0_clk_en())
+            .field("twai1_clk_src_sel", &self.twai1_clk_src_sel())
+            .field("twai1_clk_en", &self.twai1_clk_en())
+            .field("twai2_clk_src_sel", &self.twai2_clk_src_sel())
+            .field("twai2_clk_en", &self.twai2_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL115_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl116.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl116.rs
index 5b2afd70c8..70d14e877e 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl116.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl116.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL116")
-            .field(
-                "gpspi2_clk_src_sel",
-                &format_args!("{}", self.gpspi2_clk_src_sel().bits()),
-            )
-            .field(
-                "gpspi2_hs_clk_en",
-                &format_args!("{}", self.gpspi2_hs_clk_en().bit()),
-            )
-            .field(
-                "gpspi2_hs_clk_div_num",
-                &format_args!("{}", self.gpspi2_hs_clk_div_num().bits()),
-            )
-            .field(
-                "gpspi2_mst_clk_div_num",
-                &format_args!("{}", self.gpspi2_mst_clk_div_num().bits()),
-            )
-            .field(
-                "gpspi2_mst_clk_en",
-                &format_args!("{}", self.gpspi2_mst_clk_en().bit()),
-            )
-            .field(
-                "gpspi3_clk_src_sel",
-                &format_args!("{}", self.gpspi3_clk_src_sel().bits()),
-            )
-            .field(
-                "gpspi3_hs_clk_en",
-                &format_args!("{}", self.gpspi3_hs_clk_en().bit()),
-            )
+            .field("gpspi2_clk_src_sel", &self.gpspi2_clk_src_sel())
+            .field("gpspi2_hs_clk_en", &self.gpspi2_hs_clk_en())
+            .field("gpspi2_hs_clk_div_num", &self.gpspi2_hs_clk_div_num())
+            .field("gpspi2_mst_clk_div_num", &self.gpspi2_mst_clk_div_num())
+            .field("gpspi2_mst_clk_en", &self.gpspi2_mst_clk_en())
+            .field("gpspi3_clk_src_sel", &self.gpspi3_clk_src_sel())
+            .field("gpspi3_hs_clk_en", &self.gpspi3_hs_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL116_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl117.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl117.rs
index 588074c848..bbf7557a84 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl117.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl117.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL117")
-            .field(
-                "gpspi3_hs_clk_div_num",
-                &format_args!("{}", self.gpspi3_hs_clk_div_num().bits()),
-            )
-            .field(
-                "gpspi3_mst_clk_div_num",
-                &format_args!("{}", self.gpspi3_mst_clk_div_num().bits()),
-            )
-            .field(
-                "gpspi3_mst_clk_en",
-                &format_args!("{}", self.gpspi3_mst_clk_en().bit()),
-            )
-            .field(
-                "parlio_rx_clk_src_sel",
-                &format_args!("{}", self.parlio_rx_clk_src_sel().bits()),
-            )
-            .field(
-                "parlio_rx_clk_en",
-                &format_args!("{}", self.parlio_rx_clk_en().bit()),
-            )
-            .field(
-                "parlio_rx_clk_div_num",
-                &format_args!("{}", self.parlio_rx_clk_div_num().bits()),
-            )
+            .field("gpspi3_hs_clk_div_num", &self.gpspi3_hs_clk_div_num())
+            .field("gpspi3_mst_clk_div_num", &self.gpspi3_mst_clk_div_num())
+            .field("gpspi3_mst_clk_en", &self.gpspi3_mst_clk_en())
+            .field("parlio_rx_clk_src_sel", &self.parlio_rx_clk_src_sel())
+            .field("parlio_rx_clk_en", &self.parlio_rx_clk_en())
+            .field("parlio_rx_clk_div_num", &self.parlio_rx_clk_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL117_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl118.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl118.rs
index bde564ea08..be20261249 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl118.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl118.rs
@@ -55,33 +55,18 @@ impl core::fmt::Debug for R {
         f.debug_struct("PERI_CLK_CTRL118")
             .field(
                 "parlio_rx_clk_div_numerator",
-                &format_args!("{}", self.parlio_rx_clk_div_numerator().bits()),
+                &self.parlio_rx_clk_div_numerator(),
             )
             .field(
                 "parlio_rx_clk_div_denominator",
-                &format_args!("{}", self.parlio_rx_clk_div_denominator().bits()),
-            )
-            .field(
-                "parlio_tx_clk_src_sel",
-                &format_args!("{}", self.parlio_tx_clk_src_sel().bits()),
-            )
-            .field(
-                "parlio_tx_clk_en",
-                &format_args!("{}", self.parlio_tx_clk_en().bit()),
-            )
-            .field(
-                "parlio_tx_clk_div_num",
-                &format_args!("{}", self.parlio_tx_clk_div_num().bits()),
+                &self.parlio_rx_clk_div_denominator(),
             )
+            .field("parlio_tx_clk_src_sel", &self.parlio_tx_clk_src_sel())
+            .field("parlio_tx_clk_en", &self.parlio_tx_clk_en())
+            .field("parlio_tx_clk_div_num", &self.parlio_tx_clk_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL118_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl119.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl119.rs
index ac52132352..b2e9474741 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl119.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl119.rs
@@ -73,38 +73,20 @@ impl core::fmt::Debug for R {
         f.debug_struct("PERI_CLK_CTRL119")
             .field(
                 "parlio_tx_clk_div_numerator",
-                &format_args!("{}", self.parlio_tx_clk_div_numerator().bits()),
+                &self.parlio_tx_clk_div_numerator(),
             )
             .field(
                 "parlio_tx_clk_div_denominator",
-                &format_args!("{}", self.parlio_tx_clk_div_denominator().bits()),
+                &self.parlio_tx_clk_div_denominator(),
             )
-            .field(
-                "i3c_mst_clk_src_sel",
-                &format_args!("{}", self.i3c_mst_clk_src_sel().bits()),
-            )
-            .field(
-                "i3c_mst_clk_en",
-                &format_args!("{}", self.i3c_mst_clk_en().bit()),
-            )
-            .field(
-                "i3c_mst_clk_div_num",
-                &format_args!("{}", self.i3c_mst_clk_div_num().bits()),
-            )
-            .field(
-                "cam_clk_src_sel",
-                &format_args!("{}", self.cam_clk_src_sel().bits()),
-            )
-            .field("cam_clk_en", &format_args!("{}", self.cam_clk_en().bit()))
+            .field("i3c_mst_clk_src_sel", &self.i3c_mst_clk_src_sel())
+            .field("i3c_mst_clk_en", &self.i3c_mst_clk_en())
+            .field("i3c_mst_clk_div_num", &self.i3c_mst_clk_div_num())
+            .field("cam_clk_src_sel", &self.cam_clk_src_sel())
+            .field("cam_clk_en", &self.cam_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL119_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl12.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl12.rs
index 6e4cf64295..c27c7afe7c 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl12.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl12.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL12")
-            .field(
-                "i2s0_rx_div_n",
-                &format_args!("{}", self.i2s0_rx_div_n().bits()),
-            )
-            .field(
-                "i2s0_rx_div_x",
-                &format_args!("{}", self.i2s0_rx_div_x().bits()),
-            )
-            .field(
-                "i2s0_rx_div_y",
-                &format_args!("{}", self.i2s0_rx_div_y().bits()),
-            )
+            .field("i2s0_rx_div_n", &self.i2s0_rx_div_n())
+            .field("i2s0_rx_div_x", &self.i2s0_rx_div_x())
+            .field("i2s0_rx_div_y", &self.i2s0_rx_div_y())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl120.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl120.rs
index 1a6b2ea370..a34b14ff30 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl120.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl120.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL120")
-            .field(
-                "cam_clk_div_num",
-                &format_args!("{}", self.cam_clk_div_num().bits()),
-            )
-            .field(
-                "cam_clk_div_numerator",
-                &format_args!("{}", self.cam_clk_div_numerator().bits()),
-            )
-            .field(
-                "cam_clk_div_denominator",
-                &format_args!("{}", self.cam_clk_div_denominator().bits()),
-            )
+            .field("cam_clk_div_num", &self.cam_clk_div_num())
+            .field("cam_clk_div_numerator", &self.cam_clk_div_numerator())
+            .field("cam_clk_div_denominator", &self.cam_clk_div_denominator())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL120_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl13.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl13.rs
index d2d93b3893..90e55cb1bb 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl13.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl13.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL13")
-            .field(
-                "i2s0_rx_div_z",
-                &format_args!("{}", self.i2s0_rx_div_z().bits()),
-            )
-            .field(
-                "i2s0_rx_div_yn1",
-                &format_args!("{}", self.i2s0_rx_div_yn1().bit()),
-            )
-            .field(
-                "i2s0_tx_clk_en",
-                &format_args!("{}", self.i2s0_tx_clk_en().bit()),
-            )
-            .field(
-                "i2s0_tx_clk_src_sel",
-                &format_args!("{}", self.i2s0_tx_clk_src_sel().bits()),
-            )
-            .field(
-                "i2s0_tx_div_n",
-                &format_args!("{}", self.i2s0_tx_div_n().bits()),
-            )
-            .field(
-                "i2s0_tx_div_x",
-                &format_args!("{}", self.i2s0_tx_div_x().bits()),
-            )
+            .field("i2s0_rx_div_z", &self.i2s0_rx_div_z())
+            .field("i2s0_rx_div_yn1", &self.i2s0_rx_div_yn1())
+            .field("i2s0_tx_clk_en", &self.i2s0_tx_clk_en())
+            .field("i2s0_tx_clk_src_sel", &self.i2s0_tx_clk_src_sel())
+            .field("i2s0_tx_div_n", &self.i2s0_tx_div_n())
+            .field("i2s0_tx_div_x", &self.i2s0_tx_div_x())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl14.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl14.rs
index dd45cbf1fb..43861671f2 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl14.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl14.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL14")
-            .field(
-                "i2s0_tx_div_y",
-                &format_args!("{}", self.i2s0_tx_div_y().bits()),
-            )
-            .field(
-                "i2s0_tx_div_z",
-                &format_args!("{}", self.i2s0_tx_div_z().bits()),
-            )
-            .field(
-                "i2s0_tx_div_yn1",
-                &format_args!("{}", self.i2s0_tx_div_yn1().bit()),
-            )
-            .field(
-                "i2s0_mst_clk_sel",
-                &format_args!("{}", self.i2s0_mst_clk_sel().bit()),
-            )
-            .field(
-                "i2s1_rx_clk_en",
-                &format_args!("{}", self.i2s1_rx_clk_en().bit()),
-            )
-            .field(
-                "i2s1_rx_clk_src_sel",
-                &format_args!("{}", self.i2s1_rx_clk_src_sel().bits()),
-            )
-            .field(
-                "i2s1_rx_div_n",
-                &format_args!("{}", self.i2s1_rx_div_n().bits()),
-            )
+            .field("i2s0_tx_div_y", &self.i2s0_tx_div_y())
+            .field("i2s0_tx_div_z", &self.i2s0_tx_div_z())
+            .field("i2s0_tx_div_yn1", &self.i2s0_tx_div_yn1())
+            .field("i2s0_mst_clk_sel", &self.i2s0_mst_clk_sel())
+            .field("i2s1_rx_clk_en", &self.i2s1_rx_clk_en())
+            .field("i2s1_rx_clk_src_sel", &self.i2s1_rx_clk_src_sel())
+            .field("i2s1_rx_div_n", &self.i2s1_rx_div_n())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl15.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl15.rs
index 59859f2f08..2287925de2 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl15.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl15.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL15")
-            .field(
-                "i2s1_rx_div_x",
-                &format_args!("{}", self.i2s1_rx_div_x().bits()),
-            )
-            .field(
-                "i2s1_rx_div_y",
-                &format_args!("{}", self.i2s1_rx_div_y().bits()),
-            )
-            .field(
-                "i2s1_rx_div_z",
-                &format_args!("{}", self.i2s1_rx_div_z().bits()),
-            )
-            .field(
-                "i2s1_rx_div_yn1",
-                &format_args!("{}", self.i2s1_rx_div_yn1().bit()),
-            )
-            .field(
-                "i2s1_tx_clk_en",
-                &format_args!("{}", self.i2s1_tx_clk_en().bit()),
-            )
-            .field(
-                "i2s1_tx_clk_src_sel",
-                &format_args!("{}", self.i2s1_tx_clk_src_sel().bits()),
-            )
+            .field("i2s1_rx_div_x", &self.i2s1_rx_div_x())
+            .field("i2s1_rx_div_y", &self.i2s1_rx_div_y())
+            .field("i2s1_rx_div_z", &self.i2s1_rx_div_z())
+            .field("i2s1_rx_div_yn1", &self.i2s1_rx_div_yn1())
+            .field("i2s1_tx_clk_en", &self.i2s1_tx_clk_en())
+            .field("i2s1_tx_clk_src_sel", &self.i2s1_tx_clk_src_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl16.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl16.rs
index 1930d40c5a..536fd79f4f 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl16.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl16.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL16")
-            .field(
-                "i2s1_tx_div_n",
-                &format_args!("{}", self.i2s1_tx_div_n().bits()),
-            )
-            .field(
-                "i2s1_tx_div_x",
-                &format_args!("{}", self.i2s1_tx_div_x().bits()),
-            )
-            .field(
-                "i2s1_tx_div_y",
-                &format_args!("{}", self.i2s1_tx_div_y().bits()),
-            )
+            .field("i2s1_tx_div_n", &self.i2s1_tx_div_n())
+            .field("i2s1_tx_div_x", &self.i2s1_tx_div_x())
+            .field("i2s1_tx_div_y", &self.i2s1_tx_div_y())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL16_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl17.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl17.rs
index e9b971554b..93391ee188 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl17.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl17.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL17")
-            .field(
-                "i2s1_tx_div_z",
-                &format_args!("{}", self.i2s1_tx_div_z().bits()),
-            )
-            .field(
-                "i2s1_tx_div_yn1",
-                &format_args!("{}", self.i2s1_tx_div_yn1().bit()),
-            )
-            .field(
-                "i2s1_mst_clk_sel",
-                &format_args!("{}", self.i2s1_mst_clk_sel().bit()),
-            )
-            .field(
-                "i2s2_rx_clk_en",
-                &format_args!("{}", self.i2s2_rx_clk_en().bit()),
-            )
-            .field(
-                "i2s2_rx_clk_src_sel",
-                &format_args!("{}", self.i2s2_rx_clk_src_sel().bits()),
-            )
-            .field(
-                "i2s2_rx_div_n",
-                &format_args!("{}", self.i2s2_rx_div_n().bits()),
-            )
-            .field(
-                "i2s2_rx_div_x",
-                &format_args!("{}", self.i2s2_rx_div_x().bits()),
-            )
+            .field("i2s1_tx_div_z", &self.i2s1_tx_div_z())
+            .field("i2s1_tx_div_yn1", &self.i2s1_tx_div_yn1())
+            .field("i2s1_mst_clk_sel", &self.i2s1_mst_clk_sel())
+            .field("i2s2_rx_clk_en", &self.i2s2_rx_clk_en())
+            .field("i2s2_rx_clk_src_sel", &self.i2s2_rx_clk_src_sel())
+            .field("i2s2_rx_div_n", &self.i2s2_rx_div_n())
+            .field("i2s2_rx_div_x", &self.i2s2_rx_div_x())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL17_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl18.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl18.rs
index 3c6226f616..73dc3ada2e 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl18.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl18.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL18")
-            .field(
-                "i2s2_rx_div_y",
-                &format_args!("{}", self.i2s2_rx_div_y().bits()),
-            )
-            .field(
-                "i2s2_rx_div_z",
-                &format_args!("{}", self.i2s2_rx_div_z().bits()),
-            )
-            .field(
-                "i2s2_rx_div_yn1",
-                &format_args!("{}", self.i2s2_rx_div_yn1().bit()),
-            )
-            .field(
-                "i2s2_tx_clk_en",
-                &format_args!("{}", self.i2s2_tx_clk_en().bit()),
-            )
-            .field(
-                "i2s2_tx_clk_src_sel",
-                &format_args!("{}", self.i2s2_tx_clk_src_sel().bits()),
-            )
-            .field(
-                "i2s2_tx_div_n",
-                &format_args!("{}", self.i2s2_tx_div_n().bits()),
-            )
+            .field("i2s2_rx_div_y", &self.i2s2_rx_div_y())
+            .field("i2s2_rx_div_z", &self.i2s2_rx_div_z())
+            .field("i2s2_rx_div_yn1", &self.i2s2_rx_div_yn1())
+            .field("i2s2_tx_clk_en", &self.i2s2_tx_clk_en())
+            .field("i2s2_tx_clk_src_sel", &self.i2s2_tx_clk_src_sel())
+            .field("i2s2_tx_div_n", &self.i2s2_tx_div_n())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL18_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl19.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl19.rs
index c05337badf..413b58f288 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl19.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl19.rs
@@ -71,40 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL19")
-            .field(
-                "i2s2_tx_div_x",
-                &format_args!("{}", self.i2s2_tx_div_x().bits()),
-            )
-            .field(
-                "i2s2_tx_div_y",
-                &format_args!("{}", self.i2s2_tx_div_y().bits()),
-            )
-            .field(
-                "i2s2_tx_div_z",
-                &format_args!("{}", self.i2s2_tx_div_z().bits()),
-            )
-            .field(
-                "i2s2_tx_div_yn1",
-                &format_args!("{}", self.i2s2_tx_div_yn1().bit()),
-            )
-            .field(
-                "i2s2_mst_clk_sel",
-                &format_args!("{}", self.i2s2_mst_clk_sel().bit()),
-            )
-            .field(
-                "lcd_clk_src_sel",
-                &format_args!("{}", self.lcd_clk_src_sel().bits()),
-            )
-            .field("lcd_clk_en", &format_args!("{}", self.lcd_clk_en().bit()))
+            .field("i2s2_tx_div_x", &self.i2s2_tx_div_x())
+            .field("i2s2_tx_div_y", &self.i2s2_tx_div_y())
+            .field("i2s2_tx_div_z", &self.i2s2_tx_div_z())
+            .field("i2s2_tx_div_yn1", &self.i2s2_tx_div_yn1())
+            .field("i2s2_mst_clk_sel", &self.i2s2_mst_clk_sel())
+            .field("lcd_clk_src_sel", &self.lcd_clk_src_sel())
+            .field("lcd_clk_en", &self.lcd_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL19_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl20.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl20.rs
index 8382658a98..fde798a14b 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl20.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl20.rs
@@ -125,67 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL20")
-            .field(
-                "mcpwm0_clk_src_sel",
-                &format_args!("{}", self.mcpwm0_clk_src_sel().bits()),
-            )
-            .field(
-                "mcpwm0_clk_en",
-                &format_args!("{}", self.mcpwm0_clk_en().bit()),
-            )
-            .field(
-                "mcpwm0_clk_div_num",
-                &format_args!("{}", self.mcpwm0_clk_div_num().bits()),
-            )
-            .field(
-                "mcpwm1_clk_src_sel",
-                &format_args!("{}", self.mcpwm1_clk_src_sel().bits()),
-            )
-            .field(
-                "mcpwm1_clk_en",
-                &format_args!("{}", self.mcpwm1_clk_en().bit()),
-            )
-            .field(
-                "mcpwm1_clk_div_num",
-                &format_args!("{}", self.mcpwm1_clk_div_num().bits()),
-            )
-            .field(
-                "timergrp0_t0_src_sel",
-                &format_args!("{}", self.timergrp0_t0_src_sel().bits()),
-            )
-            .field(
-                "timergrp0_t0_clk_en",
-                &format_args!("{}", self.timergrp0_t0_clk_en().bit()),
-            )
-            .field(
-                "timergrp0_t1_src_sel",
-                &format_args!("{}", self.timergrp0_t1_src_sel().bits()),
-            )
-            .field(
-                "timergrp0_t1_clk_en",
-                &format_args!("{}", self.timergrp0_t1_clk_en().bit()),
-            )
-            .field(
-                "timergrp0_wdt_src_sel",
-                &format_args!("{}", self.timergrp0_wdt_src_sel().bits()),
-            )
-            .field(
-                "timergrp0_wdt_clk_en",
-                &format_args!("{}", self.timergrp0_wdt_clk_en().bit()),
-            )
-            .field(
-                "timergrp0_tgrt_clk_en",
-                &format_args!("{}", self.timergrp0_tgrt_clk_en().bit()),
-            )
+            .field("mcpwm0_clk_src_sel", &self.mcpwm0_clk_src_sel())
+            .field("mcpwm0_clk_en", &self.mcpwm0_clk_en())
+            .field("mcpwm0_clk_div_num", &self.mcpwm0_clk_div_num())
+            .field("mcpwm1_clk_src_sel", &self.mcpwm1_clk_src_sel())
+            .field("mcpwm1_clk_en", &self.mcpwm1_clk_en())
+            .field("mcpwm1_clk_div_num", &self.mcpwm1_clk_div_num())
+            .field("timergrp0_t0_src_sel", &self.timergrp0_t0_src_sel())
+            .field("timergrp0_t0_clk_en", &self.timergrp0_t0_clk_en())
+            .field("timergrp0_t1_src_sel", &self.timergrp0_t1_src_sel())
+            .field("timergrp0_t1_clk_en", &self.timergrp0_t1_clk_en())
+            .field("timergrp0_wdt_src_sel", &self.timergrp0_wdt_src_sel())
+            .field("timergrp0_wdt_clk_en", &self.timergrp0_wdt_clk_en())
+            .field("timergrp0_tgrt_clk_en", &self.timergrp0_tgrt_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL20_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl21.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl21.rs
index 72a0759c9c..677477d4fa 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl21.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl21.rs
@@ -100,53 +100,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("PERI_CLK_CTRL21")
             .field(
                 "timergrp0_tgrt_clk_src_sel",
-                &format_args!("{}", self.timergrp0_tgrt_clk_src_sel().bits()),
+                &self.timergrp0_tgrt_clk_src_sel(),
             )
             .field(
                 "timergrp0_tgrt_clk_div_num",
-                &format_args!("{}", self.timergrp0_tgrt_clk_div_num().bits()),
-            )
-            .field(
-                "timergrp1_t0_src_sel",
-                &format_args!("{}", self.timergrp1_t0_src_sel().bits()),
-            )
-            .field(
-                "timergrp1_t0_clk_en",
-                &format_args!("{}", self.timergrp1_t0_clk_en().bit()),
-            )
-            .field(
-                "timergrp1_t1_src_sel",
-                &format_args!("{}", self.timergrp1_t1_src_sel().bits()),
-            )
-            .field(
-                "timergrp1_t1_clk_en",
-                &format_args!("{}", self.timergrp1_t1_clk_en().bit()),
-            )
-            .field(
-                "timergrp1_wdt_src_sel",
-                &format_args!("{}", self.timergrp1_wdt_src_sel().bits()),
-            )
-            .field(
-                "timergrp1_wdt_clk_en",
-                &format_args!("{}", self.timergrp1_wdt_clk_en().bit()),
-            )
-            .field(
-                "systimer_clk_src_sel",
-                &format_args!("{}", self.systimer_clk_src_sel().bit()),
-            )
-            .field(
-                "systimer_clk_en",
-                &format_args!("{}", self.systimer_clk_en().bit()),
+                &self.timergrp0_tgrt_clk_div_num(),
             )
+            .field("timergrp1_t0_src_sel", &self.timergrp1_t0_src_sel())
+            .field("timergrp1_t0_clk_en", &self.timergrp1_t0_clk_en())
+            .field("timergrp1_t1_src_sel", &self.timergrp1_t1_src_sel())
+            .field("timergrp1_t1_clk_en", &self.timergrp1_t1_clk_en())
+            .field("timergrp1_wdt_src_sel", &self.timergrp1_wdt_src_sel())
+            .field("timergrp1_wdt_clk_en", &self.timergrp1_wdt_clk_en())
+            .field("systimer_clk_src_sel", &self.systimer_clk_src_sel())
+            .field("systimer_clk_en", &self.systimer_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL21_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl22.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl22.rs
index 2a81be07e3..9bd0123bce 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl22.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl22.rs
@@ -80,41 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL22")
-            .field(
-                "ledc_clk_src_sel",
-                &format_args!("{}", self.ledc_clk_src_sel().bits()),
-            )
-            .field("ledc_clk_en", &format_args!("{}", self.ledc_clk_en().bit()))
-            .field(
-                "rmt_clk_src_sel",
-                &format_args!("{}", self.rmt_clk_src_sel().bits()),
-            )
-            .field("rmt_clk_en", &format_args!("{}", self.rmt_clk_en().bit()))
-            .field(
-                "rmt_clk_div_num",
-                &format_args!("{}", self.rmt_clk_div_num().bits()),
-            )
-            .field(
-                "rmt_clk_div_numerator",
-                &format_args!("{}", self.rmt_clk_div_numerator().bits()),
-            )
-            .field(
-                "rmt_clk_div_denominator",
-                &format_args!("{}", self.rmt_clk_div_denominator().bits()),
-            )
-            .field(
-                "adc_clk_src_sel",
-                &format_args!("{}", self.adc_clk_src_sel().bits()),
-            )
+            .field("ledc_clk_src_sel", &self.ledc_clk_src_sel())
+            .field("ledc_clk_en", &self.ledc_clk_en())
+            .field("rmt_clk_src_sel", &self.rmt_clk_src_sel())
+            .field("rmt_clk_en", &self.rmt_clk_en())
+            .field("rmt_clk_div_num", &self.rmt_clk_div_num())
+            .field("rmt_clk_div_numerator", &self.rmt_clk_div_numerator())
+            .field("rmt_clk_div_denominator", &self.rmt_clk_div_denominator())
+            .field("adc_clk_src_sel", &self.adc_clk_src_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL22_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl23.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl23.rs
index 16d2f5e9bc..45c3080083 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl23.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl23.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL23")
-            .field("adc_clk_en", &format_args!("{}", self.adc_clk_en().bit()))
-            .field(
-                "adc_clk_div_num",
-                &format_args!("{}", self.adc_clk_div_num().bits()),
-            )
-            .field(
-                "adc_clk_div_numerator",
-                &format_args!("{}", self.adc_clk_div_numerator().bits()),
-            )
-            .field(
-                "adc_clk_div_denominator",
-                &format_args!("{}", self.adc_clk_div_denominator().bits()),
-            )
+            .field("adc_clk_en", &self.adc_clk_en())
+            .field("adc_clk_div_num", &self.adc_clk_div_num())
+            .field("adc_clk_div_numerator", &self.adc_clk_div_numerator())
+            .field("adc_clk_div_denominator", &self.adc_clk_div_denominator())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL23_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl24.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl24.rs
index 4f31b202ea..e0355e5fd0 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl24.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl24.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL24")
-            .field(
-                "adc_sar1_clk_div_num",
-                &format_args!("{}", self.adc_sar1_clk_div_num().bits()),
-            )
-            .field(
-                "adc_sar2_clk_div_num",
-                &format_args!("{}", self.adc_sar2_clk_div_num().bits()),
-            )
-            .field(
-                "pvt_clk_div_num",
-                &format_args!("{}", self.pvt_clk_div_num().bits()),
-            )
-            .field("pvt_clk_en", &format_args!("{}", self.pvt_clk_en().bit()))
+            .field("adc_sar1_clk_div_num", &self.adc_sar1_clk_div_num())
+            .field("adc_sar2_clk_div_num", &self.adc_sar2_clk_div_num())
+            .field("pvt_clk_div_num", &self.pvt_clk_div_num())
+            .field("pvt_clk_en", &self.pvt_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL24_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl25.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl25.rs
index ff4cb43c52..dd3a04ba3a 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl25.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl25.rs
@@ -163,78 +163,27 @@ impl core::fmt::Debug for R {
         f.debug_struct("PERI_CLK_CTRL25")
             .field(
                 "pvt_peri_group_clk_div_num",
-                &format_args!("{}", self.pvt_peri_group_clk_div_num().bits()),
+                &self.pvt_peri_group_clk_div_num(),
             )
-            .field(
-                "pvt_peri_group1_clk_en",
-                &format_args!("{}", self.pvt_peri_group1_clk_en().bit()),
-            )
-            .field(
-                "pvt_peri_group2_clk_en",
-                &format_args!("{}", self.pvt_peri_group2_clk_en().bit()),
-            )
-            .field(
-                "pvt_peri_group3_clk_en",
-                &format_args!("{}", self.pvt_peri_group3_clk_en().bit()),
-            )
-            .field(
-                "pvt_peri_group4_clk_en",
-                &format_args!("{}", self.pvt_peri_group4_clk_en().bit()),
-            )
-            .field(
-                "crypto_clk_src_sel",
-                &format_args!("{}", self.crypto_clk_src_sel().bits()),
-            )
-            .field(
-                "crypto_aes_clk_en",
-                &format_args!("{}", self.crypto_aes_clk_en().bit()),
-            )
-            .field(
-                "crypto_ds_clk_en",
-                &format_args!("{}", self.crypto_ds_clk_en().bit()),
-            )
-            .field(
-                "crypto_ecc_clk_en",
-                &format_args!("{}", self.crypto_ecc_clk_en().bit()),
-            )
-            .field(
-                "crypto_hmac_clk_en",
-                &format_args!("{}", self.crypto_hmac_clk_en().bit()),
-            )
-            .field(
-                "crypto_rsa_clk_en",
-                &format_args!("{}", self.crypto_rsa_clk_en().bit()),
-            )
-            .field(
-                "crypto_sec_clk_en",
-                &format_args!("{}", self.crypto_sec_clk_en().bit()),
-            )
-            .field(
-                "crypto_sha_clk_en",
-                &format_args!("{}", self.crypto_sha_clk_en().bit()),
-            )
-            .field(
-                "crypto_ecdsa_clk_en",
-                &format_args!("{}", self.crypto_ecdsa_clk_en().bit()),
-            )
-            .field(
-                "crypto_km_clk_en",
-                &format_args!("{}", self.crypto_km_clk_en().bit()),
-            )
-            .field(
-                "isp_clk_src_sel",
-                &format_args!("{}", self.isp_clk_src_sel().bits()),
-            )
-            .field("isp_clk_en", &format_args!("{}", self.isp_clk_en().bit()))
+            .field("pvt_peri_group1_clk_en", &self.pvt_peri_group1_clk_en())
+            .field("pvt_peri_group2_clk_en", &self.pvt_peri_group2_clk_en())
+            .field("pvt_peri_group3_clk_en", &self.pvt_peri_group3_clk_en())
+            .field("pvt_peri_group4_clk_en", &self.pvt_peri_group4_clk_en())
+            .field("crypto_clk_src_sel", &self.crypto_clk_src_sel())
+            .field("crypto_aes_clk_en", &self.crypto_aes_clk_en())
+            .field("crypto_ds_clk_en", &self.crypto_ds_clk_en())
+            .field("crypto_ecc_clk_en", &self.crypto_ecc_clk_en())
+            .field("crypto_hmac_clk_en", &self.crypto_hmac_clk_en())
+            .field("crypto_rsa_clk_en", &self.crypto_rsa_clk_en())
+            .field("crypto_sec_clk_en", &self.crypto_sec_clk_en())
+            .field("crypto_sha_clk_en", &self.crypto_sha_clk_en())
+            .field("crypto_ecdsa_clk_en", &self.crypto_ecdsa_clk_en())
+            .field("crypto_km_clk_en", &self.crypto_km_clk_en())
+            .field("isp_clk_src_sel", &self.isp_clk_src_sel())
+            .field("isp_clk_en", &self.isp_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL25_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl26.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl26.rs
index fd6b8e80d7..6194a7e516 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl26.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl26.rs
@@ -89,48 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL26")
-            .field(
-                "isp_clk_div_num",
-                &format_args!("{}", self.isp_clk_div_num().bits()),
-            )
-            .field(
-                "iomux_clk_src_sel",
-                &format_args!("{}", self.iomux_clk_src_sel().bit()),
-            )
-            .field(
-                "iomux_clk_en",
-                &format_args!("{}", self.iomux_clk_en().bit()),
-            )
-            .field(
-                "iomux_clk_div_num",
-                &format_args!("{}", self.iomux_clk_div_num().bits()),
-            )
-            .field(
-                "h264_clk_src_sel",
-                &format_args!("{}", self.h264_clk_src_sel().bit()),
-            )
-            .field("h264_clk_en", &format_args!("{}", self.h264_clk_en().bit()))
-            .field(
-                "h264_clk_div_num",
-                &format_args!("{}", self.h264_clk_div_num().bits()),
-            )
-            .field(
-                "padbist_rx_clk_src_sel",
-                &format_args!("{}", self.padbist_rx_clk_src_sel().bit()),
-            )
-            .field(
-                "padbist_rx_clk_en",
-                &format_args!("{}", self.padbist_rx_clk_en().bit()),
-            )
+            .field("isp_clk_div_num", &self.isp_clk_div_num())
+            .field("iomux_clk_src_sel", &self.iomux_clk_src_sel())
+            .field("iomux_clk_en", &self.iomux_clk_en())
+            .field("iomux_clk_div_num", &self.iomux_clk_div_num())
+            .field("h264_clk_src_sel", &self.h264_clk_src_sel())
+            .field("h264_clk_en", &self.h264_clk_en())
+            .field("h264_clk_div_num", &self.h264_clk_div_num())
+            .field("padbist_rx_clk_src_sel", &self.padbist_rx_clk_src_sel())
+            .field("padbist_rx_clk_en", &self.padbist_rx_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL26_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl27.rs b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl27.rs
index 7450d3c50b..14b1aca6eb 100644
--- a/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl27.rs
+++ b/esp32p4/src/hp_sys_clkrst/peri_clk_ctrl27.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_CLK_CTRL27")
-            .field(
-                "padbist_rx_clk_div_num",
-                &format_args!("{}", self.padbist_rx_clk_div_num().bits()),
-            )
-            .field(
-                "padbist_tx_clk_src_sel",
-                &format_args!("{}", self.padbist_tx_clk_src_sel().bit()),
-            )
-            .field(
-                "padbist_tx_clk_en",
-                &format_args!("{}", self.padbist_tx_clk_en().bit()),
-            )
-            .field(
-                "padbist_tx_clk_div_num",
-                &format_args!("{}", self.padbist_tx_clk_div_num().bits()),
-            )
+            .field("padbist_rx_clk_div_num", &self.padbist_rx_clk_div_num())
+            .field("padbist_tx_clk_src_sel", &self.padbist_tx_clk_src_sel())
+            .field("padbist_tx_clk_en", &self.padbist_tx_clk_en())
+            .field("padbist_tx_clk_div_num", &self.padbist_tx_clk_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL27_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl0.rs
index 73fc82d538..e72cce38d0 100644
--- a/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl0.rs
+++ b/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl0.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REF_CLK_CTRL0")
-            .field(
-                "ref_50m_clk_div_num",
-                &format_args!("{}", self.ref_50m_clk_div_num().bits()),
-            )
-            .field(
-                "ref_25m_clk_div_num",
-                &format_args!("{}", self.ref_25m_clk_div_num().bits()),
-            )
-            .field(
-                "ref_240m_clk_div_num",
-                &format_args!("{}", self.ref_240m_clk_div_num().bits()),
-            )
-            .field(
-                "ref_160m_clk_div_num",
-                &format_args!("{}", self.ref_160m_clk_div_num().bits()),
-            )
+            .field("ref_50m_clk_div_num", &self.ref_50m_clk_div_num())
+            .field("ref_25m_clk_div_num", &self.ref_25m_clk_div_num())
+            .field("ref_240m_clk_div_num", &self.ref_240m_clk_div_num())
+            .field("ref_160m_clk_div_num", &self.ref_160m_clk_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REF_CLK_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl1.rs b/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl1.rs
index 19729138d3..8233c6ca92 100644
--- a/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl1.rs
+++ b/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl1.rs
@@ -107,59 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REF_CLK_CTRL1")
-            .field(
-                "ref_120m_clk_div_num",
-                &format_args!("{}", self.ref_120m_clk_div_num().bits()),
-            )
-            .field(
-                "ref_80m_clk_div_num",
-                &format_args!("{}", self.ref_80m_clk_div_num().bits()),
-            )
-            .field(
-                "ref_20m_clk_div_num",
-                &format_args!("{}", self.ref_20m_clk_div_num().bits()),
-            )
-            .field(
-                "tm_400m_clk_en",
-                &format_args!("{}", self.tm_400m_clk_en().bit()),
-            )
-            .field(
-                "tm_200m_clk_en",
-                &format_args!("{}", self.tm_200m_clk_en().bit()),
-            )
-            .field(
-                "tm_100m_clk_en",
-                &format_args!("{}", self.tm_100m_clk_en().bit()),
-            )
-            .field(
-                "ref_50m_clk_en",
-                &format_args!("{}", self.ref_50m_clk_en().bit()),
-            )
-            .field(
-                "ref_25m_clk_en",
-                &format_args!("{}", self.ref_25m_clk_en().bit()),
-            )
-            .field(
-                "tm_480m_clk_en",
-                &format_args!("{}", self.tm_480m_clk_en().bit()),
-            )
-            .field(
-                "ref_240m_clk_en",
-                &format_args!("{}", self.ref_240m_clk_en().bit()),
-            )
-            .field(
-                "tm_240m_clk_en",
-                &format_args!("{}", self.tm_240m_clk_en().bit()),
-            )
+            .field("ref_120m_clk_div_num", &self.ref_120m_clk_div_num())
+            .field("ref_80m_clk_div_num", &self.ref_80m_clk_div_num())
+            .field("ref_20m_clk_div_num", &self.ref_20m_clk_div_num())
+            .field("tm_400m_clk_en", &self.tm_400m_clk_en())
+            .field("tm_200m_clk_en", &self.tm_200m_clk_en())
+            .field("tm_100m_clk_en", &self.tm_100m_clk_en())
+            .field("ref_50m_clk_en", &self.ref_50m_clk_en())
+            .field("ref_25m_clk_en", &self.ref_25m_clk_en())
+            .field("tm_480m_clk_en", &self.tm_480m_clk_en())
+            .field("ref_240m_clk_en", &self.ref_240m_clk_en())
+            .field("tm_240m_clk_en", &self.tm_240m_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REF_CLK_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl2.rs b/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl2.rs
index 841e74b7ba..9e70676e67 100644
--- a/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl2.rs
+++ b/esp32p4/src/hp_sys_clkrst/ref_clk_ctrl2.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REF_CLK_CTRL2")
-            .field(
-                "ref_160m_clk_en",
-                &format_args!("{}", self.ref_160m_clk_en().bit()),
-            )
-            .field(
-                "tm_160m_clk_en",
-                &format_args!("{}", self.tm_160m_clk_en().bit()),
-            )
-            .field(
-                "ref_120m_clk_en",
-                &format_args!("{}", self.ref_120m_clk_en().bit()),
-            )
-            .field(
-                "tm_120m_clk_en",
-                &format_args!("{}", self.tm_120m_clk_en().bit()),
-            )
-            .field(
-                "ref_80m_clk_en",
-                &format_args!("{}", self.ref_80m_clk_en().bit()),
-            )
-            .field(
-                "tm_80m_clk_en",
-                &format_args!("{}", self.tm_80m_clk_en().bit()),
-            )
-            .field(
-                "tm_60m_clk_en",
-                &format_args!("{}", self.tm_60m_clk_en().bit()),
-            )
-            .field(
-                "tm_48m_clk_en",
-                &format_args!("{}", self.tm_48m_clk_en().bit()),
-            )
-            .field(
-                "ref_20m_clk_en",
-                &format_args!("{}", self.ref_20m_clk_en().bit()),
-            )
-            .field(
-                "tm_20m_clk_en",
-                &format_args!("{}", self.tm_20m_clk_en().bit()),
-            )
+            .field("ref_160m_clk_en", &self.ref_160m_clk_en())
+            .field("tm_160m_clk_en", &self.tm_160m_clk_en())
+            .field("ref_120m_clk_en", &self.ref_120m_clk_en())
+            .field("tm_120m_clk_en", &self.tm_120m_clk_en())
+            .field("ref_80m_clk_en", &self.ref_80m_clk_en())
+            .field("tm_80m_clk_en", &self.tm_80m_clk_en())
+            .field("tm_60m_clk_en", &self.tm_60m_clk_en())
+            .field("tm_48m_clk_en", &self.tm_48m_clk_en())
+            .field("ref_20m_clk_en", &self.ref_20m_clk_en())
+            .field("tm_20m_clk_en", &self.tm_20m_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REF_CLK_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/root_clk_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl0.rs
index b564e50eeb..728ee1c4fc 100644
--- a/esp32p4/src/hp_sys_clkrst/root_clk_ctrl0.rs
+++ b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl0.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROOT_CLK_CTRL0")
-            .field(
-                "cpuicm_delay_num",
-                &format_args!("{}", self.cpuicm_delay_num().bits()),
-            )
-            .field(
-                "soc_clk_div_update",
-                &format_args!("{}", self.soc_clk_div_update().bit()),
-            )
-            .field(
-                "cpu_clk_div_num",
-                &format_args!("{}", self.cpu_clk_div_num().bits()),
-            )
-            .field(
-                "cpu_clk_div_numerator",
-                &format_args!("{}", self.cpu_clk_div_numerator().bits()),
-            )
-            .field(
-                "cpu_clk_div_denominator",
-                &format_args!("{}", self.cpu_clk_div_denominator().bits()),
-            )
+            .field("cpuicm_delay_num", &self.cpuicm_delay_num())
+            .field("soc_clk_div_update", &self.soc_clk_div_update())
+            .field("cpu_clk_div_num", &self.cpu_clk_div_num())
+            .field("cpu_clk_div_numerator", &self.cpu_clk_div_numerator())
+            .field("cpu_clk_div_denominator", &self.cpu_clk_div_denominator())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROOT_CLK_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/root_clk_ctrl1.rs b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl1.rs
index 935ea67404..dd8589e7ea 100644
--- a/esp32p4/src/hp_sys_clkrst/root_clk_ctrl1.rs
+++ b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROOT_CLK_CTRL1")
-            .field(
-                "mem_clk_div_num",
-                &format_args!("{}", self.mem_clk_div_num().bits()),
-            )
-            .field(
-                "mem_clk_div_numerator",
-                &format_args!("{}", self.mem_clk_div_numerator().bits()),
-            )
-            .field(
-                "mem_clk_div_denominator",
-                &format_args!("{}", self.mem_clk_div_denominator().bits()),
-            )
-            .field(
-                "sys_clk_div_num",
-                &format_args!("{}", self.sys_clk_div_num().bits()),
-            )
+            .field("mem_clk_div_num", &self.mem_clk_div_num())
+            .field("mem_clk_div_numerator", &self.mem_clk_div_numerator())
+            .field("mem_clk_div_denominator", &self.mem_clk_div_denominator())
+            .field("sys_clk_div_num", &self.sys_clk_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROOT_CLK_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/root_clk_ctrl2.rs b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl2.rs
index e83a64ab1e..7f89c5f9d2 100644
--- a/esp32p4/src/hp_sys_clkrst/root_clk_ctrl2.rs
+++ b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl2.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROOT_CLK_CTRL2")
-            .field(
-                "sys_clk_div_numerator",
-                &format_args!("{}", self.sys_clk_div_numerator().bits()),
-            )
-            .field(
-                "sys_clk_div_denominator",
-                &format_args!("{}", self.sys_clk_div_denominator().bits()),
-            )
-            .field(
-                "apb_clk_div_num",
-                &format_args!("{}", self.apb_clk_div_num().bits()),
-            )
-            .field(
-                "apb_clk_div_numerator",
-                &format_args!("{}", self.apb_clk_div_numerator().bits()),
-            )
+            .field("sys_clk_div_numerator", &self.sys_clk_div_numerator())
+            .field("sys_clk_div_denominator", &self.sys_clk_div_denominator())
+            .field("apb_clk_div_num", &self.apb_clk_div_num())
+            .field("apb_clk_div_numerator", &self.apb_clk_div_numerator())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROOT_CLK_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/root_clk_ctrl3.rs b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl3.rs
index 2c87e37f35..3ff5c142dd 100644
--- a/esp32p4/src/hp_sys_clkrst/root_clk_ctrl3.rs
+++ b/esp32p4/src/hp_sys_clkrst/root_clk_ctrl3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROOT_CLK_CTRL3")
-            .field(
-                "apb_clk_div_denominator",
-                &format_args!("{}", self.apb_clk_div_denominator().bits()),
-            )
+            .field("apb_clk_div_denominator", &self.apb_clk_div_denominator())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROOT_CLK_CTRL3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl0.rs b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl0.rs
index 325420f530..c18603ed04 100644
--- a/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl0.rs
+++ b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl0.rs
@@ -296,143 +296,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SOC_CLK_CTRL0")
-            .field(
-                "core0_clic_clk_en",
-                &format_args!("{}", self.core0_clic_clk_en().bit()),
-            )
-            .field(
-                "core1_clic_clk_en",
-                &format_args!("{}", self.core1_clic_clk_en().bit()),
-            )
-            .field(
-                "misc_cpu_clk_en",
-                &format_args!("{}", self.misc_cpu_clk_en().bit()),
-            )
-            .field(
-                "core0_cpu_clk_en",
-                &format_args!("{}", self.core0_cpu_clk_en().bit()),
-            )
-            .field(
-                "core1_cpu_clk_en",
-                &format_args!("{}", self.core1_cpu_clk_en().bit()),
-            )
-            .field(
-                "tcm_cpu_clk_en",
-                &format_args!("{}", self.tcm_cpu_clk_en().bit()),
-            )
-            .field(
-                "busmon_cpu_clk_en",
-                &format_args!("{}", self.busmon_cpu_clk_en().bit()),
-            )
-            .field(
-                "l1cache_cpu_clk_en",
-                &format_args!("{}", self.l1cache_cpu_clk_en().bit()),
-            )
-            .field(
-                "l1cache_d_cpu_clk_en",
-                &format_args!("{}", self.l1cache_d_cpu_clk_en().bit()),
-            )
-            .field(
-                "l1cache_i0_cpu_clk_en",
-                &format_args!("{}", self.l1cache_i0_cpu_clk_en().bit()),
-            )
-            .field(
-                "l1cache_i1_cpu_clk_en",
-                &format_args!("{}", self.l1cache_i1_cpu_clk_en().bit()),
-            )
-            .field(
-                "trace_cpu_clk_en",
-                &format_args!("{}", self.trace_cpu_clk_en().bit()),
-            )
-            .field(
-                "icm_cpu_clk_en",
-                &format_args!("{}", self.icm_cpu_clk_en().bit()),
-            )
-            .field(
-                "gdma_cpu_clk_en",
-                &format_args!("{}", self.gdma_cpu_clk_en().bit()),
-            )
-            .field(
-                "vpu_cpu_clk_en",
-                &format_args!("{}", self.vpu_cpu_clk_en().bit()),
-            )
-            .field(
-                "l1cache_mem_clk_en",
-                &format_args!("{}", self.l1cache_mem_clk_en().bit()),
-            )
-            .field(
-                "l1cache_d_mem_clk_en",
-                &format_args!("{}", self.l1cache_d_mem_clk_en().bit()),
-            )
-            .field(
-                "l1cache_i0_mem_clk_en",
-                &format_args!("{}", self.l1cache_i0_mem_clk_en().bit()),
-            )
-            .field(
-                "l1cache_i1_mem_clk_en",
-                &format_args!("{}", self.l1cache_i1_mem_clk_en().bit()),
-            )
-            .field(
-                "l2cache_mem_clk_en",
-                &format_args!("{}", self.l2cache_mem_clk_en().bit()),
-            )
-            .field(
-                "l2mem_mem_clk_en",
-                &format_args!("{}", self.l2mem_mem_clk_en().bit()),
-            )
-            .field(
-                "l2memmon_mem_clk_en",
-                &format_args!("{}", self.l2memmon_mem_clk_en().bit()),
-            )
-            .field(
-                "icm_mem_clk_en",
-                &format_args!("{}", self.icm_mem_clk_en().bit()),
-            )
-            .field(
-                "misc_sys_clk_en",
-                &format_args!("{}", self.misc_sys_clk_en().bit()),
-            )
-            .field(
-                "trace_sys_clk_en",
-                &format_args!("{}", self.trace_sys_clk_en().bit()),
-            )
-            .field(
-                "l2cache_sys_clk_en",
-                &format_args!("{}", self.l2cache_sys_clk_en().bit()),
-            )
-            .field(
-                "l2mem_sys_clk_en",
-                &format_args!("{}", self.l2mem_sys_clk_en().bit()),
-            )
-            .field(
-                "l2memmon_sys_clk_en",
-                &format_args!("{}", self.l2memmon_sys_clk_en().bit()),
-            )
-            .field(
-                "tcmmon_sys_clk_en",
-                &format_args!("{}", self.tcmmon_sys_clk_en().bit()),
-            )
-            .field(
-                "icm_sys_clk_en",
-                &format_args!("{}", self.icm_sys_clk_en().bit()),
-            )
-            .field(
-                "flash_sys_clk_en",
-                &format_args!("{}", self.flash_sys_clk_en().bit()),
-            )
-            .field(
-                "psram_sys_clk_en",
-                &format_args!("{}", self.psram_sys_clk_en().bit()),
-            )
+            .field("core0_clic_clk_en", &self.core0_clic_clk_en())
+            .field("core1_clic_clk_en", &self.core1_clic_clk_en())
+            .field("misc_cpu_clk_en", &self.misc_cpu_clk_en())
+            .field("core0_cpu_clk_en", &self.core0_cpu_clk_en())
+            .field("core1_cpu_clk_en", &self.core1_cpu_clk_en())
+            .field("tcm_cpu_clk_en", &self.tcm_cpu_clk_en())
+            .field("busmon_cpu_clk_en", &self.busmon_cpu_clk_en())
+            .field("l1cache_cpu_clk_en", &self.l1cache_cpu_clk_en())
+            .field("l1cache_d_cpu_clk_en", &self.l1cache_d_cpu_clk_en())
+            .field("l1cache_i0_cpu_clk_en", &self.l1cache_i0_cpu_clk_en())
+            .field("l1cache_i1_cpu_clk_en", &self.l1cache_i1_cpu_clk_en())
+            .field("trace_cpu_clk_en", &self.trace_cpu_clk_en())
+            .field("icm_cpu_clk_en", &self.icm_cpu_clk_en())
+            .field("gdma_cpu_clk_en", &self.gdma_cpu_clk_en())
+            .field("vpu_cpu_clk_en", &self.vpu_cpu_clk_en())
+            .field("l1cache_mem_clk_en", &self.l1cache_mem_clk_en())
+            .field("l1cache_d_mem_clk_en", &self.l1cache_d_mem_clk_en())
+            .field("l1cache_i0_mem_clk_en", &self.l1cache_i0_mem_clk_en())
+            .field("l1cache_i1_mem_clk_en", &self.l1cache_i1_mem_clk_en())
+            .field("l2cache_mem_clk_en", &self.l2cache_mem_clk_en())
+            .field("l2mem_mem_clk_en", &self.l2mem_mem_clk_en())
+            .field("l2memmon_mem_clk_en", &self.l2memmon_mem_clk_en())
+            .field("icm_mem_clk_en", &self.icm_mem_clk_en())
+            .field("misc_sys_clk_en", &self.misc_sys_clk_en())
+            .field("trace_sys_clk_en", &self.trace_sys_clk_en())
+            .field("l2cache_sys_clk_en", &self.l2cache_sys_clk_en())
+            .field("l2mem_sys_clk_en", &self.l2mem_sys_clk_en())
+            .field("l2memmon_sys_clk_en", &self.l2memmon_sys_clk_en())
+            .field("tcmmon_sys_clk_en", &self.tcmmon_sys_clk_en())
+            .field("icm_sys_clk_en", &self.icm_sys_clk_en())
+            .field("flash_sys_clk_en", &self.flash_sys_clk_en())
+            .field("psram_sys_clk_en", &self.psram_sys_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SOC_CLK_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl1.rs b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl1.rs
index 13ff4ca038..4dbfe57454 100644
--- a/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl1.rs
+++ b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl1.rs
@@ -296,143 +296,47 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SOC_CLK_CTRL1")
-            .field(
-                "gpspi2_sys_clk_en",
-                &format_args!("{}", self.gpspi2_sys_clk_en().bit()),
-            )
-            .field(
-                "gpspi3_sys_clk_en",
-                &format_args!("{}", self.gpspi3_sys_clk_en().bit()),
-            )
-            .field(
-                "regdma_sys_clk_en",
-                &format_args!("{}", self.regdma_sys_clk_en().bit()),
-            )
-            .field(
-                "ahb_pdma_sys_clk_en",
-                &format_args!("{}", self.ahb_pdma_sys_clk_en().bit()),
-            )
-            .field(
-                "axi_pdma_sys_clk_en",
-                &format_args!("{}", self.axi_pdma_sys_clk_en().bit()),
-            )
-            .field(
-                "gdma_sys_clk_en",
-                &format_args!("{}", self.gdma_sys_clk_en().bit()),
-            )
-            .field(
-                "dma2d_sys_clk_en",
-                &format_args!("{}", self.dma2d_sys_clk_en().bit()),
-            )
-            .field(
-                "vpu_sys_clk_en",
-                &format_args!("{}", self.vpu_sys_clk_en().bit()),
-            )
-            .field(
-                "jpeg_sys_clk_en",
-                &format_args!("{}", self.jpeg_sys_clk_en().bit()),
-            )
-            .field(
-                "ppa_sys_clk_en",
-                &format_args!("{}", self.ppa_sys_clk_en().bit()),
-            )
-            .field(
-                "csi_brg_sys_clk_en",
-                &format_args!("{}", self.csi_brg_sys_clk_en().bit()),
-            )
-            .field(
-                "csi_host_sys_clk_en",
-                &format_args!("{}", self.csi_host_sys_clk_en().bit()),
-            )
-            .field(
-                "dsi_sys_clk_en",
-                &format_args!("{}", self.dsi_sys_clk_en().bit()),
-            )
-            .field(
-                "emac_sys_clk_en",
-                &format_args!("{}", self.emac_sys_clk_en().bit()),
-            )
-            .field(
-                "sdmmc_sys_clk_en",
-                &format_args!("{}", self.sdmmc_sys_clk_en().bit()),
-            )
-            .field(
-                "usb_otg11_sys_clk_en",
-                &format_args!("{}", self.usb_otg11_sys_clk_en().bit()),
-            )
-            .field(
-                "usb_otg20_sys_clk_en",
-                &format_args!("{}", self.usb_otg20_sys_clk_en().bit()),
-            )
-            .field(
-                "uhci_sys_clk_en",
-                &format_args!("{}", self.uhci_sys_clk_en().bit()),
-            )
-            .field(
-                "uart0_sys_clk_en",
-                &format_args!("{}", self.uart0_sys_clk_en().bit()),
-            )
-            .field(
-                "uart1_sys_clk_en",
-                &format_args!("{}", self.uart1_sys_clk_en().bit()),
-            )
-            .field(
-                "uart2_sys_clk_en",
-                &format_args!("{}", self.uart2_sys_clk_en().bit()),
-            )
-            .field(
-                "uart3_sys_clk_en",
-                &format_args!("{}", self.uart3_sys_clk_en().bit()),
-            )
-            .field(
-                "uart4_sys_clk_en",
-                &format_args!("{}", self.uart4_sys_clk_en().bit()),
-            )
-            .field(
-                "parlio_sys_clk_en",
-                &format_args!("{}", self.parlio_sys_clk_en().bit()),
-            )
-            .field(
-                "etm_sys_clk_en",
-                &format_args!("{}", self.etm_sys_clk_en().bit()),
-            )
-            .field(
-                "pvt_sys_clk_en",
-                &format_args!("{}", self.pvt_sys_clk_en().bit()),
-            )
-            .field(
-                "crypto_sys_clk_en",
-                &format_args!("{}", self.crypto_sys_clk_en().bit()),
-            )
-            .field(
-                "key_manager_sys_clk_en",
-                &format_args!("{}", self.key_manager_sys_clk_en().bit()),
-            )
-            .field(
-                "bitsrambler_sys_clk_en",
-                &format_args!("{}", self.bitsrambler_sys_clk_en().bit()),
-            )
+            .field("gpspi2_sys_clk_en", &self.gpspi2_sys_clk_en())
+            .field("gpspi3_sys_clk_en", &self.gpspi3_sys_clk_en())
+            .field("regdma_sys_clk_en", &self.regdma_sys_clk_en())
+            .field("ahb_pdma_sys_clk_en", &self.ahb_pdma_sys_clk_en())
+            .field("axi_pdma_sys_clk_en", &self.axi_pdma_sys_clk_en())
+            .field("gdma_sys_clk_en", &self.gdma_sys_clk_en())
+            .field("dma2d_sys_clk_en", &self.dma2d_sys_clk_en())
+            .field("vpu_sys_clk_en", &self.vpu_sys_clk_en())
+            .field("jpeg_sys_clk_en", &self.jpeg_sys_clk_en())
+            .field("ppa_sys_clk_en", &self.ppa_sys_clk_en())
+            .field("csi_brg_sys_clk_en", &self.csi_brg_sys_clk_en())
+            .field("csi_host_sys_clk_en", &self.csi_host_sys_clk_en())
+            .field("dsi_sys_clk_en", &self.dsi_sys_clk_en())
+            .field("emac_sys_clk_en", &self.emac_sys_clk_en())
+            .field("sdmmc_sys_clk_en", &self.sdmmc_sys_clk_en())
+            .field("usb_otg11_sys_clk_en", &self.usb_otg11_sys_clk_en())
+            .field("usb_otg20_sys_clk_en", &self.usb_otg20_sys_clk_en())
+            .field("uhci_sys_clk_en", &self.uhci_sys_clk_en())
+            .field("uart0_sys_clk_en", &self.uart0_sys_clk_en())
+            .field("uart1_sys_clk_en", &self.uart1_sys_clk_en())
+            .field("uart2_sys_clk_en", &self.uart2_sys_clk_en())
+            .field("uart3_sys_clk_en", &self.uart3_sys_clk_en())
+            .field("uart4_sys_clk_en", &self.uart4_sys_clk_en())
+            .field("parlio_sys_clk_en", &self.parlio_sys_clk_en())
+            .field("etm_sys_clk_en", &self.etm_sys_clk_en())
+            .field("pvt_sys_clk_en", &self.pvt_sys_clk_en())
+            .field("crypto_sys_clk_en", &self.crypto_sys_clk_en())
+            .field("key_manager_sys_clk_en", &self.key_manager_sys_clk_en())
+            .field("bitsrambler_sys_clk_en", &self.bitsrambler_sys_clk_en())
             .field(
                 "bitsrambler_rx_sys_clk_en",
-                &format_args!("{}", self.bitsrambler_rx_sys_clk_en().bit()),
+                &self.bitsrambler_rx_sys_clk_en(),
             )
             .field(
                 "bitsrambler_tx_sys_clk_en",
-                &format_args!("{}", self.bitsrambler_tx_sys_clk_en().bit()),
-            )
-            .field(
-                "h264_sys_clk_en",
-                &format_args!("{}", self.h264_sys_clk_en().bit()),
+                &self.bitsrambler_tx_sys_clk_en(),
             )
+            .field("h264_sys_clk_en", &self.h264_sys_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SOC_CLK_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl2.rs b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl2.rs
index d42959729c..08fd62929c 100644
--- a/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl2.rs
+++ b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl2.rs
@@ -296,143 +296,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SOC_CLK_CTRL2")
-            .field(
-                "rmt_sys_clk_en",
-                &format_args!("{}", self.rmt_sys_clk_en().bit()),
-            )
-            .field(
-                "hp_clkrst_apb_clk_en",
-                &format_args!("{}", self.hp_clkrst_apb_clk_en().bit()),
-            )
-            .field(
-                "sysreg_apb_clk_en",
-                &format_args!("{}", self.sysreg_apb_clk_en().bit()),
-            )
-            .field(
-                "icm_apb_clk_en",
-                &format_args!("{}", self.icm_apb_clk_en().bit()),
-            )
-            .field(
-                "intrmtx_apb_clk_en",
-                &format_args!("{}", self.intrmtx_apb_clk_en().bit()),
-            )
-            .field(
-                "adc_apb_clk_en",
-                &format_args!("{}", self.adc_apb_clk_en().bit()),
-            )
-            .field(
-                "uhci_apb_clk_en",
-                &format_args!("{}", self.uhci_apb_clk_en().bit()),
-            )
-            .field(
-                "uart0_apb_clk_en",
-                &format_args!("{}", self.uart0_apb_clk_en().bit()),
-            )
-            .field(
-                "uart1_apb_clk_en",
-                &format_args!("{}", self.uart1_apb_clk_en().bit()),
-            )
-            .field(
-                "uart2_apb_clk_en",
-                &format_args!("{}", self.uart2_apb_clk_en().bit()),
-            )
-            .field(
-                "uart3_apb_clk_en",
-                &format_args!("{}", self.uart3_apb_clk_en().bit()),
-            )
-            .field(
-                "uart4_apb_clk_en",
-                &format_args!("{}", self.uart4_apb_clk_en().bit()),
-            )
-            .field(
-                "i2c0_apb_clk_en",
-                &format_args!("{}", self.i2c0_apb_clk_en().bit()),
-            )
-            .field(
-                "i2c1_apb_clk_en",
-                &format_args!("{}", self.i2c1_apb_clk_en().bit()),
-            )
-            .field(
-                "i2s0_apb_clk_en",
-                &format_args!("{}", self.i2s0_apb_clk_en().bit()),
-            )
-            .field(
-                "i2s1_apb_clk_en",
-                &format_args!("{}", self.i2s1_apb_clk_en().bit()),
-            )
-            .field(
-                "i2s2_apb_clk_en",
-                &format_args!("{}", self.i2s2_apb_clk_en().bit()),
-            )
-            .field(
-                "i3c_mst_apb_clk_en",
-                &format_args!("{}", self.i3c_mst_apb_clk_en().bit()),
-            )
-            .field(
-                "i3c_slv_apb_clk_en",
-                &format_args!("{}", self.i3c_slv_apb_clk_en().bit()),
-            )
-            .field(
-                "gpspi2_apb_clk_en",
-                &format_args!("{}", self.gpspi2_apb_clk_en().bit()),
-            )
-            .field(
-                "gpspi3_apb_clk_en",
-                &format_args!("{}", self.gpspi3_apb_clk_en().bit()),
-            )
-            .field(
-                "timergrp0_apb_clk_en",
-                &format_args!("{}", self.timergrp0_apb_clk_en().bit()),
-            )
-            .field(
-                "timergrp1_apb_clk_en",
-                &format_args!("{}", self.timergrp1_apb_clk_en().bit()),
-            )
-            .field(
-                "systimer_apb_clk_en",
-                &format_args!("{}", self.systimer_apb_clk_en().bit()),
-            )
-            .field(
-                "twai0_apb_clk_en",
-                &format_args!("{}", self.twai0_apb_clk_en().bit()),
-            )
-            .field(
-                "twai1_apb_clk_en",
-                &format_args!("{}", self.twai1_apb_clk_en().bit()),
-            )
-            .field(
-                "twai2_apb_clk_en",
-                &format_args!("{}", self.twai2_apb_clk_en().bit()),
-            )
-            .field(
-                "mcpwm0_apb_clk_en",
-                &format_args!("{}", self.mcpwm0_apb_clk_en().bit()),
-            )
-            .field(
-                "mcpwm1_apb_clk_en",
-                &format_args!("{}", self.mcpwm1_apb_clk_en().bit()),
-            )
-            .field(
-                "usb_device_apb_clk_en",
-                &format_args!("{}", self.usb_device_apb_clk_en().bit()),
-            )
-            .field(
-                "pcnt_apb_clk_en",
-                &format_args!("{}", self.pcnt_apb_clk_en().bit()),
-            )
-            .field(
-                "parlio_apb_clk_en",
-                &format_args!("{}", self.parlio_apb_clk_en().bit()),
-            )
+            .field("rmt_sys_clk_en", &self.rmt_sys_clk_en())
+            .field("hp_clkrst_apb_clk_en", &self.hp_clkrst_apb_clk_en())
+            .field("sysreg_apb_clk_en", &self.sysreg_apb_clk_en())
+            .field("icm_apb_clk_en", &self.icm_apb_clk_en())
+            .field("intrmtx_apb_clk_en", &self.intrmtx_apb_clk_en())
+            .field("adc_apb_clk_en", &self.adc_apb_clk_en())
+            .field("uhci_apb_clk_en", &self.uhci_apb_clk_en())
+            .field("uart0_apb_clk_en", &self.uart0_apb_clk_en())
+            .field("uart1_apb_clk_en", &self.uart1_apb_clk_en())
+            .field("uart2_apb_clk_en", &self.uart2_apb_clk_en())
+            .field("uart3_apb_clk_en", &self.uart3_apb_clk_en())
+            .field("uart4_apb_clk_en", &self.uart4_apb_clk_en())
+            .field("i2c0_apb_clk_en", &self.i2c0_apb_clk_en())
+            .field("i2c1_apb_clk_en", &self.i2c1_apb_clk_en())
+            .field("i2s0_apb_clk_en", &self.i2s0_apb_clk_en())
+            .field("i2s1_apb_clk_en", &self.i2s1_apb_clk_en())
+            .field("i2s2_apb_clk_en", &self.i2s2_apb_clk_en())
+            .field("i3c_mst_apb_clk_en", &self.i3c_mst_apb_clk_en())
+            .field("i3c_slv_apb_clk_en", &self.i3c_slv_apb_clk_en())
+            .field("gpspi2_apb_clk_en", &self.gpspi2_apb_clk_en())
+            .field("gpspi3_apb_clk_en", &self.gpspi3_apb_clk_en())
+            .field("timergrp0_apb_clk_en", &self.timergrp0_apb_clk_en())
+            .field("timergrp1_apb_clk_en", &self.timergrp1_apb_clk_en())
+            .field("systimer_apb_clk_en", &self.systimer_apb_clk_en())
+            .field("twai0_apb_clk_en", &self.twai0_apb_clk_en())
+            .field("twai1_apb_clk_en", &self.twai1_apb_clk_en())
+            .field("twai2_apb_clk_en", &self.twai2_apb_clk_en())
+            .field("mcpwm0_apb_clk_en", &self.mcpwm0_apb_clk_en())
+            .field("mcpwm1_apb_clk_en", &self.mcpwm1_apb_clk_en())
+            .field("usb_device_apb_clk_en", &self.usb_device_apb_clk_en())
+            .field("pcnt_apb_clk_en", &self.pcnt_apb_clk_en())
+            .field("parlio_apb_clk_en", &self.parlio_apb_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SOC_CLK_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl3.rs b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl3.rs
index 5a4b36dcb5..3969b74388 100644
--- a/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl3.rs
+++ b/esp32p4/src/hp_sys_clkrst/soc_clk_ctrl3.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SOC_CLK_CTRL3")
-            .field(
-                "ledc_apb_clk_en",
-                &format_args!("{}", self.ledc_apb_clk_en().bit()),
-            )
-            .field(
-                "lcdcam_apb_clk_en",
-                &format_args!("{}", self.lcdcam_apb_clk_en().bit()),
-            )
-            .field(
-                "etm_apb_clk_en",
-                &format_args!("{}", self.etm_apb_clk_en().bit()),
-            )
-            .field(
-                "iomux_apb_clk_en",
-                &format_args!("{}", self.iomux_apb_clk_en().bit()),
-            )
+            .field("ledc_apb_clk_en", &self.ledc_apb_clk_en())
+            .field("lcdcam_apb_clk_en", &self.lcdcam_apb_clk_en())
+            .field("etm_apb_clk_en", &self.etm_apb_clk_en())
+            .field("iomux_apb_clk_en", &self.iomux_apb_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SOC_CLK_CTRL3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/clk_conf.rs b/esp32p4/src/i2c0/clk_conf.rs
index 0c369fb990..8575bb85bf 100644
--- a/esp32p4/src/i2c0/clk_conf.rs
+++ b/esp32p4/src/i2c0/clk_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bit()))
-            .field("sclk_active", &format_args!("{}", self.sclk_active().bit()))
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_active", &self.sclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/comd.rs b/esp32p4/src/i2c0/comd.rs
index dac825d348..bfc17217e0 100644
--- a/esp32p4/src/i2c0/comd.rs
+++ b/esp32p4/src/i2c0/comd.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMD")
-            .field("command", &format_args!("{}", self.command().bits()))
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Configures command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information."]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/ctr.rs b/esp32p4/src/i2c0/ctr.rs
index 6ab9cb8bf3..41a68ba5e1 100644
--- a/esp32p4/src/i2c0/ctr.rs
+++ b/esp32p4/src/i2c0/ctr.rs
@@ -122,57 +122,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTR")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field(
-                "sample_scl_level",
-                &format_args!("{}", self.sample_scl_level().bit()),
-            )
-            .field(
-                "rx_full_ack_level",
-                &format_args!("{}", self.rx_full_ack_level().bit()),
-            )
-            .field("ms_mode", &format_args!("{}", self.ms_mode().bit()))
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "arbitration_en",
-                &format_args!("{}", self.arbitration_en().bit()),
-            )
-            .field(
-                "slv_tx_auto_start_en",
-                &format_args!("{}", self.slv_tx_auto_start_en().bit()),
-            )
-            .field(
-                "addr_10bit_rw_check_en",
-                &format_args!("{}", self.addr_10bit_rw_check_en().bit()),
-            )
-            .field(
-                "addr_broadcasting_en",
-                &format_args!("{}", self.addr_broadcasting_en().bit()),
-            )
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("sample_scl_level", &self.sample_scl_level())
+            .field("rx_full_ack_level", &self.rx_full_ack_level())
+            .field("ms_mode", &self.ms_mode())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("clk_en", &self.clk_en())
+            .field("arbitration_en", &self.arbitration_en())
+            .field("slv_tx_auto_start_en", &self.slv_tx_auto_start_en())
+            .field("addr_10bit_rw_check_en", &self.addr_10bit_rw_check_en())
+            .field("addr_broadcasting_en", &self.addr_broadcasting_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures the SDA output mode 1: Direct output, 0: Open drain output."]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/data.rs b/esp32p4/src/i2c0/data.rs
index 8987c4faf0..9fa567e42f 100644
--- a/esp32p4/src/i2c0/data.rs
+++ b/esp32p4/src/i2c0/data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field("fifo_rdata", &format_args!("{}", self.fifo_rdata().bits()))
+            .field("fifo_rdata", &self.fifo_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Rx FIFO read data.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DATA_SPEC;
 impl crate::RegisterSpec for DATA_SPEC {
diff --git a/esp32p4/src/i2c0/date.rs b/esp32p4/src/i2c0/date.rs
index 154c1795f0..7b11449653 100644
--- a/esp32p4/src/i2c0/date.rs
+++ b/esp32p4/src/i2c0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/i2c0/fifo_conf.rs b/esp32p4/src/i2c0/fifo_conf.rs
index e222f5b450..8210851a63 100644
--- a/esp32p4/src/i2c0/fifo_conf.rs
+++ b/esp32p4/src/i2c0/fifo_conf.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CONF")
-            .field(
-                "rxfifo_wm_thrhd",
-                &format_args!("{}", self.rxfifo_wm_thrhd().bits()),
-            )
-            .field(
-                "txfifo_wm_thrhd",
-                &format_args!("{}", self.txfifo_wm_thrhd().bits()),
-            )
-            .field("nonfifo_en", &format_args!("{}", self.nonfifo_en().bit()))
-            .field(
-                "fifo_addr_cfg_en",
-                &format_args!("{}", self.fifo_addr_cfg_en().bit()),
-            )
-            .field("rx_fifo_rst", &format_args!("{}", self.rx_fifo_rst().bit()))
-            .field("tx_fifo_rst", &format_args!("{}", self.tx_fifo_rst().bit()))
-            .field("fifo_prt_en", &format_args!("{}", self.fifo_prt_en().bit()))
+            .field("rxfifo_wm_thrhd", &self.rxfifo_wm_thrhd())
+            .field("txfifo_wm_thrhd", &self.txfifo_wm_thrhd())
+            .field("nonfifo_en", &self.nonfifo_en())
+            .field("fifo_addr_cfg_en", &self.fifo_addr_cfg_en())
+            .field("rx_fifo_rst", &self.rx_fifo_rst())
+            .field("tx_fifo_rst", &self.tx_fifo_rst())
+            .field("fifo_prt_en", &self.fifo_prt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[4:0\\], reg_rxfifo_wm_int_raw bit will be valid."]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/fifo_st.rs b/esp32p4/src/i2c0/fifo_st.rs
index d0210fbe90..14e1b17981 100644
--- a/esp32p4/src/i2c0/fifo_st.rs
+++ b/esp32p4/src/i2c0/fifo_st.rs
@@ -41,35 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_ST")
-            .field(
-                "rxfifo_raddr",
-                &format_args!("{}", self.rxfifo_raddr().bits()),
-            )
-            .field(
-                "rxfifo_waddr",
-                &format_args!("{}", self.rxfifo_waddr().bits()),
-            )
-            .field(
-                "txfifo_raddr",
-                &format_args!("{}", self.txfifo_raddr().bits()),
-            )
-            .field(
-                "txfifo_waddr",
-                &format_args!("{}", self.txfifo_waddr().bits()),
-            )
-            .field(
-                "slave_rw_point",
-                &format_args!("{}", self.slave_rw_point().bits()),
-            )
+            .field("rxfifo_raddr", &self.rxfifo_raddr())
+            .field("rxfifo_waddr", &self.rxfifo_waddr())
+            .field("txfifo_raddr", &self.txfifo_raddr())
+            .field("txfifo_waddr", &self.txfifo_waddr())
+            .field("slave_rw_point", &self.slave_rw_point())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "FIFO status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_ST_SPEC;
 impl crate::RegisterSpec for FIFO_ST_SPEC {
diff --git a/esp32p4/src/i2c0/filter_cfg.rs b/esp32p4/src/i2c0/filter_cfg.rs
index 45f6761a6d..cd0010ee77 100644
--- a/esp32p4/src/i2c0/filter_cfg.rs
+++ b/esp32p4/src/i2c0/filter_cfg.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CFG")
-            .field(
-                "scl_filter_thres",
-                &format_args!("{}", self.scl_filter_thres().bits()),
-            )
-            .field(
-                "sda_filter_thres",
-                &format_args!("{}", self.sda_filter_thres().bits()),
-            )
-            .field(
-                "scl_filter_en",
-                &format_args!("{}", self.scl_filter_en().bit()),
-            )
-            .field(
-                "sda_filter_en",
-                &format_args!("{}", self.sda_filter_en().bit()),
-            )
+            .field("scl_filter_thres", &self.scl_filter_thres())
+            .field("sda_filter_thres", &self.sda_filter_thres())
+            .field("scl_filter_en", &self.scl_filter_en())
+            .field("sda_filter_en", &self.sda_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/int_ena.rs b/esp32p4/src/i2c0/int_ena.rs
index f737a63251..3f638f16ee 100644
--- a/esp32p4/src/i2c0/int_ena.rs
+++ b/esp32p4/src/i2c0/int_ena.rs
@@ -179,58 +179,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
-            .field(
-                "general_call",
-                &format_args!("{}", self.general_call().bit()),
-            )
-            .field(
-                "slave_addr_unmatch",
-                &format_args!("{}", self.slave_addr_unmatch().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
+            .field("general_call", &self.general_call())
+            .field("slave_addr_unmatch", &self.slave_addr_unmatch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to enable I2C_RXFIFO_WM_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/int_raw.rs b/esp32p4/src/i2c0/int_raw.rs
index 1436c65333..d55ee7ffb0 100644
--- a/esp32p4/src/i2c0/int_raw.rs
+++ b/esp32p4/src/i2c0/int_raw.rs
@@ -139,58 +139,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
-            .field(
-                "general_call",
-                &format_args!("{}", self.general_call().bit()),
-            )
-            .field(
-                "slave_addr_unmatch",
-                &format_args!("{}", self.slave_addr_unmatch().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
+            .field("general_call", &self.general_call())
+            .field("slave_addr_unmatch", &self.slave_addr_unmatch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32p4/src/i2c0/int_st.rs b/esp32p4/src/i2c0/int_st.rs
index 259eea6b12..72cf0fae4d 100644
--- a/esp32p4/src/i2c0/int_st.rs
+++ b/esp32p4/src/i2c0/int_st.rs
@@ -139,58 +139,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
-            .field(
-                "general_call",
-                &format_args!("{}", self.general_call().bit()),
-            )
-            .field(
-                "slave_addr_unmatch",
-                &format_args!("{}", self.slave_addr_unmatch().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
+            .field("general_call", &self.general_call())
+            .field("slave_addr_unmatch", &self.slave_addr_unmatch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of captured I2C communication events\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/i2c0/rxfifo_start_addr.rs b/esp32p4/src/i2c0/rxfifo_start_addr.rs
index 067266ecf1..1f42f0bb10 100644
--- a/esp32p4/src/i2c0/rxfifo_start_addr.rs
+++ b/esp32p4/src/i2c0/rxfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXFIFO_START_ADDR")
-            .field(
-                "rxfifo_start_addr",
-                &format_args!("{}", self.rxfifo_start_addr().bits()),
-            )
+            .field("rxfifo_start_addr", &self.rxfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C RXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for RXFIFO_START_ADDR_SPEC {
diff --git a/esp32p4/src/i2c0/scl_high_period.rs b/esp32p4/src/i2c0/scl_high_period.rs
index 1c3e204567..1df7cb180b 100644
--- a/esp32p4/src/i2c0/scl_high_period.rs
+++ b/esp32p4/src/i2c0/scl_high_period.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH_PERIOD")
-            .field(
-                "scl_high_period",
-                &format_args!("{}", self.scl_high_period().bits()),
-            )
-            .field(
-                "scl_wait_high_period",
-                &format_args!("{}", self.scl_wait_high_period().bits()),
-            )
+            .field("scl_high_period", &self.scl_high_period())
+            .field("scl_wait_high_period", &self.scl_wait_high_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures for how long SCL remains high in master mode. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/scl_low_period.rs b/esp32p4/src/i2c0/scl_low_period.rs
index 8088e04de0..7c222c5e93 100644
--- a/esp32p4/src/i2c0/scl_low_period.rs
+++ b/esp32p4/src/i2c0/scl_low_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW_PERIOD")
-            .field(
-                "scl_low_period",
-                &format_args!("{}", self.scl_low_period().bits()),
-            )
+            .field("scl_low_period", &self.scl_low_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures the low level width of the SCL Clock. Measurement unit: i2c_sclk."]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/scl_main_st_time_out.rs b/esp32p4/src/i2c0/scl_main_st_time_out.rs
index 4aecde25ab..ab1bc1474e 100644
--- a/esp32p4/src/i2c0/scl_main_st_time_out.rs
+++ b/esp32p4/src/i2c0/scl_main_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_MAIN_ST_TIME_OUT")
-            .field(
-                "scl_main_st_to_i2c",
-                &format_args!("{}", self.scl_main_st_to_i2c().bits()),
-            )
+            .field("scl_main_st_to_i2c", &self.scl_main_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_MAIN_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/scl_rstart_setup.rs b/esp32p4/src/i2c0/scl_rstart_setup.rs
index c8bc95dba1..522b4ff4ef 100644
--- a/esp32p4/src/i2c0/scl_rstart_setup.rs
+++ b/esp32p4/src/i2c0/scl_rstart_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_RSTART_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_RSTART_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/scl_sp_conf.rs b/esp32p4/src/i2c0/scl_sp_conf.rs
index 8bbc05b0e5..0646f979bc 100644
--- a/esp32p4/src/i2c0/scl_sp_conf.rs
+++ b/esp32p4/src/i2c0/scl_sp_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_SP_CONF")
-            .field(
-                "scl_rst_slv_en",
-                &format_args!("{}", self.scl_rst_slv_en().bit()),
-            )
-            .field(
-                "scl_rst_slv_num",
-                &format_args!("{}", self.scl_rst_slv_num().bits()),
-            )
-            .field("scl_pd_en", &format_args!("{}", self.scl_pd_en().bit()))
-            .field("sda_pd_en", &format_args!("{}", self.sda_pd_en().bit()))
+            .field("scl_rst_slv_en", &self.scl_rst_slv_en())
+            .field("scl_rst_slv_num", &self.scl_rst_slv_num())
+            .field("scl_pd_en", &self.scl_pd_en())
+            .field("sda_pd_en", &self.sda_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_SP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/scl_st_time_out.rs b/esp32p4/src/i2c0/scl_st_time_out.rs
index c9a6f6d300..28832dad1f 100644
--- a/esp32p4/src/i2c0/scl_st_time_out.rs
+++ b/esp32p4/src/i2c0/scl_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_ST_TIME_OUT")
-            .field(
-                "scl_st_to_i2c",
-                &format_args!("{}", self.scl_st_to_i2c().bits()),
-            )
+            .field("scl_st_to_i2c", &self.scl_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/scl_start_hold.rs b/esp32p4/src/i2c0/scl_start_hold.rs
index 87e4288b59..e9a36d3973 100644
--- a/esp32p4/src/i2c0/scl_start_hold.rs
+++ b/esp32p4/src/i2c0/scl_start_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. Measurement unit: i2c_sclk."]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/scl_stop_hold.rs b/esp32p4/src/i2c0/scl_stop_hold.rs
index aac05a54ef..52e10c120f 100644
--- a/esp32p4/src/i2c0/scl_stop_hold.rs
+++ b/esp32p4/src/i2c0/scl_stop_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures the delay after the STOP condition. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/scl_stop_setup.rs b/esp32p4/src/i2c0/scl_stop_setup.rs
index 5f04ccf508..01367b285b 100644
--- a/esp32p4/src/i2c0/scl_stop_setup.rs
+++ b/esp32p4/src/i2c0/scl_stop_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures the time between the rising edge of SCL and the rising edge of SDA. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/scl_stretch_conf.rs b/esp32p4/src/i2c0/scl_stretch_conf.rs
index 74dfd3dfea..81b109f3fe 100644
--- a/esp32p4/src/i2c0/scl_stretch_conf.rs
+++ b/esp32p4/src/i2c0/scl_stretch_conf.rs
@@ -46,31 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STRETCH_CONF")
-            .field(
-                "stretch_protect_num",
-                &format_args!("{}", self.stretch_protect_num().bits()),
-            )
-            .field(
-                "slave_scl_stretch_en",
-                &format_args!("{}", self.slave_scl_stretch_en().bit()),
-            )
-            .field(
-                "slave_byte_ack_ctl_en",
-                &format_args!("{}", self.slave_byte_ack_ctl_en().bit()),
-            )
-            .field(
-                "slave_byte_ack_lvl",
-                &format_args!("{}", self.slave_byte_ack_lvl().bit()),
-            )
+            .field("stretch_protect_num", &self.stretch_protect_num())
+            .field("slave_scl_stretch_en", &self.slave_scl_stretch_en())
+            .field("slave_byte_ack_ctl_en", &self.slave_byte_ack_ctl_en())
+            .field("slave_byte_ack_lvl", &self.slave_byte_ack_lvl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STRETCH_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - Configures the time period to release the SCL line from stretching to avoid timing violation. Usually it should be larger than the SDA setup time. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/sda_hold.rs b/esp32p4/src/i2c0/sda_hold.rs
index dc93a49e22..ff54b9533d 100644
--- a/esp32p4/src/i2c0/sda_hold.rs
+++ b/esp32p4/src/i2c0/sda_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures the time to hold the data after the falling edge of SCL. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/sda_sample.rs b/esp32p4/src/i2c0/sda_sample.rs
index fed1f6154d..24ede7a043 100644
--- a/esp32p4/src/i2c0/sda_sample.rs
+++ b/esp32p4/src/i2c0/sda_sample.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_SAMPLE")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures the sample time after a positive SCL edge. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/slave_addr.rs b/esp32p4/src/i2c0/slave_addr.rs
index eac17ae090..a0b08e6b1f 100644
--- a/esp32p4/src/i2c0/slave_addr.rs
+++ b/esp32p4/src/i2c0/slave_addr.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE_ADDR")
-            .field("slave_addr", &format_args!("{}", self.slave_addr().bits()))
-            .field(
-                "addr_10bit_en",
-                &format_args!("{}", self.addr_10bit_en().bit()),
-            )
+            .field("slave_addr", &self.slave_addr())
+            .field("addr_10bit_en", &self.addr_10bit_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - Configure the slave address of I2C Slave."]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/sr.rs b/esp32p4/src/i2c0/sr.rs
index 6e8edc0bb9..0fd2be2773 100644
--- a/esp32p4/src/i2c0/sr.rs
+++ b/esp32p4/src/i2c0/sr.rs
@@ -76,37 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR")
-            .field("resp_rec", &format_args!("{}", self.resp_rec().bit()))
-            .field("slave_rw", &format_args!("{}", self.slave_rw().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field(
-                "slave_addressed",
-                &format_args!("{}", self.slave_addressed().bit()),
-            )
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field(
-                "stretch_cause",
-                &format_args!("{}", self.stretch_cause().bits()),
-            )
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field(
-                "scl_main_state_last",
-                &format_args!("{}", self.scl_main_state_last().bits()),
-            )
-            .field(
-                "scl_state_last",
-                &format_args!("{}", self.scl_state_last().bits()),
-            )
+            .field("resp_rec", &self.resp_rec())
+            .field("slave_rw", &self.slave_rw())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("slave_addressed", &self.slave_addressed())
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("stretch_cause", &self.stretch_cause())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("scl_main_state_last", &self.scl_main_state_last())
+            .field("scl_state_last", &self.scl_state_last())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Describe I2C work status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SR_SPEC;
 impl crate::RegisterSpec for SR_SPEC {
diff --git a/esp32p4/src/i2c0/to.rs b/esp32p4/src/i2c0/to.rs
index 671fc7e961..17a2cd5f55 100644
--- a/esp32p4/src/i2c0/to.rs
+++ b/esp32p4/src/i2c0/to.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO")
-            .field(
-                "time_out_value",
-                &format_args!("{}", self.time_out_value().bits()),
-            )
-            .field("time_out_en", &format_args!("{}", self.time_out_en().bit()))
+            .field("time_out_value", &self.time_out_value())
+            .field("time_out_en", &self.time_out_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). Measurement unit: i2c_sclk."]
     #[inline(always)]
diff --git a/esp32p4/src/i2c0/txfifo_start_addr.rs b/esp32p4/src/i2c0/txfifo_start_addr.rs
index a56802879f..93b2a29e2e 100644
--- a/esp32p4/src/i2c0/txfifo_start_addr.rs
+++ b/esp32p4/src/i2c0/txfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXFIFO_START_ADDR")
-            .field(
-                "txfifo_start_addr",
-                &format_args!("{}", self.txfifo_start_addr().bits()),
-            )
+            .field("txfifo_start_addr", &self.txfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C TXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for TXFIFO_START_ADDR_SPEC {
diff --git a/esp32p4/src/i2s0/bck_cnt.rs b/esp32p4/src/i2s0/bck_cnt.rs
index 355ec49125..91348f2b00 100644
--- a/esp32p4/src/i2s0/bck_cnt.rs
+++ b/esp32p4/src/i2s0/bck_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BCK_CNT")
-            .field("tx_bck_cnt", &format_args!("{}", self.tx_bck_cnt().bits()))
+            .field("tx_bck_cnt", &self.tx_bck_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BCK_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Set this bit to reset tx bck counter."]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/clk_gate.rs b/esp32p4/src/i2s0/clk_gate.rs
index c88aa3b6fb..0ba6bebfeb 100644
--- a/esp32p4/src/i2s0/clk_gate.rs
+++ b/esp32p4/src/i2s0/clk_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this bit to enable clock gate"]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/conf_sigle_data.rs b/esp32p4/src/i2s0/conf_sigle_data.rs
index f979345988..3c75f59255 100644
--- a/esp32p4/src/i2s0/conf_sigle_data.rs
+++ b/esp32p4/src/i2s0/conf_sigle_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_SIGLE_DATA")
-            .field(
-                "single_data",
-                &format_args!("{}", self.single_data().bits()),
-            )
+            .field("single_data", &self.single_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SIGLE_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The configured constant channel data to be sent out."]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/date.rs b/esp32p4/src/i2s0/date.rs
index a2c2908959..25c8f6a479 100644
--- a/esp32p4/src/i2s0/date.rs
+++ b/esp32p4/src/i2s0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/i2s0/etm_conf.rs b/esp32p4/src/i2s0/etm_conf.rs
index ba87038a24..456f1152f9 100644
--- a/esp32p4/src/i2s0/etm_conf.rs
+++ b/esp32p4/src/i2s0/etm_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ETM_CONF")
-            .field(
-                "etm_tx_send_word_num",
-                &format_args!("{}", self.etm_tx_send_word_num().bits()),
-            )
-            .field(
-                "etm_rx_receive_word_num",
-                &format_args!("{}", self.etm_rx_receive_word_num().bits()),
-            )
+            .field("etm_tx_send_word_num", &self.etm_tx_send_word_num())
+            .field("etm_rx_receive_word_num", &self.etm_rx_receive_word_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ETM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num\\[9:0\\], i2s will trigger an etm event."]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/fifo_cnt.rs b/esp32p4/src/i2s0/fifo_cnt.rs
index 296b325698..2515352337 100644
--- a/esp32p4/src/i2s0/fifo_cnt.rs
+++ b/esp32p4/src/i2s0/fifo_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CNT")
-            .field(
-                "tx_fifo_cnt",
-                &format_args!("{}", self.tx_fifo_cnt().bits()),
-            )
+            .field("tx_fifo_cnt", &self.tx_fifo_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Set this bit to reset tx fifo counter."]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/int_ena.rs b/esp32p4/src/i2s0/int_ena.rs
index ffbc92bacc..0a538b90e5 100644
--- a/esp32p4/src/i2s0/int_ena.rs
+++ b/esp32p4/src/i2s0/int_ena.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/int_raw.rs b/esp32p4/src/i2s0/int_raw.rs
index 7ec2d42cfd..e69602c0be 100644
--- a/esp32p4/src/i2s0/int_raw.rs
+++ b/esp32p4/src/i2s0/int_raw.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32p4/src/i2s0/int_st.rs b/esp32p4/src/i2s0/int_st.rs
index 5eac7b9c9d..ddf72a352e 100644
--- a/esp32p4/src/i2s0/int_st.rs
+++ b/esp32p4/src/i2s0/int_st.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/i2s0/lc_hung_conf.rs b/esp32p4/src/i2s0/lc_hung_conf.rs
index 060b1cdb60..71f0c84fa7 100644
--- a/esp32p4/src/i2s0/lc_hung_conf.rs
+++ b/esp32p4/src/i2s0/lc_hung_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_HUNG_CONF")
-            .field(
-                "lc_fifo_timeout",
-                &format_args!("{}", self.lc_fifo_timeout().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_shift",
-                &format_args!("{}", self.lc_fifo_timeout_shift().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_ena",
-                &format_args!("{}", self.lc_fifo_timeout_ena().bit()),
-            )
+            .field("lc_fifo_timeout", &self.lc_fifo_timeout())
+            .field("lc_fifo_timeout_shift", &self.lc_fifo_timeout_shift())
+            .field("lc_fifo_timeout_ena", &self.lc_fifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/rx_conf.rs b/esp32p4/src/i2s0/rx_conf.rs
index 5bb25c8d6b..243dbee06f 100644
--- a/esp32p4/src/i2s0/rx_conf.rs
+++ b/esp32p4/src/i2s0/rx_conf.rs
@@ -165,68 +165,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CONF")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field(
-                "rx_slave_mod",
-                &format_args!("{}", self.rx_slave_mod().bit()),
-            )
-            .field(
-                "rx_stop_mode",
-                &format_args!("{}", self.rx_stop_mode().bits()),
-            )
-            .field("rx_mono", &format_args!("{}", self.rx_mono().bit()))
-            .field(
-                "rx_big_endian",
-                &format_args!("{}", self.rx_big_endian().bit()),
-            )
-            .field("rx_update", &format_args!("{}", self.rx_update().bit()))
-            .field(
-                "rx_mono_fst_vld",
-                &format_args!("{}", self.rx_mono_fst_vld().bit()),
-            )
-            .field(
-                "rx_pcm_conf",
-                &format_args!("{}", self.rx_pcm_conf().bits()),
-            )
-            .field(
-                "rx_pcm_bypass",
-                &format_args!("{}", self.rx_pcm_bypass().bit()),
-            )
-            .field(
-                "rx_msb_shift",
-                &format_args!("{}", self.rx_msb_shift().bit()),
-            )
-            .field(
-                "rx_left_align",
-                &format_args!("{}", self.rx_left_align().bit()),
-            )
-            .field(
-                "rx_24_fill_en",
-                &format_args!("{}", self.rx_24_fill_en().bit()),
-            )
-            .field(
-                "rx_ws_idle_pol",
-                &format_args!("{}", self.rx_ws_idle_pol().bit()),
-            )
-            .field(
-                "rx_bit_order",
-                &format_args!("{}", self.rx_bit_order().bit()),
-            )
-            .field("rx_tdm_en", &format_args!("{}", self.rx_tdm_en().bit()))
-            .field("rx_pdm_en", &format_args!("{}", self.rx_pdm_en().bit()))
-            .field(
-                "rx_bck_div_num",
-                &format_args!("{}", self.rx_bck_div_num().bits()),
-            )
+            .field("rx_start", &self.rx_start())
+            .field("rx_slave_mod", &self.rx_slave_mod())
+            .field("rx_stop_mode", &self.rx_stop_mode())
+            .field("rx_mono", &self.rx_mono())
+            .field("rx_big_endian", &self.rx_big_endian())
+            .field("rx_update", &self.rx_update())
+            .field("rx_mono_fst_vld", &self.rx_mono_fst_vld())
+            .field("rx_pcm_conf", &self.rx_pcm_conf())
+            .field("rx_pcm_bypass", &self.rx_pcm_bypass())
+            .field("rx_msb_shift", &self.rx_msb_shift())
+            .field("rx_left_align", &self.rx_left_align())
+            .field("rx_24_fill_en", &self.rx_24_fill_en())
+            .field("rx_ws_idle_pol", &self.rx_ws_idle_pol())
+            .field("rx_bit_order", &self.rx_bit_order())
+            .field("rx_tdm_en", &self.rx_tdm_en())
+            .field("rx_pdm_en", &self.rx_pdm_en())
+            .field("rx_bck_div_num", &self.rx_bck_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset receiver"]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/rx_conf1.rs b/esp32p4/src/i2s0/rx_conf1.rs
index 898003bcab..a4e0fc2df4 100644
--- a/esp32p4/src/i2s0/rx_conf1.rs
+++ b/esp32p4/src/i2s0/rx_conf1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CONF1")
-            .field(
-                "rx_tdm_ws_width",
-                &format_args!("{}", self.rx_tdm_ws_width().bits()),
-            )
-            .field(
-                "rx_bits_mod",
-                &format_args!("{}", self.rx_bits_mod().bits()),
-            )
-            .field(
-                "rx_half_sample_bits",
-                &format_args!("{}", self.rx_half_sample_bits().bits()),
-            )
-            .field(
-                "rx_tdm_chan_bits",
-                &format_args!("{}", self.rx_tdm_chan_bits().bits()),
-            )
+            .field("rx_tdm_ws_width", &self.rx_tdm_ws_width())
+            .field("rx_bits_mod", &self.rx_bits_mod())
+            .field("rx_half_sample_bits", &self.rx_half_sample_bits())
+            .field("rx_tdm_chan_bits", &self.rx_tdm_chan_bits())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[8:0\\] +1) * T_bck"]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/rx_pdm2pcm_conf.rs b/esp32p4/src/i2s0/rx_pdm2pcm_conf.rs
index b1ab416f09..4452147712 100644
--- a/esp32p4/src/i2s0/rx_pdm2pcm_conf.rs
+++ b/esp32p4/src/i2s0/rx_pdm2pcm_conf.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_PDM2PCM_CONF")
-            .field(
-                "rx_pdm2pcm_en",
-                &format_args!("{}", self.rx_pdm2pcm_en().bit()),
-            )
-            .field(
-                "rx_pdm_sinc_dsr_16_en",
-                &format_args!("{}", self.rx_pdm_sinc_dsr_16_en().bit()),
-            )
-            .field(
-                "rx_pdm2pcm_amplify_num",
-                &format_args!("{}", self.rx_pdm2pcm_amplify_num().bits()),
-            )
-            .field(
-                "rx_pdm_hp_bypass",
-                &format_args!("{}", self.rx_pdm_hp_bypass().bit()),
-            )
-            .field(
-                "rx_iir_hp_mult12_5",
-                &format_args!("{}", self.rx_iir_hp_mult12_5().bits()),
-            )
-            .field(
-                "rx_iir_hp_mult12_0",
-                &format_args!("{}", self.rx_iir_hp_mult12_0().bits()),
-            )
+            .field("rx_pdm2pcm_en", &self.rx_pdm2pcm_en())
+            .field("rx_pdm_sinc_dsr_16_en", &self.rx_pdm_sinc_dsr_16_en())
+            .field("rx_pdm2pcm_amplify_num", &self.rx_pdm2pcm_amplify_num())
+            .field("rx_pdm_hp_bypass", &self.rx_pdm_hp_bypass())
+            .field("rx_iir_hp_mult12_5", &self.rx_iir_hp_mult12_5())
+            .field("rx_iir_hp_mult12_0", &self.rx_iir_hp_mult12_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_PDM2PCM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 19 - 1: Enable PDM2PCM RX mode. 0: DIsable."]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/rx_tdm_ctrl.rs b/esp32p4/src/i2s0/rx_tdm_ctrl.rs
index fe01f97aeb..0d18f522f2 100644
--- a/esp32p4/src/i2s0/rx_tdm_ctrl.rs
+++ b/esp32p4/src/i2s0/rx_tdm_ctrl.rs
@@ -161,83 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_TDM_CTRL")
-            .field(
-                "rx_tdm_pdm_chan0_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan0_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan1_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan1_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan2_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan2_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan3_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan3_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan4_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan4_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan5_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan5_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan6_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan6_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan7_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan7_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan8_en",
-                &format_args!("{}", self.rx_tdm_chan8_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan9_en",
-                &format_args!("{}", self.rx_tdm_chan9_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan10_en",
-                &format_args!("{}", self.rx_tdm_chan10_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan11_en",
-                &format_args!("{}", self.rx_tdm_chan11_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan12_en",
-                &format_args!("{}", self.rx_tdm_chan12_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan13_en",
-                &format_args!("{}", self.rx_tdm_chan13_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan14_en",
-                &format_args!("{}", self.rx_tdm_chan14_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan15_en",
-                &format_args!("{}", self.rx_tdm_chan15_en().bit()),
-            )
-            .field(
-                "rx_tdm_tot_chan_num",
-                &format_args!("{}", self.rx_tdm_tot_chan_num().bits()),
-            )
+            .field("rx_tdm_pdm_chan0_en", &self.rx_tdm_pdm_chan0_en())
+            .field("rx_tdm_pdm_chan1_en", &self.rx_tdm_pdm_chan1_en())
+            .field("rx_tdm_pdm_chan2_en", &self.rx_tdm_pdm_chan2_en())
+            .field("rx_tdm_pdm_chan3_en", &self.rx_tdm_pdm_chan3_en())
+            .field("rx_tdm_pdm_chan4_en", &self.rx_tdm_pdm_chan4_en())
+            .field("rx_tdm_pdm_chan5_en", &self.rx_tdm_pdm_chan5_en())
+            .field("rx_tdm_pdm_chan6_en", &self.rx_tdm_pdm_chan6_en())
+            .field("rx_tdm_pdm_chan7_en", &self.rx_tdm_pdm_chan7_en())
+            .field("rx_tdm_chan8_en", &self.rx_tdm_chan8_en())
+            .field("rx_tdm_chan9_en", &self.rx_tdm_chan9_en())
+            .field("rx_tdm_chan10_en", &self.rx_tdm_chan10_en())
+            .field("rx_tdm_chan11_en", &self.rx_tdm_chan11_en())
+            .field("rx_tdm_chan12_en", &self.rx_tdm_chan12_en())
+            .field("rx_tdm_chan13_en", &self.rx_tdm_chan13_en())
+            .field("rx_tdm_chan14_en", &self.rx_tdm_chan14_en())
+            .field("rx_tdm_chan15_en", &self.rx_tdm_chan15_en())
+            .field("rx_tdm_tot_chan_num", &self.rx_tdm_tot_chan_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_TDM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/rx_timing.rs b/esp32p4/src/i2s0/rx_timing.rs
index 872c8ee1b5..7ae3ab60d7 100644
--- a/esp32p4/src/i2s0/rx_timing.rs
+++ b/esp32p4/src/i2s0/rx_timing.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_TIMING")
-            .field(
-                "rx_sd_in_dm",
-                &format_args!("{}", self.rx_sd_in_dm().bits()),
-            )
-            .field(
-                "rx_sd1_in_dm",
-                &format_args!("{}", self.rx_sd1_in_dm().bits()),
-            )
-            .field(
-                "rx_sd2_in_dm",
-                &format_args!("{}", self.rx_sd2_in_dm().bits()),
-            )
-            .field(
-                "rx_sd3_in_dm",
-                &format_args!("{}", self.rx_sd3_in_dm().bits()),
-            )
-            .field(
-                "rx_ws_out_dm",
-                &format_args!("{}", self.rx_ws_out_dm().bits()),
-            )
-            .field(
-                "rx_bck_out_dm",
-                &format_args!("{}", self.rx_bck_out_dm().bits()),
-            )
-            .field(
-                "rx_ws_in_dm",
-                &format_args!("{}", self.rx_ws_in_dm().bits()),
-            )
-            .field(
-                "rx_bck_in_dm",
-                &format_args!("{}", self.rx_bck_in_dm().bits()),
-            )
+            .field("rx_sd_in_dm", &self.rx_sd_in_dm())
+            .field("rx_sd1_in_dm", &self.rx_sd1_in_dm())
+            .field("rx_sd2_in_dm", &self.rx_sd2_in_dm())
+            .field("rx_sd3_in_dm", &self.rx_sd3_in_dm())
+            .field("rx_ws_out_dm", &self.rx_ws_out_dm())
+            .field("rx_bck_out_dm", &self.rx_bck_out_dm())
+            .field("rx_ws_in_dm", &self.rx_ws_in_dm())
+            .field("rx_bck_in_dm", &self.rx_bck_in_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/rxeof_num.rs b/esp32p4/src/i2s0/rxeof_num.rs
index 06f6d22ff0..b9674d5891 100644
--- a/esp32p4/src/i2s0/rxeof_num.rs
+++ b/esp32p4/src/i2s0/rxeof_num.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXEOF_NUM")
-            .field("rx_eof_num", &format_args!("{}", self.rx_eof_num().bits()))
+            .field("rx_eof_num", &self.rx_eof_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXEOF_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/state.rs b/esp32p4/src/i2s0/state.rs
index 7988d4067c..d16247a40d 100644
--- a/esp32p4/src/i2s0/state.rs
+++ b/esp32p4/src/i2s0/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("tx_idle", &format_args!("{}", self.tx_idle().bit()))
+            .field("tx_idle", &self.tx_idle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S TX status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32p4/src/i2s0/tx_conf.rs b/esp32p4/src/i2s0/tx_conf.rs
index f8247c5f9c..84ddc2d9bf 100644
--- a/esp32p4/src/i2s0/tx_conf.rs
+++ b/esp32p4/src/i2s0/tx_conf.rs
@@ -201,81 +201,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CONF")
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field(
-                "tx_slave_mod",
-                &format_args!("{}", self.tx_slave_mod().bit()),
-            )
-            .field("tx_stop_en", &format_args!("{}", self.tx_stop_en().bit()))
-            .field(
-                "tx_chan_equal",
-                &format_args!("{}", self.tx_chan_equal().bit()),
-            )
-            .field("tx_mono", &format_args!("{}", self.tx_mono().bit()))
-            .field(
-                "tx_big_endian",
-                &format_args!("{}", self.tx_big_endian().bit()),
-            )
-            .field("tx_update", &format_args!("{}", self.tx_update().bit()))
-            .field(
-                "tx_mono_fst_vld",
-                &format_args!("{}", self.tx_mono_fst_vld().bit()),
-            )
-            .field(
-                "tx_pcm_conf",
-                &format_args!("{}", self.tx_pcm_conf().bits()),
-            )
-            .field(
-                "tx_pcm_bypass",
-                &format_args!("{}", self.tx_pcm_bypass().bit()),
-            )
-            .field(
-                "tx_msb_shift",
-                &format_args!("{}", self.tx_msb_shift().bit()),
-            )
-            .field(
-                "tx_bck_no_dly",
-                &format_args!("{}", self.tx_bck_no_dly().bit()),
-            )
-            .field(
-                "tx_left_align",
-                &format_args!("{}", self.tx_left_align().bit()),
-            )
-            .field(
-                "tx_24_fill_en",
-                &format_args!("{}", self.tx_24_fill_en().bit()),
-            )
-            .field(
-                "tx_ws_idle_pol",
-                &format_args!("{}", self.tx_ws_idle_pol().bit()),
-            )
-            .field(
-                "tx_bit_order",
-                &format_args!("{}", self.tx_bit_order().bit()),
-            )
-            .field("tx_tdm_en", &format_args!("{}", self.tx_tdm_en().bit()))
-            .field("tx_pdm_en", &format_args!("{}", self.tx_pdm_en().bit()))
-            .field(
-                "tx_bck_div_num",
-                &format_args!("{}", self.tx_bck_div_num().bits()),
-            )
-            .field(
-                "tx_chan_mod",
-                &format_args!("{}", self.tx_chan_mod().bits()),
-            )
-            .field(
-                "sig_loopback",
-                &format_args!("{}", self.sig_loopback().bit()),
-            )
+            .field("tx_start", &self.tx_start())
+            .field("tx_slave_mod", &self.tx_slave_mod())
+            .field("tx_stop_en", &self.tx_stop_en())
+            .field("tx_chan_equal", &self.tx_chan_equal())
+            .field("tx_mono", &self.tx_mono())
+            .field("tx_big_endian", &self.tx_big_endian())
+            .field("tx_update", &self.tx_update())
+            .field("tx_mono_fst_vld", &self.tx_mono_fst_vld())
+            .field("tx_pcm_conf", &self.tx_pcm_conf())
+            .field("tx_pcm_bypass", &self.tx_pcm_bypass())
+            .field("tx_msb_shift", &self.tx_msb_shift())
+            .field("tx_bck_no_dly", &self.tx_bck_no_dly())
+            .field("tx_left_align", &self.tx_left_align())
+            .field("tx_24_fill_en", &self.tx_24_fill_en())
+            .field("tx_ws_idle_pol", &self.tx_ws_idle_pol())
+            .field("tx_bit_order", &self.tx_bit_order())
+            .field("tx_tdm_en", &self.tx_tdm_en())
+            .field("tx_pdm_en", &self.tx_pdm_en())
+            .field("tx_bck_div_num", &self.tx_bck_div_num())
+            .field("tx_chan_mod", &self.tx_chan_mod())
+            .field("sig_loopback", &self.sig_loopback())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset transmitter"]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/tx_conf1.rs b/esp32p4/src/i2s0/tx_conf1.rs
index 6a076d5334..580fa1b86c 100644
--- a/esp32p4/src/i2s0/tx_conf1.rs
+++ b/esp32p4/src/i2s0/tx_conf1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CONF1")
-            .field(
-                "tx_tdm_ws_width",
-                &format_args!("{}", self.tx_tdm_ws_width().bits()),
-            )
-            .field(
-                "tx_bits_mod",
-                &format_args!("{}", self.tx_bits_mod().bits()),
-            )
-            .field(
-                "tx_half_sample_bits",
-                &format_args!("{}", self.tx_half_sample_bits().bits()),
-            )
-            .field(
-                "tx_tdm_chan_bits",
-                &format_args!("{}", self.tx_tdm_chan_bits().bits()),
-            )
+            .field("tx_tdm_ws_width", &self.tx_tdm_ws_width())
+            .field("tx_bits_mod", &self.tx_bits_mod())
+            .field("tx_half_sample_bits", &self.tx_half_sample_bits())
+            .field("tx_tdm_chan_bits", &self.tx_tdm_chan_bits())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[8:0\\] +1) * T_bck"]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/tx_pcm2pdm_conf.rs b/esp32p4/src/i2s0/tx_pcm2pdm_conf.rs
index f361f43fa5..833a737465 100644
--- a/esp32p4/src/i2s0/tx_pcm2pdm_conf.rs
+++ b/esp32p4/src/i2s0/tx_pcm2pdm_conf.rs
@@ -116,63 +116,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_PCM2PDM_CONF")
-            .field(
-                "tx_pdm_hp_bypass",
-                &format_args!("{}", self.tx_pdm_hp_bypass().bit()),
-            )
-            .field(
-                "tx_pdm_sinc_osr2",
-                &format_args!("{}", self.tx_pdm_sinc_osr2().bits()),
-            )
-            .field(
-                "tx_pdm_prescale",
-                &format_args!("{}", self.tx_pdm_prescale().bits()),
-            )
-            .field(
-                "tx_pdm_hp_in_shift",
-                &format_args!("{}", self.tx_pdm_hp_in_shift().bits()),
-            )
-            .field(
-                "tx_pdm_lp_in_shift",
-                &format_args!("{}", self.tx_pdm_lp_in_shift().bits()),
-            )
-            .field(
-                "tx_pdm_sinc_in_shift",
-                &format_args!("{}", self.tx_pdm_sinc_in_shift().bits()),
-            )
+            .field("tx_pdm_hp_bypass", &self.tx_pdm_hp_bypass())
+            .field("tx_pdm_sinc_osr2", &self.tx_pdm_sinc_osr2())
+            .field("tx_pdm_prescale", &self.tx_pdm_prescale())
+            .field("tx_pdm_hp_in_shift", &self.tx_pdm_hp_in_shift())
+            .field("tx_pdm_lp_in_shift", &self.tx_pdm_lp_in_shift())
+            .field("tx_pdm_sinc_in_shift", &self.tx_pdm_sinc_in_shift())
             .field(
                 "tx_pdm_sigmadelta_in_shift",
-                &format_args!("{}", self.tx_pdm_sigmadelta_in_shift().bits()),
+                &self.tx_pdm_sigmadelta_in_shift(),
             )
             .field(
                 "tx_pdm_sigmadelta_dither2",
-                &format_args!("{}", self.tx_pdm_sigmadelta_dither2().bit()),
-            )
-            .field(
-                "tx_pdm_sigmadelta_dither",
-                &format_args!("{}", self.tx_pdm_sigmadelta_dither().bit()),
-            )
-            .field(
-                "tx_pdm_dac_2out_en",
-                &format_args!("{}", self.tx_pdm_dac_2out_en().bit()),
-            )
-            .field(
-                "tx_pdm_dac_mode_en",
-                &format_args!("{}", self.tx_pdm_dac_mode_en().bit()),
-            )
-            .field(
-                "pcm2pdm_conv_en",
-                &format_args!("{}", self.pcm2pdm_conv_en().bit()),
+                &self.tx_pdm_sigmadelta_dither2(),
             )
+            .field("tx_pdm_sigmadelta_dither", &self.tx_pdm_sigmadelta_dither())
+            .field("tx_pdm_dac_2out_en", &self.tx_pdm_dac_2out_en())
+            .field("tx_pdm_dac_mode_en", &self.tx_pdm_dac_mode_en())
+            .field("pcm2pdm_conv_en", &self.pcm2pdm_conv_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_PCM2PDM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - I2S TX PDM bypass hp filter or not. The option has been removed."]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/tx_pcm2pdm_conf1.rs b/esp32p4/src/i2s0/tx_pcm2pdm_conf1.rs
index dfcd334df0..48c460dc25 100644
--- a/esp32p4/src/i2s0/tx_pcm2pdm_conf1.rs
+++ b/esp32p4/src/i2s0/tx_pcm2pdm_conf1.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_PCM2PDM_CONF1")
-            .field("tx_pdm_fp", &format_args!("{}", self.tx_pdm_fp().bits()))
-            .field("tx_pdm_fs", &format_args!("{}", self.tx_pdm_fs().bits()))
-            .field(
-                "tx_iir_hp_mult12_5",
-                &format_args!("{}", self.tx_iir_hp_mult12_5().bits()),
-            )
-            .field(
-                "tx_iir_hp_mult12_0",
-                &format_args!("{}", self.tx_iir_hp_mult12_0().bits()),
-            )
+            .field("tx_pdm_fp", &self.tx_pdm_fp())
+            .field("tx_pdm_fs", &self.tx_pdm_fs())
+            .field("tx_iir_hp_mult12_5", &self.tx_iir_hp_mult12_5())
+            .field("tx_iir_hp_mult12_0", &self.tx_iir_hp_mult12_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_PCM2PDM_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - I2S TX PDM Fp"]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/tx_tdm_ctrl.rs b/esp32p4/src/i2s0/tx_tdm_ctrl.rs
index a6511fa2f9..8b06e96c6c 100644
--- a/esp32p4/src/i2s0/tx_tdm_ctrl.rs
+++ b/esp32p4/src/i2s0/tx_tdm_ctrl.rs
@@ -170,87 +170,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_TDM_CTRL")
-            .field(
-                "tx_tdm_chan0_en",
-                &format_args!("{}", self.tx_tdm_chan0_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan1_en",
-                &format_args!("{}", self.tx_tdm_chan1_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan2_en",
-                &format_args!("{}", self.tx_tdm_chan2_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan3_en",
-                &format_args!("{}", self.tx_tdm_chan3_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan4_en",
-                &format_args!("{}", self.tx_tdm_chan4_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan5_en",
-                &format_args!("{}", self.tx_tdm_chan5_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan6_en",
-                &format_args!("{}", self.tx_tdm_chan6_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan7_en",
-                &format_args!("{}", self.tx_tdm_chan7_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan8_en",
-                &format_args!("{}", self.tx_tdm_chan8_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan9_en",
-                &format_args!("{}", self.tx_tdm_chan9_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan10_en",
-                &format_args!("{}", self.tx_tdm_chan10_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan11_en",
-                &format_args!("{}", self.tx_tdm_chan11_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan12_en",
-                &format_args!("{}", self.tx_tdm_chan12_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan13_en",
-                &format_args!("{}", self.tx_tdm_chan13_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan14_en",
-                &format_args!("{}", self.tx_tdm_chan14_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan15_en",
-                &format_args!("{}", self.tx_tdm_chan15_en().bit()),
-            )
-            .field(
-                "tx_tdm_tot_chan_num",
-                &format_args!("{}", self.tx_tdm_tot_chan_num().bits()),
-            )
-            .field(
-                "tx_tdm_skip_msk_en",
-                &format_args!("{}", self.tx_tdm_skip_msk_en().bit()),
-            )
+            .field("tx_tdm_chan0_en", &self.tx_tdm_chan0_en())
+            .field("tx_tdm_chan1_en", &self.tx_tdm_chan1_en())
+            .field("tx_tdm_chan2_en", &self.tx_tdm_chan2_en())
+            .field("tx_tdm_chan3_en", &self.tx_tdm_chan3_en())
+            .field("tx_tdm_chan4_en", &self.tx_tdm_chan4_en())
+            .field("tx_tdm_chan5_en", &self.tx_tdm_chan5_en())
+            .field("tx_tdm_chan6_en", &self.tx_tdm_chan6_en())
+            .field("tx_tdm_chan7_en", &self.tx_tdm_chan7_en())
+            .field("tx_tdm_chan8_en", &self.tx_tdm_chan8_en())
+            .field("tx_tdm_chan9_en", &self.tx_tdm_chan9_en())
+            .field("tx_tdm_chan10_en", &self.tx_tdm_chan10_en())
+            .field("tx_tdm_chan11_en", &self.tx_tdm_chan11_en())
+            .field("tx_tdm_chan12_en", &self.tx_tdm_chan12_en())
+            .field("tx_tdm_chan13_en", &self.tx_tdm_chan13_en())
+            .field("tx_tdm_chan14_en", &self.tx_tdm_chan14_en())
+            .field("tx_tdm_chan15_en", &self.tx_tdm_chan15_en())
+            .field("tx_tdm_tot_chan_num", &self.tx_tdm_tot_chan_num())
+            .field("tx_tdm_skip_msk_en", &self.tx_tdm_skip_msk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_TDM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
diff --git a/esp32p4/src/i2s0/tx_timing.rs b/esp32p4/src/i2s0/tx_timing.rs
index 90d44db432..550930d1b6 100644
--- a/esp32p4/src/i2s0/tx_timing.rs
+++ b/esp32p4/src/i2s0/tx_timing.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_TIMING")
-            .field(
-                "tx_sd_out_dm",
-                &format_args!("{}", self.tx_sd_out_dm().bits()),
-            )
-            .field(
-                "tx_sd1_out_dm",
-                &format_args!("{}", self.tx_sd1_out_dm().bits()),
-            )
-            .field(
-                "tx_ws_out_dm",
-                &format_args!("{}", self.tx_ws_out_dm().bits()),
-            )
-            .field(
-                "tx_bck_out_dm",
-                &format_args!("{}", self.tx_bck_out_dm().bits()),
-            )
-            .field(
-                "tx_ws_in_dm",
-                &format_args!("{}", self.tx_ws_in_dm().bits()),
-            )
-            .field(
-                "tx_bck_in_dm",
-                &format_args!("{}", self.tx_bck_in_dm().bits()),
-            )
+            .field("tx_sd_out_dm", &self.tx_sd_out_dm())
+            .field("tx_sd1_out_dm", &self.tx_sd1_out_dm())
+            .field("tx_ws_out_dm", &self.tx_ws_out_dm())
+            .field("tx_bck_out_dm", &self.tx_bck_out_dm())
+            .field("tx_ws_in_dm", &self.tx_ws_in_dm())
+            .field("tx_bck_in_dm", &self.tx_bck_in_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/buffer_status_level.rs b/esp32p4/src/i3c_mst/buffer_status_level.rs
index 03cc00b5f2..dd408b516c 100644
--- a/esp32p4/src/i3c_mst/buffer_status_level.rs
+++ b/esp32p4/src/i3c_mst/buffer_status_level.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUFFER_STATUS_LEVEL")
-            .field(
-                "cmd_buf_empty_cnt",
-                &format_args!("{}", self.cmd_buf_empty_cnt().bits()),
-            )
-            .field(
-                "resp_buf_cnt",
-                &format_args!("{}", self.resp_buf_cnt().bits()),
-            )
-            .field(
-                "ibi_data_buf_cnt",
-                &format_args!("{}", self.ibi_data_buf_cnt().bits()),
-            )
-            .field(
-                "ibi_status_buf_cnt",
-                &format_args!("{}", self.ibi_status_buf_cnt().bits()),
-            )
+            .field("cmd_buf_empty_cnt", &self.cmd_buf_empty_cnt())
+            .field("resp_buf_cnt", &self.resp_buf_cnt())
+            .field("ibi_data_buf_cnt", &self.ibi_data_buf_cnt())
+            .field("ibi_status_buf_cnt", &self.ibi_status_buf_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUFFER_STATUS_LEVEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buffer_status_level::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUFFER_STATUS_LEVEL_SPEC;
 impl crate::RegisterSpec for BUFFER_STATUS_LEVEL_SPEC {
diff --git a/esp32p4/src/i3c_mst/buffer_thld_ctrl.rs b/esp32p4/src/i3c_mst/buffer_thld_ctrl.rs
index 3a3a385cb2..09c9137aee 100644
--- a/esp32p4/src/i3c_mst/buffer_thld_ctrl.rs
+++ b/esp32p4/src/i3c_mst/buffer_thld_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUFFER_THLD_CTRL")
-            .field(
-                "reg_cmd_buf_empty_thld",
-                &format_args!("{}", self.reg_cmd_buf_empty_thld().bits()),
-            )
-            .field(
-                "reg_resp_buf_thld",
-                &format_args!("{}", self.reg_resp_buf_thld().bits()),
-            )
-            .field(
-                "reg_ibi_data_buf_thld",
-                &format_args!("{}", self.reg_ibi_data_buf_thld().bits()),
-            )
-            .field(
-                "reg_ibi_status_buf_thld",
-                &format_args!("{}", self.reg_ibi_status_buf_thld().bits()),
-            )
+            .field("reg_cmd_buf_empty_thld", &self.reg_cmd_buf_empty_thld())
+            .field("reg_resp_buf_thld", &self.reg_resp_buf_thld())
+            .field("reg_ibi_data_buf_thld", &self.reg_ibi_data_buf_thld())
+            .field("reg_ibi_status_buf_thld", &self.reg_ibi_status_buf_thld())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUFFER_THLD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Command Buffer Empty Threshold Value is used to control the number of empty locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/bus_free_time.rs b/esp32p4/src/i3c_mst/bus_free_time.rs
index bbd88eb2d4..6ef6bb38a1 100644
--- a/esp32p4/src/i3c_mst/bus_free_time.rs
+++ b/esp32p4/src/i3c_mst/bus_free_time.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_FREE_TIME")
-            .field(
-                "reg_bus_free_time",
-                &format_args!("{}", self.reg_bus_free_time().bits()),
-            )
+            .field("reg_bus_free_time", &self.reg_bus_free_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_FREE_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing."]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/data_buffer_status_level.rs b/esp32p4/src/i3c_mst/data_buffer_status_level.rs
index 0ec2262a7a..eb86d0c669 100644
--- a/esp32p4/src/i3c_mst/data_buffer_status_level.rs
+++ b/esp32p4/src/i3c_mst/data_buffer_status_level.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_BUFFER_STATUS_LEVEL")
-            .field(
-                "tx_data_buf_empty_cnt",
-                &format_args!("{}", self.tx_data_buf_empty_cnt().bits()),
-            )
-            .field(
-                "rx_data_buf_cnt",
-                &format_args!("{}", self.rx_data_buf_cnt().bits()),
-            )
+            .field("tx_data_buf_empty_cnt", &self.tx_data_buf_empty_cnt())
+            .field("rx_data_buf_cnt", &self.rx_data_buf_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_BUFFER_STATUS_LEVEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_buffer_status_level::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DATA_BUFFER_STATUS_LEVEL_SPEC;
 impl crate::RegisterSpec for DATA_BUFFER_STATUS_LEVEL_SPEC {
diff --git a/esp32p4/src/i3c_mst/data_buffer_thld_ctrl.rs b/esp32p4/src/i3c_mst/data_buffer_thld_ctrl.rs
index 37203a91e2..d9d2b520f7 100644
--- a/esp32p4/src/i3c_mst/data_buffer_thld_ctrl.rs
+++ b/esp32p4/src/i3c_mst/data_buffer_thld_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_BUFFER_THLD_CTRL")
-            .field(
-                "reg_tx_data_buf_thld",
-                &format_args!("{}", self.reg_tx_data_buf_thld().bits()),
-            )
-            .field(
-                "reg_rx_data_buf_thld",
-                &format_args!("{}", self.reg_rx_data_buf_thld().bits()),
-            )
+            .field("reg_tx_data_buf_thld", &self.reg_tx_data_buf_thld())
+            .field("reg_rx_data_buf_thld", &self.reg_rx_data_buf_thld())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_BUFFER_THLD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Transmit Buffer Threshold Value. This field controls the number of empty locations in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values: 000:2 001:4 010:8 011:16 100:31, else:31"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/device_ctrl.rs b/esp32p4/src/i3c_mst/device_ctrl.rs
index cfefa8dbc6..be2e986e18 100644
--- a/esp32p4/src/i3c_mst/device_ctrl.rs
+++ b/esp32p4/src/i3c_mst/device_ctrl.rs
@@ -161,80 +161,35 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEVICE_CTRL")
-            .field(
-                "reg_ba_include",
-                &format_args!("{}", self.reg_ba_include().bit()),
-            )
-            .field(
-                "reg_trans_start",
-                &format_args!("{}", self.reg_trans_start().bit()),
-            )
-            .field("reg_clk_en", &format_args!("{}", self.reg_clk_en().bit()))
-            .field(
-                "reg_ibi_rstart_trans_en",
-                &format_args!("{}", self.reg_ibi_rstart_trans_en().bit()),
-            )
-            .field(
-                "reg_auto_dis_ibi_en",
-                &format_args!("{}", self.reg_auto_dis_ibi_en().bit()),
-            )
-            .field(
-                "reg_dma_rx_en",
-                &format_args!("{}", self.reg_dma_rx_en().bit()),
-            )
-            .field(
-                "reg_dma_tx_en",
-                &format_args!("{}", self.reg_dma_tx_en().bit()),
-            )
+            .field("reg_ba_include", &self.reg_ba_include())
+            .field("reg_trans_start", &self.reg_trans_start())
+            .field("reg_clk_en", &self.reg_clk_en())
+            .field("reg_ibi_rstart_trans_en", &self.reg_ibi_rstart_trans_en())
+            .field("reg_auto_dis_ibi_en", &self.reg_auto_dis_ibi_en())
+            .field("reg_dma_rx_en", &self.reg_dma_rx_en())
+            .field("reg_dma_tx_en", &self.reg_dma_tx_en())
             .field(
                 "reg_multi_slv_single_ccc_en",
-                &format_args!("{}", self.reg_multi_slv_single_ccc_en().bit()),
-            )
-            .field(
-                "reg_rx_bit_order",
-                &format_args!("{}", self.reg_rx_bit_order().bit()),
-            )
-            .field(
-                "reg_rx_byte_order",
-                &format_args!("{}", self.reg_rx_byte_order().bit()),
-            )
-            .field(
-                "reg_scl_pullup_force_en",
-                &format_args!("{}", self.reg_scl_pullup_force_en().bit()),
-            )
-            .field(
-                "reg_scl_oe_force_en",
-                &format_args!("{}", self.reg_scl_oe_force_en().bit()),
-            )
-            .field(
-                "reg_sda_pp_rd_pullup_en",
-                &format_args!("{}", self.reg_sda_pp_rd_pullup_en().bit()),
+                &self.reg_multi_slv_single_ccc_en(),
             )
+            .field("reg_rx_bit_order", &self.reg_rx_bit_order())
+            .field("reg_rx_byte_order", &self.reg_rx_byte_order())
+            .field("reg_scl_pullup_force_en", &self.reg_scl_pullup_force_en())
+            .field("reg_scl_oe_force_en", &self.reg_scl_oe_force_en())
+            .field("reg_sda_pp_rd_pullup_en", &self.reg_sda_pp_rd_pullup_en())
             .field(
                 "reg_sda_rd_tbit_hlvl_pullup_en",
-                &format_args!("{}", self.reg_sda_rd_tbit_hlvl_pullup_en().bit()),
-            )
-            .field(
-                "reg_sda_pp_wr_pullup_en",
-                &format_args!("{}", self.reg_sda_pp_wr_pullup_en().bit()),
+                &self.reg_sda_rd_tbit_hlvl_pullup_en(),
             )
+            .field("reg_sda_pp_wr_pullup_en", &self.reg_sda_pp_wr_pullup_en())
             .field(
                 "reg_data_byte_cnt_unlatch",
-                &format_args!("{}", self.reg_data_byte_cnt_unlatch().bit()),
-            )
-            .field(
-                "reg_mem_clk_force_on",
-                &format_args!("{}", self.reg_mem_clk_force_on().bit()),
+                &self.reg_data_byte_cnt_unlatch(),
             )
+            .field("reg_mem_clk_force_on", &self.reg_mem_clk_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEVICE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - This bit is used to include I3C broadcast address(0x7E) for private transfer.(If I3C broadcast address is not include for the private transfer, In-Band Interrupts driven from Slaves may not win address arbitration. Hence IBIs will get delayed)"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/device_table.rs b/esp32p4/src/i3c_mst/device_table.rs
index d98d23d13e..cea0260086 100644
--- a/esp32p4/src/i3c_mst/device_table.rs
+++ b/esp32p4/src/i3c_mst/device_table.rs
@@ -40,31 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEVICE_TABLE")
-            .field(
-                "reg_dct_daa_init_index",
-                &format_args!("{}", self.reg_dct_daa_init_index().bits()),
-            )
-            .field(
-                "reg_dat_daa_init_index",
-                &format_args!("{}", self.reg_dat_daa_init_index().bits()),
-            )
-            .field(
-                "present_dct_index",
-                &format_args!("{}", self.present_dct_index().bits()),
-            )
-            .field(
-                "present_dat_index",
-                &format_args!("{}", self.present_dat_index().bits()),
-            )
+            .field("reg_dct_daa_init_index", &self.reg_dct_daa_init_index())
+            .field("reg_dat_daa_init_index", &self.reg_dat_daa_init_index())
+            .field("present_dct_index", &self.present_dct_index())
+            .field("present_dat_index", &self.present_dat_index())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEVICE_TABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/fpga_debug_probe.rs b/esp32p4/src/i3c_mst/fpga_debug_probe.rs
index 662bedcd93..52fb0f73e3 100644
--- a/esp32p4/src/i3c_mst/fpga_debug_probe.rs
+++ b/esp32p4/src/i3c_mst/fpga_debug_probe.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("FPGA_DEBUG_PROBE")
             .field(
                 "reg_i3c_mst_fpga_debug_probe",
-                &format_args!("{}", self.reg_i3c_mst_fpga_debug_probe().bits()),
+                &self.reg_i3c_mst_fpga_debug_probe(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FPGA_DEBUG_PROBE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - For Debug Probe Test on FPGA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/ibi_notify_ctrl.rs b/esp32p4/src/i3c_mst/ibi_notify_ctrl.rs
index eb5f81dc46..9638400f3c 100644
--- a/esp32p4/src/i3c_mst/ibi_notify_ctrl.rs
+++ b/esp32p4/src/i3c_mst/ibi_notify_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBI_NOTIFY_CTRL")
-            .field(
-                "reg_notify_sir_rejected",
-                &format_args!("{}", self.reg_notify_sir_rejected().bit()),
-            )
+            .field("reg_notify_sir_rejected", &self.reg_notify_sir_rejected())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBI_NOTIFY_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - Notify Rejected Slave Interrupt Request Control. This bit is used to suppress reporting to the application about Slave Interrupt Request. 0:Suppress passing the IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT registerl."]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/ibi_sir_req_payload.rs b/esp32p4/src/i3c_mst/ibi_sir_req_payload.rs
index 5ac284c078..3cc8008118 100644
--- a/esp32p4/src/i3c_mst/ibi_sir_req_payload.rs
+++ b/esp32p4/src/i3c_mst/ibi_sir_req_payload.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBI_SIR_REQ_PAYLOAD")
-            .field(
-                "reg_sir_req_payload",
-                &format_args!("{}", self.reg_sir_req_payload().bits()),
-            )
+            .field("reg_sir_req_payload", &self.reg_sir_req_payload())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBI_SIR_REQ_PAYLOAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/ibi_sir_req_reject.rs b/esp32p4/src/i3c_mst/ibi_sir_req_reject.rs
index 54f433f1bc..7d48b33341 100644
--- a/esp32p4/src/i3c_mst/ibi_sir_req_reject.rs
+++ b/esp32p4/src/i3c_mst/ibi_sir_req_reject.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBI_SIR_REQ_REJECT")
-            .field(
-                "reg_sir_req_reject",
-                &format_args!("{}", self.reg_sir_req_reject().bits()),
-            )
+            .field("reg_sir_req_reject", &self.reg_sir_req_reject())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBI_SIR_REQ_REJECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The application of controller can decide whether to send ACK or NACK for Slave request received from any I3C device. A device specific response control bit is provided to select the response option, Master will ACK/NACK the Master Request based on programming of control bit, corresponding to the interrupting device. 0:ACK the SIR Request 1:NACK and send direct auto disable CCC"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/int_ena.rs b/esp32p4/src/i3c_mst/int_ena.rs
index 245d59f9e2..51e3581d3d 100644
--- a/esp32p4/src/i3c_mst/int_ena.rs
+++ b/esp32p4/src/i3c_mst/int_ena.rs
@@ -152,73 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "tx_data_buf_thld",
-                &format_args!("{}", self.tx_data_buf_thld().bit()),
-            )
-            .field(
-                "rx_data_buf_thld",
-                &format_args!("{}", self.rx_data_buf_thld().bit()),
-            )
-            .field(
-                "ibi_status_thld",
-                &format_args!("{}", self.ibi_status_thld().bit()),
-            )
-            .field(
-                "cmd_buf_empty_thld",
-                &format_args!("{}", self.cmd_buf_empty_thld().bit()),
-            )
-            .field("resp_ready", &format_args!("{}", self.resp_ready().bit()))
-            .field(
-                "nxt_cmd_req_err",
-                &format_args!("{}", self.nxt_cmd_req_err().bit()),
-            )
-            .field(
-                "transfer_err",
-                &format_args!("{}", self.transfer_err().bit()),
-            )
-            .field(
-                "transfer_complete",
-                &format_args!("{}", self.transfer_complete().bit()),
-            )
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
-            .field(
-                "detect_start",
-                &format_args!("{}", self.detect_start().bit()),
-            )
-            .field(
-                "resp_buf_ovf",
-                &format_args!("{}", self.resp_buf_ovf().bit()),
-            )
-            .field(
-                "ibi_data_buf_ovf",
-                &format_args!("{}", self.ibi_data_buf_ovf().bit()),
-            )
-            .field(
-                "ibi_status_buf_ovf",
-                &format_args!("{}", self.ibi_status_buf_ovf().bit()),
-            )
-            .field(
-                "ibi_handle_done",
-                &format_args!("{}", self.ibi_handle_done().bit()),
-            )
-            .field("ibi_detect", &format_args!("{}", self.ibi_detect().bit()))
-            .field(
-                "cmd_ccc_mismatch",
-                &format_args!("{}", self.cmd_ccc_mismatch().bit()),
-            )
+            .field("tx_data_buf_thld", &self.tx_data_buf_thld())
+            .field("rx_data_buf_thld", &self.rx_data_buf_thld())
+            .field("ibi_status_thld", &self.ibi_status_thld())
+            .field("cmd_buf_empty_thld", &self.cmd_buf_empty_thld())
+            .field("resp_ready", &self.resp_ready())
+            .field("nxt_cmd_req_err", &self.nxt_cmd_req_err())
+            .field("transfer_err", &self.transfer_err())
+            .field("transfer_complete", &self.transfer_complete())
+            .field("command_done", &self.command_done())
+            .field("detect_start", &self.detect_start())
+            .field("resp_buf_ovf", &self.resp_buf_ovf())
+            .field("ibi_data_buf_ovf", &self.ibi_data_buf_ovf())
+            .field("ibi_status_buf_ovf", &self.ibi_status_buf_ovf())
+            .field("ibi_handle_done", &self.ibi_handle_done())
+            .field("ibi_detect", &self.ibi_detect())
+            .field("cmd_ccc_mismatch", &self.cmd_ccc_mismatch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Transmit Buffer threshold status enable."]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/int_raw.rs b/esp32p4/src/i3c_mst/int_raw.rs
index 1454c1fe8d..8843492e99 100644
--- a/esp32p4/src/i3c_mst/int_raw.rs
+++ b/esp32p4/src/i3c_mst/int_raw.rs
@@ -152,73 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "tx_data_buf_thld",
-                &format_args!("{}", self.tx_data_buf_thld().bit()),
-            )
-            .field(
-                "rx_data_buf_thld",
-                &format_args!("{}", self.rx_data_buf_thld().bit()),
-            )
-            .field(
-                "ibi_status_thld",
-                &format_args!("{}", self.ibi_status_thld().bit()),
-            )
-            .field(
-                "cmd_buf_empty_thld",
-                &format_args!("{}", self.cmd_buf_empty_thld().bit()),
-            )
-            .field("resp_ready", &format_args!("{}", self.resp_ready().bit()))
-            .field(
-                "nxt_cmd_req_err",
-                &format_args!("{}", self.nxt_cmd_req_err().bit()),
-            )
-            .field(
-                "transfer_err",
-                &format_args!("{}", self.transfer_err().bit()),
-            )
-            .field(
-                "transfer_complete",
-                &format_args!("{}", self.transfer_complete().bit()),
-            )
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
-            .field(
-                "detect_start",
-                &format_args!("{}", self.detect_start().bit()),
-            )
-            .field(
-                "resp_buf_ovf",
-                &format_args!("{}", self.resp_buf_ovf().bit()),
-            )
-            .field(
-                "ibi_data_buf_ovf",
-                &format_args!("{}", self.ibi_data_buf_ovf().bit()),
-            )
-            .field(
-                "ibi_status_buf_ovf",
-                &format_args!("{}", self.ibi_status_buf_ovf().bit()),
-            )
-            .field(
-                "ibi_handle_done",
-                &format_args!("{}", self.ibi_handle_done().bit()),
-            )
-            .field("ibi_detect", &format_args!("{}", self.ibi_detect().bit()))
-            .field(
-                "cmd_ccc_mismatch",
-                &format_args!("{}", self.cmd_ccc_mismatch().bit()),
-            )
+            .field("tx_data_buf_thld", &self.tx_data_buf_thld())
+            .field("rx_data_buf_thld", &self.rx_data_buf_thld())
+            .field("ibi_status_thld", &self.ibi_status_thld())
+            .field("cmd_buf_empty_thld", &self.cmd_buf_empty_thld())
+            .field("resp_ready", &self.resp_ready())
+            .field("nxt_cmd_req_err", &self.nxt_cmd_req_err())
+            .field("transfer_err", &self.transfer_err())
+            .field("transfer_complete", &self.transfer_complete())
+            .field("command_done", &self.command_done())
+            .field("detect_start", &self.detect_start())
+            .field("resp_buf_ovf", &self.resp_buf_ovf())
+            .field("ibi_data_buf_ovf", &self.ibi_data_buf_ovf())
+            .field("ibi_status_buf_ovf", &self.ibi_status_buf_ovf())
+            .field("ibi_handle_done", &self.ibi_handle_done())
+            .field("ibi_detect", &self.ibi_detect())
+            .field("cmd_ccc_mismatch", &self.cmd_ccc_mismatch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/int_st.rs b/esp32p4/src/i3c_mst/int_st.rs
index 5def15f933..d5556eb5e0 100644
--- a/esp32p4/src/i3c_mst/int_st.rs
+++ b/esp32p4/src/i3c_mst/int_st.rs
@@ -118,73 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "tx_data_buf_thld",
-                &format_args!("{}", self.tx_data_buf_thld().bit()),
-            )
-            .field(
-                "rx_data_buf_thld",
-                &format_args!("{}", self.rx_data_buf_thld().bit()),
-            )
-            .field(
-                "ibi_status_thld",
-                &format_args!("{}", self.ibi_status_thld().bit()),
-            )
-            .field(
-                "cmd_buf_empty_thld",
-                &format_args!("{}", self.cmd_buf_empty_thld().bit()),
-            )
-            .field("resp_ready", &format_args!("{}", self.resp_ready().bit()))
-            .field(
-                "nxt_cmd_req_err",
-                &format_args!("{}", self.nxt_cmd_req_err().bit()),
-            )
-            .field(
-                "transfer_err",
-                &format_args!("{}", self.transfer_err().bit()),
-            )
-            .field(
-                "transfer_complete",
-                &format_args!("{}", self.transfer_complete().bit()),
-            )
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
-            .field(
-                "detect_start",
-                &format_args!("{}", self.detect_start().bit()),
-            )
-            .field(
-                "resp_buf_ovf",
-                &format_args!("{}", self.resp_buf_ovf().bit()),
-            )
-            .field(
-                "ibi_data_buf_ovf",
-                &format_args!("{}", self.ibi_data_buf_ovf().bit()),
-            )
-            .field(
-                "ibi_status_buf_ovf",
-                &format_args!("{}", self.ibi_status_buf_ovf().bit()),
-            )
-            .field(
-                "ibi_handle_done",
-                &format_args!("{}", self.ibi_handle_done().bit()),
-            )
-            .field("ibi_detect", &format_args!("{}", self.ibi_detect().bit()))
-            .field(
-                "cmd_ccc_mismatch",
-                &format_args!("{}", self.cmd_ccc_mismatch().bit()),
-            )
+            .field("tx_data_buf_thld", &self.tx_data_buf_thld())
+            .field("rx_data_buf_thld", &self.rx_data_buf_thld())
+            .field("ibi_status_thld", &self.ibi_status_thld())
+            .field("cmd_buf_empty_thld", &self.cmd_buf_empty_thld())
+            .field("resp_ready", &self.resp_ready())
+            .field("nxt_cmd_req_err", &self.nxt_cmd_req_err())
+            .field("transfer_err", &self.transfer_err())
+            .field("transfer_complete", &self.transfer_complete())
+            .field("command_done", &self.command_done())
+            .field("detect_start", &self.detect_start())
+            .field("resp_buf_ovf", &self.resp_buf_ovf())
+            .field("ibi_data_buf_ovf", &self.ibi_data_buf_ovf())
+            .field("ibi_status_buf_ovf", &self.ibi_status_buf_ovf())
+            .field("ibi_handle_done", &self.ibi_handle_done())
+            .field("ibi_detect", &self.ibi_detect())
+            .field("cmd_ccc_mismatch", &self.cmd_ccc_mismatch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/i3c_mst/present_state0.rs b/esp32p4/src/i3c_mst/present_state0.rs
index e2bbfaa76d..712d3f1843 100644
--- a/esp32p4/src/i3c_mst/present_state0.rs
+++ b/esp32p4/src/i3c_mst/present_state0.rs
@@ -83,44 +83,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRESENT_STATE0")
-            .field("sda_lvl", &format_args!("{}", self.sda_lvl().bit()))
-            .field("scl_lvl", &format_args!("{}", self.scl_lvl().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field("bus_free", &format_args!("{}", self.bus_free().bit()))
-            .field("cmd_tid", &format_args!("{}", self.cmd_tid().bits()))
-            .field(
-                "scl_gen_fsm_state",
-                &format_args!("{}", self.scl_gen_fsm_state().bits()),
-            )
-            .field(
-                "ibi_ev_handle_fsm_state",
-                &format_args!("{}", self.ibi_ev_handle_fsm_state().bits()),
-            )
-            .field(
-                "i2c_mode_fsm_state",
-                &format_args!("{}", self.i2c_mode_fsm_state().bits()),
-            )
-            .field(
-                "sdr_mode_fsm_state",
-                &format_args!("{}", self.sdr_mode_fsm_state().bits()),
-            )
-            .field(
-                "daa_mode_fsm_state",
-                &format_args!("{}", self.daa_mode_fsm_state().bits()),
-            )
-            .field(
-                "main_fsm_state",
-                &format_args!("{}", self.main_fsm_state().bits()),
-            )
+            .field("sda_lvl", &self.sda_lvl())
+            .field("scl_lvl", &self.scl_lvl())
+            .field("bus_busy", &self.bus_busy())
+            .field("bus_free", &self.bus_free())
+            .field("cmd_tid", &self.cmd_tid())
+            .field("scl_gen_fsm_state", &self.scl_gen_fsm_state())
+            .field("ibi_ev_handle_fsm_state", &self.ibi_ev_handle_fsm_state())
+            .field("i2c_mode_fsm_state", &self.i2c_mode_fsm_state())
+            .field("sdr_mode_fsm_state", &self.sdr_mode_fsm_state())
+            .field("daa_mode_fsm_state", &self.daa_mode_fsm_state())
+            .field("main_fsm_state", &self.main_fsm_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRESENT_STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`present_state0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRESENT_STATE0_SPEC;
 impl crate::RegisterSpec for PRESENT_STATE0_SPEC {
diff --git a/esp32p4/src/i3c_mst/present_state1.rs b/esp32p4/src/i3c_mst/present_state1.rs
index 3ac2f4f777..23301a677d 100644
--- a/esp32p4/src/i3c_mst/present_state1.rs
+++ b/esp32p4/src/i3c_mst/present_state1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRESENT_STATE1")
-            .field(
-                "data_byte_cnt",
-                &format_args!("{}", self.data_byte_cnt().bits()),
-            )
+            .field("data_byte_cnt", &self.data_byte_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRESENT_STATE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`present_state1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRESENT_STATE1_SPEC;
 impl crate::RegisterSpec for PRESENT_STATE1_SPEC {
diff --git a/esp32p4/src/i3c_mst/reset_ctrl.rs b/esp32p4/src/i3c_mst/reset_ctrl.rs
index 8532828d52..f93d8ba5b3 100644
--- a/esp32p4/src/i3c_mst/reset_ctrl.rs
+++ b/esp32p4/src/i3c_mst/reset_ctrl.rs
@@ -64,39 +64,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET_CTRL")
-            .field(
-                "reg_cmd_buf_rst",
-                &format_args!("{}", self.reg_cmd_buf_rst().bit()),
-            )
-            .field(
-                "reg_resp_buf_rst",
-                &format_args!("{}", self.reg_resp_buf_rst().bit()),
-            )
-            .field(
-                "reg_tx_data_buf_buf_rst",
-                &format_args!("{}", self.reg_tx_data_buf_buf_rst().bit()),
-            )
-            .field(
-                "reg_rx_data_buf_rst",
-                &format_args!("{}", self.reg_rx_data_buf_rst().bit()),
-            )
-            .field(
-                "reg_ibi_data_buf_rst",
-                &format_args!("{}", self.reg_ibi_data_buf_rst().bit()),
-            )
-            .field(
-                "reg_ibi_status_buf_rst",
-                &format_args!("{}", self.reg_ibi_status_buf_rst().bit()),
-            )
+            .field("reg_cmd_buf_rst", &self.reg_cmd_buf_rst())
+            .field("reg_resp_buf_rst", &self.reg_resp_buf_rst())
+            .field("reg_tx_data_buf_buf_rst", &self.reg_tx_data_buf_buf_rst())
+            .field("reg_rx_data_buf_rst", &self.reg_rx_data_buf_rst())
+            .field("reg_ibi_data_buf_rst", &self.reg_ibi_data_buf_rst())
+            .field("reg_ibi_status_buf_rst", &self.reg_ibi_status_buf_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/rnd_eco_cs.rs b/esp32p4/src/i3c_mst/rnd_eco_cs.rs
index 2f7b868047..3370ceacf2 100644
--- a/esp32p4/src/i3c_mst/rnd_eco_cs.rs
+++ b/esp32p4/src/i3c_mst/rnd_eco_cs.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_CS")
-            .field(
-                "reg_rnd_eco_en",
-                &format_args!("{}", self.reg_rnd_eco_en().bit()),
-            )
-            .field(
-                "rnd_eco_result",
-                &format_args!("{}", self.rnd_eco_result().bit()),
-            )
+            .field("reg_rnd_eco_en", &self.reg_rnd_eco_en())
+            .field("rnd_eco_result", &self.rnd_eco_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_CS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/rnd_eco_high.rs b/esp32p4/src/i3c_mst/rnd_eco_high.rs
index 14d6f3ddff..6c2afd7693 100644
--- a/esp32p4/src/i3c_mst/rnd_eco_high.rs
+++ b/esp32p4/src/i3c_mst/rnd_eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_HIGH")
-            .field(
-                "reg_rnd_eco_high",
-                &format_args!("{}", self.reg_rnd_eco_high().bits()),
-            )
+            .field("reg_rnd_eco_high", &self.reg_rnd_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/rnd_eco_low.rs b/esp32p4/src/i3c_mst/rnd_eco_low.rs
index d141831f5d..e902a1527d 100644
--- a/esp32p4/src/i3c_mst/rnd_eco_low.rs
+++ b/esp32p4/src/i3c_mst/rnd_eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_LOW")
-            .field(
-                "reg_rnd_eco_low",
-                &format_args!("{}", self.reg_rnd_eco_low().bits()),
-            )
+            .field("reg_rnd_eco_low", &self.reg_rnd_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/scl_ext_low_time.rs b/esp32p4/src/i3c_mst/scl_ext_low_time.rs
index 87f43ca265..faca3014df 100644
--- a/esp32p4/src/i3c_mst/scl_ext_low_time.rs
+++ b/esp32p4/src/i3c_mst/scl_ext_low_time.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("SCL_EXT_LOW_TIME")
             .field(
                 "reg_i3c_mst_ext_low_period1",
-                &format_args!("{}", self.reg_i3c_mst_ext_low_period1().bits()),
+                &self.reg_i3c_mst_ext_low_period1(),
             )
             .field(
                 "reg_i3c_mst_ext_low_period2",
-                &format_args!("{}", self.reg_i3c_mst_ext_low_period2().bits()),
+                &self.reg_i3c_mst_ext_low_period2(),
             )
             .field(
                 "reg_i3c_mst_ext_low_period3",
-                &format_args!("{}", self.reg_i3c_mst_ext_low_period3().bits()),
+                &self.reg_i3c_mst_ext_low_period3(),
             )
             .field(
                 "reg_i3c_mst_ext_low_period4",
-                &format_args!("{}", self.reg_i3c_mst_ext_low_period4().bits()),
+                &self.reg_i3c_mst_ext_low_period4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_EXT_LOW_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/scl_i2c_fm_time.rs b/esp32p4/src/i3c_mst/scl_i2c_fm_time.rs
index 4c4bbbf75f..577fd45ad4 100644
--- a/esp32p4/src/i3c_mst/scl_i2c_fm_time.rs
+++ b/esp32p4/src/i3c_mst/scl_i2c_fm_time.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_I2C_FM_TIME")
-            .field(
-                "reg_i2c_fm_low_period",
-                &format_args!("{}", self.reg_i2c_fm_low_period().bits()),
-            )
-            .field(
-                "reg_i2c_fm_high_period",
-                &format_args!("{}", self.reg_i2c_fm_high_period().bits()),
-            )
+            .field("reg_i2c_fm_low_period", &self.reg_i2c_fm_low_period())
+            .field("reg_i2c_fm_high_period", &self.reg_i2c_fm_high_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_I2C_FM_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/scl_i2c_fmp_time.rs b/esp32p4/src/i3c_mst/scl_i2c_fmp_time.rs
index f2e11084fc..e059d4696b 100644
--- a/esp32p4/src/i3c_mst/scl_i2c_fmp_time.rs
+++ b/esp32p4/src/i3c_mst/scl_i2c_fmp_time.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_I2C_FMP_TIME")
-            .field(
-                "reg_i2c_fmp_low_period",
-                &format_args!("{}", self.reg_i2c_fmp_low_period().bits()),
-            )
-            .field(
-                "reg_i2c_fmp_high_period",
-                &format_args!("{}", self.reg_i2c_fmp_high_period().bits()),
-            )
+            .field("reg_i2c_fmp_low_period", &self.reg_i2c_fmp_low_period())
+            .field("reg_i2c_fmp_high_period", &self.reg_i2c_fmp_high_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_I2C_FMP_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/scl_i3c_mst_od_time.rs b/esp32p4/src/i3c_mst/scl_i3c_mst_od_time.rs
index 095d4acf24..298b5cfacd 100644
--- a/esp32p4/src/i3c_mst/scl_i3c_mst_od_time.rs
+++ b/esp32p4/src/i3c_mst/scl_i3c_mst_od_time.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("SCL_I3C_MST_OD_TIME")
             .field(
                 "reg_i3c_mst_od_low_period",
-                &format_args!("{}", self.reg_i3c_mst_od_low_period().bits()),
+                &self.reg_i3c_mst_od_low_period(),
             )
             .field(
                 "reg_i3c_mst_od_high_period",
-                &format_args!("{}", self.reg_i3c_mst_od_high_period().bits()),
+                &self.reg_i3c_mst_od_high_period(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_I3C_MST_OD_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - SCL Open-Drain low count for I3C transfers targeted to I3C devices."]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/scl_i3c_mst_pp_time.rs b/esp32p4/src/i3c_mst/scl_i3c_mst_pp_time.rs
index 504268bfa1..d8010c8214 100644
--- a/esp32p4/src/i3c_mst/scl_i3c_mst_pp_time.rs
+++ b/esp32p4/src/i3c_mst/scl_i3c_mst_pp_time.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("SCL_I3C_MST_PP_TIME")
             .field(
                 "reg_i3c_mst_pp_low_period",
-                &format_args!("{}", self.reg_i3c_mst_pp_low_period().bits()),
+                &self.reg_i3c_mst_pp_low_period(),
             )
             .field(
                 "reg_i3c_mst_pp_high_period",
-                &format_args!("{}", self.reg_i3c_mst_pp_high_period().bits()),
+                &self.reg_i3c_mst_pp_high_period(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_I3C_MST_PP_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/scl_rstart_setup.rs b/esp32p4/src/i3c_mst/scl_rstart_setup.rs
index eab752c73c..d9003256c0 100644
--- a/esp32p4/src/i3c_mst/scl_rstart_setup.rs
+++ b/esp32p4/src/i3c_mst/scl_rstart_setup.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("SCL_RSTART_SETUP")
             .field(
                 "reg_scl_rstart_setup_time",
-                &format_args!("{}", self.reg_scl_rstart_setup_time().bits()),
+                &self.reg_scl_rstart_setup_time(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_RSTART_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - I2C_SCL_RSTART_SETUP_TIME"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/scl_start_hold.rs b/esp32p4/src/i3c_mst/scl_start_hold.rs
index 0f7e311b1f..76752ae08b 100644
--- a/esp32p4/src/i3c_mst/scl_start_hold.rs
+++ b/esp32p4/src/i3c_mst/scl_start_hold.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_HOLD")
-            .field(
-                "reg_scl_start_hold_time",
-                &format_args!("{}", self.reg_scl_start_hold_time().bits()),
-            )
-            .field(
-                "reg_start_det_hold_time",
-                &format_args!("{}", self.reg_start_det_hold_time().bits()),
-            )
+            .field("reg_scl_start_hold_time", &self.reg_scl_start_hold_time())
+            .field("reg_start_det_hold_time", &self.reg_start_det_hold_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - I2C_SCL_START_HOLD_TIME"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/scl_stop_hold.rs b/esp32p4/src/i3c_mst/scl_stop_hold.rs
index f1bbd5cbec..3b1d0fd594 100644
--- a/esp32p4/src/i3c_mst/scl_stop_hold.rs
+++ b/esp32p4/src/i3c_mst/scl_stop_hold.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_HOLD")
-            .field(
-                "reg_scl_stop_hold_time",
-                &format_args!("{}", self.reg_scl_stop_hold_time().bits()),
-            )
+            .field("reg_scl_stop_hold_time", &self.reg_scl_stop_hold_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - I2C_SCL_STOP_HOLD_TIME"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/scl_stop_setup.rs b/esp32p4/src/i3c_mst/scl_stop_setup.rs
index 8cfb1a43fc..6b809d510f 100644
--- a/esp32p4/src/i3c_mst/scl_stop_setup.rs
+++ b/esp32p4/src/i3c_mst/scl_stop_setup.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_SETUP")
-            .field(
-                "reg_scl_stop_setup_time",
-                &format_args!("{}", self.reg_scl_stop_setup_time().bits()),
-            )
+            .field("reg_scl_stop_setup_time", &self.reg_scl_stop_setup_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - I2C_SCL_STOP_SETUP_TIME"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/scl_termn_t_ext_low_time.rs b/esp32p4/src/i3c_mst/scl_termn_t_ext_low_time.rs
index 4908437f01..3f0a5811bb 100644
--- a/esp32p4/src/i3c_mst/scl_termn_t_ext_low_time.rs
+++ b/esp32p4/src/i3c_mst/scl_termn_t_ext_low_time.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("SCL_TERMN_T_EXT_LOW_TIME")
             .field(
                 "reg_i3c_mst_termn_t_ext_low_time",
-                &format_args!("{}", self.reg_i3c_mst_termn_t_ext_low_time().bits()),
+                &self.reg_i3c_mst_termn_t_ext_low_time(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_TERMN_T_EXT_LOW_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/sda_hold_time.rs b/esp32p4/src/i3c_mst/sda_hold_time.rs
index 4dc7f0af3f..48b1e754b7 100644
--- a/esp32p4/src/i3c_mst/sda_hold_time.rs
+++ b/esp32p4/src/i3c_mst/sda_hold_time.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_HOLD_TIME")
-            .field(
-                "reg_sda_od_tx_hold_time",
-                &format_args!("{}", self.reg_sda_od_tx_hold_time().bits()),
-            )
-            .field(
-                "reg_sda_pp_tx_hold_time",
-                &format_args!("{}", self.reg_sda_pp_tx_hold_time().bits()),
-            )
+            .field("reg_sda_od_tx_hold_time", &self.reg_sda_od_tx_hold_time())
+            .field("reg_sda_pp_tx_hold_time", &self.reg_sda_pp_tx_hold_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_HOLD_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - It is used to adjust sda drive point after scl neg under open drain speed"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/sda_sample_time.rs b/esp32p4/src/i3c_mst/sda_sample_time.rs
index 77e74706f3..80fb0ffdfb 100644
--- a/esp32p4/src/i3c_mst/sda_sample_time.rs
+++ b/esp32p4/src/i3c_mst/sda_sample_time.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_SAMPLE_TIME")
-            .field(
-                "reg_sda_od_sample_time",
-                &format_args!("{}", self.reg_sda_od_sample_time().bits()),
-            )
-            .field(
-                "reg_sda_pp_sample_time",
-                &format_args!("{}", self.reg_sda_pp_sample_time().bits()),
-            )
+            .field("reg_sda_od_sample_time", &self.reg_sda_od_sample_time())
+            .field("reg_sda_pp_sample_time", &self.reg_sda_pp_sample_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_SAMPLE_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - It is used to adjust sda sample point when scl high under open drain speed"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/time_out_value.rs b/esp32p4/src/i3c_mst/time_out_value.rs
index fac97f2842..7758e3eeb0 100644
--- a/esp32p4/src/i3c_mst/time_out_value.rs
+++ b/esp32p4/src/i3c_mst/time_out_value.rs
@@ -80,47 +80,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_OUT_VALUE")
-            .field(
-                "reg_resp_buf_to_value",
-                &format_args!("{}", self.reg_resp_buf_to_value().bits()),
-            )
-            .field(
-                "reg_resp_buf_to_en",
-                &format_args!("{}", self.reg_resp_buf_to_en().bit()),
-            )
+            .field("reg_resp_buf_to_value", &self.reg_resp_buf_to_value())
+            .field("reg_resp_buf_to_en", &self.reg_resp_buf_to_en())
             .field(
                 "reg_ibi_data_buf_to_value",
-                &format_args!("{}", self.reg_ibi_data_buf_to_value().bits()),
-            )
-            .field(
-                "reg_ibi_data_buf_to_en",
-                &format_args!("{}", self.reg_ibi_data_buf_to_en().bit()),
+                &self.reg_ibi_data_buf_to_value(),
             )
+            .field("reg_ibi_data_buf_to_en", &self.reg_ibi_data_buf_to_en())
             .field(
                 "reg_ibi_status_buf_to_value",
-                &format_args!("{}", self.reg_ibi_status_buf_to_value().bits()),
-            )
-            .field(
-                "reg_ibi_status_buf_to_en",
-                &format_args!("{}", self.reg_ibi_status_buf_to_en().bit()),
-            )
-            .field(
-                "reg_rx_data_buf_to_value",
-                &format_args!("{}", self.reg_rx_data_buf_to_value().bits()),
-            )
-            .field(
-                "reg_rx_data_buf_to_en",
-                &format_args!("{}", self.reg_rx_data_buf_to_en().bit()),
+                &self.reg_ibi_status_buf_to_value(),
             )
+            .field("reg_ibi_status_buf_to_en", &self.reg_ibi_status_buf_to_en())
+            .field("reg_rx_data_buf_to_value", &self.reg_rx_data_buf_to_value())
+            .field("reg_rx_data_buf_to_en", &self.reg_rx_data_buf_to_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_OUT_VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/ver_id.rs b/esp32p4/src/i3c_mst/ver_id.rs
index 29bbf9411e..bcc0dca140 100644
--- a/esp32p4/src/i3c_mst/ver_id.rs
+++ b/esp32p4/src/i3c_mst/ver_id.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VER_ID")
-            .field(
-                "reg_i3c_mst_ver_id",
-                &format_args!("{}", self.reg_i3c_mst_ver_id().bits()),
-            )
+            .field("reg_i3c_mst_ver_id", &self.reg_i3c_mst_ver_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VER_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This field indicates the controller current release number that is read by an application."]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst/ver_type.rs b/esp32p4/src/i3c_mst/ver_type.rs
index 28ed4b5527..cffa581aa5 100644
--- a/esp32p4/src/i3c_mst/ver_type.rs
+++ b/esp32p4/src/i3c_mst/ver_type.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VER_TYPE")
-            .field(
-                "reg_i3c_mst_ver_type",
-                &format_args!("{}", self.reg_i3c_mst_ver_type().bits()),
-            )
+            .field("reg_i3c_mst_ver_type", &self.reg_i3c_mst_ver_type())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VER_TYPE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This field indicates the controller current release type that is read by an application."]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst_mem/command_buf_port.rs b/esp32p4/src/i3c_mst_mem/command_buf_port.rs
index 5f4625c647..7a52f5f67f 100644
--- a/esp32p4/src/i3c_mst_mem/command_buf_port.rs
+++ b/esp32p4/src/i3c_mst_mem/command_buf_port.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMMAND_BUF_PORT")
-            .field(
-                "reg_command",
-                &format_args!("{}", self.reg_command().bits()),
-            )
+            .field("reg_command", &self.reg_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMMAND_BUF_PORT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Contains a Command Descriptor structure that depends on the requested transfer type. Command Descriptor structure is used to schedule the transfers to devices on I3C bus."]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table10_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table10_loc.rs
index e60bcc6e2b..edd91bb7f8 100644
--- a/esp32p4/src/i3c_mst_mem/dev_addr_table10_loc.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_addr_table10_loc.rs
@@ -46,29 +46,20 @@ impl core::fmt::Debug for R {
         f.debug_struct("DEV_ADDR_TABLE10_LOC")
             .field(
                 "reg_dat_dev10_static_addr",
-                &format_args!("{}", self.reg_dat_dev10_static_addr().bits()),
+                &self.reg_dat_dev10_static_addr(),
             )
             .field(
                 "reg_dat_dev10_dynamic_addr",
-                &format_args!("{}", self.reg_dat_dev10_dynamic_addr().bits()),
+                &self.reg_dat_dev10_dynamic_addr(),
             )
             .field(
                 "reg_dat_dev10_nack_retry_cnt",
-                &format_args!("{}", self.reg_dat_dev10_nack_retry_cnt().bits()),
-            )
-            .field(
-                "reg_dat_dev10_i2c",
-                &format_args!("{}", self.reg_dat_dev10_i2c().bit()),
+                &self.reg_dat_dev10_nack_retry_cnt(),
             )
+            .field("reg_dat_dev10_i2c", &self.reg_dat_dev10_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_ADDR_TABLE10_LOC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table11_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table11_loc.rs
index c33db8d3eb..940b7f68b6 100644
--- a/esp32p4/src/i3c_mst_mem/dev_addr_table11_loc.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_addr_table11_loc.rs
@@ -46,29 +46,20 @@ impl core::fmt::Debug for R {
         f.debug_struct("DEV_ADDR_TABLE11_LOC")
             .field(
                 "reg_dat_dev11_static_addr",
-                &format_args!("{}", self.reg_dat_dev11_static_addr().bits()),
+                &self.reg_dat_dev11_static_addr(),
             )
             .field(
                 "reg_dat_dev11_dynamic_addr",
-                &format_args!("{}", self.reg_dat_dev11_dynamic_addr().bits()),
+                &self.reg_dat_dev11_dynamic_addr(),
             )
             .field(
                 "reg_dat_dev11_nack_retry_cnt",
-                &format_args!("{}", self.reg_dat_dev11_nack_retry_cnt().bits()),
-            )
-            .field(
-                "reg_dat_dev11_i2c",
-                &format_args!("{}", self.reg_dat_dev11_i2c().bit()),
+                &self.reg_dat_dev11_nack_retry_cnt(),
             )
+            .field("reg_dat_dev11_i2c", &self.reg_dat_dev11_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_ADDR_TABLE11_LOC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table12_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table12_loc.rs
index d8821687a0..e4755eb46a 100644
--- a/esp32p4/src/i3c_mst_mem/dev_addr_table12_loc.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_addr_table12_loc.rs
@@ -46,29 +46,20 @@ impl core::fmt::Debug for R {
         f.debug_struct("DEV_ADDR_TABLE12_LOC")
             .field(
                 "reg_dat_dev12_static_addr",
-                &format_args!("{}", self.reg_dat_dev12_static_addr().bits()),
+                &self.reg_dat_dev12_static_addr(),
             )
             .field(
                 "reg_dat_dev12_dynamic_addr",
-                &format_args!("{}", self.reg_dat_dev12_dynamic_addr().bits()),
+                &self.reg_dat_dev12_dynamic_addr(),
             )
             .field(
                 "reg_dat_dev12_nack_retry_cnt",
-                &format_args!("{}", self.reg_dat_dev12_nack_retry_cnt().bits()),
-            )
-            .field(
-                "reg_dat_dev12_i2c",
-                &format_args!("{}", self.reg_dat_dev12_i2c().bit()),
+                &self.reg_dat_dev12_nack_retry_cnt(),
             )
+            .field("reg_dat_dev12_i2c", &self.reg_dat_dev12_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_ADDR_TABLE12_LOC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table1_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table1_loc.rs
index 00791c3c9f..cab74a4042 100644
--- a/esp32p4/src/i3c_mst_mem/dev_addr_table1_loc.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_addr_table1_loc.rs
@@ -44,31 +44,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_ADDR_TABLE1_LOC")
-            .field(
-                "reg_dat_dev1_static_addr",
-                &format_args!("{}", self.reg_dat_dev1_static_addr().bits()),
-            )
+            .field("reg_dat_dev1_static_addr", &self.reg_dat_dev1_static_addr())
             .field(
                 "reg_dat_dev1_dynamic_addr",
-                &format_args!("{}", self.reg_dat_dev1_dynamic_addr().bits()),
+                &self.reg_dat_dev1_dynamic_addr(),
             )
             .field(
                 "reg_dat_dev1_nack_retry_cnt",
-                &format_args!("{}", self.reg_dat_dev1_nack_retry_cnt().bits()),
-            )
-            .field(
-                "reg_dat_dev1_i2c",
-                &format_args!("{}", self.reg_dat_dev1_i2c().bit()),
+                &self.reg_dat_dev1_nack_retry_cnt(),
             )
+            .field("reg_dat_dev1_i2c", &self.reg_dat_dev1_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_ADDR_TABLE1_LOC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table2_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table2_loc.rs
index a9dcb42609..a03cba8749 100644
--- a/esp32p4/src/i3c_mst_mem/dev_addr_table2_loc.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_addr_table2_loc.rs
@@ -44,31 +44,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_ADDR_TABLE2_LOC")
-            .field(
-                "reg_dat_dev2_static_addr",
-                &format_args!("{}", self.reg_dat_dev2_static_addr().bits()),
-            )
+            .field("reg_dat_dev2_static_addr", &self.reg_dat_dev2_static_addr())
             .field(
                 "reg_dat_dev2_dynamic_addr",
-                &format_args!("{}", self.reg_dat_dev2_dynamic_addr().bits()),
+                &self.reg_dat_dev2_dynamic_addr(),
             )
             .field(
                 "reg_dat_dev2_nack_retry_cnt",
-                &format_args!("{}", self.reg_dat_dev2_nack_retry_cnt().bits()),
-            )
-            .field(
-                "reg_dat_dev2_i2c",
-                &format_args!("{}", self.reg_dat_dev2_i2c().bit()),
+                &self.reg_dat_dev2_nack_retry_cnt(),
             )
+            .field("reg_dat_dev2_i2c", &self.reg_dat_dev2_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_ADDR_TABLE2_LOC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table3_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table3_loc.rs
index 5e38be7074..acd89eed8a 100644
--- a/esp32p4/src/i3c_mst_mem/dev_addr_table3_loc.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_addr_table3_loc.rs
@@ -44,31 +44,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_ADDR_TABLE3_LOC")
-            .field(
-                "reg_dat_dev3_static_addr",
-                &format_args!("{}", self.reg_dat_dev3_static_addr().bits()),
-            )
+            .field("reg_dat_dev3_static_addr", &self.reg_dat_dev3_static_addr())
             .field(
                 "reg_dat_dev3_dynamic_addr",
-                &format_args!("{}", self.reg_dat_dev3_dynamic_addr().bits()),
+                &self.reg_dat_dev3_dynamic_addr(),
             )
             .field(
                 "reg_dat_dev3_nack_retry_cnt",
-                &format_args!("{}", self.reg_dat_dev3_nack_retry_cnt().bits()),
-            )
-            .field(
-                "reg_dat_dev3_i2c",
-                &format_args!("{}", self.reg_dat_dev3_i2c().bit()),
+                &self.reg_dat_dev3_nack_retry_cnt(),
             )
+            .field("reg_dat_dev3_i2c", &self.reg_dat_dev3_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_ADDR_TABLE3_LOC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table4_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table4_loc.rs
index 6ae6b380ec..e294fc57fd 100644
--- a/esp32p4/src/i3c_mst_mem/dev_addr_table4_loc.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_addr_table4_loc.rs
@@ -44,31 +44,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_ADDR_TABLE4_LOC")
-            .field(
-                "reg_dat_dev4_static_addr",
-                &format_args!("{}", self.reg_dat_dev4_static_addr().bits()),
-            )
+            .field("reg_dat_dev4_static_addr", &self.reg_dat_dev4_static_addr())
             .field(
                 "reg_dat_dev4_dynamic_addr",
-                &format_args!("{}", self.reg_dat_dev4_dynamic_addr().bits()),
+                &self.reg_dat_dev4_dynamic_addr(),
             )
             .field(
                 "reg_dat_dev4_nack_retry_cnt",
-                &format_args!("{}", self.reg_dat_dev4_nack_retry_cnt().bits()),
-            )
-            .field(
-                "reg_dat_dev4_i2c",
-                &format_args!("{}", self.reg_dat_dev4_i2c().bit()),
+                &self.reg_dat_dev4_nack_retry_cnt(),
             )
+            .field("reg_dat_dev4_i2c", &self.reg_dat_dev4_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_ADDR_TABLE4_LOC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table5_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table5_loc.rs
index 9bbf2ca0c4..d93bf8fa13 100644
--- a/esp32p4/src/i3c_mst_mem/dev_addr_table5_loc.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_addr_table5_loc.rs
@@ -44,31 +44,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_ADDR_TABLE5_LOC")
-            .field(
-                "reg_dat_dev5_static_addr",
-                &format_args!("{}", self.reg_dat_dev5_static_addr().bits()),
-            )
+            .field("reg_dat_dev5_static_addr", &self.reg_dat_dev5_static_addr())
             .field(
                 "reg_dat_dev5_dynamic_addr",
-                &format_args!("{}", self.reg_dat_dev5_dynamic_addr().bits()),
+                &self.reg_dat_dev5_dynamic_addr(),
             )
             .field(
                 "reg_dat_dev5_nack_retry_cnt",
-                &format_args!("{}", self.reg_dat_dev5_nack_retry_cnt().bits()),
-            )
-            .field(
-                "reg_dat_dev5_i2c",
-                &format_args!("{}", self.reg_dat_dev5_i2c().bit()),
+                &self.reg_dat_dev5_nack_retry_cnt(),
             )
+            .field("reg_dat_dev5_i2c", &self.reg_dat_dev5_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_ADDR_TABLE5_LOC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table6_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table6_loc.rs
index 36a66ef292..84bec82734 100644
--- a/esp32p4/src/i3c_mst_mem/dev_addr_table6_loc.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_addr_table6_loc.rs
@@ -44,31 +44,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_ADDR_TABLE6_LOC")
-            .field(
-                "reg_dat_dev6_static_addr",
-                &format_args!("{}", self.reg_dat_dev6_static_addr().bits()),
-            )
+            .field("reg_dat_dev6_static_addr", &self.reg_dat_dev6_static_addr())
             .field(
                 "reg_dat_dev6_dynamic_addr",
-                &format_args!("{}", self.reg_dat_dev6_dynamic_addr().bits()),
+                &self.reg_dat_dev6_dynamic_addr(),
             )
             .field(
                 "reg_dat_dev6_nack_retry_cnt",
-                &format_args!("{}", self.reg_dat_dev6_nack_retry_cnt().bits()),
-            )
-            .field(
-                "reg_dat_dev6_i2c",
-                &format_args!("{}", self.reg_dat_dev6_i2c().bit()),
+                &self.reg_dat_dev6_nack_retry_cnt(),
             )
+            .field("reg_dat_dev6_i2c", &self.reg_dat_dev6_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_ADDR_TABLE6_LOC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table7_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table7_loc.rs
index 488ec5ecd4..905bad70fd 100644
--- a/esp32p4/src/i3c_mst_mem/dev_addr_table7_loc.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_addr_table7_loc.rs
@@ -44,31 +44,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_ADDR_TABLE7_LOC")
-            .field(
-                "reg_dat_dev7_static_addr",
-                &format_args!("{}", self.reg_dat_dev7_static_addr().bits()),
-            )
+            .field("reg_dat_dev7_static_addr", &self.reg_dat_dev7_static_addr())
             .field(
                 "reg_dat_dev7_dynamic_addr",
-                &format_args!("{}", self.reg_dat_dev7_dynamic_addr().bits()),
+                &self.reg_dat_dev7_dynamic_addr(),
             )
             .field(
                 "reg_dat_dev7_nack_retry_cnt",
-                &format_args!("{}", self.reg_dat_dev7_nack_retry_cnt().bits()),
-            )
-            .field(
-                "reg_dat_dev7_i2c",
-                &format_args!("{}", self.reg_dat_dev7_i2c().bit()),
+                &self.reg_dat_dev7_nack_retry_cnt(),
             )
+            .field("reg_dat_dev7_i2c", &self.reg_dat_dev7_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_ADDR_TABLE7_LOC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table8_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table8_loc.rs
index 9ee68aad75..917a7a4968 100644
--- a/esp32p4/src/i3c_mst_mem/dev_addr_table8_loc.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_addr_table8_loc.rs
@@ -44,31 +44,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_ADDR_TABLE8_LOC")
-            .field(
-                "reg_dat_dev8_static_addr",
-                &format_args!("{}", self.reg_dat_dev8_static_addr().bits()),
-            )
+            .field("reg_dat_dev8_static_addr", &self.reg_dat_dev8_static_addr())
             .field(
                 "reg_dat_dev8_dynamic_addr",
-                &format_args!("{}", self.reg_dat_dev8_dynamic_addr().bits()),
+                &self.reg_dat_dev8_dynamic_addr(),
             )
             .field(
                 "reg_dat_dev8_nack_retry_cnt",
-                &format_args!("{}", self.reg_dat_dev8_nack_retry_cnt().bits()),
-            )
-            .field(
-                "reg_dat_dev8_i2c",
-                &format_args!("{}", self.reg_dat_dev8_i2c().bit()),
+                &self.reg_dat_dev8_nack_retry_cnt(),
             )
+            .field("reg_dat_dev8_i2c", &self.reg_dat_dev8_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_ADDR_TABLE8_LOC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst_mem/dev_addr_table9_loc.rs b/esp32p4/src/i3c_mst_mem/dev_addr_table9_loc.rs
index dc400f0071..7a87718e22 100644
--- a/esp32p4/src/i3c_mst_mem/dev_addr_table9_loc.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_addr_table9_loc.rs
@@ -44,31 +44,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_ADDR_TABLE9_LOC")
-            .field(
-                "reg_dat_dev9_static_addr",
-                &format_args!("{}", self.reg_dat_dev9_static_addr().bits()),
-            )
+            .field("reg_dat_dev9_static_addr", &self.reg_dat_dev9_static_addr())
             .field(
                 "reg_dat_dev9_dynamic_addr",
-                &format_args!("{}", self.reg_dat_dev9_dynamic_addr().bits()),
+                &self.reg_dat_dev9_dynamic_addr(),
             )
             .field(
                 "reg_dat_dev9_nack_retry_cnt",
-                &format_args!("{}", self.reg_dat_dev9_nack_retry_cnt().bits()),
-            )
-            .field(
-                "reg_dat_dev9_i2c",
-                &format_args!("{}", self.reg_dat_dev9_i2c().bit()),
+                &self.reg_dat_dev9_nack_retry_cnt(),
             )
+            .field("reg_dat_dev9_i2c", &self.reg_dat_dev9_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_ADDR_TABLE9_LOC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table10_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc1.rs
index 26720d8a00..89fed691bc 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table10_loc1.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE10_LOC1")
-            .field(
-                "dct_dev10_loc1",
-                &format_args!("{}", self.dct_dev10_loc1().bits()),
-            )
+            .field("dct_dev10_loc1", &self.dct_dev10_loc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE10_LOC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table10_loc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE10_LOC1_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE10_LOC1_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table10_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc2.rs
index 72082976eb..c36ff28826 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table10_loc2.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE10_LOC2")
-            .field(
-                "dct_dev10_loc2",
-                &format_args!("{}", self.dct_dev10_loc2().bits()),
-            )
+            .field("dct_dev10_loc2", &self.dct_dev10_loc2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE10_LOC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table10_loc2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE10_LOC2_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE10_LOC2_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table10_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc3.rs
index 0806f216f4..b785f8d107 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table10_loc3.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE10_LOC3")
-            .field(
-                "dct_dev10_loc3",
-                &format_args!("{}", self.dct_dev10_loc3().bits()),
-            )
+            .field("dct_dev10_loc3", &self.dct_dev10_loc3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE10_LOC3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table10_loc3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE10_LOC3_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE10_LOC3_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table10_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc4.rs
index 93a5fb5e0a..a3fe9ebdf8 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table10_loc4.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table10_loc4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE10_LOC4")
-            .field(
-                "dct_dev10_loc4",
-                &format_args!("{}", self.dct_dev10_loc4().bits()),
-            )
+            .field("dct_dev10_loc4", &self.dct_dev10_loc4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE10_LOC4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table10_loc4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE10_LOC4_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE10_LOC4_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table11_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc1.rs
index 46874e46c7..43d9d964a9 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table11_loc1.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE11_LOC1")
-            .field(
-                "dct_dev11_loc1",
-                &format_args!("{}", self.dct_dev11_loc1().bits()),
-            )
+            .field("dct_dev11_loc1", &self.dct_dev11_loc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE11_LOC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table11_loc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE11_LOC1_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE11_LOC1_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table11_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc2.rs
index 96a9a45430..3ccc46ddb8 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table11_loc2.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE11_LOC2")
-            .field(
-                "dct_dev11_loc2",
-                &format_args!("{}", self.dct_dev11_loc2().bits()),
-            )
+            .field("dct_dev11_loc2", &self.dct_dev11_loc2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE11_LOC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table11_loc2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE11_LOC2_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE11_LOC2_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table11_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc3.rs
index c71693dcdc..8dd027e5ca 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table11_loc3.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE11_LOC3")
-            .field(
-                "dct_dev11_loc3",
-                &format_args!("{}", self.dct_dev11_loc3().bits()),
-            )
+            .field("dct_dev11_loc3", &self.dct_dev11_loc3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE11_LOC3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table11_loc3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE11_LOC3_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE11_LOC3_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table11_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc4.rs
index 662c4e9062..9f70588eff 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table11_loc4.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table11_loc4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE11_LOC4")
-            .field(
-                "dct_dev11_loc4",
-                &format_args!("{}", self.dct_dev11_loc4().bits()),
-            )
+            .field("dct_dev11_loc4", &self.dct_dev11_loc4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE11_LOC4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table11_loc4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE11_LOC4_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE11_LOC4_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table12_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc1.rs
index 5b15c149c5..866f3da1b3 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table12_loc1.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE12_LOC1")
-            .field(
-                "dct_dev12_loc1",
-                &format_args!("{}", self.dct_dev12_loc1().bits()),
-            )
+            .field("dct_dev12_loc1", &self.dct_dev12_loc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE12_LOC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table12_loc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE12_LOC1_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE12_LOC1_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table12_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc2.rs
index 7506389e2e..ae7e226b39 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table12_loc2.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE12_LOC2")
-            .field(
-                "dct_dev12_loc2",
-                &format_args!("{}", self.dct_dev12_loc2().bits()),
-            )
+            .field("dct_dev12_loc2", &self.dct_dev12_loc2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE12_LOC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table12_loc2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE12_LOC2_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE12_LOC2_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table12_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc3.rs
index defc469d8c..558dfc5c2e 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table12_loc3.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE12_LOC3")
-            .field(
-                "dct_dev12_loc3",
-                &format_args!("{}", self.dct_dev12_loc3().bits()),
-            )
+            .field("dct_dev12_loc3", &self.dct_dev12_loc3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE12_LOC3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table12_loc3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE12_LOC3_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE12_LOC3_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table12_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc4.rs
index 7855e20405..d6f5e62630 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table12_loc4.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table12_loc4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE12_LOC4")
-            .field(
-                "dct_dev12_loc4",
-                &format_args!("{}", self.dct_dev12_loc4().bits()),
-            )
+            .field("dct_dev12_loc4", &self.dct_dev12_loc4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE12_LOC4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table12_loc4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE12_LOC4_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE12_LOC4_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table1_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc1.rs
index 4c400daba1..e6962dbeba 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table1_loc1.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE1_LOC1")
-            .field(
-                "dct_dev1_loc1",
-                &format_args!("{}", self.dct_dev1_loc1().bits()),
-            )
+            .field("dct_dev1_loc1", &self.dct_dev1_loc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE1_LOC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table1_loc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE1_LOC1_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE1_LOC1_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table1_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc2.rs
index ff3cbf56dc..52446fb895 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table1_loc2.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE1_LOC2")
-            .field(
-                "dct_dev1_loc2",
-                &format_args!("{}", self.dct_dev1_loc2().bits()),
-            )
+            .field("dct_dev1_loc2", &self.dct_dev1_loc2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE1_LOC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table1_loc2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE1_LOC2_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE1_LOC2_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table1_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc3.rs
index fa805ae400..e42255571e 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table1_loc3.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE1_LOC3")
-            .field(
-                "dct_dev1_loc3",
-                &format_args!("{}", self.dct_dev1_loc3().bits()),
-            )
+            .field("dct_dev1_loc3", &self.dct_dev1_loc3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE1_LOC3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table1_loc3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE1_LOC3_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE1_LOC3_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table1_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc4.rs
index 3dea86f64b..f52eefde3a 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table1_loc4.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table1_loc4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE1_LOC4")
-            .field(
-                "dct_dev1_loc4",
-                &format_args!("{}", self.dct_dev1_loc4().bits()),
-            )
+            .field("dct_dev1_loc4", &self.dct_dev1_loc4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE1_LOC4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table1_loc4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE1_LOC4_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE1_LOC4_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table2_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc1.rs
index 4a8ca23c0d..8ea5445011 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table2_loc1.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE2_LOC1")
-            .field(
-                "dct_dev2_loc1",
-                &format_args!("{}", self.dct_dev2_loc1().bits()),
-            )
+            .field("dct_dev2_loc1", &self.dct_dev2_loc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE2_LOC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table2_loc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE2_LOC1_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE2_LOC1_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table2_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc2.rs
index fbb3eb6c18..d6f40f6e93 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table2_loc2.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE2_LOC2")
-            .field(
-                "dct_dev2_loc2",
-                &format_args!("{}", self.dct_dev2_loc2().bits()),
-            )
+            .field("dct_dev2_loc2", &self.dct_dev2_loc2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE2_LOC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table2_loc2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE2_LOC2_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE2_LOC2_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table2_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc3.rs
index 7f6a7db9c1..215fce1341 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table2_loc3.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE2_LOC3")
-            .field(
-                "dct_dev2_loc3",
-                &format_args!("{}", self.dct_dev2_loc3().bits()),
-            )
+            .field("dct_dev2_loc3", &self.dct_dev2_loc3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE2_LOC3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table2_loc3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE2_LOC3_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE2_LOC3_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table2_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc4.rs
index edf0952f6e..0590b2fc71 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table2_loc4.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table2_loc4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE2_LOC4")
-            .field(
-                "dct_dev2_loc4",
-                &format_args!("{}", self.dct_dev2_loc4().bits()),
-            )
+            .field("dct_dev2_loc4", &self.dct_dev2_loc4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE2_LOC4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table2_loc4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE2_LOC4_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE2_LOC4_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table3_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc1.rs
index 4f300f76fa..eec5053e6d 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table3_loc1.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE3_LOC1")
-            .field(
-                "dct_dev3_loc1",
-                &format_args!("{}", self.dct_dev3_loc1().bits()),
-            )
+            .field("dct_dev3_loc1", &self.dct_dev3_loc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE3_LOC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table3_loc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE3_LOC1_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE3_LOC1_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table3_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc2.rs
index 26723a75a9..b99a34e6ba 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table3_loc2.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE3_LOC2")
-            .field(
-                "dct_dev3_loc2",
-                &format_args!("{}", self.dct_dev3_loc2().bits()),
-            )
+            .field("dct_dev3_loc2", &self.dct_dev3_loc2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE3_LOC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table3_loc2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE3_LOC2_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE3_LOC2_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table3_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc3.rs
index 59ff99e6bc..6bb9af1760 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table3_loc3.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE3_LOC3")
-            .field(
-                "dct_dev3_loc3",
-                &format_args!("{}", self.dct_dev3_loc3().bits()),
-            )
+            .field("dct_dev3_loc3", &self.dct_dev3_loc3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE3_LOC3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table3_loc3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE3_LOC3_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE3_LOC3_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table3_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc4.rs
index 8929352396..ac1d5e11d3 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table3_loc4.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table3_loc4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE3_LOC4")
-            .field(
-                "dct_dev3_loc4",
-                &format_args!("{}", self.dct_dev3_loc4().bits()),
-            )
+            .field("dct_dev3_loc4", &self.dct_dev3_loc4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE3_LOC4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table3_loc4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE3_LOC4_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE3_LOC4_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table4_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc1.rs
index 82be461a28..275877fc79 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table4_loc1.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE4_LOC1")
-            .field(
-                "dct_dev4_loc1",
-                &format_args!("{}", self.dct_dev4_loc1().bits()),
-            )
+            .field("dct_dev4_loc1", &self.dct_dev4_loc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE4_LOC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table4_loc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE4_LOC1_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE4_LOC1_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table4_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc2.rs
index 2aab4735f8..2bd32ecd06 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table4_loc2.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE4_LOC2")
-            .field(
-                "dct_dev4_loc2",
-                &format_args!("{}", self.dct_dev4_loc2().bits()),
-            )
+            .field("dct_dev4_loc2", &self.dct_dev4_loc2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE4_LOC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table4_loc2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE4_LOC2_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE4_LOC2_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table4_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc3.rs
index 511fa571a2..73deff95bb 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table4_loc3.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE4_LOC3")
-            .field(
-                "dct_dev4_loc3",
-                &format_args!("{}", self.dct_dev4_loc3().bits()),
-            )
+            .field("dct_dev4_loc3", &self.dct_dev4_loc3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE4_LOC3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table4_loc3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE4_LOC3_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE4_LOC3_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table4_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc4.rs
index 29f11921be..0dacd21e87 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table4_loc4.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table4_loc4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE4_LOC4")
-            .field(
-                "dct_dev4_loc4",
-                &format_args!("{}", self.dct_dev4_loc4().bits()),
-            )
+            .field("dct_dev4_loc4", &self.dct_dev4_loc4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE4_LOC4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table4_loc4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE4_LOC4_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE4_LOC4_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table5_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc1.rs
index 6a4295744b..b4174c5658 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table5_loc1.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE5_LOC1")
-            .field(
-                "dct_dev5_loc1",
-                &format_args!("{}", self.dct_dev5_loc1().bits()),
-            )
+            .field("dct_dev5_loc1", &self.dct_dev5_loc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE5_LOC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table5_loc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE5_LOC1_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE5_LOC1_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table5_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc2.rs
index 66df60c712..7f94c06e31 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table5_loc2.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE5_LOC2")
-            .field(
-                "dct_dev5_loc2",
-                &format_args!("{}", self.dct_dev5_loc2().bits()),
-            )
+            .field("dct_dev5_loc2", &self.dct_dev5_loc2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE5_LOC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table5_loc2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE5_LOC2_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE5_LOC2_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table5_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc3.rs
index 83eeff1ce8..bb12951eb2 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table5_loc3.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE5_LOC3")
-            .field(
-                "dct_dev5_loc3",
-                &format_args!("{}", self.dct_dev5_loc3().bits()),
-            )
+            .field("dct_dev5_loc3", &self.dct_dev5_loc3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE5_LOC3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table5_loc3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE5_LOC3_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE5_LOC3_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table5_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc4.rs
index b6092aa1c5..f80cca09ed 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table5_loc4.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table5_loc4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE5_LOC4")
-            .field(
-                "dct_dev5_loc4",
-                &format_args!("{}", self.dct_dev5_loc4().bits()),
-            )
+            .field("dct_dev5_loc4", &self.dct_dev5_loc4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE5_LOC4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table5_loc4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE5_LOC4_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE5_LOC4_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table6_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc1.rs
index 17ddcc9baf..09b91642c7 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table6_loc1.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE6_LOC1")
-            .field(
-                "dct_dev6_loc1",
-                &format_args!("{}", self.dct_dev6_loc1().bits()),
-            )
+            .field("dct_dev6_loc1", &self.dct_dev6_loc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE6_LOC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table6_loc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE6_LOC1_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE6_LOC1_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table6_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc2.rs
index f34bc41542..f36a1c78ee 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table6_loc2.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE6_LOC2")
-            .field(
-                "dct_dev6_loc2",
-                &format_args!("{}", self.dct_dev6_loc2().bits()),
-            )
+            .field("dct_dev6_loc2", &self.dct_dev6_loc2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE6_LOC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table6_loc2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE6_LOC2_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE6_LOC2_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table6_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc3.rs
index 79a9d56733..7d53dcb85e 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table6_loc3.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE6_LOC3")
-            .field(
-                "dct_dev6_loc3",
-                &format_args!("{}", self.dct_dev6_loc3().bits()),
-            )
+            .field("dct_dev6_loc3", &self.dct_dev6_loc3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE6_LOC3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table6_loc3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE6_LOC3_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE6_LOC3_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table6_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc4.rs
index 03900ed75b..250f026131 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table6_loc4.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table6_loc4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE6_LOC4")
-            .field(
-                "dct_dev6_loc4",
-                &format_args!("{}", self.dct_dev6_loc4().bits()),
-            )
+            .field("dct_dev6_loc4", &self.dct_dev6_loc4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE6_LOC4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table6_loc4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE6_LOC4_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE6_LOC4_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table7_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc1.rs
index 9e69b66268..f94e1eb8e7 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table7_loc1.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE7_LOC1")
-            .field(
-                "dct_dev7_loc1",
-                &format_args!("{}", self.dct_dev7_loc1().bits()),
-            )
+            .field("dct_dev7_loc1", &self.dct_dev7_loc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE7_LOC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table7_loc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE7_LOC1_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE7_LOC1_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table7_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc2.rs
index 8e3267fc2b..34b97a8475 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table7_loc2.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE7_LOC2")
-            .field(
-                "dct_dev7_loc2",
-                &format_args!("{}", self.dct_dev7_loc2().bits()),
-            )
+            .field("dct_dev7_loc2", &self.dct_dev7_loc2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE7_LOC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table7_loc2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE7_LOC2_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE7_LOC2_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table7_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc3.rs
index 7796920e97..427e2f595f 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table7_loc3.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE7_LOC3")
-            .field(
-                "dct_dev7_loc3",
-                &format_args!("{}", self.dct_dev7_loc3().bits()),
-            )
+            .field("dct_dev7_loc3", &self.dct_dev7_loc3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE7_LOC3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table7_loc3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE7_LOC3_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE7_LOC3_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table7_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc4.rs
index 758ba50aaf..1dd401c466 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table7_loc4.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table7_loc4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE7_LOC4")
-            .field(
-                "dct_dev7_loc4",
-                &format_args!("{}", self.dct_dev7_loc4().bits()),
-            )
+            .field("dct_dev7_loc4", &self.dct_dev7_loc4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE7_LOC4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table7_loc4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE7_LOC4_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE7_LOC4_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table8_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc1.rs
index c4c16e3ab9..d5e1fdedb2 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table8_loc1.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE8_LOC1")
-            .field(
-                "dct_dev8_loc1",
-                &format_args!("{}", self.dct_dev8_loc1().bits()),
-            )
+            .field("dct_dev8_loc1", &self.dct_dev8_loc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE8_LOC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table8_loc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE8_LOC1_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE8_LOC1_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table8_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc2.rs
index 339c39542d..aea46c1c15 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table8_loc2.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE8_LOC2")
-            .field(
-                "dct_dev8_loc2",
-                &format_args!("{}", self.dct_dev8_loc2().bits()),
-            )
+            .field("dct_dev8_loc2", &self.dct_dev8_loc2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE8_LOC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table8_loc2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE8_LOC2_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE8_LOC2_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table8_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc3.rs
index 2c43866c10..d3c93582af 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table8_loc3.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE8_LOC3")
-            .field(
-                "dct_dev8_loc3",
-                &format_args!("{}", self.dct_dev8_loc3().bits()),
-            )
+            .field("dct_dev8_loc3", &self.dct_dev8_loc3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE8_LOC3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table8_loc3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE8_LOC3_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE8_LOC3_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table8_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc4.rs
index 37f6edf4e0..4bdb2bc70d 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table8_loc4.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table8_loc4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE8_LOC4")
-            .field(
-                "dct_dev8_loc4",
-                &format_args!("{}", self.dct_dev8_loc4().bits()),
-            )
+            .field("dct_dev8_loc4", &self.dct_dev8_loc4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE8_LOC4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table8_loc4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE8_LOC4_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE8_LOC4_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table9_loc1.rs b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc1.rs
index 4f8189b13f..8ea73e9318 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table9_loc1.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE9_LOC1")
-            .field(
-                "dct_dev9_loc1",
-                &format_args!("{}", self.dct_dev9_loc1().bits()),
-            )
+            .field("dct_dev9_loc1", &self.dct_dev9_loc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE9_LOC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table9_loc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE9_LOC1_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE9_LOC1_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table9_loc2.rs b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc2.rs
index 7aa37d151e..c8fc39dd4c 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table9_loc2.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE9_LOC2")
-            .field(
-                "dct_dev9_loc2",
-                &format_args!("{}", self.dct_dev9_loc2().bits()),
-            )
+            .field("dct_dev9_loc2", &self.dct_dev9_loc2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE9_LOC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table9_loc2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE9_LOC2_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE9_LOC2_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table9_loc3.rs b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc3.rs
index 1546ad7738..7227e6a8fd 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table9_loc3.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE9_LOC3")
-            .field(
-                "dct_dev9_loc3",
-                &format_args!("{}", self.dct_dev9_loc3().bits()),
-            )
+            .field("dct_dev9_loc3", &self.dct_dev9_loc3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE9_LOC3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table9_loc3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE9_LOC3_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE9_LOC3_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/dev_char_table9_loc4.rs b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc4.rs
index ca5fb1c481..e6c1513537 100644
--- a/esp32p4/src/i3c_mst_mem/dev_char_table9_loc4.rs
+++ b/esp32p4/src/i3c_mst_mem/dev_char_table9_loc4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEV_CHAR_TABLE9_LOC4")
-            .field(
-                "dct_dev9_loc4",
-                &format_args!("{}", self.dct_dev9_loc4().bits()),
-            )
+            .field("dct_dev9_loc4", &self.dct_dev9_loc4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEV_CHAR_TABLE9_LOC4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dev_char_table9_loc4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DEV_CHAR_TABLE9_LOC4_SPEC;
 impl crate::RegisterSpec for DEV_CHAR_TABLE9_LOC4_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/ibi_data_buf.rs b/esp32p4/src/i3c_mst_mem/ibi_data_buf.rs
index 7b8a7ce3ea..829b6e22ba 100644
--- a/esp32p4/src/i3c_mst_mem/ibi_data_buf.rs
+++ b/esp32p4/src/i3c_mst_mem/ibi_data_buf.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBI_DATA_BUF")
-            .field("ibi_data", &format_args!("{}", self.ibi_data().bits()))
+            .field("ibi_data", &self.ibi_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBI_DATA_BUF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibi_data_buf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IBI_DATA_BUF_SPEC;
 impl crate::RegisterSpec for IBI_DATA_BUF_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/ibi_status_buf.rs b/esp32p4/src/i3c_mst_mem/ibi_status_buf.rs
index 23d684d044..56602701d9 100644
--- a/esp32p4/src/i3c_mst_mem/ibi_status_buf.rs
+++ b/esp32p4/src/i3c_mst_mem/ibi_status_buf.rs
@@ -27,21 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBI_STATUS_BUF")
-            .field(
-                "data_length",
-                &format_args!("{}", self.data_length().bits()),
-            )
-            .field("ibi_id", &format_args!("{}", self.ibi_id().bits()))
-            .field("ibi_sts", &format_args!("{}", self.ibi_sts().bit()))
+            .field("data_length", &self.data_length())
+            .field("ibi_id", &self.ibi_id())
+            .field("ibi_sts", &self.ibi_sts())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBI_STATUS_BUF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibi_status_buf::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IBI_STATUS_BUF_SPEC;
 impl crate::RegisterSpec for IBI_STATUS_BUF_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/response_buf_port.rs b/esp32p4/src/i3c_mst_mem/response_buf_port.rs
index 25e58a4c43..7f908de2d6 100644
--- a/esp32p4/src/i3c_mst_mem/response_buf_port.rs
+++ b/esp32p4/src/i3c_mst_mem/response_buf_port.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESPONSE_BUF_PORT")
-            .field("response", &format_args!("{}", self.response().bits()))
+            .field("response", &self.response())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESPONSE_BUF_PORT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`response_buf_port::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESPONSE_BUF_PORT_SPEC;
 impl crate::RegisterSpec for RESPONSE_BUF_PORT_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/rx_data_port.rs b/esp32p4/src/i3c_mst_mem/rx_data_port.rs
index c13af28673..c8cc42edef 100644
--- a/esp32p4/src/i3c_mst_mem/rx_data_port.rs
+++ b/esp32p4/src/i3c_mst_mem/rx_data_port.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_DATA_PORT")
-            .field(
-                "rx_data_port",
-                &format_args!("{}", self.rx_data_port().bits()),
-            )
+            .field("rx_data_port", &self.rx_data_port())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_DATA_PORT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_data_port::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_DATA_PORT_SPEC;
 impl crate::RegisterSpec for RX_DATA_PORT_SPEC {
diff --git a/esp32p4/src/i3c_mst_mem/tx_data_port.rs b/esp32p4/src/i3c_mst_mem/tx_data_port.rs
index ef39753ba3..7addbaf648 100644
--- a/esp32p4/src/i3c_mst_mem/tx_data_port.rs
+++ b/esp32p4/src/i3c_mst_mem/tx_data_port.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_DATA_PORT")
-            .field(
-                "reg_tx_data_port",
-                &format_args!("{}", self.reg_tx_data_port().bits()),
-            )
+            .field("reg_tx_data_port", &self.reg_tx_data_port())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_DATA_PORT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Transmit Data Port. Transmit data is mapped to the Tx-data buffer and transmit data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor."]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_slv/capabilities.rs b/esp32p4/src/i3c_slv/capabilities.rs
index cded7004b4..45aefbd2fc 100644
--- a/esp32p4/src/i3c_slv/capabilities.rs
+++ b/esp32p4/src/i3c_slv/capabilities.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAPABILITIES")
-            .field(
-                "capablities",
-                &format_args!("{}", self.capablities().bits()),
-            )
+            .field("capablities", &self.capablities())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAPABILITIES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capabilities::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CAPABILITIES_SPEC;
 impl crate::RegisterSpec for CAPABILITIES_SPEC {
diff --git a/esp32p4/src/i3c_slv/capabilities2.rs b/esp32p4/src/i3c_slv/capabilities2.rs
index 1fe020cfda..ca63483c3f 100644
--- a/esp32p4/src/i3c_slv/capabilities2.rs
+++ b/esp32p4/src/i3c_slv/capabilities2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAPABILITIES2")
-            .field(
-                "capablities2",
-                &format_args!("{}", self.capablities2().bits()),
-            )
+            .field("capablities2", &self.capablities2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAPABILITIES2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capabilities2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CAPABILITIES2_SPEC;
 impl crate::RegisterSpec for CAPABILITIES2_SPEC {
diff --git a/esp32p4/src/i3c_slv/config.rs b/esp32p4/src/i3c_slv/config.rs
index 5220fc70d7..0a42613d2a 100644
--- a/esp32p4/src/i3c_slv/config.rs
+++ b/esp32p4/src/i3c_slv/config.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG")
-            .field("slvena", &format_args!("{}", self.slvena().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("matchss", &format_args!("{}", self.matchss().bit()))
-            .field("s0ignore", &format_args!("{}", self.s0ignore().bit()))
-            .field("ddrok", &format_args!("{}", self.ddrok().bit()))
-            .field("idrand", &format_args!("{}", self.idrand().bit()))
-            .field("offline", &format_args!("{}", self.offline().bit()))
-            .field("bamatch", &format_args!("{}", self.bamatch().bits()))
-            .field("saddr", &format_args!("{}", self.saddr().bits()))
+            .field("slvena", &self.slvena())
+            .field("nack", &self.nack())
+            .field("matchss", &self.matchss())
+            .field("s0ignore", &self.s0ignore())
+            .field("ddrok", &self.ddrok())
+            .field("idrand", &self.idrand())
+            .field("offline", &self.offline())
+            .field("bamatch", &self.bamatch())
+            .field("saddr", &self.saddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus. This should be not set until registers such as PARTNO, IDEXT and the like are set 1st -if used- since they impact data to the master"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_slv/ctrl.rs b/esp32p4/src/i3c_slv/ctrl.rs
index 53bd15c161..62d5a44185 100644
--- a/esp32p4/src/i3c_slv/ctrl.rs
+++ b/esp32p4/src/i3c_slv/ctrl.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("slv_event", &format_args!("{}", self.slv_event().bits()))
-            .field("extdata", &format_args!("{}", self.extdata().bit()))
-            .field("mapidx", &format_args!("{}", self.mapidx().bits()))
-            .field("ibidata", &format_args!("{}", self.ibidata().bits()))
-            .field("pendint", &format_args!("{}", self.pendint().bits()))
-            .field("actstate", &format_args!("{}", self.actstate().bits()))
-            .field("vendinfo", &format_args!("{}", self.vendinfo().bits()))
+            .field("slv_event", &self.slv_event())
+            .field("extdata", &self.extdata())
+            .field("mapidx", &self.mapidx())
+            .field("ibidata", &self.ibidata())
+            .field("pendint", &self.pendint())
+            .field("actstate", &self.actstate())
+            .field("vendinfo", &self.vendinfo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will show the status as it progresses. Once completed, the field will automatically return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1: start an IBI. This will try to push through an IBI on the bus. If data associate with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is enabled, this will include anytime control related bytes further, the IBIDATA byte will have bit7 set to 1."]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_slv/datactrl.rs b/esp32p4/src/i3c_slv/datactrl.rs
index 7b104639a4..76e81e95ec 100644
--- a/esp32p4/src/i3c_slv/datactrl.rs
+++ b/esp32p4/src/i3c_slv/datactrl.rs
@@ -60,21 +60,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATACTRL")
-            .field("txtrig", &format_args!("{}", self.txtrig().bits()))
-            .field("rxtrig", &format_args!("{}", self.rxtrig().bits()))
-            .field("txcount", &format_args!("{}", self.txcount().bits()))
-            .field("rxcount", &format_args!("{}", self.rxcount().bits()))
-            .field("txfull", &format_args!("{}", self.txfull().bit()))
-            .field("rxempty", &format_args!("{}", self.rxempty().bit()))
+            .field("txtrig", &self.txtrig())
+            .field("rxtrig", &self.rxtrig())
+            .field("txcount", &self.txcount())
+            .field("rxcount", &self.rxcount())
+            .field("txfull", &self.txfull())
+            .field("rxempty", &self.rxempty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATACTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Flushes the from-bus buffer/FIFO. Not normally used"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_slv/idext.rs b/esp32p4/src/i3c_slv/idext.rs
index 419e3c23f8..56ee956ca2 100644
--- a/esp32p4/src/i3c_slv/idext.rs
+++ b/esp32p4/src/i3c_slv/idext.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDEXT")
-            .field("idext", &format_args!("{}", self.idext().bits()))
+            .field("idext", &self.idext())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDEXT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_slv/idpartno.rs b/esp32p4/src/i3c_slv/idpartno.rs
index ed40e332a3..d8b6f73d59 100644
--- a/esp32p4/src/i3c_slv/idpartno.rs
+++ b/esp32p4/src/i3c_slv/idpartno.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDPARTNO")
-            .field("partno", &format_args!("{}", self.partno().bits()))
+            .field("partno", &self.partno())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDPARTNO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_slv/intmasked.rs b/esp32p4/src/i3c_slv/intmasked.rs
index d98146195d..2dd51a7842 100644
--- a/esp32p4/src/i3c_slv/intmasked.rs
+++ b/esp32p4/src/i3c_slv/intmasked.rs
@@ -27,18 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTMASKED")
-            .field("stop_mask", &format_args!("{}", self.stop_mask().bit()))
-            .field("rxpend_mask", &format_args!("{}", self.rxpend_mask().bit()))
-            .field("txsend_mask", &format_args!("{}", self.txsend_mask().bit()))
+            .field("stop_mask", &self.stop_mask())
+            .field("rxpend_mask", &self.rxpend_mask())
+            .field("txsend_mask", &self.txsend_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTMASKED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intmasked::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTMASKED_SPEC;
 impl crate::RegisterSpec for INTMASKED_SPEC {
diff --git a/esp32p4/src/i3c_slv/intset.rs b/esp32p4/src/i3c_slv/intset.rs
index 9cfba9db43..ed5adeab7d 100644
--- a/esp32p4/src/i3c_slv/intset.rs
+++ b/esp32p4/src/i3c_slv/intset.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTSET")
-            .field("stop_ena", &format_args!("{}", self.stop_ena().bit()))
-            .field("rxpend_ena", &format_args!("{}", self.rxpend_ena().bit()))
-            .field("txsend_ena", &format_args!("{}", self.txsend_ena().bit()))
+            .field("stop_ena", &self.stop_ena())
+            .field("rxpend_ena", &self.rxpend_ena())
+            .field("txsend_ena", &self.txsend_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTSET_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 10 - Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped."]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_slv/rdarab.rs b/esp32p4/src/i3c_slv/rdarab.rs
index b7fb1875e9..41b85ca3b1 100644
--- a/esp32p4/src/i3c_slv/rdarab.rs
+++ b/esp32p4/src/i3c_slv/rdarab.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDARAB")
-            .field("data0", &format_args!("{}", self.data0().bits()))
+            .field("data0", &self.data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDARAB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read Byte Data (from-bus) register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdarab::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RDARAB_SPEC;
 impl crate::RegisterSpec for RDARAB_SPEC {
diff --git a/esp32p4/src/i3c_slv/rdatah.rs b/esp32p4/src/i3c_slv/rdatah.rs
index 65feadebed..52db4d65af 100644
--- a/esp32p4/src/i3c_slv/rdatah.rs
+++ b/esp32p4/src/i3c_slv/rdatah.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDATAH")
-            .field("data_lsb", &format_args!("{}", self.data_lsb().bits()))
-            .field("data_msb", &format_args!("{}", self.data_msb().bits()))
+            .field("data_lsb", &self.data_lsb())
+            .field("data_msb", &self.data_msb())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDATAH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read Half-word Data (from-bus) register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdatah::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RDATAH_SPEC;
 impl crate::RegisterSpec for RDATAH_SPEC {
diff --git a/esp32p4/src/i3c_slv/status.rs b/esp32p4/src/i3c_slv/status.rs
index 35b6c8a3fa..6365c84bcc 100644
--- a/esp32p4/src/i3c_slv/status.rs
+++ b/esp32p4/src/i3c_slv/status.rs
@@ -132,31 +132,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("stnotstop", &format_args!("{}", self.stnotstop().bit()))
-            .field("stmsg", &format_args!("{}", self.stmsg().bit()))
-            .field("stccch", &format_args!("{}", self.stccch().bit()))
-            .field("streqrd", &format_args!("{}", self.streqrd().bit()))
-            .field("streqwr", &format_args!("{}", self.streqwr().bit()))
-            .field("stdaa", &format_args!("{}", self.stdaa().bit()))
-            .field("sthdr", &format_args!("{}", self.sthdr().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("matched", &format_args!("{}", self.matched().bit()))
-            .field("stop", &format_args!("{}", self.stop().bit()))
-            .field("rxpend", &format_args!("{}", self.rxpend().bit()))
-            .field("txnotfull", &format_args!("{}", self.txnotfull().bit()))
-            .field("dachg", &format_args!("{}", self.dachg().bit()))
-            .field("ccc", &format_args!("{}", self.ccc().bit()))
-            .field("errwarn", &format_args!("{}", self.errwarn().bit()))
-            .field("hdrmatch", &format_args!("{}", self.hdrmatch().bit()))
+            .field("stnotstop", &self.stnotstop())
+            .field("stmsg", &self.stmsg())
+            .field("stccch", &self.stccch())
+            .field("streqrd", &self.streqrd())
+            .field("streqwr", &self.streqwr())
+            .field("stdaa", &self.stdaa())
+            .field("sthdr", &self.sthdr())
+            .field("start", &self.start())
+            .field("matched", &self.matched())
+            .field("stop", &self.stop())
+            .field("rxpend", &self.rxpend())
+            .field("txnotfull", &self.txnotfull())
+            .field("dachg", &self.dachg())
+            .field("ccc", &self.ccc())
+            .field("errwarn", &self.errwarn())
+            .field("hdrmatch", &self.hdrmatch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/i3c_slv/vendorid.rs b/esp32p4/src/i3c_slv/vendorid.rs
index 5b59810687..8e87ebe4be 100644
--- a/esp32p4/src/i3c_slv/vendorid.rs
+++ b/esp32p4/src/i3c_slv/vendorid.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VENDORID")
-            .field("vid", &format_args!("{}", self.vid().bits()))
+            .field("vid", &self.vid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VENDORID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/adc_int_map.rs b/esp32p4/src/interrupt_core0/adc_int_map.rs
index d0366a893b..17d25950c1 100644
--- a/esp32p4/src/interrupt_core0/adc_int_map.rs
+++ b/esp32p4/src/interrupt_core0/adc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADC_INT_MAP")
-            .field(
-                "core0_adc_int_map",
-                &format_args!("{}", self.core0_adc_int_map().bits()),
-            )
+            .field("core0_adc_int_map", &self.core0_adc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/aes_int_map.rs b/esp32p4/src/interrupt_core0/aes_int_map.rs
index b85e6a2ec4..90c866fb57 100644
--- a/esp32p4/src/interrupt_core0/aes_int_map.rs
+++ b/esp32p4/src/interrupt_core0/aes_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AES_INT_MAP")
-            .field(
-                "core0_aes_int_map",
-                &format_args!("{}", self.core0_aes_int_map().bits()),
-            )
+            .field("core0_aes_int_map", &self.core0_aes_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AES_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/ahb_pdma_in_ch0_int_map.rs b/esp32p4/src/interrupt_core0/ahb_pdma_in_ch0_int_map.rs
index 99a30dda4c..31d95c8681 100644
--- a/esp32p4/src/interrupt_core0/ahb_pdma_in_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/ahb_pdma_in_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHB_PDMA_IN_CH0_INT_MAP")
             .field(
                 "core0_ahb_pdma_in_ch0_int_map",
-                &format_args!("{}", self.core0_ahb_pdma_in_ch0_int_map().bits()),
+                &self.core0_ahb_pdma_in_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_PDMA_IN_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/ahb_pdma_in_ch1_int_map.rs b/esp32p4/src/interrupt_core0/ahb_pdma_in_ch1_int_map.rs
index 9144f90036..c0d488c7c2 100644
--- a/esp32p4/src/interrupt_core0/ahb_pdma_in_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/ahb_pdma_in_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHB_PDMA_IN_CH1_INT_MAP")
             .field(
                 "core0_ahb_pdma_in_ch1_int_map",
-                &format_args!("{}", self.core0_ahb_pdma_in_ch1_int_map().bits()),
+                &self.core0_ahb_pdma_in_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_PDMA_IN_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/ahb_pdma_in_ch2_int_map.rs b/esp32p4/src/interrupt_core0/ahb_pdma_in_ch2_int_map.rs
index acdd287539..8625a0e5c6 100644
--- a/esp32p4/src/interrupt_core0/ahb_pdma_in_ch2_int_map.rs
+++ b/esp32p4/src/interrupt_core0/ahb_pdma_in_ch2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHB_PDMA_IN_CH2_INT_MAP")
             .field(
                 "core0_ahb_pdma_in_ch2_int_map",
-                &format_args!("{}", self.core0_ahb_pdma_in_ch2_int_map().bits()),
+                &self.core0_ahb_pdma_in_ch2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_PDMA_IN_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/ahb_pdma_out_ch0_int_map.rs b/esp32p4/src/interrupt_core0/ahb_pdma_out_ch0_int_map.rs
index 9d7a57b086..aba00806b4 100644
--- a/esp32p4/src/interrupt_core0/ahb_pdma_out_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/ahb_pdma_out_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHB_PDMA_OUT_CH0_INT_MAP")
             .field(
                 "core0_ahb_pdma_out_ch0_int_map",
-                &format_args!("{}", self.core0_ahb_pdma_out_ch0_int_map().bits()),
+                &self.core0_ahb_pdma_out_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_PDMA_OUT_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/ahb_pdma_out_ch1_int_map.rs b/esp32p4/src/interrupt_core0/ahb_pdma_out_ch1_int_map.rs
index 8dba11a48a..945fa6ddb2 100644
--- a/esp32p4/src/interrupt_core0/ahb_pdma_out_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/ahb_pdma_out_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHB_PDMA_OUT_CH1_INT_MAP")
             .field(
                 "core0_ahb_pdma_out_ch1_int_map",
-                &format_args!("{}", self.core0_ahb_pdma_out_ch1_int_map().bits()),
+                &self.core0_ahb_pdma_out_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_PDMA_OUT_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/ahb_pdma_out_ch2_int_map.rs b/esp32p4/src/interrupt_core0/ahb_pdma_out_ch2_int_map.rs
index ee3dc3ab41..47a46f13e7 100644
--- a/esp32p4/src/interrupt_core0/ahb_pdma_out_ch2_int_map.rs
+++ b/esp32p4/src/interrupt_core0/ahb_pdma_out_ch2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHB_PDMA_OUT_CH2_INT_MAP")
             .field(
                 "core0_ahb_pdma_out_ch2_int_map",
-                &format_args!("{}", self.core0_ahb_pdma_out_ch2_int_map().bits()),
+                &self.core0_ahb_pdma_out_ch2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_PDMA_OUT_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/assist_debug_int_map.rs b/esp32p4/src/interrupt_core0/assist_debug_int_map.rs
index 61f289effb..af25938d0d 100644
--- a/esp32p4/src/interrupt_core0/assist_debug_int_map.rs
+++ b/esp32p4/src/interrupt_core0/assist_debug_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ASSIST_DEBUG_INT_MAP")
             .field(
                 "core0_assist_debug_int_map",
-                &format_args!("{}", self.core0_assist_debug_int_map().bits()),
+                &self.core0_assist_debug_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ASSIST_DEBUG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/axi_pdma_in_ch0_int_map.rs b/esp32p4/src/interrupt_core0/axi_pdma_in_ch0_int_map.rs
index 078c501de2..602f9f37aa 100644
--- a/esp32p4/src/interrupt_core0/axi_pdma_in_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/axi_pdma_in_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AXI_PDMA_IN_CH0_INT_MAP")
             .field(
                 "core0_axi_pdma_in_ch0_int_map",
-                &format_args!("{}", self.core0_axi_pdma_in_ch0_int_map().bits()),
+                &self.core0_axi_pdma_in_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_PDMA_IN_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/axi_pdma_in_ch1_int_map.rs b/esp32p4/src/interrupt_core0/axi_pdma_in_ch1_int_map.rs
index c9b3c2407b..06e734d3a3 100644
--- a/esp32p4/src/interrupt_core0/axi_pdma_in_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/axi_pdma_in_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AXI_PDMA_IN_CH1_INT_MAP")
             .field(
                 "core0_axi_pdma_in_ch1_int_map",
-                &format_args!("{}", self.core0_axi_pdma_in_ch1_int_map().bits()),
+                &self.core0_axi_pdma_in_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_PDMA_IN_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/axi_pdma_in_ch2_int_map.rs b/esp32p4/src/interrupt_core0/axi_pdma_in_ch2_int_map.rs
index 5c8f1b6374..0adc61ec9a 100644
--- a/esp32p4/src/interrupt_core0/axi_pdma_in_ch2_int_map.rs
+++ b/esp32p4/src/interrupt_core0/axi_pdma_in_ch2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AXI_PDMA_IN_CH2_INT_MAP")
             .field(
                 "core0_axi_pdma_in_ch2_int_map",
-                &format_args!("{}", self.core0_axi_pdma_in_ch2_int_map().bits()),
+                &self.core0_axi_pdma_in_ch2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_PDMA_IN_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/axi_pdma_out_ch0_int_map.rs b/esp32p4/src/interrupt_core0/axi_pdma_out_ch0_int_map.rs
index 971e3f5952..6e00fdec23 100644
--- a/esp32p4/src/interrupt_core0/axi_pdma_out_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/axi_pdma_out_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AXI_PDMA_OUT_CH0_INT_MAP")
             .field(
                 "core0_axi_pdma_out_ch0_int_map",
-                &format_args!("{}", self.core0_axi_pdma_out_ch0_int_map().bits()),
+                &self.core0_axi_pdma_out_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_PDMA_OUT_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/axi_pdma_out_ch1_int_map.rs b/esp32p4/src/interrupt_core0/axi_pdma_out_ch1_int_map.rs
index 2615ca37ba..315c8e85fa 100644
--- a/esp32p4/src/interrupt_core0/axi_pdma_out_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/axi_pdma_out_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AXI_PDMA_OUT_CH1_INT_MAP")
             .field(
                 "core0_axi_pdma_out_ch1_int_map",
-                &format_args!("{}", self.core0_axi_pdma_out_ch1_int_map().bits()),
+                &self.core0_axi_pdma_out_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_PDMA_OUT_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/axi_pdma_out_ch2_int_map.rs b/esp32p4/src/interrupt_core0/axi_pdma_out_ch2_int_map.rs
index 1b60037c1a..a226662b23 100644
--- a/esp32p4/src/interrupt_core0/axi_pdma_out_ch2_int_map.rs
+++ b/esp32p4/src/interrupt_core0/axi_pdma_out_ch2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AXI_PDMA_OUT_CH2_INT_MAP")
             .field(
                 "core0_axi_pdma_out_ch2_int_map",
-                &format_args!("{}", self.core0_axi_pdma_out_ch2_int_map().bits()),
+                &self.core0_axi_pdma_out_ch2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_PDMA_OUT_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/cache_int_map.rs b/esp32p4/src/interrupt_core0/cache_int_map.rs
index 020a6db8fa..2754118cb6 100644
--- a/esp32p4/src/interrupt_core0/cache_int_map.rs
+++ b/esp32p4/src/interrupt_core0/cache_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_INT_MAP")
-            .field(
-                "core0_cache_int_map",
-                &format_args!("{}", self.core0_cache_int_map().bits()),
-            )
+            .field("core0_cache_int_map", &self.core0_cache_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/can0_int_map.rs b/esp32p4/src/interrupt_core0/can0_int_map.rs
index 2ea127f249..e970642619 100644
--- a/esp32p4/src/interrupt_core0/can0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/can0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAN0_INT_MAP")
-            .field(
-                "core0_can0_int_map",
-                &format_args!("{}", self.core0_can0_int_map().bits()),
-            )
+            .field("core0_can0_int_map", &self.core0_can0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAN0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/can1_int_map.rs b/esp32p4/src/interrupt_core0/can1_int_map.rs
index d6dc48ac09..1db1a86ad0 100644
--- a/esp32p4/src/interrupt_core0/can1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/can1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAN1_INT_MAP")
-            .field(
-                "core0_can1_int_map",
-                &format_args!("{}", self.core0_can1_int_map().bits()),
-            )
+            .field("core0_can1_int_map", &self.core0_can1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAN1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/can2_int_map.rs b/esp32p4/src/interrupt_core0/can2_int_map.rs
index 0239d4dc3a..be2b4738ce 100644
--- a/esp32p4/src/interrupt_core0/can2_int_map.rs
+++ b/esp32p4/src/interrupt_core0/can2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAN2_INT_MAP")
-            .field(
-                "core0_can2_int_map",
-                &format_args!("{}", self.core0_can2_int_map().bits()),
-            )
+            .field("core0_can2_int_map", &self.core0_can2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAN2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/clock_gate.rs b/esp32p4/src/interrupt_core0/clock_gate.rs
index 69ad940b8e..326b65c336 100644
--- a/esp32p4/src/interrupt_core0/clock_gate.rs
+++ b/esp32p4/src/interrupt_core0/clock_gate.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field(
-                "core0_reg_clk_en",
-                &format_args!("{}", self.core0_reg_clk_en().bit()),
-            )
+            .field("core0_reg_clk_en", &self.core0_reg_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/core0_trace_int_map.rs b/esp32p4/src/interrupt_core0/core0_trace_int_map.rs
index e42c34e031..8bdec4be93 100644
--- a/esp32p4/src/interrupt_core0/core0_trace_int_map.rs
+++ b/esp32p4/src/interrupt_core0/core0_trace_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE0_TRACE_INT_MAP")
             .field(
                 "core0_core0_trace_int_map",
-                &format_args!("{}", self.core0_core0_trace_int_map().bits()),
+                &self.core0_core0_trace_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_TRACE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/core1_trace_int_map.rs b/esp32p4/src/interrupt_core0/core1_trace_int_map.rs
index 8dac135826..e856c3070a 100644
--- a/esp32p4/src/interrupt_core0/core1_trace_int_map.rs
+++ b/esp32p4/src/interrupt_core0/core1_trace_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE1_TRACE_INT_MAP")
             .field(
                 "core0_core1_trace_int_map",
-                &format_args!("{}", self.core0_core1_trace_int_map().bits()),
+                &self.core0_core1_trace_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE1_TRACE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/cpu_int_from_cpu_0_map.rs b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_0_map.rs
index 6993d7e8ef..53d821c670 100644
--- a/esp32p4/src/interrupt_core0/cpu_int_from_cpu_0_map.rs
+++ b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_0_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CPU_INT_FROM_CPU_0_MAP")
             .field(
                 "core0_cpu_int_from_cpu_0_map",
-                &format_args!("{}", self.core0_cpu_int_from_cpu_0_map().bits()),
+                &self.core0_cpu_int_from_cpu_0_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_FROM_CPU_0_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/cpu_int_from_cpu_1_map.rs b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_1_map.rs
index 2c36c87a8f..8a8f6aa784 100644
--- a/esp32p4/src/interrupt_core0/cpu_int_from_cpu_1_map.rs
+++ b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_1_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CPU_INT_FROM_CPU_1_MAP")
             .field(
                 "core0_cpu_int_from_cpu_1_map",
-                &format_args!("{}", self.core0_cpu_int_from_cpu_1_map().bits()),
+                &self.core0_cpu_int_from_cpu_1_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_FROM_CPU_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/cpu_int_from_cpu_2_map.rs b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_2_map.rs
index 378dee19ff..915afa392c 100644
--- a/esp32p4/src/interrupt_core0/cpu_int_from_cpu_2_map.rs
+++ b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_2_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CPU_INT_FROM_CPU_2_MAP")
             .field(
                 "core0_cpu_int_from_cpu_2_map",
-                &format_args!("{}", self.core0_cpu_int_from_cpu_2_map().bits()),
+                &self.core0_cpu_int_from_cpu_2_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_FROM_CPU_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/cpu_int_from_cpu_3_map.rs b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_3_map.rs
index 6a6de5dd9c..ef657c076e 100644
--- a/esp32p4/src/interrupt_core0/cpu_int_from_cpu_3_map.rs
+++ b/esp32p4/src/interrupt_core0/cpu_int_from_cpu_3_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CPU_INT_FROM_CPU_3_MAP")
             .field(
                 "core0_cpu_int_from_cpu_3_map",
-                &format_args!("{}", self.core0_cpu_int_from_cpu_3_map().bits()),
+                &self.core0_cpu_int_from_cpu_3_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_FROM_CPU_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/csi_bridge_int_map.rs b/esp32p4/src/interrupt_core0/csi_bridge_int_map.rs
index e27983f283..c1747cc6ba 100644
--- a/esp32p4/src/interrupt_core0/csi_bridge_int_map.rs
+++ b/esp32p4/src/interrupt_core0/csi_bridge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CSI_BRIDGE_INT_MAP")
-            .field(
-                "core0_csi_bridge_int_map",
-                &format_args!("{}", self.core0_csi_bridge_int_map().bits()),
-            )
+            .field("core0_csi_bridge_int_map", &self.core0_csi_bridge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CSI_BRIDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/csi_int_map.rs b/esp32p4/src/interrupt_core0/csi_int_map.rs
index f36247e9e6..35ff0f50dd 100644
--- a/esp32p4/src/interrupt_core0/csi_int_map.rs
+++ b/esp32p4/src/interrupt_core0/csi_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CSI_INT_MAP")
-            .field(
-                "core0_csi_int_map",
-                &format_args!("{}", self.core0_csi_int_map().bits()),
-            )
+            .field("core0_csi_int_map", &self.core0_csi_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CSI_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/dma2d_in_ch0_int_map.rs b/esp32p4/src/interrupt_core0/dma2d_in_ch0_int_map.rs
index 51b84a218f..3790694339 100644
--- a/esp32p4/src/interrupt_core0/dma2d_in_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/dma2d_in_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA2D_IN_CH0_INT_MAP")
             .field(
                 "core0_dma2d_in_ch0_int_map",
-                &format_args!("{}", self.core0_dma2d_in_ch0_int_map().bits()),
+                &self.core0_dma2d_in_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA2D_IN_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/dma2d_in_ch1_int_map.rs b/esp32p4/src/interrupt_core0/dma2d_in_ch1_int_map.rs
index 6ec3d4a34d..5c2d179026 100644
--- a/esp32p4/src/interrupt_core0/dma2d_in_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/dma2d_in_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA2D_IN_CH1_INT_MAP")
             .field(
                 "core0_dma2d_in_ch1_int_map",
-                &format_args!("{}", self.core0_dma2d_in_ch1_int_map().bits()),
+                &self.core0_dma2d_in_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA2D_IN_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/dma2d_out_ch0_int_map.rs b/esp32p4/src/interrupt_core0/dma2d_out_ch0_int_map.rs
index 01e91528db..ab8b32a869 100644
--- a/esp32p4/src/interrupt_core0/dma2d_out_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/dma2d_out_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA2D_OUT_CH0_INT_MAP")
             .field(
                 "core0_dma2d_out_ch0_int_map",
-                &format_args!("{}", self.core0_dma2d_out_ch0_int_map().bits()),
+                &self.core0_dma2d_out_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA2D_OUT_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/dma2d_out_ch1_int_map.rs b/esp32p4/src/interrupt_core0/dma2d_out_ch1_int_map.rs
index 3dcc061cae..bdae60975a 100644
--- a/esp32p4/src/interrupt_core0/dma2d_out_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/dma2d_out_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA2D_OUT_CH1_INT_MAP")
             .field(
                 "core0_dma2d_out_ch1_int_map",
-                &format_args!("{}", self.core0_dma2d_out_ch1_int_map().bits()),
+                &self.core0_dma2d_out_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA2D_OUT_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/dma2d_out_ch2_int_map.rs b/esp32p4/src/interrupt_core0/dma2d_out_ch2_int_map.rs
index 3d109fd6ca..7845deec53 100644
--- a/esp32p4/src/interrupt_core0/dma2d_out_ch2_int_map.rs
+++ b/esp32p4/src/interrupt_core0/dma2d_out_ch2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA2D_OUT_CH2_INT_MAP")
             .field(
                 "core0_dma2d_out_ch2_int_map",
-                &format_args!("{}", self.core0_dma2d_out_ch2_int_map().bits()),
+                &self.core0_dma2d_out_ch2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA2D_OUT_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/dsi_bridge_int_map.rs b/esp32p4/src/interrupt_core0/dsi_bridge_int_map.rs
index 3cb7940368..273b96f80c 100644
--- a/esp32p4/src/interrupt_core0/dsi_bridge_int_map.rs
+++ b/esp32p4/src/interrupt_core0/dsi_bridge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSI_BRIDGE_INT_MAP")
-            .field(
-                "core0_dsi_bridge_int_map",
-                &format_args!("{}", self.core0_dsi_bridge_int_map().bits()),
-            )
+            .field("core0_dsi_bridge_int_map", &self.core0_dsi_bridge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSI_BRIDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/dsi_int_map.rs b/esp32p4/src/interrupt_core0/dsi_int_map.rs
index b0c54c214b..905f659875 100644
--- a/esp32p4/src/interrupt_core0/dsi_int_map.rs
+++ b/esp32p4/src/interrupt_core0/dsi_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSI_INT_MAP")
-            .field(
-                "core0_dsi_int_map",
-                &format_args!("{}", self.core0_dsi_int_map().bits()),
-            )
+            .field("core0_dsi_int_map", &self.core0_dsi_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSI_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/ecc_int_map.rs b/esp32p4/src/interrupt_core0/ecc_int_map.rs
index eb912a1e0c..4dd48b24bb 100644
--- a/esp32p4/src/interrupt_core0/ecc_int_map.rs
+++ b/esp32p4/src/interrupt_core0/ecc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_INT_MAP")
-            .field(
-                "core0_ecc_int_map",
-                &format_args!("{}", self.core0_ecc_int_map().bits()),
-            )
+            .field("core0_ecc_int_map", &self.core0_ecc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/ecdsa_int_map.rs b/esp32p4/src/interrupt_core0/ecdsa_int_map.rs
index 61543d1356..02f734f930 100644
--- a/esp32p4/src/interrupt_core0/ecdsa_int_map.rs
+++ b/esp32p4/src/interrupt_core0/ecdsa_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECDSA_INT_MAP")
-            .field(
-                "core0_ecdsa_int_map",
-                &format_args!("{}", self.core0_ecdsa_int_map().bits()),
-            )
+            .field("core0_ecdsa_int_map", &self.core0_ecdsa_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECDSA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/flash_mspi_int_map.rs b/esp32p4/src/interrupt_core0/flash_mspi_int_map.rs
index 0a59c1c9d5..24e05b20a7 100644
--- a/esp32p4/src/interrupt_core0/flash_mspi_int_map.rs
+++ b/esp32p4/src/interrupt_core0/flash_mspi_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_MSPI_INT_MAP")
-            .field(
-                "core0_flash_mspi_int_map",
-                &format_args!("{}", self.core0_flash_mspi_int_map().bits()),
-            )
+            .field("core0_flash_mspi_int_map", &self.core0_flash_mspi_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_MSPI_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/gdma_int_map.rs b/esp32p4/src/interrupt_core0/gdma_int_map.rs
index 998afcb0c1..3945fc3313 100644
--- a/esp32p4/src/interrupt_core0/gdma_int_map.rs
+++ b/esp32p4/src/interrupt_core0/gdma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GDMA_INT_MAP")
-            .field(
-                "core0_gdma_int_map",
-                &format_args!("{}", self.core0_gdma_int_map().bits()),
-            )
+            .field("core0_gdma_int_map", &self.core0_gdma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GDMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/gmii_phy_int_map.rs b/esp32p4/src/interrupt_core0/gmii_phy_int_map.rs
index 0a0e9a7930..f372e2ad69 100644
--- a/esp32p4/src/interrupt_core0/gmii_phy_int_map.rs
+++ b/esp32p4/src/interrupt_core0/gmii_phy_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GMII_PHY_INT_MAP")
-            .field(
-                "core0_gmii_phy_int_map",
-                &format_args!("{}", self.core0_gmii_phy_int_map().bits()),
-            )
+            .field("core0_gmii_phy_int_map", &self.core0_gmii_phy_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GMII_PHY_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/gpio_int0_map.rs b/esp32p4/src/interrupt_core0/gpio_int0_map.rs
index ac371627ff..481f144b7e 100644
--- a/esp32p4/src/interrupt_core0/gpio_int0_map.rs
+++ b/esp32p4/src/interrupt_core0/gpio_int0_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INT0_MAP")
-            .field(
-                "core0_gpio_int0_map",
-                &format_args!("{}", self.core0_gpio_int0_map().bits()),
-            )
+            .field("core0_gpio_int0_map", &self.core0_gpio_int0_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INT0_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/gpio_int1_map.rs b/esp32p4/src/interrupt_core0/gpio_int1_map.rs
index d2c828aa93..413743ea46 100644
--- a/esp32p4/src/interrupt_core0/gpio_int1_map.rs
+++ b/esp32p4/src/interrupt_core0/gpio_int1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INT1_MAP")
-            .field(
-                "core0_gpio_int1_map",
-                &format_args!("{}", self.core0_gpio_int1_map().bits()),
-            )
+            .field("core0_gpio_int1_map", &self.core0_gpio_int1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INT1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/gpio_int2_map.rs b/esp32p4/src/interrupt_core0/gpio_int2_map.rs
index 29ef63059e..babb19fff1 100644
--- a/esp32p4/src/interrupt_core0/gpio_int2_map.rs
+++ b/esp32p4/src/interrupt_core0/gpio_int2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INT2_MAP")
-            .field(
-                "core0_gpio_int2_map",
-                &format_args!("{}", self.core0_gpio_int2_map().bits()),
-            )
+            .field("core0_gpio_int2_map", &self.core0_gpio_int2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INT2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/gpio_int3_map.rs b/esp32p4/src/interrupt_core0/gpio_int3_map.rs
index 1b0005a16e..56a4f990fc 100644
--- a/esp32p4/src/interrupt_core0/gpio_int3_map.rs
+++ b/esp32p4/src/interrupt_core0/gpio_int3_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INT3_MAP")
-            .field(
-                "core0_gpio_int3_map",
-                &format_args!("{}", self.core0_gpio_int3_map().bits()),
-            )
+            .field("core0_gpio_int3_map", &self.core0_gpio_int3_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INT3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/gpio_pad_comp_int_map.rs b/esp32p4/src/interrupt_core0/gpio_pad_comp_int_map.rs
index b91a6f4f00..e792cc6ce1 100644
--- a/esp32p4/src/interrupt_core0/gpio_pad_comp_int_map.rs
+++ b/esp32p4/src/interrupt_core0/gpio_pad_comp_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("GPIO_PAD_COMP_INT_MAP")
             .field(
                 "core0_gpio_pad_comp_int_map",
-                &format_args!("{}", self.core0_gpio_pad_comp_int_map().bits()),
+                &self.core0_gpio_pad_comp_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_PAD_COMP_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch0_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch0_int_map.rs
index 8e300aef38..4fa1e420ec 100644
--- a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_IN_CH0_INT_MAP")
             .field(
                 "core0_h264_dma2d_in_ch0_int_map",
-                &format_args!("{}", self.core0_h264_dma2d_in_ch0_int_map().bits()),
+                &self.core0_h264_dma2d_in_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_IN_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch1_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch1_int_map.rs
index 95048ad8d6..1069a114f8 100644
--- a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_IN_CH1_INT_MAP")
             .field(
                 "core0_h264_dma2d_in_ch1_int_map",
-                &format_args!("{}", self.core0_h264_dma2d_in_ch1_int_map().bits()),
+                &self.core0_h264_dma2d_in_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_IN_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch2_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch2_int_map.rs
index 00767eb065..8dc82a9ddd 100644
--- a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch2_int_map.rs
+++ b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_IN_CH2_INT_MAP")
             .field(
                 "core0_h264_dma2d_in_ch2_int_map",
-                &format_args!("{}", self.core0_h264_dma2d_in_ch2_int_map().bits()),
+                &self.core0_h264_dma2d_in_ch2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_IN_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch3_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch3_int_map.rs
index 75f6f04319..e73c328c19 100644
--- a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch3_int_map.rs
+++ b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch3_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_IN_CH3_INT_MAP")
             .field(
                 "core0_h264_dma2d_in_ch3_int_map",
-                &format_args!("{}", self.core0_h264_dma2d_in_ch3_int_map().bits()),
+                &self.core0_h264_dma2d_in_ch3_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_IN_CH3_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch4_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch4_int_map.rs
index c16bf1e604..29f9b3d37e 100644
--- a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch4_int_map.rs
+++ b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch4_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_IN_CH4_INT_MAP")
             .field(
                 "core0_h264_dma2d_in_ch4_int_map",
-                &format_args!("{}", self.core0_h264_dma2d_in_ch4_int_map().bits()),
+                &self.core0_h264_dma2d_in_ch4_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_IN_CH4_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch5_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch5_int_map.rs
index a3e65b425e..40bf68bfe7 100644
--- a/esp32p4/src/interrupt_core0/h264_dma2d_in_ch5_int_map.rs
+++ b/esp32p4/src/interrupt_core0/h264_dma2d_in_ch5_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_IN_CH5_INT_MAP")
             .field(
                 "core0_h264_dma2d_in_ch5_int_map",
-                &format_args!("{}", self.core0_h264_dma2d_in_ch5_int_map().bits()),
+                &self.core0_h264_dma2d_in_ch5_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_IN_CH5_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_out_ch0_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch0_int_map.rs
index ebecfad235..7ba0aef86b 100644
--- a/esp32p4/src/interrupt_core0/h264_dma2d_out_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_OUT_CH0_INT_MAP")
             .field(
                 "core0_h264_dma2d_out_ch0_int_map",
-                &format_args!("{}", self.core0_h264_dma2d_out_ch0_int_map().bits()),
+                &self.core0_h264_dma2d_out_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_OUT_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_out_ch1_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch1_int_map.rs
index 7f07101470..c17d163004 100644
--- a/esp32p4/src/interrupt_core0/h264_dma2d_out_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_OUT_CH1_INT_MAP")
             .field(
                 "core0_h264_dma2d_out_ch1_int_map",
-                &format_args!("{}", self.core0_h264_dma2d_out_ch1_int_map().bits()),
+                &self.core0_h264_dma2d_out_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_OUT_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_out_ch2_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch2_int_map.rs
index 9a4a07206d..f3081bcb48 100644
--- a/esp32p4/src/interrupt_core0/h264_dma2d_out_ch2_int_map.rs
+++ b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_OUT_CH2_INT_MAP")
             .field(
                 "core0_h264_dma2d_out_ch2_int_map",
-                &format_args!("{}", self.core0_h264_dma2d_out_ch2_int_map().bits()),
+                &self.core0_h264_dma2d_out_ch2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_OUT_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_out_ch3_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch3_int_map.rs
index 5347515842..557ab747a2 100644
--- a/esp32p4/src/interrupt_core0/h264_dma2d_out_ch3_int_map.rs
+++ b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch3_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_OUT_CH3_INT_MAP")
             .field(
                 "core0_h264_dma2d_out_ch3_int_map",
-                &format_args!("{}", self.core0_h264_dma2d_out_ch3_int_map().bits()),
+                &self.core0_h264_dma2d_out_ch3_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_OUT_CH3_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/h264_dma2d_out_ch4_int_map.rs b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch4_int_map.rs
index 8027b7bc4e..df48759d8d 100644
--- a/esp32p4/src/interrupt_core0/h264_dma2d_out_ch4_int_map.rs
+++ b/esp32p4/src/interrupt_core0/h264_dma2d_out_ch4_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_OUT_CH4_INT_MAP")
             .field(
                 "core0_h264_dma2d_out_ch4_int_map",
-                &format_args!("{}", self.core0_h264_dma2d_out_ch4_int_map().bits()),
+                &self.core0_h264_dma2d_out_ch4_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_OUT_CH4_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/h264_reg_int_map.rs b/esp32p4/src/interrupt_core0/h264_reg_int_map.rs
index 8b0abbfb51..4ad681dbdc 100644
--- a/esp32p4/src/interrupt_core0/h264_reg_int_map.rs
+++ b/esp32p4/src/interrupt_core0/h264_reg_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("H264_REG_INT_MAP")
-            .field(
-                "core0_h264_reg_int_map",
-                &format_args!("{}", self.core0_h264_reg_int_map().bits()),
-            )
+            .field("core0_h264_reg_int_map", &self.core0_h264_reg_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_REG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/hp_core_ctrl_int_map.rs b/esp32p4/src/interrupt_core0/hp_core_ctrl_int_map.rs
index 858dd3f416..a8f66f3c9c 100644
--- a/esp32p4/src/interrupt_core0/hp_core_ctrl_int_map.rs
+++ b/esp32p4/src/interrupt_core0/hp_core_ctrl_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_CORE_CTRL_INT_MAP")
             .field(
                 "core0_hp_core_ctrl_int_map",
-                &format_args!("{}", self.core0_hp_core_ctrl_int_map().bits()),
+                &self.core0_hp_core_ctrl_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_CORE_CTRL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/hp_parlio_rx_int_map.rs b/esp32p4/src/interrupt_core0/hp_parlio_rx_int_map.rs
index 13cf6c068e..cdef0e04d3 100644
--- a/esp32p4/src/interrupt_core0/hp_parlio_rx_int_map.rs
+++ b/esp32p4/src/interrupt_core0/hp_parlio_rx_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_PARLIO_RX_INT_MAP")
             .field(
                 "core0_hp_parlio_rx_int_map",
-                &format_args!("{}", self.core0_hp_parlio_rx_int_map().bits()),
+                &self.core0_hp_parlio_rx_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_PARLIO_RX_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/hp_parlio_tx_int_map.rs b/esp32p4/src/interrupt_core0/hp_parlio_tx_int_map.rs
index c2c7da5af1..56979a9de1 100644
--- a/esp32p4/src/interrupt_core0/hp_parlio_tx_int_map.rs
+++ b/esp32p4/src/interrupt_core0/hp_parlio_tx_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_PARLIO_TX_INT_MAP")
             .field(
                 "core0_hp_parlio_tx_int_map",
-                &format_args!("{}", self.core0_hp_parlio_tx_int_map().bits()),
+                &self.core0_hp_parlio_tx_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_PARLIO_TX_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/hp_pau_int_map.rs b/esp32p4/src/interrupt_core0/hp_pau_int_map.rs
index 484832bc3c..b160c4b907 100644
--- a/esp32p4/src/interrupt_core0/hp_pau_int_map.rs
+++ b/esp32p4/src/interrupt_core0/hp_pau_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_PAU_INT_MAP")
-            .field(
-                "core0_hp_pau_int_map",
-                &format_args!("{}", self.core0_hp_pau_int_map().bits()),
-            )
+            .field("core0_hp_pau_int_map", &self.core0_hp_pau_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_PAU_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/hp_sysreg_int_map.rs b/esp32p4/src/interrupt_core0/hp_sysreg_int_map.rs
index 4687cb4fea..b98f4dfccd 100644
--- a/esp32p4/src/interrupt_core0/hp_sysreg_int_map.rs
+++ b/esp32p4/src/interrupt_core0/hp_sysreg_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SYSREG_INT_MAP")
-            .field(
-                "core0_hp_sysreg_int_map",
-                &format_args!("{}", self.core0_hp_sysreg_int_map().bits()),
-            )
+            .field("core0_hp_sysreg_int_map", &self.core0_hp_sysreg_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SYSREG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/i2c0_int_map.rs b/esp32p4/src/interrupt_core0/i2c0_int_map.rs
index fa8bb4cf77..e0c2163e49 100644
--- a/esp32p4/src/interrupt_core0/i2c0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/i2c0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C0_INT_MAP")
-            .field(
-                "core0_i2c0_int_map",
-                &format_args!("{}", self.core0_i2c0_int_map().bits()),
-            )
+            .field("core0_i2c0_int_map", &self.core0_i2c0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/i2c1_int_map.rs b/esp32p4/src/interrupt_core0/i2c1_int_map.rs
index 3d55a5dbd5..313eb1c951 100644
--- a/esp32p4/src/interrupt_core0/i2c1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/i2c1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C1_INT_MAP")
-            .field(
-                "core0_i2c1_int_map",
-                &format_args!("{}", self.core0_i2c1_int_map().bits()),
-            )
+            .field("core0_i2c1_int_map", &self.core0_i2c1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/i2s0_int_map.rs b/esp32p4/src/interrupt_core0/i2s0_int_map.rs
index a9057f9ef9..10ad5432f5 100644
--- a/esp32p4/src/interrupt_core0/i2s0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/i2s0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S0_INT_MAP")
-            .field(
-                "core0_i2s0_int_map",
-                &format_args!("{}", self.core0_i2s0_int_map().bits()),
-            )
+            .field("core0_i2s0_int_map", &self.core0_i2s0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/i2s1_int_map.rs b/esp32p4/src/interrupt_core0/i2s1_int_map.rs
index 3222c58838..05bf3d6324 100644
--- a/esp32p4/src/interrupt_core0/i2s1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/i2s1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S1_INT_MAP")
-            .field(
-                "core0_i2s1_int_map",
-                &format_args!("{}", self.core0_i2s1_int_map().bits()),
-            )
+            .field("core0_i2s1_int_map", &self.core0_i2s1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/i2s2_int_map.rs b/esp32p4/src/interrupt_core0/i2s2_int_map.rs
index e924efcda8..ee68933b00 100644
--- a/esp32p4/src/interrupt_core0/i2s2_int_map.rs
+++ b/esp32p4/src/interrupt_core0/i2s2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S2_INT_MAP")
-            .field(
-                "core0_i2s2_int_map",
-                &format_args!("{}", self.core0_i2s2_int_map().bits()),
-            )
+            .field("core0_i2s2_int_map", &self.core0_i2s2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/i3c_mst_int_map.rs b/esp32p4/src/interrupt_core0/i3c_mst_int_map.rs
index 7aaa30711d..74b492dcdb 100644
--- a/esp32p4/src/interrupt_core0/i3c_mst_int_map.rs
+++ b/esp32p4/src/interrupt_core0/i3c_mst_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I3C_MST_INT_MAP")
-            .field(
-                "core0_i3c_mst_int_map",
-                &format_args!("{}", self.core0_i3c_mst_int_map().bits()),
-            )
+            .field("core0_i3c_mst_int_map", &self.core0_i3c_mst_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I3C_MST_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/i3c_slv_int_map.rs b/esp32p4/src/interrupt_core0/i3c_slv_int_map.rs
index 7a50ef3074..6b97b6b778 100644
--- a/esp32p4/src/interrupt_core0/i3c_slv_int_map.rs
+++ b/esp32p4/src/interrupt_core0/i3c_slv_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I3C_SLV_INT_MAP")
-            .field(
-                "core0_i3c_slv_int_map",
-                &format_args!("{}", self.core0_i3c_slv_int_map().bits()),
-            )
+            .field("core0_i3c_slv_int_map", &self.core0_i3c_slv_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I3C_SLV_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/interrupt_reg_date.rs b/esp32p4/src/interrupt_core0/interrupt_reg_date.rs
index d56ef66ec3..f81676c5ec 100644
--- a/esp32p4/src/interrupt_core0/interrupt_reg_date.rs
+++ b/esp32p4/src/interrupt_core0/interrupt_reg_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT_REG_DATE")
-            .field(
-                "core0_interrupt_reg_date",
-                &format_args!("{}", self.core0_interrupt_reg_date().bits()),
-            )
+            .field("core0_interrupt_reg_date", &self.core0_interrupt_reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/intr_status_reg_0.rs b/esp32p4/src/interrupt_core0/intr_status_reg_0.rs
index 0615221b3c..053582054b 100644
--- a/esp32p4/src/interrupt_core0/intr_status_reg_0.rs
+++ b/esp32p4/src/interrupt_core0/intr_status_reg_0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_0")
-            .field(
-                "core0_intr_status_0",
-                &format_args!("{}", self.core0_intr_status_0().bits()),
-            )
+            .field("core0_intr_status_0", &self.core0_intr_status_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_0_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_0_SPEC {
diff --git a/esp32p4/src/interrupt_core0/intr_status_reg_1.rs b/esp32p4/src/interrupt_core0/intr_status_reg_1.rs
index bb7553708c..1879556e75 100644
--- a/esp32p4/src/interrupt_core0/intr_status_reg_1.rs
+++ b/esp32p4/src/interrupt_core0/intr_status_reg_1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_1")
-            .field(
-                "core0_intr_status_1",
-                &format_args!("{}", self.core0_intr_status_1().bits()),
-            )
+            .field("core0_intr_status_1", &self.core0_intr_status_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_1_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_1_SPEC {
diff --git a/esp32p4/src/interrupt_core0/intr_status_reg_2.rs b/esp32p4/src/interrupt_core0/intr_status_reg_2.rs
index da9187d751..98338bc9cf 100644
--- a/esp32p4/src/interrupt_core0/intr_status_reg_2.rs
+++ b/esp32p4/src/interrupt_core0/intr_status_reg_2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_2")
-            .field(
-                "core0_intr_status_2",
-                &format_args!("{}", self.core0_intr_status_2().bits()),
-            )
+            .field("core0_intr_status_2", &self.core0_intr_status_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_2_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_2_SPEC {
diff --git a/esp32p4/src/interrupt_core0/intr_status_reg_3.rs b/esp32p4/src/interrupt_core0/intr_status_reg_3.rs
index 9fede0afdc..f4ca44fa02 100644
--- a/esp32p4/src/interrupt_core0/intr_status_reg_3.rs
+++ b/esp32p4/src/interrupt_core0/intr_status_reg_3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_3")
-            .field(
-                "core0_intr_status_3",
-                &format_args!("{}", self.core0_intr_status_3().bits()),
-            )
+            .field("core0_intr_status_3", &self.core0_intr_status_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_3_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_3_SPEC {
diff --git a/esp32p4/src/interrupt_core0/isp_int_map.rs b/esp32p4/src/interrupt_core0/isp_int_map.rs
index 9910046982..dc7698dd86 100644
--- a/esp32p4/src/interrupt_core0/isp_int_map.rs
+++ b/esp32p4/src/interrupt_core0/isp_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ISP_INT_MAP")
-            .field(
-                "core0_isp_int_map",
-                &format_args!("{}", self.core0_isp_int_map().bits()),
-            )
+            .field("core0_isp_int_map", &self.core0_isp_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ISP_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/jpeg_int_map.rs b/esp32p4/src/interrupt_core0/jpeg_int_map.rs
index 1ce26cc873..c5d074e449 100644
--- a/esp32p4/src/interrupt_core0/jpeg_int_map.rs
+++ b/esp32p4/src/interrupt_core0/jpeg_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("JPEG_INT_MAP")
-            .field(
-                "core0_jpeg_int_map",
-                &format_args!("{}", self.core0_jpeg_int_map().bits()),
-            )
+            .field("core0_jpeg_int_map", &self.core0_jpeg_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<JPEG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/km_int_map.rs b/esp32p4/src/interrupt_core0/km_int_map.rs
index a881e2a2dc..7fe11ca956 100644
--- a/esp32p4/src/interrupt_core0/km_int_map.rs
+++ b/esp32p4/src/interrupt_core0/km_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("KM_INT_MAP")
-            .field(
-                "core0_km_int_map",
-                &format_args!("{}", self.core0_km_int_map().bits()),
-            )
+            .field("core0_km_int_map", &self.core0_km_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<KM_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lcd_cam_int_map.rs b/esp32p4/src/interrupt_core0/lcd_cam_int_map.rs
index b641cba40a..26ee65c059 100644
--- a/esp32p4/src/interrupt_core0/lcd_cam_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lcd_cam_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CAM_INT_MAP")
-            .field(
-                "core0_lcd_cam_int_map",
-                &format_args!("{}", self.core0_lcd_cam_int_map().bits()),
-            )
+            .field("core0_lcd_cam_int_map", &self.core0_lcd_cam_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CAM_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/ledc_int_map.rs b/esp32p4/src/interrupt_core0/ledc_int_map.rs
index 7f1cc71b21..d9790552bf 100644
--- a/esp32p4/src/interrupt_core0/ledc_int_map.rs
+++ b/esp32p4/src/interrupt_core0/ledc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEDC_INT_MAP")
-            .field(
-                "core0_ledc_int_map",
-                &format_args!("{}", self.core0_ledc_int_map().bits()),
-            )
+            .field("core0_ledc_int_map", &self.core0_ledc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEDC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_adc_int_map.rs b/esp32p4/src/interrupt_core0/lp_adc_int_map.rs
index 1aa05a8c21..a8cd12eb8f 100644
--- a/esp32p4/src/interrupt_core0/lp_adc_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_adc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_ADC_INT_MAP")
-            .field(
-                "core0_lp_adc_int_map",
-                &format_args!("{}", self.core0_lp_adc_int_map().bits()),
-            )
+            .field("core0_lp_adc_int_map", &self.core0_lp_adc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_ADC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_anaperi_int_map.rs b/esp32p4/src/interrupt_core0/lp_anaperi_int_map.rs
index 37bd71909b..6240a773f8 100644
--- a/esp32p4/src/interrupt_core0/lp_anaperi_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_anaperi_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_ANAPERI_INT_MAP")
-            .field(
-                "core0_lp_anaperi_int_map",
-                &format_args!("{}", self.core0_lp_anaperi_int_map().bits()),
-            )
+            .field("core0_lp_anaperi_int_map", &self.core0_lp_anaperi_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_ANAPERI_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_efuse_int_map.rs b/esp32p4/src/interrupt_core0/lp_efuse_int_map.rs
index 117bc0958f..be39570bba 100644
--- a/esp32p4/src/interrupt_core0/lp_efuse_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_efuse_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_EFUSE_INT_MAP")
-            .field(
-                "core0_lp_efuse_int_map",
-                &format_args!("{}", self.core0_lp_efuse_int_map().bits()),
-            )
+            .field("core0_lp_efuse_int_map", &self.core0_lp_efuse_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_EFUSE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_gpio_int_map.rs b/esp32p4/src/interrupt_core0/lp_gpio_int_map.rs
index 5ff860bc8f..84f0baf2a4 100644
--- a/esp32p4/src/interrupt_core0/lp_gpio_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_gpio_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_GPIO_INT_MAP")
-            .field(
-                "core0_lp_gpio_int_map",
-                &format_args!("{}", self.core0_lp_gpio_int_map().bits()),
-            )
+            .field("core0_lp_gpio_int_map", &self.core0_lp_gpio_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_GPIO_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_huk_int_map.rs b/esp32p4/src/interrupt_core0/lp_huk_int_map.rs
index c2f60b13b5..452561c157 100644
--- a/esp32p4/src/interrupt_core0/lp_huk_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_huk_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_HUK_INT_MAP")
-            .field(
-                "core0_lp_huk_int_map",
-                &format_args!("{}", self.core0_lp_huk_int_map().bits()),
-            )
+            .field("core0_lp_huk_int_map", &self.core0_lp_huk_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_HUK_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_i2c_int_map.rs b/esp32p4/src/interrupt_core0/lp_i2c_int_map.rs
index ad03b0a810..9be8a36e7e 100644
--- a/esp32p4/src/interrupt_core0/lp_i2c_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_i2c_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_I2C_INT_MAP")
-            .field(
-                "core0_lp_i2c_int_map",
-                &format_args!("{}", self.core0_lp_i2c_int_map().bits()),
-            )
+            .field("core0_lp_i2c_int_map", &self.core0_lp_i2c_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_I2C_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_i2s_int_map.rs b/esp32p4/src/interrupt_core0/lp_i2s_int_map.rs
index 2ab8729d32..a9c72e6389 100644
--- a/esp32p4/src/interrupt_core0/lp_i2s_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_i2s_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_I2S_INT_MAP")
-            .field(
-                "core0_lp_i2s_int_map",
-                &format_args!("{}", self.core0_lp_i2s_int_map().bits()),
-            )
+            .field("core0_lp_i2s_int_map", &self.core0_lp_i2s_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_I2S_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_rtc_int_map.rs b/esp32p4/src/interrupt_core0/lp_rtc_int_map.rs
index 14296157b5..d3c854db17 100644
--- a/esp32p4/src/interrupt_core0/lp_rtc_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_rtc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_RTC_INT_MAP")
-            .field(
-                "core0_lp_rtc_int_map",
-                &format_args!("{}", self.core0_lp_rtc_int_map().bits()),
-            )
+            .field("core0_lp_rtc_int_map", &self.core0_lp_rtc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_RTC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_spi_int_map.rs b/esp32p4/src/interrupt_core0/lp_spi_int_map.rs
index 0e290a2b17..7b6189049e 100644
--- a/esp32p4/src/interrupt_core0/lp_spi_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_spi_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SPI_INT_MAP")
-            .field(
-                "core0_lp_spi_int_map",
-                &format_args!("{}", self.core0_lp_spi_int_map().bits()),
-            )
+            .field("core0_lp_spi_int_map", &self.core0_lp_spi_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SPI_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_sw_int_map.rs b/esp32p4/src/interrupt_core0/lp_sw_int_map.rs
index 4d83cd770b..342754c251 100644
--- a/esp32p4/src/interrupt_core0/lp_sw_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_sw_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SW_INT_MAP")
-            .field(
-                "core0_lp_sw_int_map",
-                &format_args!("{}", self.core0_lp_sw_int_map().bits()),
-            )
+            .field("core0_lp_sw_int_map", &self.core0_lp_sw_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SW_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_sysreg_int_map.rs b/esp32p4/src/interrupt_core0/lp_sysreg_int_map.rs
index 056bf50fee..d0a824dc7f 100644
--- a/esp32p4/src/interrupt_core0/lp_sysreg_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_sysreg_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SYSREG_INT_MAP")
-            .field(
-                "core0_lp_sysreg_int_map",
-                &format_args!("{}", self.core0_lp_sysreg_int_map().bits()),
-            )
+            .field("core0_lp_sysreg_int_map", &self.core0_lp_sysreg_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SYSREG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_timer_reg_0_int_map.rs b/esp32p4/src/interrupt_core0/lp_timer_reg_0_int_map.rs
index e36cf08f62..41d6a883d0 100644
--- a/esp32p4/src/interrupt_core0/lp_timer_reg_0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_timer_reg_0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_TIMER_REG_0_INT_MAP")
             .field(
                 "core0_lp_timer_reg_0_int_map",
-                &format_args!("{}", self.core0_lp_timer_reg_0_int_map().bits()),
+                &self.core0_lp_timer_reg_0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TIMER_REG_0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_timer_reg_1_int_map.rs b/esp32p4/src/interrupt_core0/lp_timer_reg_1_int_map.rs
index f17fc317c3..85316a26e2 100644
--- a/esp32p4/src/interrupt_core0/lp_timer_reg_1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_timer_reg_1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_TIMER_REG_1_INT_MAP")
             .field(
                 "core0_lp_timer_reg_1_int_map",
-                &format_args!("{}", self.core0_lp_timer_reg_1_int_map().bits()),
+                &self.core0_lp_timer_reg_1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TIMER_REG_1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_touch_int_map.rs b/esp32p4/src/interrupt_core0/lp_touch_int_map.rs
index 41246dce00..8ac01ed6e7 100644
--- a/esp32p4/src/interrupt_core0/lp_touch_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_touch_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_TOUCH_INT_MAP")
-            .field(
-                "core0_lp_touch_int_map",
-                &format_args!("{}", self.core0_lp_touch_int_map().bits()),
-            )
+            .field("core0_lp_touch_int_map", &self.core0_lp_touch_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TOUCH_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_tsens_int_map.rs b/esp32p4/src/interrupt_core0/lp_tsens_int_map.rs
index c054222ba9..97b4afb716 100644
--- a/esp32p4/src/interrupt_core0/lp_tsens_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_tsens_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_TSENS_INT_MAP")
-            .field(
-                "core0_lp_tsens_int_map",
-                &format_args!("{}", self.core0_lp_tsens_int_map().bits()),
-            )
+            .field("core0_lp_tsens_int_map", &self.core0_lp_tsens_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TSENS_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_uart_int_map.rs b/esp32p4/src/interrupt_core0/lp_uart_int_map.rs
index 8f8261e684..2b062c00ba 100644
--- a/esp32p4/src/interrupt_core0/lp_uart_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_uart_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_UART_INT_MAP")
-            .field(
-                "core0_lp_uart_int_map",
-                &format_args!("{}", self.core0_lp_uart_int_map().bits()),
-            )
+            .field("core0_lp_uart_int_map", &self.core0_lp_uart_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_UART_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lp_wdt_int_map.rs b/esp32p4/src/interrupt_core0/lp_wdt_int_map.rs
index 88fb719187..e2547eb331 100644
--- a/esp32p4/src/interrupt_core0/lp_wdt_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lp_wdt_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_WDT_INT_MAP")
-            .field(
-                "core0_lp_wdt_int_map",
-                &format_args!("{}", self.core0_lp_wdt_int_map().bits()),
-            )
+            .field("core0_lp_wdt_int_map", &self.core0_lp_wdt_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_WDT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/lpi_int_map.rs b/esp32p4/src/interrupt_core0/lpi_int_map.rs
index 69ecbb88e1..ff64893eba 100644
--- a/esp32p4/src/interrupt_core0/lpi_int_map.rs
+++ b/esp32p4/src/interrupt_core0/lpi_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPI_INT_MAP")
-            .field(
-                "core0_lpi_int_map",
-                &format_args!("{}", self.core0_lpi_int_map().bits()),
-            )
+            .field("core0_lpi_int_map", &self.core0_lpi_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPI_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/mb_hp_int_map.rs b/esp32p4/src/interrupt_core0/mb_hp_int_map.rs
index 695191dba8..2097cbd8d9 100644
--- a/esp32p4/src/interrupt_core0/mb_hp_int_map.rs
+++ b/esp32p4/src/interrupt_core0/mb_hp_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MB_HP_INT_MAP")
-            .field(
-                "core0_mb_hp_int_map",
-                &format_args!("{}", self.core0_mb_hp_int_map().bits()),
-            )
+            .field("core0_mb_hp_int_map", &self.core0_mb_hp_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MB_HP_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/mb_lp_int_map.rs b/esp32p4/src/interrupt_core0/mb_lp_int_map.rs
index 992f304df0..999e99d03a 100644
--- a/esp32p4/src/interrupt_core0/mb_lp_int_map.rs
+++ b/esp32p4/src/interrupt_core0/mb_lp_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MB_LP_INT_MAP")
-            .field(
-                "core0_mb_lp_int_map",
-                &format_args!("{}", self.core0_mb_lp_int_map().bits()),
-            )
+            .field("core0_mb_lp_int_map", &self.core0_mb_lp_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MB_LP_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/pcnt_int_map.rs b/esp32p4/src/interrupt_core0/pcnt_int_map.rs
index 1f8208b88b..f110553c3e 100644
--- a/esp32p4/src/interrupt_core0/pcnt_int_map.rs
+++ b/esp32p4/src/interrupt_core0/pcnt_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCNT_INT_MAP")
-            .field(
-                "core0_pcnt_int_map",
-                &format_args!("{}", self.core0_pcnt_int_map().bits()),
-            )
+            .field("core0_pcnt_int_map", &self.core0_pcnt_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCNT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/pmt_int_map.rs b/esp32p4/src/interrupt_core0/pmt_int_map.rs
index 410db6671f..7511ed7677 100644
--- a/esp32p4/src/interrupt_core0/pmt_int_map.rs
+++ b/esp32p4/src/interrupt_core0/pmt_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMT_INT_MAP")
-            .field(
-                "core0_pmt_int_map",
-                &format_args!("{}", self.core0_pmt_int_map().bits()),
-            )
+            .field("core0_pmt_int_map", &self.core0_pmt_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/pmu_reg_0_int_map.rs b/esp32p4/src/interrupt_core0/pmu_reg_0_int_map.rs
index 53c1ebf813..c309950ffd 100644
--- a/esp32p4/src/interrupt_core0/pmu_reg_0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/pmu_reg_0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMU_REG_0_INT_MAP")
-            .field(
-                "core0_pmu_reg_0_int_map",
-                &format_args!("{}", self.core0_pmu_reg_0_int_map().bits()),
-            )
+            .field("core0_pmu_reg_0_int_map", &self.core0_pmu_reg_0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMU_REG_0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/pmu_reg_1_int_map.rs b/esp32p4/src/interrupt_core0/pmu_reg_1_int_map.rs
index cc0169fffc..49a6d5ffcd 100644
--- a/esp32p4/src/interrupt_core0/pmu_reg_1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/pmu_reg_1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMU_REG_1_INT_MAP")
-            .field(
-                "core0_pmu_reg_1_int_map",
-                &format_args!("{}", self.core0_pmu_reg_1_int_map().bits()),
-            )
+            .field("core0_pmu_reg_1_int_map", &self.core0_pmu_reg_1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMU_REG_1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/ppa_int_map.rs b/esp32p4/src/interrupt_core0/ppa_int_map.rs
index ef312d04a7..172d158914 100644
--- a/esp32p4/src/interrupt_core0/ppa_int_map.rs
+++ b/esp32p4/src/interrupt_core0/ppa_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PPA_INT_MAP")
-            .field(
-                "core0_ppa_int_map",
-                &format_args!("{}", self.core0_ppa_int_map().bits()),
-            )
+            .field("core0_ppa_int_map", &self.core0_ppa_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PPA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/psram_mspi_int_map.rs b/esp32p4/src/interrupt_core0/psram_mspi_int_map.rs
index 0a42443b65..009375da21 100644
--- a/esp32p4/src/interrupt_core0/psram_mspi_int_map.rs
+++ b/esp32p4/src/interrupt_core0/psram_mspi_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PSRAM_MSPI_INT_MAP")
-            .field(
-                "core0_psram_mspi_int_map",
-                &format_args!("{}", self.core0_psram_mspi_int_map().bits()),
-            )
+            .field("core0_psram_mspi_int_map", &self.core0_psram_mspi_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PSRAM_MSPI_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/pwm0_int_map.rs b/esp32p4/src/interrupt_core0/pwm0_int_map.rs
index 8cc6a34b85..2159123b65 100644
--- a/esp32p4/src/interrupt_core0/pwm0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/pwm0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM0_INT_MAP")
-            .field(
-                "core0_pwm0_int_map",
-                &format_args!("{}", self.core0_pwm0_int_map().bits()),
-            )
+            .field("core0_pwm0_int_map", &self.core0_pwm0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/pwm1_int_map.rs b/esp32p4/src/interrupt_core0/pwm1_int_map.rs
index b05654fbdc..3cb2035476 100644
--- a/esp32p4/src/interrupt_core0/pwm1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/pwm1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM1_INT_MAP")
-            .field(
-                "core0_pwm1_int_map",
-                &format_args!("{}", self.core0_pwm1_int_map().bits()),
-            )
+            .field("core0_pwm1_int_map", &self.core0_pwm1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/rmt_int_map.rs b/esp32p4/src/interrupt_core0/rmt_int_map.rs
index b4f1f5019e..0e944242fa 100644
--- a/esp32p4/src/interrupt_core0/rmt_int_map.rs
+++ b/esp32p4/src/interrupt_core0/rmt_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RMT_INT_MAP")
-            .field(
-                "core0_rmt_int_map",
-                &format_args!("{}", self.core0_rmt_int_map().bits()),
-            )
+            .field("core0_rmt_int_map", &self.core0_rmt_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RMT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/rsa_int_map.rs b/esp32p4/src/interrupt_core0/rsa_int_map.rs
index 340cc42ec5..d34946fcf7 100644
--- a/esp32p4/src/interrupt_core0/rsa_int_map.rs
+++ b/esp32p4/src/interrupt_core0/rsa_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_INT_MAP")
-            .field(
-                "core0_rsa_int_map",
-                &format_args!("{}", self.core0_rsa_int_map().bits()),
-            )
+            .field("core0_rsa_int_map", &self.core0_rsa_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/sbd_int_map.rs b/esp32p4/src/interrupt_core0/sbd_int_map.rs
index e1ba66596a..1151481549 100644
--- a/esp32p4/src/interrupt_core0/sbd_int_map.rs
+++ b/esp32p4/src/interrupt_core0/sbd_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SBD_INT_MAP")
-            .field(
-                "core0_sbd_int_map",
-                &format_args!("{}", self.core0_sbd_int_map().bits()),
-            )
+            .field("core0_sbd_int_map", &self.core0_sbd_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SBD_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/sdio_host_int_map.rs b/esp32p4/src/interrupt_core0/sdio_host_int_map.rs
index 52671375e0..b3600949d2 100644
--- a/esp32p4/src/interrupt_core0/sdio_host_int_map.rs
+++ b/esp32p4/src/interrupt_core0/sdio_host_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_HOST_INT_MAP")
-            .field(
-                "core0_sdio_host_int_map",
-                &format_args!("{}", self.core0_sdio_host_int_map().bits()),
-            )
+            .field("core0_sdio_host_int_map", &self.core0_sdio_host_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_HOST_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/sha_int_map.rs b/esp32p4/src/interrupt_core0/sha_int_map.rs
index 1361df3c1f..27f7f64424 100644
--- a/esp32p4/src/interrupt_core0/sha_int_map.rs
+++ b/esp32p4/src/interrupt_core0/sha_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA_INT_MAP")
-            .field(
-                "core0_sha_int_map",
-                &format_args!("{}", self.core0_sha_int_map().bits()),
-            )
+            .field("core0_sha_int_map", &self.core0_sha_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/spi2_int_map.rs b/esp32p4/src/interrupt_core0/spi2_int_map.rs
index a8d8ca6d45..d910e52eaf 100644
--- a/esp32p4/src/interrupt_core0/spi2_int_map.rs
+++ b/esp32p4/src/interrupt_core0/spi2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI2_INT_MAP")
-            .field(
-                "core0_spi2_int_map",
-                &format_args!("{}", self.core0_spi2_int_map().bits()),
-            )
+            .field("core0_spi2_int_map", &self.core0_spi2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/spi3_int_map.rs b/esp32p4/src/interrupt_core0/spi3_int_map.rs
index a7139af8bf..805f65aa3e 100644
--- a/esp32p4/src/interrupt_core0/spi3_int_map.rs
+++ b/esp32p4/src/interrupt_core0/spi3_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI3_INT_MAP")
-            .field(
-                "core0_spi3_int_map",
-                &format_args!("{}", self.core0_spi3_int_map().bits()),
-            )
+            .field("core0_spi3_int_map", &self.core0_spi3_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI3_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/sys_icm_int_map.rs b/esp32p4/src/interrupt_core0/sys_icm_int_map.rs
index c6833a5127..659c9d1c6e 100644
--- a/esp32p4/src/interrupt_core0/sys_icm_int_map.rs
+++ b/esp32p4/src/interrupt_core0/sys_icm_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYS_ICM_INT_MAP")
-            .field(
-                "core0_sys_icm_int_map",
-                &format_args!("{}", self.core0_sys_icm_int_map().bits()),
-            )
+            .field("core0_sys_icm_int_map", &self.core0_sys_icm_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYS_ICM_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/systimer_target0_int_map.rs b/esp32p4/src/interrupt_core0/systimer_target0_int_map.rs
index 9a2180da6e..8b8846e982 100644
--- a/esp32p4/src/interrupt_core0/systimer_target0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/systimer_target0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYSTIMER_TARGET0_INT_MAP")
             .field(
                 "core0_systimer_target0_int_map",
-                &format_args!("{}", self.core0_systimer_target0_int_map().bits()),
+                &self.core0_systimer_target0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/systimer_target1_int_map.rs b/esp32p4/src/interrupt_core0/systimer_target1_int_map.rs
index bc3aea04d7..2973953c88 100644
--- a/esp32p4/src/interrupt_core0/systimer_target1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/systimer_target1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYSTIMER_TARGET1_INT_MAP")
             .field(
                 "core0_systimer_target1_int_map",
-                &format_args!("{}", self.core0_systimer_target1_int_map().bits()),
+                &self.core0_systimer_target1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/systimer_target2_int_map.rs b/esp32p4/src/interrupt_core0/systimer_target2_int_map.rs
index 2f859ea832..e1b7470e93 100644
--- a/esp32p4/src/interrupt_core0/systimer_target2_int_map.rs
+++ b/esp32p4/src/interrupt_core0/systimer_target2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYSTIMER_TARGET2_INT_MAP")
             .field(
                 "core0_systimer_target2_int_map",
-                &format_args!("{}", self.core0_systimer_target2_int_map().bits()),
+                &self.core0_systimer_target2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/timergrp0_t0_int_map.rs b/esp32p4/src/interrupt_core0/timergrp0_t0_int_map.rs
index c09321748f..9cfd8f7383 100644
--- a/esp32p4/src/interrupt_core0/timergrp0_t0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/timergrp0_t0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("TIMERGRP0_T0_INT_MAP")
             .field(
                 "core0_timergrp0_t0_int_map",
-                &format_args!("{}", self.core0_timergrp0_t0_int_map().bits()),
+                &self.core0_timergrp0_t0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGRP0_T0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/timergrp0_t1_int_map.rs b/esp32p4/src/interrupt_core0/timergrp0_t1_int_map.rs
index f604a0ba24..5d37558837 100644
--- a/esp32p4/src/interrupt_core0/timergrp0_t1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/timergrp0_t1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("TIMERGRP0_T1_INT_MAP")
             .field(
                 "core0_timergrp0_t1_int_map",
-                &format_args!("{}", self.core0_timergrp0_t1_int_map().bits()),
+                &self.core0_timergrp0_t1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGRP0_T1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/timergrp0_wdt_int_map.rs b/esp32p4/src/interrupt_core0/timergrp0_wdt_int_map.rs
index 45ec89ea36..eb570c2cb4 100644
--- a/esp32p4/src/interrupt_core0/timergrp0_wdt_int_map.rs
+++ b/esp32p4/src/interrupt_core0/timergrp0_wdt_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("TIMERGRP0_WDT_INT_MAP")
             .field(
                 "core0_timergrp0_wdt_int_map",
-                &format_args!("{}", self.core0_timergrp0_wdt_int_map().bits()),
+                &self.core0_timergrp0_wdt_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGRP0_WDT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/timergrp1_t0_int_map.rs b/esp32p4/src/interrupt_core0/timergrp1_t0_int_map.rs
index 0c6d3220d6..897cfdc67e 100644
--- a/esp32p4/src/interrupt_core0/timergrp1_t0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/timergrp1_t0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("TIMERGRP1_T0_INT_MAP")
             .field(
                 "core0_timergrp1_t0_int_map",
-                &format_args!("{}", self.core0_timergrp1_t0_int_map().bits()),
+                &self.core0_timergrp1_t0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGRP1_T0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/timergrp1_t1_int_map.rs b/esp32p4/src/interrupt_core0/timergrp1_t1_int_map.rs
index 8e75da4358..1cc202274a 100644
--- a/esp32p4/src/interrupt_core0/timergrp1_t1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/timergrp1_t1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("TIMERGRP1_T1_INT_MAP")
             .field(
                 "core0_timergrp1_t1_int_map",
-                &format_args!("{}", self.core0_timergrp1_t1_int_map().bits()),
+                &self.core0_timergrp1_t1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGRP1_T1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/timergrp1_wdt_int_map.rs b/esp32p4/src/interrupt_core0/timergrp1_wdt_int_map.rs
index 10d0656ecc..f5a918cabf 100644
--- a/esp32p4/src/interrupt_core0/timergrp1_wdt_int_map.rs
+++ b/esp32p4/src/interrupt_core0/timergrp1_wdt_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("TIMERGRP1_WDT_INT_MAP")
             .field(
                 "core0_timergrp1_wdt_int_map",
-                &format_args!("{}", self.core0_timergrp1_wdt_int_map().bits()),
+                &self.core0_timergrp1_wdt_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGRP1_WDT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/uart0_int_map.rs b/esp32p4/src/interrupt_core0/uart0_int_map.rs
index 08cc191802..632d8586a7 100644
--- a/esp32p4/src/interrupt_core0/uart0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/uart0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART0_INT_MAP")
-            .field(
-                "core0_uart0_int_map",
-                &format_args!("{}", self.core0_uart0_int_map().bits()),
-            )
+            .field("core0_uart0_int_map", &self.core0_uart0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/uart1_int_map.rs b/esp32p4/src/interrupt_core0/uart1_int_map.rs
index e7de2c0cfa..e63b8082d7 100644
--- a/esp32p4/src/interrupt_core0/uart1_int_map.rs
+++ b/esp32p4/src/interrupt_core0/uart1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART1_INT_MAP")
-            .field(
-                "core0_uart1_int_map",
-                &format_args!("{}", self.core0_uart1_int_map().bits()),
-            )
+            .field("core0_uart1_int_map", &self.core0_uart1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/uart2_int_map.rs b/esp32p4/src/interrupt_core0/uart2_int_map.rs
index a8513fed97..b00be8b162 100644
--- a/esp32p4/src/interrupt_core0/uart2_int_map.rs
+++ b/esp32p4/src/interrupt_core0/uart2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART2_INT_MAP")
-            .field(
-                "core0_uart2_int_map",
-                &format_args!("{}", self.core0_uart2_int_map().bits()),
-            )
+            .field("core0_uart2_int_map", &self.core0_uart2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/uart3_int_map.rs b/esp32p4/src/interrupt_core0/uart3_int_map.rs
index c0b9dfb42a..3c362610af 100644
--- a/esp32p4/src/interrupt_core0/uart3_int_map.rs
+++ b/esp32p4/src/interrupt_core0/uart3_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART3_INT_MAP")
-            .field(
-                "core0_uart3_int_map",
-                &format_args!("{}", self.core0_uart3_int_map().bits()),
-            )
+            .field("core0_uart3_int_map", &self.core0_uart3_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART3_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/uart4_int_map.rs b/esp32p4/src/interrupt_core0/uart4_int_map.rs
index 706f9643b3..80a24004c9 100644
--- a/esp32p4/src/interrupt_core0/uart4_int_map.rs
+++ b/esp32p4/src/interrupt_core0/uart4_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART4_INT_MAP")
-            .field(
-                "core0_uart4_int_map",
-                &format_args!("{}", self.core0_uart4_int_map().bits()),
-            )
+            .field("core0_uart4_int_map", &self.core0_uart4_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART4_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/uhci0_int_map.rs b/esp32p4/src/interrupt_core0/uhci0_int_map.rs
index 0dbce7e0a7..a0a4126a7f 100644
--- a/esp32p4/src/interrupt_core0/uhci0_int_map.rs
+++ b/esp32p4/src/interrupt_core0/uhci0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UHCI0_INT_MAP")
-            .field(
-                "core0_uhci0_int_map",
-                &format_args!("{}", self.core0_uhci0_int_map().bits()),
-            )
+            .field("core0_uhci0_int_map", &self.core0_uhci0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UHCI0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/usb_device_int_map.rs b/esp32p4/src/interrupt_core0/usb_device_int_map.rs
index 0667764101..fc0b99230d 100644
--- a/esp32p4/src/interrupt_core0/usb_device_int_map.rs
+++ b/esp32p4/src/interrupt_core0/usb_device_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_DEVICE_INT_MAP")
-            .field(
-                "core0_usb_device_int_map",
-                &format_args!("{}", self.core0_usb_device_int_map().bits()),
-            )
+            .field("core0_usb_device_int_map", &self.core0_usb_device_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_DEVICE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/usb_otg11_int_map.rs b/esp32p4/src/interrupt_core0/usb_otg11_int_map.rs
index ae672d2a12..7ef3d9fb36 100644
--- a/esp32p4/src/interrupt_core0/usb_otg11_int_map.rs
+++ b/esp32p4/src/interrupt_core0/usb_otg11_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_OTG11_INT_MAP")
-            .field(
-                "core0_usb_otg11_int_map",
-                &format_args!("{}", self.core0_usb_otg11_int_map().bits()),
-            )
+            .field("core0_usb_otg11_int_map", &self.core0_usb_otg11_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_OTG11_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/usb_otg_endp_multi_proc_int_map.rs b/esp32p4/src/interrupt_core0/usb_otg_endp_multi_proc_int_map.rs
index 8f5f21015e..985bc29dcd 100644
--- a/esp32p4/src/interrupt_core0/usb_otg_endp_multi_proc_int_map.rs
+++ b/esp32p4/src/interrupt_core0/usb_otg_endp_multi_proc_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("USB_OTG_ENDP_MULTI_PROC_INT_MAP")
             .field(
                 "core0_usb_otg_endp_multi_proc_int_map",
-                &format_args!("{}", self.core0_usb_otg_endp_multi_proc_int_map().bits()),
+                &self.core0_usb_otg_endp_multi_proc_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_OTG_ENDP_MULTI_PROC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core0/usb_otg_int_map.rs b/esp32p4/src/interrupt_core0/usb_otg_int_map.rs
index 45772b573c..2729ad94e2 100644
--- a/esp32p4/src/interrupt_core0/usb_otg_int_map.rs
+++ b/esp32p4/src/interrupt_core0/usb_otg_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_OTG_INT_MAP")
-            .field(
-                "core0_usb_otg_int_map",
-                &format_args!("{}", self.core0_usb_otg_int_map().bits()),
-            )
+            .field("core0_usb_otg_int_map", &self.core0_usb_otg_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_OTG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/adc_int_map.rs b/esp32p4/src/interrupt_core1/adc_int_map.rs
index e2a8b7f288..cf162b4412 100644
--- a/esp32p4/src/interrupt_core1/adc_int_map.rs
+++ b/esp32p4/src/interrupt_core1/adc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADC_INT_MAP")
-            .field(
-                "core1_adc_int_map",
-                &format_args!("{}", self.core1_adc_int_map().bits()),
-            )
+            .field("core1_adc_int_map", &self.core1_adc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/aes_int_map.rs b/esp32p4/src/interrupt_core1/aes_int_map.rs
index dcf4baa075..77cd19e542 100644
--- a/esp32p4/src/interrupt_core1/aes_int_map.rs
+++ b/esp32p4/src/interrupt_core1/aes_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AES_INT_MAP")
-            .field(
-                "core1_aes_int_map",
-                &format_args!("{}", self.core1_aes_int_map().bits()),
-            )
+            .field("core1_aes_int_map", &self.core1_aes_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AES_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/ahb_pdma_in_ch0_int_map.rs b/esp32p4/src/interrupt_core1/ahb_pdma_in_ch0_int_map.rs
index 3813b393a5..2c80df1704 100644
--- a/esp32p4/src/interrupt_core1/ahb_pdma_in_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/ahb_pdma_in_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHB_PDMA_IN_CH0_INT_MAP")
             .field(
                 "core1_ahb_pdma_in_ch0_int_map",
-                &format_args!("{}", self.core1_ahb_pdma_in_ch0_int_map().bits()),
+                &self.core1_ahb_pdma_in_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_PDMA_IN_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/ahb_pdma_in_ch1_int_map.rs b/esp32p4/src/interrupt_core1/ahb_pdma_in_ch1_int_map.rs
index 686330f0a9..1d142b568a 100644
--- a/esp32p4/src/interrupt_core1/ahb_pdma_in_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/ahb_pdma_in_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHB_PDMA_IN_CH1_INT_MAP")
             .field(
                 "core1_ahb_pdma_in_ch1_int_map",
-                &format_args!("{}", self.core1_ahb_pdma_in_ch1_int_map().bits()),
+                &self.core1_ahb_pdma_in_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_PDMA_IN_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/ahb_pdma_in_ch2_int_map.rs b/esp32p4/src/interrupt_core1/ahb_pdma_in_ch2_int_map.rs
index 8a345f329a..ea3cd05b23 100644
--- a/esp32p4/src/interrupt_core1/ahb_pdma_in_ch2_int_map.rs
+++ b/esp32p4/src/interrupt_core1/ahb_pdma_in_ch2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHB_PDMA_IN_CH2_INT_MAP")
             .field(
                 "core1_ahb_pdma_in_ch2_int_map",
-                &format_args!("{}", self.core1_ahb_pdma_in_ch2_int_map().bits()),
+                &self.core1_ahb_pdma_in_ch2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_PDMA_IN_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/ahb_pdma_out_ch0_int_map.rs b/esp32p4/src/interrupt_core1/ahb_pdma_out_ch0_int_map.rs
index 55d4ff869f..6b7970a577 100644
--- a/esp32p4/src/interrupt_core1/ahb_pdma_out_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/ahb_pdma_out_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHB_PDMA_OUT_CH0_INT_MAP")
             .field(
                 "core1_ahb_pdma_out_ch0_int_map",
-                &format_args!("{}", self.core1_ahb_pdma_out_ch0_int_map().bits()),
+                &self.core1_ahb_pdma_out_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_PDMA_OUT_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/ahb_pdma_out_ch1_int_map.rs b/esp32p4/src/interrupt_core1/ahb_pdma_out_ch1_int_map.rs
index 17ee5f21be..dcb771f38c 100644
--- a/esp32p4/src/interrupt_core1/ahb_pdma_out_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/ahb_pdma_out_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHB_PDMA_OUT_CH1_INT_MAP")
             .field(
                 "core1_ahb_pdma_out_ch1_int_map",
-                &format_args!("{}", self.core1_ahb_pdma_out_ch1_int_map().bits()),
+                &self.core1_ahb_pdma_out_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_PDMA_OUT_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/ahb_pdma_out_ch2_int_map.rs b/esp32p4/src/interrupt_core1/ahb_pdma_out_ch2_int_map.rs
index 73dc8daf59..a98d6f8d5e 100644
--- a/esp32p4/src/interrupt_core1/ahb_pdma_out_ch2_int_map.rs
+++ b/esp32p4/src/interrupt_core1/ahb_pdma_out_ch2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AHB_PDMA_OUT_CH2_INT_MAP")
             .field(
                 "core1_ahb_pdma_out_ch2_int_map",
-                &format_args!("{}", self.core1_ahb_pdma_out_ch2_int_map().bits()),
+                &self.core1_ahb_pdma_out_ch2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_PDMA_OUT_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/assist_debug_int_map.rs b/esp32p4/src/interrupt_core1/assist_debug_int_map.rs
index c7967ea02d..55a344c185 100644
--- a/esp32p4/src/interrupt_core1/assist_debug_int_map.rs
+++ b/esp32p4/src/interrupt_core1/assist_debug_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ASSIST_DEBUG_INT_MAP")
             .field(
                 "core1_assist_debug_int_map",
-                &format_args!("{}", self.core1_assist_debug_int_map().bits()),
+                &self.core1_assist_debug_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ASSIST_DEBUG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/axi_pdma_in_ch0_int_map.rs b/esp32p4/src/interrupt_core1/axi_pdma_in_ch0_int_map.rs
index 4a626e7e35..e751620d6b 100644
--- a/esp32p4/src/interrupt_core1/axi_pdma_in_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/axi_pdma_in_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AXI_PDMA_IN_CH0_INT_MAP")
             .field(
                 "core1_axi_pdma_in_ch0_int_map",
-                &format_args!("{}", self.core1_axi_pdma_in_ch0_int_map().bits()),
+                &self.core1_axi_pdma_in_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_PDMA_IN_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/axi_pdma_in_ch1_int_map.rs b/esp32p4/src/interrupt_core1/axi_pdma_in_ch1_int_map.rs
index 50801b2735..b5e5b0560e 100644
--- a/esp32p4/src/interrupt_core1/axi_pdma_in_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/axi_pdma_in_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AXI_PDMA_IN_CH1_INT_MAP")
             .field(
                 "core1_axi_pdma_in_ch1_int_map",
-                &format_args!("{}", self.core1_axi_pdma_in_ch1_int_map().bits()),
+                &self.core1_axi_pdma_in_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_PDMA_IN_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/axi_pdma_in_ch2_int_map.rs b/esp32p4/src/interrupt_core1/axi_pdma_in_ch2_int_map.rs
index 155d3a89de..67033c8138 100644
--- a/esp32p4/src/interrupt_core1/axi_pdma_in_ch2_int_map.rs
+++ b/esp32p4/src/interrupt_core1/axi_pdma_in_ch2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AXI_PDMA_IN_CH2_INT_MAP")
             .field(
                 "core1_axi_pdma_in_ch2_int_map",
-                &format_args!("{}", self.core1_axi_pdma_in_ch2_int_map().bits()),
+                &self.core1_axi_pdma_in_ch2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_PDMA_IN_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/axi_pdma_out_ch0_int_map.rs b/esp32p4/src/interrupt_core1/axi_pdma_out_ch0_int_map.rs
index afb481f64e..2f150f2849 100644
--- a/esp32p4/src/interrupt_core1/axi_pdma_out_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/axi_pdma_out_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AXI_PDMA_OUT_CH0_INT_MAP")
             .field(
                 "core1_axi_pdma_out_ch0_int_map",
-                &format_args!("{}", self.core1_axi_pdma_out_ch0_int_map().bits()),
+                &self.core1_axi_pdma_out_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_PDMA_OUT_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/axi_pdma_out_ch1_int_map.rs b/esp32p4/src/interrupt_core1/axi_pdma_out_ch1_int_map.rs
index aac42a9945..e8233761d3 100644
--- a/esp32p4/src/interrupt_core1/axi_pdma_out_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/axi_pdma_out_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AXI_PDMA_OUT_CH1_INT_MAP")
             .field(
                 "core1_axi_pdma_out_ch1_int_map",
-                &format_args!("{}", self.core1_axi_pdma_out_ch1_int_map().bits()),
+                &self.core1_axi_pdma_out_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_PDMA_OUT_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/axi_pdma_out_ch2_int_map.rs b/esp32p4/src/interrupt_core1/axi_pdma_out_ch2_int_map.rs
index ce039f5c61..18f418886a 100644
--- a/esp32p4/src/interrupt_core1/axi_pdma_out_ch2_int_map.rs
+++ b/esp32p4/src/interrupt_core1/axi_pdma_out_ch2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AXI_PDMA_OUT_CH2_INT_MAP")
             .field(
                 "core1_axi_pdma_out_ch2_int_map",
-                &format_args!("{}", self.core1_axi_pdma_out_ch2_int_map().bits()),
+                &self.core1_axi_pdma_out_ch2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_PDMA_OUT_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/cache_int_map.rs b/esp32p4/src/interrupt_core1/cache_int_map.rs
index e559d2a844..cb6d528499 100644
--- a/esp32p4/src/interrupt_core1/cache_int_map.rs
+++ b/esp32p4/src/interrupt_core1/cache_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_INT_MAP")
-            .field(
-                "core1_cache_int_map",
-                &format_args!("{}", self.core1_cache_int_map().bits()),
-            )
+            .field("core1_cache_int_map", &self.core1_cache_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/can0_int_map.rs b/esp32p4/src/interrupt_core1/can0_int_map.rs
index 321d6e9fc3..20738006b3 100644
--- a/esp32p4/src/interrupt_core1/can0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/can0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAN0_INT_MAP")
-            .field(
-                "core1_can0_int_map",
-                &format_args!("{}", self.core1_can0_int_map().bits()),
-            )
+            .field("core1_can0_int_map", &self.core1_can0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAN0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/can1_int_map.rs b/esp32p4/src/interrupt_core1/can1_int_map.rs
index 2bb5d116ab..ae6f980062 100644
--- a/esp32p4/src/interrupt_core1/can1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/can1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAN1_INT_MAP")
-            .field(
-                "core1_can1_int_map",
-                &format_args!("{}", self.core1_can1_int_map().bits()),
-            )
+            .field("core1_can1_int_map", &self.core1_can1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAN1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/can2_int_map.rs b/esp32p4/src/interrupt_core1/can2_int_map.rs
index 63e1d00b95..cc8ce476ff 100644
--- a/esp32p4/src/interrupt_core1/can2_int_map.rs
+++ b/esp32p4/src/interrupt_core1/can2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAN2_INT_MAP")
-            .field(
-                "core1_can2_int_map",
-                &format_args!("{}", self.core1_can2_int_map().bits()),
-            )
+            .field("core1_can2_int_map", &self.core1_can2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAN2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/clock_gate.rs b/esp32p4/src/interrupt_core1/clock_gate.rs
index d36459fae4..dfb982fa3b 100644
--- a/esp32p4/src/interrupt_core1/clock_gate.rs
+++ b/esp32p4/src/interrupt_core1/clock_gate.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field(
-                "core1_reg_clk_en",
-                &format_args!("{}", self.core1_reg_clk_en().bit()),
-            )
+            .field("core1_reg_clk_en", &self.core1_reg_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/core0_trace_int_map.rs b/esp32p4/src/interrupt_core1/core0_trace_int_map.rs
index eaa544a970..58f59128d4 100644
--- a/esp32p4/src/interrupt_core1/core0_trace_int_map.rs
+++ b/esp32p4/src/interrupt_core1/core0_trace_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE0_TRACE_INT_MAP")
             .field(
                 "core1_core0_trace_int_map",
-                &format_args!("{}", self.core1_core0_trace_int_map().bits()),
+                &self.core1_core0_trace_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_TRACE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/core1_trace_int_map.rs b/esp32p4/src/interrupt_core1/core1_trace_int_map.rs
index f2cdbdd686..1972912f12 100644
--- a/esp32p4/src/interrupt_core1/core1_trace_int_map.rs
+++ b/esp32p4/src/interrupt_core1/core1_trace_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE1_TRACE_INT_MAP")
             .field(
                 "core1_core1_trace_int_map",
-                &format_args!("{}", self.core1_core1_trace_int_map().bits()),
+                &self.core1_core1_trace_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE1_TRACE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/cpu_int_from_cpu_0_map.rs b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_0_map.rs
index f64c39475e..62f855d1a8 100644
--- a/esp32p4/src/interrupt_core1/cpu_int_from_cpu_0_map.rs
+++ b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_0_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CPU_INT_FROM_CPU_0_MAP")
             .field(
                 "core1_cpu_int_from_cpu_0_map",
-                &format_args!("{}", self.core1_cpu_int_from_cpu_0_map().bits()),
+                &self.core1_cpu_int_from_cpu_0_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_FROM_CPU_0_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/cpu_int_from_cpu_1_map.rs b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_1_map.rs
index ec0374756b..d4bfefaf8e 100644
--- a/esp32p4/src/interrupt_core1/cpu_int_from_cpu_1_map.rs
+++ b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_1_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CPU_INT_FROM_CPU_1_MAP")
             .field(
                 "core1_cpu_int_from_cpu_1_map",
-                &format_args!("{}", self.core1_cpu_int_from_cpu_1_map().bits()),
+                &self.core1_cpu_int_from_cpu_1_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_FROM_CPU_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/cpu_int_from_cpu_2_map.rs b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_2_map.rs
index 674cce8746..570af1ee37 100644
--- a/esp32p4/src/interrupt_core1/cpu_int_from_cpu_2_map.rs
+++ b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_2_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CPU_INT_FROM_CPU_2_MAP")
             .field(
                 "core1_cpu_int_from_cpu_2_map",
-                &format_args!("{}", self.core1_cpu_int_from_cpu_2_map().bits()),
+                &self.core1_cpu_int_from_cpu_2_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_FROM_CPU_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/cpu_int_from_cpu_3_map.rs b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_3_map.rs
index 8ed49c2c38..010880e0b2 100644
--- a/esp32p4/src/interrupt_core1/cpu_int_from_cpu_3_map.rs
+++ b/esp32p4/src/interrupt_core1/cpu_int_from_cpu_3_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CPU_INT_FROM_CPU_3_MAP")
             .field(
                 "core1_cpu_int_from_cpu_3_map",
-                &format_args!("{}", self.core1_cpu_int_from_cpu_3_map().bits()),
+                &self.core1_cpu_int_from_cpu_3_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INT_FROM_CPU_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/csi_bridge_int_map.rs b/esp32p4/src/interrupt_core1/csi_bridge_int_map.rs
index 8dd4010dea..884d6955b8 100644
--- a/esp32p4/src/interrupt_core1/csi_bridge_int_map.rs
+++ b/esp32p4/src/interrupt_core1/csi_bridge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CSI_BRIDGE_INT_MAP")
-            .field(
-                "core1_csi_bridge_int_map",
-                &format_args!("{}", self.core1_csi_bridge_int_map().bits()),
-            )
+            .field("core1_csi_bridge_int_map", &self.core1_csi_bridge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CSI_BRIDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/csi_int_map.rs b/esp32p4/src/interrupt_core1/csi_int_map.rs
index 0e830a4bb9..8c6a227032 100644
--- a/esp32p4/src/interrupt_core1/csi_int_map.rs
+++ b/esp32p4/src/interrupt_core1/csi_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CSI_INT_MAP")
-            .field(
-                "core1_csi_int_map",
-                &format_args!("{}", self.core1_csi_int_map().bits()),
-            )
+            .field("core1_csi_int_map", &self.core1_csi_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CSI_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/dma2d_in_ch0_int_map.rs b/esp32p4/src/interrupt_core1/dma2d_in_ch0_int_map.rs
index 547ccc0850..e6139ad074 100644
--- a/esp32p4/src/interrupt_core1/dma2d_in_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/dma2d_in_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA2D_IN_CH0_INT_MAP")
             .field(
                 "core1_dma2d_in_ch0_int_map",
-                &format_args!("{}", self.core1_dma2d_in_ch0_int_map().bits()),
+                &self.core1_dma2d_in_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA2D_IN_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/dma2d_in_ch1_int_map.rs b/esp32p4/src/interrupt_core1/dma2d_in_ch1_int_map.rs
index 13964de11c..1d8f8476a4 100644
--- a/esp32p4/src/interrupt_core1/dma2d_in_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/dma2d_in_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA2D_IN_CH1_INT_MAP")
             .field(
                 "core1_dma2d_in_ch1_int_map",
-                &format_args!("{}", self.core1_dma2d_in_ch1_int_map().bits()),
+                &self.core1_dma2d_in_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA2D_IN_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/dma2d_out_ch0_int_map.rs b/esp32p4/src/interrupt_core1/dma2d_out_ch0_int_map.rs
index 858ba5eb3d..fd973c8008 100644
--- a/esp32p4/src/interrupt_core1/dma2d_out_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/dma2d_out_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA2D_OUT_CH0_INT_MAP")
             .field(
                 "core1_dma2d_out_ch0_int_map",
-                &format_args!("{}", self.core1_dma2d_out_ch0_int_map().bits()),
+                &self.core1_dma2d_out_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA2D_OUT_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/dma2d_out_ch1_int_map.rs b/esp32p4/src/interrupt_core1/dma2d_out_ch1_int_map.rs
index d936f5c7b3..6a875a8a2a 100644
--- a/esp32p4/src/interrupt_core1/dma2d_out_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/dma2d_out_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA2D_OUT_CH1_INT_MAP")
             .field(
                 "core1_dma2d_out_ch1_int_map",
-                &format_args!("{}", self.core1_dma2d_out_ch1_int_map().bits()),
+                &self.core1_dma2d_out_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA2D_OUT_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/dma2d_out_ch2_int_map.rs b/esp32p4/src/interrupt_core1/dma2d_out_ch2_int_map.rs
index fd8ed276a7..35e0f19b96 100644
--- a/esp32p4/src/interrupt_core1/dma2d_out_ch2_int_map.rs
+++ b/esp32p4/src/interrupt_core1/dma2d_out_ch2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA2D_OUT_CH2_INT_MAP")
             .field(
                 "core1_dma2d_out_ch2_int_map",
-                &format_args!("{}", self.core1_dma2d_out_ch2_int_map().bits()),
+                &self.core1_dma2d_out_ch2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA2D_OUT_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/dsi_bridge_int_map.rs b/esp32p4/src/interrupt_core1/dsi_bridge_int_map.rs
index 8396ae66c4..41af1c08a2 100644
--- a/esp32p4/src/interrupt_core1/dsi_bridge_int_map.rs
+++ b/esp32p4/src/interrupt_core1/dsi_bridge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSI_BRIDGE_INT_MAP")
-            .field(
-                "core1_dsi_bridge_int_map",
-                &format_args!("{}", self.core1_dsi_bridge_int_map().bits()),
-            )
+            .field("core1_dsi_bridge_int_map", &self.core1_dsi_bridge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSI_BRIDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/dsi_int_map.rs b/esp32p4/src/interrupt_core1/dsi_int_map.rs
index a78090c5c6..7a18240e12 100644
--- a/esp32p4/src/interrupt_core1/dsi_int_map.rs
+++ b/esp32p4/src/interrupt_core1/dsi_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSI_INT_MAP")
-            .field(
-                "core1_dsi_int_map",
-                &format_args!("{}", self.core1_dsi_int_map().bits()),
-            )
+            .field("core1_dsi_int_map", &self.core1_dsi_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSI_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/ecc_int_map.rs b/esp32p4/src/interrupt_core1/ecc_int_map.rs
index e5c3635527..05b7be93ac 100644
--- a/esp32p4/src/interrupt_core1/ecc_int_map.rs
+++ b/esp32p4/src/interrupt_core1/ecc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_INT_MAP")
-            .field(
-                "core1_ecc_int_map",
-                &format_args!("{}", self.core1_ecc_int_map().bits()),
-            )
+            .field("core1_ecc_int_map", &self.core1_ecc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/ecdsa_int_map.rs b/esp32p4/src/interrupt_core1/ecdsa_int_map.rs
index 15170f2213..b072b4788f 100644
--- a/esp32p4/src/interrupt_core1/ecdsa_int_map.rs
+++ b/esp32p4/src/interrupt_core1/ecdsa_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECDSA_INT_MAP")
-            .field(
-                "core1_ecdsa_int_map",
-                &format_args!("{}", self.core1_ecdsa_int_map().bits()),
-            )
+            .field("core1_ecdsa_int_map", &self.core1_ecdsa_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECDSA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/flash_mspi_int_map.rs b/esp32p4/src/interrupt_core1/flash_mspi_int_map.rs
index 69cfea7d2a..361b70f88a 100644
--- a/esp32p4/src/interrupt_core1/flash_mspi_int_map.rs
+++ b/esp32p4/src/interrupt_core1/flash_mspi_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_MSPI_INT_MAP")
-            .field(
-                "core1_flash_mspi_int_map",
-                &format_args!("{}", self.core1_flash_mspi_int_map().bits()),
-            )
+            .field("core1_flash_mspi_int_map", &self.core1_flash_mspi_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_MSPI_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/gdma_int_map.rs b/esp32p4/src/interrupt_core1/gdma_int_map.rs
index d0e616c9a9..7d6ada0423 100644
--- a/esp32p4/src/interrupt_core1/gdma_int_map.rs
+++ b/esp32p4/src/interrupt_core1/gdma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GDMA_INT_MAP")
-            .field(
-                "core1_gdma_int_map",
-                &format_args!("{}", self.core1_gdma_int_map().bits()),
-            )
+            .field("core1_gdma_int_map", &self.core1_gdma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GDMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/gmii_phy_int_map.rs b/esp32p4/src/interrupt_core1/gmii_phy_int_map.rs
index 31887a50b2..74ed2a642b 100644
--- a/esp32p4/src/interrupt_core1/gmii_phy_int_map.rs
+++ b/esp32p4/src/interrupt_core1/gmii_phy_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GMII_PHY_INT_MAP")
-            .field(
-                "core1_gmii_phy_int_map",
-                &format_args!("{}", self.core1_gmii_phy_int_map().bits()),
-            )
+            .field("core1_gmii_phy_int_map", &self.core1_gmii_phy_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GMII_PHY_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/gpio_int0_map.rs b/esp32p4/src/interrupt_core1/gpio_int0_map.rs
index 4ae4aa0796..4520be26e8 100644
--- a/esp32p4/src/interrupt_core1/gpio_int0_map.rs
+++ b/esp32p4/src/interrupt_core1/gpio_int0_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INT0_MAP")
-            .field(
-                "core1_gpio_int0_map",
-                &format_args!("{}", self.core1_gpio_int0_map().bits()),
-            )
+            .field("core1_gpio_int0_map", &self.core1_gpio_int0_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INT0_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/gpio_int1_map.rs b/esp32p4/src/interrupt_core1/gpio_int1_map.rs
index 6b16448ee5..e38f052055 100644
--- a/esp32p4/src/interrupt_core1/gpio_int1_map.rs
+++ b/esp32p4/src/interrupt_core1/gpio_int1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INT1_MAP")
-            .field(
-                "core1_gpio_int1_map",
-                &format_args!("{}", self.core1_gpio_int1_map().bits()),
-            )
+            .field("core1_gpio_int1_map", &self.core1_gpio_int1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INT1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/gpio_int2_map.rs b/esp32p4/src/interrupt_core1/gpio_int2_map.rs
index 6947890533..ff0378c68f 100644
--- a/esp32p4/src/interrupt_core1/gpio_int2_map.rs
+++ b/esp32p4/src/interrupt_core1/gpio_int2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INT2_MAP")
-            .field(
-                "core1_gpio_int2_map",
-                &format_args!("{}", self.core1_gpio_int2_map().bits()),
-            )
+            .field("core1_gpio_int2_map", &self.core1_gpio_int2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INT2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/gpio_int3_map.rs b/esp32p4/src/interrupt_core1/gpio_int3_map.rs
index 259b41abec..b70f892f1f 100644
--- a/esp32p4/src/interrupt_core1/gpio_int3_map.rs
+++ b/esp32p4/src/interrupt_core1/gpio_int3_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INT3_MAP")
-            .field(
-                "core1_gpio_int3_map",
-                &format_args!("{}", self.core1_gpio_int3_map().bits()),
-            )
+            .field("core1_gpio_int3_map", &self.core1_gpio_int3_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INT3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/gpio_pad_comp_int_map.rs b/esp32p4/src/interrupt_core1/gpio_pad_comp_int_map.rs
index a56587b02b..7c87adcc67 100644
--- a/esp32p4/src/interrupt_core1/gpio_pad_comp_int_map.rs
+++ b/esp32p4/src/interrupt_core1/gpio_pad_comp_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("GPIO_PAD_COMP_INT_MAP")
             .field(
                 "core1_gpio_pad_comp_int_map",
-                &format_args!("{}", self.core1_gpio_pad_comp_int_map().bits()),
+                &self.core1_gpio_pad_comp_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_PAD_COMP_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch0_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch0_int_map.rs
index acff792af9..bb39ec0f4b 100644
--- a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_IN_CH0_INT_MAP")
             .field(
                 "core1_h264_dma2d_in_ch0_int_map",
-                &format_args!("{}", self.core1_h264_dma2d_in_ch0_int_map().bits()),
+                &self.core1_h264_dma2d_in_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_IN_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch1_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch1_int_map.rs
index 1bf1c7492b..40ee1afac8 100644
--- a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_IN_CH1_INT_MAP")
             .field(
                 "core1_h264_dma2d_in_ch1_int_map",
-                &format_args!("{}", self.core1_h264_dma2d_in_ch1_int_map().bits()),
+                &self.core1_h264_dma2d_in_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_IN_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch2_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch2_int_map.rs
index e2942fe865..682eaf407b 100644
--- a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch2_int_map.rs
+++ b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_IN_CH2_INT_MAP")
             .field(
                 "core1_h264_dma2d_in_ch2_int_map",
-                &format_args!("{}", self.core1_h264_dma2d_in_ch2_int_map().bits()),
+                &self.core1_h264_dma2d_in_ch2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_IN_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch3_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch3_int_map.rs
index 6c8e820674..87dbaff3ab 100644
--- a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch3_int_map.rs
+++ b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch3_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_IN_CH3_INT_MAP")
             .field(
                 "core1_h264_dma2d_in_ch3_int_map",
-                &format_args!("{}", self.core1_h264_dma2d_in_ch3_int_map().bits()),
+                &self.core1_h264_dma2d_in_ch3_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_IN_CH3_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch4_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch4_int_map.rs
index 667c862303..586e2feebd 100644
--- a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch4_int_map.rs
+++ b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch4_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_IN_CH4_INT_MAP")
             .field(
                 "core1_h264_dma2d_in_ch4_int_map",
-                &format_args!("{}", self.core1_h264_dma2d_in_ch4_int_map().bits()),
+                &self.core1_h264_dma2d_in_ch4_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_IN_CH4_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch5_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch5_int_map.rs
index f343f54eda..7cecdc7606 100644
--- a/esp32p4/src/interrupt_core1/h264_dma2d_in_ch5_int_map.rs
+++ b/esp32p4/src/interrupt_core1/h264_dma2d_in_ch5_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_IN_CH5_INT_MAP")
             .field(
                 "core1_h264_dma2d_in_ch5_int_map",
-                &format_args!("{}", self.core1_h264_dma2d_in_ch5_int_map().bits()),
+                &self.core1_h264_dma2d_in_ch5_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_IN_CH5_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_out_ch0_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch0_int_map.rs
index 5a43c8ff03..4bc4e65368 100644
--- a/esp32p4/src/interrupt_core1/h264_dma2d_out_ch0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_OUT_CH0_INT_MAP")
             .field(
                 "core1_h264_dma2d_out_ch0_int_map",
-                &format_args!("{}", self.core1_h264_dma2d_out_ch0_int_map().bits()),
+                &self.core1_h264_dma2d_out_ch0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_OUT_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_out_ch1_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch1_int_map.rs
index 610c60caee..f894988267 100644
--- a/esp32p4/src/interrupt_core1/h264_dma2d_out_ch1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_OUT_CH1_INT_MAP")
             .field(
                 "core1_h264_dma2d_out_ch1_int_map",
-                &format_args!("{}", self.core1_h264_dma2d_out_ch1_int_map().bits()),
+                &self.core1_h264_dma2d_out_ch1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_OUT_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_out_ch2_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch2_int_map.rs
index a42a2a747d..4583135540 100644
--- a/esp32p4/src/interrupt_core1/h264_dma2d_out_ch2_int_map.rs
+++ b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_OUT_CH2_INT_MAP")
             .field(
                 "core1_h264_dma2d_out_ch2_int_map",
-                &format_args!("{}", self.core1_h264_dma2d_out_ch2_int_map().bits()),
+                &self.core1_h264_dma2d_out_ch2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_OUT_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_out_ch3_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch3_int_map.rs
index 74f3822d50..8a8477c1fc 100644
--- a/esp32p4/src/interrupt_core1/h264_dma2d_out_ch3_int_map.rs
+++ b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch3_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_OUT_CH3_INT_MAP")
             .field(
                 "core1_h264_dma2d_out_ch3_int_map",
-                &format_args!("{}", self.core1_h264_dma2d_out_ch3_int_map().bits()),
+                &self.core1_h264_dma2d_out_ch3_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_OUT_CH3_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/h264_dma2d_out_ch4_int_map.rs b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch4_int_map.rs
index 3f036fd986..8830803c51 100644
--- a/esp32p4/src/interrupt_core1/h264_dma2d_out_ch4_int_map.rs
+++ b/esp32p4/src/interrupt_core1/h264_dma2d_out_ch4_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("H264_DMA2D_OUT_CH4_INT_MAP")
             .field(
                 "core1_h264_dma2d_out_ch4_int_map",
-                &format_args!("{}", self.core1_h264_dma2d_out_ch4_int_map().bits()),
+                &self.core1_h264_dma2d_out_ch4_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_DMA2D_OUT_CH4_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/h264_reg_int_map.rs b/esp32p4/src/interrupt_core1/h264_reg_int_map.rs
index 96264d3609..1ce2297052 100644
--- a/esp32p4/src/interrupt_core1/h264_reg_int_map.rs
+++ b/esp32p4/src/interrupt_core1/h264_reg_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("H264_REG_INT_MAP")
-            .field(
-                "core1_h264_reg_int_map",
-                &format_args!("{}", self.core1_h264_reg_int_map().bits()),
-            )
+            .field("core1_h264_reg_int_map", &self.core1_h264_reg_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H264_REG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/hp_core_ctrl_int_map.rs b/esp32p4/src/interrupt_core1/hp_core_ctrl_int_map.rs
index a83e582dcd..e724198e01 100644
--- a/esp32p4/src/interrupt_core1/hp_core_ctrl_int_map.rs
+++ b/esp32p4/src/interrupt_core1/hp_core_ctrl_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_CORE_CTRL_INT_MAP")
             .field(
                 "core1_hp_core_ctrl_int_map",
-                &format_args!("{}", self.core1_hp_core_ctrl_int_map().bits()),
+                &self.core1_hp_core_ctrl_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_CORE_CTRL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/hp_parlio_rx_int_map.rs b/esp32p4/src/interrupt_core1/hp_parlio_rx_int_map.rs
index 6376ad124f..a74bb2a88b 100644
--- a/esp32p4/src/interrupt_core1/hp_parlio_rx_int_map.rs
+++ b/esp32p4/src/interrupt_core1/hp_parlio_rx_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_PARLIO_RX_INT_MAP")
             .field(
                 "core1_hp_parlio_rx_int_map",
-                &format_args!("{}", self.core1_hp_parlio_rx_int_map().bits()),
+                &self.core1_hp_parlio_rx_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_PARLIO_RX_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/hp_parlio_tx_int_map.rs b/esp32p4/src/interrupt_core1/hp_parlio_tx_int_map.rs
index 2d2acd3537..b7d0399a10 100644
--- a/esp32p4/src/interrupt_core1/hp_parlio_tx_int_map.rs
+++ b/esp32p4/src/interrupt_core1/hp_parlio_tx_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_PARLIO_TX_INT_MAP")
             .field(
                 "core1_hp_parlio_tx_int_map",
-                &format_args!("{}", self.core1_hp_parlio_tx_int_map().bits()),
+                &self.core1_hp_parlio_tx_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_PARLIO_TX_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/hp_pau_int_map.rs b/esp32p4/src/interrupt_core1/hp_pau_int_map.rs
index 7c95a1bc71..f8512d9e91 100644
--- a/esp32p4/src/interrupt_core1/hp_pau_int_map.rs
+++ b/esp32p4/src/interrupt_core1/hp_pau_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_PAU_INT_MAP")
-            .field(
-                "core1_hp_pau_int_map",
-                &format_args!("{}", self.core1_hp_pau_int_map().bits()),
-            )
+            .field("core1_hp_pau_int_map", &self.core1_hp_pau_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_PAU_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/hp_sysreg_int_map.rs b/esp32p4/src/interrupt_core1/hp_sysreg_int_map.rs
index 29a858919a..2ed3be038f 100644
--- a/esp32p4/src/interrupt_core1/hp_sysreg_int_map.rs
+++ b/esp32p4/src/interrupt_core1/hp_sysreg_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SYSREG_INT_MAP")
-            .field(
-                "core1_hp_sysreg_int_map",
-                &format_args!("{}", self.core1_hp_sysreg_int_map().bits()),
-            )
+            .field("core1_hp_sysreg_int_map", &self.core1_hp_sysreg_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SYSREG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/i2c0_int_map.rs b/esp32p4/src/interrupt_core1/i2c0_int_map.rs
index ac4cf3ed35..cb58b38820 100644
--- a/esp32p4/src/interrupt_core1/i2c0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/i2c0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C0_INT_MAP")
-            .field(
-                "core1_i2c0_int_map",
-                &format_args!("{}", self.core1_i2c0_int_map().bits()),
-            )
+            .field("core1_i2c0_int_map", &self.core1_i2c0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/i2c1_int_map.rs b/esp32p4/src/interrupt_core1/i2c1_int_map.rs
index 2d5eaa3448..3c84d4db56 100644
--- a/esp32p4/src/interrupt_core1/i2c1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/i2c1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C1_INT_MAP")
-            .field(
-                "core1_i2c1_int_map",
-                &format_args!("{}", self.core1_i2c1_int_map().bits()),
-            )
+            .field("core1_i2c1_int_map", &self.core1_i2c1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/i2s0_int_map.rs b/esp32p4/src/interrupt_core1/i2s0_int_map.rs
index eb32338984..5e17651295 100644
--- a/esp32p4/src/interrupt_core1/i2s0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/i2s0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S0_INT_MAP")
-            .field(
-                "core1_i2s0_int_map",
-                &format_args!("{}", self.core1_i2s0_int_map().bits()),
-            )
+            .field("core1_i2s0_int_map", &self.core1_i2s0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/i2s1_int_map.rs b/esp32p4/src/interrupt_core1/i2s1_int_map.rs
index c9935a6b63..27865f86a6 100644
--- a/esp32p4/src/interrupt_core1/i2s1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/i2s1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S1_INT_MAP")
-            .field(
-                "core1_i2s1_int_map",
-                &format_args!("{}", self.core1_i2s1_int_map().bits()),
-            )
+            .field("core1_i2s1_int_map", &self.core1_i2s1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/i2s2_int_map.rs b/esp32p4/src/interrupt_core1/i2s2_int_map.rs
index 8564cc0199..9a7945d2c9 100644
--- a/esp32p4/src/interrupt_core1/i2s2_int_map.rs
+++ b/esp32p4/src/interrupt_core1/i2s2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S2_INT_MAP")
-            .field(
-                "core1_i2s2_int_map",
-                &format_args!("{}", self.core1_i2s2_int_map().bits()),
-            )
+            .field("core1_i2s2_int_map", &self.core1_i2s2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/i3c_mst_int_map.rs b/esp32p4/src/interrupt_core1/i3c_mst_int_map.rs
index 2af452872c..8fa121eed2 100644
--- a/esp32p4/src/interrupt_core1/i3c_mst_int_map.rs
+++ b/esp32p4/src/interrupt_core1/i3c_mst_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I3C_MST_INT_MAP")
-            .field(
-                "core1_i3c_mst_int_map",
-                &format_args!("{}", self.core1_i3c_mst_int_map().bits()),
-            )
+            .field("core1_i3c_mst_int_map", &self.core1_i3c_mst_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I3C_MST_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/i3c_slv_int_map.rs b/esp32p4/src/interrupt_core1/i3c_slv_int_map.rs
index 536cd4f50e..9cae9aacb3 100644
--- a/esp32p4/src/interrupt_core1/i3c_slv_int_map.rs
+++ b/esp32p4/src/interrupt_core1/i3c_slv_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I3C_SLV_INT_MAP")
-            .field(
-                "core1_i3c_slv_int_map",
-                &format_args!("{}", self.core1_i3c_slv_int_map().bits()),
-            )
+            .field("core1_i3c_slv_int_map", &self.core1_i3c_slv_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I3C_SLV_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/interrupt_reg_date.rs b/esp32p4/src/interrupt_core1/interrupt_reg_date.rs
index d7acee56d8..f331b36643 100644
--- a/esp32p4/src/interrupt_core1/interrupt_reg_date.rs
+++ b/esp32p4/src/interrupt_core1/interrupt_reg_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT_REG_DATE")
-            .field(
-                "core1_interrupt_reg_date",
-                &format_args!("{}", self.core1_interrupt_reg_date().bits()),
-            )
+            .field("core1_interrupt_reg_date", &self.core1_interrupt_reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/intr_status_reg_0.rs b/esp32p4/src/interrupt_core1/intr_status_reg_0.rs
index 733e20a2bb..3b82487aaa 100644
--- a/esp32p4/src/interrupt_core1/intr_status_reg_0.rs
+++ b/esp32p4/src/interrupt_core1/intr_status_reg_0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_0")
-            .field(
-                "core1_intr_status_0",
-                &format_args!("{}", self.core1_intr_status_0().bits()),
-            )
+            .field("core1_intr_status_0", &self.core1_intr_status_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_0_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_0_SPEC {
diff --git a/esp32p4/src/interrupt_core1/intr_status_reg_1.rs b/esp32p4/src/interrupt_core1/intr_status_reg_1.rs
index 86e99871df..bec723b610 100644
--- a/esp32p4/src/interrupt_core1/intr_status_reg_1.rs
+++ b/esp32p4/src/interrupt_core1/intr_status_reg_1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_1")
-            .field(
-                "core1_intr_status_1",
-                &format_args!("{}", self.core1_intr_status_1().bits()),
-            )
+            .field("core1_intr_status_1", &self.core1_intr_status_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_1_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_1_SPEC {
diff --git a/esp32p4/src/interrupt_core1/intr_status_reg_2.rs b/esp32p4/src/interrupt_core1/intr_status_reg_2.rs
index 478acfb655..9828605b71 100644
--- a/esp32p4/src/interrupt_core1/intr_status_reg_2.rs
+++ b/esp32p4/src/interrupt_core1/intr_status_reg_2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_2")
-            .field(
-                "core1_intr_status_2",
-                &format_args!("{}", self.core1_intr_status_2().bits()),
-            )
+            .field("core1_intr_status_2", &self.core1_intr_status_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_2_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_2_SPEC {
diff --git a/esp32p4/src/interrupt_core1/intr_status_reg_3.rs b/esp32p4/src/interrupt_core1/intr_status_reg_3.rs
index 3b9fb32c63..224d5cd68a 100644
--- a/esp32p4/src/interrupt_core1/intr_status_reg_3.rs
+++ b/esp32p4/src/interrupt_core1/intr_status_reg_3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_STATUS_REG_3")
-            .field(
-                "core1_intr_status_3",
-                &format_args!("{}", self.core1_intr_status_3().bits()),
-            )
+            .field("core1_intr_status_3", &self.core1_intr_status_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_STATUS_REG_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_status_reg_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_STATUS_REG_3_SPEC;
 impl crate::RegisterSpec for INTR_STATUS_REG_3_SPEC {
diff --git a/esp32p4/src/interrupt_core1/isp_int_map.rs b/esp32p4/src/interrupt_core1/isp_int_map.rs
index 37730bf11b..c49fc0543f 100644
--- a/esp32p4/src/interrupt_core1/isp_int_map.rs
+++ b/esp32p4/src/interrupt_core1/isp_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ISP_INT_MAP")
-            .field(
-                "core1_isp_int_map",
-                &format_args!("{}", self.core1_isp_int_map().bits()),
-            )
+            .field("core1_isp_int_map", &self.core1_isp_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ISP_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/jpeg_int_map.rs b/esp32p4/src/interrupt_core1/jpeg_int_map.rs
index b59b66a5a4..a6d7331ce7 100644
--- a/esp32p4/src/interrupt_core1/jpeg_int_map.rs
+++ b/esp32p4/src/interrupt_core1/jpeg_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("JPEG_INT_MAP")
-            .field(
-                "core1_jpeg_int_map",
-                &format_args!("{}", self.core1_jpeg_int_map().bits()),
-            )
+            .field("core1_jpeg_int_map", &self.core1_jpeg_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<JPEG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/km_int_map.rs b/esp32p4/src/interrupt_core1/km_int_map.rs
index cb6b0c963d..e3ea5c032c 100644
--- a/esp32p4/src/interrupt_core1/km_int_map.rs
+++ b/esp32p4/src/interrupt_core1/km_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("KM_INT_MAP")
-            .field(
-                "core1_km_int_map",
-                &format_args!("{}", self.core1_km_int_map().bits()),
-            )
+            .field("core1_km_int_map", &self.core1_km_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<KM_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lcd_cam_int_map.rs b/esp32p4/src/interrupt_core1/lcd_cam_int_map.rs
index 42e3c08c7a..e6c937c829 100644
--- a/esp32p4/src/interrupt_core1/lcd_cam_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lcd_cam_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CAM_INT_MAP")
-            .field(
-                "core1_lcd_cam_int_map",
-                &format_args!("{}", self.core1_lcd_cam_int_map().bits()),
-            )
+            .field("core1_lcd_cam_int_map", &self.core1_lcd_cam_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CAM_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/ledc_int_map.rs b/esp32p4/src/interrupt_core1/ledc_int_map.rs
index 74188afd73..6461348614 100644
--- a/esp32p4/src/interrupt_core1/ledc_int_map.rs
+++ b/esp32p4/src/interrupt_core1/ledc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEDC_INT_MAP")
-            .field(
-                "core1_ledc_int_map",
-                &format_args!("{}", self.core1_ledc_int_map().bits()),
-            )
+            .field("core1_ledc_int_map", &self.core1_ledc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEDC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_adc_int_map.rs b/esp32p4/src/interrupt_core1/lp_adc_int_map.rs
index bfd10f6e38..538eaebbd9 100644
--- a/esp32p4/src/interrupt_core1/lp_adc_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_adc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_ADC_INT_MAP")
-            .field(
-                "core1_lp_adc_int_map",
-                &format_args!("{}", self.core1_lp_adc_int_map().bits()),
-            )
+            .field("core1_lp_adc_int_map", &self.core1_lp_adc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_ADC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_anaperi_int_map.rs b/esp32p4/src/interrupt_core1/lp_anaperi_int_map.rs
index 6f77fc88a5..b949361481 100644
--- a/esp32p4/src/interrupt_core1/lp_anaperi_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_anaperi_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_ANAPERI_INT_MAP")
-            .field(
-                "core1_lp_anaperi_int_map",
-                &format_args!("{}", self.core1_lp_anaperi_int_map().bits()),
-            )
+            .field("core1_lp_anaperi_int_map", &self.core1_lp_anaperi_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_ANAPERI_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_efuse_int_map.rs b/esp32p4/src/interrupt_core1/lp_efuse_int_map.rs
index 021f8704ea..9d7a19ced4 100644
--- a/esp32p4/src/interrupt_core1/lp_efuse_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_efuse_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_EFUSE_INT_MAP")
-            .field(
-                "core1_lp_efuse_int_map",
-                &format_args!("{}", self.core1_lp_efuse_int_map().bits()),
-            )
+            .field("core1_lp_efuse_int_map", &self.core1_lp_efuse_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_EFUSE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_gpio_int_map.rs b/esp32p4/src/interrupt_core1/lp_gpio_int_map.rs
index 0bb10ef038..1f254c21ee 100644
--- a/esp32p4/src/interrupt_core1/lp_gpio_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_gpio_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_GPIO_INT_MAP")
-            .field(
-                "core1_lp_gpio_int_map",
-                &format_args!("{}", self.core1_lp_gpio_int_map().bits()),
-            )
+            .field("core1_lp_gpio_int_map", &self.core1_lp_gpio_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_GPIO_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_huk_int_map.rs b/esp32p4/src/interrupt_core1/lp_huk_int_map.rs
index ce65a5f6fa..79d16aecb3 100644
--- a/esp32p4/src/interrupt_core1/lp_huk_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_huk_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_HUK_INT_MAP")
-            .field(
-                "core1_lp_huk_int_map",
-                &format_args!("{}", self.core1_lp_huk_int_map().bits()),
-            )
+            .field("core1_lp_huk_int_map", &self.core1_lp_huk_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_HUK_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_i2c_int_map.rs b/esp32p4/src/interrupt_core1/lp_i2c_int_map.rs
index a9031a16a1..9d46e6cace 100644
--- a/esp32p4/src/interrupt_core1/lp_i2c_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_i2c_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_I2C_INT_MAP")
-            .field(
-                "core1_lp_i2c_int_map",
-                &format_args!("{}", self.core1_lp_i2c_int_map().bits()),
-            )
+            .field("core1_lp_i2c_int_map", &self.core1_lp_i2c_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_I2C_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_i2s_int_map.rs b/esp32p4/src/interrupt_core1/lp_i2s_int_map.rs
index 294a26deef..58457a78d3 100644
--- a/esp32p4/src/interrupt_core1/lp_i2s_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_i2s_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_I2S_INT_MAP")
-            .field(
-                "core1_lp_i2s_int_map",
-                &format_args!("{}", self.core1_lp_i2s_int_map().bits()),
-            )
+            .field("core1_lp_i2s_int_map", &self.core1_lp_i2s_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_I2S_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_rtc_int_map.rs b/esp32p4/src/interrupt_core1/lp_rtc_int_map.rs
index 2486625853..531e4141bb 100644
--- a/esp32p4/src/interrupt_core1/lp_rtc_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_rtc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_RTC_INT_MAP")
-            .field(
-                "core1_lp_rtc_int_map",
-                &format_args!("{}", self.core1_lp_rtc_int_map().bits()),
-            )
+            .field("core1_lp_rtc_int_map", &self.core1_lp_rtc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_RTC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_spi_int_map.rs b/esp32p4/src/interrupt_core1/lp_spi_int_map.rs
index 100265e8ac..a8432c8940 100644
--- a/esp32p4/src/interrupt_core1/lp_spi_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_spi_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SPI_INT_MAP")
-            .field(
-                "core1_lp_spi_int_map",
-                &format_args!("{}", self.core1_lp_spi_int_map().bits()),
-            )
+            .field("core1_lp_spi_int_map", &self.core1_lp_spi_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SPI_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_sw_int_map.rs b/esp32p4/src/interrupt_core1/lp_sw_int_map.rs
index fcbafe521e..063fb2372c 100644
--- a/esp32p4/src/interrupt_core1/lp_sw_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_sw_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SW_INT_MAP")
-            .field(
-                "core1_lp_sw_int_map",
-                &format_args!("{}", self.core1_lp_sw_int_map().bits()),
-            )
+            .field("core1_lp_sw_int_map", &self.core1_lp_sw_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SW_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_sysreg_int_map.rs b/esp32p4/src/interrupt_core1/lp_sysreg_int_map.rs
index 162e1887c6..1eb0075fef 100644
--- a/esp32p4/src/interrupt_core1/lp_sysreg_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_sysreg_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SYSREG_INT_MAP")
-            .field(
-                "core1_lp_sysreg_int_map",
-                &format_args!("{}", self.core1_lp_sysreg_int_map().bits()),
-            )
+            .field("core1_lp_sysreg_int_map", &self.core1_lp_sysreg_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SYSREG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_timer_reg_0_int_map.rs b/esp32p4/src/interrupt_core1/lp_timer_reg_0_int_map.rs
index 33cee54b4b..757592e783 100644
--- a/esp32p4/src/interrupt_core1/lp_timer_reg_0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_timer_reg_0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_TIMER_REG_0_INT_MAP")
             .field(
                 "core1_lp_timer_reg_0_int_map",
-                &format_args!("{}", self.core1_lp_timer_reg_0_int_map().bits()),
+                &self.core1_lp_timer_reg_0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TIMER_REG_0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_timer_reg_1_int_map.rs b/esp32p4/src/interrupt_core1/lp_timer_reg_1_int_map.rs
index 890b50da25..9e5ce2cdb1 100644
--- a/esp32p4/src/interrupt_core1/lp_timer_reg_1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_timer_reg_1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_TIMER_REG_1_INT_MAP")
             .field(
                 "core1_lp_timer_reg_1_int_map",
-                &format_args!("{}", self.core1_lp_timer_reg_1_int_map().bits()),
+                &self.core1_lp_timer_reg_1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TIMER_REG_1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_touch_int_map.rs b/esp32p4/src/interrupt_core1/lp_touch_int_map.rs
index 7a67a095d9..eb0e8b4a28 100644
--- a/esp32p4/src/interrupt_core1/lp_touch_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_touch_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_TOUCH_INT_MAP")
-            .field(
-                "core1_lp_touch_int_map",
-                &format_args!("{}", self.core1_lp_touch_int_map().bits()),
-            )
+            .field("core1_lp_touch_int_map", &self.core1_lp_touch_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TOUCH_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_tsens_int_map.rs b/esp32p4/src/interrupt_core1/lp_tsens_int_map.rs
index debc43eb0e..18d9fe348c 100644
--- a/esp32p4/src/interrupt_core1/lp_tsens_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_tsens_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_TSENS_INT_MAP")
-            .field(
-                "core1_lp_tsens_int_map",
-                &format_args!("{}", self.core1_lp_tsens_int_map().bits()),
-            )
+            .field("core1_lp_tsens_int_map", &self.core1_lp_tsens_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TSENS_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_uart_int_map.rs b/esp32p4/src/interrupt_core1/lp_uart_int_map.rs
index d82231482d..b5e34d65ac 100644
--- a/esp32p4/src/interrupt_core1/lp_uart_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_uart_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_UART_INT_MAP")
-            .field(
-                "core1_lp_uart_int_map",
-                &format_args!("{}", self.core1_lp_uart_int_map().bits()),
-            )
+            .field("core1_lp_uart_int_map", &self.core1_lp_uart_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_UART_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lp_wdt_int_map.rs b/esp32p4/src/interrupt_core1/lp_wdt_int_map.rs
index 3637fea9e6..c68c09ce63 100644
--- a/esp32p4/src/interrupt_core1/lp_wdt_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lp_wdt_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_WDT_INT_MAP")
-            .field(
-                "core1_lp_wdt_int_map",
-                &format_args!("{}", self.core1_lp_wdt_int_map().bits()),
-            )
+            .field("core1_lp_wdt_int_map", &self.core1_lp_wdt_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_WDT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/lpi_int_map.rs b/esp32p4/src/interrupt_core1/lpi_int_map.rs
index 69be1dd41d..f265969706 100644
--- a/esp32p4/src/interrupt_core1/lpi_int_map.rs
+++ b/esp32p4/src/interrupt_core1/lpi_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPI_INT_MAP")
-            .field(
-                "core1_lpi_int_map",
-                &format_args!("{}", self.core1_lpi_int_map().bits()),
-            )
+            .field("core1_lpi_int_map", &self.core1_lpi_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPI_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/mb_hp_int_map.rs b/esp32p4/src/interrupt_core1/mb_hp_int_map.rs
index 5b5330c2e4..121aaaa2f9 100644
--- a/esp32p4/src/interrupt_core1/mb_hp_int_map.rs
+++ b/esp32p4/src/interrupt_core1/mb_hp_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MB_HP_INT_MAP")
-            .field(
-                "core1_mb_hp_int_map",
-                &format_args!("{}", self.core1_mb_hp_int_map().bits()),
-            )
+            .field("core1_mb_hp_int_map", &self.core1_mb_hp_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MB_HP_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/mb_lp_int_map.rs b/esp32p4/src/interrupt_core1/mb_lp_int_map.rs
index 745898549f..e13eb676d3 100644
--- a/esp32p4/src/interrupt_core1/mb_lp_int_map.rs
+++ b/esp32p4/src/interrupt_core1/mb_lp_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MB_LP_INT_MAP")
-            .field(
-                "core1_mb_lp_int_map",
-                &format_args!("{}", self.core1_mb_lp_int_map().bits()),
-            )
+            .field("core1_mb_lp_int_map", &self.core1_mb_lp_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MB_LP_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/pcnt_int_map.rs b/esp32p4/src/interrupt_core1/pcnt_int_map.rs
index ba1d06d604..f7e2109930 100644
--- a/esp32p4/src/interrupt_core1/pcnt_int_map.rs
+++ b/esp32p4/src/interrupt_core1/pcnt_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCNT_INT_MAP")
-            .field(
-                "core1_pcnt_int_map",
-                &format_args!("{}", self.core1_pcnt_int_map().bits()),
-            )
+            .field("core1_pcnt_int_map", &self.core1_pcnt_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCNT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/pmt_int_map.rs b/esp32p4/src/interrupt_core1/pmt_int_map.rs
index 547be0c026..6e238a172c 100644
--- a/esp32p4/src/interrupt_core1/pmt_int_map.rs
+++ b/esp32p4/src/interrupt_core1/pmt_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMT_INT_MAP")
-            .field(
-                "core1_pmt_int_map",
-                &format_args!("{}", self.core1_pmt_int_map().bits()),
-            )
+            .field("core1_pmt_int_map", &self.core1_pmt_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/pmu_reg_0_int_map.rs b/esp32p4/src/interrupt_core1/pmu_reg_0_int_map.rs
index 53560bb60e..a0d9f813c9 100644
--- a/esp32p4/src/interrupt_core1/pmu_reg_0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/pmu_reg_0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMU_REG_0_INT_MAP")
-            .field(
-                "core1_pmu_reg_0_int_map",
-                &format_args!("{}", self.core1_pmu_reg_0_int_map().bits()),
-            )
+            .field("core1_pmu_reg_0_int_map", &self.core1_pmu_reg_0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMU_REG_0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/pmu_reg_1_int_map.rs b/esp32p4/src/interrupt_core1/pmu_reg_1_int_map.rs
index 74384e3a21..f1339d9e18 100644
--- a/esp32p4/src/interrupt_core1/pmu_reg_1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/pmu_reg_1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMU_REG_1_INT_MAP")
-            .field(
-                "core1_pmu_reg_1_int_map",
-                &format_args!("{}", self.core1_pmu_reg_1_int_map().bits()),
-            )
+            .field("core1_pmu_reg_1_int_map", &self.core1_pmu_reg_1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMU_REG_1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/ppa_int_map.rs b/esp32p4/src/interrupt_core1/ppa_int_map.rs
index 9531b0fbbd..2e2143c4d0 100644
--- a/esp32p4/src/interrupt_core1/ppa_int_map.rs
+++ b/esp32p4/src/interrupt_core1/ppa_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PPA_INT_MAP")
-            .field(
-                "core1_ppa_int_map",
-                &format_args!("{}", self.core1_ppa_int_map().bits()),
-            )
+            .field("core1_ppa_int_map", &self.core1_ppa_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PPA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/psram_mspi_int_map.rs b/esp32p4/src/interrupt_core1/psram_mspi_int_map.rs
index 1362712964..8b8f80de1a 100644
--- a/esp32p4/src/interrupt_core1/psram_mspi_int_map.rs
+++ b/esp32p4/src/interrupt_core1/psram_mspi_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PSRAM_MSPI_INT_MAP")
-            .field(
-                "core1_psram_mspi_int_map",
-                &format_args!("{}", self.core1_psram_mspi_int_map().bits()),
-            )
+            .field("core1_psram_mspi_int_map", &self.core1_psram_mspi_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PSRAM_MSPI_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/pwm0_int_map.rs b/esp32p4/src/interrupt_core1/pwm0_int_map.rs
index 54a2910c37..e1b2598010 100644
--- a/esp32p4/src/interrupt_core1/pwm0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/pwm0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM0_INT_MAP")
-            .field(
-                "core1_pwm0_int_map",
-                &format_args!("{}", self.core1_pwm0_int_map().bits()),
-            )
+            .field("core1_pwm0_int_map", &self.core1_pwm0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/pwm1_int_map.rs b/esp32p4/src/interrupt_core1/pwm1_int_map.rs
index 217103b801..10126108a5 100644
--- a/esp32p4/src/interrupt_core1/pwm1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/pwm1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM1_INT_MAP")
-            .field(
-                "core1_pwm1_int_map",
-                &format_args!("{}", self.core1_pwm1_int_map().bits()),
-            )
+            .field("core1_pwm1_int_map", &self.core1_pwm1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/rmt_int_map.rs b/esp32p4/src/interrupt_core1/rmt_int_map.rs
index 314766ba8f..7506ed7298 100644
--- a/esp32p4/src/interrupt_core1/rmt_int_map.rs
+++ b/esp32p4/src/interrupt_core1/rmt_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RMT_INT_MAP")
-            .field(
-                "core1_rmt_int_map",
-                &format_args!("{}", self.core1_rmt_int_map().bits()),
-            )
+            .field("core1_rmt_int_map", &self.core1_rmt_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RMT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/rsa_int_map.rs b/esp32p4/src/interrupt_core1/rsa_int_map.rs
index 2e637e7510..93d73458a9 100644
--- a/esp32p4/src/interrupt_core1/rsa_int_map.rs
+++ b/esp32p4/src/interrupt_core1/rsa_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_INT_MAP")
-            .field(
-                "core1_rsa_int_map",
-                &format_args!("{}", self.core1_rsa_int_map().bits()),
-            )
+            .field("core1_rsa_int_map", &self.core1_rsa_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/sbd_int_map.rs b/esp32p4/src/interrupt_core1/sbd_int_map.rs
index c20248f143..ef31a7dc31 100644
--- a/esp32p4/src/interrupt_core1/sbd_int_map.rs
+++ b/esp32p4/src/interrupt_core1/sbd_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SBD_INT_MAP")
-            .field(
-                "core1_sbd_int_map",
-                &format_args!("{}", self.core1_sbd_int_map().bits()),
-            )
+            .field("core1_sbd_int_map", &self.core1_sbd_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SBD_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/sdio_host_int_map.rs b/esp32p4/src/interrupt_core1/sdio_host_int_map.rs
index ae2f1358a7..68ed171836 100644
--- a/esp32p4/src/interrupt_core1/sdio_host_int_map.rs
+++ b/esp32p4/src/interrupt_core1/sdio_host_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_HOST_INT_MAP")
-            .field(
-                "core1_sdio_host_int_map",
-                &format_args!("{}", self.core1_sdio_host_int_map().bits()),
-            )
+            .field("core1_sdio_host_int_map", &self.core1_sdio_host_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_HOST_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/sha_int_map.rs b/esp32p4/src/interrupt_core1/sha_int_map.rs
index c6d66d32d5..740549dba3 100644
--- a/esp32p4/src/interrupt_core1/sha_int_map.rs
+++ b/esp32p4/src/interrupt_core1/sha_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA_INT_MAP")
-            .field(
-                "core1_sha_int_map",
-                &format_args!("{}", self.core1_sha_int_map().bits()),
-            )
+            .field("core1_sha_int_map", &self.core1_sha_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/spi2_int_map.rs b/esp32p4/src/interrupt_core1/spi2_int_map.rs
index 89c05148e5..d5a371e219 100644
--- a/esp32p4/src/interrupt_core1/spi2_int_map.rs
+++ b/esp32p4/src/interrupt_core1/spi2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI2_INT_MAP")
-            .field(
-                "core1_spi2_int_map",
-                &format_args!("{}", self.core1_spi2_int_map().bits()),
-            )
+            .field("core1_spi2_int_map", &self.core1_spi2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/spi3_int_map.rs b/esp32p4/src/interrupt_core1/spi3_int_map.rs
index 02fbdd9a79..f2730d7821 100644
--- a/esp32p4/src/interrupt_core1/spi3_int_map.rs
+++ b/esp32p4/src/interrupt_core1/spi3_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI3_INT_MAP")
-            .field(
-                "core1_spi3_int_map",
-                &format_args!("{}", self.core1_spi3_int_map().bits()),
-            )
+            .field("core1_spi3_int_map", &self.core1_spi3_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI3_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/sys_icm_int_map.rs b/esp32p4/src/interrupt_core1/sys_icm_int_map.rs
index b5facbde38..09ffec94f9 100644
--- a/esp32p4/src/interrupt_core1/sys_icm_int_map.rs
+++ b/esp32p4/src/interrupt_core1/sys_icm_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYS_ICM_INT_MAP")
-            .field(
-                "core1_sys_icm_int_map",
-                &format_args!("{}", self.core1_sys_icm_int_map().bits()),
-            )
+            .field("core1_sys_icm_int_map", &self.core1_sys_icm_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYS_ICM_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/systimer_target0_int_map.rs b/esp32p4/src/interrupt_core1/systimer_target0_int_map.rs
index 00aa3b8ac9..3202897ae7 100644
--- a/esp32p4/src/interrupt_core1/systimer_target0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/systimer_target0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYSTIMER_TARGET0_INT_MAP")
             .field(
                 "core1_systimer_target0_int_map",
-                &format_args!("{}", self.core1_systimer_target0_int_map().bits()),
+                &self.core1_systimer_target0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/systimer_target1_int_map.rs b/esp32p4/src/interrupt_core1/systimer_target1_int_map.rs
index b2ef303004..2c3a62bb12 100644
--- a/esp32p4/src/interrupt_core1/systimer_target1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/systimer_target1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYSTIMER_TARGET1_INT_MAP")
             .field(
                 "core1_systimer_target1_int_map",
-                &format_args!("{}", self.core1_systimer_target1_int_map().bits()),
+                &self.core1_systimer_target1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/systimer_target2_int_map.rs b/esp32p4/src/interrupt_core1/systimer_target2_int_map.rs
index ba0c324ff8..f3a58544a4 100644
--- a/esp32p4/src/interrupt_core1/systimer_target2_int_map.rs
+++ b/esp32p4/src/interrupt_core1/systimer_target2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("SYSTIMER_TARGET2_INT_MAP")
             .field(
                 "core1_systimer_target2_int_map",
-                &format_args!("{}", self.core1_systimer_target2_int_map().bits()),
+                &self.core1_systimer_target2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/timergrp0_t0_int_map.rs b/esp32p4/src/interrupt_core1/timergrp0_t0_int_map.rs
index 6a386f92be..86a93e0a00 100644
--- a/esp32p4/src/interrupt_core1/timergrp0_t0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/timergrp0_t0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("TIMERGRP0_T0_INT_MAP")
             .field(
                 "core1_timergrp0_t0_int_map",
-                &format_args!("{}", self.core1_timergrp0_t0_int_map().bits()),
+                &self.core1_timergrp0_t0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGRP0_T0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/timergrp0_t1_int_map.rs b/esp32p4/src/interrupt_core1/timergrp0_t1_int_map.rs
index 76eec2b4d3..10420ead9c 100644
--- a/esp32p4/src/interrupt_core1/timergrp0_t1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/timergrp0_t1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("TIMERGRP0_T1_INT_MAP")
             .field(
                 "core1_timergrp0_t1_int_map",
-                &format_args!("{}", self.core1_timergrp0_t1_int_map().bits()),
+                &self.core1_timergrp0_t1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGRP0_T1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/timergrp0_wdt_int_map.rs b/esp32p4/src/interrupt_core1/timergrp0_wdt_int_map.rs
index 5d502b65f4..5e74d9b996 100644
--- a/esp32p4/src/interrupt_core1/timergrp0_wdt_int_map.rs
+++ b/esp32p4/src/interrupt_core1/timergrp0_wdt_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("TIMERGRP0_WDT_INT_MAP")
             .field(
                 "core1_timergrp0_wdt_int_map",
-                &format_args!("{}", self.core1_timergrp0_wdt_int_map().bits()),
+                &self.core1_timergrp0_wdt_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGRP0_WDT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/timergrp1_t0_int_map.rs b/esp32p4/src/interrupt_core1/timergrp1_t0_int_map.rs
index 1f4b9daed6..68a5bd574a 100644
--- a/esp32p4/src/interrupt_core1/timergrp1_t0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/timergrp1_t0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("TIMERGRP1_T0_INT_MAP")
             .field(
                 "core1_timergrp1_t0_int_map",
-                &format_args!("{}", self.core1_timergrp1_t0_int_map().bits()),
+                &self.core1_timergrp1_t0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGRP1_T0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/timergrp1_t1_int_map.rs b/esp32p4/src/interrupt_core1/timergrp1_t1_int_map.rs
index b39511437d..93929acf13 100644
--- a/esp32p4/src/interrupt_core1/timergrp1_t1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/timergrp1_t1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("TIMERGRP1_T1_INT_MAP")
             .field(
                 "core1_timergrp1_t1_int_map",
-                &format_args!("{}", self.core1_timergrp1_t1_int_map().bits()),
+                &self.core1_timergrp1_t1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGRP1_T1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/timergrp1_wdt_int_map.rs b/esp32p4/src/interrupt_core1/timergrp1_wdt_int_map.rs
index 33f8fcbebd..00a2add037 100644
--- a/esp32p4/src/interrupt_core1/timergrp1_wdt_int_map.rs
+++ b/esp32p4/src/interrupt_core1/timergrp1_wdt_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("TIMERGRP1_WDT_INT_MAP")
             .field(
                 "core1_timergrp1_wdt_int_map",
-                &format_args!("{}", self.core1_timergrp1_wdt_int_map().bits()),
+                &self.core1_timergrp1_wdt_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERGRP1_WDT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/uart0_int_map.rs b/esp32p4/src/interrupt_core1/uart0_int_map.rs
index 07c5aec586..f6ba8f2018 100644
--- a/esp32p4/src/interrupt_core1/uart0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/uart0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART0_INT_MAP")
-            .field(
-                "core1_uart0_int_map",
-                &format_args!("{}", self.core1_uart0_int_map().bits()),
-            )
+            .field("core1_uart0_int_map", &self.core1_uart0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/uart1_int_map.rs b/esp32p4/src/interrupt_core1/uart1_int_map.rs
index 8c2833be8f..3aba7184be 100644
--- a/esp32p4/src/interrupt_core1/uart1_int_map.rs
+++ b/esp32p4/src/interrupt_core1/uart1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART1_INT_MAP")
-            .field(
-                "core1_uart1_int_map",
-                &format_args!("{}", self.core1_uart1_int_map().bits()),
-            )
+            .field("core1_uart1_int_map", &self.core1_uart1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/uart2_int_map.rs b/esp32p4/src/interrupt_core1/uart2_int_map.rs
index 71cce9b78f..44cc4335c4 100644
--- a/esp32p4/src/interrupt_core1/uart2_int_map.rs
+++ b/esp32p4/src/interrupt_core1/uart2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART2_INT_MAP")
-            .field(
-                "core1_uart2_int_map",
-                &format_args!("{}", self.core1_uart2_int_map().bits()),
-            )
+            .field("core1_uart2_int_map", &self.core1_uart2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/uart3_int_map.rs b/esp32p4/src/interrupt_core1/uart3_int_map.rs
index 16100b1cd6..bf095374e6 100644
--- a/esp32p4/src/interrupt_core1/uart3_int_map.rs
+++ b/esp32p4/src/interrupt_core1/uart3_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART3_INT_MAP")
-            .field(
-                "core1_uart3_int_map",
-                &format_args!("{}", self.core1_uart3_int_map().bits()),
-            )
+            .field("core1_uart3_int_map", &self.core1_uart3_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART3_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/uart4_int_map.rs b/esp32p4/src/interrupt_core1/uart4_int_map.rs
index 91520a5e22..ec695627ed 100644
--- a/esp32p4/src/interrupt_core1/uart4_int_map.rs
+++ b/esp32p4/src/interrupt_core1/uart4_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART4_INT_MAP")
-            .field(
-                "core1_uart4_int_map",
-                &format_args!("{}", self.core1_uart4_int_map().bits()),
-            )
+            .field("core1_uart4_int_map", &self.core1_uart4_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART4_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/uhci0_int_map.rs b/esp32p4/src/interrupt_core1/uhci0_int_map.rs
index d0d3a8ed1d..992c5a5daa 100644
--- a/esp32p4/src/interrupt_core1/uhci0_int_map.rs
+++ b/esp32p4/src/interrupt_core1/uhci0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UHCI0_INT_MAP")
-            .field(
-                "core1_uhci0_int_map",
-                &format_args!("{}", self.core1_uhci0_int_map().bits()),
-            )
+            .field("core1_uhci0_int_map", &self.core1_uhci0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UHCI0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/usb_device_int_map.rs b/esp32p4/src/interrupt_core1/usb_device_int_map.rs
index 47bd868ba0..02615dbd69 100644
--- a/esp32p4/src/interrupt_core1/usb_device_int_map.rs
+++ b/esp32p4/src/interrupt_core1/usb_device_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_DEVICE_INT_MAP")
-            .field(
-                "core1_usb_device_int_map",
-                &format_args!("{}", self.core1_usb_device_int_map().bits()),
-            )
+            .field("core1_usb_device_int_map", &self.core1_usb_device_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_DEVICE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/usb_otg11_int_map.rs b/esp32p4/src/interrupt_core1/usb_otg11_int_map.rs
index 519864594b..f56ec1f533 100644
--- a/esp32p4/src/interrupt_core1/usb_otg11_int_map.rs
+++ b/esp32p4/src/interrupt_core1/usb_otg11_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_OTG11_INT_MAP")
-            .field(
-                "core1_usb_otg11_int_map",
-                &format_args!("{}", self.core1_usb_otg11_int_map().bits()),
-            )
+            .field("core1_usb_otg11_int_map", &self.core1_usb_otg11_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_OTG11_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/usb_otg_endp_multi_proc_int_map.rs b/esp32p4/src/interrupt_core1/usb_otg_endp_multi_proc_int_map.rs
index cc487fda8d..33f626b760 100644
--- a/esp32p4/src/interrupt_core1/usb_otg_endp_multi_proc_int_map.rs
+++ b/esp32p4/src/interrupt_core1/usb_otg_endp_multi_proc_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("USB_OTG_ENDP_MULTI_PROC_INT_MAP")
             .field(
                 "core1_usb_otg_endp_multi_proc_int_map",
-                &format_args!("{}", self.core1_usb_otg_endp_multi_proc_int_map().bits()),
+                &self.core1_usb_otg_endp_multi_proc_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_OTG_ENDP_MULTI_PROC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/interrupt_core1/usb_otg_int_map.rs b/esp32p4/src/interrupt_core1/usb_otg_int_map.rs
index 021005de5e..a1347ef561 100644
--- a/esp32p4/src/interrupt_core1/usb_otg_int_map.rs
+++ b/esp32p4/src/interrupt_core1/usb_otg_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_OTG_INT_MAP")
-            .field(
-                "core1_usb_otg_int_map",
-                &format_args!("{}", self.core1_usb_otg_int_map().bits()),
-            )
+            .field("core1_usb_otg_int_map", &self.core1_usb_otg_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_OTG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/io_mux/date.rs b/esp32p4/src/io_mux/date.rs
index cb9e477b12..187eea854e 100644
--- a/esp32p4/src/io_mux/date.rs
+++ b/esp32p4/src/io_mux/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/io_mux/gpio.rs b/esp32p4/src/io_mux/gpio.rs
index 8e50d81f8d..b2e687e5b8 100644
--- a/esp32p4/src/io_mux/gpio.rs
+++ b/esp32p4/src/io_mux/gpio.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("mcu_drv", &format_args!("{}", self.mcu_drv().bits()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("mcu_drv", &self.mcu_drv())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to enable the output of GPIOn in sleep mode. 0: Disable 1: Enable"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/ae_block_mean_0.rs b/esp32p4/src/isp/ae_block_mean_0.rs
index 3115272fcb..b03b344106 100644
--- a/esp32p4/src/isp/ae_block_mean_0.rs
+++ b/esp32p4/src/isp/ae_block_mean_0.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AE_BLOCK_MEAN_0")
-            .field(
-                "ae_b03_mean",
-                &format_args!("{}", self.ae_b03_mean().bits()),
-            )
-            .field(
-                "ae_b02_mean",
-                &format_args!("{}", self.ae_b02_mean().bits()),
-            )
-            .field(
-                "ae_b01_mean",
-                &format_args!("{}", self.ae_b01_mean().bits()),
-            )
-            .field(
-                "ae_b00_mean",
-                &format_args!("{}", self.ae_b00_mean().bits()),
-            )
+            .field("ae_b03_mean", &self.ae_b03_mean())
+            .field("ae_b02_mean", &self.ae_b02_mean())
+            .field("ae_b01_mean", &self.ae_b01_mean())
+            .field("ae_b00_mean", &self.ae_b00_mean())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AE_BLOCK_MEAN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ae statistic result register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AE_BLOCK_MEAN_0_SPEC;
 impl crate::RegisterSpec for AE_BLOCK_MEAN_0_SPEC {
diff --git a/esp32p4/src/isp/ae_block_mean_1.rs b/esp32p4/src/isp/ae_block_mean_1.rs
index ad637a982e..6eaf12ac56 100644
--- a/esp32p4/src/isp/ae_block_mean_1.rs
+++ b/esp32p4/src/isp/ae_block_mean_1.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AE_BLOCK_MEAN_1")
-            .field(
-                "ae_b12_mean",
-                &format_args!("{}", self.ae_b12_mean().bits()),
-            )
-            .field(
-                "ae_b11_mean",
-                &format_args!("{}", self.ae_b11_mean().bits()),
-            )
-            .field(
-                "ae_b10_mean",
-                &format_args!("{}", self.ae_b10_mean().bits()),
-            )
-            .field(
-                "ae_b04_mean",
-                &format_args!("{}", self.ae_b04_mean().bits()),
-            )
+            .field("ae_b12_mean", &self.ae_b12_mean())
+            .field("ae_b11_mean", &self.ae_b11_mean())
+            .field("ae_b10_mean", &self.ae_b10_mean())
+            .field("ae_b04_mean", &self.ae_b04_mean())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AE_BLOCK_MEAN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ae statistic result register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AE_BLOCK_MEAN_1_SPEC;
 impl crate::RegisterSpec for AE_BLOCK_MEAN_1_SPEC {
diff --git a/esp32p4/src/isp/ae_block_mean_2.rs b/esp32p4/src/isp/ae_block_mean_2.rs
index 94ceba13d8..60915e897e 100644
--- a/esp32p4/src/isp/ae_block_mean_2.rs
+++ b/esp32p4/src/isp/ae_block_mean_2.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AE_BLOCK_MEAN_2")
-            .field(
-                "ae_b21_mean",
-                &format_args!("{}", self.ae_b21_mean().bits()),
-            )
-            .field(
-                "ae_b20_mean",
-                &format_args!("{}", self.ae_b20_mean().bits()),
-            )
-            .field(
-                "ae_b14_mean",
-                &format_args!("{}", self.ae_b14_mean().bits()),
-            )
-            .field(
-                "ae_b13_mean",
-                &format_args!("{}", self.ae_b13_mean().bits()),
-            )
+            .field("ae_b21_mean", &self.ae_b21_mean())
+            .field("ae_b20_mean", &self.ae_b20_mean())
+            .field("ae_b14_mean", &self.ae_b14_mean())
+            .field("ae_b13_mean", &self.ae_b13_mean())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AE_BLOCK_MEAN_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ae statistic result register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AE_BLOCK_MEAN_2_SPEC;
 impl crate::RegisterSpec for AE_BLOCK_MEAN_2_SPEC {
diff --git a/esp32p4/src/isp/ae_block_mean_3.rs b/esp32p4/src/isp/ae_block_mean_3.rs
index d70cc05de9..7541d7ccbe 100644
--- a/esp32p4/src/isp/ae_block_mean_3.rs
+++ b/esp32p4/src/isp/ae_block_mean_3.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AE_BLOCK_MEAN_3")
-            .field(
-                "ae_b30_mean",
-                &format_args!("{}", self.ae_b30_mean().bits()),
-            )
-            .field(
-                "ae_b24_mean",
-                &format_args!("{}", self.ae_b24_mean().bits()),
-            )
-            .field(
-                "ae_b23_mean",
-                &format_args!("{}", self.ae_b23_mean().bits()),
-            )
-            .field(
-                "ae_b22_mean",
-                &format_args!("{}", self.ae_b22_mean().bits()),
-            )
+            .field("ae_b30_mean", &self.ae_b30_mean())
+            .field("ae_b24_mean", &self.ae_b24_mean())
+            .field("ae_b23_mean", &self.ae_b23_mean())
+            .field("ae_b22_mean", &self.ae_b22_mean())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AE_BLOCK_MEAN_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ae statistic result register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AE_BLOCK_MEAN_3_SPEC;
 impl crate::RegisterSpec for AE_BLOCK_MEAN_3_SPEC {
diff --git a/esp32p4/src/isp/ae_block_mean_4.rs b/esp32p4/src/isp/ae_block_mean_4.rs
index 085d5a35dd..3456b87914 100644
--- a/esp32p4/src/isp/ae_block_mean_4.rs
+++ b/esp32p4/src/isp/ae_block_mean_4.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AE_BLOCK_MEAN_4")
-            .field(
-                "ae_b34_mean",
-                &format_args!("{}", self.ae_b34_mean().bits()),
-            )
-            .field(
-                "ae_b33_mean",
-                &format_args!("{}", self.ae_b33_mean().bits()),
-            )
-            .field(
-                "ae_b32_mean",
-                &format_args!("{}", self.ae_b32_mean().bits()),
-            )
-            .field(
-                "ae_b31_mean",
-                &format_args!("{}", self.ae_b31_mean().bits()),
-            )
+            .field("ae_b34_mean", &self.ae_b34_mean())
+            .field("ae_b33_mean", &self.ae_b33_mean())
+            .field("ae_b32_mean", &self.ae_b32_mean())
+            .field("ae_b31_mean", &self.ae_b31_mean())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AE_BLOCK_MEAN_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ae statistic result register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AE_BLOCK_MEAN_4_SPEC;
 impl crate::RegisterSpec for AE_BLOCK_MEAN_4_SPEC {
diff --git a/esp32p4/src/isp/ae_block_mean_5.rs b/esp32p4/src/isp/ae_block_mean_5.rs
index 82ef2ad70d..0066709a47 100644
--- a/esp32p4/src/isp/ae_block_mean_5.rs
+++ b/esp32p4/src/isp/ae_block_mean_5.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AE_BLOCK_MEAN_5")
-            .field(
-                "ae_b43_mean",
-                &format_args!("{}", self.ae_b43_mean().bits()),
-            )
-            .field(
-                "ae_b42_mean",
-                &format_args!("{}", self.ae_b42_mean().bits()),
-            )
-            .field(
-                "ae_b41_mean",
-                &format_args!("{}", self.ae_b41_mean().bits()),
-            )
-            .field(
-                "ae_b40_mean",
-                &format_args!("{}", self.ae_b40_mean().bits()),
-            )
+            .field("ae_b43_mean", &self.ae_b43_mean())
+            .field("ae_b42_mean", &self.ae_b42_mean())
+            .field("ae_b41_mean", &self.ae_b41_mean())
+            .field("ae_b40_mean", &self.ae_b40_mean())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AE_BLOCK_MEAN_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ae statistic result register 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AE_BLOCK_MEAN_5_SPEC;
 impl crate::RegisterSpec for AE_BLOCK_MEAN_5_SPEC {
diff --git a/esp32p4/src/isp/ae_block_mean_6.rs b/esp32p4/src/isp/ae_block_mean_6.rs
index e04a734d25..754b23c28d 100644
--- a/esp32p4/src/isp/ae_block_mean_6.rs
+++ b/esp32p4/src/isp/ae_block_mean_6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AE_BLOCK_MEAN_6")
-            .field(
-                "ae_b44_mean",
-                &format_args!("{}", self.ae_b44_mean().bits()),
-            )
+            .field("ae_b44_mean", &self.ae_b44_mean())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AE_BLOCK_MEAN_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ae statistic result register 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae_block_mean_6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AE_BLOCK_MEAN_6_SPEC;
 impl crate::RegisterSpec for AE_BLOCK_MEAN_6_SPEC {
diff --git a/esp32p4/src/isp/ae_bx.rs b/esp32p4/src/isp/ae_bx.rs
index d5f3ede600..cd117fb860 100644
--- a/esp32p4/src/isp/ae_bx.rs
+++ b/esp32p4/src/isp/ae_bx.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AE_BX")
-            .field("ae_x_bsize", &format_args!("{}", self.ae_x_bsize().bits()))
-            .field("ae_x_start", &format_args!("{}", self.ae_x_start().bits()))
+            .field("ae_x_bsize", &self.ae_x_bsize())
+            .field("ae_x_start", &self.ae_x_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AE_BX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - this field configures every block x size"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/ae_by.rs b/esp32p4/src/isp/ae_by.rs
index 1ce764bac6..8d52fbefbd 100644
--- a/esp32p4/src/isp/ae_by.rs
+++ b/esp32p4/src/isp/ae_by.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AE_BY")
-            .field("ae_y_bsize", &format_args!("{}", self.ae_y_bsize().bits()))
-            .field("ae_y_start", &format_args!("{}", self.ae_y_start().bits()))
+            .field("ae_y_bsize", &self.ae_y_bsize())
+            .field("ae_y_start", &self.ae_y_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AE_BY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - this field configures every block y size"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/ae_ctrl.rs b/esp32p4/src/isp/ae_ctrl.rs
index eadadad4db..25ba8e616c 100644
--- a/esp32p4/src/isp/ae_ctrl.rs
+++ b/esp32p4/src/isp/ae_ctrl.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AE_CTRL")
-            .field("ae_select", &format_args!("{}", self.ae_select().bit()))
+            .field("ae_select", &self.ae_select())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - write 1 to this bit triggers one statistic event"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/ae_monitor.rs b/esp32p4/src/isp/ae_monitor.rs
index 228e0214ac..d9e8536b42 100644
--- a/esp32p4/src/isp/ae_monitor.rs
+++ b/esp32p4/src/isp/ae_monitor.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AE_MONITOR")
-            .field("tl", &format_args!("{}", self.tl().bits()))
-            .field("th", &format_args!("{}", self.th().bits()))
-            .field("period", &format_args!("{}", self.period().bits()))
+            .field("tl", &self.tl())
+            .field("th", &self.th())
+            .field("period", &self.period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AE_MONITOR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the lower lum threshold of ae monitor"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/ae_win_reciprocal.rs b/esp32p4/src/isp/ae_win_reciprocal.rs
index 0817e6c5ab..0bbd06b832 100644
--- a/esp32p4/src/isp/ae_win_reciprocal.rs
+++ b/esp32p4/src/isp/ae_win_reciprocal.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AE_WIN_RECIPROCAL")
-            .field(
-                "ae_subwin_recip",
-                &format_args!("{}", self.ae_subwin_recip().bits()),
-            )
+            .field("ae_subwin_recip", &self.ae_subwin_recip())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AE_WIN_RECIPROCAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - this field configures the reciprocal of each subwin_pixnum, 20bit fraction"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/ae_winpixnum.rs b/esp32p4/src/isp/ae_winpixnum.rs
index 18ef75ea62..dec1806876 100644
--- a/esp32p4/src/isp/ae_winpixnum.rs
+++ b/esp32p4/src/isp/ae_winpixnum.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AE_WINPIXNUM")
-            .field(
-                "ae_subwin_pixnum",
-                &format_args!("{}", self.ae_subwin_pixnum().bits()),
-            )
+            .field("ae_subwin_pixnum", &self.ae_subwin_pixnum())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AE_WINPIXNUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:16 - this field configures the pixel number of each sub win"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/af_ctrl0.rs b/esp32p4/src/isp/af_ctrl0.rs
index b21f0649f1..cdef5f5612 100644
--- a/esp32p4/src/isp/af_ctrl0.rs
+++ b/esp32p4/src/isp/af_ctrl0.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_CTRL0")
-            .field(
-                "af_auto_update",
-                &format_args!("{}", self.af_auto_update().bit()),
-            )
-            .field(
-                "af_env_threshold",
-                &format_args!("{}", self.af_env_threshold().bits()),
-            )
-            .field(
-                "af_env_period",
-                &format_args!("{}", self.af_env_period().bits()),
-            )
+            .field("af_auto_update", &self.af_auto_update())
+            .field("af_env_threshold", &self.af_env_threshold())
+            .field("af_env_period", &self.af_env_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit configures auto_update enable. when set to 1, will update sum and lum each frame"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/af_ctrl1.rs b/esp32p4/src/isp/af_ctrl1.rs
index 7940869a84..e62130b071 100644
--- a/esp32p4/src/isp/af_ctrl1.rs
+++ b/esp32p4/src/isp/af_ctrl1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_CTRL1")
-            .field(
-                "af_thpixnum",
-                &format_args!("{}", self.af_thpixnum().bits()),
-            )
+            .field("af_thpixnum", &self.af_thpixnum())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - this field configures pixnum used when calculating the autofocus threshold. Set to 0 to disable threshold calculation"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/af_env_user_th_lum.rs b/esp32p4/src/isp/af_env_user_th_lum.rs
index b43b9f7292..c7b30d7831 100644
--- a/esp32p4/src/isp/af_env_user_th_lum.rs
+++ b/esp32p4/src/isp/af_env_user_th_lum.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AF_ENV_USER_TH_LUM")
             .field(
                 "af_env_user_threshold_lum",
-                &format_args!("{}", self.af_env_user_threshold_lum().bits()),
+                &self.af_env_user_threshold_lum(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_ENV_USER_TH_LUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - this field configures user setup env detect lum threshold"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/af_env_user_th_sum.rs b/esp32p4/src/isp/af_env_user_th_sum.rs
index 42d20e2e51..c5acedaffd 100644
--- a/esp32p4/src/isp/af_env_user_th_sum.rs
+++ b/esp32p4/src/isp/af_env_user_th_sum.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("AF_ENV_USER_TH_SUM")
             .field(
                 "af_env_user_threshold_sum",
-                &format_args!("{}", self.af_env_user_threshold_sum().bits()),
+                &self.af_env_user_threshold_sum(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_ENV_USER_TH_SUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - this field configures user setup env detect sum threshold"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/af_gen_th_ctrl.rs b/esp32p4/src/isp/af_gen_th_ctrl.rs
index 1384e9128e..d1d4ce4b23 100644
--- a/esp32p4/src/isp/af_gen_th_ctrl.rs
+++ b/esp32p4/src/isp/af_gen_th_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_GEN_TH_CTRL")
-            .field(
-                "af_gen_threshold_min",
-                &format_args!("{}", self.af_gen_threshold_min().bits()),
-            )
-            .field(
-                "af_gen_threshold_max",
-                &format_args!("{}", self.af_gen_threshold_max().bits()),
-            )
+            .field("af_gen_threshold_min", &self.af_gen_threshold_min())
+            .field("af_gen_threshold_max", &self.af_gen_threshold_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_GEN_TH_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - this field configures min threshold when use auto_threshold"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/af_hscale_a.rs b/esp32p4/src/isp/af_hscale_a.rs
index 989df9692d..0368d42ee2 100644
--- a/esp32p4/src/isp/af_hscale_a.rs
+++ b/esp32p4/src/isp/af_hscale_a.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_HSCALE_A")
-            .field(
-                "af_rpoint_a",
-                &format_args!("{}", self.af_rpoint_a().bits()),
-            )
-            .field(
-                "af_lpoint_a",
-                &format_args!("{}", self.af_lpoint_a().bits()),
-            )
+            .field("af_rpoint_a", &self.af_rpoint_a())
+            .field("af_lpoint_a", &self.af_lpoint_a())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_HSCALE_A_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - this field configures left coordinate of focus window a, must >= 2"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/af_hscale_b.rs b/esp32p4/src/isp/af_hscale_b.rs
index b95295dfad..d5d2957523 100644
--- a/esp32p4/src/isp/af_hscale_b.rs
+++ b/esp32p4/src/isp/af_hscale_b.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_HSCALE_B")
-            .field(
-                "af_rpoint_b",
-                &format_args!("{}", self.af_rpoint_b().bits()),
-            )
-            .field(
-                "af_lpoint_b",
-                &format_args!("{}", self.af_lpoint_b().bits()),
-            )
+            .field("af_rpoint_b", &self.af_rpoint_b())
+            .field("af_lpoint_b", &self.af_lpoint_b())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_HSCALE_B_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - this field configures left coordinate of focus window b, must >= 2"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/af_hscale_c.rs b/esp32p4/src/isp/af_hscale_c.rs
index c0be7fbf9f..efa6894a85 100644
--- a/esp32p4/src/isp/af_hscale_c.rs
+++ b/esp32p4/src/isp/af_hscale_c.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_HSCALE_C")
-            .field(
-                "af_rpoint_c",
-                &format_args!("{}", self.af_rpoint_c().bits()),
-            )
-            .field(
-                "af_lpoint_c",
-                &format_args!("{}", self.af_lpoint_c().bits()),
-            )
+            .field("af_rpoint_c", &self.af_rpoint_c())
+            .field("af_lpoint_c", &self.af_lpoint_c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_HSCALE_C_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - this field configures left coordinate of focus window c, must >= 2"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/af_lum_a.rs b/esp32p4/src/isp/af_lum_a.rs
index 88458cb71d..4d43ce1db7 100644
--- a/esp32p4/src/isp/af_lum_a.rs
+++ b/esp32p4/src/isp/af_lum_a.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_LUM_A")
-            .field("af_luma", &format_args!("{}", self.af_luma().bits()))
+            .field("af_luma", &self.af_luma())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_LUM_A_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of lum of af window a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_lum_a::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AF_LUM_A_SPEC;
 impl crate::RegisterSpec for AF_LUM_A_SPEC {
diff --git a/esp32p4/src/isp/af_lum_b.rs b/esp32p4/src/isp/af_lum_b.rs
index f3dbd2d61e..cdc18ae963 100644
--- a/esp32p4/src/isp/af_lum_b.rs
+++ b/esp32p4/src/isp/af_lum_b.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_LUM_B")
-            .field("af_lumb", &format_args!("{}", self.af_lumb().bits()))
+            .field("af_lumb", &self.af_lumb())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_LUM_B_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of lum of af window b\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_lum_b::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AF_LUM_B_SPEC;
 impl crate::RegisterSpec for AF_LUM_B_SPEC {
diff --git a/esp32p4/src/isp/af_lum_c.rs b/esp32p4/src/isp/af_lum_c.rs
index 7baabe8b76..7470be3a5f 100644
--- a/esp32p4/src/isp/af_lum_c.rs
+++ b/esp32p4/src/isp/af_lum_c.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_LUM_C")
-            .field("af_lumc", &format_args!("{}", self.af_lumc().bits()))
+            .field("af_lumc", &self.af_lumc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_LUM_C_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of lum of af window c\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_lum_c::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AF_LUM_C_SPEC;
 impl crate::RegisterSpec for AF_LUM_C_SPEC {
diff --git a/esp32p4/src/isp/af_sum_a.rs b/esp32p4/src/isp/af_sum_a.rs
index 019699c9f7..596ed2b1c8 100644
--- a/esp32p4/src/isp/af_sum_a.rs
+++ b/esp32p4/src/isp/af_sum_a.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_SUM_A")
-            .field("af_suma", &format_args!("{}", self.af_suma().bits()))
+            .field("af_suma", &self.af_suma())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_SUM_A_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of sum of af window a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_sum_a::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AF_SUM_A_SPEC;
 impl crate::RegisterSpec for AF_SUM_A_SPEC {
diff --git a/esp32p4/src/isp/af_sum_b.rs b/esp32p4/src/isp/af_sum_b.rs
index 24ce536989..530ca44117 100644
--- a/esp32p4/src/isp/af_sum_b.rs
+++ b/esp32p4/src/isp/af_sum_b.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_SUM_B")
-            .field("af_sumb", &format_args!("{}", self.af_sumb().bits()))
+            .field("af_sumb", &self.af_sumb())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_SUM_B_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of sum of af window b\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_sum_b::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AF_SUM_B_SPEC;
 impl crate::RegisterSpec for AF_SUM_B_SPEC {
diff --git a/esp32p4/src/isp/af_sum_c.rs b/esp32p4/src/isp/af_sum_c.rs
index 9b99335fdb..97b20b3438 100644
--- a/esp32p4/src/isp/af_sum_c.rs
+++ b/esp32p4/src/isp/af_sum_c.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_SUM_C")
-            .field("af_sumc", &format_args!("{}", self.af_sumc().bits()))
+            .field("af_sumc", &self.af_sumc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_SUM_C_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of sum of af window c\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`af_sum_c::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AF_SUM_C_SPEC;
 impl crate::RegisterSpec for AF_SUM_C_SPEC {
diff --git a/esp32p4/src/isp/af_threshold.rs b/esp32p4/src/isp/af_threshold.rs
index 5829509387..c5a251b9fd 100644
--- a/esp32p4/src/isp/af_threshold.rs
+++ b/esp32p4/src/isp/af_threshold.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_THRESHOLD")
-            .field(
-                "af_threshold",
-                &format_args!("{}", self.af_threshold().bits()),
-            )
-            .field(
-                "af_gen_threshold",
-                &format_args!("{}", self.af_gen_threshold().bits()),
-            )
+            .field("af_threshold", &self.af_threshold())
+            .field("af_gen_threshold", &self.af_gen_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_THRESHOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - this field configures user threshold. When set to non-zero, autofocus will use this threshold"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/af_vscale_a.rs b/esp32p4/src/isp/af_vscale_a.rs
index 03c6f2220a..cb06bdbf0f 100644
--- a/esp32p4/src/isp/af_vscale_a.rs
+++ b/esp32p4/src/isp/af_vscale_a.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_VSCALE_A")
-            .field(
-                "af_bpoint_a",
-                &format_args!("{}", self.af_bpoint_a().bits()),
-            )
-            .field(
-                "af_tpoint_a",
-                &format_args!("{}", self.af_tpoint_a().bits()),
-            )
+            .field("af_bpoint_a", &self.af_bpoint_a())
+            .field("af_tpoint_a", &self.af_tpoint_a())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_VSCALE_A_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - this field configures right coordinate of focus window a, must &lt;= hnum-2"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/af_vscale_b.rs b/esp32p4/src/isp/af_vscale_b.rs
index c18cf69268..ac2506f3dc 100644
--- a/esp32p4/src/isp/af_vscale_b.rs
+++ b/esp32p4/src/isp/af_vscale_b.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_VSCALE_B")
-            .field(
-                "af_bpoint_b",
-                &format_args!("{}", self.af_bpoint_b().bits()),
-            )
-            .field(
-                "af_tpoint_b",
-                &format_args!("{}", self.af_tpoint_b().bits()),
-            )
+            .field("af_bpoint_b", &self.af_bpoint_b())
+            .field("af_tpoint_b", &self.af_tpoint_b())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_VSCALE_B_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - this field configures right coordinate of focus window b, must &lt;= hnum-2"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/af_vscale_c.rs b/esp32p4/src/isp/af_vscale_c.rs
index 23725feccc..d126d00d3e 100644
--- a/esp32p4/src/isp/af_vscale_c.rs
+++ b/esp32p4/src/isp/af_vscale_c.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AF_VSCALE_C")
-            .field(
-                "af_bpoint_c",
-                &format_args!("{}", self.af_bpoint_c().bits()),
-            )
-            .field(
-                "af_tpoint_c",
-                &format_args!("{}", self.af_tpoint_c().bits()),
-            )
+            .field("af_bpoint_c", &self.af_bpoint_c())
+            .field("af_tpoint_c", &self.af_tpoint_c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AF_VSCALE_C_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - this field configures right coordinate of focus window c, must &lt;= hnum-2"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/awb0_acc_b.rs b/esp32p4/src/isp/awb0_acc_b.rs
index 730c47f53a..316cb05031 100644
--- a/esp32p4/src/isp/awb0_acc_b.rs
+++ b/esp32p4/src/isp/awb0_acc_b.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AWB0_ACC_B")
-            .field("awb0_acc_b", &format_args!("{}", self.awb0_acc_b().bits()))
+            .field("awb0_acc_b", &self.awb0_acc_b())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AWB0_ACC_B_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of accumulate of b channel of all white points\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb0_acc_b::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AWB0_ACC_B_SPEC;
 impl crate::RegisterSpec for AWB0_ACC_B_SPEC {
diff --git a/esp32p4/src/isp/awb0_acc_g.rs b/esp32p4/src/isp/awb0_acc_g.rs
index b87cf3ca64..f58df8dbb2 100644
--- a/esp32p4/src/isp/awb0_acc_g.rs
+++ b/esp32p4/src/isp/awb0_acc_g.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AWB0_ACC_G")
-            .field("awb0_acc_g", &format_args!("{}", self.awb0_acc_g().bits()))
+            .field("awb0_acc_g", &self.awb0_acc_g())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AWB0_ACC_G_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of accumulate of g channel of all white points\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb0_acc_g::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AWB0_ACC_G_SPEC;
 impl crate::RegisterSpec for AWB0_ACC_G_SPEC {
diff --git a/esp32p4/src/isp/awb0_acc_r.rs b/esp32p4/src/isp/awb0_acc_r.rs
index e2a7974e56..767418a7a4 100644
--- a/esp32p4/src/isp/awb0_acc_r.rs
+++ b/esp32p4/src/isp/awb0_acc_r.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AWB0_ACC_R")
-            .field("awb0_acc_r", &format_args!("{}", self.awb0_acc_r().bits()))
+            .field("awb0_acc_r", &self.awb0_acc_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AWB0_ACC_R_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of accumulate of r channel of all white points\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb0_acc_r::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AWB0_ACC_R_SPEC;
 impl crate::RegisterSpec for AWB0_ACC_R_SPEC {
diff --git a/esp32p4/src/isp/awb0_white_cnt.rs b/esp32p4/src/isp/awb0_white_cnt.rs
index d48ecd57ff..2f482f0fd0 100644
--- a/esp32p4/src/isp/awb0_white_cnt.rs
+++ b/esp32p4/src/isp/awb0_white_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AWB0_WHITE_CNT")
-            .field(
-                "awb0_white_cnt",
-                &format_args!("{}", self.awb0_white_cnt().bits()),
-            )
+            .field("awb0_white_cnt", &self.awb0_white_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AWB0_WHITE_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of awb white point number\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`awb0_white_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AWB0_WHITE_CNT_SPEC;
 impl crate::RegisterSpec for AWB0_WHITE_CNT_SPEC {
diff --git a/esp32p4/src/isp/awb_hscale.rs b/esp32p4/src/isp/awb_hscale.rs
index 550fe7bb3f..a94d727429 100644
--- a/esp32p4/src/isp/awb_hscale.rs
+++ b/esp32p4/src/isp/awb_hscale.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AWB_HSCALE")
-            .field("awb_rpoint", &format_args!("{}", self.awb_rpoint().bits()))
-            .field("awb_lpoint", &format_args!("{}", self.awb_lpoint().bits()))
+            .field("awb_rpoint", &self.awb_rpoint())
+            .field("awb_lpoint", &self.awb_lpoint())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AWB_HSCALE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - this field configures awb window right coordinate"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/awb_mode.rs b/esp32p4/src/isp/awb_mode.rs
index a651e7c35b..f9e93a5e8f 100644
--- a/esp32p4/src/isp/awb_mode.rs
+++ b/esp32p4/src/isp/awb_mode.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AWB_MODE")
-            .field("awb_mode", &format_args!("{}", self.awb_mode().bits()))
-            .field("awb_sample", &format_args!("{}", self.awb_sample().bit()))
+            .field("awb_mode", &self.awb_mode())
+            .field("awb_sample", &self.awb_sample())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AWB_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - this field configures awb algo sel. 00: none sellected. 01: sel algo0. 10: sel algo1. 11: sel both algo0 and algo1"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/awb_th_bg.rs b/esp32p4/src/isp/awb_th_bg.rs
index 22ba5c3abf..50b17c3a26 100644
--- a/esp32p4/src/isp/awb_th_bg.rs
+++ b/esp32p4/src/isp/awb_th_bg.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AWB_TH_BG")
-            .field("awb_min_bg", &format_args!("{}", self.awb_min_bg().bits()))
-            .field("awb_max_bg", &format_args!("{}", self.awb_max_bg().bits()))
+            .field("awb_min_bg", &self.awb_min_bg())
+            .field("awb_max_bg", &self.awb_max_bg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AWB_TH_BG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - this field configures lower threshold of b/g, 2bit integer and 8bit fraction"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/awb_th_lum.rs b/esp32p4/src/isp/awb_th_lum.rs
index bfffef0501..49127565dc 100644
--- a/esp32p4/src/isp/awb_th_lum.rs
+++ b/esp32p4/src/isp/awb_th_lum.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AWB_TH_LUM")
-            .field(
-                "awb_min_lum",
-                &format_args!("{}", self.awb_min_lum().bits()),
-            )
-            .field(
-                "awb_max_lum",
-                &format_args!("{}", self.awb_max_lum().bits()),
-            )
+            .field("awb_min_lum", &self.awb_min_lum())
+            .field("awb_max_lum", &self.awb_max_lum())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AWB_TH_LUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - this field configures lower threshold of r+g+b"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/awb_th_rg.rs b/esp32p4/src/isp/awb_th_rg.rs
index f773b408d8..14e3ae592d 100644
--- a/esp32p4/src/isp/awb_th_rg.rs
+++ b/esp32p4/src/isp/awb_th_rg.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AWB_TH_RG")
-            .field("awb_min_rg", &format_args!("{}", self.awb_min_rg().bits()))
-            .field("awb_max_rg", &format_args!("{}", self.awb_max_rg().bits()))
+            .field("awb_min_rg", &self.awb_min_rg())
+            .field("awb_max_rg", &self.awb_max_rg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AWB_TH_RG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - this field configures lower threshold of r/g, 2bit integer and 8bit fraction"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/awb_vscale.rs b/esp32p4/src/isp/awb_vscale.rs
index 83fd5a5b36..09be42ce1e 100644
--- a/esp32p4/src/isp/awb_vscale.rs
+++ b/esp32p4/src/isp/awb_vscale.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AWB_VSCALE")
-            .field("awb_bpoint", &format_args!("{}", self.awb_bpoint().bits()))
-            .field("awb_tpoint", &format_args!("{}", self.awb_tpoint().bits()))
+            .field("awb_bpoint", &self.awb_bpoint())
+            .field("awb_tpoint", &self.awb_tpoint())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AWB_VSCALE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - this field configures awb window bottom coordinate"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/bf_gau0.rs b/esp32p4/src/isp/bf_gau0.rs
index 5517396d5c..9b88876767 100644
--- a/esp32p4/src/isp/bf_gau0.rs
+++ b/esp32p4/src/isp/bf_gau0.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BF_GAU0")
-            .field(
-                "gau_template21",
-                &format_args!("{}", self.gau_template21().bits()),
-            )
-            .field(
-                "gau_template20",
-                &format_args!("{}", self.gau_template20().bits()),
-            )
-            .field(
-                "gau_template12",
-                &format_args!("{}", self.gau_template12().bits()),
-            )
-            .field(
-                "gau_template11",
-                &format_args!("{}", self.gau_template11().bits()),
-            )
-            .field(
-                "gau_template10",
-                &format_args!("{}", self.gau_template10().bits()),
-            )
-            .field(
-                "gau_template02",
-                &format_args!("{}", self.gau_template02().bits()),
-            )
-            .field(
-                "gau_template01",
-                &format_args!("{}", self.gau_template01().bits()),
-            )
-            .field(
-                "gau_template00",
-                &format_args!("{}", self.gau_template00().bits()),
-            )
+            .field("gau_template21", &self.gau_template21())
+            .field("gau_template20", &self.gau_template20())
+            .field("gau_template12", &self.gau_template12())
+            .field("gau_template11", &self.gau_template11())
+            .field("gau_template10", &self.gau_template10())
+            .field("gau_template02", &self.gau_template02())
+            .field("gau_template01", &self.gau_template01())
+            .field("gau_template00", &self.gau_template00())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BF_GAU0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - this field configures index 21 of gausian template"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/bf_gau1.rs b/esp32p4/src/isp/bf_gau1.rs
index 74802898ef..98f581f6ac 100644
--- a/esp32p4/src/isp/bf_gau1.rs
+++ b/esp32p4/src/isp/bf_gau1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BF_GAU1")
-            .field(
-                "gau_template22",
-                &format_args!("{}", self.gau_template22().bits()),
-            )
+            .field("gau_template22", &self.gau_template22())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BF_GAU1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - this field configures index 22 of gausian template"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/bf_matrix_ctrl.rs b/esp32p4/src/isp/bf_matrix_ctrl.rs
index 5e8845d1c2..229b7a505c 100644
--- a/esp32p4/src/isp/bf_matrix_ctrl.rs
+++ b/esp32p4/src/isp/bf_matrix_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BF_MATRIX_CTRL")
-            .field(
-                "bf_tail_pixen_pulse_tl",
-                &format_args!("{}", self.bf_tail_pixen_pulse_tl().bits()),
-            )
-            .field(
-                "bf_tail_pixen_pulse_th",
-                &format_args!("{}", self.bf_tail_pixen_pulse_th().bits()),
-            )
-            .field(
-                "bf_padding_data",
-                &format_args!("{}", self.bf_padding_data().bits()),
-            )
-            .field(
-                "bf_padding_mode",
-                &format_args!("{}", self.bf_padding_mode().bit()),
-            )
+            .field("bf_tail_pixen_pulse_tl", &self.bf_tail_pixen_pulse_tl())
+            .field("bf_tail_pixen_pulse_th", &self.bf_tail_pixen_pulse_th())
+            .field("bf_padding_data", &self.bf_padding_data())
+            .field("bf_padding_mode", &self.bf_padding_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BF_MATRIX_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th &lt; reg_bf_tail_pixen_pulse_tl will enable tail pulse function"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/bf_sigma.rs b/esp32p4/src/isp/bf_sigma.rs
index 8f386b14c4..5a9cf94302 100644
--- a/esp32p4/src/isp/bf_sigma.rs
+++ b/esp32p4/src/isp/bf_sigma.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BF_SIGMA")
-            .field("sigma", &format_args!("{}", self.sigma().bits()))
+            .field("sigma", &self.sigma())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BF_SIGMA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - this field configures the bayer denoising level, valid data from 2 to 20"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/blc_ctrl0.rs b/esp32p4/src/isp/blc_ctrl0.rs
index 27a2c5e2d4..b0e367851f 100644
--- a/esp32p4/src/isp/blc_ctrl0.rs
+++ b/esp32p4/src/isp/blc_ctrl0.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLC_CTRL0")
-            .field(
-                "blc_r3_stretch",
-                &format_args!("{}", self.blc_r3_stretch().bit()),
-            )
-            .field(
-                "blc_r2_stretch",
-                &format_args!("{}", self.blc_r2_stretch().bit()),
-            )
-            .field(
-                "blc_r1_stretch",
-                &format_args!("{}", self.blc_r1_stretch().bit()),
-            )
-            .field(
-                "blc_r0_stretch",
-                &format_args!("{}", self.blc_r0_stretch().bit()),
-            )
+            .field("blc_r3_stretch", &self.blc_r3_stretch())
+            .field("blc_r2_stretch", &self.blc_r2_stretch())
+            .field("blc_r1_stretch", &self.blc_r1_stretch())
+            .field("blc_r0_stretch", &self.blc_r0_stretch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLC_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit configures the stretch feature of bottom right channel. 0: stretch disable, 1: stretch enable"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/blc_ctrl1.rs b/esp32p4/src/isp/blc_ctrl1.rs
index bcab7fb743..17a5429540 100644
--- a/esp32p4/src/isp/blc_ctrl1.rs
+++ b/esp32p4/src/isp/blc_ctrl1.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLC_CTRL1")
-            .field(
-                "blc_window_top",
-                &format_args!("{}", self.blc_window_top().bits()),
-            )
-            .field(
-                "blc_window_left",
-                &format_args!("{}", self.blc_window_left().bits()),
-            )
-            .field(
-                "blc_window_vnum",
-                &format_args!("{}", self.blc_window_vnum().bits()),
-            )
-            .field(
-                "blc_window_hnum",
-                &format_args!("{}", self.blc_window_hnum().bits()),
-            )
-            .field(
-                "blc_filter_en",
-                &format_args!("{}", self.blc_filter_en().bit()),
-            )
+            .field("blc_window_top", &self.blc_window_top())
+            .field("blc_window_left", &self.blc_window_left())
+            .field("blc_window_vnum", &self.blc_window_vnum())
+            .field("blc_window_hnum", &self.blc_window_hnum())
+            .field("blc_filter_en", &self.blc_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLC_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - this field configures blc average calculation window top"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/blc_ctrl2.rs b/esp32p4/src/isp/blc_ctrl2.rs
index 2f375640fe..be24250653 100644
--- a/esp32p4/src/isp/blc_ctrl2.rs
+++ b/esp32p4/src/isp/blc_ctrl2.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLC_CTRL2")
-            .field("blc_r3_th", &format_args!("{}", self.blc_r3_th().bits()))
-            .field("blc_r2_th", &format_args!("{}", self.blc_r2_th().bits()))
-            .field("blc_r1_th", &format_args!("{}", self.blc_r1_th().bits()))
-            .field("blc_r0_th", &format_args!("{}", self.blc_r0_th().bits()))
+            .field("blc_r3_th", &self.blc_r3_th())
+            .field("blc_r2_th", &self.blc_r2_th())
+            .field("blc_r1_th", &self.blc_r1_th())
+            .field("blc_r0_th", &self.blc_r0_th())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLC_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures black threshold when get blc average of bottom right channel"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/blc_mean.rs b/esp32p4/src/isp/blc_mean.rs
index ca6fd9d4a9..3c51788a32 100644
--- a/esp32p4/src/isp/blc_mean.rs
+++ b/esp32p4/src/isp/blc_mean.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLC_MEAN")
-            .field(
-                "blc_r3_mean",
-                &format_args!("{}", self.blc_r3_mean().bits()),
-            )
-            .field(
-                "blc_r2_mean",
-                &format_args!("{}", self.blc_r2_mean().bits()),
-            )
-            .field(
-                "blc_r1_mean",
-                &format_args!("{}", self.blc_r1_mean().bits()),
-            )
-            .field(
-                "blc_r0_mean",
-                &format_args!("{}", self.blc_r0_mean().bits()),
-            )
+            .field("blc_r3_mean", &self.blc_r3_mean())
+            .field("blc_r2_mean", &self.blc_r2_mean())
+            .field("blc_r1_mean", &self.blc_r1_mean())
+            .field("blc_r0_mean", &self.blc_r0_mean())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLC_MEAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "results of the average of black window\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blc_mean::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLC_MEAN_SPEC;
 impl crate::RegisterSpec for BLC_MEAN_SPEC {
diff --git a/esp32p4/src/isp/blc_value.rs b/esp32p4/src/isp/blc_value.rs
index 7ff76c5f23..3dbfe585f0 100644
--- a/esp32p4/src/isp/blc_value.rs
+++ b/esp32p4/src/isp/blc_value.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLC_VALUE")
-            .field(
-                "blc_r3_value",
-                &format_args!("{}", self.blc_r3_value().bits()),
-            )
-            .field(
-                "blc_r2_value",
-                &format_args!("{}", self.blc_r2_value().bits()),
-            )
-            .field(
-                "blc_r1_value",
-                &format_args!("{}", self.blc_r1_value().bits()),
-            )
-            .field(
-                "blc_r0_value",
-                &format_args!("{}", self.blc_r0_value().bits()),
-            )
+            .field("blc_r3_value", &self.blc_r3_value())
+            .field("blc_r2_value", &self.blc_r2_value())
+            .field("blc_r1_value", &self.blc_r1_value())
+            .field("blc_r0_value", &self.blc_r0_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLC_VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the black level of bottom right channel of bayer img"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/cam_cntl.rs b/esp32p4/src/isp/cam_cntl.rs
index b2e1a1022f..d0c54fd288 100644
--- a/esp32p4/src/isp/cam_cntl.rs
+++ b/esp32p4/src/isp/cam_cntl.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAM_CNTL")
-            .field("cam_en", &format_args!("{}", self.cam_en().bit()))
-            .field("cam_update", &format_args!("{}", self.cam_update().bit()))
-            .field("cam_reset", &format_args!("{}", self.cam_reset().bit()))
-            .field("cam_clk_inv", &format_args!("{}", self.cam_clk_inv().bit()))
+            .field("cam_en", &self.cam_en())
+            .field("cam_update", &self.cam_update())
+            .field("cam_reset", &self.cam_reset())
+            .field("cam_clk_inv", &self.cam_clk_inv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAM_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - write 1 to start recive camera data, write 0 to disable"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/cam_conf.rs b/esp32p4/src/isp/cam_conf.rs
index d6a33c6d75..265c370661 100644
--- a/esp32p4/src/isp/cam_conf.rs
+++ b/esp32p4/src/isp/cam_conf.rs
@@ -80,44 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAM_CONF")
-            .field(
-                "cam_data_order",
-                &format_args!("{}", self.cam_data_order().bit()),
-            )
-            .field(
-                "cam_2byte_mode",
-                &format_args!("{}", self.cam_2byte_mode().bit()),
-            )
-            .field(
-                "cam_data_type",
-                &format_args!("{}", self.cam_data_type().bits()),
-            )
-            .field("cam_de_inv", &format_args!("{}", self.cam_de_inv().bit()))
-            .field(
-                "cam_hsync_inv",
-                &format_args!("{}", self.cam_hsync_inv().bit()),
-            )
-            .field(
-                "cam_vsync_inv",
-                &format_args!("{}", self.cam_vsync_inv().bit()),
-            )
-            .field(
-                "cam_vsync_filter_thres",
-                &format_args!("{}", self.cam_vsync_filter_thres().bits()),
-            )
-            .field(
-                "cam_vsync_filter_en",
-                &format_args!("{}", self.cam_vsync_filter_en().bit()),
-            )
+            .field("cam_data_order", &self.cam_data_order())
+            .field("cam_2byte_mode", &self.cam_2byte_mode())
+            .field("cam_data_type", &self.cam_data_type())
+            .field("cam_de_inv", &self.cam_de_inv())
+            .field("cam_hsync_inv", &self.cam_hsync_inv())
+            .field("cam_vsync_inv", &self.cam_vsync_inv())
+            .field("cam_vsync_filter_thres", &self.cam_vsync_filter_thres())
+            .field("cam_vsync_filter_en", &self.cam_vsync_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in\\[7:0\\], cam_data_in\\[15:8\\]}"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/ccm_coef0.rs b/esp32p4/src/isp/ccm_coef0.rs
index 27a58bad46..2ee0ac22dc 100644
--- a/esp32p4/src/isp/ccm_coef0.rs
+++ b/esp32p4/src/isp/ccm_coef0.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CCM_COEF0")
-            .field("ccm_rr", &format_args!("{}", self.ccm_rr().bits()))
-            .field("ccm_rg", &format_args!("{}", self.ccm_rg().bits()))
+            .field("ccm_rr", &self.ccm_rr())
+            .field("ccm_rg", &self.ccm_rg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CCM_COEF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - this field configures the color correction matrix coefficient"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/ccm_coef1.rs b/esp32p4/src/isp/ccm_coef1.rs
index df4f1b0205..c982ec6156 100644
--- a/esp32p4/src/isp/ccm_coef1.rs
+++ b/esp32p4/src/isp/ccm_coef1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CCM_COEF1")
-            .field("ccm_rb", &format_args!("{}", self.ccm_rb().bits()))
-            .field("ccm_gr", &format_args!("{}", self.ccm_gr().bits()))
+            .field("ccm_rb", &self.ccm_rb())
+            .field("ccm_gr", &self.ccm_gr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CCM_COEF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - this field configures the color correction matrix coefficient"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/ccm_coef3.rs b/esp32p4/src/isp/ccm_coef3.rs
index 2f8b988e24..40040838be 100644
--- a/esp32p4/src/isp/ccm_coef3.rs
+++ b/esp32p4/src/isp/ccm_coef3.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CCM_COEF3")
-            .field("ccm_gg", &format_args!("{}", self.ccm_gg().bits()))
-            .field("ccm_gb", &format_args!("{}", self.ccm_gb().bits()))
+            .field("ccm_gg", &self.ccm_gg())
+            .field("ccm_gb", &self.ccm_gb())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CCM_COEF3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - this field configures the color correction matrix coefficient"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/ccm_coef4.rs b/esp32p4/src/isp/ccm_coef4.rs
index 4968df04ca..970d4cb59e 100644
--- a/esp32p4/src/isp/ccm_coef4.rs
+++ b/esp32p4/src/isp/ccm_coef4.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CCM_COEF4")
-            .field("ccm_br", &format_args!("{}", self.ccm_br().bits()))
-            .field("ccm_bg", &format_args!("{}", self.ccm_bg().bits()))
+            .field("ccm_br", &self.ccm_br())
+            .field("ccm_bg", &self.ccm_bg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CCM_COEF4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - this field configures the color correction matrix coefficient"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/ccm_coef5.rs b/esp32p4/src/isp/ccm_coef5.rs
index 8e1235390e..a220ebb455 100644
--- a/esp32p4/src/isp/ccm_coef5.rs
+++ b/esp32p4/src/isp/ccm_coef5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CCM_COEF5")
-            .field("ccm_bb", &format_args!("{}", self.ccm_bb().bits()))
+            .field("ccm_bb", &self.ccm_bb())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CCM_COEF5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - this field configures the color correction matrix coefficient"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/clk_en.rs b/esp32p4/src/isp/clk_en.rs
index 31cd01fc27..58f3d0075f 100644
--- a/esp32p4/src/isp/clk_en.rs
+++ b/esp32p4/src/isp/clk_en.rs
@@ -179,88 +179,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EN")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "clk_blc_force_on",
-                &format_args!("{}", self.clk_blc_force_on().bit()),
-            )
-            .field(
-                "clk_dpc_force_on",
-                &format_args!("{}", self.clk_dpc_force_on().bit()),
-            )
-            .field(
-                "clk_bf_force_on",
-                &format_args!("{}", self.clk_bf_force_on().bit()),
-            )
-            .field(
-                "clk_lsc_force_on",
-                &format_args!("{}", self.clk_lsc_force_on().bit()),
-            )
-            .field(
-                "clk_demosaic_force_on",
-                &format_args!("{}", self.clk_demosaic_force_on().bit()),
-            )
-            .field(
-                "clk_median_force_on",
-                &format_args!("{}", self.clk_median_force_on().bit()),
-            )
-            .field(
-                "clk_ccm_force_on",
-                &format_args!("{}", self.clk_ccm_force_on().bit()),
-            )
-            .field(
-                "clk_gamma_force_on",
-                &format_args!("{}", self.clk_gamma_force_on().bit()),
-            )
-            .field(
-                "clk_rgb2yuv_force_on",
-                &format_args!("{}", self.clk_rgb2yuv_force_on().bit()),
-            )
-            .field(
-                "clk_sharp_force_on",
-                &format_args!("{}", self.clk_sharp_force_on().bit()),
-            )
-            .field(
-                "clk_color_force_on",
-                &format_args!("{}", self.clk_color_force_on().bit()),
-            )
-            .field(
-                "clk_yuv2rgb_force_on",
-                &format_args!("{}", self.clk_yuv2rgb_force_on().bit()),
-            )
-            .field(
-                "clk_ae_force_on",
-                &format_args!("{}", self.clk_ae_force_on().bit()),
-            )
-            .field(
-                "clk_af_force_on",
-                &format_args!("{}", self.clk_af_force_on().bit()),
-            )
-            .field(
-                "clk_awb_force_on",
-                &format_args!("{}", self.clk_awb_force_on().bit()),
-            )
-            .field(
-                "clk_hist_force_on",
-                &format_args!("{}", self.clk_hist_force_on().bit()),
-            )
-            .field(
-                "clk_mipi_idi_force_on",
-                &format_args!("{}", self.clk_mipi_idi_force_on().bit()),
-            )
-            .field(
-                "isp_mem_clk_force_on",
-                &format_args!("{}", self.isp_mem_clk_force_on().bit()),
-            )
+            .field("clk_en", &self.clk_en())
+            .field("clk_blc_force_on", &self.clk_blc_force_on())
+            .field("clk_dpc_force_on", &self.clk_dpc_force_on())
+            .field("clk_bf_force_on", &self.clk_bf_force_on())
+            .field("clk_lsc_force_on", &self.clk_lsc_force_on())
+            .field("clk_demosaic_force_on", &self.clk_demosaic_force_on())
+            .field("clk_median_force_on", &self.clk_median_force_on())
+            .field("clk_ccm_force_on", &self.clk_ccm_force_on())
+            .field("clk_gamma_force_on", &self.clk_gamma_force_on())
+            .field("clk_rgb2yuv_force_on", &self.clk_rgb2yuv_force_on())
+            .field("clk_sharp_force_on", &self.clk_sharp_force_on())
+            .field("clk_color_force_on", &self.clk_color_force_on())
+            .field("clk_yuv2rgb_force_on", &self.clk_yuv2rgb_force_on())
+            .field("clk_ae_force_on", &self.clk_ae_force_on())
+            .field("clk_af_force_on", &self.clk_af_force_on())
+            .field("clk_awb_force_on", &self.clk_awb_force_on())
+            .field("clk_hist_force_on", &self.clk_hist_force_on())
+            .field("clk_mipi_idi_force_on", &self.clk_mipi_idi_force_on())
+            .field("isp_mem_clk_force_on", &self.isp_mem_clk_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit configures the clk force on of isp reg. 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/cntl.rs b/esp32p4/src/isp/cntl.rs
index 2ffc7977b5..5982d6db2d 100644
--- a/esp32p4/src/isp/cntl.rs
+++ b/esp32p4/src/isp/cntl.rs
@@ -206,49 +206,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CNTL")
-            .field(
-                "mipi_data_en",
-                &format_args!("{}", self.mipi_data_en().bit()),
-            )
-            .field("isp_en", &format_args!("{}", self.isp_en().bit()))
-            .field("blc_en", &format_args!("{}", self.blc_en().bit()))
-            .field("dpc_en", &format_args!("{}", self.dpc_en().bit()))
-            .field("bf_en", &format_args!("{}", self.bf_en().bit()))
-            .field("lsc_en", &format_args!("{}", self.lsc_en().bit()))
-            .field("demosaic_en", &format_args!("{}", self.demosaic_en().bit()))
-            .field("median_en", &format_args!("{}", self.median_en().bit()))
-            .field("ccm_en", &format_args!("{}", self.ccm_en().bit()))
-            .field("gamma_en", &format_args!("{}", self.gamma_en().bit()))
-            .field("rgb2yuv_en", &format_args!("{}", self.rgb2yuv_en().bit()))
-            .field("sharp_en", &format_args!("{}", self.sharp_en().bit()))
-            .field("color_en", &format_args!("{}", self.color_en().bit()))
-            .field("yuv2rgb_en", &format_args!("{}", self.yuv2rgb_en().bit()))
-            .field("ae_en", &format_args!("{}", self.ae_en().bit()))
-            .field("af_en", &format_args!("{}", self.af_en().bit()))
-            .field("awb_en", &format_args!("{}", self.awb_en().bit()))
-            .field("hist_en", &format_args!("{}", self.hist_en().bit()))
-            .field(
-                "byte_endian_order",
-                &format_args!("{}", self.byte_endian_order().bit()),
-            )
-            .field(
-                "isp_data_type",
-                &format_args!("{}", self.isp_data_type().bits()),
-            )
-            .field("isp_in_src", &format_args!("{}", self.isp_in_src().bits()))
-            .field(
-                "isp_out_type",
-                &format_args!("{}", self.isp_out_type().bits()),
-            )
+            .field("mipi_data_en", &self.mipi_data_en())
+            .field("isp_en", &self.isp_en())
+            .field("blc_en", &self.blc_en())
+            .field("dpc_en", &self.dpc_en())
+            .field("bf_en", &self.bf_en())
+            .field("lsc_en", &self.lsc_en())
+            .field("demosaic_en", &self.demosaic_en())
+            .field("median_en", &self.median_en())
+            .field("ccm_en", &self.ccm_en())
+            .field("gamma_en", &self.gamma_en())
+            .field("rgb2yuv_en", &self.rgb2yuv_en())
+            .field("sharp_en", &self.sharp_en())
+            .field("color_en", &self.color_en())
+            .field("yuv2rgb_en", &self.yuv2rgb_en())
+            .field("ae_en", &self.ae_en())
+            .field("af_en", &self.af_en())
+            .field("awb_en", &self.awb_en())
+            .field("hist_en", &self.hist_en())
+            .field("byte_endian_order", &self.byte_endian_order())
+            .field("isp_data_type", &self.isp_data_type())
+            .field("isp_in_src", &self.isp_in_src())
+            .field("isp_out_type", &self.isp_out_type())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit configures mipi input data enable. 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/color_ctrl.rs b/esp32p4/src/isp/color_ctrl.rs
index 7c29f155d7..92a1e0d6a4 100644
--- a/esp32p4/src/isp/color_ctrl.rs
+++ b/esp32p4/src/isp/color_ctrl.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COLOR_CTRL")
-            .field(
-                "color_saturation",
-                &format_args!("{}", self.color_saturation().bits()),
-            )
-            .field("color_hue", &format_args!("{}", self.color_hue().bits()))
-            .field(
-                "color_contrast",
-                &format_args!("{}", self.color_contrast().bits()),
-            )
-            .field(
-                "color_brightness",
-                &format_args!("{}", self.color_brightness().bits()),
-            )
+            .field("color_saturation", &self.color_saturation())
+            .field("color_hue", &self.color_hue())
+            .field("color_contrast", &self.color_contrast())
+            .field("color_brightness", &self.color_brightness())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COLOR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the color saturation value"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/demosaic_grad_ratio.rs b/esp32p4/src/isp/demosaic_grad_ratio.rs
index 09544298fd..bb1ea7a7ff 100644
--- a/esp32p4/src/isp/demosaic_grad_ratio.rs
+++ b/esp32p4/src/isp/demosaic_grad_ratio.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEMOSAIC_GRAD_RATIO")
-            .field(
-                "demosaic_grad_ratio",
-                &format_args!("{}", self.demosaic_grad_ratio().bits()),
-            )
+            .field("demosaic_grad_ratio", &self.demosaic_grad_ratio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEMOSAIC_GRAD_RATIO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - this field configures demosaic gradient select ratio"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/demosaic_matrix_ctrl.rs b/esp32p4/src/isp/demosaic_matrix_ctrl.rs
index be0724bd16..2935c6ce43 100644
--- a/esp32p4/src/isp/demosaic_matrix_ctrl.rs
+++ b/esp32p4/src/isp/demosaic_matrix_ctrl.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("DEMOSAIC_MATRIX_CTRL")
             .field(
                 "demosaic_tail_pixen_pulse_tl",
-                &format_args!("{}", self.demosaic_tail_pixen_pulse_tl().bits()),
+                &self.demosaic_tail_pixen_pulse_tl(),
             )
             .field(
                 "demosaic_tail_pixen_pulse_th",
-                &format_args!("{}", self.demosaic_tail_pixen_pulse_th().bits()),
-            )
-            .field(
-                "demosaic_padding_data",
-                &format_args!("{}", self.demosaic_padding_data().bits()),
-            )
-            .field(
-                "demosaic_padding_mode",
-                &format_args!("{}", self.demosaic_padding_mode().bit()),
+                &self.demosaic_tail_pixen_pulse_th(),
             )
+            .field("demosaic_padding_data", &self.demosaic_padding_data())
+            .field("demosaic_padding_mode", &self.demosaic_padding_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEMOSAIC_MATRIX_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th &lt; reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/dma_cntl.rs b/esp32p4/src/isp/dma_cntl.rs
index 18fc42408a..128a69cb65 100644
--- a/esp32p4/src/isp/dma_cntl.rs
+++ b/esp32p4/src/isp/dma_cntl.rs
@@ -46,28 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CNTL")
-            .field("dma_update", &format_args!("{}", self.dma_update().bit()))
-            .field(
-                "dma_data_type",
-                &format_args!("{}", self.dma_data_type().bits()),
-            )
-            .field(
-                "dma_burst_len",
-                &format_args!("{}", self.dma_burst_len().bits()),
-            )
-            .field(
-                "dma_interval",
-                &format_args!("{}", self.dma_interval().bits()),
-            )
+            .field("dma_update", &self.dma_update())
+            .field("dma_data_type", &self.dma_data_type())
+            .field("dma_burst_len", &self.dma_burst_len())
+            .field("dma_interval", &self.dma_interval())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - write 1 to triger dma to get 1 frame"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/dma_raw_data.rs b/esp32p4/src/isp/dma_raw_data.rs
index 0a57bc5ef9..2dd850e8c5 100644
--- a/esp32p4/src/isp/dma_raw_data.rs
+++ b/esp32p4/src/isp/dma_raw_data.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_RAW_DATA")
-            .field(
-                "dma_raw_num_total",
-                &format_args!("{}", self.dma_raw_num_total().bits()),
-            )
+            .field("dma_raw_num_total", &self.dma_raw_num_total())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_RAW_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - this field configures the the number of 64bits in a frame"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/dpc_conf.rs b/esp32p4/src/isp/dpc_conf.rs
index b23bfc81e9..78a6546022 100644
--- a/esp32p4/src/isp/dpc_conf.rs
+++ b/esp32p4/src/isp/dpc_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPC_CONF")
-            .field(
-                "dpc_threshold_l",
-                &format_args!("{}", self.dpc_threshold_l().bits()),
-            )
-            .field(
-                "dpc_threshold_h",
-                &format_args!("{}", self.dpc_threshold_h().bits()),
-            )
-            .field(
-                "dpc_factor_dark",
-                &format_args!("{}", self.dpc_factor_dark().bits()),
-            )
-            .field(
-                "dpc_factor_brig",
-                &format_args!("{}", self.dpc_factor_brig().bits()),
-            )
+            .field("dpc_threshold_l", &self.dpc_threshold_l())
+            .field("dpc_threshold_h", &self.dpc_threshold_h())
+            .field("dpc_factor_dark", &self.dpc_factor_dark())
+            .field("dpc_factor_brig", &self.dpc_factor_brig())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this bit configures the threshold to detect black img in check mode, or the low threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/dpc_ctrl.rs b/esp32p4/src/isp/dpc_ctrl.rs
index 0d6e62b7ff..e2c0a43bab 100644
--- a/esp32p4/src/isp/dpc_ctrl.rs
+++ b/esp32p4/src/isp/dpc_ctrl.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPC_CTRL")
-            .field(
-                "dpc_check_en",
-                &format_args!("{}", self.dpc_check_en().bit()),
-            )
-            .field("sta_en", &format_args!("{}", self.sta_en().bit()))
-            .field("dyn_en", &format_args!("{}", self.dyn_en().bit()))
-            .field(
-                "dpc_black_en",
-                &format_args!("{}", self.dpc_black_en().bit()),
-            )
-            .field(
-                "dpc_method_sel",
-                &format_args!("{}", self.dpc_method_sel().bit()),
-            )
-            .field(
-                "dpc_check_od_en",
-                &format_args!("{}", self.dpc_check_od_en().bit()),
-            )
+            .field("dpc_check_en", &self.dpc_check_en())
+            .field("sta_en", &self.sta_en())
+            .field("dyn_en", &self.dyn_en())
+            .field("dpc_black_en", &self.dpc_black_en())
+            .field("dpc_method_sel", &self.dpc_method_sel())
+            .field("dpc_check_od_en", &self.dpc_check_od_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit configures the check mode enable. 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/dpc_deadpix_cnt.rs b/esp32p4/src/isp/dpc_deadpix_cnt.rs
index fb870f0171..ce21af90f7 100644
--- a/esp32p4/src/isp/dpc_deadpix_cnt.rs
+++ b/esp32p4/src/isp/dpc_deadpix_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPC_DEADPIX_CNT")
-            .field(
-                "dpc_deadpix_cnt",
-                &format_args!("{}", self.dpc_deadpix_cnt().bits()),
-            )
+            .field("dpc_deadpix_cnt", &self.dpc_deadpix_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPC_DEADPIX_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DPC dead-pix number register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpc_deadpix_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DPC_DEADPIX_CNT_SPEC;
 impl crate::RegisterSpec for DPC_DEADPIX_CNT_SPEC {
diff --git a/esp32p4/src/isp/dpc_matrix_ctrl.rs b/esp32p4/src/isp/dpc_matrix_ctrl.rs
index 9ec1458b01..c53703d9e7 100644
--- a/esp32p4/src/isp/dpc_matrix_ctrl.rs
+++ b/esp32p4/src/isp/dpc_matrix_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPC_MATRIX_CTRL")
-            .field(
-                "dpc_tail_pixen_pulse_tl",
-                &format_args!("{}", self.dpc_tail_pixen_pulse_tl().bits()),
-            )
-            .field(
-                "dpc_tail_pixen_pulse_th",
-                &format_args!("{}", self.dpc_tail_pixen_pulse_th().bits()),
-            )
-            .field(
-                "dpc_padding_data",
-                &format_args!("{}", self.dpc_padding_data().bits()),
-            )
-            .field(
-                "dpc_padding_mode",
-                &format_args!("{}", self.dpc_padding_mode().bit()),
-            )
+            .field("dpc_tail_pixen_pulse_tl", &self.dpc_tail_pixen_pulse_tl())
+            .field("dpc_tail_pixen_pulse_th", &self.dpc_tail_pixen_pulse_th())
+            .field("dpc_padding_data", &self.dpc_padding_data())
+            .field("dpc_padding_mode", &self.dpc_padding_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPC_MATRIX_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th &lt; reg_dpc_tail_pixen_pulse_tl will enable tail pulse function"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/frame_cfg.rs b/esp32p4/src/isp/frame_cfg.rs
index 2b54fb63f5..f244ebd348 100644
--- a/esp32p4/src/isp/frame_cfg.rs
+++ b/esp32p4/src/isp/frame_cfg.rs
@@ -53,26 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FRAME_CFG")
-            .field("vadr_num", &format_args!("{}", self.vadr_num().bits()))
-            .field("hadr_num", &format_args!("{}", self.hadr_num().bits()))
-            .field("bayer_mode", &format_args!("{}", self.bayer_mode().bits()))
-            .field(
-                "hsync_start_exist",
-                &format_args!("{}", self.hsync_start_exist().bit()),
-            )
-            .field(
-                "hsync_end_exist",
-                &format_args!("{}", self.hsync_end_exist().bit()),
-            )
+            .field("vadr_num", &self.vadr_num())
+            .field("hadr_num", &self.hadr_num())
+            .field("bayer_mode", &self.bayer_mode())
+            .field("hsync_start_exist", &self.hsync_start_exist())
+            .field("hsync_end_exist", &self.hsync_end_exist())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FRAME_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - this field configures input image size in y-direction, image row number - 1"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_bx1.rs b/esp32p4/src/isp/gamma_bx1.rs
index a492c14403..f02aabf3b2 100644
--- a/esp32p4/src/isp/gamma_bx1.rs
+++ b/esp32p4/src/isp/gamma_bx1.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_BX1")
-            .field(
-                "gamma_b_x07",
-                &format_args!("{}", self.gamma_b_x07().bits()),
-            )
-            .field(
-                "gamma_b_x06",
-                &format_args!("{}", self.gamma_b_x06().bits()),
-            )
-            .field(
-                "gamma_b_x05",
-                &format_args!("{}", self.gamma_b_x05().bits()),
-            )
-            .field(
-                "gamma_b_x04",
-                &format_args!("{}", self.gamma_b_x04().bits()),
-            )
-            .field(
-                "gamma_b_x03",
-                &format_args!("{}", self.gamma_b_x03().bits()),
-            )
-            .field(
-                "gamma_b_x02",
-                &format_args!("{}", self.gamma_b_x02().bits()),
-            )
-            .field(
-                "gamma_b_x01",
-                &format_args!("{}", self.gamma_b_x01().bits()),
-            )
-            .field(
-                "gamma_b_x00",
-                &format_args!("{}", self.gamma_b_x00().bits()),
-            )
+            .field("gamma_b_x07", &self.gamma_b_x07())
+            .field("gamma_b_x06", &self.gamma_b_x06())
+            .field("gamma_b_x05", &self.gamma_b_x05())
+            .field("gamma_b_x04", &self.gamma_b_x04())
+            .field("gamma_b_x03", &self.gamma_b_x03())
+            .field("gamma_b_x02", &self.gamma_b_x02())
+            .field("gamma_b_x01", &self.gamma_b_x01())
+            .field("gamma_b_x00", &self.gamma_b_x00())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_BX1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - this field configures the point 7 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_bx2.rs b/esp32p4/src/isp/gamma_bx2.rs
index 0cced017f1..075473c075 100644
--- a/esp32p4/src/isp/gamma_bx2.rs
+++ b/esp32p4/src/isp/gamma_bx2.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_BX2")
-            .field(
-                "gamma_b_x0f",
-                &format_args!("{}", self.gamma_b_x0f().bits()),
-            )
-            .field(
-                "gamma_b_x0e",
-                &format_args!("{}", self.gamma_b_x0e().bits()),
-            )
-            .field(
-                "gamma_b_x0d",
-                &format_args!("{}", self.gamma_b_x0d().bits()),
-            )
-            .field(
-                "gamma_b_x0c",
-                &format_args!("{}", self.gamma_b_x0c().bits()),
-            )
-            .field(
-                "gamma_b_x0b",
-                &format_args!("{}", self.gamma_b_x0b().bits()),
-            )
-            .field(
-                "gamma_b_x0a",
-                &format_args!("{}", self.gamma_b_x0a().bits()),
-            )
-            .field(
-                "gamma_b_x09",
-                &format_args!("{}", self.gamma_b_x09().bits()),
-            )
-            .field(
-                "gamma_b_x08",
-                &format_args!("{}", self.gamma_b_x08().bits()),
-            )
+            .field("gamma_b_x0f", &self.gamma_b_x0f())
+            .field("gamma_b_x0e", &self.gamma_b_x0e())
+            .field("gamma_b_x0d", &self.gamma_b_x0d())
+            .field("gamma_b_x0c", &self.gamma_b_x0c())
+            .field("gamma_b_x0b", &self.gamma_b_x0b())
+            .field("gamma_b_x0a", &self.gamma_b_x0a())
+            .field("gamma_b_x09", &self.gamma_b_x09())
+            .field("gamma_b_x08", &self.gamma_b_x08())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_BX2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - this field configures the point 15 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_by1.rs b/esp32p4/src/isp/gamma_by1.rs
index fc697b9f09..4f2a509684 100644
--- a/esp32p4/src/isp/gamma_by1.rs
+++ b/esp32p4/src/isp/gamma_by1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_BY1")
-            .field(
-                "gamma_b_y03",
-                &format_args!("{}", self.gamma_b_y03().bits()),
-            )
-            .field(
-                "gamma_b_y02",
-                &format_args!("{}", self.gamma_b_y02().bits()),
-            )
-            .field(
-                "gamma_b_y01",
-                &format_args!("{}", self.gamma_b_y01().bits()),
-            )
-            .field(
-                "gamma_b_y00",
-                &format_args!("{}", self.gamma_b_y00().bits()),
-            )
+            .field("gamma_b_y03", &self.gamma_b_y03())
+            .field("gamma_b_y02", &self.gamma_b_y02())
+            .field("gamma_b_y01", &self.gamma_b_y01())
+            .field("gamma_b_y00", &self.gamma_b_y00())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_BY1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the point 3 of Y-axis of b channel gamma curve"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_by2.rs b/esp32p4/src/isp/gamma_by2.rs
index 677ec53e7b..73f4d8a1e0 100644
--- a/esp32p4/src/isp/gamma_by2.rs
+++ b/esp32p4/src/isp/gamma_by2.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_BY2")
-            .field(
-                "gamma_b_y07",
-                &format_args!("{}", self.gamma_b_y07().bits()),
-            )
-            .field(
-                "gamma_b_y06",
-                &format_args!("{}", self.gamma_b_y06().bits()),
-            )
-            .field(
-                "gamma_b_y05",
-                &format_args!("{}", self.gamma_b_y05().bits()),
-            )
-            .field(
-                "gamma_b_y04",
-                &format_args!("{}", self.gamma_b_y04().bits()),
-            )
+            .field("gamma_b_y07", &self.gamma_b_y07())
+            .field("gamma_b_y06", &self.gamma_b_y06())
+            .field("gamma_b_y05", &self.gamma_b_y05())
+            .field("gamma_b_y04", &self.gamma_b_y04())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_BY2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the point 7 of Y-axis of b channel gamma curve"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_by3.rs b/esp32p4/src/isp/gamma_by3.rs
index a9cb482b6b..8be9f0ce05 100644
--- a/esp32p4/src/isp/gamma_by3.rs
+++ b/esp32p4/src/isp/gamma_by3.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_BY3")
-            .field(
-                "gamma_b_y0b",
-                &format_args!("{}", self.gamma_b_y0b().bits()),
-            )
-            .field(
-                "gamma_b_y0a",
-                &format_args!("{}", self.gamma_b_y0a().bits()),
-            )
-            .field(
-                "gamma_b_y09",
-                &format_args!("{}", self.gamma_b_y09().bits()),
-            )
-            .field(
-                "gamma_b_y08",
-                &format_args!("{}", self.gamma_b_y08().bits()),
-            )
+            .field("gamma_b_y0b", &self.gamma_b_y0b())
+            .field("gamma_b_y0a", &self.gamma_b_y0a())
+            .field("gamma_b_y09", &self.gamma_b_y09())
+            .field("gamma_b_y08", &self.gamma_b_y08())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_BY3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the point 11 of Y-axis of b channel gamma curve"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_by4.rs b/esp32p4/src/isp/gamma_by4.rs
index e599a3c342..e9256d5311 100644
--- a/esp32p4/src/isp/gamma_by4.rs
+++ b/esp32p4/src/isp/gamma_by4.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_BY4")
-            .field(
-                "gamma_b_y0f",
-                &format_args!("{}", self.gamma_b_y0f().bits()),
-            )
-            .field(
-                "gamma_b_y0e",
-                &format_args!("{}", self.gamma_b_y0e().bits()),
-            )
-            .field(
-                "gamma_b_y0d",
-                &format_args!("{}", self.gamma_b_y0d().bits()),
-            )
-            .field(
-                "gamma_b_y0c",
-                &format_args!("{}", self.gamma_b_y0c().bits()),
-            )
+            .field("gamma_b_y0f", &self.gamma_b_y0f())
+            .field("gamma_b_y0e", &self.gamma_b_y0e())
+            .field("gamma_b_y0d", &self.gamma_b_y0d())
+            .field("gamma_b_y0c", &self.gamma_b_y0c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_BY4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the point 15 of Y-axis of b channel gamma curve"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_ctrl.rs b/esp32p4/src/isp/gamma_ctrl.rs
index 79ba787a33..6483db14ff 100644
--- a/esp32p4/src/isp/gamma_ctrl.rs
+++ b/esp32p4/src/isp/gamma_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_CTRL")
-            .field(
-                "gamma_update",
-                &format_args!("{}", self.gamma_update().bit()),
-            )
-            .field(
-                "gamma_b_last_correct",
-                &format_args!("{}", self.gamma_b_last_correct().bit()),
-            )
-            .field(
-                "gamma_g_last_correct",
-                &format_args!("{}", self.gamma_g_last_correct().bit()),
-            )
-            .field(
-                "gamma_r_last_correct",
-                &format_args!("{}", self.gamma_r_last_correct().bit()),
-            )
+            .field("gamma_update", &self.gamma_update())
+            .field("gamma_b_last_correct", &self.gamma_b_last_correct())
+            .field("gamma_g_last_correct", &self.gamma_g_last_correct())
+            .field("gamma_r_last_correct", &self.gamma_r_last_correct())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Indicates that gamma register configuration is complete"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_gx1.rs b/esp32p4/src/isp/gamma_gx1.rs
index 3204a82ccc..88e93c2bcd 100644
--- a/esp32p4/src/isp/gamma_gx1.rs
+++ b/esp32p4/src/isp/gamma_gx1.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_GX1")
-            .field(
-                "gamma_g_x07",
-                &format_args!("{}", self.gamma_g_x07().bits()),
-            )
-            .field(
-                "gamma_g_x06",
-                &format_args!("{}", self.gamma_g_x06().bits()),
-            )
-            .field(
-                "gamma_g_x05",
-                &format_args!("{}", self.gamma_g_x05().bits()),
-            )
-            .field(
-                "gamma_g_x04",
-                &format_args!("{}", self.gamma_g_x04().bits()),
-            )
-            .field(
-                "gamma_g_x03",
-                &format_args!("{}", self.gamma_g_x03().bits()),
-            )
-            .field(
-                "gamma_g_x02",
-                &format_args!("{}", self.gamma_g_x02().bits()),
-            )
-            .field(
-                "gamma_g_x01",
-                &format_args!("{}", self.gamma_g_x01().bits()),
-            )
-            .field(
-                "gamma_g_x00",
-                &format_args!("{}", self.gamma_g_x00().bits()),
-            )
+            .field("gamma_g_x07", &self.gamma_g_x07())
+            .field("gamma_g_x06", &self.gamma_g_x06())
+            .field("gamma_g_x05", &self.gamma_g_x05())
+            .field("gamma_g_x04", &self.gamma_g_x04())
+            .field("gamma_g_x03", &self.gamma_g_x03())
+            .field("gamma_g_x02", &self.gamma_g_x02())
+            .field("gamma_g_x01", &self.gamma_g_x01())
+            .field("gamma_g_x00", &self.gamma_g_x00())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_GX1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - this field configures the point 7 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_gx2.rs b/esp32p4/src/isp/gamma_gx2.rs
index fdada64dd9..59ce25e01c 100644
--- a/esp32p4/src/isp/gamma_gx2.rs
+++ b/esp32p4/src/isp/gamma_gx2.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_GX2")
-            .field(
-                "gamma_g_x0f",
-                &format_args!("{}", self.gamma_g_x0f().bits()),
-            )
-            .field(
-                "gamma_g_x0e",
-                &format_args!("{}", self.gamma_g_x0e().bits()),
-            )
-            .field(
-                "gamma_g_x0d",
-                &format_args!("{}", self.gamma_g_x0d().bits()),
-            )
-            .field(
-                "gamma_g_x0c",
-                &format_args!("{}", self.gamma_g_x0c().bits()),
-            )
-            .field(
-                "gamma_g_x0b",
-                &format_args!("{}", self.gamma_g_x0b().bits()),
-            )
-            .field(
-                "gamma_g_x0a",
-                &format_args!("{}", self.gamma_g_x0a().bits()),
-            )
-            .field(
-                "gamma_g_x09",
-                &format_args!("{}", self.gamma_g_x09().bits()),
-            )
-            .field(
-                "gamma_g_x08",
-                &format_args!("{}", self.gamma_g_x08().bits()),
-            )
+            .field("gamma_g_x0f", &self.gamma_g_x0f())
+            .field("gamma_g_x0e", &self.gamma_g_x0e())
+            .field("gamma_g_x0d", &self.gamma_g_x0d())
+            .field("gamma_g_x0c", &self.gamma_g_x0c())
+            .field("gamma_g_x0b", &self.gamma_g_x0b())
+            .field("gamma_g_x0a", &self.gamma_g_x0a())
+            .field("gamma_g_x09", &self.gamma_g_x09())
+            .field("gamma_g_x08", &self.gamma_g_x08())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_GX2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - this field configures the point 15 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_gy1.rs b/esp32p4/src/isp/gamma_gy1.rs
index e84d7a373b..8397d9ec79 100644
--- a/esp32p4/src/isp/gamma_gy1.rs
+++ b/esp32p4/src/isp/gamma_gy1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_GY1")
-            .field(
-                "gamma_g_y03",
-                &format_args!("{}", self.gamma_g_y03().bits()),
-            )
-            .field(
-                "gamma_g_y02",
-                &format_args!("{}", self.gamma_g_y02().bits()),
-            )
-            .field(
-                "gamma_g_y01",
-                &format_args!("{}", self.gamma_g_y01().bits()),
-            )
-            .field(
-                "gamma_g_y00",
-                &format_args!("{}", self.gamma_g_y00().bits()),
-            )
+            .field("gamma_g_y03", &self.gamma_g_y03())
+            .field("gamma_g_y02", &self.gamma_g_y02())
+            .field("gamma_g_y01", &self.gamma_g_y01())
+            .field("gamma_g_y00", &self.gamma_g_y00())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_GY1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the point 3 of Y-axis of g channel gamma curve"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_gy2.rs b/esp32p4/src/isp/gamma_gy2.rs
index 0315df27fa..85c2a48030 100644
--- a/esp32p4/src/isp/gamma_gy2.rs
+++ b/esp32p4/src/isp/gamma_gy2.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_GY2")
-            .field(
-                "gamma_g_y07",
-                &format_args!("{}", self.gamma_g_y07().bits()),
-            )
-            .field(
-                "gamma_g_y06",
-                &format_args!("{}", self.gamma_g_y06().bits()),
-            )
-            .field(
-                "gamma_g_y05",
-                &format_args!("{}", self.gamma_g_y05().bits()),
-            )
-            .field(
-                "gamma_g_y04",
-                &format_args!("{}", self.gamma_g_y04().bits()),
-            )
+            .field("gamma_g_y07", &self.gamma_g_y07())
+            .field("gamma_g_y06", &self.gamma_g_y06())
+            .field("gamma_g_y05", &self.gamma_g_y05())
+            .field("gamma_g_y04", &self.gamma_g_y04())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_GY2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the point 7 of Y-axis of g channel gamma curve"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_gy3.rs b/esp32p4/src/isp/gamma_gy3.rs
index 54f2b2acfc..249dc54c2b 100644
--- a/esp32p4/src/isp/gamma_gy3.rs
+++ b/esp32p4/src/isp/gamma_gy3.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_GY3")
-            .field(
-                "gamma_g_y0b",
-                &format_args!("{}", self.gamma_g_y0b().bits()),
-            )
-            .field(
-                "gamma_g_y0a",
-                &format_args!("{}", self.gamma_g_y0a().bits()),
-            )
-            .field(
-                "gamma_g_y09",
-                &format_args!("{}", self.gamma_g_y09().bits()),
-            )
-            .field(
-                "gamma_g_y08",
-                &format_args!("{}", self.gamma_g_y08().bits()),
-            )
+            .field("gamma_g_y0b", &self.gamma_g_y0b())
+            .field("gamma_g_y0a", &self.gamma_g_y0a())
+            .field("gamma_g_y09", &self.gamma_g_y09())
+            .field("gamma_g_y08", &self.gamma_g_y08())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_GY3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the point 11 of Y-axis of g channel gamma curve"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_gy4.rs b/esp32p4/src/isp/gamma_gy4.rs
index 7638cd2f51..91361b5d3d 100644
--- a/esp32p4/src/isp/gamma_gy4.rs
+++ b/esp32p4/src/isp/gamma_gy4.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_GY4")
-            .field(
-                "gamma_g_y0f",
-                &format_args!("{}", self.gamma_g_y0f().bits()),
-            )
-            .field(
-                "gamma_g_y0e",
-                &format_args!("{}", self.gamma_g_y0e().bits()),
-            )
-            .field(
-                "gamma_g_y0d",
-                &format_args!("{}", self.gamma_g_y0d().bits()),
-            )
-            .field(
-                "gamma_g_y0c",
-                &format_args!("{}", self.gamma_g_y0c().bits()),
-            )
+            .field("gamma_g_y0f", &self.gamma_g_y0f())
+            .field("gamma_g_y0e", &self.gamma_g_y0e())
+            .field("gamma_g_y0d", &self.gamma_g_y0d())
+            .field("gamma_g_y0c", &self.gamma_g_y0c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_GY4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the point 15 of Y-axis of g channel gamma curve"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_rx1.rs b/esp32p4/src/isp/gamma_rx1.rs
index 77fda27bdc..0709b33824 100644
--- a/esp32p4/src/isp/gamma_rx1.rs
+++ b/esp32p4/src/isp/gamma_rx1.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_RX1")
-            .field(
-                "gamma_r_x07",
-                &format_args!("{}", self.gamma_r_x07().bits()),
-            )
-            .field(
-                "gamma_r_x06",
-                &format_args!("{}", self.gamma_r_x06().bits()),
-            )
-            .field(
-                "gamma_r_x05",
-                &format_args!("{}", self.gamma_r_x05().bits()),
-            )
-            .field(
-                "gamma_r_x04",
-                &format_args!("{}", self.gamma_r_x04().bits()),
-            )
-            .field(
-                "gamma_r_x03",
-                &format_args!("{}", self.gamma_r_x03().bits()),
-            )
-            .field(
-                "gamma_r_x02",
-                &format_args!("{}", self.gamma_r_x02().bits()),
-            )
-            .field(
-                "gamma_r_x01",
-                &format_args!("{}", self.gamma_r_x01().bits()),
-            )
-            .field(
-                "gamma_r_x00",
-                &format_args!("{}", self.gamma_r_x00().bits()),
-            )
+            .field("gamma_r_x07", &self.gamma_r_x07())
+            .field("gamma_r_x06", &self.gamma_r_x06())
+            .field("gamma_r_x05", &self.gamma_r_x05())
+            .field("gamma_r_x04", &self.gamma_r_x04())
+            .field("gamma_r_x03", &self.gamma_r_x03())
+            .field("gamma_r_x02", &self.gamma_r_x02())
+            .field("gamma_r_x01", &self.gamma_r_x01())
+            .field("gamma_r_x00", &self.gamma_r_x00())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_RX1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - this field configures the point 7 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_rx2.rs b/esp32p4/src/isp/gamma_rx2.rs
index 46e3e4bf91..e08497f891 100644
--- a/esp32p4/src/isp/gamma_rx2.rs
+++ b/esp32p4/src/isp/gamma_rx2.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_RX2")
-            .field(
-                "gamma_r_x0f",
-                &format_args!("{}", self.gamma_r_x0f().bits()),
-            )
-            .field(
-                "gamma_r_x0e",
-                &format_args!("{}", self.gamma_r_x0e().bits()),
-            )
-            .field(
-                "gamma_r_x0d",
-                &format_args!("{}", self.gamma_r_x0d().bits()),
-            )
-            .field(
-                "gamma_r_x0c",
-                &format_args!("{}", self.gamma_r_x0c().bits()),
-            )
-            .field(
-                "gamma_r_x0b",
-                &format_args!("{}", self.gamma_r_x0b().bits()),
-            )
-            .field(
-                "gamma_r_x0a",
-                &format_args!("{}", self.gamma_r_x0a().bits()),
-            )
-            .field(
-                "gamma_r_x09",
-                &format_args!("{}", self.gamma_r_x09().bits()),
-            )
-            .field(
-                "gamma_r_x08",
-                &format_args!("{}", self.gamma_r_x08().bits()),
-            )
+            .field("gamma_r_x0f", &self.gamma_r_x0f())
+            .field("gamma_r_x0e", &self.gamma_r_x0e())
+            .field("gamma_r_x0d", &self.gamma_r_x0d())
+            .field("gamma_r_x0c", &self.gamma_r_x0c())
+            .field("gamma_r_x0b", &self.gamma_r_x0b())
+            .field("gamma_r_x0a", &self.gamma_r_x0a())
+            .field("gamma_r_x09", &self.gamma_r_x09())
+            .field("gamma_r_x08", &self.gamma_r_x08())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_RX2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - this field configures the point 15 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_ry1.rs b/esp32p4/src/isp/gamma_ry1.rs
index dd06b09955..1b3da2e04a 100644
--- a/esp32p4/src/isp/gamma_ry1.rs
+++ b/esp32p4/src/isp/gamma_ry1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_RY1")
-            .field(
-                "gamma_r_y03",
-                &format_args!("{}", self.gamma_r_y03().bits()),
-            )
-            .field(
-                "gamma_r_y02",
-                &format_args!("{}", self.gamma_r_y02().bits()),
-            )
-            .field(
-                "gamma_r_y01",
-                &format_args!("{}", self.gamma_r_y01().bits()),
-            )
-            .field(
-                "gamma_r_y00",
-                &format_args!("{}", self.gamma_r_y00().bits()),
-            )
+            .field("gamma_r_y03", &self.gamma_r_y03())
+            .field("gamma_r_y02", &self.gamma_r_y02())
+            .field("gamma_r_y01", &self.gamma_r_y01())
+            .field("gamma_r_y00", &self.gamma_r_y00())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_RY1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the point 3 of Y-axis of r channel gamma curve"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_ry2.rs b/esp32p4/src/isp/gamma_ry2.rs
index de25a046d5..7c9ce6ae6c 100644
--- a/esp32p4/src/isp/gamma_ry2.rs
+++ b/esp32p4/src/isp/gamma_ry2.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_RY2")
-            .field(
-                "gamma_r_y07",
-                &format_args!("{}", self.gamma_r_y07().bits()),
-            )
-            .field(
-                "gamma_r_y06",
-                &format_args!("{}", self.gamma_r_y06().bits()),
-            )
-            .field(
-                "gamma_r_y05",
-                &format_args!("{}", self.gamma_r_y05().bits()),
-            )
-            .field(
-                "gamma_r_y04",
-                &format_args!("{}", self.gamma_r_y04().bits()),
-            )
+            .field("gamma_r_y07", &self.gamma_r_y07())
+            .field("gamma_r_y06", &self.gamma_r_y06())
+            .field("gamma_r_y05", &self.gamma_r_y05())
+            .field("gamma_r_y04", &self.gamma_r_y04())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_RY2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the point 7 of Y-axis of r channel gamma curve"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_ry3.rs b/esp32p4/src/isp/gamma_ry3.rs
index c09315ba11..f3346043ee 100644
--- a/esp32p4/src/isp/gamma_ry3.rs
+++ b/esp32p4/src/isp/gamma_ry3.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_RY3")
-            .field(
-                "gamma_r_y0b",
-                &format_args!("{}", self.gamma_r_y0b().bits()),
-            )
-            .field(
-                "gamma_r_y0a",
-                &format_args!("{}", self.gamma_r_y0a().bits()),
-            )
-            .field(
-                "gamma_r_y09",
-                &format_args!("{}", self.gamma_r_y09().bits()),
-            )
-            .field(
-                "gamma_r_y08",
-                &format_args!("{}", self.gamma_r_y08().bits()),
-            )
+            .field("gamma_r_y0b", &self.gamma_r_y0b())
+            .field("gamma_r_y0a", &self.gamma_r_y0a())
+            .field("gamma_r_y09", &self.gamma_r_y09())
+            .field("gamma_r_y08", &self.gamma_r_y08())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_RY3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the point 11 of Y-axis of r channel gamma curve"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/gamma_ry4.rs b/esp32p4/src/isp/gamma_ry4.rs
index aa2e2a2078..0ae56f6288 100644
--- a/esp32p4/src/isp/gamma_ry4.rs
+++ b/esp32p4/src/isp/gamma_ry4.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAMMA_RY4")
-            .field(
-                "gamma_r_y0f",
-                &format_args!("{}", self.gamma_r_y0f().bits()),
-            )
-            .field(
-                "gamma_r_y0e",
-                &format_args!("{}", self.gamma_r_y0e().bits()),
-            )
-            .field(
-                "gamma_r_y0d",
-                &format_args!("{}", self.gamma_r_y0d().bits()),
-            )
-            .field(
-                "gamma_r_y0c",
-                &format_args!("{}", self.gamma_r_y0c().bits()),
-            )
+            .field("gamma_r_y0f", &self.gamma_r_y0f())
+            .field("gamma_r_y0e", &self.gamma_r_y0e())
+            .field("gamma_r_y0d", &self.gamma_r_y0d())
+            .field("gamma_r_y0c", &self.gamma_r_y0c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAMMA_RY4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the point 15 of Y-axis of r channel gamma curve"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hist_bin0.rs b/esp32p4/src/isp/hist_bin0.rs
index 6ca0843253..3273f777a3 100644
--- a/esp32p4/src/isp/hist_bin0.rs
+++ b/esp32p4/src/isp/hist_bin0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN0")
-            .field("hist_bin_0", &format_args!("{}", self.hist_bin_0().bits()))
+            .field("hist_bin_0", &self.hist_bin_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN0_SPEC;
 impl crate::RegisterSpec for HIST_BIN0_SPEC {
diff --git a/esp32p4/src/isp/hist_bin1.rs b/esp32p4/src/isp/hist_bin1.rs
index a166559208..4dd9df0c8d 100644
--- a/esp32p4/src/isp/hist_bin1.rs
+++ b/esp32p4/src/isp/hist_bin1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN1")
-            .field("hist_bin_1", &format_args!("{}", self.hist_bin_1().bits()))
+            .field("hist_bin_1", &self.hist_bin_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN1_SPEC;
 impl crate::RegisterSpec for HIST_BIN1_SPEC {
diff --git a/esp32p4/src/isp/hist_bin10.rs b/esp32p4/src/isp/hist_bin10.rs
index 9954bc63b0..7ddde5279e 100644
--- a/esp32p4/src/isp/hist_bin10.rs
+++ b/esp32p4/src/isp/hist_bin10.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN10")
-            .field(
-                "hist_bin_10",
-                &format_args!("{}", self.hist_bin_10().bits()),
-            )
+            .field("hist_bin_10", &self.hist_bin_10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN10_SPEC;
 impl crate::RegisterSpec for HIST_BIN10_SPEC {
diff --git a/esp32p4/src/isp/hist_bin11.rs b/esp32p4/src/isp/hist_bin11.rs
index 0cca5b22a2..ae9d9618da 100644
--- a/esp32p4/src/isp/hist_bin11.rs
+++ b/esp32p4/src/isp/hist_bin11.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN11")
-            .field(
-                "hist_bin_11",
-                &format_args!("{}", self.hist_bin_11().bits()),
-            )
+            .field("hist_bin_11", &self.hist_bin_11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN11_SPEC;
 impl crate::RegisterSpec for HIST_BIN11_SPEC {
diff --git a/esp32p4/src/isp/hist_bin12.rs b/esp32p4/src/isp/hist_bin12.rs
index 12208cdd02..dfbe66cf9e 100644
--- a/esp32p4/src/isp/hist_bin12.rs
+++ b/esp32p4/src/isp/hist_bin12.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN12")
-            .field(
-                "hist_bin_12",
-                &format_args!("{}", self.hist_bin_12().bits()),
-            )
+            .field("hist_bin_12", &self.hist_bin_12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin12::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN12_SPEC;
 impl crate::RegisterSpec for HIST_BIN12_SPEC {
diff --git a/esp32p4/src/isp/hist_bin13.rs b/esp32p4/src/isp/hist_bin13.rs
index 6fceae4bb2..1e8f1769e5 100644
--- a/esp32p4/src/isp/hist_bin13.rs
+++ b/esp32p4/src/isp/hist_bin13.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN13")
-            .field(
-                "hist_bin_13",
-                &format_args!("{}", self.hist_bin_13().bits()),
-            )
+            .field("hist_bin_13", &self.hist_bin_13())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin13::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN13_SPEC;
 impl crate::RegisterSpec for HIST_BIN13_SPEC {
diff --git a/esp32p4/src/isp/hist_bin14.rs b/esp32p4/src/isp/hist_bin14.rs
index 95830a87ae..f893702931 100644
--- a/esp32p4/src/isp/hist_bin14.rs
+++ b/esp32p4/src/isp/hist_bin14.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN14")
-            .field(
-                "hist_bin_14",
-                &format_args!("{}", self.hist_bin_14().bits()),
-            )
+            .field("hist_bin_14", &self.hist_bin_14())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin14::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN14_SPEC;
 impl crate::RegisterSpec for HIST_BIN14_SPEC {
diff --git a/esp32p4/src/isp/hist_bin15.rs b/esp32p4/src/isp/hist_bin15.rs
index fa00a9f5e1..f2b84bd69c 100644
--- a/esp32p4/src/isp/hist_bin15.rs
+++ b/esp32p4/src/isp/hist_bin15.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN15")
-            .field(
-                "hist_bin_15",
-                &format_args!("{}", self.hist_bin_15().bits()),
-            )
+            .field("hist_bin_15", &self.hist_bin_15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 15\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin15::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN15_SPEC;
 impl crate::RegisterSpec for HIST_BIN15_SPEC {
diff --git a/esp32p4/src/isp/hist_bin2.rs b/esp32p4/src/isp/hist_bin2.rs
index a4b1bc5a80..5404ea1738 100644
--- a/esp32p4/src/isp/hist_bin2.rs
+++ b/esp32p4/src/isp/hist_bin2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN2")
-            .field("hist_bin_2", &format_args!("{}", self.hist_bin_2().bits()))
+            .field("hist_bin_2", &self.hist_bin_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN2_SPEC;
 impl crate::RegisterSpec for HIST_BIN2_SPEC {
diff --git a/esp32p4/src/isp/hist_bin3.rs b/esp32p4/src/isp/hist_bin3.rs
index 3d1ca441b6..168e5e7477 100644
--- a/esp32p4/src/isp/hist_bin3.rs
+++ b/esp32p4/src/isp/hist_bin3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN3")
-            .field("hist_bin_3", &format_args!("{}", self.hist_bin_3().bits()))
+            .field("hist_bin_3", &self.hist_bin_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN3_SPEC;
 impl crate::RegisterSpec for HIST_BIN3_SPEC {
diff --git a/esp32p4/src/isp/hist_bin4.rs b/esp32p4/src/isp/hist_bin4.rs
index 7328a84d97..481541009d 100644
--- a/esp32p4/src/isp/hist_bin4.rs
+++ b/esp32p4/src/isp/hist_bin4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN4")
-            .field("hist_bin_4", &format_args!("{}", self.hist_bin_4().bits()))
+            .field("hist_bin_4", &self.hist_bin_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN4_SPEC;
 impl crate::RegisterSpec for HIST_BIN4_SPEC {
diff --git a/esp32p4/src/isp/hist_bin5.rs b/esp32p4/src/isp/hist_bin5.rs
index 40de012bab..a1eed4956d 100644
--- a/esp32p4/src/isp/hist_bin5.rs
+++ b/esp32p4/src/isp/hist_bin5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN5")
-            .field("hist_bin_5", &format_args!("{}", self.hist_bin_5().bits()))
+            .field("hist_bin_5", &self.hist_bin_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN5_SPEC;
 impl crate::RegisterSpec for HIST_BIN5_SPEC {
diff --git a/esp32p4/src/isp/hist_bin6.rs b/esp32p4/src/isp/hist_bin6.rs
index 62ad413f40..4dba40d2d0 100644
--- a/esp32p4/src/isp/hist_bin6.rs
+++ b/esp32p4/src/isp/hist_bin6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN6")
-            .field("hist_bin_6", &format_args!("{}", self.hist_bin_6().bits()))
+            .field("hist_bin_6", &self.hist_bin_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN6_SPEC;
 impl crate::RegisterSpec for HIST_BIN6_SPEC {
diff --git a/esp32p4/src/isp/hist_bin7.rs b/esp32p4/src/isp/hist_bin7.rs
index c1ccda0734..d24114f789 100644
--- a/esp32p4/src/isp/hist_bin7.rs
+++ b/esp32p4/src/isp/hist_bin7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN7")
-            .field("hist_bin_7", &format_args!("{}", self.hist_bin_7().bits()))
+            .field("hist_bin_7", &self.hist_bin_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN7_SPEC;
 impl crate::RegisterSpec for HIST_BIN7_SPEC {
diff --git a/esp32p4/src/isp/hist_bin8.rs b/esp32p4/src/isp/hist_bin8.rs
index ded9067651..0aeed873d0 100644
--- a/esp32p4/src/isp/hist_bin8.rs
+++ b/esp32p4/src/isp/hist_bin8.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN8")
-            .field("hist_bin_8", &format_args!("{}", self.hist_bin_8().bits()))
+            .field("hist_bin_8", &self.hist_bin_8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN8_SPEC;
 impl crate::RegisterSpec for HIST_BIN8_SPEC {
diff --git a/esp32p4/src/isp/hist_bin9.rs b/esp32p4/src/isp/hist_bin9.rs
index 2fc2057fa1..30aff47f94 100644
--- a/esp32p4/src/isp/hist_bin9.rs
+++ b/esp32p4/src/isp/hist_bin9.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_BIN9")
-            .field("hist_bin_9", &format_args!("{}", self.hist_bin_9().bits()))
+            .field("hist_bin_9", &self.hist_bin_9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_BIN9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "result of histogram bin 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hist_bin9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIST_BIN9_SPEC;
 impl crate::RegisterSpec for HIST_BIN9_SPEC {
diff --git a/esp32p4/src/isp/hist_coeff.rs b/esp32p4/src/isp/hist_coeff.rs
index ab949d5336..559542d006 100644
--- a/esp32p4/src/isp/hist_coeff.rs
+++ b/esp32p4/src/isp/hist_coeff.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_COEFF")
-            .field("b", &format_args!("{}", self.b().bits()))
-            .field("g", &format_args!("{}", self.g().bits()))
-            .field("r", &format_args!("{}", self.r().bits()))
+            .field("b", &self.b())
+            .field("g", &self.g())
+            .field("r", &self.r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_COEFF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hist_mode.rs b/esp32p4/src/isp/hist_mode.rs
index e006690428..9493f24408 100644
--- a/esp32p4/src/isp/hist_mode.rs
+++ b/esp32p4/src/isp/hist_mode.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_MODE")
-            .field("hist_mode", &format_args!("{}", self.hist_mode().bits()))
+            .field("hist_mode", &self.hist_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4: RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hist_offs.rs b/esp32p4/src/isp/hist_offs.rs
index 6dd75aff36..283d4312c9 100644
--- a/esp32p4/src/isp/hist_offs.rs
+++ b/esp32p4/src/isp/hist_offs.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_OFFS")
-            .field(
-                "hist_y_offs",
-                &format_args!("{}", self.hist_y_offs().bits()),
-            )
-            .field(
-                "hist_x_offs",
-                &format_args!("{}", self.hist_x_offs().bits()),
-            )
+            .field("hist_y_offs", &self.hist_y_offs())
+            .field("hist_x_offs", &self.hist_x_offs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_OFFS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - this field configures y coordinate of first window"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hist_seg0.rs b/esp32p4/src/isp/hist_seg0.rs
index f0ecf1d1a3..3f9d6c5144 100644
--- a/esp32p4/src/isp/hist_seg0.rs
+++ b/esp32p4/src/isp/hist_seg0.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_SEG0")
-            .field(
-                "hist_seg_3_4",
-                &format_args!("{}", self.hist_seg_3_4().bits()),
-            )
-            .field(
-                "hist_seg_2_3",
-                &format_args!("{}", self.hist_seg_2_3().bits()),
-            )
-            .field(
-                "hist_seg_1_2",
-                &format_args!("{}", self.hist_seg_1_2().bits()),
-            )
-            .field(
-                "hist_seg_0_1",
-                &format_args!("{}", self.hist_seg_0_1().bits()),
-            )
+            .field("hist_seg_3_4", &self.hist_seg_3_4())
+            .field("hist_seg_2_3", &self.hist_seg_2_3())
+            .field("hist_seg_1_2", &self.hist_seg_1_2())
+            .field("hist_seg_0_1", &self.hist_seg_0_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_SEG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures threshold of histogram bin 3 and bin 4"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hist_seg1.rs b/esp32p4/src/isp/hist_seg1.rs
index d0fd34ba93..300274fa09 100644
--- a/esp32p4/src/isp/hist_seg1.rs
+++ b/esp32p4/src/isp/hist_seg1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_SEG1")
-            .field(
-                "hist_seg_7_8",
-                &format_args!("{}", self.hist_seg_7_8().bits()),
-            )
-            .field(
-                "hist_seg_6_7",
-                &format_args!("{}", self.hist_seg_6_7().bits()),
-            )
-            .field(
-                "hist_seg_5_6",
-                &format_args!("{}", self.hist_seg_5_6().bits()),
-            )
-            .field(
-                "hist_seg_4_5",
-                &format_args!("{}", self.hist_seg_4_5().bits()),
-            )
+            .field("hist_seg_7_8", &self.hist_seg_7_8())
+            .field("hist_seg_6_7", &self.hist_seg_6_7())
+            .field("hist_seg_5_6", &self.hist_seg_5_6())
+            .field("hist_seg_4_5", &self.hist_seg_4_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_SEG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures threshold of histogram bin 7 and bin 8"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hist_seg2.rs b/esp32p4/src/isp/hist_seg2.rs
index df4af250a6..8096b53439 100644
--- a/esp32p4/src/isp/hist_seg2.rs
+++ b/esp32p4/src/isp/hist_seg2.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_SEG2")
-            .field(
-                "hist_seg_11_12",
-                &format_args!("{}", self.hist_seg_11_12().bits()),
-            )
-            .field(
-                "hist_seg_10_11",
-                &format_args!("{}", self.hist_seg_10_11().bits()),
-            )
-            .field(
-                "hist_seg_9_10",
-                &format_args!("{}", self.hist_seg_9_10().bits()),
-            )
-            .field(
-                "hist_seg_8_9",
-                &format_args!("{}", self.hist_seg_8_9().bits()),
-            )
+            .field("hist_seg_11_12", &self.hist_seg_11_12())
+            .field("hist_seg_10_11", &self.hist_seg_10_11())
+            .field("hist_seg_9_10", &self.hist_seg_9_10())
+            .field("hist_seg_8_9", &self.hist_seg_8_9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_SEG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures threshold of histogram bin 11 and bin 12"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hist_seg3.rs b/esp32p4/src/isp/hist_seg3.rs
index 58bb94949a..b2d61c69de 100644
--- a/esp32p4/src/isp/hist_seg3.rs
+++ b/esp32p4/src/isp/hist_seg3.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_SEG3")
-            .field(
-                "hist_seg_14_15",
-                &format_args!("{}", self.hist_seg_14_15().bits()),
-            )
-            .field(
-                "hist_seg_13_14",
-                &format_args!("{}", self.hist_seg_13_14().bits()),
-            )
-            .field(
-                "hist_seg_12_13",
-                &format_args!("{}", self.hist_seg_12_13().bits()),
-            )
+            .field("hist_seg_14_15", &self.hist_seg_14_15())
+            .field("hist_seg_13_14", &self.hist_seg_13_14())
+            .field("hist_seg_12_13", &self.hist_seg_12_13())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_SEG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures threshold of histogram bin 14 and bin 15"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hist_size.rs b/esp32p4/src/isp/hist_size.rs
index 3d498e5ae0..04374edfd8 100644
--- a/esp32p4/src/isp/hist_size.rs
+++ b/esp32p4/src/isp/hist_size.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_SIZE")
-            .field(
-                "hist_y_size",
-                &format_args!("{}", self.hist_y_size().bits()),
-            )
-            .field(
-                "hist_x_size",
-                &format_args!("{}", self.hist_x_size().bits()),
-            )
+            .field("hist_y_size", &self.hist_y_size())
+            .field("hist_x_size", &self.hist_x_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - this field configures y direction size of subwindow"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hist_weight0.rs b/esp32p4/src/isp/hist_weight0.rs
index 3348baae98..85c667bfd3 100644
--- a/esp32p4/src/isp/hist_weight0.rs
+++ b/esp32p4/src/isp/hist_weight0.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_WEIGHT0")
-            .field(
-                "hist_weight_03",
-                &format_args!("{}", self.hist_weight_03().bits()),
-            )
-            .field(
-                "hist_weight_02",
-                &format_args!("{}", self.hist_weight_02().bits()),
-            )
-            .field(
-                "hist_weight_01",
-                &format_args!("{}", self.hist_weight_01().bits()),
-            )
-            .field(
-                "hist_weight_00",
-                &format_args!("{}", self.hist_weight_00().bits()),
-            )
+            .field("hist_weight_03", &self.hist_weight_03())
+            .field("hist_weight_02", &self.hist_weight_02())
+            .field("hist_weight_01", &self.hist_weight_01())
+            .field("hist_weight_00", &self.hist_weight_00())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_WEIGHT0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures weight of subwindow 03"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hist_weight1.rs b/esp32p4/src/isp/hist_weight1.rs
index 16209d0c0a..90b383020d 100644
--- a/esp32p4/src/isp/hist_weight1.rs
+++ b/esp32p4/src/isp/hist_weight1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_WEIGHT1")
-            .field(
-                "hist_weight_12",
-                &format_args!("{}", self.hist_weight_12().bits()),
-            )
-            .field(
-                "hist_weight_11",
-                &format_args!("{}", self.hist_weight_11().bits()),
-            )
-            .field(
-                "hist_weight_10",
-                &format_args!("{}", self.hist_weight_10().bits()),
-            )
-            .field(
-                "hist_weight_04",
-                &format_args!("{}", self.hist_weight_04().bits()),
-            )
+            .field("hist_weight_12", &self.hist_weight_12())
+            .field("hist_weight_11", &self.hist_weight_11())
+            .field("hist_weight_10", &self.hist_weight_10())
+            .field("hist_weight_04", &self.hist_weight_04())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_WEIGHT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures weight of subwindow 12"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hist_weight2.rs b/esp32p4/src/isp/hist_weight2.rs
index 4239cd27a3..0c9815988b 100644
--- a/esp32p4/src/isp/hist_weight2.rs
+++ b/esp32p4/src/isp/hist_weight2.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_WEIGHT2")
-            .field(
-                "hist_weight_21",
-                &format_args!("{}", self.hist_weight_21().bits()),
-            )
-            .field(
-                "hist_weight_20",
-                &format_args!("{}", self.hist_weight_20().bits()),
-            )
-            .field(
-                "hist_weight_14",
-                &format_args!("{}", self.hist_weight_14().bits()),
-            )
-            .field(
-                "hist_weight_13",
-                &format_args!("{}", self.hist_weight_13().bits()),
-            )
+            .field("hist_weight_21", &self.hist_weight_21())
+            .field("hist_weight_20", &self.hist_weight_20())
+            .field("hist_weight_14", &self.hist_weight_14())
+            .field("hist_weight_13", &self.hist_weight_13())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_WEIGHT2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures weight of subwindow 21"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hist_weight3.rs b/esp32p4/src/isp/hist_weight3.rs
index 0eba594590..53bff21f73 100644
--- a/esp32p4/src/isp/hist_weight3.rs
+++ b/esp32p4/src/isp/hist_weight3.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_WEIGHT3")
-            .field(
-                "hist_weight_30",
-                &format_args!("{}", self.hist_weight_30().bits()),
-            )
-            .field(
-                "hist_weight_24",
-                &format_args!("{}", self.hist_weight_24().bits()),
-            )
-            .field(
-                "hist_weight_23",
-                &format_args!("{}", self.hist_weight_23().bits()),
-            )
-            .field(
-                "hist_weight_22",
-                &format_args!("{}", self.hist_weight_22().bits()),
-            )
+            .field("hist_weight_30", &self.hist_weight_30())
+            .field("hist_weight_24", &self.hist_weight_24())
+            .field("hist_weight_23", &self.hist_weight_23())
+            .field("hist_weight_22", &self.hist_weight_22())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_WEIGHT3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures weight of subwindow 30"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hist_weight4.rs b/esp32p4/src/isp/hist_weight4.rs
index ce54aa968e..e17c80c7a6 100644
--- a/esp32p4/src/isp/hist_weight4.rs
+++ b/esp32p4/src/isp/hist_weight4.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_WEIGHT4")
-            .field(
-                "hist_weight_34",
-                &format_args!("{}", self.hist_weight_34().bits()),
-            )
-            .field(
-                "hist_weight_33",
-                &format_args!("{}", self.hist_weight_33().bits()),
-            )
-            .field(
-                "hist_weight_32",
-                &format_args!("{}", self.hist_weight_32().bits()),
-            )
-            .field(
-                "hist_weight_31",
-                &format_args!("{}", self.hist_weight_31().bits()),
-            )
+            .field("hist_weight_34", &self.hist_weight_34())
+            .field("hist_weight_33", &self.hist_weight_33())
+            .field("hist_weight_32", &self.hist_weight_32())
+            .field("hist_weight_31", &self.hist_weight_31())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_WEIGHT4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures weight of subwindow 34"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hist_weight5.rs b/esp32p4/src/isp/hist_weight5.rs
index 0fa5fe6d84..a446ada24e 100644
--- a/esp32p4/src/isp/hist_weight5.rs
+++ b/esp32p4/src/isp/hist_weight5.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_WEIGHT5")
-            .field(
-                "hist_weight_43",
-                &format_args!("{}", self.hist_weight_43().bits()),
-            )
-            .field(
-                "hist_weight_42",
-                &format_args!("{}", self.hist_weight_42().bits()),
-            )
-            .field(
-                "hist_weight_41",
-                &format_args!("{}", self.hist_weight_41().bits()),
-            )
-            .field(
-                "hist_weight_40",
-                &format_args!("{}", self.hist_weight_40().bits()),
-            )
+            .field("hist_weight_43", &self.hist_weight_43())
+            .field("hist_weight_42", &self.hist_weight_42())
+            .field("hist_weight_41", &self.hist_weight_41())
+            .field("hist_weight_40", &self.hist_weight_40())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_WEIGHT5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures weight of subwindow 43"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hist_weight6.rs b/esp32p4/src/isp/hist_weight6.rs
index fb154d3b02..acc74bfe59 100644
--- a/esp32p4/src/isp/hist_weight6.rs
+++ b/esp32p4/src/isp/hist_weight6.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIST_WEIGHT6")
-            .field(
-                "hist_weight_44",
-                &format_args!("{}", self.hist_weight_44().bits()),
-            )
+            .field("hist_weight_44", &self.hist_weight_44())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIST_WEIGHT6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures weight of subwindow 44"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/hsync_cnt.rs b/esp32p4/src/isp/hsync_cnt.rs
index c007999f09..6a32b93d9f 100644
--- a/esp32p4/src/isp/hsync_cnt.rs
+++ b/esp32p4/src/isp/hsync_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HSYNC_CNT")
-            .field("hsync_cnt", &format_args!("{}", self.hsync_cnt().bits()))
+            .field("hsync_cnt", &self.hsync_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HSYNC_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures the number of clock before hsync and after vsync and line_end when decodes pix data from idi to isp"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/int_ena.rs b/esp32p4/src/isp/int_ena.rs
index 4720288426..1b693d16b8 100644
--- a/esp32p4/src/isp/int_ena.rs
+++ b/esp32p4/src/isp/int_ena.rs
@@ -269,89 +269,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "isp_data_type_err",
-                &format_args!("{}", self.isp_data_type_err().bit()),
-            )
-            .field(
-                "isp_async_fifo_ovf",
-                &format_args!("{}", self.isp_async_fifo_ovf().bit()),
-            )
-            .field(
-                "isp_buf_full",
-                &format_args!("{}", self.isp_buf_full().bit()),
-            )
-            .field(
-                "isp_hvnum_setting_err",
-                &format_args!("{}", self.isp_hvnum_setting_err().bit()),
-            )
+            .field("isp_data_type_err", &self.isp_data_type_err())
+            .field("isp_async_fifo_ovf", &self.isp_async_fifo_ovf())
+            .field("isp_buf_full", &self.isp_buf_full())
+            .field("isp_hvnum_setting_err", &self.isp_hvnum_setting_err())
             .field(
                 "isp_data_type_setting_err",
-                &format_args!("{}", self.isp_data_type_setting_err().bit()),
-            )
-            .field(
-                "isp_mipi_hnum_unmatch",
-                &format_args!("{}", self.isp_mipi_hnum_unmatch().bit()),
-            )
-            .field(
-                "dpc_check_done",
-                &format_args!("{}", self.dpc_check_done().bit()),
-            )
-            .field(
-                "gamma_xcoord_err",
-                &format_args!("{}", self.gamma_xcoord_err().bit()),
-            )
-            .field("ae_monitor", &format_args!("{}", self.ae_monitor().bit()))
-            .field(
-                "ae_frame_done",
-                &format_args!("{}", self.ae_frame_done().bit()),
-            )
-            .field("af_fdone", &format_args!("{}", self.af_fdone().bit()))
-            .field("af_env", &format_args!("{}", self.af_env().bit()))
-            .field("awb_fdone", &format_args!("{}", self.awb_fdone().bit()))
-            .field("hist_fdone", &format_args!("{}", self.hist_fdone().bit()))
-            .field("frame", &format_args!("{}", self.frame().bit()))
-            .field("blc_frame", &format_args!("{}", self.blc_frame().bit()))
-            .field("lsc_frame", &format_args!("{}", self.lsc_frame().bit()))
-            .field("dpc_frame", &format_args!("{}", self.dpc_frame().bit()))
-            .field("bf_frame", &format_args!("{}", self.bf_frame().bit()))
-            .field(
-                "demosaic_frame",
-                &format_args!("{}", self.demosaic_frame().bit()),
-            )
-            .field(
-                "median_frame",
-                &format_args!("{}", self.median_frame().bit()),
-            )
-            .field("ccm_frame", &format_args!("{}", self.ccm_frame().bit()))
-            .field("gamma_frame", &format_args!("{}", self.gamma_frame().bit()))
-            .field(
-                "rgb2yuv_frame",
-                &format_args!("{}", self.rgb2yuv_frame().bit()),
-            )
-            .field("sharp_frame", &format_args!("{}", self.sharp_frame().bit()))
-            .field("color_frame", &format_args!("{}", self.color_frame().bit()))
-            .field(
-                "yuv2rgb_frame",
-                &format_args!("{}", self.yuv2rgb_frame().bit()),
-            )
-            .field(
-                "tail_idi_frame",
-                &format_args!("{}", self.tail_idi_frame().bit()),
-            )
-            .field(
-                "header_idi_frame",
-                &format_args!("{}", self.header_idi_frame().bit()),
+                &self.isp_data_type_setting_err(),
             )
+            .field("isp_mipi_hnum_unmatch", &self.isp_mipi_hnum_unmatch())
+            .field("dpc_check_done", &self.dpc_check_done())
+            .field("gamma_xcoord_err", &self.gamma_xcoord_err())
+            .field("ae_monitor", &self.ae_monitor())
+            .field("ae_frame_done", &self.ae_frame_done())
+            .field("af_fdone", &self.af_fdone())
+            .field("af_env", &self.af_env())
+            .field("awb_fdone", &self.awb_fdone())
+            .field("hist_fdone", &self.hist_fdone())
+            .field("frame", &self.frame())
+            .field("blc_frame", &self.blc_frame())
+            .field("lsc_frame", &self.lsc_frame())
+            .field("dpc_frame", &self.dpc_frame())
+            .field("bf_frame", &self.bf_frame())
+            .field("demosaic_frame", &self.demosaic_frame())
+            .field("median_frame", &self.median_frame())
+            .field("ccm_frame", &self.ccm_frame())
+            .field("gamma_frame", &self.gamma_frame())
+            .field("rgb2yuv_frame", &self.rgb2yuv_frame())
+            .field("sharp_frame", &self.sharp_frame())
+            .field("color_frame", &self.color_frame())
+            .field("yuv2rgb_frame", &self.yuv2rgb_frame())
+            .field("tail_idi_frame", &self.tail_idi_frame())
+            .field("header_idi_frame", &self.header_idi_frame())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - write 1 to enable input data type error"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/int_raw.rs b/esp32p4/src/isp/int_raw.rs
index 15a6720475..251a5c6b9f 100644
--- a/esp32p4/src/isp/int_raw.rs
+++ b/esp32p4/src/isp/int_raw.rs
@@ -209,89 +209,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "isp_data_type_err",
-                &format_args!("{}", self.isp_data_type_err().bit()),
-            )
-            .field(
-                "isp_async_fifo_ovf",
-                &format_args!("{}", self.isp_async_fifo_ovf().bit()),
-            )
-            .field(
-                "isp_buf_full",
-                &format_args!("{}", self.isp_buf_full().bit()),
-            )
-            .field(
-                "isp_hvnum_setting_err",
-                &format_args!("{}", self.isp_hvnum_setting_err().bit()),
-            )
+            .field("isp_data_type_err", &self.isp_data_type_err())
+            .field("isp_async_fifo_ovf", &self.isp_async_fifo_ovf())
+            .field("isp_buf_full", &self.isp_buf_full())
+            .field("isp_hvnum_setting_err", &self.isp_hvnum_setting_err())
             .field(
                 "isp_data_type_setting_err",
-                &format_args!("{}", self.isp_data_type_setting_err().bit()),
-            )
-            .field(
-                "isp_mipi_hnum_unmatch",
-                &format_args!("{}", self.isp_mipi_hnum_unmatch().bit()),
-            )
-            .field(
-                "dpc_check_done",
-                &format_args!("{}", self.dpc_check_done().bit()),
-            )
-            .field(
-                "gamma_xcoord_err",
-                &format_args!("{}", self.gamma_xcoord_err().bit()),
-            )
-            .field("ae_monitor", &format_args!("{}", self.ae_monitor().bit()))
-            .field(
-                "ae_frame_done",
-                &format_args!("{}", self.ae_frame_done().bit()),
-            )
-            .field("af_fdone", &format_args!("{}", self.af_fdone().bit()))
-            .field("af_env", &format_args!("{}", self.af_env().bit()))
-            .field("awb_fdone", &format_args!("{}", self.awb_fdone().bit()))
-            .field("hist_fdone", &format_args!("{}", self.hist_fdone().bit()))
-            .field("frame", &format_args!("{}", self.frame().bit()))
-            .field("blc_frame", &format_args!("{}", self.blc_frame().bit()))
-            .field("lsc_frame", &format_args!("{}", self.lsc_frame().bit()))
-            .field("dpc_frame", &format_args!("{}", self.dpc_frame().bit()))
-            .field("bf_frame", &format_args!("{}", self.bf_frame().bit()))
-            .field(
-                "demosaic_frame",
-                &format_args!("{}", self.demosaic_frame().bit()),
-            )
-            .field(
-                "median_frame",
-                &format_args!("{}", self.median_frame().bit()),
-            )
-            .field("ccm_frame", &format_args!("{}", self.ccm_frame().bit()))
-            .field("gamma_frame", &format_args!("{}", self.gamma_frame().bit()))
-            .field(
-                "rgb2yuv_frame",
-                &format_args!("{}", self.rgb2yuv_frame().bit()),
-            )
-            .field("sharp_frame", &format_args!("{}", self.sharp_frame().bit()))
-            .field("color_frame", &format_args!("{}", self.color_frame().bit()))
-            .field(
-                "yuv2rgb_frame",
-                &format_args!("{}", self.yuv2rgb_frame().bit()),
-            )
-            .field(
-                "tail_idi_frame",
-                &format_args!("{}", self.tail_idi_frame().bit()),
-            )
-            .field(
-                "header_idi_frame",
-                &format_args!("{}", self.header_idi_frame().bit()),
+                &self.isp_data_type_setting_err(),
             )
+            .field("isp_mipi_hnum_unmatch", &self.isp_mipi_hnum_unmatch())
+            .field("dpc_check_done", &self.dpc_check_done())
+            .field("gamma_xcoord_err", &self.gamma_xcoord_err())
+            .field("ae_monitor", &self.ae_monitor())
+            .field("ae_frame_done", &self.ae_frame_done())
+            .field("af_fdone", &self.af_fdone())
+            .field("af_env", &self.af_env())
+            .field("awb_fdone", &self.awb_fdone())
+            .field("hist_fdone", &self.hist_fdone())
+            .field("frame", &self.frame())
+            .field("blc_frame", &self.blc_frame())
+            .field("lsc_frame", &self.lsc_frame())
+            .field("dpc_frame", &self.dpc_frame())
+            .field("bf_frame", &self.bf_frame())
+            .field("demosaic_frame", &self.demosaic_frame())
+            .field("median_frame", &self.median_frame())
+            .field("ccm_frame", &self.ccm_frame())
+            .field("gamma_frame", &self.gamma_frame())
+            .field("rgb2yuv_frame", &self.rgb2yuv_frame())
+            .field("sharp_frame", &self.sharp_frame())
+            .field("color_frame", &self.color_frame())
+            .field("yuv2rgb_frame", &self.yuv2rgb_frame())
+            .field("tail_idi_frame", &self.tail_idi_frame())
+            .field("header_idi_frame", &self.header_idi_frame())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "raw interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32p4/src/isp/int_st.rs b/esp32p4/src/isp/int_st.rs
index 226f44e9c7..d635037b16 100644
--- a/esp32p4/src/isp/int_st.rs
+++ b/esp32p4/src/isp/int_st.rs
@@ -209,89 +209,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "isp_data_type_err",
-                &format_args!("{}", self.isp_data_type_err().bit()),
-            )
-            .field(
-                "isp_async_fifo_ovf",
-                &format_args!("{}", self.isp_async_fifo_ovf().bit()),
-            )
-            .field(
-                "isp_buf_full",
-                &format_args!("{}", self.isp_buf_full().bit()),
-            )
-            .field(
-                "isp_hvnum_setting_err",
-                &format_args!("{}", self.isp_hvnum_setting_err().bit()),
-            )
+            .field("isp_data_type_err", &self.isp_data_type_err())
+            .field("isp_async_fifo_ovf", &self.isp_async_fifo_ovf())
+            .field("isp_buf_full", &self.isp_buf_full())
+            .field("isp_hvnum_setting_err", &self.isp_hvnum_setting_err())
             .field(
                 "isp_data_type_setting_err",
-                &format_args!("{}", self.isp_data_type_setting_err().bit()),
-            )
-            .field(
-                "isp_mipi_hnum_unmatch",
-                &format_args!("{}", self.isp_mipi_hnum_unmatch().bit()),
-            )
-            .field(
-                "dpc_check_done",
-                &format_args!("{}", self.dpc_check_done().bit()),
-            )
-            .field(
-                "gamma_xcoord_err",
-                &format_args!("{}", self.gamma_xcoord_err().bit()),
-            )
-            .field("ae_monitor", &format_args!("{}", self.ae_monitor().bit()))
-            .field(
-                "ae_frame_done",
-                &format_args!("{}", self.ae_frame_done().bit()),
-            )
-            .field("af_fdone", &format_args!("{}", self.af_fdone().bit()))
-            .field("af_env", &format_args!("{}", self.af_env().bit()))
-            .field("awb_fdone", &format_args!("{}", self.awb_fdone().bit()))
-            .field("hist_fdone", &format_args!("{}", self.hist_fdone().bit()))
-            .field("frame", &format_args!("{}", self.frame().bit()))
-            .field("blc_frame", &format_args!("{}", self.blc_frame().bit()))
-            .field("lsc_frame", &format_args!("{}", self.lsc_frame().bit()))
-            .field("dpc_frame", &format_args!("{}", self.dpc_frame().bit()))
-            .field("bf_frame", &format_args!("{}", self.bf_frame().bit()))
-            .field(
-                "demosaic_frame",
-                &format_args!("{}", self.demosaic_frame().bit()),
-            )
-            .field(
-                "median_frame",
-                &format_args!("{}", self.median_frame().bit()),
-            )
-            .field("ccm_frame", &format_args!("{}", self.ccm_frame().bit()))
-            .field("gamma_frame", &format_args!("{}", self.gamma_frame().bit()))
-            .field(
-                "rgb2yuv_frame",
-                &format_args!("{}", self.rgb2yuv_frame().bit()),
-            )
-            .field("sharp_frame", &format_args!("{}", self.sharp_frame().bit()))
-            .field("color_frame", &format_args!("{}", self.color_frame().bit()))
-            .field(
-                "yuv2rgb_frame",
-                &format_args!("{}", self.yuv2rgb_frame().bit()),
-            )
-            .field(
-                "tail_idi_frame",
-                &format_args!("{}", self.tail_idi_frame().bit()),
-            )
-            .field(
-                "header_idi_frame",
-                &format_args!("{}", self.header_idi_frame().bit()),
+                &self.isp_data_type_setting_err(),
             )
+            .field("isp_mipi_hnum_unmatch", &self.isp_mipi_hnum_unmatch())
+            .field("dpc_check_done", &self.dpc_check_done())
+            .field("gamma_xcoord_err", &self.gamma_xcoord_err())
+            .field("ae_monitor", &self.ae_monitor())
+            .field("ae_frame_done", &self.ae_frame_done())
+            .field("af_fdone", &self.af_fdone())
+            .field("af_env", &self.af_env())
+            .field("awb_fdone", &self.awb_fdone())
+            .field("hist_fdone", &self.hist_fdone())
+            .field("frame", &self.frame())
+            .field("blc_frame", &self.blc_frame())
+            .field("lsc_frame", &self.lsc_frame())
+            .field("dpc_frame", &self.dpc_frame())
+            .field("bf_frame", &self.bf_frame())
+            .field("demosaic_frame", &self.demosaic_frame())
+            .field("median_frame", &self.median_frame())
+            .field("ccm_frame", &self.ccm_frame())
+            .field("gamma_frame", &self.gamma_frame())
+            .field("rgb2yuv_frame", &self.rgb2yuv_frame())
+            .field("sharp_frame", &self.sharp_frame())
+            .field("color_frame", &self.color_frame())
+            .field("yuv2rgb_frame", &self.yuv2rgb_frame())
+            .field("tail_idi_frame", &self.tail_idi_frame())
+            .field("header_idi_frame", &self.header_idi_frame())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/isp/lsc_tablesize.rs b/esp32p4/src/isp/lsc_tablesize.rs
index e990bd5875..4afa2bc8bf 100644
--- a/esp32p4/src/isp/lsc_tablesize.rs
+++ b/esp32p4/src/isp/lsc_tablesize.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LSC_TABLESIZE")
-            .field(
-                "lsc_xtablesize",
-                &format_args!("{}", self.lsc_xtablesize().bits()),
-            )
+            .field("lsc_xtablesize", &self.lsc_xtablesize())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LSC_TABLESIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this field configures lsc table size in x-direction"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/lut_rdata.rs b/esp32p4/src/isp/lut_rdata.rs
index e5c92bce4b..e5ada239ac 100644
--- a/esp32p4/src/isp/lut_rdata.rs
+++ b/esp32p4/src/isp/lut_rdata.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LUT_RDATA")
-            .field("lut_rdata", &format_args!("{}", self.lut_rdata().bits()))
+            .field("lut_rdata", &self.lut_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LUT_RDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "LUT read data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lut_rdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LUT_RDATA_SPEC;
 impl crate::RegisterSpec for LUT_RDATA_SPEC {
diff --git a/esp32p4/src/isp/lut_wdata.rs b/esp32p4/src/isp/lut_wdata.rs
index bebb901095..ffc53b6fe6 100644
--- a/esp32p4/src/isp/lut_wdata.rs
+++ b/esp32p4/src/isp/lut_wdata.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LUT_WDATA")
-            .field("lut_wdata", &format_args!("{}", self.lut_wdata().bits()))
+            .field("lut_wdata", &self.lut_wdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LUT_WDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - this field configures the write data of lut. please initial ISP_LUT_WDATA before write ISP_LUT_CMD register"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/median_matrix_ctrl.rs b/esp32p4/src/isp/median_matrix_ctrl.rs
index ff502f498b..8be17e32ae 100644
--- a/esp32p4/src/isp/median_matrix_ctrl.rs
+++ b/esp32p4/src/isp/median_matrix_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEDIAN_MATRIX_CTRL")
-            .field(
-                "median_padding_data",
-                &format_args!("{}", self.median_padding_data().bits()),
-            )
-            .field(
-                "median_padding_mode",
-                &format_args!("{}", self.median_padding_mode().bit()),
-            )
+            .field("median_padding_data", &self.median_padding_data())
+            .field("median_padding_mode", &self.median_padding_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEDIAN_MATRIX_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures median matrix padding data"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/mem_aux_ctrl_0.rs b/esp32p4/src/isp/mem_aux_ctrl_0.rs
index b9474bed44..581c6662db 100644
--- a/esp32p4/src/isp/mem_aux_ctrl_0.rs
+++ b/esp32p4/src/isp/mem_aux_ctrl_0.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_AUX_CTRL_0")
-            .field(
-                "header_mem_aux_ctrl",
-                &format_args!("{}", self.header_mem_aux_ctrl().bits()),
-            )
-            .field(
-                "dpc_lut_mem_aux_ctrl",
-                &format_args!("{}", self.dpc_lut_mem_aux_ctrl().bits()),
-            )
+            .field("header_mem_aux_ctrl", &self.header_mem_aux_ctrl())
+            .field("dpc_lut_mem_aux_ctrl", &self.dpc_lut_mem_aux_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_AUX_CTRL_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - this field configures the mem_aux of isp input buffer memory"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/mem_aux_ctrl_1.rs b/esp32p4/src/isp/mem_aux_ctrl_1.rs
index 837c57b080..b53ac3e758 100644
--- a/esp32p4/src/isp/mem_aux_ctrl_1.rs
+++ b/esp32p4/src/isp/mem_aux_ctrl_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("MEM_AUX_CTRL_1")
             .field(
                 "lsc_lut_r_gr_mem_aux_ctrl",
-                &format_args!("{}", self.lsc_lut_r_gr_mem_aux_ctrl().bits()),
+                &self.lsc_lut_r_gr_mem_aux_ctrl(),
             )
             .field(
                 "lsc_lut_gb_b_mem_aux_ctrl",
-                &format_args!("{}", self.lsc_lut_gb_b_mem_aux_ctrl().bits()),
+                &self.lsc_lut_gb_b_mem_aux_ctrl(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_AUX_CTRL_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - this field configures the mem_aux of lsc r gr lut memory"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/mem_aux_ctrl_2.rs b/esp32p4/src/isp/mem_aux_ctrl_2.rs
index 393dd4ed27..83bdde876c 100644
--- a/esp32p4/src/isp/mem_aux_ctrl_2.rs
+++ b/esp32p4/src/isp/mem_aux_ctrl_2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_AUX_CTRL_2")
-            .field(
-                "bf_matrix_mem_aux_ctrl",
-                &format_args!("{}", self.bf_matrix_mem_aux_ctrl().bits()),
-            )
-            .field(
-                "dpc_matrix_mem_aux_ctrl",
-                &format_args!("{}", self.dpc_matrix_mem_aux_ctrl().bits()),
-            )
+            .field("bf_matrix_mem_aux_ctrl", &self.bf_matrix_mem_aux_ctrl())
+            .field("dpc_matrix_mem_aux_ctrl", &self.dpc_matrix_mem_aux_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_AUX_CTRL_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - this field configures the mem_aux of bf line buffer memory"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/mem_aux_ctrl_3.rs b/esp32p4/src/isp/mem_aux_ctrl_3.rs
index 3af0c49944..5b3e500f0a 100644
--- a/esp32p4/src/isp/mem_aux_ctrl_3.rs
+++ b/esp32p4/src/isp/mem_aux_ctrl_3.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("MEM_AUX_CTRL_3")
             .field(
                 "sharp_matrix_y_mem_aux_ctrl",
-                &format_args!("{}", self.sharp_matrix_y_mem_aux_ctrl().bits()),
+                &self.sharp_matrix_y_mem_aux_ctrl(),
             )
             .field(
                 "demosaic_matrix_mem_aux_ctrl",
-                &format_args!("{}", self.demosaic_matrix_mem_aux_ctrl().bits()),
+                &self.demosaic_matrix_mem_aux_ctrl(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_AUX_CTRL_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - this field configures the mem_aux of sharp y line buffer memory"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/mem_aux_ctrl_4.rs b/esp32p4/src/isp/mem_aux_ctrl_4.rs
index 238cfd539e..53f464a8ac 100644
--- a/esp32p4/src/isp/mem_aux_ctrl_4.rs
+++ b/esp32p4/src/isp/mem_aux_ctrl_4.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("MEM_AUX_CTRL_4")
             .field(
                 "sharp_matrix_uv_mem_aux_ctrl",
-                &format_args!("{}", self.sharp_matrix_uv_mem_aux_ctrl().bits()),
+                &self.sharp_matrix_uv_mem_aux_ctrl(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_AUX_CTRL_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - this field configures the mem_aux of sharp uv line buffer memory"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/rdn_eco_cs.rs b/esp32p4/src/isp/rdn_eco_cs.rs
index da543ffd30..7c8d3022d3 100644
--- a/esp32p4/src/isp/rdn_eco_cs.rs
+++ b/esp32p4/src/isp/rdn_eco_cs.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDN_ECO_CS")
-            .field("rdn_eco_en", &format_args!("{}", self.rdn_eco_en().bit()))
-            .field(
-                "rdn_eco_result",
-                &format_args!("{}", self.rdn_eco_result().bit()),
-            )
+            .field("rdn_eco_en", &self.rdn_eco_en())
+            .field("rdn_eco_result", &self.rdn_eco_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDN_ECO_CS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - rdn_eco_en"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/rdn_eco_high.rs b/esp32p4/src/isp/rdn_eco_high.rs
index d39b4a4cf6..726c2ca48b 100644
--- a/esp32p4/src/isp/rdn_eco_high.rs
+++ b/esp32p4/src/isp/rdn_eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDN_ECO_HIGH")
-            .field(
-                "rdn_eco_high",
-                &format_args!("{}", self.rdn_eco_high().bits()),
-            )
+            .field("rdn_eco_high", &self.rdn_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDN_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - rdn_eco_high"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/rdn_eco_low.rs b/esp32p4/src/isp/rdn_eco_low.rs
index 8bf7219130..2ae919c695 100644
--- a/esp32p4/src/isp/rdn_eco_low.rs
+++ b/esp32p4/src/isp/rdn_eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDN_ECO_LOW")
-            .field(
-                "rdn_eco_low",
-                &format_args!("{}", self.rdn_eco_low().bits()),
-            )
+            .field("rdn_eco_low", &self.rdn_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDN_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - rdn_eco_low"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/sharp_ctrl0.rs b/esp32p4/src/isp/sharp_ctrl0.rs
index f10c97665d..956e51a5cb 100644
--- a/esp32p4/src/isp/sharp_ctrl0.rs
+++ b/esp32p4/src/isp/sharp_ctrl0.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHARP_CTRL0")
-            .field(
-                "sharp_threshold_low",
-                &format_args!("{}", self.sharp_threshold_low().bits()),
-            )
-            .field(
-                "sharp_threshold_high",
-                &format_args!("{}", self.sharp_threshold_high().bits()),
-            )
-            .field(
-                "sharp_amount_low",
-                &format_args!("{}", self.sharp_amount_low().bits()),
-            )
-            .field(
-                "sharp_amount_high",
-                &format_args!("{}", self.sharp_amount_high().bits()),
-            )
+            .field("sharp_threshold_low", &self.sharp_threshold_low())
+            .field("sharp_threshold_high", &self.sharp_threshold_high())
+            .field("sharp_amount_low", &self.sharp_amount_low())
+            .field("sharp_amount_high", &self.sharp_amount_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHARP_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - this field configures sharpen threshold for detail"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/sharp_ctrl1.rs b/esp32p4/src/isp/sharp_ctrl1.rs
index ae33e38055..0074273559 100644
--- a/esp32p4/src/isp/sharp_ctrl1.rs
+++ b/esp32p4/src/isp/sharp_ctrl1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHARP_CTRL1")
-            .field(
-                "sharp_gradient_max",
-                &format_args!("{}", self.sharp_gradient_max().bits()),
-            )
+            .field("sharp_gradient_max", &self.sharp_gradient_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHARP_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "sharp control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sharp_ctrl1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SHARP_CTRL1_SPEC;
 impl crate::RegisterSpec for SHARP_CTRL1_SPEC {
diff --git a/esp32p4/src/isp/sharp_filter0.rs b/esp32p4/src/isp/sharp_filter0.rs
index 03d9e1d1d5..586ff0c9d9 100644
--- a/esp32p4/src/isp/sharp_filter0.rs
+++ b/esp32p4/src/isp/sharp_filter0.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHARP_FILTER0")
-            .field(
-                "sharp_filter_coe00",
-                &format_args!("{}", self.sharp_filter_coe00().bits()),
-            )
-            .field(
-                "sharp_filter_coe01",
-                &format_args!("{}", self.sharp_filter_coe01().bits()),
-            )
-            .field(
-                "sharp_filter_coe02",
-                &format_args!("{}", self.sharp_filter_coe02().bits()),
-            )
+            .field("sharp_filter_coe00", &self.sharp_filter_coe00())
+            .field("sharp_filter_coe01", &self.sharp_filter_coe01())
+            .field("sharp_filter_coe02", &self.sharp_filter_coe02())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHARP_FILTER0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this field configures unsharp masking(usm) filter coefficient"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/sharp_filter1.rs b/esp32p4/src/isp/sharp_filter1.rs
index 2ea24f077e..10d9de4348 100644
--- a/esp32p4/src/isp/sharp_filter1.rs
+++ b/esp32p4/src/isp/sharp_filter1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHARP_FILTER1")
-            .field(
-                "sharp_filter_coe10",
-                &format_args!("{}", self.sharp_filter_coe10().bits()),
-            )
-            .field(
-                "sharp_filter_coe11",
-                &format_args!("{}", self.sharp_filter_coe11().bits()),
-            )
-            .field(
-                "sharp_filter_coe12",
-                &format_args!("{}", self.sharp_filter_coe12().bits()),
-            )
+            .field("sharp_filter_coe10", &self.sharp_filter_coe10())
+            .field("sharp_filter_coe11", &self.sharp_filter_coe11())
+            .field("sharp_filter_coe12", &self.sharp_filter_coe12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHARP_FILTER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this field configures usm filter coefficient"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/sharp_filter2.rs b/esp32p4/src/isp/sharp_filter2.rs
index 7eddacf6e0..f91cdd545f 100644
--- a/esp32p4/src/isp/sharp_filter2.rs
+++ b/esp32p4/src/isp/sharp_filter2.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHARP_FILTER2")
-            .field(
-                "sharp_filter_coe20",
-                &format_args!("{}", self.sharp_filter_coe20().bits()),
-            )
-            .field(
-                "sharp_filter_coe21",
-                &format_args!("{}", self.sharp_filter_coe21().bits()),
-            )
-            .field(
-                "sharp_filter_coe22",
-                &format_args!("{}", self.sharp_filter_coe22().bits()),
-            )
+            .field("sharp_filter_coe20", &self.sharp_filter_coe20())
+            .field("sharp_filter_coe21", &self.sharp_filter_coe21())
+            .field("sharp_filter_coe22", &self.sharp_filter_coe22())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHARP_FILTER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this field configures usm filter coefficient"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/sharp_matrix_ctrl.rs b/esp32p4/src/isp/sharp_matrix_ctrl.rs
index 7075ae0af3..42e9d5bd92 100644
--- a/esp32p4/src/isp/sharp_matrix_ctrl.rs
+++ b/esp32p4/src/isp/sharp_matrix_ctrl.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("SHARP_MATRIX_CTRL")
             .field(
                 "sharp_tail_pixen_pulse_tl",
-                &format_args!("{}", self.sharp_tail_pixen_pulse_tl().bits()),
+                &self.sharp_tail_pixen_pulse_tl(),
             )
             .field(
                 "sharp_tail_pixen_pulse_th",
-                &format_args!("{}", self.sharp_tail_pixen_pulse_th().bits()),
-            )
-            .field(
-                "sharp_padding_data",
-                &format_args!("{}", self.sharp_padding_data().bits()),
-            )
-            .field(
-                "sharp_padding_mode",
-                &format_args!("{}", self.sharp_padding_mode().bit()),
+                &self.sharp_tail_pixen_pulse_th(),
             )
+            .field("sharp_padding_data", &self.sharp_padding_data())
+            .field("sharp_padding_mode", &self.sharp_padding_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHARP_MATRIX_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th &lt; reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/ver_date.rs b/esp32p4/src/isp/ver_date.rs
index 87afc7ae56..7f34b42887 100644
--- a/esp32p4/src/isp/ver_date.rs
+++ b/esp32p4/src/isp/ver_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VER_DATE")
-            .field("ver_data", &format_args!("{}", self.ver_data().bits()))
+            .field("ver_data", &self.ver_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VER_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - csv version"]
     #[inline(always)]
diff --git a/esp32p4/src/isp/yuv_format.rs b/esp32p4/src/isp/yuv_format.rs
index a7c567632c..0f297e01df 100644
--- a/esp32p4/src/isp/yuv_format.rs
+++ b/esp32p4/src/isp/yuv_format.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("YUV_FORMAT")
-            .field("yuv_mode", &format_args!("{}", self.yuv_mode().bit()))
-            .field("yuv_range", &format_args!("{}", self.yuv_range().bit()))
+            .field("yuv_mode", &self.yuv_mode())
+            .field("yuv_range", &self.yuv_range())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<YUV_FORMAT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709"]
     #[inline(always)]
diff --git a/esp32p4/src/jpeg/c.rs b/esp32p4/src/jpeg/c.rs
index 64f2677b9a..e1731e0aea 100644
--- a/esp32p4/src/jpeg/c.rs
+++ b/esp32p4/src/jpeg/c.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("C")
-            .field(
-                "dqt_tbl_sel",
-                &format_args!("{}", self.dqt_tbl_sel().bits()),
-            )
-            .field("y_factor", &format_args!("{}", self.y_factor().bits()))
-            .field("x_factor", &format_args!("{}", self.x_factor().bits()))
-            .field("id", &format_args!("{}", self.id().bits()))
+            .field("dqt_tbl_sel", &self.dqt_tbl_sel())
+            .field("y_factor", &self.y_factor())
+            .field("x_factor", &self.x_factor())
+            .field("id", &self.id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<C_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - choose c0 quntization table id (TBD)"]
     #[inline(always)]
diff --git a/esp32p4/src/jpeg/config.rs b/esp32p4/src/jpeg/config.rs
index 2aba9bfcb7..dcbcb914bb 100644
--- a/esp32p4/src/jpeg/config.rs
+++ b/esp32p4/src/jpeg/config.rs
@@ -199,66 +199,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG")
-            .field(
-                "qnr_presition",
-                &format_args!("{}", self.qnr_presition().bit()),
-            )
-            .field("ff_check_en", &format_args!("{}", self.ff_check_en().bit()))
-            .field("sample_sel", &format_args!("{}", self.sample_sel().bits()))
-            .field(
-                "dma_linklist_mode",
-                &format_args!("{}", self.dma_linklist_mode().bit()),
-            )
-            .field(
-                "debug_direct_out_en",
-                &format_args!("{}", self.debug_direct_out_en().bit()),
-            )
-            .field("gray_sel", &format_args!("{}", self.gray_sel().bit()))
-            .field(
-                "lqnr_tbl_sel",
-                &format_args!("{}", self.lqnr_tbl_sel().bits()),
-            )
-            .field(
-                "cqnr_tbl_sel",
-                &format_args!("{}", self.cqnr_tbl_sel().bits()),
-            )
-            .field(
-                "color_space",
-                &format_args!("{}", self.color_space().bits()),
-            )
-            .field("dht_fifo_en", &format_args!("{}", self.dht_fifo_en().bit()))
-            .field(
-                "mem_clk_force_on",
-                &format_args!("{}", self.mem_clk_force_on().bit()),
-            )
-            .field("jfif_ver", &format_args!("{}", self.jfif_ver().bits()))
-            .field(
-                "decode_timeout_task_sel",
-                &format_args!("{}", self.decode_timeout_task_sel().bit()),
-            )
-            .field("soft_rst", &format_args!("{}", self.soft_rst().bit()))
-            .field("fifo_rst", &format_args!("{}", self.fifo_rst().bit()))
-            .field("pixel_rev", &format_args!("{}", self.pixel_rev().bit()))
-            .field("tailer_en", &format_args!("{}", self.tailer_en().bit()))
-            .field("pause_en", &format_args!("{}", self.pause_en().bit()))
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
-            .field("mode", &format_args!("{}", self.mode().bit()))
+            .field("qnr_presition", &self.qnr_presition())
+            .field("ff_check_en", &self.ff_check_en())
+            .field("sample_sel", &self.sample_sel())
+            .field("dma_linklist_mode", &self.dma_linklist_mode())
+            .field("debug_direct_out_en", &self.debug_direct_out_en())
+            .field("gray_sel", &self.gray_sel())
+            .field("lqnr_tbl_sel", &self.lqnr_tbl_sel())
+            .field("cqnr_tbl_sel", &self.cqnr_tbl_sel())
+            .field("color_space", &self.color_space())
+            .field("dht_fifo_en", &self.dht_fifo_en())
+            .field("mem_clk_force_on", &self.mem_clk_force_on())
+            .field("jfif_ver", &self.jfif_ver())
+            .field("decode_timeout_task_sel", &self.decode_timeout_task_sel())
+            .field("soft_rst", &self.soft_rst())
+            .field("fifo_rst", &self.fifo_rst())
+            .field("pixel_rev", &self.pixel_rev())
+            .field("tailer_en", &self.tailer_en())
+            .field("pause_en", &self.pause_en())
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
+            .field("mode", &self.mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - fsm reset"]
     #[inline(always)]
diff --git a/esp32p4/src/jpeg/decode_conf.rs b/esp32p4/src/jpeg/decode_conf.rs
index 737ed13b24..91619a693e 100644
--- a/esp32p4/src/jpeg/decode_conf.rs
+++ b/esp32p4/src/jpeg/decode_conf.rs
@@ -69,40 +69,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DECODE_CONF")
-            .field(
-                "restart_interval",
-                &format_args!("{}", self.restart_interval().bits()),
-            )
-            .field(
-                "component_num",
-                &format_args!("{}", self.component_num().bits()),
-            )
-            .field("sw_dht_en", &format_args!("{}", self.sw_dht_en().bit()))
-            .field(
-                "sos_check_byte_num",
-                &format_args!("{}", self.sos_check_byte_num().bits()),
-            )
-            .field(
-                "rst_check_byte_num",
-                &format_args!("{}", self.rst_check_byte_num().bits()),
-            )
-            .field(
-                "multi_scan_err_check",
-                &format_args!("{}", self.multi_scan_err_check().bit()),
-            )
-            .field(
-                "dezigzag_ready_ctl",
-                &format_args!("{}", self.dezigzag_ready_ctl().bit()),
-            )
+            .field("restart_interval", &self.restart_interval())
+            .field("component_num", &self.component_num())
+            .field("sw_dht_en", &self.sw_dht_en())
+            .field("sos_check_byte_num", &self.sos_check_byte_num())
+            .field("rst_check_byte_num", &self.rst_check_byte_num())
+            .field("multi_scan_err_check", &self.multi_scan_err_check())
+            .field("dezigzag_ready_ctl", &self.dezigzag_ready_ctl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DECODE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - configure restart interval in DRI marker when decode"]
     #[inline(always)]
diff --git a/esp32p4/src/jpeg/decoder_status0.rs b/esp32p4/src/jpeg/decoder_status0.rs
index 93e6e05dbf..48de7af304 100644
--- a/esp32p4/src/jpeg/decoder_status0.rs
+++ b/esp32p4/src/jpeg/decoder_status0.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DECODER_STATUS0")
-            .field(
-                "decode_byte_cnt",
-                &format_args!("{}", self.decode_byte_cnt().bits()),
-            )
-            .field(
-                "header_dec_st",
-                &format_args!("{}", self.header_dec_st().bits()),
-            )
-            .field(
-                "decode_sample_sel",
-                &format_args!("{}", self.decode_sample_sel().bits()),
-            )
+            .field("decode_byte_cnt", &self.decode_byte_cnt())
+            .field("header_dec_st", &self.header_dec_st())
+            .field("decode_sample_sel", &self.decode_sample_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DECODER_STATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DECODER_STATUS0_SPEC;
 impl crate::RegisterSpec for DECODER_STATUS0_SPEC {
diff --git a/esp32p4/src/jpeg/decoder_status1.rs b/esp32p4/src/jpeg/decoder_status1.rs
index 7a5f41c1e6..84f170e0f5 100644
--- a/esp32p4/src/jpeg/decoder_status1.rs
+++ b/esp32p4/src/jpeg/decoder_status1.rs
@@ -34,28 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DECODER_STATUS1")
-            .field(
-                "encode_data",
-                &format_args!("{}", self.encode_data().bits()),
-            )
-            .field("count_q", &format_args!("{}", self.count_q().bits()))
-            .field(
-                "mcu_fsm_ready",
-                &format_args!("{}", self.mcu_fsm_ready().bit()),
-            )
-            .field(
-                "decode_data",
-                &format_args!("{}", self.decode_data().bits()),
-            )
+            .field("encode_data", &self.encode_data())
+            .field("count_q", &self.count_q())
+            .field("mcu_fsm_ready", &self.mcu_fsm_ready())
+            .field("decode_data", &self.decode_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DECODER_STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DECODER_STATUS1_SPEC;
 impl crate::RegisterSpec for DECODER_STATUS1_SPEC {
diff --git a/esp32p4/src/jpeg/decoder_status2.rs b/esp32p4/src/jpeg/decoder_status2.rs
index b585aa422e..de6dd8649f 100644
--- a/esp32p4/src/jpeg/decoder_status2.rs
+++ b/esp32p4/src/jpeg/decoder_status2.rs
@@ -41,29 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DECODER_STATUS2")
-            .field(
-                "comp_block_num",
-                &format_args!("{}", self.comp_block_num().bits()),
-            )
-            .field("scan_num", &format_args!("{}", self.scan_num().bits()))
-            .field(
-                "rst_check_wait",
-                &format_args!("{}", self.rst_check_wait().bit()),
-            )
-            .field(
-                "scan_check_wait",
-                &format_args!("{}", self.scan_check_wait().bit()),
-            )
-            .field("mcu_in_proc", &format_args!("{}", self.mcu_in_proc().bit()))
+            .field("comp_block_num", &self.comp_block_num())
+            .field("scan_num", &self.scan_num())
+            .field("rst_check_wait", &self.rst_check_wait())
+            .field("scan_check_wait", &self.scan_check_wait())
+            .field("mcu_in_proc", &self.mcu_in_proc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DECODER_STATUS2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DECODER_STATUS2_SPEC;
 impl crate::RegisterSpec for DECODER_STATUS2_SPEC {
diff --git a/esp32p4/src/jpeg/decoder_status3.rs b/esp32p4/src/jpeg/decoder_status3.rs
index 5a05d32442..b7ac8caa4e 100644
--- a/esp32p4/src/jpeg/decoder_status3.rs
+++ b/esp32p4/src/jpeg/decoder_status3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DECODER_STATUS3")
-            .field(
-                "lookup_data",
-                &format_args!("{}", self.lookup_data().bits()),
-            )
+            .field("lookup_data", &self.lookup_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DECODER_STATUS3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DECODER_STATUS3_SPEC;
 impl crate::RegisterSpec for DECODER_STATUS3_SPEC {
diff --git a/esp32p4/src/jpeg/decoder_status4.rs b/esp32p4/src/jpeg/decoder_status4.rs
index 422ae81494..6196b7e1d1 100644
--- a/esp32p4/src/jpeg/decoder_status4.rs
+++ b/esp32p4/src/jpeg/decoder_status4.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DECODER_STATUS4")
-            .field(
-                "block_eof_cnt",
-                &format_args!("{}", self.block_eof_cnt().bits()),
-            )
-            .field(
-                "dezigzag_ready",
-                &format_args!("{}", self.dezigzag_ready().bit()),
-            )
-            .field(
-                "de_frame_eof_check",
-                &format_args!("{}", self.de_frame_eof_check().bit()),
-            )
-            .field(
-                "de_dma2d_in_push",
-                &format_args!("{}", self.de_dma2d_in_push().bit()),
-            )
+            .field("block_eof_cnt", &self.block_eof_cnt())
+            .field("dezigzag_ready", &self.dezigzag_ready())
+            .field("de_frame_eof_check", &self.de_frame_eof_check())
+            .field("de_dma2d_in_push", &self.de_dma2d_in_push())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DECODER_STATUS4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`decoder_status4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DECODER_STATUS4_SPEC;
 impl crate::RegisterSpec for DECODER_STATUS4_SPEC {
diff --git a/esp32p4/src/jpeg/decoder_status5.rs b/esp32p4/src/jpeg/decoder_status5.rs
index d947cb3664..33b7de561c 100644
--- a/esp32p4/src/jpeg/decoder_status5.rs
+++ b/esp32p4/src/jpeg/decoder_status5.rs
@@ -66,26 +66,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DECODER_STATUS5")
-            .field(
-                "idct_hfm_data",
-                &format_args!("{}", self.idct_hfm_data().bits()),
-            )
-            .field("ns0", &format_args!("{}", self.ns0().bits()))
-            .field("ns1", &format_args!("{}", self.ns1().bits()))
-            .field("ns2", &format_args!("{}", self.ns2().bits()))
-            .field("ns3", &format_args!("{}", self.ns3().bits()))
-            .field("data_last_o", &format_args!("{}", self.data_last_o().bit()))
-            .field("rdn_result", &format_args!("{}", self.rdn_result().bit()))
-            .field("rdn_ena", &format_args!("{}", self.rdn_ena().bit()))
+            .field("idct_hfm_data", &self.idct_hfm_data())
+            .field("ns0", &self.ns0())
+            .field("ns1", &self.ns1())
+            .field("ns2", &self.ns2())
+            .field("ns3", &self.ns3())
+            .field("data_last_o", &self.data_last_o())
+            .field("rdn_result", &self.rdn_result())
+            .field("rdn_ena", &self.rdn_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DECODER_STATUS5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - redundant control registers for jpeg"]
     #[inline(always)]
diff --git a/esp32p4/src/jpeg/dht_codemin_ac0.rs b/esp32p4/src/jpeg/dht_codemin_ac0.rs
index 8e5a12c187..8d79211cc1 100644
--- a/esp32p4/src/jpeg/dht_codemin_ac0.rs
+++ b/esp32p4/src/jpeg/dht_codemin_ac0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DHT_CODEMIN_AC0")
-            .field(
-                "dht_codemin_ac0",
-                &format_args!("{}", self.dht_codemin_ac0().bits()),
-            )
+            .field("dht_codemin_ac0", &self.dht_codemin_ac0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DHT_CODEMIN_AC0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_codemin_ac0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DHT_CODEMIN_AC0_SPEC;
 impl crate::RegisterSpec for DHT_CODEMIN_AC0_SPEC {
diff --git a/esp32p4/src/jpeg/dht_codemin_ac1.rs b/esp32p4/src/jpeg/dht_codemin_ac1.rs
index 6cc5bd5b45..bc6730adaf 100644
--- a/esp32p4/src/jpeg/dht_codemin_ac1.rs
+++ b/esp32p4/src/jpeg/dht_codemin_ac1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DHT_CODEMIN_AC1")
-            .field(
-                "dht_codemin_ac1",
-                &format_args!("{}", self.dht_codemin_ac1().bits()),
-            )
+            .field("dht_codemin_ac1", &self.dht_codemin_ac1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DHT_CODEMIN_AC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_codemin_ac1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DHT_CODEMIN_AC1_SPEC;
 impl crate::RegisterSpec for DHT_CODEMIN_AC1_SPEC {
diff --git a/esp32p4/src/jpeg/dht_codemin_dc0.rs b/esp32p4/src/jpeg/dht_codemin_dc0.rs
index 08ca9ce426..4b1feb7ea0 100644
--- a/esp32p4/src/jpeg/dht_codemin_dc0.rs
+++ b/esp32p4/src/jpeg/dht_codemin_dc0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DHT_CODEMIN_DC0")
-            .field(
-                "dht_codemin_dc0",
-                &format_args!("{}", self.dht_codemin_dc0().bits()),
-            )
+            .field("dht_codemin_dc0", &self.dht_codemin_dc0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DHT_CODEMIN_DC0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_codemin_dc0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DHT_CODEMIN_DC0_SPEC;
 impl crate::RegisterSpec for DHT_CODEMIN_DC0_SPEC {
diff --git a/esp32p4/src/jpeg/dht_codemin_dc1.rs b/esp32p4/src/jpeg/dht_codemin_dc1.rs
index 85deb70707..aabbf8f665 100644
--- a/esp32p4/src/jpeg/dht_codemin_dc1.rs
+++ b/esp32p4/src/jpeg/dht_codemin_dc1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DHT_CODEMIN_DC1")
-            .field(
-                "dht_codemin_dc1",
-                &format_args!("{}", self.dht_codemin_dc1().bits()),
-            )
+            .field("dht_codemin_dc1", &self.dht_codemin_dc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DHT_CODEMIN_DC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_codemin_dc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DHT_CODEMIN_DC1_SPEC;
 impl crate::RegisterSpec for DHT_CODEMIN_DC1_SPEC {
diff --git a/esp32p4/src/jpeg/dht_info.rs b/esp32p4/src/jpeg/dht_info.rs
index cc8ce7f0d7..05e23c612e 100644
--- a/esp32p4/src/jpeg/dht_info.rs
+++ b/esp32p4/src/jpeg/dht_info.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DHT_INFO")
-            .field("dc0_dht_id", &format_args!("{}", self.dc0_dht_id().bits()))
-            .field("dc1_dht_id", &format_args!("{}", self.dc1_dht_id().bits()))
-            .field("ac0_dht_id", &format_args!("{}", self.ac0_dht_id().bits()))
-            .field("ac1_dht_id", &format_args!("{}", self.ac1_dht_id().bits()))
+            .field("dc0_dht_id", &self.dc0_dht_id())
+            .field("dc1_dht_id", &self.dc1_dht_id())
+            .field("ac0_dht_id", &self.ac0_dht_id())
+            .field("ac1_dht_id", &self.ac1_dht_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DHT_INFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - configure dht dc table 0 id"]
     #[inline(always)]
diff --git a/esp32p4/src/jpeg/dht_totlen_ac0.rs b/esp32p4/src/jpeg/dht_totlen_ac0.rs
index a255f5b78b..484dd6dbb3 100644
--- a/esp32p4/src/jpeg/dht_totlen_ac0.rs
+++ b/esp32p4/src/jpeg/dht_totlen_ac0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DHT_TOTLEN_AC0")
-            .field(
-                "dht_totlen_ac0",
-                &format_args!("{}", self.dht_totlen_ac0().bits()),
-            )
+            .field("dht_totlen_ac0", &self.dht_totlen_ac0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DHT_TOTLEN_AC0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_totlen_ac0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DHT_TOTLEN_AC0_SPEC;
 impl crate::RegisterSpec for DHT_TOTLEN_AC0_SPEC {
diff --git a/esp32p4/src/jpeg/dht_totlen_ac1.rs b/esp32p4/src/jpeg/dht_totlen_ac1.rs
index 98a0b1042d..4c40f9d23a 100644
--- a/esp32p4/src/jpeg/dht_totlen_ac1.rs
+++ b/esp32p4/src/jpeg/dht_totlen_ac1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DHT_TOTLEN_AC1")
-            .field(
-                "dht_totlen_ac1",
-                &format_args!("{}", self.dht_totlen_ac1().bits()),
-            )
+            .field("dht_totlen_ac1", &self.dht_totlen_ac1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DHT_TOTLEN_AC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_totlen_ac1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DHT_TOTLEN_AC1_SPEC;
 impl crate::RegisterSpec for DHT_TOTLEN_AC1_SPEC {
diff --git a/esp32p4/src/jpeg/dht_totlen_dc0.rs b/esp32p4/src/jpeg/dht_totlen_dc0.rs
index 168dc3a9f7..0354d49438 100644
--- a/esp32p4/src/jpeg/dht_totlen_dc0.rs
+++ b/esp32p4/src/jpeg/dht_totlen_dc0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DHT_TOTLEN_DC0")
-            .field(
-                "dht_totlen_dc0",
-                &format_args!("{}", self.dht_totlen_dc0().bits()),
-            )
+            .field("dht_totlen_dc0", &self.dht_totlen_dc0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DHT_TOTLEN_DC0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_totlen_dc0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DHT_TOTLEN_DC0_SPEC;
 impl crate::RegisterSpec for DHT_TOTLEN_DC0_SPEC {
diff --git a/esp32p4/src/jpeg/dht_totlen_dc1.rs b/esp32p4/src/jpeg/dht_totlen_dc1.rs
index 01529ca76f..744dd9363b 100644
--- a/esp32p4/src/jpeg/dht_totlen_dc1.rs
+++ b/esp32p4/src/jpeg/dht_totlen_dc1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DHT_TOTLEN_DC1")
-            .field(
-                "dht_totlen_dc1",
-                &format_args!("{}", self.dht_totlen_dc1().bits()),
-            )
+            .field("dht_totlen_dc1", &self.dht_totlen_dc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DHT_TOTLEN_DC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_totlen_dc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DHT_TOTLEN_DC1_SPEC;
 impl crate::RegisterSpec for DHT_TOTLEN_DC1_SPEC {
diff --git a/esp32p4/src/jpeg/dht_val_ac0.rs b/esp32p4/src/jpeg/dht_val_ac0.rs
index 612b751dd8..c53dfd39db 100644
--- a/esp32p4/src/jpeg/dht_val_ac0.rs
+++ b/esp32p4/src/jpeg/dht_val_ac0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DHT_VAl_AC0")
-            .field(
-                "dht_val_ac0",
-                &format_args!("{}", self.dht_val_ac0().bits()),
-            )
+            .field("dht_val_ac0", &self.dht_val_ac0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DHT_VAL_AC0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_val_ac0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DHT_VAL_AC0_SPEC;
 impl crate::RegisterSpec for DHT_VAL_AC0_SPEC {
diff --git a/esp32p4/src/jpeg/dht_val_ac1.rs b/esp32p4/src/jpeg/dht_val_ac1.rs
index 1f6eec7ea9..31392dbd83 100644
--- a/esp32p4/src/jpeg/dht_val_ac1.rs
+++ b/esp32p4/src/jpeg/dht_val_ac1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DHT_VAl_AC1")
-            .field(
-                "dht_val_ac1",
-                &format_args!("{}", self.dht_val_ac1().bits()),
-            )
+            .field("dht_val_ac1", &self.dht_val_ac1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DHT_VAL_AC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_val_ac1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DHT_VAL_AC1_SPEC;
 impl crate::RegisterSpec for DHT_VAL_AC1_SPEC {
diff --git a/esp32p4/src/jpeg/dht_val_dc0.rs b/esp32p4/src/jpeg/dht_val_dc0.rs
index 28bac17ef9..1515fc8ef7 100644
--- a/esp32p4/src/jpeg/dht_val_dc0.rs
+++ b/esp32p4/src/jpeg/dht_val_dc0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DHT_VAl_DC0")
-            .field(
-                "dht_val_dc0",
-                &format_args!("{}", self.dht_val_dc0().bits()),
-            )
+            .field("dht_val_dc0", &self.dht_val_dc0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DHT_VAL_DC0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_val_dc0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DHT_VAL_DC0_SPEC;
 impl crate::RegisterSpec for DHT_VAL_DC0_SPEC {
diff --git a/esp32p4/src/jpeg/dht_val_dc1.rs b/esp32p4/src/jpeg/dht_val_dc1.rs
index 29bf00f86c..b57153bf7e 100644
--- a/esp32p4/src/jpeg/dht_val_dc1.rs
+++ b/esp32p4/src/jpeg/dht_val_dc1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DHT_VAl_DC1")
-            .field(
-                "dht_val_dc1",
-                &format_args!("{}", self.dht_val_dc1().bits()),
-            )
+            .field("dht_val_dc1", &self.dht_val_dc1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DHT_VAL_DC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dht_val_dc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DHT_VAL_DC1_SPEC;
 impl crate::RegisterSpec for DHT_VAL_DC1_SPEC {
diff --git a/esp32p4/src/jpeg/dqt_info.rs b/esp32p4/src/jpeg/dqt_info.rs
index 64182574f7..f1b536b2f7 100644
--- a/esp32p4/src/jpeg/dqt_info.rs
+++ b/esp32p4/src/jpeg/dqt_info.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DQT_INFO")
-            .field(
-                "t0_dqt_info",
-                &format_args!("{}", self.t0_dqt_info().bits()),
-            )
-            .field(
-                "t1_dqt_info",
-                &format_args!("{}", self.t1_dqt_info().bits()),
-            )
-            .field(
-                "t2_dqt_info",
-                &format_args!("{}", self.t2_dqt_info().bits()),
-            )
-            .field(
-                "t3_dqt_info",
-                &format_args!("{}", self.t3_dqt_info().bits()),
-            )
+            .field("t0_dqt_info", &self.t0_dqt_info())
+            .field("t1_dqt_info", &self.t1_dqt_info())
+            .field("t2_dqt_info", &self.t2_dqt_info())
+            .field("t3_dqt_info", &self.t3_dqt_info())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DQT_INFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configure dqt table0's quantization coefficient precision in bit\\[7:4\\], configure dqt table0's table id in bit\\[3:0\\]"]
     #[inline(always)]
diff --git a/esp32p4/src/jpeg/eco_high.rs b/esp32p4/src/jpeg/eco_high.rs
index 34f03852f1..53022f1ff3 100644
--- a/esp32p4/src/jpeg/eco_high.rs
+++ b/esp32p4/src/jpeg/eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_HIGH")
-            .field(
-                "rdn_eco_high",
-                &format_args!("{}", self.rdn_eco_high().bits()),
-            )
+            .field("rdn_eco_high", &self.rdn_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - redundant registers for jpeg"]
     #[inline(always)]
diff --git a/esp32p4/src/jpeg/eco_low.rs b/esp32p4/src/jpeg/eco_low.rs
index e0a59c763f..cd3ea8c164 100644
--- a/esp32p4/src/jpeg/eco_low.rs
+++ b/esp32p4/src/jpeg/eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_LOW")
-            .field(
-                "rdn_eco_low",
-                &format_args!("{}", self.rdn_eco_low().bits()),
-            )
+            .field("rdn_eco_low", &self.rdn_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - redundant registers for jpeg"]
     #[inline(always)]
diff --git a/esp32p4/src/jpeg/int_ena.rs b/esp32p4/src/jpeg/int_ena.rs
index 6da6f4a8c7..00a9c448de 100644
--- a/esp32p4/src/jpeg/int_ena.rs
+++ b/esp32p4/src/jpeg/int_ena.rs
@@ -233,94 +233,34 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field(
-                "rle_parallel_err",
-                &format_args!("{}", self.rle_parallel_err().bit()),
-            )
-            .field("cid_err", &format_args!("{}", self.cid_err().bit()))
-            .field(
-                "c_dht_dc_id_err",
-                &format_args!("{}", self.c_dht_dc_id_err().bit()),
-            )
-            .field(
-                "c_dht_ac_id_err",
-                &format_args!("{}", self.c_dht_ac_id_err().bit()),
-            )
-            .field(
-                "c_dqt_id_err",
-                &format_args!("{}", self.c_dqt_id_err().bit()),
-            )
-            .field("rst_uxp_err", &format_args!("{}", self.rst_uxp_err().bit()))
-            .field(
-                "rst_check_none_err",
-                &format_args!("{}", self.rst_check_none_err().bit()),
-            )
-            .field(
-                "rst_check_pos_err",
-                &format_args!("{}", self.rst_check_pos_err().bit()),
-            )
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "sr_color_mode_err",
-                &format_args!("{}", self.sr_color_mode_err().bit()),
-            )
-            .field("dct_done", &format_args!("{}", self.dct_done().bit()))
-            .field(
-                "bs_last_block_eof",
-                &format_args!("{}", self.bs_last_block_eof().bit()),
-            )
-            .field(
-                "scan_check_none_err",
-                &format_args!("{}", self.scan_check_none_err().bit()),
-            )
-            .field(
-                "scan_check_pos_err",
-                &format_args!("{}", self.scan_check_pos_err().bit()),
-            )
-            .field("uxp_det", &format_args!("{}", self.uxp_det().bit()))
-            .field(
-                "en_frame_eof_err",
-                &format_args!("{}", self.en_frame_eof_err().bit()),
-            )
-            .field(
-                "en_frame_eof_lack",
-                &format_args!("{}", self.en_frame_eof_lack().bit()),
-            )
-            .field(
-                "de_frame_eof_err",
-                &format_args!("{}", self.de_frame_eof_err().bit()),
-            )
-            .field(
-                "de_frame_eof_lack",
-                &format_args!("{}", self.de_frame_eof_lack().bit()),
-            )
-            .field(
-                "sos_unmatch_err",
-                &format_args!("{}", self.sos_unmatch_err().bit()),
-            )
-            .field(
-                "marker_err_fst_scan",
-                &format_args!("{}", self.marker_err_fst_scan().bit()),
-            )
-            .field(
-                "marker_err_other_scan",
-                &format_args!("{}", self.marker_err_other_scan().bit()),
-            )
-            .field("undet", &format_args!("{}", self.undet().bit()))
-            .field(
-                "decode_timeout",
-                &format_args!("{}", self.decode_timeout().bit()),
-            )
+            .field("done", &self.done())
+            .field("rle_parallel_err", &self.rle_parallel_err())
+            .field("cid_err", &self.cid_err())
+            .field("c_dht_dc_id_err", &self.c_dht_dc_id_err())
+            .field("c_dht_ac_id_err", &self.c_dht_ac_id_err())
+            .field("c_dqt_id_err", &self.c_dqt_id_err())
+            .field("rst_uxp_err", &self.rst_uxp_err())
+            .field("rst_check_none_err", &self.rst_check_none_err())
+            .field("rst_check_pos_err", &self.rst_check_pos_err())
+            .field("out_eof", &self.out_eof())
+            .field("sr_color_mode_err", &self.sr_color_mode_err())
+            .field("dct_done", &self.dct_done())
+            .field("bs_last_block_eof", &self.bs_last_block_eof())
+            .field("scan_check_none_err", &self.scan_check_none_err())
+            .field("scan_check_pos_err", &self.scan_check_pos_err())
+            .field("uxp_det", &self.uxp_det())
+            .field("en_frame_eof_err", &self.en_frame_eof_err())
+            .field("en_frame_eof_lack", &self.en_frame_eof_lack())
+            .field("de_frame_eof_err", &self.de_frame_eof_err())
+            .field("de_frame_eof_lack", &self.de_frame_eof_lack())
+            .field("sos_unmatch_err", &self.sos_unmatch_err())
+            .field("marker_err_fst_scan", &self.marker_err_fst_scan())
+            .field("marker_err_other_scan", &self.marker_err_other_scan())
+            .field("undet", &self.undet())
+            .field("decode_timeout", &self.decode_timeout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This enable interrupt bit turns to high level when JPEG finishes encoding a picture.."]
     #[inline(always)]
diff --git a/esp32p4/src/jpeg/int_raw.rs b/esp32p4/src/jpeg/int_raw.rs
index f235a30134..fb54e43462 100644
--- a/esp32p4/src/jpeg/int_raw.rs
+++ b/esp32p4/src/jpeg/int_raw.rs
@@ -233,94 +233,34 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field(
-                "rle_parallel_err",
-                &format_args!("{}", self.rle_parallel_err().bit()),
-            )
-            .field("cid_err", &format_args!("{}", self.cid_err().bit()))
-            .field(
-                "c_dht_dc_id_err",
-                &format_args!("{}", self.c_dht_dc_id_err().bit()),
-            )
-            .field(
-                "c_dht_ac_id_err",
-                &format_args!("{}", self.c_dht_ac_id_err().bit()),
-            )
-            .field(
-                "c_dqt_id_err",
-                &format_args!("{}", self.c_dqt_id_err().bit()),
-            )
-            .field("rst_uxp_err", &format_args!("{}", self.rst_uxp_err().bit()))
-            .field(
-                "rst_check_none_err",
-                &format_args!("{}", self.rst_check_none_err().bit()),
-            )
-            .field(
-                "rst_check_pos_err",
-                &format_args!("{}", self.rst_check_pos_err().bit()),
-            )
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "sr_color_mode_err",
-                &format_args!("{}", self.sr_color_mode_err().bit()),
-            )
-            .field("dct_done", &format_args!("{}", self.dct_done().bit()))
-            .field(
-                "bs_last_block_eof",
-                &format_args!("{}", self.bs_last_block_eof().bit()),
-            )
-            .field(
-                "scan_check_none_err",
-                &format_args!("{}", self.scan_check_none_err().bit()),
-            )
-            .field(
-                "scan_check_pos_err",
-                &format_args!("{}", self.scan_check_pos_err().bit()),
-            )
-            .field("uxp_det", &format_args!("{}", self.uxp_det().bit()))
-            .field(
-                "en_frame_eof_err",
-                &format_args!("{}", self.en_frame_eof_err().bit()),
-            )
-            .field(
-                "en_frame_eof_lack",
-                &format_args!("{}", self.en_frame_eof_lack().bit()),
-            )
-            .field(
-                "de_frame_eof_err",
-                &format_args!("{}", self.de_frame_eof_err().bit()),
-            )
-            .field(
-                "de_frame_eof_lack",
-                &format_args!("{}", self.de_frame_eof_lack().bit()),
-            )
-            .field(
-                "sos_unmatch_err",
-                &format_args!("{}", self.sos_unmatch_err().bit()),
-            )
-            .field(
-                "marker_err_fst_scan",
-                &format_args!("{}", self.marker_err_fst_scan().bit()),
-            )
-            .field(
-                "marker_err_other_scan",
-                &format_args!("{}", self.marker_err_other_scan().bit()),
-            )
-            .field("undet", &format_args!("{}", self.undet().bit()))
-            .field(
-                "decode_timeout",
-                &format_args!("{}", self.decode_timeout().bit()),
-            )
+            .field("done", &self.done())
+            .field("rle_parallel_err", &self.rle_parallel_err())
+            .field("cid_err", &self.cid_err())
+            .field("c_dht_dc_id_err", &self.c_dht_dc_id_err())
+            .field("c_dht_ac_id_err", &self.c_dht_ac_id_err())
+            .field("c_dqt_id_err", &self.c_dqt_id_err())
+            .field("rst_uxp_err", &self.rst_uxp_err())
+            .field("rst_check_none_err", &self.rst_check_none_err())
+            .field("rst_check_pos_err", &self.rst_check_pos_err())
+            .field("out_eof", &self.out_eof())
+            .field("sr_color_mode_err", &self.sr_color_mode_err())
+            .field("dct_done", &self.dct_done())
+            .field("bs_last_block_eof", &self.bs_last_block_eof())
+            .field("scan_check_none_err", &self.scan_check_none_err())
+            .field("scan_check_pos_err", &self.scan_check_pos_err())
+            .field("uxp_det", &self.uxp_det())
+            .field("en_frame_eof_err", &self.en_frame_eof_err())
+            .field("en_frame_eof_lack", &self.en_frame_eof_lack())
+            .field("de_frame_eof_err", &self.de_frame_eof_err())
+            .field("de_frame_eof_lack", &self.de_frame_eof_lack())
+            .field("sos_unmatch_err", &self.sos_unmatch_err())
+            .field("marker_err_fst_scan", &self.marker_err_fst_scan())
+            .field("marker_err_other_scan", &self.marker_err_other_scan())
+            .field("undet", &self.undet())
+            .field("decode_timeout", &self.decode_timeout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This raw interrupt bit turns to high level when JPEG finishes encoding a picture.."]
     #[inline(always)]
diff --git a/esp32p4/src/jpeg/int_st.rs b/esp32p4/src/jpeg/int_st.rs
index 0f96079a1f..c3fc153ea2 100644
--- a/esp32p4/src/jpeg/int_st.rs
+++ b/esp32p4/src/jpeg/int_st.rs
@@ -181,94 +181,34 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field(
-                "rle_parallel_err",
-                &format_args!("{}", self.rle_parallel_err().bit()),
-            )
-            .field("cid_err", &format_args!("{}", self.cid_err().bit()))
-            .field(
-                "c_dht_dc_id_err",
-                &format_args!("{}", self.c_dht_dc_id_err().bit()),
-            )
-            .field(
-                "c_dht_ac_id_err",
-                &format_args!("{}", self.c_dht_ac_id_err().bit()),
-            )
-            .field(
-                "c_dqt_id_err",
-                &format_args!("{}", self.c_dqt_id_err().bit()),
-            )
-            .field("rst_uxp_err", &format_args!("{}", self.rst_uxp_err().bit()))
-            .field(
-                "rst_check_none_err",
-                &format_args!("{}", self.rst_check_none_err().bit()),
-            )
-            .field(
-                "rst_check_pos_err",
-                &format_args!("{}", self.rst_check_pos_err().bit()),
-            )
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "sr_color_mode_err",
-                &format_args!("{}", self.sr_color_mode_err().bit()),
-            )
-            .field("dct_done", &format_args!("{}", self.dct_done().bit()))
-            .field(
-                "bs_last_block_eof",
-                &format_args!("{}", self.bs_last_block_eof().bit()),
-            )
-            .field(
-                "scan_check_none_err",
-                &format_args!("{}", self.scan_check_none_err().bit()),
-            )
-            .field(
-                "scan_check_pos_err",
-                &format_args!("{}", self.scan_check_pos_err().bit()),
-            )
-            .field("uxp_det", &format_args!("{}", self.uxp_det().bit()))
-            .field(
-                "en_frame_eof_err",
-                &format_args!("{}", self.en_frame_eof_err().bit()),
-            )
-            .field(
-                "en_frame_eof_lack",
-                &format_args!("{}", self.en_frame_eof_lack().bit()),
-            )
-            .field(
-                "de_frame_eof_err",
-                &format_args!("{}", self.de_frame_eof_err().bit()),
-            )
-            .field(
-                "de_frame_eof_lack",
-                &format_args!("{}", self.de_frame_eof_lack().bit()),
-            )
-            .field(
-                "sos_unmatch_err",
-                &format_args!("{}", self.sos_unmatch_err().bit()),
-            )
-            .field(
-                "marker_err_fst_scan",
-                &format_args!("{}", self.marker_err_fst_scan().bit()),
-            )
-            .field(
-                "marker_err_other_scan",
-                &format_args!("{}", self.marker_err_other_scan().bit()),
-            )
-            .field("undet", &format_args!("{}", self.undet().bit()))
-            .field(
-                "decode_timeout",
-                &format_args!("{}", self.decode_timeout().bit()),
-            )
+            .field("done", &self.done())
+            .field("rle_parallel_err", &self.rle_parallel_err())
+            .field("cid_err", &self.cid_err())
+            .field("c_dht_dc_id_err", &self.c_dht_dc_id_err())
+            .field("c_dht_ac_id_err", &self.c_dht_ac_id_err())
+            .field("c_dqt_id_err", &self.c_dqt_id_err())
+            .field("rst_uxp_err", &self.rst_uxp_err())
+            .field("rst_check_none_err", &self.rst_check_none_err())
+            .field("rst_check_pos_err", &self.rst_check_pos_err())
+            .field("out_eof", &self.out_eof())
+            .field("sr_color_mode_err", &self.sr_color_mode_err())
+            .field("dct_done", &self.dct_done())
+            .field("bs_last_block_eof", &self.bs_last_block_eof())
+            .field("scan_check_none_err", &self.scan_check_none_err())
+            .field("scan_check_pos_err", &self.scan_check_pos_err())
+            .field("uxp_det", &self.uxp_det())
+            .field("en_frame_eof_err", &self.en_frame_eof_err())
+            .field("en_frame_eof_lack", &self.en_frame_eof_lack())
+            .field("de_frame_eof_err", &self.de_frame_eof_err())
+            .field("de_frame_eof_lack", &self.de_frame_eof_lack())
+            .field("sos_unmatch_err", &self.sos_unmatch_err())
+            .field("marker_err_fst_scan", &self.marker_err_fst_scan())
+            .field("marker_err_other_scan", &self.marker_err_other_scan())
+            .field("undet", &self.undet())
+            .field("decode_timeout", &self.decode_timeout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/jpeg/pic_size.rs b/esp32p4/src/jpeg/pic_size.rs
index 1839a729e0..e36ee2591d 100644
--- a/esp32p4/src/jpeg/pic_size.rs
+++ b/esp32p4/src/jpeg/pic_size.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIC_SIZE")
-            .field("va", &format_args!("{}", self.va().bits()))
-            .field("ha", &format_args!("{}", self.ha().bits()))
+            .field("va", &self.va())
+            .field("ha", &self.ha())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIC_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - configure picture's height. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16"]
     #[inline(always)]
diff --git a/esp32p4/src/jpeg/status0.rs b/esp32p4/src/jpeg/status0.rs
index b7d95575c2..508ba8e130 100644
--- a/esp32p4/src/jpeg/status0.rs
+++ b/esp32p4/src/jpeg/status0.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS0")
-            .field(
-                "bitstream_eof_vld_cnt",
-                &format_args!("{}", self.bitstream_eof_vld_cnt().bits()),
-            )
-            .field(
-                "dctout_zzscan_addr",
-                &format_args!("{}", self.dctout_zzscan_addr().bits()),
-            )
-            .field(
-                "qnrval_zzscan_addr",
-                &format_args!("{}", self.qnrval_zzscan_addr().bits()),
-            )
-            .field(
-                "reg_state_yuv",
-                &format_args!("{}", self.reg_state_yuv().bits()),
-            )
+            .field("bitstream_eof_vld_cnt", &self.bitstream_eof_vld_cnt())
+            .field("dctout_zzscan_addr", &self.dctout_zzscan_addr())
+            .field("qnrval_zzscan_addr", &self.qnrval_zzscan_addr())
+            .field("reg_state_yuv", &self.reg_state_yuv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS0_SPEC;
 impl crate::RegisterSpec for STATUS0_SPEC {
diff --git a/esp32p4/src/jpeg/status2.rs b/esp32p4/src/jpeg/status2.rs
index d1193b46a9..32181107fc 100644
--- a/esp32p4/src/jpeg/status2.rs
+++ b/esp32p4/src/jpeg/status2.rs
@@ -41,26 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS2")
-            .field(
-                "source_pixel",
-                &format_args!("{}", self.source_pixel().bits()),
-            )
-            .field("last_block", &format_args!("{}", self.last_block().bit()))
-            .field("last_mcu", &format_args!("{}", self.last_mcu().bit()))
-            .field("last_dc", &format_args!("{}", self.last_dc().bit()))
-            .field(
-                "packfifo_ready",
-                &format_args!("{}", self.packfifo_ready().bit()),
-            )
+            .field("source_pixel", &self.source_pixel())
+            .field("last_block", &self.last_block())
+            .field("last_mcu", &self.last_mcu())
+            .field("last_dc", &self.last_dc())
+            .field("packfifo_ready", &self.packfifo_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS2_SPEC;
 impl crate::RegisterSpec for STATUS2_SPEC {
diff --git a/esp32p4/src/jpeg/status3.rs b/esp32p4/src/jpeg/status3.rs
index 525d7eb1b8..8158c3ad08 100644
--- a/esp32p4/src/jpeg/status3.rs
+++ b/esp32p4/src/jpeg/status3.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS3")
-            .field("yo", &format_args!("{}", self.yo().bits()))
-            .field("y_ready", &format_args!("{}", self.y_ready().bit()))
-            .field("cbo", &format_args!("{}", self.cbo().bits()))
-            .field("cb_ready", &format_args!("{}", self.cb_ready().bit()))
-            .field("cro", &format_args!("{}", self.cro().bits()))
-            .field("cr_ready", &format_args!("{}", self.cr_ready().bit()))
+            .field("yo", &self.yo())
+            .field("y_ready", &self.y_ready())
+            .field("cbo", &self.cbo())
+            .field("cb_ready", &self.cb_ready())
+            .field("cro", &self.cro())
+            .field("cr_ready", &self.cr_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS3_SPEC;
 impl crate::RegisterSpec for STATUS3_SPEC {
diff --git a/esp32p4/src/jpeg/status4.rs b/esp32p4/src/jpeg/status4.rs
index 9e8d3c6e65..c181a2eb93 100644
--- a/esp32p4/src/jpeg/status4.rs
+++ b/esp32p4/src/jpeg/status4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS4")
-            .field(
-                "hfm_bitstream",
-                &format_args!("{}", self.hfm_bitstream().bits()),
-            )
+            .field("hfm_bitstream", &self.hfm_bitstream())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS4_SPEC;
 impl crate::RegisterSpec for STATUS4_SPEC {
diff --git a/esp32p4/src/jpeg/status5.rs b/esp32p4/src/jpeg/status5.rs
index 4afa5534a9..b43ee42b4d 100644
--- a/esp32p4/src/jpeg/status5.rs
+++ b/esp32p4/src/jpeg/status5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS5")
-            .field(
-                "pic_block_num",
-                &format_args!("{}", self.pic_block_num().bits()),
-            )
+            .field("pic_block_num", &self.pic_block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Trace and Debug registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS5_SPEC;
 impl crate::RegisterSpec for STATUS5_SPEC {
diff --git a/esp32p4/src/jpeg/sys.rs b/esp32p4/src/jpeg/sys.rs
index ace80b431b..55dd34cb19 100644
--- a/esp32p4/src/jpeg/sys.rs
+++ b/esp32p4/src/jpeg/sys.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYS")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/jpeg/t0qnr.rs b/esp32p4/src/jpeg/t0qnr.rs
index 14d7a27853..3499849a0b 100644
--- a/esp32p4/src/jpeg/t0qnr.rs
+++ b/esp32p4/src/jpeg/t0qnr.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T0QNR")
-            .field("t0_qnr_val", &format_args!("{}", self.t0_qnr_val().bits()))
+            .field("t0_qnr_val", &self.t0_qnr_val())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T0QNR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0qnr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct T0QNR_SPEC;
 impl crate::RegisterSpec for T0QNR_SPEC {
diff --git a/esp32p4/src/jpeg/t1qnr.rs b/esp32p4/src/jpeg/t1qnr.rs
index 84012c9609..9c2edd548d 100644
--- a/esp32p4/src/jpeg/t1qnr.rs
+++ b/esp32p4/src/jpeg/t1qnr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T1QNR")
-            .field(
-                "chrominance_qnr_val",
-                &format_args!("{}", self.chrominance_qnr_val().bits()),
-            )
+            .field("chrominance_qnr_val", &self.chrominance_qnr_val())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T1QNR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t1qnr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct T1QNR_SPEC;
 impl crate::RegisterSpec for T1QNR_SPEC {
diff --git a/esp32p4/src/jpeg/t2qnr.rs b/esp32p4/src/jpeg/t2qnr.rs
index 0f9a9ec3e9..a89e52fdf6 100644
--- a/esp32p4/src/jpeg/t2qnr.rs
+++ b/esp32p4/src/jpeg/t2qnr.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T2QNR")
-            .field("t2_qnr_val", &format_args!("{}", self.t2_qnr_val().bits()))
+            .field("t2_qnr_val", &self.t2_qnr_val())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T2QNR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t2qnr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct T2QNR_SPEC;
 impl crate::RegisterSpec for T2QNR_SPEC {
diff --git a/esp32p4/src/jpeg/t3qnr.rs b/esp32p4/src/jpeg/t3qnr.rs
index 3dd44caa3d..47e9004c80 100644
--- a/esp32p4/src/jpeg/t3qnr.rs
+++ b/esp32p4/src/jpeg/t3qnr.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T3QNR")
-            .field("t3_qnr_val", &format_args!("{}", self.t3_qnr_val().bits()))
+            .field("t3_qnr_val", &self.t3_qnr_val())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T3QNR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Control and configuration registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t3qnr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct T3QNR_SPEC;
 impl crate::RegisterSpec for T3QNR_SPEC {
diff --git a/esp32p4/src/jpeg/version.rs b/esp32p4/src/jpeg/version.rs
index 5350d56e85..41bd8dffeb 100644
--- a/esp32p4/src/jpeg/version.rs
+++ b/esp32p4/src/jpeg/version.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field("jpeg_ver", &format_args!("{}", self.jpeg_ver().bits()))
+            .field("jpeg_ver", &self.jpeg_ver())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lcd_cam/cam_ctrl.rs b/esp32p4/src/lcd_cam/cam_ctrl.rs
index 0ff8d98c7b..a7b329a6d4 100644
--- a/esp32p4/src/lcd_cam/cam_ctrl.rs
+++ b/esp32p4/src/lcd_cam/cam_ctrl.rs
@@ -107,53 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAM_CTRL")
-            .field("cam_stop_en", &format_args!("{}", self.cam_stop_en().bit()))
-            .field(
-                "cam_vsync_filter_thres",
-                &format_args!("{}", self.cam_vsync_filter_thres().bits()),
-            )
-            .field("cam_update", &format_args!("{}", self.cam_update().bit()))
-            .field(
-                "cam_byte_order",
-                &format_args!("{}", self.cam_byte_order().bit()),
-            )
-            .field(
-                "cam_bit_order",
-                &format_args!("{}", self.cam_bit_order().bit()),
-            )
-            .field(
-                "cam_line_int_en",
-                &format_args!("{}", self.cam_line_int_en().bit()),
-            )
-            .field(
-                "cam_vs_eof_en",
-                &format_args!("{}", self.cam_vs_eof_en().bit()),
-            )
-            .field(
-                "cam_clkm_div_num",
-                &format_args!("{}", self.cam_clkm_div_num().bits()),
-            )
-            .field(
-                "cam_clkm_div_b",
-                &format_args!("{}", self.cam_clkm_div_b().bits()),
-            )
-            .field(
-                "cam_clkm_div_a",
-                &format_args!("{}", self.cam_clkm_div_a().bits()),
-            )
-            .field(
-                "cam_clk_sel",
-                &format_args!("{}", self.cam_clk_sel().bits()),
-            )
+            .field("cam_stop_en", &self.cam_stop_en())
+            .field("cam_vsync_filter_thres", &self.cam_vsync_filter_thres())
+            .field("cam_update", &self.cam_update())
+            .field("cam_byte_order", &self.cam_byte_order())
+            .field("cam_bit_order", &self.cam_bit_order())
+            .field("cam_line_int_en", &self.cam_line_int_en())
+            .field("cam_vs_eof_en", &self.cam_vs_eof_en())
+            .field("cam_clkm_div_num", &self.cam_clkm_div_num())
+            .field("cam_clkm_div_b", &self.cam_clkm_div_b())
+            .field("cam_clkm_div_a", &self.cam_clkm_div_a())
+            .field("cam_clk_sel", &self.cam_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop."]
     #[inline(always)]
diff --git a/esp32p4/src/lcd_cam/cam_ctrl1.rs b/esp32p4/src/lcd_cam/cam_ctrl1.rs
index c55a678eb2..c4b1c75458 100644
--- a/esp32p4/src/lcd_cam/cam_ctrl1.rs
+++ b/esp32p4/src/lcd_cam/cam_ctrl1.rs
@@ -102,46 +102,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAM_CTRL1")
-            .field(
-                "cam_rec_data_bytelen",
-                &format_args!("{}", self.cam_rec_data_bytelen().bits()),
-            )
-            .field(
-                "cam_line_int_num",
-                &format_args!("{}", self.cam_line_int_num().bits()),
-            )
-            .field("cam_clk_inv", &format_args!("{}", self.cam_clk_inv().bit()))
-            .field(
-                "cam_vsync_filter_en",
-                &format_args!("{}", self.cam_vsync_filter_en().bit()),
-            )
-            .field(
-                "cam_2byte_en",
-                &format_args!("{}", self.cam_2byte_en().bit()),
-            )
-            .field("cam_de_inv", &format_args!("{}", self.cam_de_inv().bit()))
-            .field(
-                "cam_hsync_inv",
-                &format_args!("{}", self.cam_hsync_inv().bit()),
-            )
-            .field(
-                "cam_vsync_inv",
-                &format_args!("{}", self.cam_vsync_inv().bit()),
-            )
-            .field(
-                "cam_vh_de_mode_en",
-                &format_args!("{}", self.cam_vh_de_mode_en().bit()),
-            )
-            .field("cam_start", &format_args!("{}", self.cam_start().bit()))
+            .field("cam_rec_data_bytelen", &self.cam_rec_data_bytelen())
+            .field("cam_line_int_num", &self.cam_line_int_num())
+            .field("cam_clk_inv", &self.cam_clk_inv())
+            .field("cam_vsync_filter_en", &self.cam_vsync_filter_en())
+            .field("cam_2byte_en", &self.cam_2byte_en())
+            .field("cam_de_inv", &self.cam_de_inv())
+            .field("cam_hsync_inv", &self.cam_hsync_inv())
+            .field("cam_vsync_inv", &self.cam_vsync_inv())
+            .field("cam_vh_de_mode_en", &self.cam_vh_de_mode_en())
+            .field("cam_start", &self.cam_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAM_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Camera receive data byte length minus 1 to set DMA in_suc_eof_int."]
     #[inline(always)]
diff --git a/esp32p4/src/lcd_cam/cam_rgb_yuv.rs b/esp32p4/src/lcd_cam/cam_rgb_yuv.rs
index 306d7dbc9e..fb80082fb5 100644
--- a/esp32p4/src/lcd_cam/cam_rgb_yuv.rs
+++ b/esp32p4/src/lcd_cam/cam_rgb_yuv.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAM_RGB_YUV")
-            .field(
-                "cam_conv_8bits_data_inv",
-                &format_args!("{}", self.cam_conv_8bits_data_inv().bit()),
-            )
-            .field(
-                "cam_conv_yuv2yuv_mode",
-                &format_args!("{}", self.cam_conv_yuv2yuv_mode().bits()),
-            )
-            .field(
-                "cam_conv_yuv_mode",
-                &format_args!("{}", self.cam_conv_yuv_mode().bits()),
-            )
-            .field(
-                "cam_conv_protocol_mode",
-                &format_args!("{}", self.cam_conv_protocol_mode().bit()),
-            )
-            .field(
-                "cam_conv_data_out_mode",
-                &format_args!("{}", self.cam_conv_data_out_mode().bit()),
-            )
-            .field(
-                "cam_conv_data_in_mode",
-                &format_args!("{}", self.cam_conv_data_in_mode().bit()),
-            )
-            .field(
-                "cam_conv_mode_8bits_on",
-                &format_args!("{}", self.cam_conv_mode_8bits_on().bit()),
-            )
-            .field(
-                "cam_conv_trans_mode",
-                &format_args!("{}", self.cam_conv_trans_mode().bit()),
-            )
-            .field(
-                "cam_conv_enable",
-                &format_args!("{}", self.cam_conv_enable().bit()),
-            )
+            .field("cam_conv_8bits_data_inv", &self.cam_conv_8bits_data_inv())
+            .field("cam_conv_yuv2yuv_mode", &self.cam_conv_yuv2yuv_mode())
+            .field("cam_conv_yuv_mode", &self.cam_conv_yuv_mode())
+            .field("cam_conv_protocol_mode", &self.cam_conv_protocol_mode())
+            .field("cam_conv_data_out_mode", &self.cam_conv_data_out_mode())
+            .field("cam_conv_data_in_mode", &self.cam_conv_data_in_mode())
+            .field("cam_conv_mode_8bits_on", &self.cam_conv_mode_8bits_on())
+            .field("cam_conv_trans_mode", &self.cam_conv_trans_mode())
+            .field("cam_conv_enable", &self.cam_conv_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAM_RGB_YUV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - 1:invert every two 8bits input data. 2. disabled."]
     #[inline(always)]
diff --git a/esp32p4/src/lcd_cam/lc_dma_int_ena.rs b/esp32p4/src/lcd_cam/lc_dma_int_ena.rs
index 0e3dcb7024..8fc0d3b41e 100644
--- a/esp32p4/src/lcd_cam/lc_dma_int_ena.rs
+++ b/esp32p4/src/lcd_cam/lc_dma_int_ena.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_DMA_INT_ENA")
-            .field(
-                "lcd_vsync_int_ena",
-                &format_args!("{}", self.lcd_vsync_int_ena().bit()),
-            )
-            .field(
-                "lcd_trans_done_int_ena",
-                &format_args!("{}", self.lcd_trans_done_int_ena().bit()),
-            )
-            .field(
-                "cam_vsync_int_ena",
-                &format_args!("{}", self.cam_vsync_int_ena().bit()),
-            )
-            .field(
-                "cam_hs_int_ena",
-                &format_args!("{}", self.cam_hs_int_ena().bit()),
-            )
+            .field("lcd_vsync_int_ena", &self.lcd_vsync_int_ena())
+            .field("lcd_trans_done_int_ena", &self.lcd_trans_done_int_ena())
+            .field("cam_vsync_int_ena", &self.cam_vsync_int_ena())
+            .field("cam_hs_int_ena", &self.cam_hs_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_DMA_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for LCD frame end interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/lcd_cam/lc_dma_int_raw.rs b/esp32p4/src/lcd_cam/lc_dma_int_raw.rs
index b0e2027f6b..5f7546d0dc 100644
--- a/esp32p4/src/lcd_cam/lc_dma_int_raw.rs
+++ b/esp32p4/src/lcd_cam/lc_dma_int_raw.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_DMA_INT_RAW")
-            .field(
-                "lcd_vsync_int_raw",
-                &format_args!("{}", self.lcd_vsync_int_raw().bit()),
-            )
-            .field(
-                "lcd_trans_done_int_raw",
-                &format_args!("{}", self.lcd_trans_done_int_raw().bit()),
-            )
-            .field(
-                "cam_vsync_int_raw",
-                &format_args!("{}", self.cam_vsync_int_raw().bit()),
-            )
-            .field(
-                "cam_hs_int_raw",
-                &format_args!("{}", self.cam_hs_int_raw().bit()),
-            )
+            .field("lcd_vsync_int_raw", &self.lcd_vsync_int_raw())
+            .field("lcd_trans_done_int_raw", &self.lcd_trans_done_int_raw())
+            .field("cam_vsync_int_raw", &self.cam_vsync_int_raw())
+            .field("cam_hs_int_raw", &self.cam_hs_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_DMA_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "LCDCAM interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_dma_int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LC_DMA_INT_RAW_SPEC;
 impl crate::RegisterSpec for LC_DMA_INT_RAW_SPEC {
diff --git a/esp32p4/src/lcd_cam/lc_dma_int_st.rs b/esp32p4/src/lcd_cam/lc_dma_int_st.rs
index c12704ccac..5733216643 100644
--- a/esp32p4/src/lcd_cam/lc_dma_int_st.rs
+++ b/esp32p4/src/lcd_cam/lc_dma_int_st.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_DMA_INT_ST")
-            .field(
-                "lcd_vsync_int_st",
-                &format_args!("{}", self.lcd_vsync_int_st().bit()),
-            )
-            .field(
-                "lcd_trans_done_int_st",
-                &format_args!("{}", self.lcd_trans_done_int_st().bit()),
-            )
-            .field(
-                "cam_vsync_int_st",
-                &format_args!("{}", self.cam_vsync_int_st().bit()),
-            )
-            .field(
-                "cam_hs_int_st",
-                &format_args!("{}", self.cam_hs_int_st().bit()),
-            )
+            .field("lcd_vsync_int_st", &self.lcd_vsync_int_st())
+            .field("lcd_trans_done_int_st", &self.lcd_trans_done_int_st())
+            .field("cam_vsync_int_st", &self.cam_vsync_int_st())
+            .field("cam_hs_int_st", &self.cam_hs_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_DMA_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "LCDCAM interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_dma_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LC_DMA_INT_ST_SPEC;
 impl crate::RegisterSpec for LC_DMA_INT_ST_SPEC {
diff --git a/esp32p4/src/lcd_cam/lc_reg_date.rs b/esp32p4/src/lcd_cam/lc_reg_date.rs
index 791f9e8259..77487a3be4 100644
--- a/esp32p4/src/lcd_cam/lc_reg_date.rs
+++ b/esp32p4/src/lcd_cam/lc_reg_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_REG_DATE")
-            .field("lc_date", &format_args!("{}", self.lc_date().bits()))
+            .field("lc_date", &self.lc_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - LCD_CAM version control register"]
     #[inline(always)]
diff --git a/esp32p4/src/lcd_cam/lcd_clock.rs b/esp32p4/src/lcd_cam/lcd_clock.rs
index 271799a990..2e9823e3be 100644
--- a/esp32p4/src/lcd_cam/lcd_clock.rs
+++ b/esp32p4/src/lcd_cam/lcd_clock.rs
@@ -89,48 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CLOCK")
-            .field(
-                "lcd_clkcnt_n",
-                &format_args!("{}", self.lcd_clkcnt_n().bits()),
-            )
-            .field(
-                "lcd_clk_equ_sysclk",
-                &format_args!("{}", self.lcd_clk_equ_sysclk().bit()),
-            )
-            .field(
-                "lcd_ck_idle_edge",
-                &format_args!("{}", self.lcd_ck_idle_edge().bit()),
-            )
-            .field(
-                "lcd_ck_out_edge",
-                &format_args!("{}", self.lcd_ck_out_edge().bit()),
-            )
-            .field(
-                "lcd_clkm_div_num",
-                &format_args!("{}", self.lcd_clkm_div_num().bits()),
-            )
-            .field(
-                "lcd_clkm_div_b",
-                &format_args!("{}", self.lcd_clkm_div_b().bits()),
-            )
-            .field(
-                "lcd_clkm_div_a",
-                &format_args!("{}", self.lcd_clkm_div_a().bits()),
-            )
-            .field(
-                "lcd_clk_sel",
-                &format_args!("{}", self.lcd_clk_sel().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("lcd_clkcnt_n", &self.lcd_clkcnt_n())
+            .field("lcd_clk_equ_sysclk", &self.lcd_clk_equ_sysclk())
+            .field("lcd_ck_idle_edge", &self.lcd_ck_idle_edge())
+            .field("lcd_ck_out_edge", &self.lcd_ck_out_edge())
+            .field("lcd_clkm_div_num", &self.lcd_clkm_div_num())
+            .field("lcd_clkm_div_b", &self.lcd_clkm_div_b())
+            .field("lcd_clkm_div_a", &self.lcd_clkm_div_a())
+            .field("lcd_clk_sel", &self.lcd_clk_sel())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0."]
     #[inline(always)]
diff --git a/esp32p4/src/lcd_cam/lcd_ctrl.rs b/esp32p4/src/lcd_cam/lcd_ctrl.rs
index bc2a16ee88..3f8ee37317 100644
--- a/esp32p4/src/lcd_cam/lcd_ctrl.rs
+++ b/esp32p4/src/lcd_cam/lcd_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CTRL")
-            .field(
-                "lcd_hb_front",
-                &format_args!("{}", self.lcd_hb_front().bits()),
-            )
-            .field(
-                "lcd_va_height",
-                &format_args!("{}", self.lcd_va_height().bits()),
-            )
-            .field(
-                "lcd_vt_height",
-                &format_args!("{}", self.lcd_vt_height().bits()),
-            )
-            .field(
-                "lcd_rgb_mode_en",
-                &format_args!("{}", self.lcd_rgb_mode_en().bit()),
-            )
+            .field("lcd_hb_front", &self.lcd_hb_front())
+            .field("lcd_va_height", &self.lcd_va_height())
+            .field("lcd_vt_height", &self.lcd_vt_height())
+            .field("lcd_rgb_mode_en", &self.lcd_rgb_mode_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - It is the horizontal blank front porch of a frame."]
     #[inline(always)]
diff --git a/esp32p4/src/lcd_cam/lcd_ctrl1.rs b/esp32p4/src/lcd_cam/lcd_ctrl1.rs
index a09a1d95a2..4d68cb1c38 100644
--- a/esp32p4/src/lcd_cam/lcd_ctrl1.rs
+++ b/esp32p4/src/lcd_cam/lcd_ctrl1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CTRL1")
-            .field(
-                "lcd_vb_front",
-                &format_args!("{}", self.lcd_vb_front().bits()),
-            )
-            .field(
-                "lcd_ha_width",
-                &format_args!("{}", self.lcd_ha_width().bits()),
-            )
-            .field(
-                "lcd_ht_width",
-                &format_args!("{}", self.lcd_ht_width().bits()),
-            )
+            .field("lcd_vb_front", &self.lcd_vb_front())
+            .field("lcd_ha_width", &self.lcd_ha_width())
+            .field("lcd_ht_width", &self.lcd_ht_width())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - It is the vertical blank front porch of a frame."]
     #[inline(always)]
diff --git a/esp32p4/src/lcd_cam/lcd_ctrl2.rs b/esp32p4/src/lcd_cam/lcd_ctrl2.rs
index 5d65cb5641..b36e1f6bc4 100644
--- a/esp32p4/src/lcd_cam/lcd_ctrl2.rs
+++ b/esp32p4/src/lcd_cam/lcd_ctrl2.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CTRL2")
-            .field(
-                "lcd_vsync_width",
-                &format_args!("{}", self.lcd_vsync_width().bits()),
-            )
-            .field(
-                "lcd_vsync_idle_pol",
-                &format_args!("{}", self.lcd_vsync_idle_pol().bit()),
-            )
-            .field(
-                "lcd_de_idle_pol",
-                &format_args!("{}", self.lcd_de_idle_pol().bit()),
-            )
-            .field(
-                "lcd_hs_blank_en",
-                &format_args!("{}", self.lcd_hs_blank_en().bit()),
-            )
-            .field(
-                "lcd_hsync_width",
-                &format_args!("{}", self.lcd_hsync_width().bits()),
-            )
-            .field(
-                "lcd_hsync_idle_pol",
-                &format_args!("{}", self.lcd_hsync_idle_pol().bit()),
-            )
-            .field(
-                "lcd_hsync_position",
-                &format_args!("{}", self.lcd_hsync_position().bits()),
-            )
+            .field("lcd_vsync_width", &self.lcd_vsync_width())
+            .field("lcd_vsync_idle_pol", &self.lcd_vsync_idle_pol())
+            .field("lcd_de_idle_pol", &self.lcd_de_idle_pol())
+            .field("lcd_hs_blank_en", &self.lcd_hs_blank_en())
+            .field("lcd_hsync_width", &self.lcd_hsync_width())
+            .field("lcd_hsync_idle_pol", &self.lcd_hsync_idle_pol())
+            .field("lcd_hsync_position", &self.lcd_hsync_position())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - It is the position of LCD_VSYNC active pulse in a line."]
     #[inline(always)]
diff --git a/esp32p4/src/lcd_cam/lcd_dly_mode_cfg1.rs b/esp32p4/src/lcd_cam/lcd_dly_mode_cfg1.rs
index 3050b81332..b1438372f8 100644
--- a/esp32p4/src/lcd_cam/lcd_dly_mode_cfg1.rs
+++ b/esp32p4/src/lcd_cam/lcd_dly_mode_cfg1.rs
@@ -173,63 +173,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_DLY_MODE_CFG1")
-            .field(
-                "dout16_mode",
-                &format_args!("{}", self.dout16_mode().bits()),
-            )
-            .field(
-                "dout17_mode",
-                &format_args!("{}", self.dout17_mode().bits()),
-            )
-            .field(
-                "dout18_mode",
-                &format_args!("{}", self.dout18_mode().bits()),
-            )
-            .field(
-                "dout19_mode",
-                &format_args!("{}", self.dout19_mode().bits()),
-            )
-            .field(
-                "dout20_mode",
-                &format_args!("{}", self.dout20_mode().bits()),
-            )
-            .field(
-                "dout21_mode",
-                &format_args!("{}", self.dout21_mode().bits()),
-            )
-            .field(
-                "dout22_mode",
-                &format_args!("{}", self.dout22_mode().bits()),
-            )
-            .field(
-                "dout23_mode",
-                &format_args!("{}", self.dout23_mode().bits()),
-            )
-            .field(
-                "lcd_cd_mode",
-                &format_args!("{}", self.lcd_cd_mode().bits()),
-            )
-            .field(
-                "lcd_de_mode",
-                &format_args!("{}", self.lcd_de_mode().bits()),
-            )
-            .field(
-                "lcd_hsync_mode",
-                &format_args!("{}", self.lcd_hsync_mode().bits()),
-            )
-            .field(
-                "lcd_vsync_mode",
-                &format_args!("{}", self.lcd_vsync_mode().bits()),
-            )
+            .field("dout16_mode", &self.dout16_mode())
+            .field("dout17_mode", &self.dout17_mode())
+            .field("dout18_mode", &self.dout18_mode())
+            .field("dout19_mode", &self.dout19_mode())
+            .field("dout20_mode", &self.dout20_mode())
+            .field("dout21_mode", &self.dout21_mode())
+            .field("dout22_mode", &self.dout22_mode())
+            .field("dout23_mode", &self.dout23_mode())
+            .field("lcd_cd_mode", &self.lcd_cd_mode())
+            .field("lcd_de_mode", &self.lcd_de_mode())
+            .field("lcd_hsync_mode", &self.lcd_hsync_mode())
+            .field("lcd_vsync_mode", &self.lcd_vsync_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_DLY_MODE_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The output data bit (16-23) is delayed by module clock LCD_CLK"]
     #[doc = ""]
diff --git a/esp32p4/src/lcd_cam/lcd_dly_mode_cfg2.rs b/esp32p4/src/lcd_cam/lcd_dly_mode_cfg2.rs
index 30efe910e3..e628461903 100644
--- a/esp32p4/src/lcd_cam/lcd_dly_mode_cfg2.rs
+++ b/esp32p4/src/lcd_cam/lcd_dly_mode_cfg2.rs
@@ -109,49 +109,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_DLY_MODE_CFG2")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bits()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bits()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bits()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bits()))
-            .field("dout4_mode", &format_args!("{}", self.dout4_mode().bits()))
-            .field("dout5_mode", &format_args!("{}", self.dout5_mode().bits()))
-            .field("dout6_mode", &format_args!("{}", self.dout6_mode().bits()))
-            .field("dout7_mode", &format_args!("{}", self.dout7_mode().bits()))
-            .field("dout8_mode", &format_args!("{}", self.dout8_mode().bits()))
-            .field("dout9_mode", &format_args!("{}", self.dout9_mode().bits()))
-            .field(
-                "dout10_mode",
-                &format_args!("{}", self.dout10_mode().bits()),
-            )
-            .field(
-                "dout11_mode",
-                &format_args!("{}", self.dout11_mode().bits()),
-            )
-            .field(
-                "dout12_mode",
-                &format_args!("{}", self.dout12_mode().bits()),
-            )
-            .field(
-                "dout13_mode",
-                &format_args!("{}", self.dout13_mode().bits()),
-            )
-            .field(
-                "dout14_mode",
-                &format_args!("{}", self.dout14_mode().bits()),
-            )
-            .field(
-                "dout15_mode",
-                &format_args!("{}", self.dout15_mode().bits()),
-            )
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
+            .field("dout4_mode", &self.dout4_mode())
+            .field("dout5_mode", &self.dout5_mode())
+            .field("dout6_mode", &self.dout6_mode())
+            .field("dout7_mode", &self.dout7_mode())
+            .field("dout8_mode", &self.dout8_mode())
+            .field("dout9_mode", &self.dout9_mode())
+            .field("dout10_mode", &self.dout10_mode())
+            .field("dout11_mode", &self.dout11_mode())
+            .field("dout12_mode", &self.dout12_mode())
+            .field("dout13_mode", &self.dout13_mode())
+            .field("dout14_mode", &self.dout14_mode())
+            .field("dout15_mode", &self.dout15_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_DLY_MODE_CFG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The output data bit (0-15) is delayed by module clock LCD_CLK"]
     #[doc = ""]
diff --git a/esp32p4/src/lcd_cam/lcd_first_cmd_val.rs b/esp32p4/src/lcd_cam/lcd_first_cmd_val.rs
index a66781ac2a..4bc7d7eaca 100644
--- a/esp32p4/src/lcd_cam/lcd_first_cmd_val.rs
+++ b/esp32p4/src/lcd_cam/lcd_first_cmd_val.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_FIRST_CMD_VAL")
-            .field(
-                "lcd_first_cmd_value",
-                &format_args!("{}", self.lcd_first_cmd_value().bits()),
-            )
+            .field("lcd_first_cmd_value", &self.lcd_first_cmd_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_FIRST_CMD_VAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The LCD write command value of first cmd cycle."]
     #[inline(always)]
diff --git a/esp32p4/src/lcd_cam/lcd_latter_cmd_val.rs b/esp32p4/src/lcd_cam/lcd_latter_cmd_val.rs
index fbe5f378e3..618539c7a8 100644
--- a/esp32p4/src/lcd_cam/lcd_latter_cmd_val.rs
+++ b/esp32p4/src/lcd_cam/lcd_latter_cmd_val.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_LATTER_CMD_VAL")
-            .field(
-                "lcd_latter_cmd_value",
-                &format_args!("{}", self.lcd_latter_cmd_value().bits()),
-            )
+            .field("lcd_latter_cmd_value", &self.lcd_latter_cmd_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_LATTER_CMD_VAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The LCD write command value of latter cmd cycle."]
     #[inline(always)]
diff --git a/esp32p4/src/lcd_cam/lcd_misc.rs b/esp32p4/src/lcd_cam/lcd_misc.rs
index 89e236cf87..776a2be921 100644
--- a/esp32p4/src/lcd_cam/lcd_misc.rs
+++ b/esp32p4/src/lcd_cam/lcd_misc.rs
@@ -91,48 +91,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_MISC")
-            .field(
-                "lcd_wire_mode",
-                &format_args!("{}", self.lcd_wire_mode().bits()),
-            )
-            .field(
-                "lcd_vfk_cyclelen",
-                &format_args!("{}", self.lcd_vfk_cyclelen().bits()),
-            )
-            .field(
-                "lcd_vbk_cyclelen",
-                &format_args!("{}", self.lcd_vbk_cyclelen().bits()),
-            )
-            .field(
-                "lcd_next_frame_en",
-                &format_args!("{}", self.lcd_next_frame_en().bit()),
-            )
-            .field("lcd_bk_en", &format_args!("{}", self.lcd_bk_en().bit()))
-            .field(
-                "lcd_cd_data_set",
-                &format_args!("{}", self.lcd_cd_data_set().bit()),
-            )
-            .field(
-                "lcd_cd_dummy_set",
-                &format_args!("{}", self.lcd_cd_dummy_set().bit()),
-            )
-            .field(
-                "lcd_cd_cmd_set",
-                &format_args!("{}", self.lcd_cd_cmd_set().bit()),
-            )
-            .field(
-                "lcd_cd_idle_edge",
-                &format_args!("{}", self.lcd_cd_idle_edge().bit()),
-            )
+            .field("lcd_wire_mode", &self.lcd_wire_mode())
+            .field("lcd_vfk_cyclelen", &self.lcd_vfk_cyclelen())
+            .field("lcd_vbk_cyclelen", &self.lcd_vbk_cyclelen())
+            .field("lcd_next_frame_en", &self.lcd_next_frame_en())
+            .field("lcd_bk_en", &self.lcd_bk_en())
+            .field("lcd_cd_data_set", &self.lcd_cd_data_set())
+            .field("lcd_cd_dummy_set", &self.lcd_cd_dummy_set())
+            .field("lcd_cd_cmd_set", &self.lcd_cd_cmd_set())
+            .field("lcd_cd_idle_edge", &self.lcd_cd_idle_edge())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 4:5 - The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit"]
     #[inline(always)]
diff --git a/esp32p4/src/lcd_cam/lcd_rgb_yuv.rs b/esp32p4/src/lcd_cam/lcd_rgb_yuv.rs
index af4221f334..0bde10873a 100644
--- a/esp32p4/src/lcd_cam/lcd_rgb_yuv.rs
+++ b/esp32p4/src/lcd_cam/lcd_rgb_yuv.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_RGB_YUV")
-            .field(
-                "lcd_conv_8bits_data_inv",
-                &format_args!("{}", self.lcd_conv_8bits_data_inv().bit()),
-            )
-            .field(
-                "lcd_conv_txtorx",
-                &format_args!("{}", self.lcd_conv_txtorx().bit()),
-            )
-            .field(
-                "lcd_conv_yuv2yuv_mode",
-                &format_args!("{}", self.lcd_conv_yuv2yuv_mode().bits()),
-            )
-            .field(
-                "lcd_conv_yuv_mode",
-                &format_args!("{}", self.lcd_conv_yuv_mode().bits()),
-            )
-            .field(
-                "lcd_conv_protocol_mode",
-                &format_args!("{}", self.lcd_conv_protocol_mode().bit()),
-            )
-            .field(
-                "lcd_conv_data_out_mode",
-                &format_args!("{}", self.lcd_conv_data_out_mode().bit()),
-            )
-            .field(
-                "lcd_conv_data_in_mode",
-                &format_args!("{}", self.lcd_conv_data_in_mode().bit()),
-            )
-            .field(
-                "lcd_conv_mode_8bits_on",
-                &format_args!("{}", self.lcd_conv_mode_8bits_on().bit()),
-            )
-            .field(
-                "lcd_conv_trans_mode",
-                &format_args!("{}", self.lcd_conv_trans_mode().bit()),
-            )
-            .field(
-                "lcd_conv_enable",
-                &format_args!("{}", self.lcd_conv_enable().bit()),
-            )
+            .field("lcd_conv_8bits_data_inv", &self.lcd_conv_8bits_data_inv())
+            .field("lcd_conv_txtorx", &self.lcd_conv_txtorx())
+            .field("lcd_conv_yuv2yuv_mode", &self.lcd_conv_yuv2yuv_mode())
+            .field("lcd_conv_yuv_mode", &self.lcd_conv_yuv_mode())
+            .field("lcd_conv_protocol_mode", &self.lcd_conv_protocol_mode())
+            .field("lcd_conv_data_out_mode", &self.lcd_conv_data_out_mode())
+            .field("lcd_conv_data_in_mode", &self.lcd_conv_data_in_mode())
+            .field("lcd_conv_mode_8bits_on", &self.lcd_conv_mode_8bits_on())
+            .field("lcd_conv_trans_mode", &self.lcd_conv_trans_mode())
+            .field("lcd_conv_enable", &self.lcd_conv_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_RGB_YUV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - 1:invert every two 8bits input data. 2. disabled."]
     #[inline(always)]
diff --git a/esp32p4/src/lcd_cam/lcd_user.rs b/esp32p4/src/lcd_cam/lcd_user.rs
index ffc937c92d..bdc22722e6 100644
--- a/esp32p4/src/lcd_cam/lcd_user.rs
+++ b/esp32p4/src/lcd_cam/lcd_user.rs
@@ -145,60 +145,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_USER")
-            .field(
-                "lcd_dout_cyclelen",
-                &format_args!("{}", self.lcd_dout_cyclelen().bits()),
-            )
-            .field(
-                "lcd_always_out_en",
-                &format_args!("{}", self.lcd_always_out_en().bit()),
-            )
+            .field("lcd_dout_cyclelen", &self.lcd_dout_cyclelen())
+            .field("lcd_always_out_en", &self.lcd_always_out_en())
             .field(
                 "lcd_dout_byte_swizzle_mode",
-                &format_args!("{}", self.lcd_dout_byte_swizzle_mode().bits()),
+                &self.lcd_dout_byte_swizzle_mode(),
             )
             .field(
                 "lcd_dout_byte_swizzle_enable",
-                &format_args!("{}", self.lcd_dout_byte_swizzle_enable().bit()),
-            )
-            .field(
-                "lcd_dout_bit_order",
-                &format_args!("{}", self.lcd_dout_bit_order().bit()),
-            )
-            .field(
-                "lcd_byte_mode",
-                &format_args!("{}", self.lcd_byte_mode().bits()),
-            )
-            .field("lcd_update", &format_args!("{}", self.lcd_update().bit()))
-            .field(
-                "lcd_bit_order",
-                &format_args!("{}", self.lcd_bit_order().bit()),
-            )
-            .field(
-                "lcd_byte_order",
-                &format_args!("{}", self.lcd_byte_order().bit()),
-            )
-            .field("lcd_dout", &format_args!("{}", self.lcd_dout().bit()))
-            .field("lcd_dummy", &format_args!("{}", self.lcd_dummy().bit()))
-            .field("lcd_cmd", &format_args!("{}", self.lcd_cmd().bit()))
-            .field("lcd_start", &format_args!("{}", self.lcd_start().bit()))
-            .field(
-                "lcd_dummy_cyclelen",
-                &format_args!("{}", self.lcd_dummy_cyclelen().bits()),
-            )
-            .field(
-                "lcd_cmd_2_cycle_en",
-                &format_args!("{}", self.lcd_cmd_2_cycle_en().bit()),
+                &self.lcd_dout_byte_swizzle_enable(),
             )
+            .field("lcd_dout_bit_order", &self.lcd_dout_bit_order())
+            .field("lcd_byte_mode", &self.lcd_byte_mode())
+            .field("lcd_update", &self.lcd_update())
+            .field("lcd_bit_order", &self.lcd_bit_order())
+            .field("lcd_byte_order", &self.lcd_byte_order())
+            .field("lcd_dout", &self.lcd_dout())
+            .field("lcd_dummy", &self.lcd_dummy())
+            .field("lcd_cmd", &self.lcd_cmd())
+            .field("lcd_start", &self.lcd_start())
+            .field("lcd_dummy_cyclelen", &self.lcd_dummy_cyclelen())
+            .field("lcd_cmd_2_cycle_en", &self.lcd_cmd_2_cycle_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - The output data cycles minus 1 of LCD module."]
     #[inline(always)]
diff --git a/esp32p4/src/ledc/ch/conf0.rs b/esp32p4/src/ledc/ch/conf0.rs
index 115dc8e307..87f418bfa8 100644
--- a/esp32p4/src/ledc/ch/conf0.rs
+++ b/esp32p4/src/ledc/ch/conf0.rs
@@ -57,20 +57,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("timer_sel", &format_args!("{}", self.timer_sel().bits()))
-            .field("sig_out_en", &format_args!("{}", self.sig_out_en().bit()))
-            .field("idle_lv", &format_args!("{}", self.idle_lv().bit()))
-            .field("ovf_num", &format_args!("{}", self.ovf_num().bits()))
-            .field("ovf_cnt_en", &format_args!("{}", self.ovf_cnt_en().bit()))
+            .field("timer_sel", &self.timer_sel())
+            .field("sig_out_en", &self.sig_out_en())
+            .field("idle_lv", &self.idle_lv())
+            .field("ovf_num", &self.ovf_num())
+            .field("ovf_cnt_en", &self.ovf_cnt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Configures which timer is channel %s selected.\\\\0: Select timer0\\\\1: Select timer1\\\\2: Select timer2\\\\3: Select timer3"]
     #[inline(always)]
diff --git a/esp32p4/src/ledc/ch/conf1.rs b/esp32p4/src/ledc/ch/conf1.rs
index a54a2912d4..ce2be092a7 100644
--- a/esp32p4/src/ledc/ch/conf1.rs
+++ b/esp32p4/src/ledc/ch/conf1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field("duty_start", &format_args!("{}", self.duty_start().bit()))
+            .field("duty_start", &self.duty_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Configures whether the duty cycle fading configurations take effect.\\\\0: Not take effect\\\\1: Take effect"]
     #[inline(always)]
diff --git a/esp32p4/src/ledc/ch/duty.rs b/esp32p4/src/ledc/ch/duty.rs
index 496047fab2..060e86f8a0 100644
--- a/esp32p4/src/ledc/ch/duty.rs
+++ b/esp32p4/src/ledc/ch/duty.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DUTY")
-            .field("duty", &format_args!("{}", self.duty().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DUTY").field("duty", &self.duty()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/ledc/ch/duty_r.rs b/esp32p4/src/ledc/ch/duty_r.rs
index 408d639066..2e88e4ab7c 100644
--- a/esp32p4/src/ledc/ch/duty_r.rs
+++ b/esp32p4/src/ledc/ch/duty_r.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DUTY_R")
-            .field("duty_r", &format_args!("{}", self.duty_r().bits()))
+            .field("duty_r", &self.duty_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_R_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current duty cycle register for channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`duty_r::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DUTY_R_SPEC;
 impl crate::RegisterSpec for DUTY_R_SPEC {
diff --git a/esp32p4/src/ledc/ch/hpoint.rs b/esp32p4/src/ledc/ch/hpoint.rs
index f3232d8b8d..fb36d40627 100644
--- a/esp32p4/src/ledc/ch/hpoint.rs
+++ b/esp32p4/src/ledc/ch/hpoint.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPOINT")
-            .field("hpoint", &format_args!("{}", self.hpoint().bits()))
+            .field("hpoint", &self.hpoint())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPOINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - Configures high point of signal output on channel %s. The output value changes to high when the selected timers has reached the value specified by this register."]
     #[inline(always)]
diff --git a/esp32p4/src/ledc/ch_gamma_conf.rs b/esp32p4/src/ledc/ch_gamma_conf.rs
index 2465d88375..69b52d356a 100644
--- a/esp32p4/src/ledc/ch_gamma_conf.rs
+++ b/esp32p4/src/ledc/ch_gamma_conf.rs
@@ -21,19 +21,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_GAMMA_CONF")
-            .field(
-                "ch_gamma_entry_num",
-                &format_args!("{}", self.ch_gamma_entry_num().bits()),
-            )
+            .field("ch_gamma_entry_num", &self.ch_gamma_entry_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_GAMMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Configures the number of duty cycle fading rages for LEDC ch%s."]
     #[inline(always)]
diff --git a/esp32p4/src/ledc/conf.rs b/esp32p4/src/ledc/conf.rs
index 76d011e3de..92fef2f64c 100644
--- a/esp32p4/src/ledc/conf.rs
+++ b/esp32p4/src/ledc/conf.rs
@@ -98,52 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field(
-                "apb_clk_sel",
-                &format_args!("{}", self.apb_clk_sel().bits()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch0",
-                &format_args!("{}", self.gamma_ram_clk_en_ch0().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch1",
-                &format_args!("{}", self.gamma_ram_clk_en_ch1().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch2",
-                &format_args!("{}", self.gamma_ram_clk_en_ch2().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch3",
-                &format_args!("{}", self.gamma_ram_clk_en_ch3().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch4",
-                &format_args!("{}", self.gamma_ram_clk_en_ch4().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch5",
-                &format_args!("{}", self.gamma_ram_clk_en_ch5().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch6",
-                &format_args!("{}", self.gamma_ram_clk_en_ch6().bit()),
-            )
-            .field(
-                "gamma_ram_clk_en_ch7",
-                &format_args!("{}", self.gamma_ram_clk_en_ch7().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("apb_clk_sel", &self.apb_clk_sel())
+            .field("gamma_ram_clk_en_ch0", &self.gamma_ram_clk_en_ch0())
+            .field("gamma_ram_clk_en_ch1", &self.gamma_ram_clk_en_ch1())
+            .field("gamma_ram_clk_en_ch2", &self.gamma_ram_clk_en_ch2())
+            .field("gamma_ram_clk_en_ch3", &self.gamma_ram_clk_en_ch3())
+            .field("gamma_ram_clk_en_ch4", &self.gamma_ram_clk_en_ch4())
+            .field("gamma_ram_clk_en_ch5", &self.gamma_ram_clk_en_ch5())
+            .field("gamma_ram_clk_en_ch6", &self.gamma_ram_clk_en_ch6())
+            .field("gamma_ram_clk_en_ch7", &self.gamma_ram_clk_en_ch7())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Configures the clock source for the four timers.\\\\0: APB_CLK\\\\1: RC_FAST_CLK\\\\2: XTAL_CLK\\\\3: Invalid. No clock"]
     #[inline(always)]
diff --git a/esp32p4/src/ledc/date.rs b/esp32p4/src/ledc/date.rs
index 8316f04750..155e72312a 100644
--- a/esp32p4/src/ledc/date.rs
+++ b/esp32p4/src/ledc/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("ledc_date", &format_args!("{}", self.ledc_date().bits()))
+            .field("ledc_date", &self.ledc_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Configures the version."]
     #[inline(always)]
diff --git a/esp32p4/src/ledc/evt_task_en0.rs b/esp32p4/src/ledc/evt_task_en0.rs
index 875a1fb564..71e2bd1561 100644
--- a/esp32p4/src/ledc/evt_task_en0.rs
+++ b/esp32p4/src/ledc/evt_task_en0.rs
@@ -296,143 +296,65 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVT_TASK_EN0")
-            .field(
-                "evt_duty_chng_end_ch0_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch0_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch1_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch1_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch2_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch2_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch3_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch3_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch4_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch4_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch5_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch5_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch6_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch6_en().bit()),
-            )
-            .field(
-                "evt_duty_chng_end_ch7_en",
-                &format_args!("{}", self.evt_duty_chng_end_ch7_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch0_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch0_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch1_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch1_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch2_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch2_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch3_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch3_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch4_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch4_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch5_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch5_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch6_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch6_en().bit()),
-            )
-            .field(
-                "evt_ovf_cnt_pls_ch7_en",
-                &format_args!("{}", self.evt_ovf_cnt_pls_ch7_en().bit()),
-            )
-            .field(
-                "evt_time_ovf_timer0_en",
-                &format_args!("{}", self.evt_time_ovf_timer0_en().bit()),
-            )
-            .field(
-                "evt_time_ovf_timer1_en",
-                &format_args!("{}", self.evt_time_ovf_timer1_en().bit()),
-            )
-            .field(
-                "evt_time_ovf_timer2_en",
-                &format_args!("{}", self.evt_time_ovf_timer2_en().bit()),
-            )
-            .field(
-                "evt_time_ovf_timer3_en",
-                &format_args!("{}", self.evt_time_ovf_timer3_en().bit()),
-            )
-            .field(
-                "evt_time0_cmp_en",
-                &format_args!("{}", self.evt_time0_cmp_en().bit()),
-            )
-            .field(
-                "evt_time1_cmp_en",
-                &format_args!("{}", self.evt_time1_cmp_en().bit()),
-            )
-            .field(
-                "evt_time2_cmp_en",
-                &format_args!("{}", self.evt_time2_cmp_en().bit()),
-            )
-            .field(
-                "evt_time3_cmp_en",
-                &format_args!("{}", self.evt_time3_cmp_en().bit()),
-            )
+            .field("evt_duty_chng_end_ch0_en", &self.evt_duty_chng_end_ch0_en())
+            .field("evt_duty_chng_end_ch1_en", &self.evt_duty_chng_end_ch1_en())
+            .field("evt_duty_chng_end_ch2_en", &self.evt_duty_chng_end_ch2_en())
+            .field("evt_duty_chng_end_ch3_en", &self.evt_duty_chng_end_ch3_en())
+            .field("evt_duty_chng_end_ch4_en", &self.evt_duty_chng_end_ch4_en())
+            .field("evt_duty_chng_end_ch5_en", &self.evt_duty_chng_end_ch5_en())
+            .field("evt_duty_chng_end_ch6_en", &self.evt_duty_chng_end_ch6_en())
+            .field("evt_duty_chng_end_ch7_en", &self.evt_duty_chng_end_ch7_en())
+            .field("evt_ovf_cnt_pls_ch0_en", &self.evt_ovf_cnt_pls_ch0_en())
+            .field("evt_ovf_cnt_pls_ch1_en", &self.evt_ovf_cnt_pls_ch1_en())
+            .field("evt_ovf_cnt_pls_ch2_en", &self.evt_ovf_cnt_pls_ch2_en())
+            .field("evt_ovf_cnt_pls_ch3_en", &self.evt_ovf_cnt_pls_ch3_en())
+            .field("evt_ovf_cnt_pls_ch4_en", &self.evt_ovf_cnt_pls_ch4_en())
+            .field("evt_ovf_cnt_pls_ch5_en", &self.evt_ovf_cnt_pls_ch5_en())
+            .field("evt_ovf_cnt_pls_ch6_en", &self.evt_ovf_cnt_pls_ch6_en())
+            .field("evt_ovf_cnt_pls_ch7_en", &self.evt_ovf_cnt_pls_ch7_en())
+            .field("evt_time_ovf_timer0_en", &self.evt_time_ovf_timer0_en())
+            .field("evt_time_ovf_timer1_en", &self.evt_time_ovf_timer1_en())
+            .field("evt_time_ovf_timer2_en", &self.evt_time_ovf_timer2_en())
+            .field("evt_time_ovf_timer3_en", &self.evt_time_ovf_timer3_en())
+            .field("evt_time0_cmp_en", &self.evt_time0_cmp_en())
+            .field("evt_time1_cmp_en", &self.evt_time1_cmp_en())
+            .field("evt_time2_cmp_en", &self.evt_time2_cmp_en())
+            .field("evt_time3_cmp_en", &self.evt_time3_cmp_en())
             .field(
                 "task_duty_scale_update_ch0_en",
-                &format_args!("{}", self.task_duty_scale_update_ch0_en().bit()),
+                &self.task_duty_scale_update_ch0_en(),
             )
             .field(
                 "task_duty_scale_update_ch1_en",
-                &format_args!("{}", self.task_duty_scale_update_ch1_en().bit()),
+                &self.task_duty_scale_update_ch1_en(),
             )
             .field(
                 "task_duty_scale_update_ch2_en",
-                &format_args!("{}", self.task_duty_scale_update_ch2_en().bit()),
+                &self.task_duty_scale_update_ch2_en(),
             )
             .field(
                 "task_duty_scale_update_ch3_en",
-                &format_args!("{}", self.task_duty_scale_update_ch3_en().bit()),
+                &self.task_duty_scale_update_ch3_en(),
             )
             .field(
                 "task_duty_scale_update_ch4_en",
-                &format_args!("{}", self.task_duty_scale_update_ch4_en().bit()),
+                &self.task_duty_scale_update_ch4_en(),
             )
             .field(
                 "task_duty_scale_update_ch5_en",
-                &format_args!("{}", self.task_duty_scale_update_ch5_en().bit()),
+                &self.task_duty_scale_update_ch5_en(),
             )
             .field(
                 "task_duty_scale_update_ch6_en",
-                &format_args!("{}", self.task_duty_scale_update_ch6_en().bit()),
+                &self.task_duty_scale_update_ch6_en(),
             )
             .field(
                 "task_duty_scale_update_ch7_en",
-                &format_args!("{}", self.task_duty_scale_update_ch7_en().bit()),
+                &self.task_duty_scale_update_ch7_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_TASK_EN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\\\0: Disable\\\\1: Enable"]
     #[inline(always)]
diff --git a/esp32p4/src/ledc/evt_task_en1.rs b/esp32p4/src/ledc/evt_task_en1.rs
index 706990cdf9..e319f51db2 100644
--- a/esp32p4/src/ledc/evt_task_en1.rs
+++ b/esp32p4/src/ledc/evt_task_en1.rs
@@ -298,141 +298,63 @@ impl core::fmt::Debug for R {
         f.debug_struct("EVT_TASK_EN1")
             .field(
                 "task_timer0_res_update_en",
-                &format_args!("{}", self.task_timer0_res_update_en().bit()),
+                &self.task_timer0_res_update_en(),
             )
             .field(
                 "task_timer1_res_update_en",
-                &format_args!("{}", self.task_timer1_res_update_en().bit()),
+                &self.task_timer1_res_update_en(),
             )
             .field(
                 "task_timer2_res_update_en",
-                &format_args!("{}", self.task_timer2_res_update_en().bit()),
+                &self.task_timer2_res_update_en(),
             )
             .field(
                 "task_timer3_res_update_en",
-                &format_args!("{}", self.task_timer3_res_update_en().bit()),
-            )
-            .field(
-                "task_timer0_cap_en",
-                &format_args!("{}", self.task_timer0_cap_en().bit()),
-            )
-            .field(
-                "task_timer1_cap_en",
-                &format_args!("{}", self.task_timer1_cap_en().bit()),
-            )
-            .field(
-                "task_timer2_cap_en",
-                &format_args!("{}", self.task_timer2_cap_en().bit()),
-            )
-            .field(
-                "task_timer3_cap_en",
-                &format_args!("{}", self.task_timer3_cap_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch0_en",
-                &format_args!("{}", self.task_sig_out_dis_ch0_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch1_en",
-                &format_args!("{}", self.task_sig_out_dis_ch1_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch2_en",
-                &format_args!("{}", self.task_sig_out_dis_ch2_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch3_en",
-                &format_args!("{}", self.task_sig_out_dis_ch3_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch4_en",
-                &format_args!("{}", self.task_sig_out_dis_ch4_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch5_en",
-                &format_args!("{}", self.task_sig_out_dis_ch5_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch6_en",
-                &format_args!("{}", self.task_sig_out_dis_ch6_en().bit()),
-            )
-            .field(
-                "task_sig_out_dis_ch7_en",
-                &format_args!("{}", self.task_sig_out_dis_ch7_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch0_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch0_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch1_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch1_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch2_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch2_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch3_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch3_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch4_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch4_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch5_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch5_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch6_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch6_en().bit()),
-            )
-            .field(
-                "task_ovf_cnt_rst_ch7_en",
-                &format_args!("{}", self.task_ovf_cnt_rst_ch7_en().bit()),
-            )
-            .field(
-                "task_timer0_rst_en",
-                &format_args!("{}", self.task_timer0_rst_en().bit()),
-            )
-            .field(
-                "task_timer1_rst_en",
-                &format_args!("{}", self.task_timer1_rst_en().bit()),
-            )
-            .field(
-                "task_timer2_rst_en",
-                &format_args!("{}", self.task_timer2_rst_en().bit()),
-            )
-            .field(
-                "task_timer3_rst_en",
-                &format_args!("{}", self.task_timer3_rst_en().bit()),
-            )
+                &self.task_timer3_res_update_en(),
+            )
+            .field("task_timer0_cap_en", &self.task_timer0_cap_en())
+            .field("task_timer1_cap_en", &self.task_timer1_cap_en())
+            .field("task_timer2_cap_en", &self.task_timer2_cap_en())
+            .field("task_timer3_cap_en", &self.task_timer3_cap_en())
+            .field("task_sig_out_dis_ch0_en", &self.task_sig_out_dis_ch0_en())
+            .field("task_sig_out_dis_ch1_en", &self.task_sig_out_dis_ch1_en())
+            .field("task_sig_out_dis_ch2_en", &self.task_sig_out_dis_ch2_en())
+            .field("task_sig_out_dis_ch3_en", &self.task_sig_out_dis_ch3_en())
+            .field("task_sig_out_dis_ch4_en", &self.task_sig_out_dis_ch4_en())
+            .field("task_sig_out_dis_ch5_en", &self.task_sig_out_dis_ch5_en())
+            .field("task_sig_out_dis_ch6_en", &self.task_sig_out_dis_ch6_en())
+            .field("task_sig_out_dis_ch7_en", &self.task_sig_out_dis_ch7_en())
+            .field("task_ovf_cnt_rst_ch0_en", &self.task_ovf_cnt_rst_ch0_en())
+            .field("task_ovf_cnt_rst_ch1_en", &self.task_ovf_cnt_rst_ch1_en())
+            .field("task_ovf_cnt_rst_ch2_en", &self.task_ovf_cnt_rst_ch2_en())
+            .field("task_ovf_cnt_rst_ch3_en", &self.task_ovf_cnt_rst_ch3_en())
+            .field("task_ovf_cnt_rst_ch4_en", &self.task_ovf_cnt_rst_ch4_en())
+            .field("task_ovf_cnt_rst_ch5_en", &self.task_ovf_cnt_rst_ch5_en())
+            .field("task_ovf_cnt_rst_ch6_en", &self.task_ovf_cnt_rst_ch6_en())
+            .field("task_ovf_cnt_rst_ch7_en", &self.task_ovf_cnt_rst_ch7_en())
+            .field("task_timer0_rst_en", &self.task_timer0_rst_en())
+            .field("task_timer1_rst_en", &self.task_timer1_rst_en())
+            .field("task_timer2_rst_en", &self.task_timer2_rst_en())
+            .field("task_timer3_rst_en", &self.task_timer3_rst_en())
             .field(
                 "task_timer0_pause_resume_en",
-                &format_args!("{}", self.task_timer0_pause_resume_en().bit()),
+                &self.task_timer0_pause_resume_en(),
             )
             .field(
                 "task_timer1_pause_resume_en",
-                &format_args!("{}", self.task_timer1_pause_resume_en().bit()),
+                &self.task_timer1_pause_resume_en(),
             )
             .field(
                 "task_timer2_pause_resume_en",
-                &format_args!("{}", self.task_timer2_pause_resume_en().bit()),
+                &self.task_timer2_pause_resume_en(),
             )
             .field(
                 "task_timer3_pause_resume_en",
-                &format_args!("{}", self.task_timer3_pause_resume_en().bit()),
+                &self.task_timer3_pause_resume_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_TASK_EN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to enable ledc_timer0_res_update task.\\\\0: Disable\\\\1: Enable"]
     #[inline(always)]
diff --git a/esp32p4/src/ledc/evt_task_en2.rs b/esp32p4/src/ledc/evt_task_en2.rs
index 8ce6eb4813..f404fa1b87 100644
--- a/esp32p4/src/ledc/evt_task_en2.rs
+++ b/esp32p4/src/ledc/evt_task_en2.rs
@@ -226,109 +226,55 @@ impl core::fmt::Debug for R {
         f.debug_struct("EVT_TASK_EN2")
             .field(
                 "task_gamma_restart_ch0_en",
-                &format_args!("{}", self.task_gamma_restart_ch0_en().bit()),
+                &self.task_gamma_restart_ch0_en(),
             )
             .field(
                 "task_gamma_restart_ch1_en",
-                &format_args!("{}", self.task_gamma_restart_ch1_en().bit()),
+                &self.task_gamma_restart_ch1_en(),
             )
             .field(
                 "task_gamma_restart_ch2_en",
-                &format_args!("{}", self.task_gamma_restart_ch2_en().bit()),
+                &self.task_gamma_restart_ch2_en(),
             )
             .field(
                 "task_gamma_restart_ch3_en",
-                &format_args!("{}", self.task_gamma_restart_ch3_en().bit()),
+                &self.task_gamma_restart_ch3_en(),
             )
             .field(
                 "task_gamma_restart_ch4_en",
-                &format_args!("{}", self.task_gamma_restart_ch4_en().bit()),
+                &self.task_gamma_restart_ch4_en(),
             )
             .field(
                 "task_gamma_restart_ch5_en",
-                &format_args!("{}", self.task_gamma_restart_ch5_en().bit()),
+                &self.task_gamma_restart_ch5_en(),
             )
             .field(
                 "task_gamma_restart_ch6_en",
-                &format_args!("{}", self.task_gamma_restart_ch6_en().bit()),
+                &self.task_gamma_restart_ch6_en(),
             )
             .field(
                 "task_gamma_restart_ch7_en",
-                &format_args!("{}", self.task_gamma_restart_ch7_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch0_en",
-                &format_args!("{}", self.task_gamma_pause_ch0_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch1_en",
-                &format_args!("{}", self.task_gamma_pause_ch1_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch2_en",
-                &format_args!("{}", self.task_gamma_pause_ch2_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch3_en",
-                &format_args!("{}", self.task_gamma_pause_ch3_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch4_en",
-                &format_args!("{}", self.task_gamma_pause_ch4_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch5_en",
-                &format_args!("{}", self.task_gamma_pause_ch5_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch6_en",
-                &format_args!("{}", self.task_gamma_pause_ch6_en().bit()),
-            )
-            .field(
-                "task_gamma_pause_ch7_en",
-                &format_args!("{}", self.task_gamma_pause_ch7_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch0_en",
-                &format_args!("{}", self.task_gamma_resume_ch0_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch1_en",
-                &format_args!("{}", self.task_gamma_resume_ch1_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch2_en",
-                &format_args!("{}", self.task_gamma_resume_ch2_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch3_en",
-                &format_args!("{}", self.task_gamma_resume_ch3_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch4_en",
-                &format_args!("{}", self.task_gamma_resume_ch4_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch5_en",
-                &format_args!("{}", self.task_gamma_resume_ch5_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch6_en",
-                &format_args!("{}", self.task_gamma_resume_ch6_en().bit()),
-            )
-            .field(
-                "task_gamma_resume_ch7_en",
-                &format_args!("{}", self.task_gamma_resume_ch7_en().bit()),
+                &self.task_gamma_restart_ch7_en(),
             )
+            .field("task_gamma_pause_ch0_en", &self.task_gamma_pause_ch0_en())
+            .field("task_gamma_pause_ch1_en", &self.task_gamma_pause_ch1_en())
+            .field("task_gamma_pause_ch2_en", &self.task_gamma_pause_ch2_en())
+            .field("task_gamma_pause_ch3_en", &self.task_gamma_pause_ch3_en())
+            .field("task_gamma_pause_ch4_en", &self.task_gamma_pause_ch4_en())
+            .field("task_gamma_pause_ch5_en", &self.task_gamma_pause_ch5_en())
+            .field("task_gamma_pause_ch6_en", &self.task_gamma_pause_ch6_en())
+            .field("task_gamma_pause_ch7_en", &self.task_gamma_pause_ch7_en())
+            .field("task_gamma_resume_ch0_en", &self.task_gamma_resume_ch0_en())
+            .field("task_gamma_resume_ch1_en", &self.task_gamma_resume_ch1_en())
+            .field("task_gamma_resume_ch2_en", &self.task_gamma_resume_ch2_en())
+            .field("task_gamma_resume_ch3_en", &self.task_gamma_resume_ch3_en())
+            .field("task_gamma_resume_ch4_en", &self.task_gamma_resume_ch4_en())
+            .field("task_gamma_resume_ch5_en", &self.task_gamma_resume_ch5_en())
+            .field("task_gamma_resume_ch6_en", &self.task_gamma_resume_ch6_en())
+            .field("task_gamma_resume_ch7_en", &self.task_gamma_resume_ch7_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_TASK_EN2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to enable ledc_ch0_gamma_restart task.\\\\0: Disable\\\\1: Enable"]
     #[inline(always)]
diff --git a/esp32p4/src/ledc/int_ena.rs b/esp32p4/src/ledc/int_ena.rs
index e15d7d24c7..c84d1ba7bb 100644
--- a/esp32p4/src/ledc/int_ena.rs
+++ b/esp32p4/src/ledc/int_ena.rs
@@ -165,59 +165,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field(
-                "duty_chng_end_ch6",
-                &format_args!("{}", self.duty_chng_end_ch6().bit()),
-            )
-            .field(
-                "duty_chng_end_ch7",
-                &format_args!("{}", self.duty_chng_end_ch7().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
-            .field("ovf_cnt_ch6", &format_args!("{}", self.ovf_cnt_ch6().bit()))
-            .field("ovf_cnt_ch7", &format_args!("{}", self.ovf_cnt_ch7().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("duty_chng_end_ch6", &self.duty_chng_end_ch6())
+            .field("duty_chng_end_ch7", &self.duty_chng_end_ch7())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
+            .field("ovf_cnt_ch6", &self.ovf_cnt_ch6())
+            .field("ovf_cnt_ch7", &self.ovf_cnt_ch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the TIMER(0-3)_OVF interrupt."]
     #[doc = ""]
diff --git a/esp32p4/src/ledc/int_raw.rs b/esp32p4/src/ledc/int_raw.rs
index 9830edaad6..031572b6d7 100644
--- a/esp32p4/src/ledc/int_raw.rs
+++ b/esp32p4/src/ledc/int_raw.rs
@@ -165,59 +165,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field(
-                "duty_chng_end_ch6",
-                &format_args!("{}", self.duty_chng_end_ch6().bit()),
-            )
-            .field(
-                "duty_chng_end_ch7",
-                &format_args!("{}", self.duty_chng_end_ch7().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
-            .field("ovf_cnt_ch6", &format_args!("{}", self.ovf_cnt_ch6().bit()))
-            .field("ovf_cnt_ch7", &format_args!("{}", self.ovf_cnt_ch7().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("duty_chng_end_ch6", &self.duty_chng_end_ch6())
+            .field("duty_chng_end_ch7", &self.duty_chng_end_ch7())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
+            .field("ovf_cnt_ch6", &self.ovf_cnt_ch6())
+            .field("ovf_cnt_ch7", &self.ovf_cnt_ch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Triggered when the timer(0-3) has reached its maximum counter value."]
     #[doc = ""]
diff --git a/esp32p4/src/ledc/int_st.rs b/esp32p4/src/ledc/int_st.rs
index baf0a7116a..916c78c040 100644
--- a/esp32p4/src/ledc/int_st.rs
+++ b/esp32p4/src/ledc/int_st.rs
@@ -157,59 +157,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field(
-                "duty_chng_end_ch6",
-                &format_args!("{}", self.duty_chng_end_ch6().bit()),
-            )
-            .field(
-                "duty_chng_end_ch7",
-                &format_args!("{}", self.duty_chng_end_ch7().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
-            .field("ovf_cnt_ch6", &format_args!("{}", self.ovf_cnt_ch6().bit()))
-            .field("ovf_cnt_ch7", &format_args!("{}", self.ovf_cnt_ch7().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("duty_chng_end_ch6", &self.duty_chng_end_ch6())
+            .field("duty_chng_end_ch7", &self.duty_chng_end_ch7())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
+            .field("ovf_cnt_ch6", &self.ovf_cnt_ch6())
+            .field("ovf_cnt_ch7", &self.ovf_cnt_ch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt masked status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/ledc/timer/conf.rs b/esp32p4/src/ledc/timer/conf.rs
index 1d80cabbab..27cef12ef2 100644
--- a/esp32p4/src/ledc/timer/conf.rs
+++ b/esp32p4/src/ledc/timer/conf.rs
@@ -55,20 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("duty_res", &format_args!("{}", self.duty_res().bits()))
-            .field("clk_div", &format_args!("{}", self.clk_div().bits()))
-            .field("pause", &format_args!("{}", self.pause().bit()))
-            .field("rst", &format_args!("{}", self.rst().bit()))
-            .field("tick_sel", &format_args!("{}", self.tick_sel().bit()))
+            .field("duty_res", &self.duty_res())
+            .field("clk_div", &self.clk_div())
+            .field("pause", &self.pause())
+            .field("rst", &self.rst())
+            .field("tick_sel", &self.tick_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Configures the range of the counter in timer %s."]
     #[inline(always)]
diff --git a/esp32p4/src/ledc/timer/value.rs b/esp32p4/src/ledc/timer/value.rs
index fb60c9b405..8358117ce1 100644
--- a/esp32p4/src/ledc/timer/value.rs
+++ b/esp32p4/src/ledc/timer/value.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("VALUE")
-            .field("cnt", &format_args!("{}", self.cnt().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("VALUE").field("cnt", &self.cnt()).finish()
     }
 }
 #[doc = "Timer 0 current counter value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32p4/src/ledc/timer_cmp.rs b/esp32p4/src/ledc/timer_cmp.rs
index a953ed16c5..e421480a20 100644
--- a/esp32p4/src/ledc/timer_cmp.rs
+++ b/esp32p4/src/ledc/timer_cmp.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_CMP")
-            .field("timer_cmp", &format_args!("{}", self.timer_cmp().bits()))
+            .field("timer_cmp", &self.timer_cmp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_CMP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - Configures the comparison value for LEDC timer%s."]
     #[inline(always)]
diff --git a/esp32p4/src/ledc/timer_cnt_cap.rs b/esp32p4/src/ledc/timer_cnt_cap.rs
index ac6d24037c..5b3cf3a332 100644
--- a/esp32p4/src/ledc/timer_cnt_cap.rs
+++ b/esp32p4/src/ledc/timer_cnt_cap.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_CNT_CAP")
-            .field(
-                "timer_cnt_cap",
-                &format_args!("{}", self.timer_cnt_cap().bits()),
-            )
+            .field("timer_cnt_cap", &self.timer_cnt_cap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_CNT_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Ledc timer%s captured count value register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timer_cnt_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMER_CNT_CAP_SPEC;
 impl crate::RegisterSpec for TIMER_CNT_CAP_SPEC {
diff --git a/esp32p4/src/lib.rs b/esp32p4/src/lib.rs
index d413fd7c23..f02029873e 100644
--- a/esp32p4/src/lib.rs
+++ b/esp32p4/src/lib.rs
@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32-P4 microcontrollers (generated using svd2rust v0.33.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32-P4 microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
diff --git a/esp32p4/src/lp_adc/amp_ctrl1.rs b/esp32p4/src/lp_adc/amp_ctrl1.rs
index 28ff8be674..10959538d9 100644
--- a/esp32p4/src/lp_adc/amp_ctrl1.rs
+++ b/esp32p4/src/lp_adc/amp_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AMP_CTRL1")
-            .field(
-                "sar_amp_wait1",
-                &format_args!("{}", self.sar_amp_wait1().bits()),
-            )
-            .field(
-                "sar_amp_wait2",
-                &format_args!("{}", self.sar_amp_wait2().bits()),
-            )
+            .field("sar_amp_wait1", &self.sar_amp_wait1())
+            .field("sar_amp_wait2", &self.sar_amp_wait2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AMP_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/amp_ctrl2.rs b/esp32p4/src/lp_adc/amp_ctrl2.rs
index 8e7be280f1..6644937b8f 100644
--- a/esp32p4/src/lp_adc/amp_ctrl2.rs
+++ b/esp32p4/src/lp_adc/amp_ctrl2.rs
@@ -80,47 +80,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AMP_CTRL2")
-            .field(
-                "sar1_dac_xpd_fsm_idle",
-                &format_args!("{}", self.sar1_dac_xpd_fsm_idle().bit()),
-            )
-            .field(
-                "xpd_sar_amp_fsm_idle",
-                &format_args!("{}", self.xpd_sar_amp_fsm_idle().bit()),
-            )
-            .field(
-                "amp_rst_fb_fsm_idle",
-                &format_args!("{}", self.amp_rst_fb_fsm_idle().bit()),
-            )
-            .field(
-                "amp_short_ref_fsm_idle",
-                &format_args!("{}", self.amp_short_ref_fsm_idle().bit()),
-            )
+            .field("sar1_dac_xpd_fsm_idle", &self.sar1_dac_xpd_fsm_idle())
+            .field("xpd_sar_amp_fsm_idle", &self.xpd_sar_amp_fsm_idle())
+            .field("amp_rst_fb_fsm_idle", &self.amp_rst_fb_fsm_idle())
+            .field("amp_short_ref_fsm_idle", &self.amp_short_ref_fsm_idle())
             .field(
                 "amp_short_ref_gnd_fsm_idle",
-                &format_args!("{}", self.amp_short_ref_gnd_fsm_idle().bit()),
-            )
-            .field(
-                "xpd_sar_fsm_idle",
-                &format_args!("{}", self.xpd_sar_fsm_idle().bit()),
-            )
-            .field(
-                "sar_rstb_fsm_idle",
-                &format_args!("{}", self.sar_rstb_fsm_idle().bit()),
-            )
-            .field(
-                "sar_amp_wait3",
-                &format_args!("{}", self.sar_amp_wait3().bits()),
+                &self.amp_short_ref_gnd_fsm_idle(),
             )
+            .field("xpd_sar_fsm_idle", &self.xpd_sar_fsm_idle())
+            .field("sar_rstb_fsm_idle", &self.sar_rstb_fsm_idle())
+            .field("sar_amp_wait3", &self.sar_amp_wait3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AMP_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/amp_ctrl3.rs b/esp32p4/src/lp_adc/amp_ctrl3.rs
index 062523eb5d..9cfde99404 100644
--- a/esp32p4/src/lp_adc/amp_ctrl3.rs
+++ b/esp32p4/src/lp_adc/amp_ctrl3.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AMP_CTRL3")
-            .field(
-                "sar1_dac_xpd_fsm",
-                &format_args!("{}", self.sar1_dac_xpd_fsm().bits()),
-            )
-            .field(
-                "xpd_sar_amp_fsm",
-                &format_args!("{}", self.xpd_sar_amp_fsm().bits()),
-            )
-            .field(
-                "amp_rst_fb_fsm",
-                &format_args!("{}", self.amp_rst_fb_fsm().bits()),
-            )
-            .field(
-                "amp_short_ref_fsm",
-                &format_args!("{}", self.amp_short_ref_fsm().bits()),
-            )
-            .field(
-                "amp_short_ref_gnd_fsm",
-                &format_args!("{}", self.amp_short_ref_gnd_fsm().bits()),
-            )
-            .field(
-                "xpd_sar_fsm",
-                &format_args!("{}", self.xpd_sar_fsm().bits()),
-            )
-            .field(
-                "sar_rstb_fsm",
-                &format_args!("{}", self.sar_rstb_fsm().bits()),
-            )
+            .field("sar1_dac_xpd_fsm", &self.sar1_dac_xpd_fsm())
+            .field("xpd_sar_amp_fsm", &self.xpd_sar_amp_fsm())
+            .field("amp_rst_fb_fsm", &self.amp_rst_fb_fsm())
+            .field("amp_short_ref_fsm", &self.amp_short_ref_fsm())
+            .field("amp_short_ref_gnd_fsm", &self.amp_short_ref_gnd_fsm())
+            .field("xpd_sar_fsm", &self.xpd_sar_fsm())
+            .field("sar_rstb_fsm", &self.sar_rstb_fsm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AMP_CTRL3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/atten1.rs b/esp32p4/src/lp_adc/atten1.rs
index 284cb42282..09d49e90df 100644
--- a/esp32p4/src/lp_adc/atten1.rs
+++ b/esp32p4/src/lp_adc/atten1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ATTEN1")
-            .field("sar1_atten", &format_args!("{}", self.sar1_atten().bits()))
+            .field("sar1_atten", &self.sar1_atten())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ATTEN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 2-bit attenuation for each pad."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/atten2.rs b/esp32p4/src/lp_adc/atten2.rs
index b17d00d43f..7be9705ba8 100644
--- a/esp32p4/src/lp_adc/atten2.rs
+++ b/esp32p4/src/lp_adc/atten2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ATTEN2")
-            .field("sar2_atten", &format_args!("{}", self.sar2_atten().bits()))
+            .field("sar2_atten", &self.sar2_atten())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ATTEN2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 2-bit attenuation for each pad."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/cocpu_int_raw.rs b/esp32p4/src/lp_adc/cocpu_int_raw.rs
index 0a93ad5a32..0849d040f2 100644
--- a/esp32p4/src/lp_adc/cocpu_int_raw.rs
+++ b/esp32p4/src/lp_adc/cocpu_int_raw.rs
@@ -62,39 +62,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COCPU_INT_RAW")
-            .field(
-                "cocpu_saradc1_int_raw",
-                &format_args!("{}", self.cocpu_saradc1_int_raw().bit()),
-            )
-            .field(
-                "cocpu_saradc2_int_raw",
-                &format_args!("{}", self.cocpu_saradc2_int_raw().bit()),
-            )
+            .field("cocpu_saradc1_int_raw", &self.cocpu_saradc1_int_raw())
+            .field("cocpu_saradc2_int_raw", &self.cocpu_saradc2_int_raw())
             .field(
                 "cocpu_saradc1_error_int_raw",
-                &format_args!("{}", self.cocpu_saradc1_error_int_raw().bit()),
+                &self.cocpu_saradc1_error_int_raw(),
             )
             .field(
                 "cocpu_saradc2_error_int_raw",
-                &format_args!("{}", self.cocpu_saradc2_error_int_raw().bit()),
+                &self.cocpu_saradc2_error_int_raw(),
             )
             .field(
                 "cocpu_saradc1_wake_int_raw",
-                &format_args!("{}", self.cocpu_saradc1_wake_int_raw().bit()),
+                &self.cocpu_saradc1_wake_int_raw(),
             )
             .field(
                 "cocpu_saradc2_wake_int_raw",
-                &format_args!("{}", self.cocpu_saradc2_wake_int_raw().bit()),
+                &self.cocpu_saradc2_wake_int_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COCPU_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ADC1 Conversion is done, int raw."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/force_wpd_sar.rs b/esp32p4/src/lp_adc/force_wpd_sar.rs
index 8ee8562058..4bd0a3c689 100644
--- a/esp32p4/src/lp_adc/force_wpd_sar.rs
+++ b/esp32p4/src/lp_adc/force_wpd_sar.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FORCE_WPD_SAR")
-            .field(
-                "force_xpd_sar1",
-                &format_args!("{}", self.force_xpd_sar1().bits()),
-            )
-            .field(
-                "force_xpd_sar2",
-                &format_args!("{}", self.force_xpd_sar2().bits()),
-            )
+            .field("force_xpd_sar1", &self.force_xpd_sar1())
+            .field("force_xpd_sar2", &self.force_xpd_sar2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FORCE_WPD_SAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/int_ena.rs b/esp32p4/src/lp_adc/int_ena.rs
index 6856609ad4..c6978c33f7 100644
--- a/esp32p4/src/lp_adc/int_ena.rs
+++ b/esp32p4/src/lp_adc/int_ena.rs
@@ -62,39 +62,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "cocpu_saradc1_int_ena",
-                &format_args!("{}", self.cocpu_saradc1_int_ena().bit()),
-            )
-            .field(
-                "cocpu_saradc2_int_ena",
-                &format_args!("{}", self.cocpu_saradc2_int_ena().bit()),
-            )
+            .field("cocpu_saradc1_int_ena", &self.cocpu_saradc1_int_ena())
+            .field("cocpu_saradc2_int_ena", &self.cocpu_saradc2_int_ena())
             .field(
                 "cocpu_saradc1_error_int_ena",
-                &format_args!("{}", self.cocpu_saradc1_error_int_ena().bit()),
+                &self.cocpu_saradc1_error_int_ena(),
             )
             .field(
                 "cocpu_saradc2_error_int_ena",
-                &format_args!("{}", self.cocpu_saradc2_error_int_ena().bit()),
+                &self.cocpu_saradc2_error_int_ena(),
             )
             .field(
                 "cocpu_saradc1_wake_int_ena",
-                &format_args!("{}", self.cocpu_saradc1_wake_int_ena().bit()),
+                &self.cocpu_saradc1_wake_int_ena(),
             )
             .field(
                 "cocpu_saradc2_wake_int_ena",
-                &format_args!("{}", self.cocpu_saradc2_wake_int_ena().bit()),
+                &self.cocpu_saradc2_wake_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ADC1 Conversion is done, int enable."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/int_st.rs b/esp32p4/src/lp_adc/int_st.rs
index e7f545a60a..57aafb7854 100644
--- a/esp32p4/src/lp_adc/int_st.rs
+++ b/esp32p4/src/lp_adc/int_st.rs
@@ -48,39 +48,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "cocpu_saradc1_int_st",
-                &format_args!("{}", self.cocpu_saradc1_int_st().bit()),
-            )
-            .field(
-                "cocpu_saradc2_int_st",
-                &format_args!("{}", self.cocpu_saradc2_int_st().bit()),
-            )
+            .field("cocpu_saradc1_int_st", &self.cocpu_saradc1_int_st())
+            .field("cocpu_saradc2_int_st", &self.cocpu_saradc2_int_st())
             .field(
                 "cocpu_saradc1_error_int_st",
-                &format_args!("{}", self.cocpu_saradc1_error_int_st().bit()),
+                &self.cocpu_saradc1_error_int_st(),
             )
             .field(
                 "cocpu_saradc2_error_int_st",
-                &format_args!("{}", self.cocpu_saradc2_error_int_st().bit()),
+                &self.cocpu_saradc2_error_int_st(),
             )
             .field(
                 "cocpu_saradc1_wake_int_st",
-                &format_args!("{}", self.cocpu_saradc1_wake_int_st().bit()),
+                &self.cocpu_saradc1_wake_int_st(),
             )
             .field(
                 "cocpu_saradc2_wake_int_st",
-                &format_args!("{}", self.cocpu_saradc2_wake_int_st().bit()),
+                &self.cocpu_saradc2_wake_int_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/lp_adc/meas1_ctrl1.rs b/esp32p4/src/lp_adc/meas1_ctrl1.rs
index 080331352c..2bf6a3a346 100644
--- a/esp32p4/src/lp_adc/meas1_ctrl1.rs
+++ b/esp32p4/src/lp_adc/meas1_ctrl1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEAS1_CTRL1")
-            .field(
-                "force_xpd_amp",
-                &format_args!("{}", self.force_xpd_amp().bits()),
-            )
-            .field(
-                "amp_rst_fb_force",
-                &format_args!("{}", self.amp_rst_fb_force().bits()),
-            )
-            .field(
-                "amp_short_ref_force",
-                &format_args!("{}", self.amp_short_ref_force().bits()),
-            )
-            .field(
-                "amp_short_ref_gnd_force",
-                &format_args!("{}", self.amp_short_ref_gnd_force().bits()),
-            )
+            .field("force_xpd_amp", &self.force_xpd_amp())
+            .field("amp_rst_fb_force", &self.amp_rst_fb_force())
+            .field("amp_short_ref_force", &self.amp_short_ref_force())
+            .field("amp_short_ref_gnd_force", &self.amp_short_ref_gnd_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEAS1_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 24:25 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/meas1_ctrl2.rs b/esp32p4/src/lp_adc/meas1_ctrl2.rs
index 39b93f5034..8aad42e3d5 100644
--- a/esp32p4/src/lp_adc/meas1_ctrl2.rs
+++ b/esp32p4/src/lp_adc/meas1_ctrl2.rs
@@ -58,39 +58,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEAS1_CTRL2")
-            .field(
-                "meas1_data_sar",
-                &format_args!("{}", self.meas1_data_sar().bits()),
-            )
-            .field(
-                "meas1_done_sar",
-                &format_args!("{}", self.meas1_done_sar().bit()),
-            )
-            .field(
-                "meas1_start_sar",
-                &format_args!("{}", self.meas1_start_sar().bit()),
-            )
-            .field(
-                "meas1_start_force",
-                &format_args!("{}", self.meas1_start_force().bit()),
-            )
-            .field(
-                "sar1_en_pad",
-                &format_args!("{}", self.sar1_en_pad().bits()),
-            )
-            .field(
-                "sar1_en_pad_force",
-                &format_args!("{}", self.sar1_en_pad_force().bit()),
-            )
+            .field("meas1_data_sar", &self.meas1_data_sar())
+            .field("meas1_done_sar", &self.meas1_done_sar())
+            .field("meas1_start_sar", &self.meas1_start_sar())
+            .field("meas1_start_force", &self.meas1_start_force())
+            .field("sar1_en_pad", &self.sar1_en_pad())
+            .field("sar1_en_pad_force", &self.sar1_en_pad_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEAS1_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - SAR ADC1 controller (in RTC) starts conversion."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/meas1_mux.rs b/esp32p4/src/lp_adc/meas1_mux.rs
index 54306d8898..120f6cb01a 100644
--- a/esp32p4/src/lp_adc/meas1_mux.rs
+++ b/esp32p4/src/lp_adc/meas1_mux.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEAS1_MUX")
-            .field(
-                "sar1_dig_force",
-                &format_args!("{}", self.sar1_dig_force().bit()),
-            )
+            .field("sar1_dig_force", &self.sar1_dig_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEAS1_MUX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - 1: SAR ADC1 controlled by DIG ADC1 CTRL."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/meas2_ctrl1.rs b/esp32p4/src/lp_adc/meas2_ctrl1.rs
index b0e513c952..3bf5118cc5 100644
--- a/esp32p4/src/lp_adc/meas2_ctrl1.rs
+++ b/esp32p4/src/lp_adc/meas2_ctrl1.rs
@@ -78,47 +78,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEAS2_CTRL1")
-            .field(
-                "sar2_cntl_state",
-                &format_args!("{}", self.sar2_cntl_state().bits()),
-            )
-            .field(
-                "sar2_pwdet_cal_en",
-                &format_args!("{}", self.sar2_pwdet_cal_en().bit()),
-            )
-            .field(
-                "sar2_pkdet_cal_en",
-                &format_args!("{}", self.sar2_pkdet_cal_en().bit()),
-            )
-            .field(
-                "sar2_en_test",
-                &format_args!("{}", self.sar2_en_test().bit()),
-            )
-            .field(
-                "sar2_rstb_force",
-                &format_args!("{}", self.sar2_rstb_force().bits()),
-            )
-            .field(
-                "sar2_standby_wait",
-                &format_args!("{}", self.sar2_standby_wait().bits()),
-            )
-            .field(
-                "sar2_rstb_wait",
-                &format_args!("{}", self.sar2_rstb_wait().bits()),
-            )
-            .field(
-                "sar2_xpd_wait",
-                &format_args!("{}", self.sar2_xpd_wait().bits()),
-            )
+            .field("sar2_cntl_state", &self.sar2_cntl_state())
+            .field("sar2_pwdet_cal_en", &self.sar2_pwdet_cal_en())
+            .field("sar2_pkdet_cal_en", &self.sar2_pkdet_cal_en())
+            .field("sar2_en_test", &self.sar2_en_test())
+            .field("sar2_rstb_force", &self.sar2_rstb_force())
+            .field("sar2_standby_wait", &self.sar2_standby_wait())
+            .field("sar2_rstb_wait", &self.sar2_rstb_wait())
+            .field("sar2_xpd_wait", &self.sar2_xpd_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEAS2_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - RTC control pwdet enable."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/meas2_ctrl2.rs b/esp32p4/src/lp_adc/meas2_ctrl2.rs
index 1a847d11b8..dfb705f4d4 100644
--- a/esp32p4/src/lp_adc/meas2_ctrl2.rs
+++ b/esp32p4/src/lp_adc/meas2_ctrl2.rs
@@ -58,39 +58,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEAS2_CTRL2")
-            .field(
-                "meas2_data_sar",
-                &format_args!("{}", self.meas2_data_sar().bits()),
-            )
-            .field(
-                "meas2_done_sar",
-                &format_args!("{}", self.meas2_done_sar().bit()),
-            )
-            .field(
-                "meas2_start_sar",
-                &format_args!("{}", self.meas2_start_sar().bit()),
-            )
-            .field(
-                "meas2_start_force",
-                &format_args!("{}", self.meas2_start_force().bit()),
-            )
-            .field(
-                "sar2_en_pad",
-                &format_args!("{}", self.sar2_en_pad().bits()),
-            )
-            .field(
-                "sar2_en_pad_force",
-                &format_args!("{}", self.sar2_en_pad_force().bit()),
-            )
+            .field("meas2_data_sar", &self.meas2_data_sar())
+            .field("meas2_done_sar", &self.meas2_done_sar())
+            .field("meas2_start_sar", &self.meas2_start_sar())
+            .field("meas2_start_force", &self.meas2_start_force())
+            .field("sar2_en_pad", &self.sar2_en_pad())
+            .field("sar2_en_pad_force", &self.sar2_en_pad_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEAS2_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - SAR ADC2 controller (in RTC) starts conversion."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/meas2_mux.rs b/esp32p4/src/lp_adc/meas2_mux.rs
index b6067ddec8..1cdc8d92a2 100644
--- a/esp32p4/src/lp_adc/meas2_mux.rs
+++ b/esp32p4/src/lp_adc/meas2_mux.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEAS2_MUX")
-            .field(
-                "sar2_pwdet_cct",
-                &format_args!("{}", self.sar2_pwdet_cct().bits()),
-            )
-            .field(
-                "sar2_rtc_force",
-                &format_args!("{}", self.sar2_rtc_force().bit()),
-            )
+            .field("sar2_pwdet_cct", &self.sar2_pwdet_cct())
+            .field("sar2_rtc_force", &self.sar2_rtc_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEAS2_MUX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 28:30 - SAR2_PWDET_CCT."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/meas_status.rs b/esp32p4/src/lp_adc/meas_status.rs
index 12a88e1a66..f344ba9656 100644
--- a/esp32p4/src/lp_adc/meas_status.rs
+++ b/esp32p4/src/lp_adc/meas_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEAS_STATUS")
-            .field(
-                "saradc_meas_status",
-                &format_args!("{}", self.saradc_meas_status().bits()),
-            )
+            .field("saradc_meas_status", &self.saradc_meas_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEAS_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`meas_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEAS_STATUS_SPEC;
 impl crate::RegisterSpec for MEAS_STATUS_SPEC {
diff --git a/esp32p4/src/lp_adc/reader1_ctrl.rs b/esp32p4/src/lp_adc/reader1_ctrl.rs
index c338fbb75e..ebbc24d401 100644
--- a/esp32p4/src/lp_adc/reader1_ctrl.rs
+++ b/esp32p4/src/lp_adc/reader1_ctrl.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("READER1_CTRL")
-            .field(
-                "sar1_clk_div",
-                &format_args!("{}", self.sar1_clk_div().bits()),
-            )
-            .field(
-                "sar1_clk_gated",
-                &format_args!("{}", self.sar1_clk_gated().bit()),
-            )
-            .field(
-                "sar1_sample_num",
-                &format_args!("{}", self.sar1_sample_num().bits()),
-            )
-            .field(
-                "sar1_data_inv",
-                &format_args!("{}", self.sar1_data_inv().bit()),
-            )
-            .field("sar1_int_en", &format_args!("{}", self.sar1_int_en().bit()))
-            .field(
-                "sar1_en_pad_force_enable",
-                &format_args!("{}", self.sar1_en_pad_force_enable().bits()),
-            )
+            .field("sar1_clk_div", &self.sar1_clk_div())
+            .field("sar1_clk_gated", &self.sar1_clk_gated())
+            .field("sar1_sample_num", &self.sar1_sample_num())
+            .field("sar1_data_inv", &self.sar1_data_inv())
+            .field("sar1_int_en", &self.sar1_int_en())
+            .field("sar1_en_pad_force_enable", &self.sar1_en_pad_force_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<READER1_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Clock divider."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/reader1_status.rs b/esp32p4/src/lp_adc/reader1_status.rs
index 5f140d4ca5..6fdd5ba9b3 100644
--- a/esp32p4/src/lp_adc/reader1_status.rs
+++ b/esp32p4/src/lp_adc/reader1_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("READER1_STATUS")
-            .field(
-                "sar1_reader_status",
-                &format_args!("{}", self.sar1_reader_status().bits()),
-            )
+            .field("sar1_reader_status", &self.sar1_reader_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<READER1_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reader1_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct READER1_STATUS_SPEC;
 impl crate::RegisterSpec for READER1_STATUS_SPEC {
diff --git a/esp32p4/src/lp_adc/reader2_ctrl.rs b/esp32p4/src/lp_adc/reader2_ctrl.rs
index 181450cbb1..4699292368 100644
--- a/esp32p4/src/lp_adc/reader2_ctrl.rs
+++ b/esp32p4/src/lp_adc/reader2_ctrl.rs
@@ -71,40 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("READER2_CTRL")
-            .field(
-                "sar2_clk_div",
-                &format_args!("{}", self.sar2_clk_div().bits()),
-            )
-            .field(
-                "sar2_wait_arb_cycle",
-                &format_args!("{}", self.sar2_wait_arb_cycle().bits()),
-            )
-            .field(
-                "sar2_clk_gated",
-                &format_args!("{}", self.sar2_clk_gated().bit()),
-            )
-            .field(
-                "sar2_sample_num",
-                &format_args!("{}", self.sar2_sample_num().bits()),
-            )
-            .field(
-                "sar2_en_pad_force_enable",
-                &format_args!("{}", self.sar2_en_pad_force_enable().bits()),
-            )
-            .field(
-                "sar2_data_inv",
-                &format_args!("{}", self.sar2_data_inv().bit()),
-            )
-            .field("sar2_int_en", &format_args!("{}", self.sar2_int_en().bit()))
+            .field("sar2_clk_div", &self.sar2_clk_div())
+            .field("sar2_wait_arb_cycle", &self.sar2_wait_arb_cycle())
+            .field("sar2_clk_gated", &self.sar2_clk_gated())
+            .field("sar2_sample_num", &self.sar2_sample_num())
+            .field("sar2_en_pad_force_enable", &self.sar2_en_pad_force_enable())
+            .field("sar2_data_inv", &self.sar2_data_inv())
+            .field("sar2_int_en", &self.sar2_int_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<READER2_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Clock divider."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/reader2_status.rs b/esp32p4/src/lp_adc/reader2_status.rs
index e75b7b4f73..8f36b6c819 100644
--- a/esp32p4/src/lp_adc/reader2_status.rs
+++ b/esp32p4/src/lp_adc/reader2_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("READER2_STATUS")
-            .field(
-                "sar2_reader_status",
-                &format_args!("{}", self.sar2_reader_status().bits()),
-            )
+            .field("sar2_reader_status", &self.sar2_reader_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<READER2_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "N/A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reader2_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct READER2_STATUS_SPEC;
 impl crate::RegisterSpec for READER2_STATUS_SPEC {
diff --git a/esp32p4/src/lp_adc/reg_clken.rs b/esp32p4/src/lp_adc/reg_clken.rs
index 021c829a25..0da8018649 100644
--- a/esp32p4/src/lp_adc/reg_clken.rs
+++ b/esp32p4/src/lp_adc/reg_clken.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_CLKEN")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_CLKEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/rnd_eco_cs.rs b/esp32p4/src/lp_adc/rnd_eco_cs.rs
index 0ee5cda8ca..77b98c54df 100644
--- a/esp32p4/src/lp_adc/rnd_eco_cs.rs
+++ b/esp32p4/src/lp_adc/rnd_eco_cs.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_CS")
-            .field("rnd_eco_en", &format_args!("{}", self.rnd_eco_en().bit()))
-            .field(
-                "rnd_eco_result",
-                &format_args!("{}", self.rnd_eco_result().bit()),
-            )
+            .field("rnd_eco_en", &self.rnd_eco_en())
+            .field("rnd_eco_result", &self.rnd_eco_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_CS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/rnd_eco_high.rs b/esp32p4/src/lp_adc/rnd_eco_high.rs
index 46e6df17f4..a222a6c4bd 100644
--- a/esp32p4/src/lp_adc/rnd_eco_high.rs
+++ b/esp32p4/src/lp_adc/rnd_eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_HIGH")
-            .field(
-                "rnd_eco_high",
-                &format_args!("{}", self.rnd_eco_high().bits()),
-            )
+            .field("rnd_eco_high", &self.rnd_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/rnd_eco_low.rs b/esp32p4/src/lp_adc/rnd_eco_low.rs
index f61a420f49..109836b913 100644
--- a/esp32p4/src/lp_adc/rnd_eco_low.rs
+++ b/esp32p4/src/lp_adc/rnd_eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_LOW")
-            .field(
-                "rnd_eco_low",
-                &format_args!("{}", self.rnd_eco_low().bits()),
-            )
+            .field("rnd_eco_low", &self.rnd_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/sar1_hw_wakeup.rs b/esp32p4/src/lp_adc/sar1_hw_wakeup.rs
index 960c066190..0a749df1d0 100644
--- a/esp32p4/src/lp_adc/sar1_hw_wakeup.rs
+++ b/esp32p4/src/lp_adc/sar1_hw_wakeup.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_HW_WAKEUP")
-            .field(
-                "adc1_hw_read_en_i",
-                &format_args!("{}", self.adc1_hw_read_en_i().bit()),
-            )
-            .field(
-                "adc1_hw_read_rate_i",
-                &format_args!("{}", self.adc1_hw_read_rate_i().bits()),
-            )
+            .field("adc1_hw_read_en_i", &self.adc1_hw_read_en_i())
+            .field("adc1_hw_read_rate_i", &self.adc1_hw_read_rate_i())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_HW_WAKEUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable hardware automatic sampling."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/sar2_hw_wakeup.rs b/esp32p4/src/lp_adc/sar2_hw_wakeup.rs
index b5aaf671f8..599235407d 100644
--- a/esp32p4/src/lp_adc/sar2_hw_wakeup.rs
+++ b/esp32p4/src/lp_adc/sar2_hw_wakeup.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_HW_WAKEUP")
-            .field(
-                "adc2_hw_read_en_i",
-                &format_args!("{}", self.adc2_hw_read_en_i().bit()),
-            )
-            .field(
-                "adc2_hw_read_rate_i",
-                &format_args!("{}", self.adc2_hw_read_rate_i().bits()),
-            )
+            .field("adc2_hw_read_en_i", &self.adc2_hw_read_en_i())
+            .field("adc2_hw_read_rate_i", &self.adc2_hw_read_rate_i())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_HW_WAKEUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable hardware automatic sampling."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/wakeup1.rs b/esp32p4/src/lp_adc/wakeup1.rs
index 9b8d58f7e4..be84778acf 100644
--- a/esp32p4/src/lp_adc/wakeup1.rs
+++ b/esp32p4/src/lp_adc/wakeup1.rs
@@ -51,35 +51,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WAKEUP1")
-            .field(
-                "sar1_wakeup_th_low",
-                &format_args!("{}", self.sar1_wakeup_th_low().bits()),
-            )
-            .field(
-                "sar1_wakeup_th_high",
-                &format_args!("{}", self.sar1_wakeup_th_high().bits()),
-            )
+            .field("sar1_wakeup_th_low", &self.sar1_wakeup_th_low())
+            .field("sar1_wakeup_th_high", &self.sar1_wakeup_th_high())
             .field(
                 "sar1_wakeup_over_upper_th",
-                &format_args!("{}", self.sar1_wakeup_over_upper_th().bit()),
-            )
-            .field(
-                "sar1_wakeup_en",
-                &format_args!("{}", self.sar1_wakeup_en().bit()),
-            )
-            .field(
-                "sar1_wakeup_mode",
-                &format_args!("{}", self.sar1_wakeup_mode().bit()),
+                &self.sar1_wakeup_over_upper_th(),
             )
+            .field("sar1_wakeup_en", &self.sar1_wakeup_en())
+            .field("sar1_wakeup_mode", &self.sar1_wakeup_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WAKEUP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - Lower threshold."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/wakeup2.rs b/esp32p4/src/lp_adc/wakeup2.rs
index 437503bddf..edffaf8176 100644
--- a/esp32p4/src/lp_adc/wakeup2.rs
+++ b/esp32p4/src/lp_adc/wakeup2.rs
@@ -51,35 +51,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WAKEUP2")
-            .field(
-                "sar2_wakeup_th_low",
-                &format_args!("{}", self.sar2_wakeup_th_low().bits()),
-            )
-            .field(
-                "sar2_wakeup_th_high",
-                &format_args!("{}", self.sar2_wakeup_th_high().bits()),
-            )
+            .field("sar2_wakeup_th_low", &self.sar2_wakeup_th_low())
+            .field("sar2_wakeup_th_high", &self.sar2_wakeup_th_high())
             .field(
                 "sar2_wakeup_over_upper_th",
-                &format_args!("{}", self.sar2_wakeup_over_upper_th().bit()),
-            )
-            .field(
-                "sar2_wakeup_en",
-                &format_args!("{}", self.sar2_wakeup_en().bit()),
-            )
-            .field(
-                "sar2_wakeup_mode",
-                &format_args!("{}", self.sar2_wakeup_mode().bit()),
+                &self.sar2_wakeup_over_upper_th(),
             )
+            .field("sar2_wakeup_en", &self.sar2_wakeup_en())
+            .field("sar2_wakeup_mode", &self.sar2_wakeup_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WAKEUP2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - Lower threshold."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_adc/wakeup_sel.rs b/esp32p4/src/lp_adc/wakeup_sel.rs
index ad94dadbcc..394b370762 100644
--- a/esp32p4/src/lp_adc/wakeup_sel.rs
+++ b/esp32p4/src/lp_adc/wakeup_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WAKEUP_SEL")
-            .field(
-                "sar_wakeup_sel",
-                &format_args!("{}", self.sar_wakeup_sel().bit()),
-            )
+            .field("sar_wakeup_sel", &self.sar_wakeup_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WAKEUP_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 0: ADC1. 1: ADC2."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/bod_mode0_cntl.rs b/esp32p4/src/lp_ana/bod_mode0_cntl.rs
index 4eae1d17a9..51c9ae872d 100644
--- a/esp32p4/src/lp_ana/bod_mode0_cntl.rs
+++ b/esp32p4/src/lp_ana/bod_mode0_cntl.rs
@@ -82,45 +82,18 @@ impl core::fmt::Debug for R {
         f.debug_struct("BOD_MODE0_CNTL")
             .field(
                 "bod_mode0_close_flash_ena",
-                &format_args!("{}", self.bod_mode0_close_flash_ena().bit()),
-            )
-            .field(
-                "bod_mode0_pd_rf_ena",
-                &format_args!("{}", self.bod_mode0_pd_rf_ena().bit()),
-            )
-            .field(
-                "bod_mode0_intr_wait",
-                &format_args!("{}", self.bod_mode0_intr_wait().bits()),
-            )
-            .field(
-                "bod_mode0_reset_wait",
-                &format_args!("{}", self.bod_mode0_reset_wait().bits()),
-            )
-            .field(
-                "bod_mode0_cnt_clr",
-                &format_args!("{}", self.bod_mode0_cnt_clr().bit()),
-            )
-            .field(
-                "bod_mode0_intr_ena",
-                &format_args!("{}", self.bod_mode0_intr_ena().bit()),
-            )
-            .field(
-                "bod_mode0_reset_sel",
-                &format_args!("{}", self.bod_mode0_reset_sel().bit()),
-            )
-            .field(
-                "bod_mode0_reset_ena",
-                &format_args!("{}", self.bod_mode0_reset_ena().bit()),
+                &self.bod_mode0_close_flash_ena(),
             )
+            .field("bod_mode0_pd_rf_ena", &self.bod_mode0_pd_rf_ena())
+            .field("bod_mode0_intr_wait", &self.bod_mode0_intr_wait())
+            .field("bod_mode0_reset_wait", &self.bod_mode0_reset_wait())
+            .field("bod_mode0_cnt_clr", &self.bod_mode0_cnt_clr())
+            .field("bod_mode0_intr_ena", &self.bod_mode0_intr_ena())
+            .field("bod_mode0_reset_sel", &self.bod_mode0_reset_sel())
+            .field("bod_mode0_reset_ena", &self.bod_mode0_reset_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BOD_MODE0_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/bod_mode1_cntl.rs b/esp32p4/src/lp_ana/bod_mode1_cntl.rs
index daab8a45d0..3aa7fe569f 100644
--- a/esp32p4/src/lp_ana/bod_mode1_cntl.rs
+++ b/esp32p4/src/lp_ana/bod_mode1_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BOD_MODE1_CNTL")
-            .field(
-                "bod_mode1_reset_ena",
-                &format_args!("{}", self.bod_mode1_reset_ena().bit()),
-            )
+            .field("bod_mode1_reset_ena", &self.bod_mode1_reset_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BOD_MODE1_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/ck_glitch_cntl.rs b/esp32p4/src/lp_ana/ck_glitch_cntl.rs
index 603bbcf118..e33a2b6db7 100644
--- a/esp32p4/src/lp_ana/ck_glitch_cntl.rs
+++ b/esp32p4/src/lp_ana/ck_glitch_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CK_GLITCH_CNTL")
-            .field(
-                "ck_glitch_reset_ena",
-                &format_args!("{}", self.ck_glitch_reset_ena().bit()),
-            )
+            .field("ck_glitch_reset_ena", &self.ck_glitch_reset_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CK_GLITCH_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/date.rs b/esp32p4/src/lp_ana/date.rs
index f14dc91ecf..58d5c74681 100644
--- a/esp32p4/src/lp_ana/date.rs
+++ b/esp32p4/src/lp_ana/date.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "lp_ana_date",
-                &format_args!("{}", self.lp_ana_date().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("lp_ana_date", &self.lp_ana_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/fib_enable.rs b/esp32p4/src/lp_ana/fib_enable.rs
index 4b991a5896..e6b9fbc95c 100644
--- a/esp32p4/src/lp_ana/fib_enable.rs
+++ b/esp32p4/src/lp_ana/fib_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIB_ENABLE")
-            .field(
-                "ana_fib_ena",
-                &format_args!("{}", self.ana_fib_ena().bits()),
-            )
+            .field("ana_fib_ena", &self.ana_fib_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIB_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/int_ena.rs b/esp32p4/src/lp_ana/int_ena.rs
index 124fd27b7b..f7bc20cc03 100644
--- a/esp32p4/src/lp_ana/int_ena.rs
+++ b/esp32p4/src/lp_ana/int_ena.rs
@@ -53,32 +53,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "vddbat_charge_upvoltage",
-                &format_args!("{}", self.vddbat_charge_upvoltage().bit()),
-            )
+            .field("vddbat_charge_upvoltage", &self.vddbat_charge_upvoltage())
             .field(
                 "vddbat_charge_undervoltage",
-                &format_args!("{}", self.vddbat_charge_undervoltage().bit()),
+                &self.vddbat_charge_undervoltage(),
             )
-            .field(
-                "vddbat_upvoltage",
-                &format_args!("{}", self.vddbat_upvoltage().bit()),
-            )
-            .field(
-                "vddbat_undervoltage",
-                &format_args!("{}", self.vddbat_undervoltage().bit()),
-            )
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("vddbat_upvoltage", &self.vddbat_upvoltage())
+            .field("vddbat_undervoltage", &self.vddbat_undervoltage())
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/int_raw.rs b/esp32p4/src/lp_ana/int_raw.rs
index 7b62d3b106..9bdc535bcc 100644
--- a/esp32p4/src/lp_ana/int_raw.rs
+++ b/esp32p4/src/lp_ana/int_raw.rs
@@ -53,32 +53,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "vddbat_charge_upvoltage",
-                &format_args!("{}", self.vddbat_charge_upvoltage().bit()),
-            )
+            .field("vddbat_charge_upvoltage", &self.vddbat_charge_upvoltage())
             .field(
                 "vddbat_charge_undervoltage",
-                &format_args!("{}", self.vddbat_charge_undervoltage().bit()),
+                &self.vddbat_charge_undervoltage(),
             )
-            .field(
-                "vddbat_upvoltage",
-                &format_args!("{}", self.vddbat_upvoltage().bit()),
-            )
-            .field(
-                "vddbat_undervoltage",
-                &format_args!("{}", self.vddbat_undervoltage().bit()),
-            )
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("vddbat_upvoltage", &self.vddbat_upvoltage())
+            .field("vddbat_undervoltage", &self.vddbat_undervoltage())
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/int_st.rs b/esp32p4/src/lp_ana/int_st.rs
index 3d16eefff5..a7176f7ab7 100644
--- a/esp32p4/src/lp_ana/int_st.rs
+++ b/esp32p4/src/lp_ana/int_st.rs
@@ -41,32 +41,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "vddbat_charge_upvoltage",
-                &format_args!("{}", self.vddbat_charge_upvoltage().bit()),
-            )
+            .field("vddbat_charge_upvoltage", &self.vddbat_charge_upvoltage())
             .field(
                 "vddbat_charge_undervoltage",
-                &format_args!("{}", self.vddbat_charge_undervoltage().bit()),
+                &self.vddbat_charge_undervoltage(),
             )
-            .field(
-                "vddbat_upvoltage",
-                &format_args!("{}", self.vddbat_upvoltage().bit()),
-            )
-            .field(
-                "vddbat_undervoltage",
-                &format_args!("{}", self.vddbat_undervoltage().bit()),
-            )
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("vddbat_upvoltage", &self.vddbat_upvoltage())
+            .field("vddbat_undervoltage", &self.vddbat_undervoltage())
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/lp_ana/lp_int_ena.rs b/esp32p4/src/lp_ana/lp_int_ena.rs
index 20c74f7372..044e93357d 100644
--- a/esp32p4/src/lp_ana/lp_int_ena.rs
+++ b/esp32p4/src/lp_ana/lp_int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ENA")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/lp_int_raw.rs b/esp32p4/src/lp_ana/lp_int_raw.rs
index fcbabdea21..dde3b77a5d 100644
--- a/esp32p4/src/lp_ana/lp_int_raw.rs
+++ b/esp32p4/src/lp_ana/lp_int_raw.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_RAW")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/lp_int_st.rs b/esp32p4/src/lp_ana/lp_int_st.rs
index 8516622718..2e393bffab 100644
--- a/esp32p4/src/lp_ana/lp_int_st.rs
+++ b/esp32p4/src/lp_ana/lp_int_st.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ST")
-            .field("bod_mode0", &format_args!("{}", self.bod_mode0().bit()))
+            .field("bod_mode0", &self.bod_mode0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_INT_ST_SPEC;
 impl crate::RegisterSpec for LP_INT_ST_SPEC {
diff --git a/esp32p4/src/lp_ana/pg_glitch_cntl.rs b/esp32p4/src/lp_ana/pg_glitch_cntl.rs
index 19b273019e..747b98374c 100644
--- a/esp32p4/src/lp_ana/pg_glitch_cntl.rs
+++ b/esp32p4/src/lp_ana/pg_glitch_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PG_GLITCH_CNTL")
-            .field(
-                "power_glitch_reset_ena",
-                &format_args!("{}", self.power_glitch_reset_ena().bit()),
-            )
+            .field("power_glitch_reset_ena", &self.power_glitch_reset_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PG_GLITCH_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_ana_para.rs b/esp32p4/src/lp_ana/touch_ana_para.rs
index a715ff78bc..7b400d2de3 100644
--- a/esp32p4/src/lp_ana/touch_ana_para.rs
+++ b/esp32p4/src/lp_ana/touch_ana_para.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_ANA_PARA")
-            .field(
-                "touch_touch_buf_drv",
-                &format_args!("{}", self.touch_touch_buf_drv().bits()),
-            )
-            .field(
-                "touch_touch_en_cal",
-                &format_args!("{}", self.touch_touch_en_cal().bit()),
-            )
-            .field(
-                "touch_touch_dcap_cal",
-                &format_args!("{}", self.touch_touch_dcap_cal().bits()),
-            )
+            .field("touch_touch_buf_drv", &self.touch_touch_buf_drv())
+            .field("touch_touch_en_cal", &self.touch_touch_en_cal())
+            .field("touch_touch_dcap_cal", &self.touch_touch_dcap_cal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_ANA_PARA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_approach.rs b/esp32p4/src/lp_ana/touch_approach.rs
index 5a2d3d3fbc..93c7c55c8e 100644
--- a/esp32p4/src/lp_ana/touch_approach.rs
+++ b/esp32p4/src/lp_ana/touch_approach.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_APPROACH")
-            .field("pad0", &format_args!("{}", self.pad0().bits()))
-            .field("pad1", &format_args!("{}", self.pad1().bits()))
-            .field("pad2", &format_args!("{}", self.pad2().bits()))
-            .field(
-                "touch_slp_approach_en",
-                &format_args!("{}", self.touch_slp_approach_en().bit()),
-            )
+            .field("pad0", &self.pad0())
+            .field("pad1", &self.pad1())
+            .field("pad2", &self.pad2())
+            .field("touch_slp_approach_en", &self.touch_slp_approach_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_APPROACH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_approach_work_meas_num.rs b/esp32p4/src/lp_ana/touch_approach_work_meas_num.rs
index 4d2d1aa562..e4d0233a4d 100644
--- a/esp32p4/src/lp_ana/touch_approach_work_meas_num.rs
+++ b/esp32p4/src/lp_ana/touch_approach_work_meas_num.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_APPROACH_WORK_MEAS_NUM")
-            .field(
-                "touch_approach_meas_num2",
-                &format_args!("{}", self.touch_approach_meas_num2().bits()),
-            )
-            .field(
-                "touch_approach_meas_num1",
-                &format_args!("{}", self.touch_approach_meas_num1().bits()),
-            )
-            .field(
-                "touch_approach_meas_num0",
-                &format_args!("{}", self.touch_approach_meas_num0().bits()),
-            )
+            .field("touch_approach_meas_num2", &self.touch_approach_meas_num2())
+            .field("touch_approach_meas_num1", &self.touch_approach_meas_num1())
+            .field("touch_approach_meas_num0", &self.touch_approach_meas_num0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_APPROACH_WORK_MEAS_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_filter1.rs b/esp32p4/src/lp_ana/touch_filter1.rs
index 30eadf128d..5f150a459d 100644
--- a/esp32p4/src/lp_ana/touch_filter1.rs
+++ b/esp32p4/src/lp_ana/touch_filter1.rs
@@ -109,57 +109,21 @@ impl core::fmt::Debug for R {
         f.debug_struct("TOUCH_FILTER1")
             .field(
                 "touch_neg_noise_disupdate_baseline_en",
-                &format_args!("{}", self.touch_neg_noise_disupdate_baseline_en().bit()),
-            )
-            .field(
-                "touch_hysteresis",
-                &format_args!("{}", self.touch_hysteresis().bits()),
-            )
-            .field(
-                "touch_neg_noise_thres",
-                &format_args!("{}", self.touch_neg_noise_thres().bits()),
-            )
-            .field(
-                "touch_noise_thres",
-                &format_args!("{}", self.touch_noise_thres().bits()),
-            )
-            .field(
-                "touch_smooth_lvl",
-                &format_args!("{}", self.touch_smooth_lvl().bits()),
-            )
-            .field(
-                "touch_jitter_step",
-                &format_args!("{}", self.touch_jitter_step().bits()),
-            )
-            .field(
-                "touch_filter_mode",
-                &format_args!("{}", self.touch_filter_mode().bits()),
-            )
-            .field(
-                "touch_filter_en",
-                &format_args!("{}", self.touch_filter_en().bit()),
-            )
-            .field(
-                "touch_neg_noise_limit",
-                &format_args!("{}", self.touch_neg_noise_limit().bits()),
-            )
-            .field(
-                "touch_approach_limit",
-                &format_args!("{}", self.touch_approach_limit().bits()),
-            )
-            .field(
-                "touch_debounce_limit",
-                &format_args!("{}", self.touch_debounce_limit().bits()),
+                &self.touch_neg_noise_disupdate_baseline_en(),
             )
+            .field("touch_hysteresis", &self.touch_hysteresis())
+            .field("touch_neg_noise_thres", &self.touch_neg_noise_thres())
+            .field("touch_noise_thres", &self.touch_noise_thres())
+            .field("touch_smooth_lvl", &self.touch_smooth_lvl())
+            .field("touch_jitter_step", &self.touch_jitter_step())
+            .field("touch_filter_mode", &self.touch_filter_mode())
+            .field("touch_filter_en", &self.touch_filter_en())
+            .field("touch_neg_noise_limit", &self.touch_neg_noise_limit())
+            .field("touch_approach_limit", &self.touch_approach_limit())
+            .field("touch_debounce_limit", &self.touch_debounce_limit())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_FILTER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_filter2.rs b/esp32p4/src/lp_ana/touch_filter2.rs
index 15653027c4..544bb57544 100644
--- a/esp32p4/src/lp_ana/touch_filter2.rs
+++ b/esp32p4/src/lp_ana/touch_filter2.rs
@@ -35,27 +35,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_FILTER2")
-            .field(
-                "touch_outen",
-                &format_args!("{}", self.touch_outen().bits()),
-            )
-            .field(
-                "touch_bypass_noise_thres",
-                &format_args!("{}", self.touch_bypass_noise_thres().bit()),
-            )
+            .field("touch_outen", &self.touch_outen())
+            .field("touch_bypass_noise_thres", &self.touch_bypass_noise_thres())
             .field(
                 "touch_bypass_neg_noise_thres",
-                &format_args!("{}", self.touch_bypass_neg_noise_thres().bit()),
+                &self.touch_bypass_neg_noise_thres(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_FILTER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 15:29 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_filter3.rs b/esp32p4/src/lp_ana/touch_filter3.rs
index f223a5f302..bf8fc3a76d 100644
--- a/esp32p4/src/lp_ana/touch_filter3.rs
+++ b/esp32p4/src/lp_ana/touch_filter3.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_FILTER3")
-            .field(
-                "touch_baseline_sw",
-                &format_args!("{}", self.touch_baseline_sw().bits()),
-            )
+            .field("touch_baseline_sw", &self.touch_baseline_sw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_FILTER3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_freq0_scan_para.rs b/esp32p4/src/lp_ana/touch_freq0_scan_para.rs
index cad0f70bff..e466aa4606 100644
--- a/esp32p4/src/lp_ana/touch_freq0_scan_para.rs
+++ b/esp32p4/src/lp_ana/touch_freq0_scan_para.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_FREQ0_SCAN_PARA")
-            .field(
-                "touch_freq0_dcap_lpf",
-                &format_args!("{}", self.touch_freq0_dcap_lpf().bits()),
-            )
-            .field(
-                "touch_freq0_dres_lpf",
-                &format_args!("{}", self.touch_freq0_dres_lpf().bits()),
-            )
-            .field(
-                "touch_freq0_drv_ls",
-                &format_args!("{}", self.touch_freq0_drv_ls().bits()),
-            )
-            .field(
-                "touch_freq0_drv_hs",
-                &format_args!("{}", self.touch_freq0_drv_hs().bits()),
-            )
-            .field(
-                "touch_freq0_dbias",
-                &format_args!("{}", self.touch_freq0_dbias().bits()),
-            )
+            .field("touch_freq0_dcap_lpf", &self.touch_freq0_dcap_lpf())
+            .field("touch_freq0_dres_lpf", &self.touch_freq0_dres_lpf())
+            .field("touch_freq0_drv_ls", &self.touch_freq0_drv_ls())
+            .field("touch_freq0_drv_hs", &self.touch_freq0_drv_hs())
+            .field("touch_freq0_dbias", &self.touch_freq0_dbias())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_FREQ0_SCAN_PARA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_freq1_scan_para.rs b/esp32p4/src/lp_ana/touch_freq1_scan_para.rs
index f3624bad77..0eb66b96c2 100644
--- a/esp32p4/src/lp_ana/touch_freq1_scan_para.rs
+++ b/esp32p4/src/lp_ana/touch_freq1_scan_para.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_FREQ1_SCAN_PARA")
-            .field(
-                "touch_freq1_dcap_lpf",
-                &format_args!("{}", self.touch_freq1_dcap_lpf().bits()),
-            )
-            .field(
-                "touch_freq1_dres_lpf",
-                &format_args!("{}", self.touch_freq1_dres_lpf().bits()),
-            )
-            .field(
-                "touch_freq1_drv_ls",
-                &format_args!("{}", self.touch_freq1_drv_ls().bits()),
-            )
-            .field(
-                "touch_freq1_drv_hs",
-                &format_args!("{}", self.touch_freq1_drv_hs().bits()),
-            )
-            .field(
-                "touch_freq1_dbias",
-                &format_args!("{}", self.touch_freq1_dbias().bits()),
-            )
+            .field("touch_freq1_dcap_lpf", &self.touch_freq1_dcap_lpf())
+            .field("touch_freq1_dres_lpf", &self.touch_freq1_dres_lpf())
+            .field("touch_freq1_drv_ls", &self.touch_freq1_drv_ls())
+            .field("touch_freq1_drv_hs", &self.touch_freq1_drv_hs())
+            .field("touch_freq1_dbias", &self.touch_freq1_dbias())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_FREQ1_SCAN_PARA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_freq2_scan_para.rs b/esp32p4/src/lp_ana/touch_freq2_scan_para.rs
index 7d10b90997..723e261314 100644
--- a/esp32p4/src/lp_ana/touch_freq2_scan_para.rs
+++ b/esp32p4/src/lp_ana/touch_freq2_scan_para.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_FREQ2_SCAN_PARA")
-            .field(
-                "touch_freq2_dcap_lpf",
-                &format_args!("{}", self.touch_freq2_dcap_lpf().bits()),
-            )
-            .field(
-                "touch_freq2_dres_lpf",
-                &format_args!("{}", self.touch_freq2_dres_lpf().bits()),
-            )
-            .field(
-                "touch_freq2_drv_ls",
-                &format_args!("{}", self.touch_freq2_drv_ls().bits()),
-            )
-            .field(
-                "touch_freq2_drv_hs",
-                &format_args!("{}", self.touch_freq2_drv_hs().bits()),
-            )
-            .field(
-                "touch_freq2_dbias",
-                &format_args!("{}", self.touch_freq2_dbias().bits()),
-            )
+            .field("touch_freq2_dcap_lpf", &self.touch_freq2_dcap_lpf())
+            .field("touch_freq2_dres_lpf", &self.touch_freq2_dres_lpf())
+            .field("touch_freq2_drv_ls", &self.touch_freq2_drv_ls())
+            .field("touch_freq2_drv_hs", &self.touch_freq2_drv_hs())
+            .field("touch_freq2_dbias", &self.touch_freq2_dbias())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_FREQ2_SCAN_PARA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_mux0.rs b/esp32p4/src/lp_ana/touch_mux0.rs
index 6e4e8c4a09..9506b85d1b 100644
--- a/esp32p4/src/lp_ana/touch_mux0.rs
+++ b/esp32p4/src/lp_ana/touch_mux0.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_MUX0")
-            .field(
-                "touch_data_sel",
-                &format_args!("{}", self.touch_data_sel().bits()),
-            )
-            .field(
-                "touch_freq_sel",
-                &format_args!("{}", self.touch_freq_sel().bits()),
-            )
-            .field(
-                "touch_bufsel",
-                &format_args!("{}", self.touch_bufsel().bits()),
-            )
-            .field(
-                "touch_done_en",
-                &format_args!("{}", self.touch_done_en().bit()),
-            )
-            .field(
-                "touch_done_force",
-                &format_args!("{}", self.touch_done_force().bit()),
-            )
-            .field(
-                "touch_fsm_en",
-                &format_args!("{}", self.touch_fsm_en().bit()),
-            )
-            .field(
-                "touch_start_en",
-                &format_args!("{}", self.touch_start_en().bit()),
-            )
-            .field(
-                "touch_start_force",
-                &format_args!("{}", self.touch_start_force().bit()),
-            )
+            .field("touch_data_sel", &self.touch_data_sel())
+            .field("touch_freq_sel", &self.touch_freq_sel())
+            .field("touch_bufsel", &self.touch_bufsel())
+            .field("touch_done_en", &self.touch_done_en())
+            .field("touch_done_force", &self.touch_done_force())
+            .field("touch_fsm_en", &self.touch_fsm_en())
+            .field("touch_start_en", &self.touch_start_en())
+            .field("touch_start_force", &self.touch_start_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_MUX0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:9 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_mux1.rs b/esp32p4/src/lp_ana/touch_mux1.rs
index 323ad7a7f2..89ec91171f 100644
--- a/esp32p4/src/lp_ana/touch_mux1.rs
+++ b/esp32p4/src/lp_ana/touch_mux1.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_MUX1")
-            .field(
-                "touch_start",
-                &format_args!("{}", self.touch_start().bits()),
-            )
-            .field("touch_xpd", &format_args!("{}", self.touch_xpd().bits()))
+            .field("touch_start", &self.touch_start())
+            .field("touch_xpd", &self.touch_xpd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_MUX1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad0_th0.rs b/esp32p4/src/lp_ana/touch_pad0_th0.rs
index 292f9e8c0e..8eee9802a8 100644
--- a/esp32p4/src/lp_ana/touch_pad0_th0.rs
+++ b/esp32p4/src/lp_ana/touch_pad0_th0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD0_TH0")
-            .field(
-                "touch_pad0_th0",
-                &format_args!("{}", self.touch_pad0_th0().bits()),
-            )
+            .field("touch_pad0_th0", &self.touch_pad0_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD0_TH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad0_th1.rs b/esp32p4/src/lp_ana/touch_pad0_th1.rs
index 8275d13725..2a4033d312 100644
--- a/esp32p4/src/lp_ana/touch_pad0_th1.rs
+++ b/esp32p4/src/lp_ana/touch_pad0_th1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD0_TH1")
-            .field(
-                "touch_pad0_th1",
-                &format_args!("{}", self.touch_pad0_th1().bits()),
-            )
+            .field("touch_pad0_th1", &self.touch_pad0_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD0_TH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad0_th2.rs b/esp32p4/src/lp_ana/touch_pad0_th2.rs
index 6b0fe05b57..0741bb3b60 100644
--- a/esp32p4/src/lp_ana/touch_pad0_th2.rs
+++ b/esp32p4/src/lp_ana/touch_pad0_th2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD0_TH2")
-            .field(
-                "touch_pad0_th2",
-                &format_args!("{}", self.touch_pad0_th2().bits()),
-            )
+            .field("touch_pad0_th2", &self.touch_pad0_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD0_TH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad10_th0.rs b/esp32p4/src/lp_ana/touch_pad10_th0.rs
index aa6027c6f1..979262ca99 100644
--- a/esp32p4/src/lp_ana/touch_pad10_th0.rs
+++ b/esp32p4/src/lp_ana/touch_pad10_th0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD10_TH0")
-            .field(
-                "touch_pad10_th0",
-                &format_args!("{}", self.touch_pad10_th0().bits()),
-            )
+            .field("touch_pad10_th0", &self.touch_pad10_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD10_TH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad10_th1.rs b/esp32p4/src/lp_ana/touch_pad10_th1.rs
index 077f4f58df..9a6dc2ee8e 100644
--- a/esp32p4/src/lp_ana/touch_pad10_th1.rs
+++ b/esp32p4/src/lp_ana/touch_pad10_th1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD10_TH1")
-            .field(
-                "touch_pad10_th1",
-                &format_args!("{}", self.touch_pad10_th1().bits()),
-            )
+            .field("touch_pad10_th1", &self.touch_pad10_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD10_TH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad10_th2.rs b/esp32p4/src/lp_ana/touch_pad10_th2.rs
index 682349eb31..3dfef0a814 100644
--- a/esp32p4/src/lp_ana/touch_pad10_th2.rs
+++ b/esp32p4/src/lp_ana/touch_pad10_th2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD10_TH2")
-            .field(
-                "touch_pad10_th2",
-                &format_args!("{}", self.touch_pad10_th2().bits()),
-            )
+            .field("touch_pad10_th2", &self.touch_pad10_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD10_TH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad11_th0.rs b/esp32p4/src/lp_ana/touch_pad11_th0.rs
index 588dfb4bfd..e88c972e0b 100644
--- a/esp32p4/src/lp_ana/touch_pad11_th0.rs
+++ b/esp32p4/src/lp_ana/touch_pad11_th0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD11_TH0")
-            .field(
-                "touch_pad11_th0",
-                &format_args!("{}", self.touch_pad11_th0().bits()),
-            )
+            .field("touch_pad11_th0", &self.touch_pad11_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD11_TH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad11_th1.rs b/esp32p4/src/lp_ana/touch_pad11_th1.rs
index c693f72a4a..8374df9c57 100644
--- a/esp32p4/src/lp_ana/touch_pad11_th1.rs
+++ b/esp32p4/src/lp_ana/touch_pad11_th1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD11_TH1")
-            .field(
-                "touch_pad11_th1",
-                &format_args!("{}", self.touch_pad11_th1().bits()),
-            )
+            .field("touch_pad11_th1", &self.touch_pad11_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD11_TH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad11_th2.rs b/esp32p4/src/lp_ana/touch_pad11_th2.rs
index 8c7e88d808..278711d126 100644
--- a/esp32p4/src/lp_ana/touch_pad11_th2.rs
+++ b/esp32p4/src/lp_ana/touch_pad11_th2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD11_TH2")
-            .field(
-                "touch_pad11_th2",
-                &format_args!("{}", self.touch_pad11_th2().bits()),
-            )
+            .field("touch_pad11_th2", &self.touch_pad11_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD11_TH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad12_th0.rs b/esp32p4/src/lp_ana/touch_pad12_th0.rs
index 22c8196e95..ac1619787d 100644
--- a/esp32p4/src/lp_ana/touch_pad12_th0.rs
+++ b/esp32p4/src/lp_ana/touch_pad12_th0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD12_TH0")
-            .field(
-                "touch_pad12_th0",
-                &format_args!("{}", self.touch_pad12_th0().bits()),
-            )
+            .field("touch_pad12_th0", &self.touch_pad12_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD12_TH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad12_th1.rs b/esp32p4/src/lp_ana/touch_pad12_th1.rs
index e371372d4e..4b3155689b 100644
--- a/esp32p4/src/lp_ana/touch_pad12_th1.rs
+++ b/esp32p4/src/lp_ana/touch_pad12_th1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD12_TH1")
-            .field(
-                "touch_pad12_th1",
-                &format_args!("{}", self.touch_pad12_th1().bits()),
-            )
+            .field("touch_pad12_th1", &self.touch_pad12_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD12_TH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad12_th2.rs b/esp32p4/src/lp_ana/touch_pad12_th2.rs
index d47c794051..9cfaba7d3f 100644
--- a/esp32p4/src/lp_ana/touch_pad12_th2.rs
+++ b/esp32p4/src/lp_ana/touch_pad12_th2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD12_TH2")
-            .field(
-                "touch_pad12_th2",
-                &format_args!("{}", self.touch_pad12_th2().bits()),
-            )
+            .field("touch_pad12_th2", &self.touch_pad12_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD12_TH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad13_th0.rs b/esp32p4/src/lp_ana/touch_pad13_th0.rs
index d625f6d266..560c236815 100644
--- a/esp32p4/src/lp_ana/touch_pad13_th0.rs
+++ b/esp32p4/src/lp_ana/touch_pad13_th0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD13_TH0")
-            .field(
-                "touch_pad13_th0",
-                &format_args!("{}", self.touch_pad13_th0().bits()),
-            )
+            .field("touch_pad13_th0", &self.touch_pad13_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD13_TH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad13_th1.rs b/esp32p4/src/lp_ana/touch_pad13_th1.rs
index ead3afedb3..7727d62e62 100644
--- a/esp32p4/src/lp_ana/touch_pad13_th1.rs
+++ b/esp32p4/src/lp_ana/touch_pad13_th1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD13_TH1")
-            .field(
-                "touch_pad13_th1",
-                &format_args!("{}", self.touch_pad13_th1().bits()),
-            )
+            .field("touch_pad13_th1", &self.touch_pad13_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD13_TH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad13_th2.rs b/esp32p4/src/lp_ana/touch_pad13_th2.rs
index 1d77ec5ca8..8b53bf04de 100644
--- a/esp32p4/src/lp_ana/touch_pad13_th2.rs
+++ b/esp32p4/src/lp_ana/touch_pad13_th2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD13_TH2")
-            .field(
-                "touch_pad13_th2",
-                &format_args!("{}", self.touch_pad13_th2().bits()),
-            )
+            .field("touch_pad13_th2", &self.touch_pad13_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD13_TH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad14_th0.rs b/esp32p4/src/lp_ana/touch_pad14_th0.rs
index 19dc110dc5..ffdf5f60d7 100644
--- a/esp32p4/src/lp_ana/touch_pad14_th0.rs
+++ b/esp32p4/src/lp_ana/touch_pad14_th0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD14_TH0")
-            .field(
-                "touch_pad14_th0",
-                &format_args!("{}", self.touch_pad14_th0().bits()),
-            )
+            .field("touch_pad14_th0", &self.touch_pad14_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD14_TH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad14_th1.rs b/esp32p4/src/lp_ana/touch_pad14_th1.rs
index 14456cd813..9e8efb34ce 100644
--- a/esp32p4/src/lp_ana/touch_pad14_th1.rs
+++ b/esp32p4/src/lp_ana/touch_pad14_th1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD14_TH1")
-            .field(
-                "touch_pad14_th1",
-                &format_args!("{}", self.touch_pad14_th1().bits()),
-            )
+            .field("touch_pad14_th1", &self.touch_pad14_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD14_TH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad14_th2.rs b/esp32p4/src/lp_ana/touch_pad14_th2.rs
index 9a3cb59f1e..0d5cabc9dc 100644
--- a/esp32p4/src/lp_ana/touch_pad14_th2.rs
+++ b/esp32p4/src/lp_ana/touch_pad14_th2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD14_TH2")
-            .field(
-                "touch_pad14_th2",
-                &format_args!("{}", self.touch_pad14_th2().bits()),
-            )
+            .field("touch_pad14_th2", &self.touch_pad14_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD14_TH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad1_th0.rs b/esp32p4/src/lp_ana/touch_pad1_th0.rs
index 484f241cb1..e1294649c6 100644
--- a/esp32p4/src/lp_ana/touch_pad1_th0.rs
+++ b/esp32p4/src/lp_ana/touch_pad1_th0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD1_TH0")
-            .field(
-                "touch_pad1_th0",
-                &format_args!("{}", self.touch_pad1_th0().bits()),
-            )
+            .field("touch_pad1_th0", &self.touch_pad1_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD1_TH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad1_th1.rs b/esp32p4/src/lp_ana/touch_pad1_th1.rs
index 3396af271b..025f30a9ab 100644
--- a/esp32p4/src/lp_ana/touch_pad1_th1.rs
+++ b/esp32p4/src/lp_ana/touch_pad1_th1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD1_TH1")
-            .field(
-                "touch_pad1_th1",
-                &format_args!("{}", self.touch_pad1_th1().bits()),
-            )
+            .field("touch_pad1_th1", &self.touch_pad1_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD1_TH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad1_th2.rs b/esp32p4/src/lp_ana/touch_pad1_th2.rs
index ddd57109b1..1a6934db55 100644
--- a/esp32p4/src/lp_ana/touch_pad1_th2.rs
+++ b/esp32p4/src/lp_ana/touch_pad1_th2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD1_TH2")
-            .field(
-                "touch_pad1_th2",
-                &format_args!("{}", self.touch_pad1_th2().bits()),
-            )
+            .field("touch_pad1_th2", &self.touch_pad1_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD1_TH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad2_th0.rs b/esp32p4/src/lp_ana/touch_pad2_th0.rs
index f35d8b06e0..b92cf311cb 100644
--- a/esp32p4/src/lp_ana/touch_pad2_th0.rs
+++ b/esp32p4/src/lp_ana/touch_pad2_th0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD2_TH0")
-            .field(
-                "touch_pad2_th0",
-                &format_args!("{}", self.touch_pad2_th0().bits()),
-            )
+            .field("touch_pad2_th0", &self.touch_pad2_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD2_TH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad2_th1.rs b/esp32p4/src/lp_ana/touch_pad2_th1.rs
index 9df6da8d85..2ee9fca751 100644
--- a/esp32p4/src/lp_ana/touch_pad2_th1.rs
+++ b/esp32p4/src/lp_ana/touch_pad2_th1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD2_TH1")
-            .field(
-                "touch_pad2_th1",
-                &format_args!("{}", self.touch_pad2_th1().bits()),
-            )
+            .field("touch_pad2_th1", &self.touch_pad2_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD2_TH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad2_th2.rs b/esp32p4/src/lp_ana/touch_pad2_th2.rs
index 6fdcda7056..cce6f424d1 100644
--- a/esp32p4/src/lp_ana/touch_pad2_th2.rs
+++ b/esp32p4/src/lp_ana/touch_pad2_th2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD2_TH2")
-            .field(
-                "touch_pad2_th2",
-                &format_args!("{}", self.touch_pad2_th2().bits()),
-            )
+            .field("touch_pad2_th2", &self.touch_pad2_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD2_TH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad3_th0.rs b/esp32p4/src/lp_ana/touch_pad3_th0.rs
index 99509c842b..c90fe5f545 100644
--- a/esp32p4/src/lp_ana/touch_pad3_th0.rs
+++ b/esp32p4/src/lp_ana/touch_pad3_th0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD3_TH0")
-            .field(
-                "touch_pad3_th0",
-                &format_args!("{}", self.touch_pad3_th0().bits()),
-            )
+            .field("touch_pad3_th0", &self.touch_pad3_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD3_TH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad3_th1.rs b/esp32p4/src/lp_ana/touch_pad3_th1.rs
index 2e81b28cd2..c904b3134c 100644
--- a/esp32p4/src/lp_ana/touch_pad3_th1.rs
+++ b/esp32p4/src/lp_ana/touch_pad3_th1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD3_TH1")
-            .field(
-                "touch_pad3_th1",
-                &format_args!("{}", self.touch_pad3_th1().bits()),
-            )
+            .field("touch_pad3_th1", &self.touch_pad3_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD3_TH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad3_th2.rs b/esp32p4/src/lp_ana/touch_pad3_th2.rs
index 232ab03a65..bb3f1b6be7 100644
--- a/esp32p4/src/lp_ana/touch_pad3_th2.rs
+++ b/esp32p4/src/lp_ana/touch_pad3_th2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD3_TH2")
-            .field(
-                "touch_pad3_th2",
-                &format_args!("{}", self.touch_pad3_th2().bits()),
-            )
+            .field("touch_pad3_th2", &self.touch_pad3_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD3_TH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad4_th0.rs b/esp32p4/src/lp_ana/touch_pad4_th0.rs
index 8f2f9d1411..88d857816b 100644
--- a/esp32p4/src/lp_ana/touch_pad4_th0.rs
+++ b/esp32p4/src/lp_ana/touch_pad4_th0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD4_TH0")
-            .field(
-                "touch_pad4_th0",
-                &format_args!("{}", self.touch_pad4_th0().bits()),
-            )
+            .field("touch_pad4_th0", &self.touch_pad4_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD4_TH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad4_th1.rs b/esp32p4/src/lp_ana/touch_pad4_th1.rs
index 92a915893a..b24b5715b9 100644
--- a/esp32p4/src/lp_ana/touch_pad4_th1.rs
+++ b/esp32p4/src/lp_ana/touch_pad4_th1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD4_TH1")
-            .field(
-                "touch_pad4_th1",
-                &format_args!("{}", self.touch_pad4_th1().bits()),
-            )
+            .field("touch_pad4_th1", &self.touch_pad4_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD4_TH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad4_th2.rs b/esp32p4/src/lp_ana/touch_pad4_th2.rs
index de65e87caf..095d62b3d7 100644
--- a/esp32p4/src/lp_ana/touch_pad4_th2.rs
+++ b/esp32p4/src/lp_ana/touch_pad4_th2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD4_TH2")
-            .field(
-                "touch_pad4_th2",
-                &format_args!("{}", self.touch_pad4_th2().bits()),
-            )
+            .field("touch_pad4_th2", &self.touch_pad4_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD4_TH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad5_th0.rs b/esp32p4/src/lp_ana/touch_pad5_th0.rs
index d523c1975d..516ab0b304 100644
--- a/esp32p4/src/lp_ana/touch_pad5_th0.rs
+++ b/esp32p4/src/lp_ana/touch_pad5_th0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD5_TH0")
-            .field(
-                "touch_pad5_th0",
-                &format_args!("{}", self.touch_pad5_th0().bits()),
-            )
+            .field("touch_pad5_th0", &self.touch_pad5_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD5_TH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad5_th1.rs b/esp32p4/src/lp_ana/touch_pad5_th1.rs
index 6b76d5ecd9..962dc1047b 100644
--- a/esp32p4/src/lp_ana/touch_pad5_th1.rs
+++ b/esp32p4/src/lp_ana/touch_pad5_th1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD5_TH1")
-            .field(
-                "touch_pad5_th1",
-                &format_args!("{}", self.touch_pad5_th1().bits()),
-            )
+            .field("touch_pad5_th1", &self.touch_pad5_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD5_TH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad5_th2.rs b/esp32p4/src/lp_ana/touch_pad5_th2.rs
index 76871f1b33..dfa9178db5 100644
--- a/esp32p4/src/lp_ana/touch_pad5_th2.rs
+++ b/esp32p4/src/lp_ana/touch_pad5_th2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD5_TH2")
-            .field(
-                "touch_pad5_th2",
-                &format_args!("{}", self.touch_pad5_th2().bits()),
-            )
+            .field("touch_pad5_th2", &self.touch_pad5_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD5_TH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad6_th0.rs b/esp32p4/src/lp_ana/touch_pad6_th0.rs
index bc2cedaff1..cdea20fec3 100644
--- a/esp32p4/src/lp_ana/touch_pad6_th0.rs
+++ b/esp32p4/src/lp_ana/touch_pad6_th0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD6_TH0")
-            .field(
-                "touch_pad6_th0",
-                &format_args!("{}", self.touch_pad6_th0().bits()),
-            )
+            .field("touch_pad6_th0", &self.touch_pad6_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD6_TH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad6_th1.rs b/esp32p4/src/lp_ana/touch_pad6_th1.rs
index ac7c49874d..d06945df3f 100644
--- a/esp32p4/src/lp_ana/touch_pad6_th1.rs
+++ b/esp32p4/src/lp_ana/touch_pad6_th1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD6_TH1")
-            .field(
-                "touch_pad6_th1",
-                &format_args!("{}", self.touch_pad6_th1().bits()),
-            )
+            .field("touch_pad6_th1", &self.touch_pad6_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD6_TH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad6_th2.rs b/esp32p4/src/lp_ana/touch_pad6_th2.rs
index cf06e7d4d8..32ea004888 100644
--- a/esp32p4/src/lp_ana/touch_pad6_th2.rs
+++ b/esp32p4/src/lp_ana/touch_pad6_th2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD6_TH2")
-            .field(
-                "touch_pad6_th2",
-                &format_args!("{}", self.touch_pad6_th2().bits()),
-            )
+            .field("touch_pad6_th2", &self.touch_pad6_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD6_TH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad7_th0.rs b/esp32p4/src/lp_ana/touch_pad7_th0.rs
index c31b4b54d0..05060384b5 100644
--- a/esp32p4/src/lp_ana/touch_pad7_th0.rs
+++ b/esp32p4/src/lp_ana/touch_pad7_th0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD7_TH0")
-            .field(
-                "touch_pad7_th0",
-                &format_args!("{}", self.touch_pad7_th0().bits()),
-            )
+            .field("touch_pad7_th0", &self.touch_pad7_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD7_TH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad7_th1.rs b/esp32p4/src/lp_ana/touch_pad7_th1.rs
index bf75f0172e..c9c9e0708e 100644
--- a/esp32p4/src/lp_ana/touch_pad7_th1.rs
+++ b/esp32p4/src/lp_ana/touch_pad7_th1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD7_TH1")
-            .field(
-                "touch_pad7_th1",
-                &format_args!("{}", self.touch_pad7_th1().bits()),
-            )
+            .field("touch_pad7_th1", &self.touch_pad7_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD7_TH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad7_th2.rs b/esp32p4/src/lp_ana/touch_pad7_th2.rs
index 63712c4d2d..af40f77b3d 100644
--- a/esp32p4/src/lp_ana/touch_pad7_th2.rs
+++ b/esp32p4/src/lp_ana/touch_pad7_th2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD7_TH2")
-            .field(
-                "touch_pad7_th2",
-                &format_args!("{}", self.touch_pad7_th2().bits()),
-            )
+            .field("touch_pad7_th2", &self.touch_pad7_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD7_TH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad8_th0.rs b/esp32p4/src/lp_ana/touch_pad8_th0.rs
index e7b52b3203..e8aa6eafa9 100644
--- a/esp32p4/src/lp_ana/touch_pad8_th0.rs
+++ b/esp32p4/src/lp_ana/touch_pad8_th0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD8_TH0")
-            .field(
-                "touch_pad8_th0",
-                &format_args!("{}", self.touch_pad8_th0().bits()),
-            )
+            .field("touch_pad8_th0", &self.touch_pad8_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD8_TH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad8_th1.rs b/esp32p4/src/lp_ana/touch_pad8_th1.rs
index 4837776ef0..3360cb3a6f 100644
--- a/esp32p4/src/lp_ana/touch_pad8_th1.rs
+++ b/esp32p4/src/lp_ana/touch_pad8_th1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD8_TH1")
-            .field(
-                "touch_pad8_th1",
-                &format_args!("{}", self.touch_pad8_th1().bits()),
-            )
+            .field("touch_pad8_th1", &self.touch_pad8_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD8_TH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad8_th2.rs b/esp32p4/src/lp_ana/touch_pad8_th2.rs
index 8caf62af3c..7120a6427f 100644
--- a/esp32p4/src/lp_ana/touch_pad8_th2.rs
+++ b/esp32p4/src/lp_ana/touch_pad8_th2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD8_TH2")
-            .field(
-                "touch_pad8_th2",
-                &format_args!("{}", self.touch_pad8_th2().bits()),
-            )
+            .field("touch_pad8_th2", &self.touch_pad8_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD8_TH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad9_th0.rs b/esp32p4/src/lp_ana/touch_pad9_th0.rs
index 47b23a3eab..b6f018d3c3 100644
--- a/esp32p4/src/lp_ana/touch_pad9_th0.rs
+++ b/esp32p4/src/lp_ana/touch_pad9_th0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD9_TH0")
-            .field(
-                "touch_pad9_th0",
-                &format_args!("{}", self.touch_pad9_th0().bits()),
-            )
+            .field("touch_pad9_th0", &self.touch_pad9_th0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD9_TH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad9_th1.rs b/esp32p4/src/lp_ana/touch_pad9_th1.rs
index 137b9a4be1..f25a6ca959 100644
--- a/esp32p4/src/lp_ana/touch_pad9_th1.rs
+++ b/esp32p4/src/lp_ana/touch_pad9_th1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD9_TH1")
-            .field(
-                "touch_pad9_th1",
-                &format_args!("{}", self.touch_pad9_th1().bits()),
-            )
+            .field("touch_pad9_th1", &self.touch_pad9_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD9_TH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_pad9_th2.rs b/esp32p4/src/lp_ana/touch_pad9_th2.rs
index 4fac9c4f3d..59eec48316 100644
--- a/esp32p4/src/lp_ana/touch_pad9_th2.rs
+++ b/esp32p4/src/lp_ana/touch_pad9_th2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD9_TH2")
-            .field(
-                "touch_pad9_th2",
-                &format_args!("{}", self.touch_pad9_th2().bits()),
-            )
+            .field("touch_pad9_th2", &self.touch_pad9_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD9_TH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_scan_ctrl1.rs b/esp32p4/src/lp_ana/touch_scan_ctrl1.rs
index e735b95098..2a33be94b5 100644
--- a/esp32p4/src/lp_ana/touch_scan_ctrl1.rs
+++ b/esp32p4/src/lp_ana/touch_scan_ctrl1.rs
@@ -44,31 +44,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_SCAN_CTRL1")
-            .field(
-                "touch_shield_pad_en",
-                &format_args!("{}", self.touch_shield_pad_en().bit()),
-            )
+            .field("touch_shield_pad_en", &self.touch_shield_pad_en())
             .field(
                 "touch_inactive_connection",
-                &format_args!("{}", self.touch_inactive_connection().bit()),
-            )
-            .field(
-                "touch_scan_pad_map",
-                &format_args!("{}", self.touch_scan_pad_map().bits()),
-            )
-            .field(
-                "touch_xpd_wait",
-                &format_args!("{}", self.touch_xpd_wait().bits()),
+                &self.touch_inactive_connection(),
             )
+            .field("touch_scan_pad_map", &self.touch_scan_pad_map())
+            .field("touch_xpd_wait", &self.touch_xpd_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_SCAN_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_scan_ctrl2.rs b/esp32p4/src/lp_ana/touch_scan_ctrl2.rs
index 9add376236..17b1ec0b1d 100644
--- a/esp32p4/src/lp_ana/touch_scan_ctrl2.rs
+++ b/esp32p4/src/lp_ana/touch_scan_ctrl2.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_SCAN_CTRL2")
-            .field(
-                "touch_timeout_num",
-                &format_args!("{}", self.touch_timeout_num().bits()),
-            )
-            .field(
-                "touch_timeout_en",
-                &format_args!("{}", self.touch_timeout_en().bit()),
-            )
-            .field(
-                "touch_out_ring",
-                &format_args!("{}", self.touch_out_ring().bits()),
-            )
-            .field(
-                "freq_scan_en",
-                &format_args!("{}", self.freq_scan_en().bit()),
-            )
-            .field(
-                "freq_scan_cnt_limit",
-                &format_args!("{}", self.freq_scan_cnt_limit().bits()),
-            )
+            .field("touch_timeout_num", &self.touch_timeout_num())
+            .field("touch_timeout_en", &self.touch_timeout_en())
+            .field("touch_out_ring", &self.touch_out_ring())
+            .field("freq_scan_en", &self.freq_scan_en())
+            .field("freq_scan_cnt_limit", &self.freq_scan_cnt_limit())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_SCAN_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 6:21 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_slp0.rs b/esp32p4/src/lp_ana/touch_slp0.rs
index e0cfd0481f..ff672037ce 100644
--- a/esp32p4/src/lp_ana/touch_slp0.rs
+++ b/esp32p4/src/lp_ana/touch_slp0.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_SLP0")
-            .field(
-                "touch_slp_th0",
-                &format_args!("{}", self.touch_slp_th0().bits()),
-            )
-            .field(
-                "touch_slp_pad",
-                &format_args!("{}", self.touch_slp_pad().bits()),
-            )
+            .field("touch_slp_th0", &self.touch_slp_th0())
+            .field("touch_slp_pad", &self.touch_slp_pad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_SLP0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_slp1.rs b/esp32p4/src/lp_ana/touch_slp1.rs
index 63009cbf77..2a3c26ddb7 100644
--- a/esp32p4/src/lp_ana/touch_slp1.rs
+++ b/esp32p4/src/lp_ana/touch_slp1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_SLP1")
-            .field(
-                "touch_slp_th2",
-                &format_args!("{}", self.touch_slp_th2().bits()),
-            )
-            .field(
-                "touch_slp_th1",
-                &format_args!("{}", self.touch_slp_th1().bits()),
-            )
+            .field("touch_slp_th2", &self.touch_slp_th2())
+            .field("touch_slp_th1", &self.touch_slp_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_SLP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_work.rs b/esp32p4/src/lp_ana/touch_work.rs
index bf6164238c..6ca15e0ce5 100644
--- a/esp32p4/src/lp_ana/touch_work.rs
+++ b/esp32p4/src/lp_ana/touch_work.rs
@@ -55,26 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_WORK")
-            .field("div_num2", &format_args!("{}", self.div_num2().bits()))
-            .field("div_num1", &format_args!("{}", self.div_num1().bits()))
-            .field("div_num0", &format_args!("{}", self.div_num0().bits()))
-            .field(
-                "touch_out_sel",
-                &format_args!("{}", self.touch_out_sel().bit()),
-            )
-            .field(
-                "touch_out_gate",
-                &format_args!("{}", self.touch_out_gate().bit()),
-            )
+            .field("div_num2", &self.div_num2())
+            .field("div_num1", &self.div_num1())
+            .field("div_num0", &self.div_num0())
+            .field("touch_out_sel", &self.touch_out_sel())
+            .field("touch_out_gate", &self.touch_out_gate())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_WORK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:18 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/touch_work_meas_num.rs b/esp32p4/src/lp_ana/touch_work_meas_num.rs
index 5e29db9e70..0ec99592d7 100644
--- a/esp32p4/src/lp_ana/touch_work_meas_num.rs
+++ b/esp32p4/src/lp_ana/touch_work_meas_num.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_WORK_MEAS_NUM")
-            .field(
-                "touch_meas_num2",
-                &format_args!("{}", self.touch_meas_num2().bits()),
-            )
-            .field(
-                "touch_meas_num1",
-                &format_args!("{}", self.touch_meas_num1().bits()),
-            )
-            .field(
-                "touch_meas_num0",
-                &format_args!("{}", self.touch_meas_num0().bits()),
-            )
+            .field("touch_meas_num2", &self.touch_meas_num2())
+            .field("touch_meas_num1", &self.touch_meas_num1())
+            .field("touch_meas_num0", &self.touch_meas_num0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_WORK_MEAS_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/vdd_source_cntl.rs b/esp32p4/src/lp_ana/vdd_source_cntl.rs
index 1ecbb2d162..5d407afd57 100644
--- a/esp32p4/src/lp_ana/vdd_source_cntl.rs
+++ b/esp32p4/src/lp_ana/vdd_source_cntl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VDD_SOURCE_CNTL")
-            .field(
-                "detmode_sel",
-                &format_args!("{}", self.detmode_sel().bits()),
-            )
-            .field(
-                "vgood_event_record",
-                &format_args!("{}", self.vgood_event_record().bits()),
-            )
-            .field(
-                "bod_source_ena",
-                &format_args!("{}", self.bod_source_ena().bits()),
-            )
+            .field("detmode_sel", &self.detmode_sel())
+            .field("vgood_event_record", &self.vgood_event_record())
+            .field("bod_source_ena", &self.bod_source_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VDD_SOURCE_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/vddbat_bod_cntl.rs b/esp32p4/src/lp_ana/vddbat_bod_cntl.rs
index b246574595..3f51154a37 100644
--- a/esp32p4/src/lp_ana/vddbat_bod_cntl.rs
+++ b/esp32p4/src/lp_ana/vddbat_bod_cntl.rs
@@ -51,35 +51,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VDDBAT_BOD_CNTL")
-            .field(
-                "vddbat_undervoltage_flag",
-                &format_args!("{}", self.vddbat_undervoltage_flag().bit()),
-            )
-            .field(
-                "vddbat_charger",
-                &format_args!("{}", self.vddbat_charger().bit()),
-            )
-            .field(
-                "vddbat_cnt_clr",
-                &format_args!("{}", self.vddbat_cnt_clr().bit()),
-            )
-            .field(
-                "vddbat_upvoltage_target",
-                &format_args!("{}", self.vddbat_upvoltage_target().bits()),
-            )
+            .field("vddbat_undervoltage_flag", &self.vddbat_undervoltage_flag())
+            .field("vddbat_charger", &self.vddbat_charger())
+            .field("vddbat_cnt_clr", &self.vddbat_cnt_clr())
+            .field("vddbat_upvoltage_target", &self.vddbat_upvoltage_target())
             .field(
                 "vddbat_undervoltage_target",
-                &format_args!("{}", self.vddbat_undervoltage_target().bits()),
+                &self.vddbat_undervoltage_target(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VDDBAT_BOD_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 10 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_ana/vddbat_charge_cntl.rs b/esp32p4/src/lp_ana/vddbat_charge_cntl.rs
index 0d3c6367e5..063631ba31 100644
--- a/esp32p4/src/lp_ana/vddbat_charge_cntl.rs
+++ b/esp32p4/src/lp_ana/vddbat_charge_cntl.rs
@@ -53,33 +53,21 @@ impl core::fmt::Debug for R {
         f.debug_struct("VDDBAT_CHARGE_CNTL")
             .field(
                 "vddbat_charge_undervoltage_flag",
-                &format_args!("{}", self.vddbat_charge_undervoltage_flag().bit()),
-            )
-            .field(
-                "vddbat_charge_charger",
-                &format_args!("{}", self.vddbat_charge_charger().bit()),
-            )
-            .field(
-                "vddbat_charge_cnt_clr",
-                &format_args!("{}", self.vddbat_charge_cnt_clr().bit()),
+                &self.vddbat_charge_undervoltage_flag(),
             )
+            .field("vddbat_charge_charger", &self.vddbat_charge_charger())
+            .field("vddbat_charge_cnt_clr", &self.vddbat_charge_cnt_clr())
             .field(
                 "vddbat_charge_upvoltage_target",
-                &format_args!("{}", self.vddbat_charge_upvoltage_target().bits()),
+                &self.vddbat_charge_upvoltage_target(),
             )
             .field(
                 "vddbat_charge_undervoltage_target",
-                &format_args!("{}", self.vddbat_charge_undervoltage_target().bits()),
+                &self.vddbat_charge_undervoltage_target(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VDDBAT_CHARGE_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 10 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_clk_to_hp.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_clk_to_hp.rs
index adf3b8cafb..feb39b8182 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_clk_to_hp.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_clk_to_hp.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_CLK_TO_HP")
             .field(
                 "lp_aonclkrst_icg_hp_xtal32k",
-                &format_args!("{}", self.lp_aonclkrst_icg_hp_xtal32k().bit()),
-            )
-            .field(
-                "lp_aonclkrst_icg_hp_sosc",
-                &format_args!("{}", self.lp_aonclkrst_icg_hp_sosc().bit()),
+                &self.lp_aonclkrst_icg_hp_xtal32k(),
             )
+            .field("lp_aonclkrst_icg_hp_sosc", &self.lp_aonclkrst_icg_hp_sosc())
             .field(
                 "lp_aonclkrst_icg_hp_osc32k",
-                &format_args!("{}", self.lp_aonclkrst_icg_hp_osc32k().bit()),
-            )
-            .field(
-                "lp_aonclkrst_icg_hp_fosc",
-                &format_args!("{}", self.lp_aonclkrst_icg_hp_fosc().bit()),
+                &self.lp_aonclkrst_icg_hp_osc32k(),
             )
+            .field("lp_aonclkrst_icg_hp_fosc", &self.lp_aonclkrst_icg_hp_fosc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_CLK_TO_HP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_date.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_date.rs
index d62894a96b..ae658f761b 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_date.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_AONCLKRST_DATE")
-            .field(
-                "lp_aonclkrst_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_clk_en().bit()),
-            )
+            .field("lp_aonclkrst_clk_en", &self.lp_aonclkrst_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_fosc_cntl.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_fosc_cntl.rs
index d82e174464..33eb085f3a 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_fosc_cntl.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_fosc_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_AONCLKRST_FOSC_CNTL")
-            .field(
-                "lp_aonclkrst_fosc_dfreq",
-                &format_args!("{}", self.lp_aonclkrst_fosc_dfreq().bits()),
-            )
+            .field("lp_aonclkrst_fosc_dfreq", &self.lp_aonclkrst_fosc_dfreq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_FOSC_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_clk_ctrl.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_clk_ctrl.rs
index 3d5cd6b370..197730f389 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_clk_ctrl.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_clk_ctrl.rs
@@ -262,125 +262,119 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_HP_CLK_CTRL")
             .field(
                 "lp_aonclkrst_hp_root_clk_src_sel",
-                &format_args!("{}", self.lp_aonclkrst_hp_root_clk_src_sel().bits()),
+                &self.lp_aonclkrst_hp_root_clk_src_sel(),
             )
             .field(
                 "lp_aonclkrst_hp_root_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_root_clk_en().bit()),
+                &self.lp_aonclkrst_hp_root_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_pad_parlio_tx_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_pad_parlio_tx_clk_en().bit()),
+                &self.lp_aonclkrst_hp_pad_parlio_tx_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_pad_parlio_rx_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_pad_parlio_rx_clk_en().bit()),
+                &self.lp_aonclkrst_hp_pad_parlio_rx_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_pad_uart4_slp_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_pad_uart4_slp_clk_en().bit()),
+                &self.lp_aonclkrst_hp_pad_uart4_slp_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_pad_uart3_slp_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_pad_uart3_slp_clk_en().bit()),
+                &self.lp_aonclkrst_hp_pad_uart3_slp_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_pad_uart2_slp_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_pad_uart2_slp_clk_en().bit()),
+                &self.lp_aonclkrst_hp_pad_uart2_slp_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_pad_uart1_slp_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_pad_uart1_slp_clk_en().bit()),
+                &self.lp_aonclkrst_hp_pad_uart1_slp_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_pad_uart0_slp_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_pad_uart0_slp_clk_en().bit()),
+                &self.lp_aonclkrst_hp_pad_uart0_slp_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_pad_i2s2_mclk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_pad_i2s2_mclk_en().bit()),
+                &self.lp_aonclkrst_hp_pad_i2s2_mclk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_pad_i2s1_mclk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_pad_i2s1_mclk_en().bit()),
+                &self.lp_aonclkrst_hp_pad_i2s1_mclk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_pad_i2s0_mclk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_pad_i2s0_mclk_en().bit()),
+                &self.lp_aonclkrst_hp_pad_i2s0_mclk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_pad_emac_tx_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_pad_emac_tx_clk_en().bit()),
+                &self.lp_aonclkrst_hp_pad_emac_tx_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_pad_emac_rx_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_pad_emac_rx_clk_en().bit()),
+                &self.lp_aonclkrst_hp_pad_emac_rx_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_pad_emac_txrx_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_pad_emac_txrx_clk_en().bit()),
+                &self.lp_aonclkrst_hp_pad_emac_txrx_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_xtal_32k_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_xtal_32k_clk_en().bit()),
+                &self.lp_aonclkrst_hp_xtal_32k_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_rc_32k_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_rc_32k_clk_en().bit()),
+                &self.lp_aonclkrst_hp_rc_32k_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_sosc_150k_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_sosc_150k_clk_en().bit()),
+                &self.lp_aonclkrst_hp_sosc_150k_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_pll_8m_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_pll_8m_clk_en().bit()),
+                &self.lp_aonclkrst_hp_pll_8m_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_audio_pll_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_audio_pll_clk_en().bit()),
+                &self.lp_aonclkrst_hp_audio_pll_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_sdio_pll2_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_sdio_pll2_clk_en().bit()),
+                &self.lp_aonclkrst_hp_sdio_pll2_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_sdio_pll1_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_sdio_pll1_clk_en().bit()),
+                &self.lp_aonclkrst_hp_sdio_pll1_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_sdio_pll0_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_sdio_pll0_clk_en().bit()),
+                &self.lp_aonclkrst_hp_sdio_pll0_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_fosc_20m_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_fosc_20m_clk_en().bit()),
+                &self.lp_aonclkrst_hp_fosc_20m_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_xtal_40m_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_xtal_40m_clk_en().bit()),
+                &self.lp_aonclkrst_hp_xtal_40m_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_cpll_400m_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_cpll_400m_clk_en().bit()),
+                &self.lp_aonclkrst_hp_cpll_400m_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_spll_480m_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_spll_480m_clk_en().bit()),
+                &self.lp_aonclkrst_hp_spll_480m_clk_en(),
             )
             .field(
                 "lp_aonclkrst_hp_mpll_500m_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_hp_mpll_500m_clk_en().bit()),
+                &self.lp_aonclkrst_hp_mpll_500m_clk_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_HP_CLK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_sdmmc_emac_rst_ctrl.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_sdmmc_emac_rst_ctrl.rs
index 3c33877e1f..a71bd8f616 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_sdmmc_emac_rst_ctrl.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_sdmmc_emac_rst_ctrl.rs
@@ -46,29 +46,20 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL")
             .field(
                 "lp_aonclkrst_rst_en_sdmmc",
-                &format_args!("{}", self.lp_aonclkrst_rst_en_sdmmc().bit()),
+                &self.lp_aonclkrst_rst_en_sdmmc(),
             )
             .field(
                 "lp_aonclkrst_force_norst_sdmmc",
-                &format_args!("{}", self.lp_aonclkrst_force_norst_sdmmc().bit()),
-            )
-            .field(
-                "lp_aonclkrst_rst_en_emac",
-                &format_args!("{}", self.lp_aonclkrst_rst_en_emac().bit()),
+                &self.lp_aonclkrst_force_norst_sdmmc(),
             )
+            .field("lp_aonclkrst_rst_en_emac", &self.lp_aonclkrst_rst_en_emac())
             .field(
                 "lp_aonclkrst_force_norst_emac",
-                &format_args!("{}", self.lp_aonclkrst_force_norst_emac().bit()),
+                &self.lp_aonclkrst_force_norst_emac(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - hp sdmmc reset en"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_usb_clkrst_ctrl0.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_usb_clkrst_ctrl0.rs
index fcd9f22173..ff33e8fae4 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_usb_clkrst_ctrl0.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_usb_clkrst_ctrl0.rs
@@ -91,49 +91,43 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_HP_USB_CLKRST_CTRL0")
             .field(
                 "lp_aonclkrst_usb_otg20_sleep_mode",
-                &format_args!("{}", self.lp_aonclkrst_usb_otg20_sleep_mode().bit()),
+                &self.lp_aonclkrst_usb_otg20_sleep_mode(),
             )
             .field(
                 "lp_aonclkrst_usb_otg20_bk_sys_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_usb_otg20_bk_sys_clk_en().bit()),
+                &self.lp_aonclkrst_usb_otg20_bk_sys_clk_en(),
             )
             .field(
                 "lp_aonclkrst_usb_otg11_sleep_mode",
-                &format_args!("{}", self.lp_aonclkrst_usb_otg11_sleep_mode().bit()),
+                &self.lp_aonclkrst_usb_otg11_sleep_mode(),
             )
             .field(
                 "lp_aonclkrst_usb_otg11_bk_sys_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_usb_otg11_bk_sys_clk_en().bit()),
+                &self.lp_aonclkrst_usb_otg11_bk_sys_clk_en(),
             )
             .field(
                 "lp_aonclkrst_usb_otg11_48m_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_usb_otg11_48m_clk_en().bit()),
+                &self.lp_aonclkrst_usb_otg11_48m_clk_en(),
             )
             .field(
                 "lp_aonclkrst_usb_device_48m_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_usb_device_48m_clk_en().bit()),
+                &self.lp_aonclkrst_usb_device_48m_clk_en(),
             )
             .field(
                 "lp_aonclkrst_usb_48m_div_num",
-                &format_args!("{}", self.lp_aonclkrst_usb_48m_div_num().bits()),
+                &self.lp_aonclkrst_usb_48m_div_num(),
             )
             .field(
                 "lp_aonclkrst_usb_25m_div_num",
-                &format_args!("{}", self.lp_aonclkrst_usb_25m_div_num().bits()),
+                &self.lp_aonclkrst_usb_25m_div_num(),
             )
             .field(
                 "lp_aonclkrst_usb_12m_div_num",
-                &format_args!("{}", self.lp_aonclkrst_usb_12m_div_num().bits()),
+                &self.lp_aonclkrst_usb_12m_div_num(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_HP_USB_CLKRST_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - unused."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_usb_clkrst_ctrl1.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_usb_clkrst_ctrl1.rs
index 83a99fb8b5..064761420e 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_usb_clkrst_ctrl1.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hp_usb_clkrst_ctrl1.rs
@@ -84,48 +84,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_HP_USB_CLKRST_CTRL1")
             .field(
                 "lp_aonclkrst_rst_en_usb_otg20_adp",
-                &format_args!("{}", self.lp_aonclkrst_rst_en_usb_otg20_adp().bit()),
+                &self.lp_aonclkrst_rst_en_usb_otg20_adp(),
             )
             .field(
                 "lp_aonclkrst_rst_en_usb_otg20_phy",
-                &format_args!("{}", self.lp_aonclkrst_rst_en_usb_otg20_phy().bit()),
+                &self.lp_aonclkrst_rst_en_usb_otg20_phy(),
             )
             .field(
                 "lp_aonclkrst_rst_en_usb_otg20",
-                &format_args!("{}", self.lp_aonclkrst_rst_en_usb_otg20().bit()),
+                &self.lp_aonclkrst_rst_en_usb_otg20(),
             )
             .field(
                 "lp_aonclkrst_rst_en_usb_otg11",
-                &format_args!("{}", self.lp_aonclkrst_rst_en_usb_otg11().bit()),
+                &self.lp_aonclkrst_rst_en_usb_otg11(),
             )
             .field(
                 "lp_aonclkrst_rst_en_usb_device",
-                &format_args!("{}", self.lp_aonclkrst_rst_en_usb_device().bit()),
+                &self.lp_aonclkrst_rst_en_usb_device(),
             )
             .field(
                 "lp_aonclkrst_usb_otg20_phyref_clk_src_sel",
-                &format_args!(
-                    "{}",
-                    self.lp_aonclkrst_usb_otg20_phyref_clk_src_sel().bits()
-                ),
+                &self.lp_aonclkrst_usb_otg20_phyref_clk_src_sel(),
             )
             .field(
                 "lp_aonclkrst_usb_otg20_phyref_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_usb_otg20_phyref_clk_en().bit()),
+                &self.lp_aonclkrst_usb_otg20_phyref_clk_en(),
             )
             .field(
                 "lp_aonclkrst_usb_otg20_ulpi_clk_en",
-                &format_args!("{}", self.lp_aonclkrst_usb_otg20_ulpi_clk_en().bit()),
+                &self.lp_aonclkrst_usb_otg20_ulpi_clk_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_HP_USB_CLKRST_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - usb otg20 adp reset en"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpcpu_reset_ctrl0.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpcpu_reset_ctrl0.rs
index add41ae166..caa8205b77 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpcpu_reset_ctrl0.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpcpu_reset_ctrl0.rs
@@ -148,69 +148,63 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_HPCPU_RESET_CTRL0")
             .field(
                 "lp_aonclkrst_hpcore0_lockup_reset_en",
-                &format_args!("{}", self.lp_aonclkrst_hpcore0_lockup_reset_en().bit()),
+                &self.lp_aonclkrst_hpcore0_lockup_reset_en(),
             )
             .field(
                 "lp_aonclkrst_lp_wdt_hpcore0_reset_length",
-                &format_args!("{}", self.lp_aonclkrst_lp_wdt_hpcore0_reset_length().bits()),
+                &self.lp_aonclkrst_lp_wdt_hpcore0_reset_length(),
             )
             .field(
                 "lp_aonclkrst_lp_wdt_hpcore0_reset_en",
-                &format_args!("{}", self.lp_aonclkrst_lp_wdt_hpcore0_reset_en().bit()),
+                &self.lp_aonclkrst_lp_wdt_hpcore0_reset_en(),
             )
             .field(
                 "lp_aonclkrst_hpcore0_stall_wait",
-                &format_args!("{}", self.lp_aonclkrst_hpcore0_stall_wait().bits()),
+                &self.lp_aonclkrst_hpcore0_stall_wait(),
             )
             .field(
                 "lp_aonclkrst_hpcore0_stall_en",
-                &format_args!("{}", self.lp_aonclkrst_hpcore0_stall_en().bit()),
+                &self.lp_aonclkrst_hpcore0_stall_en(),
             )
             .field(
                 "lp_aonclkrst_hpcore0_ocd_halt_on_reset",
-                &format_args!("{}", self.lp_aonclkrst_hpcore0_ocd_halt_on_reset().bit()),
+                &self.lp_aonclkrst_hpcore0_ocd_halt_on_reset(),
             )
             .field(
                 "lp_aonclkrst_hpcore0_stat_vector_sel",
-                &format_args!("{}", self.lp_aonclkrst_hpcore0_stat_vector_sel().bit()),
+                &self.lp_aonclkrst_hpcore0_stat_vector_sel(),
             )
             .field(
                 "lp_aonclkrst_hpcore1_lockup_reset_en",
-                &format_args!("{}", self.lp_aonclkrst_hpcore1_lockup_reset_en().bit()),
+                &self.lp_aonclkrst_hpcore1_lockup_reset_en(),
             )
             .field(
                 "lp_aonclkrst_lp_wdt_hpcore1_reset_length",
-                &format_args!("{}", self.lp_aonclkrst_lp_wdt_hpcore1_reset_length().bits()),
+                &self.lp_aonclkrst_lp_wdt_hpcore1_reset_length(),
             )
             .field(
                 "lp_aonclkrst_lp_wdt_hpcore1_reset_en",
-                &format_args!("{}", self.lp_aonclkrst_lp_wdt_hpcore1_reset_en().bit()),
+                &self.lp_aonclkrst_lp_wdt_hpcore1_reset_en(),
             )
             .field(
                 "lp_aonclkrst_hpcore1_stall_wait",
-                &format_args!("{}", self.lp_aonclkrst_hpcore1_stall_wait().bits()),
+                &self.lp_aonclkrst_hpcore1_stall_wait(),
             )
             .field(
                 "lp_aonclkrst_hpcore1_stall_en",
-                &format_args!("{}", self.lp_aonclkrst_hpcore1_stall_en().bit()),
+                &self.lp_aonclkrst_hpcore1_stall_en(),
             )
             .field(
                 "lp_aonclkrst_hpcore1_ocd_halt_on_reset",
-                &format_args!("{}", self.lp_aonclkrst_hpcore1_ocd_halt_on_reset().bit()),
+                &self.lp_aonclkrst_hpcore1_ocd_halt_on_reset(),
             )
             .field(
                 "lp_aonclkrst_hpcore1_stat_vector_sel",
-                &format_args!("{}", self.lp_aonclkrst_hpcore1_stat_vector_sel().bit()),
+                &self.lp_aonclkrst_hpcore1_stat_vector_sel(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup reset feature"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpcpu_reset_ctrl1.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpcpu_reset_ctrl1.rs
index a1bd4b6227..23552ef34e 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpcpu_reset_ctrl1.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpcpu_reset_ctrl1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_HPCPU_RESET_CTRL1")
             .field(
                 "lp_aonclkrst_hpcore0_sw_stall_code",
-                &format_args!("{}", self.lp_aonclkrst_hpcore0_sw_stall_code().bits()),
+                &self.lp_aonclkrst_hpcore0_sw_stall_code(),
             )
             .field(
                 "lp_aonclkrst_hpcore1_sw_stall_code",
-                &format_args!("{}", self.lp_aonclkrst_hpcore1_sw_stall_code().bits()),
+                &self.lp_aonclkrst_hpcore1_sw_stall_code(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_HPCPU_RESET_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:23 - HP core0 software stall when set to 8'h86"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpsys_0_reset_bypass.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpsys_0_reset_bypass.rs
index 4e04ec641b..f93c2f439d 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpsys_0_reset_bypass.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpsys_0_reset_bypass.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_HPSYS_0_RESET_BYPASS")
             .field(
                 "lp_aonclkrst_hpsys_0_reset_bypass",
-                &format_args!("{}", self.lp_aonclkrst_hpsys_0_reset_bypass().bits()),
+                &self.lp_aonclkrst_hpsys_0_reset_bypass(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_HPSYS_0_RESET_BYPASS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpsys_apm_reset_bypass.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpsys_apm_reset_bypass.rs
index 6a265e9039..89190ae170 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpsys_apm_reset_bypass.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_hpsys_apm_reset_bypass.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_HPSYS_APM_RESET_BYPASS")
             .field(
                 "lp_aonclkrst_hpsys_apm_reset_bypass",
-                &format_args!("{}", self.lp_aonclkrst_hpsys_apm_reset_bypass().bits()),
+                &self.lp_aonclkrst_hpsys_apm_reset_bypass(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_HPSYS_APM_RESET_BYPASS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_conf.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_conf.rs
index 07b0a8349d..b934332079 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_conf.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_conf.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_LP_CLK_CONF")
             .field(
                 "lp_aonclkrst_slow_clk_sel",
-                &format_args!("{}", self.lp_aonclkrst_slow_clk_sel().bits()),
+                &self.lp_aonclkrst_slow_clk_sel(),
             )
             .field(
                 "lp_aonclkrst_fast_clk_sel",
-                &format_args!("{}", self.lp_aonclkrst_fast_clk_sel().bits()),
+                &self.lp_aonclkrst_fast_clk_sel(),
             )
             .field(
                 "lp_aonclkrst_lp_peri_div_num",
-                &format_args!("{}", self.lp_aonclkrst_lp_peri_div_num().bits()),
+                &self.lp_aonclkrst_lp_peri_div_num(),
             )
             .field(
                 "lp_aonclkrst_ana_sel_ref_pll8m",
-                &format_args!("{}", self.lp_aonclkrst_ana_sel_ref_pll8m().bit()),
+                &self.lp_aonclkrst_ana_sel_ref_pll8m(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_LP_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_en.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_en.rs
index bffa067844..78496fc6ca 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_en.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_en.rs
@@ -64,37 +64,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_LP_CLK_EN")
             .field(
                 "lp_aonclkrst_lp_rtc_xtal_force_on",
-                &format_args!("{}", self.lp_aonclkrst_lp_rtc_xtal_force_on().bit()),
+                &self.lp_aonclkrst_lp_rtc_xtal_force_on(),
             )
             .field(
                 "lp_aonclkrst_ck_en_lp_ram",
-                &format_args!("{}", self.lp_aonclkrst_ck_en_lp_ram().bit()),
+                &self.lp_aonclkrst_ck_en_lp_ram(),
             )
             .field(
                 "lp_aonclkrst_etm_event_tick_en",
-                &format_args!("{}", self.lp_aonclkrst_etm_event_tick_en().bit()),
+                &self.lp_aonclkrst_etm_event_tick_en(),
             )
             .field(
                 "lp_aonclkrst_pll8m_clk_force_on",
-                &format_args!("{}", self.lp_aonclkrst_pll8m_clk_force_on().bit()),
+                &self.lp_aonclkrst_pll8m_clk_force_on(),
             )
             .field(
                 "lp_aonclkrst_xtal_clk_force_on",
-                &format_args!("{}", self.lp_aonclkrst_xtal_clk_force_on().bit()),
+                &self.lp_aonclkrst_xtal_clk_force_on(),
             )
             .field(
                 "lp_aonclkrst_fosc_clk_force_on",
-                &format_args!("{}", self.lp_aonclkrst_fosc_clk_force_on().bit()),
+                &self.lp_aonclkrst_fosc_clk_force_on(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_LP_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_po_en.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_po_en.rs
index 693f310949..2a22e97ce2 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_po_en.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_clk_po_en.rs
@@ -100,53 +100,47 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_LP_CLK_PO_EN")
             .field(
                 "lp_aonclkrst_clk_core_efuse_oen",
-                &format_args!("{}", self.lp_aonclkrst_clk_core_efuse_oen().bit()),
+                &self.lp_aonclkrst_clk_core_efuse_oen(),
             )
             .field(
                 "lp_aonclkrst_clk_lp_bus_oen",
-                &format_args!("{}", self.lp_aonclkrst_clk_lp_bus_oen().bit()),
+                &self.lp_aonclkrst_clk_lp_bus_oen(),
             )
             .field(
                 "lp_aonclkrst_clk_aon_slow_oen",
-                &format_args!("{}", self.lp_aonclkrst_clk_aon_slow_oen().bit()),
+                &self.lp_aonclkrst_clk_aon_slow_oen(),
             )
             .field(
                 "lp_aonclkrst_clk_aon_fast_oen",
-                &format_args!("{}", self.lp_aonclkrst_clk_aon_fast_oen().bit()),
+                &self.lp_aonclkrst_clk_aon_fast_oen(),
             )
             .field(
                 "lp_aonclkrst_clk_slow_oen",
-                &format_args!("{}", self.lp_aonclkrst_clk_slow_oen().bit()),
+                &self.lp_aonclkrst_clk_slow_oen(),
             )
             .field(
                 "lp_aonclkrst_clk_fast_oen",
-                &format_args!("{}", self.lp_aonclkrst_clk_fast_oen().bit()),
+                &self.lp_aonclkrst_clk_fast_oen(),
             )
             .field(
                 "lp_aonclkrst_clk_fosc_oen",
-                &format_args!("{}", self.lp_aonclkrst_clk_fosc_oen().bit()),
+                &self.lp_aonclkrst_clk_fosc_oen(),
             )
             .field(
                 "lp_aonclkrst_clk_rc32k_oen",
-                &format_args!("{}", self.lp_aonclkrst_clk_rc32k_oen().bit()),
+                &self.lp_aonclkrst_clk_rc32k_oen(),
             )
             .field(
                 "lp_aonclkrst_clk_sxtal_oen",
-                &format_args!("{}", self.lp_aonclkrst_clk_sxtal_oen().bit()),
+                &self.lp_aonclkrst_clk_sxtal_oen(),
             )
             .field(
                 "lp_aonclkrst_clk_sosc_oen",
-                &format_args!("{}", self.lp_aonclkrst_clk_sosc_oen().bit()),
+                &self.lp_aonclkrst_clk_sosc_oen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_LP_CLK_PO_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_rst_en.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_rst_en.rs
index 1398370b28..bfbcfe31e1 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_rst_en.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lp_rst_en.rs
@@ -82,45 +82,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_LP_RST_EN")
             .field(
                 "lp_aonclkrst_rst_en_lp_huk",
-                &format_args!("{}", self.lp_aonclkrst_rst_en_lp_huk().bit()),
+                &self.lp_aonclkrst_rst_en_lp_huk(),
             )
             .field(
                 "lp_aonclkrst_rst_en_lp_anaperi",
-                &format_args!("{}", self.lp_aonclkrst_rst_en_lp_anaperi().bit()),
+                &self.lp_aonclkrst_rst_en_lp_anaperi(),
             )
             .field(
                 "lp_aonclkrst_rst_en_lp_wdt",
-                &format_args!("{}", self.lp_aonclkrst_rst_en_lp_wdt().bit()),
+                &self.lp_aonclkrst_rst_en_lp_wdt(),
             )
             .field(
                 "lp_aonclkrst_rst_en_lp_timer",
-                &format_args!("{}", self.lp_aonclkrst_rst_en_lp_timer().bit()),
+                &self.lp_aonclkrst_rst_en_lp_timer(),
             )
             .field(
                 "lp_aonclkrst_rst_en_lp_rtc",
-                &format_args!("{}", self.lp_aonclkrst_rst_en_lp_rtc().bit()),
+                &self.lp_aonclkrst_rst_en_lp_rtc(),
             )
             .field(
                 "lp_aonclkrst_rst_en_lp_mailbox",
-                &format_args!("{}", self.lp_aonclkrst_rst_en_lp_mailbox().bit()),
+                &self.lp_aonclkrst_rst_en_lp_mailbox(),
             )
             .field(
                 "lp_aonclkrst_rst_en_lp_aonefusereg",
-                &format_args!("{}", self.lp_aonclkrst_rst_en_lp_aonefusereg().bit()),
+                &self.lp_aonclkrst_rst_en_lp_aonefusereg(),
             )
             .field(
                 "lp_aonclkrst_rst_en_lp_ram",
-                &format_args!("{}", self.lp_aonclkrst_rst_en_lp_ram().bit()),
+                &self.lp_aonclkrst_rst_en_lp_ram(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_LP_RST_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lpmem_force.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lpmem_force.rs
index e55ddae1b2..66ae9fda1e 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lpmem_force.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_lpmem_force.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_LPMEM_FORCE")
             .field(
                 "lp_aonclkrst_lpmem_clk_force_on",
-                &format_args!("{}", self.lp_aonclkrst_lpmem_clk_force_on().bit()),
+                &self.lp_aonclkrst_lpmem_clk_force_on(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_LPMEM_FORCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_mux_hpsys_reset_bypass.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_mux_hpsys_reset_bypass.rs
index aae4d72749..8c4121eb49 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_mux_hpsys_reset_bypass.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_mux_hpsys_reset_bypass.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS")
             .field(
                 "lp_aonclkrst_mux_hpsys_reset_bypass",
-                &format_args!("{}", self.lp_aonclkrst_mux_hpsys_reset_bypass().bits()),
+                &self.lp_aonclkrst_mux_hpsys_reset_bypass(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_rc32k_cntl.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_rc32k_cntl.rs
index 9ab095752b..0cd6fb0f0d 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_rc32k_cntl.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_rc32k_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_AONCLKRST_RC32K_CNTL")
-            .field(
-                "lp_aonclkrst_rc32k_dfreq",
-                &format_args!("{}", self.lp_aonclkrst_rc32k_dfreq().bits()),
-            )
+            .field("lp_aonclkrst_rc32k_dfreq", &self.lp_aonclkrst_rc32k_dfreq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_RC32K_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_reset_cause.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_reset_cause.rs
index cade3d7afc..7b79f62f6e 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_reset_cause.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_reset_cause.rs
@@ -75,44 +75,35 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_RESET_CAUSE")
             .field(
                 "lp_aonclkrst_lpcore_reset_cause",
-                &format_args!("{}", self.lp_aonclkrst_lpcore_reset_cause().bits()),
+                &self.lp_aonclkrst_lpcore_reset_cause(),
             )
             .field(
                 "lp_aonclkrst_lpcore_reset_flag",
-                &format_args!("{}", self.lp_aonclkrst_lpcore_reset_flag().bit()),
+                &self.lp_aonclkrst_lpcore_reset_flag(),
             )
             .field(
                 "lp_aonclkrst_hpcore0_reset_cause",
-                &format_args!("{}", self.lp_aonclkrst_hpcore0_reset_cause().bits()),
+                &self.lp_aonclkrst_hpcore0_reset_cause(),
             )
             .field(
                 "lp_aonclkrst_hpcore0_reset_flag",
-                &format_args!("{}", self.lp_aonclkrst_hpcore0_reset_flag().bit()),
+                &self.lp_aonclkrst_hpcore0_reset_flag(),
             )
             .field(
                 "lp_aonclkrst_hpcore1_reset_cause",
-                &format_args!("{}", self.lp_aonclkrst_hpcore1_reset_cause().bits()),
+                &self.lp_aonclkrst_hpcore1_reset_cause(),
             )
             .field(
                 "lp_aonclkrst_hpcore1_reset_flag",
-                &format_args!("{}", self.lp_aonclkrst_hpcore1_reset_flag().bit()),
+                &self.lp_aonclkrst_hpcore1_reset_flag(),
             )
             .field(
                 "lp_aonclkrst_lpcore_reset_cause_pmu_lp_cpu_mask",
-                &format_args!(
-                    "{}",
-                    self.lp_aonclkrst_lpcore_reset_cause_pmu_lp_cpu_mask().bit()
-                ),
+                &self.lp_aonclkrst_lpcore_reset_cause_pmu_lp_cpu_mask(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_RESET_CAUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - 1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore pmu_lp_cpu_reset reset_cause"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_sosc_cntl.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_sosc_cntl.rs
index d536277f38..5032c6d91c 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_sosc_cntl.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_sosc_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_AONCLKRST_SOSC_CNTL")
-            .field(
-                "lp_aonclkrst_sosc_dfreq",
-                &format_args!("{}", self.lp_aonclkrst_sosc_dfreq().bits()),
-            )
+            .field("lp_aonclkrst_sosc_dfreq", &self.lp_aonclkrst_sosc_dfreq())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_SOSC_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_xtal32k.rs b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_xtal32k.rs
index ccfa3500e1..4341cbf03d 100644
--- a/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_xtal32k.rs
+++ b/esp32p4/src/lp_aon_clkrst/lp_aonclkrst_xtal32k.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_AONCLKRST_XTAL32K")
             .field(
                 "lp_aonclkrst_dres_xtal32k",
-                &format_args!("{}", self.lp_aonclkrst_dres_xtal32k().bits()),
-            )
-            .field(
-                "lp_aonclkrst_dgm_xtal32k",
-                &format_args!("{}", self.lp_aonclkrst_dgm_xtal32k().bits()),
+                &self.lp_aonclkrst_dres_xtal32k(),
             )
+            .field("lp_aonclkrst_dgm_xtal32k", &self.lp_aonclkrst_dgm_xtal32k())
             .field(
                 "lp_aonclkrst_dbuf_xtal32k",
-                &format_args!("{}", self.lp_aonclkrst_dbuf_xtal32k().bit()),
-            )
-            .field(
-                "lp_aonclkrst_dac_xtal32k",
-                &format_args!("{}", self.lp_aonclkrst_dac_xtal32k().bits()),
+                &self.lp_aonclkrst_dbuf_xtal32k(),
             )
+            .field("lp_aonclkrst_dac_xtal32k", &self.lp_aonclkrst_dac_xtal32k())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_XTAL32K_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:24 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/clk_en.rs b/esp32p4/src/lp_gpio/clk_en.rs
index 2c28fcfb34..fd0eedde58 100644
--- a/esp32p4/src/lp_gpio/clk_en.rs
+++ b/esp32p4/src/lp_gpio/clk_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EN")
-            .field("reg_clk_en", &format_args!("{}", self.reg_clk_en().bit()))
+            .field("reg_clk_en", &self.reg_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/enable.rs b/esp32p4/src/lp_gpio/enable.rs
index 42536ff6b4..f652032963 100644
--- a/esp32p4/src/lp_gpio/enable.rs
+++ b/esp32p4/src/lp_gpio/enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE")
-            .field(
-                "reg_gpio_enable_data",
-                &format_args!("{}", self.reg_gpio_enable_data().bits()),
-            )
+            .field("reg_gpio_enable_data", &self.reg_gpio_enable_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func0_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func0_in_sel_cfg.rs
index 3f06635b6c..4fbfef13a4 100644
--- a/esp32p4/src/lp_gpio/func0_in_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func0_in_sel_cfg.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC0_IN_SEL_CFG")
             .field(
                 "reg_gpio_func0_in_inv_sel",
-                &format_args!("{}", self.reg_gpio_func0_in_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_sig0_in_sel",
-                &format_args!("{}", self.reg_gpio_sig0_in_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func0_in_sel",
-                &format_args!("{}", self.reg_gpio_func0_in_sel().bits()),
+                &self.reg_gpio_func0_in_inv_sel(),
             )
+            .field("reg_gpio_sig0_in_sel", &self.reg_gpio_sig0_in_sel())
+            .field("reg_gpio_func0_in_sel", &self.reg_gpio_func0_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC0_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func0_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func0_out_sel_cfg.rs
index bbabb36900..dfa757c121 100644
--- a/esp32p4/src/lp_gpio/func0_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func0_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC0_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func0_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func0_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func0_oe_sel",
-                &format_args!("{}", self.reg_gpio_func0_oe_sel().bit()),
+                &self.reg_gpio_func0_oe_inv_sel(),
             )
+            .field("reg_gpio_func0_oe_sel", &self.reg_gpio_func0_oe_sel())
             .field(
                 "reg_gpio_func0_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func0_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func0_out_sel",
-                &format_args!("{}", self.reg_gpio_func0_out_sel().bits()),
+                &self.reg_gpio_func0_out_inv_sel(),
             )
+            .field("reg_gpio_func0_out_sel", &self.reg_gpio_func0_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC0_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func10_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func10_in_sel_cfg.rs
index b05e2bc388..099cb6ac7e 100644
--- a/esp32p4/src/lp_gpio/func10_in_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func10_in_sel_cfg.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC10_IN_SEL_CFG")
             .field(
                 "reg_gpio_func10_in_inv_sel",
-                &format_args!("{}", self.reg_gpio_func10_in_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_sig10_in_sel",
-                &format_args!("{}", self.reg_gpio_sig10_in_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func10_in_sel",
-                &format_args!("{}", self.reg_gpio_func10_in_sel().bits()),
+                &self.reg_gpio_func10_in_inv_sel(),
             )
+            .field("reg_gpio_sig10_in_sel", &self.reg_gpio_sig10_in_sel())
+            .field("reg_gpio_func10_in_sel", &self.reg_gpio_func10_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC10_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func10_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func10_out_sel_cfg.rs
index 4c3bd298d6..a70c8cb1f5 100644
--- a/esp32p4/src/lp_gpio/func10_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func10_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC10_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func10_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func10_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func10_oe_sel",
-                &format_args!("{}", self.reg_gpio_func10_oe_sel().bit()),
+                &self.reg_gpio_func10_oe_inv_sel(),
             )
+            .field("reg_gpio_func10_oe_sel", &self.reg_gpio_func10_oe_sel())
             .field(
                 "reg_gpio_func10_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func10_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func10_out_sel",
-                &format_args!("{}", self.reg_gpio_func10_out_sel().bits()),
+                &self.reg_gpio_func10_out_inv_sel(),
             )
+            .field("reg_gpio_func10_out_sel", &self.reg_gpio_func10_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC10_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func11_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func11_in_sel_cfg.rs
index c1ed7cd0a7..39fb804e45 100644
--- a/esp32p4/src/lp_gpio/func11_in_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func11_in_sel_cfg.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC11_IN_SEL_CFG")
             .field(
                 "reg_gpio_func11_in_inv_sel",
-                &format_args!("{}", self.reg_gpio_func11_in_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_sig11_in_sel",
-                &format_args!("{}", self.reg_gpio_sig11_in_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func11_in_sel",
-                &format_args!("{}", self.reg_gpio_func11_in_sel().bits()),
+                &self.reg_gpio_func11_in_inv_sel(),
             )
+            .field("reg_gpio_sig11_in_sel", &self.reg_gpio_sig11_in_sel())
+            .field("reg_gpio_func11_in_sel", &self.reg_gpio_func11_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC11_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func11_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func11_out_sel_cfg.rs
index 258f778723..2f1622bdc5 100644
--- a/esp32p4/src/lp_gpio/func11_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func11_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC11_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func11_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func11_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func11_oe_sel",
-                &format_args!("{}", self.reg_gpio_func11_oe_sel().bit()),
+                &self.reg_gpio_func11_oe_inv_sel(),
             )
+            .field("reg_gpio_func11_oe_sel", &self.reg_gpio_func11_oe_sel())
             .field(
                 "reg_gpio_func11_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func11_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func11_out_sel",
-                &format_args!("{}", self.reg_gpio_func11_out_sel().bits()),
+                &self.reg_gpio_func11_out_inv_sel(),
             )
+            .field("reg_gpio_func11_out_sel", &self.reg_gpio_func11_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC11_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func12_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func12_in_sel_cfg.rs
index 729a723478..bc58e35a79 100644
--- a/esp32p4/src/lp_gpio/func12_in_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func12_in_sel_cfg.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC12_IN_SEL_CFG")
             .field(
                 "reg_gpio_func12_in_inv_sel",
-                &format_args!("{}", self.reg_gpio_func12_in_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_sig12_in_sel",
-                &format_args!("{}", self.reg_gpio_sig12_in_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func12_in_sel",
-                &format_args!("{}", self.reg_gpio_func12_in_sel().bits()),
+                &self.reg_gpio_func12_in_inv_sel(),
             )
+            .field("reg_gpio_sig12_in_sel", &self.reg_gpio_sig12_in_sel())
+            .field("reg_gpio_func12_in_sel", &self.reg_gpio_func12_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC12_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func12_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func12_out_sel_cfg.rs
index a414362b94..6cfe632077 100644
--- a/esp32p4/src/lp_gpio/func12_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func12_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC12_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func12_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func12_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func12_oe_sel",
-                &format_args!("{}", self.reg_gpio_func12_oe_sel().bit()),
+                &self.reg_gpio_func12_oe_inv_sel(),
             )
+            .field("reg_gpio_func12_oe_sel", &self.reg_gpio_func12_oe_sel())
             .field(
                 "reg_gpio_func12_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func12_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func12_out_sel",
-                &format_args!("{}", self.reg_gpio_func12_out_sel().bits()),
+                &self.reg_gpio_func12_out_inv_sel(),
             )
+            .field("reg_gpio_func12_out_sel", &self.reg_gpio_func12_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC12_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func13_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func13_in_sel_cfg.rs
index c304897f7d..efe06a201f 100644
--- a/esp32p4/src/lp_gpio/func13_in_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func13_in_sel_cfg.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC13_IN_SEL_CFG")
             .field(
                 "reg_gpio_func13_in_inv_sel",
-                &format_args!("{}", self.reg_gpio_func13_in_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_sig13_in_sel",
-                &format_args!("{}", self.reg_gpio_sig13_in_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func13_in_sel",
-                &format_args!("{}", self.reg_gpio_func13_in_sel().bits()),
+                &self.reg_gpio_func13_in_inv_sel(),
             )
+            .field("reg_gpio_sig13_in_sel", &self.reg_gpio_sig13_in_sel())
+            .field("reg_gpio_func13_in_sel", &self.reg_gpio_func13_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC13_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func13_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func13_out_sel_cfg.rs
index e771929274..5dfe2aff22 100644
--- a/esp32p4/src/lp_gpio/func13_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func13_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC13_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func13_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func13_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func13_oe_sel",
-                &format_args!("{}", self.reg_gpio_func13_oe_sel().bit()),
+                &self.reg_gpio_func13_oe_inv_sel(),
             )
+            .field("reg_gpio_func13_oe_sel", &self.reg_gpio_func13_oe_sel())
             .field(
                 "reg_gpio_func13_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func13_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func13_out_sel",
-                &format_args!("{}", self.reg_gpio_func13_out_sel().bits()),
+                &self.reg_gpio_func13_out_inv_sel(),
             )
+            .field("reg_gpio_func13_out_sel", &self.reg_gpio_func13_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC13_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func14_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func14_out_sel_cfg.rs
index fffdac6177..f29d9a1cfd 100644
--- a/esp32p4/src/lp_gpio/func14_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func14_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC14_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func14_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func14_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func14_oe_sel",
-                &format_args!("{}", self.reg_gpio_func14_oe_sel().bit()),
+                &self.reg_gpio_func14_oe_inv_sel(),
             )
+            .field("reg_gpio_func14_oe_sel", &self.reg_gpio_func14_oe_sel())
             .field(
                 "reg_gpio_func14_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func14_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func14_out_sel",
-                &format_args!("{}", self.reg_gpio_func14_out_sel().bits()),
+                &self.reg_gpio_func14_out_inv_sel(),
             )
+            .field("reg_gpio_func14_out_sel", &self.reg_gpio_func14_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC14_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func15_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func15_out_sel_cfg.rs
index d632e414eb..b363a928fa 100644
--- a/esp32p4/src/lp_gpio/func15_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func15_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC15_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func15_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func15_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func15_oe_sel",
-                &format_args!("{}", self.reg_gpio_func15_oe_sel().bit()),
+                &self.reg_gpio_func15_oe_inv_sel(),
             )
+            .field("reg_gpio_func15_oe_sel", &self.reg_gpio_func15_oe_sel())
             .field(
                 "reg_gpio_func15_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func15_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func15_out_sel",
-                &format_args!("{}", self.reg_gpio_func15_out_sel().bits()),
+                &self.reg_gpio_func15_out_inv_sel(),
             )
+            .field("reg_gpio_func15_out_sel", &self.reg_gpio_func15_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC15_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func1_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func1_in_sel_cfg.rs
index 47bc2c04be..b9313bf917 100644
--- a/esp32p4/src/lp_gpio/func1_in_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func1_in_sel_cfg.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC1_IN_SEL_CFG")
             .field(
                 "reg_gpio_func1_in_inv_sel",
-                &format_args!("{}", self.reg_gpio_func1_in_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_sig1_in_sel",
-                &format_args!("{}", self.reg_gpio_sig1_in_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func1_in_sel",
-                &format_args!("{}", self.reg_gpio_func1_in_sel().bits()),
+                &self.reg_gpio_func1_in_inv_sel(),
             )
+            .field("reg_gpio_sig1_in_sel", &self.reg_gpio_sig1_in_sel())
+            .field("reg_gpio_func1_in_sel", &self.reg_gpio_func1_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC1_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func1_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func1_out_sel_cfg.rs
index f345faf92d..159cf2eae2 100644
--- a/esp32p4/src/lp_gpio/func1_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func1_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC1_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func1_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func1_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func1_oe_sel",
-                &format_args!("{}", self.reg_gpio_func1_oe_sel().bit()),
+                &self.reg_gpio_func1_oe_inv_sel(),
             )
+            .field("reg_gpio_func1_oe_sel", &self.reg_gpio_func1_oe_sel())
             .field(
                 "reg_gpio_func1_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func1_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func1_out_sel",
-                &format_args!("{}", self.reg_gpio_func1_out_sel().bits()),
+                &self.reg_gpio_func1_out_inv_sel(),
             )
+            .field("reg_gpio_func1_out_sel", &self.reg_gpio_func1_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC1_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func2_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func2_in_sel_cfg.rs
index 22c5e0a0e3..d79dc63c63 100644
--- a/esp32p4/src/lp_gpio/func2_in_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func2_in_sel_cfg.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC2_IN_SEL_CFG")
             .field(
                 "reg_gpio_func2_in_inv_sel",
-                &format_args!("{}", self.reg_gpio_func2_in_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_sig2_in_sel",
-                &format_args!("{}", self.reg_gpio_sig2_in_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func2_in_sel",
-                &format_args!("{}", self.reg_gpio_func2_in_sel().bits()),
+                &self.reg_gpio_func2_in_inv_sel(),
             )
+            .field("reg_gpio_sig2_in_sel", &self.reg_gpio_sig2_in_sel())
+            .field("reg_gpio_func2_in_sel", &self.reg_gpio_func2_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC2_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func2_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func2_out_sel_cfg.rs
index 2d545242b6..8a33aab140 100644
--- a/esp32p4/src/lp_gpio/func2_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func2_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC2_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func2_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func2_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func2_oe_sel",
-                &format_args!("{}", self.reg_gpio_func2_oe_sel().bit()),
+                &self.reg_gpio_func2_oe_inv_sel(),
             )
+            .field("reg_gpio_func2_oe_sel", &self.reg_gpio_func2_oe_sel())
             .field(
                 "reg_gpio_func2_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func2_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func2_out_sel",
-                &format_args!("{}", self.reg_gpio_func2_out_sel().bits()),
+                &self.reg_gpio_func2_out_inv_sel(),
             )
+            .field("reg_gpio_func2_out_sel", &self.reg_gpio_func2_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC2_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func3_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func3_in_sel_cfg.rs
index caea68ebc4..b52b111f33 100644
--- a/esp32p4/src/lp_gpio/func3_in_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func3_in_sel_cfg.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC3_IN_SEL_CFG")
             .field(
                 "reg_gpio_func3_in_inv_sel",
-                &format_args!("{}", self.reg_gpio_func3_in_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_sig3_in_sel",
-                &format_args!("{}", self.reg_gpio_sig3_in_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func3_in_sel",
-                &format_args!("{}", self.reg_gpio_func3_in_sel().bits()),
+                &self.reg_gpio_func3_in_inv_sel(),
             )
+            .field("reg_gpio_sig3_in_sel", &self.reg_gpio_sig3_in_sel())
+            .field("reg_gpio_func3_in_sel", &self.reg_gpio_func3_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC3_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func3_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func3_out_sel_cfg.rs
index f1a604fe19..0c22fad979 100644
--- a/esp32p4/src/lp_gpio/func3_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func3_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC3_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func3_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func3_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func3_oe_sel",
-                &format_args!("{}", self.reg_gpio_func3_oe_sel().bit()),
+                &self.reg_gpio_func3_oe_inv_sel(),
             )
+            .field("reg_gpio_func3_oe_sel", &self.reg_gpio_func3_oe_sel())
             .field(
                 "reg_gpio_func3_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func3_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func3_out_sel",
-                &format_args!("{}", self.reg_gpio_func3_out_sel().bits()),
+                &self.reg_gpio_func3_out_inv_sel(),
             )
+            .field("reg_gpio_func3_out_sel", &self.reg_gpio_func3_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC3_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func4_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func4_in_sel_cfg.rs
index a41449faf1..f228aaa933 100644
--- a/esp32p4/src/lp_gpio/func4_in_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func4_in_sel_cfg.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC4_IN_SEL_CFG")
             .field(
                 "reg_gpio_func4_in_inv_sel",
-                &format_args!("{}", self.reg_gpio_func4_in_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_sig4_in_sel",
-                &format_args!("{}", self.reg_gpio_sig4_in_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func4_in_sel",
-                &format_args!("{}", self.reg_gpio_func4_in_sel().bits()),
+                &self.reg_gpio_func4_in_inv_sel(),
             )
+            .field("reg_gpio_sig4_in_sel", &self.reg_gpio_sig4_in_sel())
+            .field("reg_gpio_func4_in_sel", &self.reg_gpio_func4_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC4_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func4_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func4_out_sel_cfg.rs
index 85b7ce3a21..8d923c9a98 100644
--- a/esp32p4/src/lp_gpio/func4_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func4_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC4_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func4_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func4_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func4_oe_sel",
-                &format_args!("{}", self.reg_gpio_func4_oe_sel().bit()),
+                &self.reg_gpio_func4_oe_inv_sel(),
             )
+            .field("reg_gpio_func4_oe_sel", &self.reg_gpio_func4_oe_sel())
             .field(
                 "reg_gpio_func4_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func4_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func4_out_sel",
-                &format_args!("{}", self.reg_gpio_func4_out_sel().bits()),
+                &self.reg_gpio_func4_out_inv_sel(),
             )
+            .field("reg_gpio_func4_out_sel", &self.reg_gpio_func4_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC4_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func5_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func5_in_sel_cfg.rs
index e38f81d269..09e5b9e724 100644
--- a/esp32p4/src/lp_gpio/func5_in_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func5_in_sel_cfg.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC5_IN_SEL_CFG")
             .field(
                 "reg_gpio_func5_in_inv_sel",
-                &format_args!("{}", self.reg_gpio_func5_in_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_sig5_in_sel",
-                &format_args!("{}", self.reg_gpio_sig5_in_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func5_in_sel",
-                &format_args!("{}", self.reg_gpio_func5_in_sel().bits()),
+                &self.reg_gpio_func5_in_inv_sel(),
             )
+            .field("reg_gpio_sig5_in_sel", &self.reg_gpio_sig5_in_sel())
+            .field("reg_gpio_func5_in_sel", &self.reg_gpio_func5_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC5_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func5_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func5_out_sel_cfg.rs
index 61d5eabe24..9fc9af3915 100644
--- a/esp32p4/src/lp_gpio/func5_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func5_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC5_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func5_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func5_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func5_oe_sel",
-                &format_args!("{}", self.reg_gpio_func5_oe_sel().bit()),
+                &self.reg_gpio_func5_oe_inv_sel(),
             )
+            .field("reg_gpio_func5_oe_sel", &self.reg_gpio_func5_oe_sel())
             .field(
                 "reg_gpio_func5_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func5_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func5_out_sel",
-                &format_args!("{}", self.reg_gpio_func5_out_sel().bits()),
+                &self.reg_gpio_func5_out_inv_sel(),
             )
+            .field("reg_gpio_func5_out_sel", &self.reg_gpio_func5_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC5_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func6_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func6_in_sel_cfg.rs
index 0346c9a79a..2df6293ba3 100644
--- a/esp32p4/src/lp_gpio/func6_in_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func6_in_sel_cfg.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC6_IN_SEL_CFG")
             .field(
                 "reg_gpio_func6_in_inv_sel",
-                &format_args!("{}", self.reg_gpio_func6_in_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_sig6_in_sel",
-                &format_args!("{}", self.reg_gpio_sig6_in_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func6_in_sel",
-                &format_args!("{}", self.reg_gpio_func6_in_sel().bits()),
+                &self.reg_gpio_func6_in_inv_sel(),
             )
+            .field("reg_gpio_sig6_in_sel", &self.reg_gpio_sig6_in_sel())
+            .field("reg_gpio_func6_in_sel", &self.reg_gpio_func6_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC6_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func6_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func6_out_sel_cfg.rs
index fdb32a8212..16d29b5e8c 100644
--- a/esp32p4/src/lp_gpio/func6_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func6_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC6_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func6_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func6_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func6_oe_sel",
-                &format_args!("{}", self.reg_gpio_func6_oe_sel().bit()),
+                &self.reg_gpio_func6_oe_inv_sel(),
             )
+            .field("reg_gpio_func6_oe_sel", &self.reg_gpio_func6_oe_sel())
             .field(
                 "reg_gpio_func6_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func6_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func6_out_sel",
-                &format_args!("{}", self.reg_gpio_func6_out_sel().bits()),
+                &self.reg_gpio_func6_out_inv_sel(),
             )
+            .field("reg_gpio_func6_out_sel", &self.reg_gpio_func6_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC6_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func7_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func7_in_sel_cfg.rs
index c0fd486907..765b47c328 100644
--- a/esp32p4/src/lp_gpio/func7_in_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func7_in_sel_cfg.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC7_IN_SEL_CFG")
             .field(
                 "reg_gpio_func7_in_inv_sel",
-                &format_args!("{}", self.reg_gpio_func7_in_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_sig7_in_sel",
-                &format_args!("{}", self.reg_gpio_sig7_in_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func7_in_sel",
-                &format_args!("{}", self.reg_gpio_func7_in_sel().bits()),
+                &self.reg_gpio_func7_in_inv_sel(),
             )
+            .field("reg_gpio_sig7_in_sel", &self.reg_gpio_sig7_in_sel())
+            .field("reg_gpio_func7_in_sel", &self.reg_gpio_func7_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC7_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func7_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func7_out_sel_cfg.rs
index c36aafaf31..ca0f78d753 100644
--- a/esp32p4/src/lp_gpio/func7_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func7_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC7_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func7_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func7_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func7_oe_sel",
-                &format_args!("{}", self.reg_gpio_func7_oe_sel().bit()),
+                &self.reg_gpio_func7_oe_inv_sel(),
             )
+            .field("reg_gpio_func7_oe_sel", &self.reg_gpio_func7_oe_sel())
             .field(
                 "reg_gpio_func7_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func7_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func7_out_sel",
-                &format_args!("{}", self.reg_gpio_func7_out_sel().bits()),
+                &self.reg_gpio_func7_out_inv_sel(),
             )
+            .field("reg_gpio_func7_out_sel", &self.reg_gpio_func7_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC7_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func8_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func8_in_sel_cfg.rs
index 77927c2233..8b37f51aea 100644
--- a/esp32p4/src/lp_gpio/func8_in_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func8_in_sel_cfg.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC8_IN_SEL_CFG")
             .field(
                 "reg_gpio_func8_in_inv_sel",
-                &format_args!("{}", self.reg_gpio_func8_in_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_sig8_in_sel",
-                &format_args!("{}", self.reg_gpio_sig8_in_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func8_in_sel",
-                &format_args!("{}", self.reg_gpio_func8_in_sel().bits()),
+                &self.reg_gpio_func8_in_inv_sel(),
             )
+            .field("reg_gpio_sig8_in_sel", &self.reg_gpio_sig8_in_sel())
+            .field("reg_gpio_func8_in_sel", &self.reg_gpio_func8_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC8_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func8_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func8_out_sel_cfg.rs
index a3004b8671..491d2bc989 100644
--- a/esp32p4/src/lp_gpio/func8_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func8_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC8_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func8_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func8_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func8_oe_sel",
-                &format_args!("{}", self.reg_gpio_func8_oe_sel().bit()),
+                &self.reg_gpio_func8_oe_inv_sel(),
             )
+            .field("reg_gpio_func8_oe_sel", &self.reg_gpio_func8_oe_sel())
             .field(
                 "reg_gpio_func8_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func8_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func8_out_sel",
-                &format_args!("{}", self.reg_gpio_func8_out_sel().bits()),
+                &self.reg_gpio_func8_out_inv_sel(),
             )
+            .field("reg_gpio_func8_out_sel", &self.reg_gpio_func8_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC8_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func9_in_sel_cfg.rs b/esp32p4/src/lp_gpio/func9_in_sel_cfg.rs
index c481e3e7df..491e4fb2ab 100644
--- a/esp32p4/src/lp_gpio/func9_in_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func9_in_sel_cfg.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC9_IN_SEL_CFG")
             .field(
                 "reg_gpio_func9_in_inv_sel",
-                &format_args!("{}", self.reg_gpio_func9_in_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_sig9_in_sel",
-                &format_args!("{}", self.reg_gpio_sig9_in_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func9_in_sel",
-                &format_args!("{}", self.reg_gpio_func9_in_sel().bits()),
+                &self.reg_gpio_func9_in_inv_sel(),
             )
+            .field("reg_gpio_sig9_in_sel", &self.reg_gpio_sig9_in_sel())
+            .field("reg_gpio_func9_in_sel", &self.reg_gpio_func9_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC9_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/func9_out_sel_cfg.rs b/esp32p4/src/lp_gpio/func9_out_sel_cfg.rs
index e2bcc40f36..2b168c5d43 100644
--- a/esp32p4/src/lp_gpio/func9_out_sel_cfg.rs
+++ b/esp32p4/src/lp_gpio/func9_out_sel_cfg.rs
@@ -46,29 +46,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("FUNC9_OUT_SEL_CFG")
             .field(
                 "reg_gpio_func9_oe_inv_sel",
-                &format_args!("{}", self.reg_gpio_func9_oe_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func9_oe_sel",
-                &format_args!("{}", self.reg_gpio_func9_oe_sel().bit()),
+                &self.reg_gpio_func9_oe_inv_sel(),
             )
+            .field("reg_gpio_func9_oe_sel", &self.reg_gpio_func9_oe_sel())
             .field(
                 "reg_gpio_func9_out_inv_sel",
-                &format_args!("{}", self.reg_gpio_func9_out_inv_sel().bit()),
-            )
-            .field(
-                "reg_gpio_func9_out_sel",
-                &format_args!("{}", self.reg_gpio_func9_out_sel().bits()),
+                &self.reg_gpio_func9_out_inv_sel(),
             )
+            .field("reg_gpio_func9_out_sel", &self.reg_gpio_func9_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC9_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/in_.rs b/esp32p4/src/lp_gpio/in_.rs
index 36dfdf1e39..228679673f 100644
--- a/esp32p4/src/lp_gpio/in_.rs
+++ b/esp32p4/src/lp_gpio/in_.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN")
-            .field(
-                "reg_gpio_in_data_next",
-                &format_args!("{}", self.reg_gpio_in_data_next().bits()),
-            )
+            .field("reg_gpio_in_data_next", &self.reg_gpio_in_data_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SPEC;
 impl crate::RegisterSpec for IN_SPEC {
diff --git a/esp32p4/src/lp_gpio/out.rs b/esp32p4/src/lp_gpio/out.rs
index fd461abbcc..67e3da06dc 100644
--- a/esp32p4/src/lp_gpio/out.rs
+++ b/esp32p4/src/lp_gpio/out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT")
-            .field(
-                "reg_gpio_out_data",
-                &format_args!("{}", self.reg_gpio_out_data().bits()),
-            )
+            .field("reg_gpio_out_data", &self.reg_gpio_out_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin0.rs b/esp32p4/src/lp_gpio/pin0.rs
index e644cbb4a2..c75db78092 100644
--- a/esp32p4/src/lp_gpio/pin0.rs
+++ b/esp32p4/src/lp_gpio/pin0.rs
@@ -39,25 +39,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN0")
             .field(
                 "reg_gpio_pin0_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin0_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin0_int_type",
-                &format_args!("{}", self.reg_gpio_pin0_int_type().bits()),
-            )
-            .field(
-                "reg_gpio_pin0_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin0_pad_driver().bit()),
+                &self.reg_gpio_pin0_wakeup_enable(),
             )
+            .field("reg_gpio_pin0_int_type", &self.reg_gpio_pin0_int_type())
+            .field("reg_gpio_pin0_pad_driver", &self.reg_gpio_pin0_pad_driver())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin1.rs b/esp32p4/src/lp_gpio/pin1.rs
index 39d24e466e..0db1392e0c 100644
--- a/esp32p4/src/lp_gpio/pin1.rs
+++ b/esp32p4/src/lp_gpio/pin1.rs
@@ -39,25 +39,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN1")
             .field(
                 "reg_gpio_pin1_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin1_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin1_int_type",
-                &format_args!("{}", self.reg_gpio_pin1_int_type().bits()),
-            )
-            .field(
-                "reg_gpio_pin1_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin1_pad_driver().bit()),
+                &self.reg_gpio_pin1_wakeup_enable(),
             )
+            .field("reg_gpio_pin1_int_type", &self.reg_gpio_pin1_int_type())
+            .field("reg_gpio_pin1_pad_driver", &self.reg_gpio_pin1_pad_driver())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin10.rs b/esp32p4/src/lp_gpio/pin10.rs
index 21a4a3e7fc..0e6c488e2d 100644
--- a/esp32p4/src/lp_gpio/pin10.rs
+++ b/esp32p4/src/lp_gpio/pin10.rs
@@ -39,25 +39,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN10")
             .field(
                 "reg_gpio_pin10_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin10_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin10_int_type",
-                &format_args!("{}", self.reg_gpio_pin10_int_type().bits()),
+                &self.reg_gpio_pin10_wakeup_enable(),
             )
+            .field("reg_gpio_pin10_int_type", &self.reg_gpio_pin10_int_type())
             .field(
                 "reg_gpio_pin10_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin10_pad_driver().bit()),
+                &self.reg_gpio_pin10_pad_driver(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin11.rs b/esp32p4/src/lp_gpio/pin11.rs
index e9e05b077b..fb72bdf1e2 100644
--- a/esp32p4/src/lp_gpio/pin11.rs
+++ b/esp32p4/src/lp_gpio/pin11.rs
@@ -39,25 +39,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN11")
             .field(
                 "reg_gpio_pin11_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin11_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin11_int_type",
-                &format_args!("{}", self.reg_gpio_pin11_int_type().bits()),
+                &self.reg_gpio_pin11_wakeup_enable(),
             )
+            .field("reg_gpio_pin11_int_type", &self.reg_gpio_pin11_int_type())
             .field(
                 "reg_gpio_pin11_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin11_pad_driver().bit()),
+                &self.reg_gpio_pin11_pad_driver(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin12.rs b/esp32p4/src/lp_gpio/pin12.rs
index 346594a30b..f57489bc0a 100644
--- a/esp32p4/src/lp_gpio/pin12.rs
+++ b/esp32p4/src/lp_gpio/pin12.rs
@@ -39,25 +39,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN12")
             .field(
                 "reg_gpio_pin12_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin12_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin12_int_type",
-                &format_args!("{}", self.reg_gpio_pin12_int_type().bits()),
+                &self.reg_gpio_pin12_wakeup_enable(),
             )
+            .field("reg_gpio_pin12_int_type", &self.reg_gpio_pin12_int_type())
             .field(
                 "reg_gpio_pin12_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin12_pad_driver().bit()),
+                &self.reg_gpio_pin12_pad_driver(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin13.rs b/esp32p4/src/lp_gpio/pin13.rs
index f91d7f3047..8ee565ffc0 100644
--- a/esp32p4/src/lp_gpio/pin13.rs
+++ b/esp32p4/src/lp_gpio/pin13.rs
@@ -39,25 +39,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN13")
             .field(
                 "reg_gpio_pin13_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin13_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin13_int_type",
-                &format_args!("{}", self.reg_gpio_pin13_int_type().bits()),
+                &self.reg_gpio_pin13_wakeup_enable(),
             )
+            .field("reg_gpio_pin13_int_type", &self.reg_gpio_pin13_int_type())
             .field(
                 "reg_gpio_pin13_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin13_pad_driver().bit()),
+                &self.reg_gpio_pin13_pad_driver(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin14.rs b/esp32p4/src/lp_gpio/pin14.rs
index 198b6609da..e6a15d1b64 100644
--- a/esp32p4/src/lp_gpio/pin14.rs
+++ b/esp32p4/src/lp_gpio/pin14.rs
@@ -39,25 +39,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN14")
             .field(
                 "reg_gpio_pin14_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin14_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin14_int_type",
-                &format_args!("{}", self.reg_gpio_pin14_int_type().bits()),
+                &self.reg_gpio_pin14_wakeup_enable(),
             )
+            .field("reg_gpio_pin14_int_type", &self.reg_gpio_pin14_int_type())
             .field(
                 "reg_gpio_pin14_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin14_pad_driver().bit()),
+                &self.reg_gpio_pin14_pad_driver(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin15.rs b/esp32p4/src/lp_gpio/pin15.rs
index 2b857d4691..c1c635e335 100644
--- a/esp32p4/src/lp_gpio/pin15.rs
+++ b/esp32p4/src/lp_gpio/pin15.rs
@@ -39,25 +39,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN15")
             .field(
                 "reg_gpio_pin15_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin15_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin15_int_type",
-                &format_args!("{}", self.reg_gpio_pin15_int_type().bits()),
+                &self.reg_gpio_pin15_wakeup_enable(),
             )
+            .field("reg_gpio_pin15_int_type", &self.reg_gpio_pin15_int_type())
             .field(
                 "reg_gpio_pin15_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin15_pad_driver().bit()),
+                &self.reg_gpio_pin15_pad_driver(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin2.rs b/esp32p4/src/lp_gpio/pin2.rs
index 82b608f096..beb40e18e5 100644
--- a/esp32p4/src/lp_gpio/pin2.rs
+++ b/esp32p4/src/lp_gpio/pin2.rs
@@ -39,25 +39,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN2")
             .field(
                 "reg_gpio_pin2_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin2_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin2_int_type",
-                &format_args!("{}", self.reg_gpio_pin2_int_type().bits()),
-            )
-            .field(
-                "reg_gpio_pin2_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin2_pad_driver().bit()),
+                &self.reg_gpio_pin2_wakeup_enable(),
             )
+            .field("reg_gpio_pin2_int_type", &self.reg_gpio_pin2_int_type())
+            .field("reg_gpio_pin2_pad_driver", &self.reg_gpio_pin2_pad_driver())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin3.rs b/esp32p4/src/lp_gpio/pin3.rs
index ac85e02610..487f371713 100644
--- a/esp32p4/src/lp_gpio/pin3.rs
+++ b/esp32p4/src/lp_gpio/pin3.rs
@@ -39,25 +39,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN3")
             .field(
                 "reg_gpio_pin3_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin3_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin3_int_type",
-                &format_args!("{}", self.reg_gpio_pin3_int_type().bits()),
-            )
-            .field(
-                "reg_gpio_pin3_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin3_pad_driver().bit()),
+                &self.reg_gpio_pin3_wakeup_enable(),
             )
+            .field("reg_gpio_pin3_int_type", &self.reg_gpio_pin3_int_type())
+            .field("reg_gpio_pin3_pad_driver", &self.reg_gpio_pin3_pad_driver())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin4.rs b/esp32p4/src/lp_gpio/pin4.rs
index e8ce5c4947..46a13d107e 100644
--- a/esp32p4/src/lp_gpio/pin4.rs
+++ b/esp32p4/src/lp_gpio/pin4.rs
@@ -39,25 +39,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN4")
             .field(
                 "reg_gpio_pin4_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin4_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin4_int_type",
-                &format_args!("{}", self.reg_gpio_pin4_int_type().bits()),
-            )
-            .field(
-                "reg_gpio_pin4_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin4_pad_driver().bit()),
+                &self.reg_gpio_pin4_wakeup_enable(),
             )
+            .field("reg_gpio_pin4_int_type", &self.reg_gpio_pin4_int_type())
+            .field("reg_gpio_pin4_pad_driver", &self.reg_gpio_pin4_pad_driver())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin5.rs b/esp32p4/src/lp_gpio/pin5.rs
index 011b210df6..29b30ebc2f 100644
--- a/esp32p4/src/lp_gpio/pin5.rs
+++ b/esp32p4/src/lp_gpio/pin5.rs
@@ -39,25 +39,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN5")
             .field(
                 "reg_gpio_pin5_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin5_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin5_int_type",
-                &format_args!("{}", self.reg_gpio_pin5_int_type().bits()),
-            )
-            .field(
-                "reg_gpio_pin5_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin5_pad_driver().bit()),
+                &self.reg_gpio_pin5_wakeup_enable(),
             )
+            .field("reg_gpio_pin5_int_type", &self.reg_gpio_pin5_int_type())
+            .field("reg_gpio_pin5_pad_driver", &self.reg_gpio_pin5_pad_driver())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin6.rs b/esp32p4/src/lp_gpio/pin6.rs
index a5000207c9..25641d6a9f 100644
--- a/esp32p4/src/lp_gpio/pin6.rs
+++ b/esp32p4/src/lp_gpio/pin6.rs
@@ -39,25 +39,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN6")
             .field(
                 "reg_gpio_pin6_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin6_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin6_int_type",
-                &format_args!("{}", self.reg_gpio_pin6_int_type().bits()),
-            )
-            .field(
-                "reg_gpio_pin6_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin6_pad_driver().bit()),
+                &self.reg_gpio_pin6_wakeup_enable(),
             )
+            .field("reg_gpio_pin6_int_type", &self.reg_gpio_pin6_int_type())
+            .field("reg_gpio_pin6_pad_driver", &self.reg_gpio_pin6_pad_driver())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin7.rs b/esp32p4/src/lp_gpio/pin7.rs
index 4188e3cd77..818e769944 100644
--- a/esp32p4/src/lp_gpio/pin7.rs
+++ b/esp32p4/src/lp_gpio/pin7.rs
@@ -39,25 +39,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN7")
             .field(
                 "reg_gpio_pin7_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin7_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin7_int_type",
-                &format_args!("{}", self.reg_gpio_pin7_int_type().bits()),
-            )
-            .field(
-                "reg_gpio_pin7_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin7_pad_driver().bit()),
+                &self.reg_gpio_pin7_wakeup_enable(),
             )
+            .field("reg_gpio_pin7_int_type", &self.reg_gpio_pin7_int_type())
+            .field("reg_gpio_pin7_pad_driver", &self.reg_gpio_pin7_pad_driver())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin8.rs b/esp32p4/src/lp_gpio/pin8.rs
index cb4aaea6e4..aea8db4468 100644
--- a/esp32p4/src/lp_gpio/pin8.rs
+++ b/esp32p4/src/lp_gpio/pin8.rs
@@ -39,25 +39,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN8")
             .field(
                 "reg_gpio_pin8_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin8_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin8_int_type",
-                &format_args!("{}", self.reg_gpio_pin8_int_type().bits()),
-            )
-            .field(
-                "reg_gpio_pin8_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin8_pad_driver().bit()),
+                &self.reg_gpio_pin8_wakeup_enable(),
             )
+            .field("reg_gpio_pin8_int_type", &self.reg_gpio_pin8_int_type())
+            .field("reg_gpio_pin8_pad_driver", &self.reg_gpio_pin8_pad_driver())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/pin9.rs b/esp32p4/src/lp_gpio/pin9.rs
index 9205c5028b..44ec02c285 100644
--- a/esp32p4/src/lp_gpio/pin9.rs
+++ b/esp32p4/src/lp_gpio/pin9.rs
@@ -39,25 +39,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("PIN9")
             .field(
                 "reg_gpio_pin9_wakeup_enable",
-                &format_args!("{}", self.reg_gpio_pin9_wakeup_enable().bit()),
-            )
-            .field(
-                "reg_gpio_pin9_int_type",
-                &format_args!("{}", self.reg_gpio_pin9_int_type().bits()),
-            )
-            .field(
-                "reg_gpio_pin9_pad_driver",
-                &format_args!("{}", self.reg_gpio_pin9_pad_driver().bit()),
+                &self.reg_gpio_pin9_wakeup_enable(),
             )
+            .field("reg_gpio_pin9_int_type", &self.reg_gpio_pin9_int_type())
+            .field("reg_gpio_pin9_pad_driver", &self.reg_gpio_pin9_pad_driver())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/status.rs b/esp32p4/src/lp_gpio/status.rs
index 0dac43461f..09fa0dd013 100644
--- a/esp32p4/src/lp_gpio/status.rs
+++ b/esp32p4/src/lp_gpio/status.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field(
-                "reg_gpio_status_data",
-                &format_args!("{}", self.reg_gpio_status_data().bits()),
-            )
+            .field("reg_gpio_status_data", &self.reg_gpio_status_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_gpio/status_next.rs b/esp32p4/src/lp_gpio/status_next.rs
index d3e6f40997..58b9e0fa9a 100644
--- a/esp32p4/src/lp_gpio/status_next.rs
+++ b/esp32p4/src/lp_gpio/status_next.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("STATUS_NEXT")
             .field(
                 "reg_gpio_status_interrupt_next",
-                &format_args!("{}", self.reg_gpio_status_interrupt_next().bits()),
+                &self.reg_gpio_status_interrupt_next(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_NEXT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_NEXT_SPEC;
 impl crate::RegisterSpec for STATUS_NEXT_SPEC {
diff --git a/esp32p4/src/lp_gpio/ver_date.rs b/esp32p4/src/lp_gpio/ver_date.rs
index 9b20917cb7..a1dee0ace3 100644
--- a/esp32p4/src/lp_gpio/ver_date.rs
+++ b/esp32p4/src/lp_gpio/ver_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VER_DATE")
-            .field(
-                "reg_ver_date",
-                &format_args!("{}", self.reg_ver_date().bits()),
-            )
+            .field("reg_ver_date", &self.reg_ver_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VER_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_huk/clk.rs b/esp32p4/src/lp_huk/clk.rs
index 6f7ed22ad7..7379804256 100644
--- a/esp32p4/src/lp_huk/clk.rs
+++ b/esp32p4/src/lp_huk/clk.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field(
-                "mem_cg_force_on",
-                &format_args!("{}", self.mem_cg_force_on().bit()),
-            )
+            .field("en", &self.en())
+            .field("mem_cg_force_on", &self.mem_cg_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to force on register clock gate."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_huk/conf.rs b/esp32p4/src/lp_huk/conf.rs
index 46f5793799..2e128d7ffb 100644
--- a/esp32p4/src/lp_huk/conf.rs
+++ b/esp32p4/src/lp_huk/conf.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CONF")
-            .field("mode", &format_args!("{}", self.mode().bit()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CONF").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/lp_huk/date.rs b/esp32p4/src/lp_huk/date.rs
index 6a556521b2..11a56dbb7c 100644
--- a/esp32p4/src/lp_huk/date.rs
+++ b/esp32p4/src/lp_huk/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/lp_huk/info_mem.rs b/esp32p4/src/lp_huk/info_mem.rs
index 5de860c50d..80c2ed7da5 100644
--- a/esp32p4/src/lp_huk/info_mem.rs
+++ b/esp32p4/src/lp_huk/info_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INFO_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores HUK info.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`info_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`info_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INFO_MEM_SPEC;
diff --git a/esp32p4/src/lp_huk/int_ena.rs b/esp32p4/src/lp_huk/int_ena.rs
index 1974d5a159..df0f73816a 100644
--- a/esp32p4/src/lp_huk/int_ena.rs
+++ b/esp32p4/src/lp_huk/int_ena.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("prep_done", &format_args!("{}", self.prep_done().bit()))
-            .field("proc_done", &format_args!("{}", self.proc_done().bit()))
-            .field("post_done", &format_args!("{}", self.post_done().bit()))
+            .field("prep_done", &self.prep_done())
+            .field("proc_done", &self.proc_done())
+            .field("post_done", &self.post_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the huk_prep_done_int interrupt"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_huk/int_raw.rs b/esp32p4/src/lp_huk/int_raw.rs
index 3f82183722..b531e3170c 100644
--- a/esp32p4/src/lp_huk/int_raw.rs
+++ b/esp32p4/src/lp_huk/int_raw.rs
@@ -27,18 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("prep_done", &format_args!("{}", self.prep_done().bit()))
-            .field("proc_done", &format_args!("{}", self.proc_done().bit()))
-            .field("post_done", &format_args!("{}", self.post_done().bit()))
+            .field("prep_done", &self.prep_done())
+            .field("proc_done", &self.proc_done())
+            .field("post_done", &self.post_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "HUK Generator interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32p4/src/lp_huk/int_st.rs b/esp32p4/src/lp_huk/int_st.rs
index e104ddd77f..682d299273 100644
--- a/esp32p4/src/lp_huk/int_st.rs
+++ b/esp32p4/src/lp_huk/int_st.rs
@@ -27,18 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("prep_done", &format_args!("{}", self.prep_done().bit()))
-            .field("proc_done", &format_args!("{}", self.proc_done().bit()))
-            .field("post_done", &format_args!("{}", self.post_done().bit()))
+            .field("prep_done", &self.prep_done())
+            .field("proc_done", &self.proc_done())
+            .field("post_done", &self.post_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "HUK Generator interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/lp_huk/state.rs b/esp32p4/src/lp_huk/state.rs
index 2de637f20a..935a9ddc5f 100644
--- a/esp32p4/src/lp_huk/state.rs
+++ b/esp32p4/src/lp_huk/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("state", &format_args!("{}", self.state().bits()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "HUK Generator state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32p4/src/lp_huk/status.rs b/esp32p4/src/lp_huk/status.rs
index f4d1b7b4ea..f13a61f28d 100644
--- a/esp32p4/src/lp_huk/status.rs
+++ b/esp32p4/src/lp_huk/status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("status", &format_args!("{}", self.status().bits()))
-            .field("risk_level", &format_args!("{}", self.risk_level().bits()))
+            .field("status", &self.status())
+            .field("risk_level", &self.risk_level())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "HUK Generator HUK status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32p4/src/lp_i2c0/clk_conf.rs b/esp32p4/src/lp_i2c0/clk_conf.rs
index 0c369fb990..8575bb85bf 100644
--- a/esp32p4/src/lp_i2c0/clk_conf.rs
+++ b/esp32p4/src/lp_i2c0/clk_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bit()))
-            .field("sclk_active", &format_args!("{}", self.sclk_active().bit()))
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_active", &self.sclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/comd.rs b/esp32p4/src/lp_i2c0/comd.rs
index dac825d348..bfc17217e0 100644
--- a/esp32p4/src/lp_i2c0/comd.rs
+++ b/esp32p4/src/lp_i2c0/comd.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMD")
-            .field("command", &format_args!("{}", self.command().bits()))
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Configures command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/ctr.rs b/esp32p4/src/lp_i2c0/ctr.rs
index 756d365dc5..6425784977 100644
--- a/esp32p4/src/lp_i2c0/ctr.rs
+++ b/esp32p4/src/lp_i2c0/ctr.rs
@@ -86,44 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTR")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field(
-                "sample_scl_level",
-                &format_args!("{}", self.sample_scl_level().bit()),
-            )
-            .field(
-                "rx_full_ack_level",
-                &format_args!("{}", self.rx_full_ack_level().bit()),
-            )
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "arbitration_en",
-                &format_args!("{}", self.arbitration_en().bit()),
-            )
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("sample_scl_level", &self.sample_scl_level())
+            .field("rx_full_ack_level", &self.rx_full_ack_level())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("clk_en", &self.clk_en())
+            .field("arbitration_en", &self.arbitration_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures the SDA output mode 1: Direct output, 0: Open drain output."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/data.rs b/esp32p4/src/lp_i2c0/data.rs
index 8987c4faf0..9fa567e42f 100644
--- a/esp32p4/src/lp_i2c0/data.rs
+++ b/esp32p4/src/lp_i2c0/data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field("fifo_rdata", &format_args!("{}", self.fifo_rdata().bits()))
+            .field("fifo_rdata", &self.fifo_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Rx FIFO read data.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DATA_SPEC;
 impl crate::RegisterSpec for DATA_SPEC {
diff --git a/esp32p4/src/lp_i2c0/date.rs b/esp32p4/src/lp_i2c0/date.rs
index ef152473f3..8f12d93ac5 100644
--- a/esp32p4/src/lp_i2c0/date.rs
+++ b/esp32p4/src/lp_i2c0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/lp_i2c0/fifo_conf.rs b/esp32p4/src/lp_i2c0/fifo_conf.rs
index 55c8a341de..7497cbcae1 100644
--- a/esp32p4/src/lp_i2c0/fifo_conf.rs
+++ b/esp32p4/src/lp_i2c0/fifo_conf.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CONF")
-            .field(
-                "rxfifo_wm_thrhd",
-                &format_args!("{}", self.rxfifo_wm_thrhd().bits()),
-            )
-            .field(
-                "txfifo_wm_thrhd",
-                &format_args!("{}", self.txfifo_wm_thrhd().bits()),
-            )
-            .field("nonfifo_en", &format_args!("{}", self.nonfifo_en().bit()))
-            .field("rx_fifo_rst", &format_args!("{}", self.rx_fifo_rst().bit()))
-            .field("tx_fifo_rst", &format_args!("{}", self.tx_fifo_rst().bit()))
-            .field("fifo_prt_en", &format_args!("{}", self.fifo_prt_en().bit()))
+            .field("rxfifo_wm_thrhd", &self.rxfifo_wm_thrhd())
+            .field("txfifo_wm_thrhd", &self.txfifo_wm_thrhd())
+            .field("nonfifo_en", &self.nonfifo_en())
+            .field("rx_fifo_rst", &self.rx_fifo_rst())
+            .field("tx_fifo_rst", &self.tx_fifo_rst())
+            .field("fifo_prt_en", &self.fifo_prt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[3:0\\], reg_rxfifo_wm_int_raw bit will be valid."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/fifo_st.rs b/esp32p4/src/lp_i2c0/fifo_st.rs
index 48479cf1c7..3e1d55c6bf 100644
--- a/esp32p4/src/lp_i2c0/fifo_st.rs
+++ b/esp32p4/src/lp_i2c0/fifo_st.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_ST")
-            .field(
-                "rxfifo_raddr",
-                &format_args!("{}", self.rxfifo_raddr().bits()),
-            )
-            .field(
-                "rxfifo_waddr",
-                &format_args!("{}", self.rxfifo_waddr().bits()),
-            )
-            .field(
-                "txfifo_raddr",
-                &format_args!("{}", self.txfifo_raddr().bits()),
-            )
-            .field(
-                "txfifo_waddr",
-                &format_args!("{}", self.txfifo_waddr().bits()),
-            )
+            .field("rxfifo_raddr", &self.rxfifo_raddr())
+            .field("rxfifo_waddr", &self.rxfifo_waddr())
+            .field("txfifo_raddr", &self.txfifo_raddr())
+            .field("txfifo_waddr", &self.txfifo_waddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "FIFO status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_ST_SPEC;
 impl crate::RegisterSpec for FIFO_ST_SPEC {
diff --git a/esp32p4/src/lp_i2c0/filter_cfg.rs b/esp32p4/src/lp_i2c0/filter_cfg.rs
index 45f6761a6d..cd0010ee77 100644
--- a/esp32p4/src/lp_i2c0/filter_cfg.rs
+++ b/esp32p4/src/lp_i2c0/filter_cfg.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CFG")
-            .field(
-                "scl_filter_thres",
-                &format_args!("{}", self.scl_filter_thres().bits()),
-            )
-            .field(
-                "sda_filter_thres",
-                &format_args!("{}", self.sda_filter_thres().bits()),
-            )
-            .field(
-                "scl_filter_en",
-                &format_args!("{}", self.scl_filter_en().bit()),
-            )
-            .field(
-                "sda_filter_en",
-                &format_args!("{}", self.sda_filter_en().bit()),
-            )
+            .field("scl_filter_thres", &self.scl_filter_thres())
+            .field("sda_filter_thres", &self.sda_filter_thres())
+            .field("scl_filter_en", &self.scl_filter_en())
+            .field("sda_filter_en", &self.sda_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/int_ena.rs b/esp32p4/src/lp_i2c0/int_ena.rs
index 49ddad4190..144796a6c2 100644
--- a/esp32p4/src/lp_i2c0/int_ena.rs
+++ b/esp32p4/src/lp_i2c0/int_ena.rs
@@ -152,46 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to anable I2C_RXFIFO_WM_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/int_raw.rs b/esp32p4/src/lp_i2c0/int_raw.rs
index ca5e8dae9b..6b110d53ce 100644
--- a/esp32p4/src/lp_i2c0/int_raw.rs
+++ b/esp32p4/src/lp_i2c0/int_raw.rs
@@ -118,46 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32p4/src/lp_i2c0/int_st.rs b/esp32p4/src/lp_i2c0/int_st.rs
index 701d45384d..63af868c3a 100644
--- a/esp32p4/src/lp_i2c0/int_st.rs
+++ b/esp32p4/src/lp_i2c0/int_st.rs
@@ -118,46 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of captured I2C communication events\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/lp_i2c0/rxfifo_start_addr.rs b/esp32p4/src/lp_i2c0/rxfifo_start_addr.rs
index 067266ecf1..1f42f0bb10 100644
--- a/esp32p4/src/lp_i2c0/rxfifo_start_addr.rs
+++ b/esp32p4/src/lp_i2c0/rxfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXFIFO_START_ADDR")
-            .field(
-                "rxfifo_start_addr",
-                &format_args!("{}", self.rxfifo_start_addr().bits()),
-            )
+            .field("rxfifo_start_addr", &self.rxfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C RXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for RXFIFO_START_ADDR_SPEC {
diff --git a/esp32p4/src/lp_i2c0/scl_high_period.rs b/esp32p4/src/lp_i2c0/scl_high_period.rs
index 1c3e204567..1df7cb180b 100644
--- a/esp32p4/src/lp_i2c0/scl_high_period.rs
+++ b/esp32p4/src/lp_i2c0/scl_high_period.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH_PERIOD")
-            .field(
-                "scl_high_period",
-                &format_args!("{}", self.scl_high_period().bits()),
-            )
-            .field(
-                "scl_wait_high_period",
-                &format_args!("{}", self.scl_wait_high_period().bits()),
-            )
+            .field("scl_high_period", &self.scl_high_period())
+            .field("scl_wait_high_period", &self.scl_wait_high_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures for how long SCL remains high in master mode. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/scl_low_period.rs b/esp32p4/src/lp_i2c0/scl_low_period.rs
index 8a350c9994..16d7c4df30 100644
--- a/esp32p4/src/lp_i2c0/scl_low_period.rs
+++ b/esp32p4/src/lp_i2c0/scl_low_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW_PERIOD")
-            .field(
-                "scl_low_period",
-                &format_args!("{}", self.scl_low_period().bits()),
-            )
+            .field("scl_low_period", &self.scl_low_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures the low level width of the SCL Clock. Measurement unit: i2c_sclk."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/scl_main_st_time_out.rs b/esp32p4/src/lp_i2c0/scl_main_st_time_out.rs
index 4aecde25ab..ab1bc1474e 100644
--- a/esp32p4/src/lp_i2c0/scl_main_st_time_out.rs
+++ b/esp32p4/src/lp_i2c0/scl_main_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_MAIN_ST_TIME_OUT")
-            .field(
-                "scl_main_st_to_i2c",
-                &format_args!("{}", self.scl_main_st_to_i2c().bits()),
-            )
+            .field("scl_main_st_to_i2c", &self.scl_main_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_MAIN_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/scl_rstart_setup.rs b/esp32p4/src/lp_i2c0/scl_rstart_setup.rs
index c8bc95dba1..522b4ff4ef 100644
--- a/esp32p4/src/lp_i2c0/scl_rstart_setup.rs
+++ b/esp32p4/src/lp_i2c0/scl_rstart_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_RSTART_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_RSTART_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/scl_sp_conf.rs b/esp32p4/src/lp_i2c0/scl_sp_conf.rs
index ce31615629..87609a228b 100644
--- a/esp32p4/src/lp_i2c0/scl_sp_conf.rs
+++ b/esp32p4/src/lp_i2c0/scl_sp_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_SP_CONF")
-            .field(
-                "scl_rst_slv_en",
-                &format_args!("{}", self.scl_rst_slv_en().bit()),
-            )
-            .field(
-                "scl_rst_slv_num",
-                &format_args!("{}", self.scl_rst_slv_num().bits()),
-            )
-            .field("scl_pd_en", &format_args!("{}", self.scl_pd_en().bit()))
-            .field("sda_pd_en", &format_args!("{}", self.sda_pd_en().bit()))
+            .field("scl_rst_slv_en", &self.scl_rst_slv_en())
+            .field("scl_rst_slv_num", &self.scl_rst_slv_num())
+            .field("scl_pd_en", &self.scl_pd_en())
+            .field("sda_pd_en", &self.sda_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_SP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/scl_st_time_out.rs b/esp32p4/src/lp_i2c0/scl_st_time_out.rs
index c9a6f6d300..28832dad1f 100644
--- a/esp32p4/src/lp_i2c0/scl_st_time_out.rs
+++ b/esp32p4/src/lp_i2c0/scl_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_ST_TIME_OUT")
-            .field(
-                "scl_st_to_i2c",
-                &format_args!("{}", self.scl_st_to_i2c().bits()),
-            )
+            .field("scl_st_to_i2c", &self.scl_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/scl_start_hold.rs b/esp32p4/src/lp_i2c0/scl_start_hold.rs
index 87e4288b59..e9a36d3973 100644
--- a/esp32p4/src/lp_i2c0/scl_start_hold.rs
+++ b/esp32p4/src/lp_i2c0/scl_start_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition. Measurement unit: i2c_sclk."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/scl_stop_hold.rs b/esp32p4/src/lp_i2c0/scl_stop_hold.rs
index aac05a54ef..52e10c120f 100644
--- a/esp32p4/src/lp_i2c0/scl_stop_hold.rs
+++ b/esp32p4/src/lp_i2c0/scl_stop_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures the delay after the STOP condition. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/scl_stop_setup.rs b/esp32p4/src/lp_i2c0/scl_stop_setup.rs
index 622f83cd8e..a8e9e43d1b 100644
--- a/esp32p4/src/lp_i2c0/scl_stop_setup.rs
+++ b/esp32p4/src/lp_i2c0/scl_stop_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures the time between the rising edge of SCL and the rising edge of SDA. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/sda_hold.rs b/esp32p4/src/lp_i2c0/sda_hold.rs
index dc93a49e22..ff54b9533d 100644
--- a/esp32p4/src/lp_i2c0/sda_hold.rs
+++ b/esp32p4/src/lp_i2c0/sda_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures the time to hold the data after the falling edge of SCL. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/sda_sample.rs b/esp32p4/src/lp_i2c0/sda_sample.rs
index fed1f6154d..24ede7a043 100644
--- a/esp32p4/src/lp_i2c0/sda_sample.rs
+++ b/esp32p4/src/lp_i2c0/sda_sample.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_SAMPLE")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Configures the sample time after a positive SCL edge. Measurement unit: i2c_sclk"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/sr.rs b/esp32p4/src/lp_i2c0/sr.rs
index e2d299a3c9..e71d53b285 100644
--- a/esp32p4/src/lp_i2c0/sr.rs
+++ b/esp32p4/src/lp_i2c0/sr.rs
@@ -55,28 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR")
-            .field("resp_rec", &format_args!("{}", self.resp_rec().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field(
-                "scl_main_state_last",
-                &format_args!("{}", self.scl_main_state_last().bits()),
-            )
-            .field(
-                "scl_state_last",
-                &format_args!("{}", self.scl_state_last().bits()),
-            )
+            .field("resp_rec", &self.resp_rec())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("scl_main_state_last", &self.scl_main_state_last())
+            .field("scl_state_last", &self.scl_state_last())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Describe I2C work status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SR_SPEC;
 impl crate::RegisterSpec for SR_SPEC {
diff --git a/esp32p4/src/lp_i2c0/to.rs b/esp32p4/src/lp_i2c0/to.rs
index 671fc7e961..17a2cd5f55 100644
--- a/esp32p4/src/lp_i2c0/to.rs
+++ b/esp32p4/src/lp_i2c0/to.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO")
-            .field(
-                "time_out_value",
-                &format_args!("{}", self.time_out_value().bits()),
-            )
-            .field("time_out_en", &format_args!("{}", self.time_out_en().bit()))
+            .field("time_out_value", &self.time_out_value())
+            .field("time_out_en", &self.time_out_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value). Measurement unit: i2c_sclk."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c0/txfifo_start_addr.rs b/esp32p4/src/lp_i2c0/txfifo_start_addr.rs
index a56802879f..93b2a29e2e 100644
--- a/esp32p4/src/lp_i2c0/txfifo_start_addr.rs
+++ b/esp32p4/src/lp_i2c0/txfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXFIFO_START_ADDR")
-            .field(
-                "txfifo_start_addr",
-                &format_args!("{}", self.txfifo_start_addr().bits()),
-            )
+            .field("txfifo_start_addr", &self.txfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C TXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for TXFIFO_START_ADDR_SPEC {
diff --git a/esp32p4/src/lp_i2c_ana_mst/ana_conf0.rs b/esp32p4/src/lp_i2c_ana_mst/ana_conf0.rs
index f6aaf0228f..3fd987e946 100644
--- a/esp32p4/src/lp_i2c_ana_mst/ana_conf0.rs
+++ b/esp32p4/src/lp_i2c_ana_mst/ana_conf0.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ANA_CONF0")
-            .field("ana_conf0", &format_args!("{}", self.ana_conf0().bits()))
-            .field(
-                "ana_status0",
-                &format_args!("{}", self.ana_status0().bits()),
-            )
+            .field("ana_conf0", &self.ana_conf0())
+            .field("ana_status0", &self.ana_status0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ANA_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - need des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c_ana_mst/ana_conf1.rs b/esp32p4/src/lp_i2c_ana_mst/ana_conf1.rs
index 1cd73998a0..f9b1b0018d 100644
--- a/esp32p4/src/lp_i2c_ana_mst/ana_conf1.rs
+++ b/esp32p4/src/lp_i2c_ana_mst/ana_conf1.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ANA_CONF1")
-            .field("ana_conf1", &format_args!("{}", self.ana_conf1().bits()))
-            .field(
-                "ana_status1",
-                &format_args!("{}", self.ana_status1().bits()),
-            )
+            .field("ana_conf1", &self.ana_conf1())
+            .field("ana_status1", &self.ana_status1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ANA_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - need des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c_ana_mst/ana_conf2.rs b/esp32p4/src/lp_i2c_ana_mst/ana_conf2.rs
index f10f061a9e..e963187437 100644
--- a/esp32p4/src/lp_i2c_ana_mst/ana_conf2.rs
+++ b/esp32p4/src/lp_i2c_ana_mst/ana_conf2.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ANA_CONF2")
-            .field("ana_conf2", &format_args!("{}", self.ana_conf2().bits()))
-            .field(
-                "ana_status2",
-                &format_args!("{}", self.ana_status2().bits()),
-            )
+            .field("ana_conf2", &self.ana_conf2())
+            .field("ana_status2", &self.ana_status2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ANA_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - need des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c_ana_mst/clk160m.rs b/esp32p4/src/lp_i2c_ana_mst/clk160m.rs
index e0102fe6b5..bd366c05fa 100644
--- a/esp32p4/src/lp_i2c_ana_mst/clk160m.rs
+++ b/esp32p4/src/lp_i2c_ana_mst/clk160m.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK160M")
-            .field(
-                "clk_i2c_mst_sel_160m",
-                &format_args!("{}", self.clk_i2c_mst_sel_160m().bit()),
-            )
+            .field("clk_i2c_mst_sel_160m", &self.clk_i2c_mst_sel_160m())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK160M_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c_ana_mst/date.rs b/esp32p4/src/lp_i2c_ana_mst/date.rs
index 9786d9e5b3..a4bf5bf68b 100644
--- a/esp32p4/src/lp_i2c_ana_mst/date.rs
+++ b/esp32p4/src/lp_i2c_ana_mst/date.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .field(
-                "i2c_mst_clk_en",
-                &format_args!("{}", self.i2c_mst_clk_en().bit()),
-            )
+            .field("date", &self.date())
+            .field("i2c_mst_clk_en", &self.i2c_mst_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - need des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c_ana_mst/hw_i2c_ctrl.rs b/esp32p4/src/lp_i2c_ana_mst/hw_i2c_ctrl.rs
index 9c676c4312..fed16029d9 100644
--- a/esp32p4/src/lp_i2c_ana_mst/hw_i2c_ctrl.rs
+++ b/esp32p4/src/lp_i2c_ana_mst/hw_i2c_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HW_I2C_CTRL")
-            .field(
-                "hw_i2c_scl_pulse_dur",
-                &format_args!("{}", self.hw_i2c_scl_pulse_dur().bits()),
-            )
-            .field(
-                "hw_i2c_sda_side_guard",
-                &format_args!("{}", self.hw_i2c_sda_side_guard().bits()),
-            )
-            .field("arbiter_dis", &format_args!("{}", self.arbiter_dis().bit()))
+            .field("hw_i2c_scl_pulse_dur", &self.hw_i2c_scl_pulse_dur())
+            .field("hw_i2c_sda_side_guard", &self.hw_i2c_sda_side_guard())
+            .field("arbiter_dis", &self.arbiter_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HW_I2C_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - need des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c0_conf.rs b/esp32p4/src/lp_i2c_ana_mst/i2c0_conf.rs
index 9cffc14c01..e764403200 100644
--- a/esp32p4/src/lp_i2c_ana_mst/i2c0_conf.rs
+++ b/esp32p4/src/lp_i2c_ana_mst/i2c0_conf.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C0_CONF")
-            .field("i2c0_conf", &format_args!("{}", self.i2c0_conf().bits()))
-            .field(
-                "i2c0_status",
-                &format_args!("{}", self.i2c0_status().bits()),
-            )
+            .field("i2c0_conf", &self.i2c0_conf())
+            .field("i2c0_status", &self.i2c0_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C0_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - need des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c0_ctrl.rs b/esp32p4/src/lp_i2c_ana_mst/i2c0_ctrl.rs
index 2a4077d5f5..df55da2665 100644
--- a/esp32p4/src/lp_i2c_ana_mst/i2c0_ctrl.rs
+++ b/esp32p4/src/lp_i2c_ana_mst/i2c0_ctrl.rs
@@ -24,17 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C0_CTRL")
-            .field("i2c0_ctrl", &format_args!("{}", self.i2c0_ctrl().bits()))
-            .field("i2c0_busy", &format_args!("{}", self.i2c0_busy().bit()))
+            .field("i2c0_ctrl", &self.i2c0_ctrl())
+            .field("i2c0_busy", &self.i2c0_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C0_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:24 - need des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c0_ctrl1.rs b/esp32p4/src/lp_i2c_ana_mst/i2c0_ctrl1.rs
index d38155994c..a34b88781f 100644
--- a/esp32p4/src/lp_i2c_ana_mst/i2c0_ctrl1.rs
+++ b/esp32p4/src/lp_i2c_ana_mst/i2c0_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C0_CTRL1")
-            .field(
-                "i2c0_scl_pulse_dur",
-                &format_args!("{}", self.i2c0_scl_pulse_dur().bits()),
-            )
-            .field(
-                "i2c0_sda_side_guard",
-                &format_args!("{}", self.i2c0_sda_side_guard().bits()),
-            )
+            .field("i2c0_scl_pulse_dur", &self.i2c0_scl_pulse_dur())
+            .field("i2c0_sda_side_guard", &self.i2c0_sda_side_guard())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C0_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - need des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c1_conf.rs b/esp32p4/src/lp_i2c_ana_mst/i2c1_conf.rs
index 025a9e3b4e..6fffecc8dc 100644
--- a/esp32p4/src/lp_i2c_ana_mst/i2c1_conf.rs
+++ b/esp32p4/src/lp_i2c_ana_mst/i2c1_conf.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C1_CONF")
-            .field("i2c1_conf", &format_args!("{}", self.i2c1_conf().bits()))
-            .field(
-                "i2c1_status",
-                &format_args!("{}", self.i2c1_status().bits()),
-            )
+            .field("i2c1_conf", &self.i2c1_conf())
+            .field("i2c1_status", &self.i2c1_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C1_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - need des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c1_ctrl.rs b/esp32p4/src/lp_i2c_ana_mst/i2c1_ctrl.rs
index e4e9bc2aab..338c804581 100644
--- a/esp32p4/src/lp_i2c_ana_mst/i2c1_ctrl.rs
+++ b/esp32p4/src/lp_i2c_ana_mst/i2c1_ctrl.rs
@@ -24,17 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C1_CTRL")
-            .field("i2c1_ctrl", &format_args!("{}", self.i2c1_ctrl().bits()))
-            .field("i2c1_busy", &format_args!("{}", self.i2c1_busy().bit()))
+            .field("i2c1_ctrl", &self.i2c1_ctrl())
+            .field("i2c1_busy", &self.i2c1_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C1_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:24 - need des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c1_ctrl1.rs b/esp32p4/src/lp_i2c_ana_mst/i2c1_ctrl1.rs
index 31811b916d..c2f3a23d61 100644
--- a/esp32p4/src/lp_i2c_ana_mst/i2c1_ctrl1.rs
+++ b/esp32p4/src/lp_i2c_ana_mst/i2c1_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C1_CTRL1")
-            .field(
-                "i2c1_scl_pulse_dur",
-                &format_args!("{}", self.i2c1_scl_pulse_dur().bits()),
-            )
-            .field(
-                "i2c1_sda_side_guard",
-                &format_args!("{}", self.i2c1_sda_side_guard().bits()),
-            )
+            .field("i2c1_scl_pulse_dur", &self.i2c1_scl_pulse_dur())
+            .field("i2c1_sda_side_guard", &self.i2c1_sda_side_guard())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C1_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - need des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c_burst_conf.rs b/esp32p4/src/lp_i2c_ana_mst/i2c_burst_conf.rs
index e71963e1e7..5262802950 100644
--- a/esp32p4/src/lp_i2c_ana_mst/i2c_burst_conf.rs
+++ b/esp32p4/src/lp_i2c_ana_mst/i2c_burst_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_BURST_CONF")
-            .field(
-                "i2c_mst_burst_ctrl",
-                &format_args!("{}", self.i2c_mst_burst_ctrl().bits()),
-            )
+            .field("i2c_mst_burst_ctrl", &self.i2c_mst_burst_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_BURST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c_ana_mst/i2c_burst_status.rs b/esp32p4/src/lp_i2c_ana_mst/i2c_burst_status.rs
index 00ccb14c82..f9e65b31d4 100644
--- a/esp32p4/src/lp_i2c_ana_mst/i2c_burst_status.rs
+++ b/esp32p4/src/lp_i2c_ana_mst/i2c_burst_status.rs
@@ -38,31 +38,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_BURST_STATUS")
-            .field(
-                "i2c_mst_burst_done",
-                &format_args!("{}", self.i2c_mst_burst_done().bit()),
-            )
-            .field(
-                "i2c_mst0_burst_err_flag",
-                &format_args!("{}", self.i2c_mst0_burst_err_flag().bit()),
-            )
-            .field(
-                "i2c_mst1_burst_err_flag",
-                &format_args!("{}", self.i2c_mst1_burst_err_flag().bit()),
-            )
+            .field("i2c_mst_burst_done", &self.i2c_mst_burst_done())
+            .field("i2c_mst0_burst_err_flag", &self.i2c_mst0_burst_err_flag())
+            .field("i2c_mst1_burst_err_flag", &self.i2c_mst1_burst_err_flag())
             .field(
                 "i2c_mst_burst_timeout_cnt",
-                &format_args!("{}", self.i2c_mst_burst_timeout_cnt().bits()),
+                &self.i2c_mst_burst_timeout_cnt(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_BURST_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:31 - need des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2c_ana_mst/nouse.rs b/esp32p4/src/lp_i2c_ana_mst/nouse.rs
index ec434e8e9d..354baa8fef 100644
--- a/esp32p4/src/lp_i2c_ana_mst/nouse.rs
+++ b/esp32p4/src/lp_i2c_ana_mst/nouse.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NOUSE")
-            .field(
-                "i2c_mst_nouse",
-                &format_args!("{}", self.i2c_mst_nouse().bits()),
-            )
+            .field("i2c_mst_nouse", &self.i2c_mst_nouse())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NOUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/clk_gate.rs b/esp32p4/src/lp_i2s0/clk_gate.rs
index 459a3cd42d..c1bc1d882e 100644
--- a/esp32p4/src/lp_i2s0/clk_gate.rs
+++ b/esp32p4/src/lp_i2s0/clk_gate.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "vad_cg_force_on",
-                &format_args!("{}", self.vad_cg_force_on().bit()),
-            )
-            .field(
-                "rx_mem_cg_force_on",
-                &format_args!("{}", self.rx_mem_cg_force_on().bit()),
-            )
-            .field(
-                "rx_reg_cg_force_on",
-                &format_args!("{}", self.rx_reg_cg_force_on().bit()),
-            )
+            .field("clk_en", &self.clk_en())
+            .field("vad_cg_force_on", &self.vad_cg_force_on())
+            .field("rx_mem_cg_force_on", &self.rx_mem_cg_force_on())
+            .field("rx_reg_cg_force_on", &self.rx_reg_cg_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this bit to enable clock gate"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/conf_sigle_data.rs b/esp32p4/src/lp_i2s0/conf_sigle_data.rs
index f979345988..3c75f59255 100644
--- a/esp32p4/src/lp_i2s0/conf_sigle_data.rs
+++ b/esp32p4/src/lp_i2s0/conf_sigle_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_SIGLE_DATA")
-            .field(
-                "single_data",
-                &format_args!("{}", self.single_data().bits()),
-            )
+            .field("single_data", &self.single_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SIGLE_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The configured constant channel data to be sent out."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/date.rs b/esp32p4/src/lp_i2s0/date.rs
index 95fef3f77e..a972dd6b53 100644
--- a/esp32p4/src/lp_i2s0/date.rs
+++ b/esp32p4/src/lp_i2s0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/lp_i2s0/eco_conf.rs b/esp32p4/src/lp_i2s0/eco_conf.rs
index dccd32b675..6324285692 100644
--- a/esp32p4/src/lp_i2s0/eco_conf.rs
+++ b/esp32p4/src/lp_i2s0/eco_conf.rs
@@ -24,17 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_CONF")
-            .field("rdn_ena", &format_args!("{}", self.rdn_ena().bit()))
-            .field("rdn_result", &format_args!("{}", self.rdn_result().bit()))
+            .field("rdn_ena", &self.rdn_ena())
+            .field("rdn_result", &self.rdn_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable rdn counter bit"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/eco_high.rs b/esp32p4/src/lp_i2s0/eco_high.rs
index 30d36a5764..576ffe9af0 100644
--- a/esp32p4/src/lp_i2s0/eco_high.rs
+++ b/esp32p4/src/lp_i2s0/eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_HIGH")
-            .field(
-                "rdn_eco_high",
-                &format_args!("{}", self.rdn_eco_high().bits()),
-            )
+            .field("rdn_eco_high", &self.rdn_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - logic high eco registers"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/eco_low.rs b/esp32p4/src/lp_i2s0/eco_low.rs
index 036fc0320f..3ab4af4c26 100644
--- a/esp32p4/src/lp_i2s0/eco_low.rs
+++ b/esp32p4/src/lp_i2s0/eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_LOW")
-            .field(
-                "rdn_eco_low",
-                &format_args!("{}", self.rdn_eco_low().bits()),
-            )
+            .field("rdn_eco_low", &self.rdn_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - logic low eco registers"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/int_ena.rs b/esp32p4/src/lp_i2s0/int_ena.rs
index 196537a937..256006cc97 100644
--- a/esp32p4/src/lp_i2s0/int_ena.rs
+++ b/esp32p4/src/lp_i2s0/int_ena.rs
@@ -62,30 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field(
-                "rx_fifomem_udf",
-                &format_args!("{}", self.rx_fifomem_udf().bit()),
-            )
-            .field("lp_vad_done", &format_args!("{}", self.lp_vad_done().bit()))
-            .field(
-                "lp_vad_reset_done",
-                &format_args!("{}", self.lp_vad_reset_done().bit()),
-            )
-            .field(
-                "rx_mem_threshold",
-                &format_args!("{}", self.rx_mem_threshold().bit()),
-            )
+            .field("rx_done", &self.rx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("rx_fifomem_udf", &self.rx_fifomem_udf())
+            .field("lp_vad_done", &self.lp_vad_done())
+            .field("lp_vad_reset_done", &self.lp_vad_reset_done())
+            .field("rx_mem_threshold", &self.rx_mem_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/int_raw.rs b/esp32p4/src/lp_i2s0/int_raw.rs
index c9469534de..62d806120d 100644
--- a/esp32p4/src/lp_i2s0/int_raw.rs
+++ b/esp32p4/src/lp_i2s0/int_raw.rs
@@ -48,30 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field(
-                "rx_fifomem_udf",
-                &format_args!("{}", self.rx_fifomem_udf().bit()),
-            )
-            .field("vad_done", &format_args!("{}", self.vad_done().bit()))
-            .field(
-                "vad_reset_done",
-                &format_args!("{}", self.vad_reset_done().bit()),
-            )
-            .field(
-                "rx_mem_threshold",
-                &format_args!("{}", self.rx_mem_threshold().bit()),
-            )
+            .field("rx_done", &self.rx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("rx_fifomem_udf", &self.rx_fifomem_udf())
+            .field("vad_done", &self.vad_done())
+            .field("vad_reset_done", &self.vad_reset_done())
+            .field("rx_mem_threshold", &self.rx_mem_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32p4/src/lp_i2s0/int_st.rs b/esp32p4/src/lp_i2s0/int_st.rs
index 6dda97ec0b..1b5533bee0 100644
--- a/esp32p4/src/lp_i2s0/int_st.rs
+++ b/esp32p4/src/lp_i2s0/int_st.rs
@@ -48,30 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field(
-                "rx_fifomem_udf",
-                &format_args!("{}", self.rx_fifomem_udf().bit()),
-            )
-            .field("lp_vad_done", &format_args!("{}", self.lp_vad_done().bit()))
-            .field(
-                "lp_vad_reset_done",
-                &format_args!("{}", self.lp_vad_reset_done().bit()),
-            )
-            .field(
-                "rx_mem_threshold",
-                &format_args!("{}", self.rx_mem_threshold().bit()),
-            )
+            .field("rx_done", &self.rx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("rx_fifomem_udf", &self.rx_fifomem_udf())
+            .field("lp_vad_done", &self.lp_vad_done())
+            .field("lp_vad_reset_done", &self.lp_vad_reset_done())
+            .field("rx_mem_threshold", &self.rx_mem_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/lp_i2s0/lc_hung_conf.rs b/esp32p4/src/lp_i2s0/lc_hung_conf.rs
index 060b1cdb60..71f0c84fa7 100644
--- a/esp32p4/src/lp_i2s0/lc_hung_conf.rs
+++ b/esp32p4/src/lp_i2s0/lc_hung_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_HUNG_CONF")
-            .field(
-                "lc_fifo_timeout",
-                &format_args!("{}", self.lc_fifo_timeout().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_shift",
-                &format_args!("{}", self.lc_fifo_timeout_shift().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_ena",
-                &format_args!("{}", self.lc_fifo_timeout_ena().bit()),
-            )
+            .field("lc_fifo_timeout", &self.lc_fifo_timeout())
+            .field("lc_fifo_timeout_shift", &self.lc_fifo_timeout_shift())
+            .field("lc_fifo_timeout_ena", &self.lc_fifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/rx_conf.rs b/esp32p4/src/lp_i2s0/rx_conf.rs
index cc49507178..d15fa45115 100644
--- a/esp32p4/src/lp_i2s0/rx_conf.rs
+++ b/esp32p4/src/lp_i2s0/rx_conf.rs
@@ -149,60 +149,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CONF")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field(
-                "rx_slave_mod",
-                &format_args!("{}", self.rx_slave_mod().bit()),
-            )
-            .field("rx_mono", &format_args!("{}", self.rx_mono().bit()))
-            .field(
-                "rx_big_endian",
-                &format_args!("{}", self.rx_big_endian().bit()),
-            )
-            .field("rx_update", &format_args!("{}", self.rx_update().bit()))
-            .field(
-                "rx_mono_fst_vld",
-                &format_args!("{}", self.rx_mono_fst_vld().bit()),
-            )
-            .field(
-                "rx_pcm_conf",
-                &format_args!("{}", self.rx_pcm_conf().bits()),
-            )
-            .field(
-                "rx_pcm_bypass",
-                &format_args!("{}", self.rx_pcm_bypass().bit()),
-            )
-            .field(
-                "rx_stop_mode",
-                &format_args!("{}", self.rx_stop_mode().bits()),
-            )
-            .field(
-                "rx_left_align",
-                &format_args!("{}", self.rx_left_align().bit()),
-            )
-            .field(
-                "rx_24_fill_en",
-                &format_args!("{}", self.rx_24_fill_en().bit()),
-            )
-            .field(
-                "rx_ws_idle_pol",
-                &format_args!("{}", self.rx_ws_idle_pol().bit()),
-            )
-            .field(
-                "rx_bit_order",
-                &format_args!("{}", self.rx_bit_order().bit()),
-            )
-            .field("rx_tdm_en", &format_args!("{}", self.rx_tdm_en().bit()))
-            .field("rx_pdm_en", &format_args!("{}", self.rx_pdm_en().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("rx_slave_mod", &self.rx_slave_mod())
+            .field("rx_mono", &self.rx_mono())
+            .field("rx_big_endian", &self.rx_big_endian())
+            .field("rx_update", &self.rx_update())
+            .field("rx_mono_fst_vld", &self.rx_mono_fst_vld())
+            .field("rx_pcm_conf", &self.rx_pcm_conf())
+            .field("rx_pcm_bypass", &self.rx_pcm_bypass())
+            .field("rx_stop_mode", &self.rx_stop_mode())
+            .field("rx_left_align", &self.rx_left_align())
+            .field("rx_24_fill_en", &self.rx_24_fill_en())
+            .field("rx_ws_idle_pol", &self.rx_ws_idle_pol())
+            .field("rx_bit_order", &self.rx_bit_order())
+            .field("rx_tdm_en", &self.rx_tdm_en())
+            .field("rx_pdm_en", &self.rx_pdm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset receiver"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/rx_conf1.rs b/esp32p4/src/lp_i2s0/rx_conf1.rs
index 24c13494fb..31fa7a1f88 100644
--- a/esp32p4/src/lp_i2s0/rx_conf1.rs
+++ b/esp32p4/src/lp_i2s0/rx_conf1.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CONF1")
-            .field(
-                "rx_tdm_ws_width",
-                &format_args!("{}", self.rx_tdm_ws_width().bits()),
-            )
-            .field(
-                "rx_bck_div_num",
-                &format_args!("{}", self.rx_bck_div_num().bits()),
-            )
-            .field(
-                "rx_bits_mod",
-                &format_args!("{}", self.rx_bits_mod().bits()),
-            )
-            .field(
-                "rx_half_sample_bits",
-                &format_args!("{}", self.rx_half_sample_bits().bits()),
-            )
-            .field(
-                "rx_tdm_chan_bits",
-                &format_args!("{}", self.rx_tdm_chan_bits().bits()),
-            )
-            .field(
-                "rx_msb_shift",
-                &format_args!("{}", self.rx_msb_shift().bit()),
-            )
+            .field("rx_tdm_ws_width", &self.rx_tdm_ws_width())
+            .field("rx_bck_div_num", &self.rx_bck_div_num())
+            .field("rx_bits_mod", &self.rx_bits_mod())
+            .field("rx_half_sample_bits", &self.rx_half_sample_bits())
+            .field("rx_tdm_chan_bits", &self.rx_tdm_chan_bits())
+            .field("rx_msb_shift", &self.rx_msb_shift())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/rx_mem_conf.rs b/esp32p4/src/lp_i2s0/rx_mem_conf.rs
index 1ad866dcb7..8f866b8018 100644
--- a/esp32p4/src/lp_i2s0/rx_mem_conf.rs
+++ b/esp32p4/src/lp_i2s0/rx_mem_conf.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_MEM_CONF")
-            .field(
-                "rx_mem_fifo_cnt",
-                &format_args!("{}", self.rx_mem_fifo_cnt().bits()),
-            )
-            .field(
-                "rx_mem_threshold",
-                &format_args!("{}", self.rx_mem_threshold().bits()),
-            )
+            .field("rx_mem_fifo_cnt", &self.rx_mem_fifo_cnt())
+            .field("rx_mem_threshold", &self.rx_mem_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 9:16 - I2S rx mem will trigger an interrupt when the data in the mem is over(not including equal) reg_rx_mem_threshold"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/rx_pdm_conf.rs b/esp32p4/src/lp_i2s0/rx_pdm_conf.rs
index bd4369bc6b..f328d19c85 100644
--- a/esp32p4/src/lp_i2s0/rx_pdm_conf.rs
+++ b/esp32p4/src/lp_i2s0/rx_pdm_conf.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_PDM_CONF")
-            .field(
-                "rx_pdm2pcm_en",
-                &format_args!("{}", self.rx_pdm2pcm_en().bit()),
-            )
-            .field(
-                "rx_pdm_sinc_dsr_16_en",
-                &format_args!("{}", self.rx_pdm_sinc_dsr_16_en().bit()),
-            )
-            .field(
-                "rx_pdm2pcm_amplify_num",
-                &format_args!("{}", self.rx_pdm2pcm_amplify_num().bits()),
-            )
-            .field(
-                "rx_pdm_hp_bypass",
-                &format_args!("{}", self.rx_pdm_hp_bypass().bit()),
-            )
-            .field(
-                "rx_iir_hp_mult12_5",
-                &format_args!("{}", self.rx_iir_hp_mult12_5().bits()),
-            )
-            .field(
-                "rx_iir_hp_mult12_0",
-                &format_args!("{}", self.rx_iir_hp_mult12_0().bits()),
-            )
+            .field("rx_pdm2pcm_en", &self.rx_pdm2pcm_en())
+            .field("rx_pdm_sinc_dsr_16_en", &self.rx_pdm_sinc_dsr_16_en())
+            .field("rx_pdm2pcm_amplify_num", &self.rx_pdm2pcm_amplify_num())
+            .field("rx_pdm_hp_bypass", &self.rx_pdm_hp_bypass())
+            .field("rx_iir_hp_mult12_5", &self.rx_iir_hp_mult12_5())
+            .field("rx_iir_hp_mult12_0", &self.rx_iir_hp_mult12_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_PDM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 19 - 1: Enable PDM2PCM RX mode. 0: DIsable."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/rx_tdm_ctrl.rs b/esp32p4/src/lp_i2s0/rx_tdm_ctrl.rs
index 515fd096fe..9e83cd474a 100644
--- a/esp32p4/src/lp_i2s0/rx_tdm_ctrl.rs
+++ b/esp32p4/src/lp_i2s0/rx_tdm_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_TDM_CTRL")
-            .field(
-                "rx_tdm_pdm_chan0_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan0_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan1_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan1_en().bit()),
-            )
-            .field(
-                "rx_tdm_tot_chan_num",
-                &format_args!("{}", self.rx_tdm_tot_chan_num().bits()),
-            )
+            .field("rx_tdm_pdm_chan0_en", &self.rx_tdm_pdm_chan0_en())
+            .field("rx_tdm_pdm_chan1_en", &self.rx_tdm_pdm_chan1_en())
+            .field("rx_tdm_tot_chan_num", &self.rx_tdm_tot_chan_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_TDM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/rx_timing.rs b/esp32p4/src/lp_i2s0/rx_timing.rs
index 66daf81e08..fe227b5840 100644
--- a/esp32p4/src/lp_i2s0/rx_timing.rs
+++ b/esp32p4/src/lp_i2s0/rx_timing.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_TIMING")
-            .field(
-                "rx_sd_in_dm",
-                &format_args!("{}", self.rx_sd_in_dm().bits()),
-            )
-            .field(
-                "rx_ws_out_dm",
-                &format_args!("{}", self.rx_ws_out_dm().bits()),
-            )
-            .field(
-                "rx_bck_out_dm",
-                &format_args!("{}", self.rx_bck_out_dm().bits()),
-            )
-            .field(
-                "rx_ws_in_dm",
-                &format_args!("{}", self.rx_ws_in_dm().bits()),
-            )
-            .field(
-                "rx_bck_in_dm",
-                &format_args!("{}", self.rx_bck_in_dm().bits()),
-            )
+            .field("rx_sd_in_dm", &self.rx_sd_in_dm())
+            .field("rx_ws_out_dm", &self.rx_ws_out_dm())
+            .field("rx_bck_out_dm", &self.rx_bck_out_dm())
+            .field("rx_ws_in_dm", &self.rx_ws_in_dm())
+            .field("rx_bck_in_dm", &self.rx_bck_in_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/rxeof_num.rs b/esp32p4/src/lp_i2s0/rxeof_num.rs
index 06f6d22ff0..b9674d5891 100644
--- a/esp32p4/src/lp_i2s0/rxeof_num.rs
+++ b/esp32p4/src/lp_i2s0/rxeof_num.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXEOF_NUM")
-            .field("rx_eof_num", &format_args!("{}", self.rx_eof_num().bits()))
+            .field("rx_eof_num", &self.rx_eof_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXEOF_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/vad_conf.rs b/esp32p4/src/lp_i2s0/vad_conf.rs
index 5b8c931303..27e4650cbf 100644
--- a/esp32p4/src/lp_i2s0/vad_conf.rs
+++ b/esp32p4/src/lp_i2s0/vad_conf.rs
@@ -21,16 +21,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_CONF")
-            .field("vad_en", &format_args!("{}", self.vad_en().bit()))
+            .field("vad_en", &self.vad_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - VAD enable register"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/vad_ob0.rs b/esp32p4/src/lp_i2s0/vad_ob0.rs
index 238d3307e5..4482b70435 100644
--- a/esp32p4/src/lp_i2s0/vad_ob0.rs
+++ b/esp32p4/src/lp_i2s0/vad_ob0.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_OB0")
-            .field(
-                "speech_count_ob",
-                &format_args!("{}", self.speech_count_ob().bits()),
-            )
-            .field(
-                "silent_count_ob",
-                &format_args!("{}", self.silent_count_ob().bits()),
-            )
-            .field(
-                "max_signal0_ob",
-                &format_args!("{}", self.max_signal0_ob().bits()),
-            )
+            .field("speech_count_ob", &self.speech_count_ob())
+            .field("silent_count_ob", &self.silent_count_ob())
+            .field("max_signal0_ob", &self.max_signal0_ob())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_OB0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VAD_OB0_SPEC;
 impl crate::RegisterSpec for VAD_OB0_SPEC {
diff --git a/esp32p4/src/lp_i2s0/vad_ob1.rs b/esp32p4/src/lp_i2s0/vad_ob1.rs
index a12179cfaf..b8ff79ba3e 100644
--- a/esp32p4/src/lp_i2s0/vad_ob1.rs
+++ b/esp32p4/src/lp_i2s0/vad_ob1.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_OB1")
-            .field(
-                "max_signal1_ob",
-                &format_args!("{}", self.max_signal1_ob().bits()),
-            )
-            .field(
-                "max_signal2_ob",
-                &format_args!("{}", self.max_signal2_ob().bits()),
-            )
+            .field("max_signal1_ob", &self.max_signal1_ob())
+            .field("max_signal2_ob", &self.max_signal2_ob())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_OB1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VAD_OB1_SPEC;
 impl crate::RegisterSpec for VAD_OB1_SPEC {
diff --git a/esp32p4/src/lp_i2s0/vad_ob2.rs b/esp32p4/src/lp_i2s0/vad_ob2.rs
index 6af8788521..c309dc3ac0 100644
--- a/esp32p4/src/lp_i2s0/vad_ob2.rs
+++ b/esp32p4/src/lp_i2s0/vad_ob2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_OB2")
-            .field(
-                "noise_amp_ob",
-                &format_args!("{}", self.noise_amp_ob().bits()),
-            )
+            .field("noise_amp_ob", &self.noise_amp_ob())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_OB2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VAD_OB2_SPEC;
 impl crate::RegisterSpec for VAD_OB2_SPEC {
diff --git a/esp32p4/src/lp_i2s0/vad_ob3.rs b/esp32p4/src/lp_i2s0/vad_ob3.rs
index 2011acae67..85ccfac8ab 100644
--- a/esp32p4/src/lp_i2s0/vad_ob3.rs
+++ b/esp32p4/src/lp_i2s0/vad_ob3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_OB3")
-            .field(
-                "noise_mean_ob",
-                &format_args!("{}", self.noise_mean_ob().bits()),
-            )
+            .field("noise_mean_ob", &self.noise_mean_ob())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_OB3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VAD_OB3_SPEC;
 impl crate::RegisterSpec for VAD_OB3_SPEC {
diff --git a/esp32p4/src/lp_i2s0/vad_ob4.rs b/esp32p4/src/lp_i2s0/vad_ob4.rs
index 77d274eb10..231d4d9478 100644
--- a/esp32p4/src/lp_i2s0/vad_ob4.rs
+++ b/esp32p4/src/lp_i2s0/vad_ob4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_OB4")
-            .field(
-                "noise_std_ob",
-                &format_args!("{}", self.noise_std_ob().bits()),
-            )
+            .field("noise_std_ob", &self.noise_std_ob())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_OB4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VAD_OB4_SPEC;
 impl crate::RegisterSpec for VAD_OB4_SPEC {
diff --git a/esp32p4/src/lp_i2s0/vad_ob5.rs b/esp32p4/src/lp_i2s0/vad_ob5.rs
index d218dd532f..3136994ab2 100644
--- a/esp32p4/src/lp_i2s0/vad_ob5.rs
+++ b/esp32p4/src/lp_i2s0/vad_ob5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_OB5")
-            .field("offset_ob", &format_args!("{}", self.offset_ob().bits()))
+            .field("offset_ob", &self.offset_ob())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_OB5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VAD_OB5_SPEC;
 impl crate::RegisterSpec for VAD_OB5_SPEC {
diff --git a/esp32p4/src/lp_i2s0/vad_ob6.rs b/esp32p4/src/lp_i2s0/vad_ob6.rs
index 4950eab9fa..f99e6834c2 100644
--- a/esp32p4/src/lp_i2s0/vad_ob6.rs
+++ b/esp32p4/src/lp_i2s0/vad_ob6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_OB6")
-            .field(
-                "threshold_ob",
-                &format_args!("{}", self.threshold_ob().bits()),
-            )
+            .field("threshold_ob", &self.threshold_ob())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_OB6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VAD_OB6_SPEC;
 impl crate::RegisterSpec for VAD_OB6_SPEC {
diff --git a/esp32p4/src/lp_i2s0/vad_ob7.rs b/esp32p4/src/lp_i2s0/vad_ob7.rs
index 5faecaee0e..c841aa9307 100644
--- a/esp32p4/src/lp_i2s0/vad_ob7.rs
+++ b/esp32p4/src/lp_i2s0/vad_ob7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_OB7")
-            .field(
-                "energy_low_ob",
-                &format_args!("{}", self.energy_low_ob().bits()),
-            )
+            .field("energy_low_ob", &self.energy_low_ob())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_OB7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VAD_OB7_SPEC;
 impl crate::RegisterSpec for VAD_OB7_SPEC {
diff --git a/esp32p4/src/lp_i2s0/vad_ob8.rs b/esp32p4/src/lp_i2s0/vad_ob8.rs
index 6fe8e9fef7..e20049d3d6 100644
--- a/esp32p4/src/lp_i2s0/vad_ob8.rs
+++ b/esp32p4/src/lp_i2s0/vad_ob8.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_OB8")
-            .field(
-                "energy_high_ob",
-                &format_args!("{}", self.energy_high_ob().bits()),
-            )
+            .field("energy_high_ob", &self.energy_high_ob())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_OB8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S VAD Observe register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_ob8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VAD_OB8_SPEC;
 impl crate::RegisterSpec for VAD_OB8_SPEC {
diff --git a/esp32p4/src/lp_i2s0/vad_param0.rs b/esp32p4/src/lp_i2s0/vad_param0.rs
index 3a79b52ac9..0d2af37053 100644
--- a/esp32p4/src/lp_i2s0/vad_param0.rs
+++ b/esp32p4/src/lp_i2s0/vad_param0.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_PARAM0")
-            .field(
-                "param_min_energy",
-                &format_args!("{}", self.param_min_energy().bits()),
-            )
-            .field(
-                "param_init_frame_num",
-                &format_args!("{}", self.param_init_frame_num().bits()),
-            )
+            .field("param_min_energy", &self.param_min_energy())
+            .field("param_init_frame_num", &self.param_init_frame_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_PARAM0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - VAD parameter"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/vad_param1.rs b/esp32p4/src/lp_i2s0/vad_param1.rs
index 91c204c12e..ade5f688ec 100644
--- a/esp32p4/src/lp_i2s0/vad_param1.rs
+++ b/esp32p4/src/lp_i2s0/vad_param1.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_PARAM1")
-            .field(
-                "param_min_speech_count",
-                &format_args!("{}", self.param_min_speech_count().bits()),
-            )
-            .field(
-                "param_max_speech_count",
-                &format_args!("{}", self.param_max_speech_count().bits()),
-            )
-            .field(
-                "param_hangover_speech",
-                &format_args!("{}", self.param_hangover_speech().bits()),
-            )
-            .field(
-                "param_hangover_silent",
-                &format_args!("{}", self.param_hangover_silent().bits()),
-            )
-            .field(
-                "param_max_offset",
-                &format_args!("{}", self.param_max_offset().bits()),
-            )
-            .field(
-                "param_skip_band_energy",
-                &format_args!("{}", self.param_skip_band_energy().bit()),
-            )
+            .field("param_min_speech_count", &self.param_min_speech_count())
+            .field("param_max_speech_count", &self.param_max_speech_count())
+            .field("param_hangover_speech", &self.param_hangover_speech())
+            .field("param_hangover_silent", &self.param_hangover_silent())
+            .field("param_max_offset", &self.param_max_offset())
+            .field("param_skip_band_energy", &self.param_skip_band_energy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_PARAM1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - VAD parameter"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/vad_param2.rs b/esp32p4/src/lp_i2s0/vad_param2.rs
index 148fd54d04..8cbaabcf68 100644
--- a/esp32p4/src/lp_i2s0/vad_param2.rs
+++ b/esp32p4/src/lp_i2s0/vad_param2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_PARAM2")
-            .field(
-                "param_noise_amp_down",
-                &format_args!("{}", self.param_noise_amp_down().bits()),
-            )
-            .field(
-                "param_noise_amp_up",
-                &format_args!("{}", self.param_noise_amp_up().bits()),
-            )
+            .field("param_noise_amp_down", &self.param_noise_amp_down())
+            .field("param_noise_amp_up", &self.param_noise_amp_up())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_PARAM2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - VAD parameter"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/vad_param3.rs b/esp32p4/src/lp_i2s0/vad_param3.rs
index 80c048571c..c77f685fc2 100644
--- a/esp32p4/src/lp_i2s0/vad_param3.rs
+++ b/esp32p4/src/lp_i2s0/vad_param3.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_PARAM3")
-            .field(
-                "param_noise_spe_up0",
-                &format_args!("{}", self.param_noise_spe_up0().bits()),
-            )
-            .field(
-                "param_noise_spe_up1",
-                &format_args!("{}", self.param_noise_spe_up1().bits()),
-            )
+            .field("param_noise_spe_up0", &self.param_noise_spe_up0())
+            .field("param_noise_spe_up1", &self.param_noise_spe_up1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_PARAM3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - VAD parameter"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/vad_param4.rs b/esp32p4/src/lp_i2s0/vad_param4.rs
index 3c0bfc5b28..3c759a73d9 100644
--- a/esp32p4/src/lp_i2s0/vad_param4.rs
+++ b/esp32p4/src/lp_i2s0/vad_param4.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_PARAM4")
-            .field(
-                "param_noise_spe_down",
-                &format_args!("{}", self.param_noise_spe_down().bits()),
-            )
-            .field(
-                "param_noise_mean_down",
-                &format_args!("{}", self.param_noise_mean_down().bits()),
-            )
+            .field("param_noise_spe_down", &self.param_noise_spe_down())
+            .field("param_noise_mean_down", &self.param_noise_mean_down())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_PARAM4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - VAD parameter"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/vad_param5.rs b/esp32p4/src/lp_i2s0/vad_param5.rs
index 97471a61ef..46794345be 100644
--- a/esp32p4/src/lp_i2s0/vad_param5.rs
+++ b/esp32p4/src/lp_i2s0/vad_param5.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_PARAM5")
-            .field(
-                "param_noise_mean_up0",
-                &format_args!("{}", self.param_noise_mean_up0().bits()),
-            )
-            .field(
-                "param_noise_mean_up1",
-                &format_args!("{}", self.param_noise_mean_up1().bits()),
-            )
+            .field("param_noise_mean_up0", &self.param_noise_mean_up0())
+            .field("param_noise_mean_up1", &self.param_noise_mean_up1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_PARAM5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - VAD parameter"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/vad_param6.rs b/esp32p4/src/lp_i2s0/vad_param6.rs
index 8c81dd6527..fe24e8b6ac 100644
--- a/esp32p4/src/lp_i2s0/vad_param6.rs
+++ b/esp32p4/src/lp_i2s0/vad_param6.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_PARAM6")
-            .field(
-                "param_noise_std_fs_thsl",
-                &format_args!("{}", self.param_noise_std_fs_thsl().bits()),
-            )
-            .field(
-                "param_noise_std_fs_thsh",
-                &format_args!("{}", self.param_noise_std_fs_thsh().bits()),
-            )
+            .field("param_noise_std_fs_thsl", &self.param_noise_std_fs_thsl())
+            .field("param_noise_std_fs_thsh", &self.param_noise_std_fs_thsh())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_PARAM6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to ((noise_std_max)>>11)^2*5"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/vad_param7.rs b/esp32p4/src/lp_i2s0/vad_param7.rs
index 72372fa849..cd9d42388a 100644
--- a/esp32p4/src/lp_i2s0/vad_param7.rs
+++ b/esp32p4/src/lp_i2s0/vad_param7.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_PARAM7")
-            .field(
-                "param_thres_upd_base",
-                &format_args!("{}", self.param_thres_upd_base().bits()),
-            )
-            .field(
-                "param_thres_upd_vary",
-                &format_args!("{}", self.param_thres_upd_vary().bits()),
-            )
+            .field("param_thres_upd_base", &self.param_thres_upd_base())
+            .field("param_thres_upd_vary", &self.param_thres_upd_vary())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_PARAM7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - VAD parameter"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/vad_param8.rs b/esp32p4/src/lp_i2s0/vad_param8.rs
index 5e4349301c..8c14daa742 100644
--- a/esp32p4/src/lp_i2s0/vad_param8.rs
+++ b/esp32p4/src/lp_i2s0/vad_param8.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_PARAM8")
-            .field(
-                "param_thres_upd_bdl",
-                &format_args!("{}", self.param_thres_upd_bdl().bits()),
-            )
-            .field(
-                "param_thres_upd_bdh",
-                &format_args!("{}", self.param_thres_upd_bdh().bits()),
-            )
-            .field(
-                "param_feature_burst",
-                &format_args!("{}", self.param_feature_burst().bits()),
-            )
+            .field("param_thres_upd_bdl", &self.param_thres_upd_bdl())
+            .field("param_thres_upd_bdh", &self.param_thres_upd_bdh())
+            .field("param_feature_burst", &self.param_feature_burst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_PARAM8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Noise_std boundary low when updating threshold."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_i2s0/vad_result.rs b/esp32p4/src/lp_i2s0/vad_result.rs
index 8a137cb110..19b83d6874 100644
--- a/esp32p4/src/lp_i2s0/vad_result.rs
+++ b/esp32p4/src/lp_i2s0/vad_result.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VAD_RESULT")
-            .field("vad_flag", &format_args!("{}", self.vad_flag().bit()))
-            .field(
-                "energy_enough",
-                &format_args!("{}", self.energy_enough().bit()),
-            )
+            .field("vad_flag", &self.vad_flag())
+            .field("energy_enough", &self.energy_enough())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VAD_RESULT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S VAD Result register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vad_result::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VAD_RESULT_SPEC;
 impl crate::RegisterSpec for VAD_RESULT_SPEC {
diff --git a/esp32p4/src/lp_intr/date.rs b/esp32p4/src/lp_intr/date.rs
index 1988aab0c4..dd9a8122d3 100644
--- a/esp32p4/src/lp_intr/date.rs
+++ b/esp32p4/src/lp_intr/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_intr/status.rs b/esp32p4/src/lp_intr/status.rs
index a997160ede..4e45ce25fa 100644
--- a/esp32p4/src/lp_intr/status.rs
+++ b/esp32p4/src/lp_intr/status.rs
@@ -160,100 +160,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field(
-                "lp_huk_intr_st",
-                &format_args!("{}", self.lp_huk_intr_st().bit()),
-            )
-            .field(
-                "sysreg_intr_st",
-                &format_args!("{}", self.sysreg_intr_st().bit()),
-            )
-            .field(
-                "lp_sw_intr_st",
-                &format_args!("{}", self.lp_sw_intr_st().bit()),
-            )
-            .field(
-                "lp_efuse_intr_st",
-                &format_args!("{}", self.lp_efuse_intr_st().bit()),
-            )
-            .field(
-                "lp_uart_intr_st",
-                &format_args!("{}", self.lp_uart_intr_st().bit()),
-            )
-            .field(
-                "lp_tsens_intr_st",
-                &format_args!("{}", self.lp_tsens_intr_st().bit()),
-            )
-            .field(
-                "lp_touch_intr_st",
-                &format_args!("{}", self.lp_touch_intr_st().bit()),
-            )
-            .field(
-                "lp_spi_intr_st",
-                &format_args!("{}", self.lp_spi_intr_st().bit()),
-            )
-            .field(
-                "lp_i2s_intr_st",
-                &format_args!("{}", self.lp_i2s_intr_st().bit()),
-            )
-            .field(
-                "lp_i2c_intr_st",
-                &format_args!("{}", self.lp_i2c_intr_st().bit()),
-            )
-            .field(
-                "lp_gpio_intr_st",
-                &format_args!("{}", self.lp_gpio_intr_st().bit()),
-            )
-            .field(
-                "lp_adc_intr_st",
-                &format_args!("{}", self.lp_adc_intr_st().bit()),
-            )
-            .field(
-                "anaperi_intr_st",
-                &format_args!("{}", self.anaperi_intr_st().bit()),
-            )
-            .field(
-                "pmu_reg_1_intr_st",
-                &format_args!("{}", self.pmu_reg_1_intr_st().bit()),
-            )
-            .field(
-                "pmu_reg_0_intr_st",
-                &format_args!("{}", self.pmu_reg_0_intr_st().bit()),
-            )
-            .field(
-                "mb_lp_intr_st",
-                &format_args!("{}", self.mb_lp_intr_st().bit()),
-            )
-            .field(
-                "mb_hp_intr_st",
-                &format_args!("{}", self.mb_hp_intr_st().bit()),
-            )
-            .field(
-                "lp_timer_reg_1_intr_st",
-                &format_args!("{}", self.lp_timer_reg_1_intr_st().bit()),
-            )
-            .field(
-                "lp_timer_reg_0_intr_st",
-                &format_args!("{}", self.lp_timer_reg_0_intr_st().bit()),
-            )
-            .field(
-                "lp_wdt_intr_st",
-                &format_args!("{}", self.lp_wdt_intr_st().bit()),
-            )
-            .field(
-                "lp_rtc_intr_st",
-                &format_args!("{}", self.lp_rtc_intr_st().bit()),
-            )
-            .field("hp_intr_st", &format_args!("{}", self.hp_intr_st().bit()))
+            .field("lp_huk_intr_st", &self.lp_huk_intr_st())
+            .field("sysreg_intr_st", &self.sysreg_intr_st())
+            .field("lp_sw_intr_st", &self.lp_sw_intr_st())
+            .field("lp_efuse_intr_st", &self.lp_efuse_intr_st())
+            .field("lp_uart_intr_st", &self.lp_uart_intr_st())
+            .field("lp_tsens_intr_st", &self.lp_tsens_intr_st())
+            .field("lp_touch_intr_st", &self.lp_touch_intr_st())
+            .field("lp_spi_intr_st", &self.lp_spi_intr_st())
+            .field("lp_i2s_intr_st", &self.lp_i2s_intr_st())
+            .field("lp_i2c_intr_st", &self.lp_i2c_intr_st())
+            .field("lp_gpio_intr_st", &self.lp_gpio_intr_st())
+            .field("lp_adc_intr_st", &self.lp_adc_intr_st())
+            .field("anaperi_intr_st", &self.anaperi_intr_st())
+            .field("pmu_reg_1_intr_st", &self.pmu_reg_1_intr_st())
+            .field("pmu_reg_0_intr_st", &self.pmu_reg_0_intr_st())
+            .field("mb_lp_intr_st", &self.mb_lp_intr_st())
+            .field("mb_hp_intr_st", &self.mb_hp_intr_st())
+            .field("lp_timer_reg_1_intr_st", &self.lp_timer_reg_1_intr_st())
+            .field("lp_timer_reg_0_intr_st", &self.lp_timer_reg_0_intr_st())
+            .field("lp_wdt_intr_st", &self.lp_wdt_intr_st())
+            .field("lp_rtc_intr_st", &self.lp_rtc_intr_st())
+            .field("hp_intr_st", &self.hp_intr_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32p4/src/lp_intr/sw_int_ena.rs b/esp32p4/src/lp_intr/sw_int_ena.rs
index d5bd84a41c..17e3943b8e 100644
--- a/esp32p4/src/lp_intr/sw_int_ena.rs
+++ b/esp32p4/src/lp_intr/sw_int_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SW_INT_ENA")
-            .field(
-                "lp_sw_int_ena",
-                &format_args!("{}", self.lp_sw_int_ena().bit()),
-            )
+            .field("lp_sw_int_ena", &self.lp_sw_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SW_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_intr/sw_int_raw.rs b/esp32p4/src/lp_intr/sw_int_raw.rs
index d15d2c60ad..914d3fcf5f 100644
--- a/esp32p4/src/lp_intr/sw_int_raw.rs
+++ b/esp32p4/src/lp_intr/sw_int_raw.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SW_INT_RAW")
-            .field(
-                "lp_sw_int_raw",
-                &format_args!("{}", self.lp_sw_int_raw().bit()),
-            )
+            .field("lp_sw_int_raw", &self.lp_sw_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SW_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_intr/sw_int_st.rs b/esp32p4/src/lp_intr/sw_int_st.rs
index 53e2d814b7..0c1616486c 100644
--- a/esp32p4/src/lp_intr/sw_int_st.rs
+++ b/esp32p4/src/lp_intr/sw_int_st.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SW_INT_ST")
-            .field(
-                "lp_sw_int_st",
-                &format_args!("{}", self.lp_sw_int_st().bit()),
-            )
+            .field("lp_sw_int_st", &self.lp_sw_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SW_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SW_INT_ST_SPEC;
 impl crate::RegisterSpec for SW_INT_ST_SPEC {
diff --git a/esp32p4/src/lp_io_mux/clk_en.rs b/esp32p4/src/lp_io_mux/clk_en.rs
index 2c28fcfb34..fd0eedde58 100644
--- a/esp32p4/src/lp_io_mux/clk_en.rs
+++ b/esp32p4/src/lp_io_mux/clk_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EN")
-            .field("reg_clk_en", &format_args!("{}", self.reg_clk_en().bit()))
+            .field("reg_clk_en", &self.reg_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/ext_wakeup0_sel.rs b/esp32p4/src/lp_io_mux/ext_wakeup0_sel.rs
index 207657c1cb..541262a811 100644
--- a/esp32p4/src/lp_io_mux/ext_wakeup0_sel.rs
+++ b/esp32p4/src/lp_io_mux/ext_wakeup0_sel.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP0_SEL")
-            .field(
-                "reg_xtl_ext_ctr_sel",
-                &format_args!("{}", self.reg_xtl_ext_ctr_sel().bits()),
-            )
-            .field(
-                "reg_ext_wakeup0_sel",
-                &format_args!("{}", self.reg_ext_wakeup0_sel().bits()),
-            )
+            .field("reg_xtl_ext_ctr_sel", &self.reg_xtl_ext_ctr_sel())
+            .field("reg_ext_wakeup0_sel", &self.reg_ext_wakeup0_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP0_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - select LP GPIO 0 ~ 15 to control XTAL"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/lp_pad_hold.rs b/esp32p4/src/lp_io_mux/lp_pad_hold.rs
index fc0d30bd65..84ab498a59 100644
--- a/esp32p4/src/lp_io_mux/lp_pad_hold.rs
+++ b/esp32p4/src/lp_io_mux/lp_pad_hold.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_PAD_HOLD")
-            .field(
-                "reg_lp_gpio_hold",
-                &format_args!("{}", self.reg_lp_gpio_hold().bits()),
-            )
+            .field("reg_lp_gpio_hold", &self.reg_lp_gpio_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_PAD_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/lp_pad_hys.rs b/esp32p4/src/lp_io_mux/lp_pad_hys.rs
index e4a2423718..848eded5af 100644
--- a/esp32p4/src/lp_io_mux/lp_pad_hys.rs
+++ b/esp32p4/src/lp_io_mux/lp_pad_hys.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_PAD_HYS")
-            .field(
-                "reg_lp_gpio_hys",
-                &format_args!("{}", self.reg_lp_gpio_hys().bits()),
-            )
+            .field("reg_lp_gpio_hys", &self.reg_lp_gpio_hys())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_PAD_HYS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad0.rs b/esp32p4/src/lp_io_mux/pad0.rs
index 08b5d91f06..b391f1f287 100644
--- a/esp32p4/src/lp_io_mux/pad0.rs
+++ b/esp32p4/src/lp_io_mux/pad0.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD0")
-            .field(
-                "reg_pad0_drv",
-                &format_args!("{}", self.reg_pad0_drv().bits()),
-            )
-            .field(
-                "reg_pad0_rde",
-                &format_args!("{}", self.reg_pad0_rde().bit()),
-            )
-            .field(
-                "reg_pad0_rue",
-                &format_args!("{}", self.reg_pad0_rue().bit()),
-            )
-            .field(
-                "reg_pad0_mux_sel",
-                &format_args!("{}", self.reg_pad0_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad0_fun_sel",
-                &format_args!("{}", self.reg_pad0_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad0_slp_sel",
-                &format_args!("{}", self.reg_pad0_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad0_slp_ie",
-                &format_args!("{}", self.reg_pad0_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad0_slp_oe",
-                &format_args!("{}", self.reg_pad0_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad0_fun_ie",
-                &format_args!("{}", self.reg_pad0_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad0_filter_en",
-                &format_args!("{}", self.reg_pad0_filter_en().bit()),
-            )
+            .field("reg_pad0_drv", &self.reg_pad0_drv())
+            .field("reg_pad0_rde", &self.reg_pad0_rde())
+            .field("reg_pad0_rue", &self.reg_pad0_rue())
+            .field("reg_pad0_mux_sel", &self.reg_pad0_mux_sel())
+            .field("reg_pad0_fun_sel", &self.reg_pad0_fun_sel())
+            .field("reg_pad0_slp_sel", &self.reg_pad0_slp_sel())
+            .field("reg_pad0_slp_ie", &self.reg_pad0_slp_ie())
+            .field("reg_pad0_slp_oe", &self.reg_pad0_slp_oe())
+            .field("reg_pad0_fun_ie", &self.reg_pad0_fun_ie())
+            .field("reg_pad0_filter_en", &self.reg_pad0_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad1.rs b/esp32p4/src/lp_io_mux/pad1.rs
index 172d8e43bb..b3da7ac807 100644
--- a/esp32p4/src/lp_io_mux/pad1.rs
+++ b/esp32p4/src/lp_io_mux/pad1.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD1")
-            .field(
-                "reg_pad1_drv",
-                &format_args!("{}", self.reg_pad1_drv().bits()),
-            )
-            .field(
-                "reg_pad1_rde",
-                &format_args!("{}", self.reg_pad1_rde().bit()),
-            )
-            .field(
-                "reg_pad1_rue",
-                &format_args!("{}", self.reg_pad1_rue().bit()),
-            )
-            .field(
-                "reg_pad1_mux_sel",
-                &format_args!("{}", self.reg_pad1_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad1_fun_sel",
-                &format_args!("{}", self.reg_pad1_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad1_slp_sel",
-                &format_args!("{}", self.reg_pad1_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad1_slp_ie",
-                &format_args!("{}", self.reg_pad1_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad1_slp_oe",
-                &format_args!("{}", self.reg_pad1_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad1_fun_ie",
-                &format_args!("{}", self.reg_pad1_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad1_filter_en",
-                &format_args!("{}", self.reg_pad1_filter_en().bit()),
-            )
+            .field("reg_pad1_drv", &self.reg_pad1_drv())
+            .field("reg_pad1_rde", &self.reg_pad1_rde())
+            .field("reg_pad1_rue", &self.reg_pad1_rue())
+            .field("reg_pad1_mux_sel", &self.reg_pad1_mux_sel())
+            .field("reg_pad1_fun_sel", &self.reg_pad1_fun_sel())
+            .field("reg_pad1_slp_sel", &self.reg_pad1_slp_sel())
+            .field("reg_pad1_slp_ie", &self.reg_pad1_slp_ie())
+            .field("reg_pad1_slp_oe", &self.reg_pad1_slp_oe())
+            .field("reg_pad1_fun_ie", &self.reg_pad1_fun_ie())
+            .field("reg_pad1_filter_en", &self.reg_pad1_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad10.rs b/esp32p4/src/lp_io_mux/pad10.rs
index b23e895de0..232a893f7a 100644
--- a/esp32p4/src/lp_io_mux/pad10.rs
+++ b/esp32p4/src/lp_io_mux/pad10.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD10")
-            .field(
-                "reg_pad10_drv",
-                &format_args!("{}", self.reg_pad10_drv().bits()),
-            )
-            .field(
-                "reg_pad10_rde",
-                &format_args!("{}", self.reg_pad10_rde().bit()),
-            )
-            .field(
-                "reg_pad10_rue",
-                &format_args!("{}", self.reg_pad10_rue().bit()),
-            )
-            .field(
-                "reg_pad10_mux_sel",
-                &format_args!("{}", self.reg_pad10_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad10_fun_sel",
-                &format_args!("{}", self.reg_pad10_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad10_slp_sel",
-                &format_args!("{}", self.reg_pad10_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad10_slp_ie",
-                &format_args!("{}", self.reg_pad10_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad10_slp_oe",
-                &format_args!("{}", self.reg_pad10_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad10_fun_ie",
-                &format_args!("{}", self.reg_pad10_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad10_filter_en",
-                &format_args!("{}", self.reg_pad10_filter_en().bit()),
-            )
+            .field("reg_pad10_drv", &self.reg_pad10_drv())
+            .field("reg_pad10_rde", &self.reg_pad10_rde())
+            .field("reg_pad10_rue", &self.reg_pad10_rue())
+            .field("reg_pad10_mux_sel", &self.reg_pad10_mux_sel())
+            .field("reg_pad10_fun_sel", &self.reg_pad10_fun_sel())
+            .field("reg_pad10_slp_sel", &self.reg_pad10_slp_sel())
+            .field("reg_pad10_slp_ie", &self.reg_pad10_slp_ie())
+            .field("reg_pad10_slp_oe", &self.reg_pad10_slp_oe())
+            .field("reg_pad10_fun_ie", &self.reg_pad10_fun_ie())
+            .field("reg_pad10_filter_en", &self.reg_pad10_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad11.rs b/esp32p4/src/lp_io_mux/pad11.rs
index c8450a2704..a39ed6d4e8 100644
--- a/esp32p4/src/lp_io_mux/pad11.rs
+++ b/esp32p4/src/lp_io_mux/pad11.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD11")
-            .field(
-                "reg_pad11_drv",
-                &format_args!("{}", self.reg_pad11_drv().bits()),
-            )
-            .field(
-                "reg_pad11_rde",
-                &format_args!("{}", self.reg_pad11_rde().bit()),
-            )
-            .field(
-                "reg_pad11_rue",
-                &format_args!("{}", self.reg_pad11_rue().bit()),
-            )
-            .field(
-                "reg_pad11_mux_sel",
-                &format_args!("{}", self.reg_pad11_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad11_fun_sel",
-                &format_args!("{}", self.reg_pad11_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad11_slp_sel",
-                &format_args!("{}", self.reg_pad11_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad11_slp_ie",
-                &format_args!("{}", self.reg_pad11_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad11_slp_oe",
-                &format_args!("{}", self.reg_pad11_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad11_fun_ie",
-                &format_args!("{}", self.reg_pad11_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad11_filter_en",
-                &format_args!("{}", self.reg_pad11_filter_en().bit()),
-            )
+            .field("reg_pad11_drv", &self.reg_pad11_drv())
+            .field("reg_pad11_rde", &self.reg_pad11_rde())
+            .field("reg_pad11_rue", &self.reg_pad11_rue())
+            .field("reg_pad11_mux_sel", &self.reg_pad11_mux_sel())
+            .field("reg_pad11_fun_sel", &self.reg_pad11_fun_sel())
+            .field("reg_pad11_slp_sel", &self.reg_pad11_slp_sel())
+            .field("reg_pad11_slp_ie", &self.reg_pad11_slp_ie())
+            .field("reg_pad11_slp_oe", &self.reg_pad11_slp_oe())
+            .field("reg_pad11_fun_ie", &self.reg_pad11_fun_ie())
+            .field("reg_pad11_filter_en", &self.reg_pad11_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad120.rs b/esp32p4/src/lp_io_mux/pad120.rs
index ff284a2839..970c79546f 100644
--- a/esp32p4/src/lp_io_mux/pad120.rs
+++ b/esp32p4/src/lp_io_mux/pad120.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD120")
-            .field(
-                "reg_pad12_drv",
-                &format_args!("{}", self.reg_pad12_drv().bits()),
-            )
-            .field(
-                "reg_pad12_rde",
-                &format_args!("{}", self.reg_pad12_rde().bit()),
-            )
-            .field(
-                "reg_pad12_rue",
-                &format_args!("{}", self.reg_pad12_rue().bit()),
-            )
-            .field(
-                "reg_pad12_mux_sel",
-                &format_args!("{}", self.reg_pad12_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad12_fun_sel",
-                &format_args!("{}", self.reg_pad12_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad12_slp_sel",
-                &format_args!("{}", self.reg_pad12_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad12_slp_ie",
-                &format_args!("{}", self.reg_pad12_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad12_slp_oe",
-                &format_args!("{}", self.reg_pad12_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad12_fun_ie",
-                &format_args!("{}", self.reg_pad12_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad12_filter_en",
-                &format_args!("{}", self.reg_pad12_filter_en().bit()),
-            )
+            .field("reg_pad12_drv", &self.reg_pad12_drv())
+            .field("reg_pad12_rde", &self.reg_pad12_rde())
+            .field("reg_pad12_rue", &self.reg_pad12_rue())
+            .field("reg_pad12_mux_sel", &self.reg_pad12_mux_sel())
+            .field("reg_pad12_fun_sel", &self.reg_pad12_fun_sel())
+            .field("reg_pad12_slp_sel", &self.reg_pad12_slp_sel())
+            .field("reg_pad12_slp_ie", &self.reg_pad12_slp_ie())
+            .field("reg_pad12_slp_oe", &self.reg_pad12_slp_oe())
+            .field("reg_pad12_fun_ie", &self.reg_pad12_fun_ie())
+            .field("reg_pad12_filter_en", &self.reg_pad12_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD120_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad13.rs b/esp32p4/src/lp_io_mux/pad13.rs
index 859997da20..3b4c21eda9 100644
--- a/esp32p4/src/lp_io_mux/pad13.rs
+++ b/esp32p4/src/lp_io_mux/pad13.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD13")
-            .field(
-                "reg_pad13_drv",
-                &format_args!("{}", self.reg_pad13_drv().bits()),
-            )
-            .field(
-                "reg_pad13_rde",
-                &format_args!("{}", self.reg_pad13_rde().bit()),
-            )
-            .field(
-                "reg_pad13_rue",
-                &format_args!("{}", self.reg_pad13_rue().bit()),
-            )
-            .field(
-                "reg_pad13_mux_sel",
-                &format_args!("{}", self.reg_pad13_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad13_fun_sel",
-                &format_args!("{}", self.reg_pad13_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad13_slp_sel",
-                &format_args!("{}", self.reg_pad13_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad13_slp_ie",
-                &format_args!("{}", self.reg_pad13_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad13_slp_oe",
-                &format_args!("{}", self.reg_pad13_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad13_fun_ie",
-                &format_args!("{}", self.reg_pad13_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad13_filter_en",
-                &format_args!("{}", self.reg_pad13_filter_en().bit()),
-            )
+            .field("reg_pad13_drv", &self.reg_pad13_drv())
+            .field("reg_pad13_rde", &self.reg_pad13_rde())
+            .field("reg_pad13_rue", &self.reg_pad13_rue())
+            .field("reg_pad13_mux_sel", &self.reg_pad13_mux_sel())
+            .field("reg_pad13_fun_sel", &self.reg_pad13_fun_sel())
+            .field("reg_pad13_slp_sel", &self.reg_pad13_slp_sel())
+            .field("reg_pad13_slp_ie", &self.reg_pad13_slp_ie())
+            .field("reg_pad13_slp_oe", &self.reg_pad13_slp_oe())
+            .field("reg_pad13_fun_ie", &self.reg_pad13_fun_ie())
+            .field("reg_pad13_filter_en", &self.reg_pad13_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad14.rs b/esp32p4/src/lp_io_mux/pad14.rs
index 9f892b754c..77ac9eac2a 100644
--- a/esp32p4/src/lp_io_mux/pad14.rs
+++ b/esp32p4/src/lp_io_mux/pad14.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD14")
-            .field(
-                "reg_pad14_drv",
-                &format_args!("{}", self.reg_pad14_drv().bits()),
-            )
-            .field(
-                "reg_pad14_rde",
-                &format_args!("{}", self.reg_pad14_rde().bit()),
-            )
-            .field(
-                "reg_pad14_rue",
-                &format_args!("{}", self.reg_pad14_rue().bit()),
-            )
-            .field(
-                "reg_pad14_mux_sel",
-                &format_args!("{}", self.reg_pad14_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad14_fun_sel",
-                &format_args!("{}", self.reg_pad14_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad14_slp_sel",
-                &format_args!("{}", self.reg_pad14_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad14_slp_ie",
-                &format_args!("{}", self.reg_pad14_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad14_slp_oe",
-                &format_args!("{}", self.reg_pad14_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad14_fun_ie",
-                &format_args!("{}", self.reg_pad14_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad14_filter_en",
-                &format_args!("{}", self.reg_pad14_filter_en().bit()),
-            )
+            .field("reg_pad14_drv", &self.reg_pad14_drv())
+            .field("reg_pad14_rde", &self.reg_pad14_rde())
+            .field("reg_pad14_rue", &self.reg_pad14_rue())
+            .field("reg_pad14_mux_sel", &self.reg_pad14_mux_sel())
+            .field("reg_pad14_fun_sel", &self.reg_pad14_fun_sel())
+            .field("reg_pad14_slp_sel", &self.reg_pad14_slp_sel())
+            .field("reg_pad14_slp_ie", &self.reg_pad14_slp_ie())
+            .field("reg_pad14_slp_oe", &self.reg_pad14_slp_oe())
+            .field("reg_pad14_fun_ie", &self.reg_pad14_fun_ie())
+            .field("reg_pad14_filter_en", &self.reg_pad14_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad15.rs b/esp32p4/src/lp_io_mux/pad15.rs
index dd50eb7c52..b5eef0d56f 100644
--- a/esp32p4/src/lp_io_mux/pad15.rs
+++ b/esp32p4/src/lp_io_mux/pad15.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD15")
-            .field(
-                "reg_pad15_drv",
-                &format_args!("{}", self.reg_pad15_drv().bits()),
-            )
-            .field(
-                "reg_pad15_rde",
-                &format_args!("{}", self.reg_pad15_rde().bit()),
-            )
-            .field(
-                "reg_pad15_rue",
-                &format_args!("{}", self.reg_pad15_rue().bit()),
-            )
-            .field(
-                "reg_pad15_mux_sel",
-                &format_args!("{}", self.reg_pad15_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad15_fun_sel",
-                &format_args!("{}", self.reg_pad15_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad15_slp_sel",
-                &format_args!("{}", self.reg_pad15_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad15_slp_ie",
-                &format_args!("{}", self.reg_pad15_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad15_slp_oe",
-                &format_args!("{}", self.reg_pad15_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad15_fun_ie",
-                &format_args!("{}", self.reg_pad15_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad15_filter_en",
-                &format_args!("{}", self.reg_pad15_filter_en().bit()),
-            )
+            .field("reg_pad15_drv", &self.reg_pad15_drv())
+            .field("reg_pad15_rde", &self.reg_pad15_rde())
+            .field("reg_pad15_rue", &self.reg_pad15_rue())
+            .field("reg_pad15_mux_sel", &self.reg_pad15_mux_sel())
+            .field("reg_pad15_fun_sel", &self.reg_pad15_fun_sel())
+            .field("reg_pad15_slp_sel", &self.reg_pad15_slp_sel())
+            .field("reg_pad15_slp_ie", &self.reg_pad15_slp_ie())
+            .field("reg_pad15_slp_oe", &self.reg_pad15_slp_oe())
+            .field("reg_pad15_fun_ie", &self.reg_pad15_fun_ie())
+            .field("reg_pad15_filter_en", &self.reg_pad15_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad2.rs b/esp32p4/src/lp_io_mux/pad2.rs
index fc1ae05af2..76aa675e20 100644
--- a/esp32p4/src/lp_io_mux/pad2.rs
+++ b/esp32p4/src/lp_io_mux/pad2.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD2")
-            .field(
-                "reg_pad2_drv",
-                &format_args!("{}", self.reg_pad2_drv().bits()),
-            )
-            .field(
-                "reg_pad2_rde",
-                &format_args!("{}", self.reg_pad2_rde().bit()),
-            )
-            .field(
-                "reg_pad2_rue",
-                &format_args!("{}", self.reg_pad2_rue().bit()),
-            )
-            .field(
-                "reg_pad2_mux_sel",
-                &format_args!("{}", self.reg_pad2_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad2_fun_sel",
-                &format_args!("{}", self.reg_pad2_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad2_slp_sel",
-                &format_args!("{}", self.reg_pad2_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad2_slp_ie",
-                &format_args!("{}", self.reg_pad2_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad2_slp_oe",
-                &format_args!("{}", self.reg_pad2_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad2_fun_ie",
-                &format_args!("{}", self.reg_pad2_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad2_filter_en",
-                &format_args!("{}", self.reg_pad2_filter_en().bit()),
-            )
+            .field("reg_pad2_drv", &self.reg_pad2_drv())
+            .field("reg_pad2_rde", &self.reg_pad2_rde())
+            .field("reg_pad2_rue", &self.reg_pad2_rue())
+            .field("reg_pad2_mux_sel", &self.reg_pad2_mux_sel())
+            .field("reg_pad2_fun_sel", &self.reg_pad2_fun_sel())
+            .field("reg_pad2_slp_sel", &self.reg_pad2_slp_sel())
+            .field("reg_pad2_slp_ie", &self.reg_pad2_slp_ie())
+            .field("reg_pad2_slp_oe", &self.reg_pad2_slp_oe())
+            .field("reg_pad2_fun_ie", &self.reg_pad2_fun_ie())
+            .field("reg_pad2_filter_en", &self.reg_pad2_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad3.rs b/esp32p4/src/lp_io_mux/pad3.rs
index 71981dbd7c..6dfe3bd2e9 100644
--- a/esp32p4/src/lp_io_mux/pad3.rs
+++ b/esp32p4/src/lp_io_mux/pad3.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD3")
-            .field(
-                "reg_pad3_drv",
-                &format_args!("{}", self.reg_pad3_drv().bits()),
-            )
-            .field(
-                "reg_pad3_rde",
-                &format_args!("{}", self.reg_pad3_rde().bit()),
-            )
-            .field(
-                "reg_pad3_rue",
-                &format_args!("{}", self.reg_pad3_rue().bit()),
-            )
-            .field(
-                "reg_pad3_mux_sel",
-                &format_args!("{}", self.reg_pad3_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad3_fun_sel",
-                &format_args!("{}", self.reg_pad3_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad3_slp_sel",
-                &format_args!("{}", self.reg_pad3_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad3_slp_ie",
-                &format_args!("{}", self.reg_pad3_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad3_slp_oe",
-                &format_args!("{}", self.reg_pad3_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad3_fun_ie",
-                &format_args!("{}", self.reg_pad3_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad3_filter_en",
-                &format_args!("{}", self.reg_pad3_filter_en().bit()),
-            )
+            .field("reg_pad3_drv", &self.reg_pad3_drv())
+            .field("reg_pad3_rde", &self.reg_pad3_rde())
+            .field("reg_pad3_rue", &self.reg_pad3_rue())
+            .field("reg_pad3_mux_sel", &self.reg_pad3_mux_sel())
+            .field("reg_pad3_fun_sel", &self.reg_pad3_fun_sel())
+            .field("reg_pad3_slp_sel", &self.reg_pad3_slp_sel())
+            .field("reg_pad3_slp_ie", &self.reg_pad3_slp_ie())
+            .field("reg_pad3_slp_oe", &self.reg_pad3_slp_oe())
+            .field("reg_pad3_fun_ie", &self.reg_pad3_fun_ie())
+            .field("reg_pad3_filter_en", &self.reg_pad3_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad4.rs b/esp32p4/src/lp_io_mux/pad4.rs
index 8536180fe1..631a90fe9b 100644
--- a/esp32p4/src/lp_io_mux/pad4.rs
+++ b/esp32p4/src/lp_io_mux/pad4.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD4")
-            .field(
-                "reg_pad4_drv",
-                &format_args!("{}", self.reg_pad4_drv().bits()),
-            )
-            .field(
-                "reg_pad4_rde",
-                &format_args!("{}", self.reg_pad4_rde().bit()),
-            )
-            .field(
-                "reg_pad4_rue",
-                &format_args!("{}", self.reg_pad4_rue().bit()),
-            )
-            .field(
-                "reg_pad4_mux_sel",
-                &format_args!("{}", self.reg_pad4_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad4_fun_sel",
-                &format_args!("{}", self.reg_pad4_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad4_slp_sel",
-                &format_args!("{}", self.reg_pad4_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad4_slp_ie",
-                &format_args!("{}", self.reg_pad4_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad4_slp_oe",
-                &format_args!("{}", self.reg_pad4_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad4_fun_ie",
-                &format_args!("{}", self.reg_pad4_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad4_filter_en",
-                &format_args!("{}", self.reg_pad4_filter_en().bit()),
-            )
+            .field("reg_pad4_drv", &self.reg_pad4_drv())
+            .field("reg_pad4_rde", &self.reg_pad4_rde())
+            .field("reg_pad4_rue", &self.reg_pad4_rue())
+            .field("reg_pad4_mux_sel", &self.reg_pad4_mux_sel())
+            .field("reg_pad4_fun_sel", &self.reg_pad4_fun_sel())
+            .field("reg_pad4_slp_sel", &self.reg_pad4_slp_sel())
+            .field("reg_pad4_slp_ie", &self.reg_pad4_slp_ie())
+            .field("reg_pad4_slp_oe", &self.reg_pad4_slp_oe())
+            .field("reg_pad4_fun_ie", &self.reg_pad4_fun_ie())
+            .field("reg_pad4_filter_en", &self.reg_pad4_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad5.rs b/esp32p4/src/lp_io_mux/pad5.rs
index c9c172018f..3b8435d5b1 100644
--- a/esp32p4/src/lp_io_mux/pad5.rs
+++ b/esp32p4/src/lp_io_mux/pad5.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD5")
-            .field(
-                "reg_pad5_drv",
-                &format_args!("{}", self.reg_pad5_drv().bits()),
-            )
-            .field(
-                "reg_pad5_rde",
-                &format_args!("{}", self.reg_pad5_rde().bit()),
-            )
-            .field(
-                "reg_pad5_rue",
-                &format_args!("{}", self.reg_pad5_rue().bit()),
-            )
-            .field(
-                "reg_pad5_mux_sel",
-                &format_args!("{}", self.reg_pad5_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad5_fun_sel",
-                &format_args!("{}", self.reg_pad5_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad5_slp_sel",
-                &format_args!("{}", self.reg_pad5_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad5_slp_ie",
-                &format_args!("{}", self.reg_pad5_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad5_slp_oe",
-                &format_args!("{}", self.reg_pad5_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad5_fun_ie",
-                &format_args!("{}", self.reg_pad5_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad5_filter_en",
-                &format_args!("{}", self.reg_pad5_filter_en().bit()),
-            )
+            .field("reg_pad5_drv", &self.reg_pad5_drv())
+            .field("reg_pad5_rde", &self.reg_pad5_rde())
+            .field("reg_pad5_rue", &self.reg_pad5_rue())
+            .field("reg_pad5_mux_sel", &self.reg_pad5_mux_sel())
+            .field("reg_pad5_fun_sel", &self.reg_pad5_fun_sel())
+            .field("reg_pad5_slp_sel", &self.reg_pad5_slp_sel())
+            .field("reg_pad5_slp_ie", &self.reg_pad5_slp_ie())
+            .field("reg_pad5_slp_oe", &self.reg_pad5_slp_oe())
+            .field("reg_pad5_fun_ie", &self.reg_pad5_fun_ie())
+            .field("reg_pad5_filter_en", &self.reg_pad5_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad6.rs b/esp32p4/src/lp_io_mux/pad6.rs
index e406157554..92c6240bbc 100644
--- a/esp32p4/src/lp_io_mux/pad6.rs
+++ b/esp32p4/src/lp_io_mux/pad6.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD6")
-            .field(
-                "reg_pad6_drv",
-                &format_args!("{}", self.reg_pad6_drv().bits()),
-            )
-            .field(
-                "reg_pad6_rde",
-                &format_args!("{}", self.reg_pad6_rde().bit()),
-            )
-            .field(
-                "reg_pad6_rue",
-                &format_args!("{}", self.reg_pad6_rue().bit()),
-            )
-            .field(
-                "reg_pad6_mux_sel",
-                &format_args!("{}", self.reg_pad6_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad6_fun_sel",
-                &format_args!("{}", self.reg_pad6_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad6_slp_sel",
-                &format_args!("{}", self.reg_pad6_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad6_slp_ie",
-                &format_args!("{}", self.reg_pad6_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad6_slp_oe",
-                &format_args!("{}", self.reg_pad6_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad6_fun_ie",
-                &format_args!("{}", self.reg_pad6_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad6_filter_en",
-                &format_args!("{}", self.reg_pad6_filter_en().bit()),
-            )
+            .field("reg_pad6_drv", &self.reg_pad6_drv())
+            .field("reg_pad6_rde", &self.reg_pad6_rde())
+            .field("reg_pad6_rue", &self.reg_pad6_rue())
+            .field("reg_pad6_mux_sel", &self.reg_pad6_mux_sel())
+            .field("reg_pad6_fun_sel", &self.reg_pad6_fun_sel())
+            .field("reg_pad6_slp_sel", &self.reg_pad6_slp_sel())
+            .field("reg_pad6_slp_ie", &self.reg_pad6_slp_ie())
+            .field("reg_pad6_slp_oe", &self.reg_pad6_slp_oe())
+            .field("reg_pad6_fun_ie", &self.reg_pad6_fun_ie())
+            .field("reg_pad6_filter_en", &self.reg_pad6_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad7.rs b/esp32p4/src/lp_io_mux/pad7.rs
index 177545ac59..262d371852 100644
--- a/esp32p4/src/lp_io_mux/pad7.rs
+++ b/esp32p4/src/lp_io_mux/pad7.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD7")
-            .field(
-                "reg_pad7_drv",
-                &format_args!("{}", self.reg_pad7_drv().bits()),
-            )
-            .field(
-                "reg_pad7_rde",
-                &format_args!("{}", self.reg_pad7_rde().bit()),
-            )
-            .field(
-                "reg_pad7_rue",
-                &format_args!("{}", self.reg_pad7_rue().bit()),
-            )
-            .field(
-                "reg_pad7_mux_sel",
-                &format_args!("{}", self.reg_pad7_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad7_fun_sel",
-                &format_args!("{}", self.reg_pad7_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad7_slp_sel",
-                &format_args!("{}", self.reg_pad7_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad7_slp_ie",
-                &format_args!("{}", self.reg_pad7_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad7_slp_oe",
-                &format_args!("{}", self.reg_pad7_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad7_fun_ie",
-                &format_args!("{}", self.reg_pad7_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad7_filter_en",
-                &format_args!("{}", self.reg_pad7_filter_en().bit()),
-            )
+            .field("reg_pad7_drv", &self.reg_pad7_drv())
+            .field("reg_pad7_rde", &self.reg_pad7_rde())
+            .field("reg_pad7_rue", &self.reg_pad7_rue())
+            .field("reg_pad7_mux_sel", &self.reg_pad7_mux_sel())
+            .field("reg_pad7_fun_sel", &self.reg_pad7_fun_sel())
+            .field("reg_pad7_slp_sel", &self.reg_pad7_slp_sel())
+            .field("reg_pad7_slp_ie", &self.reg_pad7_slp_ie())
+            .field("reg_pad7_slp_oe", &self.reg_pad7_slp_oe())
+            .field("reg_pad7_fun_ie", &self.reg_pad7_fun_ie())
+            .field("reg_pad7_filter_en", &self.reg_pad7_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad8.rs b/esp32p4/src/lp_io_mux/pad8.rs
index d0be715ecb..10ea067a27 100644
--- a/esp32p4/src/lp_io_mux/pad8.rs
+++ b/esp32p4/src/lp_io_mux/pad8.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD8")
-            .field(
-                "reg_pad8_drv",
-                &format_args!("{}", self.reg_pad8_drv().bits()),
-            )
-            .field(
-                "reg_pad8_rde",
-                &format_args!("{}", self.reg_pad8_rde().bit()),
-            )
-            .field(
-                "reg_pad8_rue",
-                &format_args!("{}", self.reg_pad8_rue().bit()),
-            )
-            .field(
-                "reg_pad8_mux_sel",
-                &format_args!("{}", self.reg_pad8_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad8_fun_sel",
-                &format_args!("{}", self.reg_pad8_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad8_slp_sel",
-                &format_args!("{}", self.reg_pad8_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad8_slp_ie",
-                &format_args!("{}", self.reg_pad8_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad8_slp_oe",
-                &format_args!("{}", self.reg_pad8_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad8_fun_ie",
-                &format_args!("{}", self.reg_pad8_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad8_filter_en",
-                &format_args!("{}", self.reg_pad8_filter_en().bit()),
-            )
+            .field("reg_pad8_drv", &self.reg_pad8_drv())
+            .field("reg_pad8_rde", &self.reg_pad8_rde())
+            .field("reg_pad8_rue", &self.reg_pad8_rue())
+            .field("reg_pad8_mux_sel", &self.reg_pad8_mux_sel())
+            .field("reg_pad8_fun_sel", &self.reg_pad8_fun_sel())
+            .field("reg_pad8_slp_sel", &self.reg_pad8_slp_sel())
+            .field("reg_pad8_slp_ie", &self.reg_pad8_slp_ie())
+            .field("reg_pad8_slp_oe", &self.reg_pad8_slp_oe())
+            .field("reg_pad8_fun_ie", &self.reg_pad8_fun_ie())
+            .field("reg_pad8_filter_en", &self.reg_pad8_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/pad9.rs b/esp32p4/src/lp_io_mux/pad9.rs
index 392d9798a7..e44ee60565 100644
--- a/esp32p4/src/lp_io_mux/pad9.rs
+++ b/esp32p4/src/lp_io_mux/pad9.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD9")
-            .field(
-                "reg_pad9_drv",
-                &format_args!("{}", self.reg_pad9_drv().bits()),
-            )
-            .field(
-                "reg_pad9_rde",
-                &format_args!("{}", self.reg_pad9_rde().bit()),
-            )
-            .field(
-                "reg_pad9_rue",
-                &format_args!("{}", self.reg_pad9_rue().bit()),
-            )
-            .field(
-                "reg_pad9_mux_sel",
-                &format_args!("{}", self.reg_pad9_mux_sel().bit()),
-            )
-            .field(
-                "reg_pad9_fun_sel",
-                &format_args!("{}", self.reg_pad9_fun_sel().bits()),
-            )
-            .field(
-                "reg_pad9_slp_sel",
-                &format_args!("{}", self.reg_pad9_slp_sel().bit()),
-            )
-            .field(
-                "reg_pad9_slp_ie",
-                &format_args!("{}", self.reg_pad9_slp_ie().bit()),
-            )
-            .field(
-                "reg_pad9_slp_oe",
-                &format_args!("{}", self.reg_pad9_slp_oe().bit()),
-            )
-            .field(
-                "reg_pad9_fun_ie",
-                &format_args!("{}", self.reg_pad9_fun_ie().bit()),
-            )
-            .field(
-                "reg_pad9_filter_en",
-                &format_args!("{}", self.reg_pad9_filter_en().bit()),
-            )
+            .field("reg_pad9_drv", &self.reg_pad9_drv())
+            .field("reg_pad9_rde", &self.reg_pad9_rde())
+            .field("reg_pad9_rue", &self.reg_pad9_rue())
+            .field("reg_pad9_mux_sel", &self.reg_pad9_mux_sel())
+            .field("reg_pad9_fun_sel", &self.reg_pad9_fun_sel())
+            .field("reg_pad9_slp_sel", &self.reg_pad9_slp_sel())
+            .field("reg_pad9_slp_ie", &self.reg_pad9_slp_ie())
+            .field("reg_pad9_slp_oe", &self.reg_pad9_slp_oe())
+            .field("reg_pad9_fun_ie", &self.reg_pad9_fun_ie())
+            .field("reg_pad9_filter_en", &self.reg_pad9_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_io_mux/ver_date.rs b/esp32p4/src/lp_io_mux/ver_date.rs
index 71eb865fca..09f6a314a6 100644
--- a/esp32p4/src/lp_io_mux/ver_date.rs
+++ b/esp32p4/src/lp_io_mux/ver_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VER_DATE")
-            .field(
-                "reg_ver_date",
-                &format_args!("{}", self.reg_ver_date().bits()),
-            )
+            .field("reg_ver_date", &self.reg_ver_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VER_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_peri/adc_ctrl.rs b/esp32p4/src/lp_peri/adc_ctrl.rs
index 091a06f967..d0d1463c05 100644
--- a/esp32p4/src/lp_peri/adc_ctrl.rs
+++ b/esp32p4/src/lp_peri/adc_ctrl.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADC_CTRL")
-            .field(
-                "sar2_clk_force_on",
-                &format_args!("{}", self.sar2_clk_force_on().bit()),
-            )
-            .field(
-                "sar1_clk_force_on",
-                &format_args!("{}", self.sar1_clk_force_on().bit()),
-            )
-            .field(
-                "lpadc_func_div_num",
-                &format_args!("{}", self.lpadc_func_div_num().bits()),
-            )
-            .field(
-                "lpadc_sar2_div_num",
-                &format_args!("{}", self.lpadc_sar2_div_num().bits()),
-            )
-            .field(
-                "lpadc_sar1_div_num",
-                &format_args!("{}", self.lpadc_sar1_div_num().bits()),
-            )
+            .field("sar2_clk_force_on", &self.sar2_clk_force_on())
+            .field("sar1_clk_force_on", &self.sar1_clk_force_on())
+            .field("lpadc_func_div_num", &self.lpadc_func_div_num())
+            .field("lpadc_sar2_div_num", &self.lpadc_sar2_div_num())
+            .field("lpadc_sar1_div_num", &self.lpadc_sar1_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_peri/clk_en.rs b/esp32p4/src/lp_peri/clk_en.rs
index 93e318ae96..4475b8abbe 100644
--- a/esp32p4/src/lp_peri/clk_en.rs
+++ b/esp32p4/src/lp_peri/clk_en.rs
@@ -152,76 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EN")
-            .field("ck_en_rng", &format_args!("{}", self.ck_en_rng().bit()))
-            .field(
-                "ck_en_lp_tsens",
-                &format_args!("{}", self.ck_en_lp_tsens().bit()),
-            )
-            .field(
-                "ck_en_lp_pms",
-                &format_args!("{}", self.ck_en_lp_pms().bit()),
-            )
-            .field(
-                "ck_en_lp_efuse",
-                &format_args!("{}", self.ck_en_lp_efuse().bit()),
-            )
-            .field(
-                "ck_en_lp_iomux",
-                &format_args!("{}", self.ck_en_lp_iomux().bit()),
-            )
-            .field(
-                "ck_en_lp_touch",
-                &format_args!("{}", self.ck_en_lp_touch().bit()),
-            )
-            .field(
-                "ck_en_lp_spi",
-                &format_args!("{}", self.ck_en_lp_spi().bit()),
-            )
-            .field(
-                "ck_en_lp_adc",
-                &format_args!("{}", self.ck_en_lp_adc().bit()),
-            )
-            .field(
-                "ck_en_lp_i2s_tx",
-                &format_args!("{}", self.ck_en_lp_i2s_tx().bit()),
-            )
-            .field(
-                "ck_en_lp_i2s_rx",
-                &format_args!("{}", self.ck_en_lp_i2s_rx().bit()),
-            )
-            .field(
-                "ck_en_lp_i2s",
-                &format_args!("{}", self.ck_en_lp_i2s().bit()),
-            )
-            .field(
-                "ck_en_lp_i2cmst",
-                &format_args!("{}", self.ck_en_lp_i2cmst().bit()),
-            )
-            .field(
-                "ck_en_lp_i2c",
-                &format_args!("{}", self.ck_en_lp_i2c().bit()),
-            )
-            .field(
-                "ck_en_lp_uart",
-                &format_args!("{}", self.ck_en_lp_uart().bit()),
-            )
-            .field(
-                "ck_en_lp_intr",
-                &format_args!("{}", self.ck_en_lp_intr().bit()),
-            )
-            .field(
-                "ck_en_lp_core",
-                &format_args!("{}", self.ck_en_lp_core().bit()),
-            )
+            .field("ck_en_rng", &self.ck_en_rng())
+            .field("ck_en_lp_tsens", &self.ck_en_lp_tsens())
+            .field("ck_en_lp_pms", &self.ck_en_lp_pms())
+            .field("ck_en_lp_efuse", &self.ck_en_lp_efuse())
+            .field("ck_en_lp_iomux", &self.ck_en_lp_iomux())
+            .field("ck_en_lp_touch", &self.ck_en_lp_touch())
+            .field("ck_en_lp_spi", &self.ck_en_lp_spi())
+            .field("ck_en_lp_adc", &self.ck_en_lp_adc())
+            .field("ck_en_lp_i2s_tx", &self.ck_en_lp_i2s_tx())
+            .field("ck_en_lp_i2s_rx", &self.ck_en_lp_i2s_rx())
+            .field("ck_en_lp_i2s", &self.ck_en_lp_i2s())
+            .field("ck_en_lp_i2cmst", &self.ck_en_lp_i2cmst())
+            .field("ck_en_lp_i2c", &self.ck_en_lp_i2c())
+            .field("ck_en_lp_uart", &self.ck_en_lp_uart())
+            .field("ck_en_lp_intr", &self.ck_en_lp_intr())
+            .field("ck_en_lp_core", &self.ck_en_lp_core())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_peri/core_clk_sel.rs b/esp32p4/src/lp_peri/core_clk_sel.rs
index 08203e6b41..92e05db935 100644
--- a/esp32p4/src/lp_peri/core_clk_sel.rs
+++ b/esp32p4/src/lp_peri/core_clk_sel.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_CLK_SEL")
-            .field(
-                "lp_i2s_tx_clk_sel",
-                &format_args!("{}", self.lp_i2s_tx_clk_sel().bits()),
-            )
-            .field(
-                "lp_i2s_rx_clk_sel",
-                &format_args!("{}", self.lp_i2s_rx_clk_sel().bits()),
-            )
-            .field(
-                "lp_i2c_clk_sel",
-                &format_args!("{}", self.lp_i2c_clk_sel().bits()),
-            )
-            .field(
-                "lp_uart_clk_sel",
-                &format_args!("{}", self.lp_uart_clk_sel().bits()),
-            )
+            .field("lp_i2s_tx_clk_sel", &self.lp_i2s_tx_clk_sel())
+            .field("lp_i2s_rx_clk_sel", &self.lp_i2s_rx_clk_sel())
+            .field("lp_i2c_clk_sel", &self.lp_i2c_clk_sel())
+            .field("lp_uart_clk_sel", &self.lp_uart_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_CLK_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 24:25 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_peri/cpu.rs b/esp32p4/src/lp_peri/cpu.rs
index 1d6fd7b274..ff93641431 100644
--- a/esp32p4/src/lp_peri/cpu.rs
+++ b/esp32p4/src/lp_peri/cpu.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU")
-            .field(
-                "lpcore_dbgm_unavailable",
-                &format_args!("{}", self.lpcore_dbgm_unavailable().bit()),
-            )
+            .field("lpcore_dbgm_unavailable", &self.lpcore_dbgm_unavailable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_peri/date.rs b/esp32p4/src/lp_peri/date.rs
index 1988aab0c4..dd9a8122d3 100644
--- a/esp32p4/src/lp_peri/date.rs
+++ b/esp32p4/src/lp_peri/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_peri/lp_i2s_rxclk_div_num.rs b/esp32p4/src/lp_peri/lp_i2s_rxclk_div_num.rs
index 5d1c2e4869..87a9fe9fd8 100644
--- a/esp32p4/src/lp_peri/lp_i2s_rxclk_div_num.rs
+++ b/esp32p4/src/lp_peri/lp_i2s_rxclk_div_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_I2S_RXCLK_DIV_NUM")
-            .field(
-                "lp_i2s_rx_clkm_div_num",
-                &format_args!("{}", self.lp_i2s_rx_clkm_div_num().bits()),
-            )
+            .field("lp_i2s_rx_clkm_div_num", &self.lp_i2s_rx_clkm_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_I2S_RXCLK_DIV_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 24:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_peri/lp_i2s_rxclk_div_xyz.rs b/esp32p4/src/lp_peri/lp_i2s_rxclk_div_xyz.rs
index cba0a9e872..bb437c4bec 100644
--- a/esp32p4/src/lp_peri/lp_i2s_rxclk_div_xyz.rs
+++ b/esp32p4/src/lp_peri/lp_i2s_rxclk_div_xyz.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_I2S_RXCLK_DIV_XYZ")
-            .field(
-                "lp_i2s_rx_clkm_div_yn1",
-                &format_args!("{}", self.lp_i2s_rx_clkm_div_yn1().bit()),
-            )
-            .field(
-                "lp_i2s_rx_clkm_div_z",
-                &format_args!("{}", self.lp_i2s_rx_clkm_div_z().bits()),
-            )
-            .field(
-                "lp_i2s_rx_clkm_div_y",
-                &format_args!("{}", self.lp_i2s_rx_clkm_div_y().bits()),
-            )
-            .field(
-                "lp_i2s_rx_clkm_div_x",
-                &format_args!("{}", self.lp_i2s_rx_clkm_div_x().bits()),
-            )
+            .field("lp_i2s_rx_clkm_div_yn1", &self.lp_i2s_rx_clkm_div_yn1())
+            .field("lp_i2s_rx_clkm_div_z", &self.lp_i2s_rx_clkm_div_z())
+            .field("lp_i2s_rx_clkm_div_y", &self.lp_i2s_rx_clkm_div_y())
+            .field("lp_i2s_rx_clkm_div_x", &self.lp_i2s_rx_clkm_div_x())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_I2S_RXCLK_DIV_XYZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_peri/lp_i2s_txclk_div_num.rs b/esp32p4/src/lp_peri/lp_i2s_txclk_div_num.rs
index 1bcc9e640c..ddc7e8813a 100644
--- a/esp32p4/src/lp_peri/lp_i2s_txclk_div_num.rs
+++ b/esp32p4/src/lp_peri/lp_i2s_txclk_div_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_I2S_TXCLK_DIV_NUM")
-            .field(
-                "lp_i2s_tx_clkm_div_num",
-                &format_args!("{}", self.lp_i2s_tx_clkm_div_num().bits()),
-            )
+            .field("lp_i2s_tx_clkm_div_num", &self.lp_i2s_tx_clkm_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_I2S_TXCLK_DIV_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 24:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_peri/lp_i2s_txclk_div_xyz.rs b/esp32p4/src/lp_peri/lp_i2s_txclk_div_xyz.rs
index 5178546cb1..e8de3f6e66 100644
--- a/esp32p4/src/lp_peri/lp_i2s_txclk_div_xyz.rs
+++ b/esp32p4/src/lp_peri/lp_i2s_txclk_div_xyz.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_I2S_TXCLK_DIV_XYZ")
-            .field(
-                "lp_i2s_tx_clkm_div_yn1",
-                &format_args!("{}", self.lp_i2s_tx_clkm_div_yn1().bit()),
-            )
-            .field(
-                "lp_i2s_tx_clkm_div_z",
-                &format_args!("{}", self.lp_i2s_tx_clkm_div_z().bits()),
-            )
-            .field(
-                "lp_i2s_tx_clkm_div_y",
-                &format_args!("{}", self.lp_i2s_tx_clkm_div_y().bits()),
-            )
-            .field(
-                "lp_i2s_tx_clkm_div_x",
-                &format_args!("{}", self.lp_i2s_tx_clkm_div_x().bits()),
-            )
+            .field("lp_i2s_tx_clkm_div_yn1", &self.lp_i2s_tx_clkm_div_yn1())
+            .field("lp_i2s_tx_clkm_div_z", &self.lp_i2s_tx_clkm_div_z())
+            .field("lp_i2s_tx_clkm_div_y", &self.lp_i2s_tx_clkm_div_y())
+            .field("lp_i2s_tx_clkm_div_x", &self.lp_i2s_tx_clkm_div_x())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_I2S_TXCLK_DIV_XYZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_peri/mem_ctrl.rs b/esp32p4/src/lp_peri/mem_ctrl.rs
index a778fb85d5..f9536c5758 100644
--- a/esp32p4/src/lp_peri/mem_ctrl.rs
+++ b/esp32p4/src/lp_peri/mem_ctrl.rs
@@ -46,31 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CTRL")
-            .field(
-                "lp_uart_wakeup_flag",
-                &format_args!("{}", self.lp_uart_wakeup_flag().bit()),
-            )
-            .field(
-                "lp_uart_wakeup_en",
-                &format_args!("{}", self.lp_uart_wakeup_en().bit()),
-            )
-            .field(
-                "lp_uart_mem_force_pd",
-                &format_args!("{}", self.lp_uart_mem_force_pd().bit()),
-            )
-            .field(
-                "lp_uart_mem_force_pu",
-                &format_args!("{}", self.lp_uart_mem_force_pu().bit()),
-            )
+            .field("lp_uart_wakeup_flag", &self.lp_uart_wakeup_flag())
+            .field("lp_uart_wakeup_en", &self.lp_uart_wakeup_en())
+            .field("lp_uart_mem_force_pd", &self.lp_uart_mem_force_pd())
+            .field("lp_uart_mem_force_pu", &self.lp_uart_mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_peri/reset_en.rs b/esp32p4/src/lp_peri/reset_en.rs
index 25894f9443..34ceeb98a1 100644
--- a/esp32p4/src/lp_peri/reset_en.rs
+++ b/esp32p4/src/lp_peri/reset_en.rs
@@ -127,67 +127,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET_EN")
-            .field(
-                "rst_en_lp_tsens",
-                &format_args!("{}", self.rst_en_lp_tsens().bit()),
-            )
-            .field(
-                "rst_en_lp_pms",
-                &format_args!("{}", self.rst_en_lp_pms().bit()),
-            )
-            .field(
-                "rst_en_lp_efuse",
-                &format_args!("{}", self.rst_en_lp_efuse().bit()),
-            )
-            .field(
-                "rst_en_lp_iomux",
-                &format_args!("{}", self.rst_en_lp_iomux().bit()),
-            )
-            .field(
-                "rst_en_lp_touch",
-                &format_args!("{}", self.rst_en_lp_touch().bit()),
-            )
-            .field(
-                "rst_en_lp_spi",
-                &format_args!("{}", self.rst_en_lp_spi().bit()),
-            )
-            .field(
-                "rst_en_lp_adc",
-                &format_args!("{}", self.rst_en_lp_adc().bit()),
-            )
-            .field(
-                "rst_en_lp_i2s",
-                &format_args!("{}", self.rst_en_lp_i2s().bit()),
-            )
-            .field(
-                "rst_en_lp_i2cmst",
-                &format_args!("{}", self.rst_en_lp_i2cmst().bit()),
-            )
-            .field(
-                "rst_en_lp_i2c",
-                &format_args!("{}", self.rst_en_lp_i2c().bit()),
-            )
-            .field(
-                "rst_en_lp_uart",
-                &format_args!("{}", self.rst_en_lp_uart().bit()),
-            )
-            .field(
-                "rst_en_lp_intr",
-                &format_args!("{}", self.rst_en_lp_intr().bit()),
-            )
-            .field(
-                "rst_en_lp_rom",
-                &format_args!("{}", self.rst_en_lp_rom().bit()),
-            )
+            .field("rst_en_lp_tsens", &self.rst_en_lp_tsens())
+            .field("rst_en_lp_pms", &self.rst_en_lp_pms())
+            .field("rst_en_lp_efuse", &self.rst_en_lp_efuse())
+            .field("rst_en_lp_iomux", &self.rst_en_lp_iomux())
+            .field("rst_en_lp_touch", &self.rst_en_lp_touch())
+            .field("rst_en_lp_spi", &self.rst_en_lp_spi())
+            .field("rst_en_lp_adc", &self.rst_en_lp_adc())
+            .field("rst_en_lp_i2s", &self.rst_en_lp_i2s())
+            .field("rst_en_lp_i2cmst", &self.rst_en_lp_i2cmst())
+            .field("rst_en_lp_i2c", &self.rst_en_lp_i2c())
+            .field("rst_en_lp_uart", &self.rst_en_lp_uart())
+            .field("rst_en_lp_intr", &self.rst_en_lp_intr())
+            .field("rst_en_lp_rom", &self.rst_en_lp_rom())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/ana_xpd_pad_group.rs b/esp32p4/src/lp_sys/ana_xpd_pad_group.rs
index 8dbd122579..2afc10ba8d 100644
--- a/esp32p4/src/lp_sys/ana_xpd_pad_group.rs
+++ b/esp32p4/src/lp_sys/ana_xpd_pad_group.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ANA_XPD_PAD_GROUP")
-            .field(
-                "ana_reg_xpd_pad_group",
-                &format_args!("{}", self.ana_reg_xpd_pad_group().bits()),
-            )
+            .field("ana_reg_xpd_pad_group", &self.ana_reg_xpd_pad_group())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ANA_XPD_PAD_GROUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Set 1 to power up pad group"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/backup_dma_cfg0.rs b/esp32p4/src/lp_sys/backup_dma_cfg0.rs
index f4fe025f89..b95702be4e 100644
--- a/esp32p4/src/lp_sys/backup_dma_cfg0.rs
+++ b/esp32p4/src/lp_sys/backup_dma_cfg0.rs
@@ -44,31 +44,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BACKUP_DMA_CFG0")
-            .field(
-                "burst_limit_aon",
-                &format_args!("{}", self.burst_limit_aon().bits()),
-            )
-            .field(
-                "read_interval_aon",
-                &format_args!("{}", self.read_interval_aon().bits()),
-            )
+            .field("burst_limit_aon", &self.burst_limit_aon())
+            .field("read_interval_aon", &self.read_interval_aon())
             .field(
                 "link_backup_tout_thres_aon",
-                &format_args!("{}", self.link_backup_tout_thres_aon().bits()),
-            )
-            .field(
-                "link_tout_thres_aon",
-                &format_args!("{}", self.link_tout_thres_aon().bits()),
+                &self.link_backup_tout_thres_aon(),
             )
+            .field("link_tout_thres_aon", &self.link_tout_thres_aon())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_DMA_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/backup_dma_cfg1.rs b/esp32p4/src/lp_sys/backup_dma_cfg1.rs
index 25347c921d..c33b8038a3 100644
--- a/esp32p4/src/lp_sys/backup_dma_cfg1.rs
+++ b/esp32p4/src/lp_sys/backup_dma_cfg1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BACKUP_DMA_CFG1")
-            .field("aon_bypass", &format_args!("{}", self.aon_bypass().bit()))
+            .field("aon_bypass", &self.aon_bypass())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_DMA_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/backup_dma_cfg2.rs b/esp32p4/src/lp_sys/backup_dma_cfg2.rs
index 7ca77e0063..156a13ae10 100644
--- a/esp32p4/src/lp_sys/backup_dma_cfg2.rs
+++ b/esp32p4/src/lp_sys/backup_dma_cfg2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BACKUP_DMA_CFG2")
-            .field(
-                "link_addr_aon",
-                &format_args!("{}", self.link_addr_aon().bits()),
-            )
+            .field("link_addr_aon", &self.link_addr_aon())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_DMA_CFG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/boot_addr_hp_core1.rs b/esp32p4/src/lp_sys/boot_addr_hp_core1.rs
index b328c9b28c..613fffc14a 100644
--- a/esp32p4/src/lp_sys/boot_addr_hp_core1.rs
+++ b/esp32p4/src/lp_sys/boot_addr_hp_core1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BOOT_ADDR_HP_CORE1")
-            .field(
-                "boot_addr_hp_core1",
-                &format_args!("{}", self.boot_addr_hp_core1().bits()),
-            )
+            .field("boot_addr_hp_core1", &self.boot_addr_hp_core1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BOOT_ADDR_HP_CORE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/boot_addr_hp_lp.rs b/esp32p4/src/lp_sys/boot_addr_hp_lp.rs
index 6c3d7d2a78..bc21091c06 100644
--- a/esp32p4/src/lp_sys/boot_addr_hp_lp.rs
+++ b/esp32p4/src/lp_sys/boot_addr_hp_lp.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BOOT_ADDR_HP_LP")
-            .field(
-                "boot_addr_hp_lp",
-                &format_args!("{}", self.boot_addr_hp_lp().bits()),
-            )
+            .field("boot_addr_hp_lp", &self.boot_addr_hp_lp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BOOT_ADDR_HP_LP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/clk_sel_ctrl.rs b/esp32p4/src/lp_sys/clk_sel_ctrl.rs
index 1f351c4343..d03a2d11fe 100644
--- a/esp32p4/src/lp_sys/clk_sel_ctrl.rs
+++ b/esp32p4/src/lp_sys/clk_sel_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_SEL_CTRL")
-            .field(
-                "ena_sw_sel_sys_clk",
-                &format_args!("{}", self.ena_sw_sel_sys_clk().bit()),
-            )
-            .field(
-                "sw_sys_clk_src_sel",
-                &format_args!("{}", self.sw_sys_clk_src_sel().bit()),
-            )
+            .field("ena_sw_sel_sys_clk", &self.ena_sw_sel_sys_clk())
+            .field("sw_sys_clk_src_sel", &self.sw_sys_clk_src_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SEL_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/ext_wakeup1.rs b/esp32p4/src/lp_sys/ext_wakeup1.rs
index a716f451c4..a16f41d7d7 100644
--- a/esp32p4/src/lp_sys/ext_wakeup1.rs
+++ b/esp32p4/src/lp_sys/ext_wakeup1.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP1")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Bitmap to select RTC pads for ext wakeup1"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/ext_wakeup1_status.rs b/esp32p4/src/lp_sys/ext_wakeup1_status.rs
index 6e99c3a17f..6d0d93dbb2 100644
--- a/esp32p4/src/lp_sys/ext_wakeup1_status.rs
+++ b/esp32p4/src/lp_sys/ext_wakeup1_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP1_STATUS")
-            .field(
-                "ext_wakeup1_status",
-                &format_args!("{}", self.ext_wakeup1_status().bits()),
-            )
+            .field("ext_wakeup1_status", &self.ext_wakeup1_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP1_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup1_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXT_WAKEUP1_STATUS_SPEC;
 impl crate::RegisterSpec for EXT_WAKEUP1_STATUS_SPEC {
diff --git a/esp32p4/src/lp_sys/f2s_apb_brg_cntl.rs b/esp32p4/src/lp_sys/f2s_apb_brg_cntl.rs
index fed84ae237..ce5bc3a5e9 100644
--- a/esp32p4/src/lp_sys/f2s_apb_brg_cntl.rs
+++ b/esp32p4/src/lp_sys/f2s_apb_brg_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("F2S_APB_BRG_CNTL")
-            .field(
-                "f2s_apb_postw_en",
-                &format_args!("{}", self.f2s_apb_postw_en().bit()),
-            )
+            .field("f2s_apb_postw_en", &self.f2s_apb_postw_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<F2S_APB_BRG_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reserved"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/hp_mem_aux_ctrl.rs b/esp32p4/src/lp_sys/hp_mem_aux_ctrl.rs
index da3b24d447..ade786cd99 100644
--- a/esp32p4/src/lp_sys/hp_mem_aux_ctrl.rs
+++ b/esp32p4/src/lp_sys/hp_mem_aux_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_MEM_AUX_CTRL")
-            .field(
-                "hp_mem_aux_ctrl",
-                &format_args!("{}", self.hp_mem_aux_ctrl().bits()),
-            )
+            .field("hp_mem_aux_ctrl", &self.hp_mem_aux_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MEM_AUX_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/hp_por_rst_bypass_ctrl.rs b/esp32p4/src/lp_sys/hp_por_rst_bypass_ctrl.rs
index 5ea4990db3..93163d3cbb 100644
--- a/esp32p4/src/lp_sys/hp_por_rst_bypass_ctrl.rs
+++ b/esp32p4/src/lp_sys/hp_por_rst_bypass_ctrl.rs
@@ -28,21 +28,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_POR_RST_BYPASS_CTRL")
             .field(
                 "hp_po_cnnt_rstn_bypass_ctrl",
-                &format_args!("{}", self.hp_po_cnnt_rstn_bypass_ctrl().bits()),
-            )
-            .field(
-                "hp_po_rstn_bypass_ctrl",
-                &format_args!("{}", self.hp_po_rstn_bypass_ctrl().bits()),
+                &self.hp_po_cnnt_rstn_bypass_ctrl(),
             )
+            .field("hp_po_rstn_bypass_ctrl", &self.hp_po_rstn_bypass_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_POR_RST_BYPASS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:15 - 15\\] 1'b1: po_cnnt_rstn bypass sys_sw_rstn \\[14\\] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn \\[13\\] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn \\[12\\] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn \\[11\\] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst \\[10\\] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst \\[9\\] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn \\[8\\] 1'b1: po_cnnt_rstn bypass efuse_err_rstn"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/hp_rom_aux_ctrl.rs b/esp32p4/src/lp_sys/hp_rom_aux_ctrl.rs
index 73e88d9312..0d6f47a006 100644
--- a/esp32p4/src/lp_sys/hp_rom_aux_ctrl.rs
+++ b/esp32p4/src/lp_sys/hp_rom_aux_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ROM_AUX_CTRL")
-            .field(
-                "hp_rom_aux_ctrl",
-                &format_args!("{}", self.hp_rom_aux_ctrl().bits()),
-            )
+            .field("hp_rom_aux_ctrl", &self.hp_rom_aux_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ROM_AUX_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/hp_root_clk_ctrl.rs b/esp32p4/src/lp_sys/hp_root_clk_ctrl.rs
index ca7c066c3a..c48e70e5c4 100644
--- a/esp32p4/src/lp_sys/hp_root_clk_ctrl.rs
+++ b/esp32p4/src/lp_sys/hp_root_clk_ctrl.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ROOT_CLK_CTRL")
-            .field("cpu_clk_en", &format_args!("{}", self.cpu_clk_en().bit()))
-            .field("sys_clk_en", &format_args!("{}", self.sys_clk_en().bit()))
+            .field("cpu_clk_en", &self.cpu_clk_en())
+            .field("sys_clk_en", &self.sys_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ROOT_CLK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - clock gate enable for hp cpu root 400M clk"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/idbus_addrhole_addr.rs b/esp32p4/src/lp_sys/idbus_addrhole_addr.rs
index 1e3e74cdb3..7164db88a2 100644
--- a/esp32p4/src/lp_sys/idbus_addrhole_addr.rs
+++ b/esp32p4/src/lp_sys/idbus_addrhole_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDBUS_ADDRHOLE_ADDR")
-            .field(
-                "idbus_addrhole_addr",
-                &format_args!("{}", self.idbus_addrhole_addr().bits()),
-            )
+            .field("idbus_addrhole_addr", &self.idbus_addrhole_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDBUS_ADDRHOLE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idbus_addrhole_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IDBUS_ADDRHOLE_ADDR_SPEC;
 impl crate::RegisterSpec for IDBUS_ADDRHOLE_ADDR_SPEC {
diff --git a/esp32p4/src/lp_sys/idbus_addrhole_info.rs b/esp32p4/src/lp_sys/idbus_addrhole_info.rs
index d3f91f626d..632a86c9c4 100644
--- a/esp32p4/src/lp_sys/idbus_addrhole_info.rs
+++ b/esp32p4/src/lp_sys/idbus_addrhole_info.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDBUS_ADDRHOLE_INFO")
-            .field(
-                "idbus_addrhole_id",
-                &format_args!("{}", self.idbus_addrhole_id().bits()),
-            )
-            .field(
-                "idbus_addrhole_wr",
-                &format_args!("{}", self.idbus_addrhole_wr().bit()),
-            )
-            .field(
-                "idbus_addrhole_secure",
-                &format_args!("{}", self.idbus_addrhole_secure().bit()),
-            )
+            .field("idbus_addrhole_id", &self.idbus_addrhole_id())
+            .field("idbus_addrhole_wr", &self.idbus_addrhole_wr())
+            .field("idbus_addrhole_secure", &self.idbus_addrhole_secure())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDBUS_ADDRHOLE_INFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idbus_addrhole_info::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IDBUS_ADDRHOLE_INFO_SPEC;
 impl crate::RegisterSpec for IDBUS_ADDRHOLE_INFO_SPEC {
diff --git a/esp32p4/src/lp_sys/int_ena.rs b/esp32p4/src/lp_sys/int_ena.rs
index 28bcb888d5..a936a0e880 100644
--- a/esp32p4/src/lp_sys/int_ena.rs
+++ b/esp32p4/src/lp_sys/int_ena.rs
@@ -71,43 +71,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "lp_addrhole_int_ena",
-                &format_args!("{}", self.lp_addrhole_int_ena().bit()),
-            )
-            .field(
-                "idbus_addrhole_int_ena",
-                &format_args!("{}", self.idbus_addrhole_int_ena().bit()),
-            )
+            .field("lp_addrhole_int_ena", &self.lp_addrhole_int_ena())
+            .field("idbus_addrhole_int_ena", &self.idbus_addrhole_int_ena())
             .field(
                 "lp_core_ahb_timeout_int_ena",
-                &format_args!("{}", self.lp_core_ahb_timeout_int_ena().bit()),
+                &self.lp_core_ahb_timeout_int_ena(),
             )
             .field(
                 "lp_core_ibus_timeout_int_ena",
-                &format_args!("{}", self.lp_core_ibus_timeout_int_ena().bit()),
+                &self.lp_core_ibus_timeout_int_ena(),
             )
             .field(
                 "lp_core_dbus_timeout_int_ena",
-                &format_args!("{}", self.lp_core_dbus_timeout_int_ena().bit()),
-            )
-            .field(
-                "etm_task_ulp_int_ena",
-                &format_args!("{}", self.etm_task_ulp_int_ena().bit()),
-            )
-            .field(
-                "slow_clk_tick_int_ena",
-                &format_args!("{}", self.slow_clk_tick_int_ena().bit()),
+                &self.lp_core_dbus_timeout_int_ena(),
             )
+            .field("etm_task_ulp_int_ena", &self.etm_task_ulp_int_ena())
+            .field("slow_clk_tick_int_ena", &self.slow_clk_tick_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to enable lp addrhole int"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/int_raw.rs b/esp32p4/src/lp_sys/int_raw.rs
index a4f92a696d..c12096682d 100644
--- a/esp32p4/src/lp_sys/int_raw.rs
+++ b/esp32p4/src/lp_sys/int_raw.rs
@@ -55,43 +55,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "lp_addrhole_int_raw",
-                &format_args!("{}", self.lp_addrhole_int_raw().bit()),
-            )
-            .field(
-                "idbus_addrhole_int_raw",
-                &format_args!("{}", self.idbus_addrhole_int_raw().bit()),
-            )
+            .field("lp_addrhole_int_raw", &self.lp_addrhole_int_raw())
+            .field("idbus_addrhole_int_raw", &self.idbus_addrhole_int_raw())
             .field(
                 "lp_core_ahb_timeout_int_raw",
-                &format_args!("{}", self.lp_core_ahb_timeout_int_raw().bit()),
+                &self.lp_core_ahb_timeout_int_raw(),
             )
             .field(
                 "lp_core_ibus_timeout_int_raw",
-                &format_args!("{}", self.lp_core_ibus_timeout_int_raw().bit()),
+                &self.lp_core_ibus_timeout_int_raw(),
             )
             .field(
                 "lp_core_dbus_timeout_int_raw",
-                &format_args!("{}", self.lp_core_dbus_timeout_int_raw().bit()),
-            )
-            .field(
-                "etm_task_ulp_int_raw",
-                &format_args!("{}", self.etm_task_ulp_int_raw().bit()),
-            )
-            .field(
-                "slow_clk_tick_int_raw",
-                &format_args!("{}", self.slow_clk_tick_int_raw().bit()),
+                &self.lp_core_dbus_timeout_int_raw(),
             )
+            .field("etm_task_ulp_int_raw", &self.etm_task_ulp_int_raw())
+            .field("slow_clk_tick_int_raw", &self.slow_clk_tick_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "raw interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32p4/src/lp_sys/int_st.rs b/esp32p4/src/lp_sys/int_st.rs
index 6dd7b65d9f..b35e2f4fe7 100644
--- a/esp32p4/src/lp_sys/int_st.rs
+++ b/esp32p4/src/lp_sys/int_st.rs
@@ -55,43 +55,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "lp_addrhole_int_st",
-                &format_args!("{}", self.lp_addrhole_int_st().bit()),
-            )
-            .field(
-                "idbus_addrhole_int_st",
-                &format_args!("{}", self.idbus_addrhole_int_st().bit()),
-            )
+            .field("lp_addrhole_int_st", &self.lp_addrhole_int_st())
+            .field("idbus_addrhole_int_st", &self.idbus_addrhole_int_st())
             .field(
                 "lp_core_ahb_timeout_int_st",
-                &format_args!("{}", self.lp_core_ahb_timeout_int_st().bit()),
+                &self.lp_core_ahb_timeout_int_st(),
             )
             .field(
                 "lp_core_ibus_timeout_int_st",
-                &format_args!("{}", self.lp_core_ibus_timeout_int_st().bit()),
+                &self.lp_core_ibus_timeout_int_st(),
             )
             .field(
                 "lp_core_dbus_timeout_int_st",
-                &format_args!("{}", self.lp_core_dbus_timeout_int_st().bit()),
-            )
-            .field(
-                "etm_task_ulp_int_st",
-                &format_args!("{}", self.etm_task_ulp_int_st().bit()),
-            )
-            .field(
-                "slow_clk_tick_int_st",
-                &format_args!("{}", self.slow_clk_tick_int_st().bit()),
+                &self.lp_core_dbus_timeout_int_st(),
             )
+            .field("etm_task_ulp_int_st", &self.etm_task_ulp_int_st())
+            .field("slow_clk_tick_int_st", &self.slow_clk_tick_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/lp_sys/lp_addrhole_addr.rs b/esp32p4/src/lp_sys/lp_addrhole_addr.rs
index fb345d6d49..2b9b9545d1 100644
--- a/esp32p4/src/lp_sys/lp_addrhole_addr.rs
+++ b/esp32p4/src/lp_sys/lp_addrhole_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_ADDRHOLE_ADDR")
-            .field(
-                "lp_addrhole_addr",
-                &format_args!("{}", self.lp_addrhole_addr().bits()),
-            )
+            .field("lp_addrhole_addr", &self.lp_addrhole_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_ADDRHOLE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_addrhole_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_ADDRHOLE_ADDR_SPEC;
 impl crate::RegisterSpec for LP_ADDRHOLE_ADDR_SPEC {
diff --git a/esp32p4/src/lp_sys/lp_addrhole_info.rs b/esp32p4/src/lp_sys/lp_addrhole_info.rs
index a0df81292e..2ad18d71d4 100644
--- a/esp32p4/src/lp_sys/lp_addrhole_info.rs
+++ b/esp32p4/src/lp_sys/lp_addrhole_info.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_ADDRHOLE_INFO")
-            .field(
-                "lp_addrhole_id",
-                &format_args!("{}", self.lp_addrhole_id().bits()),
-            )
-            .field(
-                "lp_addrhole_wr",
-                &format_args!("{}", self.lp_addrhole_wr().bit()),
-            )
-            .field(
-                "lp_addrhole_secure",
-                &format_args!("{}", self.lp_addrhole_secure().bit()),
-            )
+            .field("lp_addrhole_id", &self.lp_addrhole_id())
+            .field("lp_addrhole_wr", &self.lp_addrhole_wr())
+            .field("lp_addrhole_secure", &self.lp_addrhole_secure())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_ADDRHOLE_INFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_addrhole_info::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_ADDRHOLE_INFO_SPEC;
 impl crate::RegisterSpec for LP_ADDRHOLE_INFO_SPEC {
diff --git a/esp32p4/src/lp_sys/lp_clk_ctrl.rs b/esp32p4/src/lp_sys/lp_clk_ctrl.rs
index 708d23cd10..3c5461bf61 100644
--- a/esp32p4/src/lp_sys/lp_clk_ctrl.rs
+++ b/esp32p4/src/lp_sys/lp_clk_ctrl.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CLK_CTRL")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "lp_fosc_hp_cken",
-                &format_args!("{}", self.lp_fosc_hp_cken().bit()),
-            )
+            .field("clk_en", &self.clk_en())
+            .field("lp_fosc_hp_cken", &self.lp_fosc_hp_cken())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CLK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_core_ahb_timeout.rs b/esp32p4/src/lp_sys/lp_core_ahb_timeout.rs
index 96fd776c0d..dc59586fe6 100644
--- a/esp32p4/src/lp_sys/lp_core_ahb_timeout.rs
+++ b/esp32p4/src/lp_sys/lp_core_ahb_timeout.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CORE_AHB_TIMEOUT")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("thres", &format_args!("{}", self.thres().bits()))
-            .field(
-                "lp2hp_ahb_timeout_en",
-                &format_args!("{}", self.lp2hp_ahb_timeout_en().bit()),
-            )
-            .field(
-                "lp2hp_ahb_timeout_thres",
-                &format_args!("{}", self.lp2hp_ahb_timeout_thres().bits()),
-            )
+            .field("en", &self.en())
+            .field("thres", &self.thres())
+            .field("lp2hp_ahb_timeout_en", &self.lp2hp_ahb_timeout_en())
+            .field("lp2hp_ahb_timeout_thres", &self.lp2hp_ahb_timeout_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CORE_AHB_TIMEOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this field to 1 to enable lp core ahb timeout handle"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_core_boot_addr.rs b/esp32p4/src/lp_sys/lp_core_boot_addr.rs
index f04de37fbd..e5146abf06 100644
--- a/esp32p4/src/lp_sys/lp_core_boot_addr.rs
+++ b/esp32p4/src/lp_sys/lp_core_boot_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CORE_BOOT_ADDR")
-            .field(
-                "lp_cpu_boot_addr",
-                &format_args!("{}", self.lp_cpu_boot_addr().bits()),
-            )
+            .field("lp_cpu_boot_addr", &self.lp_cpu_boot_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CORE_BOOT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_core_dbus_timeout.rs b/esp32p4/src/lp_sys/lp_core_dbus_timeout.rs
index 9bf71c5560..150098ea48 100644
--- a/esp32p4/src/lp_sys/lp_core_dbus_timeout.rs
+++ b/esp32p4/src/lp_sys/lp_core_dbus_timeout.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CORE_DBUS_TIMEOUT")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("thres", &format_args!("{}", self.thres().bits()))
+            .field("en", &self.en())
+            .field("thres", &self.thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CORE_DBUS_TIMEOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this field to 1 to enable lp core dbus timeout handle"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_core_err_resp_dis.rs b/esp32p4/src/lp_sys/lp_core_err_resp_dis.rs
index a1f25dee0e..1f04a9e30e 100644
--- a/esp32p4/src/lp_sys/lp_core_err_resp_dis.rs
+++ b/esp32p4/src/lp_sys/lp_core_err_resp_dis.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CORE_ERR_RESP_DIS")
-            .field(
-                "lp_core_err_resp_dis",
-                &format_args!("{}", self.lp_core_err_resp_dis().bits()),
-            )
+            .field("lp_core_err_resp_dis", &self.lp_core_err_resp_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CORE_ERR_RESP_DIS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to disable ahb err resp."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_core_ibus_timeout.rs b/esp32p4/src/lp_sys/lp_core_ibus_timeout.rs
index 6669894c0c..187d47093f 100644
--- a/esp32p4/src/lp_sys/lp_core_ibus_timeout.rs
+++ b/esp32p4/src/lp_sys/lp_core_ibus_timeout.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CORE_IBUS_TIMEOUT")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("thres", &format_args!("{}", self.thres().bits()))
+            .field("en", &self.en())
+            .field("thres", &self.thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CORE_IBUS_TIMEOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this field to 1 to enable lp core ibus timeout handle"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_cpu_dbg_pc.rs b/esp32p4/src/lp_sys/lp_cpu_dbg_pc.rs
index 204f7d3b74..9938ac7487 100644
--- a/esp32p4/src/lp_sys/lp_cpu_dbg_pc.rs
+++ b/esp32p4/src/lp_sys/lp_cpu_dbg_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CPU_DBG_PC")
-            .field(
-                "lp_cpu_dbg_pc",
-                &format_args!("{}", self.lp_cpu_dbg_pc().bits()),
-            )
+            .field("lp_cpu_dbg_pc", &self.lp_cpu_dbg_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CPU_DBG_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_dbg_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_CPU_DBG_PC_SPEC;
 impl crate::RegisterSpec for LP_CPU_DBG_PC_SPEC {
diff --git a/esp32p4/src/lp_sys/lp_cpu_exc_pc.rs b/esp32p4/src/lp_sys/lp_cpu_exc_pc.rs
index 94a09d4e28..aeacac4517 100644
--- a/esp32p4/src/lp_sys/lp_cpu_exc_pc.rs
+++ b/esp32p4/src/lp_sys/lp_cpu_exc_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CPU_EXC_PC")
-            .field(
-                "lp_cpu_exc_pc",
-                &format_args!("{}", self.lp_cpu_exc_pc().bits()),
-            )
+            .field("lp_cpu_exc_pc", &self.lp_cpu_exc_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CPU_EXC_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_exc_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_CPU_EXC_PC_SPEC;
 impl crate::RegisterSpec for LP_CPU_EXC_PC_SPEC {
diff --git a/esp32p4/src/lp_sys/lp_mem_aux_ctrl.rs b/esp32p4/src/lp_sys/lp_mem_aux_ctrl.rs
index 6f07479f4f..82ff62c1d0 100644
--- a/esp32p4/src/lp_sys/lp_mem_aux_ctrl.rs
+++ b/esp32p4/src/lp_sys/lp_mem_aux_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_MEM_AUX_CTRL")
-            .field(
-                "lp_mem_aux_ctrl",
-                &format_args!("{}", self.lp_mem_aux_ctrl().bits()),
-            )
+            .field("lp_mem_aux_ctrl", &self.lp_mem_aux_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_MEM_AUX_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_pmu_rdn_eco_high.rs b/esp32p4/src/lp_sys/lp_pmu_rdn_eco_high.rs
index 9bf0921bc2..3624820ac5 100644
--- a/esp32p4/src/lp_sys/lp_pmu_rdn_eco_high.rs
+++ b/esp32p4/src/lp_sys/lp_pmu_rdn_eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_PMU_RDN_ECO_HIGH")
-            .field(
-                "pmu_rdn_eco_high",
-                &format_args!("{}", self.pmu_rdn_eco_high().bits()),
-            )
+            .field("pmu_rdn_eco_high", &self.pmu_rdn_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_PMU_RDN_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_pmu_rdn_eco_low.rs b/esp32p4/src/lp_sys/lp_pmu_rdn_eco_low.rs
index e839796994..bd07616421 100644
--- a/esp32p4/src/lp_sys/lp_pmu_rdn_eco_low.rs
+++ b/esp32p4/src/lp_sys/lp_pmu_rdn_eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_PMU_RDN_ECO_LOW")
-            .field(
-                "pmu_rdn_eco_low",
-                &format_args!("{}", self.pmu_rdn_eco_low().bits()),
-            )
+            .field("pmu_rdn_eco_low", &self.pmu_rdn_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_PMU_RDN_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_probe_out.rs b/esp32p4/src/lp_sys/lp_probe_out.rs
index 363b53c3b2..8ac0bc3e55 100644
--- a/esp32p4/src/lp_sys/lp_probe_out.rs
+++ b/esp32p4/src/lp_sys/lp_probe_out.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_PROBE_OUT")
-            .field(
-                "probe_top_out",
-                &format_args!("{}", self.probe_top_out().bits()),
-            )
+            .field("probe_top_out", &self.probe_top_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_PROBE_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_probe_out::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_PROBE_OUT_SPEC;
 impl crate::RegisterSpec for LP_PROBE_OUT_SPEC {
diff --git a/esp32p4/src/lp_sys/lp_probea_ctrl.rs b/esp32p4/src/lp_sys/lp_probea_ctrl.rs
index 2b94949803..75865ca0b4 100644
--- a/esp32p4/src/lp_sys/lp_probea_ctrl.rs
+++ b/esp32p4/src/lp_sys/lp_probea_ctrl.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_PROBEA_CTRL")
-            .field(
-                "probe_a_mod_sel",
-                &format_args!("{}", self.probe_a_mod_sel().bits()),
-            )
-            .field(
-                "probe_a_top_sel",
-                &format_args!("{}", self.probe_a_top_sel().bits()),
-            )
-            .field(
-                "probe_l_sel",
-                &format_args!("{}", self.probe_l_sel().bits()),
-            )
-            .field(
-                "probe_h_sel",
-                &format_args!("{}", self.probe_h_sel().bits()),
-            )
-            .field(
-                "probe_global_en",
-                &format_args!("{}", self.probe_global_en().bit()),
-            )
+            .field("probe_a_mod_sel", &self.probe_a_mod_sel())
+            .field("probe_a_top_sel", &self.probe_a_top_sel())
+            .field("probe_l_sel", &self.probe_l_sel())
+            .field("probe_h_sel", &self.probe_h_sel())
+            .field("probe_global_en", &self.probe_global_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_PROBEA_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_probeb_ctrl.rs b/esp32p4/src/lp_sys/lp_probeb_ctrl.rs
index 32c72b703e..7009a77694 100644
--- a/esp32p4/src/lp_sys/lp_probeb_ctrl.rs
+++ b/esp32p4/src/lp_sys/lp_probeb_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_PROBEB_CTRL")
-            .field(
-                "probe_b_mod_sel",
-                &format_args!("{}", self.probe_b_mod_sel().bits()),
-            )
-            .field(
-                "probe_b_top_sel",
-                &format_args!("{}", self.probe_b_top_sel().bits()),
-            )
-            .field("probe_b_en", &format_args!("{}", self.probe_b_en().bit()))
+            .field("probe_b_mod_sel", &self.probe_b_mod_sel())
+            .field("probe_b_top_sel", &self.probe_b_top_sel())
+            .field("probe_b_en", &self.probe_b_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_PROBEB_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_rom_aux_ctrl.rs b/esp32p4/src/lp_sys/lp_rom_aux_ctrl.rs
index 715860b163..cac3907909 100644
--- a/esp32p4/src/lp_sys/lp_rom_aux_ctrl.rs
+++ b/esp32p4/src/lp_sys/lp_rom_aux_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_ROM_AUX_CTRL")
-            .field(
-                "lp_rom_aux_ctrl",
-                &format_args!("{}", self.lp_rom_aux_ctrl().bits()),
-            )
+            .field("lp_rom_aux_ctrl", &self.lp_rom_aux_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_ROM_AUX_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_rst_ctrl.rs b/esp32p4/src/lp_sys/lp_rst_ctrl.rs
index a4e58dc49f..bf0b26112b 100644
--- a/esp32p4/src/lp_sys/lp_rst_ctrl.rs
+++ b/esp32p4/src/lp_sys/lp_rst_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_RST_CTRL")
-            .field(
-                "ana_rst_bypass",
-                &format_args!("{}", self.ana_rst_bypass().bit()),
-            )
-            .field(
-                "sys_rst_bypass",
-                &format_args!("{}", self.sys_rst_bypass().bit()),
-            )
-            .field(
-                "efuse_force_norst",
-                &format_args!("{}", self.efuse_force_norst().bit()),
-            )
+            .field("ana_rst_bypass", &self.ana_rst_bypass())
+            .field("sys_rst_bypass", &self.sys_rst_bypass())
+            .field("efuse_force_norst", &self.efuse_force_norst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_RST_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - analog source reset bypass : wdt,brown out,super wdt,glitch"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store0.rs b/esp32p4/src/lp_sys/lp_store0.rs
index ff1b2dfceb..e55dbf8ad6 100644
--- a/esp32p4/src/lp_sys/lp_store0.rs
+++ b/esp32p4/src/lp_sys/lp_store0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE0")
-            .field(
-                "lp_scratch0",
-                &format_args!("{}", self.lp_scratch0().bits()),
-            )
+            .field("lp_scratch0", &self.lp_scratch0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store1.rs b/esp32p4/src/lp_sys/lp_store1.rs
index 7ea6a4253a..f8029c285b 100644
--- a/esp32p4/src/lp_sys/lp_store1.rs
+++ b/esp32p4/src/lp_sys/lp_store1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE1")
-            .field(
-                "lp_scratch1",
-                &format_args!("{}", self.lp_scratch1().bits()),
-            )
+            .field("lp_scratch1", &self.lp_scratch1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store10.rs b/esp32p4/src/lp_sys/lp_store10.rs
index c367652d2f..6dac8e5ef1 100644
--- a/esp32p4/src/lp_sys/lp_store10.rs
+++ b/esp32p4/src/lp_sys/lp_store10.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE10")
-            .field(
-                "lp_scratch10",
-                &format_args!("{}", self.lp_scratch10().bits()),
-            )
+            .field("lp_scratch10", &self.lp_scratch10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store11.rs b/esp32p4/src/lp_sys/lp_store11.rs
index 444cd959be..aaa39c9ffa 100644
--- a/esp32p4/src/lp_sys/lp_store11.rs
+++ b/esp32p4/src/lp_sys/lp_store11.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE11")
-            .field(
-                "lp_scratch11",
-                &format_args!("{}", self.lp_scratch11().bits()),
-            )
+            .field("lp_scratch11", &self.lp_scratch11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store12.rs b/esp32p4/src/lp_sys/lp_store12.rs
index 4e00e3f417..9741f4f1aa 100644
--- a/esp32p4/src/lp_sys/lp_store12.rs
+++ b/esp32p4/src/lp_sys/lp_store12.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE12")
-            .field(
-                "lp_scratch12",
-                &format_args!("{}", self.lp_scratch12().bits()),
-            )
+            .field("lp_scratch12", &self.lp_scratch12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store13.rs b/esp32p4/src/lp_sys/lp_store13.rs
index f59e19477b..0d46080b75 100644
--- a/esp32p4/src/lp_sys/lp_store13.rs
+++ b/esp32p4/src/lp_sys/lp_store13.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE13")
-            .field(
-                "lp_scratch13",
-                &format_args!("{}", self.lp_scratch13().bits()),
-            )
+            .field("lp_scratch13", &self.lp_scratch13())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store14.rs b/esp32p4/src/lp_sys/lp_store14.rs
index 808817b01e..ad79929a02 100644
--- a/esp32p4/src/lp_sys/lp_store14.rs
+++ b/esp32p4/src/lp_sys/lp_store14.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE14")
-            .field(
-                "lp_scratch14",
-                &format_args!("{}", self.lp_scratch14().bits()),
-            )
+            .field("lp_scratch14", &self.lp_scratch14())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store15.rs b/esp32p4/src/lp_sys/lp_store15.rs
index a0e8414969..05310dfc6f 100644
--- a/esp32p4/src/lp_sys/lp_store15.rs
+++ b/esp32p4/src/lp_sys/lp_store15.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE15")
-            .field(
-                "lp_scratch15",
-                &format_args!("{}", self.lp_scratch15().bits()),
-            )
+            .field("lp_scratch15", &self.lp_scratch15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store2.rs b/esp32p4/src/lp_sys/lp_store2.rs
index be9a7aafb6..f71ad955a7 100644
--- a/esp32p4/src/lp_sys/lp_store2.rs
+++ b/esp32p4/src/lp_sys/lp_store2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE2")
-            .field(
-                "lp_scratch2",
-                &format_args!("{}", self.lp_scratch2().bits()),
-            )
+            .field("lp_scratch2", &self.lp_scratch2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store3.rs b/esp32p4/src/lp_sys/lp_store3.rs
index fa1711677b..ecf6833d59 100644
--- a/esp32p4/src/lp_sys/lp_store3.rs
+++ b/esp32p4/src/lp_sys/lp_store3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE3")
-            .field(
-                "lp_scratch3",
-                &format_args!("{}", self.lp_scratch3().bits()),
-            )
+            .field("lp_scratch3", &self.lp_scratch3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store4.rs b/esp32p4/src/lp_sys/lp_store4.rs
index e77c0c4c5c..8e0debffd3 100644
--- a/esp32p4/src/lp_sys/lp_store4.rs
+++ b/esp32p4/src/lp_sys/lp_store4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE4")
-            .field(
-                "lp_scratch4",
-                &format_args!("{}", self.lp_scratch4().bits()),
-            )
+            .field("lp_scratch4", &self.lp_scratch4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store5.rs b/esp32p4/src/lp_sys/lp_store5.rs
index bc64112947..844bbea641 100644
--- a/esp32p4/src/lp_sys/lp_store5.rs
+++ b/esp32p4/src/lp_sys/lp_store5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE5")
-            .field(
-                "lp_scratch5",
-                &format_args!("{}", self.lp_scratch5().bits()),
-            )
+            .field("lp_scratch5", &self.lp_scratch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store6.rs b/esp32p4/src/lp_sys/lp_store6.rs
index 9bd08ee6b0..c0d6766e19 100644
--- a/esp32p4/src/lp_sys/lp_store6.rs
+++ b/esp32p4/src/lp_sys/lp_store6.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE6")
-            .field(
-                "lp_scratch6",
-                &format_args!("{}", self.lp_scratch6().bits()),
-            )
+            .field("lp_scratch6", &self.lp_scratch6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store7.rs b/esp32p4/src/lp_sys/lp_store7.rs
index 4a31baf813..e4f162288d 100644
--- a/esp32p4/src/lp_sys/lp_store7.rs
+++ b/esp32p4/src/lp_sys/lp_store7.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE7")
-            .field(
-                "lp_scratch7",
-                &format_args!("{}", self.lp_scratch7().bits()),
-            )
+            .field("lp_scratch7", &self.lp_scratch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store8.rs b/esp32p4/src/lp_sys/lp_store8.rs
index b29bebd39c..9ef49147d5 100644
--- a/esp32p4/src/lp_sys/lp_store8.rs
+++ b/esp32p4/src/lp_sys/lp_store8.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE8")
-            .field(
-                "lp_scratch8",
-                &format_args!("{}", self.lp_scratch8().bits()),
-            )
+            .field("lp_scratch8", &self.lp_scratch8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_store9.rs b/esp32p4/src/lp_sys/lp_store9.rs
index e2ef5cd235..462033d7ff 100644
--- a/esp32p4/src/lp_sys/lp_store9.rs
+++ b/esp32p4/src/lp_sys/lp_store9.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_STORE9")
-            .field(
-                "lp_scratch9",
-                &format_args!("{}", self.lp_scratch9().bits()),
-            )
+            .field("lp_scratch9", &self.lp_scratch9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_STORE9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_sys_ver_date.rs b/esp32p4/src/lp_sys/lp_sys_ver_date.rs
index 162409e83a..aac943ebf7 100644
--- a/esp32p4/src/lp_sys/lp_sys_ver_date.rs
+++ b/esp32p4/src/lp_sys/lp_sys_ver_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SYS_VER_DATE")
-            .field("ver_date", &format_args!("{}", self.ver_date().bits()))
+            .field("ver_date", &self.ver_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SYS_VER_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_tcm_pwr_ctrl.rs b/esp32p4/src/lp_sys/lp_tcm_pwr_ctrl.rs
index d07404c976..63e4d54508 100644
--- a/esp32p4/src/lp_sys/lp_tcm_pwr_ctrl.rs
+++ b/esp32p4/src/lp_sys/lp_tcm_pwr_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_TCM_PWR_CTRL")
-            .field(
-                "lp_tcm_rom_clk_force_on",
-                &format_args!("{}", self.lp_tcm_rom_clk_force_on().bit()),
-            )
-            .field(
-                "lp_tcm_ram_clk_force_on",
-                &format_args!("{}", self.lp_tcm_ram_clk_force_on().bit()),
-            )
+            .field("lp_tcm_rom_clk_force_on", &self.lp_tcm_rom_clk_force_on())
+            .field("lp_tcm_ram_clk_force_on", &self.lp_tcm_ram_clk_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TCM_PWR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 5 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_cs.rs b/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_cs.rs
index ec6c08aa8e..689f919ec6 100644
--- a/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_cs.rs
+++ b/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_cs.rs
@@ -24,23 +24,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_TCM_RAM_RDN_ECO_CS")
-            .field(
-                "lp_tcm_ram_rdn_eco_en",
-                &format_args!("{}", self.lp_tcm_ram_rdn_eco_en().bit()),
-            )
+            .field("lp_tcm_ram_rdn_eco_en", &self.lp_tcm_ram_rdn_eco_en())
             .field(
                 "lp_tcm_ram_rdn_eco_result",
-                &format_args!("{}", self.lp_tcm_ram_rdn_eco_result().bit()),
+                &self.lp_tcm_ram_rdn_eco_result(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TCM_RAM_RDN_ECO_CS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_high.rs b/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_high.rs
index babe5787cd..052a6355fd 100644
--- a/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_high.rs
+++ b/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_TCM_RAM_RDN_ECO_HIGH")
-            .field(
-                "lp_tcm_ram_rdn_eco_high",
-                &format_args!("{}", self.lp_tcm_ram_rdn_eco_high().bits()),
-            )
+            .field("lp_tcm_ram_rdn_eco_high", &self.lp_tcm_ram_rdn_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TCM_RAM_RDN_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_low.rs b/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_low.rs
index 21f726ef35..0c32f77b7e 100644
--- a/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_low.rs
+++ b/esp32p4/src/lp_sys/lp_tcm_ram_rdn_eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_TCM_RAM_RDN_ECO_LOW")
-            .field(
-                "lp_tcm_ram_rdn_eco_low",
-                &format_args!("{}", self.lp_tcm_ram_rdn_eco_low().bits()),
-            )
+            .field("lp_tcm_ram_rdn_eco_low", &self.lp_tcm_ram_rdn_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TCM_RAM_RDN_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_cs.rs b/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_cs.rs
index d3c99ac451..6759a2f900 100644
--- a/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_cs.rs
+++ b/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_cs.rs
@@ -24,23 +24,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_TCM_ROM_RDN_ECO_CS")
-            .field(
-                "lp_tcm_rom_rdn_eco_en",
-                &format_args!("{}", self.lp_tcm_rom_rdn_eco_en().bit()),
-            )
+            .field("lp_tcm_rom_rdn_eco_en", &self.lp_tcm_rom_rdn_eco_en())
             .field(
                 "lp_tcm_rom_rdn_eco_result",
-                &format_args!("{}", self.lp_tcm_rom_rdn_eco_result().bit()),
+                &self.lp_tcm_rom_rdn_eco_result(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TCM_ROM_RDN_ECO_CS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_high.rs b/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_high.rs
index da6889c9d7..24e02dc572 100644
--- a/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_high.rs
+++ b/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_TCM_ROM_RDN_ECO_HIGH")
-            .field(
-                "lp_tcm_rom_rdn_eco_high",
-                &format_args!("{}", self.lp_tcm_rom_rdn_eco_high().bits()),
-            )
+            .field("lp_tcm_rom_rdn_eco_high", &self.lp_tcm_rom_rdn_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TCM_ROM_RDN_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_low.rs b/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_low.rs
index 1afab54ab0..f370cc0daa 100644
--- a/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_low.rs
+++ b/esp32p4/src/lp_sys/lp_tcm_rom_rdn_eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_TCM_ROM_RDN_ECO_LOW")
-            .field(
-                "lp_tcm_rom_rdn_eco_low",
-                &format_args!("{}", self.lp_tcm_rom_rdn_eco_low().bits()),
-            )
+            .field("lp_tcm_rom_rdn_eco_low", &self.lp_tcm_rom_rdn_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_TCM_ROM_RDN_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/pad_comp0.rs b/esp32p4/src/lp_sys/pad_comp0.rs
index b48b901ae6..0c54e17a8f 100644
--- a/esp32p4/src/lp_sys/pad_comp0.rs
+++ b/esp32p4/src/lp_sys/pad_comp0.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_COMP0")
-            .field("dref_comp0", &format_args!("{}", self.dref_comp0().bits()))
-            .field("mode_comp0", &format_args!("{}", self.mode_comp0().bit()))
-            .field("xpd_comp0", &format_args!("{}", self.xpd_comp0().bit()))
+            .field("dref_comp0", &self.dref_comp0())
+            .field("mode_comp0", &self.mode_comp0())
+            .field("xpd_comp0", &self.xpd_comp0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_COMP0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - pad comp dref"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/pad_comp1.rs b/esp32p4/src/lp_sys/pad_comp1.rs
index ac6d1237d9..46635fe178 100644
--- a/esp32p4/src/lp_sys/pad_comp1.rs
+++ b/esp32p4/src/lp_sys/pad_comp1.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_COMP1")
-            .field("dref_comp1", &format_args!("{}", self.dref_comp1().bits()))
-            .field("mode_comp1", &format_args!("{}", self.mode_comp1().bit()))
-            .field("xpd_comp1", &format_args!("{}", self.xpd_comp1().bit()))
+            .field("dref_comp1", &self.dref_comp1())
+            .field("mode_comp1", &self.mode_comp1())
+            .field("xpd_comp1", &self.xpd_comp1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_COMP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - pad comp dref"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/rng_cfg.rs b/esp32p4/src/lp_sys/rng_cfg.rs
index da8b74b96c..28399c3ee8 100644
--- a/esp32p4/src/lp_sys/rng_cfg.rs
+++ b/esp32p4/src/lp_sys/rng_cfg.rs
@@ -42,31 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RNG_CFG")
-            .field(
-                "rng_timer_en",
-                &format_args!("{}", self.rng_timer_en().bit()),
-            )
-            .field(
-                "rng_timer_pscale",
-                &format_args!("{}", self.rng_timer_pscale().bits()),
-            )
-            .field(
-                "rng_sar_enable",
-                &format_args!("{}", self.rng_sar_enable().bit()),
-            )
-            .field(
-                "rng_sar_data",
-                &format_args!("{}", self.rng_sar_data().bits()),
-            )
+            .field("rng_timer_en", &self.rng_timer_en())
+            .field("rng_timer_pscale", &self.rng_timer_pscale())
+            .field("rng_sar_enable", &self.rng_sar_enable())
+            .field("rng_sar_data", &self.rng_sar_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RNG_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable rng timer"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/rng_data.rs b/esp32p4/src/lp_sys/rng_data.rs
index a0f3e3b9cf..9c66e4c17a 100644
--- a/esp32p4/src/lp_sys/rng_data.rs
+++ b/esp32p4/src/lp_sys/rng_data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RNG_DATA")
-            .field("rnd_data", &format_args!("{}", self.rnd_data().bits()))
+            .field("rnd_data", &self.rnd_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RNG_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rng data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RNG_DATA_SPEC;
 impl crate::RegisterSpec for RNG_DATA_SPEC {
diff --git a/esp32p4/src/lp_sys/sys_ctrl.rs b/esp32p4/src/lp_sys/sys_ctrl.rs
index f56553ffc1..7fec1261f9 100644
--- a/esp32p4/src/lp_sys/sys_ctrl.rs
+++ b/esp32p4/src/lp_sys/sys_ctrl.rs
@@ -82,38 +82,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYS_CTRL")
-            .field(
-                "lp_core_disable",
-                &format_args!("{}", self.lp_core_disable().bit()),
-            )
-            .field(
-                "force_download_boot",
-                &format_args!("{}", self.force_download_boot().bit()),
-            )
-            .field("dig_fib", &format_args!("{}", self.dig_fib().bits()))
-            .field(
-                "io_mux_reset_disable",
-                &format_args!("{}", self.io_mux_reset_disable().bit()),
-            )
-            .field("ana_fib", &format_args!("{}", self.ana_fib().bits()))
-            .field("lp_fib_sel", &format_args!("{}", self.lp_fib_sel().bits()))
-            .field(
-                "lp_core_etm_wakeup_flag",
-                &format_args!("{}", self.lp_core_etm_wakeup_flag().bit()),
-            )
-            .field(
-                "systimer_stall_sel",
-                &format_args!("{}", self.systimer_stall_sel().bit()),
-            )
+            .field("lp_core_disable", &self.lp_core_disable())
+            .field("force_download_boot", &self.force_download_boot())
+            .field("dig_fib", &self.dig_fib())
+            .field("io_mux_reset_disable", &self.io_mux_reset_disable())
+            .field("ana_fib", &self.ana_fib())
+            .field("lp_fib_sel", &self.lp_fib_sel())
+            .field("lp_core_etm_wakeup_flag", &self.lp_core_etm_wakeup_flag())
+            .field("systimer_stall_sel", &self.systimer_stall_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - lp cpu disable"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_sys/usb_ctrl.rs b/esp32p4/src/lp_sys/usb_ctrl.rs
index 2c4ee25cbd..cf696e5fe2 100644
--- a/esp32p4/src/lp_sys/usb_ctrl.rs
+++ b/esp32p4/src/lp_sys/usb_ctrl.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_CTRL")
-            .field(
-                "sw_hw_usb_phy_sel",
-                &format_args!("{}", self.sw_hw_usb_phy_sel().bit()),
-            )
-            .field(
-                "sw_usb_phy_sel",
-                &format_args!("{}", self.sw_usb_phy_sel().bit()),
-            )
-            .field(
-                "usbotg20_in_suspend",
-                &format_args!("{}", self.usbotg20_in_suspend().bit()),
-            )
+            .field("sw_hw_usb_phy_sel", &self.sw_hw_usb_phy_sel())
+            .field("sw_usb_phy_sel", &self.sw_usb_phy_sel())
+            .field("usbotg20_in_suspend", &self.usbotg20_in_suspend())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_timer/date.rs b/esp32p4/src/lp_timer/date.rs
index d47a89ee4b..e9890af6e1 100644
--- a/esp32p4/src/lp_timer/date.rs
+++ b/esp32p4/src/lp_timer/date.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("date", &self.date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_timer/int_ena.rs b/esp32p4/src/lp_timer/int_ena.rs
index 92ce086df1..f27ed7c86e 100644
--- a/esp32p4/src/lp_timer/int_ena.rs
+++ b/esp32p4/src/lp_timer/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("overflow", &format_args!("{}", self.overflow().bit()))
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("overflow", &self.overflow())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_timer/int_raw.rs b/esp32p4/src/lp_timer/int_raw.rs
index a18d0a9b31..a5598fb406 100644
--- a/esp32p4/src/lp_timer/int_raw.rs
+++ b/esp32p4/src/lp_timer/int_raw.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("overflow", &format_args!("{}", self.overflow().bit()))
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("overflow", &self.overflow())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_timer/int_st.rs b/esp32p4/src/lp_timer/int_st.rs
index 101196ba9b..ee18087a3c 100644
--- a/esp32p4/src/lp_timer/int_st.rs
+++ b/esp32p4/src/lp_timer/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("overflow", &format_args!("{}", self.overflow().bit()))
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("overflow", &self.overflow())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/lp_timer/lp_int_ena.rs b/esp32p4/src/lp_timer/lp_int_ena.rs
index 5ea363c710..91e11e2772 100644
--- a/esp32p4/src/lp_timer/lp_int_ena.rs
+++ b/esp32p4/src/lp_timer/lp_int_ena.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ENA")
-            .field(
-                "main_timer_overflow",
-                &format_args!("{}", self.main_timer_overflow().bit()),
-            )
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
+            .field("main_timer_overflow", &self.main_timer_overflow())
+            .field("main_timer", &self.main_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_timer/lp_int_raw.rs b/esp32p4/src/lp_timer/lp_int_raw.rs
index 6df03d55aa..0c01b2cf70 100644
--- a/esp32p4/src/lp_timer/lp_int_raw.rs
+++ b/esp32p4/src/lp_timer/lp_int_raw.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_RAW")
-            .field(
-                "main_timer_overflow",
-                &format_args!("{}", self.main_timer_overflow().bit()),
-            )
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
+            .field("main_timer_overflow", &self.main_timer_overflow())
+            .field("main_timer", &self.main_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_timer/lp_int_st.rs b/esp32p4/src/lp_timer/lp_int_st.rs
index ca21a1cf4d..b109777cd5 100644
--- a/esp32p4/src/lp_timer/lp_int_st.rs
+++ b/esp32p4/src/lp_timer/lp_int_st.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ST")
-            .field(
-                "main_timer_overflow",
-                &format_args!("{}", self.main_timer_overflow().bit()),
-            )
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
+            .field("main_timer_overflow", &self.main_timer_overflow())
+            .field("main_timer", &self.main_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_INT_ST_SPEC;
 impl crate::RegisterSpec for LP_INT_ST_SPEC {
diff --git a/esp32p4/src/lp_timer/main_buf0_high.rs b/esp32p4/src/lp_timer/main_buf0_high.rs
index 7ec6b260aa..4545617b27 100644
--- a/esp32p4/src/lp_timer/main_buf0_high.rs
+++ b/esp32p4/src/lp_timer/main_buf0_high.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF0_HIGH")
-            .field(
-                "main_timer_buf0_high",
-                &format_args!("{}", self.main_timer_buf0_high().bits()),
-            )
+            .field("main_timer_buf0_high", &self.main_timer_buf0_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF0_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf0_high::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF0_HIGH_SPEC;
 impl crate::RegisterSpec for MAIN_BUF0_HIGH_SPEC {
diff --git a/esp32p4/src/lp_timer/main_buf0_low.rs b/esp32p4/src/lp_timer/main_buf0_low.rs
index b3e2efd010..9c176ef6e3 100644
--- a/esp32p4/src/lp_timer/main_buf0_low.rs
+++ b/esp32p4/src/lp_timer/main_buf0_low.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF0_LOW")
-            .field(
-                "main_timer_buf0_low",
-                &format_args!("{}", self.main_timer_buf0_low().bits()),
-            )
+            .field("main_timer_buf0_low", &self.main_timer_buf0_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF0_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf0_low::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF0_LOW_SPEC;
 impl crate::RegisterSpec for MAIN_BUF0_LOW_SPEC {
diff --git a/esp32p4/src/lp_timer/main_buf1_high.rs b/esp32p4/src/lp_timer/main_buf1_high.rs
index 343bec706f..3fd0b05256 100644
--- a/esp32p4/src/lp_timer/main_buf1_high.rs
+++ b/esp32p4/src/lp_timer/main_buf1_high.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF1_HIGH")
-            .field(
-                "main_timer_buf1_high",
-                &format_args!("{}", self.main_timer_buf1_high().bits()),
-            )
+            .field("main_timer_buf1_high", &self.main_timer_buf1_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF1_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf1_high::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF1_HIGH_SPEC;
 impl crate::RegisterSpec for MAIN_BUF1_HIGH_SPEC {
diff --git a/esp32p4/src/lp_timer/main_buf1_low.rs b/esp32p4/src/lp_timer/main_buf1_low.rs
index e9cb954df6..020cfc0659 100644
--- a/esp32p4/src/lp_timer/main_buf1_low.rs
+++ b/esp32p4/src/lp_timer/main_buf1_low.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_BUF1_LOW")
-            .field(
-                "main_timer_buf1_low",
-                &format_args!("{}", self.main_timer_buf1_low().bits()),
-            )
+            .field("main_timer_buf1_low", &self.main_timer_buf1_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_BUF1_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`main_buf1_low::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MAIN_BUF1_LOW_SPEC;
 impl crate::RegisterSpec for MAIN_BUF1_LOW_SPEC {
diff --git a/esp32p4/src/lp_timer/tar0_high.rs b/esp32p4/src/lp_timer/tar0_high.rs
index ba43f1ec62..abf6de0468 100644
--- a/esp32p4/src/lp_timer/tar0_high.rs
+++ b/esp32p4/src/lp_timer/tar0_high.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TAR0_HIGH")
-            .field(
-                "main_timer_tar_high0",
-                &format_args!("{}", self.main_timer_tar_high0().bits()),
-            )
+            .field("main_timer_tar_high0", &self.main_timer_tar_high0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TAR0_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_timer/tar0_low.rs b/esp32p4/src/lp_timer/tar0_low.rs
index 131d1c04d8..fe2273147d 100644
--- a/esp32p4/src/lp_timer/tar0_low.rs
+++ b/esp32p4/src/lp_timer/tar0_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TAR0_LOW")
-            .field(
-                "main_timer_tar_low0",
-                &format_args!("{}", self.main_timer_tar_low0().bits()),
-            )
+            .field("main_timer_tar_low0", &self.main_timer_tar_low0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TAR0_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_timer/tar1_high.rs b/esp32p4/src/lp_timer/tar1_high.rs
index b3005a0f94..730d601d28 100644
--- a/esp32p4/src/lp_timer/tar1_high.rs
+++ b/esp32p4/src/lp_timer/tar1_high.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TAR1_HIGH")
-            .field(
-                "main_timer_tar_high1",
-                &format_args!("{}", self.main_timer_tar_high1().bits()),
-            )
+            .field("main_timer_tar_high1", &self.main_timer_tar_high1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TAR1_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_timer/tar1_low.rs b/esp32p4/src/lp_timer/tar1_low.rs
index 78226f1ebc..1a74b66e78 100644
--- a/esp32p4/src/lp_timer/tar1_low.rs
+++ b/esp32p4/src/lp_timer/tar1_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TAR1_LOW")
-            .field(
-                "main_timer_tar_low1",
-                &format_args!("{}", self.main_timer_tar_low1().bits()),
-            )
+            .field("main_timer_tar_low1", &self.main_timer_tar_low1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TAR1_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_timer/update.rs b/esp32p4/src/lp_timer/update.rs
index 9f49d41d18..b0cb0a2d30 100644
--- a/esp32p4/src/lp_timer/update.rs
+++ b/esp32p4/src/lp_timer/update.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE")
-            .field(
-                "main_timer_xtal_off",
-                &format_args!("{}", self.main_timer_xtal_off().bit()),
-            )
-            .field(
-                "main_timer_sys_stall",
-                &format_args!("{}", self.main_timer_sys_stall().bit()),
-            )
-            .field(
-                "main_timer_sys_rst",
-                &format_args!("{}", self.main_timer_sys_rst().bit()),
-            )
+            .field("main_timer_xtal_off", &self.main_timer_xtal_off())
+            .field("main_timer_sys_stall", &self.main_timer_sys_stall())
+            .field("main_timer_sys_rst", &self.main_timer_sys_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_touch/chn_status.rs b/esp32p4/src/lp_touch/chn_status.rs
index 5a5c076d39..a5d836de91 100644
--- a/esp32p4/src/lp_touch/chn_status.rs
+++ b/esp32p4/src/lp_touch/chn_status.rs
@@ -27,18 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHN_STATUS")
-            .field("pad_active", &format_args!("{}", self.pad_active().bits()))
-            .field("meas_done", &format_args!("{}", self.meas_done().bit()))
-            .field("scan_curr", &format_args!("{}", self.scan_curr().bits()))
+            .field("pad_active", &self.pad_active())
+            .field("meas_done", &self.meas_done())
+            .field("scan_curr", &self.scan_curr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHN_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chn_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CHN_STATUS_SPEC;
 impl crate::RegisterSpec for CHN_STATUS_SPEC {
diff --git a/esp32p4/src/lp_touch/chn_tmp_status.rs b/esp32p4/src/lp_touch/chn_tmp_status.rs
index d9fff55566..e6a68fa5da 100644
--- a/esp32p4/src/lp_touch/chn_tmp_status.rs
+++ b/esp32p4/src/lp_touch/chn_tmp_status.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHN_TMP_STATUS")
-            .field(
-                "pad_inactive_status",
-                &format_args!("{}", self.pad_inactive_status().bits()),
-            )
-            .field(
-                "pad_active_status",
-                &format_args!("{}", self.pad_active_status().bits()),
-            )
+            .field("pad_inactive_status", &self.pad_inactive_status())
+            .field("pad_active_status", &self.pad_active_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHN_TMP_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chn_tmp_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CHN_TMP_STATUS_SPEC;
 impl crate::RegisterSpec for CHN_TMP_STATUS_SPEC {
diff --git a/esp32p4/src/lp_touch/date.rs b/esp32p4/src/lp_touch/date.rs
index 854ada4269..269a4bb9de 100644
--- a/esp32p4/src/lp_touch/date.rs
+++ b/esp32p4/src/lp_touch/date.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("rtc_date", &format_args!("{}", self.rtc_date().bits()))
-            .field("rtc_clk_en", &format_args!("{}", self.rtc_clk_en().bit()))
+            .field("rtc_date", &self.rtc_date())
+            .field("rtc_clk_en", &self.rtc_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_touch/int_ena.rs b/esp32p4/src/lp_touch/int_ena.rs
index c219b2d826..5306789904 100644
--- a/esp32p4/src/lp_touch/int_ena.rs
+++ b/esp32p4/src/lp_touch/int_ena.rs
@@ -62,24 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("scan_done", &format_args!("{}", self.scan_done().bit()))
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("active", &format_args!("{}", self.active().bit()))
-            .field("inactive", &format_args!("{}", self.inactive().bit()))
-            .field("timeout", &format_args!("{}", self.timeout().bit()))
-            .field(
-                "approach_loop_done",
-                &format_args!("{}", self.approach_loop_done().bit()),
-            )
+            .field("scan_done", &self.scan_done())
+            .field("done", &self.done())
+            .field("active", &self.active())
+            .field("inactive", &self.inactive())
+            .field("timeout", &self.timeout())
+            .field("approach_loop_done", &self.approach_loop_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_touch/int_raw.rs b/esp32p4/src/lp_touch/int_raw.rs
index 4891f4e56c..9b576ea4ad 100644
--- a/esp32p4/src/lp_touch/int_raw.rs
+++ b/esp32p4/src/lp_touch/int_raw.rs
@@ -62,24 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("scan_done", &format_args!("{}", self.scan_done().bit()))
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("active", &format_args!("{}", self.active().bit()))
-            .field("inactive", &format_args!("{}", self.inactive().bit()))
-            .field("timeout", &format_args!("{}", self.timeout().bit()))
-            .field(
-                "approach_loop_done",
-                &format_args!("{}", self.approach_loop_done().bit()),
-            )
+            .field("scan_done", &self.scan_done())
+            .field("done", &self.done())
+            .field("active", &self.active())
+            .field("inactive", &self.inactive())
+            .field("timeout", &self.timeout())
+            .field("approach_loop_done", &self.approach_loop_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_touch/int_st.rs b/esp32p4/src/lp_touch/int_st.rs
index b39ad67ca6..3385c836e2 100644
--- a/esp32p4/src/lp_touch/int_st.rs
+++ b/esp32p4/src/lp_touch/int_st.rs
@@ -48,24 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("scan_done", &format_args!("{}", self.scan_done().bit()))
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("active", &format_args!("{}", self.active().bit()))
-            .field("inactive", &format_args!("{}", self.inactive().bit()))
-            .field("timeout", &format_args!("{}", self.timeout().bit()))
-            .field(
-                "approach_loop_done",
-                &format_args!("{}", self.approach_loop_done().bit()),
-            )
+            .field("scan_done", &self.scan_done())
+            .field("done", &self.done())
+            .field("active", &self.active())
+            .field("inactive", &self.inactive())
+            .field("timeout", &self.timeout())
+            .field("approach_loop_done", &self.approach_loop_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/lp_touch/status_0.rs b/esp32p4/src/lp_touch/status_0.rs
index e79b9b0bf1..7aa0c546ac 100644
--- a/esp32p4/src/lp_touch/status_0.rs
+++ b/esp32p4/src/lp_touch/status_0.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_0")
-            .field("pad0_data", &format_args!("{}", self.pad0_data().bits()))
-            .field(
-                "pad0_debounce_cnt",
-                &format_args!("{}", self.pad0_debounce_cnt().bits()),
-            )
-            .field(
-                "pad0_neg_noise_cnt",
-                &format_args!("{}", self.pad0_neg_noise_cnt().bits()),
-            )
+            .field("pad0_data", &self.pad0_data())
+            .field("pad0_debounce_cnt", &self.pad0_debounce_cnt())
+            .field("pad0_neg_noise_cnt", &self.pad0_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_0_SPEC;
 impl crate::RegisterSpec for STATUS_0_SPEC {
diff --git a/esp32p4/src/lp_touch/status_1.rs b/esp32p4/src/lp_touch/status_1.rs
index aac825ed2a..a4a11264f6 100644
--- a/esp32p4/src/lp_touch/status_1.rs
+++ b/esp32p4/src/lp_touch/status_1.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_1")
-            .field("pad1_data", &format_args!("{}", self.pad1_data().bits()))
-            .field(
-                "pad1_debounce_cnt",
-                &format_args!("{}", self.pad1_debounce_cnt().bits()),
-            )
-            .field(
-                "pad1_neg_noise_cnt",
-                &format_args!("{}", self.pad1_neg_noise_cnt().bits()),
-            )
+            .field("pad1_data", &self.pad1_data())
+            .field("pad1_debounce_cnt", &self.pad1_debounce_cnt())
+            .field("pad1_neg_noise_cnt", &self.pad1_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_1_SPEC;
 impl crate::RegisterSpec for STATUS_1_SPEC {
diff --git a/esp32p4/src/lp_touch/status_10.rs b/esp32p4/src/lp_touch/status_10.rs
index 7315edd7e1..4c72708ca7 100644
--- a/esp32p4/src/lp_touch/status_10.rs
+++ b/esp32p4/src/lp_touch/status_10.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_10")
-            .field("pad10_data", &format_args!("{}", self.pad10_data().bits()))
-            .field(
-                "pad10_debounce_cnt",
-                &format_args!("{}", self.pad10_debounce_cnt().bits()),
-            )
-            .field(
-                "pad10_neg_noise_cnt",
-                &format_args!("{}", self.pad10_neg_noise_cnt().bits()),
-            )
+            .field("pad10_data", &self.pad10_data())
+            .field("pad10_debounce_cnt", &self.pad10_debounce_cnt())
+            .field("pad10_neg_noise_cnt", &self.pad10_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_10_SPEC;
 impl crate::RegisterSpec for STATUS_10_SPEC {
diff --git a/esp32p4/src/lp_touch/status_11.rs b/esp32p4/src/lp_touch/status_11.rs
index cecf1bbae7..4c19ace45c 100644
--- a/esp32p4/src/lp_touch/status_11.rs
+++ b/esp32p4/src/lp_touch/status_11.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_11")
-            .field("pad11_data", &format_args!("{}", self.pad11_data().bits()))
-            .field(
-                "pad11_debounce_cnt",
-                &format_args!("{}", self.pad11_debounce_cnt().bits()),
-            )
-            .field(
-                "pad11_neg_noise_cnt",
-                &format_args!("{}", self.pad11_neg_noise_cnt().bits()),
-            )
+            .field("pad11_data", &self.pad11_data())
+            .field("pad11_debounce_cnt", &self.pad11_debounce_cnt())
+            .field("pad11_neg_noise_cnt", &self.pad11_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_11_SPEC;
 impl crate::RegisterSpec for STATUS_11_SPEC {
diff --git a/esp32p4/src/lp_touch/status_12.rs b/esp32p4/src/lp_touch/status_12.rs
index 8ccaa3dbe8..73399a5022 100644
--- a/esp32p4/src/lp_touch/status_12.rs
+++ b/esp32p4/src/lp_touch/status_12.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_12")
-            .field("pad12_data", &format_args!("{}", self.pad12_data().bits()))
-            .field(
-                "pad12_debounce_cnt",
-                &format_args!("{}", self.pad12_debounce_cnt().bits()),
-            )
-            .field(
-                "pad12_neg_noise_cnt",
-                &format_args!("{}", self.pad12_neg_noise_cnt().bits()),
-            )
+            .field("pad12_data", &self.pad12_data())
+            .field("pad12_debounce_cnt", &self.pad12_debounce_cnt())
+            .field("pad12_neg_noise_cnt", &self.pad12_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_12::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_12_SPEC;
 impl crate::RegisterSpec for STATUS_12_SPEC {
diff --git a/esp32p4/src/lp_touch/status_13.rs b/esp32p4/src/lp_touch/status_13.rs
index 4382e998a4..0f976b0928 100644
--- a/esp32p4/src/lp_touch/status_13.rs
+++ b/esp32p4/src/lp_touch/status_13.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_13")
-            .field("pad13_data", &format_args!("{}", self.pad13_data().bits()))
-            .field(
-                "pad13_debounce_cnt",
-                &format_args!("{}", self.pad13_debounce_cnt().bits()),
-            )
-            .field(
-                "pad13_neg_noise_cnt",
-                &format_args!("{}", self.pad13_neg_noise_cnt().bits()),
-            )
+            .field("pad13_data", &self.pad13_data())
+            .field("pad13_debounce_cnt", &self.pad13_debounce_cnt())
+            .field("pad13_neg_noise_cnt", &self.pad13_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_13::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_13_SPEC;
 impl crate::RegisterSpec for STATUS_13_SPEC {
diff --git a/esp32p4/src/lp_touch/status_14.rs b/esp32p4/src/lp_touch/status_14.rs
index b1b1358c6a..157683df08 100644
--- a/esp32p4/src/lp_touch/status_14.rs
+++ b/esp32p4/src/lp_touch/status_14.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_14")
-            .field("pad14_data", &format_args!("{}", self.pad14_data().bits()))
-            .field(
-                "pad14_debounce_cnt",
-                &format_args!("{}", self.pad14_debounce_cnt().bits()),
-            )
-            .field(
-                "pad14_neg_noise_cnt",
-                &format_args!("{}", self.pad14_neg_noise_cnt().bits()),
-            )
+            .field("pad14_data", &self.pad14_data())
+            .field("pad14_debounce_cnt", &self.pad14_debounce_cnt())
+            .field("pad14_neg_noise_cnt", &self.pad14_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_14::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_14_SPEC;
 impl crate::RegisterSpec for STATUS_14_SPEC {
diff --git a/esp32p4/src/lp_touch/status_15.rs b/esp32p4/src/lp_touch/status_15.rs
index 8498e02d11..1848a64dd7 100644
--- a/esp32p4/src/lp_touch/status_15.rs
+++ b/esp32p4/src/lp_touch/status_15.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_15")
-            .field("slp_data", &format_args!("{}", self.slp_data().bits()))
-            .field(
-                "slp_debounce_cnt",
-                &format_args!("{}", self.slp_debounce_cnt().bits()),
-            )
-            .field(
-                "slp_neg_noise_cnt",
-                &format_args!("{}", self.slp_neg_noise_cnt().bits()),
-            )
+            .field("slp_data", &self.slp_data())
+            .field("slp_debounce_cnt", &self.slp_debounce_cnt())
+            .field("slp_neg_noise_cnt", &self.slp_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_15::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_15_SPEC;
 impl crate::RegisterSpec for STATUS_15_SPEC {
diff --git a/esp32p4/src/lp_touch/status_16.rs b/esp32p4/src/lp_touch/status_16.rs
index cc43a3a90b..2b223390cb 100644
--- a/esp32p4/src/lp_touch/status_16.rs
+++ b/esp32p4/src/lp_touch/status_16.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_16")
-            .field(
-                "approach_pad2_cnt",
-                &format_args!("{}", self.approach_pad2_cnt().bits()),
-            )
-            .field(
-                "approach_pad1_cnt",
-                &format_args!("{}", self.approach_pad1_cnt().bits()),
-            )
-            .field(
-                "approach_pad0_cnt",
-                &format_args!("{}", self.approach_pad0_cnt().bits()),
-            )
-            .field(
-                "slp_approach_cnt",
-                &format_args!("{}", self.slp_approach_cnt().bits()),
-            )
+            .field("approach_pad2_cnt", &self.approach_pad2_cnt())
+            .field("approach_pad1_cnt", &self.approach_pad1_cnt())
+            .field("approach_pad0_cnt", &self.approach_pad0_cnt())
+            .field("slp_approach_cnt", &self.slp_approach_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_16_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_16::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_16_SPEC;
 impl crate::RegisterSpec for STATUS_16_SPEC {
diff --git a/esp32p4/src/lp_touch/status_17.rs b/esp32p4/src/lp_touch/status_17.rs
index 6c65200802..289bcc53ca 100644
--- a/esp32p4/src/lp_touch/status_17.rs
+++ b/esp32p4/src/lp_touch/status_17.rs
@@ -48,24 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_17")
-            .field("dcap_lpf", &format_args!("{}", self.dcap_lpf().bits()))
-            .field("dres_lpf", &format_args!("{}", self.dres_lpf().bits()))
-            .field("drv_ls", &format_args!("{}", self.drv_ls().bits()))
-            .field("drv_hs", &format_args!("{}", self.drv_hs().bits()))
-            .field("dbias", &format_args!("{}", self.dbias().bits()))
-            .field(
-                "rtc_freq_scan_cnt",
-                &format_args!("{}", self.rtc_freq_scan_cnt().bits()),
-            )
+            .field("dcap_lpf", &self.dcap_lpf())
+            .field("dres_lpf", &self.dres_lpf())
+            .field("drv_ls", &self.drv_ls())
+            .field("drv_hs", &self.drv_hs())
+            .field("dbias", &self.dbias())
+            .field("rtc_freq_scan_cnt", &self.rtc_freq_scan_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_17_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_17::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_17_SPEC;
 impl crate::RegisterSpec for STATUS_17_SPEC {
diff --git a/esp32p4/src/lp_touch/status_2.rs b/esp32p4/src/lp_touch/status_2.rs
index 70c052dff7..2d6c23b601 100644
--- a/esp32p4/src/lp_touch/status_2.rs
+++ b/esp32p4/src/lp_touch/status_2.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_2")
-            .field("pad2_data", &format_args!("{}", self.pad2_data().bits()))
-            .field(
-                "pad2_debounce_cnt",
-                &format_args!("{}", self.pad2_debounce_cnt().bits()),
-            )
-            .field(
-                "pad2_neg_noise_cnt",
-                &format_args!("{}", self.pad2_neg_noise_cnt().bits()),
-            )
+            .field("pad2_data", &self.pad2_data())
+            .field("pad2_debounce_cnt", &self.pad2_debounce_cnt())
+            .field("pad2_neg_noise_cnt", &self.pad2_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_2_SPEC;
 impl crate::RegisterSpec for STATUS_2_SPEC {
diff --git a/esp32p4/src/lp_touch/status_3.rs b/esp32p4/src/lp_touch/status_3.rs
index b5c1f54604..095de68612 100644
--- a/esp32p4/src/lp_touch/status_3.rs
+++ b/esp32p4/src/lp_touch/status_3.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_3")
-            .field("pad3_data", &format_args!("{}", self.pad3_data().bits()))
-            .field(
-                "pad3_debounce_cnt",
-                &format_args!("{}", self.pad3_debounce_cnt().bits()),
-            )
-            .field(
-                "pad3_neg_noise_cnt",
-                &format_args!("{}", self.pad3_neg_noise_cnt().bits()),
-            )
+            .field("pad3_data", &self.pad3_data())
+            .field("pad3_debounce_cnt", &self.pad3_debounce_cnt())
+            .field("pad3_neg_noise_cnt", &self.pad3_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_3_SPEC;
 impl crate::RegisterSpec for STATUS_3_SPEC {
diff --git a/esp32p4/src/lp_touch/status_4.rs b/esp32p4/src/lp_touch/status_4.rs
index f576d73dc0..226b3ceac4 100644
--- a/esp32p4/src/lp_touch/status_4.rs
+++ b/esp32p4/src/lp_touch/status_4.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_4")
-            .field("pad4_data", &format_args!("{}", self.pad4_data().bits()))
-            .field(
-                "pad4_debounce_cnt",
-                &format_args!("{}", self.pad4_debounce_cnt().bits()),
-            )
-            .field(
-                "pad4_neg_noise_cnt",
-                &format_args!("{}", self.pad4_neg_noise_cnt().bits()),
-            )
+            .field("pad4_data", &self.pad4_data())
+            .field("pad4_debounce_cnt", &self.pad4_debounce_cnt())
+            .field("pad4_neg_noise_cnt", &self.pad4_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_4_SPEC;
 impl crate::RegisterSpec for STATUS_4_SPEC {
diff --git a/esp32p4/src/lp_touch/status_5.rs b/esp32p4/src/lp_touch/status_5.rs
index 2ba6980a2f..8180f9248f 100644
--- a/esp32p4/src/lp_touch/status_5.rs
+++ b/esp32p4/src/lp_touch/status_5.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_5")
-            .field("pad5_data", &format_args!("{}", self.pad5_data().bits()))
-            .field(
-                "pad5_debounce_cnt",
-                &format_args!("{}", self.pad5_debounce_cnt().bits()),
-            )
-            .field(
-                "pad5_neg_noise_cnt",
-                &format_args!("{}", self.pad5_neg_noise_cnt().bits()),
-            )
+            .field("pad5_data", &self.pad5_data())
+            .field("pad5_debounce_cnt", &self.pad5_debounce_cnt())
+            .field("pad5_neg_noise_cnt", &self.pad5_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_5_SPEC;
 impl crate::RegisterSpec for STATUS_5_SPEC {
diff --git a/esp32p4/src/lp_touch/status_6.rs b/esp32p4/src/lp_touch/status_6.rs
index 591b1895e5..ee65cfb271 100644
--- a/esp32p4/src/lp_touch/status_6.rs
+++ b/esp32p4/src/lp_touch/status_6.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_6")
-            .field("pad6_data", &format_args!("{}", self.pad6_data().bits()))
-            .field(
-                "pad6_debounce_cnt",
-                &format_args!("{}", self.pad6_debounce_cnt().bits()),
-            )
-            .field(
-                "pad6_neg_noise_cnt",
-                &format_args!("{}", self.pad6_neg_noise_cnt().bits()),
-            )
+            .field("pad6_data", &self.pad6_data())
+            .field("pad6_debounce_cnt", &self.pad6_debounce_cnt())
+            .field("pad6_neg_noise_cnt", &self.pad6_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_6_SPEC;
 impl crate::RegisterSpec for STATUS_6_SPEC {
diff --git a/esp32p4/src/lp_touch/status_7.rs b/esp32p4/src/lp_touch/status_7.rs
index 4f1d3ab9a6..99870eee89 100644
--- a/esp32p4/src/lp_touch/status_7.rs
+++ b/esp32p4/src/lp_touch/status_7.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_7")
-            .field("pad7_data", &format_args!("{}", self.pad7_data().bits()))
-            .field(
-                "pad7_debounce_cnt",
-                &format_args!("{}", self.pad7_debounce_cnt().bits()),
-            )
-            .field(
-                "pad7_neg_noise_cnt",
-                &format_args!("{}", self.pad7_neg_noise_cnt().bits()),
-            )
+            .field("pad7_data", &self.pad7_data())
+            .field("pad7_debounce_cnt", &self.pad7_debounce_cnt())
+            .field("pad7_neg_noise_cnt", &self.pad7_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_7_SPEC;
 impl crate::RegisterSpec for STATUS_7_SPEC {
diff --git a/esp32p4/src/lp_touch/status_8.rs b/esp32p4/src/lp_touch/status_8.rs
index 7965787de8..8b0ab66407 100644
--- a/esp32p4/src/lp_touch/status_8.rs
+++ b/esp32p4/src/lp_touch/status_8.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_8")
-            .field("pad8_data", &format_args!("{}", self.pad8_data().bits()))
-            .field(
-                "pad8_debounce_cnt",
-                &format_args!("{}", self.pad8_debounce_cnt().bits()),
-            )
-            .field(
-                "pad8_neg_noise_cnt",
-                &format_args!("{}", self.pad8_neg_noise_cnt().bits()),
-            )
+            .field("pad8_data", &self.pad8_data())
+            .field("pad8_debounce_cnt", &self.pad8_debounce_cnt())
+            .field("pad8_neg_noise_cnt", &self.pad8_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_8_SPEC;
 impl crate::RegisterSpec for STATUS_8_SPEC {
diff --git a/esp32p4/src/lp_touch/status_9.rs b/esp32p4/src/lp_touch/status_9.rs
index 145170ff0f..fb5c34c850 100644
--- a/esp32p4/src/lp_touch/status_9.rs
+++ b/esp32p4/src/lp_touch/status_9.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_9")
-            .field("pad9_data", &format_args!("{}", self.pad9_data().bits()))
-            .field(
-                "pad9_debounce_cnt",
-                &format_args!("{}", self.pad9_debounce_cnt().bits()),
-            )
-            .field(
-                "pad9_neg_noise_cnt",
-                &format_args!("{}", self.pad9_neg_noise_cnt().bits()),
-            )
+            .field("pad9_data", &self.pad9_data())
+            .field("pad9_debounce_cnt", &self.pad9_debounce_cnt())
+            .field("pad9_neg_noise_cnt", &self.pad9_neg_noise_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_9_SPEC;
 impl crate::RegisterSpec for STATUS_9_SPEC {
diff --git a/esp32p4/src/lp_tsens/clk_conf.rs b/esp32p4/src/lp_tsens/clk_conf.rs
index 91394b6a72..bfdc62e433 100644
--- a/esp32p4/src/lp_tsens/clk_conf.rs
+++ b/esp32p4/src/lp_tsens/clk_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Tsens regbank clock gating enable."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_tsens/ctrl.rs b/esp32p4/src/lp_tsens/ctrl.rs
index 17f8936d7e..8b65dbaa58 100644
--- a/esp32p4/src/lp_tsens/ctrl.rs
+++ b/esp32p4/src/lp_tsens/ctrl.rs
@@ -85,27 +85,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("out", &format_args!("{}", self.out().bits()))
-            .field("ready", &format_args!("{}", self.ready().bit()))
-            .field("sample_en", &format_args!("{}", self.sample_en().bit()))
-            .field("wakeup_mask", &format_args!("{}", self.wakeup_mask().bit()))
-            .field("int_en", &format_args!("{}", self.int_en().bit()))
-            .field("in_inv", &format_args!("{}", self.in_inv().bit()))
-            .field("clk_div", &format_args!("{}", self.clk_div().bits()))
-            .field("power_up", &format_args!("{}", self.power_up().bit()))
-            .field(
-                "power_up_force",
-                &format_args!("{}", self.power_up_force().bit()),
-            )
+            .field("out", &self.out())
+            .field("ready", &self.ready())
+            .field("sample_en", &self.sample_en())
+            .field("wakeup_mask", &self.wakeup_mask())
+            .field("int_en", &self.int_en())
+            .field("in_inv", &self.in_inv())
+            .field("clk_div", &self.clk_div())
+            .field("power_up", &self.power_up())
+            .field("power_up_force", &self.power_up_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - Enable sample signal for wakeup module."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_tsens/ctrl2.rs b/esp32p4/src/lp_tsens/ctrl2.rs
index b55a11513d..9ca790658e 100644
--- a/esp32p4/src/lp_tsens/ctrl2.rs
+++ b/esp32p4/src/lp_tsens/ctrl2.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field("xpd_wait", &format_args!("{}", self.xpd_wait().bits()))
-            .field("xpd_force", &format_args!("{}", self.xpd_force().bits()))
-            .field("clk_inv", &format_args!("{}", self.clk_inv().bit()))
+            .field("xpd_wait", &self.xpd_wait())
+            .field("xpd_force", &self.xpd_force())
+            .field("clk_inv", &self.clk_inv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_tsens/int_ena.rs b/esp32p4/src/lp_tsens/int_ena.rs
index 188bcdb93a..bda86a178e 100644
--- a/esp32p4/src/lp_tsens/int_ena.rs
+++ b/esp32p4/src/lp_tsens/int_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "cocpu_tsens_wake",
-                &format_args!("{}", self.cocpu_tsens_wake().bit()),
-            )
+            .field("cocpu_tsens_wake", &self.cocpu_tsens_wake())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Tsens wakeup interrupt enable."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_tsens/int_raw.rs b/esp32p4/src/lp_tsens/int_raw.rs
index 58275e2f55..ce2636adb1 100644
--- a/esp32p4/src/lp_tsens/int_raw.rs
+++ b/esp32p4/src/lp_tsens/int_raw.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "cocpu_tsens_wake",
-                &format_args!("{}", self.cocpu_tsens_wake().bit()),
-            )
+            .field("cocpu_tsens_wake", &self.cocpu_tsens_wake())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Tsens wakeup interrupt raw."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_tsens/int_st.rs b/esp32p4/src/lp_tsens/int_st.rs
index c754435bfc..5f18982f2c 100644
--- a/esp32p4/src/lp_tsens/int_st.rs
+++ b/esp32p4/src/lp_tsens/int_st.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "cocpu_tsens_wake",
-                &format_args!("{}", self.cocpu_tsens_wake().bit()),
-            )
+            .field("cocpu_tsens_wake", &self.cocpu_tsens_wake())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Tsens interrupt status registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/lp_tsens/rnd_eco_cs.rs b/esp32p4/src/lp_tsens/rnd_eco_cs.rs
index 0ee5cda8ca..77b98c54df 100644
--- a/esp32p4/src/lp_tsens/rnd_eco_cs.rs
+++ b/esp32p4/src/lp_tsens/rnd_eco_cs.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_CS")
-            .field("rnd_eco_en", &format_args!("{}", self.rnd_eco_en().bit()))
-            .field(
-                "rnd_eco_result",
-                &format_args!("{}", self.rnd_eco_result().bit()),
-            )
+            .field("rnd_eco_en", &self.rnd_eco_en())
+            .field("rnd_eco_result", &self.rnd_eco_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_CS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_tsens/rnd_eco_high.rs b/esp32p4/src/lp_tsens/rnd_eco_high.rs
index 46e6df17f4..a222a6c4bd 100644
--- a/esp32p4/src/lp_tsens/rnd_eco_high.rs
+++ b/esp32p4/src/lp_tsens/rnd_eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_HIGH")
-            .field(
-                "rnd_eco_high",
-                &format_args!("{}", self.rnd_eco_high().bits()),
-            )
+            .field("rnd_eco_high", &self.rnd_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_tsens/rnd_eco_low.rs b/esp32p4/src/lp_tsens/rnd_eco_low.rs
index f61a420f49..109836b913 100644
--- a/esp32p4/src/lp_tsens/rnd_eco_low.rs
+++ b/esp32p4/src/lp_tsens/rnd_eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RND_ECO_LOW")
-            .field(
-                "rnd_eco_low",
-                &format_args!("{}", self.rnd_eco_low().bits()),
-            )
+            .field("rnd_eco_low", &self.rnd_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RND_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_tsens/sample_rate.rs b/esp32p4/src/lp_tsens/sample_rate.rs
index d3eac9aa41..ea9c89864d 100644
--- a/esp32p4/src/lp_tsens/sample_rate.rs
+++ b/esp32p4/src/lp_tsens/sample_rate.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAMPLE_RATE")
-            .field(
-                "sample_rate",
-                &format_args!("{}", self.sample_rate().bits()),
-            )
+            .field("sample_rate", &self.sample_rate())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAMPLE_RATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Hardware automatic sampling rate."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_tsens/wakeup_ctrl.rs b/esp32p4/src/lp_tsens/wakeup_ctrl.rs
index 1315e2d3a3..b838659b5e 100644
--- a/esp32p4/src/lp_tsens/wakeup_ctrl.rs
+++ b/esp32p4/src/lp_tsens/wakeup_ctrl.rs
@@ -51,29 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WAKEUP_CTRL")
-            .field(
-                "wakeup_th_low",
-                &format_args!("{}", self.wakeup_th_low().bits()),
-            )
-            .field(
-                "wakeup_th_high",
-                &format_args!("{}", self.wakeup_th_high().bits()),
-            )
-            .field(
-                "wakeup_over_upper_th",
-                &format_args!("{}", self.wakeup_over_upper_th().bit()),
-            )
-            .field("wakeup_en", &format_args!("{}", self.wakeup_en().bit()))
-            .field("wakeup_mode", &format_args!("{}", self.wakeup_mode().bit()))
+            .field("wakeup_th_low", &self.wakeup_th_low())
+            .field("wakeup_th_high", &self.wakeup_th_high())
+            .field("wakeup_over_upper_th", &self.wakeup_over_upper_th())
+            .field("wakeup_en", &self.wakeup_en())
+            .field("wakeup_mode", &self.wakeup_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WAKEUP_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Lower threshold."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/afifo_status.rs b/esp32p4/src/lp_uart/afifo_status.rs
index 32a27a7eed..22f55103b7 100644
--- a/esp32p4/src/lp_uart/afifo_status.rs
+++ b/esp32p4/src/lp_uart/afifo_status.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AFIFO_STATUS")
-            .field(
-                "tx_afifo_full",
-                &format_args!("{}", self.tx_afifo_full().bit()),
-            )
-            .field(
-                "tx_afifo_empty",
-                &format_args!("{}", self.tx_afifo_empty().bit()),
-            )
-            .field(
-                "rx_afifo_full",
-                &format_args!("{}", self.rx_afifo_full().bit()),
-            )
-            .field(
-                "rx_afifo_empty",
-                &format_args!("{}", self.rx_afifo_empty().bit()),
-            )
+            .field("tx_afifo_full", &self.tx_afifo_full())
+            .field("tx_afifo_empty", &self.tx_afifo_empty())
+            .field("rx_afifo_full", &self.rx_afifo_full())
+            .field("rx_afifo_empty", &self.rx_afifo_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART AFIFO Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`afifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for AFIFO_STATUS_SPEC {
diff --git a/esp32p4/src/lp_uart/at_cmd_char_sync.rs b/esp32p4/src/lp_uart/at_cmd_char_sync.rs
index 61d6f515b8..73181d6fdd 100644
--- a/esp32p4/src/lp_uart/at_cmd_char_sync.rs
+++ b/esp32p4/src/lp_uart/at_cmd_char_sync.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_CHAR_SYNC")
-            .field(
-                "at_cmd_char",
-                &format_args!("{}", self.at_cmd_char().bits()),
-            )
-            .field("char_num", &format_args!("{}", self.char_num().bits()))
+            .field("at_cmd_char", &self.at_cmd_char())
+            .field("char_num", &self.char_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_CHAR_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/at_cmd_gaptout_sync.rs b/esp32p4/src/lp_uart/at_cmd_gaptout_sync.rs
index 4c3bef3cde..6da82a6678 100644
--- a/esp32p4/src/lp_uart/at_cmd_gaptout_sync.rs
+++ b/esp32p4/src/lp_uart/at_cmd_gaptout_sync.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_GAPTOUT_SYNC")
-            .field(
-                "rx_gap_tout",
-                &format_args!("{}", self.rx_gap_tout().bits()),
-            )
+            .field("rx_gap_tout", &self.rx_gap_tout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_GAPTOUT_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the at_cmd chars."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/at_cmd_postcnt_sync.rs b/esp32p4/src/lp_uart/at_cmd_postcnt_sync.rs
index 7489ff4b31..23ce0ca37d 100644
--- a/esp32p4/src/lp_uart/at_cmd_postcnt_sync.rs
+++ b/esp32p4/src/lp_uart/at_cmd_postcnt_sync.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_POSTCNT_SYNC")
-            .field(
-                "post_idle_num",
-                &format_args!("{}", self.post_idle_num().bits()),
-            )
+            .field("post_idle_num", &self.post_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_POSTCNT_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the last at_cmd and the next data."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/at_cmd_precnt_sync.rs b/esp32p4/src/lp_uart/at_cmd_precnt_sync.rs
index e96ddde6d5..9b4dbd34ae 100644
--- a/esp32p4/src/lp_uart/at_cmd_precnt_sync.rs
+++ b/esp32p4/src/lp_uart/at_cmd_precnt_sync.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_PRECNT_SYNC")
-            .field(
-                "pre_idle_num",
-                &format_args!("{}", self.pre_idle_num().bits()),
-            )
+            .field("pre_idle_num", &self.pre_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_PRECNT_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first at_cmd is received by receiver."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/clk_conf.rs b/esp32p4/src/lp_uart/clk_conf.rs
index 52620b1d53..0ef610442e 100644
--- a/esp32p4/src/lp_uart/clk_conf.rs
+++ b/esp32p4/src/lp_uart/clk_conf.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field("tx_sclk_en", &format_args!("{}", self.tx_sclk_en().bit()))
-            .field("rx_sclk_en", &format_args!("{}", self.rx_sclk_en().bit()))
-            .field("tx_rst_core", &format_args!("{}", self.tx_rst_core().bit()))
-            .field("rx_rst_core", &format_args!("{}", self.rx_rst_core().bit()))
+            .field("tx_sclk_en", &self.tx_sclk_en())
+            .field("rx_sclk_en", &self.rx_sclk_en())
+            .field("tx_rst_core", &self.tx_rst_core())
+            .field("rx_rst_core", &self.rx_rst_core())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - Set this bit to enable UART Tx clock."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/clkdiv_sync.rs b/esp32p4/src/lp_uart/clkdiv_sync.rs
index 9b5485fec2..7bf406c6e5 100644
--- a/esp32p4/src/lp_uart/clkdiv_sync.rs
+++ b/esp32p4/src/lp_uart/clkdiv_sync.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKDIV_SYNC")
-            .field("clkdiv", &format_args!("{}", self.clkdiv().bits()))
-            .field(
-                "clkdiv_frag",
-                &format_args!("{}", self.clkdiv_frag().bits()),
-            )
+            .field("clkdiv", &self.clkdiv())
+            .field("clkdiv_frag", &self.clkdiv_frag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKDIV_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/conf0_sync.rs b/esp32p4/src/lp_uart/conf0_sync.rs
index a857de9e30..d553b3f069 100644
--- a/esp32p4/src/lp_uart/conf0_sync.rs
+++ b/esp32p4/src/lp_uart/conf0_sync.rs
@@ -143,36 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0_SYNC")
-            .field("parity", &format_args!("{}", self.parity().bit()))
-            .field("parity_en", &format_args!("{}", self.parity_en().bit()))
-            .field("bit_num", &format_args!("{}", self.bit_num().bits()))
-            .field(
-                "stop_bit_num",
-                &format_args!("{}", self.stop_bit_num().bits()),
-            )
-            .field("txd_brk", &format_args!("{}", self.txd_brk().bit()))
-            .field("loopback", &format_args!("{}", self.loopback().bit()))
-            .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit()))
-            .field("rxd_inv", &format_args!("{}", self.rxd_inv().bit()))
-            .field("txd_inv", &format_args!("{}", self.txd_inv().bit()))
-            .field(
-                "dis_rx_dat_ovf",
-                &format_args!("{}", self.dis_rx_dat_ovf().bit()),
-            )
-            .field("err_wr_mask", &format_args!("{}", self.err_wr_mask().bit()))
-            .field("mem_clk_en", &format_args!("{}", self.mem_clk_en().bit()))
-            .field("sw_rts", &format_args!("{}", self.sw_rts().bit()))
-            .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit()))
-            .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit()))
+            .field("parity", &self.parity())
+            .field("parity_en", &self.parity_en())
+            .field("bit_num", &self.bit_num())
+            .field("stop_bit_num", &self.stop_bit_num())
+            .field("txd_brk", &self.txd_brk())
+            .field("loopback", &self.loopback())
+            .field("tx_flow_en", &self.tx_flow_en())
+            .field("rxd_inv", &self.rxd_inv())
+            .field("txd_inv", &self.txd_inv())
+            .field("dis_rx_dat_ovf", &self.dis_rx_dat_ovf())
+            .field("err_wr_mask", &self.err_wr_mask())
+            .field("mem_clk_en", &self.mem_clk_en())
+            .field("sw_rts", &self.sw_rts())
+            .field("rxfifo_rst", &self.rxfifo_rst())
+            .field("txfifo_rst", &self.txfifo_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to configure the parity check mode."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/conf1.rs b/esp32p4/src/lp_uart/conf1.rs
index 1c6045b655..dfab209c1d 100644
--- a/esp32p4/src/lp_uart/conf1.rs
+++ b/esp32p4/src/lp_uart/conf1.rs
@@ -80,29 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "rxfifo_full_thrhd",
-                &format_args!("{}", self.rxfifo_full_thrhd().bits()),
-            )
-            .field(
-                "txfifo_empty_thrhd",
-                &format_args!("{}", self.txfifo_empty_thrhd().bits()),
-            )
-            .field("cts_inv", &format_args!("{}", self.cts_inv().bit()))
-            .field("dsr_inv", &format_args!("{}", self.dsr_inv().bit()))
-            .field("rts_inv", &format_args!("{}", self.rts_inv().bit()))
-            .field("dtr_inv", &format_args!("{}", self.dtr_inv().bit()))
-            .field("sw_dtr", &format_args!("{}", self.sw_dtr().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("rxfifo_full_thrhd", &self.rxfifo_full_thrhd())
+            .field("txfifo_empty_thrhd", &self.txfifo_empty_thrhd())
+            .field("cts_inv", &self.cts_inv())
+            .field("dsr_inv", &self.dsr_inv())
+            .field("rts_inv", &self.rts_inv())
+            .field("dtr_inv", &self.dtr_inv())
+            .field("sw_dtr", &self.sw_dtr())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:7 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/date.rs b/esp32p4/src/lp_uart/date.rs
index ca8e77528d..a8a192238f 100644
--- a/esp32p4/src/lp_uart/date.rs
+++ b/esp32p4/src/lp_uart/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/lp_uart/fifo.rs b/esp32p4/src/lp_uart/fifo.rs
index 0f69f5a845..30ff8b3ce4 100644
--- a/esp32p4/src/lp_uart/fifo.rs
+++ b/esp32p4/src/lp_uart/fifo.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO")
-            .field(
-                "rxfifo_rd_byte",
-                &format_args!("{}", self.rxfifo_rd_byte().bits()),
-            )
+            .field("rxfifo_rd_byte", &self.rxfifo_rd_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "FIFO data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_SPEC;
 impl crate::RegisterSpec for FIFO_SPEC {
diff --git a/esp32p4/src/lp_uart/fsm_status.rs b/esp32p4/src/lp_uart/fsm_status.rs
index 7e47b06bf6..4088ac153f 100644
--- a/esp32p4/src/lp_uart/fsm_status.rs
+++ b/esp32p4/src/lp_uart/fsm_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_STATUS")
-            .field("st_urx_out", &format_args!("{}", self.st_urx_out().bits()))
-            .field("st_utx_out", &format_args!("{}", self.st_utx_out().bits()))
+            .field("st_urx_out", &self.st_urx_out())
+            .field("st_utx_out", &self.st_utx_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART transmit and receive status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FSM_STATUS_SPEC;
 impl crate::RegisterSpec for FSM_STATUS_SPEC {
diff --git a/esp32p4/src/lp_uart/hwfc_conf_sync.rs b/esp32p4/src/lp_uart/hwfc_conf_sync.rs
index 0284e7e2da..3ffd3cc4ac 100644
--- a/esp32p4/src/lp_uart/hwfc_conf_sync.rs
+++ b/esp32p4/src/lp_uart/hwfc_conf_sync.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HWFC_CONF_SYNC")
-            .field(
-                "rx_flow_thrhd",
-                &format_args!("{}", self.rx_flow_thrhd().bits()),
-            )
-            .field("rx_flow_en", &format_args!("{}", self.rx_flow_en().bit()))
+            .field("rx_flow_thrhd", &self.rx_flow_thrhd())
+            .field("rx_flow_en", &self.rx_flow_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HWFC_CONF_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:7 - This register is used to configure the maximum amount of data that can be received when hardware flow control works."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/id.rs b/esp32p4/src/lp_uart/id.rs
index 9c8cfa3a6b..670842afd9 100644
--- a/esp32p4/src/lp_uart/id.rs
+++ b/esp32p4/src/lp_uart/id.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("ID")
-            .field("id", &format_args!("{}", self.id().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("ID").field("id", &self.id()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/lp_uart/idle_conf_sync.rs b/esp32p4/src/lp_uart/idle_conf_sync.rs
index 9f4f7d07c5..50b7bda9ab 100644
--- a/esp32p4/src/lp_uart/idle_conf_sync.rs
+++ b/esp32p4/src/lp_uart/idle_conf_sync.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDLE_CONF_SYNC")
-            .field(
-                "rx_idle_thrhd",
-                &format_args!("{}", self.rx_idle_thrhd().bits()),
-            )
-            .field(
-                "tx_idle_num",
-                &format_args!("{}", self.tx_idle_num().bits()),
-            )
+            .field("rx_idle_thrhd", &self.rx_idle_thrhd())
+            .field("tx_idle_num", &self.tx_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_CONF_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/int_ena.rs b/esp32p4/src/lp_uart/int_ena.rs
index 3d91b96662..ae4d6f4b24 100644
--- a/esp32p4/src/lp_uart/int_ena.rs
+++ b/esp32p4/src/lp_uart/int_ena.rs
@@ -161,41 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/int_raw.rs b/esp32p4/src/lp_uart/int_raw.rs
index dcfb481c5d..3e2b40190a 100644
--- a/esp32p4/src/lp_uart/int_raw.rs
+++ b/esp32p4/src/lp_uart/int_raw.rs
@@ -161,41 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/int_st.rs b/esp32p4/src/lp_uart/int_st.rs
index 82aaf89509..57e0dc3bd8 100644
--- a/esp32p4/src/lp_uart/int_st.rs
+++ b/esp32p4/src/lp_uart/int_st.rs
@@ -125,41 +125,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/lp_uart/mem_conf.rs b/esp32p4/src/lp_uart/mem_conf.rs
index 8c55da8b47..e930d52fc0 100644
--- a/esp32p4/src/lp_uart/mem_conf.rs
+++ b/esp32p4/src/lp_uart/mem_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - Set this bit to force power down UART memory."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/mem_rx_status.rs b/esp32p4/src/lp_uart/mem_rx_status.rs
index fafe24b358..d7b91a2cef 100644
--- a/esp32p4/src/lp_uart/mem_rx_status.rs
+++ b/esp32p4/src/lp_uart/mem_rx_status.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_RX_STATUS")
-            .field(
-                "rx_sram_raddr",
-                &format_args!("{}", self.rx_sram_raddr().bits()),
-            )
-            .field(
-                "rx_sram_waddr",
-                &format_args!("{}", self.rx_sram_waddr().bits()),
-            )
+            .field("rx_sram_raddr", &self.rx_sram_raddr())
+            .field("rx_sram_waddr", &self.rx_sram_waddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Rx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_RX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_RX_STATUS_SPEC {
diff --git a/esp32p4/src/lp_uart/mem_tx_status.rs b/esp32p4/src/lp_uart/mem_tx_status.rs
index 05d25d084e..1ad31fce44 100644
--- a/esp32p4/src/lp_uart/mem_tx_status.rs
+++ b/esp32p4/src/lp_uart/mem_tx_status.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_TX_STATUS")
-            .field(
-                "tx_sram_waddr",
-                &format_args!("{}", self.tx_sram_waddr().bits()),
-            )
-            .field(
-                "tx_sram_raddr",
-                &format_args!("{}", self.tx_sram_raddr().bits()),
-            )
+            .field("tx_sram_waddr", &self.tx_sram_waddr())
+            .field("tx_sram_raddr", &self.tx_sram_raddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Tx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_TX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_TX_STATUS_SPEC {
diff --git a/esp32p4/src/lp_uart/reg_update.rs b/esp32p4/src/lp_uart/reg_update.rs
index b2e4551f76..441e05815f 100644
--- a/esp32p4/src/lp_uart/reg_update.rs
+++ b/esp32p4/src/lp_uart/reg_update.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_UPDATE")
-            .field("reg_update", &format_args!("{}", self.reg_update().bit()))
+            .field("reg_update", &self.reg_update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/rs485_conf_sync.rs b/esp32p4/src/lp_uart/rs485_conf_sync.rs
index 9dc21e5447..f910bef69a 100644
--- a/esp32p4/src/lp_uart/rs485_conf_sync.rs
+++ b/esp32p4/src/lp_uart/rs485_conf_sync.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RS485_CONF_SYNC")
-            .field("dl0_en", &format_args!("{}", self.dl0_en().bit()))
-            .field("dl1_en", &format_args!("{}", self.dl1_en().bit()))
+            .field("dl0_en", &self.dl0_en())
+            .field("dl1_en", &self.dl1_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RS485_CONF_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set this bit to delay the stop bit by 1 bit."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/rx_filt.rs b/esp32p4/src/lp_uart/rx_filt.rs
index c24c62977e..21576af0e9 100644
--- a/esp32p4/src/lp_uart/rx_filt.rs
+++ b/esp32p4/src/lp_uart/rx_filt.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_FILT")
-            .field(
-                "glitch_filt",
-                &format_args!("{}", self.glitch_filt().bits()),
-            )
-            .field(
-                "glitch_filt_en",
-                &format_args!("{}", self.glitch_filt_en().bit()),
-            )
+            .field("glitch_filt", &self.glitch_filt())
+            .field("glitch_filt_en", &self.glitch_filt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_FILT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - when input pulse width is lower than this value the pulse is ignored."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/sleep_conf0.rs b/esp32p4/src/lp_uart/sleep_conf0.rs
index 1c5c7f7eed..a8481a8783 100644
--- a/esp32p4/src/lp_uart/sleep_conf0.rs
+++ b/esp32p4/src/lp_uart/sleep_conf0.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF0")
-            .field("wk_char1", &format_args!("{}", self.wk_char1().bits()))
-            .field("wk_char2", &format_args!("{}", self.wk_char2().bits()))
-            .field("wk_char3", &format_args!("{}", self.wk_char3().bits()))
-            .field("wk_char4", &format_args!("{}", self.wk_char4().bits()))
+            .field("wk_char1", &self.wk_char1())
+            .field("wk_char2", &self.wk_char2())
+            .field("wk_char3", &self.wk_char3())
+            .field("wk_char4", &self.wk_char4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register restores the specified wake up char1 to wake up"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/sleep_conf1.rs b/esp32p4/src/lp_uart/sleep_conf1.rs
index f9f665a833..bf71699cf5 100644
--- a/esp32p4/src/lp_uart/sleep_conf1.rs
+++ b/esp32p4/src/lp_uart/sleep_conf1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF1")
-            .field("wk_char0", &format_args!("{}", self.wk_char0().bits()))
+            .field("wk_char0", &self.wk_char0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register restores the specified char0 to wake up"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/sleep_conf2.rs b/esp32p4/src/lp_uart/sleep_conf2.rs
index f2fdbaae7f..a32f4c66fd 100644
--- a/esp32p4/src/lp_uart/sleep_conf2.rs
+++ b/esp32p4/src/lp_uart/sleep_conf2.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF2")
-            .field(
-                "active_threshold",
-                &format_args!("{}", self.active_threshold().bits()),
-            )
-            .field(
-                "rx_wake_up_thrhd",
-                &format_args!("{}", self.rx_wake_up_thrhd().bits()),
-            )
-            .field(
-                "wk_char_num",
-                &format_args!("{}", self.wk_char_num().bits()),
-            )
-            .field(
-                "wk_char_mask",
-                &format_args!("{}", self.wk_char_mask().bits()),
-            )
-            .field(
-                "wk_mode_sel",
-                &format_args!("{}", self.wk_mode_sel().bits()),
-            )
+            .field("active_threshold", &self.active_threshold())
+            .field("rx_wake_up_thrhd", &self.rx_wake_up_thrhd())
+            .field("wk_char_num", &self.wk_char_num())
+            .field("wk_char_mask", &self.wk_char_mask())
+            .field("wk_mode_sel", &self.wk_mode_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/status.rs b/esp32p4/src/lp_uart/status.rs
index 50000e82e0..d25c3beb30 100644
--- a/esp32p4/src/lp_uart/status.rs
+++ b/esp32p4/src/lp_uart/status.rs
@@ -62,23 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("dsrn", &format_args!("{}", self.dsrn().bit()))
-            .field("ctsn", &format_args!("{}", self.ctsn().bit()))
-            .field("rxd", &format_args!("{}", self.rxd().bit()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field("dtrn", &format_args!("{}", self.dtrn().bit()))
-            .field("rtsn", &format_args!("{}", self.rtsn().bit()))
-            .field("txd", &format_args!("{}", self.txd().bit()))
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("dsrn", &self.dsrn())
+            .field("ctsn", &self.ctsn())
+            .field("rxd", &self.rxd())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("dtrn", &self.dtrn())
+            .field("rtsn", &self.rtsn())
+            .field("txd", &self.txd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32p4/src/lp_uart/swfc_conf0_sync.rs b/esp32p4/src/lp_uart/swfc_conf0_sync.rs
index e29be79632..3b6b88a494 100644
--- a/esp32p4/src/lp_uart/swfc_conf0_sync.rs
+++ b/esp32p4/src/lp_uart/swfc_conf0_sync.rs
@@ -89,30 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF0_SYNC")
-            .field("xon_char", &format_args!("{}", self.xon_char().bits()))
-            .field("xoff_char", &format_args!("{}", self.xoff_char().bits()))
-            .field(
-                "xon_xoff_still_send",
-                &format_args!("{}", self.xon_xoff_still_send().bit()),
-            )
-            .field(
-                "sw_flow_con_en",
-                &format_args!("{}", self.sw_flow_con_en().bit()),
-            )
-            .field("xonoff_del", &format_args!("{}", self.xonoff_del().bit()))
-            .field("force_xon", &format_args!("{}", self.force_xon().bit()))
-            .field("force_xoff", &format_args!("{}", self.force_xoff().bit()))
-            .field("send_xon", &format_args!("{}", self.send_xon().bit()))
-            .field("send_xoff", &format_args!("{}", self.send_xoff().bit()))
+            .field("xon_char", &self.xon_char())
+            .field("xoff_char", &self.xoff_char())
+            .field("xon_xoff_still_send", &self.xon_xoff_still_send())
+            .field("sw_flow_con_en", &self.sw_flow_con_en())
+            .field("xonoff_del", &self.xonoff_del())
+            .field("force_xon", &self.force_xon())
+            .field("force_xoff", &self.force_xoff())
+            .field("send_xon", &self.send_xon())
+            .field("send_xoff", &self.send_xoff())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF0_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register stores the Xon flow control char."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/swfc_conf1.rs b/esp32p4/src/lp_uart/swfc_conf1.rs
index 253a05d3c6..15050eecf9 100644
--- a/esp32p4/src/lp_uart/swfc_conf1.rs
+++ b/esp32p4/src/lp_uart/swfc_conf1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF1")
-            .field(
-                "xon_threshold",
-                &format_args!("{}", self.xon_threshold().bits()),
-            )
-            .field(
-                "xoff_threshold",
-                &format_args!("{}", self.xoff_threshold().bits()),
-            )
+            .field("xon_threshold", &self.xon_threshold())
+            .field("xoff_threshold", &self.xoff_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:7 - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/tout_conf_sync.rs b/esp32p4/src/lp_uart/tout_conf_sync.rs
index 972d62c52a..11491121e1 100644
--- a/esp32p4/src/lp_uart/tout_conf_sync.rs
+++ b/esp32p4/src/lp_uart/tout_conf_sync.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUT_CONF_SYNC")
-            .field("rx_tout_en", &format_args!("{}", self.rx_tout_en().bit()))
-            .field(
-                "rx_tout_flow_dis",
-                &format_args!("{}", self.rx_tout_flow_dis().bit()),
-            )
-            .field(
-                "rx_tout_thrhd",
-                &format_args!("{}", self.rx_tout_thrhd().bits()),
-            )
+            .field("rx_tout_en", &self.rx_tout_en())
+            .field("rx_tout_flow_dis", &self.rx_tout_flow_dis())
+            .field("rx_tout_thrhd", &self.rx_tout_thrhd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUT_CONF_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enble bit for uart receiver's timeout function."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_uart/txbrk_conf_sync.rs b/esp32p4/src/lp_uart/txbrk_conf_sync.rs
index 5a96901f8a..413d24ce7d 100644
--- a/esp32p4/src/lp_uart/txbrk_conf_sync.rs
+++ b/esp32p4/src/lp_uart/txbrk_conf_sync.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXBRK_CONF_SYNC")
-            .field("tx_brk_num", &format_args!("{}", self.tx_brk_num().bits()))
+            .field("tx_brk_num", &self.tx_brk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXBRK_CONF_SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."]
     #[inline(always)]
diff --git a/esp32p4/src/lp_wdt/config0.rs b/esp32p4/src/lp_wdt/config0.rs
index c07a77295a..59a4cb7788 100644
--- a/esp32p4/src/lp_wdt/config0.rs
+++ b/esp32p4/src/lp_wdt/config0.rs
@@ -125,52 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG0")
-            .field(
-                "wdt_chip_reset_width",
-                &format_args!("{}", self.wdt_chip_reset_width().bits()),
-            )
-            .field(
-                "wdt_chip_reset_en",
-                &format_args!("{}", self.wdt_chip_reset_en().bit()),
-            )
-            .field(
-                "wdt_pause_in_slp",
-                &format_args!("{}", self.wdt_pause_in_slp().bit()),
-            )
-            .field(
-                "wdt_appcpu_reset_en",
-                &format_args!("{}", self.wdt_appcpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_chip_reset_width", &self.wdt_chip_reset_width())
+            .field("wdt_chip_reset_en", &self.wdt_chip_reset_en())
+            .field("wdt_pause_in_slp", &self.wdt_pause_in_slp())
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_wdt/config1.rs b/esp32p4/src/lp_wdt/config1.rs
index 5718bd36a7..cc20f95485 100644
--- a/esp32p4/src/lp_wdt/config1.rs
+++ b/esp32p4/src/lp_wdt/config1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG1")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_wdt/config2.rs b/esp32p4/src/lp_wdt/config2.rs
index a1ed774a2e..1208d49421 100644
--- a/esp32p4/src/lp_wdt/config2.rs
+++ b/esp32p4/src/lp_wdt/config2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG2")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_wdt/config3.rs b/esp32p4/src/lp_wdt/config3.rs
index 51d57fe8f9..41322e4dc9 100644
--- a/esp32p4/src/lp_wdt/config3.rs
+++ b/esp32p4/src/lp_wdt/config3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG3")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_wdt/config4.rs b/esp32p4/src/lp_wdt/config4.rs
index f0857186f5..efe8bb1a07 100644
--- a/esp32p4/src/lp_wdt/config4.rs
+++ b/esp32p4/src/lp_wdt/config4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG4")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_wdt/date.rs b/esp32p4/src/lp_wdt/date.rs
index ad999360f1..c4762f886a 100644
--- a/esp32p4/src/lp_wdt/date.rs
+++ b/esp32p4/src/lp_wdt/date.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "lp_wdt_date",
-                &format_args!("{}", self.lp_wdt_date().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("lp_wdt_date", &self.lp_wdt_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_wdt/int_ena.rs b/esp32p4/src/lp_wdt/int_ena.rs
index 31da42e32e..8fa7730e67 100644
--- a/esp32p4/src/lp_wdt/int_ena.rs
+++ b/esp32p4/src/lp_wdt/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("super_wdt", &format_args!("{}", self.super_wdt().bit()))
-            .field("lp_wdt", &format_args!("{}", self.lp_wdt().bit()))
+            .field("super_wdt", &self.super_wdt())
+            .field("lp_wdt", &self.lp_wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_wdt/int_raw.rs b/esp32p4/src/lp_wdt/int_raw.rs
index c4f12e1d5e..fd7e3c5567 100644
--- a/esp32p4/src/lp_wdt/int_raw.rs
+++ b/esp32p4/src/lp_wdt/int_raw.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("super_wdt", &format_args!("{}", self.super_wdt().bit()))
-            .field("lp_wdt", &format_args!("{}", self.lp_wdt().bit()))
+            .field("super_wdt", &self.super_wdt())
+            .field("lp_wdt", &self.lp_wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_wdt/int_st.rs b/esp32p4/src/lp_wdt/int_st.rs
index 0f1014ca7b..7801732fb2 100644
--- a/esp32p4/src/lp_wdt/int_st.rs
+++ b/esp32p4/src/lp_wdt/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("super_wdt", &format_args!("{}", self.super_wdt().bit()))
-            .field("lp_wdt", &format_args!("{}", self.lp_wdt().bit()))
+            .field("super_wdt", &self.super_wdt())
+            .field("lp_wdt", &self.lp_wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/lp_wdt/swd_config.rs b/esp32p4/src/lp_wdt/swd_config.rs
index edafc084f0..3c3b00ce99 100644
--- a/esp32p4/src/lp_wdt/swd_config.rs
+++ b/esp32p4/src/lp_wdt/swd_config.rs
@@ -46,28 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_CONFIG")
-            .field(
-                "swd_reset_flag",
-                &format_args!("{}", self.swd_reset_flag().bit()),
-            )
-            .field(
-                "swd_auto_feed_en",
-                &format_args!("{}", self.swd_auto_feed_en().bit()),
-            )
-            .field(
-                "swd_signal_width",
-                &format_args!("{}", self.swd_signal_width().bits()),
-            )
-            .field("swd_disable", &format_args!("{}", self.swd_disable().bit()))
+            .field("swd_reset_flag", &self.swd_reset_flag())
+            .field("swd_auto_feed_en", &self.swd_auto_feed_en())
+            .field("swd_signal_width", &self.swd_signal_width())
+            .field("swd_disable", &self.swd_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_wdt/swd_wprotect.rs b/esp32p4/src/lp_wdt/swd_wprotect.rs
index b3d6f51abb..38581d43f4 100644
--- a/esp32p4/src/lp_wdt/swd_wprotect.rs
+++ b/esp32p4/src/lp_wdt/swd_wprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_WPROTECT")
-            .field("swd_wkey", &format_args!("{}", self.swd_wkey().bits()))
+            .field("swd_wkey", &self.swd_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_WPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/lp_wdt/wprotect.rs b/esp32p4/src/lp_wdt/wprotect.rs
index e32763d1d9..fe98108b4e 100644
--- a/esp32p4/src/lp_wdt/wprotect.rs
+++ b/esp32p4/src/lp_wdt/wprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/cap_ch.rs b/esp32p4/src/mcpwm0/cap_ch.rs
index c35cb35aeb..1825d5d768 100644
--- a/esp32p4/src/mcpwm0/cap_ch.rs
+++ b/esp32p4/src/mcpwm0/cap_ch.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_CH")
-            .field("value", &format_args!("{}", self.value().bits()))
+            .field("value", &self.value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CAP%s capture value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_ch::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CAP_CH_SPEC;
 impl crate::RegisterSpec for CAP_CH_SPEC {
diff --git a/esp32p4/src/mcpwm0/cap_ch_cfg.rs b/esp32p4/src/mcpwm0/cap_ch_cfg.rs
index 75f76edb92..25439265b0 100644
--- a/esp32p4/src/mcpwm0/cap_ch_cfg.rs
+++ b/esp32p4/src/mcpwm0/cap_ch_cfg.rs
@@ -46,19 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_CH_CFG")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
-            .field("in_invert", &format_args!("{}", self.in_invert().bit()))
+            .field("en", &self.en())
+            .field("mode", &self.mode())
+            .field("prescale", &self.prescale())
+            .field("in_invert", &self.in_invert())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_CH_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to enable capture on channel %s.\\\\0: Disable\\\\1: Enable"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/cap_status.rs b/esp32p4/src/mcpwm0/cap_status.rs
index bb5b917af4..6dc8f0eb14 100644
--- a/esp32p4/src/mcpwm0/cap_status.rs
+++ b/esp32p4/src/mcpwm0/cap_status.rs
@@ -27,18 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_STATUS")
-            .field("cap0_edge", &format_args!("{}", self.cap0_edge().bit()))
-            .field("cap1_edge", &format_args!("{}", self.cap1_edge().bit()))
-            .field("cap2_edge", &format_args!("{}", self.cap2_edge().bit()))
+            .field("cap0_edge", &self.cap0_edge())
+            .field("cap1_edge", &self.cap1_edge())
+            .field("cap2_edge", &self.cap2_edge())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Last capture trigger edge information register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CAP_STATUS_SPEC;
 impl crate::RegisterSpec for CAP_STATUS_SPEC {
diff --git a/esp32p4/src/mcpwm0/cap_timer_cfg.rs b/esp32p4/src/mcpwm0/cap_timer_cfg.rs
index 1986b97fd7..058c96f12d 100644
--- a/esp32p4/src/mcpwm0/cap_timer_cfg.rs
+++ b/esp32p4/src/mcpwm0/cap_timer_cfg.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_TIMER_CFG")
-            .field(
-                "cap_timer_en",
-                &format_args!("{}", self.cap_timer_en().bit()),
-            )
-            .field(
-                "cap_synci_en",
-                &format_args!("{}", self.cap_synci_en().bit()),
-            )
-            .field(
-                "cap_synci_sel",
-                &format_args!("{}", self.cap_synci_sel().bits()),
-            )
+            .field("cap_timer_en", &self.cap_timer_en())
+            .field("cap_synci_en", &self.cap_synci_en())
+            .field("cap_synci_sel", &self.cap_synci_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_TIMER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to enable capture timer increment.\\\\0: Disable\\\\1: Enable"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/cap_timer_phase.rs b/esp32p4/src/mcpwm0/cap_timer_phase.rs
index 7846289520..6a45236f7f 100644
--- a/esp32p4/src/mcpwm0/cap_timer_phase.rs
+++ b/esp32p4/src/mcpwm0/cap_timer_phase.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_TIMER_PHASE")
-            .field("cap_phase", &format_args!("{}", self.cap_phase().bits()))
+            .field("cap_phase", &self.cap_phase())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_TIMER_PHASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures phase value for capture timer sync operation."]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/ch/carrier_cfg.rs b/esp32p4/src/mcpwm0/ch/carrier_cfg.rs
index 284965a480..f9a6dbb5ea 100644
--- a/esp32p4/src/mcpwm0/ch/carrier_cfg.rs
+++ b/esp32p4/src/mcpwm0/ch/carrier_cfg.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CARRIER_CFG")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
-            .field("duty", &format_args!("{}", self.duty().bits()))
-            .field("oshtwth", &format_args!("{}", self.oshtwth().bits()))
-            .field("out_invert", &format_args!("{}", self.out_invert().bit()))
-            .field("in_invert", &format_args!("{}", self.in_invert().bit()))
+            .field("en", &self.en())
+            .field("prescale", &self.prescale())
+            .field("duty", &self.duty())
+            .field("oshtwth", &self.oshtwth())
+            .field("out_invert", &self.out_invert())
+            .field("in_invert", &self.in_invert())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CARRIER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to enable carrier%s.\\\\0: Bypassed\\\\1: Enabled"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/ch/dt_cfg.rs b/esp32p4/src/mcpwm0/ch/dt_cfg.rs
index b40359b687..ea428ac60d 100644
--- a/esp32p4/src/mcpwm0/ch/dt_cfg.rs
+++ b/esp32p4/src/mcpwm0/ch/dt_cfg.rs
@@ -116,39 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DT_CFG")
-            .field(
-                "fed_upmethod",
-                &format_args!("{}", self.fed_upmethod().bits()),
-            )
-            .field(
-                "red_upmethod",
-                &format_args!("{}", self.red_upmethod().bits()),
-            )
-            .field("deb_mode", &format_args!("{}", self.deb_mode().bit()))
-            .field("a_outswap", &format_args!("{}", self.a_outswap().bit()))
-            .field("b_outswap", &format_args!("{}", self.b_outswap().bit()))
-            .field("red_insel", &format_args!("{}", self.red_insel().bit()))
-            .field("fed_insel", &format_args!("{}", self.fed_insel().bit()))
-            .field(
-                "red_outinvert",
-                &format_args!("{}", self.red_outinvert().bit()),
-            )
-            .field(
-                "fed_outinvert",
-                &format_args!("{}", self.fed_outinvert().bit()),
-            )
-            .field("a_outbypass", &format_args!("{}", self.a_outbypass().bit()))
-            .field("b_outbypass", &format_args!("{}", self.b_outbypass().bit()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bit()))
+            .field("fed_upmethod", &self.fed_upmethod())
+            .field("red_upmethod", &self.red_upmethod())
+            .field("deb_mode", &self.deb_mode())
+            .field("a_outswap", &self.a_outswap())
+            .field("b_outswap", &self.b_outswap())
+            .field("red_insel", &self.red_insel())
+            .field("fed_insel", &self.fed_insel())
+            .field("red_outinvert", &self.red_outinvert())
+            .field("fed_outinvert", &self.fed_outinvert())
+            .field("a_outbypass", &self.a_outbypass())
+            .field("b_outbypass", &self.b_outbypass())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DT_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/ch/dt_fed_cfg.rs b/esp32p4/src/mcpwm0/ch/dt_fed_cfg.rs
index 2ebbae2fcf..c9fd24d929 100644
--- a/esp32p4/src/mcpwm0/ch/dt_fed_cfg.rs
+++ b/esp32p4/src/mcpwm0/ch/dt_fed_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DT_FED_CFG")
-            .field("fed", &format_args!("{}", self.fed().bits()))
+            .field("fed", &self.fed())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DT_FED_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures shadow register for FED."]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/ch/dt_red_cfg.rs b/esp32p4/src/mcpwm0/ch/dt_red_cfg.rs
index c0c2ff1cc7..1c14438a25 100644
--- a/esp32p4/src/mcpwm0/ch/dt_red_cfg.rs
+++ b/esp32p4/src/mcpwm0/ch/dt_red_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DT_RED_CFG")
-            .field("red", &format_args!("{}", self.red().bits()))
+            .field("red", &self.red())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DT_RED_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures shadow register for RED."]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/ch/fh_cfg0.rs b/esp32p4/src/mcpwm0/ch/fh_cfg0.rs
index eb6f0e8a2a..4ca12c6596 100644
--- a/esp32p4/src/mcpwm0/ch/fh_cfg0.rs
+++ b/esp32p4/src/mcpwm0/ch/fh_cfg0.rs
@@ -152,31 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FH_CFG0")
-            .field("sw_cbc", &format_args!("{}", self.sw_cbc().bit()))
-            .field("f2_cbc", &format_args!("{}", self.f2_cbc().bit()))
-            .field("f1_cbc", &format_args!("{}", self.f1_cbc().bit()))
-            .field("f0_cbc", &format_args!("{}", self.f0_cbc().bit()))
-            .field("sw_ost", &format_args!("{}", self.sw_ost().bit()))
-            .field("f2_ost", &format_args!("{}", self.f2_ost().bit()))
-            .field("f1_ost", &format_args!("{}", self.f1_ost().bit()))
-            .field("f0_ost", &format_args!("{}", self.f0_ost().bit()))
-            .field("a_cbc_d", &format_args!("{}", self.a_cbc_d().bits()))
-            .field("a_cbc_u", &format_args!("{}", self.a_cbc_u().bits()))
-            .field("a_ost_d", &format_args!("{}", self.a_ost_d().bits()))
-            .field("a_ost_u", &format_args!("{}", self.a_ost_u().bits()))
-            .field("b_cbc_d", &format_args!("{}", self.b_cbc_d().bits()))
-            .field("b_cbc_u", &format_args!("{}", self.b_cbc_u().bits()))
-            .field("b_ost_d", &format_args!("{}", self.b_ost_d().bits()))
-            .field("b_ost_u", &format_args!("{}", self.b_ost_u().bits()))
+            .field("sw_cbc", &self.sw_cbc())
+            .field("f2_cbc", &self.f2_cbc())
+            .field("f1_cbc", &self.f1_cbc())
+            .field("f0_cbc", &self.f0_cbc())
+            .field("sw_ost", &self.sw_ost())
+            .field("f2_ost", &self.f2_ost())
+            .field("f1_ost", &self.f1_ost())
+            .field("f0_ost", &self.f0_ost())
+            .field("a_cbc_d", &self.a_cbc_d())
+            .field("a_cbc_u", &self.a_cbc_u())
+            .field("a_ost_d", &self.a_ost_d())
+            .field("a_ost_u", &self.a_ost_u())
+            .field("b_cbc_d", &self.b_cbc_d())
+            .field("b_cbc_u", &self.b_cbc_u())
+            .field("b_ost_d", &self.b_ost_d())
+            .field("b_ost_u", &self.b_ost_u())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FH_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to enable software force cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/ch/fh_cfg1.rs b/esp32p4/src/mcpwm0/ch/fh_cfg1.rs
index 1b7b8ab8ab..ba50b40a4e 100644
--- a/esp32p4/src/mcpwm0/ch/fh_cfg1.rs
+++ b/esp32p4/src/mcpwm0/ch/fh_cfg1.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FH_CFG1")
-            .field("clr_ost", &format_args!("{}", self.clr_ost().bit()))
-            .field("cbcpulse", &format_args!("{}", self.cbcpulse().bits()))
-            .field("force_cbc", &format_args!("{}", self.force_cbc().bit()))
-            .field("force_ost", &format_args!("{}", self.force_ost().bit()))
+            .field("clr_ost", &self.clr_ost())
+            .field("cbcpulse", &self.cbcpulse())
+            .field("force_cbc", &self.force_cbc())
+            .field("force_ost", &self.force_ost())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FH_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action."]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/ch/fh_status.rs b/esp32p4/src/mcpwm0/ch/fh_status.rs
index dc84ac9ee3..47e74ec926 100644
--- a/esp32p4/src/mcpwm0/ch/fh_status.rs
+++ b/esp32p4/src/mcpwm0/ch/fh_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FH_STATUS")
-            .field("cbc_on", &format_args!("{}", self.cbc_on().bit()))
-            .field("ost_on", &format_args!("{}", self.ost_on().bit()))
+            .field("cbc_on", &self.cbc_on())
+            .field("ost_on", &self.ost_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FH_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Fault events status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fh_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FH_STATUS_SPEC;
 impl crate::RegisterSpec for FH_STATUS_SPEC {
diff --git a/esp32p4/src/mcpwm0/ch/gen.rs b/esp32p4/src/mcpwm0/ch/gen.rs
index 1aaf363758..40baba7d45 100644
--- a/esp32p4/src/mcpwm0/ch/gen.rs
+++ b/esp32p4/src/mcpwm0/ch/gen.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN")
-            .field("utez", &format_args!("{}", self.utez().bits()))
-            .field("utep", &format_args!("{}", self.utep().bits()))
-            .field("utea", &format_args!("{}", self.utea().bits()))
-            .field("uteb", &format_args!("{}", self.uteb().bits()))
-            .field("ut0", &format_args!("{}", self.ut0().bits()))
-            .field("ut1", &format_args!("{}", self.ut1().bits()))
-            .field("dtez", &format_args!("{}", self.dtez().bits()))
-            .field("dtep", &format_args!("{}", self.dtep().bits()))
-            .field("dtea", &format_args!("{}", self.dtea().bits()))
-            .field("dteb", &format_args!("{}", self.dteb().bits()))
-            .field("dt0", &format_args!("{}", self.dt0().bits()))
-            .field("dt1", &format_args!("{}", self.dt1().bits()))
+            .field("utez", &self.utez())
+            .field("utep", &self.utep())
+            .field("utea", &self.utea())
+            .field("uteb", &self.uteb())
+            .field("ut0", &self.ut0())
+            .field("ut1", &self.ut1())
+            .field("dtez", &self.dtez())
+            .field("dtep", &self.dtep())
+            .field("dtea", &self.dtea())
+            .field("dteb", &self.dteb())
+            .field("dt0", &self.dt0())
+            .field("dt1", &self.dt1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Configures action on PWM%s A triggered by event TEZ when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/ch/gen_cfg0.rs b/esp32p4/src/mcpwm0/ch/gen_cfg0.rs
index 138807d626..c0367f2a17 100644
--- a/esp32p4/src/mcpwm0/ch/gen_cfg0.rs
+++ b/esp32p4/src/mcpwm0/ch/gen_cfg0.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_CFG0")
-            .field(
-                "cfg_upmethod",
-                &format_args!("{}", self.cfg_upmethod().bits()),
-            )
-            .field("t0_sel", &format_args!("{}", self.t0_sel().bits()))
-            .field("t1_sel", &format_args!("{}", self.t1_sel().bits()))
+            .field("cfg_upmethod", &self.cfg_upmethod())
+            .field("t0_sel", &self.t0_sel())
+            .field("t1_sel", &self.t1_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Configures update method for PWM generator %s's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/ch/gen_force.rs b/esp32p4/src/mcpwm0/ch/gen_force.rs
index dacec5663c..05f10ad206 100644
--- a/esp32p4/src/mcpwm0/ch/gen_force.rs
+++ b/esp32p4/src/mcpwm0/ch/gen_force.rs
@@ -71,37 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_FORCE")
-            .field(
-                "cntuforce_upmethod",
-                &format_args!("{}", self.cntuforce_upmethod().bits()),
-            )
-            .field(
-                "a_cntuforce_mode",
-                &format_args!("{}", self.a_cntuforce_mode().bits()),
-            )
-            .field(
-                "b_cntuforce_mode",
-                &format_args!("{}", self.b_cntuforce_mode().bits()),
-            )
-            .field("a_nciforce", &format_args!("{}", self.a_nciforce().bit()))
-            .field(
-                "a_nciforce_mode",
-                &format_args!("{}", self.a_nciforce_mode().bits()),
-            )
-            .field("b_nciforce", &format_args!("{}", self.b_nciforce().bit()))
-            .field(
-                "b_nciforce_mode",
-                &format_args!("{}", self.b_nciforce_mode().bits()),
-            )
+            .field("cntuforce_upmethod", &self.cntuforce_upmethod())
+            .field("a_cntuforce_mode", &self.a_cntuforce_mode())
+            .field("b_cntuforce_mode", &self.b_cntuforce_mode())
+            .field("a_nciforce", &self.a_nciforce())
+            .field("a_nciforce_mode", &self.a_nciforce_mode())
+            .field("b_nciforce", &self.b_nciforce())
+            .field("b_nciforce_mode", &self.b_nciforce_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_FORCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Configures update method for continuous software force of PWM generator%s.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: TEA\\\\Bit3 is set to 1: TEB\\\\Bit4 is set to 1: Sync\\\\Bit5 is set to 1: Disable update. TEA/B here and below means an event generated when the timer's value equals to that of register A/B."]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/ch/gen_stmp_cfg.rs b/esp32p4/src/mcpwm0/ch/gen_stmp_cfg.rs
index 9f2eabbd91..8609c4e409 100644
--- a/esp32p4/src/mcpwm0/ch/gen_stmp_cfg.rs
+++ b/esp32p4/src/mcpwm0/ch/gen_stmp_cfg.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_STMP_CFG")
-            .field("a_upmethod", &format_args!("{}", self.a_upmethod().bits()))
-            .field("b_upmethod", &format_args!("{}", self.b_upmethod().bits()))
-            .field("a_shdw_full", &format_args!("{}", self.a_shdw_full().bit()))
-            .field("b_shdw_full", &format_args!("{}", self.b_shdw_full().bit()))
+            .field("a_upmethod", &self.a_upmethod())
+            .field("b_upmethod", &self.b_upmethod())
+            .field("a_shdw_full", &self.a_shdw_full())
+            .field("b_shdw_full", &self.b_shdw_full())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_STMP_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Configures the update method for PWM generator %s time stamp A's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/ch/gen_tstmp_a.rs b/esp32p4/src/mcpwm0/ch/gen_tstmp_a.rs
index 6f4cfe411a..2040ce8403 100644
--- a/esp32p4/src/mcpwm0/ch/gen_tstmp_a.rs
+++ b/esp32p4/src/mcpwm0/ch/gen_tstmp_a.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("GEN_TSTMP_A")
-            .field("a", &format_args!("{}", self.a().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_TSTMP_A_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("GEN_TSTMP_A").field("a", &self.a()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/mcpwm0/ch/gen_tstmp_b.rs b/esp32p4/src/mcpwm0/ch/gen_tstmp_b.rs
index 7e48408c0c..852ab775e9 100644
--- a/esp32p4/src/mcpwm0/ch/gen_tstmp_b.rs
+++ b/esp32p4/src/mcpwm0/ch/gen_tstmp_b.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("GEN_TSTMP_B")
-            .field("b", &format_args!("{}", self.b().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_TSTMP_B_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("GEN_TSTMP_B").field("b", &self.b()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/mcpwm0/clk.rs b/esp32p4/src/mcpwm0/clk.rs
index e331e29112..68d599e149 100644
--- a/esp32p4/src/mcpwm0/clk.rs
+++ b/esp32p4/src/mcpwm0/clk.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CLK")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CLK").field("en", &self.en()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/mcpwm0/clk_cfg.rs b/esp32p4/src/mcpwm0/clk_cfg.rs
index 08b8646de2..5ba9e3bec8 100644
--- a/esp32p4/src/mcpwm0/clk_cfg.rs
+++ b/esp32p4/src/mcpwm0/clk_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CFG")
-            .field(
-                "clk_prescale",
-                &format_args!("{}", self.clk_prescale().bits()),
-            )
+            .field("clk_prescale", &self.clk_prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)."]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/evt_en.rs b/esp32p4/src/mcpwm0/evt_en.rs
index e189af9c8b..b67706ea18 100644
--- a/esp32p4/src/mcpwm0/evt_en.rs
+++ b/esp32p4/src/mcpwm0/evt_en.rs
@@ -278,45 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVT_EN")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("op0_tea", &format_args!("{}", self.op0_tea().bit()))
-            .field("op1_tea", &format_args!("{}", self.op1_tea().bit()))
-            .field("op2_tea", &format_args!("{}", self.op2_tea().bit()))
-            .field("op0_teb", &format_args!("{}", self.op0_teb().bit()))
-            .field("op1_teb", &format_args!("{}", self.op1_teb().bit()))
-            .field("op2_teb", &format_args!("{}", self.op2_teb().bit()))
-            .field("f0", &format_args!("{}", self.f0().bit()))
-            .field("f1", &format_args!("{}", self.f1().bit()))
-            .field("f2", &format_args!("{}", self.f2().bit()))
-            .field("f0_clr", &format_args!("{}", self.f0_clr().bit()))
-            .field("f1_clr", &format_args!("{}", self.f1_clr().bit()))
-            .field("f2_clr", &format_args!("{}", self.f2_clr().bit()))
-            .field("tz0_cbc", &format_args!("{}", self.tz0_cbc().bit()))
-            .field("tz1_cbc", &format_args!("{}", self.tz1_cbc().bit()))
-            .field("tz2_cbc", &format_args!("{}", self.tz2_cbc().bit()))
-            .field("tz0_ost", &format_args!("{}", self.tz0_ost().bit()))
-            .field("tz1_ost", &format_args!("{}", self.tz1_ost().bit()))
-            .field("tz2_ost", &format_args!("{}", self.tz2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("op0_tea", &self.op0_tea())
+            .field("op1_tea", &self.op1_tea())
+            .field("op2_tea", &self.op2_tea())
+            .field("op0_teb", &self.op0_teb())
+            .field("op1_teb", &self.op1_teb())
+            .field("op2_teb", &self.op2_teb())
+            .field("f0", &self.f0())
+            .field("f1", &self.f1())
+            .field("f2", &self.f2())
+            .field("f0_clr", &self.f0_clr())
+            .field("f1_clr", &self.f1_clr())
+            .field("f2_clr", &self.f2_clr())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to enable timer0 stop event generate.\\\\0: Disable\\\\1: Enable"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/evt_en2.rs b/esp32p4/src/mcpwm0/evt_en2.rs
index cfcab92436..9582843515 100644
--- a/esp32p4/src/mcpwm0/evt_en2.rs
+++ b/esp32p4/src/mcpwm0/evt_en2.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVT_EN2")
-            .field("op0_tee1", &format_args!("{}", self.op0_tee1().bit()))
-            .field("op1_tee1", &format_args!("{}", self.op1_tee1().bit()))
-            .field("op2_tee1", &format_args!("{}", self.op2_tee1().bit()))
-            .field("op0_tee2", &format_args!("{}", self.op0_tee2().bit()))
-            .field("op1_tee2", &format_args!("{}", self.op1_tee2().bit()))
-            .field("op2_tee2", &format_args!("{}", self.op2_tee2().bit()))
+            .field("op0_tee1", &self.op0_tee1())
+            .field("op1_tee1", &self.op1_tee1())
+            .field("op2_tee1", &self.op2_tee1())
+            .field("op0_tee2", &self.op0_tee2())
+            .field("op1_tee2", &self.op1_tee2())
+            .field("op2_tee2", &self.op2_tee2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_EN2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/fault_detect.rs b/esp32p4/src/mcpwm0/fault_detect.rs
index 2b2226e9de..5e1a79cda9 100644
--- a/esp32p4/src/mcpwm0/fault_detect.rs
+++ b/esp32p4/src/mcpwm0/fault_detect.rs
@@ -83,24 +83,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FAULT_DETECT")
-            .field("f0_en", &format_args!("{}", self.f0_en().bit()))
-            .field("f1_en", &format_args!("{}", self.f1_en().bit()))
-            .field("f2_en", &format_args!("{}", self.f2_en().bit()))
-            .field("f0_pole", &format_args!("{}", self.f0_pole().bit()))
-            .field("f1_pole", &format_args!("{}", self.f1_pole().bit()))
-            .field("f2_pole", &format_args!("{}", self.f2_pole().bit()))
-            .field("event_f0", &format_args!("{}", self.event_f0().bit()))
-            .field("event_f1", &format_args!("{}", self.event_f1().bit()))
-            .field("event_f2", &format_args!("{}", self.event_f2().bit()))
+            .field("f0_en", &self.f0_en())
+            .field("f1_en", &self.f1_en())
+            .field("f2_en", &self.f2_en())
+            .field("f0_pole", &self.f0_pole())
+            .field("f1_pole", &self.f1_pole())
+            .field("f2_pole", &self.f2_pole())
+            .field("event_f0", &self.event_f0())
+            .field("event_f1", &self.event_f1())
+            .field("event_f2", &self.event_f2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FAULT_DETECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to enable event_f0 generation.\\\\0: Disable\\\\1: Enable"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/int_ena.rs b/esp32p4/src/mcpwm0/int_ena.rs
index e60364c508..13a6875833 100644
--- a/esp32p4/src/mcpwm0/int_ena.rs
+++ b/esp32p4/src/mcpwm0/int_ena.rs
@@ -278,45 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("fault0", &format_args!("{}", self.fault0().bit()))
-            .field("fault1", &format_args!("{}", self.fault1().bit()))
-            .field("fault2", &format_args!("{}", self.fault2().bit()))
-            .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
-            .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
-            .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
-            .field("cmpr0_tea", &format_args!("{}", self.cmpr0_tea().bit()))
-            .field("cmpr1_tea", &format_args!("{}", self.cmpr1_tea().bit()))
-            .field("cmpr2_tea", &format_args!("{}", self.cmpr2_tea().bit()))
-            .field("cmpr0_teb", &format_args!("{}", self.cmpr0_teb().bit()))
-            .field("cmpr1_teb", &format_args!("{}", self.cmpr1_teb().bit()))
-            .field("cmpr2_teb", &format_args!("{}", self.cmpr2_teb().bit()))
-            .field("tz0_cbc", &format_args!("{}", self.tz0_cbc().bit()))
-            .field("tz1_cbc", &format_args!("{}", self.tz1_cbc().bit()))
-            .field("tz2_cbc", &format_args!("{}", self.tz2_cbc().bit()))
-            .field("tz0_ost", &format_args!("{}", self.tz0_ost().bit()))
-            .field("tz1_ost", &format_args!("{}", self.tz1_ost().bit()))
-            .field("tz2_ost", &format_args!("{}", self.tz2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops."]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/int_raw.rs b/esp32p4/src/mcpwm0/int_raw.rs
index dfbcc698a7..15399dbb75 100644
--- a/esp32p4/src/mcpwm0/int_raw.rs
+++ b/esp32p4/src/mcpwm0/int_raw.rs
@@ -278,45 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("fault0", &format_args!("{}", self.fault0().bit()))
-            .field("fault1", &format_args!("{}", self.fault1().bit()))
-            .field("fault2", &format_args!("{}", self.fault2().bit()))
-            .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
-            .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
-            .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
-            .field("cmpr0_tea", &format_args!("{}", self.cmpr0_tea().bit()))
-            .field("cmpr1_tea", &format_args!("{}", self.cmpr1_tea().bit()))
-            .field("cmpr2_tea", &format_args!("{}", self.cmpr2_tea().bit()))
-            .field("cmpr0_teb", &format_args!("{}", self.cmpr0_teb().bit()))
-            .field("cmpr1_teb", &format_args!("{}", self.cmpr1_teb().bit()))
-            .field("cmpr2_teb", &format_args!("{}", self.cmpr2_teb().bit()))
-            .field("tz0_cbc", &format_args!("{}", self.tz0_cbc().bit()))
-            .field("tz1_cbc", &format_args!("{}", self.tz1_cbc().bit()))
-            .field("tz2_cbc", &format_args!("{}", self.tz2_cbc().bit()))
-            .field("tz0_ost", &format_args!("{}", self.tz0_ost().bit()))
-            .field("tz1_ost", &format_args!("{}", self.tz1_ost().bit()))
-            .field("tz2_ost", &format_args!("{}", self.tz2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops."]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/int_st.rs b/esp32p4/src/mcpwm0/int_st.rs
index da4f7a2167..7a46cef83d 100644
--- a/esp32p4/src/mcpwm0/int_st.rs
+++ b/esp32p4/src/mcpwm0/int_st.rs
@@ -216,45 +216,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("fault0", &format_args!("{}", self.fault0().bit()))
-            .field("fault1", &format_args!("{}", self.fault1().bit()))
-            .field("fault2", &format_args!("{}", self.fault2().bit()))
-            .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
-            .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
-            .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
-            .field("cmpr0_tea", &format_args!("{}", self.cmpr0_tea().bit()))
-            .field("cmpr1_tea", &format_args!("{}", self.cmpr1_tea().bit()))
-            .field("cmpr2_tea", &format_args!("{}", self.cmpr2_tea().bit()))
-            .field("cmpr0_teb", &format_args!("{}", self.cmpr0_teb().bit()))
-            .field("cmpr1_teb", &format_args!("{}", self.cmpr1_teb().bit()))
-            .field("cmpr2_teb", &format_args!("{}", self.cmpr2_teb().bit()))
-            .field("tz0_cbc", &format_args!("{}", self.tz0_cbc().bit()))
-            .field("tz1_cbc", &format_args!("{}", self.tz1_cbc().bit()))
-            .field("tz2_cbc", &format_args!("{}", self.tz2_cbc().bit()))
-            .field("tz0_ost", &format_args!("{}", self.tz0_ost().bit()))
-            .field("tz1_ost", &format_args!("{}", self.tz1_ost().bit()))
-            .field("tz2_ost", &format_args!("{}", self.tz2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt masked status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/mcpwm0/op_tstmp_e1.rs b/esp32p4/src/mcpwm0/op_tstmp_e1.rs
index 81098c043a..fd30b29a64 100644
--- a/esp32p4/src/mcpwm0/op_tstmp_e1.rs
+++ b/esp32p4/src/mcpwm0/op_tstmp_e1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OP_TSTMP_E1")
-            .field(
-                "op_tstmp_e1",
-                &format_args!("{}", self.op_tstmp_e1().bits()),
-            )
+            .field("op_tstmp_e1", &self.op_tstmp_e1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OP_TSTMP_E1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures generator%s timer stamp E1 value register"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/op_tstmp_e2.rs b/esp32p4/src/mcpwm0/op_tstmp_e2.rs
index d19515d0e6..1f163f1303 100644
--- a/esp32p4/src/mcpwm0/op_tstmp_e2.rs
+++ b/esp32p4/src/mcpwm0/op_tstmp_e2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OP_TSTMP_E2")
-            .field(
-                "op_tstmp_e2",
-                &format_args!("{}", self.op_tstmp_e2().bits()),
-            )
+            .field("op_tstmp_e2", &self.op_tstmp_e2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OP_TSTMP_E2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures generator%s timer stamp E2 value register"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/operator_timersel.rs b/esp32p4/src/mcpwm0/operator_timersel.rs
index c24c1848a8..90ef79ca33 100644
--- a/esp32p4/src/mcpwm0/operator_timersel.rs
+++ b/esp32p4/src/mcpwm0/operator_timersel.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OPERATOR_TIMERSEL")
-            .field(
-                "operator0_timersel",
-                &format_args!("{}", self.operator0_timersel().bits()),
-            )
-            .field(
-                "operator1_timersel",
-                &format_args!("{}", self.operator1_timersel().bits()),
-            )
-            .field(
-                "operator2_timersel",
-                &format_args!("{}", self.operator2_timersel().bits()),
-            )
+            .field("operator0_timersel", &self.operator0_timersel())
+            .field("operator1_timersel", &self.operator1_timersel())
+            .field("operator2_timersel", &self.operator2_timersel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OPERATOR_TIMERSEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Configures which PWM timer will be the timing reference for PWM operator0.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/task_en.rs b/esp32p4/src/mcpwm0/task_en.rs
index c678f11ef6..745ab63bec 100644
--- a/esp32p4/src/mcpwm0/task_en.rs
+++ b/esp32p4/src/mcpwm0/task_en.rs
@@ -206,46 +206,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TASK_EN")
-            .field("cmpr0_a_up", &format_args!("{}", self.cmpr0_a_up().bit()))
-            .field("cmpr1_a_up", &format_args!("{}", self.cmpr1_a_up().bit()))
-            .field("cmpr2_a_up", &format_args!("{}", self.cmpr2_a_up().bit()))
-            .field("cmpr0_b_up", &format_args!("{}", self.cmpr0_b_up().bit()))
-            .field("cmpr1_b_up", &format_args!("{}", self.cmpr1_b_up().bit()))
-            .field("cmpr2_b_up", &format_args!("{}", self.cmpr2_b_up().bit()))
-            .field("gen_stop", &format_args!("{}", self.gen_stop().bit()))
-            .field("timer0_sync", &format_args!("{}", self.timer0_sync().bit()))
-            .field("timer1_sync", &format_args!("{}", self.timer1_sync().bit()))
-            .field("timer2_sync", &format_args!("{}", self.timer2_sync().bit()))
-            .field(
-                "timer0_period_up",
-                &format_args!("{}", self.timer0_period_up().bit()),
-            )
-            .field(
-                "timer1_period_up",
-                &format_args!("{}", self.timer1_period_up().bit()),
-            )
-            .field(
-                "timer2_period_up",
-                &format_args!("{}", self.timer2_period_up().bit()),
-            )
-            .field("tz0_ost", &format_args!("{}", self.tz0_ost().bit()))
-            .field("tz1_ost", &format_args!("{}", self.tz1_ost().bit()))
-            .field("tz2_ost", &format_args!("{}", self.tz2_ost().bit()))
-            .field("clr0_ost", &format_args!("{}", self.clr0_ost().bit()))
-            .field("clr1_ost", &format_args!("{}", self.clr1_ost().bit()))
-            .field("clr2_ost", &format_args!("{}", self.clr2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("cmpr0_a_up", &self.cmpr0_a_up())
+            .field("cmpr1_a_up", &self.cmpr1_a_up())
+            .field("cmpr2_a_up", &self.cmpr2_a_up())
+            .field("cmpr0_b_up", &self.cmpr0_b_up())
+            .field("cmpr1_b_up", &self.cmpr1_b_up())
+            .field("cmpr2_b_up", &self.cmpr2_b_up())
+            .field("gen_stop", &self.gen_stop())
+            .field("timer0_sync", &self.timer0_sync())
+            .field("timer1_sync", &self.timer1_sync())
+            .field("timer2_sync", &self.timer2_sync())
+            .field("timer0_period_up", &self.timer0_period_up())
+            .field("timer1_period_up", &self.timer1_period_up())
+            .field("timer2_period_up", &self.timer2_period_up())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("clr0_ost", &self.clr0_ost())
+            .field("clr1_ost", &self.clr1_ost())
+            .field("clr2_ost", &self.clr2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TASK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to enable PWM generator0 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/timer/cfg0.rs b/esp32p4/src/mcpwm0/timer/cfg0.rs
index 42c3f9548a..e437973457 100644
--- a/esp32p4/src/mcpwm0/timer/cfg0.rs
+++ b/esp32p4/src/mcpwm0/timer/cfg0.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG0")
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
-            .field("period", &format_args!("{}", self.period().bits()))
-            .field(
-                "period_upmethod",
-                &format_args!("{}", self.period_upmethod().bits()),
-            )
+            .field("prescale", &self.prescale())
+            .field("period", &self.period())
+            .field("period_upmethod", &self.period_upmethod())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures the prescaler value of timer%s, so that the period of PT0_clk = Period of PWM_clk * (PWM_TIMER%s_PRESCALE + 1)"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/timer/cfg1.rs b/esp32p4/src/mcpwm0/timer/cfg1.rs
index 28b60f16ed..aa8697b09d 100644
--- a/esp32p4/src/mcpwm0/timer/cfg1.rs
+++ b/esp32p4/src/mcpwm0/timer/cfg1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG1")
-            .field("start", &format_args!("{}", self.start().bits()))
-            .field("mod_", &format_args!("{}", self.mod_().bits()))
+            .field("start", &self.start())
+            .field("mod_", &self.mod_())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Configures whether or not to start/stop PWM timer%s.\\\\0: If PWM timer%s starts, then stops at TEZ\\\\1: If timer%s starts, then stops at TEP\\\\2: PWM timer%s starts and runs on\\\\3: Timer%s starts and stops at the next TEZ\\\\4: Timer0 starts and stops at the next TEP.\\\\TEP here and below means the event that happens when the timer equals to period"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/timer/status.rs b/esp32p4/src/mcpwm0/timer/status.rs
index b1fef43731..6dc95e1a34 100644
--- a/esp32p4/src/mcpwm0/timer/status.rs
+++ b/esp32p4/src/mcpwm0/timer/status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("value", &format_args!("{}", self.value().bits()))
-            .field("direction", &format_args!("{}", self.direction().bit()))
+            .field("value", &self.value())
+            .field("direction", &self.direction())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "PWM timer0 status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32p4/src/mcpwm0/timer/sync.rs b/esp32p4/src/mcpwm0/timer/sync.rs
index e0a7388052..e357006335 100644
--- a/esp32p4/src/mcpwm0/timer/sync.rs
+++ b/esp32p4/src/mcpwm0/timer/sync.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYNC")
-            .field("synci_en", &format_args!("{}", self.synci_en().bit()))
-            .field("sw", &format_args!("{}", self.sw().bit()))
-            .field("synco_sel", &format_args!("{}", self.synco_sel().bits()))
-            .field("phase", &format_args!("{}", self.phase().bits()))
-            .field(
-                "phase_direction",
-                &format_args!("{}", self.phase_direction().bit()),
-            )
+            .field("synci_en", &self.synci_en())
+            .field("sw", &self.sw())
+            .field("synco_sel", &self.synco_sel())
+            .field("phase", &self.phase())
+            .field("phase_direction", &self.phase_direction())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to enable timer%s reloading with phase on sync input event is enabled.\\\\0: Disable\\\\1: Enable"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/timer_synci_cfg.rs b/esp32p4/src/mcpwm0/timer_synci_cfg.rs
index a63d088f16..9235e12dca 100644
--- a/esp32p4/src/mcpwm0/timer_synci_cfg.rs
+++ b/esp32p4/src/mcpwm0/timer_synci_cfg.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_SYNCI_CFG")
-            .field(
-                "timer0_syncisel",
-                &format_args!("{}", self.timer0_syncisel().bits()),
-            )
-            .field(
-                "timer1_syncisel",
-                &format_args!("{}", self.timer1_syncisel().bits()),
-            )
-            .field(
-                "timer2_syncisel",
-                &format_args!("{}", self.timer2_syncisel().bits()),
-            )
-            .field(
-                "external_synci0_invert",
-                &format_args!("{}", self.external_synci0_invert().bit()),
-            )
-            .field(
-                "external_synci1_invert",
-                &format_args!("{}", self.external_synci1_invert().bit()),
-            )
-            .field(
-                "external_synci2_invert",
-                &format_args!("{}", self.external_synci2_invert().bit()),
-            )
+            .field("timer0_syncisel", &self.timer0_syncisel())
+            .field("timer1_syncisel", &self.timer1_syncisel())
+            .field("timer2_syncisel", &self.timer2_syncisel())
+            .field("external_synci0_invert", &self.external_synci0_invert())
+            .field("external_synci1_invert", &self.external_synci1_invert())
+            .field("external_synci2_invert", &self.external_synci2_invert())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_SYNCI_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Configures the selection of sync input for PWM timer0.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/update_cfg.rs b/esp32p4/src/mcpwm0/update_cfg.rs
index 0317fe76c3..d8cb2739ba 100644
--- a/esp32p4/src/mcpwm0/update_cfg.rs
+++ b/esp32p4/src/mcpwm0/update_cfg.rs
@@ -80,38 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE_CFG")
-            .field(
-                "global_up_en",
-                &format_args!("{}", self.global_up_en().bit()),
-            )
-            .field(
-                "global_force_up",
-                &format_args!("{}", self.global_force_up().bit()),
-            )
-            .field("op0_up_en", &format_args!("{}", self.op0_up_en().bit()))
-            .field(
-                "op0_force_up",
-                &format_args!("{}", self.op0_force_up().bit()),
-            )
-            .field("op1_up_en", &format_args!("{}", self.op1_up_en().bit()))
-            .field(
-                "op1_force_up",
-                &format_args!("{}", self.op1_force_up().bit()),
-            )
-            .field("op2_up_en", &format_args!("{}", self.op2_up_en().bit()))
-            .field(
-                "op2_force_up",
-                &format_args!("{}", self.op2_force_up().bit()),
-            )
+            .field("global_up_en", &self.global_up_en())
+            .field("global_force_up", &self.global_force_up())
+            .field("op0_up_en", &self.op0_up_en())
+            .field("op0_force_up", &self.op0_force_up())
+            .field("op1_up_en", &self.op1_up_en())
+            .field("op1_force_up", &self.op1_force_up())
+            .field("op2_up_en", &self.op2_up_en())
+            .field("op2_force_up", &self.op2_force_up())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to enable global update for all active registers in MCPWM module.\\\\0: Disable\\\\1: Enable"]
     #[inline(always)]
diff --git a/esp32p4/src/mcpwm0/version.rs b/esp32p4/src/mcpwm0/version.rs
index d379ab9ef0..58b81c0916 100644
--- a/esp32p4/src/mcpwm0/version.rs
+++ b/esp32p4/src/mcpwm0/version.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Configures the version."]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/buf_flow_ctl.rs b/esp32p4/src/mipi_csi_bridge/buf_flow_ctl.rs
index af8d13c623..0181e30f13 100644
--- a/esp32p4/src/mipi_csi_bridge/buf_flow_ctl.rs
+++ b/esp32p4/src/mipi_csi_bridge/buf_flow_ctl.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUF_FLOW_CTL")
-            .field(
-                "csi_buf_afull_thrd",
-                &format_args!("{}", self.csi_buf_afull_thrd().bits()),
-            )
-            .field(
-                "csi_buf_depth",
-                &format_args!("{}", self.csi_buf_depth().bits()),
-            )
+            .field("csi_buf_afull_thrd", &self.csi_buf_afull_thrd())
+            .field("csi_buf_depth", &self.csi_buf_depth())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUF_FLOW_CTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - buffer almost full threshold."]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/clk_en.rs b/esp32p4/src/mipi_csi_bridge/clk_en.rs
index 6e5c350a4f..e86aa5a161 100644
--- a/esp32p4/src/mipi_csi_bridge/clk_en.rs
+++ b/esp32p4/src/mipi_csi_bridge/clk_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EN")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 0: enable clock gating. 1: disable clock gating, clock always on."]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/csi_en.rs b/esp32p4/src/mipi_csi_bridge/csi_en.rs
index e317854993..d6c616ddcc 100644
--- a/esp32p4/src/mipi_csi_bridge/csi_en.rs
+++ b/esp32p4/src/mipi_csi_bridge/csi_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CSI_EN")
-            .field("csi_brig_en", &format_args!("{}", self.csi_brig_en().bit()))
+            .field("csi_brig_en", &self.csi_brig_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CSI_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 0: disable csi bridge. 1: enable csi bridge."]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/data_type_cfg.rs b/esp32p4/src/mipi_csi_bridge/data_type_cfg.rs
index 8870cb9163..ed9dba81df 100644
--- a/esp32p4/src/mipi_csi_bridge/data_type_cfg.rs
+++ b/esp32p4/src/mipi_csi_bridge/data_type_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_TYPE_CFG")
-            .field(
-                "data_type_min",
-                &format_args!("{}", self.data_type_min().bits()),
-            )
-            .field(
-                "data_type_max",
-                &format_args!("{}", self.data_type_max().bits()),
-            )
+            .field("data_type_min", &self.data_type_min())
+            .field("data_type_max", &self.data_type_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_TYPE_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - the min value of data type used for pixel filter."]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/dma_req_cfg.rs b/esp32p4/src/mipi_csi_bridge/dma_req_cfg.rs
index 1e202087e5..c0c2894fa1 100644
--- a/esp32p4/src/mipi_csi_bridge/dma_req_cfg.rs
+++ b/esp32p4/src/mipi_csi_bridge/dma_req_cfg.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_REQ_CFG")
-            .field(
-                "dma_burst_len",
-                &format_args!("{}", self.dma_burst_len().bits()),
-            )
-            .field(
-                "dma_cfg_upd_by_blk",
-                &format_args!("{}", self.dma_cfg_upd_by_blk().bit()),
-            )
-            .field(
-                "dma_force_rd_status",
-                &format_args!("{}", self.dma_force_rd_status().bit()),
-            )
+            .field("dma_burst_len", &self.dma_burst_len())
+            .field("dma_cfg_upd_by_blk", &self.dma_cfg_upd_by_blk())
+            .field("dma_force_rd_status", &self.dma_force_rd_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_REQ_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - DMA burst length."]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/dma_req_interval.rs b/esp32p4/src/mipi_csi_bridge/dma_req_interval.rs
index 325d60208b..12647bfde6 100644
--- a/esp32p4/src/mipi_csi_bridge/dma_req_interval.rs
+++ b/esp32p4/src/mipi_csi_bridge/dma_req_interval.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_REQ_INTERVAL")
-            .field(
-                "dma_req_interval",
-                &format_args!("{}", self.dma_req_interval().bits()),
-            )
+            .field("dma_req_interval", &self.dma_req_interval())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_REQ_INTERVAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle."]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/dmablk_size.rs b/esp32p4/src/mipi_csi_bridge/dmablk_size.rs
index fc3956e5e6..81367c7dc3 100644
--- a/esp32p4/src/mipi_csi_bridge/dmablk_size.rs
+++ b/esp32p4/src/mipi_csi_bridge/dmablk_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMABLK_SIZE")
-            .field(
-                "dmablk_size",
-                &format_args!("{}", self.dmablk_size().bits()),
-            )
+            .field("dmablk_size", &self.dmablk_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMABLK_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - the number of reg_dma_burst_len in a block"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/endian_mode.rs b/esp32p4/src/mipi_csi_bridge/endian_mode.rs
index d18bcf022d..7498967897 100644
--- a/esp32p4/src/mipi_csi_bridge/endian_mode.rs
+++ b/esp32p4/src/mipi_csi_bridge/endian_mode.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENDIAN_MODE")
-            .field(
-                "byte_endian_order",
-                &format_args!("{}", self.byte_endian_order().bit()),
-            )
-            .field(
-                "bit_endian_order",
-                &format_args!("{}", self.bit_endian_order().bit()),
-            )
+            .field("byte_endian_order", &self.byte_endian_order())
+            .field("bit_endian_order", &self.bit_endian_order())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENDIAN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) when isp is bapassed."]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/frame_cfg.rs b/esp32p4/src/mipi_csi_bridge/frame_cfg.rs
index 31b2eb31f7..dc803e2989 100644
--- a/esp32p4/src/mipi_csi_bridge/frame_cfg.rs
+++ b/esp32p4/src/mipi_csi_bridge/frame_cfg.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FRAME_CFG")
-            .field("vadr_num", &format_args!("{}", self.vadr_num().bits()))
-            .field("hadr_num", &format_args!("{}", self.hadr_num().bits()))
-            .field("has_hsync_e", &format_args!("{}", self.has_hsync_e().bit()))
-            .field(
-                "vadr_num_check",
-                &format_args!("{}", self.vadr_num_check().bit()),
-            )
+            .field("vadr_num", &self.vadr_num())
+            .field("hadr_num", &self.hadr_num())
+            .field("has_hsync_e", &self.has_hsync_e())
+            .field("vadr_num_check", &self.vadr_num_check())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FRAME_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - vadr of frame data."]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/host_ctrl.rs b/esp32p4/src/mipi_csi_bridge/host_ctrl.rs
index 7beab938b2..e940fa2d51 100644
--- a/esp32p4/src/mipi_csi_bridge/host_ctrl.rs
+++ b/esp32p4/src/mipi_csi_bridge/host_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_CTRL")
-            .field(
-                "csi_enableclk",
-                &format_args!("{}", self.csi_enableclk().bit()),
-            )
-            .field(
-                "csi_cfg_clk_en",
-                &format_args!("{}", self.csi_cfg_clk_en().bit()),
-            )
-            .field(
-                "loopbk_test_en",
-                &format_args!("{}", self.loopbk_test_en().bit()),
-            )
+            .field("csi_enableclk", &self.csi_enableclk())
+            .field("csi_cfg_clk_en", &self.csi_cfg_clk_en())
+            .field("loopbk_test_en", &self.loopbk_test_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable clock lane module of csi phy."]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/int_ena.rs b/esp32p4/src/mipi_csi_bridge/int_ena.rs
index 56b00af99c..f6291256de 100644
--- a/esp32p4/src/mipi_csi_bridge/int_ena.rs
+++ b/esp32p4/src/mipi_csi_bridge/int_ena.rs
@@ -62,30 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("vadr_num_gt", &format_args!("{}", self.vadr_num_gt().bit()))
-            .field("vadr_num_lt", &format_args!("{}", self.vadr_num_lt().bit()))
-            .field("discard", &format_args!("{}", self.discard().bit()))
-            .field(
-                "csi_buf_overrun",
-                &format_args!("{}", self.csi_buf_overrun().bit()),
-            )
-            .field(
-                "csi_async_fifo_ovf",
-                &format_args!("{}", self.csi_async_fifo_ovf().bit()),
-            )
-            .field(
-                "dma_cfg_has_updated",
-                &format_args!("{}", self.dma_cfg_has_updated().bit()),
-            )
+            .field("vadr_num_gt", &self.vadr_num_gt())
+            .field("vadr_num_lt", &self.vadr_num_lt())
+            .field("discard", &self.discard())
+            .field("csi_buf_overrun", &self.csi_buf_overrun())
+            .field("csi_async_fifo_ovf", &self.csi_async_fifo_ovf())
+            .field("dma_cfg_has_updated", &self.dma_cfg_has_updated())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_vadr_num is greater than real interrupt enable."]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/int_raw.rs b/esp32p4/src/mipi_csi_bridge/int_raw.rs
index 0d53ec5ad7..429abdf506 100644
--- a/esp32p4/src/mipi_csi_bridge/int_raw.rs
+++ b/esp32p4/src/mipi_csi_bridge/int_raw.rs
@@ -62,30 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("vadr_num_gt", &format_args!("{}", self.vadr_num_gt().bit()))
-            .field("vadr_num_lt", &format_args!("{}", self.vadr_num_lt().bit()))
-            .field("discard", &format_args!("{}", self.discard().bit()))
-            .field(
-                "csi_buf_overrun",
-                &format_args!("{}", self.csi_buf_overrun().bit()),
-            )
-            .field(
-                "csi_async_fifo_ovf",
-                &format_args!("{}", self.csi_async_fifo_ovf().bit()),
-            )
-            .field(
-                "dma_cfg_has_updated",
-                &format_args!("{}", self.dma_cfg_has_updated().bit()),
-            )
+            .field("vadr_num_gt", &self.vadr_num_gt())
+            .field("vadr_num_lt", &self.vadr_num_lt())
+            .field("discard", &self.discard())
+            .field("csi_buf_overrun", &self.csi_buf_overrun())
+            .field("csi_async_fifo_ovf", &self.csi_async_fifo_ovf())
+            .field("dma_cfg_has_updated", &self.dma_cfg_has_updated())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - reg_vadr_num is greater than real interrupt raw."]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/int_st.rs b/esp32p4/src/mipi_csi_bridge/int_st.rs
index 1734659578..c00ffe7312 100644
--- a/esp32p4/src/mipi_csi_bridge/int_st.rs
+++ b/esp32p4/src/mipi_csi_bridge/int_st.rs
@@ -48,30 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("vadr_num_gt", &format_args!("{}", self.vadr_num_gt().bit()))
-            .field("vadr_num_lt", &format_args!("{}", self.vadr_num_lt().bit()))
-            .field("discard", &format_args!("{}", self.discard().bit()))
-            .field(
-                "csi_buf_overrun",
-                &format_args!("{}", self.csi_buf_overrun().bit()),
-            )
-            .field(
-                "csi_async_fifo_ovf",
-                &format_args!("{}", self.csi_async_fifo_ovf().bit()),
-            )
-            .field(
-                "dma_cfg_has_updated",
-                &format_args!("{}", self.dma_cfg_has_updated().bit()),
-            )
+            .field("vadr_num_gt", &self.vadr_num_gt())
+            .field("vadr_num_lt", &self.vadr_num_lt())
+            .field("discard", &self.discard())
+            .field("csi_buf_overrun", &self.csi_buf_overrun())
+            .field("csi_async_fifo_ovf", &self.csi_async_fifo_ovf())
+            .field("dma_cfg_has_updated", &self.dma_cfg_has_updated())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "csi bridge interrupt st.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/mipi_csi_bridge/mem_ctrl.rs b/esp32p4/src/mipi_csi_bridge/mem_ctrl.rs
index de26a1f29c..ed14153207 100644
--- a/esp32p4/src/mipi_csi_bridge/mem_ctrl.rs
+++ b/esp32p4/src/mipi_csi_bridge/mem_ctrl.rs
@@ -28,21 +28,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("MEM_CTRL")
             .field(
                 "csi_bridge_mem_clk_force_on",
-                &format_args!("{}", self.csi_bridge_mem_clk_force_on().bit()),
-            )
-            .field(
-                "csi_mem_aux_ctrl",
-                &format_args!("{}", self.csi_mem_aux_ctrl().bits()),
+                &self.csi_bridge_mem_clk_force_on(),
             )
+            .field("csi_mem_aux_ctrl", &self.csi_mem_aux_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - csi bridge memory clock gating force on."]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/rdn_eco_cs.rs b/esp32p4/src/mipi_csi_bridge/rdn_eco_cs.rs
index a74641196e..5e633f179d 100644
--- a/esp32p4/src/mipi_csi_bridge/rdn_eco_cs.rs
+++ b/esp32p4/src/mipi_csi_bridge/rdn_eco_cs.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDN_ECO_CS")
-            .field("rdn_eco_en", &format_args!("{}", self.rdn_eco_en().bit()))
-            .field(
-                "rdn_eco_result",
-                &format_args!("{}", self.rdn_eco_result().bit()),
-            )
+            .field("rdn_eco_en", &self.rdn_eco_en())
+            .field("rdn_eco_result", &self.rdn_eco_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDN_ECO_CS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/rdn_eco_high.rs b/esp32p4/src/mipi_csi_bridge/rdn_eco_high.rs
index a684acee8d..e7dd858391 100644
--- a/esp32p4/src/mipi_csi_bridge/rdn_eco_high.rs
+++ b/esp32p4/src/mipi_csi_bridge/rdn_eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDN_ECO_HIGH")
-            .field(
-                "rdn_eco_high",
-                &format_args!("{}", self.rdn_eco_high().bits()),
-            )
+            .field("rdn_eco_high", &self.rdn_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDN_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_bridge/rdn_eco_low.rs b/esp32p4/src/mipi_csi_bridge/rdn_eco_low.rs
index 6972c2dba0..bcf30a67b9 100644
--- a/esp32p4/src/mipi_csi_bridge/rdn_eco_low.rs
+++ b/esp32p4/src/mipi_csi_bridge/rdn_eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDN_ECO_LOW")
-            .field(
-                "rdn_eco_low",
-                &format_args!("{}", self.rdn_eco_low().bits()),
-            )
+            .field("rdn_eco_low", &self.rdn_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDN_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - N/A"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/csi2_resetn.rs b/esp32p4/src/mipi_csi_host/csi2_resetn.rs
index 15734214f5..17af5e5aa5 100644
--- a/esp32p4/src/mipi_csi_host/csi2_resetn.rs
+++ b/esp32p4/src/mipi_csi_host/csi2_resetn.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CSI2_RESETN")
-            .field("csi2_resetn", &format_args!("{}", self.csi2_resetn().bit()))
+            .field("csi2_resetn", &self.csi2_resetn())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CSI2_RESETN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/dphy_rstz.rs b/esp32p4/src/mipi_csi_host/dphy_rstz.rs
index 86de0c08e7..1b1315a664 100644
--- a/esp32p4/src/mipi_csi_host/dphy_rstz.rs
+++ b/esp32p4/src/mipi_csi_host/dphy_rstz.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPHY_RSTZ")
-            .field("dphy_rstz", &format_args!("{}", self.dphy_rstz().bit()))
+            .field("dphy_rstz", &self.dphy_rstz())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPHY_RSTZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_force_bndry_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_force_bndry_frame_fatal.rs
index e688a1d77c..0feea691d0 100644
--- a/esp32p4/src/mipi_csi_host/int_force_bndry_frame_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_force_bndry_frame_fatal.rs
@@ -154,77 +154,71 @@ impl core::fmt::Debug for R {
         f.debug_struct("INT_FORCE_BNDRY_FRAME_FATAL")
             .field(
                 "force_err_f_bndry_match_vc0",
-                &format_args!("{}", self.force_err_f_bndry_match_vc0().bit()),
+                &self.force_err_f_bndry_match_vc0(),
             )
             .field(
                 "force_err_f_bndry_match_vc1",
-                &format_args!("{}", self.force_err_f_bndry_match_vc1().bit()),
+                &self.force_err_f_bndry_match_vc1(),
             )
             .field(
                 "force_err_f_bndry_match_vc2",
-                &format_args!("{}", self.force_err_f_bndry_match_vc2().bit()),
+                &self.force_err_f_bndry_match_vc2(),
             )
             .field(
                 "force_err_f_bndry_match_vc3",
-                &format_args!("{}", self.force_err_f_bndry_match_vc3().bit()),
+                &self.force_err_f_bndry_match_vc3(),
             )
             .field(
                 "force_err_f_bndry_match_vc4",
-                &format_args!("{}", self.force_err_f_bndry_match_vc4().bit()),
+                &self.force_err_f_bndry_match_vc4(),
             )
             .field(
                 "force_err_f_bndry_match_vc5",
-                &format_args!("{}", self.force_err_f_bndry_match_vc5().bit()),
+                &self.force_err_f_bndry_match_vc5(),
             )
             .field(
                 "force_err_f_bndry_match_vc6",
-                &format_args!("{}", self.force_err_f_bndry_match_vc6().bit()),
+                &self.force_err_f_bndry_match_vc6(),
             )
             .field(
                 "force_err_f_bndry_match_vc7",
-                &format_args!("{}", self.force_err_f_bndry_match_vc7().bit()),
+                &self.force_err_f_bndry_match_vc7(),
             )
             .field(
                 "force_err_f_bndry_match_vc8",
-                &format_args!("{}", self.force_err_f_bndry_match_vc8().bit()),
+                &self.force_err_f_bndry_match_vc8(),
             )
             .field(
                 "force_err_f_bndry_match_vc9",
-                &format_args!("{}", self.force_err_f_bndry_match_vc9().bit()),
+                &self.force_err_f_bndry_match_vc9(),
             )
             .field(
                 "force_err_f_bndry_match_vc10",
-                &format_args!("{}", self.force_err_f_bndry_match_vc10().bit()),
+                &self.force_err_f_bndry_match_vc10(),
             )
             .field(
                 "force_err_f_bndry_match_vc11",
-                &format_args!("{}", self.force_err_f_bndry_match_vc11().bit()),
+                &self.force_err_f_bndry_match_vc11(),
             )
             .field(
                 "force_err_f_bndry_match_vc12",
-                &format_args!("{}", self.force_err_f_bndry_match_vc12().bit()),
+                &self.force_err_f_bndry_match_vc12(),
             )
             .field(
                 "force_err_f_bndry_match_vc13",
-                &format_args!("{}", self.force_err_f_bndry_match_vc13().bit()),
+                &self.force_err_f_bndry_match_vc13(),
             )
             .field(
                 "force_err_f_bndry_match_vc14",
-                &format_args!("{}", self.force_err_f_bndry_match_vc14().bit()),
+                &self.force_err_f_bndry_match_vc14(),
             )
             .field(
                 "force_err_f_bndry_match_vc15",
-                &format_args!("{}", self.force_err_f_bndry_match_vc15().bit()),
+                &self.force_err_f_bndry_match_vc15(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_FORCE_BNDRY_FRAME_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_force_crc_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_force_crc_frame_fatal.rs
index dadc2e6b6f..6ec041e5f9 100644
--- a/esp32p4/src/mipi_csi_host/int_force_crc_frame_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_force_crc_frame_fatal.rs
@@ -152,79 +152,43 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_FORCE_CRC_FRAME_FATAL")
-            .field(
-                "force_err_frame_data_vc0",
-                &format_args!("{}", self.force_err_frame_data_vc0().bit()),
-            )
-            .field(
-                "force_err_frame_data_vc1",
-                &format_args!("{}", self.force_err_frame_data_vc1().bit()),
-            )
-            .field(
-                "force_err_frame_data_vc2",
-                &format_args!("{}", self.force_err_frame_data_vc2().bit()),
-            )
-            .field(
-                "force_err_frame_data_vc3",
-                &format_args!("{}", self.force_err_frame_data_vc3().bit()),
-            )
-            .field(
-                "force_err_frame_data_vc4",
-                &format_args!("{}", self.force_err_frame_data_vc4().bit()),
-            )
-            .field(
-                "force_err_frame_data_vc5",
-                &format_args!("{}", self.force_err_frame_data_vc5().bit()),
-            )
-            .field(
-                "force_err_frame_data_vc6",
-                &format_args!("{}", self.force_err_frame_data_vc6().bit()),
-            )
-            .field(
-                "force_err_frame_data_vc7",
-                &format_args!("{}", self.force_err_frame_data_vc7().bit()),
-            )
-            .field(
-                "force_err_frame_data_vc8",
-                &format_args!("{}", self.force_err_frame_data_vc8().bit()),
-            )
-            .field(
-                "force_err_frame_data_vc9",
-                &format_args!("{}", self.force_err_frame_data_vc9().bit()),
-            )
+            .field("force_err_frame_data_vc0", &self.force_err_frame_data_vc0())
+            .field("force_err_frame_data_vc1", &self.force_err_frame_data_vc1())
+            .field("force_err_frame_data_vc2", &self.force_err_frame_data_vc2())
+            .field("force_err_frame_data_vc3", &self.force_err_frame_data_vc3())
+            .field("force_err_frame_data_vc4", &self.force_err_frame_data_vc4())
+            .field("force_err_frame_data_vc5", &self.force_err_frame_data_vc5())
+            .field("force_err_frame_data_vc6", &self.force_err_frame_data_vc6())
+            .field("force_err_frame_data_vc7", &self.force_err_frame_data_vc7())
+            .field("force_err_frame_data_vc8", &self.force_err_frame_data_vc8())
+            .field("force_err_frame_data_vc9", &self.force_err_frame_data_vc9())
             .field(
                 "force_err_frame_data_vc10",
-                &format_args!("{}", self.force_err_frame_data_vc10().bit()),
+                &self.force_err_frame_data_vc10(),
             )
             .field(
                 "force_err_frame_data_vc11",
-                &format_args!("{}", self.force_err_frame_data_vc11().bit()),
+                &self.force_err_frame_data_vc11(),
             )
             .field(
                 "force_err_frame_data_vc12",
-                &format_args!("{}", self.force_err_frame_data_vc12().bit()),
+                &self.force_err_frame_data_vc12(),
             )
             .field(
                 "force_err_frame_data_vc13",
-                &format_args!("{}", self.force_err_frame_data_vc13().bit()),
+                &self.force_err_frame_data_vc13(),
             )
             .field(
                 "force_err_frame_data_vc14",
-                &format_args!("{}", self.force_err_frame_data_vc14().bit()),
+                &self.force_err_frame_data_vc14(),
             )
             .field(
                 "force_err_frame_data_vc15",
-                &format_args!("{}", self.force_err_frame_data_vc15().bit()),
+                &self.force_err_frame_data_vc15(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_FORCE_CRC_FRAME_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_force_data_id.rs b/esp32p4/src/mipi_csi_host/int_force_data_id.rs
index 16e7c19714..79711ee6a4 100644
--- a/esp32p4/src/mipi_csi_host/int_force_data_id.rs
+++ b/esp32p4/src/mipi_csi_host/int_force_data_id.rs
@@ -152,79 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_FORCE_DATA_ID")
-            .field(
-                "force_err_id_vc0",
-                &format_args!("{}", self.force_err_id_vc0().bit()),
-            )
-            .field(
-                "force_err_id_vc1",
-                &format_args!("{}", self.force_err_id_vc1().bit()),
-            )
-            .field(
-                "force_err_id_vc2",
-                &format_args!("{}", self.force_err_id_vc2().bit()),
-            )
-            .field(
-                "force_err_id_vc3",
-                &format_args!("{}", self.force_err_id_vc3().bit()),
-            )
-            .field(
-                "force_err_id_vc4",
-                &format_args!("{}", self.force_err_id_vc4().bit()),
-            )
-            .field(
-                "force_err_id_vc5",
-                &format_args!("{}", self.force_err_id_vc5().bit()),
-            )
-            .field(
-                "force_err_id_vc6",
-                &format_args!("{}", self.force_err_id_vc6().bit()),
-            )
-            .field(
-                "force_err_id_vc7",
-                &format_args!("{}", self.force_err_id_vc7().bit()),
-            )
-            .field(
-                "force_err_id_vc8",
-                &format_args!("{}", self.force_err_id_vc8().bit()),
-            )
-            .field(
-                "force_err_id_vc9",
-                &format_args!("{}", self.force_err_id_vc9().bit()),
-            )
-            .field(
-                "force_err_id_vc10",
-                &format_args!("{}", self.force_err_id_vc10().bit()),
-            )
-            .field(
-                "force_err_id_vc11",
-                &format_args!("{}", self.force_err_id_vc11().bit()),
-            )
-            .field(
-                "force_err_id_vc12",
-                &format_args!("{}", self.force_err_id_vc12().bit()),
-            )
-            .field(
-                "force_err_id_vc13",
-                &format_args!("{}", self.force_err_id_vc13().bit()),
-            )
-            .field(
-                "force_err_id_vc14",
-                &format_args!("{}", self.force_err_id_vc14().bit()),
-            )
-            .field(
-                "force_err_id_vc15",
-                &format_args!("{}", self.force_err_id_vc15().bit()),
-            )
+            .field("force_err_id_vc0", &self.force_err_id_vc0())
+            .field("force_err_id_vc1", &self.force_err_id_vc1())
+            .field("force_err_id_vc2", &self.force_err_id_vc2())
+            .field("force_err_id_vc3", &self.force_err_id_vc3())
+            .field("force_err_id_vc4", &self.force_err_id_vc4())
+            .field("force_err_id_vc5", &self.force_err_id_vc5())
+            .field("force_err_id_vc6", &self.force_err_id_vc6())
+            .field("force_err_id_vc7", &self.force_err_id_vc7())
+            .field("force_err_id_vc8", &self.force_err_id_vc8())
+            .field("force_err_id_vc9", &self.force_err_id_vc9())
+            .field("force_err_id_vc10", &self.force_err_id_vc10())
+            .field("force_err_id_vc11", &self.force_err_id_vc11())
+            .field("force_err_id_vc12", &self.force_err_id_vc12())
+            .field("force_err_id_vc13", &self.force_err_id_vc13())
+            .field("force_err_id_vc14", &self.force_err_id_vc14())
+            .field("force_err_id_vc15", &self.force_err_id_vc15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_FORCE_DATA_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_force_ecc_corrected.rs b/esp32p4/src/mipi_csi_host/int_force_ecc_corrected.rs
index bfece93602..4e6e899838 100644
--- a/esp32p4/src/mipi_csi_host/int_force_ecc_corrected.rs
+++ b/esp32p4/src/mipi_csi_host/int_force_ecc_corrected.rs
@@ -154,77 +154,71 @@ impl core::fmt::Debug for R {
         f.debug_struct("INT_FORCE_ECC_CORRECTED")
             .field(
                 "force_err_ecc_corrected_vc0",
-                &format_args!("{}", self.force_err_ecc_corrected_vc0().bit()),
+                &self.force_err_ecc_corrected_vc0(),
             )
             .field(
                 "force_err_ecc_corrected_vc1",
-                &format_args!("{}", self.force_err_ecc_corrected_vc1().bit()),
+                &self.force_err_ecc_corrected_vc1(),
             )
             .field(
                 "force_err_ecc_corrected_vc2",
-                &format_args!("{}", self.force_err_ecc_corrected_vc2().bit()),
+                &self.force_err_ecc_corrected_vc2(),
             )
             .field(
                 "force_err_ecc_corrected_vc3",
-                &format_args!("{}", self.force_err_ecc_corrected_vc3().bit()),
+                &self.force_err_ecc_corrected_vc3(),
             )
             .field(
                 "force_err_ecc_corrected_vc4",
-                &format_args!("{}", self.force_err_ecc_corrected_vc4().bit()),
+                &self.force_err_ecc_corrected_vc4(),
             )
             .field(
                 "force_err_ecc_corrected_vc5",
-                &format_args!("{}", self.force_err_ecc_corrected_vc5().bit()),
+                &self.force_err_ecc_corrected_vc5(),
             )
             .field(
                 "force_err_ecc_corrected_vc6",
-                &format_args!("{}", self.force_err_ecc_corrected_vc6().bit()),
+                &self.force_err_ecc_corrected_vc6(),
             )
             .field(
                 "force_err_ecc_corrected_vc7",
-                &format_args!("{}", self.force_err_ecc_corrected_vc7().bit()),
+                &self.force_err_ecc_corrected_vc7(),
             )
             .field(
                 "force_err_ecc_corrected_vc8",
-                &format_args!("{}", self.force_err_ecc_corrected_vc8().bit()),
+                &self.force_err_ecc_corrected_vc8(),
             )
             .field(
                 "force_err_ecc_corrected_vc9",
-                &format_args!("{}", self.force_err_ecc_corrected_vc9().bit()),
+                &self.force_err_ecc_corrected_vc9(),
             )
             .field(
                 "force_err_ecc_corrected_vc10",
-                &format_args!("{}", self.force_err_ecc_corrected_vc10().bit()),
+                &self.force_err_ecc_corrected_vc10(),
             )
             .field(
                 "force_err_ecc_corrected_vc11",
-                &format_args!("{}", self.force_err_ecc_corrected_vc11().bit()),
+                &self.force_err_ecc_corrected_vc11(),
             )
             .field(
                 "force_err_ecc_corrected_vc12",
-                &format_args!("{}", self.force_err_ecc_corrected_vc12().bit()),
+                &self.force_err_ecc_corrected_vc12(),
             )
             .field(
                 "force_err_ecc_corrected_vc13",
-                &format_args!("{}", self.force_err_ecc_corrected_vc13().bit()),
+                &self.force_err_ecc_corrected_vc13(),
             )
             .field(
                 "force_err_ecc_corrected_vc14",
-                &format_args!("{}", self.force_err_ecc_corrected_vc14().bit()),
+                &self.force_err_ecc_corrected_vc14(),
             )
             .field(
                 "force_err_ecc_corrected_vc15",
-                &format_args!("{}", self.force_err_ecc_corrected_vc15().bit()),
+                &self.force_err_ecc_corrected_vc15(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_FORCE_ECC_CORRECTED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_force_phy.rs b/esp32p4/src/mipi_csi_host/int_force_phy.rs
index 1698dceb6e..9f1b3b53b9 100644
--- a/esp32p4/src/mipi_csi_host/int_force_phy.rs
+++ b/esp32p4/src/mipi_csi_host/int_force_phy.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_FORCE_PHY")
-            .field(
-                "force_phy_errsoths_0",
-                &format_args!("{}", self.force_phy_errsoths_0().bit()),
-            )
-            .field(
-                "force_phy_errsoths_1",
-                &format_args!("{}", self.force_phy_errsoths_1().bit()),
-            )
-            .field(
-                "force_phy_erresc_0",
-                &format_args!("{}", self.force_phy_erresc_0().bit()),
-            )
-            .field(
-                "force_phy_erresc_1",
-                &format_args!("{}", self.force_phy_erresc_1().bit()),
-            )
+            .field("force_phy_errsoths_0", &self.force_phy_errsoths_0())
+            .field("force_phy_errsoths_1", &self.force_phy_errsoths_1())
+            .field("force_phy_erresc_0", &self.force_phy_erresc_0())
+            .field("force_phy_erresc_1", &self.force_phy_erresc_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_FORCE_PHY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_force_phy_fatal.rs b/esp32p4/src/mipi_csi_host/int_force_phy_fatal.rs
index c1a0a42daf..0fc8a2bdb7 100644
--- a/esp32p4/src/mipi_csi_host/int_force_phy_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_force_phy_fatal.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_FORCE_PHY_FATAL")
-            .field(
-                "force_phy_errsotsynchs_0",
-                &format_args!("{}", self.force_phy_errsotsynchs_0().bit()),
-            )
-            .field(
-                "force_phy_errsotsynchs_1",
-                &format_args!("{}", self.force_phy_errsotsynchs_1().bit()),
-            )
+            .field("force_phy_errsotsynchs_0", &self.force_phy_errsotsynchs_0())
+            .field("force_phy_errsotsynchs_1", &self.force_phy_errsotsynchs_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_FORCE_PHY_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_force_pkt_fatal.rs b/esp32p4/src/mipi_csi_host/int_force_pkt_fatal.rs
index 979340e6c4..98ccf65799 100644
--- a/esp32p4/src/mipi_csi_host/int_force_pkt_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_force_pkt_fatal.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_FORCE_PKT_FATAL")
-            .field(
-                "force_err_ecc_double",
-                &format_args!("{}", self.force_err_ecc_double().bit()),
-            )
-            .field(
-                "force_shorter_payload",
-                &format_args!("{}", self.force_shorter_payload().bit()),
-            )
+            .field("force_err_ecc_double", &self.force_err_ecc_double())
+            .field("force_shorter_payload", &self.force_shorter_payload())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_FORCE_PKT_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_force_pld_crc_fatal.rs b/esp32p4/src/mipi_csi_host/int_force_pld_crc_fatal.rs
index 9b761ca9a6..4614281230 100644
--- a/esp32p4/src/mipi_csi_host/int_force_pld_crc_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_force_pld_crc_fatal.rs
@@ -152,79 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_FORCE_PLD_CRC_FATAL")
-            .field(
-                "force_err_crc_vc0",
-                &format_args!("{}", self.force_err_crc_vc0().bit()),
-            )
-            .field(
-                "force_err_crc_vc1",
-                &format_args!("{}", self.force_err_crc_vc1().bit()),
-            )
-            .field(
-                "force_err_crc_vc2",
-                &format_args!("{}", self.force_err_crc_vc2().bit()),
-            )
-            .field(
-                "force_err_crc_vc3",
-                &format_args!("{}", self.force_err_crc_vc3().bit()),
-            )
-            .field(
-                "force_err_crc_vc4",
-                &format_args!("{}", self.force_err_crc_vc4().bit()),
-            )
-            .field(
-                "force_err_crc_vc5",
-                &format_args!("{}", self.force_err_crc_vc5().bit()),
-            )
-            .field(
-                "force_err_crc_vc6",
-                &format_args!("{}", self.force_err_crc_vc6().bit()),
-            )
-            .field(
-                "force_err_crc_vc7",
-                &format_args!("{}", self.force_err_crc_vc7().bit()),
-            )
-            .field(
-                "force_err_crc_vc8",
-                &format_args!("{}", self.force_err_crc_vc8().bit()),
-            )
-            .field(
-                "force_err_crc_vc9",
-                &format_args!("{}", self.force_err_crc_vc9().bit()),
-            )
-            .field(
-                "force_err_crc_vc10",
-                &format_args!("{}", self.force_err_crc_vc10().bit()),
-            )
-            .field(
-                "force_err_crc_vc11",
-                &format_args!("{}", self.force_err_crc_vc11().bit()),
-            )
-            .field(
-                "force_err_crc_vc12",
-                &format_args!("{}", self.force_err_crc_vc12().bit()),
-            )
-            .field(
-                "force_err_crc_vc13",
-                &format_args!("{}", self.force_err_crc_vc13().bit()),
-            )
-            .field(
-                "force_err_crc_vc14",
-                &format_args!("{}", self.force_err_crc_vc14().bit()),
-            )
-            .field(
-                "force_err_crc_vc15",
-                &format_args!("{}", self.force_err_crc_vc15().bit()),
-            )
+            .field("force_err_crc_vc0", &self.force_err_crc_vc0())
+            .field("force_err_crc_vc1", &self.force_err_crc_vc1())
+            .field("force_err_crc_vc2", &self.force_err_crc_vc2())
+            .field("force_err_crc_vc3", &self.force_err_crc_vc3())
+            .field("force_err_crc_vc4", &self.force_err_crc_vc4())
+            .field("force_err_crc_vc5", &self.force_err_crc_vc5())
+            .field("force_err_crc_vc6", &self.force_err_crc_vc6())
+            .field("force_err_crc_vc7", &self.force_err_crc_vc7())
+            .field("force_err_crc_vc8", &self.force_err_crc_vc8())
+            .field("force_err_crc_vc9", &self.force_err_crc_vc9())
+            .field("force_err_crc_vc10", &self.force_err_crc_vc10())
+            .field("force_err_crc_vc11", &self.force_err_crc_vc11())
+            .field("force_err_crc_vc12", &self.force_err_crc_vc12())
+            .field("force_err_crc_vc13", &self.force_err_crc_vc13())
+            .field("force_err_crc_vc14", &self.force_err_crc_vc14())
+            .field("force_err_crc_vc15", &self.force_err_crc_vc15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_FORCE_PLD_CRC_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_force_seq_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_force_seq_frame_fatal.rs
index 9bd53ca799..5c29ff8507 100644
--- a/esp32p4/src/mipi_csi_host/int_force_seq_frame_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_force_seq_frame_fatal.rs
@@ -152,79 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_FORCE_SEQ_FRAME_FATAL")
-            .field(
-                "force_err_f_seq_vc0",
-                &format_args!("{}", self.force_err_f_seq_vc0().bit()),
-            )
-            .field(
-                "force_err_f_seq_vc1",
-                &format_args!("{}", self.force_err_f_seq_vc1().bit()),
-            )
-            .field(
-                "force_err_f_seq_vc2",
-                &format_args!("{}", self.force_err_f_seq_vc2().bit()),
-            )
-            .field(
-                "force_err_f_seq_vc3",
-                &format_args!("{}", self.force_err_f_seq_vc3().bit()),
-            )
-            .field(
-                "force_err_f_seq_vc4",
-                &format_args!("{}", self.force_err_f_seq_vc4().bit()),
-            )
-            .field(
-                "force_err_f_seq_vc5",
-                &format_args!("{}", self.force_err_f_seq_vc5().bit()),
-            )
-            .field(
-                "force_err_f_seq_vc6",
-                &format_args!("{}", self.force_err_f_seq_vc6().bit()),
-            )
-            .field(
-                "force_err_f_seq_vc7",
-                &format_args!("{}", self.force_err_f_seq_vc7().bit()),
-            )
-            .field(
-                "force_err_f_seq_vc8",
-                &format_args!("{}", self.force_err_f_seq_vc8().bit()),
-            )
-            .field(
-                "force_err_f_seq_vc9",
-                &format_args!("{}", self.force_err_f_seq_vc9().bit()),
-            )
-            .field(
-                "force_err_f_seq_vc10",
-                &format_args!("{}", self.force_err_f_seq_vc10().bit()),
-            )
-            .field(
-                "force_err_f_seq_vc11",
-                &format_args!("{}", self.force_err_f_seq_vc11().bit()),
-            )
-            .field(
-                "force_err_f_seq_vc12",
-                &format_args!("{}", self.force_err_f_seq_vc12().bit()),
-            )
-            .field(
-                "force_err_f_seq_vc13",
-                &format_args!("{}", self.force_err_f_seq_vc13().bit()),
-            )
-            .field(
-                "force_err_f_seq_vc14",
-                &format_args!("{}", self.force_err_f_seq_vc14().bit()),
-            )
-            .field(
-                "force_err_f_seq_vc15",
-                &format_args!("{}", self.force_err_f_seq_vc15().bit()),
-            )
+            .field("force_err_f_seq_vc0", &self.force_err_f_seq_vc0())
+            .field("force_err_f_seq_vc1", &self.force_err_f_seq_vc1())
+            .field("force_err_f_seq_vc2", &self.force_err_f_seq_vc2())
+            .field("force_err_f_seq_vc3", &self.force_err_f_seq_vc3())
+            .field("force_err_f_seq_vc4", &self.force_err_f_seq_vc4())
+            .field("force_err_f_seq_vc5", &self.force_err_f_seq_vc5())
+            .field("force_err_f_seq_vc6", &self.force_err_f_seq_vc6())
+            .field("force_err_f_seq_vc7", &self.force_err_f_seq_vc7())
+            .field("force_err_f_seq_vc8", &self.force_err_f_seq_vc8())
+            .field("force_err_f_seq_vc9", &self.force_err_f_seq_vc9())
+            .field("force_err_f_seq_vc10", &self.force_err_f_seq_vc10())
+            .field("force_err_f_seq_vc11", &self.force_err_f_seq_vc11())
+            .field("force_err_f_seq_vc12", &self.force_err_f_seq_vc12())
+            .field("force_err_f_seq_vc13", &self.force_err_f_seq_vc13())
+            .field("force_err_f_seq_vc14", &self.force_err_f_seq_vc14())
+            .field("force_err_f_seq_vc15", &self.force_err_f_seq_vc15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_FORCE_SEQ_FRAME_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_msk_bndry_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_msk_bndry_frame_fatal.rs
index 8185e7eba1..380a14929d 100644
--- a/esp32p4/src/mipi_csi_host/int_msk_bndry_frame_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_msk_bndry_frame_fatal.rs
@@ -154,77 +154,71 @@ impl core::fmt::Debug for R {
         f.debug_struct("INT_MSK_BNDRY_FRAME_FATAL")
             .field(
                 "mask_err_f_bndry_match_vc0",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc0().bit()),
+                &self.mask_err_f_bndry_match_vc0(),
             )
             .field(
                 "mask_err_f_bndry_match_vc1",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc1().bit()),
+                &self.mask_err_f_bndry_match_vc1(),
             )
             .field(
                 "mask_err_f_bndry_match_vc2",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc2().bit()),
+                &self.mask_err_f_bndry_match_vc2(),
             )
             .field(
                 "mask_err_f_bndry_match_vc3",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc3().bit()),
+                &self.mask_err_f_bndry_match_vc3(),
             )
             .field(
                 "mask_err_f_bndry_match_vc4",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc4().bit()),
+                &self.mask_err_f_bndry_match_vc4(),
             )
             .field(
                 "mask_err_f_bndry_match_vc5",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc5().bit()),
+                &self.mask_err_f_bndry_match_vc5(),
             )
             .field(
                 "mask_err_f_bndry_match_vc6",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc6().bit()),
+                &self.mask_err_f_bndry_match_vc6(),
             )
             .field(
                 "mask_err_f_bndry_match_vc7",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc7().bit()),
+                &self.mask_err_f_bndry_match_vc7(),
             )
             .field(
                 "mask_err_f_bndry_match_vc8",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc8().bit()),
+                &self.mask_err_f_bndry_match_vc8(),
             )
             .field(
                 "mask_err_f_bndry_match_vc9",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc9().bit()),
+                &self.mask_err_f_bndry_match_vc9(),
             )
             .field(
                 "mask_err_f_bndry_match_vc10",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc10().bit()),
+                &self.mask_err_f_bndry_match_vc10(),
             )
             .field(
                 "mask_err_f_bndry_match_vc11",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc11().bit()),
+                &self.mask_err_f_bndry_match_vc11(),
             )
             .field(
                 "mask_err_f_bndry_match_vc12",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc12().bit()),
+                &self.mask_err_f_bndry_match_vc12(),
             )
             .field(
                 "mask_err_f_bndry_match_vc13",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc13().bit()),
+                &self.mask_err_f_bndry_match_vc13(),
             )
             .field(
                 "mask_err_f_bndry_match_vc14",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc14().bit()),
+                &self.mask_err_f_bndry_match_vc14(),
             )
             .field(
                 "mask_err_f_bndry_match_vc15",
-                &format_args!("{}", self.mask_err_f_bndry_match_vc15().bit()),
+                &self.mask_err_f_bndry_match_vc15(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_MSK_BNDRY_FRAME_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_msk_crc_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_msk_crc_frame_fatal.rs
index bf5ebb781d..eb228609f8 100644
--- a/esp32p4/src/mipi_csi_host/int_msk_crc_frame_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_msk_crc_frame_fatal.rs
@@ -152,79 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_MSK_CRC_FRAME_FATAL")
-            .field(
-                "mask_err_frame_data_vc0",
-                &format_args!("{}", self.mask_err_frame_data_vc0().bit()),
-            )
-            .field(
-                "mask_err_frame_data_vc1",
-                &format_args!("{}", self.mask_err_frame_data_vc1().bit()),
-            )
-            .field(
-                "mask_err_frame_data_vc2",
-                &format_args!("{}", self.mask_err_frame_data_vc2().bit()),
-            )
-            .field(
-                "mask_err_frame_data_vc3",
-                &format_args!("{}", self.mask_err_frame_data_vc3().bit()),
-            )
-            .field(
-                "mask_err_frame_data_vc4",
-                &format_args!("{}", self.mask_err_frame_data_vc4().bit()),
-            )
-            .field(
-                "mask_err_frame_data_vc5",
-                &format_args!("{}", self.mask_err_frame_data_vc5().bit()),
-            )
-            .field(
-                "mask_err_frame_data_vc6",
-                &format_args!("{}", self.mask_err_frame_data_vc6().bit()),
-            )
-            .field(
-                "mask_err_frame_data_vc7",
-                &format_args!("{}", self.mask_err_frame_data_vc7().bit()),
-            )
-            .field(
-                "mask_err_frame_data_vc8",
-                &format_args!("{}", self.mask_err_frame_data_vc8().bit()),
-            )
-            .field(
-                "mask_err_frame_data_vc9",
-                &format_args!("{}", self.mask_err_frame_data_vc9().bit()),
-            )
-            .field(
-                "mask_err_frame_data_vc10",
-                &format_args!("{}", self.mask_err_frame_data_vc10().bit()),
-            )
-            .field(
-                "mask_err_frame_data_vc11",
-                &format_args!("{}", self.mask_err_frame_data_vc11().bit()),
-            )
-            .field(
-                "mask_err_frame_data_vc12",
-                &format_args!("{}", self.mask_err_frame_data_vc12().bit()),
-            )
-            .field(
-                "mask_err_frame_data_vc13",
-                &format_args!("{}", self.mask_err_frame_data_vc13().bit()),
-            )
-            .field(
-                "mask_err_frame_data_vc14",
-                &format_args!("{}", self.mask_err_frame_data_vc14().bit()),
-            )
-            .field(
-                "mask_err_frame_data_vc15",
-                &format_args!("{}", self.mask_err_frame_data_vc15().bit()),
-            )
+            .field("mask_err_frame_data_vc0", &self.mask_err_frame_data_vc0())
+            .field("mask_err_frame_data_vc1", &self.mask_err_frame_data_vc1())
+            .field("mask_err_frame_data_vc2", &self.mask_err_frame_data_vc2())
+            .field("mask_err_frame_data_vc3", &self.mask_err_frame_data_vc3())
+            .field("mask_err_frame_data_vc4", &self.mask_err_frame_data_vc4())
+            .field("mask_err_frame_data_vc5", &self.mask_err_frame_data_vc5())
+            .field("mask_err_frame_data_vc6", &self.mask_err_frame_data_vc6())
+            .field("mask_err_frame_data_vc7", &self.mask_err_frame_data_vc7())
+            .field("mask_err_frame_data_vc8", &self.mask_err_frame_data_vc8())
+            .field("mask_err_frame_data_vc9", &self.mask_err_frame_data_vc9())
+            .field("mask_err_frame_data_vc10", &self.mask_err_frame_data_vc10())
+            .field("mask_err_frame_data_vc11", &self.mask_err_frame_data_vc11())
+            .field("mask_err_frame_data_vc12", &self.mask_err_frame_data_vc12())
+            .field("mask_err_frame_data_vc13", &self.mask_err_frame_data_vc13())
+            .field("mask_err_frame_data_vc14", &self.mask_err_frame_data_vc14())
+            .field("mask_err_frame_data_vc15", &self.mask_err_frame_data_vc15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_MSK_CRC_FRAME_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_msk_data_id.rs b/esp32p4/src/mipi_csi_host/int_msk_data_id.rs
index 624f89ec9a..13e40d9e01 100644
--- a/esp32p4/src/mipi_csi_host/int_msk_data_id.rs
+++ b/esp32p4/src/mipi_csi_host/int_msk_data_id.rs
@@ -152,79 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_MSK_DATA_ID")
-            .field(
-                "mask_err_id_vc0",
-                &format_args!("{}", self.mask_err_id_vc0().bit()),
-            )
-            .field(
-                "mask_err_id_vc1",
-                &format_args!("{}", self.mask_err_id_vc1().bit()),
-            )
-            .field(
-                "mask_err_id_vc2",
-                &format_args!("{}", self.mask_err_id_vc2().bit()),
-            )
-            .field(
-                "mask_err_id_vc3",
-                &format_args!("{}", self.mask_err_id_vc3().bit()),
-            )
-            .field(
-                "mask_err_id_vc4",
-                &format_args!("{}", self.mask_err_id_vc4().bit()),
-            )
-            .field(
-                "mask_err_id_vc5",
-                &format_args!("{}", self.mask_err_id_vc5().bit()),
-            )
-            .field(
-                "mask_err_id_vc6",
-                &format_args!("{}", self.mask_err_id_vc6().bit()),
-            )
-            .field(
-                "mask_err_id_vc7",
-                &format_args!("{}", self.mask_err_id_vc7().bit()),
-            )
-            .field(
-                "mask_err_id_vc8",
-                &format_args!("{}", self.mask_err_id_vc8().bit()),
-            )
-            .field(
-                "mask_err_id_vc9",
-                &format_args!("{}", self.mask_err_id_vc9().bit()),
-            )
-            .field(
-                "mask_err_id_vc10",
-                &format_args!("{}", self.mask_err_id_vc10().bit()),
-            )
-            .field(
-                "mask_err_id_vc11",
-                &format_args!("{}", self.mask_err_id_vc11().bit()),
-            )
-            .field(
-                "mask_err_id_vc12",
-                &format_args!("{}", self.mask_err_id_vc12().bit()),
-            )
-            .field(
-                "mask_err_id_vc13",
-                &format_args!("{}", self.mask_err_id_vc13().bit()),
-            )
-            .field(
-                "mask_err_id_vc14",
-                &format_args!("{}", self.mask_err_id_vc14().bit()),
-            )
-            .field(
-                "mask_err_id_vc15",
-                &format_args!("{}", self.mask_err_id_vc15().bit()),
-            )
+            .field("mask_err_id_vc0", &self.mask_err_id_vc0())
+            .field("mask_err_id_vc1", &self.mask_err_id_vc1())
+            .field("mask_err_id_vc2", &self.mask_err_id_vc2())
+            .field("mask_err_id_vc3", &self.mask_err_id_vc3())
+            .field("mask_err_id_vc4", &self.mask_err_id_vc4())
+            .field("mask_err_id_vc5", &self.mask_err_id_vc5())
+            .field("mask_err_id_vc6", &self.mask_err_id_vc6())
+            .field("mask_err_id_vc7", &self.mask_err_id_vc7())
+            .field("mask_err_id_vc8", &self.mask_err_id_vc8())
+            .field("mask_err_id_vc9", &self.mask_err_id_vc9())
+            .field("mask_err_id_vc10", &self.mask_err_id_vc10())
+            .field("mask_err_id_vc11", &self.mask_err_id_vc11())
+            .field("mask_err_id_vc12", &self.mask_err_id_vc12())
+            .field("mask_err_id_vc13", &self.mask_err_id_vc13())
+            .field("mask_err_id_vc14", &self.mask_err_id_vc14())
+            .field("mask_err_id_vc15", &self.mask_err_id_vc15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_MSK_DATA_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_msk_ecc_corrected.rs b/esp32p4/src/mipi_csi_host/int_msk_ecc_corrected.rs
index 9896d23bf4..b42d01fc86 100644
--- a/esp32p4/src/mipi_csi_host/int_msk_ecc_corrected.rs
+++ b/esp32p4/src/mipi_csi_host/int_msk_ecc_corrected.rs
@@ -154,77 +154,71 @@ impl core::fmt::Debug for R {
         f.debug_struct("INT_MSK_ECC_CORRECTED")
             .field(
                 "mask_err_ecc_corrected_vc0",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc0().bit()),
+                &self.mask_err_ecc_corrected_vc0(),
             )
             .field(
                 "mask_err_ecc_corrected_vc1",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc1().bit()),
+                &self.mask_err_ecc_corrected_vc1(),
             )
             .field(
                 "mask_err_ecc_corrected_vc2",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc2().bit()),
+                &self.mask_err_ecc_corrected_vc2(),
             )
             .field(
                 "mask_err_ecc_corrected_vc3",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc3().bit()),
+                &self.mask_err_ecc_corrected_vc3(),
             )
             .field(
                 "mask_err_ecc_corrected_vc4",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc4().bit()),
+                &self.mask_err_ecc_corrected_vc4(),
             )
             .field(
                 "mask_err_ecc_corrected_vc5",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc5().bit()),
+                &self.mask_err_ecc_corrected_vc5(),
             )
             .field(
                 "mask_err_ecc_corrected_vc6",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc6().bit()),
+                &self.mask_err_ecc_corrected_vc6(),
             )
             .field(
                 "mask_err_ecc_corrected_vc7",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc7().bit()),
+                &self.mask_err_ecc_corrected_vc7(),
             )
             .field(
                 "mask_err_ecc_corrected_vc8",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc8().bit()),
+                &self.mask_err_ecc_corrected_vc8(),
             )
             .field(
                 "mask_err_ecc_corrected_vc9",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc9().bit()),
+                &self.mask_err_ecc_corrected_vc9(),
             )
             .field(
                 "mask_err_ecc_corrected_vc10",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc10().bit()),
+                &self.mask_err_ecc_corrected_vc10(),
             )
             .field(
                 "mask_err_ecc_corrected_vc11",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc11().bit()),
+                &self.mask_err_ecc_corrected_vc11(),
             )
             .field(
                 "mask_err_ecc_corrected_vc12",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc12().bit()),
+                &self.mask_err_ecc_corrected_vc12(),
             )
             .field(
                 "mask_err_ecc_corrected_vc13",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc13().bit()),
+                &self.mask_err_ecc_corrected_vc13(),
             )
             .field(
                 "mask_err_ecc_corrected_vc14",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc14().bit()),
+                &self.mask_err_ecc_corrected_vc14(),
             )
             .field(
                 "mask_err_ecc_corrected_vc15",
-                &format_args!("{}", self.mask_err_ecc_corrected_vc15().bit()),
+                &self.mask_err_ecc_corrected_vc15(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_MSK_ECC_CORRECTED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_msk_phy.rs b/esp32p4/src/mipi_csi_host/int_msk_phy.rs
index ebf1b3fdc6..e29fdf63ec 100644
--- a/esp32p4/src/mipi_csi_host/int_msk_phy.rs
+++ b/esp32p4/src/mipi_csi_host/int_msk_phy.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_MSK_PHY")
-            .field(
-                "mask_phy_errsoths_0",
-                &format_args!("{}", self.mask_phy_errsoths_0().bit()),
-            )
-            .field(
-                "mask_phy_errsoths_1",
-                &format_args!("{}", self.mask_phy_errsoths_1().bit()),
-            )
-            .field(
-                "mask_phy_erresc_0",
-                &format_args!("{}", self.mask_phy_erresc_0().bit()),
-            )
-            .field(
-                "mask_phy_erresc_1",
-                &format_args!("{}", self.mask_phy_erresc_1().bit()),
-            )
+            .field("mask_phy_errsoths_0", &self.mask_phy_errsoths_0())
+            .field("mask_phy_errsoths_1", &self.mask_phy_errsoths_1())
+            .field("mask_phy_erresc_0", &self.mask_phy_erresc_0())
+            .field("mask_phy_erresc_1", &self.mask_phy_erresc_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_MSK_PHY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_msk_phy_fatal.rs b/esp32p4/src/mipi_csi_host/int_msk_phy_fatal.rs
index 835090a98e..b5e8386105 100644
--- a/esp32p4/src/mipi_csi_host/int_msk_phy_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_msk_phy_fatal.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_MSK_PHY_FATAL")
-            .field(
-                "mask_phy_errsotsynchs_0",
-                &format_args!("{}", self.mask_phy_errsotsynchs_0().bit()),
-            )
-            .field(
-                "mask_phy_errsotsynchs_1",
-                &format_args!("{}", self.mask_phy_errsotsynchs_1().bit()),
-            )
+            .field("mask_phy_errsotsynchs_0", &self.mask_phy_errsotsynchs_0())
+            .field("mask_phy_errsotsynchs_1", &self.mask_phy_errsotsynchs_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_MSK_PHY_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_msk_pkt_fatal.rs b/esp32p4/src/mipi_csi_host/int_msk_pkt_fatal.rs
index 2ac62bc060..3a296d9e10 100644
--- a/esp32p4/src/mipi_csi_host/int_msk_pkt_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_msk_pkt_fatal.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_MSK_PKT_FATAL")
-            .field(
-                "mask_err_ecc_double",
-                &format_args!("{}", self.mask_err_ecc_double().bit()),
-            )
-            .field(
-                "mask_shorter_payload",
-                &format_args!("{}", self.mask_shorter_payload().bit()),
-            )
+            .field("mask_err_ecc_double", &self.mask_err_ecc_double())
+            .field("mask_shorter_payload", &self.mask_shorter_payload())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_MSK_PKT_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_msk_pld_crc_fatal.rs b/esp32p4/src/mipi_csi_host/int_msk_pld_crc_fatal.rs
index 5b374af603..5b714a673e 100644
--- a/esp32p4/src/mipi_csi_host/int_msk_pld_crc_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_msk_pld_crc_fatal.rs
@@ -152,79 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_MSK_PLD_CRC_FATAL")
-            .field(
-                "mask_err_crc_vc0",
-                &format_args!("{}", self.mask_err_crc_vc0().bit()),
-            )
-            .field(
-                "mask_err_crc_vc1",
-                &format_args!("{}", self.mask_err_crc_vc1().bit()),
-            )
-            .field(
-                "mask_err_crc_vc2",
-                &format_args!("{}", self.mask_err_crc_vc2().bit()),
-            )
-            .field(
-                "mask_err_crc_vc3",
-                &format_args!("{}", self.mask_err_crc_vc3().bit()),
-            )
-            .field(
-                "mask_err_crc_vc4",
-                &format_args!("{}", self.mask_err_crc_vc4().bit()),
-            )
-            .field(
-                "mask_err_crc_vc5",
-                &format_args!("{}", self.mask_err_crc_vc5().bit()),
-            )
-            .field(
-                "mask_err_crc_vc6",
-                &format_args!("{}", self.mask_err_crc_vc6().bit()),
-            )
-            .field(
-                "mask_err_crc_vc7",
-                &format_args!("{}", self.mask_err_crc_vc7().bit()),
-            )
-            .field(
-                "mask_err_crc_vc8",
-                &format_args!("{}", self.mask_err_crc_vc8().bit()),
-            )
-            .field(
-                "mask_err_crc_vc9",
-                &format_args!("{}", self.mask_err_crc_vc9().bit()),
-            )
-            .field(
-                "mask_err_crc_vc10",
-                &format_args!("{}", self.mask_err_crc_vc10().bit()),
-            )
-            .field(
-                "mask_err_crc_vc11",
-                &format_args!("{}", self.mask_err_crc_vc11().bit()),
-            )
-            .field(
-                "mask_err_crc_vc12",
-                &format_args!("{}", self.mask_err_crc_vc12().bit()),
-            )
-            .field(
-                "mask_err_crc_vc13",
-                &format_args!("{}", self.mask_err_crc_vc13().bit()),
-            )
-            .field(
-                "mask_err_crc_vc14",
-                &format_args!("{}", self.mask_err_crc_vc14().bit()),
-            )
-            .field(
-                "mask_err_crc_vc15",
-                &format_args!("{}", self.mask_err_crc_vc15().bit()),
-            )
+            .field("mask_err_crc_vc0", &self.mask_err_crc_vc0())
+            .field("mask_err_crc_vc1", &self.mask_err_crc_vc1())
+            .field("mask_err_crc_vc2", &self.mask_err_crc_vc2())
+            .field("mask_err_crc_vc3", &self.mask_err_crc_vc3())
+            .field("mask_err_crc_vc4", &self.mask_err_crc_vc4())
+            .field("mask_err_crc_vc5", &self.mask_err_crc_vc5())
+            .field("mask_err_crc_vc6", &self.mask_err_crc_vc6())
+            .field("mask_err_crc_vc7", &self.mask_err_crc_vc7())
+            .field("mask_err_crc_vc8", &self.mask_err_crc_vc8())
+            .field("mask_err_crc_vc9", &self.mask_err_crc_vc9())
+            .field("mask_err_crc_vc10", &self.mask_err_crc_vc10())
+            .field("mask_err_crc_vc11", &self.mask_err_crc_vc11())
+            .field("mask_err_crc_vc12", &self.mask_err_crc_vc12())
+            .field("mask_err_crc_vc13", &self.mask_err_crc_vc13())
+            .field("mask_err_crc_vc14", &self.mask_err_crc_vc14())
+            .field("mask_err_crc_vc15", &self.mask_err_crc_vc15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_MSK_PLD_CRC_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_msk_seq_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_msk_seq_frame_fatal.rs
index 7d75f6ff27..3e4d3e7242 100644
--- a/esp32p4/src/mipi_csi_host/int_msk_seq_frame_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_msk_seq_frame_fatal.rs
@@ -152,79 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_MSK_SEQ_FRAME_FATAL")
-            .field(
-                "mask_err_f_seq_vc0",
-                &format_args!("{}", self.mask_err_f_seq_vc0().bit()),
-            )
-            .field(
-                "mask_err_f_seq_vc1",
-                &format_args!("{}", self.mask_err_f_seq_vc1().bit()),
-            )
-            .field(
-                "mask_err_f_seq_vc2",
-                &format_args!("{}", self.mask_err_f_seq_vc2().bit()),
-            )
-            .field(
-                "mask_err_f_seq_vc3",
-                &format_args!("{}", self.mask_err_f_seq_vc3().bit()),
-            )
-            .field(
-                "mask_err_f_seq_vc4",
-                &format_args!("{}", self.mask_err_f_seq_vc4().bit()),
-            )
-            .field(
-                "mask_err_f_seq_vc5",
-                &format_args!("{}", self.mask_err_f_seq_vc5().bit()),
-            )
-            .field(
-                "mask_err_f_seq_vc6",
-                &format_args!("{}", self.mask_err_f_seq_vc6().bit()),
-            )
-            .field(
-                "mask_err_f_seq_vc7",
-                &format_args!("{}", self.mask_err_f_seq_vc7().bit()),
-            )
-            .field(
-                "mask_err_f_seq_vc8",
-                &format_args!("{}", self.mask_err_f_seq_vc8().bit()),
-            )
-            .field(
-                "mask_err_f_seq_vc9",
-                &format_args!("{}", self.mask_err_f_seq_vc9().bit()),
-            )
-            .field(
-                "mask_err_f_seq_vc10",
-                &format_args!("{}", self.mask_err_f_seq_vc10().bit()),
-            )
-            .field(
-                "mask_err_f_seq_vc11",
-                &format_args!("{}", self.mask_err_f_seq_vc11().bit()),
-            )
-            .field(
-                "mask_err_f_seq_vc12",
-                &format_args!("{}", self.mask_err_f_seq_vc12().bit()),
-            )
-            .field(
-                "mask_err_f_seq_vc13",
-                &format_args!("{}", self.mask_err_f_seq_vc13().bit()),
-            )
-            .field(
-                "mask_err_f_seq_vc14",
-                &format_args!("{}", self.mask_err_f_seq_vc14().bit()),
-            )
-            .field(
-                "mask_err_f_seq_vc15",
-                &format_args!("{}", self.mask_err_f_seq_vc15().bit()),
-            )
+            .field("mask_err_f_seq_vc0", &self.mask_err_f_seq_vc0())
+            .field("mask_err_f_seq_vc1", &self.mask_err_f_seq_vc1())
+            .field("mask_err_f_seq_vc2", &self.mask_err_f_seq_vc2())
+            .field("mask_err_f_seq_vc3", &self.mask_err_f_seq_vc3())
+            .field("mask_err_f_seq_vc4", &self.mask_err_f_seq_vc4())
+            .field("mask_err_f_seq_vc5", &self.mask_err_f_seq_vc5())
+            .field("mask_err_f_seq_vc6", &self.mask_err_f_seq_vc6())
+            .field("mask_err_f_seq_vc7", &self.mask_err_f_seq_vc7())
+            .field("mask_err_f_seq_vc8", &self.mask_err_f_seq_vc8())
+            .field("mask_err_f_seq_vc9", &self.mask_err_f_seq_vc9())
+            .field("mask_err_f_seq_vc10", &self.mask_err_f_seq_vc10())
+            .field("mask_err_f_seq_vc11", &self.mask_err_f_seq_vc11())
+            .field("mask_err_f_seq_vc12", &self.mask_err_f_seq_vc12())
+            .field("mask_err_f_seq_vc13", &self.mask_err_f_seq_vc13())
+            .field("mask_err_f_seq_vc14", &self.mask_err_f_seq_vc14())
+            .field("mask_err_f_seq_vc15", &self.mask_err_f_seq_vc15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_MSK_SEQ_FRAME_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/int_st_bndry_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_st_bndry_frame_fatal.rs
index 195f4cde6d..9554093389 100644
--- a/esp32p4/src/mipi_csi_host/int_st_bndry_frame_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_st_bndry_frame_fatal.rs
@@ -118,79 +118,43 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_BNDRY_FRAME_FATAL")
-            .field(
-                "st_err_f_bndry_match_vc0",
-                &format_args!("{}", self.st_err_f_bndry_match_vc0().bit()),
-            )
-            .field(
-                "st_err_f_bndry_match_vc1",
-                &format_args!("{}", self.st_err_f_bndry_match_vc1().bit()),
-            )
-            .field(
-                "st_err_f_bndry_match_vc2",
-                &format_args!("{}", self.st_err_f_bndry_match_vc2().bit()),
-            )
-            .field(
-                "st_err_f_bndry_match_vc3",
-                &format_args!("{}", self.st_err_f_bndry_match_vc3().bit()),
-            )
-            .field(
-                "st_err_f_bndry_match_vc4",
-                &format_args!("{}", self.st_err_f_bndry_match_vc4().bit()),
-            )
-            .field(
-                "st_err_f_bndry_match_vc5",
-                &format_args!("{}", self.st_err_f_bndry_match_vc5().bit()),
-            )
-            .field(
-                "st_err_f_bndry_match_vc6",
-                &format_args!("{}", self.st_err_f_bndry_match_vc6().bit()),
-            )
-            .field(
-                "st_err_f_bndry_match_vc7",
-                &format_args!("{}", self.st_err_f_bndry_match_vc7().bit()),
-            )
-            .field(
-                "st_err_f_bndry_match_vc8",
-                &format_args!("{}", self.st_err_f_bndry_match_vc8().bit()),
-            )
-            .field(
-                "st_err_f_bndry_match_vc9",
-                &format_args!("{}", self.st_err_f_bndry_match_vc9().bit()),
-            )
+            .field("st_err_f_bndry_match_vc0", &self.st_err_f_bndry_match_vc0())
+            .field("st_err_f_bndry_match_vc1", &self.st_err_f_bndry_match_vc1())
+            .field("st_err_f_bndry_match_vc2", &self.st_err_f_bndry_match_vc2())
+            .field("st_err_f_bndry_match_vc3", &self.st_err_f_bndry_match_vc3())
+            .field("st_err_f_bndry_match_vc4", &self.st_err_f_bndry_match_vc4())
+            .field("st_err_f_bndry_match_vc5", &self.st_err_f_bndry_match_vc5())
+            .field("st_err_f_bndry_match_vc6", &self.st_err_f_bndry_match_vc6())
+            .field("st_err_f_bndry_match_vc7", &self.st_err_f_bndry_match_vc7())
+            .field("st_err_f_bndry_match_vc8", &self.st_err_f_bndry_match_vc8())
+            .field("st_err_f_bndry_match_vc9", &self.st_err_f_bndry_match_vc9())
             .field(
                 "st_err_f_bndry_match_vc10",
-                &format_args!("{}", self.st_err_f_bndry_match_vc10().bit()),
+                &self.st_err_f_bndry_match_vc10(),
             )
             .field(
                 "st_err_f_bndry_match_vc11",
-                &format_args!("{}", self.st_err_f_bndry_match_vc11().bit()),
+                &self.st_err_f_bndry_match_vc11(),
             )
             .field(
                 "st_err_f_bndry_match_vc12",
-                &format_args!("{}", self.st_err_f_bndry_match_vc12().bit()),
+                &self.st_err_f_bndry_match_vc12(),
             )
             .field(
                 "st_err_f_bndry_match_vc13",
-                &format_args!("{}", self.st_err_f_bndry_match_vc13().bit()),
+                &self.st_err_f_bndry_match_vc13(),
             )
             .field(
                 "st_err_f_bndry_match_vc14",
-                &format_args!("{}", self.st_err_f_bndry_match_vc14().bit()),
+                &self.st_err_f_bndry_match_vc14(),
             )
             .field(
                 "st_err_f_bndry_match_vc15",
-                &format_args!("{}", self.st_err_f_bndry_match_vc15().bit()),
+                &self.st_err_f_bndry_match_vc15(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_BNDRY_FRAME_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_bndry_frame_fatal::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_BNDRY_FRAME_FATAL_SPEC;
 impl crate::RegisterSpec for INT_ST_BNDRY_FRAME_FATAL_SPEC {
diff --git a/esp32p4/src/mipi_csi_host/int_st_crc_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_st_crc_frame_fatal.rs
index c11c32ae4a..c8fcdc412c 100644
--- a/esp32p4/src/mipi_csi_host/int_st_crc_frame_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_st_crc_frame_fatal.rs
@@ -118,79 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_CRC_FRAME_FATAL")
-            .field(
-                "st_err_frame_data_vc0",
-                &format_args!("{}", self.st_err_frame_data_vc0().bit()),
-            )
-            .field(
-                "st_err_frame_data_vc1",
-                &format_args!("{}", self.st_err_frame_data_vc1().bit()),
-            )
-            .field(
-                "st_err_frame_data_vc2",
-                &format_args!("{}", self.st_err_frame_data_vc2().bit()),
-            )
-            .field(
-                "st_err_frame_data_vc3",
-                &format_args!("{}", self.st_err_frame_data_vc3().bit()),
-            )
-            .field(
-                "st_err_frame_data_vc4",
-                &format_args!("{}", self.st_err_frame_data_vc4().bit()),
-            )
-            .field(
-                "st_err_frame_data_vc5",
-                &format_args!("{}", self.st_err_frame_data_vc5().bit()),
-            )
-            .field(
-                "st_err_frame_data_vc6",
-                &format_args!("{}", self.st_err_frame_data_vc6().bit()),
-            )
-            .field(
-                "st_err_frame_data_vc7",
-                &format_args!("{}", self.st_err_frame_data_vc7().bit()),
-            )
-            .field(
-                "st_err_frame_data_vc8",
-                &format_args!("{}", self.st_err_frame_data_vc8().bit()),
-            )
-            .field(
-                "st_err_frame_data_vc9",
-                &format_args!("{}", self.st_err_frame_data_vc9().bit()),
-            )
-            .field(
-                "st_err_frame_data_vc10",
-                &format_args!("{}", self.st_err_frame_data_vc10().bit()),
-            )
-            .field(
-                "st_err_frame_data_vc11",
-                &format_args!("{}", self.st_err_frame_data_vc11().bit()),
-            )
-            .field(
-                "st_err_frame_data_vc12",
-                &format_args!("{}", self.st_err_frame_data_vc12().bit()),
-            )
-            .field(
-                "st_err_frame_data_vc13",
-                &format_args!("{}", self.st_err_frame_data_vc13().bit()),
-            )
-            .field(
-                "st_err_frame_data_vc14",
-                &format_args!("{}", self.st_err_frame_data_vc14().bit()),
-            )
-            .field(
-                "st_err_frame_data_vc15",
-                &format_args!("{}", self.st_err_frame_data_vc15().bit()),
-            )
+            .field("st_err_frame_data_vc0", &self.st_err_frame_data_vc0())
+            .field("st_err_frame_data_vc1", &self.st_err_frame_data_vc1())
+            .field("st_err_frame_data_vc2", &self.st_err_frame_data_vc2())
+            .field("st_err_frame_data_vc3", &self.st_err_frame_data_vc3())
+            .field("st_err_frame_data_vc4", &self.st_err_frame_data_vc4())
+            .field("st_err_frame_data_vc5", &self.st_err_frame_data_vc5())
+            .field("st_err_frame_data_vc6", &self.st_err_frame_data_vc6())
+            .field("st_err_frame_data_vc7", &self.st_err_frame_data_vc7())
+            .field("st_err_frame_data_vc8", &self.st_err_frame_data_vc8())
+            .field("st_err_frame_data_vc9", &self.st_err_frame_data_vc9())
+            .field("st_err_frame_data_vc10", &self.st_err_frame_data_vc10())
+            .field("st_err_frame_data_vc11", &self.st_err_frame_data_vc11())
+            .field("st_err_frame_data_vc12", &self.st_err_frame_data_vc12())
+            .field("st_err_frame_data_vc13", &self.st_err_frame_data_vc13())
+            .field("st_err_frame_data_vc14", &self.st_err_frame_data_vc14())
+            .field("st_err_frame_data_vc15", &self.st_err_frame_data_vc15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_CRC_FRAME_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_crc_frame_fatal::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_CRC_FRAME_FATAL_SPEC;
 impl crate::RegisterSpec for INT_ST_CRC_FRAME_FATAL_SPEC {
diff --git a/esp32p4/src/mipi_csi_host/int_st_data_id.rs b/esp32p4/src/mipi_csi_host/int_st_data_id.rs
index 681cd50ab0..864b2540d9 100644
--- a/esp32p4/src/mipi_csi_host/int_st_data_id.rs
+++ b/esp32p4/src/mipi_csi_host/int_st_data_id.rs
@@ -118,79 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_DATA_ID")
-            .field(
-                "st_err_id_vc0",
-                &format_args!("{}", self.st_err_id_vc0().bit()),
-            )
-            .field(
-                "st_err_id_vc1",
-                &format_args!("{}", self.st_err_id_vc1().bit()),
-            )
-            .field(
-                "st_err_id_vc2",
-                &format_args!("{}", self.st_err_id_vc2().bit()),
-            )
-            .field(
-                "st_err_id_vc3",
-                &format_args!("{}", self.st_err_id_vc3().bit()),
-            )
-            .field(
-                "st_err_id_vc4",
-                &format_args!("{}", self.st_err_id_vc4().bit()),
-            )
-            .field(
-                "st_err_id_vc5",
-                &format_args!("{}", self.st_err_id_vc5().bit()),
-            )
-            .field(
-                "st_err_id_vc6",
-                &format_args!("{}", self.st_err_id_vc6().bit()),
-            )
-            .field(
-                "st_err_id_vc7",
-                &format_args!("{}", self.st_err_id_vc7().bit()),
-            )
-            .field(
-                "st_err_id_vc8",
-                &format_args!("{}", self.st_err_id_vc8().bit()),
-            )
-            .field(
-                "st_err_id_vc9",
-                &format_args!("{}", self.st_err_id_vc9().bit()),
-            )
-            .field(
-                "st_err_id_vc10",
-                &format_args!("{}", self.st_err_id_vc10().bit()),
-            )
-            .field(
-                "st_err_id_vc11",
-                &format_args!("{}", self.st_err_id_vc11().bit()),
-            )
-            .field(
-                "st_err_id_vc12",
-                &format_args!("{}", self.st_err_id_vc12().bit()),
-            )
-            .field(
-                "st_err_id_vc13",
-                &format_args!("{}", self.st_err_id_vc13().bit()),
-            )
-            .field(
-                "st_err_id_vc14",
-                &format_args!("{}", self.st_err_id_vc14().bit()),
-            )
-            .field(
-                "st_err_id_vc15",
-                &format_args!("{}", self.st_err_id_vc15().bit()),
-            )
+            .field("st_err_id_vc0", &self.st_err_id_vc0())
+            .field("st_err_id_vc1", &self.st_err_id_vc1())
+            .field("st_err_id_vc2", &self.st_err_id_vc2())
+            .field("st_err_id_vc3", &self.st_err_id_vc3())
+            .field("st_err_id_vc4", &self.st_err_id_vc4())
+            .field("st_err_id_vc5", &self.st_err_id_vc5())
+            .field("st_err_id_vc6", &self.st_err_id_vc6())
+            .field("st_err_id_vc7", &self.st_err_id_vc7())
+            .field("st_err_id_vc8", &self.st_err_id_vc8())
+            .field("st_err_id_vc9", &self.st_err_id_vc9())
+            .field("st_err_id_vc10", &self.st_err_id_vc10())
+            .field("st_err_id_vc11", &self.st_err_id_vc11())
+            .field("st_err_id_vc12", &self.st_err_id_vc12())
+            .field("st_err_id_vc13", &self.st_err_id_vc13())
+            .field("st_err_id_vc14", &self.st_err_id_vc14())
+            .field("st_err_id_vc15", &self.st_err_id_vc15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_DATA_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_data_id::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_DATA_ID_SPEC;
 impl crate::RegisterSpec for INT_ST_DATA_ID_SPEC {
diff --git a/esp32p4/src/mipi_csi_host/int_st_ecc_corrected.rs b/esp32p4/src/mipi_csi_host/int_st_ecc_corrected.rs
index 74870924e5..cc0d618f96 100644
--- a/esp32p4/src/mipi_csi_host/int_st_ecc_corrected.rs
+++ b/esp32p4/src/mipi_csi_host/int_st_ecc_corrected.rs
@@ -118,79 +118,43 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_ECC_CORRECTED")
-            .field(
-                "st_err_ecc_corrected_vc0",
-                &format_args!("{}", self.st_err_ecc_corrected_vc0().bit()),
-            )
-            .field(
-                "st_err_ecc_corrected_vc1",
-                &format_args!("{}", self.st_err_ecc_corrected_vc1().bit()),
-            )
-            .field(
-                "st_err_ecc_corrected_vc2",
-                &format_args!("{}", self.st_err_ecc_corrected_vc2().bit()),
-            )
-            .field(
-                "st_err_ecc_corrected_vc3",
-                &format_args!("{}", self.st_err_ecc_corrected_vc3().bit()),
-            )
-            .field(
-                "st_err_ecc_corrected_vc4",
-                &format_args!("{}", self.st_err_ecc_corrected_vc4().bit()),
-            )
-            .field(
-                "st_err_ecc_corrected_vc5",
-                &format_args!("{}", self.st_err_ecc_corrected_vc5().bit()),
-            )
-            .field(
-                "st_err_ecc_corrected_vc6",
-                &format_args!("{}", self.st_err_ecc_corrected_vc6().bit()),
-            )
-            .field(
-                "st_err_ecc_corrected_vc7",
-                &format_args!("{}", self.st_err_ecc_corrected_vc7().bit()),
-            )
-            .field(
-                "st_err_ecc_corrected_vc8",
-                &format_args!("{}", self.st_err_ecc_corrected_vc8().bit()),
-            )
-            .field(
-                "st_err_ecc_corrected_vc9",
-                &format_args!("{}", self.st_err_ecc_corrected_vc9().bit()),
-            )
+            .field("st_err_ecc_corrected_vc0", &self.st_err_ecc_corrected_vc0())
+            .field("st_err_ecc_corrected_vc1", &self.st_err_ecc_corrected_vc1())
+            .field("st_err_ecc_corrected_vc2", &self.st_err_ecc_corrected_vc2())
+            .field("st_err_ecc_corrected_vc3", &self.st_err_ecc_corrected_vc3())
+            .field("st_err_ecc_corrected_vc4", &self.st_err_ecc_corrected_vc4())
+            .field("st_err_ecc_corrected_vc5", &self.st_err_ecc_corrected_vc5())
+            .field("st_err_ecc_corrected_vc6", &self.st_err_ecc_corrected_vc6())
+            .field("st_err_ecc_corrected_vc7", &self.st_err_ecc_corrected_vc7())
+            .field("st_err_ecc_corrected_vc8", &self.st_err_ecc_corrected_vc8())
+            .field("st_err_ecc_corrected_vc9", &self.st_err_ecc_corrected_vc9())
             .field(
                 "st_err_ecc_corrected_vc10",
-                &format_args!("{}", self.st_err_ecc_corrected_vc10().bit()),
+                &self.st_err_ecc_corrected_vc10(),
             )
             .field(
                 "st_err_ecc_corrected_vc11",
-                &format_args!("{}", self.st_err_ecc_corrected_vc11().bit()),
+                &self.st_err_ecc_corrected_vc11(),
             )
             .field(
                 "st_err_ecc_corrected_vc12",
-                &format_args!("{}", self.st_err_ecc_corrected_vc12().bit()),
+                &self.st_err_ecc_corrected_vc12(),
             )
             .field(
                 "st_err_ecc_corrected_vc13",
-                &format_args!("{}", self.st_err_ecc_corrected_vc13().bit()),
+                &self.st_err_ecc_corrected_vc13(),
             )
             .field(
                 "st_err_ecc_corrected_vc14",
-                &format_args!("{}", self.st_err_ecc_corrected_vc14().bit()),
+                &self.st_err_ecc_corrected_vc14(),
             )
             .field(
                 "st_err_ecc_corrected_vc15",
-                &format_args!("{}", self.st_err_ecc_corrected_vc15().bit()),
+                &self.st_err_ecc_corrected_vc15(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_ECC_CORRECTED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_ecc_corrected::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_ECC_CORRECTED_SPEC;
 impl crate::RegisterSpec for INT_ST_ECC_CORRECTED_SPEC {
diff --git a/esp32p4/src/mipi_csi_host/int_st_main.rs b/esp32p4/src/mipi_csi_host/int_st_main.rs
index 52d64dd35c..22982e90c0 100644
--- a/esp32p4/src/mipi_csi_host/int_st_main.rs
+++ b/esp32p4/src/mipi_csi_host/int_st_main.rs
@@ -69,51 +69,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_MAIN")
-            .field(
-                "st_status_int_phy_fatal",
-                &format_args!("{}", self.st_status_int_phy_fatal().bit()),
-            )
-            .field(
-                "st_status_int_pkt_fatal",
-                &format_args!("{}", self.st_status_int_pkt_fatal().bit()),
-            )
+            .field("st_status_int_phy_fatal", &self.st_status_int_phy_fatal())
+            .field("st_status_int_pkt_fatal", &self.st_status_int_pkt_fatal())
             .field(
                 "st_status_int_bndry_frame_fatal",
-                &format_args!("{}", self.st_status_int_bndry_frame_fatal().bit()),
+                &self.st_status_int_bndry_frame_fatal(),
             )
             .field(
                 "st_status_int_seq_frame_fatal",
-                &format_args!("{}", self.st_status_int_seq_frame_fatal().bit()),
+                &self.st_status_int_seq_frame_fatal(),
             )
             .field(
                 "st_status_int_crc_frame_fatal",
-                &format_args!("{}", self.st_status_int_crc_frame_fatal().bit()),
+                &self.st_status_int_crc_frame_fatal(),
             )
             .field(
                 "st_status_int_pld_crc_fatal",
-                &format_args!("{}", self.st_status_int_pld_crc_fatal().bit()),
-            )
-            .field(
-                "st_status_int_data_id",
-                &format_args!("{}", self.st_status_int_data_id().bit()),
+                &self.st_status_int_pld_crc_fatal(),
             )
+            .field("st_status_int_data_id", &self.st_status_int_data_id())
             .field(
                 "st_status_int_ecc_corrected",
-                &format_args!("{}", self.st_status_int_ecc_corrected().bit()),
-            )
-            .field(
-                "st_status_int_phy",
-                &format_args!("{}", self.st_status_int_phy().bit()),
+                &self.st_status_int_ecc_corrected(),
             )
+            .field("st_status_int_phy", &self.st_status_int_phy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_MAIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_main::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_MAIN_SPEC;
 impl crate::RegisterSpec for INT_ST_MAIN_SPEC {
diff --git a/esp32p4/src/mipi_csi_host/int_st_phy.rs b/esp32p4/src/mipi_csi_host/int_st_phy.rs
index e8de5f4d59..797ccd4190 100644
--- a/esp32p4/src/mipi_csi_host/int_st_phy.rs
+++ b/esp32p4/src/mipi_csi_host/int_st_phy.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_PHY")
-            .field(
-                "st_phy_errsoths_0",
-                &format_args!("{}", self.st_phy_errsoths_0().bit()),
-            )
-            .field(
-                "st_phy_errsoths_1",
-                &format_args!("{}", self.st_phy_errsoths_1().bit()),
-            )
-            .field(
-                "st_phy_erresc_0",
-                &format_args!("{}", self.st_phy_erresc_0().bit()),
-            )
-            .field(
-                "st_phy_erresc_1",
-                &format_args!("{}", self.st_phy_erresc_1().bit()),
-            )
+            .field("st_phy_errsoths_0", &self.st_phy_errsoths_0())
+            .field("st_phy_errsoths_1", &self.st_phy_errsoths_1())
+            .field("st_phy_erresc_0", &self.st_phy_erresc_0())
+            .field("st_phy_erresc_1", &self.st_phy_erresc_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_PHY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_phy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_PHY_SPEC;
 impl crate::RegisterSpec for INT_ST_PHY_SPEC {
diff --git a/esp32p4/src/mipi_csi_host/int_st_phy_fatal.rs b/esp32p4/src/mipi_csi_host/int_st_phy_fatal.rs
index 94b80667f6..e808c51851 100644
--- a/esp32p4/src/mipi_csi_host/int_st_phy_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_st_phy_fatal.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_PHY_FATAL")
-            .field(
-                "st_phy_errsotsynchs_0",
-                &format_args!("{}", self.st_phy_errsotsynchs_0().bit()),
-            )
-            .field(
-                "st_phy_errsotsynchs_1",
-                &format_args!("{}", self.st_phy_errsotsynchs_1().bit()),
-            )
+            .field("st_phy_errsotsynchs_0", &self.st_phy_errsotsynchs_0())
+            .field("st_phy_errsotsynchs_1", &self.st_phy_errsotsynchs_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_PHY_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_phy_fatal::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_PHY_FATAL_SPEC;
 impl crate::RegisterSpec for INT_ST_PHY_FATAL_SPEC {
diff --git a/esp32p4/src/mipi_csi_host/int_st_pkt_fatal.rs b/esp32p4/src/mipi_csi_host/int_st_pkt_fatal.rs
index 00817ee395..264e210a6f 100644
--- a/esp32p4/src/mipi_csi_host/int_st_pkt_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_st_pkt_fatal.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_PKT_FATAL")
-            .field(
-                "st_err_ecc_double",
-                &format_args!("{}", self.st_err_ecc_double().bit()),
-            )
-            .field(
-                "st_shorter_payload",
-                &format_args!("{}", self.st_shorter_payload().bit()),
-            )
+            .field("st_err_ecc_double", &self.st_err_ecc_double())
+            .field("st_shorter_payload", &self.st_shorter_payload())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_PKT_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_pkt_fatal::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_PKT_FATAL_SPEC;
 impl crate::RegisterSpec for INT_ST_PKT_FATAL_SPEC {
diff --git a/esp32p4/src/mipi_csi_host/int_st_pld_crc_fatal.rs b/esp32p4/src/mipi_csi_host/int_st_pld_crc_fatal.rs
index 72c8340f0b..34e06fcd60 100644
--- a/esp32p4/src/mipi_csi_host/int_st_pld_crc_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_st_pld_crc_fatal.rs
@@ -118,79 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_PLD_CRC_FATAL")
-            .field(
-                "st_err_crc_vc0",
-                &format_args!("{}", self.st_err_crc_vc0().bit()),
-            )
-            .field(
-                "st_err_crc_vc1",
-                &format_args!("{}", self.st_err_crc_vc1().bit()),
-            )
-            .field(
-                "st_err_crc_vc2",
-                &format_args!("{}", self.st_err_crc_vc2().bit()),
-            )
-            .field(
-                "st_err_crc_vc3",
-                &format_args!("{}", self.st_err_crc_vc3().bit()),
-            )
-            .field(
-                "st_err_crc_vc4",
-                &format_args!("{}", self.st_err_crc_vc4().bit()),
-            )
-            .field(
-                "st_err_crc_vc5",
-                &format_args!("{}", self.st_err_crc_vc5().bit()),
-            )
-            .field(
-                "st_err_crc_vc6",
-                &format_args!("{}", self.st_err_crc_vc6().bit()),
-            )
-            .field(
-                "st_err_crc_vc7",
-                &format_args!("{}", self.st_err_crc_vc7().bit()),
-            )
-            .field(
-                "st_err_crc_vc8",
-                &format_args!("{}", self.st_err_crc_vc8().bit()),
-            )
-            .field(
-                "st_err_crc_vc9",
-                &format_args!("{}", self.st_err_crc_vc9().bit()),
-            )
-            .field(
-                "st_err_crc_vc10",
-                &format_args!("{}", self.st_err_crc_vc10().bit()),
-            )
-            .field(
-                "st_err_crc_vc11",
-                &format_args!("{}", self.st_err_crc_vc11().bit()),
-            )
-            .field(
-                "st_err_crc_vc12",
-                &format_args!("{}", self.st_err_crc_vc12().bit()),
-            )
-            .field(
-                "st_err_crc_vc13",
-                &format_args!("{}", self.st_err_crc_vc13().bit()),
-            )
-            .field(
-                "st_err_crc_vc14",
-                &format_args!("{}", self.st_err_crc_vc14().bit()),
-            )
-            .field(
-                "st_err_crc_vc15",
-                &format_args!("{}", self.st_err_crc_vc15().bit()),
-            )
+            .field("st_err_crc_vc0", &self.st_err_crc_vc0())
+            .field("st_err_crc_vc1", &self.st_err_crc_vc1())
+            .field("st_err_crc_vc2", &self.st_err_crc_vc2())
+            .field("st_err_crc_vc3", &self.st_err_crc_vc3())
+            .field("st_err_crc_vc4", &self.st_err_crc_vc4())
+            .field("st_err_crc_vc5", &self.st_err_crc_vc5())
+            .field("st_err_crc_vc6", &self.st_err_crc_vc6())
+            .field("st_err_crc_vc7", &self.st_err_crc_vc7())
+            .field("st_err_crc_vc8", &self.st_err_crc_vc8())
+            .field("st_err_crc_vc9", &self.st_err_crc_vc9())
+            .field("st_err_crc_vc10", &self.st_err_crc_vc10())
+            .field("st_err_crc_vc11", &self.st_err_crc_vc11())
+            .field("st_err_crc_vc12", &self.st_err_crc_vc12())
+            .field("st_err_crc_vc13", &self.st_err_crc_vc13())
+            .field("st_err_crc_vc14", &self.st_err_crc_vc14())
+            .field("st_err_crc_vc15", &self.st_err_crc_vc15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_PLD_CRC_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_pld_crc_fatal::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_PLD_CRC_FATAL_SPEC;
 impl crate::RegisterSpec for INT_ST_PLD_CRC_FATAL_SPEC {
diff --git a/esp32p4/src/mipi_csi_host/int_st_seq_frame_fatal.rs b/esp32p4/src/mipi_csi_host/int_st_seq_frame_fatal.rs
index 5c95af1535..d7617f79b5 100644
--- a/esp32p4/src/mipi_csi_host/int_st_seq_frame_fatal.rs
+++ b/esp32p4/src/mipi_csi_host/int_st_seq_frame_fatal.rs
@@ -118,79 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_SEQ_FRAME_FATAL")
-            .field(
-                "st_err_f_seq_vc0",
-                &format_args!("{}", self.st_err_f_seq_vc0().bit()),
-            )
-            .field(
-                "st_err_f_seq_vc1",
-                &format_args!("{}", self.st_err_f_seq_vc1().bit()),
-            )
-            .field(
-                "st_err_f_seq_vc2",
-                &format_args!("{}", self.st_err_f_seq_vc2().bit()),
-            )
-            .field(
-                "st_err_f_seq_vc3",
-                &format_args!("{}", self.st_err_f_seq_vc3().bit()),
-            )
-            .field(
-                "st_err_f_seq_vc4",
-                &format_args!("{}", self.st_err_f_seq_vc4().bit()),
-            )
-            .field(
-                "st_err_f_seq_vc5",
-                &format_args!("{}", self.st_err_f_seq_vc5().bit()),
-            )
-            .field(
-                "st_err_f_seq_vc6",
-                &format_args!("{}", self.st_err_f_seq_vc6().bit()),
-            )
-            .field(
-                "st_err_f_seq_vc7",
-                &format_args!("{}", self.st_err_f_seq_vc7().bit()),
-            )
-            .field(
-                "st_err_f_seq_vc8",
-                &format_args!("{}", self.st_err_f_seq_vc8().bit()),
-            )
-            .field(
-                "st_err_f_seq_vc9",
-                &format_args!("{}", self.st_err_f_seq_vc9().bit()),
-            )
-            .field(
-                "st_err_f_seq_vc10",
-                &format_args!("{}", self.st_err_f_seq_vc10().bit()),
-            )
-            .field(
-                "st_err_f_seq_vc11",
-                &format_args!("{}", self.st_err_f_seq_vc11().bit()),
-            )
-            .field(
-                "st_err_f_seq_vc12",
-                &format_args!("{}", self.st_err_f_seq_vc12().bit()),
-            )
-            .field(
-                "st_err_f_seq_vc13",
-                &format_args!("{}", self.st_err_f_seq_vc13().bit()),
-            )
-            .field(
-                "st_err_f_seq_vc14",
-                &format_args!("{}", self.st_err_f_seq_vc14().bit()),
-            )
-            .field(
-                "st_err_f_seq_vc15",
-                &format_args!("{}", self.st_err_f_seq_vc15().bit()),
-            )
+            .field("st_err_f_seq_vc0", &self.st_err_f_seq_vc0())
+            .field("st_err_f_seq_vc1", &self.st_err_f_seq_vc1())
+            .field("st_err_f_seq_vc2", &self.st_err_f_seq_vc2())
+            .field("st_err_f_seq_vc3", &self.st_err_f_seq_vc3())
+            .field("st_err_f_seq_vc4", &self.st_err_f_seq_vc4())
+            .field("st_err_f_seq_vc5", &self.st_err_f_seq_vc5())
+            .field("st_err_f_seq_vc6", &self.st_err_f_seq_vc6())
+            .field("st_err_f_seq_vc7", &self.st_err_f_seq_vc7())
+            .field("st_err_f_seq_vc8", &self.st_err_f_seq_vc8())
+            .field("st_err_f_seq_vc9", &self.st_err_f_seq_vc9())
+            .field("st_err_f_seq_vc10", &self.st_err_f_seq_vc10())
+            .field("st_err_f_seq_vc11", &self.st_err_f_seq_vc11())
+            .field("st_err_f_seq_vc12", &self.st_err_f_seq_vc12())
+            .field("st_err_f_seq_vc13", &self.st_err_f_seq_vc13())
+            .field("st_err_f_seq_vc14", &self.st_err_f_seq_vc14())
+            .field("st_err_f_seq_vc15", &self.st_err_f_seq_vc15())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SEQ_FRAME_FATAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_seq_frame_fatal::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SEQ_FRAME_FATAL_SPEC;
 impl crate::RegisterSpec for INT_ST_SEQ_FRAME_FATAL_SPEC {
diff --git a/esp32p4/src/mipi_csi_host/n_lanes.rs b/esp32p4/src/mipi_csi_host/n_lanes.rs
index b36113b257..c0be892581 100644
--- a/esp32p4/src/mipi_csi_host/n_lanes.rs
+++ b/esp32p4/src/mipi_csi_host/n_lanes.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("N_LANES")
-            .field("n_lanes", &format_args!("{}", self.n_lanes().bits()))
+            .field("n_lanes", &self.n_lanes())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<N_LANES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/phy_cal.rs b/esp32p4/src/mipi_csi_host/phy_cal.rs
index 8054f25db7..589ad266de 100644
--- a/esp32p4/src/mipi_csi_host/phy_cal.rs
+++ b/esp32p4/src/mipi_csi_host/phy_cal.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_CAL")
-            .field("rxskewcalhs", &format_args!("{}", self.rxskewcalhs().bit()))
+            .field("rxskewcalhs", &self.rxskewcalhs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_CAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_cal::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PHY_CAL_SPEC;
 impl crate::RegisterSpec for PHY_CAL_SPEC {
diff --git a/esp32p4/src/mipi_csi_host/phy_rx.rs b/esp32p4/src/mipi_csi_host/phy_rx.rs
index 729d21f2a5..7c4194edfd 100644
--- a/esp32p4/src/mipi_csi_host/phy_rx.rs
+++ b/esp32p4/src/mipi_csi_host/phy_rx.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_RX")
-            .field(
-                "phy_rxulpsesc_0",
-                &format_args!("{}", self.phy_rxulpsesc_0().bit()),
-            )
-            .field(
-                "phy_rxulpsesc_1",
-                &format_args!("{}", self.phy_rxulpsesc_1().bit()),
-            )
-            .field(
-                "phy_rxulpsclknot",
-                &format_args!("{}", self.phy_rxulpsclknot().bit()),
-            )
-            .field(
-                "phy_rxclkactivehs",
-                &format_args!("{}", self.phy_rxclkactivehs().bit()),
-            )
+            .field("phy_rxulpsesc_0", &self.phy_rxulpsesc_0())
+            .field("phy_rxulpsesc_1", &self.phy_rxulpsesc_1())
+            .field("phy_rxulpsclknot", &self.phy_rxulpsclknot())
+            .field("phy_rxclkactivehs", &self.phy_rxclkactivehs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_RX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_rx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PHY_RX_SPEC;
 impl crate::RegisterSpec for PHY_RX_SPEC {
diff --git a/esp32p4/src/mipi_csi_host/phy_shutdownz.rs b/esp32p4/src/mipi_csi_host/phy_shutdownz.rs
index d4bd40b498..b94ce33117 100644
--- a/esp32p4/src/mipi_csi_host/phy_shutdownz.rs
+++ b/esp32p4/src/mipi_csi_host/phy_shutdownz.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_SHUTDOWNZ")
-            .field(
-                "phy_shutdownz",
-                &format_args!("{}", self.phy_shutdownz().bit()),
-            )
+            .field("phy_shutdownz", &self.phy_shutdownz())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_SHUTDOWNZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/phy_stopstate.rs b/esp32p4/src/mipi_csi_host/phy_stopstate.rs
index 8b039bff42..acb21c0804 100644
--- a/esp32p4/src/mipi_csi_host/phy_stopstate.rs
+++ b/esp32p4/src/mipi_csi_host/phy_stopstate.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_STOPSTATE")
-            .field(
-                "phy_stopstatedata_0",
-                &format_args!("{}", self.phy_stopstatedata_0().bit()),
-            )
-            .field(
-                "phy_stopstatedata_1",
-                &format_args!("{}", self.phy_stopstatedata_1().bit()),
-            )
-            .field(
-                "phy_stopstateclk",
-                &format_args!("{}", self.phy_stopstateclk().bit()),
-            )
+            .field("phy_stopstatedata_0", &self.phy_stopstatedata_0())
+            .field("phy_stopstatedata_1", &self.phy_stopstatedata_1())
+            .field("phy_stopstateclk", &self.phy_stopstateclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_STOPSTATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_stopstate::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PHY_STOPSTATE_SPEC;
 impl crate::RegisterSpec for PHY_STOPSTATE_SPEC {
diff --git a/esp32p4/src/mipi_csi_host/phy_test_ctrl0.rs b/esp32p4/src/mipi_csi_host/phy_test_ctrl0.rs
index 7f72234997..3dab9a3387 100644
--- a/esp32p4/src/mipi_csi_host/phy_test_ctrl0.rs
+++ b/esp32p4/src/mipi_csi_host/phy_test_ctrl0.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_TEST_CTRL0")
-            .field("phy_testclr", &format_args!("{}", self.phy_testclr().bit()))
-            .field("phy_testclk", &format_args!("{}", self.phy_testclk().bit()))
+            .field("phy_testclr", &self.phy_testclr())
+            .field("phy_testclk", &self.phy_testclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_TEST_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/phy_test_ctrl1.rs b/esp32p4/src/mipi_csi_host/phy_test_ctrl1.rs
index c4931bbf30..28a1fb15ca 100644
--- a/esp32p4/src/mipi_csi_host/phy_test_ctrl1.rs
+++ b/esp32p4/src/mipi_csi_host/phy_test_ctrl1.rs
@@ -33,24 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_TEST_CTRL1")
-            .field(
-                "phy_testdin",
-                &format_args!("{}", self.phy_testdin().bits()),
-            )
-            .field(
-                "phy_testdout",
-                &format_args!("{}", self.phy_testdout().bits()),
-            )
-            .field("phy_testen", &format_args!("{}", self.phy_testen().bit()))
+            .field("phy_testdin", &self.phy_testdin())
+            .field("phy_testdout", &self.phy_testdout())
+            .field("phy_testen", &self.phy_testen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_TEST_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/scrambling.rs b/esp32p4/src/mipi_csi_host/scrambling.rs
index 788dcc3dac..62eb228e29 100644
--- a/esp32p4/src/mipi_csi_host/scrambling.rs
+++ b/esp32p4/src/mipi_csi_host/scrambling.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCRAMBLING")
-            .field(
-                "scramble_enable",
-                &format_args!("{}", self.scramble_enable().bit()),
-            )
+            .field("scramble_enable", &self.scramble_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCRAMBLING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/scrambling_seed1.rs b/esp32p4/src/mipi_csi_host/scrambling_seed1.rs
index 85e5b8bc3d..52488ebe40 100644
--- a/esp32p4/src/mipi_csi_host/scrambling_seed1.rs
+++ b/esp32p4/src/mipi_csi_host/scrambling_seed1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCRAMBLING_SEED1")
-            .field(
-                "scramble_seed_lane1",
-                &format_args!("{}", self.scramble_seed_lane1().bits()),
-            )
+            .field("scramble_seed_lane1", &self.scramble_seed_lane1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCRAMBLING_SEED1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/scrambling_seed2.rs b/esp32p4/src/mipi_csi_host/scrambling_seed2.rs
index f7dd2a2616..4356b1aa49 100644
--- a/esp32p4/src/mipi_csi_host/scrambling_seed2.rs
+++ b/esp32p4/src/mipi_csi_host/scrambling_seed2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCRAMBLING_SEED2")
-            .field(
-                "scramble_seed_lane2",
-                &format_args!("{}", self.scramble_seed_lane2().bits()),
-            )
+            .field("scramble_seed_lane2", &self.scramble_seed_lane2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCRAMBLING_SEED2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/vc_extension.rs b/esp32p4/src/mipi_csi_host/vc_extension.rs
index c2b3bfa407..9ff5f3db5d 100644
--- a/esp32p4/src/mipi_csi_host/vc_extension.rs
+++ b/esp32p4/src/mipi_csi_host/vc_extension.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VC_EXTENSION")
-            .field("vcx", &format_args!("{}", self.vcx().bit()))
+            .field("vcx", &self.vcx())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VC_EXTENSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_csi_host/version.rs b/esp32p4/src/mipi_csi_host/version.rs
index c521cdc9e6..37d550e8f0 100644
--- a/esp32p4/src/mipi_csi_host/version.rs
+++ b/esp32p4/src/mipi_csi_host/version.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field("version", &format_args!("{}", self.version().bits()))
+            .field("version", &self.version())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VERSION_SPEC;
 impl crate::RegisterSpec for VERSION_SPEC {
diff --git a/esp32p4/src/mipi_dsi_bridge/blk_raw_num_cfg.rs b/esp32p4/src/mipi_dsi_bridge/blk_raw_num_cfg.rs
index 93b99a0472..69c6245c95 100644
--- a/esp32p4/src/mipi_dsi_bridge/blk_raw_num_cfg.rs
+++ b/esp32p4/src/mipi_dsi_bridge/blk_raw_num_cfg.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLK_RAW_NUM_CFG")
-            .field(
-                "blk_raw_num_total",
-                &format_args!("{}", self.blk_raw_num_total().bits()),
-            )
+            .field("blk_raw_num_total", &self.blk_raw_num_total())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLK_RAW_NUM_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - this field configures number of total block pix bits/64"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/clk_en.rs b/esp32p4/src/mipi_dsi_bridge/clk_en.rs
index a49e4cf6a8..751979d179 100644
--- a/esp32p4/src/mipi_dsi_bridge/clk_en.rs
+++ b/esp32p4/src/mipi_dsi_bridge/clk_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EN")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit configures force_on of dsi_bridge register clock gate"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/dma_block_interval.rs b/esp32p4/src/mipi_dsi_bridge/dma_block_interval.rs
index 5ea0fe52f0..e573a2cc65 100644
--- a/esp32p4/src/mipi_dsi_bridge/dma_block_interval.rs
+++ b/esp32p4/src/mipi_dsi_bridge/dma_block_interval.rs
@@ -44,28 +44,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_BLOCK_INTERVAL")
-            .field(
-                "dma_block_slot",
-                &format_args!("{}", self.dma_block_slot().bits()),
-            )
-            .field(
-                "dma_block_interval",
-                &format_args!("{}", self.dma_block_interval().bits()),
-            )
+            .field("dma_block_slot", &self.dma_block_slot())
+            .field("dma_block_interval", &self.dma_block_interval())
             .field(
                 "raw_num_total_auto_reload",
-                &format_args!("{}", self.raw_num_total_auto_reload().bit()),
+                &self.raw_num_total_auto_reload(),
             )
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_BLOCK_INTERVAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - this field configures the max block_slot_cnt"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/dma_flow_ctrl.rs b/esp32p4/src/mipi_dsi_bridge/dma_flow_ctrl.rs
index c782e015f8..938353f43a 100644
--- a/esp32p4/src/mipi_dsi_bridge/dma_flow_ctrl.rs
+++ b/esp32p4/src/mipi_dsi_bridge/dma_flow_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_FLOW_CTRL")
-            .field(
-                "dsi_dma_flow_controller",
-                &format_args!("{}", self.dsi_dma_flow_controller().bit()),
-            )
-            .field(
-                "dma_flow_multiblk_num",
-                &format_args!("{}", self.dma_flow_multiblk_num().bits()),
-            )
+            .field("dsi_dma_flow_controller", &self.dsi_dma_flow_controller())
+            .field("dma_flow_multiblk_num", &self.dma_flow_multiblk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_FLOW_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge as flow controller"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/dma_frame_interval.rs b/esp32p4/src/mipi_dsi_bridge/dma_frame_interval.rs
index 54913f6632..948c2af495 100644
--- a/esp32p4/src/mipi_dsi_bridge/dma_frame_interval.rs
+++ b/esp32p4/src/mipi_dsi_bridge/dma_frame_interval.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_FRAME_INTERVAL")
-            .field(
-                "dma_frame_slot",
-                &format_args!("{}", self.dma_frame_slot().bits()),
-            )
-            .field(
-                "dma_frame_interval",
-                &format_args!("{}", self.dma_frame_interval().bits()),
-            )
-            .field(
-                "dma_multiblk_en",
-                &format_args!("{}", self.dma_multiblk_en().bit()),
-            )
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("dma_frame_slot", &self.dma_frame_slot())
+            .field("dma_frame_interval", &self.dma_frame_interval())
+            .field("dma_multiblk_en", &self.dma_multiblk_en())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_FRAME_INTERVAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - this field configures the max frame_slot_cnt"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/dma_req_cfg.rs b/esp32p4/src/mipi_dsi_bridge/dma_req_cfg.rs
index 7645a31285..99e38af8c3 100644
--- a/esp32p4/src/mipi_dsi_bridge/dma_req_cfg.rs
+++ b/esp32p4/src/mipi_dsi_bridge/dma_req_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_REQ_CFG")
-            .field(
-                "dma_burst_len",
-                &format_args!("{}", self.dma_burst_len().bits()),
-            )
+            .field("dma_burst_len", &self.dma_burst_len())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_REQ_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - this field configures the num of 64-bit in one dma burst transfer, valid only when dsi_bridge as flow controller"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/dma_req_interval.rs b/esp32p4/src/mipi_dsi_bridge/dma_req_interval.rs
index 4759cab049..0cf3772266 100644
--- a/esp32p4/src/mipi_dsi_bridge/dma_req_interval.rs
+++ b/esp32p4/src/mipi_dsi_bridge/dma_req_interval.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_REQ_INTERVAL")
-            .field(
-                "dma_req_interval",
-                &format_args!("{}", self.dma_req_interval().bits()),
-            )
+            .field("dma_req_interval", &self.dma_req_interval())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_REQ_INTERVAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - this field configures the interval between dma req events"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/dpi_h_cfg0.rs b/esp32p4/src/mipi_dsi_bridge/dpi_h_cfg0.rs
index 2adad9836d..42c77ca14b 100644
--- a/esp32p4/src/mipi_dsi_bridge/dpi_h_cfg0.rs
+++ b/esp32p4/src/mipi_dsi_bridge/dpi_h_cfg0.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPI_H_CFG0")
-            .field("htotal", &format_args!("{}", self.htotal().bits()))
-            .field("hdisp", &format_args!("{}", self.hdisp().bits()))
+            .field("htotal", &self.htotal())
+            .field("hdisp", &self.hdisp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPI_H_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - this field configures the total length of one line (by pixel num) for dpi output, must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/dpi_h_cfg1.rs b/esp32p4/src/mipi_dsi_bridge/dpi_h_cfg1.rs
index 59697f1bfe..47103c07a2 100644
--- a/esp32p4/src/mipi_dsi_bridge/dpi_h_cfg1.rs
+++ b/esp32p4/src/mipi_dsi_bridge/dpi_h_cfg1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPI_H_CFG1")
-            .field("hbank", &format_args!("{}", self.hbank().bits()))
-            .field("hsync", &format_args!("{}", self.hsync().bits()))
+            .field("hbank", &self.hbank())
+            .field("hsync", &self.hsync())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPI_H_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - this field configures the length between hsync and pixel data valid (by pixel num) for dpi output"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/dpi_lcd_ctl.rs b/esp32p4/src/mipi_dsi_bridge/dpi_lcd_ctl.rs
index 5163cfb4f1..66fe2ac95f 100644
--- a/esp32p4/src/mipi_dsi_bridge/dpi_lcd_ctl.rs
+++ b/esp32p4/src/mipi_dsi_bridge/dpi_lcd_ctl.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPI_LCD_CTL")
-            .field("dpishutdn", &format_args!("{}", self.dpishutdn().bit()))
-            .field("dpicolorm", &format_args!("{}", self.dpicolorm().bit()))
-            .field(
-                "dpiupdatecfg",
-                &format_args!("{}", self.dpiupdatecfg().bit()),
-            )
+            .field("dpishutdn", &self.dpishutdn())
+            .field("dpicolorm", &self.dpicolorm())
+            .field("dpiupdatecfg", &self.dpiupdatecfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPI_LCD_CTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit configures dpishutdn signal in dpi interface"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/dpi_misc_config.rs b/esp32p4/src/mipi_dsi_bridge/dpi_misc_config.rs
index ac1609529b..585bbf2254 100644
--- a/esp32p4/src/mipi_dsi_bridge/dpi_misc_config.rs
+++ b/esp32p4/src/mipi_dsi_bridge/dpi_misc_config.rs
@@ -26,20 +26,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPI_MISC_CONFIG")
-            .field("dpi_en", &format_args!("{}", self.dpi_en().bit()))
+            .field("dpi_en", &self.dpi_en())
             .field(
                 "fifo_underrun_discard_vcnt",
-                &format_args!("{}", self.fifo_underrun_discard_vcnt().bits()),
+                &self.fifo_underrun_discard_vcnt(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPI_MISC_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit configures enable of dpi output, 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/dpi_rsv_dpi_data.rs b/esp32p4/src/mipi_dsi_bridge/dpi_rsv_dpi_data.rs
index 0a2616796c..07870a31db 100644
--- a/esp32p4/src/mipi_dsi_bridge/dpi_rsv_dpi_data.rs
+++ b/esp32p4/src/mipi_dsi_bridge/dpi_rsv_dpi_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPI_RSV_DPI_DATA")
-            .field(
-                "dpi_rsv_data",
-                &format_args!("{}", self.dpi_rsv_data().bits()),
-            )
+            .field("dpi_rsv_data", &self.dpi_rsv_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPI_RSV_DPI_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - this field controls the pixel data sent to dsi_host when dsi_bridge fifo underflow"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/dpi_v_cfg0.rs b/esp32p4/src/mipi_dsi_bridge/dpi_v_cfg0.rs
index 6c1acb7284..d6e1fc1e77 100644
--- a/esp32p4/src/mipi_dsi_bridge/dpi_v_cfg0.rs
+++ b/esp32p4/src/mipi_dsi_bridge/dpi_v_cfg0.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPI_V_CFG0")
-            .field("vtotal", &format_args!("{}", self.vtotal().bits()))
-            .field("vdisp", &format_args!("{}", self.vdisp().bits()))
+            .field("vtotal", &self.vtotal())
+            .field("vdisp", &self.vdisp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPI_V_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - this field configures the total length of one frame (by line) for dpi output, must meet: reg_vtotal > reg_vdisp+reg_vsync+reg_vbank"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/dpi_v_cfg1.rs b/esp32p4/src/mipi_dsi_bridge/dpi_v_cfg1.rs
index 9f282275e7..3783e9507f 100644
--- a/esp32p4/src/mipi_dsi_bridge/dpi_v_cfg1.rs
+++ b/esp32p4/src/mipi_dsi_bridge/dpi_v_cfg1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPI_V_CFG1")
-            .field("vbank", &format_args!("{}", self.vbank().bits()))
-            .field("vsync", &format_args!("{}", self.vsync().bits()))
+            .field("vbank", &self.vbank())
+            .field("vsync", &self.vsync())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPI_V_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - this field configures the length between vsync and valid line (by line) for dpi output"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/en.rs b/esp32p4/src/mipi_dsi_bridge/en.rs
index 3f12850866..d1642b2a12 100644
--- a/esp32p4/src/mipi_dsi_bridge/en.rs
+++ b/esp32p4/src/mipi_dsi_bridge/en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EN")
-            .field("dsi_en", &format_args!("{}", self.dsi_en().bit()))
+            .field("dsi_en", &self.dsi_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit configures module enable of dsi_bridge. 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/fifo_flow_status.rs b/esp32p4/src/mipi_dsi_bridge/fifo_flow_status.rs
index 47bacd0f38..4022ee8c25 100644
--- a/esp32p4/src/mipi_dsi_bridge/fifo_flow_status.rs
+++ b/esp32p4/src/mipi_dsi_bridge/fifo_flow_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_FLOW_STATUS")
-            .field(
-                "raw_buf_depth",
-                &format_args!("{}", self.raw_buf_depth().bits()),
-            )
+            .field("raw_buf_depth", &self.raw_buf_depth())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_FLOW_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "dsi bridge raw buffer depth register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_flow_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_FLOW_STATUS_SPEC;
 impl crate::RegisterSpec for FIFO_FLOW_STATUS_SPEC {
diff --git a/esp32p4/src/mipi_dsi_bridge/host_bist_ctl.rs b/esp32p4/src/mipi_dsi_bridge/host_bist_ctl.rs
index 312b4cc3a4..e7425b5239 100644
--- a/esp32p4/src/mipi_dsi_bridge/host_bist_ctl.rs
+++ b/esp32p4/src/mipi_dsi_bridge/host_bist_ctl.rs
@@ -24,17 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_BIST_CTL")
-            .field("bistok", &format_args!("{}", self.bistok().bit()))
-            .field("biston", &format_args!("{}", self.biston().bit()))
+            .field("bistok", &self.bistok())
+            .field("biston", &self.biston())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_BIST_CTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - biston"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/host_ctrl.rs b/esp32p4/src/mipi_dsi_bridge/host_ctrl.rs
index a2a4ee2ede..9dd42df741 100644
--- a/esp32p4/src/mipi_dsi_bridge/host_ctrl.rs
+++ b/esp32p4/src/mipi_dsi_bridge/host_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_CTRL")
-            .field(
-                "dsi_cfg_ref_clk_en",
-                &format_args!("{}", self.dsi_cfg_ref_clk_en().bit()),
-            )
+            .field("dsi_cfg_ref_clk_en", &self.dsi_cfg_ref_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/host_trigger_rev.rs b/esp32p4/src/mipi_dsi_bridge/host_trigger_rev.rs
index 8ba339662b..610e82540b 100644
--- a/esp32p4/src/mipi_dsi_bridge/host_trigger_rev.rs
+++ b/esp32p4/src/mipi_dsi_bridge/host_trigger_rev.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_TRIGGER_REV")
-            .field(
-                "tx_trigger_rev_en",
-                &format_args!("{}", self.tx_trigger_rev_en().bit()),
-            )
-            .field(
-                "rx_trigger_rev_en",
-                &format_args!("{}", self.rx_trigger_rev_en().bit()),
-            )
+            .field("tx_trigger_rev_en", &self.tx_trigger_rev_en())
+            .field("rx_trigger_rev_en", &self.rx_trigger_rev_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_TRIGGER_REV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - tx_trigger reverse. 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/int_ena.rs b/esp32p4/src/mipi_dsi_bridge/int_ena.rs
index 8bcaeba4ba..30272d2ee7 100644
--- a/esp32p4/src/mipi_dsi_bridge/int_ena.rs
+++ b/esp32p4/src/mipi_dsi_bridge/int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("underrun", &format_args!("{}", self.underrun().bit()))
+            .field("underrun", &self.underrun())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by dpi_underrun interrupt signal"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/int_raw.rs b/esp32p4/src/mipi_dsi_bridge/int_raw.rs
index 6dbab6a43f..2ae40b80d6 100644
--- a/esp32p4/src/mipi_dsi_bridge/int_raw.rs
+++ b/esp32p4/src/mipi_dsi_bridge/int_raw.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("underrun", &format_args!("{}", self.underrun().bit()))
+            .field("underrun", &self.underrun())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - the raw interrupt status of dpi_underrun"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/int_st.rs b/esp32p4/src/mipi_dsi_bridge/int_st.rs
index f75999f597..a7fe0787af 100644
--- a/esp32p4/src/mipi_dsi_bridge/int_st.rs
+++ b/esp32p4/src/mipi_dsi_bridge/int_st.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("underrun", &format_args!("{}", self.underrun().bit()))
+            .field("underrun", &self.underrun())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "dsi_bridge masked interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/mipi_dsi_bridge/mem_aux_ctrl.rs b/esp32p4/src/mipi_dsi_bridge/mem_aux_ctrl.rs
index 46620a6789..f4edfe4266 100644
--- a/esp32p4/src/mipi_dsi_bridge/mem_aux_ctrl.rs
+++ b/esp32p4/src/mipi_dsi_bridge/mem_aux_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_AUX_CTRL")
-            .field(
-                "dsi_mem_aux_ctrl",
-                &format_args!("{}", self.dsi_mem_aux_ctrl().bits()),
-            )
+            .field("dsi_mem_aux_ctrl", &self.dsi_mem_aux_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_AUX_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - this field configures dsi_bridge fifo memory aux ctrl"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/mem_clk_ctrl.rs b/esp32p4/src/mipi_dsi_bridge/mem_clk_ctrl.rs
index dcf0748fef..3ea2b10453 100644
--- a/esp32p4/src/mipi_dsi_bridge/mem_clk_ctrl.rs
+++ b/esp32p4/src/mipi_dsi_bridge/mem_clk_ctrl.rs
@@ -28,21 +28,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("MEM_CLK_CTRL")
             .field(
                 "dsi_bridge_mem_clk_force_on",
-                &format_args!("{}", self.dsi_bridge_mem_clk_force_on().bit()),
-            )
-            .field(
-                "dsi_mem_clk_force_on",
-                &format_args!("{}", self.dsi_mem_clk_force_on().bit()),
+                &self.dsi_bridge_mem_clk_force_on(),
             )
+            .field("dsi_mem_clk_force_on", &self.dsi_mem_clk_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CLK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/phy_hs_loopback_ctrl.rs b/esp32p4/src/mipi_dsi_bridge/phy_hs_loopback_ctrl.rs
index 2ebd7c9232..300bcd9d9f 100644
--- a/esp32p4/src/mipi_dsi_bridge/phy_hs_loopback_ctrl.rs
+++ b/esp32p4/src/mipi_dsi_bridge/phy_hs_loopback_ctrl.rs
@@ -96,55 +96,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_HS_LOOPBACK_CTRL")
-            .field(
-                "phy_hs_txdatahs_1",
-                &format_args!("{}", self.phy_hs_txdatahs_1().bits()),
-            )
-            .field(
-                "phy_hs_txrequestdatahs_1",
-                &format_args!("{}", self.phy_hs_txrequestdatahs_1().bit()),
-            )
-            .field(
-                "phy_hs_basedir_1",
-                &format_args!("{}", self.phy_hs_basedir_1().bit()),
-            )
-            .field(
-                "phy_hs_txdatahs_0",
-                &format_args!("{}", self.phy_hs_txdatahs_0().bits()),
-            )
-            .field(
-                "phy_hs_txrequestdatahs_0",
-                &format_args!("{}", self.phy_hs_txrequestdatahs_0().bit()),
-            )
-            .field(
-                "phy_hs_basedir_0",
-                &format_args!("{}", self.phy_hs_basedir_0().bit()),
-            )
-            .field(
-                "phy_hs_txrequesthsclk",
-                &format_args!("{}", self.phy_hs_txrequesthsclk().bit()),
-            )
+            .field("phy_hs_txdatahs_1", &self.phy_hs_txdatahs_1())
+            .field("phy_hs_txrequestdatahs_1", &self.phy_hs_txrequestdatahs_1())
+            .field("phy_hs_basedir_1", &self.phy_hs_basedir_1())
+            .field("phy_hs_txdatahs_0", &self.phy_hs_txdatahs_0())
+            .field("phy_hs_txrequestdatahs_0", &self.phy_hs_txrequestdatahs_0())
+            .field("phy_hs_basedir_0", &self.phy_hs_basedir_0())
+            .field("phy_hs_txrequesthsclk", &self.phy_hs_txrequesthsclk())
             .field(
                 "phy_hs_loopback_check_done",
-                &format_args!("{}", self.phy_hs_loopback_check_done().bit()),
-            )
-            .field(
-                "phy_hs_loopback_en",
-                &format_args!("{}", self.phy_hs_loopback_en().bit()),
-            )
-            .field(
-                "phy_hs_loopback_ok",
-                &format_args!("{}", self.phy_hs_loopback_ok().bit()),
+                &self.phy_hs_loopback_check_done(),
             )
+            .field("phy_hs_loopback_en", &self.phy_hs_loopback_en())
+            .field("phy_hs_loopback_ok", &self.phy_hs_loopback_ok())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_HS_LOOPBACK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - txdatahs_1 ctrl when enable dsi phy hs_loopback_test"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/phy_loopback_cnt.rs b/esp32p4/src/mipi_dsi_bridge/phy_loopback_cnt.rs
index 7a1c904569..cebdba4da5 100644
--- a/esp32p4/src/mipi_dsi_bridge/phy_loopback_cnt.rs
+++ b/esp32p4/src/mipi_dsi_bridge/phy_loopback_cnt.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_LOOPBACK_CNT")
-            .field(
-                "phy_hs_check_cnt_th",
-                &format_args!("{}", self.phy_hs_check_cnt_th().bits()),
-            )
-            .field(
-                "phy_lp_check_cnt_th",
-                &format_args!("{}", self.phy_lp_check_cnt_th().bits()),
-            )
+            .field("phy_hs_check_cnt_th", &self.phy_hs_check_cnt_th())
+            .field("phy_lp_check_cnt_th", &self.phy_lp_check_cnt_th())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_LOOPBACK_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - hs_loopback test check cnt"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/phy_lp_loopback_ctrl.rs b/esp32p4/src/mipi_dsi_bridge/phy_lp_loopback_ctrl.rs
index 59d711573c..37e71cea3b 100644
--- a/esp32p4/src/mipi_dsi_bridge/phy_lp_loopback_ctrl.rs
+++ b/esp32p4/src/mipi_dsi_bridge/phy_lp_loopback_ctrl.rs
@@ -123,67 +123,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_LP_LOOPBACK_CTRL")
-            .field(
-                "phy_lp_txdataesc_1",
-                &format_args!("{}", self.phy_lp_txdataesc_1().bits()),
-            )
-            .field(
-                "phy_lp_txrequestesc_1",
-                &format_args!("{}", self.phy_lp_txrequestesc_1().bit()),
-            )
-            .field(
-                "phy_lp_txvalidesc_1",
-                &format_args!("{}", self.phy_lp_txvalidesc_1().bit()),
-            )
-            .field(
-                "phy_lp_txlpdtesc_1",
-                &format_args!("{}", self.phy_lp_txlpdtesc_1().bit()),
-            )
-            .field(
-                "phy_lp_basedir_1",
-                &format_args!("{}", self.phy_lp_basedir_1().bit()),
-            )
-            .field(
-                "phy_lp_txdataesc_0",
-                &format_args!("{}", self.phy_lp_txdataesc_0().bits()),
-            )
-            .field(
-                "phy_lp_txrequestesc_0",
-                &format_args!("{}", self.phy_lp_txrequestesc_0().bit()),
-            )
-            .field(
-                "phy_lp_txvalidesc_0",
-                &format_args!("{}", self.phy_lp_txvalidesc_0().bit()),
-            )
-            .field(
-                "phy_lp_txlpdtesc_0",
-                &format_args!("{}", self.phy_lp_txlpdtesc_0().bit()),
-            )
-            .field(
-                "phy_lp_basedir_0",
-                &format_args!("{}", self.phy_lp_basedir_0().bit()),
-            )
+            .field("phy_lp_txdataesc_1", &self.phy_lp_txdataesc_1())
+            .field("phy_lp_txrequestesc_1", &self.phy_lp_txrequestesc_1())
+            .field("phy_lp_txvalidesc_1", &self.phy_lp_txvalidesc_1())
+            .field("phy_lp_txlpdtesc_1", &self.phy_lp_txlpdtesc_1())
+            .field("phy_lp_basedir_1", &self.phy_lp_basedir_1())
+            .field("phy_lp_txdataesc_0", &self.phy_lp_txdataesc_0())
+            .field("phy_lp_txrequestesc_0", &self.phy_lp_txrequestesc_0())
+            .field("phy_lp_txvalidesc_0", &self.phy_lp_txvalidesc_0())
+            .field("phy_lp_txlpdtesc_0", &self.phy_lp_txlpdtesc_0())
+            .field("phy_lp_basedir_0", &self.phy_lp_basedir_0())
             .field(
                 "phy_lp_loopback_check_done",
-                &format_args!("{}", self.phy_lp_loopback_check_done().bit()),
-            )
-            .field(
-                "phy_lp_loopback_en",
-                &format_args!("{}", self.phy_lp_loopback_en().bit()),
-            )
-            .field(
-                "phy_lp_loopback_ok",
-                &format_args!("{}", self.phy_lp_loopback_ok().bit()),
+                &self.phy_lp_loopback_check_done(),
             )
+            .field("phy_lp_loopback_en", &self.phy_lp_loopback_en())
+            .field("phy_lp_loopback_ok", &self.phy_lp_loopback_ok())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_LP_LOOPBACK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - txdataesc_1 ctrl when enable dsi phy lp_loopback_test"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/pixel_type.rs b/esp32p4/src/mipi_dsi_bridge/pixel_type.rs
index 56f9d71dec..53585e505d 100644
--- a/esp32p4/src/mipi_dsi_bridge/pixel_type.rs
+++ b/esp32p4/src/mipi_dsi_bridge/pixel_type.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIXEL_TYPE")
-            .field("raw_type", &format_args!("{}", self.raw_type().bits()))
-            .field("dpi_config", &format_args!("{}", self.dpi_config().bits()))
-            .field(
-                "data_in_type",
-                &format_args!("{}", self.data_in_type().bit()),
-            )
+            .field("raw_type", &self.raw_type())
+            .field("dpi_config", &self.dpi_config())
+            .field("data_in_type", &self.data_in_type())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIXEL_TYPE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - this field configures the pixel type. 0: rgb888, 1:rgb666, 2:rgb565"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/raw_buf_almost_empty_thrd.rs b/esp32p4/src/mipi_dsi_bridge/raw_buf_almost_empty_thrd.rs
index 39d274c071..7cff6a30ef 100644
--- a/esp32p4/src/mipi_dsi_bridge/raw_buf_almost_empty_thrd.rs
+++ b/esp32p4/src/mipi_dsi_bridge/raw_buf_almost_empty_thrd.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("RAW_BUF_ALMOST_EMPTY_THRD")
             .field(
                 "dsi_raw_buf_almost_empty_thrd",
-                &format_args!("{}", self.dsi_raw_buf_almost_empty_thrd().bits()),
+                &self.dsi_raw_buf_almost_empty_thrd(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_BUF_ALMOST_EMPTY_THRD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - this field configures the fifo almost empty threshold, is valid only when dmac as flow controller"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/raw_buf_credit_ctl.rs b/esp32p4/src/mipi_dsi_bridge/raw_buf_credit_ctl.rs
index fec1da3d33..fe87ac35fc 100644
--- a/esp32p4/src/mipi_dsi_bridge/raw_buf_credit_ctl.rs
+++ b/esp32p4/src/mipi_dsi_bridge/raw_buf_credit_ctl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RAW_BUF_CREDIT_CTL")
-            .field(
-                "credit_thrd",
-                &format_args!("{}", self.credit_thrd().bits()),
-            )
-            .field(
-                "credit_burst_thrd",
-                &format_args!("{}", self.credit_burst_thrd().bits()),
-            )
-            .field(
-                "credit_reset",
-                &format_args!("{}", self.credit_reset().bit()),
-            )
+            .field("credit_thrd", &self.credit_thrd())
+            .field("credit_burst_thrd", &self.credit_burst_thrd())
+            .field("credit_reset", &self.credit_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_BUF_CREDIT_CTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - this field configures the threshold whether dsi_bridge fifo can receive one more 64-bit, valid only when dsi_bridge as flow controller"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/raw_num_cfg.rs b/esp32p4/src/mipi_dsi_bridge/raw_num_cfg.rs
index b0b7282285..a4c903510b 100644
--- a/esp32p4/src/mipi_dsi_bridge/raw_num_cfg.rs
+++ b/esp32p4/src/mipi_dsi_bridge/raw_num_cfg.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RAW_NUM_CFG")
-            .field(
-                "raw_num_total",
-                &format_args!("{}", self.raw_num_total().bits()),
-            )
-            .field(
-                "unalign_64bit_en",
-                &format_args!("{}", self.unalign_64bit_en().bit()),
-            )
+            .field("raw_num_total", &self.raw_num_total())
+            .field("unalign_64bit_en", &self.unalign_64bit_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_NUM_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - this field configures number of total pix bits/64"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/rdn_eco_cs.rs b/esp32p4/src/mipi_dsi_bridge/rdn_eco_cs.rs
index 5f1be9e16a..4634d1e862 100644
--- a/esp32p4/src/mipi_dsi_bridge/rdn_eco_cs.rs
+++ b/esp32p4/src/mipi_dsi_bridge/rdn_eco_cs.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDN_ECO_CS")
-            .field("rdn_eco_en", &format_args!("{}", self.rdn_eco_en().bit()))
-            .field(
-                "rdn_eco_result",
-                &format_args!("{}", self.rdn_eco_result().bit()),
-            )
+            .field("rdn_eco_en", &self.rdn_eco_en())
+            .field("rdn_eco_result", &self.rdn_eco_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDN_ECO_CS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - rdn_eco_en"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/rdn_eco_high.rs b/esp32p4/src/mipi_dsi_bridge/rdn_eco_high.rs
index 2f9b7729d3..4910cace47 100644
--- a/esp32p4/src/mipi_dsi_bridge/rdn_eco_high.rs
+++ b/esp32p4/src/mipi_dsi_bridge/rdn_eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDN_ECO_HIGH")
-            .field(
-                "rdn_eco_high",
-                &format_args!("{}", self.rdn_eco_high().bits()),
-            )
+            .field("rdn_eco_high", &self.rdn_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDN_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - rdn_eco_high"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/rdn_eco_low.rs b/esp32p4/src/mipi_dsi_bridge/rdn_eco_low.rs
index 967213ddc6..86d1465c6b 100644
--- a/esp32p4/src/mipi_dsi_bridge/rdn_eco_low.rs
+++ b/esp32p4/src/mipi_dsi_bridge/rdn_eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDN_ECO_LOW")
-            .field(
-                "rdn_eco_low",
-                &format_args!("{}", self.rdn_eco_low().bits()),
-            )
+            .field("rdn_eco_low", &self.rdn_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDN_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - rdn_eco_low"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_bridge/yuv_cfg.rs b/esp32p4/src/mipi_dsi_bridge/yuv_cfg.rs
index 9a729f9b17..87afdf27d6 100644
--- a/esp32p4/src/mipi_dsi_bridge/yuv_cfg.rs
+++ b/esp32p4/src/mipi_dsi_bridge/yuv_cfg.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("YUV_CFG")
-            .field("protocal", &format_args!("{}", self.protocal().bit()))
-            .field(
-                "yuv_pix_endian",
-                &format_args!("{}", self.yuv_pix_endian().bit()),
-            )
-            .field(
-                "yuv422_format",
-                &format_args!("{}", self.yuv422_format().bits()),
-            )
+            .field("protocal", &self.protocal())
+            .field("yuv_pix_endian", &self.yuv_pix_endian())
+            .field("yuv422_format", &self.yuv422_format())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<YUV_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit configures yuv protoocl, 0: bt.601, 1: bt.709"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/bta_to_cnt.rs b/esp32p4/src/mipi_dsi_host/bta_to_cnt.rs
index 3394fc4e70..3cdc1193bd 100644
--- a/esp32p4/src/mipi_dsi_host/bta_to_cnt.rs
+++ b/esp32p4/src/mipi_dsi_host/bta_to_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BTA_TO_CNT")
-            .field("bta_to_cnt", &format_args!("{}", self.bta_to_cnt().bits()))
+            .field("bta_to_cnt", &self.bta_to_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BTA_TO_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/clkmgr_cfg.rs b/esp32p4/src/mipi_dsi_host/clkmgr_cfg.rs
index 8aa20e23d4..30fe28ac58 100644
--- a/esp32p4/src/mipi_dsi_host/clkmgr_cfg.rs
+++ b/esp32p4/src/mipi_dsi_host/clkmgr_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKMGR_CFG")
-            .field(
-                "tx_esc_clk_division",
-                &format_args!("{}", self.tx_esc_clk_division().bits()),
-            )
-            .field(
-                "to_clk_division",
-                &format_args!("{}", self.to_clk_division().bits()),
-            )
+            .field("tx_esc_clk_division", &self.tx_esc_clk_division())
+            .field("to_clk_division", &self.to_clk_division())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKMGR_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/cmd_mode_cfg.rs b/esp32p4/src/mipi_dsi_host/cmd_mode_cfg.rs
index 31f11f08de..b2b70e9f1c 100644
--- a/esp32p4/src/mipi_dsi_host/cmd_mode_cfg.rs
+++ b/esp32p4/src/mipi_dsi_host/cmd_mode_cfg.rs
@@ -134,59 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD_MODE_CFG")
-            .field("tear_fx_en", &format_args!("{}", self.tear_fx_en().bit()))
-            .field("ack_rqst_en", &format_args!("{}", self.ack_rqst_en().bit()))
-            .field(
-                "gen_sw_0p_tx",
-                &format_args!("{}", self.gen_sw_0p_tx().bit()),
-            )
-            .field(
-                "gen_sw_1p_tx",
-                &format_args!("{}", self.gen_sw_1p_tx().bit()),
-            )
-            .field(
-                "gen_sw_2p_tx",
-                &format_args!("{}", self.gen_sw_2p_tx().bit()),
-            )
-            .field(
-                "gen_sr_0p_tx",
-                &format_args!("{}", self.gen_sr_0p_tx().bit()),
-            )
-            .field(
-                "gen_sr_1p_tx",
-                &format_args!("{}", self.gen_sr_1p_tx().bit()),
-            )
-            .field(
-                "gen_sr_2p_tx",
-                &format_args!("{}", self.gen_sr_2p_tx().bit()),
-            )
-            .field("gen_lw_tx", &format_args!("{}", self.gen_lw_tx().bit()))
-            .field(
-                "dcs_sw_0p_tx",
-                &format_args!("{}", self.dcs_sw_0p_tx().bit()),
-            )
-            .field(
-                "dcs_sw_1p_tx",
-                &format_args!("{}", self.dcs_sw_1p_tx().bit()),
-            )
-            .field(
-                "dcs_sr_0p_tx",
-                &format_args!("{}", self.dcs_sr_0p_tx().bit()),
-            )
-            .field("dcs_lw_tx", &format_args!("{}", self.dcs_lw_tx().bit()))
-            .field(
-                "max_rd_pkt_size",
-                &format_args!("{}", self.max_rd_pkt_size().bit()),
-            )
+            .field("tear_fx_en", &self.tear_fx_en())
+            .field("ack_rqst_en", &self.ack_rqst_en())
+            .field("gen_sw_0p_tx", &self.gen_sw_0p_tx())
+            .field("gen_sw_1p_tx", &self.gen_sw_1p_tx())
+            .field("gen_sw_2p_tx", &self.gen_sw_2p_tx())
+            .field("gen_sr_0p_tx", &self.gen_sr_0p_tx())
+            .field("gen_sr_1p_tx", &self.gen_sr_1p_tx())
+            .field("gen_sr_2p_tx", &self.gen_sr_2p_tx())
+            .field("gen_lw_tx", &self.gen_lw_tx())
+            .field("dcs_sw_0p_tx", &self.dcs_sw_0p_tx())
+            .field("dcs_sw_1p_tx", &self.dcs_sw_1p_tx())
+            .field("dcs_sr_0p_tx", &self.dcs_sr_0p_tx())
+            .field("dcs_lw_tx", &self.dcs_lw_tx())
+            .field("max_rd_pkt_size", &self.max_rd_pkt_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_MODE_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/cmd_pkt_status.rs b/esp32p4/src/mipi_dsi_host/cmd_pkt_status.rs
index 4028c27c1f..f2086d56c6 100644
--- a/esp32p4/src/mipi_dsi_host/cmd_pkt_status.rs
+++ b/esp32p4/src/mipi_dsi_host/cmd_pkt_status.rs
@@ -83,59 +83,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD_PKT_STATUS")
-            .field(
-                "gen_cmd_empty",
-                &format_args!("{}", self.gen_cmd_empty().bit()),
-            )
-            .field(
-                "gen_cmd_full",
-                &format_args!("{}", self.gen_cmd_full().bit()),
-            )
-            .field(
-                "gen_pld_w_empty",
-                &format_args!("{}", self.gen_pld_w_empty().bit()),
-            )
-            .field(
-                "gen_pld_w_full",
-                &format_args!("{}", self.gen_pld_w_full().bit()),
-            )
-            .field(
-                "gen_pld_r_empty",
-                &format_args!("{}", self.gen_pld_r_empty().bit()),
-            )
-            .field(
-                "gen_pld_r_full",
-                &format_args!("{}", self.gen_pld_r_full().bit()),
-            )
-            .field(
-                "gen_rd_cmd_busy",
-                &format_args!("{}", self.gen_rd_cmd_busy().bit()),
-            )
-            .field(
-                "gen_buff_cmd_empty",
-                &format_args!("{}", self.gen_buff_cmd_empty().bit()),
-            )
-            .field(
-                "gen_buff_cmd_full",
-                &format_args!("{}", self.gen_buff_cmd_full().bit()),
-            )
-            .field(
-                "gen_buff_pld_empty",
-                &format_args!("{}", self.gen_buff_pld_empty().bit()),
-            )
-            .field(
-                "gen_buff_pld_full",
-                &format_args!("{}", self.gen_buff_pld_full().bit()),
-            )
+            .field("gen_cmd_empty", &self.gen_cmd_empty())
+            .field("gen_cmd_full", &self.gen_cmd_full())
+            .field("gen_pld_w_empty", &self.gen_pld_w_empty())
+            .field("gen_pld_w_full", &self.gen_pld_w_full())
+            .field("gen_pld_r_empty", &self.gen_pld_r_empty())
+            .field("gen_pld_r_full", &self.gen_pld_r_full())
+            .field("gen_rd_cmd_busy", &self.gen_rd_cmd_busy())
+            .field("gen_buff_cmd_empty", &self.gen_buff_cmd_empty())
+            .field("gen_buff_cmd_full", &self.gen_buff_cmd_full())
+            .field("gen_buff_pld_empty", &self.gen_buff_pld_empty())
+            .field("gen_buff_pld_full", &self.gen_buff_pld_full())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_PKT_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd_pkt_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CMD_PKT_STATUS_SPEC;
 impl crate::RegisterSpec for CMD_PKT_STATUS_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/dbi_cfg.rs b/esp32p4/src/mipi_dsi_host/dbi_cfg.rs
index a8588d41f2..887ff4a5ae 100644
--- a/esp32p4/src/mipi_dsi_host/dbi_cfg.rs
+++ b/esp32p4/src/mipi_dsi_host/dbi_cfg.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBI_CFG")
-            .field(
-                "in_dbi_conf",
-                &format_args!("{}", self.in_dbi_conf().bits()),
-            )
-            .field(
-                "out_dbi_conf",
-                &format_args!("{}", self.out_dbi_conf().bits()),
-            )
-            .field(
-                "lut_size_conf",
-                &format_args!("{}", self.lut_size_conf().bits()),
-            )
+            .field("in_dbi_conf", &self.in_dbi_conf())
+            .field("out_dbi_conf", &self.out_dbi_conf())
+            .field("lut_size_conf", &self.lut_size_conf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBI_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/dbi_cmdsize.rs b/esp32p4/src/mipi_dsi_host/dbi_cmdsize.rs
index 2b149c195d..b7329f3264 100644
--- a/esp32p4/src/mipi_dsi_host/dbi_cmdsize.rs
+++ b/esp32p4/src/mipi_dsi_host/dbi_cmdsize.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBI_CMDSIZE")
-            .field(
-                "wr_cmd_size",
-                &format_args!("{}", self.wr_cmd_size().bits()),
-            )
-            .field(
-                "allowed_cmd_size",
-                &format_args!("{}", self.allowed_cmd_size().bits()),
-            )
+            .field("wr_cmd_size", &self.wr_cmd_size())
+            .field("allowed_cmd_size", &self.allowed_cmd_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBI_CMDSIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/dbi_partitioning_en.rs b/esp32p4/src/mipi_dsi_host/dbi_partitioning_en.rs
index 9528d72cde..27048d1afa 100644
--- a/esp32p4/src/mipi_dsi_host/dbi_partitioning_en.rs
+++ b/esp32p4/src/mipi_dsi_host/dbi_partitioning_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBI_PARTITIONING_EN")
-            .field(
-                "partitioning_en",
-                &format_args!("{}", self.partitioning_en().bit()),
-            )
+            .field("partitioning_en", &self.partitioning_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBI_PARTITIONING_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/dbi_vcid.rs b/esp32p4/src/mipi_dsi_host/dbi_vcid.rs
index f915b719f4..5b72766769 100644
--- a/esp32p4/src/mipi_dsi_host/dbi_vcid.rs
+++ b/esp32p4/src/mipi_dsi_host/dbi_vcid.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBI_VCID")
-            .field("dbi_vcid", &format_args!("{}", self.dbi_vcid().bits()))
+            .field("dbi_vcid", &self.dbi_vcid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBI_VCID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/dpi_cfg_pol.rs b/esp32p4/src/mipi_dsi_host/dpi_cfg_pol.rs
index af1f847502..73bb42ff7f 100644
--- a/esp32p4/src/mipi_dsi_host/dpi_cfg_pol.rs
+++ b/esp32p4/src/mipi_dsi_host/dpi_cfg_pol.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPI_CFG_POL")
-            .field(
-                "dataen_active_low",
-                &format_args!("{}", self.dataen_active_low().bit()),
-            )
-            .field(
-                "vsync_active_low",
-                &format_args!("{}", self.vsync_active_low().bit()),
-            )
-            .field(
-                "hsync_active_low",
-                &format_args!("{}", self.hsync_active_low().bit()),
-            )
-            .field(
-                "shutd_active_low",
-                &format_args!("{}", self.shutd_active_low().bit()),
-            )
-            .field(
-                "colorm_active_low",
-                &format_args!("{}", self.colorm_active_low().bit()),
-            )
+            .field("dataen_active_low", &self.dataen_active_low())
+            .field("vsync_active_low", &self.vsync_active_low())
+            .field("hsync_active_low", &self.hsync_active_low())
+            .field("shutd_active_low", &self.shutd_active_low())
+            .field("colorm_active_low", &self.colorm_active_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPI_CFG_POL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/dpi_color_coding.rs b/esp32p4/src/mipi_dsi_host/dpi_color_coding.rs
index 8fc11de41b..352c2381a6 100644
--- a/esp32p4/src/mipi_dsi_host/dpi_color_coding.rs
+++ b/esp32p4/src/mipi_dsi_host/dpi_color_coding.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPI_COLOR_CODING")
-            .field(
-                "dpi_color_coding",
-                &format_args!("{}", self.dpi_color_coding().bits()),
-            )
-            .field(
-                "loosely18_en",
-                &format_args!("{}", self.loosely18_en().bit()),
-            )
+            .field("dpi_color_coding", &self.dpi_color_coding())
+            .field("loosely18_en", &self.loosely18_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPI_COLOR_CODING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/dpi_color_coding_act.rs b/esp32p4/src/mipi_dsi_host/dpi_color_coding_act.rs
index 546b497403..0acfb1ea3e 100644
--- a/esp32p4/src/mipi_dsi_host/dpi_color_coding_act.rs
+++ b/esp32p4/src/mipi_dsi_host/dpi_color_coding_act.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPI_COLOR_CODING_ACT")
-            .field(
-                "dpi_color_coding_act",
-                &format_args!("{}", self.dpi_color_coding_act().bits()),
-            )
-            .field(
-                "loosely18_en_act",
-                &format_args!("{}", self.loosely18_en_act().bit()),
-            )
+            .field("dpi_color_coding_act", &self.dpi_color_coding_act())
+            .field("loosely18_en_act", &self.loosely18_en_act())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPI_COLOR_CODING_ACT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_color_coding_act::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DPI_COLOR_CODING_ACT_SPEC;
 impl crate::RegisterSpec for DPI_COLOR_CODING_ACT_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/dpi_lp_cmd_tim.rs b/esp32p4/src/mipi_dsi_host/dpi_lp_cmd_tim.rs
index ec7bbef8d9..f5c8bbe83e 100644
--- a/esp32p4/src/mipi_dsi_host/dpi_lp_cmd_tim.rs
+++ b/esp32p4/src/mipi_dsi_host/dpi_lp_cmd_tim.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPI_LP_CMD_TIM")
-            .field(
-                "invact_lpcmd_time",
-                &format_args!("{}", self.invact_lpcmd_time().bits()),
-            )
-            .field(
-                "outvact_lpcmd_time",
-                &format_args!("{}", self.outvact_lpcmd_time().bits()),
-            )
+            .field("invact_lpcmd_time", &self.invact_lpcmd_time())
+            .field("outvact_lpcmd_time", &self.outvact_lpcmd_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPI_LP_CMD_TIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/dpi_lp_cmd_tim_act.rs b/esp32p4/src/mipi_dsi_host/dpi_lp_cmd_tim_act.rs
index b8dae94d05..7633299cd9 100644
--- a/esp32p4/src/mipi_dsi_host/dpi_lp_cmd_tim_act.rs
+++ b/esp32p4/src/mipi_dsi_host/dpi_lp_cmd_tim_act.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPI_LP_CMD_TIM_ACT")
-            .field(
-                "invact_lpcmd_time_act",
-                &format_args!("{}", self.invact_lpcmd_time_act().bits()),
-            )
-            .field(
-                "outvact_lpcmd_time_act",
-                &format_args!("{}", self.outvact_lpcmd_time_act().bits()),
-            )
+            .field("invact_lpcmd_time_act", &self.invact_lpcmd_time_act())
+            .field("outvact_lpcmd_time_act", &self.outvact_lpcmd_time_act())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPI_LP_CMD_TIM_ACT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_lp_cmd_tim_act::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DPI_LP_CMD_TIM_ACT_SPEC;
 impl crate::RegisterSpec for DPI_LP_CMD_TIM_ACT_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/dpi_vcid.rs b/esp32p4/src/mipi_dsi_host/dpi_vcid.rs
index 9ee17681de..c8cb4667e9 100644
--- a/esp32p4/src/mipi_dsi_host/dpi_vcid.rs
+++ b/esp32p4/src/mipi_dsi_host/dpi_vcid.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPI_VCID")
-            .field("dpi_vcid", &format_args!("{}", self.dpi_vcid().bits()))
+            .field("dpi_vcid", &self.dpi_vcid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPI_VCID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/dpi_vcid_act.rs b/esp32p4/src/mipi_dsi_host/dpi_vcid_act.rs
index e68e209bf6..6a4114bd84 100644
--- a/esp32p4/src/mipi_dsi_host/dpi_vcid_act.rs
+++ b/esp32p4/src/mipi_dsi_host/dpi_vcid_act.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPI_VCID_ACT")
-            .field(
-                "dpi_vcid_act",
-                &format_args!("{}", self.dpi_vcid_act().bits()),
-            )
+            .field("dpi_vcid_act", &self.dpi_vcid_act())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPI_VCID_ACT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpi_vcid_act::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DPI_VCID_ACT_SPEC;
 impl crate::RegisterSpec for DPI_VCID_ACT_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/dsc_parameter.rs b/esp32p4/src/mipi_dsi_host/dsc_parameter.rs
index 3fe9393df1..79b6d808cb 100644
--- a/esp32p4/src/mipi_dsi_host/dsc_parameter.rs
+++ b/esp32p4/src/mipi_dsi_host/dsc_parameter.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSC_PARAMETER")
-            .field(
-                "compression_mode",
-                &format_args!("{}", self.compression_mode().bit()),
-            )
-            .field(
-                "compress_algo",
-                &format_args!("{}", self.compress_algo().bits()),
-            )
-            .field("pps_sel", &format_args!("{}", self.pps_sel().bits()))
+            .field("compression_mode", &self.compression_mode())
+            .field("compress_algo", &self.compress_algo())
+            .field("pps_sel", &self.pps_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSC_PARAMETER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/edpi_cmd_size.rs b/esp32p4/src/mipi_dsi_host/edpi_cmd_size.rs
index f60d1e80b6..fdce6c15f5 100644
--- a/esp32p4/src/mipi_dsi_host/edpi_cmd_size.rs
+++ b/esp32p4/src/mipi_dsi_host/edpi_cmd_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDPI_CMD_SIZE")
-            .field(
-                "edpi_allowed_cmd_size",
-                &format_args!("{}", self.edpi_allowed_cmd_size().bits()),
-            )
+            .field("edpi_allowed_cmd_size", &self.edpi_allowed_cmd_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDPI_CMD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/edpi_te_hw_cfg.rs b/esp32p4/src/mipi_dsi_host/edpi_te_hw_cfg.rs
index 3c34dfb1c8..40ec0795c7 100644
--- a/esp32p4/src/mipi_dsi_host/edpi_te_hw_cfg.rs
+++ b/esp32p4/src/mipi_dsi_host/edpi_te_hw_cfg.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDPI_TE_HW_CFG")
-            .field(
-                "hw_tear_effect_on",
-                &format_args!("{}", self.hw_tear_effect_on().bit()),
-            )
-            .field(
-                "hw_tear_effect_gen",
-                &format_args!("{}", self.hw_tear_effect_gen().bit()),
-            )
-            .field(
-                "hw_set_scan_line",
-                &format_args!("{}", self.hw_set_scan_line().bit()),
-            )
-            .field(
-                "scan_line_parameter",
-                &format_args!("{}", self.scan_line_parameter().bits()),
-            )
+            .field("hw_tear_effect_on", &self.hw_tear_effect_on())
+            .field("hw_tear_effect_gen", &self.hw_tear_effect_gen())
+            .field("hw_set_scan_line", &self.hw_set_scan_line())
+            .field("scan_line_parameter", &self.scan_line_parameter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDPI_TE_HW_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/gen_hdr.rs b/esp32p4/src/mipi_dsi_host/gen_hdr.rs
index eb2fe1207a..7a005c867d 100644
--- a/esp32p4/src/mipi_dsi_host/gen_hdr.rs
+++ b/esp32p4/src/mipi_dsi_host/gen_hdr.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_HDR")
-            .field("gen_dt", &format_args!("{}", self.gen_dt().bits()))
-            .field("gen_vc", &format_args!("{}", self.gen_vc().bits()))
-            .field(
-                "gen_wc_lsbyte",
-                &format_args!("{}", self.gen_wc_lsbyte().bits()),
-            )
-            .field(
-                "gen_wc_msbyte",
-                &format_args!("{}", self.gen_wc_msbyte().bits()),
-            )
+            .field("gen_dt", &self.gen_dt())
+            .field("gen_vc", &self.gen_vc())
+            .field("gen_wc_lsbyte", &self.gen_wc_lsbyte())
+            .field("gen_wc_msbyte", &self.gen_wc_msbyte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_HDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/gen_pld_data.rs b/esp32p4/src/mipi_dsi_host/gen_pld_data.rs
index 6707cddd3f..9323643f15 100644
--- a/esp32p4/src/mipi_dsi_host/gen_pld_data.rs
+++ b/esp32p4/src/mipi_dsi_host/gen_pld_data.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_PLD_DATA")
-            .field("gen_pld_b1", &format_args!("{}", self.gen_pld_b1().bits()))
-            .field("gen_pld_b2", &format_args!("{}", self.gen_pld_b2().bits()))
-            .field("gen_pld_b3", &format_args!("{}", self.gen_pld_b3().bits()))
-            .field("gen_pld_b4", &format_args!("{}", self.gen_pld_b4().bits()))
+            .field("gen_pld_b1", &self.gen_pld_b1())
+            .field("gen_pld_b2", &self.gen_pld_b2())
+            .field("gen_pld_b3", &self.gen_pld_b3())
+            .field("gen_pld_b4", &self.gen_pld_b4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_PLD_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/gen_vcid.rs b/esp32p4/src/mipi_dsi_host/gen_vcid.rs
index e8e3d2e7c4..d96881dc2c 100644
--- a/esp32p4/src/mipi_dsi_host/gen_vcid.rs
+++ b/esp32p4/src/mipi_dsi_host/gen_vcid.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_VCID")
-            .field("rx", &format_args!("{}", self.rx().bits()))
-            .field("tear_auto", &format_args!("{}", self.tear_auto().bits()))
-            .field("tx_auto", &format_args!("{}", self.tx_auto().bits()))
+            .field("rx", &self.rx())
+            .field("tear_auto", &self.tear_auto())
+            .field("tx_auto", &self.tx_auto())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_VCID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/hs_rd_to_cnt.rs b/esp32p4/src/mipi_dsi_host/hs_rd_to_cnt.rs
index 1cb29dd708..342a2b4f44 100644
--- a/esp32p4/src/mipi_dsi_host/hs_rd_to_cnt.rs
+++ b/esp32p4/src/mipi_dsi_host/hs_rd_to_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HS_RD_TO_CNT")
-            .field(
-                "hs_rd_to_cnt",
-                &format_args!("{}", self.hs_rd_to_cnt().bits()),
-            )
+            .field("hs_rd_to_cnt", &self.hs_rd_to_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HS_RD_TO_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/hs_wr_to_cnt.rs b/esp32p4/src/mipi_dsi_host/hs_wr_to_cnt.rs
index baf320d566..50b55776e4 100644
--- a/esp32p4/src/mipi_dsi_host/hs_wr_to_cnt.rs
+++ b/esp32p4/src/mipi_dsi_host/hs_wr_to_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HS_WR_TO_CNT")
-            .field(
-                "hs_wr_to_cnt",
-                &format_args!("{}", self.hs_wr_to_cnt().bits()),
-            )
+            .field("hs_wr_to_cnt", &self.hs_wr_to_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HS_WR_TO_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/int_force0.rs b/esp32p4/src/mipi_dsi_host/int_force0.rs
index 1f2d99b0b8..6f41d4bc2e 100644
--- a/esp32p4/src/mipi_dsi_host/int_force0.rs
+++ b/esp32p4/src/mipi_dsi_host/int_force0.rs
@@ -197,99 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_FORCE0")
-            .field(
-                "force_ack_with_err_0",
-                &format_args!("{}", self.force_ack_with_err_0().bit()),
-            )
-            .field(
-                "force_ack_with_err_1",
-                &format_args!("{}", self.force_ack_with_err_1().bit()),
-            )
-            .field(
-                "force_ack_with_err_2",
-                &format_args!("{}", self.force_ack_with_err_2().bit()),
-            )
-            .field(
-                "force_ack_with_err_3",
-                &format_args!("{}", self.force_ack_with_err_3().bit()),
-            )
-            .field(
-                "force_ack_with_err_4",
-                &format_args!("{}", self.force_ack_with_err_4().bit()),
-            )
-            .field(
-                "force_ack_with_err_5",
-                &format_args!("{}", self.force_ack_with_err_5().bit()),
-            )
-            .field(
-                "force_ack_with_err_6",
-                &format_args!("{}", self.force_ack_with_err_6().bit()),
-            )
-            .field(
-                "force_ack_with_err_7",
-                &format_args!("{}", self.force_ack_with_err_7().bit()),
-            )
-            .field(
-                "force_ack_with_err_8",
-                &format_args!("{}", self.force_ack_with_err_8().bit()),
-            )
-            .field(
-                "force_ack_with_err_9",
-                &format_args!("{}", self.force_ack_with_err_9().bit()),
-            )
-            .field(
-                "force_ack_with_err_10",
-                &format_args!("{}", self.force_ack_with_err_10().bit()),
-            )
-            .field(
-                "force_ack_with_err_11",
-                &format_args!("{}", self.force_ack_with_err_11().bit()),
-            )
-            .field(
-                "force_ack_with_err_12",
-                &format_args!("{}", self.force_ack_with_err_12().bit()),
-            )
-            .field(
-                "force_ack_with_err_13",
-                &format_args!("{}", self.force_ack_with_err_13().bit()),
-            )
-            .field(
-                "force_ack_with_err_14",
-                &format_args!("{}", self.force_ack_with_err_14().bit()),
-            )
-            .field(
-                "force_ack_with_err_15",
-                &format_args!("{}", self.force_ack_with_err_15().bit()),
-            )
-            .field(
-                "force_dphy_errors_0",
-                &format_args!("{}", self.force_dphy_errors_0().bit()),
-            )
-            .field(
-                "force_dphy_errors_1",
-                &format_args!("{}", self.force_dphy_errors_1().bit()),
-            )
-            .field(
-                "force_dphy_errors_2",
-                &format_args!("{}", self.force_dphy_errors_2().bit()),
-            )
-            .field(
-                "force_dphy_errors_3",
-                &format_args!("{}", self.force_dphy_errors_3().bit()),
-            )
-            .field(
-                "force_dphy_errors_4",
-                &format_args!("{}", self.force_dphy_errors_4().bit()),
-            )
+            .field("force_ack_with_err_0", &self.force_ack_with_err_0())
+            .field("force_ack_with_err_1", &self.force_ack_with_err_1())
+            .field("force_ack_with_err_2", &self.force_ack_with_err_2())
+            .field("force_ack_with_err_3", &self.force_ack_with_err_3())
+            .field("force_ack_with_err_4", &self.force_ack_with_err_4())
+            .field("force_ack_with_err_5", &self.force_ack_with_err_5())
+            .field("force_ack_with_err_6", &self.force_ack_with_err_6())
+            .field("force_ack_with_err_7", &self.force_ack_with_err_7())
+            .field("force_ack_with_err_8", &self.force_ack_with_err_8())
+            .field("force_ack_with_err_9", &self.force_ack_with_err_9())
+            .field("force_ack_with_err_10", &self.force_ack_with_err_10())
+            .field("force_ack_with_err_11", &self.force_ack_with_err_11())
+            .field("force_ack_with_err_12", &self.force_ack_with_err_12())
+            .field("force_ack_with_err_13", &self.force_ack_with_err_13())
+            .field("force_ack_with_err_14", &self.force_ack_with_err_14())
+            .field("force_ack_with_err_15", &self.force_ack_with_err_15())
+            .field("force_dphy_errors_0", &self.force_dphy_errors_0())
+            .field("force_dphy_errors_1", &self.force_dphy_errors_1())
+            .field("force_dphy_errors_2", &self.force_dphy_errors_2())
+            .field("force_dphy_errors_3", &self.force_dphy_errors_3())
+            .field("force_dphy_errors_4", &self.force_dphy_errors_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_FORCE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/int_force1.rs b/esp32p4/src/mipi_dsi_host/int_force1.rs
index 9d3adabaea..a5dd115e66 100644
--- a/esp32p4/src/mipi_dsi_host/int_force1.rs
+++ b/esp32p4/src/mipi_dsi_host/int_force1.rs
@@ -134,71 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_FORCE1")
-            .field(
-                "force_to_hs_tx",
-                &format_args!("{}", self.force_to_hs_tx().bit()),
-            )
-            .field(
-                "force_to_lp_rx",
-                &format_args!("{}", self.force_to_lp_rx().bit()),
-            )
-            .field(
-                "force_ecc_single_err",
-                &format_args!("{}", self.force_ecc_single_err().bit()),
-            )
-            .field(
-                "force_ecc_milti_err",
-                &format_args!("{}", self.force_ecc_milti_err().bit()),
-            )
-            .field(
-                "force_crc_err",
-                &format_args!("{}", self.force_crc_err().bit()),
-            )
-            .field(
-                "force_pkt_size_err",
-                &format_args!("{}", self.force_pkt_size_err().bit()),
-            )
-            .field(
-                "force_eopt_err",
-                &format_args!("{}", self.force_eopt_err().bit()),
-            )
-            .field(
-                "force_dpi_pld_wr_err",
-                &format_args!("{}", self.force_dpi_pld_wr_err().bit()),
-            )
-            .field(
-                "force_gen_cmd_wr_err",
-                &format_args!("{}", self.force_gen_cmd_wr_err().bit()),
-            )
-            .field(
-                "force_gen_pld_wr_err",
-                &format_args!("{}", self.force_gen_pld_wr_err().bit()),
-            )
-            .field(
-                "force_gen_pld_send_err",
-                &format_args!("{}", self.force_gen_pld_send_err().bit()),
-            )
-            .field(
-                "force_gen_pld_rd_err",
-                &format_args!("{}", self.force_gen_pld_rd_err().bit()),
-            )
-            .field(
-                "force_gen_pld_recev_err",
-                &format_args!("{}", self.force_gen_pld_recev_err().bit()),
-            )
-            .field(
-                "force_dpi_buff_pld_under",
-                &format_args!("{}", self.force_dpi_buff_pld_under().bit()),
-            )
+            .field("force_to_hs_tx", &self.force_to_hs_tx())
+            .field("force_to_lp_rx", &self.force_to_lp_rx())
+            .field("force_ecc_single_err", &self.force_ecc_single_err())
+            .field("force_ecc_milti_err", &self.force_ecc_milti_err())
+            .field("force_crc_err", &self.force_crc_err())
+            .field("force_pkt_size_err", &self.force_pkt_size_err())
+            .field("force_eopt_err", &self.force_eopt_err())
+            .field("force_dpi_pld_wr_err", &self.force_dpi_pld_wr_err())
+            .field("force_gen_cmd_wr_err", &self.force_gen_cmd_wr_err())
+            .field("force_gen_pld_wr_err", &self.force_gen_pld_wr_err())
+            .field("force_gen_pld_send_err", &self.force_gen_pld_send_err())
+            .field("force_gen_pld_rd_err", &self.force_gen_pld_rd_err())
+            .field("force_gen_pld_recev_err", &self.force_gen_pld_recev_err())
+            .field("force_dpi_buff_pld_under", &self.force_dpi_buff_pld_under())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_FORCE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/int_msk0.rs b/esp32p4/src/mipi_dsi_host/int_msk0.rs
index 2676e59fd5..aad5deab42 100644
--- a/esp32p4/src/mipi_dsi_host/int_msk0.rs
+++ b/esp32p4/src/mipi_dsi_host/int_msk0.rs
@@ -197,99 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_MSK0")
-            .field(
-                "mask_ack_with_err_0",
-                &format_args!("{}", self.mask_ack_with_err_0().bit()),
-            )
-            .field(
-                "mask_ack_with_err_1",
-                &format_args!("{}", self.mask_ack_with_err_1().bit()),
-            )
-            .field(
-                "mask_ack_with_err_2",
-                &format_args!("{}", self.mask_ack_with_err_2().bit()),
-            )
-            .field(
-                "mask_ack_with_err_3",
-                &format_args!("{}", self.mask_ack_with_err_3().bit()),
-            )
-            .field(
-                "mask_ack_with_err_4",
-                &format_args!("{}", self.mask_ack_with_err_4().bit()),
-            )
-            .field(
-                "mask_ack_with_err_5",
-                &format_args!("{}", self.mask_ack_with_err_5().bit()),
-            )
-            .field(
-                "mask_ack_with_err_6",
-                &format_args!("{}", self.mask_ack_with_err_6().bit()),
-            )
-            .field(
-                "mask_ack_with_err_7",
-                &format_args!("{}", self.mask_ack_with_err_7().bit()),
-            )
-            .field(
-                "mask_ack_with_err_8",
-                &format_args!("{}", self.mask_ack_with_err_8().bit()),
-            )
-            .field(
-                "mask_ack_with_err_9",
-                &format_args!("{}", self.mask_ack_with_err_9().bit()),
-            )
-            .field(
-                "mask_ack_with_err_10",
-                &format_args!("{}", self.mask_ack_with_err_10().bit()),
-            )
-            .field(
-                "mask_ack_with_err_11",
-                &format_args!("{}", self.mask_ack_with_err_11().bit()),
-            )
-            .field(
-                "mask_ack_with_err_12",
-                &format_args!("{}", self.mask_ack_with_err_12().bit()),
-            )
-            .field(
-                "mask_ack_with_err_13",
-                &format_args!("{}", self.mask_ack_with_err_13().bit()),
-            )
-            .field(
-                "mask_ack_with_err_14",
-                &format_args!("{}", self.mask_ack_with_err_14().bit()),
-            )
-            .field(
-                "mask_ack_with_err_15",
-                &format_args!("{}", self.mask_ack_with_err_15().bit()),
-            )
-            .field(
-                "mask_dphy_errors_0",
-                &format_args!("{}", self.mask_dphy_errors_0().bit()),
-            )
-            .field(
-                "mask_dphy_errors_1",
-                &format_args!("{}", self.mask_dphy_errors_1().bit()),
-            )
-            .field(
-                "mask_dphy_errors_2",
-                &format_args!("{}", self.mask_dphy_errors_2().bit()),
-            )
-            .field(
-                "mask_dphy_errors_3",
-                &format_args!("{}", self.mask_dphy_errors_3().bit()),
-            )
-            .field(
-                "mask_dphy_errors_4",
-                &format_args!("{}", self.mask_dphy_errors_4().bit()),
-            )
+            .field("mask_ack_with_err_0", &self.mask_ack_with_err_0())
+            .field("mask_ack_with_err_1", &self.mask_ack_with_err_1())
+            .field("mask_ack_with_err_2", &self.mask_ack_with_err_2())
+            .field("mask_ack_with_err_3", &self.mask_ack_with_err_3())
+            .field("mask_ack_with_err_4", &self.mask_ack_with_err_4())
+            .field("mask_ack_with_err_5", &self.mask_ack_with_err_5())
+            .field("mask_ack_with_err_6", &self.mask_ack_with_err_6())
+            .field("mask_ack_with_err_7", &self.mask_ack_with_err_7())
+            .field("mask_ack_with_err_8", &self.mask_ack_with_err_8())
+            .field("mask_ack_with_err_9", &self.mask_ack_with_err_9())
+            .field("mask_ack_with_err_10", &self.mask_ack_with_err_10())
+            .field("mask_ack_with_err_11", &self.mask_ack_with_err_11())
+            .field("mask_ack_with_err_12", &self.mask_ack_with_err_12())
+            .field("mask_ack_with_err_13", &self.mask_ack_with_err_13())
+            .field("mask_ack_with_err_14", &self.mask_ack_with_err_14())
+            .field("mask_ack_with_err_15", &self.mask_ack_with_err_15())
+            .field("mask_dphy_errors_0", &self.mask_dphy_errors_0())
+            .field("mask_dphy_errors_1", &self.mask_dphy_errors_1())
+            .field("mask_dphy_errors_2", &self.mask_dphy_errors_2())
+            .field("mask_dphy_errors_3", &self.mask_dphy_errors_3())
+            .field("mask_dphy_errors_4", &self.mask_dphy_errors_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_MSK0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/int_msk1.rs b/esp32p4/src/mipi_dsi_host/int_msk1.rs
index 05834fda9c..766d477d3b 100644
--- a/esp32p4/src/mipi_dsi_host/int_msk1.rs
+++ b/esp32p4/src/mipi_dsi_host/int_msk1.rs
@@ -134,71 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_MSK1")
-            .field(
-                "mask_to_hs_tx",
-                &format_args!("{}", self.mask_to_hs_tx().bit()),
-            )
-            .field(
-                "mask_to_lp_rx",
-                &format_args!("{}", self.mask_to_lp_rx().bit()),
-            )
-            .field(
-                "mask_ecc_single_err",
-                &format_args!("{}", self.mask_ecc_single_err().bit()),
-            )
-            .field(
-                "mask_ecc_milti_err",
-                &format_args!("{}", self.mask_ecc_milti_err().bit()),
-            )
-            .field(
-                "mask_crc_err",
-                &format_args!("{}", self.mask_crc_err().bit()),
-            )
-            .field(
-                "mask_pkt_size_err",
-                &format_args!("{}", self.mask_pkt_size_err().bit()),
-            )
-            .field(
-                "mask_eopt_err",
-                &format_args!("{}", self.mask_eopt_err().bit()),
-            )
-            .field(
-                "mask_dpi_pld_wr_err",
-                &format_args!("{}", self.mask_dpi_pld_wr_err().bit()),
-            )
-            .field(
-                "mask_gen_cmd_wr_err",
-                &format_args!("{}", self.mask_gen_cmd_wr_err().bit()),
-            )
-            .field(
-                "mask_gen_pld_wr_err",
-                &format_args!("{}", self.mask_gen_pld_wr_err().bit()),
-            )
-            .field(
-                "mask_gen_pld_send_err",
-                &format_args!("{}", self.mask_gen_pld_send_err().bit()),
-            )
-            .field(
-                "mask_gen_pld_rd_err",
-                &format_args!("{}", self.mask_gen_pld_rd_err().bit()),
-            )
-            .field(
-                "mask_gen_pld_recev_err",
-                &format_args!("{}", self.mask_gen_pld_recev_err().bit()),
-            )
-            .field(
-                "mask_dpi_buff_pld_under",
-                &format_args!("{}", self.mask_dpi_buff_pld_under().bit()),
-            )
+            .field("mask_to_hs_tx", &self.mask_to_hs_tx())
+            .field("mask_to_lp_rx", &self.mask_to_lp_rx())
+            .field("mask_ecc_single_err", &self.mask_ecc_single_err())
+            .field("mask_ecc_milti_err", &self.mask_ecc_milti_err())
+            .field("mask_crc_err", &self.mask_crc_err())
+            .field("mask_pkt_size_err", &self.mask_pkt_size_err())
+            .field("mask_eopt_err", &self.mask_eopt_err())
+            .field("mask_dpi_pld_wr_err", &self.mask_dpi_pld_wr_err())
+            .field("mask_gen_cmd_wr_err", &self.mask_gen_cmd_wr_err())
+            .field("mask_gen_pld_wr_err", &self.mask_gen_pld_wr_err())
+            .field("mask_gen_pld_send_err", &self.mask_gen_pld_send_err())
+            .field("mask_gen_pld_rd_err", &self.mask_gen_pld_rd_err())
+            .field("mask_gen_pld_recev_err", &self.mask_gen_pld_recev_err())
+            .field("mask_dpi_buff_pld_under", &self.mask_dpi_buff_pld_under())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_MSK1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/int_st0.rs b/esp32p4/src/mipi_dsi_host/int_st0.rs
index e89e18c9e7..6b6b0aa7f3 100644
--- a/esp32p4/src/mipi_dsi_host/int_st0.rs
+++ b/esp32p4/src/mipi_dsi_host/int_st0.rs
@@ -153,99 +153,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST0")
-            .field(
-                "ack_with_err_0",
-                &format_args!("{}", self.ack_with_err_0().bit()),
-            )
-            .field(
-                "ack_with_err_1",
-                &format_args!("{}", self.ack_with_err_1().bit()),
-            )
-            .field(
-                "ack_with_err_2",
-                &format_args!("{}", self.ack_with_err_2().bit()),
-            )
-            .field(
-                "ack_with_err_3",
-                &format_args!("{}", self.ack_with_err_3().bit()),
-            )
-            .field(
-                "ack_with_err_4",
-                &format_args!("{}", self.ack_with_err_4().bit()),
-            )
-            .field(
-                "ack_with_err_5",
-                &format_args!("{}", self.ack_with_err_5().bit()),
-            )
-            .field(
-                "ack_with_err_6",
-                &format_args!("{}", self.ack_with_err_6().bit()),
-            )
-            .field(
-                "ack_with_err_7",
-                &format_args!("{}", self.ack_with_err_7().bit()),
-            )
-            .field(
-                "ack_with_err_8",
-                &format_args!("{}", self.ack_with_err_8().bit()),
-            )
-            .field(
-                "ack_with_err_9",
-                &format_args!("{}", self.ack_with_err_9().bit()),
-            )
-            .field(
-                "ack_with_err_10",
-                &format_args!("{}", self.ack_with_err_10().bit()),
-            )
-            .field(
-                "ack_with_err_11",
-                &format_args!("{}", self.ack_with_err_11().bit()),
-            )
-            .field(
-                "ack_with_err_12",
-                &format_args!("{}", self.ack_with_err_12().bit()),
-            )
-            .field(
-                "ack_with_err_13",
-                &format_args!("{}", self.ack_with_err_13().bit()),
-            )
-            .field(
-                "ack_with_err_14",
-                &format_args!("{}", self.ack_with_err_14().bit()),
-            )
-            .field(
-                "ack_with_err_15",
-                &format_args!("{}", self.ack_with_err_15().bit()),
-            )
-            .field(
-                "dphy_errors_0",
-                &format_args!("{}", self.dphy_errors_0().bit()),
-            )
-            .field(
-                "dphy_errors_1",
-                &format_args!("{}", self.dphy_errors_1().bit()),
-            )
-            .field(
-                "dphy_errors_2",
-                &format_args!("{}", self.dphy_errors_2().bit()),
-            )
-            .field(
-                "dphy_errors_3",
-                &format_args!("{}", self.dphy_errors_3().bit()),
-            )
-            .field(
-                "dphy_errors_4",
-                &format_args!("{}", self.dphy_errors_4().bit()),
-            )
+            .field("ack_with_err_0", &self.ack_with_err_0())
+            .field("ack_with_err_1", &self.ack_with_err_1())
+            .field("ack_with_err_2", &self.ack_with_err_2())
+            .field("ack_with_err_3", &self.ack_with_err_3())
+            .field("ack_with_err_4", &self.ack_with_err_4())
+            .field("ack_with_err_5", &self.ack_with_err_5())
+            .field("ack_with_err_6", &self.ack_with_err_6())
+            .field("ack_with_err_7", &self.ack_with_err_7())
+            .field("ack_with_err_8", &self.ack_with_err_8())
+            .field("ack_with_err_9", &self.ack_with_err_9())
+            .field("ack_with_err_10", &self.ack_with_err_10())
+            .field("ack_with_err_11", &self.ack_with_err_11())
+            .field("ack_with_err_12", &self.ack_with_err_12())
+            .field("ack_with_err_13", &self.ack_with_err_13())
+            .field("ack_with_err_14", &self.ack_with_err_14())
+            .field("ack_with_err_15", &self.ack_with_err_15())
+            .field("dphy_errors_0", &self.dphy_errors_0())
+            .field("dphy_errors_1", &self.dphy_errors_1())
+            .field("dphy_errors_2", &self.dphy_errors_2())
+            .field("dphy_errors_3", &self.dphy_errors_3())
+            .field("dphy_errors_4", &self.dphy_errors_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST0_SPEC;
 impl crate::RegisterSpec for INT_ST0_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/int_st1.rs b/esp32p4/src/mipi_dsi_host/int_st1.rs
index d79201187c..0d6c2c18ee 100644
--- a/esp32p4/src/mipi_dsi_host/int_st1.rs
+++ b/esp32p4/src/mipi_dsi_host/int_st1.rs
@@ -104,59 +104,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST1")
-            .field("to_hs_tx", &format_args!("{}", self.to_hs_tx().bit()))
-            .field("to_lp_rx", &format_args!("{}", self.to_lp_rx().bit()))
-            .field(
-                "ecc_single_err",
-                &format_args!("{}", self.ecc_single_err().bit()),
-            )
-            .field(
-                "ecc_milti_err",
-                &format_args!("{}", self.ecc_milti_err().bit()),
-            )
-            .field("crc_err", &format_args!("{}", self.crc_err().bit()))
-            .field(
-                "pkt_size_err",
-                &format_args!("{}", self.pkt_size_err().bit()),
-            )
-            .field("eopt_err", &format_args!("{}", self.eopt_err().bit()))
-            .field(
-                "dpi_pld_wr_err",
-                &format_args!("{}", self.dpi_pld_wr_err().bit()),
-            )
-            .field(
-                "gen_cmd_wr_err",
-                &format_args!("{}", self.gen_cmd_wr_err().bit()),
-            )
-            .field(
-                "gen_pld_wr_err",
-                &format_args!("{}", self.gen_pld_wr_err().bit()),
-            )
-            .field(
-                "gen_pld_send_err",
-                &format_args!("{}", self.gen_pld_send_err().bit()),
-            )
-            .field(
-                "gen_pld_rd_err",
-                &format_args!("{}", self.gen_pld_rd_err().bit()),
-            )
-            .field(
-                "gen_pld_recev_err",
-                &format_args!("{}", self.gen_pld_recev_err().bit()),
-            )
-            .field(
-                "dpi_buff_pld_under",
-                &format_args!("{}", self.dpi_buff_pld_under().bit()),
-            )
+            .field("to_hs_tx", &self.to_hs_tx())
+            .field("to_lp_rx", &self.to_lp_rx())
+            .field("ecc_single_err", &self.ecc_single_err())
+            .field("ecc_milti_err", &self.ecc_milti_err())
+            .field("crc_err", &self.crc_err())
+            .field("pkt_size_err", &self.pkt_size_err())
+            .field("eopt_err", &self.eopt_err())
+            .field("dpi_pld_wr_err", &self.dpi_pld_wr_err())
+            .field("gen_cmd_wr_err", &self.gen_cmd_wr_err())
+            .field("gen_pld_wr_err", &self.gen_pld_wr_err())
+            .field("gen_pld_send_err", &self.gen_pld_send_err())
+            .field("gen_pld_rd_err", &self.gen_pld_rd_err())
+            .field("gen_pld_recev_err", &self.gen_pld_recev_err())
+            .field("dpi_buff_pld_under", &self.dpi_buff_pld_under())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST1_SPEC;
 impl crate::RegisterSpec for INT_ST1_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/lp_rd_to_cnt.rs b/esp32p4/src/mipi_dsi_host/lp_rd_to_cnt.rs
index b85d18b9c7..4429d51642 100644
--- a/esp32p4/src/mipi_dsi_host/lp_rd_to_cnt.rs
+++ b/esp32p4/src/mipi_dsi_host/lp_rd_to_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_RD_TO_CNT")
-            .field(
-                "lp_rd_to_cnt",
-                &format_args!("{}", self.lp_rd_to_cnt().bits()),
-            )
+            .field("lp_rd_to_cnt", &self.lp_rd_to_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_RD_TO_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/lp_wr_to_cnt.rs b/esp32p4/src/mipi_dsi_host/lp_wr_to_cnt.rs
index 966dfcacb5..9844b75966 100644
--- a/esp32p4/src/mipi_dsi_host/lp_wr_to_cnt.rs
+++ b/esp32p4/src/mipi_dsi_host/lp_wr_to_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_WR_TO_CNT")
-            .field(
-                "lp_wr_to_cnt",
-                &format_args!("{}", self.lp_wr_to_cnt().bits()),
-            )
+            .field("lp_wr_to_cnt", &self.lp_wr_to_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_WR_TO_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/lpclk_ctrl.rs b/esp32p4/src/mipi_dsi_host/lpclk_ctrl.rs
index c1e05153df..04ad034748 100644
--- a/esp32p4/src/mipi_dsi_host/lpclk_ctrl.rs
+++ b/esp32p4/src/mipi_dsi_host/lpclk_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPCLK_CTRL")
-            .field(
-                "phy_txrequestclkhs",
-                &format_args!("{}", self.phy_txrequestclkhs().bit()),
-            )
-            .field(
-                "auto_clklane_ctrl",
-                &format_args!("{}", self.auto_clklane_ctrl().bit()),
-            )
+            .field("phy_txrequestclkhs", &self.phy_txrequestclkhs())
+            .field("auto_clklane_ctrl", &self.auto_clklane_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPCLK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/mode_cfg.rs b/esp32p4/src/mipi_dsi_host/mode_cfg.rs
index 5b8afae025..72fee26e56 100644
--- a/esp32p4/src/mipi_dsi_host/mode_cfg.rs
+++ b/esp32p4/src/mipi_dsi_host/mode_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODE_CFG")
-            .field(
-                "cmd_video_mode",
-                &format_args!("{}", self.cmd_video_mode().bit()),
-            )
+            .field("cmd_video_mode", &self.cmd_video_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/pckhdl_cfg.rs b/esp32p4/src/mipi_dsi_host/pckhdl_cfg.rs
index 91178f56d8..74f10bd2ad 100644
--- a/esp32p4/src/mipi_dsi_host/pckhdl_cfg.rs
+++ b/esp32p4/src/mipi_dsi_host/pckhdl_cfg.rs
@@ -62,24 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCKHDL_CFG")
-            .field("eotp_tx_en", &format_args!("{}", self.eotp_tx_en().bit()))
-            .field("eotp_rx_en", &format_args!("{}", self.eotp_rx_en().bit()))
-            .field("bta_en", &format_args!("{}", self.bta_en().bit()))
-            .field("ecc_rx_en", &format_args!("{}", self.ecc_rx_en().bit()))
-            .field("crc_rx_en", &format_args!("{}", self.crc_rx_en().bit()))
-            .field(
-                "eotp_tx_lp_en",
-                &format_args!("{}", self.eotp_tx_lp_en().bit()),
-            )
+            .field("eotp_tx_en", &self.eotp_tx_en())
+            .field("eotp_rx_en", &self.eotp_rx_en())
+            .field("bta_en", &self.bta_en())
+            .field("ecc_rx_en", &self.ecc_rx_en())
+            .field("crc_rx_en", &self.crc_rx_en())
+            .field("eotp_tx_lp_en", &self.eotp_tx_lp_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCKHDL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/phy_cal.rs b/esp32p4/src/mipi_dsi_host/phy_cal.rs
index dc4c4dc184..3a95caafd3 100644
--- a/esp32p4/src/mipi_dsi_host/phy_cal.rs
+++ b/esp32p4/src/mipi_dsi_host/phy_cal.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_CAL")
-            .field("txskewcalhs", &format_args!("{}", self.txskewcalhs().bit()))
+            .field("txskewcalhs", &self.txskewcalhs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_CAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/phy_if_cfg.rs b/esp32p4/src/mipi_dsi_host/phy_if_cfg.rs
index fab64aed15..1cf3646141 100644
--- a/esp32p4/src/mipi_dsi_host/phy_if_cfg.rs
+++ b/esp32p4/src/mipi_dsi_host/phy_if_cfg.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_IF_CFG")
-            .field("n_lanes", &format_args!("{}", self.n_lanes().bits()))
-            .field(
-                "phy_stop_wait_time",
-                &format_args!("{}", self.phy_stop_wait_time().bits()),
-            )
+            .field("n_lanes", &self.n_lanes())
+            .field("phy_stop_wait_time", &self.phy_stop_wait_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_IF_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/phy_rstz.rs b/esp32p4/src/mipi_dsi_host/phy_rstz.rs
index d2b6ba9add..ee41bc56a3 100644
--- a/esp32p4/src/mipi_dsi_host/phy_rstz.rs
+++ b/esp32p4/src/mipi_dsi_host/phy_rstz.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_RSTZ")
-            .field(
-                "phy_shutdownz",
-                &format_args!("{}", self.phy_shutdownz().bit()),
-            )
-            .field("phy_rstz", &format_args!("{}", self.phy_rstz().bit()))
-            .field(
-                "phy_enableclk",
-                &format_args!("{}", self.phy_enableclk().bit()),
-            )
-            .field(
-                "phy_forcepll",
-                &format_args!("{}", self.phy_forcepll().bit()),
-            )
+            .field("phy_shutdownz", &self.phy_shutdownz())
+            .field("phy_rstz", &self.phy_rstz())
+            .field("phy_enableclk", &self.phy_enableclk())
+            .field("phy_forcepll", &self.phy_forcepll())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_RSTZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/phy_status.rs b/esp32p4/src/mipi_dsi_host/phy_status.rs
index a96cf4a4f7..06f15312cf 100644
--- a/esp32p4/src/mipi_dsi_host/phy_status.rs
+++ b/esp32p4/src/mipi_dsi_host/phy_status.rs
@@ -69,48 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_STATUS")
-            .field("phy_lock", &format_args!("{}", self.phy_lock().bit()))
-            .field(
-                "phy_direction",
-                &format_args!("{}", self.phy_direction().bit()),
-            )
-            .field(
-                "phy_stopstateclklane",
-                &format_args!("{}", self.phy_stopstateclklane().bit()),
-            )
-            .field(
-                "phy_ulpsactivenotclk",
-                &format_args!("{}", self.phy_ulpsactivenotclk().bit()),
-            )
-            .field(
-                "phy_stopstate0lane",
-                &format_args!("{}", self.phy_stopstate0lane().bit()),
-            )
-            .field(
-                "phy_ulpsactivenot0lane",
-                &format_args!("{}", self.phy_ulpsactivenot0lane().bit()),
-            )
-            .field(
-                "phy_rxulpsesc0lane",
-                &format_args!("{}", self.phy_rxulpsesc0lane().bit()),
-            )
-            .field(
-                "phy_stopstate1lane",
-                &format_args!("{}", self.phy_stopstate1lane().bit()),
-            )
-            .field(
-                "phy_ulpsactivenot1lane",
-                &format_args!("{}", self.phy_ulpsactivenot1lane().bit()),
-            )
+            .field("phy_lock", &self.phy_lock())
+            .field("phy_direction", &self.phy_direction())
+            .field("phy_stopstateclklane", &self.phy_stopstateclklane())
+            .field("phy_ulpsactivenotclk", &self.phy_ulpsactivenotclk())
+            .field("phy_stopstate0lane", &self.phy_stopstate0lane())
+            .field("phy_ulpsactivenot0lane", &self.phy_ulpsactivenot0lane())
+            .field("phy_rxulpsesc0lane", &self.phy_rxulpsesc0lane())
+            .field("phy_stopstate1lane", &self.phy_stopstate1lane())
+            .field("phy_ulpsactivenot1lane", &self.phy_ulpsactivenot1lane())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PHY_STATUS_SPEC;
 impl crate::RegisterSpec for PHY_STATUS_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/phy_tmr_cfg.rs b/esp32p4/src/mipi_dsi_host/phy_tmr_cfg.rs
index a12bd30baa..4b2f253b90 100644
--- a/esp32p4/src/mipi_dsi_host/phy_tmr_cfg.rs
+++ b/esp32p4/src/mipi_dsi_host/phy_tmr_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_TMR_CFG")
-            .field(
-                "phy_lp2hs_time",
-                &format_args!("{}", self.phy_lp2hs_time().bits()),
-            )
-            .field(
-                "phy_hs2lp_time",
-                &format_args!("{}", self.phy_hs2lp_time().bits()),
-            )
+            .field("phy_lp2hs_time", &self.phy_lp2hs_time())
+            .field("phy_hs2lp_time", &self.phy_hs2lp_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_TMR_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/phy_tmr_lpclk_cfg.rs b/esp32p4/src/mipi_dsi_host/phy_tmr_lpclk_cfg.rs
index ec3dafd4af..e817d47eb4 100644
--- a/esp32p4/src/mipi_dsi_host/phy_tmr_lpclk_cfg.rs
+++ b/esp32p4/src/mipi_dsi_host/phy_tmr_lpclk_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_TMR_LPCLK_CFG")
-            .field(
-                "phy_clklp2hs_time",
-                &format_args!("{}", self.phy_clklp2hs_time().bits()),
-            )
-            .field(
-                "phy_clkhs2lp_time",
-                &format_args!("{}", self.phy_clkhs2lp_time().bits()),
-            )
+            .field("phy_clklp2hs_time", &self.phy_clklp2hs_time())
+            .field("phy_clkhs2lp_time", &self.phy_clkhs2lp_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_TMR_LPCLK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/phy_tmr_rd_cfg.rs b/esp32p4/src/mipi_dsi_host/phy_tmr_rd_cfg.rs
index daf276fb93..9ee0baa88f 100644
--- a/esp32p4/src/mipi_dsi_host/phy_tmr_rd_cfg.rs
+++ b/esp32p4/src/mipi_dsi_host/phy_tmr_rd_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_TMR_RD_CFG")
-            .field(
-                "max_rd_time",
-                &format_args!("{}", self.max_rd_time().bits()),
-            )
+            .field("max_rd_time", &self.max_rd_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_TMR_RD_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/phy_tst_ctrl0.rs b/esp32p4/src/mipi_dsi_host/phy_tst_ctrl0.rs
index e97531aee6..1541953019 100644
--- a/esp32p4/src/mipi_dsi_host/phy_tst_ctrl0.rs
+++ b/esp32p4/src/mipi_dsi_host/phy_tst_ctrl0.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_TST_CTRL0")
-            .field("phy_testclr", &format_args!("{}", self.phy_testclr().bit()))
-            .field("phy_testclk", &format_args!("{}", self.phy_testclk().bit()))
+            .field("phy_testclr", &self.phy_testclr())
+            .field("phy_testclk", &self.phy_testclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_TST_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/phy_tst_ctrl1.rs b/esp32p4/src/mipi_dsi_host/phy_tst_ctrl1.rs
index ecf50f5bad..33b2c0f495 100644
--- a/esp32p4/src/mipi_dsi_host/phy_tst_ctrl1.rs
+++ b/esp32p4/src/mipi_dsi_host/phy_tst_ctrl1.rs
@@ -33,24 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_TST_CTRL1")
-            .field(
-                "phy_testdin",
-                &format_args!("{}", self.phy_testdin().bits()),
-            )
-            .field(
-                "pht_testdout",
-                &format_args!("{}", self.pht_testdout().bits()),
-            )
-            .field("phy_testen", &format_args!("{}", self.phy_testen().bit()))
+            .field("phy_testdin", &self.phy_testdin())
+            .field("pht_testdout", &self.pht_testdout())
+            .field("phy_testen", &self.phy_testen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_TST_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/phy_tx_triggers.rs b/esp32p4/src/mipi_dsi_host/phy_tx_triggers.rs
index 409b92f46f..7d8e869493 100644
--- a/esp32p4/src/mipi_dsi_host/phy_tx_triggers.rs
+++ b/esp32p4/src/mipi_dsi_host/phy_tx_triggers.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_TX_TRIGGERS")
-            .field(
-                "phy_tx_triggers",
-                &format_args!("{}", self.phy_tx_triggers().bits()),
-            )
+            .field("phy_tx_triggers", &self.phy_tx_triggers())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_TX_TRIGGERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/phy_ulps_ctrl.rs b/esp32p4/src/mipi_dsi_host/phy_ulps_ctrl.rs
index aa09449035..57cee006ca 100644
--- a/esp32p4/src/mipi_dsi_host/phy_ulps_ctrl.rs
+++ b/esp32p4/src/mipi_dsi_host/phy_ulps_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHY_ULPS_CTRL")
-            .field(
-                "phy_txrequlpsclk",
-                &format_args!("{}", self.phy_txrequlpsclk().bit()),
-            )
-            .field(
-                "phy_txexitulpsclk",
-                &format_args!("{}", self.phy_txexitulpsclk().bit()),
-            )
-            .field(
-                "phy_txrequlpslan",
-                &format_args!("{}", self.phy_txrequlpslan().bit()),
-            )
-            .field(
-                "phy_txexitulpslan",
-                &format_args!("{}", self.phy_txexitulpslan().bit()),
-            )
+            .field("phy_txrequlpsclk", &self.phy_txrequlpsclk())
+            .field("phy_txexitulpsclk", &self.phy_txexitulpsclk())
+            .field("phy_txrequlpslan", &self.phy_txrequlpslan())
+            .field("phy_txexitulpslan", &self.phy_txexitulpslan())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHY_ULPS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/pwr_up.rs b/esp32p4/src/mipi_dsi_host/pwr_up.rs
index 1bda270c4f..288bca9cfd 100644
--- a/esp32p4/src/mipi_dsi_host/pwr_up.rs
+++ b/esp32p4/src/mipi_dsi_host/pwr_up.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWR_UP")
-            .field("shutdownz", &format_args!("{}", self.shutdownz().bit()))
+            .field("shutdownz", &self.shutdownz())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWR_UP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/sdf_3d.rs b/esp32p4/src/mipi_dsi_host/sdf_3d.rs
index f64e28448a..26adb4e7db 100644
--- a/esp32p4/src/mipi_dsi_host/sdf_3d.rs
+++ b/esp32p4/src/mipi_dsi_host/sdf_3d.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDF_3D")
-            .field("mode_3d", &format_args!("{}", self.mode_3d().bits()))
-            .field("format_3d", &format_args!("{}", self.format_3d().bits()))
-            .field(
-                "second_vsync",
-                &format_args!("{}", self.second_vsync().bit()),
-            )
-            .field("right_first", &format_args!("{}", self.right_first().bit()))
-            .field("send_3d_cfg", &format_args!("{}", self.send_3d_cfg().bit()))
+            .field("mode_3d", &self.mode_3d())
+            .field("format_3d", &self.format_3d())
+            .field("second_vsync", &self.second_vsync())
+            .field("right_first", &self.right_first())
+            .field("send_3d_cfg", &self.send_3d_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDF_3D_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/sdf_3d_act.rs b/esp32p4/src/mipi_dsi_host/sdf_3d_act.rs
index aaa8a8744e..bf6ee54815 100644
--- a/esp32p4/src/mipi_dsi_host/sdf_3d_act.rs
+++ b/esp32p4/src/mipi_dsi_host/sdf_3d_act.rs
@@ -41,35 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDF_3D_ACT")
-            .field(
-                "mode_3d_act",
-                &format_args!("{}", self.mode_3d_act().bits()),
-            )
-            .field(
-                "format_3d_act",
-                &format_args!("{}", self.format_3d_act().bits()),
-            )
-            .field(
-                "second_vsync_act",
-                &format_args!("{}", self.second_vsync_act().bit()),
-            )
-            .field(
-                "right_first_act",
-                &format_args!("{}", self.right_first_act().bit()),
-            )
-            .field(
-                "send_3d_cfg_act",
-                &format_args!("{}", self.send_3d_cfg_act().bit()),
-            )
+            .field("mode_3d_act", &self.mode_3d_act())
+            .field("format_3d_act", &self.format_3d_act())
+            .field("second_vsync_act", &self.second_vsync_act())
+            .field("right_first_act", &self.right_first_act())
+            .field("send_3d_cfg_act", &self.send_3d_cfg_act())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDF_3D_ACT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdf_3d_act::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SDF_3D_ACT_SPEC;
 impl crate::RegisterSpec for SDF_3D_ACT_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/to_cnt_cfg.rs b/esp32p4/src/mipi_dsi_host/to_cnt_cfg.rs
index 6059969a3a..e2df309d01 100644
--- a/esp32p4/src/mipi_dsi_host/to_cnt_cfg.rs
+++ b/esp32p4/src/mipi_dsi_host/to_cnt_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO_CNT_CFG")
-            .field(
-                "lprx_to_cnt",
-                &format_args!("{}", self.lprx_to_cnt().bits()),
-            )
-            .field(
-                "hstx_to_cnt",
-                &format_args!("{}", self.hstx_to_cnt().bits()),
-            )
+            .field("lprx_to_cnt", &self.lprx_to_cnt())
+            .field("hstx_to_cnt", &self.hstx_to_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_CNT_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/version.rs b/esp32p4/src/mipi_dsi_host/version.rs
index 3bb9633b18..c70718f030 100644
--- a/esp32p4/src/mipi_dsi_host/version.rs
+++ b/esp32p4/src/mipi_dsi_host/version.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field("version", &format_args!("{}", self.version().bits()))
+            .field("version", &self.version())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`version::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VERSION_SPEC;
 impl crate::RegisterSpec for VERSION_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/vid_hbp_time.rs b/esp32p4/src/mipi_dsi_host/vid_hbp_time.rs
index 600c536802..0e997d92fd 100644
--- a/esp32p4/src/mipi_dsi_host/vid_hbp_time.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_hbp_time.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_HBP_TIME")
-            .field(
-                "vid_hbp_time",
-                &format_args!("{}", self.vid_hbp_time().bits()),
-            )
+            .field("vid_hbp_time", &self.vid_hbp_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_HBP_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/vid_hbp_time_act.rs b/esp32p4/src/mipi_dsi_host/vid_hbp_time_act.rs
index 77c6a91476..3ea13a9114 100644
--- a/esp32p4/src/mipi_dsi_host/vid_hbp_time_act.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_hbp_time_act.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_HBP_TIME_ACT")
-            .field(
-                "vid_hbp_time_act",
-                &format_args!("{}", self.vid_hbp_time_act().bits()),
-            )
+            .field("vid_hbp_time_act", &self.vid_hbp_time_act())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_HBP_TIME_ACT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_hbp_time_act::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VID_HBP_TIME_ACT_SPEC;
 impl crate::RegisterSpec for VID_HBP_TIME_ACT_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/vid_hline_time.rs b/esp32p4/src/mipi_dsi_host/vid_hline_time.rs
index 2be100d99a..71bfd0890f 100644
--- a/esp32p4/src/mipi_dsi_host/vid_hline_time.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_hline_time.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_HLINE_TIME")
-            .field(
-                "vid_hline_time",
-                &format_args!("{}", self.vid_hline_time().bits()),
-            )
+            .field("vid_hline_time", &self.vid_hline_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_HLINE_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/vid_hline_time_act.rs b/esp32p4/src/mipi_dsi_host/vid_hline_time_act.rs
index 6009b91e54..b4e7130091 100644
--- a/esp32p4/src/mipi_dsi_host/vid_hline_time_act.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_hline_time_act.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_HLINE_TIME_ACT")
-            .field(
-                "vid_hline_time_act",
-                &format_args!("{}", self.vid_hline_time_act().bits()),
-            )
+            .field("vid_hline_time_act", &self.vid_hline_time_act())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_HLINE_TIME_ACT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_hline_time_act::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VID_HLINE_TIME_ACT_SPEC;
 impl crate::RegisterSpec for VID_HLINE_TIME_ACT_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/vid_hsa_time.rs b/esp32p4/src/mipi_dsi_host/vid_hsa_time.rs
index 371fc20550..1211f36924 100644
--- a/esp32p4/src/mipi_dsi_host/vid_hsa_time.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_hsa_time.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_HSA_TIME")
-            .field(
-                "vid_hsa_time",
-                &format_args!("{}", self.vid_hsa_time().bits()),
-            )
+            .field("vid_hsa_time", &self.vid_hsa_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_HSA_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/vid_hsa_time_act.rs b/esp32p4/src/mipi_dsi_host/vid_hsa_time_act.rs
index bd9beb37b9..19e5e48958 100644
--- a/esp32p4/src/mipi_dsi_host/vid_hsa_time_act.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_hsa_time_act.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_HSA_TIME_ACT")
-            .field(
-                "vid_hsa_time_act",
-                &format_args!("{}", self.vid_hsa_time_act().bits()),
-            )
+            .field("vid_hsa_time_act", &self.vid_hsa_time_act())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_HSA_TIME_ACT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_hsa_time_act::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VID_HSA_TIME_ACT_SPEC;
 impl crate::RegisterSpec for VID_HSA_TIME_ACT_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/vid_mode_cfg.rs b/esp32p4/src/mipi_dsi_host/vid_mode_cfg.rs
index 0e288617f1..87d4d7561f 100644
--- a/esp32p4/src/mipi_dsi_host/vid_mode_cfg.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_mode_cfg.rs
@@ -116,36 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_MODE_CFG")
-            .field(
-                "vid_mode_type",
-                &format_args!("{}", self.vid_mode_type().bits()),
-            )
-            .field("lp_vsa_en", &format_args!("{}", self.lp_vsa_en().bit()))
-            .field("lp_vbp_en", &format_args!("{}", self.lp_vbp_en().bit()))
-            .field("lp_vfp_en", &format_args!("{}", self.lp_vfp_en().bit()))
-            .field("lp_vact_en", &format_args!("{}", self.lp_vact_en().bit()))
-            .field("lp_hbp_en", &format_args!("{}", self.lp_hbp_en().bit()))
-            .field("lp_hfp_en", &format_args!("{}", self.lp_hfp_en().bit()))
-            .field(
-                "frame_bta_ack_en",
-                &format_args!("{}", self.frame_bta_ack_en().bit()),
-            )
-            .field("lp_cmd_en", &format_args!("{}", self.lp_cmd_en().bit()))
-            .field("vpg_en", &format_args!("{}", self.vpg_en().bit()))
-            .field("vpg_mode", &format_args!("{}", self.vpg_mode().bit()))
-            .field(
-                "vpg_orientation",
-                &format_args!("{}", self.vpg_orientation().bit()),
-            )
+            .field("vid_mode_type", &self.vid_mode_type())
+            .field("lp_vsa_en", &self.lp_vsa_en())
+            .field("lp_vbp_en", &self.lp_vbp_en())
+            .field("lp_vfp_en", &self.lp_vfp_en())
+            .field("lp_vact_en", &self.lp_vact_en())
+            .field("lp_hbp_en", &self.lp_hbp_en())
+            .field("lp_hfp_en", &self.lp_hfp_en())
+            .field("frame_bta_ack_en", &self.frame_bta_ack_en())
+            .field("lp_cmd_en", &self.lp_cmd_en())
+            .field("vpg_en", &self.vpg_en())
+            .field("vpg_mode", &self.vpg_mode())
+            .field("vpg_orientation", &self.vpg_orientation())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_MODE_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/vid_mode_cfg_act.rs b/esp32p4/src/mipi_dsi_host/vid_mode_cfg_act.rs
index 8cc249cae0..971634fa1a 100644
--- a/esp32p4/src/mipi_dsi_host/vid_mode_cfg_act.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_mode_cfg_act.rs
@@ -69,51 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_MODE_CFG_ACT")
-            .field(
-                "vid_mode_type_act",
-                &format_args!("{}", self.vid_mode_type_act().bits()),
-            )
-            .field(
-                "lp_vsa_en_act",
-                &format_args!("{}", self.lp_vsa_en_act().bit()),
-            )
-            .field(
-                "lp_vbp_en_act",
-                &format_args!("{}", self.lp_vbp_en_act().bit()),
-            )
-            .field(
-                "lp_vfp_en_act",
-                &format_args!("{}", self.lp_vfp_en_act().bit()),
-            )
-            .field(
-                "lp_vact_en_act",
-                &format_args!("{}", self.lp_vact_en_act().bit()),
-            )
-            .field(
-                "lp_hbp_en_act",
-                &format_args!("{}", self.lp_hbp_en_act().bit()),
-            )
-            .field(
-                "lp_hfp_en_act",
-                &format_args!("{}", self.lp_hfp_en_act().bit()),
-            )
-            .field(
-                "frame_bta_ack_en_act",
-                &format_args!("{}", self.frame_bta_ack_en_act().bit()),
-            )
-            .field(
-                "lp_cmd_en_act",
-                &format_args!("{}", self.lp_cmd_en_act().bit()),
-            )
+            .field("vid_mode_type_act", &self.vid_mode_type_act())
+            .field("lp_vsa_en_act", &self.lp_vsa_en_act())
+            .field("lp_vbp_en_act", &self.lp_vbp_en_act())
+            .field("lp_vfp_en_act", &self.lp_vfp_en_act())
+            .field("lp_vact_en_act", &self.lp_vact_en_act())
+            .field("lp_hbp_en_act", &self.lp_hbp_en_act())
+            .field("lp_hfp_en_act", &self.lp_hfp_en_act())
+            .field("frame_bta_ack_en_act", &self.frame_bta_ack_en_act())
+            .field("lp_cmd_en_act", &self.lp_cmd_en_act())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_MODE_CFG_ACT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_mode_cfg_act::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VID_MODE_CFG_ACT_SPEC;
 impl crate::RegisterSpec for VID_MODE_CFG_ACT_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/vid_null_size.rs b/esp32p4/src/mipi_dsi_host/vid_null_size.rs
index c51fe52d12..8aff18fafc 100644
--- a/esp32p4/src/mipi_dsi_host/vid_null_size.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_null_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_NULL_SIZE")
-            .field(
-                "vid_null_size",
-                &format_args!("{}", self.vid_null_size().bits()),
-            )
+            .field("vid_null_size", &self.vid_null_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_NULL_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/vid_null_size_act.rs b/esp32p4/src/mipi_dsi_host/vid_null_size_act.rs
index 302a3fa259..c846a3c01f 100644
--- a/esp32p4/src/mipi_dsi_host/vid_null_size_act.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_null_size_act.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_NULL_SIZE_ACT")
-            .field(
-                "vid_null_size_act",
-                &format_args!("{}", self.vid_null_size_act().bits()),
-            )
+            .field("vid_null_size_act", &self.vid_null_size_act())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_NULL_SIZE_ACT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_null_size_act::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VID_NULL_SIZE_ACT_SPEC;
 impl crate::RegisterSpec for VID_NULL_SIZE_ACT_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/vid_num_chunks.rs b/esp32p4/src/mipi_dsi_host/vid_num_chunks.rs
index 8a24f0c594..832ee1a9c6 100644
--- a/esp32p4/src/mipi_dsi_host/vid_num_chunks.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_num_chunks.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_NUM_CHUNKS")
-            .field(
-                "vid_num_chunks",
-                &format_args!("{}", self.vid_num_chunks().bits()),
-            )
+            .field("vid_num_chunks", &self.vid_num_chunks())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_NUM_CHUNKS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/vid_num_chunks_act.rs b/esp32p4/src/mipi_dsi_host/vid_num_chunks_act.rs
index 0425de4a52..9619a7217f 100644
--- a/esp32p4/src/mipi_dsi_host/vid_num_chunks_act.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_num_chunks_act.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_NUM_CHUNKS_ACT")
-            .field(
-                "vid_num_chunks_act",
-                &format_args!("{}", self.vid_num_chunks_act().bits()),
-            )
+            .field("vid_num_chunks_act", &self.vid_num_chunks_act())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_NUM_CHUNKS_ACT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_num_chunks_act::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VID_NUM_CHUNKS_ACT_SPEC;
 impl crate::RegisterSpec for VID_NUM_CHUNKS_ACT_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/vid_pkt_size.rs b/esp32p4/src/mipi_dsi_host/vid_pkt_size.rs
index 241d7afa95..45aef57e15 100644
--- a/esp32p4/src/mipi_dsi_host/vid_pkt_size.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_pkt_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_PKT_SIZE")
-            .field(
-                "vid_pkt_size",
-                &format_args!("{}", self.vid_pkt_size().bits()),
-            )
+            .field("vid_pkt_size", &self.vid_pkt_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_PKT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/vid_pkt_size_act.rs b/esp32p4/src/mipi_dsi_host/vid_pkt_size_act.rs
index 78f8e1b1dd..e6136a514d 100644
--- a/esp32p4/src/mipi_dsi_host/vid_pkt_size_act.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_pkt_size_act.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_PKT_SIZE_ACT")
-            .field(
-                "vid_pkt_size_act",
-                &format_args!("{}", self.vid_pkt_size_act().bits()),
-            )
+            .field("vid_pkt_size_act", &self.vid_pkt_size_act())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_PKT_SIZE_ACT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_pkt_size_act::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VID_PKT_SIZE_ACT_SPEC;
 impl crate::RegisterSpec for VID_PKT_SIZE_ACT_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/vid_pkt_status.rs b/esp32p4/src/mipi_dsi_host/vid_pkt_status.rs
index 14e6120068..fe60e13423 100644
--- a/esp32p4/src/mipi_dsi_host/vid_pkt_status.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_pkt_status.rs
@@ -48,39 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_PKT_STATUS")
-            .field(
-                "dpi_cmd_w_empty",
-                &format_args!("{}", self.dpi_cmd_w_empty().bit()),
-            )
-            .field(
-                "dpi_cmd_w_full",
-                &format_args!("{}", self.dpi_cmd_w_full().bit()),
-            )
-            .field(
-                "dpi_pld_w_empty",
-                &format_args!("{}", self.dpi_pld_w_empty().bit()),
-            )
-            .field(
-                "dpi_pld_w_full",
-                &format_args!("{}", self.dpi_pld_w_full().bit()),
-            )
-            .field(
-                "dpi_buff_pld_empty",
-                &format_args!("{}", self.dpi_buff_pld_empty().bit()),
-            )
-            .field(
-                "dpi_buff_pld_full",
-                &format_args!("{}", self.dpi_buff_pld_full().bit()),
-            )
+            .field("dpi_cmd_w_empty", &self.dpi_cmd_w_empty())
+            .field("dpi_cmd_w_full", &self.dpi_cmd_w_full())
+            .field("dpi_pld_w_empty", &self.dpi_pld_w_empty())
+            .field("dpi_pld_w_full", &self.dpi_pld_w_full())
+            .field("dpi_buff_pld_empty", &self.dpi_buff_pld_empty())
+            .field("dpi_buff_pld_full", &self.dpi_buff_pld_full())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_PKT_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_pkt_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VID_PKT_STATUS_SPEC;
 impl crate::RegisterSpec for VID_PKT_STATUS_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/vid_shadow_ctrl.rs b/esp32p4/src/mipi_dsi_host/vid_shadow_ctrl.rs
index 12451c25a9..129a903d2c 100644
--- a/esp32p4/src/mipi_dsi_host/vid_shadow_ctrl.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_shadow_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_SHADOW_CTRL")
-            .field(
-                "vid_shadow_en",
-                &format_args!("{}", self.vid_shadow_en().bit()),
-            )
-            .field(
-                "vid_shadow_req",
-                &format_args!("{}", self.vid_shadow_req().bit()),
-            )
-            .field(
-                "vid_shadow_pin_req",
-                &format_args!("{}", self.vid_shadow_pin_req().bit()),
-            )
+            .field("vid_shadow_en", &self.vid_shadow_en())
+            .field("vid_shadow_req", &self.vid_shadow_req())
+            .field("vid_shadow_pin_req", &self.vid_shadow_pin_req())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_SHADOW_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/vid_vactive_lines.rs b/esp32p4/src/mipi_dsi_host/vid_vactive_lines.rs
index f4fd22a0fc..d9e809c83a 100644
--- a/esp32p4/src/mipi_dsi_host/vid_vactive_lines.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_vactive_lines.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_VACTIVE_LINES")
-            .field(
-                "v_active_lines",
-                &format_args!("{}", self.v_active_lines().bits()),
-            )
+            .field("v_active_lines", &self.v_active_lines())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_VACTIVE_LINES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/vid_vactive_lines_act.rs b/esp32p4/src/mipi_dsi_host/vid_vactive_lines_act.rs
index 979a96af30..97a991d758 100644
--- a/esp32p4/src/mipi_dsi_host/vid_vactive_lines_act.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_vactive_lines_act.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_VACTIVE_LINES_ACT")
-            .field(
-                "v_active_lines_act",
-                &format_args!("{}", self.v_active_lines_act().bits()),
-            )
+            .field("v_active_lines_act", &self.v_active_lines_act())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_VACTIVE_LINES_ACT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vactive_lines_act::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VID_VACTIVE_LINES_ACT_SPEC;
 impl crate::RegisterSpec for VID_VACTIVE_LINES_ACT_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/vid_vbp_lines.rs b/esp32p4/src/mipi_dsi_host/vid_vbp_lines.rs
index b928588a80..acf8039224 100644
--- a/esp32p4/src/mipi_dsi_host/vid_vbp_lines.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_vbp_lines.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_VBP_LINES")
-            .field("vbp_lines", &format_args!("{}", self.vbp_lines().bits()))
+            .field("vbp_lines", &self.vbp_lines())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_VBP_LINES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/vid_vbp_lines_act.rs b/esp32p4/src/mipi_dsi_host/vid_vbp_lines_act.rs
index bac7553309..5ae1fc723c 100644
--- a/esp32p4/src/mipi_dsi_host/vid_vbp_lines_act.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_vbp_lines_act.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_VBP_LINES_ACT")
-            .field(
-                "vbp_lines_act",
-                &format_args!("{}", self.vbp_lines_act().bits()),
-            )
+            .field("vbp_lines_act", &self.vbp_lines_act())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_VBP_LINES_ACT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vbp_lines_act::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VID_VBP_LINES_ACT_SPEC;
 impl crate::RegisterSpec for VID_VBP_LINES_ACT_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/vid_vfp_lines.rs b/esp32p4/src/mipi_dsi_host/vid_vfp_lines.rs
index a034455ef2..695e239167 100644
--- a/esp32p4/src/mipi_dsi_host/vid_vfp_lines.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_vfp_lines.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_VFP_LINES")
-            .field("vfp_lines", &format_args!("{}", self.vfp_lines().bits()))
+            .field("vfp_lines", &self.vfp_lines())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_VFP_LINES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/vid_vfp_lines_act.rs b/esp32p4/src/mipi_dsi_host/vid_vfp_lines_act.rs
index 33c5eb62bb..07868fcdeb 100644
--- a/esp32p4/src/mipi_dsi_host/vid_vfp_lines_act.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_vfp_lines_act.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_VFP_LINES_ACT")
-            .field(
-                "vfp_lines_act",
-                &format_args!("{}", self.vfp_lines_act().bits()),
-            )
+            .field("vfp_lines_act", &self.vfp_lines_act())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_VFP_LINES_ACT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vfp_lines_act::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VID_VFP_LINES_ACT_SPEC;
 impl crate::RegisterSpec for VID_VFP_LINES_ACT_SPEC {
diff --git a/esp32p4/src/mipi_dsi_host/vid_vsa_lines.rs b/esp32p4/src/mipi_dsi_host/vid_vsa_lines.rs
index 449948f26e..f30ebd3a26 100644
--- a/esp32p4/src/mipi_dsi_host/vid_vsa_lines.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_vsa_lines.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_VSA_LINES")
-            .field("vsa_lines", &format_args!("{}", self.vsa_lines().bits()))
+            .field("vsa_lines", &self.vsa_lines())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_VSA_LINES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - NA"]
     #[inline(always)]
diff --git a/esp32p4/src/mipi_dsi_host/vid_vsa_lines_act.rs b/esp32p4/src/mipi_dsi_host/vid_vsa_lines_act.rs
index 5c68a08981..2b12e0e7e6 100644
--- a/esp32p4/src/mipi_dsi_host/vid_vsa_lines_act.rs
+++ b/esp32p4/src/mipi_dsi_host/vid_vsa_lines_act.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VID_VSA_LINES_ACT")
-            .field(
-                "vsa_lines_act",
-                &format_args!("{}", self.vsa_lines_act().bits()),
-            )
+            .field("vsa_lines_act", &self.vsa_lines_act())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VID_VSA_LINES_ACT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vid_vsa_lines_act::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VID_VSA_LINES_ACT_SPEC;
 impl crate::RegisterSpec for VID_VSA_LINES_ACT_SPEC {
diff --git a/esp32p4/src/parl_io/clk.rs b/esp32p4/src/parl_io/clk.rs
index e4708b2032..60f6e7929d 100644
--- a/esp32p4/src/parl_io/clk.rs
+++ b/esp32p4/src/parl_io/clk.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CLK")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CLK").field("en", &self.en()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/parl_io/fifo_cfg.rs b/esp32p4/src/parl_io/fifo_cfg.rs
index 005b5e1292..b248788cca 100644
--- a/esp32p4/src/parl_io/fifo_cfg.rs
+++ b/esp32p4/src/parl_io/fifo_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CFG")
-            .field(
-                "tx_fifo_srst",
-                &format_args!("{}", self.tx_fifo_srst().bit()),
-            )
-            .field(
-                "rx_fifo_srst",
-                &format_args!("{}", self.rx_fifo_srst().bit()),
-            )
+            .field("tx_fifo_srst", &self.tx_fifo_srst())
+            .field("rx_fifo_srst", &self.rx_fifo_srst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - Set this bit to reset async fifo in tx module."]
     #[inline(always)]
diff --git a/esp32p4/src/parl_io/int_ena.rs b/esp32p4/src/parl_io/int_ena.rs
index 305aeb2eda..426fde28df 100644
--- a/esp32p4/src/parl_io/int_ena.rs
+++ b/esp32p4/src/parl_io/int_ena.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "tx_fifo_rempty",
-                &format_args!("{}", self.tx_fifo_rempty().bit()),
-            )
-            .field(
-                "rx_fifo_wovf",
-                &format_args!("{}", self.rx_fifo_wovf().bit()),
-            )
-            .field("tx_eof", &format_args!("{}", self.tx_eof().bit()))
+            .field("tx_fifo_rempty", &self.tx_fifo_rempty())
+            .field("rx_fifo_wovf", &self.rx_fifo_wovf())
+            .field("tx_eof", &self.tx_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable TX_FIFO_REMPTY_INT."]
     #[inline(always)]
diff --git a/esp32p4/src/parl_io/int_raw.rs b/esp32p4/src/parl_io/int_raw.rs
index a49950cddd..0b62801757 100644
--- a/esp32p4/src/parl_io/int_raw.rs
+++ b/esp32p4/src/parl_io/int_raw.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "tx_fifo_rempty",
-                &format_args!("{}", self.tx_fifo_rempty().bit()),
-            )
-            .field(
-                "rx_fifo_wovf",
-                &format_args!("{}", self.rx_fifo_wovf().bit()),
-            )
-            .field("tx_eof", &format_args!("{}", self.tx_eof().bit()))
+            .field("tx_fifo_rempty", &self.tx_fifo_rempty())
+            .field("rx_fifo_wovf", &self.rx_fifo_wovf())
+            .field("tx_eof", &self.tx_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt status of TX_FIFO_REMPTY_INT."]
     #[inline(always)]
diff --git a/esp32p4/src/parl_io/int_st.rs b/esp32p4/src/parl_io/int_st.rs
index e3459c434c..f0a02381dc 100644
--- a/esp32p4/src/parl_io/int_st.rs
+++ b/esp32p4/src/parl_io/int_st.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "tx_fifo_rempty",
-                &format_args!("{}", self.tx_fifo_rempty().bit()),
-            )
-            .field(
-                "rx_fifo_wovf",
-                &format_args!("{}", self.rx_fifo_wovf().bit()),
-            )
-            .field("tx_eof", &format_args!("{}", self.tx_eof().bit()))
+            .field("tx_fifo_rempty", &self.tx_fifo_rempty())
+            .field("rx_fifo_wovf", &self.rx_fifo_wovf())
+            .field("tx_eof", &self.tx_eof())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Parallel IO interrupt singal status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/parl_io/rx_clk_cfg.rs b/esp32p4/src/parl_io/rx_clk_cfg.rs
index 41d97f4f41..5b1df21c96 100644
--- a/esp32p4/src/parl_io/rx_clk_cfg.rs
+++ b/esp32p4/src/parl_io/rx_clk_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CLK_CFG")
-            .field(
-                "rx_clk_i_inv",
-                &format_args!("{}", self.rx_clk_i_inv().bit()),
-            )
-            .field(
-                "rx_clk_o_inv",
-                &format_args!("{}", self.rx_clk_o_inv().bit()),
-            )
+            .field("rx_clk_i_inv", &self.rx_clk_i_inv())
+            .field("rx_clk_o_inv", &self.rx_clk_o_inv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CLK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - Set this bit to invert the input Rx core clock."]
     #[inline(always)]
diff --git a/esp32p4/src/parl_io/rx_data_cfg.rs b/esp32p4/src/parl_io/rx_data_cfg.rs
index 782441df10..1df2b7993f 100644
--- a/esp32p4/src/parl_io/rx_data_cfg.rs
+++ b/esp32p4/src/parl_io/rx_data_cfg.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_DATA_CFG")
-            .field("rx_bitlen", &format_args!("{}", self.rx_bitlen().bits()))
-            .field(
-                "rx_data_order_inv",
-                &format_args!("{}", self.rx_data_order_inv().bit()),
-            )
-            .field(
-                "rx_bus_wid_sel",
-                &format_args!("{}", self.rx_bus_wid_sel().bits()),
-            )
+            .field("rx_bitlen", &self.rx_bitlen())
+            .field("rx_data_order_inv", &self.rx_data_order_inv())
+            .field("rx_bus_wid_sel", &self.rx_bus_wid_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_DATA_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 9:27 - Configures expected byte number of received data."]
     #[inline(always)]
diff --git a/esp32p4/src/parl_io/rx_genrl_cfg.rs b/esp32p4/src/parl_io/rx_genrl_cfg.rs
index 1984b6f19d..299a16daa0 100644
--- a/esp32p4/src/parl_io/rx_genrl_cfg.rs
+++ b/esp32p4/src/parl_io/rx_genrl_cfg.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_GENRL_CFG")
-            .field(
-                "rx_gating_en",
-                &format_args!("{}", self.rx_gating_en().bit()),
-            )
-            .field(
-                "rx_timeout_thres",
-                &format_args!("{}", self.rx_timeout_thres().bits()),
-            )
-            .field(
-                "rx_timeout_en",
-                &format_args!("{}", self.rx_timeout_en().bit()),
-            )
-            .field(
-                "rx_eof_gen_sel",
-                &format_args!("{}", self.rx_eof_gen_sel().bit()),
-            )
+            .field("rx_gating_en", &self.rx_gating_en())
+            .field("rx_timeout_thres", &self.rx_timeout_thres())
+            .field("rx_timeout_en", &self.rx_timeout_en())
+            .field("rx_eof_gen_sel", &self.rx_eof_gen_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_GENRL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to enable the clock gating of output rx clock."]
     #[inline(always)]
diff --git a/esp32p4/src/parl_io/rx_mode_cfg.rs b/esp32p4/src/parl_io/rx_mode_cfg.rs
index 9cc0e559dd..20f1277bb8 100644
--- a/esp32p4/src/parl_io/rx_mode_cfg.rs
+++ b/esp32p4/src/parl_io/rx_mode_cfg.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_MODE_CFG")
-            .field(
-                "rx_ext_en_sel",
-                &format_args!("{}", self.rx_ext_en_sel().bits()),
-            )
-            .field("rx_sw_en", &format_args!("{}", self.rx_sw_en().bit()))
-            .field(
-                "rx_ext_en_inv",
-                &format_args!("{}", self.rx_ext_en_inv().bit()),
-            )
-            .field(
-                "rx_pulse_submode_sel",
-                &format_args!("{}", self.rx_pulse_submode_sel().bits()),
-            )
-            .field(
-                "rx_smp_mode_sel",
-                &format_args!("{}", self.rx_smp_mode_sel().bits()),
-            )
+            .field("rx_ext_en_sel", &self.rx_ext_en_sel())
+            .field("rx_sw_en", &self.rx_sw_en())
+            .field("rx_ext_en_inv", &self.rx_ext_en_inv())
+            .field("rx_pulse_submode_sel", &self.rx_pulse_submode_sel())
+            .field("rx_smp_mode_sel", &self.rx_smp_mode_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_MODE_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 21:24 - Configures rx external enable signal selection from IO PAD."]
     #[inline(always)]
diff --git a/esp32p4/src/parl_io/rx_st0.rs b/esp32p4/src/parl_io/rx_st0.rs
index a625514dcd..99f4dbf0a9 100644
--- a/esp32p4/src/parl_io/rx_st0.rs
+++ b/esp32p4/src/parl_io/rx_st0.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ST0")
-            .field("rx_cnt", &format_args!("{}", self.rx_cnt().bits()))
-            .field(
-                "rx_fifo_wr_bit_cnt",
-                &format_args!("{}", self.rx_fifo_wr_bit_cnt().bits()),
-            )
+            .field("rx_cnt", &self.rx_cnt())
+            .field("rx_fifo_wr_bit_cnt", &self.rx_fifo_wr_bit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ST0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Parallel IO RX status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_st0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_ST0_SPEC;
 impl crate::RegisterSpec for RX_ST0_SPEC {
diff --git a/esp32p4/src/parl_io/rx_st1.rs b/esp32p4/src/parl_io/rx_st1.rs
index f53d69a2fc..eb31daa2e2 100644
--- a/esp32p4/src/parl_io/rx_st1.rs
+++ b/esp32p4/src/parl_io/rx_st1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ST1")
-            .field(
-                "rx_fifo_rd_bit_cnt",
-                &format_args!("{}", self.rx_fifo_rd_bit_cnt().bits()),
-            )
+            .field("rx_fifo_rd_bit_cnt", &self.rx_fifo_rd_bit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ST1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Parallel IO RX status register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_st1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_ST1_SPEC;
 impl crate::RegisterSpec for RX_ST1_SPEC {
diff --git a/esp32p4/src/parl_io/rx_start_cfg.rs b/esp32p4/src/parl_io/rx_start_cfg.rs
index 2c998c6bf1..08d5d2193c 100644
--- a/esp32p4/src/parl_io/rx_start_cfg.rs
+++ b/esp32p4/src/parl_io/rx_start_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_START_CFG")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
+            .field("rx_start", &self.rx_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_START_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Set this bit to start rx data sampling."]
     #[inline(always)]
diff --git a/esp32p4/src/parl_io/st.rs b/esp32p4/src/parl_io/st.rs
index 18b48fe330..728d6ffa71 100644
--- a/esp32p4/src/parl_io/st.rs
+++ b/esp32p4/src/parl_io/st.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ST")
-            .field("tx_ready", &format_args!("{}", self.tx_ready().bit()))
+            .field("tx_ready", &self.tx_ready())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Parallel IO module status register0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ST_SPEC;
 impl crate::RegisterSpec for ST_SPEC {
diff --git a/esp32p4/src/parl_io/tx_clk_cfg.rs b/esp32p4/src/parl_io/tx_clk_cfg.rs
index 411ab4a196..2b14ef91a6 100644
--- a/esp32p4/src/parl_io/tx_clk_cfg.rs
+++ b/esp32p4/src/parl_io/tx_clk_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CLK_CFG")
-            .field(
-                "tx_clk_i_inv",
-                &format_args!("{}", self.tx_clk_i_inv().bit()),
-            )
-            .field(
-                "tx_clk_o_inv",
-                &format_args!("{}", self.tx_clk_o_inv().bit()),
-            )
+            .field("tx_clk_i_inv", &self.tx_clk_i_inv())
+            .field("tx_clk_o_inv", &self.tx_clk_o_inv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CLK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - Set this bit to invert the input Tx core clock."]
     #[inline(always)]
diff --git a/esp32p4/src/parl_io/tx_data_cfg.rs b/esp32p4/src/parl_io/tx_data_cfg.rs
index dc0e1063bd..e3c0e5c8cb 100644
--- a/esp32p4/src/parl_io/tx_data_cfg.rs
+++ b/esp32p4/src/parl_io/tx_data_cfg.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_DATA_CFG")
-            .field("tx_bitlen", &format_args!("{}", self.tx_bitlen().bits()))
-            .field(
-                "tx_data_order_inv",
-                &format_args!("{}", self.tx_data_order_inv().bit()),
-            )
-            .field(
-                "tx_bus_wid_sel",
-                &format_args!("{}", self.tx_bus_wid_sel().bits()),
-            )
+            .field("tx_bitlen", &self.tx_bitlen())
+            .field("tx_data_order_inv", &self.tx_data_order_inv())
+            .field("tx_bus_wid_sel", &self.tx_bus_wid_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_DATA_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 9:27 - Configures expected byte number of sent data."]
     #[inline(always)]
diff --git a/esp32p4/src/parl_io/tx_genrl_cfg.rs b/esp32p4/src/parl_io/tx_genrl_cfg.rs
index a9a9512c31..b775d539d5 100644
--- a/esp32p4/src/parl_io/tx_genrl_cfg.rs
+++ b/esp32p4/src/parl_io/tx_genrl_cfg.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_GENRL_CFG")
-            .field(
-                "tx_eof_gen_sel",
-                &format_args!("{}", self.tx_eof_gen_sel().bit()),
-            )
-            .field(
-                "tx_idle_value",
-                &format_args!("{}", self.tx_idle_value().bits()),
-            )
-            .field(
-                "tx_gating_en",
-                &format_args!("{}", self.tx_gating_en().bit()),
-            )
-            .field(
-                "tx_valid_output_en",
-                &format_args!("{}", self.tx_valid_output_en().bit()),
-            )
+            .field("tx_eof_gen_sel", &self.tx_eof_gen_sel())
+            .field("tx_idle_value", &self.tx_idle_value())
+            .field("tx_gating_en", &self.tx_gating_en())
+            .field("tx_valid_output_en", &self.tx_valid_output_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_GENRL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by DMA eof."]
     #[inline(always)]
diff --git a/esp32p4/src/parl_io/tx_st0.rs b/esp32p4/src/parl_io/tx_st0.rs
index ef866a2ae3..e3b75faa64 100644
--- a/esp32p4/src/parl_io/tx_st0.rs
+++ b/esp32p4/src/parl_io/tx_st0.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_ST0")
-            .field("tx_cnt", &format_args!("{}", self.tx_cnt().bits()))
-            .field(
-                "tx_fifo_rd_bit_cnt",
-                &format_args!("{}", self.tx_fifo_rd_bit_cnt().bits()),
-            )
+            .field("tx_cnt", &self.tx_cnt())
+            .field("tx_fifo_rd_bit_cnt", &self.tx_fifo_rd_bit_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_ST0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Parallel IO TX status register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_st0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TX_ST0_SPEC;
 impl crate::RegisterSpec for TX_ST0_SPEC {
diff --git a/esp32p4/src/parl_io/tx_start_cfg.rs b/esp32p4/src/parl_io/tx_start_cfg.rs
index fa2341b17a..fd377658e8 100644
--- a/esp32p4/src/parl_io/tx_start_cfg.rs
+++ b/esp32p4/src/parl_io/tx_start_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_START_CFG")
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
+            .field("tx_start", &self.tx_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_START_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Set this bit to start tx data transmit."]
     #[inline(always)]
diff --git a/esp32p4/src/parl_io/version.rs b/esp32p4/src/parl_io/version.rs
index 70ecf017bf..8eeb8aee1d 100644
--- a/esp32p4/src/parl_io/version.rs
+++ b/esp32p4/src/parl_io/version.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version of this register file"]
     #[inline(always)]
diff --git a/esp32p4/src/pau/date.rs b/esp32p4/src/pau/date.rs
index 3b18bdc4fe..0b7173416e 100644
--- a/esp32p4/src/pau/date.rs
+++ b/esp32p4/src/pau/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/pau/int_ena.rs b/esp32p4/src/pau/int_ena.rs
index a424ba5145..011fec4c81 100644
--- a/esp32p4/src/pau/int_ena.rs
+++ b/esp32p4/src/pau/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("error", &format_args!("{}", self.error().bit()))
+            .field("done", &self.done())
+            .field("error", &self.error())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - backup done flag"]
     #[inline(always)]
diff --git a/esp32p4/src/pau/int_raw.rs b/esp32p4/src/pau/int_raw.rs
index d0b1838f1a..1003c8ece8 100644
--- a/esp32p4/src/pau/int_raw.rs
+++ b/esp32p4/src/pau/int_raw.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("error", &format_args!("{}", self.error().bit()))
+            .field("done", &self.done())
+            .field("error", &self.error())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - backup done flag"]
     #[inline(always)]
diff --git a/esp32p4/src/pau/int_st.rs b/esp32p4/src/pau/int_st.rs
index 8a0bf89170..d6834ae88d 100644
--- a/esp32p4/src/pau/int_st.rs
+++ b/esp32p4/src/pau/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("error", &format_args!("{}", self.error().bit()))
+            .field("done", &self.done())
+            .field("error", &self.error())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Read only register for error and done\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/pau/regdma_backup_addr.rs b/esp32p4/src/pau/regdma_backup_addr.rs
index 3789b97494..06640e6e76 100644
--- a/esp32p4/src/pau/regdma_backup_addr.rs
+++ b/esp32p4/src/pau/regdma_backup_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_BACKUP_ADDR")
-            .field(
-                "backup_addr",
-                &format_args!("{}", self.backup_addr().bits()),
-            )
+            .field("backup_addr", &self.backup_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_BACKUP_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Backup addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_backup_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REGDMA_BACKUP_ADDR_SPEC;
 impl crate::RegisterSpec for REGDMA_BACKUP_ADDR_SPEC {
diff --git a/esp32p4/src/pau/regdma_bkp_conf.rs b/esp32p4/src/pau/regdma_bkp_conf.rs
index b373fb172b..e25f46eba5 100644
--- a/esp32p4/src/pau/regdma_bkp_conf.rs
+++ b/esp32p4/src/pau/regdma_bkp_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_BKP_CONF")
-            .field(
-                "read_interval",
-                &format_args!("{}", self.read_interval().bits()),
-            )
-            .field(
-                "link_tout_thres",
-                &format_args!("{}", self.link_tout_thres().bits()),
-            )
-            .field(
-                "burst_limit",
-                &format_args!("{}", self.burst_limit().bits()),
-            )
-            .field(
-                "backup_tout_thres",
-                &format_args!("{}", self.backup_tout_thres().bits()),
-            )
+            .field("read_interval", &self.read_interval())
+            .field("link_tout_thres", &self.link_tout_thres())
+            .field("burst_limit", &self.burst_limit())
+            .field("backup_tout_thres", &self.backup_tout_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_BKP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Link read_interval"]
     #[inline(always)]
diff --git a/esp32p4/src/pau/regdma_clk_conf.rs b/esp32p4/src/pau/regdma_clk_conf.rs
index c61741bd1f..fec6254df5 100644
--- a/esp32p4/src/pau/regdma_clk_conf.rs
+++ b/esp32p4/src/pau/regdma_clk_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_CLK_CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - clock enable"]
     #[inline(always)]
diff --git a/esp32p4/src/pau/regdma_conf.rs b/esp32p4/src/pau/regdma_conf.rs
index ea713cee3a..676f794539 100644
--- a/esp32p4/src/pau/regdma_conf.rs
+++ b/esp32p4/src/pau/regdma_conf.rs
@@ -55,20 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_CONF")
-            .field("flow_err", &format_args!("{}", self.flow_err().bits()))
-            .field("to_mem", &format_args!("{}", self.to_mem().bit()))
-            .field("link_sel", &format_args!("{}", self.link_sel().bits()))
-            .field("to_mem_mac", &format_args!("{}", self.to_mem_mac().bit()))
-            .field("sel_mac", &format_args!("{}", self.sel_mac().bit()))
+            .field("flow_err", &self.flow_err())
+            .field("to_mem", &self.to_mem())
+            .field("link_sel", &self.link_sel())
+            .field("to_mem_mac", &self.to_mem_mac())
+            .field("sel_mac", &self.sel_mac())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - backup start signal"]
     #[inline(always)]
diff --git a/esp32p4/src/pau/regdma_current_link_addr.rs b/esp32p4/src/pau/regdma_current_link_addr.rs
index 4ca2373a2b..7e5133b489 100644
--- a/esp32p4/src/pau/regdma_current_link_addr.rs
+++ b/esp32p4/src/pau/regdma_current_link_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_CURRENT_LINK_ADDR")
-            .field(
-                "current_link_addr",
-                &format_args!("{}", self.current_link_addr().bits()),
-            )
+            .field("current_link_addr", &self.current_link_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_CURRENT_LINK_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "current link addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_current_link_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REGDMA_CURRENT_LINK_ADDR_SPEC;
 impl crate::RegisterSpec for REGDMA_CURRENT_LINK_ADDR_SPEC {
diff --git a/esp32p4/src/pau/regdma_link_0_addr.rs b/esp32p4/src/pau/regdma_link_0_addr.rs
index f415b2ede1..64d3ebfd0a 100644
--- a/esp32p4/src/pau/regdma_link_0_addr.rs
+++ b/esp32p4/src/pau/regdma_link_0_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_LINK_0_ADDR")
-            .field(
-                "link_addr_0",
-                &format_args!("{}", self.link_addr_0().bits()),
-            )
+            .field("link_addr_0", &self.link_addr_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - link_0_addr reg"]
     #[inline(always)]
diff --git a/esp32p4/src/pau/regdma_link_1_addr.rs b/esp32p4/src/pau/regdma_link_1_addr.rs
index 2974370620..c0d1614d2e 100644
--- a/esp32p4/src/pau/regdma_link_1_addr.rs
+++ b/esp32p4/src/pau/regdma_link_1_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_LINK_1_ADDR")
-            .field(
-                "link_addr_1",
-                &format_args!("{}", self.link_addr_1().bits()),
-            )
+            .field("link_addr_1", &self.link_addr_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Link_1_addr reg"]
     #[inline(always)]
diff --git a/esp32p4/src/pau/regdma_link_2_addr.rs b/esp32p4/src/pau/regdma_link_2_addr.rs
index dc5d14f41e..913a395db9 100644
--- a/esp32p4/src/pau/regdma_link_2_addr.rs
+++ b/esp32p4/src/pau/regdma_link_2_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_LINK_2_ADDR")
-            .field(
-                "link_addr_2",
-                &format_args!("{}", self.link_addr_2().bits()),
-            )
+            .field("link_addr_2", &self.link_addr_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Link_2_addr reg"]
     #[inline(always)]
diff --git a/esp32p4/src/pau/regdma_link_3_addr.rs b/esp32p4/src/pau/regdma_link_3_addr.rs
index d8840a9794..1a77662e9c 100644
--- a/esp32p4/src/pau/regdma_link_3_addr.rs
+++ b/esp32p4/src/pau/regdma_link_3_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_LINK_3_ADDR")
-            .field(
-                "link_addr_3",
-                &format_args!("{}", self.link_addr_3().bits()),
-            )
+            .field("link_addr_3", &self.link_addr_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Link_3_addr reg"]
     #[inline(always)]
diff --git a/esp32p4/src/pau/regdma_link_mac_addr.rs b/esp32p4/src/pau/regdma_link_mac_addr.rs
index 9e524ad211..0781e7a9a0 100644
--- a/esp32p4/src/pau/regdma_link_mac_addr.rs
+++ b/esp32p4/src/pau/regdma_link_mac_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_LINK_MAC_ADDR")
-            .field(
-                "link_addr_mac",
-                &format_args!("{}", self.link_addr_mac().bits()),
-            )
+            .field("link_addr_mac", &self.link_addr_mac())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_MAC_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Link_mac_addr reg"]
     #[inline(always)]
diff --git a/esp32p4/src/pau/regdma_mem_addr.rs b/esp32p4/src/pau/regdma_mem_addr.rs
index b6fa3aa6d7..417bf965b3 100644
--- a/esp32p4/src/pau/regdma_mem_addr.rs
+++ b/esp32p4/src/pau/regdma_mem_addr.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGDMA_MEM_ADDR")
-            .field("mem_addr", &format_args!("{}", self.mem_addr().bits()))
+            .field("mem_addr", &self.mem_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGDMA_MEM_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_mem_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct REGDMA_MEM_ADDR_SPEC;
 impl crate::RegisterSpec for REGDMA_MEM_ADDR_SPEC {
diff --git a/esp32p4/src/pcnt/ctrl.rs b/esp32p4/src/pcnt/ctrl.rs
index 30cac499c3..5a0ba0a8ef 100644
--- a/esp32p4/src/pcnt/ctrl.rs
+++ b/esp32p4/src/pcnt/ctrl.rs
@@ -134,52 +134,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("cnt_rst_u0", &format_args!("{}", self.cnt_rst_u0().bit()))
-            .field("cnt_rst_u1", &format_args!("{}", self.cnt_rst_u1().bit()))
-            .field("cnt_rst_u2", &format_args!("{}", self.cnt_rst_u2().bit()))
-            .field("cnt_rst_u3", &format_args!("{}", self.cnt_rst_u3().bit()))
-            .field(
-                "cnt_pause_u0",
-                &format_args!("{}", self.cnt_pause_u0().bit()),
-            )
-            .field(
-                "cnt_pause_u1",
-                &format_args!("{}", self.cnt_pause_u1().bit()),
-            )
-            .field(
-                "cnt_pause_u2",
-                &format_args!("{}", self.cnt_pause_u2().bit()),
-            )
-            .field(
-                "cnt_pause_u3",
-                &format_args!("{}", self.cnt_pause_u3().bit()),
-            )
-            .field(
-                "dalta_change_en_u0",
-                &format_args!("{}", self.dalta_change_en_u0().bit()),
-            )
-            .field(
-                "dalta_change_en_u1",
-                &format_args!("{}", self.dalta_change_en_u1().bit()),
-            )
-            .field(
-                "dalta_change_en_u2",
-                &format_args!("{}", self.dalta_change_en_u2().bit()),
-            )
-            .field(
-                "dalta_change_en_u3",
-                &format_args!("{}", self.dalta_change_en_u3().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("cnt_rst_u0", &self.cnt_rst_u0())
+            .field("cnt_rst_u1", &self.cnt_rst_u1())
+            .field("cnt_rst_u2", &self.cnt_rst_u2())
+            .field("cnt_rst_u3", &self.cnt_rst_u3())
+            .field("cnt_pause_u0", &self.cnt_pause_u0())
+            .field("cnt_pause_u1", &self.cnt_pause_u1())
+            .field("cnt_pause_u2", &self.cnt_pause_u2())
+            .field("cnt_pause_u3", &self.cnt_pause_u3())
+            .field("dalta_change_en_u0", &self.dalta_change_en_u0())
+            .field("dalta_change_en_u1", &self.dalta_change_en_u1())
+            .field("dalta_change_en_u2", &self.dalta_change_en_u2())
+            .field("dalta_change_en_u3", &self.dalta_change_en_u3())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Set this bit to clear unit (0-3)'s counter."]
     #[doc = ""]
diff --git a/esp32p4/src/pcnt/date.rs b/esp32p4/src/pcnt/date.rs
index 644005f405..9bd78a3ce4 100644
--- a/esp32p4/src/pcnt/date.rs
+++ b/esp32p4/src/pcnt/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/pcnt/int_ena.rs b/esp32p4/src/pcnt/int_ena.rs
index 4423a16c83..7372693fe3 100644
--- a/esp32p4/src/pcnt/int_ena.rs
+++ b/esp32p4/src/pcnt/int_ena.rs
@@ -47,31 +47,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
     #[doc = ""]
diff --git a/esp32p4/src/pcnt/int_raw.rs b/esp32p4/src/pcnt/int_raw.rs
index 9730ee9237..1c6db4c12b 100644
--- a/esp32p4/src/pcnt/int_raw.rs
+++ b/esp32p4/src/pcnt/int_raw.rs
@@ -47,31 +47,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
     #[doc = ""]
diff --git a/esp32p4/src/pcnt/int_st.rs b/esp32p4/src/pcnt/int_st.rs
index d1a59c1bf3..870d7ad253 100644
--- a/esp32p4/src/pcnt/int_st.rs
+++ b/esp32p4/src/pcnt/int_st.rs
@@ -43,31 +43,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/pcnt/u0_change_conf.rs b/esp32p4/src/pcnt/u0_change_conf.rs
index caa9eb42a3..6f7350521c 100644
--- a/esp32p4/src/pcnt/u0_change_conf.rs
+++ b/esp32p4/src/pcnt/u0_change_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("U0_CHANGE_CONF")
-            .field(
-                "cnt_step_u0",
-                &format_args!("{}", self.cnt_step_u0().bits()),
-            )
-            .field(
-                "cnt_step_lim_u0",
-                &format_args!("{}", self.cnt_step_lim_u0().bits()),
-            )
+            .field("cnt_step_u0", &self.cnt_step_u0())
+            .field("cnt_step_lim_u0", &self.cnt_step_lim_u0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U0_CHANGE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures the step value for unit 0."]
     #[inline(always)]
diff --git a/esp32p4/src/pcnt/u1_change_conf.rs b/esp32p4/src/pcnt/u1_change_conf.rs
index 86fd78cf1d..468e7771ce 100644
--- a/esp32p4/src/pcnt/u1_change_conf.rs
+++ b/esp32p4/src/pcnt/u1_change_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("U1_CHANGE_CONF")
-            .field(
-                "cnt_step_u1",
-                &format_args!("{}", self.cnt_step_u1().bits()),
-            )
-            .field(
-                "cnt_step_lim_u1",
-                &format_args!("{}", self.cnt_step_lim_u1().bits()),
-            )
+            .field("cnt_step_u1", &self.cnt_step_u1())
+            .field("cnt_step_lim_u1", &self.cnt_step_lim_u1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U1_CHANGE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures the step value for unit 1."]
     #[inline(always)]
diff --git a/esp32p4/src/pcnt/u2_change_conf.rs b/esp32p4/src/pcnt/u2_change_conf.rs
index 726c9255a8..02c65b75b6 100644
--- a/esp32p4/src/pcnt/u2_change_conf.rs
+++ b/esp32p4/src/pcnt/u2_change_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("U2_CHANGE_CONF")
-            .field(
-                "cnt_step_u2",
-                &format_args!("{}", self.cnt_step_u2().bits()),
-            )
-            .field(
-                "cnt_step_lim_u2",
-                &format_args!("{}", self.cnt_step_lim_u2().bits()),
-            )
+            .field("cnt_step_u2", &self.cnt_step_u2())
+            .field("cnt_step_lim_u2", &self.cnt_step_lim_u2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U2_CHANGE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures the step value for unit 2."]
     #[inline(always)]
diff --git a/esp32p4/src/pcnt/u3_change_conf.rs b/esp32p4/src/pcnt/u3_change_conf.rs
index e347b05558..03f902a990 100644
--- a/esp32p4/src/pcnt/u3_change_conf.rs
+++ b/esp32p4/src/pcnt/u3_change_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("U3_CHANGE_CONF")
-            .field(
-                "cnt_step_u3",
-                &format_args!("{}", self.cnt_step_u3().bits()),
-            )
-            .field(
-                "cnt_step_lim_u3",
-                &format_args!("{}", self.cnt_step_lim_u3().bits()),
-            )
+            .field("cnt_step_u3", &self.cnt_step_u3())
+            .field("cnt_step_lim_u3", &self.cnt_step_lim_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U3_CHANGE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures the step value for unit 3."]
     #[inline(always)]
diff --git a/esp32p4/src/pcnt/u_cnt.rs b/esp32p4/src/pcnt/u_cnt.rs
index 34bef2c06c..7a45c58a0d 100644
--- a/esp32p4/src/pcnt/u_cnt.rs
+++ b/esp32p4/src/pcnt/u_cnt.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("U_CNT")
-            .field("cnt", &format_args!("{}", self.cnt().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("U_CNT").field("cnt", &self.cnt()).finish()
     }
 }
 #[doc = "Counter value for unit %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32p4/src/pcnt/u_status.rs b/esp32p4/src/pcnt/u_status.rs
index 408d450824..9d516e2c99 100644
--- a/esp32p4/src/pcnt/u_status.rs
+++ b/esp32p4/src/pcnt/u_status.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("U_STATUS")
-            .field("zero_mode", &format_args!("{}", self.zero_mode().bits()))
-            .field("thres1", &format_args!("{}", self.thres1().bit()))
-            .field("thres0", &format_args!("{}", self.thres0().bit()))
-            .field("l_lim", &format_args!("{}", self.l_lim().bit()))
-            .field("h_lim", &format_args!("{}", self.h_lim().bit()))
-            .field("zero", &format_args!("{}", self.zero().bit()))
+            .field("zero_mode", &self.zero_mode())
+            .field("thres1", &self.thres1())
+            .field("thres0", &self.thres0())
+            .field("l_lim", &self.l_lim())
+            .field("h_lim", &self.h_lim())
+            .field("zero", &self.zero())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "PNCT UNIT%s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct U_STATUS_SPEC;
 impl crate::RegisterSpec for U_STATUS_SPEC {
diff --git a/esp32p4/src/pcnt/unit/conf0.rs b/esp32p4/src/pcnt/unit/conf0.rs
index 96f657d7f6..11e74f3113 100644
--- a/esp32p4/src/pcnt/unit/conf0.rs
+++ b/esp32p4/src/pcnt/unit/conf0.rs
@@ -325,69 +325,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field(
-                "filter_thres",
-                &format_args!("{}", self.filter_thres().bits()),
-            )
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
-            .field("thr_zero_en", &format_args!("{}", self.thr_zero_en().bit()))
-            .field(
-                "thr_h_lim_en",
-                &format_args!("{}", self.thr_h_lim_en().bit()),
-            )
-            .field(
-                "thr_l_lim_en",
-                &format_args!("{}", self.thr_l_lim_en().bit()),
-            )
-            .field(
-                "thr_thres0_en",
-                &format_args!("{}", self.thr_thres0_en().bit()),
-            )
-            .field(
-                "thr_thres1_en",
-                &format_args!("{}", self.thr_thres1_en().bit()),
-            )
-            .field(
-                "ch0_neg_mode",
-                &format_args!("{}", self.ch0_neg_mode().bits()),
-            )
-            .field(
-                "ch1_neg_mode",
-                &format_args!("{}", self.ch1_neg_mode().bits()),
-            )
-            .field(
-                "ch0_pos_mode",
-                &format_args!("{}", self.ch0_pos_mode().bits()),
-            )
-            .field(
-                "ch1_pos_mode",
-                &format_args!("{}", self.ch1_pos_mode().bits()),
-            )
-            .field(
-                "ch0_hctrl_mode",
-                &format_args!("{}", self.ch0_hctrl_mode().bits()),
-            )
-            .field(
-                "ch1_hctrl_mode",
-                &format_args!("{}", self.ch1_hctrl_mode().bits()),
-            )
-            .field(
-                "ch0_lctrl_mode",
-                &format_args!("{}", self.ch0_lctrl_mode().bits()),
-            )
-            .field(
-                "ch1_lctrl_mode",
-                &format_args!("{}", self.ch1_lctrl_mode().bits()),
-            )
+            .field("filter_thres", &self.filter_thres())
+            .field("filter_en", &self.filter_en())
+            .field("thr_zero_en", &self.thr_zero_en())
+            .field("thr_h_lim_en", &self.thr_h_lim_en())
+            .field("thr_l_lim_en", &self.thr_l_lim_en())
+            .field("thr_thres0_en", &self.thr_thres0_en())
+            .field("thr_thres1_en", &self.thr_thres1_en())
+            .field("ch0_neg_mode", &self.ch0_neg_mode())
+            .field("ch1_neg_mode", &self.ch1_neg_mode())
+            .field("ch0_pos_mode", &self.ch0_pos_mode())
+            .field("ch1_pos_mode", &self.ch1_pos_mode())
+            .field("ch0_hctrl_mode", &self.ch0_hctrl_mode())
+            .field("ch1_hctrl_mode", &self.ch1_hctrl_mode())
+            .field("ch0_lctrl_mode", &self.ch0_lctrl_mode())
+            .field("ch1_lctrl_mode", &self.ch1_lctrl_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
     #[inline(always)]
diff --git a/esp32p4/src/pcnt/unit/conf1.rs b/esp32p4/src/pcnt/unit/conf1.rs
index 62e92aa446..d516d127e6 100644
--- a/esp32p4/src/pcnt/unit/conf1.rs
+++ b/esp32p4/src/pcnt/unit/conf1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field("cnt_thres0", &format_args!("{}", self.cnt_thres0().bits()))
-            .field("cnt_thres1", &format_args!("{}", self.cnt_thres1().bits()))
+            .field("cnt_thres0", &self.cnt_thres0())
+            .field("cnt_thres1", &self.cnt_thres1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the thres0 value for unit %s."]
     #[inline(always)]
diff --git a/esp32p4/src/pcnt/unit/conf2.rs b/esp32p4/src/pcnt/unit/conf2.rs
index 0cdbbf2f56..11c700d6c3 100644
--- a/esp32p4/src/pcnt/unit/conf2.rs
+++ b/esp32p4/src/pcnt/unit/conf2.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF2")
-            .field("cnt_h_lim", &format_args!("{}", self.cnt_h_lim().bits()))
-            .field("cnt_l_lim", &format_args!("{}", self.cnt_l_lim().bits()))
+            .field("cnt_h_lim", &self.cnt_h_lim())
+            .field("cnt_l_lim", &self.cnt_l_lim())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the thr_h_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0."]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/backup_cfg.rs b/esp32p4/src/pmu/backup_cfg.rs
index e503db6afd..c2d51cd862 100644
--- a/esp32p4/src/pmu/backup_cfg.rs
+++ b/esp32p4/src/pmu/backup_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BACKUP_CFG")
-            .field(
-                "backup_sys_clk_no_div",
-                &format_args!("{}", self.backup_sys_clk_no_div().bit()),
-            )
+            .field("backup_sys_clk_no_div", &self.backup_sys_clk_no_div())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/clk_state0.rs b/esp32p4/src/pmu/clk_state0.rs
index 03ae474196..c4b3d553f3 100644
--- a/esp32p4/src/pmu/clk_state0.rs
+++ b/esp32p4/src/pmu/clk_state0.rs
@@ -118,79 +118,40 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_STATE0")
-            .field(
-                "stable_xpd_pll_state",
-                &format_args!("{}", self.stable_xpd_pll_state().bits()),
-            )
-            .field(
-                "stable_xpd_xtal_state",
-                &format_args!("{}", self.stable_xpd_xtal_state().bit()),
-            )
+            .field("stable_xpd_pll_state", &self.stable_xpd_pll_state())
+            .field("stable_xpd_xtal_state", &self.stable_xpd_xtal_state())
             .field(
                 "pmu_ana_xpd_pll_i2c_state",
-                &format_args!("{}", self.pmu_ana_xpd_pll_i2c_state().bits()),
+                &self.pmu_ana_xpd_pll_i2c_state(),
             )
             .field(
                 "pmu_sys_clk_slp_sel_state",
-                &format_args!("{}", self.pmu_sys_clk_slp_sel_state().bit()),
-            )
-            .field(
-                "pmu_sys_clk_sel_state",
-                &format_args!("{}", self.pmu_sys_clk_sel_state().bits()),
-            )
-            .field(
-                "pmu_sys_clk_no_div_state",
-                &format_args!("{}", self.pmu_sys_clk_no_div_state().bit()),
-            )
-            .field(
-                "pmu_icg_sys_clk_en_state",
-                &format_args!("{}", self.pmu_icg_sys_clk_en_state().bit()),
+                &self.pmu_sys_clk_slp_sel_state(),
             )
+            .field("pmu_sys_clk_sel_state", &self.pmu_sys_clk_sel_state())
+            .field("pmu_sys_clk_no_div_state", &self.pmu_sys_clk_no_div_state())
+            .field("pmu_icg_sys_clk_en_state", &self.pmu_icg_sys_clk_en_state())
             .field(
                 "pmu_icg_modem_switch_state",
-                &format_args!("{}", self.pmu_icg_modem_switch_state().bit()),
-            )
-            .field(
-                "pmu_icg_modem_code_state",
-                &format_args!("{}", self.pmu_icg_modem_code_state().bits()),
-            )
-            .field(
-                "pmu_icg_slp_sel_state",
-                &format_args!("{}", self.pmu_icg_slp_sel_state().bit()),
+                &self.pmu_icg_modem_switch_state(),
             )
+            .field("pmu_icg_modem_code_state", &self.pmu_icg_modem_code_state())
+            .field("pmu_icg_slp_sel_state", &self.pmu_icg_slp_sel_state())
             .field(
                 "pmu_icg_global_xtal_state",
-                &format_args!("{}", self.pmu_icg_global_xtal_state().bit()),
-            )
-            .field(
-                "pmu_icg_global_pll_state",
-                &format_args!("{}", self.pmu_icg_global_pll_state().bits()),
-            )
-            .field(
-                "pmu_ana_i2c_iso_en_state",
-                &format_args!("{}", self.pmu_ana_i2c_iso_en_state().bit()),
+                &self.pmu_icg_global_xtal_state(),
             )
+            .field("pmu_icg_global_pll_state", &self.pmu_icg_global_pll_state())
+            .field("pmu_ana_i2c_iso_en_state", &self.pmu_ana_i2c_iso_en_state())
             .field(
                 "pmu_ana_i2c_retention_state",
-                &format_args!("{}", self.pmu_ana_i2c_retention_state().bit()),
-            )
-            .field(
-                "pmu_ana_xpd_pll_state",
-                &format_args!("{}", self.pmu_ana_xpd_pll_state().bits()),
-            )
-            .field(
-                "pmu_ana_xpd_xtal_state",
-                &format_args!("{}", self.pmu_ana_xpd_xtal_state().bit()),
+                &self.pmu_ana_i2c_retention_state(),
             )
+            .field("pmu_ana_xpd_pll_state", &self.pmu_ana_xpd_pll_state())
+            .field("pmu_ana_xpd_xtal_state", &self.pmu_ana_xpd_xtal_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_state0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_STATE0_SPEC;
 impl crate::RegisterSpec for CLK_STATE0_SPEC {
diff --git a/esp32p4/src/pmu/clk_state1.rs b/esp32p4/src/pmu/clk_state1.rs
index 63b5db2ecf..d364b421b0 100644
--- a/esp32p4/src/pmu/clk_state1.rs
+++ b/esp32p4/src/pmu/clk_state1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_STATE1")
-            .field(
-                "pmu_icg_func_en_state",
-                &format_args!("{}", self.pmu_icg_func_en_state().bits()),
-            )
+            .field("pmu_icg_func_en_state", &self.pmu_icg_func_en_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_STATE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_state1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_STATE1_SPEC;
 impl crate::RegisterSpec for CLK_STATE1_SPEC {
diff --git a/esp32p4/src/pmu/clk_state2.rs b/esp32p4/src/pmu/clk_state2.rs
index 8fdb111279..7a942b9e8d 100644
--- a/esp32p4/src/pmu/clk_state2.rs
+++ b/esp32p4/src/pmu/clk_state2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_STATE2")
-            .field(
-                "pmu_icg_apb_en_state",
-                &format_args!("{}", self.pmu_icg_apb_en_state().bits()),
-            )
+            .field("pmu_icg_apb_en_state", &self.pmu_icg_apb_en_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_STATE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_state2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLK_STATE2_SPEC;
 impl crate::RegisterSpec for CLK_STATE2_SPEC {
diff --git a/esp32p4/src/pmu/cpu_sw_stall.rs b/esp32p4/src/pmu/cpu_sw_stall.rs
index 48f66adbcc..1606a45813 100644
--- a/esp32p4/src/pmu/cpu_sw_stall.rs
+++ b/esp32p4/src/pmu/cpu_sw_stall.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_SW_STALL")
-            .field(
-                "hpcore1_sw_stall_code",
-                &format_args!("{}", self.hpcore1_sw_stall_code().bits()),
-            )
-            .field(
-                "hpcore0_sw_stall_code",
-                &format_args!("{}", self.hpcore0_sw_stall_code().bits()),
-            )
+            .field("hpcore1_sw_stall_code", &self.hpcore1_sw_stall_code())
+            .field("hpcore0_sw_stall_code", &self.hpcore0_sw_stall_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_SW_STALL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:23 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/date.rs b/esp32p4/src/pmu/date.rs
index be7f67e31e..a83536b30b 100644
--- a/esp32p4/src/pmu/date.rs
+++ b/esp32p4/src/pmu/date.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("pmu_date", &format_args!("{}", self.pmu_date().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("pmu_date", &self.pmu_date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/dcm_ctrl.rs b/esp32p4/src/pmu/dcm_ctrl.rs
index 8083073f68..cb6850f231 100644
--- a/esp32p4/src/pmu/dcm_ctrl.rs
+++ b/esp32p4/src/pmu/dcm_ctrl.rs
@@ -113,56 +113,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCM_CTRL")
-            .field(
-                "dcdc_done_force",
-                &format_args!("{}", self.dcdc_done_force().bit()),
-            )
-            .field(
-                "dcdc_on_force_pu",
-                &format_args!("{}", self.dcdc_on_force_pu().bit()),
-            )
-            .field(
-                "dcdc_on_force_pd",
-                &format_args!("{}", self.dcdc_on_force_pd().bit()),
-            )
-            .field(
-                "dcdc_fb_res_force_pu",
-                &format_args!("{}", self.dcdc_fb_res_force_pu().bit()),
-            )
-            .field(
-                "dcdc_fb_res_force_pd",
-                &format_args!("{}", self.dcdc_fb_res_force_pd().bit()),
-            )
-            .field(
-                "dcdc_ls_force_pu",
-                &format_args!("{}", self.dcdc_ls_force_pu().bit()),
-            )
-            .field(
-                "dcdc_ls_force_pd",
-                &format_args!("{}", self.dcdc_ls_force_pd().bit()),
-            )
-            .field(
-                "dcdc_ds_force_pu",
-                &format_args!("{}", self.dcdc_ds_force_pu().bit()),
-            )
-            .field(
-                "dcdc_ds_force_pd",
-                &format_args!("{}", self.dcdc_ds_force_pd().bit()),
-            )
-            .field("dcm_cur_st", &format_args!("{}", self.dcm_cur_st().bits()))
-            .field(
-                "dcdc_en_amux_test",
-                &format_args!("{}", self.dcdc_en_amux_test().bit()),
-            )
+            .field("dcdc_done_force", &self.dcdc_done_force())
+            .field("dcdc_on_force_pu", &self.dcdc_on_force_pu())
+            .field("dcdc_on_force_pd", &self.dcdc_on_force_pd())
+            .field("dcdc_fb_res_force_pu", &self.dcdc_fb_res_force_pu())
+            .field("dcdc_fb_res_force_pd", &self.dcdc_fb_res_force_pd())
+            .field("dcdc_ls_force_pu", &self.dcdc_ls_force_pu())
+            .field("dcdc_ls_force_pd", &self.dcdc_ls_force_pd())
+            .field("dcdc_ds_force_pu", &self.dcdc_ds_force_pu())
+            .field("dcdc_ds_force_pd", &self.dcdc_ds_force_pd())
+            .field("dcm_cur_st", &self.dcm_cur_st())
+            .field("dcdc_en_amux_test", &self.dcdc_en_amux_test())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SW trigger dcdc on"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/dcm_wait_delay.rs b/esp32p4/src/pmu/dcm_wait_delay.rs
index d716711d16..73ce330836 100644
--- a/esp32p4/src/pmu/dcm_wait_delay.rs
+++ b/esp32p4/src/pmu/dcm_wait_delay.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCM_WAIT_DELAY")
-            .field(
-                "dcdc_pre_delay",
-                &format_args!("{}", self.dcdc_pre_delay().bits()),
-            )
-            .field(
-                "dcdc_res_off_delay",
-                &format_args!("{}", self.dcdc_res_off_delay().bits()),
-            )
-            .field(
-                "dcdc_stable_delay",
-                &format_args!("{}", self.dcdc_stable_delay().bits()),
-            )
+            .field("dcdc_pre_delay", &self.dcdc_pre_delay())
+            .field("dcdc_res_off_delay", &self.dcdc_res_off_delay())
+            .field("dcdc_stable_delay", &self.dcdc_stable_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCM_WAIT_DELAY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - DCDC pre-on/post off delay"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_ldo_p0_0p1a.rs b/esp32p4/src/pmu/ext_ldo_p0_0p1a.rs
index bdb0d31236..8e16840f8a 100644
--- a/esp32p4/src/pmu/ext_ldo_p0_0p1a.rs
+++ b/esp32p4/src/pmu/ext_ldo_p0_0p1a.rs
@@ -89,48 +89,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_LDO_P0_0P1A")
-            .field(
-                "_0p1a_force_tieh_sel_0",
-                &format_args!("{}", self._0p1a_force_tieh_sel_0().bit()),
-            )
-            .field("_0p1a_xpd_0", &format_args!("{}", self._0p1a_xpd_0().bit()))
-            .field(
-                "_0p1a_tieh_sel_0",
-                &format_args!("{}", self._0p1a_tieh_sel_0().bits()),
-            )
-            .field(
-                "_0p1a_tieh_pos_en_0",
-                &format_args!("{}", self._0p1a_tieh_pos_en_0().bit()),
-            )
-            .field(
-                "_0p1a_tieh_neg_en_0",
-                &format_args!("{}", self._0p1a_tieh_neg_en_0().bit()),
-            )
-            .field(
-                "_0p1a_tieh_0",
-                &format_args!("{}", self._0p1a_tieh_0().bit()),
-            )
-            .field(
-                "_0p1a_target1_0",
-                &format_args!("{}", self._0p1a_target1_0().bits()),
-            )
-            .field(
-                "_0p1a_target0_0",
-                &format_args!("{}", self._0p1a_target0_0().bits()),
-            )
+            .field("_0p1a_force_tieh_sel_0", &self._0p1a_force_tieh_sel_0())
+            .field("_0p1a_xpd_0", &self._0p1a_xpd_0())
+            .field("_0p1a_tieh_sel_0", &self._0p1a_tieh_sel_0())
+            .field("_0p1a_tieh_pos_en_0", &self._0p1a_tieh_pos_en_0())
+            .field("_0p1a_tieh_neg_en_0", &self._0p1a_tieh_neg_en_0())
+            .field("_0p1a_tieh_0", &self._0p1a_tieh_0())
+            .field("_0p1a_target1_0", &self._0p1a_target1_0())
+            .field("_0p1a_target0_0", &self._0p1a_target0_0())
             .field(
                 "_0p1a_ldo_cnt_prescaler_sel_0",
-                &format_args!("{}", self._0p1a_ldo_cnt_prescaler_sel_0().bit()),
+                &self._0p1a_ldo_cnt_prescaler_sel_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_LDO_P0_0P1A_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_ldo_p0_0p1a_ana.rs b/esp32p4/src/pmu/ext_ldo_p0_0p1a_ana.rs
index fd79d19b0c..3b2e0cabe9 100644
--- a/esp32p4/src/pmu/ext_ldo_p0_0p1a_ana.rs
+++ b/esp32p4/src/pmu/ext_ldo_p0_0p1a_ana.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_LDO_P0_0P1A_ANA")
-            .field(
-                "ana_0p1a_mul_0",
-                &format_args!("{}", self.ana_0p1a_mul_0().bits()),
-            )
-            .field(
-                "ana_0p1a_en_vdet_0",
-                &format_args!("{}", self.ana_0p1a_en_vdet_0().bit()),
-            )
-            .field(
-                "ana_0p1a_en_cur_lim_0",
-                &format_args!("{}", self.ana_0p1a_en_cur_lim_0().bit()),
-            )
-            .field(
-                "ana_0p1a_dref_0",
-                &format_args!("{}", self.ana_0p1a_dref_0().bits()),
-            )
+            .field("ana_0p1a_mul_0", &self.ana_0p1a_mul_0())
+            .field("ana_0p1a_en_vdet_0", &self.ana_0p1a_en_vdet_0())
+            .field("ana_0p1a_en_cur_lim_0", &self.ana_0p1a_en_cur_lim_0())
+            .field("ana_0p1a_dref_0", &self.ana_0p1a_dref_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_LDO_P0_0P1A_ANA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:25 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_ldo_p0_0p2a.rs b/esp32p4/src/pmu/ext_ldo_p0_0p2a.rs
index d5ae44ebe2..ec35ae9b90 100644
--- a/esp32p4/src/pmu/ext_ldo_p0_0p2a.rs
+++ b/esp32p4/src/pmu/ext_ldo_p0_0p2a.rs
@@ -89,48 +89,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_LDO_P0_0P2A")
-            .field(
-                "_0p2a_force_tieh_sel_0",
-                &format_args!("{}", self._0p2a_force_tieh_sel_0().bit()),
-            )
-            .field("_0p2a_xpd_0", &format_args!("{}", self._0p2a_xpd_0().bit()))
-            .field(
-                "_0p2a_tieh_sel_0",
-                &format_args!("{}", self._0p2a_tieh_sel_0().bits()),
-            )
-            .field(
-                "_0p2a_tieh_pos_en_0",
-                &format_args!("{}", self._0p2a_tieh_pos_en_0().bit()),
-            )
-            .field(
-                "_0p2a_tieh_neg_en_0",
-                &format_args!("{}", self._0p2a_tieh_neg_en_0().bit()),
-            )
-            .field(
-                "_0p2a_tieh_0",
-                &format_args!("{}", self._0p2a_tieh_0().bit()),
-            )
-            .field(
-                "_0p2a_target1_0",
-                &format_args!("{}", self._0p2a_target1_0().bits()),
-            )
-            .field(
-                "_0p2a_target0_0",
-                &format_args!("{}", self._0p2a_target0_0().bits()),
-            )
+            .field("_0p2a_force_tieh_sel_0", &self._0p2a_force_tieh_sel_0())
+            .field("_0p2a_xpd_0", &self._0p2a_xpd_0())
+            .field("_0p2a_tieh_sel_0", &self._0p2a_tieh_sel_0())
+            .field("_0p2a_tieh_pos_en_0", &self._0p2a_tieh_pos_en_0())
+            .field("_0p2a_tieh_neg_en_0", &self._0p2a_tieh_neg_en_0())
+            .field("_0p2a_tieh_0", &self._0p2a_tieh_0())
+            .field("_0p2a_target1_0", &self._0p2a_target1_0())
+            .field("_0p2a_target0_0", &self._0p2a_target0_0())
             .field(
                 "_0p2a_ldo_cnt_prescaler_sel_0",
-                &format_args!("{}", self._0p2a_ldo_cnt_prescaler_sel_0().bit()),
+                &self._0p2a_ldo_cnt_prescaler_sel_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_LDO_P0_0P2A_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_ldo_p0_0p2a_ana.rs b/esp32p4/src/pmu/ext_ldo_p0_0p2a_ana.rs
index 3399369ec7..17c8e8506b 100644
--- a/esp32p4/src/pmu/ext_ldo_p0_0p2a_ana.rs
+++ b/esp32p4/src/pmu/ext_ldo_p0_0p2a_ana.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_LDO_P0_0P2A_ANA")
-            .field(
-                "ana_0p2a_mul_0",
-                &format_args!("{}", self.ana_0p2a_mul_0().bits()),
-            )
-            .field(
-                "ana_0p2a_en_vdet_0",
-                &format_args!("{}", self.ana_0p2a_en_vdet_0().bit()),
-            )
-            .field(
-                "ana_0p2a_en_cur_lim_0",
-                &format_args!("{}", self.ana_0p2a_en_cur_lim_0().bit()),
-            )
-            .field(
-                "ana_0p2a_dref_0",
-                &format_args!("{}", self.ana_0p2a_dref_0().bits()),
-            )
+            .field("ana_0p2a_mul_0", &self.ana_0p2a_mul_0())
+            .field("ana_0p2a_en_vdet_0", &self.ana_0p2a_en_vdet_0())
+            .field("ana_0p2a_en_cur_lim_0", &self.ana_0p2a_en_cur_lim_0())
+            .field("ana_0p2a_dref_0", &self.ana_0p2a_dref_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_LDO_P0_0P2A_ANA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:25 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_ldo_p0_0p3a.rs b/esp32p4/src/pmu/ext_ldo_p0_0p3a.rs
index 4d3a65e167..ab23884445 100644
--- a/esp32p4/src/pmu/ext_ldo_p0_0p3a.rs
+++ b/esp32p4/src/pmu/ext_ldo_p0_0p3a.rs
@@ -89,48 +89,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_LDO_P0_0P3A")
-            .field(
-                "_0p3a_force_tieh_sel_0",
-                &format_args!("{}", self._0p3a_force_tieh_sel_0().bit()),
-            )
-            .field("_0p3a_xpd_0", &format_args!("{}", self._0p3a_xpd_0().bit()))
-            .field(
-                "_0p3a_tieh_sel_0",
-                &format_args!("{}", self._0p3a_tieh_sel_0().bits()),
-            )
-            .field(
-                "_0p3a_tieh_pos_en_0",
-                &format_args!("{}", self._0p3a_tieh_pos_en_0().bit()),
-            )
-            .field(
-                "_0p3a_tieh_neg_en_0",
-                &format_args!("{}", self._0p3a_tieh_neg_en_0().bit()),
-            )
-            .field(
-                "_0p3a_tieh_0",
-                &format_args!("{}", self._0p3a_tieh_0().bit()),
-            )
-            .field(
-                "_0p3a_target1_0",
-                &format_args!("{}", self._0p3a_target1_0().bits()),
-            )
-            .field(
-                "_0p3a_target0_0",
-                &format_args!("{}", self._0p3a_target0_0().bits()),
-            )
+            .field("_0p3a_force_tieh_sel_0", &self._0p3a_force_tieh_sel_0())
+            .field("_0p3a_xpd_0", &self._0p3a_xpd_0())
+            .field("_0p3a_tieh_sel_0", &self._0p3a_tieh_sel_0())
+            .field("_0p3a_tieh_pos_en_0", &self._0p3a_tieh_pos_en_0())
+            .field("_0p3a_tieh_neg_en_0", &self._0p3a_tieh_neg_en_0())
+            .field("_0p3a_tieh_0", &self._0p3a_tieh_0())
+            .field("_0p3a_target1_0", &self._0p3a_target1_0())
+            .field("_0p3a_target0_0", &self._0p3a_target0_0())
             .field(
                 "_0p3a_ldo_cnt_prescaler_sel_0",
-                &format_args!("{}", self._0p3a_ldo_cnt_prescaler_sel_0().bit()),
+                &self._0p3a_ldo_cnt_prescaler_sel_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_LDO_P0_0P3A_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_ldo_p0_0p3a_ana.rs b/esp32p4/src/pmu/ext_ldo_p0_0p3a_ana.rs
index ee5d060357..f17cfcbbe7 100644
--- a/esp32p4/src/pmu/ext_ldo_p0_0p3a_ana.rs
+++ b/esp32p4/src/pmu/ext_ldo_p0_0p3a_ana.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_LDO_P0_0P3A_ANA")
-            .field(
-                "ana_0p3a_mul_0",
-                &format_args!("{}", self.ana_0p3a_mul_0().bits()),
-            )
-            .field(
-                "ana_0p3a_en_vdet_0",
-                &format_args!("{}", self.ana_0p3a_en_vdet_0().bit()),
-            )
-            .field(
-                "ana_0p3a_en_cur_lim_0",
-                &format_args!("{}", self.ana_0p3a_en_cur_lim_0().bit()),
-            )
-            .field(
-                "ana_0p3a_dref_0",
-                &format_args!("{}", self.ana_0p3a_dref_0().bits()),
-            )
+            .field("ana_0p3a_mul_0", &self.ana_0p3a_mul_0())
+            .field("ana_0p3a_en_vdet_0", &self.ana_0p3a_en_vdet_0())
+            .field("ana_0p3a_en_cur_lim_0", &self.ana_0p3a_en_cur_lim_0())
+            .field("ana_0p3a_dref_0", &self.ana_0p3a_dref_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_LDO_P0_0P3A_ANA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:25 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_ldo_p1_0p1a.rs b/esp32p4/src/pmu/ext_ldo_p1_0p1a.rs
index 6a2ae01eeb..4eeb45a829 100644
--- a/esp32p4/src/pmu/ext_ldo_p1_0p1a.rs
+++ b/esp32p4/src/pmu/ext_ldo_p1_0p1a.rs
@@ -89,48 +89,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_LDO_P1_0P1A")
-            .field(
-                "_0p1a_force_tieh_sel_1",
-                &format_args!("{}", self._0p1a_force_tieh_sel_1().bit()),
-            )
-            .field("_0p1a_xpd_1", &format_args!("{}", self._0p1a_xpd_1().bit()))
-            .field(
-                "_0p1a_tieh_sel_1",
-                &format_args!("{}", self._0p1a_tieh_sel_1().bits()),
-            )
-            .field(
-                "_0p1a_tieh_pos_en_1",
-                &format_args!("{}", self._0p1a_tieh_pos_en_1().bit()),
-            )
-            .field(
-                "_0p1a_tieh_neg_en_1",
-                &format_args!("{}", self._0p1a_tieh_neg_en_1().bit()),
-            )
-            .field(
-                "_0p1a_tieh_1",
-                &format_args!("{}", self._0p1a_tieh_1().bit()),
-            )
-            .field(
-                "_0p1a_target1_1",
-                &format_args!("{}", self._0p1a_target1_1().bits()),
-            )
-            .field(
-                "_0p1a_target0_1",
-                &format_args!("{}", self._0p1a_target0_1().bits()),
-            )
+            .field("_0p1a_force_tieh_sel_1", &self._0p1a_force_tieh_sel_1())
+            .field("_0p1a_xpd_1", &self._0p1a_xpd_1())
+            .field("_0p1a_tieh_sel_1", &self._0p1a_tieh_sel_1())
+            .field("_0p1a_tieh_pos_en_1", &self._0p1a_tieh_pos_en_1())
+            .field("_0p1a_tieh_neg_en_1", &self._0p1a_tieh_neg_en_1())
+            .field("_0p1a_tieh_1", &self._0p1a_tieh_1())
+            .field("_0p1a_target1_1", &self._0p1a_target1_1())
+            .field("_0p1a_target0_1", &self._0p1a_target0_1())
             .field(
                 "_0p1a_ldo_cnt_prescaler_sel_1",
-                &format_args!("{}", self._0p1a_ldo_cnt_prescaler_sel_1().bit()),
+                &self._0p1a_ldo_cnt_prescaler_sel_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_LDO_P1_0P1A_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_ldo_p1_0p1a_ana.rs b/esp32p4/src/pmu/ext_ldo_p1_0p1a_ana.rs
index 47cee90d54..ed863c43ee 100644
--- a/esp32p4/src/pmu/ext_ldo_p1_0p1a_ana.rs
+++ b/esp32p4/src/pmu/ext_ldo_p1_0p1a_ana.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_LDO_P1_0P1A_ANA")
-            .field(
-                "ana_0p1a_mul_1",
-                &format_args!("{}", self.ana_0p1a_mul_1().bits()),
-            )
-            .field(
-                "ana_0p1a_en_vdet_1",
-                &format_args!("{}", self.ana_0p1a_en_vdet_1().bit()),
-            )
-            .field(
-                "ana_0p1a_en_cur_lim_1",
-                &format_args!("{}", self.ana_0p1a_en_cur_lim_1().bit()),
-            )
-            .field(
-                "ana_0p1a_dref_1",
-                &format_args!("{}", self.ana_0p1a_dref_1().bits()),
-            )
+            .field("ana_0p1a_mul_1", &self.ana_0p1a_mul_1())
+            .field("ana_0p1a_en_vdet_1", &self.ana_0p1a_en_vdet_1())
+            .field("ana_0p1a_en_cur_lim_1", &self.ana_0p1a_en_cur_lim_1())
+            .field("ana_0p1a_dref_1", &self.ana_0p1a_dref_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_LDO_P1_0P1A_ANA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:25 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_ldo_p1_0p2a.rs b/esp32p4/src/pmu/ext_ldo_p1_0p2a.rs
index 757566f894..aa9434b21b 100644
--- a/esp32p4/src/pmu/ext_ldo_p1_0p2a.rs
+++ b/esp32p4/src/pmu/ext_ldo_p1_0p2a.rs
@@ -89,48 +89,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_LDO_P1_0P2A")
-            .field(
-                "_0p2a_force_tieh_sel_1",
-                &format_args!("{}", self._0p2a_force_tieh_sel_1().bit()),
-            )
-            .field("_0p2a_xpd_1", &format_args!("{}", self._0p2a_xpd_1().bit()))
-            .field(
-                "_0p2a_tieh_sel_1",
-                &format_args!("{}", self._0p2a_tieh_sel_1().bits()),
-            )
-            .field(
-                "_0p2a_tieh_pos_en_1",
-                &format_args!("{}", self._0p2a_tieh_pos_en_1().bit()),
-            )
-            .field(
-                "_0p2a_tieh_neg_en_1",
-                &format_args!("{}", self._0p2a_tieh_neg_en_1().bit()),
-            )
-            .field(
-                "_0p2a_tieh_1",
-                &format_args!("{}", self._0p2a_tieh_1().bit()),
-            )
-            .field(
-                "_0p2a_target1_1",
-                &format_args!("{}", self._0p2a_target1_1().bits()),
-            )
-            .field(
-                "_0p2a_target0_1",
-                &format_args!("{}", self._0p2a_target0_1().bits()),
-            )
+            .field("_0p2a_force_tieh_sel_1", &self._0p2a_force_tieh_sel_1())
+            .field("_0p2a_xpd_1", &self._0p2a_xpd_1())
+            .field("_0p2a_tieh_sel_1", &self._0p2a_tieh_sel_1())
+            .field("_0p2a_tieh_pos_en_1", &self._0p2a_tieh_pos_en_1())
+            .field("_0p2a_tieh_neg_en_1", &self._0p2a_tieh_neg_en_1())
+            .field("_0p2a_tieh_1", &self._0p2a_tieh_1())
+            .field("_0p2a_target1_1", &self._0p2a_target1_1())
+            .field("_0p2a_target0_1", &self._0p2a_target0_1())
             .field(
                 "_0p2a_ldo_cnt_prescaler_sel_1",
-                &format_args!("{}", self._0p2a_ldo_cnt_prescaler_sel_1().bit()),
+                &self._0p2a_ldo_cnt_prescaler_sel_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_LDO_P1_0P2A_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_ldo_p1_0p2a_ana.rs b/esp32p4/src/pmu/ext_ldo_p1_0p2a_ana.rs
index fdc63f6c7f..3683e2ae71 100644
--- a/esp32p4/src/pmu/ext_ldo_p1_0p2a_ana.rs
+++ b/esp32p4/src/pmu/ext_ldo_p1_0p2a_ana.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_LDO_P1_0P2A_ANA")
-            .field(
-                "ana_0p2a_mul_1",
-                &format_args!("{}", self.ana_0p2a_mul_1().bits()),
-            )
-            .field(
-                "ana_0p2a_en_vdet_1",
-                &format_args!("{}", self.ana_0p2a_en_vdet_1().bit()),
-            )
-            .field(
-                "ana_0p2a_en_cur_lim_1",
-                &format_args!("{}", self.ana_0p2a_en_cur_lim_1().bit()),
-            )
-            .field(
-                "ana_0p2a_dref_1",
-                &format_args!("{}", self.ana_0p2a_dref_1().bits()),
-            )
+            .field("ana_0p2a_mul_1", &self.ana_0p2a_mul_1())
+            .field("ana_0p2a_en_vdet_1", &self.ana_0p2a_en_vdet_1())
+            .field("ana_0p2a_en_cur_lim_1", &self.ana_0p2a_en_cur_lim_1())
+            .field("ana_0p2a_dref_1", &self.ana_0p2a_dref_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_LDO_P1_0P2A_ANA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:25 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_ldo_p1_0p3a.rs b/esp32p4/src/pmu/ext_ldo_p1_0p3a.rs
index 4fb1f9cae6..cf687e85e5 100644
--- a/esp32p4/src/pmu/ext_ldo_p1_0p3a.rs
+++ b/esp32p4/src/pmu/ext_ldo_p1_0p3a.rs
@@ -89,48 +89,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_LDO_P1_0P3A")
-            .field(
-                "_0p3a_force_tieh_sel_1",
-                &format_args!("{}", self._0p3a_force_tieh_sel_1().bit()),
-            )
-            .field("_0p3a_xpd_1", &format_args!("{}", self._0p3a_xpd_1().bit()))
-            .field(
-                "_0p3a_tieh_sel_1",
-                &format_args!("{}", self._0p3a_tieh_sel_1().bits()),
-            )
-            .field(
-                "_0p3a_tieh_pos_en_1",
-                &format_args!("{}", self._0p3a_tieh_pos_en_1().bit()),
-            )
-            .field(
-                "_0p3a_tieh_neg_en_1",
-                &format_args!("{}", self._0p3a_tieh_neg_en_1().bit()),
-            )
-            .field(
-                "_0p3a_tieh_1",
-                &format_args!("{}", self._0p3a_tieh_1().bit()),
-            )
-            .field(
-                "_0p3a_target1_1",
-                &format_args!("{}", self._0p3a_target1_1().bits()),
-            )
-            .field(
-                "_0p3a_target0_1",
-                &format_args!("{}", self._0p3a_target0_1().bits()),
-            )
+            .field("_0p3a_force_tieh_sel_1", &self._0p3a_force_tieh_sel_1())
+            .field("_0p3a_xpd_1", &self._0p3a_xpd_1())
+            .field("_0p3a_tieh_sel_1", &self._0p3a_tieh_sel_1())
+            .field("_0p3a_tieh_pos_en_1", &self._0p3a_tieh_pos_en_1())
+            .field("_0p3a_tieh_neg_en_1", &self._0p3a_tieh_neg_en_1())
+            .field("_0p3a_tieh_1", &self._0p3a_tieh_1())
+            .field("_0p3a_target1_1", &self._0p3a_target1_1())
+            .field("_0p3a_target0_1", &self._0p3a_target0_1())
             .field(
                 "_0p3a_ldo_cnt_prescaler_sel_1",
-                &format_args!("{}", self._0p3a_ldo_cnt_prescaler_sel_1().bit()),
+                &self._0p3a_ldo_cnt_prescaler_sel_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_LDO_P1_0P3A_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_ldo_p1_0p3a_ana.rs b/esp32p4/src/pmu/ext_ldo_p1_0p3a_ana.rs
index d96431f73b..265e2a363d 100644
--- a/esp32p4/src/pmu/ext_ldo_p1_0p3a_ana.rs
+++ b/esp32p4/src/pmu/ext_ldo_p1_0p3a_ana.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_LDO_P1_0P3A_ANA")
-            .field(
-                "ana_0p3a_mul_1",
-                &format_args!("{}", self.ana_0p3a_mul_1().bits()),
-            )
-            .field(
-                "ana_0p3a_en_vdet_1",
-                &format_args!("{}", self.ana_0p3a_en_vdet_1().bit()),
-            )
-            .field(
-                "ana_0p3a_en_cur_lim_1",
-                &format_args!("{}", self.ana_0p3a_en_cur_lim_1().bit()),
-            )
-            .field(
-                "ana_0p3a_dref_1",
-                &format_args!("{}", self.ana_0p3a_dref_1().bits()),
-            )
+            .field("ana_0p3a_mul_1", &self.ana_0p3a_mul_1())
+            .field("ana_0p3a_en_vdet_1", &self.ana_0p3a_en_vdet_1())
+            .field("ana_0p3a_en_cur_lim_1", &self.ana_0p3a_en_cur_lim_1())
+            .field("ana_0p3a_dref_1", &self.ana_0p3a_dref_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_LDO_P1_0P3A_ANA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:25 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_wakeup_cntl.rs b/esp32p4/src/pmu/ext_wakeup_cntl.rs
index bbcd907440..fd979ad022 100644
--- a/esp32p4/src/pmu/ext_wakeup_cntl.rs
+++ b/esp32p4/src/pmu/ext_wakeup_cntl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP_CNTL")
-            .field(
-                "ext_wakeup_status_clr",
-                &format_args!("{}", self.ext_wakeup_status_clr().bit()),
-            )
-            .field(
-                "ext_wakeup_filter",
-                &format_args!("{}", self.ext_wakeup_filter().bit()),
-            )
+            .field("ext_wakeup_status_clr", &self.ext_wakeup_status_clr())
+            .field("ext_wakeup_filter", &self.ext_wakeup_filter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_wakeup_lv.rs b/esp32p4/src/pmu/ext_wakeup_lv.rs
index 3be775c29a..e2aa14c1ba 100644
--- a/esp32p4/src/pmu/ext_wakeup_lv.rs
+++ b/esp32p4/src/pmu/ext_wakeup_lv.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP_LV")
-            .field(
-                "ext_wakeup_lv",
-                &format_args!("{}", self.ext_wakeup_lv().bits()),
-            )
+            .field("ext_wakeup_lv", &self.ext_wakeup_lv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP_LV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_wakeup_sel.rs b/esp32p4/src/pmu/ext_wakeup_sel.rs
index d5d2000608..cdb8c14e19 100644
--- a/esp32p4/src/pmu/ext_wakeup_sel.rs
+++ b/esp32p4/src/pmu/ext_wakeup_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP_SEL")
-            .field(
-                "ext_wakeup_sel",
-                &format_args!("{}", self.ext_wakeup_sel().bits()),
-            )
+            .field("ext_wakeup_sel", &self.ext_wakeup_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/ext_wakeup_st.rs b/esp32p4/src/pmu/ext_wakeup_st.rs
index 8bfbc206a7..63273c7fd7 100644
--- a/esp32p4/src/pmu/ext_wakeup_st.rs
+++ b/esp32p4/src/pmu/ext_wakeup_st.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP_ST")
-            .field(
-                "ext_wakeup_status",
-                &format_args!("{}", self.ext_wakeup_status().bits()),
-            )
+            .field("ext_wakeup_status", &self.ext_wakeup_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXT_WAKEUP_ST_SPEC;
 impl crate::RegisterSpec for EXT_WAKEUP_ST_SPEC {
diff --git a/esp32p4/src/pmu/hp_active_backup.rs b/esp32p4/src/pmu/hp_active_backup.rs
index 62f9dc774b..121423fc4c 100644
--- a/esp32p4/src/pmu/hp_active_backup.rs
+++ b/esp32p4/src/pmu/hp_active_backup.rs
@@ -109,57 +109,48 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_BACKUP")
             .field(
                 "hp_sleep2active_backup_modem_clk_code",
-                &format_args!("{}", self.hp_sleep2active_backup_modem_clk_code().bits()),
+                &self.hp_sleep2active_backup_modem_clk_code(),
             )
             .field(
                 "hp_modem2active_backup_modem_clk_code",
-                &format_args!("{}", self.hp_modem2active_backup_modem_clk_code().bits()),
-            )
-            .field(
-                "hp_active_retention_mode",
-                &format_args!("{}", self.hp_active_retention_mode().bit()),
+                &self.hp_modem2active_backup_modem_clk_code(),
             )
+            .field("hp_active_retention_mode", &self.hp_active_retention_mode())
             .field(
                 "hp_sleep2active_retention_en",
-                &format_args!("{}", self.hp_sleep2active_retention_en().bit()),
+                &self.hp_sleep2active_retention_en(),
             )
             .field(
                 "hp_modem2active_retention_en",
-                &format_args!("{}", self.hp_modem2active_retention_en().bit()),
+                &self.hp_modem2active_retention_en(),
             )
             .field(
                 "hp_sleep2active_backup_clk_sel",
-                &format_args!("{}", self.hp_sleep2active_backup_clk_sel().bits()),
+                &self.hp_sleep2active_backup_clk_sel(),
             )
             .field(
                 "hp_modem2active_backup_clk_sel",
-                &format_args!("{}", self.hp_modem2active_backup_clk_sel().bits()),
+                &self.hp_modem2active_backup_clk_sel(),
             )
             .field(
                 "hp_sleep2active_backup_mode",
-                &format_args!("{}", self.hp_sleep2active_backup_mode().bits()),
+                &self.hp_sleep2active_backup_mode(),
             )
             .field(
                 "hp_modem2active_backup_mode",
-                &format_args!("{}", self.hp_modem2active_backup_mode().bits()),
+                &self.hp_modem2active_backup_mode(),
             )
             .field(
                 "hp_sleep2active_backup_en",
-                &format_args!("{}", self.hp_sleep2active_backup_en().bit()),
+                &self.hp_sleep2active_backup_en(),
             )
             .field(
                 "hp_modem2active_backup_en",
-                &format_args!("{}", self.hp_modem2active_backup_en().bit()),
+                &self.hp_modem2active_backup_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_BACKUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 4:5 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_active_backup_clk.rs b/esp32p4/src/pmu/hp_active_backup_clk.rs
index 263dfe5caa..86da7e6aa1 100644
--- a/esp32p4/src/pmu/hp_active_backup_clk.rs
+++ b/esp32p4/src/pmu/hp_active_backup_clk.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_BACKUP_CLK")
             .field(
                 "hp_active_backup_icg_func_en",
-                &format_args!("{}", self.hp_active_backup_icg_func_en().bits()),
+                &self.hp_active_backup_icg_func_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_BACKUP_CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_active_bias.rs b/esp32p4/src/pmu/hp_active_bias.rs
index bedcab4f11..cf86bbd4fa 100644
--- a/esp32p4/src/pmu/hp_active_bias.rs
+++ b/esp32p4/src/pmu/hp_active_bias.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_BIAS")
-            .field(
-                "hp_active_dcm_vset",
-                &format_args!("{}", self.hp_active_dcm_vset().bits()),
-            )
-            .field(
-                "hp_active_dcm_mode",
-                &format_args!("{}", self.hp_active_dcm_mode().bits()),
-            )
-            .field(
-                "hp_active_xpd_bias",
-                &format_args!("{}", self.hp_active_xpd_bias().bit()),
-            )
-            .field(
-                "hp_active_dbg_atten",
-                &format_args!("{}", self.hp_active_dbg_atten().bits()),
-            )
-            .field(
-                "hp_active_pd_cur",
-                &format_args!("{}", self.hp_active_pd_cur().bit()),
-            )
-            .field("sleep", &format_args!("{}", self.sleep().bit()))
+            .field("hp_active_dcm_vset", &self.hp_active_dcm_vset())
+            .field("hp_active_dcm_mode", &self.hp_active_dcm_mode())
+            .field("hp_active_xpd_bias", &self.hp_active_xpd_bias())
+            .field("hp_active_dbg_atten", &self.hp_active_dbg_atten())
+            .field("hp_active_pd_cur", &self.hp_active_pd_cur())
+            .field("sleep", &self.sleep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_BIAS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 18:22 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_active_dig_power.rs b/esp32p4/src/pmu/hp_active_dig_power.rs
index 081e79e8f4..24194d5a1a 100644
--- a/esp32p4/src/pmu/hp_active_dig_power.rs
+++ b/esp32p4/src/pmu/hp_active_dig_power.rs
@@ -55,33 +55,18 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_DIG_POWER")
             .field(
                 "hp_active_dcdc_switch_pd_en",
-                &format_args!("{}", self.hp_active_dcdc_switch_pd_en().bit()),
-            )
-            .field(
-                "hp_active_hp_mem_dslp",
-                &format_args!("{}", self.hp_active_hp_mem_dslp().bit()),
+                &self.hp_active_dcdc_switch_pd_en(),
             )
+            .field("hp_active_hp_mem_dslp", &self.hp_active_hp_mem_dslp())
             .field(
                 "hp_active_pd_hp_mem_pd_en",
-                &format_args!("{}", self.hp_active_pd_hp_mem_pd_en().bit()),
-            )
-            .field(
-                "hp_active_pd_cnnt_pd_en",
-                &format_args!("{}", self.hp_active_pd_cnnt_pd_en().bit()),
-            )
-            .field(
-                "hp_active_pd_top_pd_en",
-                &format_args!("{}", self.hp_active_pd_top_pd_en().bit()),
+                &self.hp_active_pd_hp_mem_pd_en(),
             )
+            .field("hp_active_pd_cnnt_pd_en", &self.hp_active_pd_cnnt_pd_en())
+            .field("hp_active_pd_top_pd_en", &self.hp_active_pd_top_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_DIG_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_active_hp_ck_power.rs b/esp32p4/src/pmu/hp_active_hp_ck_power.rs
index 1d3f475dac..bacaa0f116 100644
--- a/esp32p4/src/pmu/hp_active_hp_ck_power.rs
+++ b/esp32p4/src/pmu/hp_active_hp_ck_power.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_HP_CK_POWER")
-            .field(
-                "hp_active_i2c_iso_en",
-                &format_args!("{}", self.hp_active_i2c_iso_en().bit()),
-            )
-            .field(
-                "hp_active_i2c_retention",
-                &format_args!("{}", self.hp_active_i2c_retention().bit()),
-            )
-            .field(
-                "hp_active_xpd_pll_i2c",
-                &format_args!("{}", self.hp_active_xpd_pll_i2c().bits()),
-            )
-            .field(
-                "hp_active_xpd_pll",
-                &format_args!("{}", self.hp_active_xpd_pll().bits()),
-            )
+            .field("hp_active_i2c_iso_en", &self.hp_active_i2c_iso_en())
+            .field("hp_active_i2c_retention", &self.hp_active_i2c_retention())
+            .field("hp_active_xpd_pll_i2c", &self.hp_active_xpd_pll_i2c())
+            .field("hp_active_xpd_pll", &self.hp_active_xpd_pll())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_HP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_active_hp_regulator0.rs b/esp32p4/src/pmu/hp_active_hp_regulator0.rs
index c85c10aa4e..28deda3186 100644
--- a/esp32p4/src/pmu/hp_active_hp_regulator0.rs
+++ b/esp32p4/src/pmu/hp_active_hp_regulator0.rs
@@ -89,51 +89,36 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_HP_REGULATOR0")
-            .field(
-                "lp_dbias_vol",
-                &format_args!("{}", self.lp_dbias_vol().bits()),
-            )
-            .field(
-                "hp_dbias_vol",
-                &format_args!("{}", self.hp_dbias_vol().bits()),
-            )
-            .field(
-                "dig_regulator0_dbias_sel",
-                &format_args!("{}", self.dig_regulator0_dbias_sel().bit()),
-            )
+            .field("lp_dbias_vol", &self.lp_dbias_vol())
+            .field("hp_dbias_vol", &self.hp_dbias_vol())
+            .field("dig_regulator0_dbias_sel", &self.dig_regulator0_dbias_sel())
             .field(
                 "hp_active_hp_regulator_slp_mem_xpd",
-                &format_args!("{}", self.hp_active_hp_regulator_slp_mem_xpd().bit()),
+                &self.hp_active_hp_regulator_slp_mem_xpd(),
             )
             .field(
                 "hp_active_hp_regulator_slp_logic_xpd",
-                &format_args!("{}", self.hp_active_hp_regulator_slp_logic_xpd().bit()),
+                &self.hp_active_hp_regulator_slp_logic_xpd(),
             )
             .field(
                 "hp_active_hp_regulator_xpd",
-                &format_args!("{}", self.hp_active_hp_regulator_xpd().bit()),
+                &self.hp_active_hp_regulator_xpd(),
             )
             .field(
                 "hp_active_hp_regulator_slp_mem_dbias",
-                &format_args!("{}", self.hp_active_hp_regulator_slp_mem_dbias().bits()),
+                &self.hp_active_hp_regulator_slp_mem_dbias(),
             )
             .field(
                 "hp_active_hp_regulator_slp_logic_dbias",
-                &format_args!("{}", self.hp_active_hp_regulator_slp_logic_dbias().bits()),
+                &self.hp_active_hp_regulator_slp_logic_dbias(),
             )
             .field(
                 "hp_active_hp_regulator_dbias",
-                &format_args!("{}", self.hp_active_hp_regulator_dbias().bits()),
+                &self.hp_active_hp_regulator_dbias(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_HP_REGULATOR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 14 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_active_hp_regulator1.rs b/esp32p4/src/pmu/hp_active_hp_regulator1.rs
index 277199ae41..d60672b27e 100644
--- a/esp32p4/src/pmu/hp_active_hp_regulator1.rs
+++ b/esp32p4/src/pmu/hp_active_hp_regulator1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_HP_REGULATOR1")
             .field(
                 "hp_active_hp_regulator_drv_b",
-                &format_args!("{}", self.hp_active_hp_regulator_drv_b().bits()),
+                &self.hp_active_hp_regulator_drv_b(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_HP_REGULATOR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 26:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_active_hp_sys_cntl.rs b/esp32p4/src/pmu/hp_active_hp_sys_cntl.rs
index 7e8c8ce961..a99cd24500 100644
--- a/esp32p4/src/pmu/hp_active_hp_sys_cntl.rs
+++ b/esp32p4/src/pmu/hp_active_hp_sys_cntl.rs
@@ -73,41 +73,26 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_HP_SYS_CNTL")
             .field(
                 "hp_active_hp_power_det_bypass",
-                &format_args!("{}", self.hp_active_hp_power_det_bypass().bit()),
-            )
-            .field(
-                "hp_active_uart_wakeup_en",
-                &format_args!("{}", self.hp_active_uart_wakeup_en().bit()),
+                &self.hp_active_hp_power_det_bypass(),
             )
+            .field("hp_active_uart_wakeup_en", &self.hp_active_uart_wakeup_en())
             .field(
                 "hp_active_lp_pad_hold_all",
-                &format_args!("{}", self.hp_active_lp_pad_hold_all().bit()),
+                &self.hp_active_lp_pad_hold_all(),
             )
             .field(
                 "hp_active_hp_pad_hold_all",
-                &format_args!("{}", self.hp_active_hp_pad_hold_all().bit()),
+                &self.hp_active_hp_pad_hold_all(),
             )
             .field(
                 "hp_active_dig_pad_slp_sel",
-                &format_args!("{}", self.hp_active_dig_pad_slp_sel().bit()),
-            )
-            .field(
-                "hp_active_dig_pause_wdt",
-                &format_args!("{}", self.hp_active_dig_pause_wdt().bit()),
-            )
-            .field(
-                "hp_active_dig_cpu_stall",
-                &format_args!("{}", self.hp_active_dig_cpu_stall().bit()),
+                &self.hp_active_dig_pad_slp_sel(),
             )
+            .field("hp_active_dig_pause_wdt", &self.hp_active_dig_pause_wdt())
+            .field("hp_active_dig_cpu_stall", &self.hp_active_dig_cpu_stall())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_HP_SYS_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 23 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_active_icg_hp_apb.rs b/esp32p4/src/pmu/hp_active_icg_hp_apb.rs
index 6f5c572621..bce128b876 100644
--- a/esp32p4/src/pmu/hp_active_icg_hp_apb.rs
+++ b/esp32p4/src/pmu/hp_active_icg_hp_apb.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_ICG_HP_APB")
-            .field(
-                "hp_active_dig_icg_apb_en",
-                &format_args!("{}", self.hp_active_dig_icg_apb_en().bits()),
-            )
+            .field("hp_active_dig_icg_apb_en", &self.hp_active_dig_icg_apb_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_ICG_HP_APB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_active_icg_hp_func.rs b/esp32p4/src/pmu/hp_active_icg_hp_func.rs
index 66f7bfc1cc..9702957d41 100644
--- a/esp32p4/src/pmu/hp_active_icg_hp_func.rs
+++ b/esp32p4/src/pmu/hp_active_icg_hp_func.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_ICG_HP_FUNC")
             .field(
                 "hp_active_dig_icg_func_en",
-                &format_args!("{}", self.hp_active_dig_icg_func_en().bits()),
+                &self.hp_active_dig_icg_func_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_ICG_HP_FUNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_active_icg_modem.rs b/esp32p4/src/pmu/hp_active_icg_modem.rs
index 6bec45bec6..191bc539f8 100644
--- a/esp32p4/src/pmu/hp_active_icg_modem.rs
+++ b/esp32p4/src/pmu/hp_active_icg_modem.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_ICG_MODEM")
             .field(
                 "hp_active_dig_icg_modem_code",
-                &format_args!("{}", self.hp_active_dig_icg_modem_code().bits()),
+                &self.hp_active_dig_icg_modem_code(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_ICG_MODEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 30:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_active_sysclk.rs b/esp32p4/src/pmu/hp_active_sysclk.rs
index 6c8183a1a1..210c9638ed 100644
--- a/esp32p4/src/pmu/hp_active_sysclk.rs
+++ b/esp32p4/src/pmu/hp_active_sysclk.rs
@@ -55,33 +55,24 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_ACTIVE_SYSCLK")
             .field(
                 "hp_active_dig_sys_clk_no_div",
-                &format_args!("{}", self.hp_active_dig_sys_clk_no_div().bit()),
+                &self.hp_active_dig_sys_clk_no_div(),
             )
             .field(
                 "hp_active_icg_sys_clock_en",
-                &format_args!("{}", self.hp_active_icg_sys_clock_en().bit()),
+                &self.hp_active_icg_sys_clock_en(),
             )
             .field(
                 "hp_active_sys_clk_slp_sel",
-                &format_args!("{}", self.hp_active_sys_clk_slp_sel().bit()),
-            )
-            .field(
-                "hp_active_icg_slp_sel",
-                &format_args!("{}", self.hp_active_icg_slp_sel().bit()),
+                &self.hp_active_sys_clk_slp_sel(),
             )
+            .field("hp_active_icg_slp_sel", &self.hp_active_icg_slp_sel())
             .field(
                 "hp_active_dig_sys_clk_sel",
-                &format_args!("{}", self.hp_active_dig_sys_clk_sel().bits()),
+                &self.hp_active_dig_sys_clk_sel(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_SYSCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_active_xtal.rs b/esp32p4/src/pmu/hp_active_xtal.rs
index 2bee4e63fa..9a8de33501 100644
--- a/esp32p4/src/pmu/hp_active_xtal.rs
+++ b/esp32p4/src/pmu/hp_active_xtal.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_ACTIVE_XTAL")
-            .field(
-                "hp_active_xpd_xtal",
-                &format_args!("{}", self.hp_active_xpd_xtal().bit()),
-            )
+            .field("hp_active_xpd_xtal", &self.hp_active_xpd_xtal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_ACTIVE_XTAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_ck_cntl.rs b/esp32p4/src/pmu/hp_ck_cntl.rs
index 324311fa38..a85fe2cf77 100644
--- a/esp32p4/src/pmu/hp_ck_cntl.rs
+++ b/esp32p4/src/pmu/hp_ck_cntl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_CK_CNTL")
-            .field(
-                "modify_icg_cntl_wait",
-                &format_args!("{}", self.modify_icg_cntl_wait().bits()),
-            )
-            .field(
-                "switch_icg_cntl_wait",
-                &format_args!("{}", self.switch_icg_cntl_wait().bits()),
-            )
+            .field("modify_icg_cntl_wait", &self.modify_icg_cntl_wait())
+            .field("switch_icg_cntl_wait", &self.switch_icg_cntl_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_CK_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_ck_poweron.rs b/esp32p4/src/pmu/hp_ck_poweron.rs
index 294f83088c..4242d0c588 100644
--- a/esp32p4/src/pmu/hp_ck_poweron.rs
+++ b/esp32p4/src/pmu/hp_ck_poweron.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_CK_POWERON")
-            .field(
-                "i2c_por_wait_target",
-                &format_args!("{}", self.i2c_por_wait_target().bits()),
-            )
+            .field("i2c_por_wait_target", &self.i2c_por_wait_target())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_CK_POWERON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_modem_dig_power.rs b/esp32p4/src/pmu/hp_modem_dig_power.rs
index 66bda2f5a3..0e446b9614 100644
--- a/esp32p4/src/pmu/hp_modem_dig_power.rs
+++ b/esp32p4/src/pmu/hp_modem_dig_power.rs
@@ -31,17 +31,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_MODEM_DIG_POWER")
             .field(
                 "hp_modem_dcdc_switch_pd_en",
-                &format_args!("{}", self.hp_modem_dcdc_switch_pd_en().bit()),
+                &self.hp_modem_dcdc_switch_pd_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_MODEM_DIG_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_regulator_cfg.rs b/esp32p4/src/pmu/hp_regulator_cfg.rs
index ad2910e8f2..d97579a523 100644
--- a/esp32p4/src/pmu/hp_regulator_cfg.rs
+++ b/esp32p4/src/pmu/hp_regulator_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_REGULATOR_CFG")
-            .field(
-                "dig_regulator_en_cal",
-                &format_args!("{}", self.dig_regulator_en_cal().bit()),
-            )
+            .field("dig_regulator_en_cal", &self.dig_regulator_en_cal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_REGULATOR_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_backup.rs b/esp32p4/src/pmu/hp_sleep_backup.rs
index 7f86bbd960..aa2cc24f40 100644
--- a/esp32p4/src/pmu/hp_sleep_backup.rs
+++ b/esp32p4/src/pmu/hp_sleep_backup.rs
@@ -109,57 +109,45 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_BACKUP")
             .field(
                 "hp_modem2sleep_backup_modem_clk_code",
-                &format_args!("{}", self.hp_modem2sleep_backup_modem_clk_code().bits()),
+                &self.hp_modem2sleep_backup_modem_clk_code(),
             )
             .field(
                 "hp_active2sleep_backup_modem_clk_code",
-                &format_args!("{}", self.hp_active2sleep_backup_modem_clk_code().bits()),
-            )
-            .field(
-                "hp_sleep_retention_mode",
-                &format_args!("{}", self.hp_sleep_retention_mode().bit()),
+                &self.hp_active2sleep_backup_modem_clk_code(),
             )
+            .field("hp_sleep_retention_mode", &self.hp_sleep_retention_mode())
             .field(
                 "hp_modem2sleep_retention_en",
-                &format_args!("{}", self.hp_modem2sleep_retention_en().bit()),
+                &self.hp_modem2sleep_retention_en(),
             )
             .field(
                 "hp_active2sleep_retention_en",
-                &format_args!("{}", self.hp_active2sleep_retention_en().bit()),
+                &self.hp_active2sleep_retention_en(),
             )
             .field(
                 "hp_modem2sleep_backup_clk_sel",
-                &format_args!("{}", self.hp_modem2sleep_backup_clk_sel().bits()),
+                &self.hp_modem2sleep_backup_clk_sel(),
             )
             .field(
                 "hp_active2sleep_backup_clk_sel",
-                &format_args!("{}", self.hp_active2sleep_backup_clk_sel().bits()),
+                &self.hp_active2sleep_backup_clk_sel(),
             )
             .field(
                 "hp_modem2sleep_backup_mode",
-                &format_args!("{}", self.hp_modem2sleep_backup_mode().bits()),
+                &self.hp_modem2sleep_backup_mode(),
             )
             .field(
                 "hp_active2sleep_backup_mode",
-                &format_args!("{}", self.hp_active2sleep_backup_mode().bits()),
-            )
-            .field(
-                "hp_modem2sleep_backup_en",
-                &format_args!("{}", self.hp_modem2sleep_backup_en().bit()),
+                &self.hp_active2sleep_backup_mode(),
             )
+            .field("hp_modem2sleep_backup_en", &self.hp_modem2sleep_backup_en())
             .field(
                 "hp_active2sleep_backup_en",
-                &format_args!("{}", self.hp_active2sleep_backup_en().bit()),
+                &self.hp_active2sleep_backup_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_BACKUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 6:7 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_backup_clk.rs b/esp32p4/src/pmu/hp_sleep_backup_clk.rs
index 614a958d65..e0fccffe56 100644
--- a/esp32p4/src/pmu/hp_sleep_backup_clk.rs
+++ b/esp32p4/src/pmu/hp_sleep_backup_clk.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_BACKUP_CLK")
             .field(
                 "hp_sleep_backup_icg_func_en",
-                &format_args!("{}", self.hp_sleep_backup_icg_func_en().bits()),
+                &self.hp_sleep_backup_icg_func_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_BACKUP_CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_bias.rs b/esp32p4/src/pmu/hp_sleep_bias.rs
index 8866b14791..604fd517d5 100644
--- a/esp32p4/src/pmu/hp_sleep_bias.rs
+++ b/esp32p4/src/pmu/hp_sleep_bias.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_BIAS")
-            .field(
-                "hp_sleep_dcm_vset",
-                &format_args!("{}", self.hp_sleep_dcm_vset().bits()),
-            )
-            .field(
-                "hp_sleep_dcm_mode",
-                &format_args!("{}", self.hp_sleep_dcm_mode().bits()),
-            )
-            .field(
-                "hp_sleep_xpd_bias",
-                &format_args!("{}", self.hp_sleep_xpd_bias().bit()),
-            )
-            .field(
-                "hp_sleep_dbg_atten",
-                &format_args!("{}", self.hp_sleep_dbg_atten().bits()),
-            )
-            .field(
-                "hp_sleep_pd_cur",
-                &format_args!("{}", self.hp_sleep_pd_cur().bit()),
-            )
-            .field("sleep", &format_args!("{}", self.sleep().bit()))
+            .field("hp_sleep_dcm_vset", &self.hp_sleep_dcm_vset())
+            .field("hp_sleep_dcm_mode", &self.hp_sleep_dcm_mode())
+            .field("hp_sleep_xpd_bias", &self.hp_sleep_xpd_bias())
+            .field("hp_sleep_dbg_atten", &self.hp_sleep_dbg_atten())
+            .field("hp_sleep_pd_cur", &self.hp_sleep_pd_cur())
+            .field("sleep", &self.sleep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_BIAS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 18:22 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_dig_power.rs b/esp32p4/src/pmu/hp_sleep_dig_power.rs
index 16ba2632de..cd4d998be8 100644
--- a/esp32p4/src/pmu/hp_sleep_dig_power.rs
+++ b/esp32p4/src/pmu/hp_sleep_dig_power.rs
@@ -55,33 +55,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_DIG_POWER")
             .field(
                 "hp_sleep_dcdc_switch_pd_en",
-                &format_args!("{}", self.hp_sleep_dcdc_switch_pd_en().bit()),
-            )
-            .field(
-                "hp_sleep_hp_mem_dslp",
-                &format_args!("{}", self.hp_sleep_hp_mem_dslp().bit()),
-            )
-            .field(
-                "hp_sleep_pd_hp_mem_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_hp_mem_pd_en().bit()),
-            )
-            .field(
-                "hp_sleep_pd_cnnt_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_cnnt_pd_en().bit()),
-            )
-            .field(
-                "hp_sleep_pd_top_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_top_pd_en().bit()),
+                &self.hp_sleep_dcdc_switch_pd_en(),
             )
+            .field("hp_sleep_hp_mem_dslp", &self.hp_sleep_hp_mem_dslp())
+            .field("hp_sleep_pd_hp_mem_pd_en", &self.hp_sleep_pd_hp_mem_pd_en())
+            .field("hp_sleep_pd_cnnt_pd_en", &self.hp_sleep_pd_cnnt_pd_en())
+            .field("hp_sleep_pd_top_pd_en", &self.hp_sleep_pd_top_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_DIG_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_hp_ck_power.rs b/esp32p4/src/pmu/hp_sleep_hp_ck_power.rs
index 4df376c86b..355bbd4160 100644
--- a/esp32p4/src/pmu/hp_sleep_hp_ck_power.rs
+++ b/esp32p4/src/pmu/hp_sleep_hp_ck_power.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_HP_CK_POWER")
-            .field(
-                "hp_sleep_i2c_iso_en",
-                &format_args!("{}", self.hp_sleep_i2c_iso_en().bit()),
-            )
-            .field(
-                "hp_sleep_i2c_retention",
-                &format_args!("{}", self.hp_sleep_i2c_retention().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_pll_i2c",
-                &format_args!("{}", self.hp_sleep_xpd_pll_i2c().bits()),
-            )
-            .field(
-                "hp_sleep_xpd_pll",
-                &format_args!("{}", self.hp_sleep_xpd_pll().bits()),
-            )
+            .field("hp_sleep_i2c_iso_en", &self.hp_sleep_i2c_iso_en())
+            .field("hp_sleep_i2c_retention", &self.hp_sleep_i2c_retention())
+            .field("hp_sleep_xpd_pll_i2c", &self.hp_sleep_xpd_pll_i2c())
+            .field("hp_sleep_xpd_pll", &self.hp_sleep_xpd_pll())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_HP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_hp_regulator0.rs b/esp32p4/src/pmu/hp_sleep_hp_regulator0.rs
index 84b261f38a..0d75042e74 100644
--- a/esp32p4/src/pmu/hp_sleep_hp_regulator0.rs
+++ b/esp32p4/src/pmu/hp_sleep_hp_regulator0.rs
@@ -64,37 +64,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_HP_REGULATOR0")
             .field(
                 "hp_sleep_hp_regulator_slp_mem_xpd",
-                &format_args!("{}", self.hp_sleep_hp_regulator_slp_mem_xpd().bit()),
+                &self.hp_sleep_hp_regulator_slp_mem_xpd(),
             )
             .field(
                 "hp_sleep_hp_regulator_slp_logic_xpd",
-                &format_args!("{}", self.hp_sleep_hp_regulator_slp_logic_xpd().bit()),
+                &self.hp_sleep_hp_regulator_slp_logic_xpd(),
             )
             .field(
                 "hp_sleep_hp_regulator_xpd",
-                &format_args!("{}", self.hp_sleep_hp_regulator_xpd().bit()),
+                &self.hp_sleep_hp_regulator_xpd(),
             )
             .field(
                 "hp_sleep_hp_regulator_slp_mem_dbias",
-                &format_args!("{}", self.hp_sleep_hp_regulator_slp_mem_dbias().bits()),
+                &self.hp_sleep_hp_regulator_slp_mem_dbias(),
             )
             .field(
                 "hp_sleep_hp_regulator_slp_logic_dbias",
-                &format_args!("{}", self.hp_sleep_hp_regulator_slp_logic_dbias().bits()),
+                &self.hp_sleep_hp_regulator_slp_logic_dbias(),
             )
             .field(
                 "hp_sleep_hp_regulator_dbias",
-                &format_args!("{}", self.hp_sleep_hp_regulator_dbias().bits()),
+                &self.hp_sleep_hp_regulator_dbias(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_HP_REGULATOR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_hp_regulator1.rs b/esp32p4/src/pmu/hp_sleep_hp_regulator1.rs
index 854b4a2537..a33174cd01 100644
--- a/esp32p4/src/pmu/hp_sleep_hp_regulator1.rs
+++ b/esp32p4/src/pmu/hp_sleep_hp_regulator1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_HP_REGULATOR1")
             .field(
                 "hp_sleep_hp_regulator_drv_b",
-                &format_args!("{}", self.hp_sleep_hp_regulator_drv_b().bits()),
+                &self.hp_sleep_hp_regulator_drv_b(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_HP_REGULATOR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 26:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_hp_sys_cntl.rs b/esp32p4/src/pmu/hp_sleep_hp_sys_cntl.rs
index a432b445a4..9881f51025 100644
--- a/esp32p4/src/pmu/hp_sleep_hp_sys_cntl.rs
+++ b/esp32p4/src/pmu/hp_sleep_hp_sys_cntl.rs
@@ -73,41 +73,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_HP_SYS_CNTL")
             .field(
                 "hp_sleep_hp_power_det_bypass",
-                &format_args!("{}", self.hp_sleep_hp_power_det_bypass().bit()),
-            )
-            .field(
-                "hp_sleep_uart_wakeup_en",
-                &format_args!("{}", self.hp_sleep_uart_wakeup_en().bit()),
-            )
-            .field(
-                "hp_sleep_lp_pad_hold_all",
-                &format_args!("{}", self.hp_sleep_lp_pad_hold_all().bit()),
-            )
-            .field(
-                "hp_sleep_hp_pad_hold_all",
-                &format_args!("{}", self.hp_sleep_hp_pad_hold_all().bit()),
-            )
-            .field(
-                "hp_sleep_dig_pad_slp_sel",
-                &format_args!("{}", self.hp_sleep_dig_pad_slp_sel().bit()),
-            )
-            .field(
-                "hp_sleep_dig_pause_wdt",
-                &format_args!("{}", self.hp_sleep_dig_pause_wdt().bit()),
-            )
-            .field(
-                "hp_sleep_dig_cpu_stall",
-                &format_args!("{}", self.hp_sleep_dig_cpu_stall().bit()),
+                &self.hp_sleep_hp_power_det_bypass(),
             )
+            .field("hp_sleep_uart_wakeup_en", &self.hp_sleep_uart_wakeup_en())
+            .field("hp_sleep_lp_pad_hold_all", &self.hp_sleep_lp_pad_hold_all())
+            .field("hp_sleep_hp_pad_hold_all", &self.hp_sleep_hp_pad_hold_all())
+            .field("hp_sleep_dig_pad_slp_sel", &self.hp_sleep_dig_pad_slp_sel())
+            .field("hp_sleep_dig_pause_wdt", &self.hp_sleep_dig_pause_wdt())
+            .field("hp_sleep_dig_cpu_stall", &self.hp_sleep_dig_cpu_stall())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_HP_SYS_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 23 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_icg_hp_apb.rs b/esp32p4/src/pmu/hp_sleep_icg_hp_apb.rs
index f88b25a3ef..528420839b 100644
--- a/esp32p4/src/pmu/hp_sleep_icg_hp_apb.rs
+++ b/esp32p4/src/pmu/hp_sleep_icg_hp_apb.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_ICG_HP_APB")
-            .field(
-                "hp_sleep_dig_icg_apb_en",
-                &format_args!("{}", self.hp_sleep_dig_icg_apb_en().bits()),
-            )
+            .field("hp_sleep_dig_icg_apb_en", &self.hp_sleep_dig_icg_apb_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_ICG_HP_APB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_icg_hp_func.rs b/esp32p4/src/pmu/hp_sleep_icg_hp_func.rs
index 7c25582392..a78d413e13 100644
--- a/esp32p4/src/pmu/hp_sleep_icg_hp_func.rs
+++ b/esp32p4/src/pmu/hp_sleep_icg_hp_func.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_ICG_HP_FUNC")
-            .field(
-                "hp_sleep_dig_icg_func_en",
-                &format_args!("{}", self.hp_sleep_dig_icg_func_en().bits()),
-            )
+            .field("hp_sleep_dig_icg_func_en", &self.hp_sleep_dig_icg_func_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_ICG_HP_FUNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_icg_modem.rs b/esp32p4/src/pmu/hp_sleep_icg_modem.rs
index 28d2bd644e..43fc5f1da0 100644
--- a/esp32p4/src/pmu/hp_sleep_icg_modem.rs
+++ b/esp32p4/src/pmu/hp_sleep_icg_modem.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_ICG_MODEM")
             .field(
                 "hp_sleep_dig_icg_modem_code",
-                &format_args!("{}", self.hp_sleep_dig_icg_modem_code().bits()),
+                &self.hp_sleep_dig_icg_modem_code(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_ICG_MODEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 30:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_lp_ck_power.rs b/esp32p4/src/pmu/hp_sleep_lp_ck_power.rs
index edf7b9db57..cccbc909c2 100644
--- a/esp32p4/src/pmu/hp_sleep_lp_ck_power.rs
+++ b/esp32p4/src/pmu/hp_sleep_lp_ck_power.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_LP_CK_POWER")
-            .field(
-                "hp_sleep_xpd_lppll",
-                &format_args!("{}", self.hp_sleep_xpd_lppll().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_xtal32k",
-                &format_args!("{}", self.hp_sleep_xpd_xtal32k().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_rc32k",
-                &format_args!("{}", self.hp_sleep_xpd_rc32k().bit()),
-            )
-            .field(
-                "hp_sleep_xpd_fosc_clk",
-                &format_args!("{}", self.hp_sleep_xpd_fosc_clk().bit()),
-            )
-            .field(
-                "hp_sleep_pd_osc_clk",
-                &format_args!("{}", self.hp_sleep_pd_osc_clk().bit()),
-            )
+            .field("hp_sleep_xpd_lppll", &self.hp_sleep_xpd_lppll())
+            .field("hp_sleep_xpd_xtal32k", &self.hp_sleep_xpd_xtal32k())
+            .field("hp_sleep_xpd_rc32k", &self.hp_sleep_xpd_rc32k())
+            .field("hp_sleep_xpd_fosc_clk", &self.hp_sleep_xpd_fosc_clk())
+            .field("hp_sleep_pd_osc_clk", &self.hp_sleep_pd_osc_clk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_LP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_lp_dig_power.rs b/esp32p4/src/pmu/hp_sleep_lp_dig_power.rs
index 1144f24450..055924f3ff 100644
--- a/esp32p4/src/pmu/hp_sleep_lp_dig_power.rs
+++ b/esp32p4/src/pmu/hp_sleep_lp_dig_power.rs
@@ -53,35 +53,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_LP_DIG_POWER")
-            .field(
-                "hp_sleep_lp_pad_slp_sel",
-                &format_args!("{}", self.hp_sleep_lp_pad_slp_sel().bit()),
-            )
-            .field(
-                "hp_sleep_bod_source_sel",
-                &format_args!("{}", self.hp_sleep_bod_source_sel().bit()),
-            )
-            .field(
-                "hp_sleep_vddbat_mode",
-                &format_args!("{}", self.hp_sleep_vddbat_mode().bits()),
-            )
-            .field(
-                "hp_sleep_lp_mem_dslp",
-                &format_args!("{}", self.hp_sleep_lp_mem_dslp().bit()),
-            )
+            .field("hp_sleep_lp_pad_slp_sel", &self.hp_sleep_lp_pad_slp_sel())
+            .field("hp_sleep_bod_source_sel", &self.hp_sleep_bod_source_sel())
+            .field("hp_sleep_vddbat_mode", &self.hp_sleep_vddbat_mode())
+            .field("hp_sleep_lp_mem_dslp", &self.hp_sleep_lp_mem_dslp())
             .field(
                 "hp_sleep_pd_lp_peri_pd_en",
-                &format_args!("{}", self.hp_sleep_pd_lp_peri_pd_en().bit()),
+                &self.hp_sleep_pd_lp_peri_pd_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_LP_DIG_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_lp_regulator0.rs b/esp32p4/src/pmu/hp_sleep_lp_regulator0.rs
index e4546dcb5d..f924dd5e5c 100644
--- a/esp32p4/src/pmu/hp_sleep_lp_regulator0.rs
+++ b/esp32p4/src/pmu/hp_sleep_lp_regulator0.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_LP_REGULATOR0")
             .field(
                 "hp_sleep_lp_regulator_slp_xpd",
-                &format_args!("{}", self.hp_sleep_lp_regulator_slp_xpd().bit()),
+                &self.hp_sleep_lp_regulator_slp_xpd(),
             )
             .field(
                 "hp_sleep_lp_regulator_xpd",
-                &format_args!("{}", self.hp_sleep_lp_regulator_xpd().bit()),
+                &self.hp_sleep_lp_regulator_xpd(),
             )
             .field(
                 "hp_sleep_lp_regulator_slp_dbias",
-                &format_args!("{}", self.hp_sleep_lp_regulator_slp_dbias().bits()),
+                &self.hp_sleep_lp_regulator_slp_dbias(),
             )
             .field(
                 "hp_sleep_lp_regulator_dbias",
-                &format_args!("{}", self.hp_sleep_lp_regulator_dbias().bits()),
+                &self.hp_sleep_lp_regulator_dbias(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_LP_REGULATOR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_lp_regulator1.rs b/esp32p4/src/pmu/hp_sleep_lp_regulator1.rs
index a0f77ccd89..4b01930a2b 100644
--- a/esp32p4/src/pmu/hp_sleep_lp_regulator1.rs
+++ b/esp32p4/src/pmu/hp_sleep_lp_regulator1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_LP_REGULATOR1")
             .field(
                 "hp_sleep_lp_regulator_drv_b",
-                &format_args!("{}", self.hp_sleep_lp_regulator_drv_b().bits()),
+                &self.hp_sleep_lp_regulator_drv_b(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_LP_REGULATOR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 26:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_sysclk.rs b/esp32p4/src/pmu/hp_sleep_sysclk.rs
index 747f40e916..774ea4245c 100644
--- a/esp32p4/src/pmu/hp_sleep_sysclk.rs
+++ b/esp32p4/src/pmu/hp_sleep_sysclk.rs
@@ -55,33 +55,18 @@ impl core::fmt::Debug for R {
         f.debug_struct("HP_SLEEP_SYSCLK")
             .field(
                 "hp_sleep_dig_sys_clk_no_div",
-                &format_args!("{}", self.hp_sleep_dig_sys_clk_no_div().bit()),
+                &self.hp_sleep_dig_sys_clk_no_div(),
             )
             .field(
                 "hp_sleep_icg_sys_clock_en",
-                &format_args!("{}", self.hp_sleep_icg_sys_clock_en().bit()),
-            )
-            .field(
-                "hp_sleep_sys_clk_slp_sel",
-                &format_args!("{}", self.hp_sleep_sys_clk_slp_sel().bit()),
-            )
-            .field(
-                "hp_sleep_icg_slp_sel",
-                &format_args!("{}", self.hp_sleep_icg_slp_sel().bit()),
-            )
-            .field(
-                "hp_sleep_dig_sys_clk_sel",
-                &format_args!("{}", self.hp_sleep_dig_sys_clk_sel().bits()),
+                &self.hp_sleep_icg_sys_clock_en(),
             )
+            .field("hp_sleep_sys_clk_slp_sel", &self.hp_sleep_sys_clk_slp_sel())
+            .field("hp_sleep_icg_slp_sel", &self.hp_sleep_icg_slp_sel())
+            .field("hp_sleep_dig_sys_clk_sel", &self.hp_sleep_dig_sys_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_SYSCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/hp_sleep_xtal.rs b/esp32p4/src/pmu/hp_sleep_xtal.rs
index 6a54e1ef0a..f1e6e47a01 100644
--- a/esp32p4/src/pmu/hp_sleep_xtal.rs
+++ b/esp32p4/src/pmu/hp_sleep_xtal.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HP_SLEEP_XTAL")
-            .field(
-                "hp_sleep_xpd_xtal",
-                &format_args!("{}", self.hp_sleep_xpd_xtal().bit()),
-            )
+            .field("hp_sleep_xpd_xtal", &self.hp_sleep_xpd_xtal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HP_SLEEP_XTAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/imm_hp_ck_power.rs b/esp32p4/src/pmu/imm_hp_ck_power.rs
index 9b2e5e5998..737d0969b4 100644
--- a/esp32p4/src/pmu/imm_hp_ck_power.rs
+++ b/esp32p4/src/pmu/imm_hp_ck_power.rs
@@ -50,23 +50,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMM_HP_CK_POWER")
-            .field(
-                "tie_low_cali_xtal_icg",
-                &format_args!("{}", self.tie_low_cali_xtal_icg().bit()),
-            )
-            .field(
-                "tie_high_cali_xtal_icg",
-                &format_args!("{}", self.tie_high_cali_xtal_icg().bit()),
-            )
+            .field("tie_low_cali_xtal_icg", &self.tie_low_cali_xtal_icg())
+            .field("tie_high_cali_xtal_icg", &self.tie_high_cali_xtal_icg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMM_HP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/imm_pad_hold_all.rs b/esp32p4/src/pmu/imm_pad_hold_all.rs
index 7d0c40d073..990b15e23f 100644
--- a/esp32p4/src/pmu/imm_pad_hold_all.rs
+++ b/esp32p4/src/pmu/imm_pad_hold_all.rs
@@ -41,24 +41,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IMM_PAD_HOLD_ALL")
-            .field("pad_slp_sel", &format_args!("{}", self.pad_slp_sel().bit()))
-            .field(
-                "lp_pad_hold_all",
-                &format_args!("{}", self.lp_pad_hold_all().bit()),
-            )
-            .field(
-                "hp_pad_hold_all",
-                &format_args!("{}", self.hp_pad_hold_all().bit()),
-            )
+            .field("pad_slp_sel", &self.pad_slp_sel())
+            .field("lp_pad_hold_all", &self.lp_pad_hold_all())
+            .field("hp_pad_hold_all", &self.hp_pad_hold_all())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IMM_PAD_HOLD_ALL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/int_ena.rs b/esp32p4/src/pmu/int_ena.rs
index eb15a25276..e4686408c8 100644
--- a/esp32p4/src/pmu/int_ena.rs
+++ b/esp32p4/src/pmu/int_ena.rs
@@ -163,69 +163,60 @@ impl core::fmt::Debug for R {
         f.debug_struct("INT_ENA")
             .field(
                 "_0p1a_cnt_target0_reach_0_hp",
-                &format_args!("{}", self._0p1a_cnt_target0_reach_0_hp().bit()),
+                &self._0p1a_cnt_target0_reach_0_hp(),
             )
             .field(
                 "_0p1a_cnt_target1_reach_0_hp",
-                &format_args!("{}", self._0p1a_cnt_target1_reach_0_hp().bit()),
+                &self._0p1a_cnt_target1_reach_0_hp(),
             )
             .field(
                 "_0p1a_cnt_target0_reach_1_hp",
-                &format_args!("{}", self._0p1a_cnt_target0_reach_1_hp().bit()),
+                &self._0p1a_cnt_target0_reach_1_hp(),
             )
             .field(
                 "_0p1a_cnt_target1_reach_1_hp",
-                &format_args!("{}", self._0p1a_cnt_target1_reach_1_hp().bit()),
+                &self._0p1a_cnt_target1_reach_1_hp(),
             )
             .field(
                 "_0p2a_cnt_target0_reach_0_hp",
-                &format_args!("{}", self._0p2a_cnt_target0_reach_0_hp().bit()),
+                &self._0p2a_cnt_target0_reach_0_hp(),
             )
             .field(
                 "_0p2a_cnt_target1_reach_0_hp",
-                &format_args!("{}", self._0p2a_cnt_target1_reach_0_hp().bit()),
+                &self._0p2a_cnt_target1_reach_0_hp(),
             )
             .field(
                 "_0p2a_cnt_target0_reach_1_hp",
-                &format_args!("{}", self._0p2a_cnt_target0_reach_1_hp().bit()),
+                &self._0p2a_cnt_target0_reach_1_hp(),
             )
             .field(
                 "_0p2a_cnt_target1_reach_1_hp",
-                &format_args!("{}", self._0p2a_cnt_target1_reach_1_hp().bit()),
+                &self._0p2a_cnt_target1_reach_1_hp(),
             )
             .field(
                 "_0p3a_cnt_target0_reach_0_hp",
-                &format_args!("{}", self._0p3a_cnt_target0_reach_0_hp().bit()),
+                &self._0p3a_cnt_target0_reach_0_hp(),
             )
             .field(
                 "_0p3a_cnt_target1_reach_0_hp",
-                &format_args!("{}", self._0p3a_cnt_target1_reach_0_hp().bit()),
+                &self._0p3a_cnt_target1_reach_0_hp(),
             )
             .field(
                 "_0p3a_cnt_target0_reach_1_hp",
-                &format_args!("{}", self._0p3a_cnt_target0_reach_1_hp().bit()),
+                &self._0p3a_cnt_target0_reach_1_hp(),
             )
             .field(
                 "_0p3a_cnt_target1_reach_1_hp",
-                &format_args!("{}", self._0p3a_cnt_target1_reach_1_hp().bit()),
+                &self._0p3a_cnt_target1_reach_1_hp(),
             )
-            .field("lp_cpu_exc", &format_args!("{}", self.lp_cpu_exc().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("sw", &format_args!("{}", self.sw().bit()))
-            .field(
-                "soc_sleep_reject",
-                &format_args!("{}", self.soc_sleep_reject().bit()),
-            )
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("lp_cpu_exc", &self.lp_cpu_exc())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("sw", &self.sw())
+            .field("soc_sleep_reject", &self.soc_sleep_reject())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 14 - reg_0p1a_0_counter after xpd reach target0"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/int_raw.rs b/esp32p4/src/pmu/int_raw.rs
index a096239590..36c2938f92 100644
--- a/esp32p4/src/pmu/int_raw.rs
+++ b/esp32p4/src/pmu/int_raw.rs
@@ -163,69 +163,60 @@ impl core::fmt::Debug for R {
         f.debug_struct("INT_RAW")
             .field(
                 "_0p1a_cnt_target0_reach_0_hp",
-                &format_args!("{}", self._0p1a_cnt_target0_reach_0_hp().bit()),
+                &self._0p1a_cnt_target0_reach_0_hp(),
             )
             .field(
                 "_0p1a_cnt_target1_reach_0_hp",
-                &format_args!("{}", self._0p1a_cnt_target1_reach_0_hp().bit()),
+                &self._0p1a_cnt_target1_reach_0_hp(),
             )
             .field(
                 "_0p1a_cnt_target0_reach_1_hp",
-                &format_args!("{}", self._0p1a_cnt_target0_reach_1_hp().bit()),
+                &self._0p1a_cnt_target0_reach_1_hp(),
             )
             .field(
                 "_0p1a_cnt_target1_reach_1_hp",
-                &format_args!("{}", self._0p1a_cnt_target1_reach_1_hp().bit()),
+                &self._0p1a_cnt_target1_reach_1_hp(),
             )
             .field(
                 "_0p2a_cnt_target0_reach_0_hp",
-                &format_args!("{}", self._0p2a_cnt_target0_reach_0_hp().bit()),
+                &self._0p2a_cnt_target0_reach_0_hp(),
             )
             .field(
                 "_0p2a_cnt_target1_reach_0_hp",
-                &format_args!("{}", self._0p2a_cnt_target1_reach_0_hp().bit()),
+                &self._0p2a_cnt_target1_reach_0_hp(),
             )
             .field(
                 "_0p2a_cnt_target0_reach_1_hp",
-                &format_args!("{}", self._0p2a_cnt_target0_reach_1_hp().bit()),
+                &self._0p2a_cnt_target0_reach_1_hp(),
             )
             .field(
                 "_0p2a_cnt_target1_reach_1_hp",
-                &format_args!("{}", self._0p2a_cnt_target1_reach_1_hp().bit()),
+                &self._0p2a_cnt_target1_reach_1_hp(),
             )
             .field(
                 "_0p3a_cnt_target0_reach_0_hp",
-                &format_args!("{}", self._0p3a_cnt_target0_reach_0_hp().bit()),
+                &self._0p3a_cnt_target0_reach_0_hp(),
             )
             .field(
                 "_0p3a_cnt_target1_reach_0_hp",
-                &format_args!("{}", self._0p3a_cnt_target1_reach_0_hp().bit()),
+                &self._0p3a_cnt_target1_reach_0_hp(),
             )
             .field(
                 "_0p3a_cnt_target0_reach_1_hp",
-                &format_args!("{}", self._0p3a_cnt_target0_reach_1_hp().bit()),
+                &self._0p3a_cnt_target0_reach_1_hp(),
             )
             .field(
                 "_0p3a_cnt_target1_reach_1_hp",
-                &format_args!("{}", self._0p3a_cnt_target1_reach_1_hp().bit()),
+                &self._0p3a_cnt_target1_reach_1_hp(),
             )
-            .field("lp_cpu_exc", &format_args!("{}", self.lp_cpu_exc().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("sw", &format_args!("{}", self.sw().bit()))
-            .field(
-                "soc_sleep_reject",
-                &format_args!("{}", self.soc_sleep_reject().bit()),
-            )
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("lp_cpu_exc", &self.lp_cpu_exc())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("sw", &self.sw())
+            .field("soc_sleep_reject", &self.soc_sleep_reject())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 14 - reg_0p1a_0_counter after xpd reach target0"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/int_st.rs b/esp32p4/src/pmu/int_st.rs
index 93d74d8e6e..331acf4e4e 100644
--- a/esp32p4/src/pmu/int_st.rs
+++ b/esp32p4/src/pmu/int_st.rs
@@ -127,69 +127,60 @@ impl core::fmt::Debug for R {
         f.debug_struct("INT_ST")
             .field(
                 "_0p1a_cnt_target0_reach_0_hp",
-                &format_args!("{}", self._0p1a_cnt_target0_reach_0_hp().bit()),
+                &self._0p1a_cnt_target0_reach_0_hp(),
             )
             .field(
                 "_0p1a_cnt_target1_reach_0_hp",
-                &format_args!("{}", self._0p1a_cnt_target1_reach_0_hp().bit()),
+                &self._0p1a_cnt_target1_reach_0_hp(),
             )
             .field(
                 "_0p1a_cnt_target0_reach_1_hp",
-                &format_args!("{}", self._0p1a_cnt_target0_reach_1_hp().bit()),
+                &self._0p1a_cnt_target0_reach_1_hp(),
             )
             .field(
                 "_0p1a_cnt_target1_reach_1_hp",
-                &format_args!("{}", self._0p1a_cnt_target1_reach_1_hp().bit()),
+                &self._0p1a_cnt_target1_reach_1_hp(),
             )
             .field(
                 "_0p2a_cnt_target0_reach_0_hp",
-                &format_args!("{}", self._0p2a_cnt_target0_reach_0_hp().bit()),
+                &self._0p2a_cnt_target0_reach_0_hp(),
             )
             .field(
                 "_0p2a_cnt_target1_reach_0_hp",
-                &format_args!("{}", self._0p2a_cnt_target1_reach_0_hp().bit()),
+                &self._0p2a_cnt_target1_reach_0_hp(),
             )
             .field(
                 "_0p2a_cnt_target0_reach_1_hp",
-                &format_args!("{}", self._0p2a_cnt_target0_reach_1_hp().bit()),
+                &self._0p2a_cnt_target0_reach_1_hp(),
             )
             .field(
                 "_0p2a_cnt_target1_reach_1_hp",
-                &format_args!("{}", self._0p2a_cnt_target1_reach_1_hp().bit()),
+                &self._0p2a_cnt_target1_reach_1_hp(),
             )
             .field(
                 "_0p3a_cnt_target0_reach_0_hp",
-                &format_args!("{}", self._0p3a_cnt_target0_reach_0_hp().bit()),
+                &self._0p3a_cnt_target0_reach_0_hp(),
             )
             .field(
                 "_0p3a_cnt_target1_reach_0_hp",
-                &format_args!("{}", self._0p3a_cnt_target1_reach_0_hp().bit()),
+                &self._0p3a_cnt_target1_reach_0_hp(),
             )
             .field(
                 "_0p3a_cnt_target0_reach_1_hp",
-                &format_args!("{}", self._0p3a_cnt_target0_reach_1_hp().bit()),
+                &self._0p3a_cnt_target0_reach_1_hp(),
             )
             .field(
                 "_0p3a_cnt_target1_reach_1_hp",
-                &format_args!("{}", self._0p3a_cnt_target1_reach_1_hp().bit()),
+                &self._0p3a_cnt_target1_reach_1_hp(),
             )
-            .field("lp_cpu_exc", &format_args!("{}", self.lp_cpu_exc().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("sw", &format_args!("{}", self.sw().bit()))
-            .field(
-                "soc_sleep_reject",
-                &format_args!("{}", self.soc_sleep_reject().bit()),
-            )
-            .field("soc_wakeup", &format_args!("{}", self.soc_wakeup().bit()))
+            .field("lp_cpu_exc", &self.lp_cpu_exc())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("sw", &self.sw())
+            .field("soc_sleep_reject", &self.soc_sleep_reject())
+            .field("soc_wakeup", &self.soc_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/pmu/lp_cpu_pwr0.rs b/esp32p4/src/pmu/lp_cpu_pwr0.rs
index 7147a7513f..0d670be9e5 100644
--- a/esp32p4/src/pmu/lp_cpu_pwr0.rs
+++ b/esp32p4/src/pmu/lp_cpu_pwr0.rs
@@ -85,51 +85,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CPU_PWR0")
-            .field(
-                "lp_cpu_waiti_rdy",
-                &format_args!("{}", self.lp_cpu_waiti_rdy().bit()),
-            )
-            .field(
-                "lp_cpu_stall_rdy",
-                &format_args!("{}", self.lp_cpu_stall_rdy().bit()),
-            )
-            .field(
-                "lp_cpu_force_stall",
-                &format_args!("{}", self.lp_cpu_force_stall().bit()),
-            )
-            .field(
-                "lp_cpu_slp_waiti_flag_en",
-                &format_args!("{}", self.lp_cpu_slp_waiti_flag_en().bit()),
-            )
-            .field(
-                "lp_cpu_slp_stall_flag_en",
-                &format_args!("{}", self.lp_cpu_slp_stall_flag_en().bit()),
-            )
-            .field(
-                "lp_cpu_slp_stall_wait",
-                &format_args!("{}", self.lp_cpu_slp_stall_wait().bits()),
-            )
-            .field(
-                "lp_cpu_slp_stall_en",
-                &format_args!("{}", self.lp_cpu_slp_stall_en().bit()),
-            )
-            .field(
-                "lp_cpu_slp_reset_en",
-                &format_args!("{}", self.lp_cpu_slp_reset_en().bit()),
-            )
+            .field("lp_cpu_waiti_rdy", &self.lp_cpu_waiti_rdy())
+            .field("lp_cpu_stall_rdy", &self.lp_cpu_stall_rdy())
+            .field("lp_cpu_force_stall", &self.lp_cpu_force_stall())
+            .field("lp_cpu_slp_waiti_flag_en", &self.lp_cpu_slp_waiti_flag_en())
+            .field("lp_cpu_slp_stall_flag_en", &self.lp_cpu_slp_stall_flag_en())
+            .field("lp_cpu_slp_stall_wait", &self.lp_cpu_slp_stall_wait())
+            .field("lp_cpu_slp_stall_en", &self.lp_cpu_slp_stall_en())
+            .field("lp_cpu_slp_reset_en", &self.lp_cpu_slp_reset_en())
             .field(
                 "lp_cpu_slp_bypass_intr_en",
-                &format_args!("{}", self.lp_cpu_slp_bypass_intr_en().bit()),
+                &self.lp_cpu_slp_bypass_intr_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CPU_PWR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/lp_cpu_pwr2.rs b/esp32p4/src/pmu/lp_cpu_pwr2.rs
index 237093e0de..9bd8182d61 100644
--- a/esp32p4/src/pmu/lp_cpu_pwr2.rs
+++ b/esp32p4/src/pmu/lp_cpu_pwr2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CPU_PWR2")
-            .field(
-                "lp_cpu_wakeup_en",
-                &format_args!("{}", self.lp_cpu_wakeup_en().bits()),
-            )
+            .field("lp_cpu_wakeup_en", &self.lp_cpu_wakeup_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CPU_PWR2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/lp_cpu_pwr3.rs b/esp32p4/src/pmu/lp_cpu_pwr3.rs
index 43b4ab6f30..31635fe771 100644
--- a/esp32p4/src/pmu/lp_cpu_pwr3.rs
+++ b/esp32p4/src/pmu/lp_cpu_pwr3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CPU_PWR3")
-            .field(
-                "lp_cpu_wakeup_cause",
-                &format_args!("{}", self.lp_cpu_wakeup_cause().bits()),
-            )
+            .field("lp_cpu_wakeup_cause", &self.lp_cpu_wakeup_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CPU_PWR3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_pwr3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_CPU_PWR3_SPEC;
 impl crate::RegisterSpec for LP_CPU_PWR3_SPEC {
diff --git a/esp32p4/src/pmu/lp_cpu_pwr4.rs b/esp32p4/src/pmu/lp_cpu_pwr4.rs
index e4b07ab389..0139cbe2c2 100644
--- a/esp32p4/src/pmu/lp_cpu_pwr4.rs
+++ b/esp32p4/src/pmu/lp_cpu_pwr4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CPU_PWR4")
-            .field(
-                "lp_cpu_reject_en",
-                &format_args!("{}", self.lp_cpu_reject_en().bits()),
-            )
+            .field("lp_cpu_reject_en", &self.lp_cpu_reject_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CPU_PWR4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/lp_cpu_pwr5.rs b/esp32p4/src/pmu/lp_cpu_pwr5.rs
index dddb20a951..9ded6b61b6 100644
--- a/esp32p4/src/pmu/lp_cpu_pwr5.rs
+++ b/esp32p4/src/pmu/lp_cpu_pwr5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_CPU_PWR5")
-            .field(
-                "lp_cpu_reject_cause",
-                &format_args!("{}", self.lp_cpu_reject_cause().bits()),
-            )
+            .field("lp_cpu_reject_cause", &self.lp_cpu_reject_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_CPU_PWR5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_cpu_pwr5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_CPU_PWR5_SPEC;
 impl crate::RegisterSpec for LP_CPU_PWR5_SPEC {
diff --git a/esp32p4/src/pmu/lp_int_ena.rs b/esp32p4/src/pmu/lp_int_ena.rs
index f8a7d27a95..6eeb0643c5 100644
--- a/esp32p4/src/pmu/lp_int_ena.rs
+++ b/esp32p4/src/pmu/lp_int_ena.rs
@@ -179,91 +179,70 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ENA")
-            .field(
-                "lp_cpu_sleep_reject",
-                &format_args!("{}", self.lp_cpu_sleep_reject().bit()),
-            )
+            .field("lp_cpu_sleep_reject", &self.lp_cpu_sleep_reject())
             .field(
                 "_0p1a_cnt_target0_reach_0_lp",
-                &format_args!("{}", self._0p1a_cnt_target0_reach_0_lp().bit()),
+                &self._0p1a_cnt_target0_reach_0_lp(),
             )
             .field(
                 "_0p1a_cnt_target1_reach_0_lp",
-                &format_args!("{}", self._0p1a_cnt_target1_reach_0_lp().bit()),
+                &self._0p1a_cnt_target1_reach_0_lp(),
             )
             .field(
                 "_0p1a_cnt_target0_reach_1_lp",
-                &format_args!("{}", self._0p1a_cnt_target0_reach_1_lp().bit()),
+                &self._0p1a_cnt_target0_reach_1_lp(),
             )
             .field(
                 "_0p1a_cnt_target1_reach_1_lp",
-                &format_args!("{}", self._0p1a_cnt_target1_reach_1_lp().bit()),
+                &self._0p1a_cnt_target1_reach_1_lp(),
             )
             .field(
                 "_0p2a_cnt_target0_reach_0_lp",
-                &format_args!("{}", self._0p2a_cnt_target0_reach_0_lp().bit()),
+                &self._0p2a_cnt_target0_reach_0_lp(),
             )
             .field(
                 "_0p2a_cnt_target1_reach_0_lp",
-                &format_args!("{}", self._0p2a_cnt_target1_reach_0_lp().bit()),
+                &self._0p2a_cnt_target1_reach_0_lp(),
             )
             .field(
                 "_0p2a_cnt_target0_reach_1_lp",
-                &format_args!("{}", self._0p2a_cnt_target0_reach_1_lp().bit()),
+                &self._0p2a_cnt_target0_reach_1_lp(),
             )
             .field(
                 "_0p2a_cnt_target1_reach_1_lp",
-                &format_args!("{}", self._0p2a_cnt_target1_reach_1_lp().bit()),
+                &self._0p2a_cnt_target1_reach_1_lp(),
             )
             .field(
                 "_0p3a_cnt_target0_reach_0_lp",
-                &format_args!("{}", self._0p3a_cnt_target0_reach_0_lp().bit()),
+                &self._0p3a_cnt_target0_reach_0_lp(),
             )
             .field(
                 "_0p3a_cnt_target1_reach_0_lp",
-                &format_args!("{}", self._0p3a_cnt_target1_reach_0_lp().bit()),
+                &self._0p3a_cnt_target1_reach_0_lp(),
             )
             .field(
                 "_0p3a_cnt_target0_reach_1_lp",
-                &format_args!("{}", self._0p3a_cnt_target0_reach_1_lp().bit()),
+                &self._0p3a_cnt_target0_reach_1_lp(),
             )
             .field(
                 "_0p3a_cnt_target1_reach_1_lp",
-                &format_args!("{}", self._0p3a_cnt_target1_reach_1_lp().bit()),
-            )
-            .field(
-                "lp_cpu_wakeup",
-                &format_args!("{}", self.lp_cpu_wakeup().bit()),
-            )
-            .field(
-                "sleep_switch_active_end",
-                &format_args!("{}", self.sleep_switch_active_end().bit()),
-            )
-            .field(
-                "active_switch_sleep_end",
-                &format_args!("{}", self.active_switch_sleep_end().bit()),
+                &self._0p3a_cnt_target1_reach_1_lp(),
             )
+            .field("lp_cpu_wakeup", &self.lp_cpu_wakeup())
+            .field("sleep_switch_active_end", &self.sleep_switch_active_end())
+            .field("active_switch_sleep_end", &self.active_switch_sleep_end())
             .field(
                 "sleep_switch_active_start",
-                &format_args!("{}", self.sleep_switch_active_start().bit()),
+                &self.sleep_switch_active_start(),
             )
             .field(
                 "active_switch_sleep_start",
-                &format_args!("{}", self.active_switch_sleep_start().bit()),
-            )
-            .field(
-                "hp_sw_trigger",
-                &format_args!("{}", self.hp_sw_trigger().bit()),
+                &self.active_switch_sleep_start(),
             )
+            .field("hp_sw_trigger", &self.hp_sw_trigger())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/lp_int_raw.rs b/esp32p4/src/pmu/lp_int_raw.rs
index cd69b6f4da..976f509b86 100644
--- a/esp32p4/src/pmu/lp_int_raw.rs
+++ b/esp32p4/src/pmu/lp_int_raw.rs
@@ -179,91 +179,70 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_RAW")
-            .field(
-                "lp_cpu_sleep_reject",
-                &format_args!("{}", self.lp_cpu_sleep_reject().bit()),
-            )
+            .field("lp_cpu_sleep_reject", &self.lp_cpu_sleep_reject())
             .field(
                 "_0p1a_cnt_target0_reach_0_lp",
-                &format_args!("{}", self._0p1a_cnt_target0_reach_0_lp().bit()),
+                &self._0p1a_cnt_target0_reach_0_lp(),
             )
             .field(
                 "_0p1a_cnt_target1_reach_0_lp",
-                &format_args!("{}", self._0p1a_cnt_target1_reach_0_lp().bit()),
+                &self._0p1a_cnt_target1_reach_0_lp(),
             )
             .field(
                 "_0p1a_cnt_target0_reach_1_lp",
-                &format_args!("{}", self._0p1a_cnt_target0_reach_1_lp().bit()),
+                &self._0p1a_cnt_target0_reach_1_lp(),
             )
             .field(
                 "_0p1a_cnt_target1_reach_1_lp",
-                &format_args!("{}", self._0p1a_cnt_target1_reach_1_lp().bit()),
+                &self._0p1a_cnt_target1_reach_1_lp(),
             )
             .field(
                 "_0p2a_cnt_target0_reach_0_lp",
-                &format_args!("{}", self._0p2a_cnt_target0_reach_0_lp().bit()),
+                &self._0p2a_cnt_target0_reach_0_lp(),
             )
             .field(
                 "_0p2a_cnt_target1_reach_0_lp",
-                &format_args!("{}", self._0p2a_cnt_target1_reach_0_lp().bit()),
+                &self._0p2a_cnt_target1_reach_0_lp(),
             )
             .field(
                 "_0p2a_cnt_target0_reach_1_lp",
-                &format_args!("{}", self._0p2a_cnt_target0_reach_1_lp().bit()),
+                &self._0p2a_cnt_target0_reach_1_lp(),
             )
             .field(
                 "_0p2a_cnt_target1_reach_1_lp",
-                &format_args!("{}", self._0p2a_cnt_target1_reach_1_lp().bit()),
+                &self._0p2a_cnt_target1_reach_1_lp(),
             )
             .field(
                 "_0p3a_cnt_target0_reach_0_lp",
-                &format_args!("{}", self._0p3a_cnt_target0_reach_0_lp().bit()),
+                &self._0p3a_cnt_target0_reach_0_lp(),
             )
             .field(
                 "_0p3a_cnt_target1_reach_0_lp",
-                &format_args!("{}", self._0p3a_cnt_target1_reach_0_lp().bit()),
+                &self._0p3a_cnt_target1_reach_0_lp(),
             )
             .field(
                 "_0p3a_cnt_target0_reach_1_lp",
-                &format_args!("{}", self._0p3a_cnt_target0_reach_1_lp().bit()),
+                &self._0p3a_cnt_target0_reach_1_lp(),
             )
             .field(
                 "_0p3a_cnt_target1_reach_1_lp",
-                &format_args!("{}", self._0p3a_cnt_target1_reach_1_lp().bit()),
-            )
-            .field(
-                "lp_cpu_wakeup",
-                &format_args!("{}", self.lp_cpu_wakeup().bit()),
-            )
-            .field(
-                "sleep_switch_active_end",
-                &format_args!("{}", self.sleep_switch_active_end().bit()),
-            )
-            .field(
-                "active_switch_sleep_end",
-                &format_args!("{}", self.active_switch_sleep_end().bit()),
+                &self._0p3a_cnt_target1_reach_1_lp(),
             )
+            .field("lp_cpu_wakeup", &self.lp_cpu_wakeup())
+            .field("sleep_switch_active_end", &self.sleep_switch_active_end())
+            .field("active_switch_sleep_end", &self.active_switch_sleep_end())
             .field(
                 "sleep_switch_active_start",
-                &format_args!("{}", self.sleep_switch_active_start().bit()),
+                &self.sleep_switch_active_start(),
             )
             .field(
                 "active_switch_sleep_start",
-                &format_args!("{}", self.active_switch_sleep_start().bit()),
-            )
-            .field(
-                "hp_sw_trigger",
-                &format_args!("{}", self.hp_sw_trigger().bit()),
+                &self.active_switch_sleep_start(),
             )
+            .field("hp_sw_trigger", &self.hp_sw_trigger())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/lp_int_st.rs b/esp32p4/src/pmu/lp_int_st.rs
index 9d086cb6ef..4fd20bc1ea 100644
--- a/esp32p4/src/pmu/lp_int_st.rs
+++ b/esp32p4/src/pmu/lp_int_st.rs
@@ -139,91 +139,70 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_INT_ST")
-            .field(
-                "lp_cpu_sleep_reject",
-                &format_args!("{}", self.lp_cpu_sleep_reject().bit()),
-            )
+            .field("lp_cpu_sleep_reject", &self.lp_cpu_sleep_reject())
             .field(
                 "_0p1a_cnt_target0_reach_0_lp",
-                &format_args!("{}", self._0p1a_cnt_target0_reach_0_lp().bit()),
+                &self._0p1a_cnt_target0_reach_0_lp(),
             )
             .field(
                 "_0p1a_cnt_target1_reach_0_lp",
-                &format_args!("{}", self._0p1a_cnt_target1_reach_0_lp().bit()),
+                &self._0p1a_cnt_target1_reach_0_lp(),
             )
             .field(
                 "_0p1a_cnt_target0_reach_1_lp",
-                &format_args!("{}", self._0p1a_cnt_target0_reach_1_lp().bit()),
+                &self._0p1a_cnt_target0_reach_1_lp(),
             )
             .field(
                 "_0p1a_cnt_target1_reach_1_lp",
-                &format_args!("{}", self._0p1a_cnt_target1_reach_1_lp().bit()),
+                &self._0p1a_cnt_target1_reach_1_lp(),
             )
             .field(
                 "_0p2a_cnt_target0_reach_0_lp",
-                &format_args!("{}", self._0p2a_cnt_target0_reach_0_lp().bit()),
+                &self._0p2a_cnt_target0_reach_0_lp(),
             )
             .field(
                 "_0p2a_cnt_target1_reach_0_lp",
-                &format_args!("{}", self._0p2a_cnt_target1_reach_0_lp().bit()),
+                &self._0p2a_cnt_target1_reach_0_lp(),
             )
             .field(
                 "_0p2a_cnt_target0_reach_1_lp",
-                &format_args!("{}", self._0p2a_cnt_target0_reach_1_lp().bit()),
+                &self._0p2a_cnt_target0_reach_1_lp(),
             )
             .field(
                 "_0p2a_cnt_target1_reach_1_lp",
-                &format_args!("{}", self._0p2a_cnt_target1_reach_1_lp().bit()),
+                &self._0p2a_cnt_target1_reach_1_lp(),
             )
             .field(
                 "_0p3a_cnt_target0_reach_0_lp",
-                &format_args!("{}", self._0p3a_cnt_target0_reach_0_lp().bit()),
+                &self._0p3a_cnt_target0_reach_0_lp(),
             )
             .field(
                 "_0p3a_cnt_target1_reach_0_lp",
-                &format_args!("{}", self._0p3a_cnt_target1_reach_0_lp().bit()),
+                &self._0p3a_cnt_target1_reach_0_lp(),
             )
             .field(
                 "_0p3a_cnt_target0_reach_1_lp",
-                &format_args!("{}", self._0p3a_cnt_target0_reach_1_lp().bit()),
+                &self._0p3a_cnt_target0_reach_1_lp(),
             )
             .field(
                 "_0p3a_cnt_target1_reach_1_lp",
-                &format_args!("{}", self._0p3a_cnt_target1_reach_1_lp().bit()),
-            )
-            .field(
-                "lp_cpu_wakeup",
-                &format_args!("{}", self.lp_cpu_wakeup().bit()),
-            )
-            .field(
-                "sleep_switch_active_end",
-                &format_args!("{}", self.sleep_switch_active_end().bit()),
-            )
-            .field(
-                "active_switch_sleep_end",
-                &format_args!("{}", self.active_switch_sleep_end().bit()),
+                &self._0p3a_cnt_target1_reach_1_lp(),
             )
+            .field("lp_cpu_wakeup", &self.lp_cpu_wakeup())
+            .field("sleep_switch_active_end", &self.sleep_switch_active_end())
+            .field("active_switch_sleep_end", &self.active_switch_sleep_end())
             .field(
                 "sleep_switch_active_start",
-                &format_args!("{}", self.sleep_switch_active_start().bit()),
+                &self.sleep_switch_active_start(),
             )
             .field(
                 "active_switch_sleep_start",
-                &format_args!("{}", self.active_switch_sleep_start().bit()),
-            )
-            .field(
-                "hp_sw_trigger",
-                &format_args!("{}", self.hp_sw_trigger().bit()),
+                &self.active_switch_sleep_start(),
             )
+            .field("hp_sw_trigger", &self.hp_sw_trigger())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LP_INT_ST_SPEC;
 impl crate::RegisterSpec for LP_INT_ST_SPEC {
diff --git a/esp32p4/src/pmu/lp_sleep_bias.rs b/esp32p4/src/pmu/lp_sleep_bias.rs
index a5b438dea0..52b4077b44 100644
--- a/esp32p4/src/pmu/lp_sleep_bias.rs
+++ b/esp32p4/src/pmu/lp_sleep_bias.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SLEEP_BIAS")
-            .field(
-                "lp_sleep_xpd_bias",
-                &format_args!("{}", self.lp_sleep_xpd_bias().bit()),
-            )
-            .field(
-                "lp_sleep_dbg_atten",
-                &format_args!("{}", self.lp_sleep_dbg_atten().bits()),
-            )
-            .field(
-                "lp_sleep_pd_cur",
-                &format_args!("{}", self.lp_sleep_pd_cur().bit()),
-            )
-            .field("sleep", &format_args!("{}", self.sleep().bit()))
+            .field("lp_sleep_xpd_bias", &self.lp_sleep_xpd_bias())
+            .field("lp_sleep_dbg_atten", &self.lp_sleep_dbg_atten())
+            .field("lp_sleep_pd_cur", &self.lp_sleep_pd_cur())
+            .field("sleep", &self.sleep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_BIAS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/lp_sleep_lp_ck_power.rs b/esp32p4/src/pmu/lp_sleep_lp_ck_power.rs
index f91ac6d85b..f398b2de77 100644
--- a/esp32p4/src/pmu/lp_sleep_lp_ck_power.rs
+++ b/esp32p4/src/pmu/lp_sleep_lp_ck_power.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SLEEP_LP_CK_POWER")
-            .field(
-                "lp_sleep_xpd_lppll",
-                &format_args!("{}", self.lp_sleep_xpd_lppll().bit()),
-            )
-            .field(
-                "lp_sleep_xpd_xtal32k",
-                &format_args!("{}", self.lp_sleep_xpd_xtal32k().bit()),
-            )
-            .field(
-                "lp_sleep_xpd_rc32k",
-                &format_args!("{}", self.lp_sleep_xpd_rc32k().bit()),
-            )
-            .field(
-                "lp_sleep_xpd_fosc_clk",
-                &format_args!("{}", self.lp_sleep_xpd_fosc_clk().bit()),
-            )
-            .field(
-                "lp_sleep_pd_osc_clk",
-                &format_args!("{}", self.lp_sleep_pd_osc_clk().bit()),
-            )
+            .field("lp_sleep_xpd_lppll", &self.lp_sleep_xpd_lppll())
+            .field("lp_sleep_xpd_xtal32k", &self.lp_sleep_xpd_xtal32k())
+            .field("lp_sleep_xpd_rc32k", &self.lp_sleep_xpd_rc32k())
+            .field("lp_sleep_xpd_fosc_clk", &self.lp_sleep_xpd_fosc_clk())
+            .field("lp_sleep_pd_osc_clk", &self.lp_sleep_pd_osc_clk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_LP_CK_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/lp_sleep_lp_dig_power.rs b/esp32p4/src/pmu/lp_sleep_lp_dig_power.rs
index 15294cdd27..c452d03e7e 100644
--- a/esp32p4/src/pmu/lp_sleep_lp_dig_power.rs
+++ b/esp32p4/src/pmu/lp_sleep_lp_dig_power.rs
@@ -53,35 +53,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SLEEP_LP_DIG_POWER")
-            .field(
-                "lp_sleep_lp_pad_slp_sel",
-                &format_args!("{}", self.lp_sleep_lp_pad_slp_sel().bit()),
-            )
-            .field(
-                "lp_sleep_bod_source_sel",
-                &format_args!("{}", self.lp_sleep_bod_source_sel().bit()),
-            )
-            .field(
-                "lp_sleep_vddbat_mode",
-                &format_args!("{}", self.lp_sleep_vddbat_mode().bits()),
-            )
-            .field(
-                "lp_sleep_lp_mem_dslp",
-                &format_args!("{}", self.lp_sleep_lp_mem_dslp().bit()),
-            )
+            .field("lp_sleep_lp_pad_slp_sel", &self.lp_sleep_lp_pad_slp_sel())
+            .field("lp_sleep_bod_source_sel", &self.lp_sleep_bod_source_sel())
+            .field("lp_sleep_vddbat_mode", &self.lp_sleep_vddbat_mode())
+            .field("lp_sleep_lp_mem_dslp", &self.lp_sleep_lp_mem_dslp())
             .field(
                 "lp_sleep_pd_lp_peri_pd_en",
-                &format_args!("{}", self.lp_sleep_pd_lp_peri_pd_en().bit()),
+                &self.lp_sleep_pd_lp_peri_pd_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_LP_DIG_POWER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/lp_sleep_lp_regulator0.rs b/esp32p4/src/pmu/lp_sleep_lp_regulator0.rs
index 931f46ac78..3705814cf1 100644
--- a/esp32p4/src/pmu/lp_sleep_lp_regulator0.rs
+++ b/esp32p4/src/pmu/lp_sleep_lp_regulator0.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_SLEEP_LP_REGULATOR0")
             .field(
                 "lp_sleep_lp_regulator_slp_xpd",
-                &format_args!("{}", self.lp_sleep_lp_regulator_slp_xpd().bit()),
+                &self.lp_sleep_lp_regulator_slp_xpd(),
             )
             .field(
                 "lp_sleep_lp_regulator_xpd",
-                &format_args!("{}", self.lp_sleep_lp_regulator_xpd().bit()),
+                &self.lp_sleep_lp_regulator_xpd(),
             )
             .field(
                 "lp_sleep_lp_regulator_slp_dbias",
-                &format_args!("{}", self.lp_sleep_lp_regulator_slp_dbias().bits()),
+                &self.lp_sleep_lp_regulator_slp_dbias(),
             )
             .field(
                 "lp_sleep_lp_regulator_dbias",
-                &format_args!("{}", self.lp_sleep_lp_regulator_dbias().bits()),
+                &self.lp_sleep_lp_regulator_dbias(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_LP_REGULATOR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/lp_sleep_lp_regulator1.rs b/esp32p4/src/pmu/lp_sleep_lp_regulator1.rs
index 10b28a3965..93ccf313d0 100644
--- a/esp32p4/src/pmu/lp_sleep_lp_regulator1.rs
+++ b/esp32p4/src/pmu/lp_sleep_lp_regulator1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("LP_SLEEP_LP_REGULATOR1")
             .field(
                 "lp_sleep_lp_regulator_drv_b",
-                &format_args!("{}", self.lp_sleep_lp_regulator_drv_b().bits()),
+                &self.lp_sleep_lp_regulator_drv_b(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_LP_REGULATOR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 26:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/lp_sleep_xtal.rs b/esp32p4/src/pmu/lp_sleep_xtal.rs
index bae4466d7d..cc7e2ac036 100644
--- a/esp32p4/src/pmu/lp_sleep_xtal.rs
+++ b/esp32p4/src/pmu/lp_sleep_xtal.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LP_SLEEP_XTAL")
-            .field(
-                "lp_sleep_xpd_xtal",
-                &format_args!("{}", self.lp_sleep_xpd_xtal().bit()),
-            )
+            .field("lp_sleep_xpd_xtal", &self.lp_sleep_xpd_xtal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LP_SLEEP_XTAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/main_state.rs b/esp32p4/src/pmu/main_state.rs
index 68a26588f1..d531b09562 100644
--- a/esp32p4/src/pmu/main_state.rs
+++ b/esp32p4/src/pmu/main_state.rs
@@ -38,31 +38,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAIN_STATE")
-            .field(
-                "enable_cali_pmu_cntl",
-                &format_args!("{}", self.enable_cali_pmu_cntl().bit()),
-            )
-            .field(
-                "pmu_main_last_st_state",
-                &format_args!("{}", self.pmu_main_last_st_state().bits()),
-            )
-            .field(
-                "pmu_main_tar_st_state",
-                &format_args!("{}", self.pmu_main_tar_st_state().bits()),
-            )
-            .field(
-                "pmu_main_cur_st_state",
-                &format_args!("{}", self.pmu_main_cur_st_state().bits()),
-            )
+            .field("enable_cali_pmu_cntl", &self.enable_cali_pmu_cntl())
+            .field("pmu_main_last_st_state", &self.pmu_main_last_st_state())
+            .field("pmu_main_tar_st_state", &self.pmu_main_tar_st_state())
+            .field("pmu_main_cur_st_state", &self.pmu_main_cur_st_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAIN_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/por_status.rs b/esp32p4/src/pmu/por_status.rs
index eb68c0356d..1625236680 100644
--- a/esp32p4/src/pmu/por_status.rs
+++ b/esp32p4/src/pmu/por_status.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POR_STATUS")
-            .field("por_done", &format_args!("{}", self.por_done().bit()))
+            .field("por_done", &self.por_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POR_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`por_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct POR_STATUS_SPEC;
 impl crate::RegisterSpec for POR_STATUS_SPEC {
diff --git a/esp32p4/src/pmu/power_ck_wait_cntl.rs b/esp32p4/src/pmu/power_ck_wait_cntl.rs
index f021f02fda..40efb46ae9 100644
--- a/esp32p4/src/pmu/power_ck_wait_cntl.rs
+++ b/esp32p4/src/pmu/power_ck_wait_cntl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_CK_WAIT_CNTL")
-            .field(
-                "pmu_wait_xtl_stable",
-                &format_args!("{}", self.pmu_wait_xtl_stable().bits()),
-            )
-            .field(
-                "pmu_wait_pll_stable",
-                &format_args!("{}", self.pmu_wait_pll_stable().bits()),
-            )
+            .field("pmu_wait_xtl_stable", &self.pmu_wait_xtl_stable())
+            .field("pmu_wait_pll_stable", &self.pmu_wait_pll_stable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_CK_WAIT_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/power_dcdc_switch.rs b/esp32p4/src/pmu/power_dcdc_switch.rs
index 8f8d12db86..d83211c49c 100644
--- a/esp32p4/src/pmu/power_dcdc_switch.rs
+++ b/esp32p4/src/pmu/power_dcdc_switch.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_DCDC_SWITCH")
-            .field(
-                "force_dcdc_switch_pu",
-                &format_args!("{}", self.force_dcdc_switch_pu().bit()),
-            )
-            .field(
-                "force_dcdc_switch_pd",
-                &format_args!("{}", self.force_dcdc_switch_pd().bit()),
-            )
+            .field("force_dcdc_switch_pu", &self.force_dcdc_switch_pu())
+            .field("force_dcdc_switch_pd", &self.force_dcdc_switch_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_DCDC_SWITCH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/power_hp_pad.rs b/esp32p4/src/pmu/power_hp_pad.rs
index c28d331333..b339bbef5d 100644
--- a/esp32p4/src/pmu/power_hp_pad.rs
+++ b/esp32p4/src/pmu/power_hp_pad.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_HP_PAD")
-            .field(
-                "force_hp_pad_no_iso_all",
-                &format_args!("{}", self.force_hp_pad_no_iso_all().bit()),
-            )
-            .field(
-                "force_hp_pad_iso_all",
-                &format_args!("{}", self.force_hp_pad_iso_all().bit()),
-            )
+            .field("force_hp_pad_no_iso_all", &self.force_hp_pad_no_iso_all())
+            .field("force_hp_pad_iso_all", &self.force_hp_pad_iso_all())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_HP_PAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/power_pd_cnnt_cntl.rs b/esp32p4/src/pmu/power_pd_cnnt_cntl.rs
index e851fc3701..40eab26f85 100644
--- a/esp32p4/src/pmu/power_pd_cnnt_cntl.rs
+++ b/esp32p4/src/pmu/power_pd_cnnt_cntl.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_CNNT_CNTL")
-            .field(
-                "force_cnnt_reset",
-                &format_args!("{}", self.force_cnnt_reset().bit()),
-            )
-            .field(
-                "force_cnnt_iso",
-                &format_args!("{}", self.force_cnnt_iso().bit()),
-            )
-            .field(
-                "force_cnnt_pu",
-                &format_args!("{}", self.force_cnnt_pu().bit()),
-            )
-            .field(
-                "force_cnnt_no_reset",
-                &format_args!("{}", self.force_cnnt_no_reset().bit()),
-            )
-            .field(
-                "force_cnnt_no_iso",
-                &format_args!("{}", self.force_cnnt_no_iso().bit()),
-            )
-            .field(
-                "force_cnnt_pd",
-                &format_args!("{}", self.force_cnnt_pd().bit()),
-            )
+            .field("force_cnnt_reset", &self.force_cnnt_reset())
+            .field("force_cnnt_iso", &self.force_cnnt_iso())
+            .field("force_cnnt_pu", &self.force_cnnt_pu())
+            .field("force_cnnt_no_reset", &self.force_cnnt_no_reset())
+            .field("force_cnnt_no_iso", &self.force_cnnt_no_iso())
+            .field("force_cnnt_pd", &self.force_cnnt_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_CNNT_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/power_pd_cnnt_mask.rs b/esp32p4/src/pmu/power_pd_cnnt_mask.rs
index e36056c85b..4fc19e4d71 100644
--- a/esp32p4/src/pmu/power_pd_cnnt_mask.rs
+++ b/esp32p4/src/pmu/power_pd_cnnt_mask.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_CNNT_MASK")
-            .field(
-                "xpd_cnnt_mask",
-                &format_args!("{}", self.xpd_cnnt_mask().bits()),
-            )
-            .field(
-                "pd_cnnt_mask",
-                &format_args!("{}", self.pd_cnnt_mask().bits()),
-            )
+            .field("xpd_cnnt_mask", &self.xpd_cnnt_mask())
+            .field("pd_cnnt_mask", &self.pd_cnnt_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_CNNT_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/power_pd_hpmem_cntl.rs b/esp32p4/src/pmu/power_pd_hpmem_cntl.rs
index 34acce51cb..7f3c1b89d2 100644
--- a/esp32p4/src/pmu/power_pd_hpmem_cntl.rs
+++ b/esp32p4/src/pmu/power_pd_hpmem_cntl.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_HPMEM_CNTL")
-            .field(
-                "force_hp_mem_reset",
-                &format_args!("{}", self.force_hp_mem_reset().bit()),
-            )
-            .field(
-                "force_hp_mem_iso",
-                &format_args!("{}", self.force_hp_mem_iso().bit()),
-            )
-            .field(
-                "force_hp_mem_pu",
-                &format_args!("{}", self.force_hp_mem_pu().bit()),
-            )
-            .field(
-                "force_hp_mem_no_reset",
-                &format_args!("{}", self.force_hp_mem_no_reset().bit()),
-            )
-            .field(
-                "force_hp_mem_no_iso",
-                &format_args!("{}", self.force_hp_mem_no_iso().bit()),
-            )
-            .field(
-                "force_hp_mem_pd",
-                &format_args!("{}", self.force_hp_mem_pd().bit()),
-            )
+            .field("force_hp_mem_reset", &self.force_hp_mem_reset())
+            .field("force_hp_mem_iso", &self.force_hp_mem_iso())
+            .field("force_hp_mem_pu", &self.force_hp_mem_pu())
+            .field("force_hp_mem_no_reset", &self.force_hp_mem_no_reset())
+            .field("force_hp_mem_no_iso", &self.force_hp_mem_no_iso())
+            .field("force_hp_mem_pd", &self.force_hp_mem_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_HPMEM_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/power_pd_hpmem_mask.rs b/esp32p4/src/pmu/power_pd_hpmem_mask.rs
index eb6ccb4ab5..680c7d0a0e 100644
--- a/esp32p4/src/pmu/power_pd_hpmem_mask.rs
+++ b/esp32p4/src/pmu/power_pd_hpmem_mask.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_HPMEM_MASK")
-            .field(
-                "xpd_hp_mem_mask",
-                &format_args!("{}", self.xpd_hp_mem_mask().bits()),
-            )
-            .field(
-                "pd_hp_mem_mask",
-                &format_args!("{}", self.pd_hp_mem_mask().bits()),
-            )
+            .field("xpd_hp_mem_mask", &self.xpd_hp_mem_mask())
+            .field("pd_hp_mem_mask", &self.pd_hp_mem_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_HPMEM_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/power_pd_lpperi_cntl.rs b/esp32p4/src/pmu/power_pd_lpperi_cntl.rs
index 6f27fae0e2..f1a688639c 100644
--- a/esp32p4/src/pmu/power_pd_lpperi_cntl.rs
+++ b/esp32p4/src/pmu/power_pd_lpperi_cntl.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_LPPERI_CNTL")
-            .field(
-                "force_lp_peri_reset",
-                &format_args!("{}", self.force_lp_peri_reset().bit()),
-            )
-            .field(
-                "force_lp_peri_iso",
-                &format_args!("{}", self.force_lp_peri_iso().bit()),
-            )
-            .field(
-                "force_lp_peri_pu",
-                &format_args!("{}", self.force_lp_peri_pu().bit()),
-            )
-            .field(
-                "force_lp_peri_no_reset",
-                &format_args!("{}", self.force_lp_peri_no_reset().bit()),
-            )
-            .field(
-                "force_lp_peri_no_iso",
-                &format_args!("{}", self.force_lp_peri_no_iso().bit()),
-            )
-            .field(
-                "force_lp_peri_pd",
-                &format_args!("{}", self.force_lp_peri_pd().bit()),
-            )
+            .field("force_lp_peri_reset", &self.force_lp_peri_reset())
+            .field("force_lp_peri_iso", &self.force_lp_peri_iso())
+            .field("force_lp_peri_pu", &self.force_lp_peri_pu())
+            .field("force_lp_peri_no_reset", &self.force_lp_peri_no_reset())
+            .field("force_lp_peri_no_iso", &self.force_lp_peri_no_iso())
+            .field("force_lp_peri_pd", &self.force_lp_peri_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_LPPERI_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/power_pd_lpperi_mask.rs b/esp32p4/src/pmu/power_pd_lpperi_mask.rs
index b9bc5abd05..2508323a97 100644
--- a/esp32p4/src/pmu/power_pd_lpperi_mask.rs
+++ b/esp32p4/src/pmu/power_pd_lpperi_mask.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_LPPERI_MASK")
-            .field(
-                "xpd_lp_peri_mask",
-                &format_args!("{}", self.xpd_lp_peri_mask().bits()),
-            )
-            .field(
-                "pd_lp_peri_mask",
-                &format_args!("{}", self.pd_lp_peri_mask().bits()),
-            )
+            .field("xpd_lp_peri_mask", &self.xpd_lp_peri_mask())
+            .field("pd_lp_peri_mask", &self.pd_lp_peri_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_LPPERI_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/power_pd_top_cntl.rs b/esp32p4/src/pmu/power_pd_top_cntl.rs
index ed9dac03ab..62b3f01412 100644
--- a/esp32p4/src/pmu/power_pd_top_cntl.rs
+++ b/esp32p4/src/pmu/power_pd_top_cntl.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_TOP_CNTL")
-            .field(
-                "force_top_reset",
-                &format_args!("{}", self.force_top_reset().bit()),
-            )
-            .field(
-                "force_top_iso",
-                &format_args!("{}", self.force_top_iso().bit()),
-            )
-            .field(
-                "force_top_pu",
-                &format_args!("{}", self.force_top_pu().bit()),
-            )
-            .field(
-                "force_top_no_reset",
-                &format_args!("{}", self.force_top_no_reset().bit()),
-            )
-            .field(
-                "force_top_no_iso",
-                &format_args!("{}", self.force_top_no_iso().bit()),
-            )
-            .field(
-                "force_top_pd",
-                &format_args!("{}", self.force_top_pd().bit()),
-            )
+            .field("force_top_reset", &self.force_top_reset())
+            .field("force_top_iso", &self.force_top_iso())
+            .field("force_top_pu", &self.force_top_pu())
+            .field("force_top_no_reset", &self.force_top_no_reset())
+            .field("force_top_no_iso", &self.force_top_no_iso())
+            .field("force_top_pd", &self.force_top_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_TOP_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/power_pd_top_mask.rs b/esp32p4/src/pmu/power_pd_top_mask.rs
index ad7f045dac..1cafa63e09 100644
--- a/esp32p4/src/pmu/power_pd_top_mask.rs
+++ b/esp32p4/src/pmu/power_pd_top_mask.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_PD_TOP_MASK")
-            .field(
-                "xpd_top_mask",
-                &format_args!("{}", self.xpd_top_mask().bits()),
-            )
-            .field(
-                "pd_top_mask",
-                &format_args!("{}", self.pd_top_mask().bits()),
-            )
+            .field("xpd_top_mask", &self.xpd_top_mask())
+            .field("pd_top_mask", &self.pd_top_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_PD_TOP_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/power_wait_timer0.rs b/esp32p4/src/pmu/power_wait_timer0.rs
index 30802f3fd5..b3cf314033 100644
--- a/esp32p4/src/pmu/power_wait_timer0.rs
+++ b/esp32p4/src/pmu/power_wait_timer0.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_WAIT_TIMER0")
-            .field(
-                "dg_hp_powerdown_timer",
-                &format_args!("{}", self.dg_hp_powerdown_timer().bits()),
-            )
-            .field(
-                "dg_hp_powerup_timer",
-                &format_args!("{}", self.dg_hp_powerup_timer().bits()),
-            )
-            .field(
-                "dg_hp_wait_timer",
-                &format_args!("{}", self.dg_hp_wait_timer().bits()),
-            )
+            .field("dg_hp_powerdown_timer", &self.dg_hp_powerdown_timer())
+            .field("dg_hp_powerup_timer", &self.dg_hp_powerup_timer())
+            .field("dg_hp_wait_timer", &self.dg_hp_wait_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_WAIT_TIMER0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 5:13 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/power_wait_timer1.rs b/esp32p4/src/pmu/power_wait_timer1.rs
index fd70ae1aa1..3dff83cd67 100644
--- a/esp32p4/src/pmu/power_wait_timer1.rs
+++ b/esp32p4/src/pmu/power_wait_timer1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POWER_WAIT_TIMER1")
-            .field(
-                "dg_lp_powerdown_timer",
-                &format_args!("{}", self.dg_lp_powerdown_timer().bits()),
-            )
-            .field(
-                "dg_lp_powerup_timer",
-                &format_args!("{}", self.dg_lp_powerup_timer().bits()),
-            )
-            .field(
-                "dg_lp_wait_timer",
-                &format_args!("{}", self.dg_lp_wait_timer().bits()),
-            )
+            .field("dg_lp_powerdown_timer", &self.dg_lp_powerdown_timer())
+            .field("dg_lp_powerup_timer", &self.dg_lp_powerup_timer())
+            .field("dg_lp_wait_timer", &self.dg_lp_wait_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POWER_WAIT_TIMER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 5:13 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/pwr_state.rs b/esp32p4/src/pmu/pwr_state.rs
index 0be6c7c29c..6a3fcc5018 100644
--- a/esp32p4/src/pmu/pwr_state.rs
+++ b/esp32p4/src/pmu/pwr_state.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWR_STATE")
-            .field(
-                "pmu_backup_st_state",
-                &format_args!("{}", self.pmu_backup_st_state().bits()),
-            )
-            .field(
-                "pmu_lp_pwr_st_state",
-                &format_args!("{}", self.pmu_lp_pwr_st_state().bits()),
-            )
-            .field(
-                "pmu_hp_pwr_st_state",
-                &format_args!("{}", self.pmu_hp_pwr_st_state().bits()),
-            )
+            .field("pmu_backup_st_state", &self.pmu_backup_st_state())
+            .field("pmu_lp_pwr_st_state", &self.pmu_lp_pwr_st_state())
+            .field("pmu_hp_pwr_st_state", &self.pmu_hp_pwr_st_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWR_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwr_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PWR_STATE_SPEC;
 impl crate::RegisterSpec for PWR_STATE_SPEC {
diff --git a/esp32p4/src/pmu/rdn_eco.rs b/esp32p4/src/pmu/rdn_eco.rs
index fef2b72213..ad1e7b7662 100644
--- a/esp32p4/src/pmu/rdn_eco.rs
+++ b/esp32p4/src/pmu/rdn_eco.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RDN_ECO")
-            .field(
-                "pmu_rdn_eco_result",
-                &format_args!("{}", self.pmu_rdn_eco_result().bit()),
-            )
-            .field(
-                "pmu_rdn_eco_en",
-                &format_args!("{}", self.pmu_rdn_eco_en().bit()),
-            )
+            .field("pmu_rdn_eco_result", &self.pmu_rdn_eco_result())
+            .field("pmu_rdn_eco_en", &self.pmu_rdn_eco_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RDN_ECO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/rf_pwc.rs b/esp32p4/src/pmu/rf_pwc.rs
index 240ccb1552..a68d3225fc 100644
--- a/esp32p4/src/pmu/rf_pwc.rs
+++ b/esp32p4/src/pmu/rf_pwc.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RF_PWC")
-            .field(
-                "mspi_phy_xpd",
-                &format_args!("{}", self.mspi_phy_xpd().bit()),
-            )
-            .field(
-                "sdio_pll_xpd",
-                &format_args!("{}", self.sdio_pll_xpd().bit()),
-            )
-            .field(
-                "perif_i2c_rstb",
-                &format_args!("{}", self.perif_i2c_rstb().bit()),
-            )
-            .field(
-                "xpd_perif_i2c",
-                &format_args!("{}", self.xpd_perif_i2c().bit()),
-            )
-            .field(
-                "xpd_txrf_i2c",
-                &format_args!("{}", self.xpd_txrf_i2c().bit()),
-            )
-            .field(
-                "xpd_rfrx_pbus",
-                &format_args!("{}", self.xpd_rfrx_pbus().bit()),
-            )
-            .field(
-                "xpd_ckgen_i2c",
-                &format_args!("{}", self.xpd_ckgen_i2c().bit()),
-            )
+            .field("mspi_phy_xpd", &self.mspi_phy_xpd())
+            .field("sdio_pll_xpd", &self.sdio_pll_xpd())
+            .field("perif_i2c_rstb", &self.perif_i2c_rstb())
+            .field("xpd_perif_i2c", &self.xpd_perif_i2c())
+            .field("xpd_txrf_i2c", &self.xpd_txrf_i2c())
+            .field("xpd_rfrx_pbus", &self.xpd_rfrx_pbus())
+            .field("xpd_ckgen_i2c", &self.xpd_ckgen_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RF_PWC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/sdio_wakeup_cntl.rs b/esp32p4/src/pmu/sdio_wakeup_cntl.rs
index bba73f9986..c2d77c9baa 100644
--- a/esp32p4/src/pmu/sdio_wakeup_cntl.rs
+++ b/esp32p4/src/pmu/sdio_wakeup_cntl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_WAKEUP_CNTL")
-            .field(
-                "sdio_act_dnum",
-                &format_args!("{}", self.sdio_act_dnum().bits()),
-            )
+            .field("sdio_act_dnum", &self.sdio_act_dnum())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_WAKEUP_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/slp_wakeup_cntl1.rs b/esp32p4/src/pmu/slp_wakeup_cntl1.rs
index b5813a7699..0211531bff 100644
--- a/esp32p4/src/pmu/slp_wakeup_cntl1.rs
+++ b/esp32p4/src/pmu/slp_wakeup_cntl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL1")
-            .field(
-                "sleep_reject_ena",
-                &format_args!("{}", self.sleep_reject_ena().bits()),
-            )
-            .field(
-                "slp_reject_en",
-                &format_args!("{}", self.slp_reject_en().bit()),
-            )
+            .field("sleep_reject_ena", &self.sleep_reject_ena())
+            .field("slp_reject_en", &self.slp_reject_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/slp_wakeup_cntl2.rs b/esp32p4/src/pmu/slp_wakeup_cntl2.rs
index 4b2c159da5..b730ebb5d6 100644
--- a/esp32p4/src/pmu/slp_wakeup_cntl2.rs
+++ b/esp32p4/src/pmu/slp_wakeup_cntl2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL2")
-            .field("wakeup_ena", &format_args!("{}", self.wakeup_ena().bits()))
+            .field("wakeup_ena", &self.wakeup_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/slp_wakeup_cntl3.rs b/esp32p4/src/pmu/slp_wakeup_cntl3.rs
index b9fcfe21ca..dcde09eb3a 100644
--- a/esp32p4/src/pmu/slp_wakeup_cntl3.rs
+++ b/esp32p4/src/pmu/slp_wakeup_cntl3.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL3")
-            .field(
-                "lp_min_slp_val",
-                &format_args!("{}", self.lp_min_slp_val().bits()),
-            )
-            .field(
-                "hp_min_slp_val",
-                &format_args!("{}", self.hp_min_slp_val().bits()),
-            )
-            .field(
-                "sleep_prt_sel",
-                &format_args!("{}", self.sleep_prt_sel().bits()),
-            )
+            .field("lp_min_slp_val", &self.lp_min_slp_val())
+            .field("hp_min_slp_val", &self.hp_min_slp_val())
+            .field("sleep_prt_sel", &self.sleep_prt_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/slp_wakeup_cntl5.rs b/esp32p4/src/pmu/slp_wakeup_cntl5.rs
index 0073fbaa70..6022a5a3ee 100644
--- a/esp32p4/src/pmu/slp_wakeup_cntl5.rs
+++ b/esp32p4/src/pmu/slp_wakeup_cntl5.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL5")
-            .field(
-                "modem_wait_target",
-                &format_args!("{}", self.modem_wait_target().bits()),
-            )
-            .field(
-                "lp_ana_wait_target",
-                &format_args!("{}", self.lp_ana_wait_target().bits()),
-            )
+            .field("modem_wait_target", &self.modem_wait_target())
+            .field("lp_ana_wait_target", &self.lp_ana_wait_target())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/slp_wakeup_cntl6.rs b/esp32p4/src/pmu/slp_wakeup_cntl6.rs
index 30e86accf3..9aff65cbae 100644
--- a/esp32p4/src/pmu/slp_wakeup_cntl6.rs
+++ b/esp32p4/src/pmu/slp_wakeup_cntl6.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL6")
-            .field(
-                "soc_wakeup_wait",
-                &format_args!("{}", self.soc_wakeup_wait().bits()),
-            )
-            .field(
-                "soc_wakeup_wait_cfg",
-                &format_args!("{}", self.soc_wakeup_wait_cfg().bits()),
-            )
+            .field("soc_wakeup_wait", &self.soc_wakeup_wait())
+            .field("soc_wakeup_wait_cfg", &self.soc_wakeup_wait_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/slp_wakeup_cntl7.rs b/esp32p4/src/pmu/slp_wakeup_cntl7.rs
index 811e157fd8..ec649cb9a4 100644
--- a/esp32p4/src/pmu/slp_wakeup_cntl7.rs
+++ b/esp32p4/src/pmu/slp_wakeup_cntl7.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL7")
-            .field(
-                "ana_wait_target",
-                &format_args!("{}", self.ana_wait_target().bits()),
-            )
+            .field("ana_wait_target", &self.ana_wait_target())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/slp_wakeup_cntl8.rs b/esp32p4/src/pmu/slp_wakeup_cntl8.rs
index d50fae937f..dbcced2998 100644
--- a/esp32p4/src/pmu/slp_wakeup_cntl8.rs
+++ b/esp32p4/src/pmu/slp_wakeup_cntl8.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CNTL8")
-            .field(
-                "lp_lite_wakeup_ena",
-                &format_args!("{}", self.lp_lite_wakeup_ena().bit()),
-            )
+            .field("lp_lite_wakeup_ena", &self.lp_lite_wakeup_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CNTL8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/slp_wakeup_status0.rs b/esp32p4/src/pmu/slp_wakeup_status0.rs
index 43fdf4c1ea..7609c65414 100644
--- a/esp32p4/src/pmu/slp_wakeup_status0.rs
+++ b/esp32p4/src/pmu/slp_wakeup_status0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_STATUS0")
-            .field(
-                "wakeup_cause",
-                &format_args!("{}", self.wakeup_cause().bits()),
-            )
+            .field("wakeup_cause", &self.wakeup_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_STATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_status0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLP_WAKEUP_STATUS0_SPEC;
 impl crate::RegisterSpec for SLP_WAKEUP_STATUS0_SPEC {
diff --git a/esp32p4/src/pmu/slp_wakeup_status1.rs b/esp32p4/src/pmu/slp_wakeup_status1.rs
index f42b86130d..3f0a108ae0 100644
--- a/esp32p4/src/pmu/slp_wakeup_status1.rs
+++ b/esp32p4/src/pmu/slp_wakeup_status1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_STATUS1")
-            .field(
-                "reject_cause",
-                &format_args!("{}", self.reject_cause().bits()),
-            )
+            .field("reject_cause", &self.reject_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_status1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLP_WAKEUP_STATUS1_SPEC;
 impl crate::RegisterSpec for SLP_WAKEUP_STATUS1_SPEC {
diff --git a/esp32p4/src/pmu/slp_wakeup_status2.rs b/esp32p4/src/pmu/slp_wakeup_status2.rs
index b8de54d963..3888db556e 100644
--- a/esp32p4/src/pmu/slp_wakeup_status2.rs
+++ b/esp32p4/src/pmu/slp_wakeup_status2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_STATUS2")
-            .field(
-                "lp_lite_wakeup_cause",
-                &format_args!("{}", self.lp_lite_wakeup_cause().bit()),
-            )
+            .field("lp_lite_wakeup_cause", &self.lp_lite_wakeup_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_STATUS2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_status2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLP_WAKEUP_STATUS2_SPEC;
 impl crate::RegisterSpec for SLP_WAKEUP_STATUS2_SPEC {
diff --git a/esp32p4/src/pmu/touch_pwr_cntl.rs b/esp32p4/src/pmu/touch_pwr_cntl.rs
index e66c636d72..8862ec8fe8 100644
--- a/esp32p4/src/pmu/touch_pwr_cntl.rs
+++ b/esp32p4/src/pmu/touch_pwr_cntl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PWR_CNTL")
-            .field(
-                "touch_wait_cycles",
-                &format_args!("{}", self.touch_wait_cycles().bits()),
-            )
-            .field(
-                "touch_sleep_cycles",
-                &format_args!("{}", self.touch_sleep_cycles().bits()),
-            )
-            .field(
-                "touch_force_done",
-                &format_args!("{}", self.touch_force_done().bit()),
-            )
-            .field(
-                "touch_sleep_timer_en",
-                &format_args!("{}", self.touch_sleep_timer_en().bit()),
-            )
+            .field("touch_wait_cycles", &self.touch_wait_cycles())
+            .field("touch_sleep_cycles", &self.touch_sleep_cycles())
+            .field("touch_force_done", &self.touch_force_done())
+            .field("touch_sleep_timer_en", &self.touch_sleep_timer_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PWR_CNTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 5:13 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/vddbat_cfg.rs b/esp32p4/src/pmu/vddbat_cfg.rs
index 08bb312da3..687c0ca6f1 100644
--- a/esp32p4/src/pmu/vddbat_cfg.rs
+++ b/esp32p4/src/pmu/vddbat_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VDDBAT_CFG")
-            .field(
-                "ana_vddbat_mode",
-                &format_args!("{}", self.ana_vddbat_mode().bits()),
-            )
+            .field("ana_vddbat_mode", &self.ana_vddbat_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VDDBAT_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/pmu/xtal_slp.rs b/esp32p4/src/pmu/xtal_slp.rs
index 16a94a2b2a..114b8fb244 100644
--- a/esp32p4/src/pmu/xtal_slp.rs
+++ b/esp32p4/src/pmu/xtal_slp.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL_SLP")
-            .field("cnt_target", &format_args!("{}", self.cnt_target().bits()))
+            .field("cnt_target", &self.cnt_target())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL_SLP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - need_des"]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/blend0_clut_data.rs b/esp32p4/src/ppa/blend0_clut_data.rs
index bf12271d50..def1f77cda 100644
--- a/esp32p4/src/ppa/blend0_clut_data.rs
+++ b/esp32p4/src/ppa/blend0_clut_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLEND0_CLUT_DATA")
-            .field(
-                "rdwr_word_blend0_clut",
-                &format_args!("{}", self.rdwr_word_blend0_clut().bits()),
-            )
+            .field("rdwr_word_blend0_clut", &self.rdwr_word_blend0_clut())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLEND0_CLUT_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Write and read data to/from CLUT RAM in background plane of blender engine through this field in fifo mode."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/blend1_clut_data.rs b/esp32p4/src/ppa/blend1_clut_data.rs
index d8fa043457..ae59241958 100644
--- a/esp32p4/src/ppa/blend1_clut_data.rs
+++ b/esp32p4/src/ppa/blend1_clut_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLEND1_CLUT_DATA")
-            .field(
-                "rdwr_word_blend1_clut",
-                &format_args!("{}", self.rdwr_word_blend1_clut().bits()),
-            )
+            .field("rdwr_word_blend1_clut", &self.rdwr_word_blend1_clut())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLEND1_CLUT_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Write and read data to/from CLUT RAM in foreground plane of blender engine through this field in fifo mode."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/blend_byte_order.rs b/esp32p4/src/ppa/blend_byte_order.rs
index 8e133d1e50..d17c19661f 100644
--- a/esp32p4/src/ppa/blend_byte_order.rs
+++ b/esp32p4/src/ppa/blend_byte_order.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLEND_BYTE_ORDER")
-            .field(
-                "blend0_rx_byte_swap_en",
-                &format_args!("{}", self.blend0_rx_byte_swap_en().bit()),
-            )
-            .field(
-                "blend1_rx_byte_swap_en",
-                &format_args!("{}", self.blend1_rx_byte_swap_en().bit()),
-            )
-            .field(
-                "blend0_rx_rgb_swap_en",
-                &format_args!("{}", self.blend0_rx_rgb_swap_en().bit()),
-            )
-            .field(
-                "blend1_rx_rgb_swap_en",
-                &format_args!("{}", self.blend1_rx_rgb_swap_en().bit()),
-            )
+            .field("blend0_rx_byte_swap_en", &self.blend0_rx_byte_swap_en())
+            .field("blend1_rx_byte_swap_en", &self.blend1_rx_byte_swap_en())
+            .field("blend0_rx_rgb_swap_en", &self.blend0_rx_rgb_swap_en())
+            .field("blend1_rx_rgb_swap_en", &self.blend1_rx_rgb_swap_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLEND_BYTE_ORDER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/blend_color_mode.rs b/esp32p4/src/ppa/blend_color_mode.rs
index fcb1b970c8..ad3e8d961f 100644
--- a/esp32p4/src/ppa/blend_color_mode.rs
+++ b/esp32p4/src/ppa/blend_color_mode.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLEND_COLOR_MODE")
-            .field(
-                "blend0_rx_cm",
-                &format_args!("{}", self.blend0_rx_cm().bits()),
-            )
-            .field(
-                "blend1_rx_cm",
-                &format_args!("{}", self.blend1_rx_cm().bits()),
-            )
-            .field(
-                "blend_tx_cm",
-                &format_args!("{}", self.blend_tx_cm().bits()),
-            )
+            .field("blend0_rx_cm", &self.blend0_rx_cm())
+            .field("blend1_rx_cm", &self.blend1_rx_cm())
+            .field("blend_tx_cm", &self.blend_tx_cm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLEND_COLOR_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/blend_fix_alpha.rs b/esp32p4/src/ppa/blend_fix_alpha.rs
index b7cde531b0..f47d02e881 100644
--- a/esp32p4/src/ppa/blend_fix_alpha.rs
+++ b/esp32p4/src/ppa/blend_fix_alpha.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLEND_FIX_ALPHA")
-            .field(
-                "blend0_rx_fix_alpha",
-                &format_args!("{}", self.blend0_rx_fix_alpha().bits()),
-            )
-            .field(
-                "blend1_rx_fix_alpha",
-                &format_args!("{}", self.blend1_rx_fix_alpha().bits()),
-            )
-            .field(
-                "blend0_rx_alpha_mod",
-                &format_args!("{}", self.blend0_rx_alpha_mod().bits()),
-            )
-            .field(
-                "blend1_rx_alpha_mod",
-                &format_args!("{}", self.blend1_rx_alpha_mod().bits()),
-            )
-            .field(
-                "blend0_rx_alpha_inv",
-                &format_args!("{}", self.blend0_rx_alpha_inv().bit()),
-            )
-            .field(
-                "blend1_rx_alpha_inv",
-                &format_args!("{}", self.blend1_rx_alpha_inv().bit()),
-            )
+            .field("blend0_rx_fix_alpha", &self.blend0_rx_fix_alpha())
+            .field("blend1_rx_fix_alpha", &self.blend1_rx_fix_alpha())
+            .field("blend0_rx_alpha_mod", &self.blend0_rx_alpha_mod())
+            .field("blend1_rx_alpha_mod", &self.blend1_rx_alpha_mod())
+            .field("blend0_rx_alpha_inv", &self.blend0_rx_alpha_inv())
+            .field("blend1_rx_alpha_inv", &self.blend1_rx_alpha_inv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLEND_FIX_ALPHA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value would replace the alpha value in received pixel for background plane of blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/blend_fix_pixel.rs b/esp32p4/src/ppa/blend_fix_pixel.rs
index dba5f6e0d8..9135fab521 100644
--- a/esp32p4/src/ppa/blend_fix_pixel.rs
+++ b/esp32p4/src/ppa/blend_fix_pixel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLEND_FIX_PIXEL")
-            .field(
-                "blend_tx_fix_pixel",
-                &format_args!("{}", self.blend_tx_fix_pixel().bits()),
-            )
+            .field("blend_tx_fix_pixel", &self.blend_tx_fix_pixel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLEND_FIX_PIXEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The configure fix pixel in fix pixel filling mode for blender engine."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/blend_rgb.rs b/esp32p4/src/ppa/blend_rgb.rs
index 232788cadd..bfd8fb4c21 100644
--- a/esp32p4/src/ppa/blend_rgb.rs
+++ b/esp32p4/src/ppa/blend_rgb.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLEND_RGB")
-            .field(
-                "blend1_rx_b",
-                &format_args!("{}", self.blend1_rx_b().bits()),
-            )
-            .field(
-                "blend1_rx_g",
-                &format_args!("{}", self.blend1_rx_g().bits()),
-            )
-            .field(
-                "blend1_rx_r",
-                &format_args!("{}", self.blend1_rx_r().bits()),
-            )
+            .field("blend1_rx_b", &self.blend1_rx_b())
+            .field("blend1_rx_g", &self.blend1_rx_g())
+            .field("blend1_rx_r", &self.blend1_rx_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLEND_RGB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - blue color for A4/A8 mode."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/blend_st.rs b/esp32p4/src/ppa/blend_st.rs
index 77b1e52f67..2399722b8b 100644
--- a/esp32p4/src/ppa/blend_st.rs
+++ b/esp32p4/src/ppa/blend_st.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLEND_ST")
-            .field(
-                "blend_size_diff_st",
-                &format_args!("{}", self.blend_size_diff_st().bit()),
-            )
+            .field("blend_size_diff_st", &self.blend_size_diff_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLEND_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Blending engine status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blend_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BLEND_ST_SPEC;
 impl crate::RegisterSpec for BLEND_ST_SPEC {
diff --git a/esp32p4/src/ppa/blend_trans_mode.rs b/esp32p4/src/ppa/blend_trans_mode.rs
index 5a0e929434..dec195258b 100644
--- a/esp32p4/src/ppa/blend_trans_mode.rs
+++ b/esp32p4/src/ppa/blend_trans_mode.rs
@@ -46,25 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLEND_TRANS_MODE")
-            .field("blend_en", &format_args!("{}", self.blend_en().bit()))
-            .field(
-                "blend_bypass",
-                &format_args!("{}", self.blend_bypass().bit()),
-            )
-            .field(
-                "blend_fix_pixel_fill_en",
-                &format_args!("{}", self.blend_fix_pixel_fill_en().bit()),
-            )
-            .field("blend_rst", &format_args!("{}", self.blend_rst().bit()))
+            .field("blend_en", &self.blend_en())
+            .field("blend_bypass", &self.blend_bypass())
+            .field("blend_fix_pixel_fill_en", &self.blend_fix_pixel_fill_en())
+            .field("blend_rst", &self.blend_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLEND_TRANS_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable alpha blending."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/blend_tx_size.rs b/esp32p4/src/ppa/blend_tx_size.rs
index f1f40029d3..c61e3338fc 100644
--- a/esp32p4/src/ppa/blend_tx_size.rs
+++ b/esp32p4/src/ppa/blend_tx_size.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLEND_TX_SIZE")
-            .field("blend_hb", &format_args!("{}", self.blend_hb().bits()))
-            .field("blend_vb", &format_args!("{}", self.blend_vb().bits()))
+            .field("blend_hb", &self.blend_hb())
+            .field("blend_vb", &self.blend_vb())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLEND_TX_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - The horizontal width of image block that would be filled in fix pixel filling mode. The unit is pixel"]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/ck_bg_high.rs b/esp32p4/src/ppa/ck_bg_high.rs
index 9f88521b3f..d534895ead 100644
--- a/esp32p4/src/ppa/ck_bg_high.rs
+++ b/esp32p4/src/ppa/ck_bg_high.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CK_BG_HIGH")
-            .field(
-                "colorkey_bg_b_high",
-                &format_args!("{}", self.colorkey_bg_b_high().bits()),
-            )
-            .field(
-                "colorkey_bg_g_high",
-                &format_args!("{}", self.colorkey_bg_g_high().bits()),
-            )
-            .field(
-                "colorkey_bg_r_high",
-                &format_args!("{}", self.colorkey_bg_r_high().bits()),
-            )
+            .field("colorkey_bg_b_high", &self.colorkey_bg_b_high())
+            .field("colorkey_bg_g_high", &self.colorkey_bg_g_high())
+            .field("colorkey_bg_r_high", &self.colorkey_bg_r_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CK_BG_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - color key higher threshold of background b channel"]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/ck_bg_low.rs b/esp32p4/src/ppa/ck_bg_low.rs
index 1c189ab81e..98da637663 100644
--- a/esp32p4/src/ppa/ck_bg_low.rs
+++ b/esp32p4/src/ppa/ck_bg_low.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CK_BG_LOW")
-            .field(
-                "colorkey_bg_b_low",
-                &format_args!("{}", self.colorkey_bg_b_low().bits()),
-            )
-            .field(
-                "colorkey_bg_g_low",
-                &format_args!("{}", self.colorkey_bg_g_low().bits()),
-            )
-            .field(
-                "colorkey_bg_r_low",
-                &format_args!("{}", self.colorkey_bg_r_low().bits()),
-            )
+            .field("colorkey_bg_b_low", &self.colorkey_bg_b_low())
+            .field("colorkey_bg_g_low", &self.colorkey_bg_g_low())
+            .field("colorkey_bg_r_low", &self.colorkey_bg_r_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CK_BG_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - color key lower threshold of background b channel"]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/ck_default.rs b/esp32p4/src/ppa/ck_default.rs
index 96b3ac977d..ed989c8367 100644
--- a/esp32p4/src/ppa/ck_default.rs
+++ b/esp32p4/src/ppa/ck_default.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CK_DEFAULT")
-            .field(
-                "colorkey_default_b",
-                &format_args!("{}", self.colorkey_default_b().bits()),
-            )
-            .field(
-                "colorkey_default_g",
-                &format_args!("{}", self.colorkey_default_g().bits()),
-            )
-            .field(
-                "colorkey_default_r",
-                &format_args!("{}", self.colorkey_default_r().bits()),
-            )
-            .field(
-                "colorkey_fg_bg_reverse",
-                &format_args!("{}", self.colorkey_fg_bg_reverse().bit()),
-            )
+            .field("colorkey_default_b", &self.colorkey_default_b())
+            .field("colorkey_default_g", &self.colorkey_default_g())
+            .field("colorkey_default_r", &self.colorkey_default_r())
+            .field("colorkey_fg_bg_reverse", &self.colorkey_fg_bg_reverse())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CK_DEFAULT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - default B channle value of color key"]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/ck_fg_high.rs b/esp32p4/src/ppa/ck_fg_high.rs
index bca67adcd0..31694dd0d2 100644
--- a/esp32p4/src/ppa/ck_fg_high.rs
+++ b/esp32p4/src/ppa/ck_fg_high.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CK_FG_HIGH")
-            .field(
-                "colorkey_fg_b_high",
-                &format_args!("{}", self.colorkey_fg_b_high().bits()),
-            )
-            .field(
-                "colorkey_fg_g_high",
-                &format_args!("{}", self.colorkey_fg_g_high().bits()),
-            )
-            .field(
-                "colorkey_fg_r_high",
-                &format_args!("{}", self.colorkey_fg_r_high().bits()),
-            )
+            .field("colorkey_fg_b_high", &self.colorkey_fg_b_high())
+            .field("colorkey_fg_g_high", &self.colorkey_fg_g_high())
+            .field("colorkey_fg_r_high", &self.colorkey_fg_r_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CK_FG_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - color key higher threshold of foreground b channel"]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/ck_fg_low.rs b/esp32p4/src/ppa/ck_fg_low.rs
index ba47376319..ef63a18905 100644
--- a/esp32p4/src/ppa/ck_fg_low.rs
+++ b/esp32p4/src/ppa/ck_fg_low.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CK_FG_LOW")
-            .field(
-                "colorkey_fg_b_low",
-                &format_args!("{}", self.colorkey_fg_b_low().bits()),
-            )
-            .field(
-                "colorkey_fg_g_low",
-                &format_args!("{}", self.colorkey_fg_g_low().bits()),
-            )
-            .field(
-                "colorkey_fg_r_low",
-                &format_args!("{}", self.colorkey_fg_r_low().bits()),
-            )
+            .field("colorkey_fg_b_low", &self.colorkey_fg_b_low())
+            .field("colorkey_fg_g_low", &self.colorkey_fg_g_low())
+            .field("colorkey_fg_r_low", &self.colorkey_fg_r_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CK_FG_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - color key lower threshold of foreground b channel"]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/clut_cnt.rs b/esp32p4/src/ppa/clut_cnt.rs
index 0d9a208691..d00387f392 100644
--- a/esp32p4/src/ppa/clut_cnt.rs
+++ b/esp32p4/src/ppa/clut_cnt.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLUT_CNT")
-            .field(
-                "blend0_clut_cnt",
-                &format_args!("{}", self.blend0_clut_cnt().bits()),
-            )
-            .field(
-                "blend1_clut_cnt",
-                &format_args!("{}", self.blend1_clut_cnt().bits()),
-            )
+            .field("blend0_clut_cnt", &self.blend0_clut_cnt())
+            .field("blend1_clut_cnt", &self.blend1_clut_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLUT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLEND CLUT write counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clut_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLUT_CNT_SPEC;
 impl crate::RegisterSpec for CLUT_CNT_SPEC {
diff --git a/esp32p4/src/ppa/clut_conf.rs b/esp32p4/src/ppa/clut_conf.rs
index f8c1f8dcd7..e36d8f5686 100644
--- a/esp32p4/src/ppa/clut_conf.rs
+++ b/esp32p4/src/ppa/clut_conf.rs
@@ -80,47 +80,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLUT_CONF")
-            .field(
-                "apb_fifo_mask",
-                &format_args!("{}", self.apb_fifo_mask().bit()),
-            )
-            .field(
-                "blend0_clut_mem_rst",
-                &format_args!("{}", self.blend0_clut_mem_rst().bit()),
-            )
-            .field(
-                "blend1_clut_mem_rst",
-                &format_args!("{}", self.blend1_clut_mem_rst().bit()),
-            )
+            .field("apb_fifo_mask", &self.apb_fifo_mask())
+            .field("blend0_clut_mem_rst", &self.blend0_clut_mem_rst())
+            .field("blend1_clut_mem_rst", &self.blend1_clut_mem_rst())
             .field(
                 "blend0_clut_mem_rdaddr_rst",
-                &format_args!("{}", self.blend0_clut_mem_rdaddr_rst().bit()),
+                &self.blend0_clut_mem_rdaddr_rst(),
             )
             .field(
                 "blend1_clut_mem_rdaddr_rst",
-                &format_args!("{}", self.blend1_clut_mem_rdaddr_rst().bit()),
-            )
-            .field(
-                "blend0_clut_mem_force_pd",
-                &format_args!("{}", self.blend0_clut_mem_force_pd().bit()),
-            )
-            .field(
-                "blend0_clut_mem_force_pu",
-                &format_args!("{}", self.blend0_clut_mem_force_pu().bit()),
-            )
-            .field(
-                "blend0_clut_mem_clk_ena",
-                &format_args!("{}", self.blend0_clut_mem_clk_ena().bit()),
+                &self.blend1_clut_mem_rdaddr_rst(),
             )
+            .field("blend0_clut_mem_force_pd", &self.blend0_clut_mem_force_pd())
+            .field("blend0_clut_mem_force_pu", &self.blend0_clut_mem_force_pu())
+            .field("blend0_clut_mem_clk_ena", &self.blend0_clut_mem_clk_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLUT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr should be 01 to access sr clut and should be 10 to access blend0 clut and should be 11 to access blend 1 clut in memory mode."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/date.rs b/esp32p4/src/ppa/date.rs
index 62122a8052..cf8786110d 100644
--- a/esp32p4/src/ppa/date.rs
+++ b/esp32p4/src/ppa/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/ppa/eco_cell_ctrl.rs b/esp32p4/src/ppa/eco_cell_ctrl.rs
index c88e8e8f8b..b4b62ed80c 100644
--- a/esp32p4/src/ppa/eco_cell_ctrl.rs
+++ b/esp32p4/src/ppa/eco_cell_ctrl.rs
@@ -24,17 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_CELL_CTRL")
-            .field("rdn_result", &format_args!("{}", self.rdn_result().bit()))
-            .field("rdn_ena", &format_args!("{}", self.rdn_ena().bit()))
+            .field("rdn_result", &self.rdn_result())
+            .field("rdn_ena", &self.rdn_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_CELL_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Reserved."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/eco_high.rs b/esp32p4/src/ppa/eco_high.rs
index 7d8ba79ecf..d69eeff72a 100644
--- a/esp32p4/src/ppa/eco_high.rs
+++ b/esp32p4/src/ppa/eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_HIGH")
-            .field(
-                "rnd_eco_high",
-                &format_args!("{}", self.rnd_eco_high().bits()),
-            )
+            .field("rnd_eco_high", &self.rnd_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/eco_low.rs b/esp32p4/src/ppa/eco_low.rs
index 52e42e9190..87c8dac1a0 100644
--- a/esp32p4/src/ppa/eco_low.rs
+++ b/esp32p4/src/ppa/eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_LOW")
-            .field(
-                "rnd_eco_low",
-                &format_args!("{}", self.rnd_eco_low().bits()),
-            )
+            .field("rnd_eco_low", &self.rnd_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/int_ena.rs b/esp32p4/src/ppa/int_ena.rs
index d2ce918414..b8d1153881 100644
--- a/esp32p4/src/ppa/int_ena.rs
+++ b/esp32p4/src/ppa/int_ena.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("sr_eof", &format_args!("{}", self.sr_eof().bit()))
-            .field("blend_eof", &format_args!("{}", self.blend_eof().bit()))
-            .field(
-                "sr_param_cfg_err",
-                &format_args!("{}", self.sr_param_cfg_err().bit()),
-            )
+            .field("sr_eof", &self.sr_eof())
+            .field("blend_eof", &self.blend_eof())
+            .field("sr_param_cfg_err", &self.sr_param_cfg_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the PPA_SR_EOF_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/int_raw.rs b/esp32p4/src/ppa/int_raw.rs
index 9369107328..fa9be71ee4 100644
--- a/esp32p4/src/ppa/int_raw.rs
+++ b/esp32p4/src/ppa/int_raw.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("sr_eof", &format_args!("{}", self.sr_eof().bit()))
-            .field("blend_eof", &format_args!("{}", self.blend_eof().bit()))
-            .field(
-                "sr_param_cfg_err",
-                &format_args!("{}", self.sr_param_cfg_err().bit()),
-            )
+            .field("sr_eof", &self.sr_eof())
+            .field("blend_eof", &self.blend_eof())
+            .field("sr_param_cfg_err", &self.sr_param_cfg_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when scaling and rotating engine calculate one frame image."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/int_st.rs b/esp32p4/src/ppa/int_st.rs
index 0b62b8825e..7f461f8613 100644
--- a/esp32p4/src/ppa/int_st.rs
+++ b/esp32p4/src/ppa/int_st.rs
@@ -27,21 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("sr_eof", &format_args!("{}", self.sr_eof().bit()))
-            .field("blend_eof", &format_args!("{}", self.blend_eof().bit()))
-            .field(
-                "sr_param_cfg_err",
-                &format_args!("{}", self.sr_param_cfg_err().bit()),
-            )
+            .field("sr_eof", &self.sr_eof())
+            .field("blend_eof", &self.blend_eof())
+            .field("sr_param_cfg_err", &self.sr_param_cfg_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/ppa/reg_conf.rs b/esp32p4/src/ppa/reg_conf.rs
index a731544d43..1bc0b07b62 100644
--- a/esp32p4/src/ppa/reg_conf.rs
+++ b/esp32p4/src/ppa/reg_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - PPA register clock gate enable signal."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/sr_byte_order.rs b/esp32p4/src/ppa/sr_byte_order.rs
index 771cb822d3..f762a6f83a 100644
--- a/esp32p4/src/ppa/sr_byte_order.rs
+++ b/esp32p4/src/ppa/sr_byte_order.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR_BYTE_ORDER")
-            .field(
-                "sr_rx_byte_swap_en",
-                &format_args!("{}", self.sr_rx_byte_swap_en().bit()),
-            )
-            .field(
-                "sr_rx_rgb_swap_en",
-                &format_args!("{}", self.sr_rx_rgb_swap_en().bit()),
-            )
-            .field(
-                "sr_macro_bk_ro_bypass",
-                &format_args!("{}", self.sr_macro_bk_ro_bypass().bit()),
-            )
+            .field("sr_rx_byte_swap_en", &self.sr_rx_byte_swap_en())
+            .field("sr_rx_rgb_swap_en", &self.sr_rx_rgb_swap_en())
+            .field("sr_macro_bk_ro_bypass", &self.sr_macro_bk_ro_bypass())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_BYTE_ORDER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/sr_color_mode.rs b/esp32p4/src/ppa/sr_color_mode.rs
index 80647172af..b0a79ada5a 100644
--- a/esp32p4/src/ppa/sr_color_mode.rs
+++ b/esp32p4/src/ppa/sr_color_mode.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR_COLOR_MODE")
-            .field("sr_rx_cm", &format_args!("{}", self.sr_rx_cm().bits()))
-            .field("sr_tx_cm", &format_args!("{}", self.sr_tx_cm().bits()))
-            .field(
-                "yuv_rx_range",
-                &format_args!("{}", self.yuv_rx_range().bit()),
-            )
-            .field(
-                "yuv_tx_range",
-                &format_args!("{}", self.yuv_tx_range().bit()),
-            )
-            .field(
-                "yuv2rgb_protocal",
-                &format_args!("{}", self.yuv2rgb_protocal().bit()),
-            )
-            .field(
-                "rgb2yuv_protocal",
-                &format_args!("{}", self.rgb2yuv_protocal().bit()),
-            )
+            .field("sr_rx_cm", &self.sr_rx_cm())
+            .field("sr_tx_cm", &self.sr_tx_cm())
+            .field("yuv_rx_range", &self.yuv_rx_range())
+            .field("yuv_tx_range", &self.yuv_tx_range())
+            .field("yuv2rgb_protocal", &self.yuv2rgb_protocal())
+            .field("rgb2yuv_protocal", &self.rgb2yuv_protocal())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_COLOR_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/sr_fix_alpha.rs b/esp32p4/src/ppa/sr_fix_alpha.rs
index ae7578a6c5..0dc980d5e4 100644
--- a/esp32p4/src/ppa/sr_fix_alpha.rs
+++ b/esp32p4/src/ppa/sr_fix_alpha.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR_FIX_ALPHA")
-            .field(
-                "sr_rx_fix_alpha",
-                &format_args!("{}", self.sr_rx_fix_alpha().bits()),
-            )
-            .field(
-                "sr_rx_alpha_mod",
-                &format_args!("{}", self.sr_rx_alpha_mod().bits()),
-            )
-            .field(
-                "sr_rx_alpha_inv",
-                &format_args!("{}", self.sr_rx_alpha_inv().bit()),
-            )
+            .field("sr_rx_fix_alpha", &self.sr_rx_fix_alpha())
+            .field("sr_rx_alpha_mod", &self.sr_rx_alpha_mod())
+            .field("sr_rx_alpha_inv", &self.sr_rx_alpha_inv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_FIX_ALPHA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value would replace the alpha value in received pixel for Scaling and Rotating engine when PPA_SR_RX_ALPHA_CONF_EN is enabled."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/sr_mem_pd.rs b/esp32p4/src/ppa/sr_mem_pd.rs
index 2a972dacf4..a2fd5670aa 100644
--- a/esp32p4/src/ppa/sr_mem_pd.rs
+++ b/esp32p4/src/ppa/sr_mem_pd.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR_MEM_PD")
-            .field(
-                "sr_mem_clk_ena",
-                &format_args!("{}", self.sr_mem_clk_ena().bit()),
-            )
-            .field(
-                "sr_mem_force_pd",
-                &format_args!("{}", self.sr_mem_force_pd().bit()),
-            )
-            .field(
-                "sr_mem_force_pu",
-                &format_args!("{}", self.sr_mem_force_pu().bit()),
-            )
+            .field("sr_mem_clk_ena", &self.sr_mem_clk_ena())
+            .field("sr_mem_force_pd", &self.sr_mem_force_pd())
+            .field("sr_mem_force_pu", &self.sr_mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_MEM_PD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to force clock enable of scaling and rotating engine's data memory."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/sr_param_err_st.rs b/esp32p4/src/ppa/sr_param_err_st.rs
index beb74abe8c..67f541625e 100644
--- a/esp32p4/src/ppa/sr_param_err_st.rs
+++ b/esp32p4/src/ppa/sr_param_err_st.rs
@@ -104,71 +104,35 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR_PARAM_ERR_ST")
-            .field(
-                "tx_dscr_vb_err_st",
-                &format_args!("{}", self.tx_dscr_vb_err_st().bit()),
-            )
-            .field(
-                "tx_dscr_hb_err_st",
-                &format_args!("{}", self.tx_dscr_hb_err_st().bit()),
-            )
-            .field(
-                "y_rx_scal_equal_0_err_st",
-                &format_args!("{}", self.y_rx_scal_equal_0_err_st().bit()),
-            )
-            .field(
-                "rx_dscr_vb_err_st",
-                &format_args!("{}", self.rx_dscr_vb_err_st().bit()),
-            )
+            .field("tx_dscr_vb_err_st", &self.tx_dscr_vb_err_st())
+            .field("tx_dscr_hb_err_st", &self.tx_dscr_hb_err_st())
+            .field("y_rx_scal_equal_0_err_st", &self.y_rx_scal_equal_0_err_st())
+            .field("rx_dscr_vb_err_st", &self.rx_dscr_vb_err_st())
             .field(
                 "ydst_len_too_samll_err_st",
-                &format_args!("{}", self.ydst_len_too_samll_err_st().bit()),
+                &self.ydst_len_too_samll_err_st(),
             )
             .field(
                 "ydst_len_too_large_err_st",
-                &format_args!("{}", self.ydst_len_too_large_err_st().bit()),
-            )
-            .field(
-                "x_rx_scal_equal_0_err_st",
-                &format_args!("{}", self.x_rx_scal_equal_0_err_st().bit()),
-            )
-            .field(
-                "rx_dscr_hb_err_st",
-                &format_args!("{}", self.rx_dscr_hb_err_st().bit()),
+                &self.ydst_len_too_large_err_st(),
             )
+            .field("x_rx_scal_equal_0_err_st", &self.x_rx_scal_equal_0_err_st())
+            .field("rx_dscr_hb_err_st", &self.rx_dscr_hb_err_st())
             .field(
                 "xdst_len_too_samll_err_st",
-                &format_args!("{}", self.xdst_len_too_samll_err_st().bit()),
+                &self.xdst_len_too_samll_err_st(),
             )
             .field(
                 "xdst_len_too_large_err_st",
-                &format_args!("{}", self.xdst_len_too_large_err_st().bit()),
-            )
-            .field(
-                "x_yuv420_rx_scale_err_st",
-                &format_args!("{}", self.x_yuv420_rx_scale_err_st().bit()),
-            )
-            .field(
-                "y_yuv420_rx_scale_err_st",
-                &format_args!("{}", self.y_yuv420_rx_scale_err_st().bit()),
-            )
-            .field(
-                "x_yuv420_tx_scale_err_st",
-                &format_args!("{}", self.x_yuv420_tx_scale_err_st().bit()),
-            )
-            .field(
-                "y_yuv420_tx_scale_err_st",
-                &format_args!("{}", self.y_yuv420_tx_scale_err_st().bit()),
+                &self.xdst_len_too_large_err_st(),
             )
+            .field("x_yuv420_rx_scale_err_st", &self.x_yuv420_rx_scale_err_st())
+            .field("y_yuv420_rx_scale_err_st", &self.y_yuv420_rx_scale_err_st())
+            .field("x_yuv420_tx_scale_err_st", &self.x_yuv420_tx_scale_err_st())
+            .field("y_yuv420_tx_scale_err_st", &self.y_yuv420_tx_scale_err_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_PARAM_ERR_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Scaling and rotating coefficient error register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_param_err_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SR_PARAM_ERR_ST_SPEC;
 impl crate::RegisterSpec for SR_PARAM_ERR_ST_SPEC {
diff --git a/esp32p4/src/ppa/sr_scal_rotate.rs b/esp32p4/src/ppa/sr_scal_rotate.rs
index 1009de9cf6..5517309703 100644
--- a/esp32p4/src/ppa/sr_scal_rotate.rs
+++ b/esp32p4/src/ppa/sr_scal_rotate.rs
@@ -82,41 +82,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR_SCAL_ROTATE")
-            .field(
-                "sr_scal_x_int",
-                &format_args!("{}", self.sr_scal_x_int().bits()),
-            )
-            .field(
-                "sr_scal_x_frag",
-                &format_args!("{}", self.sr_scal_x_frag().bits()),
-            )
-            .field(
-                "sr_scal_y_int",
-                &format_args!("{}", self.sr_scal_y_int().bits()),
-            )
-            .field(
-                "sr_scal_y_frag",
-                &format_args!("{}", self.sr_scal_y_frag().bits()),
-            )
-            .field(
-                "sr_rotate_angle",
-                &format_args!("{}", self.sr_rotate_angle().bits()),
-            )
-            .field(
-                "scal_rotate_rst",
-                &format_args!("{}", self.scal_rotate_rst().bit()),
-            )
-            .field("sr_mirror_x", &format_args!("{}", self.sr_mirror_x().bit()))
-            .field("sr_mirror_y", &format_args!("{}", self.sr_mirror_y().bit()))
+            .field("sr_scal_x_int", &self.sr_scal_x_int())
+            .field("sr_scal_x_frag", &self.sr_scal_x_frag())
+            .field("sr_scal_y_int", &self.sr_scal_y_int())
+            .field("sr_scal_y_frag", &self.sr_scal_y_frag())
+            .field("sr_rotate_angle", &self.sr_rotate_angle())
+            .field("scal_rotate_rst", &self.scal_rotate_rst())
+            .field("sr_mirror_x", &self.sr_mirror_x())
+            .field("sr_mirror_y", &self.sr_mirror_y())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_SCAL_ROTATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The integrated part of scaling coefficient in X direction."]
     #[inline(always)]
diff --git a/esp32p4/src/ppa/sr_status.rs b/esp32p4/src/ppa/sr_status.rs
index 070d81d1b4..4cc1e415b0 100644
--- a/esp32p4/src/ppa/sr_status.rs
+++ b/esp32p4/src/ppa/sr_status.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR_STATUS")
-            .field(
-                "sr_rx_dscr_sample_state",
-                &format_args!("{}", self.sr_rx_dscr_sample_state().bits()),
-            )
-            .field(
-                "sr_rx_scan_state",
-                &format_args!("{}", self.sr_rx_scan_state().bits()),
-            )
-            .field(
-                "sr_tx_dscr_sample_state",
-                &format_args!("{}", self.sr_tx_dscr_sample_state().bits()),
-            )
-            .field(
-                "sr_tx_scan_state",
-                &format_args!("{}", self.sr_tx_scan_state().bits()),
-            )
+            .field("sr_rx_dscr_sample_state", &self.sr_rx_dscr_sample_state())
+            .field("sr_rx_scan_state", &self.sr_rx_scan_state())
+            .field("sr_tx_dscr_sample_state", &self.sr_tx_dscr_sample_state())
+            .field("sr_tx_scan_state", &self.sr_tx_scan_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SR FSM register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SR_STATUS_SPEC;
 impl crate::RegisterSpec for SR_STATUS_SPEC {
diff --git a/esp32p4/src/ppa/sram_ctrl.rs b/esp32p4/src/ppa/sram_ctrl.rs
index 6eb1278bb5..34cac8233a 100644
--- a/esp32p4/src/ppa/sram_ctrl.rs
+++ b/esp32p4/src/ppa/sram_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_CTRL")
-            .field(
-                "mem_aux_ctrl",
-                &format_args!("{}", self.mem_aux_ctrl().bits()),
-            )
+            .field("mem_aux_ctrl", &self.mem_aux_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Control signals"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/clk_cfg.rs b/esp32p4/src/pvt/clk_cfg.rs
index 45211a1b7a..864f2e7b95 100644
--- a/esp32p4/src/pvt/clk_cfg.rs
+++ b/esp32p4/src/pvt/clk_cfg.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CFG")
-            .field(
-                "pump_clk_div_num",
-                &format_args!("{}", self.pump_clk_div_num().bits()),
-            )
-            .field(
-                "monitor_clk_pvt_en",
-                &format_args!("{}", self.monitor_clk_pvt_en().bit()),
-            )
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bit()))
+            .field("pump_clk_div_num", &self.pump_clk_div_num())
+            .field("monitor_clk_pvt_en", &self.monitor_clk_pvt_en())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit0_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit0_vt0_conf1.rs
index 0201a67274..fa917780fc 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit0_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit0_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT0_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site0_unit0",
-                &format_args!("{}", self.monitor_en_vt0_pd_site0_unit0().bit()),
+                &self.monitor_en_vt0_pd_site0_unit0(),
             )
             .field(
                 "delay_limit_vt0_pd_site0_unit0",
-                &format_args!("{}", self.delay_limit_vt0_pd_site0_unit0().bits()),
+                &self.delay_limit_vt0_pd_site0_unit0(),
             )
             .field(
                 "delay_num_o_vt0_pd_site0_unit0",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site0_unit0().bits()),
+                &self.delay_num_o_vt0_pd_site0_unit0(),
             )
             .field(
                 "timing_err_vt0_pd_site0_unit0",
-                &format_args!("{}", self.timing_err_vt0_pd_site0_unit0().bit()),
+                &self.timing_err_vt0_pd_site0_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT0_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit0_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit0_vt0_conf2.rs
index e3ecb01828..3e4169cf20 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit0_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit0_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT0_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site0_unit0",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site0_unit0().bits()),
+                &self.monitor_edg_mod_vt0_pd_site0_unit0(),
             )
             .field(
                 "delay_ovf_vt0_pd_site0_unit0",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site0_unit0().bit()),
+                &self.delay_ovf_vt0_pd_site0_unit0(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site0_unit0",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site0_unit0().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site0_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT0_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit0_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit0_vt1_conf1.rs
index 059006cfa3..910792cdd4 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit0_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit0_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT0_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site0_unit0",
-                &format_args!("{}", self.monitor_en_vt1_pd_site0_unit0().bit()),
+                &self.monitor_en_vt1_pd_site0_unit0(),
             )
             .field(
                 "delay_limit_vt1_pd_site0_unit0",
-                &format_args!("{}", self.delay_limit_vt1_pd_site0_unit0().bits()),
+                &self.delay_limit_vt1_pd_site0_unit0(),
             )
             .field(
                 "delay_num_o_vt1_pd_site0_unit0",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site0_unit0().bits()),
+                &self.delay_num_o_vt1_pd_site0_unit0(),
             )
             .field(
                 "timing_err_vt1_pd_site0_unit0",
-                &format_args!("{}", self.timing_err_vt1_pd_site0_unit0().bit()),
+                &self.timing_err_vt1_pd_site0_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT0_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit0_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit0_vt1_conf2.rs
index c2b3096fc4..b5b265b194 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit0_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit0_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT0_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site0_unit0",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site0_unit0().bits()),
+                &self.monitor_edg_mod_vt1_pd_site0_unit0(),
             )
             .field(
                 "delay_ovf_vt1_pd_site0_unit0",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site0_unit0().bit()),
+                &self.delay_ovf_vt1_pd_site0_unit0(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site0_unit0",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site0_unit0().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site0_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT0_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit0_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit0_vt2_conf1.rs
index 73bd0d249b..5c2cde420d 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit0_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit0_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT0_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site0_unit0",
-                &format_args!("{}", self.monitor_en_vt2_pd_site0_unit0().bit()),
+                &self.monitor_en_vt2_pd_site0_unit0(),
             )
             .field(
                 "delay_limit_vt2_pd_site0_unit0",
-                &format_args!("{}", self.delay_limit_vt2_pd_site0_unit0().bits()),
+                &self.delay_limit_vt2_pd_site0_unit0(),
             )
             .field(
                 "delay_num_o_vt2_pd_site0_unit0",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site0_unit0().bits()),
+                &self.delay_num_o_vt2_pd_site0_unit0(),
             )
             .field(
                 "timing_err_vt2_pd_site0_unit0",
-                &format_args!("{}", self.timing_err_vt2_pd_site0_unit0().bit()),
+                &self.timing_err_vt2_pd_site0_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT0_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit0_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit0_vt2_conf2.rs
index 785088b54e..f79692c810 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit0_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit0_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT0_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site0_unit0",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site0_unit0().bits()),
+                &self.monitor_edg_mod_vt2_pd_site0_unit0(),
             )
             .field(
                 "delay_ovf_vt2_pd_site0_unit0",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site0_unit0().bit()),
+                &self.delay_ovf_vt2_pd_site0_unit0(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site0_unit0",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site0_unit0().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site0_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT0_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit1_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit1_vt0_conf1.rs
index 021de608bf..53f2e02256 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit1_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit1_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT1_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site0_unit1",
-                &format_args!("{}", self.monitor_en_vt0_pd_site0_unit1().bit()),
+                &self.monitor_en_vt0_pd_site0_unit1(),
             )
             .field(
                 "delay_limit_vt0_pd_site0_unit1",
-                &format_args!("{}", self.delay_limit_vt0_pd_site0_unit1().bits()),
+                &self.delay_limit_vt0_pd_site0_unit1(),
             )
             .field(
                 "delay_num_o_vt0_pd_site0_unit1",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site0_unit1().bits()),
+                &self.delay_num_o_vt0_pd_site0_unit1(),
             )
             .field(
                 "timing_err_vt0_pd_site0_unit1",
-                &format_args!("{}", self.timing_err_vt0_pd_site0_unit1().bit()),
+                &self.timing_err_vt0_pd_site0_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT1_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit1_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit1_vt0_conf2.rs
index d1f57ad8c4..1aebeb73af 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit1_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit1_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT1_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site0_unit1",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site0_unit1().bits()),
+                &self.monitor_edg_mod_vt0_pd_site0_unit1(),
             )
             .field(
                 "delay_ovf_vt0_pd_site0_unit1",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site0_unit1().bit()),
+                &self.delay_ovf_vt0_pd_site0_unit1(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site0_unit1",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site0_unit1().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site0_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT1_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit1_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit1_vt1_conf1.rs
index 9a81678ec1..e19e1d38d2 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit1_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit1_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT1_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site0_unit1",
-                &format_args!("{}", self.monitor_en_vt1_pd_site0_unit1().bit()),
+                &self.monitor_en_vt1_pd_site0_unit1(),
             )
             .field(
                 "delay_limit_vt1_pd_site0_unit1",
-                &format_args!("{}", self.delay_limit_vt1_pd_site0_unit1().bits()),
+                &self.delay_limit_vt1_pd_site0_unit1(),
             )
             .field(
                 "delay_num_o_vt1_pd_site0_unit1",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site0_unit1().bits()),
+                &self.delay_num_o_vt1_pd_site0_unit1(),
             )
             .field(
                 "timing_err_vt1_pd_site0_unit1",
-                &format_args!("{}", self.timing_err_vt1_pd_site0_unit1().bit()),
+                &self.timing_err_vt1_pd_site0_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT1_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit1_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit1_vt1_conf2.rs
index f76ee35c7b..1cff7dea96 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit1_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit1_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT1_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site0_unit1",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site0_unit1().bits()),
+                &self.monitor_edg_mod_vt1_pd_site0_unit1(),
             )
             .field(
                 "delay_ovf_vt1_pd_site0_unit1",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site0_unit1().bit()),
+                &self.delay_ovf_vt1_pd_site0_unit1(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site0_unit1",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site0_unit1().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site0_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT1_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit1_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit1_vt2_conf1.rs
index 3bab7b110c..8a07b5265a 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit1_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit1_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT1_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site0_unit1",
-                &format_args!("{}", self.monitor_en_vt2_pd_site0_unit1().bit()),
+                &self.monitor_en_vt2_pd_site0_unit1(),
             )
             .field(
                 "delay_limit_vt2_pd_site0_unit1",
-                &format_args!("{}", self.delay_limit_vt2_pd_site0_unit1().bits()),
+                &self.delay_limit_vt2_pd_site0_unit1(),
             )
             .field(
                 "delay_num_o_vt2_pd_site0_unit1",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site0_unit1().bits()),
+                &self.delay_num_o_vt2_pd_site0_unit1(),
             )
             .field(
                 "timing_err_vt2_pd_site0_unit1",
-                &format_args!("{}", self.timing_err_vt2_pd_site0_unit1().bit()),
+                &self.timing_err_vt2_pd_site0_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT1_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit1_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit1_vt2_conf2.rs
index 17ad4a6c89..0a1dae14b3 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit1_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit1_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT1_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site0_unit1",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site0_unit1().bits()),
+                &self.monitor_edg_mod_vt2_pd_site0_unit1(),
             )
             .field(
                 "delay_ovf_vt2_pd_site0_unit1",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site0_unit1().bit()),
+                &self.delay_ovf_vt2_pd_site0_unit1(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site0_unit1",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site0_unit1().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site0_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT1_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit2_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit2_vt0_conf1.rs
index 94f5f19110..cc73937b73 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit2_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit2_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT2_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site0_unit2",
-                &format_args!("{}", self.monitor_en_vt0_pd_site0_unit2().bit()),
+                &self.monitor_en_vt0_pd_site0_unit2(),
             )
             .field(
                 "delay_limit_vt0_pd_site0_unit2",
-                &format_args!("{}", self.delay_limit_vt0_pd_site0_unit2().bits()),
+                &self.delay_limit_vt0_pd_site0_unit2(),
             )
             .field(
                 "delay_num_o_vt0_pd_site0_unit2",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site0_unit2().bits()),
+                &self.delay_num_o_vt0_pd_site0_unit2(),
             )
             .field(
                 "timing_err_vt0_pd_site0_unit2",
-                &format_args!("{}", self.timing_err_vt0_pd_site0_unit2().bit()),
+                &self.timing_err_vt0_pd_site0_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT2_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit2_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit2_vt0_conf2.rs
index 9dd1f0c0ff..7bf2326b88 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit2_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit2_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT2_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site0_unit2",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site0_unit2().bits()),
+                &self.monitor_edg_mod_vt0_pd_site0_unit2(),
             )
             .field(
                 "delay_ovf_vt0_pd_site0_unit2",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site0_unit2().bit()),
+                &self.delay_ovf_vt0_pd_site0_unit2(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site0_unit2",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site0_unit2().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site0_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT2_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit2_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit2_vt1_conf1.rs
index a4ba6d6713..10ad1616f1 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit2_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit2_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT2_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site0_unit2",
-                &format_args!("{}", self.monitor_en_vt1_pd_site0_unit2().bit()),
+                &self.monitor_en_vt1_pd_site0_unit2(),
             )
             .field(
                 "delay_limit_vt1_pd_site0_unit2",
-                &format_args!("{}", self.delay_limit_vt1_pd_site0_unit2().bits()),
+                &self.delay_limit_vt1_pd_site0_unit2(),
             )
             .field(
                 "delay_num_o_vt1_pd_site0_unit2",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site0_unit2().bits()),
+                &self.delay_num_o_vt1_pd_site0_unit2(),
             )
             .field(
                 "timing_err_vt1_pd_site0_unit2",
-                &format_args!("{}", self.timing_err_vt1_pd_site0_unit2().bit()),
+                &self.timing_err_vt1_pd_site0_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT2_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit2_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit2_vt1_conf2.rs
index 69fc00a55d..40be6e8f82 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit2_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit2_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT2_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site0_unit2",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site0_unit2().bits()),
+                &self.monitor_edg_mod_vt1_pd_site0_unit2(),
             )
             .field(
                 "delay_ovf_vt1_pd_site0_unit2",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site0_unit2().bit()),
+                &self.delay_ovf_vt1_pd_site0_unit2(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site0_unit2",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site0_unit2().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site0_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT2_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit2_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit2_vt2_conf1.rs
index 8d6e73e01b..715919f01b 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit2_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit2_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT2_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site0_unit2",
-                &format_args!("{}", self.monitor_en_vt2_pd_site0_unit2().bit()),
+                &self.monitor_en_vt2_pd_site0_unit2(),
             )
             .field(
                 "delay_limit_vt2_pd_site0_unit2",
-                &format_args!("{}", self.delay_limit_vt2_pd_site0_unit2().bits()),
+                &self.delay_limit_vt2_pd_site0_unit2(),
             )
             .field(
                 "delay_num_o_vt2_pd_site0_unit2",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site0_unit2().bits()),
+                &self.delay_num_o_vt2_pd_site0_unit2(),
             )
             .field(
                 "timing_err_vt2_pd_site0_unit2",
-                &format_args!("{}", self.timing_err_vt2_pd_site0_unit2().bit()),
+                &self.timing_err_vt2_pd_site0_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT2_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit2_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit2_vt2_conf2.rs
index cf8ec8caf1..37b8e1559f 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit2_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit2_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT2_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site0_unit2",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site0_unit2().bits()),
+                &self.monitor_edg_mod_vt2_pd_site0_unit2(),
             )
             .field(
                 "delay_ovf_vt2_pd_site0_unit2",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site0_unit2().bit()),
+                &self.delay_ovf_vt2_pd_site0_unit2(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site0_unit2",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site0_unit2().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site0_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT2_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit3_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit3_vt0_conf1.rs
index 2fdd5cfe57..7fd75c0b04 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit3_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit3_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT3_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site0_unit3",
-                &format_args!("{}", self.monitor_en_vt0_pd_site0_unit3().bit()),
+                &self.monitor_en_vt0_pd_site0_unit3(),
             )
             .field(
                 "delay_limit_vt0_pd_site0_unit3",
-                &format_args!("{}", self.delay_limit_vt0_pd_site0_unit3().bits()),
+                &self.delay_limit_vt0_pd_site0_unit3(),
             )
             .field(
                 "delay_num_o_vt0_pd_site0_unit3",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site0_unit3().bits()),
+                &self.delay_num_o_vt0_pd_site0_unit3(),
             )
             .field(
                 "timing_err_vt0_pd_site0_unit3",
-                &format_args!("{}", self.timing_err_vt0_pd_site0_unit3().bit()),
+                &self.timing_err_vt0_pd_site0_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT3_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit3_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit3_vt0_conf2.rs
index b9b6ff8569..35753822a8 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit3_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit3_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT3_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site0_unit3",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site0_unit3().bits()),
+                &self.monitor_edg_mod_vt0_pd_site0_unit3(),
             )
             .field(
                 "delay_ovf_vt0_pd_site0_unit3",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site0_unit3().bit()),
+                &self.delay_ovf_vt0_pd_site0_unit3(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site0_unit3",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site0_unit3().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site0_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT3_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit3_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit3_vt1_conf1.rs
index 76bc216dc6..201cae6b42 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit3_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit3_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT3_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site0_unit3",
-                &format_args!("{}", self.monitor_en_vt1_pd_site0_unit3().bit()),
+                &self.monitor_en_vt1_pd_site0_unit3(),
             )
             .field(
                 "delay_limit_vt1_pd_site0_unit3",
-                &format_args!("{}", self.delay_limit_vt1_pd_site0_unit3().bits()),
+                &self.delay_limit_vt1_pd_site0_unit3(),
             )
             .field(
                 "delay_num_o_vt1_pd_site0_unit3",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site0_unit3().bits()),
+                &self.delay_num_o_vt1_pd_site0_unit3(),
             )
             .field(
                 "timing_err_vt1_pd_site0_unit3",
-                &format_args!("{}", self.timing_err_vt1_pd_site0_unit3().bit()),
+                &self.timing_err_vt1_pd_site0_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT3_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit3_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit3_vt1_conf2.rs
index beb6419abf..f8ff0585f6 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit3_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit3_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT3_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site0_unit3",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site0_unit3().bits()),
+                &self.monitor_edg_mod_vt1_pd_site0_unit3(),
             )
             .field(
                 "delay_ovf_vt1_pd_site0_unit3",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site0_unit3().bit()),
+                &self.delay_ovf_vt1_pd_site0_unit3(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site0_unit3",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site0_unit3().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site0_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT3_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit3_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site0_unit3_vt2_conf1.rs
index 9b242555d9..f44a5109b9 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit3_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit3_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT3_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site0_unit3",
-                &format_args!("{}", self.monitor_en_vt2_pd_site0_unit3().bit()),
+                &self.monitor_en_vt2_pd_site0_unit3(),
             )
             .field(
                 "delay_limit_vt2_pd_site0_unit3",
-                &format_args!("{}", self.delay_limit_vt2_pd_site0_unit3().bits()),
+                &self.delay_limit_vt2_pd_site0_unit3(),
             )
             .field(
                 "delay_num_o_vt2_pd_site0_unit3",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site0_unit3().bits()),
+                &self.delay_num_o_vt2_pd_site0_unit3(),
             )
             .field(
                 "timing_err_vt2_pd_site0_unit3",
-                &format_args!("{}", self.timing_err_vt2_pd_site0_unit3().bit()),
+                &self.timing_err_vt2_pd_site0_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT3_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site0_unit3_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site0_unit3_vt2_conf2.rs
index 798dbae933..53ee353b60 100644
--- a/esp32p4/src/pvt/comb_pd_site0_unit3_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site0_unit3_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE0_UNIT3_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site0_unit3",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site0_unit3().bits()),
+                &self.monitor_edg_mod_vt2_pd_site0_unit3(),
             )
             .field(
                 "delay_ovf_vt2_pd_site0_unit3",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site0_unit3().bit()),
+                &self.delay_ovf_vt2_pd_site0_unit3(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site0_unit3",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site0_unit3().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site0_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE0_UNIT3_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit0_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit0_vt0_conf1.rs
index 1d7249d261..fc8ddf76b2 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit0_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit0_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT0_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site1_unit0",
-                &format_args!("{}", self.monitor_en_vt0_pd_site1_unit0().bit()),
+                &self.monitor_en_vt0_pd_site1_unit0(),
             )
             .field(
                 "delay_limit_vt0_pd_site1_unit0",
-                &format_args!("{}", self.delay_limit_vt0_pd_site1_unit0().bits()),
+                &self.delay_limit_vt0_pd_site1_unit0(),
             )
             .field(
                 "delay_num_o_vt0_pd_site1_unit0",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site1_unit0().bits()),
+                &self.delay_num_o_vt0_pd_site1_unit0(),
             )
             .field(
                 "timing_err_vt0_pd_site1_unit0",
-                &format_args!("{}", self.timing_err_vt0_pd_site1_unit0().bit()),
+                &self.timing_err_vt0_pd_site1_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT0_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit0_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit0_vt0_conf2.rs
index 7bb2b1f529..03ab7e4cd7 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit0_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit0_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT0_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site1_unit0",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site1_unit0().bits()),
+                &self.monitor_edg_mod_vt0_pd_site1_unit0(),
             )
             .field(
                 "delay_ovf_vt0_pd_site1_unit0",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site1_unit0().bit()),
+                &self.delay_ovf_vt0_pd_site1_unit0(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site1_unit0",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site1_unit0().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site1_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT0_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit0_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit0_vt1_conf1.rs
index 099c501607..fb3f5ff544 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit0_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit0_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT0_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site1_unit0",
-                &format_args!("{}", self.monitor_en_vt1_pd_site1_unit0().bit()),
+                &self.monitor_en_vt1_pd_site1_unit0(),
             )
             .field(
                 "delay_limit_vt1_pd_site1_unit0",
-                &format_args!("{}", self.delay_limit_vt1_pd_site1_unit0().bits()),
+                &self.delay_limit_vt1_pd_site1_unit0(),
             )
             .field(
                 "delay_num_o_vt1_pd_site1_unit0",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site1_unit0().bits()),
+                &self.delay_num_o_vt1_pd_site1_unit0(),
             )
             .field(
                 "timing_err_vt1_pd_site1_unit0",
-                &format_args!("{}", self.timing_err_vt1_pd_site1_unit0().bit()),
+                &self.timing_err_vt1_pd_site1_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT0_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit0_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit0_vt1_conf2.rs
index 8df1c2057d..3e44ecc565 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit0_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit0_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT0_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site1_unit0",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site1_unit0().bits()),
+                &self.monitor_edg_mod_vt1_pd_site1_unit0(),
             )
             .field(
                 "delay_ovf_vt1_pd_site1_unit0",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site1_unit0().bit()),
+                &self.delay_ovf_vt1_pd_site1_unit0(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site1_unit0",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site1_unit0().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site1_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT0_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit0_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit0_vt2_conf1.rs
index bed5409ab3..f47fcd4ceb 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit0_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit0_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT0_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site1_unit0",
-                &format_args!("{}", self.monitor_en_vt2_pd_site1_unit0().bit()),
+                &self.monitor_en_vt2_pd_site1_unit0(),
             )
             .field(
                 "delay_limit_vt2_pd_site1_unit0",
-                &format_args!("{}", self.delay_limit_vt2_pd_site1_unit0().bits()),
+                &self.delay_limit_vt2_pd_site1_unit0(),
             )
             .field(
                 "delay_num_o_vt2_pd_site1_unit0",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site1_unit0().bits()),
+                &self.delay_num_o_vt2_pd_site1_unit0(),
             )
             .field(
                 "timing_err_vt2_pd_site1_unit0",
-                &format_args!("{}", self.timing_err_vt2_pd_site1_unit0().bit()),
+                &self.timing_err_vt2_pd_site1_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT0_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit0_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit0_vt2_conf2.rs
index f50d0d833b..efa8064d28 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit0_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit0_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT0_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site1_unit0",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site1_unit0().bits()),
+                &self.monitor_edg_mod_vt2_pd_site1_unit0(),
             )
             .field(
                 "delay_ovf_vt2_pd_site1_unit0",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site1_unit0().bit()),
+                &self.delay_ovf_vt2_pd_site1_unit0(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site1_unit0",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site1_unit0().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site1_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT0_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit1_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit1_vt0_conf1.rs
index 58c4a3188c..43d8597e36 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit1_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit1_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT1_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site1_unit1",
-                &format_args!("{}", self.monitor_en_vt0_pd_site1_unit1().bit()),
+                &self.monitor_en_vt0_pd_site1_unit1(),
             )
             .field(
                 "delay_limit_vt0_pd_site1_unit1",
-                &format_args!("{}", self.delay_limit_vt0_pd_site1_unit1().bits()),
+                &self.delay_limit_vt0_pd_site1_unit1(),
             )
             .field(
                 "delay_num_o_vt0_pd_site1_unit1",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site1_unit1().bits()),
+                &self.delay_num_o_vt0_pd_site1_unit1(),
             )
             .field(
                 "timing_err_vt0_pd_site1_unit1",
-                &format_args!("{}", self.timing_err_vt0_pd_site1_unit1().bit()),
+                &self.timing_err_vt0_pd_site1_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT1_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit1_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit1_vt0_conf2.rs
index a2e1617b4e..e3032611a8 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit1_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit1_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT1_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site1_unit1",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site1_unit1().bits()),
+                &self.monitor_edg_mod_vt0_pd_site1_unit1(),
             )
             .field(
                 "delay_ovf_vt0_pd_site1_unit1",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site1_unit1().bit()),
+                &self.delay_ovf_vt0_pd_site1_unit1(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site1_unit1",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site1_unit1().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site1_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT1_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit1_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit1_vt1_conf1.rs
index a083f6a887..fe2db2a13a 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit1_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit1_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT1_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site1_unit1",
-                &format_args!("{}", self.monitor_en_vt1_pd_site1_unit1().bit()),
+                &self.monitor_en_vt1_pd_site1_unit1(),
             )
             .field(
                 "delay_limit_vt1_pd_site1_unit1",
-                &format_args!("{}", self.delay_limit_vt1_pd_site1_unit1().bits()),
+                &self.delay_limit_vt1_pd_site1_unit1(),
             )
             .field(
                 "delay_num_o_vt1_pd_site1_unit1",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site1_unit1().bits()),
+                &self.delay_num_o_vt1_pd_site1_unit1(),
             )
             .field(
                 "timing_err_vt1_pd_site1_unit1",
-                &format_args!("{}", self.timing_err_vt1_pd_site1_unit1().bit()),
+                &self.timing_err_vt1_pd_site1_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT1_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit1_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit1_vt1_conf2.rs
index cde56c149c..b509b2a718 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit1_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit1_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT1_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site1_unit1",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site1_unit1().bits()),
+                &self.monitor_edg_mod_vt1_pd_site1_unit1(),
             )
             .field(
                 "delay_ovf_vt1_pd_site1_unit1",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site1_unit1().bit()),
+                &self.delay_ovf_vt1_pd_site1_unit1(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site1_unit1",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site1_unit1().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site1_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT1_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit1_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit1_vt2_conf1.rs
index 7fe7044cde..e0b517a82b 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit1_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit1_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT1_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site1_unit1",
-                &format_args!("{}", self.monitor_en_vt2_pd_site1_unit1().bit()),
+                &self.monitor_en_vt2_pd_site1_unit1(),
             )
             .field(
                 "delay_limit_vt2_pd_site1_unit1",
-                &format_args!("{}", self.delay_limit_vt2_pd_site1_unit1().bits()),
+                &self.delay_limit_vt2_pd_site1_unit1(),
             )
             .field(
                 "delay_num_o_vt2_pd_site1_unit1",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site1_unit1().bits()),
+                &self.delay_num_o_vt2_pd_site1_unit1(),
             )
             .field(
                 "timing_err_vt2_pd_site1_unit1",
-                &format_args!("{}", self.timing_err_vt2_pd_site1_unit1().bit()),
+                &self.timing_err_vt2_pd_site1_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT1_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit1_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit1_vt2_conf2.rs
index a8115f179b..722d3c6f16 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit1_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit1_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT1_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site1_unit1",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site1_unit1().bits()),
+                &self.monitor_edg_mod_vt2_pd_site1_unit1(),
             )
             .field(
                 "delay_ovf_vt2_pd_site1_unit1",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site1_unit1().bit()),
+                &self.delay_ovf_vt2_pd_site1_unit1(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site1_unit1",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site1_unit1().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site1_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT1_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit2_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit2_vt0_conf1.rs
index 1ace0681ca..31fb613df1 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit2_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit2_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT2_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site1_unit2",
-                &format_args!("{}", self.monitor_en_vt0_pd_site1_unit2().bit()),
+                &self.monitor_en_vt0_pd_site1_unit2(),
             )
             .field(
                 "delay_limit_vt0_pd_site1_unit2",
-                &format_args!("{}", self.delay_limit_vt0_pd_site1_unit2().bits()),
+                &self.delay_limit_vt0_pd_site1_unit2(),
             )
             .field(
                 "delay_num_o_vt0_pd_site1_unit2",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site1_unit2().bits()),
+                &self.delay_num_o_vt0_pd_site1_unit2(),
             )
             .field(
                 "timing_err_vt0_pd_site1_unit2",
-                &format_args!("{}", self.timing_err_vt0_pd_site1_unit2().bit()),
+                &self.timing_err_vt0_pd_site1_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT2_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit2_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit2_vt0_conf2.rs
index 18241132de..7ddbd8f526 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit2_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit2_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT2_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site1_unit2",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site1_unit2().bits()),
+                &self.monitor_edg_mod_vt0_pd_site1_unit2(),
             )
             .field(
                 "delay_ovf_vt0_pd_site1_unit2",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site1_unit2().bit()),
+                &self.delay_ovf_vt0_pd_site1_unit2(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site1_unit2",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site1_unit2().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site1_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT2_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit2_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit2_vt1_conf1.rs
index 880d4cf3c4..620ee1c761 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit2_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit2_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT2_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site1_unit2",
-                &format_args!("{}", self.monitor_en_vt1_pd_site1_unit2().bit()),
+                &self.monitor_en_vt1_pd_site1_unit2(),
             )
             .field(
                 "delay_limit_vt1_pd_site1_unit2",
-                &format_args!("{}", self.delay_limit_vt1_pd_site1_unit2().bits()),
+                &self.delay_limit_vt1_pd_site1_unit2(),
             )
             .field(
                 "delay_num_o_vt1_pd_site1_unit2",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site1_unit2().bits()),
+                &self.delay_num_o_vt1_pd_site1_unit2(),
             )
             .field(
                 "timing_err_vt1_pd_site1_unit2",
-                &format_args!("{}", self.timing_err_vt1_pd_site1_unit2().bit()),
+                &self.timing_err_vt1_pd_site1_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT2_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit2_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit2_vt1_conf2.rs
index d35c4e16ee..acbe7d0087 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit2_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit2_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT2_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site1_unit2",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site1_unit2().bits()),
+                &self.monitor_edg_mod_vt1_pd_site1_unit2(),
             )
             .field(
                 "delay_ovf_vt1_pd_site1_unit2",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site1_unit2().bit()),
+                &self.delay_ovf_vt1_pd_site1_unit2(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site1_unit2",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site1_unit2().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site1_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT2_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit2_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit2_vt2_conf1.rs
index 714c7e694c..431456e450 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit2_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit2_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT2_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site1_unit2",
-                &format_args!("{}", self.monitor_en_vt2_pd_site1_unit2().bit()),
+                &self.monitor_en_vt2_pd_site1_unit2(),
             )
             .field(
                 "delay_limit_vt2_pd_site1_unit2",
-                &format_args!("{}", self.delay_limit_vt2_pd_site1_unit2().bits()),
+                &self.delay_limit_vt2_pd_site1_unit2(),
             )
             .field(
                 "delay_num_o_vt2_pd_site1_unit2",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site1_unit2().bits()),
+                &self.delay_num_o_vt2_pd_site1_unit2(),
             )
             .field(
                 "timing_err_vt2_pd_site1_unit2",
-                &format_args!("{}", self.timing_err_vt2_pd_site1_unit2().bit()),
+                &self.timing_err_vt2_pd_site1_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT2_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit2_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit2_vt2_conf2.rs
index fa4cdae989..31273c04b6 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit2_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit2_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT2_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site1_unit2",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site1_unit2().bits()),
+                &self.monitor_edg_mod_vt2_pd_site1_unit2(),
             )
             .field(
                 "delay_ovf_vt2_pd_site1_unit2",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site1_unit2().bit()),
+                &self.delay_ovf_vt2_pd_site1_unit2(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site1_unit2",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site1_unit2().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site1_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT2_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit3_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit3_vt0_conf1.rs
index 28917d1767..f3f3d9a590 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit3_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit3_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT3_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site1_unit3",
-                &format_args!("{}", self.monitor_en_vt0_pd_site1_unit3().bit()),
+                &self.monitor_en_vt0_pd_site1_unit3(),
             )
             .field(
                 "delay_limit_vt0_pd_site1_unit3",
-                &format_args!("{}", self.delay_limit_vt0_pd_site1_unit3().bits()),
+                &self.delay_limit_vt0_pd_site1_unit3(),
             )
             .field(
                 "delay_num_o_vt0_pd_site1_unit3",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site1_unit3().bits()),
+                &self.delay_num_o_vt0_pd_site1_unit3(),
             )
             .field(
                 "timing_err_vt0_pd_site1_unit3",
-                &format_args!("{}", self.timing_err_vt0_pd_site1_unit3().bit()),
+                &self.timing_err_vt0_pd_site1_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT3_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit3_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit3_vt0_conf2.rs
index 2ce3a042ea..7f769f66e3 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit3_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit3_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT3_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site1_unit3",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site1_unit3().bits()),
+                &self.monitor_edg_mod_vt0_pd_site1_unit3(),
             )
             .field(
                 "delay_ovf_vt0_pd_site1_unit3",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site1_unit3().bit()),
+                &self.delay_ovf_vt0_pd_site1_unit3(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site1_unit3",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site1_unit3().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site1_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT3_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit3_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit3_vt1_conf1.rs
index 1888404967..650c58c38a 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit3_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit3_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT3_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site1_unit3",
-                &format_args!("{}", self.monitor_en_vt1_pd_site1_unit3().bit()),
+                &self.monitor_en_vt1_pd_site1_unit3(),
             )
             .field(
                 "delay_limit_vt1_pd_site1_unit3",
-                &format_args!("{}", self.delay_limit_vt1_pd_site1_unit3().bits()),
+                &self.delay_limit_vt1_pd_site1_unit3(),
             )
             .field(
                 "delay_num_o_vt1_pd_site1_unit3",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site1_unit3().bits()),
+                &self.delay_num_o_vt1_pd_site1_unit3(),
             )
             .field(
                 "timing_err_vt1_pd_site1_unit3",
-                &format_args!("{}", self.timing_err_vt1_pd_site1_unit3().bit()),
+                &self.timing_err_vt1_pd_site1_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT3_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit3_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit3_vt1_conf2.rs
index 66e9ba38b8..d603e9f5bb 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit3_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit3_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT3_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site1_unit3",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site1_unit3().bits()),
+                &self.monitor_edg_mod_vt1_pd_site1_unit3(),
             )
             .field(
                 "delay_ovf_vt1_pd_site1_unit3",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site1_unit3().bit()),
+                &self.delay_ovf_vt1_pd_site1_unit3(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site1_unit3",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site1_unit3().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site1_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT3_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit3_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site1_unit3_vt2_conf1.rs
index f7d24951fc..7c3a4d5e62 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit3_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit3_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT3_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site1_unit3",
-                &format_args!("{}", self.monitor_en_vt2_pd_site1_unit3().bit()),
+                &self.monitor_en_vt2_pd_site1_unit3(),
             )
             .field(
                 "delay_limit_vt2_pd_site1_unit3",
-                &format_args!("{}", self.delay_limit_vt2_pd_site1_unit3().bits()),
+                &self.delay_limit_vt2_pd_site1_unit3(),
             )
             .field(
                 "delay_num_o_vt2_pd_site1_unit3",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site1_unit3().bits()),
+                &self.delay_num_o_vt2_pd_site1_unit3(),
             )
             .field(
                 "timing_err_vt2_pd_site1_unit3",
-                &format_args!("{}", self.timing_err_vt2_pd_site1_unit3().bit()),
+                &self.timing_err_vt2_pd_site1_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT3_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site1_unit3_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site1_unit3_vt2_conf2.rs
index 9b8d3af82f..60ea2f1609 100644
--- a/esp32p4/src/pvt/comb_pd_site1_unit3_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site1_unit3_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE1_UNIT3_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site1_unit3",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site1_unit3().bits()),
+                &self.monitor_edg_mod_vt2_pd_site1_unit3(),
             )
             .field(
                 "delay_ovf_vt2_pd_site1_unit3",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site1_unit3().bit()),
+                &self.delay_ovf_vt2_pd_site1_unit3(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site1_unit3",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site1_unit3().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site1_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE1_UNIT3_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit0_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit0_vt0_conf1.rs
index bd7bea0ba8..1f7e4827a4 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit0_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit0_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT0_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site2_unit0",
-                &format_args!("{}", self.monitor_en_vt0_pd_site2_unit0().bit()),
+                &self.monitor_en_vt0_pd_site2_unit0(),
             )
             .field(
                 "delay_limit_vt0_pd_site2_unit0",
-                &format_args!("{}", self.delay_limit_vt0_pd_site2_unit0().bits()),
+                &self.delay_limit_vt0_pd_site2_unit0(),
             )
             .field(
                 "delay_num_o_vt0_pd_site2_unit0",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site2_unit0().bits()),
+                &self.delay_num_o_vt0_pd_site2_unit0(),
             )
             .field(
                 "timing_err_vt0_pd_site2_unit0",
-                &format_args!("{}", self.timing_err_vt0_pd_site2_unit0().bit()),
+                &self.timing_err_vt0_pd_site2_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT0_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit0_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit0_vt0_conf2.rs
index 6691773dc4..1932ab0ad1 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit0_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit0_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT0_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site2_unit0",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site2_unit0().bits()),
+                &self.monitor_edg_mod_vt0_pd_site2_unit0(),
             )
             .field(
                 "delay_ovf_vt0_pd_site2_unit0",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site2_unit0().bit()),
+                &self.delay_ovf_vt0_pd_site2_unit0(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site2_unit0",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site2_unit0().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site2_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT0_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit0_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit0_vt1_conf1.rs
index db97b8d486..301c9efcaa 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit0_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit0_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT0_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site2_unit0",
-                &format_args!("{}", self.monitor_en_vt1_pd_site2_unit0().bit()),
+                &self.monitor_en_vt1_pd_site2_unit0(),
             )
             .field(
                 "delay_limit_vt1_pd_site2_unit0",
-                &format_args!("{}", self.delay_limit_vt1_pd_site2_unit0().bits()),
+                &self.delay_limit_vt1_pd_site2_unit0(),
             )
             .field(
                 "delay_num_o_vt1_pd_site2_unit0",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site2_unit0().bits()),
+                &self.delay_num_o_vt1_pd_site2_unit0(),
             )
             .field(
                 "timing_err_vt1_pd_site2_unit0",
-                &format_args!("{}", self.timing_err_vt1_pd_site2_unit0().bit()),
+                &self.timing_err_vt1_pd_site2_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT0_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit0_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit0_vt1_conf2.rs
index ad0a08245e..112fcf9e91 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit0_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit0_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT0_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site2_unit0",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site2_unit0().bits()),
+                &self.monitor_edg_mod_vt1_pd_site2_unit0(),
             )
             .field(
                 "delay_ovf_vt1_pd_site2_unit0",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site2_unit0().bit()),
+                &self.delay_ovf_vt1_pd_site2_unit0(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site2_unit0",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site2_unit0().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site2_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT0_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit0_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit0_vt2_conf1.rs
index 283398afed..0c1c519908 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit0_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit0_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT0_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site2_unit0",
-                &format_args!("{}", self.monitor_en_vt2_pd_site2_unit0().bit()),
+                &self.monitor_en_vt2_pd_site2_unit0(),
             )
             .field(
                 "delay_limit_vt2_pd_site2_unit0",
-                &format_args!("{}", self.delay_limit_vt2_pd_site2_unit0().bits()),
+                &self.delay_limit_vt2_pd_site2_unit0(),
             )
             .field(
                 "delay_num_o_vt2_pd_site2_unit0",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site2_unit0().bits()),
+                &self.delay_num_o_vt2_pd_site2_unit0(),
             )
             .field(
                 "timing_err_vt2_pd_site2_unit0",
-                &format_args!("{}", self.timing_err_vt2_pd_site2_unit0().bit()),
+                &self.timing_err_vt2_pd_site2_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT0_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit0_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit0_vt2_conf2.rs
index 1452cbfc06..412acc70b9 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit0_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit0_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT0_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site2_unit0",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site2_unit0().bits()),
+                &self.monitor_edg_mod_vt2_pd_site2_unit0(),
             )
             .field(
                 "delay_ovf_vt2_pd_site2_unit0",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site2_unit0().bit()),
+                &self.delay_ovf_vt2_pd_site2_unit0(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site2_unit0",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site2_unit0().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site2_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT0_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit1_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit1_vt0_conf1.rs
index 4bd97e7c87..fda6d41102 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit1_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit1_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT1_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site2_unit1",
-                &format_args!("{}", self.monitor_en_vt0_pd_site2_unit1().bit()),
+                &self.monitor_en_vt0_pd_site2_unit1(),
             )
             .field(
                 "delay_limit_vt0_pd_site2_unit1",
-                &format_args!("{}", self.delay_limit_vt0_pd_site2_unit1().bits()),
+                &self.delay_limit_vt0_pd_site2_unit1(),
             )
             .field(
                 "delay_num_o_vt0_pd_site2_unit1",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site2_unit1().bits()),
+                &self.delay_num_o_vt0_pd_site2_unit1(),
             )
             .field(
                 "timing_err_vt0_pd_site2_unit1",
-                &format_args!("{}", self.timing_err_vt0_pd_site2_unit1().bit()),
+                &self.timing_err_vt0_pd_site2_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT1_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit1_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit1_vt0_conf2.rs
index 301863d745..7b995f8b43 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit1_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit1_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT1_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site2_unit1",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site2_unit1().bits()),
+                &self.monitor_edg_mod_vt0_pd_site2_unit1(),
             )
             .field(
                 "delay_ovf_vt0_pd_site2_unit1",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site2_unit1().bit()),
+                &self.delay_ovf_vt0_pd_site2_unit1(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site2_unit1",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site2_unit1().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site2_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT1_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit1_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit1_vt1_conf1.rs
index fab290fe3a..34ff016a9a 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit1_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit1_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT1_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site2_unit1",
-                &format_args!("{}", self.monitor_en_vt1_pd_site2_unit1().bit()),
+                &self.monitor_en_vt1_pd_site2_unit1(),
             )
             .field(
                 "delay_limit_vt1_pd_site2_unit1",
-                &format_args!("{}", self.delay_limit_vt1_pd_site2_unit1().bits()),
+                &self.delay_limit_vt1_pd_site2_unit1(),
             )
             .field(
                 "delay_num_o_vt1_pd_site2_unit1",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site2_unit1().bits()),
+                &self.delay_num_o_vt1_pd_site2_unit1(),
             )
             .field(
                 "timing_err_vt1_pd_site2_unit1",
-                &format_args!("{}", self.timing_err_vt1_pd_site2_unit1().bit()),
+                &self.timing_err_vt1_pd_site2_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT1_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit1_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit1_vt1_conf2.rs
index 655381bcaa..f2ca2d4d33 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit1_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit1_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT1_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site2_unit1",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site2_unit1().bits()),
+                &self.monitor_edg_mod_vt1_pd_site2_unit1(),
             )
             .field(
                 "delay_ovf_vt1_pd_site2_unit1",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site2_unit1().bit()),
+                &self.delay_ovf_vt1_pd_site2_unit1(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site2_unit1",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site2_unit1().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site2_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT1_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit1_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit1_vt2_conf1.rs
index fc92705895..d372ed846c 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit1_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit1_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT1_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site2_unit1",
-                &format_args!("{}", self.monitor_en_vt2_pd_site2_unit1().bit()),
+                &self.monitor_en_vt2_pd_site2_unit1(),
             )
             .field(
                 "delay_limit_vt2_pd_site2_unit1",
-                &format_args!("{}", self.delay_limit_vt2_pd_site2_unit1().bits()),
+                &self.delay_limit_vt2_pd_site2_unit1(),
             )
             .field(
                 "delay_num_o_vt2_pd_site2_unit1",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site2_unit1().bits()),
+                &self.delay_num_o_vt2_pd_site2_unit1(),
             )
             .field(
                 "timing_err_vt2_pd_site2_unit1",
-                &format_args!("{}", self.timing_err_vt2_pd_site2_unit1().bit()),
+                &self.timing_err_vt2_pd_site2_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT1_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit1_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit1_vt2_conf2.rs
index afd9f3457a..5de9f0be7d 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit1_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit1_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT1_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site2_unit1",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site2_unit1().bits()),
+                &self.monitor_edg_mod_vt2_pd_site2_unit1(),
             )
             .field(
                 "delay_ovf_vt2_pd_site2_unit1",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site2_unit1().bit()),
+                &self.delay_ovf_vt2_pd_site2_unit1(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site2_unit1",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site2_unit1().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site2_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT1_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit2_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit2_vt0_conf1.rs
index 619cc78d75..97bf3b07bc 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit2_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit2_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT2_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site2_unit2",
-                &format_args!("{}", self.monitor_en_vt0_pd_site2_unit2().bit()),
+                &self.monitor_en_vt0_pd_site2_unit2(),
             )
             .field(
                 "delay_limit_vt0_pd_site2_unit2",
-                &format_args!("{}", self.delay_limit_vt0_pd_site2_unit2().bits()),
+                &self.delay_limit_vt0_pd_site2_unit2(),
             )
             .field(
                 "delay_num_o_vt0_pd_site2_unit2",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site2_unit2().bits()),
+                &self.delay_num_o_vt0_pd_site2_unit2(),
             )
             .field(
                 "timing_err_vt0_pd_site2_unit2",
-                &format_args!("{}", self.timing_err_vt0_pd_site2_unit2().bit()),
+                &self.timing_err_vt0_pd_site2_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT2_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit2_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit2_vt0_conf2.rs
index 83cd1588be..6299f652a1 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit2_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit2_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT2_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site2_unit2",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site2_unit2().bits()),
+                &self.monitor_edg_mod_vt0_pd_site2_unit2(),
             )
             .field(
                 "delay_ovf_vt0_pd_site2_unit2",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site2_unit2().bit()),
+                &self.delay_ovf_vt0_pd_site2_unit2(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site2_unit2",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site2_unit2().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site2_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT2_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit2_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit2_vt1_conf1.rs
index 948bf04d45..f48044ce51 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit2_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit2_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT2_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site2_unit2",
-                &format_args!("{}", self.monitor_en_vt1_pd_site2_unit2().bit()),
+                &self.monitor_en_vt1_pd_site2_unit2(),
             )
             .field(
                 "delay_limit_vt1_pd_site2_unit2",
-                &format_args!("{}", self.delay_limit_vt1_pd_site2_unit2().bits()),
+                &self.delay_limit_vt1_pd_site2_unit2(),
             )
             .field(
                 "delay_num_o_vt1_pd_site2_unit2",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site2_unit2().bits()),
+                &self.delay_num_o_vt1_pd_site2_unit2(),
             )
             .field(
                 "timing_err_vt1_pd_site2_unit2",
-                &format_args!("{}", self.timing_err_vt1_pd_site2_unit2().bit()),
+                &self.timing_err_vt1_pd_site2_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT2_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit2_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit2_vt1_conf2.rs
index 4072e6b6bc..5297969bc5 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit2_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit2_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT2_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site2_unit2",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site2_unit2().bits()),
+                &self.monitor_edg_mod_vt1_pd_site2_unit2(),
             )
             .field(
                 "delay_ovf_vt1_pd_site2_unit2",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site2_unit2().bit()),
+                &self.delay_ovf_vt1_pd_site2_unit2(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site2_unit2",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site2_unit2().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site2_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT2_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit2_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit2_vt2_conf1.rs
index d903c2c672..aedb0493e6 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit2_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit2_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT2_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site2_unit2",
-                &format_args!("{}", self.monitor_en_vt2_pd_site2_unit2().bit()),
+                &self.monitor_en_vt2_pd_site2_unit2(),
             )
             .field(
                 "delay_limit_vt2_pd_site2_unit2",
-                &format_args!("{}", self.delay_limit_vt2_pd_site2_unit2().bits()),
+                &self.delay_limit_vt2_pd_site2_unit2(),
             )
             .field(
                 "delay_num_o_vt2_pd_site2_unit2",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site2_unit2().bits()),
+                &self.delay_num_o_vt2_pd_site2_unit2(),
             )
             .field(
                 "timing_err_vt2_pd_site2_unit2",
-                &format_args!("{}", self.timing_err_vt2_pd_site2_unit2().bit()),
+                &self.timing_err_vt2_pd_site2_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT2_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit2_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit2_vt2_conf2.rs
index 585cc8fb7e..a6ba9b1982 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit2_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit2_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT2_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site2_unit2",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site2_unit2().bits()),
+                &self.monitor_edg_mod_vt2_pd_site2_unit2(),
             )
             .field(
                 "delay_ovf_vt2_pd_site2_unit2",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site2_unit2().bit()),
+                &self.delay_ovf_vt2_pd_site2_unit2(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site2_unit2",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site2_unit2().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site2_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT2_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit3_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit3_vt0_conf1.rs
index c414e0f549..c6f68bb7b2 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit3_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit3_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT3_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site2_unit3",
-                &format_args!("{}", self.monitor_en_vt0_pd_site2_unit3().bit()),
+                &self.monitor_en_vt0_pd_site2_unit3(),
             )
             .field(
                 "delay_limit_vt0_pd_site2_unit3",
-                &format_args!("{}", self.delay_limit_vt0_pd_site2_unit3().bits()),
+                &self.delay_limit_vt0_pd_site2_unit3(),
             )
             .field(
                 "delay_num_o_vt0_pd_site2_unit3",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site2_unit3().bits()),
+                &self.delay_num_o_vt0_pd_site2_unit3(),
             )
             .field(
                 "timing_err_vt0_pd_site2_unit3",
-                &format_args!("{}", self.timing_err_vt0_pd_site2_unit3().bit()),
+                &self.timing_err_vt0_pd_site2_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT3_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit3_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit3_vt0_conf2.rs
index e88d5d9dbd..0816aed536 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit3_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit3_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT3_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site2_unit3",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site2_unit3().bits()),
+                &self.monitor_edg_mod_vt0_pd_site2_unit3(),
             )
             .field(
                 "delay_ovf_vt0_pd_site2_unit3",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site2_unit3().bit()),
+                &self.delay_ovf_vt0_pd_site2_unit3(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site2_unit3",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site2_unit3().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site2_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT3_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit3_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit3_vt1_conf1.rs
index 2183702b94..655145bc96 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit3_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit3_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT3_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site2_unit3",
-                &format_args!("{}", self.monitor_en_vt1_pd_site2_unit3().bit()),
+                &self.monitor_en_vt1_pd_site2_unit3(),
             )
             .field(
                 "delay_limit_vt1_pd_site2_unit3",
-                &format_args!("{}", self.delay_limit_vt1_pd_site2_unit3().bits()),
+                &self.delay_limit_vt1_pd_site2_unit3(),
             )
             .field(
                 "delay_num_o_vt1_pd_site2_unit3",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site2_unit3().bits()),
+                &self.delay_num_o_vt1_pd_site2_unit3(),
             )
             .field(
                 "timing_err_vt1_pd_site2_unit3",
-                &format_args!("{}", self.timing_err_vt1_pd_site2_unit3().bit()),
+                &self.timing_err_vt1_pd_site2_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT3_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit3_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit3_vt1_conf2.rs
index b9da1e629b..0c89cf25bf 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit3_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit3_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT3_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site2_unit3",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site2_unit3().bits()),
+                &self.monitor_edg_mod_vt1_pd_site2_unit3(),
             )
             .field(
                 "delay_ovf_vt1_pd_site2_unit3",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site2_unit3().bit()),
+                &self.delay_ovf_vt1_pd_site2_unit3(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site2_unit3",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site2_unit3().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site2_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT3_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit3_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site2_unit3_vt2_conf1.rs
index 14fe5adbe9..943c34d3ec 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit3_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit3_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT3_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site2_unit3",
-                &format_args!("{}", self.monitor_en_vt2_pd_site2_unit3().bit()),
+                &self.monitor_en_vt2_pd_site2_unit3(),
             )
             .field(
                 "delay_limit_vt2_pd_site2_unit3",
-                &format_args!("{}", self.delay_limit_vt2_pd_site2_unit3().bits()),
+                &self.delay_limit_vt2_pd_site2_unit3(),
             )
             .field(
                 "delay_num_o_vt2_pd_site2_unit3",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site2_unit3().bits()),
+                &self.delay_num_o_vt2_pd_site2_unit3(),
             )
             .field(
                 "timing_err_vt2_pd_site2_unit3",
-                &format_args!("{}", self.timing_err_vt2_pd_site2_unit3().bit()),
+                &self.timing_err_vt2_pd_site2_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT3_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site2_unit3_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site2_unit3_vt2_conf2.rs
index 0212e9835d..154835934f 100644
--- a/esp32p4/src/pvt/comb_pd_site2_unit3_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site2_unit3_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE2_UNIT3_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site2_unit3",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site2_unit3().bits()),
+                &self.monitor_edg_mod_vt2_pd_site2_unit3(),
             )
             .field(
                 "delay_ovf_vt2_pd_site2_unit3",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site2_unit3().bit()),
+                &self.delay_ovf_vt2_pd_site2_unit3(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site2_unit3",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site2_unit3().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site2_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE2_UNIT3_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit0_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit0_vt0_conf1.rs
index 24465cbe8b..23479a908b 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit0_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit0_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT0_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site3_unit0",
-                &format_args!("{}", self.monitor_en_vt0_pd_site3_unit0().bit()),
+                &self.monitor_en_vt0_pd_site3_unit0(),
             )
             .field(
                 "delay_limit_vt0_pd_site3_unit0",
-                &format_args!("{}", self.delay_limit_vt0_pd_site3_unit0().bits()),
+                &self.delay_limit_vt0_pd_site3_unit0(),
             )
             .field(
                 "delay_num_o_vt0_pd_site3_unit0",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site3_unit0().bits()),
+                &self.delay_num_o_vt0_pd_site3_unit0(),
             )
             .field(
                 "timing_err_vt0_pd_site3_unit0",
-                &format_args!("{}", self.timing_err_vt0_pd_site3_unit0().bit()),
+                &self.timing_err_vt0_pd_site3_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT0_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit0_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit0_vt0_conf2.rs
index a4b8beb442..fa0c48fb91 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit0_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit0_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT0_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site3_unit0",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site3_unit0().bits()),
+                &self.monitor_edg_mod_vt0_pd_site3_unit0(),
             )
             .field(
                 "delay_ovf_vt0_pd_site3_unit0",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site3_unit0().bit()),
+                &self.delay_ovf_vt0_pd_site3_unit0(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site3_unit0",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site3_unit0().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site3_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT0_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit0_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit0_vt1_conf1.rs
index 802f301410..4b1a2c6da8 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit0_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit0_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT0_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site3_unit0",
-                &format_args!("{}", self.monitor_en_vt1_pd_site3_unit0().bit()),
+                &self.monitor_en_vt1_pd_site3_unit0(),
             )
             .field(
                 "delay_limit_vt1_pd_site3_unit0",
-                &format_args!("{}", self.delay_limit_vt1_pd_site3_unit0().bits()),
+                &self.delay_limit_vt1_pd_site3_unit0(),
             )
             .field(
                 "delay_num_o_vt1_pd_site3_unit0",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site3_unit0().bits()),
+                &self.delay_num_o_vt1_pd_site3_unit0(),
             )
             .field(
                 "timing_err_vt1_pd_site3_unit0",
-                &format_args!("{}", self.timing_err_vt1_pd_site3_unit0().bit()),
+                &self.timing_err_vt1_pd_site3_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT0_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit0_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit0_vt1_conf2.rs
index a90496c6d3..e3e560ff40 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit0_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit0_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT0_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site3_unit0",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site3_unit0().bits()),
+                &self.monitor_edg_mod_vt1_pd_site3_unit0(),
             )
             .field(
                 "delay_ovf_vt1_pd_site3_unit0",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site3_unit0().bit()),
+                &self.delay_ovf_vt1_pd_site3_unit0(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site3_unit0",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site3_unit0().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site3_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT0_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit0_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit0_vt2_conf1.rs
index badd08e37f..ba4b1a571b 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit0_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit0_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT0_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site3_unit0",
-                &format_args!("{}", self.monitor_en_vt2_pd_site3_unit0().bit()),
+                &self.monitor_en_vt2_pd_site3_unit0(),
             )
             .field(
                 "delay_limit_vt2_pd_site3_unit0",
-                &format_args!("{}", self.delay_limit_vt2_pd_site3_unit0().bits()),
+                &self.delay_limit_vt2_pd_site3_unit0(),
             )
             .field(
                 "delay_num_o_vt2_pd_site3_unit0",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site3_unit0().bits()),
+                &self.delay_num_o_vt2_pd_site3_unit0(),
             )
             .field(
                 "timing_err_vt2_pd_site3_unit0",
-                &format_args!("{}", self.timing_err_vt2_pd_site3_unit0().bit()),
+                &self.timing_err_vt2_pd_site3_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT0_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit0_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit0_vt2_conf2.rs
index 76ab35f3ce..92041d5abf 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit0_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit0_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT0_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site3_unit0",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site3_unit0().bits()),
+                &self.monitor_edg_mod_vt2_pd_site3_unit0(),
             )
             .field(
                 "delay_ovf_vt2_pd_site3_unit0",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site3_unit0().bit()),
+                &self.delay_ovf_vt2_pd_site3_unit0(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site3_unit0",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site3_unit0().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site3_unit0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT0_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit1_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit1_vt0_conf1.rs
index 5587db8399..8806132e9b 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit1_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit1_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT1_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site3_unit1",
-                &format_args!("{}", self.monitor_en_vt0_pd_site3_unit1().bit()),
+                &self.monitor_en_vt0_pd_site3_unit1(),
             )
             .field(
                 "delay_limit_vt0_pd_site3_unit1",
-                &format_args!("{}", self.delay_limit_vt0_pd_site3_unit1().bits()),
+                &self.delay_limit_vt0_pd_site3_unit1(),
             )
             .field(
                 "delay_num_o_vt0_pd_site3_unit1",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site3_unit1().bits()),
+                &self.delay_num_o_vt0_pd_site3_unit1(),
             )
             .field(
                 "timing_err_vt0_pd_site3_unit1",
-                &format_args!("{}", self.timing_err_vt0_pd_site3_unit1().bit()),
+                &self.timing_err_vt0_pd_site3_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT1_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit1_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit1_vt0_conf2.rs
index b279c61ede..deb5ede164 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit1_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit1_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT1_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site3_unit1",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site3_unit1().bits()),
+                &self.monitor_edg_mod_vt0_pd_site3_unit1(),
             )
             .field(
                 "delay_ovf_vt0_pd_site3_unit1",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site3_unit1().bit()),
+                &self.delay_ovf_vt0_pd_site3_unit1(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site3_unit1",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site3_unit1().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site3_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT1_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit1_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit1_vt1_conf1.rs
index 0f8b0bf0e9..98ad216e71 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit1_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit1_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT1_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site3_unit1",
-                &format_args!("{}", self.monitor_en_vt1_pd_site3_unit1().bit()),
+                &self.monitor_en_vt1_pd_site3_unit1(),
             )
             .field(
                 "delay_limit_vt1_pd_site3_unit1",
-                &format_args!("{}", self.delay_limit_vt1_pd_site3_unit1().bits()),
+                &self.delay_limit_vt1_pd_site3_unit1(),
             )
             .field(
                 "delay_num_o_vt1_pd_site3_unit1",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site3_unit1().bits()),
+                &self.delay_num_o_vt1_pd_site3_unit1(),
             )
             .field(
                 "timing_err_vt1_pd_site3_unit1",
-                &format_args!("{}", self.timing_err_vt1_pd_site3_unit1().bit()),
+                &self.timing_err_vt1_pd_site3_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT1_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit1_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit1_vt1_conf2.rs
index 6b3369528c..05dbe04b8f 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit1_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit1_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT1_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site3_unit1",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site3_unit1().bits()),
+                &self.monitor_edg_mod_vt1_pd_site3_unit1(),
             )
             .field(
                 "delay_ovf_vt1_pd_site3_unit1",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site3_unit1().bit()),
+                &self.delay_ovf_vt1_pd_site3_unit1(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site3_unit1",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site3_unit1().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site3_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT1_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit1_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit1_vt2_conf1.rs
index f08b36ba1b..43ef494916 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit1_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit1_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT1_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site3_unit1",
-                &format_args!("{}", self.monitor_en_vt2_pd_site3_unit1().bit()),
+                &self.monitor_en_vt2_pd_site3_unit1(),
             )
             .field(
                 "delay_limit_vt2_pd_site3_unit1",
-                &format_args!("{}", self.delay_limit_vt2_pd_site3_unit1().bits()),
+                &self.delay_limit_vt2_pd_site3_unit1(),
             )
             .field(
                 "delay_num_o_vt2_pd_site3_unit1",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site3_unit1().bits()),
+                &self.delay_num_o_vt2_pd_site3_unit1(),
             )
             .field(
                 "timing_err_vt2_pd_site3_unit1",
-                &format_args!("{}", self.timing_err_vt2_pd_site3_unit1().bit()),
+                &self.timing_err_vt2_pd_site3_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT1_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit1_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit1_vt2_conf2.rs
index 37fda1944c..32272cd9e3 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit1_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit1_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT1_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site3_unit1",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site3_unit1().bits()),
+                &self.monitor_edg_mod_vt2_pd_site3_unit1(),
             )
             .field(
                 "delay_ovf_vt2_pd_site3_unit1",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site3_unit1().bit()),
+                &self.delay_ovf_vt2_pd_site3_unit1(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site3_unit1",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site3_unit1().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site3_unit1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT1_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit2_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit2_vt0_conf1.rs
index 918c702a1e..3507e6100c 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit2_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit2_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT2_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site3_unit2",
-                &format_args!("{}", self.monitor_en_vt0_pd_site3_unit2().bit()),
+                &self.monitor_en_vt0_pd_site3_unit2(),
             )
             .field(
                 "delay_limit_vt0_pd_site3_unit2",
-                &format_args!("{}", self.delay_limit_vt0_pd_site3_unit2().bits()),
+                &self.delay_limit_vt0_pd_site3_unit2(),
             )
             .field(
                 "delay_num_o_vt0_pd_site3_unit2",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site3_unit2().bits()),
+                &self.delay_num_o_vt0_pd_site3_unit2(),
             )
             .field(
                 "timing_err_vt0_pd_site3_unit2",
-                &format_args!("{}", self.timing_err_vt0_pd_site3_unit2().bit()),
+                &self.timing_err_vt0_pd_site3_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT2_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit2_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit2_vt0_conf2.rs
index 5271d0b2bd..b7c1ce441f 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit2_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit2_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT2_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site3_unit2",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site3_unit2().bits()),
+                &self.monitor_edg_mod_vt0_pd_site3_unit2(),
             )
             .field(
                 "delay_ovf_vt0_pd_site3_unit2",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site3_unit2().bit()),
+                &self.delay_ovf_vt0_pd_site3_unit2(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site3_unit2",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site3_unit2().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site3_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT2_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit2_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit2_vt1_conf1.rs
index 8310554014..cc2989da02 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit2_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit2_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT2_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site3_unit2",
-                &format_args!("{}", self.monitor_en_vt1_pd_site3_unit2().bit()),
+                &self.monitor_en_vt1_pd_site3_unit2(),
             )
             .field(
                 "delay_limit_vt1_pd_site3_unit2",
-                &format_args!("{}", self.delay_limit_vt1_pd_site3_unit2().bits()),
+                &self.delay_limit_vt1_pd_site3_unit2(),
             )
             .field(
                 "delay_num_o_vt1_pd_site3_unit2",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site3_unit2().bits()),
+                &self.delay_num_o_vt1_pd_site3_unit2(),
             )
             .field(
                 "timing_err_vt1_pd_site3_unit2",
-                &format_args!("{}", self.timing_err_vt1_pd_site3_unit2().bit()),
+                &self.timing_err_vt1_pd_site3_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT2_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit2_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit2_vt1_conf2.rs
index 3ec863f4ac..e172a7a0b5 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit2_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit2_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT2_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site3_unit2",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site3_unit2().bits()),
+                &self.monitor_edg_mod_vt1_pd_site3_unit2(),
             )
             .field(
                 "delay_ovf_vt1_pd_site3_unit2",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site3_unit2().bit()),
+                &self.delay_ovf_vt1_pd_site3_unit2(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site3_unit2",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site3_unit2().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site3_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT2_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit2_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit2_vt2_conf1.rs
index 941aa4e336..12041c36d8 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit2_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit2_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT2_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site3_unit2",
-                &format_args!("{}", self.monitor_en_vt2_pd_site3_unit2().bit()),
+                &self.monitor_en_vt2_pd_site3_unit2(),
             )
             .field(
                 "delay_limit_vt2_pd_site3_unit2",
-                &format_args!("{}", self.delay_limit_vt2_pd_site3_unit2().bits()),
+                &self.delay_limit_vt2_pd_site3_unit2(),
             )
             .field(
                 "delay_num_o_vt2_pd_site3_unit2",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site3_unit2().bits()),
+                &self.delay_num_o_vt2_pd_site3_unit2(),
             )
             .field(
                 "timing_err_vt2_pd_site3_unit2",
-                &format_args!("{}", self.timing_err_vt2_pd_site3_unit2().bit()),
+                &self.timing_err_vt2_pd_site3_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT2_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit2_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit2_vt2_conf2.rs
index 0eb0d6ed8e..5248c51339 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit2_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit2_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT2_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site3_unit2",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site3_unit2().bits()),
+                &self.monitor_edg_mod_vt2_pd_site3_unit2(),
             )
             .field(
                 "delay_ovf_vt2_pd_site3_unit2",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site3_unit2().bit()),
+                &self.delay_ovf_vt2_pd_site3_unit2(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site3_unit2",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site3_unit2().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site3_unit2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT2_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit3_vt0_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit3_vt0_conf1.rs
index 8464982ef4..44db88e8ab 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit3_vt0_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit3_vt0_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT3_VT0_CONF1")
             .field(
                 "monitor_en_vt0_pd_site3_unit3",
-                &format_args!("{}", self.monitor_en_vt0_pd_site3_unit3().bit()),
+                &self.monitor_en_vt0_pd_site3_unit3(),
             )
             .field(
                 "delay_limit_vt0_pd_site3_unit3",
-                &format_args!("{}", self.delay_limit_vt0_pd_site3_unit3().bits()),
+                &self.delay_limit_vt0_pd_site3_unit3(),
             )
             .field(
                 "delay_num_o_vt0_pd_site3_unit3",
-                &format_args!("{}", self.delay_num_o_vt0_pd_site3_unit3().bits()),
+                &self.delay_num_o_vt0_pd_site3_unit3(),
             )
             .field(
                 "timing_err_vt0_pd_site3_unit3",
-                &format_args!("{}", self.timing_err_vt0_pd_site3_unit3().bit()),
+                &self.timing_err_vt0_pd_site3_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT3_VT0_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit3_vt0_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit3_vt0_conf2.rs
index cfd880405c..646bd4a3e9 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit3_vt0_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit3_vt0_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT3_VT0_CONF2")
             .field(
                 "monitor_edg_mod_vt0_pd_site3_unit3",
-                &format_args!("{}", self.monitor_edg_mod_vt0_pd_site3_unit3().bits()),
+                &self.monitor_edg_mod_vt0_pd_site3_unit3(),
             )
             .field(
                 "delay_ovf_vt0_pd_site3_unit3",
-                &format_args!("{}", self.delay_ovf_vt0_pd_site3_unit3().bit()),
+                &self.delay_ovf_vt0_pd_site3_unit3(),
             )
             .field(
                 "timing_err_cnt_o_vt0_pd_site3_unit3",
-                &format_args!("{}", self.timing_err_cnt_o_vt0_pd_site3_unit3().bits()),
+                &self.timing_err_cnt_o_vt0_pd_site3_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT3_VT0_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit3_vt1_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit3_vt1_conf1.rs
index 886393db35..d42733c7bf 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit3_vt1_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit3_vt1_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT3_VT1_CONF1")
             .field(
                 "monitor_en_vt1_pd_site3_unit3",
-                &format_args!("{}", self.monitor_en_vt1_pd_site3_unit3().bit()),
+                &self.monitor_en_vt1_pd_site3_unit3(),
             )
             .field(
                 "delay_limit_vt1_pd_site3_unit3",
-                &format_args!("{}", self.delay_limit_vt1_pd_site3_unit3().bits()),
+                &self.delay_limit_vt1_pd_site3_unit3(),
             )
             .field(
                 "delay_num_o_vt1_pd_site3_unit3",
-                &format_args!("{}", self.delay_num_o_vt1_pd_site3_unit3().bits()),
+                &self.delay_num_o_vt1_pd_site3_unit3(),
             )
             .field(
                 "timing_err_vt1_pd_site3_unit3",
-                &format_args!("{}", self.timing_err_vt1_pd_site3_unit3().bit()),
+                &self.timing_err_vt1_pd_site3_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT3_VT1_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit3_vt1_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit3_vt1_conf2.rs
index aae8d6f090..69eaceaad8 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit3_vt1_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit3_vt1_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT3_VT1_CONF2")
             .field(
                 "monitor_edg_mod_vt1_pd_site3_unit3",
-                &format_args!("{}", self.monitor_edg_mod_vt1_pd_site3_unit3().bits()),
+                &self.monitor_edg_mod_vt1_pd_site3_unit3(),
             )
             .field(
                 "delay_ovf_vt1_pd_site3_unit3",
-                &format_args!("{}", self.delay_ovf_vt1_pd_site3_unit3().bit()),
+                &self.delay_ovf_vt1_pd_site3_unit3(),
             )
             .field(
                 "timing_err_cnt_o_vt1_pd_site3_unit3",
-                &format_args!("{}", self.timing_err_cnt_o_vt1_pd_site3_unit3().bits()),
+                &self.timing_err_cnt_o_vt1_pd_site3_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT3_VT1_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit3_vt2_conf1.rs b/esp32p4/src/pvt/comb_pd_site3_unit3_vt2_conf1.rs
index b16b48b6da..bf6203ccd5 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit3_vt2_conf1.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit3_vt2_conf1.rs
@@ -44,29 +44,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT3_VT2_CONF1")
             .field(
                 "monitor_en_vt2_pd_site3_unit3",
-                &format_args!("{}", self.monitor_en_vt2_pd_site3_unit3().bit()),
+                &self.monitor_en_vt2_pd_site3_unit3(),
             )
             .field(
                 "delay_limit_vt2_pd_site3_unit3",
-                &format_args!("{}", self.delay_limit_vt2_pd_site3_unit3().bits()),
+                &self.delay_limit_vt2_pd_site3_unit3(),
             )
             .field(
                 "delay_num_o_vt2_pd_site3_unit3",
-                &format_args!("{}", self.delay_num_o_vt2_pd_site3_unit3().bits()),
+                &self.delay_num_o_vt2_pd_site3_unit3(),
             )
             .field(
                 "timing_err_vt2_pd_site3_unit3",
-                &format_args!("{}", self.timing_err_vt2_pd_site3_unit3().bit()),
+                &self.timing_err_vt2_pd_site3_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT3_VT2_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/comb_pd_site3_unit3_vt2_conf2.rs b/esp32p4/src/pvt/comb_pd_site3_unit3_vt2_conf2.rs
index d33dda4ba8..43d53657af 100644
--- a/esp32p4/src/pvt/comb_pd_site3_unit3_vt2_conf2.rs
+++ b/esp32p4/src/pvt/comb_pd_site3_unit3_vt2_conf2.rs
@@ -33,25 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PD_SITE3_UNIT3_VT2_CONF2")
             .field(
                 "monitor_edg_mod_vt2_pd_site3_unit3",
-                &format_args!("{}", self.monitor_edg_mod_vt2_pd_site3_unit3().bits()),
+                &self.monitor_edg_mod_vt2_pd_site3_unit3(),
             )
             .field(
                 "delay_ovf_vt2_pd_site3_unit3",
-                &format_args!("{}", self.delay_ovf_vt2_pd_site3_unit3().bit()),
+                &self.delay_ovf_vt2_pd_site3_unit3(),
             )
             .field(
                 "timing_err_cnt_o_vt2_pd_site3_unit3",
-                &format_args!("{}", self.timing_err_cnt_o_vt2_pd_site3_unit3().bits()),
+                &self.timing_err_cnt_o_vt2_pd_site3_unit3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PD_SITE3_UNIT3_VT2_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/date.rs b/esp32p4/src/pvt/date.rs
index 8f34a2a388..acc79c6bbb 100644
--- a/esp32p4/src/pvt/date.rs
+++ b/esp32p4/src/pvt/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/pvt/dbias_channel0_sel.rs b/esp32p4/src/pvt/dbias_channel0_sel.rs
index 3d27f29e32..5d0ba9137a 100644
--- a/esp32p4/src/pvt/dbias_channel0_sel.rs
+++ b/esp32p4/src/pvt/dbias_channel0_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBIAS_CHANNEL0_SEL")
-            .field(
-                "dbias_channel0_cfg",
-                &format_args!("{}", self.dbias_channel0_cfg().bits()),
-            )
+            .field("dbias_channel0_cfg", &self.dbias_channel0_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBIAS_CHANNEL0_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:16 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/dbias_channel1_sel.rs b/esp32p4/src/pvt/dbias_channel1_sel.rs
index 74c7aa6e67..e45ecfd66b 100644
--- a/esp32p4/src/pvt/dbias_channel1_sel.rs
+++ b/esp32p4/src/pvt/dbias_channel1_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBIAS_CHANNEL1_SEL")
-            .field(
-                "dbias_channel1_cfg",
-                &format_args!("{}", self.dbias_channel1_cfg().bits()),
-            )
+            .field("dbias_channel1_cfg", &self.dbias_channel1_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBIAS_CHANNEL1_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:16 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/dbias_channel2_sel.rs b/esp32p4/src/pvt/dbias_channel2_sel.rs
index c9c893edc3..fea1ce4976 100644
--- a/esp32p4/src/pvt/dbias_channel2_sel.rs
+++ b/esp32p4/src/pvt/dbias_channel2_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBIAS_CHANNEL2_SEL")
-            .field(
-                "dbias_channel2_cfg",
-                &format_args!("{}", self.dbias_channel2_cfg().bits()),
-            )
+            .field("dbias_channel2_cfg", &self.dbias_channel2_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBIAS_CHANNEL2_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:16 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/dbias_channel3_sel.rs b/esp32p4/src/pvt/dbias_channel3_sel.rs
index 6b126a6be4..548c661e3d 100644
--- a/esp32p4/src/pvt/dbias_channel3_sel.rs
+++ b/esp32p4/src/pvt/dbias_channel3_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBIAS_CHANNEL3_SEL")
-            .field(
-                "dbias_channel3_cfg",
-                &format_args!("{}", self.dbias_channel3_cfg().bits()),
-            )
+            .field("dbias_channel3_cfg", &self.dbias_channel3_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBIAS_CHANNEL3_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:16 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/dbias_channel4_sel.rs b/esp32p4/src/pvt/dbias_channel4_sel.rs
index b93ccf447b..26809912ca 100644
--- a/esp32p4/src/pvt/dbias_channel4_sel.rs
+++ b/esp32p4/src/pvt/dbias_channel4_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBIAS_CHANNEL4_SEL")
-            .field(
-                "dbias_channel4_cfg",
-                &format_args!("{}", self.dbias_channel4_cfg().bits()),
-            )
+            .field("dbias_channel4_cfg", &self.dbias_channel4_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBIAS_CHANNEL4_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:16 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/dbias_channel_sel0.rs b/esp32p4/src/pvt/dbias_channel_sel0.rs
index 482b43697a..89fb4ade00 100644
--- a/esp32p4/src/pvt/dbias_channel_sel0.rs
+++ b/esp32p4/src/pvt/dbias_channel_sel0.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBIAS_CHANNEL_SEL0")
-            .field(
-                "dbias_channel3_sel",
-                &format_args!("{}", self.dbias_channel3_sel().bits()),
-            )
-            .field(
-                "dbias_channel2_sel",
-                &format_args!("{}", self.dbias_channel2_sel().bits()),
-            )
-            .field(
-                "dbias_channel1_sel",
-                &format_args!("{}", self.dbias_channel1_sel().bits()),
-            )
-            .field(
-                "dbias_channel0_sel",
-                &format_args!("{}", self.dbias_channel0_sel().bits()),
-            )
+            .field("dbias_channel3_sel", &self.dbias_channel3_sel())
+            .field("dbias_channel2_sel", &self.dbias_channel2_sel())
+            .field("dbias_channel1_sel", &self.dbias_channel1_sel())
+            .field("dbias_channel0_sel", &self.dbias_channel0_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBIAS_CHANNEL_SEL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 4:10 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/dbias_channel_sel1.rs b/esp32p4/src/pvt/dbias_channel_sel1.rs
index 381e21fe46..59273bd00a 100644
--- a/esp32p4/src/pvt/dbias_channel_sel1.rs
+++ b/esp32p4/src/pvt/dbias_channel_sel1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBIAS_CHANNEL_SEL1")
-            .field(
-                "dbias_channel4_sel",
-                &format_args!("{}", self.dbias_channel4_sel().bits()),
-            )
+            .field("dbias_channel4_sel", &self.dbias_channel4_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBIAS_CHANNEL_SEL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 25:31 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/dbias_cmd0.rs b/esp32p4/src/pvt/dbias_cmd0.rs
index be89b5bf70..5365055d01 100644
--- a/esp32p4/src/pvt/dbias_cmd0.rs
+++ b/esp32p4/src/pvt/dbias_cmd0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBIAS_CMD0")
-            .field("dbias_cmd0", &format_args!("{}", self.dbias_cmd0().bits()))
+            .field("dbias_cmd0", &self.dbias_cmd0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBIAS_CMD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:16 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/dbias_cmd1.rs b/esp32p4/src/pvt/dbias_cmd1.rs
index b02622bad6..0bb1c349fb 100644
--- a/esp32p4/src/pvt/dbias_cmd1.rs
+++ b/esp32p4/src/pvt/dbias_cmd1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBIAS_CMD1")
-            .field("dbias_cmd1", &format_args!("{}", self.dbias_cmd1().bits()))
+            .field("dbias_cmd1", &self.dbias_cmd1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBIAS_CMD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:16 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/dbias_cmd2.rs b/esp32p4/src/pvt/dbias_cmd2.rs
index 381224d707..0d2d676695 100644
--- a/esp32p4/src/pvt/dbias_cmd2.rs
+++ b/esp32p4/src/pvt/dbias_cmd2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBIAS_CMD2")
-            .field("dbias_cmd2", &format_args!("{}", self.dbias_cmd2().bits()))
+            .field("dbias_cmd2", &self.dbias_cmd2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBIAS_CMD2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:16 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/dbias_cmd3.rs b/esp32p4/src/pvt/dbias_cmd3.rs
index 20528a67f4..70c2538ebe 100644
--- a/esp32p4/src/pvt/dbias_cmd3.rs
+++ b/esp32p4/src/pvt/dbias_cmd3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBIAS_CMD3")
-            .field("dbias_cmd3", &format_args!("{}", self.dbias_cmd3().bits()))
+            .field("dbias_cmd3", &self.dbias_cmd3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBIAS_CMD3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:16 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/dbias_cmd4.rs b/esp32p4/src/pvt/dbias_cmd4.rs
index 696ab0b8df..680afbc021 100644
--- a/esp32p4/src/pvt/dbias_cmd4.rs
+++ b/esp32p4/src/pvt/dbias_cmd4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBIAS_CMD4")
-            .field("dbias_cmd4", &format_args!("{}", self.dbias_cmd4().bits()))
+            .field("dbias_cmd4", &self.dbias_cmd4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBIAS_CMD4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:16 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/dbias_timer.rs b/esp32p4/src/pvt/dbias_timer.rs
index b4e7fa08ef..feeb21865c 100644
--- a/esp32p4/src/pvt/dbias_timer.rs
+++ b/esp32p4/src/pvt/dbias_timer.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBIAS_TIMER")
-            .field(
-                "timer_target",
-                &format_args!("{}", self.timer_target().bits()),
-            )
-            .field("timer_en", &format_args!("{}", self.timer_en().bit()))
+            .field("timer_target", &self.timer_target())
+            .field("timer_en", &self.timer_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBIAS_TIMER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 15:30 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/pmup_bitmap_high0.rs b/esp32p4/src/pvt/pmup_bitmap_high0.rs
index 2d98d33d59..86e0ac4076 100644
--- a/esp32p4/src/pvt/pmup_bitmap_high0.rs
+++ b/esp32p4/src/pvt/pmup_bitmap_high0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMUP_BITMAP_HIGH0")
-            .field(
-                "pump_bitmap_high0",
-                &format_args!("{}", self.pump_bitmap_high0().bits()),
-            )
+            .field("pump_bitmap_high0", &self.pump_bitmap_high0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMUP_BITMAP_HIGH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - select valid high channel0"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/pmup_bitmap_high1.rs b/esp32p4/src/pvt/pmup_bitmap_high1.rs
index 8a387c8c4b..18cd941d8c 100644
--- a/esp32p4/src/pvt/pmup_bitmap_high1.rs
+++ b/esp32p4/src/pvt/pmup_bitmap_high1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMUP_BITMAP_HIGH1")
-            .field(
-                "pump_bitmap_high1",
-                &format_args!("{}", self.pump_bitmap_high1().bits()),
-            )
+            .field("pump_bitmap_high1", &self.pump_bitmap_high1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMUP_BITMAP_HIGH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - select valid high channel1"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/pmup_bitmap_high2.rs b/esp32p4/src/pvt/pmup_bitmap_high2.rs
index c51a497dfd..89b5cbfbe6 100644
--- a/esp32p4/src/pvt/pmup_bitmap_high2.rs
+++ b/esp32p4/src/pvt/pmup_bitmap_high2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMUP_BITMAP_HIGH2")
-            .field(
-                "pump_bitmap_high2",
-                &format_args!("{}", self.pump_bitmap_high2().bits()),
-            )
+            .field("pump_bitmap_high2", &self.pump_bitmap_high2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMUP_BITMAP_HIGH2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - select valid high channel2"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/pmup_bitmap_high3.rs b/esp32p4/src/pvt/pmup_bitmap_high3.rs
index 22e7223e81..f759e87677 100644
--- a/esp32p4/src/pvt/pmup_bitmap_high3.rs
+++ b/esp32p4/src/pvt/pmup_bitmap_high3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMUP_BITMAP_HIGH3")
-            .field(
-                "pump_bitmap_high3",
-                &format_args!("{}", self.pump_bitmap_high3().bits()),
-            )
+            .field("pump_bitmap_high3", &self.pump_bitmap_high3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMUP_BITMAP_HIGH3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - select valid high channel3"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/pmup_bitmap_high4.rs b/esp32p4/src/pvt/pmup_bitmap_high4.rs
index 5dc7a28091..780752e102 100644
--- a/esp32p4/src/pvt/pmup_bitmap_high4.rs
+++ b/esp32p4/src/pvt/pmup_bitmap_high4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMUP_BITMAP_HIGH4")
-            .field(
-                "pump_bitmap_high4",
-                &format_args!("{}", self.pump_bitmap_high4().bits()),
-            )
+            .field("pump_bitmap_high4", &self.pump_bitmap_high4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMUP_BITMAP_HIGH4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - select valid high channel4"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/pmup_bitmap_low0.rs b/esp32p4/src/pvt/pmup_bitmap_low0.rs
index a0f91a687d..369c2a7a53 100644
--- a/esp32p4/src/pvt/pmup_bitmap_low0.rs
+++ b/esp32p4/src/pvt/pmup_bitmap_low0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMUP_BITMAP_LOW0")
-            .field(
-                "pump_bitmap_low0",
-                &format_args!("{}", self.pump_bitmap_low0().bits()),
-            )
+            .field("pump_bitmap_low0", &self.pump_bitmap_low0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMUP_BITMAP_LOW0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - select valid low channel0"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/pmup_bitmap_low1.rs b/esp32p4/src/pvt/pmup_bitmap_low1.rs
index 040f5c7277..f9f0bdb65a 100644
--- a/esp32p4/src/pvt/pmup_bitmap_low1.rs
+++ b/esp32p4/src/pvt/pmup_bitmap_low1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMUP_BITMAP_LOW1")
-            .field(
-                "pump_bitmap_low1",
-                &format_args!("{}", self.pump_bitmap_low1().bits()),
-            )
+            .field("pump_bitmap_low1", &self.pump_bitmap_low1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMUP_BITMAP_LOW1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - select valid low channel1"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/pmup_bitmap_low2.rs b/esp32p4/src/pvt/pmup_bitmap_low2.rs
index 1f77bc78e1..a94af8b8a6 100644
--- a/esp32p4/src/pvt/pmup_bitmap_low2.rs
+++ b/esp32p4/src/pvt/pmup_bitmap_low2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMUP_BITMAP_LOW2")
-            .field(
-                "pump_bitmap_low2",
-                &format_args!("{}", self.pump_bitmap_low2().bits()),
-            )
+            .field("pump_bitmap_low2", &self.pump_bitmap_low2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMUP_BITMAP_LOW2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - select valid low channel2"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/pmup_bitmap_low3.rs b/esp32p4/src/pvt/pmup_bitmap_low3.rs
index f956a0e518..217455a84b 100644
--- a/esp32p4/src/pvt/pmup_bitmap_low3.rs
+++ b/esp32p4/src/pvt/pmup_bitmap_low3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMUP_BITMAP_LOW3")
-            .field(
-                "pump_bitmap_low3",
-                &format_args!("{}", self.pump_bitmap_low3().bits()),
-            )
+            .field("pump_bitmap_low3", &self.pump_bitmap_low3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMUP_BITMAP_LOW3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - select valid low channel3"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/pmup_bitmap_low4.rs b/esp32p4/src/pvt/pmup_bitmap_low4.rs
index 425d297cfb..0bfb12cfc4 100644
--- a/esp32p4/src/pvt/pmup_bitmap_low4.rs
+++ b/esp32p4/src/pvt/pmup_bitmap_low4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMUP_BITMAP_LOW4")
-            .field(
-                "pump_bitmap_low4",
-                &format_args!("{}", self.pump_bitmap_low4().bits()),
-            )
+            .field("pump_bitmap_low4", &self.pump_bitmap_low4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMUP_BITMAP_LOW4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - select valid low channel4"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/pmup_channel_cfg.rs b/esp32p4/src/pvt/pmup_channel_cfg.rs
index 773356ee7f..e260198439 100644
--- a/esp32p4/src/pvt/pmup_channel_cfg.rs
+++ b/esp32p4/src/pvt/pmup_channel_cfg.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMUP_CHANNEL_CFG")
-            .field(
-                "pump_channel_code4",
-                &format_args!("{}", self.pump_channel_code4().bits()),
-            )
-            .field(
-                "pump_channel_code3",
-                &format_args!("{}", self.pump_channel_code3().bits()),
-            )
-            .field(
-                "pump_channel_code2",
-                &format_args!("{}", self.pump_channel_code2().bits()),
-            )
-            .field(
-                "pump_channel_code1",
-                &format_args!("{}", self.pump_channel_code1().bits()),
-            )
-            .field(
-                "pump_channel_code0",
-                &format_args!("{}", self.pump_channel_code0().bits()),
-            )
+            .field("pump_channel_code4", &self.pump_channel_code4())
+            .field("pump_channel_code3", &self.pump_channel_code3())
+            .field("pump_channel_code2", &self.pump_channel_code2())
+            .field("pump_channel_code1", &self.pump_channel_code1())
+            .field("pump_channel_code0", &self.pump_channel_code0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMUP_CHANNEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 7:11 - configure cmd4 code"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/pmup_drv_cfg.rs b/esp32p4/src/pvt/pmup_drv_cfg.rs
index 2c5b93f501..456b9b596a 100644
--- a/esp32p4/src/pvt/pmup_drv_cfg.rs
+++ b/esp32p4/src/pvt/pmup_drv_cfg.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMUP_DRV_CFG")
-            .field("pump_en", &format_args!("{}", self.pump_en().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("pump_drv4", &format_args!("{}", self.pump_drv4().bits()))
-            .field("pump_drv3", &format_args!("{}", self.pump_drv3().bits()))
-            .field("pump_drv2", &format_args!("{}", self.pump_drv2().bits()))
-            .field("pump_drv1", &format_args!("{}", self.pump_drv1().bits()))
-            .field("pump_drv0", &format_args!("{}", self.pump_drv0().bits()))
+            .field("pump_en", &self.pump_en())
+            .field("clk_en", &self.clk_en())
+            .field("pump_drv4", &self.pump_drv4())
+            .field("pump_drv3", &self.pump_drv3())
+            .field("pump_drv2", &self.pump_drv2())
+            .field("pump_drv1", &self.pump_drv1())
+            .field("pump_drv0", &self.pump_drv0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMUP_DRV_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - configure pvt charge xpd"]
     #[inline(always)]
diff --git a/esp32p4/src/pvt/value_update.rs b/esp32p4/src/pvt/value_update.rs
index 933de9bf00..2308a6dcd1 100644
--- a/esp32p4/src/pvt/value_update.rs
+++ b/esp32p4/src/pvt/value_update.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VALUE_UPDATE")
-            .field("bypass", &format_args!("{}", self.bypass().bit()))
+            .field("bypass", &self.bypass())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VALUE_UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - needs field desc"]
     #[inline(always)]
diff --git a/esp32p4/src/rmt/ch_rx_carrier_rm.rs b/esp32p4/src/rmt/ch_rx_carrier_rm.rs
index a04a297412..466db8fbd1 100644
--- a/esp32p4/src/rmt/ch_rx_carrier_rm.rs
+++ b/esp32p4/src/rmt/ch_rx_carrier_rm.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_CARRIER_RM")
-            .field(
-                "carrier_low_thres_ch",
-                &format_args!("{}", self.carrier_low_thres_ch().bits()),
-            )
-            .field(
-                "carrier_high_thres_ch",
-                &format_args!("{}", self.carrier_high_thres_ch().bits()),
-            )
+            .field("carrier_low_thres_ch", &self.carrier_low_thres_ch())
+            .field("carrier_high_thres_ch", &self.carrier_high_thres_ch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_CARRIER_RM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s."]
     #[inline(always)]
diff --git a/esp32p4/src/rmt/ch_rx_lim.rs b/esp32p4/src/rmt/ch_rx_lim.rs
index f08015a1f5..78e9a1afb0 100644
--- a/esp32p4/src/rmt/ch_rx_lim.rs
+++ b/esp32p4/src/rmt/ch_rx_lim.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_LIM")
-            .field("rx_lim_ch4", &format_args!("{}", self.rx_lim_ch4().bits()))
+            .field("rx_lim_ch4", &self.rx_lim_ch4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_LIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can receive."]
     #[inline(always)]
diff --git a/esp32p4/src/rmt/ch_tx_lim.rs b/esp32p4/src/rmt/ch_tx_lim.rs
index 00f214f102..507e6b4c43 100644
--- a/esp32p4/src/rmt/ch_tx_lim.rs
+++ b/esp32p4/src/rmt/ch_tx_lim.rs
@@ -46,28 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_TX_LIM")
-            .field("tx_lim_ch", &format_args!("{}", self.tx_lim_ch().bits()))
-            .field(
-                "tx_loop_num_ch",
-                &format_args!("{}", self.tx_loop_num_ch().bits()),
-            )
-            .field(
-                "tx_loop_cnt_en_ch",
-                &format_args!("{}", self.tx_loop_cnt_en_ch().bit()),
-            )
-            .field(
-                "loop_stop_en_ch",
-                &format_args!("{}", self.loop_stop_en_ch().bit()),
-            )
+            .field("tx_lim_ch", &self.tx_lim_ch())
+            .field("tx_loop_num_ch", &self.tx_loop_num_ch())
+            .field("tx_loop_cnt_en_ch", &self.tx_loop_cnt_en_ch())
+            .field("loop_stop_en_ch", &self.loop_stop_en_ch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_TX_LIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can send out."]
     #[inline(always)]
diff --git a/esp32p4/src/rmt/chcarrier_duty.rs b/esp32p4/src/rmt/chcarrier_duty.rs
index 38cf6fc52c..af196857c6 100644
--- a/esp32p4/src/rmt/chcarrier_duty.rs
+++ b/esp32p4/src/rmt/chcarrier_duty.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHCARRIER_DUTY")
-            .field(
-                "carrier_low_ch",
-                &format_args!("{}", self.carrier_low_ch().bits()),
-            )
-            .field(
-                "carrier_high_ch",
-                &format_args!("{}", self.carrier_high_ch().bits()),
-            )
+            .field("carrier_low_ch", &self.carrier_low_ch())
+            .field("carrier_high_ch", &self.carrier_high_ch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHCARRIER_DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure carrier wave 's low level clock period for CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32p4/src/rmt/date.rs b/esp32p4/src/rmt/date.rs
index 99c4573ee6..aef587291c 100644
--- a/esp32p4/src/rmt/date.rs
+++ b/esp32p4/src/rmt/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/rmt/int_ena.rs b/esp32p4/src/rmt/int_ena.rs
index d1e936b243..a9dbba2c5c 100644
--- a/esp32p4/src/rmt/int_ena.rs
+++ b/esp32p4/src/rmt/int_ena.rs
@@ -278,75 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_tx_end", &format_args!("{}", self.ch2_tx_end().bit()))
-            .field("ch3_tx_end", &format_args!("{}", self.ch3_tx_end().bit()))
-            .field("tx_ch0_err", &format_args!("{}", self.tx_ch0_err().bit()))
-            .field("tx_ch1_err", &format_args!("{}", self.tx_ch1_err().bit()))
-            .field("tx_ch2_err", &format_args!("{}", self.tx_ch2_err().bit()))
-            .field("tx_ch3_err", &format_args!("{}", self.tx_ch3_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_tx_thr_event",
-                &format_args!("{}", self.ch2_tx_thr_event().bit()),
-            )
-            .field(
-                "ch3_tx_thr_event",
-                &format_args!("{}", self.ch3_tx_thr_event().bit()),
-            )
-            .field("ch0_tx_loop", &format_args!("{}", self.ch0_tx_loop().bit()))
-            .field("ch1_tx_loop", &format_args!("{}", self.ch1_tx_loop().bit()))
-            .field("ch2_tx_loop", &format_args!("{}", self.ch2_tx_loop().bit()))
-            .field("ch3_tx_loop", &format_args!("{}", self.ch3_tx_loop().bit()))
-            .field("ch4_rx_end", &format_args!("{}", self.ch4_rx_end().bit()))
-            .field("ch5_rx_end", &format_args!("{}", self.ch5_rx_end().bit()))
-            .field("ch6_rx_end", &format_args!("{}", self.ch6_rx_end().bit()))
-            .field("ch7_rx_end", &format_args!("{}", self.ch7_rx_end().bit()))
-            .field("ch4_err", &format_args!("{}", self.ch4_err().bit()))
-            .field("ch5_err", &format_args!("{}", self.ch5_err().bit()))
-            .field("ch6_err", &format_args!("{}", self.ch6_err().bit()))
-            .field("ch7_err", &format_args!("{}", self.ch7_err().bit()))
-            .field(
-                "ch4_rx_thr_event",
-                &format_args!("{}", self.ch4_rx_thr_event().bit()),
-            )
-            .field(
-                "ch5_rx_thr_event",
-                &format_args!("{}", self.ch5_rx_thr_event().bit()),
-            )
-            .field(
-                "ch6_rx_thr_event",
-                &format_args!("{}", self.ch6_rx_thr_event().bit()),
-            )
-            .field(
-                "ch7_rx_thr_event",
-                &format_args!("{}", self.ch7_rx_thr_event().bit()),
-            )
-            .field(
-                "tx_ch3_dma_access_fail",
-                &format_args!("{}", self.tx_ch3_dma_access_fail().bit()),
-            )
-            .field(
-                "rx_ch7_dma_access_fail",
-                &format_args!("{}", self.rx_ch7_dma_access_fail().bit()),
-            )
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_tx_end", &self.ch2_tx_end())
+            .field("ch3_tx_end", &self.ch3_tx_end())
+            .field("tx_ch0_err", &self.tx_ch0_err())
+            .field("tx_ch1_err", &self.tx_ch1_err())
+            .field("tx_ch2_err", &self.tx_ch2_err())
+            .field("tx_ch3_err", &self.tx_ch3_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_tx_thr_event", &self.ch2_tx_thr_event())
+            .field("ch3_tx_thr_event", &self.ch3_tx_thr_event())
+            .field("ch0_tx_loop", &self.ch0_tx_loop())
+            .field("ch1_tx_loop", &self.ch1_tx_loop())
+            .field("ch2_tx_loop", &self.ch2_tx_loop())
+            .field("ch3_tx_loop", &self.ch3_tx_loop())
+            .field("ch4_rx_end", &self.ch4_rx_end())
+            .field("ch5_rx_end", &self.ch5_rx_end())
+            .field("ch6_rx_end", &self.ch6_rx_end())
+            .field("ch7_rx_end", &self.ch7_rx_end())
+            .field("ch4_err", &self.ch4_err())
+            .field("ch5_err", &self.ch5_err())
+            .field("ch6_err", &self.ch6_err())
+            .field("ch7_err", &self.ch7_err())
+            .field("ch4_rx_thr_event", &self.ch4_rx_thr_event())
+            .field("ch5_rx_thr_event", &self.ch5_rx_thr_event())
+            .field("ch6_rx_thr_event", &self.ch6_rx_thr_event())
+            .field("ch7_rx_thr_event", &self.ch7_rx_thr_event())
+            .field("tx_ch3_dma_access_fail", &self.tx_ch3_dma_access_fail())
+            .field("rx_ch7_dma_access_fail", &self.rx_ch7_dma_access_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for CH0_TX_END_INT."]
     #[inline(always)]
diff --git a/esp32p4/src/rmt/int_raw.rs b/esp32p4/src/rmt/int_raw.rs
index 09df5f13be..72531fb559 100644
--- a/esp32p4/src/rmt/int_raw.rs
+++ b/esp32p4/src/rmt/int_raw.rs
@@ -278,75 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_tx_end", &format_args!("{}", self.ch2_tx_end().bit()))
-            .field("ch3_tx_end", &format_args!("{}", self.ch3_tx_end().bit()))
-            .field("tx_ch0_err", &format_args!("{}", self.tx_ch0_err().bit()))
-            .field("tx_ch1_err", &format_args!("{}", self.tx_ch1_err().bit()))
-            .field("tx_ch2_err", &format_args!("{}", self.tx_ch2_err().bit()))
-            .field("tx_ch3_err", &format_args!("{}", self.tx_ch3_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_tx_thr_event",
-                &format_args!("{}", self.ch2_tx_thr_event().bit()),
-            )
-            .field(
-                "ch3_tx_thr_event",
-                &format_args!("{}", self.ch3_tx_thr_event().bit()),
-            )
-            .field("ch0_tx_loop", &format_args!("{}", self.ch0_tx_loop().bit()))
-            .field("ch1_tx_loop", &format_args!("{}", self.ch1_tx_loop().bit()))
-            .field("ch2_tx_loop", &format_args!("{}", self.ch2_tx_loop().bit()))
-            .field("ch3_tx_loop", &format_args!("{}", self.ch3_tx_loop().bit()))
-            .field("ch4_rx_end", &format_args!("{}", self.ch4_rx_end().bit()))
-            .field("ch5_rx_end", &format_args!("{}", self.ch5_rx_end().bit()))
-            .field("ch6_rx_end", &format_args!("{}", self.ch6_rx_end().bit()))
-            .field("ch7_rx_end", &format_args!("{}", self.ch7_rx_end().bit()))
-            .field("rx_ch4_err", &format_args!("{}", self.rx_ch4_err().bit()))
-            .field("rx_ch5_err", &format_args!("{}", self.rx_ch5_err().bit()))
-            .field("rx_ch6_err", &format_args!("{}", self.rx_ch6_err().bit()))
-            .field("rx_ch7_err", &format_args!("{}", self.rx_ch7_err().bit()))
-            .field(
-                "ch4_rx_thr_event",
-                &format_args!("{}", self.ch4_rx_thr_event().bit()),
-            )
-            .field(
-                "ch5_rx_thr_event",
-                &format_args!("{}", self.ch5_rx_thr_event().bit()),
-            )
-            .field(
-                "ch6_rx_thr_event",
-                &format_args!("{}", self.ch6_rx_thr_event().bit()),
-            )
-            .field(
-                "ch7_rx_thr_event",
-                &format_args!("{}", self.ch7_rx_thr_event().bit()),
-            )
-            .field(
-                "tx_ch3_dma_access_fail",
-                &format_args!("{}", self.tx_ch3_dma_access_fail().bit()),
-            )
-            .field(
-                "rx_ch7_dma_access_fail",
-                &format_args!("{}", self.rx_ch7_dma_access_fail().bit()),
-            )
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_tx_end", &self.ch2_tx_end())
+            .field("ch3_tx_end", &self.ch3_tx_end())
+            .field("tx_ch0_err", &self.tx_ch0_err())
+            .field("tx_ch1_err", &self.tx_ch1_err())
+            .field("tx_ch2_err", &self.tx_ch2_err())
+            .field("tx_ch3_err", &self.tx_ch3_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_tx_thr_event", &self.ch2_tx_thr_event())
+            .field("ch3_tx_thr_event", &self.ch3_tx_thr_event())
+            .field("ch0_tx_loop", &self.ch0_tx_loop())
+            .field("ch1_tx_loop", &self.ch1_tx_loop())
+            .field("ch2_tx_loop", &self.ch2_tx_loop())
+            .field("ch3_tx_loop", &self.ch3_tx_loop())
+            .field("ch4_rx_end", &self.ch4_rx_end())
+            .field("ch5_rx_end", &self.ch5_rx_end())
+            .field("ch6_rx_end", &self.ch6_rx_end())
+            .field("ch7_rx_end", &self.ch7_rx_end())
+            .field("rx_ch4_err", &self.rx_ch4_err())
+            .field("rx_ch5_err", &self.rx_ch5_err())
+            .field("rx_ch6_err", &self.rx_ch6_err())
+            .field("rx_ch7_err", &self.rx_ch7_err())
+            .field("ch4_rx_thr_event", &self.ch4_rx_thr_event())
+            .field("ch5_rx_thr_event", &self.ch5_rx_thr_event())
+            .field("ch6_rx_thr_event", &self.ch6_rx_thr_event())
+            .field("ch7_rx_thr_event", &self.ch7_rx_thr_event())
+            .field("tx_ch3_dma_access_fail", &self.tx_ch3_dma_access_fail())
+            .field("rx_ch7_dma_access_fail", &self.rx_ch7_dma_access_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt raw bit for CHANNEL0. Triggered when transmission done."]
     #[inline(always)]
diff --git a/esp32p4/src/rmt/int_st.rs b/esp32p4/src/rmt/int_st.rs
index cc5ce85641..255ff75287 100644
--- a/esp32p4/src/rmt/int_st.rs
+++ b/esp32p4/src/rmt/int_st.rs
@@ -216,75 +216,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_tx_end", &format_args!("{}", self.ch2_tx_end().bit()))
-            .field("ch3_tx_end", &format_args!("{}", self.ch3_tx_end().bit()))
-            .field("tx_ch0_err", &format_args!("{}", self.tx_ch0_err().bit()))
-            .field("tx_ch1_err", &format_args!("{}", self.tx_ch1_err().bit()))
-            .field("tx_ch2_err", &format_args!("{}", self.tx_ch2_err().bit()))
-            .field("tx_ch3_err", &format_args!("{}", self.tx_ch3_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_tx_thr_event",
-                &format_args!("{}", self.ch2_tx_thr_event().bit()),
-            )
-            .field(
-                "ch3_tx_thr_event",
-                &format_args!("{}", self.ch3_tx_thr_event().bit()),
-            )
-            .field("ch0_tx_loop", &format_args!("{}", self.ch0_tx_loop().bit()))
-            .field("ch1_tx_loop", &format_args!("{}", self.ch1_tx_loop().bit()))
-            .field("ch2_tx_loop", &format_args!("{}", self.ch2_tx_loop().bit()))
-            .field("ch3_tx_loop", &format_args!("{}", self.ch3_tx_loop().bit()))
-            .field("ch4_rx_end", &format_args!("{}", self.ch4_rx_end().bit()))
-            .field("ch5_rx_end", &format_args!("{}", self.ch5_rx_end().bit()))
-            .field("ch6_rx_end", &format_args!("{}", self.ch6_rx_end().bit()))
-            .field("ch7_rx_end", &format_args!("{}", self.ch7_rx_end().bit()))
-            .field("rx_ch4_err", &format_args!("{}", self.rx_ch4_err().bit()))
-            .field("rx_ch5_err", &format_args!("{}", self.rx_ch5_err().bit()))
-            .field("rx_ch6_err", &format_args!("{}", self.rx_ch6_err().bit()))
-            .field("rx_ch7_err", &format_args!("{}", self.rx_ch7_err().bit()))
-            .field(
-                "ch4_rx_thr_event",
-                &format_args!("{}", self.ch4_rx_thr_event().bit()),
-            )
-            .field(
-                "ch5_rx_thr_event",
-                &format_args!("{}", self.ch5_rx_thr_event().bit()),
-            )
-            .field(
-                "ch6_rx_thr_event",
-                &format_args!("{}", self.ch6_rx_thr_event().bit()),
-            )
-            .field(
-                "ch7_rx_thr_event",
-                &format_args!("{}", self.ch7_rx_thr_event().bit()),
-            )
-            .field(
-                "tx_ch3_dma_access_fail",
-                &format_args!("{}", self.tx_ch3_dma_access_fail().bit()),
-            )
-            .field(
-                "rx_ch7_dma_access_fail",
-                &format_args!("{}", self.rx_ch7_dma_access_fail().bit()),
-            )
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_tx_end", &self.ch2_tx_end())
+            .field("ch3_tx_end", &self.ch3_tx_end())
+            .field("tx_ch0_err", &self.tx_ch0_err())
+            .field("tx_ch1_err", &self.tx_ch1_err())
+            .field("tx_ch2_err", &self.tx_ch2_err())
+            .field("tx_ch3_err", &self.tx_ch3_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_tx_thr_event", &self.ch2_tx_thr_event())
+            .field("ch3_tx_thr_event", &self.ch3_tx_thr_event())
+            .field("ch0_tx_loop", &self.ch0_tx_loop())
+            .field("ch1_tx_loop", &self.ch1_tx_loop())
+            .field("ch2_tx_loop", &self.ch2_tx_loop())
+            .field("ch3_tx_loop", &self.ch3_tx_loop())
+            .field("ch4_rx_end", &self.ch4_rx_end())
+            .field("ch5_rx_end", &self.ch5_rx_end())
+            .field("ch6_rx_end", &self.ch6_rx_end())
+            .field("ch7_rx_end", &self.ch7_rx_end())
+            .field("rx_ch4_err", &self.rx_ch4_err())
+            .field("rx_ch5_err", &self.rx_ch5_err())
+            .field("rx_ch6_err", &self.rx_ch6_err())
+            .field("rx_ch7_err", &self.rx_ch7_err())
+            .field("ch4_rx_thr_event", &self.ch4_rx_thr_event())
+            .field("ch5_rx_thr_event", &self.ch5_rx_thr_event())
+            .field("ch6_rx_thr_event", &self.ch6_rx_thr_event())
+            .field("ch7_rx_thr_event", &self.ch7_rx_thr_event())
+            .field("tx_ch3_dma_access_fail", &self.tx_ch3_dma_access_fail())
+            .field("rx_ch7_dma_access_fail", &self.rx_ch7_dma_access_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/rmt/rx_chconf0.rs b/esp32p4/src/rmt/rx_chconf0.rs
index 0723741cee..5e5a0bb18f 100644
--- a/esp32p4/src/rmt/rx_chconf0.rs
+++ b/esp32p4/src/rmt/rx_chconf0.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CHCONF0")
-            .field(
-                "div_cnt_ch4",
-                &format_args!("{}", self.div_cnt_ch4().bits()),
-            )
-            .field(
-                "idle_thres_ch4",
-                &format_args!("{}", self.idle_thres_ch4().bits()),
-            )
-            .field(
-                "mem_size_ch4",
-                &format_args!("{}", self.mem_size_ch4().bits()),
-            )
-            .field(
-                "carrier_en_ch4",
-                &format_args!("{}", self.carrier_en_ch4().bit()),
-            )
-            .field(
-                "carrier_out_lv_ch4",
-                &format_args!("{}", self.carrier_out_lv_ch4().bit()),
-            )
+            .field("div_cnt_ch4", &self.div_cnt_ch4())
+            .field("idle_thres_ch4", &self.idle_thres_ch4())
+            .field("mem_size_ch4", &self.mem_size_ch4())
+            .field("carrier_en_ch4", &self.carrier_en_ch4())
+            .field("carrier_out_lv_ch4", &self.carrier_out_lv_ch4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CHCONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the divider for clock of CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32p4/src/rmt/rx_chconf1.rs b/esp32p4/src/rmt/rx_chconf1.rs
index 9a3592d220..3c82684d8f 100644
--- a/esp32p4/src/rmt/rx_chconf1.rs
+++ b/esp32p4/src/rmt/rx_chconf1.rs
@@ -61,32 +61,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CHCONF1")
-            .field("rx_en_ch4", &format_args!("{}", self.rx_en_ch4().bit()))
-            .field(
-                "mem_owner_ch4",
-                &format_args!("{}", self.mem_owner_ch4().bit()),
-            )
-            .field(
-                "rx_filter_en_ch4",
-                &format_args!("{}", self.rx_filter_en_ch4().bit()),
-            )
-            .field(
-                "rx_filter_thres_ch4",
-                &format_args!("{}", self.rx_filter_thres_ch4().bits()),
-            )
-            .field(
-                "mem_rx_wrap_en_ch4",
-                &format_args!("{}", self.mem_rx_wrap_en_ch4().bit()),
-            )
+            .field("rx_en_ch4", &self.rx_en_ch4())
+            .field("mem_owner_ch4", &self.mem_owner_ch4())
+            .field("rx_filter_en_ch4", &self.rx_filter_en_ch4())
+            .field("rx_filter_thres_ch4", &self.rx_filter_thres_ch4())
+            .field("mem_rx_wrap_en_ch4", &self.mem_rx_wrap_en_ch4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CHCONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable receiver to receive data on CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32p4/src/rmt/rx_chdata.rs b/esp32p4/src/rmt/rx_chdata.rs
index d93e246de7..6a2dc514e0 100644
--- a/esp32p4/src/rmt/rx_chdata.rs
+++ b/esp32p4/src/rmt/rx_chdata.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CHDATA")
-            .field("chdata", &format_args!("{}", self.chdata().bits()))
+            .field("chdata", &self.chdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CHDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The read and write data register for CHANNEL$n by apb fifo access.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_chdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_CHDATA_SPEC;
 impl crate::RegisterSpec for RX_CHDATA_SPEC {
diff --git a/esp32p4/src/rmt/rx_chstatus.rs b/esp32p4/src/rmt/rx_chstatus.rs
index 06c93b29ae..a1d72c9a7e 100644
--- a/esp32p4/src/rmt/rx_chstatus.rs
+++ b/esp32p4/src/rmt/rx_chstatus.rs
@@ -48,36 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CHSTATUS")
-            .field(
-                "mem_waddr_ex_ch4",
-                &format_args!("{}", self.mem_waddr_ex_ch4().bits()),
-            )
-            .field(
-                "apb_mem_raddr_ch4",
-                &format_args!("{}", self.apb_mem_raddr_ch4().bits()),
-            )
-            .field("state_ch4", &format_args!("{}", self.state_ch4().bits()))
-            .field(
-                "mem_owner_err_ch4",
-                &format_args!("{}", self.mem_owner_err_ch4().bit()),
-            )
-            .field(
-                "mem_full_ch4",
-                &format_args!("{}", self.mem_full_ch4().bit()),
-            )
-            .field(
-                "apb_mem_rd_err_ch4",
-                &format_args!("{}", self.apb_mem_rd_err_ch4().bit()),
-            )
+            .field("mem_waddr_ex_ch4", &self.mem_waddr_ex_ch4())
+            .field("apb_mem_raddr_ch4", &self.apb_mem_raddr_ch4())
+            .field("state_ch4", &self.state_ch4())
+            .field("mem_owner_err_ch4", &self.mem_owner_err_ch4())
+            .field("mem_full_ch4", &self.mem_full_ch4())
+            .field("apb_mem_rd_err_ch4", &self.apb_mem_rd_err_ch4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CHSTATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Channel %s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_chstatus::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_CHSTATUS_SPEC;
 impl crate::RegisterSpec for RX_CHSTATUS_SPEC {
diff --git a/esp32p4/src/rmt/sys_conf.rs b/esp32p4/src/rmt/sys_conf.rs
index 1f3ab91f43..15129494c2 100644
--- a/esp32p4/src/rmt/sys_conf.rs
+++ b/esp32p4/src/rmt/sys_conf.rs
@@ -98,40 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYS_CONF")
-            .field(
-                "apb_fifo_mask",
-                &format_args!("{}", self.apb_fifo_mask().bit()),
-            )
-            .field(
-                "mem_clk_force_on",
-                &format_args!("{}", self.mem_clk_force_on().bit()),
-            )
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bits()))
-            .field("sclk_active", &format_args!("{}", self.sclk_active().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("apb_fifo_mask", &self.apb_fifo_mask())
+            .field("mem_clk_force_on", &self.mem_clk_force_on())
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_active", &self.sclk_active())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'h1: access memory directly. 1'h0: access memory by FIFO."]
     #[inline(always)]
diff --git a/esp32p4/src/rmt/tx_chconf0.rs b/esp32p4/src/rmt/tx_chconf0.rs
index a0dc3e475a..40c8ecaa3d 100644
--- a/esp32p4/src/rmt/tx_chconf0.rs
+++ b/esp32p4/src/rmt/tx_chconf0.rs
@@ -108,52 +108,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CHCONF0")
-            .field(
-                "tx_conti_mode_ch0",
-                &format_args!("{}", self.tx_conti_mode_ch0().bit()),
-            )
-            .field(
-                "mem_tx_wrap_en_ch0",
-                &format_args!("{}", self.mem_tx_wrap_en_ch0().bit()),
-            )
-            .field(
-                "idle_out_lv_ch0",
-                &format_args!("{}", self.idle_out_lv_ch0().bit()),
-            )
-            .field(
-                "idle_out_en_ch0",
-                &format_args!("{}", self.idle_out_en_ch0().bit()),
-            )
-            .field("tx_stop_ch0", &format_args!("{}", self.tx_stop_ch0().bit()))
-            .field(
-                "div_cnt_ch0",
-                &format_args!("{}", self.div_cnt_ch0().bits()),
-            )
-            .field(
-                "mem_size_ch0",
-                &format_args!("{}", self.mem_size_ch0().bits()),
-            )
-            .field(
-                "carrier_eff_en_ch0",
-                &format_args!("{}", self.carrier_eff_en_ch0().bit()),
-            )
-            .field(
-                "carrier_en_ch0",
-                &format_args!("{}", self.carrier_en_ch0().bit()),
-            )
-            .field(
-                "carrier_out_lv_ch0",
-                &format_args!("{}", self.carrier_out_lv_ch0().bit()),
-            )
+            .field("tx_conti_mode_ch0", &self.tx_conti_mode_ch0())
+            .field("mem_tx_wrap_en_ch0", &self.mem_tx_wrap_en_ch0())
+            .field("idle_out_lv_ch0", &self.idle_out_lv_ch0())
+            .field("idle_out_en_ch0", &self.idle_out_en_ch0())
+            .field("tx_stop_ch0", &self.tx_stop_ch0())
+            .field("div_cnt_ch0", &self.div_cnt_ch0())
+            .field("mem_size_ch0", &self.mem_size_ch0())
+            .field("carrier_eff_en_ch0", &self.carrier_eff_en_ch0())
+            .field("carrier_en_ch0", &self.carrier_en_ch0())
+            .field("carrier_out_lv_ch0", &self.carrier_out_lv_ch0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CHCONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to start sending data on CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32p4/src/rmt/tx_chdata.rs b/esp32p4/src/rmt/tx_chdata.rs
index dd89c19a79..3f4858899e 100644
--- a/esp32p4/src/rmt/tx_chdata.rs
+++ b/esp32p4/src/rmt/tx_chdata.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CHDATA")
-            .field("chdata", &format_args!("{}", self.chdata().bits()))
+            .field("chdata", &self.chdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CHDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The read and write data register for CHANNEL%s by apb fifo access.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_chdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TX_CHDATA_SPEC;
 impl crate::RegisterSpec for TX_CHDATA_SPEC {
diff --git a/esp32p4/src/rmt/tx_chstatus.rs b/esp32p4/src/rmt/tx_chstatus.rs
index fffc9d1db7..c002a88d8f 100644
--- a/esp32p4/src/rmt/tx_chstatus.rs
+++ b/esp32p4/src/rmt/tx_chstatus.rs
@@ -41,32 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CHSTATUS")
-            .field(
-                "mem_raddr_ex_ch0",
-                &format_args!("{}", self.mem_raddr_ex_ch0().bits()),
-            )
-            .field(
-                "apb_mem_waddr_ch0",
-                &format_args!("{}", self.apb_mem_waddr_ch0().bits()),
-            )
-            .field("state_ch0", &format_args!("{}", self.state_ch0().bits()))
-            .field(
-                "mem_empty_ch0",
-                &format_args!("{}", self.mem_empty_ch0().bit()),
-            )
-            .field(
-                "apb_mem_wr_err_ch0",
-                &format_args!("{}", self.apb_mem_wr_err_ch0().bit()),
-            )
+            .field("mem_raddr_ex_ch0", &self.mem_raddr_ex_ch0())
+            .field("apb_mem_waddr_ch0", &self.apb_mem_waddr_ch0())
+            .field("state_ch0", &self.state_ch0())
+            .field("mem_empty_ch0", &self.mem_empty_ch0())
+            .field("apb_mem_wr_err_ch0", &self.apb_mem_wr_err_ch0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CHSTATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Channel %s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_chstatus::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TX_CHSTATUS_SPEC;
 impl crate::RegisterSpec for TX_CHSTATUS_SPEC {
diff --git a/esp32p4/src/rmt/tx_sim.rs b/esp32p4/src/rmt/tx_sim.rs
index b76a424751..fa17898d18 100644
--- a/esp32p4/src/rmt/tx_sim.rs
+++ b/esp32p4/src/rmt/tx_sim.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_SIM")
-            .field("ch0", &format_args!("{}", self.ch0().bit()))
-            .field("ch1", &format_args!("{}", self.ch1().bit()))
-            .field("ch2", &format_args!("{}", self.ch2().bit()))
-            .field("ch3", &format_args!("{}", self.ch3().bit()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("ch0", &self.ch0())
+            .field("ch1", &self.ch1())
+            .field("ch2", &self.ch2())
+            .field("ch3", &self.ch3())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_SIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels."]
     #[inline(always)]
diff --git a/esp32p4/src/rsa/constant_time.rs b/esp32p4/src/rsa/constant_time.rs
index 843789ba32..2638b8415a 100644
--- a/esp32p4/src/rsa/constant_time.rs
+++ b/esp32p4/src/rsa/constant_time.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONSTANT_TIME")
-            .field(
-                "constant_time",
-                &format_args!("{}", self.constant_time().bit()),
-            )
+            .field("constant_time", &self.constant_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONSTANT_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures the constant_time option. 0: Acceleration 1: No acceleration (default)"]
     #[inline(always)]
diff --git a/esp32p4/src/rsa/date.rs b/esp32p4/src/rsa/date.rs
index 1eee4833d1..9a33aff7a7 100644
--- a/esp32p4/src/rsa/date.rs
+++ b/esp32p4/src/rsa/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/rsa/int_ena.rs b/esp32p4/src/rsa/int_ena.rs
index f1ce51b819..1782ceda85 100644
--- a/esp32p4/src/rsa/int_ena.rs
+++ b/esp32p4/src/rsa/int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("int_ena", &format_args!("{}", self.int_ena().bit()))
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to enable the RSA interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/rsa/m_mem.rs b/esp32p4/src/rsa/m_mem.rs
index f889cb91cf..cdddfe42b8 100644
--- a/esp32p4/src/rsa/m_mem.rs
+++ b/esp32p4/src/rsa/m_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Represents M\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct M_MEM_SPEC;
diff --git a/esp32p4/src/rsa/m_prime.rs b/esp32p4/src/rsa/m_prime.rs
index 33fae2142f..56f959cc98 100644
--- a/esp32p4/src/rsa/m_prime.rs
+++ b/esp32p4/src/rsa/m_prime.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("M_PRIME")
-            .field("m_prime", &format_args!("{}", self.m_prime().bits()))
+            .field("m_prime", &self.m_prime())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_PRIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Represents M’"]
     #[inline(always)]
diff --git a/esp32p4/src/rsa/mode.rs b/esp32p4/src/rsa/mode.rs
index db479d6a09..7bdd4fe50f 100644
--- a/esp32p4/src/rsa/mode.rs
+++ b/esp32p4/src/rsa/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/rsa/query_clean.rs b/esp32p4/src/rsa/query_clean.rs
index b777d7ed18..200fde38af 100644
--- a/esp32p4/src/rsa/query_clean.rs
+++ b/esp32p4/src/rsa/query_clean.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_CLEAN")
-            .field("query_clean", &format_args!("{}", self.query_clean().bit()))
+            .field("query_clean", &self.query_clean())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_CLEAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RSA clean register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_clean::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_CLEAN_SPEC;
 impl crate::RegisterSpec for QUERY_CLEAN_SPEC {
diff --git a/esp32p4/src/rsa/query_idle.rs b/esp32p4/src/rsa/query_idle.rs
index 494d76973a..0fa4c50db2 100644
--- a/esp32p4/src/rsa/query_idle.rs
+++ b/esp32p4/src/rsa/query_idle.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_IDLE")
-            .field("query_idle", &format_args!("{}", self.query_idle().bit()))
+            .field("query_idle", &self.query_idle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_IDLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Represents the RSA status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_idle::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_IDLE_SPEC;
 impl crate::RegisterSpec for QUERY_IDLE_SPEC {
diff --git a/esp32p4/src/rsa/search_enable.rs b/esp32p4/src/rsa/search_enable.rs
index a08c68f820..1965337ac2 100644
--- a/esp32p4/src/rsa/search_enable.rs
+++ b/esp32p4/src/rsa/search_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEARCH_ENABLE")
-            .field(
-                "search_enable",
-                &format_args!("{}", self.search_enable().bit()),
-            )
+            .field("search_enable", &self.search_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEARCH_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configure the search option. 0: No acceleration (default) 1: Acceleration This option should be used together with RSA_SEARCH_POS."]
     #[inline(always)]
diff --git a/esp32p4/src/rsa/search_pos.rs b/esp32p4/src/rsa/search_pos.rs
index 0f1e4cd9e1..defcfe53d8 100644
--- a/esp32p4/src/rsa/search_pos.rs
+++ b/esp32p4/src/rsa/search_pos.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEARCH_POS")
-            .field("search_pos", &format_args!("{}", self.search_pos().bits()))
+            .field("search_pos", &self.search_pos())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEARCH_POS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high."]
     #[inline(always)]
diff --git a/esp32p4/src/rsa/x_mem.rs b/esp32p4/src/rsa/x_mem.rs
index edcf1cf0c4..122f41e2e1 100644
--- a/esp32p4/src/rsa/x_mem.rs
+++ b/esp32p4/src/rsa/x_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<X_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Represents X\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`x_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`x_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct X_MEM_SPEC;
diff --git a/esp32p4/src/rsa/y_mem.rs b/esp32p4/src/rsa/y_mem.rs
index c687cd0a52..fe33d71507 100644
--- a/esp32p4/src/rsa/y_mem.rs
+++ b/esp32p4/src/rsa/y_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Y_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Represents Y\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Y_MEM_SPEC;
diff --git a/esp32p4/src/rsa/z_mem.rs b/esp32p4/src/rsa/z_mem.rs
index 6826e9d664..5bee6c1785 100644
--- a/esp32p4/src/rsa/z_mem.rs
+++ b/esp32p4/src/rsa/z_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Z_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Represents Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Z_MEM_SPEC;
diff --git a/esp32p4/src/sdhost/blksiz.rs b/esp32p4/src/sdhost/blksiz.rs
index 661464ff62..cc43139dce 100644
--- a/esp32p4/src/sdhost/blksiz.rs
+++ b/esp32p4/src/sdhost/blksiz.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLKSIZ")
-            .field("block_size", &format_args!("{}", self.block_size().bits()))
+            .field("block_size", &self.block_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLKSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Block size."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/bmod.rs b/esp32p4/src/sdhost/bmod.rs
index 84e024e84c..40bf525ef2 100644
--- a/esp32p4/src/sdhost/bmod.rs
+++ b/esp32p4/src/sdhost/bmod.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BMOD")
-            .field("swr", &format_args!("{}", self.swr().bit()))
-            .field("fb", &format_args!("{}", self.fb().bit()))
-            .field("de", &format_args!("{}", self.de().bit()))
-            .field("pbl", &format_args!("{}", self.pbl().bits()))
+            .field("swr", &self.swr())
+            .field("fb", &self.fb())
+            .field("de", &self.de())
+            .field("pbl", &self.pbl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BMOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/bufaddr.rs b/esp32p4/src/sdhost/bufaddr.rs
index 720082ccb4..432972a890 100644
--- a/esp32p4/src/sdhost/bufaddr.rs
+++ b/esp32p4/src/sdhost/bufaddr.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUFADDR")
-            .field("bufaddr", &format_args!("{}", self.bufaddr().bits()))
+            .field("bufaddr", &self.bufaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUFADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Host buffer address pointer register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bufaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUFADDR_SPEC;
 impl crate::RegisterSpec for BUFADDR_SPEC {
diff --git a/esp32p4/src/sdhost/buffifo.rs b/esp32p4/src/sdhost/buffifo.rs
index fad83364df..75e09b3936 100644
--- a/esp32p4/src/sdhost/buffifo.rs
+++ b/esp32p4/src/sdhost/buffifo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUFFIFO")
-            .field("buffifo", &format_args!("{}", self.buffifo().bits()))
+            .field("buffifo", &self.buffifo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUFFIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - CPU write and read transmit data by FIFO. This register points to the current Data FIFO ."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/bytcnt.rs b/esp32p4/src/sdhost/bytcnt.rs
index af93408fdf..fed252d44c 100644
--- a/esp32p4/src/sdhost/bytcnt.rs
+++ b/esp32p4/src/sdhost/bytcnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BYTCNT")
-            .field("byte_count", &format_args!("{}", self.byte_count().bits()))
+            .field("byte_count", &self.byte_count())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BYTCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/cardthrctl.rs b/esp32p4/src/sdhost/cardthrctl.rs
index 9273aba36f..b1a29d375d 100644
--- a/esp32p4/src/sdhost/cardthrctl.rs
+++ b/esp32p4/src/sdhost/cardthrctl.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CARDTHRCTL")
-            .field("cardrdthren", &format_args!("{}", self.cardrdthren().bit()))
-            .field(
-                "cardclrinten",
-                &format_args!("{}", self.cardclrinten().bit()),
-            )
-            .field("cardwrthren", &format_args!("{}", self.cardwrthren().bit()))
-            .field(
-                "cardthreshold",
-                &format_args!("{}", self.cardthreshold().bits()),
-            )
+            .field("cardrdthren", &self.cardrdthren())
+            .field("cardclrinten", &self.cardclrinten())
+            .field("cardwrthren", &self.cardwrthren())
+            .field("cardthreshold", &self.cardthreshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CARDTHRCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Card read threshold enable. 1'b0-Card read threshold disabled. 1'b1-Card read threshold enabled."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/cdetect.rs b/esp32p4/src/sdhost/cdetect.rs
index b8c669a95b..e9df01474b 100644
--- a/esp32p4/src/sdhost/cdetect.rs
+++ b/esp32p4/src/sdhost/cdetect.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CDETECT")
-            .field(
-                "card_detect_n",
-                &format_args!("{}", self.card_detect_n().bits()),
-            )
+            .field("card_detect_n", &self.card_detect_n())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CDETECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Card detect register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cdetect::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CDETECT_SPEC;
 impl crate::RegisterSpec for CDETECT_SPEC {
diff --git a/esp32p4/src/sdhost/clk_edge_sel.rs b/esp32p4/src/sdhost/clk_edge_sel.rs
index 1af8fb74c5..7481b7a6c0 100644
--- a/esp32p4/src/sdhost/clk_edge_sel.rs
+++ b/esp32p4/src/sdhost/clk_edge_sel.rs
@@ -98,46 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EDGE_SEL")
-            .field(
-                "cclkin_edge_drv_sel",
-                &format_args!("{}", self.cclkin_edge_drv_sel().bits()),
-            )
-            .field(
-                "cclkin_edge_sam_sel",
-                &format_args!("{}", self.cclkin_edge_sam_sel().bits()),
-            )
-            .field(
-                "cclkin_edge_slf_sel",
-                &format_args!("{}", self.cclkin_edge_slf_sel().bits()),
-            )
-            .field(
-                "ccllkin_edge_h",
-                &format_args!("{}", self.ccllkin_edge_h().bits()),
-            )
-            .field(
-                "ccllkin_edge_l",
-                &format_args!("{}", self.ccllkin_edge_l().bits()),
-            )
-            .field(
-                "ccllkin_edge_n",
-                &format_args!("{}", self.ccllkin_edge_n().bits()),
-            )
-            .field("esdio_mode", &format_args!("{}", self.esdio_mode().bit()))
-            .field("esd_mode", &format_args!("{}", self.esd_mode().bit()))
-            .field("cclk_en", &format_args!("{}", self.cclk_en().bit()))
-            .field(
-                "ultra_high_speed_mode",
-                &format_args!("{}", self.ultra_high_speed_mode().bit()),
-            )
+            .field("cclkin_edge_drv_sel", &self.cclkin_edge_drv_sel())
+            .field("cclkin_edge_sam_sel", &self.cclkin_edge_sam_sel())
+            .field("cclkin_edge_slf_sel", &self.cclkin_edge_slf_sel())
+            .field("ccllkin_edge_h", &self.ccllkin_edge_h())
+            .field("ccllkin_edge_l", &self.ccllkin_edge_l())
+            .field("ccllkin_edge_n", &self.ccllkin_edge_n())
+            .field("esdio_mode", &self.esdio_mode())
+            .field("esd_mode", &self.esd_mode())
+            .field("cclk_en", &self.cclk_en())
+            .field("ultra_high_speed_mode", &self.ultra_high_speed_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EDGE_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/clkdiv.rs b/esp32p4/src/sdhost/clkdiv.rs
index 1f025bc3a7..ecb1a5c6e4 100644
--- a/esp32p4/src/sdhost/clkdiv.rs
+++ b/esp32p4/src/sdhost/clkdiv.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKDIV")
-            .field(
-                "clk_divider0",
-                &format_args!("{}", self.clk_divider0().bits()),
-            )
-            .field(
-                "clk_divider1",
-                &format_args!("{}", self.clk_divider1().bits()),
-            )
-            .field(
-                "clk_divider2",
-                &format_args!("{}", self.clk_divider2().bits()),
-            )
-            .field(
-                "clk_divider3",
-                &format_args!("{}", self.clk_divider3().bits()),
-            )
+            .field("clk_divider0", &self.clk_divider0())
+            .field("clk_divider1", &self.clk_divider1())
+            .field("clk_divider2", &self.clk_divider2())
+            .field("clk_divider3", &self.clk_divider3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKDIV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/clkena.rs b/esp32p4/src/sdhost/clkena.rs
index b9ab1045ee..9c066422e5 100644
--- a/esp32p4/src/sdhost/clkena.rs
+++ b/esp32p4/src/sdhost/clkena.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKENA")
-            .field(
-                "cclk_enable",
-                &format_args!("{}", self.cclk_enable().bits()),
-            )
-            .field("lp_enable", &format_args!("{}", self.lp_enable().bits()))
+            .field("cclk_enable", &self.cclk_enable())
+            .field("lp_enable", &self.lp_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. 0: Clock disabled; 1: Clock enabled."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/clksrc.rs b/esp32p4/src/sdhost/clksrc.rs
index 4e506db40d..c65f699e31 100644
--- a/esp32p4/src/sdhost/clksrc.rs
+++ b/esp32p4/src/sdhost/clksrc.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKSRC")
-            .field("clksrc", &format_args!("{}", self.clksrc().bits()))
+            .field("clksrc", &self.clksrc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKSRC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/cmd.rs b/esp32p4/src/sdhost/cmd.rs
index 8f7e1af323..1c3d217d5c 100644
--- a/esp32p4/src/sdhost/cmd.rs
+++ b/esp32p4/src/sdhost/cmd.rs
@@ -161,71 +161,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("index", &format_args!("{}", self.index().bits()))
-            .field(
-                "response_expect",
-                &format_args!("{}", self.response_expect().bit()),
-            )
-            .field(
-                "response_length",
-                &format_args!("{}", self.response_length().bit()),
-            )
-            .field(
-                "check_response_crc",
-                &format_args!("{}", self.check_response_crc().bit()),
-            )
-            .field(
-                "data_expected",
-                &format_args!("{}", self.data_expected().bit()),
-            )
-            .field("read_write", &format_args!("{}", self.read_write().bit()))
-            .field(
-                "transfer_mode",
-                &format_args!("{}", self.transfer_mode().bit()),
-            )
-            .field(
-                "send_auto_stop",
-                &format_args!("{}", self.send_auto_stop().bit()),
-            )
-            .field(
-                "wait_prvdata_complete",
-                &format_args!("{}", self.wait_prvdata_complete().bit()),
-            )
-            .field(
-                "stop_abort_cmd",
-                &format_args!("{}", self.stop_abort_cmd().bit()),
-            )
-            .field(
-                "send_initialization",
-                &format_args!("{}", self.send_initialization().bit()),
-            )
-            .field(
-                "card_number",
-                &format_args!("{}", self.card_number().bits()),
-            )
+            .field("index", &self.index())
+            .field("response_expect", &self.response_expect())
+            .field("response_length", &self.response_length())
+            .field("check_response_crc", &self.check_response_crc())
+            .field("data_expected", &self.data_expected())
+            .field("read_write", &self.read_write())
+            .field("transfer_mode", &self.transfer_mode())
+            .field("send_auto_stop", &self.send_auto_stop())
+            .field("wait_prvdata_complete", &self.wait_prvdata_complete())
+            .field("stop_abort_cmd", &self.stop_abort_cmd())
+            .field("send_initialization", &self.send_initialization())
+            .field("card_number", &self.card_number())
             .field(
                 "update_clock_registers_only",
-                &format_args!("{}", self.update_clock_registers_only().bit()),
+                &self.update_clock_registers_only(),
             )
-            .field(
-                "read_ceata_device",
-                &format_args!("{}", self.read_ceata_device().bit()),
-            )
-            .field(
-                "ccs_expected",
-                &format_args!("{}", self.ccs_expected().bit()),
-            )
-            .field("use_hole", &format_args!("{}", self.use_hole().bit()))
-            .field("start_cmd", &format_args!("{}", self.start_cmd().bit()))
+            .field("read_ceata_device", &self.read_ceata_device())
+            .field("ccs_expected", &self.ccs_expected())
+            .field("use_hole", &self.use_hole())
+            .field("start_cmd", &self.start_cmd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Command index."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/cmdarg.rs b/esp32p4/src/sdhost/cmdarg.rs
index db8f85bd5c..94ac7da52a 100644
--- a/esp32p4/src/sdhost/cmdarg.rs
+++ b/esp32p4/src/sdhost/cmdarg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMDARG")
-            .field("cmdarg", &format_args!("{}", self.cmdarg().bits()))
+            .field("cmdarg", &self.cmdarg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMDARG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Value indicates command argument to be passed to the card."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/ctrl.rs b/esp32p4/src/sdhost/ctrl.rs
index f0e1ff619d..e9544443a1 100644
--- a/esp32p4/src/sdhost/ctrl.rs
+++ b/esp32p4/src/sdhost/ctrl.rs
@@ -98,40 +98,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field(
-                "controller_reset",
-                &format_args!("{}", self.controller_reset().bit()),
-            )
-            .field("fifo_reset", &format_args!("{}", self.fifo_reset().bit()))
-            .field("dma_reset", &format_args!("{}", self.dma_reset().bit()))
-            .field("int_enable", &format_args!("{}", self.int_enable().bit()))
-            .field("read_wait", &format_args!("{}", self.read_wait().bit()))
-            .field(
-                "send_irq_response",
-                &format_args!("{}", self.send_irq_response().bit()),
-            )
-            .field(
-                "abort_read_data",
-                &format_args!("{}", self.abort_read_data().bit()),
-            )
-            .field("send_ccsd", &format_args!("{}", self.send_ccsd().bit()))
-            .field(
-                "send_auto_stop_ccsd",
-                &format_args!("{}", self.send_auto_stop_ccsd().bit()),
-            )
+            .field("controller_reset", &self.controller_reset())
+            .field("fifo_reset", &self.fifo_reset())
+            .field("dma_reset", &self.dma_reset())
+            .field("int_enable", &self.int_enable())
+            .field("read_wait", &self.read_wait())
+            .field("send_irq_response", &self.send_irq_response())
+            .field("abort_read_data", &self.abort_read_data())
+            .field("send_ccsd", &self.send_ccsd())
+            .field("send_auto_stop_ccsd", &self.send_auto_stop_ccsd())
             .field(
                 "ceata_device_interrupt_status",
-                &format_args!("{}", self.ceata_device_interrupt_status().bit()),
+                &self.ceata_device_interrupt_status(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/ctype.rs b/esp32p4/src/sdhost/ctype.rs
index 3d50d29f24..55173aecd3 100644
--- a/esp32p4/src/sdhost/ctype.rs
+++ b/esp32p4/src/sdhost/ctype.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTYPE")
-            .field(
-                "card_width4",
-                &format_args!("{}", self.card_width4().bits()),
-            )
-            .field(
-                "card_width8",
-                &format_args!("{}", self.card_width8().bits()),
-            )
+            .field("card_width4", &self.card_width4())
+            .field("card_width8", &self.card_width8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTYPE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit\\[1:0\\] correspond to card\\[1:0\\] respectively."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/dbaddr.rs b/esp32p4/src/sdhost/dbaddr.rs
index ea5fb55c53..3866cfa354 100644
--- a/esp32p4/src/sdhost/dbaddr.rs
+++ b/esp32p4/src/sdhost/dbaddr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBADDR")
-            .field("dbaddr", &format_args!("{}", self.dbaddr().bits()))
+            .field("dbaddr", &self.dbaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits \\[1:0\\] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/debnce.rs b/esp32p4/src/sdhost/debnce.rs
index a7f179fe77..022482c4a3 100644
--- a/esp32p4/src/sdhost/debnce.rs
+++ b/esp32p4/src/sdhost/debnce.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEBNCE")
-            .field(
-                "debounce_count",
-                &format_args!("{}", self.debounce_count().bits()),
-            )
+            .field("debounce_count", &self.debounce_count())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBNCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/dll_clk_conf.rs b/esp32p4/src/sdhost/dll_clk_conf.rs
index 2c0ffa4d5d..a3576722f6 100644
--- a/esp32p4/src/sdhost/dll_clk_conf.rs
+++ b/esp32p4/src/sdhost/dll_clk_conf.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DLL_CLK_CONF")
-            .field(
-                "dll_cclk_in_slf_en",
-                &format_args!("{}", self.dll_cclk_in_slf_en().bit()),
-            )
-            .field(
-                "dll_cclk_in_drv_en",
-                &format_args!("{}", self.dll_cclk_in_drv_en().bit()),
-            )
-            .field(
-                "dll_cclk_in_sam_en",
-                &format_args!("{}", self.dll_cclk_in_sam_en().bit()),
-            )
-            .field(
-                "dll_cclk_in_slf_phase",
-                &format_args!("{}", self.dll_cclk_in_slf_phase().bits()),
-            )
-            .field(
-                "dll_cclk_in_drv_phase",
-                &format_args!("{}", self.dll_cclk_in_drv_phase().bits()),
-            )
-            .field(
-                "dll_cclk_in_sam_phase",
-                &format_args!("{}", self.dll_cclk_in_sam_phase().bits()),
-            )
+            .field("dll_cclk_in_slf_en", &self.dll_cclk_in_slf_en())
+            .field("dll_cclk_in_drv_en", &self.dll_cclk_in_drv_en())
+            .field("dll_cclk_in_sam_en", &self.dll_cclk_in_sam_en())
+            .field("dll_cclk_in_slf_phase", &self.dll_cclk_in_slf_phase())
+            .field("dll_cclk_in_drv_phase", &self.dll_cclk_in_drv_phase())
+            .field("dll_cclk_in_sam_phase", &self.dll_cclk_in_sam_phase())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DLL_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/dll_conf.rs b/esp32p4/src/sdhost/dll_conf.rs
index 6a6bce2052..d6f45a87a9 100644
--- a/esp32p4/src/sdhost/dll_conf.rs
+++ b/esp32p4/src/sdhost/dll_conf.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DLL_CONF")
-            .field(
-                "dll_cal_stop",
-                &format_args!("{}", self.dll_cal_stop().bit()),
-            )
-            .field("dll_cal_end", &format_args!("{}", self.dll_cal_end().bit()))
+            .field("dll_cal_stop", &self.dll_cal_stop())
+            .field("dll_cal_end", &self.dll_cal_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DLL_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to stop calibration."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/dscaddr.rs b/esp32p4/src/sdhost/dscaddr.rs
index a8b43628b2..0e5e74f7e0 100644
--- a/esp32p4/src/sdhost/dscaddr.rs
+++ b/esp32p4/src/sdhost/dscaddr.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSCADDR")
-            .field("dscaddr", &format_args!("{}", self.dscaddr().bits()))
+            .field("dscaddr", &self.dscaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSCADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Host descriptor address pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dscaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DSCADDR_SPEC;
 impl crate::RegisterSpec for DSCADDR_SPEC {
diff --git a/esp32p4/src/sdhost/emmcddr.rs b/esp32p4/src/sdhost/emmcddr.rs
index a7905808ae..c09a8b9611 100644
--- a/esp32p4/src/sdhost/emmcddr.rs
+++ b/esp32p4/src/sdhost/emmcddr.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMMCDDR")
-            .field(
-                "halfstartbit",
-                &format_args!("{}", self.halfstartbit().bits()),
-            )
-            .field("hs400_mode", &format_args!("{}", self.hs400_mode().bit()))
+            .field("halfstartbit", &self.halfstartbit())
+            .field("hs400_mode", &self.hs400_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMMCDDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: 1'b0-Full cycle. 1'b1-less than one full cycle."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/enshift.rs b/esp32p4/src/sdhost/enshift.rs
index fb0f2357dc..5f8e486fda 100644
--- a/esp32p4/src/sdhost/enshift.rs
+++ b/esp32p4/src/sdhost/enshift.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENSHIFT")
-            .field(
-                "enable_shift",
-                &format_args!("{}", self.enable_shift().bits()),
-            )
+            .field("enable_shift", &self.enable_shift())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENSHIFT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. 2'b00-Default phase shift. 2'b01-Enables shifted to next immediate positive edge. 2'b10-Enables shifted to next immediate negative edge. 2'b11-Reserved."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/fifoth.rs b/esp32p4/src/sdhost/fifoth.rs
index b0e03f0226..735765f001 100644
--- a/esp32p4/src/sdhost/fifoth.rs
+++ b/esp32p4/src/sdhost/fifoth.rs
@@ -35,21 +35,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFOTH")
-            .field("tx_wmark", &format_args!("{}", self.tx_wmark().bits()))
-            .field("rx_wmark", &format_args!("{}", self.rx_wmark().bits()))
+            .field("tx_wmark", &self.tx_wmark())
+            .field("rx_wmark", &self.rx_wmark())
             .field(
                 "dma_multiple_transaction_size",
-                &format_args!("{}", self.dma_multiple_transaction_size().bits()),
+                &self.dma_multiple_transaction_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFOTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/hcon.rs b/esp32p4/src/sdhost/hcon.rs
index 0200e41188..f7790404e1 100644
--- a/esp32p4/src/sdhost/hcon.rs
+++ b/esp32p4/src/sdhost/hcon.rs
@@ -69,27 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HCON")
-            .field("card_type", &format_args!("{}", self.card_type().bit()))
-            .field("card_num", &format_args!("{}", self.card_num().bits()))
-            .field("bus_type", &format_args!("{}", self.bus_type().bit()))
-            .field("data_width", &format_args!("{}", self.data_width().bits()))
-            .field("addr_width", &format_args!("{}", self.addr_width().bits()))
-            .field("dma_width", &format_args!("{}", self.dma_width().bits()))
-            .field("ram_indise", &format_args!("{}", self.ram_indise().bit()))
-            .field("hold", &format_args!("{}", self.hold().bit()))
-            .field(
-                "num_clk_div",
-                &format_args!("{}", self.num_clk_div().bits()),
-            )
+            .field("card_type", &self.card_type())
+            .field("card_num", &self.card_num())
+            .field("bus_type", &self.bus_type())
+            .field("data_width", &self.data_width())
+            .field("addr_width", &self.addr_width())
+            .field("dma_width", &self.dma_width())
+            .field("ram_indise", &self.ram_indise())
+            .field("hold", &self.hold())
+            .field("num_clk_div", &self.num_clk_div())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HCON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Hardware feature register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcon::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HCON_SPEC;
 impl crate::RegisterSpec for HCON_SPEC {
diff --git a/esp32p4/src/sdhost/idinten.rs b/esp32p4/src/sdhost/idinten.rs
index 7998f81685..709ad85941 100644
--- a/esp32p4/src/sdhost/idinten.rs
+++ b/esp32p4/src/sdhost/idinten.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDINTEN")
-            .field("ti", &format_args!("{}", self.ti().bit()))
-            .field("ri", &format_args!("{}", self.ri().bit()))
-            .field("fbe", &format_args!("{}", self.fbe().bit()))
-            .field("du", &format_args!("{}", self.du().bit()))
-            .field("ces", &format_args!("{}", self.ces().bit()))
-            .field("ni", &format_args!("{}", self.ni().bit()))
-            .field("ai", &format_args!("{}", self.ai().bit()))
+            .field("ti", &self.ti())
+            .field("ri", &self.ri())
+            .field("fbe", &self.fbe())
+            .field("du", &self.du())
+            .field("ces", &self.ces())
+            .field("ni", &self.ni())
+            .field("ai", &self.ai())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDINTEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/idsts.rs b/esp32p4/src/sdhost/idsts.rs
index c4d4f42dcc..a3de143483 100644
--- a/esp32p4/src/sdhost/idsts.rs
+++ b/esp32p4/src/sdhost/idsts.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDSTS")
-            .field("ti", &format_args!("{}", self.ti().bit()))
-            .field("ri", &format_args!("{}", self.ri().bit()))
-            .field("fbe", &format_args!("{}", self.fbe().bit()))
-            .field("du", &format_args!("{}", self.du().bit()))
-            .field("ces", &format_args!("{}", self.ces().bit()))
-            .field("nis", &format_args!("{}", self.nis().bit()))
-            .field("ais", &format_args!("{}", self.ais().bit()))
-            .field("fbe_code", &format_args!("{}", self.fbe_code().bits()))
-            .field("fsm", &format_args!("{}", self.fsm().bits()))
+            .field("ti", &self.ti())
+            .field("ri", &self.ri())
+            .field("fbe", &self.fbe())
+            .field("du", &self.du())
+            .field("ces", &self.ces())
+            .field("nis", &self.nis())
+            .field("ais", &self.ais())
+            .field("fbe_code", &self.fbe_code())
+            .field("fsm", &self.fsm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/intmask.rs b/esp32p4/src/sdhost/intmask.rs
index d19916144a..c55d4e7c79 100644
--- a/esp32p4/src/sdhost/intmask.rs
+++ b/esp32p4/src/sdhost/intmask.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTMASK")
-            .field("int_mask", &format_args!("{}", self.int_mask().bits()))
-            .field(
-                "sdio_int_mask",
-                &format_args!("{}", self.sdio_int_mask().bits()),
-            )
+            .field("int_mask", &self.int_mask())
+            .field("sdio_int_mask", &self.sdio_int_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTMASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): Rx Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation-by-host timeout; Bit 9 (DRTO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/mintsts.rs b/esp32p4/src/sdhost/mintsts.rs
index ce1a8af58f..4f907e6f71 100644
--- a/esp32p4/src/sdhost/mintsts.rs
+++ b/esp32p4/src/sdhost/mintsts.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MINTSTS")
-            .field(
-                "int_status_msk",
-                &format_args!("{}", self.int_status_msk().bits()),
-            )
-            .field(
-                "sdio_interrupt_msk",
-                &format_args!("{}", self.sdio_interrupt_msk().bits()),
-            )
+            .field("int_status_msk", &self.int_status_msk())
+            .field("sdio_interrupt_msk", &self.sdio_interrupt_msk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MINTSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mintsts::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MINTSTS_SPEC;
 impl crate::RegisterSpec for MINTSTS_SPEC {
diff --git a/esp32p4/src/sdhost/raw_ints.rs b/esp32p4/src/sdhost/raw_ints.rs
index fdb0a68546..9d0a63c578 100644
--- a/esp32p4/src/sdhost/raw_ints.rs
+++ b/esp32p4/src/sdhost/raw_ints.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RAW_INTS")
-            .field("raw_ints", &format_args!("{}", self.raw_ints().bits()))
+            .field("raw_ints", &self.raw_ints())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_INTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SDIO raw ints register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`raw_ints::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RAW_INTS_SPEC;
 impl crate::RegisterSpec for RAW_INTS_SPEC {
diff --git a/esp32p4/src/sdhost/resp0.rs b/esp32p4/src/sdhost/resp0.rs
index 1b4aa21517..9ff09e1a06 100644
--- a/esp32p4/src/sdhost/resp0.rs
+++ b/esp32p4/src/sdhost/resp0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESP0")
-            .field("response0", &format_args!("{}", self.response0().bits()))
+            .field("response0", &self.response0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESP0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESP0_SPEC;
 impl crate::RegisterSpec for RESP0_SPEC {
diff --git a/esp32p4/src/sdhost/resp1.rs b/esp32p4/src/sdhost/resp1.rs
index 1b69601dd9..f7356973c4 100644
--- a/esp32p4/src/sdhost/resp1.rs
+++ b/esp32p4/src/sdhost/resp1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESP1")
-            .field("response1", &format_args!("{}", self.response1().bits()))
+            .field("response1", &self.response1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Long response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESP1_SPEC;
 impl crate::RegisterSpec for RESP1_SPEC {
diff --git a/esp32p4/src/sdhost/resp2.rs b/esp32p4/src/sdhost/resp2.rs
index 1a43d9001f..178a098e32 100644
--- a/esp32p4/src/sdhost/resp2.rs
+++ b/esp32p4/src/sdhost/resp2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESP2")
-            .field("response2", &format_args!("{}", self.response2().bits()))
+            .field("response2", &self.response2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESP2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Long response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESP2_SPEC;
 impl crate::RegisterSpec for RESP2_SPEC {
diff --git a/esp32p4/src/sdhost/resp3.rs b/esp32p4/src/sdhost/resp3.rs
index 73432f9173..b73efbf947 100644
--- a/esp32p4/src/sdhost/resp3.rs
+++ b/esp32p4/src/sdhost/resp3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESP3")
-            .field("response3", &format_args!("{}", self.response3().bits()))
+            .field("response3", &self.response3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESP3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Long response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESP3_SPEC;
 impl crate::RegisterSpec for RESP3_SPEC {
diff --git a/esp32p4/src/sdhost/rintsts.rs b/esp32p4/src/sdhost/rintsts.rs
index 25724778fc..ead4f84f3d 100644
--- a/esp32p4/src/sdhost/rintsts.rs
+++ b/esp32p4/src/sdhost/rintsts.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RINTSTS")
-            .field(
-                "int_status_raw",
-                &format_args!("{}", self.int_status_raw().bits()),
-            )
-            .field(
-                "sdio_interrupt_raw",
-                &format_args!("{}", self.sdio_interrupt_raw().bits()),
-            )
+            .field("int_status_raw", &self.int_status_raw())
+            .field("sdio_interrupt_raw", &self.sdio_interrupt_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RINTSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/rst_n.rs b/esp32p4/src/sdhost/rst_n.rs
index d4fad96220..515c3ad743 100644
--- a/esp32p4/src/sdhost/rst_n.rs
+++ b/esp32p4/src/sdhost/rst_n.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RST_N")
-            .field("card_reset", &format_args!("{}", self.card_reset().bits()))
+            .field("card_reset", &self.card_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RST_N_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Hardware reset. 1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET\\[0\\] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET\\[1\\] should be set to 1'b0 to reset card1."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/status.rs b/esp32p4/src/sdhost/status.rs
index a4ae56c313..ef268c61e4 100644
--- a/esp32p4/src/sdhost/status.rs
+++ b/esp32p4/src/sdhost/status.rs
@@ -76,43 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field(
-                "fifo_rx_watermark",
-                &format_args!("{}", self.fifo_rx_watermark().bit()),
-            )
-            .field(
-                "fifo_tx_watermark",
-                &format_args!("{}", self.fifo_tx_watermark().bit()),
-            )
-            .field("fifo_empty", &format_args!("{}", self.fifo_empty().bit()))
-            .field("fifo_full", &format_args!("{}", self.fifo_full().bit()))
-            .field(
-                "command_fsm_states",
-                &format_args!("{}", self.command_fsm_states().bits()),
-            )
-            .field(
-                "data_3_status",
-                &format_args!("{}", self.data_3_status().bit()),
-            )
-            .field("data_busy", &format_args!("{}", self.data_busy().bit()))
-            .field(
-                "data_state_mc_busy",
-                &format_args!("{}", self.data_state_mc_busy().bit()),
-            )
-            .field(
-                "response_index",
-                &format_args!("{}", self.response_index().bits()),
-            )
-            .field("fifo_count", &format_args!("{}", self.fifo_count().bits()))
+            .field("fifo_rx_watermark", &self.fifo_rx_watermark())
+            .field("fifo_tx_watermark", &self.fifo_tx_watermark())
+            .field("fifo_empty", &self.fifo_empty())
+            .field("fifo_full", &self.fifo_full())
+            .field("command_fsm_states", &self.command_fsm_states())
+            .field("data_3_status", &self.data_3_status())
+            .field("data_busy", &self.data_busy())
+            .field("data_state_mc_busy", &self.data_state_mc_busy())
+            .field("response_index", &self.response_index())
+            .field("fifo_count", &self.fifo_count())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SD/MMC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32p4/src/sdhost/tbbcnt.rs b/esp32p4/src/sdhost/tbbcnt.rs
index 410acd8cd8..bb4ac6ca03 100644
--- a/esp32p4/src/sdhost/tbbcnt.rs
+++ b/esp32p4/src/sdhost/tbbcnt.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TBBCNT")
-            .field("tbbcnt", &format_args!("{}", self.tbbcnt().bits()))
+            .field("tbbcnt", &self.tbbcnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TBBCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transferred byte count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbbcnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TBBCNT_SPEC;
 impl crate::RegisterSpec for TBBCNT_SPEC {
diff --git a/esp32p4/src/sdhost/tcbcnt.rs b/esp32p4/src/sdhost/tcbcnt.rs
index 0332649df8..2f744b171a 100644
--- a/esp32p4/src/sdhost/tcbcnt.rs
+++ b/esp32p4/src/sdhost/tcbcnt.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TCBCNT")
-            .field("tcbcnt", &format_args!("{}", self.tcbcnt().bits()))
+            .field("tcbcnt", &self.tcbcnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCBCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transferred byte count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcbcnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TCBCNT_SPEC;
 impl crate::RegisterSpec for TCBCNT_SPEC {
diff --git a/esp32p4/src/sdhost/tmout.rs b/esp32p4/src/sdhost/tmout.rs
index b0ad6750a7..f9a4084a1b 100644
--- a/esp32p4/src/sdhost/tmout.rs
+++ b/esp32p4/src/sdhost/tmout.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TMOUT")
-            .field(
-                "response_timeout",
-                &format_args!("{}", self.response_timeout().bits()),
-            )
-            .field(
-                "data_timeout",
-                &format_args!("{}", self.data_timeout().bits()),
-            )
+            .field("response_timeout", &self.response_timeout())
+            .field("data_timeout", &self.data_timeout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TMOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/uhs.rs b/esp32p4/src/sdhost/uhs.rs
index a4da564e20..13762b101a 100644
--- a/esp32p4/src/sdhost/uhs.rs
+++ b/esp32p4/src/sdhost/uhs.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("UHS")
-            .field("ddr", &format_args!("{}", self.ddr().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UHS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("UHS").field("ddr", &self.ddr()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/sdhost/usrid.rs b/esp32p4/src/sdhost/usrid.rs
index c1f4d4468f..00a625ffb6 100644
--- a/esp32p4/src/sdhost/usrid.rs
+++ b/esp32p4/src/sdhost/usrid.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USRID")
-            .field("usrid", &format_args!("{}", self.usrid().bits()))
+            .field("usrid", &self.usrid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USRID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - User identification register, value set by user. Can also be used as a scratchpad register by user."]
     #[inline(always)]
diff --git a/esp32p4/src/sdhost/verid.rs b/esp32p4/src/sdhost/verid.rs
index 0874ea6135..4c138b6386 100644
--- a/esp32p4/src/sdhost/verid.rs
+++ b/esp32p4/src/sdhost/verid.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERID")
-            .field("versionid", &format_args!("{}", self.versionid().bits()))
+            .field("versionid", &self.versionid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Version ID (scratchpad) register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`verid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VERID_SPEC;
 impl crate::RegisterSpec for VERID_SPEC {
diff --git a/esp32p4/src/sdhost/wrtprt.rs b/esp32p4/src/sdhost/wrtprt.rs
index cd98eab48c..ed6a8d409e 100644
--- a/esp32p4/src/sdhost/wrtprt.rs
+++ b/esp32p4/src/sdhost/wrtprt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WRTPRT")
-            .field(
-                "write_protect",
-                &format_args!("{}", self.write_protect().bits()),
-            )
+            .field("write_protect", &self.write_protect())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WRTPRT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Card write protection (WP) status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wrtprt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WRTPRT_SPEC;
 impl crate::RegisterSpec for WRTPRT_SPEC {
diff --git a/esp32p4/src/sha/busy.rs b/esp32p4/src/sha/busy.rs
index d586138364..ec4ecab687 100644
--- a/esp32p4/src/sha/busy.rs
+++ b/esp32p4/src/sha/busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUSY")
-            .field("state", &format_args!("{}", self.state().bit()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Busy register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUSY_SPEC;
 impl crate::RegisterSpec for BUSY_SPEC {
diff --git a/esp32p4/src/sha/continue_.rs b/esp32p4/src/sha/continue_.rs
index a5d02d7900..e3c16db2a3 100644
--- a/esp32p4/src/sha/continue_.rs
+++ b/esp32p4/src/sha/continue_.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONTINUE")
-            .field("continue_", &format_args!("{}", self.continue_().bits()))
+            .field("continue_", &self.continue_())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONTINUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Typical SHA configuration register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`continue_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CONTINUE_SPEC;
 impl crate::RegisterSpec for CONTINUE_SPEC {
diff --git a/esp32p4/src/sha/date.rs b/esp32p4/src/sha/date.rs
index fea49bfb0c..9d86578ecf 100644
--- a/esp32p4/src/sha/date.rs
+++ b/esp32p4/src/sha/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/sha/dma_block_num.rs b/esp32p4/src/sha/dma_block_num.rs
index 235679368f..be8854254d 100644
--- a/esp32p4/src/sha/dma_block_num.rs
+++ b/esp32p4/src/sha/dma_block_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_BLOCK_NUM")
-            .field(
-                "dma_block_num",
-                &format_args!("{}", self.dma_block_num().bits()),
-            )
+            .field("dma_block_num", &self.dma_block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Dma-sha block number."]
     #[inline(always)]
diff --git a/esp32p4/src/sha/h_mem.rs b/esp32p4/src/sha/h_mem.rs
index e0865c92c6..13a6f95266 100644
--- a/esp32p4/src/sha/h_mem.rs
+++ b/esp32p4/src/sha/h_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Sha H memory which contains intermediate hash or finial hash.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct H_MEM_SPEC;
diff --git a/esp32p4/src/sha/irq_ena.rs b/esp32p4/src/sha/irq_ena.rs
index 8d61ac4aae..725a0f2641 100644
--- a/esp32p4/src/sha/irq_ena.rs
+++ b/esp32p4/src/sha/irq_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IRQ_ENA")
-            .field(
-                "interrupt_ena",
-                &format_args!("{}", self.interrupt_ena().bit()),
-            )
+            .field("interrupt_ena", &self.interrupt_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IRQ_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable."]
     #[inline(always)]
diff --git a/esp32p4/src/sha/m_mem.rs b/esp32p4/src/sha/m_mem.rs
index ccac5e7d71..7418659e89 100644
--- a/esp32p4/src/sha/m_mem.rs
+++ b/esp32p4/src/sha/m_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Sha M memory which contains message.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct M_MEM_SPEC;
diff --git a/esp32p4/src/sha/mode.rs b/esp32p4/src/sha/mode.rs
index 2b849314d6..ab2c8b2b20 100644
--- a/esp32p4/src/sha/mode.rs
+++ b/esp32p4/src/sha/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/sha/start.rs b/esp32p4/src/sha/start.rs
index fb32543baa..7c93b02442 100644
--- a/esp32p4/src/sha/start.rs
+++ b/esp32p4/src/sha/start.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("START")
-            .field("start", &format_args!("{}", self.start().bits()))
+            .field("start", &self.start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<START_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Typical SHA configuration register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`start::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct START_SPEC;
 impl crate::RegisterSpec for START_SPEC {
diff --git a/esp32p4/src/sha/t_length.rs b/esp32p4/src/sha/t_length.rs
index 523a021805..845f709a89 100644
--- a/esp32p4/src/sha/t_length.rs
+++ b/esp32p4/src/sha/t_length.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T_LENGTH")
-            .field("t_length", &format_args!("{}", self.t_length().bits()))
+            .field("t_length", &self.t_length())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T_LENGTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Sha t_length (used if and only if mode == SHA_512/t)."]
     #[inline(always)]
diff --git a/esp32p4/src/sha/t_string.rs b/esp32p4/src/sha/t_string.rs
index db1093db4b..c533a0e0d5 100644
--- a/esp32p4/src/sha/t_string.rs
+++ b/esp32p4/src/sha/t_string.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T_STRING")
-            .field("t_string", &format_args!("{}", self.t_string().bits()))
+            .field("t_string", &self.t_string())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T_STRING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Sha t_string (used if and only if mode == SHA_512/t)."]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/ch/evt_id.rs b/esp32p4/src/soc_etm/ch/evt_id.rs
index efbfc94bcf..473c214fe4 100644
--- a/esp32p4/src/soc_etm/ch/evt_id.rs
+++ b/esp32p4/src/soc_etm/ch/evt_id.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVT_ID")
-            .field("evt_id", &format_args!("{}", self.evt_id().bits()))
+            .field("evt_id", &self.evt_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures ch0_evt_id"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/ch/task_id.rs b/esp32p4/src/soc_etm/ch/task_id.rs
index 6d9fc00cfd..3fce1ee31d 100644
--- a/esp32p4/src/soc_etm/ch/task_id.rs
+++ b/esp32p4/src/soc_etm/ch/task_id.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TASK_ID")
-            .field("task_id", &format_args!("{}", self.task_id().bits()))
+            .field("task_id", &self.task_id())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TASK_ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures ch0_task_id"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/ch_ena_ad0.rs b/esp32p4/src/soc_etm/ch_ena_ad0.rs
index c70125d930..53c43c2702 100644
--- a/esp32p4/src/soc_etm/ch_ena_ad0.rs
+++ b/esp32p4/src/soc_etm/ch_ena_ad0.rs
@@ -187,47 +187,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_ENA_AD0")
-            .field("ch_ena0", &format_args!("{}", self.ch_ena0().bit()))
-            .field("ch_ena1", &format_args!("{}", self.ch_ena1().bit()))
-            .field("ch_ena2", &format_args!("{}", self.ch_ena2().bit()))
-            .field("ch_ena3", &format_args!("{}", self.ch_ena3().bit()))
-            .field("ch_ena4", &format_args!("{}", self.ch_ena4().bit()))
-            .field("ch_ena5", &format_args!("{}", self.ch_ena5().bit()))
-            .field("ch_ena6", &format_args!("{}", self.ch_ena6().bit()))
-            .field("ch_ena7", &format_args!("{}", self.ch_ena7().bit()))
-            .field("ch_ena8", &format_args!("{}", self.ch_ena8().bit()))
-            .field("ch_ena9", &format_args!("{}", self.ch_ena9().bit()))
-            .field("ch_ena10", &format_args!("{}", self.ch_ena10().bit()))
-            .field("ch_ena11", &format_args!("{}", self.ch_ena11().bit()))
-            .field("ch_ena12", &format_args!("{}", self.ch_ena12().bit()))
-            .field("ch_ena13", &format_args!("{}", self.ch_ena13().bit()))
-            .field("ch_ena14", &format_args!("{}", self.ch_ena14().bit()))
-            .field("ch_ena15", &format_args!("{}", self.ch_ena15().bit()))
-            .field("ch_ena16", &format_args!("{}", self.ch_ena16().bit()))
-            .field("ch_ena17", &format_args!("{}", self.ch_ena17().bit()))
-            .field("ch_ena18", &format_args!("{}", self.ch_ena18().bit()))
-            .field("ch_ena19", &format_args!("{}", self.ch_ena19().bit()))
-            .field("ch_ena20", &format_args!("{}", self.ch_ena20().bit()))
-            .field("ch_ena21", &format_args!("{}", self.ch_ena21().bit()))
-            .field("ch_ena22", &format_args!("{}", self.ch_ena22().bit()))
-            .field("ch_ena23", &format_args!("{}", self.ch_ena23().bit()))
-            .field("ch_ena24", &format_args!("{}", self.ch_ena24().bit()))
-            .field("ch_ena25", &format_args!("{}", self.ch_ena25().bit()))
-            .field("ch_ena26", &format_args!("{}", self.ch_ena26().bit()))
-            .field("ch_ena27", &format_args!("{}", self.ch_ena27().bit()))
-            .field("ch_ena28", &format_args!("{}", self.ch_ena28().bit()))
-            .field("ch_ena29", &format_args!("{}", self.ch_ena29().bit()))
-            .field("ch_ena30", &format_args!("{}", self.ch_ena30().bit()))
-            .field("ch_ena31", &format_args!("{}", self.ch_ena31().bit()))
+            .field("ch_ena0", &self.ch_ena0())
+            .field("ch_ena1", &self.ch_ena1())
+            .field("ch_ena2", &self.ch_ena2())
+            .field("ch_ena3", &self.ch_ena3())
+            .field("ch_ena4", &self.ch_ena4())
+            .field("ch_ena5", &self.ch_ena5())
+            .field("ch_ena6", &self.ch_ena6())
+            .field("ch_ena7", &self.ch_ena7())
+            .field("ch_ena8", &self.ch_ena8())
+            .field("ch_ena9", &self.ch_ena9())
+            .field("ch_ena10", &self.ch_ena10())
+            .field("ch_ena11", &self.ch_ena11())
+            .field("ch_ena12", &self.ch_ena12())
+            .field("ch_ena13", &self.ch_ena13())
+            .field("ch_ena14", &self.ch_ena14())
+            .field("ch_ena15", &self.ch_ena15())
+            .field("ch_ena16", &self.ch_ena16())
+            .field("ch_ena17", &self.ch_ena17())
+            .field("ch_ena18", &self.ch_ena18())
+            .field("ch_ena19", &self.ch_ena19())
+            .field("ch_ena20", &self.ch_ena20())
+            .field("ch_ena21", &self.ch_ena21())
+            .field("ch_ena22", &self.ch_ena22())
+            .field("ch_ena23", &self.ch_ena23())
+            .field("ch_ena24", &self.ch_ena24())
+            .field("ch_ena25", &self.ch_ena25())
+            .field("ch_ena26", &self.ch_ena26())
+            .field("ch_ena27", &self.ch_ena27())
+            .field("ch_ena28", &self.ch_ena28())
+            .field("ch_ena29", &self.ch_ena29())
+            .field("ch_ena30", &self.ch_ena30())
+            .field("ch_ena31", &self.ch_ena31())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_ENA_AD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Represents ch(0-31) enable status.\\\\0: Disable\\\\1: Enable"]
     #[doc = ""]
diff --git a/esp32p4/src/soc_etm/ch_ena_ad1.rs b/esp32p4/src/soc_etm/ch_ena_ad1.rs
index db80a55fb2..9da54b1b17 100644
--- a/esp32p4/src/soc_etm/ch_ena_ad1.rs
+++ b/esp32p4/src/soc_etm/ch_ena_ad1.rs
@@ -117,33 +117,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_ENA_AD1")
-            .field("ch_ena32", &format_args!("{}", self.ch_ena32().bit()))
-            .field("ch_ena33", &format_args!("{}", self.ch_ena33().bit()))
-            .field("ch_ena34", &format_args!("{}", self.ch_ena34().bit()))
-            .field("ch_ena35", &format_args!("{}", self.ch_ena35().bit()))
-            .field("ch_ena36", &format_args!("{}", self.ch_ena36().bit()))
-            .field("ch_ena37", &format_args!("{}", self.ch_ena37().bit()))
-            .field("ch_ena38", &format_args!("{}", self.ch_ena38().bit()))
-            .field("ch_ena39", &format_args!("{}", self.ch_ena39().bit()))
-            .field("ch_ena40", &format_args!("{}", self.ch_ena40().bit()))
-            .field("ch_ena41", &format_args!("{}", self.ch_ena41().bit()))
-            .field("ch_ena42", &format_args!("{}", self.ch_ena42().bit()))
-            .field("ch_ena43", &format_args!("{}", self.ch_ena43().bit()))
-            .field("ch_ena44", &format_args!("{}", self.ch_ena44().bit()))
-            .field("ch_ena45", &format_args!("{}", self.ch_ena45().bit()))
-            .field("ch_ena46", &format_args!("{}", self.ch_ena46().bit()))
-            .field("ch_ena47", &format_args!("{}", self.ch_ena47().bit()))
-            .field("ch_ena48", &format_args!("{}", self.ch_ena48().bit()))
-            .field("ch_ena49", &format_args!("{}", self.ch_ena49().bit()))
+            .field("ch_ena32", &self.ch_ena32())
+            .field("ch_ena33", &self.ch_ena33())
+            .field("ch_ena34", &self.ch_ena34())
+            .field("ch_ena35", &self.ch_ena35())
+            .field("ch_ena36", &self.ch_ena36())
+            .field("ch_ena37", &self.ch_ena37())
+            .field("ch_ena38", &self.ch_ena38())
+            .field("ch_ena39", &self.ch_ena39())
+            .field("ch_ena40", &self.ch_ena40())
+            .field("ch_ena41", &self.ch_ena41())
+            .field("ch_ena42", &self.ch_ena42())
+            .field("ch_ena43", &self.ch_ena43())
+            .field("ch_ena44", &self.ch_ena44())
+            .field("ch_ena45", &self.ch_ena45())
+            .field("ch_ena46", &self.ch_ena46())
+            .field("ch_ena47", &self.ch_ena47())
+            .field("ch_ena48", &self.ch_ena48())
+            .field("ch_ena49", &self.ch_ena49())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_ENA_AD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Represents ch(32-49) enable status.\\\\0: Disable\\\\1: Enable"]
     #[doc = ""]
diff --git a/esp32p4/src/soc_etm/clk_en.rs b/esp32p4/src/soc_etm/clk_en.rs
index f4b3a18bb7..152e966075 100644
--- a/esp32p4/src/soc_etm/clk_en.rs
+++ b/esp32p4/src/soc_etm/clk_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EN")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/date.rs b/esp32p4/src/soc_etm/date.rs
index fcef7c1136..fbf1e7ef57 100644
--- a/esp32p4/src/soc_etm/date.rs
+++ b/esp32p4/src/soc_etm/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/soc_etm/evt_st0.rs b/esp32p4/src/soc_etm/evt_st0.rs
index b054e72704..f5c7d39ac1 100644
--- a/esp32p4/src/soc_etm/evt_st0.rs
+++ b/esp32p4/src/soc_etm/evt_st0.rs
@@ -298,141 +298,111 @@ impl core::fmt::Debug for R {
         f.debug_struct("EVT_ST0")
             .field(
                 "gpio_evt_ch0_rise_edge_st",
-                &format_args!("{}", self.gpio_evt_ch0_rise_edge_st().bit()),
+                &self.gpio_evt_ch0_rise_edge_st(),
             )
             .field(
                 "gpio_evt_ch1_rise_edge_st",
-                &format_args!("{}", self.gpio_evt_ch1_rise_edge_st().bit()),
+                &self.gpio_evt_ch1_rise_edge_st(),
             )
             .field(
                 "gpio_evt_ch2_rise_edge_st",
-                &format_args!("{}", self.gpio_evt_ch2_rise_edge_st().bit()),
+                &self.gpio_evt_ch2_rise_edge_st(),
             )
             .field(
                 "gpio_evt_ch3_rise_edge_st",
-                &format_args!("{}", self.gpio_evt_ch3_rise_edge_st().bit()),
+                &self.gpio_evt_ch3_rise_edge_st(),
             )
             .field(
                 "gpio_evt_ch4_rise_edge_st",
-                &format_args!("{}", self.gpio_evt_ch4_rise_edge_st().bit()),
+                &self.gpio_evt_ch4_rise_edge_st(),
             )
             .field(
                 "gpio_evt_ch5_rise_edge_st",
-                &format_args!("{}", self.gpio_evt_ch5_rise_edge_st().bit()),
+                &self.gpio_evt_ch5_rise_edge_st(),
             )
             .field(
                 "gpio_evt_ch6_rise_edge_st",
-                &format_args!("{}", self.gpio_evt_ch6_rise_edge_st().bit()),
+                &self.gpio_evt_ch6_rise_edge_st(),
             )
             .field(
                 "gpio_evt_ch7_rise_edge_st",
-                &format_args!("{}", self.gpio_evt_ch7_rise_edge_st().bit()),
+                &self.gpio_evt_ch7_rise_edge_st(),
             )
             .field(
                 "gpio_evt_ch0_fall_edge_st",
-                &format_args!("{}", self.gpio_evt_ch0_fall_edge_st().bit()),
+                &self.gpio_evt_ch0_fall_edge_st(),
             )
             .field(
                 "gpio_evt_ch1_fall_edge_st",
-                &format_args!("{}", self.gpio_evt_ch1_fall_edge_st().bit()),
+                &self.gpio_evt_ch1_fall_edge_st(),
             )
             .field(
                 "gpio_evt_ch2_fall_edge_st",
-                &format_args!("{}", self.gpio_evt_ch2_fall_edge_st().bit()),
+                &self.gpio_evt_ch2_fall_edge_st(),
             )
             .field(
                 "gpio_evt_ch3_fall_edge_st",
-                &format_args!("{}", self.gpio_evt_ch3_fall_edge_st().bit()),
+                &self.gpio_evt_ch3_fall_edge_st(),
             )
             .field(
                 "gpio_evt_ch4_fall_edge_st",
-                &format_args!("{}", self.gpio_evt_ch4_fall_edge_st().bit()),
+                &self.gpio_evt_ch4_fall_edge_st(),
             )
             .field(
                 "gpio_evt_ch5_fall_edge_st",
-                &format_args!("{}", self.gpio_evt_ch5_fall_edge_st().bit()),
+                &self.gpio_evt_ch5_fall_edge_st(),
             )
             .field(
                 "gpio_evt_ch6_fall_edge_st",
-                &format_args!("{}", self.gpio_evt_ch6_fall_edge_st().bit()),
+                &self.gpio_evt_ch6_fall_edge_st(),
             )
             .field(
                 "gpio_evt_ch7_fall_edge_st",
-                &format_args!("{}", self.gpio_evt_ch7_fall_edge_st().bit()),
-            )
-            .field(
-                "gpio_evt_ch0_any_edge_st",
-                &format_args!("{}", self.gpio_evt_ch0_any_edge_st().bit()),
-            )
-            .field(
-                "gpio_evt_ch1_any_edge_st",
-                &format_args!("{}", self.gpio_evt_ch1_any_edge_st().bit()),
-            )
-            .field(
-                "gpio_evt_ch2_any_edge_st",
-                &format_args!("{}", self.gpio_evt_ch2_any_edge_st().bit()),
-            )
-            .field(
-                "gpio_evt_ch3_any_edge_st",
-                &format_args!("{}", self.gpio_evt_ch3_any_edge_st().bit()),
-            )
-            .field(
-                "gpio_evt_ch4_any_edge_st",
-                &format_args!("{}", self.gpio_evt_ch4_any_edge_st().bit()),
-            )
-            .field(
-                "gpio_evt_ch5_any_edge_st",
-                &format_args!("{}", self.gpio_evt_ch5_any_edge_st().bit()),
-            )
-            .field(
-                "gpio_evt_ch6_any_edge_st",
-                &format_args!("{}", self.gpio_evt_ch6_any_edge_st().bit()),
-            )
-            .field(
-                "gpio_evt_ch7_any_edge_st",
-                &format_args!("{}", self.gpio_evt_ch7_any_edge_st().bit()),
+                &self.gpio_evt_ch7_fall_edge_st(),
             )
+            .field("gpio_evt_ch0_any_edge_st", &self.gpio_evt_ch0_any_edge_st())
+            .field("gpio_evt_ch1_any_edge_st", &self.gpio_evt_ch1_any_edge_st())
+            .field("gpio_evt_ch2_any_edge_st", &self.gpio_evt_ch2_any_edge_st())
+            .field("gpio_evt_ch3_any_edge_st", &self.gpio_evt_ch3_any_edge_st())
+            .field("gpio_evt_ch4_any_edge_st", &self.gpio_evt_ch4_any_edge_st())
+            .field("gpio_evt_ch5_any_edge_st", &self.gpio_evt_ch5_any_edge_st())
+            .field("gpio_evt_ch6_any_edge_st", &self.gpio_evt_ch6_any_edge_st())
+            .field("gpio_evt_ch7_any_edge_st", &self.gpio_evt_ch7_any_edge_st())
             .field(
                 "gpio_evt_zero_det_pos0_st",
-                &format_args!("{}", self.gpio_evt_zero_det_pos0_st().bit()),
+                &self.gpio_evt_zero_det_pos0_st(),
             )
             .field(
                 "gpio_evt_zero_det_neg0_st",
-                &format_args!("{}", self.gpio_evt_zero_det_neg0_st().bit()),
+                &self.gpio_evt_zero_det_neg0_st(),
             )
             .field(
                 "gpio_evt_zero_det_pos1_st",
-                &format_args!("{}", self.gpio_evt_zero_det_pos1_st().bit()),
+                &self.gpio_evt_zero_det_pos1_st(),
             )
             .field(
                 "gpio_evt_zero_det_neg1_st",
-                &format_args!("{}", self.gpio_evt_zero_det_neg1_st().bit()),
+                &self.gpio_evt_zero_det_neg1_st(),
             )
             .field(
                 "ledc_evt_duty_chng_end_ch0_st",
-                &format_args!("{}", self.ledc_evt_duty_chng_end_ch0_st().bit()),
+                &self.ledc_evt_duty_chng_end_ch0_st(),
             )
             .field(
                 "ledc_evt_duty_chng_end_ch1_st",
-                &format_args!("{}", self.ledc_evt_duty_chng_end_ch1_st().bit()),
+                &self.ledc_evt_duty_chng_end_ch1_st(),
             )
             .field(
                 "ledc_evt_duty_chng_end_ch2_st",
-                &format_args!("{}", self.ledc_evt_duty_chng_end_ch2_st().bit()),
+                &self.ledc_evt_duty_chng_end_ch2_st(),
             )
             .field(
                 "ledc_evt_duty_chng_end_ch3_st",
-                &format_args!("{}", self.ledc_evt_duty_chng_end_ch3_st().bit()),
+                &self.ledc_evt_duty_chng_end_ch3_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_ST0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Represents GPIO_evt_ch0_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/evt_st1.rs b/esp32p4/src/soc_etm/evt_st1.rs
index 83645d4b4d..bcf140c105 100644
--- a/esp32p4/src/soc_etm/evt_st1.rs
+++ b/esp32p4/src/soc_etm/evt_st1.rs
@@ -298,141 +298,108 @@ impl core::fmt::Debug for R {
         f.debug_struct("EVT_ST1")
             .field(
                 "ledc_evt_duty_chng_end_ch4_st",
-                &format_args!("{}", self.ledc_evt_duty_chng_end_ch4_st().bit()),
+                &self.ledc_evt_duty_chng_end_ch4_st(),
             )
             .field(
                 "ledc_evt_duty_chng_end_ch5_st",
-                &format_args!("{}", self.ledc_evt_duty_chng_end_ch5_st().bit()),
+                &self.ledc_evt_duty_chng_end_ch5_st(),
             )
             .field(
                 "ledc_evt_duty_chng_end_ch6_st",
-                &format_args!("{}", self.ledc_evt_duty_chng_end_ch6_st().bit()),
+                &self.ledc_evt_duty_chng_end_ch6_st(),
             )
             .field(
                 "ledc_evt_duty_chng_end_ch7_st",
-                &format_args!("{}", self.ledc_evt_duty_chng_end_ch7_st().bit()),
+                &self.ledc_evt_duty_chng_end_ch7_st(),
             )
             .field(
                 "ledc_evt_ovf_cnt_pls_ch0_st",
-                &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch0_st().bit()),
+                &self.ledc_evt_ovf_cnt_pls_ch0_st(),
             )
             .field(
                 "ledc_evt_ovf_cnt_pls_ch1_st",
-                &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch1_st().bit()),
+                &self.ledc_evt_ovf_cnt_pls_ch1_st(),
             )
             .field(
                 "ledc_evt_ovf_cnt_pls_ch2_st",
-                &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch2_st().bit()),
+                &self.ledc_evt_ovf_cnt_pls_ch2_st(),
             )
             .field(
                 "ledc_evt_ovf_cnt_pls_ch3_st",
-                &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch3_st().bit()),
+                &self.ledc_evt_ovf_cnt_pls_ch3_st(),
             )
             .field(
                 "ledc_evt_ovf_cnt_pls_ch4_st",
-                &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch4_st().bit()),
+                &self.ledc_evt_ovf_cnt_pls_ch4_st(),
             )
             .field(
                 "ledc_evt_ovf_cnt_pls_ch5_st",
-                &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch5_st().bit()),
+                &self.ledc_evt_ovf_cnt_pls_ch5_st(),
             )
             .field(
                 "ledc_evt_ovf_cnt_pls_ch6_st",
-                &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch6_st().bit()),
+                &self.ledc_evt_ovf_cnt_pls_ch6_st(),
             )
             .field(
                 "ledc_evt_ovf_cnt_pls_ch7_st",
-                &format_args!("{}", self.ledc_evt_ovf_cnt_pls_ch7_st().bit()),
+                &self.ledc_evt_ovf_cnt_pls_ch7_st(),
             )
             .field(
                 "ledc_evt_time_ovf_timer0_st",
-                &format_args!("{}", self.ledc_evt_time_ovf_timer0_st().bit()),
+                &self.ledc_evt_time_ovf_timer0_st(),
             )
             .field(
                 "ledc_evt_time_ovf_timer1_st",
-                &format_args!("{}", self.ledc_evt_time_ovf_timer1_st().bit()),
+                &self.ledc_evt_time_ovf_timer1_st(),
             )
             .field(
                 "ledc_evt_time_ovf_timer2_st",
-                &format_args!("{}", self.ledc_evt_time_ovf_timer2_st().bit()),
+                &self.ledc_evt_time_ovf_timer2_st(),
             )
             .field(
                 "ledc_evt_time_ovf_timer3_st",
-                &format_args!("{}", self.ledc_evt_time_ovf_timer3_st().bit()),
-            )
-            .field(
-                "ledc_evt_timer0_cmp_st",
-                &format_args!("{}", self.ledc_evt_timer0_cmp_st().bit()),
-            )
-            .field(
-                "ledc_evt_timer1_cmp_st",
-                &format_args!("{}", self.ledc_evt_timer1_cmp_st().bit()),
-            )
-            .field(
-                "ledc_evt_timer2_cmp_st",
-                &format_args!("{}", self.ledc_evt_timer2_cmp_st().bit()),
-            )
-            .field(
-                "ledc_evt_timer3_cmp_st",
-                &format_args!("{}", self.ledc_evt_timer3_cmp_st().bit()),
+                &self.ledc_evt_time_ovf_timer3_st(),
             )
+            .field("ledc_evt_timer0_cmp_st", &self.ledc_evt_timer0_cmp_st())
+            .field("ledc_evt_timer1_cmp_st", &self.ledc_evt_timer1_cmp_st())
+            .field("ledc_evt_timer2_cmp_st", &self.ledc_evt_timer2_cmp_st())
+            .field("ledc_evt_timer3_cmp_st", &self.ledc_evt_timer3_cmp_st())
             .field(
                 "tg0_evt_cnt_cmp_timer0_st",
-                &format_args!("{}", self.tg0_evt_cnt_cmp_timer0_st().bit()),
+                &self.tg0_evt_cnt_cmp_timer0_st(),
             )
             .field(
                 "tg0_evt_cnt_cmp_timer1_st",
-                &format_args!("{}", self.tg0_evt_cnt_cmp_timer1_st().bit()),
+                &self.tg0_evt_cnt_cmp_timer1_st(),
             )
             .field(
                 "tg1_evt_cnt_cmp_timer0_st",
-                &format_args!("{}", self.tg1_evt_cnt_cmp_timer0_st().bit()),
+                &self.tg1_evt_cnt_cmp_timer0_st(),
             )
             .field(
                 "tg1_evt_cnt_cmp_timer1_st",
-                &format_args!("{}", self.tg1_evt_cnt_cmp_timer1_st().bit()),
-            )
-            .field(
-                "systimer_evt_cnt_cmp0_st",
-                &format_args!("{}", self.systimer_evt_cnt_cmp0_st().bit()),
-            )
-            .field(
-                "systimer_evt_cnt_cmp1_st",
-                &format_args!("{}", self.systimer_evt_cnt_cmp1_st().bit()),
-            )
-            .field(
-                "systimer_evt_cnt_cmp2_st",
-                &format_args!("{}", self.systimer_evt_cnt_cmp2_st().bit()),
+                &self.tg1_evt_cnt_cmp_timer1_st(),
             )
+            .field("systimer_evt_cnt_cmp0_st", &self.systimer_evt_cnt_cmp0_st())
+            .field("systimer_evt_cnt_cmp1_st", &self.systimer_evt_cnt_cmp1_st())
+            .field("systimer_evt_cnt_cmp2_st", &self.systimer_evt_cnt_cmp2_st())
             .field(
                 "mcpwm0_evt_timer0_stop_st",
-                &format_args!("{}", self.mcpwm0_evt_timer0_stop_st().bit()),
+                &self.mcpwm0_evt_timer0_stop_st(),
             )
             .field(
                 "mcpwm0_evt_timer1_stop_st",
-                &format_args!("{}", self.mcpwm0_evt_timer1_stop_st().bit()),
+                &self.mcpwm0_evt_timer1_stop_st(),
             )
             .field(
                 "mcpwm0_evt_timer2_stop_st",
-                &format_args!("{}", self.mcpwm0_evt_timer2_stop_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_timer0_tez_st",
-                &format_args!("{}", self.mcpwm0_evt_timer0_tez_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_timer1_tez_st",
-                &format_args!("{}", self.mcpwm0_evt_timer1_tez_st().bit()),
+                &self.mcpwm0_evt_timer2_stop_st(),
             )
+            .field("mcpwm0_evt_timer0_tez_st", &self.mcpwm0_evt_timer0_tez_st())
+            .field("mcpwm0_evt_timer1_tez_st", &self.mcpwm0_evt_timer1_tez_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_ST1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/evt_st2.rs b/esp32p4/src/soc_etm/evt_st2.rs
index abf48f5175..2c54d8a50d 100644
--- a/esp32p4/src/soc_etm/evt_st2.rs
+++ b/esp32p4/src/soc_etm/evt_st2.rs
@@ -296,143 +296,44 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVT_ST2")
-            .field(
-                "mcpwm0_evt_timer2_tez_st",
-                &format_args!("{}", self.mcpwm0_evt_timer2_tez_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_timer0_tep_st",
-                &format_args!("{}", self.mcpwm0_evt_timer0_tep_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_timer1_tep_st",
-                &format_args!("{}", self.mcpwm0_evt_timer1_tep_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_timer2_tep_st",
-                &format_args!("{}", self.mcpwm0_evt_timer2_tep_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_op0_tea_st",
-                &format_args!("{}", self.mcpwm0_evt_op0_tea_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_op1_tea_st",
-                &format_args!("{}", self.mcpwm0_evt_op1_tea_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_op2_tea_st",
-                &format_args!("{}", self.mcpwm0_evt_op2_tea_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_op0_teb_st",
-                &format_args!("{}", self.mcpwm0_evt_op0_teb_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_op1_teb_st",
-                &format_args!("{}", self.mcpwm0_evt_op1_teb_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_op2_teb_st",
-                &format_args!("{}", self.mcpwm0_evt_op2_teb_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_f0_st",
-                &format_args!("{}", self.mcpwm0_evt_f0_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_f1_st",
-                &format_args!("{}", self.mcpwm0_evt_f1_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_f2_st",
-                &format_args!("{}", self.mcpwm0_evt_f2_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_f0_clr_st",
-                &format_args!("{}", self.mcpwm0_evt_f0_clr_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_f1_clr_st",
-                &format_args!("{}", self.mcpwm0_evt_f1_clr_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_f2_clr_st",
-                &format_args!("{}", self.mcpwm0_evt_f2_clr_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_tz0_cbc_st",
-                &format_args!("{}", self.mcpwm0_evt_tz0_cbc_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_tz1_cbc_st",
-                &format_args!("{}", self.mcpwm0_evt_tz1_cbc_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_tz2_cbc_st",
-                &format_args!("{}", self.mcpwm0_evt_tz2_cbc_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_tz0_ost_st",
-                &format_args!("{}", self.mcpwm0_evt_tz0_ost_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_tz1_ost_st",
-                &format_args!("{}", self.mcpwm0_evt_tz1_ost_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_tz2_ost_st",
-                &format_args!("{}", self.mcpwm0_evt_tz2_ost_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_cap0_st",
-                &format_args!("{}", self.mcpwm0_evt_cap0_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_cap1_st",
-                &format_args!("{}", self.mcpwm0_evt_cap1_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_cap2_st",
-                &format_args!("{}", self.mcpwm0_evt_cap2_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_op0_tee1_st",
-                &format_args!("{}", self.mcpwm0_evt_op0_tee1_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_op1_tee1_st",
-                &format_args!("{}", self.mcpwm0_evt_op1_tee1_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_op2_tee1_st",
-                &format_args!("{}", self.mcpwm0_evt_op2_tee1_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_op0_tee2_st",
-                &format_args!("{}", self.mcpwm0_evt_op0_tee2_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_op1_tee2_st",
-                &format_args!("{}", self.mcpwm0_evt_op1_tee2_st().bit()),
-            )
-            .field(
-                "mcpwm0_evt_op2_tee2_st",
-                &format_args!("{}", self.mcpwm0_evt_op2_tee2_st().bit()),
-            )
+            .field("mcpwm0_evt_timer2_tez_st", &self.mcpwm0_evt_timer2_tez_st())
+            .field("mcpwm0_evt_timer0_tep_st", &self.mcpwm0_evt_timer0_tep_st())
+            .field("mcpwm0_evt_timer1_tep_st", &self.mcpwm0_evt_timer1_tep_st())
+            .field("mcpwm0_evt_timer2_tep_st", &self.mcpwm0_evt_timer2_tep_st())
+            .field("mcpwm0_evt_op0_tea_st", &self.mcpwm0_evt_op0_tea_st())
+            .field("mcpwm0_evt_op1_tea_st", &self.mcpwm0_evt_op1_tea_st())
+            .field("mcpwm0_evt_op2_tea_st", &self.mcpwm0_evt_op2_tea_st())
+            .field("mcpwm0_evt_op0_teb_st", &self.mcpwm0_evt_op0_teb_st())
+            .field("mcpwm0_evt_op1_teb_st", &self.mcpwm0_evt_op1_teb_st())
+            .field("mcpwm0_evt_op2_teb_st", &self.mcpwm0_evt_op2_teb_st())
+            .field("mcpwm0_evt_f0_st", &self.mcpwm0_evt_f0_st())
+            .field("mcpwm0_evt_f1_st", &self.mcpwm0_evt_f1_st())
+            .field("mcpwm0_evt_f2_st", &self.mcpwm0_evt_f2_st())
+            .field("mcpwm0_evt_f0_clr_st", &self.mcpwm0_evt_f0_clr_st())
+            .field("mcpwm0_evt_f1_clr_st", &self.mcpwm0_evt_f1_clr_st())
+            .field("mcpwm0_evt_f2_clr_st", &self.mcpwm0_evt_f2_clr_st())
+            .field("mcpwm0_evt_tz0_cbc_st", &self.mcpwm0_evt_tz0_cbc_st())
+            .field("mcpwm0_evt_tz1_cbc_st", &self.mcpwm0_evt_tz1_cbc_st())
+            .field("mcpwm0_evt_tz2_cbc_st", &self.mcpwm0_evt_tz2_cbc_st())
+            .field("mcpwm0_evt_tz0_ost_st", &self.mcpwm0_evt_tz0_ost_st())
+            .field("mcpwm0_evt_tz1_ost_st", &self.mcpwm0_evt_tz1_ost_st())
+            .field("mcpwm0_evt_tz2_ost_st", &self.mcpwm0_evt_tz2_ost_st())
+            .field("mcpwm0_evt_cap0_st", &self.mcpwm0_evt_cap0_st())
+            .field("mcpwm0_evt_cap1_st", &self.mcpwm0_evt_cap1_st())
+            .field("mcpwm0_evt_cap2_st", &self.mcpwm0_evt_cap2_st())
+            .field("mcpwm0_evt_op0_tee1_st", &self.mcpwm0_evt_op0_tee1_st())
+            .field("mcpwm0_evt_op1_tee1_st", &self.mcpwm0_evt_op1_tee1_st())
+            .field("mcpwm0_evt_op2_tee1_st", &self.mcpwm0_evt_op2_tee1_st())
+            .field("mcpwm0_evt_op0_tee2_st", &self.mcpwm0_evt_op0_tee2_st())
+            .field("mcpwm0_evt_op1_tee2_st", &self.mcpwm0_evt_op1_tee2_st())
+            .field("mcpwm0_evt_op2_tee2_st", &self.mcpwm0_evt_op2_tee2_st())
             .field(
                 "mcpwm1_evt_timer0_stop_st",
-                &format_args!("{}", self.mcpwm1_evt_timer0_stop_st().bit()),
+                &self.mcpwm1_evt_timer0_stop_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_ST2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Represents MCPWM0_evt_timer2_tez trigger status.\\\\0: Not triggered\\\\1: Triggered"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/evt_st3.rs b/esp32p4/src/soc_etm/evt_st3.rs
index c57b6a5f1c..5e059b5c84 100644
--- a/esp32p4/src/soc_etm/evt_st3.rs
+++ b/esp32p4/src/soc_etm/evt_st3.rs
@@ -298,141 +298,45 @@ impl core::fmt::Debug for R {
         f.debug_struct("EVT_ST3")
             .field(
                 "mcpwm1_evt_timer1_stop_st",
-                &format_args!("{}", self.mcpwm1_evt_timer1_stop_st().bit()),
+                &self.mcpwm1_evt_timer1_stop_st(),
             )
             .field(
                 "mcpwm1_evt_timer2_stop_st",
-                &format_args!("{}", self.mcpwm1_evt_timer2_stop_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_timer0_tez_st",
-                &format_args!("{}", self.mcpwm1_evt_timer0_tez_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_timer1_tez_st",
-                &format_args!("{}", self.mcpwm1_evt_timer1_tez_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_timer2_tez_st",
-                &format_args!("{}", self.mcpwm1_evt_timer2_tez_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_timer0_tep_st",
-                &format_args!("{}", self.mcpwm1_evt_timer0_tep_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_timer1_tep_st",
-                &format_args!("{}", self.mcpwm1_evt_timer1_tep_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_timer2_tep_st",
-                &format_args!("{}", self.mcpwm1_evt_timer2_tep_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_op0_tea_st",
-                &format_args!("{}", self.mcpwm1_evt_op0_tea_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_op1_tea_st",
-                &format_args!("{}", self.mcpwm1_evt_op1_tea_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_op2_tea_st",
-                &format_args!("{}", self.mcpwm1_evt_op2_tea_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_op0_teb_st",
-                &format_args!("{}", self.mcpwm1_evt_op0_teb_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_op1_teb_st",
-                &format_args!("{}", self.mcpwm1_evt_op1_teb_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_op2_teb_st",
-                &format_args!("{}", self.mcpwm1_evt_op2_teb_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_f0_st",
-                &format_args!("{}", self.mcpwm1_evt_f0_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_f1_st",
-                &format_args!("{}", self.mcpwm1_evt_f1_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_f2_st",
-                &format_args!("{}", self.mcpwm1_evt_f2_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_f0_clr_st",
-                &format_args!("{}", self.mcpwm1_evt_f0_clr_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_f1_clr_st",
-                &format_args!("{}", self.mcpwm1_evt_f1_clr_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_f2_clr_st",
-                &format_args!("{}", self.mcpwm1_evt_f2_clr_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_tz0_cbc_st",
-                &format_args!("{}", self.mcpwm1_evt_tz0_cbc_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_tz1_cbc_st",
-                &format_args!("{}", self.mcpwm1_evt_tz1_cbc_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_tz2_cbc_st",
-                &format_args!("{}", self.mcpwm1_evt_tz2_cbc_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_tz0_ost_st",
-                &format_args!("{}", self.mcpwm1_evt_tz0_ost_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_tz1_ost_st",
-                &format_args!("{}", self.mcpwm1_evt_tz1_ost_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_tz2_ost_st",
-                &format_args!("{}", self.mcpwm1_evt_tz2_ost_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_cap0_st",
-                &format_args!("{}", self.mcpwm1_evt_cap0_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_cap1_st",
-                &format_args!("{}", self.mcpwm1_evt_cap1_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_cap2_st",
-                &format_args!("{}", self.mcpwm1_evt_cap2_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_op0_tee1_st",
-                &format_args!("{}", self.mcpwm1_evt_op0_tee1_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_op1_tee1_st",
-                &format_args!("{}", self.mcpwm1_evt_op1_tee1_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_op2_tee1_st",
-                &format_args!("{}", self.mcpwm1_evt_op2_tee1_st().bit()),
-            )
+                &self.mcpwm1_evt_timer2_stop_st(),
+            )
+            .field("mcpwm1_evt_timer0_tez_st", &self.mcpwm1_evt_timer0_tez_st())
+            .field("mcpwm1_evt_timer1_tez_st", &self.mcpwm1_evt_timer1_tez_st())
+            .field("mcpwm1_evt_timer2_tez_st", &self.mcpwm1_evt_timer2_tez_st())
+            .field("mcpwm1_evt_timer0_tep_st", &self.mcpwm1_evt_timer0_tep_st())
+            .field("mcpwm1_evt_timer1_tep_st", &self.mcpwm1_evt_timer1_tep_st())
+            .field("mcpwm1_evt_timer2_tep_st", &self.mcpwm1_evt_timer2_tep_st())
+            .field("mcpwm1_evt_op0_tea_st", &self.mcpwm1_evt_op0_tea_st())
+            .field("mcpwm1_evt_op1_tea_st", &self.mcpwm1_evt_op1_tea_st())
+            .field("mcpwm1_evt_op2_tea_st", &self.mcpwm1_evt_op2_tea_st())
+            .field("mcpwm1_evt_op0_teb_st", &self.mcpwm1_evt_op0_teb_st())
+            .field("mcpwm1_evt_op1_teb_st", &self.mcpwm1_evt_op1_teb_st())
+            .field("mcpwm1_evt_op2_teb_st", &self.mcpwm1_evt_op2_teb_st())
+            .field("mcpwm1_evt_f0_st", &self.mcpwm1_evt_f0_st())
+            .field("mcpwm1_evt_f1_st", &self.mcpwm1_evt_f1_st())
+            .field("mcpwm1_evt_f2_st", &self.mcpwm1_evt_f2_st())
+            .field("mcpwm1_evt_f0_clr_st", &self.mcpwm1_evt_f0_clr_st())
+            .field("mcpwm1_evt_f1_clr_st", &self.mcpwm1_evt_f1_clr_st())
+            .field("mcpwm1_evt_f2_clr_st", &self.mcpwm1_evt_f2_clr_st())
+            .field("mcpwm1_evt_tz0_cbc_st", &self.mcpwm1_evt_tz0_cbc_st())
+            .field("mcpwm1_evt_tz1_cbc_st", &self.mcpwm1_evt_tz1_cbc_st())
+            .field("mcpwm1_evt_tz2_cbc_st", &self.mcpwm1_evt_tz2_cbc_st())
+            .field("mcpwm1_evt_tz0_ost_st", &self.mcpwm1_evt_tz0_ost_st())
+            .field("mcpwm1_evt_tz1_ost_st", &self.mcpwm1_evt_tz1_ost_st())
+            .field("mcpwm1_evt_tz2_ost_st", &self.mcpwm1_evt_tz2_ost_st())
+            .field("mcpwm1_evt_cap0_st", &self.mcpwm1_evt_cap0_st())
+            .field("mcpwm1_evt_cap1_st", &self.mcpwm1_evt_cap1_st())
+            .field("mcpwm1_evt_cap2_st", &self.mcpwm1_evt_cap2_st())
+            .field("mcpwm1_evt_op0_tee1_st", &self.mcpwm1_evt_op0_tee1_st())
+            .field("mcpwm1_evt_op1_tee1_st", &self.mcpwm1_evt_op1_tee1_st())
+            .field("mcpwm1_evt_op2_tee1_st", &self.mcpwm1_evt_op2_tee1_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_ST3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Represents MCPWM1_evt_timer1_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/evt_st4.rs b/esp32p4/src/soc_etm/evt_st4.rs
index f16ebb3704..cff004e6e8 100644
--- a/esp32p4/src/soc_etm/evt_st4.rs
+++ b/esp32p4/src/soc_etm/evt_st4.rs
@@ -296,143 +296,65 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVT_ST4")
-            .field(
-                "mcpwm1_evt_op0_tee2_st",
-                &format_args!("{}", self.mcpwm1_evt_op0_tee2_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_op1_tee2_st",
-                &format_args!("{}", self.mcpwm1_evt_op1_tee2_st().bit()),
-            )
-            .field(
-                "mcpwm1_evt_op2_tee2_st",
-                &format_args!("{}", self.mcpwm1_evt_op2_tee2_st().bit()),
-            )
-            .field(
-                "adc_evt_conv_cmplt0_st",
-                &format_args!("{}", self.adc_evt_conv_cmplt0_st().bit()),
-            )
+            .field("mcpwm1_evt_op0_tee2_st", &self.mcpwm1_evt_op0_tee2_st())
+            .field("mcpwm1_evt_op1_tee2_st", &self.mcpwm1_evt_op1_tee2_st())
+            .field("mcpwm1_evt_op2_tee2_st", &self.mcpwm1_evt_op2_tee2_st())
+            .field("adc_evt_conv_cmplt0_st", &self.adc_evt_conv_cmplt0_st())
             .field(
                 "adc_evt_eq_above_thresh0_st",
-                &format_args!("{}", self.adc_evt_eq_above_thresh0_st().bit()),
+                &self.adc_evt_eq_above_thresh0_st(),
             )
             .field(
                 "adc_evt_eq_above_thresh1_st",
-                &format_args!("{}", self.adc_evt_eq_above_thresh1_st().bit()),
+                &self.adc_evt_eq_above_thresh1_st(),
             )
             .field(
                 "adc_evt_eq_below_thresh0_st",
-                &format_args!("{}", self.adc_evt_eq_below_thresh0_st().bit()),
+                &self.adc_evt_eq_below_thresh0_st(),
             )
             .field(
                 "adc_evt_eq_below_thresh1_st",
-                &format_args!("{}", self.adc_evt_eq_below_thresh1_st().bit()),
-            )
-            .field(
-                "adc_evt_result_done0_st",
-                &format_args!("{}", self.adc_evt_result_done0_st().bit()),
-            )
-            .field(
-                "adc_evt_stopped0_st",
-                &format_args!("{}", self.adc_evt_stopped0_st().bit()),
-            )
-            .field(
-                "adc_evt_started0_st",
-                &format_args!("{}", self.adc_evt_started0_st().bit()),
-            )
-            .field(
-                "regdma_evt_done0_st",
-                &format_args!("{}", self.regdma_evt_done0_st().bit()),
-            )
-            .field(
-                "regdma_evt_done1_st",
-                &format_args!("{}", self.regdma_evt_done1_st().bit()),
-            )
-            .field(
-                "regdma_evt_done2_st",
-                &format_args!("{}", self.regdma_evt_done2_st().bit()),
-            )
-            .field(
-                "regdma_evt_done3_st",
-                &format_args!("{}", self.regdma_evt_done3_st().bit()),
-            )
-            .field(
-                "regdma_evt_err0_st",
-                &format_args!("{}", self.regdma_evt_err0_st().bit()),
-            )
-            .field(
-                "regdma_evt_err1_st",
-                &format_args!("{}", self.regdma_evt_err1_st().bit()),
-            )
-            .field(
-                "regdma_evt_err2_st",
-                &format_args!("{}", self.regdma_evt_err2_st().bit()),
-            )
-            .field(
-                "regdma_evt_err3_st",
-                &format_args!("{}", self.regdma_evt_err3_st().bit()),
-            )
+                &self.adc_evt_eq_below_thresh1_st(),
+            )
+            .field("adc_evt_result_done0_st", &self.adc_evt_result_done0_st())
+            .field("adc_evt_stopped0_st", &self.adc_evt_stopped0_st())
+            .field("adc_evt_started0_st", &self.adc_evt_started0_st())
+            .field("regdma_evt_done0_st", &self.regdma_evt_done0_st())
+            .field("regdma_evt_done1_st", &self.regdma_evt_done1_st())
+            .field("regdma_evt_done2_st", &self.regdma_evt_done2_st())
+            .field("regdma_evt_done3_st", &self.regdma_evt_done3_st())
+            .field("regdma_evt_err0_st", &self.regdma_evt_err0_st())
+            .field("regdma_evt_err1_st", &self.regdma_evt_err1_st())
+            .field("regdma_evt_err2_st", &self.regdma_evt_err2_st())
+            .field("regdma_evt_err3_st", &self.regdma_evt_err3_st())
             .field(
                 "tmpsnsr_evt_over_limit_st",
-                &format_args!("{}", self.tmpsnsr_evt_over_limit_st().bit()),
-            )
-            .field(
-                "i2s0_evt_rx_done_st",
-                &format_args!("{}", self.i2s0_evt_rx_done_st().bit()),
-            )
-            .field(
-                "i2s0_evt_tx_done_st",
-                &format_args!("{}", self.i2s0_evt_tx_done_st().bit()),
+                &self.tmpsnsr_evt_over_limit_st(),
             )
+            .field("i2s0_evt_rx_done_st", &self.i2s0_evt_rx_done_st())
+            .field("i2s0_evt_tx_done_st", &self.i2s0_evt_tx_done_st())
             .field(
                 "i2s0_evt_x_words_received_st",
-                &format_args!("{}", self.i2s0_evt_x_words_received_st().bit()),
-            )
-            .field(
-                "i2s0_evt_x_words_sent_st",
-                &format_args!("{}", self.i2s0_evt_x_words_sent_st().bit()),
-            )
-            .field(
-                "i2s1_evt_rx_done_st",
-                &format_args!("{}", self.i2s1_evt_rx_done_st().bit()),
-            )
-            .field(
-                "i2s1_evt_tx_done_st",
-                &format_args!("{}", self.i2s1_evt_tx_done_st().bit()),
+                &self.i2s0_evt_x_words_received_st(),
             )
+            .field("i2s0_evt_x_words_sent_st", &self.i2s0_evt_x_words_sent_st())
+            .field("i2s1_evt_rx_done_st", &self.i2s1_evt_rx_done_st())
+            .field("i2s1_evt_tx_done_st", &self.i2s1_evt_tx_done_st())
             .field(
                 "i2s1_evt_x_words_received_st",
-                &format_args!("{}", self.i2s1_evt_x_words_received_st().bit()),
-            )
-            .field(
-                "i2s1_evt_x_words_sent_st",
-                &format_args!("{}", self.i2s1_evt_x_words_sent_st().bit()),
-            )
-            .field(
-                "i2s2_evt_rx_done_st",
-                &format_args!("{}", self.i2s2_evt_rx_done_st().bit()),
-            )
-            .field(
-                "i2s2_evt_tx_done_st",
-                &format_args!("{}", self.i2s2_evt_tx_done_st().bit()),
+                &self.i2s1_evt_x_words_received_st(),
             )
+            .field("i2s1_evt_x_words_sent_st", &self.i2s1_evt_x_words_sent_st())
+            .field("i2s2_evt_rx_done_st", &self.i2s2_evt_rx_done_st())
+            .field("i2s2_evt_tx_done_st", &self.i2s2_evt_tx_done_st())
             .field(
                 "i2s2_evt_x_words_received_st",
-                &format_args!("{}", self.i2s2_evt_x_words_received_st().bit()),
-            )
-            .field(
-                "i2s2_evt_x_words_sent_st",
-                &format_args!("{}", self.i2s2_evt_x_words_sent_st().bit()),
+                &self.i2s2_evt_x_words_received_st(),
             )
+            .field("i2s2_evt_x_words_sent_st", &self.i2s2_evt_x_words_sent_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_ST4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Represents MCPWM1_evt_op0_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/evt_st5.rs b/esp32p4/src/soc_etm/evt_st5.rs
index 692c732085..c95b440335 100644
--- a/esp32p4/src/soc_etm/evt_st5.rs
+++ b/esp32p4/src/soc_etm/evt_st5.rs
@@ -296,143 +296,119 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EVT_ST5")
-            .field(
-                "ulp_evt_err_intr_st",
-                &format_args!("{}", self.ulp_evt_err_intr_st().bit()),
-            )
-            .field(
-                "ulp_evt_halt_st",
-                &format_args!("{}", self.ulp_evt_halt_st().bit()),
-            )
-            .field(
-                "ulp_evt_start_intr_st",
-                &format_args!("{}", self.ulp_evt_start_intr_st().bit()),
-            )
-            .field(
-                "rtc_evt_tick_st",
-                &format_args!("{}", self.rtc_evt_tick_st().bit()),
-            )
-            .field(
-                "rtc_evt_ovf_st",
-                &format_args!("{}", self.rtc_evt_ovf_st().bit()),
-            )
-            .field(
-                "rtc_evt_cmp_st",
-                &format_args!("{}", self.rtc_evt_cmp_st().bit()),
-            )
+            .field("ulp_evt_err_intr_st", &self.ulp_evt_err_intr_st())
+            .field("ulp_evt_halt_st", &self.ulp_evt_halt_st())
+            .field("ulp_evt_start_intr_st", &self.ulp_evt_start_intr_st())
+            .field("rtc_evt_tick_st", &self.rtc_evt_tick_st())
+            .field("rtc_evt_ovf_st", &self.rtc_evt_ovf_st())
+            .field("rtc_evt_cmp_st", &self.rtc_evt_cmp_st())
             .field(
                 "pdma_ahb_evt_in_done_ch0_st",
-                &format_args!("{}", self.pdma_ahb_evt_in_done_ch0_st().bit()),
+                &self.pdma_ahb_evt_in_done_ch0_st(),
             )
             .field(
                 "pdma_ahb_evt_in_done_ch1_st",
-                &format_args!("{}", self.pdma_ahb_evt_in_done_ch1_st().bit()),
+                &self.pdma_ahb_evt_in_done_ch1_st(),
             )
             .field(
                 "pdma_ahb_evt_in_done_ch2_st",
-                &format_args!("{}", self.pdma_ahb_evt_in_done_ch2_st().bit()),
+                &self.pdma_ahb_evt_in_done_ch2_st(),
             )
             .field(
                 "pdma_ahb_evt_in_suc_eof_ch0_st",
-                &format_args!("{}", self.pdma_ahb_evt_in_suc_eof_ch0_st().bit()),
+                &self.pdma_ahb_evt_in_suc_eof_ch0_st(),
             )
             .field(
                 "pdma_ahb_evt_in_suc_eof_ch1_st",
-                &format_args!("{}", self.pdma_ahb_evt_in_suc_eof_ch1_st().bit()),
+                &self.pdma_ahb_evt_in_suc_eof_ch1_st(),
             )
             .field(
                 "pdma_ahb_evt_in_suc_eof_ch2_st",
-                &format_args!("{}", self.pdma_ahb_evt_in_suc_eof_ch2_st().bit()),
+                &self.pdma_ahb_evt_in_suc_eof_ch2_st(),
             )
             .field(
                 "pdma_ahb_evt_in_fifo_empty_ch0_st",
-                &format_args!("{}", self.pdma_ahb_evt_in_fifo_empty_ch0_st().bit()),
+                &self.pdma_ahb_evt_in_fifo_empty_ch0_st(),
             )
             .field(
                 "pdma_ahb_evt_in_fifo_empty_ch1_st",
-                &format_args!("{}", self.pdma_ahb_evt_in_fifo_empty_ch1_st().bit()),
+                &self.pdma_ahb_evt_in_fifo_empty_ch1_st(),
             )
             .field(
                 "pdma_ahb_evt_in_fifo_empty_ch2_st",
-                &format_args!("{}", self.pdma_ahb_evt_in_fifo_empty_ch2_st().bit()),
+                &self.pdma_ahb_evt_in_fifo_empty_ch2_st(),
             )
             .field(
                 "pdma_ahb_evt_in_fifo_full_ch0_st",
-                &format_args!("{}", self.pdma_ahb_evt_in_fifo_full_ch0_st().bit()),
+                &self.pdma_ahb_evt_in_fifo_full_ch0_st(),
             )
             .field(
                 "pdma_ahb_evt_in_fifo_full_ch1_st",
-                &format_args!("{}", self.pdma_ahb_evt_in_fifo_full_ch1_st().bit()),
+                &self.pdma_ahb_evt_in_fifo_full_ch1_st(),
             )
             .field(
                 "pdma_ahb_evt_in_fifo_full_ch2_st",
-                &format_args!("{}", self.pdma_ahb_evt_in_fifo_full_ch2_st().bit()),
+                &self.pdma_ahb_evt_in_fifo_full_ch2_st(),
             )
             .field(
                 "pdma_ahb_evt_out_done_ch0_st",
-                &format_args!("{}", self.pdma_ahb_evt_out_done_ch0_st().bit()),
+                &self.pdma_ahb_evt_out_done_ch0_st(),
             )
             .field(
                 "pdma_ahb_evt_out_done_ch1_st",
-                &format_args!("{}", self.pdma_ahb_evt_out_done_ch1_st().bit()),
+                &self.pdma_ahb_evt_out_done_ch1_st(),
             )
             .field(
                 "pdma_ahb_evt_out_done_ch2_st",
-                &format_args!("{}", self.pdma_ahb_evt_out_done_ch2_st().bit()),
+                &self.pdma_ahb_evt_out_done_ch2_st(),
             )
             .field(
                 "pdma_ahb_evt_out_eof_ch0_st",
-                &format_args!("{}", self.pdma_ahb_evt_out_eof_ch0_st().bit()),
+                &self.pdma_ahb_evt_out_eof_ch0_st(),
             )
             .field(
                 "pdma_ahb_evt_out_eof_ch1_st",
-                &format_args!("{}", self.pdma_ahb_evt_out_eof_ch1_st().bit()),
+                &self.pdma_ahb_evt_out_eof_ch1_st(),
             )
             .field(
                 "pdma_ahb_evt_out_eof_ch2_st",
-                &format_args!("{}", self.pdma_ahb_evt_out_eof_ch2_st().bit()),
+                &self.pdma_ahb_evt_out_eof_ch2_st(),
             )
             .field(
                 "pdma_ahb_evt_out_total_eof_ch0_st",
-                &format_args!("{}", self.pdma_ahb_evt_out_total_eof_ch0_st().bit()),
+                &self.pdma_ahb_evt_out_total_eof_ch0_st(),
             )
             .field(
                 "pdma_ahb_evt_out_total_eof_ch1_st",
-                &format_args!("{}", self.pdma_ahb_evt_out_total_eof_ch1_st().bit()),
+                &self.pdma_ahb_evt_out_total_eof_ch1_st(),
             )
             .field(
                 "pdma_ahb_evt_out_total_eof_ch2_st",
-                &format_args!("{}", self.pdma_ahb_evt_out_total_eof_ch2_st().bit()),
+                &self.pdma_ahb_evt_out_total_eof_ch2_st(),
             )
             .field(
                 "pdma_ahb_evt_out_fifo_empty_ch0_st",
-                &format_args!("{}", self.pdma_ahb_evt_out_fifo_empty_ch0_st().bit()),
+                &self.pdma_ahb_evt_out_fifo_empty_ch0_st(),
             )
             .field(
                 "pdma_ahb_evt_out_fifo_empty_ch1_st",
-                &format_args!("{}", self.pdma_ahb_evt_out_fifo_empty_ch1_st().bit()),
+                &self.pdma_ahb_evt_out_fifo_empty_ch1_st(),
             )
             .field(
                 "pdma_ahb_evt_out_fifo_empty_ch2_st",
-                &format_args!("{}", self.pdma_ahb_evt_out_fifo_empty_ch2_st().bit()),
+                &self.pdma_ahb_evt_out_fifo_empty_ch2_st(),
             )
             .field(
                 "pdma_ahb_evt_out_fifo_full_ch0_st",
-                &format_args!("{}", self.pdma_ahb_evt_out_fifo_full_ch0_st().bit()),
+                &self.pdma_ahb_evt_out_fifo_full_ch0_st(),
             )
             .field(
                 "pdma_ahb_evt_out_fifo_full_ch1_st",
-                &format_args!("{}", self.pdma_ahb_evt_out_fifo_full_ch1_st().bit()),
+                &self.pdma_ahb_evt_out_fifo_full_ch1_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_ST5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Represents ULP_evt_err_intr trigger status.\\\\0: Not triggered\\\\1: Triggered"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/evt_st6.rs b/esp32p4/src/soc_etm/evt_st6.rs
index 321b096157..2666af7070 100644
--- a/esp32p4/src/soc_etm/evt_st6.rs
+++ b/esp32p4/src/soc_etm/evt_st6.rs
@@ -298,141 +298,126 @@ impl core::fmt::Debug for R {
         f.debug_struct("EVT_ST6")
             .field(
                 "pdma_ahb_evt_out_fifo_full_ch2_st",
-                &format_args!("{}", self.pdma_ahb_evt_out_fifo_full_ch2_st().bit()),
+                &self.pdma_ahb_evt_out_fifo_full_ch2_st(),
             )
             .field(
                 "pdma_axi_evt_in_done_ch0_st",
-                &format_args!("{}", self.pdma_axi_evt_in_done_ch0_st().bit()),
+                &self.pdma_axi_evt_in_done_ch0_st(),
             )
             .field(
                 "pdma_axi_evt_in_done_ch1_st",
-                &format_args!("{}", self.pdma_axi_evt_in_done_ch1_st().bit()),
+                &self.pdma_axi_evt_in_done_ch1_st(),
             )
             .field(
                 "pdma_axi_evt_in_done_ch2_st",
-                &format_args!("{}", self.pdma_axi_evt_in_done_ch2_st().bit()),
+                &self.pdma_axi_evt_in_done_ch2_st(),
             )
             .field(
                 "pdma_axi_evt_in_suc_eof_ch0_st",
-                &format_args!("{}", self.pdma_axi_evt_in_suc_eof_ch0_st().bit()),
+                &self.pdma_axi_evt_in_suc_eof_ch0_st(),
             )
             .field(
                 "pdma_axi_evt_in_suc_eof_ch1_st",
-                &format_args!("{}", self.pdma_axi_evt_in_suc_eof_ch1_st().bit()),
+                &self.pdma_axi_evt_in_suc_eof_ch1_st(),
             )
             .field(
                 "pdma_axi_evt_in_suc_eof_ch2_st",
-                &format_args!("{}", self.pdma_axi_evt_in_suc_eof_ch2_st().bit()),
+                &self.pdma_axi_evt_in_suc_eof_ch2_st(),
             )
             .field(
                 "pdma_axi_evt_in_fifo_empty_ch0_st",
-                &format_args!("{}", self.pdma_axi_evt_in_fifo_empty_ch0_st().bit()),
+                &self.pdma_axi_evt_in_fifo_empty_ch0_st(),
             )
             .field(
                 "pdma_axi_evt_in_fifo_empty_ch1_st",
-                &format_args!("{}", self.pdma_axi_evt_in_fifo_empty_ch1_st().bit()),
+                &self.pdma_axi_evt_in_fifo_empty_ch1_st(),
             )
             .field(
                 "pdma_axi_evt_in_fifo_empty_ch2_st",
-                &format_args!("{}", self.pdma_axi_evt_in_fifo_empty_ch2_st().bit()),
+                &self.pdma_axi_evt_in_fifo_empty_ch2_st(),
             )
             .field(
                 "pdma_axi_evt_in_fifo_full_ch0_st",
-                &format_args!("{}", self.pdma_axi_evt_in_fifo_full_ch0_st().bit()),
+                &self.pdma_axi_evt_in_fifo_full_ch0_st(),
             )
             .field(
                 "pdma_axi_evt_in_fifo_full_ch1_st",
-                &format_args!("{}", self.pdma_axi_evt_in_fifo_full_ch1_st().bit()),
+                &self.pdma_axi_evt_in_fifo_full_ch1_st(),
             )
             .field(
                 "pdma_axi_evt_in_fifo_full_ch2_st",
-                &format_args!("{}", self.pdma_axi_evt_in_fifo_full_ch2_st().bit()),
+                &self.pdma_axi_evt_in_fifo_full_ch2_st(),
             )
             .field(
                 "pdma_axi_evt_out_done_ch0_st",
-                &format_args!("{}", self.pdma_axi_evt_out_done_ch0_st().bit()),
+                &self.pdma_axi_evt_out_done_ch0_st(),
             )
             .field(
                 "pdma_axi_evt_out_done_ch1_st",
-                &format_args!("{}", self.pdma_axi_evt_out_done_ch1_st().bit()),
+                &self.pdma_axi_evt_out_done_ch1_st(),
             )
             .field(
                 "pdma_axi_evt_out_done_ch2_st",
-                &format_args!("{}", self.pdma_axi_evt_out_done_ch2_st().bit()),
+                &self.pdma_axi_evt_out_done_ch2_st(),
             )
             .field(
                 "pdma_axi_evt_out_eof_ch0_st",
-                &format_args!("{}", self.pdma_axi_evt_out_eof_ch0_st().bit()),
+                &self.pdma_axi_evt_out_eof_ch0_st(),
             )
             .field(
                 "pdma_axi_evt_out_eof_ch1_st",
-                &format_args!("{}", self.pdma_axi_evt_out_eof_ch1_st().bit()),
+                &self.pdma_axi_evt_out_eof_ch1_st(),
             )
             .field(
                 "pdma_axi_evt_out_eof_ch2_st",
-                &format_args!("{}", self.pdma_axi_evt_out_eof_ch2_st().bit()),
+                &self.pdma_axi_evt_out_eof_ch2_st(),
             )
             .field(
                 "pdma_axi_evt_out_total_eof_ch0_st",
-                &format_args!("{}", self.pdma_axi_evt_out_total_eof_ch0_st().bit()),
+                &self.pdma_axi_evt_out_total_eof_ch0_st(),
             )
             .field(
                 "pdma_axi_evt_out_total_eof_ch1_st",
-                &format_args!("{}", self.pdma_axi_evt_out_total_eof_ch1_st().bit()),
+                &self.pdma_axi_evt_out_total_eof_ch1_st(),
             )
             .field(
                 "pdma_axi_evt_out_total_eof_ch2_st",
-                &format_args!("{}", self.pdma_axi_evt_out_total_eof_ch2_st().bit()),
+                &self.pdma_axi_evt_out_total_eof_ch2_st(),
             )
             .field(
                 "pdma_axi_evt_out_fifo_empty_ch0_st",
-                &format_args!("{}", self.pdma_axi_evt_out_fifo_empty_ch0_st().bit()),
+                &self.pdma_axi_evt_out_fifo_empty_ch0_st(),
             )
             .field(
                 "pdma_axi_evt_out_fifo_empty_ch1_st",
-                &format_args!("{}", self.pdma_axi_evt_out_fifo_empty_ch1_st().bit()),
+                &self.pdma_axi_evt_out_fifo_empty_ch1_st(),
             )
             .field(
                 "pdma_axi_evt_out_fifo_empty_ch2_st",
-                &format_args!("{}", self.pdma_axi_evt_out_fifo_empty_ch2_st().bit()),
+                &self.pdma_axi_evt_out_fifo_empty_ch2_st(),
             )
             .field(
                 "pdma_axi_evt_out_fifo_full_ch0_st",
-                &format_args!("{}", self.pdma_axi_evt_out_fifo_full_ch0_st().bit()),
+                &self.pdma_axi_evt_out_fifo_full_ch0_st(),
             )
             .field(
                 "pdma_axi_evt_out_fifo_full_ch1_st",
-                &format_args!("{}", self.pdma_axi_evt_out_fifo_full_ch1_st().bit()),
+                &self.pdma_axi_evt_out_fifo_full_ch1_st(),
             )
             .field(
                 "pdma_axi_evt_out_fifo_full_ch2_st",
-                &format_args!("{}", self.pdma_axi_evt_out_fifo_full_ch2_st().bit()),
-            )
-            .field(
-                "pmu_evt_sleep_weekup_st",
-                &format_args!("{}", self.pmu_evt_sleep_weekup_st().bit()),
-            )
-            .field(
-                "dma2d_evt_in_done_ch0_st",
-                &format_args!("{}", self.dma2d_evt_in_done_ch0_st().bit()),
-            )
-            .field(
-                "dma2d_evt_in_done_ch1_st",
-                &format_args!("{}", self.dma2d_evt_in_done_ch1_st().bit()),
+                &self.pdma_axi_evt_out_fifo_full_ch2_st(),
             )
+            .field("pmu_evt_sleep_weekup_st", &self.pmu_evt_sleep_weekup_st())
+            .field("dma2d_evt_in_done_ch0_st", &self.dma2d_evt_in_done_ch0_st())
+            .field("dma2d_evt_in_done_ch1_st", &self.dma2d_evt_in_done_ch1_st())
             .field(
                 "dma2d_evt_in_suc_eof_ch0_st",
-                &format_args!("{}", self.dma2d_evt_in_suc_eof_ch0_st().bit()),
+                &self.dma2d_evt_in_suc_eof_ch0_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_ST6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/evt_st7.rs b/esp32p4/src/soc_etm/evt_st7.rs
index 9fa88888f5..a3ec80abf4 100644
--- a/esp32p4/src/soc_etm/evt_st7.rs
+++ b/esp32p4/src/soc_etm/evt_st7.rs
@@ -100,53 +100,38 @@ impl core::fmt::Debug for R {
         f.debug_struct("EVT_ST7")
             .field(
                 "dma2d_evt_in_suc_eof_ch1_st",
-                &format_args!("{}", self.dma2d_evt_in_suc_eof_ch1_st().bit()),
+                &self.dma2d_evt_in_suc_eof_ch1_st(),
             )
             .field(
                 "dma2d_evt_out_done_ch0_st",
-                &format_args!("{}", self.dma2d_evt_out_done_ch0_st().bit()),
+                &self.dma2d_evt_out_done_ch0_st(),
             )
             .field(
                 "dma2d_evt_out_done_ch1_st",
-                &format_args!("{}", self.dma2d_evt_out_done_ch1_st().bit()),
+                &self.dma2d_evt_out_done_ch1_st(),
             )
             .field(
                 "dma2d_evt_out_done_ch2_st",
-                &format_args!("{}", self.dma2d_evt_out_done_ch2_st().bit()),
-            )
-            .field(
-                "dma2d_evt_out_eof_ch0_st",
-                &format_args!("{}", self.dma2d_evt_out_eof_ch0_st().bit()),
-            )
-            .field(
-                "dma2d_evt_out_eof_ch1_st",
-                &format_args!("{}", self.dma2d_evt_out_eof_ch1_st().bit()),
-            )
-            .field(
-                "dma2d_evt_out_eof_ch2_st",
-                &format_args!("{}", self.dma2d_evt_out_eof_ch2_st().bit()),
+                &self.dma2d_evt_out_done_ch2_st(),
             )
+            .field("dma2d_evt_out_eof_ch0_st", &self.dma2d_evt_out_eof_ch0_st())
+            .field("dma2d_evt_out_eof_ch1_st", &self.dma2d_evt_out_eof_ch1_st())
+            .field("dma2d_evt_out_eof_ch2_st", &self.dma2d_evt_out_eof_ch2_st())
             .field(
                 "dma2d_evt_out_total_eof_ch0_st",
-                &format_args!("{}", self.dma2d_evt_out_total_eof_ch0_st().bit()),
+                &self.dma2d_evt_out_total_eof_ch0_st(),
             )
             .field(
                 "dma2d_evt_out_total_eof_ch1_st",
-                &format_args!("{}", self.dma2d_evt_out_total_eof_ch1_st().bit()),
+                &self.dma2d_evt_out_total_eof_ch1_st(),
             )
             .field(
                 "dma2d_evt_out_total_eof_ch2_st",
-                &format_args!("{}", self.dma2d_evt_out_total_eof_ch2_st().bit()),
+                &self.dma2d_evt_out_total_eof_ch2_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EVT_ST7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Represents DMA2D_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/task_st0.rs b/esp32p4/src/soc_etm/task_st0.rs
index 8f9671b751..57ff054445 100644
--- a/esp32p4/src/soc_etm/task_st0.rs
+++ b/esp32p4/src/soc_etm/task_st0.rs
@@ -296,143 +296,65 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TASK_ST0")
-            .field(
-                "gpio_task_ch0_set_st",
-                &format_args!("{}", self.gpio_task_ch0_set_st().bit()),
-            )
-            .field(
-                "gpio_task_ch1_set_st",
-                &format_args!("{}", self.gpio_task_ch1_set_st().bit()),
-            )
-            .field(
-                "gpio_task_ch2_set_st",
-                &format_args!("{}", self.gpio_task_ch2_set_st().bit()),
-            )
-            .field(
-                "gpio_task_ch3_set_st",
-                &format_args!("{}", self.gpio_task_ch3_set_st().bit()),
-            )
-            .field(
-                "gpio_task_ch4_set_st",
-                &format_args!("{}", self.gpio_task_ch4_set_st().bit()),
-            )
-            .field(
-                "gpio_task_ch5_set_st",
-                &format_args!("{}", self.gpio_task_ch5_set_st().bit()),
-            )
-            .field(
-                "gpio_task_ch6_set_st",
-                &format_args!("{}", self.gpio_task_ch6_set_st().bit()),
-            )
-            .field(
-                "gpio_task_ch7_set_st",
-                &format_args!("{}", self.gpio_task_ch7_set_st().bit()),
-            )
-            .field(
-                "gpio_task_ch0_clear_st",
-                &format_args!("{}", self.gpio_task_ch0_clear_st().bit()),
-            )
-            .field(
-                "gpio_task_ch1_clear_st",
-                &format_args!("{}", self.gpio_task_ch1_clear_st().bit()),
-            )
-            .field(
-                "gpio_task_ch2_clear_st",
-                &format_args!("{}", self.gpio_task_ch2_clear_st().bit()),
-            )
-            .field(
-                "gpio_task_ch3_clear_st",
-                &format_args!("{}", self.gpio_task_ch3_clear_st().bit()),
-            )
-            .field(
-                "gpio_task_ch4_clear_st",
-                &format_args!("{}", self.gpio_task_ch4_clear_st().bit()),
-            )
-            .field(
-                "gpio_task_ch5_clear_st",
-                &format_args!("{}", self.gpio_task_ch5_clear_st().bit()),
-            )
-            .field(
-                "gpio_task_ch6_clear_st",
-                &format_args!("{}", self.gpio_task_ch6_clear_st().bit()),
-            )
-            .field(
-                "gpio_task_ch7_clear_st",
-                &format_args!("{}", self.gpio_task_ch7_clear_st().bit()),
-            )
-            .field(
-                "gpio_task_ch0_toggle_st",
-                &format_args!("{}", self.gpio_task_ch0_toggle_st().bit()),
-            )
-            .field(
-                "gpio_task_ch1_toggle_st",
-                &format_args!("{}", self.gpio_task_ch1_toggle_st().bit()),
-            )
-            .field(
-                "gpio_task_ch2_toggle_st",
-                &format_args!("{}", self.gpio_task_ch2_toggle_st().bit()),
-            )
-            .field(
-                "gpio_task_ch3_toggle_st",
-                &format_args!("{}", self.gpio_task_ch3_toggle_st().bit()),
-            )
-            .field(
-                "gpio_task_ch4_toggle_st",
-                &format_args!("{}", self.gpio_task_ch4_toggle_st().bit()),
-            )
-            .field(
-                "gpio_task_ch5_toggle_st",
-                &format_args!("{}", self.gpio_task_ch5_toggle_st().bit()),
-            )
-            .field(
-                "gpio_task_ch6_toggle_st",
-                &format_args!("{}", self.gpio_task_ch6_toggle_st().bit()),
-            )
-            .field(
-                "gpio_task_ch7_toggle_st",
-                &format_args!("{}", self.gpio_task_ch7_toggle_st().bit()),
-            )
+            .field("gpio_task_ch0_set_st", &self.gpio_task_ch0_set_st())
+            .field("gpio_task_ch1_set_st", &self.gpio_task_ch1_set_st())
+            .field("gpio_task_ch2_set_st", &self.gpio_task_ch2_set_st())
+            .field("gpio_task_ch3_set_st", &self.gpio_task_ch3_set_st())
+            .field("gpio_task_ch4_set_st", &self.gpio_task_ch4_set_st())
+            .field("gpio_task_ch5_set_st", &self.gpio_task_ch5_set_st())
+            .field("gpio_task_ch6_set_st", &self.gpio_task_ch6_set_st())
+            .field("gpio_task_ch7_set_st", &self.gpio_task_ch7_set_st())
+            .field("gpio_task_ch0_clear_st", &self.gpio_task_ch0_clear_st())
+            .field("gpio_task_ch1_clear_st", &self.gpio_task_ch1_clear_st())
+            .field("gpio_task_ch2_clear_st", &self.gpio_task_ch2_clear_st())
+            .field("gpio_task_ch3_clear_st", &self.gpio_task_ch3_clear_st())
+            .field("gpio_task_ch4_clear_st", &self.gpio_task_ch4_clear_st())
+            .field("gpio_task_ch5_clear_st", &self.gpio_task_ch5_clear_st())
+            .field("gpio_task_ch6_clear_st", &self.gpio_task_ch6_clear_st())
+            .field("gpio_task_ch7_clear_st", &self.gpio_task_ch7_clear_st())
+            .field("gpio_task_ch0_toggle_st", &self.gpio_task_ch0_toggle_st())
+            .field("gpio_task_ch1_toggle_st", &self.gpio_task_ch1_toggle_st())
+            .field("gpio_task_ch2_toggle_st", &self.gpio_task_ch2_toggle_st())
+            .field("gpio_task_ch3_toggle_st", &self.gpio_task_ch3_toggle_st())
+            .field("gpio_task_ch4_toggle_st", &self.gpio_task_ch4_toggle_st())
+            .field("gpio_task_ch5_toggle_st", &self.gpio_task_ch5_toggle_st())
+            .field("gpio_task_ch6_toggle_st", &self.gpio_task_ch6_toggle_st())
+            .field("gpio_task_ch7_toggle_st", &self.gpio_task_ch7_toggle_st())
             .field(
                 "ledc_task_timer0_res_update_st",
-                &format_args!("{}", self.ledc_task_timer0_res_update_st().bit()),
+                &self.ledc_task_timer0_res_update_st(),
             )
             .field(
                 "ledc_task_timer1_res_update_st",
-                &format_args!("{}", self.ledc_task_timer1_res_update_st().bit()),
+                &self.ledc_task_timer1_res_update_st(),
             )
             .field(
                 "ledc_task_timer2_res_update_st",
-                &format_args!("{}", self.ledc_task_timer2_res_update_st().bit()),
+                &self.ledc_task_timer2_res_update_st(),
             )
             .field(
                 "ledc_task_timer3_res_update_st",
-                &format_args!("{}", self.ledc_task_timer3_res_update_st().bit()),
+                &self.ledc_task_timer3_res_update_st(),
             )
             .field(
                 "ledc_task_duty_scale_update_ch0_st",
-                &format_args!("{}", self.ledc_task_duty_scale_update_ch0_st().bit()),
+                &self.ledc_task_duty_scale_update_ch0_st(),
             )
             .field(
                 "ledc_task_duty_scale_update_ch1_st",
-                &format_args!("{}", self.ledc_task_duty_scale_update_ch1_st().bit()),
+                &self.ledc_task_duty_scale_update_ch1_st(),
             )
             .field(
                 "ledc_task_duty_scale_update_ch2_st",
-                &format_args!("{}", self.ledc_task_duty_scale_update_ch2_st().bit()),
+                &self.ledc_task_duty_scale_update_ch2_st(),
             )
             .field(
                 "ledc_task_duty_scale_update_ch3_st",
-                &format_args!("{}", self.ledc_task_duty_scale_update_ch3_st().bit()),
+                &self.ledc_task_duty_scale_update_ch3_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TASK_ST0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Represents GPIO_task_ch0_set trigger status.\\\\0: Not triggered\\\\1: Triggered"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/task_st1.rs b/esp32p4/src/soc_etm/task_st1.rs
index 067bbca5a7..b9811e4efd 100644
--- a/esp32p4/src/soc_etm/task_st1.rs
+++ b/esp32p4/src/soc_etm/task_st1.rs
@@ -298,141 +298,111 @@ impl core::fmt::Debug for R {
         f.debug_struct("TASK_ST1")
             .field(
                 "ledc_task_duty_scale_update_ch4_st",
-                &format_args!("{}", self.ledc_task_duty_scale_update_ch4_st().bit()),
+                &self.ledc_task_duty_scale_update_ch4_st(),
             )
             .field(
                 "ledc_task_duty_scale_update_ch5_st",
-                &format_args!("{}", self.ledc_task_duty_scale_update_ch5_st().bit()),
+                &self.ledc_task_duty_scale_update_ch5_st(),
             )
             .field(
                 "ledc_task_duty_scale_update_ch6_st",
-                &format_args!("{}", self.ledc_task_duty_scale_update_ch6_st().bit()),
+                &self.ledc_task_duty_scale_update_ch6_st(),
             )
             .field(
                 "ledc_task_duty_scale_update_ch7_st",
-                &format_args!("{}", self.ledc_task_duty_scale_update_ch7_st().bit()),
-            )
-            .field(
-                "ledc_task_timer0_cap_st",
-                &format_args!("{}", self.ledc_task_timer0_cap_st().bit()),
-            )
-            .field(
-                "ledc_task_timer1_cap_st",
-                &format_args!("{}", self.ledc_task_timer1_cap_st().bit()),
-            )
-            .field(
-                "ledc_task_timer2_cap_st",
-                &format_args!("{}", self.ledc_task_timer2_cap_st().bit()),
-            )
-            .field(
-                "ledc_task_timer3_cap_st",
-                &format_args!("{}", self.ledc_task_timer3_cap_st().bit()),
+                &self.ledc_task_duty_scale_update_ch7_st(),
             )
+            .field("ledc_task_timer0_cap_st", &self.ledc_task_timer0_cap_st())
+            .field("ledc_task_timer1_cap_st", &self.ledc_task_timer1_cap_st())
+            .field("ledc_task_timer2_cap_st", &self.ledc_task_timer2_cap_st())
+            .field("ledc_task_timer3_cap_st", &self.ledc_task_timer3_cap_st())
             .field(
                 "ledc_task_sig_out_dis_ch0_st",
-                &format_args!("{}", self.ledc_task_sig_out_dis_ch0_st().bit()),
+                &self.ledc_task_sig_out_dis_ch0_st(),
             )
             .field(
                 "ledc_task_sig_out_dis_ch1_st",
-                &format_args!("{}", self.ledc_task_sig_out_dis_ch1_st().bit()),
+                &self.ledc_task_sig_out_dis_ch1_st(),
             )
             .field(
                 "ledc_task_sig_out_dis_ch2_st",
-                &format_args!("{}", self.ledc_task_sig_out_dis_ch2_st().bit()),
+                &self.ledc_task_sig_out_dis_ch2_st(),
             )
             .field(
                 "ledc_task_sig_out_dis_ch3_st",
-                &format_args!("{}", self.ledc_task_sig_out_dis_ch3_st().bit()),
+                &self.ledc_task_sig_out_dis_ch3_st(),
             )
             .field(
                 "ledc_task_sig_out_dis_ch4_st",
-                &format_args!("{}", self.ledc_task_sig_out_dis_ch4_st().bit()),
+                &self.ledc_task_sig_out_dis_ch4_st(),
             )
             .field(
                 "ledc_task_sig_out_dis_ch5_st",
-                &format_args!("{}", self.ledc_task_sig_out_dis_ch5_st().bit()),
+                &self.ledc_task_sig_out_dis_ch5_st(),
             )
             .field(
                 "ledc_task_sig_out_dis_ch6_st",
-                &format_args!("{}", self.ledc_task_sig_out_dis_ch6_st().bit()),
+                &self.ledc_task_sig_out_dis_ch6_st(),
             )
             .field(
                 "ledc_task_sig_out_dis_ch7_st",
-                &format_args!("{}", self.ledc_task_sig_out_dis_ch7_st().bit()),
+                &self.ledc_task_sig_out_dis_ch7_st(),
             )
             .field(
                 "ledc_task_ovf_cnt_rst_ch0_st",
-                &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch0_st().bit()),
+                &self.ledc_task_ovf_cnt_rst_ch0_st(),
             )
             .field(
                 "ledc_task_ovf_cnt_rst_ch1_st",
-                &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch1_st().bit()),
+                &self.ledc_task_ovf_cnt_rst_ch1_st(),
             )
             .field(
                 "ledc_task_ovf_cnt_rst_ch2_st",
-                &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch2_st().bit()),
+                &self.ledc_task_ovf_cnt_rst_ch2_st(),
             )
             .field(
                 "ledc_task_ovf_cnt_rst_ch3_st",
-                &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch3_st().bit()),
+                &self.ledc_task_ovf_cnt_rst_ch3_st(),
             )
             .field(
                 "ledc_task_ovf_cnt_rst_ch4_st",
-                &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch4_st().bit()),
+                &self.ledc_task_ovf_cnt_rst_ch4_st(),
             )
             .field(
                 "ledc_task_ovf_cnt_rst_ch5_st",
-                &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch5_st().bit()),
+                &self.ledc_task_ovf_cnt_rst_ch5_st(),
             )
             .field(
                 "ledc_task_ovf_cnt_rst_ch6_st",
-                &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch6_st().bit()),
+                &self.ledc_task_ovf_cnt_rst_ch6_st(),
             )
             .field(
                 "ledc_task_ovf_cnt_rst_ch7_st",
-                &format_args!("{}", self.ledc_task_ovf_cnt_rst_ch7_st().bit()),
-            )
-            .field(
-                "ledc_task_timer0_rst_st",
-                &format_args!("{}", self.ledc_task_timer0_rst_st().bit()),
-            )
-            .field(
-                "ledc_task_timer1_rst_st",
-                &format_args!("{}", self.ledc_task_timer1_rst_st().bit()),
-            )
-            .field(
-                "ledc_task_timer2_rst_st",
-                &format_args!("{}", self.ledc_task_timer2_rst_st().bit()),
-            )
-            .field(
-                "ledc_task_timer3_rst_st",
-                &format_args!("{}", self.ledc_task_timer3_rst_st().bit()),
+                &self.ledc_task_ovf_cnt_rst_ch7_st(),
             )
+            .field("ledc_task_timer0_rst_st", &self.ledc_task_timer0_rst_st())
+            .field("ledc_task_timer1_rst_st", &self.ledc_task_timer1_rst_st())
+            .field("ledc_task_timer2_rst_st", &self.ledc_task_timer2_rst_st())
+            .field("ledc_task_timer3_rst_st", &self.ledc_task_timer3_rst_st())
             .field(
                 "ledc_task_timer0_resume_st",
-                &format_args!("{}", self.ledc_task_timer0_resume_st().bit()),
+                &self.ledc_task_timer0_resume_st(),
             )
             .field(
                 "ledc_task_timer1_resume_st",
-                &format_args!("{}", self.ledc_task_timer1_resume_st().bit()),
+                &self.ledc_task_timer1_resume_st(),
             )
             .field(
                 "ledc_task_timer2_resume_st",
-                &format_args!("{}", self.ledc_task_timer2_resume_st().bit()),
+                &self.ledc_task_timer2_resume_st(),
             )
             .field(
                 "ledc_task_timer3_resume_st",
-                &format_args!("{}", self.ledc_task_timer3_resume_st().bit()),
+                &self.ledc_task_timer3_resume_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TASK_ST1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Represents LEDC_task_duty_scale_update_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/task_st2.rs b/esp32p4/src/soc_etm/task_st2.rs
index 5cbd2b0e0e..356b05aaaf 100644
--- a/esp32p4/src/soc_etm/task_st2.rs
+++ b/esp32p4/src/soc_etm/task_st2.rs
@@ -298,141 +298,135 @@ impl core::fmt::Debug for R {
         f.debug_struct("TASK_ST2")
             .field(
                 "ledc_task_timer0_pause_st",
-                &format_args!("{}", self.ledc_task_timer0_pause_st().bit()),
+                &self.ledc_task_timer0_pause_st(),
             )
             .field(
                 "ledc_task_timer1_pause_st",
-                &format_args!("{}", self.ledc_task_timer1_pause_st().bit()),
+                &self.ledc_task_timer1_pause_st(),
             )
             .field(
                 "ledc_task_timer2_pause_st",
-                &format_args!("{}", self.ledc_task_timer2_pause_st().bit()),
+                &self.ledc_task_timer2_pause_st(),
             )
             .field(
                 "ledc_task_timer3_pause_st",
-                &format_args!("{}", self.ledc_task_timer3_pause_st().bit()),
+                &self.ledc_task_timer3_pause_st(),
             )
             .field(
                 "ledc_task_gamma_restart_ch0_st",
-                &format_args!("{}", self.ledc_task_gamma_restart_ch0_st().bit()),
+                &self.ledc_task_gamma_restart_ch0_st(),
             )
             .field(
                 "ledc_task_gamma_restart_ch1_st",
-                &format_args!("{}", self.ledc_task_gamma_restart_ch1_st().bit()),
+                &self.ledc_task_gamma_restart_ch1_st(),
             )
             .field(
                 "ledc_task_gamma_restart_ch2_st",
-                &format_args!("{}", self.ledc_task_gamma_restart_ch2_st().bit()),
+                &self.ledc_task_gamma_restart_ch2_st(),
             )
             .field(
                 "ledc_task_gamma_restart_ch3_st",
-                &format_args!("{}", self.ledc_task_gamma_restart_ch3_st().bit()),
+                &self.ledc_task_gamma_restart_ch3_st(),
             )
             .field(
                 "ledc_task_gamma_restart_ch4_st",
-                &format_args!("{}", self.ledc_task_gamma_restart_ch4_st().bit()),
+                &self.ledc_task_gamma_restart_ch4_st(),
             )
             .field(
                 "ledc_task_gamma_restart_ch5_st",
-                &format_args!("{}", self.ledc_task_gamma_restart_ch5_st().bit()),
+                &self.ledc_task_gamma_restart_ch5_st(),
             )
             .field(
                 "ledc_task_gamma_restart_ch6_st",
-                &format_args!("{}", self.ledc_task_gamma_restart_ch6_st().bit()),
+                &self.ledc_task_gamma_restart_ch6_st(),
             )
             .field(
                 "ledc_task_gamma_restart_ch7_st",
-                &format_args!("{}", self.ledc_task_gamma_restart_ch7_st().bit()),
+                &self.ledc_task_gamma_restart_ch7_st(),
             )
             .field(
                 "ledc_task_gamma_pause_ch0_st",
-                &format_args!("{}", self.ledc_task_gamma_pause_ch0_st().bit()),
+                &self.ledc_task_gamma_pause_ch0_st(),
             )
             .field(
                 "ledc_task_gamma_pause_ch1_st",
-                &format_args!("{}", self.ledc_task_gamma_pause_ch1_st().bit()),
+                &self.ledc_task_gamma_pause_ch1_st(),
             )
             .field(
                 "ledc_task_gamma_pause_ch2_st",
-                &format_args!("{}", self.ledc_task_gamma_pause_ch2_st().bit()),
+                &self.ledc_task_gamma_pause_ch2_st(),
             )
             .field(
                 "ledc_task_gamma_pause_ch3_st",
-                &format_args!("{}", self.ledc_task_gamma_pause_ch3_st().bit()),
+                &self.ledc_task_gamma_pause_ch3_st(),
             )
             .field(
                 "ledc_task_gamma_pause_ch4_st",
-                &format_args!("{}", self.ledc_task_gamma_pause_ch4_st().bit()),
+                &self.ledc_task_gamma_pause_ch4_st(),
             )
             .field(
                 "ledc_task_gamma_pause_ch5_st",
-                &format_args!("{}", self.ledc_task_gamma_pause_ch5_st().bit()),
+                &self.ledc_task_gamma_pause_ch5_st(),
             )
             .field(
                 "ledc_task_gamma_pause_ch6_st",
-                &format_args!("{}", self.ledc_task_gamma_pause_ch6_st().bit()),
+                &self.ledc_task_gamma_pause_ch6_st(),
             )
             .field(
                 "ledc_task_gamma_pause_ch7_st",
-                &format_args!("{}", self.ledc_task_gamma_pause_ch7_st().bit()),
+                &self.ledc_task_gamma_pause_ch7_st(),
             )
             .field(
                 "ledc_task_gamma_resume_ch0_st",
-                &format_args!("{}", self.ledc_task_gamma_resume_ch0_st().bit()),
+                &self.ledc_task_gamma_resume_ch0_st(),
             )
             .field(
                 "ledc_task_gamma_resume_ch1_st",
-                &format_args!("{}", self.ledc_task_gamma_resume_ch1_st().bit()),
+                &self.ledc_task_gamma_resume_ch1_st(),
             )
             .field(
                 "ledc_task_gamma_resume_ch2_st",
-                &format_args!("{}", self.ledc_task_gamma_resume_ch2_st().bit()),
+                &self.ledc_task_gamma_resume_ch2_st(),
             )
             .field(
                 "ledc_task_gamma_resume_ch3_st",
-                &format_args!("{}", self.ledc_task_gamma_resume_ch3_st().bit()),
+                &self.ledc_task_gamma_resume_ch3_st(),
             )
             .field(
                 "ledc_task_gamma_resume_ch4_st",
-                &format_args!("{}", self.ledc_task_gamma_resume_ch4_st().bit()),
+                &self.ledc_task_gamma_resume_ch4_st(),
             )
             .field(
                 "ledc_task_gamma_resume_ch5_st",
-                &format_args!("{}", self.ledc_task_gamma_resume_ch5_st().bit()),
+                &self.ledc_task_gamma_resume_ch5_st(),
             )
             .field(
                 "ledc_task_gamma_resume_ch6_st",
-                &format_args!("{}", self.ledc_task_gamma_resume_ch6_st().bit()),
+                &self.ledc_task_gamma_resume_ch6_st(),
             )
             .field(
                 "ledc_task_gamma_resume_ch7_st",
-                &format_args!("{}", self.ledc_task_gamma_resume_ch7_st().bit()),
+                &self.ledc_task_gamma_resume_ch7_st(),
             )
             .field(
                 "tg0_task_cnt_start_timer0_st",
-                &format_args!("{}", self.tg0_task_cnt_start_timer0_st().bit()),
+                &self.tg0_task_cnt_start_timer0_st(),
             )
             .field(
                 "tg0_task_alarm_start_timer0_st",
-                &format_args!("{}", self.tg0_task_alarm_start_timer0_st().bit()),
+                &self.tg0_task_alarm_start_timer0_st(),
             )
             .field(
                 "tg0_task_cnt_stop_timer0_st",
-                &format_args!("{}", self.tg0_task_cnt_stop_timer0_st().bit()),
+                &self.tg0_task_cnt_stop_timer0_st(),
             )
             .field(
                 "tg0_task_cnt_reload_timer0_st",
-                &format_args!("{}", self.tg0_task_cnt_reload_timer0_st().bit()),
+                &self.tg0_task_cnt_reload_timer0_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TASK_ST2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Represents LEDC_task_timer0_pause trigger status.\\\\0: Not triggered\\\\1: Triggered"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/task_st3.rs b/esp32p4/src/soc_etm/task_st3.rs
index e307e22270..14f85fb34e 100644
--- a/esp32p4/src/soc_etm/task_st3.rs
+++ b/esp32p4/src/soc_etm/task_st3.rs
@@ -298,141 +298,123 @@ impl core::fmt::Debug for R {
         f.debug_struct("TASK_ST3")
             .field(
                 "tg0_task_cnt_cap_timer0_st",
-                &format_args!("{}", self.tg0_task_cnt_cap_timer0_st().bit()),
+                &self.tg0_task_cnt_cap_timer0_st(),
             )
             .field(
                 "tg0_task_cnt_start_timer1_st",
-                &format_args!("{}", self.tg0_task_cnt_start_timer1_st().bit()),
+                &self.tg0_task_cnt_start_timer1_st(),
             )
             .field(
                 "tg0_task_alarm_start_timer1_st",
-                &format_args!("{}", self.tg0_task_alarm_start_timer1_st().bit()),
+                &self.tg0_task_alarm_start_timer1_st(),
             )
             .field(
                 "tg0_task_cnt_stop_timer1_st",
-                &format_args!("{}", self.tg0_task_cnt_stop_timer1_st().bit()),
+                &self.tg0_task_cnt_stop_timer1_st(),
             )
             .field(
                 "tg0_task_cnt_reload_timer1_st",
-                &format_args!("{}", self.tg0_task_cnt_reload_timer1_st().bit()),
+                &self.tg0_task_cnt_reload_timer1_st(),
             )
             .field(
                 "tg0_task_cnt_cap_timer1_st",
-                &format_args!("{}", self.tg0_task_cnt_cap_timer1_st().bit()),
+                &self.tg0_task_cnt_cap_timer1_st(),
             )
             .field(
                 "tg1_task_cnt_start_timer0_st",
-                &format_args!("{}", self.tg1_task_cnt_start_timer0_st().bit()),
+                &self.tg1_task_cnt_start_timer0_st(),
             )
             .field(
                 "tg1_task_alarm_start_timer0_st",
-                &format_args!("{}", self.tg1_task_alarm_start_timer0_st().bit()),
+                &self.tg1_task_alarm_start_timer0_st(),
             )
             .field(
                 "tg1_task_cnt_stop_timer0_st",
-                &format_args!("{}", self.tg1_task_cnt_stop_timer0_st().bit()),
+                &self.tg1_task_cnt_stop_timer0_st(),
             )
             .field(
                 "tg1_task_cnt_reload_timer0_st",
-                &format_args!("{}", self.tg1_task_cnt_reload_timer0_st().bit()),
+                &self.tg1_task_cnt_reload_timer0_st(),
             )
             .field(
                 "tg1_task_cnt_cap_timer0_st",
-                &format_args!("{}", self.tg1_task_cnt_cap_timer0_st().bit()),
+                &self.tg1_task_cnt_cap_timer0_st(),
             )
             .field(
                 "tg1_task_cnt_start_timer1_st",
-                &format_args!("{}", self.tg1_task_cnt_start_timer1_st().bit()),
+                &self.tg1_task_cnt_start_timer1_st(),
             )
             .field(
                 "tg1_task_alarm_start_timer1_st",
-                &format_args!("{}", self.tg1_task_alarm_start_timer1_st().bit()),
+                &self.tg1_task_alarm_start_timer1_st(),
             )
             .field(
                 "tg1_task_cnt_stop_timer1_st",
-                &format_args!("{}", self.tg1_task_cnt_stop_timer1_st().bit()),
+                &self.tg1_task_cnt_stop_timer1_st(),
             )
             .field(
                 "tg1_task_cnt_reload_timer1_st",
-                &format_args!("{}", self.tg1_task_cnt_reload_timer1_st().bit()),
+                &self.tg1_task_cnt_reload_timer1_st(),
             )
             .field(
                 "tg1_task_cnt_cap_timer1_st",
-                &format_args!("{}", self.tg1_task_cnt_cap_timer1_st().bit()),
+                &self.tg1_task_cnt_cap_timer1_st(),
             )
             .field(
                 "mcpwm0_task_cmpr0_a_up_st",
-                &format_args!("{}", self.mcpwm0_task_cmpr0_a_up_st().bit()),
+                &self.mcpwm0_task_cmpr0_a_up_st(),
             )
             .field(
                 "mcpwm0_task_cmpr1_a_up_st",
-                &format_args!("{}", self.mcpwm0_task_cmpr1_a_up_st().bit()),
+                &self.mcpwm0_task_cmpr1_a_up_st(),
             )
             .field(
                 "mcpwm0_task_cmpr2_a_up_st",
-                &format_args!("{}", self.mcpwm0_task_cmpr2_a_up_st().bit()),
+                &self.mcpwm0_task_cmpr2_a_up_st(),
             )
             .field(
                 "mcpwm0_task_cmpr0_b_up_st",
-                &format_args!("{}", self.mcpwm0_task_cmpr0_b_up_st().bit()),
+                &self.mcpwm0_task_cmpr0_b_up_st(),
             )
             .field(
                 "mcpwm0_task_cmpr1_b_up_st",
-                &format_args!("{}", self.mcpwm0_task_cmpr1_b_up_st().bit()),
+                &self.mcpwm0_task_cmpr1_b_up_st(),
             )
             .field(
                 "mcpwm0_task_cmpr2_b_up_st",
-                &format_args!("{}", self.mcpwm0_task_cmpr2_b_up_st().bit()),
-            )
-            .field(
-                "mcpwm0_task_gen_stop_st",
-                &format_args!("{}", self.mcpwm0_task_gen_stop_st().bit()),
+                &self.mcpwm0_task_cmpr2_b_up_st(),
             )
+            .field("mcpwm0_task_gen_stop_st", &self.mcpwm0_task_gen_stop_st())
             .field(
                 "mcpwm0_task_timer0_syn_st",
-                &format_args!("{}", self.mcpwm0_task_timer0_syn_st().bit()),
+                &self.mcpwm0_task_timer0_syn_st(),
             )
             .field(
                 "mcpwm0_task_timer1_syn_st",
-                &format_args!("{}", self.mcpwm0_task_timer1_syn_st().bit()),
+                &self.mcpwm0_task_timer1_syn_st(),
             )
             .field(
                 "mcpwm0_task_timer2_syn_st",
-                &format_args!("{}", self.mcpwm0_task_timer2_syn_st().bit()),
+                &self.mcpwm0_task_timer2_syn_st(),
             )
             .field(
                 "mcpwm0_task_timer0_period_up_st",
-                &format_args!("{}", self.mcpwm0_task_timer0_period_up_st().bit()),
+                &self.mcpwm0_task_timer0_period_up_st(),
             )
             .field(
                 "mcpwm0_task_timer1_period_up_st",
-                &format_args!("{}", self.mcpwm0_task_timer1_period_up_st().bit()),
+                &self.mcpwm0_task_timer1_period_up_st(),
             )
             .field(
                 "mcpwm0_task_timer2_period_up_st",
-                &format_args!("{}", self.mcpwm0_task_timer2_period_up_st().bit()),
-            )
-            .field(
-                "mcpwm0_task_tz0_ost_st",
-                &format_args!("{}", self.mcpwm0_task_tz0_ost_st().bit()),
-            )
-            .field(
-                "mcpwm0_task_tz1_ost_st",
-                &format_args!("{}", self.mcpwm0_task_tz1_ost_st().bit()),
-            )
-            .field(
-                "mcpwm0_task_tz2_ost_st",
-                &format_args!("{}", self.mcpwm0_task_tz2_ost_st().bit()),
+                &self.mcpwm0_task_timer2_period_up_st(),
             )
+            .field("mcpwm0_task_tz0_ost_st", &self.mcpwm0_task_tz0_ost_st())
+            .field("mcpwm0_task_tz1_ost_st", &self.mcpwm0_task_tz1_ost_st())
+            .field("mcpwm0_task_tz2_ost_st", &self.mcpwm0_task_tz2_ost_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TASK_ST3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Represents TG0_task_cnt_cap_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/task_st4.rs b/esp32p4/src/soc_etm/task_st4.rs
index c2de911134..cf2f2f14e6 100644
--- a/esp32p4/src/soc_etm/task_st4.rs
+++ b/esp32p4/src/soc_etm/task_st4.rs
@@ -296,143 +296,77 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TASK_ST4")
-            .field(
-                "mcpwm0_task_clr0_ost_st",
-                &format_args!("{}", self.mcpwm0_task_clr0_ost_st().bit()),
-            )
-            .field(
-                "mcpwm0_task_clr1_ost_st",
-                &format_args!("{}", self.mcpwm0_task_clr1_ost_st().bit()),
-            )
-            .field(
-                "mcpwm0_task_clr2_ost_st",
-                &format_args!("{}", self.mcpwm0_task_clr2_ost_st().bit()),
-            )
-            .field(
-                "mcpwm0_task_cap0_st",
-                &format_args!("{}", self.mcpwm0_task_cap0_st().bit()),
-            )
-            .field(
-                "mcpwm0_task_cap1_st",
-                &format_args!("{}", self.mcpwm0_task_cap1_st().bit()),
-            )
-            .field(
-                "mcpwm0_task_cap2_st",
-                &format_args!("{}", self.mcpwm0_task_cap2_st().bit()),
-            )
+            .field("mcpwm0_task_clr0_ost_st", &self.mcpwm0_task_clr0_ost_st())
+            .field("mcpwm0_task_clr1_ost_st", &self.mcpwm0_task_clr1_ost_st())
+            .field("mcpwm0_task_clr2_ost_st", &self.mcpwm0_task_clr2_ost_st())
+            .field("mcpwm0_task_cap0_st", &self.mcpwm0_task_cap0_st())
+            .field("mcpwm0_task_cap1_st", &self.mcpwm0_task_cap1_st())
+            .field("mcpwm0_task_cap2_st", &self.mcpwm0_task_cap2_st())
             .field(
                 "mcpwm1_task_cmpr0_a_up_st",
-                &format_args!("{}", self.mcpwm1_task_cmpr0_a_up_st().bit()),
+                &self.mcpwm1_task_cmpr0_a_up_st(),
             )
             .field(
                 "mcpwm1_task_cmpr1_a_up_st",
-                &format_args!("{}", self.mcpwm1_task_cmpr1_a_up_st().bit()),
+                &self.mcpwm1_task_cmpr1_a_up_st(),
             )
             .field(
                 "mcpwm1_task_cmpr2_a_up_st",
-                &format_args!("{}", self.mcpwm1_task_cmpr2_a_up_st().bit()),
+                &self.mcpwm1_task_cmpr2_a_up_st(),
             )
             .field(
                 "mcpwm1_task_cmpr0_b_up_st",
-                &format_args!("{}", self.mcpwm1_task_cmpr0_b_up_st().bit()),
+                &self.mcpwm1_task_cmpr0_b_up_st(),
             )
             .field(
                 "mcpwm1_task_cmpr1_b_up_st",
-                &format_args!("{}", self.mcpwm1_task_cmpr1_b_up_st().bit()),
+                &self.mcpwm1_task_cmpr1_b_up_st(),
             )
             .field(
                 "mcpwm1_task_cmpr2_b_up_st",
-                &format_args!("{}", self.mcpwm1_task_cmpr2_b_up_st().bit()),
-            )
-            .field(
-                "mcpwm1_task_gen_stop_st",
-                &format_args!("{}", self.mcpwm1_task_gen_stop_st().bit()),
+                &self.mcpwm1_task_cmpr2_b_up_st(),
             )
+            .field("mcpwm1_task_gen_stop_st", &self.mcpwm1_task_gen_stop_st())
             .field(
                 "mcpwm1_task_timer0_syn_st",
-                &format_args!("{}", self.mcpwm1_task_timer0_syn_st().bit()),
+                &self.mcpwm1_task_timer0_syn_st(),
             )
             .field(
                 "mcpwm1_task_timer1_syn_st",
-                &format_args!("{}", self.mcpwm1_task_timer1_syn_st().bit()),
+                &self.mcpwm1_task_timer1_syn_st(),
             )
             .field(
                 "mcpwm1_task_timer2_syn_st",
-                &format_args!("{}", self.mcpwm1_task_timer2_syn_st().bit()),
+                &self.mcpwm1_task_timer2_syn_st(),
             )
             .field(
                 "mcpwm1_task_timer0_period_up_st",
-                &format_args!("{}", self.mcpwm1_task_timer0_period_up_st().bit()),
+                &self.mcpwm1_task_timer0_period_up_st(),
             )
             .field(
                 "mcpwm1_task_timer1_period_up_st",
-                &format_args!("{}", self.mcpwm1_task_timer1_period_up_st().bit()),
+                &self.mcpwm1_task_timer1_period_up_st(),
             )
             .field(
                 "mcpwm1_task_timer2_period_up_st",
-                &format_args!("{}", self.mcpwm1_task_timer2_period_up_st().bit()),
-            )
-            .field(
-                "mcpwm1_task_tz0_ost_st",
-                &format_args!("{}", self.mcpwm1_task_tz0_ost_st().bit()),
-            )
-            .field(
-                "mcpwm1_task_tz1_ost_st",
-                &format_args!("{}", self.mcpwm1_task_tz1_ost_st().bit()),
-            )
-            .field(
-                "mcpwm1_task_tz2_ost_st",
-                &format_args!("{}", self.mcpwm1_task_tz2_ost_st().bit()),
-            )
-            .field(
-                "mcpwm1_task_clr0_ost_st",
-                &format_args!("{}", self.mcpwm1_task_clr0_ost_st().bit()),
-            )
-            .field(
-                "mcpwm1_task_clr1_ost_st",
-                &format_args!("{}", self.mcpwm1_task_clr1_ost_st().bit()),
-            )
-            .field(
-                "mcpwm1_task_clr2_ost_st",
-                &format_args!("{}", self.mcpwm1_task_clr2_ost_st().bit()),
-            )
-            .field(
-                "mcpwm1_task_cap0_st",
-                &format_args!("{}", self.mcpwm1_task_cap0_st().bit()),
-            )
-            .field(
-                "mcpwm1_task_cap1_st",
-                &format_args!("{}", self.mcpwm1_task_cap1_st().bit()),
-            )
-            .field(
-                "mcpwm1_task_cap2_st",
-                &format_args!("{}", self.mcpwm1_task_cap2_st().bit()),
-            )
-            .field(
-                "adc_task_sample0_st",
-                &format_args!("{}", self.adc_task_sample0_st().bit()),
-            )
-            .field(
-                "adc_task_sample1_st",
-                &format_args!("{}", self.adc_task_sample1_st().bit()),
-            )
-            .field(
-                "adc_task_start0_st",
-                &format_args!("{}", self.adc_task_start0_st().bit()),
-            )
-            .field(
-                "adc_task_stop0_st",
-                &format_args!("{}", self.adc_task_stop0_st().bit()),
-            )
+                &self.mcpwm1_task_timer2_period_up_st(),
+            )
+            .field("mcpwm1_task_tz0_ost_st", &self.mcpwm1_task_tz0_ost_st())
+            .field("mcpwm1_task_tz1_ost_st", &self.mcpwm1_task_tz1_ost_st())
+            .field("mcpwm1_task_tz2_ost_st", &self.mcpwm1_task_tz2_ost_st())
+            .field("mcpwm1_task_clr0_ost_st", &self.mcpwm1_task_clr0_ost_st())
+            .field("mcpwm1_task_clr1_ost_st", &self.mcpwm1_task_clr1_ost_st())
+            .field("mcpwm1_task_clr2_ost_st", &self.mcpwm1_task_clr2_ost_st())
+            .field("mcpwm1_task_cap0_st", &self.mcpwm1_task_cap0_st())
+            .field("mcpwm1_task_cap1_st", &self.mcpwm1_task_cap1_st())
+            .field("mcpwm1_task_cap2_st", &self.mcpwm1_task_cap2_st())
+            .field("adc_task_sample0_st", &self.adc_task_sample0_st())
+            .field("adc_task_sample1_st", &self.adc_task_sample1_st())
+            .field("adc_task_start0_st", &self.adc_task_start0_st())
+            .field("adc_task_stop0_st", &self.adc_task_stop0_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TASK_ST4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Represents MCPWM0_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/task_st5.rs b/esp32p4/src/soc_etm/task_st5.rs
index 2208bc8c68..593a989a8d 100644
--- a/esp32p4/src/soc_etm/task_st5.rs
+++ b/esp32p4/src/soc_etm/task_st5.rs
@@ -296,143 +296,71 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TASK_ST5")
-            .field(
-                "regdma_task_start0_st",
-                &format_args!("{}", self.regdma_task_start0_st().bit()),
-            )
-            .field(
-                "regdma_task_start1_st",
-                &format_args!("{}", self.regdma_task_start1_st().bit()),
-            )
-            .field(
-                "regdma_task_start2_st",
-                &format_args!("{}", self.regdma_task_start2_st().bit()),
-            )
-            .field(
-                "regdma_task_start3_st",
-                &format_args!("{}", self.regdma_task_start3_st().bit()),
-            )
+            .field("regdma_task_start0_st", &self.regdma_task_start0_st())
+            .field("regdma_task_start1_st", &self.regdma_task_start1_st())
+            .field("regdma_task_start2_st", &self.regdma_task_start2_st())
+            .field("regdma_task_start3_st", &self.regdma_task_start3_st())
             .field(
                 "tmpsnsr_task_start_sample_st",
-                &format_args!("{}", self.tmpsnsr_task_start_sample_st().bit()),
+                &self.tmpsnsr_task_start_sample_st(),
             )
             .field(
                 "tmpsnsr_task_stop_sample_st",
-                &format_args!("{}", self.tmpsnsr_task_stop_sample_st().bit()),
-            )
-            .field(
-                "i2s0_task_start_rx_st",
-                &format_args!("{}", self.i2s0_task_start_rx_st().bit()),
-            )
-            .field(
-                "i2s0_task_start_tx_st",
-                &format_args!("{}", self.i2s0_task_start_tx_st().bit()),
-            )
-            .field(
-                "i2s0_task_stop_rx_st",
-                &format_args!("{}", self.i2s0_task_stop_rx_st().bit()),
-            )
-            .field(
-                "i2s0_task_stop_tx_st",
-                &format_args!("{}", self.i2s0_task_stop_tx_st().bit()),
-            )
-            .field(
-                "i2s1_task_start_rx_st",
-                &format_args!("{}", self.i2s1_task_start_rx_st().bit()),
-            )
-            .field(
-                "i2s1_task_start_tx_st",
-                &format_args!("{}", self.i2s1_task_start_tx_st().bit()),
-            )
-            .field(
-                "i2s1_task_stop_rx_st",
-                &format_args!("{}", self.i2s1_task_stop_rx_st().bit()),
-            )
-            .field(
-                "i2s1_task_stop_tx_st",
-                &format_args!("{}", self.i2s1_task_stop_tx_st().bit()),
-            )
-            .field(
-                "i2s2_task_start_rx_st",
-                &format_args!("{}", self.i2s2_task_start_rx_st().bit()),
-            )
-            .field(
-                "i2s2_task_start_tx_st",
-                &format_args!("{}", self.i2s2_task_start_tx_st().bit()),
-            )
-            .field(
-                "i2s2_task_stop_rx_st",
-                &format_args!("{}", self.i2s2_task_stop_rx_st().bit()),
-            )
-            .field(
-                "i2s2_task_stop_tx_st",
-                &format_args!("{}", self.i2s2_task_stop_tx_st().bit()),
-            )
-            .field(
-                "ulp_task_wakeup_cpu_st",
-                &format_args!("{}", self.ulp_task_wakeup_cpu_st().bit()),
-            )
-            .field(
-                "ulp_task_int_cpu_st",
-                &format_args!("{}", self.ulp_task_int_cpu_st().bit()),
-            )
-            .field(
-                "rtc_task_start_st",
-                &format_args!("{}", self.rtc_task_start_st().bit()),
-            )
-            .field(
-                "rtc_task_stop_st",
-                &format_args!("{}", self.rtc_task_stop_st().bit()),
-            )
-            .field(
-                "rtc_task_clr_st",
-                &format_args!("{}", self.rtc_task_clr_st().bit()),
-            )
-            .field(
-                "rtc_task_triggerflw_st",
-                &format_args!("{}", self.rtc_task_triggerflw_st().bit()),
-            )
+                &self.tmpsnsr_task_stop_sample_st(),
+            )
+            .field("i2s0_task_start_rx_st", &self.i2s0_task_start_rx_st())
+            .field("i2s0_task_start_tx_st", &self.i2s0_task_start_tx_st())
+            .field("i2s0_task_stop_rx_st", &self.i2s0_task_stop_rx_st())
+            .field("i2s0_task_stop_tx_st", &self.i2s0_task_stop_tx_st())
+            .field("i2s1_task_start_rx_st", &self.i2s1_task_start_rx_st())
+            .field("i2s1_task_start_tx_st", &self.i2s1_task_start_tx_st())
+            .field("i2s1_task_stop_rx_st", &self.i2s1_task_stop_rx_st())
+            .field("i2s1_task_stop_tx_st", &self.i2s1_task_stop_tx_st())
+            .field("i2s2_task_start_rx_st", &self.i2s2_task_start_rx_st())
+            .field("i2s2_task_start_tx_st", &self.i2s2_task_start_tx_st())
+            .field("i2s2_task_stop_rx_st", &self.i2s2_task_stop_rx_st())
+            .field("i2s2_task_stop_tx_st", &self.i2s2_task_stop_tx_st())
+            .field("ulp_task_wakeup_cpu_st", &self.ulp_task_wakeup_cpu_st())
+            .field("ulp_task_int_cpu_st", &self.ulp_task_int_cpu_st())
+            .field("rtc_task_start_st", &self.rtc_task_start_st())
+            .field("rtc_task_stop_st", &self.rtc_task_stop_st())
+            .field("rtc_task_clr_st", &self.rtc_task_clr_st())
+            .field("rtc_task_triggerflw_st", &self.rtc_task_triggerflw_st())
             .field(
                 "pdma_ahb_task_in_start_ch0_st",
-                &format_args!("{}", self.pdma_ahb_task_in_start_ch0_st().bit()),
+                &self.pdma_ahb_task_in_start_ch0_st(),
             )
             .field(
                 "pdma_ahb_task_in_start_ch1_st",
-                &format_args!("{}", self.pdma_ahb_task_in_start_ch1_st().bit()),
+                &self.pdma_ahb_task_in_start_ch1_st(),
             )
             .field(
                 "pdma_ahb_task_in_start_ch2_st",
-                &format_args!("{}", self.pdma_ahb_task_in_start_ch2_st().bit()),
+                &self.pdma_ahb_task_in_start_ch2_st(),
             )
             .field(
                 "pdma_ahb_task_out_start_ch0_st",
-                &format_args!("{}", self.pdma_ahb_task_out_start_ch0_st().bit()),
+                &self.pdma_ahb_task_out_start_ch0_st(),
             )
             .field(
                 "pdma_ahb_task_out_start_ch1_st",
-                &format_args!("{}", self.pdma_ahb_task_out_start_ch1_st().bit()),
+                &self.pdma_ahb_task_out_start_ch1_st(),
             )
             .field(
                 "pdma_ahb_task_out_start_ch2_st",
-                &format_args!("{}", self.pdma_ahb_task_out_start_ch2_st().bit()),
+                &self.pdma_ahb_task_out_start_ch2_st(),
             )
             .field(
                 "pdma_axi_task_in_start_ch0_st",
-                &format_args!("{}", self.pdma_axi_task_in_start_ch0_st().bit()),
+                &self.pdma_axi_task_in_start_ch0_st(),
             )
             .field(
                 "pdma_axi_task_in_start_ch1_st",
-                &format_args!("{}", self.pdma_axi_task_in_start_ch1_st().bit()),
+                &self.pdma_axi_task_in_start_ch1_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TASK_ST5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Represents REGDMA_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
     #[inline(always)]
diff --git a/esp32p4/src/soc_etm/task_st6.rs b/esp32p4/src/soc_etm/task_st6.rs
index afd481b5d6..ba80d6ce93 100644
--- a/esp32p4/src/soc_etm/task_st6.rs
+++ b/esp32p4/src/soc_etm/task_st6.rs
@@ -145,73 +145,64 @@ impl core::fmt::Debug for R {
         f.debug_struct("TASK_ST6")
             .field(
                 "pdma_axi_task_in_start_ch2_st",
-                &format_args!("{}", self.pdma_axi_task_in_start_ch2_st().bit()),
+                &self.pdma_axi_task_in_start_ch2_st(),
             )
             .field(
                 "pdma_axi_task_out_start_ch0_st",
-                &format_args!("{}", self.pdma_axi_task_out_start_ch0_st().bit()),
+                &self.pdma_axi_task_out_start_ch0_st(),
             )
             .field(
                 "pdma_axi_task_out_start_ch1_st",
-                &format_args!("{}", self.pdma_axi_task_out_start_ch1_st().bit()),
+                &self.pdma_axi_task_out_start_ch1_st(),
             )
             .field(
                 "pdma_axi_task_out_start_ch2_st",
-                &format_args!("{}", self.pdma_axi_task_out_start_ch2_st().bit()),
-            )
-            .field(
-                "pmu_task_sleep_req_st",
-                &format_args!("{}", self.pmu_task_sleep_req_st().bit()),
+                &self.pdma_axi_task_out_start_ch2_st(),
             )
+            .field("pmu_task_sleep_req_st", &self.pmu_task_sleep_req_st())
             .field(
                 "dma2d_task_in_start_ch0_st",
-                &format_args!("{}", self.dma2d_task_in_start_ch0_st().bit()),
+                &self.dma2d_task_in_start_ch0_st(),
             )
             .field(
                 "dma2d_task_in_start_ch1_st",
-                &format_args!("{}", self.dma2d_task_in_start_ch1_st().bit()),
+                &self.dma2d_task_in_start_ch1_st(),
             )
             .field(
                 "dma2d_task_in_dscr_ready_ch0_st",
-                &format_args!("{}", self.dma2d_task_in_dscr_ready_ch0_st().bit()),
+                &self.dma2d_task_in_dscr_ready_ch0_st(),
             )
             .field(
                 "dma2d_task_in_dscr_ready_ch1_st",
-                &format_args!("{}", self.dma2d_task_in_dscr_ready_ch1_st().bit()),
+                &self.dma2d_task_in_dscr_ready_ch1_st(),
             )
             .field(
                 "dma2d_task_out_start_ch0_st",
-                &format_args!("{}", self.dma2d_task_out_start_ch0_st().bit()),
+                &self.dma2d_task_out_start_ch0_st(),
             )
             .field(
                 "dma2d_task_out_start_ch1_st",
-                &format_args!("{}", self.dma2d_task_out_start_ch1_st().bit()),
+                &self.dma2d_task_out_start_ch1_st(),
             )
             .field(
                 "dma2d_task_out_start_ch2_st",
-                &format_args!("{}", self.dma2d_task_out_start_ch2_st().bit()),
+                &self.dma2d_task_out_start_ch2_st(),
             )
             .field(
                 "dma2d_task_out_dscr_ready_ch0_st",
-                &format_args!("{}", self.dma2d_task_out_dscr_ready_ch0_st().bit()),
+                &self.dma2d_task_out_dscr_ready_ch0_st(),
             )
             .field(
                 "dma2d_task_out_dscr_ready_ch1_st",
-                &format_args!("{}", self.dma2d_task_out_dscr_ready_ch1_st().bit()),
+                &self.dma2d_task_out_dscr_ready_ch1_st(),
             )
             .field(
                 "dma2d_task_out_dscr_ready_ch2_st",
-                &format_args!("{}", self.dma2d_task_out_dscr_ready_ch2_st().bit()),
+                &self.dma2d_task_out_dscr_ready_ch2_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TASK_ST6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Represents PDMA_AXI_task_in_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/axi_err_addr.rs b/esp32p4/src/spi0/axi_err_addr.rs
index 69dd5d61e7..002e1adbe9 100644
--- a/esp32p4/src/spi0/axi_err_addr.rs
+++ b/esp32p4/src/spi0/axi_err_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AXI_ERR_ADDR")
-            .field(
-                "axi_err_addr",
-                &format_args!("{}", self.axi_err_addr().bits()),
-            )
+            .field("axi_err_addr", &self.axi_err_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_ERR_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 AXI request error address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`axi_err_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AXI_ERR_ADDR_SPEC;
 impl crate::RegisterSpec for AXI_ERR_ADDR_SPEC {
diff --git a/esp32p4/src/spi0/axi_err_resp_en.rs b/esp32p4/src/spi0/axi_err_resp_en.rs
index dabef9c503..7a17137a3b 100644
--- a/esp32p4/src/spi0/axi_err_resp_en.rs
+++ b/esp32p4/src/spi0/axi_err_resp_en.rs
@@ -116,63 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AXI_ERR_RESP_EN")
-            .field(
-                "aw_resp_en_mmu_vld",
-                &format_args!("{}", self.aw_resp_en_mmu_vld().bit()),
-            )
-            .field(
-                "aw_resp_en_mmu_gid",
-                &format_args!("{}", self.aw_resp_en_mmu_gid().bit()),
-            )
-            .field(
-                "aw_resp_en_axi_size",
-                &format_args!("{}", self.aw_resp_en_axi_size().bit()),
-            )
-            .field(
-                "aw_resp_en_axi_flash",
-                &format_args!("{}", self.aw_resp_en_axi_flash().bit()),
-            )
-            .field(
-                "aw_resp_en_mmu_ecc",
-                &format_args!("{}", self.aw_resp_en_mmu_ecc().bit()),
-            )
-            .field(
-                "aw_resp_en_mmu_sens",
-                &format_args!("{}", self.aw_resp_en_mmu_sens().bit()),
-            )
-            .field(
-                "aw_resp_en_axi_wstrb",
-                &format_args!("{}", self.aw_resp_en_axi_wstrb().bit()),
-            )
-            .field(
-                "ar_resp_en_mmu_vld",
-                &format_args!("{}", self.ar_resp_en_mmu_vld().bit()),
-            )
-            .field(
-                "ar_resp_en_mmu_gid",
-                &format_args!("{}", self.ar_resp_en_mmu_gid().bit()),
-            )
-            .field(
-                "ar_resp_en_mmu_ecc",
-                &format_args!("{}", self.ar_resp_en_mmu_ecc().bit()),
-            )
-            .field(
-                "ar_resp_en_mmu_sens",
-                &format_args!("{}", self.ar_resp_en_mmu_sens().bit()),
-            )
-            .field(
-                "ar_resp_en_axi_size",
-                &format_args!("{}", self.ar_resp_en_axi_size().bit()),
-            )
+            .field("aw_resp_en_mmu_vld", &self.aw_resp_en_mmu_vld())
+            .field("aw_resp_en_mmu_gid", &self.aw_resp_en_mmu_gid())
+            .field("aw_resp_en_axi_size", &self.aw_resp_en_axi_size())
+            .field("aw_resp_en_axi_flash", &self.aw_resp_en_axi_flash())
+            .field("aw_resp_en_mmu_ecc", &self.aw_resp_en_mmu_ecc())
+            .field("aw_resp_en_mmu_sens", &self.aw_resp_en_mmu_sens())
+            .field("aw_resp_en_axi_wstrb", &self.aw_resp_en_axi_wstrb())
+            .field("ar_resp_en_mmu_vld", &self.ar_resp_en_mmu_vld())
+            .field("ar_resp_en_mmu_gid", &self.ar_resp_en_mmu_gid())
+            .field("ar_resp_en_mmu_ecc", &self.ar_resp_en_mmu_ecc())
+            .field("ar_resp_en_mmu_sens", &self.ar_resp_en_mmu_sens())
+            .field("ar_resp_en_axi_size", &self.ar_resp_en_axi_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AXI_ERR_RESP_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable AXI response function for mmu valid err in axi write trans."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/cache_fctrl.rs b/esp32p4/src/spi0/cache_fctrl.rs
index 6f902cc161..6fdcbb1ab3 100644
--- a/esp32p4/src/spi0/cache_fctrl.rs
+++ b/esp32p4/src/spi0/cache_fctrl.rs
@@ -107,38 +107,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_FCTRL")
-            .field("axi_req_en", &format_args!("{}", self.axi_req_en().bit()))
-            .field(
-                "cache_usr_addr_4byte",
-                &format_args!("{}", self.cache_usr_addr_4byte().bit()),
-            )
-            .field(
-                "cache_flash_usr_cmd",
-                &format_args!("{}", self.cache_flash_usr_cmd().bit()),
-            )
-            .field("fdin_dual", &format_args!("{}", self.fdin_dual().bit()))
-            .field("fdout_dual", &format_args!("{}", self.fdout_dual().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("fdin_quad", &format_args!("{}", self.fdin_quad().bit()))
-            .field("fdout_quad", &format_args!("{}", self.fdout_quad().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
+            .field("axi_req_en", &self.axi_req_en())
+            .field("cache_usr_addr_4byte", &self.cache_usr_addr_4byte())
+            .field("cache_flash_usr_cmd", &self.cache_flash_usr_cmd())
+            .field("fdin_dual", &self.fdin_dual())
+            .field("fdout_dual", &self.fdout_dual())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("fdin_quad", &self.fdin_quad())
+            .field("fdout_quad", &self.fdout_quad())
+            .field("faddr_quad", &self.faddr_quad())
             .field(
                 "spi_same_aw_ar_addr_chk_en",
-                &format_args!("{}", self.spi_same_aw_ar_addr_chk_en().bit()),
-            )
-            .field(
-                "spi_close_axi_inf_en",
-                &format_args!("{}", self.spi_close_axi_inf_en().bit()),
+                &self.spi_same_aw_ar_addr_chk_en(),
             )
+            .field("spi_close_axi_inf_en", &self.spi_close_axi_inf_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_FCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - For SPI0, AXI master access enable, 1: enable, 0:disable."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/cache_sctrl.rs b/esp32p4/src/spi0/cache_sctrl.rs
index 5279243a02..1ec91378cf 100644
--- a/esp32p4/src/spi0/cache_sctrl.rs
+++ b/esp32p4/src/spi0/cache_sctrl.rs
@@ -107,56 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_SCTRL")
-            .field(
-                "cache_usr_saddr_4byte",
-                &format_args!("{}", self.cache_usr_saddr_4byte().bit()),
-            )
-            .field(
-                "usr_sram_dio",
-                &format_args!("{}", self.usr_sram_dio().bit()),
-            )
-            .field(
-                "usr_sram_qio",
-                &format_args!("{}", self.usr_sram_qio().bit()),
-            )
-            .field(
-                "usr_wr_sram_dummy",
-                &format_args!("{}", self.usr_wr_sram_dummy().bit()),
-            )
-            .field(
-                "usr_rd_sram_dummy",
-                &format_args!("{}", self.usr_rd_sram_dummy().bit()),
-            )
-            .field(
-                "cache_sram_usr_rcmd",
-                &format_args!("{}", self.cache_sram_usr_rcmd().bit()),
-            )
-            .field(
-                "sram_rdummy_cyclelen",
-                &format_args!("{}", self.sram_rdummy_cyclelen().bits()),
-            )
-            .field(
-                "sram_addr_bitlen",
-                &format_args!("{}", self.sram_addr_bitlen().bits()),
-            )
-            .field(
-                "cache_sram_usr_wcmd",
-                &format_args!("{}", self.cache_sram_usr_wcmd().bit()),
-            )
-            .field("sram_oct", &format_args!("{}", self.sram_oct().bit()))
-            .field(
-                "sram_wdummy_cyclelen",
-                &format_args!("{}", self.sram_wdummy_cyclelen().bits()),
-            )
+            .field("cache_usr_saddr_4byte", &self.cache_usr_saddr_4byte())
+            .field("usr_sram_dio", &self.usr_sram_dio())
+            .field("usr_sram_qio", &self.usr_sram_qio())
+            .field("usr_wr_sram_dummy", &self.usr_wr_sram_dummy())
+            .field("usr_rd_sram_dummy", &self.usr_rd_sram_dummy())
+            .field("cache_sram_usr_rcmd", &self.cache_sram_usr_rcmd())
+            .field("sram_rdummy_cyclelen", &self.sram_rdummy_cyclelen())
+            .field("sram_addr_bitlen", &self.sram_addr_bitlen())
+            .field("cache_sram_usr_wcmd", &self.cache_sram_usr_wcmd())
+            .field("sram_oct", &self.sram_oct())
+            .field("sram_wdummy_cyclelen", &self.sram_wdummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_SCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/clock.rs b/esp32p4/src/spi0/clock.rs
index e44e658046..5adc5d874b 100644
--- a/esp32p4/src/spi0/clock.rs
+++ b/esp32p4/src/spi0/clock.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/clock_gate.rs b/esp32p4/src/spi0/clock_gate.rs
index 9e3dcbf652..eede18e876 100644
--- a/esp32p4/src/spi0/clock_gate.rs
+++ b/esp32p4/src/spi0/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("spi_clk_en", &format_args!("{}", self.spi_clk_en().bit()))
+            .field("spi_clk_en", &self.spi_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/cmd.rs b/esp32p4/src/spi0/cmd.rs
index 668e900c12..1b01eda873 100644
--- a/esp32p4/src/spi0/cmd.rs
+++ b/esp32p4/src/spi0/cmd.rs
@@ -27,18 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("mst_st", &format_args!("{}", self.mst_st().bits()))
-            .field("slv_st", &format_args!("{}", self.slv_st().bits()))
-            .field("usr", &format_args!("{}", self.usr().bit()))
+            .field("mst_st", &self.mst_st())
+            .field("slv_st", &self.slv_st())
+            .field("usr", &self.usr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 FSM status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CMD_SPEC;
 impl crate::RegisterSpec for CMD_SPEC {
diff --git a/esp32p4/src/spi0/ctrl.rs b/esp32p4/src/spi0/ctrl.rs
index 35dae1567d..3261c3173a 100644
--- a/esp32p4/src/spi0/ctrl.rs
+++ b/esp32p4/src/spi0/ctrl.rs
@@ -179,46 +179,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field(
-                "wdummy_dqs_always_out",
-                &format_args!("{}", self.wdummy_dqs_always_out().bit()),
-            )
-            .field(
-                "wdummy_always_out",
-                &format_args!("{}", self.wdummy_always_out().bit()),
-            )
-            .field("fdummy_rin", &format_args!("{}", self.fdummy_rin().bit()))
-            .field("fdummy_wout", &format_args!("{}", self.fdummy_wout().bit()))
-            .field("fdout_oct", &format_args!("{}", self.fdout_oct().bit()))
-            .field("fdin_oct", &format_args!("{}", self.fdin_oct().bit()))
-            .field("faddr_oct", &format_args!("{}", self.faddr_oct().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcmd_oct", &format_args!("{}", self.fcmd_oct().bit()))
-            .field("fastrd_mode", &format_args!("{}", self.fastrd_mode().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("wp", &format_args!("{}", self.wp().bit()))
-            .field("fread_dio", &format_args!("{}", self.fread_dio().bit()))
-            .field("fread_qio", &format_args!("{}", self.fread_qio().bit()))
-            .field(
-                "dqs_ie_always_on",
-                &format_args!("{}", self.dqs_ie_always_on().bit()),
-            )
-            .field(
-                "data_ie_always_on",
-                &format_args!("{}", self.data_ie_always_on().bit()),
-            )
+            .field("wdummy_dqs_always_out", &self.wdummy_dqs_always_out())
+            .field("wdummy_always_out", &self.wdummy_always_out())
+            .field("fdummy_rin", &self.fdummy_rin())
+            .field("fdummy_wout", &self.fdummy_wout())
+            .field("fdout_oct", &self.fdout_oct())
+            .field("fdin_oct", &self.fdin_oct())
+            .field("faddr_oct", &self.faddr_oct())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcmd_oct", &self.fcmd_oct())
+            .field("fastrd_mode", &self.fastrd_mode())
+            .field("fread_dual", &self.fread_dual())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("fread_quad", &self.fread_quad())
+            .field("wp", &self.wp())
+            .field("fread_dio", &self.fread_dio())
+            .field("fread_qio", &self.fread_qio())
+            .field("dqs_ie_always_on", &self.dqs_ie_always_on())
+            .field("data_ie_always_on", &self.data_ie_always_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/ctrl1.rs b/esp32p4/src/spi0/ctrl1.rs
index b1e743be76..8fe18db21a 100644
--- a/esp32p4/src/spi0/ctrl1.rs
+++ b/esp32p4/src/spi0/ctrl1.rs
@@ -98,46 +98,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL1")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
+            .field("clk_mode", &self.clk_mode())
             .field(
                 "spi_ar_size0_1_support_en",
-                &format_args!("{}", self.spi_ar_size0_1_support_en().bit()),
+                &self.spi_ar_size0_1_support_en(),
             )
             .field(
                 "spi_aw_size0_1_support_en",
-                &format_args!("{}", self.spi_aw_size0_1_support_en().bit()),
-            )
-            .field(
-                "spi_axi_rdata_back_fast",
-                &format_args!("{}", self.spi_axi_rdata_back_fast().bit()),
-            )
-            .field(
-                "rresp_ecc_err_en",
-                &format_args!("{}", self.rresp_ecc_err_en().bit()),
-            )
-            .field(
-                "ar_splice_en",
-                &format_args!("{}", self.ar_splice_en().bit()),
-            )
-            .field(
-                "aw_splice_en",
-                &format_args!("{}", self.aw_splice_en().bit()),
-            )
-            .field("ram0_en", &format_args!("{}", self.ram0_en().bit()))
-            .field("dual_ram_en", &format_args!("{}", self.dual_ram_en().bit()))
-            .field(
-                "fast_write_en",
-                &format_args!("{}", self.fast_write_en().bit()),
+                &self.spi_aw_size0_1_support_en(),
             )
+            .field("spi_axi_rdata_back_fast", &self.spi_axi_rdata_back_fast())
+            .field("rresp_ecc_err_en", &self.rresp_ecc_err_en())
+            .field("ar_splice_en", &self.ar_splice_en())
+            .field("aw_splice_en", &self.aw_splice_en())
+            .field("ram0_en", &self.ram0_en())
+            .field("dual_ram_en", &self.dual_ram_en())
+            .field("fast_write_en", &self.fast_write_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/ctrl2.rs b/esp32p4/src/spi0/ctrl2.rs
index 05beae2314..42eca6b7d1 100644
--- a/esp32p4/src/spi0/ctrl2.rs
+++ b/esp32p4/src/spi0/ctrl2.rs
@@ -73,43 +73,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field(
-                "cs_setup_time",
-                &format_args!("{}", self.cs_setup_time().bits()),
-            )
-            .field(
-                "cs_hold_time",
-                &format_args!("{}", self.cs_hold_time().bits()),
-            )
-            .field(
-                "ecc_cs_hold_time",
-                &format_args!("{}", self.ecc_cs_hold_time().bits()),
-            )
-            .field(
-                "ecc_skip_page_corner",
-                &format_args!("{}", self.ecc_skip_page_corner().bit()),
-            )
-            .field(
-                "ecc_16to18_byte_en",
-                &format_args!("{}", self.ecc_16to18_byte_en().bit()),
-            )
-            .field(
-                "split_trans_en",
-                &format_args!("{}", self.split_trans_en().bit()),
-            )
-            .field(
-                "cs_hold_delay",
-                &format_args!("{}", self.cs_hold_delay().bits()),
-            )
+            .field("cs_setup_time", &self.cs_setup_time())
+            .field("cs_hold_time", &self.cs_hold_time())
+            .field("ecc_cs_hold_time", &self.ecc_cs_hold_time())
+            .field("ecc_skip_page_corner", &self.ecc_skip_page_corner())
+            .field("ecc_16to18_byte_en", &self.ecc_16to18_byte_en())
+            .field("split_trans_en", &self.split_trans_en())
+            .field("cs_hold_delay", &self.cs_hold_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/date.rs b/esp32p4/src/spi0/date.rs
index ebddc631be..0293d18da3 100644
--- a/esp32p4/src/spi0/date.rs
+++ b/esp32p4/src/spi0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/spi0/ddr.rs b/esp32p4/src/spi0/ddr.rs
index ac0d8415b2..e5b39518ad 100644
--- a/esp32p4/src/spi0/ddr.rs
+++ b/esp32p4/src/spi0/ddr.rs
@@ -152,79 +152,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DDR")
-            .field(
-                "spi_fmem_ddr_en",
-                &format_args!("{}", self.spi_fmem_ddr_en().bit()),
-            )
-            .field(
-                "spi_fmem_var_dummy",
-                &format_args!("{}", self.spi_fmem_var_dummy().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_rdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_rdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_wdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_wdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_cmd_dis",
-                &format_args!("{}", self.spi_fmem_ddr_cmd_dis().bit()),
-            )
-            .field(
-                "spi_fmem_outminbytelen",
-                &format_args!("{}", self.spi_fmem_outminbytelen().bits()),
-            )
-            .field(
-                "spi_fmem_tx_ddr_msk_en",
-                &format_args!("{}", self.spi_fmem_tx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_fmem_rx_ddr_msk_en",
-                &format_args!("{}", self.spi_fmem_rx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_fmem_usr_ddr_dqs_thd",
-                &format_args!("{}", self.spi_fmem_usr_ddr_dqs_thd().bits()),
-            )
-            .field(
-                "spi_fmem_ddr_dqs_loop",
-                &format_args!("{}", self.spi_fmem_ddr_dqs_loop().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_en",
-                &format_args!("{}", self.spi_fmem_clk_diff_en().bit()),
-            )
-            .field(
-                "spi_fmem_dqs_ca_in",
-                &format_args!("{}", self.spi_fmem_dqs_ca_in().bit()),
-            )
+            .field("spi_fmem_ddr_en", &self.spi_fmem_ddr_en())
+            .field("spi_fmem_var_dummy", &self.spi_fmem_var_dummy())
+            .field("spi_fmem_ddr_rdat_swp", &self.spi_fmem_ddr_rdat_swp())
+            .field("spi_fmem_ddr_wdat_swp", &self.spi_fmem_ddr_wdat_swp())
+            .field("spi_fmem_ddr_cmd_dis", &self.spi_fmem_ddr_cmd_dis())
+            .field("spi_fmem_outminbytelen", &self.spi_fmem_outminbytelen())
+            .field("spi_fmem_tx_ddr_msk_en", &self.spi_fmem_tx_ddr_msk_en())
+            .field("spi_fmem_rx_ddr_msk_en", &self.spi_fmem_rx_ddr_msk_en())
+            .field("spi_fmem_usr_ddr_dqs_thd", &self.spi_fmem_usr_ddr_dqs_thd())
+            .field("spi_fmem_ddr_dqs_loop", &self.spi_fmem_ddr_dqs_loop())
+            .field("spi_fmem_clk_diff_en", &self.spi_fmem_clk_diff_en())
+            .field("spi_fmem_dqs_ca_in", &self.spi_fmem_dqs_ca_in())
             .field(
                 "spi_fmem_hyperbus_dummy_2x",
-                &format_args!("{}", self.spi_fmem_hyperbus_dummy_2x().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_inv",
-                &format_args!("{}", self.spi_fmem_clk_diff_inv().bit()),
-            )
-            .field(
-                "spi_fmem_octa_ram_addr",
-                &format_args!("{}", self.spi_fmem_octa_ram_addr().bit()),
-            )
-            .field(
-                "spi_fmem_hyperbus_ca",
-                &format_args!("{}", self.spi_fmem_hyperbus_ca().bit()),
+                &self.spi_fmem_hyperbus_dummy_2x(),
             )
+            .field("spi_fmem_clk_diff_inv", &self.spi_fmem_clk_diff_inv())
+            .field("spi_fmem_octa_ram_addr", &self.spi_fmem_octa_ram_addr())
+            .field("spi_fmem_hyperbus_ca", &self.spi_fmem_hyperbus_ca())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: in DDR mode, 0 in SDR mode"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/din_mode.rs b/esp32p4/src/spi0/din_mode.rs
index 90d7b5a3fd..dfc428573f 100644
--- a/esp32p4/src/spi0/din_mode.rs
+++ b/esp32p4/src/spi0/din_mode.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_MODE")
-            .field("din0_mode", &format_args!("{}", self.din0_mode().bits()))
-            .field("din1_mode", &format_args!("{}", self.din1_mode().bits()))
-            .field("din2_mode", &format_args!("{}", self.din2_mode().bits()))
-            .field("din3_mode", &format_args!("{}", self.din3_mode().bits()))
-            .field("din4_mode", &format_args!("{}", self.din4_mode().bits()))
-            .field("din5_mode", &format_args!("{}", self.din5_mode().bits()))
-            .field("din6_mode", &format_args!("{}", self.din6_mode().bits()))
-            .field("din7_mode", &format_args!("{}", self.din7_mode().bits()))
-            .field("dins_mode", &format_args!("{}", self.dins_mode().bits()))
+            .field("din0_mode", &self.din0_mode())
+            .field("din1_mode", &self.din1_mode())
+            .field("din2_mode", &self.din2_mode())
+            .field("din3_mode", &self.din3_mode())
+            .field("din4_mode", &self.din4_mode())
+            .field("din5_mode", &self.din5_mode())
+            .field("din6_mode", &self.din6_mode())
+            .field("din7_mode", &self.din7_mode())
+            .field("dins_mode", &self.dins_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/din_num.rs b/esp32p4/src/spi0/din_num.rs
index 2ee1addcc8..e349d63599 100644
--- a/esp32p4/src/spi0/din_num.rs
+++ b/esp32p4/src/spi0/din_num.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_NUM")
-            .field("din0_num", &format_args!("{}", self.din0_num().bits()))
-            .field("din1_num", &format_args!("{}", self.din1_num().bits()))
-            .field("din2_num", &format_args!("{}", self.din2_num().bits()))
-            .field("din3_num", &format_args!("{}", self.din3_num().bits()))
-            .field("din4_num", &format_args!("{}", self.din4_num().bits()))
-            .field("din5_num", &format_args!("{}", self.din5_num().bits()))
-            .field("din6_num", &format_args!("{}", self.din6_num().bits()))
-            .field("din7_num", &format_args!("{}", self.din7_num().bits()))
-            .field("dins_num", &format_args!("{}", self.dins_num().bits()))
+            .field("din0_num", &self.din0_num())
+            .field("din1_num", &self.din1_num())
+            .field("din2_num", &self.din2_num())
+            .field("din3_num", &self.din3_num())
+            .field("din4_num", &self.din4_num())
+            .field("din5_num", &self.din5_num())
+            .field("din6_num", &self.din6_num())
+            .field("din7_num", &self.din7_num())
+            .field("dins_num", &self.dins_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/dout_mode.rs b/esp32p4/src/spi0/dout_mode.rs
index fa50bdd69a..e426b2bf23 100644
--- a/esp32p4/src/spi0/dout_mode.rs
+++ b/esp32p4/src/spi0/dout_mode.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOUT_MODE")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bit()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bit()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bit()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bit()))
-            .field("dout4_mode", &format_args!("{}", self.dout4_mode().bit()))
-            .field("dout5_mode", &format_args!("{}", self.dout5_mode().bit()))
-            .field("dout6_mode", &format_args!("{}", self.dout6_mode().bit()))
-            .field("dout7_mode", &format_args!("{}", self.dout7_mode().bit()))
-            .field("douts_mode", &format_args!("{}", self.douts_mode().bit()))
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
+            .field("dout4_mode", &self.dout4_mode())
+            .field("dout5_mode", &self.dout5_mode())
+            .field("dout6_mode", &self.dout6_mode())
+            .field("dout7_mode", &self.dout7_mode())
+            .field("douts_mode", &self.douts_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/dpa_ctrl.rs b/esp32p4/src/spi0/dpa_ctrl.rs
index 36adf8a2a3..aea7e042b7 100644
--- a/esp32p4/src/spi0/dpa_ctrl.rs
+++ b/esp32p4/src/spi0/dpa_ctrl.rs
@@ -35,27 +35,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DPA_CTRL")
-            .field(
-                "spi_crypt_security_level",
-                &format_args!("{}", self.spi_crypt_security_level().bits()),
-            )
-            .field(
-                "spi_crypt_calc_d_dpa_en",
-                &format_args!("{}", self.spi_crypt_calc_d_dpa_en().bit()),
-            )
+            .field("spi_crypt_security_level", &self.spi_crypt_security_level())
+            .field("spi_crypt_calc_d_dpa_en", &self.spi_crypt_calc_d_dpa_en())
             .field(
                 "spi_crypt_dpa_select_register",
-                &format_args!("{}", self.spi_crypt_dpa_select_register().bit()),
+                &self.spi_crypt_dpa_select_register(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DPA_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/ecc_ctrl.rs b/esp32p4/src/spi0/ecc_ctrl.rs
index 2330166bc6..db9c2499a2 100644
--- a/esp32p4/src/spi0/ecc_ctrl.rs
+++ b/esp32p4/src/spi0/ecc_ctrl.rs
@@ -76,47 +76,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_CTRL")
-            .field(
-                "ecc_err_cnt",
-                &format_args!("{}", self.ecc_err_cnt().bits()),
-            )
-            .field(
-                "spi_fmem_ecc_err_int_num",
-                &format_args!("{}", self.spi_fmem_ecc_err_int_num().bits()),
-            )
-            .field(
-                "spi_fmem_ecc_err_int_en",
-                &format_args!("{}", self.spi_fmem_ecc_err_int_en().bit()),
-            )
-            .field(
-                "spi_fmem_page_size",
-                &format_args!("{}", self.spi_fmem_page_size().bits()),
-            )
-            .field(
-                "spi_fmem_ecc_addr_en",
-                &format_args!("{}", self.spi_fmem_ecc_addr_en().bit()),
-            )
-            .field(
-                "usr_ecc_addr_en",
-                &format_args!("{}", self.usr_ecc_addr_en().bit()),
-            )
+            .field("ecc_err_cnt", &self.ecc_err_cnt())
+            .field("spi_fmem_ecc_err_int_num", &self.spi_fmem_ecc_err_int_num())
+            .field("spi_fmem_ecc_err_int_en", &self.spi_fmem_ecc_err_int_en())
+            .field("spi_fmem_page_size", &self.spi_fmem_page_size())
+            .field("spi_fmem_ecc_addr_en", &self.spi_fmem_ecc_addr_en())
+            .field("usr_ecc_addr_en", &self.usr_ecc_addr_en())
             .field(
                 "ecc_continue_record_err_en",
-                &format_args!("{}", self.ecc_continue_record_err_en().bit()),
-            )
-            .field(
-                "ecc_err_bits",
-                &format_args!("{}", self.ecc_err_bits().bits()),
+                &self.ecc_continue_record_err_en(),
             )
+            .field("ecc_err_bits", &self.ecc_err_bits())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 11:16 - Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/ecc_err_addr.rs b/esp32p4/src/spi0/ecc_err_addr.rs
index 2098a43078..6b482fda3b 100644
--- a/esp32p4/src/spi0/ecc_err_addr.rs
+++ b/esp32p4/src/spi0/ecc_err_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_ERR_ADDR")
-            .field(
-                "ecc_err_addr",
-                &format_args!("{}", self.ecc_err_addr().bits()),
-            )
+            .field("ecc_err_addr", &self.ecc_err_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_ERR_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI ECC error address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecc_err_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ECC_ERR_ADDR_SPEC;
 impl crate::RegisterSpec for ECC_ERR_ADDR_SPEC {
diff --git a/esp32p4/src/spi0/fsm.rs b/esp32p4/src/spi0/fsm.rs
index 54045ebf4f..ed0f815e8e 100644
--- a/esp32p4/src/spi0/fsm.rs
+++ b/esp32p4/src/spi0/fsm.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM")
-            .field(
-                "lock_delay_time",
-                &format_args!("{}", self.lock_delay_time().bits()),
-            )
+            .field("lock_delay_time", &self.lock_delay_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 7:11 - The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/int_ena.rs b/esp32p4/src/spi0/int_ena.rs
index d99143e64b..2e4a7941bf 100644
--- a/esp32p4/src/spi0/int_ena.rs
+++ b/esp32p4/src/spi0/int_ena.rs
@@ -107,47 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("ecc_err", &format_args!("{}", self.ecc_err().bit()))
-            .field("pms_reject", &format_args!("{}", self.pms_reject().bit()))
-            .field(
-                "axi_raddr_err",
-                &format_args!("{}", self.axi_raddr_err().bit()),
-            )
-            .field(
-                "axi_wr_flash_err",
-                &format_args!("{}", self.axi_wr_flash_err().bit()),
-            )
-            .field(
-                "axi_waddr_err_int__ena",
-                &format_args!("{}", self.axi_waddr_err_int__ena().bit()),
-            )
-            .field(
-                "dqs0_afifo_ovf",
-                &format_args!("{}", self.dqs0_afifo_ovf().bit()),
-            )
-            .field(
-                "dqs1_afifo_ovf",
-                &format_args!("{}", self.dqs1_afifo_ovf().bit()),
-            )
-            .field(
-                "bus_fifo1_udf",
-                &format_args!("{}", self.bus_fifo1_udf().bit()),
-            )
-            .field(
-                "bus_fifo0_udf",
-                &format_args!("{}", self.bus_fifo0_udf().bit()),
-            )
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("ecc_err", &self.ecc_err())
+            .field("pms_reject", &self.pms_reject())
+            .field("axi_raddr_err", &self.axi_raddr_err())
+            .field("axi_wr_flash_err", &self.axi_wr_flash_err())
+            .field("axi_waddr_err_int__ena", &self.axi_waddr_err_int__ena())
+            .field("dqs0_afifo_ovf", &self.dqs0_afifo_ovf())
+            .field("dqs1_afifo_ovf", &self.dqs1_afifo_ovf())
+            .field("bus_fifo1_udf", &self.bus_fifo1_udf())
+            .field("bus_fifo0_udf", &self.bus_fifo0_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - The enable bit for SPI_MEM_SLV_ST_END_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/int_raw.rs b/esp32p4/src/spi0/int_raw.rs
index 6408e67e87..e89efd3740 100644
--- a/esp32p4/src/spi0/int_raw.rs
+++ b/esp32p4/src/spi0/int_raw.rs
@@ -107,47 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("ecc_err", &format_args!("{}", self.ecc_err().bit()))
-            .field("pms_reject", &format_args!("{}", self.pms_reject().bit()))
-            .field(
-                "axi_raddr_err",
-                &format_args!("{}", self.axi_raddr_err().bit()),
-            )
-            .field(
-                "axi_wr_flash_err",
-                &format_args!("{}", self.axi_wr_flash_err().bit()),
-            )
-            .field(
-                "axi_waddr_err",
-                &format_args!("{}", self.axi_waddr_err().bit()),
-            )
-            .field(
-                "dqs0_afifo_ovf",
-                &format_args!("{}", self.dqs0_afifo_ovf().bit()),
-            )
-            .field(
-                "dqs1_afifo_ovf",
-                &format_args!("{}", self.dqs1_afifo_ovf().bit()),
-            )
-            .field(
-                "bus_fifo1_udf",
-                &format_args!("{}", self.bus_fifo1_udf().bit()),
-            )
-            .field(
-                "bus_fifo0_udf",
-                &format_args!("{}", self.bus_fifo0_udf().bit()),
-            )
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("ecc_err", &self.ecc_err())
+            .field("pms_reject", &self.pms_reject())
+            .field("axi_raddr_err", &self.axi_raddr_err())
+            .field("axi_wr_flash_err", &self.axi_wr_flash_err())
+            .field("axi_waddr_err", &self.axi_waddr_err())
+            .field("dqs0_afifo_ovf", &self.dqs0_afifo_ovf())
+            .field("dqs1_afifo_ovf", &self.dqs1_afifo_ovf())
+            .field("bus_fifo1_udf", &self.bus_fifo1_udf())
+            .field("bus_fifo0_udf", &self.bus_fifo0_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/int_st.rs b/esp32p4/src/spi0/int_st.rs
index daed204941..d1cc046bc9 100644
--- a/esp32p4/src/spi0/int_st.rs
+++ b/esp32p4/src/spi0/int_st.rs
@@ -83,47 +83,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("ecc_err", &format_args!("{}", self.ecc_err().bit()))
-            .field("pms_reject", &format_args!("{}", self.pms_reject().bit()))
-            .field(
-                "axi_raddr_err",
-                &format_args!("{}", self.axi_raddr_err().bit()),
-            )
-            .field(
-                "axi_wr_flash_err",
-                &format_args!("{}", self.axi_wr_flash_err().bit()),
-            )
-            .field(
-                "axi_waddr_err",
-                &format_args!("{}", self.axi_waddr_err().bit()),
-            )
-            .field(
-                "dqs0_afifo_ovf",
-                &format_args!("{}", self.dqs0_afifo_ovf().bit()),
-            )
-            .field(
-                "dqs1_afifo_ovf",
-                &format_args!("{}", self.dqs1_afifo_ovf().bit()),
-            )
-            .field(
-                "bus_fifo1_udf",
-                &format_args!("{}", self.bus_fifo1_udf().bit()),
-            )
-            .field(
-                "bus_fifo0_udf",
-                &format_args!("{}", self.bus_fifo0_udf().bit()),
-            )
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("ecc_err", &self.ecc_err())
+            .field("pms_reject", &self.pms_reject())
+            .field("axi_raddr_err", &self.axi_raddr_err())
+            .field("axi_wr_flash_err", &self.axi_wr_flash_err())
+            .field("axi_waddr_err", &self.axi_waddr_err())
+            .field("dqs0_afifo_ovf", &self.dqs0_afifo_ovf())
+            .field("dqs1_afifo_ovf", &self.dqs1_afifo_ovf())
+            .field("bus_fifo1_udf", &self.bus_fifo1_udf())
+            .field("bus_fifo0_udf", &self.bus_fifo0_udf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/spi0/misc.rs b/esp32p4/src/spi0/misc.rs
index e462432ead..36bfd33b48 100644
--- a/esp32p4/src/spi0/misc.rs
+++ b/esp32p4/src/spi0/misc.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("fsub_pin", &format_args!("{}", self.fsub_pin().bit()))
-            .field("ssub_pin", &format_args!("{}", self.ssub_pin().bit()))
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
+            .field("fsub_pin", &self.fsub_pin())
+            .field("ssub_pin", &self.ssub_pin())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - For SPI0, flash is connected to SUBPINs."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/mmu_item_content.rs b/esp32p4/src/spi0/mmu_item_content.rs
index 543a1fc5db..a3898f8b78 100644
--- a/esp32p4/src/spi0/mmu_item_content.rs
+++ b/esp32p4/src/spi0/mmu_item_content.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MMU_ITEM_CONTENT")
-            .field(
-                "spi_mmu_item_content",
-                &format_args!("{}", self.spi_mmu_item_content().bits()),
-            )
+            .field("spi_mmu_item_content", &self.spi_mmu_item_content())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MMU_ITEM_CONTENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - MSPI-MMU item content"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/mmu_item_index.rs b/esp32p4/src/spi0/mmu_item_index.rs
index 9b421e3af3..3cdaed760f 100644
--- a/esp32p4/src/spi0/mmu_item_index.rs
+++ b/esp32p4/src/spi0/mmu_item_index.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MMU_ITEM_INDEX")
-            .field(
-                "spi_mmu_item_index",
-                &format_args!("{}", self.spi_mmu_item_index().bits()),
-            )
+            .field("spi_mmu_item_index", &self.spi_mmu_item_index())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MMU_ITEM_INDEX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - MSPI-MMU item index"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/mmu_power_ctrl.rs b/esp32p4/src/spi0/mmu_power_ctrl.rs
index 82e8a1b177..2701024e0c 100644
--- a/esp32p4/src/spi0/mmu_power_ctrl.rs
+++ b/esp32p4/src/spi0/mmu_power_ctrl.rs
@@ -60,30 +60,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MMU_POWER_CTRL")
-            .field(
-                "spi_mmu_mem_force_on",
-                &format_args!("{}", self.spi_mmu_mem_force_on().bit()),
-            )
-            .field(
-                "spi_mmu_mem_force_pd",
-                &format_args!("{}", self.spi_mmu_mem_force_pd().bit()),
-            )
-            .field(
-                "spi_mmu_mem_force_pu",
-                &format_args!("{}", self.spi_mmu_mem_force_pu().bit()),
-            )
-            .field("aux_ctrl", &format_args!("{}", self.aux_ctrl().bits()))
-            .field("rdn_ena", &format_args!("{}", self.rdn_ena().bit()))
-            .field("rdn_result", &format_args!("{}", self.rdn_result().bit()))
+            .field("spi_mmu_mem_force_on", &self.spi_mmu_mem_force_on())
+            .field("spi_mmu_mem_force_pd", &self.spi_mmu_mem_force_pd())
+            .field("spi_mmu_mem_force_pu", &self.spi_mmu_mem_force_pu())
+            .field("aux_ctrl", &self.aux_ctrl())
+            .field("rdn_ena", &self.rdn_ena())
+            .field("rdn_result", &self.rdn_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MMU_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable mmu-memory clock force on"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/pms_reject.rs b/esp32p4/src/spi0/pms_reject.rs
index a00856bfc9..26e4e8ee37 100644
--- a/esp32p4/src/spi0/pms_reject.rs
+++ b/esp32p4/src/spi0/pms_reject.rs
@@ -52,27 +52,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PMS_REJECT")
-            .field(
-                "reject_addr",
-                &format_args!("{}", self.reject_addr().bits()),
-            )
-            .field("pm_en", &format_args!("{}", self.pm_en().bit()))
-            .field("pms_ld", &format_args!("{}", self.pms_ld().bit()))
-            .field("pms_st", &format_args!("{}", self.pms_st().bit()))
-            .field(
-                "pms_multi_hit",
-                &format_args!("{}", self.pms_multi_hit().bit()),
-            )
-            .field("pms_ivd", &format_args!("{}", self.pms_ivd().bit()))
+            .field("reject_addr", &self.reject_addr())
+            .field("pm_en", &self.pm_en())
+            .field("pms_ld", &self.pms_ld())
+            .field("pms_st", &self.pms_st())
+            .field("pms_multi_hit", &self.pms_multi_hit())
+            .field("pms_ivd", &self.pms_ivd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PMS_REJECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - Set this bit to enable SPI0/1 transfer permission control function."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/rd_status.rs b/esp32p4/src/spi0/rd_status.rs
index f0916ef916..ce4af380ee 100644
--- a/esp32p4/src/spi0/rd_status.rs
+++ b/esp32p4/src/spi0/rd_status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_STATUS")
-            .field("wb_mode", &format_args!("{}", self.wb_mode().bits()))
+            .field("wb_mode", &self.wb_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:23 - Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/registerrnd_eco_high.rs b/esp32p4/src/spi0/registerrnd_eco_high.rs
index c9c6e1a0e2..1192aa5a95 100644
--- a/esp32p4/src/spi0/registerrnd_eco_high.rs
+++ b/esp32p4/src/spi0/registerrnd_eco_high.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGISTERRND_ECO_HIGH")
-            .field(
-                "registerrnd_eco_high",
-                &format_args!("{}", self.registerrnd_eco_high().bits()),
-            )
+            .field("registerrnd_eco_high", &self.registerrnd_eco_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGISTERRND_ECO_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - ECO high register"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/registerrnd_eco_low.rs b/esp32p4/src/spi0/registerrnd_eco_low.rs
index 68eb0b713a..fa221d7a63 100644
--- a/esp32p4/src/spi0/registerrnd_eco_low.rs
+++ b/esp32p4/src/spi0/registerrnd_eco_low.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGISTERRND_ECO_LOW")
-            .field(
-                "registerrnd_eco_low",
-                &format_args!("{}", self.registerrnd_eco_low().bits()),
-            )
+            .field("registerrnd_eco_low", &self.registerrnd_eco_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGISTERRND_ECO_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - ECO low register"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_fmem_pms_addr.rs b/esp32p4/src/spi0/spi_fmem_pms_addr.rs
index 48de907489..a4b805d51f 100644
--- a/esp32p4/src/spi0/spi_fmem_pms_addr.rs
+++ b/esp32p4/src/spi0/spi_fmem_pms_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_FMEM_PMS_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_FMEM_PMS_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:26 - SPI1 flash PMS section %s start address value"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_fmem_pms_attr.rs b/esp32p4/src/spi0/spi_fmem_pms_attr.rs
index c34044e1e9..5507540266 100644
--- a/esp32p4/src/spi0/spi_fmem_pms_attr.rs
+++ b/esp32p4/src/spi0/spi_fmem_pms_attr.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_FMEM_PMS_ATTR")
-            .field(
-                "spi_fmem_pms_rd_attr",
-                &format_args!("{}", self.spi_fmem_pms_rd_attr().bit()),
-            )
-            .field(
-                "spi_fmem_pms_wr_attr",
-                &format_args!("{}", self.spi_fmem_pms_wr_attr().bit()),
-            )
-            .field(
-                "spi_fmem_pms_ecc",
-                &format_args!("{}", self.spi_fmem_pms_ecc().bit()),
-            )
+            .field("spi_fmem_pms_rd_attr", &self.spi_fmem_pms_rd_attr())
+            .field("spi_fmem_pms_wr_attr", &self.spi_fmem_pms_wr_attr())
+            .field("spi_fmem_pms_ecc", &self.spi_fmem_pms_ecc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_FMEM_PMS_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: SPI1 flash PMS section %s read accessible. 0: Not allowed."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_fmem_pms_size.rs b/esp32p4/src/spi0/spi_fmem_pms_size.rs
index 29ff993585..805d876c77 100644
--- a/esp32p4/src/spi0/spi_fmem_pms_size.rs
+++ b/esp32p4/src/spi0/spi_fmem_pms_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_FMEM_PMS_SIZE")
-            .field(
-                "spi_fmem_pms_size",
-                &format_args!("{}", self.spi_fmem_pms_size().bits()),
-            )
+            .field("spi_fmem_pms_size", &self.spi_fmem_pms_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_FMEM_PMS_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - SPI1 flash PMS section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE)"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_smem_ac.rs b/esp32p4/src/spi0/spi_smem_ac.rs
index 2e8106c961..6589fe4de7 100644
--- a/esp32p4/src/spi0/spi_smem_ac.rs
+++ b/esp32p4/src/spi0/spi_smem_ac.rs
@@ -89,51 +89,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_AC")
-            .field(
-                "spi_smem_cs_setup",
-                &format_args!("{}", self.spi_smem_cs_setup().bit()),
-            )
-            .field(
-                "spi_smem_cs_hold",
-                &format_args!("{}", self.spi_smem_cs_hold().bit()),
-            )
-            .field(
-                "spi_smem_cs_setup_time",
-                &format_args!("{}", self.spi_smem_cs_setup_time().bits()),
-            )
-            .field(
-                "spi_smem_cs_hold_time",
-                &format_args!("{}", self.spi_smem_cs_hold_time().bits()),
-            )
+            .field("spi_smem_cs_setup", &self.spi_smem_cs_setup())
+            .field("spi_smem_cs_hold", &self.spi_smem_cs_hold())
+            .field("spi_smem_cs_setup_time", &self.spi_smem_cs_setup_time())
+            .field("spi_smem_cs_hold_time", &self.spi_smem_cs_hold_time())
             .field(
                 "spi_smem_ecc_cs_hold_time",
-                &format_args!("{}", self.spi_smem_ecc_cs_hold_time().bits()),
+                &self.spi_smem_ecc_cs_hold_time(),
             )
             .field(
                 "spi_smem_ecc_skip_page_corner",
-                &format_args!("{}", self.spi_smem_ecc_skip_page_corner().bit()),
+                &self.spi_smem_ecc_skip_page_corner(),
             )
             .field(
                 "spi_smem_ecc_16to18_byte_en",
-                &format_args!("{}", self.spi_smem_ecc_16to18_byte_en().bit()),
-            )
-            .field(
-                "spi_smem_cs_hold_delay",
-                &format_args!("{}", self.spi_smem_cs_hold_delay().bits()),
-            )
-            .field(
-                "spi_smem_split_trans_en",
-                &format_args!("{}", self.spi_smem_split_trans_en().bit()),
+                &self.spi_smem_ecc_16to18_byte_en(),
             )
+            .field("spi_smem_cs_hold_delay", &self.spi_smem_cs_hold_delay())
+            .field("spi_smem_split_trans_en", &self.spi_smem_split_trans_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_AC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_smem_axi_addr_ctrl.rs b/esp32p4/src/spi0/spi_smem_axi_addr_ctrl.rs
index 56533f8285..dcffcb19bb 100644
--- a/esp32p4/src/spi0/spi_smem_axi_addr_ctrl.rs
+++ b/esp32p4/src/spi0/spi_smem_axi_addr_ctrl.rs
@@ -48,39 +48,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_AXI_ADDR_CTRL")
-            .field(
-                "all_fifo_empty",
-                &format_args!("{}", self.all_fifo_empty().bit()),
-            )
-            .field(
-                "spi_rdata_afifo_rempty",
-                &format_args!("{}", self.spi_rdata_afifo_rempty().bit()),
-            )
-            .field(
-                "spi_raddr_afifo_rempty",
-                &format_args!("{}", self.spi_raddr_afifo_rempty().bit()),
-            )
-            .field(
-                "spi_wdata_afifo_rempty",
-                &format_args!("{}", self.spi_wdata_afifo_rempty().bit()),
-            )
-            .field(
-                "spi_wblen_afifo_rempty",
-                &format_args!("{}", self.spi_wblen_afifo_rempty().bit()),
-            )
+            .field("all_fifo_empty", &self.all_fifo_empty())
+            .field("spi_rdata_afifo_rempty", &self.spi_rdata_afifo_rempty())
+            .field("spi_raddr_afifo_rempty", &self.spi_raddr_afifo_rempty())
+            .field("spi_wdata_afifo_rempty", &self.spi_wdata_afifo_rempty())
+            .field("spi_wblen_afifo_rempty", &self.spi_wblen_afifo_rempty())
             .field(
                 "spi_all_axi_trans_afifo_empty",
-                &format_args!("{}", self.spi_all_axi_trans_afifo_empty().bit()),
+                &self.spi_all_axi_trans_afifo_empty(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_AXI_ADDR_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI0 AXI address control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_smem_axi_addr_ctrl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_SMEM_AXI_ADDR_CTRL_SPEC;
 impl crate::RegisterSpec for SPI_SMEM_AXI_ADDR_CTRL_SPEC {
diff --git a/esp32p4/src/spi0/spi_smem_ddr.rs b/esp32p4/src/spi0/spi_smem_ddr.rs
index 5c95c366c1..e2565bf246 100644
--- a/esp32p4/src/spi0/spi_smem_ddr.rs
+++ b/esp32p4/src/spi0/spi_smem_ddr.rs
@@ -152,64 +152,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DDR")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field(
-                "spi_smem_var_dummy",
-                &format_args!("{}", self.spi_smem_var_dummy().bit()),
-            )
-            .field("rdat_swp", &format_args!("{}", self.rdat_swp().bit()))
-            .field("wdat_swp", &format_args!("{}", self.wdat_swp().bit()))
-            .field("cmd_dis", &format_args!("{}", self.cmd_dis().bit()))
-            .field(
-                "spi_smem_outminbytelen",
-                &format_args!("{}", self.spi_smem_outminbytelen().bits()),
-            )
-            .field(
-                "spi_smem_tx_ddr_msk_en",
-                &format_args!("{}", self.spi_smem_tx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_smem_rx_ddr_msk_en",
-                &format_args!("{}", self.spi_smem_rx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_smem_usr_ddr_dqs_thd",
-                &format_args!("{}", self.spi_smem_usr_ddr_dqs_thd().bits()),
-            )
-            .field("dqs_loop", &format_args!("{}", self.dqs_loop().bit()))
-            .field(
-                "spi_smem_clk_diff_en",
-                &format_args!("{}", self.spi_smem_clk_diff_en().bit()),
-            )
-            .field(
-                "spi_smem_dqs_ca_in",
-                &format_args!("{}", self.spi_smem_dqs_ca_in().bit()),
-            )
+            .field("en", &self.en())
+            .field("spi_smem_var_dummy", &self.spi_smem_var_dummy())
+            .field("rdat_swp", &self.rdat_swp())
+            .field("wdat_swp", &self.wdat_swp())
+            .field("cmd_dis", &self.cmd_dis())
+            .field("spi_smem_outminbytelen", &self.spi_smem_outminbytelen())
+            .field("spi_smem_tx_ddr_msk_en", &self.spi_smem_tx_ddr_msk_en())
+            .field("spi_smem_rx_ddr_msk_en", &self.spi_smem_rx_ddr_msk_en())
+            .field("spi_smem_usr_ddr_dqs_thd", &self.spi_smem_usr_ddr_dqs_thd())
+            .field("dqs_loop", &self.dqs_loop())
+            .field("spi_smem_clk_diff_en", &self.spi_smem_clk_diff_en())
+            .field("spi_smem_dqs_ca_in", &self.spi_smem_dqs_ca_in())
             .field(
                 "spi_smem_hyperbus_dummy_2x",
-                &format_args!("{}", self.spi_smem_hyperbus_dummy_2x().bit()),
-            )
-            .field(
-                "spi_smem_clk_diff_inv",
-                &format_args!("{}", self.spi_smem_clk_diff_inv().bit()),
-            )
-            .field(
-                "spi_smem_octa_ram_addr",
-                &format_args!("{}", self.spi_smem_octa_ram_addr().bit()),
-            )
-            .field(
-                "spi_smem_hyperbus_ca",
-                &format_args!("{}", self.spi_smem_hyperbus_ca().bit()),
+                &self.spi_smem_hyperbus_dummy_2x(),
             )
+            .field("spi_smem_clk_diff_inv", &self.spi_smem_clk_diff_inv())
+            .field("spi_smem_octa_ram_addr", &self.spi_smem_octa_ram_addr())
+            .field("spi_smem_hyperbus_ca", &self.spi_smem_hyperbus_ca())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: in DDR mode, 0 in SDR mode"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_smem_din_hex_mode.rs b/esp32p4/src/spi0/spi_smem_din_hex_mode.rs
index 355eb91391..3856f3bbe6 100644
--- a/esp32p4/src/spi0/spi_smem_din_hex_mode.rs
+++ b/esp32p4/src/spi0/spi_smem_din_hex_mode.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DIN_HEX_MODE")
-            .field(
-                "spi_smem_din08_mode",
-                &format_args!("{}", self.spi_smem_din08_mode().bits()),
-            )
-            .field(
-                "spi_smem_din09_mode",
-                &format_args!("{}", self.spi_smem_din09_mode().bits()),
-            )
-            .field(
-                "spi_smem_din10_mode",
-                &format_args!("{}", self.spi_smem_din10_mode().bits()),
-            )
-            .field(
-                "spi_smem_din11_mode",
-                &format_args!("{}", self.spi_smem_din11_mode().bits()),
-            )
-            .field(
-                "spi_smem_din12_mode",
-                &format_args!("{}", self.spi_smem_din12_mode().bits()),
-            )
-            .field(
-                "spi_smem_din13_mode",
-                &format_args!("{}", self.spi_smem_din13_mode().bits()),
-            )
-            .field(
-                "spi_smem_din14_mode",
-                &format_args!("{}", self.spi_smem_din14_mode().bits()),
-            )
-            .field(
-                "spi_smem_din15_mode",
-                &format_args!("{}", self.spi_smem_din15_mode().bits()),
-            )
-            .field(
-                "spi_smem_dins_hex_mode",
-                &format_args!("{}", self.spi_smem_dins_hex_mode().bits()),
-            )
+            .field("spi_smem_din08_mode", &self.spi_smem_din08_mode())
+            .field("spi_smem_din09_mode", &self.spi_smem_din09_mode())
+            .field("spi_smem_din10_mode", &self.spi_smem_din10_mode())
+            .field("spi_smem_din11_mode", &self.spi_smem_din11_mode())
+            .field("spi_smem_din12_mode", &self.spi_smem_din12_mode())
+            .field("spi_smem_din13_mode", &self.spi_smem_din13_mode())
+            .field("spi_smem_din14_mode", &self.spi_smem_din14_mode())
+            .field("spi_smem_din15_mode", &self.spi_smem_din15_mode())
+            .field("spi_smem_dins_hex_mode", &self.spi_smem_dins_hex_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DIN_HEX_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_smem_din_hex_num.rs b/esp32p4/src/spi0/spi_smem_din_hex_num.rs
index b1d0e5c01b..37e4579e40 100644
--- a/esp32p4/src/spi0/spi_smem_din_hex_num.rs
+++ b/esp32p4/src/spi0/spi_smem_din_hex_num.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DIN_HEX_NUM")
-            .field(
-                "spi_smem_din08_num",
-                &format_args!("{}", self.spi_smem_din08_num().bits()),
-            )
-            .field(
-                "spi_smem_din09_num",
-                &format_args!("{}", self.spi_smem_din09_num().bits()),
-            )
-            .field(
-                "spi_smem_din10_num",
-                &format_args!("{}", self.spi_smem_din10_num().bits()),
-            )
-            .field(
-                "spi_smem_din11_num",
-                &format_args!("{}", self.spi_smem_din11_num().bits()),
-            )
-            .field(
-                "spi_smem_din12_num",
-                &format_args!("{}", self.spi_smem_din12_num().bits()),
-            )
-            .field(
-                "spi_smem_din13_num",
-                &format_args!("{}", self.spi_smem_din13_num().bits()),
-            )
-            .field(
-                "spi_smem_din14_num",
-                &format_args!("{}", self.spi_smem_din14_num().bits()),
-            )
-            .field(
-                "spi_smem_din15_num",
-                &format_args!("{}", self.spi_smem_din15_num().bits()),
-            )
-            .field(
-                "spi_smem_dins_hex_num",
-                &format_args!("{}", self.spi_smem_dins_hex_num().bits()),
-            )
+            .field("spi_smem_din08_num", &self.spi_smem_din08_num())
+            .field("spi_smem_din09_num", &self.spi_smem_din09_num())
+            .field("spi_smem_din10_num", &self.spi_smem_din10_num())
+            .field("spi_smem_din11_num", &self.spi_smem_din11_num())
+            .field("spi_smem_din12_num", &self.spi_smem_din12_num())
+            .field("spi_smem_din13_num", &self.spi_smem_din13_num())
+            .field("spi_smem_din14_num", &self.spi_smem_din14_num())
+            .field("spi_smem_din15_num", &self.spi_smem_din15_num())
+            .field("spi_smem_dins_hex_num", &self.spi_smem_dins_hex_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DIN_HEX_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_smem_din_mode.rs b/esp32p4/src/spi0/spi_smem_din_mode.rs
index c5b1473e3e..58aaf9783f 100644
--- a/esp32p4/src/spi0/spi_smem_din_mode.rs
+++ b/esp32p4/src/spi0/spi_smem_din_mode.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DIN_MODE")
-            .field(
-                "spi_smem_din0_mode",
-                &format_args!("{}", self.spi_smem_din0_mode().bits()),
-            )
-            .field(
-                "spi_smem_din1_mode",
-                &format_args!("{}", self.spi_smem_din1_mode().bits()),
-            )
-            .field(
-                "spi_smem_din2_mode",
-                &format_args!("{}", self.spi_smem_din2_mode().bits()),
-            )
-            .field(
-                "spi_smem_din3_mode",
-                &format_args!("{}", self.spi_smem_din3_mode().bits()),
-            )
-            .field(
-                "spi_smem_din4_mode",
-                &format_args!("{}", self.spi_smem_din4_mode().bits()),
-            )
-            .field(
-                "spi_smem_din5_mode",
-                &format_args!("{}", self.spi_smem_din5_mode().bits()),
-            )
-            .field(
-                "spi_smem_din6_mode",
-                &format_args!("{}", self.spi_smem_din6_mode().bits()),
-            )
-            .field(
-                "spi_smem_din7_mode",
-                &format_args!("{}", self.spi_smem_din7_mode().bits()),
-            )
-            .field(
-                "spi_smem_dins_mode",
-                &format_args!("{}", self.spi_smem_dins_mode().bits()),
-            )
+            .field("spi_smem_din0_mode", &self.spi_smem_din0_mode())
+            .field("spi_smem_din1_mode", &self.spi_smem_din1_mode())
+            .field("spi_smem_din2_mode", &self.spi_smem_din2_mode())
+            .field("spi_smem_din3_mode", &self.spi_smem_din3_mode())
+            .field("spi_smem_din4_mode", &self.spi_smem_din4_mode())
+            .field("spi_smem_din5_mode", &self.spi_smem_din5_mode())
+            .field("spi_smem_din6_mode", &self.spi_smem_din6_mode())
+            .field("spi_smem_din7_mode", &self.spi_smem_din7_mode())
+            .field("spi_smem_dins_mode", &self.spi_smem_dins_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_smem_din_num.rs b/esp32p4/src/spi0/spi_smem_din_num.rs
index 263b687e4b..98481640aa 100644
--- a/esp32p4/src/spi0/spi_smem_din_num.rs
+++ b/esp32p4/src/spi0/spi_smem_din_num.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DIN_NUM")
-            .field(
-                "spi_smem_din0_num",
-                &format_args!("{}", self.spi_smem_din0_num().bits()),
-            )
-            .field(
-                "spi_smem_din1_num",
-                &format_args!("{}", self.spi_smem_din1_num().bits()),
-            )
-            .field(
-                "spi_smem_din2_num",
-                &format_args!("{}", self.spi_smem_din2_num().bits()),
-            )
-            .field(
-                "spi_smem_din3_num",
-                &format_args!("{}", self.spi_smem_din3_num().bits()),
-            )
-            .field(
-                "spi_smem_din4_num",
-                &format_args!("{}", self.spi_smem_din4_num().bits()),
-            )
-            .field(
-                "spi_smem_din5_num",
-                &format_args!("{}", self.spi_smem_din5_num().bits()),
-            )
-            .field(
-                "spi_smem_din6_num",
-                &format_args!("{}", self.spi_smem_din6_num().bits()),
-            )
-            .field(
-                "spi_smem_din7_num",
-                &format_args!("{}", self.spi_smem_din7_num().bits()),
-            )
-            .field(
-                "spi_smem_dins_num",
-                &format_args!("{}", self.spi_smem_dins_num().bits()),
-            )
+            .field("spi_smem_din0_num", &self.spi_smem_din0_num())
+            .field("spi_smem_din1_num", &self.spi_smem_din1_num())
+            .field("spi_smem_din2_num", &self.spi_smem_din2_num())
+            .field("spi_smem_din3_num", &self.spi_smem_din3_num())
+            .field("spi_smem_din4_num", &self.spi_smem_din4_num())
+            .field("spi_smem_din5_num", &self.spi_smem_din5_num())
+            .field("spi_smem_din6_num", &self.spi_smem_din6_num())
+            .field("spi_smem_din7_num", &self.spi_smem_din7_num())
+            .field("spi_smem_dins_num", &self.spi_smem_dins_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_smem_dout_hex_mode.rs b/esp32p4/src/spi0/spi_smem_dout_hex_mode.rs
index 4e6f37e7c9..1431700c26 100644
--- a/esp32p4/src/spi0/spi_smem_dout_hex_mode.rs
+++ b/esp32p4/src/spi0/spi_smem_dout_hex_mode.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DOUT_HEX_MODE")
-            .field(
-                "spi_smem_dout08_mode",
-                &format_args!("{}", self.spi_smem_dout08_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout09_mode",
-                &format_args!("{}", self.spi_smem_dout09_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout10_mode",
-                &format_args!("{}", self.spi_smem_dout10_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout11_mode",
-                &format_args!("{}", self.spi_smem_dout11_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout12_mode",
-                &format_args!("{}", self.spi_smem_dout12_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout13_mode",
-                &format_args!("{}", self.spi_smem_dout13_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout14_mode",
-                &format_args!("{}", self.spi_smem_dout14_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout15_mode",
-                &format_args!("{}", self.spi_smem_dout15_mode().bit()),
-            )
-            .field(
-                "spi_smem_douts_hex_mode",
-                &format_args!("{}", self.spi_smem_douts_hex_mode().bit()),
-            )
+            .field("spi_smem_dout08_mode", &self.spi_smem_dout08_mode())
+            .field("spi_smem_dout09_mode", &self.spi_smem_dout09_mode())
+            .field("spi_smem_dout10_mode", &self.spi_smem_dout10_mode())
+            .field("spi_smem_dout11_mode", &self.spi_smem_dout11_mode())
+            .field("spi_smem_dout12_mode", &self.spi_smem_dout12_mode())
+            .field("spi_smem_dout13_mode", &self.spi_smem_dout13_mode())
+            .field("spi_smem_dout14_mode", &self.spi_smem_dout14_mode())
+            .field("spi_smem_dout15_mode", &self.spi_smem_dout15_mode())
+            .field("spi_smem_douts_hex_mode", &self.spi_smem_douts_hex_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DOUT_HEX_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_smem_dout_mode.rs b/esp32p4/src/spi0/spi_smem_dout_mode.rs
index b49073f762..0fd83944a8 100644
--- a/esp32p4/src/spi0/spi_smem_dout_mode.rs
+++ b/esp32p4/src/spi0/spi_smem_dout_mode.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DOUT_MODE")
-            .field(
-                "spi_smem_dout0_mode",
-                &format_args!("{}", self.spi_smem_dout0_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout1_mode",
-                &format_args!("{}", self.spi_smem_dout1_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout2_mode",
-                &format_args!("{}", self.spi_smem_dout2_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout3_mode",
-                &format_args!("{}", self.spi_smem_dout3_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout4_mode",
-                &format_args!("{}", self.spi_smem_dout4_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout5_mode",
-                &format_args!("{}", self.spi_smem_dout5_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout6_mode",
-                &format_args!("{}", self.spi_smem_dout6_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout7_mode",
-                &format_args!("{}", self.spi_smem_dout7_mode().bit()),
-            )
-            .field(
-                "spi_smem_douts_mode",
-                &format_args!("{}", self.spi_smem_douts_mode().bit()),
-            )
+            .field("spi_smem_dout0_mode", &self.spi_smem_dout0_mode())
+            .field("spi_smem_dout1_mode", &self.spi_smem_dout1_mode())
+            .field("spi_smem_dout2_mode", &self.spi_smem_dout2_mode())
+            .field("spi_smem_dout3_mode", &self.spi_smem_dout3_mode())
+            .field("spi_smem_dout4_mode", &self.spi_smem_dout4_mode())
+            .field("spi_smem_dout5_mode", &self.spi_smem_dout5_mode())
+            .field("spi_smem_dout6_mode", &self.spi_smem_dout6_mode())
+            .field("spi_smem_dout7_mode", &self.spi_smem_dout7_mode())
+            .field("spi_smem_douts_mode", &self.spi_smem_douts_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_smem_ecc_ctrl.rs b/esp32p4/src/spi0/spi_smem_ecc_ctrl.rs
index a282f7d5fc..978b3848eb 100644
--- a/esp32p4/src/spi0/spi_smem_ecc_ctrl.rs
+++ b/esp32p4/src/spi0/spi_smem_ecc_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_ECC_CTRL")
-            .field(
-                "spi_smem_ecc_err_int_en",
-                &format_args!("{}", self.spi_smem_ecc_err_int_en().bit()),
-            )
-            .field(
-                "spi_smem_page_size",
-                &format_args!("{}", self.spi_smem_page_size().bits()),
-            )
-            .field(
-                "spi_smem_ecc_addr_en",
-                &format_args!("{}", self.spi_smem_ecc_addr_en().bit()),
-            )
+            .field("spi_smem_ecc_err_int_en", &self.spi_smem_ecc_err_int_en())
+            .field("spi_smem_page_size", &self.spi_smem_page_size())
+            .field("spi_smem_ecc_addr_en", &self.spi_smem_ecc_addr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_ECC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_smem_pms_addr.rs b/esp32p4/src/spi0/spi_smem_pms_addr.rs
index 8a3eff03ab..8f1296b860 100644
--- a/esp32p4/src/spi0/spi_smem_pms_addr.rs
+++ b/esp32p4/src/spi0/spi_smem_pms_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_PMS_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_PMS_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:26 - SPI1 external RAM PMS section %s start address value"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_smem_pms_attr.rs b/esp32p4/src/spi0/spi_smem_pms_attr.rs
index 53123e1575..04cea5ca86 100644
--- a/esp32p4/src/spi0/spi_smem_pms_attr.rs
+++ b/esp32p4/src/spi0/spi_smem_pms_attr.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_PMS_ATTR")
-            .field(
-                "spi_smem_pms_rd_attr",
-                &format_args!("{}", self.spi_smem_pms_rd_attr().bit()),
-            )
-            .field(
-                "spi_smem_pms_wr_attr",
-                &format_args!("{}", self.spi_smem_pms_wr_attr().bit()),
-            )
-            .field(
-                "spi_smem_pms_ecc",
-                &format_args!("{}", self.spi_smem_pms_ecc().bit()),
-            )
+            .field("spi_smem_pms_rd_attr", &self.spi_smem_pms_rd_attr())
+            .field("spi_smem_pms_wr_attr", &self.spi_smem_pms_wr_attr())
+            .field("spi_smem_pms_ecc", &self.spi_smem_pms_ecc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_PMS_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: SPI1 external RAM PMS section %s read accessible. 0: Not allowed."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_smem_pms_size.rs b/esp32p4/src/spi0/spi_smem_pms_size.rs
index 45450632e5..7a5f1f4ead 100644
--- a/esp32p4/src/spi0/spi_smem_pms_size.rs
+++ b/esp32p4/src/spi0/spi_smem_pms_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_PMS_SIZE")
-            .field(
-                "spi_smem_pms_size",
-                &format_args!("{}", self.spi_smem_pms_size().bits()),
-            )
+            .field("spi_smem_pms_size", &self.spi_smem_pms_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_PMS_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - SPI1 external RAM PMS section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE)"]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/spi_smem_timing_cali.rs b/esp32p4/src/spi0/spi_smem_timing_cali.rs
index caf3f6dfba..068694c434 100644
--- a/esp32p4/src/spi0/spi_smem_timing_cali.rs
+++ b/esp32p4/src/spi0/spi_smem_timing_cali.rs
@@ -44,31 +44,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_TIMING_CALI")
-            .field(
-                "spi_smem_timing_clk_ena",
-                &format_args!("{}", self.spi_smem_timing_clk_ena().bit()),
-            )
-            .field(
-                "spi_smem_timing_cali",
-                &format_args!("{}", self.spi_smem_timing_cali().bit()),
-            )
+            .field("spi_smem_timing_clk_ena", &self.spi_smem_timing_clk_ena())
+            .field("spi_smem_timing_cali", &self.spi_smem_timing_cali())
             .field(
                 "spi_smem_extra_dummy_cyclelen",
-                &format_args!("{}", self.spi_smem_extra_dummy_cyclelen().bits()),
-            )
-            .field(
-                "spi_smem_dll_timing_cali",
-                &format_args!("{}", self.spi_smem_dll_timing_cali().bit()),
+                &self.spi_smem_extra_dummy_cyclelen(),
             )
+            .field("spi_smem_dll_timing_cali", &self.spi_smem_dll_timing_cali())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - For sram, the bit is used to enable timing adjust clock for all reading operations."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/sram_clk.rs b/esp32p4/src/spi0/sram_clk.rs
index 8aca0e6af6..1a3f126d16 100644
--- a/esp32p4/src/spi0/sram_clk.rs
+++ b/esp32p4/src/spi0/sram_clk.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_CLK")
-            .field("sclkcnt_l", &format_args!("{}", self.sclkcnt_l().bits()))
-            .field("sclkcnt_h", &format_args!("{}", self.sclkcnt_h().bits()))
-            .field("sclkcnt_n", &format_args!("{}", self.sclkcnt_n().bits()))
-            .field(
-                "sclk_equ_sysclk",
-                &format_args!("{}", self.sclk_equ_sysclk().bit()),
-            )
+            .field("sclkcnt_l", &self.sclkcnt_l())
+            .field("sclkcnt_h", &self.sclkcnt_h())
+            .field("sclkcnt_n", &self.sclkcnt_n())
+            .field("sclk_equ_sysclk", &self.sclk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/sram_cmd.rs b/esp32p4/src/spi0/sram_cmd.rs
index 0851209585..3c30b52db0 100644
--- a/esp32p4/src/spi0/sram_cmd.rs
+++ b/esp32p4/src/spi0/sram_cmd.rs
@@ -197,48 +197,42 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_CMD")
-            .field("sclk_mode", &format_args!("{}", self.sclk_mode().bits()))
-            .field("swb_mode", &format_args!("{}", self.swb_mode().bits()))
-            .field("sdin_dual", &format_args!("{}", self.sdin_dual().bit()))
-            .field("sdout_dual", &format_args!("{}", self.sdout_dual().bit()))
-            .field("saddr_dual", &format_args!("{}", self.saddr_dual().bit()))
-            .field("sdin_quad", &format_args!("{}", self.sdin_quad().bit()))
-            .field("sdout_quad", &format_args!("{}", self.sdout_quad().bit()))
-            .field("saddr_quad", &format_args!("{}", self.saddr_quad().bit()))
-            .field("scmd_quad", &format_args!("{}", self.scmd_quad().bit()))
-            .field("sdin_oct", &format_args!("{}", self.sdin_oct().bit()))
-            .field("sdout_oct", &format_args!("{}", self.sdout_oct().bit()))
-            .field("saddr_oct", &format_args!("{}", self.saddr_oct().bit()))
-            .field("scmd_oct", &format_args!("{}", self.scmd_oct().bit()))
-            .field("sdummy_rin", &format_args!("{}", self.sdummy_rin().bit()))
-            .field("sdummy_wout", &format_args!("{}", self.sdummy_wout().bit()))
+            .field("sclk_mode", &self.sclk_mode())
+            .field("swb_mode", &self.swb_mode())
+            .field("sdin_dual", &self.sdin_dual())
+            .field("sdout_dual", &self.sdout_dual())
+            .field("saddr_dual", &self.saddr_dual())
+            .field("sdin_quad", &self.sdin_quad())
+            .field("sdout_quad", &self.sdout_quad())
+            .field("saddr_quad", &self.saddr_quad())
+            .field("scmd_quad", &self.scmd_quad())
+            .field("sdin_oct", &self.sdin_oct())
+            .field("sdout_oct", &self.sdout_oct())
+            .field("saddr_oct", &self.saddr_oct())
+            .field("scmd_oct", &self.scmd_oct())
+            .field("sdummy_rin", &self.sdummy_rin())
+            .field("sdummy_wout", &self.sdummy_wout())
             .field(
                 "spi_smem_wdummy_dqs_always_out",
-                &format_args!("{}", self.spi_smem_wdummy_dqs_always_out().bit()),
+                &self.spi_smem_wdummy_dqs_always_out(),
             )
             .field(
                 "spi_smem_wdummy_always_out",
-                &format_args!("{}", self.spi_smem_wdummy_always_out().bit()),
+                &self.spi_smem_wdummy_always_out(),
             )
-            .field("sdin_hex", &format_args!("{}", self.sdin_hex().bit()))
-            .field("sdout_hex", &format_args!("{}", self.sdout_hex().bit()))
+            .field("sdin_hex", &self.sdin_hex())
+            .field("sdout_hex", &self.sdout_hex())
             .field(
                 "spi_smem_dqs_ie_always_on",
-                &format_args!("{}", self.spi_smem_dqs_ie_always_on().bit()),
+                &self.spi_smem_dqs_ie_always_on(),
             )
             .field(
                 "spi_smem_data_ie_always_on",
-                &format_args!("{}", self.spi_smem_data_ie_always_on().bit()),
+                &self.spi_smem_data_ie_always_on(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/sram_drd_cmd.rs b/esp32p4/src/spi0/sram_drd_cmd.rs
index 1bb4f1613d..c1e6a4bced 100644
--- a/esp32p4/src/spi0/sram_drd_cmd.rs
+++ b/esp32p4/src/spi0/sram_drd_cmd.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("SRAM_DRD_CMD")
             .field(
                 "cache_sram_usr_rd_cmd_value",
-                &format_args!("{}", self.cache_sram_usr_rd_cmd_value().bits()),
+                &self.cache_sram_usr_rd_cmd_value(),
             )
             .field(
                 "cache_sram_usr_rd_cmd_bitlen",
-                &format_args!("{}", self.cache_sram_usr_rd_cmd_bitlen().bits()),
+                &self.cache_sram_usr_rd_cmd_bitlen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_DRD_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - For SPI0,When cache mode is enable it is the read command value of command phase for sram."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/sram_dwr_cmd.rs b/esp32p4/src/spi0/sram_dwr_cmd.rs
index eb1a89d601..28d7cbb894 100644
--- a/esp32p4/src/spi0/sram_dwr_cmd.rs
+++ b/esp32p4/src/spi0/sram_dwr_cmd.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("SRAM_DWR_CMD")
             .field(
                 "cache_sram_usr_wr_cmd_value",
-                &format_args!("{}", self.cache_sram_usr_wr_cmd_value().bits()),
+                &self.cache_sram_usr_wr_cmd_value(),
             )
             .field(
                 "cache_sram_usr_wr_cmd_bitlen",
-                &format_args!("{}", self.cache_sram_usr_wr_cmd_bitlen().bits()),
+                &self.cache_sram_usr_wr_cmd_bitlen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_DWR_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - For SPI0,When cache mode is enable it is the write command value of command phase for sram."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/timing_cali.rs b/esp32p4/src/spi0/timing_cali.rs
index a4c4dfb115..89f1e1394e 100644
--- a/esp32p4/src/spi0/timing_cali.rs
+++ b/esp32p4/src/spi0/timing_cali.rs
@@ -46,28 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMING_CALI")
-            .field(
-                "timing_clk_ena",
-                &format_args!("{}", self.timing_clk_ena().bit()),
-            )
-            .field("timing_cali", &format_args!("{}", self.timing_cali().bit()))
-            .field(
-                "extra_dummy_cyclelen",
-                &format_args!("{}", self.extra_dummy_cyclelen().bits()),
-            )
-            .field(
-                "dll_timing_cali",
-                &format_args!("{}", self.dll_timing_cali().bit()),
-            )
+            .field("timing_clk_ena", &self.timing_clk_ena())
+            .field("timing_cali", &self.timing_cali())
+            .field("extra_dummy_cyclelen", &self.extra_dummy_cyclelen())
+            .field("dll_timing_cali", &self.dll_timing_cali())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable timing adjust clock for all reading operations."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/user.rs b/esp32p4/src/spi0/user.rs
index 3af8b9a5f6..7c1da8336d 100644
--- a/esp32p4/src/spi0/user.rs
+++ b/esp32p4/src/spi0/user.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
-            .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
+            .field("cs_hold", &self.cs_hold())
+            .field("cs_setup", &self.cs_setup())
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_dummy", &self.usr_dummy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - spi cs keep low when spi is in done phase. 1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/user1.rs b/esp32p4/src/spi0/user1.rs
index 7261a1c0de..a951f31e26 100644
--- a/esp32p4/src/spi0/user1.rs
+++ b/esp32p4/src/spi0/user1.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "usr_dbytelen",
-                &format_args!("{}", self.usr_dbytelen().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("usr_dbytelen", &self.usr_dbytelen())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/user2.rs b/esp32p4/src/spi0/user2.rs
index 801f605c21..d0bf1413f5 100644
--- a/esp32p4/src/spi0/user2.rs
+++ b/esp32p4/src/spi0/user2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/xts_date.rs b/esp32p4/src/spi0/xts_date.rs
index f4626fb790..6a76691ffc 100644
--- a/esp32p4/src/spi0/xts_date.rs
+++ b/esp32p4/src/spi0/xts_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_DATE")
-            .field(
-                "spi_xts_date",
-                &format_args!("{}", self.spi_xts_date().bits()),
-            )
+            .field("spi_xts_date", &self.spi_xts_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - This bits stores the last modified-time of manual encryption feature."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/xts_destination.rs b/esp32p4/src/spi0/xts_destination.rs
index b892575ff3..53d1dc0664 100644
--- a/esp32p4/src/spi0/xts_destination.rs
+++ b/esp32p4/src/spi0/xts_destination.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_DESTINATION")
-            .field(
-                "spi_xts_destination",
-                &format_args!("{}", self.spi_xts_destination().bit()),
-            )
+            .field("spi_xts_destination", &self.spi_xts_destination())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_DESTINATION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/xts_linesize.rs b/esp32p4/src/spi0/xts_linesize.rs
index 69dda9b934..026adf4932 100644
--- a/esp32p4/src/spi0/xts_linesize.rs
+++ b/esp32p4/src/spi0/xts_linesize.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_LINESIZE")
-            .field(
-                "spi_xts_linesize",
-                &format_args!("{}", self.spi_xts_linesize().bits()),
-            )
+            .field("spi_xts_linesize", &self.spi_xts_linesize())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_LINESIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/xts_physical_address.rs b/esp32p4/src/spi0/xts_physical_address.rs
index 1c5e63ce4a..0bf10b2a3d 100644
--- a/esp32p4/src/spi0/xts_physical_address.rs
+++ b/esp32p4/src/spi0/xts_physical_address.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_PHYSICAL_ADDRESS")
-            .field(
-                "spi_xts_physical_address",
-                &format_args!("{}", self.spi_xts_physical_address().bits()),
-            )
+            .field("spi_xts_physical_address", &self.spi_xts_physical_address())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_PHYSICAL_ADDRESS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/xts_plain_base.rs b/esp32p4/src/spi0/xts_plain_base.rs
index 576a75225c..b411736db1 100644
--- a/esp32p4/src/spi0/xts_plain_base.rs
+++ b/esp32p4/src/spi0/xts_plain_base.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_PLAIN_BASE")
-            .field(
-                "spi_xts_plain",
-                &format_args!("{}", self.spi_xts_plain().bits()),
-            )
+            .field("spi_xts_plain", &self.spi_xts_plain())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_PLAIN_BASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This field is only used to generate include file in c case. This field is useless. Please do not use this field."]
     #[inline(always)]
diff --git a/esp32p4/src/spi0/xts_state.rs b/esp32p4/src/spi0/xts_state.rs
index f60c84f30c..7ce2fd6e44 100644
--- a/esp32p4/src/spi0/xts_state.rs
+++ b/esp32p4/src/spi0/xts_state.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTS_STATE")
-            .field(
-                "spi_xts_state",
-                &format_args!("{}", self.spi_xts_state().bits()),
-            )
+            .field("spi_xts_state", &self.spi_xts_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTS_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Manual Encryption physical address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xts_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct XTS_STATE_SPEC;
 impl crate::RegisterSpec for XTS_STATE_SPEC {
diff --git a/esp32p4/src/spi1/addr.rs b/esp32p4/src/spi1/addr.rs
index 565e7916d4..cc9a0e1b42 100644
--- a/esp32p4/src/spi1/addr.rs
+++ b/esp32p4/src/spi1/addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR")
-            .field(
-                "usr_addr_value",
-                &format_args!("{}", self.usr_addr_value().bits()),
-            )
+            .field("usr_addr_value", &self.usr_addr_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/cache_fctrl.rs b/esp32p4/src/spi1/cache_fctrl.rs
index c8eafade55..3a22f1f847 100644
--- a/esp32p4/src/spi1/cache_fctrl.rs
+++ b/esp32p4/src/spi1/cache_fctrl.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_FCTRL")
-            .field(
-                "cache_usr_addr_4byte",
-                &format_args!("{}", self.cache_usr_addr_4byte().bit()),
-            )
-            .field("fdin_dual", &format_args!("{}", self.fdin_dual().bit()))
-            .field("fdout_dual", &format_args!("{}", self.fdout_dual().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("fdin_quad", &format_args!("{}", self.fdin_quad().bit()))
-            .field("fdout_quad", &format_args!("{}", self.fdout_quad().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
+            .field("cache_usr_addr_4byte", &self.cache_usr_addr_4byte())
+            .field("fdin_dual", &self.fdin_dual())
+            .field("fdout_dual", &self.fdout_dual())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("fdin_quad", &self.fdin_quad())
+            .field("fdout_quad", &self.fdout_quad())
+            .field("faddr_quad", &self.faddr_quad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_FCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/clock.rs b/esp32p4/src/spi1/clock.rs
index 250a0c660f..ec805aad92 100644
--- a/esp32p4/src/spi1/clock.rs
+++ b/esp32p4/src/spi1/clock.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In the master mode it must be equal to spi_mem_clkcnt_N."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/clock_gate.rs b/esp32p4/src/spi1/clock_gate.rs
index c60d396767..69477e9842 100644
--- a/esp32p4/src/spi1/clock_gate.rs
+++ b/esp32p4/src/spi1/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/cmd.rs b/esp32p4/src/spi1/cmd.rs
index 8c3307af4a..6cb80f8502 100644
--- a/esp32p4/src/spi1/cmd.rs
+++ b/esp32p4/src/spi1/cmd.rs
@@ -157,32 +157,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("mst_st", &format_args!("{}", self.mst_st().bits()))
-            .field("slv_st", &format_args!("{}", self.slv_st().bits()))
-            .field("flash_pe", &format_args!("{}", self.flash_pe().bit()))
-            .field("usr", &format_args!("{}", self.usr().bit()))
-            .field("flash_hpm", &format_args!("{}", self.flash_hpm().bit()))
-            .field("flash_res", &format_args!("{}", self.flash_res().bit()))
-            .field("flash_dp", &format_args!("{}", self.flash_dp().bit()))
-            .field("flash_ce", &format_args!("{}", self.flash_ce().bit()))
-            .field("flash_be", &format_args!("{}", self.flash_be().bit()))
-            .field("flash_se", &format_args!("{}", self.flash_se().bit()))
-            .field("flash_pp", &format_args!("{}", self.flash_pp().bit()))
-            .field("flash_wrsr", &format_args!("{}", self.flash_wrsr().bit()))
-            .field("flash_rdsr", &format_args!("{}", self.flash_rdsr().bit()))
-            .field("flash_rdid", &format_args!("{}", self.flash_rdid().bit()))
-            .field("flash_wrdi", &format_args!("{}", self.flash_wrdi().bit()))
-            .field("flash_wren", &format_args!("{}", self.flash_wren().bit()))
-            .field("flash_read", &format_args!("{}", self.flash_read().bit()))
+            .field("mst_st", &self.mst_st())
+            .field("slv_st", &self.slv_st())
+            .field("flash_pe", &self.flash_pe())
+            .field("usr", &self.usr())
+            .field("flash_hpm", &self.flash_hpm())
+            .field("flash_res", &self.flash_res())
+            .field("flash_dp", &self.flash_dp())
+            .field("flash_ce", &self.flash_ce())
+            .field("flash_be", &self.flash_be())
+            .field("flash_se", &self.flash_se())
+            .field("flash_pp", &self.flash_pp())
+            .field("flash_wrsr", &self.flash_wrsr())
+            .field("flash_rdsr", &self.flash_rdsr())
+            .field("flash_rdid", &self.flash_rdid())
+            .field("flash_wrdi", &self.flash_wrdi())
+            .field("flash_wren", &self.flash_wren())
+            .field("flash_read", &self.flash_read())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/ctrl.rs b/esp32p4/src/spi1/ctrl.rs
index c478f11331..0402cf9912 100644
--- a/esp32p4/src/spi1/ctrl.rs
+++ b/esp32p4/src/spi1/ctrl.rs
@@ -179,34 +179,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("fdummy_rin", &format_args!("{}", self.fdummy_rin().bit()))
-            .field("fdummy_wout", &format_args!("{}", self.fdummy_wout().bit()))
-            .field("fdout_oct", &format_args!("{}", self.fdout_oct().bit()))
-            .field("fdin_oct", &format_args!("{}", self.fdin_oct().bit()))
-            .field("faddr_oct", &format_args!("{}", self.faddr_oct().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcmd_oct", &format_args!("{}", self.fcmd_oct().bit()))
-            .field("fcs_crc_en", &format_args!("{}", self.fcs_crc_en().bit()))
-            .field("tx_crc_en", &format_args!("{}", self.tx_crc_en().bit()))
-            .field("fastrd_mode", &format_args!("{}", self.fastrd_mode().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("resandres", &format_args!("{}", self.resandres().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("wp", &format_args!("{}", self.wp().bit()))
-            .field("wrsr_2b", &format_args!("{}", self.wrsr_2b().bit()))
-            .field("fread_dio", &format_args!("{}", self.fread_dio().bit()))
-            .field("fread_qio", &format_args!("{}", self.fread_qio().bit()))
+            .field("fdummy_rin", &self.fdummy_rin())
+            .field("fdummy_wout", &self.fdummy_wout())
+            .field("fdout_oct", &self.fdout_oct())
+            .field("fdin_oct", &self.fdin_oct())
+            .field("faddr_oct", &self.faddr_oct())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcmd_oct", &self.fcmd_oct())
+            .field("fcs_crc_en", &self.fcs_crc_en())
+            .field("tx_crc_en", &self.tx_crc_en())
+            .field("fastrd_mode", &self.fastrd_mode())
+            .field("fread_dual", &self.fread_dual())
+            .field("resandres", &self.resandres())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("fread_quad", &self.fread_quad())
+            .field("wp", &self.wp())
+            .field("wrsr_2b", &self.wrsr_2b())
+            .field("fread_dio", &self.fread_dio())
+            .field("fread_qio", &self.fread_qio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/ctrl1.rs b/esp32p4/src/spi1/ctrl1.rs
index 72546d185b..bde8ad35ad 100644
--- a/esp32p4/src/spi1/ctrl1.rs
+++ b/esp32p4/src/spi1/ctrl1.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL1")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
-            .field(
-                "cs_hold_dly_res",
-                &format_args!("{}", self.cs_hold_dly_res().bits()),
-            )
+            .field("clk_mode", &self.clk_mode())
+            .field("cs_hold_dly_res", &self.cs_hold_dly_res())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/date.rs b/esp32p4/src/spi1/date.rs
index bc9dcf2227..7491655035 100644
--- a/esp32p4/src/spi1/date.rs
+++ b/esp32p4/src/spi1/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/spi1/ddr.rs b/esp32p4/src/spi1/ddr.rs
index 552cd05d65..00c26b17eb 100644
--- a/esp32p4/src/spi1/ddr.rs
+++ b/esp32p4/src/spi1/ddr.rs
@@ -134,71 +134,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DDR")
-            .field(
-                "spi_fmem_ddr_en",
-                &format_args!("{}", self.spi_fmem_ddr_en().bit()),
-            )
-            .field(
-                "spi_fmem_var_dummy",
-                &format_args!("{}", self.spi_fmem_var_dummy().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_rdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_rdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_wdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_wdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_cmd_dis",
-                &format_args!("{}", self.spi_fmem_ddr_cmd_dis().bit()),
-            )
-            .field(
-                "spi_fmem_outminbytelen",
-                &format_args!("{}", self.spi_fmem_outminbytelen().bits()),
-            )
-            .field(
-                "spi_fmem_usr_ddr_dqs_thd",
-                &format_args!("{}", self.spi_fmem_usr_ddr_dqs_thd().bits()),
-            )
-            .field(
-                "spi_fmem_ddr_dqs_loop",
-                &format_args!("{}", self.spi_fmem_ddr_dqs_loop().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_en",
-                &format_args!("{}", self.spi_fmem_clk_diff_en().bit()),
-            )
-            .field(
-                "spi_fmem_dqs_ca_in",
-                &format_args!("{}", self.spi_fmem_dqs_ca_in().bit()),
-            )
+            .field("spi_fmem_ddr_en", &self.spi_fmem_ddr_en())
+            .field("spi_fmem_var_dummy", &self.spi_fmem_var_dummy())
+            .field("spi_fmem_ddr_rdat_swp", &self.spi_fmem_ddr_rdat_swp())
+            .field("spi_fmem_ddr_wdat_swp", &self.spi_fmem_ddr_wdat_swp())
+            .field("spi_fmem_ddr_cmd_dis", &self.spi_fmem_ddr_cmd_dis())
+            .field("spi_fmem_outminbytelen", &self.spi_fmem_outminbytelen())
+            .field("spi_fmem_usr_ddr_dqs_thd", &self.spi_fmem_usr_ddr_dqs_thd())
+            .field("spi_fmem_ddr_dqs_loop", &self.spi_fmem_ddr_dqs_loop())
+            .field("spi_fmem_clk_diff_en", &self.spi_fmem_clk_diff_en())
+            .field("spi_fmem_dqs_ca_in", &self.spi_fmem_dqs_ca_in())
             .field(
                 "spi_fmem_hyperbus_dummy_2x",
-                &format_args!("{}", self.spi_fmem_hyperbus_dummy_2x().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_inv",
-                &format_args!("{}", self.spi_fmem_clk_diff_inv().bit()),
-            )
-            .field(
-                "spi_fmem_octa_ram_addr",
-                &format_args!("{}", self.spi_fmem_octa_ram_addr().bit()),
-            )
-            .field(
-                "spi_fmem_hyperbus_ca",
-                &format_args!("{}", self.spi_fmem_hyperbus_ca().bit()),
+                &self.spi_fmem_hyperbus_dummy_2x(),
             )
+            .field("spi_fmem_clk_diff_inv", &self.spi_fmem_clk_diff_inv())
+            .field("spi_fmem_octa_ram_addr", &self.spi_fmem_octa_ram_addr())
+            .field("spi_fmem_hyperbus_ca", &self.spi_fmem_hyperbus_ca())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: in ddr mode, 0 in sdr mode"]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/flash_sus_cmd.rs b/esp32p4/src/spi1/flash_sus_cmd.rs
index 7d99bea28f..7ad88afb97 100644
--- a/esp32p4/src/spi1/flash_sus_cmd.rs
+++ b/esp32p4/src/spi1/flash_sus_cmd.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_SUS_CMD")
-            .field(
-                "flash_pes_command",
-                &format_args!("{}", self.flash_pes_command().bits()),
-            )
-            .field(
-                "wait_pesr_command",
-                &format_args!("{}", self.wait_pesr_command().bits()),
-            )
+            .field("flash_pes_command", &self.flash_pes_command())
+            .field("wait_pesr_command", &self.wait_pesr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_SUS_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Program/Erase suspend command."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/flash_sus_ctrl.rs b/esp32p4/src/spi1/flash_sus_ctrl.rs
index 187f971488..1f8d0298dd 100644
--- a/esp32p4/src/spi1/flash_sus_ctrl.rs
+++ b/esp32p4/src/spi1/flash_sus_ctrl.rs
@@ -107,44 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_SUS_CTRL")
-            .field("flash_per", &format_args!("{}", self.flash_per().bit()))
-            .field("flash_pes", &format_args!("{}", self.flash_pes().bit()))
-            .field(
-                "flash_per_wait_en",
-                &format_args!("{}", self.flash_per_wait_en().bit()),
-            )
-            .field(
-                "flash_pes_wait_en",
-                &format_args!("{}", self.flash_pes_wait_en().bit()),
-            )
-            .field("pes_per_en", &format_args!("{}", self.pes_per_en().bit()))
-            .field(
-                "flash_pes_en",
-                &format_args!("{}", self.flash_pes_en().bit()),
-            )
-            .field(
-                "pesr_end_msk",
-                &format_args!("{}", self.pesr_end_msk().bits()),
-            )
-            .field(
-                "spi_fmem_rd_sus_2b",
-                &format_args!("{}", self.spi_fmem_rd_sus_2b().bit()),
-            )
-            .field("per_end_en", &format_args!("{}", self.per_end_en().bit()))
-            .field("pes_end_en", &format_args!("{}", self.pes_end_en().bit()))
-            .field(
-                "sus_timeout_cnt",
-                &format_args!("{}", self.sus_timeout_cnt().bits()),
-            )
+            .field("flash_per", &self.flash_per())
+            .field("flash_pes", &self.flash_pes())
+            .field("flash_per_wait_en", &self.flash_per_wait_en())
+            .field("flash_pes_wait_en", &self.flash_pes_wait_en())
+            .field("pes_per_en", &self.pes_per_en())
+            .field("flash_pes_en", &self.flash_pes_en())
+            .field("pesr_end_msk", &self.pesr_end_msk())
+            .field("spi_fmem_rd_sus_2b", &self.spi_fmem_rd_sus_2b())
+            .field("per_end_en", &self.per_end_en())
+            .field("pes_end_en", &self.pes_end_en())
+            .field("sus_timeout_cnt", &self.sus_timeout_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_SUS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/flash_waiti_ctrl.rs b/esp32p4/src/spi1/flash_waiti_ctrl.rs
index 324fe5b02e..d41f29aa1b 100644
--- a/esp32p4/src/spi1/flash_waiti_ctrl.rs
+++ b/esp32p4/src/spi1/flash_waiti_ctrl.rs
@@ -71,34 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_WAITI_CTRL")
-            .field("waiti_en", &format_args!("{}", self.waiti_en().bit()))
-            .field("waiti_dummy", &format_args!("{}", self.waiti_dummy().bit()))
-            .field(
-                "waiti_addr_en",
-                &format_args!("{}", self.waiti_addr_en().bit()),
-            )
-            .field(
-                "waiti_addr_cyclelen",
-                &format_args!("{}", self.waiti_addr_cyclelen().bits()),
-            )
-            .field(
-                "waiti_cmd_2b",
-                &format_args!("{}", self.waiti_cmd_2b().bit()),
-            )
-            .field(
-                "waiti_dummy_cyclelen",
-                &format_args!("{}", self.waiti_dummy_cyclelen().bits()),
-            )
-            .field("waiti_cmd", &format_args!("{}", self.waiti_cmd().bits()))
+            .field("waiti_en", &self.waiti_en())
+            .field("waiti_dummy", &self.waiti_dummy())
+            .field("waiti_addr_en", &self.waiti_addr_en())
+            .field("waiti_addr_cyclelen", &self.waiti_addr_cyclelen())
+            .field("waiti_cmd_2b", &self.waiti_cmd_2b())
+            .field("waiti_dummy_cyclelen", &self.waiti_dummy_cyclelen())
+            .field("waiti_cmd", &self.waiti_cmd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_WAITI_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/int_ena.rs b/esp32p4/src/spi1/int_ena.rs
index bbd8af0e24..48dff931c1 100644
--- a/esp32p4/src/spi1/int_ena.rs
+++ b/esp32p4/src/spi1/int_ena.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("wpe_end", &self.wpe_end())
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("brown_out", &self.brown_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for SPI_MEM_PER_END_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/int_raw.rs b/esp32p4/src/spi1/int_raw.rs
index ae2ed7bc65..f67b50c6c6 100644
--- a/esp32p4/src/spi1/int_raw.rs
+++ b/esp32p4/src/spi1/int_raw.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("wpe_end", &self.wpe_end())
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("brown_out", &self.brown_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/int_st.rs b/esp32p4/src/spi1/int_st.rs
index b0d692f153..10cf1a6c2d 100644
--- a/esp32p4/src/spi1/int_st.rs
+++ b/esp32p4/src/spi1/int_st.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field("wpe_end", &format_args!("{}", self.wpe_end().bit()))
-            .field("slv_st_end", &format_args!("{}", self.slv_st_end().bit()))
-            .field("mst_st_end", &format_args!("{}", self.mst_st_end().bit()))
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("wpe_end", &self.wpe_end())
+            .field("slv_st_end", &self.slv_st_end())
+            .field("mst_st_end", &self.mst_st_end())
+            .field("brown_out", &self.brown_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/spi1/misc.rs b/esp32p4/src/spi1/misc.rs
index 980afa45ae..7c1f213c28 100644
--- a/esp32p4/src/spi1/misc.rs
+++ b/esp32p4/src/spi1/misc.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
-            .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/miso_dlen.rs b/esp32p4/src/spi1/miso_dlen.rs
index 737f493c8c..6813af19b3 100644
--- a/esp32p4/src/spi1/miso_dlen.rs
+++ b/esp32p4/src/spi1/miso_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISO_DLEN")
-            .field(
-                "usr_miso_dbitlen",
-                &format_args!("{}", self.usr_miso_dbitlen().bits()),
-            )
+            .field("usr_miso_dbitlen", &self.usr_miso_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISO_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The length in bits of read-data. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/mosi_dlen.rs b/esp32p4/src/spi1/mosi_dlen.rs
index b21b936f88..5cd5d155af 100644
--- a/esp32p4/src/spi1/mosi_dlen.rs
+++ b/esp32p4/src/spi1/mosi_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MOSI_DLEN")
-            .field(
-                "usr_mosi_dbitlen",
-                &format_args!("{}", self.usr_mosi_dbitlen().bits()),
-            )
+            .field("usr_mosi_dbitlen", &self.usr_mosi_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MOSI_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The length in bits of write-data. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/rd_status.rs b/esp32p4/src/spi1/rd_status.rs
index 6088e50d21..7368a19e92 100644
--- a/esp32p4/src/spi1/rd_status.rs
+++ b/esp32p4/src/spi1/rd_status.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_STATUS")
-            .field("status", &format_args!("{}", self.status().bits()))
-            .field("wb_mode", &format_args!("{}", self.wb_mode().bits()))
+            .field("status", &self.status())
+            .field("wb_mode", &self.wb_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/sus_status.rs b/esp32p4/src/spi1/sus_status.rs
index 80d580228b..8ad4de6524 100644
--- a/esp32p4/src/spi1/sus_status.rs
+++ b/esp32p4/src/spi1/sus_status.rs
@@ -98,52 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SUS_STATUS")
-            .field("flash_sus", &format_args!("{}", self.flash_sus().bit()))
-            .field(
-                "wait_pesr_cmd_2b",
-                &format_args!("{}", self.wait_pesr_cmd_2b().bit()),
-            )
-            .field(
-                "flash_hpm_dly_128",
-                &format_args!("{}", self.flash_hpm_dly_128().bit()),
-            )
-            .field(
-                "flash_res_dly_128",
-                &format_args!("{}", self.flash_res_dly_128().bit()),
-            )
-            .field(
-                "flash_dp_dly_128",
-                &format_args!("{}", self.flash_dp_dly_128().bit()),
-            )
-            .field(
-                "flash_per_dly_128",
-                &format_args!("{}", self.flash_per_dly_128().bit()),
-            )
-            .field(
-                "flash_pes_dly_128",
-                &format_args!("{}", self.flash_pes_dly_128().bit()),
-            )
-            .field(
-                "spi0_lock_en",
-                &format_args!("{}", self.spi0_lock_en().bit()),
-            )
-            .field(
-                "flash_pesr_cmd_2b",
-                &format_args!("{}", self.flash_pesr_cmd_2b().bit()),
-            )
-            .field(
-                "flash_per_command",
-                &format_args!("{}", self.flash_per_command().bits()),
-            )
+            .field("flash_sus", &self.flash_sus())
+            .field("wait_pesr_cmd_2b", &self.wait_pesr_cmd_2b())
+            .field("flash_hpm_dly_128", &self.flash_hpm_dly_128())
+            .field("flash_res_dly_128", &self.flash_res_dly_128())
+            .field("flash_dp_dly_128", &self.flash_dp_dly_128())
+            .field("flash_per_dly_128", &self.flash_per_dly_128())
+            .field("flash_pes_dly_128", &self.flash_pes_dly_128())
+            .field("spi0_lock_en", &self.spi0_lock_en())
+            .field("flash_pesr_cmd_2b", &self.flash_pesr_cmd_2b())
+            .field("flash_per_command", &self.flash_per_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SUS_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The status of flash suspend, only used in SPI1."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/timing_cali.rs b/esp32p4/src/spi1/timing_cali.rs
index 507064ae31..c6a30a5847 100644
--- a/esp32p4/src/spi1/timing_cali.rs
+++ b/esp32p4/src/spi1/timing_cali.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMING_CALI")
-            .field("timing_cali", &format_args!("{}", self.timing_cali().bit()))
-            .field(
-                "extra_dummy_cyclelen",
-                &format_args!("{}", self.extra_dummy_cyclelen().bits()),
-            )
+            .field("timing_cali", &self.timing_cali())
+            .field("extra_dummy_cyclelen", &self.extra_dummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - The bit is used to enable timing auto-calibration for all reading operations."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/tx_crc.rs b/esp32p4/src/spi1/tx_crc.rs
index 9faa1c440d..253fff1be1 100644
--- a/esp32p4/src/spi1/tx_crc.rs
+++ b/esp32p4/src/spi1/tx_crc.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 TX CRC data register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TX_CRC_SPEC;
 impl crate::RegisterSpec for TX_CRC_SPEC {
diff --git a/esp32p4/src/spi1/user.rs b/esp32p4/src/spi1/user.rs
index 66260b25e0..c53de90555 100644
--- a/esp32p4/src/spi1/user.rs
+++ b/esp32p4/src/spi1/user.rs
@@ -125,37 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
-            .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
-            .field("fwrite_dio", &format_args!("{}", self.fwrite_dio().bit()))
-            .field("fwrite_qio", &format_args!("{}", self.fwrite_qio().bit()))
-            .field(
-                "usr_miso_highpart",
-                &format_args!("{}", self.usr_miso_highpart().bit()),
-            )
-            .field(
-                "usr_mosi_highpart",
-                &format_args!("{}", self.usr_mosi_highpart().bit()),
-            )
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
-            .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
-            .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
-            .field("usr_command", &format_args!("{}", self.usr_command().bit()))
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("fwrite_dual", &self.fwrite_dual())
+            .field("fwrite_quad", &self.fwrite_quad())
+            .field("fwrite_dio", &self.fwrite_dio())
+            .field("fwrite_qio", &self.fwrite_qio())
+            .field("usr_miso_highpart", &self.usr_miso_highpart())
+            .field("usr_mosi_highpart", &self.usr_mosi_highpart())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_mosi", &self.usr_mosi())
+            .field("usr_miso", &self.usr_miso())
+            .field("usr_dummy", &self.usr_dummy())
+            .field("usr_addr", &self.usr_addr())
+            .field("usr_command", &self.usr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/user1.rs b/esp32p4/src/spi1/user1.rs
index 4b36bbf30d..8f28ca2ba4 100644
--- a/esp32p4/src/spi1/user1.rs
+++ b/esp32p4/src/spi1/user1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/user2.rs b/esp32p4/src/spi1/user2.rs
index 382c76224c..4bd67c802f 100644
--- a/esp32p4/src/spi1/user2.rs
+++ b/esp32p4/src/spi1/user2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command."]
     #[inline(always)]
diff --git a/esp32p4/src/spi1/w.rs b/esp32p4/src/spi1/w.rs
index 319a8e0611..43137019f7 100644
--- a/esp32p4/src/spi1/w.rs
+++ b/esp32p4/src/spi1/w.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("W")
-            .field("buf", &format_args!("{}", self.buf().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<W_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("W").field("buf", &self.buf()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/spi2/addr.rs b/esp32p4/src/spi2/addr.rs
index 0429f136d3..a43f100c19 100644
--- a/esp32p4/src/spi2/addr.rs
+++ b/esp32p4/src/spi2/addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR")
-            .field(
-                "usr_addr_value",
-                &format_args!("{}", self.usr_addr_value().bits()),
-            )
+            .field("usr_addr_value", &self.usr_addr_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Address to slave. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/clk_gate.rs b/esp32p4/src/spi2/clk_gate.rs
index c690702c68..c633026011 100644
--- a/esp32p4/src/spi2/clk_gate.rs
+++ b/esp32p4/src/spi2/clk_gate.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "mst_clk_active",
-                &format_args!("{}", self.mst_clk_active().bit()),
-            )
-            .field("mst_clk_sel", &format_args!("{}", self.mst_clk_sel().bit()))
+            .field("clk_en", &self.clk_en())
+            .field("mst_clk_active", &self.mst_clk_active())
+            .field("mst_clk_sel", &self.mst_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable clk gate"]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/clock.rs b/esp32p4/src/spi2/clock.rs
index a980aa1ac0..336dc15885 100644
--- a/esp32p4/src/spi2/clock.rs
+++ b/esp32p4/src/spi2/clock.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field("clkdiv_pre", &format_args!("{}", self.clkdiv_pre().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clkdiv_pre", &self.clkdiv_pre())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/cmd.rs b/esp32p4/src/spi2/cmd.rs
index bf9381f9d2..a70057794e 100644
--- a/esp32p4/src/spi2/cmd.rs
+++ b/esp32p4/src/spi2/cmd.rs
@@ -28,20 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field(
-                "conf_bitlen",
-                &format_args!("{}", self.conf_bitlen().bits()),
-            )
-            .field("usr", &format_args!("{}", self.usr().bit()))
+            .field("conf_bitlen", &self.conf_bitlen())
+            .field("usr", &self.usr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - Define the APB cycles of SPI_CONF state. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/ctrl.rs b/esp32p4/src/spi2/ctrl.rs
index bc2023770e..7975686bec 100644
--- a/esp32p4/src/spi2/ctrl.rs
+++ b/esp32p4/src/spi2/ctrl.rs
@@ -152,37 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("dummy_out", &format_args!("{}", self.dummy_out().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
-            .field("faddr_oct", &format_args!("{}", self.faddr_oct().bit()))
-            .field("fcmd_dual", &format_args!("{}", self.fcmd_dual().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcmd_oct", &format_args!("{}", self.fcmd_oct().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("fread_oct", &format_args!("{}", self.fread_oct().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("hold_pol", &format_args!("{}", self.hold_pol().bit()))
-            .field("wp_pol", &format_args!("{}", self.wp_pol().bit()))
-            .field(
-                "rd_bit_order",
-                &format_args!("{}", self.rd_bit_order().bits()),
-            )
-            .field(
-                "wr_bit_order",
-                &format_args!("{}", self.wr_bit_order().bits()),
-            )
+            .field("dummy_out", &self.dummy_out())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("faddr_quad", &self.faddr_quad())
+            .field("faddr_oct", &self.faddr_oct())
+            .field("fcmd_dual", &self.fcmd_dual())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcmd_oct", &self.fcmd_oct())
+            .field("fread_dual", &self.fread_dual())
+            .field("fread_quad", &self.fread_quad())
+            .field("fread_oct", &self.fread_oct())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("hold_pol", &self.hold_pol())
+            .field("wp_pol", &self.wp_pol())
+            .field("rd_bit_order", &self.rd_bit_order())
+            .field("wr_bit_order", &self.wr_bit_order())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/date.rs b/esp32p4/src/spi2/date.rs
index b2324c5c74..657dbccdc5 100644
--- a/esp32p4/src/spi2/date.rs
+++ b/esp32p4/src/spi2/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/spi2/din_mode.rs b/esp32p4/src/spi2/din_mode.rs
index 15a342ed62..b9070e3d49 100644
--- a/esp32p4/src/spi2/din_mode.rs
+++ b/esp32p4/src/spi2/din_mode.rs
@@ -89,27 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_MODE")
-            .field("din0_mode", &format_args!("{}", self.din0_mode().bits()))
-            .field("din1_mode", &format_args!("{}", self.din1_mode().bits()))
-            .field("din2_mode", &format_args!("{}", self.din2_mode().bits()))
-            .field("din3_mode", &format_args!("{}", self.din3_mode().bits()))
-            .field("din4_mode", &format_args!("{}", self.din4_mode().bits()))
-            .field("din5_mode", &format_args!("{}", self.din5_mode().bits()))
-            .field("din6_mode", &format_args!("{}", self.din6_mode().bits()))
-            .field("din7_mode", &format_args!("{}", self.din7_mode().bits()))
-            .field(
-                "timing_hclk_active",
-                &format_args!("{}", self.timing_hclk_active().bit()),
-            )
+            .field("din0_mode", &self.din0_mode())
+            .field("din1_mode", &self.din1_mode())
+            .field("din2_mode", &self.din2_mode())
+            .field("din3_mode", &self.din3_mode())
+            .field("din4_mode", &self.din4_mode())
+            .field("din5_mode", &self.din5_mode())
+            .field("din6_mode", &self.din6_mode())
+            .field("din7_mode", &self.din7_mode())
+            .field("timing_hclk_active", &self.timing_hclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/din_num.rs b/esp32p4/src/spi2/din_num.rs
index f79a2dedc3..1b29c8976d 100644
--- a/esp32p4/src/spi2/din_num.rs
+++ b/esp32p4/src/spi2/din_num.rs
@@ -80,23 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_NUM")
-            .field("din0_num", &format_args!("{}", self.din0_num().bits()))
-            .field("din1_num", &format_args!("{}", self.din1_num().bits()))
-            .field("din2_num", &format_args!("{}", self.din2_num().bits()))
-            .field("din3_num", &format_args!("{}", self.din3_num().bits()))
-            .field("din4_num", &format_args!("{}", self.din4_num().bits()))
-            .field("din5_num", &format_args!("{}", self.din5_num().bits()))
-            .field("din6_num", &format_args!("{}", self.din6_num().bits()))
-            .field("din7_num", &format_args!("{}", self.din7_num().bits()))
+            .field("din0_num", &self.din0_num())
+            .field("din1_num", &self.din1_num())
+            .field("din2_num", &self.din2_num())
+            .field("din3_num", &self.din3_num())
+            .field("din4_num", &self.din4_num())
+            .field("din5_num", &self.din5_num())
+            .field("din6_num", &self.din6_num())
+            .field("din7_num", &self.din7_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/dma_conf.rs b/esp32p4/src/spi2/dma_conf.rs
index 2c8ad8198f..573e0e214e 100644
--- a/esp32p4/src/spi2/dma_conf.rs
+++ b/esp32p4/src/spi2/dma_conf.rs
@@ -82,38 +82,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field(
-                "dma_outfifo_empty",
-                &format_args!("{}", self.dma_outfifo_empty().bit()),
-            )
-            .field(
-                "dma_infifo_full",
-                &format_args!("{}", self.dma_infifo_full().bit()),
-            )
-            .field(
-                "dma_slv_seg_trans_en",
-                &format_args!("{}", self.dma_slv_seg_trans_en().bit()),
-            )
-            .field(
-                "slv_rx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_rx_seg_trans_clr_en().bit()),
-            )
-            .field(
-                "slv_tx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_tx_seg_trans_clr_en().bit()),
-            )
-            .field("rx_eof_en", &format_args!("{}", self.rx_eof_en().bit()))
-            .field("dma_rx_ena", &format_args!("{}", self.dma_rx_ena().bit()))
-            .field("dma_tx_ena", &format_args!("{}", self.dma_tx_ena().bit()))
+            .field("dma_outfifo_empty", &self.dma_outfifo_empty())
+            .field("dma_infifo_full", &self.dma_infifo_full())
+            .field("dma_slv_seg_trans_en", &self.dma_slv_seg_trans_en())
+            .field("slv_rx_seg_trans_clr_en", &self.slv_rx_seg_trans_clr_en())
+            .field("slv_tx_seg_trans_clr_en", &self.slv_tx_seg_trans_clr_en())
+            .field("rx_eof_en", &self.rx_eof_en())
+            .field("dma_rx_ena", &self.dma_rx_ena())
+            .field("dma_tx_ena", &self.dma_tx_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/dma_int_ena.rs b/esp32p4/src/spi2/dma_int_ena.rs
index 5a2520a556..57d74d21ae 100644
--- a/esp32p4/src/spi2/dma_int_ena.rs
+++ b/esp32p4/src/spi2/dma_int_ena.rs
@@ -197,69 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ENA")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/dma_int_raw.rs b/esp32p4/src/spi2/dma_int_raw.rs
index 4e27e4ae69..c8e69e9935 100644
--- a/esp32p4/src/spi2/dma_int_raw.rs
+++ b/esp32p4/src/spi2/dma_int_raw.rs
@@ -197,69 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_RAW")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/dma_int_st.rs b/esp32p4/src/spi2/dma_int_st.rs
index 424ec36870..5143fbdd5e 100644
--- a/esp32p4/src/spi2/dma_int_st.rs
+++ b/esp32p4/src/spi2/dma_int_st.rs
@@ -153,69 +153,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ST")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_INT_ST_SPEC;
 impl crate::RegisterSpec for DMA_INT_ST_SPEC {
diff --git a/esp32p4/src/spi2/dout_mode.rs b/esp32p4/src/spi2/dout_mode.rs
index c782d95f30..5327365c02 100644
--- a/esp32p4/src/spi2/dout_mode.rs
+++ b/esp32p4/src/spi2/dout_mode.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOUT_MODE")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bit()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bit()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bit()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bit()))
-            .field("dout4_mode", &format_args!("{}", self.dout4_mode().bit()))
-            .field("dout5_mode", &format_args!("{}", self.dout5_mode().bit()))
-            .field("dout6_mode", &format_args!("{}", self.dout6_mode().bit()))
-            .field("dout7_mode", &format_args!("{}", self.dout7_mode().bit()))
-            .field("d_dqs_mode", &format_args!("{}", self.d_dqs_mode().bit()))
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
+            .field("dout4_mode", &self.dout4_mode())
+            .field("dout5_mode", &self.dout5_mode())
+            .field("dout6_mode", &self.dout6_mode())
+            .field("dout7_mode", &self.dout7_mode())
+            .field("d_dqs_mode", &self.d_dqs_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/misc.rs b/esp32p4/src/spi2/misc.rs
index acf949453f..21c438c62e 100644
--- a/esp32p4/src/spi2/misc.rs
+++ b/esp32p4/src/spi2/misc.rs
@@ -161,53 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
-            .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
-            .field("cs2_dis", &format_args!("{}", self.cs2_dis().bit()))
-            .field("cs3_dis", &format_args!("{}", self.cs3_dis().bit()))
-            .field("cs4_dis", &format_args!("{}", self.cs4_dis().bit()))
-            .field("cs5_dis", &format_args!("{}", self.cs5_dis().bit()))
-            .field("ck_dis", &format_args!("{}", self.ck_dis().bit()))
-            .field(
-                "master_cs_pol",
-                &format_args!("{}", self.master_cs_pol().bits()),
-            )
-            .field(
-                "clk_data_dtr_en",
-                &format_args!("{}", self.clk_data_dtr_en().bit()),
-            )
-            .field("data_dtr_en", &format_args!("{}", self.data_dtr_en().bit()))
-            .field("addr_dtr_en", &format_args!("{}", self.addr_dtr_en().bit()))
-            .field("cmd_dtr_en", &format_args!("{}", self.cmd_dtr_en().bit()))
-            .field(
-                "slave_cs_pol",
-                &format_args!("{}", self.slave_cs_pol().bit()),
-            )
-            .field(
-                "dqs_idle_edge",
-                &format_args!("{}", self.dqs_idle_edge().bit()),
-            )
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
-            .field(
-                "quad_din_pin_swap",
-                &format_args!("{}", self.quad_din_pin_swap().bit()),
-            )
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("cs2_dis", &self.cs2_dis())
+            .field("cs3_dis", &self.cs3_dis())
+            .field("cs4_dis", &self.cs4_dis())
+            .field("cs5_dis", &self.cs5_dis())
+            .field("ck_dis", &self.ck_dis())
+            .field("master_cs_pol", &self.master_cs_pol())
+            .field("clk_data_dtr_en", &self.clk_data_dtr_en())
+            .field("data_dtr_en", &self.data_dtr_en())
+            .field("addr_dtr_en", &self.addr_dtr_en())
+            .field("cmd_dtr_en", &self.cmd_dtr_en())
+            .field("slave_cs_pol", &self.slave_cs_pol())
+            .field("dqs_idle_edge", &self.dqs_idle_edge())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
+            .field("quad_din_pin_swap", &self.quad_din_pin_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/ms_dlen.rs b/esp32p4/src/spi2/ms_dlen.rs
index 116939582c..94a2915785 100644
--- a/esp32p4/src/spi2/ms_dlen.rs
+++ b/esp32p4/src/spi2/ms_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MS_DLEN")
-            .field(
-                "ms_data_bitlen",
-                &format_args!("{}", self.ms_data_bitlen().bits()),
-            )
+            .field("ms_data_bitlen", &self.ms_data_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MS_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/slave.rs b/esp32p4/src/spi2/slave.rs
index 8418191863..734a54db41 100644
--- a/esp32p4/src/spi2/slave.rs
+++ b/esp32p4/src/spi2/slave.rs
@@ -116,51 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
-            .field("clk_mode_13", &format_args!("{}", self.clk_mode_13().bit()))
-            .field(
-                "rsck_data_out",
-                &format_args!("{}", self.rsck_data_out().bit()),
-            )
-            .field(
-                "slv_rddma_bitlen_en",
-                &format_args!("{}", self.slv_rddma_bitlen_en().bit()),
-            )
-            .field(
-                "slv_wrdma_bitlen_en",
-                &format_args!("{}", self.slv_wrdma_bitlen_en().bit()),
-            )
-            .field(
-                "slv_rdbuf_bitlen_en",
-                &format_args!("{}", self.slv_rdbuf_bitlen_en().bit()),
-            )
-            .field(
-                "slv_wrbuf_bitlen_en",
-                &format_args!("{}", self.slv_wrbuf_bitlen_en().bit()),
-            )
-            .field(
-                "slv_last_byte_strb",
-                &format_args!("{}", self.slv_last_byte_strb().bits()),
-            )
-            .field(
-                "dma_seg_magic_value",
-                &format_args!("{}", self.dma_seg_magic_value().bits()),
-            )
-            .field("mode", &format_args!("{}", self.mode().bit()))
-            .field("usr_conf", &format_args!("{}", self.usr_conf().bit()))
-            .field(
-                "mst_fd_wait_dma_tx_data",
-                &format_args!("{}", self.mst_fd_wait_dma_tx_data().bit()),
-            )
+            .field("clk_mode", &self.clk_mode())
+            .field("clk_mode_13", &self.clk_mode_13())
+            .field("rsck_data_out", &self.rsck_data_out())
+            .field("slv_rddma_bitlen_en", &self.slv_rddma_bitlen_en())
+            .field("slv_wrdma_bitlen_en", &self.slv_wrdma_bitlen_en())
+            .field("slv_rdbuf_bitlen_en", &self.slv_rdbuf_bitlen_en())
+            .field("slv_wrbuf_bitlen_en", &self.slv_wrbuf_bitlen_en())
+            .field("slv_last_byte_strb", &self.slv_last_byte_strb())
+            .field("dma_seg_magic_value", &self.dma_seg_magic_value())
+            .field("mode", &self.mode())
+            .field("usr_conf", &self.usr_conf())
+            .field("mst_fd_wait_dma_tx_data", &self.mst_fd_wait_dma_tx_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/slave1.rs b/esp32p4/src/spi2/slave1.rs
index 7e216d9f86..98ad1b4b32 100644
--- a/esp32p4/src/spi2/slave1.rs
+++ b/esp32p4/src/spi2/slave1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE1")
-            .field(
-                "slv_data_bitlen",
-                &format_args!("{}", self.slv_data_bitlen().bits()),
-            )
-            .field(
-                "slv_last_command",
-                &format_args!("{}", self.slv_last_command().bits()),
-            )
-            .field(
-                "slv_last_addr",
-                &format_args!("{}", self.slv_last_addr().bits()),
-            )
+            .field("slv_data_bitlen", &self.slv_data_bitlen())
+            .field("slv_last_command", &self.slv_last_command())
+            .field("slv_last_addr", &self.slv_last_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - The transferred data bit length in SPI slave FD and HD mode."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/user.rs b/esp32p4/src/spi2/user.rs
index 60d58c5ede..10fdfadeba 100644
--- a/esp32p4/src/spi2/user.rs
+++ b/esp32p4/src/spi2/user.rs
@@ -197,48 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("doutdin", &format_args!("{}", self.doutdin().bit()))
-            .field("qpi_mode", &format_args!("{}", self.qpi_mode().bit()))
-            .field("opi_mode", &format_args!("{}", self.opi_mode().bit()))
-            .field("tsck_i_edge", &format_args!("{}", self.tsck_i_edge().bit()))
-            .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
-            .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
-            .field("rsck_i_edge", &format_args!("{}", self.rsck_i_edge().bit()))
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
-            .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
-            .field("fwrite_oct", &format_args!("{}", self.fwrite_oct().bit()))
-            .field(
-                "usr_conf_nxt",
-                &format_args!("{}", self.usr_conf_nxt().bit()),
-            )
-            .field("sio", &format_args!("{}", self.sio().bit()))
-            .field(
-                "usr_miso_highpart",
-                &format_args!("{}", self.usr_miso_highpart().bit()),
-            )
-            .field(
-                "usr_mosi_highpart",
-                &format_args!("{}", self.usr_mosi_highpart().bit()),
-            )
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
-            .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
-            .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
-            .field("usr_command", &format_args!("{}", self.usr_command().bit()))
+            .field("doutdin", &self.doutdin())
+            .field("qpi_mode", &self.qpi_mode())
+            .field("opi_mode", &self.opi_mode())
+            .field("tsck_i_edge", &self.tsck_i_edge())
+            .field("cs_hold", &self.cs_hold())
+            .field("cs_setup", &self.cs_setup())
+            .field("rsck_i_edge", &self.rsck_i_edge())
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("fwrite_dual", &self.fwrite_dual())
+            .field("fwrite_quad", &self.fwrite_quad())
+            .field("fwrite_oct", &self.fwrite_oct())
+            .field("usr_conf_nxt", &self.usr_conf_nxt())
+            .field("sio", &self.sio())
+            .field("usr_miso_highpart", &self.usr_miso_highpart())
+            .field("usr_mosi_highpart", &self.usr_mosi_highpart())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_mosi", &self.usr_mosi())
+            .field("usr_miso", &self.usr_miso())
+            .field("usr_dummy", &self.usr_dummy())
+            .field("usr_addr", &self.usr_addr())
+            .field("usr_command", &self.usr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/user1.rs b/esp32p4/src/spi2/user1.rs
index acb564ca07..1dd612d409 100644
--- a/esp32p4/src/spi2/user1.rs
+++ b/esp32p4/src/spi2/user1.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "mst_wfull_err_end_en",
-                &format_args!("{}", self.mst_wfull_err_end_en().bit()),
-            )
-            .field(
-                "cs_setup_time",
-                &format_args!("{}", self.cs_setup_time().bits()),
-            )
-            .field(
-                "cs_hold_time",
-                &format_args!("{}", self.cs_hold_time().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("mst_wfull_err_end_en", &self.mst_wfull_err_end_en())
+            .field("cs_setup_time", &self.cs_setup_time())
+            .field("cs_hold_time", &self.cs_hold_time())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/user2.rs b/esp32p4/src/spi2/user2.rs
index 065c536363..c2d5092cd2 100644
--- a/esp32p4/src/spi2/user2.rs
+++ b/esp32p4/src/spi2/user2.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "mst_rempty_err_end_en",
-                &format_args!("{}", self.mst_rempty_err_end_en().bit()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("mst_rempty_err_end_en", &self.mst_rempty_err_end_en())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi2/w.rs b/esp32p4/src/spi2/w.rs
index bd1588a6f2..016fb59d7c 100644
--- a/esp32p4/src/spi2/w.rs
+++ b/esp32p4/src/spi2/w.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("W")
-            .field("buf", &format_args!("{}", self.buf().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<W_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("W").field("buf", &self.buf()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/spi3/addr.rs b/esp32p4/src/spi3/addr.rs
index 0429f136d3..a43f100c19 100644
--- a/esp32p4/src/spi3/addr.rs
+++ b/esp32p4/src/spi3/addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR")
-            .field(
-                "usr_addr_value",
-                &format_args!("{}", self.usr_addr_value().bits()),
-            )
+            .field("usr_addr_value", &self.usr_addr_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Address to slave. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/clk_gate.rs b/esp32p4/src/spi3/clk_gate.rs
index c690702c68..c633026011 100644
--- a/esp32p4/src/spi3/clk_gate.rs
+++ b/esp32p4/src/spi3/clk_gate.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "mst_clk_active",
-                &format_args!("{}", self.mst_clk_active().bit()),
-            )
-            .field("mst_clk_sel", &format_args!("{}", self.mst_clk_sel().bit()))
+            .field("clk_en", &self.clk_en())
+            .field("mst_clk_active", &self.mst_clk_active())
+            .field("mst_clk_sel", &self.mst_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable clk gate"]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/clock.rs b/esp32p4/src/spi3/clock.rs
index a980aa1ac0..336dc15885 100644
--- a/esp32p4/src/spi3/clock.rs
+++ b/esp32p4/src/spi3/clock.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field("clkdiv_pre", &format_args!("{}", self.clkdiv_pre().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clkdiv_pre", &self.clkdiv_pre())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/cmd.rs b/esp32p4/src/spi3/cmd.rs
index 23a57fa581..90d2001365 100644
--- a/esp32p4/src/spi3/cmd.rs
+++ b/esp32p4/src/spi3/cmd.rs
@@ -18,15 +18,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CMD")
-            .field("usr", &format_args!("{}", self.usr().bit()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CMD").field("usr", &self.usr()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/spi3/ctrl.rs b/esp32p4/src/spi3/ctrl.rs
index 19072ec644..bec3faa8cb 100644
--- a/esp32p4/src/spi3/ctrl.rs
+++ b/esp32p4/src/spi3/ctrl.rs
@@ -125,34 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("dummy_out", &format_args!("{}", self.dummy_out().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
-            .field("fcmd_dual", &format_args!("{}", self.fcmd_dual().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("hold_pol", &format_args!("{}", self.hold_pol().bit()))
-            .field("wp_pol", &format_args!("{}", self.wp_pol().bit()))
-            .field(
-                "rd_bit_order",
-                &format_args!("{}", self.rd_bit_order().bits()),
-            )
-            .field(
-                "wr_bit_order",
-                &format_args!("{}", self.wr_bit_order().bits()),
-            )
+            .field("dummy_out", &self.dummy_out())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("faddr_quad", &self.faddr_quad())
+            .field("fcmd_dual", &self.fcmd_dual())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fread_dual", &self.fread_dual())
+            .field("fread_quad", &self.fread_quad())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("hold_pol", &self.hold_pol())
+            .field("wp_pol", &self.wp_pol())
+            .field("rd_bit_order", &self.rd_bit_order())
+            .field("wr_bit_order", &self.wr_bit_order())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/date.rs b/esp32p4/src/spi3/date.rs
index b2324c5c74..657dbccdc5 100644
--- a/esp32p4/src/spi3/date.rs
+++ b/esp32p4/src/spi3/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/spi3/din_mode.rs b/esp32p4/src/spi3/din_mode.rs
index 02ecb02d51..1f85bb8c0b 100644
--- a/esp32p4/src/spi3/din_mode.rs
+++ b/esp32p4/src/spi3/din_mode.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_MODE")
-            .field("din0_mode", &format_args!("{}", self.din0_mode().bits()))
-            .field("din1_mode", &format_args!("{}", self.din1_mode().bits()))
-            .field("din2_mode", &format_args!("{}", self.din2_mode().bits()))
-            .field("din3_mode", &format_args!("{}", self.din3_mode().bits()))
-            .field(
-                "timing_hclk_active",
-                &format_args!("{}", self.timing_hclk_active().bit()),
-            )
+            .field("din0_mode", &self.din0_mode())
+            .field("din1_mode", &self.din1_mode())
+            .field("din2_mode", &self.din2_mode())
+            .field("din3_mode", &self.din3_mode())
+            .field("timing_hclk_active", &self.timing_hclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/din_num.rs b/esp32p4/src/spi3/din_num.rs
index 102655776e..3fd2574245 100644
--- a/esp32p4/src/spi3/din_num.rs
+++ b/esp32p4/src/spi3/din_num.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_NUM")
-            .field("din0_num", &format_args!("{}", self.din0_num().bits()))
-            .field("din1_num", &format_args!("{}", self.din1_num().bits()))
-            .field("din2_num", &format_args!("{}", self.din2_num().bits()))
-            .field("din3_num", &format_args!("{}", self.din3_num().bits()))
+            .field("din0_num", &self.din0_num())
+            .field("din1_num", &self.din1_num())
+            .field("din2_num", &self.din2_num())
+            .field("din3_num", &self.din3_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/dma_conf.rs b/esp32p4/src/spi3/dma_conf.rs
index 2c8ad8198f..573e0e214e 100644
--- a/esp32p4/src/spi3/dma_conf.rs
+++ b/esp32p4/src/spi3/dma_conf.rs
@@ -82,38 +82,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field(
-                "dma_outfifo_empty",
-                &format_args!("{}", self.dma_outfifo_empty().bit()),
-            )
-            .field(
-                "dma_infifo_full",
-                &format_args!("{}", self.dma_infifo_full().bit()),
-            )
-            .field(
-                "dma_slv_seg_trans_en",
-                &format_args!("{}", self.dma_slv_seg_trans_en().bit()),
-            )
-            .field(
-                "slv_rx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_rx_seg_trans_clr_en().bit()),
-            )
-            .field(
-                "slv_tx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_tx_seg_trans_clr_en().bit()),
-            )
-            .field("rx_eof_en", &format_args!("{}", self.rx_eof_en().bit()))
-            .field("dma_rx_ena", &format_args!("{}", self.dma_rx_ena().bit()))
-            .field("dma_tx_ena", &format_args!("{}", self.dma_tx_ena().bit()))
+            .field("dma_outfifo_empty", &self.dma_outfifo_empty())
+            .field("dma_infifo_full", &self.dma_infifo_full())
+            .field("dma_slv_seg_trans_en", &self.dma_slv_seg_trans_en())
+            .field("slv_rx_seg_trans_clr_en", &self.slv_rx_seg_trans_clr_en())
+            .field("slv_tx_seg_trans_clr_en", &self.slv_tx_seg_trans_clr_en())
+            .field("rx_eof_en", &self.rx_eof_en())
+            .field("dma_rx_ena", &self.dma_rx_ena())
+            .field("dma_tx_ena", &self.dma_tx_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/dma_int_ena.rs b/esp32p4/src/spi3/dma_int_ena.rs
index a266a35c5f..8f9148350d 100644
--- a/esp32p4/src/spi3/dma_int_ena.rs
+++ b/esp32p4/src/spi3/dma_int_ena.rs
@@ -188,65 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ENA")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/dma_int_raw.rs b/esp32p4/src/spi3/dma_int_raw.rs
index 15053eee2d..3f3dcc2d44 100644
--- a/esp32p4/src/spi3/dma_int_raw.rs
+++ b/esp32p4/src/spi3/dma_int_raw.rs
@@ -188,65 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_RAW")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/dma_int_st.rs b/esp32p4/src/spi3/dma_int_st.rs
index e1f1d2e606..aa60060122 100644
--- a/esp32p4/src/spi3/dma_int_st.rs
+++ b/esp32p4/src/spi3/dma_int_st.rs
@@ -146,65 +146,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ST")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_INT_ST_SPEC;
 impl crate::RegisterSpec for DMA_INT_ST_SPEC {
diff --git a/esp32p4/src/spi3/dout_mode.rs b/esp32p4/src/spi3/dout_mode.rs
index 7acc1b2deb..8a10dbd9fd 100644
--- a/esp32p4/src/spi3/dout_mode.rs
+++ b/esp32p4/src/spi3/dout_mode.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOUT_MODE")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bit()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bit()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bit()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bit()))
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/misc.rs b/esp32p4/src/spi3/misc.rs
index a40344f8fc..f314394f89 100644
--- a/esp32p4/src/spi3/misc.rs
+++ b/esp32p4/src/spi3/misc.rs
@@ -89,39 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
-            .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
-            .field("cs2_dis", &format_args!("{}", self.cs2_dis().bit()))
-            .field("ck_dis", &format_args!("{}", self.ck_dis().bit()))
-            .field(
-                "master_cs_pol",
-                &format_args!("{}", self.master_cs_pol().bits()),
-            )
-            .field(
-                "slave_cs_pol",
-                &format_args!("{}", self.slave_cs_pol().bit()),
-            )
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
-            .field(
-                "quad_din_pin_swap",
-                &format_args!("{}", self.quad_din_pin_swap().bit()),
-            )
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("cs2_dis", &self.cs2_dis())
+            .field("ck_dis", &self.ck_dis())
+            .field("master_cs_pol", &self.master_cs_pol())
+            .field("slave_cs_pol", &self.slave_cs_pol())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
+            .field("quad_din_pin_swap", &self.quad_din_pin_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/ms_dlen.rs b/esp32p4/src/spi3/ms_dlen.rs
index 116939582c..94a2915785 100644
--- a/esp32p4/src/spi3/ms_dlen.rs
+++ b/esp32p4/src/spi3/ms_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MS_DLEN")
-            .field(
-                "ms_data_bitlen",
-                &format_args!("{}", self.ms_data_bitlen().bits()),
-            )
+            .field("ms_data_bitlen", &self.ms_data_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MS_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/slave.rs b/esp32p4/src/spi3/slave.rs
index bfc54939b1..00753f31b0 100644
--- a/esp32p4/src/spi3/slave.rs
+++ b/esp32p4/src/spi3/slave.rs
@@ -98,46 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
-            .field("clk_mode_13", &format_args!("{}", self.clk_mode_13().bit()))
-            .field(
-                "rsck_data_out",
-                &format_args!("{}", self.rsck_data_out().bit()),
-            )
-            .field(
-                "slv_rddma_bitlen_en",
-                &format_args!("{}", self.slv_rddma_bitlen_en().bit()),
-            )
-            .field(
-                "slv_wrdma_bitlen_en",
-                &format_args!("{}", self.slv_wrdma_bitlen_en().bit()),
-            )
-            .field(
-                "slv_rdbuf_bitlen_en",
-                &format_args!("{}", self.slv_rdbuf_bitlen_en().bit()),
-            )
-            .field(
-                "slv_wrbuf_bitlen_en",
-                &format_args!("{}", self.slv_wrbuf_bitlen_en().bit()),
-            )
-            .field(
-                "slv_last_byte_strb",
-                &format_args!("{}", self.slv_last_byte_strb().bits()),
-            )
-            .field("mode", &format_args!("{}", self.mode().bit()))
-            .field(
-                "mst_fd_wait_dma_tx_data",
-                &format_args!("{}", self.mst_fd_wait_dma_tx_data().bit()),
-            )
+            .field("clk_mode", &self.clk_mode())
+            .field("clk_mode_13", &self.clk_mode_13())
+            .field("rsck_data_out", &self.rsck_data_out())
+            .field("slv_rddma_bitlen_en", &self.slv_rddma_bitlen_en())
+            .field("slv_wrdma_bitlen_en", &self.slv_wrdma_bitlen_en())
+            .field("slv_rdbuf_bitlen_en", &self.slv_rdbuf_bitlen_en())
+            .field("slv_wrbuf_bitlen_en", &self.slv_wrbuf_bitlen_en())
+            .field("slv_last_byte_strb", &self.slv_last_byte_strb())
+            .field("mode", &self.mode())
+            .field("mst_fd_wait_dma_tx_data", &self.mst_fd_wait_dma_tx_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/slave1.rs b/esp32p4/src/spi3/slave1.rs
index 7e216d9f86..98ad1b4b32 100644
--- a/esp32p4/src/spi3/slave1.rs
+++ b/esp32p4/src/spi3/slave1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE1")
-            .field(
-                "slv_data_bitlen",
-                &format_args!("{}", self.slv_data_bitlen().bits()),
-            )
-            .field(
-                "slv_last_command",
-                &format_args!("{}", self.slv_last_command().bits()),
-            )
-            .field(
-                "slv_last_addr",
-                &format_args!("{}", self.slv_last_addr().bits()),
-            )
+            .field("slv_data_bitlen", &self.slv_data_bitlen())
+            .field("slv_last_command", &self.slv_last_command())
+            .field("slv_last_addr", &self.slv_last_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - The transferred data bit length in SPI slave FD and HD mode."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/user.rs b/esp32p4/src/spi3/user.rs
index 1c6f4bc5a0..2b17cd7a6c 100644
--- a/esp32p4/src/spi3/user.rs
+++ b/esp32p4/src/spi3/user.rs
@@ -170,42 +170,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("doutdin", &format_args!("{}", self.doutdin().bit()))
-            .field("qpi_mode", &format_args!("{}", self.qpi_mode().bit()))
-            .field("tsck_i_edge", &format_args!("{}", self.tsck_i_edge().bit()))
-            .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
-            .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
-            .field("rsck_i_edge", &format_args!("{}", self.rsck_i_edge().bit()))
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
-            .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
-            .field("sio", &format_args!("{}", self.sio().bit()))
-            .field(
-                "usr_miso_highpart",
-                &format_args!("{}", self.usr_miso_highpart().bit()),
-            )
-            .field(
-                "usr_mosi_highpart",
-                &format_args!("{}", self.usr_mosi_highpart().bit()),
-            )
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
-            .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
-            .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
-            .field("usr_command", &format_args!("{}", self.usr_command().bit()))
+            .field("doutdin", &self.doutdin())
+            .field("qpi_mode", &self.qpi_mode())
+            .field("tsck_i_edge", &self.tsck_i_edge())
+            .field("cs_hold", &self.cs_hold())
+            .field("cs_setup", &self.cs_setup())
+            .field("rsck_i_edge", &self.rsck_i_edge())
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("fwrite_dual", &self.fwrite_dual())
+            .field("fwrite_quad", &self.fwrite_quad())
+            .field("sio", &self.sio())
+            .field("usr_miso_highpart", &self.usr_miso_highpart())
+            .field("usr_mosi_highpart", &self.usr_mosi_highpart())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_mosi", &self.usr_mosi())
+            .field("usr_miso", &self.usr_miso())
+            .field("usr_dummy", &self.usr_dummy())
+            .field("usr_addr", &self.usr_addr())
+            .field("usr_command", &self.usr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/user1.rs b/esp32p4/src/spi3/user1.rs
index acb564ca07..1dd612d409 100644
--- a/esp32p4/src/spi3/user1.rs
+++ b/esp32p4/src/spi3/user1.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "mst_wfull_err_end_en",
-                &format_args!("{}", self.mst_wfull_err_end_en().bit()),
-            )
-            .field(
-                "cs_setup_time",
-                &format_args!("{}", self.cs_setup_time().bits()),
-            )
-            .field(
-                "cs_hold_time",
-                &format_args!("{}", self.cs_hold_time().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("mst_wfull_err_end_en", &self.mst_wfull_err_end_en())
+            .field("cs_setup_time", &self.cs_setup_time())
+            .field("cs_hold_time", &self.cs_hold_time())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/user2.rs b/esp32p4/src/spi3/user2.rs
index 065c536363..c2d5092cd2 100644
--- a/esp32p4/src/spi3/user2.rs
+++ b/esp32p4/src/spi3/user2.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "mst_rempty_err_end_en",
-                &format_args!("{}", self.mst_rempty_err_end_en().bit()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("mst_rempty_err_end_en", &self.mst_rempty_err_end_en())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32p4/src/spi3/w.rs b/esp32p4/src/spi3/w.rs
index bd1588a6f2..016fb59d7c 100644
--- a/esp32p4/src/spi3/w.rs
+++ b/esp32p4/src/spi3/w.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("W")
-            .field("buf", &format_args!("{}", self.buf().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<W_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("W").field("buf", &self.buf()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/systimer/conf.rs b/esp32p4/src/systimer/conf.rs
index dc9795ba23..8824e41e55 100644
--- a/esp32p4/src/systimer/conf.rs
+++ b/esp32p4/src/systimer/conf.rs
@@ -116,57 +116,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field(
-                "systimer_clk_fo",
-                &format_args!("{}", self.systimer_clk_fo().bit()),
-            )
-            .field("etm_en", &format_args!("{}", self.etm_en().bit()))
-            .field(
-                "target2_work_en",
-                &format_args!("{}", self.target2_work_en().bit()),
-            )
-            .field(
-                "target1_work_en",
-                &format_args!("{}", self.target1_work_en().bit()),
-            )
-            .field(
-                "target0_work_en",
-                &format_args!("{}", self.target0_work_en().bit()),
-            )
+            .field("systimer_clk_fo", &self.systimer_clk_fo())
+            .field("etm_en", &self.etm_en())
+            .field("target2_work_en", &self.target2_work_en())
+            .field("target1_work_en", &self.target1_work_en())
+            .field("target0_work_en", &self.target0_work_en())
             .field(
                 "timer_unit1_core1_stall_en",
-                &format_args!("{}", self.timer_unit1_core1_stall_en().bit()),
+                &self.timer_unit1_core1_stall_en(),
             )
             .field(
                 "timer_unit1_core0_stall_en",
-                &format_args!("{}", self.timer_unit1_core0_stall_en().bit()),
+                &self.timer_unit1_core0_stall_en(),
             )
             .field(
                 "timer_unit0_core1_stall_en",
-                &format_args!("{}", self.timer_unit0_core1_stall_en().bit()),
+                &self.timer_unit0_core1_stall_en(),
             )
             .field(
                 "timer_unit0_core0_stall_en",
-                &format_args!("{}", self.timer_unit0_core0_stall_en().bit()),
+                &self.timer_unit0_core0_stall_en(),
             )
-            .field(
-                "timer_unit1_work_en",
-                &format_args!("{}", self.timer_unit1_work_en().bit()),
-            )
-            .field(
-                "timer_unit0_work_en",
-                &format_args!("{}", self.timer_unit0_work_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("timer_unit1_work_en", &self.timer_unit1_work_en())
+            .field("timer_unit0_work_en", &self.timer_unit0_work_en())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - systimer clock force on"]
     #[inline(always)]
diff --git a/esp32p4/src/systimer/date.rs b/esp32p4/src/systimer/date.rs
index 9e89ffaebb..629d8212a8 100644
--- a/esp32p4/src/systimer/date.rs
+++ b/esp32p4/src/systimer/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/systimer/int_ena.rs b/esp32p4/src/systimer/int_ena.rs
index 9afbd67324..bf39753584 100644
--- a/esp32p4/src/systimer/int_ena.rs
+++ b/esp32p4/src/systimer/int_ena.rs
@@ -42,18 +42,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "interupt(0-2) enable"]
     #[doc = ""]
diff --git a/esp32p4/src/systimer/int_raw.rs b/esp32p4/src/systimer/int_raw.rs
index 9487c30025..395cb8187f 100644
--- a/esp32p4/src/systimer/int_raw.rs
+++ b/esp32p4/src/systimer/int_raw.rs
@@ -42,18 +42,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "interupt(0-2) raw"]
     #[doc = ""]
diff --git a/esp32p4/src/systimer/int_st.rs b/esp32p4/src/systimer/int_st.rs
index 4c4d3c12f8..1dc503012b 100644
--- a/esp32p4/src/systimer/int_st.rs
+++ b/esp32p4/src/systimer/int_st.rs
@@ -38,18 +38,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "systimer interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/systimer/real_target/hi.rs b/esp32p4/src/systimer/real_target/hi.rs
index e37661f89a..10d4966ea0 100644
--- a/esp32p4/src/systimer/real_target/hi.rs
+++ b/esp32p4/src/systimer/real_target/hi.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi_ro", &format_args!("{}", self.hi_ro().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi_ro", &self.hi_ro()).finish()
     }
 }
 #[doc = "system timer comp0 actual target value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32p4/src/systimer/real_target/lo.rs b/esp32p4/src/systimer/real_target/lo.rs
index 6ba16447eb..2a8623e63b 100644
--- a/esp32p4/src/systimer/real_target/lo.rs
+++ b/esp32p4/src/systimer/real_target/lo.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo_ro", &format_args!("{}", self.lo_ro().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo_ro", &self.lo_ro()).finish()
     }
 }
 #[doc = "system timer comp0 actual target value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32p4/src/systimer/target_conf.rs b/esp32p4/src/systimer/target_conf.rs
index 351218e2ba..48184bd1f3 100644
--- a/esp32p4/src/systimer/target_conf.rs
+++ b/esp32p4/src/systimer/target_conf.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TARGET_CONF")
-            .field("period", &format_args!("{}", self.period().bits()))
-            .field("period_mode", &format_args!("{}", self.period_mode().bit()))
-            .field(
-                "timer_unit_sel",
-                &format_args!("{}", self.timer_unit_sel().bit()),
-            )
+            .field("period", &self.period())
+            .field("period_mode", &self.period_mode())
+            .field("timer_unit_sel", &self.timer_unit_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TARGET_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - target0 period"]
     #[inline(always)]
diff --git a/esp32p4/src/systimer/trgt/hi.rs b/esp32p4/src/systimer/trgt/hi.rs
index 9ba19aedd7..1bbcc8532f 100644
--- a/esp32p4/src/systimer/trgt/hi.rs
+++ b/esp32p4/src/systimer/trgt/hi.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/systimer/trgt/lo.rs b/esp32p4/src/systimer/trgt/lo.rs
index cf5618b115..870fcb7923 100644
--- a/esp32p4/src/systimer/trgt/lo.rs
+++ b/esp32p4/src/systimer/trgt/lo.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/systimer/unit_op.rs b/esp32p4/src/systimer/unit_op.rs
index 161504c169..5a004338a8 100644
--- a/esp32p4/src/systimer/unit_op.rs
+++ b/esp32p4/src/systimer/unit_op.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UNIT_OP")
-            .field("value_valid", &format_args!("{}", self.value_valid().bit()))
+            .field("value_valid", &self.value_valid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UNIT_OP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - update timer_unit0"]
     #[inline(always)]
diff --git a/esp32p4/src/systimer/unit_value/hi.rs b/esp32p4/src/systimer/unit_value/hi.rs
index 3cd25b4d55..10523f249f 100644
--- a/esp32p4/src/systimer/unit_value/hi.rs
+++ b/esp32p4/src/systimer/unit_value/hi.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HI")
-            .field("value_hi", &format_args!("{}", self.value_hi().bits()))
+            .field("value_hi", &self.value_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "system timer unit0 value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HI_SPEC;
 impl crate::RegisterSpec for HI_SPEC {
diff --git a/esp32p4/src/systimer/unit_value/lo.rs b/esp32p4/src/systimer/unit_value/lo.rs
index a60743963d..92c3f4e991 100644
--- a/esp32p4/src/systimer/unit_value/lo.rs
+++ b/esp32p4/src/systimer/unit_value/lo.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LO")
-            .field("value_lo", &format_args!("{}", self.value_lo().bits()))
+            .field("value_lo", &self.value_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "system timer unit0 value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LO_SPEC;
 impl crate::RegisterSpec for LO_SPEC {
diff --git a/esp32p4/src/systimer/unitload/hi.rs b/esp32p4/src/systimer/unitload/hi.rs
index 3d663b8225..a758293265 100644
--- a/esp32p4/src/systimer/unitload/hi.rs
+++ b/esp32p4/src/systimer/unitload/hi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - timer unit0 load high 20 bits"]
     #[inline(always)]
diff --git a/esp32p4/src/systimer/unitload/lo.rs b/esp32p4/src/systimer/unitload/lo.rs
index 15e267cf3c..e01c2efb83 100644
--- a/esp32p4/src/systimer/unitload/lo.rs
+++ b/esp32p4/src/systimer/unitload/lo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - timer unit0 load low 32 bits"]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/int_ena_timers.rs b/esp32p4/src/timg0/int_ena_timers.rs
index d45fb94a17..0f0f5e347b 100644
--- a/esp32p4/src/timg0/int_ena_timers.rs
+++ b/esp32p4/src/timg0/int_ena_timers.rs
@@ -46,18 +46,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("t1", &format_args!("{}", self.t1().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("t1", &self.t1())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the TIMG_T(0-1)_INT interrupt."]
     #[doc = ""]
diff --git a/esp32p4/src/timg0/int_raw_timers.rs b/esp32p4/src/timg0/int_raw_timers.rs
index bdbd336c28..cf4fba0beb 100644
--- a/esp32p4/src/timg0/int_raw_timers.rs
+++ b/esp32p4/src/timg0/int_raw_timers.rs
@@ -40,18 +40,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("t1", &format_args!("{}", self.t1().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("t1", &self.t1())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_TIMERS_SPEC;
 impl crate::RegisterSpec for INT_RAW_TIMERS_SPEC {
diff --git a/esp32p4/src/timg0/int_st_timers.rs b/esp32p4/src/timg0/int_st_timers.rs
index 9d4210fb3f..48776fe635 100644
--- a/esp32p4/src/timg0/int_st_timers.rs
+++ b/esp32p4/src/timg0/int_st_timers.rs
@@ -40,18 +40,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("t1", &format_args!("{}", self.t1().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("t1", &self.t1())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_TIMERS_SPEC;
 impl crate::RegisterSpec for INT_ST_TIMERS_SPEC {
diff --git a/esp32p4/src/timg0/ntimers_date.rs b/esp32p4/src/timg0/ntimers_date.rs
index 475c8c345e..1660961589 100644
--- a/esp32p4/src/timg0/ntimers_date.rs
+++ b/esp32p4/src/timg0/ntimers_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NTIMERS_DATE")
-            .field(
-                "ntimgs_date",
-                &format_args!("{}", self.ntimgs_date().bits()),
-            )
+            .field("ntimgs_date", &self.ntimgs_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NTIMERS_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Timer version control register"]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/regclk.rs b/esp32p4/src/timg0/regclk.rs
index 0f90e1dc73..7449dd5019 100644
--- a/esp32p4/src/timg0/regclk.rs
+++ b/esp32p4/src/timg0/regclk.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGCLK")
-            .field("etm_en", &format_args!("{}", self.etm_en().bit()))
-            .field(
-                "wdt_clk_is_active",
-                &format_args!("{}", self.wdt_clk_is_active().bit()),
-            )
-            .field(
-                "timer_clk_is_active",
-                &format_args!("{}", self.timer_clk_is_active().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("etm_en", &self.etm_en())
+            .field("wdt_clk_is_active", &self.wdt_clk_is_active())
+            .field("timer_clk_is_active", &self.timer_clk_is_active())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - enable timer's etm task and event"]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/rtccalicfg.rs b/esp32p4/src/timg0/rtccalicfg.rs
index 25a598caa6..cac5ef6711 100644
--- a/esp32p4/src/timg0/rtccalicfg.rs
+++ b/esp32p4/src/timg0/rtccalicfg.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG")
-            .field(
-                "rtc_cali_start_cycling",
-                &format_args!("{}", self.rtc_cali_start_cycling().bit()),
-            )
-            .field(
-                "rtc_cali_clk_sel",
-                &format_args!("{}", self.rtc_cali_clk_sel().bits()),
-            )
-            .field(
-                "rtc_cali_rdy",
-                &format_args!("{}", self.rtc_cali_rdy().bit()),
-            )
-            .field(
-                "rtc_cali_max",
-                &format_args!("{}", self.rtc_cali_max().bits()),
-            )
-            .field(
-                "rtc_cali_start",
-                &format_args!("{}", self.rtc_cali_start().bit()),
-            )
+            .field("rtc_cali_start_cycling", &self.rtc_cali_start_cycling())
+            .field("rtc_cali_clk_sel", &self.rtc_cali_clk_sel())
+            .field("rtc_cali_rdy", &self.rtc_cali_rdy())
+            .field("rtc_cali_max", &self.rtc_cali_max())
+            .field("rtc_cali_start", &self.rtc_cali_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - 0: one-shot frequency calculation,1: periodic frequency calculation,"]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/rtccalicfg1.rs b/esp32p4/src/timg0/rtccalicfg1.rs
index 318e8b0ff7..fc1a1dee84 100644
--- a/esp32p4/src/timg0/rtccalicfg1.rs
+++ b/esp32p4/src/timg0/rtccalicfg1.rs
@@ -22,21 +22,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("RTCCALICFG1")
             .field(
                 "rtc_cali_cycling_data_vld",
-                &format_args!("{}", self.rtc_cali_cycling_data_vld().bit()),
-            )
-            .field(
-                "rtc_cali_value",
-                &format_args!("{}", self.rtc_cali_value().bits()),
+                &self.rtc_cali_cycling_data_vld(),
             )
+            .field("rtc_cali_value", &self.rtc_cali_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC calibration configure1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtccalicfg1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTCCALICFG1_SPEC;
 impl crate::RegisterSpec for RTCCALICFG1_SPEC {
diff --git a/esp32p4/src/timg0/rtccalicfg2.rs b/esp32p4/src/timg0/rtccalicfg2.rs
index a0ea39a67b..2142857b29 100644
--- a/esp32p4/src/timg0/rtccalicfg2.rs
+++ b/esp32p4/src/timg0/rtccalicfg2.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG2")
-            .field(
-                "rtc_cali_timeout",
-                &format_args!("{}", self.rtc_cali_timeout().bit()),
-            )
-            .field(
-                "rtc_cali_timeout_rst_cnt",
-                &format_args!("{}", self.rtc_cali_timeout_rst_cnt().bits()),
-            )
-            .field(
-                "rtc_cali_timeout_thres",
-                &format_args!("{}", self.rtc_cali_timeout_thres().bits()),
-            )
+            .field("rtc_cali_timeout", &self.rtc_cali_timeout())
+            .field("rtc_cali_timeout_rst_cnt", &self.rtc_cali_timeout_rst_cnt())
+            .field("rtc_cali_timeout_thres", &self.rtc_cali_timeout_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:6 - Cycles that release calibration timeout reset"]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/t/alarmhi.rs b/esp32p4/src/timg0/t/alarmhi.rs
index 22292581b3..e885af54c8 100644
--- a/esp32p4/src/timg0/t/alarmhi.rs
+++ b/esp32p4/src/timg0/t/alarmhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMHI")
-            .field("alarm_hi", &format_args!("{}", self.alarm_hi().bits()))
+            .field("alarm_hi", &self.alarm_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Timer %s alarm trigger time-base counter value, high 22 bits."]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/t/alarmlo.rs b/esp32p4/src/timg0/t/alarmlo.rs
index 7aaa51e9cb..d1f7b86948 100644
--- a/esp32p4/src/timg0/t/alarmlo.rs
+++ b/esp32p4/src/timg0/t/alarmlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMLO")
-            .field("alarm_lo", &format_args!("{}", self.alarm_lo().bits()))
+            .field("alarm_lo", &self.alarm_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Timer %s alarm trigger time-base counter value, low 32 bits."]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/t/config.rs b/esp32p4/src/timg0/t/config.rs
index 8e0b6da9bb..43302f2a37 100644
--- a/esp32p4/src/timg0/t/config.rs
+++ b/esp32p4/src/timg0/t/config.rs
@@ -64,21 +64,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG")
-            .field("use_xtal", &format_args!("{}", self.use_xtal().bit()))
-            .field("alarm_en", &format_args!("{}", self.alarm_en().bit()))
-            .field("divider", &format_args!("{}", self.divider().bits()))
-            .field("autoreload", &format_args!("{}", self.autoreload().bit()))
-            .field("increase", &format_args!("{}", self.increase().bit()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("use_xtal", &self.use_xtal())
+            .field("alarm_en", &self.alarm_en())
+            .field("divider", &self.divider())
+            .field("autoreload", &self.autoreload())
+            .field("increase", &self.increase())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/t/hi.rs b/esp32p4/src/timg0/t/hi.rs
index e73d1713fe..6ad1b0027a 100644
--- a/esp32p4/src/timg0/t/hi.rs
+++ b/esp32p4/src/timg0/t/hi.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
     }
 }
 #[doc = "Timer 0 current value, high 22 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32p4/src/timg0/t/lo.rs b/esp32p4/src/timg0/t/lo.rs
index 40c76cd3a1..a8846e3e83 100644
--- a/esp32p4/src/timg0/t/lo.rs
+++ b/esp32p4/src/timg0/t/lo.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
     }
 }
 #[doc = "Timer 0 current value, low 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32p4/src/timg0/t/loadhi.rs b/esp32p4/src/timg0/t/loadhi.rs
index 308a8375de..ac27dd6227 100644
--- a/esp32p4/src/timg0/t/loadhi.rs
+++ b/esp32p4/src/timg0/t/loadhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADHI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - High 22 bits of the value that a reload will load onto timer %s time-base counter."]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/t/loadlo.rs b/esp32p4/src/timg0/t/loadlo.rs
index 354ac9907d..82b436f990 100644
--- a/esp32p4/src/timg0/t/loadlo.rs
+++ b/esp32p4/src/timg0/t/loadlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADLO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Low 32 bits of the value that a reload will load onto timer %s time-base Counter."]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/t/update.rs b/esp32p4/src/timg0/t/update.rs
index 3869da8b15..139fa5cefb 100644
--- a/esp32p4/src/timg0/t/update.rs
+++ b/esp32p4/src/timg0/t/update.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE")
-            .field("update", &format_args!("{}", self.update().bit()))
+            .field("update", &self.update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched."]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/wdtconfig0.rs b/esp32p4/src/timg0/wdtconfig0.rs
index e45eea5e24..e8c89534d7 100644
--- a/esp32p4/src/timg0/wdtconfig0.rs
+++ b/esp32p4/src/timg0/wdtconfig0.rs
@@ -109,44 +109,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG0")
-            .field(
-                "wdt_appcpu_reset_en",
-                &format_args!("{}", self.wdt_appcpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field(
-                "wdt_use_xtal",
-                &format_args!("{}", self.wdt_use_xtal().bit()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_use_xtal", &self.wdt_use_xtal())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - WDT reset CPU enable."]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/wdtconfig1.rs b/esp32p4/src/timg0/wdtconfig1.rs
index 29740ede70..225f2e7355 100644
--- a/esp32p4/src/timg0/wdtconfig1.rs
+++ b/esp32p4/src/timg0/wdtconfig1.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG1")
-            .field(
-                "wdt_clk_prescale",
-                &format_args!("{}", self.wdt_clk_prescale().bits()),
-            )
+            .field("wdt_clk_prescale", &self.wdt_clk_prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, WDT 's clock divider counter will be reset."]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/wdtconfig2.rs b/esp32p4/src/timg0/wdtconfig2.rs
index f6646544fa..70947ea581 100644
--- a/esp32p4/src/timg0/wdtconfig2.rs
+++ b/esp32p4/src/timg0/wdtconfig2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG2")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 0 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/wdtconfig3.rs b/esp32p4/src/timg0/wdtconfig3.rs
index da0cf49ce2..63b4ed60f6 100644
--- a/esp32p4/src/timg0/wdtconfig3.rs
+++ b/esp32p4/src/timg0/wdtconfig3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG3")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 1 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/wdtconfig4.rs b/esp32p4/src/timg0/wdtconfig4.rs
index 2bbbc5bfe8..d132842f1f 100644
--- a/esp32p4/src/timg0/wdtconfig4.rs
+++ b/esp32p4/src/timg0/wdtconfig4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG4")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 2 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/wdtconfig5.rs b/esp32p4/src/timg0/wdtconfig5.rs
index 661482c54b..d101561533 100644
--- a/esp32p4/src/timg0/wdtconfig5.rs
+++ b/esp32p4/src/timg0/wdtconfig5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG5")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 3 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32p4/src/timg0/wdtwprotect.rs b/esp32p4/src/timg0/wdtwprotect.rs
index 44efc107f3..ca73442322 100644
--- a/esp32p4/src/timg0/wdtwprotect.rs
+++ b/esp32p4/src/timg0/wdtwprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTWPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTWPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - If the register contains a different value than its reset value, write protection is enabled."]
     #[inline(always)]
diff --git a/esp32p4/src/trace0/ahb_config.rs b/esp32p4/src/trace0/ahb_config.rs
index 3f4c3831cd..2da64ff7cf 100644
--- a/esp32p4/src/trace0/ahb_config.rs
+++ b/esp32p4/src/trace0/ahb_config.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_CONFIG")
-            .field("hburst", &format_args!("{}", self.hburst().bits()))
-            .field("max_incr", &format_args!("{}", self.max_incr().bits()))
+            .field("hburst", &self.hburst())
+            .field("max_incr", &self.max_incr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - set hburst"]
     #[inline(always)]
diff --git a/esp32p4/src/trace0/clock_gate.rs b/esp32p4/src/trace0/clock_gate.rs
index 9396387567..1798054b1a 100644
--- a/esp32p4/src/trace0/clock_gate.rs
+++ b/esp32p4/src/trace0/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable clock gate when access all registers in this module."]
     #[inline(always)]
diff --git a/esp32p4/src/trace0/config.rs b/esp32p4/src/trace0/config.rs
index 1c78df2e82..58f6f540d3 100644
--- a/esp32p4/src/trace0/config.rs
+++ b/esp32p4/src/trace0/config.rs
@@ -62,30 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG")
-            .field(
-                "dm_trigger_ena",
-                &format_args!("{}", self.dm_trigger_ena().bit()),
-            )
-            .field("reset_ena", &format_args!("{}", self.reset_ena().bit()))
-            .field("halt_ena", &format_args!("{}", self.halt_ena().bit()))
-            .field("stall_ena", &format_args!("{}", self.stall_ena().bit()))
-            .field(
-                "full_address",
-                &format_args!("{}", self.full_address().bit()),
-            )
-            .field(
-                "implicit_except",
-                &format_args!("{}", self.implicit_except().bit()),
-            )
+            .field("dm_trigger_ena", &self.dm_trigger_ena())
+            .field("reset_ena", &self.reset_ena())
+            .field("halt_ena", &self.halt_ena())
+            .field("stall_ena", &self.stall_ena())
+            .field("full_address", &self.full_address())
+            .field("implicit_except", &self.implicit_except())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configure whether or not enable cpu trigger action.\\\\1: enable\\\\0:disable\\\\"]
     #[inline(always)]
diff --git a/esp32p4/src/trace0/date.rs b/esp32p4/src/trace0/date.rs
index 774e5a9896..300677bc63 100644
--- a/esp32p4/src/trace0/date.rs
+++ b/esp32p4/src/trace0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/trace0/fifo_status.rs b/esp32p4/src/trace0/fifo_status.rs
index 78624cd5be..de91a79687 100644
--- a/esp32p4/src/trace0/fifo_status.rs
+++ b/esp32p4/src/trace0/fifo_status.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_STATUS")
-            .field("fifo_empty", &format_args!("{}", self.fifo_empty().bit()))
-            .field(
-                "work_status",
-                &format_args!("{}", self.work_status().bits()),
-            )
+            .field("fifo_empty", &self.fifo_empty())
+            .field("work_status", &self.work_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "fifo status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_STATUS_SPEC;
 impl crate::RegisterSpec for FIFO_STATUS_SPEC {
diff --git a/esp32p4/src/trace0/filter_comparator_control.rs b/esp32p4/src/trace0/filter_comparator_control.rs
index 0c0e0313b6..6bc77ed462 100644
--- a/esp32p4/src/trace0/filter_comparator_control.rs
+++ b/esp32p4/src/trace0/filter_comparator_control.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_COMPARATOR_CONTROL")
-            .field("p_input", &format_args!("{}", self.p_input().bit()))
-            .field("p_function", &format_args!("{}", self.p_function().bits()))
-            .field("p_notify", &format_args!("{}", self.p_notify().bit()))
-            .field("s_input", &format_args!("{}", self.s_input().bit()))
-            .field("s_function", &format_args!("{}", self.s_function().bits()))
-            .field("s_notify", &format_args!("{}", self.s_notify().bit()))
-            .field("match_mode", &format_args!("{}", self.match_mode().bits()))
+            .field("p_input", &self.p_input())
+            .field("p_function", &self.p_function())
+            .field("p_notify", &self.p_notify())
+            .field("s_input", &self.s_input())
+            .field("s_function", &self.s_function())
+            .field("s_notify", &self.s_notify())
+            .field("match_mode", &self.match_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_COMPARATOR_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Determines which input to compare against the primary comparator, \\\\0: iaddr, \\\\1: tval."]
     #[inline(always)]
diff --git a/esp32p4/src/trace0/filter_control.rs b/esp32p4/src/trace0/filter_control.rs
index ac99c0dd09..b52271a5a4 100644
--- a/esp32p4/src/trace0/filter_control.rs
+++ b/esp32p4/src/trace0/filter_control.rs
@@ -53,29 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CONTROL")
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
-            .field("match_comp", &format_args!("{}", self.match_comp().bit()))
-            .field(
-                "match_privilege",
-                &format_args!("{}", self.match_privilege().bit()),
-            )
-            .field(
-                "match_ecause",
-                &format_args!("{}", self.match_ecause().bit()),
-            )
-            .field(
-                "match_interrupt",
-                &format_args!("{}", self.match_interrupt().bit()),
-            )
+            .field("filter_en", &self.filter_en())
+            .field("match_comp", &self.match_comp())
+            .field("match_privilege", &self.match_privilege())
+            .field("match_ecause", &self.match_ecause())
+            .field("match_interrupt", &self.match_interrupt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configure whether or not enable filter unit. \\\\1: enable filter.\\\\ 0: always match"]
     #[inline(always)]
diff --git a/esp32p4/src/trace0/filter_match_control.rs b/esp32p4/src/trace0/filter_match_control.rs
index c08da7b556..f2621c99c4 100644
--- a/esp32p4/src/trace0/filter_match_control.rs
+++ b/esp32p4/src/trace0/filter_match_control.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_MATCH_CONTROL")
-            .field(
-                "match_choice_privilege",
-                &format_args!("{}", self.match_choice_privilege().bit()),
-            )
-            .field(
-                "match_value_interrupt",
-                &format_args!("{}", self.match_value_interrupt().bit()),
-            )
-            .field(
-                "match_choice_ecause",
-                &format_args!("{}", self.match_choice_ecause().bits()),
-            )
+            .field("match_choice_privilege", &self.match_choice_privilege())
+            .field("match_value_interrupt", &self.match_value_interrupt())
+            .field("match_choice_ecause", &self.match_choice_ecause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_MATCH_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Select match which privilege level when \\hyperref\\[fielddesc:TRACEMATCHPRIVILEGE\\]{TRACE_MATCH_PRIVILEGE} is set. \\\\1: machine mode. \\\\0: user mode"]
     #[inline(always)]
diff --git a/esp32p4/src/trace0/filter_p_comparator_match.rs b/esp32p4/src/trace0/filter_p_comparator_match.rs
index acefbcfc24..f6e3f757f2 100644
--- a/esp32p4/src/trace0/filter_p_comparator_match.rs
+++ b/esp32p4/src/trace0/filter_p_comparator_match.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_P_COMPARATOR_MATCH")
-            .field("p_match", &format_args!("{}", self.p_match().bits()))
+            .field("p_match", &self.p_match())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_P_COMPARATOR_MATCH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - primary comparator match value"]
     #[inline(always)]
diff --git a/esp32p4/src/trace0/filter_s_comparator_match.rs b/esp32p4/src/trace0/filter_s_comparator_match.rs
index b18432ab5d..d0bf53a9d0 100644
--- a/esp32p4/src/trace0/filter_s_comparator_match.rs
+++ b/esp32p4/src/trace0/filter_s_comparator_match.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_S_COMPARATOR_MATCH")
-            .field("s_match", &format_args!("{}", self.s_match().bits()))
+            .field("s_match", &self.s_match())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_S_COMPARATOR_MATCH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - secondary comparator match value"]
     #[inline(always)]
diff --git a/esp32p4/src/trace0/intr_ena.rs b/esp32p4/src/trace0/intr_ena.rs
index b5a4e078fe..e225fd8298 100644
--- a/esp32p4/src/trace0/intr_ena.rs
+++ b/esp32p4/src/trace0/intr_ena.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_ENA")
-            .field(
-                "fifo_overflow_intr_ena",
-                &format_args!("{}", self.fifo_overflow_intr_ena().bit()),
-            )
-            .field(
-                "mem_full_intr_ena",
-                &format_args!("{}", self.mem_full_intr_ena().bit()),
-            )
+            .field("fifo_overflow_intr_ena", &self.fifo_overflow_intr_ena())
+            .field("mem_full_intr_ena", &self.mem_full_intr_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 enable fifo_overflow interrupt"]
     #[inline(always)]
diff --git a/esp32p4/src/trace0/intr_raw.rs b/esp32p4/src/trace0/intr_raw.rs
index 83cb40c5ec..1393d7f17a 100644
--- a/esp32p4/src/trace0/intr_raw.rs
+++ b/esp32p4/src/trace0/intr_raw.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_RAW")
-            .field(
-                "fifo_overflow_intr_raw",
-                &format_args!("{}", self.fifo_overflow_intr_raw().bit()),
-            )
-            .field(
-                "mem_full_intr_raw",
-                &format_args!("{}", self.mem_full_intr_raw().bit()),
-            )
+            .field("fifo_overflow_intr_raw", &self.fifo_overflow_intr_raw())
+            .field("mem_full_intr_raw", &self.mem_full_intr_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_RAW_SPEC;
 impl crate::RegisterSpec for INTR_RAW_SPEC {
diff --git a/esp32p4/src/trace0/mem_current_addr.rs b/esp32p4/src/trace0/mem_current_addr.rs
index 854038cd82..611af268e9 100644
--- a/esp32p4/src/trace0/mem_current_addr.rs
+++ b/esp32p4/src/trace0/mem_current_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CURRENT_ADDR")
-            .field(
-                "mem_current_addr",
-                &format_args!("{}", self.mem_current_addr().bits()),
-            )
+            .field("mem_current_addr", &self.mem_current_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CURRENT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "mem current addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_current_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_CURRENT_ADDR_SPEC;
 impl crate::RegisterSpec for MEM_CURRENT_ADDR_SPEC {
diff --git a/esp32p4/src/trace0/mem_end_addr.rs b/esp32p4/src/trace0/mem_end_addr.rs
index 78675b80a6..de089e6fdb 100644
--- a/esp32p4/src/trace0/mem_end_addr.rs
+++ b/esp32p4/src/trace0/mem_end_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_END_ADDR")
-            .field(
-                "mem_end_addr",
-                &format_args!("{}", self.mem_end_addr().bits()),
-            )
+            .field("mem_end_addr", &self.mem_end_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_END_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The end address of trace memory"]
     #[inline(always)]
diff --git a/esp32p4/src/trace0/mem_start_addr.rs b/esp32p4/src/trace0/mem_start_addr.rs
index 4528e0e3df..f6b8320336 100644
--- a/esp32p4/src/trace0/mem_start_addr.rs
+++ b/esp32p4/src/trace0/mem_start_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_START_ADDR")
-            .field(
-                "mem_start_addr",
-                &format_args!("{}", self.mem_start_addr().bits()),
-            )
+            .field("mem_start_addr", &self.mem_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The start address of trace memory"]
     #[inline(always)]
diff --git a/esp32p4/src/trace0/resync_prolonged.rs b/esp32p4/src/trace0/resync_prolonged.rs
index 11ff7defc4..9a33441634 100644
--- a/esp32p4/src/trace0/resync_prolonged.rs
+++ b/esp32p4/src/trace0/resync_prolonged.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESYNC_PROLONGED")
-            .field(
-                "resync_prolonged",
-                &format_args!("{}", self.resync_prolonged().bits()),
-            )
-            .field(
-                "resync_mode",
-                &format_args!("{}", self.resync_mode().bits()),
-            )
+            .field("resync_prolonged", &self.resync_prolonged())
+            .field("resync_mode", &self.resync_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESYNC_PROLONGED_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - count number, when count to this value, send a sync package"]
     #[inline(always)]
diff --git a/esp32p4/src/trace0/trigger.rs b/esp32p4/src/trace0/trigger.rs
index 24beb71440..f63f29a7bb 100644
--- a/esp32p4/src/trace0/trigger.rs
+++ b/esp32p4/src/trace0/trigger.rs
@@ -30,17 +30,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TRIGGER")
-            .field("mem_loop", &format_args!("{}", self.mem_loop().bit()))
-            .field("restart_ena", &format_args!("{}", self.restart_ena().bit()))
+            .field("mem_loop", &self.mem_loop())
+            .field("restart_ena", &self.restart_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TRIGGER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configure whether or not start trace.\\\\1: start trace \\\\0: invalid\\\\"]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/arb_lost_cap.rs b/esp32p4/src/twai0/arb_lost_cap.rs
index 0e326e937c..edf5c834a7 100644
--- a/esp32p4/src/twai0/arb_lost_cap.rs
+++ b/esp32p4/src/twai0/arb_lost_cap.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_LOST_CAP")
-            .field(
-                "arbitration_lost_capture",
-                &format_args!("{}", self.arbitration_lost_capture().bits()),
-            )
+            .field("arbitration_lost_capture", &self.arbitration_lost_capture())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_LOST_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TWAI arbiter lost capture register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_lost_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ARB_LOST_CAP_SPEC;
 impl crate::RegisterSpec for ARB_LOST_CAP_SPEC {
diff --git a/esp32p4/src/twai0/bus_timing_0.rs b/esp32p4/src/twai0/bus_timing_0.rs
index 114b14ed9f..d416d38de6 100644
--- a/esp32p4/src/twai0/bus_timing_0.rs
+++ b/esp32p4/src/twai0/bus_timing_0.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMING_0")
-            .field("baud_presc", &format_args!("{}", self.baud_presc().bits()))
-            .field(
-                "sync_jump_width",
-                &format_args!("{}", self.sync_jump_width().bits()),
-            )
+            .field("baud_presc", &self.baud_presc())
+            .field("sync_jump_width", &self.sync_jump_width())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMING_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/bus_timing_1.rs b/esp32p4/src/twai0/bus_timing_1.rs
index d5ad23ca68..ab95b95428 100644
--- a/esp32p4/src/twai0/bus_timing_1.rs
+++ b/esp32p4/src/twai0/bus_timing_1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMING_1")
-            .field(
-                "time_segment1",
-                &format_args!("{}", self.time_segment1().bits()),
-            )
-            .field(
-                "time_segment2",
-                &format_args!("{}", self.time_segment2().bits()),
-            )
-            .field(
-                "time_sampling",
-                &format_args!("{}", self.time_sampling().bit()),
-            )
+            .field("time_segment1", &self.time_segment1())
+            .field("time_segment2", &self.time_segment2())
+            .field("time_sampling", &self.time_sampling())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMING_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/clock_divider.rs b/esp32p4/src/twai0/clock_divider.rs
index f5e7eb3181..e505a254ad 100644
--- a/esp32p4/src/twai0/clock_divider.rs
+++ b/esp32p4/src/twai0/clock_divider.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_DIVIDER")
-            .field("cd", &format_args!("{}", self.cd().bits()))
-            .field("clock_off", &format_args!("{}", self.clock_off().bit()))
+            .field("cd", &self.cd())
+            .field("clock_off", &self.clock_off())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_DIVIDER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - These bits are used to define the frequency at the external CLKOUT pin."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/data_0.rs b/esp32p4/src/twai0/data_0.rs
index a3cd741b06..42863fb7db 100644
--- a/esp32p4/src/twai0/data_0.rs
+++ b/esp32p4/src/twai0/data_0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_0")
-            .field("data_0", &format_args!("{}", self.data_0().bits()))
+            .field("data_0", &self.data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/data_1.rs b/esp32p4/src/twai0/data_1.rs
index 5520a720d0..80c4d2771c 100644
--- a/esp32p4/src/twai0/data_1.rs
+++ b/esp32p4/src/twai0/data_1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_1")
-            .field("data_1", &format_args!("{}", self.data_1().bits()))
+            .field("data_1", &self.data_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/data_10.rs b/esp32p4/src/twai0/data_10.rs
index 5a927a1293..b4678aa8ba 100644
--- a/esp32p4/src/twai0/data_10.rs
+++ b/esp32p4/src/twai0/data_10.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_10")
-            .field("data_10", &format_args!("{}", self.data_10().bits()))
+            .field("data_10", &self.data_10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/data_11.rs b/esp32p4/src/twai0/data_11.rs
index 881c5aa5f3..45b6970eea 100644
--- a/esp32p4/src/twai0/data_11.rs
+++ b/esp32p4/src/twai0/data_11.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_11")
-            .field("data_11", &format_args!("{}", self.data_11().bits()))
+            .field("data_11", &self.data_11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/data_12.rs b/esp32p4/src/twai0/data_12.rs
index 1e6b46c631..a270081e83 100644
--- a/esp32p4/src/twai0/data_12.rs
+++ b/esp32p4/src/twai0/data_12.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_12")
-            .field("data_12", &format_args!("{}", self.data_12().bits()))
+            .field("data_12", &self.data_12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/data_2.rs b/esp32p4/src/twai0/data_2.rs
index 664d031628..ede0fd34bc 100644
--- a/esp32p4/src/twai0/data_2.rs
+++ b/esp32p4/src/twai0/data_2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_2")
-            .field("data_2", &format_args!("{}", self.data_2().bits()))
+            .field("data_2", &self.data_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/data_3.rs b/esp32p4/src/twai0/data_3.rs
index ff24f90eef..27135c5f27 100644
--- a/esp32p4/src/twai0/data_3.rs
+++ b/esp32p4/src/twai0/data_3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_3")
-            .field("data_3", &format_args!("{}", self.data_3().bits()))
+            .field("data_3", &self.data_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/data_4.rs b/esp32p4/src/twai0/data_4.rs
index d886d0c90b..ce69844243 100644
--- a/esp32p4/src/twai0/data_4.rs
+++ b/esp32p4/src/twai0/data_4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_4")
-            .field("data_4", &format_args!("{}", self.data_4().bits()))
+            .field("data_4", &self.data_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/data_5.rs b/esp32p4/src/twai0/data_5.rs
index ca743b40c8..9a961eee6a 100644
--- a/esp32p4/src/twai0/data_5.rs
+++ b/esp32p4/src/twai0/data_5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_5")
-            .field("data_5", &format_args!("{}", self.data_5().bits()))
+            .field("data_5", &self.data_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/data_6.rs b/esp32p4/src/twai0/data_6.rs
index a23c84cbd1..6b8d8ab6b0 100644
--- a/esp32p4/src/twai0/data_6.rs
+++ b/esp32p4/src/twai0/data_6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_6")
-            .field("data_6", &format_args!("{}", self.data_6().bits()))
+            .field("data_6", &self.data_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/data_7.rs b/esp32p4/src/twai0/data_7.rs
index e33ef30519..b3117ea61e 100644
--- a/esp32p4/src/twai0/data_7.rs
+++ b/esp32p4/src/twai0/data_7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_7")
-            .field("data_7", &format_args!("{}", self.data_7().bits()))
+            .field("data_7", &self.data_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/data_8.rs b/esp32p4/src/twai0/data_8.rs
index 9fbc6cfcb8..b6d094a3b3 100644
--- a/esp32p4/src/twai0/data_8.rs
+++ b/esp32p4/src/twai0/data_8.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_8")
-            .field("data_8", &format_args!("{}", self.data_8().bits()))
+            .field("data_8", &self.data_8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/data_9.rs b/esp32p4/src/twai0/data_9.rs
index 0f633f55b7..419137bd6f 100644
--- a/esp32p4/src/twai0/data_9.rs
+++ b/esp32p4/src/twai0/data_9.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_9")
-            .field("data_9", &format_args!("{}", self.data_9().bits()))
+            .field("data_9", &self.data_9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/eco_cfg.rs b/esp32p4/src/twai0/eco_cfg.rs
index 7928138cdb..2174ebda7d 100644
--- a/esp32p4/src/twai0/eco_cfg.rs
+++ b/esp32p4/src/twai0/eco_cfg.rs
@@ -24,17 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_CFG")
-            .field("rdn_ena", &format_args!("{}", self.rdn_ena().bit()))
-            .field("rdn_result", &format_args!("{}", self.rdn_result().bit()))
+            .field("rdn_ena", &self.rdn_ena())
+            .field("rdn_result", &self.rdn_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable eco module."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/err_code_cap.rs b/esp32p4/src/twai0/err_code_cap.rs
index b32b4db0e1..189911898e 100644
--- a/esp32p4/src/twai0/err_code_cap.rs
+++ b/esp32p4/src/twai0/err_code_cap.rs
@@ -27,27 +27,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERR_CODE_CAP")
-            .field(
-                "err_capture_code_segment",
-                &format_args!("{}", self.err_capture_code_segment().bits()),
-            )
+            .field("err_capture_code_segment", &self.err_capture_code_segment())
             .field(
                 "err_capture_code_direction",
-                &format_args!("{}", self.err_capture_code_direction().bit()),
-            )
-            .field(
-                "err_capture_code_type",
-                &format_args!("{}", self.err_capture_code_type().bits()),
+                &self.err_capture_code_direction(),
             )
+            .field("err_capture_code_type", &self.err_capture_code_type())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERR_CODE_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TWAI error info capture register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_code_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ERR_CODE_CAP_SPEC;
 impl crate::RegisterSpec for ERR_CODE_CAP_SPEC {
diff --git a/esp32p4/src/twai0/err_warning_limit.rs b/esp32p4/src/twai0/err_warning_limit.rs
index c3d6ab8f2f..9c78f60158 100644
--- a/esp32p4/src/twai0/err_warning_limit.rs
+++ b/esp32p4/src/twai0/err_warning_limit.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERR_WARNING_LIMIT")
-            .field(
-                "err_warning_limit",
-                &format_args!("{}", self.err_warning_limit().bits()),
-            )
+            .field("err_warning_limit", &self.err_warning_limit())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERR_WARNING_LIMIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/hw_cfg.rs b/esp32p4/src/twai0/hw_cfg.rs
index d4b499209c..4f7c21ba6b 100644
--- a/esp32p4/src/twai0/hw_cfg.rs
+++ b/esp32p4/src/twai0/hw_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HW_CFG")
-            .field(
-                "hw_standby_en",
-                &format_args!("{}", self.hw_standby_en().bit()),
-            )
+            .field("hw_standby_en", &self.hw_standby_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HW_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable function that hardware control standby pin."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/hw_standby_cnt.rs b/esp32p4/src/twai0/hw_standby_cnt.rs
index 1aabc9964c..a41e6ee631 100644
--- a/esp32p4/src/twai0/hw_standby_cnt.rs
+++ b/esp32p4/src/twai0/hw_standby_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HW_STANDBY_CNT")
-            .field(
-                "standby_wait_cnt",
-                &format_args!("{}", self.standby_wait_cnt().bits()),
-            )
+            .field("standby_wait_cnt", &self.standby_wait_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HW_STANDBY_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/idle_intr_cnt.rs b/esp32p4/src/twai0/idle_intr_cnt.rs
index 9a4baf45b7..444052985e 100644
--- a/esp32p4/src/twai0/idle_intr_cnt.rs
+++ b/esp32p4/src/twai0/idle_intr_cnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDLE_INTR_CNT")
-            .field(
-                "idle_intr_cnt",
-                &format_args!("{}", self.idle_intr_cnt().bits()),
-            )
+            .field("idle_intr_cnt", &self.idle_intr_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_INTR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configure the number of cycles before triggering idle interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/interrupt.rs b/esp32p4/src/twai0/interrupt.rs
index 8e6b242a6f..d0504732c1 100644
--- a/esp32p4/src/twai0/interrupt.rs
+++ b/esp32p4/src/twai0/interrupt.rs
@@ -69,48 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT")
-            .field(
-                "receive_int_st",
-                &format_args!("{}", self.receive_int_st().bit()),
-            )
-            .field(
-                "transmit_int_st",
-                &format_args!("{}", self.transmit_int_st().bit()),
-            )
-            .field(
-                "err_warning_int_st",
-                &format_args!("{}", self.err_warning_int_st().bit()),
-            )
-            .field(
-                "data_overrun_int_st",
-                &format_args!("{}", self.data_overrun_int_st().bit()),
-            )
-            .field(
-                "ts_counter_ovfl_int_st",
-                &format_args!("{}", self.ts_counter_ovfl_int_st().bit()),
-            )
-            .field(
-                "err_passive_int_st",
-                &format_args!("{}", self.err_passive_int_st().bit()),
-            )
-            .field(
-                "arbitration_lost_int_st",
-                &format_args!("{}", self.arbitration_lost_int_st().bit()),
-            )
-            .field(
-                "bus_err_int_st",
-                &format_args!("{}", self.bus_err_int_st().bit()),
-            )
-            .field("idle_int_st", &format_args!("{}", self.idle_int_st().bit()))
+            .field("receive_int_st", &self.receive_int_st())
+            .field("transmit_int_st", &self.transmit_int_st())
+            .field("err_warning_int_st", &self.err_warning_int_st())
+            .field("data_overrun_int_st", &self.data_overrun_int_st())
+            .field("ts_counter_ovfl_int_st", &self.ts_counter_ovfl_int_st())
+            .field("err_passive_int_st", &self.err_passive_int_st())
+            .field("arbitration_lost_int_st", &self.arbitration_lost_int_st())
+            .field("bus_err_int_st", &self.bus_err_int_st())
+            .field("idle_int_st", &self.idle_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt signals' register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTERRUPT_SPEC;
 impl crate::RegisterSpec for INTERRUPT_SPEC {
diff --git a/esp32p4/src/twai0/interrupt_enable.rs b/esp32p4/src/twai0/interrupt_enable.rs
index 9f3372c2b5..403400a7f5 100644
--- a/esp32p4/src/twai0/interrupt_enable.rs
+++ b/esp32p4/src/twai0/interrupt_enable.rs
@@ -87,51 +87,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT_ENABLE")
-            .field(
-                "ext_receive_int_ena",
-                &format_args!("{}", self.ext_receive_int_ena().bit()),
-            )
-            .field(
-                "ext_transmit_int_ena",
-                &format_args!("{}", self.ext_transmit_int_ena().bit()),
-            )
-            .field(
-                "ext_err_warning_int_ena",
-                &format_args!("{}", self.ext_err_warning_int_ena().bit()),
-            )
-            .field(
-                "ext_data_overrun_int_ena",
-                &format_args!("{}", self.ext_data_overrun_int_ena().bit()),
-            )
-            .field(
-                "ts_counter_ovfl_int_ena",
-                &format_args!("{}", self.ts_counter_ovfl_int_ena().bit()),
-            )
-            .field(
-                "err_passive_int_ena",
-                &format_args!("{}", self.err_passive_int_ena().bit()),
-            )
-            .field(
-                "arbitration_lost_int_ena",
-                &format_args!("{}", self.arbitration_lost_int_ena().bit()),
-            )
-            .field(
-                "bus_err_int_ena",
-                &format_args!("{}", self.bus_err_int_ena().bit()),
-            )
-            .field(
-                "idle_int_ena",
-                &format_args!("{}", self.idle_int_ena().bit()),
-            )
+            .field("ext_receive_int_ena", &self.ext_receive_int_ena())
+            .field("ext_transmit_int_ena", &self.ext_transmit_int_ena())
+            .field("ext_err_warning_int_ena", &self.ext_err_warning_int_ena())
+            .field("ext_data_overrun_int_ena", &self.ext_data_overrun_int_ena())
+            .field("ts_counter_ovfl_int_ena", &self.ts_counter_ovfl_int_ena())
+            .field("err_passive_int_ena", &self.err_passive_int_ena())
+            .field("arbitration_lost_int_ena", &self.arbitration_lost_int_ena())
+            .field("bus_err_int_ena", &self.bus_err_int_ena())
+            .field("idle_int_ena", &self.idle_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable"]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/mode.rs b/esp32p4/src/twai0/mode.rs
index 4b3341db8f..94c12f63fc 100644
--- a/esp32p4/src/twai0/mode.rs
+++ b/esp32p4/src/twai0/mode.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODE")
-            .field("reset_mode", &format_args!("{}", self.reset_mode().bit()))
-            .field(
-                "listen_only_mode",
-                &format_args!("{}", self.listen_only_mode().bit()),
-            )
-            .field(
-                "self_test_mode",
-                &format_args!("{}", self.self_test_mode().bit()),
-            )
-            .field(
-                "acceptance_filter_mode",
-                &format_args!("{}", self.acceptance_filter_mode().bit()),
-            )
+            .field("reset_mode", &self.reset_mode())
+            .field("listen_only_mode", &self.listen_only_mode())
+            .field("self_test_mode", &self.self_test_mode())
+            .field("acceptance_filter_mode", &self.acceptance_filter_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/rx_err_cnt.rs b/esp32p4/src/twai0/rx_err_cnt.rs
index 6c17a3b1b8..8919de4888 100644
--- a/esp32p4/src/twai0/rx_err_cnt.rs
+++ b/esp32p4/src/twai0/rx_err_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ERR_CNT")
-            .field("rx_err_cnt", &format_args!("{}", self.rx_err_cnt().bits()))
+            .field("rx_err_cnt", &self.rx_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ERR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/rx_message_counter.rs b/esp32p4/src/twai0/rx_message_counter.rs
index 2e2dc1dc55..8286a41e35 100644
--- a/esp32p4/src/twai0/rx_message_counter.rs
+++ b/esp32p4/src/twai0/rx_message_counter.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_MESSAGE_COUNTER")
-            .field(
-                "rx_message_counter",
-                &format_args!("{}", self.rx_message_counter().bits()),
-            )
+            .field("rx_message_counter", &self.rx_message_counter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_MESSAGE_COUNTER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Received message counter register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_message_counter::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_MESSAGE_COUNTER_SPEC;
 impl crate::RegisterSpec for RX_MESSAGE_COUNTER_SPEC {
diff --git a/esp32p4/src/twai0/status.rs b/esp32p4/src/twai0/status.rs
index 911399d494..39d5ce4126 100644
--- a/esp32p4/src/twai0/status.rs
+++ b/esp32p4/src/twai0/status.rs
@@ -69,36 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field(
-                "receive_buffer",
-                &format_args!("{}", self.receive_buffer().bit()),
-            )
-            .field("overrun", &format_args!("{}", self.overrun().bit()))
-            .field(
-                "transmit_buffer",
-                &format_args!("{}", self.transmit_buffer().bit()),
-            )
-            .field(
-                "transmission_complete",
-                &format_args!("{}", self.transmission_complete().bit()),
-            )
-            .field("receive", &format_args!("{}", self.receive().bit()))
-            .field("transmit", &format_args!("{}", self.transmit().bit()))
-            .field("err", &format_args!("{}", self.err().bit()))
-            .field(
-                "node_bus_off",
-                &format_args!("{}", self.node_bus_off().bit()),
-            )
-            .field("miss", &format_args!("{}", self.miss().bit()))
+            .field("receive_buffer", &self.receive_buffer())
+            .field("overrun", &self.overrun())
+            .field("transmit_buffer", &self.transmit_buffer())
+            .field("transmission_complete", &self.transmission_complete())
+            .field("receive", &self.receive())
+            .field("transmit", &self.transmit())
+            .field("err", &self.err())
+            .field("node_bus_off", &self.node_bus_off())
+            .field("miss", &self.miss())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TWAI status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32p4/src/twai0/sw_standby_cfg.rs b/esp32p4/src/twai0/sw_standby_cfg.rs
index 77eacb6cc3..7842ae7587 100644
--- a/esp32p4/src/twai0/sw_standby_cfg.rs
+++ b/esp32p4/src/twai0/sw_standby_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SW_STANDBY_CFG")
-            .field(
-                "sw_standby_en",
-                &format_args!("{}", self.sw_standby_en().bit()),
-            )
-            .field(
-                "sw_standby_clr",
-                &format_args!("{}", self.sw_standby_clr().bit()),
-            )
+            .field("sw_standby_en", &self.sw_standby_en())
+            .field("sw_standby_clr", &self.sw_standby_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SW_STANDBY_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable standby pin."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/timestamp_cfg.rs b/esp32p4/src/twai0/timestamp_cfg.rs
index 5d9f78a2f2..08a1dc7630 100644
--- a/esp32p4/src/twai0/timestamp_cfg.rs
+++ b/esp32p4/src/twai0/timestamp_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMESTAMP_CFG")
-            .field("ts_enable", &format_args!("{}", self.ts_enable().bit()))
+            .field("ts_enable", &self.ts_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMESTAMP_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable the timestamp collection function."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/timestamp_data.rs b/esp32p4/src/twai0/timestamp_data.rs
index ed8751f4b1..1dcaa368bc 100644
--- a/esp32p4/src/twai0/timestamp_data.rs
+++ b/esp32p4/src/twai0/timestamp_data.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMESTAMP_DATA")
-            .field(
-                "timestamp_data",
-                &format_args!("{}", self.timestamp_data().bits()),
-            )
+            .field("timestamp_data", &self.timestamp_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMESTAMP_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Timestamp data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestamp_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIMESTAMP_DATA_SPEC;
 impl crate::RegisterSpec for TIMESTAMP_DATA_SPEC {
diff --git a/esp32p4/src/twai0/timestamp_prescaler.rs b/esp32p4/src/twai0/timestamp_prescaler.rs
index 6b33e7a91c..7624d83031 100644
--- a/esp32p4/src/twai0/timestamp_prescaler.rs
+++ b/esp32p4/src/twai0/timestamp_prescaler.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMESTAMP_PRESCALER")
-            .field("ts_div_num", &format_args!("{}", self.ts_div_num().bits()))
+            .field("ts_div_num", &self.ts_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMESTAMP_PRESCALER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures the clock division number of timestamp counter."]
     #[inline(always)]
diff --git a/esp32p4/src/twai0/tx_err_cnt.rs b/esp32p4/src/twai0/tx_err_cnt.rs
index 465da715b0..077faba61d 100644
--- a/esp32p4/src/twai0/tx_err_cnt.rs
+++ b/esp32p4/src/twai0/tx_err_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_ERR_CNT")
-            .field("tx_err_cnt", &format_args!("{}", self.tx_err_cnt().bits()))
+            .field("tx_err_cnt", &self.tx_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_ERR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/afifo_status.rs b/esp32p4/src/uart0/afifo_status.rs
index 32a27a7eed..22f55103b7 100644
--- a/esp32p4/src/uart0/afifo_status.rs
+++ b/esp32p4/src/uart0/afifo_status.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AFIFO_STATUS")
-            .field(
-                "tx_afifo_full",
-                &format_args!("{}", self.tx_afifo_full().bit()),
-            )
-            .field(
-                "tx_afifo_empty",
-                &format_args!("{}", self.tx_afifo_empty().bit()),
-            )
-            .field(
-                "rx_afifo_full",
-                &format_args!("{}", self.rx_afifo_full().bit()),
-            )
-            .field(
-                "rx_afifo_empty",
-                &format_args!("{}", self.rx_afifo_empty().bit()),
-            )
+            .field("tx_afifo_full", &self.tx_afifo_full())
+            .field("tx_afifo_empty", &self.tx_afifo_empty())
+            .field("rx_afifo_full", &self.rx_afifo_full())
+            .field("rx_afifo_empty", &self.rx_afifo_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART AFIFO Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`afifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for AFIFO_STATUS_SPEC {
diff --git a/esp32p4/src/uart0/at_cmd_char.rs b/esp32p4/src/uart0/at_cmd_char.rs
index 17e9222fe8..e75e1409cd 100644
--- a/esp32p4/src/uart0/at_cmd_char.rs
+++ b/esp32p4/src/uart0/at_cmd_char.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_CHAR")
-            .field(
-                "at_cmd_char",
-                &format_args!("{}", self.at_cmd_char().bits()),
-            )
-            .field("char_num", &format_args!("{}", self.char_num().bits()))
+            .field("at_cmd_char", &self.at_cmd_char())
+            .field("char_num", &self.char_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_CHAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/at_cmd_gaptout.rs b/esp32p4/src/uart0/at_cmd_gaptout.rs
index c7373436b0..7091ac8125 100644
--- a/esp32p4/src/uart0/at_cmd_gaptout.rs
+++ b/esp32p4/src/uart0/at_cmd_gaptout.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_GAPTOUT")
-            .field(
-                "rx_gap_tout",
-                &format_args!("{}", self.rx_gap_tout().bits()),
-            )
+            .field("rx_gap_tout", &self.rx_gap_tout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_GAPTOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the at_cmd chars."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/at_cmd_postcnt.rs b/esp32p4/src/uart0/at_cmd_postcnt.rs
index 078c4bb6a1..5db8445554 100644
--- a/esp32p4/src/uart0/at_cmd_postcnt.rs
+++ b/esp32p4/src/uart0/at_cmd_postcnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_POSTCNT")
-            .field(
-                "post_idle_num",
-                &format_args!("{}", self.post_idle_num().bits()),
-            )
+            .field("post_idle_num", &self.post_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_POSTCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the last at_cmd and the next data."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/at_cmd_precnt.rs b/esp32p4/src/uart0/at_cmd_precnt.rs
index 9e4a1cc58c..41790b5e67 100644
--- a/esp32p4/src/uart0/at_cmd_precnt.rs
+++ b/esp32p4/src/uart0/at_cmd_precnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_PRECNT")
-            .field(
-                "pre_idle_num",
-                &format_args!("{}", self.pre_idle_num().bits()),
-            )
+            .field("pre_idle_num", &self.pre_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_PRECNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first at_cmd is received by receiver."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/clk_conf.rs b/esp32p4/src/uart0/clk_conf.rs
index 52620b1d53..0ef610442e 100644
--- a/esp32p4/src/uart0/clk_conf.rs
+++ b/esp32p4/src/uart0/clk_conf.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field("tx_sclk_en", &format_args!("{}", self.tx_sclk_en().bit()))
-            .field("rx_sclk_en", &format_args!("{}", self.rx_sclk_en().bit()))
-            .field("tx_rst_core", &format_args!("{}", self.tx_rst_core().bit()))
-            .field("rx_rst_core", &format_args!("{}", self.rx_rst_core().bit()))
+            .field("tx_sclk_en", &self.tx_sclk_en())
+            .field("rx_sclk_en", &self.rx_sclk_en())
+            .field("tx_rst_core", &self.tx_rst_core())
+            .field("rx_rst_core", &self.rx_rst_core())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - Set this bit to enable UART Tx clock."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/clkdiv.rs b/esp32p4/src/uart0/clkdiv.rs
index ee4ca187b2..5b564fa0be 100644
--- a/esp32p4/src/uart0/clkdiv.rs
+++ b/esp32p4/src/uart0/clkdiv.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKDIV")
-            .field("clkdiv", &format_args!("{}", self.clkdiv().bits()))
-            .field(
-                "clkdiv_frag",
-                &format_args!("{}", self.clkdiv_frag().bits()),
-            )
+            .field("clkdiv", &self.clkdiv())
+            .field("clkdiv_frag", &self.clkdiv_frag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKDIV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/conf0.rs b/esp32p4/src/uart0/conf0.rs
index 6d441d9b79..318bf78ba3 100644
--- a/esp32p4/src/uart0/conf0.rs
+++ b/esp32p4/src/uart0/conf0.rs
@@ -206,43 +206,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("parity", &format_args!("{}", self.parity().bit()))
-            .field("parity_en", &format_args!("{}", self.parity_en().bit()))
-            .field("bit_num", &format_args!("{}", self.bit_num().bits()))
-            .field(
-                "stop_bit_num",
-                &format_args!("{}", self.stop_bit_num().bits()),
-            )
-            .field("txd_brk", &format_args!("{}", self.txd_brk().bit()))
-            .field("irda_dplx", &format_args!("{}", self.irda_dplx().bit()))
-            .field("irda_tx_en", &format_args!("{}", self.irda_tx_en().bit()))
-            .field("irda_wctl", &format_args!("{}", self.irda_wctl().bit()))
-            .field("irda_tx_inv", &format_args!("{}", self.irda_tx_inv().bit()))
-            .field("irda_rx_inv", &format_args!("{}", self.irda_rx_inv().bit()))
-            .field("loopback", &format_args!("{}", self.loopback().bit()))
-            .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit()))
-            .field("irda_en", &format_args!("{}", self.irda_en().bit()))
-            .field("rxd_inv", &format_args!("{}", self.rxd_inv().bit()))
-            .field("txd_inv", &format_args!("{}", self.txd_inv().bit()))
-            .field(
-                "dis_rx_dat_ovf",
-                &format_args!("{}", self.dis_rx_dat_ovf().bit()),
-            )
-            .field("err_wr_mask", &format_args!("{}", self.err_wr_mask().bit()))
-            .field("autobaud_en", &format_args!("{}", self.autobaud_en().bit()))
-            .field("mem_clk_en", &format_args!("{}", self.mem_clk_en().bit()))
-            .field("sw_rts", &format_args!("{}", self.sw_rts().bit()))
-            .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit()))
-            .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit()))
+            .field("parity", &self.parity())
+            .field("parity_en", &self.parity_en())
+            .field("bit_num", &self.bit_num())
+            .field("stop_bit_num", &self.stop_bit_num())
+            .field("txd_brk", &self.txd_brk())
+            .field("irda_dplx", &self.irda_dplx())
+            .field("irda_tx_en", &self.irda_tx_en())
+            .field("irda_wctl", &self.irda_wctl())
+            .field("irda_tx_inv", &self.irda_tx_inv())
+            .field("irda_rx_inv", &self.irda_rx_inv())
+            .field("loopback", &self.loopback())
+            .field("tx_flow_en", &self.tx_flow_en())
+            .field("irda_en", &self.irda_en())
+            .field("rxd_inv", &self.rxd_inv())
+            .field("txd_inv", &self.txd_inv())
+            .field("dis_rx_dat_ovf", &self.dis_rx_dat_ovf())
+            .field("err_wr_mask", &self.err_wr_mask())
+            .field("autobaud_en", &self.autobaud_en())
+            .field("mem_clk_en", &self.mem_clk_en())
+            .field("sw_rts", &self.sw_rts())
+            .field("rxfifo_rst", &self.rxfifo_rst())
+            .field("txfifo_rst", &self.txfifo_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to configure the parity check mode."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/conf1.rs b/esp32p4/src/uart0/conf1.rs
index 9b3521035b..88d452abe5 100644
--- a/esp32p4/src/uart0/conf1.rs
+++ b/esp32p4/src/uart0/conf1.rs
@@ -80,29 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "rxfifo_full_thrhd",
-                &format_args!("{}", self.rxfifo_full_thrhd().bits()),
-            )
-            .field(
-                "txfifo_empty_thrhd",
-                &format_args!("{}", self.txfifo_empty_thrhd().bits()),
-            )
-            .field("cts_inv", &format_args!("{}", self.cts_inv().bit()))
-            .field("dsr_inv", &format_args!("{}", self.dsr_inv().bit()))
-            .field("rts_inv", &format_args!("{}", self.rts_inv().bit()))
-            .field("dtr_inv", &format_args!("{}", self.dtr_inv().bit()))
-            .field("sw_dtr", &format_args!("{}", self.sw_dtr().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("rxfifo_full_thrhd", &self.rxfifo_full_thrhd())
+            .field("txfifo_empty_thrhd", &self.txfifo_empty_thrhd())
+            .field("cts_inv", &self.cts_inv())
+            .field("dsr_inv", &self.dsr_inv())
+            .field("rts_inv", &self.rts_inv())
+            .field("dtr_inv", &self.dtr_inv())
+            .field("sw_dtr", &self.sw_dtr())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/date.rs b/esp32p4/src/uart0/date.rs
index ca8e77528d..a8a192238f 100644
--- a/esp32p4/src/uart0/date.rs
+++ b/esp32p4/src/uart0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/uart0/fifo.rs b/esp32p4/src/uart0/fifo.rs
index 3ea719e7ab..fdc9ee6700 100644
--- a/esp32p4/src/uart0/fifo.rs
+++ b/esp32p4/src/uart0/fifo.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO")
-            .field(
-                "rxfifo_rd_byte",
-                &format_args!("{}", self.rxfifo_rd_byte().bits()),
-            )
+            .field("rxfifo_rd_byte", &self.rxfifo_rd_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - UART 0 accesses FIFO via this register."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/fsm_status.rs b/esp32p4/src/uart0/fsm_status.rs
index 7e47b06bf6..4088ac153f 100644
--- a/esp32p4/src/uart0/fsm_status.rs
+++ b/esp32p4/src/uart0/fsm_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_STATUS")
-            .field("st_urx_out", &format_args!("{}", self.st_urx_out().bits()))
-            .field("st_utx_out", &format_args!("{}", self.st_utx_out().bits()))
+            .field("st_urx_out", &self.st_urx_out())
+            .field("st_utx_out", &self.st_utx_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART transmit and receive status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FSM_STATUS_SPEC;
 impl crate::RegisterSpec for FSM_STATUS_SPEC {
diff --git a/esp32p4/src/uart0/highpulse.rs b/esp32p4/src/uart0/highpulse.rs
index 2a100f783a..8445906dbf 100644
--- a/esp32p4/src/uart0/highpulse.rs
+++ b/esp32p4/src/uart0/highpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIGHPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIGHPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud minimum high pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`highpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIGHPULSE_SPEC;
 impl crate::RegisterSpec for HIGHPULSE_SPEC {
diff --git a/esp32p4/src/uart0/hwfc_conf.rs b/esp32p4/src/uart0/hwfc_conf.rs
index c5bcb05208..f9a6aadfb8 100644
--- a/esp32p4/src/uart0/hwfc_conf.rs
+++ b/esp32p4/src/uart0/hwfc_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HWFC_CONF")
-            .field(
-                "rx_flow_thrhd",
-                &format_args!("{}", self.rx_flow_thrhd().bits()),
-            )
-            .field("rx_flow_en", &format_args!("{}", self.rx_flow_en().bit()))
+            .field("rx_flow_thrhd", &self.rx_flow_thrhd())
+            .field("rx_flow_en", &self.rx_flow_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HWFC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the maximum amount of data that can be received when hardware flow control works."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/id.rs b/esp32p4/src/uart0/id.rs
index 9c8cfa3a6b..670842afd9 100644
--- a/esp32p4/src/uart0/id.rs
+++ b/esp32p4/src/uart0/id.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("ID")
-            .field("id", &format_args!("{}", self.id().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("ID").field("id", &self.id()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/uart0/idle_conf.rs b/esp32p4/src/uart0/idle_conf.rs
index bc986732bf..a2f200e19e 100644
--- a/esp32p4/src/uart0/idle_conf.rs
+++ b/esp32p4/src/uart0/idle_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDLE_CONF")
-            .field(
-                "rx_idle_thrhd",
-                &format_args!("{}", self.rx_idle_thrhd().bits()),
-            )
-            .field(
-                "tx_idle_num",
-                &format_args!("{}", self.tx_idle_num().bits()),
-            )
+            .field("rx_idle_thrhd", &self.rx_idle_thrhd())
+            .field("tx_idle_num", &self.tx_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/int_ena.rs b/esp32p4/src/uart0/int_ena.rs
index fea57f25bd..3a8a9f2f95 100644
--- a/esp32p4/src/uart0/int_ena.rs
+++ b/esp32p4/src/uart0/int_ena.rs
@@ -188,50 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/int_raw.rs b/esp32p4/src/uart0/int_raw.rs
index 7c0c628adc..d47f4c54f2 100644
--- a/esp32p4/src/uart0/int_raw.rs
+++ b/esp32p4/src/uart0/int_raw.rs
@@ -188,50 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/int_st.rs b/esp32p4/src/uart0/int_st.rs
index 417bc433a0..c67c7f4b75 100644
--- a/esp32p4/src/uart0/int_st.rs
+++ b/esp32p4/src/uart0/int_st.rs
@@ -146,50 +146,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/uart0/lowpulse.rs b/esp32p4/src/uart0/lowpulse.rs
index 6736272863..03a2b35c08 100644
--- a/esp32p4/src/uart0/lowpulse.rs
+++ b/esp32p4/src/uart0/lowpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOWPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOWPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud minimum low pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lowpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOWPULSE_SPEC;
 impl crate::RegisterSpec for LOWPULSE_SPEC {
diff --git a/esp32p4/src/uart0/mem_conf.rs b/esp32p4/src/uart0/mem_conf.rs
index 8c55da8b47..e930d52fc0 100644
--- a/esp32p4/src/uart0/mem_conf.rs
+++ b/esp32p4/src/uart0/mem_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - Set this bit to force power down UART memory."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/mem_rx_status.rs b/esp32p4/src/uart0/mem_rx_status.rs
index 0a126a60b0..99d13455c6 100644
--- a/esp32p4/src/uart0/mem_rx_status.rs
+++ b/esp32p4/src/uart0/mem_rx_status.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_RX_STATUS")
-            .field(
-                "rx_sram_raddr",
-                &format_args!("{}", self.rx_sram_raddr().bits()),
-            )
-            .field(
-                "rx_sram_waddr",
-                &format_args!("{}", self.rx_sram_waddr().bits()),
-            )
+            .field("rx_sram_raddr", &self.rx_sram_raddr())
+            .field("rx_sram_waddr", &self.rx_sram_waddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Rx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_RX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_RX_STATUS_SPEC {
diff --git a/esp32p4/src/uart0/mem_tx_status.rs b/esp32p4/src/uart0/mem_tx_status.rs
index 8b947846b3..328cfcccd6 100644
--- a/esp32p4/src/uart0/mem_tx_status.rs
+++ b/esp32p4/src/uart0/mem_tx_status.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_TX_STATUS")
-            .field(
-                "tx_sram_waddr",
-                &format_args!("{}", self.tx_sram_waddr().bits()),
-            )
-            .field(
-                "tx_sram_raddr",
-                &format_args!("{}", self.tx_sram_raddr().bits()),
-            )
+            .field("tx_sram_waddr", &self.tx_sram_waddr())
+            .field("tx_sram_raddr", &self.tx_sram_raddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Tx-SRAM write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_TX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_TX_STATUS_SPEC {
diff --git a/esp32p4/src/uart0/negpulse.rs b/esp32p4/src/uart0/negpulse.rs
index 0daf3b983f..d033b00895 100644
--- a/esp32p4/src/uart0/negpulse.rs
+++ b/esp32p4/src/uart0/negpulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NEGPULSE")
-            .field(
-                "negedge_min_cnt",
-                &format_args!("{}", self.negedge_min_cnt().bits()),
-            )
+            .field("negedge_min_cnt", &self.negedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NEGPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud low pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`negpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NEGPULSE_SPEC;
 impl crate::RegisterSpec for NEGPULSE_SPEC {
diff --git a/esp32p4/src/uart0/pospulse.rs b/esp32p4/src/uart0/pospulse.rs
index 67a98ae05f..acf540a226 100644
--- a/esp32p4/src/uart0/pospulse.rs
+++ b/esp32p4/src/uart0/pospulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POSPULSE")
-            .field(
-                "posedge_min_cnt",
-                &format_args!("{}", self.posedge_min_cnt().bits()),
-            )
+            .field("posedge_min_cnt", &self.posedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POSPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud high pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pospulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct POSPULSE_SPEC;
 impl crate::RegisterSpec for POSPULSE_SPEC {
diff --git a/esp32p4/src/uart0/reg_update.rs b/esp32p4/src/uart0/reg_update.rs
index b2e4551f76..441e05815f 100644
--- a/esp32p4/src/uart0/reg_update.rs
+++ b/esp32p4/src/uart0/reg_update.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_UPDATE")
-            .field("reg_update", &format_args!("{}", self.reg_update().bit()))
+            .field("reg_update", &self.reg_update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/rs485_conf.rs b/esp32p4/src/uart0/rs485_conf.rs
index 5480b03198..dbf27d91ba 100644
--- a/esp32p4/src/uart0/rs485_conf.rs
+++ b/esp32p4/src/uart0/rs485_conf.rs
@@ -71,34 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RS485_CONF")
-            .field("rs485_en", &format_args!("{}", self.rs485_en().bit()))
-            .field("dl0_en", &format_args!("{}", self.dl0_en().bit()))
-            .field("dl1_en", &format_args!("{}", self.dl1_en().bit()))
-            .field(
-                "rs485tx_rx_en",
-                &format_args!("{}", self.rs485tx_rx_en().bit()),
-            )
-            .field(
-                "rs485rxby_tx_en",
-                &format_args!("{}", self.rs485rxby_tx_en().bit()),
-            )
-            .field(
-                "rs485_rx_dly_num",
-                &format_args!("{}", self.rs485_rx_dly_num().bit()),
-            )
-            .field(
-                "rs485_tx_dly_num",
-                &format_args!("{}", self.rs485_tx_dly_num().bits()),
-            )
+            .field("rs485_en", &self.rs485_en())
+            .field("dl0_en", &self.dl0_en())
+            .field("dl1_en", &self.dl1_en())
+            .field("rs485tx_rx_en", &self.rs485tx_rx_en())
+            .field("rs485rxby_tx_en", &self.rs485rxby_tx_en())
+            .field("rs485_rx_dly_num", &self.rs485_rx_dly_num())
+            .field("rs485_tx_dly_num", &self.rs485_tx_dly_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RS485_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to choose the rs485 mode."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/rx_filt.rs b/esp32p4/src/uart0/rx_filt.rs
index c24c62977e..21576af0e9 100644
--- a/esp32p4/src/uart0/rx_filt.rs
+++ b/esp32p4/src/uart0/rx_filt.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_FILT")
-            .field(
-                "glitch_filt",
-                &format_args!("{}", self.glitch_filt().bits()),
-            )
-            .field(
-                "glitch_filt_en",
-                &format_args!("{}", self.glitch_filt_en().bit()),
-            )
+            .field("glitch_filt", &self.glitch_filt())
+            .field("glitch_filt_en", &self.glitch_filt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_FILT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - when input pulse width is lower than this value the pulse is ignored."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/rxd_cnt.rs b/esp32p4/src/uart0/rxd_cnt.rs
index f08d5e0323..c3c3052a66 100644
--- a/esp32p4/src/uart0/rxd_cnt.rs
+++ b/esp32p4/src/uart0/rxd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXD_CNT")
-            .field(
-                "rxd_edge_cnt",
-                &format_args!("{}", self.rxd_edge_cnt().bits()),
-            )
+            .field("rxd_edge_cnt", &self.rxd_edge_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud edge change count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXD_CNT_SPEC;
 impl crate::RegisterSpec for RXD_CNT_SPEC {
diff --git a/esp32p4/src/uart0/sleep_conf0.rs b/esp32p4/src/uart0/sleep_conf0.rs
index 1c5c7f7eed..a8481a8783 100644
--- a/esp32p4/src/uart0/sleep_conf0.rs
+++ b/esp32p4/src/uart0/sleep_conf0.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF0")
-            .field("wk_char1", &format_args!("{}", self.wk_char1().bits()))
-            .field("wk_char2", &format_args!("{}", self.wk_char2().bits()))
-            .field("wk_char3", &format_args!("{}", self.wk_char3().bits()))
-            .field("wk_char4", &format_args!("{}", self.wk_char4().bits()))
+            .field("wk_char1", &self.wk_char1())
+            .field("wk_char2", &self.wk_char2())
+            .field("wk_char3", &self.wk_char3())
+            .field("wk_char4", &self.wk_char4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register restores the specified wake up char1 to wake up"]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/sleep_conf1.rs b/esp32p4/src/uart0/sleep_conf1.rs
index f9f665a833..bf71699cf5 100644
--- a/esp32p4/src/uart0/sleep_conf1.rs
+++ b/esp32p4/src/uart0/sleep_conf1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF1")
-            .field("wk_char0", &format_args!("{}", self.wk_char0().bits()))
+            .field("wk_char0", &self.wk_char0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register restores the specified char0 to wake up"]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/sleep_conf2.rs b/esp32p4/src/uart0/sleep_conf2.rs
index 4ba2a7a251..06e8c23f14 100644
--- a/esp32p4/src/uart0/sleep_conf2.rs
+++ b/esp32p4/src/uart0/sleep_conf2.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF2")
-            .field(
-                "active_threshold",
-                &format_args!("{}", self.active_threshold().bits()),
-            )
-            .field(
-                "rx_wake_up_thrhd",
-                &format_args!("{}", self.rx_wake_up_thrhd().bits()),
-            )
-            .field(
-                "wk_char_num",
-                &format_args!("{}", self.wk_char_num().bits()),
-            )
-            .field(
-                "wk_char_mask",
-                &format_args!("{}", self.wk_char_mask().bits()),
-            )
-            .field(
-                "wk_mode_sel",
-                &format_args!("{}", self.wk_mode_sel().bits()),
-            )
+            .field("active_threshold", &self.active_threshold())
+            .field("rx_wake_up_thrhd", &self.rx_wake_up_thrhd())
+            .field("wk_char_num", &self.wk_char_num())
+            .field("wk_char_mask", &self.wk_char_mask())
+            .field("wk_mode_sel", &self.wk_mode_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/status.rs b/esp32p4/src/uart0/status.rs
index c6f8b87e2e..b94bda636c 100644
--- a/esp32p4/src/uart0/status.rs
+++ b/esp32p4/src/uart0/status.rs
@@ -62,23 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("dsrn", &format_args!("{}", self.dsrn().bit()))
-            .field("ctsn", &format_args!("{}", self.ctsn().bit()))
-            .field("rxd", &format_args!("{}", self.rxd().bit()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field("dtrn", &format_args!("{}", self.dtrn().bit()))
-            .field("rtsn", &format_args!("{}", self.rtsn().bit()))
-            .field("txd", &format_args!("{}", self.txd().bit()))
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("dsrn", &self.dsrn())
+            .field("ctsn", &self.ctsn())
+            .field("rxd", &self.rxd())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("dtrn", &self.dtrn())
+            .field("rtsn", &self.rtsn())
+            .field("txd", &self.txd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32p4/src/uart0/swfc_conf0.rs b/esp32p4/src/uart0/swfc_conf0.rs
index 341967dafc..bbbea9d9e5 100644
--- a/esp32p4/src/uart0/swfc_conf0.rs
+++ b/esp32p4/src/uart0/swfc_conf0.rs
@@ -89,30 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF0")
-            .field("xon_char", &format_args!("{}", self.xon_char().bits()))
-            .field("xoff_char", &format_args!("{}", self.xoff_char().bits()))
-            .field(
-                "xon_xoff_still_send",
-                &format_args!("{}", self.xon_xoff_still_send().bit()),
-            )
-            .field(
-                "sw_flow_con_en",
-                &format_args!("{}", self.sw_flow_con_en().bit()),
-            )
-            .field("xonoff_del", &format_args!("{}", self.xonoff_del().bit()))
-            .field("force_xon", &format_args!("{}", self.force_xon().bit()))
-            .field("force_xoff", &format_args!("{}", self.force_xoff().bit()))
-            .field("send_xon", &format_args!("{}", self.send_xon().bit()))
-            .field("send_xoff", &format_args!("{}", self.send_xoff().bit()))
+            .field("xon_char", &self.xon_char())
+            .field("xoff_char", &self.xoff_char())
+            .field("xon_xoff_still_send", &self.xon_xoff_still_send())
+            .field("sw_flow_con_en", &self.sw_flow_con_en())
+            .field("xonoff_del", &self.xonoff_del())
+            .field("force_xon", &self.force_xon())
+            .field("force_xoff", &self.force_xoff())
+            .field("send_xon", &self.send_xon())
+            .field("send_xoff", &self.send_xoff())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register stores the Xon flow control char."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/swfc_conf1.rs b/esp32p4/src/uart0/swfc_conf1.rs
index f747b693ec..d7558a5286 100644
--- a/esp32p4/src/uart0/swfc_conf1.rs
+++ b/esp32p4/src/uart0/swfc_conf1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF1")
-            .field(
-                "xon_threshold",
-                &format_args!("{}", self.xon_threshold().bits()),
-            )
-            .field(
-                "xoff_threshold",
-                &format_args!("{}", self.xoff_threshold().bits()),
-            )
+            .field("xon_threshold", &self.xon_threshold())
+            .field("xoff_threshold", &self.xoff_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/tout_conf.rs b/esp32p4/src/uart0/tout_conf.rs
index 92fe213cbb..908b3e6b17 100644
--- a/esp32p4/src/uart0/tout_conf.rs
+++ b/esp32p4/src/uart0/tout_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUT_CONF")
-            .field("rx_tout_en", &format_args!("{}", self.rx_tout_en().bit()))
-            .field(
-                "rx_tout_flow_dis",
-                &format_args!("{}", self.rx_tout_flow_dis().bit()),
-            )
-            .field(
-                "rx_tout_thrhd",
-                &format_args!("{}", self.rx_tout_thrhd().bits()),
-            )
+            .field("rx_tout_en", &self.rx_tout_en())
+            .field("rx_tout_flow_dis", &self.rx_tout_flow_dis())
+            .field("rx_tout_thrhd", &self.rx_tout_thrhd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enble bit for uart receiver's timeout function."]
     #[inline(always)]
diff --git a/esp32p4/src/uart0/txbrk_conf.rs b/esp32p4/src/uart0/txbrk_conf.rs
index bfa2a9b911..65d37271c2 100644
--- a/esp32p4/src/uart0/txbrk_conf.rs
+++ b/esp32p4/src/uart0/txbrk_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXBRK_CONF")
-            .field("tx_brk_num", &format_args!("{}", self.tx_brk_num().bits()))
+            .field("tx_brk_num", &self.tx_brk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXBRK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."]
     #[inline(always)]
diff --git a/esp32p4/src/uhci0/ack_num.rs b/esp32p4/src/uhci0/ack_num.rs
index b766a5b42b..05022428cc 100644
--- a/esp32p4/src/uhci0/ack_num.rs
+++ b/esp32p4/src/uhci0/ack_num.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ACK_NUM")
-            .field("ack_num", &format_args!("{}", self.ack_num().bits()))
+            .field("ack_num", &self.ack_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ACK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Indicates the ACK number during software flow control."]
     #[inline(always)]
diff --git a/esp32p4/src/uhci0/conf0.rs b/esp32p4/src/uhci0/conf0.rs
index 2f3bd92c66..6658e04fdd 100644
--- a/esp32p4/src/uhci0/conf0.rs
+++ b/esp32p4/src/uhci0/conf0.rs
@@ -107,35 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("tx_rst", &format_args!("{}", self.tx_rst().bit()))
-            .field("rx_rst", &format_args!("{}", self.rx_rst().bit()))
-            .field("uart_sel", &format_args!("{}", self.uart_sel().bits()))
-            .field("seper_en", &format_args!("{}", self.seper_en().bit()))
-            .field("head_en", &format_args!("{}", self.head_en().bit()))
-            .field("crc_rec_en", &format_args!("{}", self.crc_rec_en().bit()))
-            .field(
-                "uart_idle_eof_en",
-                &format_args!("{}", self.uart_idle_eof_en().bit()),
-            )
-            .field("len_eof_en", &format_args!("{}", self.len_eof_en().bit()))
-            .field(
-                "encode_crc_en",
-                &format_args!("{}", self.encode_crc_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "uart_rx_brk_eof_en",
-                &format_args!("{}", self.uart_rx_brk_eof_en().bit()),
-            )
+            .field("tx_rst", &self.tx_rst())
+            .field("rx_rst", &self.rx_rst())
+            .field("uart_sel", &self.uart_sel())
+            .field("seper_en", &self.seper_en())
+            .field("head_en", &self.head_en())
+            .field("crc_rec_en", &self.crc_rec_en())
+            .field("uart_idle_eof_en", &self.uart_idle_eof_en())
+            .field("len_eof_en", &self.len_eof_en())
+            .field("encode_crc_en", &self.encode_crc_en())
+            .field("clk_en", &self.clk_en())
+            .field("uart_rx_brk_eof_en", &self.uart_rx_brk_eof_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 then write 0 to this bit to reset decode state machine."]
     #[inline(always)]
diff --git a/esp32p4/src/uhci0/conf1.rs b/esp32p4/src/uhci0/conf1.rs
index b4ee4f1a42..f5ee721368 100644
--- a/esp32p4/src/uhci0/conf1.rs
+++ b/esp32p4/src/uhci0/conf1.rs
@@ -73,37 +73,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "check_sum_en",
-                &format_args!("{}", self.check_sum_en().bit()),
-            )
-            .field(
-                "check_seq_en",
-                &format_args!("{}", self.check_seq_en().bit()),
-            )
-            .field("crc_disable", &format_args!("{}", self.crc_disable().bit()))
-            .field("save_head", &format_args!("{}", self.save_head().bit()))
-            .field(
-                "tx_check_sum_re",
-                &format_args!("{}", self.tx_check_sum_re().bit()),
-            )
-            .field(
-                "tx_ack_num_re",
-                &format_args!("{}", self.tx_ack_num_re().bit()),
-            )
-            .field(
-                "wait_sw_start",
-                &format_args!("{}", self.wait_sw_start().bit()),
-            )
+            .field("check_sum_en", &self.check_sum_en())
+            .field("check_seq_en", &self.check_seq_en())
+            .field("crc_disable", &self.crc_disable())
+            .field("save_head", &self.save_head())
+            .field("tx_check_sum_re", &self.tx_check_sum_re())
+            .field("tx_ack_num_re", &self.tx_ack_num_re())
+            .field("wait_sw_start", &self.wait_sw_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable head checksum check when receiving."]
     #[inline(always)]
diff --git a/esp32p4/src/uhci0/date.rs b/esp32p4/src/uhci0/date.rs
index b1c29fb247..157a787b5f 100644
--- a/esp32p4/src/uhci0/date.rs
+++ b/esp32p4/src/uhci0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/uhci0/esc_conf.rs b/esp32p4/src/uhci0/esc_conf.rs
index 91511d3359..9c2ddd50ed 100644
--- a/esp32p4/src/uhci0/esc_conf.rs
+++ b/esp32p4/src/uhci0/esc_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ESC_CONF")
-            .field("seper_char", &format_args!("{}", self.seper_char().bits()))
-            .field(
-                "seper_esc_char0",
-                &format_args!("{}", self.seper_esc_char0().bits()),
-            )
-            .field(
-                "seper_esc_char1",
-                &format_args!("{}", self.seper_esc_char1().bits()),
-            )
+            .field("seper_char", &self.seper_char())
+            .field("seper_esc_char0", &self.seper_esc_char0())
+            .field("seper_esc_char1", &self.seper_esc_char1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ESC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures the delimiter for encoding, default value is 0xC0."]
     #[inline(always)]
diff --git a/esp32p4/src/uhci0/escape_conf.rs b/esp32p4/src/uhci0/escape_conf.rs
index 33710ca4d7..3b753424c9 100644
--- a/esp32p4/src/uhci0/escape_conf.rs
+++ b/esp32p4/src/uhci0/escape_conf.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ESCAPE_CONF")
-            .field(
-                "tx_c0_esc_en",
-                &format_args!("{}", self.tx_c0_esc_en().bit()),
-            )
-            .field(
-                "tx_db_esc_en",
-                &format_args!("{}", self.tx_db_esc_en().bit()),
-            )
-            .field(
-                "tx_11_esc_en",
-                &format_args!("{}", self.tx_11_esc_en().bit()),
-            )
-            .field(
-                "tx_13_esc_en",
-                &format_args!("{}", self.tx_13_esc_en().bit()),
-            )
-            .field(
-                "rx_c0_esc_en",
-                &format_args!("{}", self.rx_c0_esc_en().bit()),
-            )
-            .field(
-                "rx_db_esc_en",
-                &format_args!("{}", self.rx_db_esc_en().bit()),
-            )
-            .field(
-                "rx_11_esc_en",
-                &format_args!("{}", self.rx_11_esc_en().bit()),
-            )
-            .field(
-                "rx_13_esc_en",
-                &format_args!("{}", self.rx_13_esc_en().bit()),
-            )
+            .field("tx_c0_esc_en", &self.tx_c0_esc_en())
+            .field("tx_db_esc_en", &self.tx_db_esc_en())
+            .field("tx_11_esc_en", &self.tx_11_esc_en())
+            .field("tx_13_esc_en", &self.tx_13_esc_en())
+            .field("rx_c0_esc_en", &self.rx_c0_esc_en())
+            .field("rx_db_esc_en", &self.rx_db_esc_en())
+            .field("rx_11_esc_en", &self.rx_11_esc_en())
+            .field("rx_13_esc_en", &self.rx_13_esc_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ESCAPE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable resolve char 0xC0 when DMA receiving data."]
     #[inline(always)]
diff --git a/esp32p4/src/uhci0/hung_conf.rs b/esp32p4/src/uhci0/hung_conf.rs
index f0d90d8564..20cd44a030 100644
--- a/esp32p4/src/uhci0/hung_conf.rs
+++ b/esp32p4/src/uhci0/hung_conf.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HUNG_CONF")
-            .field(
-                "txfifo_timeout",
-                &format_args!("{}", self.txfifo_timeout().bits()),
-            )
-            .field(
-                "txfifo_timeout_shift",
-                &format_args!("{}", self.txfifo_timeout_shift().bits()),
-            )
-            .field(
-                "txfifo_timeout_ena",
-                &format_args!("{}", self.txfifo_timeout_ena().bit()),
-            )
-            .field(
-                "rxfifo_timeout",
-                &format_args!("{}", self.rxfifo_timeout().bits()),
-            )
-            .field(
-                "rxfifo_timeout_shift",
-                &format_args!("{}", self.rxfifo_timeout_shift().bits()),
-            )
-            .field(
-                "rxfifo_timeout_ena",
-                &format_args!("{}", self.rxfifo_timeout_ena().bit()),
-            )
+            .field("txfifo_timeout", &self.txfifo_timeout())
+            .field("txfifo_timeout_shift", &self.txfifo_timeout_shift())
+            .field("txfifo_timeout_ena", &self.txfifo_timeout_ena())
+            .field("rxfifo_timeout", &self.rxfifo_timeout())
+            .field("rxfifo_timeout_shift", &self.rxfifo_timeout_shift())
+            .field("rxfifo_timeout_ena", &self.rxfifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving data."]
     #[inline(always)]
diff --git a/esp32p4/src/uhci0/int_ena.rs b/esp32p4/src/uhci0/int_ena.rs
index 10d05b5816..89c8b00078 100644
--- a/esp32p4/src/uhci0/int_ena.rs
+++ b/esp32p4/src/uhci0/int_ena.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
-            .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable the interrupt of UHCI_RX_START_INT."]
     #[inline(always)]
diff --git a/esp32p4/src/uhci0/int_raw.rs b/esp32p4/src/uhci0/int_raw.rs
index 24f110aaa0..47771a616d 100644
--- a/esp32p4/src/uhci0/int_raw.rs
+++ b/esp32p4/src/uhci0/int_raw.rs
@@ -89,30 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
-            .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("out_eof", &self.out_eof())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when delimiter is sent successfully."]
     #[inline(always)]
diff --git a/esp32p4/src/uhci0/int_st.rs b/esp32p4/src/uhci0/int_st.rs
index e02ff60b01..07481b4367 100644
--- a/esp32p4/src/uhci0/int_st.rs
+++ b/esp32p4/src/uhci0/int_st.rs
@@ -69,33 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
-            .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UHCI Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/uhci0/pkt_thres.rs b/esp32p4/src/uhci0/pkt_thres.rs
index 9619b17d53..ada0d1f6da 100644
--- a/esp32p4/src/uhci0/pkt_thres.rs
+++ b/esp32p4/src/uhci0/pkt_thres.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PKT_THRES")
-            .field("pkt_thrs", &format_args!("{}", self.pkt_thrs().bits()))
+            .field("pkt_thrs", &self.pkt_thrs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PKT_THRES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - Configures the data packet's maximum length when UHCI_HEAD_EN is 0."]
     #[inline(always)]
diff --git a/esp32p4/src/uhci0/quick_sent.rs b/esp32p4/src/uhci0/quick_sent.rs
index 486de96911..9e8e78feab 100644
--- a/esp32p4/src/uhci0/quick_sent.rs
+++ b/esp32p4/src/uhci0/quick_sent.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUICK_SENT")
-            .field(
-                "single_send_num",
-                &format_args!("{}", self.single_send_num().bits()),
-            )
-            .field(
-                "always_send_num",
-                &format_args!("{}", self.always_send_num().bits()),
-            )
-            .field(
-                "always_send_en",
-                &format_args!("{}", self.always_send_en().bit()),
-            )
+            .field("single_send_num", &self.single_send_num())
+            .field("always_send_num", &self.always_send_num())
+            .field("always_send_en", &self.always_send_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUICK_SENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Configures single_send mode."]
     #[inline(always)]
diff --git a/esp32p4/src/uhci0/reg_q/word0.rs b/esp32p4/src/uhci0/reg_q/word0.rs
index 625b5f8670..e449869777 100644
--- a/esp32p4/src/uhci0/reg_q/word0.rs
+++ b/esp32p4/src/uhci0/reg_q/word0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WORD0")
-            .field("send_word", &format_args!("{}", self.send_word().bits()))
+            .field("send_word", &self.send_word())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WORD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
     #[inline(always)]
diff --git a/esp32p4/src/uhci0/reg_q/word1.rs b/esp32p4/src/uhci0/reg_q/word1.rs
index b8dfb313c3..7239fdf4ad 100644
--- a/esp32p4/src/uhci0/reg_q/word1.rs
+++ b/esp32p4/src/uhci0/reg_q/word1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WORD1")
-            .field("send_word", &format_args!("{}", self.send_word().bits()))
+            .field("send_word", &self.send_word())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WORD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
     #[inline(always)]
diff --git a/esp32p4/src/uhci0/rx_head.rs b/esp32p4/src/uhci0/rx_head.rs
index afdf07a90c..f28c2d648a 100644
--- a/esp32p4/src/uhci0/rx_head.rs
+++ b/esp32p4/src/uhci0/rx_head.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_HEAD")
-            .field("rx_head", &format_args!("{}", self.rx_head().bits()))
+            .field("rx_head", &self.rx_head())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_HEAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UHCI Head Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_head::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_HEAD_SPEC;
 impl crate::RegisterSpec for RX_HEAD_SPEC {
diff --git a/esp32p4/src/uhci0/state0.rs b/esp32p4/src/uhci0/state0.rs
index 1c5b38008b..23e54cd08a 100644
--- a/esp32p4/src/uhci0/state0.rs
+++ b/esp32p4/src/uhci0/state0.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE0")
-            .field(
-                "rx_err_cause",
-                &format_args!("{}", self.rx_err_cause().bits()),
-            )
-            .field(
-                "decode_state",
-                &format_args!("{}", self.decode_state().bits()),
-            )
+            .field("rx_err_cause", &self.rx_err_cause())
+            .field("decode_state", &self.decode_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UHCI Receive Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE0_SPEC;
 impl crate::RegisterSpec for STATE0_SPEC {
diff --git a/esp32p4/src/uhci0/state1.rs b/esp32p4/src/uhci0/state1.rs
index 2daade578f..23f3c88dd3 100644
--- a/esp32p4/src/uhci0/state1.rs
+++ b/esp32p4/src/uhci0/state1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE1")
-            .field(
-                "encode_state",
-                &format_args!("{}", self.encode_state().bits()),
-            )
+            .field("encode_state", &self.encode_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UHCI Transmit Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE1_SPEC;
 impl crate::RegisterSpec for STATE1_SPEC {
diff --git a/esp32p4/src/usb_device/bus_reset_st.rs b/esp32p4/src/usb_device/bus_reset_st.rs
index 9b463d08d3..3c2d490751 100644
--- a/esp32p4/src/usb_device/bus_reset_st.rs
+++ b/esp32p4/src/usb_device/bus_reset_st.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_RESET_ST")
-            .field(
-                "usb_bus_reset_st",
-                &format_args!("{}", self.usb_bus_reset_st().bit()),
-            )
+            .field("usb_bus_reset_st", &self.usb_bus_reset_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_RESET_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "USB Bus reset status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_reset_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUS_RESET_ST_SPEC;
 impl crate::RegisterSpec for BUS_RESET_ST_SPEC {
diff --git a/esp32p4/src/usb_device/chip_rst.rs b/esp32p4/src/usb_device/chip_rst.rs
index f66590e261..3773555886 100644
--- a/esp32p4/src/usb_device/chip_rst.rs
+++ b/esp32p4/src/usb_device/chip_rst.rs
@@ -31,21 +31,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHIP_RST")
-            .field("rts", &format_args!("{}", self.rts().bit()))
-            .field("dtr", &format_args!("{}", self.dtr().bit()))
-            .field(
-                "usb_uart_chip_rst_dis",
-                &format_args!("{}", self.usb_uart_chip_rst_dis().bit()),
-            )
+            .field("rts", &self.rts())
+            .field("dtr", &self.dtr())
+            .field("usb_uart_chip_rst_dis", &self.usb_uart_chip_rst_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHIP_RST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - Set this bit to disable chip reset from usb serial channel to reset chip."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/conf0.rs b/esp32p4/src/usb_device/conf0.rs
index d3e851d8f0..fc639deb91 100644
--- a/esp32p4/src/usb_device/conf0.rs
+++ b/esp32p4/src/usb_device/conf0.rs
@@ -134,47 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("phy_sel", &format_args!("{}", self.phy_sel().bit()))
-            .field(
-                "exchg_pins_override",
-                &format_args!("{}", self.exchg_pins_override().bit()),
-            )
-            .field("exchg_pins", &format_args!("{}", self.exchg_pins().bit()))
-            .field("vrefh", &format_args!("{}", self.vrefh().bits()))
-            .field("vrefl", &format_args!("{}", self.vrefl().bits()))
-            .field(
-                "vref_override",
-                &format_args!("{}", self.vref_override().bit()),
-            )
-            .field(
-                "pad_pull_override",
-                &format_args!("{}", self.pad_pull_override().bit()),
-            )
-            .field("dp_pullup", &format_args!("{}", self.dp_pullup().bit()))
-            .field("dp_pulldown", &format_args!("{}", self.dp_pulldown().bit()))
-            .field("dm_pullup", &format_args!("{}", self.dm_pullup().bit()))
-            .field("dm_pulldown", &format_args!("{}", self.dm_pulldown().bit()))
-            .field(
-                "pullup_value",
-                &format_args!("{}", self.pullup_value().bit()),
-            )
-            .field(
-                "usb_pad_enable",
-                &format_args!("{}", self.usb_pad_enable().bit()),
-            )
-            .field(
-                "usb_jtag_bridge_en",
-                &format_args!("{}", self.usb_jtag_bridge_en().bit()),
-            )
+            .field("phy_sel", &self.phy_sel())
+            .field("exchg_pins_override", &self.exchg_pins_override())
+            .field("exchg_pins", &self.exchg_pins())
+            .field("vrefh", &self.vrefh())
+            .field("vrefl", &self.vrefl())
+            .field("vref_override", &self.vref_override())
+            .field("pad_pull_override", &self.pad_pull_override())
+            .field("dp_pullup", &self.dp_pullup())
+            .field("dp_pulldown", &self.dp_pulldown())
+            .field("dm_pullup", &self.dm_pullup())
+            .field("dm_pulldown", &self.dm_pulldown())
+            .field("pullup_value", &self.pullup_value())
+            .field("usb_pad_enable", &self.usb_pad_enable())
+            .field("usb_jtag_bridge_en", &self.usb_jtag_bridge_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Select internal/external PHY"]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/date.rs b/esp32p4/src/usb_device/date.rs
index 71da319938..b82f01a55d 100644
--- a/esp32p4/src/usb_device/date.rs
+++ b/esp32p4/src/usb_device/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32p4/src/usb_device/eco_cell_ctrl_48.rs b/esp32p4/src/usb_device/eco_cell_ctrl_48.rs
index a4dfc42597..d03188630b 100644
--- a/esp32p4/src/usb_device/eco_cell_ctrl_48.rs
+++ b/esp32p4/src/usb_device/eco_cell_ctrl_48.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_CELL_CTRL_48")
-            .field(
-                "rdn_result_48",
-                &format_args!("{}", self.rdn_result_48().bit()),
-            )
-            .field("rdn_ena_48", &format_args!("{}", self.rdn_ena_48().bit()))
+            .field("rdn_result_48", &self.rdn_result_48())
+            .field("rdn_ena_48", &self.rdn_ena_48())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_CELL_CTRL_48_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Reserved."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/eco_cell_ctrl_apb.rs b/esp32p4/src/usb_device/eco_cell_ctrl_apb.rs
index f469747a03..0d63af6bbb 100644
--- a/esp32p4/src/usb_device/eco_cell_ctrl_apb.rs
+++ b/esp32p4/src/usb_device/eco_cell_ctrl_apb.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_CELL_CTRL_APB")
-            .field(
-                "rdn_result_apb",
-                &format_args!("{}", self.rdn_result_apb().bit()),
-            )
-            .field("rdn_ena_apb", &format_args!("{}", self.rdn_ena_apb().bit()))
+            .field("rdn_result_apb", &self.rdn_result_apb())
+            .field("rdn_ena_apb", &self.rdn_ena_apb())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_CELL_CTRL_APB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Reserved."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/eco_high_48.rs b/esp32p4/src/usb_device/eco_high_48.rs
index b2299e0bce..a7aa11a2b3 100644
--- a/esp32p4/src/usb_device/eco_high_48.rs
+++ b/esp32p4/src/usb_device/eco_high_48.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_HIGH_48")
-            .field(
-                "rnd_eco_high_48",
-                &format_args!("{}", self.rnd_eco_high_48().bits()),
-            )
+            .field("rnd_eco_high_48", &self.rnd_eco_high_48())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_HIGH_48_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/eco_high_apb.rs b/esp32p4/src/usb_device/eco_high_apb.rs
index 1ed3d3bcfa..a2df027846 100644
--- a/esp32p4/src/usb_device/eco_high_apb.rs
+++ b/esp32p4/src/usb_device/eco_high_apb.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_HIGH_APB")
-            .field(
-                "rnd_eco_high_apb",
-                &format_args!("{}", self.rnd_eco_high_apb().bits()),
-            )
+            .field("rnd_eco_high_apb", &self.rnd_eco_high_apb())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_HIGH_APB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/eco_low_48.rs b/esp32p4/src/usb_device/eco_low_48.rs
index 93c9ed5f7f..39228504a3 100644
--- a/esp32p4/src/usb_device/eco_low_48.rs
+++ b/esp32p4/src/usb_device/eco_low_48.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_LOW_48")
-            .field(
-                "rnd_eco_low_48",
-                &format_args!("{}", self.rnd_eco_low_48().bits()),
-            )
+            .field("rnd_eco_low_48", &self.rnd_eco_low_48())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_LOW_48_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/eco_low_apb.rs b/esp32p4/src/usb_device/eco_low_apb.rs
index 6220223c7b..61d807b230 100644
--- a/esp32p4/src/usb_device/eco_low_apb.rs
+++ b/esp32p4/src/usb_device/eco_low_apb.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECO_LOW_APB")
-            .field(
-                "rnd_eco_low_apb",
-                &format_args!("{}", self.rnd_eco_low_apb().bits()),
-            )
+            .field("rnd_eco_low_apb", &self.rnd_eco_low_apb())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECO_LOW_APB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/ep1.rs b/esp32p4/src/usb_device/ep1.rs
index 92bed9b30d..d6030184bd 100644
--- a/esp32p4/src/usb_device/ep1.rs
+++ b/esp32p4/src/usb_device/ep1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EP1")
-            .field("rdwr_byte", &format_args!("{}", self.rdwr_byte().bits()))
+            .field("rdwr_byte", &self.rdwr_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/ep1_conf.rs b/esp32p4/src/usb_device/ep1_conf.rs
index c99b3b08f6..3534449ebc 100644
--- a/esp32p4/src/usb_device/ep1_conf.rs
+++ b/esp32p4/src/usb_device/ep1_conf.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EP1_CONF")
-            .field(
-                "serial_in_ep_data_free",
-                &format_args!("{}", self.serial_in_ep_data_free().bit()),
-            )
-            .field(
-                "serial_out_ep_data_avail",
-                &format_args!("{}", self.serial_out_ep_data_avail().bit()),
-            )
+            .field("serial_in_ep_data_free", &self.serial_in_ep_data_free())
+            .field("serial_out_ep_data_avail", &self.serial_out_ep_data_avail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EP1_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to indicate writing byte data to UART Tx FIFO is done."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/fram_num.rs b/esp32p4/src/usb_device/fram_num.rs
index ee7832b94b..555f25c409 100644
--- a/esp32p4/src/usb_device/fram_num.rs
+++ b/esp32p4/src/usb_device/fram_num.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FRAM_NUM")
-            .field(
-                "sof_frame_index",
-                &format_args!("{}", self.sof_frame_index().bits()),
-            )
+            .field("sof_frame_index", &self.sof_frame_index())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FRAM_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Last received SOF frame index register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fram_num::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FRAM_NUM_SPEC;
 impl crate::RegisterSpec for FRAM_NUM_SPEC {
diff --git a/esp32p4/src/usb_device/get_line_code_w0.rs b/esp32p4/src/usb_device/get_line_code_w0.rs
index d4deae05f4..374fc89555 100644
--- a/esp32p4/src/usb_device/get_line_code_w0.rs
+++ b/esp32p4/src/usb_device/get_line_code_w0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GET_LINE_CODE_W0")
-            .field(
-                "get_dw_dte_rate",
-                &format_args!("{}", self.get_dw_dte_rate().bits()),
-            )
+            .field("get_dw_dte_rate", &self.get_dw_dte_rate())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GET_LINE_CODE_W0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The value of dwDTERate set by software which is requested by GET_LINE_CODING command."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/get_line_code_w1.rs b/esp32p4/src/usb_device/get_line_code_w1.rs
index 5ad3080523..d7ae6488a4 100644
--- a/esp32p4/src/usb_device/get_line_code_w1.rs
+++ b/esp32p4/src/usb_device/get_line_code_w1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GET_LINE_CODE_W1")
-            .field(
-                "get_bdata_bits",
-                &format_args!("{}", self.get_bdata_bits().bits()),
-            )
-            .field(
-                "get_bparity_type",
-                &format_args!("{}", self.get_bparity_type().bits()),
-            )
-            .field(
-                "get_bchar_format",
-                &format_args!("{}", self.get_bchar_format().bits()),
-            )
+            .field("get_bdata_bits", &self.get_bdata_bits())
+            .field("get_bparity_type", &self.get_bparity_type())
+            .field("get_bchar_format", &self.get_bchar_format())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GET_LINE_CODE_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value of bCharFormat set by software which is requested by GET_LINE_CODING command."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/in_ep0_st.rs b/esp32p4/src/usb_device/in_ep0_st.rs
index cdba70f4ca..5e23d52fee 100644
--- a/esp32p4/src/usb_device/in_ep0_st.rs
+++ b/esp32p4/src/usb_device/in_ep0_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP0_ST")
-            .field(
-                "in_ep0_state",
-                &format_args!("{}", self.in_ep0_state().bits()),
-            )
-            .field(
-                "in_ep0_wr_addr",
-                &format_args!("{}", self.in_ep0_wr_addr().bits()),
-            )
-            .field(
-                "in_ep0_rd_addr",
-                &format_args!("{}", self.in_ep0_rd_addr().bits()),
-            )
+            .field("in_ep0_state", &self.in_ep0_state())
+            .field("in_ep0_wr_addr", &self.in_ep0_wr_addr())
+            .field("in_ep0_rd_addr", &self.in_ep0_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP0_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Control IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep0_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP0_ST_SPEC;
 impl crate::RegisterSpec for IN_EP0_ST_SPEC {
diff --git a/esp32p4/src/usb_device/in_ep1_st.rs b/esp32p4/src/usb_device/in_ep1_st.rs
index c4bbb2bf6b..c1350a8ce8 100644
--- a/esp32p4/src/usb_device/in_ep1_st.rs
+++ b/esp32p4/src/usb_device/in_ep1_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP1_ST")
-            .field(
-                "in_ep1_state",
-                &format_args!("{}", self.in_ep1_state().bits()),
-            )
-            .field(
-                "in_ep1_wr_addr",
-                &format_args!("{}", self.in_ep1_wr_addr().bits()),
-            )
-            .field(
-                "in_ep1_rd_addr",
-                &format_args!("{}", self.in_ep1_rd_addr().bits()),
-            )
+            .field("in_ep1_state", &self.in_ep1_state())
+            .field("in_ep1_wr_addr", &self.in_ep1_wr_addr())
+            .field("in_ep1_rd_addr", &self.in_ep1_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP1_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CDC-ACM IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep1_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP1_ST_SPEC;
 impl crate::RegisterSpec for IN_EP1_ST_SPEC {
diff --git a/esp32p4/src/usb_device/in_ep2_st.rs b/esp32p4/src/usb_device/in_ep2_st.rs
index d7dd32917d..15d0dbaa8d 100644
--- a/esp32p4/src/usb_device/in_ep2_st.rs
+++ b/esp32p4/src/usb_device/in_ep2_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP2_ST")
-            .field(
-                "in_ep2_state",
-                &format_args!("{}", self.in_ep2_state().bits()),
-            )
-            .field(
-                "in_ep2_wr_addr",
-                &format_args!("{}", self.in_ep2_wr_addr().bits()),
-            )
-            .field(
-                "in_ep2_rd_addr",
-                &format_args!("{}", self.in_ep2_rd_addr().bits()),
-            )
+            .field("in_ep2_state", &self.in_ep2_state())
+            .field("in_ep2_wr_addr", &self.in_ep2_wr_addr())
+            .field("in_ep2_rd_addr", &self.in_ep2_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP2_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CDC-ACM interrupt IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep2_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP2_ST_SPEC;
 impl crate::RegisterSpec for IN_EP2_ST_SPEC {
diff --git a/esp32p4/src/usb_device/in_ep3_st.rs b/esp32p4/src/usb_device/in_ep3_st.rs
index c36ea05f61..943dbe3d1c 100644
--- a/esp32p4/src/usb_device/in_ep3_st.rs
+++ b/esp32p4/src/usb_device/in_ep3_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP3_ST")
-            .field(
-                "in_ep3_state",
-                &format_args!("{}", self.in_ep3_state().bits()),
-            )
-            .field(
-                "in_ep3_wr_addr",
-                &format_args!("{}", self.in_ep3_wr_addr().bits()),
-            )
-            .field(
-                "in_ep3_rd_addr",
-                &format_args!("{}", self.in_ep3_rd_addr().bits()),
-            )
+            .field("in_ep3_state", &self.in_ep3_state())
+            .field("in_ep3_wr_addr", &self.in_ep3_wr_addr())
+            .field("in_ep3_rd_addr", &self.in_ep3_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP3_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "JTAG IN endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep3_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP3_ST_SPEC;
 impl crate::RegisterSpec for IN_EP3_ST_SPEC {
diff --git a/esp32p4/src/usb_device/int_ena.rs b/esp32p4/src/usb_device/int_ena.rs
index 7ed38f620a..e3d498b167 100644
--- a/esp32p4/src/usb_device/int_ena.rs
+++ b/esp32p4/src/usb_device/int_ena.rs
@@ -152,58 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "jtag_in_flush",
-                &format_args!("{}", self.jtag_in_flush().bit()),
-            )
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field(
-                "serial_out_recv_pkt",
-                &format_args!("{}", self.serial_out_recv_pkt().bit()),
-            )
-            .field(
-                "serial_in_empty",
-                &format_args!("{}", self.serial_in_empty().bit()),
-            )
-            .field("pid_err", &format_args!("{}", self.pid_err().bit()))
-            .field("crc5_err", &format_args!("{}", self.crc5_err().bit()))
-            .field("crc16_err", &format_args!("{}", self.crc16_err().bit()))
-            .field("stuff_err", &format_args!("{}", self.stuff_err().bit()))
-            .field(
-                "in_token_rec_in_ep1",
-                &format_args!("{}", self.in_token_rec_in_ep1().bit()),
-            )
-            .field(
-                "usb_bus_reset",
-                &format_args!("{}", self.usb_bus_reset().bit()),
-            )
-            .field(
-                "out_ep1_zero_payload",
-                &format_args!("{}", self.out_ep1_zero_payload().bit()),
-            )
-            .field(
-                "out_ep2_zero_payload",
-                &format_args!("{}", self.out_ep2_zero_payload().bit()),
-            )
-            .field("rts_chg", &format_args!("{}", self.rts_chg().bit()))
-            .field("dtr_chg", &format_args!("{}", self.dtr_chg().bit()))
-            .field(
-                "get_line_code",
-                &format_args!("{}", self.get_line_code().bit()),
-            )
-            .field(
-                "set_line_code",
-                &format_args!("{}", self.set_line_code().bit()),
-            )
+            .field("jtag_in_flush", &self.jtag_in_flush())
+            .field("sof", &self.sof())
+            .field("serial_out_recv_pkt", &self.serial_out_recv_pkt())
+            .field("serial_in_empty", &self.serial_in_empty())
+            .field("pid_err", &self.pid_err())
+            .field("crc5_err", &self.crc5_err())
+            .field("crc16_err", &self.crc16_err())
+            .field("stuff_err", &self.stuff_err())
+            .field("in_token_rec_in_ep1", &self.in_token_rec_in_ep1())
+            .field("usb_bus_reset", &self.usb_bus_reset())
+            .field("out_ep1_zero_payload", &self.out_ep1_zero_payload())
+            .field("out_ep2_zero_payload", &self.out_ep2_zero_payload())
+            .field("rts_chg", &self.rts_chg())
+            .field("dtr_chg", &self.dtr_chg())
+            .field("get_line_code", &self.get_line_code())
+            .field("set_line_code", &self.set_line_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/int_raw.rs b/esp32p4/src/usb_device/int_raw.rs
index fcb2db63ff..bc22e1a795 100644
--- a/esp32p4/src/usb_device/int_raw.rs
+++ b/esp32p4/src/usb_device/int_raw.rs
@@ -152,58 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "jtag_in_flush",
-                &format_args!("{}", self.jtag_in_flush().bit()),
-            )
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field(
-                "serial_out_recv_pkt",
-                &format_args!("{}", self.serial_out_recv_pkt().bit()),
-            )
-            .field(
-                "serial_in_empty",
-                &format_args!("{}", self.serial_in_empty().bit()),
-            )
-            .field("pid_err", &format_args!("{}", self.pid_err().bit()))
-            .field("crc5_err", &format_args!("{}", self.crc5_err().bit()))
-            .field("crc16_err", &format_args!("{}", self.crc16_err().bit()))
-            .field("stuff_err", &format_args!("{}", self.stuff_err().bit()))
-            .field(
-                "in_token_rec_in_ep1",
-                &format_args!("{}", self.in_token_rec_in_ep1().bit()),
-            )
-            .field(
-                "usb_bus_reset",
-                &format_args!("{}", self.usb_bus_reset().bit()),
-            )
-            .field(
-                "out_ep1_zero_payload",
-                &format_args!("{}", self.out_ep1_zero_payload().bit()),
-            )
-            .field(
-                "out_ep2_zero_payload",
-                &format_args!("{}", self.out_ep2_zero_payload().bit()),
-            )
-            .field("rts_chg", &format_args!("{}", self.rts_chg().bit()))
-            .field("dtr_chg", &format_args!("{}", self.dtr_chg().bit()))
-            .field(
-                "get_line_code",
-                &format_args!("{}", self.get_line_code().bit()),
-            )
-            .field(
-                "set_line_code",
-                &format_args!("{}", self.set_line_code().bit()),
-            )
+            .field("jtag_in_flush", &self.jtag_in_flush())
+            .field("sof", &self.sof())
+            .field("serial_out_recv_pkt", &self.serial_out_recv_pkt())
+            .field("serial_in_empty", &self.serial_in_empty())
+            .field("pid_err", &self.pid_err())
+            .field("crc5_err", &self.crc5_err())
+            .field("crc16_err", &self.crc16_err())
+            .field("stuff_err", &self.stuff_err())
+            .field("in_token_rec_in_ep1", &self.in_token_rec_in_ep1())
+            .field("usb_bus_reset", &self.usb_bus_reset())
+            .field("out_ep1_zero_payload", &self.out_ep1_zero_payload())
+            .field("out_ep2_zero_payload", &self.out_ep2_zero_payload())
+            .field("rts_chg", &self.rts_chg())
+            .field("dtr_chg", &self.dtr_chg())
+            .field("get_line_code", &self.get_line_code())
+            .field("set_line_code", &self.set_line_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/int_st.rs b/esp32p4/src/usb_device/int_st.rs
index ec83c07732..d968a2587e 100644
--- a/esp32p4/src/usb_device/int_st.rs
+++ b/esp32p4/src/usb_device/int_st.rs
@@ -118,58 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "jtag_in_flush",
-                &format_args!("{}", self.jtag_in_flush().bit()),
-            )
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field(
-                "serial_out_recv_pkt",
-                &format_args!("{}", self.serial_out_recv_pkt().bit()),
-            )
-            .field(
-                "serial_in_empty",
-                &format_args!("{}", self.serial_in_empty().bit()),
-            )
-            .field("pid_err", &format_args!("{}", self.pid_err().bit()))
-            .field("crc5_err", &format_args!("{}", self.crc5_err().bit()))
-            .field("crc16_err", &format_args!("{}", self.crc16_err().bit()))
-            .field("stuff_err", &format_args!("{}", self.stuff_err().bit()))
-            .field(
-                "in_token_rec_in_ep1",
-                &format_args!("{}", self.in_token_rec_in_ep1().bit()),
-            )
-            .field(
-                "usb_bus_reset",
-                &format_args!("{}", self.usb_bus_reset().bit()),
-            )
-            .field(
-                "out_ep1_zero_payload",
-                &format_args!("{}", self.out_ep1_zero_payload().bit()),
-            )
-            .field(
-                "out_ep2_zero_payload",
-                &format_args!("{}", self.out_ep2_zero_payload().bit()),
-            )
-            .field("rts_chg", &format_args!("{}", self.rts_chg().bit()))
-            .field("dtr_chg", &format_args!("{}", self.dtr_chg().bit()))
-            .field(
-                "get_line_code",
-                &format_args!("{}", self.get_line_code().bit()),
-            )
-            .field(
-                "set_line_code",
-                &format_args!("{}", self.set_line_code().bit()),
-            )
+            .field("jtag_in_flush", &self.jtag_in_flush())
+            .field("sof", &self.sof())
+            .field("serial_out_recv_pkt", &self.serial_out_recv_pkt())
+            .field("serial_in_empty", &self.serial_in_empty())
+            .field("pid_err", &self.pid_err())
+            .field("crc5_err", &self.crc5_err())
+            .field("crc16_err", &self.crc16_err())
+            .field("stuff_err", &self.stuff_err())
+            .field("in_token_rec_in_ep1", &self.in_token_rec_in_ep1())
+            .field("usb_bus_reset", &self.usb_bus_reset())
+            .field("out_ep1_zero_payload", &self.out_ep1_zero_payload())
+            .field("out_ep2_zero_payload", &self.out_ep2_zero_payload())
+            .field("rts_chg", &self.rts_chg())
+            .field("dtr_chg", &self.dtr_chg())
+            .field("get_line_code", &self.get_line_code())
+            .field("set_line_code", &self.set_line_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32p4/src/usb_device/jfifo_st.rs b/esp32p4/src/usb_device/jfifo_st.rs
index 09ed48770d..810e3b4bec 100644
--- a/esp32p4/src/usb_device/jfifo_st.rs
+++ b/esp32p4/src/usb_device/jfifo_st.rs
@@ -68,47 +68,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("JFIFO_ST")
-            .field(
-                "in_fifo_cnt",
-                &format_args!("{}", self.in_fifo_cnt().bits()),
-            )
-            .field(
-                "in_fifo_empty",
-                &format_args!("{}", self.in_fifo_empty().bit()),
-            )
-            .field(
-                "in_fifo_full",
-                &format_args!("{}", self.in_fifo_full().bit()),
-            )
-            .field(
-                "out_fifo_cnt",
-                &format_args!("{}", self.out_fifo_cnt().bits()),
-            )
-            .field(
-                "out_fifo_empty",
-                &format_args!("{}", self.out_fifo_empty().bit()),
-            )
-            .field(
-                "out_fifo_full",
-                &format_args!("{}", self.out_fifo_full().bit()),
-            )
-            .field(
-                "in_fifo_reset",
-                &format_args!("{}", self.in_fifo_reset().bit()),
-            )
-            .field(
-                "out_fifo_reset",
-                &format_args!("{}", self.out_fifo_reset().bit()),
-            )
+            .field("in_fifo_cnt", &self.in_fifo_cnt())
+            .field("in_fifo_empty", &self.in_fifo_empty())
+            .field("in_fifo_full", &self.in_fifo_full())
+            .field("out_fifo_cnt", &self.out_fifo_cnt())
+            .field("out_fifo_empty", &self.out_fifo_empty())
+            .field("out_fifo_full", &self.out_fifo_full())
+            .field("in_fifo_reset", &self.in_fifo_reset())
+            .field("out_fifo_reset", &self.out_fifo_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<JFIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - Write 1 to reset JTAG in fifo."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/mem_conf.rs b/esp32p4/src/usb_device/mem_conf.rs
index 682d7c5986..b96d8a21a7 100644
--- a/esp32p4/src/usb_device/mem_conf.rs
+++ b/esp32p4/src/usb_device/mem_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field("usb_mem_pd", &format_args!("{}", self.usb_mem_pd().bit()))
-            .field(
-                "usb_mem_clk_en",
-                &format_args!("{}", self.usb_mem_clk_en().bit()),
-            )
+            .field("usb_mem_pd", &self.usb_mem_pd())
+            .field("usb_mem_clk_en", &self.usb_mem_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: power down usb memory."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/misc_conf.rs b/esp32p4/src/usb_device/misc_conf.rs
index 22aeb01318..096db71403 100644
--- a/esp32p4/src/usb_device/misc_conf.rs
+++ b/esp32p4/src/usb_device/misc_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC_CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/out_ep0_st.rs b/esp32p4/src/usb_device/out_ep0_st.rs
index beccea168f..9778c6853e 100644
--- a/esp32p4/src/usb_device/out_ep0_st.rs
+++ b/esp32p4/src/usb_device/out_ep0_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EP0_ST")
-            .field(
-                "out_ep0_state",
-                &format_args!("{}", self.out_ep0_state().bits()),
-            )
-            .field(
-                "out_ep0_wr_addr",
-                &format_args!("{}", self.out_ep0_wr_addr().bits()),
-            )
-            .field(
-                "out_ep0_rd_addr",
-                &format_args!("{}", self.out_ep0_rd_addr().bits()),
-            )
+            .field("out_ep0_state", &self.out_ep0_state())
+            .field("out_ep0_wr_addr", &self.out_ep0_wr_addr())
+            .field("out_ep0_rd_addr", &self.out_ep0_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EP0_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Control OUT endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep0_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EP0_ST_SPEC;
 impl crate::RegisterSpec for OUT_EP0_ST_SPEC {
diff --git a/esp32p4/src/usb_device/out_ep1_st.rs b/esp32p4/src/usb_device/out_ep1_st.rs
index 81d1afe476..d1fdcebd8e 100644
--- a/esp32p4/src/usb_device/out_ep1_st.rs
+++ b/esp32p4/src/usb_device/out_ep1_st.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EP1_ST")
-            .field(
-                "out_ep1_state",
-                &format_args!("{}", self.out_ep1_state().bits()),
-            )
-            .field(
-                "out_ep1_wr_addr",
-                &format_args!("{}", self.out_ep1_wr_addr().bits()),
-            )
-            .field(
-                "out_ep1_rd_addr",
-                &format_args!("{}", self.out_ep1_rd_addr().bits()),
-            )
-            .field(
-                "out_ep1_rec_data_cnt",
-                &format_args!("{}", self.out_ep1_rec_data_cnt().bits()),
-            )
+            .field("out_ep1_state", &self.out_ep1_state())
+            .field("out_ep1_wr_addr", &self.out_ep1_wr_addr())
+            .field("out_ep1_rd_addr", &self.out_ep1_rd_addr())
+            .field("out_ep1_rec_data_cnt", &self.out_ep1_rec_data_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EP1_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "CDC-ACM OUT endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep1_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EP1_ST_SPEC;
 impl crate::RegisterSpec for OUT_EP1_ST_SPEC {
diff --git a/esp32p4/src/usb_device/out_ep2_st.rs b/esp32p4/src/usb_device/out_ep2_st.rs
index 8e7c84db34..f4bfad5198 100644
--- a/esp32p4/src/usb_device/out_ep2_st.rs
+++ b/esp32p4/src/usb_device/out_ep2_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EP2_ST")
-            .field(
-                "out_ep2_state",
-                &format_args!("{}", self.out_ep2_state().bits()),
-            )
-            .field(
-                "out_ep2_wr_addr",
-                &format_args!("{}", self.out_ep2_wr_addr().bits()),
-            )
-            .field(
-                "out_ep2_rd_addr",
-                &format_args!("{}", self.out_ep2_rd_addr().bits()),
-            )
+            .field("out_ep2_state", &self.out_ep2_state())
+            .field("out_ep2_wr_addr", &self.out_ep2_wr_addr())
+            .field("out_ep2_rd_addr", &self.out_ep2_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EP2_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "JTAG OUT endpoint status information.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep2_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EP2_ST_SPEC;
 impl crate::RegisterSpec for OUT_EP2_ST_SPEC {
diff --git a/esp32p4/src/usb_device/ser_afifo_config.rs b/esp32p4/src/usb_device/ser_afifo_config.rs
index f1fd3f981b..dad03c2716 100644
--- a/esp32p4/src/usb_device/ser_afifo_config.rs
+++ b/esp32p4/src/usb_device/ser_afifo_config.rs
@@ -58,39 +58,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SER_AFIFO_CONFIG")
-            .field(
-                "serial_in_afifo_reset_wr",
-                &format_args!("{}", self.serial_in_afifo_reset_wr().bit()),
-            )
-            .field(
-                "serial_in_afifo_reset_rd",
-                &format_args!("{}", self.serial_in_afifo_reset_rd().bit()),
-            )
+            .field("serial_in_afifo_reset_wr", &self.serial_in_afifo_reset_wr())
+            .field("serial_in_afifo_reset_rd", &self.serial_in_afifo_reset_rd())
             .field(
                 "serial_out_afifo_reset_wr",
-                &format_args!("{}", self.serial_out_afifo_reset_wr().bit()),
+                &self.serial_out_afifo_reset_wr(),
             )
             .field(
                 "serial_out_afifo_reset_rd",
-                &format_args!("{}", self.serial_out_afifo_reset_rd().bit()),
-            )
-            .field(
-                "serial_out_afifo_rempty",
-                &format_args!("{}", self.serial_out_afifo_rempty().bit()),
-            )
-            .field(
-                "serial_in_afifo_wfull",
-                &format_args!("{}", self.serial_in_afifo_wfull().bit()),
+                &self.serial_out_afifo_reset_rd(),
             )
+            .field("serial_out_afifo_rempty", &self.serial_out_afifo_rempty())
+            .field("serial_in_afifo_wfull", &self.serial_in_afifo_wfull())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SER_AFIFO_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1 to reset CDC_ACM IN async FIFO write clock domain."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/set_line_code_w0.rs b/esp32p4/src/usb_device/set_line_code_w0.rs
index c604ef35cd..5fbf6698b5 100644
--- a/esp32p4/src/usb_device/set_line_code_w0.rs
+++ b/esp32p4/src/usb_device/set_line_code_w0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SET_LINE_CODE_W0")
-            .field(
-                "dw_dte_rate",
-                &format_args!("{}", self.dw_dte_rate().bits()),
-            )
+            .field("dw_dte_rate", &self.dw_dte_rate())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SET_LINE_CODE_W0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "W0 of SET_LINE_CODING command.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set_line_code_w0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SET_LINE_CODE_W0_SPEC;
 impl crate::RegisterSpec for SET_LINE_CODE_W0_SPEC {
diff --git a/esp32p4/src/usb_device/set_line_code_w1.rs b/esp32p4/src/usb_device/set_line_code_w1.rs
index 0af91af4b5..214022604e 100644
--- a/esp32p4/src/usb_device/set_line_code_w1.rs
+++ b/esp32p4/src/usb_device/set_line_code_w1.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SET_LINE_CODE_W1")
-            .field(
-                "bchar_format",
-                &format_args!("{}", self.bchar_format().bits()),
-            )
-            .field(
-                "bparity_type",
-                &format_args!("{}", self.bparity_type().bits()),
-            )
-            .field("bdata_bits", &format_args!("{}", self.bdata_bits().bits()))
+            .field("bchar_format", &self.bchar_format())
+            .field("bparity_type", &self.bparity_type())
+            .field("bdata_bits", &self.bdata_bits())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SET_LINE_CODE_W1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "W1 of SET_LINE_CODING command.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set_line_code_w1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SET_LINE_CODE_W1_SPEC;
 impl crate::RegisterSpec for SET_LINE_CODE_W1_SPEC {
diff --git a/esp32p4/src/usb_device/sram_ctrl.rs b/esp32p4/src/usb_device/sram_ctrl.rs
index 6eb1278bb5..34cac8233a 100644
--- a/esp32p4/src/usb_device/sram_ctrl.rs
+++ b/esp32p4/src/usb_device/sram_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_CTRL")
-            .field(
-                "mem_aux_ctrl",
-                &format_args!("{}", self.mem_aux_ctrl().bits()),
-            )
+            .field("mem_aux_ctrl", &self.mem_aux_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Control signals"]
     #[inline(always)]
diff --git a/esp32p4/src/usb_device/test.rs b/esp32p4/src/usb_device/test.rs
index 031148c329..10c7308a91 100644
--- a/esp32p4/src/usb_device/test.rs
+++ b/esp32p4/src/usb_device/test.rs
@@ -65,22 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEST")
-            .field("test_enable", &format_args!("{}", self.test_enable().bit()))
-            .field("test_usb_oe", &format_args!("{}", self.test_usb_oe().bit()))
-            .field("test_tx_dp", &format_args!("{}", self.test_tx_dp().bit()))
-            .field("test_tx_dm", &format_args!("{}", self.test_tx_dm().bit()))
-            .field("test_rx_rcv", &format_args!("{}", self.test_rx_rcv().bit()))
-            .field("test_rx_dp", &format_args!("{}", self.test_rx_dp().bit()))
-            .field("test_rx_dm", &format_args!("{}", self.test_rx_dm().bit()))
+            .field("test_enable", &self.test_enable())
+            .field("test_usb_oe", &self.test_usb_oe())
+            .field("test_tx_dp", &self.test_tx_dp())
+            .field("test_tx_dm", &self.test_tx_dm())
+            .field("test_rx_rcv", &self.test_rx_rcv())
+            .field("test_rx_dp", &self.test_rx_dp())
+            .field("test_rx_dm", &self.test_rx_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable test of the USB pad"]
     #[inline(always)]
diff --git a/esp32p4/src/usb_wrap/date.rs b/esp32p4/src/usb_wrap/date.rs
index 6206a7d8b0..351949d070 100644
--- a/esp32p4/src/usb_wrap/date.rs
+++ b/esp32p4/src/usb_wrap/date.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "usb_wrap_date",
-                &format_args!("{}", self.usb_wrap_date().bits()),
-            )
+            .field("usb_wrap_date", &self.usb_wrap_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Date register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DATE_SPEC;
 impl crate::RegisterSpec for DATE_SPEC {
diff --git a/esp32p4/src/usb_wrap/otg_conf.rs b/esp32p4/src/usb_wrap/otg_conf.rs
index d432f5a0bb..760674034f 100644
--- a/esp32p4/src/usb_wrap/otg_conf.rs
+++ b/esp32p4/src/usb_wrap/otg_conf.rs
@@ -206,76 +206,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OTG_CONF")
-            .field(
-                "srp_sessend_override",
-                &format_args!("{}", self.srp_sessend_override().bit()),
-            )
-            .field(
-                "srp_sessend_value",
-                &format_args!("{}", self.srp_sessend_value().bit()),
-            )
-            .field("phy_sel", &format_args!("{}", self.phy_sel().bit()))
-            .field(
-                "dfifo_force_pd",
-                &format_args!("{}", self.dfifo_force_pd().bit()),
-            )
-            .field(
-                "dbnce_fltr_bypass",
-                &format_args!("{}", self.dbnce_fltr_bypass().bit()),
-            )
-            .field(
-                "exchg_pins_override",
-                &format_args!("{}", self.exchg_pins_override().bit()),
-            )
-            .field("exchg_pins", &format_args!("{}", self.exchg_pins().bit()))
-            .field("vrefh", &format_args!("{}", self.vrefh().bits()))
-            .field("vrefl", &format_args!("{}", self.vrefl().bits()))
-            .field(
-                "vref_override",
-                &format_args!("{}", self.vref_override().bit()),
-            )
-            .field(
-                "pad_pull_override",
-                &format_args!("{}", self.pad_pull_override().bit()),
-            )
-            .field("dp_pullup", &format_args!("{}", self.dp_pullup().bit()))
-            .field("dp_pulldown", &format_args!("{}", self.dp_pulldown().bit()))
-            .field("dm_pullup", &format_args!("{}", self.dm_pullup().bit()))
-            .field("dm_pulldown", &format_args!("{}", self.dm_pulldown().bit()))
-            .field(
-                "pullup_value",
-                &format_args!("{}", self.pullup_value().bit()),
-            )
-            .field(
-                "usb_pad_enable",
-                &format_args!("{}", self.usb_pad_enable().bit()),
-            )
-            .field(
-                "ahb_clk_force_on",
-                &format_args!("{}", self.ahb_clk_force_on().bit()),
-            )
-            .field(
-                "phy_clk_force_on",
-                &format_args!("{}", self.phy_clk_force_on().bit()),
-            )
-            .field(
-                "phy_tx_edge_sel",
-                &format_args!("{}", self.phy_tx_edge_sel().bit()),
-            )
-            .field(
-                "dfifo_force_pu",
-                &format_args!("{}", self.dfifo_force_pu().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("srp_sessend_override", &self.srp_sessend_override())
+            .field("srp_sessend_value", &self.srp_sessend_value())
+            .field("phy_sel", &self.phy_sel())
+            .field("dfifo_force_pd", &self.dfifo_force_pd())
+            .field("dbnce_fltr_bypass", &self.dbnce_fltr_bypass())
+            .field("exchg_pins_override", &self.exchg_pins_override())
+            .field("exchg_pins", &self.exchg_pins())
+            .field("vrefh", &self.vrefh())
+            .field("vrefl", &self.vrefl())
+            .field("vref_override", &self.vref_override())
+            .field("pad_pull_override", &self.pad_pull_override())
+            .field("dp_pullup", &self.dp_pullup())
+            .field("dp_pulldown", &self.dp_pulldown())
+            .field("dm_pullup", &self.dm_pullup())
+            .field("dm_pulldown", &self.dm_pulldown())
+            .field("pullup_value", &self.pullup_value())
+            .field("usb_pad_enable", &self.usb_pad_enable())
+            .field("ahb_clk_force_on", &self.ahb_clk_force_on())
+            .field("phy_clk_force_on", &self.phy_clk_force_on())
+            .field("phy_tx_edge_sel", &self.phy_tx_edge_sel())
+            .field("dfifo_force_pu", &self.dfifo_force_pu())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OTG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input, 1'b1: the signal is controlled by the software."]
     #[inline(always)]
diff --git a/esp32p4/src/usb_wrap/test_conf.rs b/esp32p4/src/usb_wrap/test_conf.rs
index 5196108144..0c78b77be0 100644
--- a/esp32p4/src/usb_wrap/test_conf.rs
+++ b/esp32p4/src/usb_wrap/test_conf.rs
@@ -65,22 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEST_CONF")
-            .field("test_enable", &format_args!("{}", self.test_enable().bit()))
-            .field("test_usb_oe", &format_args!("{}", self.test_usb_oe().bit()))
-            .field("test_tx_dp", &format_args!("{}", self.test_tx_dp().bit()))
-            .field("test_tx_dm", &format_args!("{}", self.test_tx_dm().bit()))
-            .field("test_rx_rcv", &format_args!("{}", self.test_rx_rcv().bit()))
-            .field("test_rx_dp", &format_args!("{}", self.test_rx_dp().bit()))
-            .field("test_rx_dm", &format_args!("{}", self.test_rx_dm().bit()))
+            .field("test_enable", &self.test_enable())
+            .field("test_usb_oe", &self.test_usb_oe())
+            .field("test_tx_dp", &self.test_tx_dp())
+            .field("test_tx_dm", &self.test_tx_dm())
+            .field("test_rx_rcv", &self.test_rx_rcv())
+            .field("test_rx_dp", &self.test_rx_dp())
+            .field("test_rx_dm", &self.test_rx_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable test of the USB pad."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/generic.rs b/esp32s2-ulp/src/generic.rs
index a2ae6aa053..45ebed16c4 100644
--- a/esp32s2-ulp/src/generic.rs
+++ b/esp32s2-ulp/src/generic.rs
@@ -48,7 +48,7 @@ pub trait RegisterSpec {
 #[doc = " Raw field type"]
 pub trait FieldSpec: Sized {
     #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
-    type Ux: Copy + PartialEq + From<Self>;
+    type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
 }
 #[doc = " Marker for fields with fixed values"]
 pub trait IsEnum: FieldSpec {}
@@ -237,6 +237,14 @@ impl<REG: Readable + Writable> Reg<REG> {
         );
     }
 }
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
 #[doc(hidden)]
 pub mod raw;
 #[doc = " Register reader."]
@@ -302,6 +310,11 @@ impl<FI: FieldSpec> FieldReader<FI> {
         self.bits
     }
 }
+impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 impl<FI> PartialEq<FI> for FieldReader<FI>
 where
     FI: FieldSpec + Copy,
@@ -338,10 +351,21 @@ impl<FI> BitReader<FI> {
         self.bit()
     }
 }
+impl<FI> core::fmt::Debug for BitReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 #[doc = " Marker for register/field writers which can take any value of specified width"]
 pub struct Safe;
 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
 pub struct Unsafe;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct Range<const MIN: u64, const MAX: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeFrom<const MIN: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeTo<const MAX: u64>;
 #[doc = " Write field Proxy"]
 pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
     raw::FieldWriter<'a, REG, WI, FI, Safety>;
@@ -393,6 +417,58 @@ where
         unsafe { self.bits(value) }
     }
 }
+impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
+    FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN && value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
 impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
diff --git a/esp32s2-ulp/src/lib.rs b/esp32s2-ulp/src/lib.rs
index 50614e2d2f..480dfa59a4 100644
--- a/esp32s2-ulp/src/lib.rs
+++ b/esp32s2-ulp/src/lib.rs
@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32-S2-ULP microcontrollers (generated using svd2rust v0.33.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32-S2-ULP microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
diff --git a/esp32s2-ulp/src/rtc_cntl/cocpu_ctrl.rs b/esp32s2-ulp/src/rtc_cntl/cocpu_ctrl.rs
index fcfa60963e..466b969657 100644
--- a/esp32s2-ulp/src/rtc_cntl/cocpu_ctrl.rs
+++ b/esp32s2-ulp/src/rtc_cntl/cocpu_ctrl.rs
@@ -91,42 +91,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COCPU_CTRL")
-            .field(
-                "cocpu_clk_fo",
-                &format_args!("{}", self.cocpu_clk_fo().bit()),
-            )
-            .field(
-                "cocpu_start_2_reset_dis",
-                &format_args!("{}", self.cocpu_start_2_reset_dis().bits()),
-            )
-            .field(
-                "cocpu_start_2_intr_en",
-                &format_args!("{}", self.cocpu_start_2_intr_en().bits()),
-            )
-            .field("cocpu_shut", &format_args!("{}", self.cocpu_shut().bit()))
-            .field(
-                "cocpu_shut_2_clk_dis",
-                &format_args!("{}", self.cocpu_shut_2_clk_dis().bits()),
-            )
-            .field(
-                "cocpu_shut_reset_en",
-                &format_args!("{}", self.cocpu_shut_reset_en().bit()),
-            )
-            .field("cocpu_sel", &format_args!("{}", self.cocpu_sel().bit()))
-            .field(
-                "cocpu_done_force",
-                &format_args!("{}", self.cocpu_done_force().bit()),
-            )
-            .field("cocpu_done", &format_args!("{}", self.cocpu_done().bit()))
+            .field("cocpu_clk_fo", &self.cocpu_clk_fo())
+            .field("cocpu_start_2_reset_dis", &self.cocpu_start_2_reset_dis())
+            .field("cocpu_start_2_intr_en", &self.cocpu_start_2_intr_en())
+            .field("cocpu_shut", &self.cocpu_shut())
+            .field("cocpu_shut_2_clk_dis", &self.cocpu_shut_2_clk_dis())
+            .field("cocpu_shut_reset_en", &self.cocpu_shut_reset_en())
+            .field("cocpu_sel", &self.cocpu_sel())
+            .field("cocpu_done_force", &self.cocpu_done_force())
+            .field("cocpu_done", &self.cocpu_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COCPU_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ULP-RISCV clock force on"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_cntl/ulp_cp_ctrl.rs b/esp32s2-ulp/src/rtc_cntl/ulp_cp_ctrl.rs
index dbc87c201a..694cedbf34 100644
--- a/esp32s2-ulp/src/rtc_cntl/ulp_cp_ctrl.rs
+++ b/esp32s2-ulp/src/rtc_cntl/ulp_cp_ctrl.rs
@@ -64,39 +64,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_CTRL")
-            .field(
-                "ulp_cp_mem_addr_init",
-                &format_args!("{}", self.ulp_cp_mem_addr_init().bits()),
-            )
-            .field(
-                "ulp_cp_mem_addr_size",
-                &format_args!("{}", self.ulp_cp_mem_addr_size().bits()),
-            )
-            .field(
-                "ulp_cp_clk_fo",
-                &format_args!("{}", self.ulp_cp_clk_fo().bit()),
-            )
-            .field(
-                "ulp_cp_reset",
-                &format_args!("{}", self.ulp_cp_reset().bit()),
-            )
-            .field(
-                "ulp_cp_force_start_top",
-                &format_args!("{}", self.ulp_cp_force_start_top().bit()),
-            )
-            .field(
-                "ulp_cp_start_top",
-                &format_args!("{}", self.ulp_cp_start_top().bit()),
-            )
+            .field("ulp_cp_mem_addr_init", &self.ulp_cp_mem_addr_init())
+            .field("ulp_cp_mem_addr_size", &self.ulp_cp_mem_addr_size())
+            .field("ulp_cp_clk_fo", &self.ulp_cp_clk_fo())
+            .field("ulp_cp_reset", &self.ulp_cp_reset())
+            .field("ulp_cp_force_start_top", &self.ulp_cp_force_start_top())
+            .field("ulp_cp_start_top", &self.ulp_cp_start_top())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_cntl/ulp_cp_timer.rs b/esp32s2-ulp/src/rtc_cntl/ulp_cp_timer.rs
index f19c3bf875..d519f6ab39 100644
--- a/esp32s2-ulp/src/rtc_cntl/ulp_cp_timer.rs
+++ b/esp32s2-ulp/src/rtc_cntl/ulp_cp_timer.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_TIMER")
-            .field(
-                "ulp_cp_pc_init",
-                &format_args!("{}", self.ulp_cp_pc_init().bits()),
-            )
-            .field(
-                "ulp_cp_gpio_wakeup_ena",
-                &format_args!("{}", self.ulp_cp_gpio_wakeup_ena().bit()),
-            )
-            .field(
-                "ulp_cp_slp_timer_en",
-                &format_args!("{}", self.ulp_cp_slp_timer_en().bit()),
-            )
+            .field("ulp_cp_pc_init", &self.ulp_cp_pc_init())
+            .field("ulp_cp_gpio_wakeup_ena", &self.ulp_cp_gpio_wakeup_ena())
+            .field("ulp_cp_slp_timer_en", &self.ulp_cp_slp_timer_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_TIMER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - ULP coprocessor PC initial address"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_cntl/ulp_cp_timer_1.rs b/esp32s2-ulp/src/rtc_cntl/ulp_cp_timer_1.rs
index d92d48d625..e0cb787596 100644
--- a/esp32s2-ulp/src/rtc_cntl/ulp_cp_timer_1.rs
+++ b/esp32s2-ulp/src/rtc_cntl/ulp_cp_timer_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_TIMER_1")
-            .field(
-                "ulp_cp_timer_slp_cycle",
-                &format_args!("{}", self.ulp_cp_timer_slp_cycle().bits()),
-            )
+            .field("ulp_cp_timer_slp_cycle", &self.ulp_cp_timer_slp_cycle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_TIMER_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:31 - Set sleep cycles for ULP coprocessor timer"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_i2c/cmd.rs b/esp32s2-ulp/src/rtc_i2c/cmd.rs
index f1a4792fc8..62306772ec 100644
--- a/esp32s2-ulp/src/rtc_i2c/cmd.rs
+++ b/esp32s2-ulp/src/rtc_i2c/cmd.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("command", &format_args!("{}", self.command().bits()))
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Content of command 0. For more information, please refer to the register I2C_COMD0_REG in Chapter I²C Controller"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_i2c/ctrl.rs b/esp32s2-ulp/src/rtc_i2c/ctrl.rs
index 274cb6e950..e542a862d2 100644
--- a/esp32s2-ulp/src/rtc_i2c/ctrl.rs
+++ b/esp32s2-ulp/src/rtc_i2c/ctrl.rs
@@ -89,36 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field("ms_mode", &format_args!("{}", self.ms_mode().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
-            .field("clk_gate_en", &format_args!("{}", self.clk_gate_en().bit()))
-            .field("reset", &format_args!("{}", self.reset().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("ms_mode", &self.ms_mode())
+            .field("trans_start", &self.trans_start())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("clk_gate_en", &self.clk_gate_en())
+            .field("reset", &self.reset())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SDA output mode. 0: open drain. 1: push pull."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_i2c/data.rs b/esp32s2-ulp/src/rtc_i2c/data.rs
index 2b99115683..3d84c223a5 100644
--- a/esp32s2-ulp/src/rtc_i2c/data.rs
+++ b/esp32s2-ulp/src/rtc_i2c/data.rs
@@ -31,21 +31,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field("rdata", &format_args!("{}", self.rdata().bits()))
-            .field(
-                "slave_tx_data",
-                &format_args!("{}", self.slave_tx_data().bits()),
-            )
-            .field("done", &format_args!("{}", self.done().bit()))
+            .field("rdata", &self.rdata())
+            .field("slave_tx_data", &self.slave_tx_data())
+            .field("done", &self.done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:15 - The data sent by slave"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_i2c/date.rs b/esp32s2-ulp/src/rtc_i2c/date.rs
index 7b6b864714..f4c7caacd8 100644
--- a/esp32s2-ulp/src/rtc_i2c/date.rs
+++ b/esp32s2-ulp/src/rtc_i2c/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2-ulp/src/rtc_i2c/int_ena.rs b/esp32s2-ulp/src/rtc_i2c/int_ena.rs
index 3347ddd174..c0c15bae95 100644
--- a/esp32s2-ulp/src/rtc_i2c/int_ena.rs
+++ b/esp32s2-ulp/src/rtc_i2c/int_ena.rs
@@ -89,39 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "slave_tran_comp",
-                &format_args!("{}", self.slave_tran_comp().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_tran_comp",
-                &format_args!("{}", self.master_tran_comp().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("ack_err", &format_args!("{}", self.ack_err().bit()))
-            .field("rx_data", &format_args!("{}", self.rx_data().bit()))
-            .field("tx_data", &format_args!("{}", self.tx_data().bit()))
-            .field(
-                "detect_start",
-                &format_args!("{}", self.detect_start().bit()),
-            )
+            .field("slave_tran_comp", &self.slave_tran_comp())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_tran_comp", &self.master_tran_comp())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("ack_err", &self.ack_err())
+            .field("rx_data", &self.rx_data())
+            .field("tx_data", &self.tx_data())
+            .field("detect_start", &self.detect_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - RTC_I2C_SLAVE_TRAN_COMP_INT interrupt enable bit"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_i2c/int_raw.rs b/esp32s2-ulp/src/rtc_i2c/int_raw.rs
index 07861e3951..54550ab419 100644
--- a/esp32s2-ulp/src/rtc_i2c/int_raw.rs
+++ b/esp32s2-ulp/src/rtc_i2c/int_raw.rs
@@ -69,39 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "slave_tran_comp",
-                &format_args!("{}", self.slave_tran_comp().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_tran_comp",
-                &format_args!("{}", self.master_tran_comp().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("ack_err", &format_args!("{}", self.ack_err().bit()))
-            .field("rx_data", &format_args!("{}", self.rx_data().bit()))
-            .field("tx_data", &format_args!("{}", self.tx_data().bit()))
-            .field(
-                "detect_start",
-                &format_args!("{}", self.detect_start().bit()),
-            )
+            .field("slave_tran_comp", &self.slave_tran_comp())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_tran_comp", &self.master_tran_comp())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("ack_err", &self.ack_err())
+            .field("rx_data", &self.rx_data())
+            .field("tx_data", &self.tx_data())
+            .field("detect_start", &self.detect_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC I2C raw interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s2-ulp/src/rtc_i2c/int_st.rs b/esp32s2-ulp/src/rtc_i2c/int_st.rs
index 567383878d..eea800c367 100644
--- a/esp32s2-ulp/src/rtc_i2c/int_st.rs
+++ b/esp32s2-ulp/src/rtc_i2c/int_st.rs
@@ -69,39 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "slave_tran_comp",
-                &format_args!("{}", self.slave_tran_comp().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_tran_comp",
-                &format_args!("{}", self.master_tran_comp().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("ack_err", &format_args!("{}", self.ack_err().bit()))
-            .field("rx_data", &format_args!("{}", self.rx_data().bit()))
-            .field("tx_data", &format_args!("{}", self.tx_data().bit()))
-            .field(
-                "detect_start",
-                &format_args!("{}", self.detect_start().bit()),
-            )
+            .field("slave_tran_comp", &self.slave_tran_comp())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_tran_comp", &self.master_tran_comp())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("ack_err", &self.ack_err())
+            .field("rx_data", &self.rx_data())
+            .field("tx_data", &self.tx_data())
+            .field("detect_start", &self.detect_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC I2C interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s2-ulp/src/rtc_i2c/scl_high.rs b/esp32s2-ulp/src/rtc_i2c/scl_high.rs
index 67af4dd83a..14af2585e9 100644
--- a/esp32s2-ulp/src/rtc_i2c/scl_high.rs
+++ b/esp32s2-ulp/src/rtc_i2c/scl_high.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH")
-            .field("period", &format_args!("{}", self.period().bits()))
+            .field("period", &self.period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register is used to configure how many cycles SCL remains high."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_i2c/scl_low.rs b/esp32s2-ulp/src/rtc_i2c/scl_low.rs
index a7d44338b5..bd7009a3b3 100644
--- a/esp32s2-ulp/src/rtc_i2c/scl_low.rs
+++ b/esp32s2-ulp/src/rtc_i2c/scl_low.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW")
-            .field("period", &format_args!("{}", self.period().bits()))
+            .field("period", &self.period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register is used to configure how many clock cycles SCL remains low."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_i2c/scl_start_period.rs b/esp32s2-ulp/src/rtc_i2c/scl_start_period.rs
index 13a722b0ad..d237af38c0 100644
--- a/esp32s2-ulp/src/rtc_i2c/scl_start_period.rs
+++ b/esp32s2-ulp/src/rtc_i2c/scl_start_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_PERIOD")
-            .field(
-                "scl_start_period",
-                &format_args!("{}", self.scl_start_period().bits()),
-            )
+            .field("scl_start_period", &self.scl_start_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - Number of clock cycles to wait after generating a start condition."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_i2c/scl_stop_period.rs b/esp32s2-ulp/src/rtc_i2c/scl_stop_period.rs
index 0e8fb62275..7a307f2791 100644
--- a/esp32s2-ulp/src/rtc_i2c/scl_stop_period.rs
+++ b/esp32s2-ulp/src/rtc_i2c/scl_stop_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_PERIOD")
-            .field(
-                "scl_stop_period",
-                &format_args!("{}", self.scl_stop_period().bits()),
-            )
+            .field("scl_stop_period", &self.scl_stop_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - Number of clock cycles to wait before generating a stop condition."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_i2c/sda_duty.rs b/esp32s2-ulp/src/rtc_i2c/sda_duty.rs
index d60ef29da2..125cb109ad 100644
--- a/esp32s2-ulp/src/rtc_i2c/sda_duty.rs
+++ b/esp32s2-ulp/src/rtc_i2c/sda_duty.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_DUTY")
-            .field("num", &format_args!("{}", self.num().bits()))
+            .field("num", &self.num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - The number of clock cycles between the SDA switch and the falling edge of SCL."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_i2c/slave_addr.rs b/esp32s2-ulp/src/rtc_i2c/slave_addr.rs
index 9c127aa99d..991b963e84 100644
--- a/esp32s2-ulp/src/rtc_i2c/slave_addr.rs
+++ b/esp32s2-ulp/src/rtc_i2c/slave_addr.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE_ADDR")
-            .field("slave_addr", &format_args!("{}", self.slave_addr().bits()))
-            .field(
-                "addr_10bit_en",
-                &format_args!("{}", self.addr_10bit_en().bit()),
-            )
+            .field("slave_addr", &self.slave_addr())
+            .field("addr_10bit_en", &self.addr_10bit_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - slave address"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_i2c/status.rs b/esp32s2-ulp/src/rtc_i2c/status.rs
index d0442a71b8..60d0b73b8f 100644
--- a/esp32s2-ulp/src/rtc_i2c/status.rs
+++ b/esp32s2-ulp/src/rtc_i2c/status.rs
@@ -76,34 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("ack_rec", &format_args!("{}", self.ack_rec().bit()))
-            .field("slave_rw", &format_args!("{}", self.slave_rw().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field(
-                "slave_addressed",
-                &format_args!("{}", self.slave_addressed().bit()),
-            )
-            .field("byte_trans", &format_args!("{}", self.byte_trans().bit()))
-            .field("op_cnt", &format_args!("{}", self.op_cnt().bits()))
-            .field("shift", &format_args!("{}", self.shift().bits()))
-            .field(
-                "scl_main_state_last",
-                &format_args!("{}", self.scl_main_state_last().bits()),
-            )
-            .field(
-                "scl_state_last",
-                &format_args!("{}", self.scl_state_last().bits()),
-            )
+            .field("ack_rec", &self.ack_rec())
+            .field("slave_rw", &self.slave_rw())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("slave_addressed", &self.slave_addressed())
+            .field("byte_trans", &self.byte_trans())
+            .field("op_cnt", &self.op_cnt())
+            .field("shift", &self.shift())
+            .field("scl_main_state_last", &self.scl_main_state_last())
+            .field("scl_state_last", &self.scl_state_last())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC I2C status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32s2-ulp/src/rtc_i2c/to.rs b/esp32s2-ulp/src/rtc_i2c/to.rs
index 98b81a2aa8..18ae107993 100644
--- a/esp32s2-ulp/src/rtc_i2c/to.rs
+++ b/esp32s2-ulp/src/rtc_i2c/to.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO")
-            .field("time_out", &format_args!("{}", self.time_out().bits()))
+            .field("time_out", &self.time_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - Timeout threshold"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/enable.rs b/esp32s2-ulp/src/rtc_io/enable.rs
index 0ba5c1078f..0b4f7566b2 100644
--- a/esp32s2-ulp/src/rtc_io/enable.rs
+++ b/esp32s2-ulp/src/rtc_io/enable.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ENABLE")
             .field(
                 "reg_rtcio_reg_gpio_enable",
-                &format_args!("{}", self.reg_rtcio_reg_gpio_enable().bits()),
+                &self.reg_rtcio_reg_gpio_enable(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/ext_wakeup0.rs b/esp32s2-ulp/src/rtc_io/ext_wakeup0.rs
index d2f2163134..254cc44678 100644
--- a/esp32s2-ulp/src/rtc_io/ext_wakeup0.rs
+++ b/esp32s2-ulp/src/rtc_io/ext_wakeup0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP0")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 27:31 - GPIO\\[0-17\\] can be used to wake up the chip when the chip is in the sleep mode. This register prompts the pad source to wake up the chip when the latter is indeep/light sleep mode. 0: select GPIO0; 1: select GPIO2, etc"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/in_.rs b/esp32s2-ulp/src/rtc_io/in_.rs
index 0714e2310f..61e29ae9ac 100644
--- a/esp32s2-ulp/src/rtc_io/in_.rs
+++ b/esp32s2-ulp/src/rtc_io/in_.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN")
-            .field(
-                "gpio_in_next",
-                &format_args!("{}", self.gpio_in_next().bits()),
-            )
+            .field("gpio_in_next", &self.gpio_in_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC GPIO input register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SPEC;
 impl crate::RegisterSpec for IN_SPEC {
diff --git a/esp32s2-ulp/src/rtc_io/out.rs b/esp32s2-ulp/src/rtc_io/out.rs
index 6575e1374b..12ed42c080 100644
--- a/esp32s2-ulp/src/rtc_io/out.rs
+++ b/esp32s2-ulp/src/rtc_io/out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT")
-            .field(
-                "gpio_out_data",
-                &format_args!("{}", self.gpio_out_data().bits()),
-            )
+            .field("gpio_out_data", &self.gpio_out_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/pad_dac1.rs b/esp32s2-ulp/src/rtc_io/pad_dac1.rs
index 771fbdebea..919068c5c4 100644
--- a/esp32s2-ulp/src/rtc_io/pad_dac1.rs
+++ b/esp32s2-ulp/src/rtc_io/pad_dac1.rs
@@ -116,51 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_DAC1")
-            .field("pdac1_dac", &format_args!("{}", self.pdac1_dac().bits()))
-            .field(
-                "pdac1_xpd_dac",
-                &format_args!("{}", self.pdac1_xpd_dac().bit()),
-            )
-            .field(
-                "pdac1_dac_xpd_force",
-                &format_args!("{}", self.pdac1_dac_xpd_force().bit()),
-            )
-            .field(
-                "pdac1_fun_ie",
-                &format_args!("{}", self.pdac1_fun_ie().bit()),
-            )
-            .field(
-                "pdac1_slp_oe",
-                &format_args!("{}", self.pdac1_slp_oe().bit()),
-            )
-            .field(
-                "pdac1_slp_ie",
-                &format_args!("{}", self.pdac1_slp_ie().bit()),
-            )
-            .field(
-                "pdac1_slp_sel",
-                &format_args!("{}", self.pdac1_slp_sel().bit()),
-            )
-            .field(
-                "pdac1_fun_sel",
-                &format_args!("{}", self.pdac1_fun_sel().bits()),
-            )
-            .field(
-                "pdac1_mux_sel",
-                &format_args!("{}", self.pdac1_mux_sel().bit()),
-            )
-            .field("pdac1_rue", &format_args!("{}", self.pdac1_rue().bit()))
-            .field("pdac1_rde", &format_args!("{}", self.pdac1_rde().bit()))
-            .field("pdac1_drv", &format_args!("{}", self.pdac1_drv().bits()))
+            .field("pdac1_dac", &self.pdac1_dac())
+            .field("pdac1_xpd_dac", &self.pdac1_xpd_dac())
+            .field("pdac1_dac_xpd_force", &self.pdac1_dac_xpd_force())
+            .field("pdac1_fun_ie", &self.pdac1_fun_ie())
+            .field("pdac1_slp_oe", &self.pdac1_slp_oe())
+            .field("pdac1_slp_ie", &self.pdac1_slp_ie())
+            .field("pdac1_slp_sel", &self.pdac1_slp_sel())
+            .field("pdac1_fun_sel", &self.pdac1_fun_sel())
+            .field("pdac1_mux_sel", &self.pdac1_mux_sel())
+            .field("pdac1_rue", &self.pdac1_rue())
+            .field("pdac1_rde", &self.pdac1_rde())
+            .field("pdac1_drv", &self.pdac1_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_DAC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:10 - Configure DAC_1 output when RTCIO_PDAC1_DAC_XPD_FORCE is set to 1."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/pad_dac2.rs b/esp32s2-ulp/src/rtc_io/pad_dac2.rs
index cbf3b46ea3..eabd802a43 100644
--- a/esp32s2-ulp/src/rtc_io/pad_dac2.rs
+++ b/esp32s2-ulp/src/rtc_io/pad_dac2.rs
@@ -116,51 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_DAC2")
-            .field("pdac2_dac", &format_args!("{}", self.pdac2_dac().bits()))
-            .field(
-                "pdac2_xpd_dac",
-                &format_args!("{}", self.pdac2_xpd_dac().bit()),
-            )
-            .field(
-                "pdac2_dac_xpd_force",
-                &format_args!("{}", self.pdac2_dac_xpd_force().bit()),
-            )
-            .field(
-                "pdac2_fun_ie",
-                &format_args!("{}", self.pdac2_fun_ie().bit()),
-            )
-            .field(
-                "pdac2_slp_oe",
-                &format_args!("{}", self.pdac2_slp_oe().bit()),
-            )
-            .field(
-                "pdac2_slp_ie",
-                &format_args!("{}", self.pdac2_slp_ie().bit()),
-            )
-            .field(
-                "pdac2_slp_sel",
-                &format_args!("{}", self.pdac2_slp_sel().bit()),
-            )
-            .field(
-                "pdac2_fun_sel",
-                &format_args!("{}", self.pdac2_fun_sel().bits()),
-            )
-            .field(
-                "pdac2_mux_sel",
-                &format_args!("{}", self.pdac2_mux_sel().bit()),
-            )
-            .field("pdac2_rue", &format_args!("{}", self.pdac2_rue().bit()))
-            .field("pdac2_rde", &format_args!("{}", self.pdac2_rde().bit()))
-            .field("pdac2_drv", &format_args!("{}", self.pdac2_drv().bits()))
+            .field("pdac2_dac", &self.pdac2_dac())
+            .field("pdac2_xpd_dac", &self.pdac2_xpd_dac())
+            .field("pdac2_dac_xpd_force", &self.pdac2_dac_xpd_force())
+            .field("pdac2_fun_ie", &self.pdac2_fun_ie())
+            .field("pdac2_slp_oe", &self.pdac2_slp_oe())
+            .field("pdac2_slp_ie", &self.pdac2_slp_ie())
+            .field("pdac2_slp_sel", &self.pdac2_slp_sel())
+            .field("pdac2_fun_sel", &self.pdac2_fun_sel())
+            .field("pdac2_mux_sel", &self.pdac2_mux_sel())
+            .field("pdac2_rue", &self.pdac2_rue())
+            .field("pdac2_rde", &self.pdac2_rde())
+            .field("pdac2_drv", &self.pdac2_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_DAC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:10 - Configure DAC_2 output when RTCIO_PDAC2_DAC_XPD_FORCE is set to 1."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/pin.rs b/esp32s2-ulp/src/rtc_io/pin.rs
index a7152a7517..19c872899f 100644
--- a/esp32s2-ulp/src/rtc_io/pin.rs
+++ b/esp32s2-ulp/src/rtc_io/pin.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN")
-            .field(
-                "gpio_pin_pad_driver",
-                &format_args!("{}", self.gpio_pin_pad_driver().bit()),
-            )
-            .field(
-                "gpio_pin_int_type",
-                &format_args!("{}", self.gpio_pin_int_type().bits()),
-            )
-            .field(
-                "gpio_pin_wakeup_enable",
-                &format_args!("{}", self.gpio_pin_wakeup_enable().bit()),
-            )
+            .field("gpio_pin_pad_driver", &self.gpio_pin_pad_driver())
+            .field("gpio_pin_int_type", &self.gpio_pin_int_type())
+            .field("gpio_pin_wakeup_enable", &self.gpio_pin_wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - Pad driver selection. 0: normal output. 1: open drain."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/rtc_debug_sel.rs b/esp32s2-ulp/src/rtc_io/rtc_debug_sel.rs
index 057e0a3803..3e033f7915 100644
--- a/esp32s2-ulp/src/rtc_io/rtc_debug_sel.rs
+++ b/esp32s2-ulp/src/rtc_io/rtc_debug_sel.rs
@@ -62,24 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_DEBUG_SEL")
-            .field("debug_sel0", &format_args!("{}", self.debug_sel0().bits()))
-            .field("debug_sel1", &format_args!("{}", self.debug_sel1().bits()))
-            .field("debug_sel2", &format_args!("{}", self.debug_sel2().bits()))
-            .field("debug_sel3", &format_args!("{}", self.debug_sel3().bits()))
-            .field("debug_sel4", &format_args!("{}", self.debug_sel4().bits()))
-            .field(
-                "debug_12m_no_gating",
-                &format_args!("{}", self.debug_12m_no_gating().bit()),
-            )
+            .field("debug_sel0", &self.debug_sel0())
+            .field("debug_sel1", &self.debug_sel1())
+            .field("debug_sel2", &self.debug_sel2())
+            .field("debug_sel3", &self.debug_sel3())
+            .field("debug_sel4", &self.debug_sel4())
+            .field("debug_12m_no_gating", &self.debug_12m_no_gating())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_DEBUG_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/rtc_io_date.rs b/esp32s2-ulp/src/rtc_io/rtc_io_date.rs
index 940b912c4d..d97379d088 100644
--- a/esp32s2-ulp/src/rtc_io/rtc_io_date.rs
+++ b/esp32s2-ulp/src/rtc_io/rtc_io_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_IO_DATE")
-            .field("io_date", &format_args!("{}", self.io_date().bits()))
+            .field("io_date", &self.io_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_IO_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/rtc_io_touch_ctrl.rs b/esp32s2-ulp/src/rtc_io/rtc_io_touch_ctrl.rs
index 3174ddaba2..9879fb62a1 100644
--- a/esp32s2-ulp/src/rtc_io/rtc_io_touch_ctrl.rs
+++ b/esp32s2-ulp/src/rtc_io/rtc_io_touch_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_IO_TOUCH_CTRL")
-            .field(
-                "io_touch_bufsel",
-                &format_args!("{}", self.io_touch_bufsel().bits()),
-            )
-            .field(
-                "io_touch_bufmode",
-                &format_args!("{}", self.io_touch_bufmode().bit()),
-            )
+            .field("io_touch_bufsel", &self.io_touch_bufsel())
+            .field("io_touch_bufmode", &self.io_touch_bufmode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_IO_TOUCH_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/rtc_pad19.rs b/esp32s2-ulp/src/rtc_io/rtc_pad19.rs
index 18120bb8ac..3834851721 100644
--- a/esp32s2-ulp/src/rtc_io/rtc_pad19.rs
+++ b/esp32s2-ulp/src/rtc_io/rtc_pad19.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_PAD19")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_PAD19_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/rtc_pad20.rs b/esp32s2-ulp/src/rtc_io/rtc_pad20.rs
index 2e67a4f9d3..a44ccf7031 100644
--- a/esp32s2-ulp/src/rtc_io/rtc_pad20.rs
+++ b/esp32s2-ulp/src/rtc_io/rtc_pad20.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_PAD20")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_PAD20_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/rtc_pad21.rs b/esp32s2-ulp/src/rtc_io/rtc_pad21.rs
index d0fa416ebb..509112f876 100644
--- a/esp32s2-ulp/src/rtc_io/rtc_pad21.rs
+++ b/esp32s2-ulp/src/rtc_io/rtc_pad21.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_PAD21")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_PAD21_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/sar_i2c_io.rs b/esp32s2-ulp/src/rtc_io/sar_i2c_io.rs
index 710dc7ef54..005720ceab 100644
--- a/esp32s2-ulp/src/rtc_io/sar_i2c_io.rs
+++ b/esp32s2-ulp/src/rtc_io/sar_i2c_io.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_I2C_IO")
-            .field(
-                "sar_debug_bit_sel",
-                &format_args!("{}", self.sar_debug_bit_sel().bits()),
-            )
-            .field(
-                "sar_i2c_scl_sel",
-                &format_args!("{}", self.sar_i2c_scl_sel().bits()),
-            )
-            .field(
-                "sar_i2c_sda_sel",
-                &format_args!("{}", self.sar_i2c_sda_sel().bits()),
-            )
+            .field("sar_debug_bit_sel", &self.sar_debug_bit_sel())
+            .field("sar_i2c_scl_sel", &self.sar_i2c_scl_sel())
+            .field("sar_i2c_sda_sel", &self.sar_i2c_sda_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_I2C_IO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:27"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/status.rs b/esp32s2-ulp/src/rtc_io/status.rs
index d5d11a47bf..5f73ed24cf 100644
--- a/esp32s2-ulp/src/rtc_io/status.rs
+++ b/esp32s2-ulp/src/rtc_io/status.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field(
-                "gpio_status_int",
-                &format_args!("{}", self.gpio_status_int().bits()),
-            )
+            .field("gpio_status_int", &self.gpio_status_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 interrupt status register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RTCIO_RTC_GPIO_PINn_REG. 0: no interrupt; 1: corresponding interrupt."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/touch_pad.rs b/esp32s2-ulp/src/rtc_io/touch_pad.rs
index d7bffd38b5..bc2aa83524 100644
--- a/esp32s2-ulp/src/rtc_io/touch_pad.rs
+++ b/esp32s2-ulp/src/rtc_io/touch_pad.rs
@@ -125,28 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("dac", &format_args!("{}", self.dac().bits()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("dac", &self.dac())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/xtal_32n_pad.rs b/esp32s2-ulp/src/rtc_io/xtal_32n_pad.rs
index 00247903fd..30f17ea26a 100644
--- a/esp32s2-ulp/src/rtc_io/xtal_32n_pad.rs
+++ b/esp32s2-ulp/src/rtc_io/xtal_32n_pad.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL_32N_PAD")
-            .field("x32n_fun_ie", &format_args!("{}", self.x32n_fun_ie().bit()))
-            .field("x32n_slp_oe", &format_args!("{}", self.x32n_slp_oe().bit()))
-            .field("x32n_slp_ie", &format_args!("{}", self.x32n_slp_ie().bit()))
-            .field(
-                "x32n_slp_sel",
-                &format_args!("{}", self.x32n_slp_sel().bit()),
-            )
-            .field(
-                "x32n_fun_sel",
-                &format_args!("{}", self.x32n_fun_sel().bits()),
-            )
-            .field(
-                "x32n_mux_sel",
-                &format_args!("{}", self.x32n_mux_sel().bit()),
-            )
-            .field("x32n_rue", &format_args!("{}", self.x32n_rue().bit()))
-            .field("x32n_rde", &format_args!("{}", self.x32n_rde().bit()))
-            .field("x32n_drv", &format_args!("{}", self.x32n_drv().bits()))
+            .field("x32n_fun_ie", &self.x32n_fun_ie())
+            .field("x32n_slp_oe", &self.x32n_slp_oe())
+            .field("x32n_slp_ie", &self.x32n_slp_ie())
+            .field("x32n_slp_sel", &self.x32n_slp_sel())
+            .field("x32n_fun_sel", &self.x32n_fun_sel())
+            .field("x32n_mux_sel", &self.x32n_mux_sel())
+            .field("x32n_rue", &self.x32n_rue())
+            .field("x32n_rde", &self.x32n_rde())
+            .field("x32n_drv", &self.x32n_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL_32N_PAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/xtal_32p_pad.rs b/esp32s2-ulp/src/rtc_io/xtal_32p_pad.rs
index 2dd0eba9a6..25df482e56 100644
--- a/esp32s2-ulp/src/rtc_io/xtal_32p_pad.rs
+++ b/esp32s2-ulp/src/rtc_io/xtal_32p_pad.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL_32P_PAD")
-            .field("x32p_fun_ie", &format_args!("{}", self.x32p_fun_ie().bit()))
-            .field("x32p_slp_oe", &format_args!("{}", self.x32p_slp_oe().bit()))
-            .field("x32p_slp_ie", &format_args!("{}", self.x32p_slp_ie().bit()))
-            .field(
-                "x32p_slp_sel",
-                &format_args!("{}", self.x32p_slp_sel().bit()),
-            )
-            .field(
-                "x32p_fun_sel",
-                &format_args!("{}", self.x32p_fun_sel().bits()),
-            )
-            .field(
-                "x32p_mux_sel",
-                &format_args!("{}", self.x32p_mux_sel().bit()),
-            )
-            .field("x32p_rue", &format_args!("{}", self.x32p_rue().bit()))
-            .field("x32p_rde", &format_args!("{}", self.x32p_rde().bit()))
-            .field("x32p_drv", &format_args!("{}", self.x32p_drv().bits()))
+            .field("x32p_fun_ie", &self.x32p_fun_ie())
+            .field("x32p_slp_oe", &self.x32p_slp_oe())
+            .field("x32p_slp_ie", &self.x32p_slp_ie())
+            .field("x32p_slp_sel", &self.x32p_slp_sel())
+            .field("x32p_fun_sel", &self.x32p_fun_sel())
+            .field("x32p_mux_sel", &self.x32p_mux_sel())
+            .field("x32p_rue", &self.x32p_rue())
+            .field("x32p_rde", &self.x32p_rde())
+            .field("x32p_drv", &self.x32p_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL_32P_PAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/rtc_io/xtl_ext_ctr.rs b/esp32s2-ulp/src/rtc_io/xtl_ext_ctr.rs
index 1844095718..9c90f76ae8 100644
--- a/esp32s2-ulp/src/rtc_io/xtl_ext_ctr.rs
+++ b/esp32s2-ulp/src/rtc_io/xtl_ext_ctr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTL_EXT_CTR")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTL_EXT_CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 27:31 - Select the external crystal power down enable source to get into sleep mode. 0: select GPIO0. 1: select GPIO1, etc. The input value on this pin XOR RTC_CNTL_EXT_XTL_CONF_REG\\[30\\] is the crystal power down enable signal."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/sens/sar_cocpu_int_ena.rs b/esp32s2-ulp/src/sens/sar_cocpu_int_ena.rs
index 2b6498bb56..0c9b427f56 100644
--- a/esp32s2-ulp/src/sens/sar_cocpu_int_ena.rs
+++ b/esp32s2-ulp/src/sens/sar_cocpu_int_ena.rs
@@ -89,51 +89,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_COCPU_INT_ENA")
-            .field(
-                "cocpu_touch_done_int_ena",
-                &format_args!("{}", self.cocpu_touch_done_int_ena().bit()),
-            )
+            .field("cocpu_touch_done_int_ena", &self.cocpu_touch_done_int_ena())
             .field(
                 "cocpu_touch_inactive_int_ena",
-                &format_args!("{}", self.cocpu_touch_inactive_int_ena().bit()),
+                &self.cocpu_touch_inactive_int_ena(),
             )
             .field(
                 "cocpu_touch_active_int_ena",
-                &format_args!("{}", self.cocpu_touch_active_int_ena().bit()),
-            )
-            .field(
-                "cocpu_saradc1_int_ena",
-                &format_args!("{}", self.cocpu_saradc1_int_ena().bit()),
-            )
-            .field(
-                "cocpu_saradc2_int_ena",
-                &format_args!("{}", self.cocpu_saradc2_int_ena().bit()),
-            )
-            .field(
-                "cocpu_tsens_int_ena",
-                &format_args!("{}", self.cocpu_tsens_int_ena().bit()),
-            )
-            .field(
-                "cocpu_start_int_ena",
-                &format_args!("{}", self.cocpu_start_int_ena().bit()),
-            )
-            .field(
-                "cocpu_sw_int_ena",
-                &format_args!("{}", self.cocpu_sw_int_ena().bit()),
-            )
-            .field(
-                "cocpu_swd_int_ena",
-                &format_args!("{}", self.cocpu_swd_int_ena().bit()),
+                &self.cocpu_touch_active_int_ena(),
             )
+            .field("cocpu_saradc1_int_ena", &self.cocpu_saradc1_int_ena())
+            .field("cocpu_saradc2_int_ena", &self.cocpu_saradc2_int_ena())
+            .field("cocpu_tsens_int_ena", &self.cocpu_tsens_int_ena())
+            .field("cocpu_start_int_ena", &self.cocpu_start_int_ena())
+            .field("cocpu_sw_int_ena", &self.cocpu_sw_int_ena())
+            .field("cocpu_swd_int_ena", &self.cocpu_swd_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - TOUCH_DONE_INT interrupt enable bit"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/sens/sar_cocpu_int_raw.rs b/esp32s2-ulp/src/sens/sar_cocpu_int_raw.rs
index 3fa44cfab6..e2a4de4022 100644
--- a/esp32s2-ulp/src/sens/sar_cocpu_int_raw.rs
+++ b/esp32s2-ulp/src/sens/sar_cocpu_int_raw.rs
@@ -69,51 +69,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_COCPU_INT_RAW")
-            .field(
-                "cocpu_touch_done_int_raw",
-                &format_args!("{}", self.cocpu_touch_done_int_raw().bit()),
-            )
+            .field("cocpu_touch_done_int_raw", &self.cocpu_touch_done_int_raw())
             .field(
                 "cocpu_touch_inactive_int_raw",
-                &format_args!("{}", self.cocpu_touch_inactive_int_raw().bit()),
+                &self.cocpu_touch_inactive_int_raw(),
             )
             .field(
                 "cocpu_touch_active_int_raw",
-                &format_args!("{}", self.cocpu_touch_active_int_raw().bit()),
-            )
-            .field(
-                "cocpu_saradc1_int_raw",
-                &format_args!("{}", self.cocpu_saradc1_int_raw().bit()),
-            )
-            .field(
-                "cocpu_saradc2_int_raw",
-                &format_args!("{}", self.cocpu_saradc2_int_raw().bit()),
-            )
-            .field(
-                "cocpu_tsens_int_raw",
-                &format_args!("{}", self.cocpu_tsens_int_raw().bit()),
-            )
-            .field(
-                "cocpu_start_int_raw",
-                &format_args!("{}", self.cocpu_start_int_raw().bit()),
-            )
-            .field(
-                "cocpu_sw_int_raw",
-                &format_args!("{}", self.cocpu_sw_int_raw().bit()),
-            )
-            .field(
-                "cocpu_swd_int_raw",
-                &format_args!("{}", self.cocpu_swd_int_raw().bit()),
+                &self.cocpu_touch_active_int_raw(),
             )
+            .field("cocpu_saradc1_int_raw", &self.cocpu_saradc1_int_raw())
+            .field("cocpu_saradc2_int_raw", &self.cocpu_saradc2_int_raw())
+            .field("cocpu_tsens_int_raw", &self.cocpu_tsens_int_raw())
+            .field("cocpu_start_int_raw", &self.cocpu_start_int_raw())
+            .field("cocpu_sw_int_raw", &self.cocpu_sw_int_raw())
+            .field("cocpu_swd_int_raw", &self.cocpu_swd_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt raw bit of ULP-RISCV\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_cocpu_int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_COCPU_INT_RAW_SPEC;
 impl crate::RegisterSpec for SAR_COCPU_INT_RAW_SPEC {
diff --git a/esp32s2-ulp/src/sens/sar_cocpu_int_st.rs b/esp32s2-ulp/src/sens/sar_cocpu_int_st.rs
index b54165b09e..6776d12416 100644
--- a/esp32s2-ulp/src/sens/sar_cocpu_int_st.rs
+++ b/esp32s2-ulp/src/sens/sar_cocpu_int_st.rs
@@ -69,51 +69,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_COCPU_INT_ST")
-            .field(
-                "cocpu_touch_done_int_st",
-                &format_args!("{}", self.cocpu_touch_done_int_st().bit()),
-            )
+            .field("cocpu_touch_done_int_st", &self.cocpu_touch_done_int_st())
             .field(
                 "cocpu_touch_inactive_int_st",
-                &format_args!("{}", self.cocpu_touch_inactive_int_st().bit()),
+                &self.cocpu_touch_inactive_int_st(),
             )
             .field(
                 "cocpu_touch_active_int_st",
-                &format_args!("{}", self.cocpu_touch_active_int_st().bit()),
-            )
-            .field(
-                "cocpu_saradc1_int_st",
-                &format_args!("{}", self.cocpu_saradc1_int_st().bit()),
-            )
-            .field(
-                "cocpu_saradc2_int_st",
-                &format_args!("{}", self.cocpu_saradc2_int_st().bit()),
-            )
-            .field(
-                "cocpu_tsens_int_st",
-                &format_args!("{}", self.cocpu_tsens_int_st().bit()),
-            )
-            .field(
-                "cocpu_start_int_st",
-                &format_args!("{}", self.cocpu_start_int_st().bit()),
-            )
-            .field(
-                "cocpu_sw_int_st",
-                &format_args!("{}", self.cocpu_sw_int_st().bit()),
-            )
-            .field(
-                "cocpu_swd_int_st",
-                &format_args!("{}", self.cocpu_swd_int_st().bit()),
+                &self.cocpu_touch_active_int_st(),
             )
+            .field("cocpu_saradc1_int_st", &self.cocpu_saradc1_int_st())
+            .field("cocpu_saradc2_int_st", &self.cocpu_saradc2_int_st())
+            .field("cocpu_tsens_int_st", &self.cocpu_tsens_int_st())
+            .field("cocpu_start_int_st", &self.cocpu_start_int_st())
+            .field("cocpu_sw_int_st", &self.cocpu_sw_int_st())
+            .field("cocpu_swd_int_st", &self.cocpu_swd_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status bit of ULP-RISCV\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_cocpu_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_COCPU_INT_ST_SPEC;
 impl crate::RegisterSpec for SAR_COCPU_INT_ST_SPEC {
diff --git a/esp32s2-ulp/src/sens/sar_i2c_ctrl.rs b/esp32s2-ulp/src/sens/sar_i2c_ctrl.rs
index 5713f40f15..2fec25c032 100644
--- a/esp32s2-ulp/src/sens/sar_i2c_ctrl.rs
+++ b/esp32s2-ulp/src/sens/sar_i2c_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_I2C_CTRL")
-            .field(
-                "sar_i2c_ctrl",
-                &format_args!("{}", self.sar_i2c_ctrl().bits()),
-            )
-            .field(
-                "sar_i2c_start",
-                &format_args!("{}", self.sar_i2c_start().bit()),
-            )
-            .field(
-                "sar_i2c_start_force",
-                &format_args!("{}", self.sar_i2c_start_force().bit()),
-            )
+            .field("sar_i2c_ctrl", &self.sar_i2c_ctrl())
+            .field("sar_i2c_start", &self.sar_i2c_start())
+            .field("sar_i2c_start_force", &self.sar_i2c_start_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_I2C_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - RTC I2C control data. Active only when SENS_SAR_I2C_START_FORCE = 1."]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/sens/sar_slave_addr1.rs b/esp32s2-ulp/src/sens/sar_slave_addr1.rs
index a407f4c413..f15462ff00 100644
--- a/esp32s2-ulp/src/sens/sar_slave_addr1.rs
+++ b/esp32s2-ulp/src/sens/sar_slave_addr1.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR1")
-            .field(
-                "i2c_slave_addr1",
-                &format_args!("{}", self.i2c_slave_addr1().bits()),
-            )
-            .field(
-                "i2c_slave_addr0",
-                &format_args!("{}", self.i2c_slave_addr0().bits()),
-            )
-            .field(
-                "meas_status",
-                &format_args!("{}", self.meas_status().bits()),
-            )
+            .field("i2c_slave_addr1", &self.i2c_slave_addr1())
+            .field("i2c_slave_addr0", &self.i2c_slave_addr0())
+            .field("meas_status", &self.meas_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - RTC I2C slave address 1"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/sens/sar_slave_addr2.rs b/esp32s2-ulp/src/sens/sar_slave_addr2.rs
index 083364335d..c40f612256 100644
--- a/esp32s2-ulp/src/sens/sar_slave_addr2.rs
+++ b/esp32s2-ulp/src/sens/sar_slave_addr2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR2")
-            .field(
-                "i2c_slave_addr3",
-                &format_args!("{}", self.i2c_slave_addr3().bits()),
-            )
-            .field(
-                "i2c_slave_addr2",
-                &format_args!("{}", self.i2c_slave_addr2().bits()),
-            )
+            .field("i2c_slave_addr3", &self.i2c_slave_addr3())
+            .field("i2c_slave_addr2", &self.i2c_slave_addr2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - RTC I2C slave address 3"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/sens/sar_slave_addr3.rs b/esp32s2-ulp/src/sens/sar_slave_addr3.rs
index d7ea26ecfc..a83df9c413 100644
--- a/esp32s2-ulp/src/sens/sar_slave_addr3.rs
+++ b/esp32s2-ulp/src/sens/sar_slave_addr3.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR3")
-            .field(
-                "i2c_slave_addr5",
-                &format_args!("{}", self.i2c_slave_addr5().bits()),
-            )
-            .field(
-                "i2c_slave_addr4",
-                &format_args!("{}", self.i2c_slave_addr4().bits()),
-            )
+            .field("i2c_slave_addr5", &self.i2c_slave_addr5())
+            .field("i2c_slave_addr4", &self.i2c_slave_addr4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - RTC I2C slave address 5"]
     #[inline(always)]
diff --git a/esp32s2-ulp/src/sens/sar_slave_addr4.rs b/esp32s2-ulp/src/sens/sar_slave_addr4.rs
index 2e396b65ce..4dd4b99160 100644
--- a/esp32s2-ulp/src/sens/sar_slave_addr4.rs
+++ b/esp32s2-ulp/src/sens/sar_slave_addr4.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR4")
-            .field(
-                "i2c_slave_addr7",
-                &format_args!("{}", self.i2c_slave_addr7().bits()),
-            )
-            .field(
-                "i2c_slave_addr6",
-                &format_args!("{}", self.i2c_slave_addr6().bits()),
-            )
+            .field("i2c_slave_addr7", &self.i2c_slave_addr7())
+            .field("i2c_slave_addr6", &self.i2c_slave_addr6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - RTC I2C slave address 7"]
     #[inline(always)]
diff --git a/esp32s2/src/aes/aad_block_num.rs b/esp32s2/src/aes/aad_block_num.rs
index 723c62ff74..667a8a4f5d 100644
--- a/esp32s2/src/aes/aad_block_num.rs
+++ b/esp32s2/src/aes/aad_block_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AAD_BLOCK_NUM")
-            .field(
-                "aad_block_num",
-                &format_args!("{}", self.aad_block_num().bits()),
-            )
+            .field("aad_block_num", &self.aad_block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AAD_BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stores the ADD Block Number for the GCM operation."]
     #[inline(always)]
diff --git a/esp32s2/src/aes/block_mode.rs b/esp32s2/src/aes/block_mode.rs
index c49ac354ae..f50760abd5 100644
--- a/esp32s2/src/aes/block_mode.rs
+++ b/esp32s2/src/aes/block_mode.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLOCK_MODE")
-            .field("block_mode", &format_args!("{}", self.block_mode().bits()))
+            .field("block_mode", &self.block_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLOCK_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Defines the operation type of the AES Accelerator operating under the DMA-AES working mode. For details, see Table 8. &amp; 3'h0(BLOCK_MODE_ECB): ECB # 3'h1(BLOCK_MODE_CBC): CBC # 3'h2(BLOCK_MODE_OFB): OFB # 3'h3(BLOCK_MODE_CTR): CTR # 3'h4(BLOCK_MODE_CFB8): CFB-8 # 3'h5(BLOCK_MODE_CFB128): CFB-128 # 3'h6(BLOCK_MODE_GCM): GCM &amp;"]
     #[inline(always)]
diff --git a/esp32s2/src/aes/block_num.rs b/esp32s2/src/aes/block_num.rs
index 8fafade042..0470342a49 100644
--- a/esp32s2/src/aes/block_num.rs
+++ b/esp32s2/src/aes/block_num.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLOCK_NUM")
-            .field("block_num", &format_args!("{}", self.block_num().bits()))
+            .field("block_num", &self.block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stores the Block Number of plaintext or cipertext when the AES Accelerator operates under the DMA-AES working mode. For details, see Section 1.5.4."]
     #[inline(always)]
diff --git a/esp32s2/src/aes/date.rs b/esp32s2/src/aes/date.rs
index 9fc86aefc6..b898ea6753 100644
--- a/esp32s2/src/aes/date.rs
+++ b/esp32s2/src/aes/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/aes/dma_enable.rs b/esp32s2/src/aes/dma_enable.rs
index d522489cd1..f96c66257b 100644
--- a/esp32s2/src/aes/dma_enable.rs
+++ b/esp32s2/src/aes/dma_enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_ENABLE")
-            .field("dma_enable", &format_args!("{}", self.dma_enable().bit()))
+            .field("dma_enable", &self.dma_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Defines the working mode of the AES Accelerator. For details, see Table 1. 1'h0: typical AES operation 1'h1: DMA-AES operation"]
     #[inline(always)]
diff --git a/esp32s2/src/aes/endian.rs b/esp32s2/src/aes/endian.rs
index 1e2eaec835..9df8cf32bf 100644
--- a/esp32s2/src/aes/endian.rs
+++ b/esp32s2/src/aes/endian.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENDIAN")
-            .field("endian", &format_args!("{}", self.endian().bits()))
+            .field("endian", &self.endian())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENDIAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Defines the endianness of input and output texts. &amp; \\[1:0\\] key endian # \\[3:2\\] text_in endian or in_stream endian # \\[5:4\\] text_out endian or out_stream endian # &amp;"]
     #[inline(always)]
diff --git a/esp32s2/src/aes/h_mem.rs b/esp32s2/src/aes/h_mem.rs
index bf2b7ae479..71a2f91433 100644
--- a/esp32s2/src/aes/h_mem.rs
+++ b/esp32s2/src/aes/h_mem.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("H_MEM")
-            .field("h", &format_args!("{}", self.h().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("H_MEM").field("h", &self.h()).finish()
     }
 }
 #[doc = "GCM hash subkey\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s2/src/aes/inc_sel.rs b/esp32s2/src/aes/inc_sel.rs
index f1281eb0cd..5df444eea9 100644
--- a/esp32s2/src/aes/inc_sel.rs
+++ b/esp32s2/src/aes/inc_sel.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INC_SEL")
-            .field("inc_sel", &format_args!("{}", self.inc_sel().bit()))
+            .field("inc_sel", &self.inc_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INC_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC 32 or INC 128 ."]
     #[inline(always)]
diff --git a/esp32s2/src/aes/int_ena.rs b/esp32s2/src/aes/int_ena.rs
index 178423a1b0..dd0aea378d 100644
--- a/esp32s2/src/aes/int_ena.rs
+++ b/esp32s2/src/aes/int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("int_ena", &format_args!("{}", self.int_ena().bit()))
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable AES interrupt and 0 to disable interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/aes/iv_mem.rs b/esp32s2/src/aes/iv_mem.rs
index 7f38d44352..a8c1ce5d60 100644
--- a/esp32s2/src/aes/iv_mem.rs
+++ b/esp32s2/src/aes/iv_mem.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("IV_MEM")
-            .field("iv", &format_args!("{}", self.iv().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IV_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("IV_MEM").field("iv", &self.iv()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/aes/j0_mem.rs b/esp32s2/src/aes/j0_mem.rs
index de07f597f0..eea9808b66 100644
--- a/esp32s2/src/aes/j0_mem.rs
+++ b/esp32s2/src/aes/j0_mem.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("J0_MEM")
-            .field("j0", &format_args!("{}", self.j0().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<J0_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("J0_MEM").field("j0", &self.j0()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/aes/key.rs b/esp32s2/src/aes/key.rs
index 799ad14ec5..1ff250cbe3 100644
--- a/esp32s2/src/aes/key.rs
+++ b/esp32s2/src/aes/key.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("KEY")
-            .field("key", &format_args!("{}", self.key().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<KEY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("KEY").field("key", &self.key()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/aes/mode.rs b/esp32s2/src/aes/mode.rs
index d96998318b..5acd0d0763 100644
--- a/esp32s2/src/aes/mode.rs
+++ b/esp32s2/src/aes/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/aes/remainder_bit_num.rs b/esp32s2/src/aes/remainder_bit_num.rs
index a539f6aaaf..fccc82e03f 100644
--- a/esp32s2/src/aes/remainder_bit_num.rs
+++ b/esp32s2/src/aes/remainder_bit_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REMAINDER_BIT_NUM")
-            .field(
-                "remainder_bit_num",
-                &format_args!("{}", self.remainder_bit_num().bits()),
-            )
+            .field("remainder_bit_num", &self.remainder_bit_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REMAINDER_BIT_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Stores the Remainder Bit Number for the GCM operation."]
     #[inline(always)]
diff --git a/esp32s2/src/aes/state.rs b/esp32s2/src/aes/state.rs
index df84a61713..ba890147cb 100644
--- a/esp32s2/src/aes/state.rs
+++ b/esp32s2/src/aes/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("state", &format_args!("{}", self.state().bits()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Operation status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32s2/src/aes/t0_mem.rs b/esp32s2/src/aes/t0_mem.rs
index ebdbfd6700..61f06f1988 100644
--- a/esp32s2/src/aes/t0_mem.rs
+++ b/esp32s2/src/aes/t0_mem.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("T0_MEM")
-            .field("t0", &format_args!("{}", self.t0().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T0_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("T0_MEM").field("t0", &self.t0()).finish()
     }
 }
 #[doc = "T0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0_mem::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s2/src/aes/text_in.rs b/esp32s2/src/aes/text_in.rs
index 0c051b588c..5e65b00567 100644
--- a/esp32s2/src/aes/text_in.rs
+++ b/esp32s2/src/aes/text_in.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEXT_IN")
-            .field("text_in", &format_args!("{}", self.text_in().bits()))
+            .field("text_in", &self.text_in())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEXT_IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stores the source data when the AES Accelerator operates in the Typical AES working mode."]
     #[inline(always)]
diff --git a/esp32s2/src/aes/text_out.rs b/esp32s2/src/aes/text_out.rs
index b1f0e29413..85028e6b29 100644
--- a/esp32s2/src/aes/text_out.rs
+++ b/esp32s2/src/aes/text_out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEXT_OUT")
-            .field("text_out", &format_args!("{}", self.text_out().bits()))
+            .field("text_out", &self.text_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEXT_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stores the result data when the AES Accelerator operates in the Typical AES working mode."]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/apb_dac_ctrl.rs b/esp32s2/src/apb_saradc/apb_dac_ctrl.rs
index 5e349ca1e1..790937a747 100644
--- a/esp32s2/src/apb_saradc/apb_dac_ctrl.rs
+++ b/esp32s2/src/apb_saradc/apb_dac_ctrl.rs
@@ -62,24 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_DAC_CTRL")
-            .field(
-                "timer_target",
-                &format_args!("{}", self.timer_target().bits()),
-            )
-            .field("timer_en", &format_args!("{}", self.timer_en().bit()))
-            .field("alter_mode", &format_args!("{}", self.alter_mode().bit()))
-            .field("trans", &format_args!("{}", self.trans().bit()))
-            .field("reset_fifo", &format_args!("{}", self.reset_fifo().bit()))
-            .field("rst", &format_args!("{}", self.rst().bit()))
+            .field("timer_target", &self.timer_target())
+            .field("timer_en", &self.timer_en())
+            .field("alter_mode", &self.alter_mode())
+            .field("trans", &self.trans())
+            .field("reset_fifo", &self.reset_fifo())
+            .field("rst", &self.rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_DAC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - Set DAC timer target."]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/arb_ctrl.rs b/esp32s2/src/apb_saradc/arb_ctrl.rs
index eaf44c5e19..04a1a718a0 100644
--- a/esp32s2/src/apb_saradc/arb_ctrl.rs
+++ b/esp32s2/src/apb_saradc/arb_ctrl.rs
@@ -80,35 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_CTRL")
-            .field("apb_force", &format_args!("{}", self.apb_force().bit()))
-            .field("rtc_force", &format_args!("{}", self.rtc_force().bit()))
-            .field("wifi_force", &format_args!("{}", self.wifi_force().bit()))
-            .field("grant_force", &format_args!("{}", self.grant_force().bit()))
-            .field(
-                "apb_priority",
-                &format_args!("{}", self.apb_priority().bits()),
-            )
-            .field(
-                "rtc_priority",
-                &format_args!("{}", self.rtc_priority().bits()),
-            )
-            .field(
-                "wifi_priority",
-                &format_args!("{}", self.wifi_priority().bits()),
-            )
-            .field(
-                "fix_priority",
-                &format_args!("{}", self.fix_priority().bit()),
-            )
+            .field("apb_force", &self.apb_force())
+            .field("rtc_force", &self.rtc_force())
+            .field("wifi_force", &self.wifi_force())
+            .field("grant_force", &self.grant_force())
+            .field("apb_priority", &self.apb_priority())
+            .field("rtc_priority", &self.rtc_priority())
+            .field("wifi_priority", &self.wifi_priority())
+            .field("fix_priority", &self.fix_priority())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - ADC2 arbiter forces to enable DIG ADC2 CTRL."]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/clkm_conf.rs b/esp32s2/src/apb_saradc/clkm_conf.rs
index 6d1eb89599..7e9df4a48e 100644
--- a/esp32s2/src/apb_saradc/clkm_conf.rs
+++ b/esp32s2/src/apb_saradc/clkm_conf.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKM_CONF")
-            .field(
-                "clkm_div_num",
-                &format_args!("{}", self.clkm_div_num().bits()),
-            )
-            .field("clkm_div_b", &format_args!("{}", self.clkm_div_b().bits()))
-            .field("clkm_div_a", &format_args!("{}", self.clkm_div_a().bits()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bits()))
+            .field("clkm_div_num", &self.clkm_div_num())
+            .field("clkm_div_b", &self.clkm_div_b())
+            .field("clkm_div_a", &self.clkm_div_a())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral DIG_ADC clock divider value"]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/ctrl.rs b/esp32s2/src/apb_saradc/ctrl.rs
index 5035d00796..a428a3e081 100644
--- a/esp32s2/src/apb_saradc/ctrl.rs
+++ b/esp32s2/src/apb_saradc/ctrl.rs
@@ -134,56 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("start_force", &format_args!("{}", self.start_force().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("work_mode", &format_args!("{}", self.work_mode().bits()))
-            .field("sar_sel", &format_args!("{}", self.sar_sel().bit()))
-            .field(
-                "sar_clk_gated",
-                &format_args!("{}", self.sar_clk_gated().bit()),
-            )
-            .field(
-                "sar_clk_div",
-                &format_args!("{}", self.sar_clk_div().bits()),
-            )
-            .field(
-                "sar1_patt_len",
-                &format_args!("{}", self.sar1_patt_len().bits()),
-            )
-            .field(
-                "sar2_patt_len",
-                &format_args!("{}", self.sar2_patt_len().bits()),
-            )
-            .field(
-                "sar1_patt_p_clear",
-                &format_args!("{}", self.sar1_patt_p_clear().bit()),
-            )
-            .field(
-                "sar2_patt_p_clear",
-                &format_args!("{}", self.sar2_patt_p_clear().bit()),
-            )
-            .field(
-                "data_sar_sel",
-                &format_args!("{}", self.data_sar_sel().bit()),
-            )
-            .field("data_to_i2s", &format_args!("{}", self.data_to_i2s().bit()))
-            .field(
-                "xpd_sar_force",
-                &format_args!("{}", self.xpd_sar_force().bits()),
-            )
-            .field(
-                "wait_arb_cycle",
-                &format_args!("{}", self.wait_arb_cycle().bits()),
-            )
+            .field("start_force", &self.start_force())
+            .field("start", &self.start())
+            .field("work_mode", &self.work_mode())
+            .field("sar_sel", &self.sar_sel())
+            .field("sar_clk_gated", &self.sar_clk_gated())
+            .field("sar_clk_div", &self.sar_clk_div())
+            .field("sar1_patt_len", &self.sar1_patt_len())
+            .field("sar2_patt_len", &self.sar2_patt_len())
+            .field("sar1_patt_p_clear", &self.sar1_patt_p_clear())
+            .field("sar2_patt_p_clear", &self.sar2_patt_p_clear())
+            .field("data_sar_sel", &self.data_sar_sel())
+            .field("data_to_i2s", &self.data_to_i2s())
+            .field("xpd_sar_force", &self.xpd_sar_force())
+            .field("wait_arb_cycle", &self.wait_arb_cycle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 0: select FSM to start SAR ADC. 1: select software to start SAR ADC."]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/ctrl2.rs b/esp32s2/src/apb_saradc/ctrl2.rs
index 367422880d..931e8111be 100644
--- a/esp32s2/src/apb_saradc/ctrl2.rs
+++ b/esp32s2/src/apb_saradc/ctrl2.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field(
-                "meas_num_limit",
-                &format_args!("{}", self.meas_num_limit().bit()),
-            )
-            .field(
-                "max_meas_num",
-                &format_args!("{}", self.max_meas_num().bits()),
-            )
-            .field("sar1_inv", &format_args!("{}", self.sar1_inv().bit()))
-            .field("sar2_inv", &format_args!("{}", self.sar2_inv().bit()))
-            .field("timer_sel", &format_args!("{}", self.timer_sel().bit()))
-            .field(
-                "timer_target",
-                &format_args!("{}", self.timer_target().bits()),
-            )
-            .field("timer_en", &format_args!("{}", self.timer_en().bit()))
+            .field("meas_num_limit", &self.meas_num_limit())
+            .field("max_meas_num", &self.max_meas_num())
+            .field("sar1_inv", &self.sar1_inv())
+            .field("sar2_inv", &self.sar2_inv())
+            .field("timer_sel", &self.timer_sel())
+            .field("timer_target", &self.timer_target())
+            .field("timer_en", &self.timer_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable limit times of SAR ADC sample."]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/ctrl_date.rs b/esp32s2/src/apb_saradc/ctrl_date.rs
index 38cd64d999..ae28c1e3cc 100644
--- a/esp32s2/src/apb_saradc/ctrl_date.rs
+++ b/esp32s2/src/apb_saradc/ctrl_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL_DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Version control register"]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/dma_conf.rs b/esp32s2/src/apb_saradc/dma_conf.rs
index b74ea9f992..d28663d415 100644
--- a/esp32s2/src/apb_saradc/dma_conf.rs
+++ b/esp32s2/src/apb_saradc/dma_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field(
-                "adc_eof_num",
-                &format_args!("{}", self.adc_eof_num().bits()),
-            )
-            .field(
-                "adc_reset_fsm",
-                &format_args!("{}", self.adc_reset_fsm().bit()),
-            )
-            .field("adc_trans", &format_args!("{}", self.adc_trans().bit()))
+            .field("adc_eof_num", &self.adc_eof_num())
+            .field("adc_reset_fsm", &self.adc_reset_fsm())
+            .field("adc_trans", &self.adc_trans())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Generate dma_in_suc_eof when sample cnt = spi_eof_num."]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/filter_ctrl.rs b/esp32s2/src/apb_saradc/filter_ctrl.rs
index 1435727ad6..3d31ba6522 100644
--- a/esp32s2/src/apb_saradc/filter_ctrl.rs
+++ b/esp32s2/src/apb_saradc/filter_ctrl.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CTRL")
-            .field(
-                "adc2_filter_reset",
-                &format_args!("{}", self.adc2_filter_reset().bit()),
-            )
-            .field(
-                "adc1_filter_reset",
-                &format_args!("{}", self.adc1_filter_reset().bit()),
-            )
-            .field(
-                "adc2_filter_factor",
-                &format_args!("{}", self.adc2_filter_factor().bits()),
-            )
-            .field(
-                "adc1_filter_factor",
-                &format_args!("{}", self.adc1_filter_factor().bits()),
-            )
-            .field(
-                "adc2_filter_en",
-                &format_args!("{}", self.adc2_filter_en().bit()),
-            )
-            .field(
-                "adc1_filter_en",
-                &format_args!("{}", self.adc1_filter_en().bit()),
-            )
+            .field("adc2_filter_reset", &self.adc2_filter_reset())
+            .field("adc1_filter_reset", &self.adc1_filter_reset())
+            .field("adc2_filter_factor", &self.adc2_filter_factor())
+            .field("adc1_filter_factor", &self.adc1_filter_factor())
+            .field("adc2_filter_en", &self.adc2_filter_en())
+            .field("adc1_filter_en", &self.adc1_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reset ADC2 filter."]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/filter_status.rs b/esp32s2/src/apb_saradc/filter_status.rs
index adbf1212eb..11acee4048 100644
--- a/esp32s2/src/apb_saradc/filter_status.rs
+++ b/esp32s2/src/apb_saradc/filter_status.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_STATUS")
-            .field(
-                "adc2_filter_data",
-                &format_args!("{}", self.adc2_filter_data().bits()),
-            )
-            .field(
-                "adc1_filter_data",
-                &format_args!("{}", self.adc1_filter_data().bits()),
-            )
+            .field("adc2_filter_data", &self.adc2_filter_data())
+            .field("adc1_filter_data", &self.adc1_filter_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Data status of DIG ADC2 filter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filter_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FILTER_STATUS_SPEC;
 impl crate::RegisterSpec for FILTER_STATUS_SPEC {
diff --git a/esp32s2/src/apb_saradc/fsm.rs b/esp32s2/src/apb_saradc/fsm.rs
index e069e3252e..38dbcd52a3 100644
--- a/esp32s2/src/apb_saradc/fsm.rs
+++ b/esp32s2/src/apb_saradc/fsm.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM")
-            .field("sample_num", &format_args!("{}", self.sample_num().bits()))
-            .field(
-                "sample_cycle",
-                &format_args!("{}", self.sample_cycle().bits()),
-            )
+            .field("sample_num", &self.sample_num())
+            .field("sample_cycle", &self.sample_cycle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:23 - sample number"]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/fsm_wait.rs b/esp32s2/src/apb_saradc/fsm_wait.rs
index b017e6463d..180ddade22 100644
--- a/esp32s2/src/apb_saradc/fsm_wait.rs
+++ b/esp32s2/src/apb_saradc/fsm_wait.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_WAIT")
-            .field("xpd_wait", &format_args!("{}", self.xpd_wait().bits()))
-            .field("rstb_wait", &format_args!("{}", self.rstb_wait().bits()))
-            .field(
-                "standby_wait",
-                &format_args!("{}", self.standby_wait().bits()),
-            )
+            .field("xpd_wait", &self.xpd_wait())
+            .field("rstb_wait", &self.rstb_wait())
+            .field("standby_wait", &self.standby_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_WAIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - xpd wait"]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/int_ena.rs b/esp32s2/src/apb_saradc/int_ena.rs
index defbb6f69c..b52e2eca58 100644
--- a/esp32s2/src/apb_saradc/int_ena.rs
+++ b/esp32s2/src/apb_saradc/int_ena.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("adc2_thres", &format_args!("{}", self.adc2_thres().bit()))
-            .field("adc1_thres", &format_args!("{}", self.adc1_thres().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("adc2_thres", &self.adc2_thres())
+            .field("adc1_thres", &self.adc1_thres())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - Enable bit of APB_SARADC_ADC2_THRES_INT interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/int_raw.rs b/esp32s2/src/apb_saradc/int_raw.rs
index 60bf8f1736..a0eeaac30f 100644
--- a/esp32s2/src/apb_saradc/int_raw.rs
+++ b/esp32s2/src/apb_saradc/int_raw.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("adc2_thres", &format_args!("{}", self.adc2_thres().bit()))
-            .field("adc1_thres", &format_args!("{}", self.adc1_thres().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("adc2_thres", &self.adc2_thres())
+            .field("adc1_thres", &self.adc1_thres())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DIG ADC interrupt raw bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s2/src/apb_saradc/int_st.rs b/esp32s2/src/apb_saradc/int_st.rs
index ba32e952b0..fe8b6235c7 100644
--- a/esp32s2/src/apb_saradc/int_st.rs
+++ b/esp32s2/src/apb_saradc/int_st.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("adc2_thres", &format_args!("{}", self.adc2_thres().bit()))
-            .field("adc1_thres", &format_args!("{}", self.adc1_thres().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("adc2_thres", &self.adc2_thres())
+            .field("adc1_thres", &self.adc1_thres())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DIG ADC interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s2/src/apb_saradc/sar1_patt_tab1.rs b/esp32s2/src/apb_saradc/sar1_patt_tab1.rs
index e73da1f437..1f3de174ee 100644
--- a/esp32s2/src/apb_saradc/sar1_patt_tab1.rs
+++ b/esp32s2/src/apb_saradc/sar1_patt_tab1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_PATT_TAB1")
-            .field(
-                "sar1_patt_tab1",
-                &format_args!("{}", self.sar1_patt_tab1().bits()),
-            )
+            .field("sar1_patt_tab1", &self.sar1_patt_tab1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_PATT_TAB1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - item 0 ~ 3 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/sar1_patt_tab2.rs b/esp32s2/src/apb_saradc/sar1_patt_tab2.rs
index 471573bc12..ed6717dfe7 100644
--- a/esp32s2/src/apb_saradc/sar1_patt_tab2.rs
+++ b/esp32s2/src/apb_saradc/sar1_patt_tab2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_PATT_TAB2")
-            .field(
-                "sar1_patt_tab2",
-                &format_args!("{}", self.sar1_patt_tab2().bits()),
-            )
+            .field("sar1_patt_tab2", &self.sar1_patt_tab2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_PATT_TAB2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Item 4 ~ 7 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/sar1_patt_tab3.rs b/esp32s2/src/apb_saradc/sar1_patt_tab3.rs
index dd3de02445..ca1c275b09 100644
--- a/esp32s2/src/apb_saradc/sar1_patt_tab3.rs
+++ b/esp32s2/src/apb_saradc/sar1_patt_tab3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_PATT_TAB3")
-            .field(
-                "sar1_patt_tab3",
-                &format_args!("{}", self.sar1_patt_tab3().bits()),
-            )
+            .field("sar1_patt_tab3", &self.sar1_patt_tab3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_PATT_TAB3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Item 8 ~ 11 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/sar1_patt_tab4.rs b/esp32s2/src/apb_saradc/sar1_patt_tab4.rs
index e3cc884734..c0132a46ef 100644
--- a/esp32s2/src/apb_saradc/sar1_patt_tab4.rs
+++ b/esp32s2/src/apb_saradc/sar1_patt_tab4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_PATT_TAB4")
-            .field(
-                "sar1_patt_tab4",
-                &format_args!("{}", self.sar1_patt_tab4().bits()),
-            )
+            .field("sar1_patt_tab4", &self.sar1_patt_tab4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_PATT_TAB4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Item 12 ~ 15 for pattern table 1 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/sar1_status.rs b/esp32s2/src/apb_saradc/sar1_status.rs
index ee499d0010..417c07ade7 100644
--- a/esp32s2/src/apb_saradc/sar1_status.rs
+++ b/esp32s2/src/apb_saradc/sar1_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_STATUS")
-            .field(
-                "sar1_status",
-                &format_args!("{}", self.sar1_status().bits()),
-            )
+            .field("sar1_status", &self.sar1_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital adc1 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR1_STATUS_SPEC;
 impl crate::RegisterSpec for SAR1_STATUS_SPEC {
diff --git a/esp32s2/src/apb_saradc/sar2_patt_tab1.rs b/esp32s2/src/apb_saradc/sar2_patt_tab1.rs
index 4c4291251d..837d4693ba 100644
--- a/esp32s2/src/apb_saradc/sar2_patt_tab1.rs
+++ b/esp32s2/src/apb_saradc/sar2_patt_tab1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_PATT_TAB1")
-            .field(
-                "sar2_patt_tab1",
-                &format_args!("{}", self.sar2_patt_tab1().bits()),
-            )
+            .field("sar2_patt_tab1", &self.sar2_patt_tab1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_PATT_TAB1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - item 0 ~ 3 for pattern table 2 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/sar2_patt_tab2.rs b/esp32s2/src/apb_saradc/sar2_patt_tab2.rs
index 4b5756abc1..be2f6426e0 100644
--- a/esp32s2/src/apb_saradc/sar2_patt_tab2.rs
+++ b/esp32s2/src/apb_saradc/sar2_patt_tab2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_PATT_TAB2")
-            .field(
-                "sar2_patt_tab2",
-                &format_args!("{}", self.sar2_patt_tab2().bits()),
-            )
+            .field("sar2_patt_tab2", &self.sar2_patt_tab2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_PATT_TAB2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Item 4 ~ 7 for pattern table 2 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/sar2_patt_tab3.rs b/esp32s2/src/apb_saradc/sar2_patt_tab3.rs
index 937e6ec60c..2d45a5b3cc 100644
--- a/esp32s2/src/apb_saradc/sar2_patt_tab3.rs
+++ b/esp32s2/src/apb_saradc/sar2_patt_tab3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_PATT_TAB3")
-            .field(
-                "sar2_patt_tab3",
-                &format_args!("{}", self.sar2_patt_tab3().bits()),
-            )
+            .field("sar2_patt_tab3", &self.sar2_patt_tab3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_PATT_TAB3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Item 8 ~ 11 for pattern table 2 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/sar2_patt_tab4.rs b/esp32s2/src/apb_saradc/sar2_patt_tab4.rs
index d359cebd99..1ef9687f19 100644
--- a/esp32s2/src/apb_saradc/sar2_patt_tab4.rs
+++ b/esp32s2/src/apb_saradc/sar2_patt_tab4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_PATT_TAB4")
-            .field(
-                "sar2_patt_tab4",
-                &format_args!("{}", self.sar2_patt_tab4().bits()),
-            )
+            .field("sar2_patt_tab4", &self.sar2_patt_tab4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_PATT_TAB4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Item 12 ~ 15 for pattern table 2 (each item one byte)"]
     #[inline(always)]
diff --git a/esp32s2/src/apb_saradc/sar2_status.rs b/esp32s2/src/apb_saradc/sar2_status.rs
index be5701ec61..da2d8fbd69 100644
--- a/esp32s2/src/apb_saradc/sar2_status.rs
+++ b/esp32s2/src/apb_saradc/sar2_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_STATUS")
-            .field(
-                "sar2_status",
-                &format_args!("{}", self.sar2_status().bits()),
-            )
+            .field("sar2_status", &self.sar2_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "digital adc2 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR2_STATUS_SPEC;
 impl crate::RegisterSpec for SAR2_STATUS_SPEC {
diff --git a/esp32s2/src/apb_saradc/thres_ctrl.rs b/esp32s2/src/apb_saradc/thres_ctrl.rs
index 17c6ac17c3..7921fde0cf 100644
--- a/esp32s2/src/apb_saradc/thres_ctrl.rs
+++ b/esp32s2/src/apb_saradc/thres_ctrl.rs
@@ -71,34 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES_CTRL")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "adc2_thres_mode",
-                &format_args!("{}", self.adc2_thres_mode().bit()),
-            )
-            .field(
-                "adc1_thres_mode",
-                &format_args!("{}", self.adc1_thres_mode().bit()),
-            )
-            .field("adc2_thres", &format_args!("{}", self.adc2_thres().bits()))
-            .field("adc1_thres", &format_args!("{}", self.adc1_thres().bits()))
-            .field(
-                "adc2_thres_en",
-                &format_args!("{}", self.adc2_thres_en().bit()),
-            )
-            .field(
-                "adc1_thres_en",
-                &format_args!("{}", self.adc1_thres_en().bit()),
-            )
+            .field("clk_en", &self.clk_en())
+            .field("adc2_thres_mode", &self.adc2_thres_mode())
+            .field("adc1_thres_mode", &self.adc1_thres_mode())
+            .field("adc2_thres", &self.adc2_thres())
+            .field("adc1_thres", &self.adc1_thres())
+            .field("adc2_thres_en", &self.adc2_thres_en())
+            .field("adc1_thres_en", &self.adc1_thres_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Clock gate enable."]
     #[inline(always)]
diff --git a/esp32s2/src/bb/bbpd_ctrl.rs b/esp32s2/src/bb/bbpd_ctrl.rs
index 7e31e667bb..28cf2656e4 100644
--- a/esp32s2/src/bb/bbpd_ctrl.rs
+++ b/esp32s2/src/bb/bbpd_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BBPD_CTRL")
-            .field(
-                "dc_est_force_pd",
-                &format_args!("{}", self.dc_est_force_pd().bit()),
-            )
-            .field(
-                "dc_est_force_pu",
-                &format_args!("{}", self.dc_est_force_pu().bit()),
-            )
-            .field(
-                "fft_force_pd",
-                &format_args!("{}", self.fft_force_pd().bit()),
-            )
-            .field(
-                "fft_force_pu",
-                &format_args!("{}", self.fft_force_pu().bit()),
-            )
+            .field("dc_est_force_pd", &self.dc_est_force_pd())
+            .field("dc_est_force_pu", &self.dc_est_force_pu())
+            .field("fft_force_pd", &self.fft_force_pd())
+            .field("fft_force_pu", &self.fft_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BBPD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/dedicated_gpio/in_dly.rs b/esp32s2/src/dedicated_gpio/in_dly.rs
index 2ee636a066..4c0d40d68a 100644
--- a/esp32s2/src/dedicated_gpio/in_dly.rs
+++ b/esp32s2/src/dedicated_gpio/in_dly.rs
@@ -67,23 +67,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DLY")
-            .field("ch0", &format_args!("{}", self.ch0().bits()))
-            .field("ch1", &format_args!("{}", self.ch1().bits()))
-            .field("ch2", &format_args!("{}", self.ch2().bits()))
-            .field("ch3", &format_args!("{}", self.ch3().bits()))
-            .field("ch4", &format_args!("{}", self.ch4().bits()))
-            .field("ch5", &format_args!("{}", self.ch5().bits()))
-            .field("ch6", &format_args!("{}", self.ch6().bits()))
-            .field("ch7", &format_args!("{}", self.ch7().bits()))
+            .field("ch0", &self.ch0())
+            .field("ch1", &self.ch1())
+            .field("ch2", &self.ch2())
+            .field("ch3", &self.ch3())
+            .field("ch4", &self.ch4())
+            .field("ch5", &self.ch5())
+            .field("ch6", &self.ch6())
+            .field("ch7", &self.ch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DLY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Configure GPIO(0-7) input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay."]
     #[doc = ""]
diff --git a/esp32s2/src/dedicated_gpio/in_scan.rs b/esp32s2/src/dedicated_gpio/in_scan.rs
index b928939624..0f0eb764b5 100644
--- a/esp32s2/src/dedicated_gpio/in_scan.rs
+++ b/esp32s2/src/dedicated_gpio/in_scan.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_SCAN")
-            .field("in_status", &format_args!("{}", self.in_status().bits()))
+            .field("in_status", &self.in_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SCAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Dedicated GPIO input status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_scan::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SCAN_SPEC;
 impl crate::RegisterSpec for IN_SCAN_SPEC {
diff --git a/esp32s2/src/dedicated_gpio/intr_raw.rs b/esp32s2/src/dedicated_gpio/intr_raw.rs
index e036c4e68c..bae5021a46 100644
--- a/esp32s2/src/dedicated_gpio/intr_raw.rs
+++ b/esp32s2/src/dedicated_gpio/intr_raw.rs
@@ -63,23 +63,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_RAW")
-            .field("gpio0", &format_args!("{}", self.gpio0().bit()))
-            .field("gpio1", &format_args!("{}", self.gpio1().bit()))
-            .field("gpio2", &format_args!("{}", self.gpio2().bit()))
-            .field("gpio3", &format_args!("{}", self.gpio3().bit()))
-            .field("gpio4", &format_args!("{}", self.gpio4().bit()))
-            .field("gpio5", &format_args!("{}", self.gpio5().bit()))
-            .field("gpio6", &format_args!("{}", self.gpio6().bit()))
-            .field("gpio7", &format_args!("{}", self.gpio7().bit()))
+            .field("gpio0", &self.gpio0())
+            .field("gpio1", &self.gpio1())
+            .field("gpio2", &self.gpio2())
+            .field("gpio3", &self.gpio3())
+            .field("gpio4", &self.gpio4())
+            .field("gpio5", &self.gpio5())
+            .field("gpio6", &self.gpio6())
+            .field("gpio7", &self.gpio7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_RAW_SPEC;
 impl crate::RegisterSpec for INTR_RAW_SPEC {
diff --git a/esp32s2/src/dedicated_gpio/intr_rcgn.rs b/esp32s2/src/dedicated_gpio/intr_rcgn.rs
index 703308632d..2ec80a36e4 100644
--- a/esp32s2/src/dedicated_gpio/intr_rcgn.rs
+++ b/esp32s2/src/dedicated_gpio/intr_rcgn.rs
@@ -67,47 +67,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_RCGN")
-            .field(
-                "intr_mode_ch0",
-                &format_args!("{}", self.intr_mode_ch0().bits()),
-            )
-            .field(
-                "intr_mode_ch1",
-                &format_args!("{}", self.intr_mode_ch1().bits()),
-            )
-            .field(
-                "intr_mode_ch2",
-                &format_args!("{}", self.intr_mode_ch2().bits()),
-            )
-            .field(
-                "intr_mode_ch3",
-                &format_args!("{}", self.intr_mode_ch3().bits()),
-            )
-            .field(
-                "intr_mode_ch4",
-                &format_args!("{}", self.intr_mode_ch4().bits()),
-            )
-            .field(
-                "intr_mode_ch5",
-                &format_args!("{}", self.intr_mode_ch5().bits()),
-            )
-            .field(
-                "intr_mode_ch6",
-                &format_args!("{}", self.intr_mode_ch6().bits()),
-            )
-            .field(
-                "intr_mode_ch7",
-                &format_args!("{}", self.intr_mode_ch7().bits()),
-            )
+            .field("intr_mode_ch0", &self.intr_mode_ch0())
+            .field("intr_mode_ch1", &self.intr_mode_ch1())
+            .field("intr_mode_ch2", &self.intr_mode_ch2())
+            .field("intr_mode_ch3", &self.intr_mode_ch3())
+            .field("intr_mode_ch4", &self.intr_mode_ch4())
+            .field("intr_mode_ch5", &self.intr_mode_ch5())
+            .field("intr_mode_ch6", &self.intr_mode_ch6())
+            .field("intr_mode_ch7", &self.intr_mode_ch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_RCGN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Configure channel (0-7) interrupt generate mode. 0/1: do not generate interrupt. 2: low level trigger. 3: high level trigger. 4: falling edge trigger. 5: raising edge trigger. 6/7: falling and raising edge trigger."]
     #[doc = ""]
diff --git a/esp32s2/src/dedicated_gpio/intr_rls.rs b/esp32s2/src/dedicated_gpio/intr_rls.rs
index 93e74c7027..94190b0429 100644
--- a/esp32s2/src/dedicated_gpio/intr_rls.rs
+++ b/esp32s2/src/dedicated_gpio/intr_rls.rs
@@ -67,23 +67,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_RLS")
-            .field("gpio0", &format_args!("{}", self.gpio0().bit()))
-            .field("gpio1", &format_args!("{}", self.gpio1().bit()))
-            .field("gpio2", &format_args!("{}", self.gpio2().bit()))
-            .field("gpio3", &format_args!("{}", self.gpio3().bit()))
-            .field("gpio4", &format_args!("{}", self.gpio4().bit()))
-            .field("gpio5", &format_args!("{}", self.gpio5().bit()))
-            .field("gpio6", &format_args!("{}", self.gpio6().bit()))
-            .field("gpio7", &format_args!("{}", self.gpio7().bit()))
+            .field("gpio0", &self.gpio0())
+            .field("gpio1", &self.gpio1())
+            .field("gpio2", &self.gpio2())
+            .field("gpio3", &self.gpio3())
+            .field("gpio4", &self.gpio4())
+            .field("gpio5", &self.gpio5())
+            .field("gpio6", &self.gpio6())
+            .field("gpio7", &self.gpio7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_RLS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The enable bit for DEDIC_GPIO(0-7)_INT_ST register."]
     #[doc = ""]
diff --git a/esp32s2/src/dedicated_gpio/intr_st.rs b/esp32s2/src/dedicated_gpio/intr_st.rs
index 15957c0910..0cd44f86d9 100644
--- a/esp32s2/src/dedicated_gpio/intr_st.rs
+++ b/esp32s2/src/dedicated_gpio/intr_st.rs
@@ -63,23 +63,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTR_ST")
-            .field("gpio0", &format_args!("{}", self.gpio0().bit()))
-            .field("gpio1", &format_args!("{}", self.gpio1().bit()))
-            .field("gpio2", &format_args!("{}", self.gpio2().bit()))
-            .field("gpio3", &format_args!("{}", self.gpio3().bit()))
-            .field("gpio4", &format_args!("{}", self.gpio4().bit()))
-            .field("gpio5", &format_args!("{}", self.gpio5().bit()))
-            .field("gpio6", &format_args!("{}", self.gpio6().bit()))
-            .field("gpio7", &format_args!("{}", self.gpio7().bit()))
+            .field("gpio0", &self.gpio0())
+            .field("gpio1", &self.gpio1())
+            .field("gpio2", &self.gpio2())
+            .field("gpio3", &self.gpio3())
+            .field("gpio4", &self.gpio4())
+            .field("gpio5", &self.gpio5())
+            .field("gpio6", &self.gpio6())
+            .field("gpio7", &self.gpio7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTR_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTR_ST_SPEC;
 impl crate::RegisterSpec for INTR_ST_SPEC {
diff --git a/esp32s2/src/dedicated_gpio/out_cpu.rs b/esp32s2/src/dedicated_gpio/out_cpu.rs
index 3e7e3d03cd..8823dfe515 100644
--- a/esp32s2/src/dedicated_gpio/out_cpu.rs
+++ b/esp32s2/src/dedicated_gpio/out_cpu.rs
@@ -67,23 +67,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CPU")
-            .field("sel0", &format_args!("{}", self.sel0().bit()))
-            .field("sel1", &format_args!("{}", self.sel1().bit()))
-            .field("sel2", &format_args!("{}", self.sel2().bit()))
-            .field("sel3", &format_args!("{}", self.sel3().bit()))
-            .field("sel4", &format_args!("{}", self.sel4().bit()))
-            .field("sel5", &format_args!("{}", self.sel5().bit()))
-            .field("sel6", &format_args!("{}", self.sel6().bit()))
-            .field("sel7", &format_args!("{}", self.sel7().bit()))
+            .field("sel0", &self.sel0())
+            .field("sel1", &self.sel1())
+            .field("sel2", &self.sel2())
+            .field("sel3", &self.sel3())
+            .field("sel4", &self.sel4())
+            .field("sel5", &self.sel5())
+            .field("sel6", &self.sel6())
+            .field("sel7", &self.sel7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CPU_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Select GPIO out value configured by registers or CPU instructions for channel (0-7). 0: Configured by registers. 1: configured by CPU instructions."]
     #[doc = ""]
diff --git a/esp32s2/src/dedicated_gpio/out_scan.rs b/esp32s2/src/dedicated_gpio/out_scan.rs
index 996ec78b7e..2f77c4ebec 100644
--- a/esp32s2/src/dedicated_gpio/out_scan.rs
+++ b/esp32s2/src/dedicated_gpio/out_scan.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_SCAN")
-            .field("out_status", &format_args!("{}", self.out_status().bits()))
+            .field("out_status", &self.out_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_SCAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Dedicated GPIO output status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_scan::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_SCAN_SPEC;
 impl crate::RegisterSpec for OUT_SCAN_SPEC {
diff --git a/esp32s2/src/ds/c_mem.rs b/esp32s2/src/ds/c_mem.rs
index bd20281227..24584da4cf 100644
--- a/esp32s2/src/ds/c_mem.rs
+++ b/esp32s2/src/ds/c_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<C_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory C\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct C_MEM_SPEC;
diff --git a/esp32s2/src/ds/date.rs b/esp32s2/src/ds/date.rs
index 67c740f86a..879a5b60c9 100644
--- a/esp32s2/src/ds/date.rs
+++ b/esp32s2/src/ds/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/ds/query_busy.rs b/esp32s2/src/ds/query_busy.rs
index 5e721de05e..63078c3bc1 100644
--- a/esp32s2/src/ds/query_busy.rs
+++ b/esp32s2/src/ds/query_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_BUSY")
-            .field("query_busy", &format_args!("{}", self.query_busy().bit()))
+            .field("query_busy", &self.query_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of the DS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_BUSY_SPEC;
 impl crate::RegisterSpec for QUERY_BUSY_SPEC {
diff --git a/esp32s2/src/ds/query_check.rs b/esp32s2/src/ds/query_check.rs
index 43fee36df1..e16e9f90e8 100644
--- a/esp32s2/src/ds/query_check.rs
+++ b/esp32s2/src/ds/query_check.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_CHECK")
-            .field("md_error", &format_args!("{}", self.md_error().bit()))
-            .field("padding_bad", &format_args!("{}", self.padding_bad().bit()))
+            .field("md_error", &self.md_error())
+            .field("padding_bad", &self.padding_bad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_CHECK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Queries DS check result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_check::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_CHECK_SPEC;
 impl crate::RegisterSpec for QUERY_CHECK_SPEC {
diff --git a/esp32s2/src/ds/query_key_wrong.rs b/esp32s2/src/ds/query_key_wrong.rs
index d05e561620..9e6fbeebcc 100644
--- a/esp32s2/src/ds/query_key_wrong.rs
+++ b/esp32s2/src/ds/query_key_wrong.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_KEY_WRONG")
-            .field(
-                "query_key_wrong",
-                &format_args!("{}", self.query_key_wrong().bits()),
-            )
+            .field("query_key_wrong", &self.query_key_wrong())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_KEY_WRONG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Checks the reason why DS_KEY is not ready.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_key_wrong::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_KEY_WRONG_SPEC;
 impl crate::RegisterSpec for QUERY_KEY_WRONG_SPEC {
diff --git a/esp32s2/src/ds/x_mem.rs b/esp32s2/src/ds/x_mem.rs
index 3f950862b6..346779d8d3 100644
--- a/esp32s2/src/ds/x_mem.rs
+++ b/esp32s2/src/ds/x_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<X_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory X\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`x_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`x_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct X_MEM_SPEC;
diff --git a/esp32s2/src/ds/z_mem.rs b/esp32s2/src/ds/z_mem.rs
index f08e9e2e70..3418c817a0 100644
--- a/esp32s2/src/ds/z_mem.rs
+++ b/esp32s2/src/ds/z_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Z_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "memory Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Z_MEM_SPEC;
diff --git a/esp32s2/src/efuse/clk.rs b/esp32s2/src/efuse/clk.rs
index 63918d13d2..e90eb1e6b7 100644
--- a/esp32s2/src/efuse/clk.rs
+++ b/esp32s2/src/efuse/clk.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK")
-            .field(
-                "efuse_mem_force_pd",
-                &format_args!("{}", self.efuse_mem_force_pd().bit()),
-            )
-            .field(
-                "mem_clk_force_on",
-                &format_args!("{}", self.mem_clk_force_on().bit()),
-            )
-            .field(
-                "efuse_mem_force_pu",
-                &format_args!("{}", self.efuse_mem_force_pu().bit()),
-            )
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("efuse_mem_force_pd", &self.efuse_mem_force_pd())
+            .field("mem_clk_force_on", &self.mem_clk_force_on())
+            .field("efuse_mem_force_pu", &self.efuse_mem_force_pu())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - If set, forces eFuse SRAM into power-saving mode."]
     #[inline(always)]
diff --git a/esp32s2/src/efuse/cmd.rs b/esp32s2/src/efuse/cmd.rs
index 8dee79bc65..094d443be3 100644
--- a/esp32s2/src/efuse/cmd.rs
+++ b/esp32s2/src/efuse/cmd.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("read_cmd", &format_args!("{}", self.read_cmd().bit()))
-            .field("pgm_cmd", &format_args!("{}", self.pgm_cmd().bit()))
-            .field("blk_num", &format_args!("{}", self.blk_num().bits()))
+            .field("read_cmd", &self.read_cmd())
+            .field("pgm_cmd", &self.pgm_cmd())
+            .field("blk_num", &self.blk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to send read command."]
     #[inline(always)]
diff --git a/esp32s2/src/efuse/conf.rs b/esp32s2/src/efuse/conf.rs
index 65c19e73f7..817962d976 100644
--- a/esp32s2/src/efuse/conf.rs
+++ b/esp32s2/src/efuse/conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("op_code", &format_args!("{}", self.op_code().bits()))
+            .field("op_code", &self.op_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - 0x5A5A: Operate programming command. 0x5AA5: Operate read command."]
     #[inline(always)]
diff --git a/esp32s2/src/efuse/dac_conf.rs b/esp32s2/src/efuse/dac_conf.rs
index 46081e022e..e9db91d486 100644
--- a/esp32s2/src/efuse/dac_conf.rs
+++ b/esp32s2/src/efuse/dac_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DAC_CONF")
-            .field(
-                "dac_clk_div",
-                &format_args!("{}", self.dac_clk_div().bits()),
-            )
-            .field(
-                "dac_clk_pad_sel",
-                &format_args!("{}", self.dac_clk_pad_sel().bit()),
-            )
-            .field("dac_num", &format_args!("{}", self.dac_num().bits()))
-            .field("oe_clr", &format_args!("{}", self.oe_clr().bit()))
+            .field("dac_clk_div", &self.dac_clk_div())
+            .field("dac_clk_pad_sel", &self.dac_clk_pad_sel())
+            .field("dac_num", &self.dac_num())
+            .field("oe_clr", &self.oe_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DAC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Controls the division factor of the rising clock of the programming voltage."]
     #[inline(always)]
diff --git a/esp32s2/src/efuse/date.rs b/esp32s2/src/efuse/date.rs
index 0a901a1352..034916c375 100644
--- a/esp32s2/src/efuse/date.rs
+++ b/esp32s2/src/efuse/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/efuse/int_ena.rs b/esp32s2/src/efuse/int_ena.rs
index 6386df2821..0020c7e668 100644
--- a/esp32s2/src/efuse/int_ena.rs
+++ b/esp32s2/src/efuse/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable signal for read_done interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/efuse/int_raw.rs b/esp32s2/src/efuse/int_raw.rs
index b69c288afb..efd8b89205 100644
--- a/esp32s2/src/efuse/int_raw.rs
+++ b/esp32s2/src/efuse/int_raw.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse raw interrupt register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s2/src/efuse/int_st.rs b/esp32s2/src/efuse/int_st.rs
index 898ceb8e8b..efba508ff2 100644
--- a/esp32s2/src/efuse/int_st.rs
+++ b/esp32s2/src/efuse/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s2/src/efuse/pgm_check_value.rs b/esp32s2/src/efuse/pgm_check_value.rs
index f19454083b..b8493c9f12 100644
--- a/esp32s2/src/efuse/pgm_check_value.rs
+++ b/esp32s2/src/efuse/pgm_check_value.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE")
-            .field(
-                "pgm_rs_data",
-                &format_args!("{}", self.pgm_rs_data().bits()),
-            )
+            .field("pgm_rs_data", &self.pgm_rs_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the %sth 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32s2/src/efuse/pgm_data.rs b/esp32s2/src/efuse/pgm_data.rs
index ab62c2180f..4a42795ebc 100644
--- a/esp32s2/src/efuse/pgm_data.rs
+++ b/esp32s2/src/efuse/pgm_data.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA")
-            .field("pgm_data", &format_args!("{}", self.pgm_data().bits()))
+            .field("pgm_data", &self.pgm_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the %sth 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32s2/src/efuse/rd_key0_data.rs b/esp32s2/src/efuse/rd_key0_data.rs
index 8cff8646d3..c742a2d811 100644
--- a/esp32s2/src/efuse/rd_key0_data.rs
+++ b/esp32s2/src/efuse/rd_key0_data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA")
-            .field("key0_data", &format_args!("{}", self.key0_data().bits()))
+            .field("key0_data", &self.key0_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register %s of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA_SPEC {
diff --git a/esp32s2/src/efuse/rd_key1_data.rs b/esp32s2/src/efuse/rd_key1_data.rs
index ffef5b37aa..f6f4f9830c 100644
--- a/esp32s2/src/efuse/rd_key1_data.rs
+++ b/esp32s2/src/efuse/rd_key1_data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA")
-            .field("key1_data", &format_args!("{}", self.key1_data().bits()))
+            .field("key1_data", &self.key1_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register %s of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA_SPEC {
diff --git a/esp32s2/src/efuse/rd_key2_data.rs b/esp32s2/src/efuse/rd_key2_data.rs
index a5f3526ffa..9aca627f2a 100644
--- a/esp32s2/src/efuse/rd_key2_data.rs
+++ b/esp32s2/src/efuse/rd_key2_data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA")
-            .field("key2_data", &format_args!("{}", self.key2_data().bits()))
+            .field("key2_data", &self.key2_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register %s of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA_SPEC {
diff --git a/esp32s2/src/efuse/rd_key3_data.rs b/esp32s2/src/efuse/rd_key3_data.rs
index e3b6040eb1..487af75f63 100644
--- a/esp32s2/src/efuse/rd_key3_data.rs
+++ b/esp32s2/src/efuse/rd_key3_data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA")
-            .field("key3_data", &format_args!("{}", self.key3_data().bits()))
+            .field("key3_data", &self.key3_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register %s of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA_SPEC {
diff --git a/esp32s2/src/efuse/rd_key4_data.rs b/esp32s2/src/efuse/rd_key4_data.rs
index c41f3c88d2..0f77282730 100644
--- a/esp32s2/src/efuse/rd_key4_data.rs
+++ b/esp32s2/src/efuse/rd_key4_data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA")
-            .field("key4_data", &format_args!("{}", self.key4_data().bits()))
+            .field("key4_data", &self.key4_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register %s of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA_SPEC {
diff --git a/esp32s2/src/efuse/rd_key5_data.rs b/esp32s2/src/efuse/rd_key5_data.rs
index 83cbeb5eeb..3b9bae2de3 100644
--- a/esp32s2/src/efuse/rd_key5_data.rs
+++ b/esp32s2/src/efuse/rd_key5_data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA")
-            .field("key5_data", &format_args!("{}", self.key5_data().bits()))
+            .field("key5_data", &self.key5_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register %s of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA_SPEC {
diff --git a/esp32s2/src/efuse/rd_mac_spi_sys_0.rs b/esp32s2/src/efuse/rd_mac_spi_sys_0.rs
index 58cd0451ca..25b911755a 100644
--- a/esp32s2/src/efuse/rd_mac_spi_sys_0.rs
+++ b/esp32s2/src/efuse/rd_mac_spi_sys_0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_0")
-            .field("mac_0", &format_args!("{}", self.mac_0().bits()))
+            .field("mac_0", &self.mac_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_0_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_0_SPEC {
diff --git a/esp32s2/src/efuse/rd_mac_spi_sys_1.rs b/esp32s2/src/efuse/rd_mac_spi_sys_1.rs
index 1dcad5c47c..995db68544 100644
--- a/esp32s2/src/efuse/rd_mac_spi_sys_1.rs
+++ b/esp32s2/src/efuse/rd_mac_spi_sys_1.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_1")
-            .field("mac_1", &format_args!("{}", self.mac_1().bits()))
-            .field(
-                "spi_pad_conf_0",
-                &format_args!("{}", self.spi_pad_conf_0().bits()),
-            )
+            .field("mac_1", &self.mac_1())
+            .field("spi_pad_conf_0", &self.spi_pad_conf_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_1_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_1_SPEC {
diff --git a/esp32s2/src/efuse/rd_mac_spi_sys_2.rs b/esp32s2/src/efuse/rd_mac_spi_sys_2.rs
index dedb6201eb..533b6640f1 100644
--- a/esp32s2/src/efuse/rd_mac_spi_sys_2.rs
+++ b/esp32s2/src/efuse/rd_mac_spi_sys_2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_2")
-            .field(
-                "spi_pad_conf_1",
-                &format_args!("{}", self.spi_pad_conf_1().bits()),
-            )
+            .field("spi_pad_conf_1", &self.spi_pad_conf_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_2_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_2_SPEC {
diff --git a/esp32s2/src/efuse/rd_mac_spi_sys_3.rs b/esp32s2/src/efuse/rd_mac_spi_sys_3.rs
index 4f87562a4b..0e5ec60ced 100644
--- a/esp32s2/src/efuse/rd_mac_spi_sys_3.rs
+++ b/esp32s2/src/efuse/rd_mac_spi_sys_3.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_3")
-            .field(
-                "spi_pad_conf_2",
-                &format_args!("{}", self.spi_pad_conf_2().bits()),
-            )
-            .field(
-                "sys_data_part0_0",
-                &format_args!("{}", self.sys_data_part0_0().bits()),
-            )
+            .field("spi_pad_conf_2", &self.spi_pad_conf_2())
+            .field("sys_data_part0_0", &self.sys_data_part0_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_3_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_3_SPEC {
diff --git a/esp32s2/src/efuse/rd_mac_spi_sys_4.rs b/esp32s2/src/efuse/rd_mac_spi_sys_4.rs
index eaf4dfb9b8..6798d7aea6 100644
--- a/esp32s2/src/efuse/rd_mac_spi_sys_4.rs
+++ b/esp32s2/src/efuse/rd_mac_spi_sys_4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_4")
-            .field(
-                "sys_data_part0_1",
-                &format_args!("{}", self.sys_data_part0_1().bits()),
-            )
+            .field("sys_data_part0_1", &self.sys_data_part0_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_4_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_4_SPEC {
diff --git a/esp32s2/src/efuse/rd_mac_spi_sys_5.rs b/esp32s2/src/efuse/rd_mac_spi_sys_5.rs
index 279a6a6356..38d81943a6 100644
--- a/esp32s2/src/efuse/rd_mac_spi_sys_5.rs
+++ b/esp32s2/src/efuse/rd_mac_spi_sys_5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_5")
-            .field(
-                "sys_data_part0_2",
-                &format_args!("{}", self.sys_data_part0_2().bits()),
-            )
+            .field("sys_data_part0_2", &self.sys_data_part0_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_5_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_5_SPEC {
diff --git a/esp32s2/src/efuse/rd_repeat_data0.rs b/esp32s2/src/efuse/rd_repeat_data0.rs
index 9ceffd3d47..f71eabdad4 100644
--- a/esp32s2/src/efuse/rd_repeat_data0.rs
+++ b/esp32s2/src/efuse/rd_repeat_data0.rs
@@ -160,82 +160,34 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA0")
-            .field("rd_dis", &format_args!("{}", self.rd_dis().bits()))
-            .field(
-                "dis_rtc_ram_boot",
-                &format_args!("{}", self.dis_rtc_ram_boot().bit()),
-            )
-            .field("dis_icache", &format_args!("{}", self.dis_icache().bit()))
-            .field("dis_dcache", &format_args!("{}", self.dis_dcache().bit()))
-            .field(
-                "dis_download_icache",
-                &format_args!("{}", self.dis_download_icache().bit()),
-            )
-            .field(
-                "dis_download_dcache",
-                &format_args!("{}", self.dis_download_dcache().bit()),
-            )
-            .field(
-                "dis_force_download",
-                &format_args!("{}", self.dis_force_download().bit()),
-            )
-            .field("dis_usb", &format_args!("{}", self.dis_usb().bit()))
-            .field("dis_can", &format_args!("{}", self.dis_can().bit()))
-            .field(
-                "dis_boot_remap",
-                &format_args!("{}", self.dis_boot_remap().bit()),
-            )
-            .field(
-                "rpt4_reserved5",
-                &format_args!("{}", self.rpt4_reserved5().bit()),
-            )
-            .field(
-                "soft_dis_jtag",
-                &format_args!("{}", self.soft_dis_jtag().bit()),
-            )
-            .field(
-                "hard_dis_jtag",
-                &format_args!("{}", self.hard_dis_jtag().bit()),
-            )
+            .field("rd_dis", &self.rd_dis())
+            .field("dis_rtc_ram_boot", &self.dis_rtc_ram_boot())
+            .field("dis_icache", &self.dis_icache())
+            .field("dis_dcache", &self.dis_dcache())
+            .field("dis_download_icache", &self.dis_download_icache())
+            .field("dis_download_dcache", &self.dis_download_dcache())
+            .field("dis_force_download", &self.dis_force_download())
+            .field("dis_usb", &self.dis_usb())
+            .field("dis_can", &self.dis_can())
+            .field("dis_boot_remap", &self.dis_boot_remap())
+            .field("rpt4_reserved5", &self.rpt4_reserved5())
+            .field("soft_dis_jtag", &self.soft_dis_jtag())
+            .field("hard_dis_jtag", &self.hard_dis_jtag())
             .field(
                 "dis_download_manual_encrypt",
-                &format_args!("{}", self.dis_download_manual_encrypt().bit()),
-            )
-            .field("usb_drefh", &format_args!("{}", self.usb_drefh().bits()))
-            .field("usb_drefl", &format_args!("{}", self.usb_drefl().bits()))
-            .field(
-                "usb_exchg_pins",
-                &format_args!("{}", self.usb_exchg_pins().bit()),
-            )
-            .field(
-                "ext_phy_enable",
-                &format_args!("{}", self.ext_phy_enable().bit()),
-            )
-            .field(
-                "usb_force_nopersist",
-                &format_args!("{}", self.usb_force_nopersist().bit()),
-            )
-            .field(
-                "rpt4_reserved0",
-                &format_args!("{}", self.rpt4_reserved0().bits()),
-            )
-            .field(
-                "vdd_spi_modecurlim",
-                &format_args!("{}", self.vdd_spi_modecurlim().bit()),
-            )
-            .field(
-                "vdd_spi_drefh",
-                &format_args!("{}", self.vdd_spi_drefh().bits()),
+                &self.dis_download_manual_encrypt(),
             )
+            .field("usb_drefh", &self.usb_drefh())
+            .field("usb_drefl", &self.usb_drefl())
+            .field("usb_exchg_pins", &self.usb_exchg_pins())
+            .field("ext_phy_enable", &self.ext_phy_enable())
+            .field("usb_force_nopersist", &self.usb_force_nopersist())
+            .field("rpt4_reserved0", &self.rpt4_reserved0())
+            .field("vdd_spi_modecurlim", &self.vdd_spi_modecurlim())
+            .field("vdd_spi_drefh", &self.vdd_spi_drefh())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA0_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA0_SPEC {
diff --git a/esp32s2/src/efuse/rd_repeat_data1.rs b/esp32s2/src/efuse/rd_repeat_data1.rs
index 9d0b4ba58e..f2ba34b3c4 100644
--- a/esp32s2/src/efuse/rd_repeat_data1.rs
+++ b/esp32s2/src/efuse/rd_repeat_data1.rs
@@ -125,80 +125,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA1")
-            .field(
-                "vdd_spi_drefm",
-                &format_args!("{}", self.vdd_spi_drefm().bits()),
-            )
-            .field(
-                "vdd_spi_drefl",
-                &format_args!("{}", self.vdd_spi_drefl().bits()),
-            )
-            .field("vdd_spi_xpd", &format_args!("{}", self.vdd_spi_xpd().bit()))
-            .field(
-                "vdd_spi_tieh",
-                &format_args!("{}", self.vdd_spi_tieh().bit()),
-            )
-            .field(
-                "vdd_spi_force",
-                &format_args!("{}", self.vdd_spi_force().bit()),
-            )
-            .field(
-                "vdd_spi_en_init",
-                &format_args!("{}", self.vdd_spi_en_init().bit()),
-            )
-            .field(
-                "vdd_spi_encurlim",
-                &format_args!("{}", self.vdd_spi_encurlim().bit()),
-            )
-            .field(
-                "vdd_spi_dcurlim",
-                &format_args!("{}", self.vdd_spi_dcurlim().bits()),
-            )
-            .field(
-                "vdd_spi_init",
-                &format_args!("{}", self.vdd_spi_init().bits()),
-            )
-            .field(
-                "vdd_spi_dcap",
-                &format_args!("{}", self.vdd_spi_dcap().bits()),
-            )
-            .field(
-                "wdt_delay_sel",
-                &format_args!("{}", self.wdt_delay_sel().bits()),
-            )
-            .field(
-                "spi_boot_crypt_cnt",
-                &format_args!("{}", self.spi_boot_crypt_cnt().bits()),
-            )
-            .field(
-                "secure_boot_key_revoke0",
-                &format_args!("{}", self.secure_boot_key_revoke0().bit()),
-            )
-            .field(
-                "secure_boot_key_revoke1",
-                &format_args!("{}", self.secure_boot_key_revoke1().bit()),
-            )
-            .field(
-                "secure_boot_key_revoke2",
-                &format_args!("{}", self.secure_boot_key_revoke2().bit()),
-            )
-            .field(
-                "key_purpose_0",
-                &format_args!("{}", self.key_purpose_0().bits()),
-            )
-            .field(
-                "key_purpose_1",
-                &format_args!("{}", self.key_purpose_1().bits()),
-            )
+            .field("vdd_spi_drefm", &self.vdd_spi_drefm())
+            .field("vdd_spi_drefl", &self.vdd_spi_drefl())
+            .field("vdd_spi_xpd", &self.vdd_spi_xpd())
+            .field("vdd_spi_tieh", &self.vdd_spi_tieh())
+            .field("vdd_spi_force", &self.vdd_spi_force())
+            .field("vdd_spi_en_init", &self.vdd_spi_en_init())
+            .field("vdd_spi_encurlim", &self.vdd_spi_encurlim())
+            .field("vdd_spi_dcurlim", &self.vdd_spi_dcurlim())
+            .field("vdd_spi_init", &self.vdd_spi_init())
+            .field("vdd_spi_dcap", &self.vdd_spi_dcap())
+            .field("wdt_delay_sel", &self.wdt_delay_sel())
+            .field("spi_boot_crypt_cnt", &self.spi_boot_crypt_cnt())
+            .field("secure_boot_key_revoke0", &self.secure_boot_key_revoke0())
+            .field("secure_boot_key_revoke1", &self.secure_boot_key_revoke1())
+            .field("secure_boot_key_revoke2", &self.secure_boot_key_revoke2())
+            .field("key_purpose_0", &self.key_purpose_0())
+            .field("key_purpose_1", &self.key_purpose_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA1_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA1_SPEC {
diff --git a/esp32s2/src/efuse/rd_repeat_data2.rs b/esp32s2/src/efuse/rd_repeat_data2.rs
index 8bfd3f6d14..e474a0d66d 100644
--- a/esp32s2/src/efuse/rd_repeat_data2.rs
+++ b/esp32s2/src/efuse/rd_repeat_data2.rs
@@ -69,48 +69,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA2")
-            .field(
-                "key_purpose_2",
-                &format_args!("{}", self.key_purpose_2().bits()),
-            )
-            .field(
-                "key_purpose_3",
-                &format_args!("{}", self.key_purpose_3().bits()),
-            )
-            .field(
-                "key_purpose_4",
-                &format_args!("{}", self.key_purpose_4().bits()),
-            )
-            .field(
-                "key_purpose_5",
-                &format_args!("{}", self.key_purpose_5().bits()),
-            )
-            .field(
-                "key_purpose_6",
-                &format_args!("{}", self.key_purpose_6().bits()),
-            )
-            .field(
-                "secure_boot_en",
-                &format_args!("{}", self.secure_boot_en().bit()),
-            )
+            .field("key_purpose_2", &self.key_purpose_2())
+            .field("key_purpose_3", &self.key_purpose_3())
+            .field("key_purpose_4", &self.key_purpose_4())
+            .field("key_purpose_5", &self.key_purpose_5())
+            .field("key_purpose_6", &self.key_purpose_6())
+            .field("secure_boot_en", &self.secure_boot_en())
             .field(
                 "secure_boot_aggressive_revoke",
-                &format_args!("{}", self.secure_boot_aggressive_revoke().bit()),
-            )
-            .field(
-                "rpt4_reserved1",
-                &format_args!("{}", self.rpt4_reserved1().bits()),
+                &self.secure_boot_aggressive_revoke(),
             )
-            .field("flash_tpuw", &format_args!("{}", self.flash_tpuw().bits()))
+            .field("rpt4_reserved1", &self.rpt4_reserved1())
+            .field("flash_tpuw", &self.flash_tpuw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA2_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA2_SPEC {
diff --git a/esp32s2/src/efuse/rd_repeat_data3.rs b/esp32s2/src/efuse/rd_repeat_data3.rs
index ec907da212..c66f2a8e0d 100644
--- a/esp32s2/src/efuse/rd_repeat_data3.rs
+++ b/esp32s2/src/efuse/rd_repeat_data3.rs
@@ -90,60 +90,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA3")
-            .field(
-                "dis_download_mode",
-                &format_args!("{}", self.dis_download_mode().bit()),
-            )
-            .field(
-                "dis_legacy_spi_boot",
-                &format_args!("{}", self.dis_legacy_spi_boot().bit()),
-            )
-            .field(
-                "uart_print_channel",
-                &format_args!("{}", self.uart_print_channel().bit()),
-            )
-            .field(
-                "rpt4_reserved3",
-                &format_args!("{}", self.rpt4_reserved3().bit()),
-            )
-            .field(
-                "dis_usb_download_mode",
-                &format_args!("{}", self.dis_usb_download_mode().bit()),
-            )
-            .field(
-                "enable_security_download",
-                &format_args!("{}", self.enable_security_download().bit()),
-            )
-            .field(
-                "uart_print_control",
-                &format_args!("{}", self.uart_print_control().bits()),
-            )
-            .field(
-                "pin_power_selection",
-                &format_args!("{}", self.pin_power_selection().bit()),
-            )
-            .field("flash_type", &format_args!("{}", self.flash_type().bit()))
-            .field(
-                "force_send_resume",
-                &format_args!("{}", self.force_send_resume().bit()),
-            )
-            .field(
-                "secure_version",
-                &format_args!("{}", self.secure_version().bits()),
-            )
-            .field(
-                "rpt4_reserved2",
-                &format_args!("{}", self.rpt4_reserved2().bits()),
-            )
+            .field("dis_download_mode", &self.dis_download_mode())
+            .field("dis_legacy_spi_boot", &self.dis_legacy_spi_boot())
+            .field("uart_print_channel", &self.uart_print_channel())
+            .field("rpt4_reserved3", &self.rpt4_reserved3())
+            .field("dis_usb_download_mode", &self.dis_usb_download_mode())
+            .field("enable_security_download", &self.enable_security_download())
+            .field("uart_print_control", &self.uart_print_control())
+            .field("pin_power_selection", &self.pin_power_selection())
+            .field("flash_type", &self.flash_type())
+            .field("force_send_resume", &self.force_send_resume())
+            .field("secure_version", &self.secure_version())
+            .field("rpt4_reserved2", &self.rpt4_reserved2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA3_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA3_SPEC {
diff --git a/esp32s2/src/efuse/rd_repeat_data4.rs b/esp32s2/src/efuse/rd_repeat_data4.rs
index f955fddc25..536be70dad 100644
--- a/esp32s2/src/efuse/rd_repeat_data4.rs
+++ b/esp32s2/src/efuse/rd_repeat_data4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA4")
-            .field(
-                "rpt4_reserved4",
-                &format_args!("{}", self.rpt4_reserved4().bits()),
-            )
+            .field("rpt4_reserved4", &self.rpt4_reserved4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA4_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA4_SPEC {
diff --git a/esp32s2/src/efuse/rd_repeat_err0.rs b/esp32s2/src/efuse/rd_repeat_err0.rs
index 205eaf8092..130b02a28c 100644
--- a/esp32s2/src/efuse/rd_repeat_err0.rs
+++ b/esp32s2/src/efuse/rd_repeat_err0.rs
@@ -160,94 +160,34 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR0")
-            .field("rd_dis_err", &format_args!("{}", self.rd_dis_err().bits()))
-            .field(
-                "dis_rtc_ram_boot_err",
-                &format_args!("{}", self.dis_rtc_ram_boot_err().bit()),
-            )
-            .field(
-                "dis_icache_err",
-                &format_args!("{}", self.dis_icache_err().bit()),
-            )
-            .field(
-                "dis_dcache_err",
-                &format_args!("{}", self.dis_dcache_err().bit()),
-            )
-            .field(
-                "dis_download_icache_err",
-                &format_args!("{}", self.dis_download_icache_err().bit()),
-            )
-            .field(
-                "dis_download_dcache_err",
-                &format_args!("{}", self.dis_download_dcache_err().bit()),
-            )
-            .field(
-                "dis_force_download_err",
-                &format_args!("{}", self.dis_force_download_err().bit()),
-            )
-            .field("dis_usb_err", &format_args!("{}", self.dis_usb_err().bit()))
-            .field("dis_can_err", &format_args!("{}", self.dis_can_err().bit()))
-            .field(
-                "dis_boot_remap_err",
-                &format_args!("{}", self.dis_boot_remap_err().bit()),
-            )
-            .field(
-                "rpt4_reserved5_err",
-                &format_args!("{}", self.rpt4_reserved5_err().bit()),
-            )
-            .field(
-                "soft_dis_jtag_err",
-                &format_args!("{}", self.soft_dis_jtag_err().bit()),
-            )
-            .field(
-                "hard_dis_jtag_err",
-                &format_args!("{}", self.hard_dis_jtag_err().bit()),
-            )
+            .field("rd_dis_err", &self.rd_dis_err())
+            .field("dis_rtc_ram_boot_err", &self.dis_rtc_ram_boot_err())
+            .field("dis_icache_err", &self.dis_icache_err())
+            .field("dis_dcache_err", &self.dis_dcache_err())
+            .field("dis_download_icache_err", &self.dis_download_icache_err())
+            .field("dis_download_dcache_err", &self.dis_download_dcache_err())
+            .field("dis_force_download_err", &self.dis_force_download_err())
+            .field("dis_usb_err", &self.dis_usb_err())
+            .field("dis_can_err", &self.dis_can_err())
+            .field("dis_boot_remap_err", &self.dis_boot_remap_err())
+            .field("rpt4_reserved5_err", &self.rpt4_reserved5_err())
+            .field("soft_dis_jtag_err", &self.soft_dis_jtag_err())
+            .field("hard_dis_jtag_err", &self.hard_dis_jtag_err())
             .field(
                 "dis_download_manual_encrypt_err",
-                &format_args!("{}", self.dis_download_manual_encrypt_err().bit()),
-            )
-            .field(
-                "usb_drefh_err",
-                &format_args!("{}", self.usb_drefh_err().bits()),
-            )
-            .field(
-                "usb_drefl_err",
-                &format_args!("{}", self.usb_drefl_err().bits()),
-            )
-            .field(
-                "usb_exchg_pins_err",
-                &format_args!("{}", self.usb_exchg_pins_err().bit()),
-            )
-            .field(
-                "ext_phy_enable_err",
-                &format_args!("{}", self.ext_phy_enable_err().bit()),
-            )
-            .field(
-                "usb_force_nopersist_err",
-                &format_args!("{}", self.usb_force_nopersist_err().bit()),
-            )
-            .field(
-                "rpt4_reserved0_err",
-                &format_args!("{}", self.rpt4_reserved0_err().bits()),
-            )
-            .field(
-                "vdd_spi_modecurlim_err",
-                &format_args!("{}", self.vdd_spi_modecurlim_err().bit()),
-            )
-            .field(
-                "vdd_spi_drefh_err",
-                &format_args!("{}", self.vdd_spi_drefh_err().bits()),
-            )
+                &self.dis_download_manual_encrypt_err(),
+            )
+            .field("usb_drefh_err", &self.usb_drefh_err())
+            .field("usb_drefl_err", &self.usb_drefl_err())
+            .field("usb_exchg_pins_err", &self.usb_exchg_pins_err())
+            .field("ext_phy_enable_err", &self.ext_phy_enable_err())
+            .field("usb_force_nopersist_err", &self.usb_force_nopersist_err())
+            .field("rpt4_reserved0_err", &self.rpt4_reserved0_err())
+            .field("vdd_spi_modecurlim_err", &self.vdd_spi_modecurlim_err())
+            .field("vdd_spi_drefh_err", &self.vdd_spi_drefh_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 0 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR0_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR0_SPEC {
diff --git a/esp32s2/src/efuse/rd_repeat_err1.rs b/esp32s2/src/efuse/rd_repeat_err1.rs
index 5eb0ca3168..fea5d9cc05 100644
--- a/esp32s2/src/efuse/rd_repeat_err1.rs
+++ b/esp32s2/src/efuse/rd_repeat_err1.rs
@@ -125,83 +125,35 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR1")
-            .field(
-                "vdd_spi_drefm_err",
-                &format_args!("{}", self.vdd_spi_drefm_err().bits()),
-            )
-            .field(
-                "vdd_spi_drefl_err",
-                &format_args!("{}", self.vdd_spi_drefl_err().bits()),
-            )
-            .field(
-                "vdd_spi_xpd_err",
-                &format_args!("{}", self.vdd_spi_xpd_err().bit()),
-            )
-            .field(
-                "vdd_spi_tieh_err",
-                &format_args!("{}", self.vdd_spi_tieh_err().bit()),
-            )
-            .field(
-                "vdd_spi_force_err",
-                &format_args!("{}", self.vdd_spi_force_err().bit()),
-            )
-            .field(
-                "vdd_spi_en_init_err",
-                &format_args!("{}", self.vdd_spi_en_init_err().bit()),
-            )
-            .field(
-                "vdd_spi_encurlim_err",
-                &format_args!("{}", self.vdd_spi_encurlim_err().bit()),
-            )
-            .field(
-                "vdd_spi_dcurlim_err",
-                &format_args!("{}", self.vdd_spi_dcurlim_err().bits()),
-            )
-            .field(
-                "vdd_spi_init_err",
-                &format_args!("{}", self.vdd_spi_init_err().bits()),
-            )
-            .field(
-                "vdd_spi_dcap_err",
-                &format_args!("{}", self.vdd_spi_dcap_err().bits()),
-            )
-            .field(
-                "wdt_delay_sel_err",
-                &format_args!("{}", self.wdt_delay_sel_err().bits()),
-            )
-            .field(
-                "spi_boot_crypt_cnt_err",
-                &format_args!("{}", self.spi_boot_crypt_cnt_err().bits()),
-            )
+            .field("vdd_spi_drefm_err", &self.vdd_spi_drefm_err())
+            .field("vdd_spi_drefl_err", &self.vdd_spi_drefl_err())
+            .field("vdd_spi_xpd_err", &self.vdd_spi_xpd_err())
+            .field("vdd_spi_tieh_err", &self.vdd_spi_tieh_err())
+            .field("vdd_spi_force_err", &self.vdd_spi_force_err())
+            .field("vdd_spi_en_init_err", &self.vdd_spi_en_init_err())
+            .field("vdd_spi_encurlim_err", &self.vdd_spi_encurlim_err())
+            .field("vdd_spi_dcurlim_err", &self.vdd_spi_dcurlim_err())
+            .field("vdd_spi_init_err", &self.vdd_spi_init_err())
+            .field("vdd_spi_dcap_err", &self.vdd_spi_dcap_err())
+            .field("wdt_delay_sel_err", &self.wdt_delay_sel_err())
+            .field("spi_boot_crypt_cnt_err", &self.spi_boot_crypt_cnt_err())
             .field(
                 "secure_boot_key_revoke0_err",
-                &format_args!("{}", self.secure_boot_key_revoke0_err().bit()),
+                &self.secure_boot_key_revoke0_err(),
             )
             .field(
                 "secure_boot_key_revoke1_err",
-                &format_args!("{}", self.secure_boot_key_revoke1_err().bit()),
+                &self.secure_boot_key_revoke1_err(),
             )
             .field(
                 "secure_boot_key_revoke2_err",
-                &format_args!("{}", self.secure_boot_key_revoke2_err().bit()),
-            )
-            .field(
-                "key_purpose_0_err",
-                &format_args!("{}", self.key_purpose_0_err().bits()),
-            )
-            .field(
-                "key_purpose_1_err",
-                &format_args!("{}", self.key_purpose_1_err().bits()),
+                &self.secure_boot_key_revoke2_err(),
             )
+            .field("key_purpose_0_err", &self.key_purpose_0_err())
+            .field("key_purpose_1_err", &self.key_purpose_1_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 1 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR1_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR1_SPEC {
diff --git a/esp32s2/src/efuse/rd_repeat_err2.rs b/esp32s2/src/efuse/rd_repeat_err2.rs
index 295c5bed69..66e2c91286 100644
--- a/esp32s2/src/efuse/rd_repeat_err2.rs
+++ b/esp32s2/src/efuse/rd_repeat_err2.rs
@@ -69,51 +69,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR2")
-            .field(
-                "key_purpose_2_err",
-                &format_args!("{}", self.key_purpose_2_err().bits()),
-            )
-            .field(
-                "key_purpose_3_err",
-                &format_args!("{}", self.key_purpose_3_err().bits()),
-            )
-            .field(
-                "key_purpose_4_err",
-                &format_args!("{}", self.key_purpose_4_err().bits()),
-            )
-            .field(
-                "key_purpose_5_err",
-                &format_args!("{}", self.key_purpose_5_err().bits()),
-            )
-            .field(
-                "key_purpose_6_err",
-                &format_args!("{}", self.key_purpose_6_err().bits()),
-            )
-            .field(
-                "secure_boot_en_err",
-                &format_args!("{}", self.secure_boot_en_err().bit()),
-            )
+            .field("key_purpose_2_err", &self.key_purpose_2_err())
+            .field("key_purpose_3_err", &self.key_purpose_3_err())
+            .field("key_purpose_4_err", &self.key_purpose_4_err())
+            .field("key_purpose_5_err", &self.key_purpose_5_err())
+            .field("key_purpose_6_err", &self.key_purpose_6_err())
+            .field("secure_boot_en_err", &self.secure_boot_en_err())
             .field(
                 "secure_boot_aggressive_revoke_err",
-                &format_args!("{}", self.secure_boot_aggressive_revoke_err().bit()),
-            )
-            .field(
-                "rpt4_reserved1_err",
-                &format_args!("{}", self.rpt4_reserved1_err().bits()),
-            )
-            .field(
-                "flash_tpuw_err",
-                &format_args!("{}", self.flash_tpuw_err().bits()),
+                &self.secure_boot_aggressive_revoke_err(),
             )
+            .field("rpt4_reserved1_err", &self.rpt4_reserved1_err())
+            .field("flash_tpuw_err", &self.flash_tpuw_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 2 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR2_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR2_SPEC {
diff --git a/esp32s2/src/efuse/rd_repeat_err3.rs b/esp32s2/src/efuse/rd_repeat_err3.rs
index 227b60e46b..9ce7e2e46c 100644
--- a/esp32s2/src/efuse/rd_repeat_err3.rs
+++ b/esp32s2/src/efuse/rd_repeat_err3.rs
@@ -90,63 +90,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR3")
-            .field(
-                "dis_download_mode_err",
-                &format_args!("{}", self.dis_download_mode_err().bit()),
-            )
-            .field(
-                "dis_legacy_spi_boot_err",
-                &format_args!("{}", self.dis_legacy_spi_boot_err().bit()),
-            )
-            .field(
-                "uart_print_channel_err",
-                &format_args!("{}", self.uart_print_channel_err().bit()),
-            )
-            .field(
-                "rpt4_reserved3_err",
-                &format_args!("{}", self.rpt4_reserved3_err().bit()),
-            )
+            .field("dis_download_mode_err", &self.dis_download_mode_err())
+            .field("dis_legacy_spi_boot_err", &self.dis_legacy_spi_boot_err())
+            .field("uart_print_channel_err", &self.uart_print_channel_err())
+            .field("rpt4_reserved3_err", &self.rpt4_reserved3_err())
             .field(
                 "dis_usb_download_mode_err",
-                &format_args!("{}", self.dis_usb_download_mode_err().bit()),
+                &self.dis_usb_download_mode_err(),
             )
             .field(
                 "enable_security_download_err",
-                &format_args!("{}", self.enable_security_download_err().bit()),
-            )
-            .field(
-                "uart_print_control_err",
-                &format_args!("{}", self.uart_print_control_err().bits()),
-            )
-            .field(
-                "pin_power_selection_err",
-                &format_args!("{}", self.pin_power_selection_err().bit()),
-            )
-            .field(
-                "flash_type_err",
-                &format_args!("{}", self.flash_type_err().bit()),
-            )
-            .field(
-                "force_send_resume_err",
-                &format_args!("{}", self.force_send_resume_err().bit()),
-            )
-            .field(
-                "secure_version_err",
-                &format_args!("{}", self.secure_version_err().bits()),
-            )
-            .field(
-                "rpt4_reserved2_err",
-                &format_args!("{}", self.rpt4_reserved2_err().bits()),
+                &self.enable_security_download_err(),
             )
+            .field("uart_print_control_err", &self.uart_print_control_err())
+            .field("pin_power_selection_err", &self.pin_power_selection_err())
+            .field("flash_type_err", &self.flash_type_err())
+            .field("force_send_resume_err", &self.force_send_resume_err())
+            .field("secure_version_err", &self.secure_version_err())
+            .field("rpt4_reserved2_err", &self.rpt4_reserved2_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 3 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR3_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR3_SPEC {
diff --git a/esp32s2/src/efuse/rd_repeat_err4.rs b/esp32s2/src/efuse/rd_repeat_err4.rs
index ac8048074a..5b52560182 100644
--- a/esp32s2/src/efuse/rd_repeat_err4.rs
+++ b/esp32s2/src/efuse/rd_repeat_err4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR4")
-            .field(
-                "rpt4_reserved4_err",
-                &format_args!("{}", self.rpt4_reserved4_err().bits()),
-            )
+            .field("rpt4_reserved4_err", &self.rpt4_reserved4_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 4 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR4_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR4_SPEC {
diff --git a/esp32s2/src/efuse/rd_rs_err0.rs b/esp32s2/src/efuse/rd_rs_err0.rs
index 91353b15c2..7108ecb56a 100644
--- a/esp32s2/src/efuse/rd_rs_err0.rs
+++ b/esp32s2/src/efuse/rd_rs_err0.rs
@@ -118,64 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_RS_ERR0")
-            .field(
-                "mac_spi_8m_err_num",
-                &format_args!("{}", self.mac_spi_8m_err_num().bits()),
-            )
-            .field(
-                "mac_spi_8m_fail",
-                &format_args!("{}", self.mac_spi_8m_fail().bit()),
-            )
-            .field(
-                "sys_part1_num",
-                &format_args!("{}", self.sys_part1_num().bits()),
-            )
-            .field(
-                "sys_part1_fail",
-                &format_args!("{}", self.sys_part1_fail().bit()),
-            )
-            .field(
-                "usr_data_err_num",
-                &format_args!("{}", self.usr_data_err_num().bits()),
-            )
-            .field(
-                "usr_data_fail",
-                &format_args!("{}", self.usr_data_fail().bit()),
-            )
-            .field(
-                "key0_err_num",
-                &format_args!("{}", self.key0_err_num().bits()),
-            )
-            .field("key0_fail", &format_args!("{}", self.key0_fail().bit()))
-            .field(
-                "key1_err_num",
-                &format_args!("{}", self.key1_err_num().bits()),
-            )
-            .field("key1_fail", &format_args!("{}", self.key1_fail().bit()))
-            .field(
-                "key2_err_num",
-                &format_args!("{}", self.key2_err_num().bits()),
-            )
-            .field("key2_fail", &format_args!("{}", self.key2_fail().bit()))
-            .field(
-                "key3_err_num",
-                &format_args!("{}", self.key3_err_num().bits()),
-            )
-            .field("key3_fail", &format_args!("{}", self.key3_fail().bit()))
-            .field(
-                "key4_err_num",
-                &format_args!("{}", self.key4_err_num().bits()),
-            )
-            .field("key4_fail", &format_args!("{}", self.key4_fail().bit()))
+            .field("mac_spi_8m_err_num", &self.mac_spi_8m_err_num())
+            .field("mac_spi_8m_fail", &self.mac_spi_8m_fail())
+            .field("sys_part1_num", &self.sys_part1_num())
+            .field("sys_part1_fail", &self.sys_part1_fail())
+            .field("usr_data_err_num", &self.usr_data_err_num())
+            .field("usr_data_fail", &self.usr_data_fail())
+            .field("key0_err_num", &self.key0_err_num())
+            .field("key0_fail", &self.key0_fail())
+            .field("key1_err_num", &self.key1_err_num())
+            .field("key1_fail", &self.key1_fail())
+            .field("key2_err_num", &self.key2_err_num())
+            .field("key2_fail", &self.key2_fail())
+            .field("key3_err_num", &self.key3_err_num())
+            .field("key3_fail", &self.key3_fail())
+            .field("key4_err_num", &self.key4_err_num())
+            .field("key4_fail", &self.key4_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RS_ERR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 0 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RS_ERR0_SPEC;
 impl crate::RegisterSpec for RD_RS_ERR0_SPEC {
diff --git a/esp32s2/src/efuse/rd_rs_err1.rs b/esp32s2/src/efuse/rd_rs_err1.rs
index fbcef78cba..a49fdaa73c 100644
--- a/esp32s2/src/efuse/rd_rs_err1.rs
+++ b/esp32s2/src/efuse/rd_rs_err1.rs
@@ -34,28 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_RS_ERR1")
-            .field(
-                "key5_err_num",
-                &format_args!("{}", self.key5_err_num().bits()),
-            )
-            .field("key5_fail", &format_args!("{}", self.key5_fail().bit()))
-            .field(
-                "sys_part2_err_num",
-                &format_args!("{}", self.sys_part2_err_num().bits()),
-            )
-            .field(
-                "sys_part2_fail",
-                &format_args!("{}", self.sys_part2_fail().bit()),
-            )
+            .field("key5_err_num", &self.key5_err_num())
+            .field("key5_fail", &self.key5_fail())
+            .field("sys_part2_err_num", &self.sys_part2_err_num())
+            .field("sys_part2_fail", &self.sys_part2_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RS_ERR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 1 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RS_ERR1_SPEC;
 impl crate::RegisterSpec for RD_RS_ERR1_SPEC {
diff --git a/esp32s2/src/efuse/rd_sys_data_part1_.rs b/esp32s2/src/efuse/rd_sys_data_part1_.rs
index db6ea8d35e..d1a035fe1b 100644
--- a/esp32s2/src/efuse/rd_sys_data_part1_.rs
+++ b/esp32s2/src/efuse/rd_sys_data_part1_.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_DATA_PART1_")
-            .field(
-                "sys_data_part1",
-                &format_args!("{}", self.sys_data_part1().bits()),
-            )
+            .field("sys_data_part1", &self.sys_data_part1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_DATA_PART1__SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register %s of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_data_part1_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_DATA_PART1__SPEC;
 impl crate::RegisterSpec for RD_SYS_DATA_PART1__SPEC {
diff --git a/esp32s2/src/efuse/rd_sys_data_part2_.rs b/esp32s2/src/efuse/rd_sys_data_part2_.rs
index 1f0fa10db7..72f8d24fe1 100644
--- a/esp32s2/src/efuse/rd_sys_data_part2_.rs
+++ b/esp32s2/src/efuse/rd_sys_data_part2_.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_DATA_PART2_")
-            .field(
-                "sys_data_part2",
-                &format_args!("{}", self.sys_data_part2().bits()),
-            )
+            .field("sys_data_part2", &self.sys_data_part2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_DATA_PART2__SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register %s of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_data_part2_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_DATA_PART2__SPEC;
 impl crate::RegisterSpec for RD_SYS_DATA_PART2__SPEC {
diff --git a/esp32s2/src/efuse/rd_tim_conf.rs b/esp32s2/src/efuse/rd_tim_conf.rs
index 959506bf72..ad5b7617b1 100644
--- a/esp32s2/src/efuse/rd_tim_conf.rs
+++ b/esp32s2/src/efuse/rd_tim_conf.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_TIM_CONF")
-            .field("thr_a", &format_args!("{}", self.thr_a().bits()))
-            .field("trd", &format_args!("{}", self.trd().bits()))
-            .field("tsur_a", &format_args!("{}", self.tsur_a().bits()))
-            .field(
-                "read_init_num",
-                &format_args!("{}", self.read_init_num().bits()),
-            )
+            .field("thr_a", &self.thr_a())
+            .field("trd", &self.trd())
+            .field("tsur_a", &self.tsur_a())
+            .field("read_init_num", &self.read_init_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_TIM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures the hold time of read operation."]
     #[inline(always)]
diff --git a/esp32s2/src/efuse/rd_usr_data.rs b/esp32s2/src/efuse/rd_usr_data.rs
index 7d1317ea22..37ad708c18 100644
--- a/esp32s2/src/efuse/rd_usr_data.rs
+++ b/esp32s2/src/efuse/rd_usr_data.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA")
-            .field("usr_data", &format_args!("{}", self.usr_data().bits()))
+            .field("usr_data", &self.usr_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register %s of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA_SPEC {
diff --git a/esp32s2/src/efuse/rd_wr_dis.rs b/esp32s2/src/efuse/rd_wr_dis.rs
index e5af2013ca..1ed3dea919 100644
--- a/esp32s2/src/efuse/rd_wr_dis.rs
+++ b/esp32s2/src/efuse/rd_wr_dis.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_WR_DIS")
-            .field("wr_dis", &format_args!("{}", self.wr_dis().bits()))
+            .field("wr_dis", &self.wr_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_WR_DIS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_wr_dis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_WR_DIS_SPEC;
 impl crate::RegisterSpec for RD_WR_DIS_SPEC {
diff --git a/esp32s2/src/efuse/status.rs b/esp32s2/src/efuse/status.rs
index 88ccd0f914..2402480c94 100644
--- a/esp32s2/src/efuse/status.rs
+++ b/esp32s2/src/efuse/status.rs
@@ -62,38 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field("otp_load_sw", &format_args!("{}", self.otp_load_sw().bit()))
-            .field(
-                "otp_vddq_c_sync2",
-                &format_args!("{}", self.otp_vddq_c_sync2().bit()),
-            )
-            .field(
-                "otp_strobe_sw",
-                &format_args!("{}", self.otp_strobe_sw().bit()),
-            )
-            .field("otp_csb_sw", &format_args!("{}", self.otp_csb_sw().bit()))
-            .field(
-                "otp_pgenb_sw",
-                &format_args!("{}", self.otp_pgenb_sw().bit()),
-            )
-            .field(
-                "otp_vddq_is_sw",
-                &format_args!("{}", self.otp_vddq_is_sw().bit()),
-            )
-            .field(
-                "repeat_err_cnt",
-                &format_args!("{}", self.repeat_err_cnt().bits()),
-            )
+            .field("state", &self.state())
+            .field("otp_load_sw", &self.otp_load_sw())
+            .field("otp_vddq_c_sync2", &self.otp_vddq_c_sync2())
+            .field("otp_strobe_sw", &self.otp_strobe_sw())
+            .field("otp_csb_sw", &self.otp_csb_sw())
+            .field("otp_pgenb_sw", &self.otp_pgenb_sw())
+            .field("otp_vddq_is_sw", &self.otp_vddq_is_sw())
+            .field("repeat_err_cnt", &self.repeat_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32s2/src/efuse/wr_tim_conf0.rs b/esp32s2/src/efuse/wr_tim_conf0.rs
index ce2c32b215..532b0b6d3c 100644
--- a/esp32s2/src/efuse/wr_tim_conf0.rs
+++ b/esp32s2/src/efuse/wr_tim_conf0.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF0")
-            .field("thp_a", &format_args!("{}", self.thp_a().bits()))
-            .field(
-                "tpgm_inactive",
-                &format_args!("{}", self.tpgm_inactive().bits()),
-            )
-            .field("tpgm", &format_args!("{}", self.tpgm().bits()))
+            .field("thp_a", &self.thp_a())
+            .field("tpgm_inactive", &self.tpgm_inactive())
+            .field("tpgm", &self.tpgm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures the hold time of programming operation."]
     #[inline(always)]
diff --git a/esp32s2/src/efuse/wr_tim_conf1.rs b/esp32s2/src/efuse/wr_tim_conf1.rs
index 931865ada9..efbeb3f607 100644
--- a/esp32s2/src/efuse/wr_tim_conf1.rs
+++ b/esp32s2/src/efuse/wr_tim_conf1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF1")
-            .field("tsup_a", &format_args!("{}", self.tsup_a().bits()))
-            .field("pwr_on_num", &format_args!("{}", self.pwr_on_num().bits()))
+            .field("tsup_a", &self.tsup_a())
+            .field("pwr_on_num", &self.pwr_on_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Configures the setup time of programming operation."]
     #[inline(always)]
diff --git a/esp32s2/src/efuse/wr_tim_conf2.rs b/esp32s2/src/efuse/wr_tim_conf2.rs
index 80c193cb0d..eb2cfd48b6 100644
--- a/esp32s2/src/efuse/wr_tim_conf2.rs
+++ b/esp32s2/src/efuse/wr_tim_conf2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF2")
-            .field(
-                "pwr_off_num",
-                &format_args!("{}", self.pwr_off_num().bits()),
-            )
+            .field("pwr_off_num", &self.pwr_off_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures the power outage time for VDDQ."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/cache_bridge_arbiter_ctrl.rs b/esp32s2/src/extmem/cache_bridge_arbiter_ctrl.rs
index 4bdd2a1bab..11ae2160de 100644
--- a/esp32s2/src/extmem/cache_bridge_arbiter_ctrl.rs
+++ b/esp32s2/src/extmem/cache_bridge_arbiter_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_BRIDGE_ARBITER_CTRL")
-            .field(
-                "alloc_wb_hold_arbiter",
-                &format_args!("{}", self.alloc_wb_hold_arbiter().bit()),
-            )
+            .field("alloc_wb_hold_arbiter", &self.alloc_wb_hold_arbiter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_BRIDGE_ARBITER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/cache_conf_misc.rs b/esp32s2/src/extmem/cache_conf_misc.rs
index 8008c69c0d..e1dc148cb6 100644
--- a/esp32s2/src/extmem/cache_conf_misc.rs
+++ b/esp32s2/src/extmem/cache_conf_misc.rs
@@ -30,21 +30,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CACHE_CONF_MISC")
             .field(
                 "pro_cache_ignore_preload_mmu_entry_fault",
-                &format_args!("{}", self.pro_cache_ignore_preload_mmu_entry_fault().bit()),
+                &self.pro_cache_ignore_preload_mmu_entry_fault(),
             )
             .field(
                 "pro_cache_ignore_sync_mmu_entry_fault",
-                &format_args!("{}", self.pro_cache_ignore_sync_mmu_entry_fault().bit()),
+                &self.pro_cache_ignore_sync_mmu_entry_fault(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CONF_MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable checking mmu entry fault by preload operation."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/cache_dbg_int_ena.rs b/esp32s2/src/extmem/cache_dbg_int_ena.rs
index 624079f60d..8753eb7c49 100644
--- a/esp32s2/src/extmem/cache_dbg_int_ena.rs
+++ b/esp32s2/src/extmem/cache_dbg_int_ena.rs
@@ -179,91 +179,61 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_DBG_INT_ENA")
-            .field(
-                "cache_dbg_en",
-                &format_args!("{}", self.cache_dbg_en().bit()),
-            )
-            .field(
-                "ibus_acs_msk_ic_int_ena",
-                &format_args!("{}", self.ibus_acs_msk_ic_int_ena().bit()),
-            )
-            .field(
-                "ibus_cnt_ovf_int_ena",
-                &format_args!("{}", self.ibus_cnt_ovf_int_ena().bit()),
-            )
+            .field("cache_dbg_en", &self.cache_dbg_en())
+            .field("ibus_acs_msk_ic_int_ena", &self.ibus_acs_msk_ic_int_ena())
+            .field("ibus_cnt_ovf_int_ena", &self.ibus_cnt_ovf_int_ena())
             .field(
                 "ic_sync_size_fault_int_ena",
-                &format_args!("{}", self.ic_sync_size_fault_int_ena().bit()),
+                &self.ic_sync_size_fault_int_ena(),
             )
             .field(
                 "ic_preload_size_fault_int_ena",
-                &format_args!("{}", self.ic_preload_size_fault_int_ena().bit()),
-            )
-            .field(
-                "icache_reject_int_ena",
-                &format_args!("{}", self.icache_reject_int_ena().bit()),
+                &self.ic_preload_size_fault_int_ena(),
             )
+            .field("icache_reject_int_ena", &self.icache_reject_int_ena())
             .field(
                 "icache_set_preload_ilg_int_ena",
-                &format_args!("{}", self.icache_set_preload_ilg_int_ena().bit()),
+                &self.icache_set_preload_ilg_int_ena(),
             )
             .field(
                 "icache_set_sync_ilg_int_ena",
-                &format_args!("{}", self.icache_set_sync_ilg_int_ena().bit()),
+                &self.icache_set_sync_ilg_int_ena(),
             )
             .field(
                 "icache_set_lock_ilg_int_ena",
-                &format_args!("{}", self.icache_set_lock_ilg_int_ena().bit()),
-            )
-            .field(
-                "dbus_acs_msk_dc_int_ena",
-                &format_args!("{}", self.dbus_acs_msk_dc_int_ena().bit()),
-            )
-            .field(
-                "dbus_cnt_ovf_int_ena",
-                &format_args!("{}", self.dbus_cnt_ovf_int_ena().bit()),
+                &self.icache_set_lock_ilg_int_ena(),
             )
+            .field("dbus_acs_msk_dc_int_ena", &self.dbus_acs_msk_dc_int_ena())
+            .field("dbus_cnt_ovf_int_ena", &self.dbus_cnt_ovf_int_ena())
             .field(
                 "dc_sync_size_fault_int_ena",
-                &format_args!("{}", self.dc_sync_size_fault_int_ena().bit()),
+                &self.dc_sync_size_fault_int_ena(),
             )
             .field(
                 "dc_preload_size_fault_int_ena",
-                &format_args!("{}", self.dc_preload_size_fault_int_ena().bit()),
+                &self.dc_preload_size_fault_int_ena(),
             )
             .field(
                 "dcache_write_flash_int_ena",
-                &format_args!("{}", self.dcache_write_flash_int_ena().bit()),
-            )
-            .field(
-                "dcache_reject_int_ena",
-                &format_args!("{}", self.dcache_reject_int_ena().bit()),
+                &self.dcache_write_flash_int_ena(),
             )
+            .field("dcache_reject_int_ena", &self.dcache_reject_int_ena())
             .field(
                 "dcache_set_preload_ilg_int_ena",
-                &format_args!("{}", self.dcache_set_preload_ilg_int_ena().bit()),
+                &self.dcache_set_preload_ilg_int_ena(),
             )
             .field(
                 "dcache_set_sync_ilg_int_ena",
-                &format_args!("{}", self.dcache_set_sync_ilg_int_ena().bit()),
+                &self.dcache_set_sync_ilg_int_ena(),
             )
             .field(
                 "dcache_set_lock_ilg_int_ena",
-                &format_args!("{}", self.dcache_set_lock_ilg_int_ena().bit()),
-            )
-            .field(
-                "mmu_entry_fault_int_ena",
-                &format_args!("{}", self.mmu_entry_fault_int_ena().bit()),
+                &self.dcache_set_lock_ilg_int_ena(),
             )
+            .field("mmu_entry_fault_int_ena", &self.mmu_entry_fault_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_DBG_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to activate the cache track function. 1: enable, 0: disable."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/cache_dbg_status0.rs b/esp32s2/src/extmem/cache_dbg_status0.rs
index 5935a78778..982ad54065 100644
--- a/esp32s2/src/extmem/cache_dbg_status0.rs
+++ b/esp32s2/src/extmem/cache_dbg_status0.rs
@@ -146,95 +146,44 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_DBG_STATUS0")
-            .field(
-                "ibus0_acs_msk_icache_st",
-                &format_args!("{}", self.ibus0_acs_msk_icache_st().bit()),
-            )
-            .field(
-                "ibus1_acs_msk_icache_st",
-                &format_args!("{}", self.ibus1_acs_msk_icache_st().bit()),
-            )
-            .field(
-                "ibus2_acs_msk_icache_st",
-                &format_args!("{}", self.ibus2_acs_msk_icache_st().bit()),
-            )
-            .field(
-                "ibus0_acs_cnt_ovf_st",
-                &format_args!("{}", self.ibus0_acs_cnt_ovf_st().bit()),
-            )
-            .field(
-                "ibus1_acs_cnt_ovf_st",
-                &format_args!("{}", self.ibus1_acs_cnt_ovf_st().bit()),
-            )
-            .field(
-                "ibus2_acs_cnt_ovf_st",
-                &format_args!("{}", self.ibus2_acs_cnt_ovf_st().bit()),
-            )
+            .field("ibus0_acs_msk_icache_st", &self.ibus0_acs_msk_icache_st())
+            .field("ibus1_acs_msk_icache_st", &self.ibus1_acs_msk_icache_st())
+            .field("ibus2_acs_msk_icache_st", &self.ibus2_acs_msk_icache_st())
+            .field("ibus0_acs_cnt_ovf_st", &self.ibus0_acs_cnt_ovf_st())
+            .field("ibus1_acs_cnt_ovf_st", &self.ibus1_acs_cnt_ovf_st())
+            .field("ibus2_acs_cnt_ovf_st", &self.ibus2_acs_cnt_ovf_st())
             .field(
                 "ibus0_acs_miss_cnt_ovf_st",
-                &format_args!("{}", self.ibus0_acs_miss_cnt_ovf_st().bit()),
+                &self.ibus0_acs_miss_cnt_ovf_st(),
             )
             .field(
                 "ibus1_acs_miss_cnt_ovf_st",
-                &format_args!("{}", self.ibus1_acs_miss_cnt_ovf_st().bit()),
+                &self.ibus1_acs_miss_cnt_ovf_st(),
             )
             .field(
                 "ibus2_acs_miss_cnt_ovf_st",
-                &format_args!("{}", self.ibus2_acs_miss_cnt_ovf_st().bit()),
-            )
-            .field(
-                "ibus0_abandon_cnt_ovf_st",
-                &format_args!("{}", self.ibus0_abandon_cnt_ovf_st().bit()),
-            )
-            .field(
-                "ibus1_abandon_cnt_ovf_st",
-                &format_args!("{}", self.ibus1_abandon_cnt_ovf_st().bit()),
-            )
-            .field(
-                "ibus2_abandon_cnt_ovf_st",
-                &format_args!("{}", self.ibus2_abandon_cnt_ovf_st().bit()),
+                &self.ibus2_acs_miss_cnt_ovf_st(),
             )
+            .field("ibus0_abandon_cnt_ovf_st", &self.ibus0_abandon_cnt_ovf_st())
+            .field("ibus1_abandon_cnt_ovf_st", &self.ibus1_abandon_cnt_ovf_st())
+            .field("ibus2_abandon_cnt_ovf_st", &self.ibus2_abandon_cnt_ovf_st())
             .field(
                 "ic_preload_miss_cnt_ovf_st",
-                &format_args!("{}", self.ic_preload_miss_cnt_ovf_st().bit()),
-            )
-            .field(
-                "ic_preload_cnt_ovf_st",
-                &format_args!("{}", self.ic_preload_cnt_ovf_st().bit()),
-            )
-            .field(
-                "ic_sync_size_fault_st",
-                &format_args!("{}", self.ic_sync_size_fault_st().bit()),
-            )
-            .field(
-                "ic_preload_size_fault_st",
-                &format_args!("{}", self.ic_preload_size_fault_st().bit()),
-            )
-            .field(
-                "icache_reject_st",
-                &format_args!("{}", self.icache_reject_st().bit()),
+                &self.ic_preload_miss_cnt_ovf_st(),
             )
+            .field("ic_preload_cnt_ovf_st", &self.ic_preload_cnt_ovf_st())
+            .field("ic_sync_size_fault_st", &self.ic_sync_size_fault_st())
+            .field("ic_preload_size_fault_st", &self.ic_preload_size_fault_st())
+            .field("icache_reject_st", &self.icache_reject_st())
             .field(
                 "icache_set_preload_ilg_st",
-                &format_args!("{}", self.icache_set_preload_ilg_st().bit()),
-            )
-            .field(
-                "icache_set_sync_ilg_st",
-                &format_args!("{}", self.icache_set_sync_ilg_st().bit()),
-            )
-            .field(
-                "icache_set_lock_ilg_st",
-                &format_args!("{}", self.icache_set_lock_ilg_st().bit()),
+                &self.icache_set_preload_ilg_st(),
             )
+            .field("icache_set_sync_ilg_st", &self.icache_set_sync_ilg_st())
+            .field("icache_set_lock_ilg_st", &self.icache_set_lock_ilg_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_DBG_STATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_dbg_status0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_DBG_STATUS0_SPEC;
 impl crate::RegisterSpec for CACHE_DBG_STATUS0_SPEC {
diff --git a/esp32s2/src/extmem/cache_dbg_status1.rs b/esp32s2/src/extmem/cache_dbg_status1.rs
index 8bc9bf1f34..657b697b41 100644
--- a/esp32s2/src/extmem/cache_dbg_status1.rs
+++ b/esp32s2/src/extmem/cache_dbg_status1.rs
@@ -188,119 +188,53 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_DBG_STATUS1")
-            .field(
-                "dbus0_acs_msk_dcache_st",
-                &format_args!("{}", self.dbus0_acs_msk_dcache_st().bit()),
-            )
-            .field(
-                "dbus1_acs_msk_dcache_st",
-                &format_args!("{}", self.dbus1_acs_msk_dcache_st().bit()),
-            )
-            .field(
-                "dbus2_acs_msk_dcache_st",
-                &format_args!("{}", self.dbus2_acs_msk_dcache_st().bit()),
-            )
-            .field(
-                "dbus0_acs_cnt_ovf_st",
-                &format_args!("{}", self.dbus0_acs_cnt_ovf_st().bit()),
-            )
-            .field(
-                "dbus1_acs_cnt_ovf_st",
-                &format_args!("{}", self.dbus1_acs_cnt_ovf_st().bit()),
-            )
-            .field(
-                "dbus2_acs_cnt_ovf_st",
-                &format_args!("{}", self.dbus2_acs_cnt_ovf_st().bit()),
-            )
+            .field("dbus0_acs_msk_dcache_st", &self.dbus0_acs_msk_dcache_st())
+            .field("dbus1_acs_msk_dcache_st", &self.dbus1_acs_msk_dcache_st())
+            .field("dbus2_acs_msk_dcache_st", &self.dbus2_acs_msk_dcache_st())
+            .field("dbus0_acs_cnt_ovf_st", &self.dbus0_acs_cnt_ovf_st())
+            .field("dbus1_acs_cnt_ovf_st", &self.dbus1_acs_cnt_ovf_st())
+            .field("dbus2_acs_cnt_ovf_st", &self.dbus2_acs_cnt_ovf_st())
             .field(
                 "dbus0_acs_miss_cnt_ovf_st",
-                &format_args!("{}", self.dbus0_acs_miss_cnt_ovf_st().bit()),
+                &self.dbus0_acs_miss_cnt_ovf_st(),
             )
             .field(
                 "dbus1_acs_miss_cnt_ovf_st",
-                &format_args!("{}", self.dbus1_acs_miss_cnt_ovf_st().bit()),
+                &self.dbus1_acs_miss_cnt_ovf_st(),
             )
             .field(
                 "dbus2_acs_miss_cnt_ovf_st",
-                &format_args!("{}", self.dbus2_acs_miss_cnt_ovf_st().bit()),
-            )
-            .field(
-                "dbus0_acs_wb_cnt_ovf_st",
-                &format_args!("{}", self.dbus0_acs_wb_cnt_ovf_st().bit()),
-            )
-            .field(
-                "dbus1_acs_wb_cnt_ovf_st",
-                &format_args!("{}", self.dbus1_acs_wb_cnt_ovf_st().bit()),
-            )
-            .field(
-                "dbus2_acs_wb_cnt_ovf_st",
-                &format_args!("{}", self.dbus2_acs_wb_cnt_ovf_st().bit()),
-            )
-            .field(
-                "dbus0_abandon_cnt_ovf_st",
-                &format_args!("{}", self.dbus0_abandon_cnt_ovf_st().bit()),
-            )
-            .field(
-                "dbus1_abandon_cnt_ovf_st",
-                &format_args!("{}", self.dbus1_abandon_cnt_ovf_st().bit()),
-            )
-            .field(
-                "dbus2_abandon_cnt_ovf_st",
-                &format_args!("{}", self.dbus2_abandon_cnt_ovf_st().bit()),
+                &self.dbus2_acs_miss_cnt_ovf_st(),
             )
+            .field("dbus0_acs_wb_cnt_ovf_st", &self.dbus0_acs_wb_cnt_ovf_st())
+            .field("dbus1_acs_wb_cnt_ovf_st", &self.dbus1_acs_wb_cnt_ovf_st())
+            .field("dbus2_acs_wb_cnt_ovf_st", &self.dbus2_acs_wb_cnt_ovf_st())
+            .field("dbus0_abandon_cnt_ovf_st", &self.dbus0_abandon_cnt_ovf_st())
+            .field("dbus1_abandon_cnt_ovf_st", &self.dbus1_abandon_cnt_ovf_st())
+            .field("dbus2_abandon_cnt_ovf_st", &self.dbus2_abandon_cnt_ovf_st())
             .field(
                 "dc_preload_miss_cnt_ovf_st",
-                &format_args!("{}", self.dc_preload_miss_cnt_ovf_st().bit()),
+                &self.dc_preload_miss_cnt_ovf_st(),
             )
             .field(
                 "dc_preload_evict_cnt_ovf_st",
-                &format_args!("{}", self.dc_preload_evict_cnt_ovf_st().bit()),
-            )
-            .field(
-                "dc_preload_cnt_ovf_st",
-                &format_args!("{}", self.dc_preload_cnt_ovf_st().bit()),
-            )
-            .field(
-                "dc_sync_size_fault_st",
-                &format_args!("{}", self.dc_sync_size_fault_st().bit()),
-            )
-            .field(
-                "dc_preload_size_fault_st",
-                &format_args!("{}", self.dc_preload_size_fault_st().bit()),
-            )
-            .field(
-                "dcache_write_flash_st",
-                &format_args!("{}", self.dcache_write_flash_st().bit()),
-            )
-            .field(
-                "dcache_reject_st",
-                &format_args!("{}", self.dcache_reject_st().bit()),
+                &self.dc_preload_evict_cnt_ovf_st(),
             )
+            .field("dc_preload_cnt_ovf_st", &self.dc_preload_cnt_ovf_st())
+            .field("dc_sync_size_fault_st", &self.dc_sync_size_fault_st())
+            .field("dc_preload_size_fault_st", &self.dc_preload_size_fault_st())
+            .field("dcache_write_flash_st", &self.dcache_write_flash_st())
+            .field("dcache_reject_st", &self.dcache_reject_st())
             .field(
                 "dcache_set_preload_ilg_st",
-                &format_args!("{}", self.dcache_set_preload_ilg_st().bit()),
-            )
-            .field(
-                "dcache_set_sync_ilg_st",
-                &format_args!("{}", self.dcache_set_sync_ilg_st().bit()),
-            )
-            .field(
-                "dcache_set_lock_ilg_st",
-                &format_args!("{}", self.dcache_set_lock_ilg_st().bit()),
-            )
-            .field(
-                "mmu_entry_fault_st",
-                &format_args!("{}", self.mmu_entry_fault_st().bit()),
+                &self.dcache_set_preload_ilg_st(),
             )
+            .field("dcache_set_sync_ilg_st", &self.dcache_set_sync_ilg_st())
+            .field("dcache_set_lock_ilg_st", &self.dcache_set_lock_ilg_st())
+            .field("mmu_entry_fault_st", &self.mmu_entry_fault_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_DBG_STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_dbg_status1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_DBG_STATUS1_SPEC;
 impl crate::RegisterSpec for CACHE_DBG_STATUS1_SPEC {
diff --git a/esp32s2/src/extmem/cache_encrypt_decrypt_clk_force_on.rs b/esp32s2/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
index 1c1350f34b..7af5ae78eb 100644
--- a/esp32s2/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
+++ b/esp32s2/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
@@ -37,27 +37,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON")
-            .field(
-                "clk_force_on_db_encrypt",
-                &format_args!("{}", self.clk_force_on_db_encrypt().bit()),
-            )
+            .field("clk_force_on_db_encrypt", &self.clk_force_on_db_encrypt())
             .field(
                 "clk_force_on_g0cb_decrypt",
-                &format_args!("{}", self.clk_force_on_g0cb_decrypt().bit()),
+                &self.clk_force_on_g0cb_decrypt(),
             )
             .field(
                 "clk_force_on_automatic_encrypt_decrypt",
-                &format_args!("{}", self.clk_force_on_automatic_encrypt_decrypt().bit()),
+                &self.clk_force_on_automatic_encrypt_decrypt(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of encrypt clock. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/cache_encrypt_decrypt_record_disable.rs b/esp32s2/src/extmem/cache_encrypt_decrypt_record_disable.rs
index f7bb5a6912..b882bd2469 100644
--- a/esp32s2/src/extmem/cache_encrypt_decrypt_record_disable.rs
+++ b/esp32s2/src/extmem/cache_encrypt_decrypt_record_disable.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE")
             .field(
                 "record_disable_db_encrypt",
-                &format_args!("{}", self.record_disable_db_encrypt().bit()),
+                &self.record_disable_db_encrypt(),
             )
             .field(
                 "record_disable_g0cb_decrypt",
-                &format_args!("{}", self.record_disable_g0cb_decrypt().bit()),
+                &self.record_disable_g0cb_decrypt(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/cache_preload_int_ctrl.rs b/esp32s2/src/extmem/cache_preload_int_ctrl.rs
index bdf25f514e..acedacad97 100644
--- a/esp32s2/src/extmem/cache_preload_int_ctrl.rs
+++ b/esp32s2/src/extmem/cache_preload_int_ctrl.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CACHE_PRELOAD_INT_CTRL")
             .field(
                 "pro_icache_preload_int_st",
-                &format_args!("{}", self.pro_icache_preload_int_st().bit()),
+                &self.pro_icache_preload_int_st(),
             )
             .field(
                 "pro_icache_preload_int_ena",
-                &format_args!("{}", self.pro_icache_preload_int_ena().bit()),
+                &self.pro_icache_preload_int_ena(),
             )
             .field(
                 "pro_dcache_preload_int_st",
-                &format_args!("{}", self.pro_dcache_preload_int_st().bit()),
+                &self.pro_dcache_preload_int_st(),
             )
             .field(
                 "pro_dcache_preload_int_ena",
-                &format_args!("{}", self.pro_dcache_preload_int_ena().bit()),
+                &self.pro_dcache_preload_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_PRELOAD_INT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - The bit is used to enable the interrupt by icache pre-load done."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/cache_sync_int_ctrl.rs b/esp32s2/src/extmem/cache_sync_int_ctrl.rs
index c532f5a731..5080ef1059 100644
--- a/esp32s2/src/extmem/cache_sync_int_ctrl.rs
+++ b/esp32s2/src/extmem/cache_sync_int_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_SYNC_INT_CTRL")
-            .field(
-                "pro_icache_sync_int_st",
-                &format_args!("{}", self.pro_icache_sync_int_st().bit()),
-            )
-            .field(
-                "pro_icache_sync_int_ena",
-                &format_args!("{}", self.pro_icache_sync_int_ena().bit()),
-            )
-            .field(
-                "pro_dcache_sync_int_st",
-                &format_args!("{}", self.pro_dcache_sync_int_st().bit()),
-            )
-            .field(
-                "pro_dcache_sync_int_ena",
-                &format_args!("{}", self.pro_dcache_sync_int_ena().bit()),
-            )
+            .field("pro_icache_sync_int_st", &self.pro_icache_sync_int_st())
+            .field("pro_icache_sync_int_ena", &self.pro_icache_sync_int_ena())
+            .field("pro_dcache_sync_int_st", &self.pro_dcache_sync_int_st())
+            .field("pro_dcache_sync_int_ena", &self.pro_dcache_sync_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_SYNC_INT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - The bit is used to enable the interrupt by icache sync done."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/clock_gate.rs b/esp32s2/src/extmem/clock_gate.rs
index 3f70ecd050..cca5b385c3 100644
--- a/esp32s2/src/extmem/clock_gate.rs
+++ b/esp32s2/src/extmem/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/dbus0_abandon_cnt.rs b/esp32s2/src/extmem/dbus0_abandon_cnt.rs
index c966010468..94952c67d9 100644
--- a/esp32s2/src/extmem/dbus0_abandon_cnt.rs
+++ b/esp32s2/src/extmem/dbus0_abandon_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS0_ABANDON_CNT")
-            .field(
-                "dbus0_abandon_cnt",
-                &format_args!("{}", self.dbus0_abandon_cnt().bits()),
-            )
+            .field("dbus0_abandon_cnt", &self.dbus0_abandon_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS0_ABANDON_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus0_abandon_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS0_ABANDON_CNT_SPEC;
 impl crate::RegisterSpec for DBUS0_ABANDON_CNT_SPEC {
diff --git a/esp32s2/src/extmem/dbus0_acs_cnt.rs b/esp32s2/src/extmem/dbus0_acs_cnt.rs
index 4a959debdc..1393ff22ef 100644
--- a/esp32s2/src/extmem/dbus0_acs_cnt.rs
+++ b/esp32s2/src/extmem/dbus0_acs_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS0_ACS_CNT")
-            .field(
-                "dbus0_acs_cnt",
-                &format_args!("{}", self.dbus0_acs_cnt().bits()),
-            )
+            .field("dbus0_acs_cnt", &self.dbus0_acs_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS0_ACS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus0_acs_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS0_ACS_CNT_SPEC;
 impl crate::RegisterSpec for DBUS0_ACS_CNT_SPEC {
diff --git a/esp32s2/src/extmem/dbus0_acs_miss_cnt.rs b/esp32s2/src/extmem/dbus0_acs_miss_cnt.rs
index 617edf1377..f51ca68381 100644
--- a/esp32s2/src/extmem/dbus0_acs_miss_cnt.rs
+++ b/esp32s2/src/extmem/dbus0_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS0_ACS_MISS_CNT")
-            .field(
-                "dbus0_acs_miss_cnt",
-                &format_args!("{}", self.dbus0_acs_miss_cnt().bits()),
-            )
+            .field("dbus0_acs_miss_cnt", &self.dbus0_acs_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS0_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus0_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS0_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for DBUS0_ACS_MISS_CNT_SPEC {
diff --git a/esp32s2/src/extmem/dbus0_acs_wb_cnt.rs b/esp32s2/src/extmem/dbus0_acs_wb_cnt.rs
index 62e184ac8b..b22843cea4 100644
--- a/esp32s2/src/extmem/dbus0_acs_wb_cnt.rs
+++ b/esp32s2/src/extmem/dbus0_acs_wb_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS0_ACS_WB_CNT")
-            .field(
-                "dbus0_acs_wb_cnt",
-                &format_args!("{}", self.dbus0_acs_wb_cnt().bits()),
-            )
+            .field("dbus0_acs_wb_cnt", &self.dbus0_acs_wb_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS0_ACS_WB_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus0_acs_wb_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS0_ACS_WB_CNT_SPEC;
 impl crate::RegisterSpec for DBUS0_ACS_WB_CNT_SPEC {
diff --git a/esp32s2/src/extmem/dbus1_abandon_cnt.rs b/esp32s2/src/extmem/dbus1_abandon_cnt.rs
index 9ed43a0b24..6808e1ab90 100644
--- a/esp32s2/src/extmem/dbus1_abandon_cnt.rs
+++ b/esp32s2/src/extmem/dbus1_abandon_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS1_ABANDON_CNT")
-            .field(
-                "dbus1_abandon_cnt",
-                &format_args!("{}", self.dbus1_abandon_cnt().bits()),
-            )
+            .field("dbus1_abandon_cnt", &self.dbus1_abandon_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS1_ABANDON_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus1_abandon_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS1_ABANDON_CNT_SPEC;
 impl crate::RegisterSpec for DBUS1_ABANDON_CNT_SPEC {
diff --git a/esp32s2/src/extmem/dbus1_acs_cnt.rs b/esp32s2/src/extmem/dbus1_acs_cnt.rs
index 6314863545..c2ddf96761 100644
--- a/esp32s2/src/extmem/dbus1_acs_cnt.rs
+++ b/esp32s2/src/extmem/dbus1_acs_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS1_ACS_CNT")
-            .field(
-                "dbus1_acs_cnt",
-                &format_args!("{}", self.dbus1_acs_cnt().bits()),
-            )
+            .field("dbus1_acs_cnt", &self.dbus1_acs_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS1_ACS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus1_acs_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS1_ACS_CNT_SPEC;
 impl crate::RegisterSpec for DBUS1_ACS_CNT_SPEC {
diff --git a/esp32s2/src/extmem/dbus1_acs_miss_cnt.rs b/esp32s2/src/extmem/dbus1_acs_miss_cnt.rs
index 53cf0a94c3..b325f782aa 100644
--- a/esp32s2/src/extmem/dbus1_acs_miss_cnt.rs
+++ b/esp32s2/src/extmem/dbus1_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS1_ACS_MISS_CNT")
-            .field(
-                "dbus1_acs_miss_cnt",
-                &format_args!("{}", self.dbus1_acs_miss_cnt().bits()),
-            )
+            .field("dbus1_acs_miss_cnt", &self.dbus1_acs_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS1_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus1_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS1_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for DBUS1_ACS_MISS_CNT_SPEC {
diff --git a/esp32s2/src/extmem/dbus1_acs_wb_cnt.rs b/esp32s2/src/extmem/dbus1_acs_wb_cnt.rs
index 4f01e80cd5..c9c4248a5a 100644
--- a/esp32s2/src/extmem/dbus1_acs_wb_cnt.rs
+++ b/esp32s2/src/extmem/dbus1_acs_wb_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS1_ACS_WB_CNT")
-            .field(
-                "dbus1_acs_wb_cnt",
-                &format_args!("{}", self.dbus1_acs_wb_cnt().bits()),
-            )
+            .field("dbus1_acs_wb_cnt", &self.dbus1_acs_wb_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS1_ACS_WB_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus1_acs_wb_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS1_ACS_WB_CNT_SPEC;
 impl crate::RegisterSpec for DBUS1_ACS_WB_CNT_SPEC {
diff --git a/esp32s2/src/extmem/dbus2_abandon_cnt.rs b/esp32s2/src/extmem/dbus2_abandon_cnt.rs
index 8fb848aa3b..68b501f22e 100644
--- a/esp32s2/src/extmem/dbus2_abandon_cnt.rs
+++ b/esp32s2/src/extmem/dbus2_abandon_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS2_ABANDON_CNT")
-            .field(
-                "dbus2_abandon_cnt",
-                &format_args!("{}", self.dbus2_abandon_cnt().bits()),
-            )
+            .field("dbus2_abandon_cnt", &self.dbus2_abandon_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS2_ABANDON_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus2_abandon_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS2_ABANDON_CNT_SPEC;
 impl crate::RegisterSpec for DBUS2_ABANDON_CNT_SPEC {
diff --git a/esp32s2/src/extmem/dbus2_acs_cnt.rs b/esp32s2/src/extmem/dbus2_acs_cnt.rs
index 08f305d3c9..458586a7f1 100644
--- a/esp32s2/src/extmem/dbus2_acs_cnt.rs
+++ b/esp32s2/src/extmem/dbus2_acs_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS2_ACS_CNT")
-            .field(
-                "dbus2_acs_cnt",
-                &format_args!("{}", self.dbus2_acs_cnt().bits()),
-            )
+            .field("dbus2_acs_cnt", &self.dbus2_acs_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS2_ACS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus2_acs_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS2_ACS_CNT_SPEC;
 impl crate::RegisterSpec for DBUS2_ACS_CNT_SPEC {
diff --git a/esp32s2/src/extmem/dbus2_acs_miss_cnt.rs b/esp32s2/src/extmem/dbus2_acs_miss_cnt.rs
index 7f3fa16ef5..9d984ad8c3 100644
--- a/esp32s2/src/extmem/dbus2_acs_miss_cnt.rs
+++ b/esp32s2/src/extmem/dbus2_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS2_ACS_MISS_CNT")
-            .field(
-                "dbus2_acs_miss_cnt",
-                &format_args!("{}", self.dbus2_acs_miss_cnt().bits()),
-            )
+            .field("dbus2_acs_miss_cnt", &self.dbus2_acs_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS2_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus2_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS2_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for DBUS2_ACS_MISS_CNT_SPEC {
diff --git a/esp32s2/src/extmem/dbus2_acs_wb_cnt.rs b/esp32s2/src/extmem/dbus2_acs_wb_cnt.rs
index 94444017fd..9d65fd5541 100644
--- a/esp32s2/src/extmem/dbus2_acs_wb_cnt.rs
+++ b/esp32s2/src/extmem/dbus2_acs_wb_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS2_ACS_WB_CNT")
-            .field(
-                "dbus2_acs_wb_cnt",
-                &format_args!("{}", self.dbus2_acs_wb_cnt().bits()),
-            )
+            .field("dbus2_acs_wb_cnt", &self.dbus2_acs_wb_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS2_ACS_WB_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus2_acs_wb_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS2_ACS_WB_CNT_SPEC;
 impl crate::RegisterSpec for DBUS2_ACS_WB_CNT_SPEC {
diff --git a/esp32s2/src/extmem/dc_preload_cnt.rs b/esp32s2/src/extmem/dc_preload_cnt.rs
index e47f3a7d80..c1b36520f3 100644
--- a/esp32s2/src/extmem/dc_preload_cnt.rs
+++ b/esp32s2/src/extmem/dc_preload_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DC_PRELOAD_CNT")
-            .field(
-                "dc_preload_cnt",
-                &format_args!("{}", self.dc_preload_cnt().bits()),
-            )
+            .field("dc_preload_cnt", &self.dc_preload_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DC_PRELOAD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dc_preload_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DC_PRELOAD_CNT_SPEC;
 impl crate::RegisterSpec for DC_PRELOAD_CNT_SPEC {
diff --git a/esp32s2/src/extmem/dc_preload_evict_cnt.rs b/esp32s2/src/extmem/dc_preload_evict_cnt.rs
index 31b4e5a10a..94939dcfeb 100644
--- a/esp32s2/src/extmem/dc_preload_evict_cnt.rs
+++ b/esp32s2/src/extmem/dc_preload_evict_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DC_PRELOAD_EVICT_CNT")
-            .field(
-                "dc_preload_evict_cnt",
-                &format_args!("{}", self.dc_preload_evict_cnt().bits()),
-            )
+            .field("dc_preload_evict_cnt", &self.dc_preload_evict_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DC_PRELOAD_EVICT_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dc_preload_evict_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DC_PRELOAD_EVICT_CNT_SPEC;
 impl crate::RegisterSpec for DC_PRELOAD_EVICT_CNT_SPEC {
diff --git a/esp32s2/src/extmem/dc_preload_miss_cnt.rs b/esp32s2/src/extmem/dc_preload_miss_cnt.rs
index ce23fc22e5..629300b6eb 100644
--- a/esp32s2/src/extmem/dc_preload_miss_cnt.rs
+++ b/esp32s2/src/extmem/dc_preload_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DC_PRELOAD_MISS_CNT")
-            .field(
-                "dc_preload_miss_cnt",
-                &format_args!("{}", self.dc_preload_miss_cnt().bits()),
-            )
+            .field("dc_preload_miss_cnt", &self.dc_preload_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DC_PRELOAD_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dc_preload_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DC_PRELOAD_MISS_CNT_SPEC;
 impl crate::RegisterSpec for DC_PRELOAD_MISS_CNT_SPEC {
diff --git a/esp32s2/src/extmem/ibus0_abandon_cnt.rs b/esp32s2/src/extmem/ibus0_abandon_cnt.rs
index 92872823f9..e2aeed706d 100644
--- a/esp32s2/src/extmem/ibus0_abandon_cnt.rs
+++ b/esp32s2/src/extmem/ibus0_abandon_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS0_ABANDON_CNT")
-            .field(
-                "ibus0_abandon_cnt",
-                &format_args!("{}", self.ibus0_abandon_cnt().bits()),
-            )
+            .field("ibus0_abandon_cnt", &self.ibus0_abandon_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS0_ABANDON_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibus0_abandon_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IBUS0_ABANDON_CNT_SPEC;
 impl crate::RegisterSpec for IBUS0_ABANDON_CNT_SPEC {
diff --git a/esp32s2/src/extmem/ibus0_acs_cnt.rs b/esp32s2/src/extmem/ibus0_acs_cnt.rs
index 44e533d26b..cac23552db 100644
--- a/esp32s2/src/extmem/ibus0_acs_cnt.rs
+++ b/esp32s2/src/extmem/ibus0_acs_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS0_ACS_CNT")
-            .field(
-                "ibus0_acs_cnt",
-                &format_args!("{}", self.ibus0_acs_cnt().bits()),
-            )
+            .field("ibus0_acs_cnt", &self.ibus0_acs_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS0_ACS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibus0_acs_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IBUS0_ACS_CNT_SPEC;
 impl crate::RegisterSpec for IBUS0_ACS_CNT_SPEC {
diff --git a/esp32s2/src/extmem/ibus0_acs_miss_cnt.rs b/esp32s2/src/extmem/ibus0_acs_miss_cnt.rs
index 0bd31791f8..1fcec58877 100644
--- a/esp32s2/src/extmem/ibus0_acs_miss_cnt.rs
+++ b/esp32s2/src/extmem/ibus0_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS0_ACS_MISS_CNT")
-            .field(
-                "ibus0_acs_miss_cnt",
-                &format_args!("{}", self.ibus0_acs_miss_cnt().bits()),
-            )
+            .field("ibus0_acs_miss_cnt", &self.ibus0_acs_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS0_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibus0_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IBUS0_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for IBUS0_ACS_MISS_CNT_SPEC {
diff --git a/esp32s2/src/extmem/ibus1_abandon_cnt.rs b/esp32s2/src/extmem/ibus1_abandon_cnt.rs
index 6142962e6f..952731e15f 100644
--- a/esp32s2/src/extmem/ibus1_abandon_cnt.rs
+++ b/esp32s2/src/extmem/ibus1_abandon_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS1_ABANDON_CNT")
-            .field(
-                "ibus1_abandon_cnt",
-                &format_args!("{}", self.ibus1_abandon_cnt().bits()),
-            )
+            .field("ibus1_abandon_cnt", &self.ibus1_abandon_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS1_ABANDON_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibus1_abandon_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IBUS1_ABANDON_CNT_SPEC;
 impl crate::RegisterSpec for IBUS1_ABANDON_CNT_SPEC {
diff --git a/esp32s2/src/extmem/ibus1_acs_cnt.rs b/esp32s2/src/extmem/ibus1_acs_cnt.rs
index a8238f8d2e..81740a3b04 100644
--- a/esp32s2/src/extmem/ibus1_acs_cnt.rs
+++ b/esp32s2/src/extmem/ibus1_acs_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS1_ACS_CNT")
-            .field(
-                "ibus1_acs_cnt",
-                &format_args!("{}", self.ibus1_acs_cnt().bits()),
-            )
+            .field("ibus1_acs_cnt", &self.ibus1_acs_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS1_ACS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibus1_acs_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IBUS1_ACS_CNT_SPEC;
 impl crate::RegisterSpec for IBUS1_ACS_CNT_SPEC {
diff --git a/esp32s2/src/extmem/ibus1_acs_miss_cnt.rs b/esp32s2/src/extmem/ibus1_acs_miss_cnt.rs
index 5cf6afde1a..56417401e0 100644
--- a/esp32s2/src/extmem/ibus1_acs_miss_cnt.rs
+++ b/esp32s2/src/extmem/ibus1_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS1_ACS_MISS_CNT")
-            .field(
-                "ibus1_acs_miss_cnt",
-                &format_args!("{}", self.ibus1_acs_miss_cnt().bits()),
-            )
+            .field("ibus1_acs_miss_cnt", &self.ibus1_acs_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS1_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibus1_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IBUS1_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for IBUS1_ACS_MISS_CNT_SPEC {
diff --git a/esp32s2/src/extmem/ibus2_abandon_cnt.rs b/esp32s2/src/extmem/ibus2_abandon_cnt.rs
index f043f93df8..2fc50c0e63 100644
--- a/esp32s2/src/extmem/ibus2_abandon_cnt.rs
+++ b/esp32s2/src/extmem/ibus2_abandon_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS2_ABANDON_CNT")
-            .field(
-                "ibus2_abandon_cnt",
-                &format_args!("{}", self.ibus2_abandon_cnt().bits()),
-            )
+            .field("ibus2_abandon_cnt", &self.ibus2_abandon_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS2_ABANDON_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibus2_abandon_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IBUS2_ABANDON_CNT_SPEC;
 impl crate::RegisterSpec for IBUS2_ABANDON_CNT_SPEC {
diff --git a/esp32s2/src/extmem/ibus2_acs_cnt.rs b/esp32s2/src/extmem/ibus2_acs_cnt.rs
index 868583f14b..bdaf17b3cb 100644
--- a/esp32s2/src/extmem/ibus2_acs_cnt.rs
+++ b/esp32s2/src/extmem/ibus2_acs_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS2_ACS_CNT")
-            .field(
-                "ibus2_acs_cnt",
-                &format_args!("{}", self.ibus2_acs_cnt().bits()),
-            )
+            .field("ibus2_acs_cnt", &self.ibus2_acs_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS2_ACS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibus2_acs_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IBUS2_ACS_CNT_SPEC;
 impl crate::RegisterSpec for IBUS2_ACS_CNT_SPEC {
diff --git a/esp32s2/src/extmem/ibus2_acs_miss_cnt.rs b/esp32s2/src/extmem/ibus2_acs_miss_cnt.rs
index 10653e29a2..03f151116a 100644
--- a/esp32s2/src/extmem/ibus2_acs_miss_cnt.rs
+++ b/esp32s2/src/extmem/ibus2_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS2_ACS_MISS_CNT")
-            .field(
-                "ibus2_acs_miss_cnt",
-                &format_args!("{}", self.ibus2_acs_miss_cnt().bits()),
-            )
+            .field("ibus2_acs_miss_cnt", &self.ibus2_acs_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS2_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibus2_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IBUS2_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for IBUS2_ACS_MISS_CNT_SPEC {
diff --git a/esp32s2/src/extmem/ic_preload_cnt.rs b/esp32s2/src/extmem/ic_preload_cnt.rs
index 239e15406f..98e69b3a6a 100644
--- a/esp32s2/src/extmem/ic_preload_cnt.rs
+++ b/esp32s2/src/extmem/ic_preload_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IC_PRELOAD_CNT")
-            .field(
-                "ic_preload_cnt",
-                &format_args!("{}", self.ic_preload_cnt().bits()),
-            )
+            .field("ic_preload_cnt", &self.ic_preload_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IC_PRELOAD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ic_preload_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_PRELOAD_CNT_SPEC;
 impl crate::RegisterSpec for IC_PRELOAD_CNT_SPEC {
diff --git a/esp32s2/src/extmem/ic_preload_miss_cnt.rs b/esp32s2/src/extmem/ic_preload_miss_cnt.rs
index 22fa471ad8..0afa59c8eb 100644
--- a/esp32s2/src/extmem/ic_preload_miss_cnt.rs
+++ b/esp32s2/src/extmem/ic_preload_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IC_PRELOAD_MISS_CNT")
-            .field(
-                "ic_preload_miss_cnt",
-                &format_args!("{}", self.ic_preload_miss_cnt().bits()),
-            )
+            .field("ic_preload_miss_cnt", &self.ic_preload_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IC_PRELOAD_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ic_preload_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IC_PRELOAD_MISS_CNT_SPEC;
 impl crate::RegisterSpec for IC_PRELOAD_MISS_CNT_SPEC {
diff --git a/esp32s2/src/extmem/pro_cache_mmu_fault_content.rs b/esp32s2/src/extmem/pro_cache_mmu_fault_content.rs
index 68c52c4576..e17557e0bf 100644
--- a/esp32s2/src/extmem/pro_cache_mmu_fault_content.rs
+++ b/esp32s2/src/extmem/pro_cache_mmu_fault_content.rs
@@ -22,21 +22,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_CACHE_MMU_FAULT_CONTENT")
             .field(
                 "pro_cache_mmu_fault_content",
-                &format_args!("{}", self.pro_cache_mmu_fault_content().bits()),
-            )
-            .field(
-                "pro_cache_mmu_fault_code",
-                &format_args!("{}", self.pro_cache_mmu_fault_code().bits()),
+                &self.pro_cache_mmu_fault_content(),
             )
+            .field("pro_cache_mmu_fault_code", &self.pro_cache_mmu_fault_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_MMU_FAULT_CONTENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_cache_mmu_fault_content::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_CACHE_MMU_FAULT_CONTENT_SPEC;
 impl crate::RegisterSpec for PRO_CACHE_MMU_FAULT_CONTENT_SPEC {
diff --git a/esp32s2/src/extmem/pro_cache_mmu_fault_vaddr.rs b/esp32s2/src/extmem/pro_cache_mmu_fault_vaddr.rs
index f6a25a6164..73808677c4 100644
--- a/esp32s2/src/extmem/pro_cache_mmu_fault_vaddr.rs
+++ b/esp32s2/src/extmem/pro_cache_mmu_fault_vaddr.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_CACHE_MMU_FAULT_VADDR")
             .field(
                 "pro_cache_mmu_fault_vaddr",
-                &format_args!("{}", self.pro_cache_mmu_fault_vaddr().bits()),
+                &self.pro_cache_mmu_fault_vaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_MMU_FAULT_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_cache_mmu_fault_vaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_CACHE_MMU_FAULT_VADDR_SPEC;
 impl crate::RegisterSpec for PRO_CACHE_MMU_FAULT_VADDR_SPEC {
diff --git a/esp32s2/src/extmem/pro_cache_mmu_power_ctrl.rs b/esp32s2/src/extmem/pro_cache_mmu_power_ctrl.rs
index fb7ea05664..24bcece5e7 100644
--- a/esp32s2/src/extmem/pro_cache_mmu_power_ctrl.rs
+++ b/esp32s2/src/extmem/pro_cache_mmu_power_ctrl.rs
@@ -37,25 +37,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_CACHE_MMU_POWER_CTRL")
             .field(
                 "pro_cache_mmu_mem_force_on",
-                &format_args!("{}", self.pro_cache_mmu_mem_force_on().bit()),
+                &self.pro_cache_mmu_mem_force_on(),
             )
             .field(
                 "pro_cache_mmu_mem_force_pd",
-                &format_args!("{}", self.pro_cache_mmu_mem_force_pd().bit()),
+                &self.pro_cache_mmu_mem_force_pd(),
             )
             .field(
                 "pro_cache_mmu_mem_force_pu",
-                &format_args!("{}", self.pro_cache_mmu_mem_force_pu().bit()),
+                &self.pro_cache_mmu_mem_force_pu(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_MMU_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable"]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_cache_state.rs b/esp32s2/src/extmem/pro_cache_state.rs
index e46d2e144a..b0670e397d 100644
--- a/esp32s2/src/extmem/pro_cache_state.rs
+++ b/esp32s2/src/extmem/pro_cache_state.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CACHE_STATE")
-            .field(
-                "pro_icache_state",
-                &format_args!("{}", self.pro_icache_state().bits()),
-            )
-            .field(
-                "pro_dcache_state",
-                &format_args!("{}", self.pro_dcache_state().bits()),
-            )
+            .field("pro_icache_state", &self.pro_icache_state())
+            .field("pro_dcache_state", &self.pro_dcache_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_cache_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_CACHE_STATE_SPEC;
 impl crate::RegisterSpec for PRO_CACHE_STATE_SPEC {
diff --git a/esp32s2/src/extmem/pro_cache_wrap_around_ctrl.rs b/esp32s2/src/extmem/pro_cache_wrap_around_ctrl.rs
index 85b4f01e56..3d19d81255 100644
--- a/esp32s2/src/extmem/pro_cache_wrap_around_ctrl.rs
+++ b/esp32s2/src/extmem/pro_cache_wrap_around_ctrl.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_CACHE_WRAP_AROUND_CTRL")
             .field(
                 "pro_cache_flash_wrap_around",
-                &format_args!("{}", self.pro_cache_flash_wrap_around().bit()),
+                &self.pro_cache_flash_wrap_around(),
             )
             .field(
                 "pro_cache_sram_rd_wrap_around",
-                &format_args!("{}", self.pro_cache_sram_rd_wrap_around().bit()),
+                &self.pro_cache_sram_rd_wrap_around(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_WRAP_AROUND_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable wrap around mode when read data from flash."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_autoload_cfg.rs b/esp32s2/src/extmem/pro_dcache_autoload_cfg.rs
index c3152b46aa..59d6a4242c 100644
--- a/esp32s2/src/extmem/pro_dcache_autoload_cfg.rs
+++ b/esp32s2/src/extmem/pro_dcache_autoload_cfg.rs
@@ -71,43 +71,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_AUTOLOAD_CFG")
-            .field(
-                "pro_dcache_autoload_mode",
-                &format_args!("{}", self.pro_dcache_autoload_mode().bit()),
-            )
-            .field(
-                "pro_dcache_autoload_step",
-                &format_args!("{}", self.pro_dcache_autoload_step().bits()),
-            )
+            .field("pro_dcache_autoload_mode", &self.pro_dcache_autoload_mode())
+            .field("pro_dcache_autoload_step", &self.pro_dcache_autoload_step())
             .field(
                 "pro_dcache_autoload_order",
-                &format_args!("{}", self.pro_dcache_autoload_order().bit()),
-            )
-            .field(
-                "pro_dcache_autoload_rqst",
-                &format_args!("{}", self.pro_dcache_autoload_rqst().bits()),
-            )
-            .field(
-                "pro_dcache_autoload_size",
-                &format_args!("{}", self.pro_dcache_autoload_size().bits()),
+                &self.pro_dcache_autoload_order(),
             )
+            .field("pro_dcache_autoload_rqst", &self.pro_dcache_autoload_rqst())
+            .field("pro_dcache_autoload_size", &self.pro_dcache_autoload_size())
             .field(
                 "pro_dcache_autoload_sct0_ena",
-                &format_args!("{}", self.pro_dcache_autoload_sct0_ena().bit()),
+                &self.pro_dcache_autoload_sct0_ena(),
             )
             .field(
                 "pro_dcache_autoload_sct1_ena",
-                &format_args!("{}", self.pro_dcache_autoload_sct1_ena().bit()),
+                &self.pro_dcache_autoload_sct1_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_AUTOLOAD_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_autoload_section0_addr.rs b/esp32s2/src/extmem/pro_dcache_autoload_section0_addr.rs
index c84c8cc779..6218498382 100644
--- a/esp32s2/src/extmem/pro_dcache_autoload_section0_addr.rs
+++ b/esp32s2/src/extmem/pro_dcache_autoload_section0_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_DCACHE_AUTOLOAD_SECTION0_ADDR")
             .field(
                 "pro_dcache_autoload_sct0_addr",
-                &format_args!("{}", self.pro_dcache_autoload_sct0_addr().bits()),
+                &self.pro_dcache_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_AUTOLOAD_SECTION0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the first section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_autoload_section0_size.rs b/esp32s2/src/extmem/pro_dcache_autoload_section0_size.rs
index 6921f0c962..c7f6a5cfa1 100644
--- a/esp32s2/src/extmem/pro_dcache_autoload_section0_size.rs
+++ b/esp32s2/src/extmem/pro_dcache_autoload_section0_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_DCACHE_AUTOLOAD_SECTION0_SIZE")
             .field(
                 "pro_dcache_autoload_sct0_size",
-                &format_args!("{}", self.pro_dcache_autoload_sct0_size().bits()),
+                &self.pro_dcache_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_AUTOLOAD_SECTION0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - The bits are used to configure the length of the first section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_autoload_section1_addr.rs b/esp32s2/src/extmem/pro_dcache_autoload_section1_addr.rs
index 574555ac8b..b0992bbe07 100644
--- a/esp32s2/src/extmem/pro_dcache_autoload_section1_addr.rs
+++ b/esp32s2/src/extmem/pro_dcache_autoload_section1_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_DCACHE_AUTOLOAD_SECTION1_ADDR")
             .field(
                 "pro_dcache_autoload_sct1_addr",
-                &format_args!("{}", self.pro_dcache_autoload_sct1_addr().bits()),
+                &self.pro_dcache_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_AUTOLOAD_SECTION1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the second section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_autoload_section1_size.rs b/esp32s2/src/extmem/pro_dcache_autoload_section1_size.rs
index 842e8db8c3..9525fa01c6 100644
--- a/esp32s2/src/extmem/pro_dcache_autoload_section1_size.rs
+++ b/esp32s2/src/extmem/pro_dcache_autoload_section1_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_DCACHE_AUTOLOAD_SECTION1_SIZE")
             .field(
                 "pro_dcache_autoload_sct1_size",
-                &format_args!("{}", self.pro_dcache_autoload_sct1_size().bits()),
+                &self.pro_dcache_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_AUTOLOAD_SECTION1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - The bits are used to configure the length of the second section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_ctrl.rs b/esp32s2/src/extmem/pro_dcache_ctrl.rs
index afb5d427e1..dd7a0fa5ca 100644
--- a/esp32s2/src/extmem/pro_dcache_ctrl.rs
+++ b/esp32s2/src/extmem/pro_dcache_ctrl.rs
@@ -165,91 +165,37 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_CTRL")
-            .field(
-                "pro_dcache_enable",
-                &format_args!("{}", self.pro_dcache_enable().bit()),
-            )
-            .field(
-                "pro_dcache_setsize_mode",
-                &format_args!("{}", self.pro_dcache_setsize_mode().bit()),
-            )
+            .field("pro_dcache_enable", &self.pro_dcache_enable())
+            .field("pro_dcache_setsize_mode", &self.pro_dcache_setsize_mode())
             .field(
                 "pro_dcache_blocksize_mode",
-                &format_args!("{}", self.pro_dcache_blocksize_mode().bit()),
+                &self.pro_dcache_blocksize_mode(),
             )
             .field(
                 "pro_dcache_invalidate_ena",
-                &format_args!("{}", self.pro_dcache_invalidate_ena().bit()),
+                &self.pro_dcache_invalidate_ena(),
             )
             .field(
                 "pro_dcache_invalidate_done",
-                &format_args!("{}", self.pro_dcache_invalidate_done().bit()),
-            )
-            .field(
-                "pro_dcache_flush_ena",
-                &format_args!("{}", self.pro_dcache_flush_ena().bit()),
-            )
-            .field(
-                "pro_dcache_flush_done",
-                &format_args!("{}", self.pro_dcache_flush_done().bit()),
-            )
-            .field(
-                "pro_dcache_clean_ena",
-                &format_args!("{}", self.pro_dcache_clean_ena().bit()),
-            )
-            .field(
-                "pro_dcache_clean_done",
-                &format_args!("{}", self.pro_dcache_clean_done().bit()),
-            )
-            .field(
-                "pro_dcache_lock0_en",
-                &format_args!("{}", self.pro_dcache_lock0_en().bit()),
-            )
-            .field(
-                "pro_dcache_lock1_en",
-                &format_args!("{}", self.pro_dcache_lock1_en().bit()),
-            )
-            .field(
-                "pro_dcache_autoload_ena",
-                &format_args!("{}", self.pro_dcache_autoload_ena().bit()),
-            )
-            .field(
-                "pro_dcache_autoload_done",
-                &format_args!("{}", self.pro_dcache_autoload_done().bit()),
-            )
-            .field(
-                "pro_dcache_preload_ena",
-                &format_args!("{}", self.pro_dcache_preload_ena().bit()),
-            )
-            .field(
-                "pro_dcache_preload_done",
-                &format_args!("{}", self.pro_dcache_preload_done().bit()),
-            )
-            .field(
-                "pro_dcache_unlock_ena",
-                &format_args!("{}", self.pro_dcache_unlock_ena().bit()),
-            )
-            .field(
-                "pro_dcache_unlock_done",
-                &format_args!("{}", self.pro_dcache_unlock_done().bit()),
-            )
-            .field(
-                "pro_dcache_lock_ena",
-                &format_args!("{}", self.pro_dcache_lock_ena().bit()),
-            )
-            .field(
-                "pro_dcache_lock_done",
-                &format_args!("{}", self.pro_dcache_lock_done().bit()),
+                &self.pro_dcache_invalidate_done(),
             )
+            .field("pro_dcache_flush_ena", &self.pro_dcache_flush_ena())
+            .field("pro_dcache_flush_done", &self.pro_dcache_flush_done())
+            .field("pro_dcache_clean_ena", &self.pro_dcache_clean_ena())
+            .field("pro_dcache_clean_done", &self.pro_dcache_clean_done())
+            .field("pro_dcache_lock0_en", &self.pro_dcache_lock0_en())
+            .field("pro_dcache_lock1_en", &self.pro_dcache_lock1_en())
+            .field("pro_dcache_autoload_ena", &self.pro_dcache_autoload_ena())
+            .field("pro_dcache_autoload_done", &self.pro_dcache_autoload_done())
+            .field("pro_dcache_preload_ena", &self.pro_dcache_preload_ena())
+            .field("pro_dcache_preload_done", &self.pro_dcache_preload_done())
+            .field("pro_dcache_unlock_ena", &self.pro_dcache_unlock_ena())
+            .field("pro_dcache_unlock_done", &self.pro_dcache_unlock_done())
+            .field("pro_dcache_lock_ena", &self.pro_dcache_lock_ena())
+            .field("pro_dcache_lock_done", &self.pro_dcache_lock_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_ctrl1.rs b/esp32s2/src/extmem/pro_dcache_ctrl1.rs
index be482ecdef..97499b552f 100644
--- a/esp32s2/src/extmem/pro_dcache_ctrl1.rs
+++ b/esp32s2/src/extmem/pro_dcache_ctrl1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_CTRL1")
-            .field(
-                "pro_dcache_mask_bus0",
-                &format_args!("{}", self.pro_dcache_mask_bus0().bit()),
-            )
-            .field(
-                "pro_dcache_mask_bus1",
-                &format_args!("{}", self.pro_dcache_mask_bus1().bit()),
-            )
-            .field(
-                "pro_dcache_mask_bus2",
-                &format_args!("{}", self.pro_dcache_mask_bus2().bit()),
-            )
+            .field("pro_dcache_mask_bus0", &self.pro_dcache_mask_bus0())
+            .field("pro_dcache_mask_bus1", &self.pro_dcache_mask_bus1())
+            .field("pro_dcache_mask_bus2", &self.pro_dcache_mask_bus2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable dbus0, 0: enable, 1: disable"]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_lock0_addr.rs b/esp32s2/src/extmem/pro_dcache_lock0_addr.rs
index 3c77a35eb6..2c6d65e815 100644
--- a/esp32s2/src/extmem/pro_dcache_lock0_addr.rs
+++ b/esp32s2/src/extmem/pro_dcache_lock0_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_LOCK0_ADDR")
-            .field(
-                "pro_dcache_lock0_addr",
-                &format_args!("{}", self.pro_dcache_lock0_addr().bits()),
-            )
+            .field("pro_dcache_lock0_addr", &self.pro_dcache_lock0_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_LOCK0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the first start virtual address of data locking, which is combined with PRO_DCACHE_LOCK0_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_lock0_size.rs b/esp32s2/src/extmem/pro_dcache_lock0_size.rs
index 26b762c4b2..847f930708 100644
--- a/esp32s2/src/extmem/pro_dcache_lock0_size.rs
+++ b/esp32s2/src/extmem/pro_dcache_lock0_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_LOCK0_SIZE")
-            .field(
-                "pro_dcache_lock0_size",
-                &format_args!("{}", self.pro_dcache_lock0_size().bits()),
-            )
+            .field("pro_dcache_lock0_size", &self.pro_dcache_lock0_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_LOCK0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the first length of data locking, which is combined with PRO_DCACHE_LOCK0_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_lock1_addr.rs b/esp32s2/src/extmem/pro_dcache_lock1_addr.rs
index d472f883b2..cd88691f2b 100644
--- a/esp32s2/src/extmem/pro_dcache_lock1_addr.rs
+++ b/esp32s2/src/extmem/pro_dcache_lock1_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_LOCK1_ADDR")
-            .field(
-                "pro_dcache_lock1_addr",
-                &format_args!("{}", self.pro_dcache_lock1_addr().bits()),
-            )
+            .field("pro_dcache_lock1_addr", &self.pro_dcache_lock1_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_LOCK1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the second start virtual address of data locking, which is combined with PRO_DCACHE_LOCK1_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_lock1_size.rs b/esp32s2/src/extmem/pro_dcache_lock1_size.rs
index 0ed04b666b..9698344ba2 100644
--- a/esp32s2/src/extmem/pro_dcache_lock1_size.rs
+++ b/esp32s2/src/extmem/pro_dcache_lock1_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_LOCK1_SIZE")
-            .field(
-                "pro_dcache_lock1_size",
-                &format_args!("{}", self.pro_dcache_lock1_size().bits()),
-            )
+            .field("pro_dcache_lock1_size", &self.pro_dcache_lock1_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_LOCK1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the second length of data locking, which is combined with PRO_DCACHE_LOCK1_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_mem_sync0.rs b/esp32s2/src/extmem/pro_dcache_mem_sync0.rs
index 554f258360..fe37554edb 100644
--- a/esp32s2/src/extmem/pro_dcache_mem_sync0.rs
+++ b/esp32s2/src/extmem/pro_dcache_mem_sync0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_MEM_SYNC0")
-            .field(
-                "pro_dcache_memsync_addr",
-                &format_args!("{}", self.pro_dcache_memsync_addr().bits()),
-            )
+            .field("pro_dcache_memsync_addr", &self.pro_dcache_memsync_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_MEM_SYNC0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC1."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_mem_sync1.rs b/esp32s2/src/extmem/pro_dcache_mem_sync1.rs
index e2e2a0633e..11ce28c939 100644
--- a/esp32s2/src/extmem/pro_dcache_mem_sync1.rs
+++ b/esp32s2/src/extmem/pro_dcache_mem_sync1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_MEM_SYNC1")
-            .field(
-                "pro_dcache_memsync_size",
-                &format_args!("{}", self.pro_dcache_memsync_size().bits()),
-            )
+            .field("pro_dcache_memsync_size", &self.pro_dcache_memsync_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_MEM_SYNC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:18 - The bits are used to configure the length for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC0."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_preload_addr.rs b/esp32s2/src/extmem/pro_dcache_preload_addr.rs
index 67bd501906..c3b874434c 100644
--- a/esp32s2/src/extmem/pro_dcache_preload_addr.rs
+++ b/esp32s2/src/extmem/pro_dcache_preload_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_PRELOAD_ADDR")
-            .field(
-                "pro_dcache_preload_addr",
-                &format_args!("{}", self.pro_dcache_preload_addr().bits()),
-            )
+            .field("pro_dcache_preload_addr", &self.pro_dcache_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for manual pre-load operation. It should be combined with PRO_DCACHE_PRELOAD_SIZE_REG."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_preload_size.rs b/esp32s2/src/extmem/pro_dcache_preload_size.rs
index c2044146d4..75a6a3d2f6 100644
--- a/esp32s2/src/extmem/pro_dcache_preload_size.rs
+++ b/esp32s2/src/extmem/pro_dcache_preload_size.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_PRELOAD_SIZE")
-            .field(
-                "pro_dcache_preload_size",
-                &format_args!("{}", self.pro_dcache_preload_size().bits()),
-            )
-            .field(
-                "pro_dcache_preload_order",
-                &format_args!("{}", self.pro_dcache_preload_order().bit()),
-            )
+            .field("pro_dcache_preload_size", &self.pro_dcache_preload_size())
+            .field("pro_dcache_preload_order", &self.pro_dcache_preload_order())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The bits are used to configure the length for manual pre-load operation. It should be combined with PRO_DCACHE_PRELOAD_ADDR_REG.."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_dcache_reject_st.rs b/esp32s2/src/extmem/pro_dcache_reject_st.rs
index c62db5235c..3911d877d4 100644
--- a/esp32s2/src/extmem/pro_dcache_reject_st.rs
+++ b/esp32s2/src/extmem/pro_dcache_reject_st.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_REJECT_ST")
-            .field(
-                "pro_dcache_tag_attr",
-                &format_args!("{}", self.pro_dcache_tag_attr().bits()),
-            )
-            .field(
-                "pro_dcache_cpu_attr",
-                &format_args!("{}", self.pro_dcache_cpu_attr().bits()),
-            )
+            .field("pro_dcache_tag_attr", &self.pro_dcache_tag_attr())
+            .field("pro_dcache_cpu_attr", &self.pro_dcache_cpu_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_REJECT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_dcache_reject_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_DCACHE_REJECT_ST_SPEC;
 impl crate::RegisterSpec for PRO_DCACHE_REJECT_ST_SPEC {
diff --git a/esp32s2/src/extmem/pro_dcache_reject_vaddr.rs b/esp32s2/src/extmem/pro_dcache_reject_vaddr.rs
index 0bd694cc0d..fb2bbcb04e 100644
--- a/esp32s2/src/extmem/pro_dcache_reject_vaddr.rs
+++ b/esp32s2/src/extmem/pro_dcache_reject_vaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_REJECT_VADDR")
-            .field(
-                "pro_dcache_cpu_vaddr",
-                &format_args!("{}", self.pro_dcache_cpu_vaddr().bits()),
-            )
+            .field("pro_dcache_cpu_vaddr", &self.pro_dcache_cpu_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_REJECT_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_dcache_reject_vaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_DCACHE_REJECT_VADDR_SPEC;
 impl crate::RegisterSpec for PRO_DCACHE_REJECT_VADDR_SPEC {
diff --git a/esp32s2/src/extmem/pro_dcache_tag_power_ctrl.rs b/esp32s2/src/extmem/pro_dcache_tag_power_ctrl.rs
index 2d21dedd1f..bfb8d92225 100644
--- a/esp32s2/src/extmem/pro_dcache_tag_power_ctrl.rs
+++ b/esp32s2/src/extmem/pro_dcache_tag_power_ctrl.rs
@@ -37,25 +37,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_DCACHE_TAG_POWER_CTRL")
             .field(
                 "pro_dcache_tag_mem_force_on",
-                &format_args!("{}", self.pro_dcache_tag_mem_force_on().bit()),
+                &self.pro_dcache_tag_mem_force_on(),
             )
             .field(
                 "pro_dcache_tag_mem_force_pd",
-                &format_args!("{}", self.pro_dcache_tag_mem_force_pd().bit()),
+                &self.pro_dcache_tag_mem_force_pd(),
             )
             .field(
                 "pro_dcache_tag_mem_force_pu",
-                &format_args!("{}", self.pro_dcache_tag_mem_force_pu().bit()),
+                &self.pro_dcache_tag_mem_force_pu(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_TAG_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_extmem_reg_date.rs b/esp32s2/src/extmem/pro_extmem_reg_date.rs
index 25f489719b..74bbd6906f 100644
--- a/esp32s2/src/extmem/pro_extmem_reg_date.rs
+++ b/esp32s2/src/extmem/pro_extmem_reg_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_EXTMEM_REG_DATE")
-            .field(
-                "pro_extmem_reg_date",
-                &format_args!("{}", self.pro_extmem_reg_date().bits()),
-            )
+            .field("pro_extmem_reg_date", &self.pro_extmem_reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_EXTMEM_REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Reserved."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_autoload_cfg.rs b/esp32s2/src/extmem/pro_icache_autoload_cfg.rs
index bb1e759a52..09bdcaff36 100644
--- a/esp32s2/src/extmem/pro_icache_autoload_cfg.rs
+++ b/esp32s2/src/extmem/pro_icache_autoload_cfg.rs
@@ -71,43 +71,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_ICACHE_AUTOLOAD_CFG")
-            .field(
-                "pro_icache_autoload_mode",
-                &format_args!("{}", self.pro_icache_autoload_mode().bit()),
-            )
-            .field(
-                "pro_icache_autoload_step",
-                &format_args!("{}", self.pro_icache_autoload_step().bits()),
-            )
+            .field("pro_icache_autoload_mode", &self.pro_icache_autoload_mode())
+            .field("pro_icache_autoload_step", &self.pro_icache_autoload_step())
             .field(
                 "pro_icache_autoload_order",
-                &format_args!("{}", self.pro_icache_autoload_order().bit()),
-            )
-            .field(
-                "pro_icache_autoload_rqst",
-                &format_args!("{}", self.pro_icache_autoload_rqst().bits()),
-            )
-            .field(
-                "pro_icache_autoload_size",
-                &format_args!("{}", self.pro_icache_autoload_size().bits()),
+                &self.pro_icache_autoload_order(),
             )
+            .field("pro_icache_autoload_rqst", &self.pro_icache_autoload_rqst())
+            .field("pro_icache_autoload_size", &self.pro_icache_autoload_size())
             .field(
                 "pro_icache_autoload_sct0_ena",
-                &format_args!("{}", self.pro_icache_autoload_sct0_ena().bit()),
+                &self.pro_icache_autoload_sct0_ena(),
             )
             .field(
                 "pro_icache_autoload_sct1_ena",
-                &format_args!("{}", self.pro_icache_autoload_sct1_ena().bit()),
+                &self.pro_icache_autoload_sct1_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_AUTOLOAD_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_autoload_section0_addr.rs b/esp32s2/src/extmem/pro_icache_autoload_section0_addr.rs
index 7dc85feebf..c0726bc959 100644
--- a/esp32s2/src/extmem/pro_icache_autoload_section0_addr.rs
+++ b/esp32s2/src/extmem/pro_icache_autoload_section0_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_ICACHE_AUTOLOAD_SECTION0_ADDR")
             .field(
                 "pro_icache_autoload_sct0_addr",
-                &format_args!("{}", self.pro_icache_autoload_sct0_addr().bits()),
+                &self.pro_icache_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_AUTOLOAD_SECTION0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the first section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_autoload_section0_size.rs b/esp32s2/src/extmem/pro_icache_autoload_section0_size.rs
index 230aa15d14..62877c86e2 100644
--- a/esp32s2/src/extmem/pro_icache_autoload_section0_size.rs
+++ b/esp32s2/src/extmem/pro_icache_autoload_section0_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_ICACHE_AUTOLOAD_SECTION0_SIZE")
             .field(
                 "pro_icache_autoload_sct0_size",
-                &format_args!("{}", self.pro_icache_autoload_sct0_size().bits()),
+                &self.pro_icache_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_AUTOLOAD_SECTION0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - The bits are used to configure the length of the first section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_autoload_section1_addr.rs b/esp32s2/src/extmem/pro_icache_autoload_section1_addr.rs
index f38bad197c..b8f69b2c4a 100644
--- a/esp32s2/src/extmem/pro_icache_autoload_section1_addr.rs
+++ b/esp32s2/src/extmem/pro_icache_autoload_section1_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_ICACHE_AUTOLOAD_SECTION1_ADDR")
             .field(
                 "pro_icache_autoload_sct1_addr",
-                &format_args!("{}", self.pro_icache_autoload_sct1_addr().bits()),
+                &self.pro_icache_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_AUTOLOAD_SECTION1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the second section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_autoload_section1_size.rs b/esp32s2/src/extmem/pro_icache_autoload_section1_size.rs
index 3357bcb8e8..7d71f3f941 100644
--- a/esp32s2/src/extmem/pro_icache_autoload_section1_size.rs
+++ b/esp32s2/src/extmem/pro_icache_autoload_section1_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_ICACHE_AUTOLOAD_SECTION1_SIZE")
             .field(
                 "pro_icache_autoload_sct1_size",
-                &format_args!("{}", self.pro_icache_autoload_sct1_size().bits()),
+                &self.pro_icache_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_AUTOLOAD_SECTION1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - The bits are used to configure the length of the second section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_ctrl.rs b/esp32s2/src/extmem/pro_icache_ctrl.rs
index 4e30078a21..f46a89b97f 100644
--- a/esp32s2/src/extmem/pro_icache_ctrl.rs
+++ b/esp32s2/src/extmem/pro_icache_ctrl.rs
@@ -133,75 +133,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_ICACHE_CTRL")
-            .field(
-                "pro_icache_enable",
-                &format_args!("{}", self.pro_icache_enable().bit()),
-            )
-            .field(
-                "pro_icache_setsize_mode",
-                &format_args!("{}", self.pro_icache_setsize_mode().bit()),
-            )
+            .field("pro_icache_enable", &self.pro_icache_enable())
+            .field("pro_icache_setsize_mode", &self.pro_icache_setsize_mode())
             .field(
                 "pro_icache_blocksize_mode",
-                &format_args!("{}", self.pro_icache_blocksize_mode().bit()),
+                &self.pro_icache_blocksize_mode(),
             )
             .field(
                 "pro_icache_invalidate_ena",
-                &format_args!("{}", self.pro_icache_invalidate_ena().bit()),
+                &self.pro_icache_invalidate_ena(),
             )
             .field(
                 "pro_icache_invalidate_done",
-                &format_args!("{}", self.pro_icache_invalidate_done().bit()),
-            )
-            .field(
-                "pro_icache_lock0_en",
-                &format_args!("{}", self.pro_icache_lock0_en().bit()),
-            )
-            .field(
-                "pro_icache_lock1_en",
-                &format_args!("{}", self.pro_icache_lock1_en().bit()),
-            )
-            .field(
-                "pro_icache_autoload_ena",
-                &format_args!("{}", self.pro_icache_autoload_ena().bit()),
-            )
-            .field(
-                "pro_icache_autoload_done",
-                &format_args!("{}", self.pro_icache_autoload_done().bit()),
-            )
-            .field(
-                "pro_icache_preload_ena",
-                &format_args!("{}", self.pro_icache_preload_ena().bit()),
-            )
-            .field(
-                "pro_icache_preload_done",
-                &format_args!("{}", self.pro_icache_preload_done().bit()),
-            )
-            .field(
-                "pro_icache_unlock_ena",
-                &format_args!("{}", self.pro_icache_unlock_ena().bit()),
-            )
-            .field(
-                "pro_icache_unlock_done",
-                &format_args!("{}", self.pro_icache_unlock_done().bit()),
-            )
-            .field(
-                "pro_icache_lock_ena",
-                &format_args!("{}", self.pro_icache_lock_ena().bit()),
-            )
-            .field(
-                "pro_icache_lock_done",
-                &format_args!("{}", self.pro_icache_lock_done().bit()),
+                &self.pro_icache_invalidate_done(),
             )
+            .field("pro_icache_lock0_en", &self.pro_icache_lock0_en())
+            .field("pro_icache_lock1_en", &self.pro_icache_lock1_en())
+            .field("pro_icache_autoload_ena", &self.pro_icache_autoload_ena())
+            .field("pro_icache_autoload_done", &self.pro_icache_autoload_done())
+            .field("pro_icache_preload_ena", &self.pro_icache_preload_ena())
+            .field("pro_icache_preload_done", &self.pro_icache_preload_done())
+            .field("pro_icache_unlock_ena", &self.pro_icache_unlock_ena())
+            .field("pro_icache_unlock_done", &self.pro_icache_unlock_done())
+            .field("pro_icache_lock_ena", &self.pro_icache_lock_ena())
+            .field("pro_icache_lock_done", &self.pro_icache_lock_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_ctrl1.rs b/esp32s2/src/extmem/pro_icache_ctrl1.rs
index 0b135be96a..378f6fe857 100644
--- a/esp32s2/src/extmem/pro_icache_ctrl1.rs
+++ b/esp32s2/src/extmem/pro_icache_ctrl1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_ICACHE_CTRL1")
-            .field(
-                "pro_icache_mask_bus0",
-                &format_args!("{}", self.pro_icache_mask_bus0().bit()),
-            )
-            .field(
-                "pro_icache_mask_bus1",
-                &format_args!("{}", self.pro_icache_mask_bus1().bit()),
-            )
-            .field(
-                "pro_icache_mask_bus2",
-                &format_args!("{}", self.pro_icache_mask_bus2().bit()),
-            )
+            .field("pro_icache_mask_bus0", &self.pro_icache_mask_bus0())
+            .field("pro_icache_mask_bus1", &self.pro_icache_mask_bus1())
+            .field("pro_icache_mask_bus2", &self.pro_icache_mask_bus2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable ibus0, 0: enable, 1: disable"]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_lock0_addr.rs b/esp32s2/src/extmem/pro_icache_lock0_addr.rs
index 058e2d4a50..ef76a5c1f3 100644
--- a/esp32s2/src/extmem/pro_icache_lock0_addr.rs
+++ b/esp32s2/src/extmem/pro_icache_lock0_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_ICACHE_LOCK0_ADDR")
-            .field(
-                "pro_icache_lock0_addr",
-                &format_args!("{}", self.pro_icache_lock0_addr().bits()),
-            )
+            .field("pro_icache_lock0_addr", &self.pro_icache_lock0_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_LOCK0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the first start virtual address of data locking, which is combined with PRO_ICACHE_LOCK0_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_lock0_size.rs b/esp32s2/src/extmem/pro_icache_lock0_size.rs
index fe4c15429e..97f3d21817 100644
--- a/esp32s2/src/extmem/pro_icache_lock0_size.rs
+++ b/esp32s2/src/extmem/pro_icache_lock0_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_ICACHE_LOCK0_SIZE")
-            .field(
-                "pro_icache_lock0_size",
-                &format_args!("{}", self.pro_icache_lock0_size().bits()),
-            )
+            .field("pro_icache_lock0_size", &self.pro_icache_lock0_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_LOCK0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the first length of data locking, which is combined with PRO_ICACHE_LOCK0_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_lock1_addr.rs b/esp32s2/src/extmem/pro_icache_lock1_addr.rs
index 44a4789504..400645302f 100644
--- a/esp32s2/src/extmem/pro_icache_lock1_addr.rs
+++ b/esp32s2/src/extmem/pro_icache_lock1_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_ICACHE_LOCK1_ADDR")
-            .field(
-                "pro_icache_lock1_addr",
-                &format_args!("{}", self.pro_icache_lock1_addr().bits()),
-            )
+            .field("pro_icache_lock1_addr", &self.pro_icache_lock1_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_LOCK1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the second start virtual address of data locking, which is combined with PRO_ICACHE_LOCK1_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_lock1_size.rs b/esp32s2/src/extmem/pro_icache_lock1_size.rs
index e58a08b6a2..808632ccde 100644
--- a/esp32s2/src/extmem/pro_icache_lock1_size.rs
+++ b/esp32s2/src/extmem/pro_icache_lock1_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_ICACHE_LOCK1_SIZE")
-            .field(
-                "pro_icache_lock1_size",
-                &format_args!("{}", self.pro_icache_lock1_size().bits()),
-            )
+            .field("pro_icache_lock1_size", &self.pro_icache_lock1_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_LOCK1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the second length of data locking, which is combined with PRO_ICACHE_LOCK1_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_mem_sync0.rs b/esp32s2/src/extmem/pro_icache_mem_sync0.rs
index f9af17c551..3672751b41 100644
--- a/esp32s2/src/extmem/pro_icache_mem_sync0.rs
+++ b/esp32s2/src/extmem/pro_icache_mem_sync0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_ICACHE_MEM_SYNC0")
-            .field(
-                "pro_icache_memsync_addr",
-                &format_args!("{}", self.pro_icache_memsync_addr().bits()),
-            )
+            .field("pro_icache_memsync_addr", &self.pro_icache_memsync_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_MEM_SYNC0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC1."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_mem_sync1.rs b/esp32s2/src/extmem/pro_icache_mem_sync1.rs
index fcb74d04ae..1ed359220d 100644
--- a/esp32s2/src/extmem/pro_icache_mem_sync1.rs
+++ b/esp32s2/src/extmem/pro_icache_mem_sync1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_ICACHE_MEM_SYNC1")
-            .field(
-                "pro_icache_memsync_size",
-                &format_args!("{}", self.pro_icache_memsync_size().bits()),
-            )
+            .field("pro_icache_memsync_size", &self.pro_icache_memsync_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_MEM_SYNC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:18 - The bits are used to configure the length for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC0."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_preload_addr.rs b/esp32s2/src/extmem/pro_icache_preload_addr.rs
index 4ece480528..d1c381616e 100644
--- a/esp32s2/src/extmem/pro_icache_preload_addr.rs
+++ b/esp32s2/src/extmem/pro_icache_preload_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_ICACHE_PRELOAD_ADDR")
-            .field(
-                "pro_icache_preload_addr",
-                &format_args!("{}", self.pro_icache_preload_addr().bits()),
-            )
+            .field("pro_icache_preload_addr", &self.pro_icache_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for manual pre-load operation. It should be combined with PRO_ICACHE_PRELOAD_SIZE_REG."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_preload_size.rs b/esp32s2/src/extmem/pro_icache_preload_size.rs
index d9eac1ea40..307f1cd3a2 100644
--- a/esp32s2/src/extmem/pro_icache_preload_size.rs
+++ b/esp32s2/src/extmem/pro_icache_preload_size.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_ICACHE_PRELOAD_SIZE")
-            .field(
-                "pro_icache_preload_size",
-                &format_args!("{}", self.pro_icache_preload_size().bits()),
-            )
-            .field(
-                "pro_icache_preload_order",
-                &format_args!("{}", self.pro_icache_preload_order().bit()),
-            )
+            .field("pro_icache_preload_size", &self.pro_icache_preload_size())
+            .field("pro_icache_preload_order", &self.pro_icache_preload_order())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The bits are used to configure the length for manual pre-load operation. It should be combined with PRO_ICACHE_PRELOAD_ADDR_REG.."]
     #[inline(always)]
diff --git a/esp32s2/src/extmem/pro_icache_reject_st.rs b/esp32s2/src/extmem/pro_icache_reject_st.rs
index ee39295cf7..e91234cfea 100644
--- a/esp32s2/src/extmem/pro_icache_reject_st.rs
+++ b/esp32s2/src/extmem/pro_icache_reject_st.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_ICACHE_REJECT_ST")
-            .field(
-                "pro_icache_tag_attr",
-                &format_args!("{}", self.pro_icache_tag_attr().bits()),
-            )
-            .field(
-                "pro_icache_cpu_attr",
-                &format_args!("{}", self.pro_icache_cpu_attr().bits()),
-            )
+            .field("pro_icache_tag_attr", &self.pro_icache_tag_attr())
+            .field("pro_icache_cpu_attr", &self.pro_icache_cpu_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_REJECT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_icache_reject_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_ICACHE_REJECT_ST_SPEC;
 impl crate::RegisterSpec for PRO_ICACHE_REJECT_ST_SPEC {
diff --git a/esp32s2/src/extmem/pro_icache_reject_vaddr.rs b/esp32s2/src/extmem/pro_icache_reject_vaddr.rs
index 4d67960e79..0682a8132d 100644
--- a/esp32s2/src/extmem/pro_icache_reject_vaddr.rs
+++ b/esp32s2/src/extmem/pro_icache_reject_vaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_ICACHE_REJECT_VADDR")
-            .field(
-                "pro_icache_cpu_vaddr",
-                &format_args!("{}", self.pro_icache_cpu_vaddr().bits()),
-            )
+            .field("pro_icache_cpu_vaddr", &self.pro_icache_cpu_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_REJECT_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "register description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_icache_reject_vaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_ICACHE_REJECT_VADDR_SPEC;
 impl crate::RegisterSpec for PRO_ICACHE_REJECT_VADDR_SPEC {
diff --git a/esp32s2/src/extmem/pro_icache_tag_power_ctrl.rs b/esp32s2/src/extmem/pro_icache_tag_power_ctrl.rs
index 3bb9aebd0c..505e6bc7de 100644
--- a/esp32s2/src/extmem/pro_icache_tag_power_ctrl.rs
+++ b/esp32s2/src/extmem/pro_icache_tag_power_ctrl.rs
@@ -37,25 +37,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_ICACHE_TAG_POWER_CTRL")
             .field(
                 "pro_icache_tag_mem_force_on",
-                &format_args!("{}", self.pro_icache_tag_mem_force_on().bit()),
+                &self.pro_icache_tag_mem_force_on(),
             )
             .field(
                 "pro_icache_tag_mem_force_pd",
-                &format_args!("{}", self.pro_icache_tag_mem_force_pd().bit()),
+                &self.pro_icache_tag_mem_force_pd(),
             )
             .field(
                 "pro_icache_tag_mem_force_pu",
-                &format_args!("{}", self.pro_icache_tag_mem_force_pu().bit()),
+                &self.pro_icache_tag_mem_force_pu(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_TAG_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32s2/src/generic.rs b/esp32s2/src/generic.rs
index a2ae6aa053..45ebed16c4 100644
--- a/esp32s2/src/generic.rs
+++ b/esp32s2/src/generic.rs
@@ -48,7 +48,7 @@ pub trait RegisterSpec {
 #[doc = " Raw field type"]
 pub trait FieldSpec: Sized {
     #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
-    type Ux: Copy + PartialEq + From<Self>;
+    type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
 }
 #[doc = " Marker for fields with fixed values"]
 pub trait IsEnum: FieldSpec {}
@@ -237,6 +237,14 @@ impl<REG: Readable + Writable> Reg<REG> {
         );
     }
 }
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
 #[doc(hidden)]
 pub mod raw;
 #[doc = " Register reader."]
@@ -302,6 +310,11 @@ impl<FI: FieldSpec> FieldReader<FI> {
         self.bits
     }
 }
+impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 impl<FI> PartialEq<FI> for FieldReader<FI>
 where
     FI: FieldSpec + Copy,
@@ -338,10 +351,21 @@ impl<FI> BitReader<FI> {
         self.bit()
     }
 }
+impl<FI> core::fmt::Debug for BitReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 #[doc = " Marker for register/field writers which can take any value of specified width"]
 pub struct Safe;
 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
 pub struct Unsafe;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct Range<const MIN: u64, const MAX: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeFrom<const MIN: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeTo<const MAX: u64>;
 #[doc = " Write field Proxy"]
 pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
     raw::FieldWriter<'a, REG, WI, FI, Safety>;
@@ -393,6 +417,58 @@ where
         unsafe { self.bits(value) }
     }
 }
+impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
+    FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN && value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
 impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
diff --git a/esp32s2/src/gpio/bt_select.rs b/esp32s2/src/gpio/bt_select.rs
index a0be50c040..3d29133a18 100644
--- a/esp32s2/src/gpio/bt_select.rs
+++ b/esp32s2/src/gpio/bt_select.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_SELECT")
-            .field("bt_sel", &format_args!("{}", self.bt_sel().bits()))
+            .field("bt_sel", &self.bt_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_SELECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved"]
     #[inline(always)]
diff --git a/esp32s2/src/gpio/clock_gate.rs b/esp32s2/src/gpio/clock_gate.rs
index f5d6c627d7..5520ef8cce 100644
--- a/esp32s2/src/gpio/clock_gate.rs
+++ b/esp32s2/src/gpio/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Clock gating enable bit. If set to 1, the clock is free running."]
     #[inline(always)]
diff --git a/esp32s2/src/gpio/cpusdio_int.rs b/esp32s2/src/gpio/cpusdio_int.rs
index a0131cb852..23fab64612 100644
--- a/esp32s2/src/gpio/cpusdio_int.rs
+++ b/esp32s2/src/gpio/cpusdio_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPUSDIO_INT")
-            .field("sdio_int", &format_args!("{}", self.sdio_int().bits()))
+            .field("sdio_int", &self.sdio_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPUSDIO_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO0 ~ 31 CPU SDIO interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpusdio_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPUSDIO_INT_SPEC;
 impl crate::RegisterSpec for CPUSDIO_INT_SPEC {
diff --git a/esp32s2/src/gpio/cpusdio_int1.rs b/esp32s2/src/gpio/cpusdio_int1.rs
index ea24c02145..72a33c1e73 100644
--- a/esp32s2/src/gpio/cpusdio_int1.rs
+++ b/esp32s2/src/gpio/cpusdio_int1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPUSDIO_INT1")
-            .field("sdio1_int", &format_args!("{}", self.sdio1_int().bits()))
+            .field("sdio1_int", &self.sdio1_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPUSDIO_INT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO32 ~ 53 CPU SDIO interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpusdio_int1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPUSDIO_INT1_SPEC;
 impl crate::RegisterSpec for CPUSDIO_INT1_SPEC {
diff --git a/esp32s2/src/gpio/enable.rs b/esp32s2/src/gpio/enable.rs
index 312484ebbb..688c028334 100644
--- a/esp32s2/src/gpio/enable.rs
+++ b/esp32s2/src/gpio/enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO0~31 output enable register."]
     #[inline(always)]
diff --git a/esp32s2/src/gpio/enable1.rs b/esp32s2/src/gpio/enable1.rs
index b79328b630..2b0de437ec 100644
--- a/esp32s2/src/gpio/enable1.rs
+++ b/esp32s2/src/gpio/enable1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE1")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - GPIO32~53 output enable register."]
     #[inline(always)]
diff --git a/esp32s2/src/gpio/func_in_sel_cfg.rs b/esp32s2/src/gpio/func_in_sel_cfg.rs
index 270e5e501d..71c6273c9f 100644
--- a/esp32s2/src/gpio/func_in_sel_cfg.rs
+++ b/esp32s2/src/gpio/func_in_sel_cfg.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_IN_SEL_CFG")
-            .field("in_sel", &format_args!("{}", self.in_sel().bits()))
-            .field("in_inv_sel", &format_args!("{}", self.in_inv_sel().bit()))
-            .field("sel", &format_args!("{}", self.sel().bit()))
+            .field("in_sel", &self.in_sel())
+            .field("in_inv_sel", &self.in_inv_sel())
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Selection control for peripheral input signal m, selects a pad from the 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a constantly high input or 0x3C for a constantly low input."]
     #[inline(always)]
diff --git a/esp32s2/src/gpio/func_out_sel_cfg.rs b/esp32s2/src/gpio/func_out_sel_cfg.rs
index ad1240f41e..e1ce34cf5d 100644
--- a/esp32s2/src/gpio/func_out_sel_cfg.rs
+++ b/esp32s2/src/gpio/func_out_sel_cfg.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_OUT_SEL_CFG")
-            .field("out_sel", &format_args!("{}", self.out_sel().bits()))
-            .field("inv_sel", &format_args!("{}", self.inv_sel().bit()))
-            .field("oen_sel", &format_args!("{}", self.oen_sel().bit()))
-            .field("oen_inv_sel", &format_args!("{}", self.oen_inv_sel().bit()))
+            .field("out_sel", &self.out_sel())
+            .field("inv_sel", &self.inv_sel())
+            .field("oen_sel", &self.oen_sel())
+            .field("oen_inv_sel", &self.oen_inv_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - Selection control for GPIO output n. If a value s (0&lt;=s&lt;256) is written to this field, the peripheral output signal s will be connected to GPIO output n. If a value 256 is written to this field, bit n of GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be selected as the output value and output enable."]
     #[inline(always)]
diff --git a/esp32s2/src/gpio/in1.rs b/esp32s2/src/gpio/in1.rs
index 3339d9b24c..faff47940d 100644
--- a/esp32s2/src/gpio/in1.rs
+++ b/esp32s2/src/gpio/in1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN1")
-            .field(
-                "in_data1_next",
-                &format_args!("{}", self.in_data1_next().bits()),
-            )
+            .field("in_data1_next", &self.in_data1_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO32 ~ 53 input register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN1_SPEC;
 impl crate::RegisterSpec for IN1_SPEC {
diff --git a/esp32s2/src/gpio/in_.rs b/esp32s2/src/gpio/in_.rs
index 2981d22d7d..91216e8b95 100644
--- a/esp32s2/src/gpio/in_.rs
+++ b/esp32s2/src/gpio/in_.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN")
-            .field("data_next", &format_args!("{}", self.data_next().bits()))
+            .field("data_next", &self.data_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO0 ~ 31 input value. Each bit represents a pad input value, 1 for high level and 0 for low level."]
     #[inline(always)]
diff --git a/esp32s2/src/gpio/out.rs b/esp32s2/src/gpio/out.rs
index 3f2d181414..f461c615da 100644
--- a/esp32s2/src/gpio/out.rs
+++ b/esp32s2/src/gpio/out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT")
-            .field("data_orig", &format_args!("{}", self.data_orig().bits()))
+            .field("data_orig", &self.data_orig())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO0 ~ 31 output value in simple GPIO output mode. The values of bit0 ~ bit31 correspond to the output value of GPIO0 ~ GPIO31 respectively. Bit22 ~ bit25 are invalid."]
     #[inline(always)]
diff --git a/esp32s2/src/gpio/out1.rs b/esp32s2/src/gpio/out1.rs
index 9390236e11..48f4a46b78 100644
--- a/esp32s2/src/gpio/out1.rs
+++ b/esp32s2/src/gpio/out1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT1")
-            .field("data_orig", &format_args!("{}", self.data_orig().bits()))
+            .field("data_orig", &self.data_orig())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - GPIO32 ~ 53 output value in simple GPIO output mode. The values of bit0 ~ bit13 correspond to GPIO32 ~ GPIO45. Bit14 ~ bit21 are invalid."]
     #[inline(always)]
diff --git a/esp32s2/src/gpio/pcpu_int.rs b/esp32s2/src/gpio/pcpu_int.rs
index 232c0a94b1..63385b8a78 100644
--- a/esp32s2/src/gpio/pcpu_int.rs
+++ b/esp32s2/src/gpio/pcpu_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_INT")
-            .field("procpu_int", &format_args!("{}", self.procpu_int().bits()))
+            .field("procpu_int", &self.procpu_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO0 ~ 31 PRO_CPU interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_INT_SPEC;
 impl crate::RegisterSpec for PCPU_INT_SPEC {
diff --git a/esp32s2/src/gpio/pcpu_int1.rs b/esp32s2/src/gpio/pcpu_int1.rs
index 1c83067db1..196dd0e55a 100644
--- a/esp32s2/src/gpio/pcpu_int1.rs
+++ b/esp32s2/src/gpio/pcpu_int1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_INT1")
-            .field(
-                "procpu1_int",
-                &format_args!("{}", self.procpu1_int().bits()),
-            )
+            .field("procpu1_int", &self.procpu1_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_INT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO32 ~ 53 PRO_CPU interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_int1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_INT1_SPEC;
 impl crate::RegisterSpec for PCPU_INT1_SPEC {
diff --git a/esp32s2/src/gpio/pcpu_nmi_int.rs b/esp32s2/src/gpio/pcpu_nmi_int.rs
index ff7a47ad97..04d531a5bb 100644
--- a/esp32s2/src/gpio/pcpu_nmi_int.rs
+++ b/esp32s2/src/gpio/pcpu_nmi_int.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_NMI_INT")
-            .field(
-                "procpu_nmi_int",
-                &format_args!("{}", self.procpu_nmi_int().bits()),
-            )
+            .field("procpu_nmi_int", &self.procpu_nmi_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_NMI_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO0 ~ 31 PRO_CPU non-maskable interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_nmi_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_NMI_INT_SPEC;
 impl crate::RegisterSpec for PCPU_NMI_INT_SPEC {
diff --git a/esp32s2/src/gpio/pcpu_nmi_int1.rs b/esp32s2/src/gpio/pcpu_nmi_int1.rs
index 4309f3132a..d92223394b 100644
--- a/esp32s2/src/gpio/pcpu_nmi_int1.rs
+++ b/esp32s2/src/gpio/pcpu_nmi_int1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_NMI_INT1")
-            .field(
-                "procpu_nmi1_int",
-                &format_args!("{}", self.procpu_nmi1_int().bits()),
-            )
+            .field("procpu_nmi1_int", &self.procpu_nmi1_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_NMI_INT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO32 ~ 53 PRO_CPU non-maskable interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_nmi_int1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_NMI_INT1_SPEC;
 impl crate::RegisterSpec for PCPU_NMI_INT1_SPEC {
diff --git a/esp32s2/src/gpio/pin.rs b/esp32s2/src/gpio/pin.rs
index a9c3c6e86b..1e1dd0864d 100644
--- a/esp32s2/src/gpio/pin.rs
+++ b/esp32s2/src/gpio/pin.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN")
-            .field(
-                "sync2_bypass",
-                &format_args!("{}", self.sync2_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field(
-                "sync1_bypass",
-                &format_args!("{}", self.sync1_bypass().bits()),
-            )
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("config", &format_args!("{}", self.config().bits()))
-            .field("int_ena", &format_args!("{}", self.int_ena().bits()))
+            .field("sync2_bypass", &self.sync2_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("sync1_bypass", &self.sync1_bypass())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("config", &self.config())
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - For the second stage synchronization, GPIO input data can be syn- chronized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge."]
     #[inline(always)]
diff --git a/esp32s2/src/gpio/reg_date.rs b/esp32s2/src/gpio/reg_date.rs
index a65877f2dc..96516d7706 100644
--- a/esp32s2/src/gpio/reg_date.rs
+++ b/esp32s2/src/gpio/reg_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
diff --git a/esp32s2/src/gpio/sdio_select.rs b/esp32s2/src/gpio/sdio_select.rs
index 0558a0aa4b..60ecb56b1e 100644
--- a/esp32s2/src/gpio/sdio_select.rs
+++ b/esp32s2/src/gpio/sdio_select.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_SELECT")
-            .field("sdio_sel", &format_args!("{}", self.sdio_sel().bits()))
+            .field("sdio_sel", &self.sdio_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_SELECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Reserved"]
     #[inline(always)]
diff --git a/esp32s2/src/gpio/status.rs b/esp32s2/src/gpio/status.rs
index aaae124b7f..2f712a1b5e 100644
--- a/esp32s2/src/gpio/status.rs
+++ b/esp32s2/src/gpio/status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("interrupt", &format_args!("{}", self.interrupt().bits()))
+            .field("interrupt", &self.interrupt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO0 ~ 31 interrupt status register."]
     #[inline(always)]
diff --git a/esp32s2/src/gpio/status1.rs b/esp32s2/src/gpio/status1.rs
index 96f610aa2d..de43f7ba5a 100644
--- a/esp32s2/src/gpio/status1.rs
+++ b/esp32s2/src/gpio/status1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS1")
-            .field("interrupt", &format_args!("{}", self.interrupt().bits()))
+            .field("interrupt", &self.interrupt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - GPIO32 ~ 53 interrupt status register."]
     #[inline(always)]
diff --git a/esp32s2/src/gpio/status_next.rs b/esp32s2/src/gpio/status_next.rs
index 7e96c83360..ebe107dbec 100644
--- a/esp32s2/src/gpio/status_next.rs
+++ b/esp32s2/src/gpio/status_next.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_NEXT")
-            .field(
-                "status_interrupt_next",
-                &format_args!("{}", self.status_interrupt_next().bits()),
-            )
+            .field("status_interrupt_next", &self.status_interrupt_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_NEXT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO0 ~ 31 interrupt source register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_NEXT_SPEC;
 impl crate::RegisterSpec for STATUS_NEXT_SPEC {
diff --git a/esp32s2/src/gpio/status_next1.rs b/esp32s2/src/gpio/status_next1.rs
index 3ab0c90bb7..2fba90f571 100644
--- a/esp32s2/src/gpio/status_next1.rs
+++ b/esp32s2/src/gpio/status_next1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_NEXT1")
-            .field(
-                "status1_interrupt_next",
-                &format_args!("{}", self.status1_interrupt_next().bits()),
-            )
+            .field("status1_interrupt_next", &self.status1_interrupt_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_NEXT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO32 ~ 53 interrupt source register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_NEXT1_SPEC;
 impl crate::RegisterSpec for STATUS_NEXT1_SPEC {
diff --git a/esp32s2/src/gpio/strap.rs b/esp32s2/src/gpio/strap.rs
index 765bb1c2e0..a7e2831bed 100644
--- a/esp32s2/src/gpio/strap.rs
+++ b/esp32s2/src/gpio/strap.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STRAP")
-            .field("strapping", &format_args!("{}", self.strapping().bits()))
+            .field("strapping", &self.strapping())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STRAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Bootstrap pin value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`strap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STRAP_SPEC;
 impl crate::RegisterSpec for STRAP_SPEC {
diff --git a/esp32s2/src/gpio_sd/clock_gate.rs b/esp32s2/src/gpio_sd/clock_gate.rs
index 6117663912..ee0b1f61f2 100644
--- a/esp32s2/src/gpio_sd/clock_gate.rs
+++ b/esp32s2/src/gpio_sd/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Clock enable bit of configuration registers for sigma delta modulation."]
     #[inline(always)]
diff --git a/esp32s2/src/gpio_sd/sigmadelta.rs b/esp32s2/src/gpio_sd/sigmadelta.rs
index e015617bbc..9d6e52c00e 100644
--- a/esp32s2/src/gpio_sd/sigmadelta.rs
+++ b/esp32s2/src/gpio_sd/sigmadelta.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SIGMADELTA")
-            .field("in_", &format_args!("{}", self.in_().bits()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
+            .field("in_", &self.in_())
+            .field("prescale", &self.prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SIGMADELTA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."]
     #[inline(always)]
diff --git a/esp32s2/src/gpio_sd/sigmadelta_misc.rs b/esp32s2/src/gpio_sd/sigmadelta_misc.rs
index 65372e2783..dc3921ff8f 100644
--- a/esp32s2/src/gpio_sd/sigmadelta_misc.rs
+++ b/esp32s2/src/gpio_sd/sigmadelta_misc.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SIGMADELTA_MISC")
-            .field(
-                "function_clk_en",
-                &format_args!("{}", self.function_clk_en().bit()),
-            )
-            .field("spi_swap", &format_args!("{}", self.spi_swap().bit()))
+            .field("function_clk_en", &self.function_clk_en())
+            .field("spi_swap", &self.spi_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SIGMADELTA_MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - Clock enable bit of sigma delta modulation."]
     #[inline(always)]
diff --git a/esp32s2/src/gpio_sd/version.rs b/esp32s2/src/gpio_sd/version.rs
index 31435cfe0a..c5395ac748 100644
--- a/esp32s2/src/gpio_sd/version.rs
+++ b/esp32s2/src/gpio_sd/version.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field(
-                "gpio_sd_date",
-                &format_args!("{}", self.gpio_sd_date().bits()),
-            )
+            .field("gpio_sd_date", &self.gpio_sd_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register."]
     #[inline(always)]
diff --git a/esp32s2/src/hmac/date.rs b/esp32s2/src/hmac/date.rs
index 4a54d835bb..f8c468b3e8 100644
--- a/esp32s2/src/hmac/date.rs
+++ b/esp32s2/src/hmac/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/hmac/query_busy.rs b/esp32s2/src/hmac/query_busy.rs
index 0bc6cb4824..5e904d14e0 100644
--- a/esp32s2/src/hmac/query_busy.rs
+++ b/esp32s2/src/hmac/query_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_BUSY")
-            .field("busy_state", &format_args!("{}", self.busy_state().bit()))
+            .field("busy_state", &self.busy_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The busy state of HMAC module\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_BUSY_SPEC;
 impl crate::RegisterSpec for QUERY_BUSY_SPEC {
diff --git a/esp32s2/src/hmac/query_error.rs b/esp32s2/src/hmac/query_error.rs
index 0e00114bd2..034730e919 100644
--- a/esp32s2/src/hmac/query_error.rs
+++ b/esp32s2/src/hmac/query_error.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_ERROR")
-            .field("query_check", &format_args!("{}", self.query_check().bit()))
+            .field("query_check", &self.query_check())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_ERROR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The matching result between key and purpose user configured\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_error::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_ERROR_SPEC;
 impl crate::RegisterSpec for QUERY_ERROR_SPEC {
diff --git a/esp32s2/src/hmac/rd_result_.rs b/esp32s2/src/hmac/rd_result_.rs
index 96fb116a07..708bceebd1 100644
--- a/esp32s2/src/hmac/rd_result_.rs
+++ b/esp32s2/src/hmac/rd_result_.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_RESULT_")
-            .field("rdata", &format_args!("{}", self.rdata().bits()))
+            .field("rdata", &self.rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RESULT__SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Hash result register %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_result_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RESULT__SPEC;
 impl crate::RegisterSpec for RD_RESULT__SPEC {
diff --git a/esp32s2/src/i2c0/comd.rs b/esp32s2/src/i2c0/comd.rs
index be4ee668f2..eed444d68e 100644
--- a/esp32s2/src/i2c0/comd.rs
+++ b/esp32s2/src/i2c0/comd.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMD")
-            .field("command", &format_args!("{}", self.command().bits()))
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This is the content of command 0. It consists of three parts: op_code is the command, 0: RSTART. 1: WRITE. 2: READ. 3: STOP. 4: END. byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/ctr.rs b/esp32s2/src/i2c0/ctr.rs
index d368aea416..3883cb42e9 100644
--- a/esp32s2/src/i2c0/ctr.rs
+++ b/esp32s2/src/i2c0/ctr.rs
@@ -116,51 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTR")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field(
-                "sample_scl_level",
-                &format_args!("{}", self.sample_scl_level().bit()),
-            )
-            .field(
-                "rx_full_ack_level",
-                &format_args!("{}", self.rx_full_ack_level().bit()),
-            )
-            .field("ms_mode", &format_args!("{}", self.ms_mode().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "arbitration_en",
-                &format_args!("{}", self.arbitration_en().bit()),
-            )
-            .field("fsm_rst", &format_args!("{}", self.fsm_rst().bit()))
-            .field(
-                "ref_always_on",
-                &format_args!("{}", self.ref_always_on().bit()),
-            )
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("sample_scl_level", &self.sample_scl_level())
+            .field("rx_full_ack_level", &self.rx_full_ack_level())
+            .field("ms_mode", &self.ms_mode())
+            .field("trans_start", &self.trans_start())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("clk_en", &self.clk_en())
+            .field("arbitration_en", &self.arbitration_en())
+            .field("fsm_rst", &self.fsm_rst())
+            .field("ref_always_on", &self.ref_always_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 0: direct output. 1: open drain output."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/data.rs b/esp32s2/src/i2c0/data.rs
index 5a8a754040..a67ae50f31 100644
--- a/esp32s2/src/i2c0/data.rs
+++ b/esp32s2/src/i2c0/data.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field("fifo_rdata", &format_args!("{}", self.fifo_rdata().bits()))
+            .field("fifo_rdata", &self.fifo_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value of RX FIFO read data."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/date.rs b/esp32s2/src/i2c0/date.rs
index 9357e9a0fd..252e3205bc 100644
--- a/esp32s2/src/i2c0/date.rs
+++ b/esp32s2/src/i2c0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/i2c0/fifo_conf.rs b/esp32s2/src/i2c0/fifo_conf.rs
index fb56674ee0..9e2bd8fa4c 100644
--- a/esp32s2/src/i2c0/fifo_conf.rs
+++ b/esp32s2/src/i2c0/fifo_conf.rs
@@ -89,39 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CONF")
-            .field(
-                "rxfifo_wm_thrhd",
-                &format_args!("{}", self.rxfifo_wm_thrhd().bits()),
-            )
-            .field(
-                "txfifo_wm_thrhd",
-                &format_args!("{}", self.txfifo_wm_thrhd().bits()),
-            )
-            .field("nonfifo_en", &format_args!("{}", self.nonfifo_en().bit()))
-            .field(
-                "fifo_addr_cfg_en",
-                &format_args!("{}", self.fifo_addr_cfg_en().bit()),
-            )
-            .field("rx_fifo_rst", &format_args!("{}", self.rx_fifo_rst().bit()))
-            .field("tx_fifo_rst", &format_args!("{}", self.tx_fifo_rst().bit()))
-            .field(
-                "nonfifo_rx_thres",
-                &format_args!("{}", self.nonfifo_rx_thres().bits()),
-            )
-            .field(
-                "nonfifo_tx_thres",
-                &format_args!("{}", self.nonfifo_tx_thres().bits()),
-            )
-            .field("fifo_prt_en", &format_args!("{}", self.fifo_prt_en().bit()))
+            .field("rxfifo_wm_thrhd", &self.rxfifo_wm_thrhd())
+            .field("txfifo_wm_thrhd", &self.txfifo_wm_thrhd())
+            .field("nonfifo_en", &self.nonfifo_en())
+            .field("fifo_addr_cfg_en", &self.fifo_addr_cfg_en())
+            .field("rx_fifo_rst", &self.rx_fifo_rst())
+            .field("tx_fifo_rst", &self.tx_fifo_rst())
+            .field("nonfifo_rx_thres", &self.nonfifo_rx_thres())
+            .field("nonfifo_tx_thres", &self.nonfifo_tx_thres())
+            .field("fifo_prt_en", &self.fifo_prt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The water mark threshold of RX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD\\[4:0\\], I2C_RXFIFO_WM_INT_RAW bit will be valid."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/fifo_st.rs b/esp32s2/src/i2c0/fifo_st.rs
index 7ad1048798..74036e636f 100644
--- a/esp32s2/src/i2c0/fifo_st.rs
+++ b/esp32s2/src/i2c0/fifo_st.rs
@@ -47,35 +47,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_ST")
-            .field(
-                "rxfifo_start_addr",
-                &format_args!("{}", self.rxfifo_start_addr().bits()),
-            )
-            .field(
-                "rxfifo_end_addr",
-                &format_args!("{}", self.rxfifo_end_addr().bits()),
-            )
-            .field(
-                "txfifo_start_addr",
-                &format_args!("{}", self.txfifo_start_addr().bits()),
-            )
-            .field(
-                "txfifo_end_addr",
-                &format_args!("{}", self.txfifo_end_addr().bits()),
-            )
-            .field(
-                "slave_rw_point",
-                &format_args!("{}", self.slave_rw_point().bits()),
-            )
+            .field("rxfifo_start_addr", &self.rxfifo_start_addr())
+            .field("rxfifo_end_addr", &self.rxfifo_end_addr())
+            .field("txfifo_start_addr", &self.txfifo_start_addr())
+            .field("txfifo_end_addr", &self.txfifo_end_addr())
+            .field("slave_rw_point", &self.slave_rw_point())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - Write 0 or 1 to I2C_RX_UPDATE to update the value of I2C_RXFIFO_END_ADDR and I2C_RXFIFO_START_ADDR."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/int_ena.rs b/esp32s2/src/i2c0/int_ena.rs
index 7cc52f4744..ec523e1ebf 100644
--- a/esp32s2/src/i2c0/int_ena.rs
+++ b/esp32s2/src/i2c0/int_ena.rs
@@ -161,50 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/int_raw.rs b/esp32s2/src/i2c0/int_raw.rs
index 585cdb26c7..925a31d516 100644
--- a/esp32s2/src/i2c0/int_raw.rs
+++ b/esp32s2/src/i2c0/int_raw.rs
@@ -125,50 +125,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s2/src/i2c0/int_st.rs b/esp32s2/src/i2c0/int_st.rs
index 2d3563a431..622506f0af 100644
--- a/esp32s2/src/i2c0/int_st.rs
+++ b/esp32s2/src/i2c0/int_st.rs
@@ -125,50 +125,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of captured I2C communication events\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s2/src/i2c0/scl_filter_cfg.rs b/esp32s2/src/i2c0/scl_filter_cfg.rs
index 55da12f5e9..49fff11e2b 100644
--- a/esp32s2/src/i2c0/scl_filter_cfg.rs
+++ b/esp32s2/src/i2c0/scl_filter_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_FILTER_CFG")
-            .field(
-                "scl_filter_thres",
-                &format_args!("{}", self.scl_filter_thres().bits()),
-            )
-            .field(
-                "scl_filter_en",
-                &format_args!("{}", self.scl_filter_en().bit()),
-            )
+            .field("scl_filter_thres", &self.scl_filter_thres())
+            .field("scl_filter_en", &self.scl_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_FILTER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/scl_high_period.rs b/esp32s2/src/i2c0/scl_high_period.rs
index 0b6dfe22c5..2ce69e2349 100644
--- a/esp32s2/src/i2c0/scl_high_period.rs
+++ b/esp32s2/src/i2c0/scl_high_period.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH_PERIOD")
-            .field(
-                "scl_high_period",
-                &format_args!("{}", self.scl_high_period().bits()),
-            )
-            .field(
-                "scl_wait_high_period",
-                &format_args!("{}", self.scl_wait_high_period().bits()),
-            )
+            .field("scl_high_period", &self.scl_high_period())
+            .field("scl_wait_high_period", &self.scl_wait_high_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/scl_low_period.rs b/esp32s2/src/i2c0/scl_low_period.rs
index 33b7f777c6..f4b45d03fb 100644
--- a/esp32s2/src/i2c0/scl_low_period.rs
+++ b/esp32s2/src/i2c0/scl_low_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW_PERIOD")
-            .field(
-                "scl_low_period",
-                &format_args!("{}", self.scl_low_period().bits()),
-            )
+            .field("scl_low_period", &self.scl_low_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/scl_main_st_time_out.rs b/esp32s2/src/i2c0/scl_main_st_time_out.rs
index 922fdaa4f9..c7397df9ea 100644
--- a/esp32s2/src/i2c0/scl_main_st_time_out.rs
+++ b/esp32s2/src/i2c0/scl_main_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_MAIN_ST_TIME_OUT")
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bits()),
-            )
+            .field("scl_main_st_to", &self.scl_main_st_to())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_MAIN_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - The threshold value of SCL_MAIN_FSM state unchanged period."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/scl_rstart_setup.rs b/esp32s2/src/i2c0/scl_rstart_setup.rs
index b23c7cddc7..ead077c87c 100644
--- a/esp32s2/src/i2c0/scl_rstart_setup.rs
+++ b/esp32s2/src/i2c0/scl_rstart_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_RSTART_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_RSTART_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the interval between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/scl_sp_conf.rs b/esp32s2/src/i2c0/scl_sp_conf.rs
index 401dbadf96..97858dc9b9 100644
--- a/esp32s2/src/i2c0/scl_sp_conf.rs
+++ b/esp32s2/src/i2c0/scl_sp_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_SP_CONF")
-            .field(
-                "scl_rst_slv_en",
-                &format_args!("{}", self.scl_rst_slv_en().bit()),
-            )
-            .field(
-                "scl_rst_slv_num",
-                &format_args!("{}", self.scl_rst_slv_num().bits()),
-            )
-            .field("scl_pd_en", &format_args!("{}", self.scl_pd_en().bit()))
-            .field("sda_pd_en", &format_args!("{}", self.sda_pd_en().bit()))
+            .field("scl_rst_slv_en", &self.scl_rst_slv_en())
+            .field("scl_rst_slv_num", &self.scl_rst_slv_num())
+            .field("scl_pd_en", &self.scl_pd_en())
+            .field("sda_pd_en", &self.sda_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_SP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to I2C_SCL_RST_SLV_NUM\\[4:0\\]."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/scl_st_time_out.rs b/esp32s2/src/i2c0/scl_st_time_out.rs
index 1a4652c9b4..8622b9f6eb 100644
--- a/esp32s2/src/i2c0/scl_st_time_out.rs
+++ b/esp32s2/src/i2c0/scl_st_time_out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_ST_TIME_OUT")
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bits()))
+            .field("scl_st_to", &self.scl_st_to())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - The threshold value of SCL_FSM state unchanged period."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/scl_start_hold.rs b/esp32s2/src/i2c0/scl_start_hold.rs
index f16b85f0f7..60976eccad 100644
--- a/esp32s2/src/i2c0/scl_start_hold.rs
+++ b/esp32s2/src/i2c0/scl_start_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure interval between pulling SDA low and pulling SCL low when the master generates a START condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/scl_stop_hold.rs b/esp32s2/src/i2c0/scl_stop_hold.rs
index 8658172ef9..1470679d2a 100644
--- a/esp32s2/src/i2c0/scl_stop_hold.rs
+++ b/esp32s2/src/i2c0/scl_stop_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This register is used to configure the delay after the STOP condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/scl_stop_setup.rs b/esp32s2/src/i2c0/scl_stop_setup.rs
index e139a6a113..87c1acb634 100644
--- a/esp32s2/src/i2c0/scl_stop_setup.rs
+++ b/esp32s2/src/i2c0/scl_stop_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/scl_stretch_conf.rs b/esp32s2/src/i2c0/scl_stretch_conf.rs
index 15b2665c50..3fabf23da4 100644
--- a/esp32s2/src/i2c0/scl_stretch_conf.rs
+++ b/esp32s2/src/i2c0/scl_stretch_conf.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STRETCH_CONF")
-            .field(
-                "stretch_protect_num",
-                &format_args!("{}", self.stretch_protect_num().bits()),
-            )
-            .field(
-                "slave_scl_stretch_en",
-                &format_args!("{}", self.slave_scl_stretch_en().bit()),
-            )
+            .field("stretch_protect_num", &self.stretch_protect_num())
+            .field("slave_scl_stretch_en", &self.slave_scl_stretch_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STRETCH_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - Configure the period of I2C slave stretching SCL line."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/sda_filter_cfg.rs b/esp32s2/src/i2c0/sda_filter_cfg.rs
index 6638a4a261..e5386a9359 100644
--- a/esp32s2/src/i2c0/sda_filter_cfg.rs
+++ b/esp32s2/src/i2c0/sda_filter_cfg.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_FILTER_CFG")
-            .field(
-                "sda_filter_thres",
-                &format_args!("{}", self.sda_filter_thres().bits()),
-            )
-            .field(
-                "sda_filter_en",
-                &format_args!("{}", self.sda_filter_en().bit()),
-            )
+            .field("sda_filter_thres", &self.sda_filter_thres())
+            .field("sda_filter_en", &self.sda_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_FILTER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - When a pulse on the SDA input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/sda_hold.rs b/esp32s2/src/i2c0/sda_hold.rs
index ab0f108ce4..b75bb5ede1 100644
--- a/esp32s2/src/i2c0/sda_hold.rs
+++ b/esp32s2/src/i2c0/sda_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the interval between changing the SDA output level and the falling edge of SCL, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/sda_sample.rs b/esp32s2/src/i2c0/sda_sample.rs
index ea06439832..978e955b85 100644
--- a/esp32s2/src/i2c0/sda_sample.rs
+++ b/esp32s2/src/i2c0/sda_sample.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_SAMPLE")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the interval between the rising edge of SCL and the level sampling time of SDA, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/slave_addr.rs b/esp32s2/src/i2c0/slave_addr.rs
index 004dabd9bb..04cdd14f36 100644
--- a/esp32s2/src/i2c0/slave_addr.rs
+++ b/esp32s2/src/i2c0/slave_addr.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE_ADDR")
-            .field("slave_addr", &format_args!("{}", self.slave_addr().bits()))
-            .field(
-                "addr_10bit_en",
-                &format_args!("{}", self.addr_10bit_en().bit()),
-            )
+            .field("slave_addr", &self.slave_addr())
+            .field("addr_10bit_en", &self.addr_10bit_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - When configured as an I2C Slave, this field is used to configure the slave address."]
     #[inline(always)]
diff --git a/esp32s2/src/i2c0/sr.rs b/esp32s2/src/i2c0/sr.rs
index fb151fff21..697a28d87d 100644
--- a/esp32s2/src/i2c0/sr.rs
+++ b/esp32s2/src/i2c0/sr.rs
@@ -90,39 +90,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR")
-            .field("resp_rec", &format_args!("{}", self.resp_rec().bit()))
-            .field("slave_rw", &format_args!("{}", self.slave_rw().bit()))
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field(
-                "slave_addressed",
-                &format_args!("{}", self.slave_addressed().bit()),
-            )
-            .field("byte_trans", &format_args!("{}", self.byte_trans().bit()))
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field(
-                "stretch_cause",
-                &format_args!("{}", self.stretch_cause().bits()),
-            )
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field(
-                "scl_main_state_last",
-                &format_args!("{}", self.scl_main_state_last().bits()),
-            )
-            .field(
-                "scl_state_last",
-                &format_args!("{}", self.scl_state_last().bits()),
-            )
+            .field("resp_rec", &self.resp_rec())
+            .field("slave_rw", &self.slave_rw())
+            .field("time_out", &self.time_out())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("slave_addressed", &self.slave_addressed())
+            .field("byte_trans", &self.byte_trans())
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("stretch_cause", &self.stretch_cause())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("scl_main_state_last", &self.scl_main_state_last())
+            .field("scl_state_last", &self.scl_state_last())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Describe I2C work status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SR_SPEC;
 impl crate::RegisterSpec for SR_SPEC {
diff --git a/esp32s2/src/i2c0/to.rs b/esp32s2/src/i2c0/to.rs
index 40d4773275..eef82ab9da 100644
--- a/esp32s2/src/i2c0/to.rs
+++ b/esp32s2/src/i2c0/to.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO")
-            .field(
-                "time_out_value",
-                &format_args!("{}", self.time_out_value().bits()),
-            )
-            .field("time_out_en", &format_args!("{}", self.time_out_en().bit()))
+            .field("time_out_value", &self.time_out_value())
+            .field("time_out_en", &self.time_out_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - This register is used to configure the timeout for receiving a data bit in APB clock cycles."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/clkm_conf.rs b/esp32s2/src/i2s0/clkm_conf.rs
index f08020f3b9..d876d98d6f 100644
--- a/esp32s2/src/i2s0/clkm_conf.rs
+++ b/esp32s2/src/i2s0/clkm_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKM_CONF")
-            .field(
-                "clkm_div_num",
-                &format_args!("{}", self.clkm_div_num().bits()),
-            )
-            .field("clkm_div_b", &format_args!("{}", self.clkm_div_b().bits()))
-            .field("clkm_div_a", &format_args!("{}", self.clkm_div_a().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bits()))
+            .field("clkm_div_num", &self.clkm_div_num())
+            .field("clkm_div_b", &self.clkm_div_b())
+            .field("clkm_div_a", &self.clkm_div_a())
+            .field("clk_en", &self.clk_en())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral I2S clock divider value."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/conf.rs b/esp32s2/src/i2s0/conf.rs
index b2d6dbdb65..3b36f2f0ac 100644
--- a/esp32s2/src/i2s0/conf.rs
+++ b/esp32s2/src/i2s0/conf.rs
@@ -242,98 +242,35 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field(
-                "tx_slave_mod",
-                &format_args!("{}", self.tx_slave_mod().bit()),
-            )
-            .field(
-                "rx_slave_mod",
-                &format_args!("{}", self.rx_slave_mod().bit()),
-            )
-            .field(
-                "tx_right_first",
-                &format_args!("{}", self.tx_right_first().bit()),
-            )
-            .field(
-                "rx_right_first",
-                &format_args!("{}", self.rx_right_first().bit()),
-            )
-            .field(
-                "tx_msb_shift",
-                &format_args!("{}", self.tx_msb_shift().bit()),
-            )
-            .field(
-                "rx_msb_shift",
-                &format_args!("{}", self.rx_msb_shift().bit()),
-            )
-            .field(
-                "tx_short_sync",
-                &format_args!("{}", self.tx_short_sync().bit()),
-            )
-            .field(
-                "rx_short_sync",
-                &format_args!("{}", self.rx_short_sync().bit()),
-            )
-            .field("tx_mono", &format_args!("{}", self.tx_mono().bit()))
-            .field("rx_mono", &format_args!("{}", self.rx_mono().bit()))
-            .field(
-                "tx_msb_right",
-                &format_args!("{}", self.tx_msb_right().bit()),
-            )
-            .field(
-                "rx_msb_right",
-                &format_args!("{}", self.rx_msb_right().bit()),
-            )
-            .field(
-                "tx_lsb_first_dma",
-                &format_args!("{}", self.tx_lsb_first_dma().bit()),
-            )
-            .field(
-                "rx_lsb_first_dma",
-                &format_args!("{}", self.rx_lsb_first_dma().bit()),
-            )
-            .field(
-                "sig_loopback",
-                &format_args!("{}", self.sig_loopback().bit()),
-            )
-            .field(
-                "tx_fifo_reset_st",
-                &format_args!("{}", self.tx_fifo_reset_st().bit()),
-            )
-            .field(
-                "rx_fifo_reset_st",
-                &format_args!("{}", self.rx_fifo_reset_st().bit()),
-            )
-            .field("tx_reset_st", &format_args!("{}", self.tx_reset_st().bit()))
-            .field(
-                "tx_dma_equal",
-                &format_args!("{}", self.tx_dma_equal().bit()),
-            )
-            .field(
-                "rx_dma_equal",
-                &format_args!("{}", self.rx_dma_equal().bit()),
-            )
-            .field("pre_req_en", &format_args!("{}", self.pre_req_en().bit()))
-            .field(
-                "tx_big_endian",
-                &format_args!("{}", self.tx_big_endian().bit()),
-            )
-            .field(
-                "rx_big_endian",
-                &format_args!("{}", self.rx_big_endian().bit()),
-            )
-            .field("rx_reset_st", &format_args!("{}", self.rx_reset_st().bit()))
+            .field("tx_start", &self.tx_start())
+            .field("rx_start", &self.rx_start())
+            .field("tx_slave_mod", &self.tx_slave_mod())
+            .field("rx_slave_mod", &self.rx_slave_mod())
+            .field("tx_right_first", &self.tx_right_first())
+            .field("rx_right_first", &self.rx_right_first())
+            .field("tx_msb_shift", &self.tx_msb_shift())
+            .field("rx_msb_shift", &self.rx_msb_shift())
+            .field("tx_short_sync", &self.tx_short_sync())
+            .field("rx_short_sync", &self.rx_short_sync())
+            .field("tx_mono", &self.tx_mono())
+            .field("rx_mono", &self.rx_mono())
+            .field("tx_msb_right", &self.tx_msb_right())
+            .field("rx_msb_right", &self.rx_msb_right())
+            .field("tx_lsb_first_dma", &self.tx_lsb_first_dma())
+            .field("rx_lsb_first_dma", &self.rx_lsb_first_dma())
+            .field("sig_loopback", &self.sig_loopback())
+            .field("tx_fifo_reset_st", &self.tx_fifo_reset_st())
+            .field("rx_fifo_reset_st", &self.rx_fifo_reset_st())
+            .field("tx_reset_st", &self.tx_reset_st())
+            .field("tx_dma_equal", &self.tx_dma_equal())
+            .field("rx_dma_equal", &self.rx_dma_equal())
+            .field("pre_req_en", &self.pre_req_en())
+            .field("tx_big_endian", &self.tx_big_endian())
+            .field("rx_big_endian", &self.rx_big_endian())
+            .field("rx_reset_st", &self.rx_reset_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset transmitter."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/conf1.rs b/esp32s2/src/i2s0/conf1.rs
index 7018778b29..ae09a63d47 100644
--- a/esp32s2/src/i2s0/conf1.rs
+++ b/esp32s2/src/i2s0/conf1.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "tx_pcm_conf",
-                &format_args!("{}", self.tx_pcm_conf().bits()),
-            )
-            .field(
-                "tx_pcm_bypass",
-                &format_args!("{}", self.tx_pcm_bypass().bit()),
-            )
-            .field(
-                "rx_pcm_conf",
-                &format_args!("{}", self.rx_pcm_conf().bits()),
-            )
-            .field(
-                "rx_pcm_bypass",
-                &format_args!("{}", self.rx_pcm_bypass().bit()),
-            )
-            .field("tx_stop_en", &format_args!("{}", self.tx_stop_en().bit()))
-            .field(
-                "tx_zeros_rm_en",
-                &format_args!("{}", self.tx_zeros_rm_en().bit()),
-            )
+            .field("tx_pcm_conf", &self.tx_pcm_conf())
+            .field("tx_pcm_bypass", &self.tx_pcm_bypass())
+            .field("rx_pcm_conf", &self.rx_pcm_conf())
+            .field("rx_pcm_bypass", &self.rx_pcm_bypass())
+            .field("tx_stop_en", &self.tx_stop_en())
+            .field("tx_zeros_rm_en", &self.tx_zeros_rm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Compress/Decompress module configuration bits. 0: decompress transmitted data 1:compress transmitted data"]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/conf2.rs b/esp32s2/src/i2s0/conf2.rs
index 88d9aca254..0d03cd02b1 100644
--- a/esp32s2/src/i2s0/conf2.rs
+++ b/esp32s2/src/i2s0/conf2.rs
@@ -116,54 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF2")
-            .field("camera_en", &format_args!("{}", self.camera_en().bit()))
-            .field(
-                "lcd_tx_wrx2_en",
-                &format_args!("{}", self.lcd_tx_wrx2_en().bit()),
-            )
-            .field(
-                "lcd_tx_sdx2_en",
-                &format_args!("{}", self.lcd_tx_sdx2_en().bit()),
-            )
-            .field(
-                "data_enable_test_en",
-                &format_args!("{}", self.data_enable_test_en().bit()),
-            )
-            .field("data_enable", &format_args!("{}", self.data_enable().bit()))
-            .field("lcd_en", &format_args!("{}", self.lcd_en().bit()))
-            .field(
-                "ext_adc_start_en",
-                &format_args!("{}", self.ext_adc_start_en().bit()),
-            )
-            .field(
-                "inter_valid_en",
-                &format_args!("{}", self.inter_valid_en().bit()),
-            )
-            .field(
-                "cam_sync_fifo_reset",
-                &format_args!("{}", self.cam_sync_fifo_reset().bit()),
-            )
-            .field(
-                "cam_clk_loopback",
-                &format_args!("{}", self.cam_clk_loopback().bit()),
-            )
-            .field(
-                "vsync_filter_en",
-                &format_args!("{}", self.vsync_filter_en().bit()),
-            )
-            .field(
-                "vsync_filter_thres",
-                &format_args!("{}", self.vsync_filter_thres().bits()),
-            )
+            .field("camera_en", &self.camera_en())
+            .field("lcd_tx_wrx2_en", &self.lcd_tx_wrx2_en())
+            .field("lcd_tx_sdx2_en", &self.lcd_tx_sdx2_en())
+            .field("data_enable_test_en", &self.data_enable_test_en())
+            .field("data_enable", &self.data_enable())
+            .field("lcd_en", &self.lcd_en())
+            .field("ext_adc_start_en", &self.ext_adc_start_en())
+            .field("inter_valid_en", &self.inter_valid_en())
+            .field("cam_sync_fifo_reset", &self.cam_sync_fifo_reset())
+            .field("cam_clk_loopback", &self.cam_clk_loopback())
+            .field("vsync_filter_en", &self.vsync_filter_en())
+            .field("vsync_filter_thres", &self.vsync_filter_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable camera mode."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/conf_chan.rs b/esp32s2/src/i2s0/conf_chan.rs
index 7f2e5e580e..66e3b440a0 100644
--- a/esp32s2/src/i2s0/conf_chan.rs
+++ b/esp32s2/src/i2s0/conf_chan.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_CHAN")
-            .field(
-                "tx_chan_mod",
-                &format_args!("{}", self.tx_chan_mod().bits()),
-            )
-            .field(
-                "rx_chan_mod",
-                &format_args!("{}", self.rx_chan_mod().bits()),
-            )
+            .field("tx_chan_mod", &self.tx_chan_mod())
+            .field("rx_chan_mod", &self.rx_chan_mod())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_CHAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - I2S transmitter channel mode configuration bits."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/conf_sigle_data.rs b/esp32s2/src/i2s0/conf_sigle_data.rs
index caf3c47517..7226cb57b9 100644
--- a/esp32s2/src/i2s0/conf_sigle_data.rs
+++ b/esp32s2/src/i2s0/conf_sigle_data.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_SIGLE_DATA")
-            .field("sigle_data", &format_args!("{}", self.sigle_data().bits()))
+            .field("sigle_data", &self.sigle_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SIGLE_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The right channel or left channel transmits constant value stored in this register according to I2S_TX_CHAN_MOD and I2S_TX_MSB_RIGHT."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/date.rs b/esp32s2/src/i2s0/date.rs
index 553d9dc732..0826c874e3 100644
--- a/esp32s2/src/i2s0/date.rs
+++ b/esp32s2/src/i2s0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/i2s0/fifo_conf.rs b/esp32s2/src/i2s0/fifo_conf.rs
index 4a71e2ab38..ae3226b524 100644
--- a/esp32s2/src/i2s0/fifo_conf.rs
+++ b/esp32s2/src/i2s0/fifo_conf.rs
@@ -98,46 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CONF")
-            .field(
-                "rx_data_num",
-                &format_args!("{}", self.rx_data_num().bits()),
-            )
-            .field(
-                "tx_data_num",
-                &format_args!("{}", self.tx_data_num().bits()),
-            )
-            .field("dscr_en", &format_args!("{}", self.dscr_en().bit()))
-            .field(
-                "tx_fifo_mod",
-                &format_args!("{}", self.tx_fifo_mod().bits()),
-            )
-            .field(
-                "rx_fifo_mod",
-                &format_args!("{}", self.rx_fifo_mod().bits()),
-            )
-            .field(
-                "tx_fifo_mod_force_en",
-                &format_args!("{}", self.tx_fifo_mod_force_en().bit()),
-            )
-            .field(
-                "rx_fifo_mod_force_en",
-                &format_args!("{}", self.rx_fifo_mod_force_en().bit()),
-            )
-            .field(
-                "rx_fifo_sync",
-                &format_args!("{}", self.rx_fifo_sync().bit()),
-            )
-            .field("rx_24msb_en", &format_args!("{}", self.rx_24msb_en().bit()))
-            .field("tx_24msb_en", &format_args!("{}", self.tx_24msb_en().bit()))
+            .field("rx_data_num", &self.rx_data_num())
+            .field("tx_data_num", &self.tx_data_num())
+            .field("dscr_en", &self.dscr_en())
+            .field("tx_fifo_mod", &self.tx_fifo_mod())
+            .field("rx_fifo_mod", &self.rx_fifo_mod())
+            .field("tx_fifo_mod_force_en", &self.tx_fifo_mod_force_en())
+            .field("rx_fifo_mod_force_en", &self.rx_fifo_mod_force_en())
+            .field("rx_fifo_sync", &self.rx_fifo_sync())
+            .field("rx_24msb_en", &self.rx_24msb_en())
+            .field("tx_24msb_en", &self.tx_24msb_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - I2S_RX_TAKE_DATA_INT is triggered when the left and right channel data number in RX FIFO is larger than the value of I2S_RX_DATA_NUM\\[5:0\\]. (RX FIFO is almost full threshold.)"]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/in_eof_des_addr.rs b/esp32s2/src/i2s0/in_eof_des_addr.rs
index 78b7e41f49..4dedc028a5 100644
--- a/esp32s2/src/i2s0/in_eof_des_addr.rs
+++ b/esp32s2/src/i2s0/in_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EOF_DES_ADDR")
-            .field(
-                "in_suc_eof_des_addr",
-                &format_args!("{}", self.in_suc_eof_des_addr().bits()),
-            )
+            .field("in_suc_eof_des_addr", &self.in_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Address of inlink descriptor that produces EOF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_EOF_DES_ADDR_SPEC {
diff --git a/esp32s2/src/i2s0/in_link.rs b/esp32s2/src/i2s0/in_link.rs
index 168398cd03..91e0eb23f9 100644
--- a/esp32s2/src/i2s0/in_link.rs
+++ b/esp32s2/src/i2s0/in_link.rs
@@ -51,29 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_LINK")
-            .field(
-                "inlink_addr",
-                &format_args!("{}", self.inlink_addr().bits()),
-            )
-            .field("inlink_stop", &format_args!("{}", self.inlink_stop().bit()))
-            .field(
-                "inlink_start",
-                &format_args!("{}", self.inlink_start().bit()),
-            )
-            .field(
-                "inlink_restart",
-                &format_args!("{}", self.inlink_restart().bit()),
-            )
-            .field("inlink_park", &format_args!("{}", self.inlink_park().bit()))
+            .field("inlink_addr", &self.inlink_addr())
+            .field("inlink_stop", &self.inlink_stop())
+            .field("inlink_start", &self.inlink_start())
+            .field("inlink_restart", &self.inlink_restart())
+            .field("inlink_park", &self.inlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - The address of first inlink descriptor."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/infifo_pop.rs b/esp32s2/src/i2s0/infifo_pop.rs
index 2e6dfdbbcd..fdb452c8e3 100644
--- a/esp32s2/src/i2s0/infifo_pop.rs
+++ b/esp32s2/src/i2s0/infifo_pop.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INFIFO_POP")
-            .field(
-                "infifo_rdata",
-                &format_args!("{}", self.infifo_rdata().bits()),
-            )
-            .field("infifo_pop", &format_args!("{}", self.infifo_pop().bit()))
+            .field("infifo_rdata", &self.infifo_rdata())
+            .field("infifo_pop", &self.infifo_pop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INFIFO_POP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16 - APB in FIFO pop."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/inlink_dscr.rs b/esp32s2/src/i2s0/inlink_dscr.rs
index 189c60fe60..77f8d2c703 100644
--- a/esp32s2/src/i2s0/inlink_dscr.rs
+++ b/esp32s2/src/i2s0/inlink_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INLINK_DSCR")
-            .field(
-                "inlink_dscr",
-                &format_args!("{}", self.inlink_dscr().bits()),
-            )
+            .field("inlink_dscr", &self.inlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INLINK_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Address of current inlink descriptor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inlink_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INLINK_DSCR_SPEC;
 impl crate::RegisterSpec for INLINK_DSCR_SPEC {
diff --git a/esp32s2/src/i2s0/inlink_dscr_bf0.rs b/esp32s2/src/i2s0/inlink_dscr_bf0.rs
index ba487a2fe6..789d387009 100644
--- a/esp32s2/src/i2s0/inlink_dscr_bf0.rs
+++ b/esp32s2/src/i2s0/inlink_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INLINK_DSCR_BF0")
-            .field(
-                "inlink_dscr_bf0",
-                &format_args!("{}", self.inlink_dscr_bf0().bits()),
-            )
+            .field("inlink_dscr_bf0", &self.inlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INLINK_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Address of next inlink descriptor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inlink_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INLINK_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for INLINK_DSCR_BF0_SPEC {
diff --git a/esp32s2/src/i2s0/inlink_dscr_bf1.rs b/esp32s2/src/i2s0/inlink_dscr_bf1.rs
index 704f580e28..b92441efa3 100644
--- a/esp32s2/src/i2s0/inlink_dscr_bf1.rs
+++ b/esp32s2/src/i2s0/inlink_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INLINK_DSCR_BF1")
-            .field(
-                "inlink_dscr_bf1",
-                &format_args!("{}", self.inlink_dscr_bf1().bits()),
-            )
+            .field("inlink_dscr_bf1", &self.inlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INLINK_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Address of next inlink data buffer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inlink_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INLINK_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for INLINK_DSCR_BF1_SPEC {
diff --git a/esp32s2/src/i2s0/int_ena.rs b/esp32s2/src/i2s0/int_ena.rs
index c3385fd0ee..cbb782e3c4 100644
--- a/esp32s2/src/i2s0/int_ena.rs
+++ b/esp32s2/src/i2s0/int_ena.rs
@@ -170,45 +170,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "rx_take_data",
-                &format_args!("{}", self.rx_take_data().bit()),
-            )
-            .field("tx_put_data", &format_args!("{}", self.tx_put_data().bit()))
-            .field("rx_wfull", &format_args!("{}", self.rx_wfull().bit()))
-            .field("rx_rempty", &format_args!("{}", self.rx_rempty().bit()))
-            .field("tx_wfull", &format_args!("{}", self.tx_wfull().bit()))
-            .field("tx_rempty", &format_args!("{}", self.tx_rempty().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("v_sync", &format_args!("{}", self.v_sync().bit()))
+            .field("rx_take_data", &self.rx_take_data())
+            .field("tx_put_data", &self.tx_put_data())
+            .field("rx_wfull", &self.rx_wfull())
+            .field("rx_rempty", &self.rx_rempty())
+            .field("tx_wfull", &self.tx_wfull())
+            .field("tx_rempty", &self.tx_rempty())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("v_sync", &self.v_sync())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for I2S_RX_TAKE_DATA_INT interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/int_raw.rs b/esp32s2/src/i2s0/int_raw.rs
index bf19503258..2b7b7d7fbe 100644
--- a/esp32s2/src/i2s0/int_raw.rs
+++ b/esp32s2/src/i2s0/int_raw.rs
@@ -132,45 +132,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "rx_take_data",
-                &format_args!("{}", self.rx_take_data().bit()),
-            )
-            .field("tx_put_data", &format_args!("{}", self.tx_put_data().bit()))
-            .field("rx_wfull", &format_args!("{}", self.rx_wfull().bit()))
-            .field("rx_rempty", &format_args!("{}", self.rx_rempty().bit()))
-            .field("tx_wfull", &format_args!("{}", self.tx_wfull().bit()))
-            .field("tx_rempty", &format_args!("{}", self.tx_rempty().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("v_sync", &format_args!("{}", self.v_sync().bit()))
+            .field("rx_take_data", &self.rx_take_data())
+            .field("tx_put_data", &self.tx_put_data())
+            .field("rx_wfull", &self.rx_wfull())
+            .field("rx_rempty", &self.rx_rempty())
+            .field("tx_wfull", &self.tx_wfull())
+            .field("tx_rempty", &self.tx_rempty())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("v_sync", &self.v_sync())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s2/src/i2s0/int_st.rs b/esp32s2/src/i2s0/int_st.rs
index df611297d0..5822eab1c9 100644
--- a/esp32s2/src/i2s0/int_st.rs
+++ b/esp32s2/src/i2s0/int_st.rs
@@ -132,45 +132,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "rx_take_data",
-                &format_args!("{}", self.rx_take_data().bit()),
-            )
-            .field("tx_put_data", &format_args!("{}", self.tx_put_data().bit()))
-            .field("rx_wfull", &format_args!("{}", self.rx_wfull().bit()))
-            .field("rx_rempty", &format_args!("{}", self.rx_rempty().bit()))
-            .field("tx_wfull", &format_args!("{}", self.tx_wfull().bit()))
-            .field("tx_rempty", &format_args!("{}", self.tx_rempty().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field("v_sync", &format_args!("{}", self.v_sync().bit()))
+            .field("rx_take_data", &self.rx_take_data())
+            .field("tx_put_data", &self.tx_put_data())
+            .field("rx_wfull", &self.rx_wfull())
+            .field("rx_rempty", &self.rx_rempty())
+            .field("tx_wfull", &self.tx_wfull())
+            .field("tx_rempty", &self.tx_rempty())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("v_sync", &self.v_sync())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s2/src/i2s0/lc_conf.rs b/esp32s2/src/i2s0/lc_conf.rs
index db3bb32a29..368f1897be 100644
--- a/esp32s2/src/i2s0/lc_conf.rs
+++ b/esp32s2/src/i2s0/lc_conf.rs
@@ -143,63 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_CONF")
-            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
-            .field("out_rst", &format_args!("{}", self.out_rst().bit()))
-            .field(
-                "ahbm_fifo_rst",
-                &format_args!("{}", self.ahbm_fifo_rst().bit()),
-            )
-            .field("ahbm_rst", &format_args!("{}", self.ahbm_rst().bit()))
-            .field(
-                "out_loop_test",
-                &format_args!("{}", self.out_loop_test().bit()),
-            )
-            .field(
-                "in_loop_test",
-                &format_args!("{}", self.in_loop_test().bit()),
-            )
-            .field(
-                "out_auto_wrback",
-                &format_args!("{}", self.out_auto_wrback().bit()),
-            )
-            .field(
-                "out_no_restart_clr",
-                &format_args!("{}", self.out_no_restart_clr().bit()),
-            )
-            .field(
-                "out_eof_mode",
-                &format_args!("{}", self.out_eof_mode().bit()),
-            )
-            .field(
-                "outdscr_burst_en",
-                &format_args!("{}", self.outdscr_burst_en().bit()),
-            )
-            .field(
-                "indscr_burst_en",
-                &format_args!("{}", self.indscr_burst_en().bit()),
-            )
-            .field(
-                "out_data_burst_en",
-                &format_args!("{}", self.out_data_burst_en().bit()),
-            )
-            .field("check_owner", &format_args!("{}", self.check_owner().bit()))
-            .field(
-                "mem_trans_en",
-                &format_args!("{}", self.mem_trans_en().bit()),
-            )
-            .field(
-                "ext_mem_bk_size",
-                &format_args!("{}", self.ext_mem_bk_size().bits()),
-            )
+            .field("in_rst", &self.in_rst())
+            .field("out_rst", &self.out_rst())
+            .field("ahbm_fifo_rst", &self.ahbm_fifo_rst())
+            .field("ahbm_rst", &self.ahbm_rst())
+            .field("out_loop_test", &self.out_loop_test())
+            .field("in_loop_test", &self.in_loop_test())
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("out_no_restart_clr", &self.out_no_restart_clr())
+            .field("out_eof_mode", &self.out_eof_mode())
+            .field("outdscr_burst_en", &self.outdscr_burst_en())
+            .field("indscr_burst_en", &self.indscr_burst_en())
+            .field("out_data_burst_en", &self.out_data_burst_en())
+            .field("check_owner", &self.check_owner())
+            .field("mem_trans_en", &self.mem_trans_en())
+            .field("ext_mem_bk_size", &self.ext_mem_bk_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset in-DMA FSM. Set this bit before the DMA configuration."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/lc_hung_conf.rs b/esp32s2/src/i2s0/lc_hung_conf.rs
index b56d3b8428..5d94ff0d89 100644
--- a/esp32s2/src/i2s0/lc_hung_conf.rs
+++ b/esp32s2/src/i2s0/lc_hung_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_HUNG_CONF")
-            .field(
-                "lc_fifo_timeout",
-                &format_args!("{}", self.lc_fifo_timeout().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_shift",
-                &format_args!("{}", self.lc_fifo_timeout_shift().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_ena",
-                &format_args!("{}", self.lc_fifo_timeout_ena().bit()),
-            )
+            .field("lc_fifo_timeout", &self.lc_fifo_timeout())
+            .field("lc_fifo_timeout_shift", &self.lc_fifo_timeout_shift())
+            .field("lc_fifo_timeout_ena", &self.lc_fifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - I2S_TX_HUNG_INT interrupt or I2S_RX_HUNG_INT interrupt will be triggered when FIFO hung counter is equal to this value."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/lc_state0.rs b/esp32s2/src/i2s0/lc_state0.rs
index c6224abd40..e112ecb4d7 100644
--- a/esp32s2/src/i2s0/lc_state0.rs
+++ b/esp32s2/src/i2s0/lc_state0.rs
@@ -48,30 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_STATE0")
-            .field(
-                "outlink_dscr_addr",
-                &format_args!("{}", self.outlink_dscr_addr().bits()),
-            )
-            .field(
-                "out_dscr_state",
-                &format_args!("{}", self.out_dscr_state().bits()),
-            )
-            .field("out_state", &format_args!("{}", self.out_state().bits()))
-            .field(
-                "outfifo_cnt",
-                &format_args!("{}", self.outfifo_cnt().bits()),
-            )
-            .field("out_full", &format_args!("{}", self.out_full().bit()))
-            .field("out_empty", &format_args!("{}", self.out_empty().bit()))
+            .field("outlink_dscr_addr", &self.outlink_dscr_addr())
+            .field("out_dscr_state", &self.out_dscr_state())
+            .field("out_state", &self.out_state())
+            .field("outfifo_cnt", &self.outfifo_cnt())
+            .field("out_full", &self.out_full())
+            .field("out_empty", &self.out_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S DMA TX status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_state0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LC_STATE0_SPEC;
 impl crate::RegisterSpec for LC_STATE0_SPEC {
diff --git a/esp32s2/src/i2s0/lc_state1.rs b/esp32s2/src/i2s0/lc_state1.rs
index 33976fe7be..a050c6091d 100644
--- a/esp32s2/src/i2s0/lc_state1.rs
+++ b/esp32s2/src/i2s0/lc_state1.rs
@@ -48,30 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_STATE1")
-            .field(
-                "inlink_dscr_addr",
-                &format_args!("{}", self.inlink_dscr_addr().bits()),
-            )
-            .field(
-                "in_dscr_state",
-                &format_args!("{}", self.in_dscr_state().bits()),
-            )
-            .field("in_state", &format_args!("{}", self.in_state().bits()))
-            .field(
-                "infifo_cnt_debug",
-                &format_args!("{}", self.infifo_cnt_debug().bits()),
-            )
-            .field("in_full", &format_args!("{}", self.in_full().bit()))
-            .field("in_empty", &format_args!("{}", self.in_empty().bit()))
+            .field("inlink_dscr_addr", &self.inlink_dscr_addr())
+            .field("in_dscr_state", &self.in_dscr_state())
+            .field("in_state", &self.in_state())
+            .field("infifo_cnt_debug", &self.infifo_cnt_debug())
+            .field("in_full", &self.in_full())
+            .field("in_empty", &self.in_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_STATE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S DMA RX status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_state1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LC_STATE1_SPEC;
 impl crate::RegisterSpec for LC_STATE1_SPEC {
diff --git a/esp32s2/src/i2s0/out_eof_bfr_des_addr.rs b/esp32s2/src/i2s0/out_eof_bfr_des_addr.rs
index c13dc35944..8757298abf 100644
--- a/esp32s2/src/i2s0/out_eof_bfr_des_addr.rs
+++ b/esp32s2/src/i2s0/out_eof_bfr_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_BFR_DES_ADDR")
-            .field(
-                "out_eof_bfr_des_addr",
-                &format_args!("{}", self.out_eof_bfr_des_addr().bits()),
-            )
+            .field("out_eof_bfr_des_addr", &self.out_eof_bfr_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_BFR_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Address of buffer relative to the outlink descriptor that produces EOF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_bfr_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_BFR_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_SPEC {
diff --git a/esp32s2/src/i2s0/out_eof_des_addr.rs b/esp32s2/src/i2s0/out_eof_des_addr.rs
index 6394e1c7b0..a73984fe80 100644
--- a/esp32s2/src/i2s0/out_eof_des_addr.rs
+++ b/esp32s2/src/i2s0/out_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_DES_ADDR")
-            .field(
-                "out_eof_des_addr",
-                &format_args!("{}", self.out_eof_des_addr().bits()),
-            )
+            .field("out_eof_des_addr", &self.out_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Address of outlink descriptor that produces EOF\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_DES_ADDR_SPEC {
diff --git a/esp32s2/src/i2s0/out_link.rs b/esp32s2/src/i2s0/out_link.rs
index 4f2519f0c0..7921cf3c72 100644
--- a/esp32s2/src/i2s0/out_link.rs
+++ b/esp32s2/src/i2s0/out_link.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_LINK")
-            .field(
-                "outlink_addr",
-                &format_args!("{}", self.outlink_addr().bits()),
-            )
-            .field(
-                "outlink_stop",
-                &format_args!("{}", self.outlink_stop().bit()),
-            )
-            .field(
-                "outlink_start",
-                &format_args!("{}", self.outlink_start().bit()),
-            )
-            .field(
-                "outlink_restart",
-                &format_args!("{}", self.outlink_restart().bit()),
-            )
-            .field(
-                "outlink_park",
-                &format_args!("{}", self.outlink_park().bit()),
-            )
+            .field("outlink_addr", &self.outlink_addr())
+            .field("outlink_stop", &self.outlink_stop())
+            .field("outlink_start", &self.outlink_start())
+            .field("outlink_restart", &self.outlink_restart())
+            .field("outlink_park", &self.outlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - The address of first outlink descriptor."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/outfifo_push.rs b/esp32s2/src/i2s0/outfifo_push.rs
index e4a29c65f6..4df82b443d 100644
--- a/esp32s2/src/i2s0/outfifo_push.rs
+++ b/esp32s2/src/i2s0/outfifo_push.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTFIFO_PUSH")
-            .field(
-                "outfifo_wdata",
-                &format_args!("{}", self.outfifo_wdata().bits()),
-            )
-            .field(
-                "outfifo_push",
-                &format_args!("{}", self.outfifo_push().bit()),
-            )
+            .field("outfifo_wdata", &self.outfifo_wdata())
+            .field("outfifo_push", &self.outfifo_push())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTFIFO_PUSH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - APB out FIFO write data."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/outlink_dscr.rs b/esp32s2/src/i2s0/outlink_dscr.rs
index e77defd925..584d884a43 100644
--- a/esp32s2/src/i2s0/outlink_dscr.rs
+++ b/esp32s2/src/i2s0/outlink_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTLINK_DSCR")
-            .field(
-                "outlink_dscr",
-                &format_args!("{}", self.outlink_dscr().bits()),
-            )
+            .field("outlink_dscr", &self.outlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTLINK_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Address of current outlink descriptor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outlink_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTLINK_DSCR_SPEC;
 impl crate::RegisterSpec for OUTLINK_DSCR_SPEC {
diff --git a/esp32s2/src/i2s0/outlink_dscr_bf0.rs b/esp32s2/src/i2s0/outlink_dscr_bf0.rs
index 988808aa03..36a9e3f71c 100644
--- a/esp32s2/src/i2s0/outlink_dscr_bf0.rs
+++ b/esp32s2/src/i2s0/outlink_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTLINK_DSCR_BF0")
-            .field(
-                "outlink_dscr_bf0",
-                &format_args!("{}", self.outlink_dscr_bf0().bits()),
-            )
+            .field("outlink_dscr_bf0", &self.outlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTLINK_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Address of next outlink descriptor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outlink_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTLINK_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for OUTLINK_DSCR_BF0_SPEC {
diff --git a/esp32s2/src/i2s0/outlink_dscr_bf1.rs b/esp32s2/src/i2s0/outlink_dscr_bf1.rs
index bc6c8b5347..c931745d9f 100644
--- a/esp32s2/src/i2s0/outlink_dscr_bf1.rs
+++ b/esp32s2/src/i2s0/outlink_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTLINK_DSCR_BF1")
-            .field(
-                "outlink_dscr_bf1",
-                &format_args!("{}", self.outlink_dscr_bf1().bits()),
-            )
+            .field("outlink_dscr_bf1", &self.outlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTLINK_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Address of next outlink data buffer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outlink_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTLINK_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for OUTLINK_DSCR_BF1_SPEC {
diff --git a/esp32s2/src/i2s0/pd_conf.rs b/esp32s2/src/i2s0/pd_conf.rs
index f3312fe2ec..9a03f1da5a 100644
--- a/esp32s2/src/i2s0/pd_conf.rs
+++ b/esp32s2/src/i2s0/pd_conf.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PD_CONF")
-            .field(
-                "fifo_force_pd",
-                &format_args!("{}", self.fifo_force_pd().bit()),
-            )
-            .field(
-                "fifo_force_pu",
-                &format_args!("{}", self.fifo_force_pu().bit()),
-            )
-            .field(
-                "plc_mem_force_pd",
-                &format_args!("{}", self.plc_mem_force_pd().bit()),
-            )
-            .field(
-                "plc_mem_force_pu",
-                &format_args!("{}", self.plc_mem_force_pu().bit()),
-            )
-            .field(
-                "dma_ram_force_pd",
-                &format_args!("{}", self.dma_ram_force_pd().bit()),
-            )
-            .field(
-                "dma_ram_force_pu",
-                &format_args!("{}", self.dma_ram_force_pu().bit()),
-            )
-            .field(
-                "dma_ram_clk_fo",
-                &format_args!("{}", self.dma_ram_clk_fo().bit()),
-            )
+            .field("fifo_force_pd", &self.fifo_force_pd())
+            .field("fifo_force_pu", &self.fifo_force_pu())
+            .field("plc_mem_force_pd", &self.plc_mem_force_pd())
+            .field("plc_mem_force_pu", &self.plc_mem_force_pu())
+            .field("dma_ram_force_pd", &self.dma_ram_force_pd())
+            .field("dma_ram_force_pu", &self.dma_ram_force_pu())
+            .field("dma_ram_clk_fo", &self.dma_ram_clk_fo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Force FIFO power-down."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/rxeof_num.rs b/esp32s2/src/i2s0/rxeof_num.rs
index 4c09483572..7dbdefbabb 100644
--- a/esp32s2/src/i2s0/rxeof_num.rs
+++ b/esp32s2/src/i2s0/rxeof_num.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXEOF_NUM")
-            .field("rx_eof_num", &format_args!("{}", self.rx_eof_num().bits()))
+            .field("rx_eof_num", &self.rx_eof_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXEOF_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The length of data to be received. It will trigger I2S_IN_SUC_EOF_INT."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/sample_rate_conf.rs b/esp32s2/src/i2s0/sample_rate_conf.rs
index 54ea767ca3..b8ecf20c47 100644
--- a/esp32s2/src/i2s0/sample_rate_conf.rs
+++ b/esp32s2/src/i2s0/sample_rate_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAMPLE_RATE_CONF")
-            .field(
-                "tx_bck_div_num",
-                &format_args!("{}", self.tx_bck_div_num().bits()),
-            )
-            .field(
-                "rx_bck_div_num",
-                &format_args!("{}", self.rx_bck_div_num().bits()),
-            )
-            .field(
-                "tx_bits_mod",
-                &format_args!("{}", self.tx_bits_mod().bits()),
-            )
-            .field(
-                "rx_bits_mod",
-                &format_args!("{}", self.rx_bits_mod().bits()),
-            )
+            .field("tx_bck_div_num", &self.tx_bck_div_num())
+            .field("rx_bck_div_num", &self.rx_bck_div_num())
+            .field("tx_bits_mod", &self.tx_bits_mod())
+            .field("rx_bits_mod", &self.rx_bits_mod())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAMPLE_RATE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Bit clock configuration bits in transmitter mode."]
     #[inline(always)]
diff --git a/esp32s2/src/i2s0/state.rs b/esp32s2/src/i2s0/state.rs
index c4ab54ebb3..f09a5fde7d 100644
--- a/esp32s2/src/i2s0/state.rs
+++ b/esp32s2/src/i2s0/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("tx_idle", &format_args!("{}", self.tx_idle().bit()))
+            .field("tx_idle", &self.tx_idle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S TX status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32s2/src/i2s0/timing.rs b/esp32s2/src/i2s0/timing.rs
index 8abb88f15b..4411574c06 100644
--- a/esp32s2/src/i2s0/timing.rs
+++ b/esp32s2/src/i2s0/timing.rs
@@ -134,65 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMING")
-            .field(
-                "tx_bck_in_delay",
-                &format_args!("{}", self.tx_bck_in_delay().bits()),
-            )
-            .field(
-                "tx_ws_in_delay",
-                &format_args!("{}", self.tx_ws_in_delay().bits()),
-            )
-            .field(
-                "rx_bck_in_delay",
-                &format_args!("{}", self.rx_bck_in_delay().bits()),
-            )
-            .field(
-                "rx_ws_in_delay",
-                &format_args!("{}", self.rx_ws_in_delay().bits()),
-            )
-            .field(
-                "rx_sd_in_delay",
-                &format_args!("{}", self.rx_sd_in_delay().bits()),
-            )
-            .field(
-                "tx_bck_out_delay",
-                &format_args!("{}", self.tx_bck_out_delay().bits()),
-            )
-            .field(
-                "tx_ws_out_delay",
-                &format_args!("{}", self.tx_ws_out_delay().bits()),
-            )
-            .field(
-                "tx_sd_out_delay",
-                &format_args!("{}", self.tx_sd_out_delay().bits()),
-            )
-            .field(
-                "rx_ws_out_delay",
-                &format_args!("{}", self.rx_ws_out_delay().bits()),
-            )
-            .field(
-                "rx_bck_out_delay",
-                &format_args!("{}", self.rx_bck_out_delay().bits()),
-            )
-            .field("tx_dsync_sw", &format_args!("{}", self.tx_dsync_sw().bit()))
-            .field("rx_dsync_sw", &format_args!("{}", self.rx_dsync_sw().bit()))
-            .field(
-                "data_enable_delay",
-                &format_args!("{}", self.data_enable_delay().bits()),
-            )
-            .field(
-                "tx_bck_in_inv",
-                &format_args!("{}", self.tx_bck_in_inv().bit()),
-            )
+            .field("tx_bck_in_delay", &self.tx_bck_in_delay())
+            .field("tx_ws_in_delay", &self.tx_ws_in_delay())
+            .field("rx_bck_in_delay", &self.rx_bck_in_delay())
+            .field("rx_ws_in_delay", &self.rx_ws_in_delay())
+            .field("rx_sd_in_delay", &self.rx_sd_in_delay())
+            .field("tx_bck_out_delay", &self.tx_bck_out_delay())
+            .field("tx_ws_out_delay", &self.tx_ws_out_delay())
+            .field("tx_sd_out_delay", &self.tx_sd_out_delay())
+            .field("rx_ws_out_delay", &self.rx_ws_out_delay())
+            .field("rx_bck_out_delay", &self.rx_bck_out_delay())
+            .field("tx_dsync_sw", &self.tx_dsync_sw())
+            .field("rx_dsync_sw", &self.rx_dsync_sw())
+            .field("data_enable_delay", &self.data_enable_delay())
+            .field("tx_bck_in_inv", &self.tx_bck_in_inv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Number of delay cycles for BCK signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/clock_gate.rs b/esp32s2/src/interrupt_core0/clock_gate.rs
index 630aa756cb..0db4087e66 100644
--- a/esp32s2/src/interrupt_core0/clock_gate.rs
+++ b/esp32s2/src/interrupt_core0/clock_gate.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "pro_nmi_mask_hw",
-                &format_args!("{}", self.pro_nmi_mask_hw().bit()),
-            )
+            .field("clk_en", &self.clk_en())
+            .field("pro_nmi_mask_hw", &self.pro_nmi_mask_hw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to enable or disable the clock of interrupt matrix. 1: enable the clock. 0: disable the clock."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_aes_intr_map.rs b/esp32s2/src/interrupt_core0/pro_aes_intr_map.rs
index d096868406..4af4e9d1ef 100644
--- a/esp32s2/src/interrupt_core0/pro_aes_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_aes_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_AES_INTR_MAP")
-            .field(
-                "pro_aes_intr_map",
-                &format_args!("{}", self.pro_aes_intr_map().bits()),
-            )
+            .field("pro_aes_intr_map", &self.pro_aes_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_AES_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map AES_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_apb_adc_int_map.rs b/esp32s2/src/interrupt_core0/pro_apb_adc_int_map.rs
index 1abf65800a..c6aeef7e7c 100644
--- a/esp32s2/src/interrupt_core0/pro_apb_adc_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_apb_adc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_APB_ADC_INT_MAP")
-            .field(
-                "pro_apb_adc_int_map",
-                &format_args!("{}", self.pro_apb_adc_int_map().bits()),
-            )
+            .field("pro_apb_adc_int_map", &self.pro_apb_adc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_APB_ADC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map APB_ADC_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_apb_peri_error_int_map.rs b/esp32s2/src/interrupt_core0/pro_apb_peri_error_int_map.rs
index 4aa543a3fc..de58c86235 100644
--- a/esp32s2/src/interrupt_core0/pro_apb_peri_error_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_apb_peri_error_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_APB_PERI_ERROR_INT_MAP")
             .field(
                 "pro_apb_peri_error_int_map",
-                &format_args!("{}", self.pro_apb_peri_error_int_map().bits()),
+                &self.pro_apb_peri_error_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_APB_PERI_ERROR_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map APB_PERI_ERROR_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_assist_debug_intr_map.rs b/esp32s2/src/interrupt_core0/pro_assist_debug_intr_map.rs
index 9912d91507..fc591fcfac 100644
--- a/esp32s2/src/interrupt_core0/pro_assist_debug_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_assist_debug_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_ASSIST_DEBUG_INTR_MAP")
             .field(
                 "pro_assist_debug_intr_map",
-                &format_args!("{}", self.pro_assist_debug_intr_map().bits()),
+                &self.pro_assist_debug_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ASSIST_DEBUG_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map ASSIST_DEBUG_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_bb_int_map.rs b/esp32s2/src/interrupt_core0/pro_bb_int_map.rs
index 3544377259..c79ea9795a 100644
--- a/esp32s2/src/interrupt_core0/pro_bb_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_bb_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_BB_INT_MAP")
-            .field(
-                "pro_bb_int_map",
-                &format_args!("{}", self.pro_bb_int_map().bits()),
-            )
+            .field("pro_bb_int_map", &self.pro_bb_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_BB_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map BB_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_bt_bb_int_map.rs b/esp32s2/src/interrupt_core0/pro_bt_bb_int_map.rs
index 6ea6159bab..d972157787 100644
--- a/esp32s2/src/interrupt_core0/pro_bt_bb_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_bt_bb_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_BT_BB_INT_MAP")
-            .field(
-                "pro_bt_bb_int_map",
-                &format_args!("{}", self.pro_bt_bb_int_map().bits()),
-            )
+            .field("pro_bt_bb_int_map", &self.pro_bt_bb_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_BT_BB_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map BT_BB_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_bt_bb_nmi_map.rs b/esp32s2/src/interrupt_core0/pro_bt_bb_nmi_map.rs
index 88ae7e3fa7..2703800124 100644
--- a/esp32s2/src/interrupt_core0/pro_bt_bb_nmi_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_bt_bb_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_BT_BB_NMI_MAP")
-            .field(
-                "pro_bt_bb_nmi_map",
-                &format_args!("{}", self.pro_bt_bb_nmi_map().bits()),
-            )
+            .field("pro_bt_bb_nmi_map", &self.pro_bt_bb_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_BT_BB_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map BT_BB_NMI interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_bt_mac_int_map.rs b/esp32s2/src/interrupt_core0/pro_bt_mac_int_map.rs
index 965093862a..c1fa6cef49 100644
--- a/esp32s2/src/interrupt_core0/pro_bt_mac_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_bt_mac_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_BT_MAC_INT_MAP")
-            .field(
-                "pro_bt_mac_int_map",
-                &format_args!("{}", self.pro_bt_mac_int_map().bits()),
-            )
+            .field("pro_bt_mac_int_map", &self.pro_bt_mac_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_BT_MAC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map BT_MAC_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_cache_ia_int_map.rs b/esp32s2/src/interrupt_core0/pro_cache_ia_int_map.rs
index 373190a357..c258fcd435 100644
--- a/esp32s2/src/interrupt_core0/pro_cache_ia_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_cache_ia_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CACHE_IA_INT_MAP")
-            .field(
-                "pro_cache_ia_int_map",
-                &format_args!("{}", self.pro_cache_ia_int_map().bits()),
-            )
+            .field("pro_cache_ia_int_map", &self.pro_cache_ia_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_IA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CACHE_IA_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_can_int_map.rs b/esp32s2/src/interrupt_core0/pro_can_int_map.rs
index 98f840ede9..b228c88db3 100644
--- a/esp32s2/src/interrupt_core0/pro_can_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_can_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CAN_INT_MAP")
-            .field(
-                "pro_can_int_map",
-                &format_args!("{}", self.pro_can_int_map().bits()),
-            )
+            .field("pro_can_int_map", &self.pro_can_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CAN_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CAN_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_0_map.rs b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_0_map.rs
index edca356b73..d20ed27176 100644
--- a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_0_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_0_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_CPU_INTR_FROM_CPU_0_MAP")
             .field(
                 "pro_cpu_intr_from_cpu_0_map",
-                &format_args!("{}", self.pro_cpu_intr_from_cpu_0_map().bits()),
+                &self.pro_cpu_intr_from_cpu_0_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_INTR_FROM_CPU_0_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CPU_INTR_FROM_CPU_0 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_1_map.rs b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_1_map.rs
index 469a6cc0dc..6502f29f8f 100644
--- a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_1_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_1_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_CPU_INTR_FROM_CPU_1_MAP")
             .field(
                 "pro_cpu_intr_from_cpu_1_map",
-                &format_args!("{}", self.pro_cpu_intr_from_cpu_1_map().bits()),
+                &self.pro_cpu_intr_from_cpu_1_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_INTR_FROM_CPU_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CPU_INTR_FROM_CPU_1 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_2_map.rs b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_2_map.rs
index d575b966f9..c6df2e2160 100644
--- a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_2_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_2_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_CPU_INTR_FROM_CPU_2_MAP")
             .field(
                 "pro_cpu_intr_from_cpu_2_map",
-                &format_args!("{}", self.pro_cpu_intr_from_cpu_2_map().bits()),
+                &self.pro_cpu_intr_from_cpu_2_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_INTR_FROM_CPU_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CPU_INTR_FROM_CPU_2 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_3_map.rs b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_3_map.rs
index d4ae7f28da..f6990591d6 100644
--- a/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_3_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_cpu_intr_from_cpu_3_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_CPU_INTR_FROM_CPU_3_MAP")
             .field(
                 "pro_cpu_intr_from_cpu_3_map",
-                &format_args!("{}", self.pro_cpu_intr_from_cpu_3_map().bits()),
+                &self.pro_cpu_intr_from_cpu_3_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_INTR_FROM_CPU_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CPU_INTR_FROM_CPU_3 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_cpu_peri_error_int_map.rs b/esp32s2/src/interrupt_core0/pro_cpu_peri_error_int_map.rs
index 7f119f7143..9533d11514 100644
--- a/esp32s2/src/interrupt_core0/pro_cpu_peri_error_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_cpu_peri_error_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_CPU_PERI_ERROR_INT_MAP")
             .field(
                 "pro_cpu_peri_error_int_map",
-                &format_args!("{}", self.pro_cpu_peri_error_int_map().bits()),
+                &self.pro_cpu_peri_error_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CPU_PERI_ERROR_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CPU_PERI_ERROR_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_crypto_dma_int_map.rs b/esp32s2/src/interrupt_core0/pro_crypto_dma_int_map.rs
index 700d90d2db..69c54dcf6f 100644
--- a/esp32s2/src/interrupt_core0/pro_crypto_dma_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_crypto_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CRYPTO_DMA_INT_MAP")
-            .field(
-                "pro_crypto_dma_int_map",
-                &format_args!("{}", self.pro_crypto_dma_int_map().bits()),
-            )
+            .field("pro_crypto_dma_int_map", &self.pro_crypto_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CRYPTO_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map CRYPTO_DMA_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_dcache_preload_int_map.rs b/esp32s2/src/interrupt_core0/pro_dcache_preload_int_map.rs
index fcbc7086f3..657c711d2a 100644
--- a/esp32s2/src/interrupt_core0/pro_dcache_preload_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_dcache_preload_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_DCACHE_PRELOAD_INT_MAP")
             .field(
                 "pro_dcache_preload_int_map",
-                &format_args!("{}", self.pro_dcache_preload_int_map().bits()),
+                &self.pro_dcache_preload_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_PRELOAD_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map DCACHE_PRELOAD_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_dcache_sync_int_map.rs b/esp32s2/src/interrupt_core0/pro_dcache_sync_int_map.rs
index ae45af900e..f0d8065ad9 100644
--- a/esp32s2/src/interrupt_core0/pro_dcache_sync_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_dcache_sync_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DCACHE_SYNC_INT_MAP")
-            .field(
-                "pro_dcache_sync_int_map",
-                &format_args!("{}", self.pro_dcache_sync_int_map().bits()),
-            )
+            .field("pro_dcache_sync_int_map", &self.pro_dcache_sync_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DCACHE_SYNC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map DCACHE_SYNC_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_dedicated_gpio_in_intr_map.rs b/esp32s2/src/interrupt_core0/pro_dedicated_gpio_in_intr_map.rs
index 9a5bfdb2bc..a480fc8729 100644
--- a/esp32s2/src/interrupt_core0/pro_dedicated_gpio_in_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_dedicated_gpio_in_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_DEDICATED_GPIO_IN_INTR_MAP")
             .field(
                 "pro_dedicated_gpio_in_intr_map",
-                &format_args!("{}", self.pro_dedicated_gpio_in_intr_map().bits()),
+                &self.pro_dedicated_gpio_in_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DEDICATED_GPIO_IN_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map DEDICATED_GPIO_IN_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_dma_copy_intr_map.rs b/esp32s2/src/interrupt_core0/pro_dma_copy_intr_map.rs
index 962305cb3b..d6bf228dbe 100644
--- a/esp32s2/src/interrupt_core0/pro_dma_copy_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_dma_copy_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DMA_COPY_INTR_MAP")
-            .field(
-                "pro_dma_copy_intr_map",
-                &format_args!("{}", self.pro_dma_copy_intr_map().bits()),
-            )
+            .field("pro_dma_copy_intr_map", &self.pro_dma_copy_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DMA_COPY_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map DMA_COPY_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_efuse_int_map.rs b/esp32s2/src/interrupt_core0/pro_efuse_int_map.rs
index 53cc99d4e4..e1baeea8d0 100644
--- a/esp32s2/src/interrupt_core0/pro_efuse_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_efuse_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_EFUSE_INT_MAP")
-            .field(
-                "pro_efuse_int_map",
-                &format_args!("{}", self.pro_efuse_int_map().bits()),
-            )
+            .field("pro_efuse_int_map", &self.pro_efuse_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_EFUSE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map EFUSE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_map.rs b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_map.rs
index cd1661cc69..add9f48bf2 100644
--- a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_GPIO_INTERRUPT_APP_MAP")
             .field(
                 "pro_gpio_interrupt_app_map",
-                &format_args!("{}", self.pro_gpio_interrupt_app_map().bits()),
+                &self.pro_gpio_interrupt_app_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_GPIO_INTERRUPT_APP_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map GPIO_INTERRUPT_APP interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_nmi_map.rs b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_nmi_map.rs
index fd3c661b35..00847ece52 100644
--- a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_nmi_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_app_nmi_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_GPIO_INTERRUPT_APP_NMI_MAP")
             .field(
                 "pro_gpio_interrupt_app_nmi_map",
-                &format_args!("{}", self.pro_gpio_interrupt_app_nmi_map().bits()),
+                &self.pro_gpio_interrupt_app_nmi_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_GPIO_INTERRUPT_APP_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map GPIO_INTERRUPT_APP_NMI interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_map.rs b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_map.rs
index d5f62d90b6..4051fd91a2 100644
--- a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_GPIO_INTERRUPT_PRO_MAP")
             .field(
                 "pro_gpio_interrupt_pro_map",
-                &format_args!("{}", self.pro_gpio_interrupt_pro_map().bits()),
+                &self.pro_gpio_interrupt_pro_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_GPIO_INTERRUPT_PRO_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map GPIO_INTERRUPT_PRO interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_nmi_map.rs b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_nmi_map.rs
index c5164ff7e2..3bea79824b 100644
--- a/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_nmi_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_gpio_interrupt_pro_nmi_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_GPIO_INTERRUPT_PRO_NMI_MAP")
             .field(
                 "pro_gpio_interrupt_pro_nmi_map",
-                &format_args!("{}", self.pro_gpio_interrupt_pro_nmi_map().bits()),
+                &self.pro_gpio_interrupt_pro_nmi_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_GPIO_INTERRUPT_PRO_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map GPIO_INTERRUPT_PRO_NMI interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_i2c_ext0_intr_map.rs b/esp32s2/src/interrupt_core0/pro_i2c_ext0_intr_map.rs
index 285b4dadaa..5290df3e78 100644
--- a/esp32s2/src/interrupt_core0/pro_i2c_ext0_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_i2c_ext0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_I2C_EXT0_INTR_MAP")
-            .field(
-                "pro_i2c_ext0_intr_map",
-                &format_args!("{}", self.pro_i2c_ext0_intr_map().bits()),
-            )
+            .field("pro_i2c_ext0_intr_map", &self.pro_i2c_ext0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_I2C_EXT0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map I2C_EXT0_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_i2c_ext1_intr_map.rs b/esp32s2/src/interrupt_core0/pro_i2c_ext1_intr_map.rs
index 8f69161e0d..98ebbcc698 100644
--- a/esp32s2/src/interrupt_core0/pro_i2c_ext1_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_i2c_ext1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_I2C_EXT1_INTR_MAP")
-            .field(
-                "pro_i2c_ext1_intr_map",
-                &format_args!("{}", self.pro_i2c_ext1_intr_map().bits()),
-            )
+            .field("pro_i2c_ext1_intr_map", &self.pro_i2c_ext1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_I2C_EXT1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map I2C_EXT1_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_i2s0_int_map.rs b/esp32s2/src/interrupt_core0/pro_i2s0_int_map.rs
index 11588cc2ac..8b59307a74 100644
--- a/esp32s2/src/interrupt_core0/pro_i2s0_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_i2s0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_I2S0_INT_MAP")
-            .field(
-                "pro_i2s0_int_map",
-                &format_args!("{}", self.pro_i2s0_int_map().bits()),
-            )
+            .field("pro_i2s0_int_map", &self.pro_i2s0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_I2S0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map I2S0_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_i2s1_int_map.rs b/esp32s2/src/interrupt_core0/pro_i2s1_int_map.rs
index ef69bcad95..58ab1a3e75 100644
--- a/esp32s2/src/interrupt_core0/pro_i2s1_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_i2s1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_I2S1_INT_MAP")
-            .field(
-                "pro_i2s1_int_map",
-                &format_args!("{}", self.pro_i2s1_int_map().bits()),
-            )
+            .field("pro_i2s1_int_map", &self.pro_i2s1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_I2S1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map I2S1_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_icache_preload_int_map.rs b/esp32s2/src/interrupt_core0/pro_icache_preload_int_map.rs
index ebc5ba35ef..21b380ab26 100644
--- a/esp32s2/src/interrupt_core0/pro_icache_preload_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_icache_preload_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_ICACHE_PRELOAD_INT_MAP")
             .field(
                 "pro_icache_preload_int_map",
-                &format_args!("{}", self.pro_icache_preload_int_map().bits()),
+                &self.pro_icache_preload_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_PRELOAD_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map ICACHE_PRELOAD_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_icache_sync_int_map.rs b/esp32s2/src/interrupt_core0/pro_icache_sync_int_map.rs
index 4a8e3007ce..03f95904ee 100644
--- a/esp32s2/src/interrupt_core0/pro_icache_sync_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_icache_sync_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_ICACHE_SYNC_INT_MAP")
-            .field(
-                "pro_icache_sync_int_map",
-                &format_args!("{}", self.pro_icache_sync_int_map().bits()),
-            )
+            .field("pro_icache_sync_int_map", &self.pro_icache_sync_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_ICACHE_SYNC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map ICACHE_SYNC_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_intr_status_0.rs b/esp32s2/src/interrupt_core0/pro_intr_status_0.rs
index 71dffaa9a9..b11ba5820b 100644
--- a/esp32s2/src/interrupt_core0/pro_intr_status_0.rs
+++ b/esp32s2/src/interrupt_core0/pro_intr_status_0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_INTR_STATUS_0")
-            .field(
-                "pro_intr_status_0",
-                &format_args!("{}", self.pro_intr_status_0().bits()),
-            )
+            .field("pro_intr_status_0", &self.pro_intr_status_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_INTR_STATUS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_intr_status_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_INTR_STATUS_0_SPEC;
 impl crate::RegisterSpec for PRO_INTR_STATUS_0_SPEC {
diff --git a/esp32s2/src/interrupt_core0/pro_intr_status_1.rs b/esp32s2/src/interrupt_core0/pro_intr_status_1.rs
index 753eded7f3..20e3a3ae81 100644
--- a/esp32s2/src/interrupt_core0/pro_intr_status_1.rs
+++ b/esp32s2/src/interrupt_core0/pro_intr_status_1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_INTR_STATUS_1")
-            .field(
-                "pro_intr_status_1",
-                &format_args!("{}", self.pro_intr_status_1().bits()),
-            )
+            .field("pro_intr_status_1", &self.pro_intr_status_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_INTR_STATUS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_intr_status_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_INTR_STATUS_1_SPEC;
 impl crate::RegisterSpec for PRO_INTR_STATUS_1_SPEC {
diff --git a/esp32s2/src/interrupt_core0/pro_intr_status_2.rs b/esp32s2/src/interrupt_core0/pro_intr_status_2.rs
index 0c6cb5dff4..c0262c878a 100644
--- a/esp32s2/src/interrupt_core0/pro_intr_status_2.rs
+++ b/esp32s2/src/interrupt_core0/pro_intr_status_2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_INTR_STATUS_2")
-            .field(
-                "pro_intr_status_2",
-                &format_args!("{}", self.pro_intr_status_2().bits()),
-            )
+            .field("pro_intr_status_2", &self.pro_intr_status_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_INTR_STATUS_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_intr_status_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_INTR_STATUS_2_SPEC;
 impl crate::RegisterSpec for PRO_INTR_STATUS_2_SPEC {
diff --git a/esp32s2/src/interrupt_core0/pro_ledc_int_map.rs b/esp32s2/src/interrupt_core0/pro_ledc_int_map.rs
index 919084864b..f0fab6fdc3 100644
--- a/esp32s2/src/interrupt_core0/pro_ledc_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_ledc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_LEDC_INT_MAP")
-            .field(
-                "pro_ledc_int_map",
-                &format_args!("{}", self.pro_ledc_int_map().bits()),
-            )
+            .field("pro_ledc_int_map", &self.pro_ledc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_LEDC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map LEDC_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_mac_intr_map.rs b/esp32s2/src/interrupt_core0/pro_mac_intr_map.rs
index e723f44d34..a2decc6743 100644
--- a/esp32s2/src/interrupt_core0/pro_mac_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_mac_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_MAC_INTR_MAP")
-            .field(
-                "pro_mac_intr_map",
-                &format_args!("{}", self.pro_mac_intr_map().bits()),
-            )
+            .field("pro_mac_intr_map", &self.pro_mac_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_MAC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map MAC_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_mac_nmi_map.rs b/esp32s2/src/interrupt_core0/pro_mac_nmi_map.rs
index 551dd2ab86..85b691dcca 100644
--- a/esp32s2/src/interrupt_core0/pro_mac_nmi_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_mac_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_MAC_NMI_MAP")
-            .field(
-                "pro_mac_nmi_map",
-                &format_args!("{}", self.pro_mac_nmi_map().bits()),
-            )
+            .field("pro_mac_nmi_map", &self.pro_mac_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_MAC_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map MAC_NMI interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_pcnt_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pcnt_intr_map.rs
index 426fc6bf35..33d3e56cac 100644
--- a/esp32s2/src/interrupt_core0/pro_pcnt_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pcnt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_PCNT_INTR_MAP")
-            .field(
-                "pro_pcnt_intr_map",
-                &format_args!("{}", self.pro_pcnt_intr_map().bits()),
-            )
+            .field("pro_pcnt_intr_map", &self.pro_pcnt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PCNT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PCNT_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_pms_dma_apb_i_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_dma_apb_i_ilg_intr_map.rs
index e4c9fbe59c..33816d37a2 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_dma_apb_i_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_dma_apb_i_ilg_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_PMS_DMA_APB_I_ILG_INTR_MAP")
             .field(
                 "pro_pms_dma_apb_i_ilg_intr_map",
-                &format_args!("{}", self.pro_pms_dma_apb_i_ilg_intr_map().bits()),
+                &self.pro_pms_dma_apb_i_ilg_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PMS_DMA_APB_I_ILG_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_DMA_APB_I_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_pms_dma_rx_i_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_dma_rx_i_ilg_intr_map.rs
index a78ca6ab01..487ea6bdc0 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_dma_rx_i_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_dma_rx_i_ilg_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_PMS_DMA_RX_I_ILG_INTR_MAP")
             .field(
                 "pro_pms_dma_rx_i_ilg_intr_map",
-                &format_args!("{}", self.pro_pms_dma_rx_i_ilg_intr_map().bits()),
+                &self.pro_pms_dma_rx_i_ilg_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PMS_DMA_RX_I_ILG_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_DMA_RX_I_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_pms_dma_tx_i_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_dma_tx_i_ilg_intr_map.rs
index 760ac86f60..3acfdac249 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_dma_tx_i_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_dma_tx_i_ilg_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_PMS_DMA_TX_I_ILG_INTR_MAP")
             .field(
                 "pro_pms_dma_tx_i_ilg_intr_map",
-                &format_args!("{}", self.pro_pms_dma_tx_i_ilg_intr_map().bits()),
+                &self.pro_pms_dma_tx_i_ilg_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PMS_DMA_TX_I_ILG_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_DMA_TX_I_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_pms_pro_ahb_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_pro_ahb_ilg_intr_map.rs
index 8d59e7cf5b..d32ee01d30 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_pro_ahb_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_pro_ahb_ilg_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_PMS_PRO_AHB_ILG_INTR_MAP")
             .field(
                 "pro_pms_pro_ahb_ilg_intr_map",
-                &format_args!("{}", self.pro_pms_pro_ahb_ilg_intr_map().bits()),
+                &self.pro_pms_pro_ahb_ilg_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PMS_PRO_AHB_ILG_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_PRO_AHB_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_pms_pro_cache_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_pro_cache_ilg_intr_map.rs
index 6c28f74158..99b51dc972 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_pro_cache_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_pro_cache_ilg_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_PMS_PRO_CACHE_ILG_INTR_MAP")
             .field(
                 "pro_pms_pro_cache_ilg_intr_map",
-                &format_args!("{}", self.pro_pms_pro_cache_ilg_intr_map().bits()),
+                &self.pro_pms_pro_cache_ilg_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PMS_PRO_CACHE_ILG_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_PRO_CACHE_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_pms_pro_dport_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_pro_dport_ilg_intr_map.rs
index 2bd45d6e0f..e6f285e462 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_pro_dport_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_pro_dport_ilg_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_PMS_PRO_DPORT_ILG_INTR_MAP")
             .field(
                 "pro_pms_pro_dport_ilg_intr_map",
-                &format_args!("{}", self.pro_pms_pro_dport_ilg_intr_map().bits()),
+                &self.pro_pms_pro_dport_ilg_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PMS_PRO_DPORT_ILG_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_PRO_DPORT_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_pms_pro_dram0_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_pro_dram0_ilg_intr_map.rs
index acffa4475f..839fe4a221 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_pro_dram0_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_pro_dram0_ilg_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_PMS_PRO_DRAM0_ILG_INTR_MAP")
             .field(
                 "pro_pms_pro_dram0_ilg_intr_map",
-                &format_args!("{}", self.pro_pms_pro_dram0_ilg_intr_map().bits()),
+                &self.pro_pms_pro_dram0_ilg_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_PRO_DRAM0_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_pms_pro_iram0_ilg_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pms_pro_iram0_ilg_intr_map.rs
index 12099d382b..972e50d244 100644
--- a/esp32s2/src/interrupt_core0/pro_pms_pro_iram0_ilg_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pms_pro_iram0_ilg_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_PMS_PRO_IRAM0_ILG_INTR_MAP")
             .field(
                 "pro_pms_pro_iram0_ilg_intr_map",
-                &format_args!("{}", self.pro_pms_pro_iram0_ilg_intr_map().bits()),
+                &self.pro_pms_pro_iram0_ilg_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PMS_PRO_IRAM0_ILG interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_pwm0_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pwm0_intr_map.rs
index 1cdcabb32f..d11ba4e7f9 100644
--- a/esp32s2/src/interrupt_core0/pro_pwm0_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pwm0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_PWM0_INTR_MAP")
-            .field(
-                "pro_pwm0_intr_map",
-                &format_args!("{}", self.pro_pwm0_intr_map().bits()),
-            )
+            .field("pro_pwm0_intr_map", &self.pro_pwm0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PWM0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PWM0_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_pwm1_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pwm1_intr_map.rs
index 56a2bedda7..f164aeb19f 100644
--- a/esp32s2/src/interrupt_core0/pro_pwm1_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pwm1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_PWM1_INTR_MAP")
-            .field(
-                "pro_pwm1_intr_map",
-                &format_args!("{}", self.pro_pwm1_intr_map().bits()),
-            )
+            .field("pro_pwm1_intr_map", &self.pro_pwm1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PWM1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PWM1_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_pwm2_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pwm2_intr_map.rs
index f9bd918011..4c0c50fac1 100644
--- a/esp32s2/src/interrupt_core0/pro_pwm2_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pwm2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_PWM2_INTR_MAP")
-            .field(
-                "pro_pwm2_intr_map",
-                &format_args!("{}", self.pro_pwm2_intr_map().bits()),
-            )
+            .field("pro_pwm2_intr_map", &self.pro_pwm2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PWM2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PWM2_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_pwm3_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pwm3_intr_map.rs
index d716fa6e3c..dffcdbd919 100644
--- a/esp32s2/src/interrupt_core0/pro_pwm3_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pwm3_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_PWM3_INTR_MAP")
-            .field(
-                "pro_pwm3_intr_map",
-                &format_args!("{}", self.pro_pwm3_intr_map().bits()),
-            )
+            .field("pro_pwm3_intr_map", &self.pro_pwm3_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PWM3_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PWM3_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_pwr_intr_map.rs b/esp32s2/src/interrupt_core0/pro_pwr_intr_map.rs
index bbb09049e4..9b9513399d 100644
--- a/esp32s2/src/interrupt_core0/pro_pwr_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_pwr_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_PWR_INTR_MAP")
-            .field(
-                "pro_pwr_intr_map",
-                &format_args!("{}", self.pro_pwr_intr_map().bits()),
-            )
+            .field("pro_pwr_intr_map", &self.pro_pwr_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_PWR_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map PWR_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_rmt_intr_map.rs b/esp32s2/src/interrupt_core0/pro_rmt_intr_map.rs
index da78e3d24d..3890cd601d 100644
--- a/esp32s2/src/interrupt_core0/pro_rmt_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_rmt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_RMT_INTR_MAP")
-            .field(
-                "pro_rmt_intr_map",
-                &format_args!("{}", self.pro_rmt_intr_map().bits()),
-            )
+            .field("pro_rmt_intr_map", &self.pro_rmt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_RMT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map RMT_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_rsa_intr_map.rs b/esp32s2/src/interrupt_core0/pro_rsa_intr_map.rs
index 198a6976e0..312b85b9f8 100644
--- a/esp32s2/src/interrupt_core0/pro_rsa_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_rsa_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_RSA_INTR_MAP")
-            .field(
-                "pro_rsa_intr_map",
-                &format_args!("{}", self.pro_rsa_intr_map().bits()),
-            )
+            .field("pro_rsa_intr_map", &self.pro_rsa_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_RSA_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map RSA_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_rtc_core_intr_map.rs b/esp32s2/src/interrupt_core0/pro_rtc_core_intr_map.rs
index f37c3a1ebc..46041f95ac 100644
--- a/esp32s2/src/interrupt_core0/pro_rtc_core_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_rtc_core_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_RTC_CORE_INTR_MAP")
-            .field(
-                "pro_rtc_core_intr_map",
-                &format_args!("{}", self.pro_rtc_core_intr_map().bits()),
-            )
+            .field("pro_rtc_core_intr_map", &self.pro_rtc_core_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_RTC_CORE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map RTC_CORE_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_rwble_irq_map.rs b/esp32s2/src/interrupt_core0/pro_rwble_irq_map.rs
index 8477eceb30..653867b69d 100644
--- a/esp32s2/src/interrupt_core0/pro_rwble_irq_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_rwble_irq_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_RWBLE_IRQ_MAP")
-            .field(
-                "pro_rwble_irq_map",
-                &format_args!("{}", self.pro_rwble_irq_map().bits()),
-            )
+            .field("pro_rwble_irq_map", &self.pro_rwble_irq_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_RWBLE_IRQ_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map RWBLE_IRQ interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_rwble_nmi_map.rs b/esp32s2/src/interrupt_core0/pro_rwble_nmi_map.rs
index d05c2e6432..1045290fdd 100644
--- a/esp32s2/src/interrupt_core0/pro_rwble_nmi_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_rwble_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_RWBLE_NMI_MAP")
-            .field(
-                "pro_rwble_nmi_map",
-                &format_args!("{}", self.pro_rwble_nmi_map().bits()),
-            )
+            .field("pro_rwble_nmi_map", &self.pro_rwble_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_RWBLE_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map RWBLE_NMI interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_rwbt_irq_map.rs b/esp32s2/src/interrupt_core0/pro_rwbt_irq_map.rs
index c41b6b9591..71d4e49022 100644
--- a/esp32s2/src/interrupt_core0/pro_rwbt_irq_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_rwbt_irq_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_RWBT_IRQ_MAP")
-            .field(
-                "pro_rwbt_irq_map",
-                &format_args!("{}", self.pro_rwbt_irq_map().bits()),
-            )
+            .field("pro_rwbt_irq_map", &self.pro_rwbt_irq_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_RWBT_IRQ_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map RWBT_IRQ interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_rwbt_nmi_map.rs b/esp32s2/src/interrupt_core0/pro_rwbt_nmi_map.rs
index c5b0a67f75..d3d3f9ea99 100644
--- a/esp32s2/src/interrupt_core0/pro_rwbt_nmi_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_rwbt_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_RWBT_NMI_MAP")
-            .field(
-                "pro_rwbt_nmi_map",
-                &format_args!("{}", self.pro_rwbt_nmi_map().bits()),
-            )
+            .field("pro_rwbt_nmi_map", &self.pro_rwbt_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_RWBT_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map RWBT_NMI interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_sdio_host_interrupt_map.rs b/esp32s2/src/interrupt_core0/pro_sdio_host_interrupt_map.rs
index 7fe9104028..fadd869f75 100644
--- a/esp32s2/src/interrupt_core0/pro_sdio_host_interrupt_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_sdio_host_interrupt_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_SDIO_HOST_INTERRUPT_MAP")
             .field(
                 "pro_sdio_host_interrupt_map",
-                &format_args!("{}", self.pro_sdio_host_interrupt_map().bits()),
+                &self.pro_sdio_host_interrupt_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SDIO_HOST_INTERRUPT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SDIO_HOST_INTERRUPT signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_sha_intr_map.rs b/esp32s2/src/interrupt_core0/pro_sha_intr_map.rs
index 3ee9ddf0f3..998a452eb1 100644
--- a/esp32s2/src/interrupt_core0/pro_sha_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_sha_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SHA_INTR_MAP")
-            .field(
-                "pro_sha_intr_map",
-                &format_args!("{}", self.pro_sha_intr_map().bits()),
-            )
+            .field("pro_sha_intr_map", &self.pro_sha_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SHA_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SHA_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_slc0_intr_map.rs b/esp32s2/src/interrupt_core0/pro_slc0_intr_map.rs
index e73de599d0..b12fe83ccd 100644
--- a/esp32s2/src/interrupt_core0/pro_slc0_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_slc0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SLC0_INTR_MAP")
-            .field(
-                "pro_slc0_intr_map",
-                &format_args!("{}", self.pro_slc0_intr_map().bits()),
-            )
+            .field("pro_slc0_intr_map", &self.pro_slc0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SLC0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SLC0_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_slc1_intr_map.rs b/esp32s2/src/interrupt_core0/pro_slc1_intr_map.rs
index 8db01be4d5..f038ad5383 100644
--- a/esp32s2/src/interrupt_core0/pro_slc1_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_slc1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SLC1_INTR_MAP")
-            .field(
-                "pro_slc1_intr_map",
-                &format_args!("{}", self.pro_slc1_intr_map().bits()),
-            )
+            .field("pro_slc1_intr_map", &self.pro_slc1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SLC1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SLC1_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_spi2_dma_int_map.rs b/esp32s2/src/interrupt_core0/pro_spi2_dma_int_map.rs
index e57ca6fd00..956b391c58 100644
--- a/esp32s2/src/interrupt_core0/pro_spi2_dma_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi2_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SPI2_DMA_INT_MAP")
-            .field(
-                "pro_spi2_dma_int_map",
-                &format_args!("{}", self.pro_spi2_dma_int_map().bits()),
-            )
+            .field("pro_spi2_dma_int_map", &self.pro_spi2_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SPI2_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map AES_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_spi3_dma_int_map.rs b/esp32s2/src/interrupt_core0/pro_spi3_dma_int_map.rs
index d5d1273b02..3413a0c951 100644
--- a/esp32s2/src/interrupt_core0/pro_spi3_dma_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi3_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SPI3_DMA_INT_MAP")
-            .field(
-                "pro_spi3_dma_int_map",
-                &format_args!("{}", self.pro_spi3_dma_int_map().bits()),
-            )
+            .field("pro_spi3_dma_int_map", &self.pro_spi3_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SPI3_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SPI3_DMA_INT dma interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_spi4_dma_int_map.rs b/esp32s2/src/interrupt_core0/pro_spi4_dma_int_map.rs
index 3a98545d05..4e983c77e7 100644
--- a/esp32s2/src/interrupt_core0/pro_spi4_dma_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi4_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SPI4_DMA_INT_MAP")
-            .field(
-                "pro_spi4_dma_int_map",
-                &format_args!("{}", self.pro_spi4_dma_int_map().bits()),
-            )
+            .field("pro_spi4_dma_int_map", &self.pro_spi4_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SPI4_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SPI4_DMA_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_spi_intr_1_map.rs b/esp32s2/src/interrupt_core0/pro_spi_intr_1_map.rs
index e807a8ba7b..428d9beeac 100644
--- a/esp32s2/src/interrupt_core0/pro_spi_intr_1_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi_intr_1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SPI_INTR_1_MAP")
-            .field(
-                "pro_spi_intr_1_map",
-                &format_args!("{}", self.pro_spi_intr_1_map().bits()),
-            )
+            .field("pro_spi_intr_1_map", &self.pro_spi_intr_1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SPI_INTR_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SPI_INTR_1 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_spi_intr_2_map.rs b/esp32s2/src/interrupt_core0/pro_spi_intr_2_map.rs
index 411e7e004a..4ae2487018 100644
--- a/esp32s2/src/interrupt_core0/pro_spi_intr_2_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi_intr_2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SPI_INTR_2_MAP")
-            .field(
-                "pro_spi_intr_2_map",
-                &format_args!("{}", self.pro_spi_intr_2_map().bits()),
-            )
+            .field("pro_spi_intr_2_map", &self.pro_spi_intr_2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SPI_INTR_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SPI_INTR_2 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_spi_intr_3_map.rs b/esp32s2/src/interrupt_core0/pro_spi_intr_3_map.rs
index 8183b06787..df115c01a2 100644
--- a/esp32s2/src/interrupt_core0/pro_spi_intr_3_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi_intr_3_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SPI_INTR_3_MAP")
-            .field(
-                "pro_spi_intr_3_map",
-                &format_args!("{}", self.pro_spi_intr_3_map().bits()),
-            )
+            .field("pro_spi_intr_3_map", &self.pro_spi_intr_3_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SPI_INTR_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SPI_INTR_3 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_spi_intr_4_map.rs b/esp32s2/src/interrupt_core0/pro_spi_intr_4_map.rs
index 4e16015d3f..6b1a220c5a 100644
--- a/esp32s2/src/interrupt_core0/pro_spi_intr_4_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi_intr_4_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_SPI_INTR_4_MAP")
-            .field(
-                "pro_spi_intr_4_map",
-                &format_args!("{}", self.pro_spi_intr_4_map().bits()),
-            )
+            .field("pro_spi_intr_4_map", &self.pro_spi_intr_4_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SPI_INTR_4_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SPI_INTR_4 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_spi_mem_reject_intr_map.rs b/esp32s2/src/interrupt_core0/pro_spi_mem_reject_intr_map.rs
index c5b12bef91..4ad653f366 100644
--- a/esp32s2/src/interrupt_core0/pro_spi_mem_reject_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_spi_mem_reject_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_SPI_MEM_REJECT_INTR_MAP")
             .field(
                 "pro_spi_mem_reject_intr_map",
-                &format_args!("{}", self.pro_spi_mem_reject_intr_map().bits()),
+                &self.pro_spi_mem_reject_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SPI_MEM_REJECT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SPI_MEM_REJECT_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_systimer_target0_int_map.rs b/esp32s2/src/interrupt_core0/pro_systimer_target0_int_map.rs
index cb5612aec8..8d57c8e539 100644
--- a/esp32s2/src/interrupt_core0/pro_systimer_target0_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_systimer_target0_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_SYSTIMER_TARGET0_INT_MAP")
             .field(
                 "pro_systimer_target0_int_map",
-                &format_args!("{}", self.pro_systimer_target0_int_map().bits()),
+                &self.pro_systimer_target0_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SYSTIMER_TARGET0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SYSTIMER_TARGET0_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_systimer_target1_int_map.rs b/esp32s2/src/interrupt_core0/pro_systimer_target1_int_map.rs
index 6efdf5126e..514df5fc69 100644
--- a/esp32s2/src/interrupt_core0/pro_systimer_target1_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_systimer_target1_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_SYSTIMER_TARGET1_INT_MAP")
             .field(
                 "pro_systimer_target1_int_map",
-                &format_args!("{}", self.pro_systimer_target1_int_map().bits()),
+                &self.pro_systimer_target1_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SYSTIMER_TARGET1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SYSTIMER_TARGET1_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_systimer_target2_int_map.rs b/esp32s2/src/interrupt_core0/pro_systimer_target2_int_map.rs
index ffdb4c128b..f6c9eee707 100644
--- a/esp32s2/src/interrupt_core0/pro_systimer_target2_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_systimer_target2_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_SYSTIMER_TARGET2_INT_MAP")
             .field(
                 "pro_systimer_target2_int_map",
-                &format_args!("{}", self.pro_systimer_target2_int_map().bits()),
+                &self.pro_systimer_target2_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_SYSTIMER_TARGET2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map SYSTIMER_TARGET2_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_lact_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_lact_edge_int_map.rs
index 840178d7ba..b4644f4df7 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_lact_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_lact_edge_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_TG1_LACT_EDGE_INT_MAP")
             .field(
                 "pro_tg1_lact_edge_int_map",
-                &format_args!("{}", self.pro_tg1_lact_edge_int_map().bits()),
+                &self.pro_tg1_lact_edge_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_LACT_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_LACT_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_lact_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_lact_level_int_map.rs
index 26b0853c77..a2c716efe1 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_lact_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_lact_level_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_TG1_LACT_LEVEL_INT_MAP")
             .field(
                 "pro_tg1_lact_level_int_map",
-                &format_args!("{}", self.pro_tg1_lact_level_int_map().bits()),
+                &self.pro_tg1_lact_level_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_LACT_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_LACT_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_t0_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_t0_edge_int_map.rs
index d5a54cc665..4399829a46 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_t0_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_t0_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG1_T0_EDGE_INT_MAP")
-            .field(
-                "pro_tg1_t0_edge_int_map",
-                &format_args!("{}", self.pro_tg1_t0_edge_int_map().bits()),
-            )
+            .field("pro_tg1_t0_edge_int_map", &self.pro_tg1_t0_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_T0_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_T0_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_t0_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_t0_level_int_map.rs
index 38094df653..d36aef2e63 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_t0_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_t0_level_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG1_T0_LEVEL_INT_MAP")
-            .field(
-                "pro_tg1_t0_level_int_map",
-                &format_args!("{}", self.pro_tg1_t0_level_int_map().bits()),
-            )
+            .field("pro_tg1_t0_level_int_map", &self.pro_tg1_t0_level_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_T0_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_T0_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_t1_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_t1_edge_int_map.rs
index 00f2ddc6d8..619527bc59 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_t1_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_t1_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG1_T1_EDGE_INT_MAP")
-            .field(
-                "pro_tg1_t1_edge_int_map",
-                &format_args!("{}", self.pro_tg1_t1_edge_int_map().bits()),
-            )
+            .field("pro_tg1_t1_edge_int_map", &self.pro_tg1_t1_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_T1_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_T1_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_t1_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_t1_level_int_map.rs
index e06963327f..7bcb9da6ec 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_t1_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_t1_level_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG1_T1_LEVEL_INT_MAP")
-            .field(
-                "pro_tg1_t1_level_int_map",
-                &format_args!("{}", self.pro_tg1_t1_level_int_map().bits()),
-            )
+            .field("pro_tg1_t1_level_int_map", &self.pro_tg1_t1_level_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_T1_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_T1_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_wdt_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_wdt_edge_int_map.rs
index 9059c9070c..1404e806df 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_wdt_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_wdt_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG1_WDT_EDGE_INT_MAP")
-            .field(
-                "pro_tg1_wdt_edge_int_map",
-                &format_args!("{}", self.pro_tg1_wdt_edge_int_map().bits()),
-            )
+            .field("pro_tg1_wdt_edge_int_map", &self.pro_tg1_wdt_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_WDT_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_WDT_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg1_wdt_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg1_wdt_level_int_map.rs
index d8a4983f6c..cc5493902e 100644
--- a/esp32s2/src/interrupt_core0/pro_tg1_wdt_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg1_wdt_level_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_TG1_WDT_LEVEL_INT_MAP")
             .field(
                 "pro_tg1_wdt_level_int_map",
-                &format_args!("{}", self.pro_tg1_wdt_level_int_map().bits()),
+                &self.pro_tg1_wdt_level_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG1_WDT_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG1_WDT_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg_lact_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_lact_edge_int_map.rs
index 75e723dc82..769bd0d617 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_lact_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_lact_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG_LACT_EDGE_INT_MAP")
-            .field(
-                "pro_tg_lact_edge_int_map",
-                &format_args!("{}", self.pro_tg_lact_edge_int_map().bits()),
-            )
+            .field("pro_tg_lact_edge_int_map", &self.pro_tg_lact_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_LACT_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_LACT_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg_lact_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_lact_level_int_map.rs
index 3eeb887ccc..1a56172f18 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_lact_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_lact_level_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_TG_LACT_LEVEL_INT_MAP")
             .field(
                 "pro_tg_lact_level_int_map",
-                &format_args!("{}", self.pro_tg_lact_level_int_map().bits()),
+                &self.pro_tg_lact_level_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_LACT_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_LACT_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg_t0_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_t0_edge_int_map.rs
index 6bd261af80..59bf209e02 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_t0_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_t0_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG_T0_EDGE_INT_MAP")
-            .field(
-                "pro_tg_t0_edge_int_map",
-                &format_args!("{}", self.pro_tg_t0_edge_int_map().bits()),
-            )
+            .field("pro_tg_t0_edge_int_map", &self.pro_tg_t0_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_T0_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_T0_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg_t0_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_t0_level_int_map.rs
index 7ad8386c0e..a035acf5a3 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_t0_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_t0_level_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG_T0_LEVEL_INT_MAP")
-            .field(
-                "pro_tg_t0_level_int_map",
-                &format_args!("{}", self.pro_tg_t0_level_int_map().bits()),
-            )
+            .field("pro_tg_t0_level_int_map", &self.pro_tg_t0_level_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_T0_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_T0_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg_t1_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_t1_edge_int_map.rs
index db39268d8e..4e0bd94bb7 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_t1_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_t1_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG_T1_EDGE_INT_MAP")
-            .field(
-                "pro_tg_t1_edge_int_map",
-                &format_args!("{}", self.pro_tg_t1_edge_int_map().bits()),
-            )
+            .field("pro_tg_t1_edge_int_map", &self.pro_tg_t1_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_T1_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_T1_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg_t1_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_t1_level_int_map.rs
index f53918e2d0..b7744eb758 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_t1_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_t1_level_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG_T1_LEVEL_INT_MAP")
-            .field(
-                "pro_tg_t1_level_int_map",
-                &format_args!("{}", self.pro_tg_t1_level_int_map().bits()),
-            )
+            .field("pro_tg_t1_level_int_map", &self.pro_tg_t1_level_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_T1_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_T1_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg_wdt_edge_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_wdt_edge_int_map.rs
index 788891b8bb..d00bdc4d15 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_wdt_edge_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_wdt_edge_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG_WDT_EDGE_INT_MAP")
-            .field(
-                "pro_tg_wdt_edge_int_map",
-                &format_args!("{}", self.pro_tg_wdt_edge_int_map().bits()),
-            )
+            .field("pro_tg_wdt_edge_int_map", &self.pro_tg_wdt_edge_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_WDT_EDGE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_WDT_EDGE_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_tg_wdt_level_int_map.rs b/esp32s2/src/interrupt_core0/pro_tg_wdt_level_int_map.rs
index d40ae1df7e..35b3152fb5 100644
--- a/esp32s2/src/interrupt_core0/pro_tg_wdt_level_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_tg_wdt_level_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TG_WDT_LEVEL_INT_MAP")
-            .field(
-                "pro_tg_wdt_level_int_map",
-                &format_args!("{}", self.pro_tg_wdt_level_int_map().bits()),
-            )
+            .field("pro_tg_wdt_level_int_map", &self.pro_tg_wdt_level_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TG_WDT_LEVEL_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TG_WDT_LEVEL_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_timer_int1_map.rs b/esp32s2/src/interrupt_core0/pro_timer_int1_map.rs
index 9bdd21665f..7547c9ac88 100644
--- a/esp32s2/src/interrupt_core0/pro_timer_int1_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_timer_int1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TIMER_INT1_MAP")
-            .field(
-                "pro_timer_int1_map",
-                &format_args!("{}", self.pro_timer_int1_map().bits()),
-            )
+            .field("pro_timer_int1_map", &self.pro_timer_int1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TIMER_INT1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TIMER_INT1 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_timer_int2_map.rs b/esp32s2/src/interrupt_core0/pro_timer_int2_map.rs
index b1039fa71a..a9734ea2c9 100644
--- a/esp32s2/src/interrupt_core0/pro_timer_int2_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_timer_int2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TIMER_INT2_MAP")
-            .field(
-                "pro_timer_int2_map",
-                &format_args!("{}", self.pro_timer_int2_map().bits()),
-            )
+            .field("pro_timer_int2_map", &self.pro_timer_int2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TIMER_INT2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map TIMER_INT2 interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_uart1_intr_map.rs b/esp32s2/src/interrupt_core0/pro_uart1_intr_map.rs
index ef976ad4c2..c099d2714d 100644
--- a/esp32s2/src/interrupt_core0/pro_uart1_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_uart1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_UART1_INTR_MAP")
-            .field(
-                "pro_uart1_intr_map",
-                &format_args!("{}", self.pro_uart1_intr_map().bits()),
-            )
+            .field("pro_uart1_intr_map", &self.pro_uart1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_UART1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map UART1_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_uart2_intr_map.rs b/esp32s2/src/interrupt_core0/pro_uart2_intr_map.rs
index 6141f34107..5d7295fbf8 100644
--- a/esp32s2/src/interrupt_core0/pro_uart2_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_uart2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_UART2_INTR_MAP")
-            .field(
-                "pro_uart2_intr_map",
-                &format_args!("{}", self.pro_uart2_intr_map().bits()),
-            )
+            .field("pro_uart2_intr_map", &self.pro_uart2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_UART2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map UART2_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_uart_intr_map.rs b/esp32s2/src/interrupt_core0/pro_uart_intr_map.rs
index 66306396d8..4292587422 100644
--- a/esp32s2/src/interrupt_core0/pro_uart_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_uart_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_UART_INTR_MAP")
-            .field(
-                "pro_uart_intr_map",
-                &format_args!("{}", self.pro_uart_intr_map().bits()),
-            )
+            .field("pro_uart_intr_map", &self.pro_uart_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_UART_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map UART_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_uhci0_intr_map.rs b/esp32s2/src/interrupt_core0/pro_uhci0_intr_map.rs
index 235cd0706e..7ccfd329c0 100644
--- a/esp32s2/src/interrupt_core0/pro_uhci0_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_uhci0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_UHCI0_INTR_MAP")
-            .field(
-                "pro_uhci0_intr_map",
-                &format_args!("{}", self.pro_uhci0_intr_map().bits()),
-            )
+            .field("pro_uhci0_intr_map", &self.pro_uhci0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_UHCI0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map UHCI0_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_uhci1_intr_map.rs b/esp32s2/src/interrupt_core0/pro_uhci1_intr_map.rs
index 9242baeacd..2e4c3486b7 100644
--- a/esp32s2/src/interrupt_core0/pro_uhci1_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_uhci1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_UHCI1_INTR_MAP")
-            .field(
-                "pro_uhci1_intr_map",
-                &format_args!("{}", self.pro_uhci1_intr_map().bits()),
-            )
+            .field("pro_uhci1_intr_map", &self.pro_uhci1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_UHCI1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map UHCI1_INTR interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_usb_intr_map.rs b/esp32s2/src/interrupt_core0/pro_usb_intr_map.rs
index ebb378d1a0..5243a8bc29 100644
--- a/esp32s2/src/interrupt_core0/pro_usb_intr_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_usb_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_USB_INTR_MAP")
-            .field(
-                "pro_usb_intr_map",
-                &format_args!("{}", self.pro_usb_intr_map().bits()),
-            )
+            .field("pro_usb_intr_map", &self.pro_usb_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_USB_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map USB_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/pro_wdg_int_map.rs b/esp32s2/src/interrupt_core0/pro_wdg_int_map.rs
index 7973f96dc4..e718b24bb0 100644
--- a/esp32s2/src/interrupt_core0/pro_wdg_int_map.rs
+++ b/esp32s2/src/interrupt_core0/pro_wdg_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_WDG_INT_MAP")
-            .field(
-                "pro_wdg_int_map",
-                &format_args!("{}", self.pro_wdg_int_map().bits()),
-            )
+            .field("pro_wdg_int_map", &self.pro_wdg_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_WDG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to map WDG_INT interrupt signal to one of the CPU interrupts."]
     #[inline(always)]
diff --git a/esp32s2/src/interrupt_core0/reg_date.rs b/esp32s2/src/interrupt_core0/reg_date.rs
index 2fd78a2da0..491a607149 100644
--- a/esp32s2/src/interrupt_core0/reg_date.rs
+++ b/esp32s2/src/interrupt_core0/reg_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_DATE")
-            .field(
-                "interrupt_reg_date",
-                &format_args!("{}", self.interrupt_reg_date().bits()),
-            )
+            .field("interrupt_reg_date", &self.interrupt_reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - This is the version register."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/date.rs b/esp32s2/src/io_mux/date.rs
index c53ae8039f..89118a415d 100644
--- a/esp32s2/src/io_mux/date.rs
+++ b/esp32s2/src/io_mux/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("version", &format_args!("{}", self.version().bits()))
+            .field("version", &self.version())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio0.rs b/esp32s2/src/io_mux/gpio0.rs
index dd0a90c817..8e7dfc9c31 100644
--- a/esp32s2/src/io_mux/gpio0.rs
+++ b/esp32s2/src/io_mux/gpio0.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO0")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio1.rs b/esp32s2/src/io_mux/gpio1.rs
index 9a0a140206..e13deba243 100644
--- a/esp32s2/src/io_mux/gpio1.rs
+++ b/esp32s2/src/io_mux/gpio1.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO1")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio10.rs b/esp32s2/src/io_mux/gpio10.rs
index 2e664ec926..532762dd74 100644
--- a/esp32s2/src/io_mux/gpio10.rs
+++ b/esp32s2/src/io_mux/gpio10.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO10")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio11.rs b/esp32s2/src/io_mux/gpio11.rs
index baf12a4eed..c1fa325579 100644
--- a/esp32s2/src/io_mux/gpio11.rs
+++ b/esp32s2/src/io_mux/gpio11.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO11")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio12.rs b/esp32s2/src/io_mux/gpio12.rs
index 9cd22d8abf..0c620847bc 100644
--- a/esp32s2/src/io_mux/gpio12.rs
+++ b/esp32s2/src/io_mux/gpio12.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO12")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio13.rs b/esp32s2/src/io_mux/gpio13.rs
index d2a1d892f1..d7e56f9bd8 100644
--- a/esp32s2/src/io_mux/gpio13.rs
+++ b/esp32s2/src/io_mux/gpio13.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO13")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio14.rs b/esp32s2/src/io_mux/gpio14.rs
index 1de1c44d2a..aaa3cea652 100644
--- a/esp32s2/src/io_mux/gpio14.rs
+++ b/esp32s2/src/io_mux/gpio14.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO14")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio15.rs b/esp32s2/src/io_mux/gpio15.rs
index f8fd3607e7..0c8285c86b 100644
--- a/esp32s2/src/io_mux/gpio15.rs
+++ b/esp32s2/src/io_mux/gpio15.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO15")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio16.rs b/esp32s2/src/io_mux/gpio16.rs
index 7b0a24dba3..caf4d7690b 100644
--- a/esp32s2/src/io_mux/gpio16.rs
+++ b/esp32s2/src/io_mux/gpio16.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO16")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO16_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio17.rs b/esp32s2/src/io_mux/gpio17.rs
index 961a7dcd3d..dbc656f44b 100644
--- a/esp32s2/src/io_mux/gpio17.rs
+++ b/esp32s2/src/io_mux/gpio17.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO17")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO17_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio18.rs b/esp32s2/src/io_mux/gpio18.rs
index db2b0931db..5be07a9681 100644
--- a/esp32s2/src/io_mux/gpio18.rs
+++ b/esp32s2/src/io_mux/gpio18.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO18")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO18_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio19.rs b/esp32s2/src/io_mux/gpio19.rs
index 825b884c17..08a798f2bb 100644
--- a/esp32s2/src/io_mux/gpio19.rs
+++ b/esp32s2/src/io_mux/gpio19.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO19")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO19_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio2.rs b/esp32s2/src/io_mux/gpio2.rs
index cf2abe3723..f132501784 100644
--- a/esp32s2/src/io_mux/gpio2.rs
+++ b/esp32s2/src/io_mux/gpio2.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO2")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio20.rs b/esp32s2/src/io_mux/gpio20.rs
index 033f6b1b8b..77e3a7aa7d 100644
--- a/esp32s2/src/io_mux/gpio20.rs
+++ b/esp32s2/src/io_mux/gpio20.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO20")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO20_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio21.rs b/esp32s2/src/io_mux/gpio21.rs
index 6459358a05..35570540ef 100644
--- a/esp32s2/src/io_mux/gpio21.rs
+++ b/esp32s2/src/io_mux/gpio21.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO21")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO21_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio26.rs b/esp32s2/src/io_mux/gpio26.rs
index 0fabe505da..5e66ff6d43 100644
--- a/esp32s2/src/io_mux/gpio26.rs
+++ b/esp32s2/src/io_mux/gpio26.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO26")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO26_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio27.rs b/esp32s2/src/io_mux/gpio27.rs
index e304b6830d..55ec011e59 100644
--- a/esp32s2/src/io_mux/gpio27.rs
+++ b/esp32s2/src/io_mux/gpio27.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO27")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO27_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio28.rs b/esp32s2/src/io_mux/gpio28.rs
index 875b7952da..e62b36bafc 100644
--- a/esp32s2/src/io_mux/gpio28.rs
+++ b/esp32s2/src/io_mux/gpio28.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO28")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO28_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio29.rs b/esp32s2/src/io_mux/gpio29.rs
index 2343149af1..419b51f46a 100644
--- a/esp32s2/src/io_mux/gpio29.rs
+++ b/esp32s2/src/io_mux/gpio29.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO29")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO29_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio3.rs b/esp32s2/src/io_mux/gpio3.rs
index f4bf49e2f8..8f2eac03be 100644
--- a/esp32s2/src/io_mux/gpio3.rs
+++ b/esp32s2/src/io_mux/gpio3.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO3")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio30.rs b/esp32s2/src/io_mux/gpio30.rs
index f1830faba3..63af00f9ac 100644
--- a/esp32s2/src/io_mux/gpio30.rs
+++ b/esp32s2/src/io_mux/gpio30.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO30")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO30_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio31.rs b/esp32s2/src/io_mux/gpio31.rs
index 3997719494..7e8b140c38 100644
--- a/esp32s2/src/io_mux/gpio31.rs
+++ b/esp32s2/src/io_mux/gpio31.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO31")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO31_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio32.rs b/esp32s2/src/io_mux/gpio32.rs
index bfc46f33df..2504c3be5e 100644
--- a/esp32s2/src/io_mux/gpio32.rs
+++ b/esp32s2/src/io_mux/gpio32.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO32")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO32_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio33.rs b/esp32s2/src/io_mux/gpio33.rs
index 71ad3df534..568064771e 100644
--- a/esp32s2/src/io_mux/gpio33.rs
+++ b/esp32s2/src/io_mux/gpio33.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO33")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO33_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio34.rs b/esp32s2/src/io_mux/gpio34.rs
index 3bddea41bd..88b6b0487b 100644
--- a/esp32s2/src/io_mux/gpio34.rs
+++ b/esp32s2/src/io_mux/gpio34.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO34")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO34_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio35.rs b/esp32s2/src/io_mux/gpio35.rs
index f55398b9a4..1b095e64b4 100644
--- a/esp32s2/src/io_mux/gpio35.rs
+++ b/esp32s2/src/io_mux/gpio35.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO35")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO35_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio36.rs b/esp32s2/src/io_mux/gpio36.rs
index 0cf65bd681..3ce2900d02 100644
--- a/esp32s2/src/io_mux/gpio36.rs
+++ b/esp32s2/src/io_mux/gpio36.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO36")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO36_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio37.rs b/esp32s2/src/io_mux/gpio37.rs
index 6dad0b7239..8f9f53943d 100644
--- a/esp32s2/src/io_mux/gpio37.rs
+++ b/esp32s2/src/io_mux/gpio37.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO37")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO37_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio38.rs b/esp32s2/src/io_mux/gpio38.rs
index 84f5f1951b..ff858b4f04 100644
--- a/esp32s2/src/io_mux/gpio38.rs
+++ b/esp32s2/src/io_mux/gpio38.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO38")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO38_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio39.rs b/esp32s2/src/io_mux/gpio39.rs
index bad38977f8..5717de98e6 100644
--- a/esp32s2/src/io_mux/gpio39.rs
+++ b/esp32s2/src/io_mux/gpio39.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO39")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO39_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio4.rs b/esp32s2/src/io_mux/gpio4.rs
index ee4f9006df..ed2de60f0f 100644
--- a/esp32s2/src/io_mux/gpio4.rs
+++ b/esp32s2/src/io_mux/gpio4.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO4")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio40.rs b/esp32s2/src/io_mux/gpio40.rs
index 443c2719e5..57fa1be718 100644
--- a/esp32s2/src/io_mux/gpio40.rs
+++ b/esp32s2/src/io_mux/gpio40.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO40")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO40_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio41.rs b/esp32s2/src/io_mux/gpio41.rs
index 7062cff8bc..9bb20b10bb 100644
--- a/esp32s2/src/io_mux/gpio41.rs
+++ b/esp32s2/src/io_mux/gpio41.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO41")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO41_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio42.rs b/esp32s2/src/io_mux/gpio42.rs
index 1f9ab362ac..c5ad62f1dc 100644
--- a/esp32s2/src/io_mux/gpio42.rs
+++ b/esp32s2/src/io_mux/gpio42.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO42")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO42_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio43.rs b/esp32s2/src/io_mux/gpio43.rs
index f85c6ac4cb..2bdcb9df80 100644
--- a/esp32s2/src/io_mux/gpio43.rs
+++ b/esp32s2/src/io_mux/gpio43.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO43")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO43_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio44.rs b/esp32s2/src/io_mux/gpio44.rs
index 0537417a64..156b145fb5 100644
--- a/esp32s2/src/io_mux/gpio44.rs
+++ b/esp32s2/src/io_mux/gpio44.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO44")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO44_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio45.rs b/esp32s2/src/io_mux/gpio45.rs
index 5aa96f7119..f7a3a4345f 100644
--- a/esp32s2/src/io_mux/gpio45.rs
+++ b/esp32s2/src/io_mux/gpio45.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO45")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO45_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio46.rs b/esp32s2/src/io_mux/gpio46.rs
index 256ca0e0d9..00275fd795 100644
--- a/esp32s2/src/io_mux/gpio46.rs
+++ b/esp32s2/src/io_mux/gpio46.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO46")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO46_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio5.rs b/esp32s2/src/io_mux/gpio5.rs
index 0fd8963110..812744245b 100644
--- a/esp32s2/src/io_mux/gpio5.rs
+++ b/esp32s2/src/io_mux/gpio5.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO5")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio6.rs b/esp32s2/src/io_mux/gpio6.rs
index 32417dde8a..2143c1f4ca 100644
--- a/esp32s2/src/io_mux/gpio6.rs
+++ b/esp32s2/src/io_mux/gpio6.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO6")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio7.rs b/esp32s2/src/io_mux/gpio7.rs
index 31bac9752b..2e449a7de8 100644
--- a/esp32s2/src/io_mux/gpio7.rs
+++ b/esp32s2/src/io_mux/gpio7.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO7")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio8.rs b/esp32s2/src/io_mux/gpio8.rs
index 765dfd11be..732af7429a 100644
--- a/esp32s2/src/io_mux/gpio8.rs
+++ b/esp32s2/src/io_mux/gpio8.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO8")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/gpio9.rs b/esp32s2/src/io_mux/gpio9.rs
index ec83d7c919..c0b6e01ea9 100644
--- a/esp32s2/src/io_mux/gpio9.rs
+++ b/esp32s2/src/io_mux/gpio9.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO9")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/io_mux/pin_ctrl.rs b/esp32s2/src/io_mux/pin_ctrl.rs
index e571a87b22..bae67666f0 100644
--- a/esp32s2/src/io_mux/pin_ctrl.rs
+++ b/esp32s2/src/io_mux/pin_ctrl.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN_CTRL")
-            .field(
-                "pin_clk_out1",
-                &format_args!("{}", self.pin_clk_out1().bits()),
-            )
-            .field(
-                "pin_clk_out2",
-                &format_args!("{}", self.pin_clk_out2().bits()),
-            )
-            .field(
-                "pin_clk_out3",
-                &format_args!("{}", self.pin_clk_out3().bits()),
-            )
-            .field(
-                "switch_prt_num",
-                &format_args!("{}", self.switch_prt_num().bits()),
-            )
-            .field(
-                "pad_power_ctrl",
-                &format_args!("{}", self.pad_power_ctrl().bit()),
-            )
+            .field("pin_clk_out1", &self.pin_clk_out1())
+            .field("pin_clk_out2", &self.pin_clk_out2())
+            .field("pin_clk_out3", &self.pin_clk_out3())
+            .field("switch_prt_num", &self.switch_prt_num())
+            .field("pad_power_ctrl", &self.pad_power_ctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT1. 15: disabled."]
     #[inline(always)]
diff --git a/esp32s2/src/ledc/ch/conf0.rs b/esp32s2/src/ledc/ch/conf0.rs
index f3471e8b13..e349302625 100644
--- a/esp32s2/src/ledc/ch/conf0.rs
+++ b/esp32s2/src/ledc/ch/conf0.rs
@@ -64,24 +64,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("timer_sel", &format_args!("{}", self.timer_sel().bits()))
-            .field("sig_out_en", &format_args!("{}", self.sig_out_en().bit()))
-            .field("idle_lv", &format_args!("{}", self.idle_lv().bit()))
-            .field("ovf_num", &format_args!("{}", self.ovf_num().bits()))
-            .field("ovf_cnt_en", &format_args!("{}", self.ovf_cnt_en().bit()))
-            .field(
-                "ovf_cnt_reset_st",
-                &format_args!("{}", self.ovf_cnt_reset_st().bit()),
-            )
+            .field("timer_sel", &self.timer_sel())
+            .field("sig_out_en", &self.sig_out_en())
+            .field("idle_lv", &self.idle_lv())
+            .field("ovf_num", &self.ovf_num())
+            .field("ovf_cnt_en", &self.ovf_cnt_en())
+            .field("ovf_cnt_reset_st", &self.ovf_cnt_reset_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to select one of timers for channel %s. 0: select timer 0. 1: select timer 1. 2: select timer 2. 3: select timer 3."]
     #[inline(always)]
diff --git a/esp32s2/src/ledc/ch/conf1.rs b/esp32s2/src/ledc/ch/conf1.rs
index a30314218b..1f0f511c4f 100644
--- a/esp32s2/src/ledc/ch/conf1.rs
+++ b/esp32s2/src/ledc/ch/conf1.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field("duty_scale", &format_args!("{}", self.duty_scale().bits()))
-            .field("duty_cycle", &format_args!("{}", self.duty_cycle().bits()))
-            .field("duty_num", &format_args!("{}", self.duty_num().bits()))
-            .field("duty_inc", &format_args!("{}", self.duty_inc().bit()))
-            .field("duty_start", &format_args!("{}", self.duty_start().bit()))
+            .field("duty_scale", &self.duty_scale())
+            .field("duty_cycle", &self.duty_cycle())
+            .field("duty_num", &self.duty_num())
+            .field("duty_inc", &self.duty_inc())
+            .field("duty_start", &self.duty_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the changing step scale of duty on channel %s."]
     #[inline(always)]
diff --git a/esp32s2/src/ledc/ch/duty.rs b/esp32s2/src/ledc/ch/duty.rs
index dd4f150d88..03e1bba638 100644
--- a/esp32s2/src/ledc/ch/duty.rs
+++ b/esp32s2/src/ledc/ch/duty.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DUTY")
-            .field("duty", &format_args!("{}", self.duty().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DUTY").field("duty", &self.duty()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/ledc/ch/duty_r.rs b/esp32s2/src/ledc/ch/duty_r.rs
index b1870f3014..28e94586f2 100644
--- a/esp32s2/src/ledc/ch/duty_r.rs
+++ b/esp32s2/src/ledc/ch/duty_r.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DUTY_R")
-            .field("duty_r", &format_args!("{}", self.duty_r().bits()))
+            .field("duty_r", &self.duty_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_R_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current duty cycle for channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`duty_r::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DUTY_R_SPEC;
 impl crate::RegisterSpec for DUTY_R_SPEC {
diff --git a/esp32s2/src/ledc/ch/hpoint.rs b/esp32s2/src/ledc/ch/hpoint.rs
index 559465bb7f..c2c53fa871 100644
--- a/esp32s2/src/ledc/ch/hpoint.rs
+++ b/esp32s2/src/ledc/ch/hpoint.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPOINT")
-            .field("hpoint", &format_args!("{}", self.hpoint().bits()))
+            .field("hpoint", &self.hpoint())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPOINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - The output value changes to high when the selected timers has reached the value specified by this register."]
     #[inline(always)]
diff --git a/esp32s2/src/ledc/conf.rs b/esp32s2/src/ledc/conf.rs
index bf08785441..b832d293e7 100644
--- a/esp32s2/src/ledc/conf.rs
+++ b/esp32s2/src/ledc/conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field(
-                "apb_clk_sel",
-                &format_args!("{}", self.apb_clk_sel().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("apb_clk_sel", &self.apb_clk_sel())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This bit is used to select clock source for the 4 timers . 1: APB_CLK. 2: RTC8M_CLK. 3: XTAL_CLK."]
     #[inline(always)]
diff --git a/esp32s2/src/ledc/date.rs b/esp32s2/src/ledc/date.rs
index 1ba956c2fb..f0d04c37d1 100644
--- a/esp32s2/src/ledc/date.rs
+++ b/esp32s2/src/ledc/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/ledc/int_ena.rs b/esp32s2/src/ledc/int_ena.rs
index 573e013acf..ae57204c6d 100644
--- a/esp32s2/src/ledc/int_ena.rs
+++ b/esp32s2/src/ledc/int_ena.rs
@@ -165,59 +165,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field(
-                "duty_chng_end_ch6",
-                &format_args!("{}", self.duty_chng_end_ch6().bit()),
-            )
-            .field(
-                "duty_chng_end_ch7",
-                &format_args!("{}", self.duty_chng_end_ch7().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
-            .field("ovf_cnt_ch6", &format_args!("{}", self.ovf_cnt_ch6().bit()))
-            .field("ovf_cnt_ch7", &format_args!("{}", self.ovf_cnt_ch7().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("duty_chng_end_ch6", &self.duty_chng_end_ch6())
+            .field("duty_chng_end_ch7", &self.duty_chng_end_ch7())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
+            .field("ovf_cnt_ch6", &self.ovf_cnt_ch6())
+            .field("ovf_cnt_ch7", &self.ovf_cnt_ch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the TIMER(0-3)_OVF interrupt."]
     #[doc = ""]
diff --git a/esp32s2/src/ledc/int_raw.rs b/esp32s2/src/ledc/int_raw.rs
index e8cda2b2fe..21ab54c3a1 100644
--- a/esp32s2/src/ledc/int_raw.rs
+++ b/esp32s2/src/ledc/int_raw.rs
@@ -165,59 +165,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field(
-                "duty_chng_end_ch6",
-                &format_args!("{}", self.duty_chng_end_ch6().bit()),
-            )
-            .field(
-                "duty_chng_end_ch7",
-                &format_args!("{}", self.duty_chng_end_ch7().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
-            .field("ovf_cnt_ch6", &format_args!("{}", self.ovf_cnt_ch6().bit()))
-            .field("ovf_cnt_ch7", &format_args!("{}", self.ovf_cnt_ch7().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("duty_chng_end_ch6", &self.duty_chng_end_ch6())
+            .field("duty_chng_end_ch7", &self.duty_chng_end_ch7())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
+            .field("ovf_cnt_ch6", &self.ovf_cnt_ch6())
+            .field("ovf_cnt_ch7", &self.ovf_cnt_ch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Triggered when the timer(0-3) has reached its maximum counter value."]
     #[doc = ""]
diff --git a/esp32s2/src/ledc/int_st.rs b/esp32s2/src/ledc/int_st.rs
index 72c09e8394..9674d08294 100644
--- a/esp32s2/src/ledc/int_st.rs
+++ b/esp32s2/src/ledc/int_st.rs
@@ -157,59 +157,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field(
-                "duty_chng_end_ch6",
-                &format_args!("{}", self.duty_chng_end_ch6().bit()),
-            )
-            .field(
-                "duty_chng_end_ch7",
-                &format_args!("{}", self.duty_chng_end_ch7().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
-            .field("ovf_cnt_ch6", &format_args!("{}", self.ovf_cnt_ch6().bit()))
-            .field("ovf_cnt_ch7", &format_args!("{}", self.ovf_cnt_ch7().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("duty_chng_end_ch6", &self.duty_chng_end_ch6())
+            .field("duty_chng_end_ch7", &self.duty_chng_end_ch7())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
+            .field("ovf_cnt_ch6", &self.ovf_cnt_ch6())
+            .field("ovf_cnt_ch7", &self.ovf_cnt_ch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s2/src/ledc/timer/conf.rs b/esp32s2/src/ledc/timer/conf.rs
index 32b2a24e58..5aae2f12b1 100644
--- a/esp32s2/src/ledc/timer/conf.rs
+++ b/esp32s2/src/ledc/timer/conf.rs
@@ -55,20 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("duty_res", &format_args!("{}", self.duty_res().bits()))
-            .field("clk_div", &format_args!("{}", self.clk_div().bits()))
-            .field("pause", &format_args!("{}", self.pause().bit()))
-            .field("rst", &format_args!("{}", self.rst().bit()))
-            .field("tick_sel", &format_args!("{}", self.tick_sel().bit()))
+            .field("duty_res", &self.duty_res())
+            .field("clk_div", &self.clk_div())
+            .field("pause", &self.pause())
+            .field("rst", &self.rst())
+            .field("tick_sel", &self.tick_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - This register is used to control the range of the counter in timer %s."]
     #[inline(always)]
diff --git a/esp32s2/src/ledc/timer/value.rs b/esp32s2/src/ledc/timer/value.rs
index ee3ddb9c1b..598dc71136 100644
--- a/esp32s2/src/ledc/timer/value.rs
+++ b/esp32s2/src/ledc/timer/value.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("VALUE")
-            .field("cnt", &format_args!("{}", self.cnt().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("VALUE").field("cnt", &self.cnt()).finish()
     }
 }
 #[doc = "Timer 0 current counter value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s2/src/lib.rs b/esp32s2/src/lib.rs
index 8743bcbd73..7f8620d7ee 100644
--- a/esp32s2/src/lib.rs
+++ b/esp32s2/src/lib.rs
@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32-S2 microcontrollers (generated using svd2rust v0.33.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32-S2 microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
diff --git a/esp32s2/src/pcnt/ctrl.rs b/esp32s2/src/pcnt/ctrl.rs
index 5bba68adc6..8cd43c0d37 100644
--- a/esp32s2/src/pcnt/ctrl.rs
+++ b/esp32s2/src/pcnt/ctrl.rs
@@ -95,36 +95,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("cnt_rst_u0", &format_args!("{}", self.cnt_rst_u0().bit()))
-            .field("cnt_rst_u1", &format_args!("{}", self.cnt_rst_u1().bit()))
-            .field("cnt_rst_u2", &format_args!("{}", self.cnt_rst_u2().bit()))
-            .field("cnt_rst_u3", &format_args!("{}", self.cnt_rst_u3().bit()))
-            .field(
-                "cnt_pause_u0",
-                &format_args!("{}", self.cnt_pause_u0().bit()),
-            )
-            .field(
-                "cnt_pause_u1",
-                &format_args!("{}", self.cnt_pause_u1().bit()),
-            )
-            .field(
-                "cnt_pause_u2",
-                &format_args!("{}", self.cnt_pause_u2().bit()),
-            )
-            .field(
-                "cnt_pause_u3",
-                &format_args!("{}", self.cnt_pause_u3().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("cnt_rst_u0", &self.cnt_rst_u0())
+            .field("cnt_rst_u1", &self.cnt_rst_u1())
+            .field("cnt_rst_u2", &self.cnt_rst_u2())
+            .field("cnt_rst_u3", &self.cnt_rst_u3())
+            .field("cnt_pause_u0", &self.cnt_pause_u0())
+            .field("cnt_pause_u1", &self.cnt_pause_u1())
+            .field("cnt_pause_u2", &self.cnt_pause_u2())
+            .field("cnt_pause_u3", &self.cnt_pause_u3())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Set this bit to clear unit(0-3)'s counter."]
     #[doc = ""]
diff --git a/esp32s2/src/pcnt/date.rs b/esp32s2/src/pcnt/date.rs
index daef1d7bcf..5a80a19072 100644
--- a/esp32s2/src/pcnt/date.rs
+++ b/esp32s2/src/pcnt/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/pcnt/int_ena.rs b/esp32s2/src/pcnt/int_ena.rs
index 4423a16c83..7372693fe3 100644
--- a/esp32s2/src/pcnt/int_ena.rs
+++ b/esp32s2/src/pcnt/int_ena.rs
@@ -47,31 +47,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
     #[doc = ""]
diff --git a/esp32s2/src/pcnt/int_raw.rs b/esp32s2/src/pcnt/int_raw.rs
index bd68f6891b..0e4e8347cf 100644
--- a/esp32s2/src/pcnt/int_raw.rs
+++ b/esp32s2/src/pcnt/int_raw.rs
@@ -43,31 +43,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt raw status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s2/src/pcnt/int_st.rs b/esp32s2/src/pcnt/int_st.rs
index d1a59c1bf3..870d7ad253 100644
--- a/esp32s2/src/pcnt/int_st.rs
+++ b/esp32s2/src/pcnt/int_st.rs
@@ -43,31 +43,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s2/src/pcnt/u_cnt.rs b/esp32s2/src/pcnt/u_cnt.rs
index 34bef2c06c..7a45c58a0d 100644
--- a/esp32s2/src/pcnt/u_cnt.rs
+++ b/esp32s2/src/pcnt/u_cnt.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("U_CNT")
-            .field("cnt", &format_args!("{}", self.cnt().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("U_CNT").field("cnt", &self.cnt()).finish()
     }
 }
 #[doc = "Counter value for unit %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s2/src/pcnt/u_status.rs b/esp32s2/src/pcnt/u_status.rs
index 4e4060b09d..9b1b40471f 100644
--- a/esp32s2/src/pcnt/u_status.rs
+++ b/esp32s2/src/pcnt/u_status.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("U_STATUS")
-            .field("zero_mode", &format_args!("{}", self.zero_mode().bits()))
-            .field("thres1", &format_args!("{}", self.thres1().bit()))
-            .field("thres0", &format_args!("{}", self.thres0().bit()))
-            .field("l_lim", &format_args!("{}", self.l_lim().bit()))
-            .field("h_lim", &format_args!("{}", self.h_lim().bit()))
-            .field("zero", &format_args!("{}", self.zero().bit()))
+            .field("zero_mode", &self.zero_mode())
+            .field("thres1", &self.thres1())
+            .field("thres0", &self.thres0())
+            .field("l_lim", &self.l_lim())
+            .field("h_lim", &self.h_lim())
+            .field("zero", &self.zero())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "PNCT UNIT%s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct U_STATUS_SPEC;
 impl crate::RegisterSpec for U_STATUS_SPEC {
diff --git a/esp32s2/src/pcnt/unit/conf0.rs b/esp32s2/src/pcnt/unit/conf0.rs
index 7be65a378c..a66e892dfa 100644
--- a/esp32s2/src/pcnt/unit/conf0.rs
+++ b/esp32s2/src/pcnt/unit/conf0.rs
@@ -325,69 +325,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field(
-                "filter_thres",
-                &format_args!("{}", self.filter_thres().bits()),
-            )
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
-            .field("thr_zero_en", &format_args!("{}", self.thr_zero_en().bit()))
-            .field(
-                "thr_h_lim_en",
-                &format_args!("{}", self.thr_h_lim_en().bit()),
-            )
-            .field(
-                "thr_l_lim_en",
-                &format_args!("{}", self.thr_l_lim_en().bit()),
-            )
-            .field(
-                "thr_thres0_en",
-                &format_args!("{}", self.thr_thres0_en().bit()),
-            )
-            .field(
-                "thr_thres1_en",
-                &format_args!("{}", self.thr_thres1_en().bit()),
-            )
-            .field(
-                "ch0_neg_mode",
-                &format_args!("{}", self.ch0_neg_mode().bits()),
-            )
-            .field(
-                "ch1_neg_mode",
-                &format_args!("{}", self.ch1_neg_mode().bits()),
-            )
-            .field(
-                "ch0_pos_mode",
-                &format_args!("{}", self.ch0_pos_mode().bits()),
-            )
-            .field(
-                "ch1_pos_mode",
-                &format_args!("{}", self.ch1_pos_mode().bits()),
-            )
-            .field(
-                "ch0_hctrl_mode",
-                &format_args!("{}", self.ch0_hctrl_mode().bits()),
-            )
-            .field(
-                "ch1_hctrl_mode",
-                &format_args!("{}", self.ch1_hctrl_mode().bits()),
-            )
-            .field(
-                "ch0_lctrl_mode",
-                &format_args!("{}", self.ch0_lctrl_mode().bits()),
-            )
-            .field(
-                "ch1_lctrl_mode",
-                &format_args!("{}", self.ch1_lctrl_mode().bits()),
-            )
+            .field("filter_thres", &self.filter_thres())
+            .field("filter_en", &self.filter_en())
+            .field("thr_zero_en", &self.thr_zero_en())
+            .field("thr_h_lim_en", &self.thr_h_lim_en())
+            .field("thr_l_lim_en", &self.thr_l_lim_en())
+            .field("thr_thres0_en", &self.thr_thres0_en())
+            .field("thr_thres1_en", &self.thr_thres1_en())
+            .field("ch0_neg_mode", &self.ch0_neg_mode())
+            .field("ch1_neg_mode", &self.ch1_neg_mode())
+            .field("ch0_pos_mode", &self.ch0_pos_mode())
+            .field("ch1_pos_mode", &self.ch1_pos_mode())
+            .field("ch0_hctrl_mode", &self.ch0_hctrl_mode())
+            .field("ch1_hctrl_mode", &self.ch1_hctrl_mode())
+            .field("ch0_lctrl_mode", &self.ch0_lctrl_mode())
+            .field("ch1_lctrl_mode", &self.ch1_lctrl_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
     #[inline(always)]
diff --git a/esp32s2/src/pcnt/unit/conf1.rs b/esp32s2/src/pcnt/unit/conf1.rs
index 62e92aa446..d516d127e6 100644
--- a/esp32s2/src/pcnt/unit/conf1.rs
+++ b/esp32s2/src/pcnt/unit/conf1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field("cnt_thres0", &format_args!("{}", self.cnt_thres0().bits()))
-            .field("cnt_thres1", &format_args!("{}", self.cnt_thres1().bits()))
+            .field("cnt_thres0", &self.cnt_thres0())
+            .field("cnt_thres1", &self.cnt_thres1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the thres0 value for unit %s."]
     #[inline(always)]
diff --git a/esp32s2/src/pcnt/unit/conf2.rs b/esp32s2/src/pcnt/unit/conf2.rs
index 85e906ae09..25118d3c9c 100644
--- a/esp32s2/src/pcnt/unit/conf2.rs
+++ b/esp32s2/src/pcnt/unit/conf2.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF2")
-            .field("cnt_h_lim", &format_args!("{}", self.cnt_h_lim().bits()))
-            .field("cnt_l_lim", &format_args!("{}", self.cnt_l_lim().bits()))
+            .field("cnt_h_lim", &self.cnt_h_lim())
+            .field("cnt_l_lim", &self.cnt_l_lim())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the thr_h_lim value for unit %s."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/apb_peripheral_0.rs b/esp32s2/src/pms/apb_peripheral_0.rs
index 849ba14ff3..ef77715377 100644
--- a/esp32s2/src/pms/apb_peripheral_0.rs
+++ b/esp32s2/src/pms/apb_peripheral_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_PERIPHERAL_0")
-            .field(
-                "apb_peripheral_lock",
-                &format_args!("{}", self.apb_peripheral_lock().bit()),
-            )
+            .field("apb_peripheral_lock", &self.apb_peripheral_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_PERIPHERAL_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks TX Copy DMA permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/apb_peripheral_1.rs b/esp32s2/src/pms/apb_peripheral_1.rs
index 669cbfd885..baa8ae8845 100644
--- a/esp32s2/src/pms/apb_peripheral_1.rs
+++ b/esp32s2/src/pms/apb_peripheral_1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB_PERIPHERAL_1")
             .field(
                 "apb_peripheral_split_burst",
-                &format_args!("{}", self.apb_peripheral_split_burst().bit()),
+                &self.apb_peripheral_split_burst(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_PERIPHERAL_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Setting to 1 splits the data phase of the last access and the address phase of following access."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/apb_peripheral_intr.rs b/esp32s2/src/pms/apb_peripheral_intr.rs
index 8299df822e..e8744f03c2 100644
--- a/esp32s2/src/pms/apb_peripheral_intr.rs
+++ b/esp32s2/src/pms/apb_peripheral_intr.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_PERIPHERAL_INTR")
-            .field(
-                "apb_peri_byte_error_clr",
-                &format_args!("{}", self.apb_peri_byte_error_clr().bit()),
-            )
-            .field(
-                "apb_peri_byte_error_en",
-                &format_args!("{}", self.apb_peri_byte_error_en().bit()),
-            )
-            .field(
-                "apb_peri_byte_error_intr",
-                &format_args!("{}", self.apb_peri_byte_error_intr().bit()),
-            )
+            .field("apb_peri_byte_error_clr", &self.apb_peri_byte_error_clr())
+            .field("apb_peri_byte_error_en", &self.apb_peri_byte_error_en())
+            .field("apb_peri_byte_error_intr", &self.apb_peri_byte_error_intr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_PERIPHERAL_INTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The clear signal for APB peripheral interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/apb_peripheral_status.rs b/esp32s2/src/pms/apb_peripheral_status.rs
index 6d9a4d8382..5d9d643a41 100644
--- a/esp32s2/src/pms/apb_peripheral_status.rs
+++ b/esp32s2/src/pms/apb_peripheral_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_PERIPHERAL_STATUS")
-            .field(
-                "apb_peri_byte_error_addr",
-                &format_args!("{}", self.apb_peri_byte_error_addr().bits()),
-            )
+            .field("apb_peri_byte_error_addr", &self.apb_peri_byte_error_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_PERIPHERAL_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "PeribBus2 peripheral access status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb_peripheral_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB_PERIPHERAL_STATUS_SPEC;
 impl crate::RegisterSpec for APB_PERIPHERAL_STATUS_SPEC {
diff --git a/esp32s2/src/pms/cache_mmu_access_0.rs b/esp32s2/src/pms/cache_mmu_access_0.rs
index 6e5ffbd72d..146573aa19 100644
--- a/esp32s2/src/pms/cache_mmu_access_0.rs
+++ b/esp32s2/src/pms/cache_mmu_access_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_ACCESS_0")
-            .field(
-                "cache_mmu_access_lock",
-                &format_args!("{}", self.cache_mmu_access_lock().bit()),
-            )
+            .field("cache_mmu_access_lock", &self.cache_mmu_access_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_ACCESS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks cache MMU permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/cache_mmu_access_1.rs b/esp32s2/src/pms/cache_mmu_access_1.rs
index 2c349f27c7..eade8d8f4e 100644
--- a/esp32s2/src/pms/cache_mmu_access_1.rs
+++ b/esp32s2/src/pms/cache_mmu_access_1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_ACCESS_1")
-            .field(
-                "pro_mmu_rd_acs",
-                &format_args!("{}", self.pro_mmu_rd_acs().bit()),
-            )
-            .field(
-                "pro_mmu_wr_acs",
-                &format_args!("{}", self.pro_mmu_wr_acs().bit()),
-            )
+            .field("pro_mmu_rd_acs", &self.pro_mmu_rd_acs())
+            .field("pro_mmu_wr_acs", &self.pro_mmu_wr_acs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_ACCESS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Setting to 1 permits read access to MMU memory."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/cache_source_0.rs b/esp32s2/src/pms/cache_source_0.rs
index 5c158596cb..9f3a033b7e 100644
--- a/esp32s2/src/pms/cache_source_0.rs
+++ b/esp32s2/src/pms/cache_source_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_SOURCE_0")
-            .field(
-                "cache_source_lock",
-                &format_args!("{}", self.cache_source_lock().bit()),
-            )
+            .field("cache_source_lock", &self.cache_source_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_SOURCE_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks cache access permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/cache_source_1.rs b/esp32s2/src/pms/cache_source_1.rs
index e6af622a97..dcbba48039 100644
--- a/esp32s2/src/pms/cache_source_1.rs
+++ b/esp32s2/src/pms/cache_source_1.rs
@@ -64,37 +64,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("CACHE_SOURCE_1")
             .field(
                 "pro_cache_i_source_pro_iram1",
-                &format_args!("{}", self.pro_cache_i_source_pro_iram1().bit()),
+                &self.pro_cache_i_source_pro_iram1(),
             )
             .field(
                 "pro_cache_i_source_pro_irom0",
-                &format_args!("{}", self.pro_cache_i_source_pro_irom0().bit()),
+                &self.pro_cache_i_source_pro_irom0(),
             )
             .field(
                 "pro_cache_i_source_pro_drom0",
-                &format_args!("{}", self.pro_cache_i_source_pro_drom0().bit()),
+                &self.pro_cache_i_source_pro_drom0(),
             )
             .field(
                 "pro_cache_d_source_pro_dram0",
-                &format_args!("{}", self.pro_cache_d_source_pro_dram0().bit()),
+                &self.pro_cache_d_source_pro_dram0(),
             )
             .field(
                 "pro_cache_d_source_pro_dport",
-                &format_args!("{}", self.pro_cache_d_source_pro_dport().bit()),
+                &self.pro_cache_d_source_pro_dport(),
             )
             .field(
                 "pro_cache_d_source_pro_drom0",
-                &format_args!("{}", self.pro_cache_d_source_pro_drom0().bit()),
+                &self.pro_cache_d_source_pro_drom0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_SOURCE_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - xx"]
     #[inline(always)]
diff --git a/esp32s2/src/pms/cache_tag_access_0.rs b/esp32s2/src/pms/cache_tag_access_0.rs
index 23088c5da9..2b165f8313 100644
--- a/esp32s2/src/pms/cache_tag_access_0.rs
+++ b/esp32s2/src/pms/cache_tag_access_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_TAG_ACCESS_0")
-            .field(
-                "cache_tag_access_lock",
-                &format_args!("{}", self.cache_tag_access_lock().bit()),
-            )
+            .field("cache_tag_access_lock", &self.cache_tag_access_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_TAG_ACCESS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks cache tag permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/cache_tag_access_1.rs b/esp32s2/src/pms/cache_tag_access_1.rs
index adbebd285c..a24896acdf 100644
--- a/esp32s2/src/pms/cache_tag_access_1.rs
+++ b/esp32s2/src/pms/cache_tag_access_1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_TAG_ACCESS_1")
-            .field(
-                "pro_i_tag_rd_acs",
-                &format_args!("{}", self.pro_i_tag_rd_acs().bit()),
-            )
-            .field(
-                "pro_i_tag_wr_acs",
-                &format_args!("{}", self.pro_i_tag_wr_acs().bit()),
-            )
-            .field(
-                "pro_d_tag_rd_acs",
-                &format_args!("{}", self.pro_d_tag_rd_acs().bit()),
-            )
-            .field(
-                "pro_d_tag_wr_acs",
-                &format_args!("{}", self.pro_d_tag_wr_acs().bit()),
-            )
+            .field("pro_i_tag_rd_acs", &self.pro_i_tag_rd_acs())
+            .field("pro_i_tag_wr_acs", &self.pro_i_tag_wr_acs())
+            .field("pro_d_tag_rd_acs", &self.pro_d_tag_rd_acs())
+            .field("pro_d_tag_wr_acs", &self.pro_d_tag_wr_acs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_TAG_ACCESS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Setting to 1 permits read access to Icache tag memory."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/clock_gate.rs b/esp32s2/src/pms/clock_gate.rs
index aebfbaf2b6..d4397b7191 100644
--- a/esp32s2/src/pms/clock_gate.rs
+++ b/esp32s2/src/pms/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable the clock of permission control module when set to 1."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/cpu_peripheral_intr.rs b/esp32s2/src/pms/cpu_peripheral_intr.rs
index 8eedb791f7..82328578bb 100644
--- a/esp32s2/src/pms/cpu_peripheral_intr.rs
+++ b/esp32s2/src/pms/cpu_peripheral_intr.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERIPHERAL_INTR")
-            .field(
-                "cpu_peri_byte_error_clr",
-                &format_args!("{}", self.cpu_peri_byte_error_clr().bit()),
-            )
-            .field(
-                "cpu_peri_byte_error_en",
-                &format_args!("{}", self.cpu_peri_byte_error_en().bit()),
-            )
-            .field(
-                "cpu_peri_byte_error_intr",
-                &format_args!("{}", self.cpu_peri_byte_error_intr().bit()),
-            )
+            .field("cpu_peri_byte_error_clr", &self.cpu_peri_byte_error_clr())
+            .field("cpu_peri_byte_error_en", &self.cpu_peri_byte_error_en())
+            .field("cpu_peri_byte_error_intr", &self.cpu_peri_byte_error_intr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERIPHERAL_INTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The clear signal for CPU peripheral access interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/cpu_peripheral_status.rs b/esp32s2/src/pms/cpu_peripheral_status.rs
index dc12433909..122353d211 100644
--- a/esp32s2/src/pms/cpu_peripheral_status.rs
+++ b/esp32s2/src/pms/cpu_peripheral_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERIPHERAL_STATUS")
-            .field(
-                "cpu_peri_byte_error_addr",
-                &format_args!("{}", self.cpu_peri_byte_error_addr().bits()),
-            )
+            .field("cpu_peri_byte_error_addr", &self.cpu_peri_byte_error_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERIPHERAL_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "PeribBus1 peripheral access status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_peripheral_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPU_PERIPHERAL_STATUS_SPEC;
 impl crate::RegisterSpec for CPU_PERIPHERAL_STATUS_SPEC {
diff --git a/esp32s2/src/pms/date.rs b/esp32s2/src/pms/date.rs
index fe5b908f8a..815a5754de 100644
--- a/esp32s2/src/pms/date.rs
+++ b/esp32s2/src/pms/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/pms/dma_apb_i_0.rs b/esp32s2/src/pms/dma_apb_i_0.rs
index 7d255aba2c..3d70d9ea0a 100644
--- a/esp32s2/src/pms/dma_apb_i_0.rs
+++ b/esp32s2/src/pms/dma_apb_i_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_APB_I_0")
-            .field(
-                "dma_apb_i_lock",
-                &format_args!("{}", self.dma_apb_i_lock().bit()),
-            )
+            .field("dma_apb_i_lock", &self.dma_apb_i_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APB_I_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks internal DMA permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/dma_apb_i_1.rs b/esp32s2/src/pms/dma_apb_i_1.rs
index 60f11b636b..9653fbf1e8 100644
--- a/esp32s2/src/pms/dma_apb_i_1.rs
+++ b/esp32s2/src/pms/dma_apb_i_1.rs
@@ -125,67 +125,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_APB_I_1")
-            .field(
-                "dma_apb_i_sram_0_r",
-                &format_args!("{}", self.dma_apb_i_sram_0_r().bit()),
-            )
-            .field(
-                "dma_apb_i_sram_0_w",
-                &format_args!("{}", self.dma_apb_i_sram_0_w().bit()),
-            )
-            .field(
-                "dma_apb_i_sram_1_r",
-                &format_args!("{}", self.dma_apb_i_sram_1_r().bit()),
-            )
-            .field(
-                "dma_apb_i_sram_1_w",
-                &format_args!("{}", self.dma_apb_i_sram_1_w().bit()),
-            )
-            .field(
-                "dma_apb_i_sram_2_r",
-                &format_args!("{}", self.dma_apb_i_sram_2_r().bit()),
-            )
-            .field(
-                "dma_apb_i_sram_2_w",
-                &format_args!("{}", self.dma_apb_i_sram_2_w().bit()),
-            )
-            .field(
-                "dma_apb_i_sram_3_r",
-                &format_args!("{}", self.dma_apb_i_sram_3_r().bit()),
-            )
-            .field(
-                "dma_apb_i_sram_3_w",
-                &format_args!("{}", self.dma_apb_i_sram_3_w().bit()),
-            )
+            .field("dma_apb_i_sram_0_r", &self.dma_apb_i_sram_0_r())
+            .field("dma_apb_i_sram_0_w", &self.dma_apb_i_sram_0_w())
+            .field("dma_apb_i_sram_1_r", &self.dma_apb_i_sram_1_r())
+            .field("dma_apb_i_sram_1_w", &self.dma_apb_i_sram_1_w())
+            .field("dma_apb_i_sram_2_r", &self.dma_apb_i_sram_2_r())
+            .field("dma_apb_i_sram_2_w", &self.dma_apb_i_sram_2_w())
+            .field("dma_apb_i_sram_3_r", &self.dma_apb_i_sram_3_r())
+            .field("dma_apb_i_sram_3_w", &self.dma_apb_i_sram_3_w())
             .field(
                 "dma_apb_i_sram_4_spltaddr",
-                &format_args!("{}", self.dma_apb_i_sram_4_spltaddr().bits()),
-            )
-            .field(
-                "dma_apb_i_sram_4_l_r",
-                &format_args!("{}", self.dma_apb_i_sram_4_l_r().bit()),
-            )
-            .field(
-                "dma_apb_i_sram_4_l_w",
-                &format_args!("{}", self.dma_apb_i_sram_4_l_w().bit()),
-            )
-            .field(
-                "dma_apb_i_sram_4_h_r",
-                &format_args!("{}", self.dma_apb_i_sram_4_h_r().bit()),
-            )
-            .field(
-                "dma_apb_i_sram_4_h_w",
-                &format_args!("{}", self.dma_apb_i_sram_4_h_w().bit()),
+                &self.dma_apb_i_sram_4_spltaddr(),
             )
+            .field("dma_apb_i_sram_4_l_r", &self.dma_apb_i_sram_4_l_r())
+            .field("dma_apb_i_sram_4_l_w", &self.dma_apb_i_sram_4_l_w())
+            .field("dma_apb_i_sram_4_h_r", &self.dma_apb_i_sram_4_h_r())
+            .field("dma_apb_i_sram_4_h_w", &self.dma_apb_i_sram_4_h_w())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APB_I_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Setting to 1 grants internal DMA permission to read SRAM Block 0."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/dma_apb_i_2.rs b/esp32s2/src/pms/dma_apb_i_2.rs
index cbb34a9ea7..b79febf213 100644
--- a/esp32s2/src/pms/dma_apb_i_2.rs
+++ b/esp32s2/src/pms/dma_apb_i_2.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_APB_I_2")
-            .field(
-                "dma_apb_i_ilg_clr",
-                &format_args!("{}", self.dma_apb_i_ilg_clr().bit()),
-            )
-            .field(
-                "dma_apb_i_ilg_en",
-                &format_args!("{}", self.dma_apb_i_ilg_en().bit()),
-            )
-            .field(
-                "dma_apb_i_ilg_intr",
-                &format_args!("{}", self.dma_apb_i_ilg_intr().bit()),
-            )
+            .field("dma_apb_i_ilg_clr", &self.dma_apb_i_ilg_clr())
+            .field("dma_apb_i_ilg_en", &self.dma_apb_i_ilg_en())
+            .field("dma_apb_i_ilg_intr", &self.dma_apb_i_ilg_intr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APB_I_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The clear signal for internal DMA access interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/dma_apb_i_3.rs b/esp32s2/src/pms/dma_apb_i_3.rs
index 02c17430e4..43ca2b1e4c 100644
--- a/esp32s2/src/pms/dma_apb_i_3.rs
+++ b/esp32s2/src/pms/dma_apb_i_3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_APB_I_3")
-            .field(
-                "dma_apb_i_ilg_st",
-                &format_args!("{}", self.dma_apb_i_ilg_st().bits()),
-            )
+            .field("dma_apb_i_ilg_st", &self.dma_apb_i_ilg_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APB_I_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Internal DMA status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_apb_i_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_APB_I_3_SPEC;
 impl crate::RegisterSpec for DMA_APB_I_3_SPEC {
diff --git a/esp32s2/src/pms/dma_rx_i_0.rs b/esp32s2/src/pms/dma_rx_i_0.rs
index 3c85a0b23c..4e09b3c3fc 100644
--- a/esp32s2/src/pms/dma_rx_i_0.rs
+++ b/esp32s2/src/pms/dma_rx_i_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_RX_I_0")
-            .field(
-                "dma_rx_i_lock",
-                &format_args!("{}", self.dma_rx_i_lock().bit()),
-            )
+            .field("dma_rx_i_lock", &self.dma_rx_i_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_RX_I_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks RX Copy DMA permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/dma_rx_i_1.rs b/esp32s2/src/pms/dma_rx_i_1.rs
index c1ed70f3f9..23a86c439f 100644
--- a/esp32s2/src/pms/dma_rx_i_1.rs
+++ b/esp32s2/src/pms/dma_rx_i_1.rs
@@ -125,67 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_RX_I_1")
-            .field(
-                "dma_rx_i_sram_0_r",
-                &format_args!("{}", self.dma_rx_i_sram_0_r().bit()),
-            )
-            .field(
-                "dma_rx_i_sram_0_w",
-                &format_args!("{}", self.dma_rx_i_sram_0_w().bit()),
-            )
-            .field(
-                "dma_rx_i_sram_1_r",
-                &format_args!("{}", self.dma_rx_i_sram_1_r().bit()),
-            )
-            .field(
-                "dma_rx_i_sram_1_w",
-                &format_args!("{}", self.dma_rx_i_sram_1_w().bit()),
-            )
-            .field(
-                "dma_rx_i_sram_2_r",
-                &format_args!("{}", self.dma_rx_i_sram_2_r().bit()),
-            )
-            .field(
-                "dma_rx_i_sram_2_w",
-                &format_args!("{}", self.dma_rx_i_sram_2_w().bit()),
-            )
-            .field(
-                "dma_rx_i_sram_3_r",
-                &format_args!("{}", self.dma_rx_i_sram_3_r().bit()),
-            )
-            .field(
-                "dma_rx_i_sram_3_w",
-                &format_args!("{}", self.dma_rx_i_sram_3_w().bit()),
-            )
-            .field(
-                "dma_rx_i_sram_4_spltaddr",
-                &format_args!("{}", self.dma_rx_i_sram_4_spltaddr().bits()),
-            )
-            .field(
-                "dma_rx_i_sram_4_l_r",
-                &format_args!("{}", self.dma_rx_i_sram_4_l_r().bit()),
-            )
-            .field(
-                "dma_rx_i_sram_4_l_w",
-                &format_args!("{}", self.dma_rx_i_sram_4_l_w().bit()),
-            )
-            .field(
-                "dma_rx_i_sram_4_h_r",
-                &format_args!("{}", self.dma_rx_i_sram_4_h_r().bit()),
-            )
-            .field(
-                "dma_rx_i_sram_4_h_w",
-                &format_args!("{}", self.dma_rx_i_sram_4_h_w().bit()),
-            )
+            .field("dma_rx_i_sram_0_r", &self.dma_rx_i_sram_0_r())
+            .field("dma_rx_i_sram_0_w", &self.dma_rx_i_sram_0_w())
+            .field("dma_rx_i_sram_1_r", &self.dma_rx_i_sram_1_r())
+            .field("dma_rx_i_sram_1_w", &self.dma_rx_i_sram_1_w())
+            .field("dma_rx_i_sram_2_r", &self.dma_rx_i_sram_2_r())
+            .field("dma_rx_i_sram_2_w", &self.dma_rx_i_sram_2_w())
+            .field("dma_rx_i_sram_3_r", &self.dma_rx_i_sram_3_r())
+            .field("dma_rx_i_sram_3_w", &self.dma_rx_i_sram_3_w())
+            .field("dma_rx_i_sram_4_spltaddr", &self.dma_rx_i_sram_4_spltaddr())
+            .field("dma_rx_i_sram_4_l_r", &self.dma_rx_i_sram_4_l_r())
+            .field("dma_rx_i_sram_4_l_w", &self.dma_rx_i_sram_4_l_w())
+            .field("dma_rx_i_sram_4_h_r", &self.dma_rx_i_sram_4_h_r())
+            .field("dma_rx_i_sram_4_h_w", &self.dma_rx_i_sram_4_h_w())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_RX_I_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Setting to 1 grants RX Copy DMA permission to read SRAM Block 0."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/dma_rx_i_2.rs b/esp32s2/src/pms/dma_rx_i_2.rs
index 51dad455de..0b34508f04 100644
--- a/esp32s2/src/pms/dma_rx_i_2.rs
+++ b/esp32s2/src/pms/dma_rx_i_2.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_RX_I_2")
-            .field(
-                "dma_rx_i_ilg_clr",
-                &format_args!("{}", self.dma_rx_i_ilg_clr().bit()),
-            )
-            .field(
-                "dma_rx_i_ilg_en",
-                &format_args!("{}", self.dma_rx_i_ilg_en().bit()),
-            )
-            .field(
-                "dma_rx_i_ilg_intr",
-                &format_args!("{}", self.dma_rx_i_ilg_intr().bit()),
-            )
+            .field("dma_rx_i_ilg_clr", &self.dma_rx_i_ilg_clr())
+            .field("dma_rx_i_ilg_en", &self.dma_rx_i_ilg_en())
+            .field("dma_rx_i_ilg_intr", &self.dma_rx_i_ilg_intr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_RX_I_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The clear signal for RX Copy DMA access interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/dma_rx_i_3.rs b/esp32s2/src/pms/dma_rx_i_3.rs
index 55b4025c61..22987bf2d2 100644
--- a/esp32s2/src/pms/dma_rx_i_3.rs
+++ b/esp32s2/src/pms/dma_rx_i_3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_RX_I_3")
-            .field(
-                "dma_rx_i_ilg_st",
-                &format_args!("{}", self.dma_rx_i_ilg_st().bits()),
-            )
+            .field("dma_rx_i_ilg_st", &self.dma_rx_i_ilg_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_RX_I_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX Copy DMA status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_rx_i_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_RX_I_3_SPEC;
 impl crate::RegisterSpec for DMA_RX_I_3_SPEC {
diff --git a/esp32s2/src/pms/dma_tx_i_0.rs b/esp32s2/src/pms/dma_tx_i_0.rs
index cedcc374e6..501a2be654 100644
--- a/esp32s2/src/pms/dma_tx_i_0.rs
+++ b/esp32s2/src/pms/dma_tx_i_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_TX_I_0")
-            .field(
-                "dma_tx_i_lock",
-                &format_args!("{}", self.dma_tx_i_lock().bit()),
-            )
+            .field("dma_tx_i_lock", &self.dma_tx_i_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_TX_I_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks TX Copy DMA permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/dma_tx_i_1.rs b/esp32s2/src/pms/dma_tx_i_1.rs
index 694677d0be..9d2cc3a2e7 100644
--- a/esp32s2/src/pms/dma_tx_i_1.rs
+++ b/esp32s2/src/pms/dma_tx_i_1.rs
@@ -125,67 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_TX_I_1")
-            .field(
-                "dma_tx_i_sram_0_r",
-                &format_args!("{}", self.dma_tx_i_sram_0_r().bit()),
-            )
-            .field(
-                "dma_tx_i_sram_0_w",
-                &format_args!("{}", self.dma_tx_i_sram_0_w().bit()),
-            )
-            .field(
-                "dma_tx_i_sram_1_r",
-                &format_args!("{}", self.dma_tx_i_sram_1_r().bit()),
-            )
-            .field(
-                "dma_tx_i_sram_1_w",
-                &format_args!("{}", self.dma_tx_i_sram_1_w().bit()),
-            )
-            .field(
-                "dma_tx_i_sram_2_r",
-                &format_args!("{}", self.dma_tx_i_sram_2_r().bit()),
-            )
-            .field(
-                "dma_tx_i_sram_2_w",
-                &format_args!("{}", self.dma_tx_i_sram_2_w().bit()),
-            )
-            .field(
-                "dma_tx_i_sram_3_r",
-                &format_args!("{}", self.dma_tx_i_sram_3_r().bit()),
-            )
-            .field(
-                "dma_tx_i_sram_3_w",
-                &format_args!("{}", self.dma_tx_i_sram_3_w().bit()),
-            )
-            .field(
-                "dma_tx_i_sram_4_spltaddr",
-                &format_args!("{}", self.dma_tx_i_sram_4_spltaddr().bits()),
-            )
-            .field(
-                "dma_tx_i_sram_4_l_r",
-                &format_args!("{}", self.dma_tx_i_sram_4_l_r().bit()),
-            )
-            .field(
-                "dma_tx_i_sram_4_l_w",
-                &format_args!("{}", self.dma_tx_i_sram_4_l_w().bit()),
-            )
-            .field(
-                "dma_tx_i_sram_4_h_r",
-                &format_args!("{}", self.dma_tx_i_sram_4_h_r().bit()),
-            )
-            .field(
-                "dma_tx_i_sram_4_h_w",
-                &format_args!("{}", self.dma_tx_i_sram_4_h_w().bit()),
-            )
+            .field("dma_tx_i_sram_0_r", &self.dma_tx_i_sram_0_r())
+            .field("dma_tx_i_sram_0_w", &self.dma_tx_i_sram_0_w())
+            .field("dma_tx_i_sram_1_r", &self.dma_tx_i_sram_1_r())
+            .field("dma_tx_i_sram_1_w", &self.dma_tx_i_sram_1_w())
+            .field("dma_tx_i_sram_2_r", &self.dma_tx_i_sram_2_r())
+            .field("dma_tx_i_sram_2_w", &self.dma_tx_i_sram_2_w())
+            .field("dma_tx_i_sram_3_r", &self.dma_tx_i_sram_3_r())
+            .field("dma_tx_i_sram_3_w", &self.dma_tx_i_sram_3_w())
+            .field("dma_tx_i_sram_4_spltaddr", &self.dma_tx_i_sram_4_spltaddr())
+            .field("dma_tx_i_sram_4_l_r", &self.dma_tx_i_sram_4_l_r())
+            .field("dma_tx_i_sram_4_l_w", &self.dma_tx_i_sram_4_l_w())
+            .field("dma_tx_i_sram_4_h_r", &self.dma_tx_i_sram_4_h_r())
+            .field("dma_tx_i_sram_4_h_w", &self.dma_tx_i_sram_4_h_w())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_TX_I_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Setting to 1 grants TX Copy DMA permission to read SRAM Block 0."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/dma_tx_i_2.rs b/esp32s2/src/pms/dma_tx_i_2.rs
index ead1211e0a..f2a79ac358 100644
--- a/esp32s2/src/pms/dma_tx_i_2.rs
+++ b/esp32s2/src/pms/dma_tx_i_2.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_TX_I_2")
-            .field(
-                "dma_tx_i_ilg_clr",
-                &format_args!("{}", self.dma_tx_i_ilg_clr().bit()),
-            )
-            .field(
-                "dma_tx_i_ilg_en",
-                &format_args!("{}", self.dma_tx_i_ilg_en().bit()),
-            )
-            .field(
-                "dma_tx_i_ilg_intr",
-                &format_args!("{}", self.dma_tx_i_ilg_intr().bit()),
-            )
+            .field("dma_tx_i_ilg_clr", &self.dma_tx_i_ilg_clr())
+            .field("dma_tx_i_ilg_en", &self.dma_tx_i_ilg_en())
+            .field("dma_tx_i_ilg_intr", &self.dma_tx_i_ilg_intr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_TX_I_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The clear signal for TX Copy DMA access interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/dma_tx_i_3.rs b/esp32s2/src/pms/dma_tx_i_3.rs
index eed7486a65..3726591bed 100644
--- a/esp32s2/src/pms/dma_tx_i_3.rs
+++ b/esp32s2/src/pms/dma_tx_i_3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_TX_I_3")
-            .field(
-                "dma_tx_i_ilg_st",
-                &format_args!("{}", self.dma_tx_i_ilg_st().bits()),
-            )
+            .field("dma_tx_i_ilg_st", &self.dma_tx_i_ilg_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_TX_I_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TX Copy DMA status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_tx_i_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_TX_I_3_SPEC;
 impl crate::RegisterSpec for DMA_TX_I_3_SPEC {
diff --git a/esp32s2/src/pms/mac_dump_0.rs b/esp32s2/src/pms/mac_dump_0.rs
index 92022ca567..e25610491a 100644
--- a/esp32s2/src/pms/mac_dump_0.rs
+++ b/esp32s2/src/pms/mac_dump_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAC_DUMP_0")
-            .field(
-                "mac_dump_lock",
-                &format_args!("{}", self.mac_dump_lock().bit()),
-            )
+            .field("mac_dump_lock", &self.mac_dump_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAC_DUMP_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks MAC dump permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/mac_dump_1.rs b/esp32s2/src/pms/mac_dump_1.rs
index cd50fcb237..d1cb447124 100644
--- a/esp32s2/src/pms/mac_dump_1.rs
+++ b/esp32s2/src/pms/mac_dump_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAC_DUMP_1")
-            .field(
-                "mac_dump_connect",
-                &format_args!("{}", self.mac_dump_connect().bits()),
-            )
+            .field("mac_dump_connect", &self.mac_dump_connect())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAC_DUMP_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - Configure MAC dump connection."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/occupy_0.rs b/esp32s2/src/pms/occupy_0.rs
index 0497c9786b..dae7cde986 100644
--- a/esp32s2/src/pms/occupy_0.rs
+++ b/esp32s2/src/pms/occupy_0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OCCUPY_0")
-            .field("occupy_lock", &format_args!("{}", self.occupy_lock().bit()))
+            .field("occupy_lock", &self.occupy_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OCCUPY_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks occupy permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/occupy_1.rs b/esp32s2/src/pms/occupy_1.rs
index a9b88475a9..82f967257f 100644
--- a/esp32s2/src/pms/occupy_1.rs
+++ b/esp32s2/src/pms/occupy_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OCCUPY_1")
-            .field(
-                "occupy_cache",
-                &format_args!("{}", self.occupy_cache().bits()),
-            )
+            .field("occupy_cache", &self.occupy_cache())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OCCUPY_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Configure whether SRAM Block 0-3 is used as cache memory."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/occupy_2.rs b/esp32s2/src/pms/occupy_2.rs
index 60eae9f469..776f279387 100644
--- a/esp32s2/src/pms/occupy_2.rs
+++ b/esp32s2/src/pms/occupy_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OCCUPY_2")
-            .field(
-                "occupy_mac_dump",
-                &format_args!("{}", self.occupy_mac_dump().bits()),
-            )
+            .field("occupy_mac_dump", &self.occupy_mac_dump())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OCCUPY_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Configure whether SRAM Block 18-21 is used as mac dump."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/occupy_3.rs b/esp32s2/src/pms/occupy_3.rs
index e84b99c173..5c4eb88474 100644
--- a/esp32s2/src/pms/occupy_3.rs
+++ b/esp32s2/src/pms/occupy_3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OCCUPY_3")
-            .field(
-                "occupy_pro_trace",
-                &format_args!("{}", self.occupy_pro_trace().bits()),
-            )
+            .field("occupy_pro_trace", &self.occupy_pro_trace())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OCCUPY_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - Configure one block of SRAM Block 4-21 is used as trace memory."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_ahb_0.rs b/esp32s2/src/pms/pro_ahb_0.rs
index 977450643b..68e2b01683 100644
--- a/esp32s2/src/pms/pro_ahb_0.rs
+++ b/esp32s2/src/pms/pro_ahb_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_AHB_0")
-            .field(
-                "pro_ahb_lock",
-                &format_args!("{}", self.pro_ahb_lock().bit()),
-            )
+            .field("pro_ahb_lock", &self.pro_ahb_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_AHB_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks PeriBus2 permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_ahb_1.rs b/esp32s2/src/pms/pro_ahb_1.rs
index 454089018c..8fa9496b2b 100644
--- a/esp32s2/src/pms/pro_ahb_1.rs
+++ b/esp32s2/src/pms/pro_ahb_1.rs
@@ -73,41 +73,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_AHB_1")
             .field(
                 "pro_ahb_rtcslow_0_spltaddr",
-                &format_args!("{}", self.pro_ahb_rtcslow_0_spltaddr().bits()),
-            )
-            .field(
-                "pro_ahb_rtcslow_0_l_f",
-                &format_args!("{}", self.pro_ahb_rtcslow_0_l_f().bit()),
-            )
-            .field(
-                "pro_ahb_rtcslow_0_l_r",
-                &format_args!("{}", self.pro_ahb_rtcslow_0_l_r().bit()),
-            )
-            .field(
-                "pro_ahb_rtcslow_0_l_w",
-                &format_args!("{}", self.pro_ahb_rtcslow_0_l_w().bit()),
-            )
-            .field(
-                "pro_ahb_rtcslow_0_h_f",
-                &format_args!("{}", self.pro_ahb_rtcslow_0_h_f().bit()),
-            )
-            .field(
-                "pro_ahb_rtcslow_0_h_r",
-                &format_args!("{}", self.pro_ahb_rtcslow_0_h_r().bit()),
-            )
-            .field(
-                "pro_ahb_rtcslow_0_h_w",
-                &format_args!("{}", self.pro_ahb_rtcslow_0_h_w().bit()),
+                &self.pro_ahb_rtcslow_0_spltaddr(),
             )
+            .field("pro_ahb_rtcslow_0_l_f", &self.pro_ahb_rtcslow_0_l_f())
+            .field("pro_ahb_rtcslow_0_l_r", &self.pro_ahb_rtcslow_0_l_r())
+            .field("pro_ahb_rtcslow_0_l_w", &self.pro_ahb_rtcslow_0_l_w())
+            .field("pro_ahb_rtcslow_0_h_f", &self.pro_ahb_rtcslow_0_h_f())
+            .field("pro_ahb_rtcslow_0_h_r", &self.pro_ahb_rtcslow_0_h_r())
+            .field("pro_ahb_rtcslow_0_h_w", &self.pro_ahb_rtcslow_0_h_w())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_AHB_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - Configure the split address of RTCSlow_0 for PeriBus2 access."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_ahb_2.rs b/esp32s2/src/pms/pro_ahb_2.rs
index 191ccb20ce..859cd7a1ba 100644
--- a/esp32s2/src/pms/pro_ahb_2.rs
+++ b/esp32s2/src/pms/pro_ahb_2.rs
@@ -73,41 +73,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_AHB_2")
             .field(
                 "pro_ahb_rtcslow_1_spltaddr",
-                &format_args!("{}", self.pro_ahb_rtcslow_1_spltaddr().bits()),
-            )
-            .field(
-                "pro_ahb_rtcslow_1_l_f",
-                &format_args!("{}", self.pro_ahb_rtcslow_1_l_f().bit()),
-            )
-            .field(
-                "pro_ahb_rtcslow_1_l_r",
-                &format_args!("{}", self.pro_ahb_rtcslow_1_l_r().bit()),
-            )
-            .field(
-                "pro_ahb_rtcslow_1_l_w",
-                &format_args!("{}", self.pro_ahb_rtcslow_1_l_w().bit()),
-            )
-            .field(
-                "pro_ahb_rtcslow_1_h_f",
-                &format_args!("{}", self.pro_ahb_rtcslow_1_h_f().bit()),
-            )
-            .field(
-                "pro_ahb_rtcslow_1_h_r",
-                &format_args!("{}", self.pro_ahb_rtcslow_1_h_r().bit()),
-            )
-            .field(
-                "pro_ahb_rtcslow_1_h_w",
-                &format_args!("{}", self.pro_ahb_rtcslow_1_h_w().bit()),
+                &self.pro_ahb_rtcslow_1_spltaddr(),
             )
+            .field("pro_ahb_rtcslow_1_l_f", &self.pro_ahb_rtcslow_1_l_f())
+            .field("pro_ahb_rtcslow_1_l_r", &self.pro_ahb_rtcslow_1_l_r())
+            .field("pro_ahb_rtcslow_1_l_w", &self.pro_ahb_rtcslow_1_l_w())
+            .field("pro_ahb_rtcslow_1_h_f", &self.pro_ahb_rtcslow_1_h_f())
+            .field("pro_ahb_rtcslow_1_h_r", &self.pro_ahb_rtcslow_1_h_r())
+            .field("pro_ahb_rtcslow_1_h_w", &self.pro_ahb_rtcslow_1_h_w())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_AHB_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - Configure the split address of RTCSlow_1 for PeriBus2 access."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_ahb_3.rs b/esp32s2/src/pms/pro_ahb_3.rs
index 5d59a3514e..7303872c79 100644
--- a/esp32s2/src/pms/pro_ahb_3.rs
+++ b/esp32s2/src/pms/pro_ahb_3.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_AHB_3")
-            .field(
-                "pro_ahb_ilg_clr",
-                &format_args!("{}", self.pro_ahb_ilg_clr().bit()),
-            )
-            .field(
-                "pro_ahb_ilg_en",
-                &format_args!("{}", self.pro_ahb_ilg_en().bit()),
-            )
-            .field(
-                "pro_ahb_ilg_intr",
-                &format_args!("{}", self.pro_ahb_ilg_intr().bit()),
-            )
+            .field("pro_ahb_ilg_clr", &self.pro_ahb_ilg_clr())
+            .field("pro_ahb_ilg_en", &self.pro_ahb_ilg_en())
+            .field("pro_ahb_ilg_intr", &self.pro_ahb_ilg_intr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_AHB_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The clear signal for PeriBus2 access interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_ahb_4.rs b/esp32s2/src/pms/pro_ahb_4.rs
index d370b7fcb0..8faae7e4c2 100644
--- a/esp32s2/src/pms/pro_ahb_4.rs
+++ b/esp32s2/src/pms/pro_ahb_4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_AHB_4")
-            .field(
-                "pro_ahb_ilg_st",
-                &format_args!("{}", self.pro_ahb_ilg_st().bits()),
-            )
+            .field("pro_ahb_ilg_st", &self.pro_ahb_ilg_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_AHB_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "PeriBus2 status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_ahb_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_AHB_4_SPEC;
 impl crate::RegisterSpec for PRO_AHB_4_SPEC {
diff --git a/esp32s2/src/pms/pro_boot_location_0.rs b/esp32s2/src/pms/pro_boot_location_0.rs
index 9b6c77d3a1..04e841025f 100644
--- a/esp32s2/src/pms/pro_boot_location_0.rs
+++ b/esp32s2/src/pms/pro_boot_location_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_BOOT_LOCATION_0")
-            .field(
-                "pro_boot_location_lock",
-                &format_args!("{}", self.pro_boot_location_lock().bit()),
-            )
+            .field("pro_boot_location_lock", &self.pro_boot_location_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_BOOT_LOCATION_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks boot remap permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_boot_location_1.rs b/esp32s2/src/pms/pro_boot_location_1.rs
index 02f27e5191..601d958cd1 100644
--- a/esp32s2/src/pms/pro_boot_location_1.rs
+++ b/esp32s2/src/pms/pro_boot_location_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_BOOT_LOCATION_1")
-            .field(
-                "pro_boot_remap",
-                &format_args!("{}", self.pro_boot_remap().bit()),
-            )
+            .field("pro_boot_remap", &self.pro_boot_remap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_BOOT_LOCATION_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - If set to 1, enable boot remap function."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_cache_0.rs b/esp32s2/src/pms/pro_cache_0.rs
index 20245b9e0b..828a6947af 100644
--- a/esp32s2/src/pms/pro_cache_0.rs
+++ b/esp32s2/src/pms/pro_cache_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CACHE_0")
-            .field(
-                "pro_cache_lock",
-                &format_args!("{}", self.pro_cache_lock().bit()),
-            )
+            .field("pro_cache_lock", &self.pro_cache_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks cache permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_cache_1.rs b/esp32s2/src/pms/pro_cache_1.rs
index 010469c9af..0adcb35bf9 100644
--- a/esp32s2/src/pms/pro_cache_1.rs
+++ b/esp32s2/src/pms/pro_cache_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CACHE_1")
-            .field(
-                "pro_cache_connect",
-                &format_args!("{}", self.pro_cache_connect().bits()),
-            )
+            .field("pro_cache_connect", &self.pro_cache_connect())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configure which SRAM Block will be occupied by Icache or Dcache."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_cache_2.rs b/esp32s2/src/pms/pro_cache_2.rs
index 5fc473ea0f..7dad97d91c 100644
--- a/esp32s2/src/pms/pro_cache_2.rs
+++ b/esp32s2/src/pms/pro_cache_2.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CACHE_2")
-            .field(
-                "pro_cache_ilg_clr",
-                &format_args!("{}", self.pro_cache_ilg_clr().bit()),
-            )
-            .field(
-                "pro_cache_ilg_en",
-                &format_args!("{}", self.pro_cache_ilg_en().bit()),
-            )
-            .field(
-                "pro_cache_ilg_intr",
-                &format_args!("{}", self.pro_cache_ilg_intr().bit()),
-            )
+            .field("pro_cache_ilg_clr", &self.pro_cache_ilg_clr())
+            .field("pro_cache_ilg_en", &self.pro_cache_ilg_en())
+            .field("pro_cache_ilg_intr", &self.pro_cache_ilg_intr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The clear signal for cache access interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_cache_3.rs b/esp32s2/src/pms/pro_cache_3.rs
index 2056003d50..5aee58d6b0 100644
--- a/esp32s2/src/pms/pro_cache_3.rs
+++ b/esp32s2/src/pms/pro_cache_3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CACHE_3")
-            .field(
-                "pro_cache_ilg_st_i",
-                &format_args!("{}", self.pro_cache_ilg_st_i().bits()),
-            )
+            .field("pro_cache_ilg_st_i", &self.pro_cache_ilg_st_i())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Icache status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_cache_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_CACHE_3_SPEC;
 impl crate::RegisterSpec for PRO_CACHE_3_SPEC {
diff --git a/esp32s2/src/pms/pro_cache_4.rs b/esp32s2/src/pms/pro_cache_4.rs
index bb826d0658..a5ded074c8 100644
--- a/esp32s2/src/pms/pro_cache_4.rs
+++ b/esp32s2/src/pms/pro_cache_4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_CACHE_4")
-            .field(
-                "pro_cache_ilg_st_d",
-                &format_args!("{}", self.pro_cache_ilg_st_d().bits()),
-            )
+            .field("pro_cache_ilg_st_d", &self.pro_cache_ilg_st_d())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_CACHE_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Dcache status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_cache_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_CACHE_4_SPEC;
 impl crate::RegisterSpec for PRO_CACHE_4_SPEC {
diff --git a/esp32s2/src/pms/pro_dport_0.rs b/esp32s2/src/pms/pro_dport_0.rs
index 5fafeb72e2..47559389de 100644
--- a/esp32s2/src/pms/pro_dport_0.rs
+++ b/esp32s2/src/pms/pro_dport_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DPORT_0")
-            .field(
-                "pro_dport_lock",
-                &format_args!("{}", self.pro_dport_lock().bit()),
-            )
+            .field("pro_dport_lock", &self.pro_dport_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DPORT_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks PeriBus1 permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_dport_1.rs b/esp32s2/src/pms/pro_dport_1.rs
index 7154a2ca5c..9e940ae4c8 100644
--- a/esp32s2/src/pms/pro_dport_1.rs
+++ b/esp32s2/src/pms/pro_dport_1.rs
@@ -73,41 +73,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_DPORT_1")
             .field(
                 "pro_dport_apb_peripheral_forbid",
-                &format_args!("{}", self.pro_dport_apb_peripheral_forbid().bit()),
+                &self.pro_dport_apb_peripheral_forbid(),
             )
             .field(
                 "pro_dport_rtcslow_spltaddr",
-                &format_args!("{}", self.pro_dport_rtcslow_spltaddr().bits()),
-            )
-            .field(
-                "pro_dport_rtcslow_l_r",
-                &format_args!("{}", self.pro_dport_rtcslow_l_r().bit()),
-            )
-            .field(
-                "pro_dport_rtcslow_l_w",
-                &format_args!("{}", self.pro_dport_rtcslow_l_w().bit()),
-            )
-            .field(
-                "pro_dport_rtcslow_h_r",
-                &format_args!("{}", self.pro_dport_rtcslow_h_r().bit()),
-            )
-            .field(
-                "pro_dport_rtcslow_h_w",
-                &format_args!("{}", self.pro_dport_rtcslow_h_w().bit()),
+                &self.pro_dport_rtcslow_spltaddr(),
             )
+            .field("pro_dport_rtcslow_l_r", &self.pro_dport_rtcslow_l_r())
+            .field("pro_dport_rtcslow_l_w", &self.pro_dport_rtcslow_l_w())
+            .field("pro_dport_rtcslow_h_r", &self.pro_dport_rtcslow_h_r())
+            .field("pro_dport_rtcslow_h_w", &self.pro_dport_rtcslow_h_w())
             .field(
                 "pro_dport_reserve_fifo_valid",
-                &format_args!("{}", self.pro_dport_reserve_fifo_valid().bits()),
+                &self.pro_dport_reserve_fifo_valid(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DPORT_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Setting to 1 denies PeriBus1 bus???s access to APB peripheral."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_dport_2.rs b/esp32s2/src/pms/pro_dport_2.rs
index 941c50dec1..03851dcacc 100644
--- a/esp32s2/src/pms/pro_dport_2.rs
+++ b/esp32s2/src/pms/pro_dport_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DPORT_2")
-            .field(
-                "pro_dport_reserve_fifo_0",
-                &format_args!("{}", self.pro_dport_reserve_fifo_0().bits()),
-            )
+            .field("pro_dport_reserve_fifo_0", &self.pro_dport_reserve_fifo_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DPORT_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - Configure read-protection address 0."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_dport_3.rs b/esp32s2/src/pms/pro_dport_3.rs
index f98a63da94..39dd3bcc3d 100644
--- a/esp32s2/src/pms/pro_dport_3.rs
+++ b/esp32s2/src/pms/pro_dport_3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DPORT_3")
-            .field(
-                "pro_dport_reserve_fifo_1",
-                &format_args!("{}", self.pro_dport_reserve_fifo_1().bits()),
-            )
+            .field("pro_dport_reserve_fifo_1", &self.pro_dport_reserve_fifo_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DPORT_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - Configure read-protection address 1."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_dport_4.rs b/esp32s2/src/pms/pro_dport_4.rs
index 0780f3d0fe..3f14dc9ba2 100644
--- a/esp32s2/src/pms/pro_dport_4.rs
+++ b/esp32s2/src/pms/pro_dport_4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DPORT_4")
-            .field(
-                "pro_dport_reserve_fifo_2",
-                &format_args!("{}", self.pro_dport_reserve_fifo_2().bits()),
-            )
+            .field("pro_dport_reserve_fifo_2", &self.pro_dport_reserve_fifo_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DPORT_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - Configure read-protection address 2."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_dport_5.rs b/esp32s2/src/pms/pro_dport_5.rs
index 776a480562..0143ccb518 100644
--- a/esp32s2/src/pms/pro_dport_5.rs
+++ b/esp32s2/src/pms/pro_dport_5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DPORT_5")
-            .field(
-                "pro_dport_reserve_fifo_3",
-                &format_args!("{}", self.pro_dport_reserve_fifo_3().bits()),
-            )
+            .field("pro_dport_reserve_fifo_3", &self.pro_dport_reserve_fifo_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DPORT_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - Configure read-protection address 3."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_dport_6.rs b/esp32s2/src/pms/pro_dport_6.rs
index e7c05fa846..49046cd5fc 100644
--- a/esp32s2/src/pms/pro_dport_6.rs
+++ b/esp32s2/src/pms/pro_dport_6.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DPORT_6")
-            .field(
-                "pro_dport_ilg_clr",
-                &format_args!("{}", self.pro_dport_ilg_clr().bit()),
-            )
-            .field(
-                "pro_dport_ilg_en",
-                &format_args!("{}", self.pro_dport_ilg_en().bit()),
-            )
-            .field(
-                "pro_dport_ilg_intr",
-                &format_args!("{}", self.pro_dport_ilg_intr().bit()),
-            )
+            .field("pro_dport_ilg_clr", &self.pro_dport_ilg_clr())
+            .field("pro_dport_ilg_en", &self.pro_dport_ilg_en())
+            .field("pro_dport_ilg_intr", &self.pro_dport_ilg_intr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DPORT_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The clear signal for PeriBus1 access interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_dport_7.rs b/esp32s2/src/pms/pro_dport_7.rs
index 84f94ebb33..c2f9f10ba1 100644
--- a/esp32s2/src/pms/pro_dport_7.rs
+++ b/esp32s2/src/pms/pro_dport_7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DPORT_7")
-            .field(
-                "pro_dport_ilg_st",
-                &format_args!("{}", self.pro_dport_ilg_st().bits()),
-            )
+            .field("pro_dport_ilg_st", &self.pro_dport_ilg_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DPORT_7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "PeriBus1 status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_dport_7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_DPORT_7_SPEC;
 impl crate::RegisterSpec for PRO_DPORT_7_SPEC {
diff --git a/esp32s2/src/pms/pro_dram0_0.rs b/esp32s2/src/pms/pro_dram0_0.rs
index 1f80af797d..e4775ea671 100644
--- a/esp32s2/src/pms/pro_dram0_0.rs
+++ b/esp32s2/src/pms/pro_dram0_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DRAM0_0")
-            .field(
-                "pro_dram0_lock",
-                &format_args!("{}", self.pro_dram0_lock().bit()),
-            )
+            .field("pro_dram0_lock", &self.pro_dram0_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DRAM0_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks DBUS0 permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_dram0_1.rs b/esp32s2/src/pms/pro_dram0_1.rs
index ee338460b8..6c013a9bd7 100644
--- a/esp32s2/src/pms/pro_dram0_1.rs
+++ b/esp32s2/src/pms/pro_dram0_1.rs
@@ -125,67 +125,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DRAM0_1")
-            .field(
-                "pro_dram0_sram_0_r",
-                &format_args!("{}", self.pro_dram0_sram_0_r().bit()),
-            )
-            .field(
-                "pro_dram0_sram_0_w",
-                &format_args!("{}", self.pro_dram0_sram_0_w().bit()),
-            )
-            .field(
-                "pro_dram0_sram_1_r",
-                &format_args!("{}", self.pro_dram0_sram_1_r().bit()),
-            )
-            .field(
-                "pro_dram0_sram_1_w",
-                &format_args!("{}", self.pro_dram0_sram_1_w().bit()),
-            )
-            .field(
-                "pro_dram0_sram_2_r",
-                &format_args!("{}", self.pro_dram0_sram_2_r().bit()),
-            )
-            .field(
-                "pro_dram0_sram_2_w",
-                &format_args!("{}", self.pro_dram0_sram_2_w().bit()),
-            )
-            .field(
-                "pro_dram0_sram_3_r",
-                &format_args!("{}", self.pro_dram0_sram_3_r().bit()),
-            )
-            .field(
-                "pro_dram0_sram_3_w",
-                &format_args!("{}", self.pro_dram0_sram_3_w().bit()),
-            )
+            .field("pro_dram0_sram_0_r", &self.pro_dram0_sram_0_r())
+            .field("pro_dram0_sram_0_w", &self.pro_dram0_sram_0_w())
+            .field("pro_dram0_sram_1_r", &self.pro_dram0_sram_1_r())
+            .field("pro_dram0_sram_1_w", &self.pro_dram0_sram_1_w())
+            .field("pro_dram0_sram_2_r", &self.pro_dram0_sram_2_r())
+            .field("pro_dram0_sram_2_w", &self.pro_dram0_sram_2_w())
+            .field("pro_dram0_sram_3_r", &self.pro_dram0_sram_3_r())
+            .field("pro_dram0_sram_3_w", &self.pro_dram0_sram_3_w())
             .field(
                 "pro_dram0_sram_4_spltaddr",
-                &format_args!("{}", self.pro_dram0_sram_4_spltaddr().bits()),
-            )
-            .field(
-                "pro_dram0_sram_4_l_r",
-                &format_args!("{}", self.pro_dram0_sram_4_l_r().bit()),
-            )
-            .field(
-                "pro_dram0_sram_4_l_w",
-                &format_args!("{}", self.pro_dram0_sram_4_l_w().bit()),
-            )
-            .field(
-                "pro_dram0_sram_4_h_r",
-                &format_args!("{}", self.pro_dram0_sram_4_h_r().bit()),
-            )
-            .field(
-                "pro_dram0_sram_4_h_w",
-                &format_args!("{}", self.pro_dram0_sram_4_h_w().bit()),
+                &self.pro_dram0_sram_4_spltaddr(),
             )
+            .field("pro_dram0_sram_4_l_r", &self.pro_dram0_sram_4_l_r())
+            .field("pro_dram0_sram_4_l_w", &self.pro_dram0_sram_4_l_w())
+            .field("pro_dram0_sram_4_h_r", &self.pro_dram0_sram_4_h_r())
+            .field("pro_dram0_sram_4_h_w", &self.pro_dram0_sram_4_h_w())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DRAM0_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Setting to 1 grants DBUS0 permission to read SRAM Block 0."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_dram0_2.rs b/esp32s2/src/pms/pro_dram0_2.rs
index d5767496cc..9fe369a235 100644
--- a/esp32s2/src/pms/pro_dram0_2.rs
+++ b/esp32s2/src/pms/pro_dram0_2.rs
@@ -55,33 +55,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_DRAM0_2")
             .field(
                 "pro_dram0_rtcfast_spltaddr",
-                &format_args!("{}", self.pro_dram0_rtcfast_spltaddr().bits()),
-            )
-            .field(
-                "pro_dram0_rtcfast_l_r",
-                &format_args!("{}", self.pro_dram0_rtcfast_l_r().bit()),
-            )
-            .field(
-                "pro_dram0_rtcfast_l_w",
-                &format_args!("{}", self.pro_dram0_rtcfast_l_w().bit()),
-            )
-            .field(
-                "pro_dram0_rtcfast_h_r",
-                &format_args!("{}", self.pro_dram0_rtcfast_h_r().bit()),
-            )
-            .field(
-                "pro_dram0_rtcfast_h_w",
-                &format_args!("{}", self.pro_dram0_rtcfast_h_w().bit()),
+                &self.pro_dram0_rtcfast_spltaddr(),
             )
+            .field("pro_dram0_rtcfast_l_r", &self.pro_dram0_rtcfast_l_r())
+            .field("pro_dram0_rtcfast_l_w", &self.pro_dram0_rtcfast_l_w())
+            .field("pro_dram0_rtcfast_h_r", &self.pro_dram0_rtcfast_h_r())
+            .field("pro_dram0_rtcfast_h_w", &self.pro_dram0_rtcfast_h_w())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DRAM0_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - Configure the split address of RTC FAST for DBUS0 access."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_dram0_3.rs b/esp32s2/src/pms/pro_dram0_3.rs
index e793dbf3d5..7d9c1905f7 100644
--- a/esp32s2/src/pms/pro_dram0_3.rs
+++ b/esp32s2/src/pms/pro_dram0_3.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DRAM0_3")
-            .field(
-                "pro_dram0_ilg_clr",
-                &format_args!("{}", self.pro_dram0_ilg_clr().bit()),
-            )
-            .field(
-                "pro_dram0_ilg_en",
-                &format_args!("{}", self.pro_dram0_ilg_en().bit()),
-            )
-            .field(
-                "pro_dram0_ilg_intr",
-                &format_args!("{}", self.pro_dram0_ilg_intr().bit()),
-            )
+            .field("pro_dram0_ilg_clr", &self.pro_dram0_ilg_clr())
+            .field("pro_dram0_ilg_en", &self.pro_dram0_ilg_en())
+            .field("pro_dram0_ilg_intr", &self.pro_dram0_ilg_intr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DRAM0_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The clear signal for DBUS0 access interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_dram0_4.rs b/esp32s2/src/pms/pro_dram0_4.rs
index 09bb0deea1..cf286ca9d3 100644
--- a/esp32s2/src/pms/pro_dram0_4.rs
+++ b/esp32s2/src/pms/pro_dram0_4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_DRAM0_4")
-            .field(
-                "pro_dram0_ilg_st",
-                &format_args!("{}", self.pro_dram0_ilg_st().bits()),
-            )
+            .field("pro_dram0_ilg_st", &self.pro_dram0_ilg_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_DRAM0_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DBUS status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_dram0_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_DRAM0_4_SPEC;
 impl crate::RegisterSpec for PRO_DRAM0_4_SPEC {
diff --git a/esp32s2/src/pms/pro_iram0_0.rs b/esp32s2/src/pms/pro_iram0_0.rs
index 302eba9f14..0e36d9d221 100644
--- a/esp32s2/src/pms/pro_iram0_0.rs
+++ b/esp32s2/src/pms/pro_iram0_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_IRAM0_0")
-            .field(
-                "pro_iram0_lock",
-                &format_args!("{}", self.pro_iram0_lock().bit()),
-            )
+            .field("pro_iram0_lock", &self.pro_iram0_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_IRAM0_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks IBUS permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_iram0_1.rs b/esp32s2/src/pms/pro_iram0_1.rs
index 91c551eee2..6b5605d739 100644
--- a/esp32s2/src/pms/pro_iram0_1.rs
+++ b/esp32s2/src/pms/pro_iram0_1.rs
@@ -116,63 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_IRAM0_1")
-            .field(
-                "pro_iram0_sram_0_f",
-                &format_args!("{}", self.pro_iram0_sram_0_f().bit()),
-            )
-            .field(
-                "pro_iram0_sram_0_r",
-                &format_args!("{}", self.pro_iram0_sram_0_r().bit()),
-            )
-            .field(
-                "pro_iram0_sram_0_w",
-                &format_args!("{}", self.pro_iram0_sram_0_w().bit()),
-            )
-            .field(
-                "pro_iram0_sram_1_f",
-                &format_args!("{}", self.pro_iram0_sram_1_f().bit()),
-            )
-            .field(
-                "pro_iram0_sram_1_r",
-                &format_args!("{}", self.pro_iram0_sram_1_r().bit()),
-            )
-            .field(
-                "pro_iram0_sram_1_w",
-                &format_args!("{}", self.pro_iram0_sram_1_w().bit()),
-            )
-            .field(
-                "pro_iram0_sram_2_f",
-                &format_args!("{}", self.pro_iram0_sram_2_f().bit()),
-            )
-            .field(
-                "pro_iram0_sram_2_r",
-                &format_args!("{}", self.pro_iram0_sram_2_r().bit()),
-            )
-            .field(
-                "pro_iram0_sram_2_w",
-                &format_args!("{}", self.pro_iram0_sram_2_w().bit()),
-            )
-            .field(
-                "pro_iram0_sram_3_f",
-                &format_args!("{}", self.pro_iram0_sram_3_f().bit()),
-            )
-            .field(
-                "pro_iram0_sram_3_r",
-                &format_args!("{}", self.pro_iram0_sram_3_r().bit()),
-            )
-            .field(
-                "pro_iram0_sram_3_w",
-                &format_args!("{}", self.pro_iram0_sram_3_w().bit()),
-            )
+            .field("pro_iram0_sram_0_f", &self.pro_iram0_sram_0_f())
+            .field("pro_iram0_sram_0_r", &self.pro_iram0_sram_0_r())
+            .field("pro_iram0_sram_0_w", &self.pro_iram0_sram_0_w())
+            .field("pro_iram0_sram_1_f", &self.pro_iram0_sram_1_f())
+            .field("pro_iram0_sram_1_r", &self.pro_iram0_sram_1_r())
+            .field("pro_iram0_sram_1_w", &self.pro_iram0_sram_1_w())
+            .field("pro_iram0_sram_2_f", &self.pro_iram0_sram_2_f())
+            .field("pro_iram0_sram_2_r", &self.pro_iram0_sram_2_r())
+            .field("pro_iram0_sram_2_w", &self.pro_iram0_sram_2_w())
+            .field("pro_iram0_sram_3_f", &self.pro_iram0_sram_3_f())
+            .field("pro_iram0_sram_3_r", &self.pro_iram0_sram_3_r())
+            .field("pro_iram0_sram_3_w", &self.pro_iram0_sram_3_w())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_IRAM0_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Setting to 1 grants IBUS permission to fetch SRAM Block 0."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_iram0_2.rs b/esp32s2/src/pms/pro_iram0_2.rs
index 5b3ca7e589..f3439491ed 100644
--- a/esp32s2/src/pms/pro_iram0_2.rs
+++ b/esp32s2/src/pms/pro_iram0_2.rs
@@ -73,41 +73,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_IRAM0_2")
             .field(
                 "pro_iram0_sram_4_spltaddr",
-                &format_args!("{}", self.pro_iram0_sram_4_spltaddr().bits()),
-            )
-            .field(
-                "pro_iram0_sram_4_l_f",
-                &format_args!("{}", self.pro_iram0_sram_4_l_f().bit()),
-            )
-            .field(
-                "pro_iram0_sram_4_l_r",
-                &format_args!("{}", self.pro_iram0_sram_4_l_r().bit()),
-            )
-            .field(
-                "pro_iram0_sram_4_l_w",
-                &format_args!("{}", self.pro_iram0_sram_4_l_w().bit()),
-            )
-            .field(
-                "pro_iram0_sram_4_h_f",
-                &format_args!("{}", self.pro_iram0_sram_4_h_f().bit()),
-            )
-            .field(
-                "pro_iram0_sram_4_h_r",
-                &format_args!("{}", self.pro_iram0_sram_4_h_r().bit()),
-            )
-            .field(
-                "pro_iram0_sram_4_h_w",
-                &format_args!("{}", self.pro_iram0_sram_4_h_w().bit()),
+                &self.pro_iram0_sram_4_spltaddr(),
             )
+            .field("pro_iram0_sram_4_l_f", &self.pro_iram0_sram_4_l_f())
+            .field("pro_iram0_sram_4_l_r", &self.pro_iram0_sram_4_l_r())
+            .field("pro_iram0_sram_4_l_w", &self.pro_iram0_sram_4_l_w())
+            .field("pro_iram0_sram_4_h_f", &self.pro_iram0_sram_4_h_f())
+            .field("pro_iram0_sram_4_h_r", &self.pro_iram0_sram_4_h_r())
+            .field("pro_iram0_sram_4_h_w", &self.pro_iram0_sram_4_h_w())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_IRAM0_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:16 - Configure the split address of SRAM Block 4-21 for IBUS access."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_iram0_3.rs b/esp32s2/src/pms/pro_iram0_3.rs
index ebad8972ed..8f9572372f 100644
--- a/esp32s2/src/pms/pro_iram0_3.rs
+++ b/esp32s2/src/pms/pro_iram0_3.rs
@@ -73,41 +73,17 @@ impl core::fmt::Debug for R {
         f.debug_struct("PRO_IRAM0_3")
             .field(
                 "pro_iram0_rtcfast_spltaddr",
-                &format_args!("{}", self.pro_iram0_rtcfast_spltaddr().bits()),
-            )
-            .field(
-                "pro_iram0_rtcfast_l_f",
-                &format_args!("{}", self.pro_iram0_rtcfast_l_f().bit()),
-            )
-            .field(
-                "pro_iram0_rtcfast_l_r",
-                &format_args!("{}", self.pro_iram0_rtcfast_l_r().bit()),
-            )
-            .field(
-                "pro_iram0_rtcfast_l_w",
-                &format_args!("{}", self.pro_iram0_rtcfast_l_w().bit()),
-            )
-            .field(
-                "pro_iram0_rtcfast_h_f",
-                &format_args!("{}", self.pro_iram0_rtcfast_h_f().bit()),
-            )
-            .field(
-                "pro_iram0_rtcfast_h_r",
-                &format_args!("{}", self.pro_iram0_rtcfast_h_r().bit()),
-            )
-            .field(
-                "pro_iram0_rtcfast_h_w",
-                &format_args!("{}", self.pro_iram0_rtcfast_h_w().bit()),
+                &self.pro_iram0_rtcfast_spltaddr(),
             )
+            .field("pro_iram0_rtcfast_l_f", &self.pro_iram0_rtcfast_l_f())
+            .field("pro_iram0_rtcfast_l_r", &self.pro_iram0_rtcfast_l_r())
+            .field("pro_iram0_rtcfast_l_w", &self.pro_iram0_rtcfast_l_w())
+            .field("pro_iram0_rtcfast_h_f", &self.pro_iram0_rtcfast_h_f())
+            .field("pro_iram0_rtcfast_h_r", &self.pro_iram0_rtcfast_h_r())
+            .field("pro_iram0_rtcfast_h_w", &self.pro_iram0_rtcfast_h_w())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_IRAM0_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - Configure the split address of RTC FAST for IBUS access."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_iram0_4.rs b/esp32s2/src/pms/pro_iram0_4.rs
index 250218d104..f0f97024b4 100644
--- a/esp32s2/src/pms/pro_iram0_4.rs
+++ b/esp32s2/src/pms/pro_iram0_4.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_IRAM0_4")
-            .field(
-                "pro_iram0_ilg_clr",
-                &format_args!("{}", self.pro_iram0_ilg_clr().bit()),
-            )
-            .field(
-                "pro_iram0_ilg_en",
-                &format_args!("{}", self.pro_iram0_ilg_en().bit()),
-            )
-            .field(
-                "pro_iram0_ilg_intr",
-                &format_args!("{}", self.pro_iram0_ilg_intr().bit()),
-            )
+            .field("pro_iram0_ilg_clr", &self.pro_iram0_ilg_clr())
+            .field("pro_iram0_ilg_en", &self.pro_iram0_ilg_en())
+            .field("pro_iram0_ilg_intr", &self.pro_iram0_ilg_intr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_IRAM0_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The clear signal for IBUS access interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_iram0_5.rs b/esp32s2/src/pms/pro_iram0_5.rs
index bdd16b3692..ed12e39334 100644
--- a/esp32s2/src/pms/pro_iram0_5.rs
+++ b/esp32s2/src/pms/pro_iram0_5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_IRAM0_5")
-            .field(
-                "pro_iram0_ilg_st",
-                &format_args!("{}", self.pro_iram0_ilg_st().bits()),
-            )
+            .field("pro_iram0_ilg_st", &self.pro_iram0_ilg_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_IRAM0_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "IBUS status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_iram0_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_IRAM0_5_SPEC;
 impl crate::RegisterSpec for PRO_IRAM0_5_SPEC {
diff --git a/esp32s2/src/pms/pro_trace_0.rs b/esp32s2/src/pms/pro_trace_0.rs
index d134bcb63d..3b5acdadca 100644
--- a/esp32s2/src/pms/pro_trace_0.rs
+++ b/esp32s2/src/pms/pro_trace_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TRACE_0")
-            .field(
-                "pro_trace_lock",
-                &format_args!("{}", self.pro_trace_lock().bit()),
-            )
+            .field("pro_trace_lock", &self.pro_trace_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TRACE_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks trace function permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/pro_trace_1.rs b/esp32s2/src/pms/pro_trace_1.rs
index 445e8529fe..46f19e0f9a 100644
--- a/esp32s2/src/pms/pro_trace_1.rs
+++ b/esp32s2/src/pms/pro_trace_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_TRACE_1")
-            .field(
-                "pro_trace_disable",
-                &format_args!("{}", self.pro_trace_disable().bit()),
-            )
+            .field("pro_trace_disable", &self.pro_trace_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_TRACE_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Setting to 1 disables the trace memory function."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/sdio_0.rs b/esp32s2/src/pms/sdio_0.rs
index b3fc24463f..da2b9296c2 100644
--- a/esp32s2/src/pms/sdio_0.rs
+++ b/esp32s2/src/pms/sdio_0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_0")
-            .field("sdio_lock", &format_args!("{}", self.sdio_lock().bit()))
+            .field("sdio_lock", &self.sdio_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Lock register. Setting to 1 locks SDIO permission control registers."]
     #[inline(always)]
diff --git a/esp32s2/src/pms/sdio_1.rs b/esp32s2/src/pms/sdio_1.rs
index 754b81777f..e52cdfc136 100644
--- a/esp32s2/src/pms/sdio_1.rs
+++ b/esp32s2/src/pms/sdio_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_1")
-            .field(
-                "sdio_disable",
-                &format_args!("{}", self.sdio_disable().bit()),
-            )
+            .field("sdio_disable", &self.sdio_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Setting to 1 disables the SDIO function."]
     #[inline(always)]
diff --git a/esp32s2/src/rmt/apb_conf.rs b/esp32s2/src/rmt/apb_conf.rs
index 2cfd6b3bde..d51488ae33 100644
--- a/esp32s2/src/rmt/apb_conf.rs
+++ b/esp32s2/src/rmt/apb_conf.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_CONF")
-            .field(
-                "apb_fifo_mask",
-                &format_args!("{}", self.apb_fifo_mask().bit()),
-            )
-            .field(
-                "mem_tx_wrap_en",
-                &format_args!("{}", self.mem_tx_wrap_en().bit()),
-            )
-            .field(
-                "mem_clk_force_on",
-                &format_args!("{}", self.mem_clk_force_on().bit()),
-            )
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("apb_fifo_mask", &self.apb_fifo_mask())
+            .field("mem_tx_wrap_en", &self.mem_tx_wrap_en())
+            .field("mem_clk_force_on", &self.mem_clk_force_on())
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'h1: access memory directly. 1'h0: access memory by FIFO."]
     #[inline(always)]
diff --git a/esp32s2/src/rmt/ch_rx_carrier_rm.rs b/esp32s2/src/rmt/ch_rx_carrier_rm.rs
index 110fc179a3..d55c19dbf1 100644
--- a/esp32s2/src/rmt/ch_rx_carrier_rm.rs
+++ b/esp32s2/src/rmt/ch_rx_carrier_rm.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_CARRIER_RM")
-            .field(
-                "carrier_low_thres",
-                &format_args!("{}", self.carrier_low_thres().bits()),
-            )
-            .field(
-                "carrier_high_thres",
-                &format_args!("{}", self.carrier_high_thres().bits()),
-            )
+            .field("carrier_low_thres", &self.carrier_low_thres())
+            .field("carrier_high_thres", &self.carrier_high_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_CARRIER_RM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s."]
     #[inline(always)]
diff --git a/esp32s2/src/rmt/ch_tx_lim.rs b/esp32s2/src/rmt/ch_tx_lim.rs
index e6fdadecb4..8dacbd07e3 100644
--- a/esp32s2/src/rmt/ch_tx_lim.rs
+++ b/esp32s2/src/rmt/ch_tx_lim.rs
@@ -37,24 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_TX_LIM")
-            .field("tx_lim", &format_args!("{}", self.tx_lim().bits()))
-            .field(
-                "tx_loop_num",
-                &format_args!("{}", self.tx_loop_num().bits()),
-            )
-            .field(
-                "tx_loop_cnt_en",
-                &format_args!("{}", self.tx_loop_cnt_en().bit()),
-            )
+            .field("tx_lim", &self.tx_lim())
+            .field("tx_loop_num", &self.tx_loop_num())
+            .field("tx_loop_cnt_en", &self.tx_loop_cnt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_TX_LIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can send out."]
     #[inline(always)]
diff --git a/esp32s2/src/rmt/chaddr.rs b/esp32s2/src/rmt/chaddr.rs
index d242a405b1..75a66f9c14 100644
--- a/esp32s2/src/rmt/chaddr.rs
+++ b/esp32s2/src/rmt/chaddr.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHADDR")
-            .field(
-                "apb_mem_waddr",
-                &format_args!("{}", self.apb_mem_waddr().bits()),
-            )
-            .field(
-                "apb_mem_raddr",
-                &format_args!("{}", self.apb_mem_raddr().bits()),
-            )
+            .field("apb_mem_waddr", &self.apb_mem_waddr())
+            .field("apb_mem_raddr", &self.apb_mem_raddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Channel %s address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CHADDR_SPEC;
 impl crate::RegisterSpec for CHADDR_SPEC {
diff --git a/esp32s2/src/rmt/chcarrier_duty.rs b/esp32s2/src/rmt/chcarrier_duty.rs
index a3f3981bc9..ffed06d8c2 100644
--- a/esp32s2/src/rmt/chcarrier_duty.rs
+++ b/esp32s2/src/rmt/chcarrier_duty.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHCARRIER_DUTY")
-            .field(
-                "carrier_low",
-                &format_args!("{}", self.carrier_low().bits()),
-            )
-            .field(
-                "carrier_high",
-                &format_args!("{}", self.carrier_high().bits()),
-            )
+            .field("carrier_low", &self.carrier_low())
+            .field("carrier_high", &self.carrier_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHCARRIER_DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure carrier wave 's low level clock period for CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32s2/src/rmt/chconf0.rs b/esp32s2/src/rmt/chconf0.rs
index d8ab028b1f..d305d70db4 100644
--- a/esp32s2/src/rmt/chconf0.rs
+++ b/esp32s2/src/rmt/chconf0.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHCONF0")
-            .field("div_cnt", &format_args!("{}", self.div_cnt().bits()))
-            .field("idle_thres", &format_args!("{}", self.idle_thres().bits()))
-            .field("mem_size", &format_args!("{}", self.mem_size().bits()))
-            .field(
-                "carrier_eff_en",
-                &format_args!("{}", self.carrier_eff_en().bit()),
-            )
-            .field("carrier_en", &format_args!("{}", self.carrier_en().bit()))
-            .field(
-                "carrier_out_lv",
-                &format_args!("{}", self.carrier_out_lv().bit()),
-            )
+            .field("div_cnt", &self.div_cnt())
+            .field("idle_thres", &self.idle_thres())
+            .field("mem_size", &self.mem_size())
+            .field("carrier_eff_en", &self.carrier_eff_en())
+            .field("carrier_en", &self.carrier_en())
+            .field("carrier_out_lv", &self.carrier_out_lv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHCONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the divider for clock of CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32s2/src/rmt/chconf1.rs b/esp32s2/src/rmt/chconf1.rs
index b626b19e00..b3a19c0b32 100644
--- a/esp32s2/src/rmt/chconf1.rs
+++ b/esp32s2/src/rmt/chconf1.rs
@@ -113,41 +113,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHCONF1")
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_en", &format_args!("{}", self.rx_en().bit()))
-            .field("mem_owner", &format_args!("{}", self.mem_owner().bit()))
-            .field(
-                "tx_conti_mode",
-                &format_args!("{}", self.tx_conti_mode().bit()),
-            )
-            .field(
-                "rx_filter_en",
-                &format_args!("{}", self.rx_filter_en().bit()),
-            )
-            .field(
-                "rx_filter_thres",
-                &format_args!("{}", self.rx_filter_thres().bits()),
-            )
-            .field(
-                "chk_rx_carrier_en",
-                &format_args!("{}", self.chk_rx_carrier_en().bit()),
-            )
-            .field(
-                "ref_always_on",
-                &format_args!("{}", self.ref_always_on().bit()),
-            )
-            .field("idle_out_lv", &format_args!("{}", self.idle_out_lv().bit()))
-            .field("idle_out_en", &format_args!("{}", self.idle_out_en().bit()))
-            .field("tx_stop", &format_args!("{}", self.tx_stop().bit()))
+            .field("tx_start", &self.tx_start())
+            .field("rx_en", &self.rx_en())
+            .field("mem_owner", &self.mem_owner())
+            .field("tx_conti_mode", &self.tx_conti_mode())
+            .field("rx_filter_en", &self.rx_filter_en())
+            .field("rx_filter_thres", &self.rx_filter_thres())
+            .field("chk_rx_carrier_en", &self.chk_rx_carrier_en())
+            .field("ref_always_on", &self.ref_always_on())
+            .field("idle_out_lv", &self.idle_out_lv())
+            .field("idle_out_en", &self.idle_out_en())
+            .field("tx_stop", &self.tx_stop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHCONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to start sending data on CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32s2/src/rmt/chdata.rs b/esp32s2/src/rmt/chdata.rs
index 4f21531252..51bc8e6b20 100644
--- a/esp32s2/src/rmt/chdata.rs
+++ b/esp32s2/src/rmt/chdata.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHDATA")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The read and write data register for CHANNEL%s by apb fifo access."]
     #[inline(always)]
diff --git a/esp32s2/src/rmt/chstatus.rs b/esp32s2/src/rmt/chstatus.rs
index 33f5f70ecc..b81ec3b732 100644
--- a/esp32s2/src/rmt/chstatus.rs
+++ b/esp32s2/src/rmt/chstatus.rs
@@ -62,38 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHSTATUS")
-            .field(
-                "mem_waddr_ex",
-                &format_args!("{}", self.mem_waddr_ex().bits()),
-            )
-            .field(
-                "mem_raddr_ex",
-                &format_args!("{}", self.mem_raddr_ex().bits()),
-            )
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field(
-                "mem_owner_err",
-                &format_args!("{}", self.mem_owner_err().bit()),
-            )
-            .field("mem_full", &format_args!("{}", self.mem_full().bit()))
-            .field("mem_empty", &format_args!("{}", self.mem_empty().bit()))
-            .field(
-                "apb_mem_wr_err",
-                &format_args!("{}", self.apb_mem_wr_err().bit()),
-            )
-            .field(
-                "apb_mem_rd_err",
-                &format_args!("{}", self.apb_mem_rd_err().bit()),
-            )
+            .field("mem_waddr_ex", &self.mem_waddr_ex())
+            .field("mem_raddr_ex", &self.mem_raddr_ex())
+            .field("state", &self.state())
+            .field("mem_owner_err", &self.mem_owner_err())
+            .field("mem_full", &self.mem_full())
+            .field("mem_empty", &self.mem_empty())
+            .field("apb_mem_wr_err", &self.apb_mem_wr_err())
+            .field("apb_mem_rd_err", &self.apb_mem_rd_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHSTATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Channel %s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chstatus::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CHSTATUS_SPEC;
 impl crate::RegisterSpec for CHSTATUS_SPEC {
diff --git a/esp32s2/src/rmt/date.rs b/esp32s2/src/rmt/date.rs
index ab6c599646..e154eb27b5 100644
--- a/esp32s2/src/rmt/date.rs
+++ b/esp32s2/src/rmt/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/rmt/int_ena.rs b/esp32s2/src/rmt/int_ena.rs
index d26e3233be..f0414cb341 100644
--- a/esp32s2/src/rmt/int_ena.rs
+++ b/esp32s2/src/rmt/int_ena.rs
@@ -203,47 +203,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_tx_end", &format_args!("{}", self.ch2_tx_end().bit()))
-            .field("ch3_tx_end", &format_args!("{}", self.ch3_tx_end().bit()))
-            .field("ch0_rx_end", &format_args!("{}", self.ch0_rx_end().bit()))
-            .field("ch1_rx_end", &format_args!("{}", self.ch1_rx_end().bit()))
-            .field("ch2_rx_end", &format_args!("{}", self.ch2_rx_end().bit()))
-            .field("ch3_rx_end", &format_args!("{}", self.ch3_rx_end().bit()))
-            .field("ch0_err", &format_args!("{}", self.ch0_err().bit()))
-            .field("ch1_err", &format_args!("{}", self.ch1_err().bit()))
-            .field("ch2_err", &format_args!("{}", self.ch2_err().bit()))
-            .field("ch3_err", &format_args!("{}", self.ch3_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_tx_thr_event",
-                &format_args!("{}", self.ch2_tx_thr_event().bit()),
-            )
-            .field(
-                "ch3_tx_thr_event",
-                &format_args!("{}", self.ch3_tx_thr_event().bit()),
-            )
-            .field("ch0_tx_loop", &format_args!("{}", self.ch0_tx_loop().bit()))
-            .field("ch1_tx_loop", &format_args!("{}", self.ch1_tx_loop().bit()))
-            .field("ch2_tx_loop", &format_args!("{}", self.ch2_tx_loop().bit()))
-            .field("ch3_tx_loop", &format_args!("{}", self.ch3_tx_loop().bit()))
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_tx_end", &self.ch2_tx_end())
+            .field("ch3_tx_end", &self.ch3_tx_end())
+            .field("ch0_rx_end", &self.ch0_rx_end())
+            .field("ch1_rx_end", &self.ch1_rx_end())
+            .field("ch2_rx_end", &self.ch2_rx_end())
+            .field("ch3_rx_end", &self.ch3_rx_end())
+            .field("ch0_err", &self.ch0_err())
+            .field("ch1_err", &self.ch1_err())
+            .field("ch2_err", &self.ch2_err())
+            .field("ch3_err", &self.ch3_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_tx_thr_event", &self.ch2_tx_thr_event())
+            .field("ch3_tx_thr_event", &self.ch3_tx_thr_event())
+            .field("ch0_tx_loop", &self.ch0_tx_loop())
+            .field("ch1_tx_loop", &self.ch1_tx_loop())
+            .field("ch2_tx_loop", &self.ch2_tx_loop())
+            .field("ch3_tx_loop", &self.ch3_tx_loop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enabled bit for CH(0-3)_TX_END_INT."]
     #[doc = ""]
diff --git a/esp32s2/src/rmt/int_raw.rs b/esp32s2/src/rmt/int_raw.rs
index 8c647a5fa6..c0d25df0bc 100644
--- a/esp32s2/src/rmt/int_raw.rs
+++ b/esp32s2/src/rmt/int_raw.rs
@@ -191,47 +191,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_tx_end", &format_args!("{}", self.ch2_tx_end().bit()))
-            .field("ch3_tx_end", &format_args!("{}", self.ch3_tx_end().bit()))
-            .field("ch0_rx_end", &format_args!("{}", self.ch0_rx_end().bit()))
-            .field("ch1_rx_end", &format_args!("{}", self.ch1_rx_end().bit()))
-            .field("ch2_rx_end", &format_args!("{}", self.ch2_rx_end().bit()))
-            .field("ch3_rx_end", &format_args!("{}", self.ch3_rx_end().bit()))
-            .field("ch0_err", &format_args!("{}", self.ch0_err().bit()))
-            .field("ch1_err", &format_args!("{}", self.ch1_err().bit()))
-            .field("ch2_err", &format_args!("{}", self.ch2_err().bit()))
-            .field("ch3_err", &format_args!("{}", self.ch3_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_tx_thr_event",
-                &format_args!("{}", self.ch2_tx_thr_event().bit()),
-            )
-            .field(
-                "ch3_tx_thr_event",
-                &format_args!("{}", self.ch3_tx_thr_event().bit()),
-            )
-            .field("ch0_tx_loop", &format_args!("{}", self.ch0_tx_loop().bit()))
-            .field("ch1_tx_loop", &format_args!("{}", self.ch1_tx_loop().bit()))
-            .field("ch2_tx_loop", &format_args!("{}", self.ch2_tx_loop().bit()))
-            .field("ch3_tx_loop", &format_args!("{}", self.ch3_tx_loop().bit()))
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_tx_end", &self.ch2_tx_end())
+            .field("ch3_tx_end", &self.ch3_tx_end())
+            .field("ch0_rx_end", &self.ch0_rx_end())
+            .field("ch1_rx_end", &self.ch1_rx_end())
+            .field("ch2_rx_end", &self.ch2_rx_end())
+            .field("ch3_rx_end", &self.ch3_rx_end())
+            .field("ch0_err", &self.ch0_err())
+            .field("ch1_err", &self.ch1_err())
+            .field("ch2_err", &self.ch2_err())
+            .field("ch3_err", &self.ch3_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_tx_thr_event", &self.ch2_tx_thr_event())
+            .field("ch3_tx_thr_event", &self.ch3_tx_thr_event())
+            .field("ch0_tx_loop", &self.ch0_tx_loop())
+            .field("ch1_tx_loop", &self.ch1_tx_loop())
+            .field("ch2_tx_loop", &self.ch2_tx_loop())
+            .field("ch3_tx_loop", &self.ch3_tx_loop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s2/src/rmt/int_st.rs b/esp32s2/src/rmt/int_st.rs
index 0a6f4d5e37..81c5e40cb1 100644
--- a/esp32s2/src/rmt/int_st.rs
+++ b/esp32s2/src/rmt/int_st.rs
@@ -191,47 +191,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_tx_end", &format_args!("{}", self.ch2_tx_end().bit()))
-            .field("ch3_tx_end", &format_args!("{}", self.ch3_tx_end().bit()))
-            .field("ch0_rx_end", &format_args!("{}", self.ch0_rx_end().bit()))
-            .field("ch1_rx_end", &format_args!("{}", self.ch1_rx_end().bit()))
-            .field("ch2_rx_end", &format_args!("{}", self.ch2_rx_end().bit()))
-            .field("ch3_rx_end", &format_args!("{}", self.ch3_rx_end().bit()))
-            .field("ch0_err", &format_args!("{}", self.ch0_err().bit()))
-            .field("ch1_err", &format_args!("{}", self.ch1_err().bit()))
-            .field("ch2_err", &format_args!("{}", self.ch2_err().bit()))
-            .field("ch3_err", &format_args!("{}", self.ch3_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_tx_thr_event",
-                &format_args!("{}", self.ch2_tx_thr_event().bit()),
-            )
-            .field(
-                "ch3_tx_thr_event",
-                &format_args!("{}", self.ch3_tx_thr_event().bit()),
-            )
-            .field("ch0_tx_loop", &format_args!("{}", self.ch0_tx_loop().bit()))
-            .field("ch1_tx_loop", &format_args!("{}", self.ch1_tx_loop().bit()))
-            .field("ch2_tx_loop", &format_args!("{}", self.ch2_tx_loop().bit()))
-            .field("ch3_tx_loop", &format_args!("{}", self.ch3_tx_loop().bit()))
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_tx_end", &self.ch2_tx_end())
+            .field("ch3_tx_end", &self.ch3_tx_end())
+            .field("ch0_rx_end", &self.ch0_rx_end())
+            .field("ch1_rx_end", &self.ch1_rx_end())
+            .field("ch2_rx_end", &self.ch2_rx_end())
+            .field("ch3_rx_end", &self.ch3_rx_end())
+            .field("ch0_err", &self.ch0_err())
+            .field("ch1_err", &self.ch1_err())
+            .field("ch2_err", &self.ch2_err())
+            .field("ch3_err", &self.ch3_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_tx_thr_event", &self.ch2_tx_thr_event())
+            .field("ch3_tx_thr_event", &self.ch3_tx_thr_event())
+            .field("ch0_tx_loop", &self.ch0_tx_loop())
+            .field("ch1_tx_loop", &self.ch1_tx_loop())
+            .field("ch2_tx_loop", &self.ch2_tx_loop())
+            .field("ch3_tx_loop", &self.ch3_tx_loop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s2/src/rmt/ref_cnt_rst.rs b/esp32s2/src/rmt/ref_cnt_rst.rs
index 0997b62fb4..35c00a96d0 100644
--- a/esp32s2/src/rmt/ref_cnt_rst.rs
+++ b/esp32s2/src/rmt/ref_cnt_rst.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REF_CNT_RST")
-            .field("ch0", &format_args!("{}", self.ch0().bit()))
-            .field("ch1", &format_args!("{}", self.ch1().bit()))
-            .field("ch2", &format_args!("{}", self.ch2().bit()))
-            .field("ch3", &format_args!("{}", self.ch3().bit()))
+            .field("ch0", &self.ch0())
+            .field("ch1", &self.ch1())
+            .field("ch2", &self.ch2())
+            .field("ch3", &self.ch3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REF_CNT_RST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to reset the clock divider of CHANNEL0."]
     #[inline(always)]
diff --git a/esp32s2/src/rmt/tx_sim.rs b/esp32s2/src/rmt/tx_sim.rs
index b76a424751..fa17898d18 100644
--- a/esp32s2/src/rmt/tx_sim.rs
+++ b/esp32s2/src/rmt/tx_sim.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_SIM")
-            .field("ch0", &format_args!("{}", self.ch0().bit()))
-            .field("ch1", &format_args!("{}", self.ch1().bit()))
-            .field("ch2", &format_args!("{}", self.ch2().bit()))
-            .field("ch3", &format_args!("{}", self.ch3().bit()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("ch0", &self.ch0())
+            .field("ch1", &self.ch1())
+            .field("ch2", &self.ch2())
+            .field("ch3", &self.ch3())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_SIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels."]
     #[inline(always)]
diff --git a/esp32s2/src/rng/data.rs b/esp32s2/src/rng/data.rs
index 016046274d..4d812a63aa 100644
--- a/esp32s2/src/rng/data.rs
+++ b/esp32s2/src/rng/data.rs
@@ -6,12 +6,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Random number data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DATA_SPEC;
 impl crate::RegisterSpec for DATA_SPEC {
diff --git a/esp32s2/src/rsa/clean.rs b/esp32s2/src/rsa/clean.rs
index 8f2d6a8a89..1004f25cca 100644
--- a/esp32s2/src/rsa/clean.rs
+++ b/esp32s2/src/rsa/clean.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLEAN")
-            .field("clean", &format_args!("{}", self.clean().bit()))
+            .field("clean", &self.clean())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLEAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RSA clean register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clean::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLEAN_SPEC;
 impl crate::RegisterSpec for CLEAN_SPEC {
diff --git a/esp32s2/src/rsa/constant_time.rs b/esp32s2/src/rsa/constant_time.rs
index 8f71638d03..252ad296ac 100644
--- a/esp32s2/src/rsa/constant_time.rs
+++ b/esp32s2/src/rsa/constant_time.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONSTANT_TIME")
-            .field(
-                "constant_time",
-                &format_args!("{}", self.constant_time().bit()),
-            )
+            .field("constant_time", &self.constant_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONSTANT_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to 0 to enable the acceleration option of constant_time for modular exponentiation. Set to 1 to disable the acceleration (by default)."]
     #[inline(always)]
diff --git a/esp32s2/src/rsa/date.rs b/esp32s2/src/rsa/date.rs
index 9e0f7bd0cd..67ef9b7e79 100644
--- a/esp32s2/src/rsa/date.rs
+++ b/esp32s2/src/rsa/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/rsa/idle.rs b/esp32s2/src/rsa/idle.rs
index 0b04117c96..b2e6494d3e 100644
--- a/esp32s2/src/rsa/idle.rs
+++ b/esp32s2/src/rsa/idle.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("IDLE")
-            .field("idle", &format_args!("{}", self.idle().bit()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("IDLE").field("idle", &self.idle()).finish()
     }
 }
 #[doc = "RSA idle register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idle::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s2/src/rsa/interrupt_ena.rs b/esp32s2/src/rsa/interrupt_ena.rs
index 50a18864ef..e50496a2fe 100644
--- a/esp32s2/src/rsa/interrupt_ena.rs
+++ b/esp32s2/src/rsa/interrupt_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT_ENA")
-            .field(
-                "interrupt_ena",
-                &format_args!("{}", self.interrupt_ena().bit()),
-            )
+            .field("interrupt_ena", &self.interrupt_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."]
     #[inline(always)]
diff --git a/esp32s2/src/rsa/m_prime.rs b/esp32s2/src/rsa/m_prime.rs
index 8ebf9dd22f..14fef4d9d5 100644
--- a/esp32s2/src/rsa/m_prime.rs
+++ b/esp32s2/src/rsa/m_prime.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("M_PRIME")
-            .field("m_prime", &format_args!("{}", self.m_prime().bits()))
+            .field("m_prime", &self.m_prime())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_PRIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stores M'."]
     #[inline(always)]
diff --git a/esp32s2/src/rsa/mode.rs b/esp32s2/src/rsa/mode.rs
index 93fcc8b616..77830e1ac9 100644
--- a/esp32s2/src/rsa/mode.rs
+++ b/esp32s2/src/rsa/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/rsa/search_enable.rs b/esp32s2/src/rsa/search_enable.rs
index fce21b81d2..43b48b7751 100644
--- a/esp32s2/src/rsa/search_enable.rs
+++ b/esp32s2/src/rsa/search_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEARCH_ENABLE")
-            .field(
-                "search_enable",
-                &format_args!("{}", self.search_enable().bit()),
-            )
+            .field("search_enable", &self.search_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEARCH_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable the acceleration option of search for modular exponentiation. Set to 0 to disable the acceleration (by default)."]
     #[inline(always)]
diff --git a/esp32s2/src/rsa/search_pos.rs b/esp32s2/src/rsa/search_pos.rs
index 3f9f638491..b8055d5eb8 100644
--- a/esp32s2/src/rsa/search_pos.rs
+++ b/esp32s2/src/rsa/search_pos.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEARCH_POS")
-            .field("search_pos", &format_args!("{}", self.search_pos().bits()))
+            .field("search_pos", &self.search_pos())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEARCH_POS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - Is used to configure the starting address when the acceleration option of search is used."]
     #[inline(always)]
diff --git a/esp32s2/src/rsa/z_mem.rs b/esp32s2/src/rsa/z_mem.rs
index 6826e9d664..5bee6c1785 100644
--- a/esp32s2/src/rsa/z_mem.rs
+++ b/esp32s2/src/rsa/z_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Z_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Represents Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Z_MEM_SPEC;
diff --git a/esp32s2/src/rtc_cntl/ana_conf.rs b/esp32s2/src/rtc_cntl/ana_conf.rs
index 1a1965817d..4dc1c06d9d 100644
--- a/esp32s2/src/rtc_cntl/ana_conf.rs
+++ b/esp32s2/src/rtc_cntl/ana_conf.rs
@@ -125,58 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ANA_CONF")
-            .field(
-                "i2c_reset_por_force_pd",
-                &format_args!("{}", self.i2c_reset_por_force_pd().bit()),
-            )
-            .field(
-                "i2c_reset_por_force_pu",
-                &format_args!("{}", self.i2c_reset_por_force_pu().bit()),
-            )
-            .field(
-                "glitch_rst_en",
-                &format_args!("{}", self.glitch_rst_en().bit()),
-            )
-            .field(
-                "sar_i2c_force_pd",
-                &format_args!("{}", self.sar_i2c_force_pd().bit()),
-            )
-            .field(
-                "sar_i2c_force_pu",
-                &format_args!("{}", self.sar_i2c_force_pu().bit()),
-            )
-            .field(
-                "plla_force_pd",
-                &format_args!("{}", self.plla_force_pd().bit()),
-            )
-            .field(
-                "plla_force_pu",
-                &format_args!("{}", self.plla_force_pu().bit()),
-            )
-            .field(
-                "bbpll_cal_slp_start",
-                &format_args!("{}", self.bbpll_cal_slp_start().bit()),
-            )
-            .field("pvtmon_pu", &format_args!("{}", self.pvtmon_pu().bit()))
-            .field("txrf_i2c_pu", &format_args!("{}", self.txrf_i2c_pu().bit()))
-            .field(
-                "rfrx_pbus_pu",
-                &format_args!("{}", self.rfrx_pbus_pu().bit()),
-            )
-            .field(
-                "ckgen_i2c_pu",
-                &format_args!("{}", self.ckgen_i2c_pu().bit()),
-            )
-            .field("pll_i2c_pu", &format_args!("{}", self.pll_i2c_pu().bit()))
+            .field("i2c_reset_por_force_pd", &self.i2c_reset_por_force_pd())
+            .field("i2c_reset_por_force_pu", &self.i2c_reset_por_force_pu())
+            .field("glitch_rst_en", &self.glitch_rst_en())
+            .field("sar_i2c_force_pd", &self.sar_i2c_force_pd())
+            .field("sar_i2c_force_pu", &self.sar_i2c_force_pu())
+            .field("plla_force_pd", &self.plla_force_pd())
+            .field("plla_force_pu", &self.plla_force_pu())
+            .field("bbpll_cal_slp_start", &self.bbpll_cal_slp_start())
+            .field("pvtmon_pu", &self.pvtmon_pu())
+            .field("txrf_i2c_pu", &self.txrf_i2c_pu())
+            .field("rfrx_pbus_pu", &self.rfrx_pbus_pu())
+            .field("ckgen_i2c_pu", &self.ckgen_i2c_pu())
+            .field("pll_i2c_pu", &self.pll_i2c_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ANA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - SLEEP_I2CPOR force pd"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/bias_conf.rs b/esp32s2/src/rtc_cntl/bias_conf.rs
index 6732ca4273..0c5a9ee6f1 100644
--- a/esp32s2/src/rtc_cntl/bias_conf.rs
+++ b/esp32s2/src/rtc_cntl/bias_conf.rs
@@ -152,79 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BIAS_CONF")
-            .field(
-                "bias_buf_idle",
-                &format_args!("{}", self.bias_buf_idle().bit()),
-            )
-            .field(
-                "bias_buf_wake",
-                &format_args!("{}", self.bias_buf_wake().bit()),
-            )
-            .field(
-                "bias_buf_deep_slp",
-                &format_args!("{}", self.bias_buf_deep_slp().bit()),
-            )
-            .field(
-                "bias_buf_monitor",
-                &format_args!("{}", self.bias_buf_monitor().bit()),
-            )
-            .field(
-                "pd_cur_deep_slp",
-                &format_args!("{}", self.pd_cur_deep_slp().bit()),
-            )
-            .field(
-                "pd_cur_monitor",
-                &format_args!("{}", self.pd_cur_monitor().bit()),
-            )
-            .field(
-                "bias_sleep_deep_slp",
-                &format_args!("{}", self.bias_sleep_deep_slp().bit()),
-            )
-            .field(
-                "bias_sleep_monitor",
-                &format_args!("{}", self.bias_sleep_monitor().bit()),
-            )
-            .field(
-                "dbg_atten_deep_slp",
-                &format_args!("{}", self.dbg_atten_deep_slp().bits()),
-            )
-            .field(
-                "dbg_atten_monitor",
-                &format_args!("{}", self.dbg_atten_monitor().bits()),
-            )
-            .field(
-                "enb_sck_xtal",
-                &format_args!("{}", self.enb_sck_xtal().bit()),
-            )
-            .field(
-                "inc_heartbeat_refresh",
-                &format_args!("{}", self.inc_heartbeat_refresh().bit()),
-            )
-            .field(
-                "dec_heartbeat_period",
-                &format_args!("{}", self.dec_heartbeat_period().bit()),
-            )
-            .field(
-                "inc_heartbeat_period",
-                &format_args!("{}", self.inc_heartbeat_period().bit()),
-            )
-            .field(
-                "dec_heartbeat_width",
-                &format_args!("{}", self.dec_heartbeat_width().bit()),
-            )
-            .field(
-                "rst_bias_i2c",
-                &format_args!("{}", self.rst_bias_i2c().bit()),
-            )
+            .field("bias_buf_idle", &self.bias_buf_idle())
+            .field("bias_buf_wake", &self.bias_buf_wake())
+            .field("bias_buf_deep_slp", &self.bias_buf_deep_slp())
+            .field("bias_buf_monitor", &self.bias_buf_monitor())
+            .field("pd_cur_deep_slp", &self.pd_cur_deep_slp())
+            .field("pd_cur_monitor", &self.pd_cur_monitor())
+            .field("bias_sleep_deep_slp", &self.bias_sleep_deep_slp())
+            .field("bias_sleep_monitor", &self.bias_sleep_monitor())
+            .field("dbg_atten_deep_slp", &self.dbg_atten_deep_slp())
+            .field("dbg_atten_monitor", &self.dbg_atten_monitor())
+            .field("enb_sck_xtal", &self.enb_sck_xtal())
+            .field("inc_heartbeat_refresh", &self.inc_heartbeat_refresh())
+            .field("dec_heartbeat_period", &self.dec_heartbeat_period())
+            .field("inc_heartbeat_period", &self.inc_heartbeat_period())
+            .field("dec_heartbeat_width", &self.dec_heartbeat_width())
+            .field("rst_bias_i2c", &self.rst_bias_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BIAS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 10 - open bias buf when system in active"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/brown_out.rs b/esp32s2/src/rtc_cntl/brown_out.rs
index cffd3d3b52..66282c22f1 100644
--- a/esp32s2/src/rtc_cntl/brown_out.rs
+++ b/esp32s2/src/rtc_cntl/brown_out.rs
@@ -89,30 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BROWN_OUT")
-            .field(
-                "brown_out2_ena",
-                &format_args!("{}", self.brown_out2_ena().bit()),
-            )
-            .field("int_wait", &format_args!("{}", self.int_wait().bits()))
-            .field(
-                "close_flash_ena",
-                &format_args!("{}", self.close_flash_ena().bit()),
-            )
-            .field("pd_rf_ena", &format_args!("{}", self.pd_rf_ena().bit()))
-            .field("rst_wait", &format_args!("{}", self.rst_wait().bits()))
-            .field("rst_ena", &format_args!("{}", self.rst_ena().bit()))
-            .field("rst_sel", &format_args!("{}", self.rst_sel().bit()))
-            .field("ena", &format_args!("{}", self.ena().bit()))
-            .field("det", &format_args!("{}", self.det().bit()))
+            .field("brown_out2_ena", &self.brown_out2_ena())
+            .field("int_wait", &self.int_wait())
+            .field("close_flash_ena", &self.close_flash_ena())
+            .field("pd_rf_ena", &self.pd_rf_ena())
+            .field("rst_wait", &self.rst_wait())
+            .field("rst_ena", &self.rst_ena())
+            .field("rst_sel", &self.rst_sel())
+            .field("ena", &self.ena())
+            .field("det", &self.det())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BROWN_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enables the brown_out2 to initiate a chip reset."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/clk_conf.rs b/esp32s2/src/rtc_cntl/clk_conf.rs
index 280676f997..d194f7eb97 100644
--- a/esp32s2/src/rtc_cntl/clk_conf.rs
+++ b/esp32s2/src/rtc_cntl/clk_conf.rs
@@ -143,66 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field(
-                "ck8m_div_sel_vld",
-                &format_args!("{}", self.ck8m_div_sel_vld().bit()),
-            )
-            .field("ck8m_div", &format_args!("{}", self.ck8m_div().bits()))
-            .field("enb_ck8m", &format_args!("{}", self.enb_ck8m().bit()))
-            .field(
-                "enb_ck8m_div",
-                &format_args!("{}", self.enb_ck8m_div().bit()),
-            )
-            .field(
-                "dig_xtal32k_en",
-                &format_args!("{}", self.dig_xtal32k_en().bit()),
-            )
-            .field(
-                "dig_clk8m_d256_en",
-                &format_args!("{}", self.dig_clk8m_d256_en().bit()),
-            )
-            .field(
-                "dig_clk8m_en",
-                &format_args!("{}", self.dig_clk8m_en().bit()),
-            )
-            .field(
-                "ck8m_div_sel",
-                &format_args!("{}", self.ck8m_div_sel().bits()),
-            )
-            .field(
-                "xtal_force_nogating",
-                &format_args!("{}", self.xtal_force_nogating().bit()),
-            )
-            .field(
-                "ck8m_force_nogating",
-                &format_args!("{}", self.ck8m_force_nogating().bit()),
-            )
-            .field("ck8m_dfreq", &format_args!("{}", self.ck8m_dfreq().bits()))
-            .field(
-                "ck8m_force_pd",
-                &format_args!("{}", self.ck8m_force_pd().bit()),
-            )
-            .field(
-                "ck8m_force_pu",
-                &format_args!("{}", self.ck8m_force_pu().bit()),
-            )
-            .field(
-                "fast_clk_rtc_sel",
-                &format_args!("{}", self.fast_clk_rtc_sel().bit()),
-            )
-            .field(
-                "ana_clk_rtc_sel",
-                &format_args!("{}", self.ana_clk_rtc_sel().bits()),
-            )
+            .field("ck8m_div_sel_vld", &self.ck8m_div_sel_vld())
+            .field("ck8m_div", &self.ck8m_div())
+            .field("enb_ck8m", &self.enb_ck8m())
+            .field("enb_ck8m_div", &self.enb_ck8m_div())
+            .field("dig_xtal32k_en", &self.dig_xtal32k_en())
+            .field("dig_clk8m_d256_en", &self.dig_clk8m_d256_en())
+            .field("dig_clk8m_en", &self.dig_clk8m_en())
+            .field("ck8m_div_sel", &self.ck8m_div_sel())
+            .field("xtal_force_nogating", &self.xtal_force_nogating())
+            .field("ck8m_force_nogating", &self.ck8m_force_nogating())
+            .field("ck8m_dfreq", &self.ck8m_dfreq())
+            .field("ck8m_force_pd", &self.ck8m_force_pd())
+            .field("ck8m_force_pu", &self.ck8m_force_pu())
+            .field("fast_clk_rtc_sel", &self.fast_clk_rtc_sel())
+            .field("ana_clk_rtc_sel", &self.ana_clk_rtc_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - Synchronizes the reg_ck8m_div_sel. Not that you have to invalidate the bus before switching clock, and validate the new clock."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/cocpu_ctrl.rs b/esp32s2/src/rtc_cntl/cocpu_ctrl.rs
index fcfa60963e..466b969657 100644
--- a/esp32s2/src/rtc_cntl/cocpu_ctrl.rs
+++ b/esp32s2/src/rtc_cntl/cocpu_ctrl.rs
@@ -91,42 +91,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COCPU_CTRL")
-            .field(
-                "cocpu_clk_fo",
-                &format_args!("{}", self.cocpu_clk_fo().bit()),
-            )
-            .field(
-                "cocpu_start_2_reset_dis",
-                &format_args!("{}", self.cocpu_start_2_reset_dis().bits()),
-            )
-            .field(
-                "cocpu_start_2_intr_en",
-                &format_args!("{}", self.cocpu_start_2_intr_en().bits()),
-            )
-            .field("cocpu_shut", &format_args!("{}", self.cocpu_shut().bit()))
-            .field(
-                "cocpu_shut_2_clk_dis",
-                &format_args!("{}", self.cocpu_shut_2_clk_dis().bits()),
-            )
-            .field(
-                "cocpu_shut_reset_en",
-                &format_args!("{}", self.cocpu_shut_reset_en().bit()),
-            )
-            .field("cocpu_sel", &format_args!("{}", self.cocpu_sel().bit()))
-            .field(
-                "cocpu_done_force",
-                &format_args!("{}", self.cocpu_done_force().bit()),
-            )
-            .field("cocpu_done", &format_args!("{}", self.cocpu_done().bit()))
+            .field("cocpu_clk_fo", &self.cocpu_clk_fo())
+            .field("cocpu_start_2_reset_dis", &self.cocpu_start_2_reset_dis())
+            .field("cocpu_start_2_intr_en", &self.cocpu_start_2_intr_en())
+            .field("cocpu_shut", &self.cocpu_shut())
+            .field("cocpu_shut_2_clk_dis", &self.cocpu_shut_2_clk_dis())
+            .field("cocpu_shut_reset_en", &self.cocpu_shut_reset_en())
+            .field("cocpu_sel", &self.cocpu_sel())
+            .field("cocpu_done_force", &self.cocpu_done_force())
+            .field("cocpu_done", &self.cocpu_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COCPU_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ULP-RISCV clock force on"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/cpu_period_conf.rs b/esp32s2/src/rtc_cntl/cpu_period_conf.rs
index 2dee066cca..59c914ea54 100644
--- a/esp32s2/src/rtc_cntl/cpu_period_conf.rs
+++ b/esp32s2/src/rtc_cntl/cpu_period_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERIOD_CONF")
-            .field("cpusel_conf", &format_args!("{}", self.cpusel_conf().bit()))
-            .field(
-                "cpuperiod_sel",
-                &format_args!("{}", self.cpuperiod_sel().bits()),
-            )
+            .field("cpusel_conf", &self.cpusel_conf())
+            .field("cpuperiod_sel", &self.cpuperiod_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERIOD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 29 - CPU sel option"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/date.rs b/esp32s2/src/rtc_cntl/date.rs
index 2a3aaea230..4032a66223 100644
--- a/esp32s2/src/rtc_cntl/date.rs
+++ b/esp32s2/src/rtc_cntl/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("cntl_date", &format_args!("{}", self.cntl_date().bits()))
+            .field("cntl_date", &self.cntl_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/diag0.rs b/esp32s2/src/rtc_cntl/diag0.rs
index 8b5d8deea0..068e870405 100644
--- a/esp32s2/src/rtc_cntl/diag0.rs
+++ b/esp32s2/src/rtc_cntl/diag0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIAG0")
-            .field(
-                "low_power_diag1",
-                &format_args!("{}", self.low_power_diag1().bits()),
-            )
+            .field("low_power_diag1", &self.low_power_diag1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIAG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "debug register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diag0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIAG0_SPEC;
 impl crate::RegisterSpec for DIAG0_SPEC {
diff --git a/esp32s2/src/rtc_cntl/dig_iso.rs b/esp32s2/src/rtc_cntl/dig_iso.rs
index 6f355cbfa6..c3505d87cd 100644
--- a/esp32s2/src/rtc_cntl/dig_iso.rs
+++ b/esp32s2/src/rtc_cntl/dig_iso.rs
@@ -224,105 +224,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIG_ISO")
-            .field("force_off", &format_args!("{}", self.force_off().bit()))
-            .field("force_on", &format_args!("{}", self.force_on().bit()))
-            .field(
-                "dg_pad_autohold",
-                &format_args!("{}", self.dg_pad_autohold().bit()),
-            )
-            .field(
-                "dg_pad_autohold_en",
-                &format_args!("{}", self.dg_pad_autohold_en().bit()),
-            )
-            .field(
-                "dg_pad_force_noiso",
-                &format_args!("{}", self.dg_pad_force_noiso().bit()),
-            )
-            .field(
-                "dg_pad_force_iso",
-                &format_args!("{}", self.dg_pad_force_iso().bit()),
-            )
-            .field(
-                "dg_pad_force_unhold",
-                &format_args!("{}", self.dg_pad_force_unhold().bit()),
-            )
-            .field(
-                "dg_pad_force_hold",
-                &format_args!("{}", self.dg_pad_force_hold().bit()),
-            )
-            .field(
-                "rom0_force_iso",
-                &format_args!("{}", self.rom0_force_iso().bit()),
-            )
-            .field(
-                "rom0_force_noiso",
-                &format_args!("{}", self.rom0_force_noiso().bit()),
-            )
-            .field(
-                "inter_ram0_force_iso",
-                &format_args!("{}", self.inter_ram0_force_iso().bit()),
-            )
-            .field(
-                "inter_ram0_force_noiso",
-                &format_args!("{}", self.inter_ram0_force_noiso().bit()),
-            )
-            .field(
-                "inter_ram1_force_iso",
-                &format_args!("{}", self.inter_ram1_force_iso().bit()),
-            )
-            .field(
-                "inter_ram1_force_noiso",
-                &format_args!("{}", self.inter_ram1_force_noiso().bit()),
-            )
-            .field(
-                "inter_ram2_force_iso",
-                &format_args!("{}", self.inter_ram2_force_iso().bit()),
-            )
-            .field(
-                "inter_ram2_force_noiso",
-                &format_args!("{}", self.inter_ram2_force_noiso().bit()),
-            )
-            .field(
-                "inter_ram3_force_iso",
-                &format_args!("{}", self.inter_ram3_force_iso().bit()),
-            )
-            .field(
-                "inter_ram3_force_noiso",
-                &format_args!("{}", self.inter_ram3_force_noiso().bit()),
-            )
-            .field(
-                "inter_ram4_force_iso",
-                &format_args!("{}", self.inter_ram4_force_iso().bit()),
-            )
-            .field(
-                "inter_ram4_force_noiso",
-                &format_args!("{}", self.inter_ram4_force_noiso().bit()),
-            )
-            .field(
-                "wifi_force_iso",
-                &format_args!("{}", self.wifi_force_iso().bit()),
-            )
-            .field(
-                "wifi_force_noiso",
-                &format_args!("{}", self.wifi_force_noiso().bit()),
-            )
-            .field(
-                "dg_wrap_force_iso",
-                &format_args!("{}", self.dg_wrap_force_iso().bit()),
-            )
-            .field(
-                "dg_wrap_force_noiso",
-                &format_args!("{}", self.dg_wrap_force_noiso().bit()),
-            )
+            .field("force_off", &self.force_off())
+            .field("force_on", &self.force_on())
+            .field("dg_pad_autohold", &self.dg_pad_autohold())
+            .field("dg_pad_autohold_en", &self.dg_pad_autohold_en())
+            .field("dg_pad_force_noiso", &self.dg_pad_force_noiso())
+            .field("dg_pad_force_iso", &self.dg_pad_force_iso())
+            .field("dg_pad_force_unhold", &self.dg_pad_force_unhold())
+            .field("dg_pad_force_hold", &self.dg_pad_force_hold())
+            .field("rom0_force_iso", &self.rom0_force_iso())
+            .field("rom0_force_noiso", &self.rom0_force_noiso())
+            .field("inter_ram0_force_iso", &self.inter_ram0_force_iso())
+            .field("inter_ram0_force_noiso", &self.inter_ram0_force_noiso())
+            .field("inter_ram1_force_iso", &self.inter_ram1_force_iso())
+            .field("inter_ram1_force_noiso", &self.inter_ram1_force_noiso())
+            .field("inter_ram2_force_iso", &self.inter_ram2_force_iso())
+            .field("inter_ram2_force_noiso", &self.inter_ram2_force_noiso())
+            .field("inter_ram3_force_iso", &self.inter_ram3_force_iso())
+            .field("inter_ram3_force_noiso", &self.inter_ram3_force_noiso())
+            .field("inter_ram4_force_iso", &self.inter_ram4_force_iso())
+            .field("inter_ram4_force_noiso", &self.inter_ram4_force_noiso())
+            .field("wifi_force_iso", &self.wifi_force_iso())
+            .field("wifi_force_noiso", &self.wifi_force_noiso())
+            .field("dg_wrap_force_iso", &self.dg_wrap_force_iso())
+            .field("dg_wrap_force_noiso", &self.dg_wrap_force_noiso())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIG_ISO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/dig_pad_hold.rs b/esp32s2/src/rtc_cntl/dig_pad_hold.rs
index 43c0efa047..9f87fa693a 100644
--- a/esp32s2/src/rtc_cntl/dig_pad_hold.rs
+++ b/esp32s2/src/rtc_cntl/dig_pad_hold.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIG_PAD_HOLD")
-            .field(
-                "dig_pad_hold",
-                &format_args!("{}", self.dig_pad_hold().bits()),
-            )
+            .field("dig_pad_hold", &self.dig_pad_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIG_PAD_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Set GPIO 21 to GPIO 45 to hold. (See bitmap to locate any GPIO)."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/dig_pwc.rs b/esp32s2/src/rtc_cntl/dig_pwc.rs
index 319bb292b4..c9429e4f93 100644
--- a/esp32s2/src/rtc_cntl/dig_pwc.rs
+++ b/esp32s2/src/rtc_cntl/dig_pwc.rs
@@ -269,125 +269,38 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIG_PWC")
-            .field(
-                "lslp_mem_force_pd",
-                &format_args!("{}", self.lslp_mem_force_pd().bit()),
-            )
-            .field(
-                "lslp_mem_force_pu",
-                &format_args!("{}", self.lslp_mem_force_pu().bit()),
-            )
-            .field(
-                "rom0_force_pd",
-                &format_args!("{}", self.rom0_force_pd().bit()),
-            )
-            .field(
-                "rom0_force_pu",
-                &format_args!("{}", self.rom0_force_pu().bit()),
-            )
-            .field(
-                "inter_ram0_force_pd",
-                &format_args!("{}", self.inter_ram0_force_pd().bit()),
-            )
-            .field(
-                "inter_ram0_force_pu",
-                &format_args!("{}", self.inter_ram0_force_pu().bit()),
-            )
-            .field(
-                "inter_ram1_force_pd",
-                &format_args!("{}", self.inter_ram1_force_pd().bit()),
-            )
-            .field(
-                "inter_ram1_force_pu",
-                &format_args!("{}", self.inter_ram1_force_pu().bit()),
-            )
-            .field(
-                "inter_ram2_force_pd",
-                &format_args!("{}", self.inter_ram2_force_pd().bit()),
-            )
-            .field(
-                "inter_ram2_force_pu",
-                &format_args!("{}", self.inter_ram2_force_pu().bit()),
-            )
-            .field(
-                "inter_ram3_force_pd",
-                &format_args!("{}", self.inter_ram3_force_pd().bit()),
-            )
-            .field(
-                "inter_ram3_force_pu",
-                &format_args!("{}", self.inter_ram3_force_pu().bit()),
-            )
-            .field(
-                "inter_ram4_force_pd",
-                &format_args!("{}", self.inter_ram4_force_pd().bit()),
-            )
-            .field(
-                "inter_ram4_force_pu",
-                &format_args!("{}", self.inter_ram4_force_pu().bit()),
-            )
-            .field(
-                "wifi_force_pd",
-                &format_args!("{}", self.wifi_force_pd().bit()),
-            )
-            .field(
-                "wifi_force_pu",
-                &format_args!("{}", self.wifi_force_pu().bit()),
-            )
-            .field(
-                "dg_wrap_force_pd",
-                &format_args!("{}", self.dg_wrap_force_pd().bit()),
-            )
-            .field(
-                "dg_wrap_force_pu",
-                &format_args!("{}", self.dg_wrap_force_pu().bit()),
-            )
-            .field(
-                "dg_dcdc_force_pd",
-                &format_args!("{}", self.dg_dcdc_force_pd().bit()),
-            )
-            .field(
-                "dg_dcdc_force_pu",
-                &format_args!("{}", self.dg_dcdc_force_pu().bit()),
-            )
-            .field(
-                "dg_dcdc_pd_en",
-                &format_args!("{}", self.dg_dcdc_pd_en().bit()),
-            )
-            .field("rom0_pd_en", &format_args!("{}", self.rom0_pd_en().bit()))
-            .field(
-                "inter_ram0_pd_en",
-                &format_args!("{}", self.inter_ram0_pd_en().bit()),
-            )
-            .field(
-                "inter_ram1_pd_en",
-                &format_args!("{}", self.inter_ram1_pd_en().bit()),
-            )
-            .field(
-                "inter_ram2_pd_en",
-                &format_args!("{}", self.inter_ram2_pd_en().bit()),
-            )
-            .field(
-                "inter_ram3_pd_en",
-                &format_args!("{}", self.inter_ram3_pd_en().bit()),
-            )
-            .field(
-                "inter_ram4_pd_en",
-                &format_args!("{}", self.inter_ram4_pd_en().bit()),
-            )
-            .field("wifi_pd_en", &format_args!("{}", self.wifi_pd_en().bit()))
-            .field(
-                "dg_wrap_pd_en",
-                &format_args!("{}", self.dg_wrap_pd_en().bit()),
-            )
+            .field("lslp_mem_force_pd", &self.lslp_mem_force_pd())
+            .field("lslp_mem_force_pu", &self.lslp_mem_force_pu())
+            .field("rom0_force_pd", &self.rom0_force_pd())
+            .field("rom0_force_pu", &self.rom0_force_pu())
+            .field("inter_ram0_force_pd", &self.inter_ram0_force_pd())
+            .field("inter_ram0_force_pu", &self.inter_ram0_force_pu())
+            .field("inter_ram1_force_pd", &self.inter_ram1_force_pd())
+            .field("inter_ram1_force_pu", &self.inter_ram1_force_pu())
+            .field("inter_ram2_force_pd", &self.inter_ram2_force_pd())
+            .field("inter_ram2_force_pu", &self.inter_ram2_force_pu())
+            .field("inter_ram3_force_pd", &self.inter_ram3_force_pd())
+            .field("inter_ram3_force_pu", &self.inter_ram3_force_pu())
+            .field("inter_ram4_force_pd", &self.inter_ram4_force_pd())
+            .field("inter_ram4_force_pu", &self.inter_ram4_force_pu())
+            .field("wifi_force_pd", &self.wifi_force_pd())
+            .field("wifi_force_pu", &self.wifi_force_pu())
+            .field("dg_wrap_force_pd", &self.dg_wrap_force_pd())
+            .field("dg_wrap_force_pu", &self.dg_wrap_force_pu())
+            .field("dg_dcdc_force_pd", &self.dg_dcdc_force_pd())
+            .field("dg_dcdc_force_pu", &self.dg_dcdc_force_pu())
+            .field("dg_dcdc_pd_en", &self.dg_dcdc_pd_en())
+            .field("rom0_pd_en", &self.rom0_pd_en())
+            .field("inter_ram0_pd_en", &self.inter_ram0_pd_en())
+            .field("inter_ram1_pd_en", &self.inter_ram1_pd_en())
+            .field("inter_ram2_pd_en", &self.inter_ram2_pd_en())
+            .field("inter_ram3_pd_en", &self.inter_ram3_pd_en())
+            .field("inter_ram4_pd_en", &self.inter_ram4_pd_en())
+            .field("wifi_pd_en", &self.wifi_pd_en())
+            .field("dg_wrap_pd_en", &self.dg_wrap_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIG_PWC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - Set this bit to FPD the memories in the digital system in sleep."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/ext_wakeup1.rs b/esp32s2/src/rtc_cntl/ext_wakeup1.rs
index 8177d66393..688ebb34a2 100644
--- a/esp32s2/src/rtc_cntl/ext_wakeup1.rs
+++ b/esp32s2/src/rtc_cntl/ext_wakeup1.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP1")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Selects a RTC GPIO to be the EXT1 wakeup source."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/ext_wakeup1_status.rs b/esp32s2/src/rtc_cntl/ext_wakeup1_status.rs
index 1a21992345..18bb55c978 100644
--- a/esp32s2/src/rtc_cntl/ext_wakeup1_status.rs
+++ b/esp32s2/src/rtc_cntl/ext_wakeup1_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP1_STATUS")
-            .field(
-                "ext_wakeup1_status",
-                &format_args!("{}", self.ext_wakeup1_status().bits()),
-            )
+            .field("ext_wakeup1_status", &self.ext_wakeup1_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP1_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "EXT1 wakeup source register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup1_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXT_WAKEUP1_STATUS_SPEC;
 impl crate::RegisterSpec for EXT_WAKEUP1_STATUS_SPEC {
diff --git a/esp32s2/src/rtc_cntl/ext_wakeup_conf.rs b/esp32s2/src/rtc_cntl/ext_wakeup_conf.rs
index b26b987487..0264695da5 100644
--- a/esp32s2/src/rtc_cntl/ext_wakeup_conf.rs
+++ b/esp32s2/src/rtc_cntl/ext_wakeup_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP_CONF")
-            .field(
-                "gpio_wakeup_filter",
-                &format_args!("{}", self.gpio_wakeup_filter().bit()),
-            )
-            .field(
-                "ext_wakeup0_lv",
-                &format_args!("{}", self.ext_wakeup0_lv().bit()),
-            )
-            .field(
-                "ext_wakeup1_lv",
-                &format_args!("{}", self.ext_wakeup1_lv().bit()),
-            )
+            .field("gpio_wakeup_filter", &self.gpio_wakeup_filter())
+            .field("ext_wakeup0_lv", &self.ext_wakeup0_lv())
+            .field("ext_wakeup1_lv", &self.ext_wakeup1_lv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 29 - Set this bit to enable the GPIO wakeup event filter."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/ext_xtl_conf.rs b/esp32s2/src/rtc_cntl/ext_xtl_conf.rs
index 5997cc9f69..492c04cc26 100644
--- a/esp32s2/src/rtc_cntl/ext_xtl_conf.rs
+++ b/esp32s2/src/rtc_cntl/ext_xtl_conf.rs
@@ -168,84 +168,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_XTL_CONF")
-            .field(
-                "xtal32k_wdt_en",
-                &format_args!("{}", self.xtal32k_wdt_en().bit()),
-            )
-            .field(
-                "xtal32k_wdt_clk_fo",
-                &format_args!("{}", self.xtal32k_wdt_clk_fo().bit()),
-            )
-            .field(
-                "xtal32k_wdt_reset",
-                &format_args!("{}", self.xtal32k_wdt_reset().bit()),
-            )
-            .field(
-                "xtal32k_ext_clk_fo",
-                &format_args!("{}", self.xtal32k_ext_clk_fo().bit()),
-            )
-            .field(
-                "xtal32k_auto_backup",
-                &format_args!("{}", self.xtal32k_auto_backup().bit()),
-            )
-            .field(
-                "xtal32k_auto_restart",
-                &format_args!("{}", self.xtal32k_auto_restart().bit()),
-            )
-            .field(
-                "xtal32k_auto_return",
-                &format_args!("{}", self.xtal32k_auto_return().bit()),
-            )
-            .field(
-                "xtal32k_xpd_force",
-                &format_args!("{}", self.xtal32k_xpd_force().bit()),
-            )
-            .field(
-                "enckinit_xtal_32k",
-                &format_args!("{}", self.enckinit_xtal_32k().bit()),
-            )
-            .field(
-                "dbuf_xtal_32k",
-                &format_args!("{}", self.dbuf_xtal_32k().bit()),
-            )
-            .field(
-                "dgm_xtal_32k",
-                &format_args!("{}", self.dgm_xtal_32k().bits()),
-            )
-            .field(
-                "dres_xtal_32k",
-                &format_args!("{}", self.dres_xtal_32k().bits()),
-            )
-            .field(
-                "xpd_xtal_32k",
-                &format_args!("{}", self.xpd_xtal_32k().bit()),
-            )
-            .field(
-                "dac_xtal_32k",
-                &format_args!("{}", self.dac_xtal_32k().bits()),
-            )
-            .field("wdt_state", &format_args!("{}", self.wdt_state().bits()))
-            .field(
-                "xtal32k_gpio_sel",
-                &format_args!("{}", self.xtal32k_gpio_sel().bit()),
-            )
-            .field(
-                "xtl_ext_ctr_lv",
-                &format_args!("{}", self.xtl_ext_ctr_lv().bit()),
-            )
-            .field(
-                "xtl_ext_ctr_en",
-                &format_args!("{}", self.xtl_ext_ctr_en().bit()),
-            )
+            .field("xtal32k_wdt_en", &self.xtal32k_wdt_en())
+            .field("xtal32k_wdt_clk_fo", &self.xtal32k_wdt_clk_fo())
+            .field("xtal32k_wdt_reset", &self.xtal32k_wdt_reset())
+            .field("xtal32k_ext_clk_fo", &self.xtal32k_ext_clk_fo())
+            .field("xtal32k_auto_backup", &self.xtal32k_auto_backup())
+            .field("xtal32k_auto_restart", &self.xtal32k_auto_restart())
+            .field("xtal32k_auto_return", &self.xtal32k_auto_return())
+            .field("xtal32k_xpd_force", &self.xtal32k_xpd_force())
+            .field("enckinit_xtal_32k", &self.enckinit_xtal_32k())
+            .field("dbuf_xtal_32k", &self.dbuf_xtal_32k())
+            .field("dgm_xtal_32k", &self.dgm_xtal_32k())
+            .field("dres_xtal_32k", &self.dres_xtal_32k())
+            .field("xpd_xtal_32k", &self.xpd_xtal_32k())
+            .field("dac_xtal_32k", &self.dac_xtal_32k())
+            .field("wdt_state", &self.wdt_state())
+            .field("xtal32k_gpio_sel", &self.xtal32k_gpio_sel())
+            .field("xtl_ext_ctr_lv", &self.xtl_ext_ctr_lv())
+            .field("xtl_ext_ctr_en", &self.xtl_ext_ctr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_XTL_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable the 32 kHz crystal watchdog."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/int_ena.rs b/esp32s2/src/rtc_cntl/int_ena.rs
index 99411b7315..a545d4622a 100644
--- a/esp32s2/src/rtc_cntl/int_ena.rs
+++ b/esp32s2/src/rtc_cntl/int_ena.rs
@@ -188,50 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field(
-                "touch_scan_done",
-                &format_args!("{}", self.touch_scan_done().bit()),
-            )
-            .field("ulp_cp", &format_args!("{}", self.ulp_cp().bit()))
-            .field("touch_done", &format_args!("{}", self.touch_done().bit()))
-            .field(
-                "touch_active",
-                &format_args!("{}", self.touch_active().bit()),
-            )
-            .field(
-                "touch_inactive",
-                &format_args!("{}", self.touch_inactive().bit()),
-            )
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
-            .field("saradc1", &format_args!("{}", self.saradc1().bit()))
-            .field("tsens", &format_args!("{}", self.tsens().bit()))
-            .field("cocpu", &format_args!("{}", self.cocpu().bit()))
-            .field("saradc2", &format_args!("{}", self.saradc2().bit()))
-            .field("swd", &format_args!("{}", self.swd().bit()))
-            .field(
-                "xtal32k_dead",
-                &format_args!("{}", self.xtal32k_dead().bit()),
-            )
-            .field("cocpu_trap", &format_args!("{}", self.cocpu_trap().bit()))
-            .field(
-                "touch_timeout",
-                &format_args!("{}", self.touch_timeout().bit()),
-            )
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("wdt", &self.wdt())
+            .field("touch_scan_done", &self.touch_scan_done())
+            .field("ulp_cp", &self.ulp_cp())
+            .field("touch_done", &self.touch_done())
+            .field("touch_active", &self.touch_active())
+            .field("touch_inactive", &self.touch_inactive())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("saradc1", &self.saradc1())
+            .field("tsens", &self.tsens())
+            .field("cocpu", &self.cocpu())
+            .field("saradc2", &self.saradc2())
+            .field("swd", &self.swd())
+            .field("xtal32k_dead", &self.xtal32k_dead())
+            .field("cocpu_trap", &self.cocpu_trap())
+            .field("touch_timeout", &self.touch_timeout())
+            .field("glitch_det", &self.glitch_det())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enables interruption when the chip wakes up from sleep."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/int_raw.rs b/esp32s2/src/rtc_cntl/int_raw.rs
index 155201a8c4..53efc8c5c3 100644
--- a/esp32s2/src/rtc_cntl/int_raw.rs
+++ b/esp32s2/src/rtc_cntl/int_raw.rs
@@ -146,50 +146,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field(
-                "touch_scan_done",
-                &format_args!("{}", self.touch_scan_done().bit()),
-            )
-            .field("ulp_cp", &format_args!("{}", self.ulp_cp().bit()))
-            .field("touch_done", &format_args!("{}", self.touch_done().bit()))
-            .field(
-                "touch_active",
-                &format_args!("{}", self.touch_active().bit()),
-            )
-            .field(
-                "touch_inactive",
-                &format_args!("{}", self.touch_inactive().bit()),
-            )
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
-            .field("saradc1", &format_args!("{}", self.saradc1().bit()))
-            .field("tsens", &format_args!("{}", self.tsens().bit()))
-            .field("cocpu", &format_args!("{}", self.cocpu().bit()))
-            .field("saradc2", &format_args!("{}", self.saradc2().bit()))
-            .field("swd", &format_args!("{}", self.swd().bit()))
-            .field(
-                "xtal32k_dead",
-                &format_args!("{}", self.xtal32k_dead().bit()),
-            )
-            .field("cocpu_trap", &format_args!("{}", self.cocpu_trap().bit()))
-            .field(
-                "touch_timeout",
-                &format_args!("{}", self.touch_timeout().bit()),
-            )
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("wdt", &self.wdt())
+            .field("touch_scan_done", &self.touch_scan_done())
+            .field("ulp_cp", &self.ulp_cp())
+            .field("touch_done", &self.touch_done())
+            .field("touch_active", &self.touch_active())
+            .field("touch_inactive", &self.touch_inactive())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("saradc1", &self.saradc1())
+            .field("tsens", &self.tsens())
+            .field("cocpu", &self.cocpu())
+            .field("saradc2", &self.saradc2())
+            .field("swd", &self.swd())
+            .field("xtal32k_dead", &self.xtal32k_dead())
+            .field("cocpu_trap", &self.cocpu_trap())
+            .field("touch_timeout", &self.touch_timeout())
+            .field("glitch_det", &self.glitch_det())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s2/src/rtc_cntl/int_st.rs b/esp32s2/src/rtc_cntl/int_st.rs
index 9d01e6a05c..114404b272 100644
--- a/esp32s2/src/rtc_cntl/int_st.rs
+++ b/esp32s2/src/rtc_cntl/int_st.rs
@@ -146,50 +146,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field(
-                "touch_scan_done",
-                &format_args!("{}", self.touch_scan_done().bit()),
-            )
-            .field("ulp_cp", &format_args!("{}", self.ulp_cp().bit()))
-            .field("touch_done", &format_args!("{}", self.touch_done().bit()))
-            .field(
-                "touch_active",
-                &format_args!("{}", self.touch_active().bit()),
-            )
-            .field(
-                "touch_inactive",
-                &format_args!("{}", self.touch_inactive().bit()),
-            )
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
-            .field("saradc1", &format_args!("{}", self.saradc1().bit()))
-            .field("tsens", &format_args!("{}", self.tsens().bit()))
-            .field("cocpu", &format_args!("{}", self.cocpu().bit()))
-            .field("saradc2", &format_args!("{}", self.saradc2().bit()))
-            .field("swd", &format_args!("{}", self.swd().bit()))
-            .field(
-                "xtal32k_dead",
-                &format_args!("{}", self.xtal32k_dead().bit()),
-            )
-            .field("cocpu_trap", &format_args!("{}", self.cocpu_trap().bit()))
-            .field(
-                "touch_timeout",
-                &format_args!("{}", self.touch_timeout().bit()),
-            )
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("wdt", &self.wdt())
+            .field("touch_scan_done", &self.touch_scan_done())
+            .field("ulp_cp", &self.ulp_cp())
+            .field("touch_done", &self.touch_done())
+            .field("touch_active", &self.touch_active())
+            .field("touch_inactive", &self.touch_inactive())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("saradc1", &self.saradc1())
+            .field("tsens", &self.tsens())
+            .field("cocpu", &self.cocpu())
+            .field("saradc2", &self.saradc2())
+            .field("swd", &self.swd())
+            .field("xtal32k_dead", &self.xtal32k_dead())
+            .field("cocpu_trap", &self.cocpu_trap())
+            .field("touch_timeout", &self.touch_timeout())
+            .field("glitch_det", &self.glitch_det())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC interrupt state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s2/src/rtc_cntl/low_power_st.rs b/esp32s2/src/rtc_cntl/low_power_st.rs
index 2ec54a4f23..387ff5f2bf 100644
--- a/esp32s2/src/rtc_cntl/low_power_st.rs
+++ b/esp32s2/src/rtc_cntl/low_power_st.rs
@@ -202,106 +202,37 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOW_POWER_ST")
-            .field("xpd_rom0", &format_args!("{}", self.xpd_rom0().bit()))
-            .field(
-                "xpd_dig_dcdc",
-                &format_args!("{}", self.xpd_dig_dcdc().bit()),
-            )
-            .field("peri_iso", &format_args!("{}", self.peri_iso().bit()))
-            .field(
-                "xpd_rtc_peri",
-                &format_args!("{}", self.xpd_rtc_peri().bit()),
-            )
-            .field("wifi_iso", &format_args!("{}", self.wifi_iso().bit()))
-            .field("xpd_wifi", &format_args!("{}", self.xpd_wifi().bit()))
-            .field("dig_iso", &format_args!("{}", self.dig_iso().bit()))
-            .field("xpd_dig", &format_args!("{}", self.xpd_dig().bit()))
-            .field(
-                "touch_state_start",
-                &format_args!("{}", self.touch_state_start().bit()),
-            )
-            .field(
-                "touch_state_switch",
-                &format_args!("{}", self.touch_state_switch().bit()),
-            )
-            .field(
-                "touch_state_slp",
-                &format_args!("{}", self.touch_state_slp().bit()),
-            )
-            .field(
-                "touch_state_done",
-                &format_args!("{}", self.touch_state_done().bit()),
-            )
-            .field(
-                "cocpu_state_start",
-                &format_args!("{}", self.cocpu_state_start().bit()),
-            )
-            .field(
-                "cocpu_state_switch",
-                &format_args!("{}", self.cocpu_state_switch().bit()),
-            )
-            .field(
-                "cocpu_state_slp",
-                &format_args!("{}", self.cocpu_state_slp().bit()),
-            )
-            .field(
-                "cocpu_state_done",
-                &format_args!("{}", self.cocpu_state_done().bit()),
-            )
-            .field(
-                "main_state_xtal_iso",
-                &format_args!("{}", self.main_state_xtal_iso().bit()),
-            )
-            .field(
-                "main_state_pll_on",
-                &format_args!("{}", self.main_state_pll_on().bit()),
-            )
-            .field(
-                "rdy_for_wakeup",
-                &format_args!("{}", self.rdy_for_wakeup().bit()),
-            )
-            .field(
-                "main_state_wait_end",
-                &format_args!("{}", self.main_state_wait_end().bit()),
-            )
-            .field(
-                "in_wakeup_state",
-                &format_args!("{}", self.in_wakeup_state().bit()),
-            )
-            .field(
-                "in_low_power_state",
-                &format_args!("{}", self.in_low_power_state().bit()),
-            )
-            .field(
-                "main_state_in_wait_8m",
-                &format_args!("{}", self.main_state_in_wait_8m().bit()),
-            )
-            .field(
-                "main_state_in_wait_pll",
-                &format_args!("{}", self.main_state_in_wait_pll().bit()),
-            )
-            .field(
-                "main_state_in_wait_xtl",
-                &format_args!("{}", self.main_state_in_wait_xtl().bit()),
-            )
-            .field(
-                "main_state_in_slp",
-                &format_args!("{}", self.main_state_in_slp().bit()),
-            )
-            .field(
-                "main_state_in_idle",
-                &format_args!("{}", self.main_state_in_idle().bit()),
-            )
-            .field("main_state", &format_args!("{}", self.main_state().bits()))
+            .field("xpd_rom0", &self.xpd_rom0())
+            .field("xpd_dig_dcdc", &self.xpd_dig_dcdc())
+            .field("peri_iso", &self.peri_iso())
+            .field("xpd_rtc_peri", &self.xpd_rtc_peri())
+            .field("wifi_iso", &self.wifi_iso())
+            .field("xpd_wifi", &self.xpd_wifi())
+            .field("dig_iso", &self.dig_iso())
+            .field("xpd_dig", &self.xpd_dig())
+            .field("touch_state_start", &self.touch_state_start())
+            .field("touch_state_switch", &self.touch_state_switch())
+            .field("touch_state_slp", &self.touch_state_slp())
+            .field("touch_state_done", &self.touch_state_done())
+            .field("cocpu_state_start", &self.cocpu_state_start())
+            .field("cocpu_state_switch", &self.cocpu_state_switch())
+            .field("cocpu_state_slp", &self.cocpu_state_slp())
+            .field("cocpu_state_done", &self.cocpu_state_done())
+            .field("main_state_xtal_iso", &self.main_state_xtal_iso())
+            .field("main_state_pll_on", &self.main_state_pll_on())
+            .field("rdy_for_wakeup", &self.rdy_for_wakeup())
+            .field("main_state_wait_end", &self.main_state_wait_end())
+            .field("in_wakeup_state", &self.in_wakeup_state())
+            .field("in_low_power_state", &self.in_low_power_state())
+            .field("main_state_in_wait_8m", &self.main_state_in_wait_8m())
+            .field("main_state_in_wait_pll", &self.main_state_in_wait_pll())
+            .field("main_state_in_wait_xtl", &self.main_state_in_wait_xtl())
+            .field("main_state_in_slp", &self.main_state_in_slp())
+            .field("main_state_in_idle", &self.main_state_in_idle())
+            .field("main_state", &self.main_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOW_POWER_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC main state machine status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`low_power_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOW_POWER_ST_SPEC;
 impl crate::RegisterSpec for LOW_POWER_ST_SPEC {
diff --git a/esp32s2/src/rtc_cntl/options0.rs b/esp32s2/src/rtc_cntl/options0.rs
index 822fe1f137..4d0cb5e2b7 100644
--- a/esp32s2/src/rtc_cntl/options0.rs
+++ b/esp32s2/src/rtc_cntl/options0.rs
@@ -176,87 +176,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OPTIONS0")
-            .field(
-                "sw_stall_appcpu_c0",
-                &format_args!("{}", self.sw_stall_appcpu_c0().bits()),
-            )
-            .field(
-                "sw_stall_procpu_c0",
-                &format_args!("{}", self.sw_stall_procpu_c0().bits()),
-            )
-            .field(
-                "bb_i2c_force_pd",
-                &format_args!("{}", self.bb_i2c_force_pd().bit()),
-            )
-            .field(
-                "bb_i2c_force_pu",
-                &format_args!("{}", self.bb_i2c_force_pu().bit()),
-            )
-            .field(
-                "bbpll_i2c_force_pd",
-                &format_args!("{}", self.bbpll_i2c_force_pd().bit()),
-            )
-            .field(
-                "bbpll_i2c_force_pu",
-                &format_args!("{}", self.bbpll_i2c_force_pu().bit()),
-            )
-            .field(
-                "bbpll_force_pd",
-                &format_args!("{}", self.bbpll_force_pd().bit()),
-            )
-            .field(
-                "bbpll_force_pu",
-                &format_args!("{}", self.bbpll_force_pu().bit()),
-            )
-            .field(
-                "xtl_force_pd",
-                &format_args!("{}", self.xtl_force_pd().bit()),
-            )
-            .field(
-                "xtl_force_pu",
-                &format_args!("{}", self.xtl_force_pu().bit()),
-            )
-            .field(
-                "xtl_force_iso",
-                &format_args!("{}", self.xtl_force_iso().bit()),
-            )
-            .field(
-                "pll_force_iso",
-                &format_args!("{}", self.pll_force_iso().bit()),
-            )
-            .field(
-                "analog_force_iso",
-                &format_args!("{}", self.analog_force_iso().bit()),
-            )
-            .field(
-                "xtl_force_noiso",
-                &format_args!("{}", self.xtl_force_noiso().bit()),
-            )
-            .field(
-                "pll_force_noiso",
-                &format_args!("{}", self.pll_force_noiso().bit()),
-            )
-            .field(
-                "analog_force_noiso",
-                &format_args!("{}", self.analog_force_noiso().bit()),
-            )
-            .field(
-                "dg_wrap_force_rst",
-                &format_args!("{}", self.dg_wrap_force_rst().bit()),
-            )
-            .field(
-                "dg_wrap_force_norst",
-                &format_args!("{}", self.dg_wrap_force_norst().bit()),
-            )
+            .field("sw_stall_appcpu_c0", &self.sw_stall_appcpu_c0())
+            .field("sw_stall_procpu_c0", &self.sw_stall_procpu_c0())
+            .field("bb_i2c_force_pd", &self.bb_i2c_force_pd())
+            .field("bb_i2c_force_pu", &self.bb_i2c_force_pu())
+            .field("bbpll_i2c_force_pd", &self.bbpll_i2c_force_pd())
+            .field("bbpll_i2c_force_pu", &self.bbpll_i2c_force_pu())
+            .field("bbpll_force_pd", &self.bbpll_force_pd())
+            .field("bbpll_force_pu", &self.bbpll_force_pu())
+            .field("xtl_force_pd", &self.xtl_force_pd())
+            .field("xtl_force_pu", &self.xtl_force_pu())
+            .field("xtl_force_iso", &self.xtl_force_iso())
+            .field("pll_force_iso", &self.pll_force_iso())
+            .field("analog_force_iso", &self.analog_force_iso())
+            .field("xtl_force_noiso", &self.xtl_force_noiso())
+            .field("pll_force_noiso", &self.pll_force_noiso())
+            .field("analog_force_noiso", &self.analog_force_noiso())
+            .field("dg_wrap_force_rst", &self.dg_wrap_force_rst())
+            .field("dg_wrap_force_norst", &self.dg_wrap_force_norst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OPTIONS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - {reg_sw_stall_appcpu_c1\\[5:0\\] , reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/options1.rs b/esp32s2/src/rtc_cntl/options1.rs
index 31ac48511d..d478426ae6 100644
--- a/esp32s2/src/rtc_cntl/options1.rs
+++ b/esp32s2/src/rtc_cntl/options1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OPTIONS1")
-            .field(
-                "force_download_boot",
-                &format_args!("{}", self.force_download_boot().bit()),
-            )
+            .field("force_download_boot", &self.force_download_boot())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OPTIONS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to force the chip to boot from the download mode."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/pad_hold.rs b/esp32s2/src/rtc_cntl/pad_hold.rs
index 1fabfd5e16..78527917fa 100644
--- a/esp32s2/src/rtc_cntl/pad_hold.rs
+++ b/esp32s2/src/rtc_cntl/pad_hold.rs
@@ -206,82 +206,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_HOLD")
-            .field(
-                "touch_pad0_hold",
-                &format_args!("{}", self.touch_pad0_hold().bit()),
-            )
-            .field(
-                "touch_pad1_hold",
-                &format_args!("{}", self.touch_pad1_hold().bit()),
-            )
-            .field(
-                "touch_pad2_hold",
-                &format_args!("{}", self.touch_pad2_hold().bit()),
-            )
-            .field(
-                "touch_pad3_hold",
-                &format_args!("{}", self.touch_pad3_hold().bit()),
-            )
-            .field(
-                "touch_pad4_hold",
-                &format_args!("{}", self.touch_pad4_hold().bit()),
-            )
-            .field(
-                "touch_pad5_hold",
-                &format_args!("{}", self.touch_pad5_hold().bit()),
-            )
-            .field(
-                "touch_pad6_hold",
-                &format_args!("{}", self.touch_pad6_hold().bit()),
-            )
-            .field(
-                "touch_pad7_hold",
-                &format_args!("{}", self.touch_pad7_hold().bit()),
-            )
-            .field(
-                "touch_pad8_hold",
-                &format_args!("{}", self.touch_pad8_hold().bit()),
-            )
-            .field(
-                "touch_pad9_hold",
-                &format_args!("{}", self.touch_pad9_hold().bit()),
-            )
-            .field(
-                "touch_pad10_hold",
-                &format_args!("{}", self.touch_pad10_hold().bit()),
-            )
-            .field(
-                "touch_pad11_hold",
-                &format_args!("{}", self.touch_pad11_hold().bit()),
-            )
-            .field(
-                "touch_pad12_hold",
-                &format_args!("{}", self.touch_pad12_hold().bit()),
-            )
-            .field(
-                "touch_pad13_hold",
-                &format_args!("{}", self.touch_pad13_hold().bit()),
-            )
-            .field(
-                "touch_pad14_hold",
-                &format_args!("{}", self.touch_pad14_hold().bit()),
-            )
-            .field("x32p_hold", &format_args!("{}", self.x32p_hold().bit()))
-            .field("x32n_hold", &format_args!("{}", self.x32n_hold().bit()))
-            .field("pdac1_hold", &format_args!("{}", self.pdac1_hold().bit()))
-            .field("pdac2_hold", &format_args!("{}", self.pdac2_hold().bit()))
-            .field("pad19_hold", &format_args!("{}", self.pad19_hold().bit()))
-            .field("pad20_hold", &format_args!("{}", self.pad20_hold().bit()))
-            .field("pad21_hold", &format_args!("{}", self.pad21_hold().bit()))
+            .field("touch_pad0_hold", &self.touch_pad0_hold())
+            .field("touch_pad1_hold", &self.touch_pad1_hold())
+            .field("touch_pad2_hold", &self.touch_pad2_hold())
+            .field("touch_pad3_hold", &self.touch_pad3_hold())
+            .field("touch_pad4_hold", &self.touch_pad4_hold())
+            .field("touch_pad5_hold", &self.touch_pad5_hold())
+            .field("touch_pad6_hold", &self.touch_pad6_hold())
+            .field("touch_pad7_hold", &self.touch_pad7_hold())
+            .field("touch_pad8_hold", &self.touch_pad8_hold())
+            .field("touch_pad9_hold", &self.touch_pad9_hold())
+            .field("touch_pad10_hold", &self.touch_pad10_hold())
+            .field("touch_pad11_hold", &self.touch_pad11_hold())
+            .field("touch_pad12_hold", &self.touch_pad12_hold())
+            .field("touch_pad13_hold", &self.touch_pad13_hold())
+            .field("touch_pad14_hold", &self.touch_pad14_hold())
+            .field("x32p_hold", &self.x32p_hold())
+            .field("x32n_hold", &self.x32n_hold())
+            .field("pdac1_hold", &self.pdac1_hold())
+            .field("pdac2_hold", &self.pdac2_hold())
+            .field("pad19_hold", &self.pad19_hold())
+            .field("pad20_hold", &self.pad20_hold())
+            .field("pad21_hold", &self.pad21_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Sets the touch GPIO 0 to hold."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/pwc.rs b/esp32s2/src/rtc_cntl/pwc.rs
index f7689ce549..ebf51d2ddc 100644
--- a/esp32s2/src/rtc_cntl/pwc.rs
+++ b/esp32s2/src/rtc_cntl/pwc.rs
@@ -206,88 +206,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWC")
-            .field(
-                "fastmem_force_noiso",
-                &format_args!("{}", self.fastmem_force_noiso().bit()),
-            )
-            .field(
-                "fastmem_force_iso",
-                &format_args!("{}", self.fastmem_force_iso().bit()),
-            )
-            .field(
-                "slowmem_force_noiso",
-                &format_args!("{}", self.slowmem_force_noiso().bit()),
-            )
-            .field(
-                "slowmem_force_iso",
-                &format_args!("{}", self.slowmem_force_iso().bit()),
-            )
-            .field("force_iso", &format_args!("{}", self.force_iso().bit()))
-            .field("force_noiso", &format_args!("{}", self.force_noiso().bit()))
-            .field(
-                "fastmem_folw_cpu",
-                &format_args!("{}", self.fastmem_folw_cpu().bit()),
-            )
-            .field(
-                "fastmem_force_lpd",
-                &format_args!("{}", self.fastmem_force_lpd().bit()),
-            )
-            .field(
-                "fastmem_force_lpu",
-                &format_args!("{}", self.fastmem_force_lpu().bit()),
-            )
-            .field(
-                "slowmem_folw_cpu",
-                &format_args!("{}", self.slowmem_folw_cpu().bit()),
-            )
-            .field(
-                "slowmem_force_lpd",
-                &format_args!("{}", self.slowmem_force_lpd().bit()),
-            )
-            .field(
-                "slowmem_force_lpu",
-                &format_args!("{}", self.slowmem_force_lpu().bit()),
-            )
-            .field(
-                "fastmem_force_pd",
-                &format_args!("{}", self.fastmem_force_pd().bit()),
-            )
-            .field(
-                "fastmem_force_pu",
-                &format_args!("{}", self.fastmem_force_pu().bit()),
-            )
-            .field(
-                "fastmem_pd_en",
-                &format_args!("{}", self.fastmem_pd_en().bit()),
-            )
-            .field(
-                "slowmem_force_pd",
-                &format_args!("{}", self.slowmem_force_pd().bit()),
-            )
-            .field(
-                "slowmem_force_pu",
-                &format_args!("{}", self.slowmem_force_pu().bit()),
-            )
-            .field(
-                "slowmem_pd_en",
-                &format_args!("{}", self.slowmem_pd_en().bit()),
-            )
-            .field("force_pd", &format_args!("{}", self.force_pd().bit()))
-            .field("force_pu", &format_args!("{}", self.force_pu().bit()))
-            .field("pd_en", &format_args!("{}", self.pd_en().bit()))
-            .field(
-                "pad_force_hold",
-                &format_args!("{}", self.pad_force_hold().bit()),
-            )
+            .field("fastmem_force_noiso", &self.fastmem_force_noiso())
+            .field("fastmem_force_iso", &self.fastmem_force_iso())
+            .field("slowmem_force_noiso", &self.slowmem_force_noiso())
+            .field("slowmem_force_iso", &self.slowmem_force_iso())
+            .field("force_iso", &self.force_iso())
+            .field("force_noiso", &self.force_noiso())
+            .field("fastmem_folw_cpu", &self.fastmem_folw_cpu())
+            .field("fastmem_force_lpd", &self.fastmem_force_lpd())
+            .field("fastmem_force_lpu", &self.fastmem_force_lpu())
+            .field("slowmem_folw_cpu", &self.slowmem_folw_cpu())
+            .field("slowmem_force_lpd", &self.slowmem_force_lpd())
+            .field("slowmem_force_lpu", &self.slowmem_force_lpu())
+            .field("fastmem_force_pd", &self.fastmem_force_pd())
+            .field("fastmem_force_pu", &self.fastmem_force_pu())
+            .field("fastmem_pd_en", &self.fastmem_pd_en())
+            .field("slowmem_force_pd", &self.slowmem_force_pd())
+            .field("slowmem_force_pu", &self.slowmem_force_pu())
+            .field("slowmem_pd_en", &self.slowmem_pd_en())
+            .field("force_pd", &self.force_pd())
+            .field("force_pu", &self.force_pu())
+            .field("pd_en", &self.pd_en())
+            .field("pad_force_hold", &self.pad_force_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to disable the force isolation to the RTC fast memory."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/reg.rs b/esp32s2/src/rtc_cntl/reg.rs
index c21f48b1fb..7e79f3cd6d 100644
--- a/esp32s2/src/rtc_cntl/reg.rs
+++ b/esp32s2/src/rtc_cntl/reg.rs
@@ -89,42 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG")
-            .field(
-                "dig_reg_dbias_slp",
-                &format_args!("{}", self.dig_reg_dbias_slp().bits()),
-            )
-            .field(
-                "dig_reg_dbias_wak",
-                &format_args!("{}", self.dig_reg_dbias_wak().bits()),
-            )
-            .field("sck_dcap", &format_args!("{}", self.sck_dcap().bits()))
-            .field("dbias_slp", &format_args!("{}", self.dbias_slp().bits()))
-            .field("dbias_wak", &format_args!("{}", self.dbias_wak().bits()))
-            .field(
-                "dboost_force_pd",
-                &format_args!("{}", self.dboost_force_pd().bit()),
-            )
-            .field(
-                "dboost_force_pu",
-                &format_args!("{}", self.dboost_force_pu().bit()),
-            )
-            .field(
-                "regulator_force_pd",
-                &format_args!("{}", self.regulator_force_pd().bit()),
-            )
-            .field(
-                "regulator_force_pu",
-                &format_args!("{}", self.regulator_force_pu().bit()),
-            )
+            .field("dig_reg_dbias_slp", &self.dig_reg_dbias_slp())
+            .field("dig_reg_dbias_wak", &self.dig_reg_dbias_wak())
+            .field("sck_dcap", &self.sck_dcap())
+            .field("dbias_slp", &self.dbias_slp())
+            .field("dbias_wak", &self.dbias_wak())
+            .field("dboost_force_pd", &self.dboost_force_pd())
+            .field("dboost_force_pu", &self.dboost_force_pu())
+            .field("regulator_force_pd", &self.regulator_force_pd())
+            .field("regulator_force_pu", &self.regulator_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:10 - Configures the regulation factor for the digital system voltage regulator when the CPU is in sleep status."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/reset_state.rs b/esp32s2/src/rtc_cntl/reset_state.rs
index d532c6cc0f..e3829b2c4f 100644
--- a/esp32s2/src/rtc_cntl/reset_state.rs
+++ b/esp32s2/src/rtc_cntl/reset_state.rs
@@ -40,31 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET_STATE")
-            .field(
-                "reset_cause_procpu",
-                &format_args!("{}", self.reset_cause_procpu().bits()),
-            )
-            .field(
-                "reset_cause_appcpu",
-                &format_args!("{}", self.reset_cause_appcpu().bits()),
-            )
-            .field(
-                "appcpu_stat_vector_sel",
-                &format_args!("{}", self.appcpu_stat_vector_sel().bit()),
-            )
-            .field(
-                "procpu_stat_vector_sel",
-                &format_args!("{}", self.procpu_stat_vector_sel().bit()),
-            )
+            .field("reset_cause_procpu", &self.reset_cause_procpu())
+            .field("reset_cause_appcpu", &self.reset_cause_appcpu())
+            .field("appcpu_stat_vector_sel", &self.appcpu_stat_vector_sel())
+            .field("procpu_stat_vector_sel", &self.procpu_stat_vector_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - APP CPU state vector sel"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/sdio_act_conf.rs b/esp32s2/src/rtc_cntl/sdio_act_conf.rs
index 4ce8939e35..8ec0d53243 100644
--- a/esp32s2/src/rtc_cntl/sdio_act_conf.rs
+++ b/esp32s2/src/rtc_cntl/sdio_act_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_ACT_CONF")
-            .field(
-                "sdio_act_dnum",
-                &format_args!("{}", self.sdio_act_dnum().bits()),
-            )
+            .field("sdio_act_dnum", &self.sdio_act_dnum())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_ACT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:31 - configure sdio act dnum"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/sdio_conf.rs b/esp32s2/src/rtc_cntl/sdio_conf.rs
index cd4f6463ae..3ec0025b18 100644
--- a/esp32s2/src/rtc_cntl/sdio_conf.rs
+++ b/esp32s2/src/rtc_cntl/sdio_conf.rs
@@ -150,55 +150,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_CONF")
-            .field(
-                "sdio_timer_target",
-                &format_args!("{}", self.sdio_timer_target().bits()),
-            )
-            .field(
-                "sdio_dthdrv",
-                &format_args!("{}", self.sdio_dthdrv().bits()),
-            )
-            .field("sdio_dcap", &format_args!("{}", self.sdio_dcap().bits()))
-            .field("sdio_initi", &format_args!("{}", self.sdio_initi().bits()))
-            .field(
-                "sdio_en_initi",
-                &format_args!("{}", self.sdio_en_initi().bit()),
-            )
-            .field(
-                "sdio_dcurlim",
-                &format_args!("{}", self.sdio_dcurlim().bits()),
-            )
-            .field(
-                "sdio_modecurlim",
-                &format_args!("{}", self.sdio_modecurlim().bit()),
-            )
-            .field(
-                "sdio_encurlim",
-                &format_args!("{}", self.sdio_encurlim().bit()),
-            )
-            .field(
-                "sdio_reg_pd_en",
-                &format_args!("{}", self.sdio_reg_pd_en().bit()),
-            )
-            .field("sdio_force", &format_args!("{}", self.sdio_force().bit()))
-            .field("sdio_tieh", &format_args!("{}", self.sdio_tieh().bit()))
-            .field(
-                "reg1p8_ready",
-                &format_args!("{}", self.reg1p8_ready().bit()),
-            )
-            .field("drefl_sdio", &format_args!("{}", self.drefl_sdio().bits()))
-            .field("drefm_sdio", &format_args!("{}", self.drefm_sdio().bits()))
-            .field("drefh_sdio", &format_args!("{}", self.drefh_sdio().bits()))
-            .field("xpd_sdio", &format_args!("{}", self.xpd_sdio().bit()))
+            .field("sdio_timer_target", &self.sdio_timer_target())
+            .field("sdio_dthdrv", &self.sdio_dthdrv())
+            .field("sdio_dcap", &self.sdio_dcap())
+            .field("sdio_initi", &self.sdio_initi())
+            .field("sdio_en_initi", &self.sdio_en_initi())
+            .field("sdio_dcurlim", &self.sdio_dcurlim())
+            .field("sdio_modecurlim", &self.sdio_modecurlim())
+            .field("sdio_encurlim", &self.sdio_encurlim())
+            .field("sdio_reg_pd_en", &self.sdio_reg_pd_en())
+            .field("sdio_force", &self.sdio_force())
+            .field("sdio_tieh", &self.sdio_tieh())
+            .field("reg1p8_ready", &self.reg1p8_ready())
+            .field("drefl_sdio", &self.drefl_sdio())
+            .field("drefm_sdio", &self.drefm_sdio())
+            .field("drefh_sdio", &self.drefh_sdio())
+            .field("xpd_sdio", &self.xpd_sdio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - timer count to apply reg_sdio_dcap after sdio power on"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/slow_clk_conf.rs b/esp32s2/src/rtc_cntl/slow_clk_conf.rs
index f3d84b8586..6a70c647ec 100644
--- a/esp32s2/src/rtc_cntl/slow_clk_conf.rs
+++ b/esp32s2/src/rtc_cntl/slow_clk_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLOW_CLK_CONF")
-            .field(
-                "ana_clk_div_vld",
-                &format_args!("{}", self.ana_clk_div_vld().bit()),
-            )
-            .field(
-                "ana_clk_div",
-                &format_args!("{}", self.ana_clk_div().bits()),
-            )
-            .field(
-                "slow_clk_next_edge",
-                &format_args!("{}", self.slow_clk_next_edge().bit()),
-            )
+            .field("ana_clk_div_vld", &self.ana_clk_div_vld())
+            .field("ana_clk_div", &self.ana_clk_div())
+            .field("slow_clk_next_edge", &self.slow_clk_next_edge())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLOW_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 22 - Synchronizes the reg_rtc_ana_clk_div bus. Note that you have to invalidate the bus before switching clock, and validate the new clock."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/slp_reject_cause.rs b/esp32s2/src/rtc_cntl/slp_reject_cause.rs
index b28bcf162a..aa91cb16ed 100644
--- a/esp32s2/src/rtc_cntl/slp_reject_cause.rs
+++ b/esp32s2/src/rtc_cntl/slp_reject_cause.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_REJECT_CAUSE")
-            .field(
-                "reject_cause",
-                &format_args!("{}", self.reject_cause().bits()),
-            )
+            .field("reject_cause", &self.reject_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_REJECT_CAUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Stores the reject-to-sleep cause.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_reject_cause::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLP_REJECT_CAUSE_SPEC;
 impl crate::RegisterSpec for SLP_REJECT_CAUSE_SPEC {
diff --git a/esp32s2/src/rtc_cntl/slp_reject_conf.rs b/esp32s2/src/rtc_cntl/slp_reject_conf.rs
index e9e39ca9ac..31ea39c1c6 100644
--- a/esp32s2/src/rtc_cntl/slp_reject_conf.rs
+++ b/esp32s2/src/rtc_cntl/slp_reject_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_REJECT_CONF")
-            .field(
-                "sleep_reject_ena",
-                &format_args!("{}", self.sleep_reject_ena().bits()),
-            )
-            .field(
-                "light_slp_reject_en",
-                &format_args!("{}", self.light_slp_reject_en().bit()),
-            )
-            .field(
-                "deep_slp_reject_en",
-                &format_args!("{}", self.deep_slp_reject_en().bit()),
-            )
+            .field("sleep_reject_ena", &self.sleep_reject_ena())
+            .field("light_slp_reject_en", &self.light_slp_reject_en())
+            .field("deep_slp_reject_en", &self.deep_slp_reject_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_REJECT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 13:29 - Set this bit to enable reject-to-sleep."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/slp_timer0.rs b/esp32s2/src/rtc_cntl/slp_timer0.rs
index 9678eb6550..a89cda1fe7 100644
--- a/esp32s2/src/rtc_cntl/slp_timer0.rs
+++ b/esp32s2/src/rtc_cntl/slp_timer0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_TIMER0")
-            .field("slp_val_lo", &format_args!("{}", self.slp_val_lo().bits()))
+            .field("slp_val_lo", &self.slp_val_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_TIMER0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Sets the lower 32 bits of the trigger threshold for the RTC timer."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/slp_timer1.rs b/esp32s2/src/rtc_cntl/slp_timer1.rs
index a7e5e614f0..bfb56672c4 100644
--- a/esp32s2/src/rtc_cntl/slp_timer1.rs
+++ b/esp32s2/src/rtc_cntl/slp_timer1.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_TIMER1")
-            .field("slp_val_hi", &format_args!("{}", self.slp_val_hi().bits()))
+            .field("slp_val_hi", &self.slp_val_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_TIMER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Sets the higher 16 bits of the trigger threshold for the RTC timer."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/slp_wakeup_cause.rs b/esp32s2/src/rtc_cntl/slp_wakeup_cause.rs
index 7c7f0afb5f..8268080f1a 100644
--- a/esp32s2/src/rtc_cntl/slp_wakeup_cause.rs
+++ b/esp32s2/src/rtc_cntl/slp_wakeup_cause.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CAUSE")
-            .field(
-                "wakeup_cause",
-                &format_args!("{}", self.wakeup_cause().bits()),
-            )
+            .field("wakeup_cause", &self.wakeup_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CAUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Stores the sleep-to-wakeup cause.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cause::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLP_WAKEUP_CAUSE_SPEC;
 impl crate::RegisterSpec for SLP_WAKEUP_CAUSE_SPEC {
diff --git a/esp32s2/src/rtc_cntl/state0.rs b/esp32s2/src/rtc_cntl/state0.rs
index df28bb3d3b..a60daf3a63 100644
--- a/esp32s2/src/rtc_cntl/state0.rs
+++ b/esp32s2/src/rtc_cntl/state0.rs
@@ -55,26 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE0")
-            .field(
-                "apb2rtc_bridge_sel",
-                &format_args!("{}", self.apb2rtc_bridge_sel().bit()),
-            )
-            .field(
-                "sdio_active_ind",
-                &format_args!("{}", self.sdio_active_ind().bit()),
-            )
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("sleep_en", &format_args!("{}", self.sleep_en().bit()))
+            .field("apb2rtc_bridge_sel", &self.apb2rtc_bridge_sel())
+            .field("sdio_active_ind", &self.sdio_active_ind())
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sleep_en", &self.sleep_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Sends a SW RTC interrupt to CPU."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/store0.rs b/esp32s2/src/rtc_cntl/store0.rs
index d56770e18d..383e0da2eb 100644
--- a/esp32s2/src/rtc_cntl/store0.rs
+++ b/esp32s2/src/rtc_cntl/store0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE0")
-            .field("scratch0", &format_args!("{}", self.scratch0().bits()))
+            .field("scratch0", &self.scratch0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reservation register 0"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/store1.rs b/esp32s2/src/rtc_cntl/store1.rs
index eec77f4335..b442fc034b 100644
--- a/esp32s2/src/rtc_cntl/store1.rs
+++ b/esp32s2/src/rtc_cntl/store1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE1")
-            .field("scratch1", &format_args!("{}", self.scratch1().bits()))
+            .field("scratch1", &self.scratch1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reservation register 1"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/store2.rs b/esp32s2/src/rtc_cntl/store2.rs
index 9e72524614..3e8e1dc051 100644
--- a/esp32s2/src/rtc_cntl/store2.rs
+++ b/esp32s2/src/rtc_cntl/store2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE2")
-            .field("scratch2", &format_args!("{}", self.scratch2().bits()))
+            .field("scratch2", &self.scratch2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reservation register 2"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/store3.rs b/esp32s2/src/rtc_cntl/store3.rs
index cea03aa129..67f9eae31f 100644
--- a/esp32s2/src/rtc_cntl/store3.rs
+++ b/esp32s2/src/rtc_cntl/store3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE3")
-            .field("scratch3", &format_args!("{}", self.scratch3().bits()))
+            .field("scratch3", &self.scratch3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reservation register 3"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/store4.rs b/esp32s2/src/rtc_cntl/store4.rs
index 21d75465cc..af99ade1da 100644
--- a/esp32s2/src/rtc_cntl/store4.rs
+++ b/esp32s2/src/rtc_cntl/store4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE4")
-            .field("scratch4", &format_args!("{}", self.scratch4().bits()))
+            .field("scratch4", &self.scratch4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reservation register 4."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/store5.rs b/esp32s2/src/rtc_cntl/store5.rs
index e172baf222..30b8155a77 100644
--- a/esp32s2/src/rtc_cntl/store5.rs
+++ b/esp32s2/src/rtc_cntl/store5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE5")
-            .field("scratch5", &format_args!("{}", self.scratch5().bits()))
+            .field("scratch5", &self.scratch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reservation register 5."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/store6.rs b/esp32s2/src/rtc_cntl/store6.rs
index 1ac74f8276..16e39b4125 100644
--- a/esp32s2/src/rtc_cntl/store6.rs
+++ b/esp32s2/src/rtc_cntl/store6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE6")
-            .field("scratch6", &format_args!("{}", self.scratch6().bits()))
+            .field("scratch6", &self.scratch6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reservation register 6."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/store7.rs b/esp32s2/src/rtc_cntl/store7.rs
index 2746580d7e..0d474fe8a4 100644
--- a/esp32s2/src/rtc_cntl/store7.rs
+++ b/esp32s2/src/rtc_cntl/store7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE7")
-            .field("scratch7", &format_args!("{}", self.scratch7().bits()))
+            .field("scratch7", &self.scratch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reservation register 7."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/sw_cpu_stall.rs b/esp32s2/src/rtc_cntl/sw_cpu_stall.rs
index 492812febd..9a1411017b 100644
--- a/esp32s2/src/rtc_cntl/sw_cpu_stall.rs
+++ b/esp32s2/src/rtc_cntl/sw_cpu_stall.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SW_CPU_STALL")
-            .field(
-                "sw_stall_appcpu_c1",
-                &format_args!("{}", self.sw_stall_appcpu_c1().bits()),
-            )
-            .field(
-                "sw_stall_procpu_c1",
-                &format_args!("{}", self.sw_stall_procpu_c1().bits()),
-            )
+            .field("sw_stall_appcpu_c1", &self.sw_stall_appcpu_c1())
+            .field("sw_stall_procpu_c1", &self.sw_stall_procpu_c1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SW_CPU_STALL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:25 - {reg_sw_stall_appcpu_c1\\[5:0\\] reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/swd_conf.rs b/esp32s2/src/rtc_cntl/swd_conf.rs
index a9f0c438c3..8c522a7ad1 100644
--- a/esp32s2/src/rtc_cntl/swd_conf.rs
+++ b/esp32s2/src/rtc_cntl/swd_conf.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_CONF")
-            .field(
-                "swd_reset_flag",
-                &format_args!("{}", self.swd_reset_flag().bit()),
-            )
-            .field(
-                "swd_feed_int",
-                &format_args!("{}", self.swd_feed_int().bit()),
-            )
-            .field(
-                "swd_signal_width",
-                &format_args!("{}", self.swd_signal_width().bits()),
-            )
-            .field("swd_disable", &format_args!("{}", self.swd_disable().bit()))
-            .field(
-                "swd_auto_feed_en",
-                &format_args!("{}", self.swd_auto_feed_en().bit()),
-            )
+            .field("swd_reset_flag", &self.swd_reset_flag())
+            .field("swd_feed_int", &self.swd_feed_int())
+            .field("swd_signal_width", &self.swd_signal_width())
+            .field("swd_disable", &self.swd_disable())
+            .field("swd_auto_feed_en", &self.swd_auto_feed_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 18:27 - Adjusts the signal width sent to the super watchdog."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/swd_wprotect.rs b/esp32s2/src/rtc_cntl/swd_wprotect.rs
index 04500c0141..2bd2352d97 100644
--- a/esp32s2/src/rtc_cntl/swd_wprotect.rs
+++ b/esp32s2/src/rtc_cntl/swd_wprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_WPROTECT")
-            .field("swd_wkey", &format_args!("{}", self.swd_wkey().bits()))
+            .field("swd_wkey", &self.swd_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_WPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Sets the write protection key of the super watchdog."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/time_high0.rs b/esp32s2/src/rtc_cntl/time_high0.rs
index fab03da447..b75b152c21 100644
--- a/esp32s2/src/rtc_cntl/time_high0.rs
+++ b/esp32s2/src/rtc_cntl/time_high0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_HIGH0")
-            .field(
-                "timer_value0_high",
-                &format_args!("{}", self.timer_value0_high().bits()),
-            )
+            .field("timer_value0_high", &self.timer_value0_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_HIGH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Stores the higher 16 bits of RTC timer 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_high0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIME_HIGH0_SPEC;
 impl crate::RegisterSpec for TIME_HIGH0_SPEC {
diff --git a/esp32s2/src/rtc_cntl/time_high1.rs b/esp32s2/src/rtc_cntl/time_high1.rs
index 35c81a08f6..3682f5048d 100644
--- a/esp32s2/src/rtc_cntl/time_high1.rs
+++ b/esp32s2/src/rtc_cntl/time_high1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_HIGH1")
-            .field(
-                "timer_value1_high",
-                &format_args!("{}", self.timer_value1_high().bits()),
-            )
+            .field("timer_value1_high", &self.timer_value1_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_HIGH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Stores the higher 16 bits of RTC timer 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_high1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIME_HIGH1_SPEC;
 impl crate::RegisterSpec for TIME_HIGH1_SPEC {
diff --git a/esp32s2/src/rtc_cntl/time_low0.rs b/esp32s2/src/rtc_cntl/time_low0.rs
index 8d27089e33..a7379003ac 100644
--- a/esp32s2/src/rtc_cntl/time_low0.rs
+++ b/esp32s2/src/rtc_cntl/time_low0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_LOW0")
-            .field(
-                "timer_value0_low",
-                &format_args!("{}", self.timer_value0_low().bits()),
-            )
+            .field("timer_value0_low", &self.timer_value0_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_LOW0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Stores the lower 32 bits of RTC timer 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_low0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIME_LOW0_SPEC;
 impl crate::RegisterSpec for TIME_LOW0_SPEC {
diff --git a/esp32s2/src/rtc_cntl/time_low1.rs b/esp32s2/src/rtc_cntl/time_low1.rs
index 997ac0a3aa..00a541df14 100644
--- a/esp32s2/src/rtc_cntl/time_low1.rs
+++ b/esp32s2/src/rtc_cntl/time_low1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_LOW1")
-            .field(
-                "timer_value1_low",
-                &format_args!("{}", self.timer_value1_low().bits()),
-            )
+            .field("timer_value1_low", &self.timer_value1_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_LOW1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Stores the lower 32 bits of RTC timer 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_low1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIME_LOW1_SPEC;
 impl crate::RegisterSpec for TIME_LOW1_SPEC {
diff --git a/esp32s2/src/rtc_cntl/time_update.rs b/esp32s2/src/rtc_cntl/time_update.rs
index f021344bff..82ee79cf7a 100644
--- a/esp32s2/src/rtc_cntl/time_update.rs
+++ b/esp32s2/src/rtc_cntl/time_update.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_UPDATE")
-            .field(
-                "timer_sys_stall",
-                &format_args!("{}", self.timer_sys_stall().bit()),
-            )
-            .field(
-                "timer_xtl_off",
-                &format_args!("{}", self.timer_xtl_off().bit()),
-            )
-            .field(
-                "timer_sys_rst",
-                &format_args!("{}", self.timer_sys_rst().bit()),
-            )
+            .field("timer_sys_stall", &self.timer_sys_stall())
+            .field("timer_xtl_off", &self.timer_xtl_off())
+            .field("timer_sys_rst", &self.timer_sys_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - Selects the triggering condition for the RTC timer. See details in Table 1-2."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/timer1.rs b/esp32s2/src/rtc_cntl/timer1.rs
index 8384d72a4d..8962fd2698 100644
--- a/esp32s2/src/rtc_cntl/timer1.rs
+++ b/esp32s2/src/rtc_cntl/timer1.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER1")
-            .field(
-                "cpu_stall_en",
-                &format_args!("{}", self.cpu_stall_en().bit()),
-            )
-            .field(
-                "cpu_stall_wait",
-                &format_args!("{}", self.cpu_stall_wait().bits()),
-            )
-            .field("ck8m_wait", &format_args!("{}", self.ck8m_wait().bits()))
-            .field(
-                "xtl_buf_wait",
-                &format_args!("{}", self.xtl_buf_wait().bits()),
-            )
-            .field(
-                "pll_buf_wait",
-                &format_args!("{}", self.pll_buf_wait().bits()),
-            )
+            .field("cpu_stall_en", &self.cpu_stall_en())
+            .field("cpu_stall_wait", &self.cpu_stall_wait())
+            .field("ck8m_wait", &self.ck8m_wait())
+            .field("xtl_buf_wait", &self.xtl_buf_wait())
+            .field("pll_buf_wait", &self.pll_buf_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enables CPU stalling."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/timer2.rs b/esp32s2/src/rtc_cntl/timer2.rs
index 17ffc68be7..b298c47c2a 100644
--- a/esp32s2/src/rtc_cntl/timer2.rs
+++ b/esp32s2/src/rtc_cntl/timer2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER2")
-            .field(
-                "ulpcp_touch_start_wait",
-                &format_args!("{}", self.ulpcp_touch_start_wait().bits()),
-            )
-            .field(
-                "min_time_ck8m_off",
-                &format_args!("{}", self.min_time_ck8m_off().bits()),
-            )
+            .field("ulpcp_touch_start_wait", &self.ulpcp_touch_start_wait())
+            .field("min_time_ck8m_off", &self.min_time_ck8m_off())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 15:23 - Sets the waiting cycle (using the RTC slow clock) before the ULP co-processor / touch controller start to work."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/timer3.rs b/esp32s2/src/rtc_cntl/timer3.rs
index c0d5f049c1..138cf5c69f 100644
--- a/esp32s2/src/rtc_cntl/timer3.rs
+++ b/esp32s2/src/rtc_cntl/timer3.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER3")
-            .field(
-                "wifi_wait_timer",
-                &format_args!("{}", self.wifi_wait_timer().bits()),
-            )
-            .field(
-                "wifi_powerup_timer",
-                &format_args!("{}", self.wifi_powerup_timer().bits()),
-            )
-            .field(
-                "rom_ram_wait_timer",
-                &format_args!("{}", self.rom_ram_wait_timer().bits()),
-            )
-            .field(
-                "rom_ram_powerup_timer",
-                &format_args!("{}", self.rom_ram_powerup_timer().bits()),
-            )
+            .field("wifi_wait_timer", &self.wifi_wait_timer())
+            .field("wifi_powerup_timer", &self.wifi_powerup_timer())
+            .field("rom_ram_wait_timer", &self.rom_ram_wait_timer())
+            .field("rom_ram_powerup_timer", &self.rom_ram_powerup_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/timer4.rs b/esp32s2/src/rtc_cntl/timer4.rs
index 7f440a7969..4bed1116a8 100644
--- a/esp32s2/src/rtc_cntl/timer4.rs
+++ b/esp32s2/src/rtc_cntl/timer4.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER4")
-            .field("wait_timer", &format_args!("{}", self.wait_timer().bits()))
-            .field(
-                "powerup_timer",
-                &format_args!("{}", self.powerup_timer().bits()),
-            )
-            .field(
-                "dg_wrap_wait_timer",
-                &format_args!("{}", self.dg_wrap_wait_timer().bits()),
-            )
-            .field(
-                "dg_wrap_powerup_timer",
-                &format_args!("{}", self.dg_wrap_powerup_timer().bits()),
-            )
+            .field("wait_timer", &self.wait_timer())
+            .field("powerup_timer", &self.powerup_timer())
+            .field("dg_wrap_wait_timer", &self.dg_wrap_wait_timer())
+            .field("dg_wrap_powerup_timer", &self.dg_wrap_powerup_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/timer5.rs b/esp32s2/src/rtc_cntl/timer5.rs
index e819c6551a..6faf2f97df 100644
--- a/esp32s2/src/rtc_cntl/timer5.rs
+++ b/esp32s2/src/rtc_cntl/timer5.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER5")
-            .field(
-                "min_slp_val",
-                &format_args!("{}", self.min_slp_val().bits()),
-            )
-            .field(
-                "rtcmem_wait_timer",
-                &format_args!("{}", self.rtcmem_wait_timer().bits()),
-            )
-            .field(
-                "rtcmem_powerup_timer",
-                &format_args!("{}", self.rtcmem_powerup_timer().bits()),
-            )
+            .field("min_slp_val", &self.min_slp_val())
+            .field("rtcmem_wait_timer", &self.rtcmem_wait_timer())
+            .field("rtcmem_powerup_timer", &self.rtcmem_powerup_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:15 - Sets the minimal sleep cycles (using the RTC slow clock)."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/timer6.rs b/esp32s2/src/rtc_cntl/timer6.rs
index 5517086715..5e62919a49 100644
--- a/esp32s2/src/rtc_cntl/timer6.rs
+++ b/esp32s2/src/rtc_cntl/timer6.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER6")
-            .field(
-                "dg_dcdc_wait_timer",
-                &format_args!("{}", self.dg_dcdc_wait_timer().bits()),
-            )
-            .field(
-                "dg_dcdc_powerup_timer",
-                &format_args!("{}", self.dg_dcdc_powerup_timer().bits()),
-            )
+            .field("dg_dcdc_wait_timer", &self.dg_dcdc_wait_timer())
+            .field("dg_dcdc_powerup_timer", &self.dg_dcdc_powerup_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:24"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/touch_approach.rs b/esp32s2/src/rtc_cntl/touch_approach.rs
index cccba86acc..547f08c6f6 100644
--- a/esp32s2/src/rtc_cntl/touch_approach.rs
+++ b/esp32s2/src/rtc_cntl/touch_approach.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_APPROACH")
-            .field("meas_time", &format_args!("{}", self.meas_time().bits()))
+            .field("meas_time", &self.meas_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_APPROACH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 23 - Clear touch sleep channel."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/touch_ctrl1.rs b/esp32s2/src/rtc_cntl/touch_ctrl1.rs
index d241dd3f03..fb830bdd37 100644
--- a/esp32s2/src/rtc_cntl/touch_ctrl1.rs
+++ b/esp32s2/src/rtc_cntl/touch_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_CTRL1")
-            .field(
-                "touch_sleep_cycles",
-                &format_args!("{}", self.touch_sleep_cycles().bits()),
-            )
-            .field(
-                "touch_meas_num",
-                &format_args!("{}", self.touch_meas_num().bits()),
-            )
+            .field("touch_sleep_cycles", &self.touch_sleep_cycles())
+            .field("touch_meas_num", &self.touch_meas_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Set sleep cycles for touch timer."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/touch_ctrl2.rs b/esp32s2/src/rtc_cntl/touch_ctrl2.rs
index 089a4d2d87..caaff75401 100644
--- a/esp32s2/src/rtc_cntl/touch_ctrl2.rs
+++ b/esp32s2/src/rtc_cntl/touch_ctrl2.rs
@@ -152,70 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_CTRL2")
-            .field(
-                "touch_drange",
-                &format_args!("{}", self.touch_drange().bits()),
-            )
-            .field(
-                "touch_drefl",
-                &format_args!("{}", self.touch_drefl().bits()),
-            )
-            .field(
-                "touch_drefh",
-                &format_args!("{}", self.touch_drefh().bits()),
-            )
-            .field(
-                "touch_xpd_bias",
-                &format_args!("{}", self.touch_xpd_bias().bit()),
-            )
-            .field("touch_refc", &format_args!("{}", self.touch_refc().bits()))
-            .field("touch_dbias", &format_args!("{}", self.touch_dbias().bit()))
-            .field(
-                "touch_slp_timer_en",
-                &format_args!("{}", self.touch_slp_timer_en().bit()),
-            )
-            .field(
-                "touch_start_fsm_en",
-                &format_args!("{}", self.touch_start_fsm_en().bit()),
-            )
-            .field(
-                "touch_start_en",
-                &format_args!("{}", self.touch_start_en().bit()),
-            )
-            .field(
-                "touch_start_force",
-                &format_args!("{}", self.touch_start_force().bit()),
-            )
-            .field(
-                "touch_xpd_wait",
-                &format_args!("{}", self.touch_xpd_wait().bits()),
-            )
-            .field(
-                "touch_slp_cyc_div",
-                &format_args!("{}", self.touch_slp_cyc_div().bits()),
-            )
-            .field(
-                "touch_timer_force_done",
-                &format_args!("{}", self.touch_timer_force_done().bits()),
-            )
-            .field("touch_reset", &format_args!("{}", self.touch_reset().bit()))
-            .field(
-                "touch_clk_fo",
-                &format_args!("{}", self.touch_clk_fo().bit()),
-            )
-            .field(
-                "touch_clkgate_en",
-                &format_args!("{}", self.touch_clkgate_en().bit()),
-            )
+            .field("touch_drange", &self.touch_drange())
+            .field("touch_drefl", &self.touch_drefl())
+            .field("touch_drefh", &self.touch_drefh())
+            .field("touch_xpd_bias", &self.touch_xpd_bias())
+            .field("touch_refc", &self.touch_refc())
+            .field("touch_dbias", &self.touch_dbias())
+            .field("touch_slp_timer_en", &self.touch_slp_timer_en())
+            .field("touch_start_fsm_en", &self.touch_start_fsm_en())
+            .field("touch_start_en", &self.touch_start_en())
+            .field("touch_start_force", &self.touch_start_force())
+            .field("touch_xpd_wait", &self.touch_xpd_wait())
+            .field("touch_slp_cyc_div", &self.touch_slp_cyc_div())
+            .field("touch_timer_force_done", &self.touch_timer_force_done())
+            .field("touch_reset", &self.touch_reset())
+            .field("touch_clk_fo", &self.touch_clk_fo())
+            .field("touch_clkgate_en", &self.touch_clkgate_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 2:3 - TOUCH attenuation."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/touch_filter_ctrl.rs b/esp32s2/src/rtc_cntl/touch_filter_ctrl.rs
index efd4b0d7cb..48c030e421 100644
--- a/esp32s2/src/rtc_cntl/touch_filter_ctrl.rs
+++ b/esp32s2/src/rtc_cntl/touch_filter_ctrl.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_FILTER_CTRL")
-            .field(
-                "touch_smooth_lvl",
-                &format_args!("{}", self.touch_smooth_lvl().bits()),
-            )
-            .field(
-                "touch_jitter_step",
-                &format_args!("{}", self.touch_jitter_step().bits()),
-            )
-            .field(
-                "touch_neg_noise_limit",
-                &format_args!("{}", self.touch_neg_noise_limit().bits()),
-            )
-            .field(
-                "touch_neg_noise_thres",
-                &format_args!("{}", self.touch_neg_noise_thres().bits()),
-            )
-            .field(
-                "touch_noise_thres",
-                &format_args!("{}", self.touch_noise_thres().bits()),
-            )
-            .field(
-                "touch_hysteresis",
-                &format_args!("{}", self.touch_hysteresis().bits()),
-            )
-            .field(
-                "touch_debounce",
-                &format_args!("{}", self.touch_debounce().bits()),
-            )
-            .field(
-                "touch_filter_mode",
-                &format_args!("{}", self.touch_filter_mode().bits()),
-            )
-            .field(
-                "touch_filter_en",
-                &format_args!("{}", self.touch_filter_en().bit()),
-            )
+            .field("touch_smooth_lvl", &self.touch_smooth_lvl())
+            .field("touch_jitter_step", &self.touch_jitter_step())
+            .field("touch_neg_noise_limit", &self.touch_neg_noise_limit())
+            .field("touch_neg_noise_thres", &self.touch_neg_noise_thres())
+            .field("touch_noise_thres", &self.touch_noise_thres())
+            .field("touch_hysteresis", &self.touch_hysteresis())
+            .field("touch_debounce", &self.touch_debounce())
+            .field("touch_filter_mode", &self.touch_filter_mode())
+            .field("touch_filter_en", &self.touch_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_FILTER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 9:10 - 0: Raw data. 1: IIR1/2. 2: IIR1/4. 3: IIR1/8."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/touch_scan_ctrl.rs b/esp32s2/src/rtc_cntl/touch_scan_ctrl.rs
index 1b066c8024..4961fac93f 100644
--- a/esp32s2/src/rtc_cntl/touch_scan_ctrl.rs
+++ b/esp32s2/src/rtc_cntl/touch_scan_ctrl.rs
@@ -71,43 +71,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_SCAN_CTRL")
-            .field(
-                "touch_denoise_res",
-                &format_args!("{}", self.touch_denoise_res().bits()),
-            )
-            .field(
-                "touch_denoise_en",
-                &format_args!("{}", self.touch_denoise_en().bit()),
-            )
+            .field("touch_denoise_res", &self.touch_denoise_res())
+            .field("touch_denoise_en", &self.touch_denoise_en())
             .field(
                 "touch_inactive_connection",
-                &format_args!("{}", self.touch_inactive_connection().bit()),
-            )
-            .field(
-                "touch_shield_pad_en",
-                &format_args!("{}", self.touch_shield_pad_en().bit()),
-            )
-            .field(
-                "touch_scan_pad_map",
-                &format_args!("{}", self.touch_scan_pad_map().bits()),
-            )
-            .field(
-                "touch_bufdrv",
-                &format_args!("{}", self.touch_bufdrv().bits()),
-            )
-            .field(
-                "touch_out_ring",
-                &format_args!("{}", self.touch_out_ring().bits()),
+                &self.touch_inactive_connection(),
             )
+            .field("touch_shield_pad_en", &self.touch_shield_pad_en())
+            .field("touch_scan_pad_map", &self.touch_scan_pad_map())
+            .field("touch_bufdrv", &self.touch_bufdrv())
+            .field("touch_out_ring", &self.touch_out_ring())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_SCAN_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Denoise resolution. 0: 12-bit; 1: 10-bit; 2: 8-bit; 3: 4-bit."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/touch_slp_thres.rs b/esp32s2/src/rtc_cntl/touch_slp_thres.rs
index c4f74b114b..218a6c6e2a 100644
--- a/esp32s2/src/rtc_cntl/touch_slp_thres.rs
+++ b/esp32s2/src/rtc_cntl/touch_slp_thres.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_SLP_THRES")
-            .field(
-                "touch_slp_th",
-                &format_args!("{}", self.touch_slp_th().bits()),
-            )
-            .field(
-                "touch_slp_approach_en",
-                &format_args!("{}", self.touch_slp_approach_en().bit()),
-            )
-            .field(
-                "touch_slp_pad",
-                &format_args!("{}", self.touch_slp_pad().bits()),
-            )
+            .field("touch_slp_th", &self.touch_slp_th())
+            .field("touch_slp_approach_en", &self.touch_slp_approach_en())
+            .field("touch_slp_pad", &self.touch_slp_pad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_SLP_THRES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Set the threshold for touch sleep pad."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/touch_timeout_ctrl.rs b/esp32s2/src/rtc_cntl/touch_timeout_ctrl.rs
index 699f117f69..a5b4b5c2bd 100644
--- a/esp32s2/src/rtc_cntl/touch_timeout_ctrl.rs
+++ b/esp32s2/src/rtc_cntl/touch_timeout_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_TIMEOUT_CTRL")
-            .field(
-                "touch_timeout_num",
-                &format_args!("{}", self.touch_timeout_num().bits()),
-            )
-            .field(
-                "touch_timeout_en",
-                &format_args!("{}", self.touch_timeout_en().bit()),
-            )
+            .field("touch_timeout_num", &self.touch_timeout_num())
+            .field("touch_timeout_en", &self.touch_timeout_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_TIMEOUT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Set touch timeout threshold."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/ulp_cp_ctrl.rs b/esp32s2/src/rtc_cntl/ulp_cp_ctrl.rs
index dbc87c201a..694cedbf34 100644
--- a/esp32s2/src/rtc_cntl/ulp_cp_ctrl.rs
+++ b/esp32s2/src/rtc_cntl/ulp_cp_ctrl.rs
@@ -64,39 +64,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_CTRL")
-            .field(
-                "ulp_cp_mem_addr_init",
-                &format_args!("{}", self.ulp_cp_mem_addr_init().bits()),
-            )
-            .field(
-                "ulp_cp_mem_addr_size",
-                &format_args!("{}", self.ulp_cp_mem_addr_size().bits()),
-            )
-            .field(
-                "ulp_cp_clk_fo",
-                &format_args!("{}", self.ulp_cp_clk_fo().bit()),
-            )
-            .field(
-                "ulp_cp_reset",
-                &format_args!("{}", self.ulp_cp_reset().bit()),
-            )
-            .field(
-                "ulp_cp_force_start_top",
-                &format_args!("{}", self.ulp_cp_force_start_top().bit()),
-            )
-            .field(
-                "ulp_cp_start_top",
-                &format_args!("{}", self.ulp_cp_start_top().bit()),
-            )
+            .field("ulp_cp_mem_addr_init", &self.ulp_cp_mem_addr_init())
+            .field("ulp_cp_mem_addr_size", &self.ulp_cp_mem_addr_size())
+            .field("ulp_cp_clk_fo", &self.ulp_cp_clk_fo())
+            .field("ulp_cp_reset", &self.ulp_cp_reset())
+            .field("ulp_cp_force_start_top", &self.ulp_cp_force_start_top())
+            .field("ulp_cp_start_top", &self.ulp_cp_start_top())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/ulp_cp_timer.rs b/esp32s2/src/rtc_cntl/ulp_cp_timer.rs
index f19c3bf875..d519f6ab39 100644
--- a/esp32s2/src/rtc_cntl/ulp_cp_timer.rs
+++ b/esp32s2/src/rtc_cntl/ulp_cp_timer.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_TIMER")
-            .field(
-                "ulp_cp_pc_init",
-                &format_args!("{}", self.ulp_cp_pc_init().bits()),
-            )
-            .field(
-                "ulp_cp_gpio_wakeup_ena",
-                &format_args!("{}", self.ulp_cp_gpio_wakeup_ena().bit()),
-            )
-            .field(
-                "ulp_cp_slp_timer_en",
-                &format_args!("{}", self.ulp_cp_slp_timer_en().bit()),
-            )
+            .field("ulp_cp_pc_init", &self.ulp_cp_pc_init())
+            .field("ulp_cp_gpio_wakeup_ena", &self.ulp_cp_gpio_wakeup_ena())
+            .field("ulp_cp_slp_timer_en", &self.ulp_cp_slp_timer_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_TIMER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - ULP coprocessor PC initial address"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/ulp_cp_timer_1.rs b/esp32s2/src/rtc_cntl/ulp_cp_timer_1.rs
index d92d48d625..e0cb787596 100644
--- a/esp32s2/src/rtc_cntl/ulp_cp_timer_1.rs
+++ b/esp32s2/src/rtc_cntl/ulp_cp_timer_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_TIMER_1")
-            .field(
-                "ulp_cp_timer_slp_cycle",
-                &format_args!("{}", self.ulp_cp_timer_slp_cycle().bits()),
-            )
+            .field("ulp_cp_timer_slp_cycle", &self.ulp_cp_timer_slp_cycle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_TIMER_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:31 - Set sleep cycles for ULP coprocessor timer"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/usb_conf.rs b/esp32s2/src/rtc_cntl/usb_conf.rs
index 72fbda1e73..4cc0284843 100644
--- a/esp32s2/src/rtc_cntl/usb_conf.rs
+++ b/esp32s2/src/rtc_cntl/usb_conf.rs
@@ -161,68 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_CONF")
-            .field("usb_vrefh", &format_args!("{}", self.usb_vrefh().bits()))
-            .field("usb_vrefl", &format_args!("{}", self.usb_vrefl().bits()))
-            .field(
-                "usb_vref_override",
-                &format_args!("{}", self.usb_vref_override().bit()),
-            )
-            .field(
-                "usb_pad_pull_override",
-                &format_args!("{}", self.usb_pad_pull_override().bit()),
-            )
-            .field(
-                "usb_dp_pullup",
-                &format_args!("{}", self.usb_dp_pullup().bit()),
-            )
-            .field(
-                "usb_dp_pulldown",
-                &format_args!("{}", self.usb_dp_pulldown().bit()),
-            )
-            .field(
-                "usb_dm_pullup",
-                &format_args!("{}", self.usb_dm_pullup().bit()),
-            )
-            .field(
-                "usb_dm_pulldown",
-                &format_args!("{}", self.usb_dm_pulldown().bit()),
-            )
-            .field(
-                "usb_pullup_value",
-                &format_args!("{}", self.usb_pullup_value().bit()),
-            )
-            .field(
-                "usb_pad_enable_override",
-                &format_args!("{}", self.usb_pad_enable_override().bit()),
-            )
-            .field(
-                "usb_pad_enable",
-                &format_args!("{}", self.usb_pad_enable().bit()),
-            )
-            .field("usb_txm", &format_args!("{}", self.usb_txm().bit()))
-            .field("usb_txp", &format_args!("{}", self.usb_txp().bit()))
-            .field("usb_tx_en", &format_args!("{}", self.usb_tx_en().bit()))
-            .field(
-                "usb_tx_en_override",
-                &format_args!("{}", self.usb_tx_en_override().bit()),
-            )
-            .field(
-                "usb_reset_disable",
-                &format_args!("{}", self.usb_reset_disable().bit()),
-            )
-            .field(
-                "io_mux_reset_disable",
-                &format_args!("{}", self.io_mux_reset_disable().bit()),
-            )
+            .field("usb_vrefh", &self.usb_vrefh())
+            .field("usb_vrefl", &self.usb_vrefl())
+            .field("usb_vref_override", &self.usb_vref_override())
+            .field("usb_pad_pull_override", &self.usb_pad_pull_override())
+            .field("usb_dp_pullup", &self.usb_dp_pullup())
+            .field("usb_dp_pulldown", &self.usb_dp_pulldown())
+            .field("usb_dm_pullup", &self.usb_dm_pullup())
+            .field("usb_dm_pulldown", &self.usb_dm_pulldown())
+            .field("usb_pullup_value", &self.usb_pullup_value())
+            .field("usb_pad_enable_override", &self.usb_pad_enable_override())
+            .field("usb_pad_enable", &self.usb_pad_enable())
+            .field("usb_txm", &self.usb_txm())
+            .field("usb_txp", &self.usb_txp())
+            .field("usb_tx_en", &self.usb_tx_en())
+            .field("usb_tx_en_override", &self.usb_tx_en_override())
+            .field("usb_reset_disable", &self.usb_reset_disable())
+            .field("io_mux_reset_disable", &self.io_mux_reset_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/wakeup_state.rs b/esp32s2/src/rtc_cntl/wakeup_state.rs
index 3a2bd69727..d370c24397 100644
--- a/esp32s2/src/rtc_cntl/wakeup_state.rs
+++ b/esp32s2/src/rtc_cntl/wakeup_state.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WAKEUP_STATE")
-            .field("wakeup_ena", &format_args!("{}", self.wakeup_ena().bits()))
+            .field("wakeup_ena", &self.wakeup_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WAKEUP_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 15:31 - Enables the wakeup bitmap."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/wdtconfig0.rs b/esp32s2/src/rtc_cntl/wdtconfig0.rs
index 49e5c1458c..5e41d7e60a 100644
--- a/esp32s2/src/rtc_cntl/wdtconfig0.rs
+++ b/esp32s2/src/rtc_cntl/wdtconfig0.rs
@@ -125,52 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG0")
-            .field(
-                "wdt_chip_reset_width",
-                &format_args!("{}", self.wdt_chip_reset_width().bits()),
-            )
-            .field(
-                "wdt_chip_reset_en",
-                &format_args!("{}", self.wdt_chip_reset_en().bit()),
-            )
-            .field(
-                "wdt_pause_in_slp",
-                &format_args!("{}", self.wdt_pause_in_slp().bit()),
-            )
-            .field(
-                "wdt_appcpu_reset_en",
-                &format_args!("{}", self.wdt_appcpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_chip_reset_width", &self.wdt_chip_reset_width())
+            .field("wdt_chip_reset_en", &self.wdt_chip_reset_en())
+            .field("wdt_pause_in_slp", &self.wdt_pause_in_slp())
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - chip reset siginal pulse width"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/wdtconfig1.rs b/esp32s2/src/rtc_cntl/wdtconfig1.rs
index e572bf6e6e..25d2813612 100644
--- a/esp32s2/src/rtc_cntl/wdtconfig1.rs
+++ b/esp32s2/src/rtc_cntl/wdtconfig1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG1")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the hold time of RTC watchdog at level 1."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/wdtconfig2.rs b/esp32s2/src/rtc_cntl/wdtconfig2.rs
index 6554a89b58..b2cac3c802 100644
--- a/esp32s2/src/rtc_cntl/wdtconfig2.rs
+++ b/esp32s2/src/rtc_cntl/wdtconfig2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG2")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the hold time of RTC watchdog at level 2."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/wdtconfig3.rs b/esp32s2/src/rtc_cntl/wdtconfig3.rs
index 781cead82c..e0265c253c 100644
--- a/esp32s2/src/rtc_cntl/wdtconfig3.rs
+++ b/esp32s2/src/rtc_cntl/wdtconfig3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG3")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the hold time of RTC watchdog at level 3."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/wdtconfig4.rs b/esp32s2/src/rtc_cntl/wdtconfig4.rs
index 4b902ca4ad..5447d9a1e3 100644
--- a/esp32s2/src/rtc_cntl/wdtconfig4.rs
+++ b/esp32s2/src/rtc_cntl/wdtconfig4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG4")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the hold time of RTC watchdog at level 4."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/wdtwprotect.rs b/esp32s2/src/rtc_cntl/wdtwprotect.rs
index b740a11d3b..ea1cb0019e 100644
--- a/esp32s2/src/rtc_cntl/wdtwprotect.rs
+++ b/esp32s2/src/rtc_cntl/wdtwprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTWPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTWPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Sets the write protection key of the watchdog."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/xtal32k_clk_factor.rs b/esp32s2/src/rtc_cntl/xtal32k_clk_factor.rs
index 0730d67dc0..f81baec496 100644
--- a/esp32s2/src/rtc_cntl/xtal32k_clk_factor.rs
+++ b/esp32s2/src/rtc_cntl/xtal32k_clk_factor.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL32K_CLK_FACTOR")
-            .field(
-                "xtal32k_clk_factor",
-                &format_args!("{}", self.xtal32k_clk_factor().bits()),
-            )
+            .field("xtal32k_clk_factor", &self.xtal32k_clk_factor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL32K_CLK_FACTOR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Configures the divider factor for the 32 kHz crystal oscillator."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_cntl/xtal32k_conf.rs b/esp32s2/src/rtc_cntl/xtal32k_conf.rs
index e103162d8a..11551eb67a 100644
--- a/esp32s2/src/rtc_cntl/xtal32k_conf.rs
+++ b/esp32s2/src/rtc_cntl/xtal32k_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL32K_CONF")
-            .field(
-                "xtal32k_return_wait",
-                &format_args!("{}", self.xtal32k_return_wait().bits()),
-            )
-            .field(
-                "xtal32k_restart_wait",
-                &format_args!("{}", self.xtal32k_restart_wait().bits()),
-            )
-            .field(
-                "xtal32k_wdt_timeout",
-                &format_args!("{}", self.xtal32k_wdt_timeout().bits()),
-            )
-            .field(
-                "xtal32k_stable_thres",
-                &format_args!("{}", self.xtal32k_stable_thres().bits()),
-            )
+            .field("xtal32k_return_wait", &self.xtal32k_return_wait())
+            .field("xtal32k_restart_wait", &self.xtal32k_restart_wait())
+            .field("xtal32k_wdt_timeout", &self.xtal32k_wdt_timeout())
+            .field("xtal32k_stable_thres", &self.xtal32k_stable_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL32K_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Defines the waiting cycles before returning to the normal 32 kHz crystal oscillator."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_i2c/cmd.rs b/esp32s2/src/rtc_i2c/cmd.rs
index f1a4792fc8..62306772ec 100644
--- a/esp32s2/src/rtc_i2c/cmd.rs
+++ b/esp32s2/src/rtc_i2c/cmd.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("command", &format_args!("{}", self.command().bits()))
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Content of command 0. For more information, please refer to the register I2C_COMD0_REG in Chapter I²C Controller"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_i2c/ctrl.rs b/esp32s2/src/rtc_i2c/ctrl.rs
index 274cb6e950..e542a862d2 100644
--- a/esp32s2/src/rtc_i2c/ctrl.rs
+++ b/esp32s2/src/rtc_i2c/ctrl.rs
@@ -89,36 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field("ms_mode", &format_args!("{}", self.ms_mode().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
-            .field("clk_gate_en", &format_args!("{}", self.clk_gate_en().bit()))
-            .field("reset", &format_args!("{}", self.reset().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("ms_mode", &self.ms_mode())
+            .field("trans_start", &self.trans_start())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("clk_gate_en", &self.clk_gate_en())
+            .field("reset", &self.reset())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SDA output mode. 0: open drain. 1: push pull."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_i2c/data.rs b/esp32s2/src/rtc_i2c/data.rs
index 2b99115683..3d84c223a5 100644
--- a/esp32s2/src/rtc_i2c/data.rs
+++ b/esp32s2/src/rtc_i2c/data.rs
@@ -31,21 +31,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field("rdata", &format_args!("{}", self.rdata().bits()))
-            .field(
-                "slave_tx_data",
-                &format_args!("{}", self.slave_tx_data().bits()),
-            )
-            .field("done", &format_args!("{}", self.done().bit()))
+            .field("rdata", &self.rdata())
+            .field("slave_tx_data", &self.slave_tx_data())
+            .field("done", &self.done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:15 - The data sent by slave"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_i2c/date.rs b/esp32s2/src/rtc_i2c/date.rs
index 7b6b864714..f4c7caacd8 100644
--- a/esp32s2/src/rtc_i2c/date.rs
+++ b/esp32s2/src/rtc_i2c/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/rtc_i2c/int_ena.rs b/esp32s2/src/rtc_i2c/int_ena.rs
index 3347ddd174..c0c15bae95 100644
--- a/esp32s2/src/rtc_i2c/int_ena.rs
+++ b/esp32s2/src/rtc_i2c/int_ena.rs
@@ -89,39 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "slave_tran_comp",
-                &format_args!("{}", self.slave_tran_comp().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_tran_comp",
-                &format_args!("{}", self.master_tran_comp().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("ack_err", &format_args!("{}", self.ack_err().bit()))
-            .field("rx_data", &format_args!("{}", self.rx_data().bit()))
-            .field("tx_data", &format_args!("{}", self.tx_data().bit()))
-            .field(
-                "detect_start",
-                &format_args!("{}", self.detect_start().bit()),
-            )
+            .field("slave_tran_comp", &self.slave_tran_comp())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_tran_comp", &self.master_tran_comp())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("ack_err", &self.ack_err())
+            .field("rx_data", &self.rx_data())
+            .field("tx_data", &self.tx_data())
+            .field("detect_start", &self.detect_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - RTC_I2C_SLAVE_TRAN_COMP_INT interrupt enable bit"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_i2c/int_raw.rs b/esp32s2/src/rtc_i2c/int_raw.rs
index 07861e3951..54550ab419 100644
--- a/esp32s2/src/rtc_i2c/int_raw.rs
+++ b/esp32s2/src/rtc_i2c/int_raw.rs
@@ -69,39 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "slave_tran_comp",
-                &format_args!("{}", self.slave_tran_comp().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_tran_comp",
-                &format_args!("{}", self.master_tran_comp().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("ack_err", &format_args!("{}", self.ack_err().bit()))
-            .field("rx_data", &format_args!("{}", self.rx_data().bit()))
-            .field("tx_data", &format_args!("{}", self.tx_data().bit()))
-            .field(
-                "detect_start",
-                &format_args!("{}", self.detect_start().bit()),
-            )
+            .field("slave_tran_comp", &self.slave_tran_comp())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_tran_comp", &self.master_tran_comp())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("ack_err", &self.ack_err())
+            .field("rx_data", &self.rx_data())
+            .field("tx_data", &self.tx_data())
+            .field("detect_start", &self.detect_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC I2C raw interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s2/src/rtc_i2c/int_st.rs b/esp32s2/src/rtc_i2c/int_st.rs
index 567383878d..eea800c367 100644
--- a/esp32s2/src/rtc_i2c/int_st.rs
+++ b/esp32s2/src/rtc_i2c/int_st.rs
@@ -69,39 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "slave_tran_comp",
-                &format_args!("{}", self.slave_tran_comp().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_tran_comp",
-                &format_args!("{}", self.master_tran_comp().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("ack_err", &format_args!("{}", self.ack_err().bit()))
-            .field("rx_data", &format_args!("{}", self.rx_data().bit()))
-            .field("tx_data", &format_args!("{}", self.tx_data().bit()))
-            .field(
-                "detect_start",
-                &format_args!("{}", self.detect_start().bit()),
-            )
+            .field("slave_tran_comp", &self.slave_tran_comp())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_tran_comp", &self.master_tran_comp())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("ack_err", &self.ack_err())
+            .field("rx_data", &self.rx_data())
+            .field("tx_data", &self.tx_data())
+            .field("detect_start", &self.detect_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC I2C interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s2/src/rtc_i2c/scl_high.rs b/esp32s2/src/rtc_i2c/scl_high.rs
index 67af4dd83a..14af2585e9 100644
--- a/esp32s2/src/rtc_i2c/scl_high.rs
+++ b/esp32s2/src/rtc_i2c/scl_high.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH")
-            .field("period", &format_args!("{}", self.period().bits()))
+            .field("period", &self.period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register is used to configure how many cycles SCL remains high."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_i2c/scl_low.rs b/esp32s2/src/rtc_i2c/scl_low.rs
index a7d44338b5..bd7009a3b3 100644
--- a/esp32s2/src/rtc_i2c/scl_low.rs
+++ b/esp32s2/src/rtc_i2c/scl_low.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW")
-            .field("period", &format_args!("{}", self.period().bits()))
+            .field("period", &self.period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register is used to configure how many clock cycles SCL remains low."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_i2c/scl_start_period.rs b/esp32s2/src/rtc_i2c/scl_start_period.rs
index 13a722b0ad..d237af38c0 100644
--- a/esp32s2/src/rtc_i2c/scl_start_period.rs
+++ b/esp32s2/src/rtc_i2c/scl_start_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_PERIOD")
-            .field(
-                "scl_start_period",
-                &format_args!("{}", self.scl_start_period().bits()),
-            )
+            .field("scl_start_period", &self.scl_start_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - Number of clock cycles to wait after generating a start condition."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_i2c/scl_stop_period.rs b/esp32s2/src/rtc_i2c/scl_stop_period.rs
index 0e8fb62275..7a307f2791 100644
--- a/esp32s2/src/rtc_i2c/scl_stop_period.rs
+++ b/esp32s2/src/rtc_i2c/scl_stop_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_PERIOD")
-            .field(
-                "scl_stop_period",
-                &format_args!("{}", self.scl_stop_period().bits()),
-            )
+            .field("scl_stop_period", &self.scl_stop_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - Number of clock cycles to wait before generating a stop condition."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_i2c/sda_duty.rs b/esp32s2/src/rtc_i2c/sda_duty.rs
index d60ef29da2..125cb109ad 100644
--- a/esp32s2/src/rtc_i2c/sda_duty.rs
+++ b/esp32s2/src/rtc_i2c/sda_duty.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_DUTY")
-            .field("num", &format_args!("{}", self.num().bits()))
+            .field("num", &self.num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - The number of clock cycles between the SDA switch and the falling edge of SCL."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_i2c/slave_addr.rs b/esp32s2/src/rtc_i2c/slave_addr.rs
index 9c127aa99d..991b963e84 100644
--- a/esp32s2/src/rtc_i2c/slave_addr.rs
+++ b/esp32s2/src/rtc_i2c/slave_addr.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE_ADDR")
-            .field("slave_addr", &format_args!("{}", self.slave_addr().bits()))
-            .field(
-                "addr_10bit_en",
-                &format_args!("{}", self.addr_10bit_en().bit()),
-            )
+            .field("slave_addr", &self.slave_addr())
+            .field("addr_10bit_en", &self.addr_10bit_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - slave address"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_i2c/status.rs b/esp32s2/src/rtc_i2c/status.rs
index d0442a71b8..60d0b73b8f 100644
--- a/esp32s2/src/rtc_i2c/status.rs
+++ b/esp32s2/src/rtc_i2c/status.rs
@@ -76,34 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("ack_rec", &format_args!("{}", self.ack_rec().bit()))
-            .field("slave_rw", &format_args!("{}", self.slave_rw().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field(
-                "slave_addressed",
-                &format_args!("{}", self.slave_addressed().bit()),
-            )
-            .field("byte_trans", &format_args!("{}", self.byte_trans().bit()))
-            .field("op_cnt", &format_args!("{}", self.op_cnt().bits()))
-            .field("shift", &format_args!("{}", self.shift().bits()))
-            .field(
-                "scl_main_state_last",
-                &format_args!("{}", self.scl_main_state_last().bits()),
-            )
-            .field(
-                "scl_state_last",
-                &format_args!("{}", self.scl_state_last().bits()),
-            )
+            .field("ack_rec", &self.ack_rec())
+            .field("slave_rw", &self.slave_rw())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("slave_addressed", &self.slave_addressed())
+            .field("byte_trans", &self.byte_trans())
+            .field("op_cnt", &self.op_cnt())
+            .field("shift", &self.shift())
+            .field("scl_main_state_last", &self.scl_main_state_last())
+            .field("scl_state_last", &self.scl_state_last())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC I2C status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32s2/src/rtc_i2c/to.rs b/esp32s2/src/rtc_i2c/to.rs
index 98b81a2aa8..18ae107993 100644
--- a/esp32s2/src/rtc_i2c/to.rs
+++ b/esp32s2/src/rtc_i2c/to.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO")
-            .field("time_out", &format_args!("{}", self.time_out().bits()))
+            .field("time_out", &self.time_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - Timeout threshold"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/ext_wakeup0.rs b/esp32s2/src/rtc_io/ext_wakeup0.rs
index d2f2163134..254cc44678 100644
--- a/esp32s2/src/rtc_io/ext_wakeup0.rs
+++ b/esp32s2/src/rtc_io/ext_wakeup0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP0")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 27:31 - GPIO\\[0-17\\] can be used to wake up the chip when the chip is in the sleep mode. This register prompts the pad source to wake up the chip when the latter is indeep/light sleep mode. 0: select GPIO0; 1: select GPIO2, etc"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/pad_dac1.rs b/esp32s2/src/rtc_io/pad_dac1.rs
index 771fbdebea..919068c5c4 100644
--- a/esp32s2/src/rtc_io/pad_dac1.rs
+++ b/esp32s2/src/rtc_io/pad_dac1.rs
@@ -116,51 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_DAC1")
-            .field("pdac1_dac", &format_args!("{}", self.pdac1_dac().bits()))
-            .field(
-                "pdac1_xpd_dac",
-                &format_args!("{}", self.pdac1_xpd_dac().bit()),
-            )
-            .field(
-                "pdac1_dac_xpd_force",
-                &format_args!("{}", self.pdac1_dac_xpd_force().bit()),
-            )
-            .field(
-                "pdac1_fun_ie",
-                &format_args!("{}", self.pdac1_fun_ie().bit()),
-            )
-            .field(
-                "pdac1_slp_oe",
-                &format_args!("{}", self.pdac1_slp_oe().bit()),
-            )
-            .field(
-                "pdac1_slp_ie",
-                &format_args!("{}", self.pdac1_slp_ie().bit()),
-            )
-            .field(
-                "pdac1_slp_sel",
-                &format_args!("{}", self.pdac1_slp_sel().bit()),
-            )
-            .field(
-                "pdac1_fun_sel",
-                &format_args!("{}", self.pdac1_fun_sel().bits()),
-            )
-            .field(
-                "pdac1_mux_sel",
-                &format_args!("{}", self.pdac1_mux_sel().bit()),
-            )
-            .field("pdac1_rue", &format_args!("{}", self.pdac1_rue().bit()))
-            .field("pdac1_rde", &format_args!("{}", self.pdac1_rde().bit()))
-            .field("pdac1_drv", &format_args!("{}", self.pdac1_drv().bits()))
+            .field("pdac1_dac", &self.pdac1_dac())
+            .field("pdac1_xpd_dac", &self.pdac1_xpd_dac())
+            .field("pdac1_dac_xpd_force", &self.pdac1_dac_xpd_force())
+            .field("pdac1_fun_ie", &self.pdac1_fun_ie())
+            .field("pdac1_slp_oe", &self.pdac1_slp_oe())
+            .field("pdac1_slp_ie", &self.pdac1_slp_ie())
+            .field("pdac1_slp_sel", &self.pdac1_slp_sel())
+            .field("pdac1_fun_sel", &self.pdac1_fun_sel())
+            .field("pdac1_mux_sel", &self.pdac1_mux_sel())
+            .field("pdac1_rue", &self.pdac1_rue())
+            .field("pdac1_rde", &self.pdac1_rde())
+            .field("pdac1_drv", &self.pdac1_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_DAC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:10 - Configure DAC_1 output when RTCIO_PDAC1_DAC_XPD_FORCE is set to 1."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/pad_dac2.rs b/esp32s2/src/rtc_io/pad_dac2.rs
index cbf3b46ea3..eabd802a43 100644
--- a/esp32s2/src/rtc_io/pad_dac2.rs
+++ b/esp32s2/src/rtc_io/pad_dac2.rs
@@ -116,51 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_DAC2")
-            .field("pdac2_dac", &format_args!("{}", self.pdac2_dac().bits()))
-            .field(
-                "pdac2_xpd_dac",
-                &format_args!("{}", self.pdac2_xpd_dac().bit()),
-            )
-            .field(
-                "pdac2_dac_xpd_force",
-                &format_args!("{}", self.pdac2_dac_xpd_force().bit()),
-            )
-            .field(
-                "pdac2_fun_ie",
-                &format_args!("{}", self.pdac2_fun_ie().bit()),
-            )
-            .field(
-                "pdac2_slp_oe",
-                &format_args!("{}", self.pdac2_slp_oe().bit()),
-            )
-            .field(
-                "pdac2_slp_ie",
-                &format_args!("{}", self.pdac2_slp_ie().bit()),
-            )
-            .field(
-                "pdac2_slp_sel",
-                &format_args!("{}", self.pdac2_slp_sel().bit()),
-            )
-            .field(
-                "pdac2_fun_sel",
-                &format_args!("{}", self.pdac2_fun_sel().bits()),
-            )
-            .field(
-                "pdac2_mux_sel",
-                &format_args!("{}", self.pdac2_mux_sel().bit()),
-            )
-            .field("pdac2_rue", &format_args!("{}", self.pdac2_rue().bit()))
-            .field("pdac2_rde", &format_args!("{}", self.pdac2_rde().bit()))
-            .field("pdac2_drv", &format_args!("{}", self.pdac2_drv().bits()))
+            .field("pdac2_dac", &self.pdac2_dac())
+            .field("pdac2_xpd_dac", &self.pdac2_xpd_dac())
+            .field("pdac2_dac_xpd_force", &self.pdac2_dac_xpd_force())
+            .field("pdac2_fun_ie", &self.pdac2_fun_ie())
+            .field("pdac2_slp_oe", &self.pdac2_slp_oe())
+            .field("pdac2_slp_ie", &self.pdac2_slp_ie())
+            .field("pdac2_slp_sel", &self.pdac2_slp_sel())
+            .field("pdac2_fun_sel", &self.pdac2_fun_sel())
+            .field("pdac2_mux_sel", &self.pdac2_mux_sel())
+            .field("pdac2_rue", &self.pdac2_rue())
+            .field("pdac2_rde", &self.pdac2_rde())
+            .field("pdac2_drv", &self.pdac2_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_DAC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:10 - Configure DAC_2 output when RTCIO_PDAC2_DAC_XPD_FORCE is set to 1."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/pin.rs b/esp32s2/src/rtc_io/pin.rs
index b88c3fdc47..773574c2e0 100644
--- a/esp32s2/src/rtc_io/pin.rs
+++ b/esp32s2/src/rtc_io/pin.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field(
-                "gpio_pin_int_type",
-                &format_args!("{}", self.gpio_pin_int_type().bits()),
-            )
-            .field(
-                "gpio_pin_wakeup_enable",
-                &format_args!("{}", self.gpio_pin_wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("gpio_pin_int_type", &self.gpio_pin_int_type())
+            .field("gpio_pin_wakeup_enable", &self.gpio_pin_wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - Pad driver selection. 0: normal output. 1: open drain."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/rtc_debug_sel.rs b/esp32s2/src/rtc_io/rtc_debug_sel.rs
index fffc2b964e..cbc40a6115 100644
--- a/esp32s2/src/rtc_io/rtc_debug_sel.rs
+++ b/esp32s2/src/rtc_io/rtc_debug_sel.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_DEBUG_SEL")
-            .field(
-                "rtc_debug_sel0",
-                &format_args!("{}", self.rtc_debug_sel0().bits()),
-            )
-            .field(
-                "rtc_debug_sel1",
-                &format_args!("{}", self.rtc_debug_sel1().bits()),
-            )
-            .field(
-                "rtc_debug_sel2",
-                &format_args!("{}", self.rtc_debug_sel2().bits()),
-            )
-            .field(
-                "rtc_debug_sel3",
-                &format_args!("{}", self.rtc_debug_sel3().bits()),
-            )
-            .field(
-                "rtc_debug_sel4",
-                &format_args!("{}", self.rtc_debug_sel4().bits()),
-            )
-            .field(
-                "rtc_debug_12m_no_gating",
-                &format_args!("{}", self.rtc_debug_12m_no_gating().bit()),
-            )
+            .field("rtc_debug_sel0", &self.rtc_debug_sel0())
+            .field("rtc_debug_sel1", &self.rtc_debug_sel1())
+            .field("rtc_debug_sel2", &self.rtc_debug_sel2())
+            .field("rtc_debug_sel3", &self.rtc_debug_sel3())
+            .field("rtc_debug_sel4", &self.rtc_debug_sel4())
+            .field("rtc_debug_12m_no_gating", &self.rtc_debug_12m_no_gating())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_DEBUG_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/rtc_gpio_enable.rs b/esp32s2/src/rtc_io/rtc_gpio_enable.rs
index 21b1451525..bfa5f0072c 100644
--- a/esp32s2/src/rtc_io/rtc_gpio_enable.rs
+++ b/esp32s2/src/rtc_io/rtc_gpio_enable.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("RTC_GPIO_ENABLE")
             .field(
                 "reg_rtcio_reg_gpio_enable",
-                &format_args!("{}", self.reg_rtcio_reg_gpio_enable().bits()),
+                &self.reg_rtcio_reg_gpio_enable(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/rtc_gpio_in.rs b/esp32s2/src/rtc_io/rtc_gpio_in.rs
index 838aad4057..c5c388f33c 100644
--- a/esp32s2/src/rtc_io/rtc_gpio_in.rs
+++ b/esp32s2/src/rtc_io/rtc_gpio_in.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_GPIO_IN")
-            .field(
-                "gpio_in_next",
-                &format_args!("{}", self.gpio_in_next().bits()),
-            )
+            .field("gpio_in_next", &self.gpio_in_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC GPIO input register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_gpio_in::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTC_GPIO_IN_SPEC;
 impl crate::RegisterSpec for RTC_GPIO_IN_SPEC {
diff --git a/esp32s2/src/rtc_io/rtc_gpio_out.rs b/esp32s2/src/rtc_io/rtc_gpio_out.rs
index 5cbdf5114d..47b5c07428 100644
--- a/esp32s2/src/rtc_io/rtc_gpio_out.rs
+++ b/esp32s2/src/rtc_io/rtc_gpio_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_GPIO_OUT")
-            .field(
-                "gpio_out_data",
-                &format_args!("{}", self.gpio_out_data().bits()),
-            )
+            .field("gpio_out_data", &self.gpio_out_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/rtc_gpio_status.rs b/esp32s2/src/rtc_io/rtc_gpio_status.rs
index dc4ca20cd7..759d87ea4a 100644
--- a/esp32s2/src/rtc_io/rtc_gpio_status.rs
+++ b/esp32s2/src/rtc_io/rtc_gpio_status.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_GPIO_STATUS")
-            .field(
-                "gpio_status_int",
-                &format_args!("{}", self.gpio_status_int().bits()),
-            )
+            .field("gpio_status_int", &self.gpio_status_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 interrupt status register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RTCIO_RTC_GPIO_PINn_REG. 0: no interrupt; 1: corresponding interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/rtc_io_date.rs b/esp32s2/src/rtc_io/rtc_io_date.rs
index 940b912c4d..d97379d088 100644
--- a/esp32s2/src/rtc_io/rtc_io_date.rs
+++ b/esp32s2/src/rtc_io/rtc_io_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_IO_DATE")
-            .field("io_date", &format_args!("{}", self.io_date().bits()))
+            .field("io_date", &self.io_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_IO_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/rtc_io_touch_ctrl.rs b/esp32s2/src/rtc_io/rtc_io_touch_ctrl.rs
index 3174ddaba2..9879fb62a1 100644
--- a/esp32s2/src/rtc_io/rtc_io_touch_ctrl.rs
+++ b/esp32s2/src/rtc_io/rtc_io_touch_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_IO_TOUCH_CTRL")
-            .field(
-                "io_touch_bufsel",
-                &format_args!("{}", self.io_touch_bufsel().bits()),
-            )
-            .field(
-                "io_touch_bufmode",
-                &format_args!("{}", self.io_touch_bufmode().bit()),
-            )
+            .field("io_touch_bufsel", &self.io_touch_bufsel())
+            .field("io_touch_bufmode", &self.io_touch_bufmode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_IO_TOUCH_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/rtc_pad19.rs b/esp32s2/src/rtc_io/rtc_pad19.rs
index 18120bb8ac..3834851721 100644
--- a/esp32s2/src/rtc_io/rtc_pad19.rs
+++ b/esp32s2/src/rtc_io/rtc_pad19.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_PAD19")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_PAD19_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/rtc_pad20.rs b/esp32s2/src/rtc_io/rtc_pad20.rs
index 2e67a4f9d3..a44ccf7031 100644
--- a/esp32s2/src/rtc_io/rtc_pad20.rs
+++ b/esp32s2/src/rtc_io/rtc_pad20.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_PAD20")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_PAD20_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/rtc_pad21.rs b/esp32s2/src/rtc_io/rtc_pad21.rs
index d0fa416ebb..509112f876 100644
--- a/esp32s2/src/rtc_io/rtc_pad21.rs
+++ b/esp32s2/src/rtc_io/rtc_pad21.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_PAD21")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_PAD21_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/sar_i2c_io.rs b/esp32s2/src/rtc_io/sar_i2c_io.rs
index 710dc7ef54..005720ceab 100644
--- a/esp32s2/src/rtc_io/sar_i2c_io.rs
+++ b/esp32s2/src/rtc_io/sar_i2c_io.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_I2C_IO")
-            .field(
-                "sar_debug_bit_sel",
-                &format_args!("{}", self.sar_debug_bit_sel().bits()),
-            )
-            .field(
-                "sar_i2c_scl_sel",
-                &format_args!("{}", self.sar_i2c_scl_sel().bits()),
-            )
-            .field(
-                "sar_i2c_sda_sel",
-                &format_args!("{}", self.sar_i2c_sda_sel().bits()),
-            )
+            .field("sar_debug_bit_sel", &self.sar_debug_bit_sel())
+            .field("sar_i2c_scl_sel", &self.sar_i2c_scl_sel())
+            .field("sar_i2c_sda_sel", &self.sar_i2c_sda_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_I2C_IO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:27"]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/touch_pad.rs b/esp32s2/src/rtc_io/touch_pad.rs
index d7bffd38b5..bc2aa83524 100644
--- a/esp32s2/src/rtc_io/touch_pad.rs
+++ b/esp32s2/src/rtc_io/touch_pad.rs
@@ -125,28 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("dac", &format_args!("{}", self.dac().bits()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("dac", &self.dac())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/xtal_32n_pad.rs b/esp32s2/src/rtc_io/xtal_32n_pad.rs
index 00247903fd..30f17ea26a 100644
--- a/esp32s2/src/rtc_io/xtal_32n_pad.rs
+++ b/esp32s2/src/rtc_io/xtal_32n_pad.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL_32N_PAD")
-            .field("x32n_fun_ie", &format_args!("{}", self.x32n_fun_ie().bit()))
-            .field("x32n_slp_oe", &format_args!("{}", self.x32n_slp_oe().bit()))
-            .field("x32n_slp_ie", &format_args!("{}", self.x32n_slp_ie().bit()))
-            .field(
-                "x32n_slp_sel",
-                &format_args!("{}", self.x32n_slp_sel().bit()),
-            )
-            .field(
-                "x32n_fun_sel",
-                &format_args!("{}", self.x32n_fun_sel().bits()),
-            )
-            .field(
-                "x32n_mux_sel",
-                &format_args!("{}", self.x32n_mux_sel().bit()),
-            )
-            .field("x32n_rue", &format_args!("{}", self.x32n_rue().bit()))
-            .field("x32n_rde", &format_args!("{}", self.x32n_rde().bit()))
-            .field("x32n_drv", &format_args!("{}", self.x32n_drv().bits()))
+            .field("x32n_fun_ie", &self.x32n_fun_ie())
+            .field("x32n_slp_oe", &self.x32n_slp_oe())
+            .field("x32n_slp_ie", &self.x32n_slp_ie())
+            .field("x32n_slp_sel", &self.x32n_slp_sel())
+            .field("x32n_fun_sel", &self.x32n_fun_sel())
+            .field("x32n_mux_sel", &self.x32n_mux_sel())
+            .field("x32n_rue", &self.x32n_rue())
+            .field("x32n_rde", &self.x32n_rde())
+            .field("x32n_drv", &self.x32n_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL_32N_PAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/xtal_32p_pad.rs b/esp32s2/src/rtc_io/xtal_32p_pad.rs
index 2dd0eba9a6..25df482e56 100644
--- a/esp32s2/src/rtc_io/xtal_32p_pad.rs
+++ b/esp32s2/src/rtc_io/xtal_32p_pad.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL_32P_PAD")
-            .field("x32p_fun_ie", &format_args!("{}", self.x32p_fun_ie().bit()))
-            .field("x32p_slp_oe", &format_args!("{}", self.x32p_slp_oe().bit()))
-            .field("x32p_slp_ie", &format_args!("{}", self.x32p_slp_ie().bit()))
-            .field(
-                "x32p_slp_sel",
-                &format_args!("{}", self.x32p_slp_sel().bit()),
-            )
-            .field(
-                "x32p_fun_sel",
-                &format_args!("{}", self.x32p_fun_sel().bits()),
-            )
-            .field(
-                "x32p_mux_sel",
-                &format_args!("{}", self.x32p_mux_sel().bit()),
-            )
-            .field("x32p_rue", &format_args!("{}", self.x32p_rue().bit()))
-            .field("x32p_rde", &format_args!("{}", self.x32p_rde().bit()))
-            .field("x32p_drv", &format_args!("{}", self.x32p_drv().bits()))
+            .field("x32p_fun_ie", &self.x32p_fun_ie())
+            .field("x32p_slp_oe", &self.x32p_slp_oe())
+            .field("x32p_slp_ie", &self.x32p_slp_ie())
+            .field("x32p_slp_sel", &self.x32p_slp_sel())
+            .field("x32p_fun_sel", &self.x32p_fun_sel())
+            .field("x32p_mux_sel", &self.x32p_mux_sel())
+            .field("x32p_rue", &self.x32p_rue())
+            .field("x32p_rde", &self.x32p_rde())
+            .field("x32p_drv", &self.x32p_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL_32P_PAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - Input enable in normal execution."]
     #[inline(always)]
diff --git a/esp32s2/src/rtc_io/xtl_ext_ctr.rs b/esp32s2/src/rtc_io/xtl_ext_ctr.rs
index 1844095718..9c90f76ae8 100644
--- a/esp32s2/src/rtc_io/xtl_ext_ctr.rs
+++ b/esp32s2/src/rtc_io/xtl_ext_ctr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTL_EXT_CTR")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTL_EXT_CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 27:31 - Select the external crystal power down enable source to get into sleep mode. 0: select GPIO0. 1: select GPIO1, etc. The input value on this pin XOR RTC_CNTL_EXT_XTL_CONF_REG\\[30\\] is the crystal power down enable signal."]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_amp_ctrl1.rs b/esp32s2/src/sens/sar_amp_ctrl1.rs
index c989ffe7ee..7b6be86e5d 100644
--- a/esp32s2/src/sens/sar_amp_ctrl1.rs
+++ b/esp32s2/src/sens/sar_amp_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_AMP_CTRL1")
-            .field(
-                "sar_amp_wait1",
-                &format_args!("{}", self.sar_amp_wait1().bits()),
-            )
-            .field(
-                "sar_amp_wait2",
-                &format_args!("{}", self.sar_amp_wait2().bits()),
-            )
+            .field("sar_amp_wait1", &self.sar_amp_wait1())
+            .field("sar_amp_wait2", &self.sar_amp_wait2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_AMP_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_amp_ctrl2.rs b/esp32s2/src/sens/sar_amp_ctrl2.rs
index ffe6be12ff..52d827d3c1 100644
--- a/esp32s2/src/sens/sar_amp_ctrl2.rs
+++ b/esp32s2/src/sens/sar_amp_ctrl2.rs
@@ -80,47 +80,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_AMP_CTRL2")
-            .field(
-                "sar1_dac_xpd_fsm_idle",
-                &format_args!("{}", self.sar1_dac_xpd_fsm_idle().bit()),
-            )
-            .field(
-                "xpd_sar_amp_fsm_idle",
-                &format_args!("{}", self.xpd_sar_amp_fsm_idle().bit()),
-            )
-            .field(
-                "amp_rst_fb_fsm_idle",
-                &format_args!("{}", self.amp_rst_fb_fsm_idle().bit()),
-            )
-            .field(
-                "amp_short_ref_fsm_idle",
-                &format_args!("{}", self.amp_short_ref_fsm_idle().bit()),
-            )
+            .field("sar1_dac_xpd_fsm_idle", &self.sar1_dac_xpd_fsm_idle())
+            .field("xpd_sar_amp_fsm_idle", &self.xpd_sar_amp_fsm_idle())
+            .field("amp_rst_fb_fsm_idle", &self.amp_rst_fb_fsm_idle())
+            .field("amp_short_ref_fsm_idle", &self.amp_short_ref_fsm_idle())
             .field(
                 "amp_short_ref_gnd_fsm_idle",
-                &format_args!("{}", self.amp_short_ref_gnd_fsm_idle().bit()),
-            )
-            .field(
-                "xpd_sar_fsm_idle",
-                &format_args!("{}", self.xpd_sar_fsm_idle().bit()),
-            )
-            .field(
-                "sar_rstb_fsm_idle",
-                &format_args!("{}", self.sar_rstb_fsm_idle().bit()),
-            )
-            .field(
-                "sar_amp_wait3",
-                &format_args!("{}", self.sar_amp_wait3().bits()),
+                &self.amp_short_ref_gnd_fsm_idle(),
             )
+            .field("xpd_sar_fsm_idle", &self.xpd_sar_fsm_idle())
+            .field("sar_rstb_fsm_idle", &self.sar_rstb_fsm_idle())
+            .field("sar_amp_wait3", &self.sar_amp_wait3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_AMP_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_amp_ctrl3.rs b/esp32s2/src/sens/sar_amp_ctrl3.rs
index d4c2c64266..87ea2e30e8 100644
--- a/esp32s2/src/sens/sar_amp_ctrl3.rs
+++ b/esp32s2/src/sens/sar_amp_ctrl3.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_AMP_CTRL3")
-            .field(
-                "sar1_dac_xpd_fsm",
-                &format_args!("{}", self.sar1_dac_xpd_fsm().bits()),
-            )
-            .field(
-                "xpd_sar_amp_fsm",
-                &format_args!("{}", self.xpd_sar_amp_fsm().bits()),
-            )
-            .field(
-                "amp_rst_fb_fsm",
-                &format_args!("{}", self.amp_rst_fb_fsm().bits()),
-            )
-            .field(
-                "amp_short_ref_fsm",
-                &format_args!("{}", self.amp_short_ref_fsm().bits()),
-            )
-            .field(
-                "amp_short_ref_gnd_fsm",
-                &format_args!("{}", self.amp_short_ref_gnd_fsm().bits()),
-            )
-            .field(
-                "xpd_sar_fsm",
-                &format_args!("{}", self.xpd_sar_fsm().bits()),
-            )
-            .field(
-                "sar_rstb_fsm",
-                &format_args!("{}", self.sar_rstb_fsm().bits()),
-            )
+            .field("sar1_dac_xpd_fsm", &self.sar1_dac_xpd_fsm())
+            .field("xpd_sar_amp_fsm", &self.xpd_sar_amp_fsm())
+            .field("amp_rst_fb_fsm", &self.amp_rst_fb_fsm())
+            .field("amp_short_ref_fsm", &self.amp_short_ref_fsm())
+            .field("amp_short_ref_gnd_fsm", &self.amp_short_ref_gnd_fsm())
+            .field("xpd_sar_fsm", &self.xpd_sar_fsm())
+            .field("sar_rstb_fsm", &self.sar_rstb_fsm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_AMP_CTRL3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Control of DAC. 4’b0010: disable DAC. 4’b0000: power up DAC by FSM. 4’b0011: power up DAC by software."]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_atten1.rs b/esp32s2/src/sens/sar_atten1.rs
index ea561709d6..e6cb0aaf26 100644
--- a/esp32s2/src/sens/sar_atten1.rs
+++ b/esp32s2/src/sens/sar_atten1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_ATTEN1")
-            .field("sar1_atten", &format_args!("{}", self.sar1_atten().bits()))
+            .field("sar1_atten", &self.sar1_atten())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_ATTEN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 2-bit attenuation for each pad. \\[1:0\\] is used for channel 0, \\[3:2\\] is used for channel 1, etc."]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_atten2.rs b/esp32s2/src/sens/sar_atten2.rs
index 8936826d61..8d67443976 100644
--- a/esp32s2/src/sens/sar_atten2.rs
+++ b/esp32s2/src/sens/sar_atten2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_ATTEN2")
-            .field("sar2_atten", &format_args!("{}", self.sar2_atten().bits()))
+            .field("sar2_atten", &self.sar2_atten())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_ATTEN2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 2-bit attenuation for each pad. \\[1:0\\] is used for channel 0, \\[3:2\\] is used for channel 1, etc."]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_cocpu_debug.rs b/esp32s2/src/sens/sar_cocpu_debug.rs
index ee17c3518d..4313c65e79 100644
--- a/esp32s2/src/sens/sar_cocpu_debug.rs
+++ b/esp32s2/src/sens/sar_cocpu_debug.rs
@@ -41,32 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_COCPU_DEBUG")
-            .field("cocpu_pc", &format_args!("{}", self.cocpu_pc().bits()))
-            .field(
-                "cocpu_mem_vld",
-                &format_args!("{}", self.cocpu_mem_vld().bit()),
-            )
-            .field(
-                "cocpu_mem_rdy",
-                &format_args!("{}", self.cocpu_mem_rdy().bit()),
-            )
-            .field(
-                "cocpu_mem_wen",
-                &format_args!("{}", self.cocpu_mem_wen().bits()),
-            )
-            .field(
-                "cocpu_mem_addr",
-                &format_args!("{}", self.cocpu_mem_addr().bits()),
-            )
+            .field("cocpu_pc", &self.cocpu_pc())
+            .field("cocpu_mem_vld", &self.cocpu_mem_vld())
+            .field("cocpu_mem_rdy", &self.cocpu_mem_rdy())
+            .field("cocpu_mem_wen", &self.cocpu_mem_wen())
+            .field("cocpu_mem_addr", &self.cocpu_mem_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_DEBUG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "ULP-RISCV debug register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_cocpu_debug::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_COCPU_DEBUG_SPEC;
 impl crate::RegisterSpec for SAR_COCPU_DEBUG_SPEC {
diff --git a/esp32s2/src/sens/sar_cocpu_int_ena.rs b/esp32s2/src/sens/sar_cocpu_int_ena.rs
index 2b6498bb56..0c9b427f56 100644
--- a/esp32s2/src/sens/sar_cocpu_int_ena.rs
+++ b/esp32s2/src/sens/sar_cocpu_int_ena.rs
@@ -89,51 +89,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_COCPU_INT_ENA")
-            .field(
-                "cocpu_touch_done_int_ena",
-                &format_args!("{}", self.cocpu_touch_done_int_ena().bit()),
-            )
+            .field("cocpu_touch_done_int_ena", &self.cocpu_touch_done_int_ena())
             .field(
                 "cocpu_touch_inactive_int_ena",
-                &format_args!("{}", self.cocpu_touch_inactive_int_ena().bit()),
+                &self.cocpu_touch_inactive_int_ena(),
             )
             .field(
                 "cocpu_touch_active_int_ena",
-                &format_args!("{}", self.cocpu_touch_active_int_ena().bit()),
-            )
-            .field(
-                "cocpu_saradc1_int_ena",
-                &format_args!("{}", self.cocpu_saradc1_int_ena().bit()),
-            )
-            .field(
-                "cocpu_saradc2_int_ena",
-                &format_args!("{}", self.cocpu_saradc2_int_ena().bit()),
-            )
-            .field(
-                "cocpu_tsens_int_ena",
-                &format_args!("{}", self.cocpu_tsens_int_ena().bit()),
-            )
-            .field(
-                "cocpu_start_int_ena",
-                &format_args!("{}", self.cocpu_start_int_ena().bit()),
-            )
-            .field(
-                "cocpu_sw_int_ena",
-                &format_args!("{}", self.cocpu_sw_int_ena().bit()),
-            )
-            .field(
-                "cocpu_swd_int_ena",
-                &format_args!("{}", self.cocpu_swd_int_ena().bit()),
+                &self.cocpu_touch_active_int_ena(),
             )
+            .field("cocpu_saradc1_int_ena", &self.cocpu_saradc1_int_ena())
+            .field("cocpu_saradc2_int_ena", &self.cocpu_saradc2_int_ena())
+            .field("cocpu_tsens_int_ena", &self.cocpu_tsens_int_ena())
+            .field("cocpu_start_int_ena", &self.cocpu_start_int_ena())
+            .field("cocpu_sw_int_ena", &self.cocpu_sw_int_ena())
+            .field("cocpu_swd_int_ena", &self.cocpu_swd_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - TOUCH_DONE_INT interrupt enable bit"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_cocpu_int_raw.rs b/esp32s2/src/sens/sar_cocpu_int_raw.rs
index 3fa44cfab6..e2a4de4022 100644
--- a/esp32s2/src/sens/sar_cocpu_int_raw.rs
+++ b/esp32s2/src/sens/sar_cocpu_int_raw.rs
@@ -69,51 +69,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_COCPU_INT_RAW")
-            .field(
-                "cocpu_touch_done_int_raw",
-                &format_args!("{}", self.cocpu_touch_done_int_raw().bit()),
-            )
+            .field("cocpu_touch_done_int_raw", &self.cocpu_touch_done_int_raw())
             .field(
                 "cocpu_touch_inactive_int_raw",
-                &format_args!("{}", self.cocpu_touch_inactive_int_raw().bit()),
+                &self.cocpu_touch_inactive_int_raw(),
             )
             .field(
                 "cocpu_touch_active_int_raw",
-                &format_args!("{}", self.cocpu_touch_active_int_raw().bit()),
-            )
-            .field(
-                "cocpu_saradc1_int_raw",
-                &format_args!("{}", self.cocpu_saradc1_int_raw().bit()),
-            )
-            .field(
-                "cocpu_saradc2_int_raw",
-                &format_args!("{}", self.cocpu_saradc2_int_raw().bit()),
-            )
-            .field(
-                "cocpu_tsens_int_raw",
-                &format_args!("{}", self.cocpu_tsens_int_raw().bit()),
-            )
-            .field(
-                "cocpu_start_int_raw",
-                &format_args!("{}", self.cocpu_start_int_raw().bit()),
-            )
-            .field(
-                "cocpu_sw_int_raw",
-                &format_args!("{}", self.cocpu_sw_int_raw().bit()),
-            )
-            .field(
-                "cocpu_swd_int_raw",
-                &format_args!("{}", self.cocpu_swd_int_raw().bit()),
+                &self.cocpu_touch_active_int_raw(),
             )
+            .field("cocpu_saradc1_int_raw", &self.cocpu_saradc1_int_raw())
+            .field("cocpu_saradc2_int_raw", &self.cocpu_saradc2_int_raw())
+            .field("cocpu_tsens_int_raw", &self.cocpu_tsens_int_raw())
+            .field("cocpu_start_int_raw", &self.cocpu_start_int_raw())
+            .field("cocpu_sw_int_raw", &self.cocpu_sw_int_raw())
+            .field("cocpu_swd_int_raw", &self.cocpu_swd_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt raw bit of ULP-RISCV\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_cocpu_int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_COCPU_INT_RAW_SPEC;
 impl crate::RegisterSpec for SAR_COCPU_INT_RAW_SPEC {
diff --git a/esp32s2/src/sens/sar_cocpu_int_st.rs b/esp32s2/src/sens/sar_cocpu_int_st.rs
index b54165b09e..6776d12416 100644
--- a/esp32s2/src/sens/sar_cocpu_int_st.rs
+++ b/esp32s2/src/sens/sar_cocpu_int_st.rs
@@ -69,51 +69,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_COCPU_INT_ST")
-            .field(
-                "cocpu_touch_done_int_st",
-                &format_args!("{}", self.cocpu_touch_done_int_st().bit()),
-            )
+            .field("cocpu_touch_done_int_st", &self.cocpu_touch_done_int_st())
             .field(
                 "cocpu_touch_inactive_int_st",
-                &format_args!("{}", self.cocpu_touch_inactive_int_st().bit()),
+                &self.cocpu_touch_inactive_int_st(),
             )
             .field(
                 "cocpu_touch_active_int_st",
-                &format_args!("{}", self.cocpu_touch_active_int_st().bit()),
-            )
-            .field(
-                "cocpu_saradc1_int_st",
-                &format_args!("{}", self.cocpu_saradc1_int_st().bit()),
-            )
-            .field(
-                "cocpu_saradc2_int_st",
-                &format_args!("{}", self.cocpu_saradc2_int_st().bit()),
-            )
-            .field(
-                "cocpu_tsens_int_st",
-                &format_args!("{}", self.cocpu_tsens_int_st().bit()),
-            )
-            .field(
-                "cocpu_start_int_st",
-                &format_args!("{}", self.cocpu_start_int_st().bit()),
-            )
-            .field(
-                "cocpu_sw_int_st",
-                &format_args!("{}", self.cocpu_sw_int_st().bit()),
-            )
-            .field(
-                "cocpu_swd_int_st",
-                &format_args!("{}", self.cocpu_swd_int_st().bit()),
+                &self.cocpu_touch_active_int_st(),
             )
+            .field("cocpu_saradc1_int_st", &self.cocpu_saradc1_int_st())
+            .field("cocpu_saradc2_int_st", &self.cocpu_saradc2_int_st())
+            .field("cocpu_tsens_int_st", &self.cocpu_tsens_int_st())
+            .field("cocpu_start_int_st", &self.cocpu_start_int_st())
+            .field("cocpu_sw_int_st", &self.cocpu_sw_int_st())
+            .field("cocpu_swd_int_st", &self.cocpu_swd_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status bit of ULP-RISCV\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_cocpu_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_COCPU_INT_ST_SPEC;
 impl crate::RegisterSpec for SAR_COCPU_INT_ST_SPEC {
diff --git a/esp32s2/src/sens/sar_cocpu_state.rs b/esp32s2/src/sens/sar_cocpu_state.rs
index c2a13612f0..60966de1eb 100644
--- a/esp32s2/src/sens/sar_cocpu_state.rs
+++ b/esp32s2/src/sens/sar_cocpu_state.rs
@@ -45,29 +45,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_COCPU_STATE")
-            .field(
-                "cocpu_clk_en",
-                &format_args!("{}", self.cocpu_clk_en().bit()),
-            )
-            .field(
-                "cocpu_reset_n",
-                &format_args!("{}", self.cocpu_reset_n().bit()),
-            )
-            .field("cocpu_eoi", &format_args!("{}", self.cocpu_eoi().bit()))
-            .field("cocpu_trap", &format_args!("{}", self.cocpu_trap().bit()))
-            .field(
-                "cocpu_ebreak",
-                &format_args!("{}", self.cocpu_ebreak().bit()),
-            )
+            .field("cocpu_clk_en", &self.cocpu_clk_en())
+            .field("cocpu_reset_n", &self.cocpu_reset_n())
+            .field("cocpu_eoi", &self.cocpu_eoi())
+            .field("cocpu_trap", &self.cocpu_trap())
+            .field("cocpu_ebreak", &self.cocpu_ebreak())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - Trigger ULP-RISCV debug registers"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_dac_ctrl1.rs b/esp32s2/src/sens/sar_dac_ctrl1.rs
index 96b632e02f..89c0dc2756 100644
--- a/esp32s2/src/sens/sar_dac_ctrl1.rs
+++ b/esp32s2/src/sens/sar_dac_ctrl1.rs
@@ -89,39 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_DAC_CTRL1")
-            .field("sw_fstep", &format_args!("{}", self.sw_fstep().bits()))
-            .field("sw_tone_en", &format_args!("{}", self.sw_tone_en().bit()))
-            .field(
-                "debug_bit_sel",
-                &format_args!("{}", self.debug_bit_sel().bits()),
-            )
-            .field(
-                "dac_dig_force",
-                &format_args!("{}", self.dac_dig_force().bit()),
-            )
-            .field(
-                "dac_clk_force_low",
-                &format_args!("{}", self.dac_clk_force_low().bit()),
-            )
-            .field(
-                "dac_clk_force_high",
-                &format_args!("{}", self.dac_clk_force_high().bit()),
-            )
-            .field("dac_clk_inv", &format_args!("{}", self.dac_clk_inv().bit()))
-            .field("dac_reset", &format_args!("{}", self.dac_reset().bit()))
-            .field(
-                "dac_clkgate_en",
-                &format_args!("{}", self.dac_clkgate_en().bit()),
-            )
+            .field("sw_fstep", &self.sw_fstep())
+            .field("sw_tone_en", &self.sw_tone_en())
+            .field("debug_bit_sel", &self.debug_bit_sel())
+            .field("dac_dig_force", &self.dac_dig_force())
+            .field("dac_clk_force_low", &self.dac_clk_force_low())
+            .field("dac_clk_force_high", &self.dac_clk_force_high())
+            .field("dac_clk_inv", &self.dac_clk_inv())
+            .field("dac_reset", &self.dac_reset())
+            .field("dac_clkgate_en", &self.dac_clkgate_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_DAC_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Frequency step for CW generator can be used to adjust the frequency."]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_dac_ctrl2.rs b/esp32s2/src/sens/sar_dac_ctrl2.rs
index 110d3d6bd7..0a076b9f8d 100644
--- a/esp32s2/src/sens/sar_dac_ctrl2.rs
+++ b/esp32s2/src/sens/sar_dac_ctrl2.rs
@@ -80,23 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_DAC_CTRL2")
-            .field("dac_dc1", &format_args!("{}", self.dac_dc1().bits()))
-            .field("dac_dc2", &format_args!("{}", self.dac_dc2().bits()))
-            .field("dac_scale1", &format_args!("{}", self.dac_scale1().bits()))
-            .field("dac_scale2", &format_args!("{}", self.dac_scale2().bits()))
-            .field("dac_inv1", &format_args!("{}", self.dac_inv1().bits()))
-            .field("dac_inv2", &format_args!("{}", self.dac_inv2().bits()))
-            .field("dac_cw_en1", &format_args!("{}", self.dac_cw_en1().bit()))
-            .field("dac_cw_en2", &format_args!("{}", self.dac_cw_en2().bit()))
+            .field("dac_dc1", &self.dac_dc1())
+            .field("dac_dc2", &self.dac_dc2())
+            .field("dac_scale1", &self.dac_scale1())
+            .field("dac_scale2", &self.dac_scale2())
+            .field("dac_inv1", &self.dac_inv1())
+            .field("dac_inv2", &self.dac_inv2())
+            .field("dac_cw_en1", &self.dac_cw_en1())
+            .field("dac_cw_en2", &self.dac_cw_en2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_DAC_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - DC offset for DAC1 CW generator."]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_hall_ctrl.rs b/esp32s2/src/sens/sar_hall_ctrl.rs
index 33418cd05c..4f330d694a 100644
--- a/esp32s2/src/sens/sar_hall_ctrl.rs
+++ b/esp32s2/src/sens/sar_hall_ctrl.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_HALL_CTRL")
-            .field("xpd_hall", &format_args!("{}", self.xpd_hall().bit()))
-            .field(
-                "xpd_hall_force",
-                &format_args!("{}", self.xpd_hall_force().bit()),
-            )
-            .field("hall_phase", &format_args!("{}", self.hall_phase().bit()))
-            .field(
-                "hall_phase_force",
-                &format_args!("{}", self.hall_phase_force().bit()),
-            )
+            .field("xpd_hall", &self.xpd_hall())
+            .field("xpd_hall_force", &self.xpd_hall_force())
+            .field("hall_phase", &self.hall_phase())
+            .field("hall_phase_force", &self.hall_phase_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_HALL_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - Power on hall sensor and connect to VP and VN"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_i2c_ctrl.rs b/esp32s2/src/sens/sar_i2c_ctrl.rs
index 5713f40f15..2fec25c032 100644
--- a/esp32s2/src/sens/sar_i2c_ctrl.rs
+++ b/esp32s2/src/sens/sar_i2c_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_I2C_CTRL")
-            .field(
-                "sar_i2c_ctrl",
-                &format_args!("{}", self.sar_i2c_ctrl().bits()),
-            )
-            .field(
-                "sar_i2c_start",
-                &format_args!("{}", self.sar_i2c_start().bit()),
-            )
-            .field(
-                "sar_i2c_start_force",
-                &format_args!("{}", self.sar_i2c_start_force().bit()),
-            )
+            .field("sar_i2c_ctrl", &self.sar_i2c_ctrl())
+            .field("sar_i2c_start", &self.sar_i2c_start())
+            .field("sar_i2c_start_force", &self.sar_i2c_start_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_I2C_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - RTC I2C control data. Active only when SENS_SAR_I2C_START_FORCE = 1."]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_io_mux_conf.rs b/esp32s2/src/sens/sar_io_mux_conf.rs
index 33121926ef..9b2bda781e 100644
--- a/esp32s2/src/sens/sar_io_mux_conf.rs
+++ b/esp32s2/src/sens/sar_io_mux_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_IO_MUX_CONF")
-            .field("iomux_reset", &format_args!("{}", self.iomux_reset().bit()))
-            .field(
-                "iomux_clk_gate_en",
-                &format_args!("{}", self.iomux_clk_gate_en().bit()),
-            )
+            .field("iomux_reset", &self.iomux_reset())
+            .field("iomux_clk_gate_en", &self.iomux_clk_gate_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_IO_MUX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - Reset IO MUX by software"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_meas1_ctrl1.rs b/esp32s2/src/sens/sar_meas1_ctrl1.rs
index 6f491f1f8b..1ef08b1c16 100644
--- a/esp32s2/src/sens/sar_meas1_ctrl1.rs
+++ b/esp32s2/src/sens/sar_meas1_ctrl1.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS1_CTRL1")
-            .field(
-                "rtc_saradc_reset",
-                &format_args!("{}", self.rtc_saradc_reset().bit()),
-            )
-            .field(
-                "rtc_saradc_clkgate_en",
-                &format_args!("{}", self.rtc_saradc_clkgate_en().bit()),
-            )
-            .field(
-                "force_xpd_amp",
-                &format_args!("{}", self.force_xpd_amp().bits()),
-            )
-            .field(
-                "amp_rst_fb_force",
-                &format_args!("{}", self.amp_rst_fb_force().bits()),
-            )
-            .field(
-                "amp_short_ref_force",
-                &format_args!("{}", self.amp_short_ref_force().bits()),
-            )
-            .field(
-                "amp_short_ref_gnd_force",
-                &format_args!("{}", self.amp_short_ref_gnd_force().bits()),
-            )
+            .field("rtc_saradc_reset", &self.rtc_saradc_reset())
+            .field("rtc_saradc_clkgate_en", &self.rtc_saradc_clkgate_en())
+            .field("force_xpd_amp", &self.force_xpd_amp())
+            .field("amp_rst_fb_force", &self.amp_rst_fb_force())
+            .field("amp_short_ref_force", &self.amp_short_ref_force())
+            .field("amp_short_ref_gnd_force", &self.amp_short_ref_gnd_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS1_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 22 - SAR ADC software reset."]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_meas1_ctrl2.rs b/esp32s2/src/sens/sar_meas1_ctrl2.rs
index f403ff805c..91273143b3 100644
--- a/esp32s2/src/sens/sar_meas1_ctrl2.rs
+++ b/esp32s2/src/sens/sar_meas1_ctrl2.rs
@@ -58,39 +58,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS1_CTRL2")
-            .field(
-                "meas1_data_sar",
-                &format_args!("{}", self.meas1_data_sar().bits()),
-            )
-            .field(
-                "meas1_done_sar",
-                &format_args!("{}", self.meas1_done_sar().bit()),
-            )
-            .field(
-                "meas1_start_sar",
-                &format_args!("{}", self.meas1_start_sar().bit()),
-            )
-            .field(
-                "meas1_start_force",
-                &format_args!("{}", self.meas1_start_force().bit()),
-            )
-            .field(
-                "sar1_en_pad",
-                &format_args!("{}", self.sar1_en_pad().bits()),
-            )
-            .field(
-                "sar1_en_pad_force",
-                &format_args!("{}", self.sar1_en_pad_force().bit()),
-            )
+            .field("meas1_data_sar", &self.meas1_data_sar())
+            .field("meas1_done_sar", &self.meas1_done_sar())
+            .field("meas1_start_sar", &self.meas1_start_sar())
+            .field("meas1_start_force", &self.meas1_start_force())
+            .field("sar1_en_pad", &self.sar1_en_pad())
+            .field("sar1_en_pad_force", &self.sar1_en_pad_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS1_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - SAR ADC1 controller (in RTC) starts conversion, active only when SENS_MEAS1_START_FORCE = 1."]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_meas1_mux.rs b/esp32s2/src/sens/sar_meas1_mux.rs
index 00143cb918..bc524ca3f9 100644
--- a/esp32s2/src/sens/sar_meas1_mux.rs
+++ b/esp32s2/src/sens/sar_meas1_mux.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS1_MUX")
-            .field(
-                "sar1_dig_force",
-                &format_args!("{}", self.sar1_dig_force().bit()),
-            )
+            .field("sar1_dig_force", &self.sar1_dig_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS1_MUX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - 1: SAR ADC1 controlled by DIG ADC1 CTRL"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_meas2_ctrl1.rs b/esp32s2/src/sens/sar_meas2_ctrl1.rs
index 520bbe9a8a..76a5c9474a 100644
--- a/esp32s2/src/sens/sar_meas2_ctrl1.rs
+++ b/esp32s2/src/sens/sar_meas2_ctrl1.rs
@@ -78,47 +78,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS2_CTRL1")
-            .field(
-                "sar2_cntl_state",
-                &format_args!("{}", self.sar2_cntl_state().bits()),
-            )
-            .field(
-                "sar2_pwdet_cal_en",
-                &format_args!("{}", self.sar2_pwdet_cal_en().bit()),
-            )
-            .field(
-                "sar2_pkdet_cal_en",
-                &format_args!("{}", self.sar2_pkdet_cal_en().bit()),
-            )
-            .field(
-                "sar2_en_test",
-                &format_args!("{}", self.sar2_en_test().bit()),
-            )
-            .field(
-                "sar2_rstb_force",
-                &format_args!("{}", self.sar2_rstb_force().bits()),
-            )
-            .field(
-                "sar2_standby_wait",
-                &format_args!("{}", self.sar2_standby_wait().bits()),
-            )
-            .field(
-                "sar2_rstb_wait",
-                &format_args!("{}", self.sar2_rstb_wait().bits()),
-            )
-            .field(
-                "sar2_xpd_wait",
-                &format_args!("{}", self.sar2_xpd_wait().bits()),
-            )
+            .field("sar2_cntl_state", &self.sar2_cntl_state())
+            .field("sar2_pwdet_cal_en", &self.sar2_pwdet_cal_en())
+            .field("sar2_pkdet_cal_en", &self.sar2_pkdet_cal_en())
+            .field("sar2_en_test", &self.sar2_en_test())
+            .field("sar2_rstb_force", &self.sar2_rstb_force())
+            .field("sar2_standby_wait", &self.sar2_standby_wait())
+            .field("sar2_rstb_wait", &self.sar2_rstb_wait())
+            .field("sar2_xpd_wait", &self.sar2_xpd_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS2_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - rtc control pwdet enable"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_meas2_ctrl2.rs b/esp32s2/src/sens/sar_meas2_ctrl2.rs
index caa897ddd7..8f6f6e6d2c 100644
--- a/esp32s2/src/sens/sar_meas2_ctrl2.rs
+++ b/esp32s2/src/sens/sar_meas2_ctrl2.rs
@@ -58,39 +58,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS2_CTRL2")
-            .field(
-                "meas2_data_sar",
-                &format_args!("{}", self.meas2_data_sar().bits()),
-            )
-            .field(
-                "meas2_done_sar",
-                &format_args!("{}", self.meas2_done_sar().bit()),
-            )
-            .field(
-                "meas2_start_sar",
-                &format_args!("{}", self.meas2_start_sar().bit()),
-            )
-            .field(
-                "meas2_start_force",
-                &format_args!("{}", self.meas2_start_force().bit()),
-            )
-            .field(
-                "sar2_en_pad",
-                &format_args!("{}", self.sar2_en_pad().bits()),
-            )
-            .field(
-                "sar2_en_pad_force",
-                &format_args!("{}", self.sar2_en_pad_force().bit()),
-            )
+            .field("meas2_data_sar", &self.meas2_data_sar())
+            .field("meas2_done_sar", &self.meas2_done_sar())
+            .field("meas2_start_sar", &self.meas2_start_sar())
+            .field("meas2_start_force", &self.meas2_start_force())
+            .field("sar2_en_pad", &self.sar2_en_pad())
+            .field("sar2_en_pad_force", &self.sar2_en_pad_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS2_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - SAR ADC2 controller (in RTC) starts conversion, active only when SENS_MEAS2_START_FORCE = 1."]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_meas2_mux.rs b/esp32s2/src/sens/sar_meas2_mux.rs
index 17716c4130..0e88c34542 100644
--- a/esp32s2/src/sens/sar_meas2_mux.rs
+++ b/esp32s2/src/sens/sar_meas2_mux.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS2_MUX")
-            .field(
-                "sar2_pwdet_cct",
-                &format_args!("{}", self.sar2_pwdet_cct().bits()),
-            )
-            .field(
-                "sar2_rtc_force",
-                &format_args!("{}", self.sar2_rtc_force().bit()),
-            )
+            .field("sar2_pwdet_cct", &self.sar2_pwdet_cct())
+            .field("sar2_rtc_force", &self.sar2_rtc_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS2_MUX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 28:30 - SAR2_PWDET_CCT, PA power detector capacitance tuning."]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_nouse.rs b/esp32s2/src/sens/sar_nouse.rs
index 4b2f73b32b..9a09931465 100644
--- a/esp32s2/src/sens/sar_nouse.rs
+++ b/esp32s2/src/sens/sar_nouse.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_NOUSE")
-            .field("sar_nouse", &format_args!("{}", self.sar_nouse().bits()))
+            .field("sar_nouse", &self.sar_nouse())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_NOUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - sar nouse"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_power_xpd_sar.rs b/esp32s2/src/sens/sar_power_xpd_sar.rs
index 9d9da2af05..f554abf720 100644
--- a/esp32s2/src/sens/sar_power_xpd_sar.rs
+++ b/esp32s2/src/sens/sar_power_xpd_sar.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_POWER_XPD_SAR")
-            .field(
-                "force_xpd_sar",
-                &format_args!("{}", self.force_xpd_sar().bits()),
-            )
-            .field("sarclk_en", &format_args!("{}", self.sarclk_en().bit()))
+            .field("force_xpd_sar", &self.force_xpd_sar())
+            .field("sarclk_en", &self.sarclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_POWER_XPD_SAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 29:30"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_reader1_ctrl.rs b/esp32s2/src/sens/sar_reader1_ctrl.rs
index bfde173a2a..148e2b68f1 100644
--- a/esp32s2/src/sens/sar_reader1_ctrl.rs
+++ b/esp32s2/src/sens/sar_reader1_ctrl.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_READER1_CTRL")
-            .field(
-                "sar1_clk_div",
-                &format_args!("{}", self.sar1_clk_div().bits()),
-            )
-            .field(
-                "sar1_clk_gated",
-                &format_args!("{}", self.sar1_clk_gated().bit()),
-            )
-            .field(
-                "sar1_sample_num",
-                &format_args!("{}", self.sar1_sample_num().bits()),
-            )
-            .field(
-                "sar1_data_inv",
-                &format_args!("{}", self.sar1_data_inv().bit()),
-            )
-            .field("sar1_int_en", &format_args!("{}", self.sar1_int_en().bit()))
+            .field("sar1_clk_div", &self.sar1_clk_div())
+            .field("sar1_clk_gated", &self.sar1_clk_gated())
+            .field("sar1_sample_num", &self.sar1_sample_num())
+            .field("sar1_data_inv", &self.sar1_data_inv())
+            .field("sar1_int_en", &self.sar1_int_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_READER1_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Clock divider."]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_reader1_status.rs b/esp32s2/src/sens/sar_reader1_status.rs
index 3941fd0ed7..7eabed2e0c 100644
--- a/esp32s2/src/sens/sar_reader1_status.rs
+++ b/esp32s2/src/sens/sar_reader1_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_READER1_STATUS")
-            .field(
-                "sar1_reader_status",
-                &format_args!("{}", self.sar1_reader_status().bits()),
-            )
+            .field("sar1_reader_status", &self.sar1_reader_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_READER1_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "saradc1 status for debug\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_reader1_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_READER1_STATUS_SPEC;
 impl crate::RegisterSpec for SAR_READER1_STATUS_SPEC {
diff --git a/esp32s2/src/sens/sar_reader2_ctrl.rs b/esp32s2/src/sens/sar_reader2_ctrl.rs
index d523e660d4..18cb6d7f88 100644
--- a/esp32s2/src/sens/sar_reader2_ctrl.rs
+++ b/esp32s2/src/sens/sar_reader2_ctrl.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_READER2_CTRL")
-            .field(
-                "sar2_clk_div",
-                &format_args!("{}", self.sar2_clk_div().bits()),
-            )
-            .field(
-                "sar2_wait_arb_cycle",
-                &format_args!("{}", self.sar2_wait_arb_cycle().bits()),
-            )
-            .field(
-                "sar2_clk_gated",
-                &format_args!("{}", self.sar2_clk_gated().bit()),
-            )
-            .field(
-                "sar2_sample_num",
-                &format_args!("{}", self.sar2_sample_num().bits()),
-            )
-            .field(
-                "sar2_data_inv",
-                &format_args!("{}", self.sar2_data_inv().bit()),
-            )
-            .field("sar2_int_en", &format_args!("{}", self.sar2_int_en().bit()))
+            .field("sar2_clk_div", &self.sar2_clk_div())
+            .field("sar2_wait_arb_cycle", &self.sar2_wait_arb_cycle())
+            .field("sar2_clk_gated", &self.sar2_clk_gated())
+            .field("sar2_sample_num", &self.sar2_sample_num())
+            .field("sar2_data_inv", &self.sar2_data_inv())
+            .field("sar2_int_en", &self.sar2_int_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_READER2_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - clock divider"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_reader2_status.rs b/esp32s2/src/sens/sar_reader2_status.rs
index 1ca88a35c9..638e97a425 100644
--- a/esp32s2/src/sens/sar_reader2_status.rs
+++ b/esp32s2/src/sens/sar_reader2_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_READER2_STATUS")
-            .field(
-                "sar2_reader_status",
-                &format_args!("{}", self.sar2_reader_status().bits()),
-            )
+            .field("sar2_reader_status", &self.sar2_reader_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_READER2_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "saradc2 status for debug\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_reader2_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_READER2_STATUS_SPEC;
 impl crate::RegisterSpec for SAR_READER2_STATUS_SPEC {
diff --git a/esp32s2/src/sens/sar_slave_addr1.rs b/esp32s2/src/sens/sar_slave_addr1.rs
index a407f4c413..f15462ff00 100644
--- a/esp32s2/src/sens/sar_slave_addr1.rs
+++ b/esp32s2/src/sens/sar_slave_addr1.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR1")
-            .field(
-                "i2c_slave_addr1",
-                &format_args!("{}", self.i2c_slave_addr1().bits()),
-            )
-            .field(
-                "i2c_slave_addr0",
-                &format_args!("{}", self.i2c_slave_addr0().bits()),
-            )
-            .field(
-                "meas_status",
-                &format_args!("{}", self.meas_status().bits()),
-            )
+            .field("i2c_slave_addr1", &self.i2c_slave_addr1())
+            .field("i2c_slave_addr0", &self.i2c_slave_addr0())
+            .field("meas_status", &self.meas_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - RTC I2C slave address 1"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_slave_addr2.rs b/esp32s2/src/sens/sar_slave_addr2.rs
index 083364335d..c40f612256 100644
--- a/esp32s2/src/sens/sar_slave_addr2.rs
+++ b/esp32s2/src/sens/sar_slave_addr2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR2")
-            .field(
-                "i2c_slave_addr3",
-                &format_args!("{}", self.i2c_slave_addr3().bits()),
-            )
-            .field(
-                "i2c_slave_addr2",
-                &format_args!("{}", self.i2c_slave_addr2().bits()),
-            )
+            .field("i2c_slave_addr3", &self.i2c_slave_addr3())
+            .field("i2c_slave_addr2", &self.i2c_slave_addr2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - RTC I2C slave address 3"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_slave_addr3.rs b/esp32s2/src/sens/sar_slave_addr3.rs
index d7ea26ecfc..a83df9c413 100644
--- a/esp32s2/src/sens/sar_slave_addr3.rs
+++ b/esp32s2/src/sens/sar_slave_addr3.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR3")
-            .field(
-                "i2c_slave_addr5",
-                &format_args!("{}", self.i2c_slave_addr5().bits()),
-            )
-            .field(
-                "i2c_slave_addr4",
-                &format_args!("{}", self.i2c_slave_addr4().bits()),
-            )
+            .field("i2c_slave_addr5", &self.i2c_slave_addr5())
+            .field("i2c_slave_addr4", &self.i2c_slave_addr4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - RTC I2C slave address 5"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_slave_addr4.rs b/esp32s2/src/sens/sar_slave_addr4.rs
index 2e396b65ce..4dd4b99160 100644
--- a/esp32s2/src/sens/sar_slave_addr4.rs
+++ b/esp32s2/src/sens/sar_slave_addr4.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR4")
-            .field(
-                "i2c_slave_addr7",
-                &format_args!("{}", self.i2c_slave_addr7().bits()),
-            )
-            .field(
-                "i2c_slave_addr6",
-                &format_args!("{}", self.i2c_slave_addr6().bits()),
-            )
+            .field("i2c_slave_addr7", &self.i2c_slave_addr7())
+            .field("i2c_slave_addr6", &self.i2c_slave_addr6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - RTC I2C slave address 7"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_chn_st.rs b/esp32s2/src/sens/sar_touch_chn_st.rs
index b126ee5eb2..80d0b3ea2a 100644
--- a/esp32s2/src/sens/sar_touch_chn_st.rs
+++ b/esp32s2/src/sens/sar_touch_chn_st.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_CHN_ST")
-            .field(
-                "touch_pad_active",
-                &format_args!("{}", self.touch_pad_active().bits()),
-            )
-            .field(
-                "touch_meas_done",
-                &format_args!("{}", self.touch_meas_done().bit()),
-            )
+            .field("touch_pad_active", &self.touch_pad_active())
+            .field("touch_meas_done", &self.touch_meas_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_CHN_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 15:29 - Clear touch channel"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_conf.rs b/esp32s2/src/sens/sar_touch_conf.rs
index 0b70e6d7d1..6792e693ad 100644
--- a/esp32s2/src/sens/sar_touch_conf.rs
+++ b/esp32s2/src/sens/sar_touch_conf.rs
@@ -69,43 +69,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_CONF")
-            .field(
-                "touch_outen",
-                &format_args!("{}", self.touch_outen().bits()),
-            )
-            .field(
-                "touch_data_sel",
-                &format_args!("{}", self.touch_data_sel().bits()),
-            )
-            .field(
-                "touch_denoise_end",
-                &format_args!("{}", self.touch_denoise_end().bit()),
-            )
-            .field(
-                "touch_unit_end",
-                &format_args!("{}", self.touch_unit_end().bit()),
-            )
-            .field(
-                "touch_approach_pad2",
-                &format_args!("{}", self.touch_approach_pad2().bits()),
-            )
-            .field(
-                "touch_approach_pad1",
-                &format_args!("{}", self.touch_approach_pad1().bits()),
-            )
-            .field(
-                "touch_approach_pad0",
-                &format_args!("{}", self.touch_approach_pad0().bits()),
-            )
+            .field("touch_outen", &self.touch_outen())
+            .field("touch_data_sel", &self.touch_data_sel())
+            .field("touch_denoise_end", &self.touch_denoise_end())
+            .field("touch_unit_end", &self.touch_unit_end())
+            .field("touch_approach_pad2", &self.touch_approach_pad2())
+            .field("touch_approach_pad1", &self.touch_approach_pad1())
+            .field("touch_approach_pad0", &self.touch_approach_pad0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - Enable touch controller output."]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_status0.rs b/esp32s2/src/sens/sar_touch_status0.rs
index 3263c02573..ec5c26e5c6 100644
--- a/esp32s2/src/sens/sar_touch_status0.rs
+++ b/esp32s2/src/sens/sar_touch_status0.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS0")
-            .field(
-                "touch_denoise_data",
-                &format_args!("{}", self.touch_denoise_data().bits()),
-            )
-            .field(
-                "touch_scan_curr",
-                &format_args!("{}", self.touch_scan_curr().bits()),
-            )
+            .field("touch_denoise_data", &self.touch_denoise_data())
+            .field("touch_scan_curr", &self.touch_scan_curr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of touch controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS0_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS0_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status1.rs b/esp32s2/src/sens/sar_touch_status1.rs
index ac2eaaa0b9..10bd3cb845 100644
--- a/esp32s2/src/sens/sar_touch_status1.rs
+++ b/esp32s2/src/sens/sar_touch_status1.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS1")
-            .field(
-                "touch_pad1_data",
-                &format_args!("{}", self.touch_pad1_data().bits()),
-            )
-            .field(
-                "touch_pad1_debounce",
-                &format_args!("{}", self.touch_pad1_debounce().bits()),
-            )
+            .field("touch_pad1_data", &self.touch_pad1_data())
+            .field("touch_pad1_debounce", &self.touch_pad1_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch pad 1 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS1_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS1_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status10.rs b/esp32s2/src/sens/sar_touch_status10.rs
index 13eeffacee..67f8082208 100644
--- a/esp32s2/src/sens/sar_touch_status10.rs
+++ b/esp32s2/src/sens/sar_touch_status10.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS10")
-            .field(
-                "touch_pad10_data",
-                &format_args!("{}", self.touch_pad10_data().bits()),
-            )
-            .field(
-                "touch_pad10_debounce",
-                &format_args!("{}", self.touch_pad10_debounce().bits()),
-            )
+            .field("touch_pad10_data", &self.touch_pad10_data())
+            .field("touch_pad10_debounce", &self.touch_pad10_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch pad 10 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS10_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS10_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status11.rs b/esp32s2/src/sens/sar_touch_status11.rs
index 627ae71ad4..3df44bd0f0 100644
--- a/esp32s2/src/sens/sar_touch_status11.rs
+++ b/esp32s2/src/sens/sar_touch_status11.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS11")
-            .field(
-                "touch_pad11_data",
-                &format_args!("{}", self.touch_pad11_data().bits()),
-            )
-            .field(
-                "touch_pad11_debounce",
-                &format_args!("{}", self.touch_pad11_debounce().bits()),
-            )
+            .field("touch_pad11_data", &self.touch_pad11_data())
+            .field("touch_pad11_debounce", &self.touch_pad11_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch pad 11 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS11_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS11_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status12.rs b/esp32s2/src/sens/sar_touch_status12.rs
index d1c4f431fa..29101c321d 100644
--- a/esp32s2/src/sens/sar_touch_status12.rs
+++ b/esp32s2/src/sens/sar_touch_status12.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS12")
-            .field(
-                "touch_pad12_data",
-                &format_args!("{}", self.touch_pad12_data().bits()),
-            )
-            .field(
-                "touch_pad12_debounce",
-                &format_args!("{}", self.touch_pad12_debounce().bits()),
-            )
+            .field("touch_pad12_data", &self.touch_pad12_data())
+            .field("touch_pad12_debounce", &self.touch_pad12_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch pad 12 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status12::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS12_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS12_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status13.rs b/esp32s2/src/sens/sar_touch_status13.rs
index a1a648ea79..a0415870fb 100644
--- a/esp32s2/src/sens/sar_touch_status13.rs
+++ b/esp32s2/src/sens/sar_touch_status13.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS13")
-            .field(
-                "touch_pad13_data",
-                &format_args!("{}", self.touch_pad13_data().bits()),
-            )
-            .field(
-                "touch_pad13_debounce",
-                &format_args!("{}", self.touch_pad13_debounce().bits()),
-            )
+            .field("touch_pad13_data", &self.touch_pad13_data())
+            .field("touch_pad13_debounce", &self.touch_pad13_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch pad 13 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status13::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS13_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS13_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status14.rs b/esp32s2/src/sens/sar_touch_status14.rs
index 34d6aba3f8..2ac64a5911 100644
--- a/esp32s2/src/sens/sar_touch_status14.rs
+++ b/esp32s2/src/sens/sar_touch_status14.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS14")
-            .field(
-                "touch_pad14_data",
-                &format_args!("{}", self.touch_pad14_data().bits()),
-            )
-            .field(
-                "touch_pad14_debounce",
-                &format_args!("{}", self.touch_pad14_debounce().bits()),
-            )
+            .field("touch_pad14_data", &self.touch_pad14_data())
+            .field("touch_pad14_debounce", &self.touch_pad14_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch pad 14 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status14::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS14_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS14_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status15.rs b/esp32s2/src/sens/sar_touch_status15.rs
index 0381c9449f..89e1e0df04 100644
--- a/esp32s2/src/sens/sar_touch_status15.rs
+++ b/esp32s2/src/sens/sar_touch_status15.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS15")
-            .field(
-                "touch_slp_data",
-                &format_args!("{}", self.touch_slp_data().bits()),
-            )
-            .field(
-                "touch_slp_debounce",
-                &format_args!("{}", self.touch_slp_debounce().bits()),
-            )
+            .field("touch_slp_data", &self.touch_slp_data())
+            .field("touch_slp_debounce", &self.touch_slp_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch sleep pad status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status15::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS15_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS15_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status16.rs b/esp32s2/src/sens/sar_touch_status16.rs
index 63a27c2205..05a23ee97a 100644
--- a/esp32s2/src/sens/sar_touch_status16.rs
+++ b/esp32s2/src/sens/sar_touch_status16.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS16")
-            .field(
-                "touch_approach_pad2_cnt",
-                &format_args!("{}", self.touch_approach_pad2_cnt().bits()),
-            )
-            .field(
-                "touch_approach_pad1_cnt",
-                &format_args!("{}", self.touch_approach_pad1_cnt().bits()),
-            )
-            .field(
-                "touch_approach_pad0_cnt",
-                &format_args!("{}", self.touch_approach_pad0_cnt().bits()),
-            )
-            .field(
-                "touch_slp_approach_cnt",
-                &format_args!("{}", self.touch_slp_approach_cnt().bits()),
-            )
+            .field("touch_approach_pad2_cnt", &self.touch_approach_pad2_cnt())
+            .field("touch_approach_pad1_cnt", &self.touch_approach_pad1_cnt())
+            .field("touch_approach_pad0_cnt", &self.touch_approach_pad0_cnt())
+            .field("touch_slp_approach_cnt", &self.touch_slp_approach_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS16_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch approach count status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status16::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS16_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS16_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status2.rs b/esp32s2/src/sens/sar_touch_status2.rs
index 469337dd67..d084f5a26b 100644
--- a/esp32s2/src/sens/sar_touch_status2.rs
+++ b/esp32s2/src/sens/sar_touch_status2.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS2")
-            .field(
-                "touch_pad2_data",
-                &format_args!("{}", self.touch_pad2_data().bits()),
-            )
-            .field(
-                "touch_pad2_debounce",
-                &format_args!("{}", self.touch_pad2_debounce().bits()),
-            )
+            .field("touch_pad2_data", &self.touch_pad2_data())
+            .field("touch_pad2_debounce", &self.touch_pad2_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch pad 2 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS2_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS2_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status3.rs b/esp32s2/src/sens/sar_touch_status3.rs
index 08537843c2..c3eca3497b 100644
--- a/esp32s2/src/sens/sar_touch_status3.rs
+++ b/esp32s2/src/sens/sar_touch_status3.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS3")
-            .field(
-                "touch_pad3_data",
-                &format_args!("{}", self.touch_pad3_data().bits()),
-            )
-            .field(
-                "touch_pad3_debounce",
-                &format_args!("{}", self.touch_pad3_debounce().bits()),
-            )
+            .field("touch_pad3_data", &self.touch_pad3_data())
+            .field("touch_pad3_debounce", &self.touch_pad3_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch pad 3 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS3_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS3_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status4.rs b/esp32s2/src/sens/sar_touch_status4.rs
index 843082a79a..67bb3209cd 100644
--- a/esp32s2/src/sens/sar_touch_status4.rs
+++ b/esp32s2/src/sens/sar_touch_status4.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS4")
-            .field(
-                "touch_pad4_data",
-                &format_args!("{}", self.touch_pad4_data().bits()),
-            )
-            .field(
-                "touch_pad4_debounce",
-                &format_args!("{}", self.touch_pad4_debounce().bits()),
-            )
+            .field("touch_pad4_data", &self.touch_pad4_data())
+            .field("touch_pad4_debounce", &self.touch_pad4_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch pad 4 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS4_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS4_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status5.rs b/esp32s2/src/sens/sar_touch_status5.rs
index d524a8d731..155d583678 100644
--- a/esp32s2/src/sens/sar_touch_status5.rs
+++ b/esp32s2/src/sens/sar_touch_status5.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS5")
-            .field(
-                "touch_pad5_data",
-                &format_args!("{}", self.touch_pad5_data().bits()),
-            )
-            .field(
-                "touch_pad5_debounce",
-                &format_args!("{}", self.touch_pad5_debounce().bits()),
-            )
+            .field("touch_pad5_data", &self.touch_pad5_data())
+            .field("touch_pad5_debounce", &self.touch_pad5_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch pad 5 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS5_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS5_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status6.rs b/esp32s2/src/sens/sar_touch_status6.rs
index ec366a7804..4a31f3af14 100644
--- a/esp32s2/src/sens/sar_touch_status6.rs
+++ b/esp32s2/src/sens/sar_touch_status6.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS6")
-            .field(
-                "touch_pad6_data",
-                &format_args!("{}", self.touch_pad6_data().bits()),
-            )
-            .field(
-                "touch_pad6_debounce",
-                &format_args!("{}", self.touch_pad6_debounce().bits()),
-            )
+            .field("touch_pad6_data", &self.touch_pad6_data())
+            .field("touch_pad6_debounce", &self.touch_pad6_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch pad 6 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS6_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS6_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status7.rs b/esp32s2/src/sens/sar_touch_status7.rs
index 0fc34dacfd..ad2c056b6d 100644
--- a/esp32s2/src/sens/sar_touch_status7.rs
+++ b/esp32s2/src/sens/sar_touch_status7.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS7")
-            .field(
-                "touch_pad7_data",
-                &format_args!("{}", self.touch_pad7_data().bits()),
-            )
-            .field(
-                "touch_pad7_debounce",
-                &format_args!("{}", self.touch_pad7_debounce().bits()),
-            )
+            .field("touch_pad7_data", &self.touch_pad7_data())
+            .field("touch_pad7_debounce", &self.touch_pad7_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch pad 7 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS7_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS7_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status8.rs b/esp32s2/src/sens/sar_touch_status8.rs
index f58694d33e..9ab2059871 100644
--- a/esp32s2/src/sens/sar_touch_status8.rs
+++ b/esp32s2/src/sens/sar_touch_status8.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS8")
-            .field(
-                "touch_pad8_data",
-                &format_args!("{}", self.touch_pad8_data().bits()),
-            )
-            .field(
-                "touch_pad8_debounce",
-                &format_args!("{}", self.touch_pad8_debounce().bits()),
-            )
+            .field("touch_pad8_data", &self.touch_pad8_data())
+            .field("touch_pad8_debounce", &self.touch_pad8_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch pad 8 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS8_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS8_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_status9.rs b/esp32s2/src/sens/sar_touch_status9.rs
index baf04784de..04fc4af583 100644
--- a/esp32s2/src/sens/sar_touch_status9.rs
+++ b/esp32s2/src/sens/sar_touch_status9.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS9")
-            .field(
-                "touch_pad9_data",
-                &format_args!("{}", self.touch_pad9_data().bits()),
-            )
-            .field(
-                "touch_pad9_debounce",
-                &format_args!("{}", self.touch_pad9_debounce().bits()),
-            )
+            .field("touch_pad9_data", &self.touch_pad9_data())
+            .field("touch_pad9_debounce", &self.touch_pad9_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Touch pad 9 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS9_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS9_SPEC {
diff --git a/esp32s2/src/sens/sar_touch_thres1.rs b/esp32s2/src/sens/sar_touch_thres1.rs
index 6e3fcd6b65..73be4132a7 100644
--- a/esp32s2/src/sens/sar_touch_thres1.rs
+++ b/esp32s2/src/sens/sar_touch_thres1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES1")
-            .field(
-                "touch_out_th1",
-                &format_args!("{}", self.touch_out_th1().bits()),
-            )
+            .field("touch_out_th1", &self.touch_out_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 1"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_thres10.rs b/esp32s2/src/sens/sar_touch_thres10.rs
index d518ff3150..f6bf7bc331 100644
--- a/esp32s2/src/sens/sar_touch_thres10.rs
+++ b/esp32s2/src/sens/sar_touch_thres10.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES10")
-            .field(
-                "touch_out_th10",
-                &format_args!("{}", self.touch_out_th10().bits()),
-            )
+            .field("touch_out_th10", &self.touch_out_th10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 10"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_thres11.rs b/esp32s2/src/sens/sar_touch_thres11.rs
index 2a137684b5..e6663600a1 100644
--- a/esp32s2/src/sens/sar_touch_thres11.rs
+++ b/esp32s2/src/sens/sar_touch_thres11.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES11")
-            .field(
-                "touch_out_th11",
-                &format_args!("{}", self.touch_out_th11().bits()),
-            )
+            .field("touch_out_th11", &self.touch_out_th11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 11"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_thres12.rs b/esp32s2/src/sens/sar_touch_thres12.rs
index 44b5377869..3f0dd74198 100644
--- a/esp32s2/src/sens/sar_touch_thres12.rs
+++ b/esp32s2/src/sens/sar_touch_thres12.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES12")
-            .field(
-                "touch_out_th12",
-                &format_args!("{}", self.touch_out_th12().bits()),
-            )
+            .field("touch_out_th12", &self.touch_out_th12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 12"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_thres13.rs b/esp32s2/src/sens/sar_touch_thres13.rs
index 86689b9034..d63c65639e 100644
--- a/esp32s2/src/sens/sar_touch_thres13.rs
+++ b/esp32s2/src/sens/sar_touch_thres13.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES13")
-            .field(
-                "touch_out_th13",
-                &format_args!("{}", self.touch_out_th13().bits()),
-            )
+            .field("touch_out_th13", &self.touch_out_th13())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 13"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_thres14.rs b/esp32s2/src/sens/sar_touch_thres14.rs
index 02d934c8cc..ef02fc7d60 100644
--- a/esp32s2/src/sens/sar_touch_thres14.rs
+++ b/esp32s2/src/sens/sar_touch_thres14.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES14")
-            .field(
-                "touch_out_th14",
-                &format_args!("{}", self.touch_out_th14().bits()),
-            )
+            .field("touch_out_th14", &self.touch_out_th14())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 14"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_thres2.rs b/esp32s2/src/sens/sar_touch_thres2.rs
index 527cf0dfaa..c93a065a45 100644
--- a/esp32s2/src/sens/sar_touch_thres2.rs
+++ b/esp32s2/src/sens/sar_touch_thres2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES2")
-            .field(
-                "touch_out_th2",
-                &format_args!("{}", self.touch_out_th2().bits()),
-            )
+            .field("touch_out_th2", &self.touch_out_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 2"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_thres3.rs b/esp32s2/src/sens/sar_touch_thres3.rs
index fa6d94c581..6885bdea26 100644
--- a/esp32s2/src/sens/sar_touch_thres3.rs
+++ b/esp32s2/src/sens/sar_touch_thres3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES3")
-            .field(
-                "touch_out_th3",
-                &format_args!("{}", self.touch_out_th3().bits()),
-            )
+            .field("touch_out_th3", &self.touch_out_th3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 3"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_thres4.rs b/esp32s2/src/sens/sar_touch_thres4.rs
index 7278915faa..bc0b2acbb8 100644
--- a/esp32s2/src/sens/sar_touch_thres4.rs
+++ b/esp32s2/src/sens/sar_touch_thres4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES4")
-            .field(
-                "touch_out_th4",
-                &format_args!("{}", self.touch_out_th4().bits()),
-            )
+            .field("touch_out_th4", &self.touch_out_th4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 4"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_thres5.rs b/esp32s2/src/sens/sar_touch_thres5.rs
index 409fa05e60..1febbc6eb0 100644
--- a/esp32s2/src/sens/sar_touch_thres5.rs
+++ b/esp32s2/src/sens/sar_touch_thres5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES5")
-            .field(
-                "touch_out_th5",
-                &format_args!("{}", self.touch_out_th5().bits()),
-            )
+            .field("touch_out_th5", &self.touch_out_th5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 5"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_thres6.rs b/esp32s2/src/sens/sar_touch_thres6.rs
index aaf69a2854..166d5dea53 100644
--- a/esp32s2/src/sens/sar_touch_thres6.rs
+++ b/esp32s2/src/sens/sar_touch_thres6.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES6")
-            .field(
-                "touch_out_th6",
-                &format_args!("{}", self.touch_out_th6().bits()),
-            )
+            .field("touch_out_th6", &self.touch_out_th6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 6"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_thres7.rs b/esp32s2/src/sens/sar_touch_thres7.rs
index e6f995d8d3..4ccde9a266 100644
--- a/esp32s2/src/sens/sar_touch_thres7.rs
+++ b/esp32s2/src/sens/sar_touch_thres7.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES7")
-            .field(
-                "touch_out_th7",
-                &format_args!("{}", self.touch_out_th7().bits()),
-            )
+            .field("touch_out_th7", &self.touch_out_th7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 7"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_thres8.rs b/esp32s2/src/sens/sar_touch_thres8.rs
index e9942b3180..129f307b1f 100644
--- a/esp32s2/src/sens/sar_touch_thres8.rs
+++ b/esp32s2/src/sens/sar_touch_thres8.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES8")
-            .field(
-                "touch_out_th8",
-                &format_args!("{}", self.touch_out_th8().bits()),
-            )
+            .field("touch_out_th8", &self.touch_out_th8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 8"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_touch_thres9.rs b/esp32s2/src/sens/sar_touch_thres9.rs
index e8e784ebaf..b87d19381b 100644
--- a/esp32s2/src/sens/sar_touch_thres9.rs
+++ b/esp32s2/src/sens/sar_touch_thres9.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES9")
-            .field(
-                "touch_out_th9",
-                &format_args!("{}", self.touch_out_th9().bits()),
-            )
+            .field("touch_out_th9", &self.touch_out_th9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 9"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_tsens_ctrl.rs b/esp32s2/src/sens/sar_tsens_ctrl.rs
index 8abbf85d3d..f7cbfcb4fc 100644
--- a/esp32s2/src/sens/sar_tsens_ctrl.rs
+++ b/esp32s2/src/sens/sar_tsens_ctrl.rs
@@ -76,41 +76,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TSENS_CTRL")
-            .field("tsens_out", &format_args!("{}", self.tsens_out().bits()))
-            .field("tsens_ready", &format_args!("{}", self.tsens_ready().bit()))
-            .field(
-                "tsens_int_en",
-                &format_args!("{}", self.tsens_int_en().bit()),
-            )
-            .field(
-                "tsens_in_inv",
-                &format_args!("{}", self.tsens_in_inv().bit()),
-            )
-            .field(
-                "tsens_clk_div",
-                &format_args!("{}", self.tsens_clk_div().bits()),
-            )
-            .field(
-                "tsens_power_up",
-                &format_args!("{}", self.tsens_power_up().bit()),
-            )
-            .field(
-                "tsens_power_up_force",
-                &format_args!("{}", self.tsens_power_up_force().bit()),
-            )
-            .field(
-                "tsens_dump_out",
-                &format_args!("{}", self.tsens_dump_out().bit()),
-            )
+            .field("tsens_out", &self.tsens_out())
+            .field("tsens_ready", &self.tsens_ready())
+            .field("tsens_int_en", &self.tsens_int_en())
+            .field("tsens_in_inv", &self.tsens_in_inv())
+            .field("tsens_clk_div", &self.tsens_clk_div())
+            .field("tsens_power_up", &self.tsens_power_up())
+            .field("tsens_power_up_force", &self.tsens_power_up_force())
+            .field("tsens_dump_out", &self.tsens_dump_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TSENS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Enable temperature sensor to send out interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sar_tsens_ctrl2.rs b/esp32s2/src/sens/sar_tsens_ctrl2.rs
index 14dce61f7f..bb5b179ddd 100644
--- a/esp32s2/src/sens/sar_tsens_ctrl2.rs
+++ b/esp32s2/src/sens/sar_tsens_ctrl2.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TSENS_CTRL2")
-            .field(
-                "tsens_xpd_wait",
-                &format_args!("{}", self.tsens_xpd_wait().bits()),
-            )
-            .field(
-                "tsens_xpd_force",
-                &format_args!("{}", self.tsens_xpd_force().bits()),
-            )
-            .field(
-                "tsens_clk_inv",
-                &format_args!("{}", self.tsens_clk_inv().bit()),
-            )
-            .field(
-                "tsens_clkgate_en",
-                &format_args!("{}", self.tsens_clkgate_en().bit()),
-            )
-            .field("tsens_reset", &format_args!("{}", self.tsens_reset().bit()))
+            .field("tsens_xpd_wait", &self.tsens_xpd_wait())
+            .field("tsens_xpd_force", &self.tsens_xpd_force())
+            .field("tsens_clk_inv", &self.tsens_clk_inv())
+            .field("tsens_clkgate_en", &self.tsens_clkgate_en())
+            .field("tsens_reset", &self.tsens_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TSENS_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
diff --git a/esp32s2/src/sens/sardate.rs b/esp32s2/src/sens/sardate.rs
index fc8cd6fe6a..e903e9a1aa 100644
--- a/esp32s2/src/sens/sardate.rs
+++ b/esp32s2/src/sens/sardate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SARDATE")
-            .field("sar_date", &format_args!("{}", self.sar_date().bits()))
+            .field("sar_date", &self.sar_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SARDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version Control Register"]
     #[inline(always)]
diff --git a/esp32s2/src/sha/busy.rs b/esp32s2/src/sha/busy.rs
index 2b307d044c..9030d750e8 100644
--- a/esp32s2/src/sha/busy.rs
+++ b/esp32s2/src/sha/busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUSY")
-            .field("state", &format_args!("{}", self.state().bit()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Indicates if SHA Accelerator is busy or not\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUSY_SPEC;
 impl crate::RegisterSpec for BUSY_SPEC {
diff --git a/esp32s2/src/sha/date.rs b/esp32s2/src/sha/date.rs
index 4a54d835bb..f8c468b3e8 100644
--- a/esp32s2/src/sha/date.rs
+++ b/esp32s2/src/sha/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/sha/dma_block_num.rs b/esp32s2/src/sha/dma_block_num.rs
index bab3230992..88dcd84df4 100644
--- a/esp32s2/src/sha/dma_block_num.rs
+++ b/esp32s2/src/sha/dma_block_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_BLOCK_NUM")
-            .field(
-                "dma_block_num",
-                &format_args!("{}", self.dma_block_num().bits()),
-            )
+            .field("dma_block_num", &self.dma_block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Defines the DMA-SHA block number."]
     #[inline(always)]
diff --git a/esp32s2/src/sha/h_mem.rs b/esp32s2/src/sha/h_mem.rs
index 216a37aa29..9195dad91a 100644
--- a/esp32s2/src/sha/h_mem.rs
+++ b/esp32s2/src/sha/h_mem.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("H_MEM")
-            .field("h", &format_args!("{}", self.h().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("H_MEM").field("h", &self.h()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/sha/int_ena.rs b/esp32s2/src/sha/int_ena.rs
index 50b6930537..5d02978b0b 100644
--- a/esp32s2/src/sha/int_ena.rs
+++ b/esp32s2/src/sha/int_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "interrupt_ena",
-                &format_args!("{}", self.interrupt_ena().bit()),
-            )
+            .field("interrupt_ena", &self.interrupt_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enables DMA-SHA interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/sha/m_mem.rs b/esp32s2/src/sha/m_mem.rs
index a8f26da5c2..10473220ae 100644
--- a/esp32s2/src/sha/m_mem.rs
+++ b/esp32s2/src/sha/m_mem.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("M_MEM")
-            .field("m", &format_args!("{}", self.m().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("M_MEM").field("m", &self.m()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/sha/mode.rs b/esp32s2/src/sha/mode.rs
index cc2dbea21f..752f9f313e 100644
--- a/esp32s2/src/sha/mode.rs
+++ b/esp32s2/src/sha/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/sha/t_length.rs b/esp32s2/src/sha/t_length.rs
index 941eaa8bf7..cc9cd23a64 100644
--- a/esp32s2/src/sha/t_length.rs
+++ b/esp32s2/src/sha/t_length.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T_LENGTH")
-            .field("t_length", &format_args!("{}", self.t_length().bits()))
+            .field("t_length", &self.t_length())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T_LENGTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Defines t_length for calculating the initial Hash value for SHA-512/t."]
     #[inline(always)]
diff --git a/esp32s2/src/sha/t_string.rs b/esp32s2/src/sha/t_string.rs
index ef36bc57b5..896f01a52c 100644
--- a/esp32s2/src/sha/t_string.rs
+++ b/esp32s2/src/sha/t_string.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T_STRING")
-            .field("t_string", &format_args!("{}", self.t_string().bits()))
+            .field("t_string", &self.t_string())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T_STRING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Defines t_string for calculating the initial Hash value for SHA-512/t."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/addr.rs b/esp32s2/src/spi0/addr.rs
index 3485825f43..6ec78f32d8 100644
--- a/esp32s2/src/spi0/addr.rs
+++ b/esp32s2/src/spi0/addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR")
-            .field(
-                "usr_addr_value",
-                &format_args!("{}", self.usr_addr_value().bits()),
-            )
+            .field("usr_addr_value", &self.usr_addr_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 31:8\\]:address to slave, \\[7:0\\]:Reserved. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/clock.rs b/esp32s2/src/spi0/clock.rs
index 663923e553..675edcc204 100644
--- a/esp32s2/src/spi0/clock.rs
+++ b/esp32s2/src/spi0/clock.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field("clkdiv_pre", &format_args!("{}", self.clkdiv_pre().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clkdiv_pre", &self.clkdiv_pre())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - In the master mode it must be equal to SPI_CLKCNT_N. In the slave mode it must be 0. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/cmd.rs b/esp32s2/src/spi0/cmd.rs
index 408a76842e..7f2f0f8311 100644
--- a/esp32s2/src/spi0/cmd.rs
+++ b/esp32s2/src/spi0/cmd.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field(
-                "conf_bitlen",
-                &format_args!("{}", self.conf_bitlen().bits()),
-            )
-            .field("usr", &format_args!("{}", self.usr().bit()))
+            .field("conf_bitlen", &self.conf_bitlen())
+            .field("usr", &self.usr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:22 - Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/ctrl.rs b/esp32s2/src/spi0/ctrl.rs
index f6a3a01d60..8c3f8f2284 100644
--- a/esp32s2/src/spi0/ctrl.rs
+++ b/esp32s2/src/spi0/ctrl.rs
@@ -152,37 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("ext_hold_en", &format_args!("{}", self.ext_hold_en().bit()))
-            .field("dummy_out", &format_args!("{}", self.dummy_out().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
-            .field("faddr_oct", &format_args!("{}", self.faddr_oct().bit()))
-            .field("fcmd_dual", &format_args!("{}", self.fcmd_dual().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcmd_oct", &format_args!("{}", self.fcmd_oct().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("fread_oct", &format_args!("{}", self.fread_oct().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("wp", &format_args!("{}", self.wp().bit()))
-            .field(
-                "rd_bit_order",
-                &format_args!("{}", self.rd_bit_order().bit()),
-            )
-            .field(
-                "wr_bit_order",
-                &format_args!("{}", self.wr_bit_order().bit()),
-            )
+            .field("ext_hold_en", &self.ext_hold_en())
+            .field("dummy_out", &self.dummy_out())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("faddr_quad", &self.faddr_quad())
+            .field("faddr_oct", &self.faddr_oct())
+            .field("fcmd_dual", &self.fcmd_dual())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcmd_oct", &self.fcmd_oct())
+            .field("fread_dual", &self.fread_dual())
+            .field("fread_quad", &self.fread_quad())
+            .field("fread_oct", &self.fread_oct())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("wp", &self.wp())
+            .field("rd_bit_order", &self.rd_bit_order())
+            .field("wr_bit_order", &self.wr_bit_order())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - Set the bit to hold spi. The bit is combined with SPI_USR_PREP_HOLD,SPI_USR_CMD_HOLD,SPI_USR_ADDR_HOLD,SPI_USR_DUMMY_HOLD,SPI_USR_DIN_HOLD,SPI_USR_DOUT_HOLD and SPI_USR_HOLD_POL. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/ctrl1.rs b/esp32s2/src/spi0/ctrl1.rs
index 7cc2d75694..3baa5053e3 100644
--- a/esp32s2/src/spi0/ctrl1.rs
+++ b/esp32s2/src/spi0/ctrl1.rs
@@ -53,29 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL1")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
-            .field("clk_mode_13", &format_args!("{}", self.clk_mode_13().bit()))
-            .field(
-                "rsck_data_out",
-                &format_args!("{}", self.rsck_data_out().bit()),
-            )
-            .field(
-                "w16_17_wr_ena",
-                &format_args!("{}", self.w16_17_wr_ena().bit()),
-            )
-            .field(
-                "cs_hold_delay",
-                &format_args!("{}", self.cs_hold_delay().bits()),
-            )
+            .field("clk_mode", &self.clk_mode())
+            .field("clk_mode_13", &self.clk_mode_13())
+            .field("rsck_data_out", &self.rsck_data_out())
+            .field("w16_17_wr_ena", &self.w16_17_wr_ena())
+            .field("cs_hold_delay", &self.cs_hold_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/ctrl2.rs b/esp32s2/src/spi0/ctrl2.rs
index f7f6ef9a1a..f3156c333e 100644
--- a/esp32s2/src/spi0/ctrl2.rs
+++ b/esp32s2/src/spi0/ctrl2.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field(
-                "cs_setup_time",
-                &format_args!("{}", self.cs_setup_time().bits()),
-            )
-            .field(
-                "cs_hold_time",
-                &format_args!("{}", self.cs_hold_time().bits()),
-            )
-            .field(
-                "cs_delay_mode",
-                &format_args!("{}", self.cs_delay_mode().bits()),
-            )
-            .field(
-                "cs_delay_num",
-                &format_args!("{}", self.cs_delay_num().bits()),
-            )
+            .field("cs_setup_time", &self.cs_setup_time())
+            .field("cs_hold_time", &self.cs_hold_time())
+            .field("cs_delay_mode", &self.cs_delay_mode())
+            .field("cs_delay_num", &self.cs_delay_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - (cycles+1) of prepare phase by spi clock this bits are combined with SPI_CS_SETUP bit. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/din_mode.rs b/esp32s2/src/spi0/din_mode.rs
index 206489d26d..e01fbbe919 100644
--- a/esp32s2/src/spi0/din_mode.rs
+++ b/esp32s2/src/spi0/din_mode.rs
@@ -89,27 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_MODE")
-            .field("din0_mode", &format_args!("{}", self.din0_mode().bits()))
-            .field("din1_mode", &format_args!("{}", self.din1_mode().bits()))
-            .field("din2_mode", &format_args!("{}", self.din2_mode().bits()))
-            .field("din3_mode", &format_args!("{}", self.din3_mode().bits()))
-            .field("din4_mode", &format_args!("{}", self.din4_mode().bits()))
-            .field("din5_mode", &format_args!("{}", self.din5_mode().bits()))
-            .field("din6_mode", &format_args!("{}", self.din6_mode().bits()))
-            .field("din7_mode", &format_args!("{}", self.din7_mode().bits()))
-            .field(
-                "timing_clk_ena",
-                &format_args!("{}", self.timing_clk_ena().bit()),
-            )
+            .field("din0_mode", &self.din0_mode())
+            .field("din1_mode", &self.din1_mode())
+            .field("din2_mode", &self.din2_mode())
+            .field("din3_mode", &self.din3_mode())
+            .field("din4_mode", &self.din4_mode())
+            .field("din5_mode", &self.din5_mode())
+            .field("din6_mode", &self.din6_mode())
+            .field("din7_mode", &self.din7_mode())
+            .field("timing_clk_ena", &self.timing_clk_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/din_num.rs b/esp32s2/src/spi0/din_num.rs
index 4f1ae4e395..ed76f35241 100644
--- a/esp32s2/src/spi0/din_num.rs
+++ b/esp32s2/src/spi0/din_num.rs
@@ -80,23 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_NUM")
-            .field("din0_num", &format_args!("{}", self.din0_num().bits()))
-            .field("din1_num", &format_args!("{}", self.din1_num().bits()))
-            .field("din2_num", &format_args!("{}", self.din2_num().bits()))
-            .field("din3_num", &format_args!("{}", self.din3_num().bits()))
-            .field("din4_num", &format_args!("{}", self.din4_num().bits()))
-            .field("din5_num", &format_args!("{}", self.din5_num().bits()))
-            .field("din6_num", &format_args!("{}", self.din6_num().bits()))
-            .field("din7_num", &format_args!("{}", self.din7_num().bits()))
+            .field("din0_num", &self.din0_num())
+            .field("din1_num", &self.din1_num())
+            .field("din2_num", &self.din2_num())
+            .field("din3_num", &self.din3_num())
+            .field("din4_num", &self.din4_num())
+            .field("din5_num", &self.din5_num())
+            .field("din6_num", &self.din6_num())
+            .field("din7_num", &self.din7_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/dma_conf.rs b/esp32s2/src/spi0/dma_conf.rs
index cb8144e4dd..3d782bb29d 100644
--- a/esp32s2/src/spi0/dma_conf.rs
+++ b/esp32s2/src/spi0/dma_conf.rs
@@ -224,93 +224,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
-            .field("out_rst", &format_args!("{}", self.out_rst().bit()))
-            .field(
-                "ahbm_fifo_rst",
-                &format_args!("{}", self.ahbm_fifo_rst().bit()),
-            )
-            .field("ahbm_rst", &format_args!("{}", self.ahbm_rst().bit()))
-            .field(
-                "in_loop_test",
-                &format_args!("{}", self.in_loop_test().bit()),
-            )
-            .field(
-                "out_loop_test",
-                &format_args!("{}", self.out_loop_test().bit()),
-            )
-            .field(
-                "out_auto_wrback",
-                &format_args!("{}", self.out_auto_wrback().bit()),
-            )
-            .field(
-                "out_eof_mode",
-                &format_args!("{}", self.out_eof_mode().bit()),
-            )
-            .field(
-                "outdscr_burst_en",
-                &format_args!("{}", self.outdscr_burst_en().bit()),
-            )
-            .field(
-                "indscr_burst_en",
-                &format_args!("{}", self.indscr_burst_en().bit()),
-            )
-            .field(
-                "out_data_burst_en",
-                &format_args!("{}", self.out_data_burst_en().bit()),
-            )
-            .field(
-                "mem_trans_en",
-                &format_args!("{}", self.mem_trans_en().bit()),
-            )
-            .field("dma_rx_stop", &format_args!("{}", self.dma_rx_stop().bit()))
-            .field("dma_tx_stop", &format_args!("{}", self.dma_tx_stop().bit()))
-            .field(
-                "dma_continue",
-                &format_args!("{}", self.dma_continue().bit()),
-            )
-            .field(
-                "slv_last_seg_pop_clr",
-                &format_args!("{}", self.slv_last_seg_pop_clr().bit()),
-            )
-            .field(
-                "dma_slv_seg_trans_en",
-                &format_args!("{}", self.dma_slv_seg_trans_en().bit()),
-            )
-            .field(
-                "slv_rx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_rx_seg_trans_clr_en().bit()),
-            )
-            .field(
-                "slv_tx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_tx_seg_trans_clr_en().bit()),
-            )
-            .field("rx_eof_en", &format_args!("{}", self.rx_eof_en().bit()))
-            .field(
-                "dma_infifo_full_clr",
-                &format_args!("{}", self.dma_infifo_full_clr().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_clr",
-                &format_args!("{}", self.dma_outfifo_empty_clr().bit()),
-            )
-            .field(
-                "ext_mem_bk_size",
-                &format_args!("{}", self.ext_mem_bk_size().bits()),
-            )
-            .field(
-                "dma_seg_trans_clr",
-                &format_args!("{}", self.dma_seg_trans_clr().bit()),
-            )
+            .field("in_rst", &self.in_rst())
+            .field("out_rst", &self.out_rst())
+            .field("ahbm_fifo_rst", &self.ahbm_fifo_rst())
+            .field("ahbm_rst", &self.ahbm_rst())
+            .field("in_loop_test", &self.in_loop_test())
+            .field("out_loop_test", &self.out_loop_test())
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("out_eof_mode", &self.out_eof_mode())
+            .field("outdscr_burst_en", &self.outdscr_burst_en())
+            .field("indscr_burst_en", &self.indscr_burst_en())
+            .field("out_data_burst_en", &self.out_data_burst_en())
+            .field("mem_trans_en", &self.mem_trans_en())
+            .field("dma_rx_stop", &self.dma_rx_stop())
+            .field("dma_tx_stop", &self.dma_tx_stop())
+            .field("dma_continue", &self.dma_continue())
+            .field("slv_last_seg_pop_clr", &self.slv_last_seg_pop_clr())
+            .field("dma_slv_seg_trans_en", &self.dma_slv_seg_trans_en())
+            .field("slv_rx_seg_trans_clr_en", &self.slv_rx_seg_trans_clr_en())
+            .field("slv_tx_seg_trans_clr_en", &self.slv_tx_seg_trans_clr_en())
+            .field("rx_eof_en", &self.rx_eof_en())
+            .field("dma_infifo_full_clr", &self.dma_infifo_full_clr())
+            .field("dma_outfifo_empty_clr", &self.dma_outfifo_empty_clr())
+            .field("ext_mem_bk_size", &self.ext_mem_bk_size())
+            .field("dma_seg_trans_clr", &self.dma_seg_trans_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - The bit is used to reset in dma fsm and in data fifo pointer."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/dma_in_link.rs b/esp32s2/src/spi0/dma_in_link.rs
index fe8ba6cd21..1c406c9848 100644
--- a/esp32s2/src/spi0/dma_in_link.rs
+++ b/esp32s2/src/spi0/dma_in_link.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_LINK")
-            .field(
-                "inlink_addr",
-                &format_args!("{}", self.inlink_addr().bits()),
-            )
-            .field(
-                "inlink_auto_ret",
-                &format_args!("{}", self.inlink_auto_ret().bit()),
-            )
-            .field("inlink_stop", &format_args!("{}", self.inlink_stop().bit()))
-            .field(
-                "inlink_start",
-                &format_args!("{}", self.inlink_start().bit()),
-            )
-            .field(
-                "inlink_restart",
-                &format_args!("{}", self.inlink_restart().bit()),
-            )
-            .field("dma_rx_ena", &format_args!("{}", self.dma_rx_ena().bit()))
+            .field("inlink_addr", &self.inlink_addr())
+            .field("inlink_auto_ret", &self.inlink_auto_ret())
+            .field("inlink_stop", &self.inlink_stop())
+            .field("inlink_start", &self.inlink_start())
+            .field("inlink_restart", &self.inlink_restart())
+            .field("dma_rx_ena", &self.dma_rx_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - The address of the first inlink descriptor."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/dma_instatus.rs b/esp32s2/src/spi0/dma_instatus.rs
index 8a2fc13afe..87ef3dd0ca 100644
--- a/esp32s2/src/spi0/dma_instatus.rs
+++ b/esp32s2/src/spi0/dma_instatus.rs
@@ -48,39 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INSTATUS")
-            .field(
-                "dma_indscr_addr",
-                &format_args!("{}", self.dma_indscr_addr().bits()),
-            )
-            .field(
-                "dma_indscr_state",
-                &format_args!("{}", self.dma_indscr_state().bits()),
-            )
-            .field(
-                "dma_in_state",
-                &format_args!("{}", self.dma_in_state().bits()),
-            )
-            .field(
-                "dma_infifo_cnt",
-                &format_args!("{}", self.dma_infifo_cnt().bits()),
-            )
-            .field(
-                "dma_infifo_full",
-                &format_args!("{}", self.dma_infifo_full().bit()),
-            )
-            .field(
-                "dma_infifo_empty",
-                &format_args!("{}", self.dma_infifo_empty().bit()),
-            )
+            .field("dma_indscr_addr", &self.dma_indscr_addr())
+            .field("dma_indscr_state", &self.dma_indscr_state())
+            .field("dma_in_state", &self.dma_in_state())
+            .field("dma_infifo_cnt", &self.dma_infifo_cnt())
+            .field("dma_infifo_full", &self.dma_infifo_full())
+            .field("dma_infifo_empty", &self.dma_infifo_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INSTATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI DMA RX status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_instatus::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_INSTATUS_SPEC;
 impl crate::RegisterSpec for DMA_INSTATUS_SPEC {
diff --git a/esp32s2/src/spi0/dma_int_clr.rs b/esp32s2/src/spi0/dma_int_clr.rs
index 7502884277..4ff582e73b 100644
--- a/esp32s2/src/spi0/dma_int_clr.rs
+++ b/esp32s2/src/spi0/dma_int_clr.rs
@@ -152,49 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_CLR")
-            .field(
-                "inlink_dscr_empty",
-                &format_args!("{}", self.inlink_dscr_empty().bit()),
-            )
-            .field(
-                "outlink_dscr_error",
-                &format_args!("{}", self.outlink_dscr_error().bit()),
-            )
-            .field(
-                "inlink_dscr_error",
-                &format_args!("{}", self.inlink_dscr_error().bit()),
-            )
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field(
-                "infifo_full_err",
-                &format_args!("{}", self.infifo_full_err().bit()),
-            )
-            .field(
-                "outfifo_empty_err",
-                &format_args!("{}", self.outfifo_empty_err().bit()),
-            )
-            .field("slv_cmd6", &format_args!("{}", self.slv_cmd6().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
+            .field("inlink_dscr_empty", &self.inlink_dscr_empty())
+            .field("outlink_dscr_error", &self.outlink_dscr_error())
+            .field("inlink_dscr_error", &self.inlink_dscr_error())
+            .field("in_done", &self.in_done())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("infifo_full_err", &self.infifo_full_err())
+            .field("outfifo_empty_err", &self.outfifo_empty_err())
+            .field("slv_cmd6", &self.slv_cmd6())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The clear bit for lack of enough inlink descriptors. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/dma_int_ena.rs b/esp32s2/src/spi0/dma_int_ena.rs
index c48e72ba17..66f9791a30 100644
--- a/esp32s2/src/spi0/dma_int_ena.rs
+++ b/esp32s2/src/spi0/dma_int_ena.rs
@@ -152,49 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ENA")
-            .field(
-                "inlink_dscr_empty",
-                &format_args!("{}", self.inlink_dscr_empty().bit()),
-            )
-            .field(
-                "outlink_dscr_error",
-                &format_args!("{}", self.outlink_dscr_error().bit()),
-            )
-            .field(
-                "inlink_dscr_error",
-                &format_args!("{}", self.inlink_dscr_error().bit()),
-            )
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field(
-                "infifo_full_err",
-                &format_args!("{}", self.infifo_full_err().bit()),
-            )
-            .field(
-                "outfifo_empty_err",
-                &format_args!("{}", self.outfifo_empty_err().bit()),
-            )
-            .field("slv_cmd6", &format_args!("{}", self.slv_cmd6().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
+            .field("inlink_dscr_empty", &self.inlink_dscr_empty())
+            .field("outlink_dscr_error", &self.outlink_dscr_error())
+            .field("inlink_dscr_error", &self.inlink_dscr_error())
+            .field("in_done", &self.in_done())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("infifo_full_err", &self.infifo_full_err())
+            .field("outfifo_empty_err", &self.outfifo_empty_err())
+            .field("slv_cmd6", &self.slv_cmd6())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for lack of enough inlink descriptors. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/dma_int_raw.rs b/esp32s2/src/spi0/dma_int_raw.rs
index 9ed038e8a9..a480497e9e 100644
--- a/esp32s2/src/spi0/dma_int_raw.rs
+++ b/esp32s2/src/spi0/dma_int_raw.rs
@@ -130,49 +130,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_RAW")
-            .field(
-                "inlink_dscr_empty",
-                &format_args!("{}", self.inlink_dscr_empty().bit()),
-            )
-            .field(
-                "outlink_dscr_error",
-                &format_args!("{}", self.outlink_dscr_error().bit()),
-            )
-            .field(
-                "inlink_dscr_error",
-                &format_args!("{}", self.inlink_dscr_error().bit()),
-            )
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field(
-                "infifo_full_err",
-                &format_args!("{}", self.infifo_full_err().bit()),
-            )
-            .field(
-                "outfifo_empty_err",
-                &format_args!("{}", self.outfifo_empty_err().bit()),
-            )
-            .field("slv_cmd6", &format_args!("{}", self.slv_cmd6().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
+            .field("inlink_dscr_empty", &self.inlink_dscr_empty())
+            .field("outlink_dscr_error", &self.outlink_dscr_error())
+            .field("inlink_dscr_error", &self.inlink_dscr_error())
+            .field("in_done", &self.in_done())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("infifo_full_err", &self.infifo_full_err())
+            .field("outfifo_empty_err", &self.outfifo_empty_err())
+            .field("slv_cmd6", &self.slv_cmd6())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 11 - The raw bit for SPI slave CMD6 interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/dma_int_st.rs b/esp32s2/src/spi0/dma_int_st.rs
index ed47be9e5f..a4240651a6 100644
--- a/esp32s2/src/spi0/dma_int_st.rs
+++ b/esp32s2/src/spi0/dma_int_st.rs
@@ -130,49 +130,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ST")
-            .field(
-                "inlink_dscr_empty",
-                &format_args!("{}", self.inlink_dscr_empty().bit()),
-            )
-            .field(
-                "outlink_dscr_error",
-                &format_args!("{}", self.outlink_dscr_error().bit()),
-            )
-            .field(
-                "inlink_dscr_error",
-                &format_args!("{}", self.inlink_dscr_error().bit()),
-            )
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field(
-                "infifo_full_err",
-                &format_args!("{}", self.infifo_full_err().bit()),
-            )
-            .field(
-                "outfifo_empty_err",
-                &format_args!("{}", self.outfifo_empty_err().bit()),
-            )
-            .field("slv_cmd6", &format_args!("{}", self.slv_cmd6().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
+            .field("inlink_dscr_empty", &self.inlink_dscr_empty())
+            .field("outlink_dscr_error", &self.outlink_dscr_error())
+            .field("inlink_dscr_error", &self.inlink_dscr_error())
+            .field("in_done", &self.in_done())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("infifo_full_err", &self.infifo_full_err())
+            .field("outfifo_empty_err", &self.outfifo_empty_err())
+            .field("slv_cmd6", &self.slv_cmd6())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 11 - The status bit for SPI slave CMD6 interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/dma_out_link.rs b/esp32s2/src/spi0/dma_out_link.rs
index 52ff15ec48..36caa1c403 100644
--- a/esp32s2/src/spi0/dma_out_link.rs
+++ b/esp32s2/src/spi0/dma_out_link.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_LINK")
-            .field(
-                "outlink_addr",
-                &format_args!("{}", self.outlink_addr().bits()),
-            )
-            .field(
-                "outlink_stop",
-                &format_args!("{}", self.outlink_stop().bit()),
-            )
-            .field(
-                "outlink_start",
-                &format_args!("{}", self.outlink_start().bit()),
-            )
-            .field(
-                "outlink_restart",
-                &format_args!("{}", self.outlink_restart().bit()),
-            )
-            .field("dma_tx_ena", &format_args!("{}", self.dma_tx_ena().bit()))
+            .field("outlink_addr", &self.outlink_addr())
+            .field("outlink_stop", &self.outlink_stop())
+            .field("outlink_start", &self.outlink_start())
+            .field("outlink_restart", &self.outlink_restart())
+            .field("dma_tx_ena", &self.dma_tx_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - The address of the first outlink descriptor."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/dma_outstatus.rs b/esp32s2/src/spi0/dma_outstatus.rs
index 145de4a24e..4d97f1ebf5 100644
--- a/esp32s2/src/spi0/dma_outstatus.rs
+++ b/esp32s2/src/spi0/dma_outstatus.rs
@@ -48,39 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUTSTATUS")
-            .field(
-                "dma_outdscr_addr",
-                &format_args!("{}", self.dma_outdscr_addr().bits()),
-            )
-            .field(
-                "dma_outdscr_state",
-                &format_args!("{}", self.dma_outdscr_state().bits()),
-            )
-            .field(
-                "dma_out_state",
-                &format_args!("{}", self.dma_out_state().bits()),
-            )
-            .field(
-                "dma_outfifo_cnt",
-                &format_args!("{}", self.dma_outfifo_cnt().bits()),
-            )
-            .field(
-                "dma_outfifo_full",
-                &format_args!("{}", self.dma_outfifo_full().bit()),
-            )
-            .field(
-                "dma_outfifo_empty",
-                &format_args!("{}", self.dma_outfifo_empty().bit()),
-            )
+            .field("dma_outdscr_addr", &self.dma_outdscr_addr())
+            .field("dma_outdscr_state", &self.dma_outdscr_state())
+            .field("dma_out_state", &self.dma_out_state())
+            .field("dma_outfifo_cnt", &self.dma_outfifo_cnt())
+            .field("dma_outfifo_full", &self.dma_outfifo_full())
+            .field("dma_outfifo_empty", &self.dma_outfifo_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUTSTATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI DMA TX status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_outstatus::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_OUTSTATUS_SPEC;
 impl crate::RegisterSpec for DMA_OUTSTATUS_SPEC {
diff --git a/esp32s2/src/spi0/dout_mode.rs b/esp32s2/src/spi0/dout_mode.rs
index fa904211f8..ad25d23355 100644
--- a/esp32s2/src/spi0/dout_mode.rs
+++ b/esp32s2/src/spi0/dout_mode.rs
@@ -80,23 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOUT_MODE")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bits()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bits()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bits()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bits()))
-            .field("dout4_mode", &format_args!("{}", self.dout4_mode().bits()))
-            .field("dout5_mode", &format_args!("{}", self.dout5_mode().bits()))
-            .field("dout6_mode", &format_args!("{}", self.dout6_mode().bits()))
-            .field("dout7_mode", &format_args!("{}", self.dout7_mode().bits()))
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
+            .field("dout4_mode", &self.dout4_mode())
+            .field("dout5_mode", &self.dout5_mode())
+            .field("dout6_mode", &self.dout6_mode())
+            .field("dout7_mode", &self.dout7_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/dout_num.rs b/esp32s2/src/spi0/dout_num.rs
index c6f367d8f9..ff999baec7 100644
--- a/esp32s2/src/spi0/dout_num.rs
+++ b/esp32s2/src/spi0/dout_num.rs
@@ -80,23 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOUT_NUM")
-            .field("dout0_num", &format_args!("{}", self.dout0_num().bits()))
-            .field("dout1_num", &format_args!("{}", self.dout1_num().bits()))
-            .field("dout2_num", &format_args!("{}", self.dout2_num().bits()))
-            .field("dout3_num", &format_args!("{}", self.dout3_num().bits()))
-            .field("dout4_num", &format_args!("{}", self.dout4_num().bits()))
-            .field("dout5_num", &format_args!("{}", self.dout5_num().bits()))
-            .field("dout6_num", &format_args!("{}", self.dout6_num().bits()))
-            .field("dout7_num", &format_args!("{}", self.dout7_num().bits()))
+            .field("dout0_num", &self.dout0_num())
+            .field("dout1_num", &self.dout1_num())
+            .field("dout2_num", &self.dout2_num())
+            .field("dout3_num", &self.dout3_num())
+            .field("dout4_num", &self.dout4_num())
+            .field("dout5_num", &self.dout5_num())
+            .field("dout6_num", &self.dout6_num())
+            .field("dout7_num", &self.dout7_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOUT_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/fsm.rs b/esp32s2/src/spi0/fsm.rs
index 14e73fee75..2c72ff5b21 100644
--- a/esp32s2/src/spi0/fsm.rs
+++ b/esp32s2/src/spi0/fsm.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM")
-            .field("st", &format_args!("{}", self.st().bits()))
-            .field(
-                "mst_dma_rd_bytelen",
-                &format_args!("{}", self.mst_dma_rd_bytelen().bits()),
-            )
+            .field("st", &self.st())
+            .field("mst_dma_rd_bytelen", &self.mst_dma_rd_bytelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 12:31 - Define the master DMA read byte length in non seg-conf-trans or seg-conf-trans mode. Invalid when SPI_RX_EOF_EN is 0. Can be configured in CONF state.."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/hold.rs b/esp32s2/src/spi0/hold.rs
index 91680b3043..f026aed008 100644
--- a/esp32s2/src/spi0/hold.rs
+++ b/esp32s2/src/spi0/hold.rs
@@ -53,26 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOLD")
-            .field(
-                "int_hold_ena",
-                &format_args!("{}", self.int_hold_ena().bits()),
-            )
-            .field("val", &format_args!("{}", self.val().bit()))
-            .field("out_en", &format_args!("{}", self.out_en().bit()))
-            .field("out_time", &format_args!("{}", self.out_time().bits()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
+            .field("int_hold_ena", &self.int_hold_ena())
+            .field("val", &self.val())
+            .field("out_en", &self.out_en())
+            .field("out_time", &self.out_time())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set, if the other SPI is busy, the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/in_err_eof_des_addr.rs b/esp32s2/src/spi0/in_err_eof_des_addr.rs
index cf3a427fc2..1b03753ac6 100644
--- a/esp32s2/src/spi0/in_err_eof_des_addr.rs
+++ b/esp32s2/src/spi0/in_err_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_ERR_EOF_DES_ADDR")
-            .field(
-                "dma_in_err_eof_des_addr",
-                &format_args!("{}", self.dma_in_err_eof_des_addr().bits()),
-            )
+            .field("dma_in_err_eof_des_addr", &self.dma_in_err_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_ERR_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The latest SPI DMA RX descriptor address receiving error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_ERR_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_SPEC {
diff --git a/esp32s2/src/spi0/in_suc_eof_des_addr.rs b/esp32s2/src/spi0/in_suc_eof_des_addr.rs
index 298106ff9e..b9ccd75583 100644
--- a/esp32s2/src/spi0/in_suc_eof_des_addr.rs
+++ b/esp32s2/src/spi0/in_suc_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_SUC_EOF_DES_ADDR")
-            .field(
-                "dma_in_suc_eof_des_addr",
-                &format_args!("{}", self.dma_in_suc_eof_des_addr().bits()),
-            )
+            .field("dma_in_suc_eof_des_addr", &self.dma_in_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SUC_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The latest SPI DMA eof RX descriptor address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SUC_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_SPEC {
diff --git a/esp32s2/src/spi0/inlink_dscr.rs b/esp32s2/src/spi0/inlink_dscr.rs
index 2d6769b8fd..eba3e2b3eb 100644
--- a/esp32s2/src/spi0/inlink_dscr.rs
+++ b/esp32s2/src/spi0/inlink_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INLINK_DSCR")
-            .field(
-                "dma_inlink_dscr",
-                &format_args!("{}", self.dma_inlink_dscr().bits()),
-            )
+            .field("dma_inlink_dscr", &self.dma_inlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INLINK_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current SPI DMA RX descriptor pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inlink_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INLINK_DSCR_SPEC;
 impl crate::RegisterSpec for INLINK_DSCR_SPEC {
diff --git a/esp32s2/src/spi0/inlink_dscr_bf0.rs b/esp32s2/src/spi0/inlink_dscr_bf0.rs
index 1917b1c323..f99a0cbb8b 100644
--- a/esp32s2/src/spi0/inlink_dscr_bf0.rs
+++ b/esp32s2/src/spi0/inlink_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INLINK_DSCR_BF0")
-            .field(
-                "dma_inlink_dscr_bf0",
-                &format_args!("{}", self.dma_inlink_dscr_bf0().bits()),
-            )
+            .field("dma_inlink_dscr_bf0", &self.dma_inlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INLINK_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Next SPI DMA RX descriptor pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inlink_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INLINK_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for INLINK_DSCR_BF0_SPEC {
diff --git a/esp32s2/src/spi0/inlink_dscr_bf1.rs b/esp32s2/src/spi0/inlink_dscr_bf1.rs
index 49d98f3c75..37a715076a 100644
--- a/esp32s2/src/spi0/inlink_dscr_bf1.rs
+++ b/esp32s2/src/spi0/inlink_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INLINK_DSCR_BF1")
-            .field(
-                "dma_inlink_dscr_bf1",
-                &format_args!("{}", self.dma_inlink_dscr_bf1().bits()),
-            )
+            .field("dma_inlink_dscr_bf1", &self.dma_inlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INLINK_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current SPI DMA RX buffer pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inlink_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INLINK_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for INLINK_DSCR_BF1_SPEC {
diff --git a/esp32s2/src/spi0/lcd_ctrl.rs b/esp32s2/src/spi0/lcd_ctrl.rs
index 8f5c4466af..d763388947 100644
--- a/esp32s2/src/spi0/lcd_ctrl.rs
+++ b/esp32s2/src/spi0/lcd_ctrl.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CTRL")
-            .field(
-                "lcd_hb_front",
-                &format_args!("{}", self.lcd_hb_front().bits()),
-            )
-            .field(
-                "lcd_va_height",
-                &format_args!("{}", self.lcd_va_height().bits()),
-            )
-            .field(
-                "lcd_vt_height",
-                &format_args!("{}", self.lcd_vt_height().bits()),
-            )
-            .field("lcd_mode_en", &format_args!("{}", self.lcd_mode_en().bit()))
+            .field("lcd_hb_front", &self.lcd_hb_front())
+            .field("lcd_va_height", &self.lcd_va_height())
+            .field("lcd_vt_height", &self.lcd_vt_height())
+            .field("lcd_mode_en", &self.lcd_mode_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - It is the horizontal blank front porch of a frame. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/lcd_ctrl1.rs b/esp32s2/src/spi0/lcd_ctrl1.rs
index 81e22031e3..28a6d12403 100644
--- a/esp32s2/src/spi0/lcd_ctrl1.rs
+++ b/esp32s2/src/spi0/lcd_ctrl1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CTRL1")
-            .field(
-                "lcd_vb_front",
-                &format_args!("{}", self.lcd_vb_front().bits()),
-            )
-            .field(
-                "lcd_ha_width",
-                &format_args!("{}", self.lcd_ha_width().bits()),
-            )
-            .field(
-                "lcd_ht_width",
-                &format_args!("{}", self.lcd_ht_width().bits()),
-            )
+            .field("lcd_vb_front", &self.lcd_vb_front())
+            .field("lcd_ha_width", &self.lcd_ha_width())
+            .field("lcd_ht_width", &self.lcd_ht_width())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - It is the vertical blank front porch of a frame. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/lcd_ctrl2.rs b/esp32s2/src/spi0/lcd_ctrl2.rs
index 8fff047f20..2d4efb96c9 100644
--- a/esp32s2/src/spi0/lcd_ctrl2.rs
+++ b/esp32s2/src/spi0/lcd_ctrl2.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CTRL2")
-            .field(
-                "lcd_vsync_width",
-                &format_args!("{}", self.lcd_vsync_width().bits()),
-            )
-            .field(
-                "vsync_idle_pol",
-                &format_args!("{}", self.vsync_idle_pol().bit()),
-            )
-            .field(
-                "lcd_hsync_width",
-                &format_args!("{}", self.lcd_hsync_width().bits()),
-            )
-            .field(
-                "hsync_idle_pol",
-                &format_args!("{}", self.hsync_idle_pol().bit()),
-            )
-            .field(
-                "lcd_hsync_position",
-                &format_args!("{}", self.lcd_hsync_position().bits()),
-            )
+            .field("lcd_vsync_width", &self.lcd_vsync_width())
+            .field("vsync_idle_pol", &self.vsync_idle_pol())
+            .field("lcd_hsync_width", &self.lcd_hsync_width())
+            .field("hsync_idle_pol", &self.hsync_idle_pol())
+            .field("lcd_hsync_position", &self.lcd_hsync_position())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - It is the position of spi_vsync active pulse in a line. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/lcd_d_mode.rs b/esp32s2/src/spi0/lcd_d_mode.rs
index 77d03e7580..a313b2b2f5 100644
--- a/esp32s2/src/spi0/lcd_d_mode.rs
+++ b/esp32s2/src/spi0/lcd_d_mode.rs
@@ -71,28 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_D_MODE")
-            .field("d_dqs_mode", &format_args!("{}", self.d_dqs_mode().bits()))
-            .field("d_cd_mode", &format_args!("{}", self.d_cd_mode().bits()))
-            .field("d_de_mode", &format_args!("{}", self.d_de_mode().bits()))
-            .field(
-                "d_hsync_mode",
-                &format_args!("{}", self.d_hsync_mode().bits()),
-            )
-            .field(
-                "d_vsync_mode",
-                &format_args!("{}", self.d_vsync_mode().bits()),
-            )
-            .field("de_idle_pol", &format_args!("{}", self.de_idle_pol().bit()))
-            .field("hs_blank_en", &format_args!("{}", self.hs_blank_en().bit()))
+            .field("d_dqs_mode", &self.d_dqs_mode())
+            .field("d_cd_mode", &self.d_cd_mode())
+            .field("d_de_mode", &self.d_de_mode())
+            .field("d_hsync_mode", &self.d_hsync_mode())
+            .field("d_vsync_mode", &self.d_vsync_mode())
+            .field("de_idle_pol", &self.de_idle_pol())
+            .field("hs_blank_en", &self.hs_blank_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_D_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - the output spi_dqs is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/lcd_d_num.rs b/esp32s2/src/spi0/lcd_d_num.rs
index c9172f4bb9..ed9fde49a2 100644
--- a/esp32s2/src/spi0/lcd_d_num.rs
+++ b/esp32s2/src/spi0/lcd_d_num.rs
@@ -53,26 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_D_NUM")
-            .field("d_dqs_num", &format_args!("{}", self.d_dqs_num().bits()))
-            .field("d_cd_num", &format_args!("{}", self.d_cd_num().bits()))
-            .field("d_de_num", &format_args!("{}", self.d_de_num().bits()))
-            .field(
-                "d_hsync_num",
-                &format_args!("{}", self.d_hsync_num().bits()),
-            )
-            .field(
-                "d_vsync_num",
-                &format_args!("{}", self.d_vsync_num().bits()),
-            )
+            .field("d_dqs_num", &self.d_dqs_num())
+            .field("d_cd_num", &self.d_cd_num())
+            .field("d_de_num", &self.d_de_num())
+            .field("d_hsync_num", &self.d_hsync_num())
+            .field("d_vsync_num", &self.d_vsync_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_D_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/misc.rs b/esp32s2/src/spi0/misc.rs
index 2077fe8967..4d1f6508b6 100644
--- a/esp32s2/src/spi0/misc.rs
+++ b/esp32s2/src/spi0/misc.rs
@@ -206,64 +206,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
-            .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
-            .field("cs2_dis", &format_args!("{}", self.cs2_dis().bit()))
-            .field("cs3_dis", &format_args!("{}", self.cs3_dis().bit()))
-            .field("cs4_dis", &format_args!("{}", self.cs4_dis().bit()))
-            .field("cs5_dis", &format_args!("{}", self.cs5_dis().bit()))
-            .field("ck_dis", &format_args!("{}", self.ck_dis().bit()))
-            .field(
-                "master_cs_pol",
-                &format_args!("{}", self.master_cs_pol().bits()),
-            )
-            .field(
-                "clk_data_dtr_en",
-                &format_args!("{}", self.clk_data_dtr_en().bit()),
-            )
-            .field("data_dtr_en", &format_args!("{}", self.data_dtr_en().bit()))
-            .field("addr_dtr_en", &format_args!("{}", self.addr_dtr_en().bit()))
-            .field("cmd_dtr_en", &format_args!("{}", self.cmd_dtr_en().bit()))
-            .field("cd_data_set", &format_args!("{}", self.cd_data_set().bit()))
-            .field(
-                "cd_dummy_set",
-                &format_args!("{}", self.cd_dummy_set().bit()),
-            )
-            .field("cd_addr_set", &format_args!("{}", self.cd_addr_set().bit()))
-            .field(
-                "slave_cs_pol",
-                &format_args!("{}", self.slave_cs_pol().bit()),
-            )
-            .field(
-                "dqs_idle_edge",
-                &format_args!("{}", self.dqs_idle_edge().bit()),
-            )
-            .field("cd_cmd_set", &format_args!("{}", self.cd_cmd_set().bit()))
-            .field(
-                "cd_idle_edge",
-                &format_args!("{}", self.cd_idle_edge().bit()),
-            )
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
-            .field(
-                "quad_din_pin_swap",
-                &format_args!("{}", self.quad_din_pin_swap().bit()),
-            )
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("cs2_dis", &self.cs2_dis())
+            .field("cs3_dis", &self.cs3_dis())
+            .field("cs4_dis", &self.cs4_dis())
+            .field("cs5_dis", &self.cs5_dis())
+            .field("ck_dis", &self.ck_dis())
+            .field("master_cs_pol", &self.master_cs_pol())
+            .field("clk_data_dtr_en", &self.clk_data_dtr_en())
+            .field("data_dtr_en", &self.data_dtr_en())
+            .field("addr_dtr_en", &self.addr_dtr_en())
+            .field("cmd_dtr_en", &self.cmd_dtr_en())
+            .field("cd_data_set", &self.cd_data_set())
+            .field("cd_dummy_set", &self.cd_dummy_set())
+            .field("cd_addr_set", &self.cd_addr_set())
+            .field("slave_cs_pol", &self.slave_cs_pol())
+            .field("dqs_idle_edge", &self.dqs_idle_edge())
+            .field("cd_cmd_set", &self.cd_cmd_set())
+            .field("cd_idle_edge", &self.cd_idle_edge())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
+            .field("quad_din_pin_swap", &self.quad_din_pin_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: SPI_CS0 signal is from/to CS0 pin. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/miso_dlen.rs b/esp32s2/src/spi0/miso_dlen.rs
index a04df702c7..725c84467c 100644
--- a/esp32s2/src/spi0/miso_dlen.rs
+++ b/esp32s2/src/spi0/miso_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISO_DLEN")
-            .field(
-                "usr_miso_dbitlen",
-                &format_args!("{}", self.usr_miso_dbitlen().bits()),
-            )
+            .field("usr_miso_dbitlen", &self.usr_miso_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISO_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:22 - The length in bits of read-data. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/mosi_dlen.rs b/esp32s2/src/spi0/mosi_dlen.rs
index 5b2ffc25f5..6c7b71edca 100644
--- a/esp32s2/src/spi0/mosi_dlen.rs
+++ b/esp32s2/src/spi0/mosi_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MOSI_DLEN")
-            .field(
-                "usr_mosi_dbitlen",
-                &format_args!("{}", self.usr_mosi_dbitlen().bits()),
-            )
+            .field("usr_mosi_dbitlen", &self.usr_mosi_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MOSI_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:22 - The length in bits of write-data. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/out_eof_bfr_des_addr.rs b/esp32s2/src/spi0/out_eof_bfr_des_addr.rs
index d121f651e8..743db5cc26 100644
--- a/esp32s2/src/spi0/out_eof_bfr_des_addr.rs
+++ b/esp32s2/src/spi0/out_eof_bfr_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_BFR_DES_ADDR")
-            .field(
-                "dma_out_eof_bfr_des_addr",
-                &format_args!("{}", self.dma_out_eof_bfr_des_addr().bits()),
-            )
+            .field("dma_out_eof_bfr_des_addr", &self.dma_out_eof_bfr_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_BFR_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The latest SPI DMA eof TX buffer address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_bfr_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_BFR_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_SPEC {
diff --git a/esp32s2/src/spi0/out_eof_des_addr.rs b/esp32s2/src/spi0/out_eof_des_addr.rs
index da48031fdb..acb4f7e7eb 100644
--- a/esp32s2/src/spi0/out_eof_des_addr.rs
+++ b/esp32s2/src/spi0/out_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_DES_ADDR")
-            .field(
-                "dma_out_eof_des_addr",
-                &format_args!("{}", self.dma_out_eof_des_addr().bits()),
-            )
+            .field("dma_out_eof_des_addr", &self.dma_out_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The latest SPI DMA eof TX descriptor address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_DES_ADDR_SPEC {
diff --git a/esp32s2/src/spi0/outlink_dscr.rs b/esp32s2/src/spi0/outlink_dscr.rs
index 80462e9973..31d686fe98 100644
--- a/esp32s2/src/spi0/outlink_dscr.rs
+++ b/esp32s2/src/spi0/outlink_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTLINK_DSCR")
-            .field(
-                "dma_outlink_dscr",
-                &format_args!("{}", self.dma_outlink_dscr().bits()),
-            )
+            .field("dma_outlink_dscr", &self.dma_outlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTLINK_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current SPI DMA TX descriptor pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outlink_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTLINK_DSCR_SPEC;
 impl crate::RegisterSpec for OUTLINK_DSCR_SPEC {
diff --git a/esp32s2/src/spi0/outlink_dscr_bf0.rs b/esp32s2/src/spi0/outlink_dscr_bf0.rs
index f758fec4f1..2860c0e374 100644
--- a/esp32s2/src/spi0/outlink_dscr_bf0.rs
+++ b/esp32s2/src/spi0/outlink_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTLINK_DSCR_BF0")
-            .field(
-                "dma_outlink_dscr_bf0",
-                &format_args!("{}", self.dma_outlink_dscr_bf0().bits()),
-            )
+            .field("dma_outlink_dscr_bf0", &self.dma_outlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTLINK_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Next SPI DMA TX descriptor pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outlink_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTLINK_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for OUTLINK_DSCR_BF0_SPEC {
diff --git a/esp32s2/src/spi0/outlink_dscr_bf1.rs b/esp32s2/src/spi0/outlink_dscr_bf1.rs
index a5008368be..2949807bc9 100644
--- a/esp32s2/src/spi0/outlink_dscr_bf1.rs
+++ b/esp32s2/src/spi0/outlink_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTLINK_DSCR_BF1")
-            .field(
-                "dma_outlink_dscr_bf1",
-                &format_args!("{}", self.dma_outlink_dscr_bf1().bits()),
-            )
+            .field("dma_outlink_dscr_bf1", &self.dma_outlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTLINK_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current SPI DMA TX buffer pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outlink_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTLINK_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for OUTLINK_DSCR_BF1_SPEC {
diff --git a/esp32s2/src/spi0/reg_date.rs b/esp32s2/src/spi0/reg_date.rs
index 55a80d8c74..b47ffc349b 100644
--- a/esp32s2/src/spi0/reg_date.rs
+++ b/esp32s2/src/spi0/reg_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - SPI register version."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/slave.rs b/esp32s2/src/spi0/slave.rs
index 75d5414af6..2ee71b6b29 100644
--- a/esp32s2/src/spi0/slave.rs
+++ b/esp32s2/src/spi0/slave.rs
@@ -114,51 +114,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE")
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "int_rd_buf_done_en",
-                &format_args!("{}", self.int_rd_buf_done_en().bit()),
-            )
-            .field(
-                "int_wr_buf_done_en",
-                &format_args!("{}", self.int_wr_buf_done_en().bit()),
-            )
-            .field(
-                "int_rd_dma_done_en",
-                &format_args!("{}", self.int_rd_dma_done_en().bit()),
-            )
-            .field(
-                "int_wr_dma_done_en",
-                &format_args!("{}", self.int_wr_dma_done_en().bit()),
-            )
-            .field(
-                "int_trans_done_en",
-                &format_args!("{}", self.int_trans_done_en().bit()),
-            )
-            .field(
-                "int_dma_seg_trans_en",
-                &format_args!("{}", self.int_dma_seg_trans_en().bit()),
-            )
-            .field(
-                "seg_magic_err_int_en",
-                &format_args!("{}", self.seg_magic_err_int_en().bit()),
-            )
-            .field("trans_cnt", &format_args!("{}", self.trans_cnt().bits()))
-            .field(
-                "trans_done_auto_clr_en",
-                &format_args!("{}", self.trans_done_auto_clr_en().bit()),
-            )
-            .field("mode", &format_args!("{}", self.mode().bit()))
-            .field("soft_reset", &format_args!("{}", self.soft_reset().bit()))
+            .field("trans_done", &self.trans_done())
+            .field("int_rd_buf_done_en", &self.int_rd_buf_done_en())
+            .field("int_wr_buf_done_en", &self.int_wr_buf_done_en())
+            .field("int_rd_dma_done_en", &self.int_rd_dma_done_en())
+            .field("int_wr_dma_done_en", &self.int_wr_dma_done_en())
+            .field("int_trans_done_en", &self.int_trans_done_en())
+            .field("int_dma_seg_trans_en", &self.int_dma_seg_trans_en())
+            .field("seg_magic_err_int_en", &self.seg_magic_err_int_en())
+            .field("trans_cnt", &self.trans_cnt())
+            .field("trans_done_auto_clr_en", &self.trans_done_auto_clr_en())
+            .field("mode", &self.mode())
+            .field("soft_reset", &self.soft_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. Can not be changed by CONF_buf."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/slave1.rs b/esp32s2/src/spi0/slave1.rs
index f12a74fa01..78198c9863 100644
--- a/esp32s2/src/spi0/slave1.rs
+++ b/esp32s2/src/spi0/slave1.rs
@@ -76,44 +76,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE1")
-            .field(
-                "slv_addr_err_clr",
-                &format_args!("{}", self.slv_addr_err_clr().bit()),
-            )
-            .field(
-                "slv_cmd_err_clr",
-                &format_args!("{}", self.slv_cmd_err_clr().bit()),
-            )
-            .field(
-                "slv_no_qpi_en",
-                &format_args!("{}", self.slv_no_qpi_en().bit()),
-            )
-            .field(
-                "slv_addr_err",
-                &format_args!("{}", self.slv_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_last_command",
-                &format_args!("{}", self.slv_last_command().bits()),
-            )
-            .field(
-                "slv_last_addr",
-                &format_args!("{}", self.slv_last_addr().bits()),
-            )
+            .field("slv_addr_err_clr", &self.slv_addr_err_clr())
+            .field("slv_cmd_err_clr", &self.slv_cmd_err_clr())
+            .field("slv_no_qpi_en", &self.slv_no_qpi_en())
+            .field("slv_addr_err", &self.slv_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_last_command", &self.slv_last_command())
+            .field("slv_last_addr", &self.slv_last_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 10 - 1: Clear SPI_SLV_ADDR_ERR. 0: not valid. Can be changed by CONF_buf."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/slv_rd_byte.rs b/esp32s2/src/spi0/slv_rd_byte.rs
index f343f89c8a..4368219622 100644
--- a/esp32s2/src/spi0/slv_rd_byte.rs
+++ b/esp32s2/src/spi0/slv_rd_byte.rs
@@ -80,44 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLV_RD_BYTE")
-            .field(
-                "slv_data_bytelen",
-                &format_args!("{}", self.slv_data_bytelen().bits()),
-            )
-            .field(
-                "slv_rddma_bytelen_en",
-                &format_args!("{}", self.slv_rddma_bytelen_en().bit()),
-            )
-            .field(
-                "slv_wrdma_bytelen_en",
-                &format_args!("{}", self.slv_wrdma_bytelen_en().bit()),
-            )
-            .field(
-                "slv_rdbuf_bytelen_en",
-                &format_args!("{}", self.slv_rdbuf_bytelen_en().bit()),
-            )
-            .field(
-                "slv_wrbuf_bytelen_en",
-                &format_args!("{}", self.slv_wrbuf_bytelen_en().bit()),
-            )
-            .field(
-                "dma_seg_magic_value",
-                &format_args!("{}", self.dma_seg_magic_value().bits()),
-            )
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field("usr_conf", &format_args!("{}", self.usr_conf().bit()))
+            .field("slv_data_bytelen", &self.slv_data_bytelen())
+            .field("slv_rddma_bytelen_en", &self.slv_rddma_bytelen_en())
+            .field("slv_wrdma_bytelen_en", &self.slv_wrdma_bytelen_en())
+            .field("slv_rdbuf_bytelen_en", &self.slv_rdbuf_bytelen_en())
+            .field("slv_wrbuf_bytelen_en", &self.slv_wrbuf_bytelen_en())
+            .field("dma_seg_magic_value", &self.dma_seg_magic_value())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("usr_conf", &self.usr_conf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLV_RD_BYTE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - The full-duplex or half-duplex data byte length of the last SPI transfer in slave mode. In half-duplex mode, this value is controlled by bits \\[23:20\\]."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/slv_rdbuf_dlen.rs b/esp32s2/src/spi0/slv_rdbuf_dlen.rs
index deb36ccf47..27575dddda 100644
--- a/esp32s2/src/spi0/slv_rdbuf_dlen.rs
+++ b/esp32s2/src/spi0/slv_rdbuf_dlen.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLV_RDBUF_DLEN")
-            .field(
-                "slv_dma_rd_bytelen",
-                &format_args!("{}", self.slv_dma_rd_bytelen().bits()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
+            .field("slv_dma_rd_bytelen", &self.slv_dma_rd_bytelen())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("seg_magic_err", &self.seg_magic_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLV_RDBUF_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - In the slave mode it is the length in bytes for read operations. The register value shall be byte_num."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/slv_wrbuf_dlen.rs b/esp32s2/src/spi0/slv_wrbuf_dlen.rs
index f7c9a96656..8f28e9e585 100644
--- a/esp32s2/src/spi0/slv_wrbuf_dlen.rs
+++ b/esp32s2/src/spi0/slv_wrbuf_dlen.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLV_WRBUF_DLEN")
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field(
-                "conf_base_bitlen",
-                &format_args!("{}", self.conf_base_bitlen().bits()),
-            )
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("conf_base_bitlen", &self.conf_base_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLV_WRBUF_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - The interrupt raw bit for the completion of write-buffer operation in the slave mode. Can not be changed by CONF_buf."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/user.rs b/esp32s2/src/spi0/user.rs
index 12160ec0d3..eb6c1a1174 100644
--- a/esp32s2/src/spi0/user.rs
+++ b/esp32s2/src/spi0/user.rs
@@ -278,84 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("doutdin", &format_args!("{}", self.doutdin().bit()))
-            .field("qpi_mode", &format_args!("{}", self.qpi_mode().bit()))
-            .field("opi_mode", &format_args!("{}", self.opi_mode().bit()))
-            .field("tsck_i_edge", &format_args!("{}", self.tsck_i_edge().bit()))
-            .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
-            .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
-            .field("rsck_i_edge", &format_args!("{}", self.rsck_i_edge().bit()))
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field(
-                "rd_byte_order",
-                &format_args!("{}", self.rd_byte_order().bit()),
-            )
-            .field(
-                "wr_byte_order",
-                &format_args!("{}", self.wr_byte_order().bit()),
-            )
-            .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
-            .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
-            .field("fwrite_oct", &format_args!("{}", self.fwrite_oct().bit()))
-            .field(
-                "usr_conf_nxt",
-                &format_args!("{}", self.usr_conf_nxt().bit()),
-            )
-            .field("sio", &format_args!("{}", self.sio().bit()))
-            .field(
-                "usr_hold_pol",
-                &format_args!("{}", self.usr_hold_pol().bit()),
-            )
-            .field(
-                "usr_dout_hold",
-                &format_args!("{}", self.usr_dout_hold().bit()),
-            )
-            .field(
-                "usr_din_hold",
-                &format_args!("{}", self.usr_din_hold().bit()),
-            )
-            .field(
-                "usr_dummy_hold",
-                &format_args!("{}", self.usr_dummy_hold().bit()),
-            )
-            .field(
-                "usr_addr_hold",
-                &format_args!("{}", self.usr_addr_hold().bit()),
-            )
-            .field(
-                "usr_cmd_hold",
-                &format_args!("{}", self.usr_cmd_hold().bit()),
-            )
-            .field(
-                "usr_prep_hold",
-                &format_args!("{}", self.usr_prep_hold().bit()),
-            )
-            .field(
-                "usr_miso_highpart",
-                &format_args!("{}", self.usr_miso_highpart().bit()),
-            )
-            .field(
-                "usr_mosi_highpart",
-                &format_args!("{}", self.usr_mosi_highpart().bit()),
-            )
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
-            .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
-            .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
-            .field("usr_command", &format_args!("{}", self.usr_command().bit()))
+            .field("doutdin", &self.doutdin())
+            .field("qpi_mode", &self.qpi_mode())
+            .field("opi_mode", &self.opi_mode())
+            .field("tsck_i_edge", &self.tsck_i_edge())
+            .field("cs_hold", &self.cs_hold())
+            .field("cs_setup", &self.cs_setup())
+            .field("rsck_i_edge", &self.rsck_i_edge())
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("rd_byte_order", &self.rd_byte_order())
+            .field("wr_byte_order", &self.wr_byte_order())
+            .field("fwrite_dual", &self.fwrite_dual())
+            .field("fwrite_quad", &self.fwrite_quad())
+            .field("fwrite_oct", &self.fwrite_oct())
+            .field("usr_conf_nxt", &self.usr_conf_nxt())
+            .field("sio", &self.sio())
+            .field("usr_hold_pol", &self.usr_hold_pol())
+            .field("usr_dout_hold", &self.usr_dout_hold())
+            .field("usr_din_hold", &self.usr_din_hold())
+            .field("usr_dummy_hold", &self.usr_dummy_hold())
+            .field("usr_addr_hold", &self.usr_addr_hold())
+            .field("usr_cmd_hold", &self.usr_cmd_hold())
+            .field("usr_prep_hold", &self.usr_prep_hold())
+            .field("usr_miso_highpart", &self.usr_miso_highpart())
+            .field("usr_mosi_highpart", &self.usr_mosi_highpart())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_mosi", &self.usr_mosi())
+            .field("usr_miso", &self.usr_miso())
+            .field("usr_dummy", &self.usr_dummy())
+            .field("usr_addr", &self.usr_addr())
+            .field("usr_command", &self.usr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/user1.rs b/esp32s2/src/spi0/user1.rs
index 0626e00aa7..343ebc64ac 100644
--- a/esp32s2/src/spi0/user1.rs
+++ b/esp32s2/src/spi0/user1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/user2.rs b/esp32s2/src/spi0/user2.rs
index f84844d6a5..12178dca43 100644
--- a/esp32s2/src/spi0/user2.rs
+++ b/esp32s2/src/spi0/user2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s2/src/spi0/w.rs b/esp32s2/src/spi0/w.rs
index fd429e742b..e25c54ca67 100644
--- a/esp32s2/src/spi0/w.rs
+++ b/esp32s2/src/spi0/w.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("W")
-            .field("buf", &format_args!("{}", self.buf().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<W_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("W").field("buf", &self.buf()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/syscon/clk_out_en.rs b/esp32s2/src/syscon/clk_out_en.rs
index c23828c1e1..b32685dc88 100644
--- a/esp32s2/src/syscon/clk_out_en.rs
+++ b/esp32s2/src/syscon/clk_out_en.rs
@@ -107,41 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_OUT_EN")
-            .field("clk20_oen", &format_args!("{}", self.clk20_oen().bit()))
-            .field("clk22_oen", &format_args!("{}", self.clk22_oen().bit()))
-            .field("clk44_oen", &format_args!("{}", self.clk44_oen().bit()))
-            .field("clk_bb_oen", &format_args!("{}", self.clk_bb_oen().bit()))
-            .field("clk80_oen", &format_args!("{}", self.clk80_oen().bit()))
-            .field("clk160_oen", &format_args!("{}", self.clk160_oen().bit()))
-            .field(
-                "clk_320m_oen",
-                &format_args!("{}", self.clk_320m_oen().bit()),
-            )
-            .field(
-                "clk_adc_inf_oen",
-                &format_args!("{}", self.clk_adc_inf_oen().bit()),
-            )
-            .field(
-                "clk_dac_cpu_oen",
-                &format_args!("{}", self.clk_dac_cpu_oen().bit()),
-            )
-            .field(
-                "clk40x_bb_oen",
-                &format_args!("{}", self.clk40x_bb_oen().bit()),
-            )
-            .field(
-                "clk_xtal_oen",
-                &format_args!("{}", self.clk_xtal_oen().bit()),
-            )
+            .field("clk20_oen", &self.clk20_oen())
+            .field("clk22_oen", &self.clk22_oen())
+            .field("clk44_oen", &self.clk44_oen())
+            .field("clk_bb_oen", &self.clk_bb_oen())
+            .field("clk80_oen", &self.clk80_oen())
+            .field("clk160_oen", &self.clk160_oen())
+            .field("clk_320m_oen", &self.clk_320m_oen())
+            .field("clk_adc_inf_oen", &self.clk_adc_inf_oen())
+            .field("clk_dac_cpu_oen", &self.clk_dac_cpu_oen())
+            .field("clk40x_bb_oen", &self.clk40x_bb_oen())
+            .field("clk_xtal_oen", &self.clk_xtal_oen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_OUT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/date.rs b/esp32s2/src/syscon/date.rs
index f9eeb91b08..db382806d7 100644
--- a/esp32s2/src/syscon/date.rs
+++ b/esp32s2/src/syscon/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/syscon/ext_mem_pms_lock.rs b/esp32s2/src/syscon/ext_mem_pms_lock.rs
index 8de61a73ac..a16922b09e 100644
--- a/esp32s2/src/syscon/ext_mem_pms_lock.rs
+++ b/esp32s2/src/syscon/ext_mem_pms_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_MEM_PMS_LOCK")
-            .field(
-                "ext_mem_pms_lock",
-                &format_args!("{}", self.ext_mem_pms_lock().bit()),
-            )
+            .field("ext_mem_pms_lock", &self.ext_mem_pms_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_MEM_PMS_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/flash_ace0_addr.rs b/esp32s2/src/syscon/flash_ace0_addr.rs
index bed9186868..94e392dce7 100644
--- a/esp32s2/src/syscon/flash_ace0_addr.rs
+++ b/esp32s2/src/syscon/flash_ace0_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE0_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/flash_ace0_attr.rs b/esp32s2/src/syscon/flash_ace0_attr.rs
index f8944fe1fb..9e5465289d 100644
--- a/esp32s2/src/syscon/flash_ace0_attr.rs
+++ b/esp32s2/src/syscon/flash_ace0_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE0_ATTR")
-            .field(
-                "flash_ace0_attr",
-                &format_args!("{}", self.flash_ace0_attr().bits()),
-            )
+            .field("flash_ace0_attr", &self.flash_ace0_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE0_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/flash_ace0_size.rs b/esp32s2/src/syscon/flash_ace0_size.rs
index 217185ba74..284ca83743 100644
--- a/esp32s2/src/syscon/flash_ace0_size.rs
+++ b/esp32s2/src/syscon/flash_ace0_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE0_SIZE")
-            .field(
-                "flash_ace0_size",
-                &format_args!("{}", self.flash_ace0_size().bits()),
-            )
+            .field("flash_ace0_size", &self.flash_ace0_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/flash_ace1_addr.rs b/esp32s2/src/syscon/flash_ace1_addr.rs
index 17a5d3a3b4..e081ca8cb4 100644
--- a/esp32s2/src/syscon/flash_ace1_addr.rs
+++ b/esp32s2/src/syscon/flash_ace1_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE1_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/flash_ace1_attr.rs b/esp32s2/src/syscon/flash_ace1_attr.rs
index 33957e3967..47a4476c7b 100644
--- a/esp32s2/src/syscon/flash_ace1_attr.rs
+++ b/esp32s2/src/syscon/flash_ace1_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE1_ATTR")
-            .field(
-                "flash_ace1_attr",
-                &format_args!("{}", self.flash_ace1_attr().bits()),
-            )
+            .field("flash_ace1_attr", &self.flash_ace1_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE1_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/flash_ace1_size.rs b/esp32s2/src/syscon/flash_ace1_size.rs
index 5337eaab59..2a3a7bd3f5 100644
--- a/esp32s2/src/syscon/flash_ace1_size.rs
+++ b/esp32s2/src/syscon/flash_ace1_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE1_SIZE")
-            .field(
-                "flash_ace1_size",
-                &format_args!("{}", self.flash_ace1_size().bits()),
-            )
+            .field("flash_ace1_size", &self.flash_ace1_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/flash_ace2_addr.rs b/esp32s2/src/syscon/flash_ace2_addr.rs
index 8931ce6235..00ff6136b1 100644
--- a/esp32s2/src/syscon/flash_ace2_addr.rs
+++ b/esp32s2/src/syscon/flash_ace2_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE2_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/flash_ace2_attr.rs b/esp32s2/src/syscon/flash_ace2_attr.rs
index 54ff60034e..c3ae28b9c5 100644
--- a/esp32s2/src/syscon/flash_ace2_attr.rs
+++ b/esp32s2/src/syscon/flash_ace2_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE2_ATTR")
-            .field(
-                "flash_ace2_attr",
-                &format_args!("{}", self.flash_ace2_attr().bits()),
-            )
+            .field("flash_ace2_attr", &self.flash_ace2_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE2_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/flash_ace2_size.rs b/esp32s2/src/syscon/flash_ace2_size.rs
index 928456d4f1..3b4b2a3b1f 100644
--- a/esp32s2/src/syscon/flash_ace2_size.rs
+++ b/esp32s2/src/syscon/flash_ace2_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE2_SIZE")
-            .field(
-                "flash_ace2_size",
-                &format_args!("{}", self.flash_ace2_size().bits()),
-            )
+            .field("flash_ace2_size", &self.flash_ace2_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE2_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/flash_ace3_addr.rs b/esp32s2/src/syscon/flash_ace3_addr.rs
index b2a5d0ca96..89253d275e 100644
--- a/esp32s2/src/syscon/flash_ace3_addr.rs
+++ b/esp32s2/src/syscon/flash_ace3_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE3_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/flash_ace3_attr.rs b/esp32s2/src/syscon/flash_ace3_attr.rs
index 813fb39fd6..1366e76089 100644
--- a/esp32s2/src/syscon/flash_ace3_attr.rs
+++ b/esp32s2/src/syscon/flash_ace3_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE3_ATTR")
-            .field(
-                "flash_ace3_attr",
-                &format_args!("{}", self.flash_ace3_attr().bits()),
-            )
+            .field("flash_ace3_attr", &self.flash_ace3_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE3_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/flash_ace3_size.rs b/esp32s2/src/syscon/flash_ace3_size.rs
index 5763179cd2..0c5f0e0592 100644
--- a/esp32s2/src/syscon/flash_ace3_size.rs
+++ b/esp32s2/src/syscon/flash_ace3_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE3_SIZE")
-            .field(
-                "flash_ace3_size",
-                &format_args!("{}", self.flash_ace3_size().bits()),
-            )
+            .field("flash_ace3_size", &self.flash_ace3_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE3_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/front_end_mem_pd.rs b/esp32s2/src/syscon/front_end_mem_pd.rs
index d31033308b..c1b67c0d4e 100644
--- a/esp32s2/src/syscon/front_end_mem_pd.rs
+++ b/esp32s2/src/syscon/front_end_mem_pd.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FRONT_END_MEM_PD")
-            .field(
-                "agc_mem_force_pu",
-                &format_args!("{}", self.agc_mem_force_pu().bit()),
-            )
-            .field(
-                "agc_mem_force_pd",
-                &format_args!("{}", self.agc_mem_force_pd().bit()),
-            )
-            .field(
-                "pbus_mem_force_pu",
-                &format_args!("{}", self.pbus_mem_force_pu().bit()),
-            )
-            .field(
-                "pbus_mem_force_pd",
-                &format_args!("{}", self.pbus_mem_force_pd().bit()),
-            )
-            .field(
-                "dc_mem_force_pu",
-                &format_args!("{}", self.dc_mem_force_pu().bit()),
-            )
-            .field(
-                "dc_mem_force_pd",
-                &format_args!("{}", self.dc_mem_force_pd().bit()),
-            )
+            .field("agc_mem_force_pu", &self.agc_mem_force_pu())
+            .field("agc_mem_force_pd", &self.agc_mem_force_pd())
+            .field("pbus_mem_force_pu", &self.pbus_mem_force_pu())
+            .field("pbus_mem_force_pd", &self.pbus_mem_force_pd())
+            .field("dc_mem_force_pu", &self.dc_mem_force_pu())
+            .field("dc_mem_force_pd", &self.dc_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FRONT_END_MEM_PD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/host_inf_sel.rs b/esp32s2/src/syscon/host_inf_sel.rs
index fdd17d068d..89563c815f 100644
--- a/esp32s2/src/syscon/host_inf_sel.rs
+++ b/esp32s2/src/syscon/host_inf_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_INF_SEL")
-            .field(
-                "peri_io_swap",
-                &format_args!("{}", self.peri_io_swap().bits()),
-            )
+            .field("peri_io_swap", &self.peri_io_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_INF_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/redcy_sig0.rs b/esp32s2/src/syscon/redcy_sig0.rs
index f42718f9f2..2154ff3804 100644
--- a/esp32s2/src/syscon/redcy_sig0.rs
+++ b/esp32s2/src/syscon/redcy_sig0.rs
@@ -24,17 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDCY_SIG0")
-            .field("redcy_sig0", &format_args!("{}", self.redcy_sig0().bits()))
-            .field("redcy_andor", &format_args!("{}", self.redcy_andor().bit()))
+            .field("redcy_sig0", &self.redcy_sig0())
+            .field("redcy_andor", &self.redcy_andor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDCY_SIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/redcy_sig1.rs b/esp32s2/src/syscon/redcy_sig1.rs
index 710e1f7904..bec6b71a92 100644
--- a/esp32s2/src/syscon/redcy_sig1.rs
+++ b/esp32s2/src/syscon/redcy_sig1.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDCY_SIG1")
-            .field("redcy_sig1", &format_args!("{}", self.redcy_sig1().bits()))
-            .field(
-                "redcy_nandor",
-                &format_args!("{}", self.redcy_nandor().bit()),
-            )
+            .field("redcy_sig1", &self.redcy_sig1())
+            .field("redcy_nandor", &self.redcy_nandor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDCY_SIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/sdio_ctrl.rs b/esp32s2/src/syscon/sdio_ctrl.rs
index 0898e39b4f..f7a5005c67 100644
--- a/esp32s2/src/syscon/sdio_ctrl.rs
+++ b/esp32s2/src/syscon/sdio_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_CTRL")
-            .field(
-                "sdio_win_access_en",
-                &format_args!("{}", self.sdio_win_access_en().bit()),
-            )
+            .field("sdio_win_access_en", &self.sdio_win_access_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/spi_mem_pms_ctrl.rs b/esp32s2/src/syscon/spi_mem_pms_ctrl.rs
index 1c1c8ea9d0..9e7a93e76c 100644
--- a/esp32s2/src/syscon/spi_mem_pms_ctrl.rs
+++ b/esp32s2/src/syscon/spi_mem_pms_ctrl.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_MEM_PMS_CTRL")
-            .field(
-                "spi_mem_reject_int",
-                &format_args!("{}", self.spi_mem_reject_int().bit()),
-            )
-            .field(
-                "spi_mem_reject_cde",
-                &format_args!("{}", self.spi_mem_reject_cde().bits()),
-            )
+            .field("spi_mem_reject_int", &self.spi_mem_reject_int())
+            .field("spi_mem_reject_cde", &self.spi_mem_reject_cde())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_MEM_PMS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/spi_mem_reject_addr.rs b/esp32s2/src/syscon/spi_mem_reject_addr.rs
index 47238dba90..4e90e55804 100644
--- a/esp32s2/src/syscon/spi_mem_reject_addr.rs
+++ b/esp32s2/src/syscon/spi_mem_reject_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_MEM_REJECT_ADDR")
-            .field(
-                "spi_mem_reject_addr",
-                &format_args!("{}", self.spi_mem_reject_addr().bits()),
-            )
+            .field("spi_mem_reject_addr", &self.spi_mem_reject_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_MEM_REJECT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_reject_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_MEM_REJECT_ADDR_SPEC;
 impl crate::RegisterSpec for SPI_MEM_REJECT_ADDR_SPEC {
diff --git a/esp32s2/src/syscon/sram_ace0_addr.rs b/esp32s2/src/syscon/sram_ace0_addr.rs
index 2b0bcb8807..2695b39e90 100644
--- a/esp32s2/src/syscon/sram_ace0_addr.rs
+++ b/esp32s2/src/syscon/sram_ace0_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE0_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/sram_ace0_attr.rs b/esp32s2/src/syscon/sram_ace0_attr.rs
index 55c37e8e54..456a7ecd9f 100644
--- a/esp32s2/src/syscon/sram_ace0_attr.rs
+++ b/esp32s2/src/syscon/sram_ace0_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE0_ATTR")
-            .field(
-                "sram_ace0_attr",
-                &format_args!("{}", self.sram_ace0_attr().bits()),
-            )
+            .field("sram_ace0_attr", &self.sram_ace0_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE0_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/sram_ace0_size.rs b/esp32s2/src/syscon/sram_ace0_size.rs
index 64309a091a..95d148bc84 100644
--- a/esp32s2/src/syscon/sram_ace0_size.rs
+++ b/esp32s2/src/syscon/sram_ace0_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE0_SIZE")
-            .field(
-                "sram_ace0_size",
-                &format_args!("{}", self.sram_ace0_size().bits()),
-            )
+            .field("sram_ace0_size", &self.sram_ace0_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/sram_ace1_addr.rs b/esp32s2/src/syscon/sram_ace1_addr.rs
index 8558dd5f90..d23f94bac0 100644
--- a/esp32s2/src/syscon/sram_ace1_addr.rs
+++ b/esp32s2/src/syscon/sram_ace1_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE1_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/sram_ace1_attr.rs b/esp32s2/src/syscon/sram_ace1_attr.rs
index 85ea3bbe08..20aa097432 100644
--- a/esp32s2/src/syscon/sram_ace1_attr.rs
+++ b/esp32s2/src/syscon/sram_ace1_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE1_ATTR")
-            .field(
-                "sram_ace1_attr",
-                &format_args!("{}", self.sram_ace1_attr().bits()),
-            )
+            .field("sram_ace1_attr", &self.sram_ace1_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE1_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/sram_ace1_size.rs b/esp32s2/src/syscon/sram_ace1_size.rs
index 84f16ffc7c..e6cbb29779 100644
--- a/esp32s2/src/syscon/sram_ace1_size.rs
+++ b/esp32s2/src/syscon/sram_ace1_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE1_SIZE")
-            .field(
-                "sram_ace1_size",
-                &format_args!("{}", self.sram_ace1_size().bits()),
-            )
+            .field("sram_ace1_size", &self.sram_ace1_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/sram_ace2_addr.rs b/esp32s2/src/syscon/sram_ace2_addr.rs
index 74f394ff39..fb45ea3457 100644
--- a/esp32s2/src/syscon/sram_ace2_addr.rs
+++ b/esp32s2/src/syscon/sram_ace2_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE2_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/sram_ace2_attr.rs b/esp32s2/src/syscon/sram_ace2_attr.rs
index 28d9f68d7e..fd43a3268d 100644
--- a/esp32s2/src/syscon/sram_ace2_attr.rs
+++ b/esp32s2/src/syscon/sram_ace2_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE2_ATTR")
-            .field(
-                "sram_ace2_attr",
-                &format_args!("{}", self.sram_ace2_attr().bits()),
-            )
+            .field("sram_ace2_attr", &self.sram_ace2_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE2_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/sram_ace2_size.rs b/esp32s2/src/syscon/sram_ace2_size.rs
index da8e094a9f..a4becf7a57 100644
--- a/esp32s2/src/syscon/sram_ace2_size.rs
+++ b/esp32s2/src/syscon/sram_ace2_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE2_SIZE")
-            .field(
-                "sram_ace2_size",
-                &format_args!("{}", self.sram_ace2_size().bits()),
-            )
+            .field("sram_ace2_size", &self.sram_ace2_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE2_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/sram_ace3_addr.rs b/esp32s2/src/syscon/sram_ace3_addr.rs
index b26b259617..61fbf98f43 100644
--- a/esp32s2/src/syscon/sram_ace3_addr.rs
+++ b/esp32s2/src/syscon/sram_ace3_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE3_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/sram_ace3_attr.rs b/esp32s2/src/syscon/sram_ace3_attr.rs
index 363c0b7281..1863347639 100644
--- a/esp32s2/src/syscon/sram_ace3_attr.rs
+++ b/esp32s2/src/syscon/sram_ace3_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE3_ATTR")
-            .field(
-                "sram_ace3_attr",
-                &format_args!("{}", self.sram_ace3_attr().bits()),
-            )
+            .field("sram_ace3_attr", &self.sram_ace3_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE3_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/sram_ace3_size.rs b/esp32s2/src/syscon/sram_ace3_size.rs
index 5dc096571b..557605c7dd 100644
--- a/esp32s2/src/syscon/sram_ace3_size.rs
+++ b/esp32s2/src/syscon/sram_ace3_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE3_SIZE")
-            .field(
-                "sram_ace3_size",
-                &format_args!("{}", self.sram_ace3_size().bits()),
-            )
+            .field("sram_ace3_size", &self.sram_ace3_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE3_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/sysclk_conf.rs b/esp32s2/src/syscon/sysclk_conf.rs
index 6230ee2046..ec1618f94a 100644
--- a/esp32s2/src/syscon/sysclk_conf.rs
+++ b/esp32s2/src/syscon/sysclk_conf.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSCLK_CONF")
-            .field("clk_320m_en", &format_args!("{}", self.clk_320m_en().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "rst_tick_cnt",
-                &format_args!("{}", self.rst_tick_cnt().bit()),
-            )
+            .field("clk_320m_en", &self.clk_320m_en())
+            .field("clk_en", &self.clk_en())
+            .field("rst_tick_cnt", &self.rst_tick_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 10"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/tick_conf.rs b/esp32s2/src/syscon/tick_conf.rs
index 6a80ebc95a..568db81f99 100644
--- a/esp32s2/src/syscon/tick_conf.rs
+++ b/esp32s2/src/syscon/tick_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TICK_CONF")
-            .field(
-                "xtal_tick_num",
-                &format_args!("{}", self.xtal_tick_num().bits()),
-            )
-            .field(
-                "ck8m_tick_num",
-                &format_args!("{}", self.ck8m_tick_num().bits()),
-            )
-            .field("tick_enable", &format_args!("{}", self.tick_enable().bit()))
+            .field("xtal_tick_num", &self.xtal_tick_num())
+            .field("ck8m_tick_num", &self.ck8m_tick_num())
+            .field("tick_enable", &self.tick_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TICK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/wifi_bb_cfg.rs b/esp32s2/src/syscon/wifi_bb_cfg.rs
index add5c8d9d1..484f9dd15b 100644
--- a/esp32s2/src/syscon/wifi_bb_cfg.rs
+++ b/esp32s2/src/syscon/wifi_bb_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_BB_CFG")
-            .field(
-                "wifi_bb_cfg",
-                &format_args!("{}", self.wifi_bb_cfg().bits()),
-            )
+            .field("wifi_bb_cfg", &self.wifi_bb_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_BB_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/wifi_bb_cfg_2.rs b/esp32s2/src/syscon/wifi_bb_cfg_2.rs
index f70cd5bd14..64cb926b9b 100644
--- a/esp32s2/src/syscon/wifi_bb_cfg_2.rs
+++ b/esp32s2/src/syscon/wifi_bb_cfg_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_BB_CFG_2")
-            .field(
-                "wifi_bb_cfg_2",
-                &format_args!("{}", self.wifi_bb_cfg_2().bits()),
-            )
+            .field("wifi_bb_cfg_2", &self.wifi_bb_cfg_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_BB_CFG_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/wifi_clk_en.rs b/esp32s2/src/syscon/wifi_clk_en.rs
index 2da4ea3a58..2331429256 100644
--- a/esp32s2/src/syscon/wifi_clk_en.rs
+++ b/esp32s2/src/syscon/wifi_clk_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_CLK_EN")
-            .field(
-                "wifi_clk_en",
-                &format_args!("{}", self.wifi_clk_en().bits()),
-            )
+            .field("wifi_clk_en", &self.wifi_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/syscon/wifi_rst_en.rs b/esp32s2/src/syscon/wifi_rst_en.rs
index 7d96e8b3f9..3117f1aa37 100644
--- a/esp32s2/src/syscon/wifi_rst_en.rs
+++ b/esp32s2/src/syscon/wifi_rst_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_RST_EN")
-            .field("wifi_rst", &format_args!("{}", self.wifi_rst().bits()))
+            .field("wifi_rst", &self.wifi_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_RST_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/system/bt_lpck_div_frac.rs b/esp32s2/src/system/bt_lpck_div_frac.rs
index 08c4d8d552..7fbd2b602f 100644
--- a/esp32s2/src/system/bt_lpck_div_frac.rs
+++ b/esp32s2/src/system/bt_lpck_div_frac.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_LPCK_DIV_FRAC")
-            .field(
-                "lpclk_sel_rtc_slow",
-                &format_args!("{}", self.lpclk_sel_rtc_slow().bit()),
-            )
-            .field(
-                "lpclk_sel_8m",
-                &format_args!("{}", self.lpclk_sel_8m().bit()),
-            )
-            .field(
-                "lpclk_sel_xtal",
-                &format_args!("{}", self.lpclk_sel_xtal().bit()),
-            )
-            .field(
-                "lpclk_sel_xtal32k",
-                &format_args!("{}", self.lpclk_sel_xtal32k().bit()),
-            )
-            .field(
-                "lpclk_rtc_en",
-                &format_args!("{}", self.lpclk_rtc_en().bit()),
-            )
+            .field("lpclk_sel_rtc_slow", &self.lpclk_sel_rtc_slow())
+            .field("lpclk_sel_8m", &self.lpclk_sel_8m())
+            .field("lpclk_sel_xtal", &self.lpclk_sel_xtal())
+            .field("lpclk_sel_xtal32k", &self.lpclk_sel_xtal32k())
+            .field("lpclk_rtc_en", &self.lpclk_rtc_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_LPCK_DIV_FRAC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 24 - Set this bit to select RTC slow clock as the low power clock."]
     #[inline(always)]
diff --git a/esp32s2/src/system/bustoextmem_ena.rs b/esp32s2/src/system/bustoextmem_ena.rs
index 0c97ab2c2a..ef457d6793 100644
--- a/esp32s2/src/system/bustoextmem_ena.rs
+++ b/esp32s2/src/system/bustoextmem_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUSTOEXTMEM_ENA")
-            .field(
-                "bustoextmem_ena",
-                &format_args!("{}", self.bustoextmem_ena().bit()),
-            )
+            .field("bustoextmem_ena", &self.bustoextmem_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUSTOEXTMEM_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable bus to EDMA."]
     #[inline(always)]
diff --git a/esp32s2/src/system/cache_control.rs b/esp32s2/src/system/cache_control.rs
index 2d868845d3..aa98e434ba 100644
--- a/esp32s2/src/system/cache_control.rs
+++ b/esp32s2/src/system/cache_control.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_CONTROL")
-            .field(
-                "pro_icache_clk_on",
-                &format_args!("{}", self.pro_icache_clk_on().bit()),
-            )
-            .field(
-                "pro_dcache_clk_on",
-                &format_args!("{}", self.pro_dcache_clk_on().bit()),
-            )
-            .field(
-                "pro_cache_reset",
-                &format_args!("{}", self.pro_cache_reset().bit()),
-            )
+            .field("pro_icache_clk_on", &self.pro_icache_clk_on())
+            .field("pro_dcache_clk_on", &self.pro_dcache_clk_on())
+            .field("pro_cache_reset", &self.pro_cache_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable clock of i-cache."]
     #[inline(always)]
diff --git a/esp32s2/src/system/clock_gate.rs b/esp32s2/src/system/clock_gate.rs
index c1034b1eb0..35bb503ccc 100644
--- a/esp32s2/src/system/clock_gate.rs
+++ b/esp32s2/src/system/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable clock of this module."]
     #[inline(always)]
diff --git a/esp32s2/src/system/cpu_intr_from_cpu_0.rs b/esp32s2/src/system/cpu_intr_from_cpu_0.rs
index ecef4248a6..80afd8259f 100644
--- a/esp32s2/src/system/cpu_intr_from_cpu_0.rs
+++ b/esp32s2/src/system/cpu_intr_from_cpu_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_0")
-            .field(
-                "cpu_intr_from_cpu_0",
-                &format_args!("{}", self.cpu_intr_from_cpu_0().bit()),
-            )
+            .field("cpu_intr_from_cpu_0", &self.cpu_intr_from_cpu_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to generate CPU interrupt 0. This bit needs to be reset by software in the ISR process."]
     #[inline(always)]
diff --git a/esp32s2/src/system/cpu_intr_from_cpu_1.rs b/esp32s2/src/system/cpu_intr_from_cpu_1.rs
index a23fbc146e..c0f24618ac 100644
--- a/esp32s2/src/system/cpu_intr_from_cpu_1.rs
+++ b/esp32s2/src/system/cpu_intr_from_cpu_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_1")
-            .field(
-                "cpu_intr_from_cpu_1",
-                &format_args!("{}", self.cpu_intr_from_cpu_1().bit()),
-            )
+            .field("cpu_intr_from_cpu_1", &self.cpu_intr_from_cpu_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to generate CPU interrupt 1. This bit needs to be reset by software in the ISR process."]
     #[inline(always)]
diff --git a/esp32s2/src/system/cpu_intr_from_cpu_2.rs b/esp32s2/src/system/cpu_intr_from_cpu_2.rs
index 90ef395207..b5e7c6c79e 100644
--- a/esp32s2/src/system/cpu_intr_from_cpu_2.rs
+++ b/esp32s2/src/system/cpu_intr_from_cpu_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_2")
-            .field(
-                "cpu_intr_from_cpu_2",
-                &format_args!("{}", self.cpu_intr_from_cpu_2().bit()),
-            )
+            .field("cpu_intr_from_cpu_2", &self.cpu_intr_from_cpu_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to generate CPU interrupt 2. This bit needs to be reset by software in the ISR process."]
     #[inline(always)]
diff --git a/esp32s2/src/system/cpu_intr_from_cpu_3.rs b/esp32s2/src/system/cpu_intr_from_cpu_3.rs
index c0137014cf..a32044ce68 100644
--- a/esp32s2/src/system/cpu_intr_from_cpu_3.rs
+++ b/esp32s2/src/system/cpu_intr_from_cpu_3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_3")
-            .field(
-                "cpu_intr_from_cpu_3",
-                &format_args!("{}", self.cpu_intr_from_cpu_3().bit()),
-            )
+            .field("cpu_intr_from_cpu_3", &self.cpu_intr_from_cpu_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to generate CPU interrupt 3. This bit needs to be reset by software in the ISR process."]
     #[inline(always)]
diff --git a/esp32s2/src/system/cpu_per_conf.rs b/esp32s2/src/system/cpu_per_conf.rs
index 072879212b..bbf93e8bcc 100644
--- a/esp32s2/src/system/cpu_per_conf.rs
+++ b/esp32s2/src/system/cpu_per_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PER_CONF")
-            .field(
-                "cpuperiod_sel",
-                &format_args!("{}", self.cpuperiod_sel().bits()),
-            )
-            .field(
-                "pll_freq_sel",
-                &format_args!("{}", self.pll_freq_sel().bit()),
-            )
-            .field(
-                "cpu_wait_mode_force_on",
-                &format_args!("{}", self.cpu_wait_mode_force_on().bit()),
-            )
-            .field(
-                "cpu_waiti_delay_num",
-                &format_args!("{}", self.cpu_waiti_delay_num().bits()),
-            )
+            .field("cpuperiod_sel", &self.cpuperiod_sel())
+            .field("pll_freq_sel", &self.pll_freq_sel())
+            .field("cpu_wait_mode_force_on", &self.cpu_wait_mode_force_on())
+            .field("cpu_waiti_delay_num", &self.cpu_waiti_delay_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PER_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to select the clock frequency of CPU or CPU period."]
     #[inline(always)]
diff --git a/esp32s2/src/system/cpu_peri_clk_en.rs b/esp32s2/src/system/cpu_peri_clk_en.rs
index 586d16e0d1..e33e446bf5 100644
--- a/esp32s2/src/system/cpu_peri_clk_en.rs
+++ b/esp32s2/src/system/cpu_peri_clk_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERI_CLK_EN")
-            .field(
-                "clk_en_dedicated_gpio",
-                &format_args!("{}", self.clk_en_dedicated_gpio().bit()),
-            )
+            .field("clk_en_dedicated_gpio", &self.clk_en_dedicated_gpio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - Set this bit to enable clock of DEDICATED GPIO module."]
     #[inline(always)]
diff --git a/esp32s2/src/system/cpu_peri_rst_en.rs b/esp32s2/src/system/cpu_peri_rst_en.rs
index 5d81fdafca..a643a44a52 100644
--- a/esp32s2/src/system/cpu_peri_rst_en.rs
+++ b/esp32s2/src/system/cpu_peri_rst_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERI_RST_EN")
-            .field(
-                "rst_en_dedicated_gpio",
-                &format_args!("{}", self.rst_en_dedicated_gpio().bit()),
-            )
+            .field("rst_en_dedicated_gpio", &self.rst_en_dedicated_gpio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_RST_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - Set this bit to reset DEDICATED GPIO module."]
     #[inline(always)]
diff --git a/esp32s2/src/system/date.rs b/esp32s2/src/system/date.rs
index 7d9f4a745a..3c8558803e 100644
--- a/esp32s2/src/system/date.rs
+++ b/esp32s2/src/system/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/system/external_device_encrypt_decrypt_control.rs b/esp32s2/src/system/external_device_encrypt_decrypt_control.rs
index ed385d90c1..29283d6ff4 100644
--- a/esp32s2/src/system/external_device_encrypt_decrypt_control.rs
+++ b/esp32s2/src/system/external_device_encrypt_decrypt_control.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL")
             .field(
                 "enable_spi_manual_encrypt",
-                &format_args!("{}", self.enable_spi_manual_encrypt().bit()),
+                &self.enable_spi_manual_encrypt(),
             )
             .field(
                 "enable_download_db_encrypt",
-                &format_args!("{}", self.enable_download_db_encrypt().bit()),
+                &self.enable_download_db_encrypt(),
             )
             .field(
                 "enable_download_g0cb_decrypt",
-                &format_args!("{}", self.enable_download_g0cb_decrypt().bit()),
+                &self.enable_download_g0cb_decrypt(),
             )
             .field(
                 "enable_download_manual_encrypt",
-                &format_args!("{}", self.enable_download_manual_encrypt().bit()),
+                &self.enable_download_manual_encrypt(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable Manual Encryption under SPI Boot mode."]
     #[inline(always)]
diff --git a/esp32s2/src/system/lpck_div_int.rs b/esp32s2/src/system/lpck_div_int.rs
index d5be660363..92d897d980 100644
--- a/esp32s2/src/system/lpck_div_int.rs
+++ b/esp32s2/src/system/lpck_div_int.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LPCK_DIV_INT")
-            .field(
-                "lpck_div_num",
-                &format_args!("{}", self.lpck_div_num().bits()),
-            )
+            .field("lpck_div_num", &self.lpck_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LPCK_DIV_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - This field is used to set the integer number of the divider value."]
     #[inline(always)]
diff --git a/esp32s2/src/system/mem_pd_mask.rs b/esp32s2/src/system/mem_pd_mask.rs
index d9fc80a55e..a7f54d2246 100644
--- a/esp32s2/src/system/mem_pd_mask.rs
+++ b/esp32s2/src/system/mem_pd_mask.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_PD_MASK")
-            .field(
-                "lslp_mem_pd_mask",
-                &format_args!("{}", self.lslp_mem_pd_mask().bit()),
-            )
+            .field("lslp_mem_pd_mask", &self.lslp_mem_pd_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_PD_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to allow the memory to work as usual when the chip enters the light-sleep state."]
     #[inline(always)]
diff --git a/esp32s2/src/system/perip_clk_en0.rs b/esp32s2/src/system/perip_clk_en0.rs
index 643fa24761..e05fa2eef8 100644
--- a/esp32s2/src/system/perip_clk_en0.rs
+++ b/esp32s2/src/system/perip_clk_en0.rs
@@ -296,95 +296,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_CLK_EN0")
-            .field(
-                "timers_clk_en",
-                &format_args!("{}", self.timers_clk_en().bit()),
-            )
-            .field(
-                "spi01_clk_en",
-                &format_args!("{}", self.spi01_clk_en().bit()),
-            )
-            .field("uart_clk_en", &format_args!("{}", self.uart_clk_en().bit()))
-            .field("wdg_clk_en", &format_args!("{}", self.wdg_clk_en().bit()))
-            .field("i2s0_clk_en", &format_args!("{}", self.i2s0_clk_en().bit()))
-            .field(
-                "uart1_clk_en",
-                &format_args!("{}", self.uart1_clk_en().bit()),
-            )
-            .field("spi2_clk_en", &format_args!("{}", self.spi2_clk_en().bit()))
-            .field(
-                "i2c_ext0_clk_en",
-                &format_args!("{}", self.i2c_ext0_clk_en().bit()),
-            )
-            .field(
-                "uhci0_clk_en",
-                &format_args!("{}", self.uhci0_clk_en().bit()),
-            )
-            .field("rmt_clk_en", &format_args!("{}", self.rmt_clk_en().bit()))
-            .field("pcnt_clk_en", &format_args!("{}", self.pcnt_clk_en().bit()))
-            .field("ledc_clk_en", &format_args!("{}", self.ledc_clk_en().bit()))
-            .field(
-                "uhci1_clk_en",
-                &format_args!("{}", self.uhci1_clk_en().bit()),
-            )
-            .field(
-                "timergroup_clk_en",
-                &format_args!("{}", self.timergroup_clk_en().bit()),
-            )
-            .field(
-                "efuse_clk_en",
-                &format_args!("{}", self.efuse_clk_en().bit()),
-            )
-            .field(
-                "timergroup1_clk_en",
-                &format_args!("{}", self.timergroup1_clk_en().bit()),
-            )
-            .field("spi3_clk_en", &format_args!("{}", self.spi3_clk_en().bit()))
-            .field("pwm0_clk_en", &format_args!("{}", self.pwm0_clk_en().bit()))
-            .field(
-                "i2c_ext1_clk_en",
-                &format_args!("{}", self.i2c_ext1_clk_en().bit()),
-            )
-            .field("twai_clk_en", &format_args!("{}", self.twai_clk_en().bit()))
-            .field("pwm1_clk_en", &format_args!("{}", self.pwm1_clk_en().bit()))
-            .field("i2s1_clk_en", &format_args!("{}", self.i2s1_clk_en().bit()))
-            .field(
-                "spi2_dma_clk_en",
-                &format_args!("{}", self.spi2_dma_clk_en().bit()),
-            )
-            .field("usb_clk_en", &format_args!("{}", self.usb_clk_en().bit()))
-            .field(
-                "uart_mem_clk_en",
-                &format_args!("{}", self.uart_mem_clk_en().bit()),
-            )
-            .field("pwm2_clk_en", &format_args!("{}", self.pwm2_clk_en().bit()))
-            .field("pwm3_clk_en", &format_args!("{}", self.pwm3_clk_en().bit()))
-            .field(
-                "spi3_dma_clk_en",
-                &format_args!("{}", self.spi3_dma_clk_en().bit()),
-            )
-            .field(
-                "apb_saradc_clk_en",
-                &format_args!("{}", self.apb_saradc_clk_en().bit()),
-            )
-            .field(
-                "systimer_clk_en",
-                &format_args!("{}", self.systimer_clk_en().bit()),
-            )
-            .field(
-                "adc2_arb_clk_en",
-                &format_args!("{}", self.adc2_arb_clk_en().bit()),
-            )
-            .field("spi4_clk_en", &format_args!("{}", self.spi4_clk_en().bit()))
+            .field("timers_clk_en", &self.timers_clk_en())
+            .field("spi01_clk_en", &self.spi01_clk_en())
+            .field("uart_clk_en", &self.uart_clk_en())
+            .field("wdg_clk_en", &self.wdg_clk_en())
+            .field("i2s0_clk_en", &self.i2s0_clk_en())
+            .field("uart1_clk_en", &self.uart1_clk_en())
+            .field("spi2_clk_en", &self.spi2_clk_en())
+            .field("i2c_ext0_clk_en", &self.i2c_ext0_clk_en())
+            .field("uhci0_clk_en", &self.uhci0_clk_en())
+            .field("rmt_clk_en", &self.rmt_clk_en())
+            .field("pcnt_clk_en", &self.pcnt_clk_en())
+            .field("ledc_clk_en", &self.ledc_clk_en())
+            .field("uhci1_clk_en", &self.uhci1_clk_en())
+            .field("timergroup_clk_en", &self.timergroup_clk_en())
+            .field("efuse_clk_en", &self.efuse_clk_en())
+            .field("timergroup1_clk_en", &self.timergroup1_clk_en())
+            .field("spi3_clk_en", &self.spi3_clk_en())
+            .field("pwm0_clk_en", &self.pwm0_clk_en())
+            .field("i2c_ext1_clk_en", &self.i2c_ext1_clk_en())
+            .field("twai_clk_en", &self.twai_clk_en())
+            .field("pwm1_clk_en", &self.pwm1_clk_en())
+            .field("i2s1_clk_en", &self.i2s1_clk_en())
+            .field("spi2_dma_clk_en", &self.spi2_dma_clk_en())
+            .field("usb_clk_en", &self.usb_clk_en())
+            .field("uart_mem_clk_en", &self.uart_mem_clk_en())
+            .field("pwm2_clk_en", &self.pwm2_clk_en())
+            .field("pwm3_clk_en", &self.pwm3_clk_en())
+            .field("spi3_dma_clk_en", &self.spi3_dma_clk_en())
+            .field("apb_saradc_clk_en", &self.apb_saradc_clk_en())
+            .field("systimer_clk_en", &self.systimer_clk_en())
+            .field("adc2_arb_clk_en", &self.adc2_arb_clk_en())
+            .field("spi4_clk_en", &self.spi4_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_CLK_EN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable clock of timers."]
     #[inline(always)]
diff --git a/esp32s2/src/system/perip_clk_en1.rs b/esp32s2/src/system/perip_clk_en1.rs
index 39df87e122..f2a6e87697 100644
--- a/esp32s2/src/system/perip_clk_en1.rs
+++ b/esp32s2/src/system/perip_clk_en1.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_CLK_EN1")
-            .field(
-                "crypto_aes_clk_en",
-                &format_args!("{}", self.crypto_aes_clk_en().bit()),
-            )
-            .field(
-                "crypto_sha_clk_en",
-                &format_args!("{}", self.crypto_sha_clk_en().bit()),
-            )
-            .field(
-                "crypto_rsa_clk_en",
-                &format_args!("{}", self.crypto_rsa_clk_en().bit()),
-            )
-            .field(
-                "crypto_ds_clk_en",
-                &format_args!("{}", self.crypto_ds_clk_en().bit()),
-            )
-            .field(
-                "crypto_hmac_clk_en",
-                &format_args!("{}", self.crypto_hmac_clk_en().bit()),
-            )
-            .field(
-                "crypto_dma_clk_en",
-                &format_args!("{}", self.crypto_dma_clk_en().bit()),
-            )
+            .field("crypto_aes_clk_en", &self.crypto_aes_clk_en())
+            .field("crypto_sha_clk_en", &self.crypto_sha_clk_en())
+            .field("crypto_rsa_clk_en", &self.crypto_rsa_clk_en())
+            .field("crypto_ds_clk_en", &self.crypto_ds_clk_en())
+            .field("crypto_hmac_clk_en", &self.crypto_hmac_clk_en())
+            .field("crypto_dma_clk_en", &self.crypto_dma_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_CLK_EN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set this bit to enable clock of cryptography AES."]
     #[inline(always)]
diff --git a/esp32s2/src/system/perip_rst_en0.rs b/esp32s2/src/system/perip_rst_en0.rs
index 004bbe2ee6..90ddd87cdc 100644
--- a/esp32s2/src/system/perip_rst_en0.rs
+++ b/esp32s2/src/system/perip_rst_en0.rs
@@ -296,77 +296,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_RST_EN0")
-            .field("timers_rst", &format_args!("{}", self.timers_rst().bit()))
-            .field("spi01_rst", &format_args!("{}", self.spi01_rst().bit()))
-            .field("uart_rst", &format_args!("{}", self.uart_rst().bit()))
-            .field("wdg_rst", &format_args!("{}", self.wdg_rst().bit()))
-            .field("i2s0_rst", &format_args!("{}", self.i2s0_rst().bit()))
-            .field("uart1_rst", &format_args!("{}", self.uart1_rst().bit()))
-            .field("spi2_rst", &format_args!("{}", self.spi2_rst().bit()))
-            .field(
-                "i2c_ext0_rst",
-                &format_args!("{}", self.i2c_ext0_rst().bit()),
-            )
-            .field("uhci0_rst", &format_args!("{}", self.uhci0_rst().bit()))
-            .field("rmt_rst", &format_args!("{}", self.rmt_rst().bit()))
-            .field("pcnt_rst", &format_args!("{}", self.pcnt_rst().bit()))
-            .field("ledc_rst", &format_args!("{}", self.ledc_rst().bit()))
-            .field("uhci1_rst", &format_args!("{}", self.uhci1_rst().bit()))
-            .field(
-                "timergroup_rst",
-                &format_args!("{}", self.timergroup_rst().bit()),
-            )
-            .field("efuse_rst", &format_args!("{}", self.efuse_rst().bit()))
-            .field(
-                "timergroup1_rst",
-                &format_args!("{}", self.timergroup1_rst().bit()),
-            )
-            .field("spi3_rst", &format_args!("{}", self.spi3_rst().bit()))
-            .field("pwm0_rst", &format_args!("{}", self.pwm0_rst().bit()))
-            .field(
-                "i2c_ext1_rst",
-                &format_args!("{}", self.i2c_ext1_rst().bit()),
-            )
-            .field("twai_rst", &format_args!("{}", self.twai_rst().bit()))
-            .field("pwm1_rst", &format_args!("{}", self.pwm1_rst().bit()))
-            .field("i2s1_rst", &format_args!("{}", self.i2s1_rst().bit()))
-            .field(
-                "spi2_dma_rst",
-                &format_args!("{}", self.spi2_dma_rst().bit()),
-            )
-            .field("usb_rst", &format_args!("{}", self.usb_rst().bit()))
-            .field(
-                "uart_mem_rst",
-                &format_args!("{}", self.uart_mem_rst().bit()),
-            )
-            .field("pwm2_rst", &format_args!("{}", self.pwm2_rst().bit()))
-            .field("pwm3_rst", &format_args!("{}", self.pwm3_rst().bit()))
-            .field(
-                "spi3_dma_rst",
-                &format_args!("{}", self.spi3_dma_rst().bit()),
-            )
-            .field(
-                "apb_saradc_rst",
-                &format_args!("{}", self.apb_saradc_rst().bit()),
-            )
-            .field(
-                "systimer_rst",
-                &format_args!("{}", self.systimer_rst().bit()),
-            )
-            .field(
-                "adc2_arb_rst",
-                &format_args!("{}", self.adc2_arb_rst().bit()),
-            )
-            .field("spi4_rst", &format_args!("{}", self.spi4_rst().bit()))
+            .field("timers_rst", &self.timers_rst())
+            .field("spi01_rst", &self.spi01_rst())
+            .field("uart_rst", &self.uart_rst())
+            .field("wdg_rst", &self.wdg_rst())
+            .field("i2s0_rst", &self.i2s0_rst())
+            .field("uart1_rst", &self.uart1_rst())
+            .field("spi2_rst", &self.spi2_rst())
+            .field("i2c_ext0_rst", &self.i2c_ext0_rst())
+            .field("uhci0_rst", &self.uhci0_rst())
+            .field("rmt_rst", &self.rmt_rst())
+            .field("pcnt_rst", &self.pcnt_rst())
+            .field("ledc_rst", &self.ledc_rst())
+            .field("uhci1_rst", &self.uhci1_rst())
+            .field("timergroup_rst", &self.timergroup_rst())
+            .field("efuse_rst", &self.efuse_rst())
+            .field("timergroup1_rst", &self.timergroup1_rst())
+            .field("spi3_rst", &self.spi3_rst())
+            .field("pwm0_rst", &self.pwm0_rst())
+            .field("i2c_ext1_rst", &self.i2c_ext1_rst())
+            .field("twai_rst", &self.twai_rst())
+            .field("pwm1_rst", &self.pwm1_rst())
+            .field("i2s1_rst", &self.i2s1_rst())
+            .field("spi2_dma_rst", &self.spi2_dma_rst())
+            .field("usb_rst", &self.usb_rst())
+            .field("uart_mem_rst", &self.uart_mem_rst())
+            .field("pwm2_rst", &self.pwm2_rst())
+            .field("pwm3_rst", &self.pwm3_rst())
+            .field("spi3_dma_rst", &self.spi3_dma_rst())
+            .field("apb_saradc_rst", &self.apb_saradc_rst())
+            .field("systimer_rst", &self.systimer_rst())
+            .field("adc2_arb_rst", &self.adc2_arb_rst())
+            .field("spi4_rst", &self.spi4_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_RST_EN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset timers."]
     #[inline(always)]
diff --git a/esp32s2/src/system/perip_rst_en1.rs b/esp32s2/src/system/perip_rst_en1.rs
index 60068d099f..503e473c49 100644
--- a/esp32s2/src/system/perip_rst_en1.rs
+++ b/esp32s2/src/system/perip_rst_en1.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_RST_EN1")
-            .field(
-                "crypto_aes_rst",
-                &format_args!("{}", self.crypto_aes_rst().bit()),
-            )
-            .field(
-                "crypto_sha_rst",
-                &format_args!("{}", self.crypto_sha_rst().bit()),
-            )
-            .field(
-                "crypto_rsa_rst",
-                &format_args!("{}", self.crypto_rsa_rst().bit()),
-            )
-            .field(
-                "crypto_ds_rst",
-                &format_args!("{}", self.crypto_ds_rst().bit()),
-            )
-            .field(
-                "crypto_hmac_rst",
-                &format_args!("{}", self.crypto_hmac_rst().bit()),
-            )
-            .field(
-                "crypto_dma_rst",
-                &format_args!("{}", self.crypto_dma_rst().bit()),
-            )
+            .field("crypto_aes_rst", &self.crypto_aes_rst())
+            .field("crypto_sha_rst", &self.crypto_sha_rst())
+            .field("crypto_rsa_rst", &self.crypto_rsa_rst())
+            .field("crypto_ds_rst", &self.crypto_ds_rst())
+            .field("crypto_hmac_rst", &self.crypto_hmac_rst())
+            .field("crypto_dma_rst", &self.crypto_dma_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_RST_EN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set this bit to reset cryptography AES."]
     #[inline(always)]
diff --git a/esp32s2/src/system/redundant_eco_ctrl.rs b/esp32s2/src/system/redundant_eco_ctrl.rs
index e428fb2cbd..5835d58cc4 100644
--- a/esp32s2/src/system/redundant_eco_ctrl.rs
+++ b/esp32s2/src/system/redundant_eco_ctrl.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Redundant_ECO_Ctrl")
-            .field(
-                "redundant_eco_drive",
-                &format_args!("{}", self.redundant_eco_drive().bit()),
-            )
-            .field(
-                "redundant_eco_result",
-                &format_args!("{}", self.redundant_eco_result().bit()),
-            )
+            .field("redundant_eco_drive", &self.redundant_eco_drive())
+            .field("redundant_eco_result", &self.redundant_eco_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDUNDANT_ECO_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The redundant ECO drive bit to avoid optimization in circuits."]
     #[inline(always)]
diff --git a/esp32s2/src/system/rom_ctrl_0.rs b/esp32s2/src/system/rom_ctrl_0.rs
index 69c72c46a7..5e88fdb869 100644
--- a/esp32s2/src/system/rom_ctrl_0.rs
+++ b/esp32s2/src/system/rom_ctrl_0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_CTRL_0")
-            .field("rom_fo", &format_args!("{}", self.rom_fo().bits()))
+            .field("rom_fo", &self.rom_fo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_CTRL_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to force on clock gate of internal ROM."]
     #[inline(always)]
diff --git a/esp32s2/src/system/rom_ctrl_1.rs b/esp32s2/src/system/rom_ctrl_1.rs
index a6b6f77638..c99c20f63d 100644
--- a/esp32s2/src/system/rom_ctrl_1.rs
+++ b/esp32s2/src/system/rom_ctrl_1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ROM_CTRL_1")
-            .field(
-                "rom_force_pd",
-                &format_args!("{}", self.rom_force_pd().bits()),
-            )
-            .field(
-                "rom_force_pu",
-                &format_args!("{}", self.rom_force_pu().bits()),
-            )
+            .field("rom_force_pd", &self.rom_force_pd())
+            .field("rom_force_pu", &self.rom_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ROM_CTRL_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to power down internal ROM."]
     #[inline(always)]
diff --git a/esp32s2/src/system/rsa_pd_ctrl.rs b/esp32s2/src/system/rsa_pd_ctrl.rs
index beba5c991f..8c643a5f39 100644
--- a/esp32s2/src/system/rsa_pd_ctrl.rs
+++ b/esp32s2/src/system/rsa_pd_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_PD_CTRL")
-            .field("rsa_mem_pd", &format_args!("{}", self.rsa_mem_pd().bit()))
-            .field(
-                "rsa_mem_force_pu",
-                &format_args!("{}", self.rsa_mem_force_pu().bit()),
-            )
-            .field(
-                "rsa_mem_force_pd",
-                &format_args!("{}", self.rsa_mem_force_pd().bit()),
-            )
+            .field("rsa_mem_pd", &self.rsa_mem_pd())
+            .field("rsa_mem_force_pu", &self.rsa_mem_force_pu())
+            .field("rsa_mem_force_pd", &self.rsa_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to power down RSA memory. This bit has the lowest priority. When Digital Signature occupies the RSA, this bit is invalid."]
     #[inline(always)]
diff --git a/esp32s2/src/system/rtc_fastmem_config.rs b/esp32s2/src/system/rtc_fastmem_config.rs
index b3bd6badf6..4943059ce5 100644
--- a/esp32s2/src/system/rtc_fastmem_config.rs
+++ b/esp32s2/src/system/rtc_fastmem_config.rs
@@ -42,31 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_FASTMEM_CONFIG")
-            .field(
-                "rtc_mem_crc_start",
-                &format_args!("{}", self.rtc_mem_crc_start().bit()),
-            )
-            .field(
-                "rtc_mem_crc_addr",
-                &format_args!("{}", self.rtc_mem_crc_addr().bits()),
-            )
-            .field(
-                "rtc_mem_crc_len",
-                &format_args!("{}", self.rtc_mem_crc_len().bits()),
-            )
-            .field(
-                "rtc_mem_crc_finish",
-                &format_args!("{}", self.rtc_mem_crc_finish().bit()),
-            )
+            .field("rtc_mem_crc_start", &self.rtc_mem_crc_start())
+            .field("rtc_mem_crc_addr", &self.rtc_mem_crc_addr())
+            .field("rtc_mem_crc_len", &self.rtc_mem_crc_len())
+            .field("rtc_mem_crc_finish", &self.rtc_mem_crc_finish())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_FASTMEM_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - Set this bit to start the CRC of RTC memory."]
     #[inline(always)]
diff --git a/esp32s2/src/system/rtc_fastmem_crc.rs b/esp32s2/src/system/rtc_fastmem_crc.rs
index 6763877122..8236f5c833 100644
--- a/esp32s2/src/system/rtc_fastmem_crc.rs
+++ b/esp32s2/src/system/rtc_fastmem_crc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_FASTMEM_CRC")
-            .field(
-                "rtc_mem_crc_res",
-                &format_args!("{}", self.rtc_mem_crc_res().bits()),
-            )
+            .field("rtc_mem_crc_res", &self.rtc_mem_crc_res())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_FASTMEM_CRC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC fast memory CRC controlling register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_fastmem_crc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTC_FASTMEM_CRC_SPEC;
 impl crate::RegisterSpec for RTC_FASTMEM_CRC_SPEC {
diff --git a/esp32s2/src/system/sram_ctrl_0.rs b/esp32s2/src/system/sram_ctrl_0.rs
index 6dfe4daedf..2730b5be43 100644
--- a/esp32s2/src/system/sram_ctrl_0.rs
+++ b/esp32s2/src/system/sram_ctrl_0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_CTRL_0")
-            .field("sram_fo", &format_args!("{}", self.sram_fo().bits()))
+            .field("sram_fo", &self.sram_fo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_CTRL_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - This field is used to force on clock gate of internal SRAM."]
     #[inline(always)]
diff --git a/esp32s2/src/system/sram_ctrl_1.rs b/esp32s2/src/system/sram_ctrl_1.rs
index 4e1e4fca57..c01367a572 100644
--- a/esp32s2/src/system/sram_ctrl_1.rs
+++ b/esp32s2/src/system/sram_ctrl_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_CTRL_1")
-            .field(
-                "sram_force_pd",
-                &format_args!("{}", self.sram_force_pd().bits()),
-            )
+            .field("sram_force_pd", &self.sram_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_CTRL_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - This field is used to power down internal SRAM."]
     #[inline(always)]
diff --git a/esp32s2/src/system/sram_ctrl_2.rs b/esp32s2/src/system/sram_ctrl_2.rs
index a9baaa1d9d..4b6d2dcc9f 100644
--- a/esp32s2/src/system/sram_ctrl_2.rs
+++ b/esp32s2/src/system/sram_ctrl_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_CTRL_2")
-            .field(
-                "sram_force_pu",
-                &format_args!("{}", self.sram_force_pu().bits()),
-            )
+            .field("sram_force_pu", &self.sram_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_CTRL_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - This field is used to power up internal SRAM."]
     #[inline(always)]
diff --git a/esp32s2/src/system/sysclk_conf.rs b/esp32s2/src/system/sysclk_conf.rs
index 202fae9d9c..ff94172b86 100644
--- a/esp32s2/src/system/sysclk_conf.rs
+++ b/esp32s2/src/system/sysclk_conf.rs
@@ -40,28 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSCLK_CONF")
-            .field(
-                "pre_div_cnt",
-                &format_args!("{}", self.pre_div_cnt().bits()),
-            )
-            .field(
-                "soc_clk_sel",
-                &format_args!("{}", self.soc_clk_sel().bits()),
-            )
-            .field(
-                "clk_xtal_freq",
-                &format_args!("{}", self.clk_xtal_freq().bits()),
-            )
-            .field("clk_div_en", &format_args!("{}", self.clk_div_en().bit()))
+            .field("pre_div_cnt", &self.pre_div_cnt())
+            .field("soc_clk_sel", &self.soc_clk_sel())
+            .field("clk_xtal_freq", &self.clk_xtal_freq())
+            .field("clk_div_en", &self.clk_div_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This field is used to set the count of prescaler of XTAL\\_CLK."]
     #[inline(always)]
diff --git a/esp32s2/src/systimer/conf.rs b/esp32s2/src/systimer/conf.rs
index 7f07eb9732..de0d794f3c 100644
--- a/esp32s2/src/systimer/conf.rs
+++ b/esp32s2/src/systimer/conf.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("clk_fo", &format_args!("{}", self.clk_fo().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_fo", &self.clk_fo())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - System timer clock force enable."]
     #[inline(always)]
diff --git a/esp32s2/src/systimer/date.rs b/esp32s2/src/systimer/date.rs
index 089761b536..1468028606 100644
--- a/esp32s2/src/systimer/date.rs
+++ b/esp32s2/src/systimer/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/systimer/int_ena.rs b/esp32s2/src/systimer/int_ena.rs
index 1b1b8ed885..732360d717 100644
--- a/esp32s2/src/systimer/int_ena.rs
+++ b/esp32s2/src/systimer/int_ena.rs
@@ -42,18 +42,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Interrupt enable bit of system timer target (0-2)."]
     #[doc = ""]
diff --git a/esp32s2/src/systimer/int_raw.rs b/esp32s2/src/systimer/int_raw.rs
index a7fcedef22..4d75c337d8 100644
--- a/esp32s2/src/systimer/int_raw.rs
+++ b/esp32s2/src/systimer/int_raw.rs
@@ -38,18 +38,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "System timer interrupt raw\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s2/src/systimer/load_hi.rs b/esp32s2/src/systimer/load_hi.rs
index 511d5ff4aa..ff0ecf9394 100644
--- a/esp32s2/src/systimer/load_hi.rs
+++ b/esp32s2/src/systimer/load_hi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOAD_HI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOAD_HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The value to be loaded into system timer, high 32 bits."]
     #[inline(always)]
diff --git a/esp32s2/src/systimer/load_lo.rs b/esp32s2/src/systimer/load_lo.rs
index 94877419b8..3b486ae163 100644
--- a/esp32s2/src/systimer/load_lo.rs
+++ b/esp32s2/src/systimer/load_lo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOAD_LO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOAD_LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The value to be loaded into system timer, low 32 bits."]
     #[inline(always)]
diff --git a/esp32s2/src/systimer/step.rs b/esp32s2/src/systimer/step.rs
index 059ee500f4..8e647c1626 100644
--- a/esp32s2/src/systimer/step.rs
+++ b/esp32s2/src/systimer/step.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STEP")
-            .field("xtal_step", &format_args!("{}", self.xtal_step().bits()))
-            .field("pll_step", &format_args!("{}", self.pll_step().bits()))
+            .field("xtal_step", &self.xtal_step())
+            .field("pll_step", &self.pll_step())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STEP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - Set system timer increment step when using XTAL_CLK."]
     #[inline(always)]
diff --git a/esp32s2/src/systimer/target_conf.rs b/esp32s2/src/systimer/target_conf.rs
index 67bc519340..6a7eff8f79 100644
--- a/esp32s2/src/systimer/target_conf.rs
+++ b/esp32s2/src/systimer/target_conf.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TARGET_CONF")
-            .field("period", &format_args!("{}", self.period().bits()))
-            .field("period_mode", &format_args!("{}", self.period_mode().bit()))
-            .field("work_en", &format_args!("{}", self.work_en().bit()))
+            .field("period", &self.period())
+            .field("period_mode", &self.period_mode())
+            .field("work_en", &self.work_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TARGET_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Set alarm period for system timer target 0, only valid in periodic alarms mode."]
     #[inline(always)]
diff --git a/esp32s2/src/systimer/trgt/hi.rs b/esp32s2/src/systimer/trgt/hi.rs
index 277e4de94f..5455a8f4cf 100644
--- a/esp32s2/src/systimer/trgt/hi.rs
+++ b/esp32s2/src/systimer/trgt/hi.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/systimer/trgt/lo.rs b/esp32s2/src/systimer/trgt/lo.rs
index 43b5fc6545..43795c83c8 100644
--- a/esp32s2/src/systimer/trgt/lo.rs
+++ b/esp32s2/src/systimer/trgt/lo.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/systimer/unit_op.rs b/esp32s2/src/systimer/unit_op.rs
index 1404d54422..13e679e1b8 100644
--- a/esp32s2/src/systimer/unit_op.rs
+++ b/esp32s2/src/systimer/unit_op.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UNIT_OP")
-            .field("value_valid", &format_args!("{}", self.value_valid().bit()))
+            .field("value_valid", &self.value_valid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UNIT_OP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Update system timer value to registers."]
     #[inline(always)]
diff --git a/esp32s2/src/systimer/unit_value/hi.rs b/esp32s2/src/systimer/unit_value/hi.rs
index b6c2b1c6eb..fbe9025a65 100644
--- a/esp32s2/src/systimer/unit_value/hi.rs
+++ b/esp32s2/src/systimer/unit_value/hi.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HI")
-            .field("value_hi", &format_args!("{}", self.value_hi().bits()))
+            .field("value_hi", &self.value_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "System timer value, high 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HI_SPEC;
 impl crate::RegisterSpec for HI_SPEC {
diff --git a/esp32s2/src/systimer/unit_value/lo.rs b/esp32s2/src/systimer/unit_value/lo.rs
index c9f730edd9..501bcc8d17 100644
--- a/esp32s2/src/systimer/unit_value/lo.rs
+++ b/esp32s2/src/systimer/unit_value/lo.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LO")
-            .field("value_lo", &format_args!("{}", self.value_lo().bits()))
+            .field("value_lo", &self.value_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "System timer value, low 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LO_SPEC;
 impl crate::RegisterSpec for LO_SPEC {
diff --git a/esp32s2/src/timg0/int_ena_timers.rs b/esp32s2/src/timg0/int_ena_timers.rs
index 39c61772ef..c1ef6ccb2a 100644
--- a/esp32s2/src/timg0/int_ena_timers.rs
+++ b/esp32s2/src/timg0/int_ena_timers.rs
@@ -55,19 +55,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("t1", &format_args!("{}", self.t1().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("lact", &format_args!("{}", self.lact().bit()))
+            .field("t0", &self.t0())
+            .field("t1", &self.t1())
+            .field("wdt", &self.wdt())
+            .field("lact", &self.lact())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the TIMG_T(0-1)_INT interrupt."]
     #[doc = ""]
diff --git a/esp32s2/src/timg0/int_raw_timers.rs b/esp32s2/src/timg0/int_raw_timers.rs
index 006d1e255a..bc1acd2cfd 100644
--- a/esp32s2/src/timg0/int_raw_timers.rs
+++ b/esp32s2/src/timg0/int_raw_timers.rs
@@ -47,19 +47,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("t1", &format_args!("{}", self.t1().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("lact", &format_args!("{}", self.lact().bit()))
+            .field("t0", &self.t0())
+            .field("t1", &self.t1())
+            .field("wdt", &self.wdt())
+            .field("lact", &self.lact())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_TIMERS_SPEC;
 impl crate::RegisterSpec for INT_RAW_TIMERS_SPEC {
diff --git a/esp32s2/src/timg0/int_st_timers.rs b/esp32s2/src/timg0/int_st_timers.rs
index c11c4cf2d3..8ebb5b2b1e 100644
--- a/esp32s2/src/timg0/int_st_timers.rs
+++ b/esp32s2/src/timg0/int_st_timers.rs
@@ -47,19 +47,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("t1", &format_args!("{}", self.t1().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field("lact", &format_args!("{}", self.lact().bit()))
+            .field("t0", &self.t0())
+            .field("t1", &self.t1())
+            .field("wdt", &self.wdt())
+            .field("lact", &self.lact())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_TIMERS_SPEC;
 impl crate::RegisterSpec for INT_ST_TIMERS_SPEC {
diff --git a/esp32s2/src/timg0/lactalarmhi.rs b/esp32s2/src/timg0/lactalarmhi.rs
index 821310716b..0663a355bc 100644
--- a/esp32s2/src/timg0/lactalarmhi.rs
+++ b/esp32s2/src/timg0/lactalarmhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LACTALARMHI")
-            .field("alarm_hi", &format_args!("{}", self.alarm_hi().bits()))
+            .field("alarm_hi", &self.alarm_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTALARMHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/lactalarmlo.rs b/esp32s2/src/timg0/lactalarmlo.rs
index 55ec0b50c2..c123339aed 100644
--- a/esp32s2/src/timg0/lactalarmlo.rs
+++ b/esp32s2/src/timg0/lactalarmlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LACTALARMLO")
-            .field("alarm_lo", &format_args!("{}", self.alarm_lo().bits()))
+            .field("alarm_lo", &self.alarm_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTALARMLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/lactconfig.rs b/esp32s2/src/timg0/lactconfig.rs
index b05a9b6455..c0ab67115d 100644
--- a/esp32s2/src/timg0/lactconfig.rs
+++ b/esp32s2/src/timg0/lactconfig.rs
@@ -107,29 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LACTCONFIG")
-            .field("use_reftick", &format_args!("{}", self.use_reftick().bit()))
-            .field("rtc_only", &format_args!("{}", self.rtc_only().bit()))
-            .field("cpst_en", &format_args!("{}", self.cpst_en().bit()))
-            .field("lac_en", &format_args!("{}", self.lac_en().bit()))
-            .field("alarm_en", &format_args!("{}", self.alarm_en().bit()))
-            .field(
-                "level_int_en",
-                &format_args!("{}", self.level_int_en().bit()),
-            )
-            .field("edge_int_en", &format_args!("{}", self.edge_int_en().bit()))
-            .field("divider", &format_args!("{}", self.divider().bits()))
-            .field("autoreload", &format_args!("{}", self.autoreload().bit()))
-            .field("increase", &format_args!("{}", self.increase().bit()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("use_reftick", &self.use_reftick())
+            .field("rtc_only", &self.rtc_only())
+            .field("cpst_en", &self.cpst_en())
+            .field("lac_en", &self.lac_en())
+            .field("alarm_en", &self.alarm_en())
+            .field("level_int_en", &self.level_int_en())
+            .field("edge_int_en", &self.edge_int_en())
+            .field("divider", &self.divider())
+            .field("autoreload", &self.autoreload())
+            .field("increase", &self.increase())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTCONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - Reserved."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/lacthi.rs b/esp32s2/src/timg0/lacthi.rs
index 536b476a59..d0c076c15a 100644
--- a/esp32s2/src/timg0/lacthi.rs
+++ b/esp32s2/src/timg0/lacthi.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LACTHI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LACTHI").field("hi", &self.hi()).finish()
     }
 }
 #[doc = "LACT high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lacthi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s2/src/timg0/lactlo.rs b/esp32s2/src/timg0/lactlo.rs
index 1d497805c8..8464c16efd 100644
--- a/esp32s2/src/timg0/lactlo.rs
+++ b/esp32s2/src/timg0/lactlo.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LACTLO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LACTLO").field("lo", &self.lo()).finish()
     }
 }
 #[doc = "LACT low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lactlo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s2/src/timg0/lactloadhi.rs b/esp32s2/src/timg0/lactloadhi.rs
index 32d81fb290..ea6aee1e7d 100644
--- a/esp32s2/src/timg0/lactloadhi.rs
+++ b/esp32s2/src/timg0/lactloadhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LACTLOADHI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTLOADHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/lactloadlo.rs b/esp32s2/src/timg0/lactloadlo.rs
index 9e26264a79..0b19ea5ec4 100644
--- a/esp32s2/src/timg0/lactloadlo.rs
+++ b/esp32s2/src/timg0/lactloadlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LACTLOADLO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTLOADLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/lactrtc.rs b/esp32s2/src/timg0/lactrtc.rs
index eb7c5d043b..4a368fec37 100644
--- a/esp32s2/src/timg0/lactrtc.rs
+++ b/esp32s2/src/timg0/lactrtc.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LACTRTC")
-            .field(
-                "rtc_step_len",
-                &format_args!("{}", self.rtc_step_len().bits()),
-            )
+            .field("rtc_step_len", &self.rtc_step_len())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LACTRTC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 6:31 - Reserved."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/regclk.rs b/esp32s2/src/timg0/regclk.rs
index ffbebaea24..43b505222f 100644
--- a/esp32s2/src/timg0/regclk.rs
+++ b/esp32s2/src/timg0/regclk.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGCLK")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/rtccalicfg.rs b/esp32s2/src/timg0/rtccalicfg.rs
index 04f0f2da8b..e9be04c8b4 100644
--- a/esp32s2/src/timg0/rtccalicfg.rs
+++ b/esp32s2/src/timg0/rtccalicfg.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG")
-            .field(
-                "rtc_cali_start_cycling",
-                &format_args!("{}", self.rtc_cali_start_cycling().bit()),
-            )
-            .field(
-                "rtc_cali_clk_sel",
-                &format_args!("{}", self.rtc_cali_clk_sel().bits()),
-            )
-            .field(
-                "rtc_cali_rdy",
-                &format_args!("{}", self.rtc_cali_rdy().bit()),
-            )
-            .field(
-                "rtc_cali_max",
-                &format_args!("{}", self.rtc_cali_max().bits()),
-            )
-            .field(
-                "rtc_cali_start",
-                &format_args!("{}", self.rtc_cali_start().bit()),
-            )
+            .field("rtc_cali_start_cycling", &self.rtc_cali_start_cycling())
+            .field("rtc_cali_clk_sel", &self.rtc_cali_clk_sel())
+            .field("rtc_cali_rdy", &self.rtc_cali_rdy())
+            .field("rtc_cali_max", &self.rtc_cali_max())
+            .field("rtc_cali_start", &self.rtc_cali_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - When set, periodic calibration is enabled."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/rtccalicfg1.rs b/esp32s2/src/timg0/rtccalicfg1.rs
index 65b7a86015..f475b27d34 100644
--- a/esp32s2/src/timg0/rtccalicfg1.rs
+++ b/esp32s2/src/timg0/rtccalicfg1.rs
@@ -22,21 +22,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("RTCCALICFG1")
             .field(
                 "rtc_cali_cycling_data_vld",
-                &format_args!("{}", self.rtc_cali_cycling_data_vld().bit()),
-            )
-            .field(
-                "rtc_cali_value",
-                &format_args!("{}", self.rtc_cali_value().bits()),
+                &self.rtc_cali_cycling_data_vld(),
             )
+            .field("rtc_cali_value", &self.rtc_cali_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC calibration configuration register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtccalicfg1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTCCALICFG1_SPEC;
 impl crate::RegisterSpec for RTCCALICFG1_SPEC {
diff --git a/esp32s2/src/timg0/rtccalicfg2.rs b/esp32s2/src/timg0/rtccalicfg2.rs
index a0ea39a67b..2142857b29 100644
--- a/esp32s2/src/timg0/rtccalicfg2.rs
+++ b/esp32s2/src/timg0/rtccalicfg2.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG2")
-            .field(
-                "rtc_cali_timeout",
-                &format_args!("{}", self.rtc_cali_timeout().bit()),
-            )
-            .field(
-                "rtc_cali_timeout_rst_cnt",
-                &format_args!("{}", self.rtc_cali_timeout_rst_cnt().bits()),
-            )
-            .field(
-                "rtc_cali_timeout_thres",
-                &format_args!("{}", self.rtc_cali_timeout_thres().bits()),
-            )
+            .field("rtc_cali_timeout", &self.rtc_cali_timeout())
+            .field("rtc_cali_timeout_rst_cnt", &self.rtc_cali_timeout_rst_cnt())
+            .field("rtc_cali_timeout_thres", &self.rtc_cali_timeout_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:6 - Cycles that release calibration timeout reset"]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/t/alarmhi.rs b/esp32s2/src/timg0/t/alarmhi.rs
index 6cd815d11e..759bf33b04 100644
--- a/esp32s2/src/timg0/t/alarmhi.rs
+++ b/esp32s2/src/timg0/t/alarmhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMHI")
-            .field("alarm_hi", &format_args!("{}", self.alarm_hi().bits()))
+            .field("alarm_hi", &self.alarm_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Timer %s alarm trigger time-base counter value, high 32 bits."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/t/alarmlo.rs b/esp32s2/src/timg0/t/alarmlo.rs
index 7aaa51e9cb..d1f7b86948 100644
--- a/esp32s2/src/timg0/t/alarmlo.rs
+++ b/esp32s2/src/timg0/t/alarmlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMLO")
-            .field("alarm_lo", &format_args!("{}", self.alarm_lo().bits()))
+            .field("alarm_lo", &self.alarm_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Timer %s alarm trigger time-base counter value, low 32 bits."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/t/config.rs b/esp32s2/src/timg0/t/config.rs
index 7b32c3c0ad..f6c5afc542 100644
--- a/esp32s2/src/timg0/t/config.rs
+++ b/esp32s2/src/timg0/t/config.rs
@@ -80,26 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG")
-            .field("use_xtal", &format_args!("{}", self.use_xtal().bit()))
-            .field("alarm_en", &format_args!("{}", self.alarm_en().bit()))
-            .field(
-                "level_int_en",
-                &format_args!("{}", self.level_int_en().bit()),
-            )
-            .field("edge_int_en", &format_args!("{}", self.edge_int_en().bit()))
-            .field("divider", &format_args!("{}", self.divider().bits()))
-            .field("autoreload", &format_args!("{}", self.autoreload().bit()))
-            .field("increase", &format_args!("{}", self.increase().bit()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("use_xtal", &self.use_xtal())
+            .field("alarm_en", &self.alarm_en())
+            .field("level_int_en", &self.level_int_en())
+            .field("edge_int_en", &self.edge_int_en())
+            .field("divider", &self.divider())
+            .field("autoreload", &self.autoreload())
+            .field("increase", &self.increase())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/t/hi.rs b/esp32s2/src/timg0/t/hi.rs
index dcf7ea3833..719f5b0224 100644
--- a/esp32s2/src/timg0/t/hi.rs
+++ b/esp32s2/src/timg0/t/hi.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
     }
 }
 #[doc = "Timer 0 current value, high 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s2/src/timg0/t/lo.rs b/esp32s2/src/timg0/t/lo.rs
index 40c76cd3a1..a8846e3e83 100644
--- a/esp32s2/src/timg0/t/lo.rs
+++ b/esp32s2/src/timg0/t/lo.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
     }
 }
 #[doc = "Timer 0 current value, low 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s2/src/timg0/t/loadhi.rs b/esp32s2/src/timg0/t/loadhi.rs
index 8e771d3789..3ed74b7ab5 100644
--- a/esp32s2/src/timg0/t/loadhi.rs
+++ b/esp32s2/src/timg0/t/loadhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADHI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - High 32 bits of the value that a reload will load onto timer %s time-base counter."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/t/loadlo.rs b/esp32s2/src/timg0/t/loadlo.rs
index 64e4851686..9a2ec529f8 100644
--- a/esp32s2/src/timg0/t/loadlo.rs
+++ b/esp32s2/src/timg0/t/loadlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADLO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Low 32 bits of the value that a reload will load onto timer %s time-base counter."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/t/update.rs b/esp32s2/src/timg0/t/update.rs
index b3c28f79be..4b55d1d77d 100644
--- a/esp32s2/src/timg0/t/update.rs
+++ b/esp32s2/src/timg0/t/update.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE")
-            .field("update", &format_args!("{}", self.update().bit()))
+            .field("update", &self.update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/timers_date.rs b/esp32s2/src/timg0/timers_date.rs
index ff8fc8dedf..154c9f92c8 100644
--- a/esp32s2/src/timg0/timers_date.rs
+++ b/esp32s2/src/timg0/timers_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMERS_DATE")
-            .field(
-                "timers_date",
-                &format_args!("{}", self.timers_date().bits()),
-            )
+            .field("timers_date", &self.timers_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMERS_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/wdtconfig0.rs b/esp32s2/src/timg0/wdtconfig0.rs
index 046e754e21..7934b8c188 100644
--- a/esp32s2/src/timg0/wdtconfig0.rs
+++ b/esp32s2/src/timg0/wdtconfig0.rs
@@ -116,48 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG0")
-            .field(
-                "wdt_appcpu_reset_en",
-                &format_args!("{}", self.wdt_appcpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field(
-                "wdt_level_int_en",
-                &format_args!("{}", self.wdt_level_int_en().bit()),
-            )
-            .field(
-                "wdt_edge_int_en",
-                &format_args!("{}", self.wdt_edge_int_en().bit()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_level_int_en", &self.wdt_level_int_en())
+            .field("wdt_edge_int_en", &self.wdt_edge_int_en())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Reserved."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/wdtconfig1.rs b/esp32s2/src/timg0/wdtconfig1.rs
index 3aa68de08a..1a09586ed3 100644
--- a/esp32s2/src/timg0/wdtconfig1.rs
+++ b/esp32s2/src/timg0/wdtconfig1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG1")
-            .field(
-                "wdt_clk_prescale",
-                &format_args!("{}", self.wdt_clk_prescale().bits()),
-            )
+            .field("wdt_clk_prescale", &self.wdt_clk_prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - MWDT clock prescaler value. MWDT clock period = 12.5 ns * TIMG_WDT_CLK_PRESCALE."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/wdtconfig2.rs b/esp32s2/src/timg0/wdtconfig2.rs
index f6646544fa..70947ea581 100644
--- a/esp32s2/src/timg0/wdtconfig2.rs
+++ b/esp32s2/src/timg0/wdtconfig2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG2")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 0 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/wdtconfig3.rs b/esp32s2/src/timg0/wdtconfig3.rs
index da0cf49ce2..63b4ed60f6 100644
--- a/esp32s2/src/timg0/wdtconfig3.rs
+++ b/esp32s2/src/timg0/wdtconfig3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG3")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 1 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/wdtconfig4.rs b/esp32s2/src/timg0/wdtconfig4.rs
index 2bbbc5bfe8..d132842f1f 100644
--- a/esp32s2/src/timg0/wdtconfig4.rs
+++ b/esp32s2/src/timg0/wdtconfig4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG4")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 2 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/wdtconfig5.rs b/esp32s2/src/timg0/wdtconfig5.rs
index 661482c54b..d101561533 100644
--- a/esp32s2/src/timg0/wdtconfig5.rs
+++ b/esp32s2/src/timg0/wdtconfig5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG5")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 3 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32s2/src/timg0/wdtwprotect.rs b/esp32s2/src/timg0/wdtwprotect.rs
index 44efc107f3..ca73442322 100644
--- a/esp32s2/src/timg0/wdtwprotect.rs
+++ b/esp32s2/src/timg0/wdtwprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTWPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTWPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - If the register contains a different value than its reset value, write protection is enabled."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/arb_lost_cap.rs b/esp32s2/src/twai0/arb_lost_cap.rs
index 20ab158c4b..02b4812ac4 100644
--- a/esp32s2/src/twai0/arb_lost_cap.rs
+++ b/esp32s2/src/twai0/arb_lost_cap.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_LOST_CAP")
-            .field(
-                "arb_lost_cap",
-                &format_args!("{}", self.arb_lost_cap().bits()),
-            )
+            .field("arb_lost_cap", &self.arb_lost_cap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_LOST_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Arbitration Lost Capture Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_lost_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ARB_LOST_CAP_SPEC;
 impl crate::RegisterSpec for ARB_LOST_CAP_SPEC {
diff --git a/esp32s2/src/twai0/bus_timing_0.rs b/esp32s2/src/twai0/bus_timing_0.rs
index 4fe29d9648..c26ca19211 100644
--- a/esp32s2/src/twai0/bus_timing_0.rs
+++ b/esp32s2/src/twai0/bus_timing_0.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMING_0")
-            .field("baud_presc", &format_args!("{}", self.baud_presc().bits()))
-            .field(
-                "sync_jump_width",
-                &format_args!("{}", self.sync_jump_width().bits()),
-            )
+            .field("baud_presc", &self.baud_presc())
+            .field("sync_jump_width", &self.sync_jump_width())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMING_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Baud Rate Prescaler, determines the frequency dividing ratio."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/bus_timing_1.rs b/esp32s2/src/twai0/bus_timing_1.rs
index ec698b25b8..89a5dcc905 100644
--- a/esp32s2/src/twai0/bus_timing_1.rs
+++ b/esp32s2/src/twai0/bus_timing_1.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMING_1")
-            .field("time_seg1", &format_args!("{}", self.time_seg1().bits()))
-            .field("time_seg2", &format_args!("{}", self.time_seg2().bits()))
-            .field("time_samp", &format_args!("{}", self.time_samp().bit()))
+            .field("time_seg1", &self.time_seg1())
+            .field("time_seg2", &self.time_seg2())
+            .field("time_samp", &self.time_samp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMING_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The width of PBS1."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/clock_divider.rs b/esp32s2/src/twai0/clock_divider.rs
index 9d5176aca5..3021eab737 100644
--- a/esp32s2/src/twai0/clock_divider.rs
+++ b/esp32s2/src/twai0/clock_divider.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_DIVIDER")
-            .field("cd", &format_args!("{}", self.cd().bits()))
-            .field("clock_off", &format_args!("{}", self.clock_off().bit()))
+            .field("cd", &self.cd())
+            .field("clock_off", &self.clock_off())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_DIVIDER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - These bits are used to configure frequency dividing coefficients of the external CLKOUT pin."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/data_0.rs b/esp32s2/src/twai0/data_0.rs
index 921ebf3ab0..d87f222f23 100644
--- a/esp32s2/src/twai0/data_0.rs
+++ b/esp32s2/src/twai0/data_0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_0")
-            .field("tx_byte_0", &format_args!("{}", self.tx_byte_0().bits()))
+            .field("tx_byte_0", &self.tx_byte_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/data_1.rs b/esp32s2/src/twai0/data_1.rs
index aacde9f161..1e7ca2029e 100644
--- a/esp32s2/src/twai0/data_1.rs
+++ b/esp32s2/src/twai0/data_1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_1")
-            .field("tx_byte_1", &format_args!("{}", self.tx_byte_1().bits()))
+            .field("tx_byte_1", &self.tx_byte_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/data_10.rs b/esp32s2/src/twai0/data_10.rs
index d978cb608a..77ea6c46e1 100644
--- a/esp32s2/src/twai0/data_10.rs
+++ b/esp32s2/src/twai0/data_10.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_10")
-            .field("tx_byte_10", &format_args!("{}", self.tx_byte_10().bits()))
+            .field("tx_byte_10", &self.tx_byte_10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stored the 10th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/data_11.rs b/esp32s2/src/twai0/data_11.rs
index 69b3c01179..ea0f6a7d35 100644
--- a/esp32s2/src/twai0/data_11.rs
+++ b/esp32s2/src/twai0/data_11.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_11")
-            .field("tx_byte_11", &format_args!("{}", self.tx_byte_11().bits()))
+            .field("tx_byte_11", &self.tx_byte_11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stored the 11th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/data_12.rs b/esp32s2/src/twai0/data_12.rs
index be60409250..d8afde2384 100644
--- a/esp32s2/src/twai0/data_12.rs
+++ b/esp32s2/src/twai0/data_12.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_12")
-            .field("tx_byte_12", &format_args!("{}", self.tx_byte_12().bits()))
+            .field("tx_byte_12", &self.tx_byte_12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stored the 12th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/data_2.rs b/esp32s2/src/twai0/data_2.rs
index 8dfbf55812..f993610525 100644
--- a/esp32s2/src/twai0/data_2.rs
+++ b/esp32s2/src/twai0/data_2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_2")
-            .field("tx_byte_2", &format_args!("{}", self.tx_byte_2().bits()))
+            .field("tx_byte_2", &self.tx_byte_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/data_3.rs b/esp32s2/src/twai0/data_3.rs
index af279627a4..60075e6328 100644
--- a/esp32s2/src/twai0/data_3.rs
+++ b/esp32s2/src/twai0/data_3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_3")
-            .field("tx_byte_3", &format_args!("{}", self.tx_byte_3().bits()))
+            .field("tx_byte_3", &self.tx_byte_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/data_4.rs b/esp32s2/src/twai0/data_4.rs
index b55cb89b50..d64e72daaa 100644
--- a/esp32s2/src/twai0/data_4.rs
+++ b/esp32s2/src/twai0/data_4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_4")
-            .field("tx_byte_4", &format_args!("{}", self.tx_byte_4().bits()))
+            .field("tx_byte_4", &self.tx_byte_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/data_5.rs b/esp32s2/src/twai0/data_5.rs
index 81b906ce88..0378e6b32e 100644
--- a/esp32s2/src/twai0/data_5.rs
+++ b/esp32s2/src/twai0/data_5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_5")
-            .field("tx_byte_5", &format_args!("{}", self.tx_byte_5().bits()))
+            .field("tx_byte_5", &self.tx_byte_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/data_6.rs b/esp32s2/src/twai0/data_6.rs
index 9ea130bcfc..0de8e69ce7 100644
--- a/esp32s2/src/twai0/data_6.rs
+++ b/esp32s2/src/twai0/data_6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_6")
-            .field("tx_byte_6", &format_args!("{}", self.tx_byte_6().bits()))
+            .field("tx_byte_6", &self.tx_byte_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/data_7.rs b/esp32s2/src/twai0/data_7.rs
index 4081ec2628..0339194cea 100644
--- a/esp32s2/src/twai0/data_7.rs
+++ b/esp32s2/src/twai0/data_7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_7")
-            .field("tx_byte_7", &format_args!("{}", self.tx_byte_7().bits()))
+            .field("tx_byte_7", &self.tx_byte_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/data_8.rs b/esp32s2/src/twai0/data_8.rs
index 29694983b1..09ffc85913 100644
--- a/esp32s2/src/twai0/data_8.rs
+++ b/esp32s2/src/twai0/data_8.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_8")
-            .field("tx_byte_8", &format_args!("{}", self.tx_byte_8().bits()))
+            .field("tx_byte_8", &self.tx_byte_8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stored the 8th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/data_9.rs b/esp32s2/src/twai0/data_9.rs
index 6cb211c10e..60f9949a12 100644
--- a/esp32s2/src/twai0/data_9.rs
+++ b/esp32s2/src/twai0/data_9.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_9")
-            .field("tx_byte_9", &format_args!("{}", self.tx_byte_9().bits()))
+            .field("tx_byte_9", &self.tx_byte_9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stored the 9th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/err_code_cap.rs b/esp32s2/src/twai0/err_code_cap.rs
index 77f4f8b361..f4ce2b4b16 100644
--- a/esp32s2/src/twai0/err_code_cap.rs
+++ b/esp32s2/src/twai0/err_code_cap.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERR_CODE_CAP")
-            .field(
-                "ecc_segment",
-                &format_args!("{}", self.ecc_segment().bits()),
-            )
-            .field(
-                "ecc_direction",
-                &format_args!("{}", self.ecc_direction().bit()),
-            )
-            .field("ecc_type", &format_args!("{}", self.ecc_type().bits()))
+            .field("ecc_segment", &self.ecc_segment())
+            .field("ecc_direction", &self.ecc_direction())
+            .field("ecc_type", &self.ecc_type())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERR_CODE_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Error Code Capture Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_code_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ERR_CODE_CAP_SPEC;
 impl crate::RegisterSpec for ERR_CODE_CAP_SPEC {
diff --git a/esp32s2/src/twai0/err_warning_limit.rs b/esp32s2/src/twai0/err_warning_limit.rs
index eaca9801b5..0197a2df38 100644
--- a/esp32s2/src/twai0/err_warning_limit.rs
+++ b/esp32s2/src/twai0/err_warning_limit.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERR_WARNING_LIMIT")
-            .field(
-                "err_warning_limit",
-                &format_args!("{}", self.err_warning_limit().bits()),
-            )
+            .field("err_warning_limit", &self.err_warning_limit())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERR_WARNING_LIMIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid)."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/int_ena.rs b/esp32s2/src/twai0/int_ena.rs
index 750cc94df5..01ac1eef65 100644
--- a/esp32s2/src/twai0/int_ena.rs
+++ b/esp32s2/src/twai0/int_ena.rs
@@ -71,37 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_int_ena", &format_args!("{}", self.rx_int_ena().bit()))
-            .field("tx_int_ena", &format_args!("{}", self.tx_int_ena().bit()))
-            .field(
-                "err_warn_int_ena",
-                &format_args!("{}", self.err_warn_int_ena().bit()),
-            )
-            .field(
-                "overrun_int_ena",
-                &format_args!("{}", self.overrun_int_ena().bit()),
-            )
-            .field(
-                "err_passive_int_ena",
-                &format_args!("{}", self.err_passive_int_ena().bit()),
-            )
-            .field(
-                "arb_lost_int_ena",
-                &format_args!("{}", self.arb_lost_int_ena().bit()),
-            )
-            .field(
-                "bus_err_int_ena",
-                &format_args!("{}", self.bus_err_int_ena().bit()),
-            )
+            .field("rx_int_ena", &self.rx_int_ena())
+            .field("tx_int_ena", &self.tx_int_ena())
+            .field("err_warn_int_ena", &self.err_warn_int_ena())
+            .field("overrun_int_ena", &self.overrun_int_ena())
+            .field("err_passive_int_ena", &self.err_passive_int_ena())
+            .field("arb_lost_int_ena", &self.arb_lost_int_ena())
+            .field("bus_err_int_ena", &self.bus_err_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable receive interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/int_raw.rs b/esp32s2/src/twai0/int_raw.rs
index bcb5a07717..fe0b2105a8 100644
--- a/esp32s2/src/twai0/int_raw.rs
+++ b/esp32s2/src/twai0/int_raw.rs
@@ -55,37 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_int_st", &format_args!("{}", self.rx_int_st().bit()))
-            .field("tx_int_st", &format_args!("{}", self.tx_int_st().bit()))
-            .field(
-                "err_warn_int_st",
-                &format_args!("{}", self.err_warn_int_st().bit()),
-            )
-            .field(
-                "overrun_int_st",
-                &format_args!("{}", self.overrun_int_st().bit()),
-            )
-            .field(
-                "err_passive_int_st",
-                &format_args!("{}", self.err_passive_int_st().bit()),
-            )
-            .field(
-                "arb_lost_int_st",
-                &format_args!("{}", self.arb_lost_int_st().bit()),
-            )
-            .field(
-                "bus_err_int_st",
-                &format_args!("{}", self.bus_err_int_st().bit()),
-            )
+            .field("rx_int_st", &self.rx_int_st())
+            .field("tx_int_st", &self.tx_int_st())
+            .field("err_warn_int_st", &self.err_warn_int_st())
+            .field("overrun_int_st", &self.overrun_int_st())
+            .field("err_passive_int_st", &self.err_passive_int_st())
+            .field("arb_lost_int_st", &self.arb_lost_int_st())
+            .field("bus_err_int_st", &self.bus_err_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s2/src/twai0/mode.rs b/esp32s2/src/twai0/mode.rs
index dc3560c7e3..0d66f9a85c 100644
--- a/esp32s2/src/twai0/mode.rs
+++ b/esp32s2/src/twai0/mode.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODE")
-            .field("reset_mode", &format_args!("{}", self.reset_mode().bit()))
-            .field(
-                "listen_only_mode",
-                &format_args!("{}", self.listen_only_mode().bit()),
-            )
-            .field(
-                "self_test_mode",
-                &format_args!("{}", self.self_test_mode().bit()),
-            )
-            .field(
-                "rx_filter_mode",
-                &format_args!("{}", self.rx_filter_mode().bit()),
-            )
+            .field("reset_mode", &self.reset_mode())
+            .field("listen_only_mode", &self.listen_only_mode())
+            .field("self_test_mode", &self.self_test_mode())
+            .field("rx_filter_mode", &self.rx_filter_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/rx_err_cnt.rs b/esp32s2/src/twai0/rx_err_cnt.rs
index 66bf5c5d52..9c05d16bf3 100644
--- a/esp32s2/src/twai0/rx_err_cnt.rs
+++ b/esp32s2/src/twai0/rx_err_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ERR_CNT")
-            .field("rx_err_cnt", &format_args!("{}", self.rx_err_cnt().bits()))
+            .field("rx_err_cnt", &self.rx_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ERR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The RX error counter register, reflects value changes under reception status."]
     #[inline(always)]
diff --git a/esp32s2/src/twai0/rx_message_cnt.rs b/esp32s2/src/twai0/rx_message_cnt.rs
index 606f9b251e..13ca2f8eb4 100644
--- a/esp32s2/src/twai0/rx_message_cnt.rs
+++ b/esp32s2/src/twai0/rx_message_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_MESSAGE_CNT")
-            .field(
-                "rx_message_counter",
-                &format_args!("{}", self.rx_message_counter().bits()),
-            )
+            .field("rx_message_counter", &self.rx_message_counter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_MESSAGE_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive Message Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_message_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_MESSAGE_CNT_SPEC;
 impl crate::RegisterSpec for RX_MESSAGE_CNT_SPEC {
diff --git a/esp32s2/src/twai0/status.rs b/esp32s2/src/twai0/status.rs
index c9d0dd58e5..9a577030bd 100644
--- a/esp32s2/src/twai0/status.rs
+++ b/esp32s2/src/twai0/status.rs
@@ -69,24 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rx_buf_st", &format_args!("{}", self.rx_buf_st().bit()))
-            .field("overrun_st", &format_args!("{}", self.overrun_st().bit()))
-            .field("tx_buf_st", &format_args!("{}", self.tx_buf_st().bit()))
-            .field("tx_complete", &format_args!("{}", self.tx_complete().bit()))
-            .field("rx_st", &format_args!("{}", self.rx_st().bit()))
-            .field("tx_st", &format_args!("{}", self.tx_st().bit()))
-            .field("err_st", &format_args!("{}", self.err_st().bit()))
-            .field("bus_off_st", &format_args!("{}", self.bus_off_st().bit()))
-            .field("miss_st", &format_args!("{}", self.miss_st().bit()))
+            .field("rx_buf_st", &self.rx_buf_st())
+            .field("overrun_st", &self.overrun_st())
+            .field("tx_buf_st", &self.tx_buf_st())
+            .field("tx_complete", &self.tx_complete())
+            .field("rx_st", &self.rx_st())
+            .field("tx_st", &self.tx_st())
+            .field("err_st", &self.err_st())
+            .field("bus_off_st", &self.bus_off_st())
+            .field("miss_st", &self.miss_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32s2/src/twai0/tx_err_cnt.rs b/esp32s2/src/twai0/tx_err_cnt.rs
index 3fb0a9d0ef..5d5b84441c 100644
--- a/esp32s2/src/twai0/tx_err_cnt.rs
+++ b/esp32s2/src/twai0/tx_err_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_ERR_CNT")
-            .field("tx_err_cnt", &format_args!("{}", self.tx_err_cnt().bits()))
+            .field("tx_err_cnt", &self.tx_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_ERR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The TX error counter register, reflects value changes under transmission status."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/at_cmd_char.rs b/esp32s2/src/uart0/at_cmd_char.rs
index a99a8e07dd..cfd3dcec5d 100644
--- a/esp32s2/src/uart0/at_cmd_char.rs
+++ b/esp32s2/src/uart0/at_cmd_char.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_CHAR")
-            .field(
-                "at_cmd_char",
-                &format_args!("{}", self.at_cmd_char().bits()),
-            )
-            .field("char_num", &format_args!("{}", self.char_num().bits()))
+            .field("at_cmd_char", &self.at_cmd_char())
+            .field("char_num", &self.char_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_CHAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the content of AT_CMD character."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/at_cmd_gaptout.rs b/esp32s2/src/uart0/at_cmd_gaptout.rs
index 619e98db83..8666d30739 100644
--- a/esp32s2/src/uart0/at_cmd_gaptout.rs
+++ b/esp32s2/src/uart0/at_cmd_gaptout.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_GAPTOUT")
-            .field(
-                "rx_gap_tout",
-                &format_args!("{}", self.rx_gap_tout().bits()),
-            )
+            .field("rx_gap_tout", &self.rx_gap_tout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_GAPTOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the AT_CMD characters. It will not take the data as continuous AT_CMD characters when the duration time is less than this register's value."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/at_cmd_postcnt.rs b/esp32s2/src/uart0/at_cmd_postcnt.rs
index 4057a09a35..4945522db8 100644
--- a/esp32s2/src/uart0/at_cmd_postcnt.rs
+++ b/esp32s2/src/uart0/at_cmd_postcnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_POSTCNT")
-            .field(
-                "post_idle_num",
-                &format_args!("{}", self.post_idle_num().bits()),
-            )
+            .field("post_idle_num", &self.post_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_POSTCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the last AT_CMD and the next data. It will not take the previous data as AT_CMD character when the duration is less than this register's value."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/at_cmd_precnt.rs b/esp32s2/src/uart0/at_cmd_precnt.rs
index 05ebe01519..0beb1740c6 100644
--- a/esp32s2/src/uart0/at_cmd_precnt.rs
+++ b/esp32s2/src/uart0/at_cmd_precnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_PRECNT")
-            .field(
-                "pre_idle_num",
-                &format_args!("{}", self.pre_idle_num().bits()),
-            )
+            .field("pre_idle_num", &self.pre_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_PRECNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first AT_CMD is received by the receiver. It will not take the next data received as AT_CMD character when the duration is less than this register's value."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/autobaud.rs b/esp32s2/src/uart0/autobaud.rs
index db47d45de0..3f464b29ca 100644
--- a/esp32s2/src/uart0/autobaud.rs
+++ b/esp32s2/src/uart0/autobaud.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AUTOBAUD")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field(
-                "glitch_filt",
-                &format_args!("{}", self.glitch_filt().bits()),
-            )
+            .field("en", &self.en())
+            .field("glitch_filt", &self.glitch_filt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AUTOBAUD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enable bit for baud rate detection."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/clkdiv.rs b/esp32s2/src/uart0/clkdiv.rs
index be12339d77..7a243e0cc8 100644
--- a/esp32s2/src/uart0/clkdiv.rs
+++ b/esp32s2/src/uart0/clkdiv.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKDIV")
-            .field("clkdiv", &format_args!("{}", self.clkdiv().bits()))
-            .field("frag", &format_args!("{}", self.frag().bits()))
+            .field("clkdiv", &self.clkdiv())
+            .field("frag", &self.frag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKDIV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - The integral part of the frequency divisor."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/conf0.rs b/esp32s2/src/uart0/conf0.rs
index 295e4874cb..ceb89565f6 100644
--- a/esp32s2/src/uart0/conf0.rs
+++ b/esp32s2/src/uart0/conf0.rs
@@ -251,48 +251,36 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("parity", &format_args!("{}", self.parity().bit()))
-            .field("parity_en", &format_args!("{}", self.parity_en().bit()))
-            .field("bit_num", &format_args!("{}", self.bit_num().bits()))
-            .field(
-                "stop_bit_num",
-                &format_args!("{}", self.stop_bit_num().bits()),
-            )
-            .field("sw_rts", &format_args!("{}", self.sw_rts().bit()))
-            .field("sw_dtr", &format_args!("{}", self.sw_dtr().bit()))
-            .field("txd_brk", &format_args!("{}", self.txd_brk().bit()))
-            .field("irda_dplx", &format_args!("{}", self.irda_dplx().bit()))
-            .field("irda_tx_en", &format_args!("{}", self.irda_tx_en().bit()))
-            .field("irda_wctl", &format_args!("{}", self.irda_wctl().bit()))
-            .field("irda_tx_inv", &format_args!("{}", self.irda_tx_inv().bit()))
-            .field("irda_rx_inv", &format_args!("{}", self.irda_rx_inv().bit()))
-            .field("loopback", &format_args!("{}", self.loopback().bit()))
-            .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit()))
-            .field("irda_en", &format_args!("{}", self.irda_en().bit()))
-            .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit()))
-            .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit()))
-            .field("rxd_inv", &format_args!("{}", self.rxd_inv().bit()))
-            .field("cts_inv", &format_args!("{}", self.cts_inv().bit()))
-            .field("dsr_inv", &format_args!("{}", self.dsr_inv().bit()))
-            .field("txd_inv", &format_args!("{}", self.txd_inv().bit()))
-            .field("rts_inv", &format_args!("{}", self.rts_inv().bit()))
-            .field("dtr_inv", &format_args!("{}", self.dtr_inv().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("err_wr_mask", &format_args!("{}", self.err_wr_mask().bit()))
-            .field(
-                "tick_ref_always_on",
-                &format_args!("{}", self.tick_ref_always_on().bit()),
-            )
-            .field("mem_clk_en", &format_args!("{}", self.mem_clk_en().bit()))
+            .field("parity", &self.parity())
+            .field("parity_en", &self.parity_en())
+            .field("bit_num", &self.bit_num())
+            .field("stop_bit_num", &self.stop_bit_num())
+            .field("sw_rts", &self.sw_rts())
+            .field("sw_dtr", &self.sw_dtr())
+            .field("txd_brk", &self.txd_brk())
+            .field("irda_dplx", &self.irda_dplx())
+            .field("irda_tx_en", &self.irda_tx_en())
+            .field("irda_wctl", &self.irda_wctl())
+            .field("irda_tx_inv", &self.irda_tx_inv())
+            .field("irda_rx_inv", &self.irda_rx_inv())
+            .field("loopback", &self.loopback())
+            .field("tx_flow_en", &self.tx_flow_en())
+            .field("irda_en", &self.irda_en())
+            .field("rxfifo_rst", &self.rxfifo_rst())
+            .field("txfifo_rst", &self.txfifo_rst())
+            .field("rxd_inv", &self.rxd_inv())
+            .field("cts_inv", &self.cts_inv())
+            .field("dsr_inv", &self.dsr_inv())
+            .field("txd_inv", &self.txd_inv())
+            .field("rts_inv", &self.rts_inv())
+            .field("dtr_inv", &self.dtr_inv())
+            .field("clk_en", &self.clk_en())
+            .field("err_wr_mask", &self.err_wr_mask())
+            .field("tick_ref_always_on", &self.tick_ref_always_on())
+            .field("mem_clk_en", &self.mem_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to configure the parity check mode. 0: even. 1: odd."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/conf1.rs b/esp32s2/src/uart0/conf1.rs
index 2bec7046cf..a9a88e949f 100644
--- a/esp32s2/src/uart0/conf1.rs
+++ b/esp32s2/src/uart0/conf1.rs
@@ -53,29 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "rxfifo_full_thrhd",
-                &format_args!("{}", self.rxfifo_full_thrhd().bits()),
-            )
-            .field(
-                "txfifo_empty_thrhd",
-                &format_args!("{}", self.txfifo_empty_thrhd().bits()),
-            )
-            .field(
-                "rx_tout_flow_dis",
-                &format_args!("{}", self.rx_tout_flow_dis().bit()),
-            )
-            .field("rx_flow_en", &format_args!("{}", self.rx_flow_en().bit()))
-            .field("rx_tout_en", &format_args!("{}", self.rx_tout_en().bit()))
+            .field("rxfifo_full_thrhd", &self.rxfifo_full_thrhd())
+            .field("txfifo_empty_thrhd", &self.txfifo_empty_thrhd())
+            .field("rx_tout_flow_dis", &self.rx_tout_flow_dis())
+            .field("rx_flow_en", &self.rx_flow_en())
+            .field("rx_tout_en", &self.rx_tout_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - An UART_RXFIFO_FULL_INT interrupt is generated when the receiver receives more data than this register’s value."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/date.rs b/esp32s2/src/uart0/date.rs
index 4eb1d8257b..54e7cefd85 100644
--- a/esp32s2/src/uart0/date.rs
+++ b/esp32s2/src/uart0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/uart0/fifo.rs b/esp32s2/src/uart0/fifo.rs
index 3ea719e7ab..fdc9ee6700 100644
--- a/esp32s2/src/uart0/fifo.rs
+++ b/esp32s2/src/uart0/fifo.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO")
-            .field(
-                "rxfifo_rd_byte",
-                &format_args!("{}", self.rxfifo_rd_byte().bits()),
-            )
+            .field("rxfifo_rd_byte", &self.rxfifo_rd_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - UART 0 accesses FIFO via this register."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/flow_conf.rs b/esp32s2/src/uart0/flow_conf.rs
index bd79847318..e82a398a42 100644
--- a/esp32s2/src/uart0/flow_conf.rs
+++ b/esp32s2/src/uart0/flow_conf.rs
@@ -62,24 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLOW_CONF")
-            .field(
-                "sw_flow_con_en",
-                &format_args!("{}", self.sw_flow_con_en().bit()),
-            )
-            .field("xonoff_del", &format_args!("{}", self.xonoff_del().bit()))
-            .field("force_xon", &format_args!("{}", self.force_xon().bit()))
-            .field("force_xoff", &format_args!("{}", self.force_xoff().bit()))
-            .field("send_xon", &format_args!("{}", self.send_xon().bit()))
-            .field("send_xoff", &format_args!("{}", self.send_xoff().bit()))
+            .field("sw_flow_con_en", &self.sw_flow_con_en())
+            .field("xonoff_del", &self.xonoff_del())
+            .field("force_xon", &self.force_xon())
+            .field("force_xoff", &self.force_xoff())
+            .field("send_xon", &self.send_xon())
+            .field("send_xoff", &self.send_xoff())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLOW_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable software flow control. When UART receives flow control characters XON or XOFF, which can be configured by UART_XON_CHAR or UART_XOFF_CHAR respectively, UART_SW_XON_INT or UART_SW_XOFF_INT interrupts can be triggered if enabled."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/fsm_status.rs b/esp32s2/src/uart0/fsm_status.rs
index 92c9158287..60770a47a2 100644
--- a/esp32s2/src/uart0/fsm_status.rs
+++ b/esp32s2/src/uart0/fsm_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_STATUS")
-            .field("st_urx_out", &format_args!("{}", self.st_urx_out().bits()))
-            .field("st_utx_out", &format_args!("{}", self.st_utx_out().bits()))
+            .field("st_urx_out", &self.st_urx_out())
+            .field("st_utx_out", &self.st_utx_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART transmitter and receiver status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FSM_STATUS_SPEC;
 impl crate::RegisterSpec for FSM_STATUS_SPEC {
diff --git a/esp32s2/src/uart0/highpulse.rs b/esp32s2/src/uart0/highpulse.rs
index f3b6e88967..5e60f60ed6 100644
--- a/esp32s2/src/uart0/highpulse.rs
+++ b/esp32s2/src/uart0/highpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIGHPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIGHPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud minimum high pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`highpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIGHPULSE_SPEC;
 impl crate::RegisterSpec for HIGHPULSE_SPEC {
diff --git a/esp32s2/src/uart0/id.rs b/esp32s2/src/uart0/id.rs
index c56cf3bcb6..6774166853 100644
--- a/esp32s2/src/uart0/id.rs
+++ b/esp32s2/src/uart0/id.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("ID")
-            .field("id", &format_args!("{}", self.id().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("ID").field("id", &self.id()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/uart0/idle_conf.rs b/esp32s2/src/uart0/idle_conf.rs
index 9b1a9a81f6..b348c3155b 100644
--- a/esp32s2/src/uart0/idle_conf.rs
+++ b/esp32s2/src/uart0/idle_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDLE_CONF")
-            .field(
-                "rx_idle_thrhd",
-                &format_args!("{}", self.rx_idle_thrhd().bits()),
-            )
-            .field(
-                "tx_idle_num",
-                &format_args!("{}", self.tx_idle_num().bits()),
-            )
-            .field("tx_brk_num", &format_args!("{}", self.tx_brk_num().bits()))
+            .field("rx_idle_thrhd", &self.rx_idle_thrhd())
+            .field("tx_idle_num", &self.tx_idle_num())
+            .field("tx_brk_num", &self.tx_brk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - A frame end signal is generated when the receiver takes more time to receive one byte data than this register's value, in the unit of bit time (the time it takes to transfer one bit)."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/int_ena.rs b/esp32s2/src/uart0/int_ena.rs
index 4ed38c5151..397d913666 100644
--- a/esp32s2/src/uart0/int_ena.rs
+++ b/esp32s2/src/uart0/int_ena.rs
@@ -188,50 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enable bit for UART_RXFIFO_FULL_INT."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/int_raw.rs b/esp32s2/src/uart0/int_raw.rs
index 1b1a8b2825..cb9ab172fa 100644
--- a/esp32s2/src/uart0/int_raw.rs
+++ b/esp32s2/src/uart0/int_raw.rs
@@ -146,50 +146,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s2/src/uart0/int_st.rs b/esp32s2/src/uart0/int_st.rs
index 9c779b57be..935be49aad 100644
--- a/esp32s2/src/uart0/int_st.rs
+++ b/esp32s2/src/uart0/int_st.rs
@@ -146,50 +146,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s2/src/uart0/lowpulse.rs b/esp32s2/src/uart0/lowpulse.rs
index 0314486b6d..723ca88246 100644
--- a/esp32s2/src/uart0/lowpulse.rs
+++ b/esp32s2/src/uart0/lowpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOWPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOWPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud minimum low pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lowpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOWPULSE_SPEC;
 impl crate::RegisterSpec for LOWPULSE_SPEC {
diff --git a/esp32s2/src/uart0/mem_conf.rs b/esp32s2/src/uart0/mem_conf.rs
index ea9569d05e..a1c5e81db3 100644
--- a/esp32s2/src/uart0/mem_conf.rs
+++ b/esp32s2/src/uart0/mem_conf.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field("rx_size", &format_args!("{}", self.rx_size().bits()))
-            .field("tx_size", &format_args!("{}", self.tx_size().bits()))
-            .field(
-                "rx_flow_thrhd",
-                &format_args!("{}", self.rx_flow_thrhd().bits()),
-            )
-            .field(
-                "rx_tout_thrhd",
-                &format_args!("{}", self.rx_tout_thrhd().bits()),
-            )
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
+            .field("rx_size", &self.rx_size())
+            .field("tx_size", &self.tx_size())
+            .field("rx_flow_thrhd", &self.rx_flow_thrhd())
+            .field("rx_tout_thrhd", &self.rx_tout_thrhd())
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 1:3 - This register is used to configure the amount of RAM allocated for RX FIFO. The default number is 128 bytes."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/mem_rx_status.rs b/esp32s2/src/uart0/mem_rx_status.rs
index 872d81fa2f..c9406483c7 100644
--- a/esp32s2/src/uart0/mem_rx_status.rs
+++ b/esp32s2/src/uart0/mem_rx_status.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_RX_STATUS")
-            .field(
-                "apb_rx_raddr",
-                &format_args!("{}", self.apb_rx_raddr().bits()),
-            )
-            .field("rx_waddr", &format_args!("{}", self.rx_waddr().bits()))
+            .field("apb_rx_raddr", &self.apb_rx_raddr())
+            .field("rx_waddr", &self.rx_waddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RX FIFO write and read offset address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_RX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_RX_STATUS_SPEC {
diff --git a/esp32s2/src/uart0/mem_tx_status.rs b/esp32s2/src/uart0/mem_tx_status.rs
index 2d41eb279a..f9c24cd3ba 100644
--- a/esp32s2/src/uart0/mem_tx_status.rs
+++ b/esp32s2/src/uart0/mem_tx_status.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_TX_STATUS")
-            .field(
-                "apb_tx_waddr",
-                &format_args!("{}", self.apb_tx_waddr().bits()),
-            )
-            .field("tx_raddr", &format_args!("{}", self.tx_raddr().bits()))
+            .field("apb_tx_waddr", &self.apb_tx_waddr())
+            .field("tx_raddr", &self.tx_raddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "TX FIFO write and read offset address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_TX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_TX_STATUS_SPEC {
diff --git a/esp32s2/src/uart0/negpulse.rs b/esp32s2/src/uart0/negpulse.rs
index c65ce1b60a..1052b91554 100644
--- a/esp32s2/src/uart0/negpulse.rs
+++ b/esp32s2/src/uart0/negpulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NEGPULSE")
-            .field(
-                "negedge_min_cnt",
-                &format_args!("{}", self.negedge_min_cnt().bits()),
-            )
+            .field("negedge_min_cnt", &self.negedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NEGPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud low pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`negpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NEGPULSE_SPEC;
 impl crate::RegisterSpec for NEGPULSE_SPEC {
diff --git a/esp32s2/src/uart0/pospulse.rs b/esp32s2/src/uart0/pospulse.rs
index 272d2b6ca5..090515995b 100644
--- a/esp32s2/src/uart0/pospulse.rs
+++ b/esp32s2/src/uart0/pospulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POSPULSE")
-            .field(
-                "posedge_min_cnt",
-                &format_args!("{}", self.posedge_min_cnt().bits()),
-            )
+            .field("posedge_min_cnt", &self.posedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POSPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud high pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pospulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct POSPULSE_SPEC;
 impl crate::RegisterSpec for POSPULSE_SPEC {
diff --git a/esp32s2/src/uart0/rs485_conf.rs b/esp32s2/src/uart0/rs485_conf.rs
index 4e7cf021aa..2f4c28822f 100644
--- a/esp32s2/src/uart0/rs485_conf.rs
+++ b/esp32s2/src/uart0/rs485_conf.rs
@@ -71,34 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RS485_CONF")
-            .field("rs485_en", &format_args!("{}", self.rs485_en().bit()))
-            .field("dl0_en", &format_args!("{}", self.dl0_en().bit()))
-            .field("dl1_en", &format_args!("{}", self.dl1_en().bit()))
-            .field(
-                "rs485tx_rx_en",
-                &format_args!("{}", self.rs485tx_rx_en().bit()),
-            )
-            .field(
-                "rs485rxby_tx_en",
-                &format_args!("{}", self.rs485rxby_tx_en().bit()),
-            )
-            .field(
-                "rs485_rx_dly_num",
-                &format_args!("{}", self.rs485_rx_dly_num().bit()),
-            )
-            .field(
-                "rs485_tx_dly_num",
-                &format_args!("{}", self.rs485_tx_dly_num().bits()),
-            )
+            .field("rs485_en", &self.rs485_en())
+            .field("dl0_en", &self.dl0_en())
+            .field("dl1_en", &self.dl1_en())
+            .field("rs485tx_rx_en", &self.rs485tx_rx_en())
+            .field("rs485rxby_tx_en", &self.rs485rxby_tx_en())
+            .field("rs485_rx_dly_num", &self.rs485_rx_dly_num())
+            .field("rs485_tx_dly_num", &self.rs485_tx_dly_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RS485_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to choose RS485 mode."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/rxd_cnt.rs b/esp32s2/src/uart0/rxd_cnt.rs
index bd6056d241..68b7b28998 100644
--- a/esp32s2/src/uart0/rxd_cnt.rs
+++ b/esp32s2/src/uart0/rxd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXD_CNT")
-            .field(
-                "rxd_edge_cnt",
-                &format_args!("{}", self.rxd_edge_cnt().bits()),
-            )
+            .field("rxd_edge_cnt", &self.rxd_edge_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud edge change count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXD_CNT_SPEC;
 impl crate::RegisterSpec for RXD_CNT_SPEC {
diff --git a/esp32s2/src/uart0/sleep_conf.rs b/esp32s2/src/uart0/sleep_conf.rs
index 128e4eabab..a530e86db4 100644
--- a/esp32s2/src/uart0/sleep_conf.rs
+++ b/esp32s2/src/uart0/sleep_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF")
-            .field(
-                "active_threshold",
-                &format_args!("{}", self.active_threshold().bits()),
-            )
+            .field("active_threshold", &self.active_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The UART is activated from Light-sleep mode when the input RXD edge changes more times than this register's value."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/status.rs b/esp32s2/src/uart0/status.rs
index 841696685a..01e6b01213 100644
--- a/esp32s2/src/uart0/status.rs
+++ b/esp32s2/src/uart0/status.rs
@@ -62,23 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("dsrn", &format_args!("{}", self.dsrn().bit()))
-            .field("ctsn", &format_args!("{}", self.ctsn().bit()))
-            .field("rxd", &format_args!("{}", self.rxd().bit()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field("dtrn", &format_args!("{}", self.dtrn().bit()))
-            .field("rtsn", &format_args!("{}", self.rtsn().bit()))
-            .field("txd", &format_args!("{}", self.txd().bit()))
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("dsrn", &self.dsrn())
+            .field("ctsn", &self.ctsn())
+            .field("rxd", &self.rxd())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("dtrn", &self.dtrn())
+            .field("rtsn", &self.rtsn())
+            .field("txd", &self.txd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32s2/src/uart0/swfc_conf0.rs b/esp32s2/src/uart0/swfc_conf0.rs
index 2e23a8295c..90508bceb2 100644
--- a/esp32s2/src/uart0/swfc_conf0.rs
+++ b/esp32s2/src/uart0/swfc_conf0.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF0")
-            .field(
-                "xoff_threshold",
-                &format_args!("{}", self.xoff_threshold().bits()),
-            )
-            .field("xoff_char", &format_args!("{}", self.xoff_char().bits()))
+            .field("xoff_threshold", &self.xoff_threshold())
+            .field("xoff_char", &self.xoff_char())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - When the number of data bytes in RX FIFO is more than this register's value with UART_SW_FLOW_CON_EN set to 1, the transmitter sends an XOFF character."]
     #[inline(always)]
diff --git a/esp32s2/src/uart0/swfc_conf1.rs b/esp32s2/src/uart0/swfc_conf1.rs
index 665ede12f6..31fc4611d2 100644
--- a/esp32s2/src/uart0/swfc_conf1.rs
+++ b/esp32s2/src/uart0/swfc_conf1.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF1")
-            .field(
-                "xon_threshold",
-                &format_args!("{}", self.xon_threshold().bits()),
-            )
-            .field("xon_char", &format_args!("{}", self.xon_char().bits()))
+            .field("xon_threshold", &self.xon_threshold())
+            .field("xon_char", &self.xon_char())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - When the number of data bytes in RX FIFO is less than this register's value with UART_SW_FLOW_CON_EN set to 1, the transmitter sends an XON character."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/ahb_test.rs b/esp32s2/src/uhci0/ahb_test.rs
index ab6a6f6ae7..64218f7905 100644
--- a/esp32s2/src/uhci0/ahb_test.rs
+++ b/esp32s2/src/uhci0/ahb_test.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_TEST")
-            .field(
-                "ahb_testmode",
-                &format_args!("{}", self.ahb_testmode().bits()),
-            )
-            .field(
-                "ahb_testaddr",
-                &format_args!("{}", self.ahb_testaddr().bits()),
-            )
+            .field("ahb_testmode", &self.ahb_testmode())
+            .field("ahb_testaddr", &self.ahb_testaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_TEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Reserved."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/conf0.rs b/esp32s2/src/uhci0/conf0.rs
index 8ccaeadc5c..b2390065a6 100644
--- a/esp32s2/src/uhci0/conf0.rs
+++ b/esp32s2/src/uhci0/conf0.rs
@@ -206,73 +206,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
-            .field("out_rst", &format_args!("{}", self.out_rst().bit()))
-            .field(
-                "ahbm_fifo_rst",
-                &format_args!("{}", self.ahbm_fifo_rst().bit()),
-            )
-            .field("ahbm_rst", &format_args!("{}", self.ahbm_rst().bit()))
-            .field(
-                "in_loop_test",
-                &format_args!("{}", self.in_loop_test().bit()),
-            )
-            .field(
-                "out_loop_test",
-                &format_args!("{}", self.out_loop_test().bit()),
-            )
-            .field(
-                "out_auto_wrback",
-                &format_args!("{}", self.out_auto_wrback().bit()),
-            )
-            .field(
-                "out_no_restart_clr",
-                &format_args!("{}", self.out_no_restart_clr().bit()),
-            )
-            .field(
-                "out_eof_mode",
-                &format_args!("{}", self.out_eof_mode().bit()),
-            )
-            .field("uart0_ce", &format_args!("{}", self.uart0_ce().bit()))
-            .field("uart1_ce", &format_args!("{}", self.uart1_ce().bit()))
-            .field(
-                "outdscr_burst_en",
-                &format_args!("{}", self.outdscr_burst_en().bit()),
-            )
-            .field(
-                "indscr_burst_en",
-                &format_args!("{}", self.indscr_burst_en().bit()),
-            )
-            .field(
-                "mem_trans_en",
-                &format_args!("{}", self.mem_trans_en().bit()),
-            )
-            .field("seper_en", &format_args!("{}", self.seper_en().bit()))
-            .field("head_en", &format_args!("{}", self.head_en().bit()))
-            .field("crc_rec_en", &format_args!("{}", self.crc_rec_en().bit()))
-            .field(
-                "uart_idle_eof_en",
-                &format_args!("{}", self.uart_idle_eof_en().bit()),
-            )
-            .field("len_eof_en", &format_args!("{}", self.len_eof_en().bit()))
-            .field(
-                "encode_crc_en",
-                &format_args!("{}", self.encode_crc_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "uart_rx_brk_eof_en",
-                &format_args!("{}", self.uart_rx_brk_eof_en().bit()),
-            )
+            .field("in_rst", &self.in_rst())
+            .field("out_rst", &self.out_rst())
+            .field("ahbm_fifo_rst", &self.ahbm_fifo_rst())
+            .field("ahbm_rst", &self.ahbm_rst())
+            .field("in_loop_test", &self.in_loop_test())
+            .field("out_loop_test", &self.out_loop_test())
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("out_no_restart_clr", &self.out_no_restart_clr())
+            .field("out_eof_mode", &self.out_eof_mode())
+            .field("uart0_ce", &self.uart0_ce())
+            .field("uart1_ce", &self.uart1_ce())
+            .field("outdscr_burst_en", &self.outdscr_burst_en())
+            .field("indscr_burst_en", &self.indscr_burst_en())
+            .field("mem_trans_en", &self.mem_trans_en())
+            .field("seper_en", &self.seper_en())
+            .field("head_en", &self.head_en())
+            .field("crc_rec_en", &self.crc_rec_en())
+            .field("uart_idle_eof_en", &self.uart_idle_eof_en())
+            .field("len_eof_en", &self.len_eof_en())
+            .field("encode_crc_en", &self.encode_crc_en())
+            .field("clk_en", &self.clk_en())
+            .field("uart_rx_brk_eof_en", &self.uart_rx_brk_eof_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset in DMA FSM."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/conf1.rs b/esp32s2/src/uhci0/conf1.rs
index cd811bbc56..bd934864df 100644
--- a/esp32s2/src/uhci0/conf1.rs
+++ b/esp32s2/src/uhci0/conf1.rs
@@ -98,43 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "check_sum_en",
-                &format_args!("{}", self.check_sum_en().bit()),
-            )
-            .field(
-                "check_seq_en",
-                &format_args!("{}", self.check_seq_en().bit()),
-            )
-            .field("crc_disable", &format_args!("{}", self.crc_disable().bit()))
-            .field("save_head", &format_args!("{}", self.save_head().bit()))
-            .field(
-                "tx_check_sum_re",
-                &format_args!("{}", self.tx_check_sum_re().bit()),
-            )
-            .field(
-                "tx_ack_num_re",
-                &format_args!("{}", self.tx_ack_num_re().bit()),
-            )
-            .field("check_owner", &format_args!("{}", self.check_owner().bit()))
-            .field(
-                "wait_sw_start",
-                &format_args!("{}", self.wait_sw_start().bit()),
-            )
-            .field("sw_start", &format_args!("{}", self.sw_start().bit()))
-            .field(
-                "dma_infifo_full_thrs",
-                &format_args!("{}", self.dma_infifo_full_thrs().bits()),
-            )
+            .field("check_sum_en", &self.check_sum_en())
+            .field("check_seq_en", &self.check_seq_en())
+            .field("crc_disable", &self.crc_disable())
+            .field("save_head", &self.save_head())
+            .field("tx_check_sum_re", &self.tx_check_sum_re())
+            .field("tx_ack_num_re", &self.tx_ack_num_re())
+            .field("check_owner", &self.check_owner())
+            .field("wait_sw_start", &self.wait_sw_start())
+            .field("sw_start", &self.sw_start())
+            .field("dma_infifo_full_thrs", &self.dma_infifo_full_thrs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enable bit to check header checksum when UHCI receives a data packet."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/date.rs b/esp32s2/src/uhci0/date.rs
index c2e89a206d..c0f78e4fa4 100644
--- a/esp32s2/src/uhci0/date.rs
+++ b/esp32s2/src/uhci0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/uhci0/dma_in_dscr.rs b/esp32s2/src/uhci0/dma_in_dscr.rs
index 12b0f7565f..012f5990ca 100644
--- a/esp32s2/src/uhci0/dma_in_dscr.rs
+++ b/esp32s2/src/uhci0/dma_in_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_DSCR")
-            .field(
-                "inlink_dscr",
-                &format_args!("{}", self.inlink_dscr().bits()),
-            )
+            .field("inlink_dscr", &self.inlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The third word of the next receive descriptor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_in_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_IN_DSCR_SPEC;
 impl crate::RegisterSpec for DMA_IN_DSCR_SPEC {
diff --git a/esp32s2/src/uhci0/dma_in_dscr_bf0.rs b/esp32s2/src/uhci0/dma_in_dscr_bf0.rs
index 09ff374818..02e784c529 100644
--- a/esp32s2/src/uhci0/dma_in_dscr_bf0.rs
+++ b/esp32s2/src/uhci0/dma_in_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_DSCR_BF0")
-            .field(
-                "inlink_dscr_bf0",
-                &format_args!("{}", self.inlink_dscr_bf0().bits()),
-            )
+            .field("inlink_dscr_bf0", &self.inlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The third word of current receive descriptor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_in_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_IN_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for DMA_IN_DSCR_BF0_SPEC {
diff --git a/esp32s2/src/uhci0/dma_in_err_eof_des_addr.rs b/esp32s2/src/uhci0/dma_in_err_eof_des_addr.rs
index b2603f31b5..2a195a4b24 100644
--- a/esp32s2/src/uhci0/dma_in_err_eof_des_addr.rs
+++ b/esp32s2/src/uhci0/dma_in_err_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_ERR_EOF_DES_ADDR")
-            .field(
-                "in_err_eof_des_addr",
-                &format_args!("{}", self.in_err_eof_des_addr().bits()),
-            )
+            .field("in_err_eof_des_addr", &self.in_err_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_ERR_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Inlink descriptor address when errors occur\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_in_err_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_IN_ERR_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for DMA_IN_ERR_EOF_DES_ADDR_SPEC {
diff --git a/esp32s2/src/uhci0/dma_in_link.rs b/esp32s2/src/uhci0/dma_in_link.rs
index f3a5adb2d6..ffda9bc8f1 100644
--- a/esp32s2/src/uhci0/dma_in_link.rs
+++ b/esp32s2/src/uhci0/dma_in_link.rs
@@ -60,33 +60,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_LINK")
-            .field(
-                "inlink_addr",
-                &format_args!("{}", self.inlink_addr().bits()),
-            )
-            .field(
-                "inlink_auto_ret",
-                &format_args!("{}", self.inlink_auto_ret().bit()),
-            )
-            .field("inlink_stop", &format_args!("{}", self.inlink_stop().bit()))
-            .field(
-                "inlink_start",
-                &format_args!("{}", self.inlink_start().bit()),
-            )
-            .field(
-                "inlink_restart",
-                &format_args!("{}", self.inlink_restart().bit()),
-            )
-            .field("inlink_park", &format_args!("{}", self.inlink_park().bit()))
+            .field("inlink_addr", &self.inlink_addr())
+            .field("inlink_auto_ret", &self.inlink_auto_ret())
+            .field("inlink_stop", &self.inlink_stop())
+            .field("inlink_start", &self.inlink_start())
+            .field("inlink_restart", &self.inlink_restart())
+            .field("inlink_park", &self.inlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register is used to specify the least significant 20 bits of the first receive descriptor's address."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/dma_in_pop.rs b/esp32s2/src/uhci0/dma_in_pop.rs
index 6af724985b..2f4f5d990a 100644
--- a/esp32s2/src/uhci0/dma_in_pop.rs
+++ b/esp32s2/src/uhci0/dma_in_pop.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_POP")
-            .field(
-                "infifo_rdata",
-                &format_args!("{}", self.infifo_rdata().bits()),
-            )
-            .field("infifo_pop", &format_args!("{}", self.infifo_pop().bit()))
+            .field("infifo_rdata", &self.infifo_rdata())
+            .field("infifo_pop", &self.infifo_pop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_POP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 16 - Set this bit to pop data from RX FIFO."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/dma_in_status.rs b/esp32s2/src/uhci0/dma_in_status.rs
index a77d53ccde..3645ebb6bf 100644
--- a/esp32s2/src/uhci0/dma_in_status.rs
+++ b/esp32s2/src/uhci0/dma_in_status.rs
@@ -27,21 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_STATUS")
-            .field("in_full", &format_args!("{}", self.in_full().bit()))
-            .field("in_empty", &format_args!("{}", self.in_empty().bit()))
-            .field(
-                "rx_err_cause",
-                &format_args!("{}", self.rx_err_cause().bits()),
-            )
+            .field("in_full", &self.in_full())
+            .field("in_empty", &self.in_empty())
+            .field("rx_err_cause", &self.rx_err_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UHCI data-input status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_in_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_IN_STATUS_SPEC;
 impl crate::RegisterSpec for DMA_IN_STATUS_SPEC {
diff --git a/esp32s2/src/uhci0/dma_in_suc_eof_des_addr.rs b/esp32s2/src/uhci0/dma_in_suc_eof_des_addr.rs
index abe61f5f3b..16609609f4 100644
--- a/esp32s2/src/uhci0/dma_in_suc_eof_des_addr.rs
+++ b/esp32s2/src/uhci0/dma_in_suc_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_SUC_EOF_DES_ADDR")
-            .field(
-                "in_suc_eof_des_addr",
-                &format_args!("{}", self.in_suc_eof_des_addr().bits()),
-            )
+            .field("in_suc_eof_des_addr", &self.in_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_SUC_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Inlink descriptor address when EOF occurs\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_in_suc_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_IN_SUC_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for DMA_IN_SUC_EOF_DES_ADDR_SPEC {
diff --git a/esp32s2/src/uhci0/dma_out_dscr.rs b/esp32s2/src/uhci0/dma_out_dscr.rs
index f5197043cd..1fa1f3d5c5 100644
--- a/esp32s2/src/uhci0/dma_out_dscr.rs
+++ b/esp32s2/src/uhci0/dma_out_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_DSCR")
-            .field(
-                "outlink_dscr",
-                &format_args!("{}", self.outlink_dscr().bits()),
-            )
+            .field("outlink_dscr", &self.outlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The third word of the next transmit descriptor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_out_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_OUT_DSCR_SPEC;
 impl crate::RegisterSpec for DMA_OUT_DSCR_SPEC {
diff --git a/esp32s2/src/uhci0/dma_out_dscr_bf0.rs b/esp32s2/src/uhci0/dma_out_dscr_bf0.rs
index e71a0c5b24..60ddcf9f74 100644
--- a/esp32s2/src/uhci0/dma_out_dscr_bf0.rs
+++ b/esp32s2/src/uhci0/dma_out_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_DSCR_BF0")
-            .field(
-                "outlink_dscr_bf0",
-                &format_args!("{}", self.outlink_dscr_bf0().bits()),
-            )
+            .field("outlink_dscr_bf0", &self.outlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The third word of current transmit descriptor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_out_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_OUT_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for DMA_OUT_DSCR_BF0_SPEC {
diff --git a/esp32s2/src/uhci0/dma_out_eof_bfr_des_addr.rs b/esp32s2/src/uhci0/dma_out_eof_bfr_des_addr.rs
index 54e4b7af2a..7e2ba1e2ab 100644
--- a/esp32s2/src/uhci0/dma_out_eof_bfr_des_addr.rs
+++ b/esp32s2/src/uhci0/dma_out_eof_bfr_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_EOF_BFR_DES_ADDR")
-            .field(
-                "out_eof_bfr_des_addr",
-                &format_args!("{}", self.out_eof_bfr_des_addr().bits()),
-            )
+            .field("out_eof_bfr_des_addr", &self.out_eof_bfr_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_EOF_BFR_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Outlink descriptor address before the last transmit descriptor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_out_eof_bfr_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_OUT_EOF_BFR_DES_ADDR_SPEC;
 impl crate::RegisterSpec for DMA_OUT_EOF_BFR_DES_ADDR_SPEC {
diff --git a/esp32s2/src/uhci0/dma_out_eof_des_addr.rs b/esp32s2/src/uhci0/dma_out_eof_des_addr.rs
index 2b4f69b342..bf714e641a 100644
--- a/esp32s2/src/uhci0/dma_out_eof_des_addr.rs
+++ b/esp32s2/src/uhci0/dma_out_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_EOF_DES_ADDR")
-            .field(
-                "out_eof_des_addr",
-                &format_args!("{}", self.out_eof_des_addr().bits()),
-            )
+            .field("out_eof_des_addr", &self.out_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Outlink descriptor address when EOF occurs\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_out_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_OUT_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for DMA_OUT_EOF_DES_ADDR_SPEC {
diff --git a/esp32s2/src/uhci0/dma_out_link.rs b/esp32s2/src/uhci0/dma_out_link.rs
index 8965f64f88..0c20c132d4 100644
--- a/esp32s2/src/uhci0/dma_out_link.rs
+++ b/esp32s2/src/uhci0/dma_out_link.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_LINK")
-            .field(
-                "outlink_addr",
-                &format_args!("{}", self.outlink_addr().bits()),
-            )
-            .field(
-                "outlink_stop",
-                &format_args!("{}", self.outlink_stop().bit()),
-            )
-            .field(
-                "outlink_start",
-                &format_args!("{}", self.outlink_start().bit()),
-            )
-            .field(
-                "outlink_restart",
-                &format_args!("{}", self.outlink_restart().bit()),
-            )
-            .field(
-                "outlink_park",
-                &format_args!("{}", self.outlink_park().bit()),
-            )
+            .field("outlink_addr", &self.outlink_addr())
+            .field("outlink_stop", &self.outlink_stop())
+            .field("outlink_start", &self.outlink_start())
+            .field("outlink_restart", &self.outlink_restart())
+            .field("outlink_park", &self.outlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register is used to specify the least significant 20 bits of the first transmit descriptor's address."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/dma_out_push.rs b/esp32s2/src/uhci0/dma_out_push.rs
index 0e18137646..0c6174bec0 100644
--- a/esp32s2/src/uhci0/dma_out_push.rs
+++ b/esp32s2/src/uhci0/dma_out_push.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_PUSH")
-            .field(
-                "outfifo_wdata",
-                &format_args!("{}", self.outfifo_wdata().bits()),
-            )
-            .field(
-                "outfifo_push",
-                &format_args!("{}", self.outfifo_push().bit()),
-            )
+            .field("outfifo_wdata", &self.outfifo_wdata())
+            .field("outfifo_push", &self.outfifo_push())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_PUSH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This is the data that need to be pushed into TX FIFO."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/dma_out_status.rs b/esp32s2/src/uhci0/dma_out_status.rs
index 75ba8a903e..cfc2c1687c 100644
--- a/esp32s2/src/uhci0/dma_out_status.rs
+++ b/esp32s2/src/uhci0/dma_out_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_STATUS")
-            .field("out_full", &format_args!("{}", self.out_full().bit()))
-            .field("out_empty", &format_args!("{}", self.out_empty().bit()))
+            .field("out_full", &self.out_full())
+            .field("out_empty", &self.out_empty())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "DMA data-output status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_out_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_OUT_STATUS_SPEC;
 impl crate::RegisterSpec for DMA_OUT_STATUS_SPEC {
diff --git a/esp32s2/src/uhci0/esc_conf.rs b/esp32s2/src/uhci0/esc_conf.rs
index fcfb4e1c42..33c2bb2bd1 100644
--- a/esp32s2/src/uhci0/esc_conf.rs
+++ b/esp32s2/src/uhci0/esc_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ESC_CONF")
-            .field("seper_char", &format_args!("{}", self.seper_char().bits()))
-            .field(
-                "seper_esc_char0",
-                &format_args!("{}", self.seper_esc_char0().bits()),
-            )
-            .field(
-                "seper_esc_char1",
-                &format_args!("{}", self.seper_esc_char1().bits()),
-            )
+            .field("seper_char", &self.seper_char())
+            .field("seper_esc_char0", &self.seper_esc_char0())
+            .field("seper_esc_char1", &self.seper_esc_char1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ESC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to define separators to encode data packets. The default value is 0xC0."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/escape_conf.rs b/esp32s2/src/uhci0/escape_conf.rs
index 691d88c63e..8a56acaba3 100644
--- a/esp32s2/src/uhci0/escape_conf.rs
+++ b/esp32s2/src/uhci0/escape_conf.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ESCAPE_CONF")
-            .field(
-                "tx_c0_esc_en",
-                &format_args!("{}", self.tx_c0_esc_en().bit()),
-            )
-            .field(
-                "tx_db_esc_en",
-                &format_args!("{}", self.tx_db_esc_en().bit()),
-            )
-            .field(
-                "tx_11_esc_en",
-                &format_args!("{}", self.tx_11_esc_en().bit()),
-            )
-            .field(
-                "tx_13_esc_en",
-                &format_args!("{}", self.tx_13_esc_en().bit()),
-            )
-            .field(
-                "rx_c0_esc_en",
-                &format_args!("{}", self.rx_c0_esc_en().bit()),
-            )
-            .field(
-                "rx_db_esc_en",
-                &format_args!("{}", self.rx_db_esc_en().bit()),
-            )
-            .field(
-                "rx_11_esc_en",
-                &format_args!("{}", self.rx_11_esc_en().bit()),
-            )
-            .field(
-                "rx_13_esc_en",
-                &format_args!("{}", self.rx_13_esc_en().bit()),
-            )
+            .field("tx_c0_esc_en", &self.tx_c0_esc_en())
+            .field("tx_db_esc_en", &self.tx_db_esc_en())
+            .field("tx_11_esc_en", &self.tx_11_esc_en())
+            .field("tx_13_esc_en", &self.tx_13_esc_en())
+            .field("rx_c0_esc_en", &self.rx_c0_esc_en())
+            .field("rx_db_esc_en", &self.rx_db_esc_en())
+            .field("rx_11_esc_en", &self.rx_11_esc_en())
+            .field("rx_13_esc_en", &self.rx_13_esc_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ESCAPE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to decode character 0xC0 when DMA receives data."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/hung_conf.rs b/esp32s2/src/uhci0/hung_conf.rs
index 9043b948dc..3300f178dc 100644
--- a/esp32s2/src/uhci0/hung_conf.rs
+++ b/esp32s2/src/uhci0/hung_conf.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HUNG_CONF")
-            .field(
-                "txfifo_timeout",
-                &format_args!("{}", self.txfifo_timeout().bits()),
-            )
-            .field(
-                "txfifo_timeout_shift",
-                &format_args!("{}", self.txfifo_timeout_shift().bits()),
-            )
-            .field(
-                "txfifo_timeout_ena",
-                &format_args!("{}", self.txfifo_timeout_ena().bit()),
-            )
-            .field(
-                "rxfifo_timeout",
-                &format_args!("{}", self.rxfifo_timeout().bits()),
-            )
-            .field(
-                "rxfifo_timeout_shift",
-                &format_args!("{}", self.rxfifo_timeout_shift().bits()),
-            )
-            .field(
-                "rxfifo_timeout_ena",
-                &format_args!("{}", self.rxfifo_timeout_ena().bit()),
-            )
+            .field("txfifo_timeout", &self.txfifo_timeout())
+            .field("txfifo_timeout_shift", &self.txfifo_timeout_shift())
+            .field("txfifo_timeout_ena", &self.txfifo_timeout_ena())
+            .field("rxfifo_timeout", &self.rxfifo_timeout())
+            .field("rxfifo_timeout_shift", &self.rxfifo_timeout_shift())
+            .field("rxfifo_timeout_ena", &self.rxfifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register stores the timeout value. UHCI produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/int_ena.rs b/esp32s2/src/uhci0/int_ena.rs
index 5660ce7f81..4959c12492 100644
--- a/esp32s2/src/uhci0/int_ena.rs
+++ b/esp32s2/src/uhci0/int_ena.rs
@@ -161,53 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field(
-                "dma_infifo_full_wm",
-                &format_args!("{}", self.dma_infifo_full_wm().bit()),
-            )
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("dma_infifo_full_wm", &self.dma_infifo_full_wm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the interrupt enable bit for UHCI_RX_START_INT interrupt."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/int_raw.rs b/esp32s2/src/uhci0/int_raw.rs
index 9ae4a41712..c4043deda1 100644
--- a/esp32s2/src/uhci0/int_raw.rs
+++ b/esp32s2/src/uhci0/int_raw.rs
@@ -125,53 +125,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field(
-                "dma_infifo_full_wm",
-                &format_args!("{}", self.dma_infifo_full_wm().bit()),
-            )
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("dma_infifo_full_wm", &self.dma_infifo_full_wm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s2/src/uhci0/int_st.rs b/esp32s2/src/uhci0/int_st.rs
index 633a9c7ce1..c79cb5fccf 100644
--- a/esp32s2/src/uhci0/int_st.rs
+++ b/esp32s2/src/uhci0/int_st.rs
@@ -125,53 +125,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field(
-                "dma_infifo_full_wm",
-                &format_args!("{}", self.dma_infifo_full_wm().bit()),
-            )
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("dma_infifo_full_wm", &self.dma_infifo_full_wm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s2/src/uhci0/pkt_thres.rs b/esp32s2/src/uhci0/pkt_thres.rs
index 0a08867ec8..cf9182db51 100644
--- a/esp32s2/src/uhci0/pkt_thres.rs
+++ b/esp32s2/src/uhci0/pkt_thres.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PKT_THRES")
-            .field("pkt_thrs", &format_args!("{}", self.pkt_thrs().bits()))
+            .field("pkt_thrs", &self.pkt_thrs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PKT_THRES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/q/word0.rs b/esp32s2/src/uhci0/q/word0.rs
index d038576e41..77fcf14df1 100644
--- a/esp32s2/src/uhci0/q/word0.rs
+++ b/esp32s2/src/uhci0/q/word0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WORD0")
-            .field("send_word", &format_args!("{}", self.send_word().bits()))
+            .field("send_word", &self.send_word())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WORD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/q/word1.rs b/esp32s2/src/uhci0/q/word1.rs
index 93c952a3cc..50dc74414c 100644
--- a/esp32s2/src/uhci0/q/word1.rs
+++ b/esp32s2/src/uhci0/q/word1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WORD1")
-            .field("send_word", &format_args!("{}", self.send_word().bits()))
+            .field("send_word", &self.send_word())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WORD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/quick_sent.rs b/esp32s2/src/uhci0/quick_sent.rs
index 5ac2ca551e..9273d189a5 100644
--- a/esp32s2/src/uhci0/quick_sent.rs
+++ b/esp32s2/src/uhci0/quick_sent.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUICK_SENT")
-            .field(
-                "single_send_num",
-                &format_args!("{}", self.single_send_num().bits()),
-            )
-            .field(
-                "single_send_en",
-                &format_args!("{}", self.single_send_en().bit()),
-            )
-            .field(
-                "always_send_num",
-                &format_args!("{}", self.always_send_num().bits()),
-            )
-            .field(
-                "always_send_en",
-                &format_args!("{}", self.always_send_en().bit()),
-            )
+            .field("single_send_num", &self.single_send_num())
+            .field("single_send_en", &self.single_send_en())
+            .field("always_send_num", &self.always_send_num())
+            .field("always_send_en", &self.always_send_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUICK_SENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - This register is used to specify the single_send mode."]
     #[inline(always)]
diff --git a/esp32s2/src/uhci0/rx_head.rs b/esp32s2/src/uhci0/rx_head.rs
index 1c81ed7160..542138c109 100644
--- a/esp32s2/src/uhci0/rx_head.rs
+++ b/esp32s2/src/uhci0/rx_head.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_HEAD")
-            .field("rx_head", &format_args!("{}", self.rx_head().bits()))
+            .field("rx_head", &self.rx_head())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_HEAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UHCI packet header register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_head::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_HEAD_SPEC;
 impl crate::RegisterSpec for RX_HEAD_SPEC {
diff --git a/esp32s2/src/uhci0/state0.rs b/esp32s2/src/uhci0/state0.rs
index 1671984e47..c65e5df1f3 100644
--- a/esp32s2/src/uhci0/state0.rs
+++ b/esp32s2/src/uhci0/state0.rs
@@ -41,32 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE0")
-            .field(
-                "inlink_dscr_addr",
-                &format_args!("{}", self.inlink_dscr_addr().bits()),
-            )
-            .field(
-                "in_dscr_state",
-                &format_args!("{}", self.in_dscr_state().bits()),
-            )
-            .field("in_state", &format_args!("{}", self.in_state().bits()))
-            .field(
-                "infifo_cnt_debug",
-                &format_args!("{}", self.infifo_cnt_debug().bits()),
-            )
-            .field(
-                "decode_state",
-                &format_args!("{}", self.decode_state().bits()),
-            )
+            .field("inlink_dscr_addr", &self.inlink_dscr_addr())
+            .field("in_dscr_state", &self.in_dscr_state())
+            .field("in_state", &self.in_state())
+            .field("infifo_cnt_debug", &self.infifo_cnt_debug())
+            .field("decode_state", &self.decode_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UHCI decoder status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE0_SPEC;
 impl crate::RegisterSpec for STATE0_SPEC {
diff --git a/esp32s2/src/uhci0/state1.rs b/esp32s2/src/uhci0/state1.rs
index 8897addb8f..f5e30669c7 100644
--- a/esp32s2/src/uhci0/state1.rs
+++ b/esp32s2/src/uhci0/state1.rs
@@ -41,32 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE1")
-            .field(
-                "outlink_dscr_addr",
-                &format_args!("{}", self.outlink_dscr_addr().bits()),
-            )
-            .field(
-                "out_dscr_state",
-                &format_args!("{}", self.out_dscr_state().bits()),
-            )
-            .field("out_state", &format_args!("{}", self.out_state().bits()))
-            .field(
-                "outfifo_cnt",
-                &format_args!("{}", self.outfifo_cnt().bits()),
-            )
-            .field(
-                "encode_state",
-                &format_args!("{}", self.encode_state().bits()),
-            )
+            .field("outlink_dscr_addr", &self.outlink_dscr_addr())
+            .field("out_dscr_state", &self.out_dscr_state())
+            .field("out_state", &self.out_state())
+            .field("outfifo_cnt", &self.outfifo_cnt())
+            .field("encode_state", &self.encode_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UHCI encoder status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE1_SPEC;
 impl crate::RegisterSpec for STATE1_SPEC {
diff --git a/esp32s2/src/usb0/daint.rs b/esp32s2/src/usb0/daint.rs
index 62d3956527..6d187f18e4 100644
--- a/esp32s2/src/usb0/daint.rs
+++ b/esp32s2/src/usb0/daint.rs
@@ -110,29 +110,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DAINT")
-            .field("inepint0", &format_args!("{}", self.inepint0().bit()))
-            .field("inepint1", &format_args!("{}", self.inepint1().bit()))
-            .field("inepint2", &format_args!("{}", self.inepint2().bit()))
-            .field("inepint3", &format_args!("{}", self.inepint3().bit()))
-            .field("inepint4", &format_args!("{}", self.inepint4().bit()))
-            .field("inepint5", &format_args!("{}", self.inepint5().bit()))
-            .field("inepint6", &format_args!("{}", self.inepint6().bit()))
-            .field("outepint0", &format_args!("{}", self.outepint0().bit()))
-            .field("outepint1", &format_args!("{}", self.outepint1().bit()))
-            .field("outepint2", &format_args!("{}", self.outepint2().bit()))
-            .field("outepint3", &format_args!("{}", self.outepint3().bit()))
-            .field("outepint4", &format_args!("{}", self.outepint4().bit()))
-            .field("outepint5", &format_args!("{}", self.outepint5().bit()))
-            .field("outepint6", &format_args!("{}", self.outepint6().bit()))
+            .field("inepint0", &self.inepint0())
+            .field("inepint1", &self.inepint1())
+            .field("inepint2", &self.inepint2())
+            .field("inepint3", &self.inepint3())
+            .field("inepint4", &self.inepint4())
+            .field("inepint5", &self.inepint5())
+            .field("inepint6", &self.inepint6())
+            .field("outepint0", &self.outepint0())
+            .field("outepint1", &self.outepint1())
+            .field("outepint2", &self.outepint2())
+            .field("outepint3", &self.outepint3())
+            .field("outepint4", &self.outepint4())
+            .field("outepint5", &self.outepint5())
+            .field("outepint6", &self.outepint6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DAINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daint::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DAINT_SPEC;
 impl crate::RegisterSpec for DAINT_SPEC {
diff --git a/esp32s2/src/usb0/daintmsk.rs b/esp32s2/src/usb0/daintmsk.rs
index f530c27202..57cfb41e8e 100644
--- a/esp32s2/src/usb0/daintmsk.rs
+++ b/esp32s2/src/usb0/daintmsk.rs
@@ -116,29 +116,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DAINTMSK")
-            .field("inepmsk0", &format_args!("{}", self.inepmsk0().bit()))
-            .field("inepmsk1", &format_args!("{}", self.inepmsk1().bit()))
-            .field("inepmsk2", &format_args!("{}", self.inepmsk2().bit()))
-            .field("inepmsk3", &format_args!("{}", self.inepmsk3().bit()))
-            .field("inepmsk4", &format_args!("{}", self.inepmsk4().bit()))
-            .field("inepmsk5", &format_args!("{}", self.inepmsk5().bit()))
-            .field("inepmsk6", &format_args!("{}", self.inepmsk6().bit()))
-            .field("outepmsk0", &format_args!("{}", self.outepmsk0().bit()))
-            .field("outepmsk1", &format_args!("{}", self.outepmsk1().bit()))
-            .field("outepmsk2", &format_args!("{}", self.outepmsk2().bit()))
-            .field("outepmsk3", &format_args!("{}", self.outepmsk3().bit()))
-            .field("outepmsk4", &format_args!("{}", self.outepmsk4().bit()))
-            .field("outepmsk5", &format_args!("{}", self.outepmsk5().bit()))
-            .field("outepmsk6", &format_args!("{}", self.outepmsk6().bit()))
+            .field("inepmsk0", &self.inepmsk0())
+            .field("inepmsk1", &self.inepmsk1())
+            .field("inepmsk2", &self.inepmsk2())
+            .field("inepmsk3", &self.inepmsk3())
+            .field("inepmsk4", &self.inepmsk4())
+            .field("inepmsk5", &self.inepmsk5())
+            .field("inepmsk6", &self.inepmsk6())
+            .field("outepmsk0", &self.outepmsk0())
+            .field("outepmsk1", &self.outepmsk1())
+            .field("outepmsk2", &self.outepmsk2())
+            .field("outepmsk3", &self.outepmsk3())
+            .field("outepmsk4", &self.outepmsk4())
+            .field("outepmsk5", &self.outepmsk5())
+            .field("outepmsk6", &self.outepmsk6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DAINTMSK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = ""]
     #[doc = ""]
diff --git a/esp32s2/src/usb0/dcfg.rs b/esp32s2/src/usb0/dcfg.rs
index df1d9baf2c..4d7349ec3a 100644
--- a/esp32s2/src/usb0/dcfg.rs
+++ b/esp32s2/src/usb0/dcfg.rs
@@ -107,38 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCFG")
-            .field(
-                "nzstsouthshk",
-                &format_args!("{}", self.nzstsouthshk().bit()),
-            )
-            .field(
-                "ena32khzsusp",
-                &format_args!("{}", self.ena32khzsusp().bit()),
-            )
-            .field("devaddr", &format_args!("{}", self.devaddr().bits()))
-            .field("perfrlint", &format_args!("{}", self.perfrlint().bits()))
-            .field("endevoutnak", &format_args!("{}", self.endevoutnak().bit()))
-            .field("xcvrdly", &format_args!("{}", self.xcvrdly().bit()))
-            .field(
-                "erraticintmsk",
-                &format_args!("{}", self.erraticintmsk().bit()),
-            )
-            .field("epmiscnt", &format_args!("{}", self.epmiscnt().bits()))
-            .field("descdma", &format_args!("{}", self.descdma().bit()))
-            .field(
-                "perschintvl",
-                &format_args!("{}", self.perschintvl().bits()),
-            )
-            .field("resvalid", &format_args!("{}", self.resvalid().bits()))
+            .field("nzstsouthshk", &self.nzstsouthshk())
+            .field("ena32khzsusp", &self.ena32khzsusp())
+            .field("devaddr", &self.devaddr())
+            .field("perfrlint", &self.perfrlint())
+            .field("endevoutnak", &self.endevoutnak())
+            .field("xcvrdly", &self.xcvrdly())
+            .field("erraticintmsk", &self.erraticintmsk())
+            .field("epmiscnt", &self.epmiscnt())
+            .field("descdma", &self.descdma())
+            .field("perschintvl", &self.perschintvl())
+            .field("resvalid", &self.resvalid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/dctl.rs b/esp32s2/src/usb0/dctl.rs
index dd527c4fc7..0c0b2b51f8 100644
--- a/esp32s2/src/usb0/dctl.rs
+++ b/esp32s2/src/usb0/dctl.rs
@@ -111,35 +111,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCTL")
-            .field("rmtwkupsig", &format_args!("{}", self.rmtwkupsig().bit()))
-            .field("sftdiscon", &format_args!("{}", self.sftdiscon().bit()))
-            .field("gnpinnaksts", &format_args!("{}", self.gnpinnaksts().bit()))
-            .field("goutnaksts", &format_args!("{}", self.goutnaksts().bit()))
-            .field("tstctl", &format_args!("{}", self.tstctl().bits()))
-            .field(
-                "pwronprgdone",
-                &format_args!("{}", self.pwronprgdone().bit()),
-            )
-            .field("gmc", &format_args!("{}", self.gmc().bits()))
-            .field("ignrfrmnum", &format_args!("{}", self.ignrfrmnum().bit()))
-            .field("nakonbble", &format_args!("{}", self.nakonbble().bit()))
-            .field(
-                "encountonbna",
-                &format_args!("{}", self.encountonbna().bit()),
-            )
-            .field(
-                "deepsleepbeslreject",
-                &format_args!("{}", self.deepsleepbeslreject().bit()),
-            )
+            .field("rmtwkupsig", &self.rmtwkupsig())
+            .field("sftdiscon", &self.sftdiscon())
+            .field("gnpinnaksts", &self.gnpinnaksts())
+            .field("goutnaksts", &self.goutnaksts())
+            .field("tstctl", &self.tstctl())
+            .field("pwronprgdone", &self.pwronprgdone())
+            .field("gmc", &self.gmc())
+            .field("ignrfrmnum", &self.ignrfrmnum())
+            .field("nakonbble", &self.nakonbble())
+            .field("encountonbna", &self.encountonbna())
+            .field("deepsleepbeslreject", &self.deepsleepbeslreject())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/diepempmsk.rs b/esp32s2/src/usb0/diepempmsk.rs
index 7511976134..d3c7e51a30 100644
--- a/esp32s2/src/usb0/diepempmsk.rs
+++ b/esp32s2/src/usb0/diepempmsk.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPEMPMSK")
-            .field(
-                "d_ineptxfempmsk",
-                &format_args!("{}", self.d_ineptxfempmsk().bits()),
-            )
+            .field("d_ineptxfempmsk", &self.d_ineptxfempmsk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPEMPMSK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/diepmsk.rs b/esp32s2/src/usb0/diepmsk.rs
index 07e50f8055..ca6f48aac3 100644
--- a/esp32s2/src/usb0/diepmsk.rs
+++ b/esp32s2/src/usb0/diepmsk.rs
@@ -98,46 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPMSK")
-            .field(
-                "di_xfercomplmsk",
-                &format_args!("{}", self.di_xfercomplmsk().bit()),
-            )
-            .field(
-                "di_epdisbldmsk",
-                &format_args!("{}", self.di_epdisbldmsk().bit()),
-            )
-            .field("di_ahbermsk", &format_args!("{}", self.di_ahbermsk().bit()))
-            .field("timeoutmsk", &format_args!("{}", self.timeoutmsk().bit()))
-            .field(
-                "intkntxfempmsk",
-                &format_args!("{}", self.intkntxfempmsk().bit()),
-            )
-            .field(
-                "intknepmismsk",
-                &format_args!("{}", self.intknepmismsk().bit()),
-            )
-            .field(
-                "inepnakeffmsk",
-                &format_args!("{}", self.inepnakeffmsk().bit()),
-            )
-            .field(
-                "txfifoundrnmsk",
-                &format_args!("{}", self.txfifoundrnmsk().bit()),
-            )
-            .field(
-                "bnainintrmsk",
-                &format_args!("{}", self.bnainintrmsk().bit()),
-            )
-            .field("di_nakmsk", &format_args!("{}", self.di_nakmsk().bit()))
+            .field("di_xfercomplmsk", &self.di_xfercomplmsk())
+            .field("di_epdisbldmsk", &self.di_epdisbldmsk())
+            .field("di_ahbermsk", &self.di_ahbermsk())
+            .field("timeoutmsk", &self.timeoutmsk())
+            .field("intkntxfempmsk", &self.intkntxfempmsk())
+            .field("intknepmismsk", &self.intknepmismsk())
+            .field("inepnakeffmsk", &self.inepnakeffmsk())
+            .field("txfifoundrnmsk", &self.txfifoundrnmsk())
+            .field("bnainintrmsk", &self.bnainintrmsk())
+            .field("di_nakmsk", &self.di_nakmsk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPMSK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/dieptxf.rs b/esp32s2/src/usb0/dieptxf.rs
index 2c143bd966..25d668c83a 100644
--- a/esp32s2/src/usb0/dieptxf.rs
+++ b/esp32s2/src/usb0/dieptxf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPTXF")
-            .field(
-                "inep1txfstaddr",
-                &format_args!("{}", self.inep1txfstaddr().bits()),
-            )
-            .field(
-                "inep1txfdep",
-                &format_args!("{}", self.inep1txfdep().bits()),
-            )
+            .field("inep1txfstaddr", &self.inep1txfstaddr())
+            .field("inep1txfdep", &self.inep1txfdep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPTXF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/doepmsk.rs b/esp32s2/src/usb0/doepmsk.rs
index 0a148f6608..b41015df11 100644
--- a/esp32s2/src/usb0/doepmsk.rs
+++ b/esp32s2/src/usb0/doepmsk.rs
@@ -116,45 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPMSK")
-            .field(
-                "xfercomplmsk",
-                &format_args!("{}", self.xfercomplmsk().bit()),
-            )
-            .field("epdisbldmsk", &format_args!("{}", self.epdisbldmsk().bit()))
-            .field("ahbermsk", &format_args!("{}", self.ahbermsk().bit()))
-            .field("setupmsk", &format_args!("{}", self.setupmsk().bit()))
-            .field(
-                "outtknepdismsk",
-                &format_args!("{}", self.outtknepdismsk().bit()),
-            )
-            .field(
-                "stsphsercvdmsk",
-                &format_args!("{}", self.stsphsercvdmsk().bit()),
-            )
-            .field(
-                "back2backsetup",
-                &format_args!("{}", self.back2backsetup().bit()),
-            )
-            .field(
-                "outpkterrmsk",
-                &format_args!("{}", self.outpkterrmsk().bit()),
-            )
-            .field(
-                "bnaoutintrmsk",
-                &format_args!("{}", self.bnaoutintrmsk().bit()),
-            )
-            .field("bbleerrmsk", &format_args!("{}", self.bbleerrmsk().bit()))
-            .field("nakmsk", &format_args!("{}", self.nakmsk().bit()))
-            .field("nyetmsk", &format_args!("{}", self.nyetmsk().bit()))
+            .field("xfercomplmsk", &self.xfercomplmsk())
+            .field("epdisbldmsk", &self.epdisbldmsk())
+            .field("ahbermsk", &self.ahbermsk())
+            .field("setupmsk", &self.setupmsk())
+            .field("outtknepdismsk", &self.outtknepdismsk())
+            .field("stsphsercvdmsk", &self.stsphsercvdmsk())
+            .field("back2backsetup", &self.back2backsetup())
+            .field("outpkterrmsk", &self.outpkterrmsk())
+            .field("bnaoutintrmsk", &self.bnaoutintrmsk())
+            .field("bbleerrmsk", &self.bbleerrmsk())
+            .field("nakmsk", &self.nakmsk())
+            .field("nyetmsk", &self.nyetmsk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPMSK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/dsts.rs b/esp32s2/src/usb0/dsts.rs
index 08cb678d74..6827ae6640 100644
--- a/esp32s2/src/usb0/dsts.rs
+++ b/esp32s2/src/usb0/dsts.rs
@@ -41,20 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSTS")
-            .field("suspsts", &format_args!("{}", self.suspsts().bit()))
-            .field("enumspd", &format_args!("{}", self.enumspd().bits()))
-            .field("errticerr", &format_args!("{}", self.errticerr().bit()))
-            .field("soffn", &format_args!("{}", self.soffn().bits()))
-            .field("devlnsts", &format_args!("{}", self.devlnsts().bits()))
+            .field("suspsts", &self.suspsts())
+            .field("enumspd", &self.enumspd())
+            .field("errticerr", &self.errticerr())
+            .field("soffn", &self.soffn())
+            .field("devlnsts", &self.devlnsts())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsts::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DSTS_SPEC;
 impl crate::RegisterSpec for DSTS_SPEC {
diff --git a/esp32s2/src/usb0/dthrctl.rs b/esp32s2/src/usb0/dthrctl.rs
index ad2ea373b4..af8212cee7 100644
--- a/esp32s2/src/usb0/dthrctl.rs
+++ b/esp32s2/src/usb0/dthrctl.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DTHRCTL")
-            .field("nonisothren", &format_args!("{}", self.nonisothren().bit()))
-            .field("isothren", &format_args!("{}", self.isothren().bit()))
-            .field("txthrlen", &format_args!("{}", self.txthrlen().bits()))
-            .field(
-                "ahbthrratio",
-                &format_args!("{}", self.ahbthrratio().bits()),
-            )
-            .field("rxthren", &format_args!("{}", self.rxthren().bit()))
-            .field("rxthrlen", &format_args!("{}", self.rxthrlen().bits()))
-            .field("arbprken", &format_args!("{}", self.arbprken().bit()))
+            .field("nonisothren", &self.nonisothren())
+            .field("isothren", &self.isothren())
+            .field("txthrlen", &self.txthrlen())
+            .field("ahbthrratio", &self.ahbthrratio())
+            .field("rxthren", &self.rxthren())
+            .field("rxthrlen", &self.rxthrlen())
+            .field("arbprken", &self.arbprken())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DTHRCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/dvbusdis.rs b/esp32s2/src/usb0/dvbusdis.rs
index 59a12d26ad..dc11f505a8 100644
--- a/esp32s2/src/usb0/dvbusdis.rs
+++ b/esp32s2/src/usb0/dvbusdis.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DVBUSDIS")
-            .field("dvbusdis", &format_args!("{}", self.dvbusdis().bits()))
+            .field("dvbusdis", &self.dvbusdis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DVBUSDIS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/dvbuspulse.rs b/esp32s2/src/usb0/dvbuspulse.rs
index 946c9aafd7..ab2eb101bf 100644
--- a/esp32s2/src/usb0/dvbuspulse.rs
+++ b/esp32s2/src/usb0/dvbuspulse.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DVBUSPULSE")
-            .field("dvbuspulse", &format_args!("{}", self.dvbuspulse().bits()))
+            .field("dvbuspulse", &self.dvbuspulse())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DVBUSPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/fifo.rs b/esp32s2/src/usb0/fifo.rs
index 9fc2d6e4c7..3c8c2acd66 100644
--- a/esp32s2/src/usb0/fifo.rs
+++ b/esp32s2/src/usb0/fifo.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("FIFO")
-            .field("word", &format_args!("{}", self.word().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("FIFO").field("word", &self.word()).finish()
     }
 }
 impl W {
diff --git a/esp32s2/src/usb0/gahbcfg.rs b/esp32s2/src/usb0/gahbcfg.rs
index 8bb6e7d2ed..a32afaaae7 100644
--- a/esp32s2/src/usb0/gahbcfg.rs
+++ b/esp32s2/src/usb0/gahbcfg.rs
@@ -89,30 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAHBCFG")
-            .field("glbllntrmsk", &format_args!("{}", self.glbllntrmsk().bit()))
-            .field("hbstlen", &format_args!("{}", self.hbstlen().bits()))
-            .field("dmaen", &format_args!("{}", self.dmaen().bit()))
-            .field("nptxfemplvl", &format_args!("{}", self.nptxfemplvl().bit()))
-            .field("ptxfemplvl", &format_args!("{}", self.ptxfemplvl().bit()))
-            .field("remmemsupp", &format_args!("{}", self.remmemsupp().bit()))
-            .field(
-                "notialldmawrit",
-                &format_args!("{}", self.notialldmawrit().bit()),
-            )
-            .field("ahbsingle", &format_args!("{}", self.ahbsingle().bit()))
-            .field(
-                "invdescendianess",
-                &format_args!("{}", self.invdescendianess().bit()),
-            )
+            .field("glbllntrmsk", &self.glbllntrmsk())
+            .field("hbstlen", &self.hbstlen())
+            .field("dmaen", &self.dmaen())
+            .field("nptxfemplvl", &self.nptxfemplvl())
+            .field("ptxfemplvl", &self.ptxfemplvl())
+            .field("remmemsupp", &self.remmemsupp())
+            .field("notialldmawrit", &self.notialldmawrit())
+            .field("ahbsingle", &self.ahbsingle())
+            .field("invdescendianess", &self.invdescendianess())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAHBCFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/gdfifocfg.rs b/esp32s2/src/usb0/gdfifocfg.rs
index d043bb7169..889b0d9e2e 100644
--- a/esp32s2/src/usb0/gdfifocfg.rs
+++ b/esp32s2/src/usb0/gdfifocfg.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GDFIFOCFG")
-            .field("gdfifocfg", &format_args!("{}", self.gdfifocfg().bits()))
-            .field(
-                "epinfobaseaddr",
-                &format_args!("{}", self.epinfobaseaddr().bits()),
-            )
+            .field("gdfifocfg", &self.gdfifocfg())
+            .field("epinfobaseaddr", &self.epinfobaseaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GDFIFOCFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/ghwcfg1.rs b/esp32s2/src/usb0/ghwcfg1.rs
index 2bac61c23d..e152bb4b40 100644
--- a/esp32s2/src/usb0/ghwcfg1.rs
+++ b/esp32s2/src/usb0/ghwcfg1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GHWCFG1")
-            .field("epdir", &format_args!("{}", self.epdir().bits()))
+            .field("epdir", &self.epdir())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GHWCFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ghwcfg1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GHWCFG1_SPEC;
 impl crate::RegisterSpec for GHWCFG1_SPEC {
diff --git a/esp32s2/src/usb0/ghwcfg2.rs b/esp32s2/src/usb0/ghwcfg2.rs
index cdd8edf116..c6d0e0043f 100644
--- a/esp32s2/src/usb0/ghwcfg2.rs
+++ b/esp32s2/src/usb0/ghwcfg2.rs
@@ -104,41 +104,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GHWCFG2")
-            .field("otgmode", &format_args!("{}", self.otgmode().bits()))
-            .field("otgarch", &format_args!("{}", self.otgarch().bits()))
-            .field("singpnt", &format_args!("{}", self.singpnt().bit()))
-            .field("hsphytype", &format_args!("{}", self.hsphytype().bits()))
-            .field("fsphytype", &format_args!("{}", self.fsphytype().bits()))
-            .field("numdeveps", &format_args!("{}", self.numdeveps().bits()))
-            .field("numhstchnl", &format_args!("{}", self.numhstchnl().bits()))
-            .field(
-                "periosupport",
-                &format_args!("{}", self.periosupport().bit()),
-            )
-            .field(
-                "dynfifosizing",
-                &format_args!("{}", self.dynfifosizing().bit()),
-            )
-            .field(
-                "multiprocintrpt",
-                &format_args!("{}", self.multiprocintrpt().bit()),
-            )
-            .field("nptxqdepth", &format_args!("{}", self.nptxqdepth().bits()))
-            .field("ptxqdepth", &format_args!("{}", self.ptxqdepth().bits()))
-            .field("tknqdepth", &format_args!("{}", self.tknqdepth().bits()))
-            .field(
-                "otg_enable_ic_usb",
-                &format_args!("{}", self.otg_enable_ic_usb().bit()),
-            )
+            .field("otgmode", &self.otgmode())
+            .field("otgarch", &self.otgarch())
+            .field("singpnt", &self.singpnt())
+            .field("hsphytype", &self.hsphytype())
+            .field("fsphytype", &self.fsphytype())
+            .field("numdeveps", &self.numdeveps())
+            .field("numhstchnl", &self.numhstchnl())
+            .field("periosupport", &self.periosupport())
+            .field("dynfifosizing", &self.dynfifosizing())
+            .field("multiprocintrpt", &self.multiprocintrpt())
+            .field("nptxqdepth", &self.nptxqdepth())
+            .field("ptxqdepth", &self.ptxqdepth())
+            .field("tknqdepth", &self.tknqdepth())
+            .field("otg_enable_ic_usb", &self.otg_enable_ic_usb())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GHWCFG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ghwcfg2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GHWCFG2_SPEC;
 impl crate::RegisterSpec for GHWCFG2_SPEC {
diff --git a/esp32s2/src/usb0/ghwcfg3.rs b/esp32s2/src/usb0/ghwcfg3.rs
index 01c36421d2..308a4745de 100644
--- a/esp32s2/src/usb0/ghwcfg3.rs
+++ b/esp32s2/src/usb0/ghwcfg3.rs
@@ -90,33 +90,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GHWCFG3")
-            .field(
-                "xfersizewidth",
-                &format_args!("{}", self.xfersizewidth().bits()),
-            )
-            .field(
-                "pktsizewidth",
-                &format_args!("{}", self.pktsizewidth().bits()),
-            )
-            .field("otgen", &format_args!("{}", self.otgen().bit()))
-            .field("i2cintsel", &format_args!("{}", self.i2cintsel().bit()))
-            .field("vndctlsupt", &format_args!("{}", self.vndctlsupt().bit()))
-            .field("optfeature", &format_args!("{}", self.optfeature().bit()))
-            .field("rsttype", &format_args!("{}", self.rsttype().bit()))
-            .field("adpsupport", &format_args!("{}", self.adpsupport().bit()))
-            .field("hsicmode", &format_args!("{}", self.hsicmode().bit()))
-            .field("bcsupport", &format_args!("{}", self.bcsupport().bit()))
-            .field("lpmmode", &format_args!("{}", self.lpmmode().bit()))
-            .field("dfifodepth", &format_args!("{}", self.dfifodepth().bits()))
+            .field("xfersizewidth", &self.xfersizewidth())
+            .field("pktsizewidth", &self.pktsizewidth())
+            .field("otgen", &self.otgen())
+            .field("i2cintsel", &self.i2cintsel())
+            .field("vndctlsupt", &self.vndctlsupt())
+            .field("optfeature", &self.optfeature())
+            .field("rsttype", &self.rsttype())
+            .field("adpsupport", &self.adpsupport())
+            .field("hsicmode", &self.hsicmode())
+            .field("bcsupport", &self.bcsupport())
+            .field("lpmmode", &self.lpmmode())
+            .field("dfifodepth", &self.dfifodepth())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GHWCFG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ghwcfg3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GHWCFG3_SPEC;
 impl crate::RegisterSpec for GHWCFG3_SPEC {
diff --git a/esp32s2/src/usb0/ghwcfg4.rs b/esp32s2/src/usb0/ghwcfg4.rs
index 806bbfd516..d1bc32ff09 100644
--- a/esp32s2/src/usb0/ghwcfg4.rs
+++ b/esp32s2/src/usb0/ghwcfg4.rs
@@ -132,72 +132,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GHWCFG4")
-            .field(
-                "g_numdevperioeps",
-                &format_args!("{}", self.g_numdevperioeps().bits()),
-            )
-            .field(
-                "g_partialpwrdn",
-                &format_args!("{}", self.g_partialpwrdn().bit()),
-            )
-            .field("g_ahbfreq", &format_args!("{}", self.g_ahbfreq().bit()))
-            .field(
-                "g_hibernation",
-                &format_args!("{}", self.g_hibernation().bit()),
-            )
-            .field(
-                "g_extendedhibernation",
-                &format_args!("{}", self.g_extendedhibernation().bit()),
-            )
-            .field("g_acgsupt", &format_args!("{}", self.g_acgsupt().bit()))
-            .field(
-                "g_enhancedlpmsupt",
-                &format_args!("{}", self.g_enhancedlpmsupt().bit()),
-            )
-            .field(
-                "g_phydatawidth",
-                &format_args!("{}", self.g_phydatawidth().bits()),
-            )
-            .field(
-                "g_numctleps",
-                &format_args!("{}", self.g_numctleps().bits()),
-            )
-            .field("g_iddqfltr", &format_args!("{}", self.g_iddqfltr().bit()))
-            .field(
-                "g_vbusvalidfltr",
-                &format_args!("{}", self.g_vbusvalidfltr().bit()),
-            )
-            .field(
-                "g_avalidfltr",
-                &format_args!("{}", self.g_avalidfltr().bit()),
-            )
-            .field(
-                "g_bvalidfltr",
-                &format_args!("{}", self.g_bvalidfltr().bit()),
-            )
-            .field(
-                "g_sessendfltr",
-                &format_args!("{}", self.g_sessendfltr().bit()),
-            )
-            .field(
-                "g_dedfifomode",
-                &format_args!("{}", self.g_dedfifomode().bit()),
-            )
-            .field("g_ineps", &format_args!("{}", self.g_ineps().bits()))
-            .field(
-                "g_descdmaenabled",
-                &format_args!("{}", self.g_descdmaenabled().bit()),
-            )
-            .field("g_descdma", &format_args!("{}", self.g_descdma().bit()))
+            .field("g_numdevperioeps", &self.g_numdevperioeps())
+            .field("g_partialpwrdn", &self.g_partialpwrdn())
+            .field("g_ahbfreq", &self.g_ahbfreq())
+            .field("g_hibernation", &self.g_hibernation())
+            .field("g_extendedhibernation", &self.g_extendedhibernation())
+            .field("g_acgsupt", &self.g_acgsupt())
+            .field("g_enhancedlpmsupt", &self.g_enhancedlpmsupt())
+            .field("g_phydatawidth", &self.g_phydatawidth())
+            .field("g_numctleps", &self.g_numctleps())
+            .field("g_iddqfltr", &self.g_iddqfltr())
+            .field("g_vbusvalidfltr", &self.g_vbusvalidfltr())
+            .field("g_avalidfltr", &self.g_avalidfltr())
+            .field("g_bvalidfltr", &self.g_bvalidfltr())
+            .field("g_sessendfltr", &self.g_sessendfltr())
+            .field("g_dedfifomode", &self.g_dedfifomode())
+            .field("g_ineps", &self.g_ineps())
+            .field("g_descdmaenabled", &self.g_descdmaenabled())
+            .field("g_descdma", &self.g_descdma())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GHWCFG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ghwcfg4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GHWCFG4_SPEC;
 impl crate::RegisterSpec for GHWCFG4_SPEC {
diff --git a/esp32s2/src/usb0/gintmsk.rs b/esp32s2/src/usb0/gintmsk.rs
index 1944be2246..d605948abf 100644
--- a/esp32s2/src/usb0/gintmsk.rs
+++ b/esp32s2/src/usb0/gintmsk.rs
@@ -251,63 +251,36 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GINTMSK")
-            .field("modemismsk", &format_args!("{}", self.modemismsk().bit()))
-            .field("otgintmsk", &format_args!("{}", self.otgintmsk().bit()))
-            .field("sofmsk", &format_args!("{}", self.sofmsk().bit()))
-            .field("rxflvimsk", &format_args!("{}", self.rxflvimsk().bit()))
-            .field("nptxfempmsk", &format_args!("{}", self.nptxfempmsk().bit()))
-            .field(
-                "ginnakeffmsk",
-                &format_args!("{}", self.ginnakeffmsk().bit()),
-            )
-            .field(
-                "goutnackeffmsk",
-                &format_args!("{}", self.goutnackeffmsk().bit()),
-            )
-            .field("erlysuspmsk", &format_args!("{}", self.erlysuspmsk().bit()))
-            .field("usbsuspmsk", &format_args!("{}", self.usbsuspmsk().bit()))
-            .field("usbrstmsk", &format_args!("{}", self.usbrstmsk().bit()))
-            .field("enumdonemsk", &format_args!("{}", self.enumdonemsk().bit()))
-            .field(
-                "isooutdropmsk",
-                &format_args!("{}", self.isooutdropmsk().bit()),
-            )
-            .field("eopfmsk", &format_args!("{}", self.eopfmsk().bit()))
-            .field("epmismsk", &format_args!("{}", self.epmismsk().bit()))
-            .field("iepintmsk", &format_args!("{}", self.iepintmsk().bit()))
-            .field("oepintmsk", &format_args!("{}", self.oepintmsk().bit()))
-            .field(
-                "incompisoinmsk",
-                &format_args!("{}", self.incompisoinmsk().bit()),
-            )
-            .field("incompipmsk", &format_args!("{}", self.incompipmsk().bit()))
-            .field("fetsuspmsk", &format_args!("{}", self.fetsuspmsk().bit()))
-            .field("resetdetmsk", &format_args!("{}", self.resetdetmsk().bit()))
-            .field("prtlntmsk", &format_args!("{}", self.prtlntmsk().bit()))
-            .field("hchintmsk", &format_args!("{}", self.hchintmsk().bit()))
-            .field("ptxfempmsk", &format_args!("{}", self.ptxfempmsk().bit()))
-            .field(
-                "conidstschngmsk",
-                &format_args!("{}", self.conidstschngmsk().bit()),
-            )
-            .field(
-                "disconnintmsk",
-                &format_args!("{}", self.disconnintmsk().bit()),
-            )
-            .field(
-                "sessreqintmsk",
-                &format_args!("{}", self.sessreqintmsk().bit()),
-            )
-            .field("wkupintmsk", &format_args!("{}", self.wkupintmsk().bit()))
+            .field("modemismsk", &self.modemismsk())
+            .field("otgintmsk", &self.otgintmsk())
+            .field("sofmsk", &self.sofmsk())
+            .field("rxflvimsk", &self.rxflvimsk())
+            .field("nptxfempmsk", &self.nptxfempmsk())
+            .field("ginnakeffmsk", &self.ginnakeffmsk())
+            .field("goutnackeffmsk", &self.goutnackeffmsk())
+            .field("erlysuspmsk", &self.erlysuspmsk())
+            .field("usbsuspmsk", &self.usbsuspmsk())
+            .field("usbrstmsk", &self.usbrstmsk())
+            .field("enumdonemsk", &self.enumdonemsk())
+            .field("isooutdropmsk", &self.isooutdropmsk())
+            .field("eopfmsk", &self.eopfmsk())
+            .field("epmismsk", &self.epmismsk())
+            .field("iepintmsk", &self.iepintmsk())
+            .field("oepintmsk", &self.oepintmsk())
+            .field("incompisoinmsk", &self.incompisoinmsk())
+            .field("incompipmsk", &self.incompipmsk())
+            .field("fetsuspmsk", &self.fetsuspmsk())
+            .field("resetdetmsk", &self.resetdetmsk())
+            .field("prtlntmsk", &self.prtlntmsk())
+            .field("hchintmsk", &self.hchintmsk())
+            .field("ptxfempmsk", &self.ptxfempmsk())
+            .field("conidstschngmsk", &self.conidstschngmsk())
+            .field("disconnintmsk", &self.disconnintmsk())
+            .field("sessreqintmsk", &self.sessreqintmsk())
+            .field("wkupintmsk", &self.wkupintmsk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GINTMSK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/gintsts.rs b/esp32s2/src/usb0/gintsts.rs
index 7407593bc9..a5c124bae3 100644
--- a/esp32s2/src/usb0/gintsts.rs
+++ b/esp32s2/src/usb0/gintsts.rs
@@ -238,46 +238,37 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GINTSTS")
-            .field("curmod_int", &format_args!("{}", self.curmod_int().bit()))
-            .field("modemis", &format_args!("{}", self.modemis().bit()))
-            .field("otgint", &format_args!("{}", self.otgint().bit()))
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field("rxflvi", &format_args!("{}", self.rxflvi().bit()))
-            .field("nptxfemp", &format_args!("{}", self.nptxfemp().bit()))
-            .field("ginnakeff", &format_args!("{}", self.ginnakeff().bit()))
-            .field("goutnakeff", &format_args!("{}", self.goutnakeff().bit()))
-            .field("erlysusp", &format_args!("{}", self.erlysusp().bit()))
-            .field("usbsusp", &format_args!("{}", self.usbsusp().bit()))
-            .field("usbrst", &format_args!("{}", self.usbrst().bit()))
-            .field("enumdone", &format_args!("{}", self.enumdone().bit()))
-            .field("isooutdrop", &format_args!("{}", self.isooutdrop().bit()))
-            .field("eopf", &format_args!("{}", self.eopf().bit()))
-            .field("epmis", &format_args!("{}", self.epmis().bit()))
-            .field("iepint", &format_args!("{}", self.iepint().bit()))
-            .field("oepint", &format_args!("{}", self.oepint().bit()))
-            .field("incompisoin", &format_args!("{}", self.incompisoin().bit()))
-            .field("incompip", &format_args!("{}", self.incompip().bit()))
-            .field("fetsusp", &format_args!("{}", self.fetsusp().bit()))
-            .field("resetdet", &format_args!("{}", self.resetdet().bit()))
-            .field("prtlnt", &format_args!("{}", self.prtlnt().bit()))
-            .field("hchlnt", &format_args!("{}", self.hchlnt().bit()))
-            .field("ptxfemp", &format_args!("{}", self.ptxfemp().bit()))
-            .field(
-                "conidstschng",
-                &format_args!("{}", self.conidstschng().bit()),
-            )
-            .field("disconnint", &format_args!("{}", self.disconnint().bit()))
-            .field("sessreqint", &format_args!("{}", self.sessreqint().bit()))
-            .field("wkupint", &format_args!("{}", self.wkupint().bit()))
+            .field("curmod_int", &self.curmod_int())
+            .field("modemis", &self.modemis())
+            .field("otgint", &self.otgint())
+            .field("sof", &self.sof())
+            .field("rxflvi", &self.rxflvi())
+            .field("nptxfemp", &self.nptxfemp())
+            .field("ginnakeff", &self.ginnakeff())
+            .field("goutnakeff", &self.goutnakeff())
+            .field("erlysusp", &self.erlysusp())
+            .field("usbsusp", &self.usbsusp())
+            .field("usbrst", &self.usbrst())
+            .field("enumdone", &self.enumdone())
+            .field("isooutdrop", &self.isooutdrop())
+            .field("eopf", &self.eopf())
+            .field("epmis", &self.epmis())
+            .field("iepint", &self.iepint())
+            .field("oepint", &self.oepint())
+            .field("incompisoin", &self.incompisoin())
+            .field("incompip", &self.incompip())
+            .field("fetsusp", &self.fetsusp())
+            .field("resetdet", &self.resetdet())
+            .field("prtlnt", &self.prtlnt())
+            .field("hchlnt", &self.hchlnt())
+            .field("ptxfemp", &self.ptxfemp())
+            .field("conidstschng", &self.conidstschng())
+            .field("disconnint", &self.disconnint())
+            .field("sessreqint", &self.sessreqint())
+            .field("wkupint", &self.wkupint())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GINTSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/gnptxfsiz.rs b/esp32s2/src/usb0/gnptxfsiz.rs
index b07f94ff21..992154236e 100644
--- a/esp32s2/src/usb0/gnptxfsiz.rs
+++ b/esp32s2/src/usb0/gnptxfsiz.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GNPTXFSIZ")
-            .field(
-                "nptxfstaddr",
-                &format_args!("{}", self.nptxfstaddr().bits()),
-            )
-            .field("nptxfdep", &format_args!("{}", self.nptxfdep().bits()))
+            .field("nptxfstaddr", &self.nptxfstaddr())
+            .field("nptxfdep", &self.nptxfdep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GNPTXFSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/gnptxsts.rs b/esp32s2/src/usb0/gnptxsts.rs
index 9caec58773..a270d09ce2 100644
--- a/esp32s2/src/usb0/gnptxsts.rs
+++ b/esp32s2/src/usb0/gnptxsts.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GNPTXSTS")
-            .field(
-                "nptxfspcavail",
-                &format_args!("{}", self.nptxfspcavail().bits()),
-            )
-            .field(
-                "nptxqspcavail",
-                &format_args!("{}", self.nptxqspcavail().bits()),
-            )
-            .field("nptxqtop", &format_args!("{}", self.nptxqtop().bits()))
+            .field("nptxfspcavail", &self.nptxfspcavail())
+            .field("nptxqspcavail", &self.nptxqspcavail())
+            .field("nptxqtop", &self.nptxqtop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GNPTXSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gnptxsts::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GNPTXSTS_SPEC;
 impl crate::RegisterSpec for GNPTXSTS_SPEC {
diff --git a/esp32s2/src/usb0/gotgctl.rs b/esp32s2/src/usb0/gotgctl.rs
index 7e773ded31..63c89dacfc 100644
--- a/esp32s2/src/usb0/gotgctl.rs
+++ b/esp32s2/src/usb0/gotgctl.rs
@@ -174,41 +174,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GOTGCTL")
-            .field("sesreqscs", &format_args!("{}", self.sesreqscs().bit()))
-            .field("sesreq", &format_args!("{}", self.sesreq().bit()))
-            .field("vbvalidoven", &format_args!("{}", self.vbvalidoven().bit()))
-            .field(
-                "vbvalidovval",
-                &format_args!("{}", self.vbvalidovval().bit()),
-            )
-            .field("avalidoven", &format_args!("{}", self.avalidoven().bit()))
-            .field("avalidovval", &format_args!("{}", self.avalidovval().bit()))
-            .field("bvalidoven", &format_args!("{}", self.bvalidoven().bit()))
-            .field("bvalidovval", &format_args!("{}", self.bvalidovval().bit()))
-            .field("hstnegscs", &format_args!("{}", self.hstnegscs().bit()))
-            .field("hnpreq", &format_args!("{}", self.hnpreq().bit()))
-            .field("hstsethnpen", &format_args!("{}", self.hstsethnpen().bit()))
-            .field("devhnpen", &format_args!("{}", self.devhnpen().bit()))
-            .field("ehen", &format_args!("{}", self.ehen().bit()))
-            .field(
-                "dbncefltrbypass",
-                &format_args!("{}", self.dbncefltrbypass().bit()),
-            )
-            .field("conidsts", &format_args!("{}", self.conidsts().bit()))
-            .field("dbnctime", &format_args!("{}", self.dbnctime().bit()))
-            .field("asesvld", &format_args!("{}", self.asesvld().bit()))
-            .field("bsesvld", &format_args!("{}", self.bsesvld().bit()))
-            .field("otgver", &format_args!("{}", self.otgver().bit()))
-            .field("curmod", &format_args!("{}", self.curmod().bit()))
+            .field("sesreqscs", &self.sesreqscs())
+            .field("sesreq", &self.sesreq())
+            .field("vbvalidoven", &self.vbvalidoven())
+            .field("vbvalidovval", &self.vbvalidovval())
+            .field("avalidoven", &self.avalidoven())
+            .field("avalidovval", &self.avalidovval())
+            .field("bvalidoven", &self.bvalidoven())
+            .field("bvalidovval", &self.bvalidovval())
+            .field("hstnegscs", &self.hstnegscs())
+            .field("hnpreq", &self.hnpreq())
+            .field("hstsethnpen", &self.hstsethnpen())
+            .field("devhnpen", &self.devhnpen())
+            .field("ehen", &self.ehen())
+            .field("dbncefltrbypass", &self.dbncefltrbypass())
+            .field("conidsts", &self.conidsts())
+            .field("dbnctime", &self.dbnctime())
+            .field("asesvld", &self.asesvld())
+            .field("bsesvld", &self.bsesvld())
+            .field("otgver", &self.otgver())
+            .field("curmod", &self.curmod())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GOTGCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/gotgint.rs b/esp32s2/src/usb0/gotgint.rs
index 20fe583b45..fa602368dd 100644
--- a/esp32s2/src/usb0/gotgint.rs
+++ b/esp32s2/src/usb0/gotgint.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GOTGINT")
-            .field("sesenddet", &format_args!("{}", self.sesenddet().bit()))
-            .field(
-                "sesreqsucstschng",
-                &format_args!("{}", self.sesreqsucstschng().bit()),
-            )
-            .field(
-                "hstnegsucstschng",
-                &format_args!("{}", self.hstnegsucstschng().bit()),
-            )
-            .field("hstnegdet", &format_args!("{}", self.hstnegdet().bit()))
-            .field("adevtoutchg", &format_args!("{}", self.adevtoutchg().bit()))
-            .field("dbncedone", &format_args!("{}", self.dbncedone().bit()))
+            .field("sesenddet", &self.sesenddet())
+            .field("sesreqsucstschng", &self.sesreqsucstschng())
+            .field("hstnegsucstschng", &self.hstnegsucstschng())
+            .field("hstnegdet", &self.hstnegdet())
+            .field("adevtoutchg", &self.adevtoutchg())
+            .field("dbncedone", &self.dbncedone())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GOTGINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/grstctl.rs b/esp32s2/src/usb0/grstctl.rs
index 7ededc6ce0..9ce5d1e957 100644
--- a/esp32s2/src/usb0/grstctl.rs
+++ b/esp32s2/src/usb0/grstctl.rs
@@ -76,23 +76,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GRSTCTL")
-            .field("csftrst", &format_args!("{}", self.csftrst().bit()))
-            .field("piufssftrst", &format_args!("{}", self.piufssftrst().bit()))
-            .field("frmcntrrst", &format_args!("{}", self.frmcntrrst().bit()))
-            .field("rxfflsh", &format_args!("{}", self.rxfflsh().bit()))
-            .field("txfflsh", &format_args!("{}", self.txfflsh().bit()))
-            .field("txfnum", &format_args!("{}", self.txfnum().bits()))
-            .field("dmareq", &format_args!("{}", self.dmareq().bit()))
-            .field("ahbidle", &format_args!("{}", self.ahbidle().bit()))
+            .field("csftrst", &self.csftrst())
+            .field("piufssftrst", &self.piufssftrst())
+            .field("frmcntrrst", &self.frmcntrrst())
+            .field("rxfflsh", &self.rxfflsh())
+            .field("txfflsh", &self.txfflsh())
+            .field("txfnum", &self.txfnum())
+            .field("dmareq", &self.dmareq())
+            .field("ahbidle", &self.ahbidle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GRSTCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/grxfsiz.rs b/esp32s2/src/usb0/grxfsiz.rs
index c2e6d7364b..6aae3678c2 100644
--- a/esp32s2/src/usb0/grxfsiz.rs
+++ b/esp32s2/src/usb0/grxfsiz.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GRXFSIZ")
-            .field("rxfdep", &format_args!("{}", self.rxfdep().bits()))
+            .field("rxfdep", &self.rxfdep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GRXFSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/grxstsp.rs b/esp32s2/src/usb0/grxstsp.rs
index 0fc8c2deab..de9e260051 100644
--- a/esp32s2/src/usb0/grxstsp.rs
+++ b/esp32s2/src/usb0/grxstsp.rs
@@ -41,20 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GRXSTSP")
-            .field("chnum", &format_args!("{}", self.chnum().bits()))
-            .field("bcnt", &format_args!("{}", self.bcnt().bits()))
-            .field("dpid", &format_args!("{}", self.dpid().bits()))
-            .field("pktsts", &format_args!("{}", self.pktsts().bits()))
-            .field("fn_", &format_args!("{}", self.fn_().bits()))
+            .field("chnum", &self.chnum())
+            .field("bcnt", &self.bcnt())
+            .field("dpid", &self.dpid())
+            .field("pktsts", &self.pktsts())
+            .field("fn_", &self.fn_())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GRXSTSP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GRXSTSP_SPEC;
 impl crate::RegisterSpec for GRXSTSP_SPEC {
diff --git a/esp32s2/src/usb0/grxstsr.rs b/esp32s2/src/usb0/grxstsr.rs
index eea4e03f41..da95a68786 100644
--- a/esp32s2/src/usb0/grxstsr.rs
+++ b/esp32s2/src/usb0/grxstsr.rs
@@ -41,20 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GRXSTSR")
-            .field("g_chnum", &format_args!("{}", self.g_chnum().bits()))
-            .field("g_bcnt", &format_args!("{}", self.g_bcnt().bits()))
-            .field("g_dpid", &format_args!("{}", self.g_dpid().bits()))
-            .field("g_pktsts", &format_args!("{}", self.g_pktsts().bits()))
-            .field("g_fn", &format_args!("{}", self.g_fn().bits()))
+            .field("g_chnum", &self.g_chnum())
+            .field("g_bcnt", &self.g_bcnt())
+            .field("g_dpid", &self.g_dpid())
+            .field("g_pktsts", &self.g_pktsts())
+            .field("g_fn", &self.g_fn())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GRXSTSR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GRXSTSR_SPEC;
 impl crate::RegisterSpec for GRXSTSR_SPEC {
diff --git a/esp32s2/src/usb0/gsnpsid.rs b/esp32s2/src/usb0/gsnpsid.rs
index 0b414d8063..3b222edf14 100644
--- a/esp32s2/src/usb0/gsnpsid.rs
+++ b/esp32s2/src/usb0/gsnpsid.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GSNPSID")
-            .field("synopsysid", &format_args!("{}", self.synopsysid().bits()))
+            .field("synopsysid", &self.synopsysid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GSNPSID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gsnpsid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GSNPSID_SPEC;
 impl crate::RegisterSpec for GSNPSID_SPEC {
diff --git a/esp32s2/src/usb0/gusbcfg.rs b/esp32s2/src/usb0/gusbcfg.rs
index 20ef792b20..f390ebf6f4 100644
--- a/esp32s2/src/usb0/gusbcfg.rs
+++ b/esp32s2/src/usb0/gusbcfg.rs
@@ -121,43 +121,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GUSBCFG")
-            .field("toutcal", &format_args!("{}", self.toutcal().bits()))
-            .field("phyif", &format_args!("{}", self.phyif().bit()))
-            .field(
-                "ulpi_utmi_sel",
-                &format_args!("{}", self.ulpi_utmi_sel().bit()),
-            )
-            .field("fsintf", &format_args!("{}", self.fsintf().bit()))
-            .field("physel", &format_args!("{}", self.physel().bit()))
-            .field("srpcap", &format_args!("{}", self.srpcap().bit()))
-            .field("hnpcap", &format_args!("{}", self.hnpcap().bit()))
-            .field("usbtrdtim", &format_args!("{}", self.usbtrdtim().bits()))
-            .field(
-                "termseldlpulse",
-                &format_args!("{}", self.termseldlpulse().bit()),
-            )
-            .field("txenddelay", &format_args!("{}", self.txenddelay().bit()))
-            .field(
-                "forcehstmode",
-                &format_args!("{}", self.forcehstmode().bit()),
-            )
-            .field(
-                "forcedevmode",
-                &format_args!("{}", self.forcedevmode().bit()),
-            )
-            .field(
-                "corrupttxpkt",
-                &format_args!("{}", self.corrupttxpkt().bit()),
-            )
+            .field("toutcal", &self.toutcal())
+            .field("phyif", &self.phyif())
+            .field("ulpi_utmi_sel", &self.ulpi_utmi_sel())
+            .field("fsintf", &self.fsintf())
+            .field("physel", &self.physel())
+            .field("srpcap", &self.srpcap())
+            .field("hnpcap", &self.hnpcap())
+            .field("usbtrdtim", &self.usbtrdtim())
+            .field("termseldlpulse", &self.termseldlpulse())
+            .field("txenddelay", &self.txenddelay())
+            .field("forcehstmode", &self.forcehstmode())
+            .field("forcedevmode", &self.forcedevmode())
+            .field("corrupttxpkt", &self.corrupttxpkt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GUSBCFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/haint.rs b/esp32s2/src/usb0/haint.rs
index a020f476a9..b522b1a11e 100644
--- a/esp32s2/src/usb0/haint.rs
+++ b/esp32s2/src/usb0/haint.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HAINT")
-            .field("haint", &format_args!("{}", self.haint().bits()))
+            .field("haint", &self.haint())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HAINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haint::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HAINT_SPEC;
 impl crate::RegisterSpec for HAINT_SPEC {
diff --git a/esp32s2/src/usb0/haintmsk.rs b/esp32s2/src/usb0/haintmsk.rs
index 0788d2b5c9..eef6f48fea 100644
--- a/esp32s2/src/usb0/haintmsk.rs
+++ b/esp32s2/src/usb0/haintmsk.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HAINTMSK")
-            .field("haintmsk", &format_args!("{}", self.haintmsk().bits()))
+            .field("haintmsk", &self.haintmsk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HAINTMSK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/hc/char.rs b/esp32s2/src/usb0/hc/char.rs
index 0b875a066f..9e8b0e322a 100644
--- a/esp32s2/src/usb0/hc/char.rs
+++ b/esp32s2/src/usb0/hc/char.rs
@@ -98,25 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHAR")
-            .field("mps", &format_args!("{}", self.mps().bits()))
-            .field("epnum", &format_args!("{}", self.epnum().bits()))
-            .field("epdir", &format_args!("{}", self.epdir().bit()))
-            .field("lspddev", &format_args!("{}", self.lspddev().bit()))
-            .field("eptype", &format_args!("{}", self.eptype().bits()))
-            .field("ec", &format_args!("{}", self.ec().bit()))
-            .field("devaddr", &format_args!("{}", self.devaddr().bits()))
-            .field("oddfrm", &format_args!("{}", self.oddfrm().bit()))
-            .field("chdis", &format_args!("{}", self.chdis().bit()))
-            .field("chena", &format_args!("{}", self.chena().bit()))
+            .field("mps", &self.mps())
+            .field("epnum", &self.epnum())
+            .field("epdir", &self.epdir())
+            .field("lspddev", &self.lspddev())
+            .field("eptype", &self.eptype())
+            .field("ec", &self.ec())
+            .field("devaddr", &self.devaddr())
+            .field("oddfrm", &self.oddfrm())
+            .field("chdis", &self.chdis())
+            .field("chena", &self.chena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/hc/dma.rs b/esp32s2/src/usb0/hc/dma.rs
index e99a603759..a4ceab159d 100644
--- a/esp32s2/src/usb0/hc/dma.rs
+++ b/esp32s2/src/usb0/hc/dma.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA")
-            .field("dmaaddr", &format_args!("{}", self.dmaaddr().bits()))
+            .field("dmaaddr", &self.dmaaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/hc/dmab.rs b/esp32s2/src/usb0/hc/dmab.rs
index 2acd241d7b..935df7e5ac 100644
--- a/esp32s2/src/usb0/hc/dmab.rs
+++ b/esp32s2/src/usb0/hc/dmab.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMAB")
-            .field("hcdmab", &format_args!("{}", self.hcdmab().bits()))
+            .field("hcdmab", &self.hcdmab())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMAB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmab::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMAB_SPEC;
 impl crate::RegisterSpec for DMAB_SPEC {
diff --git a/esp32s2/src/usb0/hc/int.rs b/esp32s2/src/usb0/hc/int.rs
index 4cc59dec73..803fa348ba 100644
--- a/esp32s2/src/usb0/hc/int.rs
+++ b/esp32s2/src/usb0/hc/int.rs
@@ -134,35 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT")
-            .field("xfercompl", &format_args!("{}", self.xfercompl().bit()))
-            .field("chhltd", &format_args!("{}", self.chhltd().bit()))
-            .field("ahberr", &format_args!("{}", self.ahberr().bit()))
-            .field("stall", &format_args!("{}", self.stall().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("ack", &format_args!("{}", self.ack().bit()))
-            .field("nyet", &format_args!("{}", self.nyet().bit()))
-            .field("xacterr", &format_args!("{}", self.xacterr().bit()))
-            .field("bblerr", &format_args!("{}", self.bblerr().bit()))
-            .field("frmovrun", &format_args!("{}", self.frmovrun().bit()))
-            .field("datatglerr", &format_args!("{}", self.datatglerr().bit()))
-            .field("bnaintr", &format_args!("{}", self.bnaintr().bit()))
-            .field(
-                "xcs_xact_err",
-                &format_args!("{}", self.xcs_xact_err().bit()),
-            )
-            .field(
-                "desc_lst_rollintr",
-                &format_args!("{}", self.desc_lst_rollintr().bit()),
-            )
+            .field("xfercompl", &self.xfercompl())
+            .field("chhltd", &self.chhltd())
+            .field("ahberr", &self.ahberr())
+            .field("stall", &self.stall())
+            .field("nack", &self.nack())
+            .field("ack", &self.ack())
+            .field("nyet", &self.nyet())
+            .field("xacterr", &self.xacterr())
+            .field("bblerr", &self.bblerr())
+            .field("frmovrun", &self.frmovrun())
+            .field("datatglerr", &self.datatglerr())
+            .field("bnaintr", &self.bnaintr())
+            .field("xcs_xact_err", &self.xcs_xact_err())
+            .field("desc_lst_rollintr", &self.desc_lst_rollintr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/hc/intmsk.rs b/esp32s2/src/usb0/hc/intmsk.rs
index 7d9fdcd81f..81f899ce74 100644
--- a/esp32s2/src/usb0/hc/intmsk.rs
+++ b/esp32s2/src/usb0/hc/intmsk.rs
@@ -125,37 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTMSK")
-            .field(
-                "xfercomplmsk",
-                &format_args!("{}", self.xfercomplmsk().bit()),
-            )
-            .field("chhltdmsk", &format_args!("{}", self.chhltdmsk().bit()))
-            .field("ahberrmsk", &format_args!("{}", self.ahberrmsk().bit()))
-            .field("stallmsk", &format_args!("{}", self.stallmsk().bit()))
-            .field("nakmsk", &format_args!("{}", self.nakmsk().bit()))
-            .field("ackmsk", &format_args!("{}", self.ackmsk().bit()))
-            .field("nyetmsk", &format_args!("{}", self.nyetmsk().bit()))
-            .field("xacterrmsk", &format_args!("{}", self.xacterrmsk().bit()))
-            .field("bblerrmsk", &format_args!("{}", self.bblerrmsk().bit()))
-            .field("frmovrunmsk", &format_args!("{}", self.frmovrunmsk().bit()))
-            .field(
-                "datatglerrmsk",
-                &format_args!("{}", self.datatglerrmsk().bit()),
-            )
-            .field("bnaintrmsk", &format_args!("{}", self.bnaintrmsk().bit()))
-            .field(
-                "desc_lst_rollintrmsk",
-                &format_args!("{}", self.desc_lst_rollintrmsk().bit()),
-            )
+            .field("xfercomplmsk", &self.xfercomplmsk())
+            .field("chhltdmsk", &self.chhltdmsk())
+            .field("ahberrmsk", &self.ahberrmsk())
+            .field("stallmsk", &self.stallmsk())
+            .field("nakmsk", &self.nakmsk())
+            .field("ackmsk", &self.ackmsk())
+            .field("nyetmsk", &self.nyetmsk())
+            .field("xacterrmsk", &self.xacterrmsk())
+            .field("bblerrmsk", &self.bblerrmsk())
+            .field("frmovrunmsk", &self.frmovrunmsk())
+            .field("datatglerrmsk", &self.datatglerrmsk())
+            .field("bnaintrmsk", &self.bnaintrmsk())
+            .field("desc_lst_rollintrmsk", &self.desc_lst_rollintrmsk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTMSK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/hc/tsiz.rs b/esp32s2/src/usb0/hc/tsiz.rs
index 6cd06014ce..09ce558852 100644
--- a/esp32s2/src/usb0/hc/tsiz.rs
+++ b/esp32s2/src/usb0/hc/tsiz.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSIZ")
-            .field("xfersize", &format_args!("{}", self.xfersize().bits()))
-            .field("pktcnt", &format_args!("{}", self.pktcnt().bits()))
-            .field("pid", &format_args!("{}", self.pid().bits()))
-            .field("dopng", &format_args!("{}", self.dopng().bit()))
+            .field("xfersize", &self.xfersize())
+            .field("pktcnt", &self.pktcnt())
+            .field("pid", &self.pid())
+            .field("dopng", &self.dopng())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:18"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/hcfg.rs b/esp32s2/src/usb0/hcfg.rs
index 172bddb690..8cac12f662 100644
--- a/esp32s2/src/usb0/hcfg.rs
+++ b/esp32s2/src/usb0/hcfg.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HCFG")
-            .field(
-                "fslspclksel",
-                &format_args!("{}", self.fslspclksel().bits()),
-            )
-            .field("fslssupp", &format_args!("{}", self.fslssupp().bit()))
-            .field("ena32khzs", &format_args!("{}", self.ena32khzs().bit()))
-            .field("descdma", &format_args!("{}", self.descdma().bit()))
-            .field("frlisten", &format_args!("{}", self.frlisten().bits()))
-            .field("perschedena", &format_args!("{}", self.perschedena().bit()))
-            .field("modechtimen", &format_args!("{}", self.modechtimen().bit()))
+            .field("fslspclksel", &self.fslspclksel())
+            .field("fslssupp", &self.fslssupp())
+            .field("ena32khzs", &self.ena32khzs())
+            .field("descdma", &self.descdma())
+            .field("frlisten", &self.frlisten())
+            .field("perschedena", &self.perschedena())
+            .field("modechtimen", &self.modechtimen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HCFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/hfir.rs b/esp32s2/src/usb0/hfir.rs
index aa0909fc52..11f6b0b86a 100644
--- a/esp32s2/src/usb0/hfir.rs
+++ b/esp32s2/src/usb0/hfir.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HFIR")
-            .field("frint", &format_args!("{}", self.frint().bits()))
-            .field("hfirrldctrl", &format_args!("{}", self.hfirrldctrl().bit()))
+            .field("frint", &self.frint())
+            .field("hfirrldctrl", &self.hfirrldctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HFIR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/hflbaddr.rs b/esp32s2/src/usb0/hflbaddr.rs
index 86a437b4d6..d8a3a493d8 100644
--- a/esp32s2/src/usb0/hflbaddr.rs
+++ b/esp32s2/src/usb0/hflbaddr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HFLBADDR")
-            .field("hflbaddr", &format_args!("{}", self.hflbaddr().bits()))
+            .field("hflbaddr", &self.hflbaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HFLBADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/hfnum.rs b/esp32s2/src/usb0/hfnum.rs
index 38d292d619..3d07b021e4 100644
--- a/esp32s2/src/usb0/hfnum.rs
+++ b/esp32s2/src/usb0/hfnum.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HFNUM")
-            .field("frnum", &format_args!("{}", self.frnum().bits()))
-            .field("frrem", &format_args!("{}", self.frrem().bits()))
+            .field("frnum", &self.frnum())
+            .field("frrem", &self.frrem())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HFNUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hfnum::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HFNUM_SPEC;
 impl crate::RegisterSpec for HFNUM_SPEC {
diff --git a/esp32s2/src/usb0/hprt.rs b/esp32s2/src/usb0/hprt.rs
index 95ced3cf52..331e8bd01f 100644
--- a/esp32s2/src/usb0/hprt.rs
+++ b/esp32s2/src/usb0/hprt.rs
@@ -117,34 +117,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPRT")
-            .field("prtconnsts", &format_args!("{}", self.prtconnsts().bit()))
-            .field("prtconndet", &format_args!("{}", self.prtconndet().bit()))
-            .field("prtena", &format_args!("{}", self.prtena().bit()))
-            .field("prtenchng", &format_args!("{}", self.prtenchng().bit()))
-            .field(
-                "prtovrcurract",
-                &format_args!("{}", self.prtovrcurract().bit()),
-            )
-            .field(
-                "prtovrcurrchng",
-                &format_args!("{}", self.prtovrcurrchng().bit()),
-            )
-            .field("prtres", &format_args!("{}", self.prtres().bit()))
-            .field("prtsusp", &format_args!("{}", self.prtsusp().bit()))
-            .field("prtrst", &format_args!("{}", self.prtrst().bit()))
-            .field("prtlnsts", &format_args!("{}", self.prtlnsts().bits()))
-            .field("prtpwr", &format_args!("{}", self.prtpwr().bit()))
-            .field("prttstctl", &format_args!("{}", self.prttstctl().bits()))
-            .field("prtspd", &format_args!("{}", self.prtspd().bits()))
+            .field("prtconnsts", &self.prtconnsts())
+            .field("prtconndet", &self.prtconndet())
+            .field("prtena", &self.prtena())
+            .field("prtenchng", &self.prtenchng())
+            .field("prtovrcurract", &self.prtovrcurract())
+            .field("prtovrcurrchng", &self.prtovrcurrchng())
+            .field("prtres", &self.prtres())
+            .field("prtsusp", &self.prtsusp())
+            .field("prtrst", &self.prtrst())
+            .field("prtlnsts", &self.prtlnsts())
+            .field("prtpwr", &self.prtpwr())
+            .field("prttstctl", &self.prttstctl())
+            .field("prtspd", &self.prtspd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPRT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/hptxfsiz.rs b/esp32s2/src/usb0/hptxfsiz.rs
index c145c6dab5..a183199a75 100644
--- a/esp32s2/src/usb0/hptxfsiz.rs
+++ b/esp32s2/src/usb0/hptxfsiz.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPTXFSIZ")
-            .field("ptxfstaddr", &format_args!("{}", self.ptxfstaddr().bits()))
-            .field("ptxfsize", &format_args!("{}", self.ptxfsize().bits()))
+            .field("ptxfstaddr", &self.ptxfstaddr())
+            .field("ptxfsize", &self.ptxfsize())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPTXFSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/hptxsts.rs b/esp32s2/src/usb0/hptxsts.rs
index 841c4618e2..5618635fc7 100644
--- a/esp32s2/src/usb0/hptxsts.rs
+++ b/esp32s2/src/usb0/hptxsts.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPTXSTS")
-            .field(
-                "ptxfspcavail",
-                &format_args!("{}", self.ptxfspcavail().bits()),
-            )
-            .field(
-                "ptxqspcavail",
-                &format_args!("{}", self.ptxqspcavail().bits()),
-            )
-            .field("ptxqtop", &format_args!("{}", self.ptxqtop().bits()))
+            .field("ptxfspcavail", &self.ptxfspcavail())
+            .field("ptxqspcavail", &self.ptxqspcavail())
+            .field("ptxqtop", &self.ptxqtop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPTXSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hptxsts::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HPTXSTS_SPEC;
 impl crate::RegisterSpec for HPTXSTS_SPEC {
diff --git a/esp32s2/src/usb0/in_ep/diepctl.rs b/esp32s2/src/usb0/in_ep/diepctl.rs
index fcd3ad47cc..f269337cce 100644
--- a/esp32s2/src/usb0/in_ep/diepctl.rs
+++ b/esp32s2/src/usb0/in_ep/diepctl.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPCTL")
-            .field("mps", &format_args!("{}", self.mps().bits()))
-            .field("usbactep", &format_args!("{}", self.usbactep().bit()))
-            .field("naksts", &format_args!("{}", self.naksts().bit()))
-            .field("eptype", &format_args!("{}", self.eptype().bits()))
-            .field("stall", &format_args!("{}", self.stall().bit()))
-            .field("txfnum", &format_args!("{}", self.txfnum().bits()))
-            .field("epdis", &format_args!("{}", self.epdis().bit()))
-            .field("epena", &format_args!("{}", self.epena().bit()))
+            .field("mps", &self.mps())
+            .field("usbactep", &self.usbactep())
+            .field("naksts", &self.naksts())
+            .field("eptype", &self.eptype())
+            .field("stall", &self.stall())
+            .field("txfnum", &self.txfnum())
+            .field("epdis", &self.epdis())
+            .field("epena", &self.epena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/in_ep/dieptsiz.rs b/esp32s2/src/usb0/in_ep/dieptsiz.rs
index e3d2e4d69a..cea3e21ed5 100644
--- a/esp32s2/src/usb0/in_ep/dieptsiz.rs
+++ b/esp32s2/src/usb0/in_ep/dieptsiz.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPTSIZ")
-            .field("xfersize", &format_args!("{}", self.xfersize().bits()))
-            .field("pktcnt", &format_args!("{}", self.pktcnt().bits()))
+            .field("xfersize", &self.xfersize())
+            .field("pktcnt", &self.pktcnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPTSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:18"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/in_ep0/diepctl.rs b/esp32s2/src/usb0/in_ep0/diepctl.rs
index b1a20a1e4c..1aaa2873b2 100644
--- a/esp32s2/src/usb0/in_ep0/diepctl.rs
+++ b/esp32s2/src/usb0/in_ep0/diepctl.rs
@@ -78,23 +78,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPCTL")
-            .field("mps", &format_args!("{}", self.mps().bits()))
-            .field("usbactep", &format_args!("{}", self.usbactep().bit()))
-            .field("naksts", &format_args!("{}", self.naksts().bit()))
-            .field("eptype", &format_args!("{}", self.eptype().bits()))
-            .field("stall", &format_args!("{}", self.stall().bit()))
-            .field("txfnum", &format_args!("{}", self.txfnum().bits()))
-            .field("epdis", &format_args!("{}", self.epdis().bit()))
-            .field("epena", &format_args!("{}", self.epena().bit()))
+            .field("mps", &self.mps())
+            .field("usbactep", &self.usbactep())
+            .field("naksts", &self.naksts())
+            .field("eptype", &self.eptype())
+            .field("stall", &self.stall())
+            .field("txfnum", &self.txfnum())
+            .field("epdis", &self.epdis())
+            .field("epena", &self.epena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/in_ep0/diepdma.rs b/esp32s2/src/usb0/in_ep0/diepdma.rs
index 91dd04b770..f959ce25ec 100644
--- a/esp32s2/src/usb0/in_ep0/diepdma.rs
+++ b/esp32s2/src/usb0/in_ep0/diepdma.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPDMA")
-            .field("dmaaddr", &format_args!("{}", self.dmaaddr().bits()))
+            .field("dmaaddr", &self.dmaaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPDMA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/in_ep0/diepdmab.rs b/esp32s2/src/usb0/in_ep0/diepdmab.rs
index 3b14652aab..930ae0b82d 100644
--- a/esp32s2/src/usb0/in_ep0/diepdmab.rs
+++ b/esp32s2/src/usb0/in_ep0/diepdmab.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPDMAB")
-            .field(
-                "dmabufferaddr",
-                &format_args!("{}", self.dmabufferaddr().bits()),
-            )
+            .field("dmabufferaddr", &self.dmabufferaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPDMAB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepdmab::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIEPDMAB_SPEC;
 impl crate::RegisterSpec for DIEPDMAB_SPEC {
diff --git a/esp32s2/src/usb0/in_ep0/diepint.rs b/esp32s2/src/usb0/in_ep0/diepint.rs
index 4571ae668a..af7a0f9c52 100644
--- a/esp32s2/src/usb0/in_ep0/diepint.rs
+++ b/esp32s2/src/usb0/in_ep0/diepint.rs
@@ -132,29 +132,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPINT")
-            .field("xfercompl", &format_args!("{}", self.xfercompl().bit()))
-            .field("epdisbld", &format_args!("{}", self.epdisbld().bit()))
-            .field("ahberr", &format_args!("{}", self.ahberr().bit()))
-            .field("timeout", &format_args!("{}", self.timeout().bit()))
-            .field("intkntxfemp", &format_args!("{}", self.intkntxfemp().bit()))
-            .field("intknepmis", &format_args!("{}", self.intknepmis().bit()))
-            .field("inepnakeff", &format_args!("{}", self.inepnakeff().bit()))
-            .field("txfemp", &format_args!("{}", self.txfemp().bit()))
-            .field("txfifoundrn", &format_args!("{}", self.txfifoundrn().bit()))
-            .field("bnaintr", &format_args!("{}", self.bnaintr().bit()))
-            .field("pktdrpsts", &format_args!("{}", self.pktdrpsts().bit()))
-            .field("bbleerr", &format_args!("{}", self.bbleerr().bit()))
-            .field("nakintrpt", &format_args!("{}", self.nakintrpt().bit()))
-            .field("nyetintrpt", &format_args!("{}", self.nyetintrpt().bit()))
+            .field("xfercompl", &self.xfercompl())
+            .field("epdisbld", &self.epdisbld())
+            .field("ahberr", &self.ahberr())
+            .field("timeout", &self.timeout())
+            .field("intkntxfemp", &self.intkntxfemp())
+            .field("intknepmis", &self.intknepmis())
+            .field("inepnakeff", &self.inepnakeff())
+            .field("txfemp", &self.txfemp())
+            .field("txfifoundrn", &self.txfifoundrn())
+            .field("bnaintr", &self.bnaintr())
+            .field("pktdrpsts", &self.pktdrpsts())
+            .field("bbleerr", &self.bbleerr())
+            .field("nakintrpt", &self.nakintrpt())
+            .field("nyetintrpt", &self.nyetintrpt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/in_ep0/dieptsiz.rs b/esp32s2/src/usb0/in_ep0/dieptsiz.rs
index 213c0ab105..7a93c34199 100644
--- a/esp32s2/src/usb0/in_ep0/dieptsiz.rs
+++ b/esp32s2/src/usb0/in_ep0/dieptsiz.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPTSIZ")
-            .field("xfersize", &format_args!("{}", self.xfersize().bits()))
-            .field("pktcnt", &format_args!("{}", self.pktcnt().bits()))
+            .field("xfersize", &self.xfersize())
+            .field("pktcnt", &self.pktcnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPTSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/in_ep0/dtxfsts.rs b/esp32s2/src/usb0/in_ep0/dtxfsts.rs
index 6dde2d4f48..6eaf8877b6 100644
--- a/esp32s2/src/usb0/in_ep0/dtxfsts.rs
+++ b/esp32s2/src/usb0/in_ep0/dtxfsts.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DTXFSTS")
-            .field(
-                "ineptxfspcavail",
-                &format_args!("{}", self.ineptxfspcavail().bits()),
-            )
+            .field("ineptxfspcavail", &self.ineptxfspcavail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DTXFSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtxfsts::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DTXFSTS_SPEC;
 impl crate::RegisterSpec for DTXFSTS_SPEC {
diff --git a/esp32s2/src/usb0/out_ep/doepctl.rs b/esp32s2/src/usb0/out_ep/doepctl.rs
index 7357f53efb..fd8a085bf5 100644
--- a/esp32s2/src/usb0/out_ep/doepctl.rs
+++ b/esp32s2/src/usb0/out_ep/doepctl.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPCTL")
-            .field("mps", &format_args!("{}", self.mps().bits()))
-            .field("usbactep", &format_args!("{}", self.usbactep().bit()))
-            .field("naksts", &format_args!("{}", self.naksts().bit()))
-            .field("eptype", &format_args!("{}", self.eptype().bits()))
-            .field("snp", &format_args!("{}", self.snp().bit()))
-            .field("stall", &format_args!("{}", self.stall().bit()))
-            .field("epdis", &format_args!("{}", self.epdis().bit()))
-            .field("epena", &format_args!("{}", self.epena().bit()))
+            .field("mps", &self.mps())
+            .field("usbactep", &self.usbactep())
+            .field("naksts", &self.naksts())
+            .field("eptype", &self.eptype())
+            .field("snp", &self.snp())
+            .field("stall", &self.stall())
+            .field("epdis", &self.epdis())
+            .field("epena", &self.epena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/out_ep/doeptsiz.rs b/esp32s2/src/usb0/out_ep/doeptsiz.rs
index 21c28d4811..1c54bb57b4 100644
--- a/esp32s2/src/usb0/out_ep/doeptsiz.rs
+++ b/esp32s2/src/usb0/out_ep/doeptsiz.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPTSIZ")
-            .field("xfersize", &format_args!("{}", self.xfersize().bits()))
-            .field("pktcnt", &format_args!("{}", self.pktcnt().bits()))
-            .field("supcnt", &format_args!("{}", self.supcnt().bits()))
+            .field("xfersize", &self.xfersize())
+            .field("pktcnt", &self.pktcnt())
+            .field("supcnt", &self.supcnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPTSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:18"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/out_ep0/doepctl.rs b/esp32s2/src/usb0/out_ep0/doepctl.rs
index 812ad522bb..afa8be57b1 100644
--- a/esp32s2/src/usb0/out_ep0/doepctl.rs
+++ b/esp32s2/src/usb0/out_ep0/doepctl.rs
@@ -74,23 +74,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPCTL")
-            .field("mps", &format_args!("{}", self.mps().bits()))
-            .field("usbactep", &format_args!("{}", self.usbactep().bit()))
-            .field("naksts", &format_args!("{}", self.naksts().bit()))
-            .field("eptype", &format_args!("{}", self.eptype().bits()))
-            .field("snp", &format_args!("{}", self.snp().bit()))
-            .field("stall", &format_args!("{}", self.stall().bit()))
-            .field("epdis", &format_args!("{}", self.epdis().bit()))
-            .field("epena", &format_args!("{}", self.epena().bit()))
+            .field("mps", &self.mps())
+            .field("usbactep", &self.usbactep())
+            .field("naksts", &self.naksts())
+            .field("eptype", &self.eptype())
+            .field("snp", &self.snp())
+            .field("stall", &self.stall())
+            .field("epdis", &self.epdis())
+            .field("epena", &self.epena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/out_ep0/doepdma.rs b/esp32s2/src/usb0/out_ep0/doepdma.rs
index c5f70ea68b..056a1c29bd 100644
--- a/esp32s2/src/usb0/out_ep0/doepdma.rs
+++ b/esp32s2/src/usb0/out_ep0/doepdma.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPDMA")
-            .field("dmaaddr", &format_args!("{}", self.dmaaddr().bits()))
+            .field("dmaaddr", &self.dmaaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPDMA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/out_ep0/doepdmab.rs b/esp32s2/src/usb0/out_ep0/doepdmab.rs
index 1ac9ce383c..e9f98d5f4a 100644
--- a/esp32s2/src/usb0/out_ep0/doepdmab.rs
+++ b/esp32s2/src/usb0/out_ep0/doepdmab.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPDMAB")
-            .field(
-                "dmabufferaddr",
-                &format_args!("{}", self.dmabufferaddr().bits()),
-            )
+            .field("dmabufferaddr", &self.dmabufferaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPDMAB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/out_ep0/doepint.rs b/esp32s2/src/usb0/out_ep0/doepint.rs
index c390e5f270..39486dfcbf 100644
--- a/esp32s2/src/usb0/out_ep0/doepint.rs
+++ b/esp32s2/src/usb0/out_ep0/doepint.rs
@@ -134,32 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPINT")
-            .field("xfercompl", &format_args!("{}", self.xfercompl().bit()))
-            .field("epdisbld", &format_args!("{}", self.epdisbld().bit()))
-            .field("ahberr", &format_args!("{}", self.ahberr().bit()))
-            .field("setup", &format_args!("{}", self.setup().bit()))
-            .field("outtknepdis", &format_args!("{}", self.outtknepdis().bit()))
-            .field("stsphsercvd", &format_args!("{}", self.stsphsercvd().bit()))
-            .field(
-                "back2backsetup",
-                &format_args!("{}", self.back2backsetup().bit()),
-            )
-            .field("outpkterr", &format_args!("{}", self.outpkterr().bit()))
-            .field("bnaintr", &format_args!("{}", self.bnaintr().bit()))
-            .field("pktdrpsts", &format_args!("{}", self.pktdrpsts().bit()))
-            .field("bbleerr", &format_args!("{}", self.bbleerr().bit()))
-            .field("nakintrpt", &format_args!("{}", self.nakintrpt().bit()))
-            .field("nyepintrpt", &format_args!("{}", self.nyepintrpt().bit()))
-            .field("stuppktrcvd", &format_args!("{}", self.stuppktrcvd().bit()))
+            .field("xfercompl", &self.xfercompl())
+            .field("epdisbld", &self.epdisbld())
+            .field("ahberr", &self.ahberr())
+            .field("setup", &self.setup())
+            .field("outtknepdis", &self.outtknepdis())
+            .field("stsphsercvd", &self.stsphsercvd())
+            .field("back2backsetup", &self.back2backsetup())
+            .field("outpkterr", &self.outpkterr())
+            .field("bnaintr", &self.bnaintr())
+            .field("pktdrpsts", &self.pktdrpsts())
+            .field("bbleerr", &self.bbleerr())
+            .field("nakintrpt", &self.nakintrpt())
+            .field("nyepintrpt", &self.nyepintrpt())
+            .field("stuppktrcvd", &self.stuppktrcvd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/out_ep0/doeptsiz.rs b/esp32s2/src/usb0/out_ep0/doeptsiz.rs
index 91af3ee81a..166dea70ae 100644
--- a/esp32s2/src/usb0/out_ep0/doeptsiz.rs
+++ b/esp32s2/src/usb0/out_ep0/doeptsiz.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPTSIZ")
-            .field("xfersize", &format_args!("{}", self.xfersize().bits()))
-            .field("pktcnt", &format_args!("{}", self.pktcnt().bit()))
-            .field("supcnt", &format_args!("{}", self.supcnt().bits()))
+            .field("xfersize", &self.xfersize())
+            .field("pktcnt", &self.pktcnt())
+            .field("supcnt", &self.supcnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPTSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32s2/src/usb0/pcgcctl.rs b/esp32s2/src/usb0/pcgcctl.rs
index 276690e5fc..f1b358e978 100644
--- a/esp32s2/src/usb0/pcgcctl.rs
+++ b/esp32s2/src/usb0/pcgcctl.rs
@@ -67,28 +67,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCGCCTL")
-            .field("stoppclk", &format_args!("{}", self.stoppclk().bit()))
-            .field("gatehclk", &format_args!("{}", self.gatehclk().bit()))
-            .field("pwrclmp", &format_args!("{}", self.pwrclmp().bit()))
-            .field(
-                "rstpdwnmodule",
-                &format_args!("{}", self.rstpdwnmodule().bit()),
-            )
-            .field("physleep", &format_args!("{}", self.physleep().bit()))
-            .field("l1suspended", &format_args!("{}", self.l1suspended().bit()))
-            .field(
-                "resetaftersusp",
-                &format_args!("{}", self.resetaftersusp().bit()),
-            )
+            .field("stoppclk", &self.stoppclk())
+            .field("gatehclk", &self.gatehclk())
+            .field("pwrclmp", &self.pwrclmp())
+            .field("rstpdwnmodule", &self.rstpdwnmodule())
+            .field("physleep", &self.physleep())
+            .field("l1suspended", &self.l1suspended())
+            .field("resetaftersusp", &self.resetaftersusp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCGCCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s2/src/usb_wrap/date.rs b/esp32s2/src/usb_wrap/date.rs
index c3bea7ca6c..aabca88dec 100644
--- a/esp32s2/src/usb_wrap/date.rs
+++ b/esp32s2/src/usb_wrap/date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "usb_wrap_date",
-                &format_args!("{}", self.usb_wrap_date().bits()),
-            )
+            .field("usb_wrap_date", &self.usb_wrap_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Date register"]
     #[inline(always)]
diff --git a/esp32s2/src/usb_wrap/otg_conf.rs b/esp32s2/src/usb_wrap/otg_conf.rs
index cf268b2795..b01340ca50 100644
--- a/esp32s2/src/usb_wrap/otg_conf.rs
+++ b/esp32s2/src/usb_wrap/otg_conf.rs
@@ -206,76 +206,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OTG_CONF")
-            .field(
-                "srp_sessend_override",
-                &format_args!("{}", self.srp_sessend_override().bit()),
-            )
-            .field(
-                "srp_sessend_value",
-                &format_args!("{}", self.srp_sessend_value().bit()),
-            )
-            .field("phy_sel", &format_args!("{}", self.phy_sel().bit()))
-            .field(
-                "dfifo_force_pd",
-                &format_args!("{}", self.dfifo_force_pd().bit()),
-            )
-            .field(
-                "dbnce_fltr_bypass",
-                &format_args!("{}", self.dbnce_fltr_bypass().bit()),
-            )
-            .field(
-                "exchg_pins_override",
-                &format_args!("{}", self.exchg_pins_override().bit()),
-            )
-            .field("exchg_pins", &format_args!("{}", self.exchg_pins().bit()))
-            .field("vrefh", &format_args!("{}", self.vrefh().bits()))
-            .field("vrefl", &format_args!("{}", self.vrefl().bits()))
-            .field(
-                "vref_override",
-                &format_args!("{}", self.vref_override().bit()),
-            )
-            .field(
-                "pad_pull_override",
-                &format_args!("{}", self.pad_pull_override().bit()),
-            )
-            .field("dp_pullup", &format_args!("{}", self.dp_pullup().bit()))
-            .field("dp_pulldown", &format_args!("{}", self.dp_pulldown().bit()))
-            .field("dm_pullup", &format_args!("{}", self.dm_pullup().bit()))
-            .field("dm_pulldown", &format_args!("{}", self.dm_pulldown().bit()))
-            .field(
-                "pullup_value",
-                &format_args!("{}", self.pullup_value().bit()),
-            )
-            .field(
-                "usb_pad_enable",
-                &format_args!("{}", self.usb_pad_enable().bit()),
-            )
-            .field(
-                "ahb_clk_force_on",
-                &format_args!("{}", self.ahb_clk_force_on().bit()),
-            )
-            .field(
-                "phy_clk_force_on",
-                &format_args!("{}", self.phy_clk_force_on().bit()),
-            )
-            .field(
-                "phy_tx_edge_sel",
-                &format_args!("{}", self.phy_tx_edge_sel().bit()),
-            )
-            .field(
-                "dfifo_force_pu",
-                &format_args!("{}", self.dfifo_force_pu().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("srp_sessend_override", &self.srp_sessend_override())
+            .field("srp_sessend_value", &self.srp_sessend_value())
+            .field("phy_sel", &self.phy_sel())
+            .field("dfifo_force_pd", &self.dfifo_force_pd())
+            .field("dbnce_fltr_bypass", &self.dbnce_fltr_bypass())
+            .field("exchg_pins_override", &self.exchg_pins_override())
+            .field("exchg_pins", &self.exchg_pins())
+            .field("vrefh", &self.vrefh())
+            .field("vrefl", &self.vrefl())
+            .field("vref_override", &self.vref_override())
+            .field("pad_pull_override", &self.pad_pull_override())
+            .field("dp_pullup", &self.dp_pullup())
+            .field("dp_pulldown", &self.dp_pulldown())
+            .field("dm_pullup", &self.dm_pullup())
+            .field("dm_pulldown", &self.dm_pulldown())
+            .field("pullup_value", &self.pullup_value())
+            .field("usb_pad_enable", &self.usb_pad_enable())
+            .field("ahb_clk_force_on", &self.ahb_clk_force_on())
+            .field("phy_clk_force_on", &self.phy_clk_force_on())
+            .field("phy_tx_edge_sel", &self.phy_tx_edge_sel())
+            .field("dfifo_force_pu", &self.dfifo_force_pu())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OTG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software."]
     #[inline(always)]
diff --git a/esp32s2/src/usb_wrap/test_conf.rs b/esp32s2/src/usb_wrap/test_conf.rs
index 1524639a60..8b557fcdc0 100644
--- a/esp32s2/src/usb_wrap/test_conf.rs
+++ b/esp32s2/src/usb_wrap/test_conf.rs
@@ -65,22 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEST_CONF")
-            .field("test_enable", &format_args!("{}", self.test_enable().bit()))
-            .field("test_usb_oe", &format_args!("{}", self.test_usb_oe().bit()))
-            .field("test_tx_dp", &format_args!("{}", self.test_tx_dp().bit()))
-            .field("test_tx_dm", &format_args!("{}", self.test_tx_dm().bit()))
-            .field("test_rx_rcv", &format_args!("{}", self.test_rx_rcv().bit()))
-            .field("test_rx_dp", &format_args!("{}", self.test_rx_dp().bit()))
-            .field("test_rx_dm", &format_args!("{}", self.test_rx_dm().bit()))
+            .field("test_enable", &self.test_enable())
+            .field("test_usb_oe", &self.test_usb_oe())
+            .field("test_tx_dp", &self.test_tx_dp())
+            .field("test_tx_dm", &self.test_tx_dm())
+            .field("test_rx_rcv", &self.test_rx_rcv())
+            .field("test_rx_dp", &self.test_rx_dp())
+            .field("test_rx_dm", &self.test_rx_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable test of the USB pad"]
     #[inline(always)]
diff --git a/esp32s2/src/xts_aes/date.rs b/esp32s2/src/xts_aes/date.rs
index 8d7c7adc1a..2a11d45df9 100644
--- a/esp32s2/src/xts_aes/date.rs
+++ b/esp32s2/src/xts_aes/date.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 #[doc = "Version control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`date::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s2/src/xts_aes/destination.rs b/esp32s2/src/xts_aes/destination.rs
index 9ebdd8472e..34ddaa9929 100644
--- a/esp32s2/src/xts_aes/destination.rs
+++ b/esp32s2/src/xts_aes/destination.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DESTINATION")
-            .field("destination", &format_args!("{}", self.destination().bit()))
+            .field("destination", &self.destination())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DESTINATION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occur if users write 1. 0: flash. 1: external RAM."]
     #[inline(always)]
diff --git a/esp32s2/src/xts_aes/linesize.rs b/esp32s2/src/xts_aes/linesize.rs
index 5bbb14c7aa..c97ef07163 100644
--- a/esp32s2/src/xts_aes/linesize.rs
+++ b/esp32s2/src/xts_aes/linesize.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LINESIZE")
-            .field("linesize", &format_args!("{}", self.linesize().bits()))
+            .field("linesize", &self.linesize())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LINESIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Configures the data size of a single encryption. 0: 128 bits. 1: 256 bits. 2: 512 bits."]
     #[inline(always)]
diff --git a/esp32s2/src/xts_aes/physical_address.rs b/esp32s2/src/xts_aes/physical_address.rs
index 118073a75a..2fbbc8f1a1 100644
--- a/esp32s2/src/xts_aes/physical_address.rs
+++ b/esp32s2/src/xts_aes/physical_address.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHYSICAL_ADDRESS")
-            .field(
-                "physical_address",
-                &format_args!("{}", self.physical_address().bits()),
-            )
+            .field("physical_address", &self.physical_address())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHYSICAL_ADDRESS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Physical address."]
     #[inline(always)]
diff --git a/esp32s2/src/xts_aes/plain_.rs b/esp32s2/src/xts_aes/plain_.rs
index 8152e46c3d..5a420664ea 100644
--- a/esp32s2/src/xts_aes/plain_.rs
+++ b/esp32s2/src/xts_aes/plain_.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PLAIN_")
-            .field("plain", &format_args!("{}", self.plain().bits()))
+            .field("plain", &self.plain())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PLAIN__SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register stores %sth 32-bit piece of plaintext."]
     #[inline(always)]
diff --git a/esp32s2/src/xts_aes/state.rs b/esp32s2/src/xts_aes/state.rs
index 136acc6af3..3c6a9aa50a 100644
--- a/esp32s2/src/xts_aes/state.rs
+++ b/esp32s2/src/xts_aes/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("state", &format_args!("{}", self.state().bits()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32s3-ulp/src/generic.rs b/esp32s3-ulp/src/generic.rs
index a2ae6aa053..45ebed16c4 100644
--- a/esp32s3-ulp/src/generic.rs
+++ b/esp32s3-ulp/src/generic.rs
@@ -48,7 +48,7 @@ pub trait RegisterSpec {
 #[doc = " Raw field type"]
 pub trait FieldSpec: Sized {
     #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
-    type Ux: Copy + PartialEq + From<Self>;
+    type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
 }
 #[doc = " Marker for fields with fixed values"]
 pub trait IsEnum: FieldSpec {}
@@ -237,6 +237,14 @@ impl<REG: Readable + Writable> Reg<REG> {
         );
     }
 }
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
 #[doc(hidden)]
 pub mod raw;
 #[doc = " Register reader."]
@@ -302,6 +310,11 @@ impl<FI: FieldSpec> FieldReader<FI> {
         self.bits
     }
 }
+impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 impl<FI> PartialEq<FI> for FieldReader<FI>
 where
     FI: FieldSpec + Copy,
@@ -338,10 +351,21 @@ impl<FI> BitReader<FI> {
         self.bit()
     }
 }
+impl<FI> core::fmt::Debug for BitReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 #[doc = " Marker for register/field writers which can take any value of specified width"]
 pub struct Safe;
 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
 pub struct Unsafe;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct Range<const MIN: u64, const MAX: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeFrom<const MIN: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeTo<const MAX: u64>;
 #[doc = " Write field Proxy"]
 pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
     raw::FieldWriter<'a, REG, WI, FI, Safety>;
@@ -393,6 +417,58 @@ where
         unsafe { self.bits(value) }
     }
 }
+impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
+    FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN && value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
 impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
diff --git a/esp32s3-ulp/src/lib.rs b/esp32s3-ulp/src/lib.rs
index b0789c5728..cc216c1000 100644
--- a/esp32s3-ulp/src/lib.rs
+++ b/esp32s3-ulp/src/lib.rs
@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32-S3-ULP microcontrollers (generated using svd2rust v0.33.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32-S3-ULP microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
diff --git a/esp32s3-ulp/src/rtc_cntl/cocpu_ctrl.rs b/esp32s3-ulp/src/rtc_cntl/cocpu_ctrl.rs
index 0e2339bb1c..701b39c969 100644
--- a/esp32s3-ulp/src/rtc_cntl/cocpu_ctrl.rs
+++ b/esp32s3-ulp/src/rtc_cntl/cocpu_ctrl.rs
@@ -100,46 +100,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COCPU_CTRL")
-            .field(
-                "cocpu_clk_fo",
-                &format_args!("{}", self.cocpu_clk_fo().bit()),
-            )
-            .field(
-                "cocpu_start_2_reset_dis",
-                &format_args!("{}", self.cocpu_start_2_reset_dis().bits()),
-            )
-            .field(
-                "cocpu_start_2_intr_en",
-                &format_args!("{}", self.cocpu_start_2_intr_en().bits()),
-            )
-            .field("cocpu_shut", &format_args!("{}", self.cocpu_shut().bit()))
-            .field(
-                "cocpu_shut_2_clk_dis",
-                &format_args!("{}", self.cocpu_shut_2_clk_dis().bits()),
-            )
-            .field(
-                "cocpu_shut_reset_en",
-                &format_args!("{}", self.cocpu_shut_reset_en().bit()),
-            )
-            .field("cocpu_sel", &format_args!("{}", self.cocpu_sel().bit()))
-            .field(
-                "cocpu_done_force",
-                &format_args!("{}", self.cocpu_done_force().bit()),
-            )
-            .field("cocpu_done", &format_args!("{}", self.cocpu_done().bit()))
-            .field(
-                "cocpu_clkgate_en",
-                &format_args!("{}", self.cocpu_clkgate_en().bit()),
-            )
+            .field("cocpu_clk_fo", &self.cocpu_clk_fo())
+            .field("cocpu_start_2_reset_dis", &self.cocpu_start_2_reset_dis())
+            .field("cocpu_start_2_intr_en", &self.cocpu_start_2_intr_en())
+            .field("cocpu_shut", &self.cocpu_shut())
+            .field("cocpu_shut_2_clk_dis", &self.cocpu_shut_2_clk_dis())
+            .field("cocpu_shut_reset_en", &self.cocpu_shut_reset_en())
+            .field("cocpu_sel", &self.cocpu_sel())
+            .field("cocpu_done_force", &self.cocpu_done_force())
+            .field("cocpu_done", &self.cocpu_done())
+            .field("cocpu_clkgate_en", &self.cocpu_clkgate_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COCPU_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - cocpu clk force on"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_cntl/rtc_ulp_cp_ctrl.rs b/esp32s3-ulp/src/rtc_cntl/rtc_ulp_cp_ctrl.rs
index f983cc0915..42ed8fd2b8 100644
--- a/esp32s3-ulp/src/rtc_cntl/rtc_ulp_cp_ctrl.rs
+++ b/esp32s3-ulp/src/rtc_cntl/rtc_ulp_cp_ctrl.rs
@@ -64,39 +64,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_ULP_CP_CTRL")
-            .field(
-                "ulp_cp_mem_addr_init",
-                &format_args!("{}", self.ulp_cp_mem_addr_init().bits()),
-            )
-            .field(
-                "ulp_cp_mem_addr_size",
-                &format_args!("{}", self.ulp_cp_mem_addr_size().bits()),
-            )
-            .field(
-                "ulp_cp_clk_fo",
-                &format_args!("{}", self.ulp_cp_clk_fo().bit()),
-            )
-            .field(
-                "ulp_cp_reset",
-                &format_args!("{}", self.ulp_cp_reset().bit()),
-            )
-            .field(
-                "ulp_cp_force_start_top",
-                &format_args!("{}", self.ulp_cp_force_start_top().bit()),
-            )
-            .field(
-                "ulp_cp_start_top",
-                &format_args!("{}", self.ulp_cp_start_top().bit()),
-            )
+            .field("ulp_cp_mem_addr_init", &self.ulp_cp_mem_addr_init())
+            .field("ulp_cp_mem_addr_size", &self.ulp_cp_mem_addr_size())
+            .field("ulp_cp_clk_fo", &self.ulp_cp_clk_fo())
+            .field("ulp_cp_reset", &self.ulp_cp_reset())
+            .field("ulp_cp_force_start_top", &self.ulp_cp_force_start_top())
+            .field("ulp_cp_start_top", &self.ulp_cp_start_top())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_ULP_CP_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - No public"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_cntl/rtc_ulp_cp_timer.rs b/esp32s3-ulp/src/rtc_cntl/rtc_ulp_cp_timer.rs
index e760bbd737..6d977953ec 100644
--- a/esp32s3-ulp/src/rtc_cntl/rtc_ulp_cp_timer.rs
+++ b/esp32s3-ulp/src/rtc_cntl/rtc_ulp_cp_timer.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_ULP_CP_TIMER")
-            .field(
-                "ulp_cp_pc_init",
-                &format_args!("{}", self.ulp_cp_pc_init().bits()),
-            )
-            .field(
-                "ulp_cp_gpio_wakeup_ena",
-                &format_args!("{}", self.ulp_cp_gpio_wakeup_ena().bit()),
-            )
-            .field(
-                "ulp_cp_slp_timer_en",
-                &format_args!("{}", self.ulp_cp_slp_timer_en().bit()),
-            )
+            .field("ulp_cp_pc_init", &self.ulp_cp_pc_init())
+            .field("ulp_cp_gpio_wakeup_ena", &self.ulp_cp_gpio_wakeup_ena())
+            .field("ulp_cp_slp_timer_en", &self.ulp_cp_slp_timer_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_ULP_CP_TIMER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - ULP-coprocessor PC initial address"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_cntl/rtc_ulp_cp_timer_1.rs b/esp32s3-ulp/src/rtc_cntl/rtc_ulp_cp_timer_1.rs
index fee89d3586..573c8a6c4b 100644
--- a/esp32s3-ulp/src/rtc_cntl/rtc_ulp_cp_timer_1.rs
+++ b/esp32s3-ulp/src/rtc_cntl/rtc_ulp_cp_timer_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_ULP_CP_TIMER_1")
-            .field(
-                "ulp_cp_timer_slp_cycle",
-                &format_args!("{}", self.ulp_cp_timer_slp_cycle().bits()),
-            )
+            .field("ulp_cp_timer_slp_cycle", &self.ulp_cp_timer_slp_cycle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_ULP_CP_TIMER_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:31 - sleep cycles for ULP-coprocessor timer"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_i2c/cmd.rs b/esp32s3-ulp/src/rtc_i2c/cmd.rs
index 9a93b9a334..0d65ae2943 100644
--- a/esp32s3-ulp/src/rtc_i2c/cmd.rs
+++ b/esp32s3-ulp/src/rtc_i2c/cmd.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("command", &format_args!("{}", self.command().bits()))
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - command0"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_i2c/ctrl.rs b/esp32s3-ulp/src/rtc_i2c/ctrl.rs
index e364ba7baa..ce7d4e072a 100644
--- a/esp32s3-ulp/src/rtc_i2c/ctrl.rs
+++ b/esp32s3-ulp/src/rtc_i2c/ctrl.rs
@@ -89,39 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field("ms_mode", &format_args!("{}", self.ms_mode().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
-            .field(
-                "i2c_ctrl_clk_gate_en",
-                &format_args!("{}", self.i2c_ctrl_clk_gate_en().bit()),
-            )
-            .field("i2c_reset", &format_args!("{}", self.i2c_reset().bit()))
-            .field("i2cclk_en", &format_args!("{}", self.i2cclk_en().bit()))
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("ms_mode", &self.ms_mode())
+            .field("trans_start", &self.trans_start())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("i2c_ctrl_clk_gate_en", &self.i2c_ctrl_clk_gate_en())
+            .field("i2c_reset", &self.i2c_reset())
+            .field("i2cclk_en", &self.i2cclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1=push pull,0=open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_i2c/data.rs b/esp32s3-ulp/src/rtc_i2c/data.rs
index 5e45ecf617..0616175fea 100644
--- a/esp32s3-ulp/src/rtc_i2c/data.rs
+++ b/esp32s3-ulp/src/rtc_i2c/data.rs
@@ -31,21 +31,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field("i2c_rdata", &format_args!("{}", self.i2c_rdata().bits()))
-            .field(
-                "slave_tx_data",
-                &format_args!("{}", self.slave_tx_data().bits()),
-            )
-            .field("i2c_done", &format_args!("{}", self.i2c_done().bit()))
+            .field("i2c_rdata", &self.i2c_rdata())
+            .field("slave_tx_data", &self.slave_tx_data())
+            .field("i2c_done", &self.i2c_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:15 - data sent by slave"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_i2c/date.rs b/esp32s3-ulp/src/rtc_i2c/date.rs
index c9d5c9aa7e..149ba7d705 100644
--- a/esp32s3-ulp/src/rtc_i2c/date.rs
+++ b/esp32s3-ulp/src/rtc_i2c/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("i2c_date", &format_args!("{}", self.i2c_date().bits()))
+            .field("i2c_date", &self.i2c_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - version"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_i2c/int_ena.rs b/esp32s3-ulp/src/rtc_i2c/int_ena.rs
index 3588a0a8b3..9ea56e95b2 100644
--- a/esp32s3-ulp/src/rtc_i2c/int_ena.rs
+++ b/esp32s3-ulp/src/rtc_i2c/int_ena.rs
@@ -89,39 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "slave_tran_comp",
-                &format_args!("{}", self.slave_tran_comp().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_tran_comp",
-                &format_args!("{}", self.master_tran_comp().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("ack_err", &format_args!("{}", self.ack_err().bit()))
-            .field("rx_data", &format_args!("{}", self.rx_data().bit()))
-            .field("tx_data", &format_args!("{}", self.tx_data().bit()))
-            .field(
-                "detect_start",
-                &format_args!("{}", self.detect_start().bit()),
-            )
+            .field("slave_tran_comp", &self.slave_tran_comp())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_tran_comp", &self.master_tran_comp())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("ack_err", &self.ack_err())
+            .field("rx_data", &self.rx_data())
+            .field("tx_data", &self.tx_data())
+            .field("detect_start", &self.detect_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable slave transit complete interrupt"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_i2c/int_raw.rs b/esp32s3-ulp/src/rtc_i2c/int_raw.rs
index 77ddd6e574..52e571f869 100644
--- a/esp32s3-ulp/src/rtc_i2c/int_raw.rs
+++ b/esp32s3-ulp/src/rtc_i2c/int_raw.rs
@@ -69,39 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "slave_tran_comp",
-                &format_args!("{}", self.slave_tran_comp().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_tran_comp",
-                &format_args!("{}", self.master_tran_comp().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("ack_err", &format_args!("{}", self.ack_err().bit()))
-            .field("rx_data", &format_args!("{}", self.rx_data().bit()))
-            .field("tx_data", &format_args!("{}", self.tx_data().bit()))
-            .field(
-                "detect_start",
-                &format_args!("{}", self.detect_start().bit()),
-            )
+            .field("slave_tran_comp", &self.slave_tran_comp())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_tran_comp", &self.master_tran_comp())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("ack_err", &self.ack_err())
+            .field("rx_data", &self.rx_data())
+            .field("tx_data", &self.tx_data())
+            .field("detect_start", &self.detect_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s3-ulp/src/rtc_i2c/int_st.rs b/esp32s3-ulp/src/rtc_i2c/int_st.rs
index e0cb24df8f..6766d04dae 100644
--- a/esp32s3-ulp/src/rtc_i2c/int_st.rs
+++ b/esp32s3-ulp/src/rtc_i2c/int_st.rs
@@ -69,39 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "slave_tran_comp",
-                &format_args!("{}", self.slave_tran_comp().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_tran_comp",
-                &format_args!("{}", self.master_tran_comp().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("ack_err", &format_args!("{}", self.ack_err().bit()))
-            .field("rx_data", &format_args!("{}", self.rx_data().bit()))
-            .field("tx_data", &format_args!("{}", self.tx_data().bit()))
-            .field(
-                "detect_start",
-                &format_args!("{}", self.detect_start().bit()),
-            )
+            .field("slave_tran_comp", &self.slave_tran_comp())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_tran_comp", &self.master_tran_comp())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("ack_err", &self.ack_err())
+            .field("rx_data", &self.rx_data())
+            .field("tx_data", &self.tx_data())
+            .field("detect_start", &self.detect_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "interrupt state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3-ulp/src/rtc_i2c/scl_high.rs b/esp32s3-ulp/src/rtc_i2c/scl_high.rs
index 6d52cb95a1..bfef5cffb2 100644
--- a/esp32s3-ulp/src/rtc_i2c/scl_high.rs
+++ b/esp32s3-ulp/src/rtc_i2c/scl_high.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH")
-            .field("period", &format_args!("{}", self.period().bits()))
+            .field("period", &self.period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - time period that scl = 1"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_i2c/scl_low.rs b/esp32s3-ulp/src/rtc_i2c/scl_low.rs
index b22c6e2f38..b8a3e8f8d7 100644
--- a/esp32s3-ulp/src/rtc_i2c/scl_low.rs
+++ b/esp32s3-ulp/src/rtc_i2c/scl_low.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW")
-            .field("period", &format_args!("{}", self.period().bits()))
+            .field("period", &self.period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - time period that scl =0"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_i2c/scl_start_period.rs b/esp32s3-ulp/src/rtc_i2c/scl_start_period.rs
index 0a05440618..e9bb81ca01 100644
--- a/esp32s3-ulp/src/rtc_i2c/scl_start_period.rs
+++ b/esp32s3-ulp/src/rtc_i2c/scl_start_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_PERIOD")
-            .field(
-                "scl_start_period",
-                &format_args!("{}", self.scl_start_period().bits()),
-            )
+            .field("scl_start_period", &self.scl_start_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - time period for SCL to toggle after I2C start is triggered"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_i2c/scl_stop_period.rs b/esp32s3-ulp/src/rtc_i2c/scl_stop_period.rs
index 078b53148e..373679ba9a 100644
--- a/esp32s3-ulp/src/rtc_i2c/scl_stop_period.rs
+++ b/esp32s3-ulp/src/rtc_i2c/scl_stop_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_PERIOD")
-            .field(
-                "scl_stop_period",
-                &format_args!("{}", self.scl_stop_period().bits()),
-            )
+            .field("scl_stop_period", &self.scl_stop_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - time period for SCL to stop after I2C end is triggered"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_i2c/sda_duty.rs b/esp32s3-ulp/src/rtc_i2c/sda_duty.rs
index 61b4edfe07..02ecbe7f58 100644
--- a/esp32s3-ulp/src/rtc_i2c/sda_duty.rs
+++ b/esp32s3-ulp/src/rtc_i2c/sda_duty.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_DUTY")
-            .field("num", &format_args!("{}", self.num().bits()))
+            .field("num", &self.num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - time period for SDA to toggle after SCL goes low"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_i2c/slave_addr.rs b/esp32s3-ulp/src/rtc_i2c/slave_addr.rs
index 6795ba25a3..ac82e1ef0a 100644
--- a/esp32s3-ulp/src/rtc_i2c/slave_addr.rs
+++ b/esp32s3-ulp/src/rtc_i2c/slave_addr.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE_ADDR")
-            .field("slave_addr", &format_args!("{}", self.slave_addr().bits()))
-            .field(
-                "addr_10bit_en",
-                &format_args!("{}", self.addr_10bit_en().bit()),
-            )
+            .field("slave_addr", &self.slave_addr())
+            .field("addr_10bit_en", &self.addr_10bit_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - slave address"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_i2c/status.rs b/esp32s3-ulp/src/rtc_i2c/status.rs
index c84cadbdaa..829a44a2e9 100644
--- a/esp32s3-ulp/src/rtc_i2c/status.rs
+++ b/esp32s3-ulp/src/rtc_i2c/status.rs
@@ -76,34 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("ack_rec", &format_args!("{}", self.ack_rec().bit()))
-            .field("slave_rw", &format_args!("{}", self.slave_rw().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field(
-                "slave_addressed",
-                &format_args!("{}", self.slave_addressed().bit()),
-            )
-            .field("byte_trans", &format_args!("{}", self.byte_trans().bit()))
-            .field("op_cnt", &format_args!("{}", self.op_cnt().bits()))
-            .field("shift", &format_args!("{}", self.shift().bits()))
-            .field(
-                "scl_main_state_last",
-                &format_args!("{}", self.scl_main_state_last().bits()),
-            )
-            .field(
-                "scl_state_last",
-                &format_args!("{}", self.scl_state_last().bits()),
-            )
+            .field("ack_rec", &self.ack_rec())
+            .field("slave_rw", &self.slave_rw())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("slave_addressed", &self.slave_addressed())
+            .field("byte_trans", &self.byte_trans())
+            .field("op_cnt", &self.op_cnt())
+            .field("shift", &self.shift())
+            .field("scl_main_state_last", &self.scl_main_state_last())
+            .field("scl_state_last", &self.scl_state_last())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "get i2c status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32s3-ulp/src/rtc_i2c/to.rs b/esp32s3-ulp/src/rtc_i2c/to.rs
index c7565d564c..68d04baaa5 100644
--- a/esp32s3-ulp/src/rtc_i2c/to.rs
+++ b/esp32s3-ulp/src/rtc_i2c/to.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO")
-            .field("time_out", &format_args!("{}", self.time_out().bits()))
+            .field("time_out", &self.time_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - time out threshold"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/date.rs b/esp32s3-ulp/src/rtc_io/date.rs
index 72b3a143ca..5bc973b2ce 100644
--- a/esp32s3-ulp/src/rtc_io/date.rs
+++ b/esp32s3-ulp/src/rtc_io/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3-ulp/src/rtc_io/enable.rs b/esp32s3-ulp/src/rtc_io/enable.rs
index 74376d3e9f..dcf8ec84aa 100644
--- a/esp32s3-ulp/src/rtc_io/enable.rs
+++ b/esp32s3-ulp/src/rtc_io/enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE")
-            .field(
-                "gpio_enable",
-                &format_args!("{}", self.gpio_enable().bits()),
-            )
+            .field("gpio_enable", &self.gpio_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 enable"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/ext_wakeup0.rs b/esp32s3-ulp/src/rtc_io/ext_wakeup0.rs
index e831a5f686..c44a7b32d9 100644
--- a/esp32s3-ulp/src/rtc_io/ext_wakeup0.rs
+++ b/esp32s3-ulp/src/rtc_io/ext_wakeup0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP0")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 27:31 - ******* Description configure***"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/in_.rs b/esp32s3-ulp/src/rtc_io/in_.rs
index f2000a9738..9a1e8b28c5 100644
--- a/esp32s3-ulp/src/rtc_io/in_.rs
+++ b/esp32s3-ulp/src/rtc_io/in_.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("IN")
-            .field("next", &format_args!("{}", self.next().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("IN").field("next", &self.next()).finish()
     }
 }
 #[doc = "RTC GPIO input data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s3-ulp/src/rtc_io/out.rs b/esp32s3-ulp/src/rtc_io/out.rs
index 8367d82ea0..e2d131fdec 100644
--- a/esp32s3-ulp/src/rtc_io/out.rs
+++ b/esp32s3-ulp/src/rtc_io/out.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("OUT")
-            .field("data", &format_args!("{}", self.data().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("OUT").field("data", &self.data()).finish()
     }
 }
 impl W {
diff --git a/esp32s3-ulp/src/rtc_io/pad_dac1.rs b/esp32s3-ulp/src/rtc_io/pad_dac1.rs
index 75e812d000..c8805f2db3 100644
--- a/esp32s3-ulp/src/rtc_io/pad_dac1.rs
+++ b/esp32s3-ulp/src/rtc_io/pad_dac1.rs
@@ -116,51 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_DAC1")
-            .field("pdac1_dac", &format_args!("{}", self.pdac1_dac().bits()))
-            .field(
-                "pdac1_xpd_dac",
-                &format_args!("{}", self.pdac1_xpd_dac().bit()),
-            )
-            .field(
-                "pdac1_dac_xpd_force",
-                &format_args!("{}", self.pdac1_dac_xpd_force().bit()),
-            )
-            .field(
-                "pdac1_fun_ie",
-                &format_args!("{}", self.pdac1_fun_ie().bit()),
-            )
-            .field(
-                "pdac1_slp_oe",
-                &format_args!("{}", self.pdac1_slp_oe().bit()),
-            )
-            .field(
-                "pdac1_slp_ie",
-                &format_args!("{}", self.pdac1_slp_ie().bit()),
-            )
-            .field(
-                "pdac1_slp_sel",
-                &format_args!("{}", self.pdac1_slp_sel().bit()),
-            )
-            .field(
-                "pdac1_fun_sel",
-                &format_args!("{}", self.pdac1_fun_sel().bits()),
-            )
-            .field(
-                "pdac1_mux_sel",
-                &format_args!("{}", self.pdac1_mux_sel().bit()),
-            )
-            .field("pdac1_rue", &format_args!("{}", self.pdac1_rue().bit()))
-            .field("pdac1_rde", &format_args!("{}", self.pdac1_rde().bit()))
-            .field("pdac1_drv", &format_args!("{}", self.pdac1_drv().bits()))
+            .field("pdac1_dac", &self.pdac1_dac())
+            .field("pdac1_xpd_dac", &self.pdac1_xpd_dac())
+            .field("pdac1_dac_xpd_force", &self.pdac1_dac_xpd_force())
+            .field("pdac1_fun_ie", &self.pdac1_fun_ie())
+            .field("pdac1_slp_oe", &self.pdac1_slp_oe())
+            .field("pdac1_slp_ie", &self.pdac1_slp_ie())
+            .field("pdac1_slp_sel", &self.pdac1_slp_sel())
+            .field("pdac1_fun_sel", &self.pdac1_fun_sel())
+            .field("pdac1_mux_sel", &self.pdac1_mux_sel())
+            .field("pdac1_rue", &self.pdac1_rue())
+            .field("pdac1_rde", &self.pdac1_rde())
+            .field("pdac1_drv", &self.pdac1_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_DAC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:10 - PDAC1_DAC"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pad_dac2.rs b/esp32s3-ulp/src/rtc_io/pad_dac2.rs
index 4385f207d5..c03ec538d4 100644
--- a/esp32s3-ulp/src/rtc_io/pad_dac2.rs
+++ b/esp32s3-ulp/src/rtc_io/pad_dac2.rs
@@ -116,51 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_DAC2")
-            .field("pdac2_dac", &format_args!("{}", self.pdac2_dac().bits()))
-            .field(
-                "pdac2_xpd_dac",
-                &format_args!("{}", self.pdac2_xpd_dac().bit()),
-            )
-            .field(
-                "pdac2_dac_xpd_force",
-                &format_args!("{}", self.pdac2_dac_xpd_force().bit()),
-            )
-            .field(
-                "pdac2_fun_ie",
-                &format_args!("{}", self.pdac2_fun_ie().bit()),
-            )
-            .field(
-                "pdac2_slp_oe",
-                &format_args!("{}", self.pdac2_slp_oe().bit()),
-            )
-            .field(
-                "pdac2_slp_ie",
-                &format_args!("{}", self.pdac2_slp_ie().bit()),
-            )
-            .field(
-                "pdac2_slp_sel",
-                &format_args!("{}", self.pdac2_slp_sel().bit()),
-            )
-            .field(
-                "pdac2_fun_sel",
-                &format_args!("{}", self.pdac2_fun_sel().bits()),
-            )
-            .field(
-                "pdac2_mux_sel",
-                &format_args!("{}", self.pdac2_mux_sel().bit()),
-            )
-            .field("pdac2_rue", &format_args!("{}", self.pdac2_rue().bit()))
-            .field("pdac2_rde", &format_args!("{}", self.pdac2_rde().bit()))
-            .field("pdac2_drv", &format_args!("{}", self.pdac2_drv().bits()))
+            .field("pdac2_dac", &self.pdac2_dac())
+            .field("pdac2_xpd_dac", &self.pdac2_xpd_dac())
+            .field("pdac2_dac_xpd_force", &self.pdac2_dac_xpd_force())
+            .field("pdac2_fun_ie", &self.pdac2_fun_ie())
+            .field("pdac2_slp_oe", &self.pdac2_slp_oe())
+            .field("pdac2_slp_ie", &self.pdac2_slp_ie())
+            .field("pdac2_slp_sel", &self.pdac2_slp_sel())
+            .field("pdac2_fun_sel", &self.pdac2_fun_sel())
+            .field("pdac2_mux_sel", &self.pdac2_mux_sel())
+            .field("pdac2_rue", &self.pdac2_rue())
+            .field("pdac2_rde", &self.pdac2_rde())
+            .field("pdac2_drv", &self.pdac2_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_DAC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:10 - PDAC2_DAC"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin0.rs b/esp32s3-ulp/src/rtc_io/pin0.rs
index acc40aed9c..ebe0378dbe 100644
--- a/esp32s3-ulp/src/rtc_io/pin0.rs
+++ b/esp32s3-ulp/src/rtc_io/pin0.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN0")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin1.rs b/esp32s3-ulp/src/rtc_io/pin1.rs
index 3a67761972..fdefc3b18e 100644
--- a/esp32s3-ulp/src/rtc_io/pin1.rs
+++ b/esp32s3-ulp/src/rtc_io/pin1.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN1")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin10.rs b/esp32s3-ulp/src/rtc_io/pin10.rs
index e6afb3d56a..b6a7226434 100644
--- a/esp32s3-ulp/src/rtc_io/pin10.rs
+++ b/esp32s3-ulp/src/rtc_io/pin10.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN10")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin11.rs b/esp32s3-ulp/src/rtc_io/pin11.rs
index ff272a18da..f1b31b9896 100644
--- a/esp32s3-ulp/src/rtc_io/pin11.rs
+++ b/esp32s3-ulp/src/rtc_io/pin11.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN11")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin12.rs b/esp32s3-ulp/src/rtc_io/pin12.rs
index 0caa99b51b..9bf1a0c669 100644
--- a/esp32s3-ulp/src/rtc_io/pin12.rs
+++ b/esp32s3-ulp/src/rtc_io/pin12.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN12")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin13.rs b/esp32s3-ulp/src/rtc_io/pin13.rs
index b4d44b5f54..3005a64ff3 100644
--- a/esp32s3-ulp/src/rtc_io/pin13.rs
+++ b/esp32s3-ulp/src/rtc_io/pin13.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN13")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin14.rs b/esp32s3-ulp/src/rtc_io/pin14.rs
index 7cdce6f29c..7dce93f825 100644
--- a/esp32s3-ulp/src/rtc_io/pin14.rs
+++ b/esp32s3-ulp/src/rtc_io/pin14.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN14")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin15.rs b/esp32s3-ulp/src/rtc_io/pin15.rs
index 1ec5f39fd8..f5dd37c873 100644
--- a/esp32s3-ulp/src/rtc_io/pin15.rs
+++ b/esp32s3-ulp/src/rtc_io/pin15.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN15")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin16.rs b/esp32s3-ulp/src/rtc_io/pin16.rs
index 1b220e9480..ed25ffd9f8 100644
--- a/esp32s3-ulp/src/rtc_io/pin16.rs
+++ b/esp32s3-ulp/src/rtc_io/pin16.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN16")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN16_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin17.rs b/esp32s3-ulp/src/rtc_io/pin17.rs
index fc3ab76a77..b018411d8a 100644
--- a/esp32s3-ulp/src/rtc_io/pin17.rs
+++ b/esp32s3-ulp/src/rtc_io/pin17.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN17")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN17_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin18.rs b/esp32s3-ulp/src/rtc_io/pin18.rs
index 7254f88267..2ef319b45d 100644
--- a/esp32s3-ulp/src/rtc_io/pin18.rs
+++ b/esp32s3-ulp/src/rtc_io/pin18.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN18")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN18_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin19.rs b/esp32s3-ulp/src/rtc_io/pin19.rs
index a02f7ad7e0..0de0ecf719 100644
--- a/esp32s3-ulp/src/rtc_io/pin19.rs
+++ b/esp32s3-ulp/src/rtc_io/pin19.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN19")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN19_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin2.rs b/esp32s3-ulp/src/rtc_io/pin2.rs
index d4ab02fa44..5b02341eff 100644
--- a/esp32s3-ulp/src/rtc_io/pin2.rs
+++ b/esp32s3-ulp/src/rtc_io/pin2.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN2")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin20.rs b/esp32s3-ulp/src/rtc_io/pin20.rs
index ec658ac3d0..e20761d554 100644
--- a/esp32s3-ulp/src/rtc_io/pin20.rs
+++ b/esp32s3-ulp/src/rtc_io/pin20.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN20")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN20_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin21.rs b/esp32s3-ulp/src/rtc_io/pin21.rs
index 85ea5c2c15..5c390e1b4f 100644
--- a/esp32s3-ulp/src/rtc_io/pin21.rs
+++ b/esp32s3-ulp/src/rtc_io/pin21.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN21")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN21_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin3.rs b/esp32s3-ulp/src/rtc_io/pin3.rs
index b89f7501de..446622aba7 100644
--- a/esp32s3-ulp/src/rtc_io/pin3.rs
+++ b/esp32s3-ulp/src/rtc_io/pin3.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN3")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin4.rs b/esp32s3-ulp/src/rtc_io/pin4.rs
index 51e674c094..7fae01e189 100644
--- a/esp32s3-ulp/src/rtc_io/pin4.rs
+++ b/esp32s3-ulp/src/rtc_io/pin4.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN4")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin5.rs b/esp32s3-ulp/src/rtc_io/pin5.rs
index 9544a00f0e..6a0fbe97a2 100644
--- a/esp32s3-ulp/src/rtc_io/pin5.rs
+++ b/esp32s3-ulp/src/rtc_io/pin5.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN5")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin6.rs b/esp32s3-ulp/src/rtc_io/pin6.rs
index de94439fd4..9be50e6709 100644
--- a/esp32s3-ulp/src/rtc_io/pin6.rs
+++ b/esp32s3-ulp/src/rtc_io/pin6.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN6")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin7.rs b/esp32s3-ulp/src/rtc_io/pin7.rs
index 8c6a8f8348..198998f551 100644
--- a/esp32s3-ulp/src/rtc_io/pin7.rs
+++ b/esp32s3-ulp/src/rtc_io/pin7.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN7")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin8.rs b/esp32s3-ulp/src/rtc_io/pin8.rs
index 40f932586b..dec9400ba7 100644
--- a/esp32s3-ulp/src/rtc_io/pin8.rs
+++ b/esp32s3-ulp/src/rtc_io/pin8.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN8")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/pin9.rs b/esp32s3-ulp/src/rtc_io/pin9.rs
index 119b64f71a..a465ff6155 100644
--- a/esp32s3-ulp/src/rtc_io/pin9.rs
+++ b/esp32s3-ulp/src/rtc_io/pin9.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN9")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/rtc_debug_sel.rs b/esp32s3-ulp/src/rtc_io/rtc_debug_sel.rs
index 51b13d72d7..feaf60428a 100644
--- a/esp32s3-ulp/src/rtc_io/rtc_debug_sel.rs
+++ b/esp32s3-ulp/src/rtc_io/rtc_debug_sel.rs
@@ -62,24 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_DEBUG_SEL")
-            .field("debug_sel0", &format_args!("{}", self.debug_sel0().bits()))
-            .field("debug_sel1", &format_args!("{}", self.debug_sel1().bits()))
-            .field("debug_sel2", &format_args!("{}", self.debug_sel2().bits()))
-            .field("debug_sel3", &format_args!("{}", self.debug_sel3().bits()))
-            .field("debug_sel4", &format_args!("{}", self.debug_sel4().bits()))
-            .field(
-                "debug_12m_no_gating",
-                &format_args!("{}", self.debug_12m_no_gating().bit()),
-            )
+            .field("debug_sel0", &self.debug_sel0())
+            .field("debug_sel1", &self.debug_sel1())
+            .field("debug_sel2", &self.debug_sel2())
+            .field("debug_sel3", &self.debug_sel3())
+            .field("debug_sel4", &self.debug_sel4())
+            .field("debug_12m_no_gating", &self.debug_12m_no_gating())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_DEBUG_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - configure rtc debug"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/rtc_pad19.rs b/esp32s3-ulp/src/rtc_io/rtc_pad19.rs
index 97f7c22efa..cdc4590708 100644
--- a/esp32s3-ulp/src/rtc_io/rtc_pad19.rs
+++ b/esp32s3-ulp/src/rtc_io/rtc_pad19.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_PAD19")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_PAD19_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/rtc_pad20.rs b/esp32s3-ulp/src/rtc_io/rtc_pad20.rs
index 829c1aeac5..ee52eb8887 100644
--- a/esp32s3-ulp/src/rtc_io/rtc_pad20.rs
+++ b/esp32s3-ulp/src/rtc_io/rtc_pad20.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_PAD20")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_PAD20_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/rtc_pad21.rs b/esp32s3-ulp/src/rtc_io/rtc_pad21.rs
index ac18a4607d..ec64424b7c 100644
--- a/esp32s3-ulp/src/rtc_io/rtc_pad21.rs
+++ b/esp32s3-ulp/src/rtc_io/rtc_pad21.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_PAD21")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_PAD21_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/sar_i2c_io.rs b/esp32s3-ulp/src/rtc_io/sar_i2c_io.rs
index cc37532f5a..9cdf9d4186 100644
--- a/esp32s3-ulp/src/rtc_io/sar_i2c_io.rs
+++ b/esp32s3-ulp/src/rtc_io/sar_i2c_io.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_I2C_IO")
-            .field(
-                "sar_debug_bit_sel",
-                &format_args!("{}", self.sar_debug_bit_sel().bits()),
-            )
-            .field(
-                "sar_i2c_scl_sel",
-                &format_args!("{}", self.sar_i2c_scl_sel().bits()),
-            )
-            .field(
-                "sar_i2c_sda_sel",
-                &format_args!("{}", self.sar_i2c_sda_sel().bits()),
-            )
+            .field("sar_debug_bit_sel", &self.sar_debug_bit_sel())
+            .field("sar_i2c_scl_sel", &self.sar_i2c_scl_sel())
+            .field("sar_i2c_sda_sel", &self.sar_i2c_sda_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_I2C_IO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:27 - ******* Description configure***"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/status.rs b/esp32s3-ulp/src/rtc_io/status.rs
index 60a16f6eef..ce7b735b0f 100644
--- a/esp32s3-ulp/src/rtc_io/status.rs
+++ b/esp32s3-ulp/src/rtc_io/status.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("STATUS")
-            .field("int", &format_args!("{}", self.int().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("STATUS").field("int", &self.int()).finish()
     }
 }
 impl W {
diff --git a/esp32s3-ulp/src/rtc_io/touch_ctrl.rs b/esp32s3-ulp/src/rtc_io/touch_ctrl.rs
index 5a57b687fe..2624ca411e 100644
--- a/esp32s3-ulp/src/rtc_io/touch_ctrl.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_CTRL")
-            .field(
-                "io_touch_bufsel",
-                &format_args!("{}", self.io_touch_bufsel().bits()),
-            )
-            .field(
-                "io_touch_bufmode",
-                &format_args!("{}", self.io_touch_bufmode().bit()),
-            )
+            .field("io_touch_bufsel", &self.io_touch_bufsel())
+            .field("io_touch_bufmode", &self.io_touch_bufmode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - BUF_SEL when touch work without fsm"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/touch_pad0.rs b/esp32s3-ulp/src/rtc_io/touch_pad0.rs
index 7a2669777b..42c0795fa1 100644
--- a/esp32s3-ulp/src/rtc_io/touch_pad0.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_pad0.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD0")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/touch_pad1.rs b/esp32s3-ulp/src/rtc_io/touch_pad1.rs
index 16b3f0d36d..398aef5f43 100644
--- a/esp32s3-ulp/src/rtc_io/touch_pad1.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_pad1.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD1")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/touch_pad10.rs b/esp32s3-ulp/src/rtc_io/touch_pad10.rs
index ebe80d56c0..afb2523f1a 100644
--- a/esp32s3-ulp/src/rtc_io/touch_pad10.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_pad10.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD10")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/touch_pad11.rs b/esp32s3-ulp/src/rtc_io/touch_pad11.rs
index 01ea66a137..cfae1f4823 100644
--- a/esp32s3-ulp/src/rtc_io/touch_pad11.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_pad11.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD11")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/touch_pad12.rs b/esp32s3-ulp/src/rtc_io/touch_pad12.rs
index 3dc47b7376..79f1c06a2b 100644
--- a/esp32s3-ulp/src/rtc_io/touch_pad12.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_pad12.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD12")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/touch_pad13.rs b/esp32s3-ulp/src/rtc_io/touch_pad13.rs
index 1b3ae1c584..9a1418d62b 100644
--- a/esp32s3-ulp/src/rtc_io/touch_pad13.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_pad13.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD13")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/touch_pad14.rs b/esp32s3-ulp/src/rtc_io/touch_pad14.rs
index 5832c4ce85..5fdde4fd4d 100644
--- a/esp32s3-ulp/src/rtc_io/touch_pad14.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_pad14.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD14")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/touch_pad2.rs b/esp32s3-ulp/src/rtc_io/touch_pad2.rs
index 8d94286e48..37563006bf 100644
--- a/esp32s3-ulp/src/rtc_io/touch_pad2.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_pad2.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD2")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/touch_pad3.rs b/esp32s3-ulp/src/rtc_io/touch_pad3.rs
index 1a6752c02b..060c057597 100644
--- a/esp32s3-ulp/src/rtc_io/touch_pad3.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_pad3.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD3")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/touch_pad4.rs b/esp32s3-ulp/src/rtc_io/touch_pad4.rs
index c46462b6d6..c40e4c6e9d 100644
--- a/esp32s3-ulp/src/rtc_io/touch_pad4.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_pad4.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD4")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/touch_pad5.rs b/esp32s3-ulp/src/rtc_io/touch_pad5.rs
index 2fd3554beb..2e91ece0de 100644
--- a/esp32s3-ulp/src/rtc_io/touch_pad5.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_pad5.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD5")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/touch_pad6.rs b/esp32s3-ulp/src/rtc_io/touch_pad6.rs
index 3d08bac42c..b3f8fb7066 100644
--- a/esp32s3-ulp/src/rtc_io/touch_pad6.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_pad6.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD6")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/touch_pad7.rs b/esp32s3-ulp/src/rtc_io/touch_pad7.rs
index f9aa9420b7..0c6105ed7e 100644
--- a/esp32s3-ulp/src/rtc_io/touch_pad7.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_pad7.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD7")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/touch_pad8.rs b/esp32s3-ulp/src/rtc_io/touch_pad8.rs
index cc23a4ca77..8f98942d5d 100644
--- a/esp32s3-ulp/src/rtc_io/touch_pad8.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_pad8.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD8")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/touch_pad9.rs b/esp32s3-ulp/src/rtc_io/touch_pad9.rs
index cf90e2e336..b4ca397664 100644
--- a/esp32s3-ulp/src/rtc_io/touch_pad9.rs
+++ b/esp32s3-ulp/src/rtc_io/touch_pad9.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD9")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/xtal_32n_pad.rs b/esp32s3-ulp/src/rtc_io/xtal_32n_pad.rs
index 2740083065..14c0ded41e 100644
--- a/esp32s3-ulp/src/rtc_io/xtal_32n_pad.rs
+++ b/esp32s3-ulp/src/rtc_io/xtal_32n_pad.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL_32N_PAD")
-            .field("x32n_fun_ie", &format_args!("{}", self.x32n_fun_ie().bit()))
-            .field("x32n_slp_oe", &format_args!("{}", self.x32n_slp_oe().bit()))
-            .field("x32n_slp_ie", &format_args!("{}", self.x32n_slp_ie().bit()))
-            .field(
-                "x32n_slp_sel",
-                &format_args!("{}", self.x32n_slp_sel().bit()),
-            )
-            .field(
-                "x32n_fun_sel",
-                &format_args!("{}", self.x32n_fun_sel().bits()),
-            )
-            .field(
-                "x32n_mux_sel",
-                &format_args!("{}", self.x32n_mux_sel().bit()),
-            )
-            .field("x32n_rue", &format_args!("{}", self.x32n_rue().bit()))
-            .field("x32n_rde", &format_args!("{}", self.x32n_rde().bit()))
-            .field("x32n_drv", &format_args!("{}", self.x32n_drv().bits()))
+            .field("x32n_fun_ie", &self.x32n_fun_ie())
+            .field("x32n_slp_oe", &self.x32n_slp_oe())
+            .field("x32n_slp_ie", &self.x32n_slp_ie())
+            .field("x32n_slp_sel", &self.x32n_slp_sel())
+            .field("x32n_fun_sel", &self.x32n_fun_sel())
+            .field("x32n_mux_sel", &self.x32n_mux_sel())
+            .field("x32n_rue", &self.x32n_rue())
+            .field("x32n_rde", &self.x32n_rde())
+            .field("x32n_drv", &self.x32n_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL_32N_PAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/xtal_32p_pad.rs b/esp32s3-ulp/src/rtc_io/xtal_32p_pad.rs
index 4482bc1f3c..a0cd0a6d6f 100644
--- a/esp32s3-ulp/src/rtc_io/xtal_32p_pad.rs
+++ b/esp32s3-ulp/src/rtc_io/xtal_32p_pad.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL_32P_PAD")
-            .field("x32p_fun_ie", &format_args!("{}", self.x32p_fun_ie().bit()))
-            .field("x32p_slp_oe", &format_args!("{}", self.x32p_slp_oe().bit()))
-            .field("x32p_slp_ie", &format_args!("{}", self.x32p_slp_ie().bit()))
-            .field(
-                "x32p_slp_sel",
-                &format_args!("{}", self.x32p_slp_sel().bit()),
-            )
-            .field(
-                "x32p_fun_sel",
-                &format_args!("{}", self.x32p_fun_sel().bits()),
-            )
-            .field(
-                "x32p_mux_sel",
-                &format_args!("{}", self.x32p_mux_sel().bit()),
-            )
-            .field("x32p_rue", &format_args!("{}", self.x32p_rue().bit()))
-            .field("x32p_rde", &format_args!("{}", self.x32p_rde().bit()))
-            .field("x32p_drv", &format_args!("{}", self.x32p_drv().bits()))
+            .field("x32p_fun_ie", &self.x32p_fun_ie())
+            .field("x32p_slp_oe", &self.x32p_slp_oe())
+            .field("x32p_slp_ie", &self.x32p_slp_ie())
+            .field("x32p_slp_sel", &self.x32p_slp_sel())
+            .field("x32p_fun_sel", &self.x32p_fun_sel())
+            .field("x32p_mux_sel", &self.x32p_mux_sel())
+            .field("x32p_rue", &self.x32p_rue())
+            .field("x32p_rde", &self.x32p_rde())
+            .field("x32p_drv", &self.x32p_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL_32P_PAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/rtc_io/xtl_ext_ctr.rs b/esp32s3-ulp/src/rtc_io/xtl_ext_ctr.rs
index 26aaa51228..4f8597a9d3 100644
--- a/esp32s3-ulp/src/rtc_io/xtl_ext_ctr.rs
+++ b/esp32s3-ulp/src/rtc_io/xtl_ext_ctr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTL_EXT_CTR")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTL_EXT_CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 27:31 - select RTC GPIO 0 ~ 17 to control XTAL"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/sens/sar_cocpu_int_ena.rs b/esp32s3-ulp/src/sens/sar_cocpu_int_ena.rs
index 38f9bf265a..7cb1e6dba5 100644
--- a/esp32s3-ulp/src/sens/sar_cocpu_int_ena.rs
+++ b/esp32s3-ulp/src/sens/sar_cocpu_int_ena.rs
@@ -120,64 +120,43 @@ impl core::fmt::Debug for R {
         f.debug_struct("SAR_COCPU_INT_ENA")
             .field(
                 "sar_cocpu_touch_done_int_ena",
-                &format_args!("{}", self.sar_cocpu_touch_done_int_ena().bit()),
+                &self.sar_cocpu_touch_done_int_ena(),
             )
             .field(
                 "sar_cocpu_touch_inactive_int_ena",
-                &format_args!("{}", self.sar_cocpu_touch_inactive_int_ena().bit()),
+                &self.sar_cocpu_touch_inactive_int_ena(),
             )
             .field(
                 "sar_cocpu_touch_active_int_ena",
-                &format_args!("{}", self.sar_cocpu_touch_active_int_ena().bit()),
+                &self.sar_cocpu_touch_active_int_ena(),
             )
             .field(
                 "sar_cocpu_saradc1_int_ena",
-                &format_args!("{}", self.sar_cocpu_saradc1_int_ena().bit()),
+                &self.sar_cocpu_saradc1_int_ena(),
             )
             .field(
                 "sar_cocpu_saradc2_int_ena",
-                &format_args!("{}", self.sar_cocpu_saradc2_int_ena().bit()),
-            )
-            .field(
-                "sar_cocpu_tsens_int_ena",
-                &format_args!("{}", self.sar_cocpu_tsens_int_ena().bit()),
-            )
-            .field(
-                "sar_cocpu_start_int_ena",
-                &format_args!("{}", self.sar_cocpu_start_int_ena().bit()),
-            )
-            .field(
-                "sar_cocpu_sw_int_ena",
-                &format_args!("{}", self.sar_cocpu_sw_int_ena().bit()),
-            )
-            .field(
-                "sar_cocpu_swd_int_ena",
-                &format_args!("{}", self.sar_cocpu_swd_int_ena().bit()),
+                &self.sar_cocpu_saradc2_int_ena(),
             )
+            .field("sar_cocpu_tsens_int_ena", &self.sar_cocpu_tsens_int_ena())
+            .field("sar_cocpu_start_int_ena", &self.sar_cocpu_start_int_ena())
+            .field("sar_cocpu_sw_int_ena", &self.sar_cocpu_sw_int_ena())
+            .field("sar_cocpu_swd_int_ena", &self.sar_cocpu_swd_int_ena())
             .field(
                 "sar_cocpu_touch_timeout_int_ena",
-                &format_args!("{}", self.sar_cocpu_touch_timeout_int_ena().bit()),
+                &self.sar_cocpu_touch_timeout_int_ena(),
             )
             .field(
                 "sar_cocpu_touch_approach_loop_done_int_ena",
-                &format_args!(
-                    "{}",
-                    self.sar_cocpu_touch_approach_loop_done_int_ena().bit()
-                ),
+                &self.sar_cocpu_touch_approach_loop_done_int_ena(),
             )
             .field(
                 "sar_cocpu_touch_scan_done_int_ena",
-                &format_args!("{}", self.sar_cocpu_touch_scan_done_int_ena().bit()),
+                &self.sar_cocpu_touch_scan_done_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - int enable of touch done"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/sens/sar_cocpu_int_raw.rs b/esp32s3-ulp/src/sens/sar_cocpu_int_raw.rs
index eb37023427..4f2b22c966 100644
--- a/esp32s3-ulp/src/sens/sar_cocpu_int_raw.rs
+++ b/esp32s3-ulp/src/sens/sar_cocpu_int_raw.rs
@@ -94,64 +94,43 @@ impl core::fmt::Debug for R {
         f.debug_struct("SAR_COCPU_INT_RAW")
             .field(
                 "sar_cocpu_touch_done_int_raw",
-                &format_args!("{}", self.sar_cocpu_touch_done_int_raw().bit()),
+                &self.sar_cocpu_touch_done_int_raw(),
             )
             .field(
                 "sar_cocpu_touch_inactive_int_raw",
-                &format_args!("{}", self.sar_cocpu_touch_inactive_int_raw().bit()),
+                &self.sar_cocpu_touch_inactive_int_raw(),
             )
             .field(
                 "sar_cocpu_touch_active_int_raw",
-                &format_args!("{}", self.sar_cocpu_touch_active_int_raw().bit()),
+                &self.sar_cocpu_touch_active_int_raw(),
             )
             .field(
                 "sar_cocpu_saradc1_int_raw",
-                &format_args!("{}", self.sar_cocpu_saradc1_int_raw().bit()),
+                &self.sar_cocpu_saradc1_int_raw(),
             )
             .field(
                 "sar_cocpu_saradc2_int_raw",
-                &format_args!("{}", self.sar_cocpu_saradc2_int_raw().bit()),
-            )
-            .field(
-                "sar_cocpu_tsens_int_raw",
-                &format_args!("{}", self.sar_cocpu_tsens_int_raw().bit()),
-            )
-            .field(
-                "sar_cocpu_start_int_raw",
-                &format_args!("{}", self.sar_cocpu_start_int_raw().bit()),
-            )
-            .field(
-                "sar_cocpu_sw_int_raw",
-                &format_args!("{}", self.sar_cocpu_sw_int_raw().bit()),
-            )
-            .field(
-                "sar_cocpu_swd_int_raw",
-                &format_args!("{}", self.sar_cocpu_swd_int_raw().bit()),
+                &self.sar_cocpu_saradc2_int_raw(),
             )
+            .field("sar_cocpu_tsens_int_raw", &self.sar_cocpu_tsens_int_raw())
+            .field("sar_cocpu_start_int_raw", &self.sar_cocpu_start_int_raw())
+            .field("sar_cocpu_sw_int_raw", &self.sar_cocpu_sw_int_raw())
+            .field("sar_cocpu_swd_int_raw", &self.sar_cocpu_swd_int_raw())
             .field(
                 "sar_cocpu_touch_timeout_int_raw",
-                &format_args!("{}", self.sar_cocpu_touch_timeout_int_raw().bit()),
+                &self.sar_cocpu_touch_timeout_int_raw(),
             )
             .field(
                 "sar_cocpu_touch_approach_loop_done_int_raw",
-                &format_args!(
-                    "{}",
-                    self.sar_cocpu_touch_approach_loop_done_int_raw().bit()
-                ),
+                &self.sar_cocpu_touch_approach_loop_done_int_raw(),
             )
             .field(
                 "sar_cocpu_touch_scan_done_int_raw",
-                &format_args!("{}", self.sar_cocpu_touch_scan_done_int_raw().bit()),
+                &self.sar_cocpu_touch_scan_done_int_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "the interrupt raw of ulp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_cocpu_int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_COCPU_INT_RAW_SPEC;
 impl crate::RegisterSpec for SAR_COCPU_INT_RAW_SPEC {
diff --git a/esp32s3-ulp/src/sens/sar_cocpu_int_st.rs b/esp32s3-ulp/src/sens/sar_cocpu_int_st.rs
index d3b02bfb27..1c4c60cadc 100644
--- a/esp32s3-ulp/src/sens/sar_cocpu_int_st.rs
+++ b/esp32s3-ulp/src/sens/sar_cocpu_int_st.rs
@@ -94,61 +94,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("SAR_COCPU_INT_ST")
             .field(
                 "sar_cocpu_touch_done_int_st",
-                &format_args!("{}", self.sar_cocpu_touch_done_int_st().bit()),
+                &self.sar_cocpu_touch_done_int_st(),
             )
             .field(
                 "sar_cocpu_touch_inactive_int_st",
-                &format_args!("{}", self.sar_cocpu_touch_inactive_int_st().bit()),
+                &self.sar_cocpu_touch_inactive_int_st(),
             )
             .field(
                 "sar_cocpu_touch_active_int_st",
-                &format_args!("{}", self.sar_cocpu_touch_active_int_st().bit()),
-            )
-            .field(
-                "sar_cocpu_saradc1_int_st",
-                &format_args!("{}", self.sar_cocpu_saradc1_int_st().bit()),
-            )
-            .field(
-                "sar_cocpu_saradc2_int_st",
-                &format_args!("{}", self.sar_cocpu_saradc2_int_st().bit()),
-            )
-            .field(
-                "sar_cocpu_tsens_int_st",
-                &format_args!("{}", self.sar_cocpu_tsens_int_st().bit()),
-            )
-            .field(
-                "sar_cocpu_start_int_st",
-                &format_args!("{}", self.sar_cocpu_start_int_st().bit()),
-            )
-            .field(
-                "sar_cocpu_sw_int_st",
-                &format_args!("{}", self.sar_cocpu_sw_int_st().bit()),
-            )
-            .field(
-                "sar_cocpu_swd_int_st",
-                &format_args!("{}", self.sar_cocpu_swd_int_st().bit()),
+                &self.sar_cocpu_touch_active_int_st(),
             )
+            .field("sar_cocpu_saradc1_int_st", &self.sar_cocpu_saradc1_int_st())
+            .field("sar_cocpu_saradc2_int_st", &self.sar_cocpu_saradc2_int_st())
+            .field("sar_cocpu_tsens_int_st", &self.sar_cocpu_tsens_int_st())
+            .field("sar_cocpu_start_int_st", &self.sar_cocpu_start_int_st())
+            .field("sar_cocpu_sw_int_st", &self.sar_cocpu_sw_int_st())
+            .field("sar_cocpu_swd_int_st", &self.sar_cocpu_swd_int_st())
             .field(
                 "sar_cocpu_touch_timeout_int_st",
-                &format_args!("{}", self.sar_cocpu_touch_timeout_int_st().bit()),
+                &self.sar_cocpu_touch_timeout_int_st(),
             )
             .field(
                 "sar_cocpu_touch_approach_loop_done_int_st",
-                &format_args!("{}", self.sar_cocpu_touch_approach_loop_done_int_st().bit()),
+                &self.sar_cocpu_touch_approach_loop_done_int_st(),
             )
             .field(
                 "sar_cocpu_touch_scan_done_int_st",
-                &format_args!("{}", self.sar_cocpu_touch_scan_done_int_st().bit()),
+                &self.sar_cocpu_touch_scan_done_int_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "the interrupt state of ulp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_cocpu_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_COCPU_INT_ST_SPEC;
 impl crate::RegisterSpec for SAR_COCPU_INT_ST_SPEC {
diff --git a/esp32s3-ulp/src/sens/sar_i2c_ctrl.rs b/esp32s3-ulp/src/sens/sar_i2c_ctrl.rs
index 47848dd2f7..ac538b3da3 100644
--- a/esp32s3-ulp/src/sens/sar_i2c_ctrl.rs
+++ b/esp32s3-ulp/src/sens/sar_i2c_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_I2C_CTRL")
-            .field(
-                "sar_i2c_ctrl",
-                &format_args!("{}", self.sar_i2c_ctrl().bits()),
-            )
-            .field(
-                "sar_i2c_start",
-                &format_args!("{}", self.sar_i2c_start().bit()),
-            )
-            .field(
-                "sar_i2c_start_force",
-                &format_args!("{}", self.sar_i2c_start_force().bit()),
-            )
+            .field("sar_i2c_ctrl", &self.sar_i2c_ctrl())
+            .field("sar_i2c_start", &self.sar_i2c_start())
+            .field("sar_i2c_start_force", &self.sar_i2c_start_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_I2C_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - I2C control data only active when reg_sar_i2c_start_force = 1"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/sens/sar_slave_addr1.rs b/esp32s3-ulp/src/sens/sar_slave_addr1.rs
index d94a80772a..b5e3efb81f 100644
--- a/esp32s3-ulp/src/sens/sar_slave_addr1.rs
+++ b/esp32s3-ulp/src/sens/sar_slave_addr1.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR1")
-            .field(
-                "sar_i2c_slave_addr1",
-                &format_args!("{}", self.sar_i2c_slave_addr1().bits()),
-            )
-            .field(
-                "sar_i2c_slave_addr0",
-                &format_args!("{}", self.sar_i2c_slave_addr0().bits()),
-            )
-            .field(
-                "sar_saradc_meas_status",
-                &format_args!("{}", self.sar_saradc_meas_status().bits()),
-            )
+            .field("sar_i2c_slave_addr1", &self.sar_i2c_slave_addr1())
+            .field("sar_i2c_slave_addr0", &self.sar_i2c_slave_addr0())
+            .field("sar_saradc_meas_status", &self.sar_saradc_meas_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - configure i2c slave address1"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/sens/sar_slave_addr2.rs b/esp32s3-ulp/src/sens/sar_slave_addr2.rs
index 3fb7205d6e..987d0bf655 100644
--- a/esp32s3-ulp/src/sens/sar_slave_addr2.rs
+++ b/esp32s3-ulp/src/sens/sar_slave_addr2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR2")
-            .field(
-                "sar_i2c_slave_addr3",
-                &format_args!("{}", self.sar_i2c_slave_addr3().bits()),
-            )
-            .field(
-                "sar_i2c_slave_addr2",
-                &format_args!("{}", self.sar_i2c_slave_addr2().bits()),
-            )
+            .field("sar_i2c_slave_addr3", &self.sar_i2c_slave_addr3())
+            .field("sar_i2c_slave_addr2", &self.sar_i2c_slave_addr2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - configure i2c slave address3"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/sens/sar_slave_addr3.rs b/esp32s3-ulp/src/sens/sar_slave_addr3.rs
index 005fbdc778..a5fbc48498 100644
--- a/esp32s3-ulp/src/sens/sar_slave_addr3.rs
+++ b/esp32s3-ulp/src/sens/sar_slave_addr3.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR3")
-            .field(
-                "sar_i2c_slave_addr5",
-                &format_args!("{}", self.sar_i2c_slave_addr5().bits()),
-            )
-            .field(
-                "sar_i2c_slave_addr4",
-                &format_args!("{}", self.sar_i2c_slave_addr4().bits()),
-            )
+            .field("sar_i2c_slave_addr5", &self.sar_i2c_slave_addr5())
+            .field("sar_i2c_slave_addr4", &self.sar_i2c_slave_addr4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - configure i2c slave address5"]
     #[inline(always)]
diff --git a/esp32s3-ulp/src/sens/sar_slave_addr4.rs b/esp32s3-ulp/src/sens/sar_slave_addr4.rs
index 24937373ad..23a8f8a11b 100644
--- a/esp32s3-ulp/src/sens/sar_slave_addr4.rs
+++ b/esp32s3-ulp/src/sens/sar_slave_addr4.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR4")
-            .field(
-                "sar_i2c_slave_addr7",
-                &format_args!("{}", self.sar_i2c_slave_addr7().bits()),
-            )
-            .field(
-                "sar_i2c_slave_addr6",
-                &format_args!("{}", self.sar_i2c_slave_addr6().bits()),
-            )
+            .field("sar_i2c_slave_addr7", &self.sar_i2c_slave_addr7())
+            .field("sar_i2c_slave_addr6", &self.sar_i2c_slave_addr6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - configure i2c slave address7"]
     #[inline(always)]
diff --git a/esp32s3/src/aes/aad_block_num.rs b/esp32s3/src/aes/aad_block_num.rs
index 75e37b35ae..34160ca226 100644
--- a/esp32s3/src/aes/aad_block_num.rs
+++ b/esp32s3/src/aes/aad_block_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AAD_BLOCK_NUM")
-            .field(
-                "aad_block_num",
-                &format_args!("{}", self.aad_block_num().bits()),
-            )
+            .field("aad_block_num", &self.aad_block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AAD_BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits stores the number of AAD block."]
     #[inline(always)]
diff --git a/esp32s3/src/aes/block_mode.rs b/esp32s3/src/aes/block_mode.rs
index a3f51f261f..e60151eabf 100644
--- a/esp32s3/src/aes/block_mode.rs
+++ b/esp32s3/src/aes/block_mode.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLOCK_MODE")
-            .field("block_mode", &format_args!("{}", self.block_mode().bits()))
+            .field("block_mode", &self.block_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLOCK_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Defines the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: reserved, 0x7: reserved."]
     #[inline(always)]
diff --git a/esp32s3/src/aes/block_num.rs b/esp32s3/src/aes/block_num.rs
index 48abd3fa95..910a30d43b 100644
--- a/esp32s3/src/aes/block_num.rs
+++ b/esp32s3/src/aes/block_num.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLOCK_NUM")
-            .field("block_num", &format_args!("{}", self.block_num().bits()))
+            .field("block_num", &self.block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stores the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode."]
     #[inline(always)]
diff --git a/esp32s3/src/aes/date.rs b/esp32s3/src/aes/date.rs
index a22c32c101..5e7e48df64 100644
--- a/esp32s3/src/aes/date.rs
+++ b/esp32s3/src/aes/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/aes/dma_enable.rs b/esp32s3/src/aes/dma_enable.rs
index b346d1a471..229761b079 100644
--- a/esp32s3/src/aes/dma_enable.rs
+++ b/esp32s3/src/aes/dma_enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_ENABLE")
-            .field("dma_enable", &format_args!("{}", self.dma_enable().bit()))
+            .field("dma_enable", &self.dma_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Defines the working mode of the AES accelerator. 1'b0: typical AES working mode, 1'b1: DMA-AES working mode."]
     #[inline(always)]
diff --git a/esp32s3/src/aes/h_mem.rs b/esp32s3/src/aes/h_mem.rs
index fcd1d250f9..2e4334ff37 100644
--- a/esp32s3/src/aes/h_mem.rs
+++ b/esp32s3/src/aes/h_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores GCM hash subkey\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct H_MEM_SPEC;
diff --git a/esp32s3/src/aes/inc_sel.rs b/esp32s3/src/aes/inc_sel.rs
index e172cb64b0..588360a2bb 100644
--- a/esp32s3/src/aes/inc_sel.rs
+++ b/esp32s3/src/aes/inc_sel.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INC_SEL")
-            .field("inc_sel", &format_args!("{}", self.inc_sel().bit()))
+            .field("inc_sel", &self.inc_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INC_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC32 or INC128."]
     #[inline(always)]
diff --git a/esp32s3/src/aes/int_ena.rs b/esp32s3/src/aes/int_ena.rs
index f93912cc71..8bd2f012b2 100644
--- a/esp32s3/src/aes/int_ena.rs
+++ b/esp32s3/src/aes/int_ena.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("int_ena", &format_args!("{}", self.int_ena().bit()))
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. This field is only effective for DMA-AES operation."]
     #[inline(always)]
diff --git a/esp32s3/src/aes/iv_mem.rs b/esp32s3/src/aes/iv_mem.rs
index e8b4d332de..20bdbb631b 100644
--- a/esp32s3/src/aes/iv_mem.rs
+++ b/esp32s3/src/aes/iv_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IV_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores initialization vector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iv_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iv_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IV_MEM_SPEC;
diff --git a/esp32s3/src/aes/j0_mem.rs b/esp32s3/src/aes/j0_mem.rs
index a78fdd3452..002c675bfe 100644
--- a/esp32s3/src/aes/j0_mem.rs
+++ b/esp32s3/src/aes/j0_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<J0_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores J0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`j0_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`j0_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct J0_MEM_SPEC;
diff --git a/esp32s3/src/aes/key.rs b/esp32s3/src/aes/key.rs
index 799ad14ec5..1ff250cbe3 100644
--- a/esp32s3/src/aes/key.rs
+++ b/esp32s3/src/aes/key.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("KEY")
-            .field("key", &format_args!("{}", self.key().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<KEY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("KEY").field("key", &self.key()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/aes/mode.rs b/esp32s3/src/aes/mode.rs
index 22bfdb2173..568d5f10d5 100644
--- a/esp32s3/src/aes/mode.rs
+++ b/esp32s3/src/aes/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/aes/remainder_bit_num.rs b/esp32s3/src/aes/remainder_bit_num.rs
index 330809cbc6..73a3610f09 100644
--- a/esp32s3/src/aes/remainder_bit_num.rs
+++ b/esp32s3/src/aes/remainder_bit_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REMAINDER_BIT_NUM")
-            .field(
-                "remainder_bit_num",
-                &format_args!("{}", self.remainder_bit_num().bits()),
-            )
+            .field("remainder_bit_num", &self.remainder_bit_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REMAINDER_BIT_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Those bits stores the number of remainder bit."]
     #[inline(always)]
diff --git a/esp32s3/src/aes/state.rs b/esp32s3/src/aes/state.rs
index ef077b3c4d..60807a2dd6 100644
--- a/esp32s3/src/aes/state.rs
+++ b/esp32s3/src/aes/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("state", &format_args!("{}", self.state().bits()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "AES state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32s3/src/aes/t0_mem.rs b/esp32s3/src/aes/t0_mem.rs
index 1b3fcafdb6..e2445d62f8 100644
--- a/esp32s3/src/aes/t0_mem.rs
+++ b/esp32s3/src/aes/t0_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T0_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "The memory that stores T0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t0_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t0_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct T0_MEM_SPEC;
diff --git a/esp32s3/src/aes/text_in.rs b/esp32s3/src/aes/text_in.rs
index 87496aa9b0..1f3dd35f59 100644
--- a/esp32s3/src/aes/text_in.rs
+++ b/esp32s3/src/aes/text_in.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEXT_IN")
-            .field("text_in", &format_args!("{}", self.text_in().bits()))
+            .field("text_in", &self.text_in())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEXT_IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stores the source data when the AES accelerator operates in the Typical AES working mode."]
     #[inline(always)]
diff --git a/esp32s3/src/aes/text_out.rs b/esp32s3/src/aes/text_out.rs
index 2264b85748..f1e1d1b5b7 100644
--- a/esp32s3/src/aes/text_out.rs
+++ b/esp32s3/src/aes/text_out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEXT_OUT")
-            .field("text_out", &format_args!("{}", self.text_out().bits()))
+            .field("text_out", &self.text_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEXT_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stores the result data when the AES accelerator operates in the Typical AES working mode."]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/clk_out_en.rs b/esp32s3/src/apb_ctrl/clk_out_en.rs
index a120caeef1..9ffe9f3785 100644
--- a/esp32s3/src/apb_ctrl/clk_out_en.rs
+++ b/esp32s3/src/apb_ctrl/clk_out_en.rs
@@ -107,41 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_OUT_EN")
-            .field("clk20_oen", &format_args!("{}", self.clk20_oen().bit()))
-            .field("clk22_oen", &format_args!("{}", self.clk22_oen().bit()))
-            .field("clk44_oen", &format_args!("{}", self.clk44_oen().bit()))
-            .field("clk_bb_oen", &format_args!("{}", self.clk_bb_oen().bit()))
-            .field("clk80_oen", &format_args!("{}", self.clk80_oen().bit()))
-            .field("clk160_oen", &format_args!("{}", self.clk160_oen().bit()))
-            .field(
-                "clk_320m_oen",
-                &format_args!("{}", self.clk_320m_oen().bit()),
-            )
-            .field(
-                "clk_adc_inf_oen",
-                &format_args!("{}", self.clk_adc_inf_oen().bit()),
-            )
-            .field(
-                "clk_dac_cpu_oen",
-                &format_args!("{}", self.clk_dac_cpu_oen().bit()),
-            )
-            .field(
-                "clk40x_bb_oen",
-                &format_args!("{}", self.clk40x_bb_oen().bit()),
-            )
-            .field(
-                "clk_xtal_oen",
-                &format_args!("{}", self.clk_xtal_oen().bit()),
-            )
+            .field("clk20_oen", &self.clk20_oen())
+            .field("clk22_oen", &self.clk22_oen())
+            .field("clk44_oen", &self.clk44_oen())
+            .field("clk_bb_oen", &self.clk_bb_oen())
+            .field("clk80_oen", &self.clk80_oen())
+            .field("clk160_oen", &self.clk160_oen())
+            .field("clk_320m_oen", &self.clk_320m_oen())
+            .field("clk_adc_inf_oen", &self.clk_adc_inf_oen())
+            .field("clk_dac_cpu_oen", &self.clk_dac_cpu_oen())
+            .field("clk40x_bb_oen", &self.clk40x_bb_oen())
+            .field("clk_xtal_oen", &self.clk_xtal_oen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_OUT_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/clkgate_force_on.rs b/esp32s3/src/apb_ctrl/clkgate_force_on.rs
index 328b440dcd..de9016a273 100644
--- a/esp32s3/src/apb_ctrl/clkgate_force_on.rs
+++ b/esp32s3/src/apb_ctrl/clkgate_force_on.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKGATE_FORCE_ON")
-            .field(
-                "rom_clkgate_force_on",
-                &format_args!("{}", self.rom_clkgate_force_on().bits()),
-            )
-            .field(
-                "sram_clkgate_force_on",
-                &format_args!("{}", self.sram_clkgate_force_on().bits()),
-            )
+            .field("rom_clkgate_force_on", &self.rom_clkgate_force_on())
+            .field("sram_clkgate_force_on", &self.sram_clkgate_force_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKGATE_FORCE_ON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/date.rs b/esp32s3/src/apb_ctrl/date.rs
index 967fa78b40..196ec99143 100644
--- a/esp32s3/src/apb_ctrl/date.rs
+++ b/esp32s3/src/apb_ctrl/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/apb_ctrl/ext_mem_pms_lock.rs b/esp32s3/src/apb_ctrl/ext_mem_pms_lock.rs
index 1a0890d216..916c7ecdbe 100644
--- a/esp32s3/src/apb_ctrl/ext_mem_pms_lock.rs
+++ b/esp32s3/src/apb_ctrl/ext_mem_pms_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_MEM_PMS_LOCK")
-            .field(
-                "ext_mem_pms_lock",
-                &format_args!("{}", self.ext_mem_pms_lock().bit()),
-            )
+            .field("ext_mem_pms_lock", &self.ext_mem_pms_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_MEM_PMS_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/ext_mem_writeback_bypass.rs b/esp32s3/src/apb_ctrl/ext_mem_writeback_bypass.rs
index 94c436acff..7c6da00ee2 100644
--- a/esp32s3/src/apb_ctrl/ext_mem_writeback_bypass.rs
+++ b/esp32s3/src/apb_ctrl/ext_mem_writeback_bypass.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_MEM_WRITEBACK_BYPASS")
-            .field(
-                "writeback_bypass",
-                &format_args!("{}", self.writeback_bypass().bit()),
-            )
+            .field("writeback_bypass", &self.writeback_bypass())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_MEM_WRITEBACK_BYPASS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute."]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/flash_ace0_addr.rs b/esp32s3/src/apb_ctrl/flash_ace0_addr.rs
index 6e41b1ba83..a9b1a1746a 100644
--- a/esp32s3/src/apb_ctrl/flash_ace0_addr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace0_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE0_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/flash_ace0_attr.rs b/esp32s3/src/apb_ctrl/flash_ace0_attr.rs
index 585c08f06c..b46c542a1d 100644
--- a/esp32s3/src/apb_ctrl/flash_ace0_attr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace0_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE0_ATTR")
-            .field(
-                "flash_ace0_attr",
-                &format_args!("{}", self.flash_ace0_attr().bits()),
-            )
+            .field("flash_ace0_attr", &self.flash_ace0_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE0_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/flash_ace0_size.rs b/esp32s3/src/apb_ctrl/flash_ace0_size.rs
index b784961db9..2157a0fc20 100644
--- a/esp32s3/src/apb_ctrl/flash_ace0_size.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace0_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE0_SIZE")
-            .field(
-                "flash_ace0_size",
-                &format_args!("{}", self.flash_ace0_size().bits()),
-            )
+            .field("flash_ace0_size", &self.flash_ace0_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/flash_ace1_addr.rs b/esp32s3/src/apb_ctrl/flash_ace1_addr.rs
index 707ea69b9e..c4357bee02 100644
--- a/esp32s3/src/apb_ctrl/flash_ace1_addr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace1_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE1_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/flash_ace1_attr.rs b/esp32s3/src/apb_ctrl/flash_ace1_attr.rs
index a3c930bed8..51ff55ff28 100644
--- a/esp32s3/src/apb_ctrl/flash_ace1_attr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace1_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE1_ATTR")
-            .field(
-                "flash_ace1_attr",
-                &format_args!("{}", self.flash_ace1_attr().bits()),
-            )
+            .field("flash_ace1_attr", &self.flash_ace1_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE1_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/flash_ace1_size.rs b/esp32s3/src/apb_ctrl/flash_ace1_size.rs
index 86897480f8..330e73a0c8 100644
--- a/esp32s3/src/apb_ctrl/flash_ace1_size.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace1_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE1_SIZE")
-            .field(
-                "flash_ace1_size",
-                &format_args!("{}", self.flash_ace1_size().bits()),
-            )
+            .field("flash_ace1_size", &self.flash_ace1_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/flash_ace2_addr.rs b/esp32s3/src/apb_ctrl/flash_ace2_addr.rs
index 99b421bd18..479eabdbe2 100644
--- a/esp32s3/src/apb_ctrl/flash_ace2_addr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace2_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE2_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/flash_ace2_attr.rs b/esp32s3/src/apb_ctrl/flash_ace2_attr.rs
index a13c9fec96..603f890f64 100644
--- a/esp32s3/src/apb_ctrl/flash_ace2_attr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace2_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE2_ATTR")
-            .field(
-                "flash_ace2_attr",
-                &format_args!("{}", self.flash_ace2_attr().bits()),
-            )
+            .field("flash_ace2_attr", &self.flash_ace2_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE2_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/flash_ace2_size.rs b/esp32s3/src/apb_ctrl/flash_ace2_size.rs
index f359e724d8..7669be7761 100644
--- a/esp32s3/src/apb_ctrl/flash_ace2_size.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace2_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE2_SIZE")
-            .field(
-                "flash_ace2_size",
-                &format_args!("{}", self.flash_ace2_size().bits()),
-            )
+            .field("flash_ace2_size", &self.flash_ace2_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE2_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/flash_ace3_addr.rs b/esp32s3/src/apb_ctrl/flash_ace3_addr.rs
index 4a58d6e82c..38d3e858e4 100644
--- a/esp32s3/src/apb_ctrl/flash_ace3_addr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace3_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE3_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/flash_ace3_attr.rs b/esp32s3/src/apb_ctrl/flash_ace3_attr.rs
index 72dad64984..1646c3fedf 100644
--- a/esp32s3/src/apb_ctrl/flash_ace3_attr.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace3_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE3_ATTR")
-            .field(
-                "flash_ace3_attr",
-                &format_args!("{}", self.flash_ace3_attr().bits()),
-            )
+            .field("flash_ace3_attr", &self.flash_ace3_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE3_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/flash_ace3_size.rs b/esp32s3/src/apb_ctrl/flash_ace3_size.rs
index 682070fd8f..93c73266d8 100644
--- a/esp32s3/src/apb_ctrl/flash_ace3_size.rs
+++ b/esp32s3/src/apb_ctrl/flash_ace3_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_ACE3_SIZE")
-            .field(
-                "flash_ace3_size",
-                &format_args!("{}", self.flash_ace3_size().bits()),
-            )
+            .field("flash_ace3_size", &self.flash_ace3_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_ACE3_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/front_end_mem_pd.rs b/esp32s3/src/apb_ctrl/front_end_mem_pd.rs
index d9032aa992..579173c439 100644
--- a/esp32s3/src/apb_ctrl/front_end_mem_pd.rs
+++ b/esp32s3/src/apb_ctrl/front_end_mem_pd.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FRONT_END_MEM_PD")
-            .field(
-                "agc_mem_force_pu",
-                &format_args!("{}", self.agc_mem_force_pu().bit()),
-            )
-            .field(
-                "agc_mem_force_pd",
-                &format_args!("{}", self.agc_mem_force_pd().bit()),
-            )
-            .field(
-                "pbus_mem_force_pu",
-                &format_args!("{}", self.pbus_mem_force_pu().bit()),
-            )
-            .field(
-                "pbus_mem_force_pd",
-                &format_args!("{}", self.pbus_mem_force_pd().bit()),
-            )
-            .field(
-                "dc_mem_force_pu",
-                &format_args!("{}", self.dc_mem_force_pu().bit()),
-            )
-            .field(
-                "dc_mem_force_pd",
-                &format_args!("{}", self.dc_mem_force_pd().bit()),
-            )
-            .field(
-                "freq_mem_force_pu",
-                &format_args!("{}", self.freq_mem_force_pu().bit()),
-            )
-            .field(
-                "freq_mem_force_pd",
-                &format_args!("{}", self.freq_mem_force_pd().bit()),
-            )
+            .field("agc_mem_force_pu", &self.agc_mem_force_pu())
+            .field("agc_mem_force_pd", &self.agc_mem_force_pd())
+            .field("pbus_mem_force_pu", &self.pbus_mem_force_pu())
+            .field("pbus_mem_force_pd", &self.pbus_mem_force_pd())
+            .field("dc_mem_force_pu", &self.dc_mem_force_pu())
+            .field("dc_mem_force_pd", &self.dc_mem_force_pd())
+            .field("freq_mem_force_pu", &self.freq_mem_force_pu())
+            .field("freq_mem_force_pd", &self.freq_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FRONT_END_MEM_PD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/host_inf_sel.rs b/esp32s3/src/apb_ctrl/host_inf_sel.rs
index 8aabe8ad12..ba2cc0075d 100644
--- a/esp32s3/src/apb_ctrl/host_inf_sel.rs
+++ b/esp32s3/src/apb_ctrl/host_inf_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HOST_INF_SEL")
-            .field(
-                "peri_io_swap",
-                &format_args!("{}", self.peri_io_swap().bits()),
-            )
+            .field("peri_io_swap", &self.peri_io_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HOST_INF_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/mem_power_down.rs b/esp32s3/src/apb_ctrl/mem_power_down.rs
index 6a25aa688e..25d0917807 100644
--- a/esp32s3/src/apb_ctrl/mem_power_down.rs
+++ b/esp32s3/src/apb_ctrl/mem_power_down.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_POWER_DOWN")
-            .field(
-                "rom_power_down",
-                &format_args!("{}", self.rom_power_down().bits()),
-            )
-            .field(
-                "sram_power_down",
-                &format_args!("{}", self.sram_power_down().bits()),
-            )
+            .field("rom_power_down", &self.rom_power_down())
+            .field("sram_power_down", &self.sram_power_down())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_POWER_DOWN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/mem_power_up.rs b/esp32s3/src/apb_ctrl/mem_power_up.rs
index f191081274..ee74da41d5 100644
--- a/esp32s3/src/apb_ctrl/mem_power_up.rs
+++ b/esp32s3/src/apb_ctrl/mem_power_up.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_POWER_UP")
-            .field(
-                "rom_power_up",
-                &format_args!("{}", self.rom_power_up().bits()),
-            )
-            .field(
-                "sram_power_up",
-                &format_args!("{}", self.sram_power_up().bits()),
-            )
+            .field("rom_power_up", &self.rom_power_up())
+            .field("sram_power_up", &self.sram_power_up())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_POWER_UP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/redcy_sig0.rs b/esp32s3/src/apb_ctrl/redcy_sig0.rs
index 472a7459fb..3c645c8772 100644
--- a/esp32s3/src/apb_ctrl/redcy_sig0.rs
+++ b/esp32s3/src/apb_ctrl/redcy_sig0.rs
@@ -24,17 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDCY_SIG0")
-            .field("redcy_sig0", &format_args!("{}", self.redcy_sig0().bits()))
-            .field("redcy_andor", &format_args!("{}", self.redcy_andor().bit()))
+            .field("redcy_sig0", &self.redcy_sig0())
+            .field("redcy_andor", &self.redcy_andor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDCY_SIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/redcy_sig1.rs b/esp32s3/src/apb_ctrl/redcy_sig1.rs
index 7495db33c4..453f9d89f2 100644
--- a/esp32s3/src/apb_ctrl/redcy_sig1.rs
+++ b/esp32s3/src/apb_ctrl/redcy_sig1.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDCY_SIG1")
-            .field("redcy_sig1", &format_args!("{}", self.redcy_sig1().bits()))
-            .field(
-                "redcy_nandor",
-                &format_args!("{}", self.redcy_nandor().bit()),
-            )
+            .field("redcy_sig1", &self.redcy_sig1())
+            .field("redcy_nandor", &self.redcy_nandor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDCY_SIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:30 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/retention_ctrl.rs b/esp32s3/src/apb_ctrl/retention_ctrl.rs
index 29bf4ef0e8..2f69ae7079 100644
--- a/esp32s3/src/apb_ctrl/retention_ctrl.rs
+++ b/esp32s3/src/apb_ctrl/retention_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_CTRL")
-            .field(
-                "retention_cpu_link_addr",
-                &format_args!("{}", self.retention_cpu_link_addr().bits()),
-            )
-            .field(
-                "nobypass_cpu_iso_rst",
-                &format_args!("{}", self.nobypass_cpu_iso_rst().bit()),
-            )
+            .field("retention_cpu_link_addr", &self.retention_cpu_link_addr())
+            .field("nobypass_cpu_iso_rst", &self.nobypass_cpu_iso_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:26 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/retention_ctrl1.rs b/esp32s3/src/apb_ctrl/retention_ctrl1.rs
index c39953ee6e..f2fb281a44 100644
--- a/esp32s3/src/apb_ctrl/retention_ctrl1.rs
+++ b/esp32s3/src/apb_ctrl/retention_ctrl1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_CTRL1")
-            .field(
-                "retention_tag_link_addr",
-                &format_args!("{}", self.retention_tag_link_addr().bits()),
-            )
+            .field("retention_tag_link_addr", &self.retention_tag_link_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:26 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/retention_ctrl2.rs b/esp32s3/src/apb_ctrl/retention_ctrl2.rs
index f9c710bcc9..26895efa60 100644
--- a/esp32s3/src/apb_ctrl/retention_ctrl2.rs
+++ b/esp32s3/src/apb_ctrl/retention_ctrl2.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_CTRL2")
-            .field(
-                "ret_icache_size",
-                &format_args!("{}", self.ret_icache_size().bits()),
-            )
-            .field(
-                "ret_icache_vld_size",
-                &format_args!("{}", self.ret_icache_vld_size().bits()),
-            )
-            .field(
-                "ret_icache_start_point",
-                &format_args!("{}", self.ret_icache_start_point().bits()),
-            )
-            .field(
-                "ret_icache_enable",
-                &format_args!("{}", self.ret_icache_enable().bit()),
-            )
+            .field("ret_icache_size", &self.ret_icache_size())
+            .field("ret_icache_vld_size", &self.ret_icache_vld_size())
+            .field("ret_icache_start_point", &self.ret_icache_start_point())
+            .field("ret_icache_enable", &self.ret_icache_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 4:11 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/retention_ctrl3.rs b/esp32s3/src/apb_ctrl/retention_ctrl3.rs
index 6d3ee0f4e0..844b9125ff 100644
--- a/esp32s3/src/apb_ctrl/retention_ctrl3.rs
+++ b/esp32s3/src/apb_ctrl/retention_ctrl3.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_CTRL3")
-            .field(
-                "ret_dcache_size",
-                &format_args!("{}", self.ret_dcache_size().bits()),
-            )
-            .field(
-                "ret_dcache_vld_size",
-                &format_args!("{}", self.ret_dcache_vld_size().bits()),
-            )
-            .field(
-                "ret_dcache_start_point",
-                &format_args!("{}", self.ret_dcache_start_point().bits()),
-            )
-            .field(
-                "ret_dcache_enable",
-                &format_args!("{}", self.ret_dcache_enable().bit()),
-            )
+            .field("ret_dcache_size", &self.ret_dcache_size())
+            .field("ret_dcache_vld_size", &self.ret_dcache_vld_size())
+            .field("ret_dcache_start_point", &self.ret_dcache_start_point())
+            .field("ret_dcache_enable", &self.ret_dcache_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_CTRL3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 4:12 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/retention_ctrl4.rs b/esp32s3/src/apb_ctrl/retention_ctrl4.rs
index 9d813df0f7..6f186029e6 100644
--- a/esp32s3/src/apb_ctrl/retention_ctrl4.rs
+++ b/esp32s3/src/apb_ctrl/retention_ctrl4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_CTRL4")
-            .field(
-                "retention_inv_cfg",
-                &format_args!("{}", self.retention_inv_cfg().bits()),
-            )
+            .field("retention_inv_cfg", &self.retention_inv_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_CTRL4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/retention_ctrl5.rs b/esp32s3/src/apb_ctrl/retention_ctrl5.rs
index 466e542451..829ef416db 100644
--- a/esp32s3/src/apb_ctrl/retention_ctrl5.rs
+++ b/esp32s3/src/apb_ctrl/retention_ctrl5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_CTRL5")
-            .field(
-                "retention_disable",
-                &format_args!("{}", self.retention_disable().bit()),
-            )
+            .field("retention_disable", &self.retention_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_CTRL5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/sdio_ctrl.rs b/esp32s3/src/apb_ctrl/sdio_ctrl.rs
index 6c3f05f4dd..5da5e4803d 100644
--- a/esp32s3/src/apb_ctrl/sdio_ctrl.rs
+++ b/esp32s3/src/apb_ctrl/sdio_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_CTRL")
-            .field(
-                "sdio_win_access_en",
-                &format_args!("{}", self.sdio_win_access_en().bit()),
-            )
+            .field("sdio_win_access_en", &self.sdio_win_access_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/spi_mem_ecc_ctrl.rs b/esp32s3/src/apb_ctrl/spi_mem_ecc_ctrl.rs
index e3336d5ba0..a6845a0177 100644
--- a/esp32s3/src/apb_ctrl/spi_mem_ecc_ctrl.rs
+++ b/esp32s3/src/apb_ctrl/spi_mem_ecc_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_MEM_ECC_CTRL")
-            .field(
-                "flash_page_size",
-                &format_args!("{}", self.flash_page_size().bits()),
-            )
-            .field(
-                "sram_page_size",
-                &format_args!("{}", self.sram_page_size().bits()),
-            )
+            .field("flash_page_size", &self.flash_page_size())
+            .field("sram_page_size", &self.sram_page_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_MEM_ECC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 18:19 - Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes."]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/spi_mem_pms_ctrl.rs b/esp32s3/src/apb_ctrl/spi_mem_pms_ctrl.rs
index ea3e2eb8e1..1da30c9233 100644
--- a/esp32s3/src/apb_ctrl/spi_mem_pms_ctrl.rs
+++ b/esp32s3/src/apb_ctrl/spi_mem_pms_ctrl.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_MEM_PMS_CTRL")
-            .field(
-                "spi_mem_reject_int",
-                &format_args!("{}", self.spi_mem_reject_int().bit()),
-            )
-            .field(
-                "spi_mem_reject_cde",
-                &format_args!("{}", self.spi_mem_reject_cde().bits()),
-            )
+            .field("spi_mem_reject_int", &self.spi_mem_reject_int())
+            .field("spi_mem_reject_cde", &self.spi_mem_reject_cde())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_MEM_PMS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/spi_mem_reject_addr.rs b/esp32s3/src/apb_ctrl/spi_mem_reject_addr.rs
index db99529e9d..c4ee3e24eb 100644
--- a/esp32s3/src/apb_ctrl/spi_mem_reject_addr.rs
+++ b/esp32s3/src/apb_ctrl/spi_mem_reject_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_MEM_REJECT_ADDR")
-            .field(
-                "spi_mem_reject_addr",
-                &format_args!("{}", self.spi_mem_reject_addr().bits()),
-            )
+            .field("spi_mem_reject_addr", &self.spi_mem_reject_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_MEM_REJECT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_mem_reject_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPI_MEM_REJECT_ADDR_SPEC;
 impl crate::RegisterSpec for SPI_MEM_REJECT_ADDR_SPEC {
diff --git a/esp32s3/src/apb_ctrl/sram_ace0_addr.rs b/esp32s3/src/apb_ctrl/sram_ace0_addr.rs
index 7cc4e6e4d1..16e6a7fa4e 100644
--- a/esp32s3/src/apb_ctrl/sram_ace0_addr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace0_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE0_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/sram_ace0_attr.rs b/esp32s3/src/apb_ctrl/sram_ace0_attr.rs
index 9bb37b15f6..fceeaacddf 100644
--- a/esp32s3/src/apb_ctrl/sram_ace0_attr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace0_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE0_ATTR")
-            .field(
-                "sram_ace0_attr",
-                &format_args!("{}", self.sram_ace0_attr().bits()),
-            )
+            .field("sram_ace0_attr", &self.sram_ace0_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE0_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/sram_ace0_size.rs b/esp32s3/src/apb_ctrl/sram_ace0_size.rs
index c92ac4f841..0272e6d823 100644
--- a/esp32s3/src/apb_ctrl/sram_ace0_size.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace0_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE0_SIZE")
-            .field(
-                "sram_ace0_size",
-                &format_args!("{}", self.sram_ace0_size().bits()),
-            )
+            .field("sram_ace0_size", &self.sram_ace0_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/sram_ace1_addr.rs b/esp32s3/src/apb_ctrl/sram_ace1_addr.rs
index b73ab98a92..78e35e805a 100644
--- a/esp32s3/src/apb_ctrl/sram_ace1_addr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace1_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE1_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/sram_ace1_attr.rs b/esp32s3/src/apb_ctrl/sram_ace1_attr.rs
index 5afec59f63..472fcc3fcf 100644
--- a/esp32s3/src/apb_ctrl/sram_ace1_attr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace1_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE1_ATTR")
-            .field(
-                "sram_ace1_attr",
-                &format_args!("{}", self.sram_ace1_attr().bits()),
-            )
+            .field("sram_ace1_attr", &self.sram_ace1_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE1_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/sram_ace1_size.rs b/esp32s3/src/apb_ctrl/sram_ace1_size.rs
index bf2452c4f9..f1f732b634 100644
--- a/esp32s3/src/apb_ctrl/sram_ace1_size.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace1_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE1_SIZE")
-            .field(
-                "sram_ace1_size",
-                &format_args!("{}", self.sram_ace1_size().bits()),
-            )
+            .field("sram_ace1_size", &self.sram_ace1_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/sram_ace2_addr.rs b/esp32s3/src/apb_ctrl/sram_ace2_addr.rs
index 4bd22c1880..f806d1034c 100644
--- a/esp32s3/src/apb_ctrl/sram_ace2_addr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace2_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE2_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/sram_ace2_attr.rs b/esp32s3/src/apb_ctrl/sram_ace2_attr.rs
index e9c04af80e..67946e0fba 100644
--- a/esp32s3/src/apb_ctrl/sram_ace2_attr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace2_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE2_ATTR")
-            .field(
-                "sram_ace2_attr",
-                &format_args!("{}", self.sram_ace2_attr().bits()),
-            )
+            .field("sram_ace2_attr", &self.sram_ace2_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE2_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/sram_ace2_size.rs b/esp32s3/src/apb_ctrl/sram_ace2_size.rs
index fbe550572a..68352c163f 100644
--- a/esp32s3/src/apb_ctrl/sram_ace2_size.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace2_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE2_SIZE")
-            .field(
-                "sram_ace2_size",
-                &format_args!("{}", self.sram_ace2_size().bits()),
-            )
+            .field("sram_ace2_size", &self.sram_ace2_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE2_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/sram_ace3_addr.rs b/esp32s3/src/apb_ctrl/sram_ace3_addr.rs
index a658094839..4a5c4d44ec 100644
--- a/esp32s3/src/apb_ctrl/sram_ace3_addr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace3_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE3_ADDR")
-            .field("s", &format_args!("{}", self.s().bits()))
+            .field("s", &self.s())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/sram_ace3_attr.rs b/esp32s3/src/apb_ctrl/sram_ace3_attr.rs
index ce4d9caa85..fdbea92582 100644
--- a/esp32s3/src/apb_ctrl/sram_ace3_attr.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace3_attr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE3_ATTR")
-            .field(
-                "sram_ace3_attr",
-                &format_args!("{}", self.sram_ace3_attr().bits()),
-            )
+            .field("sram_ace3_attr", &self.sram_ace3_attr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE3_ATTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/sram_ace3_size.rs b/esp32s3/src/apb_ctrl/sram_ace3_size.rs
index a0d41e107e..02ea92edfc 100644
--- a/esp32s3/src/apb_ctrl/sram_ace3_size.rs
+++ b/esp32s3/src/apb_ctrl/sram_ace3_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_ACE3_SIZE")
-            .field(
-                "sram_ace3_size",
-                &format_args!("{}", self.sram_ace3_size().bits()),
-            )
+            .field("sram_ace3_size", &self.sram_ace3_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_ACE3_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/sysclk_conf.rs b/esp32s3/src/apb_ctrl/sysclk_conf.rs
index 8801b5857e..b2450d7ad0 100644
--- a/esp32s3/src/apb_ctrl/sysclk_conf.rs
+++ b/esp32s3/src/apb_ctrl/sysclk_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSCLK_CONF")
-            .field(
-                "pre_div_cnt",
-                &format_args!("{}", self.pre_div_cnt().bits()),
-            )
-            .field("clk_320m_en", &format_args!("{}", self.clk_320m_en().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "rst_tick_cnt",
-                &format_args!("{}", self.rst_tick_cnt().bit()),
-            )
+            .field("pre_div_cnt", &self.pre_div_cnt())
+            .field("clk_320m_en", &self.clk_320m_en())
+            .field("clk_en", &self.clk_en())
+            .field("rst_tick_cnt", &self.rst_tick_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/tick_conf.rs b/esp32s3/src/apb_ctrl/tick_conf.rs
index 793c0bf0a4..9cc9b175e8 100644
--- a/esp32s3/src/apb_ctrl/tick_conf.rs
+++ b/esp32s3/src/apb_ctrl/tick_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TICK_CONF")
-            .field(
-                "xtal_tick_num",
-                &format_args!("{}", self.xtal_tick_num().bits()),
-            )
-            .field(
-                "ck8m_tick_num",
-                &format_args!("{}", self.ck8m_tick_num().bits()),
-            )
-            .field("tick_enable", &format_args!("{}", self.tick_enable().bit()))
+            .field("xtal_tick_num", &self.xtal_tick_num())
+            .field("ck8m_tick_num", &self.ck8m_tick_num())
+            .field("tick_enable", &self.tick_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TICK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/wifi_bb_cfg.rs b/esp32s3/src/apb_ctrl/wifi_bb_cfg.rs
index 5e34f39eee..08a6dbe236 100644
--- a/esp32s3/src/apb_ctrl/wifi_bb_cfg.rs
+++ b/esp32s3/src/apb_ctrl/wifi_bb_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_BB_CFG")
-            .field(
-                "wifi_bb_cfg",
-                &format_args!("{}", self.wifi_bb_cfg().bits()),
-            )
+            .field("wifi_bb_cfg", &self.wifi_bb_cfg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_BB_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/wifi_bb_cfg_2.rs b/esp32s3/src/apb_ctrl/wifi_bb_cfg_2.rs
index 82390231a0..3ca63a3eeb 100644
--- a/esp32s3/src/apb_ctrl/wifi_bb_cfg_2.rs
+++ b/esp32s3/src/apb_ctrl/wifi_bb_cfg_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_BB_CFG_2")
-            .field(
-                "wifi_bb_cfg_2",
-                &format_args!("{}", self.wifi_bb_cfg_2().bits()),
-            )
+            .field("wifi_bb_cfg_2", &self.wifi_bb_cfg_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_BB_CFG_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/wifi_clk_en.rs b/esp32s3/src/apb_ctrl/wifi_clk_en.rs
index 8bd17c0f25..ad3eafe93e 100644
--- a/esp32s3/src/apb_ctrl/wifi_clk_en.rs
+++ b/esp32s3/src/apb_ctrl/wifi_clk_en.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_CLK_EN")
-            .field(
-                "wifi_clk_en",
-                &format_args!("{}", self.wifi_clk_en().bits()),
-            )
+            .field("wifi_clk_en", &self.wifi_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_ctrl/wifi_rst_en.rs b/esp32s3/src/apb_ctrl/wifi_rst_en.rs
index 703d5edc06..7cf7639b55 100644
--- a/esp32s3/src/apb_ctrl/wifi_rst_en.rs
+++ b/esp32s3/src/apb_ctrl/wifi_rst_en.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WIFI_RST_EN")
-            .field("wifi_rst", &format_args!("{}", self.wifi_rst().bits()))
+            .field("wifi_rst", &self.wifi_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WIFI_RST_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/apb_saradc1_data_status.rs b/esp32s3/src/apb_saradc/apb_saradc1_data_status.rs
index 8c4d9923d9..7be83aaf31 100644
--- a/esp32s3/src/apb_saradc/apb_saradc1_data_status.rs
+++ b/esp32s3/src/apb_saradc/apb_saradc1_data_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_SARADC1_DATA_STATUS")
-            .field(
-                "saradc1_data",
-                &format_args!("{}", self.saradc1_data().bits()),
-            )
+            .field("saradc1_data", &self.saradc1_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_SARADC1_DATA_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "get apb saradc sample data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb_saradc1_data_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB_SARADC1_DATA_STATUS_SPEC;
 impl crate::RegisterSpec for APB_SARADC1_DATA_STATUS_SPEC {
diff --git a/esp32s3/src/apb_saradc/apb_saradc2_data_status.rs b/esp32s3/src/apb_saradc/apb_saradc2_data_status.rs
index 6bcd502a26..72076436c5 100644
--- a/esp32s3/src/apb_saradc/apb_saradc2_data_status.rs
+++ b/esp32s3/src/apb_saradc/apb_saradc2_data_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_SARADC2_DATA_STATUS")
-            .field(
-                "saradc2_data",
-                &format_args!("{}", self.saradc2_data().bits()),
-            )
+            .field("saradc2_data", &self.saradc2_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_SARADC2_DATA_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "get apb saradc2 sample data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb_saradc2_data_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APB_SARADC2_DATA_STATUS_SPEC;
 impl crate::RegisterSpec for APB_SARADC2_DATA_STATUS_SPEC {
diff --git a/esp32s3/src/apb_saradc/arb_ctrl.rs b/esp32s3/src/apb_saradc/arb_ctrl.rs
index 78eb6a0d97..4bc2d0a8db 100644
--- a/esp32s3/src/apb_saradc/arb_ctrl.rs
+++ b/esp32s3/src/apb_saradc/arb_ctrl.rs
@@ -80,35 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_CTRL")
-            .field("apb_force", &format_args!("{}", self.apb_force().bit()))
-            .field("rtc_force", &format_args!("{}", self.rtc_force().bit()))
-            .field("wifi_force", &format_args!("{}", self.wifi_force().bit()))
-            .field("grant_force", &format_args!("{}", self.grant_force().bit()))
-            .field(
-                "apb_priority",
-                &format_args!("{}", self.apb_priority().bits()),
-            )
-            .field(
-                "rtc_priority",
-                &format_args!("{}", self.rtc_priority().bits()),
-            )
-            .field(
-                "wifi_priority",
-                &format_args!("{}", self.wifi_priority().bits()),
-            )
-            .field(
-                "fix_priority",
-                &format_args!("{}", self.fix_priority().bit()),
-            )
+            .field("apb_force", &self.apb_force())
+            .field("rtc_force", &self.rtc_force())
+            .field("wifi_force", &self.wifi_force())
+            .field("grant_force", &self.grant_force())
+            .field("apb_priority", &self.apb_priority())
+            .field("rtc_priority", &self.rtc_priority())
+            .field("wifi_priority", &self.wifi_priority())
+            .field("fix_priority", &self.fix_priority())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - adc2 arbiter force to enableapb controller"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/clkm_conf.rs b/esp32s3/src/apb_saradc/clkm_conf.rs
index 2e45acf09a..25b7a86fc7 100644
--- a/esp32s3/src/apb_saradc/clkm_conf.rs
+++ b/esp32s3/src/apb_saradc/clkm_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKM_CONF")
-            .field(
-                "clkm_div_num",
-                &format_args!("{}", self.clkm_div_num().bits()),
-            )
-            .field("clkm_div_b", &format_args!("{}", self.clkm_div_b().bits()))
-            .field("clkm_div_a", &format_args!("{}", self.clkm_div_a().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bits()))
+            .field("clkm_div_num", &self.clkm_div_num())
+            .field("clkm_div_b", &self.clkm_div_b())
+            .field("clkm_div_a", &self.clkm_div_a())
+            .field("clk_en", &self.clk_en())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral clock divider value"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/ctrl.rs b/esp32s3/src/apb_saradc/ctrl.rs
index 3dda80e605..ea51a35b88 100644
--- a/esp32s3/src/apb_saradc/ctrl.rs
+++ b/esp32s3/src/apb_saradc/ctrl.rs
@@ -134,56 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("start_force", &format_args!("{}", self.start_force().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("work_mode", &format_args!("{}", self.work_mode().bits()))
-            .field("sar_sel", &format_args!("{}", self.sar_sel().bit()))
-            .field(
-                "sar_clk_gated",
-                &format_args!("{}", self.sar_clk_gated().bit()),
-            )
-            .field(
-                "sar_clk_div",
-                &format_args!("{}", self.sar_clk_div().bits()),
-            )
-            .field(
-                "sar1_patt_len",
-                &format_args!("{}", self.sar1_patt_len().bits()),
-            )
-            .field(
-                "sar2_patt_len",
-                &format_args!("{}", self.sar2_patt_len().bits()),
-            )
-            .field(
-                "sar1_patt_p_clear",
-                &format_args!("{}", self.sar1_patt_p_clear().bit()),
-            )
-            .field(
-                "sar2_patt_p_clear",
-                &format_args!("{}", self.sar2_patt_p_clear().bit()),
-            )
-            .field(
-                "data_sar_sel",
-                &format_args!("{}", self.data_sar_sel().bit()),
-            )
-            .field("data_to_i2s", &format_args!("{}", self.data_to_i2s().bit()))
-            .field(
-                "xpd_sar_force",
-                &format_args!("{}", self.xpd_sar_force().bits()),
-            )
-            .field(
-                "wait_arb_cycle",
-                &format_args!("{}", self.wait_arb_cycle().bits()),
-            )
+            .field("start_force", &self.start_force())
+            .field("start", &self.start())
+            .field("work_mode", &self.work_mode())
+            .field("sar_sel", &self.sar_sel())
+            .field("sar_clk_gated", &self.sar_clk_gated())
+            .field("sar_clk_div", &self.sar_clk_div())
+            .field("sar1_patt_len", &self.sar1_patt_len())
+            .field("sar2_patt_len", &self.sar2_patt_len())
+            .field("sar1_patt_p_clear", &self.sar1_patt_p_clear())
+            .field("sar2_patt_p_clear", &self.sar2_patt_p_clear())
+            .field("data_sar_sel", &self.data_sar_sel())
+            .field("data_to_i2s", &self.data_to_i2s())
+            .field("xpd_sar_force", &self.xpd_sar_force())
+            .field("wait_arb_cycle", &self.wait_arb_cycle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable start saradc by sw"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/ctrl2.rs b/esp32s3/src/apb_saradc/ctrl2.rs
index 93d0e39545..164bc86795 100644
--- a/esp32s3/src/apb_saradc/ctrl2.rs
+++ b/esp32s3/src/apb_saradc/ctrl2.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field(
-                "meas_num_limit",
-                &format_args!("{}", self.meas_num_limit().bit()),
-            )
-            .field(
-                "max_meas_num",
-                &format_args!("{}", self.max_meas_num().bits()),
-            )
-            .field("sar1_inv", &format_args!("{}", self.sar1_inv().bit()))
-            .field("sar2_inv", &format_args!("{}", self.sar2_inv().bit()))
-            .field("timer_sel", &format_args!("{}", self.timer_sel().bit()))
-            .field(
-                "timer_target",
-                &format_args!("{}", self.timer_target().bits()),
-            )
-            .field("timer_en", &format_args!("{}", self.timer_en().bit()))
+            .field("meas_num_limit", &self.meas_num_limit())
+            .field("max_meas_num", &self.max_meas_num())
+            .field("sar1_inv", &self.sar1_inv())
+            .field("sar2_inv", &self.sar2_inv())
+            .field("timer_sel", &self.timer_sel())
+            .field("timer_target", &self.timer_target())
+            .field("timer_en", &self.timer_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable apb saradc limit the sample num"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/ctrl_date.rs b/esp32s3/src/apb_saradc/ctrl_date.rs
index 77aa5d3ed6..a745b94ceb 100644
--- a/esp32s3/src/apb_saradc/ctrl_date.rs
+++ b/esp32s3/src/apb_saradc/ctrl_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL_DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - version"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/dma_conf.rs b/esp32s3/src/apb_saradc/dma_conf.rs
index 6b09f0ad9e..1ef54d4c24 100644
--- a/esp32s3/src/apb_saradc/dma_conf.rs
+++ b/esp32s3/src/apb_saradc/dma_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field(
-                "adc_eof_num",
-                &format_args!("{}", self.adc_eof_num().bits()),
-            )
-            .field(
-                "adc_reset_fsm",
-                &format_args!("{}", self.adc_reset_fsm().bit()),
-            )
-            .field("adc_trans", &format_args!("{}", self.adc_trans().bit()))
+            .field("adc_eof_num", &self.adc_eof_num())
+            .field("adc_reset_fsm", &self.adc_reset_fsm())
+            .field("adc_trans", &self.adc_trans())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - the dma_in_suc_eof gen when sample cnt = spi_eof_num"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/filter_ctrl0.rs b/esp32s3/src/apb_saradc/filter_ctrl0.rs
index 1f6791644f..b2beb9a89e 100644
--- a/esp32s3/src/apb_saradc/filter_ctrl0.rs
+++ b/esp32s3/src/apb_saradc/filter_ctrl0.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CTRL0")
-            .field(
-                "filter_channel1",
-                &format_args!("{}", self.filter_channel1().bits()),
-            )
-            .field(
-                "filter_channel0",
-                &format_args!("{}", self.filter_channel0().bits()),
-            )
-            .field(
-                "filter_reset",
-                &format_args!("{}", self.filter_reset().bit()),
-            )
+            .field("filter_channel1", &self.filter_channel1())
+            .field("filter_channel0", &self.filter_channel0())
+            .field("filter_reset", &self.filter_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CTRL0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 14:18 - configure the filter1 channel"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/filter_ctrl1.rs b/esp32s3/src/apb_saradc/filter_ctrl1.rs
index ad3ce5562f..171fb0636f 100644
--- a/esp32s3/src/apb_saradc/filter_ctrl1.rs
+++ b/esp32s3/src/apb_saradc/filter_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CTRL1")
-            .field(
-                "filter_factor1",
-                &format_args!("{}", self.filter_factor1().bits()),
-            )
-            .field(
-                "filter_factor0",
-                &format_args!("{}", self.filter_factor0().bits()),
-            )
+            .field("filter_factor1", &self.filter_factor1())
+            .field("filter_factor0", &self.filter_factor0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 26:28 - apb saradc factor1"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/fsm_wait.rs b/esp32s3/src/apb_saradc/fsm_wait.rs
index 68770800be..34c3efa58c 100644
--- a/esp32s3/src/apb_saradc/fsm_wait.rs
+++ b/esp32s3/src/apb_saradc/fsm_wait.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_WAIT")
-            .field("xpd_wait", &format_args!("{}", self.xpd_wait().bits()))
-            .field("rstb_wait", &format_args!("{}", self.rstb_wait().bits()))
-            .field(
-                "standby_wait",
-                &format_args!("{}", self.standby_wait().bits()),
-            )
+            .field("xpd_wait", &self.xpd_wait())
+            .field("rstb_wait", &self.rstb_wait())
+            .field("standby_wait", &self.standby_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_WAIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the cycle which saradc controller in xpd state"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/int_ena.rs b/esp32s3/src/apb_saradc/int_ena.rs
index 91dfac82c1..07a5f11340 100644
--- a/esp32s3/src/apb_saradc/int_ena.rs
+++ b/esp32s3/src/apb_saradc/int_ena.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 26 - interrupt of thres1 low"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/int_raw.rs b/esp32s3/src/apb_saradc/int_raw.rs
index 91d4df36f3..28e1b0b2fe 100644
--- a/esp32s3/src/apb_saradc/int_raw.rs
+++ b/esp32s3/src/apb_saradc/int_raw.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "raw of interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s3/src/apb_saradc/int_st.rs b/esp32s3/src/apb_saradc/int_st.rs
index caa4fd0f80..e49050d150 100644
--- a/esp32s3/src/apb_saradc/int_st.rs
+++ b/esp32s3/src/apb_saradc/int_st.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bit()))
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bit()))
-            .field("thres1_high", &format_args!("{}", self.thres1_high().bit()))
-            .field("thres0_high", &format_args!("{}", self.thres0_high().bit()))
-            .field("adc2_done", &format_args!("{}", self.adc2_done().bit()))
-            .field("adc1_done", &format_args!("{}", self.adc1_done().bit()))
+            .field("thres1_low", &self.thres1_low())
+            .field("thres0_low", &self.thres0_low())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres0_high", &self.thres0_high())
+            .field("adc2_done", &self.adc2_done())
+            .field("adc1_done", &self.adc1_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "state of interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/apb_saradc/sar1_patt_tab1.rs b/esp32s3/src/apb_saradc/sar1_patt_tab1.rs
index 9800bc3bf7..a5c025a7eb 100644
--- a/esp32s3/src/apb_saradc/sar1_patt_tab1.rs
+++ b/esp32s3/src/apb_saradc/sar1_patt_tab1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_PATT_TAB1")
-            .field(
-                "sar1_patt_tab1",
-                &format_args!("{}", self.sar1_patt_tab1().bits()),
-            )
+            .field("sar1_patt_tab1", &self.sar1_patt_tab1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_PATT_TAB1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 1 (each item 6bit)"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/sar1_patt_tab2.rs b/esp32s3/src/apb_saradc/sar1_patt_tab2.rs
index d16592271b..3af5b853cd 100644
--- a/esp32s3/src/apb_saradc/sar1_patt_tab2.rs
+++ b/esp32s3/src/apb_saradc/sar1_patt_tab2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_PATT_TAB2")
-            .field(
-                "sar1_patt_tab2",
-                &format_args!("{}", self.sar1_patt_tab2().bits()),
-            )
+            .field("sar1_patt_tab2", &self.sar1_patt_tab2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_PATT_TAB2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 1 (each item 6bit)"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/sar1_patt_tab3.rs b/esp32s3/src/apb_saradc/sar1_patt_tab3.rs
index 168f5c285e..04991ccdcb 100644
--- a/esp32s3/src/apb_saradc/sar1_patt_tab3.rs
+++ b/esp32s3/src/apb_saradc/sar1_patt_tab3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_PATT_TAB3")
-            .field(
-                "sar1_patt_tab3",
-                &format_args!("{}", self.sar1_patt_tab3().bits()),
-            )
+            .field("sar1_patt_tab3", &self.sar1_patt_tab3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_PATT_TAB3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 1 (each item 6bit)"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/sar1_patt_tab4.rs b/esp32s3/src/apb_saradc/sar1_patt_tab4.rs
index 1516db1ecf..637649bbe9 100644
--- a/esp32s3/src/apb_saradc/sar1_patt_tab4.rs
+++ b/esp32s3/src/apb_saradc/sar1_patt_tab4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_PATT_TAB4")
-            .field(
-                "sar1_patt_tab4",
-                &format_args!("{}", self.sar1_patt_tab4().bits()),
-            )
+            .field("sar1_patt_tab4", &self.sar1_patt_tab4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_PATT_TAB4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 1 (each item 6bit)"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/sar1_status.rs b/esp32s3/src/apb_saradc/sar1_status.rs
index 728fc286a7..0a0873bb1c 100644
--- a/esp32s3/src/apb_saradc/sar1_status.rs
+++ b/esp32s3/src/apb_saradc/sar1_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR1_STATUS")
-            .field(
-                "sar1_status",
-                &format_args!("{}", self.sar1_status().bits()),
-            )
+            .field("sar1_status", &self.sar1_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR1_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "saradc1 status for debug\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar1_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR1_STATUS_SPEC;
 impl crate::RegisterSpec for SAR1_STATUS_SPEC {
diff --git a/esp32s3/src/apb_saradc/sar2_patt_tab1.rs b/esp32s3/src/apb_saradc/sar2_patt_tab1.rs
index 9cbe7199f4..772d75cb50 100644
--- a/esp32s3/src/apb_saradc/sar2_patt_tab1.rs
+++ b/esp32s3/src/apb_saradc/sar2_patt_tab1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_PATT_TAB1")
-            .field(
-                "sar2_patt_tab1",
-                &format_args!("{}", self.sar2_patt_tab1().bits()),
-            )
+            .field("sar2_patt_tab1", &self.sar2_patt_tab1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_PATT_TAB1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - item 0 ~ 3 for pattern table 2 (each item 6bit)"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/sar2_patt_tab2.rs b/esp32s3/src/apb_saradc/sar2_patt_tab2.rs
index 1d5741d0c8..88a61ac8f0 100644
--- a/esp32s3/src/apb_saradc/sar2_patt_tab2.rs
+++ b/esp32s3/src/apb_saradc/sar2_patt_tab2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_PATT_TAB2")
-            .field(
-                "sar2_patt_tab2",
-                &format_args!("{}", self.sar2_patt_tab2().bits()),
-            )
+            .field("sar2_patt_tab2", &self.sar2_patt_tab2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_PATT_TAB2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 4 ~ 7 for pattern table 2 (each item 6bit)"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/sar2_patt_tab3.rs b/esp32s3/src/apb_saradc/sar2_patt_tab3.rs
index 6916b3fae9..d8f4e558b5 100644
--- a/esp32s3/src/apb_saradc/sar2_patt_tab3.rs
+++ b/esp32s3/src/apb_saradc/sar2_patt_tab3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_PATT_TAB3")
-            .field(
-                "sar2_patt_tab3",
-                &format_args!("{}", self.sar2_patt_tab3().bits()),
-            )
+            .field("sar2_patt_tab3", &self.sar2_patt_tab3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_PATT_TAB3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 8 ~ 11 for pattern table 2 (each item 6bit)"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/sar2_patt_tab4.rs b/esp32s3/src/apb_saradc/sar2_patt_tab4.rs
index e2efe010c6..5075d7b418 100644
--- a/esp32s3/src/apb_saradc/sar2_patt_tab4.rs
+++ b/esp32s3/src/apb_saradc/sar2_patt_tab4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_PATT_TAB4")
-            .field(
-                "sar2_patt_tab4",
-                &format_args!("{}", self.sar2_patt_tab4().bits()),
-            )
+            .field("sar2_patt_tab4", &self.sar2_patt_tab4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_PATT_TAB4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Item 12 ~ 15 for pattern table 2 (each item 6bit)"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/sar2_status.rs b/esp32s3/src/apb_saradc/sar2_status.rs
index 35534c2bff..0d5d030731 100644
--- a/esp32s3/src/apb_saradc/sar2_status.rs
+++ b/esp32s3/src/apb_saradc/sar2_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR2_STATUS")
-            .field(
-                "sar2_status",
-                &format_args!("{}", self.sar2_status().bits()),
-            )
+            .field("sar2_status", &self.sar2_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR2_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "saradc2 status for debug\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar2_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR2_STATUS_SPEC;
 impl crate::RegisterSpec for SAR2_STATUS_SPEC {
diff --git a/esp32s3/src/apb_saradc/thres0_ctrl.rs b/esp32s3/src/apb_saradc/thres0_ctrl.rs
index 5223f29886..5be5ca6b54 100644
--- a/esp32s3/src/apb_saradc/thres0_ctrl.rs
+++ b/esp32s3/src/apb_saradc/thres0_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES0_CTRL")
-            .field(
-                "thres0_channel",
-                &format_args!("{}", self.thres0_channel().bits()),
-            )
-            .field(
-                "thres0_high",
-                &format_args!("{}", self.thres0_high().bits()),
-            )
-            .field("thres0_low", &format_args!("{}", self.thres0_low().bits()))
+            .field("thres0_channel", &self.thres0_channel())
+            .field("thres0_high", &self.thres0_high())
+            .field("thres0_low", &self.thres0_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES0_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - configure which channel thres0 monitor"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/thres1_ctrl.rs b/esp32s3/src/apb_saradc/thres1_ctrl.rs
index b0cd14ccff..72f805d537 100644
--- a/esp32s3/src/apb_saradc/thres1_ctrl.rs
+++ b/esp32s3/src/apb_saradc/thres1_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES1_CTRL")
-            .field(
-                "thres1_channel",
-                &format_args!("{}", self.thres1_channel().bits()),
-            )
-            .field(
-                "thres1_high",
-                &format_args!("{}", self.thres1_high().bits()),
-            )
-            .field("thres1_low", &format_args!("{}", self.thres1_low().bits()))
+            .field("thres1_channel", &self.thres1_channel())
+            .field("thres1_high", &self.thres1_high())
+            .field("thres1_low", &self.thres1_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES1_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - configure which channel thres0 monitor"]
     #[inline(always)]
diff --git a/esp32s3/src/apb_saradc/thres_ctrl.rs b/esp32s3/src/apb_saradc/thres_ctrl.rs
index 210fbf0539..2b17c1243f 100644
--- a/esp32s3/src/apb_saradc/thres_ctrl.rs
+++ b/esp32s3/src/apb_saradc/thres_ctrl.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("THRES_CTRL")
-            .field(
-                "thres_all_en",
-                &format_args!("{}", self.thres_all_en().bit()),
-            )
-            .field("thres3_en", &format_args!("{}", self.thres3_en().bit()))
-            .field("thres2_en", &format_args!("{}", self.thres2_en().bit()))
-            .field("thres1_en", &format_args!("{}", self.thres1_en().bit()))
-            .field("thres0_en", &format_args!("{}", self.thres0_en().bit()))
+            .field("thres_all_en", &self.thres_all_en())
+            .field("thres3_en", &self.thres3_en())
+            .field("thres2_en", &self.thres2_en())
+            .field("thres1_en", &self.thres1_en())
+            .field("thres0_en", &self.thres0_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<THRES_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - enable thres0 to monitor all channel"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_area_dram0_0_max.rs b/esp32s3/src/assist_debug/core_0_area_dram0_0_max.rs
index 005d6a6db3..9428c7292a 100644
--- a/esp32s3/src/assist_debug/core_0_area_dram0_0_max.rs
+++ b/esp32s3/src/assist_debug/core_0_area_dram0_0_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_0_MAX")
-            .field(
-                "core_0_area_dram0_0_max",
-                &format_args!("{}", self.core_0_area_dram0_0_max().bits()),
-            )
+            .field("core_0_area_dram0_0_max", &self.core_0_area_dram0_0_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_0_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region0 end addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_area_dram0_0_min.rs b/esp32s3/src/assist_debug/core_0_area_dram0_0_min.rs
index 82ad82fe11..7bbd0597a1 100644
--- a/esp32s3/src/assist_debug/core_0_area_dram0_0_min.rs
+++ b/esp32s3/src/assist_debug/core_0_area_dram0_0_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_0_MIN")
-            .field(
-                "core_0_area_dram0_0_min",
-                &format_args!("{}", self.core_0_area_dram0_0_min().bits()),
-            )
+            .field("core_0_area_dram0_0_min", &self.core_0_area_dram0_0_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_0_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region0 start addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_area_dram0_1_max.rs b/esp32s3/src/assist_debug/core_0_area_dram0_1_max.rs
index 5386b16204..e6dcd4c10a 100644
--- a/esp32s3/src/assist_debug/core_0_area_dram0_1_max.rs
+++ b/esp32s3/src/assist_debug/core_0_area_dram0_1_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_1_MAX")
-            .field(
-                "core_0_area_dram0_1_max",
-                &format_args!("{}", self.core_0_area_dram0_1_max().bits()),
-            )
+            .field("core_0_area_dram0_1_max", &self.core_0_area_dram0_1_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_1_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region1 end addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_area_dram0_1_min.rs b/esp32s3/src/assist_debug/core_0_area_dram0_1_min.rs
index a60f37cb77..9a5ba5db20 100644
--- a/esp32s3/src/assist_debug/core_0_area_dram0_1_min.rs
+++ b/esp32s3/src/assist_debug/core_0_area_dram0_1_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_DRAM0_1_MIN")
-            .field(
-                "core_0_area_dram0_1_min",
-                &format_args!("{}", self.core_0_area_dram0_1_min().bits()),
-            )
+            .field("core_0_area_dram0_1_min", &self.core_0_area_dram0_1_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_DRAM0_1_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 dram0 region1 start addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_area_pc.rs b/esp32s3/src/assist_debug/core_0_area_pc.rs
index 29b6351fff..1c43bdaf25 100644
--- a/esp32s3/src/assist_debug/core_0_area_pc.rs
+++ b/esp32s3/src/assist_debug/core_0_area_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PC")
-            .field(
-                "core_0_area_pc",
-                &format_args!("{}", self.core_0_area_pc().bits()),
-            )
+            .field("core_0_area_pc", &self.core_0_area_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 area pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_AREA_PC_SPEC;
 impl crate::RegisterSpec for CORE_0_AREA_PC_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_area_pif_0_max.rs b/esp32s3/src/assist_debug/core_0_area_pif_0_max.rs
index 272d2c2274..2f0e9bd13c 100644
--- a/esp32s3/src/assist_debug/core_0_area_pif_0_max.rs
+++ b/esp32s3/src/assist_debug/core_0_area_pif_0_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_0_MAX")
-            .field(
-                "core_0_area_pif_0_max",
-                &format_args!("{}", self.core_0_area_pif_0_max().bits()),
-            )
+            .field("core_0_area_pif_0_max", &self.core_0_area_pif_0_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_0_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region0 end addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_area_pif_0_min.rs b/esp32s3/src/assist_debug/core_0_area_pif_0_min.rs
index 6ecf444727..88c0d9e5da 100644
--- a/esp32s3/src/assist_debug/core_0_area_pif_0_min.rs
+++ b/esp32s3/src/assist_debug/core_0_area_pif_0_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_0_MIN")
-            .field(
-                "core_0_area_pif_0_min",
-                &format_args!("{}", self.core_0_area_pif_0_min().bits()),
-            )
+            .field("core_0_area_pif_0_min", &self.core_0_area_pif_0_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_0_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region0 start addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_area_pif_1_max.rs b/esp32s3/src/assist_debug/core_0_area_pif_1_max.rs
index 1d79804931..5a00986603 100644
--- a/esp32s3/src/assist_debug/core_0_area_pif_1_max.rs
+++ b/esp32s3/src/assist_debug/core_0_area_pif_1_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_1_MAX")
-            .field(
-                "core_0_area_pif_1_max",
-                &format_args!("{}", self.core_0_area_pif_1_max().bits()),
-            )
+            .field("core_0_area_pif_1_max", &self.core_0_area_pif_1_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_1_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region1 end addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_area_pif_1_min.rs b/esp32s3/src/assist_debug/core_0_area_pif_1_min.rs
index 7a20c8326f..d75bae477d 100644
--- a/esp32s3/src/assist_debug/core_0_area_pif_1_min.rs
+++ b/esp32s3/src/assist_debug/core_0_area_pif_1_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_PIF_1_MIN")
-            .field(
-                "core_0_area_pif_1_min",
-                &format_args!("{}", self.core_0_area_pif_1_min().bits()),
-            )
+            .field("core_0_area_pif_1_min", &self.core_0_area_pif_1_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_PIF_1_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core0 PIF region1 start addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_area_sp.rs b/esp32s3/src/assist_debug/core_0_area_sp.rs
index d6aeb58a81..c673de24f2 100644
--- a/esp32s3/src/assist_debug/core_0_area_sp.rs
+++ b/esp32s3/src/assist_debug/core_0_area_sp.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_AREA_SP")
-            .field(
-                "core_0_area_sp",
-                &format_args!("{}", self.core_0_area_sp().bits()),
-            )
+            .field("core_0_area_sp", &self.core_0_area_sp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_AREA_SP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 area sp status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_area_sp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_AREA_SP_SPEC;
 impl crate::RegisterSpec for CORE_0_AREA_SP_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_0.rs b/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_0.rs
index 58d3f4f402..e2fa0455c1 100644
--- a/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_0.rs
+++ b/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_0.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_0_dram0_recording_addr_0",
-                &format_args!("{}", self.core_0_dram0_recording_addr_0().bits()),
+                &self.core_0_dram0_recording_addr_0(),
             )
             .field(
                 "core_0_dram0_recording_wr_0",
-                &format_args!("{}", self.core_0_dram0_recording_wr_0().bit()),
+                &self.core_0_dram0_recording_wr_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 bus busy status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_1.rs b/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_1.rs
index ff85d77d11..26df38e5f0 100644
--- a/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_1.rs
+++ b/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_0_dram0_recording_byteen_0",
-                &format_args!("{}", self.core_0_dram0_recording_byteen_0().bits()),
+                &self.core_0_dram0_recording_byteen_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 bus busy status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_2.rs b/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_2.rs
index d7bbb84d4b..508c178933 100644
--- a/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_2.rs
+++ b/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_2")
             .field(
                 "core_0_dram0_recording_pc_0",
-                &format_args!("{}", self.core_0_dram0_recording_pc_0().bits()),
+                &self.core_0_dram0_recording_pc_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 bus busy status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_3.rs b/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_3.rs
index cad39cc622..eaf6adac75 100644
--- a/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_3.rs
+++ b/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_3.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_3")
             .field(
                 "core_0_dram0_recording_addr_1",
-                &format_args!("{}", self.core_0_dram0_recording_addr_1().bits()),
+                &self.core_0_dram0_recording_addr_1(),
             )
             .field(
                 "core_0_dram0_recording_wr_1",
-                &format_args!("{}", self.core_0_dram0_recording_wr_1().bit()),
+                &self.core_0_dram0_recording_wr_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 bus busy status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_4.rs b/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_4.rs
index 5040eaacac..9a474742ca 100644
--- a/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_4.rs
+++ b/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_4")
             .field(
                 "core_0_dram0_recording_byteen_1",
-                &format_args!("{}", self.core_0_dram0_recording_byteen_1().bits()),
+                &self.core_0_dram0_recording_byteen_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 bus busy configuration regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_4_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_5.rs b/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_5.rs
index 5842bb5881..d3301c61be 100644
--- a/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_5.rs
+++ b/esp32s3/src/assist_debug/core_0_dram0_exception_monitor_5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_EXCEPTION_MONITOR_5")
             .field(
                 "core_0_dram0_recording_pc_1",
-                &format_args!("{}", self.core_0_dram0_recording_pc_1().bits()),
+                &self.core_0_dram0_recording_pc_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 bus busy configuration regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_exception_monitor_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_EXCEPTION_MONITOR_5_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_intr_clr.rs b/esp32s3/src/assist_debug/core_0_intr_clr.rs
index ad7f9932a9..504e36f8c8 100644
--- a/esp32s3/src/assist_debug/core_0_intr_clr.rs
+++ b/esp32s3/src/assist_debug/core_0_intr_clr.rs
@@ -118,61 +118,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_INTR_CLR")
             .field(
                 "core_0_area_dram0_0_rd_clr",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_clr().bit()),
+                &self.core_0_area_dram0_0_rd_clr(),
             )
             .field(
                 "core_0_area_dram0_0_wr_clr",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_clr().bit()),
+                &self.core_0_area_dram0_0_wr_clr(),
             )
             .field(
                 "core_0_area_dram0_1_rd_clr",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_clr().bit()),
+                &self.core_0_area_dram0_1_rd_clr(),
             )
             .field(
                 "core_0_area_dram0_1_wr_clr",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_clr().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_rd_clr",
-                &format_args!("{}", self.core_0_area_pif_0_rd_clr().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_wr_clr",
-                &format_args!("{}", self.core_0_area_pif_0_wr_clr().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_rd_clr",
-                &format_args!("{}", self.core_0_area_pif_1_rd_clr().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_wr_clr",
-                &format_args!("{}", self.core_0_area_pif_1_wr_clr().bit()),
-            )
-            .field(
-                "core_0_sp_spill_min_clr",
-                &format_args!("{}", self.core_0_sp_spill_min_clr().bit()),
-            )
-            .field(
-                "core_0_sp_spill_max_clr",
-                &format_args!("{}", self.core_0_sp_spill_max_clr().bit()),
+                &self.core_0_area_dram0_1_wr_clr(),
             )
+            .field("core_0_area_pif_0_rd_clr", &self.core_0_area_pif_0_rd_clr())
+            .field("core_0_area_pif_0_wr_clr", &self.core_0_area_pif_0_wr_clr())
+            .field("core_0_area_pif_1_rd_clr", &self.core_0_area_pif_1_rd_clr())
+            .field("core_0_area_pif_1_wr_clr", &self.core_0_area_pif_1_wr_clr())
+            .field("core_0_sp_spill_min_clr", &self.core_0_sp_spill_min_clr())
+            .field("core_0_sp_spill_max_clr", &self.core_0_sp_spill_max_clr())
             .field(
                 "core_0_iram0_exception_monitor_clr",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_clr().bit()),
+                &self.core_0_iram0_exception_monitor_clr(),
             )
             .field(
                 "core_0_dram0_exception_monitor_clr",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_clr().bit()),
+                &self.core_0_dram0_exception_monitor_clr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_INTR_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt clr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_intr_ena.rs b/esp32s3/src/assist_debug/core_0_intr_ena.rs
index 0aec36135c..52bd25880d 100644
--- a/esp32s3/src/assist_debug/core_0_intr_ena.rs
+++ b/esp32s3/src/assist_debug/core_0_intr_ena.rs
@@ -122,61 +122,55 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_INTR_ENA")
             .field(
                 "core_0_area_dram0_0_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_intr_ena().bit()),
+                &self.core_0_area_dram0_0_rd_intr_ena(),
             )
             .field(
                 "core_0_area_dram0_0_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_intr_ena().bit()),
+                &self.core_0_area_dram0_0_wr_intr_ena(),
             )
             .field(
                 "core_0_area_dram0_1_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_intr_ena().bit()),
+                &self.core_0_area_dram0_1_rd_intr_ena(),
             )
             .field(
                 "core_0_area_dram0_1_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_intr_ena().bit()),
+                &self.core_0_area_dram0_1_wr_intr_ena(),
             )
             .field(
                 "core_0_area_pif_0_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_0_rd_intr_ena().bit()),
+                &self.core_0_area_pif_0_rd_intr_ena(),
             )
             .field(
                 "core_0_area_pif_0_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_0_wr_intr_ena().bit()),
+                &self.core_0_area_pif_0_wr_intr_ena(),
             )
             .field(
                 "core_0_area_pif_1_rd_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_1_rd_intr_ena().bit()),
+                &self.core_0_area_pif_1_rd_intr_ena(),
             )
             .field(
                 "core_0_area_pif_1_wr_intr_ena",
-                &format_args!("{}", self.core_0_area_pif_1_wr_intr_ena().bit()),
+                &self.core_0_area_pif_1_wr_intr_ena(),
             )
             .field(
                 "core_0_sp_spill_min_intr_ena",
-                &format_args!("{}", self.core_0_sp_spill_min_intr_ena().bit()),
+                &self.core_0_sp_spill_min_intr_ena(),
             )
             .field(
                 "core_0_sp_spill_max_intr_ena",
-                &format_args!("{}", self.core_0_sp_spill_max_intr_ena().bit()),
+                &self.core_0_sp_spill_max_intr_ena(),
             )
             .field(
                 "core_0_iram0_exception_monitor_intr_ena",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_intr_ena().bit()),
+                &self.core_0_iram0_exception_monitor_intr_ena(),
             )
             .field(
                 "core_0_dram0_exception_monitor_intr_ena",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_intr_ena().bit()),
+                &self.core_0_dram0_exception_monitor_intr_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_INTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core0 dram0 area0 read monitor interrupt enable"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_intr_raw.rs b/esp32s3/src/assist_debug/core_0_intr_raw.rs
index e8d4346c09..93064564c6 100644
--- a/esp32s3/src/assist_debug/core_0_intr_raw.rs
+++ b/esp32s3/src/assist_debug/core_0_intr_raw.rs
@@ -92,61 +92,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_INTR_RAW")
             .field(
                 "core_0_area_dram0_0_rd_raw",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_raw().bit()),
+                &self.core_0_area_dram0_0_rd_raw(),
             )
             .field(
                 "core_0_area_dram0_0_wr_raw",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_raw().bit()),
+                &self.core_0_area_dram0_0_wr_raw(),
             )
             .field(
                 "core_0_area_dram0_1_rd_raw",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_raw().bit()),
+                &self.core_0_area_dram0_1_rd_raw(),
             )
             .field(
                 "core_0_area_dram0_1_wr_raw",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_rd_raw",
-                &format_args!("{}", self.core_0_area_pif_0_rd_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_wr_raw",
-                &format_args!("{}", self.core_0_area_pif_0_wr_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_rd_raw",
-                &format_args!("{}", self.core_0_area_pif_1_rd_raw().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_wr_raw",
-                &format_args!("{}", self.core_0_area_pif_1_wr_raw().bit()),
-            )
-            .field(
-                "core_0_sp_spill_min_raw",
-                &format_args!("{}", self.core_0_sp_spill_min_raw().bit()),
-            )
-            .field(
-                "core_0_sp_spill_max_raw",
-                &format_args!("{}", self.core_0_sp_spill_max_raw().bit()),
+                &self.core_0_area_dram0_1_wr_raw(),
             )
+            .field("core_0_area_pif_0_rd_raw", &self.core_0_area_pif_0_rd_raw())
+            .field("core_0_area_pif_0_wr_raw", &self.core_0_area_pif_0_wr_raw())
+            .field("core_0_area_pif_1_rd_raw", &self.core_0_area_pif_1_rd_raw())
+            .field("core_0_area_pif_1_wr_raw", &self.core_0_area_pif_1_wr_raw())
+            .field("core_0_sp_spill_min_raw", &self.core_0_sp_spill_min_raw())
+            .field("core_0_sp_spill_max_raw", &self.core_0_sp_spill_max_raw())
             .field(
                 "core_0_iram0_exception_monitor_raw",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_raw().bit()),
+                &self.core_0_iram0_exception_monitor_raw(),
             )
             .field(
                 "core_0_dram0_exception_monitor_raw",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_raw().bit()),
+                &self.core_0_dram0_exception_monitor_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_INTR_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 monitor interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_intr_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_INTR_RAW_SPEC;
 impl crate::RegisterSpec for CORE_0_INTR_RAW_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_iram0_exception_monitor_0.rs b/esp32s3/src/assist_debug/core_0_iram0_exception_monitor_0.rs
index 3994635294..b8730e8201 100644
--- a/esp32s3/src/assist_debug/core_0_iram0_exception_monitor_0.rs
+++ b/esp32s3/src/assist_debug/core_0_iram0_exception_monitor_0.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_0_iram0_recording_addr_0",
-                &format_args!("{}", self.core_0_iram0_recording_addr_0().bits()),
+                &self.core_0_iram0_recording_addr_0(),
             )
             .field(
                 "core_0_iram0_recording_wr_0",
-                &format_args!("{}", self.core_0_iram0_recording_wr_0().bit()),
+                &self.core_0_iram0_recording_wr_0(),
             )
             .field(
                 "core_0_iram0_recording_loadstore_0",
-                &format_args!("{}", self.core_0_iram0_recording_loadstore_0().bit()),
+                &self.core_0_iram0_recording_loadstore_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 bus busy status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_exception_monitor_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC;
 impl crate::RegisterSpec for CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_iram0_exception_monitor_1.rs b/esp32s3/src/assist_debug/core_0_iram0_exception_monitor_1.rs
index febf9525ab..535b73295f 100644
--- a/esp32s3/src/assist_debug/core_0_iram0_exception_monitor_1.rs
+++ b/esp32s3/src/assist_debug/core_0_iram0_exception_monitor_1.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_0_iram0_recording_addr_1",
-                &format_args!("{}", self.core_0_iram0_recording_addr_1().bits()),
+                &self.core_0_iram0_recording_addr_1(),
             )
             .field(
                 "core_0_iram0_recording_wr_1",
-                &format_args!("{}", self.core_0_iram0_recording_wr_1().bit()),
+                &self.core_0_iram0_recording_wr_1(),
             )
             .field(
                 "core_0_iram0_recording_loadstore_1",
-                &format_args!("{}", self.core_0_iram0_recording_loadstore_1().bit()),
+                &self.core_0_iram0_recording_loadstore_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 bus busy status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_exception_monitor_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC;
 impl crate::RegisterSpec for CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_montr_ena.rs b/esp32s3/src/assist_debug/core_0_montr_ena.rs
index 3880905834..c173e5e9dd 100644
--- a/esp32s3/src/assist_debug/core_0_montr_ena.rs
+++ b/esp32s3/src/assist_debug/core_0_montr_ena.rs
@@ -118,61 +118,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_MONTR_ENA")
             .field(
                 "core_0_area_dram0_0_rd_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_rd_ena().bit()),
+                &self.core_0_area_dram0_0_rd_ena(),
             )
             .field(
                 "core_0_area_dram0_0_wr_ena",
-                &format_args!("{}", self.core_0_area_dram0_0_wr_ena().bit()),
+                &self.core_0_area_dram0_0_wr_ena(),
             )
             .field(
                 "core_0_area_dram0_1_rd_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_rd_ena().bit()),
+                &self.core_0_area_dram0_1_rd_ena(),
             )
             .field(
                 "core_0_area_dram0_1_wr_ena",
-                &format_args!("{}", self.core_0_area_dram0_1_wr_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_rd_ena",
-                &format_args!("{}", self.core_0_area_pif_0_rd_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_0_wr_ena",
-                &format_args!("{}", self.core_0_area_pif_0_wr_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_rd_ena",
-                &format_args!("{}", self.core_0_area_pif_1_rd_ena().bit()),
-            )
-            .field(
-                "core_0_area_pif_1_wr_ena",
-                &format_args!("{}", self.core_0_area_pif_1_wr_ena().bit()),
-            )
-            .field(
-                "core_0_sp_spill_min_ena",
-                &format_args!("{}", self.core_0_sp_spill_min_ena().bit()),
-            )
-            .field(
-                "core_0_sp_spill_max_ena",
-                &format_args!("{}", self.core_0_sp_spill_max_ena().bit()),
+                &self.core_0_area_dram0_1_wr_ena(),
             )
+            .field("core_0_area_pif_0_rd_ena", &self.core_0_area_pif_0_rd_ena())
+            .field("core_0_area_pif_0_wr_ena", &self.core_0_area_pif_0_wr_ena())
+            .field("core_0_area_pif_1_rd_ena", &self.core_0_area_pif_1_rd_ena())
+            .field("core_0_area_pif_1_wr_ena", &self.core_0_area_pif_1_wr_ena())
+            .field("core_0_sp_spill_min_ena", &self.core_0_sp_spill_min_ena())
+            .field("core_0_sp_spill_max_ena", &self.core_0_sp_spill_max_ena())
             .field(
                 "core_0_iram0_exception_monitor_ena",
-                &format_args!("{}", self.core_0_iram0_exception_monitor_ena().bit()),
+                &self.core_0_iram0_exception_monitor_ena(),
             )
             .field(
                 "core_0_dram0_exception_monitor_ena",
-                &format_args!("{}", self.core_0_dram0_exception_monitor_ena().bit()),
+                &self.core_0_dram0_exception_monitor_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_MONTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core0 dram0 area0 read monitor enable"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_rcd_pdebugdata.rs b/esp32s3/src/assist_debug/core_0_rcd_pdebugdata.rs
index 1944ee0646..1ba816c30c 100644
--- a/esp32s3/src/assist_debug/core_0_rcd_pdebugdata.rs
+++ b/esp32s3/src/assist_debug/core_0_rcd_pdebugdata.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGDATA")
-            .field(
-                "core_0_rcd_pdebugdata",
-                &format_args!("{}", self.core_0_rcd_pdebugdata().bits()),
-            )
+            .field("core_0_rcd_pdebugdata", &self.core_0_rcd_pdebugdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGDATA_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGDATA_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_rcd_pdebugenable.rs b/esp32s3/src/assist_debug/core_0_rcd_pdebugenable.rs
index 1e4c674090..a8191129d8 100644
--- a/esp32s3/src/assist_debug/core_0_rcd_pdebugenable.rs
+++ b/esp32s3/src/assist_debug/core_0_rcd_pdebugenable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGENABLE")
-            .field(
-                "core_0_rcd_pdebugenable",
-                &format_args!("{}", self.core_0_rcd_pdebugenable().bit()),
-            )
+            .field("core_0_rcd_pdebugenable", &self.core_0_rcd_pdebugenable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core0 Pdebugenable,set 1 to open core0 Pdebug interface,then can get core0 PC"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_rcd_pdebuginst.rs b/esp32s3/src/assist_debug/core_0_rcd_pdebuginst.rs
index b0f17a0fc6..1dcae9d154 100644
--- a/esp32s3/src/assist_debug/core_0_rcd_pdebuginst.rs
+++ b/esp32s3/src/assist_debug/core_0_rcd_pdebuginst.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGINST")
-            .field(
-                "core_0_rcd_pdebuginst",
-                &format_args!("{}", self.core_0_rcd_pdebuginst().bits()),
-            )
+            .field("core_0_rcd_pdebuginst", &self.core_0_rcd_pdebuginst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGINST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebuginst::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGINST_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGINST_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_rcd_pdebugls0addr.rs b/esp32s3/src/assist_debug/core_0_rcd_pdebugls0addr.rs
index 4d755b2ee2..a26bebeec3 100644
--- a/esp32s3/src/assist_debug/core_0_rcd_pdebugls0addr.rs
+++ b/esp32s3/src/assist_debug/core_0_rcd_pdebugls0addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGLS0ADDR")
-            .field(
-                "core_0_rcd_pdebugls0addr",
-                &format_args!("{}", self.core_0_rcd_pdebugls0addr().bits()),
-            )
+            .field("core_0_rcd_pdebugls0addr", &self.core_0_rcd_pdebugls0addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGLS0ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugls0addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGLS0ADDR_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGLS0ADDR_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_rcd_pdebugls0data.rs b/esp32s3/src/assist_debug/core_0_rcd_pdebugls0data.rs
index a8b812cfa1..212cbba68e 100644
--- a/esp32s3/src/assist_debug/core_0_rcd_pdebugls0data.rs
+++ b/esp32s3/src/assist_debug/core_0_rcd_pdebugls0data.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGLS0DATA")
-            .field(
-                "core_0_rcd_pdebugls0data",
-                &format_args!("{}", self.core_0_rcd_pdebugls0data().bits()),
-            )
+            .field("core_0_rcd_pdebugls0data", &self.core_0_rcd_pdebugls0data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGLS0DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugls0data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGLS0DATA_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGLS0DATA_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_rcd_pdebugls0stat.rs b/esp32s3/src/assist_debug/core_0_rcd_pdebugls0stat.rs
index f4cfe0844a..f6c140ff35 100644
--- a/esp32s3/src/assist_debug/core_0_rcd_pdebugls0stat.rs
+++ b/esp32s3/src/assist_debug/core_0_rcd_pdebugls0stat.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGLS0STAT")
-            .field(
-                "core_0_rcd_pdebugls0stat",
-                &format_args!("{}", self.core_0_rcd_pdebugls0stat().bits()),
-            )
+            .field("core_0_rcd_pdebugls0stat", &self.core_0_rcd_pdebugls0stat())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGLS0STAT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugls0stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGLS0STAT_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGLS0STAT_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_rcd_pdebugpc.rs b/esp32s3/src/assist_debug/core_0_rcd_pdebugpc.rs
index e6a1b83703..8937c1dfb5 100644
--- a/esp32s3/src/assist_debug/core_0_rcd_pdebugpc.rs
+++ b/esp32s3/src/assist_debug/core_0_rcd_pdebugpc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGPC")
-            .field(
-                "core_0_rcd_pdebugpc",
-                &format_args!("{}", self.core_0_rcd_pdebugpc().bits()),
-            )
+            .field("core_0_rcd_pdebugpc", &self.core_0_rcd_pdebugpc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGPC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugpc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGPC_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGPC_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_rcd_pdebugstatus.rs b/esp32s3/src/assist_debug/core_0_rcd_pdebugstatus.rs
index c33b49f1f4..38670f2ec8 100644
--- a/esp32s3/src/assist_debug/core_0_rcd_pdebugstatus.rs
+++ b/esp32s3/src/assist_debug/core_0_rcd_pdebugstatus.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_PDEBUGSTATUS")
-            .field(
-                "core_0_rcd_pdebugstatus",
-                &format_args!("{}", self.core_0_rcd_pdebugstatus().bits()),
-            )
+            .field("core_0_rcd_pdebugstatus", &self.core_0_rcd_pdebugstatus())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_PDEBUGSTATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_pdebugstatus::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_PDEBUGSTATUS_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_PDEBUGSTATUS_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_rcd_recording.rs b/esp32s3/src/assist_debug/core_0_rcd_recording.rs
index e3db508ba9..ba7e180699 100644
--- a/esp32s3/src/assist_debug/core_0_rcd_recording.rs
+++ b/esp32s3/src/assist_debug/core_0_rcd_recording.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_RECORDING")
-            .field(
-                "core_0_rcd_recording",
-                &format_args!("{}", self.core_0_rcd_recording().bit()),
-            )
+            .field("core_0_rcd_recording", &self.core_0_rcd_recording())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_RECORDING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Pdebug record enable,set 1 to record core0 pdebug interface signal"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_rcd_sp.rs b/esp32s3/src/assist_debug/core_0_rcd_sp.rs
index 961b1d7e86..ae85e91721 100644
--- a/esp32s3/src/assist_debug/core_0_rcd_sp.rs
+++ b/esp32s3/src/assist_debug/core_0_rcd_sp.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_RCD_SP")
-            .field(
-                "core_0_rcd_sp",
-                &format_args!("{}", self.core_0_rcd_sp().bits()),
-            )
+            .field("core_0_rcd_sp", &self.core_0_rcd_sp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_RCD_SP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_rcd_sp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_RCD_SP_SPEC;
 impl crate::RegisterSpec for CORE_0_RCD_SP_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_sp_max.rs b/esp32s3/src/assist_debug/core_0_sp_max.rs
index 242f4494eb..33e92bc5af 100644
--- a/esp32s3/src/assist_debug/core_0_sp_max.rs
+++ b/esp32s3/src/assist_debug/core_0_sp_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_MAX")
-            .field(
-                "core_0_sp_max",
-                &format_args!("{}", self.core_0_sp_max().bits()),
-            )
+            .field("core_0_sp_max", &self.core_0_sp_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - stack max value"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_sp_min.rs b/esp32s3/src/assist_debug/core_0_sp_min.rs
index 1ae54d3e9c..e147fb40eb 100644
--- a/esp32s3/src/assist_debug/core_0_sp_min.rs
+++ b/esp32s3/src/assist_debug/core_0_sp_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_MIN")
-            .field(
-                "core_0_sp_min",
-                &format_args!("{}", self.core_0_sp_min().bits()),
-            )
+            .field("core_0_sp_min", &self.core_0_sp_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - stack min value"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_0_sp_pc.rs b/esp32s3/src/assist_debug/core_0_sp_pc.rs
index f206066ea6..5ca7a7c3f2 100644
--- a/esp32s3/src/assist_debug/core_0_sp_pc.rs
+++ b/esp32s3/src/assist_debug/core_0_sp_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_PC")
-            .field(
-                "core_0_sp_pc",
-                &format_args!("{}", self.core_0_sp_pc().bits()),
-            )
+            .field("core_0_sp_pc", &self.core_0_sp_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 sp pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_sp_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_SP_PC_SPEC;
 impl crate::RegisterSpec for CORE_0_SP_PC_SPEC {
diff --git a/esp32s3/src/assist_debug/core_0_sp_unstable.rs b/esp32s3/src/assist_debug/core_0_sp_unstable.rs
index 954b3cea11..174ca80ff0 100644
--- a/esp32s3/src/assist_debug/core_0_sp_unstable.rs
+++ b/esp32s3/src/assist_debug/core_0_sp_unstable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_0_SP_UNSTABLE")
-            .field(
-                "core_0_sp_unstable",
-                &format_args!("{}", self.core_0_sp_unstable().bits()),
-            )
+            .field("core_0_sp_unstable", &self.core_0_sp_unstable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_SP_UNSTABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - unstable period when window change,during this period no check stackpointer"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_area_dram0_0_max.rs b/esp32s3/src/assist_debug/core_1_area_dram0_0_max.rs
index 6f2bcc8e4f..5b7826255c 100644
--- a/esp32s3/src/assist_debug/core_1_area_dram0_0_max.rs
+++ b/esp32s3/src/assist_debug/core_1_area_dram0_0_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_DRAM0_0_MAX")
-            .field(
-                "core_1_area_dram0_0_max",
-                &format_args!("{}", self.core_1_area_dram0_0_max().bits()),
-            )
+            .field("core_1_area_dram0_0_max", &self.core_1_area_dram0_0_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_DRAM0_0_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 dram0 region0 end addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_area_dram0_0_min.rs b/esp32s3/src/assist_debug/core_1_area_dram0_0_min.rs
index 8fd4e60e34..32d39fa1ea 100644
--- a/esp32s3/src/assist_debug/core_1_area_dram0_0_min.rs
+++ b/esp32s3/src/assist_debug/core_1_area_dram0_0_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_DRAM0_0_MIN")
-            .field(
-                "core_1_area_dram0_0_min",
-                &format_args!("{}", self.core_1_area_dram0_0_min().bits()),
-            )
+            .field("core_1_area_dram0_0_min", &self.core_1_area_dram0_0_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_DRAM0_0_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 dram0 region0 start addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_area_dram0_1_max.rs b/esp32s3/src/assist_debug/core_1_area_dram0_1_max.rs
index 65c6946024..034e1188fe 100644
--- a/esp32s3/src/assist_debug/core_1_area_dram0_1_max.rs
+++ b/esp32s3/src/assist_debug/core_1_area_dram0_1_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_DRAM0_1_MAX")
-            .field(
-                "core_1_area_dram0_1_max",
-                &format_args!("{}", self.core_1_area_dram0_1_max().bits()),
-            )
+            .field("core_1_area_dram0_1_max", &self.core_1_area_dram0_1_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_DRAM0_1_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 dram0 region1 end addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_area_dram0_1_min.rs b/esp32s3/src/assist_debug/core_1_area_dram0_1_min.rs
index 6388551dce..8f52713572 100644
--- a/esp32s3/src/assist_debug/core_1_area_dram0_1_min.rs
+++ b/esp32s3/src/assist_debug/core_1_area_dram0_1_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_DRAM0_1_MIN")
-            .field(
-                "core_1_area_dram0_1_min",
-                &format_args!("{}", self.core_1_area_dram0_1_min().bits()),
-            )
+            .field("core_1_area_dram0_1_min", &self.core_1_area_dram0_1_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_DRAM0_1_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 dram0 region1 start addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_area_pc.rs b/esp32s3/src/assist_debug/core_1_area_pc.rs
index ab6e54ae84..aa9a386eb8 100644
--- a/esp32s3/src/assist_debug/core_1_area_pc.rs
+++ b/esp32s3/src/assist_debug/core_1_area_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_PC")
-            .field(
-                "core_1_area_pc",
-                &format_args!("{}", self.core_1_area_pc().bits()),
-            )
+            .field("core_1_area_pc", &self.core_1_area_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 area sp status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_AREA_PC_SPEC;
 impl crate::RegisterSpec for CORE_1_AREA_PC_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_area_pif_0_max.rs b/esp32s3/src/assist_debug/core_1_area_pif_0_max.rs
index ef9ccde91c..4da69186fe 100644
--- a/esp32s3/src/assist_debug/core_1_area_pif_0_max.rs
+++ b/esp32s3/src/assist_debug/core_1_area_pif_0_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_PIF_0_MAX")
-            .field(
-                "core_1_area_pif_0_max",
-                &format_args!("{}", self.core_1_area_pif_0_max().bits()),
-            )
+            .field("core_1_area_pif_0_max", &self.core_1_area_pif_0_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_PIF_0_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 PIF region0 end addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_area_pif_0_min.rs b/esp32s3/src/assist_debug/core_1_area_pif_0_min.rs
index f3cb3e32fe..ded086cca5 100644
--- a/esp32s3/src/assist_debug/core_1_area_pif_0_min.rs
+++ b/esp32s3/src/assist_debug/core_1_area_pif_0_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_PIF_0_MIN")
-            .field(
-                "core_1_area_pif_0_min",
-                &format_args!("{}", self.core_1_area_pif_0_min().bits()),
-            )
+            .field("core_1_area_pif_0_min", &self.core_1_area_pif_0_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_PIF_0_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 PIF region0 start addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_area_pif_1_max.rs b/esp32s3/src/assist_debug/core_1_area_pif_1_max.rs
index 457db0737c..3830366fa9 100644
--- a/esp32s3/src/assist_debug/core_1_area_pif_1_max.rs
+++ b/esp32s3/src/assist_debug/core_1_area_pif_1_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_PIF_1_MAX")
-            .field(
-                "core_1_area_pif_1_max",
-                &format_args!("{}", self.core_1_area_pif_1_max().bits()),
-            )
+            .field("core_1_area_pif_1_max", &self.core_1_area_pif_1_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_PIF_1_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 PIF region1 end addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_area_pif_1_min.rs b/esp32s3/src/assist_debug/core_1_area_pif_1_min.rs
index 88fa5b534c..0200e3988d 100644
--- a/esp32s3/src/assist_debug/core_1_area_pif_1_min.rs
+++ b/esp32s3/src/assist_debug/core_1_area_pif_1_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_PIF_1_MIN")
-            .field(
-                "core_1_area_pif_1_min",
-                &format_args!("{}", self.core_1_area_pif_1_min().bits()),
-            )
+            .field("core_1_area_pif_1_min", &self.core_1_area_pif_1_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_PIF_1_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core1 PIF region1 start addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_area_sp.rs b/esp32s3/src/assist_debug/core_1_area_sp.rs
index b1ac8777db..407e294884 100644
--- a/esp32s3/src/assist_debug/core_1_area_sp.rs
+++ b/esp32s3/src/assist_debug/core_1_area_sp.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_AREA_SP")
-            .field(
-                "core_1_area_sp",
-                &format_args!("{}", self.core_1_area_sp().bits()),
-            )
+            .field("core_1_area_sp", &self.core_1_area_sp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_AREA_SP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 area pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_area_sp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_AREA_SP_SPEC;
 impl crate::RegisterSpec for CORE_1_AREA_SP_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_0.rs b/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_0.rs
index 579246764e..cc7aac730a 100644
--- a/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_0.rs
+++ b/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_0.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_1_dram0_recording_addr_0",
-                &format_args!("{}", self.core_1_dram0_recording_addr_0().bits()),
+                &self.core_1_dram0_recording_addr_0(),
             )
             .field(
                 "core_1_dram0_recording_wr_0",
-                &format_args!("{}", self.core_1_dram0_recording_wr_0().bit()),
+                &self.core_1_dram0_recording_wr_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC;
 impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_0_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_1.rs b/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_1.rs
index acc28d2993..c478930db1 100644
--- a/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_1.rs
+++ b/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_1_dram0_recording_byteen_0",
-                &format_args!("{}", self.core_1_dram0_recording_byteen_0().bits()),
+                &self.core_1_dram0_recording_byteen_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC;
 impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_1_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_2.rs b/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_2.rs
index c38410dd49..c270090087 100644
--- a/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_2.rs
+++ b/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_2")
             .field(
                 "core_1_dram0_recording_pc_0",
-                &format_args!("{}", self.core_1_dram0_recording_pc_0().bits()),
+                &self.core_1_dram0_recording_pc_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_2_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_3.rs b/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_3.rs
index 6b8aafc4dc..0629d71c02 100644
--- a/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_3.rs
+++ b/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_3.rs
@@ -22,21 +22,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_3")
             .field(
                 "core_1_dram0_recording_addr_1",
-                &format_args!("{}", self.core_1_dram0_recording_addr_1().bits()),
+                &self.core_1_dram0_recording_addr_1(),
             )
             .field(
                 "core_1_dram0_recording_wr_1",
-                &format_args!("{}", self.core_1_dram0_recording_wr_1().bit()),
+                &self.core_1_dram0_recording_wr_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC;
 impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_3_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_4.rs b/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_4.rs
index 089873e922..fc64c33b4c 100644
--- a/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_4.rs
+++ b/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_4.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_4")
             .field(
                 "core_1_dram0_recording_byteen_1",
-                &format_args!("{}", self.core_1_dram0_recording_byteen_1().bits()),
+                &self.core_1_dram0_recording_byteen_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC;
 impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_4_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_5.rs b/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_5.rs
index d93aaad59e..bcaaee0697 100644
--- a/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_5.rs
+++ b/esp32s3/src/assist_debug/core_1_dram0_exception_monitor_5.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_EXCEPTION_MONITOR_5")
             .field(
                 "core_1_dram0_recording_pc_1",
-                &format_args!("{}", self.core_1_dram0_recording_pc_1().bits()),
+                &self.core_1_dram0_recording_pc_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_exception_monitor_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC;
 impl crate::RegisterSpec for CORE_1_DRAM0_EXCEPTION_MONITOR_5_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_intr_clr.rs b/esp32s3/src/assist_debug/core_1_intr_clr.rs
index ba0a6102ee..bf04e2ccc8 100644
--- a/esp32s3/src/assist_debug/core_1_intr_clr.rs
+++ b/esp32s3/src/assist_debug/core_1_intr_clr.rs
@@ -118,61 +118,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_INTR_CLR")
             .field(
                 "core_1_area_dram0_0_rd_clr",
-                &format_args!("{}", self.core_1_area_dram0_0_rd_clr().bit()),
+                &self.core_1_area_dram0_0_rd_clr(),
             )
             .field(
                 "core_1_area_dram0_0_wr_clr",
-                &format_args!("{}", self.core_1_area_dram0_0_wr_clr().bit()),
+                &self.core_1_area_dram0_0_wr_clr(),
             )
             .field(
                 "core_1_area_dram0_1_rd_clr",
-                &format_args!("{}", self.core_1_area_dram0_1_rd_clr().bit()),
+                &self.core_1_area_dram0_1_rd_clr(),
             )
             .field(
                 "core_1_area_dram0_1_wr_clr",
-                &format_args!("{}", self.core_1_area_dram0_1_wr_clr().bit()),
-            )
-            .field(
-                "core_1_area_pif_0_rd_clr",
-                &format_args!("{}", self.core_1_area_pif_0_rd_clr().bit()),
-            )
-            .field(
-                "core_1_area_pif_0_wr_clr",
-                &format_args!("{}", self.core_1_area_pif_0_wr_clr().bit()),
-            )
-            .field(
-                "core_1_area_pif_1_rd_clr",
-                &format_args!("{}", self.core_1_area_pif_1_rd_clr().bit()),
-            )
-            .field(
-                "core_1_area_pif_1_wr_clr",
-                &format_args!("{}", self.core_1_area_pif_1_wr_clr().bit()),
-            )
-            .field(
-                "core_1_sp_spill_min_clr",
-                &format_args!("{}", self.core_1_sp_spill_min_clr().bit()),
-            )
-            .field(
-                "core_1_sp_spill_max_clr",
-                &format_args!("{}", self.core_1_sp_spill_max_clr().bit()),
+                &self.core_1_area_dram0_1_wr_clr(),
             )
+            .field("core_1_area_pif_0_rd_clr", &self.core_1_area_pif_0_rd_clr())
+            .field("core_1_area_pif_0_wr_clr", &self.core_1_area_pif_0_wr_clr())
+            .field("core_1_area_pif_1_rd_clr", &self.core_1_area_pif_1_rd_clr())
+            .field("core_1_area_pif_1_wr_clr", &self.core_1_area_pif_1_wr_clr())
+            .field("core_1_sp_spill_min_clr", &self.core_1_sp_spill_min_clr())
+            .field("core_1_sp_spill_max_clr", &self.core_1_sp_spill_max_clr())
             .field(
                 "core_1_iram0_exception_monitor_clr",
-                &format_args!("{}", self.core_1_iram0_exception_monitor_clr().bit()),
+                &self.core_1_iram0_exception_monitor_clr(),
             )
             .field(
                 "core_1_dram0_exception_monitor_clr",
-                &format_args!("{}", self.core_1_dram0_exception_monitor_clr().bit()),
+                &self.core_1_dram0_exception_monitor_clr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_INTR_CLR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt clr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_intr_ena.rs b/esp32s3/src/assist_debug/core_1_intr_ena.rs
index 4b4b818c60..8fa0439e37 100644
--- a/esp32s3/src/assist_debug/core_1_intr_ena.rs
+++ b/esp32s3/src/assist_debug/core_1_intr_ena.rs
@@ -122,61 +122,55 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_INTR_ENA")
             .field(
                 "core_1_area_dram0_0_rd_intr_ena",
-                &format_args!("{}", self.core_1_area_dram0_0_rd_intr_ena().bit()),
+                &self.core_1_area_dram0_0_rd_intr_ena(),
             )
             .field(
                 "core_1_area_dram0_0_wr_intr_ena",
-                &format_args!("{}", self.core_1_area_dram0_0_wr_intr_ena().bit()),
+                &self.core_1_area_dram0_0_wr_intr_ena(),
             )
             .field(
                 "core_1_area_dram0_1_rd_intr_ena",
-                &format_args!("{}", self.core_1_area_dram0_1_rd_intr_ena().bit()),
+                &self.core_1_area_dram0_1_rd_intr_ena(),
             )
             .field(
                 "core_1_area_dram0_1_wr_intr_ena",
-                &format_args!("{}", self.core_1_area_dram0_1_wr_intr_ena().bit()),
+                &self.core_1_area_dram0_1_wr_intr_ena(),
             )
             .field(
                 "core_1_area_pif_0_rd_intr_ena",
-                &format_args!("{}", self.core_1_area_pif_0_rd_intr_ena().bit()),
+                &self.core_1_area_pif_0_rd_intr_ena(),
             )
             .field(
                 "core_1_area_pif_0_wr_intr_ena",
-                &format_args!("{}", self.core_1_area_pif_0_wr_intr_ena().bit()),
+                &self.core_1_area_pif_0_wr_intr_ena(),
             )
             .field(
                 "core_1_area_pif_1_rd_intr_ena",
-                &format_args!("{}", self.core_1_area_pif_1_rd_intr_ena().bit()),
+                &self.core_1_area_pif_1_rd_intr_ena(),
             )
             .field(
                 "core_1_area_pif_1_wr_intr_ena",
-                &format_args!("{}", self.core_1_area_pif_1_wr_intr_ena().bit()),
+                &self.core_1_area_pif_1_wr_intr_ena(),
             )
             .field(
                 "core_1_sp_spill_min_intr_ena",
-                &format_args!("{}", self.core_1_sp_spill_min_intr_ena().bit()),
+                &self.core_1_sp_spill_min_intr_ena(),
             )
             .field(
                 "core_1_sp_spill_max_intr_ena",
-                &format_args!("{}", self.core_1_sp_spill_max_intr_ena().bit()),
+                &self.core_1_sp_spill_max_intr_ena(),
             )
             .field(
                 "core_1_iram0_exception_monitor_intr_ena",
-                &format_args!("{}", self.core_1_iram0_exception_monitor_intr_ena().bit()),
+                &self.core_1_iram0_exception_monitor_intr_ena(),
             )
             .field(
                 "core_1_dram0_exception_monitor_intr_ena",
-                &format_args!("{}", self.core_1_dram0_exception_monitor_intr_ena().bit()),
+                &self.core_1_dram0_exception_monitor_intr_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_INTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core1 dram0 area0 read monitor interrupt enable"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_intr_raw.rs b/esp32s3/src/assist_debug/core_1_intr_raw.rs
index 717690309f..e8b6c38f51 100644
--- a/esp32s3/src/assist_debug/core_1_intr_raw.rs
+++ b/esp32s3/src/assist_debug/core_1_intr_raw.rs
@@ -92,61 +92,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_INTR_RAW")
             .field(
                 "core_1_area_dram0_0_rd_raw",
-                &format_args!("{}", self.core_1_area_dram0_0_rd_raw().bit()),
+                &self.core_1_area_dram0_0_rd_raw(),
             )
             .field(
                 "core_1_area_dram0_0_wr_raw",
-                &format_args!("{}", self.core_1_area_dram0_0_wr_raw().bit()),
+                &self.core_1_area_dram0_0_wr_raw(),
             )
             .field(
                 "core_1_area_dram0_1_rd_raw",
-                &format_args!("{}", self.core_1_area_dram0_1_rd_raw().bit()),
+                &self.core_1_area_dram0_1_rd_raw(),
             )
             .field(
                 "core_1_area_dram0_1_wr_raw",
-                &format_args!("{}", self.core_1_area_dram0_1_wr_raw().bit()),
-            )
-            .field(
-                "core_1_area_pif_0_rd_raw",
-                &format_args!("{}", self.core_1_area_pif_0_rd_raw().bit()),
-            )
-            .field(
-                "core_1_area_pif_0_wr_raw",
-                &format_args!("{}", self.core_1_area_pif_0_wr_raw().bit()),
-            )
-            .field(
-                "core_1_area_pif_1_rd_raw",
-                &format_args!("{}", self.core_1_area_pif_1_rd_raw().bit()),
-            )
-            .field(
-                "core_1_area_pif_1_wr_raw",
-                &format_args!("{}", self.core_1_area_pif_1_wr_raw().bit()),
-            )
-            .field(
-                "core_1_sp_spill_min_raw",
-                &format_args!("{}", self.core_1_sp_spill_min_raw().bit()),
-            )
-            .field(
-                "core_1_sp_spill_max_raw",
-                &format_args!("{}", self.core_1_sp_spill_max_raw().bit()),
+                &self.core_1_area_dram0_1_wr_raw(),
             )
+            .field("core_1_area_pif_0_rd_raw", &self.core_1_area_pif_0_rd_raw())
+            .field("core_1_area_pif_0_wr_raw", &self.core_1_area_pif_0_wr_raw())
+            .field("core_1_area_pif_1_rd_raw", &self.core_1_area_pif_1_rd_raw())
+            .field("core_1_area_pif_1_wr_raw", &self.core_1_area_pif_1_wr_raw())
+            .field("core_1_sp_spill_min_raw", &self.core_1_sp_spill_min_raw())
+            .field("core_1_sp_spill_max_raw", &self.core_1_sp_spill_max_raw())
             .field(
                 "core_1_iram0_exception_monitor_raw",
-                &format_args!("{}", self.core_1_iram0_exception_monitor_raw().bit()),
+                &self.core_1_iram0_exception_monitor_raw(),
             )
             .field(
                 "core_1_dram0_exception_monitor_raw",
-                &format_args!("{}", self.core_1_dram0_exception_monitor_raw().bit()),
+                &self.core_1_dram0_exception_monitor_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_INTR_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 monitor interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_intr_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_INTR_RAW_SPEC;
 impl crate::RegisterSpec for CORE_1_INTR_RAW_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_iram0_exception_monitor_0.rs b/esp32s3/src/assist_debug/core_1_iram0_exception_monitor_0.rs
index 3113dfa4dd..79e7b422e1 100644
--- a/esp32s3/src/assist_debug/core_1_iram0_exception_monitor_0.rs
+++ b/esp32s3/src/assist_debug/core_1_iram0_exception_monitor_0.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_IRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_1_iram0_recording_addr_0",
-                &format_args!("{}", self.core_1_iram0_recording_addr_0().bits()),
+                &self.core_1_iram0_recording_addr_0(),
             )
             .field(
                 "core_1_iram0_recording_wr_0",
-                &format_args!("{}", self.core_1_iram0_recording_wr_0().bit()),
+                &self.core_1_iram0_recording_wr_0(),
             )
             .field(
                 "core_1_iram0_recording_loadstore_0",
-                &format_args!("{}", self.core_1_iram0_recording_loadstore_0().bit()),
+                &self.core_1_iram0_recording_loadstore_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_iram0_exception_monitor_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC;
 impl crate::RegisterSpec for CORE_1_IRAM0_EXCEPTION_MONITOR_0_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_iram0_exception_monitor_1.rs b/esp32s3/src/assist_debug/core_1_iram0_exception_monitor_1.rs
index 8c51d7e18e..2da61eed07 100644
--- a/esp32s3/src/assist_debug/core_1_iram0_exception_monitor_1.rs
+++ b/esp32s3/src/assist_debug/core_1_iram0_exception_monitor_1.rs
@@ -29,25 +29,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_IRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_1_iram0_recording_addr_1",
-                &format_args!("{}", self.core_1_iram0_recording_addr_1().bits()),
+                &self.core_1_iram0_recording_addr_1(),
             )
             .field(
                 "core_1_iram0_recording_wr_1",
-                &format_args!("{}", self.core_1_iram0_recording_wr_1().bit()),
+                &self.core_1_iram0_recording_wr_1(),
             )
             .field(
                 "core_1_iram0_recording_loadstore_1",
-                &format_args!("{}", self.core_1_iram0_recording_loadstore_1().bit()),
+                &self.core_1_iram0_recording_loadstore_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 bus busy status regsiter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_iram0_exception_monitor_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC;
 impl crate::RegisterSpec for CORE_1_IRAM0_EXCEPTION_MONITOR_1_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_montr_ena.rs b/esp32s3/src/assist_debug/core_1_montr_ena.rs
index 266984ba16..1e48d16f6f 100644
--- a/esp32s3/src/assist_debug/core_1_montr_ena.rs
+++ b/esp32s3/src/assist_debug/core_1_montr_ena.rs
@@ -118,61 +118,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_MONTR_ENA")
             .field(
                 "core_1_area_dram0_0_rd_ena",
-                &format_args!("{}", self.core_1_area_dram0_0_rd_ena().bit()),
+                &self.core_1_area_dram0_0_rd_ena(),
             )
             .field(
                 "core_1_area_dram0_0_wr_ena",
-                &format_args!("{}", self.core_1_area_dram0_0_wr_ena().bit()),
+                &self.core_1_area_dram0_0_wr_ena(),
             )
             .field(
                 "core_1_area_dram0_1_rd_ena",
-                &format_args!("{}", self.core_1_area_dram0_1_rd_ena().bit()),
+                &self.core_1_area_dram0_1_rd_ena(),
             )
             .field(
                 "core_1_area_dram0_1_wr_ena",
-                &format_args!("{}", self.core_1_area_dram0_1_wr_ena().bit()),
-            )
-            .field(
-                "core_1_area_pif_0_rd_ena",
-                &format_args!("{}", self.core_1_area_pif_0_rd_ena().bit()),
-            )
-            .field(
-                "core_1_area_pif_0_wr_ena",
-                &format_args!("{}", self.core_1_area_pif_0_wr_ena().bit()),
-            )
-            .field(
-                "core_1_area_pif_1_rd_ena",
-                &format_args!("{}", self.core_1_area_pif_1_rd_ena().bit()),
-            )
-            .field(
-                "core_1_area_pif_1_wr_ena",
-                &format_args!("{}", self.core_1_area_pif_1_wr_ena().bit()),
-            )
-            .field(
-                "core_1_sp_spill_min_ena",
-                &format_args!("{}", self.core_1_sp_spill_min_ena().bit()),
-            )
-            .field(
-                "core_1_sp_spill_max_ena",
-                &format_args!("{}", self.core_1_sp_spill_max_ena().bit()),
+                &self.core_1_area_dram0_1_wr_ena(),
             )
+            .field("core_1_area_pif_0_rd_ena", &self.core_1_area_pif_0_rd_ena())
+            .field("core_1_area_pif_0_wr_ena", &self.core_1_area_pif_0_wr_ena())
+            .field("core_1_area_pif_1_rd_ena", &self.core_1_area_pif_1_rd_ena())
+            .field("core_1_area_pif_1_wr_ena", &self.core_1_area_pif_1_wr_ena())
+            .field("core_1_sp_spill_min_ena", &self.core_1_sp_spill_min_ena())
+            .field("core_1_sp_spill_max_ena", &self.core_1_sp_spill_max_ena())
             .field(
                 "core_1_iram0_exception_monitor_ena",
-                &format_args!("{}", self.core_1_iram0_exception_monitor_ena().bit()),
+                &self.core_1_iram0_exception_monitor_ena(),
             )
             .field(
                 "core_1_dram0_exception_monitor_ena",
-                &format_args!("{}", self.core_1_dram0_exception_monitor_ena().bit()),
+                &self.core_1_dram0_exception_monitor_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_MONTR_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core1 dram0 area0 read monitor enable"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_rcd_pdebugdata.rs b/esp32s3/src/assist_debug/core_1_rcd_pdebugdata.rs
index 2ddae79dab..a43a710e42 100644
--- a/esp32s3/src/assist_debug/core_1_rcd_pdebugdata.rs
+++ b/esp32s3/src/assist_debug/core_1_rcd_pdebugdata.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_RCD_PDEBUGDATA")
-            .field(
-                "core_1_rcd_pdebugdata",
-                &format_args!("{}", self.core_1_rcd_pdebugdata().bits()),
-            )
+            .field("core_1_rcd_pdebugdata", &self.core_1_rcd_pdebugdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_RCD_PDEBUGDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_pdebugdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_RCD_PDEBUGDATA_SPEC;
 impl crate::RegisterSpec for CORE_1_RCD_PDEBUGDATA_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_rcd_pdebugenable.rs b/esp32s3/src/assist_debug/core_1_rcd_pdebugenable.rs
index 4a1f79c7e9..a074aff49c 100644
--- a/esp32s3/src/assist_debug/core_1_rcd_pdebugenable.rs
+++ b/esp32s3/src/assist_debug/core_1_rcd_pdebugenable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_RCD_PDEBUGENABLE")
-            .field(
-                "core_1_rcd_pdebugenable",
-                &format_args!("{}", self.core_1_rcd_pdebugenable().bit()),
-            )
+            .field("core_1_rcd_pdebugenable", &self.core_1_rcd_pdebugenable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_RCD_PDEBUGENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Core1 Pdebugenable,set 1 to open Core1 Pdebug interface, then can get Core1 PC"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_rcd_pdebuginst.rs b/esp32s3/src/assist_debug/core_1_rcd_pdebuginst.rs
index 0a86f4f524..1c74c17016 100644
--- a/esp32s3/src/assist_debug/core_1_rcd_pdebuginst.rs
+++ b/esp32s3/src/assist_debug/core_1_rcd_pdebuginst.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_RCD_PDEBUGINST")
-            .field(
-                "core_1_rcd_pdebuginst",
-                &format_args!("{}", self.core_1_rcd_pdebuginst().bits()),
-            )
+            .field("core_1_rcd_pdebuginst", &self.core_1_rcd_pdebuginst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_RCD_PDEBUGINST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_pdebuginst::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_RCD_PDEBUGINST_SPEC;
 impl crate::RegisterSpec for CORE_1_RCD_PDEBUGINST_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_rcd_pdebugls0addr.rs b/esp32s3/src/assist_debug/core_1_rcd_pdebugls0addr.rs
index 237c285ff5..99b839935c 100644
--- a/esp32s3/src/assist_debug/core_1_rcd_pdebugls0addr.rs
+++ b/esp32s3/src/assist_debug/core_1_rcd_pdebugls0addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_RCD_PDEBUGLS0ADDR")
-            .field(
-                "core_1_rcd_pdebugls0addr",
-                &format_args!("{}", self.core_1_rcd_pdebugls0addr().bits()),
-            )
+            .field("core_1_rcd_pdebugls0addr", &self.core_1_rcd_pdebugls0addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_RCD_PDEBUGLS0ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_pdebugls0addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_RCD_PDEBUGLS0ADDR_SPEC;
 impl crate::RegisterSpec for CORE_1_RCD_PDEBUGLS0ADDR_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_rcd_pdebugls0data.rs b/esp32s3/src/assist_debug/core_1_rcd_pdebugls0data.rs
index 7a59f1b3c1..decfb2ed1c 100644
--- a/esp32s3/src/assist_debug/core_1_rcd_pdebugls0data.rs
+++ b/esp32s3/src/assist_debug/core_1_rcd_pdebugls0data.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_RCD_PDEBUGLS0DATA")
-            .field(
-                "core_1_rcd_pdebugls0data",
-                &format_args!("{}", self.core_1_rcd_pdebugls0data().bits()),
-            )
+            .field("core_1_rcd_pdebugls0data", &self.core_1_rcd_pdebugls0data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_RCD_PDEBUGLS0DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_pdebugls0data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_RCD_PDEBUGLS0DATA_SPEC;
 impl crate::RegisterSpec for CORE_1_RCD_PDEBUGLS0DATA_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_rcd_pdebugls0stat.rs b/esp32s3/src/assist_debug/core_1_rcd_pdebugls0stat.rs
index 8ccc48d09b..f5729916b0 100644
--- a/esp32s3/src/assist_debug/core_1_rcd_pdebugls0stat.rs
+++ b/esp32s3/src/assist_debug/core_1_rcd_pdebugls0stat.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_RCD_PDEBUGLS0STAT")
-            .field(
-                "core_1_rcd_pdebugls0stat",
-                &format_args!("{}", self.core_1_rcd_pdebugls0stat().bits()),
-            )
+            .field("core_1_rcd_pdebugls0stat", &self.core_1_rcd_pdebugls0stat())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_RCD_PDEBUGLS0STAT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_pdebugls0stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_RCD_PDEBUGLS0STAT_SPEC;
 impl crate::RegisterSpec for CORE_1_RCD_PDEBUGLS0STAT_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_rcd_pdebugpc.rs b/esp32s3/src/assist_debug/core_1_rcd_pdebugpc.rs
index 1d673a214e..de0b663049 100644
--- a/esp32s3/src/assist_debug/core_1_rcd_pdebugpc.rs
+++ b/esp32s3/src/assist_debug/core_1_rcd_pdebugpc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_RCD_PDEBUGPC")
-            .field(
-                "core_1_rcd_pdebugpc",
-                &format_args!("{}", self.core_1_rcd_pdebugpc().bits()),
-            )
+            .field("core_1_rcd_pdebugpc", &self.core_1_rcd_pdebugpc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_RCD_PDEBUGPC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_pdebugpc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_RCD_PDEBUGPC_SPEC;
 impl crate::RegisterSpec for CORE_1_RCD_PDEBUGPC_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_rcd_pdebugstatus.rs b/esp32s3/src/assist_debug/core_1_rcd_pdebugstatus.rs
index 82dddfd4d9..67fde2f095 100644
--- a/esp32s3/src/assist_debug/core_1_rcd_pdebugstatus.rs
+++ b/esp32s3/src/assist_debug/core_1_rcd_pdebugstatus.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_RCD_PDEBUGSTATUS")
-            .field(
-                "core_1_rcd_pdebugstatus",
-                &format_args!("{}", self.core_1_rcd_pdebugstatus().bits()),
-            )
+            .field("core_1_rcd_pdebugstatus", &self.core_1_rcd_pdebugstatus())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_RCD_PDEBUGSTATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_pdebugstatus::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_RCD_PDEBUGSTATUS_SPEC;
 impl crate::RegisterSpec for CORE_1_RCD_PDEBUGSTATUS_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_rcd_recording.rs b/esp32s3/src/assist_debug/core_1_rcd_recording.rs
index b5137e54e9..369c40913e 100644
--- a/esp32s3/src/assist_debug/core_1_rcd_recording.rs
+++ b/esp32s3/src/assist_debug/core_1_rcd_recording.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_RCD_RECORDING")
-            .field(
-                "core_1_rcd_recording",
-                &format_args!("{}", self.core_1_rcd_recording().bit()),
-            )
+            .field("core_1_rcd_recording", &self.core_1_rcd_recording())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_RCD_RECORDING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Pdebug record enable,set 1 to record Core1 pdebug interface signal"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_rcd_sp.rs b/esp32s3/src/assist_debug/core_1_rcd_sp.rs
index 6eeea42dfc..fa9a2f3416 100644
--- a/esp32s3/src/assist_debug/core_1_rcd_sp.rs
+++ b/esp32s3/src/assist_debug/core_1_rcd_sp.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_RCD_SP")
-            .field(
-                "core_1_rcd_sp",
-                &format_args!("{}", self.core_1_rcd_sp().bits()),
-            )
+            .field("core_1_rcd_sp", &self.core_1_rcd_sp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_RCD_SP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 pdebug status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_rcd_sp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_RCD_SP_SPEC;
 impl crate::RegisterSpec for CORE_1_RCD_SP_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_sp_max.rs b/esp32s3/src/assist_debug/core_1_sp_max.rs
index f0a3fcf7db..a05c71577c 100644
--- a/esp32s3/src/assist_debug/core_1_sp_max.rs
+++ b/esp32s3/src/assist_debug/core_1_sp_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_SP_MAX")
-            .field(
-                "core_1_sp_max",
-                &format_args!("{}", self.core_1_sp_max().bits()),
-            )
+            .field("core_1_sp_max", &self.core_1_sp_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_SP_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - stack max value"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_sp_min.rs b/esp32s3/src/assist_debug/core_1_sp_min.rs
index c201bdd670..50a850a292 100644
--- a/esp32s3/src/assist_debug/core_1_sp_min.rs
+++ b/esp32s3/src/assist_debug/core_1_sp_min.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_SP_MIN")
-            .field(
-                "core_1_sp_min",
-                &format_args!("{}", self.core_1_sp_min().bits()),
-            )
+            .field("core_1_sp_min", &self.core_1_sp_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_SP_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - stack min value"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_1_sp_pc.rs b/esp32s3/src/assist_debug/core_1_sp_pc.rs
index 101a503be3..55c812d293 100644
--- a/esp32s3/src/assist_debug/core_1_sp_pc.rs
+++ b/esp32s3/src/assist_debug/core_1_sp_pc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_SP_PC")
-            .field(
-                "core_1_sp_pc",
-                &format_args!("{}", self.core_1_sp_pc().bits()),
-            )
+            .field("core_1_sp_pc", &self.core_1_sp_pc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_SP_PC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core1 sp pc status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_sp_pc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_SP_PC_SPEC;
 impl crate::RegisterSpec for CORE_1_SP_PC_SPEC {
diff --git a/esp32s3/src/assist_debug/core_1_sp_unstable.rs b/esp32s3/src/assist_debug/core_1_sp_unstable.rs
index bb9de21c6e..307060e3ea 100644
--- a/esp32s3/src/assist_debug/core_1_sp_unstable.rs
+++ b/esp32s3/src/assist_debug/core_1_sp_unstable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_SP_UNSTABLE")
-            .field(
-                "core_1_sp_unstable",
-                &format_args!("{}", self.core_1_sp_unstable().bits()),
-            )
+            .field("core_1_sp_unstable", &self.core_1_sp_unstable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_SP_UNSTABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - unstable period when window change,during this period no check stackpointer"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs b/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
index 2871e47a0b..0f1fd42885 100644
--- a/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
+++ b/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0")
             .field(
                 "core_x_iram0_dram0_limit_cycle_0",
-                &format_args!("{}", self.core_x_iram0_dram0_limit_cycle_0().bits()),
+                &self.core_x_iram0_dram0_limit_cycle_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - busy monitor window cycle"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs b/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
index b4fc1e379d..c8fff0e565 100644
--- a/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
+++ b/esp32s3/src/assist_debug/core_x_iram0_dram0_exception_monitor_1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1")
             .field(
                 "core_x_iram0_dram0_limit_cycle_1",
-                &format_args!("{}", self.core_x_iram0_dram0_limit_cycle_1().bits()),
+                &self.core_x_iram0_dram0_limit_cycle_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - non busy cycle,for example: when cycle=100 and cycle=10,it means that in 100 cycle, if busy access success time less than 10, it will trigger interrutpt"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/date.rs b/esp32s3/src/assist_debug/date.rs
index c90fb1c635..991d720cae 100644
--- a/esp32s3/src/assist_debug/date.rs
+++ b/esp32s3/src/assist_debug/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/assist_debug/log_data_0.rs b/esp32s3/src/assist_debug/log_data_0.rs
index 2ef79de1be..056294b8e6 100644
--- a/esp32s3/src/assist_debug/log_data_0.rs
+++ b/esp32s3/src/assist_debug/log_data_0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_DATA_0")
-            .field("log_data_0", &format_args!("{}", self.log_data_0().bits()))
+            .field("log_data_0", &self.log_data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_DATA_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - check data0"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/log_data_1.rs b/esp32s3/src/assist_debug/log_data_1.rs
index 4537c0067e..0f7782197b 100644
--- a/esp32s3/src/assist_debug/log_data_1.rs
+++ b/esp32s3/src/assist_debug/log_data_1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_DATA_1")
-            .field("log_data_1", &format_args!("{}", self.log_data_1().bits()))
+            .field("log_data_1", &self.log_data_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_DATA_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - check data1"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/log_data_2.rs b/esp32s3/src/assist_debug/log_data_2.rs
index f422211180..1275fb39a2 100644
--- a/esp32s3/src/assist_debug/log_data_2.rs
+++ b/esp32s3/src/assist_debug/log_data_2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_DATA_2")
-            .field("log_data_2", &format_args!("{}", self.log_data_2().bits()))
+            .field("log_data_2", &self.log_data_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_DATA_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - check data2"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/log_data_3.rs b/esp32s3/src/assist_debug/log_data_3.rs
index 1fb23becc4..2ce35b1f3e 100644
--- a/esp32s3/src/assist_debug/log_data_3.rs
+++ b/esp32s3/src/assist_debug/log_data_3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_DATA_3")
-            .field("log_data_3", &format_args!("{}", self.log_data_3().bits()))
+            .field("log_data_3", &self.log_data_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_DATA_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - check data3"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/log_data_mask.rs b/esp32s3/src/assist_debug/log_data_mask.rs
index 62806d3eeb..a9753e8498 100644
--- a/esp32s3/src/assist_debug/log_data_mask.rs
+++ b/esp32s3/src/assist_debug/log_data_mask.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_DATA_MASK")
-            .field(
-                "log_data_size",
-                &format_args!("{}", self.log_data_size().bits()),
-            )
+            .field("log_data_size", &self.log_data_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_DATA_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - data mask"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/log_max.rs b/esp32s3/src/assist_debug/log_max.rs
index f2c1efa3e1..284546df1c 100644
--- a/esp32s3/src/assist_debug/log_max.rs
+++ b/esp32s3/src/assist_debug/log_max.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MAX")
-            .field("log_max", &format_args!("{}", self.log_max().bits()))
+            .field("log_max", &self.log_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - check region max addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/log_mem_end.rs b/esp32s3/src/assist_debug/log_mem_end.rs
index c81a790783..0105ccb691 100644
--- a/esp32s3/src/assist_debug/log_mem_end.rs
+++ b/esp32s3/src/assist_debug/log_mem_end.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_END")
-            .field(
-                "log_mem_end",
-                &format_args!("{}", self.log_mem_end().bits()),
-            )
+            .field("log_mem_end", &self.log_mem_end())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_END_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - mem end addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/log_mem_full_flag.rs b/esp32s3/src/assist_debug/log_mem_full_flag.rs
index 5ffe879ac1..19d934d3b9 100644
--- a/esp32s3/src/assist_debug/log_mem_full_flag.rs
+++ b/esp32s3/src/assist_debug/log_mem_full_flag.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_FULL_FLAG")
-            .field(
-                "log_mem_full_flag",
-                &format_args!("{}", self.log_mem_full_flag().bit()),
-            )
+            .field("log_mem_full_flag", &self.log_mem_full_flag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_FULL_FLAG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - when it's 1,show that mem write loop morte than one time."]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/log_mem_start.rs b/esp32s3/src/assist_debug/log_mem_start.rs
index 2f4e6049d1..4935830f39 100644
--- a/esp32s3/src/assist_debug/log_mem_start.rs
+++ b/esp32s3/src/assist_debug/log_mem_start.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_START")
-            .field(
-                "log_mem_start",
-                &format_args!("{}", self.log_mem_start().bits()),
-            )
+            .field("log_mem_start", &self.log_mem_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_START_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - mem start addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/log_mem_writing_addr.rs b/esp32s3/src/assist_debug/log_mem_writing_addr.rs
index f3c74dfa53..693ff187c3 100644
--- a/esp32s3/src/assist_debug/log_mem_writing_addr.rs
+++ b/esp32s3/src/assist_debug/log_mem_writing_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MEM_WRITING_ADDR")
-            .field(
-                "log_mem_writing_addr",
-                &format_args!("{}", self.log_mem_writing_addr().bits()),
-            )
+            .field("log_mem_writing_addr", &self.log_mem_writing_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MEM_WRITING_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "log mem addr status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`log_mem_writing_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOG_MEM_WRITING_ADDR_SPEC;
 impl crate::RegisterSpec for LOG_MEM_WRITING_ADDR_SPEC {
diff --git a/esp32s3/src/assist_debug/log_min.rs b/esp32s3/src/assist_debug/log_min.rs
index b702b3a1c7..764138c3a7 100644
--- a/esp32s3/src/assist_debug/log_min.rs
+++ b/esp32s3/src/assist_debug/log_min.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_MIN")
-            .field("log_min", &format_args!("{}", self.log_min().bits()))
+            .field("log_min", &self.log_min())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_MIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - check region min addr"]
     #[inline(always)]
diff --git a/esp32s3/src/assist_debug/log_setting.rs b/esp32s3/src/assist_debug/log_setting.rs
index f127bc7d1c..5611703a09 100644
--- a/esp32s3/src/assist_debug/log_setting.rs
+++ b/esp32s3/src/assist_debug/log_setting.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOG_SETTING")
-            .field("log_ena", &format_args!("{}", self.log_ena().bits()))
-            .field("log_mode", &format_args!("{}", self.log_mode().bits()))
-            .field(
-                "log_mem_loop_enable",
-                &format_args!("{}", self.log_mem_loop_enable().bit()),
-            )
+            .field("log_ena", &self.log_ena())
+            .field("log_mode", &self.log_mode())
+            .field("log_mem_loop_enable", &self.log_mem_loop_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOG_SETTING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - bus moniter enable: \\[0\\]Core1,\\[1\\]core1,\\[2\\]dma"]
     #[inline(always)]
diff --git a/esp32s3/src/bb/bbpd_ctrl.rs b/esp32s3/src/bb/bbpd_ctrl.rs
index 7e31e667bb..28cf2656e4 100644
--- a/esp32s3/src/bb/bbpd_ctrl.rs
+++ b/esp32s3/src/bb/bbpd_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BBPD_CTRL")
-            .field(
-                "dc_est_force_pd",
-                &format_args!("{}", self.dc_est_force_pd().bit()),
-            )
-            .field(
-                "dc_est_force_pu",
-                &format_args!("{}", self.dc_est_force_pu().bit()),
-            )
-            .field(
-                "fft_force_pd",
-                &format_args!("{}", self.fft_force_pd().bit()),
-            )
-            .field(
-                "fft_force_pu",
-                &format_args!("{}", self.fft_force_pu().bit()),
-            )
+            .field("dc_est_force_pd", &self.dc_est_force_pd())
+            .field("dc_est_force_pu", &self.dc_est_force_pu())
+            .field("fft_force_pd", &self.fft_force_pd())
+            .field("fft_force_pu", &self.fft_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BBPD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ahb_test.rs b/esp32s3/src/dma/ahb_test.rs
index 28c330c261..8358a35c42 100644
--- a/esp32s3/src/dma/ahb_test.rs
+++ b/esp32s3/src/dma/ahb_test.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AHB_TEST")
-            .field(
-                "ahb_testmode",
-                &format_args!("{}", self.ahb_testmode().bits()),
-            )
-            .field(
-                "ahb_testaddr",
-                &format_args!("{}", self.ahb_testaddr().bits()),
-            )
+            .field("ahb_testmode", &self.ahb_testmode())
+            .field("ahb_testaddr", &self.ahb_testaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AHB_TEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - reserved"]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/in_conf0.rs b/esp32s3/src/dma/ch/in_conf0.rs
index e536d9cac9..b7b18c5989 100644
--- a/esp32s3/src/dma/ch/in_conf0.rs
+++ b/esp32s3/src/dma/ch/in_conf0.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF0")
-            .field("in_rst", &format_args!("{}", self.in_rst().bit()))
-            .field(
-                "in_loop_test",
-                &format_args!("{}", self.in_loop_test().bit()),
-            )
-            .field(
-                "indscr_burst_en",
-                &format_args!("{}", self.indscr_burst_en().bit()),
-            )
-            .field(
-                "in_data_burst_en",
-                &format_args!("{}", self.in_data_burst_en().bit()),
-            )
-            .field(
-                "mem_trans_en",
-                &format_args!("{}", self.mem_trans_en().bit()),
-            )
+            .field("in_rst", &self.in_rst())
+            .field("in_loop_test", &self.in_loop_test())
+            .field("indscr_burst_en", &self.indscr_burst_en())
+            .field("in_data_burst_en", &self.in_data_burst_en())
+            .field("mem_trans_en", &self.mem_trans_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/in_conf1.rs b/esp32s3/src/dma/ch/in_conf1.rs
index 676b10c817..3b4a28121c 100644
--- a/esp32s3/src/dma/ch/in_conf1.rs
+++ b/esp32s3/src/dma/ch/in_conf1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_CONF1")
-            .field(
-                "dma_infifo_full_thrs",
-                &format_args!("{}", self.dma_infifo_full_thrs().bits()),
-            )
-            .field(
-                "in_check_owner",
-                &format_args!("{}", self.in_check_owner().bit()),
-            )
-            .field(
-                "in_ext_mem_bk_size",
-                &format_args!("{}", self.in_ext_mem_bk_size().bits()),
-            )
+            .field("dma_infifo_full_thrs", &self.dma_infifo_full_thrs())
+            .field("in_check_owner", &self.in_check_owner())
+            .field("in_ext_mem_bk_size", &self.in_ext_mem_bk_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/in_dscr.rs b/esp32s3/src/dma/ch/in_dscr.rs
index 3d348a76f4..e70d15df66 100644
--- a/esp32s3/src/dma/ch/in_dscr.rs
+++ b/esp32s3/src/dma/ch/in_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR")
-            .field(
-                "inlink_dscr",
-                &format_args!("{}", self.inlink_dscr().bits()),
-            )
+            .field("inlink_dscr", &self.inlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_SPEC;
 impl crate::RegisterSpec for IN_DSCR_SPEC {
diff --git a/esp32s3/src/dma/ch/in_dscr_bf0.rs b/esp32s3/src/dma/ch/in_dscr_bf0.rs
index e3023e2221..fca80e02f8 100644
--- a/esp32s3/src/dma/ch/in_dscr_bf0.rs
+++ b/esp32s3/src/dma/ch/in_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF0")
-            .field(
-                "inlink_dscr_bf0",
-                &format_args!("{}", self.inlink_dscr_bf0().bits()),
-            )
+            .field("inlink_dscr_bf0", &self.inlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for IN_DSCR_BF0_SPEC {
diff --git a/esp32s3/src/dma/ch/in_dscr_bf1.rs b/esp32s3/src/dma/ch/in_dscr_bf1.rs
index 457ee1455f..832bf9b92c 100644
--- a/esp32s3/src/dma/ch/in_dscr_bf1.rs
+++ b/esp32s3/src/dma/ch/in_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_DSCR_BF1")
-            .field(
-                "inlink_dscr_bf1",
-                &format_args!("{}", self.inlink_dscr_bf1().bits()),
-            )
+            .field("inlink_dscr_bf1", &self.inlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The second-to-last inlink descriptor address of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for IN_DSCR_BF1_SPEC {
diff --git a/esp32s3/src/dma/ch/in_err_eof_des_addr.rs b/esp32s3/src/dma/ch/in_err_eof_des_addr.rs
index 037171f572..63b8c75ca0 100644
--- a/esp32s3/src/dma/ch/in_err_eof_des_addr.rs
+++ b/esp32s3/src/dma/ch/in_err_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_ERR_EOF_DES_ADDR")
-            .field(
-                "in_err_eof_des_addr",
-                &format_args!("{}", self.in_err_eof_des_addr().bits()),
-            )
+            .field("in_err_eof_des_addr", &self.in_err_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_ERR_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Inlink descriptor address when errors occur of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_err_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_ERR_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_ERR_EOF_DES_ADDR_SPEC {
diff --git a/esp32s3/src/dma/ch/in_int/ena.rs b/esp32s3/src/dma/ch/in_int/ena.rs
index d3a9e75142..1db0027090 100644
--- a/esp32s3/src/dma/ch/in_int/ena.rs
+++ b/esp32s3/src/dma/ch/in_int/ena.rs
@@ -98,43 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENA")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "infifo_full_wm",
-                &format_args!("{}", self.infifo_full_wm().bit()),
-            )
-            .field(
-                "infifo_ovf_l1",
-                &format_args!("{}", self.infifo_ovf_l1().bit()),
-            )
-            .field(
-                "infifo_udf_l1",
-                &format_args!("{}", self.infifo_udf_l1().bit()),
-            )
-            .field(
-                "infifo_ovf_l3",
-                &format_args!("{}", self.infifo_ovf_l3().bit()),
-            )
-            .field(
-                "infifo_udf_l3",
-                &format_args!("{}", self.infifo_udf_l3().bit()),
-            )
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_full_wm", &self.infifo_full_wm())
+            .field("infifo_ovf_l1", &self.infifo_ovf_l1())
+            .field("infifo_udf_l1", &self.infifo_udf_l1())
+            .field("infifo_ovf_l3", &self.infifo_ovf_l3())
+            .field("infifo_udf_l3", &self.infifo_udf_l3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the IN_DONE_CH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/in_int/raw.rs b/esp32s3/src/dma/ch/in_int/raw.rs
index d8e87548ec..61940b6ebe 100644
--- a/esp32s3/src/dma/ch/in_int/raw.rs
+++ b/esp32s3/src/dma/ch/in_int/raw.rs
@@ -98,43 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RAW")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "infifo_full_wm",
-                &format_args!("{}", self.infifo_full_wm().bit()),
-            )
-            .field(
-                "infifo_ovf_l1",
-                &format_args!("{}", self.infifo_ovf_l1().bit()),
-            )
-            .field(
-                "infifo_udf_l1",
-                &format_args!("{}", self.infifo_udf_l1().bit()),
-            )
-            .field(
-                "infifo_ovf_l3",
-                &format_args!("{}", self.infifo_ovf_l3().bit()),
-            )
-            .field(
-                "infifo_udf_l3",
-                &format_args!("{}", self.infifo_udf_l3().bit()),
-            )
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_full_wm", &self.infifo_full_wm())
+            .field("infifo_ovf_l1", &self.infifo_ovf_l1())
+            .field("infifo_udf_l1", &self.infifo_udf_l1())
+            .field("infifo_ovf_l3", &self.infifo_ovf_l3())
+            .field("infifo_udf_l3", &self.infifo_udf_l3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/in_int/st.rs b/esp32s3/src/dma/ch/in_int/st.rs
index 12439301e1..aff9028820 100644
--- a/esp32s3/src/dma/ch/in_int/st.rs
+++ b/esp32s3/src/dma/ch/in_int/st.rs
@@ -76,43 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ST")
-            .field("in_done", &format_args!("{}", self.in_done().bit()))
-            .field("in_suc_eof", &format_args!("{}", self.in_suc_eof().bit()))
-            .field("in_err_eof", &format_args!("{}", self.in_err_eof().bit()))
-            .field("in_dscr_err", &format_args!("{}", self.in_dscr_err().bit()))
-            .field(
-                "in_dscr_empty",
-                &format_args!("{}", self.in_dscr_empty().bit()),
-            )
-            .field(
-                "infifo_full_wm",
-                &format_args!("{}", self.infifo_full_wm().bit()),
-            )
-            .field(
-                "infifo_ovf_l1",
-                &format_args!("{}", self.infifo_ovf_l1().bit()),
-            )
-            .field(
-                "infifo_udf_l1",
-                &format_args!("{}", self.infifo_udf_l1().bit()),
-            )
-            .field(
-                "infifo_ovf_l3",
-                &format_args!("{}", self.infifo_ovf_l3().bit()),
-            )
-            .field(
-                "infifo_udf_l3",
-                &format_args!("{}", self.infifo_udf_l3().bit()),
-            )
+            .field("in_done", &self.in_done())
+            .field("in_suc_eof", &self.in_suc_eof())
+            .field("in_err_eof", &self.in_err_eof())
+            .field("in_dscr_err", &self.in_dscr_err())
+            .field("in_dscr_empty", &self.in_dscr_empty())
+            .field("infifo_full_wm", &self.infifo_full_wm())
+            .field("infifo_ovf_l1", &self.infifo_ovf_l1())
+            .field("infifo_udf_l1", &self.infifo_udf_l1())
+            .field("infifo_ovf_l3", &self.infifo_ovf_l3())
+            .field("infifo_udf_l3", &self.infifo_udf_l3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ST_SPEC;
 impl crate::RegisterSpec for ST_SPEC {
diff --git a/esp32s3/src/dma/ch/in_link.rs b/esp32s3/src/dma/ch/in_link.rs
index 6f75006dbe..9ed81799cc 100644
--- a/esp32s3/src/dma/ch/in_link.rs
+++ b/esp32s3/src/dma/ch/in_link.rs
@@ -60,33 +60,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_LINK")
-            .field(
-                "inlink_addr",
-                &format_args!("{}", self.inlink_addr().bits()),
-            )
-            .field(
-                "inlink_auto_ret",
-                &format_args!("{}", self.inlink_auto_ret().bit()),
-            )
-            .field("inlink_stop", &format_args!("{}", self.inlink_stop().bit()))
-            .field(
-                "inlink_start",
-                &format_args!("{}", self.inlink_start().bit()),
-            )
-            .field(
-                "inlink_restart",
-                &format_args!("{}", self.inlink_restart().bit()),
-            )
-            .field("inlink_park", &format_args!("{}", self.inlink_park().bit()))
+            .field("inlink_addr", &self.inlink_addr())
+            .field("inlink_auto_ret", &self.inlink_auto_ret())
+            .field("inlink_stop", &self.inlink_stop())
+            .field("inlink_start", &self.inlink_start())
+            .field("inlink_restart", &self.inlink_restart())
+            .field("inlink_park", &self.inlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first inlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/in_peri_sel.rs b/esp32s3/src/dma/ch/in_peri_sel.rs
index ebac7a2518..2c7636c7cf 100644
--- a/esp32s3/src/dma/ch/in_peri_sel.rs
+++ b/esp32s3/src/dma/ch/in_peri_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_PERI_SEL")
-            .field(
-                "peri_in_sel",
-                &format_args!("{}", self.peri_in_sel().bits()),
-            )
+            .field("peri_in_sel", &self.peri_in_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_PERI_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/in_pop.rs b/esp32s3/src/dma/ch/in_pop.rs
index 225736273a..a2e3606f49 100644
--- a/esp32s3/src/dma/ch/in_pop.rs
+++ b/esp32s3/src/dma/ch/in_pop.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_POP")
-            .field(
-                "infifo_rdata",
-                &format_args!("{}", self.infifo_rdata().bits()),
-            )
-            .field("infifo_pop", &format_args!("{}", self.infifo_pop().bit()))
+            .field("infifo_rdata", &self.infifo_rdata())
+            .field("infifo_pop", &self.infifo_pop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_POP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to pop data from DMA FIFO."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/in_pri.rs b/esp32s3/src/dma/ch/in_pri.rs
index 87434befce..821be36597 100644
--- a/esp32s3/src/dma/ch/in_pri.rs
+++ b/esp32s3/src/dma/ch/in_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_PRI")
-            .field("rx_pri", &format_args!("{}", self.rx_pri().bits()))
+            .field("rx_pri", &self.rx_pri())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The priority of Rx channel 0. The larger of the value, the higher of the priority."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/in_state.rs b/esp32s3/src/dma/ch/in_state.rs
index 6c91ac50d7..83cb3124d8 100644
--- a/esp32s3/src/dma/ch/in_state.rs
+++ b/esp32s3/src/dma/ch/in_state.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_STATE")
-            .field(
-                "inlink_dscr_addr",
-                &format_args!("{}", self.inlink_dscr_addr().bits()),
-            )
-            .field(
-                "in_dscr_state",
-                &format_args!("{}", self.in_dscr_state().bits()),
-            )
-            .field("in_state", &format_args!("{}", self.in_state().bits()))
+            .field("inlink_dscr_addr", &self.inlink_dscr_addr())
+            .field("in_dscr_state", &self.in_dscr_state())
+            .field("in_state", &self.in_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_STATE_SPEC;
 impl crate::RegisterSpec for IN_STATE_SPEC {
diff --git a/esp32s3/src/dma/ch/in_suc_eof_des_addr.rs b/esp32s3/src/dma/ch/in_suc_eof_des_addr.rs
index 2b0b4e378a..bd974ca71c 100644
--- a/esp32s3/src/dma/ch/in_suc_eof_des_addr.rs
+++ b/esp32s3/src/dma/ch/in_suc_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_SUC_EOF_DES_ADDR")
-            .field(
-                "in_suc_eof_des_addr",
-                &format_args!("{}", self.in_suc_eof_des_addr().bits()),
-            )
+            .field("in_suc_eof_des_addr", &self.in_suc_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SUC_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Inlink descriptor address when EOF occurs of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_suc_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_SUC_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for IN_SUC_EOF_DES_ADDR_SPEC {
diff --git a/esp32s3/src/dma/ch/in_wight.rs b/esp32s3/src/dma/ch/in_wight.rs
index ab4273de0e..6c1a549164 100644
--- a/esp32s3/src/dma/ch/in_wight.rs
+++ b/esp32s3/src/dma/ch/in_wight.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_WIGHT")
-            .field("rx_weight", &format_args!("{}", self.rx_weight().bits()))
+            .field("rx_weight", &self.rx_weight())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_WIGHT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:11 - The weight of Rx channel 0."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/infifo_status.rs b/esp32s3/src/dma/ch/infifo_status.rs
index 713c386410..1e82355d03 100644
--- a/esp32s3/src/dma/ch/infifo_status.rs
+++ b/esp32s3/src/dma/ch/infifo_status.rs
@@ -104,71 +104,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INFIFO_STATUS")
-            .field(
-                "infifo_full_l1",
-                &format_args!("{}", self.infifo_full_l1().bit()),
-            )
-            .field(
-                "infifo_empty_l1",
-                &format_args!("{}", self.infifo_empty_l1().bit()),
-            )
-            .field(
-                "infifo_full_l2",
-                &format_args!("{}", self.infifo_full_l2().bit()),
-            )
-            .field(
-                "infifo_empty_l2",
-                &format_args!("{}", self.infifo_empty_l2().bit()),
-            )
-            .field(
-                "infifo_full_l3",
-                &format_args!("{}", self.infifo_full_l3().bit()),
-            )
-            .field(
-                "infifo_empty_l3",
-                &format_args!("{}", self.infifo_empty_l3().bit()),
-            )
-            .field(
-                "infifo_cnt_l1",
-                &format_args!("{}", self.infifo_cnt_l1().bits()),
-            )
-            .field(
-                "infifo_cnt_l2",
-                &format_args!("{}", self.infifo_cnt_l2().bits()),
-            )
-            .field(
-                "infifo_cnt_l3",
-                &format_args!("{}", self.infifo_cnt_l3().bits()),
-            )
-            .field(
-                "in_remain_under_1b_l3",
-                &format_args!("{}", self.in_remain_under_1b_l3().bit()),
-            )
-            .field(
-                "in_remain_under_2b_l3",
-                &format_args!("{}", self.in_remain_under_2b_l3().bit()),
-            )
-            .field(
-                "in_remain_under_3b_l3",
-                &format_args!("{}", self.in_remain_under_3b_l3().bit()),
-            )
-            .field(
-                "in_remain_under_4b_l3",
-                &format_args!("{}", self.in_remain_under_4b_l3().bit()),
-            )
-            .field(
-                "in_buf_hungry",
-                &format_args!("{}", self.in_buf_hungry().bit()),
-            )
+            .field("infifo_full_l1", &self.infifo_full_l1())
+            .field("infifo_empty_l1", &self.infifo_empty_l1())
+            .field("infifo_full_l2", &self.infifo_full_l2())
+            .field("infifo_empty_l2", &self.infifo_empty_l2())
+            .field("infifo_full_l3", &self.infifo_full_l3())
+            .field("infifo_empty_l3", &self.infifo_empty_l3())
+            .field("infifo_cnt_l1", &self.infifo_cnt_l1())
+            .field("infifo_cnt_l2", &self.infifo_cnt_l2())
+            .field("infifo_cnt_l3", &self.infifo_cnt_l3())
+            .field("in_remain_under_1b_l3", &self.in_remain_under_1b_l3())
+            .field("in_remain_under_2b_l3", &self.in_remain_under_2b_l3())
+            .field("in_remain_under_3b_l3", &self.in_remain_under_3b_l3())
+            .field("in_remain_under_4b_l3", &self.in_remain_under_4b_l3())
+            .field("in_buf_hungry", &self.in_buf_hungry())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive FIFO status of Rx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`infifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for INFIFO_STATUS_SPEC {
diff --git a/esp32s3/src/dma/ch/out_conf0.rs b/esp32s3/src/dma/ch/out_conf0.rs
index 1cd569ef36..b922933649 100644
--- a/esp32s3/src/dma/ch/out_conf0.rs
+++ b/esp32s3/src/dma/ch/out_conf0.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CONF0")
-            .field("out_rst", &format_args!("{}", self.out_rst().bit()))
-            .field(
-                "out_loop_test",
-                &format_args!("{}", self.out_loop_test().bit()),
-            )
-            .field(
-                "out_auto_wrback",
-                &format_args!("{}", self.out_auto_wrback().bit()),
-            )
-            .field(
-                "out_eof_mode",
-                &format_args!("{}", self.out_eof_mode().bit()),
-            )
-            .field(
-                "outdscr_burst_en",
-                &format_args!("{}", self.outdscr_burst_en().bit()),
-            )
-            .field(
-                "out_data_burst_en",
-                &format_args!("{}", self.out_data_burst_en().bit()),
-            )
+            .field("out_rst", &self.out_rst())
+            .field("out_loop_test", &self.out_loop_test())
+            .field("out_auto_wrback", &self.out_auto_wrback())
+            .field("out_eof_mode", &self.out_eof_mode())
+            .field("outdscr_burst_en", &self.outdscr_burst_en())
+            .field("out_data_burst_en", &self.out_data_burst_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/out_conf1.rs b/esp32s3/src/dma/ch/out_conf1.rs
index 9bbfe91bd5..56db2dd8a7 100644
--- a/esp32s3/src/dma/ch/out_conf1.rs
+++ b/esp32s3/src/dma/ch/out_conf1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_CONF1")
-            .field(
-                "out_check_owner",
-                &format_args!("{}", self.out_check_owner().bit()),
-            )
-            .field(
-                "out_ext_mem_bk_size",
-                &format_args!("{}", self.out_ext_mem_bk_size().bits()),
-            )
+            .field("out_check_owner", &self.out_check_owner())
+            .field("out_ext_mem_bk_size", &self.out_ext_mem_bk_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Set this bit to enable checking the owner attribute of the link descriptor."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/out_dscr.rs b/esp32s3/src/dma/ch/out_dscr.rs
index bfbfd6cd82..e64e982337 100644
--- a/esp32s3/src/dma/ch/out_dscr.rs
+++ b/esp32s3/src/dma/ch/out_dscr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR")
-            .field(
-                "outlink_dscr",
-                &format_args!("{}", self.outlink_dscr().bits()),
-            )
+            .field("outlink_dscr", &self.outlink_dscr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_SPEC {
diff --git a/esp32s3/src/dma/ch/out_dscr_bf0.rs b/esp32s3/src/dma/ch/out_dscr_bf0.rs
index 95ef8f687e..f5fec0ba50 100644
--- a/esp32s3/src/dma/ch/out_dscr_bf0.rs
+++ b/esp32s3/src/dma/ch/out_dscr_bf0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR_BF0")
-            .field(
-                "outlink_dscr_bf0",
-                &format_args!("{}", self.outlink_dscr_bf0().bits()),
-            )
+            .field("outlink_dscr_bf0", &self.outlink_dscr_bf0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_BF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_BF0_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_BF0_SPEC {
diff --git a/esp32s3/src/dma/ch/out_dscr_bf1.rs b/esp32s3/src/dma/ch/out_dscr_bf1.rs
index f75439c16c..4339b9c9b9 100644
--- a/esp32s3/src/dma/ch/out_dscr_bf1.rs
+++ b/esp32s3/src/dma/ch/out_dscr_bf1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_DSCR_BF1")
-            .field(
-                "outlink_dscr_bf1",
-                &format_args!("{}", self.outlink_dscr_bf1().bits()),
-            )
+            .field("outlink_dscr_bf1", &self.outlink_dscr_bf1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_DSCR_BF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The second-to-last inlink descriptor address of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_dscr_bf1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_DSCR_BF1_SPEC;
 impl crate::RegisterSpec for OUT_DSCR_BF1_SPEC {
diff --git a/esp32s3/src/dma/ch/out_eof_bfr_des_addr.rs b/esp32s3/src/dma/ch/out_eof_bfr_des_addr.rs
index 32fea6abcc..08cac753ad 100644
--- a/esp32s3/src/dma/ch/out_eof_bfr_des_addr.rs
+++ b/esp32s3/src/dma/ch/out_eof_bfr_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_BFR_DES_ADDR")
-            .field(
-                "out_eof_bfr_des_addr",
-                &format_args!("{}", self.out_eof_bfr_des_addr().bits()),
-            )
+            .field("out_eof_bfr_des_addr", &self.out_eof_bfr_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_BFR_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "The last outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_bfr_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_BFR_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_BFR_DES_ADDR_SPEC {
diff --git a/esp32s3/src/dma/ch/out_eof_des_addr.rs b/esp32s3/src/dma/ch/out_eof_des_addr.rs
index b85ba2ebbd..1049f7aa97 100644
--- a/esp32s3/src/dma/ch/out_eof_des_addr.rs
+++ b/esp32s3/src/dma/ch/out_eof_des_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EOF_DES_ADDR")
-            .field(
-                "out_eof_des_addr",
-                &format_args!("{}", self.out_eof_des_addr().bits()),
-            )
+            .field("out_eof_des_addr", &self.out_eof_des_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EOF_DES_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Outlink descriptor address when EOF occurs of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_eof_des_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EOF_DES_ADDR_SPEC;
 impl crate::RegisterSpec for OUT_EOF_DES_ADDR_SPEC {
diff --git a/esp32s3/src/dma/ch/out_int/ena.rs b/esp32s3/src/dma/ch/out_int/ena.rs
index bead215c0a..008bfbb5df 100644
--- a/esp32s3/src/dma/ch/out_int/ena.rs
+++ b/esp32s3/src/dma/ch/out_int/ena.rs
@@ -80,41 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENA")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field(
-                "outfifo_ovf_l1",
-                &format_args!("{}", self.outfifo_ovf_l1().bit()),
-            )
-            .field(
-                "outfifo_udf_l1",
-                &format_args!("{}", self.outfifo_udf_l1().bit()),
-            )
-            .field(
-                "outfifo_ovf_l3",
-                &format_args!("{}", self.outfifo_ovf_l3().bit()),
-            )
-            .field(
-                "outfifo_udf_l3",
-                &format_args!("{}", self.outfifo_udf_l3().bit()),
-            )
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf_l1", &self.outfifo_ovf_l1())
+            .field("outfifo_udf_l1", &self.outfifo_udf_l1())
+            .field("outfifo_ovf_l3", &self.outfifo_ovf_l3())
+            .field("outfifo_udf_l3", &self.outfifo_udf_l3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the OUT_DONE_CH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/out_int/raw.rs b/esp32s3/src/dma/ch/out_int/raw.rs
index 219250dd3f..ae79ce7876 100644
--- a/esp32s3/src/dma/ch/out_int/raw.rs
+++ b/esp32s3/src/dma/ch/out_int/raw.rs
@@ -80,41 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RAW")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field(
-                "outfifo_ovf_l1",
-                &format_args!("{}", self.outfifo_ovf_l1().bit()),
-            )
-            .field(
-                "outfifo_udf_l1",
-                &format_args!("{}", self.outfifo_udf_l1().bit()),
-            )
-            .field(
-                "outfifo_ovf_l3",
-                &format_args!("{}", self.outfifo_ovf_l3().bit()),
-            )
-            .field(
-                "outfifo_udf_l3",
-                &format_args!("{}", self.outfifo_udf_l3().bit()),
-            )
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf_l1", &self.outfifo_ovf_l1())
+            .field("outfifo_udf_l1", &self.outfifo_udf_l1())
+            .field("outfifo_ovf_l3", &self.outfifo_ovf_l3())
+            .field("outfifo_udf_l3", &self.outfifo_udf_l3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/out_int/st.rs b/esp32s3/src/dma/ch/out_int/st.rs
index d080712604..d1e0dd5fec 100644
--- a/esp32s3/src/dma/ch/out_int/st.rs
+++ b/esp32s3/src/dma/ch/out_int/st.rs
@@ -62,41 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ST")
-            .field("out_done", &format_args!("{}", self.out_done().bit()))
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field(
-                "out_dscr_err",
-                &format_args!("{}", self.out_dscr_err().bit()),
-            )
-            .field(
-                "out_total_eof",
-                &format_args!("{}", self.out_total_eof().bit()),
-            )
-            .field(
-                "outfifo_ovf_l1",
-                &format_args!("{}", self.outfifo_ovf_l1().bit()),
-            )
-            .field(
-                "outfifo_udf_l1",
-                &format_args!("{}", self.outfifo_udf_l1().bit()),
-            )
-            .field(
-                "outfifo_ovf_l3",
-                &format_args!("{}", self.outfifo_ovf_l3().bit()),
-            )
-            .field(
-                "outfifo_udf_l3",
-                &format_args!("{}", self.outfifo_udf_l3().bit()),
-            )
+            .field("out_done", &self.out_done())
+            .field("out_eof", &self.out_eof())
+            .field("out_dscr_err", &self.out_dscr_err())
+            .field("out_total_eof", &self.out_total_eof())
+            .field("outfifo_ovf_l1", &self.outfifo_ovf_l1())
+            .field("outfifo_udf_l1", &self.outfifo_udf_l1())
+            .field("outfifo_ovf_l3", &self.outfifo_ovf_l3())
+            .field("outfifo_udf_l3", &self.outfifo_udf_l3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ST_SPEC;
 impl crate::RegisterSpec for ST_SPEC {
diff --git a/esp32s3/src/dma/ch/out_link.rs b/esp32s3/src/dma/ch/out_link.rs
index 3902924ab6..6442a59042 100644
--- a/esp32s3/src/dma/ch/out_link.rs
+++ b/esp32s3/src/dma/ch/out_link.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_LINK")
-            .field(
-                "outlink_addr",
-                &format_args!("{}", self.outlink_addr().bits()),
-            )
-            .field(
-                "outlink_stop",
-                &format_args!("{}", self.outlink_stop().bit()),
-            )
-            .field(
-                "outlink_start",
-                &format_args!("{}", self.outlink_start().bit()),
-            )
-            .field(
-                "outlink_restart",
-                &format_args!("{}", self.outlink_restart().bit()),
-            )
-            .field(
-                "outlink_park",
-                &format_args!("{}", self.outlink_park().bit()),
-            )
+            .field("outlink_addr", &self.outlink_addr())
+            .field("outlink_stop", &self.outlink_stop())
+            .field("outlink_start", &self.outlink_start())
+            .field("outlink_restart", &self.outlink_restart())
+            .field("outlink_park", &self.outlink_park())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_LINK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - This register stores the 20 least significant bits of the first outlink descriptor's address."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/out_peri_sel.rs b/esp32s3/src/dma/ch/out_peri_sel.rs
index 575b30b62d..8f602ab61f 100644
--- a/esp32s3/src/dma/ch/out_peri_sel.rs
+++ b/esp32s3/src/dma/ch/out_peri_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PERI_SEL")
-            .field(
-                "peri_out_sel",
-                &format_args!("{}", self.peri_out_sel().bits()),
-            )
+            .field("peri_out_sel", &self.peri_out_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PERI_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/out_pri.rs b/esp32s3/src/dma/ch/out_pri.rs
index 22dcf38610..d2726b8f75 100644
--- a/esp32s3/src/dma/ch/out_pri.rs
+++ b/esp32s3/src/dma/ch/out_pri.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PRI")
-            .field("tx_pri", &format_args!("{}", self.tx_pri().bits()))
+            .field("tx_pri", &self.tx_pri())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PRI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The priority of Tx channel 0. The larger of the value, the higher of the priority."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/out_push.rs b/esp32s3/src/dma/ch/out_push.rs
index 81b41d1874..d5b85551ee 100644
--- a/esp32s3/src/dma/ch/out_push.rs
+++ b/esp32s3/src/dma/ch/out_push.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_PUSH")
-            .field(
-                "outfifo_wdata",
-                &format_args!("{}", self.outfifo_wdata().bits()),
-            )
-            .field(
-                "outfifo_push",
-                &format_args!("{}", self.outfifo_push().bit()),
-            )
+            .field("outfifo_wdata", &self.outfifo_wdata())
+            .field("outfifo_push", &self.outfifo_push())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_PUSH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register stores the data that need to be pushed into DMA FIFO."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/out_state.rs b/esp32s3/src/dma/ch/out_state.rs
index 32eb3ca4e8..9711790741 100644
--- a/esp32s3/src/dma/ch/out_state.rs
+++ b/esp32s3/src/dma/ch/out_state.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_STATE")
-            .field(
-                "outlink_dscr_addr",
-                &format_args!("{}", self.outlink_dscr_addr().bits()),
-            )
-            .field(
-                "out_dscr_state",
-                &format_args!("{}", self.out_dscr_state().bits()),
-            )
-            .field("out_state", &format_args!("{}", self.out_state().bits()))
+            .field("outlink_dscr_addr", &self.outlink_dscr_addr())
+            .field("out_dscr_state", &self.out_dscr_state())
+            .field("out_state", &self.out_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transmit status of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_STATE_SPEC;
 impl crate::RegisterSpec for OUT_STATE_SPEC {
diff --git a/esp32s3/src/dma/ch/out_wight.rs b/esp32s3/src/dma/ch/out_wight.rs
index cc8f81e1a2..515933211d 100644
--- a/esp32s3/src/dma/ch/out_wight.rs
+++ b/esp32s3/src/dma/ch/out_wight.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_WIGHT")
-            .field("tx_weight", &format_args!("{}", self.tx_weight().bits()))
+            .field("tx_weight", &self.tx_weight())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_WIGHT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:11 - The weight of Tx channel 0."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/ch/outfifo_status.rs b/esp32s3/src/dma/ch/outfifo_status.rs
index bbcbc6dedb..c1aaf5e752 100644
--- a/esp32s3/src/dma/ch/outfifo_status.rs
+++ b/esp32s3/src/dma/ch/outfifo_status.rs
@@ -97,67 +97,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUTFIFO_STATUS")
-            .field(
-                "outfifo_full_l1",
-                &format_args!("{}", self.outfifo_full_l1().bit()),
-            )
-            .field(
-                "outfifo_empty_l1",
-                &format_args!("{}", self.outfifo_empty_l1().bit()),
-            )
-            .field(
-                "outfifo_full_l2",
-                &format_args!("{}", self.outfifo_full_l2().bit()),
-            )
-            .field(
-                "outfifo_empty_l2",
-                &format_args!("{}", self.outfifo_empty_l2().bit()),
-            )
-            .field(
-                "outfifo_full_l3",
-                &format_args!("{}", self.outfifo_full_l3().bit()),
-            )
-            .field(
-                "outfifo_empty_l3",
-                &format_args!("{}", self.outfifo_empty_l3().bit()),
-            )
-            .field(
-                "outfifo_cnt_l1",
-                &format_args!("{}", self.outfifo_cnt_l1().bits()),
-            )
-            .field(
-                "outfifo_cnt_l2",
-                &format_args!("{}", self.outfifo_cnt_l2().bits()),
-            )
-            .field(
-                "outfifo_cnt_l3",
-                &format_args!("{}", self.outfifo_cnt_l3().bits()),
-            )
-            .field(
-                "out_remain_under_1b_l3",
-                &format_args!("{}", self.out_remain_under_1b_l3().bit()),
-            )
-            .field(
-                "out_remain_under_2b_l3",
-                &format_args!("{}", self.out_remain_under_2b_l3().bit()),
-            )
-            .field(
-                "out_remain_under_3b_l3",
-                &format_args!("{}", self.out_remain_under_3b_l3().bit()),
-            )
-            .field(
-                "out_remain_under_4b_l3",
-                &format_args!("{}", self.out_remain_under_4b_l3().bit()),
-            )
+            .field("outfifo_full_l1", &self.outfifo_full_l1())
+            .field("outfifo_empty_l1", &self.outfifo_empty_l1())
+            .field("outfifo_full_l2", &self.outfifo_full_l2())
+            .field("outfifo_empty_l2", &self.outfifo_empty_l2())
+            .field("outfifo_full_l3", &self.outfifo_full_l3())
+            .field("outfifo_empty_l3", &self.outfifo_empty_l3())
+            .field("outfifo_cnt_l1", &self.outfifo_cnt_l1())
+            .field("outfifo_cnt_l2", &self.outfifo_cnt_l2())
+            .field("outfifo_cnt_l3", &self.outfifo_cnt_l3())
+            .field("out_remain_under_1b_l3", &self.out_remain_under_1b_l3())
+            .field("out_remain_under_2b_l3", &self.out_remain_under_2b_l3())
+            .field("out_remain_under_3b_l3", &self.out_remain_under_3b_l3())
+            .field("out_remain_under_4b_l3", &self.out_remain_under_4b_l3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUTFIFO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transmit FIFO status of Tx channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`outfifo_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUTFIFO_STATUS_SPEC;
 impl crate::RegisterSpec for OUTFIFO_STATUS_SPEC {
diff --git a/esp32s3/src/dma/date.rs b/esp32s3/src/dma/date.rs
index 1a704036c9..b7939deebb 100644
--- a/esp32s3/src/dma/date.rs
+++ b/esp32s3/src/dma/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/dma/extmem_reject_addr.rs b/esp32s3/src/dma/extmem_reject_addr.rs
index c9f2a48301..2c4ba73b2a 100644
--- a/esp32s3/src/dma/extmem_reject_addr.rs
+++ b/esp32s3/src/dma/extmem_reject_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXTMEM_REJECT_ADDR")
-            .field(
-                "extmem_reject_addr",
-                &format_args!("{}", self.extmem_reject_addr().bits()),
-            )
+            .field("extmem_reject_addr", &self.extmem_reject_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTMEM_REJECT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Reject address accessing external RAM\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`extmem_reject_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXTMEM_REJECT_ADDR_SPEC;
 impl crate::RegisterSpec for EXTMEM_REJECT_ADDR_SPEC {
diff --git a/esp32s3/src/dma/extmem_reject_int_ena.rs b/esp32s3/src/dma/extmem_reject_int_ena.rs
index 97a92b7d95..0fd7e94183 100644
--- a/esp32s3/src/dma/extmem_reject_int_ena.rs
+++ b/esp32s3/src/dma/extmem_reject_int_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXTMEM_REJECT_INT_ENA")
-            .field(
-                "extmem_reject_int_ena",
-                &format_args!("{}", self.extmem_reject_int_ena().bit()),
-            )
+            .field("extmem_reject_int_ena", &self.extmem_reject_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTMEM_REJECT_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the EXTMEM_REJECT_INT interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/extmem_reject_int_raw.rs b/esp32s3/src/dma/extmem_reject_int_raw.rs
index 078df0ebee..daed83cc7d 100644
--- a/esp32s3/src/dma/extmem_reject_int_raw.rs
+++ b/esp32s3/src/dma/extmem_reject_int_raw.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXTMEM_REJECT_INT_RAW")
-            .field(
-                "extmem_reject_int_raw",
-                &format_args!("{}", self.extmem_reject_int_raw().bit()),
-            )
+            .field("extmem_reject_int_raw", &self.extmem_reject_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTMEM_REJECT_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when accessing external RAM is rejected by permission control."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/extmem_reject_int_st.rs b/esp32s3/src/dma/extmem_reject_int_st.rs
index cfa96d9138..d4c4c67963 100644
--- a/esp32s3/src/dma/extmem_reject_int_st.rs
+++ b/esp32s3/src/dma/extmem_reject_int_st.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXTMEM_REJECT_INT_ST")
-            .field(
-                "extmem_reject_int_st",
-                &format_args!("{}", self.extmem_reject_int_st().bit()),
-            )
+            .field("extmem_reject_int_st", &self.extmem_reject_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTMEM_REJECT_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status of external RAM permission\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`extmem_reject_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXTMEM_REJECT_INT_ST_SPEC;
 impl crate::RegisterSpec for EXTMEM_REJECT_INT_ST_SPEC {
diff --git a/esp32s3/src/dma/extmem_reject_st.rs b/esp32s3/src/dma/extmem_reject_st.rs
index 27989e77db..fe5e9c9f0c 100644
--- a/esp32s3/src/dma/extmem_reject_st.rs
+++ b/esp32s3/src/dma/extmem_reject_st.rs
@@ -27,27 +27,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXTMEM_REJECT_ST")
-            .field(
-                "extmem_reject_atrr",
-                &format_args!("{}", self.extmem_reject_atrr().bits()),
-            )
+            .field("extmem_reject_atrr", &self.extmem_reject_atrr())
             .field(
                 "extmem_reject_channel_num",
-                &format_args!("{}", self.extmem_reject_channel_num().bits()),
-            )
-            .field(
-                "extmem_reject_peri_num",
-                &format_args!("{}", self.extmem_reject_peri_num().bits()),
+                &self.extmem_reject_channel_num(),
             )
+            .field("extmem_reject_peri_num", &self.extmem_reject_peri_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTMEM_REJECT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Reject status accessing external RAM\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`extmem_reject_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXTMEM_REJECT_ST_SPEC;
 impl crate::RegisterSpec for EXTMEM_REJECT_ST_SPEC {
diff --git a/esp32s3/src/dma/in_sram_size_ch.rs b/esp32s3/src/dma/in_sram_size_ch.rs
index a8f25e4c7d..7245a57fdf 100644
--- a/esp32s3/src/dma/in_sram_size_ch.rs
+++ b/esp32s3/src/dma/in_sram_size_ch.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_SRAM_SIZE_CH")
-            .field("in_size", &format_args!("{}", self.in_size().bits()))
+            .field("in_size", &self.in_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SRAM_SIZE_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/misc_conf.rs b/esp32s3/src/dma/misc_conf.rs
index f2f7e784dc..41f44867cd 100644
--- a/esp32s3/src/dma/misc_conf.rs
+++ b/esp32s3/src/dma/misc_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC_CONF")
-            .field(
-                "ahbm_rst_inter",
-                &format_args!("{}", self.ahbm_rst_inter().bit()),
-            )
-            .field(
-                "ahbm_rst_exter",
-                &format_args!("{}", self.ahbm_rst_exter().bit()),
-            )
-            .field("arb_pri_dis", &format_args!("{}", self.arb_pri_dis().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("ahbm_rst_inter", &self.ahbm_rst_inter())
+            .field("ahbm_rst_exter", &self.ahbm_rst_exter())
+            .field("arb_pri_dis", &self.arb_pri_dis())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit, then clear this bit to reset the internal ahb FSM."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/out_sram_size_ch.rs b/esp32s3/src/dma/out_sram_size_ch.rs
index 3eaa05a2de..f7243aa38e 100644
--- a/esp32s3/src/dma/out_sram_size_ch.rs
+++ b/esp32s3/src/dma/out_sram_size_ch.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_SRAM_SIZE_CH")
-            .field("out_size", &format_args!("{}", self.out_size().bits()))
+            .field("out_size", &self.out_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_SRAM_SIZE_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes."]
     #[inline(always)]
diff --git a/esp32s3/src/dma/pd_conf.rs b/esp32s3/src/dma/pd_conf.rs
index 0870468c6e..8af6be9c78 100644
--- a/esp32s3/src/dma/pd_conf.rs
+++ b/esp32s3/src/dma/pd_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PD_CONF")
-            .field(
-                "dma_ram_force_pd",
-                &format_args!("{}", self.dma_ram_force_pd().bit()),
-            )
-            .field(
-                "dma_ram_force_pu",
-                &format_args!("{}", self.dma_ram_force_pu().bit()),
-            )
-            .field(
-                "dma_ram_clk_fo",
-                &format_args!("{}", self.dma_ram_clk_fo().bit()),
-            )
+            .field("dma_ram_force_pd", &self.dma_ram_force_pd())
+            .field("dma_ram_force_pu", &self.dma_ram_force_pu())
+            .field("dma_ram_clk_fo", &self.dma_ram_clk_fo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 4 - Set this bit to force power down DMA internal memory."]
     #[inline(always)]
diff --git a/esp32s3/src/ds/c_mem.rs b/esp32s3/src/ds/c_mem.rs
index a2efd21766..19881222bf 100644
--- a/esp32s3/src/ds/c_mem.rs
+++ b/esp32s3/src/ds/c_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<C_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Memory C\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`c_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`c_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct C_MEM_SPEC;
diff --git a/esp32s3/src/ds/date.rs b/esp32s3/src/ds/date.rs
index 8bdc1af468..a7d17eba27 100644
--- a/esp32s3/src/ds/date.rs
+++ b/esp32s3/src/ds/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/ds/iv_.rs b/esp32s3/src/ds/iv_.rs
index efa79db050..57bb70e4c6 100644
--- a/esp32s3/src/ds/iv_.rs
+++ b/esp32s3/src/ds/iv_.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("IV_")
-            .field("iv", &format_args!("{}", self.iv().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IV__SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("IV_").field("iv", &self.iv()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/ds/query_busy.rs b/esp32s3/src/ds/query_busy.rs
index 3fbc8ae0f7..393c760cb1 100644
--- a/esp32s3/src/ds/query_busy.rs
+++ b/esp32s3/src/ds/query_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_BUSY")
-            .field("query_busy", &format_args!("{}", self.query_busy().bit()))
+            .field("query_busy", &self.query_busy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of the DS perihperal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_BUSY_SPEC;
 impl crate::RegisterSpec for QUERY_BUSY_SPEC {
diff --git a/esp32s3/src/ds/query_check.rs b/esp32s3/src/ds/query_check.rs
index 76df8e9cc1..077c25709d 100644
--- a/esp32s3/src/ds/query_check.rs
+++ b/esp32s3/src/ds/query_check.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_CHECK")
-            .field("md_error", &format_args!("{}", self.md_error().bit()))
-            .field("padding_bad", &format_args!("{}", self.padding_bad().bit()))
+            .field("md_error", &self.md_error())
+            .field("padding_bad", &self.padding_bad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_CHECK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Queries DS check result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_check::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_CHECK_SPEC;
 impl crate::RegisterSpec for QUERY_CHECK_SPEC {
diff --git a/esp32s3/src/ds/query_key_wrong.rs b/esp32s3/src/ds/query_key_wrong.rs
index 6d0787b46f..ff03666796 100644
--- a/esp32s3/src/ds/query_key_wrong.rs
+++ b/esp32s3/src/ds/query_key_wrong.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_KEY_WRONG")
-            .field(
-                "query_key_wrong",
-                &format_args!("{}", self.query_key_wrong().bits()),
-            )
+            .field("query_key_wrong", &self.query_key_wrong())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_KEY_WRONG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Checks the reason why DS_KEY is not ready\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_key_wrong::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_KEY_WRONG_SPEC;
 impl crate::RegisterSpec for QUERY_KEY_WRONG_SPEC {
diff --git a/esp32s3/src/ds/x_mem.rs b/esp32s3/src/ds/x_mem.rs
index 73e1771489..8644f086a0 100644
--- a/esp32s3/src/ds/x_mem.rs
+++ b/esp32s3/src/ds/x_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<X_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Memory X\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`x_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`x_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct X_MEM_SPEC;
diff --git a/esp32s3/src/ds/z_mem.rs b/esp32s3/src/ds/z_mem.rs
index 746af18ef5..2ccae2ffb1 100644
--- a/esp32s3/src/ds/z_mem.rs
+++ b/esp32s3/src/ds/z_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Z_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Memory Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Z_MEM_SPEC;
diff --git a/esp32s3/src/efuse/clk.rs b/esp32s3/src/efuse/clk.rs
index 9d7225a659..e2bcfaffbf 100644
--- a/esp32s3/src/efuse/clk.rs
+++ b/esp32s3/src/efuse/clk.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK")
-            .field(
-                "efuse_mem_force_pd",
-                &format_args!("{}", self.efuse_mem_force_pd().bit()),
-            )
-            .field(
-                "mem_clk_force_on",
-                &format_args!("{}", self.mem_clk_force_on().bit()),
-            )
-            .field(
-                "efuse_mem_force_pu",
-                &format_args!("{}", self.efuse_mem_force_pu().bit()),
-            )
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("efuse_mem_force_pd", &self.efuse_mem_force_pd())
+            .field("mem_clk_force_on", &self.mem_clk_force_on())
+            .field("efuse_mem_force_pu", &self.efuse_mem_force_pu())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to force eFuse SRAM into power-saving mode."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/cmd.rs b/esp32s3/src/efuse/cmd.rs
index 8dee79bc65..094d443be3 100644
--- a/esp32s3/src/efuse/cmd.rs
+++ b/esp32s3/src/efuse/cmd.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("read_cmd", &format_args!("{}", self.read_cmd().bit()))
-            .field("pgm_cmd", &format_args!("{}", self.pgm_cmd().bit()))
-            .field("blk_num", &format_args!("{}", self.blk_num().bits()))
+            .field("read_cmd", &self.read_cmd())
+            .field("pgm_cmd", &self.pgm_cmd())
+            .field("blk_num", &self.blk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to send read command."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/conf.rs b/esp32s3/src/efuse/conf.rs
index 0aebe5f24c..3f9d5c90f6 100644
--- a/esp32s3/src/efuse/conf.rs
+++ b/esp32s3/src/efuse/conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("op_code", &format_args!("{}", self.op_code().bits()))
+            .field("op_code", &self.op_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - 0x5A5A: Operate programming command 0x5AA5: Operate read command."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/dac_conf.rs b/esp32s3/src/efuse/dac_conf.rs
index 46081e022e..e9db91d486 100644
--- a/esp32s3/src/efuse/dac_conf.rs
+++ b/esp32s3/src/efuse/dac_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DAC_CONF")
-            .field(
-                "dac_clk_div",
-                &format_args!("{}", self.dac_clk_div().bits()),
-            )
-            .field(
-                "dac_clk_pad_sel",
-                &format_args!("{}", self.dac_clk_pad_sel().bit()),
-            )
-            .field("dac_num", &format_args!("{}", self.dac_num().bits()))
-            .field("oe_clr", &format_args!("{}", self.oe_clr().bit()))
+            .field("dac_clk_div", &self.dac_clk_div())
+            .field("dac_clk_pad_sel", &self.dac_clk_pad_sel())
+            .field("dac_num", &self.dac_num())
+            .field("oe_clr", &self.oe_clr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DAC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Controls the division factor of the rising clock of the programming voltage."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/date.rs b/esp32s3/src/efuse/date.rs
index d1e39d1500..5c58eb78db 100644
--- a/esp32s3/src/efuse/date.rs
+++ b/esp32s3/src/efuse/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/efuse/int_ena.rs b/esp32s3/src/efuse/int_ena.rs
index 6386df2821..0020c7e668 100644
--- a/esp32s3/src/efuse/int_ena.rs
+++ b/esp32s3/src/efuse/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable signal for read_done interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/int_raw.rs b/esp32s3/src/efuse/int_raw.rs
index 914c4f8c84..3d99203c2c 100644
--- a/esp32s3/src/efuse/int_raw.rs
+++ b/esp32s3/src/efuse/int_raw.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw bit signal for read_done interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/int_st.rs b/esp32s3/src/efuse/int_st.rs
index 898ceb8e8b..efba508ff2 100644
--- a/esp32s3/src/efuse/int_st.rs
+++ b/esp32s3/src/efuse/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("read_done", &format_args!("{}", self.read_done().bit()))
-            .field("pgm_done", &format_args!("{}", self.pgm_done().bit()))
+            .field("read_done", &self.read_done())
+            .field("pgm_done", &self.pgm_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/efuse/pgm_check_value0.rs b/esp32s3/src/efuse/pgm_check_value0.rs
index c116858f94..a6d3c26060 100644
--- a/esp32s3/src/efuse/pgm_check_value0.rs
+++ b/esp32s3/src/efuse/pgm_check_value0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE0")
-            .field(
-                "pgm_rs_data_0",
-                &format_args!("{}", self.pgm_rs_data_0().bits()),
-            )
+            .field("pgm_rs_data_0", &self.pgm_rs_data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 0th 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/pgm_check_value1.rs b/esp32s3/src/efuse/pgm_check_value1.rs
index 331e741927..875b090b36 100644
--- a/esp32s3/src/efuse/pgm_check_value1.rs
+++ b/esp32s3/src/efuse/pgm_check_value1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE1")
-            .field(
-                "pgm_rs_data_1",
-                &format_args!("{}", self.pgm_rs_data_1().bits()),
-            )
+            .field("pgm_rs_data_1", &self.pgm_rs_data_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 1st 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/pgm_check_value2.rs b/esp32s3/src/efuse/pgm_check_value2.rs
index 57aaf58855..571fe98175 100644
--- a/esp32s3/src/efuse/pgm_check_value2.rs
+++ b/esp32s3/src/efuse/pgm_check_value2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_CHECK_VALUE2")
-            .field(
-                "pgm_rs_data_2",
-                &format_args!("{}", self.pgm_rs_data_2().bits()),
-            )
+            .field("pgm_rs_data_2", &self.pgm_rs_data_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_CHECK_VALUE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 2nd 32-bit RS code to be programmed."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/pgm_data0.rs b/esp32s3/src/efuse/pgm_data0.rs
index 3cc5ffca3b..b04bf3a372 100644
--- a/esp32s3/src/efuse/pgm_data0.rs
+++ b/esp32s3/src/efuse/pgm_data0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA0")
-            .field("pgm_data_0", &format_args!("{}", self.pgm_data_0().bits()))
+            .field("pgm_data_0", &self.pgm_data_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 0th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/pgm_data1.rs b/esp32s3/src/efuse/pgm_data1.rs
index e01b369302..4d0e9f9794 100644
--- a/esp32s3/src/efuse/pgm_data1.rs
+++ b/esp32s3/src/efuse/pgm_data1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA1")
-            .field("pgm_data_1", &format_args!("{}", self.pgm_data_1().bits()))
+            .field("pgm_data_1", &self.pgm_data_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 1st 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/pgm_data2.rs b/esp32s3/src/efuse/pgm_data2.rs
index bb62a4d24f..f04c46cc20 100644
--- a/esp32s3/src/efuse/pgm_data2.rs
+++ b/esp32s3/src/efuse/pgm_data2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA2")
-            .field("pgm_data_2", &format_args!("{}", self.pgm_data_2().bits()))
+            .field("pgm_data_2", &self.pgm_data_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 2nd 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/pgm_data3.rs b/esp32s3/src/efuse/pgm_data3.rs
index 835e17347f..50d284df5b 100644
--- a/esp32s3/src/efuse/pgm_data3.rs
+++ b/esp32s3/src/efuse/pgm_data3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA3")
-            .field("pgm_data_3", &format_args!("{}", self.pgm_data_3().bits()))
+            .field("pgm_data_3", &self.pgm_data_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 3rd 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/pgm_data4.rs b/esp32s3/src/efuse/pgm_data4.rs
index 6806135803..0de88ae64c 100644
--- a/esp32s3/src/efuse/pgm_data4.rs
+++ b/esp32s3/src/efuse/pgm_data4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA4")
-            .field("pgm_data_4", &format_args!("{}", self.pgm_data_4().bits()))
+            .field("pgm_data_4", &self.pgm_data_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 4th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/pgm_data5.rs b/esp32s3/src/efuse/pgm_data5.rs
index e76d9ed490..839f0680b0 100644
--- a/esp32s3/src/efuse/pgm_data5.rs
+++ b/esp32s3/src/efuse/pgm_data5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA5")
-            .field("pgm_data_5", &format_args!("{}", self.pgm_data_5().bits()))
+            .field("pgm_data_5", &self.pgm_data_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 5th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/pgm_data6.rs b/esp32s3/src/efuse/pgm_data6.rs
index e50d19c967..f66b3f5d01 100644
--- a/esp32s3/src/efuse/pgm_data6.rs
+++ b/esp32s3/src/efuse/pgm_data6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA6")
-            .field("pgm_data_6", &format_args!("{}", self.pgm_data_6().bits()))
+            .field("pgm_data_6", &self.pgm_data_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 6th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/pgm_data7.rs b/esp32s3/src/efuse/pgm_data7.rs
index 886fcdcb3c..f8a8d36257 100644
--- a/esp32s3/src/efuse/pgm_data7.rs
+++ b/esp32s3/src/efuse/pgm_data7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PGM_DATA7")
-            .field("pgm_data_7", &format_args!("{}", self.pgm_data_7().bits()))
+            .field("pgm_data_7", &self.pgm_data_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PGM_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The content of the 7th 32-bit data to be programmed."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/rd_key0_data0.rs b/esp32s3/src/efuse/rd_key0_data0.rs
index c4170de549..a46c1ad944 100644
--- a/esp32s3/src/efuse/rd_key0_data0.rs
+++ b/esp32s3/src/efuse/rd_key0_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA0")
-            .field("key0_data0", &format_args!("{}", self.key0_data0().bits()))
+            .field("key0_data0", &self.key0_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA0_SPEC {
diff --git a/esp32s3/src/efuse/rd_key0_data1.rs b/esp32s3/src/efuse/rd_key0_data1.rs
index c545a21ca4..d802c4324d 100644
--- a/esp32s3/src/efuse/rd_key0_data1.rs
+++ b/esp32s3/src/efuse/rd_key0_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA1")
-            .field("key0_data1", &format_args!("{}", self.key0_data1().bits()))
+            .field("key0_data1", &self.key0_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA1_SPEC {
diff --git a/esp32s3/src/efuse/rd_key0_data2.rs b/esp32s3/src/efuse/rd_key0_data2.rs
index 75a9d79d9b..c125d21c76 100644
--- a/esp32s3/src/efuse/rd_key0_data2.rs
+++ b/esp32s3/src/efuse/rd_key0_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA2")
-            .field("key0_data2", &format_args!("{}", self.key0_data2().bits()))
+            .field("key0_data2", &self.key0_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA2_SPEC {
diff --git a/esp32s3/src/efuse/rd_key0_data3.rs b/esp32s3/src/efuse/rd_key0_data3.rs
index ce90c2cf18..a9043355cf 100644
--- a/esp32s3/src/efuse/rd_key0_data3.rs
+++ b/esp32s3/src/efuse/rd_key0_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA3")
-            .field("key0_data3", &format_args!("{}", self.key0_data3().bits()))
+            .field("key0_data3", &self.key0_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA3_SPEC {
diff --git a/esp32s3/src/efuse/rd_key0_data4.rs b/esp32s3/src/efuse/rd_key0_data4.rs
index f27e3d5095..d80cc60787 100644
--- a/esp32s3/src/efuse/rd_key0_data4.rs
+++ b/esp32s3/src/efuse/rd_key0_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA4")
-            .field("key0_data4", &format_args!("{}", self.key0_data4().bits()))
+            .field("key0_data4", &self.key0_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA4_SPEC {
diff --git a/esp32s3/src/efuse/rd_key0_data5.rs b/esp32s3/src/efuse/rd_key0_data5.rs
index d4fbdcadc6..0df76ff5a6 100644
--- a/esp32s3/src/efuse/rd_key0_data5.rs
+++ b/esp32s3/src/efuse/rd_key0_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA5")
-            .field("key0_data5", &format_args!("{}", self.key0_data5().bits()))
+            .field("key0_data5", &self.key0_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA5_SPEC {
diff --git a/esp32s3/src/efuse/rd_key0_data6.rs b/esp32s3/src/efuse/rd_key0_data6.rs
index 85a08de8fa..eb4c2beec8 100644
--- a/esp32s3/src/efuse/rd_key0_data6.rs
+++ b/esp32s3/src/efuse/rd_key0_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA6")
-            .field("key0_data6", &format_args!("{}", self.key0_data6().bits()))
+            .field("key0_data6", &self.key0_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA6_SPEC {
diff --git a/esp32s3/src/efuse/rd_key0_data7.rs b/esp32s3/src/efuse/rd_key0_data7.rs
index 2cfe17e0d2..b453d144d1 100644
--- a/esp32s3/src/efuse/rd_key0_data7.rs
+++ b/esp32s3/src/efuse/rd_key0_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY0_DATA7")
-            .field("key0_data7", &format_args!("{}", self.key0_data7().bits()))
+            .field("key0_data7", &self.key0_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY0_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK4 (KEY0).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key0_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY0_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY0_DATA7_SPEC {
diff --git a/esp32s3/src/efuse/rd_key1_data0.rs b/esp32s3/src/efuse/rd_key1_data0.rs
index 291c7485e1..cbdf301dd6 100644
--- a/esp32s3/src/efuse/rd_key1_data0.rs
+++ b/esp32s3/src/efuse/rd_key1_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA0")
-            .field("key1_data0", &format_args!("{}", self.key1_data0().bits()))
+            .field("key1_data0", &self.key1_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA0_SPEC {
diff --git a/esp32s3/src/efuse/rd_key1_data1.rs b/esp32s3/src/efuse/rd_key1_data1.rs
index 2b30399c9e..0d2ca792e8 100644
--- a/esp32s3/src/efuse/rd_key1_data1.rs
+++ b/esp32s3/src/efuse/rd_key1_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA1")
-            .field("key1_data1", &format_args!("{}", self.key1_data1().bits()))
+            .field("key1_data1", &self.key1_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA1_SPEC {
diff --git a/esp32s3/src/efuse/rd_key1_data2.rs b/esp32s3/src/efuse/rd_key1_data2.rs
index d19bb9bf8c..0cfb551fa0 100644
--- a/esp32s3/src/efuse/rd_key1_data2.rs
+++ b/esp32s3/src/efuse/rd_key1_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA2")
-            .field("key1_data2", &format_args!("{}", self.key1_data2().bits()))
+            .field("key1_data2", &self.key1_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA2_SPEC {
diff --git a/esp32s3/src/efuse/rd_key1_data3.rs b/esp32s3/src/efuse/rd_key1_data3.rs
index f392fa1939..0e48686024 100644
--- a/esp32s3/src/efuse/rd_key1_data3.rs
+++ b/esp32s3/src/efuse/rd_key1_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA3")
-            .field("key1_data3", &format_args!("{}", self.key1_data3().bits()))
+            .field("key1_data3", &self.key1_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA3_SPEC {
diff --git a/esp32s3/src/efuse/rd_key1_data4.rs b/esp32s3/src/efuse/rd_key1_data4.rs
index 9eec3ea746..7856929463 100644
--- a/esp32s3/src/efuse/rd_key1_data4.rs
+++ b/esp32s3/src/efuse/rd_key1_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA4")
-            .field("key1_data4", &format_args!("{}", self.key1_data4().bits()))
+            .field("key1_data4", &self.key1_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA4_SPEC {
diff --git a/esp32s3/src/efuse/rd_key1_data5.rs b/esp32s3/src/efuse/rd_key1_data5.rs
index abb6571e50..3e1c7a10ca 100644
--- a/esp32s3/src/efuse/rd_key1_data5.rs
+++ b/esp32s3/src/efuse/rd_key1_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA5")
-            .field("key1_data5", &format_args!("{}", self.key1_data5().bits()))
+            .field("key1_data5", &self.key1_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA5_SPEC {
diff --git a/esp32s3/src/efuse/rd_key1_data6.rs b/esp32s3/src/efuse/rd_key1_data6.rs
index 2480507f1d..f9e0c0b597 100644
--- a/esp32s3/src/efuse/rd_key1_data6.rs
+++ b/esp32s3/src/efuse/rd_key1_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA6")
-            .field("key1_data6", &format_args!("{}", self.key1_data6().bits()))
+            .field("key1_data6", &self.key1_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA6_SPEC {
diff --git a/esp32s3/src/efuse/rd_key1_data7.rs b/esp32s3/src/efuse/rd_key1_data7.rs
index e912db2958..3aae5b0aa5 100644
--- a/esp32s3/src/efuse/rd_key1_data7.rs
+++ b/esp32s3/src/efuse/rd_key1_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY1_DATA7")
-            .field("key1_data7", &format_args!("{}", self.key1_data7().bits()))
+            .field("key1_data7", &self.key1_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY1_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK5 (KEY1).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key1_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY1_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY1_DATA7_SPEC {
diff --git a/esp32s3/src/efuse/rd_key2_data0.rs b/esp32s3/src/efuse/rd_key2_data0.rs
index f4e6afd656..7213af4aa1 100644
--- a/esp32s3/src/efuse/rd_key2_data0.rs
+++ b/esp32s3/src/efuse/rd_key2_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA0")
-            .field("key2_data0", &format_args!("{}", self.key2_data0().bits()))
+            .field("key2_data0", &self.key2_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA0_SPEC {
diff --git a/esp32s3/src/efuse/rd_key2_data1.rs b/esp32s3/src/efuse/rd_key2_data1.rs
index c4742c50b6..e5c0bcfc43 100644
--- a/esp32s3/src/efuse/rd_key2_data1.rs
+++ b/esp32s3/src/efuse/rd_key2_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA1")
-            .field("key2_data1", &format_args!("{}", self.key2_data1().bits()))
+            .field("key2_data1", &self.key2_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA1_SPEC {
diff --git a/esp32s3/src/efuse/rd_key2_data2.rs b/esp32s3/src/efuse/rd_key2_data2.rs
index 5f49546147..7ae05d7b8b 100644
--- a/esp32s3/src/efuse/rd_key2_data2.rs
+++ b/esp32s3/src/efuse/rd_key2_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA2")
-            .field("key2_data2", &format_args!("{}", self.key2_data2().bits()))
+            .field("key2_data2", &self.key2_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA2_SPEC {
diff --git a/esp32s3/src/efuse/rd_key2_data3.rs b/esp32s3/src/efuse/rd_key2_data3.rs
index eb778f7774..b0856f695b 100644
--- a/esp32s3/src/efuse/rd_key2_data3.rs
+++ b/esp32s3/src/efuse/rd_key2_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA3")
-            .field("key2_data3", &format_args!("{}", self.key2_data3().bits()))
+            .field("key2_data3", &self.key2_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA3_SPEC {
diff --git a/esp32s3/src/efuse/rd_key2_data4.rs b/esp32s3/src/efuse/rd_key2_data4.rs
index 613b92fb18..f8cccf58ca 100644
--- a/esp32s3/src/efuse/rd_key2_data4.rs
+++ b/esp32s3/src/efuse/rd_key2_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA4")
-            .field("key2_data4", &format_args!("{}", self.key2_data4().bits()))
+            .field("key2_data4", &self.key2_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA4_SPEC {
diff --git a/esp32s3/src/efuse/rd_key2_data5.rs b/esp32s3/src/efuse/rd_key2_data5.rs
index f759177d7f..4b3e9fb766 100644
--- a/esp32s3/src/efuse/rd_key2_data5.rs
+++ b/esp32s3/src/efuse/rd_key2_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA5")
-            .field("key2_data5", &format_args!("{}", self.key2_data5().bits()))
+            .field("key2_data5", &self.key2_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA5_SPEC {
diff --git a/esp32s3/src/efuse/rd_key2_data6.rs b/esp32s3/src/efuse/rd_key2_data6.rs
index e4532e5ac7..25c9cf68ef 100644
--- a/esp32s3/src/efuse/rd_key2_data6.rs
+++ b/esp32s3/src/efuse/rd_key2_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA6")
-            .field("key2_data6", &format_args!("{}", self.key2_data6().bits()))
+            .field("key2_data6", &self.key2_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA6_SPEC {
diff --git a/esp32s3/src/efuse/rd_key2_data7.rs b/esp32s3/src/efuse/rd_key2_data7.rs
index 3cc83cb7e1..4a67033e6f 100644
--- a/esp32s3/src/efuse/rd_key2_data7.rs
+++ b/esp32s3/src/efuse/rd_key2_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY2_DATA7")
-            .field("key2_data7", &format_args!("{}", self.key2_data7().bits()))
+            .field("key2_data7", &self.key2_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY2_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK6 (KEY2).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key2_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY2_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY2_DATA7_SPEC {
diff --git a/esp32s3/src/efuse/rd_key3_data0.rs b/esp32s3/src/efuse/rd_key3_data0.rs
index b53838b293..edc175d9ea 100644
--- a/esp32s3/src/efuse/rd_key3_data0.rs
+++ b/esp32s3/src/efuse/rd_key3_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA0")
-            .field("key3_data0", &format_args!("{}", self.key3_data0().bits()))
+            .field("key3_data0", &self.key3_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA0_SPEC {
diff --git a/esp32s3/src/efuse/rd_key3_data1.rs b/esp32s3/src/efuse/rd_key3_data1.rs
index 9bab6de8e8..20834c399e 100644
--- a/esp32s3/src/efuse/rd_key3_data1.rs
+++ b/esp32s3/src/efuse/rd_key3_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA1")
-            .field("key3_data1", &format_args!("{}", self.key3_data1().bits()))
+            .field("key3_data1", &self.key3_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA1_SPEC {
diff --git a/esp32s3/src/efuse/rd_key3_data2.rs b/esp32s3/src/efuse/rd_key3_data2.rs
index 8642471a16..e957b7fe84 100644
--- a/esp32s3/src/efuse/rd_key3_data2.rs
+++ b/esp32s3/src/efuse/rd_key3_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA2")
-            .field("key3_data2", &format_args!("{}", self.key3_data2().bits()))
+            .field("key3_data2", &self.key3_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA2_SPEC {
diff --git a/esp32s3/src/efuse/rd_key3_data3.rs b/esp32s3/src/efuse/rd_key3_data3.rs
index dbc82ce3e9..f3b0215503 100644
--- a/esp32s3/src/efuse/rd_key3_data3.rs
+++ b/esp32s3/src/efuse/rd_key3_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA3")
-            .field("key3_data3", &format_args!("{}", self.key3_data3().bits()))
+            .field("key3_data3", &self.key3_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA3_SPEC {
diff --git a/esp32s3/src/efuse/rd_key3_data4.rs b/esp32s3/src/efuse/rd_key3_data4.rs
index 7f6aa4b29a..7cc8bbe55a 100644
--- a/esp32s3/src/efuse/rd_key3_data4.rs
+++ b/esp32s3/src/efuse/rd_key3_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA4")
-            .field("key3_data4", &format_args!("{}", self.key3_data4().bits()))
+            .field("key3_data4", &self.key3_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA4_SPEC {
diff --git a/esp32s3/src/efuse/rd_key3_data5.rs b/esp32s3/src/efuse/rd_key3_data5.rs
index ba520c7d60..a5579ffdc5 100644
--- a/esp32s3/src/efuse/rd_key3_data5.rs
+++ b/esp32s3/src/efuse/rd_key3_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA5")
-            .field("key3_data5", &format_args!("{}", self.key3_data5().bits()))
+            .field("key3_data5", &self.key3_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA5_SPEC {
diff --git a/esp32s3/src/efuse/rd_key3_data6.rs b/esp32s3/src/efuse/rd_key3_data6.rs
index b5fbe2051a..57afdeaf52 100644
--- a/esp32s3/src/efuse/rd_key3_data6.rs
+++ b/esp32s3/src/efuse/rd_key3_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA6")
-            .field("key3_data6", &format_args!("{}", self.key3_data6().bits()))
+            .field("key3_data6", &self.key3_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA6_SPEC {
diff --git a/esp32s3/src/efuse/rd_key3_data7.rs b/esp32s3/src/efuse/rd_key3_data7.rs
index 4bf010d286..7224fccfd6 100644
--- a/esp32s3/src/efuse/rd_key3_data7.rs
+++ b/esp32s3/src/efuse/rd_key3_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY3_DATA7")
-            .field("key3_data7", &format_args!("{}", self.key3_data7().bits()))
+            .field("key3_data7", &self.key3_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY3_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK7 (KEY3).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key3_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY3_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY3_DATA7_SPEC {
diff --git a/esp32s3/src/efuse/rd_key4_data0.rs b/esp32s3/src/efuse/rd_key4_data0.rs
index 224e960459..e82346659e 100644
--- a/esp32s3/src/efuse/rd_key4_data0.rs
+++ b/esp32s3/src/efuse/rd_key4_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA0")
-            .field("key4_data0", &format_args!("{}", self.key4_data0().bits()))
+            .field("key4_data0", &self.key4_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA0_SPEC {
diff --git a/esp32s3/src/efuse/rd_key4_data1.rs b/esp32s3/src/efuse/rd_key4_data1.rs
index 6ff0dfd449..34e5bcdf93 100644
--- a/esp32s3/src/efuse/rd_key4_data1.rs
+++ b/esp32s3/src/efuse/rd_key4_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA1")
-            .field("key4_data1", &format_args!("{}", self.key4_data1().bits()))
+            .field("key4_data1", &self.key4_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA1_SPEC {
diff --git a/esp32s3/src/efuse/rd_key4_data2.rs b/esp32s3/src/efuse/rd_key4_data2.rs
index f997607afe..445df040aa 100644
--- a/esp32s3/src/efuse/rd_key4_data2.rs
+++ b/esp32s3/src/efuse/rd_key4_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA2")
-            .field("key4_data2", &format_args!("{}", self.key4_data2().bits()))
+            .field("key4_data2", &self.key4_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA2_SPEC {
diff --git a/esp32s3/src/efuse/rd_key4_data3.rs b/esp32s3/src/efuse/rd_key4_data3.rs
index a834d67a07..4c4e20f86e 100644
--- a/esp32s3/src/efuse/rd_key4_data3.rs
+++ b/esp32s3/src/efuse/rd_key4_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA3")
-            .field("key4_data3", &format_args!("{}", self.key4_data3().bits()))
+            .field("key4_data3", &self.key4_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA3_SPEC {
diff --git a/esp32s3/src/efuse/rd_key4_data4.rs b/esp32s3/src/efuse/rd_key4_data4.rs
index d3955483ff..25683fd8ac 100644
--- a/esp32s3/src/efuse/rd_key4_data4.rs
+++ b/esp32s3/src/efuse/rd_key4_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA4")
-            .field("key4_data4", &format_args!("{}", self.key4_data4().bits()))
+            .field("key4_data4", &self.key4_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA4_SPEC {
diff --git a/esp32s3/src/efuse/rd_key4_data5.rs b/esp32s3/src/efuse/rd_key4_data5.rs
index 6a04334533..91cdeaf66b 100644
--- a/esp32s3/src/efuse/rd_key4_data5.rs
+++ b/esp32s3/src/efuse/rd_key4_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA5")
-            .field("key4_data5", &format_args!("{}", self.key4_data5().bits()))
+            .field("key4_data5", &self.key4_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA5_SPEC {
diff --git a/esp32s3/src/efuse/rd_key4_data6.rs b/esp32s3/src/efuse/rd_key4_data6.rs
index a074f789f0..a2a37a60a0 100644
--- a/esp32s3/src/efuse/rd_key4_data6.rs
+++ b/esp32s3/src/efuse/rd_key4_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA6")
-            .field("key4_data6", &format_args!("{}", self.key4_data6().bits()))
+            .field("key4_data6", &self.key4_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA6_SPEC {
diff --git a/esp32s3/src/efuse/rd_key4_data7.rs b/esp32s3/src/efuse/rd_key4_data7.rs
index da0d7a8a25..92015173a2 100644
--- a/esp32s3/src/efuse/rd_key4_data7.rs
+++ b/esp32s3/src/efuse/rd_key4_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY4_DATA7")
-            .field("key4_data7", &format_args!("{}", self.key4_data7().bits()))
+            .field("key4_data7", &self.key4_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY4_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK8 (KEY4).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key4_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY4_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY4_DATA7_SPEC {
diff --git a/esp32s3/src/efuse/rd_key5_data0.rs b/esp32s3/src/efuse/rd_key5_data0.rs
index 77933e6ce1..ce5f01baec 100644
--- a/esp32s3/src/efuse/rd_key5_data0.rs
+++ b/esp32s3/src/efuse/rd_key5_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA0")
-            .field("key5_data0", &format_args!("{}", self.key5_data0().bits()))
+            .field("key5_data0", &self.key5_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA0_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA0_SPEC {
diff --git a/esp32s3/src/efuse/rd_key5_data1.rs b/esp32s3/src/efuse/rd_key5_data1.rs
index 541bbb93af..29fbb2fa9b 100644
--- a/esp32s3/src/efuse/rd_key5_data1.rs
+++ b/esp32s3/src/efuse/rd_key5_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA1")
-            .field("key5_data1", &format_args!("{}", self.key5_data1().bits()))
+            .field("key5_data1", &self.key5_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA1_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA1_SPEC {
diff --git a/esp32s3/src/efuse/rd_key5_data2.rs b/esp32s3/src/efuse/rd_key5_data2.rs
index 99bf133501..4c07c8914e 100644
--- a/esp32s3/src/efuse/rd_key5_data2.rs
+++ b/esp32s3/src/efuse/rd_key5_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA2")
-            .field("key5_data2", &format_args!("{}", self.key5_data2().bits()))
+            .field("key5_data2", &self.key5_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA2_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA2_SPEC {
diff --git a/esp32s3/src/efuse/rd_key5_data3.rs b/esp32s3/src/efuse/rd_key5_data3.rs
index 363fc5aff8..3964d455f7 100644
--- a/esp32s3/src/efuse/rd_key5_data3.rs
+++ b/esp32s3/src/efuse/rd_key5_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA3")
-            .field("key5_data3", &format_args!("{}", self.key5_data3().bits()))
+            .field("key5_data3", &self.key5_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA3_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA3_SPEC {
diff --git a/esp32s3/src/efuse/rd_key5_data4.rs b/esp32s3/src/efuse/rd_key5_data4.rs
index 37367759f0..05999f9ce2 100644
--- a/esp32s3/src/efuse/rd_key5_data4.rs
+++ b/esp32s3/src/efuse/rd_key5_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA4")
-            .field("key5_data4", &format_args!("{}", self.key5_data4().bits()))
+            .field("key5_data4", &self.key5_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA4_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA4_SPEC {
diff --git a/esp32s3/src/efuse/rd_key5_data5.rs b/esp32s3/src/efuse/rd_key5_data5.rs
index d26e0a4811..fbbb97ea40 100644
--- a/esp32s3/src/efuse/rd_key5_data5.rs
+++ b/esp32s3/src/efuse/rd_key5_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA5")
-            .field("key5_data5", &format_args!("{}", self.key5_data5().bits()))
+            .field("key5_data5", &self.key5_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA5_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA5_SPEC {
diff --git a/esp32s3/src/efuse/rd_key5_data6.rs b/esp32s3/src/efuse/rd_key5_data6.rs
index 70ee60bd3f..c4561ed596 100644
--- a/esp32s3/src/efuse/rd_key5_data6.rs
+++ b/esp32s3/src/efuse/rd_key5_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA6")
-            .field("key5_data6", &format_args!("{}", self.key5_data6().bits()))
+            .field("key5_data6", &self.key5_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA6_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA6_SPEC {
diff --git a/esp32s3/src/efuse/rd_key5_data7.rs b/esp32s3/src/efuse/rd_key5_data7.rs
index f6c536431d..8d595e1adb 100644
--- a/esp32s3/src/efuse/rd_key5_data7.rs
+++ b/esp32s3/src/efuse/rd_key5_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_KEY5_DATA7")
-            .field("key5_data7", &format_args!("{}", self.key5_data7().bits()))
+            .field("key5_data7", &self.key5_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_KEY5_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_key5_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_KEY5_DATA7_SPEC;
 impl crate::RegisterSpec for RD_KEY5_DATA7_SPEC {
diff --git a/esp32s3/src/efuse/rd_mac_spi_sys_0.rs b/esp32s3/src/efuse/rd_mac_spi_sys_0.rs
index 829e8e72f7..6511a28a09 100644
--- a/esp32s3/src/efuse/rd_mac_spi_sys_0.rs
+++ b/esp32s3/src/efuse/rd_mac_spi_sys_0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_0")
-            .field("mac_0", &format_args!("{}", self.mac_0().bits()))
+            .field("mac_0", &self.mac_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_0_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_0_SPEC {
diff --git a/esp32s3/src/efuse/rd_mac_spi_sys_1.rs b/esp32s3/src/efuse/rd_mac_spi_sys_1.rs
index 9256f8c032..4aec88e0e2 100644
--- a/esp32s3/src/efuse/rd_mac_spi_sys_1.rs
+++ b/esp32s3/src/efuse/rd_mac_spi_sys_1.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_1")
-            .field("mac_1", &format_args!("{}", self.mac_1().bits()))
-            .field(
-                "spi_pad_conf_0",
-                &format_args!("{}", self.spi_pad_conf_0().bits()),
-            )
+            .field("mac_1", &self.mac_1())
+            .field("spi_pad_conf_0", &self.spi_pad_conf_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_1_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_1_SPEC {
diff --git a/esp32s3/src/efuse/rd_mac_spi_sys_2.rs b/esp32s3/src/efuse/rd_mac_spi_sys_2.rs
index 7d62025d45..e5df412b3f 100644
--- a/esp32s3/src/efuse/rd_mac_spi_sys_2.rs
+++ b/esp32s3/src/efuse/rd_mac_spi_sys_2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_2")
-            .field(
-                "spi_pad_conf_1",
-                &format_args!("{}", self.spi_pad_conf_1().bits()),
-            )
+            .field("spi_pad_conf_1", &self.spi_pad_conf_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_2_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_2_SPEC {
diff --git a/esp32s3/src/efuse/rd_mac_spi_sys_3.rs b/esp32s3/src/efuse/rd_mac_spi_sys_3.rs
index 89db0e4b65..81936d0f06 100644
--- a/esp32s3/src/efuse/rd_mac_spi_sys_3.rs
+++ b/esp32s3/src/efuse/rd_mac_spi_sys_3.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_3")
-            .field(
-                "spi_pad_conf_2",
-                &format_args!("{}", self.spi_pad_conf_2().bits()),
-            )
-            .field(
-                "sys_data_part0_0",
-                &format_args!("{}", self.sys_data_part0_0().bits()),
-            )
+            .field("spi_pad_conf_2", &self.spi_pad_conf_2())
+            .field("sys_data_part0_0", &self.sys_data_part0_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_3_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_3_SPEC {
diff --git a/esp32s3/src/efuse/rd_mac_spi_sys_4.rs b/esp32s3/src/efuse/rd_mac_spi_sys_4.rs
index e0c07a6c42..27b7fa9845 100644
--- a/esp32s3/src/efuse/rd_mac_spi_sys_4.rs
+++ b/esp32s3/src/efuse/rd_mac_spi_sys_4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_4")
-            .field(
-                "sys_data_part0_1",
-                &format_args!("{}", self.sys_data_part0_1().bits()),
-            )
+            .field("sys_data_part0_1", &self.sys_data_part0_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register 4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_4_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_4_SPEC {
diff --git a/esp32s3/src/efuse/rd_mac_spi_sys_5.rs b/esp32s3/src/efuse/rd_mac_spi_sys_5.rs
index ffcbc45b90..d1cc8adab6 100644
--- a/esp32s3/src/efuse/rd_mac_spi_sys_5.rs
+++ b/esp32s3/src/efuse/rd_mac_spi_sys_5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_MAC_SPI_SYS_5")
-            .field(
-                "sys_data_part0_2",
-                &format_args!("{}", self.sys_data_part0_2().bits()),
-            )
+            .field("sys_data_part0_2", &self.sys_data_part0_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_MAC_SPI_SYS_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK1 data register 5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_mac_spi_sys_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_MAC_SPI_SYS_5_SPEC;
 impl crate::RegisterSpec for RD_MAC_SPI_SYS_5_SPEC {
diff --git a/esp32s3/src/efuse/rd_repeat_data0.rs b/esp32s3/src/efuse/rd_repeat_data0.rs
index eec3ec0799..42c8ec70c0 100644
--- a/esp32s3/src/efuse/rd_repeat_data0.rs
+++ b/esp32s3/src/efuse/rd_repeat_data0.rs
@@ -146,71 +146,32 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA0")
-            .field("rd_dis", &format_args!("{}", self.rd_dis().bits()))
-            .field(
-                "dis_rtc_ram_boot",
-                &format_args!("{}", self.dis_rtc_ram_boot().bit()),
-            )
-            .field("dis_icache", &format_args!("{}", self.dis_icache().bit()))
-            .field("dis_dcache", &format_args!("{}", self.dis_dcache().bit()))
-            .field(
-                "dis_download_icache",
-                &format_args!("{}", self.dis_download_icache().bit()),
-            )
-            .field(
-                "dis_download_dcache",
-                &format_args!("{}", self.dis_download_dcache().bit()),
-            )
-            .field(
-                "dis_force_download",
-                &format_args!("{}", self.dis_force_download().bit()),
-            )
-            .field("dis_usb", &format_args!("{}", self.dis_usb().bit()))
-            .field("dis_can", &format_args!("{}", self.dis_can().bit()))
-            .field("dis_app_cpu", &format_args!("{}", self.dis_app_cpu().bit()))
-            .field(
-                "soft_dis_jtag",
-                &format_args!("{}", self.soft_dis_jtag().bits()),
-            )
-            .field(
-                "dis_pad_jtag",
-                &format_args!("{}", self.dis_pad_jtag().bit()),
-            )
+            .field("rd_dis", &self.rd_dis())
+            .field("dis_rtc_ram_boot", &self.dis_rtc_ram_boot())
+            .field("dis_icache", &self.dis_icache())
+            .field("dis_dcache", &self.dis_dcache())
+            .field("dis_download_icache", &self.dis_download_icache())
+            .field("dis_download_dcache", &self.dis_download_dcache())
+            .field("dis_force_download", &self.dis_force_download())
+            .field("dis_usb", &self.dis_usb())
+            .field("dis_can", &self.dis_can())
+            .field("dis_app_cpu", &self.dis_app_cpu())
+            .field("soft_dis_jtag", &self.soft_dis_jtag())
+            .field("dis_pad_jtag", &self.dis_pad_jtag())
             .field(
                 "dis_download_manual_encrypt",
-                &format_args!("{}", self.dis_download_manual_encrypt().bit()),
-            )
-            .field("usb_drefh", &format_args!("{}", self.usb_drefh().bits()))
-            .field("usb_drefl", &format_args!("{}", self.usb_drefl().bits()))
-            .field(
-                "usb_exchg_pins",
-                &format_args!("{}", self.usb_exchg_pins().bit()),
-            )
-            .field(
-                "ext_phy_enable",
-                &format_args!("{}", self.ext_phy_enable().bit()),
-            )
-            .field(
-                "btlc_gpio_enable",
-                &format_args!("{}", self.btlc_gpio_enable().bits()),
-            )
-            .field(
-                "vdd_spi_modecurlim",
-                &format_args!("{}", self.vdd_spi_modecurlim().bit()),
-            )
-            .field(
-                "vdd_spi_drefh",
-                &format_args!("{}", self.vdd_spi_drefh().bits()),
+                &self.dis_download_manual_encrypt(),
             )
+            .field("usb_drefh", &self.usb_drefh())
+            .field("usb_drefl", &self.usb_drefl())
+            .field("usb_exchg_pins", &self.usb_exchg_pins())
+            .field("ext_phy_enable", &self.ext_phy_enable())
+            .field("btlc_gpio_enable", &self.btlc_gpio_enable())
+            .field("vdd_spi_modecurlim", &self.vdd_spi_modecurlim())
+            .field("vdd_spi_drefh", &self.vdd_spi_drefh())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA0_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA0_SPEC {
diff --git a/esp32s3/src/efuse/rd_repeat_data1.rs b/esp32s3/src/efuse/rd_repeat_data1.rs
index 49e858281c..7af28222c7 100644
--- a/esp32s3/src/efuse/rd_repeat_data1.rs
+++ b/esp32s3/src/efuse/rd_repeat_data1.rs
@@ -125,80 +125,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA1")
-            .field(
-                "vdd_spi_drefm",
-                &format_args!("{}", self.vdd_spi_drefm().bits()),
-            )
-            .field(
-                "vdd_spi_drefl",
-                &format_args!("{}", self.vdd_spi_drefl().bits()),
-            )
-            .field("vdd_spi_xpd", &format_args!("{}", self.vdd_spi_xpd().bit()))
-            .field(
-                "vdd_spi_tieh",
-                &format_args!("{}", self.vdd_spi_tieh().bit()),
-            )
-            .field(
-                "vdd_spi_force",
-                &format_args!("{}", self.vdd_spi_force().bit()),
-            )
-            .field(
-                "vdd_spi_en_init",
-                &format_args!("{}", self.vdd_spi_en_init().bit()),
-            )
-            .field(
-                "vdd_spi_encurlim",
-                &format_args!("{}", self.vdd_spi_encurlim().bit()),
-            )
-            .field(
-                "vdd_spi_dcurlim",
-                &format_args!("{}", self.vdd_spi_dcurlim().bits()),
-            )
-            .field(
-                "vdd_spi_init",
-                &format_args!("{}", self.vdd_spi_init().bits()),
-            )
-            .field(
-                "vdd_spi_dcap",
-                &format_args!("{}", self.vdd_spi_dcap().bits()),
-            )
-            .field(
-                "wdt_delay_sel",
-                &format_args!("{}", self.wdt_delay_sel().bits()),
-            )
-            .field(
-                "spi_boot_crypt_cnt",
-                &format_args!("{}", self.spi_boot_crypt_cnt().bits()),
-            )
-            .field(
-                "secure_boot_key_revoke0",
-                &format_args!("{}", self.secure_boot_key_revoke0().bit()),
-            )
-            .field(
-                "secure_boot_key_revoke1",
-                &format_args!("{}", self.secure_boot_key_revoke1().bit()),
-            )
-            .field(
-                "secure_boot_key_revoke2",
-                &format_args!("{}", self.secure_boot_key_revoke2().bit()),
-            )
-            .field(
-                "key_purpose_0",
-                &format_args!("{}", self.key_purpose_0().bits()),
-            )
-            .field(
-                "key_purpose_1",
-                &format_args!("{}", self.key_purpose_1().bits()),
-            )
+            .field("vdd_spi_drefm", &self.vdd_spi_drefm())
+            .field("vdd_spi_drefl", &self.vdd_spi_drefl())
+            .field("vdd_spi_xpd", &self.vdd_spi_xpd())
+            .field("vdd_spi_tieh", &self.vdd_spi_tieh())
+            .field("vdd_spi_force", &self.vdd_spi_force())
+            .field("vdd_spi_en_init", &self.vdd_spi_en_init())
+            .field("vdd_spi_encurlim", &self.vdd_spi_encurlim())
+            .field("vdd_spi_dcurlim", &self.vdd_spi_dcurlim())
+            .field("vdd_spi_init", &self.vdd_spi_init())
+            .field("vdd_spi_dcap", &self.vdd_spi_dcap())
+            .field("wdt_delay_sel", &self.wdt_delay_sel())
+            .field("spi_boot_crypt_cnt", &self.spi_boot_crypt_cnt())
+            .field("secure_boot_key_revoke0", &self.secure_boot_key_revoke0())
+            .field("secure_boot_key_revoke1", &self.secure_boot_key_revoke1())
+            .field("secure_boot_key_revoke2", &self.secure_boot_key_revoke2())
+            .field("key_purpose_0", &self.key_purpose_0())
+            .field("key_purpose_1", &self.key_purpose_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA1_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA1_SPEC {
diff --git a/esp32s3/src/efuse/rd_repeat_data2.rs b/esp32s3/src/efuse/rd_repeat_data2.rs
index 8a55950dc8..eacfaadaae 100644
--- a/esp32s3/src/efuse/rd_repeat_data2.rs
+++ b/esp32s3/src/efuse/rd_repeat_data2.rs
@@ -97,61 +97,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA2")
-            .field(
-                "key_purpose_2",
-                &format_args!("{}", self.key_purpose_2().bits()),
-            )
-            .field(
-                "key_purpose_3",
-                &format_args!("{}", self.key_purpose_3().bits()),
-            )
-            .field(
-                "key_purpose_4",
-                &format_args!("{}", self.key_purpose_4().bits()),
-            )
-            .field(
-                "key_purpose_5",
-                &format_args!("{}", self.key_purpose_5().bits()),
-            )
-            .field(
-                "rpt4_reserved0",
-                &format_args!("{}", self.rpt4_reserved0().bits()),
-            )
-            .field(
-                "secure_boot_en",
-                &format_args!("{}", self.secure_boot_en().bit()),
-            )
+            .field("key_purpose_2", &self.key_purpose_2())
+            .field("key_purpose_3", &self.key_purpose_3())
+            .field("key_purpose_4", &self.key_purpose_4())
+            .field("key_purpose_5", &self.key_purpose_5())
+            .field("rpt4_reserved0", &self.rpt4_reserved0())
+            .field("secure_boot_en", &self.secure_boot_en())
             .field(
                 "secure_boot_aggressive_revoke",
-                &format_args!("{}", self.secure_boot_aggressive_revoke().bit()),
+                &self.secure_boot_aggressive_revoke(),
             )
-            .field(
-                "dis_usb_jtag",
-                &format_args!("{}", self.dis_usb_jtag().bit()),
-            )
-            .field(
-                "dis_usb_device",
-                &format_args!("{}", self.dis_usb_device().bit()),
-            )
-            .field(
-                "strap_jtag_sel",
-                &format_args!("{}", self.strap_jtag_sel().bit()),
-            )
-            .field("usb_phy_sel", &format_args!("{}", self.usb_phy_sel().bit()))
-            .field(
-                "power_glitch_dsense",
-                &format_args!("{}", self.power_glitch_dsense().bits()),
-            )
-            .field("flash_tpuw", &format_args!("{}", self.flash_tpuw().bits()))
+            .field("dis_usb_jtag", &self.dis_usb_jtag())
+            .field("dis_usb_device", &self.dis_usb_device())
+            .field("strap_jtag_sel", &self.strap_jtag_sel())
+            .field("usb_phy_sel", &self.usb_phy_sel())
+            .field("power_glitch_dsense", &self.power_glitch_dsense())
+            .field("flash_tpuw", &self.flash_tpuw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA2_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA2_SPEC {
diff --git a/esp32s3/src/efuse/rd_repeat_data3.rs b/esp32s3/src/efuse/rd_repeat_data3.rs
index 4955cf4819..7282d588d9 100644
--- a/esp32s3/src/efuse/rd_repeat_data3.rs
+++ b/esp32s3/src/efuse/rd_repeat_data3.rs
@@ -111,72 +111,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA3")
-            .field(
-                "dis_download_mode",
-                &format_args!("{}", self.dis_download_mode().bit()),
-            )
-            .field(
-                "dis_legacy_spi_boot",
-                &format_args!("{}", self.dis_legacy_spi_boot().bit()),
-            )
-            .field(
-                "uart_print_channel",
-                &format_args!("{}", self.uart_print_channel().bit()),
-            )
-            .field(
-                "flash_ecc_mode",
-                &format_args!("{}", self.flash_ecc_mode().bit()),
-            )
-            .field(
-                "dis_usb_download_mode",
-                &format_args!("{}", self.dis_usb_download_mode().bit()),
-            )
-            .field(
-                "enable_security_download",
-                &format_args!("{}", self.enable_security_download().bit()),
-            )
-            .field(
-                "uart_print_control",
-                &format_args!("{}", self.uart_print_control().bits()),
-            )
-            .field(
-                "pin_power_selection",
-                &format_args!("{}", self.pin_power_selection().bit()),
-            )
-            .field("flash_type", &format_args!("{}", self.flash_type().bit()))
-            .field(
-                "flash_page_size",
-                &format_args!("{}", self.flash_page_size().bits()),
-            )
-            .field(
-                "flash_ecc_en",
-                &format_args!("{}", self.flash_ecc_en().bit()),
-            )
-            .field(
-                "force_send_resume",
-                &format_args!("{}", self.force_send_resume().bit()),
-            )
-            .field(
-                "secure_version",
-                &format_args!("{}", self.secure_version().bits()),
-            )
-            .field(
-                "powerglitch_en",
-                &format_args!("{}", self.powerglitch_en().bit()),
-            )
-            .field(
-                "rpt4_reserved1",
-                &format_args!("{}", self.rpt4_reserved1().bit()),
-            )
+            .field("dis_download_mode", &self.dis_download_mode())
+            .field("dis_legacy_spi_boot", &self.dis_legacy_spi_boot())
+            .field("uart_print_channel", &self.uart_print_channel())
+            .field("flash_ecc_mode", &self.flash_ecc_mode())
+            .field("dis_usb_download_mode", &self.dis_usb_download_mode())
+            .field("enable_security_download", &self.enable_security_download())
+            .field("uart_print_control", &self.uart_print_control())
+            .field("pin_power_selection", &self.pin_power_selection())
+            .field("flash_type", &self.flash_type())
+            .field("flash_page_size", &self.flash_page_size())
+            .field("flash_ecc_en", &self.flash_ecc_en())
+            .field("force_send_resume", &self.force_send_resume())
+            .field("secure_version", &self.secure_version())
+            .field("powerglitch_en", &self.powerglitch_en())
+            .field("rpt4_reserved1", &self.rpt4_reserved1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 4.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA3_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA3_SPEC {
diff --git a/esp32s3/src/efuse/rd_repeat_data4.rs b/esp32s3/src/efuse/rd_repeat_data4.rs
index 328d09a48e..3a361d0a90 100644
--- a/esp32s3/src/efuse/rd_repeat_data4.rs
+++ b/esp32s3/src/efuse/rd_repeat_data4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_DATA4")
-            .field(
-                "rpt4_reserved2",
-                &format_args!("{}", self.rpt4_reserved2().bits()),
-            )
+            .field("rpt4_reserved2", &self.rpt4_reserved2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_DATA4_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_DATA4_SPEC {
diff --git a/esp32s3/src/efuse/rd_repeat_err0.rs b/esp32s3/src/efuse/rd_repeat_err0.rs
index eb0e68b6a1..16a6faaf92 100644
--- a/esp32s3/src/efuse/rd_repeat_err0.rs
+++ b/esp32s3/src/efuse/rd_repeat_err0.rs
@@ -146,86 +146,32 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR0")
-            .field("rd_dis_err", &format_args!("{}", self.rd_dis_err().bits()))
-            .field(
-                "dis_rtc_ram_boot_err",
-                &format_args!("{}", self.dis_rtc_ram_boot_err().bit()),
-            )
-            .field(
-                "dis_icache_err",
-                &format_args!("{}", self.dis_icache_err().bit()),
-            )
-            .field(
-                "dis_dcache_err",
-                &format_args!("{}", self.dis_dcache_err().bit()),
-            )
-            .field(
-                "dis_download_icache_err",
-                &format_args!("{}", self.dis_download_icache_err().bit()),
-            )
-            .field(
-                "dis_download_dcache_err",
-                &format_args!("{}", self.dis_download_dcache_err().bit()),
-            )
-            .field(
-                "dis_force_download_err",
-                &format_args!("{}", self.dis_force_download_err().bit()),
-            )
-            .field("dis_usb_err", &format_args!("{}", self.dis_usb_err().bit()))
-            .field("dis_can_err", &format_args!("{}", self.dis_can_err().bit()))
-            .field(
-                "dis_app_cpu_err",
-                &format_args!("{}", self.dis_app_cpu_err().bit()),
-            )
-            .field(
-                "soft_dis_jtag_err",
-                &format_args!("{}", self.soft_dis_jtag_err().bits()),
-            )
-            .field(
-                "dis_pad_jtag_err",
-                &format_args!("{}", self.dis_pad_jtag_err().bit()),
-            )
+            .field("rd_dis_err", &self.rd_dis_err())
+            .field("dis_rtc_ram_boot_err", &self.dis_rtc_ram_boot_err())
+            .field("dis_icache_err", &self.dis_icache_err())
+            .field("dis_dcache_err", &self.dis_dcache_err())
+            .field("dis_download_icache_err", &self.dis_download_icache_err())
+            .field("dis_download_dcache_err", &self.dis_download_dcache_err())
+            .field("dis_force_download_err", &self.dis_force_download_err())
+            .field("dis_usb_err", &self.dis_usb_err())
+            .field("dis_can_err", &self.dis_can_err())
+            .field("dis_app_cpu_err", &self.dis_app_cpu_err())
+            .field("soft_dis_jtag_err", &self.soft_dis_jtag_err())
+            .field("dis_pad_jtag_err", &self.dis_pad_jtag_err())
             .field(
                 "dis_download_manual_encrypt_err",
-                &format_args!("{}", self.dis_download_manual_encrypt_err().bit()),
-            )
-            .field(
-                "usb_drefh_err",
-                &format_args!("{}", self.usb_drefh_err().bits()),
-            )
-            .field(
-                "usb_drefl_err",
-                &format_args!("{}", self.usb_drefl_err().bits()),
-            )
-            .field(
-                "usb_exchg_pins_err",
-                &format_args!("{}", self.usb_exchg_pins_err().bit()),
-            )
-            .field(
-                "ext_phy_enable_err",
-                &format_args!("{}", self.ext_phy_enable_err().bit()),
-            )
-            .field(
-                "btlc_gpio_enable_err",
-                &format_args!("{}", self.btlc_gpio_enable_err().bits()),
-            )
-            .field(
-                "vdd_spi_modecurlim_err",
-                &format_args!("{}", self.vdd_spi_modecurlim_err().bit()),
-            )
-            .field(
-                "vdd_spi_drefh_err",
-                &format_args!("{}", self.vdd_spi_drefh_err().bits()),
-            )
+                &self.dis_download_manual_encrypt_err(),
+            )
+            .field("usb_drefh_err", &self.usb_drefh_err())
+            .field("usb_drefl_err", &self.usb_drefl_err())
+            .field("usb_exchg_pins_err", &self.usb_exchg_pins_err())
+            .field("ext_phy_enable_err", &self.ext_phy_enable_err())
+            .field("btlc_gpio_enable_err", &self.btlc_gpio_enable_err())
+            .field("vdd_spi_modecurlim_err", &self.vdd_spi_modecurlim_err())
+            .field("vdd_spi_drefh_err", &self.vdd_spi_drefh_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 0 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR0_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR0_SPEC {
diff --git a/esp32s3/src/efuse/rd_repeat_err1.rs b/esp32s3/src/efuse/rd_repeat_err1.rs
index 69edcfc920..f72368d73e 100644
--- a/esp32s3/src/efuse/rd_repeat_err1.rs
+++ b/esp32s3/src/efuse/rd_repeat_err1.rs
@@ -125,83 +125,35 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR1")
-            .field(
-                "vdd_spi_drefm_err",
-                &format_args!("{}", self.vdd_spi_drefm_err().bits()),
-            )
-            .field(
-                "vdd_spi_drefl_err",
-                &format_args!("{}", self.vdd_spi_drefl_err().bits()),
-            )
-            .field(
-                "vdd_spi_xpd_err",
-                &format_args!("{}", self.vdd_spi_xpd_err().bit()),
-            )
-            .field(
-                "vdd_spi_tieh_err",
-                &format_args!("{}", self.vdd_spi_tieh_err().bit()),
-            )
-            .field(
-                "vdd_spi_force_err",
-                &format_args!("{}", self.vdd_spi_force_err().bit()),
-            )
-            .field(
-                "vdd_spi_en_init_err",
-                &format_args!("{}", self.vdd_spi_en_init_err().bit()),
-            )
-            .field(
-                "vdd_spi_encurlim_err",
-                &format_args!("{}", self.vdd_spi_encurlim_err().bit()),
-            )
-            .field(
-                "vdd_spi_dcurlim_err",
-                &format_args!("{}", self.vdd_spi_dcurlim_err().bits()),
-            )
-            .field(
-                "vdd_spi_init_err",
-                &format_args!("{}", self.vdd_spi_init_err().bits()),
-            )
-            .field(
-                "vdd_spi_dcap_err",
-                &format_args!("{}", self.vdd_spi_dcap_err().bits()),
-            )
-            .field(
-                "wdt_delay_sel_err",
-                &format_args!("{}", self.wdt_delay_sel_err().bits()),
-            )
-            .field(
-                "spi_boot_crypt_cnt_err",
-                &format_args!("{}", self.spi_boot_crypt_cnt_err().bits()),
-            )
+            .field("vdd_spi_drefm_err", &self.vdd_spi_drefm_err())
+            .field("vdd_spi_drefl_err", &self.vdd_spi_drefl_err())
+            .field("vdd_spi_xpd_err", &self.vdd_spi_xpd_err())
+            .field("vdd_spi_tieh_err", &self.vdd_spi_tieh_err())
+            .field("vdd_spi_force_err", &self.vdd_spi_force_err())
+            .field("vdd_spi_en_init_err", &self.vdd_spi_en_init_err())
+            .field("vdd_spi_encurlim_err", &self.vdd_spi_encurlim_err())
+            .field("vdd_spi_dcurlim_err", &self.vdd_spi_dcurlim_err())
+            .field("vdd_spi_init_err", &self.vdd_spi_init_err())
+            .field("vdd_spi_dcap_err", &self.vdd_spi_dcap_err())
+            .field("wdt_delay_sel_err", &self.wdt_delay_sel_err())
+            .field("spi_boot_crypt_cnt_err", &self.spi_boot_crypt_cnt_err())
             .field(
                 "secure_boot_key_revoke0_err",
-                &format_args!("{}", self.secure_boot_key_revoke0_err().bit()),
+                &self.secure_boot_key_revoke0_err(),
             )
             .field(
                 "secure_boot_key_revoke1_err",
-                &format_args!("{}", self.secure_boot_key_revoke1_err().bit()),
+                &self.secure_boot_key_revoke1_err(),
             )
             .field(
                 "secure_boot_key_revoke2_err",
-                &format_args!("{}", self.secure_boot_key_revoke2_err().bit()),
-            )
-            .field(
-                "key_purpose_0_err",
-                &format_args!("{}", self.key_purpose_0_err().bits()),
-            )
-            .field(
-                "key_purpose_1_err",
-                &format_args!("{}", self.key_purpose_1_err().bits()),
+                &self.secure_boot_key_revoke2_err(),
             )
+            .field("key_purpose_0_err", &self.key_purpose_0_err())
+            .field("key_purpose_1_err", &self.key_purpose_1_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 1 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR1_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR1_SPEC {
diff --git a/esp32s3/src/efuse/rd_repeat_err2.rs b/esp32s3/src/efuse/rd_repeat_err2.rs
index 38b06ff748..d24fb79c7b 100644
--- a/esp32s3/src/efuse/rd_repeat_err2.rs
+++ b/esp32s3/src/efuse/rd_repeat_err2.rs
@@ -97,67 +97,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR2")
-            .field(
-                "key_purpose_2_err",
-                &format_args!("{}", self.key_purpose_2_err().bits()),
-            )
-            .field(
-                "key_purpose_3_err",
-                &format_args!("{}", self.key_purpose_3_err().bits()),
-            )
-            .field(
-                "key_purpose_4_err",
-                &format_args!("{}", self.key_purpose_4_err().bits()),
-            )
-            .field(
-                "key_purpose_5_err",
-                &format_args!("{}", self.key_purpose_5_err().bits()),
-            )
-            .field(
-                "rpt4_reserved0_err",
-                &format_args!("{}", self.rpt4_reserved0_err().bits()),
-            )
-            .field(
-                "secure_boot_en_err",
-                &format_args!("{}", self.secure_boot_en_err().bit()),
-            )
+            .field("key_purpose_2_err", &self.key_purpose_2_err())
+            .field("key_purpose_3_err", &self.key_purpose_3_err())
+            .field("key_purpose_4_err", &self.key_purpose_4_err())
+            .field("key_purpose_5_err", &self.key_purpose_5_err())
+            .field("rpt4_reserved0_err", &self.rpt4_reserved0_err())
+            .field("secure_boot_en_err", &self.secure_boot_en_err())
             .field(
                 "secure_boot_aggressive_revoke_err",
-                &format_args!("{}", self.secure_boot_aggressive_revoke_err().bit()),
-            )
-            .field(
-                "dis_usb_jtag_err",
-                &format_args!("{}", self.dis_usb_jtag_err().bit()),
-            )
-            .field(
-                "dis_usb_device_err",
-                &format_args!("{}", self.dis_usb_device_err().bit()),
-            )
-            .field(
-                "strap_jtag_sel_err",
-                &format_args!("{}", self.strap_jtag_sel_err().bit()),
-            )
-            .field(
-                "usb_phy_sel_err",
-                &format_args!("{}", self.usb_phy_sel_err().bit()),
-            )
-            .field(
-                "power_glitch_dsense_err",
-                &format_args!("{}", self.power_glitch_dsense_err().bits()),
-            )
-            .field(
-                "flash_tpuw_err",
-                &format_args!("{}", self.flash_tpuw_err().bits()),
+                &self.secure_boot_aggressive_revoke_err(),
             )
+            .field("dis_usb_jtag_err", &self.dis_usb_jtag_err())
+            .field("dis_usb_device_err", &self.dis_usb_device_err())
+            .field("strap_jtag_sel_err", &self.strap_jtag_sel_err())
+            .field("usb_phy_sel_err", &self.usb_phy_sel_err())
+            .field("power_glitch_dsense_err", &self.power_glitch_dsense_err())
+            .field("flash_tpuw_err", &self.flash_tpuw_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 2 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR2_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR2_SPEC {
diff --git a/esp32s3/src/efuse/rd_repeat_err3.rs b/esp32s3/src/efuse/rd_repeat_err3.rs
index 8aadded2db..0ec344f0e4 100644
--- a/esp32s3/src/efuse/rd_repeat_err3.rs
+++ b/esp32s3/src/efuse/rd_repeat_err3.rs
@@ -111,75 +111,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR3")
-            .field(
-                "dis_download_mode_err",
-                &format_args!("{}", self.dis_download_mode_err().bit()),
-            )
-            .field(
-                "dis_legacy_spi_boot_err",
-                &format_args!("{}", self.dis_legacy_spi_boot_err().bit()),
-            )
-            .field(
-                "uart_print_channel_err",
-                &format_args!("{}", self.uart_print_channel_err().bit()),
-            )
-            .field(
-                "flash_ecc_mode_err",
-                &format_args!("{}", self.flash_ecc_mode_err().bit()),
-            )
+            .field("dis_download_mode_err", &self.dis_download_mode_err())
+            .field("dis_legacy_spi_boot_err", &self.dis_legacy_spi_boot_err())
+            .field("uart_print_channel_err", &self.uart_print_channel_err())
+            .field("flash_ecc_mode_err", &self.flash_ecc_mode_err())
             .field(
                 "dis_usb_download_mode_err",
-                &format_args!("{}", self.dis_usb_download_mode_err().bit()),
+                &self.dis_usb_download_mode_err(),
             )
             .field(
                 "enable_security_download_err",
-                &format_args!("{}", self.enable_security_download_err().bit()),
-            )
-            .field(
-                "uart_print_control_err",
-                &format_args!("{}", self.uart_print_control_err().bits()),
-            )
-            .field(
-                "pin_power_selection_err",
-                &format_args!("{}", self.pin_power_selection_err().bit()),
-            )
-            .field(
-                "flash_type_err",
-                &format_args!("{}", self.flash_type_err().bit()),
-            )
-            .field(
-                "flash_page_size_err",
-                &format_args!("{}", self.flash_page_size_err().bits()),
-            )
-            .field(
-                "flash_ecc_en_err",
-                &format_args!("{}", self.flash_ecc_en_err().bit()),
-            )
-            .field(
-                "force_send_resume_err",
-                &format_args!("{}", self.force_send_resume_err().bit()),
-            )
-            .field(
-                "secure_version_err",
-                &format_args!("{}", self.secure_version_err().bits()),
-            )
-            .field(
-                "powerglitch_en_err",
-                &format_args!("{}", self.powerglitch_en_err().bit()),
-            )
-            .field(
-                "rpt4_reserved1_err",
-                &format_args!("{}", self.rpt4_reserved1_err().bit()),
+                &self.enable_security_download_err(),
             )
+            .field("uart_print_control_err", &self.uart_print_control_err())
+            .field("pin_power_selection_err", &self.pin_power_selection_err())
+            .field("flash_type_err", &self.flash_type_err())
+            .field("flash_page_size_err", &self.flash_page_size_err())
+            .field("flash_ecc_en_err", &self.flash_ecc_en_err())
+            .field("force_send_resume_err", &self.force_send_resume_err())
+            .field("secure_version_err", &self.secure_version_err())
+            .field("powerglitch_en_err", &self.powerglitch_en_err())
+            .field("rpt4_reserved1_err", &self.rpt4_reserved1_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 3 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR3_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR3_SPEC {
diff --git a/esp32s3/src/efuse/rd_repeat_err4.rs b/esp32s3/src/efuse/rd_repeat_err4.rs
index 178c5ecafd..85f58d8646 100644
--- a/esp32s3/src/efuse/rd_repeat_err4.rs
+++ b/esp32s3/src/efuse/rd_repeat_err4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_REPEAT_ERR4")
-            .field(
-                "rpt4_reserved2_err",
-                &format_args!("{}", self.rpt4_reserved2_err().bits()),
-            )
+            .field("rpt4_reserved2_err", &self.rpt4_reserved2_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_REPEAT_ERR4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 4 of BLOCK0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_repeat_err4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_REPEAT_ERR4_SPEC;
 impl crate::RegisterSpec for RD_REPEAT_ERR4_SPEC {
diff --git a/esp32s3/src/efuse/rd_rs_err0.rs b/esp32s3/src/efuse/rd_rs_err0.rs
index ea7bad6e93..ed5dc386c0 100644
--- a/esp32s3/src/efuse/rd_rs_err0.rs
+++ b/esp32s3/src/efuse/rd_rs_err0.rs
@@ -118,64 +118,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_RS_ERR0")
-            .field(
-                "mac_spi_8m_err_num",
-                &format_args!("{}", self.mac_spi_8m_err_num().bits()),
-            )
-            .field(
-                "mac_spi_8m_fail",
-                &format_args!("{}", self.mac_spi_8m_fail().bit()),
-            )
-            .field(
-                "sys_part1_num",
-                &format_args!("{}", self.sys_part1_num().bits()),
-            )
-            .field(
-                "sys_part1_fail",
-                &format_args!("{}", self.sys_part1_fail().bit()),
-            )
-            .field(
-                "usr_data_err_num",
-                &format_args!("{}", self.usr_data_err_num().bits()),
-            )
-            .field(
-                "usr_data_fail",
-                &format_args!("{}", self.usr_data_fail().bit()),
-            )
-            .field(
-                "key0_err_num",
-                &format_args!("{}", self.key0_err_num().bits()),
-            )
-            .field("key0_fail", &format_args!("{}", self.key0_fail().bit()))
-            .field(
-                "key1_err_num",
-                &format_args!("{}", self.key1_err_num().bits()),
-            )
-            .field("key1_fail", &format_args!("{}", self.key1_fail().bit()))
-            .field(
-                "key2_err_num",
-                &format_args!("{}", self.key2_err_num().bits()),
-            )
-            .field("key2_fail", &format_args!("{}", self.key2_fail().bit()))
-            .field(
-                "key3_err_num",
-                &format_args!("{}", self.key3_err_num().bits()),
-            )
-            .field("key3_fail", &format_args!("{}", self.key3_fail().bit()))
-            .field(
-                "key4_err_num",
-                &format_args!("{}", self.key4_err_num().bits()),
-            )
-            .field("key4_fail", &format_args!("{}", self.key4_fail().bit()))
+            .field("mac_spi_8m_err_num", &self.mac_spi_8m_err_num())
+            .field("mac_spi_8m_fail", &self.mac_spi_8m_fail())
+            .field("sys_part1_num", &self.sys_part1_num())
+            .field("sys_part1_fail", &self.sys_part1_fail())
+            .field("usr_data_err_num", &self.usr_data_err_num())
+            .field("usr_data_fail", &self.usr_data_fail())
+            .field("key0_err_num", &self.key0_err_num())
+            .field("key0_fail", &self.key0_fail())
+            .field("key1_err_num", &self.key1_err_num())
+            .field("key1_fail", &self.key1_fail())
+            .field("key2_err_num", &self.key2_err_num())
+            .field("key2_fail", &self.key2_fail())
+            .field("key3_err_num", &self.key3_err_num())
+            .field("key3_fail", &self.key3_fail())
+            .field("key4_err_num", &self.key4_err_num())
+            .field("key4_fail", &self.key4_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RS_ERR0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 0 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RS_ERR0_SPEC;
 impl crate::RegisterSpec for RD_RS_ERR0_SPEC {
diff --git a/esp32s3/src/efuse/rd_rs_err1.rs b/esp32s3/src/efuse/rd_rs_err1.rs
index 902a43ca7f..66b22ef556 100644
--- a/esp32s3/src/efuse/rd_rs_err1.rs
+++ b/esp32s3/src/efuse/rd_rs_err1.rs
@@ -34,28 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_RS_ERR1")
-            .field(
-                "key5_err_num",
-                &format_args!("{}", self.key5_err_num().bits()),
-            )
-            .field("key5_fail", &format_args!("{}", self.key5_fail().bit()))
-            .field(
-                "sys_part2_err_num",
-                &format_args!("{}", self.sys_part2_err_num().bits()),
-            )
-            .field(
-                "sys_part2_fail",
-                &format_args!("{}", self.sys_part2_fail().bit()),
-            )
+            .field("key5_err_num", &self.key5_err_num())
+            .field("key5_fail", &self.key5_fail())
+            .field("sys_part2_err_num", &self.sys_part2_err_num())
+            .field("sys_part2_fail", &self.sys_part2_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RS_ERR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Programming error record register 1 of BLOCK1-10.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_rs_err1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RS_ERR1_SPEC;
 impl crate::RegisterSpec for RD_RS_ERR1_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part1_data0.rs b/esp32s3/src/efuse/rd_sys_part1_data0.rs
index fd380c93c9..d8f23ea6d5 100644
--- a/esp32s3/src/efuse/rd_sys_part1_data0.rs
+++ b/esp32s3/src/efuse/rd_sys_part1_data0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA0")
-            .field(
-                "sys_data_part1_0",
-                &format_args!("{}", self.sys_data_part1_0().bits()),
-            )
+            .field("sys_data_part1_0", &self.sys_data_part1_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA0_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA0_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part1_data1.rs b/esp32s3/src/efuse/rd_sys_part1_data1.rs
index 36cc24f084..d55067d5f0 100644
--- a/esp32s3/src/efuse/rd_sys_part1_data1.rs
+++ b/esp32s3/src/efuse/rd_sys_part1_data1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA1")
-            .field(
-                "sys_data_part1_1",
-                &format_args!("{}", self.sys_data_part1_1().bits()),
-            )
+            .field("sys_data_part1_1", &self.sys_data_part1_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA1_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA1_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part1_data2.rs b/esp32s3/src/efuse/rd_sys_part1_data2.rs
index 053a53e4ee..dcf911b5a3 100644
--- a/esp32s3/src/efuse/rd_sys_part1_data2.rs
+++ b/esp32s3/src/efuse/rd_sys_part1_data2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA2")
-            .field(
-                "sys_data_part1_2",
-                &format_args!("{}", self.sys_data_part1_2().bits()),
-            )
+            .field("sys_data_part1_2", &self.sys_data_part1_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA2_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA2_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part1_data3.rs b/esp32s3/src/efuse/rd_sys_part1_data3.rs
index d6179df3fb..eaa838b43b 100644
--- a/esp32s3/src/efuse/rd_sys_part1_data3.rs
+++ b/esp32s3/src/efuse/rd_sys_part1_data3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA3")
-            .field(
-                "sys_data_part1_3",
-                &format_args!("{}", self.sys_data_part1_3().bits()),
-            )
+            .field("sys_data_part1_3", &self.sys_data_part1_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA3_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA3_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part1_data4.rs b/esp32s3/src/efuse/rd_sys_part1_data4.rs
index 4a3f06dcd5..623a089550 100644
--- a/esp32s3/src/efuse/rd_sys_part1_data4.rs
+++ b/esp32s3/src/efuse/rd_sys_part1_data4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA4")
-            .field(
-                "sys_data_part1_4",
-                &format_args!("{}", self.sys_data_part1_4().bits()),
-            )
+            .field("sys_data_part1_4", &self.sys_data_part1_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA4_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA4_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part1_data5.rs b/esp32s3/src/efuse/rd_sys_part1_data5.rs
index f78c94865c..c5f8c57f12 100644
--- a/esp32s3/src/efuse/rd_sys_part1_data5.rs
+++ b/esp32s3/src/efuse/rd_sys_part1_data5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA5")
-            .field(
-                "sys_data_part1_5",
-                &format_args!("{}", self.sys_data_part1_5().bits()),
-            )
+            .field("sys_data_part1_5", &self.sys_data_part1_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA5_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA5_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part1_data6.rs b/esp32s3/src/efuse/rd_sys_part1_data6.rs
index 45addd4640..515cd46774 100644
--- a/esp32s3/src/efuse/rd_sys_part1_data6.rs
+++ b/esp32s3/src/efuse/rd_sys_part1_data6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA6")
-            .field(
-                "sys_data_part1_6",
-                &format_args!("{}", self.sys_data_part1_6().bits()),
-            )
+            .field("sys_data_part1_6", &self.sys_data_part1_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA6_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA6_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part1_data7.rs b/esp32s3/src/efuse/rd_sys_part1_data7.rs
index 444f64edf4..82ed838944 100644
--- a/esp32s3/src/efuse/rd_sys_part1_data7.rs
+++ b/esp32s3/src/efuse/rd_sys_part1_data7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART1_DATA7")
-            .field(
-                "sys_data_part1_7",
-                &format_args!("{}", self.sys_data_part1_7().bits()),
-            )
+            .field("sys_data_part1_7", &self.sys_data_part1_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART1_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK2 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part1_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART1_DATA7_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART1_DATA7_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part2_data0.rs b/esp32s3/src/efuse/rd_sys_part2_data0.rs
index d2479c149f..3062fa64da 100644
--- a/esp32s3/src/efuse/rd_sys_part2_data0.rs
+++ b/esp32s3/src/efuse/rd_sys_part2_data0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA0")
-            .field(
-                "sys_data_part2_0",
-                &format_args!("{}", self.sys_data_part2_0().bits()),
-            )
+            .field("sys_data_part2_0", &self.sys_data_part2_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA0_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA0_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part2_data1.rs b/esp32s3/src/efuse/rd_sys_part2_data1.rs
index 7c058b757e..27afe242c7 100644
--- a/esp32s3/src/efuse/rd_sys_part2_data1.rs
+++ b/esp32s3/src/efuse/rd_sys_part2_data1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA1")
-            .field(
-                "sys_data_part2_1",
-                &format_args!("{}", self.sys_data_part2_1().bits()),
-            )
+            .field("sys_data_part2_1", &self.sys_data_part2_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK9 (KEY5).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA1_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA1_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part2_data2.rs b/esp32s3/src/efuse/rd_sys_part2_data2.rs
index 0ace9e8c48..7e396cd4a9 100644
--- a/esp32s3/src/efuse/rd_sys_part2_data2.rs
+++ b/esp32s3/src/efuse/rd_sys_part2_data2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA2")
-            .field(
-                "sys_data_part2_2",
-                &format_args!("{}", self.sys_data_part2_2().bits()),
-            )
+            .field("sys_data_part2_2", &self.sys_data_part2_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA2_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA2_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part2_data3.rs b/esp32s3/src/efuse/rd_sys_part2_data3.rs
index 840a4dcc26..27c19d4b56 100644
--- a/esp32s3/src/efuse/rd_sys_part2_data3.rs
+++ b/esp32s3/src/efuse/rd_sys_part2_data3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA3")
-            .field(
-                "sys_data_part2_3",
-                &format_args!("{}", self.sys_data_part2_3().bits()),
-            )
+            .field("sys_data_part2_3", &self.sys_data_part2_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA3_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA3_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part2_data4.rs b/esp32s3/src/efuse/rd_sys_part2_data4.rs
index 7b765221e6..f7c056a5ed 100644
--- a/esp32s3/src/efuse/rd_sys_part2_data4.rs
+++ b/esp32s3/src/efuse/rd_sys_part2_data4.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA4")
-            .field(
-                "sys_data_part2_4",
-                &format_args!("{}", self.sys_data_part2_4().bits()),
-            )
+            .field("sys_data_part2_4", &self.sys_data_part2_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA4_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA4_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part2_data5.rs b/esp32s3/src/efuse/rd_sys_part2_data5.rs
index e64e6c88cb..49323b99f0 100644
--- a/esp32s3/src/efuse/rd_sys_part2_data5.rs
+++ b/esp32s3/src/efuse/rd_sys_part2_data5.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA5")
-            .field(
-                "sys_data_part2_5",
-                &format_args!("{}", self.sys_data_part2_5().bits()),
-            )
+            .field("sys_data_part2_5", &self.sys_data_part2_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA5_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA5_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part2_data6.rs b/esp32s3/src/efuse/rd_sys_part2_data6.rs
index 152193ce2b..94bdb0430b 100644
--- a/esp32s3/src/efuse/rd_sys_part2_data6.rs
+++ b/esp32s3/src/efuse/rd_sys_part2_data6.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA6")
-            .field(
-                "sys_data_part2_6",
-                &format_args!("{}", self.sys_data_part2_6().bits()),
-            )
+            .field("sys_data_part2_6", &self.sys_data_part2_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA6_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA6_SPEC {
diff --git a/esp32s3/src/efuse/rd_sys_part2_data7.rs b/esp32s3/src/efuse/rd_sys_part2_data7.rs
index 9dba6cb0e1..0d79007131 100644
--- a/esp32s3/src/efuse/rd_sys_part2_data7.rs
+++ b/esp32s3/src/efuse/rd_sys_part2_data7.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_SYS_PART2_DATA7")
-            .field(
-                "sys_data_part2_7",
-                &format_args!("{}", self.sys_data_part2_7().bits()),
-            )
+            .field("sys_data_part2_7", &self.sys_data_part2_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_SYS_PART2_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK10 (system).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_sys_part2_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_SYS_PART2_DATA7_SPEC;
 impl crate::RegisterSpec for RD_SYS_PART2_DATA7_SPEC {
diff --git a/esp32s3/src/efuse/rd_tim_conf.rs b/esp32s3/src/efuse/rd_tim_conf.rs
index 04a800fe3a..f862b2b2b2 100644
--- a/esp32s3/src/efuse/rd_tim_conf.rs
+++ b/esp32s3/src/efuse/rd_tim_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_TIM_CONF")
-            .field(
-                "read_init_num",
-                &format_args!("{}", self.read_init_num().bits()),
-            )
+            .field("read_init_num", &self.read_init_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_TIM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 24:31 - Configures the initial read time of eFuse."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/rd_usr_data0.rs b/esp32s3/src/efuse/rd_usr_data0.rs
index fce5121318..4f54f71ffd 100644
--- a/esp32s3/src/efuse/rd_usr_data0.rs
+++ b/esp32s3/src/efuse/rd_usr_data0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA0")
-            .field("usr_data0", &format_args!("{}", self.usr_data0().bits()))
+            .field("usr_data0", &self.usr_data0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 0 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA0_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA0_SPEC {
diff --git a/esp32s3/src/efuse/rd_usr_data1.rs b/esp32s3/src/efuse/rd_usr_data1.rs
index f85c53cdc2..d95f9d04d8 100644
--- a/esp32s3/src/efuse/rd_usr_data1.rs
+++ b/esp32s3/src/efuse/rd_usr_data1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA1")
-            .field("usr_data1", &format_args!("{}", self.usr_data1().bits()))
+            .field("usr_data1", &self.usr_data1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 1 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA1_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA1_SPEC {
diff --git a/esp32s3/src/efuse/rd_usr_data2.rs b/esp32s3/src/efuse/rd_usr_data2.rs
index 92364c1659..37f85f90d8 100644
--- a/esp32s3/src/efuse/rd_usr_data2.rs
+++ b/esp32s3/src/efuse/rd_usr_data2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA2")
-            .field("usr_data2", &format_args!("{}", self.usr_data2().bits()))
+            .field("usr_data2", &self.usr_data2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 2 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA2_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA2_SPEC {
diff --git a/esp32s3/src/efuse/rd_usr_data3.rs b/esp32s3/src/efuse/rd_usr_data3.rs
index 054770e514..fba0fe4cde 100644
--- a/esp32s3/src/efuse/rd_usr_data3.rs
+++ b/esp32s3/src/efuse/rd_usr_data3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA3")
-            .field("usr_data3", &format_args!("{}", self.usr_data3().bits()))
+            .field("usr_data3", &self.usr_data3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 3 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA3_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA3_SPEC {
diff --git a/esp32s3/src/efuse/rd_usr_data4.rs b/esp32s3/src/efuse/rd_usr_data4.rs
index 46c132fcdc..41942f3a5e 100644
--- a/esp32s3/src/efuse/rd_usr_data4.rs
+++ b/esp32s3/src/efuse/rd_usr_data4.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA4")
-            .field("usr_data4", &format_args!("{}", self.usr_data4().bits()))
+            .field("usr_data4", &self.usr_data4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 4 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA4_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA4_SPEC {
diff --git a/esp32s3/src/efuse/rd_usr_data5.rs b/esp32s3/src/efuse/rd_usr_data5.rs
index f5f463e31d..f1e941203a 100644
--- a/esp32s3/src/efuse/rd_usr_data5.rs
+++ b/esp32s3/src/efuse/rd_usr_data5.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA5")
-            .field("usr_data5", &format_args!("{}", self.usr_data5().bits()))
+            .field("usr_data5", &self.usr_data5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 5 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA5_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA5_SPEC {
diff --git a/esp32s3/src/efuse/rd_usr_data6.rs b/esp32s3/src/efuse/rd_usr_data6.rs
index 8dbf84538d..221b83a84e 100644
--- a/esp32s3/src/efuse/rd_usr_data6.rs
+++ b/esp32s3/src/efuse/rd_usr_data6.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA6")
-            .field("usr_data6", &format_args!("{}", self.usr_data6().bits()))
+            .field("usr_data6", &self.usr_data6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 6 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA6_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA6_SPEC {
diff --git a/esp32s3/src/efuse/rd_usr_data7.rs b/esp32s3/src/efuse/rd_usr_data7.rs
index 3010768b19..3ae6bdeb03 100644
--- a/esp32s3/src/efuse/rd_usr_data7.rs
+++ b/esp32s3/src/efuse/rd_usr_data7.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_USR_DATA7")
-            .field("usr_data7", &format_args!("{}", self.usr_data7().bits()))
+            .field("usr_data7", &self.usr_data7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_USR_DATA7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Register 7 of BLOCK3 (user).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_usr_data7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_USR_DATA7_SPEC;
 impl crate::RegisterSpec for RD_USR_DATA7_SPEC {
diff --git a/esp32s3/src/efuse/rd_wr_dis.rs b/esp32s3/src/efuse/rd_wr_dis.rs
index 606a047d13..badd8bfe7d 100644
--- a/esp32s3/src/efuse/rd_wr_dis.rs
+++ b/esp32s3/src/efuse/rd_wr_dis.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_WR_DIS")
-            .field("wr_dis", &format_args!("{}", self.wr_dis().bits()))
+            .field("wr_dis", &self.wr_dis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_WR_DIS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BLOCK0 data register 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_wr_dis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_WR_DIS_SPEC;
 impl crate::RegisterSpec for RD_WR_DIS_SPEC {
diff --git a/esp32s3/src/efuse/status.rs b/esp32s3/src/efuse/status.rs
index 88ccd0f914..2402480c94 100644
--- a/esp32s3/src/efuse/status.rs
+++ b/esp32s3/src/efuse/status.rs
@@ -62,38 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field("otp_load_sw", &format_args!("{}", self.otp_load_sw().bit()))
-            .field(
-                "otp_vddq_c_sync2",
-                &format_args!("{}", self.otp_vddq_c_sync2().bit()),
-            )
-            .field(
-                "otp_strobe_sw",
-                &format_args!("{}", self.otp_strobe_sw().bit()),
-            )
-            .field("otp_csb_sw", &format_args!("{}", self.otp_csb_sw().bit()))
-            .field(
-                "otp_pgenb_sw",
-                &format_args!("{}", self.otp_pgenb_sw().bit()),
-            )
-            .field(
-                "otp_vddq_is_sw",
-                &format_args!("{}", self.otp_vddq_is_sw().bit()),
-            )
-            .field(
-                "repeat_err_cnt",
-                &format_args!("{}", self.repeat_err_cnt().bits()),
-            )
+            .field("state", &self.state())
+            .field("otp_load_sw", &self.otp_load_sw())
+            .field("otp_vddq_c_sync2", &self.otp_vddq_c_sync2())
+            .field("otp_strobe_sw", &self.otp_strobe_sw())
+            .field("otp_csb_sw", &self.otp_csb_sw())
+            .field("otp_pgenb_sw", &self.otp_pgenb_sw())
+            .field("otp_vddq_is_sw", &self.otp_vddq_is_sw())
+            .field("repeat_err_cnt", &self.repeat_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "eFuse status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32s3/src/efuse/wr_tim_conf1.rs b/esp32s3/src/efuse/wr_tim_conf1.rs
index 7a054569ed..365c73b880 100644
--- a/esp32s3/src/efuse/wr_tim_conf1.rs
+++ b/esp32s3/src/efuse/wr_tim_conf1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF1")
-            .field("pwr_on_num", &format_args!("{}", self.pwr_on_num().bits()))
+            .field("pwr_on_num", &self.pwr_on_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:23 - Configures the power up time for VDDQ."]
     #[inline(always)]
diff --git a/esp32s3/src/efuse/wr_tim_conf2.rs b/esp32s3/src/efuse/wr_tim_conf2.rs
index 8a270afb59..3318449f16 100644
--- a/esp32s3/src/efuse/wr_tim_conf2.rs
+++ b/esp32s3/src/efuse/wr_tim_conf2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WR_TIM_CONF2")
-            .field(
-                "pwr_off_num",
-                &format_args!("{}", self.pwr_off_num().bits()),
-            )
+            .field("pwr_off_num", &self.pwr_off_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_TIM_CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configures the power outage time for VDDQ."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/cache_bridge_arbiter_ctrl.rs b/esp32s3/src/extmem/cache_bridge_arbiter_ctrl.rs
index b5b552472f..acbc6cc3fe 100644
--- a/esp32s3/src/extmem/cache_bridge_arbiter_ctrl.rs
+++ b/esp32s3/src/extmem/cache_bridge_arbiter_ctrl.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_BRIDGE_ARBITER_CTRL")
-            .field(
-                "alloc_wb_hold_arbiter",
-                &format_args!("{}", self.alloc_wb_hold_arbiter().bit()),
-            )
+            .field("alloc_wb_hold_arbiter", &self.alloc_wb_hold_arbiter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_BRIDGE_ARBITER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/cache_conf_misc.rs b/esp32s3/src/extmem/cache_conf_misc.rs
index 481b6dda73..fb3acaf969 100644
--- a/esp32s3/src/extmem/cache_conf_misc.rs
+++ b/esp32s3/src/extmem/cache_conf_misc.rs
@@ -37,25 +37,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("CACHE_CONF_MISC")
             .field(
                 "cache_ignore_preload_mmu_entry_fault",
-                &format_args!("{}", self.cache_ignore_preload_mmu_entry_fault().bit()),
+                &self.cache_ignore_preload_mmu_entry_fault(),
             )
             .field(
                 "cache_ignore_sync_mmu_entry_fault",
-                &format_args!("{}", self.cache_ignore_sync_mmu_entry_fault().bit()),
-            )
-            .field(
-                "cache_trace_ena",
-                &format_args!("{}", self.cache_trace_ena().bit()),
+                &self.cache_ignore_sync_mmu_entry_fault(),
             )
+            .field("cache_trace_ena", &self.cache_trace_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CONF_MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable checking mmu entry fault by preload operation."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/cache_encrypt_decrypt_clk_force_on.rs b/esp32s3/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
index 7f7f86e5db..e3cee79673 100644
--- a/esp32s3/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
+++ b/esp32s3/src/extmem/cache_encrypt_decrypt_clk_force_on.rs
@@ -37,25 +37,13 @@ impl core::fmt::Debug for R {
         f.debug_struct("CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON")
             .field(
                 "clk_force_on_manual_crypt",
-                &format_args!("{}", self.clk_force_on_manual_crypt().bit()),
-            )
-            .field(
-                "clk_force_on_auto_crypt",
-                &format_args!("{}", self.clk_force_on_auto_crypt().bit()),
-            )
-            .field(
-                "clk_force_on_crypt",
-                &format_args!("{}", self.clk_force_on_crypt().bit()),
+                &self.clk_force_on_manual_crypt(),
             )
+            .field("clk_force_on_auto_crypt", &self.clk_force_on_auto_crypt())
+            .field("clk_force_on_crypt", &self.clk_force_on_crypt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/cache_encrypt_decrypt_record_disable.rs b/esp32s3/src/extmem/cache_encrypt_decrypt_record_disable.rs
index 4bce687189..96e8dddc24 100644
--- a/esp32s3/src/extmem/cache_encrypt_decrypt_record_disable.rs
+++ b/esp32s3/src/extmem/cache_encrypt_decrypt_record_disable.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE")
             .field(
                 "record_disable_db_encrypt",
-                &format_args!("{}", self.record_disable_db_encrypt().bit()),
+                &self.record_disable_db_encrypt(),
             )
             .field(
                 "record_disable_g0cb_decrypt",
-                &format_args!("{}", self.record_disable_g0cb_decrypt().bit()),
+                &self.record_disable_g0cb_decrypt(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/cache_ilg_int_ena.rs b/esp32s3/src/extmem/cache_ilg_int_ena.rs
index 9ee58fe117..687d45f149 100644
--- a/esp32s3/src/extmem/cache_ilg_int_ena.rs
+++ b/esp32s3/src/extmem/cache_ilg_int_ena.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_ILG_INT_ENA")
-            .field(
-                "icache_sync_op_fault",
-                &format_args!("{}", self.icache_sync_op_fault().bit()),
-            )
-            .field(
-                "icache_preload_op_fault",
-                &format_args!("{}", self.icache_preload_op_fault().bit()),
-            )
-            .field(
-                "dcache_sync_op_fault",
-                &format_args!("{}", self.dcache_sync_op_fault().bit()),
-            )
-            .field(
-                "dcache_preload_op_fault",
-                &format_args!("{}", self.dcache_preload_op_fault().bit()),
-            )
-            .field(
-                "dcache_write_flash",
-                &format_args!("{}", self.dcache_write_flash().bit()),
-            )
-            .field(
-                "mmu_entry_fault",
-                &format_args!("{}", self.mmu_entry_fault().bit()),
-            )
-            .field(
-                "dcache_occupy_exc",
-                &format_args!("{}", self.dcache_occupy_exc().bit()),
-            )
-            .field(
-                "ibus_cnt_ovf",
-                &format_args!("{}", self.ibus_cnt_ovf().bit()),
-            )
-            .field(
-                "dbus_cnt_ovf",
-                &format_args!("{}", self.dbus_cnt_ovf().bit()),
-            )
+            .field("icache_sync_op_fault", &self.icache_sync_op_fault())
+            .field("icache_preload_op_fault", &self.icache_preload_op_fault())
+            .field("dcache_sync_op_fault", &self.dcache_sync_op_fault())
+            .field("dcache_preload_op_fault", &self.dcache_preload_op_fault())
+            .field("dcache_write_flash", &self.dcache_write_flash())
+            .field("mmu_entry_fault", &self.mmu_entry_fault())
+            .field("dcache_occupy_exc", &self.dcache_occupy_exc())
+            .field("ibus_cnt_ovf", &self.ibus_cnt_ovf())
+            .field("dbus_cnt_ovf", &self.dbus_cnt_ovf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_ILG_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable interrupt by sync configurations fault."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/cache_ilg_int_st.rs b/esp32s3/src/extmem/cache_ilg_int_st.rs
index b74a0c58dc..e22a1c7823 100644
--- a/esp32s3/src/extmem/cache_ilg_int_st.rs
+++ b/esp32s3/src/extmem/cache_ilg_int_st.rs
@@ -90,63 +90,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_ILG_INT_ST")
-            .field(
-                "icache_sync_op_fault",
-                &format_args!("{}", self.icache_sync_op_fault().bit()),
-            )
-            .field(
-                "icache_preload_op_fault",
-                &format_args!("{}", self.icache_preload_op_fault().bit()),
-            )
-            .field(
-                "dcache_sync_op_fault",
-                &format_args!("{}", self.dcache_sync_op_fault().bit()),
-            )
-            .field(
-                "dcache_preload_op_fault",
-                &format_args!("{}", self.dcache_preload_op_fault().bit()),
-            )
-            .field(
-                "dcache_write_flash",
-                &format_args!("{}", self.dcache_write_flash().bit()),
-            )
-            .field(
-                "mmu_entry_fault",
-                &format_args!("{}", self.mmu_entry_fault().bit()),
-            )
-            .field(
-                "dcache_occupy_exc",
-                &format_args!("{}", self.dcache_occupy_exc().bit()),
-            )
-            .field(
-                "ibus_acs_cnt_ovf",
-                &format_args!("{}", self.ibus_acs_cnt_ovf().bit()),
-            )
-            .field(
-                "ibus_acs_miss_cnt_ovf",
-                &format_args!("{}", self.ibus_acs_miss_cnt_ovf().bit()),
-            )
-            .field(
-                "dbus_acs_cnt_ovf",
-                &format_args!("{}", self.dbus_acs_cnt_ovf().bit()),
-            )
+            .field("icache_sync_op_fault", &self.icache_sync_op_fault())
+            .field("icache_preload_op_fault", &self.icache_preload_op_fault())
+            .field("dcache_sync_op_fault", &self.dcache_sync_op_fault())
+            .field("dcache_preload_op_fault", &self.dcache_preload_op_fault())
+            .field("dcache_write_flash", &self.dcache_write_flash())
+            .field("mmu_entry_fault", &self.mmu_entry_fault())
+            .field("dcache_occupy_exc", &self.dcache_occupy_exc())
+            .field("ibus_acs_cnt_ovf", &self.ibus_acs_cnt_ovf())
+            .field("ibus_acs_miss_cnt_ovf", &self.ibus_acs_miss_cnt_ovf())
+            .field("dbus_acs_cnt_ovf", &self.dbus_acs_cnt_ovf())
             .field(
                 "dbus_acs_flash_miss_cnt_ovf",
-                &format_args!("{}", self.dbus_acs_flash_miss_cnt_ovf().bit()),
+                &self.dbus_acs_flash_miss_cnt_ovf(),
             )
             .field(
                 "dbus_acs_spiram_miss_cnt_ovf",
-                &format_args!("{}", self.dbus_acs_spiram_miss_cnt_ovf().bit()),
+                &self.dbus_acs_spiram_miss_cnt_ovf(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_ILG_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_ilg_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_ILG_INT_ST_SPEC;
 impl crate::RegisterSpec for CACHE_ILG_INT_ST_SPEC {
diff --git a/esp32s3/src/extmem/cache_mmu_fault_content.rs b/esp32s3/src/extmem/cache_mmu_fault_content.rs
index 2a9c1e7528..91dcc1052e 100644
--- a/esp32s3/src/extmem/cache_mmu_fault_content.rs
+++ b/esp32s3/src/extmem/cache_mmu_fault_content.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_FAULT_CONTENT")
-            .field(
-                "cache_mmu_fault_content",
-                &format_args!("{}", self.cache_mmu_fault_content().bits()),
-            )
-            .field(
-                "cache_mmu_fault_code",
-                &format_args!("{}", self.cache_mmu_fault_code().bits()),
-            )
+            .field("cache_mmu_fault_content", &self.cache_mmu_fault_content())
+            .field("cache_mmu_fault_code", &self.cache_mmu_fault_code())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_FAULT_CONTENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_mmu_fault_content::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_MMU_FAULT_CONTENT_SPEC;
 impl crate::RegisterSpec for CACHE_MMU_FAULT_CONTENT_SPEC {
diff --git a/esp32s3/src/extmem/cache_mmu_fault_vaddr.rs b/esp32s3/src/extmem/cache_mmu_fault_vaddr.rs
index 09755bf40f..5aa0d6a8bb 100644
--- a/esp32s3/src/extmem/cache_mmu_fault_vaddr.rs
+++ b/esp32s3/src/extmem/cache_mmu_fault_vaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_FAULT_VADDR")
-            .field(
-                "cache_mmu_fault_vaddr",
-                &format_args!("{}", self.cache_mmu_fault_vaddr().bits()),
-            )
+            .field("cache_mmu_fault_vaddr", &self.cache_mmu_fault_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_FAULT_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_mmu_fault_vaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_MMU_FAULT_VADDR_SPEC;
 impl crate::RegisterSpec for CACHE_MMU_FAULT_VADDR_SPEC {
diff --git a/esp32s3/src/extmem/cache_mmu_owner.rs b/esp32s3/src/extmem/cache_mmu_owner.rs
index c55524e194..a54e31c9f9 100644
--- a/esp32s3/src/extmem/cache_mmu_owner.rs
+++ b/esp32s3/src/extmem/cache_mmu_owner.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_OWNER")
-            .field(
-                "cache_mmu_owner",
-                &format_args!("{}", self.cache_mmu_owner().bits()),
-            )
+            .field("cache_mmu_owner", &self.cache_mmu_owner())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_OWNER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/cache_mmu_power_ctrl.rs b/esp32s3/src/extmem/cache_mmu_power_ctrl.rs
index 82c9af3db2..d620358dce 100644
--- a/esp32s3/src/extmem/cache_mmu_power_ctrl.rs
+++ b/esp32s3/src/extmem/cache_mmu_power_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_POWER_CTRL")
-            .field(
-                "cache_mmu_mem_force_on",
-                &format_args!("{}", self.cache_mmu_mem_force_on().bit()),
-            )
-            .field(
-                "cache_mmu_mem_force_pd",
-                &format_args!("{}", self.cache_mmu_mem_force_pd().bit()),
-            )
-            .field(
-                "cache_mmu_mem_force_pu",
-                &format_args!("{}", self.cache_mmu_mem_force_pu().bit()),
-            )
+            .field("cache_mmu_mem_force_on", &self.cache_mmu_mem_force_on())
+            .field("cache_mmu_mem_force_pd", &self.cache_mmu_mem_force_pd())
+            .field("cache_mmu_mem_force_pu", &self.cache_mmu_mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/cache_preload_int_ctrl.rs b/esp32s3/src/extmem/cache_preload_int_ctrl.rs
index ebec0048c6..aa4887e922 100644
--- a/esp32s3/src/extmem/cache_preload_int_ctrl.rs
+++ b/esp32s3/src/extmem/cache_preload_int_ctrl.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_PRELOAD_INT_CTRL")
-            .field("st", &format_args!("{}", self.st().bit()))
-            .field("ena", &format_args!("{}", self.ena().bit()))
-            .field(
-                "dcache_preload_int_st",
-                &format_args!("{}", self.dcache_preload_int_st().bit()),
-            )
-            .field(
-                "dcache_preload_int_ena",
-                &format_args!("{}", self.dcache_preload_int_ena().bit()),
-            )
+            .field("st", &self.st())
+            .field("ena", &self.ena())
+            .field("dcache_preload_int_st", &self.dcache_preload_int_st())
+            .field("dcache_preload_int_ena", &self.dcache_preload_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_PRELOAD_INT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - The bit is used to enable the interrupt by icache pre-load done."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/cache_request.rs b/esp32s3/src/extmem/cache_request.rs
index 2d632d3177..54f3b21b9f 100644
--- a/esp32s3/src/extmem/cache_request.rs
+++ b/esp32s3/src/extmem/cache_request.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_REQUEST")
-            .field("bypass", &format_args!("{}", self.bypass().bit()))
+            .field("bypass", &self.bypass())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_REQUEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable request recording which could cause performance issue"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/cache_state.rs b/esp32s3/src/extmem/cache_state.rs
index 1fa126cae8..5a5b684ddb 100644
--- a/esp32s3/src/extmem/cache_state.rs
+++ b/esp32s3/src/extmem/cache_state.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_STATE")
-            .field(
-                "icache_state",
-                &format_args!("{}", self.icache_state().bits()),
-            )
-            .field(
-                "dcache_state",
-                &format_args!("{}", self.dcache_state().bits()),
-            )
+            .field("icache_state", &self.icache_state())
+            .field("dcache_state", &self.dcache_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CACHE_STATE_SPEC;
 impl crate::RegisterSpec for CACHE_STATE_SPEC {
diff --git a/esp32s3/src/extmem/cache_sync_int_ctrl.rs b/esp32s3/src/extmem/cache_sync_int_ctrl.rs
index 798a28d10f..43c4e22c7a 100644
--- a/esp32s3/src/extmem/cache_sync_int_ctrl.rs
+++ b/esp32s3/src/extmem/cache_sync_int_ctrl.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_SYNC_INT_CTRL")
-            .field("st", &format_args!("{}", self.st().bit()))
-            .field("ena", &format_args!("{}", self.ena().bit()))
-            .field(
-                "dcache_sync_int_st",
-                &format_args!("{}", self.dcache_sync_int_st().bit()),
-            )
-            .field(
-                "dcache_sync_int_ena",
-                &format_args!("{}", self.dcache_sync_int_ena().bit()),
-            )
+            .field("st", &self.st())
+            .field("ena", &self.ena())
+            .field("dcache_sync_int_st", &self.dcache_sync_int_st())
+            .field("dcache_sync_int_ena", &self.dcache_sync_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_SYNC_INT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - The bit is used to enable the interrupt by icache sync done."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/cache_tag_content.rs b/esp32s3/src/extmem/cache_tag_content.rs
index 25dc6a082a..1680015de3 100644
--- a/esp32s3/src/extmem/cache_tag_content.rs
+++ b/esp32s3/src/extmem/cache_tag_content.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_TAG_CONTENT")
-            .field(
-                "cache_tag_content",
-                &format_args!("{}", self.cache_tag_content().bits()),
-            )
+            .field("cache_tag_content", &self.cache_tag_content())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_TAG_CONTENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This is a constant place where we can write data to or read data from the tag memory on the specified cache."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/cache_tag_object_ctrl.rs b/esp32s3/src/extmem/cache_tag_object_ctrl.rs
index 276455f562..3a0d0da4dd 100644
--- a/esp32s3/src/extmem/cache_tag_object_ctrl.rs
+++ b/esp32s3/src/extmem/cache_tag_object_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_TAG_OBJECT_CTRL")
-            .field(
-                "icache_tag_object",
-                &format_args!("{}", self.icache_tag_object().bit()),
-            )
-            .field(
-                "dcache_tag_object",
-                &format_args!("{}", self.dcache_tag_object().bit()),
-            )
+            .field("icache_tag_object", &self.icache_tag_object())
+            .field("dcache_tag_object", &self.dcache_tag_object())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_TAG_OBJECT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/cache_tag_way_object.rs b/esp32s3/src/extmem/cache_tag_way_object.rs
index 2911382cc0..0d5f4b8b62 100644
--- a/esp32s3/src/extmem/cache_tag_way_object.rs
+++ b/esp32s3/src/extmem/cache_tag_way_object.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_TAG_WAY_OBJECT")
-            .field(
-                "cache_tag_way_object",
-                &format_args!("{}", self.cache_tag_way_object().bits()),
-            )
+            .field("cache_tag_way_object", &self.cache_tag_way_object())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_TAG_WAY_OBJECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/cache_vaddr.rs b/esp32s3/src/extmem/cache_vaddr.rs
index ca2d2ce1e4..1605e4c74c 100644
--- a/esp32s3/src/extmem/cache_vaddr.rs
+++ b/esp32s3/src/extmem/cache_vaddr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_VADDR")
-            .field(
-                "cache_vaddr",
-                &format_args!("{}", self.cache_vaddr().bits()),
-            )
+            .field("cache_vaddr", &self.cache_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/cache_wrap_around_ctrl.rs b/esp32s3/src/extmem/cache_wrap_around_ctrl.rs
index 87cacea39a..fff38a580f 100644
--- a/esp32s3/src/extmem/cache_wrap_around_ctrl.rs
+++ b/esp32s3/src/extmem/cache_wrap_around_ctrl.rs
@@ -26,23 +26,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_WRAP_AROUND_CTRL")
-            .field(
-                "cache_flash_wrap_around",
-                &format_args!("{}", self.cache_flash_wrap_around().bit()),
-            )
+            .field("cache_flash_wrap_around", &self.cache_flash_wrap_around())
             .field(
                 "cache_sram_rd_wrap_around",
-                &format_args!("{}", self.cache_sram_rd_wrap_around().bit()),
+                &self.cache_sram_rd_wrap_around(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_WRAP_AROUND_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable wrap around mode when read data from flash."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/clock_gate.rs b/esp32s3/src/extmem/clock_gate.rs
index aa3743d3c2..9c72b46a81 100644
--- a/esp32s3/src/extmem/clock_gate.rs
+++ b/esp32s3/src/extmem/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Reserved"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/core0_acs_cache_int_ena.rs b/esp32s3/src/extmem/core0_acs_cache_int_ena.rs
index 45873b4c1c..1459782b8e 100644
--- a/esp32s3/src/extmem/core0_acs_cache_int_ena.rs
+++ b/esp32s3/src/extmem/core0_acs_cache_int_ena.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE0_ACS_CACHE_INT_ENA")
-            .field(
-                "core0_ibus_acs_msk_ic",
-                &format_args!("{}", self.core0_ibus_acs_msk_ic().bit()),
-            )
-            .field(
-                "core0_ibus_wr_ic",
-                &format_args!("{}", self.core0_ibus_wr_ic().bit()),
-            )
-            .field(
-                "core0_ibus_reject",
-                &format_args!("{}", self.core0_ibus_reject().bit()),
-            )
-            .field(
-                "core0_dbus_acs_msk_dc",
-                &format_args!("{}", self.core0_dbus_acs_msk_dc().bit()),
-            )
-            .field(
-                "core0_dbus_reject",
-                &format_args!("{}", self.core0_dbus_reject().bit()),
-            )
+            .field("core0_ibus_acs_msk_ic", &self.core0_ibus_acs_msk_ic())
+            .field("core0_ibus_wr_ic", &self.core0_ibus_wr_ic())
+            .field("core0_ibus_reject", &self.core0_ibus_reject())
+            .field("core0_dbus_acs_msk_dc", &self.core0_dbus_acs_msk_dc())
+            .field("core0_dbus_reject", &self.core0_dbus_reject())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_ACS_CACHE_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/core0_acs_cache_int_st.rs b/esp32s3/src/extmem/core0_acs_cache_int_st.rs
index 3b48bff84d..04f4d24bbf 100644
--- a/esp32s3/src/extmem/core0_acs_cache_int_st.rs
+++ b/esp32s3/src/extmem/core0_acs_cache_int_st.rs
@@ -43,33 +43,18 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE0_ACS_CACHE_INT_ST")
             .field(
                 "core0_ibus_acs_msk_icache",
-                &format_args!("{}", self.core0_ibus_acs_msk_icache().bit()),
-            )
-            .field(
-                "core0_ibus_wr_icache",
-                &format_args!("{}", self.core0_ibus_wr_icache().bit()),
-            )
-            .field(
-                "core0_ibus_reject",
-                &format_args!("{}", self.core0_ibus_reject().bit()),
+                &self.core0_ibus_acs_msk_icache(),
             )
+            .field("core0_ibus_wr_icache", &self.core0_ibus_wr_icache())
+            .field("core0_ibus_reject", &self.core0_ibus_reject())
             .field(
                 "core0_dbus_acs_msk_dcache",
-                &format_args!("{}", self.core0_dbus_acs_msk_dcache().bit()),
-            )
-            .field(
-                "core0_dbus_reject",
-                &format_args!("{}", self.core0_dbus_reject().bit()),
+                &self.core0_dbus_acs_msk_dcache(),
             )
+            .field("core0_dbus_reject", &self.core0_dbus_reject())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_ACS_CACHE_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_acs_cache_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE0_ACS_CACHE_INT_ST_SPEC;
 impl crate::RegisterSpec for CORE0_ACS_CACHE_INT_ST_SPEC {
diff --git a/esp32s3/src/extmem/core0_dbus_reject_st.rs b/esp32s3/src/extmem/core0_dbus_reject_st.rs
index 7529ef2882..4dfa0f12ea 100644
--- a/esp32s3/src/extmem/core0_dbus_reject_st.rs
+++ b/esp32s3/src/extmem/core0_dbus_reject_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE0_DBUS_REJECT_ST")
-            .field(
-                "core0_dbus_tag_attr",
-                &format_args!("{}", self.core0_dbus_tag_attr().bits()),
-            )
-            .field(
-                "core0_dbus_attr",
-                &format_args!("{}", self.core0_dbus_attr().bits()),
-            )
-            .field(
-                "core0_dbus_world",
-                &format_args!("{}", self.core0_dbus_world().bit()),
-            )
+            .field("core0_dbus_tag_attr", &self.core0_dbus_tag_attr())
+            .field("core0_dbus_attr", &self.core0_dbus_attr())
+            .field("core0_dbus_world", &self.core0_dbus_world())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_DBUS_REJECT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_dbus_reject_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE0_DBUS_REJECT_ST_SPEC;
 impl crate::RegisterSpec for CORE0_DBUS_REJECT_ST_SPEC {
diff --git a/esp32s3/src/extmem/core0_dbus_reject_vaddr.rs b/esp32s3/src/extmem/core0_dbus_reject_vaddr.rs
index 92f70ef455..3e46184e2c 100644
--- a/esp32s3/src/extmem/core0_dbus_reject_vaddr.rs
+++ b/esp32s3/src/extmem/core0_dbus_reject_vaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE0_DBUS_REJECT_VADDR")
-            .field(
-                "core0_dbus_vaddr",
-                &format_args!("{}", self.core0_dbus_vaddr().bits()),
-            )
+            .field("core0_dbus_vaddr", &self.core0_dbus_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_DBUS_REJECT_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_dbus_reject_vaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE0_DBUS_REJECT_VADDR_SPEC;
 impl crate::RegisterSpec for CORE0_DBUS_REJECT_VADDR_SPEC {
diff --git a/esp32s3/src/extmem/core0_ibus_reject_st.rs b/esp32s3/src/extmem/core0_ibus_reject_st.rs
index e8050bc0d2..ad9562f955 100644
--- a/esp32s3/src/extmem/core0_ibus_reject_st.rs
+++ b/esp32s3/src/extmem/core0_ibus_reject_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE0_IBUS_REJECT_ST")
-            .field(
-                "core0_ibus_tag_attr",
-                &format_args!("{}", self.core0_ibus_tag_attr().bits()),
-            )
-            .field(
-                "core0_ibus_attr",
-                &format_args!("{}", self.core0_ibus_attr().bits()),
-            )
-            .field(
-                "core0_ibus_world",
-                &format_args!("{}", self.core0_ibus_world().bit()),
-            )
+            .field("core0_ibus_tag_attr", &self.core0_ibus_tag_attr())
+            .field("core0_ibus_attr", &self.core0_ibus_attr())
+            .field("core0_ibus_world", &self.core0_ibus_world())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_IBUS_REJECT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_ibus_reject_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE0_IBUS_REJECT_ST_SPEC;
 impl crate::RegisterSpec for CORE0_IBUS_REJECT_ST_SPEC {
diff --git a/esp32s3/src/extmem/core0_ibus_reject_vaddr.rs b/esp32s3/src/extmem/core0_ibus_reject_vaddr.rs
index d722e89adb..be30b18b1f 100644
--- a/esp32s3/src/extmem/core0_ibus_reject_vaddr.rs
+++ b/esp32s3/src/extmem/core0_ibus_reject_vaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE0_IBUS_REJECT_VADDR")
-            .field(
-                "core0_ibus_vaddr",
-                &format_args!("{}", self.core0_ibus_vaddr().bits()),
-            )
+            .field("core0_ibus_vaddr", &self.core0_ibus_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE0_IBUS_REJECT_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core0_ibus_reject_vaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE0_IBUS_REJECT_VADDR_SPEC;
 impl crate::RegisterSpec for CORE0_IBUS_REJECT_VADDR_SPEC {
diff --git a/esp32s3/src/extmem/core1_acs_cache_int_ena.rs b/esp32s3/src/extmem/core1_acs_cache_int_ena.rs
index 2682e6a9aa..53620415d1 100644
--- a/esp32s3/src/extmem/core1_acs_cache_int_ena.rs
+++ b/esp32s3/src/extmem/core1_acs_cache_int_ena.rs
@@ -55,33 +55,24 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE1_ACS_CACHE_INT_ENA")
             .field(
                 "core1_ibus_acs_msk_ic_int_ena",
-                &format_args!("{}", self.core1_ibus_acs_msk_ic_int_ena().bit()),
-            )
-            .field(
-                "core1_ibus_wr_ic_int_ena",
-                &format_args!("{}", self.core1_ibus_wr_ic_int_ena().bit()),
+                &self.core1_ibus_acs_msk_ic_int_ena(),
             )
+            .field("core1_ibus_wr_ic_int_ena", &self.core1_ibus_wr_ic_int_ena())
             .field(
                 "core1_ibus_reject_int_ena",
-                &format_args!("{}", self.core1_ibus_reject_int_ena().bit()),
+                &self.core1_ibus_reject_int_ena(),
             )
             .field(
                 "core1_dbus_acs_msk_dc_int_ena",
-                &format_args!("{}", self.core1_dbus_acs_msk_dc_int_ena().bit()),
+                &self.core1_dbus_acs_msk_dc_int_ena(),
             )
             .field(
                 "core1_dbus_reject_int_ena",
-                &format_args!("{}", self.core1_dbus_reject_int_ena().bit()),
+                &self.core1_dbus_reject_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE1_ACS_CACHE_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/core1_acs_cache_int_st.rs b/esp32s3/src/extmem/core1_acs_cache_int_st.rs
index d04b878dab..7b607af003 100644
--- a/esp32s3/src/extmem/core1_acs_cache_int_st.rs
+++ b/esp32s3/src/extmem/core1_acs_cache_int_st.rs
@@ -43,33 +43,18 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE1_ACS_CACHE_INT_ST")
             .field(
                 "core1_ibus_acs_msk_icache_st",
-                &format_args!("{}", self.core1_ibus_acs_msk_icache_st().bit()),
-            )
-            .field(
-                "core1_ibus_wr_icache_st",
-                &format_args!("{}", self.core1_ibus_wr_icache_st().bit()),
-            )
-            .field(
-                "core1_ibus_reject_st",
-                &format_args!("{}", self.core1_ibus_reject_st().bit()),
+                &self.core1_ibus_acs_msk_icache_st(),
             )
+            .field("core1_ibus_wr_icache_st", &self.core1_ibus_wr_icache_st())
+            .field("core1_ibus_reject_st", &self.core1_ibus_reject_st())
             .field(
                 "core1_dbus_acs_msk_dcache_st",
-                &format_args!("{}", self.core1_dbus_acs_msk_dcache_st().bit()),
-            )
-            .field(
-                "core1_dbus_reject_st",
-                &format_args!("{}", self.core1_dbus_reject_st().bit()),
+                &self.core1_dbus_acs_msk_dcache_st(),
             )
+            .field("core1_dbus_reject_st", &self.core1_dbus_reject_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE1_ACS_CACHE_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core1_acs_cache_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE1_ACS_CACHE_INT_ST_SPEC;
 impl crate::RegisterSpec for CORE1_ACS_CACHE_INT_ST_SPEC {
diff --git a/esp32s3/src/extmem/core1_dbus_reject_st.rs b/esp32s3/src/extmem/core1_dbus_reject_st.rs
index 151a5f97b1..0419f3d0bb 100644
--- a/esp32s3/src/extmem/core1_dbus_reject_st.rs
+++ b/esp32s3/src/extmem/core1_dbus_reject_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE1_DBUS_REJECT_ST")
-            .field(
-                "core1_dbus_tag_attr",
-                &format_args!("{}", self.core1_dbus_tag_attr().bits()),
-            )
-            .field(
-                "core1_dbus_attr",
-                &format_args!("{}", self.core1_dbus_attr().bits()),
-            )
-            .field(
-                "core1_dbus_world",
-                &format_args!("{}", self.core1_dbus_world().bit()),
-            )
+            .field("core1_dbus_tag_attr", &self.core1_dbus_tag_attr())
+            .field("core1_dbus_attr", &self.core1_dbus_attr())
+            .field("core1_dbus_world", &self.core1_dbus_world())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE1_DBUS_REJECT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core1_dbus_reject_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE1_DBUS_REJECT_ST_SPEC;
 impl crate::RegisterSpec for CORE1_DBUS_REJECT_ST_SPEC {
diff --git a/esp32s3/src/extmem/core1_dbus_reject_vaddr.rs b/esp32s3/src/extmem/core1_dbus_reject_vaddr.rs
index ce3dfb724b..a6b9faefff 100644
--- a/esp32s3/src/extmem/core1_dbus_reject_vaddr.rs
+++ b/esp32s3/src/extmem/core1_dbus_reject_vaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE1_DBUS_REJECT_VADDR")
-            .field(
-                "core1_dbus_vaddr",
-                &format_args!("{}", self.core1_dbus_vaddr().bits()),
-            )
+            .field("core1_dbus_vaddr", &self.core1_dbus_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE1_DBUS_REJECT_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core1_dbus_reject_vaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE1_DBUS_REJECT_VADDR_SPEC;
 impl crate::RegisterSpec for CORE1_DBUS_REJECT_VADDR_SPEC {
diff --git a/esp32s3/src/extmem/core1_ibus_reject_st.rs b/esp32s3/src/extmem/core1_ibus_reject_st.rs
index 1fc33963ad..2041f02240 100644
--- a/esp32s3/src/extmem/core1_ibus_reject_st.rs
+++ b/esp32s3/src/extmem/core1_ibus_reject_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE1_IBUS_REJECT_ST")
-            .field(
-                "core1_ibus_tag_attr",
-                &format_args!("{}", self.core1_ibus_tag_attr().bits()),
-            )
-            .field(
-                "core1_ibus_attr",
-                &format_args!("{}", self.core1_ibus_attr().bits()),
-            )
-            .field(
-                "core1_ibus_world",
-                &format_args!("{}", self.core1_ibus_world().bit()),
-            )
+            .field("core1_ibus_tag_attr", &self.core1_ibus_tag_attr())
+            .field("core1_ibus_attr", &self.core1_ibus_attr())
+            .field("core1_ibus_world", &self.core1_ibus_world())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE1_IBUS_REJECT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core1_ibus_reject_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE1_IBUS_REJECT_ST_SPEC;
 impl crate::RegisterSpec for CORE1_IBUS_REJECT_ST_SPEC {
diff --git a/esp32s3/src/extmem/core1_ibus_reject_vaddr.rs b/esp32s3/src/extmem/core1_ibus_reject_vaddr.rs
index 5ff427e6df..40c5d7659c 100644
--- a/esp32s3/src/extmem/core1_ibus_reject_vaddr.rs
+++ b/esp32s3/src/extmem/core1_ibus_reject_vaddr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE1_IBUS_REJECT_VADDR")
-            .field(
-                "core1_ibus_vaddr",
-                &format_args!("{}", self.core1_ibus_vaddr().bits()),
-            )
+            .field("core1_ibus_vaddr", &self.core1_ibus_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE1_IBUS_REJECT_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core1_ibus_reject_vaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE1_IBUS_REJECT_VADDR_SPEC;
 impl crate::RegisterSpec for CORE1_IBUS_REJECT_VADDR_SPEC {
diff --git a/esp32s3/src/extmem/date.rs b/esp32s3/src/extmem/date.rs
index 341cf438f1..de3ba6acb7 100644
--- a/esp32s3/src/extmem/date.rs
+++ b/esp32s3/src/extmem/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/extmem/dbus_acs_cnt.rs b/esp32s3/src/extmem/dbus_acs_cnt.rs
index 94157cf1dc..1abc05ddb3 100644
--- a/esp32s3/src/extmem/dbus_acs_cnt.rs
+++ b/esp32s3/src/extmem/dbus_acs_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS_ACS_CNT")
-            .field(
-                "dbus_acs_cnt",
-                &format_args!("{}", self.dbus_acs_cnt().bits()),
-            )
+            .field("dbus_acs_cnt", &self.dbus_acs_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_ACS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus_acs_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS_ACS_CNT_SPEC;
 impl crate::RegisterSpec for DBUS_ACS_CNT_SPEC {
diff --git a/esp32s3/src/extmem/dbus_acs_flash_miss_cnt.rs b/esp32s3/src/extmem/dbus_acs_flash_miss_cnt.rs
index af339b1f30..b61ca02974 100644
--- a/esp32s3/src/extmem/dbus_acs_flash_miss_cnt.rs
+++ b/esp32s3/src/extmem/dbus_acs_flash_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS_ACS_FLASH_MISS_CNT")
-            .field(
-                "dbus_acs_flash_miss_cnt",
-                &format_args!("{}", self.dbus_acs_flash_miss_cnt().bits()),
-            )
+            .field("dbus_acs_flash_miss_cnt", &self.dbus_acs_flash_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_ACS_FLASH_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus_acs_flash_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS_ACS_FLASH_MISS_CNT_SPEC;
 impl crate::RegisterSpec for DBUS_ACS_FLASH_MISS_CNT_SPEC {
diff --git a/esp32s3/src/extmem/dbus_acs_spiram_miss_cnt.rs b/esp32s3/src/extmem/dbus_acs_spiram_miss_cnt.rs
index 0d53728e11..4f7fbb426f 100644
--- a/esp32s3/src/extmem/dbus_acs_spiram_miss_cnt.rs
+++ b/esp32s3/src/extmem/dbus_acs_spiram_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS_ACS_SPIRAM_MISS_CNT")
-            .field(
-                "dbus_acs_spiram_miss_cnt",
-                &format_args!("{}", self.dbus_acs_spiram_miss_cnt().bits()),
-            )
+            .field("dbus_acs_spiram_miss_cnt", &self.dbus_acs_spiram_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_ACS_SPIRAM_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbus_acs_spiram_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DBUS_ACS_SPIRAM_MISS_CNT_SPEC;
 impl crate::RegisterSpec for DBUS_ACS_SPIRAM_MISS_CNT_SPEC {
diff --git a/esp32s3/src/extmem/dbus_to_flash_end_vaddr.rs b/esp32s3/src/extmem/dbus_to_flash_end_vaddr.rs
index da7ad0b7aa..dfaa57744f 100644
--- a/esp32s3/src/extmem/dbus_to_flash_end_vaddr.rs
+++ b/esp32s3/src/extmem/dbus_to_flash_end_vaddr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBUS_TO_FLASH_END_VADDR")
-            .field(
-                "dbus_to_flash_end_vaddr",
-                &format_args!("{}", self.dbus_to_flash_end_vaddr().bits()),
-            )
+            .field("dbus_to_flash_end_vaddr", &self.dbus_to_flash_end_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_TO_FLASH_END_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dbus_to_flash_start_vaddr.rs b/esp32s3/src/extmem/dbus_to_flash_start_vaddr.rs
index 07464cf4b1..20cac2c21c 100644
--- a/esp32s3/src/extmem/dbus_to_flash_start_vaddr.rs
+++ b/esp32s3/src/extmem/dbus_to_flash_start_vaddr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DBUS_TO_FLASH_START_VADDR")
             .field(
                 "dbus_to_flash_start_vaddr",
-                &format_args!("{}", self.dbus_to_flash_start_vaddr().bits()),
+                &self.dbus_to_flash_start_vaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBUS_TO_FLASH_START_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_atomic_operate_ena.rs b/esp32s3/src/extmem/dcache_atomic_operate_ena.rs
index 6d1134681a..96e3617255 100644
--- a/esp32s3/src/extmem/dcache_atomic_operate_ena.rs
+++ b/esp32s3/src/extmem/dcache_atomic_operate_ena.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DCACHE_ATOMIC_OPERATE_ENA")
             .field(
                 "dcache_atomic_operate_ena",
-                &format_args!("{}", self.dcache_atomic_operate_ena().bit()),
+                &self.dcache_atomic_operate_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_ATOMIC_OPERATE_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_autoload_ctrl.rs b/esp32s3/src/extmem/dcache_autoload_ctrl.rs
index 5d8f22bcb6..3f7acae717 100644
--- a/esp32s3/src/extmem/dcache_autoload_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_autoload_ctrl.rs
@@ -78,47 +78,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_AUTOLOAD_CTRL")
-            .field(
-                "dcache_autoload_sct0_ena",
-                &format_args!("{}", self.dcache_autoload_sct0_ena().bit()),
-            )
-            .field(
-                "dcache_autoload_sct1_ena",
-                &format_args!("{}", self.dcache_autoload_sct1_ena().bit()),
-            )
-            .field(
-                "dcache_autoload_ena",
-                &format_args!("{}", self.dcache_autoload_ena().bit()),
-            )
-            .field(
-                "dcache_autoload_done",
-                &format_args!("{}", self.dcache_autoload_done().bit()),
-            )
-            .field(
-                "dcache_autoload_order",
-                &format_args!("{}", self.dcache_autoload_order().bit()),
-            )
-            .field(
-                "dcache_autoload_rqst",
-                &format_args!("{}", self.dcache_autoload_rqst().bits()),
-            )
-            .field(
-                "dcache_autoload_size",
-                &format_args!("{}", self.dcache_autoload_size().bits()),
-            )
+            .field("dcache_autoload_sct0_ena", &self.dcache_autoload_sct0_ena())
+            .field("dcache_autoload_sct1_ena", &self.dcache_autoload_sct1_ena())
+            .field("dcache_autoload_ena", &self.dcache_autoload_ena())
+            .field("dcache_autoload_done", &self.dcache_autoload_done())
+            .field("dcache_autoload_order", &self.dcache_autoload_order())
+            .field("dcache_autoload_rqst", &self.dcache_autoload_rqst())
+            .field("dcache_autoload_size", &self.dcache_autoload_size())
             .field(
                 "dcache_autoload_buffer_clear",
-                &format_args!("{}", self.dcache_autoload_buffer_clear().bit()),
+                &self.dcache_autoload_buffer_clear(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_AUTOLOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bits are used to enable the first section for autoload operation."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_autoload_sct0_addr.rs b/esp32s3/src/extmem/dcache_autoload_sct0_addr.rs
index 6b548dc37f..392ae1bbf6 100644
--- a/esp32s3/src/extmem/dcache_autoload_sct0_addr.rs
+++ b/esp32s3/src/extmem/dcache_autoload_sct0_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DCACHE_AUTOLOAD_SCT0_ADDR")
             .field(
                 "dcache_autoload_sct0_addr",
-                &format_args!("{}", self.dcache_autoload_sct0_addr().bits()),
+                &self.dcache_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_AUTOLOAD_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_autoload_sct0_size.rs b/esp32s3/src/extmem/dcache_autoload_sct0_size.rs
index 76d3f2f5e2..b4f7b9f9c0 100644
--- a/esp32s3/src/extmem/dcache_autoload_sct0_size.rs
+++ b/esp32s3/src/extmem/dcache_autoload_sct0_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DCACHE_AUTOLOAD_SCT0_SIZE")
             .field(
                 "dcache_autoload_sct0_size",
-                &format_args!("{}", self.dcache_autoload_sct0_size().bits()),
+                &self.dcache_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_AUTOLOAD_SCT0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:26 - The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_autoload_sct1_addr.rs b/esp32s3/src/extmem/dcache_autoload_sct1_addr.rs
index b70dec1735..e30e134eea 100644
--- a/esp32s3/src/extmem/dcache_autoload_sct1_addr.rs
+++ b/esp32s3/src/extmem/dcache_autoload_sct1_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DCACHE_AUTOLOAD_SCT1_ADDR")
             .field(
                 "dcache_autoload_sct1_addr",
-                &format_args!("{}", self.dcache_autoload_sct1_addr().bits()),
+                &self.dcache_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_AUTOLOAD_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_autoload_sct1_size.rs b/esp32s3/src/extmem/dcache_autoload_sct1_size.rs
index de7b0339bb..ea58277cc0 100644
--- a/esp32s3/src/extmem/dcache_autoload_sct1_size.rs
+++ b/esp32s3/src/extmem/dcache_autoload_sct1_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DCACHE_AUTOLOAD_SCT1_SIZE")
             .field(
                 "dcache_autoload_sct1_size",
-                &format_args!("{}", self.dcache_autoload_sct1_size().bits()),
+                &self.dcache_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_AUTOLOAD_SCT1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:26 - The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_ctrl.rs b/esp32s3/src/extmem/dcache_ctrl.rs
index fb99f4ed6d..a1a2c2c6b7 100644
--- a/esp32s3/src/extmem/dcache_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_CTRL")
-            .field(
-                "dcache_enable",
-                &format_args!("{}", self.dcache_enable().bit()),
-            )
-            .field(
-                "dcache_size_mode",
-                &format_args!("{}", self.dcache_size_mode().bit()),
-            )
-            .field(
-                "dcache_blocksize_mode",
-                &format_args!("{}", self.dcache_blocksize_mode().bits()),
-            )
+            .field("dcache_enable", &self.dcache_enable())
+            .field("dcache_size_mode", &self.dcache_size_mode())
+            .field("dcache_blocksize_mode", &self.dcache_blocksize_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_ctrl1.rs b/esp32s3/src/extmem/dcache_ctrl1.rs
index 588d50b7c1..b71c6f25e2 100644
--- a/esp32s3/src/extmem/dcache_ctrl1.rs
+++ b/esp32s3/src/extmem/dcache_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_CTRL1")
-            .field(
-                "dcache_shut_core0_bus",
-                &format_args!("{}", self.dcache_shut_core0_bus().bit()),
-            )
-            .field(
-                "dcache_shut_core1_bus",
-                &format_args!("{}", self.dcache_shut_core1_bus().bit()),
-            )
+            .field("dcache_shut_core0_bus", &self.dcache_shut_core0_bus())
+            .field("dcache_shut_core1_bus", &self.dcache_shut_core1_bus())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable core0 dbus, 0: enable, 1: disable"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_freeze.rs b/esp32s3/src/extmem/dcache_freeze.rs
index 679819ff9c..c08b167ae1 100644
--- a/esp32s3/src/extmem/dcache_freeze.rs
+++ b/esp32s3/src/extmem/dcache_freeze.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_FREEZE")
-            .field("ena", &format_args!("{}", self.ena().bit()))
-            .field("mode", &format_args!("{}", self.mode().bit()))
-            .field("done", &format_args!("{}", self.done().bit()))
+            .field("ena", &self.ena())
+            .field("mode", &self.mode())
+            .field("done", &self.done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_FREEZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable dcache freeze mode"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_lock_addr.rs b/esp32s3/src/extmem/dcache_lock_addr.rs
index 128e7b2702..86eb5b1978 100644
--- a/esp32s3/src/extmem/dcache_lock_addr.rs
+++ b/esp32s3/src/extmem/dcache_lock_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_LOCK_ADDR")
-            .field(
-                "dcache_lock_addr",
-                &format_args!("{}", self.dcache_lock_addr().bits()),
-            )
+            .field("dcache_lock_addr", &self.dcache_lock_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_LOCK_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_lock_ctrl.rs b/esp32s3/src/extmem/dcache_lock_ctrl.rs
index aeffa53f6d..16ad19eed8 100644
--- a/esp32s3/src/extmem/dcache_lock_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_lock_ctrl.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_LOCK_CTRL")
-            .field(
-                "dcache_lock_ena",
-                &format_args!("{}", self.dcache_lock_ena().bit()),
-            )
-            .field(
-                "dcache_unlock_ena",
-                &format_args!("{}", self.dcache_unlock_ena().bit()),
-            )
-            .field(
-                "dcache_lock_done",
-                &format_args!("{}", self.dcache_lock_done().bit()),
-            )
+            .field("dcache_lock_ena", &self.dcache_lock_ena())
+            .field("dcache_unlock_ena", &self.dcache_unlock_ena())
+            .field("dcache_lock_done", &self.dcache_lock_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_LOCK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_lock_size.rs b/esp32s3/src/extmem/dcache_lock_size.rs
index 3e8b6dbfd5..021cf39124 100644
--- a/esp32s3/src/extmem/dcache_lock_size.rs
+++ b/esp32s3/src/extmem/dcache_lock_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_LOCK_SIZE")
-            .field(
-                "dcache_lock_size",
-                &format_args!("{}", self.dcache_lock_size().bits()),
-            )
+            .field("dcache_lock_size", &self.dcache_lock_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_LOCK_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_occupy_addr.rs b/esp32s3/src/extmem/dcache_occupy_addr.rs
index df556935f0..442bb503f6 100644
--- a/esp32s3/src/extmem/dcache_occupy_addr.rs
+++ b/esp32s3/src/extmem/dcache_occupy_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_OCCUPY_ADDR")
-            .field(
-                "dcache_occupy_addr",
-                &format_args!("{}", self.dcache_occupy_addr().bits()),
-            )
+            .field("dcache_occupy_addr", &self.dcache_occupy_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_OCCUPY_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_occupy_ctrl.rs b/esp32s3/src/extmem/dcache_occupy_ctrl.rs
index e1abda7196..6c3575183a 100644
--- a/esp32s3/src/extmem/dcache_occupy_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_occupy_ctrl.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_OCCUPY_CTRL")
-            .field(
-                "dcache_occupy_ena",
-                &format_args!("{}", self.dcache_occupy_ena().bit()),
-            )
-            .field(
-                "dcache_occupy_done",
-                &format_args!("{}", self.dcache_occupy_done().bit()),
-            )
+            .field("dcache_occupy_ena", &self.dcache_occupy_ena())
+            .field("dcache_occupy_done", &self.dcache_occupy_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_OCCUPY_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_occupy_size.rs b/esp32s3/src/extmem/dcache_occupy_size.rs
index 19e091aa38..13a9ac6867 100644
--- a/esp32s3/src/extmem/dcache_occupy_size.rs
+++ b/esp32s3/src/extmem/dcache_occupy_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_OCCUPY_SIZE")
-            .field(
-                "dcache_occupy_size",
-                &format_args!("{}", self.dcache_occupy_size().bits()),
-            )
+            .field("dcache_occupy_size", &self.dcache_occupy_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_OCCUPY_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_preload_addr.rs b/esp32s3/src/extmem/dcache_preload_addr.rs
index d0d13e6da4..601e4a7f52 100644
--- a/esp32s3/src/extmem/dcache_preload_addr.rs
+++ b/esp32s3/src/extmem/dcache_preload_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_PRELOAD_ADDR")
-            .field(
-                "dcache_preload_addr",
-                &format_args!("{}", self.dcache_preload_addr().bits()),
-            )
+            .field("dcache_preload_addr", &self.dcache_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_preload_ctrl.rs b/esp32s3/src/extmem/dcache_preload_ctrl.rs
index f4fb758deb..d46ee8fe02 100644
--- a/esp32s3/src/extmem/dcache_preload_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_preload_ctrl.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_PRELOAD_CTRL")
-            .field(
-                "dcache_preload_ena",
-                &format_args!("{}", self.dcache_preload_ena().bit()),
-            )
-            .field(
-                "dcache_preload_done",
-                &format_args!("{}", self.dcache_preload_done().bit()),
-            )
-            .field(
-                "dcache_preload_order",
-                &format_args!("{}", self.dcache_preload_order().bit()),
-            )
+            .field("dcache_preload_ena", &self.dcache_preload_ena())
+            .field("dcache_preload_done", &self.dcache_preload_done())
+            .field("dcache_preload_order", &self.dcache_preload_order())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_PRELOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_preload_size.rs b/esp32s3/src/extmem/dcache_preload_size.rs
index 45af061aef..46c4e4e324 100644
--- a/esp32s3/src/extmem/dcache_preload_size.rs
+++ b/esp32s3/src/extmem/dcache_preload_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_PRELOAD_SIZE")
-            .field(
-                "dcache_preload_size",
-                &format_args!("{}", self.dcache_preload_size().bits()),
-            )
+            .field("dcache_preload_size", &self.dcache_preload_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG.."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_prelock_ctrl.rs b/esp32s3/src/extmem/dcache_prelock_ctrl.rs
index 1fe1d04c00..d5447e7d46 100644
--- a/esp32s3/src/extmem/dcache_prelock_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_prelock_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_PRELOCK_CTRL")
-            .field(
-                "dcache_prelock_sct0_en",
-                &format_args!("{}", self.dcache_prelock_sct0_en().bit()),
-            )
-            .field(
-                "dcache_prelock_sct1_en",
-                &format_args!("{}", self.dcache_prelock_sct1_en().bit()),
-            )
+            .field("dcache_prelock_sct0_en", &self.dcache_prelock_sct0_en())
+            .field("dcache_prelock_sct1_en", &self.dcache_prelock_sct1_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_PRELOCK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable the first section of prelock function."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_prelock_sct0_addr.rs b/esp32s3/src/extmem/dcache_prelock_sct0_addr.rs
index c7b9c8ab4a..51d687eed7 100644
--- a/esp32s3/src/extmem/dcache_prelock_sct0_addr.rs
+++ b/esp32s3/src/extmem/dcache_prelock_sct0_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_PRELOCK_SCT0_ADDR")
-            .field(
-                "dcache_prelock_sct0_addr",
-                &format_args!("{}", self.dcache_prelock_sct0_addr().bits()),
-            )
+            .field("dcache_prelock_sct0_addr", &self.dcache_prelock_sct0_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_PRELOCK_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the first start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_prelock_sct1_addr.rs b/esp32s3/src/extmem/dcache_prelock_sct1_addr.rs
index fd96b8f167..72ad8a07f4 100644
--- a/esp32s3/src/extmem/dcache_prelock_sct1_addr.rs
+++ b/esp32s3/src/extmem/dcache_prelock_sct1_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_PRELOCK_SCT1_ADDR")
-            .field(
-                "dcache_prelock_sct1_addr",
-                &format_args!("{}", self.dcache_prelock_sct1_addr().bits()),
-            )
+            .field("dcache_prelock_sct1_addr", &self.dcache_prelock_sct1_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_PRELOCK_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the second start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_prelock_sct_size.rs b/esp32s3/src/extmem/dcache_prelock_sct_size.rs
index e565547265..6e218393a0 100644
--- a/esp32s3/src/extmem/dcache_prelock_sct_size.rs
+++ b/esp32s3/src/extmem/dcache_prelock_sct_size.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_PRELOCK_SCT_SIZE")
-            .field(
-                "dcache_prelock_sct1_size",
-                &format_args!("{}", self.dcache_prelock_sct1_size().bits()),
-            )
-            .field(
-                "dcache_prelock_sct0_size",
-                &format_args!("{}", self.dcache_prelock_sct0_size().bits()),
-            )
+            .field("dcache_prelock_sct1_size", &self.dcache_prelock_sct1_size())
+            .field("dcache_prelock_sct0_size", &self.dcache_prelock_sct0_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_PRELOCK_SCT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_sync_addr.rs b/esp32s3/src/extmem/dcache_sync_addr.rs
index 96b8e1b4f8..2f2e4fb83b 100644
--- a/esp32s3/src/extmem/dcache_sync_addr.rs
+++ b/esp32s3/src/extmem/dcache_sync_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_SYNC_ADDR")
-            .field(
-                "dcache_sync_addr",
-                &format_args!("{}", self.dcache_sync_addr().bits()),
-            )
+            .field("dcache_sync_addr", &self.dcache_sync_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_SYNC_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_sync_ctrl.rs b/esp32s3/src/extmem/dcache_sync_ctrl.rs
index 6955bdb9a9..8bb58b2da3 100644
--- a/esp32s3/src/extmem/dcache_sync_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_sync_ctrl.rs
@@ -42,31 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_SYNC_CTRL")
-            .field(
-                "dcache_invalidate_ena",
-                &format_args!("{}", self.dcache_invalidate_ena().bit()),
-            )
-            .field(
-                "dcache_writeback_ena",
-                &format_args!("{}", self.dcache_writeback_ena().bit()),
-            )
-            .field(
-                "dcache_clean_ena",
-                &format_args!("{}", self.dcache_clean_ena().bit()),
-            )
-            .field(
-                "dcache_sync_done",
-                &format_args!("{}", self.dcache_sync_done().bit()),
-            )
+            .field("dcache_invalidate_ena", &self.dcache_invalidate_ena())
+            .field("dcache_writeback_ena", &self.dcache_writeback_ena())
+            .field("dcache_clean_ena", &self.dcache_clean_ena())
+            .field("dcache_sync_done", &self.dcache_sync_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_SYNC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_sync_size.rs b/esp32s3/src/extmem/dcache_sync_size.rs
index 9e0b4f5bd4..681013949d 100644
--- a/esp32s3/src/extmem/dcache_sync_size.rs
+++ b/esp32s3/src/extmem/dcache_sync_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_SYNC_SIZE")
-            .field(
-                "dcache_sync_size",
-                &format_args!("{}", self.dcache_sync_size().bits()),
-            )
+            .field("dcache_sync_size", &self.dcache_sync_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_SYNC_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:22 - The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/dcache_tag_power_ctrl.rs b/esp32s3/src/extmem/dcache_tag_power_ctrl.rs
index 251f302905..9690227d08 100644
--- a/esp32s3/src/extmem/dcache_tag_power_ctrl.rs
+++ b/esp32s3/src/extmem/dcache_tag_power_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_TAG_POWER_CTRL")
-            .field(
-                "dcache_tag_mem_force_on",
-                &format_args!("{}", self.dcache_tag_mem_force_on().bit()),
-            )
-            .field(
-                "dcache_tag_mem_force_pd",
-                &format_args!("{}", self.dcache_tag_mem_force_pd().bit()),
-            )
-            .field(
-                "dcache_tag_mem_force_pu",
-                &format_args!("{}", self.dcache_tag_mem_force_pu().bit()),
-            )
+            .field("dcache_tag_mem_force_on", &self.dcache_tag_mem_force_on())
+            .field("dcache_tag_mem_force_pd", &self.dcache_tag_mem_force_pd())
+            .field("dcache_tag_mem_force_pu", &self.dcache_tag_mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_TAG_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/ibus_acs_cnt.rs b/esp32s3/src/extmem/ibus_acs_cnt.rs
index fb7a0e889e..fc96003fef 100644
--- a/esp32s3/src/extmem/ibus_acs_cnt.rs
+++ b/esp32s3/src/extmem/ibus_acs_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS_ACS_CNT")
-            .field(
-                "ibus_acs_cnt",
-                &format_args!("{}", self.ibus_acs_cnt().bits()),
-            )
+            .field("ibus_acs_cnt", &self.ibus_acs_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS_ACS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibus_acs_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IBUS_ACS_CNT_SPEC;
 impl crate::RegisterSpec for IBUS_ACS_CNT_SPEC {
diff --git a/esp32s3/src/extmem/ibus_acs_miss_cnt.rs b/esp32s3/src/extmem/ibus_acs_miss_cnt.rs
index 332b21c033..27ad3da8e0 100644
--- a/esp32s3/src/extmem/ibus_acs_miss_cnt.rs
+++ b/esp32s3/src/extmem/ibus_acs_miss_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS_ACS_MISS_CNT")
-            .field(
-                "ibus_acs_miss_cnt",
-                &format_args!("{}", self.ibus_acs_miss_cnt().bits()),
-            )
+            .field("ibus_acs_miss_cnt", &self.ibus_acs_miss_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS_ACS_MISS_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibus_acs_miss_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IBUS_ACS_MISS_CNT_SPEC;
 impl crate::RegisterSpec for IBUS_ACS_MISS_CNT_SPEC {
diff --git a/esp32s3/src/extmem/ibus_to_flash_end_vaddr.rs b/esp32s3/src/extmem/ibus_to_flash_end_vaddr.rs
index ecc44fe928..d24bb61a06 100644
--- a/esp32s3/src/extmem/ibus_to_flash_end_vaddr.rs
+++ b/esp32s3/src/extmem/ibus_to_flash_end_vaddr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IBUS_TO_FLASH_END_VADDR")
-            .field(
-                "ibus_to_flash_end_vaddr",
-                &format_args!("{}", self.ibus_to_flash_end_vaddr().bits()),
-            )
+            .field("ibus_to_flash_end_vaddr", &self.ibus_to_flash_end_vaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS_TO_FLASH_END_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/ibus_to_flash_start_vaddr.rs b/esp32s3/src/extmem/ibus_to_flash_start_vaddr.rs
index 8e934f8e2a..312d412d68 100644
--- a/esp32s3/src/extmem/ibus_to_flash_start_vaddr.rs
+++ b/esp32s3/src/extmem/ibus_to_flash_start_vaddr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("IBUS_TO_FLASH_START_VADDR")
             .field(
                 "ibus_to_flash_start_vaddr",
-                &format_args!("{}", self.ibus_to_flash_start_vaddr().bits()),
+                &self.ibus_to_flash_start_vaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IBUS_TO_FLASH_START_VADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_atomic_operate_ena.rs b/esp32s3/src/extmem/icache_atomic_operate_ena.rs
index 8a494bcbff..f819792b2c 100644
--- a/esp32s3/src/extmem/icache_atomic_operate_ena.rs
+++ b/esp32s3/src/extmem/icache_atomic_operate_ena.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ICACHE_ATOMIC_OPERATE_ENA")
             .field(
                 "icache_atomic_operate_ena",
-                &format_args!("{}", self.icache_atomic_operate_ena().bit()),
+                &self.icache_atomic_operate_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_ATOMIC_OPERATE_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_autoload_ctrl.rs b/esp32s3/src/extmem/icache_autoload_ctrl.rs
index 8f0db95f97..0fe1a6e593 100644
--- a/esp32s3/src/extmem/icache_autoload_ctrl.rs
+++ b/esp32s3/src/extmem/icache_autoload_ctrl.rs
@@ -78,47 +78,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_AUTOLOAD_CTRL")
-            .field(
-                "icache_autoload_sct0_ena",
-                &format_args!("{}", self.icache_autoload_sct0_ena().bit()),
-            )
-            .field(
-                "icache_autoload_sct1_ena",
-                &format_args!("{}", self.icache_autoload_sct1_ena().bit()),
-            )
-            .field(
-                "icache_autoload_ena",
-                &format_args!("{}", self.icache_autoload_ena().bit()),
-            )
-            .field(
-                "icache_autoload_done",
-                &format_args!("{}", self.icache_autoload_done().bit()),
-            )
-            .field(
-                "icache_autoload_order",
-                &format_args!("{}", self.icache_autoload_order().bit()),
-            )
-            .field(
-                "icache_autoload_rqst",
-                &format_args!("{}", self.icache_autoload_rqst().bits()),
-            )
-            .field(
-                "icache_autoload_size",
-                &format_args!("{}", self.icache_autoload_size().bits()),
-            )
+            .field("icache_autoload_sct0_ena", &self.icache_autoload_sct0_ena())
+            .field("icache_autoload_sct1_ena", &self.icache_autoload_sct1_ena())
+            .field("icache_autoload_ena", &self.icache_autoload_ena())
+            .field("icache_autoload_done", &self.icache_autoload_done())
+            .field("icache_autoload_order", &self.icache_autoload_order())
+            .field("icache_autoload_rqst", &self.icache_autoload_rqst())
+            .field("icache_autoload_size", &self.icache_autoload_size())
             .field(
                 "icache_autoload_buffer_clear",
-                &format_args!("{}", self.icache_autoload_buffer_clear().bit()),
+                &self.icache_autoload_buffer_clear(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_AUTOLOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bits are used to enable the first section for autoload operation."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_autoload_sct0_addr.rs b/esp32s3/src/extmem/icache_autoload_sct0_addr.rs
index 45b0dbe9ad..e890616535 100644
--- a/esp32s3/src/extmem/icache_autoload_sct0_addr.rs
+++ b/esp32s3/src/extmem/icache_autoload_sct0_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ICACHE_AUTOLOAD_SCT0_ADDR")
             .field(
                 "icache_autoload_sct0_addr",
-                &format_args!("{}", self.icache_autoload_sct0_addr().bits()),
+                &self.icache_autoload_sct0_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_AUTOLOAD_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_autoload_sct0_size.rs b/esp32s3/src/extmem/icache_autoload_sct0_size.rs
index d5cabe5639..de558ba80c 100644
--- a/esp32s3/src/extmem/icache_autoload_sct0_size.rs
+++ b/esp32s3/src/extmem/icache_autoload_sct0_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ICACHE_AUTOLOAD_SCT0_SIZE")
             .field(
                 "icache_autoload_sct0_size",
-                &format_args!("{}", self.icache_autoload_sct0_size().bits()),
+                &self.icache_autoload_sct0_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_AUTOLOAD_SCT0_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:26 - The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_autoload_sct1_addr.rs b/esp32s3/src/extmem/icache_autoload_sct1_addr.rs
index 38d68a37f3..fe275f51e1 100644
--- a/esp32s3/src/extmem/icache_autoload_sct1_addr.rs
+++ b/esp32s3/src/extmem/icache_autoload_sct1_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ICACHE_AUTOLOAD_SCT1_ADDR")
             .field(
                 "icache_autoload_sct1_addr",
-                &format_args!("{}", self.icache_autoload_sct1_addr().bits()),
+                &self.icache_autoload_sct1_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_AUTOLOAD_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_autoload_sct1_size.rs b/esp32s3/src/extmem/icache_autoload_sct1_size.rs
index 46430c21bb..4d9d012e35 100644
--- a/esp32s3/src/extmem/icache_autoload_sct1_size.rs
+++ b/esp32s3/src/extmem/icache_autoload_sct1_size.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("ICACHE_AUTOLOAD_SCT1_SIZE")
             .field(
                 "icache_autoload_sct1_size",
-                &format_args!("{}", self.icache_autoload_sct1_size().bits()),
+                &self.icache_autoload_sct1_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_AUTOLOAD_SCT1_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:26 - The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_ctrl.rs b/esp32s3/src/extmem/icache_ctrl.rs
index 2d334db7e9..967f201be2 100644
--- a/esp32s3/src/extmem/icache_ctrl.rs
+++ b/esp32s3/src/extmem/icache_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_CTRL")
-            .field(
-                "icache_enable",
-                &format_args!("{}", self.icache_enable().bit()),
-            )
-            .field(
-                "icache_way_mode",
-                &format_args!("{}", self.icache_way_mode().bit()),
-            )
-            .field(
-                "icache_size_mode",
-                &format_args!("{}", self.icache_size_mode().bit()),
-            )
-            .field(
-                "icache_blocksize_mode",
-                &format_args!("{}", self.icache_blocksize_mode().bit()),
-            )
+            .field("icache_enable", &self.icache_enable())
+            .field("icache_way_mode", &self.icache_way_mode())
+            .field("icache_size_mode", &self.icache_size_mode())
+            .field("icache_blocksize_mode", &self.icache_blocksize_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_ctrl1.rs b/esp32s3/src/extmem/icache_ctrl1.rs
index 84b31bb136..a8dc8619f0 100644
--- a/esp32s3/src/extmem/icache_ctrl1.rs
+++ b/esp32s3/src/extmem/icache_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_CTRL1")
-            .field(
-                "icache_shut_core0_bus",
-                &format_args!("{}", self.icache_shut_core0_bus().bit()),
-            )
-            .field(
-                "icache_shut_core1_bus",
-                &format_args!("{}", self.icache_shut_core1_bus().bit()),
-            )
+            .field("icache_shut_core0_bus", &self.icache_shut_core0_bus())
+            .field("icache_shut_core1_bus", &self.icache_shut_core1_bus())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to disable core0 ibus, 0: enable, 1: disable"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_freeze.rs b/esp32s3/src/extmem/icache_freeze.rs
index 806d83b85c..0da4691514 100644
--- a/esp32s3/src/extmem/icache_freeze.rs
+++ b/esp32s3/src/extmem/icache_freeze.rs
@@ -33,18 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_FREEZE")
-            .field("ena", &format_args!("{}", self.ena().bit()))
-            .field("mode", &format_args!("{}", self.mode().bit()))
-            .field("done", &format_args!("{}", self.done().bit()))
+            .field("ena", &self.ena())
+            .field("mode", &self.mode())
+            .field("done", &self.done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_FREEZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable icache freeze mode"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_lock_addr.rs b/esp32s3/src/extmem/icache_lock_addr.rs
index e2cbc3063b..0f862ada13 100644
--- a/esp32s3/src/extmem/icache_lock_addr.rs
+++ b/esp32s3/src/extmem/icache_lock_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_LOCK_ADDR")
-            .field(
-                "icache_lock_addr",
-                &format_args!("{}", self.icache_lock_addr().bits()),
-            )
+            .field("icache_lock_addr", &self.icache_lock_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_LOCK_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_lock_ctrl.rs b/esp32s3/src/extmem/icache_lock_ctrl.rs
index 1d1db0ac44..74c740b55d 100644
--- a/esp32s3/src/extmem/icache_lock_ctrl.rs
+++ b/esp32s3/src/extmem/icache_lock_ctrl.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_LOCK_CTRL")
-            .field(
-                "icache_lock_ena",
-                &format_args!("{}", self.icache_lock_ena().bit()),
-            )
-            .field(
-                "icache_unlock_ena",
-                &format_args!("{}", self.icache_unlock_ena().bit()),
-            )
-            .field(
-                "icache_lock_done",
-                &format_args!("{}", self.icache_lock_done().bit()),
-            )
+            .field("icache_lock_ena", &self.icache_lock_ena())
+            .field("icache_unlock_ena", &self.icache_unlock_ena())
+            .field("icache_lock_done", &self.icache_lock_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_LOCK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable lock operation. It will be cleared by hardware after lock operation done."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_lock_size.rs b/esp32s3/src/extmem/icache_lock_size.rs
index 810e3652bf..25a45a1122 100644
--- a/esp32s3/src/extmem/icache_lock_size.rs
+++ b/esp32s3/src/extmem/icache_lock_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_LOCK_SIZE")
-            .field(
-                "icache_lock_size",
-                &format_args!("{}", self.icache_lock_size().bits()),
-            )
+            .field("icache_lock_size", &self.icache_lock_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_LOCK_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_preload_addr.rs b/esp32s3/src/extmem/icache_preload_addr.rs
index 99a363e1d1..48aaa4b5da 100644
--- a/esp32s3/src/extmem/icache_preload_addr.rs
+++ b/esp32s3/src/extmem/icache_preload_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOAD_ADDR")
-            .field(
-                "icache_preload_addr",
-                &format_args!("{}", self.icache_preload_addr().bits()),
-            )
+            .field("icache_preload_addr", &self.icache_preload_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOAD_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_preload_ctrl.rs b/esp32s3/src/extmem/icache_preload_ctrl.rs
index fe812912a9..b8b9222877 100644
--- a/esp32s3/src/extmem/icache_preload_ctrl.rs
+++ b/esp32s3/src/extmem/icache_preload_ctrl.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOAD_CTRL")
-            .field(
-                "icache_preload_ena",
-                &format_args!("{}", self.icache_preload_ena().bit()),
-            )
-            .field(
-                "icache_preload_done",
-                &format_args!("{}", self.icache_preload_done().bit()),
-            )
-            .field(
-                "icache_preload_order",
-                &format_args!("{}", self.icache_preload_order().bit()),
-            )
+            .field("icache_preload_ena", &self.icache_preload_ena())
+            .field("icache_preload_done", &self.icache_preload_done())
+            .field("icache_preload_order", &self.icache_preload_order())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOAD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable preload operation. It will be cleared by hardware after preload operation done."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_preload_size.rs b/esp32s3/src/extmem/icache_preload_size.rs
index 6d9139b484..3b6efbbd6d 100644
--- a/esp32s3/src/extmem/icache_preload_size.rs
+++ b/esp32s3/src/extmem/icache_preload_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOAD_SIZE")
-            .field(
-                "icache_preload_size",
-                &format_args!("{}", self.icache_preload_size().bits()),
-            )
+            .field("icache_preload_size", &self.icache_preload_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOAD_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG.."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_prelock_ctrl.rs b/esp32s3/src/extmem/icache_prelock_ctrl.rs
index 7e5d9b603b..0502b97464 100644
--- a/esp32s3/src/extmem/icache_prelock_ctrl.rs
+++ b/esp32s3/src/extmem/icache_prelock_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOCK_CTRL")
-            .field(
-                "icache_prelock_sct0_en",
-                &format_args!("{}", self.icache_prelock_sct0_en().bit()),
-            )
-            .field(
-                "icache_prelock_sct1_en",
-                &format_args!("{}", self.icache_prelock_sct1_en().bit()),
-            )
+            .field("icache_prelock_sct0_en", &self.icache_prelock_sct0_en())
+            .field("icache_prelock_sct1_en", &self.icache_prelock_sct1_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOCK_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable the first section of prelock function."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_prelock_sct0_addr.rs b/esp32s3/src/extmem/icache_prelock_sct0_addr.rs
index 027b73785b..9c7caee1a1 100644
--- a/esp32s3/src/extmem/icache_prelock_sct0_addr.rs
+++ b/esp32s3/src/extmem/icache_prelock_sct0_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOCK_SCT0_ADDR")
-            .field(
-                "icache_prelock_sct0_addr",
-                &format_args!("{}", self.icache_prelock_sct0_addr().bits()),
-            )
+            .field("icache_prelock_sct0_addr", &self.icache_prelock_sct0_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOCK_SCT0_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_prelock_sct1_addr.rs b/esp32s3/src/extmem/icache_prelock_sct1_addr.rs
index e8ca656f69..c475b207b2 100644
--- a/esp32s3/src/extmem/icache_prelock_sct1_addr.rs
+++ b/esp32s3/src/extmem/icache_prelock_sct1_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOCK_SCT1_ADDR")
-            .field(
-                "icache_prelock_sct1_addr",
-                &format_args!("{}", self.icache_prelock_sct1_addr().bits()),
-            )
+            .field("icache_prelock_sct1_addr", &self.icache_prelock_sct1_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOCK_SCT1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_prelock_sct_size.rs b/esp32s3/src/extmem/icache_prelock_sct_size.rs
index 42a22a06dc..0168539df2 100644
--- a/esp32s3/src/extmem/icache_prelock_sct_size.rs
+++ b/esp32s3/src/extmem/icache_prelock_sct_size.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOCK_SCT_SIZE")
-            .field(
-                "icache_prelock_sct1_size",
-                &format_args!("{}", self.icache_prelock_sct1_size().bits()),
-            )
-            .field(
-                "icache_prelock_sct0_size",
-                &format_args!("{}", self.icache_prelock_sct0_size().bits()),
-            )
+            .field("icache_prelock_sct1_size", &self.icache_prelock_sct1_size())
+            .field("icache_prelock_sct0_size", &self.icache_prelock_sct0_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOCK_SCT_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG"]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_sync_addr.rs b/esp32s3/src/extmem/icache_sync_addr.rs
index b5cacf1a48..9a7eeb732d 100644
--- a/esp32s3/src/extmem/icache_sync_addr.rs
+++ b/esp32s3/src/extmem/icache_sync_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_SYNC_ADDR")
-            .field(
-                "icache_sync_addr",
-                &format_args!("{}", self.icache_sync_addr().bits()),
-            )
+            .field("icache_sync_addr", &self.icache_sync_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_SYNC_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_sync_ctrl.rs b/esp32s3/src/extmem/icache_sync_ctrl.rs
index 559364996b..a271d04907 100644
--- a/esp32s3/src/extmem/icache_sync_ctrl.rs
+++ b/esp32s3/src/extmem/icache_sync_ctrl.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_SYNC_CTRL")
-            .field(
-                "icache_invalidate_ena",
-                &format_args!("{}", self.icache_invalidate_ena().bit()),
-            )
-            .field(
-                "icache_sync_done",
-                &format_args!("{}", self.icache_sync_done().bit()),
-            )
+            .field("icache_invalidate_ena", &self.icache_invalidate_ena())
+            .field("icache_sync_done", &self.icache_sync_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_SYNC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_sync_size.rs b/esp32s3/src/extmem/icache_sync_size.rs
index 183a106f18..10ab32c6d3 100644
--- a/esp32s3/src/extmem/icache_sync_size.rs
+++ b/esp32s3/src/extmem/icache_sync_size.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_SYNC_SIZE")
-            .field(
-                "icache_sync_size",
-                &format_args!("{}", self.icache_sync_size().bits()),
-            )
+            .field("icache_sync_size", &self.icache_sync_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_SYNC_SIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:22 - The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG."]
     #[inline(always)]
diff --git a/esp32s3/src/extmem/icache_tag_power_ctrl.rs b/esp32s3/src/extmem/icache_tag_power_ctrl.rs
index 7aaac0a86a..41ea2555f7 100644
--- a/esp32s3/src/extmem/icache_tag_power_ctrl.rs
+++ b/esp32s3/src/extmem/icache_tag_power_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_TAG_POWER_CTRL")
-            .field(
-                "icache_tag_mem_force_on",
-                &format_args!("{}", self.icache_tag_mem_force_on().bit()),
-            )
-            .field(
-                "icache_tag_mem_force_pd",
-                &format_args!("{}", self.icache_tag_mem_force_pd().bit()),
-            )
-            .field(
-                "icache_tag_mem_force_pu",
-                &format_args!("{}", self.icache_tag_mem_force_pu().bit()),
-            )
+            .field("icache_tag_mem_force_on", &self.icache_tag_mem_force_on())
+            .field("icache_tag_mem_force_pd", &self.icache_tag_mem_force_pd())
+            .field("icache_tag_mem_force_pu", &self.icache_tag_mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_TAG_POWER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating."]
     #[inline(always)]
diff --git a/esp32s3/src/generic.rs b/esp32s3/src/generic.rs
index a2ae6aa053..45ebed16c4 100644
--- a/esp32s3/src/generic.rs
+++ b/esp32s3/src/generic.rs
@@ -48,7 +48,7 @@ pub trait RegisterSpec {
 #[doc = " Raw field type"]
 pub trait FieldSpec: Sized {
     #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
-    type Ux: Copy + PartialEq + From<Self>;
+    type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
 }
 #[doc = " Marker for fields with fixed values"]
 pub trait IsEnum: FieldSpec {}
@@ -237,6 +237,14 @@ impl<REG: Readable + Writable> Reg<REG> {
         );
     }
 }
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
 #[doc(hidden)]
 pub mod raw;
 #[doc = " Register reader."]
@@ -302,6 +310,11 @@ impl<FI: FieldSpec> FieldReader<FI> {
         self.bits
     }
 }
+impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 impl<FI> PartialEq<FI> for FieldReader<FI>
 where
     FI: FieldSpec + Copy,
@@ -338,10 +351,21 @@ impl<FI> BitReader<FI> {
         self.bit()
     }
 }
+impl<FI> core::fmt::Debug for BitReader<FI> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.bits, f)
+    }
+}
 #[doc = " Marker for register/field writers which can take any value of specified width"]
 pub struct Safe;
 #[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
 pub struct Unsafe;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct Range<const MIN: u64, const MAX: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeFrom<const MIN: u64>;
+#[doc = " Marker for field writers are safe to write in specified inclusive range"]
+pub struct RangeTo<const MAX: u64>;
 #[doc = " Write field Proxy"]
 pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
     raw::FieldWriter<'a, REG, WI, FI, Safety>;
@@ -393,6 +417,58 @@ where
         unsafe { self.bits(value) }
     }
 }
+impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
+    FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN && value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value >= MIN);
+        }
+        unsafe { self.bits(value) }
+    }
+}
+impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
+where
+    REG: Writable + RegisterSpec,
+    FI: FieldSpec,
+    REG::Ux: From<FI::Ux>,
+    u64: From<FI::Ux>,
+{
+    #[doc = " Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
+        {
+            let value = u64::from(value);
+            assert!(value <= MAX);
+        }
+        unsafe { self.bits(value) }
+    }
+}
 impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
diff --git a/esp32s3/src/gpio/bt_select.rs b/esp32s3/src/gpio/bt_select.rs
index d4bbc43143..d78b414754 100644
--- a/esp32s3/src/gpio/bt_select.rs
+++ b/esp32s3/src/gpio/bt_select.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_SELECT")
-            .field("bt_sel", &format_args!("{}", self.bt_sel().bits()))
+            .field("bt_sel", &self.bt_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_SELECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO bit select register"]
     #[inline(always)]
diff --git a/esp32s3/src/gpio/clock_gate.rs b/esp32s3/src/gpio/clock_gate.rs
index ebd199051e..d2bfefd1b8 100644
--- a/esp32s3/src/gpio/clock_gate.rs
+++ b/esp32s3/src/gpio/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - set this bit to enable GPIO clock gate"]
     #[inline(always)]
diff --git a/esp32s3/src/gpio/cpusdio_int.rs b/esp32s3/src/gpio/cpusdio_int.rs
index e46e64c2d4..889945a2df 100644
--- a/esp32s3/src/gpio/cpusdio_int.rs
+++ b/esp32s3/src/gpio/cpusdio_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPUSDIO_INT")
-            .field("sdio_int", &format_args!("{}", self.sdio_int().bits()))
+            .field("sdio_int", &self.sdio_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPUSDIO_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO CPUSDIO interrupt status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpusdio_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPUSDIO_INT_SPEC;
 impl crate::RegisterSpec for CPUSDIO_INT_SPEC {
diff --git a/esp32s3/src/gpio/cpusdio_int1.rs b/esp32s3/src/gpio/cpusdio_int1.rs
index 26ccb4d8c2..6bb5d58a41 100644
--- a/esp32s3/src/gpio/cpusdio_int1.rs
+++ b/esp32s3/src/gpio/cpusdio_int1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPUSDIO_INT1")
-            .field("sdio_int1", &format_args!("{}", self.sdio_int1().bits()))
+            .field("sdio_int1", &self.sdio_int1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPUSDIO_INT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO CPUSDIO interrupt status register for GPIO32-53\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpusdio_int1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CPUSDIO_INT1_SPEC;
 impl crate::RegisterSpec for CPUSDIO_INT1_SPEC {
diff --git a/esp32s3/src/gpio/enable.rs b/esp32s3/src/gpio/enable.rs
index 72557464c3..2dfdd4f50c 100644
--- a/esp32s3/src/gpio/enable.rs
+++ b/esp32s3/src/gpio/enable.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO output enable register for GPIO0-31"]
     #[inline(always)]
diff --git a/esp32s3/src/gpio/enable1.rs b/esp32s3/src/gpio/enable1.rs
index a15c861488..3c6bb98c0e 100644
--- a/esp32s3/src/gpio/enable1.rs
+++ b/esp32s3/src/gpio/enable1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENABLE1")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENABLE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - GPIO output enable register for GPIO32-53"]
     #[inline(always)]
diff --git a/esp32s3/src/gpio/func_in_sel_cfg.rs b/esp32s3/src/gpio/func_in_sel_cfg.rs
index a81b3e7871..209dbfe795 100644
--- a/esp32s3/src/gpio/func_in_sel_cfg.rs
+++ b/esp32s3/src/gpio/func_in_sel_cfg.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_IN_SEL_CFG")
-            .field("in_sel", &format_args!("{}", self.in_sel().bits()))
-            .field("in_inv_sel", &format_args!("{}", self.in_inv_sel().bit()))
-            .field("sel", &format_args!("{}", self.sel().bit()))
+            .field("in_sel", &self.in_sel())
+            .field("in_inv_sel", &self.in_inv_sel())
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_IN_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - set this value: s=0-53: connect GPIO\\[s\\] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level."]
     #[inline(always)]
diff --git a/esp32s3/src/gpio/func_out_sel_cfg.rs b/esp32s3/src/gpio/func_out_sel_cfg.rs
index 7f97f421a1..2741b8047d 100644
--- a/esp32s3/src/gpio/func_out_sel_cfg.rs
+++ b/esp32s3/src/gpio/func_out_sel_cfg.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FUNC_OUT_SEL_CFG")
-            .field("out_sel", &format_args!("{}", self.out_sel().bits()))
-            .field("inv_sel", &format_args!("{}", self.inv_sel().bit()))
-            .field("oen_sel", &format_args!("{}", self.oen_sel().bit()))
-            .field("oen_inv_sel", &format_args!("{}", self.oen_inv_sel().bit()))
+            .field("out_sel", &self.out_sel())
+            .field("inv_sel", &self.inv_sel())
+            .field("oen_sel", &self.oen_sel())
+            .field("oen_inv_sel", &self.oen_inv_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FUNC_OUT_SEL_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - The value of the bits: 0&lt;=s&lt;=256. Set the value to select output signal. s=0-255: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=256: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
     #[inline(always)]
diff --git a/esp32s3/src/gpio/in1.rs b/esp32s3/src/gpio/in1.rs
index 019e3812e7..5de36c3464 100644
--- a/esp32s3/src/gpio/in1.rs
+++ b/esp32s3/src/gpio/in1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN1")
-            .field("data_next", &format_args!("{}", self.data_next().bits()))
+            .field("data_next", &self.data_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - GPIO input register for GPIO32-53"]
     #[inline(always)]
diff --git a/esp32s3/src/gpio/in_.rs b/esp32s3/src/gpio/in_.rs
index 4d407d13ac..ec6585718e 100644
--- a/esp32s3/src/gpio/in_.rs
+++ b/esp32s3/src/gpio/in_.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN")
-            .field("data_next", &format_args!("{}", self.data_next().bits()))
+            .field("data_next", &self.data_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO input register for GPIO0-31"]
     #[inline(always)]
diff --git a/esp32s3/src/gpio/out.rs b/esp32s3/src/gpio/out.rs
index 3e77b03d34..2c8f1cfb13 100644
--- a/esp32s3/src/gpio/out.rs
+++ b/esp32s3/src/gpio/out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT")
-            .field("data_orig", &format_args!("{}", self.data_orig().bits()))
+            .field("data_orig", &self.data_orig())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO output register for GPIO0-31"]
     #[inline(always)]
diff --git a/esp32s3/src/gpio/out1.rs b/esp32s3/src/gpio/out1.rs
index 081959242b..b8dafc602e 100644
--- a/esp32s3/src/gpio/out1.rs
+++ b/esp32s3/src/gpio/out1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT1")
-            .field("data_orig", &format_args!("{}", self.data_orig().bits()))
+            .field("data_orig", &self.data_orig())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - GPIO output register for GPIO32-53"]
     #[inline(always)]
diff --git a/esp32s3/src/gpio/pcpu_int.rs b/esp32s3/src/gpio/pcpu_int.rs
index b07a90c28e..52727d2345 100644
--- a/esp32s3/src/gpio/pcpu_int.rs
+++ b/esp32s3/src/gpio/pcpu_int.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_INT")
-            .field("procpu_int", &format_args!("{}", self.procpu_int().bits()))
+            .field("procpu_int", &self.procpu_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO PRO_CPU interrupt status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_INT_SPEC;
 impl crate::RegisterSpec for PCPU_INT_SPEC {
diff --git a/esp32s3/src/gpio/pcpu_int1.rs b/esp32s3/src/gpio/pcpu_int1.rs
index d8f1adbd4c..8c5cabc9a3 100644
--- a/esp32s3/src/gpio/pcpu_int1.rs
+++ b/esp32s3/src/gpio/pcpu_int1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_INT1")
-            .field(
-                "procpu_int1",
-                &format_args!("{}", self.procpu_int1().bits()),
-            )
+            .field("procpu_int1", &self.procpu_int1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_INT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO PRO_CPU interrupt status register for GPIO32-53\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_int1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_INT1_SPEC;
 impl crate::RegisterSpec for PCPU_INT1_SPEC {
diff --git a/esp32s3/src/gpio/pcpu_nmi_int.rs b/esp32s3/src/gpio/pcpu_nmi_int.rs
index 6105c42de8..729f48eacd 100644
--- a/esp32s3/src/gpio/pcpu_nmi_int.rs
+++ b/esp32s3/src/gpio/pcpu_nmi_int.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_NMI_INT")
-            .field(
-                "procpu_nmi_int",
-                &format_args!("{}", self.procpu_nmi_int().bits()),
-            )
+            .field("procpu_nmi_int", &self.procpu_nmi_int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_NMI_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_nmi_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_NMI_INT_SPEC;
 impl crate::RegisterSpec for PCPU_NMI_INT_SPEC {
diff --git a/esp32s3/src/gpio/pcpu_nmi_int1.rs b/esp32s3/src/gpio/pcpu_nmi_int1.rs
index 419a1acf6d..51910041ea 100644
--- a/esp32s3/src/gpio/pcpu_nmi_int1.rs
+++ b/esp32s3/src/gpio/pcpu_nmi_int1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCPU_NMI_INT1")
-            .field(
-                "procpu_nmi_int1",
-                &format_args!("{}", self.procpu_nmi_int1().bits()),
-            )
+            .field("procpu_nmi_int1", &self.procpu_nmi_int1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCPU_NMI_INT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-53\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcpu_nmi_int1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PCPU_NMI_INT1_SPEC;
 impl crate::RegisterSpec for PCPU_NMI_INT1_SPEC {
diff --git a/esp32s3/src/gpio/pin.rs b/esp32s3/src/gpio/pin.rs
index 582513e76d..37d6329326 100644
--- a/esp32s3/src/gpio/pin.rs
+++ b/esp32s3/src/gpio/pin.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN")
-            .field(
-                "sync2_bypass",
-                &format_args!("{}", self.sync2_bypass().bits()),
-            )
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field(
-                "sync1_bypass",
-                &format_args!("{}", self.sync1_bypass().bits()),
-            )
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
-            .field("config", &format_args!("{}", self.config().bits()))
-            .field("int_ena", &format_args!("{}", self.int_ena().bits()))
+            .field("sync2_bypass", &self.sync2_bypass())
+            .field("pad_driver", &self.pad_driver())
+            .field("sync1_bypass", &self.sync1_bypass())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
+            .field("config", &self.config())
+            .field("int_ena", &self.int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge."]
     #[inline(always)]
diff --git a/esp32s3/src/gpio/reg_date.rs b/esp32s3/src/gpio/reg_date.rs
index 512672a265..7ed6c77afc 100644
--- a/esp32s3/src/gpio/reg_date.rs
+++ b/esp32s3/src/gpio/reg_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_DATE")
-            .field("reg_date", &format_args!("{}", self.reg_date().bits()))
+            .field("reg_date", &self.reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - version register"]
     #[inline(always)]
diff --git a/esp32s3/src/gpio/sdio_select.rs b/esp32s3/src/gpio/sdio_select.rs
index 0f94b5932d..557422a488 100644
--- a/esp32s3/src/gpio/sdio_select.rs
+++ b/esp32s3/src/gpio/sdio_select.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_SELECT")
-            .field("sdio_sel", &format_args!("{}", self.sdio_sel().bits()))
+            .field("sdio_sel", &self.sdio_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_SELECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - GPIO sdio select register"]
     #[inline(always)]
diff --git a/esp32s3/src/gpio/status.rs b/esp32s3/src/gpio/status.rs
index 349c0cde52..d41f06e1a5 100644
--- a/esp32s3/src/gpio/status.rs
+++ b/esp32s3/src/gpio/status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("interrupt", &format_args!("{}", self.interrupt().bits()))
+            .field("interrupt", &self.interrupt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - GPIO interrupt status register for GPIO0-31"]
     #[inline(always)]
diff --git a/esp32s3/src/gpio/status1.rs b/esp32s3/src/gpio/status1.rs
index 596fdb0e6c..b65b115492 100644
--- a/esp32s3/src/gpio/status1.rs
+++ b/esp32s3/src/gpio/status1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS1")
-            .field("interrupt", &format_args!("{}", self.interrupt().bits()))
+            .field("interrupt", &self.interrupt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - GPIO interrupt status register for GPIO32-53"]
     #[inline(always)]
diff --git a/esp32s3/src/gpio/status_next.rs b/esp32s3/src/gpio/status_next.rs
index 9df3402e32..ea7e8832c2 100644
--- a/esp32s3/src/gpio/status_next.rs
+++ b/esp32s3/src/gpio/status_next.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_NEXT")
-            .field(
-                "status_interrupt_next",
-                &format_args!("{}", self.status_interrupt_next().bits()),
-            )
+            .field("status_interrupt_next", &self.status_interrupt_next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_NEXT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt source register for GPIO0-31\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_NEXT_SPEC;
 impl crate::RegisterSpec for STATUS_NEXT_SPEC {
diff --git a/esp32s3/src/gpio/status_next1.rs b/esp32s3/src/gpio/status_next1.rs
index 000b051332..debef30031 100644
--- a/esp32s3/src/gpio/status_next1.rs
+++ b/esp32s3/src/gpio/status_next1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS_NEXT1")
-            .field(
-                "status_interrupt_next1",
-                &format_args!("{}", self.status_interrupt_next1().bits()),
-            )
+            .field("status_interrupt_next1", &self.status_interrupt_next1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_NEXT1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "GPIO interrupt source register for GPIO32-53\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status_next1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_NEXT1_SPEC;
 impl crate::RegisterSpec for STATUS_NEXT1_SPEC {
diff --git a/esp32s3/src/gpio/strap.rs b/esp32s3/src/gpio/strap.rs
index dfc141ecfb..3bc90c4409 100644
--- a/esp32s3/src/gpio/strap.rs
+++ b/esp32s3/src/gpio/strap.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STRAP")
-            .field("strapping", &format_args!("{}", self.strapping().bits()))
+            .field("strapping", &self.strapping())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STRAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "pad strapping register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`strap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STRAP_SPEC;
 impl crate::RegisterSpec for STRAP_SPEC {
diff --git a/esp32s3/src/gpio_sd/clock_gate.rs b/esp32s3/src/gpio_sd/clock_gate.rs
index 5d6939c423..449c80d9a8 100644
--- a/esp32s3/src/gpio_sd/clock_gate.rs
+++ b/esp32s3/src/gpio_sd/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Clock enable bit of configuration registers for sigma delta modulation."]
     #[inline(always)]
diff --git a/esp32s3/src/gpio_sd/sigmadelta.rs b/esp32s3/src/gpio_sd/sigmadelta.rs
index 2cb8973865..1d31bcd5d8 100644
--- a/esp32s3/src/gpio_sd/sigmadelta.rs
+++ b/esp32s3/src/gpio_sd/sigmadelta.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SIGMADELTA")
-            .field("in_", &format_args!("{}", self.in_().bits()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
+            .field("in_", &self.in_())
+            .field("prescale", &self.prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SIGMADELTA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This field is used to configure the duty cycle of sigma delta modulation output."]
     #[inline(always)]
diff --git a/esp32s3/src/gpio_sd/sigmadelta_misc.rs b/esp32s3/src/gpio_sd/sigmadelta_misc.rs
index b0c196b157..973947d549 100644
--- a/esp32s3/src/gpio_sd/sigmadelta_misc.rs
+++ b/esp32s3/src/gpio_sd/sigmadelta_misc.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SIGMADELTA_MISC")
-            .field(
-                "function_clk_en",
-                &format_args!("{}", self.function_clk_en().bit()),
-            )
-            .field("spi_swap", &format_args!("{}", self.spi_swap().bit()))
+            .field("function_clk_en", &self.function_clk_en())
+            .field("spi_swap", &self.spi_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SIGMADELTA_MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - Clock enable bit of sigma delta modulation."]
     #[inline(always)]
diff --git a/esp32s3/src/gpio_sd/version.rs b/esp32s3/src/gpio_sd/version.rs
index c5e0330a82..9acd6dd0bd 100644
--- a/esp32s3/src/gpio_sd/version.rs
+++ b/esp32s3/src/gpio_sd/version.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field(
-                "gpio_sd_date",
-                &format_args!("{}", self.gpio_sd_date().bits()),
-            )
+            .field("gpio_sd_date", &self.gpio_sd_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register."]
     #[inline(always)]
diff --git a/esp32s3/src/hmac/date.rs b/esp32s3/src/hmac/date.rs
index 2834a9d03b..4877971c34 100644
--- a/esp32s3/src/hmac/date.rs
+++ b/esp32s3/src/hmac/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/hmac/query_busy.rs b/esp32s3/src/hmac/query_busy.rs
index b2162c1fb3..6f817e76f4 100644
--- a/esp32s3/src/hmac/query_busy.rs
+++ b/esp32s3/src/hmac/query_busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_BUSY")
-            .field("busy_state", &format_args!("{}", self.busy_state().bit()))
+            .field("busy_state", &self.busy_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Busy register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_BUSY_SPEC;
 impl crate::RegisterSpec for QUERY_BUSY_SPEC {
diff --git a/esp32s3/src/hmac/query_error.rs b/esp32s3/src/hmac/query_error.rs
index dccd8dd32f..8f5b2d284b 100644
--- a/esp32s3/src/hmac/query_error.rs
+++ b/esp32s3/src/hmac/query_error.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUERY_ERROR")
-            .field("query_check", &format_args!("{}", self.query_check().bit()))
+            .field("query_check", &self.query_check())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUERY_ERROR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Error register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`query_error::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct QUERY_ERROR_SPEC;
 impl crate::RegisterSpec for QUERY_ERROR_SPEC {
diff --git a/esp32s3/src/hmac/rd_result_mem.rs b/esp32s3/src/hmac/rd_result_mem.rs
index e93fc1892c..15ad43ddc6 100644
--- a/esp32s3/src/hmac/rd_result_mem.rs
+++ b/esp32s3/src/hmac/rd_result_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_RESULT_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Result from upstream.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_result_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rd_result_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RD_RESULT_MEM_SPEC;
diff --git a/esp32s3/src/hmac/wr_message_mem.rs b/esp32s3/src/hmac/wr_message_mem.rs
index e4eda3e0e5..2779a44011 100644
--- a/esp32s3/src/hmac/wr_message_mem.rs
+++ b/esp32s3/src/hmac/wr_message_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WR_MESSAGE_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Message block memory.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_message_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_message_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WR_MESSAGE_MEM_SPEC;
diff --git a/esp32s3/src/i2c0/clk_conf.rs b/esp32s3/src/i2c0/clk_conf.rs
index 642ad9481a..283b362360 100644
--- a/esp32s3/src/i2c0/clk_conf.rs
+++ b/esp32s3/src/i2c0/clk_conf.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bit()))
-            .field("sclk_active", &format_args!("{}", self.sclk_active().bit()))
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_active", &self.sclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the integral part of the fractional divisor for i2c module"]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/comd.rs b/esp32s3/src/i2c0/comd.rs
index c9619bf55e..ed02e0bfe8 100644
--- a/esp32s3/src/i2c0/comd.rs
+++ b/esp32s3/src/i2c0/comd.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMD")
-            .field("command", &format_args!("{}", self.command().bits()))
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This is the content of command 0. It consists of three parts: op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/ctr.rs b/esp32s3/src/i2c0/ctr.rs
index 6466ebe778..e1ffab5bde 100644
--- a/esp32s3/src/i2c0/ctr.rs
+++ b/esp32s3/src/i2c0/ctr.rs
@@ -122,57 +122,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTR")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field(
-                "sample_scl_level",
-                &format_args!("{}", self.sample_scl_level().bit()),
-            )
-            .field(
-                "rx_full_ack_level",
-                &format_args!("{}", self.rx_full_ack_level().bit()),
-            )
-            .field("ms_mode", &format_args!("{}", self.ms_mode().bit()))
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "arbitration_en",
-                &format_args!("{}", self.arbitration_en().bit()),
-            )
-            .field(
-                "slv_tx_auto_start_en",
-                &format_args!("{}", self.slv_tx_auto_start_en().bit()),
-            )
-            .field(
-                "addr_10bit_rw_check_en",
-                &format_args!("{}", self.addr_10bit_rw_check_en().bit()),
-            )
-            .field(
-                "addr_broadcasting_en",
-                &format_args!("{}", self.addr_broadcasting_en().bit()),
-            )
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("sample_scl_level", &self.sample_scl_level())
+            .field("rx_full_ack_level", &self.rx_full_ack_level())
+            .field("ms_mode", &self.ms_mode())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("clk_en", &self.clk_en())
+            .field("arbitration_en", &self.arbitration_en())
+            .field("slv_tx_auto_start_en", &self.slv_tx_auto_start_en())
+            .field("addr_10bit_rw_check_en", &self.addr_10bit_rw_check_en())
+            .field("addr_broadcasting_en", &self.addr_broadcasting_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 0: direct output; 1: open drain output."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/data.rs b/esp32s3/src/i2c0/data.rs
index 098982488f..ffd32b29d3 100644
--- a/esp32s3/src/i2c0/data.rs
+++ b/esp32s3/src/i2c0/data.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field("fifo_rdata", &format_args!("{}", self.fifo_rdata().bits()))
+            .field("fifo_rdata", &self.fifo_rdata())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The value of rx FIFO read data."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/date.rs b/esp32s3/src/i2c0/date.rs
index ba4509f6e0..894b12744c 100644
--- a/esp32s3/src/i2c0/date.rs
+++ b/esp32s3/src/i2c0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/i2c0/fifo_conf.rs b/esp32s3/src/i2c0/fifo_conf.rs
index a676b90a14..92deed8594 100644
--- a/esp32s3/src/i2c0/fifo_conf.rs
+++ b/esp32s3/src/i2c0/fifo_conf.rs
@@ -71,31 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_CONF")
-            .field(
-                "rxfifo_wm_thrhd",
-                &format_args!("{}", self.rxfifo_wm_thrhd().bits()),
-            )
-            .field(
-                "txfifo_wm_thrhd",
-                &format_args!("{}", self.txfifo_wm_thrhd().bits()),
-            )
-            .field("nonfifo_en", &format_args!("{}", self.nonfifo_en().bit()))
-            .field(
-                "fifo_addr_cfg_en",
-                &format_args!("{}", self.fifo_addr_cfg_en().bit()),
-            )
-            .field("rx_fifo_rst", &format_args!("{}", self.rx_fifo_rst().bit()))
-            .field("tx_fifo_rst", &format_args!("{}", self.tx_fifo_rst().bit()))
-            .field("fifo_prt_en", &format_args!("{}", self.fifo_prt_en().bit()))
+            .field("rxfifo_wm_thrhd", &self.rxfifo_wm_thrhd())
+            .field("txfifo_wm_thrhd", &self.txfifo_wm_thrhd())
+            .field("nonfifo_en", &self.nonfifo_en())
+            .field("fifo_addr_cfg_en", &self.fifo_addr_cfg_en())
+            .field("rx_fifo_rst", &self.rx_fifo_rst())
+            .field("tx_fifo_rst", &self.tx_fifo_rst())
+            .field("fifo_prt_en", &self.fifo_prt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd\\[4:0\\], reg_rxfifo_wm_int_raw bit will be valid."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/fifo_st.rs b/esp32s3/src/i2c0/fifo_st.rs
index 40f2594a2b..03188e5485 100644
--- a/esp32s3/src/i2c0/fifo_st.rs
+++ b/esp32s3/src/i2c0/fifo_st.rs
@@ -41,35 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO_ST")
-            .field(
-                "rxfifo_raddr",
-                &format_args!("{}", self.rxfifo_raddr().bits()),
-            )
-            .field(
-                "rxfifo_waddr",
-                &format_args!("{}", self.rxfifo_waddr().bits()),
-            )
-            .field(
-                "txfifo_raddr",
-                &format_args!("{}", self.txfifo_raddr().bits()),
-            )
-            .field(
-                "txfifo_waddr",
-                &format_args!("{}", self.txfifo_waddr().bits()),
-            )
-            .field(
-                "slave_rw_point",
-                &format_args!("{}", self.slave_rw_point().bits()),
-            )
+            .field("rxfifo_raddr", &self.rxfifo_raddr())
+            .field("rxfifo_waddr", &self.rxfifo_waddr())
+            .field("txfifo_raddr", &self.txfifo_raddr())
+            .field("txfifo_waddr", &self.txfifo_waddr())
+            .field("slave_rw_point", &self.slave_rw_point())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "FIFO status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FIFO_ST_SPEC;
 impl crate::RegisterSpec for FIFO_ST_SPEC {
diff --git a/esp32s3/src/i2c0/filter_cfg.rs b/esp32s3/src/i2c0/filter_cfg.rs
index b05ae9a4bf..98bdaa5979 100644
--- a/esp32s3/src/i2c0/filter_cfg.rs
+++ b/esp32s3/src/i2c0/filter_cfg.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FILTER_CFG")
-            .field(
-                "scl_filter_thres",
-                &format_args!("{}", self.scl_filter_thres().bits()),
-            )
-            .field(
-                "sda_filter_thres",
-                &format_args!("{}", self.sda_filter_thres().bits()),
-            )
-            .field(
-                "scl_filter_en",
-                &format_args!("{}", self.scl_filter_en().bit()),
-            )
-            .field(
-                "sda_filter_en",
-                &format_args!("{}", self.sda_filter_en().bit()),
-            )
+            .field("scl_filter_thres", &self.scl_filter_thres())
+            .field("sda_filter_thres", &self.sda_filter_thres())
+            .field("scl_filter_en", &self.scl_filter_en())
+            .field("sda_filter_en", &self.sda_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FILTER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/int_ena.rs b/esp32s3/src/i2c0/int_ena.rs
index fe3fb0ed14..4b4a5cf26f 100644
--- a/esp32s3/src/i2c0/int_ena.rs
+++ b/esp32s3/src/i2c0/int_ena.rs
@@ -170,54 +170,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
-            .field(
-                "general_call",
-                &format_args!("{}", self.general_call().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
+            .field("general_call", &self.general_call())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/int_raw.rs b/esp32s3/src/i2c0/int_raw.rs
index 34fc9a6a4e..5585885139 100644
--- a/esp32s3/src/i2c0/int_raw.rs
+++ b/esp32s3/src/i2c0/int_raw.rs
@@ -132,54 +132,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
-            .field(
-                "general_call",
-                &format_args!("{}", self.general_call().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
+            .field("general_call", &self.general_call())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s3/src/i2c0/int_st.rs b/esp32s3/src/i2c0/int_st.rs
index 6a1558ea32..45c6f184a0 100644
--- a/esp32s3/src/i2c0/int_st.rs
+++ b/esp32s3/src/i2c0/int_st.rs
@@ -132,54 +132,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_wm", &format_args!("{}", self.rxfifo_wm().bit()))
-            .field("txfifo_wm", &format_args!("{}", self.txfifo_wm().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("end_detect", &format_args!("{}", self.end_detect().bit()))
-            .field(
-                "byte_trans_done",
-                &format_args!("{}", self.byte_trans_done().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "mst_txfifo_udf",
-                &format_args!("{}", self.mst_txfifo_udf().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("txfifo_ovf", &format_args!("{}", self.txfifo_ovf().bit()))
-            .field("rxfifo_udf", &format_args!("{}", self.rxfifo_udf().bit()))
-            .field("scl_st_to", &format_args!("{}", self.scl_st_to().bit()))
-            .field(
-                "scl_main_st_to",
-                &format_args!("{}", self.scl_main_st_to().bit()),
-            )
-            .field("det_start", &format_args!("{}", self.det_start().bit()))
-            .field(
-                "slave_stretch",
-                &format_args!("{}", self.slave_stretch().bit()),
-            )
-            .field(
-                "general_call",
-                &format_args!("{}", self.general_call().bit()),
-            )
+            .field("rxfifo_wm", &self.rxfifo_wm())
+            .field("txfifo_wm", &self.txfifo_wm())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("end_detect", &self.end_detect())
+            .field("byte_trans_done", &self.byte_trans_done())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("trans_start", &self.trans_start())
+            .field("nack", &self.nack())
+            .field("txfifo_ovf", &self.txfifo_ovf())
+            .field("rxfifo_udf", &self.rxfifo_udf())
+            .field("scl_st_to", &self.scl_st_to())
+            .field("scl_main_st_to", &self.scl_main_st_to())
+            .field("det_start", &self.det_start())
+            .field("slave_stretch", &self.slave_stretch())
+            .field("general_call", &self.general_call())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of captured I2C communication events\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/i2c0/rxfifo_start_addr.rs b/esp32s3/src/i2c0/rxfifo_start_addr.rs
index 634e8c8360..be2fa3cb09 100644
--- a/esp32s3/src/i2c0/rxfifo_start_addr.rs
+++ b/esp32s3/src/i2c0/rxfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXFIFO_START_ADDR")
-            .field(
-                "rxfifo_start_addr",
-                &format_args!("{}", self.rxfifo_start_addr().bits()),
-            )
+            .field("rxfifo_start_addr", &self.rxfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C RXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for RXFIFO_START_ADDR_SPEC {
diff --git a/esp32s3/src/i2c0/scl_high_period.rs b/esp32s3/src/i2c0/scl_high_period.rs
index 2af2564e19..3155621a91 100644
--- a/esp32s3/src/i2c0/scl_high_period.rs
+++ b/esp32s3/src/i2c0/scl_high_period.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH_PERIOD")
-            .field(
-                "scl_high_period",
-                &format_args!("{}", self.scl_high_period().bits()),
-            )
-            .field(
-                "scl_wait_high_period",
-                &format_args!("{}", self.scl_wait_high_period().bits()),
-            )
+            .field("scl_high_period", &self.scl_high_period())
+            .field("scl_wait_high_period", &self.scl_wait_high_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/scl_low_period.rs b/esp32s3/src/i2c0/scl_low_period.rs
index bb4cd05e6d..c75461f0c7 100644
--- a/esp32s3/src/i2c0/scl_low_period.rs
+++ b/esp32s3/src/i2c0/scl_low_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW_PERIOD")
-            .field(
-                "scl_low_period",
-                &format_args!("{}", self.scl_low_period().bits()),
-            )
+            .field("scl_low_period", &self.scl_low_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/scl_main_st_time_out.rs b/esp32s3/src/i2c0/scl_main_st_time_out.rs
index 7c392d273a..99069d3ce8 100644
--- a/esp32s3/src/i2c0/scl_main_st_time_out.rs
+++ b/esp32s3/src/i2c0/scl_main_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_MAIN_ST_TIME_OUT")
-            .field(
-                "scl_main_st_to_i2c",
-                &format_args!("{}", self.scl_main_st_to_i2c().bits()),
-            )
+            .field("scl_main_st_to_i2c", &self.scl_main_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_MAIN_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23"]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/scl_rstart_setup.rs b/esp32s3/src/i2c0/scl_rstart_setup.rs
index 5f61d4fc91..63ddddc0f2 100644
--- a/esp32s3/src/i2c0/scl_rstart_setup.rs
+++ b/esp32s3/src/i2c0/scl_rstart_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_RSTART_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_RSTART_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/scl_sp_conf.rs b/esp32s3/src/i2c0/scl_sp_conf.rs
index e3cdc353bf..492452e245 100644
--- a/esp32s3/src/i2c0/scl_sp_conf.rs
+++ b/esp32s3/src/i2c0/scl_sp_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_SP_CONF")
-            .field(
-                "scl_rst_slv_en",
-                &format_args!("{}", self.scl_rst_slv_en().bit()),
-            )
-            .field(
-                "scl_rst_slv_num",
-                &format_args!("{}", self.scl_rst_slv_num().bits()),
-            )
-            .field("scl_pd_en", &format_args!("{}", self.scl_pd_en().bit()))
-            .field("sda_pd_en", &format_args!("{}", self.sda_pd_en().bit()))
+            .field("scl_rst_slv_en", &self.scl_rst_slv_en())
+            .field("scl_rst_slv_num", &self.scl_rst_slv_num())
+            .field("scl_pd_en", &self.scl_pd_en())
+            .field("sda_pd_en", &self.sda_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_SP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/scl_st_time_out.rs b/esp32s3/src/i2c0/scl_st_time_out.rs
index ba02a4a885..e56dd94c72 100644
--- a/esp32s3/src/i2c0/scl_st_time_out.rs
+++ b/esp32s3/src/i2c0/scl_st_time_out.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_ST_TIME_OUT")
-            .field(
-                "scl_st_to_i2c",
-                &format_args!("{}", self.scl_st_to_i2c().bits()),
-            )
+            .field("scl_st_to_i2c", &self.scl_st_to_i2c())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_ST_TIME_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - The threshold value of SCL_FSM state unchanged period. It should be o more than 23"]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/scl_start_hold.rs b/esp32s3/src/i2c0/scl_start_hold.rs
index eaa7d6ef78..073d03f4ca 100644
--- a/esp32s3/src/i2c0/scl_start_hold.rs
+++ b/esp32s3/src/i2c0/scl_start_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/scl_stop_hold.rs b/esp32s3/src/i2c0/scl_stop_hold.rs
index edfbb10e29..3a115f7912 100644
--- a/esp32s3/src/i2c0/scl_stop_hold.rs
+++ b/esp32s3/src/i2c0/scl_stop_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the delay after the STOP condition, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/scl_stop_setup.rs b/esp32s3/src/i2c0/scl_stop_setup.rs
index f231319c28..592044b6a2 100644
--- a/esp32s3/src/i2c0/scl_stop_setup.rs
+++ b/esp32s3/src/i2c0/scl_stop_setup.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_SETUP")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_SETUP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/scl_stretch_conf.rs b/esp32s3/src/i2c0/scl_stretch_conf.rs
index 41ef0b914c..541e31a624 100644
--- a/esp32s3/src/i2c0/scl_stretch_conf.rs
+++ b/esp32s3/src/i2c0/scl_stretch_conf.rs
@@ -46,31 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STRETCH_CONF")
-            .field(
-                "stretch_protect_num",
-                &format_args!("{}", self.stretch_protect_num().bits()),
-            )
-            .field(
-                "slave_scl_stretch_en",
-                &format_args!("{}", self.slave_scl_stretch_en().bit()),
-            )
-            .field(
-                "slave_byte_ack_ctl_en",
-                &format_args!("{}", self.slave_byte_ack_ctl_en().bit()),
-            )
-            .field(
-                "slave_byte_ack_lvl",
-                &format_args!("{}", self.slave_byte_ack_lvl().bit()),
-            )
+            .field("stretch_protect_num", &self.stretch_protect_num())
+            .field("slave_scl_stretch_en", &self.slave_scl_stretch_en())
+            .field("slave_byte_ack_ctl_en", &self.slave_byte_ack_ctl_en())
+            .field("slave_byte_ack_lvl", &self.slave_byte_ack_lvl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STRETCH_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - Configure the period of I2C slave stretching SCL line."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/sda_hold.rs b/esp32s3/src/i2c0/sda_hold.rs
index b16485e33b..817872197e 100644
--- a/esp32s3/src/i2c0/sda_hold.rs
+++ b/esp32s3/src/i2c0/sda_hold.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_HOLD")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the time to hold the data after the negative edge of SCL, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/sda_sample.rs b/esp32s3/src/i2c0/sda_sample.rs
index 5a56fc1aa2..a8bd733614 100644
--- a/esp32s3/src/i2c0/sda_sample.rs
+++ b/esp32s3/src/i2c0/sda_sample.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_SAMPLE")
-            .field("time", &format_args!("{}", self.time().bits()))
+            .field("time", &self.time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_SAMPLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure for how long SDA is sampled, in I2C module clock cycles."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/slave_addr.rs b/esp32s3/src/i2c0/slave_addr.rs
index 004dabd9bb..04cdd14f36 100644
--- a/esp32s3/src/i2c0/slave_addr.rs
+++ b/esp32s3/src/i2c0/slave_addr.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE_ADDR")
-            .field("slave_addr", &format_args!("{}", self.slave_addr().bits()))
-            .field(
-                "addr_10bit_en",
-                &format_args!("{}", self.addr_10bit_en().bit()),
-            )
+            .field("slave_addr", &self.slave_addr())
+            .field("addr_10bit_en", &self.addr_10bit_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - When configured as an I2C Slave, this field is used to configure the slave address."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/sr.rs b/esp32s3/src/i2c0/sr.rs
index f24fdfcf72..f63342d604 100644
--- a/esp32s3/src/i2c0/sr.rs
+++ b/esp32s3/src/i2c0/sr.rs
@@ -76,37 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SR")
-            .field("resp_rec", &format_args!("{}", self.resp_rec().bit()))
-            .field("slave_rw", &format_args!("{}", self.slave_rw().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field(
-                "slave_addressed",
-                &format_args!("{}", self.slave_addressed().bit()),
-            )
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field(
-                "stretch_cause",
-                &format_args!("{}", self.stretch_cause().bits()),
-            )
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field(
-                "scl_main_state_last",
-                &format_args!("{}", self.scl_main_state_last().bits()),
-            )
-            .field(
-                "scl_state_last",
-                &format_args!("{}", self.scl_state_last().bits()),
-            )
+            .field("resp_rec", &self.resp_rec())
+            .field("slave_rw", &self.slave_rw())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("slave_addressed", &self.slave_addressed())
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("stretch_cause", &self.stretch_cause())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("scl_main_state_last", &self.scl_main_state_last())
+            .field("scl_state_last", &self.scl_state_last())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Describe I2C work status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SR_SPEC;
 impl crate::RegisterSpec for SR_SPEC {
diff --git a/esp32s3/src/i2c0/to.rs b/esp32s3/src/i2c0/to.rs
index 92f73cdd2b..cf95ff843d 100644
--- a/esp32s3/src/i2c0/to.rs
+++ b/esp32s3/src/i2c0/to.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO")
-            .field(
-                "time_out_value",
-                &format_args!("{}", self.time_out_value().bits()),
-            )
-            .field("time_out_en", &format_args!("{}", self.time_out_en().bit()))
+            .field("time_out_value", &self.time_out_value())
+            .field("time_out_en", &self.time_out_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - This register is used to configure the timeout for receiving a data bit in APB clock cycles."]
     #[inline(always)]
diff --git a/esp32s3/src/i2c0/txfifo_start_addr.rs b/esp32s3/src/i2c0/txfifo_start_addr.rs
index 8df0b6828e..c7cd4f0ea5 100644
--- a/esp32s3/src/i2c0/txfifo_start_addr.rs
+++ b/esp32s3/src/i2c0/txfifo_start_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXFIFO_START_ADDR")
-            .field(
-                "txfifo_start_addr",
-                &format_args!("{}", self.txfifo_start_addr().bits()),
-            )
+            .field("txfifo_start_addr", &self.txfifo_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXFIFO_START_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2C TXFIFO base address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifo_start_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TXFIFO_START_ADDR_SPEC;
 impl crate::RegisterSpec for TXFIFO_START_ADDR_SPEC {
diff --git a/esp32s3/src/i2s0/conf_sigle_data.rs b/esp32s3/src/i2s0/conf_sigle_data.rs
index f979345988..3c75f59255 100644
--- a/esp32s3/src/i2s0/conf_sigle_data.rs
+++ b/esp32s3/src/i2s0/conf_sigle_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_SIGLE_DATA")
-            .field(
-                "single_data",
-                &format_args!("{}", self.single_data().bits()),
-            )
+            .field("single_data", &self.single_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SIGLE_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The configured constant channel data to be sent out."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/date.rs b/esp32s3/src/i2s0/date.rs
index 3364ff98f6..ee83431298 100644
--- a/esp32s3/src/i2s0/date.rs
+++ b/esp32s3/src/i2s0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/i2s0/int_ena.rs b/esp32s3/src/i2s0/int_ena.rs
index ffbc92bacc..0a538b90e5 100644
--- a/esp32s3/src/i2s0/int_ena.rs
+++ b/esp32s3/src/i2s0/int_ena.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/int_raw.rs b/esp32s3/src/i2s0/int_raw.rs
index 7ec2d42cfd..e69602c0be 100644
--- a/esp32s3/src/i2s0/int_raw.rs
+++ b/esp32s3/src/i2s0/int_raw.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s3/src/i2s0/int_st.rs b/esp32s3/src/i2s0/int_st.rs
index 5eac7b9c9d..ddf72a352e 100644
--- a/esp32s3/src/i2s0/int_st.rs
+++ b/esp32s3/src/i2s0/int_st.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/i2s0/lc_hung_conf.rs b/esp32s3/src/i2s0/lc_hung_conf.rs
index 060b1cdb60..71f0c84fa7 100644
--- a/esp32s3/src/i2s0/lc_hung_conf.rs
+++ b/esp32s3/src/i2s0/lc_hung_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_HUNG_CONF")
-            .field(
-                "lc_fifo_timeout",
-                &format_args!("{}", self.lc_fifo_timeout().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_shift",
-                &format_args!("{}", self.lc_fifo_timeout_shift().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_ena",
-                &format_args!("{}", self.lc_fifo_timeout_ena().bit()),
-            )
+            .field("lc_fifo_timeout", &self.lc_fifo_timeout())
+            .field("lc_fifo_timeout_shift", &self.lc_fifo_timeout_shift())
+            .field("lc_fifo_timeout_ena", &self.lc_fifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/rx_clkm_conf.rs b/esp32s3/src/i2s0/rx_clkm_conf.rs
index 79ff9b2470..5bbb7a360a 100644
--- a/esp32s3/src/i2s0/rx_clkm_conf.rs
+++ b/esp32s3/src/i2s0/rx_clkm_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CLKM_CONF")
-            .field(
-                "rx_clkm_div_num",
-                &format_args!("{}", self.rx_clkm_div_num().bits()),
-            )
-            .field(
-                "rx_clk_active",
-                &format_args!("{}", self.rx_clk_active().bit()),
-            )
-            .field("rx_clk_sel", &format_args!("{}", self.rx_clk_sel().bits()))
-            .field("mclk_sel", &format_args!("{}", self.mclk_sel().bit()))
+            .field("rx_clkm_div_num", &self.rx_clkm_div_num())
+            .field("rx_clk_active", &self.rx_clk_active())
+            .field("rx_clk_sel", &self.rx_clk_sel())
+            .field("mclk_sel", &self.mclk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral I2S clock divider value"]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/rx_clkm_div_conf.rs b/esp32s3/src/i2s0/rx_clkm_div_conf.rs
index 9dc32721ed..d4f0ee53bc 100644
--- a/esp32s3/src/i2s0/rx_clkm_div_conf.rs
+++ b/esp32s3/src/i2s0/rx_clkm_div_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CLKM_DIV_CONF")
-            .field(
-                "rx_clkm_div_z",
-                &format_args!("{}", self.rx_clkm_div_z().bits()),
-            )
-            .field(
-                "rx_clkm_div_y",
-                &format_args!("{}", self.rx_clkm_div_y().bits()),
-            )
-            .field(
-                "rx_clkm_div_x",
-                &format_args!("{}", self.rx_clkm_div_x().bits()),
-            )
-            .field(
-                "rx_clkm_div_yn1",
-                &format_args!("{}", self.rx_clkm_div_yn1().bit()),
-            )
+            .field("rx_clkm_div_z", &self.rx_clkm_div_z())
+            .field("rx_clkm_div_y", &self.rx_clkm_div_y())
+            .field("rx_clkm_div_x", &self.rx_clkm_div_x())
+            .field("rx_clkm_div_yn1", &self.rx_clkm_div_yn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CLKM_DIV_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/rx_conf.rs b/esp32s3/src/i2s0/rx_conf.rs
index b1896c37ce..e8facf63f5 100644
--- a/esp32s3/src/i2s0/rx_conf.rs
+++ b/esp32s3/src/i2s0/rx_conf.rs
@@ -165,68 +165,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CONF")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field(
-                "rx_slave_mod",
-                &format_args!("{}", self.rx_slave_mod().bit()),
-            )
-            .field("rx_mono", &format_args!("{}", self.rx_mono().bit()))
-            .field(
-                "rx_big_endian",
-                &format_args!("{}", self.rx_big_endian().bit()),
-            )
-            .field("rx_update", &format_args!("{}", self.rx_update().bit()))
-            .field(
-                "rx_mono_fst_vld",
-                &format_args!("{}", self.rx_mono_fst_vld().bit()),
-            )
-            .field(
-                "rx_pcm_conf",
-                &format_args!("{}", self.rx_pcm_conf().bits()),
-            )
-            .field(
-                "rx_pcm_bypass",
-                &format_args!("{}", self.rx_pcm_bypass().bit()),
-            )
-            .field(
-                "rx_stop_mode",
-                &format_args!("{}", self.rx_stop_mode().bits()),
-            )
-            .field(
-                "rx_left_align",
-                &format_args!("{}", self.rx_left_align().bit()),
-            )
-            .field(
-                "rx_24_fill_en",
-                &format_args!("{}", self.rx_24_fill_en().bit()),
-            )
-            .field(
-                "rx_ws_idle_pol",
-                &format_args!("{}", self.rx_ws_idle_pol().bit()),
-            )
-            .field(
-                "rx_bit_order",
-                &format_args!("{}", self.rx_bit_order().bit()),
-            )
-            .field("rx_tdm_en", &format_args!("{}", self.rx_tdm_en().bit()))
-            .field("rx_pdm_en", &format_args!("{}", self.rx_pdm_en().bit()))
-            .field(
-                "rx_pdm2pcm_en",
-                &format_args!("{}", self.rx_pdm2pcm_en().bit()),
-            )
-            .field(
-                "rx_pdm_sinc_dsr_16_en",
-                &format_args!("{}", self.rx_pdm_sinc_dsr_16_en().bit()),
-            )
+            .field("rx_start", &self.rx_start())
+            .field("rx_slave_mod", &self.rx_slave_mod())
+            .field("rx_mono", &self.rx_mono())
+            .field("rx_big_endian", &self.rx_big_endian())
+            .field("rx_update", &self.rx_update())
+            .field("rx_mono_fst_vld", &self.rx_mono_fst_vld())
+            .field("rx_pcm_conf", &self.rx_pcm_conf())
+            .field("rx_pcm_bypass", &self.rx_pcm_bypass())
+            .field("rx_stop_mode", &self.rx_stop_mode())
+            .field("rx_left_align", &self.rx_left_align())
+            .field("rx_24_fill_en", &self.rx_24_fill_en())
+            .field("rx_ws_idle_pol", &self.rx_ws_idle_pol())
+            .field("rx_bit_order", &self.rx_bit_order())
+            .field("rx_tdm_en", &self.rx_tdm_en())
+            .field("rx_pdm_en", &self.rx_pdm_en())
+            .field("rx_pdm2pcm_en", &self.rx_pdm2pcm_en())
+            .field("rx_pdm_sinc_dsr_16_en", &self.rx_pdm_sinc_dsr_16_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset receiver"]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/rx_conf1.rs b/esp32s3/src/i2s0/rx_conf1.rs
index 24c13494fb..31fa7a1f88 100644
--- a/esp32s3/src/i2s0/rx_conf1.rs
+++ b/esp32s3/src/i2s0/rx_conf1.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CONF1")
-            .field(
-                "rx_tdm_ws_width",
-                &format_args!("{}", self.rx_tdm_ws_width().bits()),
-            )
-            .field(
-                "rx_bck_div_num",
-                &format_args!("{}", self.rx_bck_div_num().bits()),
-            )
-            .field(
-                "rx_bits_mod",
-                &format_args!("{}", self.rx_bits_mod().bits()),
-            )
-            .field(
-                "rx_half_sample_bits",
-                &format_args!("{}", self.rx_half_sample_bits().bits()),
-            )
-            .field(
-                "rx_tdm_chan_bits",
-                &format_args!("{}", self.rx_tdm_chan_bits().bits()),
-            )
-            .field(
-                "rx_msb_shift",
-                &format_args!("{}", self.rx_msb_shift().bit()),
-            )
+            .field("rx_tdm_ws_width", &self.rx_tdm_ws_width())
+            .field("rx_bck_div_num", &self.rx_bck_div_num())
+            .field("rx_bits_mod", &self.rx_bits_mod())
+            .field("rx_half_sample_bits", &self.rx_half_sample_bits())
+            .field("rx_tdm_chan_bits", &self.rx_tdm_chan_bits())
+            .field("rx_msb_shift", &self.rx_msb_shift())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/rx_tdm_ctrl.rs b/esp32s3/src/i2s0/rx_tdm_ctrl.rs
index fe01f97aeb..0d18f522f2 100644
--- a/esp32s3/src/i2s0/rx_tdm_ctrl.rs
+++ b/esp32s3/src/i2s0/rx_tdm_ctrl.rs
@@ -161,83 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_TDM_CTRL")
-            .field(
-                "rx_tdm_pdm_chan0_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan0_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan1_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan1_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan2_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan2_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan3_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan3_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan4_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan4_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan5_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan5_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan6_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan6_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan7_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan7_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan8_en",
-                &format_args!("{}", self.rx_tdm_chan8_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan9_en",
-                &format_args!("{}", self.rx_tdm_chan9_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan10_en",
-                &format_args!("{}", self.rx_tdm_chan10_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan11_en",
-                &format_args!("{}", self.rx_tdm_chan11_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan12_en",
-                &format_args!("{}", self.rx_tdm_chan12_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan13_en",
-                &format_args!("{}", self.rx_tdm_chan13_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan14_en",
-                &format_args!("{}", self.rx_tdm_chan14_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan15_en",
-                &format_args!("{}", self.rx_tdm_chan15_en().bit()),
-            )
-            .field(
-                "rx_tdm_tot_chan_num",
-                &format_args!("{}", self.rx_tdm_tot_chan_num().bits()),
-            )
+            .field("rx_tdm_pdm_chan0_en", &self.rx_tdm_pdm_chan0_en())
+            .field("rx_tdm_pdm_chan1_en", &self.rx_tdm_pdm_chan1_en())
+            .field("rx_tdm_pdm_chan2_en", &self.rx_tdm_pdm_chan2_en())
+            .field("rx_tdm_pdm_chan3_en", &self.rx_tdm_pdm_chan3_en())
+            .field("rx_tdm_pdm_chan4_en", &self.rx_tdm_pdm_chan4_en())
+            .field("rx_tdm_pdm_chan5_en", &self.rx_tdm_pdm_chan5_en())
+            .field("rx_tdm_pdm_chan6_en", &self.rx_tdm_pdm_chan6_en())
+            .field("rx_tdm_pdm_chan7_en", &self.rx_tdm_pdm_chan7_en())
+            .field("rx_tdm_chan8_en", &self.rx_tdm_chan8_en())
+            .field("rx_tdm_chan9_en", &self.rx_tdm_chan9_en())
+            .field("rx_tdm_chan10_en", &self.rx_tdm_chan10_en())
+            .field("rx_tdm_chan11_en", &self.rx_tdm_chan11_en())
+            .field("rx_tdm_chan12_en", &self.rx_tdm_chan12_en())
+            .field("rx_tdm_chan13_en", &self.rx_tdm_chan13_en())
+            .field("rx_tdm_chan14_en", &self.rx_tdm_chan14_en())
+            .field("rx_tdm_chan15_en", &self.rx_tdm_chan15_en())
+            .field("rx_tdm_tot_chan_num", &self.rx_tdm_tot_chan_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_TDM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/rx_timing.rs b/esp32s3/src/i2s0/rx_timing.rs
index 872c8ee1b5..7ae3ab60d7 100644
--- a/esp32s3/src/i2s0/rx_timing.rs
+++ b/esp32s3/src/i2s0/rx_timing.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_TIMING")
-            .field(
-                "rx_sd_in_dm",
-                &format_args!("{}", self.rx_sd_in_dm().bits()),
-            )
-            .field(
-                "rx_sd1_in_dm",
-                &format_args!("{}", self.rx_sd1_in_dm().bits()),
-            )
-            .field(
-                "rx_sd2_in_dm",
-                &format_args!("{}", self.rx_sd2_in_dm().bits()),
-            )
-            .field(
-                "rx_sd3_in_dm",
-                &format_args!("{}", self.rx_sd3_in_dm().bits()),
-            )
-            .field(
-                "rx_ws_out_dm",
-                &format_args!("{}", self.rx_ws_out_dm().bits()),
-            )
-            .field(
-                "rx_bck_out_dm",
-                &format_args!("{}", self.rx_bck_out_dm().bits()),
-            )
-            .field(
-                "rx_ws_in_dm",
-                &format_args!("{}", self.rx_ws_in_dm().bits()),
-            )
-            .field(
-                "rx_bck_in_dm",
-                &format_args!("{}", self.rx_bck_in_dm().bits()),
-            )
+            .field("rx_sd_in_dm", &self.rx_sd_in_dm())
+            .field("rx_sd1_in_dm", &self.rx_sd1_in_dm())
+            .field("rx_sd2_in_dm", &self.rx_sd2_in_dm())
+            .field("rx_sd3_in_dm", &self.rx_sd3_in_dm())
+            .field("rx_ws_out_dm", &self.rx_ws_out_dm())
+            .field("rx_bck_out_dm", &self.rx_bck_out_dm())
+            .field("rx_ws_in_dm", &self.rx_ws_in_dm())
+            .field("rx_bck_in_dm", &self.rx_bck_in_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/rxeof_num.rs b/esp32s3/src/i2s0/rxeof_num.rs
index 06f6d22ff0..b9674d5891 100644
--- a/esp32s3/src/i2s0/rxeof_num.rs
+++ b/esp32s3/src/i2s0/rxeof_num.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXEOF_NUM")
-            .field("rx_eof_num", &format_args!("{}", self.rx_eof_num().bits()))
+            .field("rx_eof_num", &self.rx_eof_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXEOF_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/state.rs b/esp32s3/src/i2s0/state.rs
index 7988d4067c..d16247a40d 100644
--- a/esp32s3/src/i2s0/state.rs
+++ b/esp32s3/src/i2s0/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("tx_idle", &format_args!("{}", self.tx_idle().bit()))
+            .field("tx_idle", &self.tx_idle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S TX status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32s3/src/i2s0/tx_clkm_conf.rs b/esp32s3/src/i2s0/tx_clkm_conf.rs
index ef82d04116..2584244722 100644
--- a/esp32s3/src/i2s0/tx_clkm_conf.rs
+++ b/esp32s3/src/i2s0/tx_clkm_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CLKM_CONF")
-            .field(
-                "tx_clkm_div_num",
-                &format_args!("{}", self.tx_clkm_div_num().bits()),
-            )
-            .field(
-                "tx_clk_active",
-                &format_args!("{}", self.tx_clk_active().bit()),
-            )
-            .field("tx_clk_sel", &format_args!("{}", self.tx_clk_sel().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("tx_clkm_div_num", &self.tx_clkm_div_num())
+            .field("tx_clk_active", &self.tx_clk_active())
+            .field("tx_clk_sel", &self.tx_clk_sel())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b &lt;= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/tx_clkm_div_conf.rs b/esp32s3/src/i2s0/tx_clkm_div_conf.rs
index eb02e39a99..8421d21999 100644
--- a/esp32s3/src/i2s0/tx_clkm_div_conf.rs
+++ b/esp32s3/src/i2s0/tx_clkm_div_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CLKM_DIV_CONF")
-            .field(
-                "tx_clkm_div_z",
-                &format_args!("{}", self.tx_clkm_div_z().bits()),
-            )
-            .field(
-                "tx_clkm_div_y",
-                &format_args!("{}", self.tx_clkm_div_y().bits()),
-            )
-            .field(
-                "tx_clkm_div_x",
-                &format_args!("{}", self.tx_clkm_div_x().bits()),
-            )
-            .field(
-                "tx_clkm_div_yn1",
-                &format_args!("{}", self.tx_clkm_div_yn1().bit()),
-            )
+            .field("tx_clkm_div_z", &self.tx_clkm_div_z())
+            .field("tx_clkm_div_y", &self.tx_clkm_div_y())
+            .field("tx_clkm_div_x", &self.tx_clkm_div_x())
+            .field("tx_clkm_div_yn1", &self.tx_clkm_div_yn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CLKM_DIV_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/tx_conf.rs b/esp32s3/src/i2s0/tx_conf.rs
index b10d6ccc62..83a890333d 100644
--- a/esp32s3/src/i2s0/tx_conf.rs
+++ b/esp32s3/src/i2s0/tx_conf.rs
@@ -174,69 +174,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CONF")
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field(
-                "tx_slave_mod",
-                &format_args!("{}", self.tx_slave_mod().bit()),
-            )
-            .field("tx_mono", &format_args!("{}", self.tx_mono().bit()))
-            .field(
-                "tx_chan_equal",
-                &format_args!("{}", self.tx_chan_equal().bit()),
-            )
-            .field(
-                "tx_big_endian",
-                &format_args!("{}", self.tx_big_endian().bit()),
-            )
-            .field("tx_update", &format_args!("{}", self.tx_update().bit()))
-            .field(
-                "tx_mono_fst_vld",
-                &format_args!("{}", self.tx_mono_fst_vld().bit()),
-            )
-            .field(
-                "tx_pcm_conf",
-                &format_args!("{}", self.tx_pcm_conf().bits()),
-            )
-            .field(
-                "tx_pcm_bypass",
-                &format_args!("{}", self.tx_pcm_bypass().bit()),
-            )
-            .field("tx_stop_en", &format_args!("{}", self.tx_stop_en().bit()))
-            .field(
-                "tx_left_align",
-                &format_args!("{}", self.tx_left_align().bit()),
-            )
-            .field(
-                "tx_24_fill_en",
-                &format_args!("{}", self.tx_24_fill_en().bit()),
-            )
-            .field(
-                "tx_ws_idle_pol",
-                &format_args!("{}", self.tx_ws_idle_pol().bit()),
-            )
-            .field(
-                "tx_bit_order",
-                &format_args!("{}", self.tx_bit_order().bit()),
-            )
-            .field("tx_tdm_en", &format_args!("{}", self.tx_tdm_en().bit()))
-            .field("tx_pdm_en", &format_args!("{}", self.tx_pdm_en().bit()))
-            .field(
-                "tx_chan_mod",
-                &format_args!("{}", self.tx_chan_mod().bits()),
-            )
-            .field(
-                "sig_loopback",
-                &format_args!("{}", self.sig_loopback().bit()),
-            )
+            .field("tx_start", &self.tx_start())
+            .field("tx_slave_mod", &self.tx_slave_mod())
+            .field("tx_mono", &self.tx_mono())
+            .field("tx_chan_equal", &self.tx_chan_equal())
+            .field("tx_big_endian", &self.tx_big_endian())
+            .field("tx_update", &self.tx_update())
+            .field("tx_mono_fst_vld", &self.tx_mono_fst_vld())
+            .field("tx_pcm_conf", &self.tx_pcm_conf())
+            .field("tx_pcm_bypass", &self.tx_pcm_bypass())
+            .field("tx_stop_en", &self.tx_stop_en())
+            .field("tx_left_align", &self.tx_left_align())
+            .field("tx_24_fill_en", &self.tx_24_fill_en())
+            .field("tx_ws_idle_pol", &self.tx_ws_idle_pol())
+            .field("tx_bit_order", &self.tx_bit_order())
+            .field("tx_tdm_en", &self.tx_tdm_en())
+            .field("tx_pdm_en", &self.tx_pdm_en())
+            .field("tx_chan_mod", &self.tx_chan_mod())
+            .field("sig_loopback", &self.sig_loopback())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset transmitter"]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/tx_conf1.rs b/esp32s3/src/i2s0/tx_conf1.rs
index 736705832c..8d70da3870 100644
--- a/esp32s3/src/i2s0/tx_conf1.rs
+++ b/esp32s3/src/i2s0/tx_conf1.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CONF1")
-            .field(
-                "tx_tdm_ws_width",
-                &format_args!("{}", self.tx_tdm_ws_width().bits()),
-            )
-            .field(
-                "tx_bck_div_num",
-                &format_args!("{}", self.tx_bck_div_num().bits()),
-            )
-            .field(
-                "tx_bits_mod",
-                &format_args!("{}", self.tx_bits_mod().bits()),
-            )
-            .field(
-                "tx_half_sample_bits",
-                &format_args!("{}", self.tx_half_sample_bits().bits()),
-            )
-            .field(
-                "tx_tdm_chan_bits",
-                &format_args!("{}", self.tx_tdm_chan_bits().bits()),
-            )
-            .field(
-                "tx_msb_shift",
-                &format_args!("{}", self.tx_msb_shift().bit()),
-            )
-            .field(
-                "tx_bck_no_dly",
-                &format_args!("{}", self.tx_bck_no_dly().bit()),
-            )
+            .field("tx_tdm_ws_width", &self.tx_tdm_ws_width())
+            .field("tx_bck_div_num", &self.tx_bck_div_num())
+            .field("tx_bits_mod", &self.tx_bits_mod())
+            .field("tx_half_sample_bits", &self.tx_half_sample_bits())
+            .field("tx_tdm_chan_bits", &self.tx_tdm_chan_bits())
+            .field("tx_msb_shift", &self.tx_msb_shift())
+            .field("tx_bck_no_dly", &self.tx_bck_no_dly())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/tx_pcm2pdm_conf.rs b/esp32s3/src/i2s0/tx_pcm2pdm_conf.rs
index f361f43fa5..833a737465 100644
--- a/esp32s3/src/i2s0/tx_pcm2pdm_conf.rs
+++ b/esp32s3/src/i2s0/tx_pcm2pdm_conf.rs
@@ -116,63 +116,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_PCM2PDM_CONF")
-            .field(
-                "tx_pdm_hp_bypass",
-                &format_args!("{}", self.tx_pdm_hp_bypass().bit()),
-            )
-            .field(
-                "tx_pdm_sinc_osr2",
-                &format_args!("{}", self.tx_pdm_sinc_osr2().bits()),
-            )
-            .field(
-                "tx_pdm_prescale",
-                &format_args!("{}", self.tx_pdm_prescale().bits()),
-            )
-            .field(
-                "tx_pdm_hp_in_shift",
-                &format_args!("{}", self.tx_pdm_hp_in_shift().bits()),
-            )
-            .field(
-                "tx_pdm_lp_in_shift",
-                &format_args!("{}", self.tx_pdm_lp_in_shift().bits()),
-            )
-            .field(
-                "tx_pdm_sinc_in_shift",
-                &format_args!("{}", self.tx_pdm_sinc_in_shift().bits()),
-            )
+            .field("tx_pdm_hp_bypass", &self.tx_pdm_hp_bypass())
+            .field("tx_pdm_sinc_osr2", &self.tx_pdm_sinc_osr2())
+            .field("tx_pdm_prescale", &self.tx_pdm_prescale())
+            .field("tx_pdm_hp_in_shift", &self.tx_pdm_hp_in_shift())
+            .field("tx_pdm_lp_in_shift", &self.tx_pdm_lp_in_shift())
+            .field("tx_pdm_sinc_in_shift", &self.tx_pdm_sinc_in_shift())
             .field(
                 "tx_pdm_sigmadelta_in_shift",
-                &format_args!("{}", self.tx_pdm_sigmadelta_in_shift().bits()),
+                &self.tx_pdm_sigmadelta_in_shift(),
             )
             .field(
                 "tx_pdm_sigmadelta_dither2",
-                &format_args!("{}", self.tx_pdm_sigmadelta_dither2().bit()),
-            )
-            .field(
-                "tx_pdm_sigmadelta_dither",
-                &format_args!("{}", self.tx_pdm_sigmadelta_dither().bit()),
-            )
-            .field(
-                "tx_pdm_dac_2out_en",
-                &format_args!("{}", self.tx_pdm_dac_2out_en().bit()),
-            )
-            .field(
-                "tx_pdm_dac_mode_en",
-                &format_args!("{}", self.tx_pdm_dac_mode_en().bit()),
-            )
-            .field(
-                "pcm2pdm_conv_en",
-                &format_args!("{}", self.pcm2pdm_conv_en().bit()),
+                &self.tx_pdm_sigmadelta_dither2(),
             )
+            .field("tx_pdm_sigmadelta_dither", &self.tx_pdm_sigmadelta_dither())
+            .field("tx_pdm_dac_2out_en", &self.tx_pdm_dac_2out_en())
+            .field("tx_pdm_dac_mode_en", &self.tx_pdm_dac_mode_en())
+            .field("pcm2pdm_conv_en", &self.pcm2pdm_conv_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_PCM2PDM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - I2S TX PDM bypass hp filter or not. The option has been removed."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/tx_pcm2pdm_conf1.rs b/esp32s3/src/i2s0/tx_pcm2pdm_conf1.rs
index dfcd334df0..48c460dc25 100644
--- a/esp32s3/src/i2s0/tx_pcm2pdm_conf1.rs
+++ b/esp32s3/src/i2s0/tx_pcm2pdm_conf1.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_PCM2PDM_CONF1")
-            .field("tx_pdm_fp", &format_args!("{}", self.tx_pdm_fp().bits()))
-            .field("tx_pdm_fs", &format_args!("{}", self.tx_pdm_fs().bits()))
-            .field(
-                "tx_iir_hp_mult12_5",
-                &format_args!("{}", self.tx_iir_hp_mult12_5().bits()),
-            )
-            .field(
-                "tx_iir_hp_mult12_0",
-                &format_args!("{}", self.tx_iir_hp_mult12_0().bits()),
-            )
+            .field("tx_pdm_fp", &self.tx_pdm_fp())
+            .field("tx_pdm_fs", &self.tx_pdm_fs())
+            .field("tx_iir_hp_mult12_5", &self.tx_iir_hp_mult12_5())
+            .field("tx_iir_hp_mult12_0", &self.tx_iir_hp_mult12_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_PCM2PDM_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - I2S TX PDM Fp"]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/tx_tdm_ctrl.rs b/esp32s3/src/i2s0/tx_tdm_ctrl.rs
index a6511fa2f9..8b06e96c6c 100644
--- a/esp32s3/src/i2s0/tx_tdm_ctrl.rs
+++ b/esp32s3/src/i2s0/tx_tdm_ctrl.rs
@@ -170,87 +170,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_TDM_CTRL")
-            .field(
-                "tx_tdm_chan0_en",
-                &format_args!("{}", self.tx_tdm_chan0_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan1_en",
-                &format_args!("{}", self.tx_tdm_chan1_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan2_en",
-                &format_args!("{}", self.tx_tdm_chan2_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan3_en",
-                &format_args!("{}", self.tx_tdm_chan3_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan4_en",
-                &format_args!("{}", self.tx_tdm_chan4_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan5_en",
-                &format_args!("{}", self.tx_tdm_chan5_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan6_en",
-                &format_args!("{}", self.tx_tdm_chan6_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan7_en",
-                &format_args!("{}", self.tx_tdm_chan7_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan8_en",
-                &format_args!("{}", self.tx_tdm_chan8_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan9_en",
-                &format_args!("{}", self.tx_tdm_chan9_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan10_en",
-                &format_args!("{}", self.tx_tdm_chan10_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan11_en",
-                &format_args!("{}", self.tx_tdm_chan11_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan12_en",
-                &format_args!("{}", self.tx_tdm_chan12_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan13_en",
-                &format_args!("{}", self.tx_tdm_chan13_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan14_en",
-                &format_args!("{}", self.tx_tdm_chan14_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan15_en",
-                &format_args!("{}", self.tx_tdm_chan15_en().bit()),
-            )
-            .field(
-                "tx_tdm_tot_chan_num",
-                &format_args!("{}", self.tx_tdm_tot_chan_num().bits()),
-            )
-            .field(
-                "tx_tdm_skip_msk_en",
-                &format_args!("{}", self.tx_tdm_skip_msk_en().bit()),
-            )
+            .field("tx_tdm_chan0_en", &self.tx_tdm_chan0_en())
+            .field("tx_tdm_chan1_en", &self.tx_tdm_chan1_en())
+            .field("tx_tdm_chan2_en", &self.tx_tdm_chan2_en())
+            .field("tx_tdm_chan3_en", &self.tx_tdm_chan3_en())
+            .field("tx_tdm_chan4_en", &self.tx_tdm_chan4_en())
+            .field("tx_tdm_chan5_en", &self.tx_tdm_chan5_en())
+            .field("tx_tdm_chan6_en", &self.tx_tdm_chan6_en())
+            .field("tx_tdm_chan7_en", &self.tx_tdm_chan7_en())
+            .field("tx_tdm_chan8_en", &self.tx_tdm_chan8_en())
+            .field("tx_tdm_chan9_en", &self.tx_tdm_chan9_en())
+            .field("tx_tdm_chan10_en", &self.tx_tdm_chan10_en())
+            .field("tx_tdm_chan11_en", &self.tx_tdm_chan11_en())
+            .field("tx_tdm_chan12_en", &self.tx_tdm_chan12_en())
+            .field("tx_tdm_chan13_en", &self.tx_tdm_chan13_en())
+            .field("tx_tdm_chan14_en", &self.tx_tdm_chan14_en())
+            .field("tx_tdm_chan15_en", &self.tx_tdm_chan15_en())
+            .field("tx_tdm_tot_chan_num", &self.tx_tdm_tot_chan_num())
+            .field("tx_tdm_skip_msk_en", &self.tx_tdm_skip_msk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_TDM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s0/tx_timing.rs b/esp32s3/src/i2s0/tx_timing.rs
index 90d44db432..550930d1b6 100644
--- a/esp32s3/src/i2s0/tx_timing.rs
+++ b/esp32s3/src/i2s0/tx_timing.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_TIMING")
-            .field(
-                "tx_sd_out_dm",
-                &format_args!("{}", self.tx_sd_out_dm().bits()),
-            )
-            .field(
-                "tx_sd1_out_dm",
-                &format_args!("{}", self.tx_sd1_out_dm().bits()),
-            )
-            .field(
-                "tx_ws_out_dm",
-                &format_args!("{}", self.tx_ws_out_dm().bits()),
-            )
-            .field(
-                "tx_bck_out_dm",
-                &format_args!("{}", self.tx_bck_out_dm().bits()),
-            )
-            .field(
-                "tx_ws_in_dm",
-                &format_args!("{}", self.tx_ws_in_dm().bits()),
-            )
-            .field(
-                "tx_bck_in_dm",
-                &format_args!("{}", self.tx_bck_in_dm().bits()),
-            )
+            .field("tx_sd_out_dm", &self.tx_sd_out_dm())
+            .field("tx_sd1_out_dm", &self.tx_sd1_out_dm())
+            .field("tx_ws_out_dm", &self.tx_ws_out_dm())
+            .field("tx_bck_out_dm", &self.tx_bck_out_dm())
+            .field("tx_ws_in_dm", &self.tx_ws_in_dm())
+            .field("tx_bck_in_dm", &self.tx_bck_in_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/conf_sigle_data.rs b/esp32s3/src/i2s1/conf_sigle_data.rs
index f979345988..3c75f59255 100644
--- a/esp32s3/src/i2s1/conf_sigle_data.rs
+++ b/esp32s3/src/i2s1/conf_sigle_data.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF_SIGLE_DATA")
-            .field(
-                "single_data",
-                &format_args!("{}", self.single_data().bits()),
-            )
+            .field("single_data", &self.single_data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SIGLE_DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The configured constant channel data to be sent out."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/date.rs b/esp32s3/src/i2s1/date.rs
index 3364ff98f6..ee83431298 100644
--- a/esp32s3/src/i2s1/date.rs
+++ b/esp32s3/src/i2s1/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/i2s1/int_ena.rs b/esp32s3/src/i2s1/int_ena.rs
index ffbc92bacc..0a538b90e5 100644
--- a/esp32s3/src/i2s1/int_ena.rs
+++ b/esp32s3/src/i2s1/int_ena.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the i2s_rx_done_int interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/int_raw.rs b/esp32s3/src/i2s1/int_raw.rs
index 7ec2d42cfd..e69602c0be 100644
--- a/esp32s3/src/i2s1/int_raw.rs
+++ b/esp32s3/src/i2s1/int_raw.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt raw register, valid in level.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s3/src/i2s1/int_st.rs b/esp32s3/src/i2s1/int_st.rs
index 5eac7b9c9d..ddf72a352e 100644
--- a/esp32s3/src/i2s1/int_st.rs
+++ b/esp32s3/src/i2s1/int_st.rs
@@ -34,19 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rx_done", &format_args!("{}", self.rx_done().bit()))
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
+            .field("rx_done", &self.rx_done())
+            .field("tx_done", &self.tx_done())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S interrupt status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/i2s1/lc_hung_conf.rs b/esp32s3/src/i2s1/lc_hung_conf.rs
index 060b1cdb60..71f0c84fa7 100644
--- a/esp32s3/src/i2s1/lc_hung_conf.rs
+++ b/esp32s3/src/i2s1/lc_hung_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_HUNG_CONF")
-            .field(
-                "lc_fifo_timeout",
-                &format_args!("{}", self.lc_fifo_timeout().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_shift",
-                &format_args!("{}", self.lc_fifo_timeout_shift().bits()),
-            )
-            .field(
-                "lc_fifo_timeout_ena",
-                &format_args!("{}", self.lc_fifo_timeout_ena().bit()),
-            )
+            .field("lc_fifo_timeout", &self.lc_fifo_timeout())
+            .field("lc_fifo_timeout_shift", &self.lc_fifo_timeout_shift())
+            .field("lc_fifo_timeout_ena", &self.lc_fifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/rx_clkm_conf.rs b/esp32s3/src/i2s1/rx_clkm_conf.rs
index 79ff9b2470..5bbb7a360a 100644
--- a/esp32s3/src/i2s1/rx_clkm_conf.rs
+++ b/esp32s3/src/i2s1/rx_clkm_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CLKM_CONF")
-            .field(
-                "rx_clkm_div_num",
-                &format_args!("{}", self.rx_clkm_div_num().bits()),
-            )
-            .field(
-                "rx_clk_active",
-                &format_args!("{}", self.rx_clk_active().bit()),
-            )
-            .field("rx_clk_sel", &format_args!("{}", self.rx_clk_sel().bits()))
-            .field("mclk_sel", &format_args!("{}", self.mclk_sel().bit()))
+            .field("rx_clkm_div_num", &self.rx_clkm_div_num())
+            .field("rx_clk_active", &self.rx_clk_active())
+            .field("rx_clk_sel", &self.rx_clk_sel())
+            .field("mclk_sel", &self.mclk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral I2S clock divider value"]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/rx_clkm_div_conf.rs b/esp32s3/src/i2s1/rx_clkm_div_conf.rs
index 9dc32721ed..d4f0ee53bc 100644
--- a/esp32s3/src/i2s1/rx_clkm_div_conf.rs
+++ b/esp32s3/src/i2s1/rx_clkm_div_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CLKM_DIV_CONF")
-            .field(
-                "rx_clkm_div_z",
-                &format_args!("{}", self.rx_clkm_div_z().bits()),
-            )
-            .field(
-                "rx_clkm_div_y",
-                &format_args!("{}", self.rx_clkm_div_y().bits()),
-            )
-            .field(
-                "rx_clkm_div_x",
-                &format_args!("{}", self.rx_clkm_div_x().bits()),
-            )
-            .field(
-                "rx_clkm_div_yn1",
-                &format_args!("{}", self.rx_clkm_div_yn1().bit()),
-            )
+            .field("rx_clkm_div_z", &self.rx_clkm_div_z())
+            .field("rx_clkm_div_y", &self.rx_clkm_div_y())
+            .field("rx_clkm_div_x", &self.rx_clkm_div_x())
+            .field("rx_clkm_div_yn1", &self.rx_clkm_div_yn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CLKM_DIV_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/rx_conf.rs b/esp32s3/src/i2s1/rx_conf.rs
index 87a73e205b..bc22e600af 100644
--- a/esp32s3/src/i2s1/rx_conf.rs
+++ b/esp32s3/src/i2s1/rx_conf.rs
@@ -147,60 +147,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CONF")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field(
-                "rx_slave_mod",
-                &format_args!("{}", self.rx_slave_mod().bit()),
-            )
-            .field("rx_mono", &format_args!("{}", self.rx_mono().bit()))
-            .field(
-                "rx_big_endian",
-                &format_args!("{}", self.rx_big_endian().bit()),
-            )
-            .field("rx_update", &format_args!("{}", self.rx_update().bit()))
-            .field(
-                "rx_mono_fst_vld",
-                &format_args!("{}", self.rx_mono_fst_vld().bit()),
-            )
-            .field(
-                "rx_pcm_conf",
-                &format_args!("{}", self.rx_pcm_conf().bits()),
-            )
-            .field(
-                "rx_pcm_bypass",
-                &format_args!("{}", self.rx_pcm_bypass().bit()),
-            )
-            .field(
-                "rx_stop_mode",
-                &format_args!("{}", self.rx_stop_mode().bits()),
-            )
-            .field(
-                "rx_left_align",
-                &format_args!("{}", self.rx_left_align().bit()),
-            )
-            .field(
-                "rx_24_fill_en",
-                &format_args!("{}", self.rx_24_fill_en().bit()),
-            )
-            .field(
-                "rx_ws_idle_pol",
-                &format_args!("{}", self.rx_ws_idle_pol().bit()),
-            )
-            .field(
-                "rx_bit_order",
-                &format_args!("{}", self.rx_bit_order().bit()),
-            )
-            .field("rx_tdm_en", &format_args!("{}", self.rx_tdm_en().bit()))
-            .field("rx_pdm_en", &format_args!("{}", self.rx_pdm_en().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("rx_slave_mod", &self.rx_slave_mod())
+            .field("rx_mono", &self.rx_mono())
+            .field("rx_big_endian", &self.rx_big_endian())
+            .field("rx_update", &self.rx_update())
+            .field("rx_mono_fst_vld", &self.rx_mono_fst_vld())
+            .field("rx_pcm_conf", &self.rx_pcm_conf())
+            .field("rx_pcm_bypass", &self.rx_pcm_bypass())
+            .field("rx_stop_mode", &self.rx_stop_mode())
+            .field("rx_left_align", &self.rx_left_align())
+            .field("rx_24_fill_en", &self.rx_24_fill_en())
+            .field("rx_ws_idle_pol", &self.rx_ws_idle_pol())
+            .field("rx_bit_order", &self.rx_bit_order())
+            .field("rx_tdm_en", &self.rx_tdm_en())
+            .field("rx_pdm_en", &self.rx_pdm_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset receiver"]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/rx_conf1.rs b/esp32s3/src/i2s1/rx_conf1.rs
index 24c13494fb..31fa7a1f88 100644
--- a/esp32s3/src/i2s1/rx_conf1.rs
+++ b/esp32s3/src/i2s1/rx_conf1.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_CONF1")
-            .field(
-                "rx_tdm_ws_width",
-                &format_args!("{}", self.rx_tdm_ws_width().bits()),
-            )
-            .field(
-                "rx_bck_div_num",
-                &format_args!("{}", self.rx_bck_div_num().bits()),
-            )
-            .field(
-                "rx_bits_mod",
-                &format_args!("{}", self.rx_bits_mod().bits()),
-            )
-            .field(
-                "rx_half_sample_bits",
-                &format_args!("{}", self.rx_half_sample_bits().bits()),
-            )
-            .field(
-                "rx_tdm_chan_bits",
-                &format_args!("{}", self.rx_tdm_chan_bits().bits()),
-            )
-            .field(
-                "rx_msb_shift",
-                &format_args!("{}", self.rx_msb_shift().bit()),
-            )
+            .field("rx_tdm_ws_width", &self.rx_tdm_ws_width())
+            .field("rx_bck_div_num", &self.rx_bck_div_num())
+            .field("rx_bits_mod", &self.rx_bits_mod())
+            .field("rx_half_sample_bits", &self.rx_half_sample_bits())
+            .field("rx_tdm_chan_bits", &self.rx_tdm_chan_bits())
+            .field("rx_msb_shift", &self.rx_msb_shift())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/rx_tdm_ctrl.rs b/esp32s3/src/i2s1/rx_tdm_ctrl.rs
index fe01f97aeb..0d18f522f2 100644
--- a/esp32s3/src/i2s1/rx_tdm_ctrl.rs
+++ b/esp32s3/src/i2s1/rx_tdm_ctrl.rs
@@ -161,83 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_TDM_CTRL")
-            .field(
-                "rx_tdm_pdm_chan0_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan0_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan1_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan1_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan2_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan2_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan3_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan3_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan4_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan4_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan5_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan5_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan6_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan6_en().bit()),
-            )
-            .field(
-                "rx_tdm_pdm_chan7_en",
-                &format_args!("{}", self.rx_tdm_pdm_chan7_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan8_en",
-                &format_args!("{}", self.rx_tdm_chan8_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan9_en",
-                &format_args!("{}", self.rx_tdm_chan9_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan10_en",
-                &format_args!("{}", self.rx_tdm_chan10_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan11_en",
-                &format_args!("{}", self.rx_tdm_chan11_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan12_en",
-                &format_args!("{}", self.rx_tdm_chan12_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan13_en",
-                &format_args!("{}", self.rx_tdm_chan13_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan14_en",
-                &format_args!("{}", self.rx_tdm_chan14_en().bit()),
-            )
-            .field(
-                "rx_tdm_chan15_en",
-                &format_args!("{}", self.rx_tdm_chan15_en().bit()),
-            )
-            .field(
-                "rx_tdm_tot_chan_num",
-                &format_args!("{}", self.rx_tdm_tot_chan_num().bits()),
-            )
+            .field("rx_tdm_pdm_chan0_en", &self.rx_tdm_pdm_chan0_en())
+            .field("rx_tdm_pdm_chan1_en", &self.rx_tdm_pdm_chan1_en())
+            .field("rx_tdm_pdm_chan2_en", &self.rx_tdm_pdm_chan2_en())
+            .field("rx_tdm_pdm_chan3_en", &self.rx_tdm_pdm_chan3_en())
+            .field("rx_tdm_pdm_chan4_en", &self.rx_tdm_pdm_chan4_en())
+            .field("rx_tdm_pdm_chan5_en", &self.rx_tdm_pdm_chan5_en())
+            .field("rx_tdm_pdm_chan6_en", &self.rx_tdm_pdm_chan6_en())
+            .field("rx_tdm_pdm_chan7_en", &self.rx_tdm_pdm_chan7_en())
+            .field("rx_tdm_chan8_en", &self.rx_tdm_chan8_en())
+            .field("rx_tdm_chan9_en", &self.rx_tdm_chan9_en())
+            .field("rx_tdm_chan10_en", &self.rx_tdm_chan10_en())
+            .field("rx_tdm_chan11_en", &self.rx_tdm_chan11_en())
+            .field("rx_tdm_chan12_en", &self.rx_tdm_chan12_en())
+            .field("rx_tdm_chan13_en", &self.rx_tdm_chan13_en())
+            .field("rx_tdm_chan14_en", &self.rx_tdm_chan14_en())
+            .field("rx_tdm_chan15_en", &self.rx_tdm_chan15_en())
+            .field("rx_tdm_tot_chan_num", &self.rx_tdm_tot_chan_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_TDM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/rx_timing.rs b/esp32s3/src/i2s1/rx_timing.rs
index 66daf81e08..fe227b5840 100644
--- a/esp32s3/src/i2s1/rx_timing.rs
+++ b/esp32s3/src/i2s1/rx_timing.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_TIMING")
-            .field(
-                "rx_sd_in_dm",
-                &format_args!("{}", self.rx_sd_in_dm().bits()),
-            )
-            .field(
-                "rx_ws_out_dm",
-                &format_args!("{}", self.rx_ws_out_dm().bits()),
-            )
-            .field(
-                "rx_bck_out_dm",
-                &format_args!("{}", self.rx_bck_out_dm().bits()),
-            )
-            .field(
-                "rx_ws_in_dm",
-                &format_args!("{}", self.rx_ws_in_dm().bits()),
-            )
-            .field(
-                "rx_bck_in_dm",
-                &format_args!("{}", self.rx_bck_in_dm().bits()),
-            )
+            .field("rx_sd_in_dm", &self.rx_sd_in_dm())
+            .field("rx_ws_out_dm", &self.rx_ws_out_dm())
+            .field("rx_bck_out_dm", &self.rx_bck_out_dm())
+            .field("rx_ws_in_dm", &self.rx_ws_in_dm())
+            .field("rx_bck_in_dm", &self.rx_bck_in_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/rxeof_num.rs b/esp32s3/src/i2s1/rxeof_num.rs
index 06f6d22ff0..b9674d5891 100644
--- a/esp32s3/src/i2s1/rxeof_num.rs
+++ b/esp32s3/src/i2s1/rxeof_num.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXEOF_NUM")
-            .field("rx_eof_num", &format_args!("{}", self.rx_eof_num().bits()))
+            .field("rx_eof_num", &self.rx_eof_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXEOF_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The receive data bit length is (I2S_RX_BITS_MOD\\[4:0\\] + 1) * (REG_RX_EOF_NUM\\[11:0\\] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/state.rs b/esp32s3/src/i2s1/state.rs
index 7988d4067c..d16247a40d 100644
--- a/esp32s3/src/i2s1/state.rs
+++ b/esp32s3/src/i2s1/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("tx_idle", &format_args!("{}", self.tx_idle().bit()))
+            .field("tx_idle", &self.tx_idle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "I2S TX status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/esp32s3/src/i2s1/tx_clkm_conf.rs b/esp32s3/src/i2s1/tx_clkm_conf.rs
index ef82d04116..2584244722 100644
--- a/esp32s3/src/i2s1/tx_clkm_conf.rs
+++ b/esp32s3/src/i2s1/tx_clkm_conf.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CLKM_CONF")
-            .field(
-                "tx_clkm_div_num",
-                &format_args!("{}", self.tx_clkm_div_num().bits()),
-            )
-            .field(
-                "tx_clk_active",
-                &format_args!("{}", self.tx_clk_active().bit()),
-            )
-            .field("tx_clk_sel", &format_args!("{}", self.tx_clk_sel().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("tx_clkm_div_num", &self.tx_clkm_div_num())
+            .field("tx_clk_active", &self.tx_clk_active())
+            .field("tx_clk_sel", &self.tx_clk_sel())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CLKM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b &lt;= a/2, z * \\[x * n-div + (n+1)-div\\] + y * n-div. For b > a/2, z * \\[n-div + x * (n+1)-div\\] + y * (n+1)-div."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/tx_clkm_div_conf.rs b/esp32s3/src/i2s1/tx_clkm_div_conf.rs
index eb02e39a99..8421d21999 100644
--- a/esp32s3/src/i2s1/tx_clkm_div_conf.rs
+++ b/esp32s3/src/i2s1/tx_clkm_div_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CLKM_DIV_CONF")
-            .field(
-                "tx_clkm_div_z",
-                &format_args!("{}", self.tx_clkm_div_z().bits()),
-            )
-            .field(
-                "tx_clkm_div_y",
-                &format_args!("{}", self.tx_clkm_div_y().bits()),
-            )
-            .field(
-                "tx_clkm_div_x",
-                &format_args!("{}", self.tx_clkm_div_x().bits()),
-            )
-            .field(
-                "tx_clkm_div_yn1",
-                &format_args!("{}", self.tx_clkm_div_yn1().bit()),
-            )
+            .field("tx_clkm_div_z", &self.tx_clkm_div_z())
+            .field("tx_clkm_div_y", &self.tx_clkm_div_y())
+            .field("tx_clkm_div_x", &self.tx_clkm_div_x())
+            .field("tx_clkm_div_yn1", &self.tx_clkm_div_yn1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CLKM_DIV_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - For b &lt;= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/tx_conf.rs b/esp32s3/src/i2s1/tx_conf.rs
index b10d6ccc62..83a890333d 100644
--- a/esp32s3/src/i2s1/tx_conf.rs
+++ b/esp32s3/src/i2s1/tx_conf.rs
@@ -174,69 +174,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CONF")
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field(
-                "tx_slave_mod",
-                &format_args!("{}", self.tx_slave_mod().bit()),
-            )
-            .field("tx_mono", &format_args!("{}", self.tx_mono().bit()))
-            .field(
-                "tx_chan_equal",
-                &format_args!("{}", self.tx_chan_equal().bit()),
-            )
-            .field(
-                "tx_big_endian",
-                &format_args!("{}", self.tx_big_endian().bit()),
-            )
-            .field("tx_update", &format_args!("{}", self.tx_update().bit()))
-            .field(
-                "tx_mono_fst_vld",
-                &format_args!("{}", self.tx_mono_fst_vld().bit()),
-            )
-            .field(
-                "tx_pcm_conf",
-                &format_args!("{}", self.tx_pcm_conf().bits()),
-            )
-            .field(
-                "tx_pcm_bypass",
-                &format_args!("{}", self.tx_pcm_bypass().bit()),
-            )
-            .field("tx_stop_en", &format_args!("{}", self.tx_stop_en().bit()))
-            .field(
-                "tx_left_align",
-                &format_args!("{}", self.tx_left_align().bit()),
-            )
-            .field(
-                "tx_24_fill_en",
-                &format_args!("{}", self.tx_24_fill_en().bit()),
-            )
-            .field(
-                "tx_ws_idle_pol",
-                &format_args!("{}", self.tx_ws_idle_pol().bit()),
-            )
-            .field(
-                "tx_bit_order",
-                &format_args!("{}", self.tx_bit_order().bit()),
-            )
-            .field("tx_tdm_en", &format_args!("{}", self.tx_tdm_en().bit()))
-            .field("tx_pdm_en", &format_args!("{}", self.tx_pdm_en().bit()))
-            .field(
-                "tx_chan_mod",
-                &format_args!("{}", self.tx_chan_mod().bits()),
-            )
-            .field(
-                "sig_loopback",
-                &format_args!("{}", self.sig_loopback().bit()),
-            )
+            .field("tx_start", &self.tx_start())
+            .field("tx_slave_mod", &self.tx_slave_mod())
+            .field("tx_mono", &self.tx_mono())
+            .field("tx_chan_equal", &self.tx_chan_equal())
+            .field("tx_big_endian", &self.tx_big_endian())
+            .field("tx_update", &self.tx_update())
+            .field("tx_mono_fst_vld", &self.tx_mono_fst_vld())
+            .field("tx_pcm_conf", &self.tx_pcm_conf())
+            .field("tx_pcm_bypass", &self.tx_pcm_bypass())
+            .field("tx_stop_en", &self.tx_stop_en())
+            .field("tx_left_align", &self.tx_left_align())
+            .field("tx_24_fill_en", &self.tx_24_fill_en())
+            .field("tx_ws_idle_pol", &self.tx_ws_idle_pol())
+            .field("tx_bit_order", &self.tx_bit_order())
+            .field("tx_tdm_en", &self.tx_tdm_en())
+            .field("tx_pdm_en", &self.tx_pdm_en())
+            .field("tx_chan_mod", &self.tx_chan_mod())
+            .field("sig_loopback", &self.sig_loopback())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to reset transmitter"]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/tx_conf1.rs b/esp32s3/src/i2s1/tx_conf1.rs
index 736705832c..8d70da3870 100644
--- a/esp32s3/src/i2s1/tx_conf1.rs
+++ b/esp32s3/src/i2s1/tx_conf1.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CONF1")
-            .field(
-                "tx_tdm_ws_width",
-                &format_args!("{}", self.tx_tdm_ws_width().bits()),
-            )
-            .field(
-                "tx_bck_div_num",
-                &format_args!("{}", self.tx_bck_div_num().bits()),
-            )
-            .field(
-                "tx_bits_mod",
-                &format_args!("{}", self.tx_bits_mod().bits()),
-            )
-            .field(
-                "tx_half_sample_bits",
-                &format_args!("{}", self.tx_half_sample_bits().bits()),
-            )
-            .field(
-                "tx_tdm_chan_bits",
-                &format_args!("{}", self.tx_tdm_chan_bits().bits()),
-            )
-            .field(
-                "tx_msb_shift",
-                &format_args!("{}", self.tx_msb_shift().bit()),
-            )
-            .field(
-                "tx_bck_no_dly",
-                &format_args!("{}", self.tx_bck_no_dly().bit()),
-            )
+            .field("tx_tdm_ws_width", &self.tx_tdm_ws_width())
+            .field("tx_bck_div_num", &self.tx_bck_div_num())
+            .field("tx_bits_mod", &self.tx_bits_mod())
+            .field("tx_half_sample_bits", &self.tx_half_sample_bits())
+            .field("tx_tdm_chan_bits", &self.tx_tdm_chan_bits())
+            .field("tx_msb_shift", &self.tx_msb_shift())
+            .field("tx_bck_no_dly", &self.tx_bck_no_dly())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH\\[6:0\\] +1) * T_bck"]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/tx_tdm_ctrl.rs b/esp32s3/src/i2s1/tx_tdm_ctrl.rs
index a6511fa2f9..8b06e96c6c 100644
--- a/esp32s3/src/i2s1/tx_tdm_ctrl.rs
+++ b/esp32s3/src/i2s1/tx_tdm_ctrl.rs
@@ -170,87 +170,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_TDM_CTRL")
-            .field(
-                "tx_tdm_chan0_en",
-                &format_args!("{}", self.tx_tdm_chan0_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan1_en",
-                &format_args!("{}", self.tx_tdm_chan1_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan2_en",
-                &format_args!("{}", self.tx_tdm_chan2_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan3_en",
-                &format_args!("{}", self.tx_tdm_chan3_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan4_en",
-                &format_args!("{}", self.tx_tdm_chan4_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan5_en",
-                &format_args!("{}", self.tx_tdm_chan5_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan6_en",
-                &format_args!("{}", self.tx_tdm_chan6_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan7_en",
-                &format_args!("{}", self.tx_tdm_chan7_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan8_en",
-                &format_args!("{}", self.tx_tdm_chan8_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan9_en",
-                &format_args!("{}", self.tx_tdm_chan9_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan10_en",
-                &format_args!("{}", self.tx_tdm_chan10_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan11_en",
-                &format_args!("{}", self.tx_tdm_chan11_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan12_en",
-                &format_args!("{}", self.tx_tdm_chan12_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan13_en",
-                &format_args!("{}", self.tx_tdm_chan13_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan14_en",
-                &format_args!("{}", self.tx_tdm_chan14_en().bit()),
-            )
-            .field(
-                "tx_tdm_chan15_en",
-                &format_args!("{}", self.tx_tdm_chan15_en().bit()),
-            )
-            .field(
-                "tx_tdm_tot_chan_num",
-                &format_args!("{}", self.tx_tdm_tot_chan_num().bits()),
-            )
-            .field(
-                "tx_tdm_skip_msk_en",
-                &format_args!("{}", self.tx_tdm_skip_msk_en().bit()),
-            )
+            .field("tx_tdm_chan0_en", &self.tx_tdm_chan0_en())
+            .field("tx_tdm_chan1_en", &self.tx_tdm_chan1_en())
+            .field("tx_tdm_chan2_en", &self.tx_tdm_chan2_en())
+            .field("tx_tdm_chan3_en", &self.tx_tdm_chan3_en())
+            .field("tx_tdm_chan4_en", &self.tx_tdm_chan4_en())
+            .field("tx_tdm_chan5_en", &self.tx_tdm_chan5_en())
+            .field("tx_tdm_chan6_en", &self.tx_tdm_chan6_en())
+            .field("tx_tdm_chan7_en", &self.tx_tdm_chan7_en())
+            .field("tx_tdm_chan8_en", &self.tx_tdm_chan8_en())
+            .field("tx_tdm_chan9_en", &self.tx_tdm_chan9_en())
+            .field("tx_tdm_chan10_en", &self.tx_tdm_chan10_en())
+            .field("tx_tdm_chan11_en", &self.tx_tdm_chan11_en())
+            .field("tx_tdm_chan12_en", &self.tx_tdm_chan12_en())
+            .field("tx_tdm_chan13_en", &self.tx_tdm_chan13_en())
+            .field("tx_tdm_chan14_en", &self.tx_tdm_chan14_en())
+            .field("tx_tdm_chan15_en", &self.tx_tdm_chan15_en())
+            .field("tx_tdm_tot_chan_num", &self.tx_tdm_tot_chan_num())
+            .field("tx_tdm_skip_msk_en", &self.tx_tdm_skip_msk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_TDM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel."]
     #[inline(always)]
diff --git a/esp32s3/src/i2s1/tx_timing.rs b/esp32s3/src/i2s1/tx_timing.rs
index 90d44db432..550930d1b6 100644
--- a/esp32s3/src/i2s1/tx_timing.rs
+++ b/esp32s3/src/i2s1/tx_timing.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_TIMING")
-            .field(
-                "tx_sd_out_dm",
-                &format_args!("{}", self.tx_sd_out_dm().bits()),
-            )
-            .field(
-                "tx_sd1_out_dm",
-                &format_args!("{}", self.tx_sd1_out_dm().bits()),
-            )
-            .field(
-                "tx_ws_out_dm",
-                &format_args!("{}", self.tx_ws_out_dm().bits()),
-            )
-            .field(
-                "tx_bck_out_dm",
-                &format_args!("{}", self.tx_bck_out_dm().bits()),
-            )
-            .field(
-                "tx_ws_in_dm",
-                &format_args!("{}", self.tx_ws_in_dm().bits()),
-            )
-            .field(
-                "tx_bck_in_dm",
-                &format_args!("{}", self.tx_bck_in_dm().bits()),
-            )
+            .field("tx_sd_out_dm", &self.tx_sd_out_dm())
+            .field("tx_sd1_out_dm", &self.tx_sd1_out_dm())
+            .field("tx_ws_out_dm", &self.tx_ws_out_dm())
+            .field("tx_bck_out_dm", &self.tx_bck_out_dm())
+            .field("tx_ws_in_dm", &self.tx_ws_in_dm())
+            .field("tx_bck_in_dm", &self.tx_bck_in_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_TIMING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used."]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/aes_int_map.rs b/esp32s3/src/interrupt_core0/aes_int_map.rs
index e193da8583..7ec248866b 100644
--- a/esp32s3/src/interrupt_core0/aes_int_map.rs
+++ b/esp32s3/src/interrupt_core0/aes_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AES_INT_MAP")
-            .field(
-                "aes_int_map",
-                &format_args!("{}", self.aes_int_map().bits()),
-            )
+            .field("aes_int_map", &self.aes_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AES_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map aes interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/apb_adc_int_map.rs b/esp32s3/src/interrupt_core0/apb_adc_int_map.rs
index b85f513312..079e985250 100644
--- a/esp32s3/src/interrupt_core0/apb_adc_int_map.rs
+++ b/esp32s3/src/interrupt_core0/apb_adc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_ADC_INT_MAP")
-            .field(
-                "apb_adc_int_map",
-                &format_args!("{}", self.apb_adc_int_map().bits()),
-            )
+            .field("apb_adc_int_map", &self.apb_adc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_ADC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map apb_adc interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/assist_debug_intr_map.rs b/esp32s3/src/interrupt_core0/assist_debug_intr_map.rs
index ffd6efa0d6..e94632f95a 100644
--- a/esp32s3/src/interrupt_core0/assist_debug_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/assist_debug_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ASSIST_DEBUG_INTR_MAP")
-            .field(
-                "assist_debug_intr_map",
-                &format_args!("{}", self.assist_debug_intr_map().bits()),
-            )
+            .field("assist_debug_intr_map", &self.assist_debug_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ASSIST_DEBUG_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map assist_debug interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/backup_pms_violate_intr_map.rs b/esp32s3/src/interrupt_core0/backup_pms_violate_intr_map.rs
index 31c76ac79e..583b27b5ec 100644
--- a/esp32s3/src/interrupt_core0/backup_pms_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/backup_pms_violate_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_PMS_VIOLATE_INTR_MAP")
             .field(
                 "backup_pms_violate_intr_map",
-                &format_args!("{}", self.backup_pms_violate_intr_map().bits()),
+                &self.backup_pms_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_PMS_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map backup_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/bb_int_map.rs b/esp32s3/src/interrupt_core0/bb_int_map.rs
index 6265276237..b9579810aa 100644
--- a/esp32s3/src/interrupt_core0/bb_int_map.rs
+++ b/esp32s3/src/interrupt_core0/bb_int_map.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BB_INT_MAP")
-            .field("bb_int_map", &format_args!("{}", self.bb_int_map().bits()))
+            .field("bb_int_map", &self.bb_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BB_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map bb interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/bt_bb_int_map.rs b/esp32s3/src/interrupt_core0/bt_bb_int_map.rs
index 28eed3d513..d897720e7b 100644
--- a/esp32s3/src/interrupt_core0/bt_bb_int_map.rs
+++ b/esp32s3/src/interrupt_core0/bt_bb_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_BB_INT_MAP")
-            .field(
-                "bt_bb_int_map",
-                &format_args!("{}", self.bt_bb_int_map().bits()),
-            )
+            .field("bt_bb_int_map", &self.bt_bb_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_BB_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map bt_bb interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/bt_bb_nmi_map.rs b/esp32s3/src/interrupt_core0/bt_bb_nmi_map.rs
index 57725259c0..0550a9181a 100644
--- a/esp32s3/src/interrupt_core0/bt_bb_nmi_map.rs
+++ b/esp32s3/src/interrupt_core0/bt_bb_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_BB_NMI_MAP")
-            .field(
-                "bt_bb_nmi_map",
-                &format_args!("{}", self.bt_bb_nmi_map().bits()),
-            )
+            .field("bt_bb_nmi_map", &self.bt_bb_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_BB_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map bb_bt_nmi interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/bt_mac_int_map.rs b/esp32s3/src/interrupt_core0/bt_mac_int_map.rs
index c40fcca79d..4fb65dfaf2 100644
--- a/esp32s3/src/interrupt_core0/bt_mac_int_map.rs
+++ b/esp32s3/src/interrupt_core0/bt_mac_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_MAC_INT_MAP")
-            .field(
-                "bt_mac_int_map",
-                &format_args!("{}", self.bt_mac_int_map().bits()),
-            )
+            .field("bt_mac_int_map", &self.bt_mac_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_MAC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map bb_mac interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/cache_core0_acs_int_map.rs b/esp32s3/src/interrupt_core0/cache_core0_acs_int_map.rs
index 451d6042b6..767d492fec 100644
--- a/esp32s3/src/interrupt_core0/cache_core0_acs_int_map.rs
+++ b/esp32s3/src/interrupt_core0/cache_core0_acs_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_CORE0_ACS_INT_MAP")
-            .field(
-                "cache_core0_acs_int_map",
-                &format_args!("{}", self.cache_core0_acs_int_map().bits()),
-            )
+            .field("cache_core0_acs_int_map", &self.cache_core0_acs_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CORE0_ACS_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map cache_core0_acs interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/cache_core1_acs_int_map.rs b/esp32s3/src/interrupt_core0/cache_core1_acs_int_map.rs
index 790586de98..8a384cc505 100644
--- a/esp32s3/src/interrupt_core0/cache_core1_acs_int_map.rs
+++ b/esp32s3/src/interrupt_core0/cache_core1_acs_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_CORE1_ACS_INT_MAP")
-            .field(
-                "cache_core1_acs_int_map",
-                &format_args!("{}", self.cache_core1_acs_int_map().bits()),
-            )
+            .field("cache_core1_acs_int_map", &self.cache_core1_acs_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CORE1_ACS_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map cache_core1_acs interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/cache_ia_int_map.rs b/esp32s3/src/interrupt_core0/cache_ia_int_map.rs
index 378cf89ca5..aae9d9089c 100644
--- a/esp32s3/src/interrupt_core0/cache_ia_int_map.rs
+++ b/esp32s3/src/interrupt_core0/cache_ia_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_IA_INT_MAP")
-            .field(
-                "cache_ia_int_map",
-                &format_args!("{}", self.cache_ia_int_map().bits()),
-            )
+            .field("cache_ia_int_map", &self.cache_ia_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_IA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map cache_ia interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/can_int_map.rs b/esp32s3/src/interrupt_core0/can_int_map.rs
index e2472e323a..c84dda5b77 100644
--- a/esp32s3/src/interrupt_core0/can_int_map.rs
+++ b/esp32s3/src/interrupt_core0/can_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAN_INT_MAP")
-            .field(
-                "can_int_map",
-                &format_args!("{}", self.can_int_map().bits()),
-            )
+            .field("can_int_map", &self.can_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAN_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map can interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/clock_gate.rs b/esp32s3/src/interrupt_core0/clock_gate.rs
index 700ba1e81e..ca1b57a8cc 100644
--- a/esp32s3/src/interrupt_core0/clock_gate.rs
+++ b/esp32s3/src/interrupt_core0/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("reg_clk_en", &format_args!("{}", self.reg_clk_en().bit()))
+            .field("reg_clk_en", &self.reg_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this register uesd to control clock-gating interupt martrix"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/core_0_dram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core0/core_0_dram0_pms_monitor_violate_intr_map.rs
index f3e9bbfa36..9220f40fd0 100644
--- a/esp32s3/src/interrupt_core0/core_0_dram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_0_dram0_pms_monitor_violate_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "core_0_dram0_pms_monitor_violate_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_0_dram0_pms_monitor_violate_intr_map().bits()
-                ),
+                &self.core_0_dram0_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_DRam0_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/core_0_iram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core0/core_0_iram0_pms_monitor_violate_intr_map.rs
index c675a1a7e9..ad047d058b 100644
--- a/esp32s3/src/interrupt_core0/core_0_iram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_0_iram0_pms_monitor_violate_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "core_0_iram0_pms_monitor_violate_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_0_iram0_pms_monitor_violate_intr_map().bits()
-                ),
+                &self.core_0_iram0_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_IRam0_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_intr_map.rs
index 0dd6113274..c1cf4e4ae0 100644
--- a/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_intr_map.rs
@@ -21,17 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "core_0_pif_pms_monitor_violate_intr_map",
-                &format_args!("{}", self.core_0_pif_pms_monitor_violate_intr_map().bits()),
+                &self.core_0_pif_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_PIF_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs b/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs
index bfdccc85f4..154c88fe9b 100644
--- a/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_0_pif_pms_monitor_violate_size_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP")
             .field(
                 "core_0_pif_pms_monitor_violate_size_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_violate_size_intr_map().bits()
-                ),
+                &self.core_0_pif_pms_monitor_violate_size_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_PIF_pms_monitor_violatile_size interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/core_1_dram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core0/core_1_dram0_pms_monitor_violate_intr_map.rs
index 9930053479..ef8323512e 100644
--- a/esp32s3/src/interrupt_core0/core_1_dram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_1_dram0_pms_monitor_violate_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "core_1_dram0_pms_monitor_violate_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_1_dram0_pms_monitor_violate_intr_map().bits()
-                ),
+                &self.core_1_dram0_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_DRam0_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/core_1_iram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core0/core_1_iram0_pms_monitor_violate_intr_map.rs
index f503a34170..a0d29baa93 100644
--- a/esp32s3/src/interrupt_core0/core_1_iram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_1_iram0_pms_monitor_violate_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "core_1_iram0_pms_monitor_violate_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_1_iram0_pms_monitor_violate_intr_map().bits()
-                ),
+                &self.core_1_iram0_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_IRam0_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_intr_map.rs
index 536a509899..3a79246ac1 100644
--- a/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_intr_map.rs
@@ -21,17 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "core_1_pif_pms_monitor_violate_intr_map",
-                &format_args!("{}", self.core_1_pif_pms_monitor_violate_intr_map().bits()),
+                &self.core_1_pif_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_PIF_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_size_intr_map.rs b/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_size_intr_map.rs
index 5ec06b23ff..c327741dc0 100644
--- a/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_size_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/core_1_pif_pms_monitor_violate_size_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP")
             .field(
                 "core_1_pif_pms_monitor_violate_size_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_monitor_violate_size_intr_map().bits()
-                ),
+                &self.core_1_pif_pms_monitor_violate_size_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_PIF_pms_monitor_violatile_size interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
index b6953978b3..3e6ac59218 100644
--- a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
+++ b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_0_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_0_MAP")
-            .field(
-                "cpu_intr_from_cpu_0_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_0_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_0_map", &self.cpu_intr_from_cpu_0_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_0_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
index fd4e0070f3..44525f9404 100644
--- a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
+++ b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_1_MAP")
-            .field(
-                "cpu_intr_from_cpu_1_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_1_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_1_map", &self.cpu_intr_from_cpu_1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
index e84b4aff89..30c3f4e937 100644
--- a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
+++ b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_2_MAP")
-            .field(
-                "cpu_intr_from_cpu_2_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_2_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_2_map", &self.cpu_intr_from_cpu_2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
index c38a5c9846..78f6e723ab 100644
--- a/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
+++ b/esp32s3/src/interrupt_core0/cpu_intr_from_cpu_3_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_3_MAP")
-            .field(
-                "cpu_intr_from_cpu_3_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_3_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_3_map", &self.cpu_intr_from_cpu_3_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_3 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/date.rs b/esp32s3/src/interrupt_core0/date.rs
index 681a59a200..d70077a58d 100644
--- a/esp32s3/src/interrupt_core0/date.rs
+++ b/esp32s3/src/interrupt_core0/date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "interrupt_reg_date",
-                &format_args!("{}", self.interrupt_reg_date().bits()),
-            )
+            .field("interrupt_reg_date", &self.interrupt_reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - version register"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/dcache_preload_int_map.rs b/esp32s3/src/interrupt_core0/dcache_preload_int_map.rs
index 96f155d1f3..0697e4a5ee 100644
--- a/esp32s3/src/interrupt_core0/dcache_preload_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dcache_preload_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_PRELOAD_INT_MAP")
-            .field(
-                "dcache_preload_int_map",
-                &format_args!("{}", self.dcache_preload_int_map().bits()),
-            )
+            .field("dcache_preload_int_map", &self.dcache_preload_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_PRELOAD_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dcache_prelaod interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/dcache_sync_int_map.rs b/esp32s3/src/interrupt_core0/dcache_sync_int_map.rs
index ebd089ce93..9ac051b993 100644
--- a/esp32s3/src/interrupt_core0/dcache_sync_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dcache_sync_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_SYNC_INT_MAP")
-            .field(
-                "dcache_sync_int_map",
-                &format_args!("{}", self.dcache_sync_int_map().bits()),
-            )
+            .field("dcache_sync_int_map", &self.dcache_sync_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_SYNC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dcache_sync interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/dma_apbperi_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core0/dma_apbperi_pms_monitor_violate_intr_map.rs
index cd2d02ef19..e27ad8e4f0 100644
--- a/esp32s3/src/interrupt_core0/dma_apbperi_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_apbperi_pms_monitor_violate_intr_map.rs
@@ -21,17 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "dma_apbperi_pms_monitor_violate_intr_map",
-                &format_args!("{}", self.dma_apbperi_pms_monitor_violate_intr_map().bits()),
+                &self.dma_apbperi_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_pms_monitor_violatile interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/dma_extmem_reject_int_map.rs b/esp32s3/src/interrupt_core0/dma_extmem_reject_int_map.rs
index 5966fe0fbb..4fa7036728 100644
--- a/esp32s3/src/interrupt_core0/dma_extmem_reject_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_extmem_reject_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_EXTMEM_REJECT_INT_MAP")
             .field(
                 "dma_extmem_reject_int_map",
-                &format_args!("{}", self.dma_extmem_reject_int_map().bits()),
+                &self.dma_extmem_reject_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_EXTMEM_REJECT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_extmem_reject interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/dma_in_ch0_int_map.rs b/esp32s3/src/interrupt_core0/dma_in_ch0_int_map.rs
index 442908b488..5eb2714ad9 100644
--- a/esp32s3/src/interrupt_core0/dma_in_ch0_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_in_ch0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH0_INT_MAP")
-            .field(
-                "dma_in_ch0_int_map",
-                &format_args!("{}", self.dma_in_ch0_int_map().bits()),
-            )
+            .field("dma_in_ch0_int_map", &self.dma_in_ch0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/dma_in_ch1_int_map.rs b/esp32s3/src/interrupt_core0/dma_in_ch1_int_map.rs
index 9fe7442353..0d69bf4ede 100644
--- a/esp32s3/src/interrupt_core0/dma_in_ch1_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_in_ch1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH1_INT_MAP")
-            .field(
-                "dma_in_ch1_int_map",
-                &format_args!("{}", self.dma_in_ch1_int_map().bits()),
-            )
+            .field("dma_in_ch1_int_map", &self.dma_in_ch1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/dma_in_ch2_int_map.rs b/esp32s3/src/interrupt_core0/dma_in_ch2_int_map.rs
index e861cfa899..80392714a0 100644
--- a/esp32s3/src/interrupt_core0/dma_in_ch2_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_in_ch2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH2_INT_MAP")
-            .field(
-                "dma_in_ch2_int_map",
-                &format_args!("{}", self.dma_in_ch2_int_map().bits()),
-            )
+            .field("dma_in_ch2_int_map", &self.dma_in_ch2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/dma_in_ch3_int_map.rs b/esp32s3/src/interrupt_core0/dma_in_ch3_int_map.rs
index 1ce5cae590..d8375c3c41 100644
--- a/esp32s3/src/interrupt_core0/dma_in_ch3_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_in_ch3_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH3_INT_MAP")
-            .field(
-                "dma_in_ch3_int_map",
-                &format_args!("{}", self.dma_in_ch3_int_map().bits()),
-            )
+            .field("dma_in_ch3_int_map", &self.dma_in_ch3_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH3_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch3 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/dma_in_ch4_int_map.rs b/esp32s3/src/interrupt_core0/dma_in_ch4_int_map.rs
index c49df85f2e..c4c8331519 100644
--- a/esp32s3/src/interrupt_core0/dma_in_ch4_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_in_ch4_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH4_INT_MAP")
-            .field(
-                "dma_in_ch4_int_map",
-                &format_args!("{}", self.dma_in_ch4_int_map().bits()),
-            )
+            .field("dma_in_ch4_int_map", &self.dma_in_ch4_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH4_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch4 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/dma_out_ch0_int_map.rs b/esp32s3/src/interrupt_core0/dma_out_ch0_int_map.rs
index 1a4ebc0502..74270e328d 100644
--- a/esp32s3/src/interrupt_core0/dma_out_ch0_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_out_ch0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH0_INT_MAP")
-            .field(
-                "dma_out_ch0_int_map",
-                &format_args!("{}", self.dma_out_ch0_int_map().bits()),
-            )
+            .field("dma_out_ch0_int_map", &self.dma_out_ch0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/dma_out_ch1_int_map.rs b/esp32s3/src/interrupt_core0/dma_out_ch1_int_map.rs
index 9487030450..1b08c35f96 100644
--- a/esp32s3/src/interrupt_core0/dma_out_ch1_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_out_ch1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH1_INT_MAP")
-            .field(
-                "dma_out_ch1_int_map",
-                &format_args!("{}", self.dma_out_ch1_int_map().bits()),
-            )
+            .field("dma_out_ch1_int_map", &self.dma_out_ch1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/dma_out_ch2_int_map.rs b/esp32s3/src/interrupt_core0/dma_out_ch2_int_map.rs
index c3ef565293..9f278021ae 100644
--- a/esp32s3/src/interrupt_core0/dma_out_ch2_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_out_ch2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH2_INT_MAP")
-            .field(
-                "dma_out_ch2_int_map",
-                &format_args!("{}", self.dma_out_ch2_int_map().bits()),
-            )
+            .field("dma_out_ch2_int_map", &self.dma_out_ch2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/dma_out_ch3_int_map.rs b/esp32s3/src/interrupt_core0/dma_out_ch3_int_map.rs
index 8ac7aadd72..8e3e23d365 100644
--- a/esp32s3/src/interrupt_core0/dma_out_ch3_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_out_ch3_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH3_INT_MAP")
-            .field(
-                "dma_out_ch3_int_map",
-                &format_args!("{}", self.dma_out_ch3_int_map().bits()),
-            )
+            .field("dma_out_ch3_int_map", &self.dma_out_ch3_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH3_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch3 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/dma_out_ch4_int_map.rs b/esp32s3/src/interrupt_core0/dma_out_ch4_int_map.rs
index 29d3ec4a88..f3b0e0e6be 100644
--- a/esp32s3/src/interrupt_core0/dma_out_ch4_int_map.rs
+++ b/esp32s3/src/interrupt_core0/dma_out_ch4_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH4_INT_MAP")
-            .field(
-                "dma_out_ch4_int_map",
-                &format_args!("{}", self.dma_out_ch4_int_map().bits()),
-            )
+            .field("dma_out_ch4_int_map", &self.dma_out_ch4_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH4_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch4 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/efuse_int_map.rs b/esp32s3/src/interrupt_core0/efuse_int_map.rs
index 3a596047ab..b524b0f79e 100644
--- a/esp32s3/src/interrupt_core0/efuse_int_map.rs
+++ b/esp32s3/src/interrupt_core0/efuse_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EFUSE_INT_MAP")
-            .field(
-                "efuse_int_map",
-                &format_args!("{}", self.efuse_int_map().bits()),
-            )
+            .field("efuse_int_map", &self.efuse_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EFUSE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map efuse interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/gpio_interrupt_app_map.rs b/esp32s3/src/interrupt_core0/gpio_interrupt_app_map.rs
index abb2496204..055b1a17a2 100644
--- a/esp32s3/src/interrupt_core0/gpio_interrupt_app_map.rs
+++ b/esp32s3/src/interrupt_core0/gpio_interrupt_app_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INTERRUPT_APP_MAP")
-            .field(
-                "gpio_interrupt_app_map",
-                &format_args!("{}", self.gpio_interrupt_app_map().bits()),
-            )
+            .field("gpio_interrupt_app_map", &self.gpio_interrupt_app_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_APP_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_app interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/gpio_interrupt_app_nmi_map.rs b/esp32s3/src/interrupt_core0/gpio_interrupt_app_nmi_map.rs
index b6da688023..845d838570 100644
--- a/esp32s3/src/interrupt_core0/gpio_interrupt_app_nmi_map.rs
+++ b/esp32s3/src/interrupt_core0/gpio_interrupt_app_nmi_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("GPIO_INTERRUPT_APP_NMI_MAP")
             .field(
                 "gpio_interrupt_app_nmi_map",
-                &format_args!("{}", self.gpio_interrupt_app_nmi_map().bits()),
+                &self.gpio_interrupt_app_nmi_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_APP_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_app_nmi interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/gpio_interrupt_pro_map.rs b/esp32s3/src/interrupt_core0/gpio_interrupt_pro_map.rs
index feaff4c07a..065795c67e 100644
--- a/esp32s3/src/interrupt_core0/gpio_interrupt_pro_map.rs
+++ b/esp32s3/src/interrupt_core0/gpio_interrupt_pro_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INTERRUPT_PRO_MAP")
-            .field(
-                "gpio_interrupt_pro_map",
-                &format_args!("{}", self.gpio_interrupt_pro_map().bits()),
-            )
+            .field("gpio_interrupt_pro_map", &self.gpio_interrupt_pro_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_PRO_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_pro interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs b/esp32s3/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
index b388cffefb..8e05757f9b 100644
--- a/esp32s3/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
+++ b/esp32s3/src/interrupt_core0/gpio_interrupt_pro_nmi_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("GPIO_INTERRUPT_PRO_NMI_MAP")
             .field(
                 "gpio_interrupt_pro_nmi_map",
-                &format_args!("{}", self.gpio_interrupt_pro_nmi_map().bits()),
+                &self.gpio_interrupt_pro_nmi_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_PRO_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_pro_nmi interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/i2c_ext0_intr_map.rs b/esp32s3/src/interrupt_core0/i2c_ext0_intr_map.rs
index 402a56a706..b6d78ab83f 100644
--- a/esp32s3/src/interrupt_core0/i2c_ext0_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/i2c_ext0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_EXT0_INTR_MAP")
-            .field(
-                "i2c_ext0_intr_map",
-                &format_args!("{}", self.i2c_ext0_intr_map().bits()),
-            )
+            .field("i2c_ext0_intr_map", &self.i2c_ext0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_EXT0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2c_ext0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/i2c_ext1_intr_map.rs b/esp32s3/src/interrupt_core0/i2c_ext1_intr_map.rs
index de82552bbe..b1f3a27058 100644
--- a/esp32s3/src/interrupt_core0/i2c_ext1_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/i2c_ext1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_EXT1_INTR_MAP")
-            .field(
-                "i2c_ext1_intr_map",
-                &format_args!("{}", self.i2c_ext1_intr_map().bits()),
-            )
+            .field("i2c_ext1_intr_map", &self.i2c_ext1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_EXT1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2c_ext1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/i2c_mst_int_map.rs b/esp32s3/src/interrupt_core0/i2c_mst_int_map.rs
index b8b42e32e1..4e07d058bc 100644
--- a/esp32s3/src/interrupt_core0/i2c_mst_int_map.rs
+++ b/esp32s3/src/interrupt_core0/i2c_mst_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_MST_INT_MAP")
-            .field(
-                "i2c_mst_int_map",
-                &format_args!("{}", self.i2c_mst_int_map().bits()),
-            )
+            .field("i2c_mst_int_map", &self.i2c_mst_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_MST_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2c_mst interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/i2s0_int_map.rs b/esp32s3/src/interrupt_core0/i2s0_int_map.rs
index affa4ac6d1..80f05dce6f 100644
--- a/esp32s3/src/interrupt_core0/i2s0_int_map.rs
+++ b/esp32s3/src/interrupt_core0/i2s0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S0_INT_MAP")
-            .field(
-                "i2s0_int_map",
-                &format_args!("{}", self.i2s0_int_map().bits()),
-            )
+            .field("i2s0_int_map", &self.i2s0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2s0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/i2s1_int_map.rs b/esp32s3/src/interrupt_core0/i2s1_int_map.rs
index 9098cc648d..ebf939e93a 100644
--- a/esp32s3/src/interrupt_core0/i2s1_int_map.rs
+++ b/esp32s3/src/interrupt_core0/i2s1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S1_INT_MAP")
-            .field(
-                "i2s1_int_map",
-                &format_args!("{}", self.i2s1_int_map().bits()),
-            )
+            .field("i2s1_int_map", &self.i2s1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2s1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/icache_preload_int_map.rs b/esp32s3/src/interrupt_core0/icache_preload_int_map.rs
index 0ab2e76a08..2a85d69507 100644
--- a/esp32s3/src/interrupt_core0/icache_preload_int_map.rs
+++ b/esp32s3/src/interrupt_core0/icache_preload_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOAD_INT_MAP")
-            .field(
-                "icache_preload_int_map",
-                &format_args!("{}", self.icache_preload_int_map().bits()),
-            )
+            .field("icache_preload_int_map", &self.icache_preload_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOAD_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map icache_preload interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/icache_sync_int_map.rs b/esp32s3/src/interrupt_core0/icache_sync_int_map.rs
index 7e91feccbc..edaf2c443d 100644
--- a/esp32s3/src/interrupt_core0/icache_sync_int_map.rs
+++ b/esp32s3/src/interrupt_core0/icache_sync_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_SYNC_INT_MAP")
-            .field(
-                "icache_sync_int_map",
-                &format_args!("{}", self.icache_sync_int_map().bits()),
-            )
+            .field("icache_sync_int_map", &self.icache_sync_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_SYNC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map icache_sync interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/lcd_cam_int_map.rs b/esp32s3/src/interrupt_core0/lcd_cam_int_map.rs
index 030a0822c2..bd1d6e523b 100644
--- a/esp32s3/src/interrupt_core0/lcd_cam_int_map.rs
+++ b/esp32s3/src/interrupt_core0/lcd_cam_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CAM_INT_MAP")
-            .field(
-                "lcd_cam_int_map",
-                &format_args!("{}", self.lcd_cam_int_map().bits()),
-            )
+            .field("lcd_cam_int_map", &self.lcd_cam_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CAM_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map lcd_cam interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/ledc_int_map.rs b/esp32s3/src/interrupt_core0/ledc_int_map.rs
index 417ed62dfc..95da0b4c63 100644
--- a/esp32s3/src/interrupt_core0/ledc_int_map.rs
+++ b/esp32s3/src/interrupt_core0/ledc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEDC_INT_MAP")
-            .field(
-                "ledc_int_map",
-                &format_args!("{}", self.ledc_int_map().bits()),
-            )
+            .field("ledc_int_map", &self.ledc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEDC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map ledc interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/mac_nmi_map.rs b/esp32s3/src/interrupt_core0/mac_nmi_map.rs
index ff80292741..20f5a629d1 100644
--- a/esp32s3/src/interrupt_core0/mac_nmi_map.rs
+++ b/esp32s3/src/interrupt_core0/mac_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAC_NMI_MAP")
-            .field(
-                "mac_nmi_map",
-                &format_args!("{}", self.mac_nmi_map().bits()),
-            )
+            .field("mac_nmi_map", &self.mac_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAC_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map_nmi interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/pcnt_intr_map.rs b/esp32s3/src/interrupt_core0/pcnt_intr_map.rs
index f4cf713158..d99814c716 100644
--- a/esp32s3/src/interrupt_core0/pcnt_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/pcnt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCNT_INTR_MAP")
-            .field(
-                "pcnt_intr_map",
-                &format_args!("{}", self.pcnt_intr_map().bits()),
-            )
+            .field("pcnt_intr_map", &self.pcnt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCNT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map pcnt interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/peri_backup_int_map.rs b/esp32s3/src/interrupt_core0/peri_backup_int_map.rs
index b18ae3641a..d60169ed6d 100644
--- a/esp32s3/src/interrupt_core0/peri_backup_int_map.rs
+++ b/esp32s3/src/interrupt_core0/peri_backup_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_BACKUP_INT_MAP")
-            .field(
-                "peri_backup_int_map",
-                &format_args!("{}", self.peri_backup_int_map().bits()),
-            )
+            .field("peri_backup_int_map", &self.peri_backup_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_BACKUP_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map peri_backup interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/pro_intr_status_0.rs b/esp32s3/src/interrupt_core0/pro_intr_status_0.rs
index 02403aa936..2ad9a2b220 100644
--- a/esp32s3/src/interrupt_core0/pro_intr_status_0.rs
+++ b/esp32s3/src/interrupt_core0/pro_intr_status_0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_INTR_STATUS_0")
-            .field(
-                "intr_status_0",
-                &format_args!("{}", self.intr_status_0().bits()),
-            )
+            .field("intr_status_0", &self.intr_status_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_INTR_STATUS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_intr_status_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_INTR_STATUS_0_SPEC;
 impl crate::RegisterSpec for PRO_INTR_STATUS_0_SPEC {
diff --git a/esp32s3/src/interrupt_core0/pro_intr_status_1.rs b/esp32s3/src/interrupt_core0/pro_intr_status_1.rs
index f6aaaa5826..71a71c99ab 100644
--- a/esp32s3/src/interrupt_core0/pro_intr_status_1.rs
+++ b/esp32s3/src/interrupt_core0/pro_intr_status_1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_INTR_STATUS_1")
-            .field(
-                "intr_status_1",
-                &format_args!("{}", self.intr_status_1().bits()),
-            )
+            .field("intr_status_1", &self.intr_status_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_INTR_STATUS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_intr_status_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_INTR_STATUS_1_SPEC;
 impl crate::RegisterSpec for PRO_INTR_STATUS_1_SPEC {
diff --git a/esp32s3/src/interrupt_core0/pro_intr_status_2.rs b/esp32s3/src/interrupt_core0/pro_intr_status_2.rs
index 350da0209b..b3796f5179 100644
--- a/esp32s3/src/interrupt_core0/pro_intr_status_2.rs
+++ b/esp32s3/src/interrupt_core0/pro_intr_status_2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_INTR_STATUS_2")
-            .field(
-                "intr_status_2",
-                &format_args!("{}", self.intr_status_2().bits()),
-            )
+            .field("intr_status_2", &self.intr_status_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_INTR_STATUS_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_intr_status_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_INTR_STATUS_2_SPEC;
 impl crate::RegisterSpec for PRO_INTR_STATUS_2_SPEC {
diff --git a/esp32s3/src/interrupt_core0/pro_intr_status_3.rs b/esp32s3/src/interrupt_core0/pro_intr_status_3.rs
index 6c4acf75aa..0bcf2920ae 100644
--- a/esp32s3/src/interrupt_core0/pro_intr_status_3.rs
+++ b/esp32s3/src/interrupt_core0/pro_intr_status_3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_INTR_STATUS_3")
-            .field(
-                "intr_status_3",
-                &format_args!("{}", self.intr_status_3().bits()),
-            )
+            .field("intr_status_3", &self.intr_status_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_INTR_STATUS_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pro_intr_status_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PRO_INTR_STATUS_3_SPEC;
 impl crate::RegisterSpec for PRO_INTR_STATUS_3_SPEC {
diff --git a/esp32s3/src/interrupt_core0/pro_mac_intr_map.rs b/esp32s3/src/interrupt_core0/pro_mac_intr_map.rs
index c6a39b27cd..fdbc656ebe 100644
--- a/esp32s3/src/interrupt_core0/pro_mac_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/pro_mac_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PRO_MAC_INTR_MAP")
-            .field(
-                "mac_intr_map",
-                &format_args!("{}", self.mac_intr_map().bits()),
-            )
+            .field("mac_intr_map", &self.mac_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PRO_MAC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map mac interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/pwm0_intr_map.rs b/esp32s3/src/interrupt_core0/pwm0_intr_map.rs
index 0a356169f6..46d3db4e53 100644
--- a/esp32s3/src/interrupt_core0/pwm0_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/pwm0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM0_INTR_MAP")
-            .field(
-                "pwm0_intr_map",
-                &format_args!("{}", self.pwm0_intr_map().bits()),
-            )
+            .field("pwm0_intr_map", &self.pwm0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/pwm1_intr_map.rs b/esp32s3/src/interrupt_core0/pwm1_intr_map.rs
index 4bf9c56fc5..fd28a8bbfd 100644
--- a/esp32s3/src/interrupt_core0/pwm1_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/pwm1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM1_INTR_MAP")
-            .field(
-                "pwm1_intr_map",
-                &format_args!("{}", self.pwm1_intr_map().bits()),
-            )
+            .field("pwm1_intr_map", &self.pwm1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/pwm2_intr_map.rs b/esp32s3/src/interrupt_core0/pwm2_intr_map.rs
index b93b36f312..0b4ec59305 100644
--- a/esp32s3/src/interrupt_core0/pwm2_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/pwm2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM2_INTR_MAP")
-            .field(
-                "pwm2_intr_map",
-                &format_args!("{}", self.pwm2_intr_map().bits()),
-            )
+            .field("pwm2_intr_map", &self.pwm2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/pwm3_intr_map.rs b/esp32s3/src/interrupt_core0/pwm3_intr_map.rs
index 5d9ae6e914..e1ba6c7c0d 100644
--- a/esp32s3/src/interrupt_core0/pwm3_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/pwm3_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM3_INTR_MAP")
-            .field(
-                "pwm3_intr_map",
-                &format_args!("{}", self.pwm3_intr_map().bits()),
-            )
+            .field("pwm3_intr_map", &self.pwm3_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM3_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm3 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/pwr_intr_map.rs b/esp32s3/src/interrupt_core0/pwr_intr_map.rs
index cdf9ad69a2..659f4839ce 100644
--- a/esp32s3/src/interrupt_core0/pwr_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/pwr_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWR_INTR_MAP")
-            .field(
-                "pwr_intr_map",
-                &format_args!("{}", self.pwr_intr_map().bits()),
-            )
+            .field("pwr_intr_map", &self.pwr_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWR_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwr interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/rmt_intr_map.rs b/esp32s3/src/interrupt_core0/rmt_intr_map.rs
index 0a3309a64f..865750868f 100644
--- a/esp32s3/src/interrupt_core0/rmt_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/rmt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RMT_INTR_MAP")
-            .field(
-                "rmt_intr_map",
-                &format_args!("{}", self.rmt_intr_map().bits()),
-            )
+            .field("rmt_intr_map", &self.rmt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RMT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map rmt interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/rsa_int_map.rs b/esp32s3/src/interrupt_core0/rsa_int_map.rs
index 5e15e62269..b74d607a62 100644
--- a/esp32s3/src/interrupt_core0/rsa_int_map.rs
+++ b/esp32s3/src/interrupt_core0/rsa_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_INT_MAP")
-            .field(
-                "rsa_int_map",
-                &format_args!("{}", self.rsa_int_map().bits()),
-            )
+            .field("rsa_int_map", &self.rsa_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map rsa interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/rtc_core_intr_map.rs b/esp32s3/src/interrupt_core0/rtc_core_intr_map.rs
index cc1a27191f..dc9ae743e6 100644
--- a/esp32s3/src/interrupt_core0/rtc_core_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/rtc_core_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_CORE_INTR_MAP")
-            .field(
-                "rtc_core_intr_map",
-                &format_args!("{}", self.rtc_core_intr_map().bits()),
-            )
+            .field("rtc_core_intr_map", &self.rtc_core_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_CORE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map rtc_core interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/rwble_irq_map.rs b/esp32s3/src/interrupt_core0/rwble_irq_map.rs
index 14a6e08455..82649ec80d 100644
--- a/esp32s3/src/interrupt_core0/rwble_irq_map.rs
+++ b/esp32s3/src/interrupt_core0/rwble_irq_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RWBLE_IRQ_MAP")
-            .field(
-                "rwble_irq_map",
-                &format_args!("{}", self.rwble_irq_map().bits()),
-            )
+            .field("rwble_irq_map", &self.rwble_irq_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RWBLE_IRQ_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map rwble_irq interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/rwble_nmi_map.rs b/esp32s3/src/interrupt_core0/rwble_nmi_map.rs
index a751ca8bc7..ae4d61db4b 100644
--- a/esp32s3/src/interrupt_core0/rwble_nmi_map.rs
+++ b/esp32s3/src/interrupt_core0/rwble_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RWBLE_NMI_MAP")
-            .field(
-                "rwble_nmi_map",
-                &format_args!("{}", self.rwble_nmi_map().bits()),
-            )
+            .field("rwble_nmi_map", &self.rwble_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RWBLE_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map rwble_nmi interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/rwbt_irq_map.rs b/esp32s3/src/interrupt_core0/rwbt_irq_map.rs
index 12c32b58b4..d3cf3ebcd7 100644
--- a/esp32s3/src/interrupt_core0/rwbt_irq_map.rs
+++ b/esp32s3/src/interrupt_core0/rwbt_irq_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RWBT_IRQ_MAP")
-            .field(
-                "rwbt_irq_map",
-                &format_args!("{}", self.rwbt_irq_map().bits()),
-            )
+            .field("rwbt_irq_map", &self.rwbt_irq_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RWBT_IRQ_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map rwbt_irq interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/rwbt_nmi_map.rs b/esp32s3/src/interrupt_core0/rwbt_nmi_map.rs
index 9084a98873..cb6eb576f6 100644
--- a/esp32s3/src/interrupt_core0/rwbt_nmi_map.rs
+++ b/esp32s3/src/interrupt_core0/rwbt_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RWBT_NMI_MAP")
-            .field(
-                "rwbt_nmi_map",
-                &format_args!("{}", self.rwbt_nmi_map().bits()),
-            )
+            .field("rwbt_nmi_map", &self.rwbt_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RWBT_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map mac rwbt_nmi to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/sdio_host_interrupt_map.rs b/esp32s3/src/interrupt_core0/sdio_host_interrupt_map.rs
index 86a1cfb417..03df67dbd0 100644
--- a/esp32s3/src/interrupt_core0/sdio_host_interrupt_map.rs
+++ b/esp32s3/src/interrupt_core0/sdio_host_interrupt_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_HOST_INTERRUPT_MAP")
-            .field(
-                "sdio_host_interrupt_map",
-                &format_args!("{}", self.sdio_host_interrupt_map().bits()),
-            )
+            .field("sdio_host_interrupt_map", &self.sdio_host_interrupt_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_HOST_INTERRUPT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map sdio_host interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/sha_int_map.rs b/esp32s3/src/interrupt_core0/sha_int_map.rs
index ccc6f25341..19b9eba87a 100644
--- a/esp32s3/src/interrupt_core0/sha_int_map.rs
+++ b/esp32s3/src/interrupt_core0/sha_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA_INT_MAP")
-            .field(
-                "sha_int_map",
-                &format_args!("{}", self.sha_int_map().bits()),
-            )
+            .field("sha_int_map", &self.sha_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map sha interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/slc0_intr_map.rs b/esp32s3/src/interrupt_core0/slc0_intr_map.rs
index 48eac85328..1e78d1bf31 100644
--- a/esp32s3/src/interrupt_core0/slc0_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/slc0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC0_INTR_MAP")
-            .field(
-                "slc0_intr_map",
-                &format_args!("{}", self.slc0_intr_map().bits()),
-            )
+            .field("slc0_intr_map", &self.slc0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map slc0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/slc1_intr_map.rs b/esp32s3/src/interrupt_core0/slc1_intr_map.rs
index 61b4e69aba..ccd0923dd2 100644
--- a/esp32s3/src/interrupt_core0/slc1_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/slc1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC1_INTR_MAP")
-            .field(
-                "slc1_intr_map",
-                &format_args!("{}", self.slc1_intr_map().bits()),
-            )
+            .field("slc1_intr_map", &self.slc1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map slc1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/spi2_dma_int_map.rs b/esp32s3/src/interrupt_core0/spi2_dma_int_map.rs
index d0c5bd398b..007174ecaf 100644
--- a/esp32s3/src/interrupt_core0/spi2_dma_int_map.rs
+++ b/esp32s3/src/interrupt_core0/spi2_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI2_DMA_INT_MAP")
-            .field(
-                "spi2_dma_int_map",
-                &format_args!("{}", self.spi2_dma_int_map().bits()),
-            )
+            .field("spi2_dma_int_map", &self.spi2_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI2_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi2_dma interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/spi3_dma_int_map.rs b/esp32s3/src/interrupt_core0/spi3_dma_int_map.rs
index 104240e93c..29c679c4be 100644
--- a/esp32s3/src/interrupt_core0/spi3_dma_int_map.rs
+++ b/esp32s3/src/interrupt_core0/spi3_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI3_DMA_INT_MAP")
-            .field(
-                "spi3_dma_int_map",
-                &format_args!("{}", self.spi3_dma_int_map().bits()),
-            )
+            .field("spi3_dma_int_map", &self.spi3_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI3_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi3_dma interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/spi4_dma_int_map.rs b/esp32s3/src/interrupt_core0/spi4_dma_int_map.rs
index 2e0e3d5641..a46505ef0e 100644
--- a/esp32s3/src/interrupt_core0/spi4_dma_int_map.rs
+++ b/esp32s3/src/interrupt_core0/spi4_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI4_DMA_INT_MAP")
-            .field(
-                "spi4_dma_int_map",
-                &format_args!("{}", self.spi4_dma_int_map().bits()),
-            )
+            .field("spi4_dma_int_map", &self.spi4_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI4_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi4_dma interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/spi_intr_1_map.rs b/esp32s3/src/interrupt_core0/spi_intr_1_map.rs
index 8235432be6..b33c904c3b 100644
--- a/esp32s3/src/interrupt_core0/spi_intr_1_map.rs
+++ b/esp32s3/src/interrupt_core0/spi_intr_1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_INTR_1_MAP")
-            .field(
-                "spi_intr_1_map",
-                &format_args!("{}", self.spi_intr_1_map().bits()),
-            )
+            .field("spi_intr_1_map", &self.spi_intr_1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_INTR_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/spi_intr_2_map.rs b/esp32s3/src/interrupt_core0/spi_intr_2_map.rs
index 21e44c0e90..57ea93b0d9 100644
--- a/esp32s3/src/interrupt_core0/spi_intr_2_map.rs
+++ b/esp32s3/src/interrupt_core0/spi_intr_2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_INTR_2_MAP")
-            .field(
-                "spi_intr_2_map",
-                &format_args!("{}", self.spi_intr_2_map().bits()),
-            )
+            .field("spi_intr_2_map", &self.spi_intr_2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_INTR_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/spi_intr_3_map.rs b/esp32s3/src/interrupt_core0/spi_intr_3_map.rs
index db25b5fd86..aad196a486 100644
--- a/esp32s3/src/interrupt_core0/spi_intr_3_map.rs
+++ b/esp32s3/src/interrupt_core0/spi_intr_3_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_INTR_3_MAP")
-            .field(
-                "spi_intr_3_map",
-                &format_args!("{}", self.spi_intr_3_map().bits()),
-            )
+            .field("spi_intr_3_map", &self.spi_intr_3_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_INTR_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_3 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/spi_intr_4_map.rs b/esp32s3/src/interrupt_core0/spi_intr_4_map.rs
index 09ce03496e..f5b6c1e9e8 100644
--- a/esp32s3/src/interrupt_core0/spi_intr_4_map.rs
+++ b/esp32s3/src/interrupt_core0/spi_intr_4_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_INTR_4_MAP")
-            .field(
-                "spi_intr_4_map",
-                &format_args!("{}", self.spi_intr_4_map().bits()),
-            )
+            .field("spi_intr_4_map", &self.spi_intr_4_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_INTR_4_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_4 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/spi_mem_reject_intr_map.rs b/esp32s3/src/interrupt_core0/spi_mem_reject_intr_map.rs
index a85a7b940f..bc023e1da7 100644
--- a/esp32s3/src/interrupt_core0/spi_mem_reject_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/spi_mem_reject_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_MEM_REJECT_INTR_MAP")
-            .field(
-                "spi_mem_reject_intr_map",
-                &format_args!("{}", self.spi_mem_reject_intr_map().bits()),
-            )
+            .field("spi_mem_reject_intr_map", &self.spi_mem_reject_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_MEM_REJECT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_mem_reject interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/systimer_target0_int_map.rs b/esp32s3/src/interrupt_core0/systimer_target0_int_map.rs
index ee6bd856e7..d261e22977 100644
--- a/esp32s3/src/interrupt_core0/systimer_target0_int_map.rs
+++ b/esp32s3/src/interrupt_core0/systimer_target0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_TARGET0_INT_MAP")
-            .field(
-                "systimer_target0_int_map",
-                &format_args!("{}", self.systimer_target0_int_map().bits()),
-            )
+            .field("systimer_target0_int_map", &self.systimer_target0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map systimer_target0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/systimer_target1_int_map.rs b/esp32s3/src/interrupt_core0/systimer_target1_int_map.rs
index b09c7a55f3..845ad13e2a 100644
--- a/esp32s3/src/interrupt_core0/systimer_target1_int_map.rs
+++ b/esp32s3/src/interrupt_core0/systimer_target1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_TARGET1_INT_MAP")
-            .field(
-                "systimer_target1_int_map",
-                &format_args!("{}", self.systimer_target1_int_map().bits()),
-            )
+            .field("systimer_target1_int_map", &self.systimer_target1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map systimer_target1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/systimer_target2_int_map.rs b/esp32s3/src/interrupt_core0/systimer_target2_int_map.rs
index 8c2c988277..35b5db3f16 100644
--- a/esp32s3/src/interrupt_core0/systimer_target2_int_map.rs
+++ b/esp32s3/src/interrupt_core0/systimer_target2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_TARGET2_INT_MAP")
-            .field(
-                "systimer_target2_int_map",
-                &format_args!("{}", self.systimer_target2_int_map().bits()),
-            )
+            .field("systimer_target2_int_map", &self.systimer_target2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map systimer_target2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/tg1_t0_int_map.rs b/esp32s3/src/interrupt_core0/tg1_t0_int_map.rs
index 940018eb8e..42818d3dc8 100644
--- a/esp32s3/src/interrupt_core0/tg1_t0_int_map.rs
+++ b/esp32s3/src/interrupt_core0/tg1_t0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG1_T0_INT_MAP")
-            .field(
-                "tg1_t0_int_map",
-                &format_args!("{}", self.tg1_t0_int_map().bits()),
-            )
+            .field("tg1_t0_int_map", &self.tg1_t0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG1_T0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg1_t0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/tg1_t1_int_map.rs b/esp32s3/src/interrupt_core0/tg1_t1_int_map.rs
index ced64a2c92..6a216b6e63 100644
--- a/esp32s3/src/interrupt_core0/tg1_t1_int_map.rs
+++ b/esp32s3/src/interrupt_core0/tg1_t1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG1_T1_INT_MAP")
-            .field(
-                "tg1_t1_int_map",
-                &format_args!("{}", self.tg1_t1_int_map().bits()),
-            )
+            .field("tg1_t1_int_map", &self.tg1_t1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG1_T1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg1_t1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/tg1_wdt_int_map.rs b/esp32s3/src/interrupt_core0/tg1_wdt_int_map.rs
index 9d008d5d1a..6b97b83ce9 100644
--- a/esp32s3/src/interrupt_core0/tg1_wdt_int_map.rs
+++ b/esp32s3/src/interrupt_core0/tg1_wdt_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG1_WDT_INT_MAP")
-            .field(
-                "tg1_wdt_int_map",
-                &format_args!("{}", self.tg1_wdt_int_map().bits()),
-            )
+            .field("tg1_wdt_int_map", &self.tg1_wdt_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG1_WDT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg1_wdt interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/tg_t0_int_map.rs b/esp32s3/src/interrupt_core0/tg_t0_int_map.rs
index b9c5b03baa..c80aac200f 100644
--- a/esp32s3/src/interrupt_core0/tg_t0_int_map.rs
+++ b/esp32s3/src/interrupt_core0/tg_t0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG_T0_INT_MAP")
-            .field(
-                "tg_t0_int_map",
-                &format_args!("{}", self.tg_t0_int_map().bits()),
-            )
+            .field("tg_t0_int_map", &self.tg_t0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG_T0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg_t0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/tg_t1_int_map.rs b/esp32s3/src/interrupt_core0/tg_t1_int_map.rs
index ec734e5422..cf0f03d48f 100644
--- a/esp32s3/src/interrupt_core0/tg_t1_int_map.rs
+++ b/esp32s3/src/interrupt_core0/tg_t1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG_T1_INT_MAP")
-            .field(
-                "tg_t1_int_map",
-                &format_args!("{}", self.tg_t1_int_map().bits()),
-            )
+            .field("tg_t1_int_map", &self.tg_t1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG_T1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg_t1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/tg_wdt_int_map.rs b/esp32s3/src/interrupt_core0/tg_wdt_int_map.rs
index 9b593767dc..8b2bcc6190 100644
--- a/esp32s3/src/interrupt_core0/tg_wdt_int_map.rs
+++ b/esp32s3/src/interrupt_core0/tg_wdt_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG_WDT_INT_MAP")
-            .field(
-                "tg_wdt_int_map",
-                &format_args!("{}", self.tg_wdt_int_map().bits()),
-            )
+            .field("tg_wdt_int_map", &self.tg_wdt_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG_WDT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map rg_wdt interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/timer_int1_map.rs b/esp32s3/src/interrupt_core0/timer_int1_map.rs
index 3f73035ea6..e87c7ad9b2 100644
--- a/esp32s3/src/interrupt_core0/timer_int1_map.rs
+++ b/esp32s3/src/interrupt_core0/timer_int1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_INT1_MAP")
-            .field(
-                "timer_int1_map",
-                &format_args!("{}", self.timer_int1_map().bits()),
-            )
+            .field("timer_int1_map", &self.timer_int1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_INT1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map timer_int1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/timer_int2_map.rs b/esp32s3/src/interrupt_core0/timer_int2_map.rs
index db5148e0df..bb9f4cb220 100644
--- a/esp32s3/src/interrupt_core0/timer_int2_map.rs
+++ b/esp32s3/src/interrupt_core0/timer_int2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_INT2_MAP")
-            .field(
-                "timer_int2_map",
-                &format_args!("{}", self.timer_int2_map().bits()),
-            )
+            .field("timer_int2_map", &self.timer_int2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_INT2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map timer_int2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/uart1_intr_map.rs b/esp32s3/src/interrupt_core0/uart1_intr_map.rs
index 0ff8bdd7b8..2670f1e6d8 100644
--- a/esp32s3/src/interrupt_core0/uart1_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/uart1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART1_INTR_MAP")
-            .field(
-                "uart1_intr_map",
-                &format_args!("{}", self.uart1_intr_map().bits()),
-            )
+            .field("uart1_intr_map", &self.uart1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map uart1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/uart2_intr_map.rs b/esp32s3/src/interrupt_core0/uart2_intr_map.rs
index d7d2580897..1c8e9f9de9 100644
--- a/esp32s3/src/interrupt_core0/uart2_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/uart2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART2_INTR_MAP")
-            .field(
-                "uart2_intr_map",
-                &format_args!("{}", self.uart2_intr_map().bits()),
-            )
+            .field("uart2_intr_map", &self.uart2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map uart2 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/uart_intr_map.rs b/esp32s3/src/interrupt_core0/uart_intr_map.rs
index ef8916ded5..7127992648 100644
--- a/esp32s3/src/interrupt_core0/uart_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/uart_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART_INTR_MAP")
-            .field(
-                "uart_intr_map",
-                &format_args!("{}", self.uart_intr_map().bits()),
-            )
+            .field("uart_intr_map", &self.uart_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map uart interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/uhci0_intr_map.rs b/esp32s3/src/interrupt_core0/uhci0_intr_map.rs
index ab961cf43c..d7641cac9f 100644
--- a/esp32s3/src/interrupt_core0/uhci0_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/uhci0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UHCI0_INTR_MAP")
-            .field(
-                "uhci0_intr_map",
-                &format_args!("{}", self.uhci0_intr_map().bits()),
-            )
+            .field("uhci0_intr_map", &self.uhci0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UHCI0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map uhci0 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/uhci1_intr_map.rs b/esp32s3/src/interrupt_core0/uhci1_intr_map.rs
index 0290160269..13e6ca72ba 100644
--- a/esp32s3/src/interrupt_core0/uhci1_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/uhci1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UHCI1_INTR_MAP")
-            .field(
-                "uhci1_intr_map",
-                &format_args!("{}", self.uhci1_intr_map().bits()),
-            )
+            .field("uhci1_intr_map", &self.uhci1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UHCI1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map uhci1 interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/usb_device_int_map.rs b/esp32s3/src/interrupt_core0/usb_device_int_map.rs
index 842d5ec29e..b935f2a931 100644
--- a/esp32s3/src/interrupt_core0/usb_device_int_map.rs
+++ b/esp32s3/src/interrupt_core0/usb_device_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_DEVICE_INT_MAP")
-            .field(
-                "usb_device_int_map",
-                &format_args!("{}", self.usb_device_int_map().bits()),
-            )
+            .field("usb_device_int_map", &self.usb_device_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_DEVICE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map usb_device interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/usb_intr_map.rs b/esp32s3/src/interrupt_core0/usb_intr_map.rs
index 1907abd5b1..fbba764173 100644
--- a/esp32s3/src/interrupt_core0/usb_intr_map.rs
+++ b/esp32s3/src/interrupt_core0/usb_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_INTR_MAP")
-            .field(
-                "usb_intr_map",
-                &format_args!("{}", self.usb_intr_map().bits()),
-            )
+            .field("usb_intr_map", &self.usb_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map usb interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core0/wdg_int_map.rs b/esp32s3/src/interrupt_core0/wdg_int_map.rs
index da638b0f8e..0e7f9a50f2 100644
--- a/esp32s3/src/interrupt_core0/wdg_int_map.rs
+++ b/esp32s3/src/interrupt_core0/wdg_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDG_INT_MAP")
-            .field(
-                "wdg_int_map",
-                &format_args!("{}", self.wdg_int_map().bits()),
-            )
+            .field("wdg_int_map", &self.wdg_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map wdg interrupt to one of core0's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/aes_int_map.rs b/esp32s3/src/interrupt_core1/aes_int_map.rs
index 134359409e..d67bb3325a 100644
--- a/esp32s3/src/interrupt_core1/aes_int_map.rs
+++ b/esp32s3/src/interrupt_core1/aes_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AES_INT_MAP")
-            .field(
-                "aes_int_map",
-                &format_args!("{}", self.aes_int_map().bits()),
-            )
+            .field("aes_int_map", &self.aes_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AES_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map aes interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/apb_adc_int_map.rs b/esp32s3/src/interrupt_core1/apb_adc_int_map.rs
index b9fd67c6b2..1c3f81826f 100644
--- a/esp32s3/src/interrupt_core1/apb_adc_int_map.rs
+++ b/esp32s3/src/interrupt_core1/apb_adc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_ADC_INT_MAP")
-            .field(
-                "apb_adc_int_map",
-                &format_args!("{}", self.apb_adc_int_map().bits()),
-            )
+            .field("apb_adc_int_map", &self.apb_adc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_ADC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map apb_adc interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/app_intr_status_0.rs b/esp32s3/src/interrupt_core1/app_intr_status_0.rs
index be2a327e08..06c4fe82d9 100644
--- a/esp32s3/src/interrupt_core1/app_intr_status_0.rs
+++ b/esp32s3/src/interrupt_core1/app_intr_status_0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_INTR_STATUS_0")
-            .field(
-                "intr_status_0",
-                &format_args!("{}", self.intr_status_0().bits()),
-            )
+            .field("intr_status_0", &self.intr_status_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_INTR_STATUS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_intr_status_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_INTR_STATUS_0_SPEC;
 impl crate::RegisterSpec for APP_INTR_STATUS_0_SPEC {
diff --git a/esp32s3/src/interrupt_core1/app_intr_status_1.rs b/esp32s3/src/interrupt_core1/app_intr_status_1.rs
index 67674c3cd3..2808fdfbec 100644
--- a/esp32s3/src/interrupt_core1/app_intr_status_1.rs
+++ b/esp32s3/src/interrupt_core1/app_intr_status_1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_INTR_STATUS_1")
-            .field(
-                "intr_status_1",
-                &format_args!("{}", self.intr_status_1().bits()),
-            )
+            .field("intr_status_1", &self.intr_status_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_INTR_STATUS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_intr_status_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_INTR_STATUS_1_SPEC;
 impl crate::RegisterSpec for APP_INTR_STATUS_1_SPEC {
diff --git a/esp32s3/src/interrupt_core1/app_intr_status_2.rs b/esp32s3/src/interrupt_core1/app_intr_status_2.rs
index ec577fc277..6f7ded4c65 100644
--- a/esp32s3/src/interrupt_core1/app_intr_status_2.rs
+++ b/esp32s3/src/interrupt_core1/app_intr_status_2.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_INTR_STATUS_2")
-            .field(
-                "intr_status_2",
-                &format_args!("{}", self.intr_status_2().bits()),
-            )
+            .field("intr_status_2", &self.intr_status_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_INTR_STATUS_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_intr_status_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_INTR_STATUS_2_SPEC;
 impl crate::RegisterSpec for APP_INTR_STATUS_2_SPEC {
diff --git a/esp32s3/src/interrupt_core1/app_intr_status_3.rs b/esp32s3/src/interrupt_core1/app_intr_status_3.rs
index c58511a886..8a77016694 100644
--- a/esp32s3/src/interrupt_core1/app_intr_status_3.rs
+++ b/esp32s3/src/interrupt_core1/app_intr_status_3.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_INTR_STATUS_3")
-            .field(
-                "intr_status_3",
-                &format_args!("{}", self.intr_status_3().bits()),
-            )
+            .field("intr_status_3", &self.intr_status_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_INTR_STATUS_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_intr_status_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct APP_INTR_STATUS_3_SPEC;
 impl crate::RegisterSpec for APP_INTR_STATUS_3_SPEC {
diff --git a/esp32s3/src/interrupt_core1/app_mac_intr_map.rs b/esp32s3/src/interrupt_core1/app_mac_intr_map.rs
index d1e48fd829..3786ef7286 100644
--- a/esp32s3/src/interrupt_core1/app_mac_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/app_mac_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APP_MAC_INTR_MAP")
-            .field(
-                "mac_intr_map",
-                &format_args!("{}", self.mac_intr_map().bits()),
-            )
+            .field("mac_intr_map", &self.mac_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APP_MAC_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map mac interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/assist_debug_intr_map.rs b/esp32s3/src/interrupt_core1/assist_debug_intr_map.rs
index 50c53a6a97..db1b0732f6 100644
--- a/esp32s3/src/interrupt_core1/assist_debug_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/assist_debug_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ASSIST_DEBUG_INTR_MAP")
-            .field(
-                "assist_debug_intr_map",
-                &format_args!("{}", self.assist_debug_intr_map().bits()),
-            )
+            .field("assist_debug_intr_map", &self.assist_debug_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ASSIST_DEBUG_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map assist_debug interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/backup_pms_violate_intr_map.rs b/esp32s3/src/interrupt_core1/backup_pms_violate_intr_map.rs
index e911f2c704..0e9fb6cb53 100644
--- a/esp32s3/src/interrupt_core1/backup_pms_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/backup_pms_violate_intr_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_PMS_VIOLATE_INTR_MAP")
             .field(
                 "backup_pms_violate_intr_map",
-                &format_args!("{}", self.backup_pms_violate_intr_map().bits()),
+                &self.backup_pms_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_PMS_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map backup_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/bb_int_map.rs b/esp32s3/src/interrupt_core1/bb_int_map.rs
index d6c851368b..adc3be3df0 100644
--- a/esp32s3/src/interrupt_core1/bb_int_map.rs
+++ b/esp32s3/src/interrupt_core1/bb_int_map.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BB_INT_MAP")
-            .field("bb_int_map", &format_args!("{}", self.bb_int_map().bits()))
+            .field("bb_int_map", &self.bb_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BB_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map bb interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/bt_bb_int_map.rs b/esp32s3/src/interrupt_core1/bt_bb_int_map.rs
index 1254ffb68a..79637c2d2f 100644
--- a/esp32s3/src/interrupt_core1/bt_bb_int_map.rs
+++ b/esp32s3/src/interrupt_core1/bt_bb_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_BB_INT_MAP")
-            .field(
-                "bt_bb_int_map",
-                &format_args!("{}", self.bt_bb_int_map().bits()),
-            )
+            .field("bt_bb_int_map", &self.bt_bb_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_BB_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map bt_bb interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/bt_bb_nmi_map.rs b/esp32s3/src/interrupt_core1/bt_bb_nmi_map.rs
index 8042268dd5..f5013a559e 100644
--- a/esp32s3/src/interrupt_core1/bt_bb_nmi_map.rs
+++ b/esp32s3/src/interrupt_core1/bt_bb_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_BB_NMI_MAP")
-            .field(
-                "bt_bb_nmi_map",
-                &format_args!("{}", self.bt_bb_nmi_map().bits()),
-            )
+            .field("bt_bb_nmi_map", &self.bt_bb_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_BB_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map bb_bt_nmi interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/bt_mac_int_map.rs b/esp32s3/src/interrupt_core1/bt_mac_int_map.rs
index 6f22cb3492..47a39e3e0b 100644
--- a/esp32s3/src/interrupt_core1/bt_mac_int_map.rs
+++ b/esp32s3/src/interrupt_core1/bt_mac_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_MAC_INT_MAP")
-            .field(
-                "bt_mac_int_map",
-                &format_args!("{}", self.bt_mac_int_map().bits()),
-            )
+            .field("bt_mac_int_map", &self.bt_mac_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_MAC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map bb_mac interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/cache_core0_acs_int_map.rs b/esp32s3/src/interrupt_core1/cache_core0_acs_int_map.rs
index b51ef9c40d..4258c246c9 100644
--- a/esp32s3/src/interrupt_core1/cache_core0_acs_int_map.rs
+++ b/esp32s3/src/interrupt_core1/cache_core0_acs_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_CORE0_ACS_INT_MAP")
-            .field(
-                "cache_core0_acs_int_map",
-                &format_args!("{}", self.cache_core0_acs_int_map().bits()),
-            )
+            .field("cache_core0_acs_int_map", &self.cache_core0_acs_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CORE0_ACS_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map cache_core0_acs interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/cache_core1_acs_int_map.rs b/esp32s3/src/interrupt_core1/cache_core1_acs_int_map.rs
index d8c3915dc2..5c35288ed2 100644
--- a/esp32s3/src/interrupt_core1/cache_core1_acs_int_map.rs
+++ b/esp32s3/src/interrupt_core1/cache_core1_acs_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_CORE1_ACS_INT_MAP")
-            .field(
-                "cache_core1_acs_int_map",
-                &format_args!("{}", self.cache_core1_acs_int_map().bits()),
-            )
+            .field("cache_core1_acs_int_map", &self.cache_core1_acs_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CORE1_ACS_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map cache_core1_acs interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/cache_ia_int_map.rs b/esp32s3/src/interrupt_core1/cache_ia_int_map.rs
index ea8707f5c3..0e7b47d876 100644
--- a/esp32s3/src/interrupt_core1/cache_ia_int_map.rs
+++ b/esp32s3/src/interrupt_core1/cache_ia_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_IA_INT_MAP")
-            .field(
-                "cache_ia_int_map",
-                &format_args!("{}", self.cache_ia_int_map().bits()),
-            )
+            .field("cache_ia_int_map", &self.cache_ia_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_IA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map cache_ia interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/can_int_map.rs b/esp32s3/src/interrupt_core1/can_int_map.rs
index 31ba70d550..6a9c83dd1e 100644
--- a/esp32s3/src/interrupt_core1/can_int_map.rs
+++ b/esp32s3/src/interrupt_core1/can_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAN_INT_MAP")
-            .field(
-                "can_int_map",
-                &format_args!("{}", self.can_int_map().bits()),
-            )
+            .field("can_int_map", &self.can_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAN_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map can interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/clock_gate.rs b/esp32s3/src/interrupt_core1/clock_gate.rs
index 700ba1e81e..ca1b57a8cc 100644
--- a/esp32s3/src/interrupt_core1/clock_gate.rs
+++ b/esp32s3/src/interrupt_core1/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("reg_clk_en", &format_args!("{}", self.reg_clk_en().bit()))
+            .field("reg_clk_en", &self.reg_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this register uesd to control clock-gating interupt martrix"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/core_0_dram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core1/core_0_dram0_pms_monitor_violate_intr_map.rs
index 3aeb417d0c..062f4867c1 100644
--- a/esp32s3/src/interrupt_core1/core_0_dram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_0_dram0_pms_monitor_violate_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "core_0_dram0_pms_monitor_violate_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_0_dram0_pms_monitor_violate_intr_map().bits()
-                ),
+                &self.core_0_dram0_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_DRam0_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/core_0_iram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core1/core_0_iram0_pms_monitor_violate_intr_map.rs
index 475d952931..e70e9848b3 100644
--- a/esp32s3/src/interrupt_core1/core_0_iram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_0_iram0_pms_monitor_violate_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "core_0_iram0_pms_monitor_violate_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_0_iram0_pms_monitor_violate_intr_map().bits()
-                ),
+                &self.core_0_iram0_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_IRam0_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_intr_map.rs
index 98cdb803df..249fde4e36 100644
--- a/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_intr_map.rs
@@ -21,17 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "core_0_pif_pms_monitor_violate_intr_map",
-                &format_args!("{}", self.core_0_pif_pms_monitor_violate_intr_map().bits()),
+                &self.core_0_pif_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_PIF_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_size_intr_map.rs b/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_size_intr_map.rs
index dc91631db6..69f5830689 100644
--- a/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_size_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_0_pif_pms_monitor_violate_size_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP")
             .field(
                 "core_0_pif_pms_monitor_violate_size_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_violate_size_intr_map().bits()
-                ),
+                &self.core_0_pif_pms_monitor_violate_size_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core0_PIF_pms_monitor_violatile_size interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/core_1_dram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core1/core_1_dram0_pms_monitor_violate_intr_map.rs
index 1c15a52047..04b8e7b0e3 100644
--- a/esp32s3/src/interrupt_core1/core_1_dram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_1_dram0_pms_monitor_violate_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "core_1_dram0_pms_monitor_violate_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_1_dram0_pms_monitor_violate_intr_map().bits()
-                ),
+                &self.core_1_dram0_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_DRam0_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/core_1_iram0_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core1/core_1_iram0_pms_monitor_violate_intr_map.rs
index 8cb533bfdb..c4ff959f9e 100644
--- a/esp32s3/src/interrupt_core1/core_1_iram0_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_1_iram0_pms_monitor_violate_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "core_1_iram0_pms_monitor_violate_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_1_iram0_pms_monitor_violate_intr_map().bits()
-                ),
+                &self.core_1_iram0_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_IRam0_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_intr_map.rs
index 9c8b28e12f..5fefe797a6 100644
--- a/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_intr_map.rs
@@ -21,17 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "core_1_pif_pms_monitor_violate_intr_map",
-                &format_args!("{}", self.core_1_pif_pms_monitor_violate_intr_map().bits()),
+                &self.core_1_pif_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_PIF_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_size_intr_map.rs b/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_size_intr_map.rs
index 884ca199f5..7ed36c5b75 100644
--- a/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_size_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/core_1_pif_pms_monitor_violate_size_intr_map.rs
@@ -21,20 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP")
             .field(
                 "core_1_pif_pms_monitor_violate_size_intr_map",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_monitor_violate_size_intr_map().bits()
-                ),
+                &self.core_1_pif_pms_monitor_violate_size_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map core1_PIF_pms_monitor_violatile_size interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_0_map.rs b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_0_map.rs
index 97eb5f5275..3158515703 100644
--- a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_0_map.rs
+++ b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_0_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_0_MAP")
-            .field(
-                "cpu_intr_from_cpu_0_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_0_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_0_map", &self.cpu_intr_from_cpu_0_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_0_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_1_map.rs b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_1_map.rs
index 8526ded2ea..d530969ab0 100644
--- a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_1_map.rs
+++ b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_1_MAP")
-            .field(
-                "cpu_intr_from_cpu_1_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_1_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_1_map", &self.cpu_intr_from_cpu_1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_2_map.rs b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_2_map.rs
index 6da641f894..a9112375e1 100644
--- a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_2_map.rs
+++ b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_2_MAP")
-            .field(
-                "cpu_intr_from_cpu_2_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_2_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_2_map", &self.cpu_intr_from_cpu_2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_3_map.rs b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_3_map.rs
index 6e714b0673..cc8d887420 100644
--- a/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_3_map.rs
+++ b/esp32s3/src/interrupt_core1/cpu_intr_from_cpu_3_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_3_MAP")
-            .field(
-                "cpu_intr_from_cpu_3_map",
-                &format_args!("{}", self.cpu_intr_from_cpu_3_map().bits()),
-            )
+            .field("cpu_intr_from_cpu_3_map", &self.cpu_intr_from_cpu_3_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map cpu_intr_from_cpu_3 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/date.rs b/esp32s3/src/interrupt_core1/date.rs
index 61f7646420..a605fd1f1d 100644
--- a/esp32s3/src/interrupt_core1/date.rs
+++ b/esp32s3/src/interrupt_core1/date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "interrupt_date",
-                &format_args!("{}", self.interrupt_date().bits()),
-            )
+            .field("interrupt_date", &self.interrupt_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - version register"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/dcache_preload_int_map.rs b/esp32s3/src/interrupt_core1/dcache_preload_int_map.rs
index 5fdf0839b0..dd933a2845 100644
--- a/esp32s3/src/interrupt_core1/dcache_preload_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dcache_preload_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_PRELOAD_INT_MAP")
-            .field(
-                "dcache_preload_int_map",
-                &format_args!("{}", self.dcache_preload_int_map().bits()),
-            )
+            .field("dcache_preload_int_map", &self.dcache_preload_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_PRELOAD_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dcache_prelaod interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/dcache_sync_int_map.rs b/esp32s3/src/interrupt_core1/dcache_sync_int_map.rs
index b539f20b9b..62e6a89ae3 100644
--- a/esp32s3/src/interrupt_core1/dcache_sync_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dcache_sync_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCACHE_SYNC_INT_MAP")
-            .field(
-                "dcache_sync_int_map",
-                &format_args!("{}", self.dcache_sync_int_map().bits()),
-            )
+            .field("dcache_sync_int_map", &self.dcache_sync_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCACHE_SYNC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dcache_sync interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/dma_apbperi_pms_monitor_violate_intr_map.rs b/esp32s3/src/interrupt_core1/dma_apbperi_pms_monitor_violate_intr_map.rs
index 3c670ee669..ef5b5b481d 100644
--- a/esp32s3/src/interrupt_core1/dma_apbperi_pms_monitor_violate_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_apbperi_pms_monitor_violate_intr_map.rs
@@ -21,17 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP")
             .field(
                 "dma_apbperi_pms_monitor_violate_intr_map",
-                &format_args!("{}", self.dma_apbperi_pms_monitor_violate_intr_map().bits()),
+                &self.dma_apbperi_pms_monitor_violate_intr_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_pms_monitor_violatile interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/dma_extmem_reject_int_map.rs b/esp32s3/src/interrupt_core1/dma_extmem_reject_int_map.rs
index f0052ac0c7..e57ef3e5b6 100644
--- a/esp32s3/src/interrupt_core1/dma_extmem_reject_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_extmem_reject_int_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_EXTMEM_REJECT_INT_MAP")
             .field(
                 "dma_extmem_reject_int_map",
-                &format_args!("{}", self.dma_extmem_reject_int_map().bits()),
+                &self.dma_extmem_reject_int_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_EXTMEM_REJECT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_extmem_reject interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/dma_in_ch0_int_map.rs b/esp32s3/src/interrupt_core1/dma_in_ch0_int_map.rs
index ebcc1f9215..5defd7e5c2 100644
--- a/esp32s3/src/interrupt_core1/dma_in_ch0_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_in_ch0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH0_INT_MAP")
-            .field(
-                "dma_in_ch0_int_map",
-                &format_args!("{}", self.dma_in_ch0_int_map().bits()),
-            )
+            .field("dma_in_ch0_int_map", &self.dma_in_ch0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/dma_in_ch1_int_map.rs b/esp32s3/src/interrupt_core1/dma_in_ch1_int_map.rs
index 75fbd9665c..51c6775185 100644
--- a/esp32s3/src/interrupt_core1/dma_in_ch1_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_in_ch1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH1_INT_MAP")
-            .field(
-                "dma_in_ch1_int_map",
-                &format_args!("{}", self.dma_in_ch1_int_map().bits()),
-            )
+            .field("dma_in_ch1_int_map", &self.dma_in_ch1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/dma_in_ch2_int_map.rs b/esp32s3/src/interrupt_core1/dma_in_ch2_int_map.rs
index 54f2335eeb..84b246991c 100644
--- a/esp32s3/src/interrupt_core1/dma_in_ch2_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_in_ch2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH2_INT_MAP")
-            .field(
-                "dma_in_ch2_int_map",
-                &format_args!("{}", self.dma_in_ch2_int_map().bits()),
-            )
+            .field("dma_in_ch2_int_map", &self.dma_in_ch2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/dma_in_ch3_int_map.rs b/esp32s3/src/interrupt_core1/dma_in_ch3_int_map.rs
index 617ea6289f..1450eb1c22 100644
--- a/esp32s3/src/interrupt_core1/dma_in_ch3_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_in_ch3_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH3_INT_MAP")
-            .field(
-                "dma_in_ch3_int_map",
-                &format_args!("{}", self.dma_in_ch3_int_map().bits()),
-            )
+            .field("dma_in_ch3_int_map", &self.dma_in_ch3_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH3_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch3 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/dma_in_ch4_int_map.rs b/esp32s3/src/interrupt_core1/dma_in_ch4_int_map.rs
index f13371998a..1502824851 100644
--- a/esp32s3/src/interrupt_core1/dma_in_ch4_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_in_ch4_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_IN_CH4_INT_MAP")
-            .field(
-                "dma_in_ch4_int_map",
-                &format_args!("{}", self.dma_in_ch4_int_map().bits()),
-            )
+            .field("dma_in_ch4_int_map", &self.dma_in_ch4_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_IN_CH4_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_in_ch4 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/dma_out_ch0_int_map.rs b/esp32s3/src/interrupt_core1/dma_out_ch0_int_map.rs
index e7e434316e..fb351706f5 100644
--- a/esp32s3/src/interrupt_core1/dma_out_ch0_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_out_ch0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH0_INT_MAP")
-            .field(
-                "dma_out_ch0_int_map",
-                &format_args!("{}", self.dma_out_ch0_int_map().bits()),
-            )
+            .field("dma_out_ch0_int_map", &self.dma_out_ch0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/dma_out_ch1_int_map.rs b/esp32s3/src/interrupt_core1/dma_out_ch1_int_map.rs
index 13944086ed..bd57d6a194 100644
--- a/esp32s3/src/interrupt_core1/dma_out_ch1_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_out_ch1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH1_INT_MAP")
-            .field(
-                "dma_out_ch1_int_map",
-                &format_args!("{}", self.dma_out_ch1_int_map().bits()),
-            )
+            .field("dma_out_ch1_int_map", &self.dma_out_ch1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/dma_out_ch2_int_map.rs b/esp32s3/src/interrupt_core1/dma_out_ch2_int_map.rs
index 9371b845de..e02518d141 100644
--- a/esp32s3/src/interrupt_core1/dma_out_ch2_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_out_ch2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH2_INT_MAP")
-            .field(
-                "dma_out_ch2_int_map",
-                &format_args!("{}", self.dma_out_ch2_int_map().bits()),
-            )
+            .field("dma_out_ch2_int_map", &self.dma_out_ch2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/dma_out_ch3_int_map.rs b/esp32s3/src/interrupt_core1/dma_out_ch3_int_map.rs
index 6a306821e4..e54b5cd111 100644
--- a/esp32s3/src/interrupt_core1/dma_out_ch3_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_out_ch3_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH3_INT_MAP")
-            .field(
-                "dma_out_ch3_int_map",
-                &format_args!("{}", self.dma_out_ch3_int_map().bits()),
-            )
+            .field("dma_out_ch3_int_map", &self.dma_out_ch3_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH3_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch3 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/dma_out_ch4_int_map.rs b/esp32s3/src/interrupt_core1/dma_out_ch4_int_map.rs
index 062e1dd68c..5b88f469e5 100644
--- a/esp32s3/src/interrupt_core1/dma_out_ch4_int_map.rs
+++ b/esp32s3/src/interrupt_core1/dma_out_ch4_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_OUT_CH4_INT_MAP")
-            .field(
-                "dma_out_ch4_int_map",
-                &format_args!("{}", self.dma_out_ch4_int_map().bits()),
-            )
+            .field("dma_out_ch4_int_map", &self.dma_out_ch4_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_OUT_CH4_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map dma_out_ch4 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/efuse_int_map.rs b/esp32s3/src/interrupt_core1/efuse_int_map.rs
index 0ca6a119fd..8beb0027f5 100644
--- a/esp32s3/src/interrupt_core1/efuse_int_map.rs
+++ b/esp32s3/src/interrupt_core1/efuse_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EFUSE_INT_MAP")
-            .field(
-                "efuse_int_map",
-                &format_args!("{}", self.efuse_int_map().bits()),
-            )
+            .field("efuse_int_map", &self.efuse_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EFUSE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map efuse interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/gpio_interrupt_app_map.rs b/esp32s3/src/interrupt_core1/gpio_interrupt_app_map.rs
index d6ac43a37a..a8aaeb074d 100644
--- a/esp32s3/src/interrupt_core1/gpio_interrupt_app_map.rs
+++ b/esp32s3/src/interrupt_core1/gpio_interrupt_app_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INTERRUPT_APP_MAP")
-            .field(
-                "gpio_interrupt_app_map",
-                &format_args!("{}", self.gpio_interrupt_app_map().bits()),
-            )
+            .field("gpio_interrupt_app_map", &self.gpio_interrupt_app_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_APP_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_app interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/gpio_interrupt_app_nmi_map.rs b/esp32s3/src/interrupt_core1/gpio_interrupt_app_nmi_map.rs
index 54e280426a..05ff056d0e 100644
--- a/esp32s3/src/interrupt_core1/gpio_interrupt_app_nmi_map.rs
+++ b/esp32s3/src/interrupt_core1/gpio_interrupt_app_nmi_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("GPIO_INTERRUPT_APP_NMI_MAP")
             .field(
                 "gpio_interrupt_app_nmi_map",
-                &format_args!("{}", self.gpio_interrupt_app_nmi_map().bits()),
+                &self.gpio_interrupt_app_nmi_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_APP_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_app_nmi interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/gpio_interrupt_pro_map.rs b/esp32s3/src/interrupt_core1/gpio_interrupt_pro_map.rs
index 7c5d14983a..9108f77d4a 100644
--- a/esp32s3/src/interrupt_core1/gpio_interrupt_pro_map.rs
+++ b/esp32s3/src/interrupt_core1/gpio_interrupt_pro_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO_INTERRUPT_PRO_MAP")
-            .field(
-                "gpio_interrupt_pro_map",
-                &format_args!("{}", self.gpio_interrupt_pro_map().bits()),
-            )
+            .field("gpio_interrupt_pro_map", &self.gpio_interrupt_pro_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_PRO_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_pro interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/gpio_interrupt_pro_nmi_map.rs b/esp32s3/src/interrupt_core1/gpio_interrupt_pro_nmi_map.rs
index 4ff2cab272..2e9fae1334 100644
--- a/esp32s3/src/interrupt_core1/gpio_interrupt_pro_nmi_map.rs
+++ b/esp32s3/src/interrupt_core1/gpio_interrupt_pro_nmi_map.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("GPIO_INTERRUPT_PRO_NMI_MAP")
             .field(
                 "gpio_interrupt_pro_nmi_map",
-                &format_args!("{}", self.gpio_interrupt_pro_nmi_map().bits()),
+                &self.gpio_interrupt_pro_nmi_map(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_INTERRUPT_PRO_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map gpio_interrupt_pro_nmi interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/i2c_ext0_intr_map.rs b/esp32s3/src/interrupt_core1/i2c_ext0_intr_map.rs
index 6ef69ac15f..9c4b098f81 100644
--- a/esp32s3/src/interrupt_core1/i2c_ext0_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/i2c_ext0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_EXT0_INTR_MAP")
-            .field(
-                "i2c_ext0_intr_map",
-                &format_args!("{}", self.i2c_ext0_intr_map().bits()),
-            )
+            .field("i2c_ext0_intr_map", &self.i2c_ext0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_EXT0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2c_ext0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/i2c_ext1_intr_map.rs b/esp32s3/src/interrupt_core1/i2c_ext1_intr_map.rs
index 0920b5da9f..22ef1d44c3 100644
--- a/esp32s3/src/interrupt_core1/i2c_ext1_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/i2c_ext1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_EXT1_INTR_MAP")
-            .field(
-                "i2c_ext1_intr_map",
-                &format_args!("{}", self.i2c_ext1_intr_map().bits()),
-            )
+            .field("i2c_ext1_intr_map", &self.i2c_ext1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_EXT1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2c_ext1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/i2c_mst_int_map.rs b/esp32s3/src/interrupt_core1/i2c_mst_int_map.rs
index f290d8f3ff..bb81896185 100644
--- a/esp32s3/src/interrupt_core1/i2c_mst_int_map.rs
+++ b/esp32s3/src/interrupt_core1/i2c_mst_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2C_MST_INT_MAP")
-            .field(
-                "i2c_mst_int_map",
-                &format_args!("{}", self.i2c_mst_int_map().bits()),
-            )
+            .field("i2c_mst_int_map", &self.i2c_mst_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2C_MST_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2c_mst interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/i2s0_int_map.rs b/esp32s3/src/interrupt_core1/i2s0_int_map.rs
index 6fcb6968b6..46d2896656 100644
--- a/esp32s3/src/interrupt_core1/i2s0_int_map.rs
+++ b/esp32s3/src/interrupt_core1/i2s0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S0_INT_MAP")
-            .field(
-                "i2s0_int_map",
-                &format_args!("{}", self.i2s0_int_map().bits()),
-            )
+            .field("i2s0_int_map", &self.i2s0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2s0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/i2s1_int_map.rs b/esp32s3/src/interrupt_core1/i2s1_int_map.rs
index 59bd3f7c31..7bad22cd4c 100644
--- a/esp32s3/src/interrupt_core1/i2s1_int_map.rs
+++ b/esp32s3/src/interrupt_core1/i2s1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("I2S1_INT_MAP")
-            .field(
-                "i2s1_int_map",
-                &format_args!("{}", self.i2s1_int_map().bits()),
-            )
+            .field("i2s1_int_map", &self.i2s1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<I2S1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map i2s1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/icache_preload_int_map.rs b/esp32s3/src/interrupt_core1/icache_preload_int_map.rs
index d1979e465e..bc0c8cc5d3 100644
--- a/esp32s3/src/interrupt_core1/icache_preload_int_map.rs
+++ b/esp32s3/src/interrupt_core1/icache_preload_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_PRELOAD_INT_MAP")
-            .field(
-                "icache_preload_int_map",
-                &format_args!("{}", self.icache_preload_int_map().bits()),
-            )
+            .field("icache_preload_int_map", &self.icache_preload_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_PRELOAD_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map icache_preload interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/icache_sync_int_map.rs b/esp32s3/src/interrupt_core1/icache_sync_int_map.rs
index 97d6cb7710..f6f48bdf18 100644
--- a/esp32s3/src/interrupt_core1/icache_sync_int_map.rs
+++ b/esp32s3/src/interrupt_core1/icache_sync_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ICACHE_SYNC_INT_MAP")
-            .field(
-                "icache_sync_int_map",
-                &format_args!("{}", self.icache_sync_int_map().bits()),
-            )
+            .field("icache_sync_int_map", &self.icache_sync_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ICACHE_SYNC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map icache_sync interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/lcd_cam_int_map.rs b/esp32s3/src/interrupt_core1/lcd_cam_int_map.rs
index 6b0a5595a6..8a5a2dcd76 100644
--- a/esp32s3/src/interrupt_core1/lcd_cam_int_map.rs
+++ b/esp32s3/src/interrupt_core1/lcd_cam_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CAM_INT_MAP")
-            .field(
-                "lcd_cam_int_map",
-                &format_args!("{}", self.lcd_cam_int_map().bits()),
-            )
+            .field("lcd_cam_int_map", &self.lcd_cam_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CAM_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map lcd_cam interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/ledc_int_map.rs b/esp32s3/src/interrupt_core1/ledc_int_map.rs
index 44dca87cb3..8b7401a0fe 100644
--- a/esp32s3/src/interrupt_core1/ledc_int_map.rs
+++ b/esp32s3/src/interrupt_core1/ledc_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LEDC_INT_MAP")
-            .field(
-                "ledc_int_map",
-                &format_args!("{}", self.ledc_int_map().bits()),
-            )
+            .field("ledc_int_map", &self.ledc_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LEDC_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map ledc interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/mac_nmi_map.rs b/esp32s3/src/interrupt_core1/mac_nmi_map.rs
index 9596e0856c..dbcea197c4 100644
--- a/esp32s3/src/interrupt_core1/mac_nmi_map.rs
+++ b/esp32s3/src/interrupt_core1/mac_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MAC_NMI_MAP")
-            .field(
-                "mac_nmi_map",
-                &format_args!("{}", self.mac_nmi_map().bits()),
-            )
+            .field("mac_nmi_map", &self.mac_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MAC_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map_nmi interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/pcnt_intr_map.rs b/esp32s3/src/interrupt_core1/pcnt_intr_map.rs
index c1444b9005..20b4ef30da 100644
--- a/esp32s3/src/interrupt_core1/pcnt_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/pcnt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCNT_INTR_MAP")
-            .field(
-                "pcnt_intr_map",
-                &format_args!("{}", self.pcnt_intr_map().bits()),
-            )
+            .field("pcnt_intr_map", &self.pcnt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCNT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map pcnt interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/peri_backup_int_map.rs b/esp32s3/src/interrupt_core1/peri_backup_int_map.rs
index 1355577be2..41714b77ca 100644
--- a/esp32s3/src/interrupt_core1/peri_backup_int_map.rs
+++ b/esp32s3/src/interrupt_core1/peri_backup_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERI_BACKUP_INT_MAP")
-            .field(
-                "peri_backup_int_map",
-                &format_args!("{}", self.peri_backup_int_map().bits()),
-            )
+            .field("peri_backup_int_map", &self.peri_backup_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERI_BACKUP_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map peri_backup interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/pwm0_intr_map.rs b/esp32s3/src/interrupt_core1/pwm0_intr_map.rs
index 49be8967b7..7c4f393ab4 100644
--- a/esp32s3/src/interrupt_core1/pwm0_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/pwm0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM0_INTR_MAP")
-            .field(
-                "pwm0_intr_map",
-                &format_args!("{}", self.pwm0_intr_map().bits()),
-            )
+            .field("pwm0_intr_map", &self.pwm0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/pwm1_intr_map.rs b/esp32s3/src/interrupt_core1/pwm1_intr_map.rs
index 5f0c18604e..1465d13607 100644
--- a/esp32s3/src/interrupt_core1/pwm1_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/pwm1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM1_INTR_MAP")
-            .field(
-                "pwm1_intr_map",
-                &format_args!("{}", self.pwm1_intr_map().bits()),
-            )
+            .field("pwm1_intr_map", &self.pwm1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/pwm2_intr_map.rs b/esp32s3/src/interrupt_core1/pwm2_intr_map.rs
index fd67c0eb1e..00760333f9 100644
--- a/esp32s3/src/interrupt_core1/pwm2_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/pwm2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM2_INTR_MAP")
-            .field(
-                "pwm2_intr_map",
-                &format_args!("{}", self.pwm2_intr_map().bits()),
-            )
+            .field("pwm2_intr_map", &self.pwm2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/pwm3_intr_map.rs b/esp32s3/src/interrupt_core1/pwm3_intr_map.rs
index bcb4e22ab8..444670f00b 100644
--- a/esp32s3/src/interrupt_core1/pwm3_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/pwm3_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWM3_INTR_MAP")
-            .field(
-                "pwm3_intr_map",
-                &format_args!("{}", self.pwm3_intr_map().bits()),
-            )
+            .field("pwm3_intr_map", &self.pwm3_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWM3_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwm3 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/pwr_intr_map.rs b/esp32s3/src/interrupt_core1/pwr_intr_map.rs
index 69600f4738..d73befbaf2 100644
--- a/esp32s3/src/interrupt_core1/pwr_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/pwr_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWR_INTR_MAP")
-            .field(
-                "pwr_intr_map",
-                &format_args!("{}", self.pwr_intr_map().bits()),
-            )
+            .field("pwr_intr_map", &self.pwr_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWR_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map pwr interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/rmt_intr_map.rs b/esp32s3/src/interrupt_core1/rmt_intr_map.rs
index a8a230e173..3f0d4abf8f 100644
--- a/esp32s3/src/interrupt_core1/rmt_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/rmt_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RMT_INTR_MAP")
-            .field(
-                "rmt_intr_map",
-                &format_args!("{}", self.rmt_intr_map().bits()),
-            )
+            .field("rmt_intr_map", &self.rmt_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RMT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map rmt interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/rsa_int_map.rs b/esp32s3/src/interrupt_core1/rsa_int_map.rs
index 1c0b772beb..a66921021d 100644
--- a/esp32s3/src/interrupt_core1/rsa_int_map.rs
+++ b/esp32s3/src/interrupt_core1/rsa_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_INT_MAP")
-            .field(
-                "rsa_int_map",
-                &format_args!("{}", self.rsa_int_map().bits()),
-            )
+            .field("rsa_int_map", &self.rsa_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map rsa interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/rtc_core_intr_map.rs b/esp32s3/src/interrupt_core1/rtc_core_intr_map.rs
index 4bdab91465..bde581721a 100644
--- a/esp32s3/src/interrupt_core1/rtc_core_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/rtc_core_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_CORE_INTR_MAP")
-            .field(
-                "rtc_core_intr_map",
-                &format_args!("{}", self.rtc_core_intr_map().bits()),
-            )
+            .field("rtc_core_intr_map", &self.rtc_core_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_CORE_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map rtc_core interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/rwble_irq_map.rs b/esp32s3/src/interrupt_core1/rwble_irq_map.rs
index e743cfed4c..bed2fb77fc 100644
--- a/esp32s3/src/interrupt_core1/rwble_irq_map.rs
+++ b/esp32s3/src/interrupt_core1/rwble_irq_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RWBLE_IRQ_MAP")
-            .field(
-                "rwble_irq_map",
-                &format_args!("{}", self.rwble_irq_map().bits()),
-            )
+            .field("rwble_irq_map", &self.rwble_irq_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RWBLE_IRQ_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map rwble_irq interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/rwble_nmi_map.rs b/esp32s3/src/interrupt_core1/rwble_nmi_map.rs
index 50cb588f16..54b298c1db 100644
--- a/esp32s3/src/interrupt_core1/rwble_nmi_map.rs
+++ b/esp32s3/src/interrupt_core1/rwble_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RWBLE_NMI_MAP")
-            .field(
-                "rwble_nmi_map",
-                &format_args!("{}", self.rwble_nmi_map().bits()),
-            )
+            .field("rwble_nmi_map", &self.rwble_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RWBLE_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map rwble_nmi interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/rwbt_irq_map.rs b/esp32s3/src/interrupt_core1/rwbt_irq_map.rs
index 4e64889244..709eb76afe 100644
--- a/esp32s3/src/interrupt_core1/rwbt_irq_map.rs
+++ b/esp32s3/src/interrupt_core1/rwbt_irq_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RWBT_IRQ_MAP")
-            .field(
-                "rwbt_irq_map",
-                &format_args!("{}", self.rwbt_irq_map().bits()),
-            )
+            .field("rwbt_irq_map", &self.rwbt_irq_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RWBT_IRQ_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map rwbt_irq interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/rwbt_nmi_map.rs b/esp32s3/src/interrupt_core1/rwbt_nmi_map.rs
index 7dc30a3ee2..d0993a689d 100644
--- a/esp32s3/src/interrupt_core1/rwbt_nmi_map.rs
+++ b/esp32s3/src/interrupt_core1/rwbt_nmi_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RWBT_NMI_MAP")
-            .field(
-                "rwbt_nmi_map",
-                &format_args!("{}", self.rwbt_nmi_map().bits()),
-            )
+            .field("rwbt_nmi_map", &self.rwbt_nmi_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RWBT_NMI_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map rwbt_nmi interupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/sdio_host_interrupt_map.rs b/esp32s3/src/interrupt_core1/sdio_host_interrupt_map.rs
index cdcc7783e0..4a40f3c84c 100644
--- a/esp32s3/src/interrupt_core1/sdio_host_interrupt_map.rs
+++ b/esp32s3/src/interrupt_core1/sdio_host_interrupt_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_HOST_INTERRUPT_MAP")
-            .field(
-                "sdio_host_interrupt_map",
-                &format_args!("{}", self.sdio_host_interrupt_map().bits()),
-            )
+            .field("sdio_host_interrupt_map", &self.sdio_host_interrupt_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_HOST_INTERRUPT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map sdio_host interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/sha_int_map.rs b/esp32s3/src/interrupt_core1/sha_int_map.rs
index ddea10f7cc..3e440bd74a 100644
--- a/esp32s3/src/interrupt_core1/sha_int_map.rs
+++ b/esp32s3/src/interrupt_core1/sha_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SHA_INT_MAP")
-            .field(
-                "sha_int_map",
-                &format_args!("{}", self.sha_int_map().bits()),
-            )
+            .field("sha_int_map", &self.sha_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SHA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map sha interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/slc0_intr_map.rs b/esp32s3/src/interrupt_core1/slc0_intr_map.rs
index 909065eba0..9ff1797214 100644
--- a/esp32s3/src/interrupt_core1/slc0_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/slc0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC0_INTR_MAP")
-            .field(
-                "slc0_intr_map",
-                &format_args!("{}", self.slc0_intr_map().bits()),
-            )
+            .field("slc0_intr_map", &self.slc0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map slc0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/slc1_intr_map.rs b/esp32s3/src/interrupt_core1/slc1_intr_map.rs
index e857675afa..f83e2ac87d 100644
--- a/esp32s3/src/interrupt_core1/slc1_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/slc1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLC1_INTR_MAP")
-            .field(
-                "slc1_intr_map",
-                &format_args!("{}", self.slc1_intr_map().bits()),
-            )
+            .field("slc1_intr_map", &self.slc1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLC1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map slc1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/spi2_dma_int_map.rs b/esp32s3/src/interrupt_core1/spi2_dma_int_map.rs
index 11201dc3bc..fe332edaa8 100644
--- a/esp32s3/src/interrupt_core1/spi2_dma_int_map.rs
+++ b/esp32s3/src/interrupt_core1/spi2_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI2_DMA_INT_MAP")
-            .field(
-                "spi2_dma_int_map",
-                &format_args!("{}", self.spi2_dma_int_map().bits()),
-            )
+            .field("spi2_dma_int_map", &self.spi2_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI2_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi2_dma interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/spi3_dma_int_map.rs b/esp32s3/src/interrupt_core1/spi3_dma_int_map.rs
index f863eec12c..3e6d97e170 100644
--- a/esp32s3/src/interrupt_core1/spi3_dma_int_map.rs
+++ b/esp32s3/src/interrupt_core1/spi3_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI3_DMA_INT_MAP")
-            .field(
-                "spi3_dma_int_map",
-                &format_args!("{}", self.spi3_dma_int_map().bits()),
-            )
+            .field("spi3_dma_int_map", &self.spi3_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI3_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi3_dma interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/spi4_dma_int_map.rs b/esp32s3/src/interrupt_core1/spi4_dma_int_map.rs
index e8ee463033..962320d0e6 100644
--- a/esp32s3/src/interrupt_core1/spi4_dma_int_map.rs
+++ b/esp32s3/src/interrupt_core1/spi4_dma_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI4_DMA_INT_MAP")
-            .field(
-                "spi4_dma_int_map",
-                &format_args!("{}", self.spi4_dma_int_map().bits()),
-            )
+            .field("spi4_dma_int_map", &self.spi4_dma_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI4_DMA_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi4_dma interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/spi_intr_1_map.rs b/esp32s3/src/interrupt_core1/spi_intr_1_map.rs
index 9d9c121f94..94ad0ee9be 100644
--- a/esp32s3/src/interrupt_core1/spi_intr_1_map.rs
+++ b/esp32s3/src/interrupt_core1/spi_intr_1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_INTR_1_MAP")
-            .field(
-                "spi_intr_1_map",
-                &format_args!("{}", self.spi_intr_1_map().bits()),
-            )
+            .field("spi_intr_1_map", &self.spi_intr_1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_INTR_1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/spi_intr_2_map.rs b/esp32s3/src/interrupt_core1/spi_intr_2_map.rs
index 40ee393044..ca8818f444 100644
--- a/esp32s3/src/interrupt_core1/spi_intr_2_map.rs
+++ b/esp32s3/src/interrupt_core1/spi_intr_2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_INTR_2_MAP")
-            .field(
-                "spi_intr_2_map",
-                &format_args!("{}", self.spi_intr_2_map().bits()),
-            )
+            .field("spi_intr_2_map", &self.spi_intr_2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_INTR_2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/spi_intr_3_map.rs b/esp32s3/src/interrupt_core1/spi_intr_3_map.rs
index 91d2b1dbd2..d23ce500c6 100644
--- a/esp32s3/src/interrupt_core1/spi_intr_3_map.rs
+++ b/esp32s3/src/interrupt_core1/spi_intr_3_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_INTR_3_MAP")
-            .field(
-                "spi_intr_3_map",
-                &format_args!("{}", self.spi_intr_3_map().bits()),
-            )
+            .field("spi_intr_3_map", &self.spi_intr_3_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_INTR_3_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_3 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/spi_intr_4_map.rs b/esp32s3/src/interrupt_core1/spi_intr_4_map.rs
index 0a897b1257..0addfa00d0 100644
--- a/esp32s3/src/interrupt_core1/spi_intr_4_map.rs
+++ b/esp32s3/src/interrupt_core1/spi_intr_4_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_INTR_4_MAP")
-            .field(
-                "spi_intr_4_map",
-                &format_args!("{}", self.spi_intr_4_map().bits()),
-            )
+            .field("spi_intr_4_map", &self.spi_intr_4_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_INTR_4_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_intr_4 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/spi_mem_reject_intr_map.rs b/esp32s3/src/interrupt_core1/spi_mem_reject_intr_map.rs
index 325327f9a4..753a503d8b 100644
--- a/esp32s3/src/interrupt_core1/spi_mem_reject_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/spi_mem_reject_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_MEM_REJECT_INTR_MAP")
-            .field(
-                "spi_mem_reject_intr_map",
-                &format_args!("{}", self.spi_mem_reject_intr_map().bits()),
-            )
+            .field("spi_mem_reject_intr_map", &self.spi_mem_reject_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_MEM_REJECT_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map spi_mem_reject interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/systimer_target0_int_map.rs b/esp32s3/src/interrupt_core1/systimer_target0_int_map.rs
index b0d66b2c31..27d4fdc366 100644
--- a/esp32s3/src/interrupt_core1/systimer_target0_int_map.rs
+++ b/esp32s3/src/interrupt_core1/systimer_target0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_TARGET0_INT_MAP")
-            .field(
-                "systimer_target0_int_map",
-                &format_args!("{}", self.systimer_target0_int_map().bits()),
-            )
+            .field("systimer_target0_int_map", &self.systimer_target0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map systimer_target0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/systimer_target1_int_map.rs b/esp32s3/src/interrupt_core1/systimer_target1_int_map.rs
index 265674e353..322363a364 100644
--- a/esp32s3/src/interrupt_core1/systimer_target1_int_map.rs
+++ b/esp32s3/src/interrupt_core1/systimer_target1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_TARGET1_INT_MAP")
-            .field(
-                "systimer_target1_int_map",
-                &format_args!("{}", self.systimer_target1_int_map().bits()),
-            )
+            .field("systimer_target1_int_map", &self.systimer_target1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map systimer_target1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/systimer_target2_int_map.rs b/esp32s3/src/interrupt_core1/systimer_target2_int_map.rs
index e9279b4768..0bebff6323 100644
--- a/esp32s3/src/interrupt_core1/systimer_target2_int_map.rs
+++ b/esp32s3/src/interrupt_core1/systimer_target2_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSTIMER_TARGET2_INT_MAP")
-            .field(
-                "systimer_target2_int_map",
-                &format_args!("{}", self.systimer_target2_int_map().bits()),
-            )
+            .field("systimer_target2_int_map", &self.systimer_target2_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSTIMER_TARGET2_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map systimer_target2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/tg1_t0_int_map.rs b/esp32s3/src/interrupt_core1/tg1_t0_int_map.rs
index fe4e985a92..f3c6107bce 100644
--- a/esp32s3/src/interrupt_core1/tg1_t0_int_map.rs
+++ b/esp32s3/src/interrupt_core1/tg1_t0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG1_T0_INT_MAP")
-            .field(
-                "tg1_t0_int_map",
-                &format_args!("{}", self.tg1_t0_int_map().bits()),
-            )
+            .field("tg1_t0_int_map", &self.tg1_t0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG1_T0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg1_t0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/tg1_t1_int_map.rs b/esp32s3/src/interrupt_core1/tg1_t1_int_map.rs
index fc3f0904c5..acd70ce3c9 100644
--- a/esp32s3/src/interrupt_core1/tg1_t1_int_map.rs
+++ b/esp32s3/src/interrupt_core1/tg1_t1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG1_T1_INT_MAP")
-            .field(
-                "tg1_t1_int_map",
-                &format_args!("{}", self.tg1_t1_int_map().bits()),
-            )
+            .field("tg1_t1_int_map", &self.tg1_t1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG1_T1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg1_t1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/tg1_wdt_int_map.rs b/esp32s3/src/interrupt_core1/tg1_wdt_int_map.rs
index 5d6dc70813..6118202522 100644
--- a/esp32s3/src/interrupt_core1/tg1_wdt_int_map.rs
+++ b/esp32s3/src/interrupt_core1/tg1_wdt_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG1_WDT_INT_MAP")
-            .field(
-                "tg1_wdt_int_map",
-                &format_args!("{}", self.tg1_wdt_int_map().bits()),
-            )
+            .field("tg1_wdt_int_map", &self.tg1_wdt_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG1_WDT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg1_wdt interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/tg_t0_int_map.rs b/esp32s3/src/interrupt_core1/tg_t0_int_map.rs
index 4f1a8d4225..c81d407578 100644
--- a/esp32s3/src/interrupt_core1/tg_t0_int_map.rs
+++ b/esp32s3/src/interrupt_core1/tg_t0_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG_T0_INT_MAP")
-            .field(
-                "tg_t0_int_map",
-                &format_args!("{}", self.tg_t0_int_map().bits()),
-            )
+            .field("tg_t0_int_map", &self.tg_t0_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG_T0_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg_t0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/tg_t1_int_map.rs b/esp32s3/src/interrupt_core1/tg_t1_int_map.rs
index 90fa472fc2..83ead163dd 100644
--- a/esp32s3/src/interrupt_core1/tg_t1_int_map.rs
+++ b/esp32s3/src/interrupt_core1/tg_t1_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG_T1_INT_MAP")
-            .field(
-                "tg_t1_int_map",
-                &format_args!("{}", self.tg_t1_int_map().bits()),
-            )
+            .field("tg_t1_int_map", &self.tg_t1_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG_T1_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map tg_t1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/tg_wdt_int_map.rs b/esp32s3/src/interrupt_core1/tg_wdt_int_map.rs
index 5740207422..67c04c9459 100644
--- a/esp32s3/src/interrupt_core1/tg_wdt_int_map.rs
+++ b/esp32s3/src/interrupt_core1/tg_wdt_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TG_WDT_INT_MAP")
-            .field(
-                "tg_wdt_int_map",
-                &format_args!("{}", self.tg_wdt_int_map().bits()),
-            )
+            .field("tg_wdt_int_map", &self.tg_wdt_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TG_WDT_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map rg_wdt interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/timer_int1_map.rs b/esp32s3/src/interrupt_core1/timer_int1_map.rs
index 8ceab19a67..9ed52d07fc 100644
--- a/esp32s3/src/interrupt_core1/timer_int1_map.rs
+++ b/esp32s3/src/interrupt_core1/timer_int1_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_INT1_MAP")
-            .field(
-                "timer_int1_map",
-                &format_args!("{}", self.timer_int1_map().bits()),
-            )
+            .field("timer_int1_map", &self.timer_int1_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_INT1_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map timer_int1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/timer_int2_map.rs b/esp32s3/src/interrupt_core1/timer_int2_map.rs
index 1457ab899c..87d47da604 100644
--- a/esp32s3/src/interrupt_core1/timer_int2_map.rs
+++ b/esp32s3/src/interrupt_core1/timer_int2_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_INT2_MAP")
-            .field(
-                "timer_int2_map",
-                &format_args!("{}", self.timer_int2_map().bits()),
-            )
+            .field("timer_int2_map", &self.timer_int2_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_INT2_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map timer_int2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/uart1_intr_map.rs b/esp32s3/src/interrupt_core1/uart1_intr_map.rs
index 3acd598238..0c4a20dabe 100644
--- a/esp32s3/src/interrupt_core1/uart1_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/uart1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART1_INTR_MAP")
-            .field(
-                "uart1_intr_map",
-                &format_args!("{}", self.uart1_intr_map().bits()),
-            )
+            .field("uart1_intr_map", &self.uart1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map uart1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/uart2_intr_map.rs b/esp32s3/src/interrupt_core1/uart2_intr_map.rs
index 166beae183..c11d90abe2 100644
--- a/esp32s3/src/interrupt_core1/uart2_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/uart2_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART2_INTR_MAP")
-            .field(
-                "uart2_intr_map",
-                &format_args!("{}", self.uart2_intr_map().bits()),
-            )
+            .field("uart2_intr_map", &self.uart2_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART2_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map uart2 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/uart_intr_map.rs b/esp32s3/src/interrupt_core1/uart_intr_map.rs
index 461c960cc5..6c4ee7c952 100644
--- a/esp32s3/src/interrupt_core1/uart_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/uart_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UART_INTR_MAP")
-            .field(
-                "uart_intr_map",
-                &format_args!("{}", self.uart_intr_map().bits()),
-            )
+            .field("uart_intr_map", &self.uart_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UART_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map uart interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/uhci0_intr_map.rs b/esp32s3/src/interrupt_core1/uhci0_intr_map.rs
index 57dd04d4d3..babcb25844 100644
--- a/esp32s3/src/interrupt_core1/uhci0_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/uhci0_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UHCI0_INTR_MAP")
-            .field(
-                "uhci0_intr_map",
-                &format_args!("{}", self.uhci0_intr_map().bits()),
-            )
+            .field("uhci0_intr_map", &self.uhci0_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UHCI0_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map uhci0 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/uhci1_intr_map.rs b/esp32s3/src/interrupt_core1/uhci1_intr_map.rs
index 89018f4b39..10abb3ea40 100644
--- a/esp32s3/src/interrupt_core1/uhci1_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/uhci1_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UHCI1_INTR_MAP")
-            .field(
-                "uhci1_intr_map",
-                &format_args!("{}", self.uhci1_intr_map().bits()),
-            )
+            .field("uhci1_intr_map", &self.uhci1_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UHCI1_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map uhci1 interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/usb_device_int_map.rs b/esp32s3/src/interrupt_core1/usb_device_int_map.rs
index 774c5199c7..f92ff6131e 100644
--- a/esp32s3/src/interrupt_core1/usb_device_int_map.rs
+++ b/esp32s3/src/interrupt_core1/usb_device_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_DEVICE_INT_MAP")
-            .field(
-                "usb_device_int_map",
-                &format_args!("{}", self.usb_device_int_map().bits()),
-            )
+            .field("usb_device_int_map", &self.usb_device_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_DEVICE_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map usb_device interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/usb_intr_map.rs b/esp32s3/src/interrupt_core1/usb_intr_map.rs
index 8446202078..7a312095ea 100644
--- a/esp32s3/src/interrupt_core1/usb_intr_map.rs
+++ b/esp32s3/src/interrupt_core1/usb_intr_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_INTR_MAP")
-            .field(
-                "usb_intr_map",
-                &format_args!("{}", self.usb_intr_map().bits()),
-            )
+            .field("usb_intr_map", &self.usb_intr_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_INTR_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map usb interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/interrupt_core1/wdg_int_map.rs b/esp32s3/src/interrupt_core1/wdg_int_map.rs
index e17d1436a1..c6e6793671 100644
--- a/esp32s3/src/interrupt_core1/wdg_int_map.rs
+++ b/esp32s3/src/interrupt_core1/wdg_int_map.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDG_INT_MAP")
-            .field(
-                "wdg_int_map",
-                &format_args!("{}", self.wdg_int_map().bits()),
-            )
+            .field("wdg_int_map", &self.wdg_int_map())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDG_INT_MAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - this register used to map wdg interrupt to one of core1's external interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/io_mux/date.rs b/esp32s3/src/io_mux/date.rs
index 58eacc9039..e05305f5d2 100644
--- a/esp32s3/src/io_mux/date.rs
+++ b/esp32s3/src/io_mux/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("reg_date", &format_args!("{}", self.reg_date().bits()))
+            .field("reg_date", &self.reg_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
diff --git a/esp32s3/src/io_mux/gpio.rs b/esp32s3/src/io_mux/gpio.rs
index a2dacae169..b724110ab7 100644
--- a/esp32s3/src/io_mux/gpio.rs
+++ b/esp32s3/src/io_mux/gpio.rs
@@ -107,26 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GPIO")
-            .field("mcu_oe", &format_args!("{}", self.mcu_oe().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("mcu_wpd", &format_args!("{}", self.mcu_wpd().bit()))
-            .field("mcu_wpu", &format_args!("{}", self.mcu_wpu().bit()))
-            .field("mcu_ie", &format_args!("{}", self.mcu_ie().bit()))
-            .field("fun_wpd", &format_args!("{}", self.fun_wpd().bit()))
-            .field("fun_wpu", &format_args!("{}", self.fun_wpu().bit()))
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("fun_drv", &format_args!("{}", self.fun_drv().bits()))
-            .field("mcu_sel", &format_args!("{}", self.mcu_sel().bits()))
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
+            .field("mcu_oe", &self.mcu_oe())
+            .field("slp_sel", &self.slp_sel())
+            .field("mcu_wpd", &self.mcu_wpd())
+            .field("mcu_wpu", &self.mcu_wpu())
+            .field("mcu_ie", &self.mcu_ie())
+            .field("fun_wpd", &self.fun_wpd())
+            .field("fun_wpu", &self.fun_wpu())
+            .field("fun_ie", &self.fun_ie())
+            .field("fun_drv", &self.fun_drv())
+            .field("mcu_sel", &self.mcu_sel())
+            .field("filter_en", &self.filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GPIO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled."]
     #[inline(always)]
diff --git a/esp32s3/src/io_mux/pin_ctrl.rs b/esp32s3/src/io_mux/pin_ctrl.rs
index ecec0837d7..9628744bc2 100644
--- a/esp32s3/src/io_mux/pin_ctrl.rs
+++ b/esp32s3/src/io_mux/pin_ctrl.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN_CTRL")
-            .field("clk_out1", &format_args!("{}", self.clk_out1().bits()))
-            .field("clk_out2", &format_args!("{}", self.clk_out2().bits()))
-            .field("clk_out3", &format_args!("{}", self.clk_out3().bits()))
+            .field("clk_out1", &self.clk_out1())
+            .field("clk_out2", &self.clk_out2())
+            .field("clk_out3", &self.clk_out3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals."]
     #[inline(always)]
diff --git a/esp32s3/src/lcd_cam/cam_ctrl.rs b/esp32s3/src/lcd_cam/cam_ctrl.rs
index 8b50ef3025..ae08e49604 100644
--- a/esp32s3/src/lcd_cam/cam_ctrl.rs
+++ b/esp32s3/src/lcd_cam/cam_ctrl.rs
@@ -107,53 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAM_CTRL")
-            .field("cam_stop_en", &format_args!("{}", self.cam_stop_en().bit()))
-            .field(
-                "cam_vsync_filter_thres",
-                &format_args!("{}", self.cam_vsync_filter_thres().bits()),
-            )
-            .field("cam_update", &format_args!("{}", self.cam_update().bit()))
-            .field(
-                "cam_byte_order",
-                &format_args!("{}", self.cam_byte_order().bit()),
-            )
-            .field(
-                "cam_bit_order",
-                &format_args!("{}", self.cam_bit_order().bit()),
-            )
-            .field(
-                "cam_line_int_en",
-                &format_args!("{}", self.cam_line_int_en().bit()),
-            )
-            .field(
-                "cam_vs_eof_en",
-                &format_args!("{}", self.cam_vs_eof_en().bit()),
-            )
-            .field(
-                "cam_clkm_div_num",
-                &format_args!("{}", self.cam_clkm_div_num().bits()),
-            )
-            .field(
-                "cam_clkm_div_b",
-                &format_args!("{}", self.cam_clkm_div_b().bits()),
-            )
-            .field(
-                "cam_clkm_div_a",
-                &format_args!("{}", self.cam_clkm_div_a().bits()),
-            )
-            .field(
-                "cam_clk_sel",
-                &format_args!("{}", self.cam_clk_sel().bits()),
-            )
+            .field("cam_stop_en", &self.cam_stop_en())
+            .field("cam_vsync_filter_thres", &self.cam_vsync_filter_thres())
+            .field("cam_update", &self.cam_update())
+            .field("cam_byte_order", &self.cam_byte_order())
+            .field("cam_bit_order", &self.cam_bit_order())
+            .field("cam_line_int_en", &self.cam_line_int_en())
+            .field("cam_vs_eof_en", &self.cam_vs_eof_en())
+            .field("cam_clkm_div_num", &self.cam_clkm_div_num())
+            .field("cam_clkm_div_b", &self.cam_clkm_div_b())
+            .field("cam_clkm_div_a", &self.cam_clkm_div_a())
+            .field("cam_clk_sel", &self.cam_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAM_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Camera stop enable signal, 1: camera stops when GDMA Rx FIFO is full. 0: Do not stop."]
     #[inline(always)]
diff --git a/esp32s3/src/lcd_cam/cam_ctrl1.rs b/esp32s3/src/lcd_cam/cam_ctrl1.rs
index 2f16becbf9..a77f7c530c 100644
--- a/esp32s3/src/lcd_cam/cam_ctrl1.rs
+++ b/esp32s3/src/lcd_cam/cam_ctrl1.rs
@@ -102,46 +102,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAM_CTRL1")
-            .field(
-                "cam_rec_data_bytelen",
-                &format_args!("{}", self.cam_rec_data_bytelen().bits()),
-            )
-            .field(
-                "cam_line_int_num",
-                &format_args!("{}", self.cam_line_int_num().bits()),
-            )
-            .field("cam_clk_inv", &format_args!("{}", self.cam_clk_inv().bit()))
-            .field(
-                "cam_vsync_filter_en",
-                &format_args!("{}", self.cam_vsync_filter_en().bit()),
-            )
-            .field(
-                "cam_2byte_en",
-                &format_args!("{}", self.cam_2byte_en().bit()),
-            )
-            .field("cam_de_inv", &format_args!("{}", self.cam_de_inv().bit()))
-            .field(
-                "cam_hsync_inv",
-                &format_args!("{}", self.cam_hsync_inv().bit()),
-            )
-            .field(
-                "cam_vsync_inv",
-                &format_args!("{}", self.cam_vsync_inv().bit()),
-            )
-            .field(
-                "cam_vh_de_mode_en",
-                &format_args!("{}", self.cam_vh_de_mode_en().bit()),
-            )
-            .field("cam_start", &format_args!("{}", self.cam_start().bit()))
+            .field("cam_rec_data_bytelen", &self.cam_rec_data_bytelen())
+            .field("cam_line_int_num", &self.cam_line_int_num())
+            .field("cam_clk_inv", &self.cam_clk_inv())
+            .field("cam_vsync_filter_en", &self.cam_vsync_filter_en())
+            .field("cam_2byte_en", &self.cam_2byte_en())
+            .field("cam_de_inv", &self.cam_de_inv())
+            .field("cam_hsync_inv", &self.cam_hsync_inv())
+            .field("cam_vsync_inv", &self.cam_vsync_inv())
+            .field("cam_vh_de_mode_en", &self.cam_vh_de_mode_en())
+            .field("cam_start", &self.cam_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAM_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Configure camera received data byte length. When the length of received data reaches this value + 1, GDMA in_suc_eof_int is triggered."]
     #[inline(always)]
diff --git a/esp32s3/src/lcd_cam/cam_rgb_yuv.rs b/esp32s3/src/lcd_cam/cam_rgb_yuv.rs
index 99ecf92ce1..d025184e5f 100644
--- a/esp32s3/src/lcd_cam/cam_rgb_yuv.rs
+++ b/esp32s3/src/lcd_cam/cam_rgb_yuv.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAM_RGB_YUV")
-            .field(
-                "cam_conv_8bits_data_inv",
-                &format_args!("{}", self.cam_conv_8bits_data_inv().bit()),
-            )
-            .field(
-                "cam_conv_yuv2yuv_mode",
-                &format_args!("{}", self.cam_conv_yuv2yuv_mode().bits()),
-            )
-            .field(
-                "cam_conv_yuv_mode",
-                &format_args!("{}", self.cam_conv_yuv_mode().bits()),
-            )
-            .field(
-                "cam_conv_protocol_mode",
-                &format_args!("{}", self.cam_conv_protocol_mode().bit()),
-            )
-            .field(
-                "cam_conv_data_out_mode",
-                &format_args!("{}", self.cam_conv_data_out_mode().bit()),
-            )
-            .field(
-                "cam_conv_data_in_mode",
-                &format_args!("{}", self.cam_conv_data_in_mode().bit()),
-            )
-            .field(
-                "cam_conv_mode_8bits_on",
-                &format_args!("{}", self.cam_conv_mode_8bits_on().bit()),
-            )
-            .field(
-                "cam_conv_trans_mode",
-                &format_args!("{}", self.cam_conv_trans_mode().bit()),
-            )
-            .field(
-                "cam_conv_bypass",
-                &format_args!("{}", self.cam_conv_bypass().bit()),
-            )
+            .field("cam_conv_8bits_data_inv", &self.cam_conv_8bits_data_inv())
+            .field("cam_conv_yuv2yuv_mode", &self.cam_conv_yuv2yuv_mode())
+            .field("cam_conv_yuv_mode", &self.cam_conv_yuv_mode())
+            .field("cam_conv_protocol_mode", &self.cam_conv_protocol_mode())
+            .field("cam_conv_data_out_mode", &self.cam_conv_data_out_mode())
+            .field("cam_conv_data_in_mode", &self.cam_conv_data_in_mode())
+            .field("cam_conv_mode_8bits_on", &self.cam_conv_mode_8bits_on())
+            .field("cam_conv_trans_mode", &self.cam_conv_trans_mode())
+            .field("cam_conv_bypass", &self.cam_conv_bypass())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAM_RGB_YUV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 21 - Swap every two 8-bit input data. 1: Enabled. 0: Disabled."]
     #[inline(always)]
diff --git a/esp32s3/src/lcd_cam/lc_dma_int_ena.rs b/esp32s3/src/lcd_cam/lc_dma_int_ena.rs
index 2e857d01e4..39b7cf570c 100644
--- a/esp32s3/src/lcd_cam/lc_dma_int_ena.rs
+++ b/esp32s3/src/lcd_cam/lc_dma_int_ena.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_DMA_INT_ENA")
-            .field(
-                "lcd_vsync_int_ena",
-                &format_args!("{}", self.lcd_vsync_int_ena().bit()),
-            )
-            .field(
-                "lcd_trans_done_int_ena",
-                &format_args!("{}", self.lcd_trans_done_int_ena().bit()),
-            )
-            .field(
-                "cam_vsync_int_ena",
-                &format_args!("{}", self.cam_vsync_int_ena().bit()),
-            )
-            .field(
-                "cam_hs_int_ena",
-                &format_args!("{}", self.cam_hs_int_ena().bit()),
-            )
+            .field("lcd_vsync_int_ena", &self.lcd_vsync_int_ena())
+            .field("lcd_trans_done_int_ena", &self.lcd_trans_done_int_ena())
+            .field("cam_vsync_int_ena", &self.cam_vsync_int_ena())
+            .field("cam_hs_int_ena", &self.cam_hs_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_DMA_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for LCD_CAM_LCD_VSYNC_INT interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/lcd_cam/lc_dma_int_raw.rs b/esp32s3/src/lcd_cam/lc_dma_int_raw.rs
index 9b86fa9abc..b06b10ea99 100644
--- a/esp32s3/src/lcd_cam/lc_dma_int_raw.rs
+++ b/esp32s3/src/lcd_cam/lc_dma_int_raw.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_DMA_INT_RAW")
-            .field(
-                "lcd_vsync_int_raw",
-                &format_args!("{}", self.lcd_vsync_int_raw().bit()),
-            )
-            .field(
-                "lcd_trans_done_int_raw",
-                &format_args!("{}", self.lcd_trans_done_int_raw().bit()),
-            )
-            .field(
-                "cam_vsync_int_raw",
-                &format_args!("{}", self.cam_vsync_int_raw().bit()),
-            )
-            .field(
-                "cam_hs_int_raw",
-                &format_args!("{}", self.cam_hs_int_raw().bit()),
-            )
+            .field("lcd_vsync_int_raw", &self.lcd_vsync_int_raw())
+            .field("lcd_trans_done_int_raw", &self.lcd_trans_done_int_raw())
+            .field("cam_vsync_int_raw", &self.cam_vsync_int_raw())
+            .field("cam_hs_int_raw", &self.cam_hs_int_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_DMA_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "LCD_CAM GDMA raw interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_dma_int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LC_DMA_INT_RAW_SPEC;
 impl crate::RegisterSpec for LC_DMA_INT_RAW_SPEC {
diff --git a/esp32s3/src/lcd_cam/lc_dma_int_st.rs b/esp32s3/src/lcd_cam/lc_dma_int_st.rs
index 5b9b55eac4..5cf15de997 100644
--- a/esp32s3/src/lcd_cam/lc_dma_int_st.rs
+++ b/esp32s3/src/lcd_cam/lc_dma_int_st.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_DMA_INT_ST")
-            .field(
-                "lcd_vsync_int_st",
-                &format_args!("{}", self.lcd_vsync_int_st().bit()),
-            )
-            .field(
-                "lcd_trans_done_int_st",
-                &format_args!("{}", self.lcd_trans_done_int_st().bit()),
-            )
-            .field(
-                "cam_vsync_int_st",
-                &format_args!("{}", self.cam_vsync_int_st().bit()),
-            )
-            .field(
-                "cam_hs_int_st",
-                &format_args!("{}", self.cam_hs_int_st().bit()),
-            )
+            .field("lcd_vsync_int_st", &self.lcd_vsync_int_st())
+            .field("lcd_trans_done_int_st", &self.lcd_trans_done_int_st())
+            .field("cam_vsync_int_st", &self.cam_vsync_int_st())
+            .field("cam_hs_int_st", &self.cam_hs_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_DMA_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "LCD_CAM GDMA masked interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_dma_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LC_DMA_INT_ST_SPEC;
 impl crate::RegisterSpec for LC_DMA_INT_ST_SPEC {
diff --git a/esp32s3/src/lcd_cam/lc_reg_date.rs b/esp32s3/src/lcd_cam/lc_reg_date.rs
index 0a0ac1f5e3..5dfe650111 100644
--- a/esp32s3/src/lcd_cam/lc_reg_date.rs
+++ b/esp32s3/src/lcd_cam/lc_reg_date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LC_REG_DATE")
-            .field("lc_date", &format_args!("{}", self.lc_date().bits()))
+            .field("lc_date", &self.lc_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LC_REG_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version control register"]
     #[inline(always)]
diff --git a/esp32s3/src/lcd_cam/lcd_clock.rs b/esp32s3/src/lcd_cam/lcd_clock.rs
index 53a871ead4..3cb71c8855 100644
--- a/esp32s3/src/lcd_cam/lcd_clock.rs
+++ b/esp32s3/src/lcd_cam/lcd_clock.rs
@@ -89,48 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CLOCK")
-            .field(
-                "lcd_clkcnt_n",
-                &format_args!("{}", self.lcd_clkcnt_n().bits()),
-            )
-            .field(
-                "lcd_clk_equ_sysclk",
-                &format_args!("{}", self.lcd_clk_equ_sysclk().bit()),
-            )
-            .field(
-                "lcd_ck_idle_edge",
-                &format_args!("{}", self.lcd_ck_idle_edge().bit()),
-            )
-            .field(
-                "lcd_ck_out_edge",
-                &format_args!("{}", self.lcd_ck_out_edge().bit()),
-            )
-            .field(
-                "lcd_clkm_div_num",
-                &format_args!("{}", self.lcd_clkm_div_num().bits()),
-            )
-            .field(
-                "lcd_clkm_div_b",
-                &format_args!("{}", self.lcd_clkm_div_b().bits()),
-            )
-            .field(
-                "lcd_clkm_div_a",
-                &format_args!("{}", self.lcd_clkm_div_a().bits()),
-            )
-            .field(
-                "lcd_clk_sel",
-                &format_args!("{}", self.lcd_clk_sel().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("lcd_clkcnt_n", &self.lcd_clkcnt_n())
+            .field("lcd_clk_equ_sysclk", &self.lcd_clk_equ_sysclk())
+            .field("lcd_ck_idle_edge", &self.lcd_ck_idle_edge())
+            .field("lcd_ck_out_edge", &self.lcd_ck_out_edge())
+            .field("lcd_clkm_div_num", &self.lcd_clkm_div_num())
+            .field("lcd_clkm_div_b", &self.lcd_clkm_div_b())
+            .field("lcd_clkm_div_a", &self.lcd_clkm_div_a())
+            .field("lcd_clk_sel", &self.lcd_clk_sel())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - f&lt;SUB>LCD_PCLK&lt;/SUB> = f&lt;SUB>LCD_CLK&lt;/SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0."]
     #[inline(always)]
diff --git a/esp32s3/src/lcd_cam/lcd_cmd_val.rs b/esp32s3/src/lcd_cam/lcd_cmd_val.rs
index fab4cf200b..800ce9d852 100644
--- a/esp32s3/src/lcd_cam/lcd_cmd_val.rs
+++ b/esp32s3/src/lcd_cam/lcd_cmd_val.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CMD_VAL")
-            .field(
-                "lcd_cmd_value",
-                &format_args!("{}", self.lcd_cmd_value().bits()),
-            )
+            .field("lcd_cmd_value", &self.lcd_cmd_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CMD_VAL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The LCD write command value."]
     #[inline(always)]
diff --git a/esp32s3/src/lcd_cam/lcd_ctrl.rs b/esp32s3/src/lcd_cam/lcd_ctrl.rs
index 3320099e68..ac02b1a4be 100644
--- a/esp32s3/src/lcd_cam/lcd_ctrl.rs
+++ b/esp32s3/src/lcd_cam/lcd_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CTRL")
-            .field(
-                "lcd_hb_front",
-                &format_args!("{}", self.lcd_hb_front().bits()),
-            )
-            .field(
-                "lcd_va_height",
-                &format_args!("{}", self.lcd_va_height().bits()),
-            )
-            .field(
-                "lcd_vt_height",
-                &format_args!("{}", self.lcd_vt_height().bits()),
-            )
-            .field(
-                "lcd_rgb_mode_en",
-                &format_args!("{}", self.lcd_rgb_mode_en().bit()),
-            )
+            .field("lcd_hb_front", &self.lcd_hb_front())
+            .field("lcd_va_height", &self.lcd_va_height())
+            .field("lcd_vt_height", &self.lcd_vt_height())
+            .field("lcd_rgb_mode_en", &self.lcd_rgb_mode_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - It is the horizontal blank front porch of a frame."]
     #[inline(always)]
diff --git a/esp32s3/src/lcd_cam/lcd_ctrl1.rs b/esp32s3/src/lcd_cam/lcd_ctrl1.rs
index 983818cc00..25bbe23a66 100644
--- a/esp32s3/src/lcd_cam/lcd_ctrl1.rs
+++ b/esp32s3/src/lcd_cam/lcd_ctrl1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CTRL1")
-            .field(
-                "lcd_vb_front",
-                &format_args!("{}", self.lcd_vb_front().bits()),
-            )
-            .field(
-                "lcd_ha_width",
-                &format_args!("{}", self.lcd_ha_width().bits()),
-            )
-            .field(
-                "lcd_ht_width",
-                &format_args!("{}", self.lcd_ht_width().bits()),
-            )
+            .field("lcd_vb_front", &self.lcd_vb_front())
+            .field("lcd_ha_width", &self.lcd_ha_width())
+            .field("lcd_ht_width", &self.lcd_ht_width())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - It is the vertical blank front porch of a frame."]
     #[inline(always)]
diff --git a/esp32s3/src/lcd_cam/lcd_ctrl2.rs b/esp32s3/src/lcd_cam/lcd_ctrl2.rs
index c502669102..3a1c61ce58 100644
--- a/esp32s3/src/lcd_cam/lcd_ctrl2.rs
+++ b/esp32s3/src/lcd_cam/lcd_ctrl2.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_CTRL2")
-            .field(
-                "lcd_vsync_width",
-                &format_args!("{}", self.lcd_vsync_width().bits()),
-            )
-            .field(
-                "lcd_vsync_idle_pol",
-                &format_args!("{}", self.lcd_vsync_idle_pol().bit()),
-            )
-            .field(
-                "lcd_de_idle_pol",
-                &format_args!("{}", self.lcd_de_idle_pol().bit()),
-            )
-            .field(
-                "lcd_hs_blank_en",
-                &format_args!("{}", self.lcd_hs_blank_en().bit()),
-            )
-            .field(
-                "lcd_hsync_width",
-                &format_args!("{}", self.lcd_hsync_width().bits()),
-            )
-            .field(
-                "lcd_hsync_idle_pol",
-                &format_args!("{}", self.lcd_hsync_idle_pol().bit()),
-            )
-            .field(
-                "lcd_hsync_position",
-                &format_args!("{}", self.lcd_hsync_position().bits()),
-            )
+            .field("lcd_vsync_width", &self.lcd_vsync_width())
+            .field("lcd_vsync_idle_pol", &self.lcd_vsync_idle_pol())
+            .field("lcd_de_idle_pol", &self.lcd_de_idle_pol())
+            .field("lcd_hs_blank_en", &self.lcd_hs_blank_en())
+            .field("lcd_hsync_width", &self.lcd_hsync_width())
+            .field("lcd_hsync_idle_pol", &self.lcd_hsync_idle_pol())
+            .field("lcd_hsync_position", &self.lcd_hsync_position())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - It is the width of LCD_VSYNC active pulse in a line."]
     #[inline(always)]
diff --git a/esp32s3/src/lcd_cam/lcd_data_dout_mode.rs b/esp32s3/src/lcd_cam/lcd_data_dout_mode.rs
index 36ef904d78..952f4dc9be 100644
--- a/esp32s3/src/lcd_cam/lcd_data_dout_mode.rs
+++ b/esp32s3/src/lcd_cam/lcd_data_dout_mode.rs
@@ -177,49 +177,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_DATA_DOUT_MODE")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bits()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bits()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bits()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bits()))
-            .field("dout4_mode", &format_args!("{}", self.dout4_mode().bits()))
-            .field("dout5_mode", &format_args!("{}", self.dout5_mode().bits()))
-            .field("dout6_mode", &format_args!("{}", self.dout6_mode().bits()))
-            .field("dout7_mode", &format_args!("{}", self.dout7_mode().bits()))
-            .field("dout8_mode", &format_args!("{}", self.dout8_mode().bits()))
-            .field("dout9_mode", &format_args!("{}", self.dout9_mode().bits()))
-            .field(
-                "dout10_mode",
-                &format_args!("{}", self.dout10_mode().bits()),
-            )
-            .field(
-                "dout11_mode",
-                &format_args!("{}", self.dout11_mode().bits()),
-            )
-            .field(
-                "dout12_mode",
-                &format_args!("{}", self.dout12_mode().bits()),
-            )
-            .field(
-                "dout13_mode",
-                &format_args!("{}", self.dout13_mode().bits()),
-            )
-            .field(
-                "dout14_mode",
-                &format_args!("{}", self.dout14_mode().bits()),
-            )
-            .field(
-                "dout15_mode",
-                &format_args!("{}", self.dout15_mode().bits()),
-            )
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
+            .field("dout4_mode", &self.dout4_mode())
+            .field("dout5_mode", &self.dout5_mode())
+            .field("dout6_mode", &self.dout6_mode())
+            .field("dout7_mode", &self.dout7_mode())
+            .field("dout8_mode", &self.dout8_mode())
+            .field("dout9_mode", &self.dout9_mode())
+            .field("dout10_mode", &self.dout10_mode())
+            .field("dout11_mode", &self.dout11_mode())
+            .field("dout12_mode", &self.dout12_mode())
+            .field("dout13_mode", &self.dout13_mode())
+            .field("dout14_mode", &self.dout14_mode())
+            .field("dout15_mode", &self.dout15_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_DATA_DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The output data bit (0-15) is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[doc = ""]
diff --git a/esp32s3/src/lcd_cam/lcd_dly_mode.rs b/esp32s3/src/lcd_cam/lcd_dly_mode.rs
index 90a21aef88..c1bf0d9764 100644
--- a/esp32s3/src/lcd_cam/lcd_dly_mode.rs
+++ b/esp32s3/src/lcd_cam/lcd_dly_mode.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_DLY_MODE")
-            .field(
-                "lcd_cd_mode",
-                &format_args!("{}", self.lcd_cd_mode().bits()),
-            )
-            .field(
-                "lcd_de_mode",
-                &format_args!("{}", self.lcd_de_mode().bits()),
-            )
-            .field(
-                "lcd_hsync_mode",
-                &format_args!("{}", self.lcd_hsync_mode().bits()),
-            )
-            .field(
-                "lcd_vsync_mode",
-                &format_args!("{}", self.lcd_vsync_mode().bits()),
-            )
+            .field("lcd_cd_mode", &self.lcd_cd_mode())
+            .field("lcd_de_mode", &self.lcd_de_mode())
+            .field("lcd_hsync_mode", &self.lcd_hsync_mode())
+            .field("lcd_vsync_mode", &self.lcd_vsync_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_DLY_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK."]
     #[inline(always)]
diff --git a/esp32s3/src/lcd_cam/lcd_misc.rs b/esp32s3/src/lcd_cam/lcd_misc.rs
index 81551ebe1d..fefbd3a4cf 100644
--- a/esp32s3/src/lcd_cam/lcd_misc.rs
+++ b/esp32s3/src/lcd_cam/lcd_misc.rs
@@ -91,48 +91,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_MISC")
-            .field(
-                "lcd_afifo_threshold_num",
-                &format_args!("{}", self.lcd_afifo_threshold_num().bits()),
-            )
-            .field(
-                "lcd_vfk_cyclelen",
-                &format_args!("{}", self.lcd_vfk_cyclelen().bits()),
-            )
-            .field(
-                "lcd_vbk_cyclelen",
-                &format_args!("{}", self.lcd_vbk_cyclelen().bits()),
-            )
-            .field(
-                "lcd_next_frame_en",
-                &format_args!("{}", self.lcd_next_frame_en().bit()),
-            )
-            .field("lcd_bk_en", &format_args!("{}", self.lcd_bk_en().bit()))
-            .field(
-                "lcd_cd_data_set",
-                &format_args!("{}", self.lcd_cd_data_set().bit()),
-            )
-            .field(
-                "lcd_cd_dummy_set",
-                &format_args!("{}", self.lcd_cd_dummy_set().bit()),
-            )
-            .field(
-                "lcd_cd_cmd_set",
-                &format_args!("{}", self.lcd_cd_cmd_set().bit()),
-            )
-            .field(
-                "lcd_cd_idle_edge",
-                &format_args!("{}", self.lcd_cd_idle_edge().bit()),
-            )
+            .field("lcd_afifo_threshold_num", &self.lcd_afifo_threshold_num())
+            .field("lcd_vfk_cyclelen", &self.lcd_vfk_cyclelen())
+            .field("lcd_vbk_cyclelen", &self.lcd_vbk_cyclelen())
+            .field("lcd_next_frame_en", &self.lcd_next_frame_en())
+            .field("lcd_bk_en", &self.lcd_bk_en())
+            .field("lcd_cd_data_set", &self.lcd_cd_data_set())
+            .field("lcd_cd_dummy_set", &self.lcd_cd_dummy_set())
+            .field("lcd_cd_cmd_set", &self.lcd_cd_cmd_set())
+            .field("lcd_cd_idle_edge", &self.lcd_cd_idle_edge())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 1:5 - Set the threshold for Async Tx FIFO full event."]
     #[inline(always)]
diff --git a/esp32s3/src/lcd_cam/lcd_rgb_yuv.rs b/esp32s3/src/lcd_cam/lcd_rgb_yuv.rs
index a2e5ad1253..0dce81076d 100644
--- a/esp32s3/src/lcd_cam/lcd_rgb_yuv.rs
+++ b/esp32s3/src/lcd_cam/lcd_rgb_yuv.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_RGB_YUV")
-            .field(
-                "lcd_conv_8bits_data_inv",
-                &format_args!("{}", self.lcd_conv_8bits_data_inv().bit()),
-            )
-            .field(
-                "lcd_conv_yuv2yuv_mode",
-                &format_args!("{}", self.lcd_conv_yuv2yuv_mode().bits()),
-            )
-            .field(
-                "lcd_conv_yuv_mode",
-                &format_args!("{}", self.lcd_conv_yuv_mode().bits()),
-            )
-            .field(
-                "lcd_conv_protocol_mode",
-                &format_args!("{}", self.lcd_conv_protocol_mode().bit()),
-            )
-            .field(
-                "lcd_conv_data_out_mode",
-                &format_args!("{}", self.lcd_conv_data_out_mode().bit()),
-            )
-            .field(
-                "lcd_conv_data_in_mode",
-                &format_args!("{}", self.lcd_conv_data_in_mode().bit()),
-            )
-            .field(
-                "lcd_conv_mode_8bits_on",
-                &format_args!("{}", self.lcd_conv_mode_8bits_on().bit()),
-            )
-            .field(
-                "lcd_conv_trans_mode",
-                &format_args!("{}", self.lcd_conv_trans_mode().bit()),
-            )
-            .field(
-                "lcd_conv_bypass",
-                &format_args!("{}", self.lcd_conv_bypass().bit()),
-            )
+            .field("lcd_conv_8bits_data_inv", &self.lcd_conv_8bits_data_inv())
+            .field("lcd_conv_yuv2yuv_mode", &self.lcd_conv_yuv2yuv_mode())
+            .field("lcd_conv_yuv_mode", &self.lcd_conv_yuv_mode())
+            .field("lcd_conv_protocol_mode", &self.lcd_conv_protocol_mode())
+            .field("lcd_conv_data_out_mode", &self.lcd_conv_data_out_mode())
+            .field("lcd_conv_data_in_mode", &self.lcd_conv_data_in_mode())
+            .field("lcd_conv_mode_8bits_on", &self.lcd_conv_mode_8bits_on())
+            .field("lcd_conv_trans_mode", &self.lcd_conv_trans_mode())
+            .field("lcd_conv_bypass", &self.lcd_conv_bypass())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_RGB_YUV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - Swap every two 8-bit input data. 1: Enabled. 0: Disabled."]
     #[inline(always)]
diff --git a/esp32s3/src/lcd_cam/lcd_user.rs b/esp32s3/src/lcd_cam/lcd_user.rs
index 22ae40740e..bd98c00a15 100644
--- a/esp32s3/src/lcd_cam/lcd_user.rs
+++ b/esp32s3/src/lcd_cam/lcd_user.rs
@@ -127,52 +127,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LCD_USER")
-            .field(
-                "lcd_dout_cyclelen",
-                &format_args!("{}", self.lcd_dout_cyclelen().bits()),
-            )
-            .field(
-                "lcd_always_out_en",
-                &format_args!("{}", self.lcd_always_out_en().bit()),
-            )
-            .field(
-                "lcd_8bits_order",
-                &format_args!("{}", self.lcd_8bits_order().bit()),
-            )
-            .field("lcd_update", &format_args!("{}", self.lcd_update().bit()))
-            .field(
-                "lcd_bit_order",
-                &format_args!("{}", self.lcd_bit_order().bit()),
-            )
-            .field(
-                "lcd_byte_order",
-                &format_args!("{}", self.lcd_byte_order().bit()),
-            )
-            .field(
-                "lcd_2byte_en",
-                &format_args!("{}", self.lcd_2byte_en().bit()),
-            )
-            .field("lcd_dout", &format_args!("{}", self.lcd_dout().bit()))
-            .field("lcd_dummy", &format_args!("{}", self.lcd_dummy().bit()))
-            .field("lcd_cmd", &format_args!("{}", self.lcd_cmd().bit()))
-            .field("lcd_start", &format_args!("{}", self.lcd_start().bit()))
-            .field(
-                "lcd_dummy_cyclelen",
-                &format_args!("{}", self.lcd_dummy_cyclelen().bits()),
-            )
-            .field(
-                "lcd_cmd_2_cycle_en",
-                &format_args!("{}", self.lcd_cmd_2_cycle_en().bit()),
-            )
+            .field("lcd_dout_cyclelen", &self.lcd_dout_cyclelen())
+            .field("lcd_always_out_en", &self.lcd_always_out_en())
+            .field("lcd_8bits_order", &self.lcd_8bits_order())
+            .field("lcd_update", &self.lcd_update())
+            .field("lcd_bit_order", &self.lcd_bit_order())
+            .field("lcd_byte_order", &self.lcd_byte_order())
+            .field("lcd_2byte_en", &self.lcd_2byte_en())
+            .field("lcd_dout", &self.lcd_dout())
+            .field("lcd_dummy", &self.lcd_dummy())
+            .field("lcd_cmd", &self.lcd_cmd())
+            .field("lcd_start", &self.lcd_start())
+            .field("lcd_dummy_cyclelen", &self.lcd_dummy_cyclelen())
+            .field("lcd_cmd_2_cycle_en", &self.lcd_cmd_2_cycle_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LCD_USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - Configure the cycles for DOUT phase of LCD module. The cycles = this value + 1."]
     #[inline(always)]
diff --git a/esp32s3/src/ledc/ch/conf0.rs b/esp32s3/src/ledc/ch/conf0.rs
index d0b7c7616f..f4416558ad 100644
--- a/esp32s3/src/ledc/ch/conf0.rs
+++ b/esp32s3/src/ledc/ch/conf0.rs
@@ -66,24 +66,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("timer_sel", &format_args!("{}", self.timer_sel().bits()))
-            .field("sig_out_en", &format_args!("{}", self.sig_out_en().bit()))
-            .field("idle_lv", &format_args!("{}", self.idle_lv().bit()))
-            .field("ovf_num", &format_args!("{}", self.ovf_num().bits()))
-            .field("ovf_cnt_en", &format_args!("{}", self.ovf_cnt_en().bit()))
-            .field(
-                "ovf_cnt_reset_st",
-                &format_args!("{}", self.ovf_cnt_reset_st().bit()),
-            )
+            .field("timer_sel", &self.timer_sel())
+            .field("sig_out_en", &self.sig_out_en())
+            .field("idle_lv", &self.idle_lv())
+            .field("ovf_num", &self.ovf_num())
+            .field("ovf_cnt_en", &self.ovf_cnt_en())
+            .field("ovf_cnt_reset_st", &self.ovf_cnt_reset_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to select one of timers for channel %s. 0: select timer0 1: select timer1 2: select timer2 3: select timer3"]
     #[inline(always)]
diff --git a/esp32s3/src/ledc/ch/conf1.rs b/esp32s3/src/ledc/ch/conf1.rs
index e413752336..4d1d093144 100644
--- a/esp32s3/src/ledc/ch/conf1.rs
+++ b/esp32s3/src/ledc/ch/conf1.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field("duty_scale", &format_args!("{}", self.duty_scale().bits()))
-            .field("duty_cycle", &format_args!("{}", self.duty_cycle().bits()))
-            .field("duty_num", &format_args!("{}", self.duty_num().bits()))
-            .field("duty_inc", &format_args!("{}", self.duty_inc().bit()))
-            .field("duty_start", &format_args!("{}", self.duty_start().bit()))
+            .field("duty_scale", &self.duty_scale())
+            .field("duty_cycle", &self.duty_cycle())
+            .field("duty_num", &self.duty_num())
+            .field("duty_inc", &self.duty_inc())
+            .field("duty_start", &self.duty_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This register is used to configure the changing step scale of duty on channel %s."]
     #[inline(always)]
diff --git a/esp32s3/src/ledc/ch/duty.rs b/esp32s3/src/ledc/ch/duty.rs
index dd4f150d88..03e1bba638 100644
--- a/esp32s3/src/ledc/ch/duty.rs
+++ b/esp32s3/src/ledc/ch/duty.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DUTY")
-            .field("duty", &format_args!("{}", self.duty().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DUTY").field("duty", &self.duty()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/ledc/ch/duty_r.rs b/esp32s3/src/ledc/ch/duty_r.rs
index b1870f3014..28e94586f2 100644
--- a/esp32s3/src/ledc/ch/duty_r.rs
+++ b/esp32s3/src/ledc/ch/duty_r.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DUTY_R")
-            .field("duty_r", &format_args!("{}", self.duty_r().bits()))
+            .field("duty_r", &self.duty_r())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DUTY_R_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Current duty cycle for channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`duty_r::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DUTY_R_SPEC;
 impl crate::RegisterSpec for DUTY_R_SPEC {
diff --git a/esp32s3/src/ledc/ch/hpoint.rs b/esp32s3/src/ledc/ch/hpoint.rs
index 559465bb7f..c2c53fa871 100644
--- a/esp32s3/src/ledc/ch/hpoint.rs
+++ b/esp32s3/src/ledc/ch/hpoint.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPOINT")
-            .field("hpoint", &format_args!("{}", self.hpoint().bits()))
+            .field("hpoint", &self.hpoint())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPOINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - The output value changes to high when the selected timers has reached the value specified by this register."]
     #[inline(always)]
diff --git a/esp32s3/src/ledc/conf.rs b/esp32s3/src/ledc/conf.rs
index 4a420f4ae7..9dfab9d08b 100644
--- a/esp32s3/src/ledc/conf.rs
+++ b/esp32s3/src/ledc/conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field(
-                "apb_clk_sel",
-                &format_args!("{}", self.apb_clk_sel().bits()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("apb_clk_sel", &self.apb_clk_sel())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This bit is used to select clock source for the 4 timers . 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK"]
     #[inline(always)]
diff --git a/esp32s3/src/ledc/date.rs b/esp32s3/src/ledc/date.rs
index 62e261b35d..66676d6094 100644
--- a/esp32s3/src/ledc/date.rs
+++ b/esp32s3/src/ledc/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/ledc/int_ena.rs b/esp32s3/src/ledc/int_ena.rs
index 573e013acf..ae57204c6d 100644
--- a/esp32s3/src/ledc/int_ena.rs
+++ b/esp32s3/src/ledc/int_ena.rs
@@ -165,59 +165,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field(
-                "duty_chng_end_ch6",
-                &format_args!("{}", self.duty_chng_end_ch6().bit()),
-            )
-            .field(
-                "duty_chng_end_ch7",
-                &format_args!("{}", self.duty_chng_end_ch7().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
-            .field("ovf_cnt_ch6", &format_args!("{}", self.ovf_cnt_ch6().bit()))
-            .field("ovf_cnt_ch7", &format_args!("{}", self.ovf_cnt_ch7().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("duty_chng_end_ch6", &self.duty_chng_end_ch6())
+            .field("duty_chng_end_ch7", &self.duty_chng_end_ch7())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
+            .field("ovf_cnt_ch6", &self.ovf_cnt_ch6())
+            .field("ovf_cnt_ch7", &self.ovf_cnt_ch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the TIMER(0-3)_OVF interrupt."]
     #[doc = ""]
diff --git a/esp32s3/src/ledc/int_raw.rs b/esp32s3/src/ledc/int_raw.rs
index e8cda2b2fe..21ab54c3a1 100644
--- a/esp32s3/src/ledc/int_raw.rs
+++ b/esp32s3/src/ledc/int_raw.rs
@@ -165,59 +165,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field(
-                "duty_chng_end_ch6",
-                &format_args!("{}", self.duty_chng_end_ch6().bit()),
-            )
-            .field(
-                "duty_chng_end_ch7",
-                &format_args!("{}", self.duty_chng_end_ch7().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
-            .field("ovf_cnt_ch6", &format_args!("{}", self.ovf_cnt_ch6().bit()))
-            .field("ovf_cnt_ch7", &format_args!("{}", self.ovf_cnt_ch7().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("duty_chng_end_ch6", &self.duty_chng_end_ch6())
+            .field("duty_chng_end_ch7", &self.duty_chng_end_ch7())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
+            .field("ovf_cnt_ch6", &self.ovf_cnt_ch6())
+            .field("ovf_cnt_ch7", &self.ovf_cnt_ch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Triggered when the timer(0-3) has reached its maximum counter value."]
     #[doc = ""]
diff --git a/esp32s3/src/ledc/int_st.rs b/esp32s3/src/ledc/int_st.rs
index 72c09e8394..9674d08294 100644
--- a/esp32s3/src/ledc/int_st.rs
+++ b/esp32s3/src/ledc/int_st.rs
@@ -157,59 +157,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("timer0_ovf", &format_args!("{}", self.timer0_ovf().bit()))
-            .field("timer1_ovf", &format_args!("{}", self.timer1_ovf().bit()))
-            .field("timer2_ovf", &format_args!("{}", self.timer2_ovf().bit()))
-            .field("timer3_ovf", &format_args!("{}", self.timer3_ovf().bit()))
-            .field(
-                "duty_chng_end_ch0",
-                &format_args!("{}", self.duty_chng_end_ch0().bit()),
-            )
-            .field(
-                "duty_chng_end_ch1",
-                &format_args!("{}", self.duty_chng_end_ch1().bit()),
-            )
-            .field(
-                "duty_chng_end_ch2",
-                &format_args!("{}", self.duty_chng_end_ch2().bit()),
-            )
-            .field(
-                "duty_chng_end_ch3",
-                &format_args!("{}", self.duty_chng_end_ch3().bit()),
-            )
-            .field(
-                "duty_chng_end_ch4",
-                &format_args!("{}", self.duty_chng_end_ch4().bit()),
-            )
-            .field(
-                "duty_chng_end_ch5",
-                &format_args!("{}", self.duty_chng_end_ch5().bit()),
-            )
-            .field(
-                "duty_chng_end_ch6",
-                &format_args!("{}", self.duty_chng_end_ch6().bit()),
-            )
-            .field(
-                "duty_chng_end_ch7",
-                &format_args!("{}", self.duty_chng_end_ch7().bit()),
-            )
-            .field("ovf_cnt_ch0", &format_args!("{}", self.ovf_cnt_ch0().bit()))
-            .field("ovf_cnt_ch1", &format_args!("{}", self.ovf_cnt_ch1().bit()))
-            .field("ovf_cnt_ch2", &format_args!("{}", self.ovf_cnt_ch2().bit()))
-            .field("ovf_cnt_ch3", &format_args!("{}", self.ovf_cnt_ch3().bit()))
-            .field("ovf_cnt_ch4", &format_args!("{}", self.ovf_cnt_ch4().bit()))
-            .field("ovf_cnt_ch5", &format_args!("{}", self.ovf_cnt_ch5().bit()))
-            .field("ovf_cnt_ch6", &format_args!("{}", self.ovf_cnt_ch6().bit()))
-            .field("ovf_cnt_ch7", &format_args!("{}", self.ovf_cnt_ch7().bit()))
+            .field("timer0_ovf", &self.timer0_ovf())
+            .field("timer1_ovf", &self.timer1_ovf())
+            .field("timer2_ovf", &self.timer2_ovf())
+            .field("timer3_ovf", &self.timer3_ovf())
+            .field("duty_chng_end_ch0", &self.duty_chng_end_ch0())
+            .field("duty_chng_end_ch1", &self.duty_chng_end_ch1())
+            .field("duty_chng_end_ch2", &self.duty_chng_end_ch2())
+            .field("duty_chng_end_ch3", &self.duty_chng_end_ch3())
+            .field("duty_chng_end_ch4", &self.duty_chng_end_ch4())
+            .field("duty_chng_end_ch5", &self.duty_chng_end_ch5())
+            .field("duty_chng_end_ch6", &self.duty_chng_end_ch6())
+            .field("duty_chng_end_ch7", &self.duty_chng_end_ch7())
+            .field("ovf_cnt_ch0", &self.ovf_cnt_ch0())
+            .field("ovf_cnt_ch1", &self.ovf_cnt_ch1())
+            .field("ovf_cnt_ch2", &self.ovf_cnt_ch2())
+            .field("ovf_cnt_ch3", &self.ovf_cnt_ch3())
+            .field("ovf_cnt_ch4", &self.ovf_cnt_ch4())
+            .field("ovf_cnt_ch5", &self.ovf_cnt_ch5())
+            .field("ovf_cnt_ch6", &self.ovf_cnt_ch6())
+            .field("ovf_cnt_ch7", &self.ovf_cnt_ch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/ledc/timer/conf.rs b/esp32s3/src/ledc/timer/conf.rs
index 20def84693..d770931c62 100644
--- a/esp32s3/src/ledc/timer/conf.rs
+++ b/esp32s3/src/ledc/timer/conf.rs
@@ -55,20 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field("duty_res", &format_args!("{}", self.duty_res().bits()))
-            .field("clk_div", &format_args!("{}", self.clk_div().bits()))
-            .field("pause", &format_args!("{}", self.pause().bit()))
-            .field("rst", &format_args!("{}", self.rst().bit()))
-            .field("tick_sel", &format_args!("{}", self.tick_sel().bit()))
+            .field("duty_res", &self.duty_res())
+            .field("clk_div", &self.clk_div())
+            .field("pause", &self.pause())
+            .field("rst", &self.rst())
+            .field("tick_sel", &self.tick_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - This register is used to control the range of the counter in timer %s."]
     #[inline(always)]
diff --git a/esp32s3/src/ledc/timer/value.rs b/esp32s3/src/ledc/timer/value.rs
index ee3ddb9c1b..598dc71136 100644
--- a/esp32s3/src/ledc/timer/value.rs
+++ b/esp32s3/src/ledc/timer/value.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("VALUE")
-            .field("cnt", &format_args!("{}", self.cnt().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VALUE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("VALUE").field("cnt", &self.cnt()).finish()
     }
 }
 #[doc = "Timer 0 current counter value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s3/src/lib.rs b/esp32s3/src/lib.rs
index 20be1c4e3a..8246968a8b 100644
--- a/esp32s3/src/lib.rs
+++ b/esp32s3/src/lib.rs
@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for ESP32-S3 microcontrollers (generated using svd2rust v0.33.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for ESP32-S3 microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")]
diff --git a/esp32s3/src/mcpwm0/cap_ch.rs b/esp32s3/src/mcpwm0/cap_ch.rs
index c65d337a76..ffa38ba07f 100644
--- a/esp32s3/src/mcpwm0/cap_ch.rs
+++ b/esp32s3/src/mcpwm0/cap_ch.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_CH")
-            .field("value", &format_args!("{}", self.value().bits()))
+            .field("value", &self.value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_CH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Value of last capture on channel %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_ch::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CAP_CH_SPEC;
 impl crate::RegisterSpec for CAP_CH_SPEC {
diff --git a/esp32s3/src/mcpwm0/cap_ch_cfg.rs b/esp32s3/src/mcpwm0/cap_ch_cfg.rs
index 625f867b5d..27980b8a1d 100644
--- a/esp32s3/src/mcpwm0/cap_ch_cfg.rs
+++ b/esp32s3/src/mcpwm0/cap_ch_cfg.rs
@@ -46,19 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_CH_CFG")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
-            .field("in_invert", &format_args!("{}", self.in_invert().bit()))
+            .field("en", &self.en())
+            .field("mode", &self.mode())
+            .field("prescale", &self.prescale())
+            .field("in_invert", &self.in_invert())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_CH_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, capture on channel 0 is enabled"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/cap_status.rs b/esp32s3/src/mcpwm0/cap_status.rs
index bc686ac57a..24aafdc56e 100644
--- a/esp32s3/src/mcpwm0/cap_status.rs
+++ b/esp32s3/src/mcpwm0/cap_status.rs
@@ -27,18 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_STATUS")
-            .field("cap0_edge", &format_args!("{}", self.cap0_edge().bit()))
-            .field("cap1_edge", &format_args!("{}", self.cap1_edge().bit()))
-            .field("cap2_edge", &format_args!("{}", self.cap2_edge().bit()))
+            .field("cap0_edge", &self.cap0_edge())
+            .field("cap1_edge", &self.cap1_edge())
+            .field("cap2_edge", &self.cap2_edge())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Edge of last capture trigger\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cap_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CAP_STATUS_SPEC;
 impl crate::RegisterSpec for CAP_STATUS_SPEC {
diff --git a/esp32s3/src/mcpwm0/cap_timer_cfg.rs b/esp32s3/src/mcpwm0/cap_timer_cfg.rs
index 0678a31f25..a63151447c 100644
--- a/esp32s3/src/mcpwm0/cap_timer_cfg.rs
+++ b/esp32s3/src/mcpwm0/cap_timer_cfg.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_TIMER_CFG")
-            .field(
-                "cap_timer_en",
-                &format_args!("{}", self.cap_timer_en().bit()),
-            )
-            .field(
-                "cap_synci_en",
-                &format_args!("{}", self.cap_synci_en().bit()),
-            )
-            .field(
-                "cap_synci_sel",
-                &format_args!("{}", self.cap_synci_sel().bits()),
-            )
+            .field("cap_timer_en", &self.cap_timer_en())
+            .field("cap_synci_en", &self.cap_synci_en())
+            .field("cap_synci_sel", &self.cap_synci_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_TIMER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, capture timer incrementing under APB_clk is enabled."]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/cap_timer_phase.rs b/esp32s3/src/mcpwm0/cap_timer_phase.rs
index c476ea129f..4a1f0aea4a 100644
--- a/esp32s3/src/mcpwm0/cap_timer_phase.rs
+++ b/esp32s3/src/mcpwm0/cap_timer_phase.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CAP_TIMER_PHASE")
-            .field("cap_phase", &format_args!("{}", self.cap_phase().bits()))
+            .field("cap_phase", &self.cap_phase())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CAP_TIMER_PHASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Phase value for capture timer sync operation."]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/ch/chopper_cfg.rs b/esp32s3/src/mcpwm0/ch/chopper_cfg.rs
index 6a4536f365..12fedf7f2d 100644
--- a/esp32s3/src/mcpwm0/ch/chopper_cfg.rs
+++ b/esp32s3/src/mcpwm0/ch/chopper_cfg.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHOPPER_CFG")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
-            .field("duty", &format_args!("{}", self.duty().bits()))
-            .field("oshtwth", &format_args!("{}", self.oshtwth().bits()))
-            .field("out_invert", &format_args!("{}", self.out_invert().bit()))
-            .field("in_invert", &format_args!("{}", self.in_invert().bit()))
+            .field("en", &self.en())
+            .field("prescale", &self.prescale())
+            .field("duty", &self.duty())
+            .field("oshtwth", &self.oshtwth())
+            .field("out_invert", &self.out_invert())
+            .field("in_invert", &self.in_invert())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHOPPER_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, carrier0 function is enabled. When cleared, carrier0 is bypassed"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/ch/cmpr_cfg.rs b/esp32s3/src/mcpwm0/ch/cmpr_cfg.rs
index 263d424ea9..702e14c54a 100644
--- a/esp32s3/src/mcpwm0/ch/cmpr_cfg.rs
+++ b/esp32s3/src/mcpwm0/ch/cmpr_cfg.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMPR_CFG")
-            .field("a_upmethod", &format_args!("{}", self.a_upmethod().bits()))
-            .field("b_upmethod", &format_args!("{}", self.b_upmethod().bits()))
-            .field("a_shdw_full", &format_args!("{}", self.a_shdw_full().bit()))
-            .field("b_shdw_full", &format_args!("{}", self.b_shdw_full().bit()))
+            .field("a_upmethod", &self.a_upmethod())
+            .field("b_upmethod", &self.b_upmethod())
+            .field("a_shdw_full", &self.a_shdw_full())
+            .field("b_shdw_full", &self.b_shdw_full())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMPR_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update."]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/ch/cmpr_value0.rs b/esp32s3/src/mcpwm0/ch/cmpr_value0.rs
index c6904c4c1a..fcce680ea8 100644
--- a/esp32s3/src/mcpwm0/ch/cmpr_value0.rs
+++ b/esp32s3/src/mcpwm0/ch/cmpr_value0.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CMPR_VALUE0")
-            .field("a", &format_args!("{}", self.a().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMPR_VALUE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CMPR_VALUE0").field("a", &self.a()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/mcpwm0/ch/cmpr_value1.rs b/esp32s3/src/mcpwm0/ch/cmpr_value1.rs
index 9c8a7efd85..ff4c89752a 100644
--- a/esp32s3/src/mcpwm0/ch/cmpr_value1.rs
+++ b/esp32s3/src/mcpwm0/ch/cmpr_value1.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CMPR_VALUE1")
-            .field("b", &format_args!("{}", self.b().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMPR_VALUE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CMPR_VALUE1").field("b", &self.b()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/mcpwm0/ch/db_cfg.rs b/esp32s3/src/mcpwm0/ch/db_cfg.rs
index b36610c97a..262475e9ba 100644
--- a/esp32s3/src/mcpwm0/ch/db_cfg.rs
+++ b/esp32s3/src/mcpwm0/ch/db_cfg.rs
@@ -116,39 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DB_CFG")
-            .field(
-                "fed_upmethod",
-                &format_args!("{}", self.fed_upmethod().bits()),
-            )
-            .field(
-                "red_upmethod",
-                &format_args!("{}", self.red_upmethod().bits()),
-            )
-            .field("deb_mode", &format_args!("{}", self.deb_mode().bit()))
-            .field("a_outswap", &format_args!("{}", self.a_outswap().bit()))
-            .field("b_outswap", &format_args!("{}", self.b_outswap().bit()))
-            .field("red_insel", &format_args!("{}", self.red_insel().bit()))
-            .field("fed_insel", &format_args!("{}", self.fed_insel().bit()))
-            .field(
-                "red_outinvert",
-                &format_args!("{}", self.red_outinvert().bit()),
-            )
-            .field(
-                "fed_outinvert",
-                &format_args!("{}", self.fed_outinvert().bit()),
-            )
-            .field("a_outbypass", &format_args!("{}", self.a_outbypass().bit()))
-            .field("b_outbypass", &format_args!("{}", self.b_outbypass().bit()))
-            .field("clk_sel", &format_args!("{}", self.clk_sel().bit()))
+            .field("fed_upmethod", &self.fed_upmethod())
+            .field("red_upmethod", &self.red_upmethod())
+            .field("deb_mode", &self.deb_mode())
+            .field("a_outswap", &self.a_outswap())
+            .field("b_outswap", &self.b_outswap())
+            .field("red_insel", &self.red_insel())
+            .field("fed_insel", &self.fed_insel())
+            .field("red_outinvert", &self.red_outinvert())
+            .field("fed_outinvert", &self.fed_outinvert())
+            .field("a_outbypass", &self.a_outbypass())
+            .field("b_outbypass", &self.b_outbypass())
+            .field("clk_sel", &self.clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DB_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/ch/db_fed_cfg.rs b/esp32s3/src/mcpwm0/ch/db_fed_cfg.rs
index 4ae07f0c7c..37112a6205 100644
--- a/esp32s3/src/mcpwm0/ch/db_fed_cfg.rs
+++ b/esp32s3/src/mcpwm0/ch/db_fed_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DB_FED_CFG")
-            .field("fed", &format_args!("{}", self.fed().bits()))
+            .field("fed", &self.fed())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DB_FED_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Shadow register for FED"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/ch/db_red_cfg.rs b/esp32s3/src/mcpwm0/ch/db_red_cfg.rs
index f1c69cb94a..f435bbb604 100644
--- a/esp32s3/src/mcpwm0/ch/db_red_cfg.rs
+++ b/esp32s3/src/mcpwm0/ch/db_red_cfg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DB_RED_CFG")
-            .field("red", &format_args!("{}", self.red().bits()))
+            .field("red", &self.red())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DB_RED_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Shadow register for RED"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/ch/gen.rs b/esp32s3/src/mcpwm0/ch/gen.rs
index 5d8addc59e..0d27bbd1b8 100644
--- a/esp32s3/src/mcpwm0/ch/gen.rs
+++ b/esp32s3/src/mcpwm0/ch/gen.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN")
-            .field("utez", &format_args!("{}", self.utez().bits()))
-            .field("utep", &format_args!("{}", self.utep().bits()))
-            .field("utea", &format_args!("{}", self.utea().bits()))
-            .field("uteb", &format_args!("{}", self.uteb().bits()))
-            .field("ut0", &format_args!("{}", self.ut0().bits()))
-            .field("ut1", &format_args!("{}", self.ut1().bits()))
-            .field("dtez", &format_args!("{}", self.dtez().bits()))
-            .field("dtep", &format_args!("{}", self.dtep().bits()))
-            .field("dtea", &format_args!("{}", self.dtea().bits()))
-            .field("dteb", &format_args!("{}", self.dteb().bits()))
-            .field("dt0", &format_args!("{}", self.dt0().bits()))
-            .field("dt1", &format_args!("{}", self.dt1().bits()))
+            .field("utez", &self.utez())
+            .field("utep", &self.utep())
+            .field("utea", &self.utea())
+            .field("uteb", &self.uteb())
+            .field("ut0", &self.ut0())
+            .field("ut1", &self.ut1())
+            .field("dtez", &self.dtez())
+            .field("dtep", &self.dtep())
+            .field("dtea", &self.dtea())
+            .field("dteb", &self.dteb())
+            .field("dt0", &self.dt0())
+            .field("dt1", &self.dt1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Action on PWM0A triggered by event TEZ when timer increasing"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/ch/gen_cfg0.rs b/esp32s3/src/mcpwm0/ch/gen_cfg0.rs
index b5ca1a8c99..356a8e6f98 100644
--- a/esp32s3/src/mcpwm0/ch/gen_cfg0.rs
+++ b/esp32s3/src/mcpwm0/ch/gen_cfg0.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_CFG0")
-            .field(
-                "cfg_upmethod",
-                &format_args!("{}", self.cfg_upmethod().bits()),
-            )
-            .field("t0_sel", &format_args!("{}", self.t0_sel().bits()))
-            .field("t1_sel", &format_args!("{}", self.t1_sel().bits()))
+            .field("cfg_upmethod", &self.cfg_upmethod())
+            .field("t0_sel", &self.t0_sel())
+            .field("t1_sel", &self.t1_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/ch/gen_force.rs b/esp32s3/src/mcpwm0/ch/gen_force.rs
index 3fcb77525c..a6a8be6844 100644
--- a/esp32s3/src/mcpwm0/ch/gen_force.rs
+++ b/esp32s3/src/mcpwm0/ch/gen_force.rs
@@ -71,37 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GEN_FORCE")
-            .field(
-                "cntuforce_upmethod",
-                &format_args!("{}", self.cntuforce_upmethod().bits()),
-            )
-            .field(
-                "a_cntuforce_mode",
-                &format_args!("{}", self.a_cntuforce_mode().bits()),
-            )
-            .field(
-                "b_cntuforce_mode",
-                &format_args!("{}", self.b_cntuforce_mode().bits()),
-            )
-            .field("a_nciforce", &format_args!("{}", self.a_nciforce().bit()))
-            .field(
-                "a_nciforce_mode",
-                &format_args!("{}", self.a_nciforce_mode().bits()),
-            )
-            .field("b_nciforce", &format_args!("{}", self.b_nciforce().bit()))
-            .field(
-                "b_nciforce_mode",
-                &format_args!("{}", self.b_nciforce_mode().bits()),
-            )
+            .field("cntuforce_upmethod", &self.cntuforce_upmethod())
+            .field("a_cntuforce_mode", &self.a_cntuforce_mode())
+            .field("b_cntuforce_mode", &self.b_cntuforce_mode())
+            .field("a_nciforce", &self.a_nciforce())
+            .field("a_nciforce_mode", &self.a_nciforce_mode())
+            .field("b_nciforce", &self.b_nciforce())
+            .field("b_nciforce_mode", &self.b_nciforce_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GEN_FORCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/ch/tz_cfg0.rs b/esp32s3/src/mcpwm0/ch/tz_cfg0.rs
index a59da6ee5b..3f12b79047 100644
--- a/esp32s3/src/mcpwm0/ch/tz_cfg0.rs
+++ b/esp32s3/src/mcpwm0/ch/tz_cfg0.rs
@@ -152,31 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TZ_CFG0")
-            .field("sw_cbc", &format_args!("{}", self.sw_cbc().bit()))
-            .field("f2_cbc", &format_args!("{}", self.f2_cbc().bit()))
-            .field("f1_cbc", &format_args!("{}", self.f1_cbc().bit()))
-            .field("f0_cbc", &format_args!("{}", self.f0_cbc().bit()))
-            .field("sw_ost", &format_args!("{}", self.sw_ost().bit()))
-            .field("f2_ost", &format_args!("{}", self.f2_ost().bit()))
-            .field("f1_ost", &format_args!("{}", self.f1_ost().bit()))
-            .field("f0_ost", &format_args!("{}", self.f0_ost().bit()))
-            .field("a_cbc_d", &format_args!("{}", self.a_cbc_d().bits()))
-            .field("a_cbc_u", &format_args!("{}", self.a_cbc_u().bits()))
-            .field("a_ost_d", &format_args!("{}", self.a_ost_d().bits()))
-            .field("a_ost_u", &format_args!("{}", self.a_ost_u().bits()))
-            .field("b_cbc_d", &format_args!("{}", self.b_cbc_d().bits()))
-            .field("b_cbc_u", &format_args!("{}", self.b_cbc_u().bits()))
-            .field("b_ost_d", &format_args!("{}", self.b_ost_d().bits()))
-            .field("b_ost_u", &format_args!("{}", self.b_ost_u().bits()))
+            .field("sw_cbc", &self.sw_cbc())
+            .field("f2_cbc", &self.f2_cbc())
+            .field("f1_cbc", &self.f1_cbc())
+            .field("f0_cbc", &self.f0_cbc())
+            .field("sw_ost", &self.sw_ost())
+            .field("f2_ost", &self.f2_ost())
+            .field("f1_ost", &self.f1_ost())
+            .field("f0_ost", &self.f0_ost())
+            .field("a_cbc_d", &self.a_cbc_d())
+            .field("a_cbc_u", &self.a_cbc_u())
+            .field("a_ost_d", &self.a_ost_d())
+            .field("a_ost_u", &self.a_ost_u())
+            .field("b_cbc_d", &self.b_cbc_d())
+            .field("b_cbc_u", &self.b_cbc_u())
+            .field("b_ost_d", &self.b_ost_d())
+            .field("b_ost_u", &self.b_ost_u())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TZ_CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/ch/tz_cfg1.rs b/esp32s3/src/mcpwm0/ch/tz_cfg1.rs
index d6f7a787d1..d167d96222 100644
--- a/esp32s3/src/mcpwm0/ch/tz_cfg1.rs
+++ b/esp32s3/src/mcpwm0/ch/tz_cfg1.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TZ_CFG1")
-            .field("clr_ost", &format_args!("{}", self.clr_ost().bit()))
-            .field("cbcpulse", &format_args!("{}", self.cbcpulse().bits()))
-            .field("force_cbc", &format_args!("{}", self.force_cbc().bit()))
-            .field("force_ost", &format_args!("{}", self.force_ost().bit()))
+            .field("clr_ost", &self.clr_ost())
+            .field("cbcpulse", &self.cbcpulse())
+            .field("force_cbc", &self.force_cbc())
+            .field("force_ost", &self.force_ost())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TZ_CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - a rising edge will clear on going one-shot mode action"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/ch/tz_status.rs b/esp32s3/src/mcpwm0/ch/tz_status.rs
index c628beabda..9ffad64fac 100644
--- a/esp32s3/src/mcpwm0/ch/tz_status.rs
+++ b/esp32s3/src/mcpwm0/ch/tz_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TZ_STATUS")
-            .field("cbc_on", &format_args!("{}", self.cbc_on().bit()))
-            .field("ost_on", &format_args!("{}", self.ost_on().bit()))
+            .field("cbc_on", &self.cbc_on())
+            .field("ost_on", &self.ost_on())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TZ_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status of fault events.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tz_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TZ_STATUS_SPEC;
 impl crate::RegisterSpec for TZ_STATUS_SPEC {
diff --git a/esp32s3/src/mcpwm0/clk.rs b/esp32s3/src/mcpwm0/clk.rs
index 806dbb6cad..6df7d05643 100644
--- a/esp32s3/src/mcpwm0/clk.rs
+++ b/esp32s3/src/mcpwm0/clk.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("CLK")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("CLK").field("en", &self.en()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/mcpwm0/clk_cfg.rs b/esp32s3/src/mcpwm0/clk_cfg.rs
index 387991fe50..dfca5315ac 100644
--- a/esp32s3/src/mcpwm0/clk_cfg.rs
+++ b/esp32s3/src/mcpwm0/clk_cfg.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CFG")
-            .field(
-                "clk_prescale",
-                &format_args!("{}", self.clk_prescale().bits()),
-            )
+            .field("clk_prescale", &self.clk_prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/fault_detect.rs b/esp32s3/src/mcpwm0/fault_detect.rs
index 52af954abd..1b5edb56d6 100644
--- a/esp32s3/src/mcpwm0/fault_detect.rs
+++ b/esp32s3/src/mcpwm0/fault_detect.rs
@@ -83,24 +83,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FAULT_DETECT")
-            .field("f0_en", &format_args!("{}", self.f0_en().bit()))
-            .field("f1_en", &format_args!("{}", self.f1_en().bit()))
-            .field("f2_en", &format_args!("{}", self.f2_en().bit()))
-            .field("f0_pole", &format_args!("{}", self.f0_pole().bit()))
-            .field("f1_pole", &format_args!("{}", self.f1_pole().bit()))
-            .field("f2_pole", &format_args!("{}", self.f2_pole().bit()))
-            .field("event_f0", &format_args!("{}", self.event_f0().bit()))
-            .field("event_f1", &format_args!("{}", self.event_f1().bit()))
-            .field("event_f2", &format_args!("{}", self.event_f2().bit()))
+            .field("f0_en", &self.f0_en())
+            .field("f1_en", &self.f1_en())
+            .field("f2_en", &self.f2_en())
+            .field("f0_pole", &self.f0_pole())
+            .field("f1_pole", &self.f1_pole())
+            .field("f2_pole", &self.f2_pole())
+            .field("event_f0", &self.event_f0())
+            .field("event_f1", &self.event_f1())
+            .field("event_f2", &self.event_f2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FAULT_DETECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, event_f0 generation is enabled"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/int_ena.rs b/esp32s3/src/mcpwm0/int_ena.rs
index 529d6f4a20..dab6312c95 100644
--- a/esp32s3/src/mcpwm0/int_ena.rs
+++ b/esp32s3/src/mcpwm0/int_ena.rs
@@ -278,45 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("fault0", &format_args!("{}", self.fault0().bit()))
-            .field("fault1", &format_args!("{}", self.fault1().bit()))
-            .field("fault2", &format_args!("{}", self.fault2().bit()))
-            .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
-            .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
-            .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
-            .field("cmpr0_tea", &format_args!("{}", self.cmpr0_tea().bit()))
-            .field("cmpr1_tea", &format_args!("{}", self.cmpr1_tea().bit()))
-            .field("cmpr2_tea", &format_args!("{}", self.cmpr2_tea().bit()))
-            .field("cmpr0_teb", &format_args!("{}", self.cmpr0_teb().bit()))
-            .field("cmpr1_teb", &format_args!("{}", self.cmpr1_teb().bit()))
-            .field("cmpr2_teb", &format_args!("{}", self.cmpr2_teb().bit()))
-            .field("tz0_cbc", &format_args!("{}", self.tz0_cbc().bit()))
-            .field("tz1_cbc", &format_args!("{}", self.tz1_cbc().bit()))
-            .field("tz2_cbc", &format_args!("{}", self.tz2_cbc().bit()))
-            .field("tz0_ost", &format_args!("{}", self.tz0_ost().bit()))
-            .field("tz1_ost", &format_args!("{}", self.tz1_ost().bit()))
-            .field("tz2_ost", &format_args!("{}", self.tz2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for the interrupt triggered when the timer 0 stops."]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/int_raw.rs b/esp32s3/src/mcpwm0/int_raw.rs
index b45523dcdc..447b1d86a2 100644
--- a/esp32s3/src/mcpwm0/int_raw.rs
+++ b/esp32s3/src/mcpwm0/int_raw.rs
@@ -278,45 +278,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("fault0", &format_args!("{}", self.fault0().bit()))
-            .field("fault1", &format_args!("{}", self.fault1().bit()))
-            .field("fault2", &format_args!("{}", self.fault2().bit()))
-            .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
-            .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
-            .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
-            .field("cmpr0_tea", &format_args!("{}", self.cmpr0_tea().bit()))
-            .field("cmpr1_tea", &format_args!("{}", self.cmpr1_tea().bit()))
-            .field("cmpr2_tea", &format_args!("{}", self.cmpr2_tea().bit()))
-            .field("cmpr0_teb", &format_args!("{}", self.cmpr0_teb().bit()))
-            .field("cmpr1_teb", &format_args!("{}", self.cmpr1_teb().bit()))
-            .field("cmpr2_teb", &format_args!("{}", self.cmpr2_teb().bit()))
-            .field("tz0_cbc", &format_args!("{}", self.tz0_cbc().bit()))
-            .field("tz1_cbc", &format_args!("{}", self.tz1_cbc().bit()))
-            .field("tz2_cbc", &format_args!("{}", self.tz2_cbc().bit()))
-            .field("tz0_ost", &format_args!("{}", self.tz0_ost().bit()))
-            .field("tz1_ost", &format_args!("{}", self.tz1_ost().bit()))
-            .field("tz2_ost", &format_args!("{}", self.tz2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw status bit for the interrupt triggered when the timer 0 stops."]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/int_st.rs b/esp32s3/src/mcpwm0/int_st.rs
index 8627093497..dff68bd8dd 100644
--- a/esp32s3/src/mcpwm0/int_st.rs
+++ b/esp32s3/src/mcpwm0/int_st.rs
@@ -216,45 +216,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("timer0_stop", &format_args!("{}", self.timer0_stop().bit()))
-            .field("timer1_stop", &format_args!("{}", self.timer1_stop().bit()))
-            .field("timer2_stop", &format_args!("{}", self.timer2_stop().bit()))
-            .field("timer0_tez", &format_args!("{}", self.timer0_tez().bit()))
-            .field("timer1_tez", &format_args!("{}", self.timer1_tez().bit()))
-            .field("timer2_tez", &format_args!("{}", self.timer2_tez().bit()))
-            .field("timer0_tep", &format_args!("{}", self.timer0_tep().bit()))
-            .field("timer1_tep", &format_args!("{}", self.timer1_tep().bit()))
-            .field("timer2_tep", &format_args!("{}", self.timer2_tep().bit()))
-            .field("fault0", &format_args!("{}", self.fault0().bit()))
-            .field("fault1", &format_args!("{}", self.fault1().bit()))
-            .field("fault2", &format_args!("{}", self.fault2().bit()))
-            .field("fault0_clr", &format_args!("{}", self.fault0_clr().bit()))
-            .field("fault1_clr", &format_args!("{}", self.fault1_clr().bit()))
-            .field("fault2_clr", &format_args!("{}", self.fault2_clr().bit()))
-            .field("cmpr0_tea", &format_args!("{}", self.cmpr0_tea().bit()))
-            .field("cmpr1_tea", &format_args!("{}", self.cmpr1_tea().bit()))
-            .field("cmpr2_tea", &format_args!("{}", self.cmpr2_tea().bit()))
-            .field("cmpr0_teb", &format_args!("{}", self.cmpr0_teb().bit()))
-            .field("cmpr1_teb", &format_args!("{}", self.cmpr1_teb().bit()))
-            .field("cmpr2_teb", &format_args!("{}", self.cmpr2_teb().bit()))
-            .field("tz0_cbc", &format_args!("{}", self.tz0_cbc().bit()))
-            .field("tz1_cbc", &format_args!("{}", self.tz1_cbc().bit()))
-            .field("tz2_cbc", &format_args!("{}", self.tz2_cbc().bit()))
-            .field("tz0_ost", &format_args!("{}", self.tz0_ost().bit()))
-            .field("tz1_ost", &format_args!("{}", self.tz1_ost().bit()))
-            .field("tz2_ost", &format_args!("{}", self.tz2_ost().bit()))
-            .field("cap0", &format_args!("{}", self.cap0().bit()))
-            .field("cap1", &format_args!("{}", self.cap1().bit()))
-            .field("cap2", &format_args!("{}", self.cap2().bit()))
+            .field("timer0_stop", &self.timer0_stop())
+            .field("timer1_stop", &self.timer1_stop())
+            .field("timer2_stop", &self.timer2_stop())
+            .field("timer0_tez", &self.timer0_tez())
+            .field("timer1_tez", &self.timer1_tez())
+            .field("timer2_tez", &self.timer2_tez())
+            .field("timer0_tep", &self.timer0_tep())
+            .field("timer1_tep", &self.timer1_tep())
+            .field("timer2_tep", &self.timer2_tep())
+            .field("fault0", &self.fault0())
+            .field("fault1", &self.fault1())
+            .field("fault2", &self.fault2())
+            .field("fault0_clr", &self.fault0_clr())
+            .field("fault1_clr", &self.fault1_clr())
+            .field("fault2_clr", &self.fault2_clr())
+            .field("cmpr0_tea", &self.cmpr0_tea())
+            .field("cmpr1_tea", &self.cmpr1_tea())
+            .field("cmpr2_tea", &self.cmpr2_tea())
+            .field("cmpr0_teb", &self.cmpr0_teb())
+            .field("cmpr1_teb", &self.cmpr1_teb())
+            .field("cmpr2_teb", &self.cmpr2_teb())
+            .field("tz0_cbc", &self.tz0_cbc())
+            .field("tz1_cbc", &self.tz1_cbc())
+            .field("tz2_cbc", &self.tz2_cbc())
+            .field("tz0_ost", &self.tz0_ost())
+            .field("tz1_ost", &self.tz1_ost())
+            .field("tz2_ost", &self.tz2_ost())
+            .field("cap0", &self.cap0())
+            .field("cap1", &self.cap1())
+            .field("cap2", &self.cap2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/mcpwm0/operator_timersel.rs b/esp32s3/src/mcpwm0/operator_timersel.rs
index a9fa9acb15..55e9d23758 100644
--- a/esp32s3/src/mcpwm0/operator_timersel.rs
+++ b/esp32s3/src/mcpwm0/operator_timersel.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OPERATOR_TIMERSEL")
-            .field(
-                "operator0_timersel",
-                &format_args!("{}", self.operator0_timersel().bits()),
-            )
-            .field(
-                "operator1_timersel",
-                &format_args!("{}", self.operator1_timersel().bits()),
-            )
-            .field(
-                "operator2_timersel",
-                &format_args!("{}", self.operator2_timersel().bits()),
-            )
+            .field("operator0_timersel", &self.operator0_timersel())
+            .field("operator1_timersel", &self.operator1_timersel())
+            .field("operator2_timersel", &self.operator2_timersel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OPERATOR_TIMERSEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/timer/cfg0.rs b/esp32s3/src/mcpwm0/timer/cfg0.rs
index 904a515549..9fb25841a5 100644
--- a/esp32s3/src/mcpwm0/timer/cfg0.rs
+++ b/esp32s3/src/mcpwm0/timer/cfg0.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG0")
-            .field("prescale", &format_args!("{}", self.prescale().bits()))
-            .field("period", &format_args!("{}", self.period().bits()))
-            .field(
-                "period_upmethod",
-                &format_args!("{}", self.period_upmethod().bits()),
-            )
+            .field("prescale", &self.prescale())
+            .field("period", &self.period())
+            .field("period_upmethod", &self.period_upmethod())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/timer/cfg1.rs b/esp32s3/src/mcpwm0/timer/cfg1.rs
index 086070d09e..92bed8f96a 100644
--- a/esp32s3/src/mcpwm0/timer/cfg1.rs
+++ b/esp32s3/src/mcpwm0/timer/cfg1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CFG1")
-            .field("start", &format_args!("{}", self.start().bits()))
-            .field("mod_", &format_args!("{}", self.mod_().bits()))
+            .field("start", &self.start())
+            .field("mod_", &self.mod_())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/timer/status.rs b/esp32s3/src/mcpwm0/timer/status.rs
index 576e1198f5..5dd843bac9 100644
--- a/esp32s3/src/mcpwm0/timer/status.rs
+++ b/esp32s3/src/mcpwm0/timer/status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("value", &format_args!("{}", self.value().bits()))
-            .field("direction", &format_args!("{}", self.direction().bit()))
+            .field("value", &self.value())
+            .field("direction", &self.direction())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "PWM TIMERx status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32s3/src/mcpwm0/timer/sync.rs b/esp32s3/src/mcpwm0/timer/sync.rs
index 14fcdb6c9e..e427faf696 100644
--- a/esp32s3/src/mcpwm0/timer/sync.rs
+++ b/esp32s3/src/mcpwm0/timer/sync.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYNC")
-            .field("synci_en", &format_args!("{}", self.synci_en().bit()))
-            .field("sw", &format_args!("{}", self.sw().bit()))
-            .field("synco_sel", &format_args!("{}", self.synco_sel().bits()))
-            .field("phase", &format_args!("{}", self.phase().bits()))
-            .field(
-                "phase_direction",
-                &format_args!("{}", self.phase_direction().bit()),
-            )
+            .field("synci_en", &self.synci_en())
+            .field("sw", &self.sw())
+            .field("synco_sel", &self.synco_sel())
+            .field("phase", &self.phase())
+            .field("phase_direction", &self.phase_direction())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYNC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - When set, timer reloading with phase on sync input event is enabled."]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/timer_synci_cfg.rs b/esp32s3/src/mcpwm0/timer_synci_cfg.rs
index e532121427..2f7f399404 100644
--- a/esp32s3/src/mcpwm0/timer_synci_cfg.rs
+++ b/esp32s3/src/mcpwm0/timer_synci_cfg.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER_SYNCI_CFG")
-            .field(
-                "timer0_syncisel",
-                &format_args!("{}", self.timer0_syncisel().bits()),
-            )
-            .field(
-                "timer1_syncisel",
-                &format_args!("{}", self.timer1_syncisel().bits()),
-            )
-            .field(
-                "timer2_syncisel",
-                &format_args!("{}", self.timer2_syncisel().bits()),
-            )
-            .field(
-                "external_synci0_invert",
-                &format_args!("{}", self.external_synci0_invert().bit()),
-            )
-            .field(
-                "external_synci1_invert",
-                &format_args!("{}", self.external_synci1_invert().bit()),
-            )
-            .field(
-                "external_synci2_invert",
-                &format_args!("{}", self.external_synci2_invert().bit()),
-            )
+            .field("timer0_syncisel", &self.timer0_syncisel())
+            .field("timer1_syncisel", &self.timer1_syncisel())
+            .field("timer2_syncisel", &self.timer2_syncisel())
+            .field("external_synci0_invert", &self.external_synci0_invert())
+            .field("external_synci1_invert", &self.external_synci1_invert())
+            .field("external_synci2_invert", &self.external_synci2_invert())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER_SYNCI_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/update_cfg.rs b/esp32s3/src/mcpwm0/update_cfg.rs
index 07aa2a6a04..f5179c7fbc 100644
--- a/esp32s3/src/mcpwm0/update_cfg.rs
+++ b/esp32s3/src/mcpwm0/update_cfg.rs
@@ -80,38 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE_CFG")
-            .field(
-                "global_up_en",
-                &format_args!("{}", self.global_up_en().bit()),
-            )
-            .field(
-                "global_force_up",
-                &format_args!("{}", self.global_force_up().bit()),
-            )
-            .field("op0_up_en", &format_args!("{}", self.op0_up_en().bit()))
-            .field(
-                "op0_force_up",
-                &format_args!("{}", self.op0_force_up().bit()),
-            )
-            .field("op1_up_en", &format_args!("{}", self.op1_up_en().bit()))
-            .field(
-                "op1_force_up",
-                &format_args!("{}", self.op1_force_up().bit()),
-            )
-            .field("op2_up_en", &format_args!("{}", self.op2_up_en().bit()))
-            .field(
-                "op2_force_up",
-                &format_args!("{}", self.op2_force_up().bit()),
-            )
+            .field("global_up_en", &self.global_up_en())
+            .field("global_force_up", &self.global_force_up())
+            .field("op0_up_en", &self.op0_up_en())
+            .field("op0_force_up", &self.op0_force_up())
+            .field("op1_up_en", &self.op1_up_en())
+            .field("op1_force_up", &self.op1_force_up())
+            .field("op2_up_en", &self.op2_up_en())
+            .field("op2_force_up", &self.op2_force_up())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_CFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The global enable of update of all active registers in MCPWM module"]
     #[inline(always)]
diff --git a/esp32s3/src/mcpwm0/version.rs b/esp32s3/src/mcpwm0/version.rs
index 7a35c7518d..b85f365741 100644
--- a/esp32s3/src/mcpwm0/version.rs
+++ b/esp32s3/src/mcpwm0/version.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERSION")
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERSION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Version of this register file"]
     #[inline(always)]
diff --git a/esp32s3/src/pcnt/ctrl.rs b/esp32s3/src/pcnt/ctrl.rs
index 366f491032..5c3a942e13 100644
--- a/esp32s3/src/pcnt/ctrl.rs
+++ b/esp32s3/src/pcnt/ctrl.rs
@@ -95,36 +95,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("cnt_rst_u0", &format_args!("{}", self.cnt_rst_u0().bit()))
-            .field("cnt_rst_u1", &format_args!("{}", self.cnt_rst_u1().bit()))
-            .field("cnt_rst_u2", &format_args!("{}", self.cnt_rst_u2().bit()))
-            .field("cnt_rst_u3", &format_args!("{}", self.cnt_rst_u3().bit()))
-            .field(
-                "cnt_pause_u0",
-                &format_args!("{}", self.cnt_pause_u0().bit()),
-            )
-            .field(
-                "cnt_pause_u1",
-                &format_args!("{}", self.cnt_pause_u1().bit()),
-            )
-            .field(
-                "cnt_pause_u2",
-                &format_args!("{}", self.cnt_pause_u2().bit()),
-            )
-            .field(
-                "cnt_pause_u3",
-                &format_args!("{}", self.cnt_pause_u3().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("cnt_rst_u0", &self.cnt_rst_u0())
+            .field("cnt_rst_u1", &self.cnt_rst_u1())
+            .field("cnt_rst_u2", &self.cnt_rst_u2())
+            .field("cnt_rst_u3", &self.cnt_rst_u3())
+            .field("cnt_pause_u0", &self.cnt_pause_u0())
+            .field("cnt_pause_u1", &self.cnt_pause_u1())
+            .field("cnt_pause_u2", &self.cnt_pause_u2())
+            .field("cnt_pause_u3", &self.cnt_pause_u3())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Set this bit to clear unit(0-3)'s counter."]
     #[doc = ""]
diff --git a/esp32s3/src/pcnt/date.rs b/esp32s3/src/pcnt/date.rs
index daef1d7bcf..5a80a19072 100644
--- a/esp32s3/src/pcnt/date.rs
+++ b/esp32s3/src/pcnt/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/pcnt/int_ena.rs b/esp32s3/src/pcnt/int_ena.rs
index 4423a16c83..7372693fe3 100644
--- a/esp32s3/src/pcnt/int_ena.rs
+++ b/esp32s3/src/pcnt/int_ena.rs
@@ -47,31 +47,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
     #[doc = ""]
diff --git a/esp32s3/src/pcnt/int_raw.rs b/esp32s3/src/pcnt/int_raw.rs
index bd68f6891b..0e4e8347cf 100644
--- a/esp32s3/src/pcnt/int_raw.rs
+++ b/esp32s3/src/pcnt/int_raw.rs
@@ -43,31 +43,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt raw status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s3/src/pcnt/int_st.rs b/esp32s3/src/pcnt/int_st.rs
index d1a59c1bf3..870d7ad253 100644
--- a/esp32s3/src/pcnt/int_st.rs
+++ b/esp32s3/src/pcnt/int_st.rs
@@ -43,31 +43,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "cnt_thr_event_u0",
-                &format_args!("{}", self.cnt_thr_event_u0().bit()),
-            )
-            .field(
-                "cnt_thr_event_u1",
-                &format_args!("{}", self.cnt_thr_event_u1().bit()),
-            )
-            .field(
-                "cnt_thr_event_u2",
-                &format_args!("{}", self.cnt_thr_event_u2().bit()),
-            )
-            .field(
-                "cnt_thr_event_u3",
-                &format_args!("{}", self.cnt_thr_event_u3().bit()),
-            )
+            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
+            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
+            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
+            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/pcnt/u_cnt.rs b/esp32s3/src/pcnt/u_cnt.rs
index 34bef2c06c..7a45c58a0d 100644
--- a/esp32s3/src/pcnt/u_cnt.rs
+++ b/esp32s3/src/pcnt/u_cnt.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("U_CNT")
-            .field("cnt", &format_args!("{}", self.cnt().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("U_CNT").field("cnt", &self.cnt()).finish()
     }
 }
 #[doc = "Counter value for unit %s\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s3/src/pcnt/u_status.rs b/esp32s3/src/pcnt/u_status.rs
index 408d450824..9d516e2c99 100644
--- a/esp32s3/src/pcnt/u_status.rs
+++ b/esp32s3/src/pcnt/u_status.rs
@@ -48,21 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("U_STATUS")
-            .field("zero_mode", &format_args!("{}", self.zero_mode().bits()))
-            .field("thres1", &format_args!("{}", self.thres1().bit()))
-            .field("thres0", &format_args!("{}", self.thres0().bit()))
-            .field("l_lim", &format_args!("{}", self.l_lim().bit()))
-            .field("h_lim", &format_args!("{}", self.h_lim().bit()))
-            .field("zero", &format_args!("{}", self.zero().bit()))
+            .field("zero_mode", &self.zero_mode())
+            .field("thres1", &self.thres1())
+            .field("thres0", &self.thres0())
+            .field("l_lim", &self.l_lim())
+            .field("h_lim", &self.h_lim())
+            .field("zero", &self.zero())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<U_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "PNCT UNIT%s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`u_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct U_STATUS_SPEC;
 impl crate::RegisterSpec for U_STATUS_SPEC {
diff --git a/esp32s3/src/pcnt/unit/conf0.rs b/esp32s3/src/pcnt/unit/conf0.rs
index 7be65a378c..a66e892dfa 100644
--- a/esp32s3/src/pcnt/unit/conf0.rs
+++ b/esp32s3/src/pcnt/unit/conf0.rs
@@ -325,69 +325,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field(
-                "filter_thres",
-                &format_args!("{}", self.filter_thres().bits()),
-            )
-            .field("filter_en", &format_args!("{}", self.filter_en().bit()))
-            .field("thr_zero_en", &format_args!("{}", self.thr_zero_en().bit()))
-            .field(
-                "thr_h_lim_en",
-                &format_args!("{}", self.thr_h_lim_en().bit()),
-            )
-            .field(
-                "thr_l_lim_en",
-                &format_args!("{}", self.thr_l_lim_en().bit()),
-            )
-            .field(
-                "thr_thres0_en",
-                &format_args!("{}", self.thr_thres0_en().bit()),
-            )
-            .field(
-                "thr_thres1_en",
-                &format_args!("{}", self.thr_thres1_en().bit()),
-            )
-            .field(
-                "ch0_neg_mode",
-                &format_args!("{}", self.ch0_neg_mode().bits()),
-            )
-            .field(
-                "ch1_neg_mode",
-                &format_args!("{}", self.ch1_neg_mode().bits()),
-            )
-            .field(
-                "ch0_pos_mode",
-                &format_args!("{}", self.ch0_pos_mode().bits()),
-            )
-            .field(
-                "ch1_pos_mode",
-                &format_args!("{}", self.ch1_pos_mode().bits()),
-            )
-            .field(
-                "ch0_hctrl_mode",
-                &format_args!("{}", self.ch0_hctrl_mode().bits()),
-            )
-            .field(
-                "ch1_hctrl_mode",
-                &format_args!("{}", self.ch1_hctrl_mode().bits()),
-            )
-            .field(
-                "ch0_lctrl_mode",
-                &format_args!("{}", self.ch0_lctrl_mode().bits()),
-            )
-            .field(
-                "ch1_lctrl_mode",
-                &format_args!("{}", self.ch1_lctrl_mode().bits()),
-            )
+            .field("filter_thres", &self.filter_thres())
+            .field("filter_en", &self.filter_en())
+            .field("thr_zero_en", &self.thr_zero_en())
+            .field("thr_h_lim_en", &self.thr_h_lim_en())
+            .field("thr_l_lim_en", &self.thr_l_lim_en())
+            .field("thr_thres0_en", &self.thr_thres0_en())
+            .field("thr_thres1_en", &self.thr_thres1_en())
+            .field("ch0_neg_mode", &self.ch0_neg_mode())
+            .field("ch1_neg_mode", &self.ch1_neg_mode())
+            .field("ch0_pos_mode", &self.ch0_pos_mode())
+            .field("ch1_pos_mode", &self.ch1_pos_mode())
+            .field("ch0_hctrl_mode", &self.ch0_hctrl_mode())
+            .field("ch1_hctrl_mode", &self.ch1_hctrl_mode())
+            .field("ch0_lctrl_mode", &self.ch0_lctrl_mode())
+            .field("ch1_lctrl_mode", &self.ch1_lctrl_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
     #[inline(always)]
diff --git a/esp32s3/src/pcnt/unit/conf1.rs b/esp32s3/src/pcnt/unit/conf1.rs
index 62e92aa446..d516d127e6 100644
--- a/esp32s3/src/pcnt/unit/conf1.rs
+++ b/esp32s3/src/pcnt/unit/conf1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field("cnt_thres0", &format_args!("{}", self.cnt_thres0().bits()))
-            .field("cnt_thres1", &format_args!("{}", self.cnt_thres1().bits()))
+            .field("cnt_thres0", &self.cnt_thres0())
+            .field("cnt_thres1", &self.cnt_thres1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the thres0 value for unit %s."]
     #[inline(always)]
diff --git a/esp32s3/src/pcnt/unit/conf2.rs b/esp32s3/src/pcnt/unit/conf2.rs
index 85e906ae09..25118d3c9c 100644
--- a/esp32s3/src/pcnt/unit/conf2.rs
+++ b/esp32s3/src/pcnt/unit/conf2.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF2")
-            .field("cnt_h_lim", &format_args!("{}", self.cnt_h_lim().bits()))
-            .field("cnt_l_lim", &format_args!("{}", self.cnt_l_lim().bits()))
+            .field("cnt_h_lim", &self.cnt_h_lim())
+            .field("cnt_l_lim", &self.cnt_l_lim())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the thr_h_lim value for unit %s."]
     #[inline(always)]
diff --git a/esp32s3/src/peri_backup/apb_addr.rs b/esp32s3/src/peri_backup/apb_addr.rs
index bb45b9d650..074ad5e854 100644
--- a/esp32s3/src/peri_backup/apb_addr.rs
+++ b/esp32s3/src/peri_backup/apb_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("APB_ADDR")
-            .field(
-                "apb_start_addr",
-                &format_args!("{}", self.apb_start_addr().bits()),
-            )
+            .field("apb_start_addr", &self.apb_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - x"]
     #[inline(always)]
diff --git a/esp32s3/src/peri_backup/config.rs b/esp32s3/src/peri_backup/config.rs
index fa277f5f1d..37a4f582e6 100644
--- a/esp32s3/src/peri_backup/config.rs
+++ b/esp32s3/src/peri_backup/config.rs
@@ -71,28 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG")
-            .field("flow_err", &format_args!("{}", self.flow_err().bits()))
-            .field(
-                "addr_map_mode",
-                &format_args!("{}", self.addr_map_mode().bit()),
-            )
-            .field(
-                "burst_limit",
-                &format_args!("{}", self.burst_limit().bits()),
-            )
-            .field("tout_thres", &format_args!("{}", self.tout_thres().bits()))
-            .field("size", &format_args!("{}", self.size().bits()))
-            .field("to_mem", &format_args!("{}", self.to_mem().bit()))
-            .field("ena", &format_args!("{}", self.ena().bit()))
+            .field("flow_err", &self.flow_err())
+            .field("addr_map_mode", &self.addr_map_mode())
+            .field("burst_limit", &self.burst_limit())
+            .field("tout_thres", &self.tout_thres())
+            .field("size", &self.size())
+            .field("to_mem", &self.to_mem())
+            .field("ena", &self.ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - x"]
     #[inline(always)]
diff --git a/esp32s3/src/peri_backup/date.rs b/esp32s3/src/peri_backup/date.rs
index 8af1347be8..c6bac50803 100644
--- a/esp32s3/src/peri_backup/date.rs
+++ b/esp32s3/src/peri_backup/date.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("date", &self.date())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - x"]
     #[inline(always)]
diff --git a/esp32s3/src/peri_backup/int_ena.rs b/esp32s3/src/peri_backup/int_ena.rs
index 6146f19b23..0ba11d3812 100644
--- a/esp32s3/src/peri_backup/int_ena.rs
+++ b/esp32s3/src/peri_backup/int_ena.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("err", &format_args!("{}", self.err().bit()))
+            .field("done", &self.done())
+            .field("err", &self.err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - x"]
     #[inline(always)]
diff --git a/esp32s3/src/peri_backup/int_raw.rs b/esp32s3/src/peri_backup/int_raw.rs
index abb1c286ec..3fdb380751 100644
--- a/esp32s3/src/peri_backup/int_raw.rs
+++ b/esp32s3/src/peri_backup/int_raw.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("err", &format_args!("{}", self.err().bit()))
+            .field("done", &self.done())
+            .field("err", &self.err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s3/src/peri_backup/int_st.rs b/esp32s3/src/peri_backup/int_st.rs
index 2e8e2e2efa..057a8cbcab 100644
--- a/esp32s3/src/peri_backup/int_st.rs
+++ b/esp32s3/src/peri_backup/int_st.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("done", &format_args!("{}", self.done().bit()))
-            .field("err", &format_args!("{}", self.err().bit()))
+            .field("done", &self.done())
+            .field("err", &self.err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "x\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/peri_backup/mem_addr.rs b/esp32s3/src/peri_backup/mem_addr.rs
index 5652b515d2..3f7f5159d8 100644
--- a/esp32s3/src/peri_backup/mem_addr.rs
+++ b/esp32s3/src/peri_backup/mem_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_ADDR")
-            .field(
-                "mem_start_addr",
-                &format_args!("{}", self.mem_start_addr().bits()),
-            )
+            .field("mem_start_addr", &self.mem_start_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - x"]
     #[inline(always)]
diff --git a/esp32s3/src/peri_backup/reg_map0.rs b/esp32s3/src/peri_backup/reg_map0.rs
index c9032fdf10..8ec8c54faa 100644
--- a/esp32s3/src/peri_backup/reg_map0.rs
+++ b/esp32s3/src/peri_backup/reg_map0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_MAP0")
-            .field("map0", &format_args!("{}", self.map0().bits()))
+            .field("map0", &self.map0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_MAP0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - x"]
     #[inline(always)]
diff --git a/esp32s3/src/peri_backup/reg_map1.rs b/esp32s3/src/peri_backup/reg_map1.rs
index 3ce54d8408..fc31e12c60 100644
--- a/esp32s3/src/peri_backup/reg_map1.rs
+++ b/esp32s3/src/peri_backup/reg_map1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_MAP1")
-            .field("map1", &format_args!("{}", self.map1().bits()))
+            .field("map1", &self.map1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_MAP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - x"]
     #[inline(always)]
diff --git a/esp32s3/src/peri_backup/reg_map2.rs b/esp32s3/src/peri_backup/reg_map2.rs
index 59e7e7e9b2..d2dc67de43 100644
--- a/esp32s3/src/peri_backup/reg_map2.rs
+++ b/esp32s3/src/peri_backup/reg_map2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_MAP2")
-            .field("map2", &format_args!("{}", self.map2().bits()))
+            .field("map2", &self.map2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_MAP2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - x"]
     #[inline(always)]
diff --git a/esp32s3/src/peri_backup/reg_map3.rs b/esp32s3/src/peri_backup/reg_map3.rs
index ab5c588455..ce901ac784 100644
--- a/esp32s3/src/peri_backup/reg_map3.rs
+++ b/esp32s3/src/peri_backup/reg_map3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REG_MAP3")
-            .field("map3", &format_args!("{}", self.map3().bits()))
+            .field("map3", &self.map3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REG_MAP3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - x"]
     #[inline(always)]
diff --git a/esp32s3/src/rmt/ch_rx_carrier_rm.rs b/esp32s3/src/rmt/ch_rx_carrier_rm.rs
index 110fc179a3..d55c19dbf1 100644
--- a/esp32s3/src/rmt/ch_rx_carrier_rm.rs
+++ b/esp32s3/src/rmt/ch_rx_carrier_rm.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_CARRIER_RM")
-            .field(
-                "carrier_low_thres",
-                &format_args!("{}", self.carrier_low_thres().bits()),
-            )
-            .field(
-                "carrier_high_thres",
-                &format_args!("{}", self.carrier_high_thres().bits()),
-            )
+            .field("carrier_low_thres", &self.carrier_low_thres())
+            .field("carrier_high_thres", &self.carrier_high_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_CARRIER_RM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s."]
     #[inline(always)]
diff --git a/esp32s3/src/rmt/ch_rx_conf0.rs b/esp32s3/src/rmt/ch_rx_conf0.rs
index a32ce0d8eb..b92a3327e2 100644
--- a/esp32s3/src/rmt/ch_rx_conf0.rs
+++ b/esp32s3/src/rmt/ch_rx_conf0.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_CONF0")
-            .field("div_cnt", &format_args!("{}", self.div_cnt().bits()))
-            .field("idle_thres", &format_args!("{}", self.idle_thres().bits()))
-            .field("mem_size", &format_args!("{}", self.mem_size().bits()))
-            .field("carrier_en", &format_args!("{}", self.carrier_en().bit()))
-            .field(
-                "carrier_out_lv",
-                &format_args!("{}", self.carrier_out_lv().bit()),
-            )
+            .field("div_cnt", &self.div_cnt())
+            .field("idle_thres", &self.idle_thres())
+            .field("mem_size", &self.mem_size())
+            .field("carrier_en", &self.carrier_en())
+            .field("carrier_out_lv", &self.carrier_out_lv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the divider for clock of CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32s3/src/rmt/ch_rx_conf1.rs b/esp32s3/src/rmt/ch_rx_conf1.rs
index 4d32c964bc..7e8199c2e3 100644
--- a/esp32s3/src/rmt/ch_rx_conf1.rs
+++ b/esp32s3/src/rmt/ch_rx_conf1.rs
@@ -61,29 +61,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_CONF1")
-            .field("rx_en", &format_args!("{}", self.rx_en().bit()))
-            .field("mem_owner", &format_args!("{}", self.mem_owner().bit()))
-            .field(
-                "rx_filter_en",
-                &format_args!("{}", self.rx_filter_en().bit()),
-            )
-            .field(
-                "rx_filter_thres",
-                &format_args!("{}", self.rx_filter_thres().bits()),
-            )
-            .field(
-                "mem_rx_wrap_en",
-                &format_args!("{}", self.mem_rx_wrap_en().bit()),
-            )
+            .field("rx_en", &self.rx_en())
+            .field("mem_owner", &self.mem_owner())
+            .field("rx_filter_en", &self.rx_filter_en())
+            .field("rx_filter_thres", &self.rx_filter_thres())
+            .field("mem_rx_wrap_en", &self.mem_rx_wrap_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable receiver to receive data on CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32s3/src/rmt/ch_rx_lim.rs b/esp32s3/src/rmt/ch_rx_lim.rs
index fd3a9b693d..0fb7824427 100644
--- a/esp32s3/src/rmt/ch_rx_lim.rs
+++ b/esp32s3/src/rmt/ch_rx_lim.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_LIM")
-            .field("rx_lim", &format_args!("{}", self.rx_lim().bits()))
+            .field("rx_lim", &self.rx_lim())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_LIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can receive."]
     #[inline(always)]
diff --git a/esp32s3/src/rmt/ch_rx_status.rs b/esp32s3/src/rmt/ch_rx_status.rs
index 37e66d128f..b47348817b 100644
--- a/esp32s3/src/rmt/ch_rx_status.rs
+++ b/esp32s3/src/rmt/ch_rx_status.rs
@@ -48,33 +48,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_RX_STATUS")
-            .field(
-                "mem_waddr_ex",
-                &format_args!("{}", self.mem_waddr_ex().bits()),
-            )
-            .field(
-                "apb_mem_raddr",
-                &format_args!("{}", self.apb_mem_raddr().bits()),
-            )
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field(
-                "mem_owner_err",
-                &format_args!("{}", self.mem_owner_err().bit()),
-            )
-            .field("mem_full", &format_args!("{}", self.mem_full().bit()))
-            .field(
-                "apb_mem_rd_err",
-                &format_args!("{}", self.apb_mem_rd_err().bit()),
-            )
+            .field("mem_waddr_ex", &self.mem_waddr_ex())
+            .field("apb_mem_raddr", &self.apb_mem_raddr())
+            .field("state", &self.state())
+            .field("mem_owner_err", &self.mem_owner_err())
+            .field("mem_full", &self.mem_full())
+            .field("apb_mem_rd_err", &self.apb_mem_rd_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Channel %s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_RX_STATUS_SPEC;
 impl crate::RegisterSpec for CH_RX_STATUS_SPEC {
diff --git a/esp32s3/src/rmt/ch_tx_conf0.rs b/esp32s3/src/rmt/ch_tx_conf0.rs
index 77a768e9ed..4675d86247 100644
--- a/esp32s3/src/rmt/ch_tx_conf0.rs
+++ b/esp32s3/src/rmt/ch_tx_conf0.rs
@@ -108,37 +108,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_TX_CONF0")
-            .field(
-                "tx_conti_mode",
-                &format_args!("{}", self.tx_conti_mode().bit()),
-            )
-            .field(
-                "mem_tx_wrap_en",
-                &format_args!("{}", self.mem_tx_wrap_en().bit()),
-            )
-            .field("idle_out_lv", &format_args!("{}", self.idle_out_lv().bit()))
-            .field("idle_out_en", &format_args!("{}", self.idle_out_en().bit()))
-            .field("tx_stop", &format_args!("{}", self.tx_stop().bit()))
-            .field("div_cnt", &format_args!("{}", self.div_cnt().bits()))
-            .field("mem_size", &format_args!("{}", self.mem_size().bits()))
-            .field(
-                "carrier_eff_en",
-                &format_args!("{}", self.carrier_eff_en().bit()),
-            )
-            .field("carrier_en", &format_args!("{}", self.carrier_en().bit()))
-            .field(
-                "carrier_out_lv",
-                &format_args!("{}", self.carrier_out_lv().bit()),
-            )
+            .field("tx_conti_mode", &self.tx_conti_mode())
+            .field("mem_tx_wrap_en", &self.mem_tx_wrap_en())
+            .field("idle_out_lv", &self.idle_out_lv())
+            .field("idle_out_en", &self.idle_out_en())
+            .field("tx_stop", &self.tx_stop())
+            .field("div_cnt", &self.div_cnt())
+            .field("mem_size", &self.mem_size())
+            .field("carrier_eff_en", &self.carrier_eff_en())
+            .field("carrier_en", &self.carrier_en())
+            .field("carrier_out_lv", &self.carrier_out_lv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_TX_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to start sending data on CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32s3/src/rmt/ch_tx_lim.rs b/esp32s3/src/rmt/ch_tx_lim.rs
index 8102018dc9..774de58471 100644
--- a/esp32s3/src/rmt/ch_tx_lim.rs
+++ b/esp32s3/src/rmt/ch_tx_lim.rs
@@ -46,28 +46,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_TX_LIM")
-            .field("tx_lim", &format_args!("{}", self.tx_lim().bits()))
-            .field(
-                "tx_loop_num",
-                &format_args!("{}", self.tx_loop_num().bits()),
-            )
-            .field(
-                "tx_loop_cnt_en",
-                &format_args!("{}", self.tx_loop_cnt_en().bit()),
-            )
-            .field(
-                "loop_stop_en",
-                &format_args!("{}", self.loop_stop_en().bit()),
-            )
+            .field("tx_lim", &self.tx_lim())
+            .field("tx_loop_num", &self.tx_loop_num())
+            .field("tx_loop_cnt_en", &self.tx_loop_cnt_en())
+            .field("loop_stop_en", &self.loop_stop_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_TX_LIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - This register is used to configure the maximum entries that CHANNEL%s can send out."]
     #[inline(always)]
diff --git a/esp32s3/src/rmt/ch_tx_status.rs b/esp32s3/src/rmt/ch_tx_status.rs
index 0a26901d7a..7d158d1749 100644
--- a/esp32s3/src/rmt/ch_tx_status.rs
+++ b/esp32s3/src/rmt/ch_tx_status.rs
@@ -41,29 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CH_TX_STATUS")
-            .field(
-                "mem_raddr_ex",
-                &format_args!("{}", self.mem_raddr_ex().bits()),
-            )
-            .field(
-                "apb_mem_waddr",
-                &format_args!("{}", self.apb_mem_waddr().bits()),
-            )
-            .field("state", &format_args!("{}", self.state().bits()))
-            .field("mem_empty", &format_args!("{}", self.mem_empty().bit()))
-            .field(
-                "apb_mem_wr_err",
-                &format_args!("{}", self.apb_mem_wr_err().bit()),
-            )
+            .field("mem_raddr_ex", &self.mem_raddr_ex())
+            .field("apb_mem_waddr", &self.apb_mem_waddr())
+            .field("state", &self.state())
+            .field("mem_empty", &self.mem_empty())
+            .field("apb_mem_wr_err", &self.apb_mem_wr_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CH_TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Channel %s status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CH_TX_STATUS_SPEC;
 impl crate::RegisterSpec for CH_TX_STATUS_SPEC {
diff --git a/esp32s3/src/rmt/chcarrier_duty.rs b/esp32s3/src/rmt/chcarrier_duty.rs
index a3f3981bc9..ffed06d8c2 100644
--- a/esp32s3/src/rmt/chcarrier_duty.rs
+++ b/esp32s3/src/rmt/chcarrier_duty.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHCARRIER_DUTY")
-            .field(
-                "carrier_low",
-                &format_args!("{}", self.carrier_low().bits()),
-            )
-            .field(
-                "carrier_high",
-                &format_args!("{}", self.carrier_high().bits()),
-            )
+            .field("carrier_low", &self.carrier_low())
+            .field("carrier_high", &self.carrier_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHCARRIER_DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure carrier wave 's low level clock period for CHANNEL%s."]
     #[inline(always)]
diff --git a/esp32s3/src/rmt/chdata.rs b/esp32s3/src/rmt/chdata.rs
index 8efd5cd2c1..5e6da546a9 100644
--- a/esp32s3/src/rmt/chdata.rs
+++ b/esp32s3/src/rmt/chdata.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHDATA")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHDATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Read and write data for channel %s via APB FIFO."]
     #[inline(always)]
diff --git a/esp32s3/src/rmt/date.rs b/esp32s3/src/rmt/date.rs
index 84b4cf5d2a..c2338423e1 100644
--- a/esp32s3/src/rmt/date.rs
+++ b/esp32s3/src/rmt/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/rmt/int_ena.rs b/esp32s3/src/rmt/int_ena.rs
index 25ca8f6f8f..b4b7aaa6a6 100644
--- a/esp32s3/src/rmt/int_ena.rs
+++ b/esp32s3/src/rmt/int_ena.rs
@@ -299,75 +299,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_tx_end", &format_args!("{}", self.ch2_tx_end().bit()))
-            .field("ch3_tx_end", &format_args!("{}", self.ch3_tx_end().bit()))
-            .field("ch0_tx_err", &format_args!("{}", self.ch0_tx_err().bit()))
-            .field("ch1_tx_err", &format_args!("{}", self.ch1_tx_err().bit()))
-            .field("ch2_tx_err", &format_args!("{}", self.ch2_tx_err().bit()))
-            .field("ch3_tx_err", &format_args!("{}", self.ch3_tx_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_tx_thr_event",
-                &format_args!("{}", self.ch2_tx_thr_event().bit()),
-            )
-            .field(
-                "ch3_tx_thr_event",
-                &format_args!("{}", self.ch3_tx_thr_event().bit()),
-            )
-            .field("ch0_tx_loop", &format_args!("{}", self.ch0_tx_loop().bit()))
-            .field("ch1_tx_loop", &format_args!("{}", self.ch1_tx_loop().bit()))
-            .field("ch2_tx_loop", &format_args!("{}", self.ch2_tx_loop().bit()))
-            .field("ch3_tx_loop", &format_args!("{}", self.ch3_tx_loop().bit()))
-            .field("ch4_rx_end", &format_args!("{}", self.ch4_rx_end().bit()))
-            .field("ch5_rx_end", &format_args!("{}", self.ch5_rx_end().bit()))
-            .field("ch6_rx_end", &format_args!("{}", self.ch6_rx_end().bit()))
-            .field("ch7_rx_end", &format_args!("{}", self.ch7_rx_end().bit()))
-            .field("ch4_rx_err", &format_args!("{}", self.ch4_rx_err().bit()))
-            .field("ch5_rx_err", &format_args!("{}", self.ch5_rx_err().bit()))
-            .field("ch6_rx_err", &format_args!("{}", self.ch6_rx_err().bit()))
-            .field("ch7_rx_err", &format_args!("{}", self.ch7_rx_err().bit()))
-            .field(
-                "ch4_rx_thr_event",
-                &format_args!("{}", self.ch4_rx_thr_event().bit()),
-            )
-            .field(
-                "ch5_rx_thr_event",
-                &format_args!("{}", self.ch5_rx_thr_event().bit()),
-            )
-            .field(
-                "ch6_rx_thr_event",
-                &format_args!("{}", self.ch6_rx_thr_event().bit()),
-            )
-            .field(
-                "ch7_rx_thr_event",
-                &format_args!("{}", self.ch7_rx_thr_event().bit()),
-            )
-            .field(
-                "tx_ch3_dma_access_fail",
-                &format_args!("{}", self.tx_ch3_dma_access_fail().bit()),
-            )
-            .field(
-                "rx_ch7_dma_access_fail",
-                &format_args!("{}", self.rx_ch7_dma_access_fail().bit()),
-            )
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_tx_end", &self.ch2_tx_end())
+            .field("ch3_tx_end", &self.ch3_tx_end())
+            .field("ch0_tx_err", &self.ch0_tx_err())
+            .field("ch1_tx_err", &self.ch1_tx_err())
+            .field("ch2_tx_err", &self.ch2_tx_err())
+            .field("ch3_tx_err", &self.ch3_tx_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_tx_thr_event", &self.ch2_tx_thr_event())
+            .field("ch3_tx_thr_event", &self.ch3_tx_thr_event())
+            .field("ch0_tx_loop", &self.ch0_tx_loop())
+            .field("ch1_tx_loop", &self.ch1_tx_loop())
+            .field("ch2_tx_loop", &self.ch2_tx_loop())
+            .field("ch3_tx_loop", &self.ch3_tx_loop())
+            .field("ch4_rx_end", &self.ch4_rx_end())
+            .field("ch5_rx_end", &self.ch5_rx_end())
+            .field("ch6_rx_end", &self.ch6_rx_end())
+            .field("ch7_rx_end", &self.ch7_rx_end())
+            .field("ch4_rx_err", &self.ch4_rx_err())
+            .field("ch5_rx_err", &self.ch5_rx_err())
+            .field("ch6_rx_err", &self.ch6_rx_err())
+            .field("ch7_rx_err", &self.ch7_rx_err())
+            .field("ch4_rx_thr_event", &self.ch4_rx_thr_event())
+            .field("ch5_rx_thr_event", &self.ch5_rx_thr_event())
+            .field("ch6_rx_thr_event", &self.ch6_rx_thr_event())
+            .field("ch7_rx_thr_event", &self.ch7_rx_thr_event())
+            .field("tx_ch3_dma_access_fail", &self.tx_ch3_dma_access_fail())
+            .field("rx_ch7_dma_access_fail", &self.rx_ch7_dma_access_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for CH(0-3)_TX_END_INT."]
     #[doc = ""]
diff --git a/esp32s3/src/rmt/int_raw.rs b/esp32s3/src/rmt/int_raw.rs
index 230e1ac917..02ae902771 100644
--- a/esp32s3/src/rmt/int_raw.rs
+++ b/esp32s3/src/rmt/int_raw.rs
@@ -299,75 +299,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_tx_end", &format_args!("{}", self.ch2_tx_end().bit()))
-            .field("ch3_tx_end", &format_args!("{}", self.ch3_tx_end().bit()))
-            .field("ch0_tx_err", &format_args!("{}", self.ch0_tx_err().bit()))
-            .field("ch1_tx_err", &format_args!("{}", self.ch1_tx_err().bit()))
-            .field("ch2_tx_err", &format_args!("{}", self.ch2_tx_err().bit()))
-            .field("ch3_tx_err", &format_args!("{}", self.ch3_tx_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_tx_thr_event",
-                &format_args!("{}", self.ch2_tx_thr_event().bit()),
-            )
-            .field(
-                "ch3_tx_thr_event",
-                &format_args!("{}", self.ch3_tx_thr_event().bit()),
-            )
-            .field("ch0_tx_loop", &format_args!("{}", self.ch0_tx_loop().bit()))
-            .field("ch1_tx_loop", &format_args!("{}", self.ch1_tx_loop().bit()))
-            .field("ch2_tx_loop", &format_args!("{}", self.ch2_tx_loop().bit()))
-            .field("ch3_tx_loop", &format_args!("{}", self.ch3_tx_loop().bit()))
-            .field("ch4_rx_end", &format_args!("{}", self.ch4_rx_end().bit()))
-            .field("ch5_rx_end", &format_args!("{}", self.ch5_rx_end().bit()))
-            .field("ch6_rx_end", &format_args!("{}", self.ch6_rx_end().bit()))
-            .field("ch7_rx_end", &format_args!("{}", self.ch7_rx_end().bit()))
-            .field("ch4_rx_err", &format_args!("{}", self.ch4_rx_err().bit()))
-            .field("ch5_rx_err", &format_args!("{}", self.ch5_rx_err().bit()))
-            .field("ch6_rx_err", &format_args!("{}", self.ch6_rx_err().bit()))
-            .field("ch7_rx_err", &format_args!("{}", self.ch7_rx_err().bit()))
-            .field(
-                "ch4_rx_thr_event",
-                &format_args!("{}", self.ch4_rx_thr_event().bit()),
-            )
-            .field(
-                "ch5_rx_thr_event",
-                &format_args!("{}", self.ch5_rx_thr_event().bit()),
-            )
-            .field(
-                "ch6_rx_thr_event",
-                &format_args!("{}", self.ch6_rx_thr_event().bit()),
-            )
-            .field(
-                "ch7_rx_thr_event",
-                &format_args!("{}", self.ch7_rx_thr_event().bit()),
-            )
-            .field(
-                "tx_ch3_dma_access_fail",
-                &format_args!("{}", self.tx_ch3_dma_access_fail().bit()),
-            )
-            .field(
-                "rx_ch7_dma_access_fail",
-                &format_args!("{}", self.rx_ch7_dma_access_fail().bit()),
-            )
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_tx_end", &self.ch2_tx_end())
+            .field("ch3_tx_end", &self.ch3_tx_end())
+            .field("ch0_tx_err", &self.ch0_tx_err())
+            .field("ch1_tx_err", &self.ch1_tx_err())
+            .field("ch2_tx_err", &self.ch2_tx_err())
+            .field("ch3_tx_err", &self.ch3_tx_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_tx_thr_event", &self.ch2_tx_thr_event())
+            .field("ch3_tx_thr_event", &self.ch3_tx_thr_event())
+            .field("ch0_tx_loop", &self.ch0_tx_loop())
+            .field("ch1_tx_loop", &self.ch1_tx_loop())
+            .field("ch2_tx_loop", &self.ch2_tx_loop())
+            .field("ch3_tx_loop", &self.ch3_tx_loop())
+            .field("ch4_rx_end", &self.ch4_rx_end())
+            .field("ch5_rx_end", &self.ch5_rx_end())
+            .field("ch6_rx_end", &self.ch6_rx_end())
+            .field("ch7_rx_end", &self.ch7_rx_end())
+            .field("ch4_rx_err", &self.ch4_rx_err())
+            .field("ch5_rx_err", &self.ch5_rx_err())
+            .field("ch6_rx_err", &self.ch6_rx_err())
+            .field("ch7_rx_err", &self.ch7_rx_err())
+            .field("ch4_rx_thr_event", &self.ch4_rx_thr_event())
+            .field("ch5_rx_thr_event", &self.ch5_rx_thr_event())
+            .field("ch6_rx_thr_event", &self.ch6_rx_thr_event())
+            .field("ch7_rx_thr_event", &self.ch7_rx_thr_event())
+            .field("tx_ch3_dma_access_fail", &self.tx_ch3_dma_access_fail())
+            .field("rx_ch7_dma_access_fail", &self.rx_ch7_dma_access_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt raw bit for CHANNEL(0-3). Triggered when transmission done."]
     #[doc = ""]
diff --git a/esp32s3/src/rmt/int_st.rs b/esp32s3/src/rmt/int_st.rs
index f530e31210..97cdf7e230 100644
--- a/esp32s3/src/rmt/int_st.rs
+++ b/esp32s3/src/rmt/int_st.rs
@@ -279,75 +279,39 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("ch0_tx_end", &format_args!("{}", self.ch0_tx_end().bit()))
-            .field("ch1_tx_end", &format_args!("{}", self.ch1_tx_end().bit()))
-            .field("ch2_tx_end", &format_args!("{}", self.ch2_tx_end().bit()))
-            .field("ch3_tx_end", &format_args!("{}", self.ch3_tx_end().bit()))
-            .field("ch0_tx_err", &format_args!("{}", self.ch0_tx_err().bit()))
-            .field("ch1_tx_err", &format_args!("{}", self.ch1_tx_err().bit()))
-            .field("ch2_tx_err", &format_args!("{}", self.ch2_tx_err().bit()))
-            .field("ch3_tx_err", &format_args!("{}", self.ch3_tx_err().bit()))
-            .field(
-                "ch0_tx_thr_event",
-                &format_args!("{}", self.ch0_tx_thr_event().bit()),
-            )
-            .field(
-                "ch1_tx_thr_event",
-                &format_args!("{}", self.ch1_tx_thr_event().bit()),
-            )
-            .field(
-                "ch2_tx_thr_event",
-                &format_args!("{}", self.ch2_tx_thr_event().bit()),
-            )
-            .field(
-                "ch3_tx_thr_event",
-                &format_args!("{}", self.ch3_tx_thr_event().bit()),
-            )
-            .field("ch0_tx_loop", &format_args!("{}", self.ch0_tx_loop().bit()))
-            .field("ch1_tx_loop", &format_args!("{}", self.ch1_tx_loop().bit()))
-            .field("ch2_tx_loop", &format_args!("{}", self.ch2_tx_loop().bit()))
-            .field("ch3_tx_loop", &format_args!("{}", self.ch3_tx_loop().bit()))
-            .field("ch4_rx_end", &format_args!("{}", self.ch4_rx_end().bit()))
-            .field("ch5_rx_end", &format_args!("{}", self.ch5_rx_end().bit()))
-            .field("ch6_rx_end", &format_args!("{}", self.ch6_rx_end().bit()))
-            .field("ch7_rx_end", &format_args!("{}", self.ch7_rx_end().bit()))
-            .field("ch4_rx_err", &format_args!("{}", self.ch4_rx_err().bit()))
-            .field("ch5_rx_err", &format_args!("{}", self.ch5_rx_err().bit()))
-            .field("ch6_rx_err", &format_args!("{}", self.ch6_rx_err().bit()))
-            .field("ch7_rx_err", &format_args!("{}", self.ch7_rx_err().bit()))
-            .field(
-                "ch4_rx_thr_event",
-                &format_args!("{}", self.ch4_rx_thr_event().bit()),
-            )
-            .field(
-                "ch5_rx_thr_event",
-                &format_args!("{}", self.ch5_rx_thr_event().bit()),
-            )
-            .field(
-                "ch6_rx_thr_event",
-                &format_args!("{}", self.ch6_rx_thr_event().bit()),
-            )
-            .field(
-                "ch7_rx_thr_event",
-                &format_args!("{}", self.ch7_rx_thr_event().bit()),
-            )
-            .field(
-                "tx_ch3_dma_access_fail",
-                &format_args!("{}", self.tx_ch3_dma_access_fail().bit()),
-            )
-            .field(
-                "rx_ch7_dma_access_fail",
-                &format_args!("{}", self.rx_ch7_dma_access_fail().bit()),
-            )
+            .field("ch0_tx_end", &self.ch0_tx_end())
+            .field("ch1_tx_end", &self.ch1_tx_end())
+            .field("ch2_tx_end", &self.ch2_tx_end())
+            .field("ch3_tx_end", &self.ch3_tx_end())
+            .field("ch0_tx_err", &self.ch0_tx_err())
+            .field("ch1_tx_err", &self.ch1_tx_err())
+            .field("ch2_tx_err", &self.ch2_tx_err())
+            .field("ch3_tx_err", &self.ch3_tx_err())
+            .field("ch0_tx_thr_event", &self.ch0_tx_thr_event())
+            .field("ch1_tx_thr_event", &self.ch1_tx_thr_event())
+            .field("ch2_tx_thr_event", &self.ch2_tx_thr_event())
+            .field("ch3_tx_thr_event", &self.ch3_tx_thr_event())
+            .field("ch0_tx_loop", &self.ch0_tx_loop())
+            .field("ch1_tx_loop", &self.ch1_tx_loop())
+            .field("ch2_tx_loop", &self.ch2_tx_loop())
+            .field("ch3_tx_loop", &self.ch3_tx_loop())
+            .field("ch4_rx_end", &self.ch4_rx_end())
+            .field("ch5_rx_end", &self.ch5_rx_end())
+            .field("ch6_rx_end", &self.ch6_rx_end())
+            .field("ch7_rx_end", &self.ch7_rx_end())
+            .field("ch4_rx_err", &self.ch4_rx_err())
+            .field("ch5_rx_err", &self.ch5_rx_err())
+            .field("ch6_rx_err", &self.ch6_rx_err())
+            .field("ch7_rx_err", &self.ch7_rx_err())
+            .field("ch4_rx_thr_event", &self.ch4_rx_thr_event())
+            .field("ch5_rx_thr_event", &self.ch5_rx_thr_event())
+            .field("ch6_rx_thr_event", &self.ch6_rx_thr_event())
+            .field("ch7_rx_thr_event", &self.ch7_rx_thr_event())
+            .field("tx_ch3_dma_access_fail", &self.tx_ch3_dma_access_fail())
+            .field("rx_ch7_dma_access_fail", &self.rx_ch7_dma_access_fail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/rmt/sys_conf.rs b/esp32s3/src/rmt/sys_conf.rs
index 7d498ce405..7d088da5cc 100644
--- a/esp32s3/src/rmt/sys_conf.rs
+++ b/esp32s3/src/rmt/sys_conf.rs
@@ -98,40 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYS_CONF")
-            .field(
-                "apb_fifo_mask",
-                &format_args!("{}", self.apb_fifo_mask().bit()),
-            )
-            .field(
-                "mem_clk_force_on",
-                &format_args!("{}", self.mem_clk_force_on().bit()),
-            )
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bits()))
-            .field("sclk_active", &format_args!("{}", self.sclk_active().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("apb_fifo_mask", &self.apb_fifo_mask())
+            .field("mem_clk_force_on", &self.mem_clk_force_on())
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_active", &self.sclk_active())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'h1: access memory directly. 1'h0: access memory by FIFO."]
     #[inline(always)]
diff --git a/esp32s3/src/rmt/tx_sim.rs b/esp32s3/src/rmt/tx_sim.rs
index b76a424751..fa17898d18 100644
--- a/esp32s3/src/rmt/tx_sim.rs
+++ b/esp32s3/src/rmt/tx_sim.rs
@@ -53,20 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_SIM")
-            .field("ch0", &format_args!("{}", self.ch0().bit()))
-            .field("ch1", &format_args!("{}", self.ch1().bit()))
-            .field("ch2", &format_args!("{}", self.ch2().bit()))
-            .field("ch3", &format_args!("{}", self.ch3().bit()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("ch0", &self.ch0())
+            .field("ch1", &self.ch1())
+            .field("ch2", &self.ch2())
+            .field("ch3", &self.ch3())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_SIM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels."]
     #[inline(always)]
diff --git a/esp32s3/src/rng/data.rs b/esp32s3/src/rng/data.rs
index 016046274d..4d812a63aa 100644
--- a/esp32s3/src/rng/data.rs
+++ b/esp32s3/src/rng/data.rs
@@ -6,12 +6,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Random number data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DATA_SPEC;
 impl crate::RegisterSpec for DATA_SPEC {
diff --git a/esp32s3/src/rsa/clean.rs b/esp32s3/src/rsa/clean.rs
index 8f2d6a8a89..1004f25cca 100644
--- a/esp32s3/src/rsa/clean.rs
+++ b/esp32s3/src/rsa/clean.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLEAN")
-            .field("clean", &format_args!("{}", self.clean().bit()))
+            .field("clean", &self.clean())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLEAN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RSA clean register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clean::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CLEAN_SPEC;
 impl crate::RegisterSpec for CLEAN_SPEC {
diff --git a/esp32s3/src/rsa/constant_time.rs b/esp32s3/src/rsa/constant_time.rs
index 691a96c9e0..5cc722f622 100644
--- a/esp32s3/src/rsa/constant_time.rs
+++ b/esp32s3/src/rsa/constant_time.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONSTANT_TIME")
-            .field(
-                "constant_time",
-                &format_args!("{}", self.constant_time().bit()),
-            )
+            .field("constant_time", &self.constant_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONSTANT_TIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Controls the CONSTANT_TIME option. 0: acceleration. 1: no acceleration(by default)."]
     #[inline(always)]
diff --git a/esp32s3/src/rsa/date.rs b/esp32s3/src/rsa/date.rs
index 87d8e3533f..319b1edcff 100644
--- a/esp32s3/src/rsa/date.rs
+++ b/esp32s3/src/rsa/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/rsa/idle.rs b/esp32s3/src/rsa/idle.rs
index 0b04117c96..b2e6494d3e 100644
--- a/esp32s3/src/rsa/idle.rs
+++ b/esp32s3/src/rsa/idle.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("IDLE")
-            .field("idle", &format_args!("{}", self.idle().bit()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("IDLE").field("idle", &self.idle()).finish()
     }
 }
 #[doc = "RSA idle register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idle::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s3/src/rsa/interrupt_ena.rs b/esp32s3/src/rsa/interrupt_ena.rs
index 4afbef8a13..147568353f 100644
--- a/esp32s3/src/rsa/interrupt_ena.rs
+++ b/esp32s3/src/rsa/interrupt_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERRUPT_ENA")
-            .field(
-                "interrupt_ena",
-                &format_args!("{}", self.interrupt_ena().bit()),
-            )
+            .field("interrupt_ena", &self.interrupt_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERRUPT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable the RSA interrupt. This option is enabled by default."]
     #[inline(always)]
diff --git a/esp32s3/src/rsa/m_prime.rs b/esp32s3/src/rsa/m_prime.rs
index a9be6a153e..68d67a62b8 100644
--- a/esp32s3/src/rsa/m_prime.rs
+++ b/esp32s3/src/rsa/m_prime.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("M_PRIME")
-            .field("m_prime", &format_args!("{}", self.m_prime().bits()))
+            .field("m_prime", &self.m_prime())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_PRIME_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stores M'"]
     #[inline(always)]
diff --git a/esp32s3/src/rsa/mode.rs b/esp32s3/src/rsa/mode.rs
index 0b67be2695..d0e2c795fc 100644
--- a/esp32s3/src/rsa/mode.rs
+++ b/esp32s3/src/rsa/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/rsa/search_enable.rs b/esp32s3/src/rsa/search_enable.rs
index 5a7194b471..1e78deb87a 100644
--- a/esp32s3/src/rsa/search_enable.rs
+++ b/esp32s3/src/rsa/search_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEARCH_ENABLE")
-            .field(
-                "search_enable",
-                &format_args!("{}", self.search_enable().bit()),
-            )
+            .field("search_enable", &self.search_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEARCH_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Controls the SEARCH option. 0: no acceleration(by default). 1: acceleration."]
     #[inline(always)]
diff --git a/esp32s3/src/rsa/search_pos.rs b/esp32s3/src/rsa/search_pos.rs
index ec767f7c3d..c136114cdc 100644
--- a/esp32s3/src/rsa/search_pos.rs
+++ b/esp32s3/src/rsa/search_pos.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SEARCH_POS")
-            .field("search_pos", &format_args!("{}", self.search_pos().bits()))
+            .field("search_pos", &self.search_pos())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SEARCH_POS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - This field is used to configure the starting search position when the acceleration option of SEARCH is used."]
     #[inline(always)]
diff --git a/esp32s3/src/rsa/z_mem.rs b/esp32s3/src/rsa/z_mem.rs
index 746af18ef5..2ccae2ffb1 100644
--- a/esp32s3/src/rsa/z_mem.rs
+++ b/esp32s3/src/rsa/z_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<Z_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Memory Z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Z_MEM_SPEC;
diff --git a/esp32s3/src/rtc_cntl/ana_conf.rs b/esp32s3/src/rtc_cntl/ana_conf.rs
index 219da8903f..74ad49830f 100644
--- a/esp32s3/src/rtc_cntl/ana_conf.rs
+++ b/esp32s3/src/rtc_cntl/ana_conf.rs
@@ -116,51 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ANA_CONF")
-            .field(
-                "i2c_reset_por_force_pd",
-                &format_args!("{}", self.i2c_reset_por_force_pd().bit()),
-            )
-            .field(
-                "i2c_reset_por_force_pu",
-                &format_args!("{}", self.i2c_reset_por_force_pu().bit()),
-            )
-            .field(
-                "glitch_rst_en",
-                &format_args!("{}", self.glitch_rst_en().bit()),
-            )
-            .field("sar_i2c_pu", &format_args!("{}", self.sar_i2c_pu().bit()))
-            .field(
-                "analog_top_iso_sleep",
-                &format_args!("{}", self.analog_top_iso_sleep().bit()),
-            )
-            .field(
-                "analog_top_iso_monitor",
-                &format_args!("{}", self.analog_top_iso_monitor().bit()),
-            )
-            .field(
-                "bbpll_cal_slp_start",
-                &format_args!("{}", self.bbpll_cal_slp_start().bit()),
-            )
-            .field("pvtmon_pu", &format_args!("{}", self.pvtmon_pu().bit()))
-            .field("txrf_i2c_pu", &format_args!("{}", self.txrf_i2c_pu().bit()))
-            .field(
-                "rfrx_pbus_pu",
-                &format_args!("{}", self.rfrx_pbus_pu().bit()),
-            )
-            .field(
-                "ckgen_i2c_pu",
-                &format_args!("{}", self.ckgen_i2c_pu().bit()),
-            )
-            .field("pll_i2c_pu", &format_args!("{}", self.pll_i2c_pu().bit()))
+            .field("i2c_reset_por_force_pd", &self.i2c_reset_por_force_pd())
+            .field("i2c_reset_por_force_pu", &self.i2c_reset_por_force_pu())
+            .field("glitch_rst_en", &self.glitch_rst_en())
+            .field("sar_i2c_pu", &self.sar_i2c_pu())
+            .field("analog_top_iso_sleep", &self.analog_top_iso_sleep())
+            .field("analog_top_iso_monitor", &self.analog_top_iso_monitor())
+            .field("bbpll_cal_slp_start", &self.bbpll_cal_slp_start())
+            .field("pvtmon_pu", &self.pvtmon_pu())
+            .field("txrf_i2c_pu", &self.txrf_i2c_pu())
+            .field("rfrx_pbus_pu", &self.rfrx_pbus_pu())
+            .field("ckgen_i2c_pu", &self.ckgen_i2c_pu())
+            .field("pll_i2c_pu", &self.pll_i2c_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ANA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - force down I2C_RESET_POR"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/bias_conf.rs b/esp32s3/src/rtc_cntl/bias_conf.rs
index 45854d6b60..c6ff3d754e 100644
--- a/esp32s3/src/rtc_cntl/bias_conf.rs
+++ b/esp32s3/src/rtc_cntl/bias_conf.rs
@@ -107,59 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BIAS_CONF")
-            .field(
-                "bias_buf_idle",
-                &format_args!("{}", self.bias_buf_idle().bit()),
-            )
-            .field(
-                "bias_buf_wake",
-                &format_args!("{}", self.bias_buf_wake().bit()),
-            )
-            .field(
-                "bias_buf_deep_slp",
-                &format_args!("{}", self.bias_buf_deep_slp().bit()),
-            )
-            .field(
-                "bias_buf_monitor",
-                &format_args!("{}", self.bias_buf_monitor().bit()),
-            )
-            .field(
-                "pd_cur_deep_slp",
-                &format_args!("{}", self.pd_cur_deep_slp().bit()),
-            )
-            .field(
-                "pd_cur_monitor",
-                &format_args!("{}", self.pd_cur_monitor().bit()),
-            )
-            .field(
-                "bias_sleep_deep_slp",
-                &format_args!("{}", self.bias_sleep_deep_slp().bit()),
-            )
-            .field(
-                "bias_sleep_monitor",
-                &format_args!("{}", self.bias_sleep_monitor().bit()),
-            )
-            .field(
-                "dbg_atten_deep_slp",
-                &format_args!("{}", self.dbg_atten_deep_slp().bits()),
-            )
-            .field(
-                "dbg_atten_monitor",
-                &format_args!("{}", self.dbg_atten_monitor().bits()),
-            )
-            .field(
-                "dbg_atten_wakeup",
-                &format_args!("{}", self.dbg_atten_wakeup().bits()),
-            )
+            .field("bias_buf_idle", &self.bias_buf_idle())
+            .field("bias_buf_wake", &self.bias_buf_wake())
+            .field("bias_buf_deep_slp", &self.bias_buf_deep_slp())
+            .field("bias_buf_monitor", &self.bias_buf_monitor())
+            .field("pd_cur_deep_slp", &self.pd_cur_deep_slp())
+            .field("pd_cur_monitor", &self.pd_cur_monitor())
+            .field("bias_sleep_deep_slp", &self.bias_sleep_deep_slp())
+            .field("bias_sleep_monitor", &self.bias_sleep_monitor())
+            .field("dbg_atten_deep_slp", &self.dbg_atten_deep_slp())
+            .field("dbg_atten_monitor", &self.dbg_atten_monitor())
+            .field("dbg_atten_wakeup", &self.dbg_atten_wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BIAS_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 10 - No public"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/brown_out.rs b/esp32s3/src/rtc_cntl/brown_out.rs
index 4ec4a2a079..dc62a29ea0 100644
--- a/esp32s3/src/rtc_cntl/brown_out.rs
+++ b/esp32s3/src/rtc_cntl/brown_out.rs
@@ -89,48 +89,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BROWN_OUT")
-            .field(
-                "brown_out_int_wait",
-                &format_args!("{}", self.brown_out_int_wait().bits()),
-            )
+            .field("brown_out_int_wait", &self.brown_out_int_wait())
             .field(
                 "brown_out_close_flash_ena",
-                &format_args!("{}", self.brown_out_close_flash_ena().bit()),
+                &self.brown_out_close_flash_ena(),
             )
-            .field(
-                "brown_out_pd_rf_ena",
-                &format_args!("{}", self.brown_out_pd_rf_ena().bit()),
-            )
-            .field(
-                "brown_out_rst_wait",
-                &format_args!("{}", self.brown_out_rst_wait().bits()),
-            )
-            .field(
-                "brown_out_rst_ena",
-                &format_args!("{}", self.brown_out_rst_ena().bit()),
-            )
-            .field(
-                "brown_out_rst_sel",
-                &format_args!("{}", self.brown_out_rst_sel().bit()),
-            )
-            .field(
-                "brown_out_ana_rst_en",
-                &format_args!("{}", self.brown_out_ana_rst_en().bit()),
-            )
-            .field(
-                "brown_out_ena",
-                &format_args!("{}", self.brown_out_ena().bit()),
-            )
-            .field("det", &format_args!("{}", self.det().bit()))
+            .field("brown_out_pd_rf_ena", &self.brown_out_pd_rf_ena())
+            .field("brown_out_rst_wait", &self.brown_out_rst_wait())
+            .field("brown_out_rst_ena", &self.brown_out_rst_ena())
+            .field("brown_out_rst_sel", &self.brown_out_rst_sel())
+            .field("brown_out_ana_rst_en", &self.brown_out_ana_rst_en())
+            .field("brown_out_ena", &self.brown_out_ena())
+            .field("det", &self.det())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BROWN_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 4:13 - brown out interrupt wait cycles"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/clk_conf.rs b/esp32s3/src/rtc_cntl/clk_conf.rs
index d3665075d5..1775c6a45f 100644
--- a/esp32s3/src/rtc_cntl/clk_conf.rs
+++ b/esp32s3/src/rtc_cntl/clk_conf.rs
@@ -179,82 +179,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field(
-                "efuse_clk_force_gating",
-                &format_args!("{}", self.efuse_clk_force_gating().bit()),
-            )
-            .field(
-                "efuse_clk_force_nogating",
-                &format_args!("{}", self.efuse_clk_force_nogating().bit()),
-            )
-            .field(
-                "ck8m_div_sel_vld",
-                &format_args!("{}", self.ck8m_div_sel_vld().bit()),
-            )
-            .field("ck8m_div", &format_args!("{}", self.ck8m_div().bits()))
-            .field("enb_ck8m", &format_args!("{}", self.enb_ck8m().bit()))
-            .field(
-                "enb_ck8m_div",
-                &format_args!("{}", self.enb_ck8m_div().bit()),
-            )
-            .field(
-                "dig_xtal32k_en",
-                &format_args!("{}", self.dig_xtal32k_en().bit()),
-            )
-            .field(
-                "dig_clk8m_d256_en",
-                &format_args!("{}", self.dig_clk8m_d256_en().bit()),
-            )
-            .field(
-                "dig_clk8m_en",
-                &format_args!("{}", self.dig_clk8m_en().bit()),
-            )
-            .field(
-                "ck8m_div_sel",
-                &format_args!("{}", self.ck8m_div_sel().bits()),
-            )
-            .field(
-                "xtal_force_nogating",
-                &format_args!("{}", self.xtal_force_nogating().bit()),
-            )
-            .field(
-                "ck8m_force_nogating",
-                &format_args!("{}", self.ck8m_force_nogating().bit()),
-            )
-            .field("ck8m_dfreq", &format_args!("{}", self.ck8m_dfreq().bits()))
-            .field(
-                "ck8m_force_pd",
-                &format_args!("{}", self.ck8m_force_pd().bit()),
-            )
-            .field(
-                "ck8m_force_pu",
-                &format_args!("{}", self.ck8m_force_pu().bit()),
-            )
-            .field(
-                "xtal_global_force_gating",
-                &format_args!("{}", self.xtal_global_force_gating().bit()),
-            )
+            .field("efuse_clk_force_gating", &self.efuse_clk_force_gating())
+            .field("efuse_clk_force_nogating", &self.efuse_clk_force_nogating())
+            .field("ck8m_div_sel_vld", &self.ck8m_div_sel_vld())
+            .field("ck8m_div", &self.ck8m_div())
+            .field("enb_ck8m", &self.enb_ck8m())
+            .field("enb_ck8m_div", &self.enb_ck8m_div())
+            .field("dig_xtal32k_en", &self.dig_xtal32k_en())
+            .field("dig_clk8m_d256_en", &self.dig_clk8m_d256_en())
+            .field("dig_clk8m_en", &self.dig_clk8m_en())
+            .field("ck8m_div_sel", &self.ck8m_div_sel())
+            .field("xtal_force_nogating", &self.xtal_force_nogating())
+            .field("ck8m_force_nogating", &self.ck8m_force_nogating())
+            .field("ck8m_dfreq", &self.ck8m_dfreq())
+            .field("ck8m_force_pd", &self.ck8m_force_pd())
+            .field("ck8m_force_pu", &self.ck8m_force_pu())
+            .field("xtal_global_force_gating", &self.xtal_global_force_gating())
             .field(
                 "xtal_global_force_nogating",
-                &format_args!("{}", self.xtal_global_force_nogating().bit()),
-            )
-            .field(
-                "fast_clk_rtc_sel",
-                &format_args!("{}", self.fast_clk_rtc_sel().bit()),
-            )
-            .field(
-                "ana_clk_rtc_sel",
-                &format_args!("{}", self.ana_clk_rtc_sel().bits()),
+                &self.xtal_global_force_nogating(),
             )
+            .field("fast_clk_rtc_sel", &self.fast_clk_rtc_sel())
+            .field("ana_clk_rtc_sel", &self.ana_clk_rtc_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - force efuse clk gating"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/cocpu_ctrl.rs b/esp32s3/src/rtc_cntl/cocpu_ctrl.rs
index 0e2339bb1c..701b39c969 100644
--- a/esp32s3/src/rtc_cntl/cocpu_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/cocpu_ctrl.rs
@@ -100,46 +100,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COCPU_CTRL")
-            .field(
-                "cocpu_clk_fo",
-                &format_args!("{}", self.cocpu_clk_fo().bit()),
-            )
-            .field(
-                "cocpu_start_2_reset_dis",
-                &format_args!("{}", self.cocpu_start_2_reset_dis().bits()),
-            )
-            .field(
-                "cocpu_start_2_intr_en",
-                &format_args!("{}", self.cocpu_start_2_intr_en().bits()),
-            )
-            .field("cocpu_shut", &format_args!("{}", self.cocpu_shut().bit()))
-            .field(
-                "cocpu_shut_2_clk_dis",
-                &format_args!("{}", self.cocpu_shut_2_clk_dis().bits()),
-            )
-            .field(
-                "cocpu_shut_reset_en",
-                &format_args!("{}", self.cocpu_shut_reset_en().bit()),
-            )
-            .field("cocpu_sel", &format_args!("{}", self.cocpu_sel().bit()))
-            .field(
-                "cocpu_done_force",
-                &format_args!("{}", self.cocpu_done_force().bit()),
-            )
-            .field("cocpu_done", &format_args!("{}", self.cocpu_done().bit()))
-            .field(
-                "cocpu_clkgate_en",
-                &format_args!("{}", self.cocpu_clkgate_en().bit()),
-            )
+            .field("cocpu_clk_fo", &self.cocpu_clk_fo())
+            .field("cocpu_start_2_reset_dis", &self.cocpu_start_2_reset_dis())
+            .field("cocpu_start_2_intr_en", &self.cocpu_start_2_intr_en())
+            .field("cocpu_shut", &self.cocpu_shut())
+            .field("cocpu_shut_2_clk_dis", &self.cocpu_shut_2_clk_dis())
+            .field("cocpu_shut_reset_en", &self.cocpu_shut_reset_en())
+            .field("cocpu_sel", &self.cocpu_sel())
+            .field("cocpu_done_force", &self.cocpu_done_force())
+            .field("cocpu_done", &self.cocpu_done())
+            .field("cocpu_clkgate_en", &self.cocpu_clkgate_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COCPU_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - cocpu clk force on"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/cocpu_disable.rs b/esp32s3/src/rtc_cntl/cocpu_disable.rs
index 6a50bfe8e8..e4b09063b0 100644
--- a/esp32s3/src/rtc_cntl/cocpu_disable.rs
+++ b/esp32s3/src/rtc_cntl/cocpu_disable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COCPU_DISABLE")
-            .field(
-                "disable_rtc_cpu",
-                &format_args!("{}", self.disable_rtc_cpu().bit()),
-            )
+            .field("disable_rtc_cpu", &self.disable_rtc_cpu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COCPU_DISABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - configure ulp diable"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/cpu_period_conf.rs b/esp32s3/src/rtc_cntl/cpu_period_conf.rs
index 0703b1a6e5..713e81c275 100644
--- a/esp32s3/src/rtc_cntl/cpu_period_conf.rs
+++ b/esp32s3/src/rtc_cntl/cpu_period_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERIOD_CONF")
-            .field("cpusel_conf", &format_args!("{}", self.cpusel_conf().bit()))
-            .field(
-                "cpuperiod_sel",
-                &format_args!("{}", self.cpuperiod_sel().bits()),
-            )
+            .field("cpusel_conf", &self.cpusel_conf())
+            .field("cpuperiod_sel", &self.cpuperiod_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERIOD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 29 - CPU sel option"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/date.rs b/esp32s3/src/rtc_cntl/date.rs
index 1c99fa8753..c1761e6b56 100644
--- a/esp32s3/src/rtc_cntl/date.rs
+++ b/esp32s3/src/rtc_cntl/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/rtc_cntl/diag0.rs b/esp32s3/src/rtc_cntl/diag0.rs
index 38fb7bd66d..5c76876276 100644
--- a/esp32s3/src/rtc_cntl/diag0.rs
+++ b/esp32s3/src/rtc_cntl/diag0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIAG0")
-            .field(
-                "low_power_diag1",
-                &format_args!("{}", self.low_power_diag1().bits()),
-            )
+            .field("low_power_diag1", &self.low_power_diag1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIAG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "No public\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diag0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIAG0_SPEC;
 impl crate::RegisterSpec for DIAG0_SPEC {
diff --git a/esp32s3/src/rtc_cntl/dig_iso.rs b/esp32s3/src/rtc_cntl/dig_iso.rs
index bb74264606..73b4e6b42f 100644
--- a/esp32s3/src/rtc_cntl/dig_iso.rs
+++ b/esp32s3/src/rtc_cntl/dig_iso.rs
@@ -170,81 +170,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIG_ISO")
-            .field("force_off", &format_args!("{}", self.force_off().bit()))
-            .field("force_on", &format_args!("{}", self.force_on().bit()))
-            .field(
-                "dg_pad_autohold",
-                &format_args!("{}", self.dg_pad_autohold().bit()),
-            )
-            .field(
-                "dg_pad_autohold_en",
-                &format_args!("{}", self.dg_pad_autohold_en().bit()),
-            )
-            .field(
-                "dg_pad_force_noiso",
-                &format_args!("{}", self.dg_pad_force_noiso().bit()),
-            )
-            .field(
-                "dg_pad_force_iso",
-                &format_args!("{}", self.dg_pad_force_iso().bit()),
-            )
-            .field(
-                "dg_pad_force_unhold",
-                &format_args!("{}", self.dg_pad_force_unhold().bit()),
-            )
-            .field(
-                "dg_pad_force_hold",
-                &format_args!("{}", self.dg_pad_force_hold().bit()),
-            )
-            .field(
-                "bt_force_iso",
-                &format_args!("{}", self.bt_force_iso().bit()),
-            )
-            .field(
-                "bt_force_noiso",
-                &format_args!("{}", self.bt_force_noiso().bit()),
-            )
-            .field(
-                "dg_peri_force_iso",
-                &format_args!("{}", self.dg_peri_force_iso().bit()),
-            )
-            .field(
-                "dg_peri_force_noiso",
-                &format_args!("{}", self.dg_peri_force_noiso().bit()),
-            )
-            .field(
-                "cpu_top_force_iso",
-                &format_args!("{}", self.cpu_top_force_iso().bit()),
-            )
-            .field(
-                "cpu_top_force_noiso",
-                &format_args!("{}", self.cpu_top_force_noiso().bit()),
-            )
-            .field(
-                "wifi_force_iso",
-                &format_args!("{}", self.wifi_force_iso().bit()),
-            )
-            .field(
-                "wifi_force_noiso",
-                &format_args!("{}", self.wifi_force_noiso().bit()),
-            )
-            .field(
-                "dg_wrap_force_iso",
-                &format_args!("{}", self.dg_wrap_force_iso().bit()),
-            )
-            .field(
-                "dg_wrap_force_noiso",
-                &format_args!("{}", self.dg_wrap_force_noiso().bit()),
-            )
+            .field("force_off", &self.force_off())
+            .field("force_on", &self.force_on())
+            .field("dg_pad_autohold", &self.dg_pad_autohold())
+            .field("dg_pad_autohold_en", &self.dg_pad_autohold_en())
+            .field("dg_pad_force_noiso", &self.dg_pad_force_noiso())
+            .field("dg_pad_force_iso", &self.dg_pad_force_iso())
+            .field("dg_pad_force_unhold", &self.dg_pad_force_unhold())
+            .field("dg_pad_force_hold", &self.dg_pad_force_hold())
+            .field("bt_force_iso", &self.bt_force_iso())
+            .field("bt_force_noiso", &self.bt_force_noiso())
+            .field("dg_peri_force_iso", &self.dg_peri_force_iso())
+            .field("dg_peri_force_noiso", &self.dg_peri_force_noiso())
+            .field("cpu_top_force_iso", &self.cpu_top_force_iso())
+            .field("cpu_top_force_noiso", &self.cpu_top_force_noiso())
+            .field("wifi_force_iso", &self.wifi_force_iso())
+            .field("wifi_force_noiso", &self.wifi_force_noiso())
+            .field("dg_wrap_force_iso", &self.dg_wrap_force_iso())
+            .field("dg_wrap_force_noiso", &self.dg_wrap_force_noiso())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIG_ISO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - No public"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/dig_pad_hold.rs b/esp32s3/src/rtc_cntl/dig_pad_hold.rs
index f78f731eda..0a98dc45c2 100644
--- a/esp32s3/src/rtc_cntl/dig_pad_hold.rs
+++ b/esp32s3/src/rtc_cntl/dig_pad_hold.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIG_PAD_HOLD")
-            .field(
-                "dig_pad_hold",
-                &format_args!("{}", self.dig_pad_hold().bits()),
-            )
+            .field("dig_pad_hold", &self.dig_pad_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIG_PAD_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - configure digtal pad hold"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/dig_pwc.rs b/esp32s3/src/rtc_cntl/dig_pwc.rs
index f21551c26c..bf6a6cd4bd 100644
--- a/esp32s3/src/rtc_cntl/dig_pwc.rs
+++ b/esp32s3/src/rtc_cntl/dig_pwc.rs
@@ -161,71 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIG_PWC")
-            .field(
-                "lslp_mem_force_pd",
-                &format_args!("{}", self.lslp_mem_force_pd().bit()),
-            )
-            .field(
-                "lslp_mem_force_pu",
-                &format_args!("{}", self.lslp_mem_force_pu().bit()),
-            )
-            .field("bt_force_pd", &format_args!("{}", self.bt_force_pd().bit()))
-            .field("bt_force_pu", &format_args!("{}", self.bt_force_pu().bit()))
-            .field(
-                "dg_peri_force_pd",
-                &format_args!("{}", self.dg_peri_force_pd().bit()),
-            )
-            .field(
-                "dg_peri_force_pu",
-                &format_args!("{}", self.dg_peri_force_pu().bit()),
-            )
-            .field(
-                "wifi_force_pd",
-                &format_args!("{}", self.wifi_force_pd().bit()),
-            )
-            .field(
-                "wifi_force_pu",
-                &format_args!("{}", self.wifi_force_pu().bit()),
-            )
-            .field(
-                "dg_wrap_force_pd",
-                &format_args!("{}", self.dg_wrap_force_pd().bit()),
-            )
-            .field(
-                "dg_wrap_force_pu",
-                &format_args!("{}", self.dg_wrap_force_pu().bit()),
-            )
-            .field(
-                "cpu_top_force_pd",
-                &format_args!("{}", self.cpu_top_force_pd().bit()),
-            )
-            .field(
-                "cpu_top_force_pu",
-                &format_args!("{}", self.cpu_top_force_pu().bit()),
-            )
-            .field("bt_pd_en", &format_args!("{}", self.bt_pd_en().bit()))
-            .field(
-                "dg_peri_pd_en",
-                &format_args!("{}", self.dg_peri_pd_en().bit()),
-            )
-            .field(
-                "cpu_top_pd_en",
-                &format_args!("{}", self.cpu_top_pd_en().bit()),
-            )
-            .field("wifi_pd_en", &format_args!("{}", self.wifi_pd_en().bit()))
-            .field(
-                "dg_wrap_pd_en",
-                &format_args!("{}", self.dg_wrap_pd_en().bit()),
-            )
+            .field("lslp_mem_force_pd", &self.lslp_mem_force_pd())
+            .field("lslp_mem_force_pu", &self.lslp_mem_force_pu())
+            .field("bt_force_pd", &self.bt_force_pd())
+            .field("bt_force_pu", &self.bt_force_pu())
+            .field("dg_peri_force_pd", &self.dg_peri_force_pd())
+            .field("dg_peri_force_pu", &self.dg_peri_force_pu())
+            .field("wifi_force_pd", &self.wifi_force_pd())
+            .field("wifi_force_pu", &self.wifi_force_pu())
+            .field("dg_wrap_force_pd", &self.dg_wrap_force_pd())
+            .field("dg_wrap_force_pu", &self.dg_wrap_force_pu())
+            .field("cpu_top_force_pd", &self.cpu_top_force_pd())
+            .field("cpu_top_force_pu", &self.cpu_top_force_pu())
+            .field("bt_pd_en", &self.bt_pd_en())
+            .field("dg_peri_pd_en", &self.dg_peri_pd_en())
+            .field("cpu_top_pd_en", &self.cpu_top_pd_en())
+            .field("wifi_pd_en", &self.wifi_pd_en())
+            .field("dg_wrap_pd_en", &self.dg_wrap_pd_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIG_PWC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - memories in digital core force PD in sleep"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/ext_wakeup1.rs b/esp32s3/src/rtc_cntl/ext_wakeup1.rs
index 378c3c2815..861ea95080 100644
--- a/esp32s3/src/rtc_cntl/ext_wakeup1.rs
+++ b/esp32s3/src/rtc_cntl/ext_wakeup1.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP1")
-            .field(
-                "ext_wakeup1_sel",
-                &format_args!("{}", self.ext_wakeup1_sel().bits()),
-            )
+            .field("ext_wakeup1_sel", &self.ext_wakeup1_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Bitmap to select RTC pads for ext wakeup1"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/ext_wakeup1_status.rs b/esp32s3/src/rtc_cntl/ext_wakeup1_status.rs
index 1f0aa23b8b..c7165c076f 100644
--- a/esp32s3/src/rtc_cntl/ext_wakeup1_status.rs
+++ b/esp32s3/src/rtc_cntl/ext_wakeup1_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP1_STATUS")
-            .field(
-                "ext_wakeup1_status",
-                &format_args!("{}", self.ext_wakeup1_status().bits()),
-            )
+            .field("ext_wakeup1_status", &self.ext_wakeup1_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP1_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "check ext wakeup1 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup1_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EXT_WAKEUP1_STATUS_SPEC;
 impl crate::RegisterSpec for EXT_WAKEUP1_STATUS_SPEC {
diff --git a/esp32s3/src/rtc_cntl/ext_wakeup_conf.rs b/esp32s3/src/rtc_cntl/ext_wakeup_conf.rs
index bc1d09de8e..9fa919f580 100644
--- a/esp32s3/src/rtc_cntl/ext_wakeup_conf.rs
+++ b/esp32s3/src/rtc_cntl/ext_wakeup_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP_CONF")
-            .field(
-                "gpio_wakeup_filter",
-                &format_args!("{}", self.gpio_wakeup_filter().bit()),
-            )
-            .field(
-                "ext_wakeup0_lv",
-                &format_args!("{}", self.ext_wakeup0_lv().bit()),
-            )
-            .field(
-                "ext_wakeup1_lv",
-                &format_args!("{}", self.ext_wakeup1_lv().bit()),
-            )
+            .field("gpio_wakeup_filter", &self.gpio_wakeup_filter())
+            .field("ext_wakeup0_lv", &self.ext_wakeup0_lv())
+            .field("ext_wakeup1_lv", &self.ext_wakeup1_lv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 29 - enable filter for gpio wakeup event"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/ext_xtl_conf.rs b/esp32s3/src/rtc_cntl/ext_xtl_conf.rs
index 99ab24ee6f..e3cba19596 100644
--- a/esp32s3/src/rtc_cntl/ext_xtl_conf.rs
+++ b/esp32s3/src/rtc_cntl/ext_xtl_conf.rs
@@ -168,84 +168,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_XTL_CONF")
-            .field(
-                "xtal32k_wdt_en",
-                &format_args!("{}", self.xtal32k_wdt_en().bit()),
-            )
-            .field(
-                "xtal32k_wdt_clk_fo",
-                &format_args!("{}", self.xtal32k_wdt_clk_fo().bit()),
-            )
-            .field(
-                "xtal32k_wdt_reset",
-                &format_args!("{}", self.xtal32k_wdt_reset().bit()),
-            )
-            .field(
-                "xtal32k_ext_clk_fo",
-                &format_args!("{}", self.xtal32k_ext_clk_fo().bit()),
-            )
-            .field(
-                "xtal32k_auto_backup",
-                &format_args!("{}", self.xtal32k_auto_backup().bit()),
-            )
-            .field(
-                "xtal32k_auto_restart",
-                &format_args!("{}", self.xtal32k_auto_restart().bit()),
-            )
-            .field(
-                "xtal32k_auto_return",
-                &format_args!("{}", self.xtal32k_auto_return().bit()),
-            )
-            .field(
-                "xtal32k_xpd_force",
-                &format_args!("{}", self.xtal32k_xpd_force().bit()),
-            )
-            .field(
-                "enckinit_xtal_32k",
-                &format_args!("{}", self.enckinit_xtal_32k().bit()),
-            )
-            .field(
-                "dbuf_xtal_32k",
-                &format_args!("{}", self.dbuf_xtal_32k().bit()),
-            )
-            .field(
-                "dgm_xtal_32k",
-                &format_args!("{}", self.dgm_xtal_32k().bits()),
-            )
-            .field(
-                "dres_xtal_32k",
-                &format_args!("{}", self.dres_xtal_32k().bits()),
-            )
-            .field(
-                "xpd_xtal_32k",
-                &format_args!("{}", self.xpd_xtal_32k().bit()),
-            )
-            .field(
-                "dac_xtal_32k",
-                &format_args!("{}", self.dac_xtal_32k().bits()),
-            )
-            .field("wdt_state", &format_args!("{}", self.wdt_state().bits()))
-            .field(
-                "xtal32k_gpio_sel",
-                &format_args!("{}", self.xtal32k_gpio_sel().bit()),
-            )
-            .field(
-                "xtl_ext_ctr_lv",
-                &format_args!("{}", self.xtl_ext_ctr_lv().bit()),
-            )
-            .field(
-                "xtl_ext_ctr_en",
-                &format_args!("{}", self.xtl_ext_ctr_en().bit()),
-            )
+            .field("xtal32k_wdt_en", &self.xtal32k_wdt_en())
+            .field("xtal32k_wdt_clk_fo", &self.xtal32k_wdt_clk_fo())
+            .field("xtal32k_wdt_reset", &self.xtal32k_wdt_reset())
+            .field("xtal32k_ext_clk_fo", &self.xtal32k_ext_clk_fo())
+            .field("xtal32k_auto_backup", &self.xtal32k_auto_backup())
+            .field("xtal32k_auto_restart", &self.xtal32k_auto_restart())
+            .field("xtal32k_auto_return", &self.xtal32k_auto_return())
+            .field("xtal32k_xpd_force", &self.xtal32k_xpd_force())
+            .field("enckinit_xtal_32k", &self.enckinit_xtal_32k())
+            .field("dbuf_xtal_32k", &self.dbuf_xtal_32k())
+            .field("dgm_xtal_32k", &self.dgm_xtal_32k())
+            .field("dres_xtal_32k", &self.dres_xtal_32k())
+            .field("xpd_xtal_32k", &self.xpd_xtal_32k())
+            .field("dac_xtal_32k", &self.dac_xtal_32k())
+            .field("wdt_state", &self.wdt_state())
+            .field("xtal32k_gpio_sel", &self.xtal32k_gpio_sel())
+            .field("xtl_ext_ctr_lv", &self.xtl_ext_ctr_lv())
+            .field("xtl_ext_ctr_en", &self.xtl_ext_ctr_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_XTL_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - xtal 32k watch dog enable"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/fib_sel.rs b/esp32s3/src/rtc_cntl/fib_sel.rs
index 63949ed9d9..1c996fe8a2 100644
--- a/esp32s3/src/rtc_cntl/fib_sel.rs
+++ b/esp32s3/src/rtc_cntl/fib_sel.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIB_SEL")
-            .field("fib_sel", &format_args!("{}", self.fib_sel().bits()))
+            .field("fib_sel", &self.fib_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIB_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - No public"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/int_ena.rs b/esp32s3/src/rtc_cntl/int_ena.rs
index 7859757a66..784c8c606e 100644
--- a/esp32s3/src/rtc_cntl/int_ena.rs
+++ b/esp32s3/src/rtc_cntl/int_ena.rs
@@ -197,54 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field(
-                "touch_scan_done",
-                &format_args!("{}", self.touch_scan_done().bit()),
-            )
-            .field("ulp_cp", &format_args!("{}", self.ulp_cp().bit()))
-            .field("touch_done", &format_args!("{}", self.touch_done().bit()))
-            .field(
-                "touch_active",
-                &format_args!("{}", self.touch_active().bit()),
-            )
-            .field(
-                "touch_inactive",
-                &format_args!("{}", self.touch_inactive().bit()),
-            )
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
-            .field("saradc1", &format_args!("{}", self.saradc1().bit()))
-            .field("tsens", &format_args!("{}", self.tsens().bit()))
-            .field("cocpu", &format_args!("{}", self.cocpu().bit()))
-            .field("saradc2", &format_args!("{}", self.saradc2().bit()))
-            .field("swd", &format_args!("{}", self.swd().bit()))
-            .field(
-                "xtal32k_dead",
-                &format_args!("{}", self.xtal32k_dead().bit()),
-            )
-            .field("cocpu_trap", &format_args!("{}", self.cocpu_trap().bit()))
-            .field(
-                "touch_timeout",
-                &format_args!("{}", self.touch_timeout().bit()),
-            )
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field(
-                "touch_approach_loop_done",
-                &format_args!("{}", self.touch_approach_loop_done().bit()),
-            )
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("wdt", &self.wdt())
+            .field("touch_scan_done", &self.touch_scan_done())
+            .field("ulp_cp", &self.ulp_cp())
+            .field("touch_done", &self.touch_done())
+            .field("touch_active", &self.touch_active())
+            .field("touch_inactive", &self.touch_inactive())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("saradc1", &self.saradc1())
+            .field("tsens", &self.tsens())
+            .field("cocpu", &self.cocpu())
+            .field("saradc2", &self.saradc2())
+            .field("swd", &self.swd())
+            .field("xtal32k_dead", &self.xtal32k_dead())
+            .field("cocpu_trap", &self.cocpu_trap())
+            .field("touch_timeout", &self.touch_timeout())
+            .field("glitch_det", &self.glitch_det())
+            .field("touch_approach_loop_done", &self.touch_approach_loop_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable sleep wakeup interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/int_raw.rs b/esp32s3/src/rtc_cntl/int_raw.rs
index e0dd428821..0cdb6e16b5 100644
--- a/esp32s3/src/rtc_cntl/int_raw.rs
+++ b/esp32s3/src/rtc_cntl/int_raw.rs
@@ -157,54 +157,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field(
-                "touch_scan_done",
-                &format_args!("{}", self.touch_scan_done().bit()),
-            )
-            .field("ulp_cp", &format_args!("{}", self.ulp_cp().bit()))
-            .field("touch_done", &format_args!("{}", self.touch_done().bit()))
-            .field(
-                "touch_active",
-                &format_args!("{}", self.touch_active().bit()),
-            )
-            .field(
-                "touch_inactive",
-                &format_args!("{}", self.touch_inactive().bit()),
-            )
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
-            .field("saradc1", &format_args!("{}", self.saradc1().bit()))
-            .field("tsens", &format_args!("{}", self.tsens().bit()))
-            .field("cocpu", &format_args!("{}", self.cocpu().bit()))
-            .field("saradc2", &format_args!("{}", self.saradc2().bit()))
-            .field("swd", &format_args!("{}", self.swd().bit()))
-            .field(
-                "xtal32k_dead",
-                &format_args!("{}", self.xtal32k_dead().bit()),
-            )
-            .field("cocpu_trap", &format_args!("{}", self.cocpu_trap().bit()))
-            .field(
-                "touch_timeout",
-                &format_args!("{}", self.touch_timeout().bit()),
-            )
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field(
-                "touch_approach_loop_done",
-                &format_args!("{}", self.touch_approach_loop_done().bit()),
-            )
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("wdt", &self.wdt())
+            .field("touch_scan_done", &self.touch_scan_done())
+            .field("ulp_cp", &self.ulp_cp())
+            .field("touch_done", &self.touch_done())
+            .field("touch_active", &self.touch_active())
+            .field("touch_inactive", &self.touch_inactive())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("saradc1", &self.saradc1())
+            .field("tsens", &self.tsens())
+            .field("cocpu", &self.cocpu())
+            .field("saradc2", &self.saradc2())
+            .field("swd", &self.swd())
+            .field("xtal32k_dead", &self.xtal32k_dead())
+            .field("cocpu_trap", &self.cocpu_trap())
+            .field("touch_timeout", &self.touch_timeout())
+            .field("glitch_det", &self.glitch_det())
+            .field("touch_approach_loop_done", &self.touch_approach_loop_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20 - touch approach mode loop interrupt raw"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/int_st.rs b/esp32s3/src/rtc_cntl/int_st.rs
index 115322f253..0f8dda3c4f 100644
--- a/esp32s3/src/rtc_cntl/int_st.rs
+++ b/esp32s3/src/rtc_cntl/int_st.rs
@@ -153,54 +153,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("sdio_idle", &format_args!("{}", self.sdio_idle().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
-            .field(
-                "touch_scan_done",
-                &format_args!("{}", self.touch_scan_done().bit()),
-            )
-            .field("ulp_cp", &format_args!("{}", self.ulp_cp().bit()))
-            .field("touch_done", &format_args!("{}", self.touch_done().bit()))
-            .field(
-                "touch_active",
-                &format_args!("{}", self.touch_active().bit()),
-            )
-            .field(
-                "touch_inactive",
-                &format_args!("{}", self.touch_inactive().bit()),
-            )
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
-            .field("main_timer", &format_args!("{}", self.main_timer().bit()))
-            .field("saradc1", &format_args!("{}", self.saradc1().bit()))
-            .field("tsens", &format_args!("{}", self.tsens().bit()))
-            .field("cocpu", &format_args!("{}", self.cocpu().bit()))
-            .field("saradc2", &format_args!("{}", self.saradc2().bit()))
-            .field("swd", &format_args!("{}", self.swd().bit()))
-            .field(
-                "xtal32k_dead",
-                &format_args!("{}", self.xtal32k_dead().bit()),
-            )
-            .field("cocpu_trap", &format_args!("{}", self.cocpu_trap().bit()))
-            .field(
-                "touch_timeout",
-                &format_args!("{}", self.touch_timeout().bit()),
-            )
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field(
-                "touch_approach_loop_done",
-                &format_args!("{}", self.touch_approach_loop_done().bit()),
-            )
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sdio_idle", &self.sdio_idle())
+            .field("wdt", &self.wdt())
+            .field("touch_scan_done", &self.touch_scan_done())
+            .field("ulp_cp", &self.ulp_cp())
+            .field("touch_done", &self.touch_done())
+            .field("touch_active", &self.touch_active())
+            .field("touch_inactive", &self.touch_inactive())
+            .field("brown_out", &self.brown_out())
+            .field("main_timer", &self.main_timer())
+            .field("saradc1", &self.saradc1())
+            .field("tsens", &self.tsens())
+            .field("cocpu", &self.cocpu())
+            .field("saradc2", &self.saradc2())
+            .field("swd", &self.swd())
+            .field("xtal32k_dead", &self.xtal32k_dead())
+            .field("cocpu_trap", &self.cocpu_trap())
+            .field("touch_timeout", &self.touch_timeout())
+            .field("glitch_det", &self.glitch_det())
+            .field("touch_approach_loop_done", &self.touch_approach_loop_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "rtc interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/rtc_cntl/low_power_st.rs b/esp32s3/src/rtc_cntl/low_power_st.rs
index 29a897d074..a4ee93e036 100644
--- a/esp32s3/src/rtc_cntl/low_power_st.rs
+++ b/esp32s3/src/rtc_cntl/low_power_st.rs
@@ -202,106 +202,37 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOW_POWER_ST")
-            .field("xpd_rom0", &format_args!("{}", self.xpd_rom0().bit()))
-            .field(
-                "xpd_dig_dcdc",
-                &format_args!("{}", self.xpd_dig_dcdc().bit()),
-            )
-            .field("peri_iso", &format_args!("{}", self.peri_iso().bit()))
-            .field(
-                "xpd_rtc_peri",
-                &format_args!("{}", self.xpd_rtc_peri().bit()),
-            )
-            .field("wifi_iso", &format_args!("{}", self.wifi_iso().bit()))
-            .field("xpd_wifi", &format_args!("{}", self.xpd_wifi().bit()))
-            .field("dig_iso", &format_args!("{}", self.dig_iso().bit()))
-            .field("xpd_dig", &format_args!("{}", self.xpd_dig().bit()))
-            .field(
-                "touch_state_start",
-                &format_args!("{}", self.touch_state_start().bit()),
-            )
-            .field(
-                "touch_state_switch",
-                &format_args!("{}", self.touch_state_switch().bit()),
-            )
-            .field(
-                "touch_state_slp",
-                &format_args!("{}", self.touch_state_slp().bit()),
-            )
-            .field(
-                "touch_state_done",
-                &format_args!("{}", self.touch_state_done().bit()),
-            )
-            .field(
-                "cocpu_state_start",
-                &format_args!("{}", self.cocpu_state_start().bit()),
-            )
-            .field(
-                "cocpu_state_switch",
-                &format_args!("{}", self.cocpu_state_switch().bit()),
-            )
-            .field(
-                "cocpu_state_slp",
-                &format_args!("{}", self.cocpu_state_slp().bit()),
-            )
-            .field(
-                "cocpu_state_done",
-                &format_args!("{}", self.cocpu_state_done().bit()),
-            )
-            .field(
-                "main_state_xtal_iso",
-                &format_args!("{}", self.main_state_xtal_iso().bit()),
-            )
-            .field(
-                "main_state_pll_on",
-                &format_args!("{}", self.main_state_pll_on().bit()),
-            )
-            .field(
-                "rdy_for_wakeup",
-                &format_args!("{}", self.rdy_for_wakeup().bit()),
-            )
-            .field(
-                "main_state_wait_end",
-                &format_args!("{}", self.main_state_wait_end().bit()),
-            )
-            .field(
-                "in_wakeup_state",
-                &format_args!("{}", self.in_wakeup_state().bit()),
-            )
-            .field(
-                "in_low_power_state",
-                &format_args!("{}", self.in_low_power_state().bit()),
-            )
-            .field(
-                "main_state_in_wait_8m",
-                &format_args!("{}", self.main_state_in_wait_8m().bit()),
-            )
-            .field(
-                "main_state_in_wait_pll",
-                &format_args!("{}", self.main_state_in_wait_pll().bit()),
-            )
-            .field(
-                "main_state_in_wait_xtl",
-                &format_args!("{}", self.main_state_in_wait_xtl().bit()),
-            )
-            .field(
-                "main_state_in_slp",
-                &format_args!("{}", self.main_state_in_slp().bit()),
-            )
-            .field(
-                "main_state_in_idle",
-                &format_args!("{}", self.main_state_in_idle().bit()),
-            )
-            .field("main_state", &format_args!("{}", self.main_state().bits()))
+            .field("xpd_rom0", &self.xpd_rom0())
+            .field("xpd_dig_dcdc", &self.xpd_dig_dcdc())
+            .field("peri_iso", &self.peri_iso())
+            .field("xpd_rtc_peri", &self.xpd_rtc_peri())
+            .field("wifi_iso", &self.wifi_iso())
+            .field("xpd_wifi", &self.xpd_wifi())
+            .field("dig_iso", &self.dig_iso())
+            .field("xpd_dig", &self.xpd_dig())
+            .field("touch_state_start", &self.touch_state_start())
+            .field("touch_state_switch", &self.touch_state_switch())
+            .field("touch_state_slp", &self.touch_state_slp())
+            .field("touch_state_done", &self.touch_state_done())
+            .field("cocpu_state_start", &self.cocpu_state_start())
+            .field("cocpu_state_switch", &self.cocpu_state_switch())
+            .field("cocpu_state_slp", &self.cocpu_state_slp())
+            .field("cocpu_state_done", &self.cocpu_state_done())
+            .field("main_state_xtal_iso", &self.main_state_xtal_iso())
+            .field("main_state_pll_on", &self.main_state_pll_on())
+            .field("rdy_for_wakeup", &self.rdy_for_wakeup())
+            .field("main_state_wait_end", &self.main_state_wait_end())
+            .field("in_wakeup_state", &self.in_wakeup_state())
+            .field("in_low_power_state", &self.in_low_power_state())
+            .field("main_state_in_wait_8m", &self.main_state_in_wait_8m())
+            .field("main_state_in_wait_pll", &self.main_state_in_wait_pll())
+            .field("main_state_in_wait_xtl", &self.main_state_in_wait_xtl())
+            .field("main_state_in_slp", &self.main_state_in_slp())
+            .field("main_state_in_idle", &self.main_state_in_idle())
+            .field("main_state", &self.main_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOW_POWER_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "reserved register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`low_power_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOW_POWER_ST_SPEC;
 impl crate::RegisterSpec for LOW_POWER_ST_SPEC {
diff --git a/esp32s3/src/rtc_cntl/option1.rs b/esp32s3/src/rtc_cntl/option1.rs
index 7db427a826..1dbf3764e1 100644
--- a/esp32s3/src/rtc_cntl/option1.rs
+++ b/esp32s3/src/rtc_cntl/option1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OPTION1")
-            .field(
-                "force_download_boot",
-                &format_args!("{}", self.force_download_boot().bit()),
-            )
+            .field("force_download_boot", &self.force_download_boot())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OPTION1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - force chip entry download boot by sw"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/options0.rs b/esp32s3/src/rtc_cntl/options0.rs
index 1ddb964da8..f5ad5cfe22 100644
--- a/esp32s3/src/rtc_cntl/options0.rs
+++ b/esp32s3/src/rtc_cntl/options0.rs
@@ -185,91 +185,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OPTIONS0")
-            .field(
-                "sw_stall_appcpu_c0",
-                &format_args!("{}", self.sw_stall_appcpu_c0().bits()),
-            )
-            .field(
-                "sw_stall_procpu_c0",
-                &format_args!("{}", self.sw_stall_procpu_c0().bits()),
-            )
-            .field(
-                "bb_i2c_force_pd",
-                &format_args!("{}", self.bb_i2c_force_pd().bit()),
-            )
-            .field(
-                "bb_i2c_force_pu",
-                &format_args!("{}", self.bb_i2c_force_pu().bit()),
-            )
-            .field(
-                "bbpll_i2c_force_pd",
-                &format_args!("{}", self.bbpll_i2c_force_pd().bit()),
-            )
-            .field(
-                "bbpll_i2c_force_pu",
-                &format_args!("{}", self.bbpll_i2c_force_pu().bit()),
-            )
-            .field(
-                "bbpll_force_pd",
-                &format_args!("{}", self.bbpll_force_pd().bit()),
-            )
-            .field(
-                "bbpll_force_pu",
-                &format_args!("{}", self.bbpll_force_pu().bit()),
-            )
-            .field(
-                "xtl_force_pd",
-                &format_args!("{}", self.xtl_force_pd().bit()),
-            )
-            .field(
-                "xtl_force_pu",
-                &format_args!("{}", self.xtl_force_pu().bit()),
-            )
-            .field(
-                "xtl_en_wait",
-                &format_args!("{}", self.xtl_en_wait().bits()),
-            )
-            .field(
-                "xtl_force_iso",
-                &format_args!("{}", self.xtl_force_iso().bit()),
-            )
-            .field(
-                "pll_force_iso",
-                &format_args!("{}", self.pll_force_iso().bit()),
-            )
-            .field(
-                "analog_force_iso",
-                &format_args!("{}", self.analog_force_iso().bit()),
-            )
-            .field(
-                "xtl_force_noiso",
-                &format_args!("{}", self.xtl_force_noiso().bit()),
-            )
-            .field(
-                "pll_force_noiso",
-                &format_args!("{}", self.pll_force_noiso().bit()),
-            )
-            .field(
-                "analog_force_noiso",
-                &format_args!("{}", self.analog_force_noiso().bit()),
-            )
-            .field(
-                "dg_wrap_force_rst",
-                &format_args!("{}", self.dg_wrap_force_rst().bit()),
-            )
-            .field(
-                "dg_wrap_force_norst",
-                &format_args!("{}", self.dg_wrap_force_norst().bit()),
-            )
+            .field("sw_stall_appcpu_c0", &self.sw_stall_appcpu_c0())
+            .field("sw_stall_procpu_c0", &self.sw_stall_procpu_c0())
+            .field("bb_i2c_force_pd", &self.bb_i2c_force_pd())
+            .field("bb_i2c_force_pu", &self.bb_i2c_force_pu())
+            .field("bbpll_i2c_force_pd", &self.bbpll_i2c_force_pd())
+            .field("bbpll_i2c_force_pu", &self.bbpll_i2c_force_pu())
+            .field("bbpll_force_pd", &self.bbpll_force_pd())
+            .field("bbpll_force_pu", &self.bbpll_force_pu())
+            .field("xtl_force_pd", &self.xtl_force_pd())
+            .field("xtl_force_pu", &self.xtl_force_pu())
+            .field("xtl_en_wait", &self.xtl_en_wait())
+            .field("xtl_force_iso", &self.xtl_force_iso())
+            .field("pll_force_iso", &self.pll_force_iso())
+            .field("analog_force_iso", &self.analog_force_iso())
+            .field("xtl_force_noiso", &self.xtl_force_noiso())
+            .field("pll_force_noiso", &self.pll_force_noiso())
+            .field("analog_force_noiso", &self.analog_force_noiso())
+            .field("dg_wrap_force_rst", &self.dg_wrap_force_rst())
+            .field("dg_wrap_force_norst", &self.dg_wrap_force_norst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OPTIONS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/pad_hold.rs b/esp32s3/src/rtc_cntl/pad_hold.rs
index 7148fdf385..284332ba14 100644
--- a/esp32s3/src/rtc_cntl/pad_hold.rs
+++ b/esp32s3/src/rtc_cntl/pad_hold.rs
@@ -206,82 +206,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_HOLD")
-            .field(
-                "touch_pad0_hold",
-                &format_args!("{}", self.touch_pad0_hold().bit()),
-            )
-            .field(
-                "touch_pad1_hold",
-                &format_args!("{}", self.touch_pad1_hold().bit()),
-            )
-            .field(
-                "touch_pad2_hold",
-                &format_args!("{}", self.touch_pad2_hold().bit()),
-            )
-            .field(
-                "touch_pad3_hold",
-                &format_args!("{}", self.touch_pad3_hold().bit()),
-            )
-            .field(
-                "touch_pad4_hold",
-                &format_args!("{}", self.touch_pad4_hold().bit()),
-            )
-            .field(
-                "touch_pad5_hold",
-                &format_args!("{}", self.touch_pad5_hold().bit()),
-            )
-            .field(
-                "touch_pad6_hold",
-                &format_args!("{}", self.touch_pad6_hold().bit()),
-            )
-            .field(
-                "touch_pad7_hold",
-                &format_args!("{}", self.touch_pad7_hold().bit()),
-            )
-            .field(
-                "touch_pad8_hold",
-                &format_args!("{}", self.touch_pad8_hold().bit()),
-            )
-            .field(
-                "touch_pad9_hold",
-                &format_args!("{}", self.touch_pad9_hold().bit()),
-            )
-            .field(
-                "touch_pad10_hold",
-                &format_args!("{}", self.touch_pad10_hold().bit()),
-            )
-            .field(
-                "touch_pad11_hold",
-                &format_args!("{}", self.touch_pad11_hold().bit()),
-            )
-            .field(
-                "touch_pad12_hold",
-                &format_args!("{}", self.touch_pad12_hold().bit()),
-            )
-            .field(
-                "touch_pad13_hold",
-                &format_args!("{}", self.touch_pad13_hold().bit()),
-            )
-            .field(
-                "touch_pad14_hold",
-                &format_args!("{}", self.touch_pad14_hold().bit()),
-            )
-            .field("x32p_hold", &format_args!("{}", self.x32p_hold().bit()))
-            .field("x32n_hold", &format_args!("{}", self.x32n_hold().bit()))
-            .field("pdac1_hold", &format_args!("{}", self.pdac1_hold().bit()))
-            .field("pdac2_hold", &format_args!("{}", self.pdac2_hold().bit()))
-            .field("pad19_hold", &format_args!("{}", self.pad19_hold().bit()))
-            .field("pad20_hold", &format_args!("{}", self.pad20_hold().bit()))
-            .field("pad21_hold", &format_args!("{}", self.pad21_hold().bit()))
+            .field("touch_pad0_hold", &self.touch_pad0_hold())
+            .field("touch_pad1_hold", &self.touch_pad1_hold())
+            .field("touch_pad2_hold", &self.touch_pad2_hold())
+            .field("touch_pad3_hold", &self.touch_pad3_hold())
+            .field("touch_pad4_hold", &self.touch_pad4_hold())
+            .field("touch_pad5_hold", &self.touch_pad5_hold())
+            .field("touch_pad6_hold", &self.touch_pad6_hold())
+            .field("touch_pad7_hold", &self.touch_pad7_hold())
+            .field("touch_pad8_hold", &self.touch_pad8_hold())
+            .field("touch_pad9_hold", &self.touch_pad9_hold())
+            .field("touch_pad10_hold", &self.touch_pad10_hold())
+            .field("touch_pad11_hold", &self.touch_pad11_hold())
+            .field("touch_pad12_hold", &self.touch_pad12_hold())
+            .field("touch_pad13_hold", &self.touch_pad13_hold())
+            .field("touch_pad14_hold", &self.touch_pad14_hold())
+            .field("x32p_hold", &self.x32p_hold())
+            .field("x32n_hold", &self.x32n_hold())
+            .field("pdac1_hold", &self.pdac1_hold())
+            .field("pdac2_hold", &self.pdac2_hold())
+            .field("pad19_hold", &self.pad19_hold())
+            .field("pad20_hold", &self.pad20_hold())
+            .field("pad21_hold", &self.pad21_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_HOLD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - hold rtc pad0"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/pg_ctrl.rs b/esp32s3/src/rtc_cntl/pg_ctrl.rs
index 098d3f3f66..ff5ad87ab7 100644
--- a/esp32s3/src/rtc_cntl/pg_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/pg_ctrl.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PG_CTRL")
-            .field(
-                "power_glitch_dsense",
-                &format_args!("{}", self.power_glitch_dsense().bits()),
-            )
-            .field(
-                "power_glitch_force_pd",
-                &format_args!("{}", self.power_glitch_force_pd().bit()),
-            )
-            .field(
-                "power_glitch_force_pu",
-                &format_args!("{}", self.power_glitch_force_pu().bit()),
-            )
-            .field(
-                "power_glitch_efuse_sel",
-                &format_args!("{}", self.power_glitch_efuse_sel().bit()),
-            )
-            .field(
-                "power_glitch_en",
-                &format_args!("{}", self.power_glitch_en().bit()),
-            )
+            .field("power_glitch_dsense", &self.power_glitch_dsense())
+            .field("power_glitch_force_pd", &self.power_glitch_force_pd())
+            .field("power_glitch_force_pu", &self.power_glitch_force_pu())
+            .field("power_glitch_efuse_sel", &self.power_glitch_efuse_sel())
+            .field("power_glitch_en", &self.power_glitch_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PG_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 26:27 - GLITCH_DSENSE"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/pwc.rs b/esp32s3/src/rtc_cntl/pwc.rs
index 0ab919fb9e..4d088408df 100644
--- a/esp32s3/src/rtc_cntl/pwc.rs
+++ b/esp32s3/src/rtc_cntl/pwc.rs
@@ -152,64 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PWC")
-            .field(
-                "fastmem_force_noiso",
-                &format_args!("{}", self.fastmem_force_noiso().bit()),
-            )
-            .field(
-                "fastmem_force_iso",
-                &format_args!("{}", self.fastmem_force_iso().bit()),
-            )
-            .field(
-                "slowmem_force_noiso",
-                &format_args!("{}", self.slowmem_force_noiso().bit()),
-            )
-            .field(
-                "slowmem_force_iso",
-                &format_args!("{}", self.slowmem_force_iso().bit()),
-            )
-            .field("force_iso", &format_args!("{}", self.force_iso().bit()))
-            .field("force_noiso", &format_args!("{}", self.force_noiso().bit()))
-            .field(
-                "fastmem_folw_cpu",
-                &format_args!("{}", self.fastmem_folw_cpu().bit()),
-            )
-            .field(
-                "fastmem_force_lpd",
-                &format_args!("{}", self.fastmem_force_lpd().bit()),
-            )
-            .field(
-                "fastmem_force_lpu",
-                &format_args!("{}", self.fastmem_force_lpu().bit()),
-            )
-            .field(
-                "slowmem_folw_cpu",
-                &format_args!("{}", self.slowmem_folw_cpu().bit()),
-            )
-            .field(
-                "slowmem_force_lpd",
-                &format_args!("{}", self.slowmem_force_lpd().bit()),
-            )
-            .field(
-                "slowmem_force_lpu",
-                &format_args!("{}", self.slowmem_force_lpu().bit()),
-            )
-            .field("force_pd", &format_args!("{}", self.force_pd().bit()))
-            .field("force_pu", &format_args!("{}", self.force_pu().bit()))
-            .field("pd_en", &format_args!("{}", self.pd_en().bit()))
-            .field(
-                "pad_force_hold",
-                &format_args!("{}", self.pad_force_hold().bit()),
-            )
+            .field("fastmem_force_noiso", &self.fastmem_force_noiso())
+            .field("fastmem_force_iso", &self.fastmem_force_iso())
+            .field("slowmem_force_noiso", &self.slowmem_force_noiso())
+            .field("slowmem_force_iso", &self.slowmem_force_iso())
+            .field("force_iso", &self.force_iso())
+            .field("force_noiso", &self.force_noiso())
+            .field("fastmem_folw_cpu", &self.fastmem_folw_cpu())
+            .field("fastmem_force_lpd", &self.fastmem_force_lpd())
+            .field("fastmem_force_lpu", &self.fastmem_force_lpu())
+            .field("slowmem_folw_cpu", &self.slowmem_folw_cpu())
+            .field("slowmem_force_lpd", &self.slowmem_force_lpd())
+            .field("slowmem_force_lpu", &self.slowmem_force_lpu())
+            .field("force_pd", &self.force_pd())
+            .field("force_pu", &self.force_pu())
+            .field("pd_en", &self.pd_en())
+            .field("pad_force_hold", &self.pad_force_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PWC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Fast RTC memory force no ISO"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/regulator_drv_ctrl.rs b/esp32s3/src/rtc_cntl/regulator_drv_ctrl.rs
index 837233e6a6..2d69f132a1 100644
--- a/esp32s3/src/rtc_cntl/regulator_drv_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/regulator_drv_ctrl.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGULATOR_DRV_CTRL")
-            .field(
-                "regulator_drv_b_monitor",
-                &format_args!("{}", self.regulator_drv_b_monitor().bits()),
-            )
-            .field(
-                "regulator_drv_b_slp",
-                &format_args!("{}", self.regulator_drv_b_slp().bits()),
-            )
-            .field(
-                "dg_vdd_drv_b_slp",
-                &format_args!("{}", self.dg_vdd_drv_b_slp().bits()),
-            )
-            .field(
-                "dg_vdd_drv_b_monitor",
-                &format_args!("{}", self.dg_vdd_drv_b_monitor().bits()),
-            )
+            .field("regulator_drv_b_monitor", &self.regulator_drv_b_monitor())
+            .field("regulator_drv_b_slp", &self.regulator_drv_b_slp())
+            .field("dg_vdd_drv_b_slp", &self.dg_vdd_drv_b_slp())
+            .field("dg_vdd_drv_b_monitor", &self.dg_vdd_drv_b_monitor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGULATOR_DRV_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - No public"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/reset_state.rs b/esp32s3/src/rtc_cntl/reset_state.rs
index 90c0ae0a9f..a8793b4e73 100644
--- a/esp32s3/src/rtc_cntl/reset_state.rs
+++ b/esp32s3/src/rtc_cntl/reset_state.rs
@@ -112,63 +112,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESET_STATE")
-            .field(
-                "reset_cause_procpu",
-                &format_args!("{}", self.reset_cause_procpu().bits()),
-            )
-            .field(
-                "reset_cause_appcpu",
-                &format_args!("{}", self.reset_cause_appcpu().bits()),
-            )
-            .field(
-                "appcpu_stat_vector_sel",
-                &format_args!("{}", self.appcpu_stat_vector_sel().bit()),
-            )
-            .field(
-                "procpu_stat_vector_sel",
-                &format_args!("{}", self.procpu_stat_vector_sel().bit()),
-            )
-            .field(
-                "reset_flag_procpu",
-                &format_args!("{}", self.reset_flag_procpu().bit()),
-            )
-            .field(
-                "reset_flag_appcpu",
-                &format_args!("{}", self.reset_flag_appcpu().bit()),
-            )
-            .field(
-                "appcpu_ocd_halt_on_reset",
-                &format_args!("{}", self.appcpu_ocd_halt_on_reset().bit()),
-            )
-            .field(
-                "procpu_ocd_halt_on_reset",
-                &format_args!("{}", self.procpu_ocd_halt_on_reset().bit()),
-            )
-            .field(
-                "reset_flag_jtag_procpu",
-                &format_args!("{}", self.reset_flag_jtag_procpu().bit()),
-            )
-            .field(
-                "reset_flag_jtag_appcpu",
-                &format_args!("{}", self.reset_flag_jtag_appcpu().bit()),
-            )
-            .field(
-                "app_dreset_mask",
-                &format_args!("{}", self.app_dreset_mask().bit()),
-            )
-            .field(
-                "pro_dreset_mask",
-                &format_args!("{}", self.pro_dreset_mask().bit()),
-            )
+            .field("reset_cause_procpu", &self.reset_cause_procpu())
+            .field("reset_cause_appcpu", &self.reset_cause_appcpu())
+            .field("appcpu_stat_vector_sel", &self.appcpu_stat_vector_sel())
+            .field("procpu_stat_vector_sel", &self.procpu_stat_vector_sel())
+            .field("reset_flag_procpu", &self.reset_flag_procpu())
+            .field("reset_flag_appcpu", &self.reset_flag_appcpu())
+            .field("appcpu_ocd_halt_on_reset", &self.appcpu_ocd_halt_on_reset())
+            .field("procpu_ocd_halt_on_reset", &self.procpu_ocd_halt_on_reset())
+            .field("reset_flag_jtag_procpu", &self.reset_flag_jtag_procpu())
+            .field("reset_flag_jtag_appcpu", &self.reset_flag_jtag_appcpu())
+            .field("app_dreset_mask", &self.app_dreset_mask())
+            .field("pro_dreset_mask", &self.pro_dreset_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESET_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - APP CPU state vector sel"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/retention_ctrl.rs b/esp32s3/src/rtc_cntl/retention_ctrl.rs
index c238eff1fd..fe695111bd 100644
--- a/esp32s3/src/rtc_cntl/retention_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/retention_ctrl.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_CTRL")
-            .field(
-                "retention_tag_mode",
-                &format_args!("{}", self.retention_tag_mode().bits()),
-            )
-            .field(
-                "retention_target",
-                &format_args!("{}", self.retention_target().bits()),
-            )
-            .field(
-                "retention_clk_sel",
-                &format_args!("{}", self.retention_clk_sel().bit()),
-            )
-            .field(
-                "retention_done_wait",
-                &format_args!("{}", self.retention_done_wait().bits()),
-            )
-            .field(
-                "retention_clkoff_wait",
-                &format_args!("{}", self.retention_clkoff_wait().bits()),
-            )
-            .field(
-                "retention_en",
-                &format_args!("{}", self.retention_en().bit()),
-            )
-            .field(
-                "retention_wait",
-                &format_args!("{}", self.retention_wait().bits()),
-            )
+            .field("retention_tag_mode", &self.retention_tag_mode())
+            .field("retention_target", &self.retention_target())
+            .field("retention_clk_sel", &self.retention_clk_sel())
+            .field("retention_done_wait", &self.retention_done_wait())
+            .field("retention_clkoff_wait", &self.retention_clkoff_wait())
+            .field("retention_en", &self.retention_en())
+            .field("retention_wait", &self.retention_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 10:13 - No public"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/rtc.rs b/esp32s3/src/rtc_cntl/rtc.rs
index 83e1588a7a..cbdbcfd2d0 100644
--- a/esp32s3/src/rtc_cntl/rtc.rs
+++ b/esp32s3/src/rtc_cntl/rtc.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC")
-            .field(
-                "dig_reg_cal_en",
-                &format_args!("{}", self.dig_reg_cal_en().bit()),
-            )
-            .field("sck_dcap", &format_args!("{}", self.sck_dcap().bits()))
-            .field(
-                "dboost_force_pd",
-                &format_args!("{}", self.dboost_force_pd().bit()),
-            )
-            .field(
-                "dboost_force_pu",
-                &format_args!("{}", self.dboost_force_pu().bit()),
-            )
-            .field(
-                "regulator_force_pd",
-                &format_args!("{}", self.regulator_force_pd().bit()),
-            )
-            .field(
-                "regulator_force_pu",
-                &format_args!("{}", self.regulator_force_pu().bit()),
-            )
+            .field("dig_reg_cal_en", &self.dig_reg_cal_en())
+            .field("sck_dcap", &self.sck_dcap())
+            .field("dboost_force_pd", &self.dboost_force_pd())
+            .field("dboost_force_pu", &self.dboost_force_pu())
+            .field("regulator_force_pd", &self.regulator_force_pd())
+            .field("regulator_force_pu", &self.regulator_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - enable dig regulator cali"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/sdio_act_conf.rs b/esp32s3/src/rtc_cntl/sdio_act_conf.rs
index 2a8d3a8174..12905d09e7 100644
--- a/esp32s3/src/rtc_cntl/sdio_act_conf.rs
+++ b/esp32s3/src/rtc_cntl/sdio_act_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_ACT_CONF")
-            .field(
-                "sdio_act_dnum",
-                &format_args!("{}", self.sdio_act_dnum().bits()),
-            )
+            .field("sdio_act_dnum", &self.sdio_act_dnum())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_ACT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 22:31 - No public"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/sdio_conf.rs b/esp32s3/src/rtc_cntl/sdio_conf.rs
index 7e439f8831..6f61f336f6 100644
--- a/esp32s3/src/rtc_cntl/sdio_conf.rs
+++ b/esp32s3/src/rtc_cntl/sdio_conf.rs
@@ -150,55 +150,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDIO_CONF")
-            .field(
-                "sdio_timer_target",
-                &format_args!("{}", self.sdio_timer_target().bits()),
-            )
-            .field(
-                "sdio_dthdrv",
-                &format_args!("{}", self.sdio_dthdrv().bits()),
-            )
-            .field("sdio_dcap", &format_args!("{}", self.sdio_dcap().bits()))
-            .field("sdio_initi", &format_args!("{}", self.sdio_initi().bits()))
-            .field(
-                "sdio_en_initi",
-                &format_args!("{}", self.sdio_en_initi().bit()),
-            )
-            .field(
-                "sdio_dcurlim",
-                &format_args!("{}", self.sdio_dcurlim().bits()),
-            )
-            .field(
-                "sdio_modecurlim",
-                &format_args!("{}", self.sdio_modecurlim().bit()),
-            )
-            .field(
-                "sdio_encurlim",
-                &format_args!("{}", self.sdio_encurlim().bit()),
-            )
-            .field(
-                "sdio_reg_pd_en",
-                &format_args!("{}", self.sdio_reg_pd_en().bit()),
-            )
-            .field("sdio_force", &format_args!("{}", self.sdio_force().bit()))
-            .field("sdio_tieh", &format_args!("{}", self.sdio_tieh().bit()))
-            .field(
-                "reg1p8_ready",
-                &format_args!("{}", self.reg1p8_ready().bit()),
-            )
-            .field("drefl_sdio", &format_args!("{}", self.drefl_sdio().bits()))
-            .field("drefm_sdio", &format_args!("{}", self.drefm_sdio().bits()))
-            .field("drefh_sdio", &format_args!("{}", self.drefh_sdio().bits()))
-            .field("xpd_sdio", &format_args!("{}", self.xpd_sdio().bit()))
+            .field("sdio_timer_target", &self.sdio_timer_target())
+            .field("sdio_dthdrv", &self.sdio_dthdrv())
+            .field("sdio_dcap", &self.sdio_dcap())
+            .field("sdio_initi", &self.sdio_initi())
+            .field("sdio_en_initi", &self.sdio_en_initi())
+            .field("sdio_dcurlim", &self.sdio_dcurlim())
+            .field("sdio_modecurlim", &self.sdio_modecurlim())
+            .field("sdio_encurlim", &self.sdio_encurlim())
+            .field("sdio_reg_pd_en", &self.sdio_reg_pd_en())
+            .field("sdio_force", &self.sdio_force())
+            .field("sdio_tieh", &self.sdio_tieh())
+            .field("reg1p8_ready", &self.reg1p8_ready())
+            .field("drefl_sdio", &self.drefl_sdio())
+            .field("drefm_sdio", &self.drefm_sdio())
+            .field("drefh_sdio", &self.drefh_sdio())
+            .field("xpd_sdio", &self.xpd_sdio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDIO_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - timer count to apply reg_sdio_dcap after sdio power on"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/slow_clk_conf.rs b/esp32s3/src/rtc_cntl/slow_clk_conf.rs
index 42b01d7494..1d51f2bd59 100644
--- a/esp32s3/src/rtc_cntl/slow_clk_conf.rs
+++ b/esp32s3/src/rtc_cntl/slow_clk_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLOW_CLK_CONF")
-            .field(
-                "ana_clk_div_vld",
-                &format_args!("{}", self.ana_clk_div_vld().bit()),
-            )
-            .field(
-                "ana_clk_div",
-                &format_args!("{}", self.ana_clk_div().bits()),
-            )
-            .field(
-                "slow_clk_next_edge",
-                &format_args!("{}", self.slow_clk_next_edge().bit()),
-            )
+            .field("ana_clk_div_vld", &self.ana_clk_div_vld())
+            .field("ana_clk_div", &self.ana_clk_div())
+            .field("slow_clk_next_edge", &self.slow_clk_next_edge())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLOW_CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 22 - used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to actually switch the clk"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/slp_reject_cause.rs b/esp32s3/src/rtc_cntl/slp_reject_cause.rs
index 20766163d2..c27474454b 100644
--- a/esp32s3/src/rtc_cntl/slp_reject_cause.rs
+++ b/esp32s3/src/rtc_cntl/slp_reject_cause.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_REJECT_CAUSE")
-            .field(
-                "reject_cause",
-                &format_args!("{}", self.reject_cause().bits()),
-            )
+            .field("reject_cause", &self.reject_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_REJECT_CAUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "get reject casue\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_reject_cause::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLP_REJECT_CAUSE_SPEC;
 impl crate::RegisterSpec for SLP_REJECT_CAUSE_SPEC {
diff --git a/esp32s3/src/rtc_cntl/slp_reject_conf.rs b/esp32s3/src/rtc_cntl/slp_reject_conf.rs
index 16d072ce71..3b91a39604 100644
--- a/esp32s3/src/rtc_cntl/slp_reject_conf.rs
+++ b/esp32s3/src/rtc_cntl/slp_reject_conf.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_REJECT_CONF")
-            .field(
-                "sleep_reject_ena",
-                &format_args!("{}", self.sleep_reject_ena().bits()),
-            )
-            .field(
-                "light_slp_reject_en",
-                &format_args!("{}", self.light_slp_reject_en().bit()),
-            )
-            .field(
-                "deep_slp_reject_en",
-                &format_args!("{}", self.deep_slp_reject_en().bit()),
-            )
+            .field("sleep_reject_ena", &self.sleep_reject_ena())
+            .field("light_slp_reject_en", &self.light_slp_reject_en())
+            .field("deep_slp_reject_en", &self.deep_slp_reject_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_REJECT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 12:29 - sleep reject enable"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/slp_timer0.rs b/esp32s3/src/rtc_cntl/slp_timer0.rs
index 573680eece..a181bc4b10 100644
--- a/esp32s3/src/rtc_cntl/slp_timer0.rs
+++ b/esp32s3/src/rtc_cntl/slp_timer0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_TIMER0")
-            .field("slp_val_lo", &format_args!("{}", self.slp_val_lo().bits()))
+            .field("slp_val_lo", &self.slp_val_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_TIMER0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - RTC sleep timer low 32 bits"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/slp_timer1.rs b/esp32s3/src/rtc_cntl/slp_timer1.rs
index 456db5d056..7ce4ca93f3 100644
--- a/esp32s3/src/rtc_cntl/slp_timer1.rs
+++ b/esp32s3/src/rtc_cntl/slp_timer1.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_TIMER1")
-            .field("slp_val_hi", &format_args!("{}", self.slp_val_hi().bits()))
+            .field("slp_val_hi", &self.slp_val_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_TIMER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - RTC sleep timer high 16 bits"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/slp_wakeup_cause.rs b/esp32s3/src/rtc_cntl/slp_wakeup_cause.rs
index 04c70dd9d0..525a4e71ee 100644
--- a/esp32s3/src/rtc_cntl/slp_wakeup_cause.rs
+++ b/esp32s3/src/rtc_cntl/slp_wakeup_cause.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLP_WAKEUP_CAUSE")
-            .field(
-                "wakeup_cause",
-                &format_args!("{}", self.wakeup_cause().bits()),
-            )
+            .field("wakeup_cause", &self.wakeup_cause())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLP_WAKEUP_CAUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "get wakeup cause\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slp_wakeup_cause::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SLP_WAKEUP_CAUSE_SPEC;
 impl crate::RegisterSpec for SLP_WAKEUP_CAUSE_SPEC {
diff --git a/esp32s3/src/rtc_cntl/state0.rs b/esp32s3/src/rtc_cntl/state0.rs
index 821fbb0cbf..77af705724 100644
--- a/esp32s3/src/rtc_cntl/state0.rs
+++ b/esp32s3/src/rtc_cntl/state0.rs
@@ -55,26 +55,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE0")
-            .field(
-                "apb2rtc_bridge_sel",
-                &format_args!("{}", self.apb2rtc_bridge_sel().bit()),
-            )
-            .field(
-                "sdio_active_ind",
-                &format_args!("{}", self.sdio_active_ind().bit()),
-            )
-            .field("slp_wakeup", &format_args!("{}", self.slp_wakeup().bit()))
-            .field("slp_reject", &format_args!("{}", self.slp_reject().bit()))
-            .field("sleep_en", &format_args!("{}", self.sleep_en().bit()))
+            .field("apb2rtc_bridge_sel", &self.apb2rtc_bridge_sel())
+            .field("sdio_active_ind", &self.sdio_active_ind())
+            .field("slp_wakeup", &self.slp_wakeup())
+            .field("slp_reject", &self.slp_reject())
+            .field("sleep_en", &self.sleep_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - rtc software interrupt to main cpu"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/store0.rs b/esp32s3/src/rtc_cntl/store0.rs
index d526fdb407..a23e828ece 100644
--- a/esp32s3/src/rtc_cntl/store0.rs
+++ b/esp32s3/src/rtc_cntl/store0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE0")
-            .field("scratch0", &format_args!("{}", self.scratch0().bits()))
+            .field("scratch0", &self.scratch0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved register"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/store1.rs b/esp32s3/src/rtc_cntl/store1.rs
index c6ba221ccb..1552859ce1 100644
--- a/esp32s3/src/rtc_cntl/store1.rs
+++ b/esp32s3/src/rtc_cntl/store1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE1")
-            .field("scratch1", &format_args!("{}", self.scratch1().bits()))
+            .field("scratch1", &self.scratch1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved register"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/store2.rs b/esp32s3/src/rtc_cntl/store2.rs
index db79128afe..1eef4c72c5 100644
--- a/esp32s3/src/rtc_cntl/store2.rs
+++ b/esp32s3/src/rtc_cntl/store2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE2")
-            .field("scratch2", &format_args!("{}", self.scratch2().bits()))
+            .field("scratch2", &self.scratch2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved register"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/store3.rs b/esp32s3/src/rtc_cntl/store3.rs
index 301bff79a5..9ddf211f83 100644
--- a/esp32s3/src/rtc_cntl/store3.rs
+++ b/esp32s3/src/rtc_cntl/store3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE3")
-            .field("scratch3", &format_args!("{}", self.scratch3().bits()))
+            .field("scratch3", &self.scratch3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Reserved register"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/store4.rs b/esp32s3/src/rtc_cntl/store4.rs
index 2369d08e7a..7e2be65655 100644
--- a/esp32s3/src/rtc_cntl/store4.rs
+++ b/esp32s3/src/rtc_cntl/store4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE4")
-            .field("scratch4", &format_args!("{}", self.scratch4().bits()))
+            .field("scratch4", &self.scratch4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/store5.rs b/esp32s3/src/rtc_cntl/store5.rs
index f43b4e576e..c23d7bbb5b 100644
--- a/esp32s3/src/rtc_cntl/store5.rs
+++ b/esp32s3/src/rtc_cntl/store5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE5")
-            .field("scratch5", &format_args!("{}", self.scratch5().bits()))
+            .field("scratch5", &self.scratch5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/store6.rs b/esp32s3/src/rtc_cntl/store6.rs
index e0c6cc5a45..05946d564c 100644
--- a/esp32s3/src/rtc_cntl/store6.rs
+++ b/esp32s3/src/rtc_cntl/store6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE6")
-            .field("scratch6", &format_args!("{}", self.scratch6().bits()))
+            .field("scratch6", &self.scratch6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/store7.rs b/esp32s3/src/rtc_cntl/store7.rs
index 8e754b9477..38de9f2294 100644
--- a/esp32s3/src/rtc_cntl/store7.rs
+++ b/esp32s3/src/rtc_cntl/store7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STORE7")
-            .field("scratch7", &format_args!("{}", self.scratch7().bits()))
+            .field("scratch7", &self.scratch7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STORE7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - reserved register"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/sw_cpu_stall.rs b/esp32s3/src/rtc_cntl/sw_cpu_stall.rs
index 480b30189b..79b3e23642 100644
--- a/esp32s3/src/rtc_cntl/sw_cpu_stall.rs
+++ b/esp32s3/src/rtc_cntl/sw_cpu_stall.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SW_CPU_STALL")
-            .field(
-                "sw_stall_appcpu_c1",
-                &format_args!("{}", self.sw_stall_appcpu_c1().bits()),
-            )
-            .field(
-                "sw_stall_procpu_c1",
-                &format_args!("{}", self.sw_stall_procpu_c1().bits()),
-            )
+            .field("sw_stall_appcpu_c1", &self.sw_stall_appcpu_c1())
+            .field("sw_stall_procpu_c1", &self.sw_stall_procpu_c1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SW_CPU_STALL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 20:25 - {reg_sw_stall_appcpu_c1\\[5:0\\], reg_sw_stall_appcpu_c0\\[1:0\\]} == 0x86 will stall APP CPU"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/swd_conf.rs b/esp32s3/src/rtc_cntl/swd_conf.rs
index 592221f0d4..0b49089551 100644
--- a/esp32s3/src/rtc_cntl/swd_conf.rs
+++ b/esp32s3/src/rtc_cntl/swd_conf.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_CONF")
-            .field(
-                "swd_reset_flag",
-                &format_args!("{}", self.swd_reset_flag().bit()),
-            )
-            .field(
-                "swd_feed_int",
-                &format_args!("{}", self.swd_feed_int().bit()),
-            )
-            .field(
-                "swd_bypass_rst",
-                &format_args!("{}", self.swd_bypass_rst().bit()),
-            )
-            .field(
-                "swd_signal_width",
-                &format_args!("{}", self.swd_signal_width().bits()),
-            )
-            .field("swd_disable", &format_args!("{}", self.swd_disable().bit()))
-            .field(
-                "swd_auto_feed_en",
-                &format_args!("{}", self.swd_auto_feed_en().bit()),
-            )
+            .field("swd_reset_flag", &self.swd_reset_flag())
+            .field("swd_feed_int", &self.swd_feed_int())
+            .field("swd_bypass_rst", &self.swd_bypass_rst())
+            .field("swd_signal_width", &self.swd_signal_width())
+            .field("swd_disable", &self.swd_disable())
+            .field("swd_auto_feed_en", &self.swd_auto_feed_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - bypass super watch dog reset"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/swd_wprotect.rs b/esp32s3/src/rtc_cntl/swd_wprotect.rs
index 25d03f968f..938d5cc7c4 100644
--- a/esp32s3/src/rtc_cntl/swd_wprotect.rs
+++ b/esp32s3/src/rtc_cntl/swd_wprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWD_WPROTECT")
-            .field("swd_wkey", &format_args!("{}", self.swd_wkey().bits()))
+            .field("swd_wkey", &self.swd_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWD_WPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - super watch dog key"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/time_high0.rs b/esp32s3/src/rtc_cntl/time_high0.rs
index c5ff06eea2..830ca11c31 100644
--- a/esp32s3/src/rtc_cntl/time_high0.rs
+++ b/esp32s3/src/rtc_cntl/time_high0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_HIGH0")
-            .field(
-                "timer_value0_high",
-                &format_args!("{}", self.timer_value0_high().bits()),
-            )
+            .field("timer_value0_high", &self.timer_value0_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_HIGH0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "read rtc_main timer high bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_high0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIME_HIGH0_SPEC;
 impl crate::RegisterSpec for TIME_HIGH0_SPEC {
diff --git a/esp32s3/src/rtc_cntl/time_high1.rs b/esp32s3/src/rtc_cntl/time_high1.rs
index 8d65cff0b6..52f2fcc5a0 100644
--- a/esp32s3/src/rtc_cntl/time_high1.rs
+++ b/esp32s3/src/rtc_cntl/time_high1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_HIGH1")
-            .field(
-                "timer_value1_high",
-                &format_args!("{}", self.timer_value1_high().bits()),
-            )
+            .field("timer_value1_high", &self.timer_value1_high())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_HIGH1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC timer high 16 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_high1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIME_HIGH1_SPEC;
 impl crate::RegisterSpec for TIME_HIGH1_SPEC {
diff --git a/esp32s3/src/rtc_cntl/time_low0.rs b/esp32s3/src/rtc_cntl/time_low0.rs
index 6c649bf986..76f4e7c444 100644
--- a/esp32s3/src/rtc_cntl/time_low0.rs
+++ b/esp32s3/src/rtc_cntl/time_low0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_LOW0")
-            .field(
-                "timer_value0_low",
-                &format_args!("{}", self.timer_value0_low().bits()),
-            )
+            .field("timer_value0_low", &self.timer_value0_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_LOW0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "read rtc_main timer low bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_low0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIME_LOW0_SPEC;
 impl crate::RegisterSpec for TIME_LOW0_SPEC {
diff --git a/esp32s3/src/rtc_cntl/time_low1.rs b/esp32s3/src/rtc_cntl/time_low1.rs
index fc889593a9..c2e57359e0 100644
--- a/esp32s3/src/rtc_cntl/time_low1.rs
+++ b/esp32s3/src/rtc_cntl/time_low1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_LOW1")
-            .field(
-                "timer_value1_low",
-                &format_args!("{}", self.timer_value1_low().bits()),
-            )
+            .field("timer_value1_low", &self.timer_value1_low())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_LOW1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC timer low 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_low1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TIME_LOW1_SPEC;
 impl crate::RegisterSpec for TIME_LOW1_SPEC {
diff --git a/esp32s3/src/rtc_cntl/time_update.rs b/esp32s3/src/rtc_cntl/time_update.rs
index 12dadbf151..eabfbf430d 100644
--- a/esp32s3/src/rtc_cntl/time_update.rs
+++ b/esp32s3/src/rtc_cntl/time_update.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIME_UPDATE")
-            .field(
-                "timer_sys_stall",
-                &format_args!("{}", self.timer_sys_stall().bit()),
-            )
-            .field(
-                "timer_xtl_off",
-                &format_args!("{}", self.timer_xtl_off().bit()),
-            )
-            .field(
-                "timer_sys_rst",
-                &format_args!("{}", self.timer_sys_rst().bit()),
-            )
+            .field("timer_sys_stall", &self.timer_sys_stall())
+            .field("timer_xtl_off", &self.timer_xtl_off())
+            .field("timer_sys_rst", &self.timer_sys_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIME_UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - Enable to record system stall time"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/timer1.rs b/esp32s3/src/rtc_cntl/timer1.rs
index 12c1802671..2911e3d8a2 100644
--- a/esp32s3/src/rtc_cntl/timer1.rs
+++ b/esp32s3/src/rtc_cntl/timer1.rs
@@ -53,32 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER1")
-            .field(
-                "cpu_stall_en",
-                &format_args!("{}", self.cpu_stall_en().bit()),
-            )
-            .field(
-                "cpu_stall_wait",
-                &format_args!("{}", self.cpu_stall_wait().bits()),
-            )
-            .field("ck8m_wait", &format_args!("{}", self.ck8m_wait().bits()))
-            .field(
-                "xtl_buf_wait",
-                &format_args!("{}", self.xtl_buf_wait().bits()),
-            )
-            .field(
-                "pll_buf_wait",
-                &format_args!("{}", self.pll_buf_wait().bits()),
-            )
+            .field("cpu_stall_en", &self.cpu_stall_en())
+            .field("cpu_stall_wait", &self.cpu_stall_wait())
+            .field("ck8m_wait", &self.ck8m_wait())
+            .field("xtl_buf_wait", &self.xtl_buf_wait())
+            .field("pll_buf_wait", &self.pll_buf_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - CPU stall enable bit"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/timer2.rs b/esp32s3/src/rtc_cntl/timer2.rs
index 233853ac13..972fea72e2 100644
--- a/esp32s3/src/rtc_cntl/timer2.rs
+++ b/esp32s3/src/rtc_cntl/timer2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER2")
-            .field(
-                "ulpcp_touch_start_wait",
-                &format_args!("{}", self.ulpcp_touch_start_wait().bits()),
-            )
-            .field(
-                "min_time_ck8m_off",
-                &format_args!("{}", self.min_time_ck8m_off().bits()),
-            )
+            .field("ulpcp_touch_start_wait", &self.ulpcp_touch_start_wait())
+            .field("min_time_ck8m_off", &self.min_time_ck8m_off())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 15:23 - wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/timer3.rs b/esp32s3/src/rtc_cntl/timer3.rs
index 2e6435d073..3854c652a7 100644
--- a/esp32s3/src/rtc_cntl/timer3.rs
+++ b/esp32s3/src/rtc_cntl/timer3.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER3")
-            .field(
-                "wifi_wait_timer",
-                &format_args!("{}", self.wifi_wait_timer().bits()),
-            )
-            .field(
-                "wifi_powerup_timer",
-                &format_args!("{}", self.wifi_powerup_timer().bits()),
-            )
-            .field(
-                "bt_wait_timer",
-                &format_args!("{}", self.bt_wait_timer().bits()),
-            )
-            .field(
-                "bt_powerup_timer",
-                &format_args!("{}", self.bt_powerup_timer().bits()),
-            )
+            .field("wifi_wait_timer", &self.wifi_wait_timer())
+            .field("wifi_powerup_timer", &self.wifi_powerup_timer())
+            .field("bt_wait_timer", &self.bt_wait_timer())
+            .field("bt_powerup_timer", &self.bt_powerup_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - No public"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/timer4.rs b/esp32s3/src/rtc_cntl/timer4.rs
index 5d875d5465..906fa63193 100644
--- a/esp32s3/src/rtc_cntl/timer4.rs
+++ b/esp32s3/src/rtc_cntl/timer4.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER4")
-            .field("wait_timer", &format_args!("{}", self.wait_timer().bits()))
-            .field(
-                "powerup_timer",
-                &format_args!("{}", self.powerup_timer().bits()),
-            )
-            .field(
-                "dg_wrap_wait_timer",
-                &format_args!("{}", self.dg_wrap_wait_timer().bits()),
-            )
-            .field(
-                "dg_wrap_powerup_timer",
-                &format_args!("{}", self.dg_wrap_powerup_timer().bits()),
-            )
+            .field("wait_timer", &self.wait_timer())
+            .field("powerup_timer", &self.powerup_timer())
+            .field("dg_wrap_wait_timer", &self.dg_wrap_wait_timer())
+            .field("dg_wrap_powerup_timer", &self.dg_wrap_powerup_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - No public"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/timer5.rs b/esp32s3/src/rtc_cntl/timer5.rs
index 57e7ccc25a..db945dca66 100644
--- a/esp32s3/src/rtc_cntl/timer5.rs
+++ b/esp32s3/src/rtc_cntl/timer5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER5")
-            .field(
-                "min_slp_val",
-                &format_args!("{}", self.min_slp_val().bits()),
-            )
+            .field("min_slp_val", &self.min_slp_val())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:15 - minimal sleep cycles in slow_clk_rtc"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/timer6.rs b/esp32s3/src/rtc_cntl/timer6.rs
index 01c01e6e64..7d14b27867 100644
--- a/esp32s3/src/rtc_cntl/timer6.rs
+++ b/esp32s3/src/rtc_cntl/timer6.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMER6")
-            .field(
-                "cpu_top_wait_timer",
-                &format_args!("{}", self.cpu_top_wait_timer().bits()),
-            )
-            .field(
-                "cpu_top_powerup_timer",
-                &format_args!("{}", self.cpu_top_powerup_timer().bits()),
-            )
-            .field(
-                "dg_peri_wait_timer",
-                &format_args!("{}", self.dg_peri_wait_timer().bits()),
-            )
-            .field(
-                "dg_peri_powerup_timer",
-                &format_args!("{}", self.dg_peri_powerup_timer().bits()),
-            )
+            .field("cpu_top_wait_timer", &self.cpu_top_wait_timer())
+            .field("cpu_top_powerup_timer", &self.cpu_top_powerup_timer())
+            .field("dg_peri_wait_timer", &self.dg_peri_wait_timer())
+            .field("dg_peri_powerup_timer", &self.dg_peri_powerup_timer())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMER6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:8 - No public"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/touch_approach.rs b/esp32s3/src/rtc_cntl/touch_approach.rs
index db37bfab64..e284338433 100644
--- a/esp32s3/src/rtc_cntl/touch_approach.rs
+++ b/esp32s3/src/rtc_cntl/touch_approach.rs
@@ -19,19 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_APPROACH")
-            .field(
-                "touch_approach_meas_time",
-                &format_args!("{}", self.touch_approach_meas_time().bits()),
-            )
+            .field("touch_approach_meas_time", &self.touch_approach_meas_time())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_APPROACH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 23 - clear touch slp channel"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/touch_ctrl1.rs b/esp32s3/src/rtc_cntl/touch_ctrl1.rs
index 28158c0f68..fb0939d147 100644
--- a/esp32s3/src/rtc_cntl/touch_ctrl1.rs
+++ b/esp32s3/src/rtc_cntl/touch_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_CTRL1")
-            .field(
-                "touch_sleep_cycles",
-                &format_args!("{}", self.touch_sleep_cycles().bits()),
-            )
-            .field(
-                "touch_meas_num",
-                &format_args!("{}", self.touch_meas_num().bits()),
-            )
+            .field("touch_sleep_cycles", &self.touch_sleep_cycles())
+            .field("touch_meas_num", &self.touch_meas_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - sleep cycles for timer"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/touch_ctrl2.rs b/esp32s3/src/rtc_cntl/touch_ctrl2.rs
index 030002faf3..19ee334e01 100644
--- a/esp32s3/src/rtc_cntl/touch_ctrl2.rs
+++ b/esp32s3/src/rtc_cntl/touch_ctrl2.rs
@@ -152,70 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_CTRL2")
-            .field(
-                "touch_drange",
-                &format_args!("{}", self.touch_drange().bits()),
-            )
-            .field(
-                "touch_drefl",
-                &format_args!("{}", self.touch_drefl().bits()),
-            )
-            .field(
-                "touch_drefh",
-                &format_args!("{}", self.touch_drefh().bits()),
-            )
-            .field(
-                "touch_xpd_bias",
-                &format_args!("{}", self.touch_xpd_bias().bit()),
-            )
-            .field("touch_refc", &format_args!("{}", self.touch_refc().bits()))
-            .field("touch_dbias", &format_args!("{}", self.touch_dbias().bit()))
-            .field(
-                "touch_slp_timer_en",
-                &format_args!("{}", self.touch_slp_timer_en().bit()),
-            )
-            .field(
-                "touch_start_fsm_en",
-                &format_args!("{}", self.touch_start_fsm_en().bit()),
-            )
-            .field(
-                "touch_start_en",
-                &format_args!("{}", self.touch_start_en().bit()),
-            )
-            .field(
-                "touch_start_force",
-                &format_args!("{}", self.touch_start_force().bit()),
-            )
-            .field(
-                "touch_xpd_wait",
-                &format_args!("{}", self.touch_xpd_wait().bits()),
-            )
-            .field(
-                "touch_slp_cyc_div",
-                &format_args!("{}", self.touch_slp_cyc_div().bits()),
-            )
-            .field(
-                "touch_timer_force_done",
-                &format_args!("{}", self.touch_timer_force_done().bits()),
-            )
-            .field("touch_reset", &format_args!("{}", self.touch_reset().bit()))
-            .field(
-                "touch_clk_fo",
-                &format_args!("{}", self.touch_clk_fo().bit()),
-            )
-            .field(
-                "touch_clkgate_en",
-                &format_args!("{}", self.touch_clkgate_en().bit()),
-            )
+            .field("touch_drange", &self.touch_drange())
+            .field("touch_drefl", &self.touch_drefl())
+            .field("touch_drefh", &self.touch_drefh())
+            .field("touch_xpd_bias", &self.touch_xpd_bias())
+            .field("touch_refc", &self.touch_refc())
+            .field("touch_dbias", &self.touch_dbias())
+            .field("touch_slp_timer_en", &self.touch_slp_timer_en())
+            .field("touch_start_fsm_en", &self.touch_start_fsm_en())
+            .field("touch_start_en", &self.touch_start_en())
+            .field("touch_start_force", &self.touch_start_force())
+            .field("touch_xpd_wait", &self.touch_xpd_wait())
+            .field("touch_slp_cyc_div", &self.touch_slp_cyc_div())
+            .field("touch_timer_force_done", &self.touch_timer_force_done())
+            .field("touch_reset", &self.touch_reset())
+            .field("touch_clk_fo", &self.touch_clk_fo())
+            .field("touch_clkgate_en", &self.touch_clkgate_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 2:3 - TOUCH_DRANGE"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/touch_dac.rs b/esp32s3/src/rtc_cntl/touch_dac.rs
index 7a3b234230..0f0bfbaf83 100644
--- a/esp32s3/src/rtc_cntl/touch_dac.rs
+++ b/esp32s3/src/rtc_cntl/touch_dac.rs
@@ -98,55 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_DAC")
-            .field(
-                "touch_pad9_dac",
-                &format_args!("{}", self.touch_pad9_dac().bits()),
-            )
-            .field(
-                "touch_pad8_dac",
-                &format_args!("{}", self.touch_pad8_dac().bits()),
-            )
-            .field(
-                "touch_pad7_dac",
-                &format_args!("{}", self.touch_pad7_dac().bits()),
-            )
-            .field(
-                "touch_pad6_dac",
-                &format_args!("{}", self.touch_pad6_dac().bits()),
-            )
-            .field(
-                "touch_pad5_dac",
-                &format_args!("{}", self.touch_pad5_dac().bits()),
-            )
-            .field(
-                "touch_pad4_dac",
-                &format_args!("{}", self.touch_pad4_dac().bits()),
-            )
-            .field(
-                "touch_pad3_dac",
-                &format_args!("{}", self.touch_pad3_dac().bits()),
-            )
-            .field(
-                "touch_pad2_dac",
-                &format_args!("{}", self.touch_pad2_dac().bits()),
-            )
-            .field(
-                "touch_pad1_dac",
-                &format_args!("{}", self.touch_pad1_dac().bits()),
-            )
-            .field(
-                "touch_pad0_dac",
-                &format_args!("{}", self.touch_pad0_dac().bits()),
-            )
+            .field("touch_pad9_dac", &self.touch_pad9_dac())
+            .field("touch_pad8_dac", &self.touch_pad8_dac())
+            .field("touch_pad7_dac", &self.touch_pad7_dac())
+            .field("touch_pad6_dac", &self.touch_pad6_dac())
+            .field("touch_pad5_dac", &self.touch_pad5_dac())
+            .field("touch_pad4_dac", &self.touch_pad4_dac())
+            .field("touch_pad3_dac", &self.touch_pad3_dac())
+            .field("touch_pad2_dac", &self.touch_pad2_dac())
+            .field("touch_pad1_dac", &self.touch_pad1_dac())
+            .field("touch_pad0_dac", &self.touch_pad0_dac())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_DAC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 2:4 - configure touch pad dac9"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/touch_dac1.rs b/esp32s3/src/rtc_cntl/touch_dac1.rs
index bde8756dda..5742ac4c3c 100644
--- a/esp32s3/src/rtc_cntl/touch_dac1.rs
+++ b/esp32s3/src/rtc_cntl/touch_dac1.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_DAC1")
-            .field(
-                "touch_pad14_dac",
-                &format_args!("{}", self.touch_pad14_dac().bits()),
-            )
-            .field(
-                "touch_pad13_dac",
-                &format_args!("{}", self.touch_pad13_dac().bits()),
-            )
-            .field(
-                "touch_pad12_dac",
-                &format_args!("{}", self.touch_pad12_dac().bits()),
-            )
-            .field(
-                "touch_pad11_dac",
-                &format_args!("{}", self.touch_pad11_dac().bits()),
-            )
-            .field(
-                "touch_pad10_dac",
-                &format_args!("{}", self.touch_pad10_dac().bits()),
-            )
+            .field("touch_pad14_dac", &self.touch_pad14_dac())
+            .field("touch_pad13_dac", &self.touch_pad13_dac())
+            .field("touch_pad12_dac", &self.touch_pad12_dac())
+            .field("touch_pad11_dac", &self.touch_pad11_dac())
+            .field("touch_pad10_dac", &self.touch_pad10_dac())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_DAC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 17:19 - configure touch pad dac14"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/touch_filter_ctrl.rs b/esp32s3/src/rtc_cntl/touch_filter_ctrl.rs
index e22872bddb..c44b53d262 100644
--- a/esp32s3/src/rtc_cntl/touch_filter_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/touch_filter_ctrl.rs
@@ -109,57 +109,21 @@ impl core::fmt::Debug for R {
         f.debug_struct("TOUCH_FILTER_CTRL")
             .field(
                 "touch_bypass_neg_noise_thres",
-                &format_args!("{}", self.touch_bypass_neg_noise_thres().bit()),
-            )
-            .field(
-                "touch_bypass_noise_thres",
-                &format_args!("{}", self.touch_bypass_noise_thres().bit()),
-            )
-            .field(
-                "touch_smooth_lvl",
-                &format_args!("{}", self.touch_smooth_lvl().bits()),
-            )
-            .field(
-                "touch_jitter_step",
-                &format_args!("{}", self.touch_jitter_step().bits()),
-            )
-            .field(
-                "touch_neg_noise_limit",
-                &format_args!("{}", self.touch_neg_noise_limit().bits()),
-            )
-            .field(
-                "touch_neg_noise_thres",
-                &format_args!("{}", self.touch_neg_noise_thres().bits()),
-            )
-            .field(
-                "touch_noise_thres",
-                &format_args!("{}", self.touch_noise_thres().bits()),
-            )
-            .field(
-                "touch_hysteresis",
-                &format_args!("{}", self.touch_hysteresis().bits()),
-            )
-            .field(
-                "touch_debounce",
-                &format_args!("{}", self.touch_debounce().bits()),
-            )
-            .field(
-                "touch_filter_mode",
-                &format_args!("{}", self.touch_filter_mode().bits()),
-            )
-            .field(
-                "touch_filter_en",
-                &format_args!("{}", self.touch_filter_en().bit()),
+                &self.touch_bypass_neg_noise_thres(),
             )
+            .field("touch_bypass_noise_thres", &self.touch_bypass_noise_thres())
+            .field("touch_smooth_lvl", &self.touch_smooth_lvl())
+            .field("touch_jitter_step", &self.touch_jitter_step())
+            .field("touch_neg_noise_limit", &self.touch_neg_noise_limit())
+            .field("touch_neg_noise_thres", &self.touch_neg_noise_thres())
+            .field("touch_noise_thres", &self.touch_noise_thres())
+            .field("touch_hysteresis", &self.touch_hysteresis())
+            .field("touch_debounce", &self.touch_debounce())
+            .field("touch_filter_mode", &self.touch_filter_mode())
+            .field("touch_filter_en", &self.touch_filter_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_FILTER_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - bypass neg noise thres"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/touch_scan_ctrl.rs b/esp32s3/src/rtc_cntl/touch_scan_ctrl.rs
index eb5c0ff7d8..c3e3da114d 100644
--- a/esp32s3/src/rtc_cntl/touch_scan_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/touch_scan_ctrl.rs
@@ -71,43 +71,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_SCAN_CTRL")
-            .field(
-                "touch_denoise_res",
-                &format_args!("{}", self.touch_denoise_res().bits()),
-            )
-            .field(
-                "touch_denoise_en",
-                &format_args!("{}", self.touch_denoise_en().bit()),
-            )
+            .field("touch_denoise_res", &self.touch_denoise_res())
+            .field("touch_denoise_en", &self.touch_denoise_en())
             .field(
                 "touch_inactive_connection",
-                &format_args!("{}", self.touch_inactive_connection().bit()),
-            )
-            .field(
-                "touch_shield_pad_en",
-                &format_args!("{}", self.touch_shield_pad_en().bit()),
-            )
-            .field(
-                "touch_scan_pad_map",
-                &format_args!("{}", self.touch_scan_pad_map().bits()),
-            )
-            .field(
-                "touch_bufdrv",
-                &format_args!("{}", self.touch_bufdrv().bits()),
-            )
-            .field(
-                "touch_out_ring",
-                &format_args!("{}", self.touch_out_ring().bits()),
+                &self.touch_inactive_connection(),
             )
+            .field("touch_shield_pad_en", &self.touch_shield_pad_en())
+            .field("touch_scan_pad_map", &self.touch_scan_pad_map())
+            .field("touch_bufdrv", &self.touch_bufdrv())
+            .field("touch_out_ring", &self.touch_out_ring())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_SCAN_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - De-noise resolution: 12/10/8/4 bit"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/touch_slp_thres.rs b/esp32s3/src/rtc_cntl/touch_slp_thres.rs
index 227a7f136f..4394c34415 100644
--- a/esp32s3/src/rtc_cntl/touch_slp_thres.rs
+++ b/esp32s3/src/rtc_cntl/touch_slp_thres.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_SLP_THRES")
-            .field(
-                "touch_slp_th",
-                &format_args!("{}", self.touch_slp_th().bits()),
-            )
-            .field(
-                "touch_slp_approach_en",
-                &format_args!("{}", self.touch_slp_approach_en().bit()),
-            )
-            .field(
-                "touch_slp_pad",
-                &format_args!("{}", self.touch_slp_pad().bits()),
-            )
+            .field("touch_slp_th", &self.touch_slp_th())
+            .field("touch_slp_approach_en", &self.touch_slp_approach_en())
+            .field("touch_slp_pad", &self.touch_slp_pad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_SLP_THRES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - the threshold for sleep touch pad"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/touch_timeout_ctrl.rs b/esp32s3/src/rtc_cntl/touch_timeout_ctrl.rs
index 19b839cf0f..43f3cc78ec 100644
--- a/esp32s3/src/rtc_cntl/touch_timeout_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/touch_timeout_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_TIMEOUT_CTRL")
-            .field(
-                "touch_timeout_num",
-                &format_args!("{}", self.touch_timeout_num().bits()),
-            )
-            .field(
-                "touch_timeout_en",
-                &format_args!("{}", self.touch_timeout_en().bit()),
-            )
+            .field("touch_timeout_num", &self.touch_timeout_num())
+            .field("touch_timeout_en", &self.touch_timeout_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_TIMEOUT_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - configure touch timerout time"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/ulp_cp_ctrl.rs b/esp32s3/src/rtc_cntl/ulp_cp_ctrl.rs
index d65dfabb5c..f03433f1bb 100644
--- a/esp32s3/src/rtc_cntl/ulp_cp_ctrl.rs
+++ b/esp32s3/src/rtc_cntl/ulp_cp_ctrl.rs
@@ -64,39 +64,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_CTRL")
-            .field(
-                "ulp_cp_mem_addr_init",
-                &format_args!("{}", self.ulp_cp_mem_addr_init().bits()),
-            )
-            .field(
-                "ulp_cp_mem_addr_size",
-                &format_args!("{}", self.ulp_cp_mem_addr_size().bits()),
-            )
-            .field(
-                "ulp_cp_clk_fo",
-                &format_args!("{}", self.ulp_cp_clk_fo().bit()),
-            )
-            .field(
-                "ulp_cp_reset",
-                &format_args!("{}", self.ulp_cp_reset().bit()),
-            )
-            .field(
-                "ulp_cp_force_start_top",
-                &format_args!("{}", self.ulp_cp_force_start_top().bit()),
-            )
-            .field(
-                "ulp_cp_start_top",
-                &format_args!("{}", self.ulp_cp_start_top().bit()),
-            )
+            .field("ulp_cp_mem_addr_init", &self.ulp_cp_mem_addr_init())
+            .field("ulp_cp_mem_addr_size", &self.ulp_cp_mem_addr_size())
+            .field("ulp_cp_clk_fo", &self.ulp_cp_clk_fo())
+            .field("ulp_cp_reset", &self.ulp_cp_reset())
+            .field("ulp_cp_force_start_top", &self.ulp_cp_force_start_top())
+            .field("ulp_cp_start_top", &self.ulp_cp_start_top())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - No public"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/ulp_cp_timer.rs b/esp32s3/src/rtc_cntl/ulp_cp_timer.rs
index 199e4563d2..b6ffdbb4b1 100644
--- a/esp32s3/src/rtc_cntl/ulp_cp_timer.rs
+++ b/esp32s3/src/rtc_cntl/ulp_cp_timer.rs
@@ -37,27 +37,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_TIMER")
-            .field(
-                "ulp_cp_pc_init",
-                &format_args!("{}", self.ulp_cp_pc_init().bits()),
-            )
-            .field(
-                "ulp_cp_gpio_wakeup_ena",
-                &format_args!("{}", self.ulp_cp_gpio_wakeup_ena().bit()),
-            )
-            .field(
-                "ulp_cp_slp_timer_en",
-                &format_args!("{}", self.ulp_cp_slp_timer_en().bit()),
-            )
+            .field("ulp_cp_pc_init", &self.ulp_cp_pc_init())
+            .field("ulp_cp_gpio_wakeup_ena", &self.ulp_cp_gpio_wakeup_ena())
+            .field("ulp_cp_slp_timer_en", &self.ulp_cp_slp_timer_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_TIMER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - ULP-coprocessor PC initial address"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/ulp_cp_timer_1.rs b/esp32s3/src/rtc_cntl/ulp_cp_timer_1.rs
index fd63b19de5..33c906ea87 100644
--- a/esp32s3/src/rtc_cntl/ulp_cp_timer_1.rs
+++ b/esp32s3/src/rtc_cntl/ulp_cp_timer_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ULP_CP_TIMER_1")
-            .field(
-                "ulp_cp_timer_slp_cycle",
-                &format_args!("{}", self.ulp_cp_timer_slp_cycle().bits()),
-            )
+            .field("ulp_cp_timer_slp_cycle", &self.ulp_cp_timer_slp_cycle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ULP_CP_TIMER_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:31 - sleep cycles for ULP-coprocessor timer"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/usb_conf.rs b/esp32s3/src/rtc_cntl/usb_conf.rs
index 7646e17f23..563e1702db 100644
--- a/esp32s3/src/rtc_cntl/usb_conf.rs
+++ b/esp32s3/src/rtc_cntl/usb_conf.rs
@@ -179,76 +179,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USB_CONF")
-            .field("usb_vrefh", &format_args!("{}", self.usb_vrefh().bits()))
-            .field("usb_vrefl", &format_args!("{}", self.usb_vrefl().bits()))
-            .field(
-                "usb_vref_override",
-                &format_args!("{}", self.usb_vref_override().bit()),
-            )
-            .field(
-                "usb_pad_pull_override",
-                &format_args!("{}", self.usb_pad_pull_override().bit()),
-            )
-            .field(
-                "usb_dp_pullup",
-                &format_args!("{}", self.usb_dp_pullup().bit()),
-            )
-            .field(
-                "usb_dp_pulldown",
-                &format_args!("{}", self.usb_dp_pulldown().bit()),
-            )
-            .field(
-                "usb_dm_pullup",
-                &format_args!("{}", self.usb_dm_pullup().bit()),
-            )
-            .field(
-                "usb_dm_pulldown",
-                &format_args!("{}", self.usb_dm_pulldown().bit()),
-            )
-            .field(
-                "usb_pullup_value",
-                &format_args!("{}", self.usb_pullup_value().bit()),
-            )
-            .field(
-                "usb_pad_enable_override",
-                &format_args!("{}", self.usb_pad_enable_override().bit()),
-            )
-            .field(
-                "usb_pad_enable",
-                &format_args!("{}", self.usb_pad_enable().bit()),
-            )
-            .field("usb_txm", &format_args!("{}", self.usb_txm().bit()))
-            .field("usb_txp", &format_args!("{}", self.usb_txp().bit()))
-            .field("usb_tx_en", &format_args!("{}", self.usb_tx_en().bit()))
-            .field(
-                "usb_tx_en_override",
-                &format_args!("{}", self.usb_tx_en_override().bit()),
-            )
-            .field(
-                "usb_reset_disable",
-                &format_args!("{}", self.usb_reset_disable().bit()),
-            )
-            .field(
-                "io_mux_reset_disable",
-                &format_args!("{}", self.io_mux_reset_disable().bit()),
-            )
-            .field(
-                "sw_usb_phy_sel",
-                &format_args!("{}", self.sw_usb_phy_sel().bit()),
-            )
-            .field(
-                "sw_hw_usb_phy_sel",
-                &format_args!("{}", self.sw_hw_usb_phy_sel().bit()),
-            )
+            .field("usb_vrefh", &self.usb_vrefh())
+            .field("usb_vrefl", &self.usb_vrefl())
+            .field("usb_vref_override", &self.usb_vref_override())
+            .field("usb_pad_pull_override", &self.usb_pad_pull_override())
+            .field("usb_dp_pullup", &self.usb_dp_pullup())
+            .field("usb_dp_pulldown", &self.usb_dp_pulldown())
+            .field("usb_dm_pullup", &self.usb_dm_pullup())
+            .field("usb_dm_pulldown", &self.usb_dm_pulldown())
+            .field("usb_pullup_value", &self.usb_pullup_value())
+            .field("usb_pad_enable_override", &self.usb_pad_enable_override())
+            .field("usb_pad_enable", &self.usb_pad_enable())
+            .field("usb_txm", &self.usb_txm())
+            .field("usb_txp", &self.usb_txp())
+            .field("usb_tx_en", &self.usb_tx_en())
+            .field("usb_tx_en_override", &self.usb_tx_en_override())
+            .field("usb_reset_disable", &self.usb_reset_disable())
+            .field("io_mux_reset_disable", &self.io_mux_reset_disable())
+            .field("sw_usb_phy_sel", &self.sw_usb_phy_sel())
+            .field("sw_hw_usb_phy_sel", &self.sw_hw_usb_phy_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USB_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - reg_usb_vrefh"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/wakeup_state.rs b/esp32s3/src/rtc_cntl/wakeup_state.rs
index c5d4d3d4d9..72d58011a0 100644
--- a/esp32s3/src/rtc_cntl/wakeup_state.rs
+++ b/esp32s3/src/rtc_cntl/wakeup_state.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WAKEUP_STATE")
-            .field("wakeup_ena", &format_args!("{}", self.wakeup_ena().bits()))
+            .field("wakeup_ena", &self.wakeup_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WAKEUP_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 15:31 - wakeup enable bitmap"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/wdtconfig0.rs b/esp32s3/src/rtc_cntl/wdtconfig0.rs
index be23b589aa..014daab2a7 100644
--- a/esp32s3/src/rtc_cntl/wdtconfig0.rs
+++ b/esp32s3/src/rtc_cntl/wdtconfig0.rs
@@ -125,52 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG0")
-            .field(
-                "wdt_chip_reset_width",
-                &format_args!("{}", self.wdt_chip_reset_width().bits()),
-            )
-            .field(
-                "wdt_chip_reset_en",
-                &format_args!("{}", self.wdt_chip_reset_en().bit()),
-            )
-            .field(
-                "wdt_pause_in_slp",
-                &format_args!("{}", self.wdt_pause_in_slp().bit()),
-            )
-            .field(
-                "wdt_appcpu_reset_en",
-                &format_args!("{}", self.wdt_appcpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_chip_reset_width", &self.wdt_chip_reset_width())
+            .field("wdt_chip_reset_en", &self.wdt_chip_reset_en())
+            .field("wdt_pause_in_slp", &self.wdt_pause_in_slp())
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - chip reset siginal pulse width"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/wdtconfig1.rs b/esp32s3/src/rtc_cntl/wdtconfig1.rs
index 3fb004c9c5..350ca47b82 100644
--- a/esp32s3/src/rtc_cntl/wdtconfig1.rs
+++ b/esp32s3/src/rtc_cntl/wdtconfig1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG1")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - stage0 hold time"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/wdtconfig2.rs b/esp32s3/src/rtc_cntl/wdtconfig2.rs
index ea8a04d5b7..dcb913dc5c 100644
--- a/esp32s3/src/rtc_cntl/wdtconfig2.rs
+++ b/esp32s3/src/rtc_cntl/wdtconfig2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG2")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - stage1 hold time"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/wdtconfig3.rs b/esp32s3/src/rtc_cntl/wdtconfig3.rs
index c8cef08fba..14f8ee487f 100644
--- a/esp32s3/src/rtc_cntl/wdtconfig3.rs
+++ b/esp32s3/src/rtc_cntl/wdtconfig3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG3")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - stage2 hold time"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/wdtconfig4.rs b/esp32s3/src/rtc_cntl/wdtconfig4.rs
index 05d86d844d..5315909f9b 100644
--- a/esp32s3/src/rtc_cntl/wdtconfig4.rs
+++ b/esp32s3/src/rtc_cntl/wdtconfig4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG4")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - stage3 hold time"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/wdtwprotect.rs b/esp32s3/src/rtc_cntl/wdtwprotect.rs
index 2b7106f521..34a6cd4e78 100644
--- a/esp32s3/src/rtc_cntl/wdtwprotect.rs
+++ b/esp32s3/src/rtc_cntl/wdtwprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTWPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTWPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - rtc watch dog key"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/xtal32k_clk_factor.rs b/esp32s3/src/rtc_cntl/xtal32k_clk_factor.rs
index fbe6115ba1..19982e353a 100644
--- a/esp32s3/src/rtc_cntl/xtal32k_clk_factor.rs
+++ b/esp32s3/src/rtc_cntl/xtal32k_clk_factor.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL32K_CLK_FACTOR")
-            .field(
-                "xtal32k_clk_factor",
-                &format_args!("{}", self.xtal32k_clk_factor().bits()),
-            )
+            .field("xtal32k_clk_factor", &self.xtal32k_clk_factor())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL32K_CLK_FACTOR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - xtal 32k watch dog backup clock factor"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_cntl/xtal32k_conf.rs b/esp32s3/src/rtc_cntl/xtal32k_conf.rs
index 96a93627d5..4b80cf7c18 100644
--- a/esp32s3/src/rtc_cntl/xtal32k_conf.rs
+++ b/esp32s3/src/rtc_cntl/xtal32k_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL32K_CONF")
-            .field(
-                "xtal32k_return_wait",
-                &format_args!("{}", self.xtal32k_return_wait().bits()),
-            )
-            .field(
-                "xtal32k_restart_wait",
-                &format_args!("{}", self.xtal32k_restart_wait().bits()),
-            )
-            .field(
-                "xtal32k_wdt_timeout",
-                &format_args!("{}", self.xtal32k_wdt_timeout().bits()),
-            )
-            .field(
-                "xtal32k_stable_thres",
-                &format_args!("{}", self.xtal32k_stable_thres().bits()),
-            )
+            .field("xtal32k_return_wait", &self.xtal32k_return_wait())
+            .field("xtal32k_restart_wait", &self.xtal32k_restart_wait())
+            .field("xtal32k_wdt_timeout", &self.xtal32k_wdt_timeout())
+            .field("xtal32k_stable_thres", &self.xtal32k_stable_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL32K_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - cycles to wait to return noral xtal 32k"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_i2c/cmd.rs b/esp32s3/src/rtc_i2c/cmd.rs
index 9a93b9a334..0d65ae2943 100644
--- a/esp32s3/src/rtc_i2c/cmd.rs
+++ b/esp32s3/src/rtc_i2c/cmd.rs
@@ -24,20 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("command", &format_args!("{}", self.command().bits()))
-            .field(
-                "command_done",
-                &format_args!("{}", self.command_done().bit()),
-            )
+            .field("command", &self.command())
+            .field("command_done", &self.command_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - command0"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_i2c/ctrl.rs b/esp32s3/src/rtc_i2c/ctrl.rs
index e364ba7baa..ce7d4e072a 100644
--- a/esp32s3/src/rtc_i2c/ctrl.rs
+++ b/esp32s3/src/rtc_i2c/ctrl.rs
@@ -89,39 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field(
-                "sda_force_out",
-                &format_args!("{}", self.sda_force_out().bit()),
-            )
-            .field(
-                "scl_force_out",
-                &format_args!("{}", self.scl_force_out().bit()),
-            )
-            .field("ms_mode", &format_args!("{}", self.ms_mode().bit()))
-            .field("trans_start", &format_args!("{}", self.trans_start().bit()))
-            .field(
-                "tx_lsb_first",
-                &format_args!("{}", self.tx_lsb_first().bit()),
-            )
-            .field(
-                "rx_lsb_first",
-                &format_args!("{}", self.rx_lsb_first().bit()),
-            )
-            .field(
-                "i2c_ctrl_clk_gate_en",
-                &format_args!("{}", self.i2c_ctrl_clk_gate_en().bit()),
-            )
-            .field("i2c_reset", &format_args!("{}", self.i2c_reset().bit()))
-            .field("i2cclk_en", &format_args!("{}", self.i2cclk_en().bit()))
+            .field("sda_force_out", &self.sda_force_out())
+            .field("scl_force_out", &self.scl_force_out())
+            .field("ms_mode", &self.ms_mode())
+            .field("trans_start", &self.trans_start())
+            .field("tx_lsb_first", &self.tx_lsb_first())
+            .field("rx_lsb_first", &self.rx_lsb_first())
+            .field("i2c_ctrl_clk_gate_en", &self.i2c_ctrl_clk_gate_en())
+            .field("i2c_reset", &self.i2c_reset())
+            .field("i2cclk_en", &self.i2cclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1=push pull,0=open drain"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_i2c/data.rs b/esp32s3/src/rtc_i2c/data.rs
index 5e45ecf617..0616175fea 100644
--- a/esp32s3/src/rtc_i2c/data.rs
+++ b/esp32s3/src/rtc_i2c/data.rs
@@ -31,21 +31,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA")
-            .field("i2c_rdata", &format_args!("{}", self.i2c_rdata().bits()))
-            .field(
-                "slave_tx_data",
-                &format_args!("{}", self.slave_tx_data().bits()),
-            )
-            .field("i2c_done", &format_args!("{}", self.i2c_done().bit()))
+            .field("i2c_rdata", &self.i2c_rdata())
+            .field("slave_tx_data", &self.slave_tx_data())
+            .field("i2c_done", &self.i2c_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 8:15 - data sent by slave"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_i2c/date.rs b/esp32s3/src/rtc_i2c/date.rs
index c9d5c9aa7e..149ba7d705 100644
--- a/esp32s3/src/rtc_i2c/date.rs
+++ b/esp32s3/src/rtc_i2c/date.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field("i2c_date", &format_args!("{}", self.i2c_date().bits()))
+            .field("i2c_date", &self.i2c_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - version"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_i2c/int_ena.rs b/esp32s3/src/rtc_i2c/int_ena.rs
index 3588a0a8b3..9ea56e95b2 100644
--- a/esp32s3/src/rtc_i2c/int_ena.rs
+++ b/esp32s3/src/rtc_i2c/int_ena.rs
@@ -89,39 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "slave_tran_comp",
-                &format_args!("{}", self.slave_tran_comp().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_tran_comp",
-                &format_args!("{}", self.master_tran_comp().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("ack_err", &format_args!("{}", self.ack_err().bit()))
-            .field("rx_data", &format_args!("{}", self.rx_data().bit()))
-            .field("tx_data", &format_args!("{}", self.tx_data().bit()))
-            .field(
-                "detect_start",
-                &format_args!("{}", self.detect_start().bit()),
-            )
+            .field("slave_tran_comp", &self.slave_tran_comp())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_tran_comp", &self.master_tran_comp())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("ack_err", &self.ack_err())
+            .field("rx_data", &self.rx_data())
+            .field("tx_data", &self.tx_data())
+            .field("detect_start", &self.detect_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - enable slave transit complete interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_i2c/int_raw.rs b/esp32s3/src/rtc_i2c/int_raw.rs
index 77ddd6e574..52e571f869 100644
--- a/esp32s3/src/rtc_i2c/int_raw.rs
+++ b/esp32s3/src/rtc_i2c/int_raw.rs
@@ -69,39 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "slave_tran_comp",
-                &format_args!("{}", self.slave_tran_comp().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_tran_comp",
-                &format_args!("{}", self.master_tran_comp().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("ack_err", &format_args!("{}", self.ack_err().bit()))
-            .field("rx_data", &format_args!("{}", self.rx_data().bit()))
-            .field("tx_data", &format_args!("{}", self.tx_data().bit()))
-            .field(
-                "detect_start",
-                &format_args!("{}", self.detect_start().bit()),
-            )
+            .field("slave_tran_comp", &self.slave_tran_comp())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_tran_comp", &self.master_tran_comp())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("ack_err", &self.ack_err())
+            .field("rx_data", &self.rx_data())
+            .field("tx_data", &self.tx_data())
+            .field("detect_start", &self.detect_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "interrupt raw register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s3/src/rtc_i2c/int_st.rs b/esp32s3/src/rtc_i2c/int_st.rs
index e0cb24df8f..6766d04dae 100644
--- a/esp32s3/src/rtc_i2c/int_st.rs
+++ b/esp32s3/src/rtc_i2c/int_st.rs
@@ -69,39 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "slave_tran_comp",
-                &format_args!("{}", self.slave_tran_comp().bit()),
-            )
-            .field(
-                "arbitration_lost",
-                &format_args!("{}", self.arbitration_lost().bit()),
-            )
-            .field(
-                "master_tran_comp",
-                &format_args!("{}", self.master_tran_comp().bit()),
-            )
-            .field(
-                "trans_complete",
-                &format_args!("{}", self.trans_complete().bit()),
-            )
-            .field("time_out", &format_args!("{}", self.time_out().bit()))
-            .field("ack_err", &format_args!("{}", self.ack_err().bit()))
-            .field("rx_data", &format_args!("{}", self.rx_data().bit()))
-            .field("tx_data", &format_args!("{}", self.tx_data().bit()))
-            .field(
-                "detect_start",
-                &format_args!("{}", self.detect_start().bit()),
-            )
+            .field("slave_tran_comp", &self.slave_tran_comp())
+            .field("arbitration_lost", &self.arbitration_lost())
+            .field("master_tran_comp", &self.master_tran_comp())
+            .field("trans_complete", &self.trans_complete())
+            .field("time_out", &self.time_out())
+            .field("ack_err", &self.ack_err())
+            .field("rx_data", &self.rx_data())
+            .field("tx_data", &self.tx_data())
+            .field("detect_start", &self.detect_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "interrupt state register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/rtc_i2c/scl_high.rs b/esp32s3/src/rtc_i2c/scl_high.rs
index 6d52cb95a1..bfef5cffb2 100644
--- a/esp32s3/src/rtc_i2c/scl_high.rs
+++ b/esp32s3/src/rtc_i2c/scl_high.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_HIGH")
-            .field("period", &format_args!("{}", self.period().bits()))
+            .field("period", &self.period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_HIGH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - time period that scl = 1"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_i2c/scl_low.rs b/esp32s3/src/rtc_i2c/scl_low.rs
index b22c6e2f38..b8a3e8f8d7 100644
--- a/esp32s3/src/rtc_i2c/scl_low.rs
+++ b/esp32s3/src/rtc_i2c/scl_low.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_LOW")
-            .field("period", &format_args!("{}", self.period().bits()))
+            .field("period", &self.period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_LOW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - time period that scl =0"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_i2c/scl_start_period.rs b/esp32s3/src/rtc_i2c/scl_start_period.rs
index 0a05440618..e9bb81ca01 100644
--- a/esp32s3/src/rtc_i2c/scl_start_period.rs
+++ b/esp32s3/src/rtc_i2c/scl_start_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_START_PERIOD")
-            .field(
-                "scl_start_period",
-                &format_args!("{}", self.scl_start_period().bits()),
-            )
+            .field("scl_start_period", &self.scl_start_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_START_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - time period for SCL to toggle after I2C start is triggered"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_i2c/scl_stop_period.rs b/esp32s3/src/rtc_i2c/scl_stop_period.rs
index 078b53148e..373679ba9a 100644
--- a/esp32s3/src/rtc_i2c/scl_stop_period.rs
+++ b/esp32s3/src/rtc_i2c/scl_stop_period.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SCL_STOP_PERIOD")
-            .field(
-                "scl_stop_period",
-                &format_args!("{}", self.scl_stop_period().bits()),
-            )
+            .field("scl_stop_period", &self.scl_stop_period())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SCL_STOP_PERIOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - time period for SCL to stop after I2C end is triggered"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_i2c/sda_duty.rs b/esp32s3/src/rtc_i2c/sda_duty.rs
index 61b4edfe07..02ecbe7f58 100644
--- a/esp32s3/src/rtc_i2c/sda_duty.rs
+++ b/esp32s3/src/rtc_i2c/sda_duty.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SDA_DUTY")
-            .field("num", &format_args!("{}", self.num().bits()))
+            .field("num", &self.num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SDA_DUTY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - time period for SDA to toggle after SCL goes low"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_i2c/slave_addr.rs b/esp32s3/src/rtc_i2c/slave_addr.rs
index 6795ba25a3..ac82e1ef0a 100644
--- a/esp32s3/src/rtc_i2c/slave_addr.rs
+++ b/esp32s3/src/rtc_i2c/slave_addr.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE_ADDR")
-            .field("slave_addr", &format_args!("{}", self.slave_addr().bits()))
-            .field(
-                "addr_10bit_en",
-                &format_args!("{}", self.addr_10bit_en().bit()),
-            )
+            .field("slave_addr", &self.slave_addr())
+            .field("addr_10bit_en", &self.addr_10bit_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - slave address"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_i2c/status.rs b/esp32s3/src/rtc_i2c/status.rs
index c84cadbdaa..829a44a2e9 100644
--- a/esp32s3/src/rtc_i2c/status.rs
+++ b/esp32s3/src/rtc_i2c/status.rs
@@ -76,34 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("ack_rec", &format_args!("{}", self.ack_rec().bit()))
-            .field("slave_rw", &format_args!("{}", self.slave_rw().bit()))
-            .field("arb_lost", &format_args!("{}", self.arb_lost().bit()))
-            .field("bus_busy", &format_args!("{}", self.bus_busy().bit()))
-            .field(
-                "slave_addressed",
-                &format_args!("{}", self.slave_addressed().bit()),
-            )
-            .field("byte_trans", &format_args!("{}", self.byte_trans().bit()))
-            .field("op_cnt", &format_args!("{}", self.op_cnt().bits()))
-            .field("shift", &format_args!("{}", self.shift().bits()))
-            .field(
-                "scl_main_state_last",
-                &format_args!("{}", self.scl_main_state_last().bits()),
-            )
-            .field(
-                "scl_state_last",
-                &format_args!("{}", self.scl_state_last().bits()),
-            )
+            .field("ack_rec", &self.ack_rec())
+            .field("slave_rw", &self.slave_rw())
+            .field("arb_lost", &self.arb_lost())
+            .field("bus_busy", &self.bus_busy())
+            .field("slave_addressed", &self.slave_addressed())
+            .field("byte_trans", &self.byte_trans())
+            .field("op_cnt", &self.op_cnt())
+            .field("shift", &self.shift())
+            .field("scl_main_state_last", &self.scl_main_state_last())
+            .field("scl_state_last", &self.scl_state_last())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "get i2c status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32s3/src/rtc_i2c/to.rs b/esp32s3/src/rtc_i2c/to.rs
index c7565d564c..68d04baaa5 100644
--- a/esp32s3/src/rtc_i2c/to.rs
+++ b/esp32s3/src/rtc_i2c/to.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TO")
-            .field("time_out", &format_args!("{}", self.time_out().bits()))
+            .field("time_out", &self.time_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - time out threshold"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/date.rs b/esp32s3/src/rtc_io/date.rs
index 72b3a143ca..5bc973b2ce 100644
--- a/esp32s3/src/rtc_io/date.rs
+++ b/esp32s3/src/rtc_io/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/rtc_io/ext_wakeup0.rs b/esp32s3/src/rtc_io/ext_wakeup0.rs
index e831a5f686..c44a7b32d9 100644
--- a/esp32s3/src/rtc_io/ext_wakeup0.rs
+++ b/esp32s3/src/rtc_io/ext_wakeup0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_WAKEUP0")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 27:31 - ******* Description configure***"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/pad_dac1.rs b/esp32s3/src/rtc_io/pad_dac1.rs
index 75e812d000..c8805f2db3 100644
--- a/esp32s3/src/rtc_io/pad_dac1.rs
+++ b/esp32s3/src/rtc_io/pad_dac1.rs
@@ -116,51 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_DAC1")
-            .field("pdac1_dac", &format_args!("{}", self.pdac1_dac().bits()))
-            .field(
-                "pdac1_xpd_dac",
-                &format_args!("{}", self.pdac1_xpd_dac().bit()),
-            )
-            .field(
-                "pdac1_dac_xpd_force",
-                &format_args!("{}", self.pdac1_dac_xpd_force().bit()),
-            )
-            .field(
-                "pdac1_fun_ie",
-                &format_args!("{}", self.pdac1_fun_ie().bit()),
-            )
-            .field(
-                "pdac1_slp_oe",
-                &format_args!("{}", self.pdac1_slp_oe().bit()),
-            )
-            .field(
-                "pdac1_slp_ie",
-                &format_args!("{}", self.pdac1_slp_ie().bit()),
-            )
-            .field(
-                "pdac1_slp_sel",
-                &format_args!("{}", self.pdac1_slp_sel().bit()),
-            )
-            .field(
-                "pdac1_fun_sel",
-                &format_args!("{}", self.pdac1_fun_sel().bits()),
-            )
-            .field(
-                "pdac1_mux_sel",
-                &format_args!("{}", self.pdac1_mux_sel().bit()),
-            )
-            .field("pdac1_rue", &format_args!("{}", self.pdac1_rue().bit()))
-            .field("pdac1_rde", &format_args!("{}", self.pdac1_rde().bit()))
-            .field("pdac1_drv", &format_args!("{}", self.pdac1_drv().bits()))
+            .field("pdac1_dac", &self.pdac1_dac())
+            .field("pdac1_xpd_dac", &self.pdac1_xpd_dac())
+            .field("pdac1_dac_xpd_force", &self.pdac1_dac_xpd_force())
+            .field("pdac1_fun_ie", &self.pdac1_fun_ie())
+            .field("pdac1_slp_oe", &self.pdac1_slp_oe())
+            .field("pdac1_slp_ie", &self.pdac1_slp_ie())
+            .field("pdac1_slp_sel", &self.pdac1_slp_sel())
+            .field("pdac1_fun_sel", &self.pdac1_fun_sel())
+            .field("pdac1_mux_sel", &self.pdac1_mux_sel())
+            .field("pdac1_rue", &self.pdac1_rue())
+            .field("pdac1_rde", &self.pdac1_rde())
+            .field("pdac1_drv", &self.pdac1_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_DAC1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:10 - PDAC1_DAC"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/pad_dac2.rs b/esp32s3/src/rtc_io/pad_dac2.rs
index 4385f207d5..c03ec538d4 100644
--- a/esp32s3/src/rtc_io/pad_dac2.rs
+++ b/esp32s3/src/rtc_io/pad_dac2.rs
@@ -116,51 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PAD_DAC2")
-            .field("pdac2_dac", &format_args!("{}", self.pdac2_dac().bits()))
-            .field(
-                "pdac2_xpd_dac",
-                &format_args!("{}", self.pdac2_xpd_dac().bit()),
-            )
-            .field(
-                "pdac2_dac_xpd_force",
-                &format_args!("{}", self.pdac2_dac_xpd_force().bit()),
-            )
-            .field(
-                "pdac2_fun_ie",
-                &format_args!("{}", self.pdac2_fun_ie().bit()),
-            )
-            .field(
-                "pdac2_slp_oe",
-                &format_args!("{}", self.pdac2_slp_oe().bit()),
-            )
-            .field(
-                "pdac2_slp_ie",
-                &format_args!("{}", self.pdac2_slp_ie().bit()),
-            )
-            .field(
-                "pdac2_slp_sel",
-                &format_args!("{}", self.pdac2_slp_sel().bit()),
-            )
-            .field(
-                "pdac2_fun_sel",
-                &format_args!("{}", self.pdac2_fun_sel().bits()),
-            )
-            .field(
-                "pdac2_mux_sel",
-                &format_args!("{}", self.pdac2_mux_sel().bit()),
-            )
-            .field("pdac2_rue", &format_args!("{}", self.pdac2_rue().bit()))
-            .field("pdac2_rde", &format_args!("{}", self.pdac2_rde().bit()))
-            .field("pdac2_drv", &format_args!("{}", self.pdac2_drv().bits()))
+            .field("pdac2_dac", &self.pdac2_dac())
+            .field("pdac2_xpd_dac", &self.pdac2_xpd_dac())
+            .field("pdac2_dac_xpd_force", &self.pdac2_dac_xpd_force())
+            .field("pdac2_fun_ie", &self.pdac2_fun_ie())
+            .field("pdac2_slp_oe", &self.pdac2_slp_oe())
+            .field("pdac2_slp_ie", &self.pdac2_slp_ie())
+            .field("pdac2_slp_sel", &self.pdac2_slp_sel())
+            .field("pdac2_fun_sel", &self.pdac2_fun_sel())
+            .field("pdac2_mux_sel", &self.pdac2_mux_sel())
+            .field("pdac2_rue", &self.pdac2_rue())
+            .field("pdac2_rde", &self.pdac2_rde())
+            .field("pdac2_drv", &self.pdac2_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PAD_DAC2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:10 - PDAC2_DAC"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/pin.rs b/esp32s3/src/rtc_io/pin.rs
index e5f918925e..9edcbec5a6 100644
--- a/esp32s3/src/rtc_io/pin.rs
+++ b/esp32s3/src/rtc_io/pin.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PIN")
-            .field("pad_driver", &format_args!("{}", self.pad_driver().bit()))
-            .field("int_type", &format_args!("{}", self.int_type().bits()))
-            .field(
-                "wakeup_enable",
-                &format_args!("{}", self.wakeup_enable().bit()),
-            )
+            .field("pad_driver", &self.pad_driver())
+            .field("int_type", &self.int_type())
+            .field("wakeup_enable", &self.wakeup_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PIN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/rtc_debug_sel.rs b/esp32s3/src/rtc_io/rtc_debug_sel.rs
index 9b57dac5cf..22a700f04a 100644
--- a/esp32s3/src/rtc_io/rtc_debug_sel.rs
+++ b/esp32s3/src/rtc_io/rtc_debug_sel.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_DEBUG_SEL")
-            .field(
-                "rtc_debug_sel0",
-                &format_args!("{}", self.rtc_debug_sel0().bits()),
-            )
-            .field(
-                "rtc_debug_sel1",
-                &format_args!("{}", self.rtc_debug_sel1().bits()),
-            )
-            .field(
-                "rtc_debug_sel2",
-                &format_args!("{}", self.rtc_debug_sel2().bits()),
-            )
-            .field(
-                "rtc_debug_sel3",
-                &format_args!("{}", self.rtc_debug_sel3().bits()),
-            )
-            .field(
-                "rtc_debug_sel4",
-                &format_args!("{}", self.rtc_debug_sel4().bits()),
-            )
-            .field(
-                "rtc_debug_12m_no_gating",
-                &format_args!("{}", self.rtc_debug_12m_no_gating().bit()),
-            )
+            .field("rtc_debug_sel0", &self.rtc_debug_sel0())
+            .field("rtc_debug_sel1", &self.rtc_debug_sel1())
+            .field("rtc_debug_sel2", &self.rtc_debug_sel2())
+            .field("rtc_debug_sel3", &self.rtc_debug_sel3())
+            .field("rtc_debug_sel4", &self.rtc_debug_sel4())
+            .field("rtc_debug_12m_no_gating", &self.rtc_debug_12m_no_gating())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_DEBUG_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - configure rtc debug"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/rtc_gpio_enable.rs b/esp32s3/src/rtc_io/rtc_gpio_enable.rs
index 40b88da416..0521408520 100644
--- a/esp32s3/src/rtc_io/rtc_gpio_enable.rs
+++ b/esp32s3/src/rtc_io/rtc_gpio_enable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_GPIO_ENABLE")
-            .field(
-                "rtc_gpio_enable",
-                &format_args!("{}", self.rtc_gpio_enable().bits()),
-            )
+            .field("rtc_gpio_enable", &self.rtc_gpio_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_ENABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 enable"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/rtc_gpio_in.rs b/esp32s3/src/rtc_io/rtc_gpio_in.rs
index 8cc54aba84..563136ff79 100644
--- a/esp32s3/src/rtc_io/rtc_gpio_in.rs
+++ b/esp32s3/src/rtc_io/rtc_gpio_in.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_GPIO_IN")
-            .field("next", &format_args!("{}", self.next().bits()))
+            .field("next", &self.next())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_IN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC GPIO input data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_gpio_in::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTC_GPIO_IN_SPEC;
 impl crate::RegisterSpec for RTC_GPIO_IN_SPEC {
diff --git a/esp32s3/src/rtc_io/rtc_gpio_out.rs b/esp32s3/src/rtc_io/rtc_gpio_out.rs
index bc2bb61c39..403a3fe3c7 100644
--- a/esp32s3/src/rtc_io/rtc_gpio_out.rs
+++ b/esp32s3/src/rtc_io/rtc_gpio_out.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_GPIO_OUT")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_OUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 output data"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/rtc_gpio_status.rs b/esp32s3/src/rtc_io/rtc_gpio_status.rs
index 99f3d30c0c..2703283199 100644
--- a/esp32s3/src/rtc_io/rtc_gpio_status.rs
+++ b/esp32s3/src/rtc_io/rtc_gpio_status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_GPIO_STATUS")
-            .field("int", &format_args!("{}", self.int().bits()))
+            .field("int", &self.int())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 10:31 - RTC GPIO 0 ~ 21 interrupt status"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/rtc_pad19.rs b/esp32s3/src/rtc_io/rtc_pad19.rs
index 97f7c22efa..cdc4590708 100644
--- a/esp32s3/src/rtc_io/rtc_pad19.rs
+++ b/esp32s3/src/rtc_io/rtc_pad19.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_PAD19")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_PAD19_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/rtc_pad20.rs b/esp32s3/src/rtc_io/rtc_pad20.rs
index 829c1aeac5..ee52eb8887 100644
--- a/esp32s3/src/rtc_io/rtc_pad20.rs
+++ b/esp32s3/src/rtc_io/rtc_pad20.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_PAD20")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_PAD20_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/rtc_pad21.rs b/esp32s3/src/rtc_io/rtc_pad21.rs
index ac18a4607d..ec64424b7c 100644
--- a/esp32s3/src/rtc_io/rtc_pad21.rs
+++ b/esp32s3/src/rtc_io/rtc_pad21.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_PAD21")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_PAD21_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/sar_i2c_io.rs b/esp32s3/src/rtc_io/sar_i2c_io.rs
index cc37532f5a..9cdf9d4186 100644
--- a/esp32s3/src/rtc_io/sar_i2c_io.rs
+++ b/esp32s3/src/rtc_io/sar_i2c_io.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_I2C_IO")
-            .field(
-                "sar_debug_bit_sel",
-                &format_args!("{}", self.sar_debug_bit_sel().bits()),
-            )
-            .field(
-                "sar_i2c_scl_sel",
-                &format_args!("{}", self.sar_i2c_scl_sel().bits()),
-            )
-            .field(
-                "sar_i2c_sda_sel",
-                &format_args!("{}", self.sar_i2c_sda_sel().bits()),
-            )
+            .field("sar_debug_bit_sel", &self.sar_debug_bit_sel())
+            .field("sar_i2c_scl_sel", &self.sar_i2c_scl_sel())
+            .field("sar_i2c_sda_sel", &self.sar_i2c_sda_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_I2C_IO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 23:27 - ******* Description configure***"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_ctrl.rs b/esp32s3/src/rtc_io/touch_ctrl.rs
index 5a57b687fe..2624ca411e 100644
--- a/esp32s3/src/rtc_io/touch_ctrl.rs
+++ b/esp32s3/src/rtc_io/touch_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_CTRL")
-            .field(
-                "io_touch_bufsel",
-                &format_args!("{}", self.io_touch_bufsel().bits()),
-            )
-            .field(
-                "io_touch_bufmode",
-                &format_args!("{}", self.io_touch_bufmode().bit()),
-            )
+            .field("io_touch_bufsel", &self.io_touch_bufsel())
+            .field("io_touch_bufmode", &self.io_touch_bufmode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - BUF_SEL when touch work without fsm"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_pad0.rs b/esp32s3/src/rtc_io/touch_pad0.rs
index 7a2669777b..42c0795fa1 100644
--- a/esp32s3/src/rtc_io/touch_pad0.rs
+++ b/esp32s3/src/rtc_io/touch_pad0.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD0")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_pad1.rs b/esp32s3/src/rtc_io/touch_pad1.rs
index 16b3f0d36d..398aef5f43 100644
--- a/esp32s3/src/rtc_io/touch_pad1.rs
+++ b/esp32s3/src/rtc_io/touch_pad1.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD1")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_pad10.rs b/esp32s3/src/rtc_io/touch_pad10.rs
index ebe80d56c0..afb2523f1a 100644
--- a/esp32s3/src/rtc_io/touch_pad10.rs
+++ b/esp32s3/src/rtc_io/touch_pad10.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD10")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_pad11.rs b/esp32s3/src/rtc_io/touch_pad11.rs
index 01ea66a137..cfae1f4823 100644
--- a/esp32s3/src/rtc_io/touch_pad11.rs
+++ b/esp32s3/src/rtc_io/touch_pad11.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD11")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_pad12.rs b/esp32s3/src/rtc_io/touch_pad12.rs
index 3dc47b7376..79f1c06a2b 100644
--- a/esp32s3/src/rtc_io/touch_pad12.rs
+++ b/esp32s3/src/rtc_io/touch_pad12.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD12")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_pad13.rs b/esp32s3/src/rtc_io/touch_pad13.rs
index 1b3ae1c584..9a1418d62b 100644
--- a/esp32s3/src/rtc_io/touch_pad13.rs
+++ b/esp32s3/src/rtc_io/touch_pad13.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD13")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_pad14.rs b/esp32s3/src/rtc_io/touch_pad14.rs
index 5832c4ce85..5fdde4fd4d 100644
--- a/esp32s3/src/rtc_io/touch_pad14.rs
+++ b/esp32s3/src/rtc_io/touch_pad14.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD14")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_pad2.rs b/esp32s3/src/rtc_io/touch_pad2.rs
index 8d94286e48..37563006bf 100644
--- a/esp32s3/src/rtc_io/touch_pad2.rs
+++ b/esp32s3/src/rtc_io/touch_pad2.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD2")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_pad3.rs b/esp32s3/src/rtc_io/touch_pad3.rs
index 1a6752c02b..060c057597 100644
--- a/esp32s3/src/rtc_io/touch_pad3.rs
+++ b/esp32s3/src/rtc_io/touch_pad3.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD3")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_pad4.rs b/esp32s3/src/rtc_io/touch_pad4.rs
index c46462b6d6..c40e4c6e9d 100644
--- a/esp32s3/src/rtc_io/touch_pad4.rs
+++ b/esp32s3/src/rtc_io/touch_pad4.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD4")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_pad5.rs b/esp32s3/src/rtc_io/touch_pad5.rs
index 2fd3554beb..2e91ece0de 100644
--- a/esp32s3/src/rtc_io/touch_pad5.rs
+++ b/esp32s3/src/rtc_io/touch_pad5.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD5")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_pad6.rs b/esp32s3/src/rtc_io/touch_pad6.rs
index 3d08bac42c..b3f8fb7066 100644
--- a/esp32s3/src/rtc_io/touch_pad6.rs
+++ b/esp32s3/src/rtc_io/touch_pad6.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD6")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_pad7.rs b/esp32s3/src/rtc_io/touch_pad7.rs
index f9aa9420b7..0c6105ed7e 100644
--- a/esp32s3/src/rtc_io/touch_pad7.rs
+++ b/esp32s3/src/rtc_io/touch_pad7.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD7")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_pad8.rs b/esp32s3/src/rtc_io/touch_pad8.rs
index cc23a4ca77..8f98942d5d 100644
--- a/esp32s3/src/rtc_io/touch_pad8.rs
+++ b/esp32s3/src/rtc_io/touch_pad8.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD8")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/touch_pad9.rs b/esp32s3/src/rtc_io/touch_pad9.rs
index cf90e2e336..b4ca397664 100644
--- a/esp32s3/src/rtc_io/touch_pad9.rs
+++ b/esp32s3/src/rtc_io/touch_pad9.rs
@@ -116,27 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TOUCH_PAD9")
-            .field("fun_ie", &format_args!("{}", self.fun_ie().bit()))
-            .field("slp_oe", &format_args!("{}", self.slp_oe().bit()))
-            .field("slp_ie", &format_args!("{}", self.slp_ie().bit()))
-            .field("slp_sel", &format_args!("{}", self.slp_sel().bit()))
-            .field("fun_sel", &format_args!("{}", self.fun_sel().bits()))
-            .field("mux_sel", &format_args!("{}", self.mux_sel().bit()))
-            .field("xpd", &format_args!("{}", self.xpd().bit()))
-            .field("tie_opt", &format_args!("{}", self.tie_opt().bit()))
-            .field("start", &format_args!("{}", self.start().bit()))
-            .field("rue", &format_args!("{}", self.rue().bit()))
-            .field("rde", &format_args!("{}", self.rde().bit()))
-            .field("drv", &format_args!("{}", self.drv().bits()))
+            .field("fun_ie", &self.fun_ie())
+            .field("slp_oe", &self.slp_oe())
+            .field("slp_ie", &self.slp_ie())
+            .field("slp_sel", &self.slp_sel())
+            .field("fun_sel", &self.fun_sel())
+            .field("mux_sel", &self.mux_sel())
+            .field("xpd", &self.xpd())
+            .field("tie_opt", &self.tie_opt())
+            .field("start", &self.start())
+            .field("rue", &self.rue())
+            .field("rde", &self.rde())
+            .field("drv", &self.drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TOUCH_PAD9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/xtal_32n_pad.rs b/esp32s3/src/rtc_io/xtal_32n_pad.rs
index 2740083065..14c0ded41e 100644
--- a/esp32s3/src/rtc_io/xtal_32n_pad.rs
+++ b/esp32s3/src/rtc_io/xtal_32n_pad.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL_32N_PAD")
-            .field("x32n_fun_ie", &format_args!("{}", self.x32n_fun_ie().bit()))
-            .field("x32n_slp_oe", &format_args!("{}", self.x32n_slp_oe().bit()))
-            .field("x32n_slp_ie", &format_args!("{}", self.x32n_slp_ie().bit()))
-            .field(
-                "x32n_slp_sel",
-                &format_args!("{}", self.x32n_slp_sel().bit()),
-            )
-            .field(
-                "x32n_fun_sel",
-                &format_args!("{}", self.x32n_fun_sel().bits()),
-            )
-            .field(
-                "x32n_mux_sel",
-                &format_args!("{}", self.x32n_mux_sel().bit()),
-            )
-            .field("x32n_rue", &format_args!("{}", self.x32n_rue().bit()))
-            .field("x32n_rde", &format_args!("{}", self.x32n_rde().bit()))
-            .field("x32n_drv", &format_args!("{}", self.x32n_drv().bits()))
+            .field("x32n_fun_ie", &self.x32n_fun_ie())
+            .field("x32n_slp_oe", &self.x32n_slp_oe())
+            .field("x32n_slp_ie", &self.x32n_slp_ie())
+            .field("x32n_slp_sel", &self.x32n_slp_sel())
+            .field("x32n_fun_sel", &self.x32n_fun_sel())
+            .field("x32n_mux_sel", &self.x32n_mux_sel())
+            .field("x32n_rue", &self.x32n_rue())
+            .field("x32n_rde", &self.x32n_rde())
+            .field("x32n_drv", &self.x32n_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL_32N_PAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/xtal_32p_pad.rs b/esp32s3/src/rtc_io/xtal_32p_pad.rs
index 4482bc1f3c..a0cd0a6d6f 100644
--- a/esp32s3/src/rtc_io/xtal_32p_pad.rs
+++ b/esp32s3/src/rtc_io/xtal_32p_pad.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTAL_32P_PAD")
-            .field("x32p_fun_ie", &format_args!("{}", self.x32p_fun_ie().bit()))
-            .field("x32p_slp_oe", &format_args!("{}", self.x32p_slp_oe().bit()))
-            .field("x32p_slp_ie", &format_args!("{}", self.x32p_slp_ie().bit()))
-            .field(
-                "x32p_slp_sel",
-                &format_args!("{}", self.x32p_slp_sel().bit()),
-            )
-            .field(
-                "x32p_fun_sel",
-                &format_args!("{}", self.x32p_fun_sel().bits()),
-            )
-            .field(
-                "x32p_mux_sel",
-                &format_args!("{}", self.x32p_mux_sel().bit()),
-            )
-            .field("x32p_rue", &format_args!("{}", self.x32p_rue().bit()))
-            .field("x32p_rde", &format_args!("{}", self.x32p_rde().bit()))
-            .field("x32p_drv", &format_args!("{}", self.x32p_drv().bits()))
+            .field("x32p_fun_ie", &self.x32p_fun_ie())
+            .field("x32p_slp_oe", &self.x32p_slp_oe())
+            .field("x32p_slp_ie", &self.x32p_slp_ie())
+            .field("x32p_slp_sel", &self.x32p_slp_sel())
+            .field("x32p_fun_sel", &self.x32p_fun_sel())
+            .field("x32p_mux_sel", &self.x32p_mux_sel())
+            .field("x32p_rue", &self.x32p_rue())
+            .field("x32p_rde", &self.x32p_rde())
+            .field("x32p_drv", &self.x32p_drv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTAL_32P_PAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 13 - input enable in work mode"]
     #[inline(always)]
diff --git a/esp32s3/src/rtc_io/xtl_ext_ctr.rs b/esp32s3/src/rtc_io/xtl_ext_ctr.rs
index 26aaa51228..4f8597a9d3 100644
--- a/esp32s3/src/rtc_io/xtl_ext_ctr.rs
+++ b/esp32s3/src/rtc_io/xtl_ext_ctr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("XTL_EXT_CTR")
-            .field("sel", &format_args!("{}", self.sel().bits()))
+            .field("sel", &self.sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<XTL_EXT_CTR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 27:31 - select RTC GPIO 0 ~ 17 to control XTAL"]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/blksiz.rs b/esp32s3/src/sdhost/blksiz.rs
index 661464ff62..cc43139dce 100644
--- a/esp32s3/src/sdhost/blksiz.rs
+++ b/esp32s3/src/sdhost/blksiz.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BLKSIZ")
-            .field("block_size", &format_args!("{}", self.block_size().bits()))
+            .field("block_size", &self.block_size())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BLKSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Block size."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/bmod.rs b/esp32s3/src/sdhost/bmod.rs
index 84e024e84c..40bf525ef2 100644
--- a/esp32s3/src/sdhost/bmod.rs
+++ b/esp32s3/src/sdhost/bmod.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BMOD")
-            .field("swr", &format_args!("{}", self.swr().bit()))
-            .field("fb", &format_args!("{}", self.fb().bit()))
-            .field("de", &format_args!("{}", self.de().bit()))
-            .field("pbl", &format_args!("{}", self.pbl().bits()))
+            .field("swr", &self.swr())
+            .field("fb", &self.fb())
+            .field("de", &self.de())
+            .field("pbl", &self.pbl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BMOD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/bufaddr.rs b/esp32s3/src/sdhost/bufaddr.rs
index 720082ccb4..432972a890 100644
--- a/esp32s3/src/sdhost/bufaddr.rs
+++ b/esp32s3/src/sdhost/bufaddr.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUFADDR")
-            .field("bufaddr", &format_args!("{}", self.bufaddr().bits()))
+            .field("bufaddr", &self.bufaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUFADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Host buffer address pointer register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bufaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUFADDR_SPEC;
 impl crate::RegisterSpec for BUFADDR_SPEC {
diff --git a/esp32s3/src/sdhost/buffifo.rs b/esp32s3/src/sdhost/buffifo.rs
index fad83364df..75e09b3936 100644
--- a/esp32s3/src/sdhost/buffifo.rs
+++ b/esp32s3/src/sdhost/buffifo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUFFIFO")
-            .field("buffifo", &format_args!("{}", self.buffifo().bits()))
+            .field("buffifo", &self.buffifo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUFFIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - CPU write and read transmit data by FIFO. This register points to the current Data FIFO ."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/bytcnt.rs b/esp32s3/src/sdhost/bytcnt.rs
index af93408fdf..fed252d44c 100644
--- a/esp32s3/src/sdhost/bytcnt.rs
+++ b/esp32s3/src/sdhost/bytcnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BYTCNT")
-            .field("byte_count", &format_args!("{}", self.byte_count().bits()))
+            .field("byte_count", &self.byte_count())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BYTCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/cardthrctl.rs b/esp32s3/src/sdhost/cardthrctl.rs
index 9273aba36f..b1a29d375d 100644
--- a/esp32s3/src/sdhost/cardthrctl.rs
+++ b/esp32s3/src/sdhost/cardthrctl.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CARDTHRCTL")
-            .field("cardrdthren", &format_args!("{}", self.cardrdthren().bit()))
-            .field(
-                "cardclrinten",
-                &format_args!("{}", self.cardclrinten().bit()),
-            )
-            .field("cardwrthren", &format_args!("{}", self.cardwrthren().bit()))
-            .field(
-                "cardthreshold",
-                &format_args!("{}", self.cardthreshold().bits()),
-            )
+            .field("cardrdthren", &self.cardrdthren())
+            .field("cardclrinten", &self.cardclrinten())
+            .field("cardwrthren", &self.cardwrthren())
+            .field("cardthreshold", &self.cardthreshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CARDTHRCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Card read threshold enable. 1'b0-Card read threshold disabled. 1'b1-Card read threshold enabled."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/cdetect.rs b/esp32s3/src/sdhost/cdetect.rs
index b8c669a95b..e9df01474b 100644
--- a/esp32s3/src/sdhost/cdetect.rs
+++ b/esp32s3/src/sdhost/cdetect.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CDETECT")
-            .field(
-                "card_detect_n",
-                &format_args!("{}", self.card_detect_n().bits()),
-            )
+            .field("card_detect_n", &self.card_detect_n())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CDETECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Card detect register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cdetect::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CDETECT_SPEC;
 impl crate::RegisterSpec for CDETECT_SPEC {
diff --git a/esp32s3/src/sdhost/clk_edge_sel.rs b/esp32s3/src/sdhost/clk_edge_sel.rs
index 6dd87cabdb..5c26a63f24 100644
--- a/esp32s3/src/sdhost/clk_edge_sel.rs
+++ b/esp32s3/src/sdhost/clk_edge_sel.rs
@@ -89,42 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_EDGE_SEL")
-            .field(
-                "cclkin_edge_drv_sel",
-                &format_args!("{}", self.cclkin_edge_drv_sel().bits()),
-            )
-            .field(
-                "cclkin_edge_sam_sel",
-                &format_args!("{}", self.cclkin_edge_sam_sel().bits()),
-            )
-            .field(
-                "cclkin_edge_slf_sel",
-                &format_args!("{}", self.cclkin_edge_slf_sel().bits()),
-            )
-            .field(
-                "ccllkin_edge_h",
-                &format_args!("{}", self.ccllkin_edge_h().bits()),
-            )
-            .field(
-                "ccllkin_edge_l",
-                &format_args!("{}", self.ccllkin_edge_l().bits()),
-            )
-            .field(
-                "ccllkin_edge_n",
-                &format_args!("{}", self.ccllkin_edge_n().bits()),
-            )
-            .field("esdio_mode", &format_args!("{}", self.esdio_mode().bit()))
-            .field("esd_mode", &format_args!("{}", self.esd_mode().bit()))
-            .field("cclk_en", &format_args!("{}", self.cclk_en().bit()))
+            .field("cclkin_edge_drv_sel", &self.cclkin_edge_drv_sel())
+            .field("cclkin_edge_sam_sel", &self.cclkin_edge_sam_sel())
+            .field("cclkin_edge_slf_sel", &self.cclkin_edge_slf_sel())
+            .field("ccllkin_edge_h", &self.ccllkin_edge_h())
+            .field("ccllkin_edge_l", &self.ccllkin_edge_l())
+            .field("ccllkin_edge_n", &self.ccllkin_edge_n())
+            .field("esdio_mode", &self.esdio_mode())
+            .field("esd_mode", &self.esd_mode())
+            .field("cclk_en", &self.cclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_EDGE_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/clkdiv.rs b/esp32s3/src/sdhost/clkdiv.rs
index 1f025bc3a7..ecb1a5c6e4 100644
--- a/esp32s3/src/sdhost/clkdiv.rs
+++ b/esp32s3/src/sdhost/clkdiv.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKDIV")
-            .field(
-                "clk_divider0",
-                &format_args!("{}", self.clk_divider0().bits()),
-            )
-            .field(
-                "clk_divider1",
-                &format_args!("{}", self.clk_divider1().bits()),
-            )
-            .field(
-                "clk_divider2",
-                &format_args!("{}", self.clk_divider2().bits()),
-            )
-            .field(
-                "clk_divider3",
-                &format_args!("{}", self.clk_divider3().bits()),
-            )
+            .field("clk_divider0", &self.clk_divider0())
+            .field("clk_divider1", &self.clk_divider1())
+            .field("clk_divider2", &self.clk_divider2())
+            .field("clk_divider3", &self.clk_divider3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKDIV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/clkena.rs b/esp32s3/src/sdhost/clkena.rs
index b9ab1045ee..9c066422e5 100644
--- a/esp32s3/src/sdhost/clkena.rs
+++ b/esp32s3/src/sdhost/clkena.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKENA")
-            .field(
-                "cclk_enable",
-                &format_args!("{}", self.cclk_enable().bits()),
-            )
-            .field("lp_enable", &format_args!("{}", self.lp_enable().bits()))
+            .field("cclk_enable", &self.cclk_enable())
+            .field("lp_enable", &self.lp_enable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card. 0: Clock disabled; 1: Clock enabled."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/clksrc.rs b/esp32s3/src/sdhost/clksrc.rs
index 4e506db40d..c65f699e31 100644
--- a/esp32s3/src/sdhost/clksrc.rs
+++ b/esp32s3/src/sdhost/clksrc.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKSRC")
-            .field("clksrc", &format_args!("{}", self.clksrc().bits()))
+            .field("clksrc", &self.clksrc())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKSRC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit\\[1:0\\] are assigned for card 0, bit\\[3:2\\] are assigned for card 1. Card 0 maps and internally routes clock divider\\[0:3\\] outputs to cclk_out\\[1:0\\] pins, depending on bit value. 00 : Clock divider 0; 01 : Clock divider 1; 10 : Clock divider 2; 11 : Clock divider 3."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/cmd.rs b/esp32s3/src/sdhost/cmd.rs
index 8f7e1af323..1c3d217d5c 100644
--- a/esp32s3/src/sdhost/cmd.rs
+++ b/esp32s3/src/sdhost/cmd.rs
@@ -161,71 +161,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("index", &format_args!("{}", self.index().bits()))
-            .field(
-                "response_expect",
-                &format_args!("{}", self.response_expect().bit()),
-            )
-            .field(
-                "response_length",
-                &format_args!("{}", self.response_length().bit()),
-            )
-            .field(
-                "check_response_crc",
-                &format_args!("{}", self.check_response_crc().bit()),
-            )
-            .field(
-                "data_expected",
-                &format_args!("{}", self.data_expected().bit()),
-            )
-            .field("read_write", &format_args!("{}", self.read_write().bit()))
-            .field(
-                "transfer_mode",
-                &format_args!("{}", self.transfer_mode().bit()),
-            )
-            .field(
-                "send_auto_stop",
-                &format_args!("{}", self.send_auto_stop().bit()),
-            )
-            .field(
-                "wait_prvdata_complete",
-                &format_args!("{}", self.wait_prvdata_complete().bit()),
-            )
-            .field(
-                "stop_abort_cmd",
-                &format_args!("{}", self.stop_abort_cmd().bit()),
-            )
-            .field(
-                "send_initialization",
-                &format_args!("{}", self.send_initialization().bit()),
-            )
-            .field(
-                "card_number",
-                &format_args!("{}", self.card_number().bits()),
-            )
+            .field("index", &self.index())
+            .field("response_expect", &self.response_expect())
+            .field("response_length", &self.response_length())
+            .field("check_response_crc", &self.check_response_crc())
+            .field("data_expected", &self.data_expected())
+            .field("read_write", &self.read_write())
+            .field("transfer_mode", &self.transfer_mode())
+            .field("send_auto_stop", &self.send_auto_stop())
+            .field("wait_prvdata_complete", &self.wait_prvdata_complete())
+            .field("stop_abort_cmd", &self.stop_abort_cmd())
+            .field("send_initialization", &self.send_initialization())
+            .field("card_number", &self.card_number())
             .field(
                 "update_clock_registers_only",
-                &format_args!("{}", self.update_clock_registers_only().bit()),
+                &self.update_clock_registers_only(),
             )
-            .field(
-                "read_ceata_device",
-                &format_args!("{}", self.read_ceata_device().bit()),
-            )
-            .field(
-                "ccs_expected",
-                &format_args!("{}", self.ccs_expected().bit()),
-            )
-            .field("use_hole", &format_args!("{}", self.use_hole().bit()))
-            .field("start_cmd", &format_args!("{}", self.start_cmd().bit()))
+            .field("read_ceata_device", &self.read_ceata_device())
+            .field("ccs_expected", &self.ccs_expected())
+            .field("use_hole", &self.use_hole())
+            .field("start_cmd", &self.start_cmd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - Command index."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/cmdarg.rs b/esp32s3/src/sdhost/cmdarg.rs
index db8f85bd5c..94ac7da52a 100644
--- a/esp32s3/src/sdhost/cmdarg.rs
+++ b/esp32s3/src/sdhost/cmdarg.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMDARG")
-            .field("cmdarg", &format_args!("{}", self.cmdarg().bits()))
+            .field("cmdarg", &self.cmdarg())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMDARG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Value indicates command argument to be passed to the card."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/ctrl.rs b/esp32s3/src/sdhost/ctrl.rs
index f0e1ff619d..e9544443a1 100644
--- a/esp32s3/src/sdhost/ctrl.rs
+++ b/esp32s3/src/sdhost/ctrl.rs
@@ -98,40 +98,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field(
-                "controller_reset",
-                &format_args!("{}", self.controller_reset().bit()),
-            )
-            .field("fifo_reset", &format_args!("{}", self.fifo_reset().bit()))
-            .field("dma_reset", &format_args!("{}", self.dma_reset().bit()))
-            .field("int_enable", &format_args!("{}", self.int_enable().bit()))
-            .field("read_wait", &format_args!("{}", self.read_wait().bit()))
-            .field(
-                "send_irq_response",
-                &format_args!("{}", self.send_irq_response().bit()),
-            )
-            .field(
-                "abort_read_data",
-                &format_args!("{}", self.abort_read_data().bit()),
-            )
-            .field("send_ccsd", &format_args!("{}", self.send_ccsd().bit()))
-            .field(
-                "send_auto_stop_ccsd",
-                &format_args!("{}", self.send_auto_stop_ccsd().bit()),
-            )
+            .field("controller_reset", &self.controller_reset())
+            .field("fifo_reset", &self.fifo_reset())
+            .field("dma_reset", &self.dma_reset())
+            .field("int_enable", &self.int_enable())
+            .field("read_wait", &self.read_wait())
+            .field("send_irq_response", &self.send_irq_response())
+            .field("abort_read_data", &self.abort_read_data())
+            .field("send_ccsd", &self.send_ccsd())
+            .field("send_auto_stop_ccsd", &self.send_auto_stop_ccsd())
             .field(
                 "ceata_device_interrupt_status",
-                &format_args!("{}", self.ceata_device_interrupt_status().bit()),
+                &self.ceata_device_interrupt_status(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/ctype.rs b/esp32s3/src/sdhost/ctype.rs
index 3d50d29f24..55173aecd3 100644
--- a/esp32s3/src/sdhost/ctype.rs
+++ b/esp32s3/src/sdhost/ctype.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTYPE")
-            .field(
-                "card_width4",
-                &format_args!("{}", self.card_width4().bits()),
-            )
-            .field(
-                "card_width8",
-                &format_args!("{}", self.card_width8().bits()),
-            )
+            .field("card_width4", &self.card_width4())
+            .field("card_width8", &self.card_width8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTYPE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - One bit per card indicates if card is 1-bit or 4-bit mode. 0: 1-bit mode; 1: 4-bit mode. Bit\\[1:0\\] correspond to card\\[1:0\\] respectively."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/dbaddr.rs b/esp32s3/src/sdhost/dbaddr.rs
index ea5fb55c53..3866cfa354 100644
--- a/esp32s3/src/sdhost/dbaddr.rs
+++ b/esp32s3/src/sdhost/dbaddr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DBADDR")
-            .field("dbaddr", &format_args!("{}", self.dbaddr().bits()))
+            .field("dbaddr", &self.dbaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DBADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits \\[1:0\\] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/debnce.rs b/esp32s3/src/sdhost/debnce.rs
index a7f179fe77..022482c4a3 100644
--- a/esp32s3/src/sdhost/debnce.rs
+++ b/esp32s3/src/sdhost/debnce.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DEBNCE")
-            .field(
-                "debounce_count",
-                &format_args!("{}", self.debounce_count().bits()),
-            )
+            .field("debounce_count", &self.debounce_count())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DEBNCE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:23 - Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/dscaddr.rs b/esp32s3/src/sdhost/dscaddr.rs
index a8b43628b2..0e5e74f7e0 100644
--- a/esp32s3/src/sdhost/dscaddr.rs
+++ b/esp32s3/src/sdhost/dscaddr.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSCADDR")
-            .field("dscaddr", &format_args!("{}", self.dscaddr().bits()))
+            .field("dscaddr", &self.dscaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSCADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Host descriptor address pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dscaddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DSCADDR_SPEC;
 impl crate::RegisterSpec for DSCADDR_SPEC {
diff --git a/esp32s3/src/sdhost/emmcddr.rs b/esp32s3/src/sdhost/emmcddr.rs
index a7905808ae..c09a8b9611 100644
--- a/esp32s3/src/sdhost/emmcddr.rs
+++ b/esp32s3/src/sdhost/emmcddr.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EMMCDDR")
-            .field(
-                "halfstartbit",
-                &format_args!("{}", self.halfstartbit().bits()),
-            )
-            .field("hs400_mode", &format_args!("{}", self.hs400_mode().bit()))
+            .field("halfstartbit", &self.halfstartbit())
+            .field("hs400_mode", &self.hs400_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EMMCDDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be: 1'b0-Full cycle. 1'b1-less than one full cycle."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/enshift.rs b/esp32s3/src/sdhost/enshift.rs
index fb0f2357dc..5f8e486fda 100644
--- a/esp32s3/src/sdhost/enshift.rs
+++ b/esp32s3/src/sdhost/enshift.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ENSHIFT")
-            .field(
-                "enable_shift",
-                &format_args!("{}", self.enable_shift().bits()),
-            )
+            .field("enable_shift", &self.enable_shift())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ENSHIFT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card. 2'b00-Default phase shift. 2'b01-Enables shifted to next immediate positive edge. 2'b10-Enables shifted to next immediate negative edge. 2'b11-Reserved."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/fifoth.rs b/esp32s3/src/sdhost/fifoth.rs
index b0e03f0226..735765f001 100644
--- a/esp32s3/src/sdhost/fifoth.rs
+++ b/esp32s3/src/sdhost/fifoth.rs
@@ -35,21 +35,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFOTH")
-            .field("tx_wmark", &format_args!("{}", self.tx_wmark().bits()))
-            .field("rx_wmark", &format_args!("{}", self.rx_wmark().bits()))
+            .field("tx_wmark", &self.tx_wmark())
+            .field("rx_wmark", &self.rx_wmark())
             .field(
                 "dma_multiple_transaction_size",
-                &format_args!("{}", self.dma_multiple_transaction_size().bits()),
+                &self.dma_multiple_transaction_size(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFOTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/hcon.rs b/esp32s3/src/sdhost/hcon.rs
index 0200e41188..f7790404e1 100644
--- a/esp32s3/src/sdhost/hcon.rs
+++ b/esp32s3/src/sdhost/hcon.rs
@@ -69,27 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HCON")
-            .field("card_type", &format_args!("{}", self.card_type().bit()))
-            .field("card_num", &format_args!("{}", self.card_num().bits()))
-            .field("bus_type", &format_args!("{}", self.bus_type().bit()))
-            .field("data_width", &format_args!("{}", self.data_width().bits()))
-            .field("addr_width", &format_args!("{}", self.addr_width().bits()))
-            .field("dma_width", &format_args!("{}", self.dma_width().bits()))
-            .field("ram_indise", &format_args!("{}", self.ram_indise().bit()))
-            .field("hold", &format_args!("{}", self.hold().bit()))
-            .field(
-                "num_clk_div",
-                &format_args!("{}", self.num_clk_div().bits()),
-            )
+            .field("card_type", &self.card_type())
+            .field("card_num", &self.card_num())
+            .field("bus_type", &self.bus_type())
+            .field("data_width", &self.data_width())
+            .field("addr_width", &self.addr_width())
+            .field("dma_width", &self.dma_width())
+            .field("ram_indise", &self.ram_indise())
+            .field("hold", &self.hold())
+            .field("num_clk_div", &self.num_clk_div())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HCON_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Hardware feature register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcon::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HCON_SPEC;
 impl crate::RegisterSpec for HCON_SPEC {
diff --git a/esp32s3/src/sdhost/idinten.rs b/esp32s3/src/sdhost/idinten.rs
index 7998f81685..709ad85941 100644
--- a/esp32s3/src/sdhost/idinten.rs
+++ b/esp32s3/src/sdhost/idinten.rs
@@ -71,22 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDINTEN")
-            .field("ti", &format_args!("{}", self.ti().bit()))
-            .field("ri", &format_args!("{}", self.ri().bit()))
-            .field("fbe", &format_args!("{}", self.fbe().bit()))
-            .field("du", &format_args!("{}", self.du().bit()))
-            .field("ces", &format_args!("{}", self.ces().bit()))
-            .field("ni", &format_args!("{}", self.ni().bit()))
-            .field("ai", &format_args!("{}", self.ai().bit()))
+            .field("ti", &self.ti())
+            .field("ri", &self.ri())
+            .field("fbe", &self.fbe())
+            .field("du", &self.du())
+            .field("ces", &self.ces())
+            .field("ni", &self.ni())
+            .field("ai", &self.ai())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDINTEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/idsts.rs b/esp32s3/src/sdhost/idsts.rs
index c4d4f42dcc..a3de143483 100644
--- a/esp32s3/src/sdhost/idsts.rs
+++ b/esp32s3/src/sdhost/idsts.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDSTS")
-            .field("ti", &format_args!("{}", self.ti().bit()))
-            .field("ri", &format_args!("{}", self.ri().bit()))
-            .field("fbe", &format_args!("{}", self.fbe().bit()))
-            .field("du", &format_args!("{}", self.du().bit()))
-            .field("ces", &format_args!("{}", self.ces().bit()))
-            .field("nis", &format_args!("{}", self.nis().bit()))
-            .field("ais", &format_args!("{}", self.ais().bit()))
-            .field("fbe_code", &format_args!("{}", self.fbe_code().bits()))
-            .field("fsm", &format_args!("{}", self.fsm().bits()))
+            .field("ti", &self.ti())
+            .field("ri", &self.ri())
+            .field("fbe", &self.fbe())
+            .field("du", &self.du())
+            .field("ces", &self.ces())
+            .field("nis", &self.nis())
+            .field("ais", &self.ais())
+            .field("fbe_code", &self.fbe_code())
+            .field("fsm", &self.fsm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/intmask.rs b/esp32s3/src/sdhost/intmask.rs
index d19916144a..c55d4e7c79 100644
--- a/esp32s3/src/sdhost/intmask.rs
+++ b/esp32s3/src/sdhost/intmask.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTMASK")
-            .field("int_mask", &format_args!("{}", self.int_mask().bits()))
-            .field(
-                "sdio_int_mask",
-                &format_args!("{}", self.sdio_int_mask().bits()),
-            )
+            .field("int_mask", &self.int_mask())
+            .field("sdio_int_mask", &self.sdio_int_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTMASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): Rx Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation-by-host timeout; Bit 9 (DRTO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/mintsts.rs b/esp32s3/src/sdhost/mintsts.rs
index ce1a8af58f..4f907e6f71 100644
--- a/esp32s3/src/sdhost/mintsts.rs
+++ b/esp32s3/src/sdhost/mintsts.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MINTSTS")
-            .field(
-                "int_status_msk",
-                &format_args!("{}", self.int_status_msk().bits()),
-            )
-            .field(
-                "sdio_interrupt_msk",
-                &format_args!("{}", self.sdio_interrupt_msk().bits()),
-            )
+            .field("int_status_msk", &self.int_status_msk())
+            .field("sdio_interrupt_msk", &self.sdio_interrupt_msk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MINTSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mintsts::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MINTSTS_SPEC;
 impl crate::RegisterSpec for MINTSTS_SPEC {
diff --git a/esp32s3/src/sdhost/resp0.rs b/esp32s3/src/sdhost/resp0.rs
index 1b4aa21517..9ff09e1a06 100644
--- a/esp32s3/src/sdhost/resp0.rs
+++ b/esp32s3/src/sdhost/resp0.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESP0")
-            .field("response0", &format_args!("{}", self.response0().bits()))
+            .field("response0", &self.response0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESP0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESP0_SPEC;
 impl crate::RegisterSpec for RESP0_SPEC {
diff --git a/esp32s3/src/sdhost/resp1.rs b/esp32s3/src/sdhost/resp1.rs
index 1b69601dd9..f7356973c4 100644
--- a/esp32s3/src/sdhost/resp1.rs
+++ b/esp32s3/src/sdhost/resp1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESP1")
-            .field("response1", &format_args!("{}", self.response1().bits()))
+            .field("response1", &self.response1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Long response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESP1_SPEC;
 impl crate::RegisterSpec for RESP1_SPEC {
diff --git a/esp32s3/src/sdhost/resp2.rs b/esp32s3/src/sdhost/resp2.rs
index 1a43d9001f..178a098e32 100644
--- a/esp32s3/src/sdhost/resp2.rs
+++ b/esp32s3/src/sdhost/resp2.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESP2")
-            .field("response2", &format_args!("{}", self.response2().bits()))
+            .field("response2", &self.response2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESP2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Long response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESP2_SPEC;
 impl crate::RegisterSpec for RESP2_SPEC {
diff --git a/esp32s3/src/sdhost/resp3.rs b/esp32s3/src/sdhost/resp3.rs
index 73432f9173..b73efbf947 100644
--- a/esp32s3/src/sdhost/resp3.rs
+++ b/esp32s3/src/sdhost/resp3.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RESP3")
-            .field("response3", &format_args!("{}", self.response3().bits()))
+            .field("response3", &self.response3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RESP3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Long response data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resp3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RESP3_SPEC;
 impl crate::RegisterSpec for RESP3_SPEC {
diff --git a/esp32s3/src/sdhost/rintsts.rs b/esp32s3/src/sdhost/rintsts.rs
index 25724778fc..ead4f84f3d 100644
--- a/esp32s3/src/sdhost/rintsts.rs
+++ b/esp32s3/src/sdhost/rintsts.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RINTSTS")
-            .field(
-                "int_status_raw",
-                &format_args!("{}", self.int_status_raw().bits()),
-            )
-            .field(
-                "sdio_interrupt_raw",
-                &format_args!("{}", self.sdio_interrupt_raw().bits()),
-            )
+            .field("int_status_raw", &self.int_status_raw())
+            .field("sdio_interrupt_raw", &self.sdio_interrupt_raw())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RINTSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status. Bit 15 (EBE): End-bit error/no CRC error; Bit 14 (ACD): Auto command done; Bit 13 (SBE/BCI): RX Start Bit Error; Bit 12 (HLE): Hardware locked write error; Bit 11 (FRUN): FIFO underrun/overrun error; Bit 10 (HTO): Data starvation by host timeout (HTO); Bit 9 (DTRO): Data read timeout; Bit 8 (RTO): Response timeout; Bit 7 (DCRC): Data CRC error; Bit 6 (RCRC): Response CRC error; Bit 5 (RXDR): Receive FIFO data request; Bit 4 (TXDR): Transmit FIFO data request; Bit 3 (DTO): Data transfer over; Bit 2 (CD): Command done; Bit 1 (RE): Response error; Bit 0 (CD): Card detect."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/rst_n.rs b/esp32s3/src/sdhost/rst_n.rs
index d4fad96220..515c3ad743 100644
--- a/esp32s3/src/sdhost/rst_n.rs
+++ b/esp32s3/src/sdhost/rst_n.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RST_N")
-            .field("card_reset", &format_args!("{}", self.card_reset().bits()))
+            .field("card_reset", &self.card_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RST_N_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Hardware reset. 1: Active mode; 0: Reset. These bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET\\[0\\] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET\\[1\\] should be set to 1'b0 to reset card1."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/status.rs b/esp32s3/src/sdhost/status.rs
index a4ae56c313..ef268c61e4 100644
--- a/esp32s3/src/sdhost/status.rs
+++ b/esp32s3/src/sdhost/status.rs
@@ -76,43 +76,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field(
-                "fifo_rx_watermark",
-                &format_args!("{}", self.fifo_rx_watermark().bit()),
-            )
-            .field(
-                "fifo_tx_watermark",
-                &format_args!("{}", self.fifo_tx_watermark().bit()),
-            )
-            .field("fifo_empty", &format_args!("{}", self.fifo_empty().bit()))
-            .field("fifo_full", &format_args!("{}", self.fifo_full().bit()))
-            .field(
-                "command_fsm_states",
-                &format_args!("{}", self.command_fsm_states().bits()),
-            )
-            .field(
-                "data_3_status",
-                &format_args!("{}", self.data_3_status().bit()),
-            )
-            .field("data_busy", &format_args!("{}", self.data_busy().bit()))
-            .field(
-                "data_state_mc_busy",
-                &format_args!("{}", self.data_state_mc_busy().bit()),
-            )
-            .field(
-                "response_index",
-                &format_args!("{}", self.response_index().bits()),
-            )
-            .field("fifo_count", &format_args!("{}", self.fifo_count().bits()))
+            .field("fifo_rx_watermark", &self.fifo_rx_watermark())
+            .field("fifo_tx_watermark", &self.fifo_tx_watermark())
+            .field("fifo_empty", &self.fifo_empty())
+            .field("fifo_full", &self.fifo_full())
+            .field("command_fsm_states", &self.command_fsm_states())
+            .field("data_3_status", &self.data_3_status())
+            .field("data_busy", &self.data_busy())
+            .field("data_state_mc_busy", &self.data_state_mc_busy())
+            .field("response_index", &self.response_index())
+            .field("fifo_count", &self.fifo_count())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SD/MMC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32s3/src/sdhost/tbbcnt.rs b/esp32s3/src/sdhost/tbbcnt.rs
index 410acd8cd8..bb4ac6ca03 100644
--- a/esp32s3/src/sdhost/tbbcnt.rs
+++ b/esp32s3/src/sdhost/tbbcnt.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TBBCNT")
-            .field("tbbcnt", &format_args!("{}", self.tbbcnt().bits()))
+            .field("tbbcnt", &self.tbbcnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TBBCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transferred byte count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbbcnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TBBCNT_SPEC;
 impl crate::RegisterSpec for TBBCNT_SPEC {
diff --git a/esp32s3/src/sdhost/tcbcnt.rs b/esp32s3/src/sdhost/tcbcnt.rs
index 0332649df8..2f744b171a 100644
--- a/esp32s3/src/sdhost/tcbcnt.rs
+++ b/esp32s3/src/sdhost/tcbcnt.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TCBCNT")
-            .field("tcbcnt", &format_args!("{}", self.tcbcnt().bits()))
+            .field("tcbcnt", &self.tcbcnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TCBCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Transferred byte count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcbcnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TCBCNT_SPEC;
 impl crate::RegisterSpec for TCBCNT_SPEC {
diff --git a/esp32s3/src/sdhost/tmout.rs b/esp32s3/src/sdhost/tmout.rs
index b0ad6750a7..f9a4084a1b 100644
--- a/esp32s3/src/sdhost/tmout.rs
+++ b/esp32s3/src/sdhost/tmout.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TMOUT")
-            .field(
-                "response_timeout",
-                &format_args!("{}", self.response_timeout().bits()),
-            )
-            .field(
-                "data_timeout",
-                &format_args!("{}", self.data_timeout().bits()),
-            )
+            .field("response_timeout", &self.response_timeout())
+            .field("data_timeout", &self.data_timeout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TMOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/uhs.rs b/esp32s3/src/sdhost/uhs.rs
index a4da564e20..13762b101a 100644
--- a/esp32s3/src/sdhost/uhs.rs
+++ b/esp32s3/src/sdhost/uhs.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("UHS")
-            .field("ddr", &format_args!("{}", self.ddr().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UHS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("UHS").field("ddr", &self.ddr()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/sdhost/usrid.rs b/esp32s3/src/sdhost/usrid.rs
index c1f4d4468f..00a625ffb6 100644
--- a/esp32s3/src/sdhost/usrid.rs
+++ b/esp32s3/src/sdhost/usrid.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USRID")
-            .field("usrid", &format_args!("{}", self.usrid().bits()))
+            .field("usrid", &self.usrid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USRID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - User identification register, value set by user. Can also be used as a scratchpad register by user."]
     #[inline(always)]
diff --git a/esp32s3/src/sdhost/verid.rs b/esp32s3/src/sdhost/verid.rs
index 0874ea6135..4c138b6386 100644
--- a/esp32s3/src/sdhost/verid.rs
+++ b/esp32s3/src/sdhost/verid.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("VERID")
-            .field("versionid", &format_args!("{}", self.versionid().bits()))
+            .field("versionid", &self.versionid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<VERID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Version ID (scratchpad) register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`verid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct VERID_SPEC;
 impl crate::RegisterSpec for VERID_SPEC {
diff --git a/esp32s3/src/sdhost/wrtprt.rs b/esp32s3/src/sdhost/wrtprt.rs
index cd98eab48c..ed6a8d409e 100644
--- a/esp32s3/src/sdhost/wrtprt.rs
+++ b/esp32s3/src/sdhost/wrtprt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WRTPRT")
-            .field(
-                "write_protect",
-                &format_args!("{}", self.write_protect().bits()),
-            )
+            .field("write_protect", &self.write_protect())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WRTPRT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Card write protection (WP) status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wrtprt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WRTPRT_SPEC;
 impl crate::RegisterSpec for WRTPRT_SPEC {
diff --git a/esp32s3/src/sens/sar_amp_ctrl1.rs b/esp32s3/src/sens/sar_amp_ctrl1.rs
index 63c33f5c73..c61872e2d7 100644
--- a/esp32s3/src/sens/sar_amp_ctrl1.rs
+++ b/esp32s3/src/sens/sar_amp_ctrl1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_AMP_CTRL1")
-            .field(
-                "sar_amp_wait1",
-                &format_args!("{}", self.sar_amp_wait1().bits()),
-            )
-            .field(
-                "sar_amp_wait2",
-                &format_args!("{}", self.sar_amp_wait2().bits()),
-            )
+            .field("sar_amp_wait1", &self.sar_amp_wait1())
+            .field("sar_amp_wait2", &self.sar_amp_wait2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_AMP_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - no public"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_amp_ctrl2.rs b/esp32s3/src/sens/sar_amp_ctrl2.rs
index 36d8c8ca82..22e095f962 100644
--- a/esp32s3/src/sens/sar_amp_ctrl2.rs
+++ b/esp32s3/src/sens/sar_amp_ctrl2.rs
@@ -82,45 +82,24 @@ impl core::fmt::Debug for R {
         f.debug_struct("SAR_AMP_CTRL2")
             .field(
                 "sar_sar1_dac_xpd_fsm_idle",
-                &format_args!("{}", self.sar_sar1_dac_xpd_fsm_idle().bit()),
-            )
-            .field(
-                "sar_xpd_sar_amp_fsm_idle",
-                &format_args!("{}", self.sar_xpd_sar_amp_fsm_idle().bit()),
-            )
-            .field(
-                "sar_amp_rst_fb_fsm_idle",
-                &format_args!("{}", self.sar_amp_rst_fb_fsm_idle().bit()),
+                &self.sar_sar1_dac_xpd_fsm_idle(),
             )
+            .field("sar_xpd_sar_amp_fsm_idle", &self.sar_xpd_sar_amp_fsm_idle())
+            .field("sar_amp_rst_fb_fsm_idle", &self.sar_amp_rst_fb_fsm_idle())
             .field(
                 "sar_amp_short_ref_fsm_idle",
-                &format_args!("{}", self.sar_amp_short_ref_fsm_idle().bit()),
+                &self.sar_amp_short_ref_fsm_idle(),
             )
             .field(
                 "sar_amp_short_ref_gnd_fsm_idle",
-                &format_args!("{}", self.sar_amp_short_ref_gnd_fsm_idle().bit()),
-            )
-            .field(
-                "sar_xpd_sar_fsm_idle",
-                &format_args!("{}", self.sar_xpd_sar_fsm_idle().bit()),
-            )
-            .field(
-                "sar_rstb_fsm_idle",
-                &format_args!("{}", self.sar_rstb_fsm_idle().bit()),
-            )
-            .field(
-                "sar_amp_wait3",
-                &format_args!("{}", self.sar_amp_wait3().bits()),
+                &self.sar_amp_short_ref_gnd_fsm_idle(),
             )
+            .field("sar_xpd_sar_fsm_idle", &self.sar_xpd_sar_fsm_idle())
+            .field("sar_rstb_fsm_idle", &self.sar_rstb_fsm_idle())
+            .field("sar_amp_wait3", &self.sar_amp_wait3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_AMP_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - no public"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_amp_ctrl3.rs b/esp32s3/src/sens/sar_amp_ctrl3.rs
index 4b8293a33e..69e2bfedc0 100644
--- a/esp32s3/src/sens/sar_amp_ctrl3.rs
+++ b/esp32s3/src/sens/sar_amp_ctrl3.rs
@@ -71,40 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_AMP_CTRL3")
-            .field(
-                "sar1_dac_xpd_fsm",
-                &format_args!("{}", self.sar1_dac_xpd_fsm().bits()),
-            )
-            .field(
-                "xpd_sar_amp_fsm",
-                &format_args!("{}", self.xpd_sar_amp_fsm().bits()),
-            )
-            .field(
-                "amp_rst_fb_fsm",
-                &format_args!("{}", self.amp_rst_fb_fsm().bits()),
-            )
-            .field(
-                "amp_short_ref_fsm",
-                &format_args!("{}", self.amp_short_ref_fsm().bits()),
-            )
-            .field(
-                "amp_short_ref_gnd_fsm",
-                &format_args!("{}", self.amp_short_ref_gnd_fsm().bits()),
-            )
-            .field(
-                "xpd_sar_fsm",
-                &format_args!("{}", self.xpd_sar_fsm().bits()),
-            )
-            .field("rstb_fsm", &format_args!("{}", self.rstb_fsm().bits()))
+            .field("sar1_dac_xpd_fsm", &self.sar1_dac_xpd_fsm())
+            .field("xpd_sar_amp_fsm", &self.xpd_sar_amp_fsm())
+            .field("amp_rst_fb_fsm", &self.amp_rst_fb_fsm())
+            .field("amp_short_ref_fsm", &self.amp_short_ref_fsm())
+            .field("amp_short_ref_gnd_fsm", &self.amp_short_ref_gnd_fsm())
+            .field("xpd_sar_fsm", &self.xpd_sar_fsm())
+            .field("rstb_fsm", &self.rstb_fsm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_AMP_CTRL3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - no public"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_atten1.rs b/esp32s3/src/sens/sar_atten1.rs
index 9850654e7f..34e3147b12 100644
--- a/esp32s3/src/sens/sar_atten1.rs
+++ b/esp32s3/src/sens/sar_atten1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_ATTEN1")
-            .field("sar1_atten", &format_args!("{}", self.sar1_atten().bits()))
+            .field("sar1_atten", &self.sar1_atten())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_ATTEN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 2-bit attenuation for each pad"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_atten2.rs b/esp32s3/src/sens/sar_atten2.rs
index 4d9b7b9f21..8315019cf5 100644
--- a/esp32s3/src/sens/sar_atten2.rs
+++ b/esp32s3/src/sens/sar_atten2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_ATTEN2")
-            .field("sar2_atten", &format_args!("{}", self.sar2_atten().bits()))
+            .field("sar2_atten", &self.sar2_atten())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_ATTEN2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - 2-bit attenuation for each pad"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_cocpu_debug.rs b/esp32s3/src/sens/sar_cocpu_debug.rs
index 50164ed918..ff1a535064 100644
--- a/esp32s3/src/sens/sar_cocpu_debug.rs
+++ b/esp32s3/src/sens/sar_cocpu_debug.rs
@@ -41,35 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_COCPU_DEBUG")
-            .field(
-                "sar_cocpu_pc",
-                &format_args!("{}", self.sar_cocpu_pc().bits()),
-            )
-            .field(
-                "sar_cocpu_mem_vld",
-                &format_args!("{}", self.sar_cocpu_mem_vld().bit()),
-            )
-            .field(
-                "sar_cocpu_mem_rdy",
-                &format_args!("{}", self.sar_cocpu_mem_rdy().bit()),
-            )
-            .field(
-                "sar_cocpu_mem_wen",
-                &format_args!("{}", self.sar_cocpu_mem_wen().bits()),
-            )
-            .field(
-                "sar_cocpu_mem_addr",
-                &format_args!("{}", self.sar_cocpu_mem_addr().bits()),
-            )
+            .field("sar_cocpu_pc", &self.sar_cocpu_pc())
+            .field("sar_cocpu_mem_vld", &self.sar_cocpu_mem_vld())
+            .field("sar_cocpu_mem_rdy", &self.sar_cocpu_mem_rdy())
+            .field("sar_cocpu_mem_wen", &self.sar_cocpu_mem_wen())
+            .field("sar_cocpu_mem_addr", &self.sar_cocpu_mem_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_DEBUG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Ulp-riscv debug signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_cocpu_debug::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_COCPU_DEBUG_SPEC;
 impl crate::RegisterSpec for SAR_COCPU_DEBUG_SPEC {
diff --git a/esp32s3/src/sens/sar_cocpu_int_ena.rs b/esp32s3/src/sens/sar_cocpu_int_ena.rs
index 38f9bf265a..7cb1e6dba5 100644
--- a/esp32s3/src/sens/sar_cocpu_int_ena.rs
+++ b/esp32s3/src/sens/sar_cocpu_int_ena.rs
@@ -120,64 +120,43 @@ impl core::fmt::Debug for R {
         f.debug_struct("SAR_COCPU_INT_ENA")
             .field(
                 "sar_cocpu_touch_done_int_ena",
-                &format_args!("{}", self.sar_cocpu_touch_done_int_ena().bit()),
+                &self.sar_cocpu_touch_done_int_ena(),
             )
             .field(
                 "sar_cocpu_touch_inactive_int_ena",
-                &format_args!("{}", self.sar_cocpu_touch_inactive_int_ena().bit()),
+                &self.sar_cocpu_touch_inactive_int_ena(),
             )
             .field(
                 "sar_cocpu_touch_active_int_ena",
-                &format_args!("{}", self.sar_cocpu_touch_active_int_ena().bit()),
+                &self.sar_cocpu_touch_active_int_ena(),
             )
             .field(
                 "sar_cocpu_saradc1_int_ena",
-                &format_args!("{}", self.sar_cocpu_saradc1_int_ena().bit()),
+                &self.sar_cocpu_saradc1_int_ena(),
             )
             .field(
                 "sar_cocpu_saradc2_int_ena",
-                &format_args!("{}", self.sar_cocpu_saradc2_int_ena().bit()),
-            )
-            .field(
-                "sar_cocpu_tsens_int_ena",
-                &format_args!("{}", self.sar_cocpu_tsens_int_ena().bit()),
-            )
-            .field(
-                "sar_cocpu_start_int_ena",
-                &format_args!("{}", self.sar_cocpu_start_int_ena().bit()),
-            )
-            .field(
-                "sar_cocpu_sw_int_ena",
-                &format_args!("{}", self.sar_cocpu_sw_int_ena().bit()),
-            )
-            .field(
-                "sar_cocpu_swd_int_ena",
-                &format_args!("{}", self.sar_cocpu_swd_int_ena().bit()),
+                &self.sar_cocpu_saradc2_int_ena(),
             )
+            .field("sar_cocpu_tsens_int_ena", &self.sar_cocpu_tsens_int_ena())
+            .field("sar_cocpu_start_int_ena", &self.sar_cocpu_start_int_ena())
+            .field("sar_cocpu_sw_int_ena", &self.sar_cocpu_sw_int_ena())
+            .field("sar_cocpu_swd_int_ena", &self.sar_cocpu_swd_int_ena())
             .field(
                 "sar_cocpu_touch_timeout_int_ena",
-                &format_args!("{}", self.sar_cocpu_touch_timeout_int_ena().bit()),
+                &self.sar_cocpu_touch_timeout_int_ena(),
             )
             .field(
                 "sar_cocpu_touch_approach_loop_done_int_ena",
-                &format_args!(
-                    "{}",
-                    self.sar_cocpu_touch_approach_loop_done_int_ena().bit()
-                ),
+                &self.sar_cocpu_touch_approach_loop_done_int_ena(),
             )
             .field(
                 "sar_cocpu_touch_scan_done_int_ena",
-                &format_args!("{}", self.sar_cocpu_touch_scan_done_int_ena().bit()),
+                &self.sar_cocpu_touch_scan_done_int_ena(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - int enable of touch done"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_cocpu_int_raw.rs b/esp32s3/src/sens/sar_cocpu_int_raw.rs
index eb37023427..4f2b22c966 100644
--- a/esp32s3/src/sens/sar_cocpu_int_raw.rs
+++ b/esp32s3/src/sens/sar_cocpu_int_raw.rs
@@ -94,64 +94,43 @@ impl core::fmt::Debug for R {
         f.debug_struct("SAR_COCPU_INT_RAW")
             .field(
                 "sar_cocpu_touch_done_int_raw",
-                &format_args!("{}", self.sar_cocpu_touch_done_int_raw().bit()),
+                &self.sar_cocpu_touch_done_int_raw(),
             )
             .field(
                 "sar_cocpu_touch_inactive_int_raw",
-                &format_args!("{}", self.sar_cocpu_touch_inactive_int_raw().bit()),
+                &self.sar_cocpu_touch_inactive_int_raw(),
             )
             .field(
                 "sar_cocpu_touch_active_int_raw",
-                &format_args!("{}", self.sar_cocpu_touch_active_int_raw().bit()),
+                &self.sar_cocpu_touch_active_int_raw(),
             )
             .field(
                 "sar_cocpu_saradc1_int_raw",
-                &format_args!("{}", self.sar_cocpu_saradc1_int_raw().bit()),
+                &self.sar_cocpu_saradc1_int_raw(),
             )
             .field(
                 "sar_cocpu_saradc2_int_raw",
-                &format_args!("{}", self.sar_cocpu_saradc2_int_raw().bit()),
-            )
-            .field(
-                "sar_cocpu_tsens_int_raw",
-                &format_args!("{}", self.sar_cocpu_tsens_int_raw().bit()),
-            )
-            .field(
-                "sar_cocpu_start_int_raw",
-                &format_args!("{}", self.sar_cocpu_start_int_raw().bit()),
-            )
-            .field(
-                "sar_cocpu_sw_int_raw",
-                &format_args!("{}", self.sar_cocpu_sw_int_raw().bit()),
-            )
-            .field(
-                "sar_cocpu_swd_int_raw",
-                &format_args!("{}", self.sar_cocpu_swd_int_raw().bit()),
+                &self.sar_cocpu_saradc2_int_raw(),
             )
+            .field("sar_cocpu_tsens_int_raw", &self.sar_cocpu_tsens_int_raw())
+            .field("sar_cocpu_start_int_raw", &self.sar_cocpu_start_int_raw())
+            .field("sar_cocpu_sw_int_raw", &self.sar_cocpu_sw_int_raw())
+            .field("sar_cocpu_swd_int_raw", &self.sar_cocpu_swd_int_raw())
             .field(
                 "sar_cocpu_touch_timeout_int_raw",
-                &format_args!("{}", self.sar_cocpu_touch_timeout_int_raw().bit()),
+                &self.sar_cocpu_touch_timeout_int_raw(),
             )
             .field(
                 "sar_cocpu_touch_approach_loop_done_int_raw",
-                &format_args!(
-                    "{}",
-                    self.sar_cocpu_touch_approach_loop_done_int_raw().bit()
-                ),
+                &self.sar_cocpu_touch_approach_loop_done_int_raw(),
             )
             .field(
                 "sar_cocpu_touch_scan_done_int_raw",
-                &format_args!("{}", self.sar_cocpu_touch_scan_done_int_raw().bit()),
+                &self.sar_cocpu_touch_scan_done_int_raw(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "the interrupt raw of ulp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_cocpu_int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_COCPU_INT_RAW_SPEC;
 impl crate::RegisterSpec for SAR_COCPU_INT_RAW_SPEC {
diff --git a/esp32s3/src/sens/sar_cocpu_int_st.rs b/esp32s3/src/sens/sar_cocpu_int_st.rs
index d3b02bfb27..1c4c60cadc 100644
--- a/esp32s3/src/sens/sar_cocpu_int_st.rs
+++ b/esp32s3/src/sens/sar_cocpu_int_st.rs
@@ -94,61 +94,37 @@ impl core::fmt::Debug for R {
         f.debug_struct("SAR_COCPU_INT_ST")
             .field(
                 "sar_cocpu_touch_done_int_st",
-                &format_args!("{}", self.sar_cocpu_touch_done_int_st().bit()),
+                &self.sar_cocpu_touch_done_int_st(),
             )
             .field(
                 "sar_cocpu_touch_inactive_int_st",
-                &format_args!("{}", self.sar_cocpu_touch_inactive_int_st().bit()),
+                &self.sar_cocpu_touch_inactive_int_st(),
             )
             .field(
                 "sar_cocpu_touch_active_int_st",
-                &format_args!("{}", self.sar_cocpu_touch_active_int_st().bit()),
-            )
-            .field(
-                "sar_cocpu_saradc1_int_st",
-                &format_args!("{}", self.sar_cocpu_saradc1_int_st().bit()),
-            )
-            .field(
-                "sar_cocpu_saradc2_int_st",
-                &format_args!("{}", self.sar_cocpu_saradc2_int_st().bit()),
-            )
-            .field(
-                "sar_cocpu_tsens_int_st",
-                &format_args!("{}", self.sar_cocpu_tsens_int_st().bit()),
-            )
-            .field(
-                "sar_cocpu_start_int_st",
-                &format_args!("{}", self.sar_cocpu_start_int_st().bit()),
-            )
-            .field(
-                "sar_cocpu_sw_int_st",
-                &format_args!("{}", self.sar_cocpu_sw_int_st().bit()),
-            )
-            .field(
-                "sar_cocpu_swd_int_st",
-                &format_args!("{}", self.sar_cocpu_swd_int_st().bit()),
+                &self.sar_cocpu_touch_active_int_st(),
             )
+            .field("sar_cocpu_saradc1_int_st", &self.sar_cocpu_saradc1_int_st())
+            .field("sar_cocpu_saradc2_int_st", &self.sar_cocpu_saradc2_int_st())
+            .field("sar_cocpu_tsens_int_st", &self.sar_cocpu_tsens_int_st())
+            .field("sar_cocpu_start_int_st", &self.sar_cocpu_start_int_st())
+            .field("sar_cocpu_sw_int_st", &self.sar_cocpu_sw_int_st())
+            .field("sar_cocpu_swd_int_st", &self.sar_cocpu_swd_int_st())
             .field(
                 "sar_cocpu_touch_timeout_int_st",
-                &format_args!("{}", self.sar_cocpu_touch_timeout_int_st().bit()),
+                &self.sar_cocpu_touch_timeout_int_st(),
             )
             .field(
                 "sar_cocpu_touch_approach_loop_done_int_st",
-                &format_args!("{}", self.sar_cocpu_touch_approach_loop_done_int_st().bit()),
+                &self.sar_cocpu_touch_approach_loop_done_int_st(),
             )
             .field(
                 "sar_cocpu_touch_scan_done_int_st",
-                &format_args!("{}", self.sar_cocpu_touch_scan_done_int_st().bit()),
+                &self.sar_cocpu_touch_scan_done_int_st(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "the interrupt state of ulp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_cocpu_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_COCPU_INT_ST_SPEC;
 impl crate::RegisterSpec for SAR_COCPU_INT_ST_SPEC {
diff --git a/esp32s3/src/sens/sar_cocpu_state.rs b/esp32s3/src/sens/sar_cocpu_state.rs
index bb3cad155f..ff44c48c6a 100644
--- a/esp32s3/src/sens/sar_cocpu_state.rs
+++ b/esp32s3/src/sens/sar_cocpu_state.rs
@@ -45,35 +45,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_COCPU_STATE")
-            .field(
-                "sar_cocpu_clk_en_st",
-                &format_args!("{}", self.sar_cocpu_clk_en_st().bit()),
-            )
-            .field(
-                "sar_cocpu_reset_n",
-                &format_args!("{}", self.sar_cocpu_reset_n().bit()),
-            )
-            .field(
-                "sar_cocpu_eoi",
-                &format_args!("{}", self.sar_cocpu_eoi().bit()),
-            )
-            .field(
-                "sar_cocpu_trap",
-                &format_args!("{}", self.sar_cocpu_trap().bit()),
-            )
-            .field(
-                "sar_cocpu_ebreak",
-                &format_args!("{}", self.sar_cocpu_ebreak().bit()),
-            )
+            .field("sar_cocpu_clk_en_st", &self.sar_cocpu_clk_en_st())
+            .field("sar_cocpu_reset_n", &self.sar_cocpu_reset_n())
+            .field("sar_cocpu_eoi", &self.sar_cocpu_eoi())
+            .field("sar_cocpu_trap", &self.sar_cocpu_trap())
+            .field("sar_cocpu_ebreak", &self.sar_cocpu_ebreak())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - trigger cocpu debug registers"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_debug_conf.rs b/esp32s3/src/sens/sar_debug_conf.rs
index 24fa23bd51..2629277735 100644
--- a/esp32s3/src/sens/sar_debug_conf.rs
+++ b/esp32s3/src/sens/sar_debug_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_DEBUG_CONF")
-            .field(
-                "sar_debug_bit_sel",
-                &format_args!("{}", self.sar_debug_bit_sel().bits()),
-            )
+            .field("sar_debug_bit_sel", &self.sar_debug_bit_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_DEBUG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - no public"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_hall_ctrl.rs b/esp32s3/src/sens/sar_hall_ctrl.rs
index 088cd908a4..049bccd792 100644
--- a/esp32s3/src/sens/sar_hall_ctrl.rs
+++ b/esp32s3/src/sens/sar_hall_ctrl.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_HALL_CTRL")
-            .field("xpd_hall", &format_args!("{}", self.xpd_hall().bit()))
-            .field(
-                "xpd_hall_force",
-                &format_args!("{}", self.xpd_hall_force().bit()),
-            )
-            .field("hall_phase", &format_args!("{}", self.hall_phase().bit()))
-            .field(
-                "hall_phase_force",
-                &format_args!("{}", self.hall_phase_force().bit()),
-            )
+            .field("xpd_hall", &self.xpd_hall())
+            .field("xpd_hall_force", &self.xpd_hall_force())
+            .field("hall_phase", &self.hall_phase())
+            .field("hall_phase_force", &self.hall_phase_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_HALL_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 28 - Power on hall sensor and connect to VP and VN"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_i2c_ctrl.rs b/esp32s3/src/sens/sar_i2c_ctrl.rs
index 47848dd2f7..ac538b3da3 100644
--- a/esp32s3/src/sens/sar_i2c_ctrl.rs
+++ b/esp32s3/src/sens/sar_i2c_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_I2C_CTRL")
-            .field(
-                "sar_i2c_ctrl",
-                &format_args!("{}", self.sar_i2c_ctrl().bits()),
-            )
-            .field(
-                "sar_i2c_start",
-                &format_args!("{}", self.sar_i2c_start().bit()),
-            )
-            .field(
-                "sar_i2c_start_force",
-                &format_args!("{}", self.sar_i2c_start_force().bit()),
-            )
+            .field("sar_i2c_ctrl", &self.sar_i2c_ctrl())
+            .field("sar_i2c_start", &self.sar_i2c_start())
+            .field("sar_i2c_start_force", &self.sar_i2c_start_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_I2C_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - I2C control data only active when reg_sar_i2c_start_force = 1"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_meas1_ctrl1.rs b/esp32s3/src/sens/sar_meas1_ctrl1.rs
index 7f836c9542..fbf44aec20 100644
--- a/esp32s3/src/sens/sar_meas1_ctrl1.rs
+++ b/esp32s3/src/sens/sar_meas1_ctrl1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS1_CTRL1")
-            .field(
-                "force_xpd_amp",
-                &format_args!("{}", self.force_xpd_amp().bits()),
-            )
-            .field(
-                "amp_rst_fb_force",
-                &format_args!("{}", self.amp_rst_fb_force().bits()),
-            )
-            .field(
-                "amp_short_ref_force",
-                &format_args!("{}", self.amp_short_ref_force().bits()),
-            )
-            .field(
-                "amp_short_ref_gnd_force",
-                &format_args!("{}", self.amp_short_ref_gnd_force().bits()),
-            )
+            .field("force_xpd_amp", &self.force_xpd_amp())
+            .field("amp_rst_fb_force", &self.amp_rst_fb_force())
+            .field("amp_short_ref_force", &self.amp_short_ref_force())
+            .field("amp_short_ref_gnd_force", &self.amp_short_ref_gnd_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS1_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 24:25 - no public"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_meas1_ctrl2.rs b/esp32s3/src/sens/sar_meas1_ctrl2.rs
index 9105f5300b..c74fc584c4 100644
--- a/esp32s3/src/sens/sar_meas1_ctrl2.rs
+++ b/esp32s3/src/sens/sar_meas1_ctrl2.rs
@@ -58,39 +58,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS1_CTRL2")
-            .field(
-                "meas1_data_sar",
-                &format_args!("{}", self.meas1_data_sar().bits()),
-            )
-            .field(
-                "meas1_done_sar",
-                &format_args!("{}", self.meas1_done_sar().bit()),
-            )
-            .field(
-                "meas1_start_sar",
-                &format_args!("{}", self.meas1_start_sar().bit()),
-            )
-            .field(
-                "meas1_start_force",
-                &format_args!("{}", self.meas1_start_force().bit()),
-            )
-            .field(
-                "sar1_en_pad",
-                &format_args!("{}", self.sar1_en_pad().bits()),
-            )
-            .field(
-                "sar1_en_pad_force",
-                &format_args!("{}", self.sar1_en_pad_force().bit()),
-            )
+            .field("meas1_data_sar", &self.meas1_data_sar())
+            .field("meas1_done_sar", &self.meas1_done_sar())
+            .field("meas1_start_sar", &self.meas1_start_sar())
+            .field("meas1_start_force", &self.meas1_start_force())
+            .field("sar1_en_pad", &self.sar1_en_pad())
+            .field("sar1_en_pad_force", &self.sar1_en_pad_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS1_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - SAR ADC1 controller (in RTC) starts conversion"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_meas1_mux.rs b/esp32s3/src/sens/sar_meas1_mux.rs
index 4bfd6af29b..c021c6d9c5 100644
--- a/esp32s3/src/sens/sar_meas1_mux.rs
+++ b/esp32s3/src/sens/sar_meas1_mux.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS1_MUX")
-            .field(
-                "sar1_dig_force",
-                &format_args!("{}", self.sar1_dig_force().bit()),
-            )
+            .field("sar1_dig_force", &self.sar1_dig_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS1_MUX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - 1: SAR ADC1 controlled by DIG ADC1 CTRL"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_meas2_ctrl1.rs b/esp32s3/src/sens/sar_meas2_ctrl1.rs
index bf33a9b243..85cf223731 100644
--- a/esp32s3/src/sens/sar_meas2_ctrl1.rs
+++ b/esp32s3/src/sens/sar_meas2_ctrl1.rs
@@ -78,47 +78,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS2_CTRL1")
-            .field(
-                "sar_sar2_cntl_state",
-                &format_args!("{}", self.sar_sar2_cntl_state().bits()),
-            )
-            .field(
-                "sar_sar2_pwdet_cal_en",
-                &format_args!("{}", self.sar_sar2_pwdet_cal_en().bit()),
-            )
-            .field(
-                "sar_sar2_pkdet_cal_en",
-                &format_args!("{}", self.sar_sar2_pkdet_cal_en().bit()),
-            )
-            .field(
-                "sar_sar2_en_test",
-                &format_args!("{}", self.sar_sar2_en_test().bit()),
-            )
-            .field(
-                "sar_sar2_rstb_force",
-                &format_args!("{}", self.sar_sar2_rstb_force().bits()),
-            )
-            .field(
-                "sar_sar2_standby_wait",
-                &format_args!("{}", self.sar_sar2_standby_wait().bits()),
-            )
-            .field(
-                "sar_sar2_rstb_wait",
-                &format_args!("{}", self.sar_sar2_rstb_wait().bits()),
-            )
-            .field(
-                "sar_sar2_xpd_wait",
-                &format_args!("{}", self.sar_sar2_xpd_wait().bits()),
-            )
+            .field("sar_sar2_cntl_state", &self.sar_sar2_cntl_state())
+            .field("sar_sar2_pwdet_cal_en", &self.sar_sar2_pwdet_cal_en())
+            .field("sar_sar2_pkdet_cal_en", &self.sar_sar2_pkdet_cal_en())
+            .field("sar_sar2_en_test", &self.sar_sar2_en_test())
+            .field("sar_sar2_rstb_force", &self.sar_sar2_rstb_force())
+            .field("sar_sar2_standby_wait", &self.sar_sar2_standby_wait())
+            .field("sar_sar2_rstb_wait", &self.sar_sar2_rstb_wait())
+            .field("sar_sar2_xpd_wait", &self.sar_sar2_xpd_wait())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS2_CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - rtc control pwdet enable"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_meas2_ctrl2.rs b/esp32s3/src/sens/sar_meas2_ctrl2.rs
index d32d16fcf3..49dbd1e8e5 100644
--- a/esp32s3/src/sens/sar_meas2_ctrl2.rs
+++ b/esp32s3/src/sens/sar_meas2_ctrl2.rs
@@ -58,39 +58,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS2_CTRL2")
-            .field(
-                "meas2_data_sar",
-                &format_args!("{}", self.meas2_data_sar().bits()),
-            )
-            .field(
-                "meas2_done_sar",
-                &format_args!("{}", self.meas2_done_sar().bit()),
-            )
-            .field(
-                "meas2_start_sar",
-                &format_args!("{}", self.meas2_start_sar().bit()),
-            )
-            .field(
-                "meas2_start_force",
-                &format_args!("{}", self.meas2_start_force().bit()),
-            )
-            .field(
-                "sar2_en_pad",
-                &format_args!("{}", self.sar2_en_pad().bits()),
-            )
-            .field(
-                "sar2_en_pad_force",
-                &format_args!("{}", self.sar2_en_pad_force().bit()),
-            )
+            .field("meas2_data_sar", &self.meas2_data_sar())
+            .field("meas2_done_sar", &self.meas2_done_sar())
+            .field("meas2_start_sar", &self.meas2_start_sar())
+            .field("meas2_start_force", &self.meas2_start_force())
+            .field("sar2_en_pad", &self.sar2_en_pad())
+            .field("sar2_en_pad_force", &self.sar2_en_pad_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS2_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - SAR ADC2 controller (in RTC) starts conversion"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_meas2_mux.rs b/esp32s3/src/sens/sar_meas2_mux.rs
index bdda53eb00..8619b30ab9 100644
--- a/esp32s3/src/sens/sar_meas2_mux.rs
+++ b/esp32s3/src/sens/sar_meas2_mux.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_MEAS2_MUX")
-            .field(
-                "sar2_pwdet_cct",
-                &format_args!("{}", self.sar2_pwdet_cct().bits()),
-            )
-            .field(
-                "sar2_rtc_force",
-                &format_args!("{}", self.sar2_rtc_force().bit()),
-            )
+            .field("sar2_pwdet_cct", &self.sar2_pwdet_cct())
+            .field("sar2_rtc_force", &self.sar2_rtc_force())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_MEAS2_MUX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 28:30 - SAR2_PWDET_CCT"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_nouse.rs b/esp32s3/src/sens/sar_nouse.rs
index d7aca7fdeb..28d9b57fcc 100644
--- a/esp32s3/src/sens/sar_nouse.rs
+++ b/esp32s3/src/sens/sar_nouse.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_NOUSE")
-            .field("sar_nouse", &format_args!("{}", self.sar_nouse().bits()))
+            .field("sar_nouse", &self.sar_nouse())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_NOUSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - no public"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_peri_clk_gate_conf.rs b/esp32s3/src/sens/sar_peri_clk_gate_conf.rs
index 4bdf8f2991..d280fa160f 100644
--- a/esp32s3/src/sens/sar_peri_clk_gate_conf.rs
+++ b/esp32s3/src/sens/sar_peri_clk_gate_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_PERI_CLK_GATE_CONF")
-            .field(
-                "rtc_i2c_clk_en",
-                &format_args!("{}", self.rtc_i2c_clk_en().bit()),
-            )
-            .field(
-                "tsens_clk_en",
-                &format_args!("{}", self.tsens_clk_en().bit()),
-            )
-            .field(
-                "saradc_clk_en",
-                &format_args!("{}", self.saradc_clk_en().bit()),
-            )
-            .field(
-                "iomux_clk_en",
-                &format_args!("{}", self.iomux_clk_en().bit()),
-            )
+            .field("rtc_i2c_clk_en", &self.rtc_i2c_clk_en())
+            .field("tsens_clk_en", &self.tsens_clk_en())
+            .field("saradc_clk_en", &self.saradc_clk_en())
+            .field("iomux_clk_en", &self.iomux_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_PERI_CLK_GATE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 27 - enable rtc i2c clock"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_peri_reset_conf.rs b/esp32s3/src/sens/sar_peri_reset_conf.rs
index 364f2ab222..d672fc6b82 100644
--- a/esp32s3/src/sens/sar_peri_reset_conf.rs
+++ b/esp32s3/src/sens/sar_peri_reset_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_PERI_RESET_CONF")
-            .field(
-                "sar_cocpu_reset",
-                &format_args!("{}", self.sar_cocpu_reset().bit()),
-            )
-            .field(
-                "sar_rtc_i2c_reset",
-                &format_args!("{}", self.sar_rtc_i2c_reset().bit()),
-            )
-            .field(
-                "sar_tsens_reset",
-                &format_args!("{}", self.sar_tsens_reset().bit()),
-            )
-            .field(
-                "sar_saradc_reset",
-                &format_args!("{}", self.sar_saradc_reset().bit()),
-            )
+            .field("sar_cocpu_reset", &self.sar_cocpu_reset())
+            .field("sar_rtc_i2c_reset", &self.sar_rtc_i2c_reset())
+            .field("sar_tsens_reset", &self.sar_tsens_reset())
+            .field("sar_saradc_reset", &self.sar_saradc_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_PERI_RESET_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 25 - enable ulp-riscv reset"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_power_xpd_sar.rs b/esp32s3/src/sens/sar_power_xpd_sar.rs
index fcc14c408a..4e701d54b1 100644
--- a/esp32s3/src/sens/sar_power_xpd_sar.rs
+++ b/esp32s3/src/sens/sar_power_xpd_sar.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_POWER_XPD_SAR")
-            .field(
-                "force_xpd_sar",
-                &format_args!("{}", self.force_xpd_sar().bits()),
-            )
-            .field("sarclk_en", &format_args!("{}", self.sarclk_en().bit()))
+            .field("force_xpd_sar", &self.force_xpd_sar())
+            .field("sarclk_en", &self.sarclk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_POWER_XPD_SAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 29:30 - force power on/off saradc"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_reader1_ctrl.rs b/esp32s3/src/sens/sar_reader1_ctrl.rs
index 28b76e42ec..7af75d2547 100644
--- a/esp32s3/src/sens/sar_reader1_ctrl.rs
+++ b/esp32s3/src/sens/sar_reader1_ctrl.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_READER1_CTRL")
-            .field(
-                "sar_sar1_clk_div",
-                &format_args!("{}", self.sar_sar1_clk_div().bits()),
-            )
-            .field(
-                "sar_sar1_clk_gated",
-                &format_args!("{}", self.sar_sar1_clk_gated().bit()),
-            )
-            .field(
-                "sar_sar1_sample_num",
-                &format_args!("{}", self.sar_sar1_sample_num().bits()),
-            )
-            .field(
-                "sar_sar1_data_inv",
-                &format_args!("{}", self.sar_sar1_data_inv().bit()),
-            )
-            .field(
-                "sar_sar1_int_en",
-                &format_args!("{}", self.sar_sar1_int_en().bit()),
-            )
+            .field("sar_sar1_clk_div", &self.sar_sar1_clk_div())
+            .field("sar_sar1_clk_gated", &self.sar_sar1_clk_gated())
+            .field("sar_sar1_sample_num", &self.sar_sar1_sample_num())
+            .field("sar_sar1_data_inv", &self.sar_sar1_data_inv())
+            .field("sar_sar1_int_en", &self.sar_sar1_int_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_READER1_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - clock divider"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_reader1_status.rs b/esp32s3/src/sens/sar_reader1_status.rs
index 0b392f067c..af4374d944 100644
--- a/esp32s3/src/sens/sar_reader1_status.rs
+++ b/esp32s3/src/sens/sar_reader1_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_READER1_STATUS")
-            .field(
-                "sar_sar1_reader_status",
-                &format_args!("{}", self.sar_sar1_reader_status().bits()),
-            )
+            .field("sar_sar1_reader_status", &self.sar_sar1_reader_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_READER1_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "get saradc1 reader controller status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_reader1_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_READER1_STATUS_SPEC;
 impl crate::RegisterSpec for SAR_READER1_STATUS_SPEC {
diff --git a/esp32s3/src/sens/sar_reader2_ctrl.rs b/esp32s3/src/sens/sar_reader2_ctrl.rs
index 59888c37b6..66ec11bc78 100644
--- a/esp32s3/src/sens/sar_reader2_ctrl.rs
+++ b/esp32s3/src/sens/sar_reader2_ctrl.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_READER2_CTRL")
-            .field(
-                "sar_sar2_clk_div",
-                &format_args!("{}", self.sar_sar2_clk_div().bits()),
-            )
-            .field(
-                "sar_sar2_wait_arb_cycle",
-                &format_args!("{}", self.sar_sar2_wait_arb_cycle().bits()),
-            )
-            .field(
-                "sar_sar2_clk_gated",
-                &format_args!("{}", self.sar_sar2_clk_gated().bit()),
-            )
-            .field(
-                "sar_sar2_sample_num",
-                &format_args!("{}", self.sar_sar2_sample_num().bits()),
-            )
-            .field(
-                "sar_sar2_data_inv",
-                &format_args!("{}", self.sar_sar2_data_inv().bit()),
-            )
-            .field(
-                "sar_sar2_int_en",
-                &format_args!("{}", self.sar_sar2_int_en().bit()),
-            )
+            .field("sar_sar2_clk_div", &self.sar_sar2_clk_div())
+            .field("sar_sar2_wait_arb_cycle", &self.sar_sar2_wait_arb_cycle())
+            .field("sar_sar2_clk_gated", &self.sar_sar2_clk_gated())
+            .field("sar_sar2_sample_num", &self.sar_sar2_sample_num())
+            .field("sar_sar2_data_inv", &self.sar_sar2_data_inv())
+            .field("sar_sar2_int_en", &self.sar_sar2_int_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_READER2_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - clock divider"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_reader2_status.rs b/esp32s3/src/sens/sar_reader2_status.rs
index 683b0e64d5..ed37794d25 100644
--- a/esp32s3/src/sens/sar_reader2_status.rs
+++ b/esp32s3/src/sens/sar_reader2_status.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_READER2_STATUS")
-            .field(
-                "sar_sar2_reader_status",
-                &format_args!("{}", self.sar_sar2_reader_status().bits()),
-            )
+            .field("sar_sar2_reader_status", &self.sar_sar2_reader_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_READER2_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "get saradc1 reader controller status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_reader2_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_READER2_STATUS_SPEC;
 impl crate::RegisterSpec for SAR_READER2_STATUS_SPEC {
diff --git a/esp32s3/src/sens/sar_sardate.rs b/esp32s3/src/sens/sar_sardate.rs
index 209ef8070b..8490afe25d 100644
--- a/esp32s3/src/sens/sar_sardate.rs
+++ b/esp32s3/src/sens/sar_sardate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SARDATE")
-            .field("sar_date", &format_args!("{}", self.sar_date().bits()))
+            .field("sar_date", &self.sar_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SARDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - version"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_slave_addr1.rs b/esp32s3/src/sens/sar_slave_addr1.rs
index d94a80772a..b5e3efb81f 100644
--- a/esp32s3/src/sens/sar_slave_addr1.rs
+++ b/esp32s3/src/sens/sar_slave_addr1.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR1")
-            .field(
-                "sar_i2c_slave_addr1",
-                &format_args!("{}", self.sar_i2c_slave_addr1().bits()),
-            )
-            .field(
-                "sar_i2c_slave_addr0",
-                &format_args!("{}", self.sar_i2c_slave_addr0().bits()),
-            )
-            .field(
-                "sar_saradc_meas_status",
-                &format_args!("{}", self.sar_saradc_meas_status().bits()),
-            )
+            .field("sar_i2c_slave_addr1", &self.sar_i2c_slave_addr1())
+            .field("sar_i2c_slave_addr0", &self.sar_i2c_slave_addr0())
+            .field("sar_saradc_meas_status", &self.sar_saradc_meas_status())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - configure i2c slave address1"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_slave_addr2.rs b/esp32s3/src/sens/sar_slave_addr2.rs
index 3fb7205d6e..987d0bf655 100644
--- a/esp32s3/src/sens/sar_slave_addr2.rs
+++ b/esp32s3/src/sens/sar_slave_addr2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR2")
-            .field(
-                "sar_i2c_slave_addr3",
-                &format_args!("{}", self.sar_i2c_slave_addr3().bits()),
-            )
-            .field(
-                "sar_i2c_slave_addr2",
-                &format_args!("{}", self.sar_i2c_slave_addr2().bits()),
-            )
+            .field("sar_i2c_slave_addr3", &self.sar_i2c_slave_addr3())
+            .field("sar_i2c_slave_addr2", &self.sar_i2c_slave_addr2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - configure i2c slave address3"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_slave_addr3.rs b/esp32s3/src/sens/sar_slave_addr3.rs
index 005fbdc778..a5fbc48498 100644
--- a/esp32s3/src/sens/sar_slave_addr3.rs
+++ b/esp32s3/src/sens/sar_slave_addr3.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR3")
-            .field(
-                "sar_i2c_slave_addr5",
-                &format_args!("{}", self.sar_i2c_slave_addr5().bits()),
-            )
-            .field(
-                "sar_i2c_slave_addr4",
-                &format_args!("{}", self.sar_i2c_slave_addr4().bits()),
-            )
+            .field("sar_i2c_slave_addr5", &self.sar_i2c_slave_addr5())
+            .field("sar_i2c_slave_addr4", &self.sar_i2c_slave_addr4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - configure i2c slave address5"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_slave_addr4.rs b/esp32s3/src/sens/sar_slave_addr4.rs
index 24937373ad..23a8f8a11b 100644
--- a/esp32s3/src/sens/sar_slave_addr4.rs
+++ b/esp32s3/src/sens/sar_slave_addr4.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_SLAVE_ADDR4")
-            .field(
-                "sar_i2c_slave_addr7",
-                &format_args!("{}", self.sar_i2c_slave_addr7().bits()),
-            )
-            .field(
-                "sar_i2c_slave_addr6",
-                &format_args!("{}", self.sar_i2c_slave_addr6().bits()),
-            )
+            .field("sar_i2c_slave_addr7", &self.sar_i2c_slave_addr7())
+            .field("sar_i2c_slave_addr6", &self.sar_i2c_slave_addr6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_SLAVE_ADDR4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - configure i2c slave address7"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_chn_st.rs b/esp32s3/src/sens/sar_touch_chn_st.rs
index 51b8018c5a..18cd200dd0 100644
--- a/esp32s3/src/sens/sar_touch_chn_st.rs
+++ b/esp32s3/src/sens/sar_touch_chn_st.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_CHN_ST")
-            .field(
-                "sar_touch_pad_active",
-                &format_args!("{}", self.sar_touch_pad_active().bits()),
-            )
-            .field(
-                "sar_touch_meas_done",
-                &format_args!("{}", self.sar_touch_meas_done().bit()),
-            )
+            .field("sar_touch_pad_active", &self.sar_touch_pad_active())
+            .field("sar_touch_meas_done", &self.sar_touch_meas_done())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_CHN_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 15:29 - Clear touch channel"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_conf.rs b/esp32s3/src/sens/sar_touch_conf.rs
index 23b6961e71..df331d3749 100644
--- a/esp32s3/src/sens/sar_touch_conf.rs
+++ b/esp32s3/src/sens/sar_touch_conf.rs
@@ -69,43 +69,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_CONF")
-            .field(
-                "sar_touch_outen",
-                &format_args!("{}", self.sar_touch_outen().bits()),
-            )
-            .field(
-                "sar_touch_data_sel",
-                &format_args!("{}", self.sar_touch_data_sel().bits()),
-            )
-            .field(
-                "sar_touch_denoise_end",
-                &format_args!("{}", self.sar_touch_denoise_end().bit()),
-            )
-            .field(
-                "sar_touch_unit_end",
-                &format_args!("{}", self.sar_touch_unit_end().bit()),
-            )
-            .field(
-                "sar_touch_approach_pad2",
-                &format_args!("{}", self.sar_touch_approach_pad2().bits()),
-            )
-            .field(
-                "sar_touch_approach_pad1",
-                &format_args!("{}", self.sar_touch_approach_pad1().bits()),
-            )
-            .field(
-                "sar_touch_approach_pad0",
-                &format_args!("{}", self.sar_touch_approach_pad0().bits()),
-            )
+            .field("sar_touch_outen", &self.sar_touch_outen())
+            .field("sar_touch_data_sel", &self.sar_touch_data_sel())
+            .field("sar_touch_denoise_end", &self.sar_touch_denoise_end())
+            .field("sar_touch_unit_end", &self.sar_touch_unit_end())
+            .field("sar_touch_approach_pad2", &self.sar_touch_approach_pad2())
+            .field("sar_touch_approach_pad1", &self.sar_touch_approach_pad1())
+            .field("sar_touch_approach_pad0", &self.sar_touch_approach_pad0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:14 - touch controller output enable"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_denoise.rs b/esp32s3/src/sens/sar_touch_denoise.rs
index 9626d7b60c..c98223c1ef 100644
--- a/esp32s3/src/sens/sar_touch_denoise.rs
+++ b/esp32s3/src/sens/sar_touch_denoise.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_DENOISE")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_DENOISE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "configure touch controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_denoise::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_DENOISE_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_DENOISE_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status0.rs b/esp32s3/src/sens/sar_touch_status0.rs
index 07351bc334..d539e9395e 100644
--- a/esp32s3/src/sens/sar_touch_status0.rs
+++ b/esp32s3/src/sens/sar_touch_status0.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS0")
-            .field(
-                "sar_touch_scan_curr",
-                &format_args!("{}", self.sar_touch_scan_curr().bits()),
-            )
+            .field("sar_touch_scan_curr", &self.sar_touch_scan_curr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "get touch scan status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS0_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS0_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status1.rs b/esp32s3/src/sens/sar_touch_status1.rs
index c02fb8cadc..fae85df782 100644
--- a/esp32s3/src/sens/sar_touch_status1.rs
+++ b/esp32s3/src/sens/sar_touch_status1.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS1")
-            .field(
-                "sar_touch_pad1_data",
-                &format_args!("{}", self.sar_touch_pad1_data().bits()),
-            )
-            .field(
-                "sar_touch_pad1_debounce",
-                &format_args!("{}", self.sar_touch_pad1_debounce().bits()),
-            )
+            .field("sar_touch_pad1_data", &self.sar_touch_pad1_data())
+            .field("sar_touch_pad1_debounce", &self.sar_touch_pad1_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of touch pad 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS1_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS1_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status10.rs b/esp32s3/src/sens/sar_touch_status10.rs
index 60425f5c10..c85d92744c 100644
--- a/esp32s3/src/sens/sar_touch_status10.rs
+++ b/esp32s3/src/sens/sar_touch_status10.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS10")
-            .field(
-                "sar_touch_pad10_data",
-                &format_args!("{}", self.sar_touch_pad10_data().bits()),
-            )
-            .field(
-                "sar_touch_pad10_debounce",
-                &format_args!("{}", self.sar_touch_pad10_debounce().bits()),
-            )
+            .field("sar_touch_pad10_data", &self.sar_touch_pad10_data())
+            .field("sar_touch_pad10_debounce", &self.sar_touch_pad10_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of touch pad 10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status10::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS10_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS10_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status11.rs b/esp32s3/src/sens/sar_touch_status11.rs
index 4ad6d01c61..cd64e20f7e 100644
--- a/esp32s3/src/sens/sar_touch_status11.rs
+++ b/esp32s3/src/sens/sar_touch_status11.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS11")
-            .field(
-                "sar_touch_pad11_data",
-                &format_args!("{}", self.sar_touch_pad11_data().bits()),
-            )
-            .field(
-                "sar_touch_pad11_debounce",
-                &format_args!("{}", self.sar_touch_pad11_debounce().bits()),
-            )
+            .field("sar_touch_pad11_data", &self.sar_touch_pad11_data())
+            .field("sar_touch_pad11_debounce", &self.sar_touch_pad11_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of touch pad 11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status11::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS11_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS11_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status12.rs b/esp32s3/src/sens/sar_touch_status12.rs
index 5b489eaf56..b4090a51ae 100644
--- a/esp32s3/src/sens/sar_touch_status12.rs
+++ b/esp32s3/src/sens/sar_touch_status12.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS12")
-            .field(
-                "sar_touch_pad12_data",
-                &format_args!("{}", self.sar_touch_pad12_data().bits()),
-            )
-            .field(
-                "sar_touch_pad12_debounce",
-                &format_args!("{}", self.sar_touch_pad12_debounce().bits()),
-            )
+            .field("sar_touch_pad12_data", &self.sar_touch_pad12_data())
+            .field("sar_touch_pad12_debounce", &self.sar_touch_pad12_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of touch pad 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status12::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS12_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS12_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status13.rs b/esp32s3/src/sens/sar_touch_status13.rs
index bbe78f0dd7..8565264084 100644
--- a/esp32s3/src/sens/sar_touch_status13.rs
+++ b/esp32s3/src/sens/sar_touch_status13.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS13")
-            .field(
-                "sar_touch_pad13_data",
-                &format_args!("{}", self.sar_touch_pad13_data().bits()),
-            )
-            .field(
-                "sar_touch_pad13_debounce",
-                &format_args!("{}", self.sar_touch_pad13_debounce().bits()),
-            )
+            .field("sar_touch_pad13_data", &self.sar_touch_pad13_data())
+            .field("sar_touch_pad13_debounce", &self.sar_touch_pad13_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of touch pad 13\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status13::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS13_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS13_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status14.rs b/esp32s3/src/sens/sar_touch_status14.rs
index fff516be76..ac316b1ab3 100644
--- a/esp32s3/src/sens/sar_touch_status14.rs
+++ b/esp32s3/src/sens/sar_touch_status14.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS14")
-            .field(
-                "sar_touch_pad14_data",
-                &format_args!("{}", self.sar_touch_pad14_data().bits()),
-            )
-            .field(
-                "sar_touch_pad14_debounce",
-                &format_args!("{}", self.sar_touch_pad14_debounce().bits()),
-            )
+            .field("sar_touch_pad14_data", &self.sar_touch_pad14_data())
+            .field("sar_touch_pad14_debounce", &self.sar_touch_pad14_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of touch pad 14\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status14::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS14_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS14_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status15.rs b/esp32s3/src/sens/sar_touch_status15.rs
index 5037f4327b..7cdb9a25c4 100644
--- a/esp32s3/src/sens/sar_touch_status15.rs
+++ b/esp32s3/src/sens/sar_touch_status15.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS15")
-            .field(
-                "sar_touch_slp_data",
-                &format_args!("{}", self.sar_touch_slp_data().bits()),
-            )
-            .field(
-                "sar_touch_slp_debounce",
-                &format_args!("{}", self.sar_touch_slp_debounce().bits()),
-            )
+            .field("sar_touch_slp_data", &self.sar_touch_slp_data())
+            .field("sar_touch_slp_debounce", &self.sar_touch_slp_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS15_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of sleep pad\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status15::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS15_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS15_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status16.rs b/esp32s3/src/sens/sar_touch_status16.rs
index 09924c6b21..8f1c9fdcee 100644
--- a/esp32s3/src/sens/sar_touch_status16.rs
+++ b/esp32s3/src/sens/sar_touch_status16.rs
@@ -36,29 +36,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("SAR_TOUCH_STATUS16")
             .field(
                 "sar_touch_approach_pad2_cnt",
-                &format_args!("{}", self.sar_touch_approach_pad2_cnt().bits()),
+                &self.sar_touch_approach_pad2_cnt(),
             )
             .field(
                 "sar_touch_approach_pad1_cnt",
-                &format_args!("{}", self.sar_touch_approach_pad1_cnt().bits()),
+                &self.sar_touch_approach_pad1_cnt(),
             )
             .field(
                 "sar_touch_approach_pad0_cnt",
-                &format_args!("{}", self.sar_touch_approach_pad0_cnt().bits()),
+                &self.sar_touch_approach_pad0_cnt(),
             )
             .field(
                 "sar_touch_slp_approach_cnt",
-                &format_args!("{}", self.sar_touch_slp_approach_cnt().bits()),
+                &self.sar_touch_slp_approach_cnt(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS16_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of approach mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status16::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS16_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS16_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status2.rs b/esp32s3/src/sens/sar_touch_status2.rs
index a1af2de371..d60ce4f592 100644
--- a/esp32s3/src/sens/sar_touch_status2.rs
+++ b/esp32s3/src/sens/sar_touch_status2.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS2")
-            .field(
-                "sar_touch_pad2_data",
-                &format_args!("{}", self.sar_touch_pad2_data().bits()),
-            )
-            .field(
-                "sar_touch_pad2_debounce",
-                &format_args!("{}", self.sar_touch_pad2_debounce().bits()),
-            )
+            .field("sar_touch_pad2_data", &self.sar_touch_pad2_data())
+            .field("sar_touch_pad2_debounce", &self.sar_touch_pad2_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of touch pad 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS2_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS2_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status3.rs b/esp32s3/src/sens/sar_touch_status3.rs
index dca079a61e..8bd8850d4a 100644
--- a/esp32s3/src/sens/sar_touch_status3.rs
+++ b/esp32s3/src/sens/sar_touch_status3.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS3")
-            .field(
-                "sar_touch_pad3_data",
-                &format_args!("{}", self.sar_touch_pad3_data().bits()),
-            )
-            .field(
-                "sar_touch_pad3_debounce",
-                &format_args!("{}", self.sar_touch_pad3_debounce().bits()),
-            )
+            .field("sar_touch_pad3_data", &self.sar_touch_pad3_data())
+            .field("sar_touch_pad3_debounce", &self.sar_touch_pad3_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of touch pad 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS3_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS3_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status4.rs b/esp32s3/src/sens/sar_touch_status4.rs
index 9c106df653..ccdc157403 100644
--- a/esp32s3/src/sens/sar_touch_status4.rs
+++ b/esp32s3/src/sens/sar_touch_status4.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS4")
-            .field(
-                "sar_touch_pad4_data",
-                &format_args!("{}", self.sar_touch_pad4_data().bits()),
-            )
-            .field(
-                "sar_touch_pad4_debounce",
-                &format_args!("{}", self.sar_touch_pad4_debounce().bits()),
-            )
+            .field("sar_touch_pad4_data", &self.sar_touch_pad4_data())
+            .field("sar_touch_pad4_debounce", &self.sar_touch_pad4_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of touch pad 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS4_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS4_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status5.rs b/esp32s3/src/sens/sar_touch_status5.rs
index 382385fcbd..ff1a7a2114 100644
--- a/esp32s3/src/sens/sar_touch_status5.rs
+++ b/esp32s3/src/sens/sar_touch_status5.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS5")
-            .field(
-                "sar_touch_pad5_data",
-                &format_args!("{}", self.sar_touch_pad5_data().bits()),
-            )
-            .field(
-                "sar_touch_pad5_debounce",
-                &format_args!("{}", self.sar_touch_pad5_debounce().bits()),
-            )
+            .field("sar_touch_pad5_data", &self.sar_touch_pad5_data())
+            .field("sar_touch_pad5_debounce", &self.sar_touch_pad5_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of touch pad 5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS5_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS5_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status6.rs b/esp32s3/src/sens/sar_touch_status6.rs
index 989f728f88..31e7b2a887 100644
--- a/esp32s3/src/sens/sar_touch_status6.rs
+++ b/esp32s3/src/sens/sar_touch_status6.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS6")
-            .field(
-                "sar_touch_pad6_data",
-                &format_args!("{}", self.sar_touch_pad6_data().bits()),
-            )
-            .field(
-                "sar_touch_pad6_debounce",
-                &format_args!("{}", self.sar_touch_pad6_debounce().bits()),
-            )
+            .field("sar_touch_pad6_data", &self.sar_touch_pad6_data())
+            .field("sar_touch_pad6_debounce", &self.sar_touch_pad6_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of touch pad 6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS6_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS6_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status7.rs b/esp32s3/src/sens/sar_touch_status7.rs
index ac07624bda..b0beafe251 100644
--- a/esp32s3/src/sens/sar_touch_status7.rs
+++ b/esp32s3/src/sens/sar_touch_status7.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS7")
-            .field(
-                "sar_touch_pad7_data",
-                &format_args!("{}", self.sar_touch_pad7_data().bits()),
-            )
-            .field(
-                "sar_touch_pad7_debounce",
-                &format_args!("{}", self.sar_touch_pad7_debounce().bits()),
-            )
+            .field("sar_touch_pad7_data", &self.sar_touch_pad7_data())
+            .field("sar_touch_pad7_debounce", &self.sar_touch_pad7_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of touch pad 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status7::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS7_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS7_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status8.rs b/esp32s3/src/sens/sar_touch_status8.rs
index b494ea9f8b..ce5aa7abf2 100644
--- a/esp32s3/src/sens/sar_touch_status8.rs
+++ b/esp32s3/src/sens/sar_touch_status8.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS8")
-            .field(
-                "sar_touch_pad8_data",
-                &format_args!("{}", self.sar_touch_pad8_data().bits()),
-            )
-            .field(
-                "sar_touch_pad8_debounce",
-                &format_args!("{}", self.sar_touch_pad8_debounce().bits()),
-            )
+            .field("sar_touch_pad8_data", &self.sar_touch_pad8_data())
+            .field("sar_touch_pad8_debounce", &self.sar_touch_pad8_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of touch pad 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS8_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS8_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_status9.rs b/esp32s3/src/sens/sar_touch_status9.rs
index f3e67f22bf..e68d02bdda 100644
--- a/esp32s3/src/sens/sar_touch_status9.rs
+++ b/esp32s3/src/sens/sar_touch_status9.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_STATUS9")
-            .field(
-                "sar_touch_pad9_data",
-                &format_args!("{}", self.sar_touch_pad9_data().bits()),
-            )
-            .field(
-                "sar_touch_pad9_debounce",
-                &format_args!("{}", self.sar_touch_pad9_debounce().bits()),
-            )
+            .field("sar_touch_pad9_data", &self.sar_touch_pad9_data())
+            .field("sar_touch_pad9_debounce", &self.sar_touch_pad9_debounce())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_STATUS9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "touch channel status of touch pad 9\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sar_touch_status9::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SAR_TOUCH_STATUS9_SPEC;
 impl crate::RegisterSpec for SAR_TOUCH_STATUS9_SPEC {
diff --git a/esp32s3/src/sens/sar_touch_thres1.rs b/esp32s3/src/sens/sar_touch_thres1.rs
index affdd26d62..1c3696eb44 100644
--- a/esp32s3/src/sens/sar_touch_thres1.rs
+++ b/esp32s3/src/sens/sar_touch_thres1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES1")
-            .field(
-                "sar_touch_out_th1",
-                &format_args!("{}", self.sar_touch_out_th1().bits()),
-            )
+            .field("sar_touch_out_th1", &self.sar_touch_out_th1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 1"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_thres10.rs b/esp32s3/src/sens/sar_touch_thres10.rs
index 90d298ce8f..0c32a72e36 100644
--- a/esp32s3/src/sens/sar_touch_thres10.rs
+++ b/esp32s3/src/sens/sar_touch_thres10.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES10")
-            .field(
-                "sar_touch_out_th10",
-                &format_args!("{}", self.sar_touch_out_th10().bits()),
-            )
+            .field("sar_touch_out_th10", &self.sar_touch_out_th10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 10"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_thres11.rs b/esp32s3/src/sens/sar_touch_thres11.rs
index 170e40bea1..02ee9db2eb 100644
--- a/esp32s3/src/sens/sar_touch_thres11.rs
+++ b/esp32s3/src/sens/sar_touch_thres11.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES11")
-            .field(
-                "sar_touch_out_th11",
-                &format_args!("{}", self.sar_touch_out_th11().bits()),
-            )
+            .field("sar_touch_out_th11", &self.sar_touch_out_th11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 11"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_thres12.rs b/esp32s3/src/sens/sar_touch_thres12.rs
index 0f2d34a25e..add4dfe890 100644
--- a/esp32s3/src/sens/sar_touch_thres12.rs
+++ b/esp32s3/src/sens/sar_touch_thres12.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES12")
-            .field(
-                "sar_touch_out_th12",
-                &format_args!("{}", self.sar_touch_out_th12().bits()),
-            )
+            .field("sar_touch_out_th12", &self.sar_touch_out_th12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 12"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_thres13.rs b/esp32s3/src/sens/sar_touch_thres13.rs
index 720f36413a..aa73daeee5 100644
--- a/esp32s3/src/sens/sar_touch_thres13.rs
+++ b/esp32s3/src/sens/sar_touch_thres13.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES13")
-            .field(
-                "sar_touch_out_th13",
-                &format_args!("{}", self.sar_touch_out_th13().bits()),
-            )
+            .field("sar_touch_out_th13", &self.sar_touch_out_th13())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 13"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_thres14.rs b/esp32s3/src/sens/sar_touch_thres14.rs
index d9d2fa513a..80a71bd45d 100644
--- a/esp32s3/src/sens/sar_touch_thres14.rs
+++ b/esp32s3/src/sens/sar_touch_thres14.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES14")
-            .field(
-                "sar_touch_out_th14",
-                &format_args!("{}", self.sar_touch_out_th14().bits()),
-            )
+            .field("sar_touch_out_th14", &self.sar_touch_out_th14())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 14"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_thres2.rs b/esp32s3/src/sens/sar_touch_thres2.rs
index b0aaed9648..feb2f052a9 100644
--- a/esp32s3/src/sens/sar_touch_thres2.rs
+++ b/esp32s3/src/sens/sar_touch_thres2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES2")
-            .field(
-                "sar_touch_out_th2",
-                &format_args!("{}", self.sar_touch_out_th2().bits()),
-            )
+            .field("sar_touch_out_th2", &self.sar_touch_out_th2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 2"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_thres3.rs b/esp32s3/src/sens/sar_touch_thres3.rs
index db1a4f246d..ed66d7bccb 100644
--- a/esp32s3/src/sens/sar_touch_thres3.rs
+++ b/esp32s3/src/sens/sar_touch_thres3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES3")
-            .field(
-                "sar_touch_out_th3",
-                &format_args!("{}", self.sar_touch_out_th3().bits()),
-            )
+            .field("sar_touch_out_th3", &self.sar_touch_out_th3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 3"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_thres4.rs b/esp32s3/src/sens/sar_touch_thres4.rs
index 8ca51ae931..5e9b933b1f 100644
--- a/esp32s3/src/sens/sar_touch_thres4.rs
+++ b/esp32s3/src/sens/sar_touch_thres4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES4")
-            .field(
-                "sar_touch_out_th4",
-                &format_args!("{}", self.sar_touch_out_th4().bits()),
-            )
+            .field("sar_touch_out_th4", &self.sar_touch_out_th4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 4"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_thres5.rs b/esp32s3/src/sens/sar_touch_thres5.rs
index 8b27860798..78350bd437 100644
--- a/esp32s3/src/sens/sar_touch_thres5.rs
+++ b/esp32s3/src/sens/sar_touch_thres5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES5")
-            .field(
-                "sar_touch_out_th5",
-                &format_args!("{}", self.sar_touch_out_th5().bits()),
-            )
+            .field("sar_touch_out_th5", &self.sar_touch_out_th5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 5"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_thres6.rs b/esp32s3/src/sens/sar_touch_thres6.rs
index b64c3fcc07..f13b314f46 100644
--- a/esp32s3/src/sens/sar_touch_thres6.rs
+++ b/esp32s3/src/sens/sar_touch_thres6.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES6")
-            .field(
-                "sar_touch_out_th6",
-                &format_args!("{}", self.sar_touch_out_th6().bits()),
-            )
+            .field("sar_touch_out_th6", &self.sar_touch_out_th6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 6"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_thres7.rs b/esp32s3/src/sens/sar_touch_thres7.rs
index d6da90ab46..ae8bc51591 100644
--- a/esp32s3/src/sens/sar_touch_thres7.rs
+++ b/esp32s3/src/sens/sar_touch_thres7.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES7")
-            .field(
-                "sar_touch_out_th7",
-                &format_args!("{}", self.sar_touch_out_th7().bits()),
-            )
+            .field("sar_touch_out_th7", &self.sar_touch_out_th7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 7"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_thres8.rs b/esp32s3/src/sens/sar_touch_thres8.rs
index 2ac1d5ff20..b6fd0d1552 100644
--- a/esp32s3/src/sens/sar_touch_thres8.rs
+++ b/esp32s3/src/sens/sar_touch_thres8.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES8")
-            .field(
-                "sar_touch_out_th8",
-                &format_args!("{}", self.sar_touch_out_th8().bits()),
-            )
+            .field("sar_touch_out_th8", &self.sar_touch_out_th8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 8"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_touch_thres9.rs b/esp32s3/src/sens/sar_touch_thres9.rs
index 136683f24a..51b80416bd 100644
--- a/esp32s3/src/sens/sar_touch_thres9.rs
+++ b/esp32s3/src/sens/sar_touch_thres9.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TOUCH_THRES9")
-            .field(
-                "sar_touch_out_th9",
-                &format_args!("{}", self.sar_touch_out_th9().bits()),
-            )
+            .field("sar_touch_out_th9", &self.sar_touch_out_th9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TOUCH_THRES9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Finger threshold for touch pad 9"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_tsens_ctrl.rs b/esp32s3/src/sens/sar_tsens_ctrl.rs
index 1d37530145..dc0ba35bf5 100644
--- a/esp32s3/src/sens/sar_tsens_ctrl.rs
+++ b/esp32s3/src/sens/sar_tsens_ctrl.rs
@@ -76,47 +76,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TSENS_CTRL")
-            .field(
-                "sar_tsens_out",
-                &format_args!("{}", self.sar_tsens_out().bits()),
-            )
-            .field(
-                "sar_tsens_ready",
-                &format_args!("{}", self.sar_tsens_ready().bit()),
-            )
-            .field(
-                "sar_tsens_int_en",
-                &format_args!("{}", self.sar_tsens_int_en().bit()),
-            )
-            .field(
-                "sar_tsens_in_inv",
-                &format_args!("{}", self.sar_tsens_in_inv().bit()),
-            )
-            .field(
-                "sar_tsens_clk_div",
-                &format_args!("{}", self.sar_tsens_clk_div().bits()),
-            )
-            .field(
-                "sar_tsens_power_up",
-                &format_args!("{}", self.sar_tsens_power_up().bit()),
-            )
-            .field(
-                "sar_tsens_power_up_force",
-                &format_args!("{}", self.sar_tsens_power_up_force().bit()),
-            )
-            .field(
-                "sar_tsens_dump_out",
-                &format_args!("{}", self.sar_tsens_dump_out().bit()),
-            )
+            .field("sar_tsens_out", &self.sar_tsens_out())
+            .field("sar_tsens_ready", &self.sar_tsens_ready())
+            .field("sar_tsens_int_en", &self.sar_tsens_int_en())
+            .field("sar_tsens_in_inv", &self.sar_tsens_in_inv())
+            .field("sar_tsens_clk_div", &self.sar_tsens_clk_div())
+            .field("sar_tsens_power_up", &self.sar_tsens_power_up())
+            .field("sar_tsens_power_up_force", &self.sar_tsens_power_up_force())
+            .field("sar_tsens_dump_out", &self.sar_tsens_dump_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TSENS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - enable temperature sensor to send out interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/sens/sar_tsens_ctrl2.rs b/esp32s3/src/sens/sar_tsens_ctrl2.rs
index 621dd318a0..e40e7dd1d5 100644
--- a/esp32s3/src/sens/sar_tsens_ctrl2.rs
+++ b/esp32s3/src/sens/sar_tsens_ctrl2.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SAR_TSENS_CTRL2")
-            .field(
-                "sar_tsens_xpd_wait",
-                &format_args!("{}", self.sar_tsens_xpd_wait().bits()),
-            )
-            .field(
-                "sar_tsens_xpd_force",
-                &format_args!("{}", self.sar_tsens_xpd_force().bits()),
-            )
-            .field(
-                "sar_tsens_clk_inv",
-                &format_args!("{}", self.sar_tsens_clk_inv().bit()),
-            )
+            .field("sar_tsens_xpd_wait", &self.sar_tsens_xpd_wait())
+            .field("sar_tsens_xpd_force", &self.sar_tsens_xpd_force())
+            .field("sar_tsens_clk_inv", &self.sar_tsens_clk_inv())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SAR_TSENS_CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - no public"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/apb_peripheral_access_0.rs b/esp32s3/src/sensitive/apb_peripheral_access_0.rs
index 1471877a45..7dcd5377f6 100644
--- a/esp32s3/src/sensitive/apb_peripheral_access_0.rs
+++ b/esp32s3/src/sensitive/apb_peripheral_access_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB_PERIPHERAL_ACCESS_0")
             .field(
                 "apb_peripheral_access_lock",
-                &format_args!("{}", self.apb_peripheral_access_lock().bit()),
+                &self.apb_peripheral_access_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_PERIPHERAL_ACCESS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock APB peripheral Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/apb_peripheral_access_1.rs b/esp32s3/src/sensitive/apb_peripheral_access_1.rs
index 00385aa7e4..b1102344b6 100644
--- a/esp32s3/src/sensitive/apb_peripheral_access_1.rs
+++ b/esp32s3/src/sensitive/apb_peripheral_access_1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("APB_PERIPHERAL_ACCESS_1")
             .field(
                 "apb_peripheral_access_split_burst",
-                &format_args!("{}", self.apb_peripheral_access_split_burst().bit()),
+                &self.apb_peripheral_access_split_burst(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<APB_PERIPHERAL_ACCESS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to support split function for AHB access to APB peripherals."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/backup_bus_pms_constrain_0.rs b/esp32s3/src/sensitive/backup_bus_pms_constrain_0.rs
index 35462e67fb..bde1c0c26e 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_0")
             .field(
                 "backup_bus_pms_constrain_lock",
-                &format_args!("{}", self.backup_bus_pms_constrain_lock().bit()),
+                &self.backup_bus_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock BackUp permission configuration registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/backup_bus_pms_constrain_1.rs b/esp32s3/src/sensitive/backup_bus_pms_constrain_1.rs
index 1c468d49c0..a838f1d273 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_constrain_1.rs
@@ -127,65 +127,59 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_1")
             .field(
                 "backup_bus_pms_constrain_uart",
-                &format_args!("{}", self.backup_bus_pms_constrain_uart().bits()),
+                &self.backup_bus_pms_constrain_uart(),
             )
             .field(
                 "backup_bus_pms_constrain_g0spi_1",
-                &format_args!("{}", self.backup_bus_pms_constrain_g0spi_1().bits()),
+                &self.backup_bus_pms_constrain_g0spi_1(),
             )
             .field(
                 "backup_bus_pms_constrain_g0spi_0",
-                &format_args!("{}", self.backup_bus_pms_constrain_g0spi_0().bits()),
+                &self.backup_bus_pms_constrain_g0spi_0(),
             )
             .field(
                 "backup_bus_pms_constrain_gpio",
-                &format_args!("{}", self.backup_bus_pms_constrain_gpio().bits()),
+                &self.backup_bus_pms_constrain_gpio(),
             )
             .field(
                 "backup_bus_pms_constrain_fe2",
-                &format_args!("{}", self.backup_bus_pms_constrain_fe2().bits()),
+                &self.backup_bus_pms_constrain_fe2(),
             )
             .field(
                 "backup_bus_pms_constrain_fe",
-                &format_args!("{}", self.backup_bus_pms_constrain_fe().bits()),
+                &self.backup_bus_pms_constrain_fe(),
             )
             .field(
                 "backup_bus_pms_constrain_rtc",
-                &format_args!("{}", self.backup_bus_pms_constrain_rtc().bits()),
+                &self.backup_bus_pms_constrain_rtc(),
             )
             .field(
                 "backup_bus_pms_constrain_io_mux",
-                &format_args!("{}", self.backup_bus_pms_constrain_io_mux().bits()),
+                &self.backup_bus_pms_constrain_io_mux(),
             )
             .field(
                 "backup_bus_pms_constrain_hinf",
-                &format_args!("{}", self.backup_bus_pms_constrain_hinf().bits()),
+                &self.backup_bus_pms_constrain_hinf(),
             )
             .field(
                 "backup_bus_pms_constrain_misc",
-                &format_args!("{}", self.backup_bus_pms_constrain_misc().bits()),
+                &self.backup_bus_pms_constrain_misc(),
             )
             .field(
                 "backup_bus_pms_constrain_i2c",
-                &format_args!("{}", self.backup_bus_pms_constrain_i2c().bits()),
+                &self.backup_bus_pms_constrain_i2c(),
             )
             .field(
                 "backup_bus_pms_constrain_i2s0",
-                &format_args!("{}", self.backup_bus_pms_constrain_i2s0().bits()),
+                &self.backup_bus_pms_constrain_i2s0(),
             )
             .field(
                 "backup_bus_pms_constrain_uart1",
-                &format_args!("{}", self.backup_bus_pms_constrain_uart1().bits()),
+                &self.backup_bus_pms_constrain_uart1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - BackUp access uart permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/backup_bus_pms_constrain_2.rs b/esp32s3/src/sensitive/backup_bus_pms_constrain_2.rs
index 8a92c44dbe..f1469c2ead 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_constrain_2.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_constrain_2.rs
@@ -136,69 +136,63 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_2")
             .field(
                 "backup_bus_pms_constrain_bt",
-                &format_args!("{}", self.backup_bus_pms_constrain_bt().bits()),
+                &self.backup_bus_pms_constrain_bt(),
             )
             .field(
                 "backup_bus_pms_constrain_i2c_ext0",
-                &format_args!("{}", self.backup_bus_pms_constrain_i2c_ext0().bits()),
+                &self.backup_bus_pms_constrain_i2c_ext0(),
             )
             .field(
                 "backup_bus_pms_constrain_uhci0",
-                &format_args!("{}", self.backup_bus_pms_constrain_uhci0().bits()),
+                &self.backup_bus_pms_constrain_uhci0(),
             )
             .field(
                 "backup_bus_pms_constrain_slchost",
-                &format_args!("{}", self.backup_bus_pms_constrain_slchost().bits()),
+                &self.backup_bus_pms_constrain_slchost(),
             )
             .field(
                 "backup_bus_pms_constrain_rmt",
-                &format_args!("{}", self.backup_bus_pms_constrain_rmt().bits()),
+                &self.backup_bus_pms_constrain_rmt(),
             )
             .field(
                 "backup_bus_pms_constrain_pcnt",
-                &format_args!("{}", self.backup_bus_pms_constrain_pcnt().bits()),
+                &self.backup_bus_pms_constrain_pcnt(),
             )
             .field(
                 "backup_bus_pms_constrain_slc",
-                &format_args!("{}", self.backup_bus_pms_constrain_slc().bits()),
+                &self.backup_bus_pms_constrain_slc(),
             )
             .field(
                 "backup_bus_pms_constrain_ledc",
-                &format_args!("{}", self.backup_bus_pms_constrain_ledc().bits()),
+                &self.backup_bus_pms_constrain_ledc(),
             )
             .field(
                 "backup_bus_pms_constrain_backup",
-                &format_args!("{}", self.backup_bus_pms_constrain_backup().bits()),
+                &self.backup_bus_pms_constrain_backup(),
             )
             .field(
                 "backup_bus_pms_constrain_bb",
-                &format_args!("{}", self.backup_bus_pms_constrain_bb().bits()),
+                &self.backup_bus_pms_constrain_bb(),
             )
             .field(
                 "backup_bus_pms_constrain_pwm0",
-                &format_args!("{}", self.backup_bus_pms_constrain_pwm0().bits()),
+                &self.backup_bus_pms_constrain_pwm0(),
             )
             .field(
                 "backup_bus_pms_constrain_timergroup",
-                &format_args!("{}", self.backup_bus_pms_constrain_timergroup().bits()),
+                &self.backup_bus_pms_constrain_timergroup(),
             )
             .field(
                 "backup_bus_pms_constrain_timergroup1",
-                &format_args!("{}", self.backup_bus_pms_constrain_timergroup1().bits()),
+                &self.backup_bus_pms_constrain_timergroup1(),
             )
             .field(
                 "backup_bus_pms_constrain_systimer",
-                &format_args!("{}", self.backup_bus_pms_constrain_systimer().bits()),
+                &self.backup_bus_pms_constrain_systimer(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_CONSTRAIN_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - BackUp access bt permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/backup_bus_pms_constrain_3.rs b/esp32s3/src/sensitive/backup_bus_pms_constrain_3.rs
index a156ebdcd0..3f6507134a 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_constrain_3.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_constrain_3.rs
@@ -118,61 +118,55 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_3")
             .field(
                 "backup_bus_pms_constrain_spi_2",
-                &format_args!("{}", self.backup_bus_pms_constrain_spi_2().bits()),
+                &self.backup_bus_pms_constrain_spi_2(),
             )
             .field(
                 "backup_bus_pms_constrain_spi_3",
-                &format_args!("{}", self.backup_bus_pms_constrain_spi_3().bits()),
+                &self.backup_bus_pms_constrain_spi_3(),
             )
             .field(
                 "backup_bus_pms_constrain_apb_ctrl",
-                &format_args!("{}", self.backup_bus_pms_constrain_apb_ctrl().bits()),
+                &self.backup_bus_pms_constrain_apb_ctrl(),
             )
             .field(
                 "backup_bus_pms_constrain_i2c_ext1",
-                &format_args!("{}", self.backup_bus_pms_constrain_i2c_ext1().bits()),
+                &self.backup_bus_pms_constrain_i2c_ext1(),
             )
             .field(
                 "backup_bus_pms_constrain_sdio_host",
-                &format_args!("{}", self.backup_bus_pms_constrain_sdio_host().bits()),
+                &self.backup_bus_pms_constrain_sdio_host(),
             )
             .field(
                 "backup_bus_pms_constrain_can",
-                &format_args!("{}", self.backup_bus_pms_constrain_can().bits()),
+                &self.backup_bus_pms_constrain_can(),
             )
             .field(
                 "backup_bus_pms_constrain_pwm1",
-                &format_args!("{}", self.backup_bus_pms_constrain_pwm1().bits()),
+                &self.backup_bus_pms_constrain_pwm1(),
             )
             .field(
                 "backup_bus_pms_constrain_i2s1",
-                &format_args!("{}", self.backup_bus_pms_constrain_i2s1().bits()),
+                &self.backup_bus_pms_constrain_i2s1(),
             )
             .field(
                 "backup_bus_pms_constrain_uart2",
-                &format_args!("{}", self.backup_bus_pms_constrain_uart2().bits()),
+                &self.backup_bus_pms_constrain_uart2(),
             )
             .field(
                 "backup_bus_pms_constrain_rwbt",
-                &format_args!("{}", self.backup_bus_pms_constrain_rwbt().bits()),
+                &self.backup_bus_pms_constrain_rwbt(),
             )
             .field(
                 "backup_bus_pms_constrain_wifimac",
-                &format_args!("{}", self.backup_bus_pms_constrain_wifimac().bits()),
+                &self.backup_bus_pms_constrain_wifimac(),
             )
             .field(
                 "backup_bus_pms_constrain_pwr",
-                &format_args!("{}", self.backup_bus_pms_constrain_pwr().bits()),
+                &self.backup_bus_pms_constrain_pwr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_CONSTRAIN_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - BackUp access spi_2 permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/backup_bus_pms_constrain_4.rs b/esp32s3/src/sensitive/backup_bus_pms_constrain_4.rs
index 0b43ea8a64..90df03e772 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_constrain_4.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_constrain_4.rs
@@ -156,80 +156,71 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_4")
             .field(
                 "backup_bus_pms_constrain_usb_device",
-                &format_args!("{}", self.backup_bus_pms_constrain_usb_device().bits()),
+                &self.backup_bus_pms_constrain_usb_device(),
             )
             .field(
                 "backup_bus_pms_constrain_usb_wrap",
-                &format_args!("{}", self.backup_bus_pms_constrain_usb_wrap().bits()),
+                &self.backup_bus_pms_constrain_usb_wrap(),
             )
             .field(
                 "backup_bus_pms_constrain_crypto_peri",
-                &format_args!("{}", self.backup_bus_pms_constrain_crypto_peri().bits()),
+                &self.backup_bus_pms_constrain_crypto_peri(),
             )
             .field(
                 "backup_bus_pms_constrain_crypto_dma",
-                &format_args!("{}", self.backup_bus_pms_constrain_crypto_dma().bits()),
+                &self.backup_bus_pms_constrain_crypto_dma(),
             )
             .field(
                 "backup_bus_pms_constrain_apb_adc",
-                &format_args!("{}", self.backup_bus_pms_constrain_apb_adc().bits()),
+                &self.backup_bus_pms_constrain_apb_adc(),
             )
             .field(
                 "backup_bus_pms_constrain_lcd_cam",
-                &format_args!("{}", self.backup_bus_pms_constrain_lcd_cam().bits()),
+                &self.backup_bus_pms_constrain_lcd_cam(),
             )
             .field(
                 "backup_bus_pms_constrain_bt_pwr",
-                &format_args!("{}", self.backup_bus_pms_constrain_bt_pwr().bits()),
+                &self.backup_bus_pms_constrain_bt_pwr(),
             )
             .field(
                 "backup_bus_pms_constrain_usb",
-                &format_args!("{}", self.backup_bus_pms_constrain_usb().bits()),
+                &self.backup_bus_pms_constrain_usb(),
             )
             .field(
                 "backup_bus_pms_constrain_system",
-                &format_args!("{}", self.backup_bus_pms_constrain_system().bits()),
+                &self.backup_bus_pms_constrain_system(),
             )
             .field(
                 "backup_bus_pms_constrain_sensitive",
-                &format_args!("{}", self.backup_bus_pms_constrain_sensitive().bits()),
+                &self.backup_bus_pms_constrain_sensitive(),
             )
             .field(
                 "backup_bus_pms_constrain_interrupt",
-                &format_args!("{}", self.backup_bus_pms_constrain_interrupt().bits()),
+                &self.backup_bus_pms_constrain_interrupt(),
             )
             .field(
                 "backup_bus_pms_constrain_dma_copy",
-                &format_args!("{}", self.backup_bus_pms_constrain_dma_copy().bits()),
+                &self.backup_bus_pms_constrain_dma_copy(),
             )
             .field(
                 "backup_bus_pms_constrain_cache_config",
-                &format_args!("{}", self.backup_bus_pms_constrain_cache_config().bits()),
+                &self.backup_bus_pms_constrain_cache_config(),
             )
             .field(
                 "backup_bus_pms_constrain_ad",
-                &format_args!("{}", self.backup_bus_pms_constrain_ad().bits()),
+                &self.backup_bus_pms_constrain_ad(),
             )
             .field(
                 "backup_bus_pms_constrain_dio",
-                &format_args!("{}", self.backup_bus_pms_constrain_dio().bits()),
+                &self.backup_bus_pms_constrain_dio(),
             )
             .field(
                 "backup_bus_pms_constrain_world_controller",
-                &format_args!(
-                    "{}",
-                    self.backup_bus_pms_constrain_world_controller().bits()
-                ),
+                &self.backup_bus_pms_constrain_world_controller(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_CONSTRAIN_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - BackUp access usb_device permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/backup_bus_pms_constrain_5.rs b/esp32s3/src/sensitive/backup_bus_pms_constrain_5.rs
index 454afd5cf3..f7185863e6 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_constrain_5.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_constrain_5.rs
@@ -22,20 +22,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_5")
             .field(
                 "backup_bus_pms_constrain_rtcfast_spltaddr",
-                &format_args!(
-                    "{}",
-                    self.backup_bus_pms_constrain_rtcfast_spltaddr().bits()
-                ),
+                &self.backup_bus_pms_constrain_rtcfast_spltaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_CONSTRAIN_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - BackUp access rtcfast_spltaddr permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/backup_bus_pms_constrain_6.rs b/esp32s3/src/sensitive/backup_bus_pms_constrain_6.rs
index 56ef6adcee..750775f606 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_constrain_6.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_constrain_6.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_CONSTRAIN_6")
             .field(
                 "backup_bus_pms_constrain_rtcfast_l",
-                &format_args!("{}", self.backup_bus_pms_constrain_rtcfast_l().bits()),
+                &self.backup_bus_pms_constrain_rtcfast_l(),
             )
             .field(
                 "backup_bus_pms_constrain_rtcfast_h",
-                &format_args!("{}", self.backup_bus_pms_constrain_rtcfast_h().bits()),
+                &self.backup_bus_pms_constrain_rtcfast_h(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_CONSTRAIN_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - BackUp access rtcfast_l permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/backup_bus_pms_monitor_0.rs b/esp32s3/src/sensitive/backup_bus_pms_monitor_0.rs
index 4eb75683f8..c85023cf83 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_MONITOR_0")
             .field(
                 "backup_bus_pms_monitor_lock",
-                &format_args!("{}", self.backup_bus_pms_monitor_lock().bit()),
+                &self.backup_bus_pms_monitor_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock BackUp permission report registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/backup_bus_pms_monitor_1.rs b/esp32s3/src/sensitive/backup_bus_pms_monitor_1.rs
index 09202aeb86..b52e644c7d 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_monitor_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_MONITOR_1")
             .field(
                 "backup_bus_pms_monitor_violate_clr",
-                &format_args!("{}", self.backup_bus_pms_monitor_violate_clr().bit()),
+                &self.backup_bus_pms_monitor_violate_clr(),
             )
             .field(
                 "backup_bus_pms_monitor_violate_en",
-                &format_args!("{}", self.backup_bus_pms_monitor_violate_en().bit()),
+                &self.backup_bus_pms_monitor_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to clear interrupt that BackUp initiate illegal access."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/backup_bus_pms_monitor_2.rs b/esp32s3/src/sensitive/backup_bus_pms_monitor_2.rs
index 50ddf5dc7f..6fb5919fb1 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_monitor_2.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_monitor_2.rs
@@ -42,38 +42,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_MONITOR_2")
             .field(
                 "backup_bus_pms_monitor_violate_intr",
-                &format_args!("{}", self.backup_bus_pms_monitor_violate_intr().bit()),
+                &self.backup_bus_pms_monitor_violate_intr(),
             )
             .field(
                 "backup_bus_pms_monitor_violate_status_htrans",
-                &format_args!(
-                    "{}",
-                    self.backup_bus_pms_monitor_violate_status_htrans().bits()
-                ),
+                &self.backup_bus_pms_monitor_violate_status_htrans(),
             )
             .field(
                 "backup_bus_pms_monitor_violate_status_hsize",
-                &format_args!(
-                    "{}",
-                    self.backup_bus_pms_monitor_violate_status_hsize().bits()
-                ),
+                &self.backup_bus_pms_monitor_violate_status_hsize(),
             )
             .field(
                 "backup_bus_pms_monitor_violate_status_hwrite",
-                &format_args!(
-                    "{}",
-                    self.backup_bus_pms_monitor_violate_status_hwrite().bit()
-                ),
+                &self.backup_bus_pms_monitor_violate_status_hwrite(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BackUp permission report register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`backup_bus_pms_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BACKUP_BUS_PMS_MONITOR_2_SPEC;
 impl crate::RegisterSpec for BACKUP_BUS_PMS_MONITOR_2_SPEC {
diff --git a/esp32s3/src/sensitive/backup_bus_pms_monitor_3.rs b/esp32s3/src/sensitive/backup_bus_pms_monitor_3.rs
index 02e114d6ca..1039de7881 100644
--- a/esp32s3/src/sensitive/backup_bus_pms_monitor_3.rs
+++ b/esp32s3/src/sensitive/backup_bus_pms_monitor_3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("BACKUP_BUS_PMS_MONITOR_3")
             .field(
                 "backup_bus_pms_monitor_violate_haddr",
-                &format_args!("{}", self.backup_bus_pms_monitor_violate_haddr().bits()),
+                &self.backup_bus_pms_monitor_violate_haddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BACKUP_BUS_PMS_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "BackUp permission report register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`backup_bus_pms_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BACKUP_BUS_PMS_MONITOR_3_SPEC;
 impl crate::RegisterSpec for BACKUP_BUS_PMS_MONITOR_3_SPEC {
diff --git a/esp32s3/src/sensitive/cache_dataarray_connect_0.rs b/esp32s3/src/sensitive/cache_dataarray_connect_0.rs
index a60b4e7a30..0fa2abf7d8 100644
--- a/esp32s3/src/sensitive/cache_dataarray_connect_0.rs
+++ b/esp32s3/src/sensitive/cache_dataarray_connect_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CACHE_DATAARRAY_CONNECT_0")
             .field(
                 "cache_dataarray_connect_lock",
-                &format_args!("{}", self.cache_dataarray_connect_lock().bit()),
+                &self.cache_dataarray_connect_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_DATAARRAY_CONNECT_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock cache data array registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/cache_dataarray_connect_1.rs b/esp32s3/src/sensitive/cache_dataarray_connect_1.rs
index 1ce424e48e..19dfb5b8f3 100644
--- a/esp32s3/src/sensitive/cache_dataarray_connect_1.rs
+++ b/esp32s3/src/sensitive/cache_dataarray_connect_1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CACHE_DATAARRAY_CONNECT_1")
             .field(
                 "cache_dataarray_connect_flatten",
-                &format_args!("{}", self.cache_dataarray_connect_flatten().bits()),
+                &self.cache_dataarray_connect_flatten(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_DATAARRAY_CONNECT_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Cache data array connection configuration."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/cache_mmu_access_0.rs b/esp32s3/src/sensitive/cache_mmu_access_0.rs
index f1dc1ea0c3..8e74234d20 100644
--- a/esp32s3/src/sensitive/cache_mmu_access_0.rs
+++ b/esp32s3/src/sensitive/cache_mmu_access_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_ACCESS_0")
-            .field(
-                "cache_mmu_access_lock",
-                &format_args!("{}", self.cache_mmu_access_lock().bit()),
-            )
+            .field("cache_mmu_access_lock", &self.cache_mmu_access_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_ACCESS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock cache MMU registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/cache_mmu_access_1.rs b/esp32s3/src/sensitive/cache_mmu_access_1.rs
index 0468176038..62572d2e20 100644
--- a/esp32s3/src/sensitive/cache_mmu_access_1.rs
+++ b/esp32s3/src/sensitive/cache_mmu_access_1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_MMU_ACCESS_1")
-            .field(
-                "pro_mmu_rd_acs",
-                &format_args!("{}", self.pro_mmu_rd_acs().bit()),
-            )
-            .field(
-                "pro_mmu_wr_acs",
-                &format_args!("{}", self.pro_mmu_wr_acs().bit()),
-            )
+            .field("pro_mmu_rd_acs", &self.pro_mmu_rd_acs())
+            .field("pro_mmu_wr_acs", &self.pro_mmu_wr_acs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_MMU_ACCESS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable read access MMU memory."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/cache_tag_access_0.rs b/esp32s3/src/sensitive/cache_tag_access_0.rs
index 9722a5145d..9235a92498 100644
--- a/esp32s3/src/sensitive/cache_tag_access_0.rs
+++ b/esp32s3/src/sensitive/cache_tag_access_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_TAG_ACCESS_0")
-            .field(
-                "cache_tag_access_lock",
-                &format_args!("{}", self.cache_tag_access_lock().bit()),
-            )
+            .field("cache_tag_access_lock", &self.cache_tag_access_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_TAG_ACCESS_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock cache tag Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/cache_tag_access_1.rs b/esp32s3/src/sensitive/cache_tag_access_1.rs
index 5e47a44f32..26ff7d887a 100644
--- a/esp32s3/src/sensitive/cache_tag_access_1.rs
+++ b/esp32s3/src/sensitive/cache_tag_access_1.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_TAG_ACCESS_1")
-            .field(
-                "pro_i_tag_rd_acs",
-                &format_args!("{}", self.pro_i_tag_rd_acs().bit()),
-            )
-            .field(
-                "pro_i_tag_wr_acs",
-                &format_args!("{}", self.pro_i_tag_wr_acs().bit()),
-            )
-            .field(
-                "pro_d_tag_rd_acs",
-                &format_args!("{}", self.pro_d_tag_rd_acs().bit()),
-            )
-            .field(
-                "pro_d_tag_wr_acs",
-                &format_args!("{}", self.pro_d_tag_wr_acs().bit()),
-            )
+            .field("pro_i_tag_rd_acs", &self.pro_i_tag_rd_acs())
+            .field("pro_i_tag_wr_acs", &self.pro_i_tag_wr_acs())
+            .field("pro_d_tag_rd_acs", &self.pro_d_tag_rd_acs())
+            .field("pro_d_tag_wr_acs", &self.pro_d_tag_wr_acs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_TAG_ACCESS_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable Icache read access tag memory."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/clock_gate.rs b/esp32s3/src/sensitive/clock_gate.rs
index a14a63424e..8f1337a97e 100644
--- a/esp32s3/src/sensitive/clock_gate.rs
+++ b/esp32s3/src/sensitive/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("reg_clk_en", &format_args!("{}", self.reg_clk_en().bit()))
+            .field("reg_clk_en", &self.reg_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable clock gate function."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_dram0_pms_monitor_0.rs b/esp32s3/src/sensitive/core_0_dram0_pms_monitor_0.rs
index e75c7897fd..14f50dcd7d 100644
--- a/esp32s3/src/sensitive/core_0_dram0_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/core_0_dram0_pms_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_PMS_MONITOR_0")
             .field(
                 "core_0_dram0_pms_monitor_lock",
-                &format_args!("{}", self.core_0_dram0_pms_monitor_lock().bit()),
+                &self.core_0_dram0_pms_monitor_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_PMS_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core0 dram0 permission monitor configuration register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_dram0_pms_monitor_1.rs b/esp32s3/src/sensitive/core_0_dram0_pms_monitor_1.rs
index f2cabf2a5e..5d4263b23b 100644
--- a/esp32s3/src/sensitive/core_0_dram0_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/core_0_dram0_pms_monitor_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_PMS_MONITOR_1")
             .field(
                 "core_0_dram0_pms_monitor_violate_clr",
-                &format_args!("{}", self.core_0_dram0_pms_monitor_violate_clr().bit()),
+                &self.core_0_dram0_pms_monitor_violate_clr(),
             )
             .field(
                 "core_0_dram0_pms_monitor_violate_en",
-                &format_args!("{}", self.core_0_dram0_pms_monitor_violate_en().bit()),
+                &self.core_0_dram0_pms_monitor_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_PMS_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to clear core0 dram0 permission monior interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_dram0_pms_monitor_2.rs b/esp32s3/src/sensitive/core_0_dram0_pms_monitor_2.rs
index 79e529072c..b2eb0b87aa 100644
--- a/esp32s3/src/sensitive/core_0_dram0_pms_monitor_2.rs
+++ b/esp32s3/src/sensitive/core_0_dram0_pms_monitor_2.rs
@@ -42,38 +42,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_PMS_MONITOR_2")
             .field(
                 "core_0_dram0_pms_monitor_violate_intr",
-                &format_args!("{}", self.core_0_dram0_pms_monitor_violate_intr().bit()),
+                &self.core_0_dram0_pms_monitor_violate_intr(),
             )
             .field(
                 "core_0_dram0_pms_monitor_violate_status_lock",
-                &format_args!(
-                    "{}",
-                    self.core_0_dram0_pms_monitor_violate_status_lock().bit()
-                ),
+                &self.core_0_dram0_pms_monitor_violate_status_lock(),
             )
             .field(
                 "core_0_dram0_pms_monitor_violate_status_world",
-                &format_args!(
-                    "{}",
-                    self.core_0_dram0_pms_monitor_violate_status_world().bits()
-                ),
+                &self.core_0_dram0_pms_monitor_violate_status_world(),
             )
             .field(
                 "core_0_dram0_pms_monitor_violate_status_addr",
-                &format_args!(
-                    "{}",
-                    self.core_0_dram0_pms_monitor_violate_status_addr().bits()
-                ),
+                &self.core_0_dram0_pms_monitor_violate_status_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_PMS_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 dram0 permission monitor configuration register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_pms_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_PMS_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_PMS_MONITOR_2_SPEC {
diff --git a/esp32s3/src/sensitive/core_0_dram0_pms_monitor_3.rs b/esp32s3/src/sensitive/core_0_dram0_pms_monitor_3.rs
index 6279c411b1..4c58501916 100644
--- a/esp32s3/src/sensitive/core_0_dram0_pms_monitor_3.rs
+++ b/esp32s3/src/sensitive/core_0_dram0_pms_monitor_3.rs
@@ -26,27 +26,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_DRAM0_PMS_MONITOR_3")
             .field(
                 "core_0_dram0_pms_monitor_violate_status_wr",
-                &format_args!(
-                    "{}",
-                    self.core_0_dram0_pms_monitor_violate_status_wr().bit()
-                ),
+                &self.core_0_dram0_pms_monitor_violate_status_wr(),
             )
             .field(
                 "core_0_dram0_pms_monitor_violate_status_byteen",
-                &format_args!(
-                    "{}",
-                    self.core_0_dram0_pms_monitor_violate_status_byteen().bits()
-                ),
+                &self.core_0_dram0_pms_monitor_violate_status_byteen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_DRAM0_PMS_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 dram0 permission monitor configuration register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_dram0_pms_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_DRAM0_PMS_MONITOR_3_SPEC;
 impl crate::RegisterSpec for CORE_0_DRAM0_PMS_MONITOR_3_SPEC {
diff --git a/esp32s3/src/sensitive/core_0_iram0_pms_monitor_0.rs b/esp32s3/src/sensitive/core_0_iram0_pms_monitor_0.rs
index 63711a09ea..4af5194e41 100644
--- a/esp32s3/src/sensitive/core_0_iram0_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/core_0_iram0_pms_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_PMS_MONITOR_0")
             .field(
                 "core_0_iram0_pms_monitor_lock",
-                &format_args!("{}", self.core_0_iram0_pms_monitor_lock().bit()),
+                &self.core_0_iram0_pms_monitor_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_PMS_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core0 iram0 permission monitor register"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_iram0_pms_monitor_1.rs b/esp32s3/src/sensitive/core_0_iram0_pms_monitor_1.rs
index 1df540282d..1098f703ae 100644
--- a/esp32s3/src/sensitive/core_0_iram0_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/core_0_iram0_pms_monitor_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_PMS_MONITOR_1")
             .field(
                 "core_0_iram0_pms_monitor_violate_clr",
-                &format_args!("{}", self.core_0_iram0_pms_monitor_violate_clr().bit()),
+                &self.core_0_iram0_pms_monitor_violate_clr(),
             )
             .field(
                 "core_0_iram0_pms_monitor_violate_en",
-                &format_args!("{}", self.core_0_iram0_pms_monitor_violate_en().bit()),
+                &self.core_0_iram0_pms_monitor_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_PMS_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to clear core0 iram0 permission violated interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_iram0_pms_monitor_2.rs b/esp32s3/src/sensitive/core_0_iram0_pms_monitor_2.rs
index 4800023142..33d5aafe81 100644
--- a/esp32s3/src/sensitive/core_0_iram0_pms_monitor_2.rs
+++ b/esp32s3/src/sensitive/core_0_iram0_pms_monitor_2.rs
@@ -51,46 +51,27 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_IRAM0_PMS_MONITOR_2")
             .field(
                 "core_0_iram0_pms_monitor_violate_intr",
-                &format_args!("{}", self.core_0_iram0_pms_monitor_violate_intr().bit()),
+                &self.core_0_iram0_pms_monitor_violate_intr(),
             )
             .field(
                 "core_0_iram0_pms_monitor_violate_status_wr",
-                &format_args!(
-                    "{}",
-                    self.core_0_iram0_pms_monitor_violate_status_wr().bit()
-                ),
+                &self.core_0_iram0_pms_monitor_violate_status_wr(),
             )
             .field(
                 "core_0_iram0_pms_monitor_violate_status_loadstore",
-                &format_args!(
-                    "{}",
-                    self.core_0_iram0_pms_monitor_violate_status_loadstore()
-                        .bit()
-                ),
+                &self.core_0_iram0_pms_monitor_violate_status_loadstore(),
             )
             .field(
                 "core_0_iram0_pms_monitor_violate_status_world",
-                &format_args!(
-                    "{}",
-                    self.core_0_iram0_pms_monitor_violate_status_world().bits()
-                ),
+                &self.core_0_iram0_pms_monitor_violate_status_world(),
             )
             .field(
                 "core_0_iram0_pms_monitor_violate_status_addr",
-                &format_args!(
-                    "{}",
-                    self.core_0_iram0_pms_monitor_violate_status_addr().bits()
-                ),
+                &self.core_0_iram0_pms_monitor_violate_status_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_IRAM0_PMS_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core0 iram0 permission monitor configuration register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_iram0_pms_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_IRAM0_PMS_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_0_IRAM0_PMS_MONITOR_2_SPEC {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_0.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_0.rs
index d00332f046..e72a3824c7 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_0")
             .field(
                 "core_0_pif_pms_constrain_lock",
-                &format_args!("{}", self.core_0_pif_pms_constrain_lock().bit()),
+                &self.core_0_pif_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core0 access peripherals permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_1.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_1.rs
index db047fced7..f73f1d9abe 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_1.rs
@@ -135,65 +135,59 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_1")
             .field(
                 "core_0_pif_pms_constrain_world_0_uart",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_uart().bits()),
+                &self.core_0_pif_pms_constrain_world_0_uart(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_g0spi_1",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_g0spi_1().bits()),
+                &self.core_0_pif_pms_constrain_world_0_g0spi_1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_g0spi_0",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_g0spi_0().bits()),
+                &self.core_0_pif_pms_constrain_world_0_g0spi_0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_gpio",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_gpio().bits()),
+                &self.core_0_pif_pms_constrain_world_0_gpio(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_fe2",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_fe2().bits()),
+                &self.core_0_pif_pms_constrain_world_0_fe2(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_fe",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_fe().bits()),
+                &self.core_0_pif_pms_constrain_world_0_fe(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_rtc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_rtc().bits()),
+                &self.core_0_pif_pms_constrain_world_0_rtc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_io_mux",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_io_mux().bits()),
+                &self.core_0_pif_pms_constrain_world_0_io_mux(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_hinf",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_hinf().bits()),
+                &self.core_0_pif_pms_constrain_world_0_hinf(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_misc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_misc().bits()),
+                &self.core_0_pif_pms_constrain_world_0_misc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_i2c",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_i2c().bits()),
+                &self.core_0_pif_pms_constrain_world_0_i2c(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_i2s0",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_i2s0().bits()),
+                &self.core_0_pif_pms_constrain_world_0_i2s0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_uart1",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_uart1().bits()),
+                &self.core_0_pif_pms_constrain_world_0_uart1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core0 access uart permission in world0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_10.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_10.rs
index 96c0f60572..c1a545a3c6 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_10.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_10.rs
@@ -54,41 +54,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_10")
             .field(
                 "core_0_pif_pms_constrain_rtcfast_world_0_l",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcfast_world_0_l().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcfast_world_0_l(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcfast_world_0_h",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcfast_world_0_h().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcfast_world_0_h(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcfast_world_1_l",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcfast_world_1_l().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcfast_world_1_l(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcfast_world_1_h",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcfast_world_1_h().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcfast_world_1_h(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - RTCFast memory low region permission in world 0 for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_11.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_11.rs
index 96db3ae47e..bdfb6d1748 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_11.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_11.rs
@@ -36,29 +36,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_11")
             .field(
                 "core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_0",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_0()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_0(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_1",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_1()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - RTCSlow_0 memory split address in world 0 for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_12.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_12.rs
index 11927ca011..24fd3900e4 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_12.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_12.rs
@@ -54,41 +54,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_12")
             .field(
                 "core_0_pif_pms_constrain_rtcslow_0_world_0_l",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcslow_0_world_0_l().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcslow_0_world_0_l(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcslow_0_world_0_h",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcslow_0_world_0_h().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcslow_0_world_0_h(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcslow_0_world_1_l",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcslow_0_world_1_l().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcslow_0_world_1_l(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcslow_0_world_1_h",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcslow_0_world_1_h().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcslow_0_world_1_h(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - RTCSlow_0 memory low region permission in world 0 for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_13.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_13.rs
index e572b25e6f..0ce3ed66a3 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_13.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_13.rs
@@ -36,29 +36,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_13")
             .field(
                 "core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_0",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_0()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_0(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_1",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_1()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - RTCSlow_1 memory split address in world 0 for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_14.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_14.rs
index e38ddb0ebe..d3d8149884 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_14.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_14.rs
@@ -54,41 +54,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_14")
             .field(
                 "core_0_pif_pms_constrain_rtcslow_1_world_0_l",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcslow_1_world_0_l().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcslow_1_world_0_l(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcslow_1_world_0_h",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcslow_1_world_0_h().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcslow_1_world_0_h(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcslow_1_world_1_l",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcslow_1_world_1_l().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcslow_1_world_1_l(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcslow_1_world_1_h",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcslow_1_world_1_h().bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcslow_1_world_1_h(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - RTCSlow_1 memory low region permission in world 0 for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_2.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_2.rs
index 432e6d447f..4ba76f776e 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_2.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_2.rs
@@ -150,81 +150,63 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_2")
             .field(
                 "core_0_pif_pms_constrain_world_0_bt",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_bt().bits()),
+                &self.core_0_pif_pms_constrain_world_0_bt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_i2c_ext0",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_i2c_ext0().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_i2c_ext0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_uhci0",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_uhci0().bits()),
+                &self.core_0_pif_pms_constrain_world_0_uhci0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_slchost",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_slchost().bits()),
+                &self.core_0_pif_pms_constrain_world_0_slchost(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_rmt",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_rmt().bits()),
+                &self.core_0_pif_pms_constrain_world_0_rmt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_pcnt",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_pcnt().bits()),
+                &self.core_0_pif_pms_constrain_world_0_pcnt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_slc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_slc().bits()),
+                &self.core_0_pif_pms_constrain_world_0_slc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_ledc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_ledc().bits()),
+                &self.core_0_pif_pms_constrain_world_0_ledc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_backup",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_backup().bits()),
+                &self.core_0_pif_pms_constrain_world_0_backup(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_bb",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_bb().bits()),
+                &self.core_0_pif_pms_constrain_world_0_bb(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_pwm0",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_pwm0().bits()),
+                &self.core_0_pif_pms_constrain_world_0_pwm0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_timergroup",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_timergroup().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_timergroup(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_timergroup1",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_timergroup1().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_timergroup1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_systimer",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_systimer().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_systimer(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core0 access bt permission in world0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_3.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_3.rs
index fe73ad1847..f58319e985 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_3.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_3.rs
@@ -132,70 +132,55 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_3")
             .field(
                 "core_0_pif_pms_constrain_world_0_spi_2",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_spi_2().bits()),
+                &self.core_0_pif_pms_constrain_world_0_spi_2(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_spi_3",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_spi_3().bits()),
+                &self.core_0_pif_pms_constrain_world_0_spi_3(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_apb_ctrl",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_apb_ctrl().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_apb_ctrl(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_i2c_ext1",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_i2c_ext1().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_i2c_ext1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_sdio_host",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_sdio_host().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_sdio_host(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_can",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_can().bits()),
+                &self.core_0_pif_pms_constrain_world_0_can(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_pwm1",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_pwm1().bits()),
+                &self.core_0_pif_pms_constrain_world_0_pwm1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_i2s1",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_i2s1().bits()),
+                &self.core_0_pif_pms_constrain_world_0_i2s1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_uart2",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_uart2().bits()),
+                &self.core_0_pif_pms_constrain_world_0_uart2(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_rwbt",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_rwbt().bits()),
+                &self.core_0_pif_pms_constrain_world_0_rwbt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_wifimac",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_wifimac().bits()),
+                &self.core_0_pif_pms_constrain_world_0_wifimac(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_pwr",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_pwr().bits()),
+                &self.core_0_pif_pms_constrain_world_0_pwr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core0 access spi_2 permission in world0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_4.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_4.rs
index c92204fb42..3cf9b78581 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_4.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_4.rs
@@ -181,105 +181,71 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_4")
             .field(
                 "core_0_pif_pms_constrain_world_0_usb_device",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_usb_device().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_usb_device(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_usb_wrap",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_usb_wrap().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_usb_wrap(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_crypto_peri",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_crypto_peri().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_crypto_peri(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_crypto_dma",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_crypto_dma().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_crypto_dma(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_apb_adc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_apb_adc().bits()),
+                &self.core_0_pif_pms_constrain_world_0_apb_adc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_lcd_cam",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_lcd_cam().bits()),
+                &self.core_0_pif_pms_constrain_world_0_lcd_cam(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_bt_pwr",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_bt_pwr().bits()),
+                &self.core_0_pif_pms_constrain_world_0_bt_pwr(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_usb",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_usb().bits()),
+                &self.core_0_pif_pms_constrain_world_0_usb(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_system",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_system().bits()),
+                &self.core_0_pif_pms_constrain_world_0_system(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_sensitive",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_sensitive().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_sensitive(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_interrupt",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_interrupt().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_interrupt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_dma_copy",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_dma_copy().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_dma_copy(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_cache_config",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_cache_config().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_cache_config(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_ad",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_ad().bits()),
+                &self.core_0_pif_pms_constrain_world_0_ad(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_dio",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_0_dio().bits()),
+                &self.core_0_pif_pms_constrain_world_0_dio(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_0_world_controller",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_0_world_controller()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_0_world_controller(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core0 access usb_device permission in world0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_5.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_5.rs
index df89abdabf..f48f43c27d 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_5.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_5.rs
@@ -135,65 +135,59 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_5")
             .field(
                 "core_0_pif_pms_constrain_world_1_uart",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_uart().bits()),
+                &self.core_0_pif_pms_constrain_world_1_uart(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_g0spi_1",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_g0spi_1().bits()),
+                &self.core_0_pif_pms_constrain_world_1_g0spi_1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_g0spi_0",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_g0spi_0().bits()),
+                &self.core_0_pif_pms_constrain_world_1_g0spi_0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_gpio",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_gpio().bits()),
+                &self.core_0_pif_pms_constrain_world_1_gpio(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_fe2",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_fe2().bits()),
+                &self.core_0_pif_pms_constrain_world_1_fe2(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_fe",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_fe().bits()),
+                &self.core_0_pif_pms_constrain_world_1_fe(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_rtc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_rtc().bits()),
+                &self.core_0_pif_pms_constrain_world_1_rtc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_io_mux",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_io_mux().bits()),
+                &self.core_0_pif_pms_constrain_world_1_io_mux(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_hinf",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_hinf().bits()),
+                &self.core_0_pif_pms_constrain_world_1_hinf(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_misc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_misc().bits()),
+                &self.core_0_pif_pms_constrain_world_1_misc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_i2c",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_i2c().bits()),
+                &self.core_0_pif_pms_constrain_world_1_i2c(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_i2s0",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_i2s0().bits()),
+                &self.core_0_pif_pms_constrain_world_1_i2s0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_uart1",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_uart1().bits()),
+                &self.core_0_pif_pms_constrain_world_1_uart1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core0 access uart permission in world1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_6.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_6.rs
index 995fafff48..36de0cc493 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_6.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_6.rs
@@ -150,81 +150,63 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_6")
             .field(
                 "core_0_pif_pms_constrain_world_1_bt",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_bt().bits()),
+                &self.core_0_pif_pms_constrain_world_1_bt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_i2c_ext0",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_i2c_ext0().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_i2c_ext0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_uhci0",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_uhci0().bits()),
+                &self.core_0_pif_pms_constrain_world_1_uhci0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_slchost",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_slchost().bits()),
+                &self.core_0_pif_pms_constrain_world_1_slchost(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_rmt",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_rmt().bits()),
+                &self.core_0_pif_pms_constrain_world_1_rmt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_pcnt",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_pcnt().bits()),
+                &self.core_0_pif_pms_constrain_world_1_pcnt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_slc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_slc().bits()),
+                &self.core_0_pif_pms_constrain_world_1_slc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_ledc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_ledc().bits()),
+                &self.core_0_pif_pms_constrain_world_1_ledc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_backup",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_backup().bits()),
+                &self.core_0_pif_pms_constrain_world_1_backup(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_bb",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_bb().bits()),
+                &self.core_0_pif_pms_constrain_world_1_bb(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_pwm0",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_pwm0().bits()),
+                &self.core_0_pif_pms_constrain_world_1_pwm0(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_timergroup",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_timergroup().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_timergroup(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_timergroup1",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_timergroup1().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_timergroup1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_systimer",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_systimer().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_systimer(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core0 access bt permission in world1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_7.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_7.rs
index a821ffba74..43b7f6c8ae 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_7.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_7.rs
@@ -132,70 +132,55 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_7")
             .field(
                 "core_0_pif_pms_constrain_world_1_spi_2",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_spi_2().bits()),
+                &self.core_0_pif_pms_constrain_world_1_spi_2(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_spi_3",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_spi_3().bits()),
+                &self.core_0_pif_pms_constrain_world_1_spi_3(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_apb_ctrl",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_apb_ctrl().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_apb_ctrl(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_i2c_ext1",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_i2c_ext1().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_i2c_ext1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_sdio_host",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_sdio_host().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_sdio_host(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_can",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_can().bits()),
+                &self.core_0_pif_pms_constrain_world_1_can(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_pwm1",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_pwm1().bits()),
+                &self.core_0_pif_pms_constrain_world_1_pwm1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_i2s1",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_i2s1().bits()),
+                &self.core_0_pif_pms_constrain_world_1_i2s1(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_uart2",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_uart2().bits()),
+                &self.core_0_pif_pms_constrain_world_1_uart2(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_rwbt",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_rwbt().bits()),
+                &self.core_0_pif_pms_constrain_world_1_rwbt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_wifimac",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_wifimac().bits()),
+                &self.core_0_pif_pms_constrain_world_1_wifimac(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_pwr",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_pwr().bits()),
+                &self.core_0_pif_pms_constrain_world_1_pwr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core0 access spi_2 permission in world1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_8.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_8.rs
index cf952208cd..c070c1ee72 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_8.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_8.rs
@@ -181,105 +181,71 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_8")
             .field(
                 "core_0_pif_pms_constrain_world_1_usb_device",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_usb_device().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_usb_device(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_usb_wrap",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_usb_wrap().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_usb_wrap(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_crypto_peri",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_crypto_peri().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_crypto_peri(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_crypto_dma",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_crypto_dma().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_crypto_dma(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_apb_adc",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_apb_adc().bits()),
+                &self.core_0_pif_pms_constrain_world_1_apb_adc(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_lcd_cam",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_lcd_cam().bits()),
+                &self.core_0_pif_pms_constrain_world_1_lcd_cam(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_bt_pwr",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_bt_pwr().bits()),
+                &self.core_0_pif_pms_constrain_world_1_bt_pwr(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_usb",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_usb().bits()),
+                &self.core_0_pif_pms_constrain_world_1_usb(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_system",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_system().bits()),
+                &self.core_0_pif_pms_constrain_world_1_system(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_sensitive",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_sensitive().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_sensitive(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_interrupt",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_interrupt().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_interrupt(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_dma_copy",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_dma_copy().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_dma_copy(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_cache_config",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_cache_config().bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_cache_config(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_ad",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_ad().bits()),
+                &self.core_0_pif_pms_constrain_world_1_ad(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_dio",
-                &format_args!("{}", self.core_0_pif_pms_constrain_world_1_dio().bits()),
+                &self.core_0_pif_pms_constrain_world_1_dio(),
             )
             .field(
                 "core_0_pif_pms_constrain_world_1_world_controller",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_world_1_world_controller()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_constrain_world_1_world_controller(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core0 access usb_device permission in world1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_constrain_9.rs b/esp32s3/src/sensitive/core_0_pif_pms_constrain_9.rs
index a92dfec1b2..2de47b11c3 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_constrain_9.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_constrain_9.rs
@@ -36,29 +36,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_9")
             .field(
                 "core_0_pif_pms_constrain_rtcfast_spltaddr_world_0",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcfast_spltaddr_world_0()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcfast_spltaddr_world_0(),
             )
             .field(
                 "core_0_pif_pms_constrain_rtcfast_spltaddr_world_1",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_constrain_rtcfast_spltaddr_world_1()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_constrain_rtcfast_spltaddr_world_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_CONSTRAIN_9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - RTCFast memory split address in world 0 for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_monitor_0.rs b/esp32s3/src/sensitive/core_0_pif_pms_monitor_0.rs
index b7e2493b76..93a123328e 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_0")
             .field(
                 "core_0_pif_pms_monitor_lock",
-                &format_args!("{}", self.core_0_pif_pms_monitor_lock().bit()),
+                &self.core_0_pif_pms_monitor_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core0 permission report registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_monitor_1.rs b/esp32s3/src/sensitive/core_0_pif_pms_monitor_1.rs
index f8a560792e..e905078ebc 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_monitor_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_1")
             .field(
                 "core_0_pif_pms_monitor_violate_clr",
-                &format_args!("{}", self.core_0_pif_pms_monitor_violate_clr().bit()),
+                &self.core_0_pif_pms_monitor_violate_clr(),
             )
             .field(
                 "core_0_pif_pms_monitor_violate_en",
-                &format_args!("{}", self.core_0_pif_pms_monitor_violate_en().bit()),
+                &self.core_0_pif_pms_monitor_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to clear interrupt that core0 initiate illegal PIF bus access."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_monitor_2.rs b/esp32s3/src/sensitive/core_0_pif_pms_monitor_2.rs
index bea61cf99e..61edf10835 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_monitor_2.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_monitor_2.rs
@@ -51,45 +51,27 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_2")
             .field(
                 "core_0_pif_pms_monitor_violate_intr",
-                &format_args!("{}", self.core_0_pif_pms_monitor_violate_intr().bit()),
+                &self.core_0_pif_pms_monitor_violate_intr(),
             )
             .field(
                 "core_0_pif_pms_monitor_violate_status_hport_0",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_violate_status_hport_0().bit()
-                ),
+                &self.core_0_pif_pms_monitor_violate_status_hport_0(),
             )
             .field(
                 "core_0_pif_pms_monitor_violate_status_hsize",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_violate_status_hsize().bits()
-                ),
+                &self.core_0_pif_pms_monitor_violate_status_hsize(),
             )
             .field(
                 "core_0_pif_pms_monitor_violate_status_hwrite",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_violate_status_hwrite().bit()
-                ),
+                &self.core_0_pif_pms_monitor_violate_status_hwrite(),
             )
             .field(
                 "core_0_pif_pms_monitor_violate_status_hworld",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_violate_status_hworld().bits()
-                ),
+                &self.core_0_pif_pms_monitor_violate_status_hworld(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core0 permission report register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_pif_pms_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_PIF_PMS_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_0_PIF_PMS_MONITOR_2_SPEC {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_monitor_3.rs b/esp32s3/src/sensitive/core_0_pif_pms_monitor_3.rs
index 7038c48aad..8eff638565 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_monitor_3.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_monitor_3.rs
@@ -17,20 +17,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_3")
             .field(
                 "core_0_pif_pms_monitor_violate_status_haddr",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_violate_status_haddr().bits()
-                ),
+                &self.core_0_pif_pms_monitor_violate_status_haddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core0 permission report register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_pif_pms_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_PIF_PMS_MONITOR_3_SPEC;
 impl crate::RegisterSpec for CORE_0_PIF_PMS_MONITOR_3_SPEC {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_monitor_4.rs b/esp32s3/src/sensitive/core_0_pif_pms_monitor_4.rs
index 3c8bd5c9db..2ee6176759 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_monitor_4.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_monitor_4.rs
@@ -32,24 +32,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_4")
             .field(
                 "core_0_pif_pms_monitor_nonword_violate_clr",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_nonword_violate_clr().bit()
-                ),
+                &self.core_0_pif_pms_monitor_nonword_violate_clr(),
             )
             .field(
                 "core_0_pif_pms_monitor_nonword_violate_en",
-                &format_args!("{}", self.core_0_pif_pms_monitor_nonword_violate_en().bit()),
+                &self.core_0_pif_pms_monitor_nonword_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to clear interrupt that core0 initiate unsupported access type."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_monitor_5.rs b/esp32s3/src/sensitive/core_0_pif_pms_monitor_5.rs
index 94cf71431f..22808f7182 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_monitor_5.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_monitor_5.rs
@@ -35,36 +35,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_5")
             .field(
                 "core_0_pif_pms_monitor_nonword_violate_intr",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_nonword_violate_intr().bit()
-                ),
+                &self.core_0_pif_pms_monitor_nonword_violate_intr(),
             )
             .field(
                 "core_0_pif_pms_monitor_nonword_violate_status_hsize",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_nonword_violate_status_hsize()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_monitor_nonword_violate_status_hsize(),
             )
             .field(
                 "core_0_pif_pms_monitor_nonword_violate_status_hworld",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_nonword_violate_status_hworld()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_monitor_nonword_violate_status_hworld(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core0 permission report register 5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_pif_pms_monitor_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_PIF_PMS_MONITOR_5_SPEC;
 impl crate::RegisterSpec for CORE_0_PIF_PMS_MONITOR_5_SPEC {
diff --git a/esp32s3/src/sensitive/core_0_pif_pms_monitor_6.rs b/esp32s3/src/sensitive/core_0_pif_pms_monitor_6.rs
index d587501091..4908322a07 100644
--- a/esp32s3/src/sensitive/core_0_pif_pms_monitor_6.rs
+++ b/esp32s3/src/sensitive/core_0_pif_pms_monitor_6.rs
@@ -17,21 +17,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_PIF_PMS_MONITOR_6")
             .field(
                 "core_0_pif_pms_monitor_nonword_violate_status_haddr",
-                &format_args!(
-                    "{}",
-                    self.core_0_pif_pms_monitor_nonword_violate_status_haddr()
-                        .bits()
-                ),
+                &self.core_0_pif_pms_monitor_nonword_violate_status_haddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_PIF_PMS_MONITOR_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core0 permission report register 6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_pif_pms_monitor_6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_PIF_PMS_MONITOR_6_SPEC;
 impl crate::RegisterSpec for CORE_0_PIF_PMS_MONITOR_6_SPEC {
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_0.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_0.rs
index addff5157b..a5d5963107 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_0")
             .field(
                 "core_0_region_pms_constrain_lock",
-                &format_args!("{}", self.core_0_region_pms_constrain_lock().bit()),
+                &self.core_0_region_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_REGION_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core0 region permission registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_1.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_1.rs
index 5257abbafb..8e8286e359 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_1.rs
@@ -131,90 +131,51 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_1")
             .field(
                 "core_0_region_pms_constrain_world_0_area_0",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_0_area_0().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_0_area_0(),
             )
             .field(
                 "core_0_region_pms_constrain_world_0_area_1",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_0_area_1().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_0_area_1(),
             )
             .field(
                 "core_0_region_pms_constrain_world_0_area_2",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_0_area_2().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_0_area_2(),
             )
             .field(
                 "core_0_region_pms_constrain_world_0_area_3",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_0_area_3().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_0_area_3(),
             )
             .field(
                 "core_0_region_pms_constrain_world_0_area_4",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_0_area_4().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_0_area_4(),
             )
             .field(
                 "core_0_region_pms_constrain_world_0_area_5",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_0_area_5().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_0_area_5(),
             )
             .field(
                 "core_0_region_pms_constrain_world_0_area_6",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_0_area_6().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_0_area_6(),
             )
             .field(
                 "core_0_region_pms_constrain_world_0_area_7",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_0_area_7().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_0_area_7(),
             )
             .field(
                 "core_0_region_pms_constrain_world_0_area_8",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_0_area_8().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_0_area_8(),
             )
             .field(
                 "core_0_region_pms_constrain_world_0_area_9",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_0_area_9().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_0_area_9(),
             )
             .field(
                 "core_0_region_pms_constrain_world_0_area_10",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_0_area_10().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_0_area_10(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_REGION_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Region 0 permission in world 0 for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_10.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_10.rs
index c00a589e36..2c101328a1 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_10.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_10.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_10")
             .field(
                 "core_0_region_pms_constrain_addr_7",
-                &format_args!("{}", self.core_0_region_pms_constrain_addr_7().bits()),
+                &self.core_0_region_pms_constrain_addr_7(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_REGION_PMS_CONSTRAIN_10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 6 end address and Region 7 start address for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_11.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_11.rs
index dca09fcf7b..f73ea0692d 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_11.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_11.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_11")
             .field(
                 "core_0_region_pms_constrain_addr_8",
-                &format_args!("{}", self.core_0_region_pms_constrain_addr_8().bits()),
+                &self.core_0_region_pms_constrain_addr_8(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_REGION_PMS_CONSTRAIN_11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 7 end address and Region 8 start address for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_12.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_12.rs
index 7a833307a9..72156866fc 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_12.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_12.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_12")
             .field(
                 "core_0_region_pms_constrain_addr_9",
-                &format_args!("{}", self.core_0_region_pms_constrain_addr_9().bits()),
+                &self.core_0_region_pms_constrain_addr_9(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_REGION_PMS_CONSTRAIN_12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 8 end address and Region 9 start address for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_13.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_13.rs
index 17f1d3ea02..2c4b940e29 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_13.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_13.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_13")
             .field(
                 "core_0_region_pms_constrain_addr_10",
-                &format_args!("{}", self.core_0_region_pms_constrain_addr_10().bits()),
+                &self.core_0_region_pms_constrain_addr_10(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_REGION_PMS_CONSTRAIN_13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 9 end address and Region 10 start address for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_14.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_14.rs
index f464d2fb14..f290b318d5 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_14.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_14.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_14")
             .field(
                 "core_0_region_pms_constrain_addr_11",
-                &format_args!("{}", self.core_0_region_pms_constrain_addr_11().bits()),
+                &self.core_0_region_pms_constrain_addr_11(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_REGION_PMS_CONSTRAIN_14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 10 end address for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_2.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_2.rs
index 910d32a921..736b04539b 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_2.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_2.rs
@@ -131,90 +131,51 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_2")
             .field(
                 "core_0_region_pms_constrain_world_1_area_0",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_1_area_0().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_1_area_0(),
             )
             .field(
                 "core_0_region_pms_constrain_world_1_area_1",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_1_area_1().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_1_area_1(),
             )
             .field(
                 "core_0_region_pms_constrain_world_1_area_2",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_1_area_2().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_1_area_2(),
             )
             .field(
                 "core_0_region_pms_constrain_world_1_area_3",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_1_area_3().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_1_area_3(),
             )
             .field(
                 "core_0_region_pms_constrain_world_1_area_4",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_1_area_4().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_1_area_4(),
             )
             .field(
                 "core_0_region_pms_constrain_world_1_area_5",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_1_area_5().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_1_area_5(),
             )
             .field(
                 "core_0_region_pms_constrain_world_1_area_6",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_1_area_6().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_1_area_6(),
             )
             .field(
                 "core_0_region_pms_constrain_world_1_area_7",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_1_area_7().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_1_area_7(),
             )
             .field(
                 "core_0_region_pms_constrain_world_1_area_8",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_1_area_8().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_1_area_8(),
             )
             .field(
                 "core_0_region_pms_constrain_world_1_area_9",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_1_area_9().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_1_area_9(),
             )
             .field(
                 "core_0_region_pms_constrain_world_1_area_10",
-                &format_args!(
-                    "{}",
-                    self.core_0_region_pms_constrain_world_1_area_10().bits()
-                ),
+                &self.core_0_region_pms_constrain_world_1_area_10(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_REGION_PMS_CONSTRAIN_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Region 0 permission in world 1 for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_3.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_3.rs
index fafa794fb1..cf2e7862c3 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_3.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_3.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_3")
             .field(
                 "core_0_region_pms_constrain_addr_0",
-                &format_args!("{}", self.core_0_region_pms_constrain_addr_0().bits()),
+                &self.core_0_region_pms_constrain_addr_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_REGION_PMS_CONSTRAIN_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 0 start address for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_4.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_4.rs
index 39c2604686..53027b80a3 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_4.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_4.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_4")
             .field(
                 "core_0_region_pms_constrain_addr_1",
-                &format_args!("{}", self.core_0_region_pms_constrain_addr_1().bits()),
+                &self.core_0_region_pms_constrain_addr_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_REGION_PMS_CONSTRAIN_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 0 end address and Region 1 start address for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_5.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_5.rs
index 42eff459ed..0b5d8686b3 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_5.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_5.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_5")
             .field(
                 "core_0_region_pms_constrain_addr_2",
-                &format_args!("{}", self.core_0_region_pms_constrain_addr_2().bits()),
+                &self.core_0_region_pms_constrain_addr_2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_REGION_PMS_CONSTRAIN_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 1 end address and Region 2 start address for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_6.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_6.rs
index 6603912984..c73b8cdc4f 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_6.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_6.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_6")
             .field(
                 "core_0_region_pms_constrain_addr_3",
-                &format_args!("{}", self.core_0_region_pms_constrain_addr_3().bits()),
+                &self.core_0_region_pms_constrain_addr_3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_REGION_PMS_CONSTRAIN_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 2 end address and Region 3 start address for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_7.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_7.rs
index fd52407dee..8570bd20dc 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_7.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_7.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_7")
             .field(
                 "core_0_region_pms_constrain_addr_4",
-                &format_args!("{}", self.core_0_region_pms_constrain_addr_4().bits()),
+                &self.core_0_region_pms_constrain_addr_4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_REGION_PMS_CONSTRAIN_7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 3 end address and Region 4 start address for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_8.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_8.rs
index 707a30daec..733a2c9d40 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_8.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_8.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_8")
             .field(
                 "core_0_region_pms_constrain_addr_5",
-                &format_args!("{}", self.core_0_region_pms_constrain_addr_5().bits()),
+                &self.core_0_region_pms_constrain_addr_5(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_REGION_PMS_CONSTRAIN_8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 4 end address and Region 5 start address for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_region_pms_constrain_9.rs b/esp32s3/src/sensitive/core_0_region_pms_constrain_9.rs
index 149de425c2..a551b762ab 100644
--- a/esp32s3/src/sensitive/core_0_region_pms_constrain_9.rs
+++ b/esp32s3/src/sensitive/core_0_region_pms_constrain_9.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_REGION_PMS_CONSTRAIN_9")
             .field(
                 "core_0_region_pms_constrain_addr_6",
-                &format_args!("{}", self.core_0_region_pms_constrain_addr_6().bits()),
+                &self.core_0_region_pms_constrain_addr_6(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_REGION_PMS_CONSTRAIN_9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 5 end address and Region 6 start address for core0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_0.rs b/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_0.rs
index 611d975235..4422a76304 100644
--- a/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_0.rs
+++ b/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_0.rs
@@ -21,17 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0")
             .field(
                 "core_0_toomanyexceptions_m_override_lock",
-                &format_args!("{}", self.core_0_toomanyexceptions_m_override_lock().bit()),
+                &self.core_0_toomanyexceptions_m_override_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core0 toomanyexception override configuration register"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_1.rs b/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_1.rs
index a4c550c307..8f6bfd9ccf 100644
--- a/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_1.rs
+++ b/esp32s3/src/sensitive/core_0_toomanyexceptions_m_override_1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1")
             .field(
                 "core_0_toomanyexceptions_m_override",
-                &format_args!("{}", self.core_0_toomanyexceptions_m_override().bit()),
+                &self.core_0_toomanyexceptions_m_override(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to mask toomanyexception."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_vecbase_override_0.rs b/esp32s3/src/sensitive/core_0_vecbase_override_0.rs
index 57d7333f73..0d8d92b7b5 100644
--- a/esp32s3/src/sensitive/core_0_vecbase_override_0.rs
+++ b/esp32s3/src/sensitive/core_0_vecbase_override_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_VECBASE_OVERRIDE_0")
             .field(
                 "core_0_vecbase_world_mask",
-                &format_args!("{}", self.core_0_vecbase_world_mask().bit()),
+                &self.core_0_vecbase_world_mask(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_VECBASE_OVERRIDE_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to mask world, then only world0_value will work."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_vecbase_override_1.rs b/esp32s3/src/sensitive/core_0_vecbase_override_1.rs
index 3aeb90a540..9b4904286b 100644
--- a/esp32s3/src/sensitive/core_0_vecbase_override_1.rs
+++ b/esp32s3/src/sensitive/core_0_vecbase_override_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_VECBASE_OVERRIDE_1")
             .field(
                 "core_0_vecbase_override_world0_value",
-                &format_args!("{}", self.core_0_vecbase_override_world0_value().bits()),
+                &self.core_0_vecbase_override_world0_value(),
             )
             .field(
                 "core_0_vecbase_override_sel",
-                &format_args!("{}", self.core_0_vecbase_override_sel().bits()),
+                &self.core_0_vecbase_override_sel(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_VECBASE_OVERRIDE_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - world0 vecbase_override register, when core0 in world0 use this register to override vecbase register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_vecbase_override_2.rs b/esp32s3/src/sensitive/core_0_vecbase_override_2.rs
index d8768c58f8..494eea4c0f 100644
--- a/esp32s3/src/sensitive/core_0_vecbase_override_2.rs
+++ b/esp32s3/src/sensitive/core_0_vecbase_override_2.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_VECBASE_OVERRIDE_2")
             .field(
                 "core_0_vecbase_override_world1_value",
-                &format_args!("{}", self.core_0_vecbase_override_world1_value().bits()),
+                &self.core_0_vecbase_override_world1_value(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_VECBASE_OVERRIDE_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - world1 vecbase_override register, when core0 in world1 use this register to override vecbase register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_0_vecbase_override_lock.rs b/esp32s3/src/sensitive/core_0_vecbase_override_lock.rs
index 452790c584..95d3d06241 100644
--- a/esp32s3/src/sensitive/core_0_vecbase_override_lock.rs
+++ b/esp32s3/src/sensitive/core_0_vecbase_override_lock.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_0_VECBASE_OVERRIDE_LOCK")
             .field(
                 "core_0_vecbase_override_lock",
-                &format_args!("{}", self.core_0_vecbase_override_lock().bit()),
+                &self.core_0_vecbase_override_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_VECBASE_OVERRIDE_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core0 vecbase configuration register"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_dram0_pms_monitor_0.rs b/esp32s3/src/sensitive/core_1_dram0_pms_monitor_0.rs
index 2c2640d60d..0036ae1a40 100644
--- a/esp32s3/src/sensitive/core_1_dram0_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/core_1_dram0_pms_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_PMS_MONITOR_0")
             .field(
                 "core_1_dram0_pms_monitor_lock",
-                &format_args!("{}", self.core_1_dram0_pms_monitor_lock().bit()),
+                &self.core_1_dram0_pms_monitor_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_PMS_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core1 dram0 permission monitor configuration register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_dram0_pms_monitor_1.rs b/esp32s3/src/sensitive/core_1_dram0_pms_monitor_1.rs
index 7892f428a4..200479ee5d 100644
--- a/esp32s3/src/sensitive/core_1_dram0_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/core_1_dram0_pms_monitor_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_PMS_MONITOR_1")
             .field(
                 "core_1_dram0_pms_monitor_violate_clr",
-                &format_args!("{}", self.core_1_dram0_pms_monitor_violate_clr().bit()),
+                &self.core_1_dram0_pms_monitor_violate_clr(),
             )
             .field(
                 "core_1_dram0_pms_monitor_violate_en",
-                &format_args!("{}", self.core_1_dram0_pms_monitor_violate_en().bit()),
+                &self.core_1_dram0_pms_monitor_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_PMS_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to clear core1 dram0 permission monior interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_dram0_pms_monitor_2.rs b/esp32s3/src/sensitive/core_1_dram0_pms_monitor_2.rs
index 9b3de30d20..f76783b689 100644
--- a/esp32s3/src/sensitive/core_1_dram0_pms_monitor_2.rs
+++ b/esp32s3/src/sensitive/core_1_dram0_pms_monitor_2.rs
@@ -42,38 +42,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_PMS_MONITOR_2")
             .field(
                 "core_1_dram0_pms_monitor_violate_intr",
-                &format_args!("{}", self.core_1_dram0_pms_monitor_violate_intr().bit()),
+                &self.core_1_dram0_pms_monitor_violate_intr(),
             )
             .field(
                 "core_1_dram0_pms_monitor_violate_status_lock",
-                &format_args!(
-                    "{}",
-                    self.core_1_dram0_pms_monitor_violate_status_lock().bit()
-                ),
+                &self.core_1_dram0_pms_monitor_violate_status_lock(),
             )
             .field(
                 "core_1_dram0_pms_monitor_violate_status_world",
-                &format_args!(
-                    "{}",
-                    self.core_1_dram0_pms_monitor_violate_status_world().bits()
-                ),
+                &self.core_1_dram0_pms_monitor_violate_status_world(),
             )
             .field(
                 "core_1_dram0_pms_monitor_violate_status_addr",
-                &format_args!(
-                    "{}",
-                    self.core_1_dram0_pms_monitor_violate_status_addr().bits()
-                ),
+                &self.core_1_dram0_pms_monitor_violate_status_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_PMS_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core1 dram0 permission monitor configuration register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_pms_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_DRAM0_PMS_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_1_DRAM0_PMS_MONITOR_2_SPEC {
diff --git a/esp32s3/src/sensitive/core_1_dram0_pms_monitor_3.rs b/esp32s3/src/sensitive/core_1_dram0_pms_monitor_3.rs
index cf350c67f0..f729cfd0b6 100644
--- a/esp32s3/src/sensitive/core_1_dram0_pms_monitor_3.rs
+++ b/esp32s3/src/sensitive/core_1_dram0_pms_monitor_3.rs
@@ -26,27 +26,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_DRAM0_PMS_MONITOR_3")
             .field(
                 "core_1_dram0_pms_monitor_violate_status_wr",
-                &format_args!(
-                    "{}",
-                    self.core_1_dram0_pms_monitor_violate_status_wr().bit()
-                ),
+                &self.core_1_dram0_pms_monitor_violate_status_wr(),
             )
             .field(
                 "core_1_dram0_pms_monitor_violate_status_byteen",
-                &format_args!(
-                    "{}",
-                    self.core_1_dram0_pms_monitor_violate_status_byteen().bits()
-                ),
+                &self.core_1_dram0_pms_monitor_violate_status_byteen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_DRAM0_PMS_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core1 dram0 permission monitor configuration register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_dram0_pms_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_DRAM0_PMS_MONITOR_3_SPEC;
 impl crate::RegisterSpec for CORE_1_DRAM0_PMS_MONITOR_3_SPEC {
diff --git a/esp32s3/src/sensitive/core_1_iram0_pms_monitor_0.rs b/esp32s3/src/sensitive/core_1_iram0_pms_monitor_0.rs
index 63a0f5fc6f..370dbe2c78 100644
--- a/esp32s3/src/sensitive/core_1_iram0_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/core_1_iram0_pms_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_IRAM0_PMS_MONITOR_0")
             .field(
                 "core_1_iram0_pms_monitor_lock",
-                &format_args!("{}", self.core_1_iram0_pms_monitor_lock().bit()),
+                &self.core_1_iram0_pms_monitor_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_IRAM0_PMS_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core1 iram0 permission monitor register"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_iram0_pms_monitor_1.rs b/esp32s3/src/sensitive/core_1_iram0_pms_monitor_1.rs
index c160df5543..2eba76ba91 100644
--- a/esp32s3/src/sensitive/core_1_iram0_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/core_1_iram0_pms_monitor_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_IRAM0_PMS_MONITOR_1")
             .field(
                 "core_1_iram0_pms_monitor_violate_clr",
-                &format_args!("{}", self.core_1_iram0_pms_monitor_violate_clr().bit()),
+                &self.core_1_iram0_pms_monitor_violate_clr(),
             )
             .field(
                 "core_1_iram0_pms_monitor_violate_en",
-                &format_args!("{}", self.core_1_iram0_pms_monitor_violate_en().bit()),
+                &self.core_1_iram0_pms_monitor_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_IRAM0_PMS_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to clear core1 iram0 permission violated interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_iram0_pms_monitor_2.rs b/esp32s3/src/sensitive/core_1_iram0_pms_monitor_2.rs
index 6b7a3d818d..3870b37cb6 100644
--- a/esp32s3/src/sensitive/core_1_iram0_pms_monitor_2.rs
+++ b/esp32s3/src/sensitive/core_1_iram0_pms_monitor_2.rs
@@ -51,46 +51,27 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_IRAM0_PMS_MONITOR_2")
             .field(
                 "core_1_iram0_pms_monitor_violate_intr",
-                &format_args!("{}", self.core_1_iram0_pms_monitor_violate_intr().bit()),
+                &self.core_1_iram0_pms_monitor_violate_intr(),
             )
             .field(
                 "core_1_iram0_pms_monitor_violate_status_wr",
-                &format_args!(
-                    "{}",
-                    self.core_1_iram0_pms_monitor_violate_status_wr().bit()
-                ),
+                &self.core_1_iram0_pms_monitor_violate_status_wr(),
             )
             .field(
                 "core_1_iram0_pms_monitor_violate_status_loadstore",
-                &format_args!(
-                    "{}",
-                    self.core_1_iram0_pms_monitor_violate_status_loadstore()
-                        .bit()
-                ),
+                &self.core_1_iram0_pms_monitor_violate_status_loadstore(),
             )
             .field(
                 "core_1_iram0_pms_monitor_violate_status_world",
-                &format_args!(
-                    "{}",
-                    self.core_1_iram0_pms_monitor_violate_status_world().bits()
-                ),
+                &self.core_1_iram0_pms_monitor_violate_status_world(),
             )
             .field(
                 "core_1_iram0_pms_monitor_violate_status_addr",
-                &format_args!(
-                    "{}",
-                    self.core_1_iram0_pms_monitor_violate_status_addr().bits()
-                ),
+                &self.core_1_iram0_pms_monitor_violate_status_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_IRAM0_PMS_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core1 iram0 permission monitor configuration register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_iram0_pms_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_IRAM0_PMS_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_1_IRAM0_PMS_MONITOR_2_SPEC {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_0.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_0.rs
index e7014d55d9..4be8d8e182 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_0")
             .field(
                 "core_1_pif_pms_constrain_lock",
-                &format_args!("{}", self.core_1_pif_pms_constrain_lock().bit()),
+                &self.core_1_pif_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core1 pif permission configuration register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_1.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_1.rs
index eee813448d..3a34a13434 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_1.rs
@@ -135,65 +135,59 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_1")
             .field(
                 "core_1_pif_pms_constrain_world_0_uart",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_uart().bits()),
+                &self.core_1_pif_pms_constrain_world_0_uart(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_g0spi_1",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_g0spi_1().bits()),
+                &self.core_1_pif_pms_constrain_world_0_g0spi_1(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_g0spi_0",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_g0spi_0().bits()),
+                &self.core_1_pif_pms_constrain_world_0_g0spi_0(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_gpio",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_gpio().bits()),
+                &self.core_1_pif_pms_constrain_world_0_gpio(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_fe2",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_fe2().bits()),
+                &self.core_1_pif_pms_constrain_world_0_fe2(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_fe",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_fe().bits()),
+                &self.core_1_pif_pms_constrain_world_0_fe(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_rtc",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_rtc().bits()),
+                &self.core_1_pif_pms_constrain_world_0_rtc(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_io_mux",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_io_mux().bits()),
+                &self.core_1_pif_pms_constrain_world_0_io_mux(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_hinf",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_hinf().bits()),
+                &self.core_1_pif_pms_constrain_world_0_hinf(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_misc",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_misc().bits()),
+                &self.core_1_pif_pms_constrain_world_0_misc(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_i2c",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_i2c().bits()),
+                &self.core_1_pif_pms_constrain_world_0_i2c(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_i2s0",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_i2s0().bits()),
+                &self.core_1_pif_pms_constrain_world_0_i2s0(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_uart1",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_uart1().bits()),
+                &self.core_1_pif_pms_constrain_world_0_uart1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core1 access uart permission in world0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_10.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_10.rs
index a0bd923647..6a998b3eab 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_10.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_10.rs
@@ -54,41 +54,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_10")
             .field(
                 "core_1_pif_pms_constrain_rtcfast_world_0_l",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcfast_world_0_l().bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcfast_world_0_l(),
             )
             .field(
                 "core_1_pif_pms_constrain_rtcfast_world_0_h",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcfast_world_0_h().bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcfast_world_0_h(),
             )
             .field(
                 "core_1_pif_pms_constrain_rtcfast_world_1_l",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcfast_world_1_l().bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcfast_world_1_l(),
             )
             .field(
                 "core_1_pif_pms_constrain_rtcfast_world_1_h",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcfast_world_1_h().bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcfast_world_1_h(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_CONSTRAIN_10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - RTCFast memory low region permission in world 0 for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_11.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_11.rs
index ff267db5dd..384b7aa10f 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_11.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_11.rs
@@ -36,29 +36,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_11")
             .field(
                 "core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_0",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_0()
-                        .bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_0(),
             )
             .field(
                 "core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_1",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_1()
-                        .bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_CONSTRAIN_11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - RTCSlow_0 memory split address in world 0 for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_12.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_12.rs
index d621f4dcd7..f8b1cd668e 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_12.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_12.rs
@@ -54,41 +54,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_12")
             .field(
                 "core_1_pif_pms_constrain_rtcslow_0_world_0_l",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcslow_0_world_0_l().bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcslow_0_world_0_l(),
             )
             .field(
                 "core_1_pif_pms_constrain_rtcslow_0_world_0_h",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcslow_0_world_0_h().bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcslow_0_world_0_h(),
             )
             .field(
                 "core_1_pif_pms_constrain_rtcslow_0_world_1_l",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcslow_0_world_1_l().bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcslow_0_world_1_l(),
             )
             .field(
                 "core_1_pif_pms_constrain_rtcslow_0_world_1_h",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcslow_0_world_1_h().bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcslow_0_world_1_h(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_CONSTRAIN_12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - RTCSlow_0 memory low region permission in world 0 for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_13.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_13.rs
index 20f9868357..5363b275d8 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_13.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_13.rs
@@ -36,29 +36,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_13")
             .field(
                 "core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_0",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_0()
-                        .bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_0(),
             )
             .field(
                 "core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_1",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_1()
-                        .bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_CONSTRAIN_13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - RTCSlow_1 memory split address in world 0 for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_14.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_14.rs
index ba4c2a04ea..5fa902caaa 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_14.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_14.rs
@@ -54,41 +54,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_14")
             .field(
                 "core_1_pif_pms_constrain_rtcslow_1_world_0_l",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcslow_1_world_0_l().bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcslow_1_world_0_l(),
             )
             .field(
                 "core_1_pif_pms_constrain_rtcslow_1_world_0_h",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcslow_1_world_0_h().bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcslow_1_world_0_h(),
             )
             .field(
                 "core_1_pif_pms_constrain_rtcslow_1_world_1_l",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcslow_1_world_1_l().bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcslow_1_world_1_l(),
             )
             .field(
                 "core_1_pif_pms_constrain_rtcslow_1_world_1_h",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcslow_1_world_1_h().bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcslow_1_world_1_h(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_CONSTRAIN_14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - RTCSlow_1 memory low region permission in world 0 for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_2.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_2.rs
index f86c8a2642..5e7acc7b41 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_2.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_2.rs
@@ -150,81 +150,63 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_2")
             .field(
                 "core_1_pif_pms_constrain_world_0_bt",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_bt().bits()),
+                &self.core_1_pif_pms_constrain_world_0_bt(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_i2c_ext0",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_i2c_ext0().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_i2c_ext0(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_uhci0",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_uhci0().bits()),
+                &self.core_1_pif_pms_constrain_world_0_uhci0(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_slchost",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_slchost().bits()),
+                &self.core_1_pif_pms_constrain_world_0_slchost(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_rmt",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_rmt().bits()),
+                &self.core_1_pif_pms_constrain_world_0_rmt(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_pcnt",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_pcnt().bits()),
+                &self.core_1_pif_pms_constrain_world_0_pcnt(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_slc",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_slc().bits()),
+                &self.core_1_pif_pms_constrain_world_0_slc(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_ledc",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_ledc().bits()),
+                &self.core_1_pif_pms_constrain_world_0_ledc(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_backup",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_backup().bits()),
+                &self.core_1_pif_pms_constrain_world_0_backup(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_bb",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_bb().bits()),
+                &self.core_1_pif_pms_constrain_world_0_bb(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_pwm0",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_pwm0().bits()),
+                &self.core_1_pif_pms_constrain_world_0_pwm0(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_timergroup",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_timergroup().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_timergroup(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_timergroup1",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_timergroup1().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_timergroup1(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_systimer",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_systimer().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_systimer(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_CONSTRAIN_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core1 access bt permission in world0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_3.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_3.rs
index f78ffbc595..e7d96b1c8e 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_3.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_3.rs
@@ -132,70 +132,55 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_3")
             .field(
                 "core_1_pif_pms_constrain_world_0_spi_2",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_spi_2().bits()),
+                &self.core_1_pif_pms_constrain_world_0_spi_2(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_spi_3",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_spi_3().bits()),
+                &self.core_1_pif_pms_constrain_world_0_spi_3(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_apb_ctrl",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_apb_ctrl().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_apb_ctrl(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_i2c_ext1",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_i2c_ext1().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_i2c_ext1(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_sdio_host",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_sdio_host().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_sdio_host(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_can",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_can().bits()),
+                &self.core_1_pif_pms_constrain_world_0_can(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_pwm1",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_pwm1().bits()),
+                &self.core_1_pif_pms_constrain_world_0_pwm1(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_i2s1",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_i2s1().bits()),
+                &self.core_1_pif_pms_constrain_world_0_i2s1(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_uart2",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_uart2().bits()),
+                &self.core_1_pif_pms_constrain_world_0_uart2(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_rwbt",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_rwbt().bits()),
+                &self.core_1_pif_pms_constrain_world_0_rwbt(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_wifimac",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_wifimac().bits()),
+                &self.core_1_pif_pms_constrain_world_0_wifimac(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_pwr",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_pwr().bits()),
+                &self.core_1_pif_pms_constrain_world_0_pwr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_CONSTRAIN_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core1 access spi_2 permission in world0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_4.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_4.rs
index d3808fa3c3..ee71e5c0ee 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_4.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_4.rs
@@ -181,105 +181,71 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_4")
             .field(
                 "core_1_pif_pms_constrain_world_0_usb_device",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_usb_device().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_usb_device(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_usb_wrap",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_usb_wrap().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_usb_wrap(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_crypto_peri",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_crypto_peri().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_crypto_peri(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_crypto_dma",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_crypto_dma().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_crypto_dma(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_apb_adc",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_apb_adc().bits()),
+                &self.core_1_pif_pms_constrain_world_0_apb_adc(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_lcd_cam",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_lcd_cam().bits()),
+                &self.core_1_pif_pms_constrain_world_0_lcd_cam(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_bt_pwr",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_bt_pwr().bits()),
+                &self.core_1_pif_pms_constrain_world_0_bt_pwr(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_usb",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_usb().bits()),
+                &self.core_1_pif_pms_constrain_world_0_usb(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_system",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_system().bits()),
+                &self.core_1_pif_pms_constrain_world_0_system(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_sensitive",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_sensitive().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_sensitive(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_interrupt",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_interrupt().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_interrupt(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_dma_copy",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_dma_copy().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_dma_copy(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_cache_config",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_cache_config().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_cache_config(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_ad",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_ad().bits()),
+                &self.core_1_pif_pms_constrain_world_0_ad(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_dio",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_0_dio().bits()),
+                &self.core_1_pif_pms_constrain_world_0_dio(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_0_world_controller",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_0_world_controller()
-                        .bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_0_world_controller(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_CONSTRAIN_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core1 access usb_device permission in world0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_5.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_5.rs
index 50101426e1..75b2df41a9 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_5.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_5.rs
@@ -135,65 +135,59 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_5")
             .field(
                 "core_1_pif_pms_constrain_world_1_uart",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_uart().bits()),
+                &self.core_1_pif_pms_constrain_world_1_uart(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_g0spi_1",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_g0spi_1().bits()),
+                &self.core_1_pif_pms_constrain_world_1_g0spi_1(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_g0spi_0",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_g0spi_0().bits()),
+                &self.core_1_pif_pms_constrain_world_1_g0spi_0(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_gpio",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_gpio().bits()),
+                &self.core_1_pif_pms_constrain_world_1_gpio(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_fe2",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_fe2().bits()),
+                &self.core_1_pif_pms_constrain_world_1_fe2(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_fe",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_fe().bits()),
+                &self.core_1_pif_pms_constrain_world_1_fe(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_rtc",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_rtc().bits()),
+                &self.core_1_pif_pms_constrain_world_1_rtc(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_io_mux",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_io_mux().bits()),
+                &self.core_1_pif_pms_constrain_world_1_io_mux(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_hinf",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_hinf().bits()),
+                &self.core_1_pif_pms_constrain_world_1_hinf(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_misc",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_misc().bits()),
+                &self.core_1_pif_pms_constrain_world_1_misc(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_i2c",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_i2c().bits()),
+                &self.core_1_pif_pms_constrain_world_1_i2c(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_i2s0",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_i2s0().bits()),
+                &self.core_1_pif_pms_constrain_world_1_i2s0(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_uart1",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_uart1().bits()),
+                &self.core_1_pif_pms_constrain_world_1_uart1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core1 access uart permission in world1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_6.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_6.rs
index e3b51e17ad..d2b9933db8 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_6.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_6.rs
@@ -150,81 +150,63 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_6")
             .field(
                 "core_1_pif_pms_constrain_world_1_bt",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_bt().bits()),
+                &self.core_1_pif_pms_constrain_world_1_bt(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_i2c_ext0",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_i2c_ext0().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_i2c_ext0(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_uhci0",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_uhci0().bits()),
+                &self.core_1_pif_pms_constrain_world_1_uhci0(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_slchost",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_slchost().bits()),
+                &self.core_1_pif_pms_constrain_world_1_slchost(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_rmt",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_rmt().bits()),
+                &self.core_1_pif_pms_constrain_world_1_rmt(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_pcnt",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_pcnt().bits()),
+                &self.core_1_pif_pms_constrain_world_1_pcnt(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_slc",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_slc().bits()),
+                &self.core_1_pif_pms_constrain_world_1_slc(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_ledc",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_ledc().bits()),
+                &self.core_1_pif_pms_constrain_world_1_ledc(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_backup",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_backup().bits()),
+                &self.core_1_pif_pms_constrain_world_1_backup(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_bb",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_bb().bits()),
+                &self.core_1_pif_pms_constrain_world_1_bb(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_pwm0",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_pwm0().bits()),
+                &self.core_1_pif_pms_constrain_world_1_pwm0(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_timergroup",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_timergroup().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_timergroup(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_timergroup1",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_timergroup1().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_timergroup1(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_systimer",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_systimer().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_systimer(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_CONSTRAIN_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core1 access bt permission in world1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_7.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_7.rs
index 6768ed1f73..42f7d5e9d3 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_7.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_7.rs
@@ -132,70 +132,55 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_7")
             .field(
                 "core_1_pif_pms_constrain_world_1_spi_2",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_spi_2().bits()),
+                &self.core_1_pif_pms_constrain_world_1_spi_2(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_spi_3",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_spi_3().bits()),
+                &self.core_1_pif_pms_constrain_world_1_spi_3(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_apb_ctrl",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_apb_ctrl().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_apb_ctrl(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_i2c_ext1",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_i2c_ext1().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_i2c_ext1(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_sdio_host",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_sdio_host().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_sdio_host(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_can",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_can().bits()),
+                &self.core_1_pif_pms_constrain_world_1_can(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_pwm1",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_pwm1().bits()),
+                &self.core_1_pif_pms_constrain_world_1_pwm1(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_i2s1",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_i2s1().bits()),
+                &self.core_1_pif_pms_constrain_world_1_i2s1(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_uart2",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_uart2().bits()),
+                &self.core_1_pif_pms_constrain_world_1_uart2(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_rwbt",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_rwbt().bits()),
+                &self.core_1_pif_pms_constrain_world_1_rwbt(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_wifimac",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_wifimac().bits()),
+                &self.core_1_pif_pms_constrain_world_1_wifimac(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_pwr",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_pwr().bits()),
+                &self.core_1_pif_pms_constrain_world_1_pwr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_CONSTRAIN_7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core1 access spi_2 permission in world1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_8.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_8.rs
index 7db4fc47f4..fd0951f44a 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_8.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_8.rs
@@ -181,105 +181,71 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_8")
             .field(
                 "core_1_pif_pms_constrain_world_1_usb_device",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_usb_device().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_usb_device(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_usb_wrap",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_usb_wrap().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_usb_wrap(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_crypto_peri",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_crypto_peri().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_crypto_peri(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_crypto_dma",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_crypto_dma().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_crypto_dma(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_apb_adc",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_apb_adc().bits()),
+                &self.core_1_pif_pms_constrain_world_1_apb_adc(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_lcd_cam",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_lcd_cam().bits()),
+                &self.core_1_pif_pms_constrain_world_1_lcd_cam(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_bt_pwr",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_bt_pwr().bits()),
+                &self.core_1_pif_pms_constrain_world_1_bt_pwr(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_usb",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_usb().bits()),
+                &self.core_1_pif_pms_constrain_world_1_usb(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_system",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_system().bits()),
+                &self.core_1_pif_pms_constrain_world_1_system(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_sensitive",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_sensitive().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_sensitive(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_interrupt",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_interrupt().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_interrupt(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_dma_copy",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_dma_copy().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_dma_copy(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_cache_config",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_cache_config().bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_cache_config(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_ad",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_ad().bits()),
+                &self.core_1_pif_pms_constrain_world_1_ad(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_dio",
-                &format_args!("{}", self.core_1_pif_pms_constrain_world_1_dio().bits()),
+                &self.core_1_pif_pms_constrain_world_1_dio(),
             )
             .field(
                 "core_1_pif_pms_constrain_world_1_world_controller",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_world_1_world_controller()
-                        .bits()
-                ),
+                &self.core_1_pif_pms_constrain_world_1_world_controller(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_CONSTRAIN_8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Core1 access usb_device permission in world1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_constrain_9.rs b/esp32s3/src/sensitive/core_1_pif_pms_constrain_9.rs
index fbacb4e918..1485507438 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_constrain_9.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_constrain_9.rs
@@ -36,29 +36,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_CONSTRAIN_9")
             .field(
                 "core_1_pif_pms_constrain_rtcfast_spltaddr_world_0",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcfast_spltaddr_world_0()
-                        .bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcfast_spltaddr_world_0(),
             )
             .field(
                 "core_1_pif_pms_constrain_rtcfast_spltaddr_world_1",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_constrain_rtcfast_spltaddr_world_1()
-                        .bits()
-                ),
+                &self.core_1_pif_pms_constrain_rtcfast_spltaddr_world_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_CONSTRAIN_9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10 - RTCFast memory split address in world 0 for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_monitor_0.rs b/esp32s3/src/sensitive/core_1_pif_pms_monitor_0.rs
index 444c45bc76..9eb2abc1ea 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_MONITOR_0")
             .field(
                 "core_1_pif_pms_monitor_lock",
-                &format_args!("{}", self.core_1_pif_pms_monitor_lock().bit()),
+                &self.core_1_pif_pms_monitor_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core1 permission report registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_monitor_1.rs b/esp32s3/src/sensitive/core_1_pif_pms_monitor_1.rs
index 12c977b2ad..4fbd5d1e53 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_monitor_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_MONITOR_1")
             .field(
                 "core_1_pif_pms_monitor_violate_clr",
-                &format_args!("{}", self.core_1_pif_pms_monitor_violate_clr().bit()),
+                &self.core_1_pif_pms_monitor_violate_clr(),
             )
             .field(
                 "core_1_pif_pms_monitor_violate_en",
-                &format_args!("{}", self.core_1_pif_pms_monitor_violate_en().bit()),
+                &self.core_1_pif_pms_monitor_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to clear interrupt that core1 initiate illegal PIF bus access."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_monitor_2.rs b/esp32s3/src/sensitive/core_1_pif_pms_monitor_2.rs
index b9d8d01969..cc80afbf20 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_monitor_2.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_monitor_2.rs
@@ -51,45 +51,27 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_MONITOR_2")
             .field(
                 "core_1_pif_pms_monitor_violate_intr",
-                &format_args!("{}", self.core_1_pif_pms_monitor_violate_intr().bit()),
+                &self.core_1_pif_pms_monitor_violate_intr(),
             )
             .field(
                 "core_1_pif_pms_monitor_violate_status_hport_0",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_monitor_violate_status_hport_0().bit()
-                ),
+                &self.core_1_pif_pms_monitor_violate_status_hport_0(),
             )
             .field(
                 "core_1_pif_pms_monitor_violate_status_hsize",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_monitor_violate_status_hsize().bits()
-                ),
+                &self.core_1_pif_pms_monitor_violate_status_hsize(),
             )
             .field(
                 "core_1_pif_pms_monitor_violate_status_hwrite",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_monitor_violate_status_hwrite().bit()
-                ),
+                &self.core_1_pif_pms_monitor_violate_status_hwrite(),
             )
             .field(
                 "core_1_pif_pms_monitor_violate_status_hworld",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_monitor_violate_status_hworld().bits()
-                ),
+                &self.core_1_pif_pms_monitor_violate_status_hworld(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core1 permission report register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_pif_pms_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_PIF_PMS_MONITOR_2_SPEC;
 impl crate::RegisterSpec for CORE_1_PIF_PMS_MONITOR_2_SPEC {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_monitor_3.rs b/esp32s3/src/sensitive/core_1_pif_pms_monitor_3.rs
index 9f1f938743..925dca84a6 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_monitor_3.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_monitor_3.rs
@@ -17,20 +17,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_MONITOR_3")
             .field(
                 "core_1_pif_pms_monitor_violate_status_haddr",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_monitor_violate_status_haddr().bits()
-                ),
+                &self.core_1_pif_pms_monitor_violate_status_haddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core1 permission report register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_pif_pms_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_PIF_PMS_MONITOR_3_SPEC;
 impl crate::RegisterSpec for CORE_1_PIF_PMS_MONITOR_3_SPEC {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_monitor_4.rs b/esp32s3/src/sensitive/core_1_pif_pms_monitor_4.rs
index 00ec72b7a1..98f5bddacc 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_monitor_4.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_monitor_4.rs
@@ -32,24 +32,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_MONITOR_4")
             .field(
                 "core_1_pif_pms_monitor_nonword_violate_clr",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_monitor_nonword_violate_clr().bit()
-                ),
+                &self.core_1_pif_pms_monitor_nonword_violate_clr(),
             )
             .field(
                 "core_1_pif_pms_monitor_nonword_violate_en",
-                &format_args!("{}", self.core_1_pif_pms_monitor_nonword_violate_en().bit()),
+                &self.core_1_pif_pms_monitor_nonword_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_MONITOR_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to clear interrupt that core1 initiate unsupported access type."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_monitor_5.rs b/esp32s3/src/sensitive/core_1_pif_pms_monitor_5.rs
index bf41ac4310..043794d247 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_monitor_5.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_monitor_5.rs
@@ -35,36 +35,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_MONITOR_5")
             .field(
                 "core_1_pif_pms_monitor_nonword_violate_intr",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_monitor_nonword_violate_intr().bit()
-                ),
+                &self.core_1_pif_pms_monitor_nonword_violate_intr(),
             )
             .field(
                 "core_1_pif_pms_monitor_nonword_violate_status_hsize",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_monitor_nonword_violate_status_hsize()
-                        .bits()
-                ),
+                &self.core_1_pif_pms_monitor_nonword_violate_status_hsize(),
             )
             .field(
                 "core_1_pif_pms_monitor_nonword_violate_status_hworld",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_monitor_nonword_violate_status_hworld()
-                        .bits()
-                ),
+                &self.core_1_pif_pms_monitor_nonword_violate_status_hworld(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_MONITOR_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core1 permission report register 5.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_pif_pms_monitor_5::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_PIF_PMS_MONITOR_5_SPEC;
 impl crate::RegisterSpec for CORE_1_PIF_PMS_MONITOR_5_SPEC {
diff --git a/esp32s3/src/sensitive/core_1_pif_pms_monitor_6.rs b/esp32s3/src/sensitive/core_1_pif_pms_monitor_6.rs
index 5c40d39e4c..947fc84ffb 100644
--- a/esp32s3/src/sensitive/core_1_pif_pms_monitor_6.rs
+++ b/esp32s3/src/sensitive/core_1_pif_pms_monitor_6.rs
@@ -17,21 +17,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_PIF_PMS_MONITOR_6")
             .field(
                 "core_1_pif_pms_monitor_nonword_violate_status_haddr",
-                &format_args!(
-                    "{}",
-                    self.core_1_pif_pms_monitor_nonword_violate_status_haddr()
-                        .bits()
-                ),
+                &self.core_1_pif_pms_monitor_nonword_violate_status_haddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_PIF_PMS_MONITOR_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "core1 permission report register 6.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_pif_pms_monitor_6::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_PIF_PMS_MONITOR_6_SPEC;
 impl crate::RegisterSpec for CORE_1_PIF_PMS_MONITOR_6_SPEC {
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_0.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_0.rs
index 4fbd003a21..828dd4f99b 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_0")
             .field(
                 "core_1_region_pms_constrain_lock",
-                &format_args!("{}", self.core_1_region_pms_constrain_lock().bit()),
+                &self.core_1_region_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_REGION_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core1 region permission registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_1.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_1.rs
index 23378a137c..413a557638 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_1.rs
@@ -131,90 +131,51 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_1")
             .field(
                 "core_1_region_pms_constrain_world_0_area_0",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_0_area_0().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_0_area_0(),
             )
             .field(
                 "core_1_region_pms_constrain_world_0_area_1",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_0_area_1().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_0_area_1(),
             )
             .field(
                 "core_1_region_pms_constrain_world_0_area_2",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_0_area_2().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_0_area_2(),
             )
             .field(
                 "core_1_region_pms_constrain_world_0_area_3",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_0_area_3().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_0_area_3(),
             )
             .field(
                 "core_1_region_pms_constrain_world_0_area_4",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_0_area_4().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_0_area_4(),
             )
             .field(
                 "core_1_region_pms_constrain_world_0_area_5",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_0_area_5().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_0_area_5(),
             )
             .field(
                 "core_1_region_pms_constrain_world_0_area_6",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_0_area_6().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_0_area_6(),
             )
             .field(
                 "core_1_region_pms_constrain_world_0_area_7",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_0_area_7().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_0_area_7(),
             )
             .field(
                 "core_1_region_pms_constrain_world_0_area_8",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_0_area_8().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_0_area_8(),
             )
             .field(
                 "core_1_region_pms_constrain_world_0_area_9",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_0_area_9().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_0_area_9(),
             )
             .field(
                 "core_1_region_pms_constrain_world_0_area_10",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_0_area_10().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_0_area_10(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_REGION_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Region 0 permission in world 0 for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_10.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_10.rs
index 314384a112..e055ea722b 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_10.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_10.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_10")
             .field(
                 "core_1_region_pms_constrain_addr_7",
-                &format_args!("{}", self.core_1_region_pms_constrain_addr_7().bits()),
+                &self.core_1_region_pms_constrain_addr_7(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_REGION_PMS_CONSTRAIN_10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 6 end address and Region 7 start address for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_11.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_11.rs
index a1235fb37a..d7b55a2c2f 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_11.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_11.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_11")
             .field(
                 "core_1_region_pms_constrain_addr_8",
-                &format_args!("{}", self.core_1_region_pms_constrain_addr_8().bits()),
+                &self.core_1_region_pms_constrain_addr_8(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_REGION_PMS_CONSTRAIN_11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 7 end address and Region 8 start address for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_12.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_12.rs
index 7bba40dd77..187660708e 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_12.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_12.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_12")
             .field(
                 "core_1_region_pms_constrain_addr_9",
-                &format_args!("{}", self.core_1_region_pms_constrain_addr_9().bits()),
+                &self.core_1_region_pms_constrain_addr_9(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_REGION_PMS_CONSTRAIN_12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 8 end address and Region 9 start address for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_13.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_13.rs
index a156f84b7f..7b2ea9ae7c 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_13.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_13.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_13")
             .field(
                 "core_1_region_pms_constrain_addr_10",
-                &format_args!("{}", self.core_1_region_pms_constrain_addr_10().bits()),
+                &self.core_1_region_pms_constrain_addr_10(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_REGION_PMS_CONSTRAIN_13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 9 end address and Region 10 start address for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_14.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_14.rs
index df43ef5c9a..7ea55562cb 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_14.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_14.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_14")
             .field(
                 "core_1_region_pms_constrain_addr_11",
-                &format_args!("{}", self.core_1_region_pms_constrain_addr_11().bits()),
+                &self.core_1_region_pms_constrain_addr_11(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_REGION_PMS_CONSTRAIN_14_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 10 end address for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_2.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_2.rs
index 86a0bcbda8..2a81bd4aac 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_2.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_2.rs
@@ -131,90 +131,51 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_2")
             .field(
                 "core_1_region_pms_constrain_world_1_area_0",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_1_area_0().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_1_area_0(),
             )
             .field(
                 "core_1_region_pms_constrain_world_1_area_1",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_1_area_1().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_1_area_1(),
             )
             .field(
                 "core_1_region_pms_constrain_world_1_area_2",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_1_area_2().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_1_area_2(),
             )
             .field(
                 "core_1_region_pms_constrain_world_1_area_3",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_1_area_3().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_1_area_3(),
             )
             .field(
                 "core_1_region_pms_constrain_world_1_area_4",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_1_area_4().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_1_area_4(),
             )
             .field(
                 "core_1_region_pms_constrain_world_1_area_5",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_1_area_5().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_1_area_5(),
             )
             .field(
                 "core_1_region_pms_constrain_world_1_area_6",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_1_area_6().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_1_area_6(),
             )
             .field(
                 "core_1_region_pms_constrain_world_1_area_7",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_1_area_7().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_1_area_7(),
             )
             .field(
                 "core_1_region_pms_constrain_world_1_area_8",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_1_area_8().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_1_area_8(),
             )
             .field(
                 "core_1_region_pms_constrain_world_1_area_9",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_1_area_9().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_1_area_9(),
             )
             .field(
                 "core_1_region_pms_constrain_world_1_area_10",
-                &format_args!(
-                    "{}",
-                    self.core_1_region_pms_constrain_world_1_area_10().bits()
-                ),
+                &self.core_1_region_pms_constrain_world_1_area_10(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_REGION_PMS_CONSTRAIN_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Region 0 permission in world 1 for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_3.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_3.rs
index e08330d63f..2760415594 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_3.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_3.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_3")
             .field(
                 "core_1_region_pms_constrain_addr_0",
-                &format_args!("{}", self.core_1_region_pms_constrain_addr_0().bits()),
+                &self.core_1_region_pms_constrain_addr_0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_REGION_PMS_CONSTRAIN_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 0 start address for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_4.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_4.rs
index b848954de0..cfc1027db0 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_4.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_4.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_4")
             .field(
                 "core_1_region_pms_constrain_addr_1",
-                &format_args!("{}", self.core_1_region_pms_constrain_addr_1().bits()),
+                &self.core_1_region_pms_constrain_addr_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_REGION_PMS_CONSTRAIN_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 0 end address and Region 1 start address for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_5.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_5.rs
index 8f04e9cf3c..f9f6d043e5 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_5.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_5.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_5")
             .field(
                 "core_1_region_pms_constrain_addr_2",
-                &format_args!("{}", self.core_1_region_pms_constrain_addr_2().bits()),
+                &self.core_1_region_pms_constrain_addr_2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_REGION_PMS_CONSTRAIN_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 1 end address and Region 2 start address for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_6.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_6.rs
index 2f764a2358..c7d39f787e 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_6.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_6.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_6")
             .field(
                 "core_1_region_pms_constrain_addr_3",
-                &format_args!("{}", self.core_1_region_pms_constrain_addr_3().bits()),
+                &self.core_1_region_pms_constrain_addr_3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_REGION_PMS_CONSTRAIN_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 2 end address and Region 3 start address for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_7.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_7.rs
index f12f2d6166..5e7bc76e56 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_7.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_7.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_7")
             .field(
                 "core_1_region_pms_constrain_addr_4",
-                &format_args!("{}", self.core_1_region_pms_constrain_addr_4().bits()),
+                &self.core_1_region_pms_constrain_addr_4(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_REGION_PMS_CONSTRAIN_7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 3 end address and Region 4 start address for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_8.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_8.rs
index 381bac6153..1e23de0aba 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_8.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_8.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_8")
             .field(
                 "core_1_region_pms_constrain_addr_5",
-                &format_args!("{}", self.core_1_region_pms_constrain_addr_5().bits()),
+                &self.core_1_region_pms_constrain_addr_5(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_REGION_PMS_CONSTRAIN_8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 4 end address and Region 5 start address for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_region_pms_constrain_9.rs b/esp32s3/src/sensitive/core_1_region_pms_constrain_9.rs
index 22cc6e160a..193f5f489c 100644
--- a/esp32s3/src/sensitive/core_1_region_pms_constrain_9.rs
+++ b/esp32s3/src/sensitive/core_1_region_pms_constrain_9.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_REGION_PMS_CONSTRAIN_9")
             .field(
                 "core_1_region_pms_constrain_addr_6",
-                &format_args!("{}", self.core_1_region_pms_constrain_addr_6().bits()),
+                &self.core_1_region_pms_constrain_addr_6(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_REGION_PMS_CONSTRAIN_9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Region 5 end address and Region 6 start address for core1."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_0.rs b/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_0.rs
index d4e5077c64..fc393c0c91 100644
--- a/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_0.rs
+++ b/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_0.rs
@@ -21,17 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0")
             .field(
                 "core_1_toomanyexceptions_m_override_lock",
-                &format_args!("{}", self.core_1_toomanyexceptions_m_override_lock().bit()),
+                &self.core_1_toomanyexceptions_m_override_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core1 toomanyexception override configuration register"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_1.rs b/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_1.rs
index a757b39569..6039306502 100644
--- a/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_1.rs
+++ b/esp32s3/src/sensitive/core_1_toomanyexceptions_m_override_1.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1")
             .field(
                 "core_1_toomanyexceptions_m_override",
-                &format_args!("{}", self.core_1_toomanyexceptions_m_override().bit()),
+                &self.core_1_toomanyexceptions_m_override(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to mask toomanyexception."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_vecbase_override_0.rs b/esp32s3/src/sensitive/core_1_vecbase_override_0.rs
index 84b8daabf8..1963c048f4 100644
--- a/esp32s3/src/sensitive/core_1_vecbase_override_0.rs
+++ b/esp32s3/src/sensitive/core_1_vecbase_override_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_VECBASE_OVERRIDE_0")
             .field(
                 "core_1_vecbase_world_mask",
-                &format_args!("{}", self.core_1_vecbase_world_mask().bit()),
+                &self.core_1_vecbase_world_mask(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_VECBASE_OVERRIDE_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to mask world, then only world0_value will work."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_vecbase_override_1.rs b/esp32s3/src/sensitive/core_1_vecbase_override_1.rs
index b0fc23bdb5..6770465cd0 100644
--- a/esp32s3/src/sensitive/core_1_vecbase_override_1.rs
+++ b/esp32s3/src/sensitive/core_1_vecbase_override_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_VECBASE_OVERRIDE_1")
             .field(
                 "core_1_vecbase_override_world0_value",
-                &format_args!("{}", self.core_1_vecbase_override_world0_value().bits()),
+                &self.core_1_vecbase_override_world0_value(),
             )
             .field(
                 "core_1_vecbase_override_sel",
-                &format_args!("{}", self.core_1_vecbase_override_sel().bits()),
+                &self.core_1_vecbase_override_sel(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_VECBASE_OVERRIDE_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - world0 vecbase_override register, when core1 in world0 use this register to override vecbase register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_vecbase_override_2.rs b/esp32s3/src/sensitive/core_1_vecbase_override_2.rs
index 099df30c42..93d8d1515f 100644
--- a/esp32s3/src/sensitive/core_1_vecbase_override_2.rs
+++ b/esp32s3/src/sensitive/core_1_vecbase_override_2.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_VECBASE_OVERRIDE_2")
             .field(
                 "core_1_vecbase_override_world1_value",
-                &format_args!("{}", self.core_1_vecbase_override_world1_value().bits()),
+                &self.core_1_vecbase_override_world1_value(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_VECBASE_OVERRIDE_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - world1 vecbase_override register, when core1 in world1 use this register to override vecbase register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_1_vecbase_override_lock.rs b/esp32s3/src/sensitive/core_1_vecbase_override_lock.rs
index 340dc0563c..b1fbb72ea3 100644
--- a/esp32s3/src/sensitive/core_1_vecbase_override_lock.rs
+++ b/esp32s3/src/sensitive/core_1_vecbase_override_lock.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_1_VECBASE_OVERRIDE_LOCK")
             .field(
                 "core_1_vecbase_override_lock",
-                &format_args!("{}", self.core_1_vecbase_override_lock().bit()),
+                &self.core_1_vecbase_override_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_VECBASE_OVERRIDE_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock core1 vecbase configuration register"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_x_dram0_pms_constrain_0.rs b/esp32s3/src/sensitive/core_x_dram0_pms_constrain_0.rs
index deacc7d090..9eadd75f7d 100644
--- a/esp32s3/src/sensitive/core_x_dram0_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/core_x_dram0_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_DRAM0_PMS_CONSTRAIN_0")
             .field(
                 "core_x_dram0_pms_constrain_lock",
-                &format_args!("{}", self.core_x_dram0_pms_constrain_lock().bit()),
+                &self.core_x_dram0_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_DRAM0_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock corex dram0 permission configuration register"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_x_dram0_pms_constrain_1.rs b/esp32s3/src/sensitive/core_x_dram0_pms_constrain_1.rs
index fe2324e01a..9b9c0f7af3 100644
--- a/esp32s3/src/sensitive/core_x_dram0_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/core_x_dram0_pms_constrain_1.rs
@@ -176,115 +176,63 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_DRAM0_PMS_CONSTRAIN_1")
             .field(
                 "core_x_dram0_pms_constrain_sram_world_0_pms_0",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_0_pms_0().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_0_pms_0(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_0_pms_1",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_0_pms_1().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_0_pms_1(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_0_pms_2",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_0_pms_2().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_0_pms_2(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_0_pms_3",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_0_pms_3().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_0_pms_3(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_0(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_1(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_1_pms_0",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_1_pms_0().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_1_pms_0(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_1_pms_1",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_1_pms_1().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_1_pms_1(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_1_pms_2",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_1_pms_2().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_1_pms_2(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_1_pms_3",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_1_pms_3().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_1_pms_3(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_0(),
             )
             .field(
                 "core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_1(),
             )
             .field(
                 "core_x_dram0_pms_constrain_rom_world_0_pms",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_rom_world_0_pms().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_rom_world_0_pms(),
             )
             .field(
                 "core_x_dram0_pms_constrain_rom_world_1_pms",
-                &format_args!(
-                    "{}",
-                    self.core_x_dram0_pms_constrain_rom_world_1_pms().bits()
-                ),
+                &self.core_x_dram0_pms_constrain_rom_world_1_pms(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_DRAM0_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - core0/core1's permission of data region0 of SRAM in world0."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_0.rs b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_0.rs
index c3740314ae..2a657d8cf8 100644
--- a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_0.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_0.rs
@@ -21,21 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0")
             .field(
                 "core_x_iram0_dram0_dma_split_line_constrain_lock",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_dram0_dma_split_line_constrain_lock()
-                        .bit()
-                ),
+                &self.core_x_iram0_dram0_dma_split_line_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock sram split configuration register"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_1.rs b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_1.rs
index addc05cbcb..e4f8bf2e6f 100644
--- a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_1.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_1.rs
@@ -96,45 +96,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1")
             .field(
                 "core_x_iram0_dram0_dma_sram_category_0",
-                &format_args!("{}", self.core_x_iram0_dram0_dma_sram_category_0().bits()),
+                &self.core_x_iram0_dram0_dma_sram_category_0(),
             )
             .field(
                 "core_x_iram0_dram0_dma_sram_category_1",
-                &format_args!("{}", self.core_x_iram0_dram0_dma_sram_category_1().bits()),
+                &self.core_x_iram0_dram0_dma_sram_category_1(),
             )
             .field(
                 "core_x_iram0_dram0_dma_sram_category_2",
-                &format_args!("{}", self.core_x_iram0_dram0_dma_sram_category_2().bits()),
+                &self.core_x_iram0_dram0_dma_sram_category_2(),
             )
             .field(
                 "core_x_iram0_dram0_dma_sram_category_3",
-                &format_args!("{}", self.core_x_iram0_dram0_dma_sram_category_3().bits()),
+                &self.core_x_iram0_dram0_dma_sram_category_3(),
             )
             .field(
                 "core_x_iram0_dram0_dma_sram_category_4",
-                &format_args!("{}", self.core_x_iram0_dram0_dma_sram_category_4().bits()),
+                &self.core_x_iram0_dram0_dma_sram_category_4(),
             )
             .field(
                 "core_x_iram0_dram0_dma_sram_category_5",
-                &format_args!("{}", self.core_x_iram0_dram0_dma_sram_category_5().bits()),
+                &self.core_x_iram0_dram0_dma_sram_category_5(),
             )
             .field(
                 "core_x_iram0_dram0_dma_sram_category_6",
-                &format_args!("{}", self.core_x_iram0_dram0_dma_sram_category_6().bits()),
+                &self.core_x_iram0_dram0_dma_sram_category_6(),
             )
             .field(
                 "core_x_iram0_dram0_dma_sram_splitaddr",
-                &format_args!("{}", self.core_x_iram0_dram0_dma_sram_splitaddr().bits()),
+                &self.core_x_iram0_dram0_dma_sram_splitaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_2.rs b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_2.rs
index f60b775c76..7abbbad313 100644
--- a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_2.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_2.rs
@@ -82,45 +82,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2")
             .field(
                 "core_x_iram0_sram_line_0_category_0",
-                &format_args!("{}", self.core_x_iram0_sram_line_0_category_0().bits()),
+                &self.core_x_iram0_sram_line_0_category_0(),
             )
             .field(
                 "core_x_iram0_sram_line_0_category_1",
-                &format_args!("{}", self.core_x_iram0_sram_line_0_category_1().bits()),
+                &self.core_x_iram0_sram_line_0_category_1(),
             )
             .field(
                 "core_x_iram0_sram_line_0_category_2",
-                &format_args!("{}", self.core_x_iram0_sram_line_0_category_2().bits()),
+                &self.core_x_iram0_sram_line_0_category_2(),
             )
             .field(
                 "core_x_iram0_sram_line_0_category_3",
-                &format_args!("{}", self.core_x_iram0_sram_line_0_category_3().bits()),
+                &self.core_x_iram0_sram_line_0_category_3(),
             )
             .field(
                 "core_x_iram0_sram_line_0_category_4",
-                &format_args!("{}", self.core_x_iram0_sram_line_0_category_4().bits()),
+                &self.core_x_iram0_sram_line_0_category_4(),
             )
             .field(
                 "core_x_iram0_sram_line_0_category_5",
-                &format_args!("{}", self.core_x_iram0_sram_line_0_category_5().bits()),
+                &self.core_x_iram0_sram_line_0_category_5(),
             )
             .field(
                 "core_x_iram0_sram_line_0_category_6",
-                &format_args!("{}", self.core_x_iram0_sram_line_0_category_6().bits()),
+                &self.core_x_iram0_sram_line_0_category_6(),
             )
             .field(
                 "core_x_iram0_sram_line_0_splitaddr",
-                &format_args!("{}", self.core_x_iram0_sram_line_0_splitaddr().bits()),
+                &self.core_x_iram0_sram_line_0_splitaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_3.rs b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_3.rs
index c47e203d1c..6538f97c04 100644
--- a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_3.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_3.rs
@@ -82,45 +82,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3")
             .field(
                 "core_x_iram0_sram_line_1_category_0",
-                &format_args!("{}", self.core_x_iram0_sram_line_1_category_0().bits()),
+                &self.core_x_iram0_sram_line_1_category_0(),
             )
             .field(
                 "core_x_iram0_sram_line_1_category_1",
-                &format_args!("{}", self.core_x_iram0_sram_line_1_category_1().bits()),
+                &self.core_x_iram0_sram_line_1_category_1(),
             )
             .field(
                 "core_x_iram0_sram_line_1_category_2",
-                &format_args!("{}", self.core_x_iram0_sram_line_1_category_2().bits()),
+                &self.core_x_iram0_sram_line_1_category_2(),
             )
             .field(
                 "core_x_iram0_sram_line_1_category_3",
-                &format_args!("{}", self.core_x_iram0_sram_line_1_category_3().bits()),
+                &self.core_x_iram0_sram_line_1_category_3(),
             )
             .field(
                 "core_x_iram0_sram_line_1_category_4",
-                &format_args!("{}", self.core_x_iram0_sram_line_1_category_4().bits()),
+                &self.core_x_iram0_sram_line_1_category_4(),
             )
             .field(
                 "core_x_iram0_sram_line_1_category_5",
-                &format_args!("{}", self.core_x_iram0_sram_line_1_category_5().bits()),
+                &self.core_x_iram0_sram_line_1_category_5(),
             )
             .field(
                 "core_x_iram0_sram_line_1_category_6",
-                &format_args!("{}", self.core_x_iram0_sram_line_1_category_6().bits()),
+                &self.core_x_iram0_sram_line_1_category_6(),
             )
             .field(
                 "core_x_iram0_sram_line_1_splitaddr",
-                &format_args!("{}", self.core_x_iram0_sram_line_1_splitaddr().bits()),
+                &self.core_x_iram0_sram_line_1_splitaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_4.rs b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_4.rs
index 3e5a3559cf..ddaf4b6f01 100644
--- a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_4.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_4.rs
@@ -98,45 +98,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4")
             .field(
                 "core_x_dram0_dma_sram_line_0_category_0",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_0_category_0().bits()),
+                &self.core_x_dram0_dma_sram_line_0_category_0(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_0_category_1",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_0_category_1().bits()),
+                &self.core_x_dram0_dma_sram_line_0_category_1(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_0_category_2",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_0_category_2().bits()),
+                &self.core_x_dram0_dma_sram_line_0_category_2(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_0_category_3",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_0_category_3().bits()),
+                &self.core_x_dram0_dma_sram_line_0_category_3(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_0_category_4",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_0_category_4().bits()),
+                &self.core_x_dram0_dma_sram_line_0_category_4(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_0_category_5",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_0_category_5().bits()),
+                &self.core_x_dram0_dma_sram_line_0_category_5(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_0_category_6",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_0_category_6().bits()),
+                &self.core_x_dram0_dma_sram_line_0_category_6(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_0_splitaddr",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_0_splitaddr().bits()),
+                &self.core_x_dram0_dma_sram_line_0_splitaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_5.rs b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_5.rs
index 6a4378b5e7..21d9104c77 100644
--- a/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_5.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_dram0_dma_split_line_constrain_5.rs
@@ -98,45 +98,39 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5")
             .field(
                 "core_x_dram0_dma_sram_line_1_category_0",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_1_category_0().bits()),
+                &self.core_x_dram0_dma_sram_line_1_category_0(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_1_category_1",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_1_category_1().bits()),
+                &self.core_x_dram0_dma_sram_line_1_category_1(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_1_category_2",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_1_category_2().bits()),
+                &self.core_x_dram0_dma_sram_line_1_category_2(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_1_category_3",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_1_category_3().bits()),
+                &self.core_x_dram0_dma_sram_line_1_category_3(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_1_category_4",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_1_category_4().bits()),
+                &self.core_x_dram0_dma_sram_line_1_category_4(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_1_category_5",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_1_category_5().bits()),
+                &self.core_x_dram0_dma_sram_line_1_category_5(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_1_category_6",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_1_category_6().bits()),
+                &self.core_x_dram0_dma_sram_line_1_category_6(),
             )
             .field(
                 "core_x_dram0_dma_sram_line_1_splitaddr",
-                &format_args!("{}", self.core_x_dram0_dma_sram_line_1_splitaddr().bits()),
+                &self.core_x_dram0_dma_sram_line_1_splitaddr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_x_iram0_pms_constrain_0.rs b/esp32s3/src/sensitive/core_x_iram0_pms_constrain_0.rs
index 965a24decb..13fc13bc2b 100644
--- a/esp32s3/src/sensitive/core_x_iram0_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_PMS_CONSTRAIN_0")
             .field(
                 "core_x_iram0_pms_constrain_lock",
-                &format_args!("{}", self.core_x_iram0_pms_constrain_lock().bit()),
+                &self.core_x_iram0_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock corex iram0 permission configuration register"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_x_iram0_pms_constrain_1.rs b/esp32s3/src/sensitive/core_x_iram0_pms_constrain_1.rs
index fa31f3fcf6..0da7e5c463 100644
--- a/esp32s3/src/sensitive/core_x_iram0_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_pms_constrain_1.rs
@@ -93,64 +93,35 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_PMS_CONSTRAIN_1")
             .field(
                 "core_x_iram0_pms_constrain_sram_world_1_pms_0",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_1_pms_0().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_1_pms_0(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_1_pms_1",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_1_pms_1().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_1_pms_1(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_1_pms_2",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_1_pms_2().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_1_pms_2(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_1_pms_3",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_1_pms_3().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_1_pms_3(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_1(),
             )
             .field(
                 "core_x_iram0_pms_constrain_rom_world_1_pms",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_rom_world_1_pms().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_rom_world_1_pms(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - core0/core1's permission of instruction region0 of SRAM in world1"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/core_x_iram0_pms_constrain_2.rs b/esp32s3/src/sensitive/core_x_iram0_pms_constrain_2.rs
index 8d485e7623..7bdc71037e 100644
--- a/esp32s3/src/sensitive/core_x_iram0_pms_constrain_2.rs
+++ b/esp32s3/src/sensitive/core_x_iram0_pms_constrain_2.rs
@@ -93,64 +93,35 @@ impl core::fmt::Debug for R {
         f.debug_struct("CORE_X_IRAM0_PMS_CONSTRAIN_2")
             .field(
                 "core_x_iram0_pms_constrain_sram_world_0_pms_0",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_0_pms_0().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_0_pms_0(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_0_pms_1",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_0_pms_1().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_0_pms_1(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_0_pms_2",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_0_pms_2().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_0_pms_2(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_0_pms_3",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_0_pms_3().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_0_pms_3(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0(),
             )
             .field(
                 "core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_1(),
             )
             .field(
                 "core_x_iram0_pms_constrain_rom_world_0_pms",
-                &format_args!(
-                    "{}",
-                    self.core_x_iram0_pms_constrain_rom_world_0_pms().bits()
-                ),
+                &self.core_x_iram0_pms_constrain_rom_world_0_pms(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_X_IRAM0_PMS_CONSTRAIN_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - core0/core1's permission of instruction region0 of SRAM in world1"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/date.rs b/esp32s3/src/sensitive/date.rs
index 487c77966f..0965fe5b9b 100644
--- a/esp32s3/src/sensitive/date.rs
+++ b/esp32s3/src/sensitive/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_0.rs
index 3c9172eaeb..1f47cb8445 100644
--- a/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_0.rs
@@ -21,17 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_adc_dac_pms_constrain_lock().bit()),
+                &self.dma_apbperi_adc_dac_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock adc_dac dma permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_1.rs
index bf7f980a7b..7b63d22d58 100644
--- a/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_adc_dac_pms_constrain_1.rs
@@ -82,57 +82,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_sram_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_adc_dac_pms_constrain_sram_pms_0().bits()
-                ),
+                &self.dma_apbperi_adc_dac_pms_constrain_sram_pms_0(),
             )
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_sram_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_adc_dac_pms_constrain_sram_pms_1().bits()
-                ),
+                &self.dma_apbperi_adc_dac_pms_constrain_sram_pms_1(),
             )
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_sram_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_adc_dac_pms_constrain_sram_pms_2().bits()
-                ),
+                &self.dma_apbperi_adc_dac_pms_constrain_sram_pms_2(),
             )
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_sram_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_adc_dac_pms_constrain_sram_pms_3().bits()
-                ),
+                &self.dma_apbperi_adc_dac_pms_constrain_sram_pms_3(),
             )
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_sram_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_adc_dac_pms_constrain_sram_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_adc_dac_pms_constrain_sram_cachedataarray_pms_0(),
             )
             .field(
                 "dma_apbperi_adc_dac_pms_constrain_sram_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_adc_dac_pms_constrain_sram_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_adc_dac_pms_constrain_sram_cachedataarray_pms_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - adc_dac's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_0.rs
index cafcc90165..0ed037eba0 100644
--- a/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_AES_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_aes_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_aes_pms_constrain_lock().bit()),
+                &self.dma_apbperi_aes_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_AES_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock aes dma permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_1.rs
index eabf6a5a07..ded02997e1 100644
--- a/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_aes_pms_constrain_1.rs
@@ -80,45 +80,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_AES_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_aes_pms_constrain_sram_pms_0",
-                &format_args!("{}", self.dma_apbperi_aes_pms_constrain_sram_pms_0().bits()),
+                &self.dma_apbperi_aes_pms_constrain_sram_pms_0(),
             )
             .field(
                 "dma_apbperi_aes_pms_constrain_sram_pms_1",
-                &format_args!("{}", self.dma_apbperi_aes_pms_constrain_sram_pms_1().bits()),
+                &self.dma_apbperi_aes_pms_constrain_sram_pms_1(),
             )
             .field(
                 "dma_apbperi_aes_pms_constrain_sram_pms_2",
-                &format_args!("{}", self.dma_apbperi_aes_pms_constrain_sram_pms_2().bits()),
+                &self.dma_apbperi_aes_pms_constrain_sram_pms_2(),
             )
             .field(
                 "dma_apbperi_aes_pms_constrain_sram_pms_3",
-                &format_args!("{}", self.dma_apbperi_aes_pms_constrain_sram_pms_3().bits()),
+                &self.dma_apbperi_aes_pms_constrain_sram_pms_3(),
             )
             .field(
                 "dma_apbperi_aes_pms_constrain_sram_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_aes_pms_constrain_sram_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_aes_pms_constrain_sram_cachedataarray_pms_0(),
             )
             .field(
                 "dma_apbperi_aes_pms_constrain_sram_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_aes_pms_constrain_sram_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_aes_pms_constrain_sram_cachedataarray_pms_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_AES_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - aes's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_0.rs
index a724d23d08..8c4a7a9b99 100644
--- a/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_backup_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_backup_pms_constrain_lock().bit()),
+                &self.dma_apbperi_backup_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock backup dma permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_1.rs
index da400c1baf..4e7e1dc8d7 100644
--- a/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_backup_pms_constrain_1.rs
@@ -82,57 +82,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_backup_pms_constrain_sram_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_backup_pms_constrain_sram_pms_0().bits()
-                ),
+                &self.dma_apbperi_backup_pms_constrain_sram_pms_0(),
             )
             .field(
                 "dma_apbperi_backup_pms_constrain_sram_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_backup_pms_constrain_sram_pms_1().bits()
-                ),
+                &self.dma_apbperi_backup_pms_constrain_sram_pms_1(),
             )
             .field(
                 "dma_apbperi_backup_pms_constrain_sram_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_backup_pms_constrain_sram_pms_2().bits()
-                ),
+                &self.dma_apbperi_backup_pms_constrain_sram_pms_2(),
             )
             .field(
                 "dma_apbperi_backup_pms_constrain_sram_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_backup_pms_constrain_sram_pms_3().bits()
-                ),
+                &self.dma_apbperi_backup_pms_constrain_sram_pms_3(),
             )
             .field(
                 "dma_apbperi_backup_pms_constrain_sram_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_backup_pms_constrain_sram_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_backup_pms_constrain_sram_cachedataarray_pms_0(),
             )
             .field(
                 "dma_apbperi_backup_pms_constrain_sram_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_backup_pms_constrain_sram_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_backup_pms_constrain_sram_cachedataarray_pms_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - backup's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_0.rs
index d30679926d..2e5487d055 100644
--- a/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_I2S0_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_i2s0_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_i2s0_pms_constrain_lock().bit()),
+                &self.dma_apbperi_i2s0_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock i2s0 dma permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_1.rs
index 88ae699c24..9c26784572 100644
--- a/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_i2s0_pms_constrain_1.rs
@@ -82,57 +82,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_I2S0_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_i2s0_pms_constrain_sram_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s0_pms_constrain_sram_pms_0().bits()
-                ),
+                &self.dma_apbperi_i2s0_pms_constrain_sram_pms_0(),
             )
             .field(
                 "dma_apbperi_i2s0_pms_constrain_sram_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s0_pms_constrain_sram_pms_1().bits()
-                ),
+                &self.dma_apbperi_i2s0_pms_constrain_sram_pms_1(),
             )
             .field(
                 "dma_apbperi_i2s0_pms_constrain_sram_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s0_pms_constrain_sram_pms_2().bits()
-                ),
+                &self.dma_apbperi_i2s0_pms_constrain_sram_pms_2(),
             )
             .field(
                 "dma_apbperi_i2s0_pms_constrain_sram_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s0_pms_constrain_sram_pms_3().bits()
-                ),
+                &self.dma_apbperi_i2s0_pms_constrain_sram_pms_3(),
             )
             .field(
                 "dma_apbperi_i2s0_pms_constrain_sram_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s0_pms_constrain_sram_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_i2s0_pms_constrain_sram_cachedataarray_pms_0(),
             )
             .field(
                 "dma_apbperi_i2s0_pms_constrain_sram_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s0_pms_constrain_sram_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_i2s0_pms_constrain_sram_cachedataarray_pms_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - i2s0's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_0.rs
index f98ad0761d..5ccfe3c89c 100644
--- a/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_I2S1_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_i2s1_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_i2s1_pms_constrain_lock().bit()),
+                &self.dma_apbperi_i2s1_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_I2S1_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock i2s1 dma permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_1.rs
index 37010fe486..6a596776ed 100644
--- a/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_i2s1_pms_constrain_1.rs
@@ -82,57 +82,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_I2S1_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_i2s1_pms_constrain_sram_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s1_pms_constrain_sram_pms_0().bits()
-                ),
+                &self.dma_apbperi_i2s1_pms_constrain_sram_pms_0(),
             )
             .field(
                 "dma_apbperi_i2s1_pms_constrain_sram_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s1_pms_constrain_sram_pms_1().bits()
-                ),
+                &self.dma_apbperi_i2s1_pms_constrain_sram_pms_1(),
             )
             .field(
                 "dma_apbperi_i2s1_pms_constrain_sram_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s1_pms_constrain_sram_pms_2().bits()
-                ),
+                &self.dma_apbperi_i2s1_pms_constrain_sram_pms_2(),
             )
             .field(
                 "dma_apbperi_i2s1_pms_constrain_sram_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s1_pms_constrain_sram_pms_3().bits()
-                ),
+                &self.dma_apbperi_i2s1_pms_constrain_sram_pms_3(),
             )
             .field(
                 "dma_apbperi_i2s1_pms_constrain_sram_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s1_pms_constrain_sram_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_i2s1_pms_constrain_sram_cachedataarray_pms_0(),
             )
             .field(
                 "dma_apbperi_i2s1_pms_constrain_sram_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_i2s1_pms_constrain_sram_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_i2s1_pms_constrain_sram_cachedataarray_pms_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - i2s1's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_0.rs
index a06706adab..e9324153c1 100644
--- a/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_LC_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_lc_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_lc_pms_constrain_lock().bit()),
+                &self.dma_apbperi_lc_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_LC_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock lc dma permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_1.rs
index 782fccb5ea..71d5f6a2ff 100644
--- a/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_lc_pms_constrain_1.rs
@@ -78,45 +78,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_LC_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_lc_pms_constrain_sram_pms_0",
-                &format_args!("{}", self.dma_apbperi_lc_pms_constrain_sram_pms_0().bits()),
+                &self.dma_apbperi_lc_pms_constrain_sram_pms_0(),
             )
             .field(
                 "dma_apbperi_lc_pms_constrain_sram_pms_1",
-                &format_args!("{}", self.dma_apbperi_lc_pms_constrain_sram_pms_1().bits()),
+                &self.dma_apbperi_lc_pms_constrain_sram_pms_1(),
             )
             .field(
                 "dma_apbperi_lc_pms_constrain_sram_pms_2",
-                &format_args!("{}", self.dma_apbperi_lc_pms_constrain_sram_pms_2().bits()),
+                &self.dma_apbperi_lc_pms_constrain_sram_pms_2(),
             )
             .field(
                 "dma_apbperi_lc_pms_constrain_sram_pms_3",
-                &format_args!("{}", self.dma_apbperi_lc_pms_constrain_sram_pms_3().bits()),
+                &self.dma_apbperi_lc_pms_constrain_sram_pms_3(),
             )
             .field(
                 "dma_apbperi_lc_pms_constrain_sram_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lc_pms_constrain_sram_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_lc_pms_constrain_sram_cachedataarray_pms_0(),
             )
             .field(
                 "dma_apbperi_lc_pms_constrain_sram_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lc_pms_constrain_sram_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_lc_pms_constrain_sram_cachedataarray_pms_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_LC_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - lc's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_0.rs
index 0862e16b08..75f73a2a80 100644
--- a/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_0.rs
@@ -21,17 +21,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_lcd_cam_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_lcd_cam_pms_constrain_lock().bit()),
+                &self.dma_apbperi_lcd_cam_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock lcd_cam dma permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_1.rs
index 0cf1ec98dc..0992c9ac2b 100644
--- a/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_lcd_cam_pms_constrain_1.rs
@@ -82,57 +82,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_lcd_cam_pms_constrain_sram_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lcd_cam_pms_constrain_sram_pms_0().bits()
-                ),
+                &self.dma_apbperi_lcd_cam_pms_constrain_sram_pms_0(),
             )
             .field(
                 "dma_apbperi_lcd_cam_pms_constrain_sram_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lcd_cam_pms_constrain_sram_pms_1().bits()
-                ),
+                &self.dma_apbperi_lcd_cam_pms_constrain_sram_pms_1(),
             )
             .field(
                 "dma_apbperi_lcd_cam_pms_constrain_sram_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lcd_cam_pms_constrain_sram_pms_2().bits()
-                ),
+                &self.dma_apbperi_lcd_cam_pms_constrain_sram_pms_2(),
             )
             .field(
                 "dma_apbperi_lcd_cam_pms_constrain_sram_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lcd_cam_pms_constrain_sram_pms_3().bits()
-                ),
+                &self.dma_apbperi_lcd_cam_pms_constrain_sram_pms_3(),
             )
             .field(
                 "dma_apbperi_lcd_cam_pms_constrain_sram_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lcd_cam_pms_constrain_sram_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_lcd_cam_pms_constrain_sram_cachedataarray_pms_0(),
             )
             .field(
                 "dma_apbperi_lcd_cam_pms_constrain_sram_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_lcd_cam_pms_constrain_sram_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_lcd_cam_pms_constrain_sram_cachedataarray_pms_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - lcd_cam's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_0.rs
index 659a9cb79a..11d563eedc 100644
--- a/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_MAC_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_mac_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_mac_pms_constrain_lock().bit()),
+                &self.dma_apbperi_mac_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_MAC_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock mac dma permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_1.rs
index 6241faa8fd..588fdcb19d 100644
--- a/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_mac_pms_constrain_1.rs
@@ -80,45 +80,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_MAC_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_mac_pms_constrain_sram_pms_0",
-                &format_args!("{}", self.dma_apbperi_mac_pms_constrain_sram_pms_0().bits()),
+                &self.dma_apbperi_mac_pms_constrain_sram_pms_0(),
             )
             .field(
                 "dma_apbperi_mac_pms_constrain_sram_pms_1",
-                &format_args!("{}", self.dma_apbperi_mac_pms_constrain_sram_pms_1().bits()),
+                &self.dma_apbperi_mac_pms_constrain_sram_pms_1(),
             )
             .field(
                 "dma_apbperi_mac_pms_constrain_sram_pms_2",
-                &format_args!("{}", self.dma_apbperi_mac_pms_constrain_sram_pms_2().bits()),
+                &self.dma_apbperi_mac_pms_constrain_sram_pms_2(),
             )
             .field(
                 "dma_apbperi_mac_pms_constrain_sram_pms_3",
-                &format_args!("{}", self.dma_apbperi_mac_pms_constrain_sram_pms_3().bits()),
+                &self.dma_apbperi_mac_pms_constrain_sram_pms_3(),
             )
             .field(
                 "dma_apbperi_mac_pms_constrain_sram_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_mac_pms_constrain_sram_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_mac_pms_constrain_sram_cachedataarray_pms_0(),
             )
             .field(
                 "dma_apbperi_mac_pms_constrain_sram_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_mac_pms_constrain_sram_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_mac_pms_constrain_sram_cachedataarray_pms_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_MAC_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - mac's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_pms_monitor_0.rs b/esp32s3/src/sensitive/dma_apbperi_pms_monitor_0.rs
index 80d969cd34..bb0878a80b 100644
--- a/esp32s3/src/sensitive/dma_apbperi_pms_monitor_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_pms_monitor_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_PMS_MONITOR_0")
             .field(
                 "dma_apbperi_pms_monitor_lock",
-                &format_args!("{}", self.dma_apbperi_pms_monitor_lock().bit()),
+                &self.dma_apbperi_pms_monitor_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_PMS_MONITOR_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock dma permission monitor Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_pms_monitor_1.rs b/esp32s3/src/sensitive/dma_apbperi_pms_monitor_1.rs
index de183983a6..9101e02e01 100644
--- a/esp32s3/src/sensitive/dma_apbperi_pms_monitor_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_pms_monitor_1.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_PMS_MONITOR_1")
             .field(
                 "dma_apbperi_pms_monitor_violate_clr",
-                &format_args!("{}", self.dma_apbperi_pms_monitor_violate_clr().bit()),
+                &self.dma_apbperi_pms_monitor_violate_clr(),
             )
             .field(
                 "dma_apbperi_pms_monitor_violate_en",
-                &format_args!("{}", self.dma_apbperi_pms_monitor_violate_en().bit()),
+                &self.dma_apbperi_pms_monitor_violate_en(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_PMS_MONITOR_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to clear dma_pms_monitor_violate interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_pms_monitor_2.rs b/esp32s3/src/sensitive/dma_apbperi_pms_monitor_2.rs
index 718b370d71..fc4bb17df8 100644
--- a/esp32s3/src/sensitive/dma_apbperi_pms_monitor_2.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_pms_monitor_2.rs
@@ -33,31 +33,19 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_PMS_MONITOR_2")
             .field(
                 "dma_apbperi_pms_monitor_violate_intr",
-                &format_args!("{}", self.dma_apbperi_pms_monitor_violate_intr().bit()),
+                &self.dma_apbperi_pms_monitor_violate_intr(),
             )
             .field(
                 "dma_apbperi_pms_monitor_violate_status_world",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_pms_monitor_violate_status_world().bits()
-                ),
+                &self.dma_apbperi_pms_monitor_violate_status_world(),
             )
             .field(
                 "dma_apbperi_pms_monitor_violate_status_addr",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_pms_monitor_violate_status_addr().bits()
-                ),
+                &self.dma_apbperi_pms_monitor_violate_status_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_PMS_MONITOR_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "dma permission monitor configuration register 2.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_apbperi_pms_monitor_2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_APBPERI_PMS_MONITOR_2_SPEC;
 impl crate::RegisterSpec for DMA_APBPERI_PMS_MONITOR_2_SPEC {
diff --git a/esp32s3/src/sensitive/dma_apbperi_pms_monitor_3.rs b/esp32s3/src/sensitive/dma_apbperi_pms_monitor_3.rs
index 3da946ac3a..8f0271b4a0 100644
--- a/esp32s3/src/sensitive/dma_apbperi_pms_monitor_3.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_pms_monitor_3.rs
@@ -26,24 +26,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_PMS_MONITOR_3")
             .field(
                 "dma_apbperi_pms_monitor_violate_status_wr",
-                &format_args!("{}", self.dma_apbperi_pms_monitor_violate_status_wr().bit()),
+                &self.dma_apbperi_pms_monitor_violate_status_wr(),
             )
             .field(
                 "dma_apbperi_pms_monitor_violate_status_byteen",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_pms_monitor_violate_status_byteen().bits()
-                ),
+                &self.dma_apbperi_pms_monitor_violate_status_byteen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_PMS_MONITOR_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "dma permission monitor configuration register 3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_apbperi_pms_monitor_3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_APBPERI_PMS_MONITOR_3_SPEC;
 impl crate::RegisterSpec for DMA_APBPERI_PMS_MONITOR_3_SPEC {
diff --git a/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_0.rs
index eb0fea3b29..036ba091c6 100644
--- a/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_RMT_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_rmt_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_rmt_pms_constrain_lock().bit()),
+                &self.dma_apbperi_rmt_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_RMT_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock rmt dma permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_1.rs
index a82ae4a695..0ea7747b20 100644
--- a/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_rmt_pms_constrain_1.rs
@@ -80,45 +80,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_RMT_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_rmt_pms_constrain_sram_pms_0",
-                &format_args!("{}", self.dma_apbperi_rmt_pms_constrain_sram_pms_0().bits()),
+                &self.dma_apbperi_rmt_pms_constrain_sram_pms_0(),
             )
             .field(
                 "dma_apbperi_rmt_pms_constrain_sram_pms_1",
-                &format_args!("{}", self.dma_apbperi_rmt_pms_constrain_sram_pms_1().bits()),
+                &self.dma_apbperi_rmt_pms_constrain_sram_pms_1(),
             )
             .field(
                 "dma_apbperi_rmt_pms_constrain_sram_pms_2",
-                &format_args!("{}", self.dma_apbperi_rmt_pms_constrain_sram_pms_2().bits()),
+                &self.dma_apbperi_rmt_pms_constrain_sram_pms_2(),
             )
             .field(
                 "dma_apbperi_rmt_pms_constrain_sram_pms_3",
-                &format_args!("{}", self.dma_apbperi_rmt_pms_constrain_sram_pms_3().bits()),
+                &self.dma_apbperi_rmt_pms_constrain_sram_pms_3(),
             )
             .field(
                 "dma_apbperi_rmt_pms_constrain_sram_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_rmt_pms_constrain_sram_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_rmt_pms_constrain_sram_cachedataarray_pms_0(),
             )
             .field(
                 "dma_apbperi_rmt_pms_constrain_sram_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_rmt_pms_constrain_sram_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_rmt_pms_constrain_sram_cachedataarray_pms_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_RMT_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - rmt's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_0.rs
index b9ef349b4c..49a22cb17d 100644
--- a/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_SDIO_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_sdio_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_sdio_pms_constrain_lock().bit()),
+                &self.dma_apbperi_sdio_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_SDIO_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock sdio dma permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_1.rs
index d1ca799fd4..06feeb70e7 100644
--- a/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_sdio_pms_constrain_1.rs
@@ -82,57 +82,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_SDIO_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_sdio_pms_constrain_sram_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sdio_pms_constrain_sram_pms_0().bits()
-                ),
+                &self.dma_apbperi_sdio_pms_constrain_sram_pms_0(),
             )
             .field(
                 "dma_apbperi_sdio_pms_constrain_sram_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sdio_pms_constrain_sram_pms_1().bits()
-                ),
+                &self.dma_apbperi_sdio_pms_constrain_sram_pms_1(),
             )
             .field(
                 "dma_apbperi_sdio_pms_constrain_sram_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sdio_pms_constrain_sram_pms_2().bits()
-                ),
+                &self.dma_apbperi_sdio_pms_constrain_sram_pms_2(),
             )
             .field(
                 "dma_apbperi_sdio_pms_constrain_sram_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sdio_pms_constrain_sram_pms_3().bits()
-                ),
+                &self.dma_apbperi_sdio_pms_constrain_sram_pms_3(),
             )
             .field(
                 "dma_apbperi_sdio_pms_constrain_sram_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sdio_pms_constrain_sram_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_sdio_pms_constrain_sram_cachedataarray_pms_0(),
             )
             .field(
                 "dma_apbperi_sdio_pms_constrain_sram_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sdio_pms_constrain_sram_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_sdio_pms_constrain_sram_cachedataarray_pms_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - sdio's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_0.rs
index 1ecb188d2d..cca422d891 100644
--- a/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_SHA_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_sha_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_sha_pms_constrain_lock().bit()),
+                &self.dma_apbperi_sha_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_SHA_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock sha dma permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_1.rs
index 8840da1bbd..76b0901af6 100644
--- a/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_sha_pms_constrain_1.rs
@@ -80,45 +80,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_SHA_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_sha_pms_constrain_sram_pms_0",
-                &format_args!("{}", self.dma_apbperi_sha_pms_constrain_sram_pms_0().bits()),
+                &self.dma_apbperi_sha_pms_constrain_sram_pms_0(),
             )
             .field(
                 "dma_apbperi_sha_pms_constrain_sram_pms_1",
-                &format_args!("{}", self.dma_apbperi_sha_pms_constrain_sram_pms_1().bits()),
+                &self.dma_apbperi_sha_pms_constrain_sram_pms_1(),
             )
             .field(
                 "dma_apbperi_sha_pms_constrain_sram_pms_2",
-                &format_args!("{}", self.dma_apbperi_sha_pms_constrain_sram_pms_2().bits()),
+                &self.dma_apbperi_sha_pms_constrain_sram_pms_2(),
             )
             .field(
                 "dma_apbperi_sha_pms_constrain_sram_pms_3",
-                &format_args!("{}", self.dma_apbperi_sha_pms_constrain_sram_pms_3().bits()),
+                &self.dma_apbperi_sha_pms_constrain_sram_pms_3(),
             )
             .field(
                 "dma_apbperi_sha_pms_constrain_sram_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sha_pms_constrain_sram_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_sha_pms_constrain_sram_cachedataarray_pms_0(),
             )
             .field(
                 "dma_apbperi_sha_pms_constrain_sram_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_sha_pms_constrain_sram_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_sha_pms_constrain_sram_cachedataarray_pms_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_SHA_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - sha's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_0.rs
index 6ffe662baa..fb18a32302 100644
--- a/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_SPI2_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_spi2_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_spi2_pms_constrain_lock().bit()),
+                &self.dma_apbperi_spi2_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock spi2 dma permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_1.rs
index 523603eed0..d16f3d2457 100644
--- a/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_spi2_pms_constrain_1.rs
@@ -82,57 +82,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_SPI2_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_spi2_pms_constrain_sram_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi2_pms_constrain_sram_pms_0().bits()
-                ),
+                &self.dma_apbperi_spi2_pms_constrain_sram_pms_0(),
             )
             .field(
                 "dma_apbperi_spi2_pms_constrain_sram_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi2_pms_constrain_sram_pms_1().bits()
-                ),
+                &self.dma_apbperi_spi2_pms_constrain_sram_pms_1(),
             )
             .field(
                 "dma_apbperi_spi2_pms_constrain_sram_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi2_pms_constrain_sram_pms_2().bits()
-                ),
+                &self.dma_apbperi_spi2_pms_constrain_sram_pms_2(),
             )
             .field(
                 "dma_apbperi_spi2_pms_constrain_sram_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi2_pms_constrain_sram_pms_3().bits()
-                ),
+                &self.dma_apbperi_spi2_pms_constrain_sram_pms_3(),
             )
             .field(
                 "dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_0(),
             )
             .field(
                 "dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - spi2's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_0.rs
index 11bd72bbc6..1e6de88c23 100644
--- a/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_SPI3_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_spi3_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_spi3_pms_constrain_lock().bit()),
+                &self.dma_apbperi_spi3_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_SPI3_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock spi3 dma permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_1.rs
index ca73c8d223..bf0d4890b4 100644
--- a/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_spi3_pms_constrain_1.rs
@@ -82,57 +82,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_SPI3_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_spi3_pms_constrain_sram_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi3_pms_constrain_sram_pms_0().bits()
-                ),
+                &self.dma_apbperi_spi3_pms_constrain_sram_pms_0(),
             )
             .field(
                 "dma_apbperi_spi3_pms_constrain_sram_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi3_pms_constrain_sram_pms_1().bits()
-                ),
+                &self.dma_apbperi_spi3_pms_constrain_sram_pms_1(),
             )
             .field(
                 "dma_apbperi_spi3_pms_constrain_sram_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi3_pms_constrain_sram_pms_2().bits()
-                ),
+                &self.dma_apbperi_spi3_pms_constrain_sram_pms_2(),
             )
             .field(
                 "dma_apbperi_spi3_pms_constrain_sram_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi3_pms_constrain_sram_pms_3().bits()
-                ),
+                &self.dma_apbperi_spi3_pms_constrain_sram_pms_3(),
             )
             .field(
                 "dma_apbperi_spi3_pms_constrain_sram_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi3_pms_constrain_sram_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_spi3_pms_constrain_sram_cachedataarray_pms_0(),
             )
             .field(
                 "dma_apbperi_spi3_pms_constrain_sram_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_spi3_pms_constrain_sram_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_spi3_pms_constrain_sram_cachedataarray_pms_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - spi3's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_0.rs
index 23e3920534..fad856bf36 100644
--- a/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_uhci0_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_uhci0_pms_constrain_lock().bit()),
+                &self.dma_apbperi_uhci0_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock uhci0 dma permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_1.rs
index 92a82d76ed..83042eabe6 100644
--- a/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_uhci0_pms_constrain_1.rs
@@ -82,57 +82,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_uhci0_pms_constrain_sram_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_uhci0_pms_constrain_sram_pms_0().bits()
-                ),
+                &self.dma_apbperi_uhci0_pms_constrain_sram_pms_0(),
             )
             .field(
                 "dma_apbperi_uhci0_pms_constrain_sram_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_uhci0_pms_constrain_sram_pms_1().bits()
-                ),
+                &self.dma_apbperi_uhci0_pms_constrain_sram_pms_1(),
             )
             .field(
                 "dma_apbperi_uhci0_pms_constrain_sram_pms_2",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_uhci0_pms_constrain_sram_pms_2().bits()
-                ),
+                &self.dma_apbperi_uhci0_pms_constrain_sram_pms_2(),
             )
             .field(
                 "dma_apbperi_uhci0_pms_constrain_sram_pms_3",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_uhci0_pms_constrain_sram_pms_3().bits()
-                ),
+                &self.dma_apbperi_uhci0_pms_constrain_sram_pms_3(),
             )
             .field(
                 "dma_apbperi_uhci0_pms_constrain_sram_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_uhci0_pms_constrain_sram_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_uhci0_pms_constrain_sram_cachedataarray_pms_0(),
             )
             .field(
                 "dma_apbperi_uhci0_pms_constrain_sram_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_uhci0_pms_constrain_sram_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_uhci0_pms_constrain_sram_cachedataarray_pms_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - uhci0's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_0.rs b/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_0.rs
index 79aab2079d..326e4c40fc 100644
--- a/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_0.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_0.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_USB_PMS_CONSTRAIN_0")
             .field(
                 "dma_apbperi_usb_pms_constrain_lock",
-                &format_args!("{}", self.dma_apbperi_usb_pms_constrain_lock().bit()),
+                &self.dma_apbperi_usb_pms_constrain_lock(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_USB_PMS_CONSTRAIN_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock usb dma permission Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_1.rs b/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_1.rs
index 8276e0b7c1..98f7341b44 100644
--- a/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_1.rs
+++ b/esp32s3/src/sensitive/dma_apbperi_usb_pms_constrain_1.rs
@@ -80,45 +80,31 @@ impl core::fmt::Debug for R {
         f.debug_struct("DMA_APBPERI_USB_PMS_CONSTRAIN_1")
             .field(
                 "dma_apbperi_usb_pms_constrain_sram_pms_0",
-                &format_args!("{}", self.dma_apbperi_usb_pms_constrain_sram_pms_0().bits()),
+                &self.dma_apbperi_usb_pms_constrain_sram_pms_0(),
             )
             .field(
                 "dma_apbperi_usb_pms_constrain_sram_pms_1",
-                &format_args!("{}", self.dma_apbperi_usb_pms_constrain_sram_pms_1().bits()),
+                &self.dma_apbperi_usb_pms_constrain_sram_pms_1(),
             )
             .field(
                 "dma_apbperi_usb_pms_constrain_sram_pms_2",
-                &format_args!("{}", self.dma_apbperi_usb_pms_constrain_sram_pms_2().bits()),
+                &self.dma_apbperi_usb_pms_constrain_sram_pms_2(),
             )
             .field(
                 "dma_apbperi_usb_pms_constrain_sram_pms_3",
-                &format_args!("{}", self.dma_apbperi_usb_pms_constrain_sram_pms_3().bits()),
+                &self.dma_apbperi_usb_pms_constrain_sram_pms_3(),
             )
             .field(
                 "dma_apbperi_usb_pms_constrain_sram_cachedataarray_pms_0",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_usb_pms_constrain_sram_cachedataarray_pms_0()
-                        .bits()
-                ),
+                &self.dma_apbperi_usb_pms_constrain_sram_cachedataarray_pms_0(),
             )
             .field(
                 "dma_apbperi_usb_pms_constrain_sram_cachedataarray_pms_1",
-                &format_args!(
-                    "{}",
-                    self.dma_apbperi_usb_pms_constrain_sram_cachedataarray_pms_1()
-                        .bits()
-                ),
+                &self.dma_apbperi_usb_pms_constrain_sram_cachedataarray_pms_1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_APBPERI_USB_PMS_CONSTRAIN_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - usb's permission(store,load) in data region0 of SRAM"]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_boundary_0.rs b/esp32s3/src/sensitive/edma_boundary_0.rs
index e0078a32f4..32bd5a5c97 100644
--- a/esp32s3/src/sensitive/edma_boundary_0.rs
+++ b/esp32s3/src/sensitive/edma_boundary_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_BOUNDARY_0")
-            .field(
-                "edma_boundary_0",
-                &format_args!("{}", self.edma_boundary_0().bits()),
-            )
+            .field("edma_boundary_0", &self.edma_boundary_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_BOUNDARY_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This field is used to configure the boundary 0 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K)."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_boundary_1.rs b/esp32s3/src/sensitive/edma_boundary_1.rs
index 0528b0a912..b65f345d09 100644
--- a/esp32s3/src/sensitive/edma_boundary_1.rs
+++ b/esp32s3/src/sensitive/edma_boundary_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_BOUNDARY_1")
-            .field(
-                "edma_boundary_1",
-                &format_args!("{}", self.edma_boundary_1().bits()),
-            )
+            .field("edma_boundary_1", &self.edma_boundary_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_BOUNDARY_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This field is used to configure the boundary 1 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K)."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_boundary_2.rs b/esp32s3/src/sensitive/edma_boundary_2.rs
index d492929e1e..9eb5f334c6 100644
--- a/esp32s3/src/sensitive/edma_boundary_2.rs
+++ b/esp32s3/src/sensitive/edma_boundary_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_BOUNDARY_2")
-            .field(
-                "edma_boundary_2",
-                &format_args!("{}", self.edma_boundary_2().bits()),
-            )
+            .field("edma_boundary_2", &self.edma_boundary_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_BOUNDARY_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - This field is used to configure the boundary 2 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K)."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_boundary_lock.rs b/esp32s3/src/sensitive/edma_boundary_lock.rs
index c4dd0a6cf4..76d17a4e2f 100644
--- a/esp32s3/src/sensitive/edma_boundary_lock.rs
+++ b/esp32s3/src/sensitive/edma_boundary_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_BOUNDARY_LOCK")
-            .field(
-                "edma_boundary_lock",
-                &format_args!("{}", self.edma_boundary_lock().bit()),
-            )
+            .field("edma_boundary_lock", &self.edma_boundary_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_BOUNDARY_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA boundary registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_adc_dac.rs b/esp32s3/src/sensitive/edma_pms_adc_dac.rs
index 2821a37c32..7a6ce5a547 100644
--- a/esp32s3/src/sensitive/edma_pms_adc_dac.rs
+++ b/esp32s3/src/sensitive/edma_pms_adc_dac.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_ADC_DAC")
-            .field("attr1", &format_args!("{}", self.attr1().bits()))
-            .field("attr2", &format_args!("{}", self.attr2().bits()))
+            .field("attr1", &self.attr1())
+            .field("attr2", &self.attr2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_ADC_DAC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_adc_dac_lock.rs b/esp32s3/src/sensitive/edma_pms_adc_dac_lock.rs
index 9bc3b76a29..e5450c0dc4 100644
--- a/esp32s3/src/sensitive/edma_pms_adc_dac_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_adc_dac_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_ADC_DAC_LOCK")
-            .field(
-                "edma_pms_adc_dac_lock",
-                &format_args!("{}", self.edma_pms_adc_dac_lock().bit()),
-            )
+            .field("edma_pms_adc_dac_lock", &self.edma_pms_adc_dac_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_ADC_DAC_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-ADC/DAC permission control registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_aes.rs b/esp32s3/src/sensitive/edma_pms_aes.rs
index 95d0ebd361..8b4e0aa552 100644
--- a/esp32s3/src/sensitive/edma_pms_aes.rs
+++ b/esp32s3/src/sensitive/edma_pms_aes.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_AES")
-            .field("attr1", &format_args!("{}", self.attr1().bits()))
-            .field("attr2", &format_args!("{}", self.attr2().bits()))
+            .field("attr1", &self.attr1())
+            .field("attr2", &self.attr2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_AES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of AES accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_aes_lock.rs b/esp32s3/src/sensitive/edma_pms_aes_lock.rs
index fce84c628d..fedfb2d77e 100644
--- a/esp32s3/src/sensitive/edma_pms_aes_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_aes_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_AES_LOCK")
-            .field(
-                "edma_pms_aes_lock",
-                &format_args!("{}", self.edma_pms_aes_lock().bit()),
-            )
+            .field("edma_pms_aes_lock", &self.edma_pms_aes_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_AES_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-AES permission control registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_i2s0.rs b/esp32s3/src/sensitive/edma_pms_i2s0.rs
index 686e83da80..4fe2e0371a 100644
--- a/esp32s3/src/sensitive/edma_pms_i2s0.rs
+++ b/esp32s3/src/sensitive/edma_pms_i2s0.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_I2S0")
-            .field("attr1", &format_args!("{}", self.attr1().bits()))
-            .field("attr2", &format_args!("{}", self.attr2().bits()))
+            .field("attr1", &self.attr1())
+            .field("attr2", &self.attr2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_I2S0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_i2s0_lock.rs b/esp32s3/src/sensitive/edma_pms_i2s0_lock.rs
index 1a02bd75a3..f9604d2d81 100644
--- a/esp32s3/src/sensitive/edma_pms_i2s0_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_i2s0_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_I2S0_LOCK")
-            .field(
-                "edma_pms_i2s0_lock",
-                &format_args!("{}", self.edma_pms_i2s0_lock().bit()),
-            )
+            .field("edma_pms_i2s0_lock", &self.edma_pms_i2s0_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_I2S0_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-I2S0 permission control registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_i2s1.rs b/esp32s3/src/sensitive/edma_pms_i2s1.rs
index 333136fb2a..2b8468d991 100644
--- a/esp32s3/src/sensitive/edma_pms_i2s1.rs
+++ b/esp32s3/src/sensitive/edma_pms_i2s1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_I2S1")
-            .field("attr1", &format_args!("{}", self.attr1().bits()))
-            .field("attr2", &format_args!("{}", self.attr2().bits()))
+            .field("attr1", &self.attr1())
+            .field("attr2", &self.attr2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_I2S1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_i2s1_lock.rs b/esp32s3/src/sensitive/edma_pms_i2s1_lock.rs
index 65934246b4..58ee65efb7 100644
--- a/esp32s3/src/sensitive/edma_pms_i2s1_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_i2s1_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_I2S1_LOCK")
-            .field(
-                "edma_pms_i2s1_lock",
-                &format_args!("{}", self.edma_pms_i2s1_lock().bit()),
-            )
+            .field("edma_pms_i2s1_lock", &self.edma_pms_i2s1_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_I2S1_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-I2S1 permission control registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_lcd_cam.rs b/esp32s3/src/sensitive/edma_pms_lcd_cam.rs
index a070a5c3c2..da923d12dc 100644
--- a/esp32s3/src/sensitive/edma_pms_lcd_cam.rs
+++ b/esp32s3/src/sensitive/edma_pms_lcd_cam.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_LCD_CAM")
-            .field("attr1", &format_args!("{}", self.attr1().bits()))
-            .field("attr2", &format_args!("{}", self.attr2().bits()))
+            .field("attr1", &self.attr1())
+            .field("attr2", &self.attr2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_LCD_CAM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_lcd_cam_lock.rs b/esp32s3/src/sensitive/edma_pms_lcd_cam_lock.rs
index b592636abb..9493facf69 100644
--- a/esp32s3/src/sensitive/edma_pms_lcd_cam_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_lcd_cam_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_LCD_CAM_LOCK")
-            .field(
-                "edma_pms_lcd_cam_lock",
-                &format_args!("{}", self.edma_pms_lcd_cam_lock().bit()),
-            )
+            .field("edma_pms_lcd_cam_lock", &self.edma_pms_lcd_cam_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_LCD_CAM_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-LCD/CAM permission control registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_rmt.rs b/esp32s3/src/sensitive/edma_pms_rmt.rs
index c5568a921b..c3d14345dc 100644
--- a/esp32s3/src/sensitive/edma_pms_rmt.rs
+++ b/esp32s3/src/sensitive/edma_pms_rmt.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_RMT")
-            .field("attr1", &format_args!("{}", self.attr1().bits()))
-            .field("attr2", &format_args!("{}", self.attr2().bits()))
+            .field("attr1", &self.attr1())
+            .field("attr2", &self.attr2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_RMT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of RMT accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_rmt_lock.rs b/esp32s3/src/sensitive/edma_pms_rmt_lock.rs
index ebfafa74d9..ff75959731 100644
--- a/esp32s3/src/sensitive/edma_pms_rmt_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_rmt_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_RMT_LOCK")
-            .field(
-                "edma_pms_rmt_lock",
-                &format_args!("{}", self.edma_pms_rmt_lock().bit()),
-            )
+            .field("edma_pms_rmt_lock", &self.edma_pms_rmt_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_RMT_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-RMT permission control registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_sha.rs b/esp32s3/src/sensitive/edma_pms_sha.rs
index 1866a8481f..bdc77004d7 100644
--- a/esp32s3/src/sensitive/edma_pms_sha.rs
+++ b/esp32s3/src/sensitive/edma_pms_sha.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_SHA")
-            .field("attr1", &format_args!("{}", self.attr1().bits()))
-            .field("attr2", &format_args!("{}", self.attr2().bits()))
+            .field("attr1", &self.attr1())
+            .field("attr2", &self.attr2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_SHA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of SHA accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_sha_lock.rs b/esp32s3/src/sensitive/edma_pms_sha_lock.rs
index ec6b539550..abe670d5a1 100644
--- a/esp32s3/src/sensitive/edma_pms_sha_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_sha_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_SHA_LOCK")
-            .field(
-                "edma_pms_sha_lock",
-                &format_args!("{}", self.edma_pms_sha_lock().bit()),
-            )
+            .field("edma_pms_sha_lock", &self.edma_pms_sha_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_SHA_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-SHA permission control registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_spi2.rs b/esp32s3/src/sensitive/edma_pms_spi2.rs
index 7651bcaa2d..a40b3a02f0 100644
--- a/esp32s3/src/sensitive/edma_pms_spi2.rs
+++ b/esp32s3/src/sensitive/edma_pms_spi2.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_SPI2")
-            .field("attr1", &format_args!("{}", self.attr1().bits()))
-            .field("attr2", &format_args!("{}", self.attr2().bits()))
+            .field("attr1", &self.attr1())
+            .field("attr2", &self.attr2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_SPI2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_spi2_lock.rs b/esp32s3/src/sensitive/edma_pms_spi2_lock.rs
index 4888260981..1b4d450bda 100644
--- a/esp32s3/src/sensitive/edma_pms_spi2_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_spi2_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_SPI2_LOCK")
-            .field(
-                "edma_pms_spi2_lock",
-                &format_args!("{}", self.edma_pms_spi2_lock().bit()),
-            )
+            .field("edma_pms_spi2_lock", &self.edma_pms_spi2_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_SPI2_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-SPI2 permission control registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_spi3.rs b/esp32s3/src/sensitive/edma_pms_spi3.rs
index dc18b9072b..a2b28fd961 100644
--- a/esp32s3/src/sensitive/edma_pms_spi3.rs
+++ b/esp32s3/src/sensitive/edma_pms_spi3.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_SPI3")
-            .field("attr1", &format_args!("{}", self.attr1().bits()))
-            .field("attr2", &format_args!("{}", self.attr2().bits()))
+            .field("attr1", &self.attr1())
+            .field("attr2", &self.attr2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_SPI3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_spi3_lock.rs b/esp32s3/src/sensitive/edma_pms_spi3_lock.rs
index ecdc1dc7da..923822ed58 100644
--- a/esp32s3/src/sensitive/edma_pms_spi3_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_spi3_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_SPI3_LOCK")
-            .field(
-                "edma_pms_spi3_lock",
-                &format_args!("{}", self.edma_pms_spi3_lock().bit()),
-            )
+            .field("edma_pms_spi3_lock", &self.edma_pms_spi3_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_SPI3_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-SPI3 permission control registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_uhci0.rs b/esp32s3/src/sensitive/edma_pms_uhci0.rs
index 1819dcaf79..06fd499ac3 100644
--- a/esp32s3/src/sensitive/edma_pms_uhci0.rs
+++ b/esp32s3/src/sensitive/edma_pms_uhci0.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_UHCI0")
-            .field("attr1", &format_args!("{}", self.attr1().bits()))
-            .field("attr2", &format_args!("{}", self.attr2().bits()))
+            .field("attr1", &self.attr1())
+            .field("attr2", &self.attr2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_UHCI0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/edma_pms_uhci0_lock.rs b/esp32s3/src/sensitive/edma_pms_uhci0_lock.rs
index 61b670d96b..1b46d3e876 100644
--- a/esp32s3/src/sensitive/edma_pms_uhci0_lock.rs
+++ b/esp32s3/src/sensitive/edma_pms_uhci0_lock.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_PMS_UHCI0_LOCK")
-            .field(
-                "edma_pms_uhci0_lock",
-                &format_args!("{}", self.edma_pms_uhci0_lock().bit()),
-            )
+            .field("edma_pms_uhci0_lock", &self.edma_pms_uhci0_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_PMS_UHCI0_LOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock EDMA-UHCI0 permission control registers."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/internal_sram_usage_0.rs b/esp32s3/src/sensitive/internal_sram_usage_0.rs
index cbf17b54e9..3daaea5e45 100644
--- a/esp32s3/src/sensitive/internal_sram_usage_0.rs
+++ b/esp32s3/src/sensitive/internal_sram_usage_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERNAL_SRAM_USAGE_0")
-            .field(
-                "internal_sram_usage_lock",
-                &format_args!("{}", self.internal_sram_usage_lock().bit()),
-            )
+            .field("internal_sram_usage_lock", &self.internal_sram_usage_lock())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERNAL_SRAM_USAGE_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to lock internal SRAM Configuration Register."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/internal_sram_usage_1.rs b/esp32s3/src/sensitive/internal_sram_usage_1.rs
index 0464997994..ccb29cc348 100644
--- a/esp32s3/src/sensitive/internal_sram_usage_1.rs
+++ b/esp32s3/src/sensitive/internal_sram_usage_1.rs
@@ -37,25 +37,16 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTERNAL_SRAM_USAGE_1")
             .field(
                 "internal_sram_icache_usage",
-                &format_args!("{}", self.internal_sram_icache_usage().bits()),
+                &self.internal_sram_icache_usage(),
             )
             .field(
                 "internal_sram_dcache_usage",
-                &format_args!("{}", self.internal_sram_dcache_usage().bits()),
-            )
-            .field(
-                "internal_sram_cpu_usage",
-                &format_args!("{}", self.internal_sram_cpu_usage().bits()),
+                &self.internal_sram_dcache_usage(),
             )
+            .field("internal_sram_cpu_usage", &self.internal_sram_cpu_usage())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERNAL_SRAM_USAGE_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - Set 1 to someone bit means corresponding internal SRAM level can be accessed by icache."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/internal_sram_usage_2.rs b/esp32s3/src/sensitive/internal_sram_usage_2.rs
index 224198f381..c414115003 100644
--- a/esp32s3/src/sensitive/internal_sram_usage_2.rs
+++ b/esp32s3/src/sensitive/internal_sram_usage_2.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTERNAL_SRAM_USAGE_2")
             .field(
                 "internal_sram_core0_trace_usage",
-                &format_args!("{}", self.internal_sram_core0_trace_usage().bits()),
+                &self.internal_sram_core0_trace_usage(),
             )
             .field(
                 "internal_sram_core1_trace_usage",
-                &format_args!("{}", self.internal_sram_core1_trace_usage().bits()),
+                &self.internal_sram_core1_trace_usage(),
             )
             .field(
                 "internal_sram_core0_trace_alloc",
-                &format_args!("{}", self.internal_sram_core0_trace_alloc().bits()),
+                &self.internal_sram_core0_trace_alloc(),
             )
             .field(
                 "internal_sram_core1_trace_alloc",
-                &format_args!("{}", self.internal_sram_core1_trace_alloc().bits()),
+                &self.internal_sram_core1_trace_alloc(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERNAL_SRAM_USAGE_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Set 1 to someone bit means corresponding internal SRAM level can be accessed by core0 trace bus."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/internal_sram_usage_3.rs b/esp32s3/src/sensitive/internal_sram_usage_3.rs
index ae29a75c7a..33e4c11f28 100644
--- a/esp32s3/src/sensitive/internal_sram_usage_3.rs
+++ b/esp32s3/src/sensitive/internal_sram_usage_3.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("INTERNAL_SRAM_USAGE_3")
             .field(
                 "internal_sram_mac_dump_usage",
-                &format_args!("{}", self.internal_sram_mac_dump_usage().bits()),
+                &self.internal_sram_mac_dump_usage(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERNAL_SRAM_USAGE_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - Set 1 to someone bit means corresponding internal SRAM level can be accessed by mac dump."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/internal_sram_usage_4.rs b/esp32s3/src/sensitive/internal_sram_usage_4.rs
index 1939e54abd..a7c7700db1 100644
--- a/esp32s3/src/sensitive/internal_sram_usage_4.rs
+++ b/esp32s3/src/sensitive/internal_sram_usage_4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTERNAL_SRAM_USAGE_4")
-            .field(
-                "internal_sram_log_usage",
-                &format_args!("{}", self.internal_sram_log_usage().bits()),
-            )
+            .field("internal_sram_log_usage", &self.internal_sram_log_usage())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTERNAL_SRAM_USAGE_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6 - Set 1 to someone bit means corresponding internal SRAM level can be accessed by log bus."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/retention_disable.rs b/esp32s3/src/sensitive/retention_disable.rs
index e93fb460ee..6c62217370 100644
--- a/esp32s3/src/sensitive/retention_disable.rs
+++ b/esp32s3/src/sensitive/retention_disable.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RETENTION_DISABLE")
-            .field(
-                "retention_disable",
-                &format_args!("{}", self.retention_disable().bit()),
-            )
+            .field("retention_disable", &self.retention_disable())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RETENTION_DISABLE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to disable retention function and lock disable state."]
     #[inline(always)]
diff --git a/esp32s3/src/sensitive/rtc_pms.rs b/esp32s3/src/sensitive/rtc_pms.rs
index 82874c746d..46ba011dc5 100644
--- a/esp32s3/src/sensitive/rtc_pms.rs
+++ b/esp32s3/src/sensitive/rtc_pms.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_PMS")
-            .field("dis_rtc_cpu", &format_args!("{}", self.dis_rtc_cpu().bit()))
+            .field("dis_rtc_cpu", &self.dis_rtc_cpu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_PMS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to disable rtc coprocessor."]
     #[inline(always)]
diff --git a/esp32s3/src/sha/busy.rs b/esp32s3/src/sha/busy.rs
index 9f8e9c5fe1..3c5d443ae4 100644
--- a/esp32s3/src/sha/busy.rs
+++ b/esp32s3/src/sha/busy.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUSY")
-            .field("state", &format_args!("{}", self.state().bit()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUSY_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Busy register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`busy::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BUSY_SPEC;
 impl crate::RegisterSpec for BUSY_SPEC {
diff --git a/esp32s3/src/sha/date.rs b/esp32s3/src/sha/date.rs
index 6f8f471f4c..e54b2dfeb9 100644
--- a/esp32s3/src/sha/date.rs
+++ b/esp32s3/src/sha/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/sha/dma_block_num.rs b/esp32s3/src/sha/dma_block_num.rs
index d878b2a3cd..9ded0c75ef 100644
--- a/esp32s3/src/sha/dma_block_num.rs
+++ b/esp32s3/src/sha/dma_block_num.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_BLOCK_NUM")
-            .field(
-                "dma_block_num",
-                &format_args!("{}", self.dma_block_num().bits()),
-            )
+            .field("dma_block_num", &self.dma_block_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_BLOCK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - dma-sha block number"]
     #[inline(always)]
diff --git a/esp32s3/src/sha/h_mem.rs b/esp32s3/src/sha/h_mem.rs
index e0865c92c6..13a6f95266 100644
--- a/esp32s3/src/sha/h_mem.rs
+++ b/esp32s3/src/sha/h_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<H_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Sha H memory which contains intermediate hash or finial hash.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`h_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`h_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct H_MEM_SPEC;
diff --git a/esp32s3/src/sha/irq_ena.rs b/esp32s3/src/sha/irq_ena.rs
index 506692ee03..1dea07dfb7 100644
--- a/esp32s3/src/sha/irq_ena.rs
+++ b/esp32s3/src/sha/irq_ena.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IRQ_ENA")
-            .field(
-                "interrupt_ena",
-                &format_args!("{}", self.interrupt_ena().bit()),
-            )
+            .field("interrupt_ena", &self.interrupt_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IRQ_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - sha interrupt enable register. 1'b0: disable(default) 1'b1: enable"]
     #[inline(always)]
diff --git a/esp32s3/src/sha/m_mem.rs b/esp32s3/src/sha/m_mem.rs
index ccac5e7d71..7418659e89 100644
--- a/esp32s3/src/sha/m_mem.rs
+++ b/esp32s3/src/sha/m_mem.rs
@@ -8,12 +8,6 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<M_MEM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {}
 #[doc = "Sha M memory which contains message.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`m_mem::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`m_mem::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct M_MEM_SPEC;
diff --git a/esp32s3/src/sha/mode.rs b/esp32s3/src/sha/mode.rs
index e457f0f9f1..693653fc7f 100644
--- a/esp32s3/src/sha/mode.rs
+++ b/esp32s3/src/sha/mode.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("MODE")
-            .field("mode", &format_args!("{}", self.mode().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("MODE").field("mode", &self.mode()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/sha/t_length.rs b/esp32s3/src/sha/t_length.rs
index 5fba1fbe66..9cc688ca3c 100644
--- a/esp32s3/src/sha/t_length.rs
+++ b/esp32s3/src/sha/t_length.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T_LENGTH")
-            .field("t_length", &format_args!("{}", self.t_length().bits()))
+            .field("t_length", &self.t_length())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T_LENGTH_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - sha t_length(used if and only if mode == sha_256/t)"]
     #[inline(always)]
diff --git a/esp32s3/src/sha/t_string.rs b/esp32s3/src/sha/t_string.rs
index 977009f761..8c8792f90c 100644
--- a/esp32s3/src/sha/t_string.rs
+++ b/esp32s3/src/sha/t_string.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("T_STRING")
-            .field("t_string", &format_args!("{}", self.t_string().bits()))
+            .field("t_string", &self.t_string())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<T_STRING_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - sha t_string(used if and only if mode == sha_256/t)"]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/cache_fctrl.rs b/esp32s3/src/spi0/cache_fctrl.rs
index 963b3cc8b9..1829253041 100644
--- a/esp32s3/src/spi0/cache_fctrl.rs
+++ b/esp32s3/src/spi0/cache_fctrl.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_FCTRL")
-            .field(
-                "cache_req_en",
-                &format_args!("{}", self.cache_req_en().bit()),
-            )
-            .field(
-                "cache_usr_cmd_4byte",
-                &format_args!("{}", self.cache_usr_cmd_4byte().bit()),
-            )
-            .field(
-                "cache_flash_usr_cmd",
-                &format_args!("{}", self.cache_flash_usr_cmd().bit()),
-            )
-            .field("fdin_dual", &format_args!("{}", self.fdin_dual().bit()))
-            .field("fdout_dual", &format_args!("{}", self.fdout_dual().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("fdin_quad", &format_args!("{}", self.fdin_quad().bit()))
-            .field("fdout_quad", &format_args!("{}", self.fdout_quad().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
+            .field("cache_req_en", &self.cache_req_en())
+            .field("cache_usr_cmd_4byte", &self.cache_usr_cmd_4byte())
+            .field("cache_flash_usr_cmd", &self.cache_flash_usr_cmd())
+            .field("fdin_dual", &self.fdin_dual())
+            .field("fdout_dual", &self.fdout_dual())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("fdin_quad", &self.fdin_quad())
+            .field("fdout_quad", &self.fdout_quad())
+            .field("faddr_quad", &self.faddr_quad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_FCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable Cache's access and SPI0's transfer."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/cache_sctrl.rs b/esp32s3/src/spi0/cache_sctrl.rs
index 060ef5a3de..7ddddb58cf 100644
--- a/esp32s3/src/spi0/cache_sctrl.rs
+++ b/esp32s3/src/spi0/cache_sctrl.rs
@@ -107,56 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_SCTRL")
-            .field(
-                "cache_usr_scmd_4byte",
-                &format_args!("{}", self.cache_usr_scmd_4byte().bit()),
-            )
-            .field(
-                "usr_sram_dio",
-                &format_args!("{}", self.usr_sram_dio().bit()),
-            )
-            .field(
-                "usr_sram_qio",
-                &format_args!("{}", self.usr_sram_qio().bit()),
-            )
-            .field(
-                "usr_wr_sram_dummy",
-                &format_args!("{}", self.usr_wr_sram_dummy().bit()),
-            )
-            .field(
-                "usr_rd_sram_dummy",
-                &format_args!("{}", self.usr_rd_sram_dummy().bit()),
-            )
-            .field(
-                "cache_sram_usr_rcmd",
-                &format_args!("{}", self.cache_sram_usr_rcmd().bit()),
-            )
-            .field(
-                "sram_rdummy_cyclelen",
-                &format_args!("{}", self.sram_rdummy_cyclelen().bits()),
-            )
-            .field(
-                "sram_addr_bitlen",
-                &format_args!("{}", self.sram_addr_bitlen().bits()),
-            )
-            .field(
-                "cache_sram_usr_wcmd",
-                &format_args!("{}", self.cache_sram_usr_wcmd().bit()),
-            )
-            .field("sram_oct", &format_args!("{}", self.sram_oct().bit()))
-            .field(
-                "sram_wdummy_cyclelen",
-                &format_args!("{}", self.sram_wdummy_cyclelen().bits()),
-            )
+            .field("cache_usr_scmd_4byte", &self.cache_usr_scmd_4byte())
+            .field("usr_sram_dio", &self.usr_sram_dio())
+            .field("usr_sram_qio", &self.usr_sram_qio())
+            .field("usr_wr_sram_dummy", &self.usr_wr_sram_dummy())
+            .field("usr_rd_sram_dummy", &self.usr_rd_sram_dummy())
+            .field("cache_sram_usr_rcmd", &self.cache_sram_usr_rcmd())
+            .field("sram_rdummy_cyclelen", &self.sram_rdummy_cyclelen())
+            .field("sram_addr_bitlen", &self.sram_addr_bitlen())
+            .field("cache_sram_usr_wcmd", &self.cache_sram_usr_wcmd())
+            .field("sram_oct", &self.sram_oct())
+            .field("sram_wdummy_cyclelen", &self.sram_wdummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_SCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/clock.rs b/esp32s3/src/spi0/clock.rs
index 0c36e6b73d..22b118b890 100644
--- a/esp32s3/src/spi0/clock.rs
+++ b/esp32s3/src/spi0/clock.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - It must equal to the value of SPI_MEM_CLKCNT_N."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/clock_gate.rs b/esp32s3/src/spi0/clock_gate.rs
index 9137df9c1e..82cb1e6398 100644
--- a/esp32s3/src/spi0/clock_gate.rs
+++ b/esp32s3/src/spi0/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/core_clk_sel.rs b/esp32s3/src/spi0/core_clk_sel.rs
index 4d9e7fc4c2..5508a421f0 100644
--- a/esp32s3/src/spi0/core_clk_sel.rs
+++ b/esp32s3/src/spi0/core_clk_sel.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_CLK_SEL")
-            .field(
-                "core_clk_sel",
-                &format_args!("{}", self.core_clk_sel().bits()),
-            )
+            .field("core_clk_sel", &self.core_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_CLK_SEL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz. 2: MSPI_CORE_CLK is 160MHz. 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: MSPI_CORE_CLK is 80MHz. 1: MSPI_CORE_CLK is 80MHz. 2: MSPI_CORE_CLK 160MHz. 3: Not used."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/ctrl.rs b/esp32s3/src/spi0/ctrl.rs
index bb6388d280..795d937793 100644
--- a/esp32s3/src/spi0/ctrl.rs
+++ b/esp32s3/src/spi0/ctrl.rs
@@ -143,30 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("fdummy_out", &format_args!("{}", self.fdummy_out().bit()))
-            .field("fdout_oct", &format_args!("{}", self.fdout_oct().bit()))
-            .field("fdin_oct", &format_args!("{}", self.fdin_oct().bit()))
-            .field("faddr_oct", &format_args!("{}", self.faddr_oct().bit()))
-            .field("fcmd_dual", &format_args!("{}", self.fcmd_dual().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcmd_oct", &format_args!("{}", self.fcmd_oct().bit()))
-            .field("fastrd_mode", &format_args!("{}", self.fastrd_mode().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("wp", &format_args!("{}", self.wp().bit()))
-            .field("fread_dio", &format_args!("{}", self.fread_dio().bit()))
-            .field("fread_qio", &format_args!("{}", self.fread_qio().bit()))
+            .field("fdummy_out", &self.fdummy_out())
+            .field("fdout_oct", &self.fdout_oct())
+            .field("fdin_oct", &self.fdin_oct())
+            .field("faddr_oct", &self.faddr_oct())
+            .field("fcmd_dual", &self.fcmd_dual())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcmd_oct", &self.fcmd_oct())
+            .field("fastrd_mode", &self.fastrd_mode())
+            .field("fread_dual", &self.fread_dual())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("fread_quad", &self.fread_quad())
+            .field("wp", &self.wp())
+            .field("fread_dio", &self.fread_dio())
+            .field("fread_qio", &self.fread_qio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/ctrl1.rs b/esp32s3/src/spi0/ctrl1.rs
index b047360a9f..c9e7ab9697 100644
--- a/esp32s3/src/spi0/ctrl1.rs
+++ b/esp32s3/src/spi0/ctrl1.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL1")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
-            .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit()))
+            .field("clk_mode", &self.clk_mode())
+            .field("rxfifo_rst", &self.rxfifo_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/ctrl2.rs b/esp32s3/src/spi0/ctrl2.rs
index 35d9fce41f..5d186a64bc 100644
--- a/esp32s3/src/spi0/ctrl2.rs
+++ b/esp32s3/src/spi0/ctrl2.rs
@@ -71,40 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field(
-                "cs_setup_time",
-                &format_args!("{}", self.cs_setup_time().bits()),
-            )
-            .field(
-                "cs_hold_time",
-                &format_args!("{}", self.cs_hold_time().bits()),
-            )
-            .field(
-                "ecc_cs_hold_time",
-                &format_args!("{}", self.ecc_cs_hold_time().bits()),
-            )
-            .field(
-                "ecc_skip_page_corner",
-                &format_args!("{}", self.ecc_skip_page_corner().bit()),
-            )
-            .field(
-                "ecc_16to18_byte_en",
-                &format_args!("{}", self.ecc_16to18_byte_en().bit()),
-            )
-            .field(
-                "cs_hold_delay",
-                &format_args!("{}", self.cs_hold_delay().bits()),
-            )
-            .field("sync_reset", &format_args!("{}", self.sync_reset().bit()))
+            .field("cs_setup_time", &self.cs_setup_time())
+            .field("cs_hold_time", &self.cs_hold_time())
+            .field("ecc_cs_hold_time", &self.ecc_cs_hold_time())
+            .field("ecc_skip_page_corner", &self.ecc_skip_page_corner())
+            .field("ecc_16to18_byte_en", &self.ecc_16to18_byte_en())
+            .field("cs_hold_delay", &self.cs_hold_delay())
+            .field("sync_reset", &self.sync_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/date.rs b/esp32s3/src/spi0/date.rs
index a316534980..bb76fcd895 100644
--- a/esp32s3/src/spi0/date.rs
+++ b/esp32s3/src/spi0/date.rs
@@ -44,28 +44,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "spi_smem_spiclk_fun_drv",
-                &format_args!("{}", self.spi_smem_spiclk_fun_drv().bits()),
-            )
-            .field(
-                "spi_fmem_spiclk_fun_drv",
-                &format_args!("{}", self.spi_fmem_spiclk_fun_drv().bits()),
-            )
+            .field("spi_smem_spiclk_fun_drv", &self.spi_smem_spiclk_fun_drv())
+            .field("spi_fmem_spiclk_fun_drv", &self.spi_fmem_spiclk_fun_drv())
             .field(
                 "spi_spiclk_pad_drv_ctl_en",
-                &format_args!("{}", self.spi_spiclk_pad_drv_ctl_en().bit()),
+                &self.spi_spiclk_pad_drv_ctl_en(),
             )
-            .field("date", &format_args!("{}", self.date().bits()))
+            .field("date", &self.date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - The driver of SPI_CLK PAD is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV\\[1:0\\] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/ddr.rs b/esp32s3/src/spi0/ddr.rs
index 2f083351b2..88da0cdedd 100644
--- a/esp32s3/src/spi0/ddr.rs
+++ b/esp32s3/src/spi0/ddr.rs
@@ -170,87 +170,33 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DDR")
-            .field(
-                "spi_fmem_ddr_en",
-                &format_args!("{}", self.spi_fmem_ddr_en().bit()),
-            )
-            .field(
-                "spi_fmem_var_dummy",
-                &format_args!("{}", self.spi_fmem_var_dummy().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_rdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_rdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_wdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_wdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_cmd_dis",
-                &format_args!("{}", self.spi_fmem_ddr_cmd_dis().bit()),
-            )
-            .field(
-                "spi_fmem_outminbytelen",
-                &format_args!("{}", self.spi_fmem_outminbytelen().bits()),
-            )
-            .field(
-                "spi_fmem_tx_ddr_msk_en",
-                &format_args!("{}", self.spi_fmem_tx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_fmem_rx_ddr_msk_en",
-                &format_args!("{}", self.spi_fmem_rx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_fmem_usr_ddr_dqs_thd",
-                &format_args!("{}", self.spi_fmem_usr_ddr_dqs_thd().bits()),
-            )
-            .field(
-                "spi_fmem_ddr_dqs_loop",
-                &format_args!("{}", self.spi_fmem_ddr_dqs_loop().bit()),
-            )
+            .field("spi_fmem_ddr_en", &self.spi_fmem_ddr_en())
+            .field("spi_fmem_var_dummy", &self.spi_fmem_var_dummy())
+            .field("spi_fmem_ddr_rdat_swp", &self.spi_fmem_ddr_rdat_swp())
+            .field("spi_fmem_ddr_wdat_swp", &self.spi_fmem_ddr_wdat_swp())
+            .field("spi_fmem_ddr_cmd_dis", &self.spi_fmem_ddr_cmd_dis())
+            .field("spi_fmem_outminbytelen", &self.spi_fmem_outminbytelen())
+            .field("spi_fmem_tx_ddr_msk_en", &self.spi_fmem_tx_ddr_msk_en())
+            .field("spi_fmem_rx_ddr_msk_en", &self.spi_fmem_rx_ddr_msk_en())
+            .field("spi_fmem_usr_ddr_dqs_thd", &self.spi_fmem_usr_ddr_dqs_thd())
+            .field("spi_fmem_ddr_dqs_loop", &self.spi_fmem_ddr_dqs_loop())
             .field(
                 "spi_fmem_ddr_dqs_loop_mode",
-                &format_args!("{}", self.spi_fmem_ddr_dqs_loop_mode().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_en",
-                &format_args!("{}", self.spi_fmem_clk_diff_en().bit()),
-            )
-            .field(
-                "spi_fmem_hyperbus_mode",
-                &format_args!("{}", self.spi_fmem_hyperbus_mode().bit()),
-            )
-            .field(
-                "spi_fmem_dqs_ca_in",
-                &format_args!("{}", self.spi_fmem_dqs_ca_in().bit()),
+                &self.spi_fmem_ddr_dqs_loop_mode(),
             )
+            .field("spi_fmem_clk_diff_en", &self.spi_fmem_clk_diff_en())
+            .field("spi_fmem_hyperbus_mode", &self.spi_fmem_hyperbus_mode())
+            .field("spi_fmem_dqs_ca_in", &self.spi_fmem_dqs_ca_in())
             .field(
                 "spi_fmem_hyperbus_dummy_2x",
-                &format_args!("{}", self.spi_fmem_hyperbus_dummy_2x().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_inv",
-                &format_args!("{}", self.spi_fmem_clk_diff_inv().bit()),
-            )
-            .field(
-                "spi_fmem_octa_ram_addr",
-                &format_args!("{}", self.spi_fmem_octa_ram_addr().bit()),
-            )
-            .field(
-                "spi_fmem_hyperbus_ca",
-                &format_args!("{}", self.spi_fmem_hyperbus_ca().bit()),
+                &self.spi_fmem_hyperbus_dummy_2x(),
             )
+            .field("spi_fmem_clk_diff_inv", &self.spi_fmem_clk_diff_inv())
+            .field("spi_fmem_octa_ram_addr", &self.spi_fmem_octa_ram_addr())
+            .field("spi_fmem_hyperbus_ca", &self.spi_fmem_hyperbus_ca())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: in ddr mode, 0 in sdr mode"]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/din_mode.rs b/esp32s3/src/spi0/din_mode.rs
index d802025c1a..3e3bd4e0bf 100644
--- a/esp32s3/src/spi0/din_mode.rs
+++ b/esp32s3/src/spi0/din_mode.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_MODE")
-            .field("din0_mode", &format_args!("{}", self.din0_mode().bits()))
-            .field("din1_mode", &format_args!("{}", self.din1_mode().bits()))
-            .field("din2_mode", &format_args!("{}", self.din2_mode().bits()))
-            .field("din3_mode", &format_args!("{}", self.din3_mode().bits()))
-            .field("din4_mode", &format_args!("{}", self.din4_mode().bits()))
-            .field("din5_mode", &format_args!("{}", self.din5_mode().bits()))
-            .field("din6_mode", &format_args!("{}", self.din6_mode().bits()))
-            .field("din7_mode", &format_args!("{}", self.din7_mode().bits()))
-            .field("dins_mode", &format_args!("{}", self.dins_mode().bits()))
+            .field("din0_mode", &self.din0_mode())
+            .field("din1_mode", &self.din1_mode())
+            .field("din2_mode", &self.din2_mode())
+            .field("din3_mode", &self.din3_mode())
+            .field("din4_mode", &self.din4_mode())
+            .field("din5_mode", &self.din5_mode())
+            .field("din6_mode", &self.din6_mode())
+            .field("din7_mode", &self.din7_mode())
+            .field("dins_mode", &self.dins_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/din_num.rs b/esp32s3/src/spi0/din_num.rs
index d447774b04..418a117303 100644
--- a/esp32s3/src/spi0/din_num.rs
+++ b/esp32s3/src/spi0/din_num.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_NUM")
-            .field("din0_num", &format_args!("{}", self.din0_num().bits()))
-            .field("din1_num", &format_args!("{}", self.din1_num().bits()))
-            .field("din2_num", &format_args!("{}", self.din2_num().bits()))
-            .field("din3_num", &format_args!("{}", self.din3_num().bits()))
-            .field("din4_num", &format_args!("{}", self.din4_num().bits()))
-            .field("din5_num", &format_args!("{}", self.din5_num().bits()))
-            .field("din6_num", &format_args!("{}", self.din6_num().bits()))
-            .field("din7_num", &format_args!("{}", self.din7_num().bits()))
-            .field("dins_num", &format_args!("{}", self.dins_num().bits()))
+            .field("din0_num", &self.din0_num())
+            .field("din1_num", &self.din1_num())
+            .field("din2_num", &self.din2_num())
+            .field("din3_num", &self.din3_num())
+            .field("din4_num", &self.din4_num())
+            .field("din5_num", &self.din5_num())
+            .field("din6_num", &self.din6_num())
+            .field("din7_num", &self.din7_num())
+            .field("dins_num", &self.dins_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI_D input delay number."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/dout_mode.rs b/esp32s3/src/spi0/dout_mode.rs
index 94b1c742a8..3ce506bb86 100644
--- a/esp32s3/src/spi0/dout_mode.rs
+++ b/esp32s3/src/spi0/dout_mode.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOUT_MODE")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bit()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bit()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bit()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bit()))
-            .field("dout4_mode", &format_args!("{}", self.dout4_mode().bit()))
-            .field("dout5_mode", &format_args!("{}", self.dout5_mode().bit()))
-            .field("dout6_mode", &format_args!("{}", self.dout6_mode().bit()))
-            .field("dout7_mode", &format_args!("{}", self.dout7_mode().bit()))
-            .field("douts_mode", &format_args!("{}", self.douts_mode().bit()))
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
+            .field("dout4_mode", &self.dout4_mode())
+            .field("dout5_mode", &self.dout5_mode())
+            .field("dout6_mode", &self.dout6_mode())
+            .field("dout7_mode", &self.dout7_mode())
+            .field("douts_mode", &self.douts_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/ecc_ctrl.rs b/esp32s3/src/spi0/ecc_ctrl.rs
index e79cc91fc6..4cda5e7fa9 100644
--- a/esp32s3/src/spi0/ecc_ctrl.rs
+++ b/esp32s3/src/spi0/ecc_ctrl.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_CTRL")
-            .field(
-                "ecc_err_int_num",
-                &format_args!("{}", self.ecc_err_int_num().bits()),
-            )
-            .field(
-                "spi_fmem_ecc_err_int_en",
-                &format_args!("{}", self.spi_fmem_ecc_err_int_en().bit()),
-            )
+            .field("ecc_err_int_num", &self.ecc_err_int_num())
+            .field("spi_fmem_ecc_err_int_en", &self.spi_fmem_ecc_err_int_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/ecc_err_addr.rs b/esp32s3/src/spi0/ecc_err_addr.rs
index 5859e8cc11..0a92c8c574 100644
--- a/esp32s3/src/spi0/ecc_err_addr.rs
+++ b/esp32s3/src/spi0/ecc_err_addr.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_ERR_ADDR")
-            .field(
-                "ecc_err_addr",
-                &format_args!("{}", self.ecc_err_addr().bits()),
-            )
+            .field("ecc_err_addr", &self.ecc_err_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_ERR_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI ECC error address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecc_err_addr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ECC_ERR_ADDR_SPEC;
 impl crate::RegisterSpec for ECC_ERR_ADDR_SPEC {
diff --git a/esp32s3/src/spi0/ecc_err_bit.rs b/esp32s3/src/spi0/ecc_err_bit.rs
index 23307620e2..cf61dd2845 100644
--- a/esp32s3/src/spi0/ecc_err_bit.rs
+++ b/esp32s3/src/spi0/ecc_err_bit.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ECC_ERR_BIT")
-            .field(
-                "ecc_data_err_bit",
-                &format_args!("{}", self.ecc_data_err_bit().bits()),
-            )
-            .field(
-                "ecc_chk_err_bit",
-                &format_args!("{}", self.ecc_chk_err_bit().bits()),
-            )
-            .field(
-                "ecc_byte_err",
-                &format_args!("{}", self.ecc_byte_err().bit()),
-            )
-            .field(
-                "ecc_err_cnt",
-                &format_args!("{}", self.ecc_err_cnt().bits()),
-            )
+            .field("ecc_data_err_bit", &self.ecc_data_err_bit())
+            .field("ecc_chk_err_bit", &self.ecc_chk_err_bit())
+            .field("ecc_byte_err", &self.ecc_byte_err())
+            .field("ecc_err_cnt", &self.ecc_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ECC_ERR_BIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "MSPI ECC error bits register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecc_err_bit::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ECC_ERR_BIT_SPEC;
 impl crate::RegisterSpec for ECC_ERR_BIT_SPEC {
diff --git a/esp32s3/src/spi0/ext_addr.rs b/esp32s3/src/spi0/ext_addr.rs
index e3356d04a7..6079032560 100644
--- a/esp32s3/src/spi0/ext_addr.rs
+++ b/esp32s3/src/spi0/ext_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_ADDR")
-            .field("ext_addr", &format_args!("{}", self.ext_addr().bits()))
+            .field("ext_addr", &self.ext_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The register are the higher 32bits in the 64 bits address mode."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/fsm.rs b/esp32s3/src/spi0/fsm.rs
index 7e2d180086..69f7c856a0 100644
--- a/esp32s3/src/spi0/fsm.rs
+++ b/esp32s3/src/spi0/fsm.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("FSM")
-            .field("st", &format_args!("{}", self.st().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("FSM").field("st", &self.st()).finish()
     }
 }
 #[doc = "SPI0 state machine(FSM) status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s3/src/spi0/int_ena.rs b/esp32s3/src/spi0/int_ena.rs
index 1263d81b86..e18e895b9d 100644
--- a/esp32s3/src/spi0/int_ena.rs
+++ b/esp32s3/src/spi0/int_ena.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "total_trans_end",
-                &format_args!("{}", self.total_trans_end().bit()),
-            )
-            .field("ecc_err", &format_args!("{}", self.ecc_err().bit()))
+            .field("total_trans_end", &self.total_trans_end())
+            .field("ecc_err", &self.ecc_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/int_raw.rs b/esp32s3/src/spi0/int_raw.rs
index 9dd294181b..02aa024f56 100644
--- a/esp32s3/src/spi0/int_raw.rs
+++ b/esp32s3/src/spi0/int_raw.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "total_trans_end",
-                &format_args!("{}", self.total_trans_end().bit()),
-            )
-            .field("ecc_err", &format_args!("{}", self.ecc_err().bit()))
+            .field("total_trans_end", &self.total_trans_end())
+            .field("ecc_err", &self.ecc_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2 - The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/int_st.rs b/esp32s3/src/spi0/int_st.rs
index 2dc96672f0..2df9dc285f 100644
--- a/esp32s3/src/spi0/int_st.rs
+++ b/esp32s3/src/spi0/int_st.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "total_trans_end",
-                &format_args!("{}", self.total_trans_end().bit()),
-            )
-            .field("ecc_err", &format_args!("{}", self.ecc_err().bit()))
+            .field("total_trans_end", &self.total_trans_end())
+            .field("ecc_err", &self.ecc_err())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/spi0/misc.rs b/esp32s3/src/spi0/misc.rs
index dbd57ae286..6b5eed2756 100644
--- a/esp32s3/src/spi0/misc.rs
+++ b/esp32s3/src/spi0/misc.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("fsub_pin", &format_args!("{}", self.fsub_pin().bit()))
-            .field("ssub_pin", &format_args!("{}", self.ssub_pin().bit()))
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
+            .field("fsub_pin", &self.fsub_pin())
+            .field("ssub_pin", &self.ssub_pin())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 7 - Flash is connected to SPI SUBPIN bus."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/rd_status.rs b/esp32s3/src/spi0/rd_status.rs
index e419c8a184..bd706b964b 100644
--- a/esp32s3/src/spi0/rd_status.rs
+++ b/esp32s3/src/spi0/rd_status.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_STATUS")
-            .field("wb_mode", &format_args!("{}", self.wb_mode().bits()))
+            .field("wb_mode", &self.wb_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:23 - Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/spi_smem_ac.rs b/esp32s3/src/spi0/spi_smem_ac.rs
index f4f0562bf8..a3f6db1434 100644
--- a/esp32s3/src/spi0/spi_smem_ac.rs
+++ b/esp32s3/src/spi0/spi_smem_ac.rs
@@ -89,51 +89,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_AC")
-            .field(
-                "spi_smem_cs_setup",
-                &format_args!("{}", self.spi_smem_cs_setup().bit()),
-            )
-            .field(
-                "spi_smem_cs_hold",
-                &format_args!("{}", self.spi_smem_cs_hold().bit()),
-            )
-            .field(
-                "spi_smem_cs_setup_time",
-                &format_args!("{}", self.spi_smem_cs_setup_time().bits()),
-            )
-            .field(
-                "spi_smem_cs_hold_time",
-                &format_args!("{}", self.spi_smem_cs_hold_time().bits()),
-            )
+            .field("spi_smem_cs_setup", &self.spi_smem_cs_setup())
+            .field("spi_smem_cs_hold", &self.spi_smem_cs_hold())
+            .field("spi_smem_cs_setup_time", &self.spi_smem_cs_setup_time())
+            .field("spi_smem_cs_hold_time", &self.spi_smem_cs_hold_time())
             .field(
                 "spi_smem_ecc_cs_hold_time",
-                &format_args!("{}", self.spi_smem_ecc_cs_hold_time().bits()),
+                &self.spi_smem_ecc_cs_hold_time(),
             )
             .field(
                 "spi_smem_ecc_skip_page_corner",
-                &format_args!("{}", self.spi_smem_ecc_skip_page_corner().bit()),
+                &self.spi_smem_ecc_skip_page_corner(),
             )
             .field(
                 "spi_smem_ecc_16to18_byte_en",
-                &format_args!("{}", self.spi_smem_ecc_16to18_byte_en().bit()),
-            )
-            .field(
-                "spi_smem_ecc_err_int_en",
-                &format_args!("{}", self.spi_smem_ecc_err_int_en().bit()),
-            )
-            .field(
-                "spi_smem_cs_hold_delay",
-                &format_args!("{}", self.spi_smem_cs_hold_delay().bits()),
+                &self.spi_smem_ecc_16to18_byte_en(),
             )
+            .field("spi_smem_ecc_err_int_en", &self.spi_smem_ecc_err_int_en())
+            .field("spi_smem_cs_hold_delay", &self.spi_smem_cs_hold_delay())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_AC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to keep SPI_CS low when MSPI is in PREP state."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/spi_smem_ddr.rs b/esp32s3/src/spi0/spi_smem_ddr.rs
index e8dcdda73f..2f8b50cfca 100644
--- a/esp32s3/src/spi0/spi_smem_ddr.rs
+++ b/esp32s3/src/spi0/spi_smem_ddr.rs
@@ -170,72 +170,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DDR")
-            .field("en", &format_args!("{}", self.en().bit()))
-            .field(
-                "spi_smem_var_dummy",
-                &format_args!("{}", self.spi_smem_var_dummy().bit()),
-            )
-            .field("rdat_swp", &format_args!("{}", self.rdat_swp().bit()))
-            .field("wdat_swp", &format_args!("{}", self.wdat_swp().bit()))
-            .field("cmd_dis", &format_args!("{}", self.cmd_dis().bit()))
-            .field(
-                "spi_smem_outminbytelen",
-                &format_args!("{}", self.spi_smem_outminbytelen().bits()),
-            )
-            .field(
-                "spi_smem_tx_ddr_msk_en",
-                &format_args!("{}", self.spi_smem_tx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_smem_rx_ddr_msk_en",
-                &format_args!("{}", self.spi_smem_rx_ddr_msk_en().bit()),
-            )
-            .field(
-                "spi_smem_usr_ddr_dqs_thd",
-                &format_args!("{}", self.spi_smem_usr_ddr_dqs_thd().bits()),
-            )
-            .field("dqs_loop", &format_args!("{}", self.dqs_loop().bit()))
-            .field(
-                "dqs_loop_mode",
-                &format_args!("{}", self.dqs_loop_mode().bit()),
-            )
-            .field(
-                "spi_smem_clk_diff_en",
-                &format_args!("{}", self.spi_smem_clk_diff_en().bit()),
-            )
-            .field(
-                "spi_smem_hyperbus_mode",
-                &format_args!("{}", self.spi_smem_hyperbus_mode().bit()),
-            )
-            .field(
-                "spi_smem_dqs_ca_in",
-                &format_args!("{}", self.spi_smem_dqs_ca_in().bit()),
-            )
+            .field("en", &self.en())
+            .field("spi_smem_var_dummy", &self.spi_smem_var_dummy())
+            .field("rdat_swp", &self.rdat_swp())
+            .field("wdat_swp", &self.wdat_swp())
+            .field("cmd_dis", &self.cmd_dis())
+            .field("spi_smem_outminbytelen", &self.spi_smem_outminbytelen())
+            .field("spi_smem_tx_ddr_msk_en", &self.spi_smem_tx_ddr_msk_en())
+            .field("spi_smem_rx_ddr_msk_en", &self.spi_smem_rx_ddr_msk_en())
+            .field("spi_smem_usr_ddr_dqs_thd", &self.spi_smem_usr_ddr_dqs_thd())
+            .field("dqs_loop", &self.dqs_loop())
+            .field("dqs_loop_mode", &self.dqs_loop_mode())
+            .field("spi_smem_clk_diff_en", &self.spi_smem_clk_diff_en())
+            .field("spi_smem_hyperbus_mode", &self.spi_smem_hyperbus_mode())
+            .field("spi_smem_dqs_ca_in", &self.spi_smem_dqs_ca_in())
             .field(
                 "spi_smem_hyperbus_dummy_2x",
-                &format_args!("{}", self.spi_smem_hyperbus_dummy_2x().bit()),
-            )
-            .field(
-                "spi_smem_clk_diff_inv",
-                &format_args!("{}", self.spi_smem_clk_diff_inv().bit()),
-            )
-            .field(
-                "spi_smem_octa_ram_addr",
-                &format_args!("{}", self.spi_smem_octa_ram_addr().bit()),
-            )
-            .field(
-                "spi_smem_hyperbus_ca",
-                &format_args!("{}", self.spi_smem_hyperbus_ca().bit()),
+                &self.spi_smem_hyperbus_dummy_2x(),
             )
+            .field("spi_smem_clk_diff_inv", &self.spi_smem_clk_diff_inv())
+            .field("spi_smem_octa_ram_addr", &self.spi_smem_octa_ram_addr())
+            .field("spi_smem_hyperbus_ca", &self.spi_smem_hyperbus_ca())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: in ddr mode, 0 in sdr mode"]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/spi_smem_din_mode.rs b/esp32s3/src/spi0/spi_smem_din_mode.rs
index 3523c676eb..95bc24d638 100644
--- a/esp32s3/src/spi0/spi_smem_din_mode.rs
+++ b/esp32s3/src/spi0/spi_smem_din_mode.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DIN_MODE")
-            .field(
-                "spi_smem_din0_mode",
-                &format_args!("{}", self.spi_smem_din0_mode().bits()),
-            )
-            .field(
-                "spi_smem_din1_mode",
-                &format_args!("{}", self.spi_smem_din1_mode().bits()),
-            )
-            .field(
-                "spi_smem_din2_mode",
-                &format_args!("{}", self.spi_smem_din2_mode().bits()),
-            )
-            .field(
-                "spi_smem_din3_mode",
-                &format_args!("{}", self.spi_smem_din3_mode().bits()),
-            )
-            .field(
-                "spi_smem_din4_mode",
-                &format_args!("{}", self.spi_smem_din4_mode().bits()),
-            )
-            .field(
-                "spi_smem_din5_mode",
-                &format_args!("{}", self.spi_smem_din5_mode().bits()),
-            )
-            .field(
-                "spi_smem_din6_mode",
-                &format_args!("{}", self.spi_smem_din6_mode().bits()),
-            )
-            .field(
-                "spi_smem_din7_mode",
-                &format_args!("{}", self.spi_smem_din7_mode().bits()),
-            )
-            .field(
-                "spi_smem_dins_mode",
-                &format_args!("{}", self.spi_smem_dins_mode().bits()),
-            )
+            .field("spi_smem_din0_mode", &self.spi_smem_din0_mode())
+            .field("spi_smem_din1_mode", &self.spi_smem_din1_mode())
+            .field("spi_smem_din2_mode", &self.spi_smem_din2_mode())
+            .field("spi_smem_din3_mode", &self.spi_smem_din3_mode())
+            .field("spi_smem_din4_mode", &self.spi_smem_din4_mode())
+            .field("spi_smem_din5_mode", &self.spi_smem_din5_mode())
+            .field("spi_smem_din6_mode", &self.spi_smem_din6_mode())
+            .field("spi_smem_din7_mode", &self.spi_smem_din7_mode())
+            .field("spi_smem_dins_mode", &self.spi_smem_dins_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/spi_smem_din_num.rs b/esp32s3/src/spi0/spi_smem_din_num.rs
index 2a187d076e..0aeebc0644 100644
--- a/esp32s3/src/spi0/spi_smem_din_num.rs
+++ b/esp32s3/src/spi0/spi_smem_din_num.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DIN_NUM")
-            .field(
-                "spi_smem_din0_num",
-                &format_args!("{}", self.spi_smem_din0_num().bits()),
-            )
-            .field(
-                "spi_smem_din1_num",
-                &format_args!("{}", self.spi_smem_din1_num().bits()),
-            )
-            .field(
-                "spi_smem_din2_num",
-                &format_args!("{}", self.spi_smem_din2_num().bits()),
-            )
-            .field(
-                "spi_smem_din3_num",
-                &format_args!("{}", self.spi_smem_din3_num().bits()),
-            )
-            .field(
-                "spi_smem_din4_num",
-                &format_args!("{}", self.spi_smem_din4_num().bits()),
-            )
-            .field(
-                "spi_smem_din5_num",
-                &format_args!("{}", self.spi_smem_din5_num().bits()),
-            )
-            .field(
-                "spi_smem_din6_num",
-                &format_args!("{}", self.spi_smem_din6_num().bits()),
-            )
-            .field(
-                "spi_smem_din7_num",
-                &format_args!("{}", self.spi_smem_din7_num().bits()),
-            )
-            .field(
-                "spi_smem_dins_num",
-                &format_args!("{}", self.spi_smem_dins_num().bits()),
-            )
+            .field("spi_smem_din0_num", &self.spi_smem_din0_num())
+            .field("spi_smem_din1_num", &self.spi_smem_din1_num())
+            .field("spi_smem_din2_num", &self.spi_smem_din2_num())
+            .field("spi_smem_din3_num", &self.spi_smem_din3_num())
+            .field("spi_smem_din4_num", &self.spi_smem_din4_num())
+            .field("spi_smem_din5_num", &self.spi_smem_din5_num())
+            .field("spi_smem_din6_num", &self.spi_smem_din6_num())
+            .field("spi_smem_din7_num", &self.spi_smem_din7_num())
+            .field("spi_smem_dins_num", &self.spi_smem_dins_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI_D input delay number."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/spi_smem_dout_mode.rs b/esp32s3/src/spi0/spi_smem_dout_mode.rs
index f9919bdb06..e1a011434f 100644
--- a/esp32s3/src/spi0/spi_smem_dout_mode.rs
+++ b/esp32s3/src/spi0/spi_smem_dout_mode.rs
@@ -89,51 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_DOUT_MODE")
-            .field(
-                "spi_smem_dout0_mode",
-                &format_args!("{}", self.spi_smem_dout0_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout1_mode",
-                &format_args!("{}", self.spi_smem_dout1_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout2_mode",
-                &format_args!("{}", self.spi_smem_dout2_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout3_mode",
-                &format_args!("{}", self.spi_smem_dout3_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout4_mode",
-                &format_args!("{}", self.spi_smem_dout4_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout5_mode",
-                &format_args!("{}", self.spi_smem_dout5_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout6_mode",
-                &format_args!("{}", self.spi_smem_dout6_mode().bit()),
-            )
-            .field(
-                "spi_smem_dout7_mode",
-                &format_args!("{}", self.spi_smem_dout7_mode().bit()),
-            )
-            .field(
-                "spi_smem_douts_mode",
-                &format_args!("{}", self.spi_smem_douts_mode().bit()),
-            )
+            .field("spi_smem_dout0_mode", &self.spi_smem_dout0_mode())
+            .field("spi_smem_dout1_mode", &self.spi_smem_dout1_mode())
+            .field("spi_smem_dout2_mode", &self.spi_smem_dout2_mode())
+            .field("spi_smem_dout3_mode", &self.spi_smem_dout3_mode())
+            .field("spi_smem_dout4_mode", &self.spi_smem_dout4_mode())
+            .field("spi_smem_dout5_mode", &self.spi_smem_dout5_mode())
+            .field("spi_smem_dout6_mode", &self.spi_smem_dout6_mode())
+            .field("spi_smem_dout7_mode", &self.spi_smem_dout7_mode())
+            .field("spi_smem_douts_mode", &self.spi_smem_douts_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/spi_smem_timing_cali.rs b/esp32s3/src/spi0/spi_smem_timing_cali.rs
index d4e0c543bc..f369894f3e 100644
--- a/esp32s3/src/spi0/spi_smem_timing_cali.rs
+++ b/esp32s3/src/spi0/spi_smem_timing_cali.rs
@@ -35,27 +35,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SPI_SMEM_TIMING_CALI")
-            .field(
-                "spi_smem_timing_clk_ena",
-                &format_args!("{}", self.spi_smem_timing_clk_ena().bit()),
-            )
-            .field(
-                "spi_smem_timing_cali",
-                &format_args!("{}", self.spi_smem_timing_cali().bit()),
-            )
+            .field("spi_smem_timing_clk_ena", &self.spi_smem_timing_clk_ena())
+            .field("spi_smem_timing_cali", &self.spi_smem_timing_cali())
             .field(
                 "spi_smem_extra_dummy_cyclelen",
-                &format_args!("{}", self.spi_smem_extra_dummy_cyclelen().bits()),
+                &self.spi_smem_extra_dummy_cyclelen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SPI_SMEM_TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/sram_clk.rs b/esp32s3/src/spi0/sram_clk.rs
index b4d980237f..96fb0b9abe 100644
--- a/esp32s3/src/spi0/sram_clk.rs
+++ b/esp32s3/src/spi0/sram_clk.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_CLK")
-            .field("sclkcnt_l", &format_args!("{}", self.sclkcnt_l().bits()))
-            .field("sclkcnt_h", &format_args!("{}", self.sclkcnt_h().bits()))
-            .field("sclkcnt_n", &format_args!("{}", self.sclkcnt_n().bits()))
-            .field(
-                "sclk_equ_sysclk",
-                &format_args!("{}", self.sclk_equ_sysclk().bit()),
-            )
+            .field("sclkcnt_l", &self.sclkcnt_l())
+            .field("sclkcnt_h", &self.sclkcnt_h())
+            .field("sclkcnt_n", &self.sclkcnt_n())
+            .field("sclk_equ_sysclk", &self.sclk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_CLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - It must equal to the value of SPI_MEM_SCLKCNT_N."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/sram_cmd.rs b/esp32s3/src/spi0/sram_cmd.rs
index ac7882e629..62dfd11ff9 100644
--- a/esp32s3/src/spi0/sram_cmd.rs
+++ b/esp32s3/src/spi0/sram_cmd.rs
@@ -143,30 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SRAM_CMD")
-            .field("sclk_mode", &format_args!("{}", self.sclk_mode().bits()))
-            .field("swb_mode", &format_args!("{}", self.swb_mode().bits()))
-            .field("sdin_dual", &format_args!("{}", self.sdin_dual().bit()))
-            .field("sdout_dual", &format_args!("{}", self.sdout_dual().bit()))
-            .field("saddr_dual", &format_args!("{}", self.saddr_dual().bit()))
-            .field("scmd_dual", &format_args!("{}", self.scmd_dual().bit()))
-            .field("sdin_quad", &format_args!("{}", self.sdin_quad().bit()))
-            .field("sdout_quad", &format_args!("{}", self.sdout_quad().bit()))
-            .field("saddr_quad", &format_args!("{}", self.saddr_quad().bit()))
-            .field("scmd_quad", &format_args!("{}", self.scmd_quad().bit()))
-            .field("sdin_oct", &format_args!("{}", self.sdin_oct().bit()))
-            .field("sdout_oct", &format_args!("{}", self.sdout_oct().bit()))
-            .field("saddr_oct", &format_args!("{}", self.saddr_oct().bit()))
-            .field("scmd_oct", &format_args!("{}", self.scmd_oct().bit()))
-            .field("sdummy_out", &format_args!("{}", self.sdummy_out().bit()))
+            .field("sclk_mode", &self.sclk_mode())
+            .field("swb_mode", &self.swb_mode())
+            .field("sdin_dual", &self.sdin_dual())
+            .field("sdout_dual", &self.sdout_dual())
+            .field("saddr_dual", &self.saddr_dual())
+            .field("scmd_dual", &self.scmd_dual())
+            .field("sdin_quad", &self.sdin_quad())
+            .field("sdout_quad", &self.sdout_quad())
+            .field("saddr_quad", &self.saddr_quad())
+            .field("scmd_quad", &self.scmd_quad())
+            .field("sdin_oct", &self.sdin_oct())
+            .field("sdout_oct", &self.sdout_oct())
+            .field("saddr_oct", &self.saddr_oct())
+            .field("scmd_oct", &self.scmd_oct())
+            .field("sdummy_out", &self.sdummy_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/sram_drd_cmd.rs b/esp32s3/src/spi0/sram_drd_cmd.rs
index d95beef0e6..2529d7b57f 100644
--- a/esp32s3/src/spi0/sram_drd_cmd.rs
+++ b/esp32s3/src/spi0/sram_drd_cmd.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("SRAM_DRD_CMD")
             .field(
                 "cache_sram_usr_rd_cmd_value",
-                &format_args!("{}", self.cache_sram_usr_rd_cmd_value().bits()),
+                &self.cache_sram_usr_rd_cmd_value(),
             )
             .field(
                 "cache_sram_usr_rd_cmd_bitlen",
-                &format_args!("{}", self.cache_sram_usr_rd_cmd_bitlen().bits()),
+                &self.cache_sram_usr_rd_cmd_bitlen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_DRD_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - When SPI0 reads Ext_RAM, it is the command value of CMD phase."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/sram_dwr_cmd.rs b/esp32s3/src/spi0/sram_dwr_cmd.rs
index 1ce2322c48..ca709dc5b2 100644
--- a/esp32s3/src/spi0/sram_dwr_cmd.rs
+++ b/esp32s3/src/spi0/sram_dwr_cmd.rs
@@ -28,21 +28,15 @@ impl core::fmt::Debug for R {
         f.debug_struct("SRAM_DWR_CMD")
             .field(
                 "cache_sram_usr_wr_cmd_value",
-                &format_args!("{}", self.cache_sram_usr_wr_cmd_value().bits()),
+                &self.cache_sram_usr_wr_cmd_value(),
             )
             .field(
                 "cache_sram_usr_wr_cmd_bitlen",
-                &format_args!("{}", self.cache_sram_usr_wr_cmd_bitlen().bits()),
+                &self.cache_sram_usr_wr_cmd_bitlen(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SRAM_DWR_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - When SPI0 writes Ext_RAM, it is the command value of CMD phase."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/timing_cali.rs b/esp32s3/src/spi0/timing_cali.rs
index 2d6ef203ac..21165ff28b 100644
--- a/esp32s3/src/spi0/timing_cali.rs
+++ b/esp32s3/src/spi0/timing_cali.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMING_CALI")
-            .field(
-                "timing_clk_ena",
-                &format_args!("{}", self.timing_clk_ena().bit()),
-            )
-            .field("timing_cali", &format_args!("{}", self.timing_cali().bit()))
-            .field(
-                "extra_dummy_cyclelen",
-                &format_args!("{}", self.extra_dummy_cyclelen().bits()),
-            )
+            .field("timing_clk_ena", &self.timing_clk_ena())
+            .field("timing_cali", &self.timing_cali())
+            .field("extra_dummy_cyclelen", &self.extra_dummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/user.rs b/esp32s3/src/spi0/user.rs
index c19c8d6bae..1687665991 100644
--- a/esp32s3/src/spi0/user.rs
+++ b/esp32s3/src/spi0/user.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
-            .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
+            .field("cs_hold", &self.cs_hold())
+            .field("cs_setup", &self.cs_setup())
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_dummy", &self.usr_dummy())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - Set this bit to keep SPI_CS low when MSPI is in DONE state."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/user1.rs b/esp32s3/src/spi0/user1.rs
index 2ec5124361..41db2f000f 100644
--- a/esp32s3/src/spi0/user1.rs
+++ b/esp32s3/src/spi0/user1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The SPI_CLK cycle length minus 1 of DUMMY phase."]
     #[inline(always)]
diff --git a/esp32s3/src/spi0/user2.rs b/esp32s3/src/spi0/user2.rs
index f42d07a9c9..0f5094dbac 100644
--- a/esp32s3/src/spi0/user2.rs
+++ b/esp32s3/src/spi0/user2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of user defined(USR) command."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/addr.rs b/esp32s3/src/spi1/addr.rs
index 565e7916d4..cc9a0e1b42 100644
--- a/esp32s3/src/spi1/addr.rs
+++ b/esp32s3/src/spi1/addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR")
-            .field(
-                "usr_addr_value",
-                &format_args!("{}", self.usr_addr_value().bits()),
-            )
+            .field("usr_addr_value", &self.usr_addr_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/cache_fctrl.rs b/esp32s3/src/spi1/cache_fctrl.rs
index 74809a7cc5..d886b6bfcc 100644
--- a/esp32s3/src/spi1/cache_fctrl.rs
+++ b/esp32s3/src/spi1/cache_fctrl.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_FCTRL")
-            .field(
-                "cache_usr_cmd_4byte",
-                &format_args!("{}", self.cache_usr_cmd_4byte().bit()),
-            )
-            .field("fdin_dual", &format_args!("{}", self.fdin_dual().bit()))
-            .field("fdout_dual", &format_args!("{}", self.fdout_dual().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("fdin_quad", &format_args!("{}", self.fdin_quad().bit()))
-            .field("fdout_quad", &format_args!("{}", self.fdout_quad().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
+            .field("cache_usr_cmd_4byte", &self.cache_usr_cmd_4byte())
+            .field("fdin_dual", &self.fdin_dual())
+            .field("fdout_dual", &self.fdout_dual())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("fdin_quad", &self.fdin_quad())
+            .field("fdout_quad", &self.fdout_quad())
+            .field("faddr_quad", &self.faddr_quad())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_FCTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/clock.rs b/esp32s3/src/spi1/clock.rs
index 53d8a45b7b..6640cb5d91 100644
--- a/esp32s3/src/spi1/clock.rs
+++ b/esp32s3/src/spi1/clock.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - It must equal to the value of SPI_MEM_CLKCNT_N."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/clock_gate.rs b/esp32s3/src/spi1/clock_gate.rs
index c60d396767..69477e9842 100644
--- a/esp32s3/src/spi1/clock_gate.rs
+++ b/esp32s3/src/spi1/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Register clock gate enable signal. 1: Enable. 0: Disable."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/cmd.rs b/esp32s3/src/spi1/cmd.rs
index b073ac4616..00e23387dc 100644
--- a/esp32s3/src/spi1/cmd.rs
+++ b/esp32s3/src/spi1/cmd.rs
@@ -143,30 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field("flash_pe", &format_args!("{}", self.flash_pe().bit()))
-            .field("usr", &format_args!("{}", self.usr().bit()))
-            .field("flash_hpm", &format_args!("{}", self.flash_hpm().bit()))
-            .field("flash_res", &format_args!("{}", self.flash_res().bit()))
-            .field("flash_dp", &format_args!("{}", self.flash_dp().bit()))
-            .field("flash_ce", &format_args!("{}", self.flash_ce().bit()))
-            .field("flash_be", &format_args!("{}", self.flash_be().bit()))
-            .field("flash_se", &format_args!("{}", self.flash_se().bit()))
-            .field("flash_pp", &format_args!("{}", self.flash_pp().bit()))
-            .field("flash_wrsr", &format_args!("{}", self.flash_wrsr().bit()))
-            .field("flash_rdsr", &format_args!("{}", self.flash_rdsr().bit()))
-            .field("flash_rdid", &format_args!("{}", self.flash_rdid().bit()))
-            .field("flash_wrdi", &format_args!("{}", self.flash_wrdi().bit()))
-            .field("flash_wren", &format_args!("{}", self.flash_wren().bit()))
-            .field("flash_read", &format_args!("{}", self.flash_read().bit()))
+            .field("flash_pe", &self.flash_pe())
+            .field("usr", &self.usr())
+            .field("flash_hpm", &self.flash_hpm())
+            .field("flash_res", &self.flash_res())
+            .field("flash_dp", &self.flash_dp())
+            .field("flash_ce", &self.flash_ce())
+            .field("flash_be", &self.flash_be())
+            .field("flash_se", &self.flash_se())
+            .field("flash_pp", &self.flash_pp())
+            .field("flash_wrsr", &self.flash_wrsr())
+            .field("flash_rdsr", &self.flash_rdsr())
+            .field("flash_rdid", &self.flash_rdid())
+            .field("flash_wrdi", &self.flash_wrdi())
+            .field("flash_wren", &self.flash_wren())
+            .field("flash_read", &self.flash_read())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 17 - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/ctrl.rs b/esp32s3/src/spi1/ctrl.rs
index 80f7f9dbda..62b4ee1b7c 100644
--- a/esp32s3/src/spi1/ctrl.rs
+++ b/esp32s3/src/spi1/ctrl.rs
@@ -179,34 +179,28 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("fdummy_out", &format_args!("{}", self.fdummy_out().bit()))
-            .field("fdout_oct", &format_args!("{}", self.fdout_oct().bit()))
-            .field("fdin_oct", &format_args!("{}", self.fdin_oct().bit()))
-            .field("faddr_oct", &format_args!("{}", self.faddr_oct().bit()))
-            .field("fcmd_dual", &format_args!("{}", self.fcmd_dual().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcmd_oct", &format_args!("{}", self.fcmd_oct().bit()))
-            .field("fcs_crc_en", &format_args!("{}", self.fcs_crc_en().bit()))
-            .field("tx_crc_en", &format_args!("{}", self.tx_crc_en().bit()))
-            .field("fastrd_mode", &format_args!("{}", self.fastrd_mode().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("resandres", &format_args!("{}", self.resandres().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("wp", &format_args!("{}", self.wp().bit()))
-            .field("wrsr_2b", &format_args!("{}", self.wrsr_2b().bit()))
-            .field("fread_dio", &format_args!("{}", self.fread_dio().bit()))
-            .field("fread_qio", &format_args!("{}", self.fread_qio().bit()))
+            .field("fdummy_out", &self.fdummy_out())
+            .field("fdout_oct", &self.fdout_oct())
+            .field("fdin_oct", &self.fdin_oct())
+            .field("faddr_oct", &self.faddr_oct())
+            .field("fcmd_dual", &self.fcmd_dual())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcmd_oct", &self.fcmd_oct())
+            .field("fcs_crc_en", &self.fcs_crc_en())
+            .field("tx_crc_en", &self.tx_crc_en())
+            .field("fastrd_mode", &self.fastrd_mode())
+            .field("fread_dual", &self.fread_dual())
+            .field("resandres", &self.resandres())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("fread_quad", &self.fread_quad())
+            .field("wp", &self.wp())
+            .field("wrsr_2b", &self.wrsr_2b())
+            .field("fread_dio", &self.fread_dio())
+            .field("fread_qio", &self.fread_qio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/ctrl1.rs b/esp32s3/src/spi1/ctrl1.rs
index f5eb960a90..cbfa6038e4 100644
--- a/esp32s3/src/spi1/ctrl1.rs
+++ b/esp32s3/src/spi1/ctrl1.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL1")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
-            .field(
-                "cs_hold_dly_res",
-                &format_args!("{}", self.cs_hold_dly_res().bits()),
-            )
+            .field("clk_mode", &self.clk_mode())
+            .field("cs_hold_dly_res", &self.cs_hold_dly_res())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/ctrl2.rs b/esp32s3/src/spi1/ctrl2.rs
index 05c9519d0f..1b9b5186ca 100644
--- a/esp32s3/src/spi1/ctrl2.rs
+++ b/esp32s3/src/spi1/ctrl2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL2")
-            .field("sync_reset", &format_args!("{}", self.sync_reset().bit()))
+            .field("sync_reset", &self.sync_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - The FSM will be reset."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/date.rs b/esp32s3/src/spi1/date.rs
index 8428d7237e..f9fab98f87 100644
--- a/esp32s3/src/spi1/date.rs
+++ b/esp32s3/src/spi1/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/spi1/ddr.rs b/esp32s3/src/spi1/ddr.rs
index bf41025002..bfdbf058de 100644
--- a/esp32s3/src/spi1/ddr.rs
+++ b/esp32s3/src/spi1/ddr.rs
@@ -152,79 +152,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DDR")
-            .field(
-                "spi_fmem_ddr_en",
-                &format_args!("{}", self.spi_fmem_ddr_en().bit()),
-            )
-            .field(
-                "spi_fmem_var_dummy",
-                &format_args!("{}", self.spi_fmem_var_dummy().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_rdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_rdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_wdat_swp",
-                &format_args!("{}", self.spi_fmem_ddr_wdat_swp().bit()),
-            )
-            .field(
-                "spi_fmem_ddr_cmd_dis",
-                &format_args!("{}", self.spi_fmem_ddr_cmd_dis().bit()),
-            )
-            .field(
-                "spi_fmem_outminbytelen",
-                &format_args!("{}", self.spi_fmem_outminbytelen().bits()),
-            )
-            .field(
-                "spi_fmem_usr_ddr_dqs_thd",
-                &format_args!("{}", self.spi_fmem_usr_ddr_dqs_thd().bits()),
-            )
-            .field(
-                "spi_fmem_ddr_dqs_loop",
-                &format_args!("{}", self.spi_fmem_ddr_dqs_loop().bit()),
-            )
+            .field("spi_fmem_ddr_en", &self.spi_fmem_ddr_en())
+            .field("spi_fmem_var_dummy", &self.spi_fmem_var_dummy())
+            .field("spi_fmem_ddr_rdat_swp", &self.spi_fmem_ddr_rdat_swp())
+            .field("spi_fmem_ddr_wdat_swp", &self.spi_fmem_ddr_wdat_swp())
+            .field("spi_fmem_ddr_cmd_dis", &self.spi_fmem_ddr_cmd_dis())
+            .field("spi_fmem_outminbytelen", &self.spi_fmem_outminbytelen())
+            .field("spi_fmem_usr_ddr_dqs_thd", &self.spi_fmem_usr_ddr_dqs_thd())
+            .field("spi_fmem_ddr_dqs_loop", &self.spi_fmem_ddr_dqs_loop())
             .field(
                 "spi_fmem_ddr_dqs_loop_mode",
-                &format_args!("{}", self.spi_fmem_ddr_dqs_loop_mode().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_en",
-                &format_args!("{}", self.spi_fmem_clk_diff_en().bit()),
-            )
-            .field(
-                "spi_fmem_hyperbus_mode",
-                &format_args!("{}", self.spi_fmem_hyperbus_mode().bit()),
-            )
-            .field(
-                "spi_fmem_dqs_ca_in",
-                &format_args!("{}", self.spi_fmem_dqs_ca_in().bit()),
+                &self.spi_fmem_ddr_dqs_loop_mode(),
             )
+            .field("spi_fmem_clk_diff_en", &self.spi_fmem_clk_diff_en())
+            .field("spi_fmem_hyperbus_mode", &self.spi_fmem_hyperbus_mode())
+            .field("spi_fmem_dqs_ca_in", &self.spi_fmem_dqs_ca_in())
             .field(
                 "spi_fmem_hyperbus_dummy_2x",
-                &format_args!("{}", self.spi_fmem_hyperbus_dummy_2x().bit()),
-            )
-            .field(
-                "spi_fmem_clk_diff_inv",
-                &format_args!("{}", self.spi_fmem_clk_diff_inv().bit()),
-            )
-            .field(
-                "spi_fmem_octa_ram_addr",
-                &format_args!("{}", self.spi_fmem_octa_ram_addr().bit()),
-            )
-            .field(
-                "spi_fmem_hyperbus_ca",
-                &format_args!("{}", self.spi_fmem_hyperbus_ca().bit()),
+                &self.spi_fmem_hyperbus_dummy_2x(),
             )
+            .field("spi_fmem_clk_diff_inv", &self.spi_fmem_clk_diff_inv())
+            .field("spi_fmem_octa_ram_addr", &self.spi_fmem_octa_ram_addr())
+            .field("spi_fmem_hyperbus_ca", &self.spi_fmem_hyperbus_ca())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: in DDR mode, 0: in SDR mode."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/ext_addr.rs b/esp32s3/src/spi1/ext_addr.rs
index aab7960a3f..6e9c1085f5 100644
--- a/esp32s3/src/spi1/ext_addr.rs
+++ b/esp32s3/src/spi1/ext_addr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EXT_ADDR")
-            .field("ext_addr", &format_args!("{}", self.ext_addr().bits()))
+            .field("ext_addr", &self.ext_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXT_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - The register are the higher 32bits in the 64 bits address mode."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/flash_sus_cmd.rs b/esp32s3/src/spi1/flash_sus_cmd.rs
index 514ae5707e..fd673e2d8b 100644
--- a/esp32s3/src/spi1/flash_sus_cmd.rs
+++ b/esp32s3/src/spi1/flash_sus_cmd.rs
@@ -62,30 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_SUS_CMD")
-            .field("flash_per", &format_args!("{}", self.flash_per().bit()))
-            .field("flash_pes", &format_args!("{}", self.flash_pes().bit()))
-            .field(
-                "flash_per_wait_en",
-                &format_args!("{}", self.flash_per_wait_en().bit()),
-            )
-            .field(
-                "flash_pes_wait_en",
-                &format_args!("{}", self.flash_pes_wait_en().bit()),
-            )
-            .field("pes_per_en", &format_args!("{}", self.pes_per_en().bit()))
-            .field(
-                "pesr_idle_en",
-                &format_args!("{}", self.pesr_idle_en().bit()),
-            )
+            .field("flash_per", &self.flash_per())
+            .field("flash_pes", &self.flash_pes())
+            .field("flash_per_wait_en", &self.flash_per_wait_en())
+            .field("flash_pes_wait_en", &self.flash_pes_wait_en())
+            .field("pes_per_en", &self.pes_per_en())
+            .field("pesr_idle_en", &self.pesr_idle_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_SUS_CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/flash_sus_ctrl.rs b/esp32s3/src/spi1/flash_sus_ctrl.rs
index c9e5418629..284802fb7a 100644
--- a/esp32s3/src/spi1/flash_sus_ctrl.rs
+++ b/esp32s3/src/spi1/flash_sus_ctrl.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_SUS_CTRL")
-            .field(
-                "flash_pes_en",
-                &format_args!("{}", self.flash_pes_en().bit()),
-            )
-            .field(
-                "flash_per_command",
-                &format_args!("{}", self.flash_per_command().bits()),
-            )
-            .field(
-                "flash_pes_command",
-                &format_args!("{}", self.flash_pes_command().bits()),
-            )
+            .field("flash_pes_en", &self.flash_pes_en())
+            .field("flash_per_command", &self.flash_per_command())
+            .field("flash_pes_command", &self.flash_pes_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_SUS_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable auto-suspend function."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/flash_waiti_ctrl.rs b/esp32s3/src/spi1/flash_waiti_ctrl.rs
index f85bbccd23..9def4f353e 100644
--- a/esp32s3/src/spi1/flash_waiti_ctrl.rs
+++ b/esp32s3/src/spi1/flash_waiti_ctrl.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLASH_WAITI_CTRL")
-            .field("waiti_en", &format_args!("{}", self.waiti_en().bit()))
-            .field("waiti_dummy", &format_args!("{}", self.waiti_dummy().bit()))
-            .field("waiti_cmd", &format_args!("{}", self.waiti_cmd().bits()))
-            .field(
-                "waiti_dummy_cyclelen",
-                &format_args!("{}", self.waiti_dummy_cyclelen().bits()),
-            )
+            .field("waiti_en", &self.waiti_en())
+            .field("waiti_dummy", &self.waiti_dummy())
+            .field("waiti_cmd", &self.waiti_cmd())
+            .field("waiti_dummy_cyclelen", &self.waiti_dummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLASH_WAITI_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/fsm.rs b/esp32s3/src/spi1/fsm.rs
index 79c4a39ef1..d59ea58deb 100644
--- a/esp32s3/src/spi1/fsm.rs
+++ b/esp32s3/src/spi1/fsm.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("FSM")
-            .field("st", &format_args!("{}", self.st().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("FSM").field("st", &self.st()).finish()
     }
 }
 #[doc = "SPI1 state machine(FSM) status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s3/src/spi1/int_ena.rs b/esp32s3/src/spi1/int_ena.rs
index b9761f7394..9a37af00d5 100644
--- a/esp32s3/src/spi1/int_ena.rs
+++ b/esp32s3/src/spi1/int_ena.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field(
-                "total_trans_end",
-                &format_args!("{}", self.total_trans_end().bit()),
-            )
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("total_trans_end", &self.total_trans_end())
+            .field("brown_out", &self.brown_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for SPI_MEM_PER_END_INT interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/int_raw.rs b/esp32s3/src/spi1/int_raw.rs
index e1145e2943..1bc131f01c 100644
--- a/esp32s3/src/spi1/int_raw.rs
+++ b/esp32s3/src/spi1/int_raw.rs
@@ -44,22 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field(
-                "total_trans_end",
-                &format_args!("{}", self.total_trans_end().bit()),
-            )
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("total_trans_end", &self.total_trans_end())
+            .field("brown_out", &self.brown_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/int_st.rs b/esp32s3/src/spi1/int_st.rs
index d8f59b4f83..ac7477c646 100644
--- a/esp32s3/src/spi1/int_st.rs
+++ b/esp32s3/src/spi1/int_st.rs
@@ -34,22 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("per_end", &format_args!("{}", self.per_end().bit()))
-            .field("pes_end", &format_args!("{}", self.pes_end().bit()))
-            .field(
-                "total_trans_end",
-                &format_args!("{}", self.total_trans_end().bit()),
-            )
-            .field("brown_out", &format_args!("{}", self.brown_out().bit()))
+            .field("per_end", &self.per_end())
+            .field("pes_end", &self.pes_end())
+            .field("total_trans_end", &self.total_trans_end())
+            .field("brown_out", &self.brown_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/spi1/misc.rs b/esp32s3/src/spi1/misc.rs
index 7481656afe..5bb89d9e3b 100644
--- a/esp32s3/src/spi1/misc.rs
+++ b/esp32s3/src/spi1/misc.rs
@@ -53,26 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
-            .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
-            .field("auto_per", &format_args!("{}", self.auto_per().bit()))
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
+            .field("auto_per", &self.auto_per())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer starts."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/miso_dlen.rs b/esp32s3/src/spi1/miso_dlen.rs
index b8b98ca090..ec49314d2a 100644
--- a/esp32s3/src/spi1/miso_dlen.rs
+++ b/esp32s3/src/spi1/miso_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISO_DLEN")
-            .field(
-                "usr_miso_dbitlen",
-                &format_args!("{}", self.usr_miso_dbitlen().bits()),
-            )
+            .field("usr_miso_dbitlen", &self.usr_miso_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISO_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The length in bits of DIN phase. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/mosi_dlen.rs b/esp32s3/src/spi1/mosi_dlen.rs
index b7b4db1261..fdf0a5bbd8 100644
--- a/esp32s3/src/spi1/mosi_dlen.rs
+++ b/esp32s3/src/spi1/mosi_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MOSI_DLEN")
-            .field(
-                "usr_mosi_dbitlen",
-                &format_args!("{}", self.usr_mosi_dbitlen().bits()),
-            )
+            .field("usr_mosi_dbitlen", &self.usr_mosi_dbitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MOSI_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The length in bits of DOUT phase. The register value shall be (bit_num-1)."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/rd_status.rs b/esp32s3/src/spi1/rd_status.rs
index a9fc3caed3..d22ab4419d 100644
--- a/esp32s3/src/spi1/rd_status.rs
+++ b/esp32s3/src/spi1/rd_status.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RD_STATUS")
-            .field("status", &format_args!("{}", self.status().bits()))
-            .field("wb_mode", &format_args!("{}", self.wb_mode().bits()))
+            .field("status", &self.status())
+            .field("wb_mode", &self.wb_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RD_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/sus_status.rs b/esp32s3/src/spi1/sus_status.rs
index 029e14c7be..10c82084d4 100644
--- a/esp32s3/src/spi1/sus_status.rs
+++ b/esp32s3/src/spi1/sus_status.rs
@@ -62,36 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SUS_STATUS")
-            .field("flash_sus", &format_args!("{}", self.flash_sus().bit()))
-            .field(
-                "flash_hpm_dly_256",
-                &format_args!("{}", self.flash_hpm_dly_256().bit()),
-            )
-            .field(
-                "flash_res_dly_256",
-                &format_args!("{}", self.flash_res_dly_256().bit()),
-            )
-            .field(
-                "flash_dp_dly_256",
-                &format_args!("{}", self.flash_dp_dly_256().bit()),
-            )
-            .field(
-                "flash_per_dly_256",
-                &format_args!("{}", self.flash_per_dly_256().bit()),
-            )
-            .field(
-                "flash_pes_dly_256",
-                &format_args!("{}", self.flash_pes_dly_256().bit()),
-            )
+            .field("flash_sus", &self.flash_sus())
+            .field("flash_hpm_dly_256", &self.flash_hpm_dly_256())
+            .field("flash_res_dly_256", &self.flash_res_dly_256())
+            .field("flash_dp_dly_256", &self.flash_dp_dly_256())
+            .field("flash_per_dly_256", &self.flash_per_dly_256())
+            .field("flash_pes_dly_256", &self.flash_pes_dly_256())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SUS_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/timing_cali.rs b/esp32s3/src/spi1/timing_cali.rs
index 0bde6483fb..0ee23ace52 100644
--- a/esp32s3/src/spi1/timing_cali.rs
+++ b/esp32s3/src/spi1/timing_cali.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TIMING_CALI")
-            .field("timing_cali", &format_args!("{}", self.timing_cali().bit()))
-            .field(
-                "extra_dummy_cyclelen",
-                &format_args!("{}", self.extra_dummy_cyclelen().bits()),
-            )
+            .field("timing_cali", &self.timing_cali())
+            .field("extra_dummy_cyclelen", &self.extra_dummy_cyclelen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TIMING_CALI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1 - Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/tx_crc.rs b/esp32s3/src/spi1/tx_crc.rs
index bb49beae13..6b97e08bfe 100644
--- a/esp32s3/src/spi1/tx_crc.rs
+++ b/esp32s3/src/spi1/tx_crc.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_CRC")
-            .field("data", &format_args!("{}", self.data().bits()))
+            .field("data", &self.data())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_CRC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI1 CRC data register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx_crc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TX_CRC_SPEC;
 impl crate::RegisterSpec for TX_CRC_SPEC {
diff --git a/esp32s3/src/spi1/user.rs b/esp32s3/src/spi1/user.rs
index b61c697c73..f7f2656166 100644
--- a/esp32s3/src/spi1/user.rs
+++ b/esp32s3/src/spi1/user.rs
@@ -125,37 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
-            .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
-            .field("fwrite_dio", &format_args!("{}", self.fwrite_dio().bit()))
-            .field("fwrite_qio", &format_args!("{}", self.fwrite_qio().bit()))
-            .field(
-                "usr_miso_highpart",
-                &format_args!("{}", self.usr_miso_highpart().bit()),
-            )
-            .field(
-                "usr_mosi_highpart",
-                &format_args!("{}", self.usr_mosi_highpart().bit()),
-            )
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
-            .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
-            .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
-            .field("usr_command", &format_args!("{}", self.usr_command().bit()))
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("fwrite_dual", &self.fwrite_dual())
+            .field("fwrite_quad", &self.fwrite_quad())
+            .field("fwrite_dio", &self.fwrite_dio())
+            .field("fwrite_qio", &self.fwrite_qio())
+            .field("usr_miso_highpart", &self.usr_miso_highpart())
+            .field("usr_mosi_highpart", &self.usr_mosi_highpart())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_mosi", &self.usr_mosi())
+            .field("usr_miso", &self.usr_miso())
+            .field("usr_dummy", &self.usr_dummy())
+            .field("usr_addr", &self.usr_addr())
+            .field("usr_command", &self.usr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/user1.rs b/esp32s3/src/spi1/user1.rs
index f3fcebb5a1..31af334c20 100644
--- a/esp32s3/src/spi1/user1.rs
+++ b/esp32s3/src/spi1/user1.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The SPI_CLK cycle length minus 1 of DUMMY phase."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/user2.rs b/esp32s3/src/spi1/user2.rs
index 41d4d3541d..5e9f4dc4b1 100644
--- a/esp32s3/src/spi1/user2.rs
+++ b/esp32s3/src/spi1/user2.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of user defined(USR) command."]
     #[inline(always)]
diff --git a/esp32s3/src/spi1/w.rs b/esp32s3/src/spi1/w.rs
index 319a8e0611..43137019f7 100644
--- a/esp32s3/src/spi1/w.rs
+++ b/esp32s3/src/spi1/w.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("W")
-            .field("buf", &format_args!("{}", self.buf().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<W_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("W").field("buf", &self.buf()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/spi2/addr.rs b/esp32s3/src/spi2/addr.rs
index 0429f136d3..a43f100c19 100644
--- a/esp32s3/src/spi2/addr.rs
+++ b/esp32s3/src/spi2/addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ADDR")
-            .field(
-                "usr_addr_value",
-                &format_args!("{}", self.usr_addr_value().bits()),
-            )
+            .field("usr_addr_value", &self.usr_addr_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Address to slave. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/clk_gate.rs b/esp32s3/src/spi2/clk_gate.rs
index c690702c68..c633026011 100644
--- a/esp32s3/src/spi2/clk_gate.rs
+++ b/esp32s3/src/spi2/clk_gate.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "mst_clk_active",
-                &format_args!("{}", self.mst_clk_active().bit()),
-            )
-            .field("mst_clk_sel", &format_args!("{}", self.mst_clk_sel().bit()))
+            .field("clk_en", &self.clk_en())
+            .field("mst_clk_active", &self.mst_clk_active())
+            .field("mst_clk_sel", &self.mst_clk_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable clk gate"]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/clock.rs b/esp32s3/src/spi2/clock.rs
index a980aa1ac0..336dc15885 100644
--- a/esp32s3/src/spi2/clock.rs
+++ b/esp32s3/src/spi2/clock.rs
@@ -53,23 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK")
-            .field("clkcnt_l", &format_args!("{}", self.clkcnt_l().bits()))
-            .field("clkcnt_h", &format_args!("{}", self.clkcnt_h().bits()))
-            .field("clkcnt_n", &format_args!("{}", self.clkcnt_n().bits()))
-            .field("clkdiv_pre", &format_args!("{}", self.clkdiv_pre().bits()))
-            .field(
-                "clk_equ_sysclk",
-                &format_args!("{}", self.clk_equ_sysclk().bit()),
-            )
+            .field("clkcnt_l", &self.clkcnt_l())
+            .field("clkcnt_h", &self.clkcnt_h())
+            .field("clkcnt_n", &self.clkcnt_n())
+            .field("clkdiv_pre", &self.clkdiv_pre())
+            .field("clk_equ_sysclk", &self.clk_equ_sysclk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/cmd.rs b/esp32s3/src/spi2/cmd.rs
index d9c54a966c..8d8333ec63 100644
--- a/esp32s3/src/spi2/cmd.rs
+++ b/esp32s3/src/spi2/cmd.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CMD")
-            .field(
-                "conf_bitlen",
-                &format_args!("{}", self.conf_bitlen().bits()),
-            )
-            .field("update", &format_args!("{}", self.update().bit()))
-            .field("usr", &format_args!("{}", self.usr().bit()))
+            .field("conf_bitlen", &self.conf_bitlen())
+            .field("update", &self.update())
+            .field("usr", &self.usr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - Define the APB cycles of SPI_CONF state. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/ctrl.rs b/esp32s3/src/spi2/ctrl.rs
index bc2023770e..7975686bec 100644
--- a/esp32s3/src/spi2/ctrl.rs
+++ b/esp32s3/src/spi2/ctrl.rs
@@ -152,37 +152,25 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CTRL")
-            .field("dummy_out", &format_args!("{}", self.dummy_out().bit()))
-            .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
-            .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
-            .field("faddr_oct", &format_args!("{}", self.faddr_oct().bit()))
-            .field("fcmd_dual", &format_args!("{}", self.fcmd_dual().bit()))
-            .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
-            .field("fcmd_oct", &format_args!("{}", self.fcmd_oct().bit()))
-            .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
-            .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
-            .field("fread_oct", &format_args!("{}", self.fread_oct().bit()))
-            .field("q_pol", &format_args!("{}", self.q_pol().bit()))
-            .field("d_pol", &format_args!("{}", self.d_pol().bit()))
-            .field("hold_pol", &format_args!("{}", self.hold_pol().bit()))
-            .field("wp_pol", &format_args!("{}", self.wp_pol().bit()))
-            .field(
-                "rd_bit_order",
-                &format_args!("{}", self.rd_bit_order().bits()),
-            )
-            .field(
-                "wr_bit_order",
-                &format_args!("{}", self.wr_bit_order().bits()),
-            )
+            .field("dummy_out", &self.dummy_out())
+            .field("faddr_dual", &self.faddr_dual())
+            .field("faddr_quad", &self.faddr_quad())
+            .field("faddr_oct", &self.faddr_oct())
+            .field("fcmd_dual", &self.fcmd_dual())
+            .field("fcmd_quad", &self.fcmd_quad())
+            .field("fcmd_oct", &self.fcmd_oct())
+            .field("fread_dual", &self.fread_dual())
+            .field("fread_quad", &self.fread_quad())
+            .field("fread_oct", &self.fread_oct())
+            .field("q_pol", &self.q_pol())
+            .field("d_pol", &self.d_pol())
+            .field("hold_pol", &self.hold_pol())
+            .field("wp_pol", &self.wp_pol())
+            .field("rd_bit_order", &self.rd_bit_order())
+            .field("wr_bit_order", &self.wr_bit_order())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 3 - 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/date.rs b/esp32s3/src/spi2/date.rs
index 2cd9dd3355..b6d21e396c 100644
--- a/esp32s3/src/spi2/date.rs
+++ b/esp32s3/src/spi2/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/spi2/din_mode.rs b/esp32s3/src/spi2/din_mode.rs
index 15a342ed62..b9070e3d49 100644
--- a/esp32s3/src/spi2/din_mode.rs
+++ b/esp32s3/src/spi2/din_mode.rs
@@ -89,27 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_MODE")
-            .field("din0_mode", &format_args!("{}", self.din0_mode().bits()))
-            .field("din1_mode", &format_args!("{}", self.din1_mode().bits()))
-            .field("din2_mode", &format_args!("{}", self.din2_mode().bits()))
-            .field("din3_mode", &format_args!("{}", self.din3_mode().bits()))
-            .field("din4_mode", &format_args!("{}", self.din4_mode().bits()))
-            .field("din5_mode", &format_args!("{}", self.din5_mode().bits()))
-            .field("din6_mode", &format_args!("{}", self.din6_mode().bits()))
-            .field("din7_mode", &format_args!("{}", self.din7_mode().bits()))
-            .field(
-                "timing_hclk_active",
-                &format_args!("{}", self.timing_hclk_active().bit()),
-            )
+            .field("din0_mode", &self.din0_mode())
+            .field("din1_mode", &self.din1_mode())
+            .field("din2_mode", &self.din2_mode())
+            .field("din3_mode", &self.din3_mode())
+            .field("din4_mode", &self.din4_mode())
+            .field("din5_mode", &self.din5_mode())
+            .field("din6_mode", &self.din6_mode())
+            .field("din7_mode", &self.din7_mode())
+            .field("timing_hclk_active", &self.timing_hclk_active())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/din_num.rs b/esp32s3/src/spi2/din_num.rs
index f79a2dedc3..1b29c8976d 100644
--- a/esp32s3/src/spi2/din_num.rs
+++ b/esp32s3/src/spi2/din_num.rs
@@ -80,23 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIN_NUM")
-            .field("din0_num", &format_args!("{}", self.din0_num().bits()))
-            .field("din1_num", &format_args!("{}", self.din1_num().bits()))
-            .field("din2_num", &format_args!("{}", self.din2_num().bits()))
-            .field("din3_num", &format_args!("{}", self.din3_num().bits()))
-            .field("din4_num", &format_args!("{}", self.din4_num().bits()))
-            .field("din5_num", &format_args!("{}", self.din5_num().bits()))
-            .field("din6_num", &format_args!("{}", self.din6_num().bits()))
-            .field("din7_num", &format_args!("{}", self.din7_num().bits()))
+            .field("din0_num", &self.din0_num())
+            .field("din1_num", &self.din1_num())
+            .field("din2_num", &self.din2_num())
+            .field("din3_num", &self.din3_num())
+            .field("din4_num", &self.din4_num())
+            .field("din5_num", &self.din5_num())
+            .field("din6_num", &self.din6_num())
+            .field("din7_num", &self.din7_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIN_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/dma_conf.rs b/esp32s3/src/spi2/dma_conf.rs
index 2c8ad8198f..573e0e214e 100644
--- a/esp32s3/src/spi2/dma_conf.rs
+++ b/esp32s3/src/spi2/dma_conf.rs
@@ -82,38 +82,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_CONF")
-            .field(
-                "dma_outfifo_empty",
-                &format_args!("{}", self.dma_outfifo_empty().bit()),
-            )
-            .field(
-                "dma_infifo_full",
-                &format_args!("{}", self.dma_infifo_full().bit()),
-            )
-            .field(
-                "dma_slv_seg_trans_en",
-                &format_args!("{}", self.dma_slv_seg_trans_en().bit()),
-            )
-            .field(
-                "slv_rx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_rx_seg_trans_clr_en().bit()),
-            )
-            .field(
-                "slv_tx_seg_trans_clr_en",
-                &format_args!("{}", self.slv_tx_seg_trans_clr_en().bit()),
-            )
-            .field("rx_eof_en", &format_args!("{}", self.rx_eof_en().bit()))
-            .field("dma_rx_ena", &format_args!("{}", self.dma_rx_ena().bit()))
-            .field("dma_tx_ena", &format_args!("{}", self.dma_tx_ena().bit()))
+            .field("dma_outfifo_empty", &self.dma_outfifo_empty())
+            .field("dma_infifo_full", &self.dma_infifo_full())
+            .field("dma_slv_seg_trans_en", &self.dma_slv_seg_trans_en())
+            .field("slv_rx_seg_trans_clr_en", &self.slv_rx_seg_trans_clr_en())
+            .field("slv_tx_seg_trans_clr_en", &self.slv_tx_seg_trans_clr_en())
+            .field("rx_eof_en", &self.rx_eof_en())
+            .field("dma_rx_ena", &self.dma_rx_ena())
+            .field("dma_tx_ena", &self.dma_tx_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/dma_int_ena.rs b/esp32s3/src/spi2/dma_int_ena.rs
index 5a2520a556..57d74d21ae 100644
--- a/esp32s3/src/spi2/dma_int_ena.rs
+++ b/esp32s3/src/spi2/dma_int_ena.rs
@@ -197,69 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ENA")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/dma_int_raw.rs b/esp32s3/src/spi2/dma_int_raw.rs
index 4e27e4ae69..c8e69e9935 100644
--- a/esp32s3/src/spi2/dma_int_raw.rs
+++ b/esp32s3/src/spi2/dma_int_raw.rs
@@ -197,69 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_RAW")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/dma_int_st.rs b/esp32s3/src/spi2/dma_int_st.rs
index 424ec36870..5143fbdd5e 100644
--- a/esp32s3/src/spi2/dma_int_st.rs
+++ b/esp32s3/src/spi2/dma_int_st.rs
@@ -153,69 +153,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA_INT_ST")
-            .field(
-                "dma_infifo_full_err",
-                &format_args!("{}", self.dma_infifo_full_err().bit()),
-            )
-            .field(
-                "dma_outfifo_empty_err",
-                &format_args!("{}", self.dma_outfifo_empty_err().bit()),
-            )
-            .field("slv_ex_qpi", &format_args!("{}", self.slv_ex_qpi().bit()))
-            .field("slv_en_qpi", &format_args!("{}", self.slv_en_qpi().bit()))
-            .field("slv_cmd7", &format_args!("{}", self.slv_cmd7().bit()))
-            .field("slv_cmd8", &format_args!("{}", self.slv_cmd8().bit()))
-            .field("slv_cmd9", &format_args!("{}", self.slv_cmd9().bit()))
-            .field("slv_cmda", &format_args!("{}", self.slv_cmda().bit()))
-            .field(
-                "slv_rd_dma_done",
-                &format_args!("{}", self.slv_rd_dma_done().bit()),
-            )
-            .field(
-                "slv_wr_dma_done",
-                &format_args!("{}", self.slv_wr_dma_done().bit()),
-            )
-            .field(
-                "slv_rd_buf_done",
-                &format_args!("{}", self.slv_rd_buf_done().bit()),
-            )
-            .field(
-                "slv_wr_buf_done",
-                &format_args!("{}", self.slv_wr_buf_done().bit()),
-            )
-            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
-            .field(
-                "dma_seg_trans_done",
-                &format_args!("{}", self.dma_seg_trans_done().bit()),
-            )
-            .field(
-                "seg_magic_err",
-                &format_args!("{}", self.seg_magic_err().bit()),
-            )
-            .field(
-                "slv_buf_addr_err",
-                &format_args!("{}", self.slv_buf_addr_err().bit()),
-            )
-            .field("slv_cmd_err", &format_args!("{}", self.slv_cmd_err().bit()))
-            .field(
-                "mst_rx_afifo_wfull_err",
-                &format_args!("{}", self.mst_rx_afifo_wfull_err().bit()),
-            )
-            .field(
-                "mst_tx_afifo_rempty_err",
-                &format_args!("{}", self.mst_tx_afifo_rempty_err().bit()),
-            )
-            .field("app2", &format_args!("{}", self.app2().bit()))
-            .field("app1", &format_args!("{}", self.app1().bit()))
+            .field("dma_infifo_full_err", &self.dma_infifo_full_err())
+            .field("dma_outfifo_empty_err", &self.dma_outfifo_empty_err())
+            .field("slv_ex_qpi", &self.slv_ex_qpi())
+            .field("slv_en_qpi", &self.slv_en_qpi())
+            .field("slv_cmd7", &self.slv_cmd7())
+            .field("slv_cmd8", &self.slv_cmd8())
+            .field("slv_cmd9", &self.slv_cmd9())
+            .field("slv_cmda", &self.slv_cmda())
+            .field("slv_rd_dma_done", &self.slv_rd_dma_done())
+            .field("slv_wr_dma_done", &self.slv_wr_dma_done())
+            .field("slv_rd_buf_done", &self.slv_rd_buf_done())
+            .field("slv_wr_buf_done", &self.slv_wr_buf_done())
+            .field("trans_done", &self.trans_done())
+            .field("dma_seg_trans_done", &self.dma_seg_trans_done())
+            .field("seg_magic_err", &self.seg_magic_err())
+            .field("slv_buf_addr_err", &self.slv_buf_addr_err())
+            .field("slv_cmd_err", &self.slv_cmd_err())
+            .field("mst_rx_afifo_wfull_err", &self.mst_rx_afifo_wfull_err())
+            .field("mst_tx_afifo_rempty_err", &self.mst_tx_afifo_rempty_err())
+            .field("app2", &self.app2())
+            .field("app1", &self.app1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SPI interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMA_INT_ST_SPEC;
 impl crate::RegisterSpec for DMA_INT_ST_SPEC {
diff --git a/esp32s3/src/spi2/dout_mode.rs b/esp32s3/src/spi2/dout_mode.rs
index c782d95f30..5327365c02 100644
--- a/esp32s3/src/spi2/dout_mode.rs
+++ b/esp32s3/src/spi2/dout_mode.rs
@@ -89,24 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOUT_MODE")
-            .field("dout0_mode", &format_args!("{}", self.dout0_mode().bit()))
-            .field("dout1_mode", &format_args!("{}", self.dout1_mode().bit()))
-            .field("dout2_mode", &format_args!("{}", self.dout2_mode().bit()))
-            .field("dout3_mode", &format_args!("{}", self.dout3_mode().bit()))
-            .field("dout4_mode", &format_args!("{}", self.dout4_mode().bit()))
-            .field("dout5_mode", &format_args!("{}", self.dout5_mode().bit()))
-            .field("dout6_mode", &format_args!("{}", self.dout6_mode().bit()))
-            .field("dout7_mode", &format_args!("{}", self.dout7_mode().bit()))
-            .field("d_dqs_mode", &format_args!("{}", self.d_dqs_mode().bit()))
+            .field("dout0_mode", &self.dout0_mode())
+            .field("dout1_mode", &self.dout1_mode())
+            .field("dout2_mode", &self.dout2_mode())
+            .field("dout3_mode", &self.dout3_mode())
+            .field("dout4_mode", &self.dout4_mode())
+            .field("dout5_mode", &self.dout5_mode())
+            .field("dout6_mode", &self.dout6_mode())
+            .field("dout7_mode", &self.dout7_mode())
+            .field("d_dqs_mode", &self.d_dqs_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOUT_MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/misc.rs b/esp32s3/src/spi2/misc.rs
index acf949453f..21c438c62e 100644
--- a/esp32s3/src/spi2/misc.rs
+++ b/esp32s3/src/spi2/misc.rs
@@ -161,53 +161,26 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC")
-            .field("cs0_dis", &format_args!("{}", self.cs0_dis().bit()))
-            .field("cs1_dis", &format_args!("{}", self.cs1_dis().bit()))
-            .field("cs2_dis", &format_args!("{}", self.cs2_dis().bit()))
-            .field("cs3_dis", &format_args!("{}", self.cs3_dis().bit()))
-            .field("cs4_dis", &format_args!("{}", self.cs4_dis().bit()))
-            .field("cs5_dis", &format_args!("{}", self.cs5_dis().bit()))
-            .field("ck_dis", &format_args!("{}", self.ck_dis().bit()))
-            .field(
-                "master_cs_pol",
-                &format_args!("{}", self.master_cs_pol().bits()),
-            )
-            .field(
-                "clk_data_dtr_en",
-                &format_args!("{}", self.clk_data_dtr_en().bit()),
-            )
-            .field("data_dtr_en", &format_args!("{}", self.data_dtr_en().bit()))
-            .field("addr_dtr_en", &format_args!("{}", self.addr_dtr_en().bit()))
-            .field("cmd_dtr_en", &format_args!("{}", self.cmd_dtr_en().bit()))
-            .field(
-                "slave_cs_pol",
-                &format_args!("{}", self.slave_cs_pol().bit()),
-            )
-            .field(
-                "dqs_idle_edge",
-                &format_args!("{}", self.dqs_idle_edge().bit()),
-            )
-            .field(
-                "ck_idle_edge",
-                &format_args!("{}", self.ck_idle_edge().bit()),
-            )
-            .field(
-                "cs_keep_active",
-                &format_args!("{}", self.cs_keep_active().bit()),
-            )
-            .field(
-                "quad_din_pin_swap",
-                &format_args!("{}", self.quad_din_pin_swap().bit()),
-            )
+            .field("cs0_dis", &self.cs0_dis())
+            .field("cs1_dis", &self.cs1_dis())
+            .field("cs2_dis", &self.cs2_dis())
+            .field("cs3_dis", &self.cs3_dis())
+            .field("cs4_dis", &self.cs4_dis())
+            .field("cs5_dis", &self.cs5_dis())
+            .field("ck_dis", &self.ck_dis())
+            .field("master_cs_pol", &self.master_cs_pol())
+            .field("clk_data_dtr_en", &self.clk_data_dtr_en())
+            .field("data_dtr_en", &self.data_dtr_en())
+            .field("addr_dtr_en", &self.addr_dtr_en())
+            .field("cmd_dtr_en", &self.cmd_dtr_en())
+            .field("slave_cs_pol", &self.slave_cs_pol())
+            .field("dqs_idle_edge", &self.dqs_idle_edge())
+            .field("ck_idle_edge", &self.ck_idle_edge())
+            .field("cs_keep_active", &self.cs_keep_active())
+            .field("quad_din_pin_swap", &self.quad_din_pin_swap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/ms_dlen.rs b/esp32s3/src/spi2/ms_dlen.rs
index 116939582c..94a2915785 100644
--- a/esp32s3/src/spi2/ms_dlen.rs
+++ b/esp32s3/src/spi2/ms_dlen.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MS_DLEN")
-            .field(
-                "ms_data_bitlen",
-                &format_args!("{}", self.ms_data_bitlen().bits()),
-            )
+            .field("ms_data_bitlen", &self.ms_data_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MS_DLEN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/slave.rs b/esp32s3/src/spi2/slave.rs
index 2deadc74df..91a5b8108d 100644
--- a/esp32s3/src/spi2/slave.rs
+++ b/esp32s3/src/spi2/slave.rs
@@ -100,43 +100,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE")
-            .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
-            .field("clk_mode_13", &format_args!("{}", self.clk_mode_13().bit()))
-            .field(
-                "rsck_data_out",
-                &format_args!("{}", self.rsck_data_out().bit()),
-            )
-            .field(
-                "slv_rddma_bitlen_en",
-                &format_args!("{}", self.slv_rddma_bitlen_en().bit()),
-            )
-            .field(
-                "slv_wrdma_bitlen_en",
-                &format_args!("{}", self.slv_wrdma_bitlen_en().bit()),
-            )
-            .field(
-                "slv_rdbuf_bitlen_en",
-                &format_args!("{}", self.slv_rdbuf_bitlen_en().bit()),
-            )
-            .field(
-                "slv_wrbuf_bitlen_en",
-                &format_args!("{}", self.slv_wrbuf_bitlen_en().bit()),
-            )
-            .field(
-                "dma_seg_magic_value",
-                &format_args!("{}", self.dma_seg_magic_value().bits()),
-            )
-            .field("mode", &format_args!("{}", self.mode().bit()))
-            .field("usr_conf", &format_args!("{}", self.usr_conf().bit()))
+            .field("clk_mode", &self.clk_mode())
+            .field("clk_mode_13", &self.clk_mode_13())
+            .field("rsck_data_out", &self.rsck_data_out())
+            .field("slv_rddma_bitlen_en", &self.slv_rddma_bitlen_en())
+            .field("slv_wrdma_bitlen_en", &self.slv_wrdma_bitlen_en())
+            .field("slv_rdbuf_bitlen_en", &self.slv_rdbuf_bitlen_en())
+            .field("slv_wrbuf_bitlen_en", &self.slv_wrbuf_bitlen_en())
+            .field("dma_seg_magic_value", &self.dma_seg_magic_value())
+            .field("mode", &self.mode())
+            .field("usr_conf", &self.usr_conf())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/slave1.rs b/esp32s3/src/spi2/slave1.rs
index 7e216d9f86..98ad1b4b32 100644
--- a/esp32s3/src/spi2/slave1.rs
+++ b/esp32s3/src/spi2/slave1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLAVE1")
-            .field(
-                "slv_data_bitlen",
-                &format_args!("{}", self.slv_data_bitlen().bits()),
-            )
-            .field(
-                "slv_last_command",
-                &format_args!("{}", self.slv_last_command().bits()),
-            )
-            .field(
-                "slv_last_addr",
-                &format_args!("{}", self.slv_last_addr().bits()),
-            )
+            .field("slv_data_bitlen", &self.slv_data_bitlen())
+            .field("slv_last_command", &self.slv_last_command())
+            .field("slv_last_addr", &self.slv_last_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLAVE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:17 - The transferred data bit length in SPI slave FD and HD mode."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/user.rs b/esp32s3/src/spi2/user.rs
index 60d58c5ede..10fdfadeba 100644
--- a/esp32s3/src/spi2/user.rs
+++ b/esp32s3/src/spi2/user.rs
@@ -197,48 +197,30 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER")
-            .field("doutdin", &format_args!("{}", self.doutdin().bit()))
-            .field("qpi_mode", &format_args!("{}", self.qpi_mode().bit()))
-            .field("opi_mode", &format_args!("{}", self.opi_mode().bit()))
-            .field("tsck_i_edge", &format_args!("{}", self.tsck_i_edge().bit()))
-            .field("cs_hold", &format_args!("{}", self.cs_hold().bit()))
-            .field("cs_setup", &format_args!("{}", self.cs_setup().bit()))
-            .field("rsck_i_edge", &format_args!("{}", self.rsck_i_edge().bit()))
-            .field("ck_out_edge", &format_args!("{}", self.ck_out_edge().bit()))
-            .field("fwrite_dual", &format_args!("{}", self.fwrite_dual().bit()))
-            .field("fwrite_quad", &format_args!("{}", self.fwrite_quad().bit()))
-            .field("fwrite_oct", &format_args!("{}", self.fwrite_oct().bit()))
-            .field(
-                "usr_conf_nxt",
-                &format_args!("{}", self.usr_conf_nxt().bit()),
-            )
-            .field("sio", &format_args!("{}", self.sio().bit()))
-            .field(
-                "usr_miso_highpart",
-                &format_args!("{}", self.usr_miso_highpart().bit()),
-            )
-            .field(
-                "usr_mosi_highpart",
-                &format_args!("{}", self.usr_mosi_highpart().bit()),
-            )
-            .field(
-                "usr_dummy_idle",
-                &format_args!("{}", self.usr_dummy_idle().bit()),
-            )
-            .field("usr_mosi", &format_args!("{}", self.usr_mosi().bit()))
-            .field("usr_miso", &format_args!("{}", self.usr_miso().bit()))
-            .field("usr_dummy", &format_args!("{}", self.usr_dummy().bit()))
-            .field("usr_addr", &format_args!("{}", self.usr_addr().bit()))
-            .field("usr_command", &format_args!("{}", self.usr_command().bit()))
+            .field("doutdin", &self.doutdin())
+            .field("qpi_mode", &self.qpi_mode())
+            .field("opi_mode", &self.opi_mode())
+            .field("tsck_i_edge", &self.tsck_i_edge())
+            .field("cs_hold", &self.cs_hold())
+            .field("cs_setup", &self.cs_setup())
+            .field("rsck_i_edge", &self.rsck_i_edge())
+            .field("ck_out_edge", &self.ck_out_edge())
+            .field("fwrite_dual", &self.fwrite_dual())
+            .field("fwrite_quad", &self.fwrite_quad())
+            .field("fwrite_oct", &self.fwrite_oct())
+            .field("usr_conf_nxt", &self.usr_conf_nxt())
+            .field("sio", &self.sio())
+            .field("usr_miso_highpart", &self.usr_miso_highpart())
+            .field("usr_mosi_highpart", &self.usr_mosi_highpart())
+            .field("usr_dummy_idle", &self.usr_dummy_idle())
+            .field("usr_mosi", &self.usr_mosi())
+            .field("usr_miso", &self.usr_miso())
+            .field("usr_dummy", &self.usr_dummy())
+            .field("usr_addr", &self.usr_addr())
+            .field("usr_command", &self.usr_command())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/user1.rs b/esp32s3/src/spi2/user1.rs
index acb564ca07..1dd612d409 100644
--- a/esp32s3/src/spi2/user1.rs
+++ b/esp32s3/src/spi2/user1.rs
@@ -53,35 +53,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER1")
-            .field(
-                "usr_dummy_cyclelen",
-                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
-            )
-            .field(
-                "mst_wfull_err_end_en",
-                &format_args!("{}", self.mst_wfull_err_end_en().bit()),
-            )
-            .field(
-                "cs_setup_time",
-                &format_args!("{}", self.cs_setup_time().bits()),
-            )
-            .field(
-                "cs_hold_time",
-                &format_args!("{}", self.cs_hold_time().bits()),
-            )
-            .field(
-                "usr_addr_bitlen",
-                &format_args!("{}", self.usr_addr_bitlen().bits()),
-            )
+            .field("usr_dummy_cyclelen", &self.usr_dummy_cyclelen())
+            .field("mst_wfull_err_end_en", &self.mst_wfull_err_end_en())
+            .field("cs_setup_time", &self.cs_setup_time())
+            .field("cs_hold_time", &self.cs_hold_time())
+            .field("usr_addr_bitlen", &self.usr_addr_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/user2.rs b/esp32s3/src/spi2/user2.rs
index 065c536363..c2d5092cd2 100644
--- a/esp32s3/src/spi2/user2.rs
+++ b/esp32s3/src/spi2/user2.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("USER2")
-            .field(
-                "usr_command_value",
-                &format_args!("{}", self.usr_command_value().bits()),
-            )
-            .field(
-                "mst_rempty_err_end_en",
-                &format_args!("{}", self.mst_rempty_err_end_en().bit()),
-            )
-            .field(
-                "usr_command_bitlen",
-                &format_args!("{}", self.usr_command_bitlen().bits()),
-            )
+            .field("usr_command_value", &self.usr_command_value())
+            .field("mst_rempty_err_end_en", &self.mst_rempty_err_end_en())
+            .field("usr_command_bitlen", &self.usr_command_bitlen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<USER2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - The value of command. Can be configured in CONF state."]
     #[inline(always)]
diff --git a/esp32s3/src/spi2/w.rs b/esp32s3/src/spi2/w.rs
index bd1588a6f2..016fb59d7c 100644
--- a/esp32s3/src/spi2/w.rs
+++ b/esp32s3/src/spi2/w.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("W")
-            .field("buf", &format_args!("{}", self.buf().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<W_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("W").field("buf", &self.buf()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/system/bt_lpck_div_frac.rs b/esp32s3/src/system/bt_lpck_div_frac.rs
index 33fe41cb99..113c21373e 100644
--- a/esp32s3/src/system/bt_lpck_div_frac.rs
+++ b/esp32s3/src/system/bt_lpck_div_frac.rs
@@ -71,43 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_LPCK_DIV_FRAC")
-            .field(
-                "bt_lpck_div_b",
-                &format_args!("{}", self.bt_lpck_div_b().bits()),
-            )
-            .field(
-                "bt_lpck_div_a",
-                &format_args!("{}", self.bt_lpck_div_a().bits()),
-            )
-            .field(
-                "lpclk_sel_rtc_slow",
-                &format_args!("{}", self.lpclk_sel_rtc_slow().bit()),
-            )
-            .field(
-                "lpclk_sel_8m",
-                &format_args!("{}", self.lpclk_sel_8m().bit()),
-            )
-            .field(
-                "lpclk_sel_xtal",
-                &format_args!("{}", self.lpclk_sel_xtal().bit()),
-            )
-            .field(
-                "lpclk_sel_xtal32k",
-                &format_args!("{}", self.lpclk_sel_xtal32k().bit()),
-            )
-            .field(
-                "lpclk_rtc_en",
-                &format_args!("{}", self.lpclk_rtc_en().bit()),
-            )
+            .field("bt_lpck_div_b", &self.bt_lpck_div_b())
+            .field("bt_lpck_div_a", &self.bt_lpck_div_a())
+            .field("lpclk_sel_rtc_slow", &self.lpclk_sel_rtc_slow())
+            .field("lpclk_sel_8m", &self.lpclk_sel_8m())
+            .field("lpclk_sel_xtal", &self.lpclk_sel_xtal())
+            .field("lpclk_sel_xtal32k", &self.lpclk_sel_xtal32k())
+            .field("lpclk_rtc_en", &self.lpclk_rtc_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_LPCK_DIV_FRAC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - This field is lower power clock frequent division factor b"]
     #[inline(always)]
diff --git a/esp32s3/src/system/bt_lpck_div_int.rs b/esp32s3/src/system/bt_lpck_div_int.rs
index 7a61ebf1aa..f55c401aad 100644
--- a/esp32s3/src/system/bt_lpck_div_int.rs
+++ b/esp32s3/src/system/bt_lpck_div_int.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BT_LPCK_DIV_INT")
-            .field(
-                "bt_lpck_div_num",
-                &format_args!("{}", self.bt_lpck_div_num().bits()),
-            )
+            .field("bt_lpck_div_num", &self.bt_lpck_div_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BT_LPCK_DIV_INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - This field is lower power clock frequent division factor"]
     #[inline(always)]
diff --git a/esp32s3/src/system/cache_control.rs b/esp32s3/src/system/cache_control.rs
index 889dc51ade..b3d013b51b 100644
--- a/esp32s3/src/system/cache_control.rs
+++ b/esp32s3/src/system/cache_control.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CACHE_CONTROL")
-            .field(
-                "icache_clk_on",
-                &format_args!("{}", self.icache_clk_on().bit()),
-            )
-            .field(
-                "icache_reset",
-                &format_args!("{}", self.icache_reset().bit()),
-            )
-            .field(
-                "dcache_clk_on",
-                &format_args!("{}", self.dcache_clk_on().bit()),
-            )
-            .field(
-                "dcache_reset",
-                &format_args!("{}", self.dcache_reset().bit()),
-            )
+            .field("icache_clk_on", &self.icache_clk_on())
+            .field("icache_reset", &self.icache_reset())
+            .field("dcache_clk_on", &self.dcache_clk_on())
+            .field("dcache_reset", &self.dcache_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CACHE_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable icache clock"]
     #[inline(always)]
diff --git a/esp32s3/src/system/clock_gate.rs b/esp32s3/src/system/clock_gate.rs
index 9b2f6940e9..d6fe4d26c3 100644
--- a/esp32s3/src/system/clock_gate.rs
+++ b/esp32s3/src/system/clock_gate.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_GATE")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_GATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/system/comb_pvt_err_hvt_site0.rs b/esp32s3/src/system/comb_pvt_err_hvt_site0.rs
index fcbf83f5b8..738cb1dd87 100644
--- a/esp32s3/src/system/comb_pvt_err_hvt_site0.rs
+++ b/esp32s3/src/system/comb_pvt_err_hvt_site0.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_HVT_SITE0")
             .field(
                 "comb_timing_err_cnt_hvt_site0",
-                &format_args!("{}", self.comb_timing_err_cnt_hvt_site0().bits()),
+                &self.comb_timing_err_cnt_hvt_site0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_HVT_SITE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_hvt_site0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_HVT_SITE0_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE0_SPEC {
diff --git a/esp32s3/src/system/comb_pvt_err_hvt_site1.rs b/esp32s3/src/system/comb_pvt_err_hvt_site1.rs
index 7b59c18558..93e134a8f6 100644
--- a/esp32s3/src/system/comb_pvt_err_hvt_site1.rs
+++ b/esp32s3/src/system/comb_pvt_err_hvt_site1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_HVT_SITE1")
             .field(
                 "comb_timing_err_cnt_hvt_site1",
-                &format_args!("{}", self.comb_timing_err_cnt_hvt_site1().bits()),
+                &self.comb_timing_err_cnt_hvt_site1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_HVT_SITE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_hvt_site1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_HVT_SITE1_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE1_SPEC {
diff --git a/esp32s3/src/system/comb_pvt_err_hvt_site2.rs b/esp32s3/src/system/comb_pvt_err_hvt_site2.rs
index 88c2bfc49d..16e6f06372 100644
--- a/esp32s3/src/system/comb_pvt_err_hvt_site2.rs
+++ b/esp32s3/src/system/comb_pvt_err_hvt_site2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_HVT_SITE2")
             .field(
                 "comb_timing_err_cnt_hvt_site2",
-                &format_args!("{}", self.comb_timing_err_cnt_hvt_site2().bits()),
+                &self.comb_timing_err_cnt_hvt_site2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_HVT_SITE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_hvt_site2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_HVT_SITE2_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE2_SPEC {
diff --git a/esp32s3/src/system/comb_pvt_err_hvt_site3.rs b/esp32s3/src/system/comb_pvt_err_hvt_site3.rs
index 22387d9901..d9ae17b67a 100644
--- a/esp32s3/src/system/comb_pvt_err_hvt_site3.rs
+++ b/esp32s3/src/system/comb_pvt_err_hvt_site3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_HVT_SITE3")
             .field(
                 "comb_timing_err_cnt_hvt_site3",
-                &format_args!("{}", self.comb_timing_err_cnt_hvt_site3().bits()),
+                &self.comb_timing_err_cnt_hvt_site3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_HVT_SITE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_hvt_site3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_HVT_SITE3_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_HVT_SITE3_SPEC {
diff --git a/esp32s3/src/system/comb_pvt_err_lvt_site0.rs b/esp32s3/src/system/comb_pvt_err_lvt_site0.rs
index da38912b86..e4ae7b2601 100644
--- a/esp32s3/src/system/comb_pvt_err_lvt_site0.rs
+++ b/esp32s3/src/system/comb_pvt_err_lvt_site0.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_LVT_SITE0")
             .field(
                 "comb_timing_err_cnt_lvt_site0",
-                &format_args!("{}", self.comb_timing_err_cnt_lvt_site0().bits()),
+                &self.comb_timing_err_cnt_lvt_site0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_LVT_SITE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_lvt_site0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_LVT_SITE0_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE0_SPEC {
diff --git a/esp32s3/src/system/comb_pvt_err_lvt_site1.rs b/esp32s3/src/system/comb_pvt_err_lvt_site1.rs
index 00c1eb5c29..b0024ec5cb 100644
--- a/esp32s3/src/system/comb_pvt_err_lvt_site1.rs
+++ b/esp32s3/src/system/comb_pvt_err_lvt_site1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_LVT_SITE1")
             .field(
                 "comb_timing_err_cnt_lvt_site1",
-                &format_args!("{}", self.comb_timing_err_cnt_lvt_site1().bits()),
+                &self.comb_timing_err_cnt_lvt_site1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_LVT_SITE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_lvt_site1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_LVT_SITE1_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE1_SPEC {
diff --git a/esp32s3/src/system/comb_pvt_err_lvt_site2.rs b/esp32s3/src/system/comb_pvt_err_lvt_site2.rs
index eaf4a57ec3..be18c6a488 100644
--- a/esp32s3/src/system/comb_pvt_err_lvt_site2.rs
+++ b/esp32s3/src/system/comb_pvt_err_lvt_site2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_LVT_SITE2")
             .field(
                 "comb_timing_err_cnt_lvt_site2",
-                &format_args!("{}", self.comb_timing_err_cnt_lvt_site2().bits()),
+                &self.comb_timing_err_cnt_lvt_site2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_LVT_SITE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_lvt_site2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_LVT_SITE2_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE2_SPEC {
diff --git a/esp32s3/src/system/comb_pvt_err_lvt_site3.rs b/esp32s3/src/system/comb_pvt_err_lvt_site3.rs
index 760d9246b9..b6c1eaa66a 100644
--- a/esp32s3/src/system/comb_pvt_err_lvt_site3.rs
+++ b/esp32s3/src/system/comb_pvt_err_lvt_site3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_LVT_SITE3")
             .field(
                 "comb_timing_err_cnt_lvt_site3",
-                &format_args!("{}", self.comb_timing_err_cnt_lvt_site3().bits()),
+                &self.comb_timing_err_cnt_lvt_site3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_LVT_SITE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_lvt_site3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_LVT_SITE3_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_LVT_SITE3_SPEC {
diff --git a/esp32s3/src/system/comb_pvt_err_nvt_site0.rs b/esp32s3/src/system/comb_pvt_err_nvt_site0.rs
index 6348d6555f..fb90143e65 100644
--- a/esp32s3/src/system/comb_pvt_err_nvt_site0.rs
+++ b/esp32s3/src/system/comb_pvt_err_nvt_site0.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_NVT_SITE0")
             .field(
                 "comb_timing_err_cnt_nvt_site0",
-                &format_args!("{}", self.comb_timing_err_cnt_nvt_site0().bits()),
+                &self.comb_timing_err_cnt_nvt_site0(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_NVT_SITE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_nvt_site0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_NVT_SITE0_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE0_SPEC {
diff --git a/esp32s3/src/system/comb_pvt_err_nvt_site1.rs b/esp32s3/src/system/comb_pvt_err_nvt_site1.rs
index f091d83c44..6ae6276974 100644
--- a/esp32s3/src/system/comb_pvt_err_nvt_site1.rs
+++ b/esp32s3/src/system/comb_pvt_err_nvt_site1.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_NVT_SITE1")
             .field(
                 "comb_timing_err_cnt_nvt_site1",
-                &format_args!("{}", self.comb_timing_err_cnt_nvt_site1().bits()),
+                &self.comb_timing_err_cnt_nvt_site1(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_NVT_SITE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_nvt_site1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_NVT_SITE1_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE1_SPEC {
diff --git a/esp32s3/src/system/comb_pvt_err_nvt_site2.rs b/esp32s3/src/system/comb_pvt_err_nvt_site2.rs
index 49195afc3e..e9d9922a8c 100644
--- a/esp32s3/src/system/comb_pvt_err_nvt_site2.rs
+++ b/esp32s3/src/system/comb_pvt_err_nvt_site2.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_NVT_SITE2")
             .field(
                 "comb_timing_err_cnt_nvt_site2",
-                &format_args!("{}", self.comb_timing_err_cnt_nvt_site2().bits()),
+                &self.comb_timing_err_cnt_nvt_site2(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_NVT_SITE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_nvt_site2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_NVT_SITE2_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE2_SPEC {
diff --git a/esp32s3/src/system/comb_pvt_err_nvt_site3.rs b/esp32s3/src/system/comb_pvt_err_nvt_site3.rs
index a16d514d26..67632f81f8 100644
--- a/esp32s3/src/system/comb_pvt_err_nvt_site3.rs
+++ b/esp32s3/src/system/comb_pvt_err_nvt_site3.rs
@@ -15,17 +15,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("COMB_PVT_ERR_NVT_SITE3")
             .field(
                 "comb_timing_err_cnt_nvt_site3",
-                &format_args!("{}", self.comb_timing_err_cnt_nvt_site3().bits()),
+                &self.comb_timing_err_cnt_nvt_site3(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_ERR_NVT_SITE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "******* Description ***********\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`comb_pvt_err_nvt_site3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COMB_PVT_ERR_NVT_SITE3_SPEC;
 impl crate::RegisterSpec for COMB_PVT_ERR_NVT_SITE3_SPEC {
diff --git a/esp32s3/src/system/comb_pvt_hvt_conf.rs b/esp32s3/src/system/comb_pvt_hvt_conf.rs
index 52538b254f..83e9d59271 100644
--- a/esp32s3/src/system/comb_pvt_hvt_conf.rs
+++ b/esp32s3/src/system/comb_pvt_hvt_conf.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMB_PVT_HVT_CONF")
-            .field(
-                "comb_path_len_hvt",
-                &format_args!("{}", self.comb_path_len_hvt().bits()),
-            )
-            .field(
-                "comb_pvt_monitor_en_hvt",
-                &format_args!("{}", self.comb_pvt_monitor_en_hvt().bit()),
-            )
+            .field("comb_path_len_hvt", &self.comb_path_len_hvt())
+            .field("comb_pvt_monitor_en_hvt", &self.comb_pvt_monitor_en_hvt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_HVT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/system/comb_pvt_lvt_conf.rs b/esp32s3/src/system/comb_pvt_lvt_conf.rs
index 35baf30288..e72810f8b1 100644
--- a/esp32s3/src/system/comb_pvt_lvt_conf.rs
+++ b/esp32s3/src/system/comb_pvt_lvt_conf.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMB_PVT_LVT_CONF")
-            .field(
-                "comb_path_len_lvt",
-                &format_args!("{}", self.comb_path_len_lvt().bits()),
-            )
-            .field(
-                "comb_pvt_monitor_en_lvt",
-                &format_args!("{}", self.comb_pvt_monitor_en_lvt().bit()),
-            )
+            .field("comb_path_len_lvt", &self.comb_path_len_lvt())
+            .field("comb_pvt_monitor_en_lvt", &self.comb_pvt_monitor_en_lvt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_LVT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/system/comb_pvt_nvt_conf.rs b/esp32s3/src/system/comb_pvt_nvt_conf.rs
index 3ad2c403c6..2bc0a777a1 100644
--- a/esp32s3/src/system/comb_pvt_nvt_conf.rs
+++ b/esp32s3/src/system/comb_pvt_nvt_conf.rs
@@ -28,23 +28,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("COMB_PVT_NVT_CONF")
-            .field(
-                "comb_path_len_nvt",
-                &format_args!("{}", self.comb_path_len_nvt().bits()),
-            )
-            .field(
-                "comb_pvt_monitor_en_nvt",
-                &format_args!("{}", self.comb_pvt_monitor_en_nvt().bit()),
-            )
+            .field("comb_path_len_nvt", &self.comb_path_len_nvt())
+            .field("comb_pvt_monitor_en_nvt", &self.comb_pvt_monitor_en_nvt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<COMB_PVT_NVT_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:4 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/system/core_1_control_0.rs b/esp32s3/src/system/core_1_control_0.rs
index dd87265260..523a54361e 100644
--- a/esp32s3/src/system/core_1_control_0.rs
+++ b/esp32s3/src/system/core_1_control_0.rs
@@ -35,27 +35,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_CONTROL_0")
-            .field(
-                "control_core_1_runstall",
-                &format_args!("{}", self.control_core_1_runstall().bit()),
-            )
+            .field("control_core_1_runstall", &self.control_core_1_runstall())
             .field(
                 "control_core_1_clkgate_en",
-                &format_args!("{}", self.control_core_1_clkgate_en().bit()),
-            )
-            .field(
-                "control_core_1_reseting",
-                &format_args!("{}", self.control_core_1_reseting().bit()),
+                &self.control_core_1_clkgate_en(),
             )
+            .field("control_core_1_reseting", &self.control_core_1_reseting())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_CONTROL_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to stall core1"]
     #[inline(always)]
diff --git a/esp32s3/src/system/core_1_control_1.rs b/esp32s3/src/system/core_1_control_1.rs
index 0f39852639..8916e58cfe 100644
--- a/esp32s3/src/system/core_1_control_1.rs
+++ b/esp32s3/src/system/core_1_control_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CORE_1_CONTROL_1")
-            .field(
-                "control_core_1_message",
-                &format_args!("{}", self.control_core_1_message().bits()),
-            )
+            .field("control_core_1_message", &self.control_core_1_message())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_CONTROL_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - it's only a R/W register, no function, software can write any value"]
     #[inline(always)]
diff --git a/esp32s3/src/system/cpu_intr_from_cpu_0.rs b/esp32s3/src/system/cpu_intr_from_cpu_0.rs
index 1c42c656fd..b05cbe54b2 100644
--- a/esp32s3/src/system/cpu_intr_from_cpu_0.rs
+++ b/esp32s3/src/system/cpu_intr_from_cpu_0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_0")
-            .field(
-                "cpu_intr_from_cpu_0",
-                &format_args!("{}", self.cpu_intr_from_cpu_0().bit()),
-            )
+            .field("cpu_intr_from_cpu_0", &self.cpu_intr_from_cpu_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to generate cpu interrupt 0"]
     #[inline(always)]
diff --git a/esp32s3/src/system/cpu_intr_from_cpu_1.rs b/esp32s3/src/system/cpu_intr_from_cpu_1.rs
index 3391784094..f2a7cc7205 100644
--- a/esp32s3/src/system/cpu_intr_from_cpu_1.rs
+++ b/esp32s3/src/system/cpu_intr_from_cpu_1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_1")
-            .field(
-                "cpu_intr_from_cpu_1",
-                &format_args!("{}", self.cpu_intr_from_cpu_1().bit()),
-            )
+            .field("cpu_intr_from_cpu_1", &self.cpu_intr_from_cpu_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to generate cpu interrupt 1"]
     #[inline(always)]
diff --git a/esp32s3/src/system/cpu_intr_from_cpu_2.rs b/esp32s3/src/system/cpu_intr_from_cpu_2.rs
index 6954bcb047..80e2ef3e59 100644
--- a/esp32s3/src/system/cpu_intr_from_cpu_2.rs
+++ b/esp32s3/src/system/cpu_intr_from_cpu_2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_2")
-            .field(
-                "cpu_intr_from_cpu_2",
-                &format_args!("{}", self.cpu_intr_from_cpu_2().bit()),
-            )
+            .field("cpu_intr_from_cpu_2", &self.cpu_intr_from_cpu_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to generate cpu interrupt 2"]
     #[inline(always)]
diff --git a/esp32s3/src/system/cpu_intr_from_cpu_3.rs b/esp32s3/src/system/cpu_intr_from_cpu_3.rs
index c23a02baa9..5a723eb299 100644
--- a/esp32s3/src/system/cpu_intr_from_cpu_3.rs
+++ b/esp32s3/src/system/cpu_intr_from_cpu_3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_INTR_FROM_CPU_3")
-            .field(
-                "cpu_intr_from_cpu_3",
-                &format_args!("{}", self.cpu_intr_from_cpu_3().bit()),
-            )
+            .field("cpu_intr_from_cpu_3", &self.cpu_intr_from_cpu_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_INTR_FROM_CPU_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to generate cpu interrupt 3"]
     #[inline(always)]
diff --git a/esp32s3/src/system/cpu_per_conf.rs b/esp32s3/src/system/cpu_per_conf.rs
index 67f3383967..1db7fed283 100644
--- a/esp32s3/src/system/cpu_per_conf.rs
+++ b/esp32s3/src/system/cpu_per_conf.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PER_CONF")
-            .field(
-                "cpuperiod_sel",
-                &format_args!("{}", self.cpuperiod_sel().bits()),
-            )
-            .field(
-                "pll_freq_sel",
-                &format_args!("{}", self.pll_freq_sel().bit()),
-            )
-            .field(
-                "cpu_wait_mode_force_on",
-                &format_args!("{}", self.cpu_wait_mode_force_on().bit()),
-            )
-            .field(
-                "cpu_waiti_delay_num",
-                &format_args!("{}", self.cpu_waiti_delay_num().bits()),
-            )
+            .field("cpuperiod_sel", &self.cpuperiod_sel())
+            .field("pll_freq_sel", &self.pll_freq_sel())
+            .field("cpu_wait_mode_force_on", &self.cpu_wait_mode_force_on())
+            .field("cpu_waiti_delay_num", &self.cpu_waiti_delay_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PER_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field used to sel cpu clock frequent."]
     #[inline(always)]
diff --git a/esp32s3/src/system/cpu_peri_clk_en.rs b/esp32s3/src/system/cpu_peri_clk_en.rs
index 5f3a670500..d191ee7c56 100644
--- a/esp32s3/src/system/cpu_peri_clk_en.rs
+++ b/esp32s3/src/system/cpu_peri_clk_en.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERI_CLK_EN")
-            .field(
-                "clk_en_assist_debug",
-                &format_args!("{}", self.clk_en_assist_debug().bit()),
-            )
-            .field(
-                "clk_en_dedicated_gpio",
-                &format_args!("{}", self.clk_en_dedicated_gpio().bit()),
-            )
+            .field("clk_en_assist_debug", &self.clk_en_assist_debug())
+            .field("clk_en_dedicated_gpio", &self.clk_en_dedicated_gpio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_CLK_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - Set 1 to open assist_debug module clock"]
     #[inline(always)]
diff --git a/esp32s3/src/system/cpu_peri_rst_en.rs b/esp32s3/src/system/cpu_peri_rst_en.rs
index 491fe36fc2..0c2bc8f181 100644
--- a/esp32s3/src/system/cpu_peri_rst_en.rs
+++ b/esp32s3/src/system/cpu_peri_rst_en.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CPU_PERI_RST_EN")
-            .field(
-                "rst_en_assist_debug",
-                &format_args!("{}", self.rst_en_assist_debug().bit()),
-            )
-            .field(
-                "rst_en_dedicated_gpio",
-                &format_args!("{}", self.rst_en_dedicated_gpio().bit()),
-            )
+            .field("rst_en_assist_debug", &self.rst_en_assist_debug())
+            .field("rst_en_dedicated_gpio", &self.rst_en_dedicated_gpio())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CPU_PERI_RST_EN_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 6 - Set 1 to let assist_debug module reset"]
     #[inline(always)]
diff --git a/esp32s3/src/system/date.rs b/esp32s3/src/system/date.rs
index e937a00569..4ee3954715 100644
--- a/esp32s3/src/system/date.rs
+++ b/esp32s3/src/system/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/system/edma_ctrl.rs b/esp32s3/src/system/edma_ctrl.rs
index 60bc789f1b..ca4c68f585 100644
--- a/esp32s3/src/system/edma_ctrl.rs
+++ b/esp32s3/src/system/edma_ctrl.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EDMA_CTRL")
-            .field("edma_clk_on", &format_args!("{}", self.edma_clk_on().bit()))
-            .field("edma_reset", &format_args!("{}", self.edma_reset().bit()))
+            .field("edma_clk_on", &self.edma_clk_on())
+            .field("edma_reset", &self.edma_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EDMA_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable EDMA clock."]
     #[inline(always)]
diff --git a/esp32s3/src/system/external_device_encrypt_decrypt_control.rs b/esp32s3/src/system/external_device_encrypt_decrypt_control.rs
index febd93a052..06a25e7539 100644
--- a/esp32s3/src/system/external_device_encrypt_decrypt_control.rs
+++ b/esp32s3/src/system/external_device_encrypt_decrypt_control.rs
@@ -46,29 +46,23 @@ impl core::fmt::Debug for R {
         f.debug_struct("EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL")
             .field(
                 "enable_spi_manual_encrypt",
-                &format_args!("{}", self.enable_spi_manual_encrypt().bit()),
+                &self.enable_spi_manual_encrypt(),
             )
             .field(
                 "enable_download_db_encrypt",
-                &format_args!("{}", self.enable_download_db_encrypt().bit()),
+                &self.enable_download_db_encrypt(),
             )
             .field(
                 "enable_download_g0cb_decrypt",
-                &format_args!("{}", self.enable_download_g0cb_decrypt().bit()),
+                &self.enable_download_g0cb_decrypt(),
             )
             .field(
                 "enable_download_manual_encrypt",
-                &format_args!("{}", self.enable_download_manual_encrypt().bit()),
+                &self.enable_download_manual_encrypt(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable the SPI manual encrypt."]
     #[inline(always)]
diff --git a/esp32s3/src/system/mem_pd_mask.rs b/esp32s3/src/system/mem_pd_mask.rs
index 925648f2b7..3eefd91842 100644
--- a/esp32s3/src/system/mem_pd_mask.rs
+++ b/esp32s3/src/system/mem_pd_mask.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_PD_MASK")
-            .field(
-                "lslp_mem_pd_mask",
-                &format_args!("{}", self.lslp_mem_pd_mask().bit()),
-            )
+            .field("lslp_mem_pd_mask", &self.lslp_mem_pd_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_PD_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to mask memory power down."]
     #[inline(always)]
diff --git a/esp32s3/src/system/mem_pvt.rs b/esp32s3/src/system/mem_pvt.rs
index d6345f6013..8992144d94 100644
--- a/esp32s3/src/system/mem_pvt.rs
+++ b/esp32s3/src/system/mem_pvt.rs
@@ -44,25 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_PVT")
-            .field(
-                "mem_path_len",
-                &format_args!("{}", self.mem_path_len().bits()),
-            )
-            .field("monitor_en", &format_args!("{}", self.monitor_en().bit()))
-            .field(
-                "mem_timing_err_cnt",
-                &format_args!("{}", self.mem_timing_err_cnt().bits()),
-            )
-            .field("mem_vt_sel", &format_args!("{}", self.mem_vt_sel().bits()))
+            .field("mem_path_len", &self.mem_path_len())
+            .field("monitor_en", &self.monitor_en())
+            .field("mem_timing_err_cnt", &self.mem_timing_err_cnt())
+            .field("mem_vt_sel", &self.mem_vt_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_PVT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/system/perip_clk_en0.rs b/esp32s3/src/system/perip_clk_en0.rs
index bfaf7a373f..03eb513e37 100644
--- a/esp32s3/src/system/perip_clk_en0.rs
+++ b/esp32s3/src/system/perip_clk_en0.rs
@@ -296,95 +296,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_CLK_EN0")
-            .field(
-                "timers_clk_en",
-                &format_args!("{}", self.timers_clk_en().bit()),
-            )
-            .field(
-                "spi01_clk_en",
-                &format_args!("{}", self.spi01_clk_en().bit()),
-            )
-            .field("uart_clk_en", &format_args!("{}", self.uart_clk_en().bit()))
-            .field("wdg_clk_en", &format_args!("{}", self.wdg_clk_en().bit()))
-            .field("i2s0_clk_en", &format_args!("{}", self.i2s0_clk_en().bit()))
-            .field(
-                "uart1_clk_en",
-                &format_args!("{}", self.uart1_clk_en().bit()),
-            )
-            .field("spi2_clk_en", &format_args!("{}", self.spi2_clk_en().bit()))
-            .field(
-                "i2c_ext0_clk_en",
-                &format_args!("{}", self.i2c_ext0_clk_en().bit()),
-            )
-            .field(
-                "uhci0_clk_en",
-                &format_args!("{}", self.uhci0_clk_en().bit()),
-            )
-            .field("rmt_clk_en", &format_args!("{}", self.rmt_clk_en().bit()))
-            .field("pcnt_clk_en", &format_args!("{}", self.pcnt_clk_en().bit()))
-            .field("ledc_clk_en", &format_args!("{}", self.ledc_clk_en().bit()))
-            .field(
-                "uhci1_clk_en",
-                &format_args!("{}", self.uhci1_clk_en().bit()),
-            )
-            .field(
-                "timergroup_clk_en",
-                &format_args!("{}", self.timergroup_clk_en().bit()),
-            )
-            .field(
-                "efuse_clk_en",
-                &format_args!("{}", self.efuse_clk_en().bit()),
-            )
-            .field(
-                "timergroup1_clk_en",
-                &format_args!("{}", self.timergroup1_clk_en().bit()),
-            )
-            .field("spi3_clk_en", &format_args!("{}", self.spi3_clk_en().bit()))
-            .field("pwm0_clk_en", &format_args!("{}", self.pwm0_clk_en().bit()))
-            .field(
-                "i2c_ext1_clk_en",
-                &format_args!("{}", self.i2c_ext1_clk_en().bit()),
-            )
-            .field("twai_clk_en", &format_args!("{}", self.twai_clk_en().bit()))
-            .field("pwm1_clk_en", &format_args!("{}", self.pwm1_clk_en().bit()))
-            .field("i2s1_clk_en", &format_args!("{}", self.i2s1_clk_en().bit()))
-            .field(
-                "spi2_dma_clk_en",
-                &format_args!("{}", self.spi2_dma_clk_en().bit()),
-            )
-            .field("usb_clk_en", &format_args!("{}", self.usb_clk_en().bit()))
-            .field(
-                "uart_mem_clk_en",
-                &format_args!("{}", self.uart_mem_clk_en().bit()),
-            )
-            .field("pwm2_clk_en", &format_args!("{}", self.pwm2_clk_en().bit()))
-            .field("pwm3_clk_en", &format_args!("{}", self.pwm3_clk_en().bit()))
-            .field(
-                "spi3_dma_clk_en",
-                &format_args!("{}", self.spi3_dma_clk_en().bit()),
-            )
-            .field(
-                "apb_saradc_clk_en",
-                &format_args!("{}", self.apb_saradc_clk_en().bit()),
-            )
-            .field(
-                "systimer_clk_en",
-                &format_args!("{}", self.systimer_clk_en().bit()),
-            )
-            .field(
-                "adc2_arb_clk_en",
-                &format_args!("{}", self.adc2_arb_clk_en().bit()),
-            )
-            .field("spi4_clk_en", &format_args!("{}", self.spi4_clk_en().bit()))
+            .field("timers_clk_en", &self.timers_clk_en())
+            .field("spi01_clk_en", &self.spi01_clk_en())
+            .field("uart_clk_en", &self.uart_clk_en())
+            .field("wdg_clk_en", &self.wdg_clk_en())
+            .field("i2s0_clk_en", &self.i2s0_clk_en())
+            .field("uart1_clk_en", &self.uart1_clk_en())
+            .field("spi2_clk_en", &self.spi2_clk_en())
+            .field("i2c_ext0_clk_en", &self.i2c_ext0_clk_en())
+            .field("uhci0_clk_en", &self.uhci0_clk_en())
+            .field("rmt_clk_en", &self.rmt_clk_en())
+            .field("pcnt_clk_en", &self.pcnt_clk_en())
+            .field("ledc_clk_en", &self.ledc_clk_en())
+            .field("uhci1_clk_en", &self.uhci1_clk_en())
+            .field("timergroup_clk_en", &self.timergroup_clk_en())
+            .field("efuse_clk_en", &self.efuse_clk_en())
+            .field("timergroup1_clk_en", &self.timergroup1_clk_en())
+            .field("spi3_clk_en", &self.spi3_clk_en())
+            .field("pwm0_clk_en", &self.pwm0_clk_en())
+            .field("i2c_ext1_clk_en", &self.i2c_ext1_clk_en())
+            .field("twai_clk_en", &self.twai_clk_en())
+            .field("pwm1_clk_en", &self.pwm1_clk_en())
+            .field("i2s1_clk_en", &self.i2s1_clk_en())
+            .field("spi2_dma_clk_en", &self.spi2_dma_clk_en())
+            .field("usb_clk_en", &self.usb_clk_en())
+            .field("uart_mem_clk_en", &self.uart_mem_clk_en())
+            .field("pwm2_clk_en", &self.pwm2_clk_en())
+            .field("pwm3_clk_en", &self.pwm3_clk_en())
+            .field("spi3_dma_clk_en", &self.spi3_dma_clk_en())
+            .field("apb_saradc_clk_en", &self.apb_saradc_clk_en())
+            .field("systimer_clk_en", &self.systimer_clk_en())
+            .field("adc2_arb_clk_en", &self.adc2_arb_clk_en())
+            .field("spi4_clk_en", &self.spi4_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_CLK_EN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable TIMERS clock"]
     #[inline(always)]
diff --git a/esp32s3/src/system/perip_clk_en1.rs b/esp32s3/src/system/perip_clk_en1.rs
index 87e9a1a4cd..1824bb5fd0 100644
--- a/esp32s3/src/system/perip_clk_en1.rs
+++ b/esp32s3/src/system/perip_clk_en1.rs
@@ -107,56 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_CLK_EN1")
-            .field(
-                "peri_backup_clk_en",
-                &format_args!("{}", self.peri_backup_clk_en().bit()),
-            )
-            .field(
-                "crypto_aes_clk_en",
-                &format_args!("{}", self.crypto_aes_clk_en().bit()),
-            )
-            .field(
-                "crypto_sha_clk_en",
-                &format_args!("{}", self.crypto_sha_clk_en().bit()),
-            )
-            .field(
-                "crypto_rsa_clk_en",
-                &format_args!("{}", self.crypto_rsa_clk_en().bit()),
-            )
-            .field(
-                "crypto_ds_clk_en",
-                &format_args!("{}", self.crypto_ds_clk_en().bit()),
-            )
-            .field(
-                "crypto_hmac_clk_en",
-                &format_args!("{}", self.crypto_hmac_clk_en().bit()),
-            )
-            .field("dma_clk_en", &format_args!("{}", self.dma_clk_en().bit()))
-            .field(
-                "sdio_host_clk_en",
-                &format_args!("{}", self.sdio_host_clk_en().bit()),
-            )
-            .field(
-                "lcd_cam_clk_en",
-                &format_args!("{}", self.lcd_cam_clk_en().bit()),
-            )
-            .field(
-                "uart2_clk_en",
-                &format_args!("{}", self.uart2_clk_en().bit()),
-            )
-            .field(
-                "usb_device_clk_en",
-                &format_args!("{}", self.usb_device_clk_en().bit()),
-            )
+            .field("peri_backup_clk_en", &self.peri_backup_clk_en())
+            .field("crypto_aes_clk_en", &self.crypto_aes_clk_en())
+            .field("crypto_sha_clk_en", &self.crypto_sha_clk_en())
+            .field("crypto_rsa_clk_en", &self.crypto_rsa_clk_en())
+            .field("crypto_ds_clk_en", &self.crypto_ds_clk_en())
+            .field("crypto_hmac_clk_en", &self.crypto_hmac_clk_en())
+            .field("dma_clk_en", &self.dma_clk_en())
+            .field("sdio_host_clk_en", &self.sdio_host_clk_en())
+            .field("lcd_cam_clk_en", &self.lcd_cam_clk_en())
+            .field("uart2_clk_en", &self.uart2_clk_en())
+            .field("usb_device_clk_en", &self.usb_device_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_CLK_EN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to enable BACKUP clock"]
     #[inline(always)]
diff --git a/esp32s3/src/system/perip_rst_en0.rs b/esp32s3/src/system/perip_rst_en0.rs
index ac2676f7bc..5c631a4b6b 100644
--- a/esp32s3/src/system/perip_rst_en0.rs
+++ b/esp32s3/src/system/perip_rst_en0.rs
@@ -296,77 +296,41 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_RST_EN0")
-            .field("timers_rst", &format_args!("{}", self.timers_rst().bit()))
-            .field("spi01_rst", &format_args!("{}", self.spi01_rst().bit()))
-            .field("uart_rst", &format_args!("{}", self.uart_rst().bit()))
-            .field("wdg_rst", &format_args!("{}", self.wdg_rst().bit()))
-            .field("i2s0_rst", &format_args!("{}", self.i2s0_rst().bit()))
-            .field("uart1_rst", &format_args!("{}", self.uart1_rst().bit()))
-            .field("spi2_rst", &format_args!("{}", self.spi2_rst().bit()))
-            .field(
-                "i2c_ext0_rst",
-                &format_args!("{}", self.i2c_ext0_rst().bit()),
-            )
-            .field("uhci0_rst", &format_args!("{}", self.uhci0_rst().bit()))
-            .field("rmt_rst", &format_args!("{}", self.rmt_rst().bit()))
-            .field("pcnt_rst", &format_args!("{}", self.pcnt_rst().bit()))
-            .field("ledc_rst", &format_args!("{}", self.ledc_rst().bit()))
-            .field("uhci1_rst", &format_args!("{}", self.uhci1_rst().bit()))
-            .field(
-                "timergroup_rst",
-                &format_args!("{}", self.timergroup_rst().bit()),
-            )
-            .field("efuse_rst", &format_args!("{}", self.efuse_rst().bit()))
-            .field(
-                "timergroup1_rst",
-                &format_args!("{}", self.timergroup1_rst().bit()),
-            )
-            .field("spi3_rst", &format_args!("{}", self.spi3_rst().bit()))
-            .field("pwm0_rst", &format_args!("{}", self.pwm0_rst().bit()))
-            .field(
-                "i2c_ext1_rst",
-                &format_args!("{}", self.i2c_ext1_rst().bit()),
-            )
-            .field("twai_rst", &format_args!("{}", self.twai_rst().bit()))
-            .field("pwm1_rst", &format_args!("{}", self.pwm1_rst().bit()))
-            .field("i2s1_rst", &format_args!("{}", self.i2s1_rst().bit()))
-            .field(
-                "spi2_dma_rst",
-                &format_args!("{}", self.spi2_dma_rst().bit()),
-            )
-            .field("usb_rst", &format_args!("{}", self.usb_rst().bit()))
-            .field(
-                "uart_mem_rst",
-                &format_args!("{}", self.uart_mem_rst().bit()),
-            )
-            .field("pwm2_rst", &format_args!("{}", self.pwm2_rst().bit()))
-            .field("pwm3_rst", &format_args!("{}", self.pwm3_rst().bit()))
-            .field(
-                "spi3_dma_rst",
-                &format_args!("{}", self.spi3_dma_rst().bit()),
-            )
-            .field(
-                "apb_saradc_rst",
-                &format_args!("{}", self.apb_saradc_rst().bit()),
-            )
-            .field(
-                "systimer_rst",
-                &format_args!("{}", self.systimer_rst().bit()),
-            )
-            .field(
-                "adc2_arb_rst",
-                &format_args!("{}", self.adc2_arb_rst().bit()),
-            )
-            .field("spi4_rst", &format_args!("{}", self.spi4_rst().bit()))
+            .field("timers_rst", &self.timers_rst())
+            .field("spi01_rst", &self.spi01_rst())
+            .field("uart_rst", &self.uart_rst())
+            .field("wdg_rst", &self.wdg_rst())
+            .field("i2s0_rst", &self.i2s0_rst())
+            .field("uart1_rst", &self.uart1_rst())
+            .field("spi2_rst", &self.spi2_rst())
+            .field("i2c_ext0_rst", &self.i2c_ext0_rst())
+            .field("uhci0_rst", &self.uhci0_rst())
+            .field("rmt_rst", &self.rmt_rst())
+            .field("pcnt_rst", &self.pcnt_rst())
+            .field("ledc_rst", &self.ledc_rst())
+            .field("uhci1_rst", &self.uhci1_rst())
+            .field("timergroup_rst", &self.timergroup_rst())
+            .field("efuse_rst", &self.efuse_rst())
+            .field("timergroup1_rst", &self.timergroup1_rst())
+            .field("spi3_rst", &self.spi3_rst())
+            .field("pwm0_rst", &self.pwm0_rst())
+            .field("i2c_ext1_rst", &self.i2c_ext1_rst())
+            .field("twai_rst", &self.twai_rst())
+            .field("pwm1_rst", &self.pwm1_rst())
+            .field("i2s1_rst", &self.i2s1_rst())
+            .field("spi2_dma_rst", &self.spi2_dma_rst())
+            .field("usb_rst", &self.usb_rst())
+            .field("uart_mem_rst", &self.uart_mem_rst())
+            .field("pwm2_rst", &self.pwm2_rst())
+            .field("pwm3_rst", &self.pwm3_rst())
+            .field("spi3_dma_rst", &self.spi3_dma_rst())
+            .field("apb_saradc_rst", &self.apb_saradc_rst())
+            .field("systimer_rst", &self.systimer_rst())
+            .field("adc2_arb_rst", &self.adc2_arb_rst())
+            .field("spi4_rst", &self.spi4_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_RST_EN0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to let TIMERS reset"]
     #[inline(always)]
diff --git a/esp32s3/src/system/perip_rst_en1.rs b/esp32s3/src/system/perip_rst_en1.rs
index 6ed6fb0e9a..35c108bbe0 100644
--- a/esp32s3/src/system/perip_rst_en1.rs
+++ b/esp32s3/src/system/perip_rst_en1.rs
@@ -107,50 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PERIP_RST_EN1")
-            .field(
-                "peri_backup_rst",
-                &format_args!("{}", self.peri_backup_rst().bit()),
-            )
-            .field(
-                "crypto_aes_rst",
-                &format_args!("{}", self.crypto_aes_rst().bit()),
-            )
-            .field(
-                "crypto_sha_rst",
-                &format_args!("{}", self.crypto_sha_rst().bit()),
-            )
-            .field(
-                "crypto_rsa_rst",
-                &format_args!("{}", self.crypto_rsa_rst().bit()),
-            )
-            .field(
-                "crypto_ds_rst",
-                &format_args!("{}", self.crypto_ds_rst().bit()),
-            )
-            .field(
-                "crypto_hmac_rst",
-                &format_args!("{}", self.crypto_hmac_rst().bit()),
-            )
-            .field("dma_rst", &format_args!("{}", self.dma_rst().bit()))
-            .field(
-                "sdio_host_rst",
-                &format_args!("{}", self.sdio_host_rst().bit()),
-            )
-            .field("lcd_cam_rst", &format_args!("{}", self.lcd_cam_rst().bit()))
-            .field("uart2_rst", &format_args!("{}", self.uart2_rst().bit()))
-            .field(
-                "usb_device_rst",
-                &format_args!("{}", self.usb_device_rst().bit()),
-            )
+            .field("peri_backup_rst", &self.peri_backup_rst())
+            .field("crypto_aes_rst", &self.crypto_aes_rst())
+            .field("crypto_sha_rst", &self.crypto_sha_rst())
+            .field("crypto_rsa_rst", &self.crypto_rsa_rst())
+            .field("crypto_ds_rst", &self.crypto_ds_rst())
+            .field("crypto_hmac_rst", &self.crypto_hmac_rst())
+            .field("dma_rst", &self.dma_rst())
+            .field("sdio_host_rst", &self.sdio_host_rst())
+            .field("lcd_cam_rst", &self.lcd_cam_rst())
+            .field("uart2_rst", &self.uart2_rst())
+            .field("usb_device_rst", &self.usb_device_rst())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PERIP_RST_EN1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to let BACKUP reset"]
     #[inline(always)]
diff --git a/esp32s3/src/system/redundant_eco_ctrl.rs b/esp32s3/src/system/redundant_eco_ctrl.rs
index 4722f330c2..11cfcc251f 100644
--- a/esp32s3/src/system/redundant_eco_ctrl.rs
+++ b/esp32s3/src/system/redundant_eco_ctrl.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REDUNDANT_ECO_CTRL")
-            .field(
-                "redundant_eco_drive",
-                &format_args!("{}", self.redundant_eco_drive().bit()),
-            )
-            .field(
-                "redundant_eco_result",
-                &format_args!("{}", self.redundant_eco_result().bit()),
-            )
+            .field("redundant_eco_drive", &self.redundant_eco_drive())
+            .field("redundant_eco_result", &self.redundant_eco_result())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REDUNDANT_ECO_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - ******* Description ***********"]
     #[inline(always)]
diff --git a/esp32s3/src/system/rsa_pd_ctrl.rs b/esp32s3/src/system/rsa_pd_ctrl.rs
index 486ff76603..9b12e2d0a9 100644
--- a/esp32s3/src/system/rsa_pd_ctrl.rs
+++ b/esp32s3/src/system/rsa_pd_ctrl.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RSA_PD_CTRL")
-            .field("rsa_mem_pd", &format_args!("{}", self.rsa_mem_pd().bit()))
-            .field(
-                "rsa_mem_force_pu",
-                &format_args!("{}", self.rsa_mem_force_pu().bit()),
-            )
-            .field(
-                "rsa_mem_force_pd",
-                &format_args!("{}", self.rsa_mem_force_pd().bit()),
-            )
+            .field("rsa_mem_pd", &self.rsa_mem_pd())
+            .field("rsa_mem_force_pu", &self.rsa_mem_force_pu())
+            .field("rsa_mem_force_pd", &self.rsa_mem_force_pd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RSA_PD_CTRL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA, this bit is invalid."]
     #[inline(always)]
diff --git a/esp32s3/src/system/rtc_fastmem_config.rs b/esp32s3/src/system/rtc_fastmem_config.rs
index fd6cfceb06..5b1c1d6af5 100644
--- a/esp32s3/src/system/rtc_fastmem_config.rs
+++ b/esp32s3/src/system/rtc_fastmem_config.rs
@@ -42,31 +42,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_FASTMEM_CONFIG")
-            .field(
-                "rtc_mem_crc_start",
-                &format_args!("{}", self.rtc_mem_crc_start().bit()),
-            )
-            .field(
-                "rtc_mem_crc_addr",
-                &format_args!("{}", self.rtc_mem_crc_addr().bits()),
-            )
-            .field(
-                "rtc_mem_crc_len",
-                &format_args!("{}", self.rtc_mem_crc_len().bits()),
-            )
-            .field(
-                "rtc_mem_crc_finish",
-                &format_args!("{}", self.rtc_mem_crc_finish().bit()),
-            )
+            .field("rtc_mem_crc_start", &self.rtc_mem_crc_start())
+            .field("rtc_mem_crc_addr", &self.rtc_mem_crc_addr())
+            .field("rtc_mem_crc_len", &self.rtc_mem_crc_len())
+            .field("rtc_mem_crc_finish", &self.rtc_mem_crc_finish())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_FASTMEM_CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - Set 1 to start the CRC of RTC memory"]
     #[inline(always)]
diff --git a/esp32s3/src/system/rtc_fastmem_crc.rs b/esp32s3/src/system/rtc_fastmem_crc.rs
index c7f9308ef3..4b81c66b68 100644
--- a/esp32s3/src/system/rtc_fastmem_crc.rs
+++ b/esp32s3/src/system/rtc_fastmem_crc.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTC_FASTMEM_CRC")
-            .field(
-                "rtc_mem_crc_res",
-                &format_args!("{}", self.rtc_mem_crc_res().bits()),
-            )
+            .field("rtc_mem_crc_res", &self.rtc_mem_crc_res())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_FASTMEM_CRC_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC fast memory CRC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_fastmem_crc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTC_FASTMEM_CRC_SPEC;
 impl crate::RegisterSpec for RTC_FASTMEM_CRC_SPEC {
diff --git a/esp32s3/src/system/sysclk_conf.rs b/esp32s3/src/system/sysclk_conf.rs
index bb3cf9c7ca..75019ca637 100644
--- a/esp32s3/src/system/sysclk_conf.rs
+++ b/esp32s3/src/system/sysclk_conf.rs
@@ -40,28 +40,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SYSCLK_CONF")
-            .field(
-                "pre_div_cnt",
-                &format_args!("{}", self.pre_div_cnt().bits()),
-            )
-            .field(
-                "soc_clk_sel",
-                &format_args!("{}", self.soc_clk_sel().bits()),
-            )
-            .field(
-                "clk_xtal_freq",
-                &format_args!("{}", self.clk_xtal_freq().bits()),
-            )
-            .field("clk_div_en", &format_args!("{}", self.clk_div_en().bit()))
+            .field("pre_div_cnt", &self.pre_div_cnt())
+            .field("soc_clk_sel", &self.soc_clk_sel())
+            .field("clk_xtal_freq", &self.clk_xtal_freq())
+            .field("clk_div_en", &self.clk_div_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SYSCLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - This field is used to set the count of prescaler of XTAL_CLK."]
     #[inline(always)]
diff --git a/esp32s3/src/systimer/conf.rs b/esp32s3/src/systimer/conf.rs
index 40ff74a8b9..1111a16ca4 100644
--- a/esp32s3/src/systimer/conf.rs
+++ b/esp32s3/src/systimer/conf.rs
@@ -107,56 +107,32 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF")
-            .field(
-                "systimer_clk_fo",
-                &format_args!("{}", self.systimer_clk_fo().bit()),
-            )
-            .field(
-                "target2_work_en",
-                &format_args!("{}", self.target2_work_en().bit()),
-            )
-            .field(
-                "target1_work_en",
-                &format_args!("{}", self.target1_work_en().bit()),
-            )
-            .field(
-                "target0_work_en",
-                &format_args!("{}", self.target0_work_en().bit()),
-            )
+            .field("systimer_clk_fo", &self.systimer_clk_fo())
+            .field("target2_work_en", &self.target2_work_en())
+            .field("target1_work_en", &self.target1_work_en())
+            .field("target0_work_en", &self.target0_work_en())
             .field(
                 "timer_unit1_core1_stall_en",
-                &format_args!("{}", self.timer_unit1_core1_stall_en().bit()),
+                &self.timer_unit1_core1_stall_en(),
             )
             .field(
                 "timer_unit1_core0_stall_en",
-                &format_args!("{}", self.timer_unit1_core0_stall_en().bit()),
+                &self.timer_unit1_core0_stall_en(),
             )
             .field(
                 "timer_unit0_core1_stall_en",
-                &format_args!("{}", self.timer_unit0_core1_stall_en().bit()),
+                &self.timer_unit0_core1_stall_en(),
             )
             .field(
                 "timer_unit0_core0_stall_en",
-                &format_args!("{}", self.timer_unit0_core0_stall_en().bit()),
+                &self.timer_unit0_core0_stall_en(),
             )
-            .field(
-                "timer_unit1_work_en",
-                &format_args!("{}", self.timer_unit1_work_en().bit()),
-            )
-            .field(
-                "timer_unit0_work_en",
-                &format_args!("{}", self.timer_unit0_work_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("timer_unit1_work_en", &self.timer_unit1_work_en())
+            .field("timer_unit0_work_en", &self.timer_unit0_work_en())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - systimer clock force on"]
     #[inline(always)]
diff --git a/esp32s3/src/systimer/date.rs b/esp32s3/src/systimer/date.rs
index ac8c0009cc..2387e338ef 100644
--- a/esp32s3/src/systimer/date.rs
+++ b/esp32s3/src/systimer/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/systimer/int_ena.rs b/esp32s3/src/systimer/int_ena.rs
index 9afbd67324..bf39753584 100644
--- a/esp32s3/src/systimer/int_ena.rs
+++ b/esp32s3/src/systimer/int_ena.rs
@@ -42,18 +42,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "interupt(0-2) enable"]
     #[doc = ""]
diff --git a/esp32s3/src/systimer/int_raw.rs b/esp32s3/src/systimer/int_raw.rs
index 9487c30025..395cb8187f 100644
--- a/esp32s3/src/systimer/int_raw.rs
+++ b/esp32s3/src/systimer/int_raw.rs
@@ -42,18 +42,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "interupt(0-2) raw"]
     #[doc = ""]
diff --git a/esp32s3/src/systimer/int_st.rs b/esp32s3/src/systimer/int_st.rs
index 4c4d3c12f8..1dc503012b 100644
--- a/esp32s3/src/systimer/int_st.rs
+++ b/esp32s3/src/systimer/int_st.rs
@@ -38,18 +38,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("target0", &format_args!("{}", self.target0().bit()))
-            .field("target1", &format_args!("{}", self.target1().bit()))
-            .field("target2", &format_args!("{}", self.target2().bit()))
+            .field("target0", &self.target0())
+            .field("target1", &self.target1())
+            .field("target2", &self.target2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "systimer interrupt status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/systimer/real_target/hi.rs b/esp32s3/src/systimer/real_target/hi.rs
index e37661f89a..10d4966ea0 100644
--- a/esp32s3/src/systimer/real_target/hi.rs
+++ b/esp32s3/src/systimer/real_target/hi.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi_ro", &format_args!("{}", self.hi_ro().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi_ro", &self.hi_ro()).finish()
     }
 }
 #[doc = "system timer comp0 actual target value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s3/src/systimer/real_target/lo.rs b/esp32s3/src/systimer/real_target/lo.rs
index 6ba16447eb..2a8623e63b 100644
--- a/esp32s3/src/systimer/real_target/lo.rs
+++ b/esp32s3/src/systimer/real_target/lo.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo_ro", &format_args!("{}", self.lo_ro().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo_ro", &self.lo_ro()).finish()
     }
 }
 #[doc = "system timer comp0 actual target value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s3/src/systimer/target_conf.rs b/esp32s3/src/systimer/target_conf.rs
index 351218e2ba..48184bd1f3 100644
--- a/esp32s3/src/systimer/target_conf.rs
+++ b/esp32s3/src/systimer/target_conf.rs
@@ -35,21 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TARGET_CONF")
-            .field("period", &format_args!("{}", self.period().bits()))
-            .field("period_mode", &format_args!("{}", self.period_mode().bit()))
-            .field(
-                "timer_unit_sel",
-                &format_args!("{}", self.timer_unit_sel().bit()),
-            )
+            .field("period", &self.period())
+            .field("period_mode", &self.period_mode())
+            .field("timer_unit_sel", &self.timer_unit_sel())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TARGET_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:25 - target0 period"]
     #[inline(always)]
diff --git a/esp32s3/src/systimer/trgt/hi.rs b/esp32s3/src/systimer/trgt/hi.rs
index 9ba19aedd7..1bbcc8532f 100644
--- a/esp32s3/src/systimer/trgt/hi.rs
+++ b/esp32s3/src/systimer/trgt/hi.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/systimer/trgt/lo.rs b/esp32s3/src/systimer/trgt/lo.rs
index cf5618b115..870fcb7923 100644
--- a/esp32s3/src/systimer/trgt/lo.rs
+++ b/esp32s3/src/systimer/trgt/lo.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/systimer/unit_op.rs b/esp32s3/src/systimer/unit_op.rs
index 161504c169..5a004338a8 100644
--- a/esp32s3/src/systimer/unit_op.rs
+++ b/esp32s3/src/systimer/unit_op.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UNIT_OP")
-            .field("value_valid", &format_args!("{}", self.value_valid().bit()))
+            .field("value_valid", &self.value_valid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UNIT_OP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 30 - update timer_unit0"]
     #[inline(always)]
diff --git a/esp32s3/src/systimer/unit_value/hi.rs b/esp32s3/src/systimer/unit_value/hi.rs
index 3cd25b4d55..10523f249f 100644
--- a/esp32s3/src/systimer/unit_value/hi.rs
+++ b/esp32s3/src/systimer/unit_value/hi.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HI")
-            .field("value_hi", &format_args!("{}", self.value_hi().bits()))
+            .field("value_hi", &self.value_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "system timer unit0 value high register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HI_SPEC;
 impl crate::RegisterSpec for HI_SPEC {
diff --git a/esp32s3/src/systimer/unit_value/lo.rs b/esp32s3/src/systimer/unit_value/lo.rs
index a60743963d..92c3f4e991 100644
--- a/esp32s3/src/systimer/unit_value/lo.rs
+++ b/esp32s3/src/systimer/unit_value/lo.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LO")
-            .field("value_lo", &format_args!("{}", self.value_lo().bits()))
+            .field("value_lo", &self.value_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "system timer unit0 value low register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LO_SPEC;
 impl crate::RegisterSpec for LO_SPEC {
diff --git a/esp32s3/src/systimer/unitload/hi.rs b/esp32s3/src/systimer/unitload/hi.rs
index 3d663b8225..a758293265 100644
--- a/esp32s3/src/systimer/unitload/hi.rs
+++ b/esp32s3/src/systimer/unitload/hi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:19 - timer unit0 load high 20 bits"]
     #[inline(always)]
diff --git a/esp32s3/src/systimer/unitload/lo.rs b/esp32s3/src/systimer/unitload/lo.rs
index 15e267cf3c..e01c2efb83 100644
--- a/esp32s3/src/systimer/unitload/lo.rs
+++ b/esp32s3/src/systimer/unitload/lo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - timer unit0 load low 32 bits"]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/int_ena_timers.rs b/esp32s3/src/timg0/int_ena_timers.rs
index d45fb94a17..0f0f5e347b 100644
--- a/esp32s3/src/timg0/int_ena_timers.rs
+++ b/esp32s3/src/timg0/int_ena_timers.rs
@@ -46,18 +46,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("t1", &format_args!("{}", self.t1().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("t1", &self.t1())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The interrupt enable bit for the TIMG_T(0-1)_INT interrupt."]
     #[doc = ""]
diff --git a/esp32s3/src/timg0/int_raw_timers.rs b/esp32s3/src/timg0/int_raw_timers.rs
index b4b67ac2ad..b8763c851d 100644
--- a/esp32s3/src/timg0/int_raw_timers.rs
+++ b/esp32s3/src/timg0/int_raw_timers.rs
@@ -46,18 +46,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("t1", &format_args!("{}", self.t1().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("t1", &self.t1())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "The raw interrupt status bit for the TIMG_T(0-1)_INT interrupt."]
     #[doc = ""]
diff --git a/esp32s3/src/timg0/int_st_timers.rs b/esp32s3/src/timg0/int_st_timers.rs
index 9d4210fb3f..48776fe635 100644
--- a/esp32s3/src/timg0/int_st_timers.rs
+++ b/esp32s3/src/timg0/int_st_timers.rs
@@ -40,18 +40,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST_TIMERS")
-            .field("t0", &format_args!("{}", self.t0().bit()))
-            .field("t1", &format_args!("{}", self.t1().bit()))
-            .field("wdt", &format_args!("{}", self.wdt().bit()))
+            .field("t0", &self.t0())
+            .field("t1", &self.t1())
+            .field("wdt", &self.wdt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_TIMERS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st_timers::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_TIMERS_SPEC;
 impl crate::RegisterSpec for INT_ST_TIMERS_SPEC {
diff --git a/esp32s3/src/timg0/ntimers_date.rs b/esp32s3/src/timg0/ntimers_date.rs
index 13806ee35a..4c6715d86b 100644
--- a/esp32s3/src/timg0/ntimers_date.rs
+++ b/esp32s3/src/timg0/ntimers_date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NTIMERS_DATE")
-            .field(
-                "ntimers_date",
-                &format_args!("{}", self.ntimers_date().bits()),
-            )
+            .field("ntimers_date", &self.ntimers_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NTIMERS_DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:27 - Timer version control register"]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/regclk.rs b/esp32s3/src/timg0/regclk.rs
index 036f2e1c3b..57f2af34db 100644
--- a/esp32s3/src/timg0/regclk.rs
+++ b/esp32s3/src/timg0/regclk.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("REGCLK")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<REGCLK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - Register clock gate signal. 1: The clock for software to read and write registers is always on. 0: The clock for software to read and write registers only exits when the operation happens."]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/rtccalicfg.rs b/esp32s3/src/timg0/rtccalicfg.rs
index 75ef1dcf6d..412ae62b81 100644
--- a/esp32s3/src/timg0/rtccalicfg.rs
+++ b/esp32s3/src/timg0/rtccalicfg.rs
@@ -51,35 +51,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG")
-            .field(
-                "rtc_cali_start_cycling",
-                &format_args!("{}", self.rtc_cali_start_cycling().bit()),
-            )
-            .field(
-                "rtc_cali_clk_sel",
-                &format_args!("{}", self.rtc_cali_clk_sel().bits()),
-            )
-            .field(
-                "rtc_cali_rdy",
-                &format_args!("{}", self.rtc_cali_rdy().bit()),
-            )
-            .field(
-                "rtc_cali_max",
-                &format_args!("{}", self.rtc_cali_max().bits()),
-            )
-            .field(
-                "rtc_cali_start",
-                &format_args!("{}", self.rtc_cali_start().bit()),
-            )
+            .field("rtc_cali_start_cycling", &self.rtc_cali_start_cycling())
+            .field("rtc_cali_clk_sel", &self.rtc_cali_clk_sel())
+            .field("rtc_cali_rdy", &self.rtc_cali_rdy())
+            .field("rtc_cali_max", &self.rtc_cali_max())
+            .field("rtc_cali_start", &self.rtc_cali_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Reserved"]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/rtccalicfg1.rs b/esp32s3/src/timg0/rtccalicfg1.rs
index ef581397c8..c5d12a9d71 100644
--- a/esp32s3/src/timg0/rtccalicfg1.rs
+++ b/esp32s3/src/timg0/rtccalicfg1.rs
@@ -22,21 +22,12 @@ impl core::fmt::Debug for R {
         f.debug_struct("RTCCALICFG1")
             .field(
                 "rtc_cali_cycling_data_vld",
-                &format_args!("{}", self.rtc_cali_cycling_data_vld().bit()),
-            )
-            .field(
-                "rtc_cali_value",
-                &format_args!("{}", self.rtc_cali_value().bits()),
+                &self.rtc_cali_cycling_data_vld(),
             )
+            .field("rtc_cali_value", &self.rtc_cali_value())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "RTC calibration configure1 register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtccalicfg1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RTCCALICFG1_SPEC;
 impl crate::RegisterSpec for RTCCALICFG1_SPEC {
diff --git a/esp32s3/src/timg0/rtccalicfg2.rs b/esp32s3/src/timg0/rtccalicfg2.rs
index a0ea39a67b..2142857b29 100644
--- a/esp32s3/src/timg0/rtccalicfg2.rs
+++ b/esp32s3/src/timg0/rtccalicfg2.rs
@@ -33,27 +33,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RTCCALICFG2")
-            .field(
-                "rtc_cali_timeout",
-                &format_args!("{}", self.rtc_cali_timeout().bit()),
-            )
-            .field(
-                "rtc_cali_timeout_rst_cnt",
-                &format_args!("{}", self.rtc_cali_timeout_rst_cnt().bits()),
-            )
-            .field(
-                "rtc_cali_timeout_thres",
-                &format_args!("{}", self.rtc_cali_timeout_thres().bits()),
-            )
+            .field("rtc_cali_timeout", &self.rtc_cali_timeout())
+            .field("rtc_cali_timeout_rst_cnt", &self.rtc_cali_timeout_rst_cnt())
+            .field("rtc_cali_timeout_thres", &self.rtc_cali_timeout_thres())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTCCALICFG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 3:6 - Cycles that release calibration timeout reset"]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/t/alarmhi.rs b/esp32s3/src/timg0/t/alarmhi.rs
index 22292581b3..e885af54c8 100644
--- a/esp32s3/src/timg0/t/alarmhi.rs
+++ b/esp32s3/src/timg0/t/alarmhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMHI")
-            .field("alarm_hi", &format_args!("{}", self.alarm_hi().bits()))
+            .field("alarm_hi", &self.alarm_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - Timer %s alarm trigger time-base counter value, high 22 bits."]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/t/alarmlo.rs b/esp32s3/src/timg0/t/alarmlo.rs
index 7aaa51e9cb..d1f7b86948 100644
--- a/esp32s3/src/timg0/t/alarmlo.rs
+++ b/esp32s3/src/timg0/t/alarmlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ALARMLO")
-            .field("alarm_lo", &format_args!("{}", self.alarm_lo().bits()))
+            .field("alarm_lo", &self.alarm_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ALARMLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Timer %s alarm trigger time-base counter value, low 32 bits."]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/t/config.rs b/esp32s3/src/timg0/t/config.rs
index 3eb63ee88a..79f476d994 100644
--- a/esp32s3/src/timg0/t/config.rs
+++ b/esp32s3/src/timg0/t/config.rs
@@ -62,21 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONFIG")
-            .field("use_xtal", &format_args!("{}", self.use_xtal().bit()))
-            .field("alarm_en", &format_args!("{}", self.alarm_en().bit()))
-            .field("divider", &format_args!("{}", self.divider().bits()))
-            .field("autoreload", &format_args!("{}", self.autoreload().bit()))
-            .field("increase", &format_args!("{}", self.increase().bit()))
-            .field("en", &format_args!("{}", self.en().bit()))
+            .field("use_xtal", &self.use_xtal())
+            .field("alarm_en", &self.alarm_en())
+            .field("divider", &self.divider())
+            .field("autoreload", &self.autoreload())
+            .field("increase", &self.increase())
+            .field("en", &self.en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONFIG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 9 - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/t/hi.rs b/esp32s3/src/timg0/t/hi.rs
index e73d1713fe..6ad1b0027a 100644
--- a/esp32s3/src/timg0/t/hi.rs
+++ b/esp32s3/src/timg0/t/hi.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("HI")
-            .field("hi", &format_args!("{}", self.hi().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("HI").field("hi", &self.hi()).finish()
     }
 }
 #[doc = "Timer 0 current value, high 22 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s3/src/timg0/t/lo.rs b/esp32s3/src/timg0/t/lo.rs
index 40c76cd3a1..a8846e3e83 100644
--- a/esp32s3/src/timg0/t/lo.rs
+++ b/esp32s3/src/timg0/t/lo.rs
@@ -12,15 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("LO")
-            .field("lo", &format_args!("{}", self.lo().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("LO").field("lo", &self.lo()).finish()
     }
 }
 #[doc = "Timer 0 current value, low 32 bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lo::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
diff --git a/esp32s3/src/timg0/t/loadhi.rs b/esp32s3/src/timg0/t/loadhi.rs
index 308a8375de..ac27dd6227 100644
--- a/esp32s3/src/timg0/t/loadhi.rs
+++ b/esp32s3/src/timg0/t/loadhi.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADHI")
-            .field("load_hi", &format_args!("{}", self.load_hi().bits()))
+            .field("load_hi", &self.load_hi())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADHI_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:21 - High 22 bits of the value that a reload will load onto timer %s time-base counter."]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/t/loadlo.rs b/esp32s3/src/timg0/t/loadlo.rs
index 354ac9907d..82b436f990 100644
--- a/esp32s3/src/timg0/t/loadlo.rs
+++ b/esp32s3/src/timg0/t/loadlo.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOADLO")
-            .field("load_lo", &format_args!("{}", self.load_lo().bits()))
+            .field("load_lo", &self.load_lo())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOADLO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Low 32 bits of the value that a reload will load onto timer %s time-base Counter."]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/t/update.rs b/esp32s3/src/timg0/t/update.rs
index 3869da8b15..139fa5cefb 100644
--- a/esp32s3/src/timg0/t/update.rs
+++ b/esp32s3/src/timg0/t/update.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UPDATE")
-            .field("update", &format_args!("{}", self.update().bit()))
+            .field("update", &self.update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<UPDATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 31 - After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched."]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/wdtconfig0.rs b/esp32s3/src/timg0/wdtconfig0.rs
index fb78bfc5dc..29eb54464c 100644
--- a/esp32s3/src/timg0/wdtconfig0.rs
+++ b/esp32s3/src/timg0/wdtconfig0.rs
@@ -98,40 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG0")
-            .field(
-                "wdt_appcpu_reset_en",
-                &format_args!("{}", self.wdt_appcpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_procpu_reset_en",
-                &format_args!("{}", self.wdt_procpu_reset_en().bit()),
-            )
-            .field(
-                "wdt_flashboot_mod_en",
-                &format_args!("{}", self.wdt_flashboot_mod_en().bit()),
-            )
-            .field(
-                "wdt_sys_reset_length",
-                &format_args!("{}", self.wdt_sys_reset_length().bits()),
-            )
-            .field(
-                "wdt_cpu_reset_length",
-                &format_args!("{}", self.wdt_cpu_reset_length().bits()),
-            )
-            .field("wdt_stg3", &format_args!("{}", self.wdt_stg3().bits()))
-            .field("wdt_stg2", &format_args!("{}", self.wdt_stg2().bits()))
-            .field("wdt_stg1", &format_args!("{}", self.wdt_stg1().bits()))
-            .field("wdt_stg0", &format_args!("{}", self.wdt_stg0().bits()))
-            .field("wdt_en", &format_args!("{}", self.wdt_en().bit()))
+            .field("wdt_appcpu_reset_en", &self.wdt_appcpu_reset_en())
+            .field("wdt_procpu_reset_en", &self.wdt_procpu_reset_en())
+            .field("wdt_flashboot_mod_en", &self.wdt_flashboot_mod_en())
+            .field("wdt_sys_reset_length", &self.wdt_sys_reset_length())
+            .field("wdt_cpu_reset_length", &self.wdt_cpu_reset_length())
+            .field("wdt_stg3", &self.wdt_stg3())
+            .field("wdt_stg2", &self.wdt_stg2())
+            .field("wdt_stg1", &self.wdt_stg1())
+            .field("wdt_stg0", &self.wdt_stg0())
+            .field("wdt_en", &self.wdt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 12 - Reserved"]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/wdtconfig1.rs b/esp32s3/src/timg0/wdtconfig1.rs
index 3aa68de08a..1a09586ed3 100644
--- a/esp32s3/src/timg0/wdtconfig1.rs
+++ b/esp32s3/src/timg0/wdtconfig1.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG1")
-            .field(
-                "wdt_clk_prescale",
-                &format_args!("{}", self.wdt_clk_prescale().bits()),
-            )
+            .field("wdt_clk_prescale", &self.wdt_clk_prescale())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 16:31 - MWDT clock prescaler value. MWDT clock period = 12.5 ns * TIMG_WDT_CLK_PRESCALE."]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/wdtconfig2.rs b/esp32s3/src/timg0/wdtconfig2.rs
index f6646544fa..70947ea581 100644
--- a/esp32s3/src/timg0/wdtconfig2.rs
+++ b/esp32s3/src/timg0/wdtconfig2.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG2")
-            .field(
-                "wdt_stg0_hold",
-                &format_args!("{}", self.wdt_stg0_hold().bits()),
-            )
+            .field("wdt_stg0_hold", &self.wdt_stg0_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 0 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/wdtconfig3.rs b/esp32s3/src/timg0/wdtconfig3.rs
index da0cf49ce2..63b4ed60f6 100644
--- a/esp32s3/src/timg0/wdtconfig3.rs
+++ b/esp32s3/src/timg0/wdtconfig3.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG3")
-            .field(
-                "wdt_stg1_hold",
-                &format_args!("{}", self.wdt_stg1_hold().bits()),
-            )
+            .field("wdt_stg1_hold", &self.wdt_stg1_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 1 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/wdtconfig4.rs b/esp32s3/src/timg0/wdtconfig4.rs
index 2bbbc5bfe8..d132842f1f 100644
--- a/esp32s3/src/timg0/wdtconfig4.rs
+++ b/esp32s3/src/timg0/wdtconfig4.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG4")
-            .field(
-                "wdt_stg2_hold",
-                &format_args!("{}", self.wdt_stg2_hold().bits()),
-            )
+            .field("wdt_stg2_hold", &self.wdt_stg2_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 2 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/wdtconfig5.rs b/esp32s3/src/timg0/wdtconfig5.rs
index 661482c54b..d101561533 100644
--- a/esp32s3/src/timg0/wdtconfig5.rs
+++ b/esp32s3/src/timg0/wdtconfig5.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTCONFIG5")
-            .field(
-                "wdt_stg3_hold",
-                &format_args!("{}", self.wdt_stg3_hold().bits()),
-            )
+            .field("wdt_stg3_hold", &self.wdt_stg3_hold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTCONFIG5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stage 3 timeout value, in MWDT clock cycles."]
     #[inline(always)]
diff --git a/esp32s3/src/timg0/wdtwprotect.rs b/esp32s3/src/timg0/wdtwprotect.rs
index 44efc107f3..ca73442322 100644
--- a/esp32s3/src/timg0/wdtwprotect.rs
+++ b/esp32s3/src/timg0/wdtwprotect.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WDTWPROTECT")
-            .field("wdt_wkey", &format_args!("{}", self.wdt_wkey().bits()))
+            .field("wdt_wkey", &self.wdt_wkey())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WDTWPROTECT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - If the register contains a different value than its reset value, write protection is enabled."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/arb_lost_cap.rs b/esp32s3/src/twai0/arb_lost_cap.rs
index 20ab158c4b..02b4812ac4 100644
--- a/esp32s3/src/twai0/arb_lost_cap.rs
+++ b/esp32s3/src/twai0/arb_lost_cap.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ARB_LOST_CAP")
-            .field(
-                "arb_lost_cap",
-                &format_args!("{}", self.arb_lost_cap().bits()),
-            )
+            .field("arb_lost_cap", &self.arb_lost_cap())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ARB_LOST_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Arbitration Lost Capture Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`arb_lost_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ARB_LOST_CAP_SPEC;
 impl crate::RegisterSpec for ARB_LOST_CAP_SPEC {
diff --git a/esp32s3/src/twai0/bus_timing_0.rs b/esp32s3/src/twai0/bus_timing_0.rs
index 4fe29d9648..c26ca19211 100644
--- a/esp32s3/src/twai0/bus_timing_0.rs
+++ b/esp32s3/src/twai0/bus_timing_0.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMING_0")
-            .field("baud_presc", &format_args!("{}", self.baud_presc().bits()))
-            .field(
-                "sync_jump_width",
-                &format_args!("{}", self.sync_jump_width().bits()),
-            )
+            .field("baud_presc", &self.baud_presc())
+            .field("sync_jump_width", &self.sync_jump_width())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMING_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:13 - Baud Rate Prescaler, determines the frequency dividing ratio."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/bus_timing_1.rs b/esp32s3/src/twai0/bus_timing_1.rs
index ec698b25b8..89a5dcc905 100644
--- a/esp32s3/src/twai0/bus_timing_1.rs
+++ b/esp32s3/src/twai0/bus_timing_1.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("BUS_TIMING_1")
-            .field("time_seg1", &format_args!("{}", self.time_seg1().bits()))
-            .field("time_seg2", &format_args!("{}", self.time_seg2().bits()))
-            .field("time_samp", &format_args!("{}", self.time_samp().bit()))
+            .field("time_seg1", &self.time_seg1())
+            .field("time_seg2", &self.time_seg2())
+            .field("time_samp", &self.time_samp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<BUS_TIMING_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - The width of PBS1."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/clock_divider.rs b/esp32s3/src/twai0/clock_divider.rs
index 9d5176aca5..3021eab737 100644
--- a/esp32s3/src/twai0/clock_divider.rs
+++ b/esp32s3/src/twai0/clock_divider.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLOCK_DIVIDER")
-            .field("cd", &format_args!("{}", self.cd().bits()))
-            .field("clock_off", &format_args!("{}", self.clock_off().bit()))
+            .field("cd", &self.cd())
+            .field("clock_off", &self.clock_off())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLOCK_DIVIDER_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - These bits are used to configure frequency dividing coefficients of the external CLKOUT pin."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/data_0.rs b/esp32s3/src/twai0/data_0.rs
index 921ebf3ab0..d87f222f23 100644
--- a/esp32s3/src/twai0/data_0.rs
+++ b/esp32s3/src/twai0/data_0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_0")
-            .field("tx_byte_0", &format_args!("{}", self.tx_byte_0().bits()))
+            .field("tx_byte_0", &self.tx_byte_0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/data_1.rs b/esp32s3/src/twai0/data_1.rs
index aacde9f161..1e7ca2029e 100644
--- a/esp32s3/src/twai0/data_1.rs
+++ b/esp32s3/src/twai0/data_1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_1")
-            .field("tx_byte_1", &format_args!("{}", self.tx_byte_1().bits()))
+            .field("tx_byte_1", &self.tx_byte_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/data_10.rs b/esp32s3/src/twai0/data_10.rs
index d978cb608a..77ea6c46e1 100644
--- a/esp32s3/src/twai0/data_10.rs
+++ b/esp32s3/src/twai0/data_10.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_10")
-            .field("tx_byte_10", &format_args!("{}", self.tx_byte_10().bits()))
+            .field("tx_byte_10", &self.tx_byte_10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stored the 10th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/data_11.rs b/esp32s3/src/twai0/data_11.rs
index 69b3c01179..ea0f6a7d35 100644
--- a/esp32s3/src/twai0/data_11.rs
+++ b/esp32s3/src/twai0/data_11.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_11")
-            .field("tx_byte_11", &format_args!("{}", self.tx_byte_11().bits()))
+            .field("tx_byte_11", &self.tx_byte_11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stored the 11th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/data_12.rs b/esp32s3/src/twai0/data_12.rs
index be60409250..d8afde2384 100644
--- a/esp32s3/src/twai0/data_12.rs
+++ b/esp32s3/src/twai0/data_12.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_12")
-            .field("tx_byte_12", &format_args!("{}", self.tx_byte_12().bits()))
+            .field("tx_byte_12", &self.tx_byte_12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stored the 12th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/data_2.rs b/esp32s3/src/twai0/data_2.rs
index 8dfbf55812..f993610525 100644
--- a/esp32s3/src/twai0/data_2.rs
+++ b/esp32s3/src/twai0/data_2.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_2")
-            .field("tx_byte_2", &format_args!("{}", self.tx_byte_2().bits()))
+            .field("tx_byte_2", &self.tx_byte_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/data_3.rs b/esp32s3/src/twai0/data_3.rs
index af279627a4..60075e6328 100644
--- a/esp32s3/src/twai0/data_3.rs
+++ b/esp32s3/src/twai0/data_3.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_3")
-            .field("tx_byte_3", &format_args!("{}", self.tx_byte_3().bits()))
+            .field("tx_byte_3", &self.tx_byte_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/data_4.rs b/esp32s3/src/twai0/data_4.rs
index b55cb89b50..d64e72daaa 100644
--- a/esp32s3/src/twai0/data_4.rs
+++ b/esp32s3/src/twai0/data_4.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_4")
-            .field("tx_byte_4", &format_args!("{}", self.tx_byte_4().bits()))
+            .field("tx_byte_4", &self.tx_byte_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/data_5.rs b/esp32s3/src/twai0/data_5.rs
index 81b906ce88..0378e6b32e 100644
--- a/esp32s3/src/twai0/data_5.rs
+++ b/esp32s3/src/twai0/data_5.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_5")
-            .field("tx_byte_5", &format_args!("{}", self.tx_byte_5().bits()))
+            .field("tx_byte_5", &self.tx_byte_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/data_6.rs b/esp32s3/src/twai0/data_6.rs
index 9ea130bcfc..0de8e69ce7 100644
--- a/esp32s3/src/twai0/data_6.rs
+++ b/esp32s3/src/twai0/data_6.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_6")
-            .field("tx_byte_6", &format_args!("{}", self.tx_byte_6().bits()))
+            .field("tx_byte_6", &self.tx_byte_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/data_7.rs b/esp32s3/src/twai0/data_7.rs
index 4081ec2628..0339194cea 100644
--- a/esp32s3/src/twai0/data_7.rs
+++ b/esp32s3/src/twai0/data_7.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_7")
-            .field("tx_byte_7", &format_args!("{}", self.tx_byte_7().bits()))
+            .field("tx_byte_7", &self.tx_byte_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/data_8.rs b/esp32s3/src/twai0/data_8.rs
index 29694983b1..09ffc85913 100644
--- a/esp32s3/src/twai0/data_8.rs
+++ b/esp32s3/src/twai0/data_8.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_8")
-            .field("tx_byte_8", &format_args!("{}", self.tx_byte_8().bits()))
+            .field("tx_byte_8", &self.tx_byte_8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stored the 8th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/data_9.rs b/esp32s3/src/twai0/data_9.rs
index 6cb211c10e..60f9949a12 100644
--- a/esp32s3/src/twai0/data_9.rs
+++ b/esp32s3/src/twai0/data_9.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATA_9")
-            .field("tx_byte_9", &format_args!("{}", self.tx_byte_9().bits()))
+            .field("tx_byte_9", &self.tx_byte_9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATA_9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Stored the 9th byte information of the data to be transmitted under operating mode."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/err_code_cap.rs b/esp32s3/src/twai0/err_code_cap.rs
index 77f4f8b361..f4ce2b4b16 100644
--- a/esp32s3/src/twai0/err_code_cap.rs
+++ b/esp32s3/src/twai0/err_code_cap.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERR_CODE_CAP")
-            .field(
-                "ecc_segment",
-                &format_args!("{}", self.ecc_segment().bits()),
-            )
-            .field(
-                "ecc_direction",
-                &format_args!("{}", self.ecc_direction().bit()),
-            )
-            .field("ecc_type", &format_args!("{}", self.ecc_type().bits()))
+            .field("ecc_segment", &self.ecc_segment())
+            .field("ecc_direction", &self.ecc_direction())
+            .field("ecc_type", &self.ecc_type())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERR_CODE_CAP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Error Code Capture Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_code_cap::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ERR_CODE_CAP_SPEC;
 impl crate::RegisterSpec for ERR_CODE_CAP_SPEC {
diff --git a/esp32s3/src/twai0/err_warning_limit.rs b/esp32s3/src/twai0/err_warning_limit.rs
index eaca9801b5..0197a2df38 100644
--- a/esp32s3/src/twai0/err_warning_limit.rs
+++ b/esp32s3/src/twai0/err_warning_limit.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ERR_WARNING_LIMIT")
-            .field(
-                "err_warning_limit",
-                &format_args!("{}", self.err_warning_limit().bits()),
-            )
+            .field("err_warning_limit", &self.err_warning_limit())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ERR_WARNING_LIMIT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid)."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/int_ena.rs b/esp32s3/src/twai0/int_ena.rs
index 750cc94df5..01ac1eef65 100644
--- a/esp32s3/src/twai0/int_ena.rs
+++ b/esp32s3/src/twai0/int_ena.rs
@@ -71,37 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_int_ena", &format_args!("{}", self.rx_int_ena().bit()))
-            .field("tx_int_ena", &format_args!("{}", self.tx_int_ena().bit()))
-            .field(
-                "err_warn_int_ena",
-                &format_args!("{}", self.err_warn_int_ena().bit()),
-            )
-            .field(
-                "overrun_int_ena",
-                &format_args!("{}", self.overrun_int_ena().bit()),
-            )
-            .field(
-                "err_passive_int_ena",
-                &format_args!("{}", self.err_passive_int_ena().bit()),
-            )
-            .field(
-                "arb_lost_int_ena",
-                &format_args!("{}", self.arb_lost_int_ena().bit()),
-            )
-            .field(
-                "bus_err_int_ena",
-                &format_args!("{}", self.bus_err_int_ena().bit()),
-            )
+            .field("rx_int_ena", &self.rx_int_ena())
+            .field("tx_int_ena", &self.tx_int_ena())
+            .field("err_warn_int_ena", &self.err_warn_int_ena())
+            .field("overrun_int_ena", &self.overrun_int_ena())
+            .field("err_passive_int_ena", &self.err_passive_int_ena())
+            .field("arb_lost_int_ena", &self.arb_lost_int_ena())
+            .field("bus_err_int_ena", &self.bus_err_int_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to 1 to enable receive interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/int_raw.rs b/esp32s3/src/twai0/int_raw.rs
index bcb5a07717..fe0b2105a8 100644
--- a/esp32s3/src/twai0/int_raw.rs
+++ b/esp32s3/src/twai0/int_raw.rs
@@ -55,37 +55,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_int_st", &format_args!("{}", self.rx_int_st().bit()))
-            .field("tx_int_st", &format_args!("{}", self.tx_int_st().bit()))
-            .field(
-                "err_warn_int_st",
-                &format_args!("{}", self.err_warn_int_st().bit()),
-            )
-            .field(
-                "overrun_int_st",
-                &format_args!("{}", self.overrun_int_st().bit()),
-            )
-            .field(
-                "err_passive_int_st",
-                &format_args!("{}", self.err_passive_int_st().bit()),
-            )
-            .field(
-                "arb_lost_int_st",
-                &format_args!("{}", self.arb_lost_int_st().bit()),
-            )
-            .field(
-                "bus_err_int_st",
-                &format_args!("{}", self.bus_err_int_st().bit()),
-            )
+            .field("rx_int_st", &self.rx_int_st())
+            .field("tx_int_st", &self.tx_int_st())
+            .field("err_warn_int_st", &self.err_warn_int_st())
+            .field("overrun_int_st", &self.overrun_int_st())
+            .field("err_passive_int_st", &self.err_passive_int_st())
+            .field("arb_lost_int_st", &self.arb_lost_int_st())
+            .field("bus_err_int_st", &self.bus_err_int_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_RAW_SPEC;
 impl crate::RegisterSpec for INT_RAW_SPEC {
diff --git a/esp32s3/src/twai0/mode.rs b/esp32s3/src/twai0/mode.rs
index dc3560c7e3..0d66f9a85c 100644
--- a/esp32s3/src/twai0/mode.rs
+++ b/esp32s3/src/twai0/mode.rs
@@ -44,28 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MODE")
-            .field("reset_mode", &format_args!("{}", self.reset_mode().bit()))
-            .field(
-                "listen_only_mode",
-                &format_args!("{}", self.listen_only_mode().bit()),
-            )
-            .field(
-                "self_test_mode",
-                &format_args!("{}", self.self_test_mode().bit()),
-            )
-            .field(
-                "rx_filter_mode",
-                &format_args!("{}", self.rx_filter_mode().bit()),
-            )
+            .field("reset_mode", &self.reset_mode())
+            .field("listen_only_mode", &self.listen_only_mode())
+            .field("self_test_mode", &self.self_test_mode())
+            .field("rx_filter_mode", &self.rx_filter_mode())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MODE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/rx_err_cnt.rs b/esp32s3/src/twai0/rx_err_cnt.rs
index 66bf5c5d52..9c05d16bf3 100644
--- a/esp32s3/src/twai0/rx_err_cnt.rs
+++ b/esp32s3/src/twai0/rx_err_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_ERR_CNT")
-            .field("rx_err_cnt", &format_args!("{}", self.rx_err_cnt().bits()))
+            .field("rx_err_cnt", &self.rx_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_ERR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The RX error counter register, reflects value changes under reception status."]
     #[inline(always)]
diff --git a/esp32s3/src/twai0/rx_message_cnt.rs b/esp32s3/src/twai0/rx_message_cnt.rs
index 606f9b251e..13ca2f8eb4 100644
--- a/esp32s3/src/twai0/rx_message_cnt.rs
+++ b/esp32s3/src/twai0/rx_message_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_MESSAGE_CNT")
-            .field(
-                "rx_message_counter",
-                &format_args!("{}", self.rx_message_counter().bits()),
-            )
+            .field("rx_message_counter", &self.rx_message_counter())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_MESSAGE_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Receive Message Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_message_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_MESSAGE_CNT_SPEC;
 impl crate::RegisterSpec for RX_MESSAGE_CNT_SPEC {
diff --git a/esp32s3/src/twai0/status.rs b/esp32s3/src/twai0/status.rs
index c9d0dd58e5..9a577030bd 100644
--- a/esp32s3/src/twai0/status.rs
+++ b/esp32s3/src/twai0/status.rs
@@ -69,24 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rx_buf_st", &format_args!("{}", self.rx_buf_st().bit()))
-            .field("overrun_st", &format_args!("{}", self.overrun_st().bit()))
-            .field("tx_buf_st", &format_args!("{}", self.tx_buf_st().bit()))
-            .field("tx_complete", &format_args!("{}", self.tx_complete().bit()))
-            .field("rx_st", &format_args!("{}", self.rx_st().bit()))
-            .field("tx_st", &format_args!("{}", self.tx_st().bit()))
-            .field("err_st", &format_args!("{}", self.err_st().bit()))
-            .field("bus_off_st", &format_args!("{}", self.bus_off_st().bit()))
-            .field("miss_st", &format_args!("{}", self.miss_st().bit()))
+            .field("rx_buf_st", &self.rx_buf_st())
+            .field("overrun_st", &self.overrun_st())
+            .field("tx_buf_st", &self.tx_buf_st())
+            .field("tx_complete", &self.tx_complete())
+            .field("rx_st", &self.rx_st())
+            .field("tx_st", &self.tx_st())
+            .field("err_st", &self.err_st())
+            .field("bus_off_st", &self.bus_off_st())
+            .field("miss_st", &self.miss_st())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32s3/src/twai0/tx_err_cnt.rs b/esp32s3/src/twai0/tx_err_cnt.rs
index 3fb0a9d0ef..5d5b84441c 100644
--- a/esp32s3/src/twai0/tx_err_cnt.rs
+++ b/esp32s3/src/twai0/tx_err_cnt.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TX_ERR_CNT")
-            .field("tx_err_cnt", &format_args!("{}", self.tx_err_cnt().bits()))
+            .field("tx_err_cnt", &self.tx_err_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TX_ERR_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - The TX error counter register, reflects value changes under transmission status."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/at_cmd_char.rs b/esp32s3/src/uart0/at_cmd_char.rs
index 17e9222fe8..e75e1409cd 100644
--- a/esp32s3/src/uart0/at_cmd_char.rs
+++ b/esp32s3/src/uart0/at_cmd_char.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_CHAR")
-            .field(
-                "at_cmd_char",
-                &format_args!("{}", self.at_cmd_char().bits()),
-            )
-            .field("char_num", &format_args!("{}", self.char_num().bits()))
+            .field("at_cmd_char", &self.at_cmd_char())
+            .field("char_num", &self.char_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_CHAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the content of at_cmd char."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/at_cmd_gaptout.rs b/esp32s3/src/uart0/at_cmd_gaptout.rs
index c7373436b0..7091ac8125 100644
--- a/esp32s3/src/uart0/at_cmd_gaptout.rs
+++ b/esp32s3/src/uart0/at_cmd_gaptout.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_GAPTOUT")
-            .field(
-                "rx_gap_tout",
-                &format_args!("{}", self.rx_gap_tout().bits()),
-            )
+            .field("rx_gap_tout", &self.rx_gap_tout())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_GAPTOUT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the at_cmd chars."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/at_cmd_postcnt.rs b/esp32s3/src/uart0/at_cmd_postcnt.rs
index 078c4bb6a1..5db8445554 100644
--- a/esp32s3/src/uart0/at_cmd_postcnt.rs
+++ b/esp32s3/src/uart0/at_cmd_postcnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_POSTCNT")
-            .field(
-                "post_idle_num",
-                &format_args!("{}", self.post_idle_num().bits()),
-            )
+            .field("post_idle_num", &self.post_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_POSTCNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the duration time between the last at_cmd and the next data."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/at_cmd_precnt.rs b/esp32s3/src/uart0/at_cmd_precnt.rs
index 9e4a1cc58c..41790b5e67 100644
--- a/esp32s3/src/uart0/at_cmd_precnt.rs
+++ b/esp32s3/src/uart0/at_cmd_precnt.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("AT_CMD_PRECNT")
-            .field(
-                "pre_idle_num",
-                &format_args!("{}", self.pre_idle_num().bits()),
-            )
+            .field("pre_idle_num", &self.pre_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<AT_CMD_PRECNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15 - This register is used to configure the idle duration time before the first at_cmd is received by receiver."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/clk_conf.rs b/esp32s3/src/uart0/clk_conf.rs
index 0ddb29638f..9f3c3a3eb2 100644
--- a/esp32s3/src/uart0/clk_conf.rs
+++ b/esp32s3/src/uart0/clk_conf.rs
@@ -98,28 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLK_CONF")
-            .field("sclk_div_b", &format_args!("{}", self.sclk_div_b().bits()))
-            .field("sclk_div_a", &format_args!("{}", self.sclk_div_a().bits()))
-            .field(
-                "sclk_div_num",
-                &format_args!("{}", self.sclk_div_num().bits()),
-            )
-            .field("sclk_sel", &format_args!("{}", self.sclk_sel().bits()))
-            .field("sclk_en", &format_args!("{}", self.sclk_en().bit()))
-            .field("rst_core", &format_args!("{}", self.rst_core().bit()))
-            .field("tx_sclk_en", &format_args!("{}", self.tx_sclk_en().bit()))
-            .field("rx_sclk_en", &format_args!("{}", self.rx_sclk_en().bit()))
-            .field("tx_rst_core", &format_args!("{}", self.tx_rst_core().bit()))
-            .field("rx_rst_core", &format_args!("{}", self.rx_rst_core().bit()))
+            .field("sclk_div_b", &self.sclk_div_b())
+            .field("sclk_div_a", &self.sclk_div_a())
+            .field("sclk_div_num", &self.sclk_div_num())
+            .field("sclk_sel", &self.sclk_sel())
+            .field("sclk_en", &self.sclk_en())
+            .field("rst_core", &self.rst_core())
+            .field("tx_sclk_en", &self.tx_sclk_en())
+            .field("rx_sclk_en", &self.rx_sclk_en())
+            .field("tx_rst_core", &self.tx_rst_core())
+            .field("rx_rst_core", &self.rx_rst_core())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:5 - The denominator of the frequency divider factor."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/clkdiv.rs b/esp32s3/src/uart0/clkdiv.rs
index c020543f66..0c1138e013 100644
--- a/esp32s3/src/uart0/clkdiv.rs
+++ b/esp32s3/src/uart0/clkdiv.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CLKDIV")
-            .field("clkdiv", &format_args!("{}", self.clkdiv().bits()))
-            .field("frag", &format_args!("{}", self.frag().bits()))
+            .field("clkdiv", &self.clkdiv())
+            .field("frag", &self.frag())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CLKDIV_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/conf0.rs b/esp32s3/src/uart0/conf0.rs
index a2981cbdc7..880c32a12e 100644
--- a/esp32s3/src/uart0/conf0.rs
+++ b/esp32s3/src/uart0/conf0.rs
@@ -251,45 +251,36 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("parity", &format_args!("{}", self.parity().bit()))
-            .field("parity_en", &format_args!("{}", self.parity_en().bit()))
-            .field("bit_num", &format_args!("{}", self.bit_num().bits()))
-            .field(
-                "stop_bit_num",
-                &format_args!("{}", self.stop_bit_num().bits()),
-            )
-            .field("sw_rts", &format_args!("{}", self.sw_rts().bit()))
-            .field("sw_dtr", &format_args!("{}", self.sw_dtr().bit()))
-            .field("txd_brk", &format_args!("{}", self.txd_brk().bit()))
-            .field("irda_dplx", &format_args!("{}", self.irda_dplx().bit()))
-            .field("irda_tx_en", &format_args!("{}", self.irda_tx_en().bit()))
-            .field("irda_wctl", &format_args!("{}", self.irda_wctl().bit()))
-            .field("irda_tx_inv", &format_args!("{}", self.irda_tx_inv().bit()))
-            .field("irda_rx_inv", &format_args!("{}", self.irda_rx_inv().bit()))
-            .field("loopback", &format_args!("{}", self.loopback().bit()))
-            .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit()))
-            .field("irda_en", &format_args!("{}", self.irda_en().bit()))
-            .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit()))
-            .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit()))
-            .field("rxd_inv", &format_args!("{}", self.rxd_inv().bit()))
-            .field("cts_inv", &format_args!("{}", self.cts_inv().bit()))
-            .field("dsr_inv", &format_args!("{}", self.dsr_inv().bit()))
-            .field("txd_inv", &format_args!("{}", self.txd_inv().bit()))
-            .field("rts_inv", &format_args!("{}", self.rts_inv().bit()))
-            .field("dtr_inv", &format_args!("{}", self.dtr_inv().bit()))
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field("err_wr_mask", &format_args!("{}", self.err_wr_mask().bit()))
-            .field("autobaud_en", &format_args!("{}", self.autobaud_en().bit()))
-            .field("mem_clk_en", &format_args!("{}", self.mem_clk_en().bit()))
+            .field("parity", &self.parity())
+            .field("parity_en", &self.parity_en())
+            .field("bit_num", &self.bit_num())
+            .field("stop_bit_num", &self.stop_bit_num())
+            .field("sw_rts", &self.sw_rts())
+            .field("sw_dtr", &self.sw_dtr())
+            .field("txd_brk", &self.txd_brk())
+            .field("irda_dplx", &self.irda_dplx())
+            .field("irda_tx_en", &self.irda_tx_en())
+            .field("irda_wctl", &self.irda_wctl())
+            .field("irda_tx_inv", &self.irda_tx_inv())
+            .field("irda_rx_inv", &self.irda_rx_inv())
+            .field("loopback", &self.loopback())
+            .field("tx_flow_en", &self.tx_flow_en())
+            .field("irda_en", &self.irda_en())
+            .field("rxfifo_rst", &self.rxfifo_rst())
+            .field("txfifo_rst", &self.txfifo_rst())
+            .field("rxd_inv", &self.rxd_inv())
+            .field("cts_inv", &self.cts_inv())
+            .field("dsr_inv", &self.dsr_inv())
+            .field("txd_inv", &self.txd_inv())
+            .field("rts_inv", &self.rts_inv())
+            .field("dtr_inv", &self.dtr_inv())
+            .field("clk_en", &self.clk_en())
+            .field("err_wr_mask", &self.err_wr_mask())
+            .field("autobaud_en", &self.autobaud_en())
+            .field("mem_clk_en", &self.mem_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This register is used to configure the parity check mode."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/conf1.rs b/esp32s3/src/uart0/conf1.rs
index 0405cb3a4b..455ec28358 100644
--- a/esp32s3/src/uart0/conf1.rs
+++ b/esp32s3/src/uart0/conf1.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "rxfifo_full_thrhd",
-                &format_args!("{}", self.rxfifo_full_thrhd().bits()),
-            )
-            .field(
-                "txfifo_empty_thrhd",
-                &format_args!("{}", self.txfifo_empty_thrhd().bits()),
-            )
-            .field(
-                "dis_rx_dat_ovf",
-                &format_args!("{}", self.dis_rx_dat_ovf().bit()),
-            )
-            .field(
-                "rx_tout_flow_dis",
-                &format_args!("{}", self.rx_tout_flow_dis().bit()),
-            )
-            .field("rx_flow_en", &format_args!("{}", self.rx_flow_en().bit()))
-            .field("rx_tout_en", &format_args!("{}", self.rx_tout_en().bit()))
+            .field("rxfifo_full_thrhd", &self.rxfifo_full_thrhd())
+            .field("txfifo_empty_thrhd", &self.txfifo_empty_thrhd())
+            .field("dis_rx_dat_ovf", &self.dis_rx_dat_ovf())
+            .field("rx_tout_flow_dis", &self.rx_tout_flow_dis())
+            .field("rx_flow_en", &self.rx_flow_en())
+            .field("rx_tout_en", &self.rx_tout_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/date.rs b/esp32s3/src/uart0/date.rs
index 816469bbff..ac4c156a82 100644
--- a/esp32s3/src/uart0/date.rs
+++ b/esp32s3/src/uart0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/uart0/fifo.rs b/esp32s3/src/uart0/fifo.rs
index 3ea719e7ab..fdc9ee6700 100644
--- a/esp32s3/src/uart0/fifo.rs
+++ b/esp32s3/src/uart0/fifo.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FIFO")
-            .field(
-                "rxfifo_rd_byte",
-                &format_args!("{}", self.rxfifo_rd_byte().bits()),
-            )
+            .field("rxfifo_rd_byte", &self.rxfifo_rd_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - UART 0 accesses FIFO via this register."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/flow_conf.rs b/esp32s3/src/uart0/flow_conf.rs
index f20cf9572e..215821f1b6 100644
--- a/esp32s3/src/uart0/flow_conf.rs
+++ b/esp32s3/src/uart0/flow_conf.rs
@@ -62,24 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FLOW_CONF")
-            .field(
-                "sw_flow_con_en",
-                &format_args!("{}", self.sw_flow_con_en().bit()),
-            )
-            .field("xonoff_del", &format_args!("{}", self.xonoff_del().bit()))
-            .field("force_xon", &format_args!("{}", self.force_xon().bit()))
-            .field("force_xoff", &format_args!("{}", self.force_xoff().bit()))
-            .field("send_xon", &format_args!("{}", self.send_xon().bit()))
-            .field("send_xoff", &format_args!("{}", self.send_xoff().bit()))
+            .field("sw_flow_con_en", &self.sw_flow_con_en())
+            .field("xonoff_del", &self.xonoff_del())
+            .field("force_xon", &self.force_xon())
+            .field("force_xoff", &self.force_xoff())
+            .field("send_xon", &self.send_xon())
+            .field("send_xoff", &self.send_xoff())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FLOW_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/fsm_status.rs b/esp32s3/src/uart0/fsm_status.rs
index 7e47b06bf6..4088ac153f 100644
--- a/esp32s3/src/uart0/fsm_status.rs
+++ b/esp32s3/src/uart0/fsm_status.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FSM_STATUS")
-            .field("st_urx_out", &format_args!("{}", self.st_urx_out().bits()))
-            .field("st_utx_out", &format_args!("{}", self.st_utx_out().bits()))
+            .field("st_urx_out", &self.st_urx_out())
+            .field("st_utx_out", &self.st_utx_out())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FSM_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART transmit and receive status.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsm_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FSM_STATUS_SPEC;
 impl crate::RegisterSpec for FSM_STATUS_SPEC {
diff --git a/esp32s3/src/uart0/highpulse.rs b/esp32s3/src/uart0/highpulse.rs
index 2a100f783a..8445906dbf 100644
--- a/esp32s3/src/uart0/highpulse.rs
+++ b/esp32s3/src/uart0/highpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HIGHPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HIGHPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud minimum high pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`highpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HIGHPULSE_SPEC;
 impl crate::RegisterSpec for HIGHPULSE_SPEC {
diff --git a/esp32s3/src/uart0/id.rs b/esp32s3/src/uart0/id.rs
index a379a1b045..d398acf67f 100644
--- a/esp32s3/src/uart0/id.rs
+++ b/esp32s3/src/uart0/id.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ID")
-            .field("id", &format_args!("{}", self.id().bits()))
-            .field("high_speed", &format_args!("{}", self.high_speed().bit()))
-            .field("reg_update", &format_args!("{}", self.reg_update().bit()))
+            .field("id", &self.id())
+            .field("high_speed", &self.high_speed())
+            .field("reg_update", &self.reg_update())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - This register is used to configure the uart_id."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/idle_conf.rs b/esp32s3/src/uart0/idle_conf.rs
index bc986732bf..a2f200e19e 100644
--- a/esp32s3/src/uart0/idle_conf.rs
+++ b/esp32s3/src/uart0/idle_conf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IDLE_CONF")
-            .field(
-                "rx_idle_thrhd",
-                &format_args!("{}", self.rx_idle_thrhd().bits()),
-            )
-            .field(
-                "tx_idle_num",
-                &format_args!("{}", self.tx_idle_num().bits()),
-            )
+            .field("rx_idle_thrhd", &self.rx_idle_thrhd())
+            .field("tx_idle_num", &self.tx_idle_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IDLE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - It will produce frame end signal when receiver takes more time to receive one byte data than this register value."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/int_ena.rs b/esp32s3/src/uart0/int_ena.rs
index fea57f25bd..3a8a9f2f95 100644
--- a/esp32s3/src/uart0/int_ena.rs
+++ b/esp32s3/src/uart0/int_ena.rs
@@ -188,50 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/int_raw.rs b/esp32s3/src/uart0/int_raw.rs
index 525414943b..5a2e80fea2 100644
--- a/esp32s3/src/uart0/int_raw.rs
+++ b/esp32s3/src/uart0/int_raw.rs
@@ -188,50 +188,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/int_st.rs b/esp32s3/src/uart0/int_st.rs
index 417bc433a0..c67c7f4b75 100644
--- a/esp32s3/src/uart0/int_st.rs
+++ b/esp32s3/src/uart0/int_st.rs
@@ -146,50 +146,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
-            .field(
-                "txfifo_empty",
-                &format_args!("{}", self.txfifo_empty().bit()),
-            )
-            .field("parity_err", &format_args!("{}", self.parity_err().bit()))
-            .field("frm_err", &format_args!("{}", self.frm_err().bit()))
-            .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
-            .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
-            .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
-            .field("brk_det", &format_args!("{}", self.brk_det().bit()))
-            .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
-            .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
-            .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
-            .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
-            .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
-            .field(
-                "tx_brk_idle_done",
-                &format_args!("{}", self.tx_brk_idle_done().bit()),
-            )
-            .field("tx_done", &format_args!("{}", self.tx_done().bit()))
-            .field(
-                "rs485_parity_err",
-                &format_args!("{}", self.rs485_parity_err().bit()),
-            )
-            .field(
-                "rs485_frm_err",
-                &format_args!("{}", self.rs485_frm_err().bit()),
-            )
-            .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
-            .field(
-                "at_cmd_char_det",
-                &format_args!("{}", self.at_cmd_char_det().bit()),
-            )
-            .field("wakeup", &format_args!("{}", self.wakeup().bit()))
+            .field("rxfifo_full", &self.rxfifo_full())
+            .field("txfifo_empty", &self.txfifo_empty())
+            .field("parity_err", &self.parity_err())
+            .field("frm_err", &self.frm_err())
+            .field("rxfifo_ovf", &self.rxfifo_ovf())
+            .field("dsr_chg", &self.dsr_chg())
+            .field("cts_chg", &self.cts_chg())
+            .field("brk_det", &self.brk_det())
+            .field("rxfifo_tout", &self.rxfifo_tout())
+            .field("sw_xon", &self.sw_xon())
+            .field("sw_xoff", &self.sw_xoff())
+            .field("glitch_det", &self.glitch_det())
+            .field("tx_brk_done", &self.tx_brk_done())
+            .field("tx_brk_idle_done", &self.tx_brk_idle_done())
+            .field("tx_done", &self.tx_done())
+            .field("rs485_parity_err", &self.rs485_parity_err())
+            .field("rs485_frm_err", &self.rs485_frm_err())
+            .field("rs485_clash", &self.rs485_clash())
+            .field("at_cmd_char_det", &self.at_cmd_char_det())
+            .field("wakeup", &self.wakeup())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/uart0/lowpulse.rs b/esp32s3/src/uart0/lowpulse.rs
index 6736272863..03a2b35c08 100644
--- a/esp32s3/src/uart0/lowpulse.rs
+++ b/esp32s3/src/uart0/lowpulse.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LOWPULSE")
-            .field("min_cnt", &format_args!("{}", self.min_cnt().bits()))
+            .field("min_cnt", &self.min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LOWPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud minimum low pulse duration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lowpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct LOWPULSE_SPEC;
 impl crate::RegisterSpec for LOWPULSE_SPEC {
diff --git a/esp32s3/src/uart0/mem_conf.rs b/esp32s3/src/uart0/mem_conf.rs
index 4b3a9dbbd7..6df6219ffd 100644
--- a/esp32s3/src/uart0/mem_conf.rs
+++ b/esp32s3/src/uart0/mem_conf.rs
@@ -62,33 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field("rx_size", &format_args!("{}", self.rx_size().bits()))
-            .field("tx_size", &format_args!("{}", self.tx_size().bits()))
-            .field(
-                "rx_flow_thrhd",
-                &format_args!("{}", self.rx_flow_thrhd().bits()),
-            )
-            .field(
-                "rx_tout_thrhd",
-                &format_args!("{}", self.rx_tout_thrhd().bits()),
-            )
-            .field(
-                "mem_force_pd",
-                &format_args!("{}", self.mem_force_pd().bit()),
-            )
-            .field(
-                "mem_force_pu",
-                &format_args!("{}", self.mem_force_pu().bit()),
-            )
+            .field("rx_size", &self.rx_size())
+            .field("tx_size", &self.tx_size())
+            .field("rx_flow_thrhd", &self.rx_flow_thrhd())
+            .field("rx_tout_thrhd", &self.rx_tout_thrhd())
+            .field("mem_force_pd", &self.mem_force_pd())
+            .field("mem_force_pu", &self.mem_force_pu())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 1:3 - This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/mem_rx_status.rs b/esp32s3/src/uart0/mem_rx_status.rs
index 3d566ff0be..b6a319de1c 100644
--- a/esp32s3/src/uart0/mem_rx_status.rs
+++ b/esp32s3/src/uart0/mem_rx_status.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_RX_STATUS")
-            .field(
-                "apb_rx_raddr",
-                &format_args!("{}", self.apb_rx_raddr().bits()),
-            )
-            .field("rx_waddr", &format_args!("{}", self.rx_waddr().bits()))
+            .field("apb_rx_raddr", &self.apb_rx_raddr())
+            .field("rx_waddr", &self.rx_waddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_RX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Rx-FIFO write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_rx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_RX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_RX_STATUS_SPEC {
diff --git a/esp32s3/src/uart0/mem_tx_status.rs b/esp32s3/src/uart0/mem_tx_status.rs
index cacd384e62..9ddad52610 100644
--- a/esp32s3/src/uart0/mem_tx_status.rs
+++ b/esp32s3/src/uart0/mem_tx_status.rs
@@ -20,20 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_TX_STATUS")
-            .field(
-                "apb_tx_waddr",
-                &format_args!("{}", self.apb_tx_waddr().bits()),
-            )
-            .field("tx_raddr", &format_args!("{}", self.tx_raddr().bits()))
+            .field("apb_tx_waddr", &self.apb_tx_waddr())
+            .field("tx_raddr", &self.tx_raddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_TX_STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Tx-FIFO write and read offset address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mem_tx_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct MEM_TX_STATUS_SPEC;
 impl crate::RegisterSpec for MEM_TX_STATUS_SPEC {
diff --git a/esp32s3/src/uart0/negpulse.rs b/esp32s3/src/uart0/negpulse.rs
index 0daf3b983f..d033b00895 100644
--- a/esp32s3/src/uart0/negpulse.rs
+++ b/esp32s3/src/uart0/negpulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("NEGPULSE")
-            .field(
-                "negedge_min_cnt",
-                &format_args!("{}", self.negedge_min_cnt().bits()),
-            )
+            .field("negedge_min_cnt", &self.negedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<NEGPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud low pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`negpulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NEGPULSE_SPEC;
 impl crate::RegisterSpec for NEGPULSE_SPEC {
diff --git a/esp32s3/src/uart0/pospulse.rs b/esp32s3/src/uart0/pospulse.rs
index 67a98ae05f..acf540a226 100644
--- a/esp32s3/src/uart0/pospulse.rs
+++ b/esp32s3/src/uart0/pospulse.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("POSPULSE")
-            .field(
-                "posedge_min_cnt",
-                &format_args!("{}", self.posedge_min_cnt().bits()),
-            )
+            .field("posedge_min_cnt", &self.posedge_min_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<POSPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud high pulse register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pospulse::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct POSPULSE_SPEC;
 impl crate::RegisterSpec for POSPULSE_SPEC {
diff --git a/esp32s3/src/uart0/rs485_conf.rs b/esp32s3/src/uart0/rs485_conf.rs
index 5480b03198..dbf27d91ba 100644
--- a/esp32s3/src/uart0/rs485_conf.rs
+++ b/esp32s3/src/uart0/rs485_conf.rs
@@ -71,34 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RS485_CONF")
-            .field("rs485_en", &format_args!("{}", self.rs485_en().bit()))
-            .field("dl0_en", &format_args!("{}", self.dl0_en().bit()))
-            .field("dl1_en", &format_args!("{}", self.dl1_en().bit()))
-            .field(
-                "rs485tx_rx_en",
-                &format_args!("{}", self.rs485tx_rx_en().bit()),
-            )
-            .field(
-                "rs485rxby_tx_en",
-                &format_args!("{}", self.rs485rxby_tx_en().bit()),
-            )
-            .field(
-                "rs485_rx_dly_num",
-                &format_args!("{}", self.rs485_rx_dly_num().bit()),
-            )
-            .field(
-                "rs485_tx_dly_num",
-                &format_args!("{}", self.rs485_tx_dly_num().bits()),
-            )
+            .field("rs485_en", &self.rs485_en())
+            .field("dl0_en", &self.dl0_en())
+            .field("dl1_en", &self.dl1_en())
+            .field("rs485tx_rx_en", &self.rs485tx_rx_en())
+            .field("rs485rxby_tx_en", &self.rs485rxby_tx_en())
+            .field("rs485_rx_dly_num", &self.rs485_rx_dly_num())
+            .field("rs485_tx_dly_num", &self.rs485_tx_dly_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RS485_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to choose the rs485 mode."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/rx_filt.rs b/esp32s3/src/uart0/rx_filt.rs
index 8b59a9e77a..c19d58140c 100644
--- a/esp32s3/src/uart0/rx_filt.rs
+++ b/esp32s3/src/uart0/rx_filt.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_FILT")
-            .field(
-                "glitch_filt",
-                &format_args!("{}", self.glitch_filt().bits()),
-            )
-            .field(
-                "glitch_filt_en",
-                &format_args!("{}", self.glitch_filt_en().bit()),
-            )
+            .field("glitch_filt", &self.glitch_filt())
+            .field("glitch_filt_en", &self.glitch_filt_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_FILT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - when input pulse width is lower than this value, the pulse is ignored."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/rxd_cnt.rs b/esp32s3/src/uart0/rxd_cnt.rs
index f08d5e0323..c3c3052a66 100644
--- a/esp32s3/src/uart0/rxd_cnt.rs
+++ b/esp32s3/src/uart0/rxd_cnt.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RXD_CNT")
-            .field(
-                "rxd_edge_cnt",
-                &format_args!("{}", self.rxd_edge_cnt().bits()),
-            )
+            .field("rxd_edge_cnt", &self.rxd_edge_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RXD_CNT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Autobaud edge change count register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxd_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RXD_CNT_SPEC;
 impl crate::RegisterSpec for RXD_CNT_SPEC {
diff --git a/esp32s3/src/uart0/sleep_conf.rs b/esp32s3/src/uart0/sleep_conf.rs
index 1715cd71a2..bfe6d45eb0 100644
--- a/esp32s3/src/uart0/sleep_conf.rs
+++ b/esp32s3/src/uart0/sleep_conf.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SLEEP_CONF")
-            .field(
-                "active_threshold",
-                &format_args!("{}", self.active_threshold().bits()),
-            )
+            .field("active_threshold", &self.active_threshold())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SLEEP_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/status.rs b/esp32s3/src/uart0/status.rs
index 4e1eee73c3..43e7f84e00 100644
--- a/esp32s3/src/uart0/status.rs
+++ b/esp32s3/src/uart0/status.rs
@@ -62,23 +62,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATUS")
-            .field("rxfifo_cnt", &format_args!("{}", self.rxfifo_cnt().bits()))
-            .field("dsrn", &format_args!("{}", self.dsrn().bit()))
-            .field("ctsn", &format_args!("{}", self.ctsn().bit()))
-            .field("rxd", &format_args!("{}", self.rxd().bit()))
-            .field("txfifo_cnt", &format_args!("{}", self.txfifo_cnt().bits()))
-            .field("dtrn", &format_args!("{}", self.dtrn().bit()))
-            .field("rtsn", &format_args!("{}", self.rtsn().bit()))
-            .field("txd", &format_args!("{}", self.txd().bit()))
+            .field("rxfifo_cnt", &self.rxfifo_cnt())
+            .field("dsrn", &self.dsrn())
+            .field("ctsn", &self.ctsn())
+            .field("rxd", &self.rxd())
+            .field("txfifo_cnt", &self.txfifo_cnt())
+            .field("dtrn", &self.dtrn())
+            .field("rtsn", &self.rtsn())
+            .field("txd", &self.txd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATUS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UART status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
diff --git a/esp32s3/src/uart0/swfc_conf0.rs b/esp32s3/src/uart0/swfc_conf0.rs
index 4cd05694b4..43fc03d002 100644
--- a/esp32s3/src/uart0/swfc_conf0.rs
+++ b/esp32s3/src/uart0/swfc_conf0.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF0")
-            .field(
-                "xoff_threshold",
-                &format_args!("{}", self.xoff_threshold().bits()),
-            )
-            .field("xoff_char", &format_args!("{}", self.xoff_char().bits()))
+            .field("xoff_threshold", &self.xoff_threshold())
+            .field("xoff_char", &self.xoff_char())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/swfc_conf1.rs b/esp32s3/src/uart0/swfc_conf1.rs
index 38ef751b21..77efb39707 100644
--- a/esp32s3/src/uart0/swfc_conf1.rs
+++ b/esp32s3/src/uart0/swfc_conf1.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("SWFC_CONF1")
-            .field(
-                "xon_threshold",
-                &format_args!("{}", self.xon_threshold().bits()),
-            )
-            .field("xon_char", &format_args!("{}", self.xon_char().bits()))
+            .field("xon_threshold", &self.xon_threshold())
+            .field("xon_char", &self.xon_char())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<SWFC_CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:9 - When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char."]
     #[inline(always)]
diff --git a/esp32s3/src/uart0/txbrk_conf.rs b/esp32s3/src/uart0/txbrk_conf.rs
index bfa2a9b911..65d37271c2 100644
--- a/esp32s3/src/uart0/txbrk_conf.rs
+++ b/esp32s3/src/uart0/txbrk_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TXBRK_CONF")
-            .field("tx_brk_num", &format_args!("{}", self.tx_brk_num().bits()))
+            .field("tx_brk_num", &self.tx_brk_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TXBRK_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1."]
     #[inline(always)]
diff --git a/esp32s3/src/uhci0/ack_num.rs b/esp32s3/src/uhci0/ack_num.rs
index 2565953ea8..045af0e719 100644
--- a/esp32s3/src/uhci0/ack_num.rs
+++ b/esp32s3/src/uhci0/ack_num.rs
@@ -19,16 +19,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ACK_NUM")
-            .field("ack_num", &format_args!("{}", self.ack_num().bits()))
+            .field("ack_num", &self.ack_num())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ACK_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - This ACK number used in software flow control."]
     #[inline(always)]
diff --git a/esp32s3/src/uhci0/conf0.rs b/esp32s3/src/uhci0/conf0.rs
index a34129845f..56fcd4b037 100644
--- a/esp32s3/src/uhci0/conf0.rs
+++ b/esp32s3/src/uhci0/conf0.rs
@@ -125,37 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("tx_rst", &format_args!("{}", self.tx_rst().bit()))
-            .field("rx_rst", &format_args!("{}", self.rx_rst().bit()))
-            .field("uart0_ce", &format_args!("{}", self.uart0_ce().bit()))
-            .field("uart1_ce", &format_args!("{}", self.uart1_ce().bit()))
-            .field("uart2_ce", &format_args!("{}", self.uart2_ce().bit()))
-            .field("seper_en", &format_args!("{}", self.seper_en().bit()))
-            .field("head_en", &format_args!("{}", self.head_en().bit()))
-            .field("crc_rec_en", &format_args!("{}", self.crc_rec_en().bit()))
-            .field(
-                "uart_idle_eof_en",
-                &format_args!("{}", self.uart_idle_eof_en().bit()),
-            )
-            .field("len_eof_en", &format_args!("{}", self.len_eof_en().bit()))
-            .field(
-                "encode_crc_en",
-                &format_args!("{}", self.encode_crc_en().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
-            .field(
-                "uart_rx_brk_eof_en",
-                &format_args!("{}", self.uart_rx_brk_eof_en().bit()),
-            )
+            .field("tx_rst", &self.tx_rst())
+            .field("rx_rst", &self.rx_rst())
+            .field("uart0_ce", &self.uart0_ce())
+            .field("uart1_ce", &self.uart1_ce())
+            .field("uart2_ce", &self.uart2_ce())
+            .field("seper_en", &self.seper_en())
+            .field("head_en", &self.head_en())
+            .field("crc_rec_en", &self.crc_rec_en())
+            .field("uart_idle_eof_en", &self.uart_idle_eof_en())
+            .field("len_eof_en", &self.len_eof_en())
+            .field("encode_crc_en", &self.encode_crc_en())
+            .field("clk_en", &self.clk_en())
+            .field("uart_rx_brk_eof_en", &self.uart_rx_brk_eof_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Write 1, then write 0 to this bit to reset decode state machine."]
     #[inline(always)]
diff --git a/esp32s3/src/uhci0/conf1.rs b/esp32s3/src/uhci0/conf1.rs
index 3441724b4e..1ae344aa21 100644
--- a/esp32s3/src/uhci0/conf1.rs
+++ b/esp32s3/src/uhci0/conf1.rs
@@ -80,38 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF1")
-            .field(
-                "check_sum_en",
-                &format_args!("{}", self.check_sum_en().bit()),
-            )
-            .field(
-                "check_seq_en",
-                &format_args!("{}", self.check_seq_en().bit()),
-            )
-            .field("crc_disable", &format_args!("{}", self.crc_disable().bit()))
-            .field("save_head", &format_args!("{}", self.save_head().bit()))
-            .field(
-                "tx_check_sum_re",
-                &format_args!("{}", self.tx_check_sum_re().bit()),
-            )
-            .field(
-                "tx_ack_num_re",
-                &format_args!("{}", self.tx_ack_num_re().bit()),
-            )
-            .field(
-                "wait_sw_start",
-                &format_args!("{}", self.wait_sw_start().bit()),
-            )
-            .field("sw_start", &format_args!("{}", self.sw_start().bit()))
+            .field("check_sum_en", &self.check_sum_en())
+            .field("check_seq_en", &self.check_seq_en())
+            .field("crc_disable", &self.crc_disable())
+            .field("save_head", &self.save_head())
+            .field("tx_check_sum_re", &self.tx_check_sum_re())
+            .field("tx_ack_num_re", &self.tx_ack_num_re())
+            .field("wait_sw_start", &self.wait_sw_start())
+            .field("sw_start", &self.sw_start())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the enable bit to check header checksum when UHCI receives a data packet."]
     #[inline(always)]
diff --git a/esp32s3/src/uhci0/date.rs b/esp32s3/src/uhci0/date.rs
index 22c5beff5a..e6a8e023fe 100644
--- a/esp32s3/src/uhci0/date.rs
+++ b/esp32s3/src/uhci0/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/uhci0/esc_conf.rs b/esp32s3/src/uhci0/esc_conf.rs
index 337dcc7506..00789e9966 100644
--- a/esp32s3/src/uhci0/esc_conf.rs
+++ b/esp32s3/src/uhci0/esc_conf.rs
@@ -35,24 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ESC_CONF")
-            .field("seper_char", &format_args!("{}", self.seper_char().bits()))
-            .field(
-                "seper_esc_char0",
-                &format_args!("{}", self.seper_esc_char0().bits()),
-            )
-            .field(
-                "seper_esc_char1",
-                &format_args!("{}", self.seper_esc_char1().bits()),
-            )
+            .field("seper_char", &self.seper_char())
+            .field("seper_esc_char0", &self.seper_esc_char0())
+            .field("seper_esc_char1", &self.seper_esc_char1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ESC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register is used to define the separate char that need to be encoded, default is 0xc0."]
     #[inline(always)]
diff --git a/esp32s3/src/uhci0/escape_conf.rs b/esp32s3/src/uhci0/escape_conf.rs
index 9aaa86c2af..999f2c5de5 100644
--- a/esp32s3/src/uhci0/escape_conf.rs
+++ b/esp32s3/src/uhci0/escape_conf.rs
@@ -80,47 +80,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("ESCAPE_CONF")
-            .field(
-                "tx_c0_esc_en",
-                &format_args!("{}", self.tx_c0_esc_en().bit()),
-            )
-            .field(
-                "tx_db_esc_en",
-                &format_args!("{}", self.tx_db_esc_en().bit()),
-            )
-            .field(
-                "tx_11_esc_en",
-                &format_args!("{}", self.tx_11_esc_en().bit()),
-            )
-            .field(
-                "tx_13_esc_en",
-                &format_args!("{}", self.tx_13_esc_en().bit()),
-            )
-            .field(
-                "rx_c0_esc_en",
-                &format_args!("{}", self.rx_c0_esc_en().bit()),
-            )
-            .field(
-                "rx_db_esc_en",
-                &format_args!("{}", self.rx_db_esc_en().bit()),
-            )
-            .field(
-                "rx_11_esc_en",
-                &format_args!("{}", self.rx_11_esc_en().bit()),
-            )
-            .field(
-                "rx_13_esc_en",
-                &format_args!("{}", self.rx_13_esc_en().bit()),
-            )
+            .field("tx_c0_esc_en", &self.tx_c0_esc_en())
+            .field("tx_db_esc_en", &self.tx_db_esc_en())
+            .field("tx_11_esc_en", &self.tx_11_esc_en())
+            .field("tx_13_esc_en", &self.tx_13_esc_en())
+            .field("rx_c0_esc_en", &self.rx_c0_esc_en())
+            .field("rx_db_esc_en", &self.rx_db_esc_en())
+            .field("rx_11_esc_en", &self.rx_11_esc_en())
+            .field("rx_13_esc_en", &self.rx_13_esc_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<ESCAPE_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to enable decoding char 0xc0 when DMA receives data."]
     #[inline(always)]
diff --git a/esp32s3/src/uhci0/hung_conf.rs b/esp32s3/src/uhci0/hung_conf.rs
index 1dee95a2d2..b502a00b7f 100644
--- a/esp32s3/src/uhci0/hung_conf.rs
+++ b/esp32s3/src/uhci0/hung_conf.rs
@@ -62,39 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HUNG_CONF")
-            .field(
-                "txfifo_timeout",
-                &format_args!("{}", self.txfifo_timeout().bits()),
-            )
-            .field(
-                "txfifo_timeout_shift",
-                &format_args!("{}", self.txfifo_timeout_shift().bits()),
-            )
-            .field(
-                "txfifo_timeout_ena",
-                &format_args!("{}", self.txfifo_timeout_ena().bit()),
-            )
-            .field(
-                "rxfifo_timeout",
-                &format_args!("{}", self.rxfifo_timeout().bits()),
-            )
-            .field(
-                "rxfifo_timeout_shift",
-                &format_args!("{}", self.rxfifo_timeout_shift().bits()),
-            )
-            .field(
-                "rxfifo_timeout_ena",
-                &format_args!("{}", self.rxfifo_timeout_ena().bit()),
-            )
+            .field("txfifo_timeout", &self.txfifo_timeout())
+            .field("txfifo_timeout_shift", &self.txfifo_timeout_shift())
+            .field("txfifo_timeout_ena", &self.txfifo_timeout_ena())
+            .field("rxfifo_timeout", &self.rxfifo_timeout())
+            .field("rxfifo_timeout_shift", &self.rxfifo_timeout_shift())
+            .field("rxfifo_timeout_ena", &self.rxfifo_timeout_ena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HUNG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - This register stores the timeout value. It will produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data."]
     #[inline(always)]
diff --git a/esp32s3/src/uhci0/int_ena.rs b/esp32s3/src/uhci0/int_ena.rs
index a13b62f0b9..08b35d6bff 100644
--- a/esp32s3/src/uhci0/int_ena.rs
+++ b/esp32s3/src/uhci0/int_ena.rs
@@ -89,33 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
-            .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the interrupt enable bit for UHCI_RX_START_INT interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/uhci0/int_raw.rs b/esp32s3/src/uhci0/int_raw.rs
index 63abf6c29e..77c9192d9e 100644
--- a/esp32s3/src/uhci0/int_raw.rs
+++ b/esp32s3/src/uhci0/int_raw.rs
@@ -89,30 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field("out_eof", &format_args!("{}", self.out_eof().bit()))
-            .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
-            .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("out_eof", &self.out_eof())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This is the interrupt raw bit. Triggered when a separator char has been sent."]
     #[inline(always)]
diff --git a/esp32s3/src/uhci0/int_st.rs b/esp32s3/src/uhci0/int_st.rs
index 613cedae3e..aba02436e3 100644
--- a/esp32s3/src/uhci0/int_st.rs
+++ b/esp32s3/src/uhci0/int_st.rs
@@ -69,33 +69,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field("rx_start", &format_args!("{}", self.rx_start().bit()))
-            .field("tx_start", &format_args!("{}", self.tx_start().bit()))
-            .field("rx_hung", &format_args!("{}", self.rx_hung().bit()))
-            .field("tx_hung", &format_args!("{}", self.tx_hung().bit()))
-            .field(
-                "send_s_reg_q",
-                &format_args!("{}", self.send_s_reg_q().bit()),
-            )
-            .field(
-                "send_a_reg_q",
-                &format_args!("{}", self.send_a_reg_q().bit()),
-            )
-            .field(
-                "outlink_eof_err",
-                &format_args!("{}", self.outlink_eof_err().bit()),
-            )
-            .field("app_ctrl0", &format_args!("{}", self.app_ctrl0().bit()))
-            .field("app_ctrl1", &format_args!("{}", self.app_ctrl1().bit()))
+            .field("rx_start", &self.rx_start())
+            .field("tx_start", &self.tx_start())
+            .field("rx_hung", &self.rx_hung())
+            .field("tx_hung", &self.tx_hung())
+            .field("send_s_reg_q", &self.send_s_reg_q())
+            .field("send_a_reg_q", &self.send_a_reg_q())
+            .field("outlink_eof_err", &self.outlink_eof_err())
+            .field("app_ctrl0", &self.app_ctrl0())
+            .field("app_ctrl1", &self.app_ctrl1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/uhci0/pkt_thres.rs b/esp32s3/src/uhci0/pkt_thres.rs
index 0a08867ec8..cf9182db51 100644
--- a/esp32s3/src/uhci0/pkt_thres.rs
+++ b/esp32s3/src/uhci0/pkt_thres.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PKT_THRES")
-            .field("pkt_thrs", &format_args!("{}", self.pkt_thrs().bits()))
+            .field("pkt_thrs", &self.pkt_thrs())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PKT_THRES_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:12 - This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0."]
     #[inline(always)]
diff --git a/esp32s3/src/uhci0/quick_sent.rs b/esp32s3/src/uhci0/quick_sent.rs
index 48a7fa9672..845d20b27e 100644
--- a/esp32s3/src/uhci0/quick_sent.rs
+++ b/esp32s3/src/uhci0/quick_sent.rs
@@ -44,31 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("QUICK_SENT")
-            .field(
-                "single_send_num",
-                &format_args!("{}", self.single_send_num().bits()),
-            )
-            .field(
-                "single_send_en",
-                &format_args!("{}", self.single_send_en().bit()),
-            )
-            .field(
-                "always_send_num",
-                &format_args!("{}", self.always_send_num().bits()),
-            )
-            .field(
-                "always_send_en",
-                &format_args!("{}", self.always_send_en().bit()),
-            )
+            .field("single_send_num", &self.single_send_num())
+            .field("single_send_en", &self.single_send_en())
+            .field("always_send_num", &self.always_send_num())
+            .field("always_send_en", &self.always_send_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<QUICK_SENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2 - This register is used to specify the single_send register."]
     #[inline(always)]
diff --git a/esp32s3/src/uhci0/reg_q/word0.rs b/esp32s3/src/uhci0/reg_q/word0.rs
index 3c8f261d68..1823a93181 100644
--- a/esp32s3/src/uhci0/reg_q/word0.rs
+++ b/esp32s3/src/uhci0/reg_q/word0.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WORD0")
-            .field("send_word", &format_args!("{}", self.send_word().bits()))
+            .field("send_word", &self.send_word())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WORD0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
     #[inline(always)]
diff --git a/esp32s3/src/uhci0/reg_q/word1.rs b/esp32s3/src/uhci0/reg_q/word1.rs
index 9c333f7966..d9205b268f 100644
--- a/esp32s3/src/uhci0/reg_q/word1.rs
+++ b/esp32s3/src/uhci0/reg_q/word1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("WORD1")
-            .field("send_word", &format_args!("{}", self.send_word().bits()))
+            .field("send_word", &self.send_word())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<WORD1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM."]
     #[inline(always)]
diff --git a/esp32s3/src/uhci0/rx_head.rs b/esp32s3/src/uhci0/rx_head.rs
index 1c81ed7160..542138c109 100644
--- a/esp32s3/src/uhci0/rx_head.rs
+++ b/esp32s3/src/uhci0/rx_head.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("RX_HEAD")
-            .field("rx_head", &format_args!("{}", self.rx_head().bits()))
+            .field("rx_head", &self.rx_head())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RX_HEAD_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UHCI packet header register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_head::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RX_HEAD_SPEC;
 impl crate::RegisterSpec for RX_HEAD_SPEC {
diff --git a/esp32s3/src/uhci0/state0.rs b/esp32s3/src/uhci0/state0.rs
index 03e353cf7a..4a730c92fa 100644
--- a/esp32s3/src/uhci0/state0.rs
+++ b/esp32s3/src/uhci0/state0.rs
@@ -20,23 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE0")
-            .field(
-                "rx_err_cause",
-                &format_args!("{}", self.rx_err_cause().bits()),
-            )
-            .field(
-                "decode_state",
-                &format_args!("{}", self.decode_state().bits()),
-            )
+            .field("rx_err_cause", &self.rx_err_cause())
+            .field("decode_state", &self.decode_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UHCI receive status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE0_SPEC;
 impl crate::RegisterSpec for STATE0_SPEC {
diff --git a/esp32s3/src/uhci0/state1.rs b/esp32s3/src/uhci0/state1.rs
index c1eaafa731..79ed5b92f4 100644
--- a/esp32s3/src/uhci0/state1.rs
+++ b/esp32s3/src/uhci0/state1.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE1")
-            .field(
-                "encode_state",
-                &format_args!("{}", self.encode_state().bits()),
-            )
+            .field("encode_state", &self.encode_state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "UHCI transmit status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE1_SPEC;
 impl crate::RegisterSpec for STATE1_SPEC {
diff --git a/esp32s3/src/usb0/daint.rs b/esp32s3/src/usb0/daint.rs
index 62d3956527..6d187f18e4 100644
--- a/esp32s3/src/usb0/daint.rs
+++ b/esp32s3/src/usb0/daint.rs
@@ -110,29 +110,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DAINT")
-            .field("inepint0", &format_args!("{}", self.inepint0().bit()))
-            .field("inepint1", &format_args!("{}", self.inepint1().bit()))
-            .field("inepint2", &format_args!("{}", self.inepint2().bit()))
-            .field("inepint3", &format_args!("{}", self.inepint3().bit()))
-            .field("inepint4", &format_args!("{}", self.inepint4().bit()))
-            .field("inepint5", &format_args!("{}", self.inepint5().bit()))
-            .field("inepint6", &format_args!("{}", self.inepint6().bit()))
-            .field("outepint0", &format_args!("{}", self.outepint0().bit()))
-            .field("outepint1", &format_args!("{}", self.outepint1().bit()))
-            .field("outepint2", &format_args!("{}", self.outepint2().bit()))
-            .field("outepint3", &format_args!("{}", self.outepint3().bit()))
-            .field("outepint4", &format_args!("{}", self.outepint4().bit()))
-            .field("outepint5", &format_args!("{}", self.outepint5().bit()))
-            .field("outepint6", &format_args!("{}", self.outepint6().bit()))
+            .field("inepint0", &self.inepint0())
+            .field("inepint1", &self.inepint1())
+            .field("inepint2", &self.inepint2())
+            .field("inepint3", &self.inepint3())
+            .field("inepint4", &self.inepint4())
+            .field("inepint5", &self.inepint5())
+            .field("inepint6", &self.inepint6())
+            .field("outepint0", &self.outepint0())
+            .field("outepint1", &self.outepint1())
+            .field("outepint2", &self.outepint2())
+            .field("outepint3", &self.outepint3())
+            .field("outepint4", &self.outepint4())
+            .field("outepint5", &self.outepint5())
+            .field("outepint6", &self.outepint6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DAINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daint::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DAINT_SPEC;
 impl crate::RegisterSpec for DAINT_SPEC {
diff --git a/esp32s3/src/usb0/daintmsk.rs b/esp32s3/src/usb0/daintmsk.rs
index f530c27202..57cfb41e8e 100644
--- a/esp32s3/src/usb0/daintmsk.rs
+++ b/esp32s3/src/usb0/daintmsk.rs
@@ -116,29 +116,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DAINTMSK")
-            .field("inepmsk0", &format_args!("{}", self.inepmsk0().bit()))
-            .field("inepmsk1", &format_args!("{}", self.inepmsk1().bit()))
-            .field("inepmsk2", &format_args!("{}", self.inepmsk2().bit()))
-            .field("inepmsk3", &format_args!("{}", self.inepmsk3().bit()))
-            .field("inepmsk4", &format_args!("{}", self.inepmsk4().bit()))
-            .field("inepmsk5", &format_args!("{}", self.inepmsk5().bit()))
-            .field("inepmsk6", &format_args!("{}", self.inepmsk6().bit()))
-            .field("outepmsk0", &format_args!("{}", self.outepmsk0().bit()))
-            .field("outepmsk1", &format_args!("{}", self.outepmsk1().bit()))
-            .field("outepmsk2", &format_args!("{}", self.outepmsk2().bit()))
-            .field("outepmsk3", &format_args!("{}", self.outepmsk3().bit()))
-            .field("outepmsk4", &format_args!("{}", self.outepmsk4().bit()))
-            .field("outepmsk5", &format_args!("{}", self.outepmsk5().bit()))
-            .field("outepmsk6", &format_args!("{}", self.outepmsk6().bit()))
+            .field("inepmsk0", &self.inepmsk0())
+            .field("inepmsk1", &self.inepmsk1())
+            .field("inepmsk2", &self.inepmsk2())
+            .field("inepmsk3", &self.inepmsk3())
+            .field("inepmsk4", &self.inepmsk4())
+            .field("inepmsk5", &self.inepmsk5())
+            .field("inepmsk6", &self.inepmsk6())
+            .field("outepmsk0", &self.outepmsk0())
+            .field("outepmsk1", &self.outepmsk1())
+            .field("outepmsk2", &self.outepmsk2())
+            .field("outepmsk3", &self.outepmsk3())
+            .field("outepmsk4", &self.outepmsk4())
+            .field("outepmsk5", &self.outepmsk5())
+            .field("outepmsk6", &self.outepmsk6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DAINTMSK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = ""]
     #[doc = ""]
diff --git a/esp32s3/src/usb0/dcfg.rs b/esp32s3/src/usb0/dcfg.rs
index df1d9baf2c..4d7349ec3a 100644
--- a/esp32s3/src/usb0/dcfg.rs
+++ b/esp32s3/src/usb0/dcfg.rs
@@ -107,38 +107,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCFG")
-            .field(
-                "nzstsouthshk",
-                &format_args!("{}", self.nzstsouthshk().bit()),
-            )
-            .field(
-                "ena32khzsusp",
-                &format_args!("{}", self.ena32khzsusp().bit()),
-            )
-            .field("devaddr", &format_args!("{}", self.devaddr().bits()))
-            .field("perfrlint", &format_args!("{}", self.perfrlint().bits()))
-            .field("endevoutnak", &format_args!("{}", self.endevoutnak().bit()))
-            .field("xcvrdly", &format_args!("{}", self.xcvrdly().bit()))
-            .field(
-                "erraticintmsk",
-                &format_args!("{}", self.erraticintmsk().bit()),
-            )
-            .field("epmiscnt", &format_args!("{}", self.epmiscnt().bits()))
-            .field("descdma", &format_args!("{}", self.descdma().bit()))
-            .field(
-                "perschintvl",
-                &format_args!("{}", self.perschintvl().bits()),
-            )
-            .field("resvalid", &format_args!("{}", self.resvalid().bits()))
+            .field("nzstsouthshk", &self.nzstsouthshk())
+            .field("ena32khzsusp", &self.ena32khzsusp())
+            .field("devaddr", &self.devaddr())
+            .field("perfrlint", &self.perfrlint())
+            .field("endevoutnak", &self.endevoutnak())
+            .field("xcvrdly", &self.xcvrdly())
+            .field("erraticintmsk", &self.erraticintmsk())
+            .field("epmiscnt", &self.epmiscnt())
+            .field("descdma", &self.descdma())
+            .field("perschintvl", &self.perschintvl())
+            .field("resvalid", &self.resvalid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/dctl.rs b/esp32s3/src/usb0/dctl.rs
index dd527c4fc7..0c0b2b51f8 100644
--- a/esp32s3/src/usb0/dctl.rs
+++ b/esp32s3/src/usb0/dctl.rs
@@ -111,35 +111,20 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DCTL")
-            .field("rmtwkupsig", &format_args!("{}", self.rmtwkupsig().bit()))
-            .field("sftdiscon", &format_args!("{}", self.sftdiscon().bit()))
-            .field("gnpinnaksts", &format_args!("{}", self.gnpinnaksts().bit()))
-            .field("goutnaksts", &format_args!("{}", self.goutnaksts().bit()))
-            .field("tstctl", &format_args!("{}", self.tstctl().bits()))
-            .field(
-                "pwronprgdone",
-                &format_args!("{}", self.pwronprgdone().bit()),
-            )
-            .field("gmc", &format_args!("{}", self.gmc().bits()))
-            .field("ignrfrmnum", &format_args!("{}", self.ignrfrmnum().bit()))
-            .field("nakonbble", &format_args!("{}", self.nakonbble().bit()))
-            .field(
-                "encountonbna",
-                &format_args!("{}", self.encountonbna().bit()),
-            )
-            .field(
-                "deepsleepbeslreject",
-                &format_args!("{}", self.deepsleepbeslreject().bit()),
-            )
+            .field("rmtwkupsig", &self.rmtwkupsig())
+            .field("sftdiscon", &self.sftdiscon())
+            .field("gnpinnaksts", &self.gnpinnaksts())
+            .field("goutnaksts", &self.goutnaksts())
+            .field("tstctl", &self.tstctl())
+            .field("pwronprgdone", &self.pwronprgdone())
+            .field("gmc", &self.gmc())
+            .field("ignrfrmnum", &self.ignrfrmnum())
+            .field("nakonbble", &self.nakonbble())
+            .field("encountonbna", &self.encountonbna())
+            .field("deepsleepbeslreject", &self.deepsleepbeslreject())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/diepempmsk.rs b/esp32s3/src/usb0/diepempmsk.rs
index 7511976134..d3c7e51a30 100644
--- a/esp32s3/src/usb0/diepempmsk.rs
+++ b/esp32s3/src/usb0/diepempmsk.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPEMPMSK")
-            .field(
-                "d_ineptxfempmsk",
-                &format_args!("{}", self.d_ineptxfempmsk().bits()),
-            )
+            .field("d_ineptxfempmsk", &self.d_ineptxfempmsk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPEMPMSK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/diepmsk.rs b/esp32s3/src/usb0/diepmsk.rs
index 07e50f8055..ca6f48aac3 100644
--- a/esp32s3/src/usb0/diepmsk.rs
+++ b/esp32s3/src/usb0/diepmsk.rs
@@ -98,46 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPMSK")
-            .field(
-                "di_xfercomplmsk",
-                &format_args!("{}", self.di_xfercomplmsk().bit()),
-            )
-            .field(
-                "di_epdisbldmsk",
-                &format_args!("{}", self.di_epdisbldmsk().bit()),
-            )
-            .field("di_ahbermsk", &format_args!("{}", self.di_ahbermsk().bit()))
-            .field("timeoutmsk", &format_args!("{}", self.timeoutmsk().bit()))
-            .field(
-                "intkntxfempmsk",
-                &format_args!("{}", self.intkntxfempmsk().bit()),
-            )
-            .field(
-                "intknepmismsk",
-                &format_args!("{}", self.intknepmismsk().bit()),
-            )
-            .field(
-                "inepnakeffmsk",
-                &format_args!("{}", self.inepnakeffmsk().bit()),
-            )
-            .field(
-                "txfifoundrnmsk",
-                &format_args!("{}", self.txfifoundrnmsk().bit()),
-            )
-            .field(
-                "bnainintrmsk",
-                &format_args!("{}", self.bnainintrmsk().bit()),
-            )
-            .field("di_nakmsk", &format_args!("{}", self.di_nakmsk().bit()))
+            .field("di_xfercomplmsk", &self.di_xfercomplmsk())
+            .field("di_epdisbldmsk", &self.di_epdisbldmsk())
+            .field("di_ahbermsk", &self.di_ahbermsk())
+            .field("timeoutmsk", &self.timeoutmsk())
+            .field("intkntxfempmsk", &self.intkntxfempmsk())
+            .field("intknepmismsk", &self.intknepmismsk())
+            .field("inepnakeffmsk", &self.inepnakeffmsk())
+            .field("txfifoundrnmsk", &self.txfifoundrnmsk())
+            .field("bnainintrmsk", &self.bnainintrmsk())
+            .field("di_nakmsk", &self.di_nakmsk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPMSK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/dieptxf.rs b/esp32s3/src/usb0/dieptxf.rs
index 2c143bd966..25d668c83a 100644
--- a/esp32s3/src/usb0/dieptxf.rs
+++ b/esp32s3/src/usb0/dieptxf.rs
@@ -26,23 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPTXF")
-            .field(
-                "inep1txfstaddr",
-                &format_args!("{}", self.inep1txfstaddr().bits()),
-            )
-            .field(
-                "inep1txfdep",
-                &format_args!("{}", self.inep1txfdep().bits()),
-            )
+            .field("inep1txfstaddr", &self.inep1txfstaddr())
+            .field("inep1txfdep", &self.inep1txfdep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPTXF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/doepmsk.rs b/esp32s3/src/usb0/doepmsk.rs
index 0a148f6608..b41015df11 100644
--- a/esp32s3/src/usb0/doepmsk.rs
+++ b/esp32s3/src/usb0/doepmsk.rs
@@ -116,45 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPMSK")
-            .field(
-                "xfercomplmsk",
-                &format_args!("{}", self.xfercomplmsk().bit()),
-            )
-            .field("epdisbldmsk", &format_args!("{}", self.epdisbldmsk().bit()))
-            .field("ahbermsk", &format_args!("{}", self.ahbermsk().bit()))
-            .field("setupmsk", &format_args!("{}", self.setupmsk().bit()))
-            .field(
-                "outtknepdismsk",
-                &format_args!("{}", self.outtknepdismsk().bit()),
-            )
-            .field(
-                "stsphsercvdmsk",
-                &format_args!("{}", self.stsphsercvdmsk().bit()),
-            )
-            .field(
-                "back2backsetup",
-                &format_args!("{}", self.back2backsetup().bit()),
-            )
-            .field(
-                "outpkterrmsk",
-                &format_args!("{}", self.outpkterrmsk().bit()),
-            )
-            .field(
-                "bnaoutintrmsk",
-                &format_args!("{}", self.bnaoutintrmsk().bit()),
-            )
-            .field("bbleerrmsk", &format_args!("{}", self.bbleerrmsk().bit()))
-            .field("nakmsk", &format_args!("{}", self.nakmsk().bit()))
-            .field("nyetmsk", &format_args!("{}", self.nyetmsk().bit()))
+            .field("xfercomplmsk", &self.xfercomplmsk())
+            .field("epdisbldmsk", &self.epdisbldmsk())
+            .field("ahbermsk", &self.ahbermsk())
+            .field("setupmsk", &self.setupmsk())
+            .field("outtknepdismsk", &self.outtknepdismsk())
+            .field("stsphsercvdmsk", &self.stsphsercvdmsk())
+            .field("back2backsetup", &self.back2backsetup())
+            .field("outpkterrmsk", &self.outpkterrmsk())
+            .field("bnaoutintrmsk", &self.bnaoutintrmsk())
+            .field("bbleerrmsk", &self.bbleerrmsk())
+            .field("nakmsk", &self.nakmsk())
+            .field("nyetmsk", &self.nyetmsk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPMSK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/dsts.rs b/esp32s3/src/usb0/dsts.rs
index 08cb678d74..6827ae6640 100644
--- a/esp32s3/src/usb0/dsts.rs
+++ b/esp32s3/src/usb0/dsts.rs
@@ -41,20 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DSTS")
-            .field("suspsts", &format_args!("{}", self.suspsts().bit()))
-            .field("enumspd", &format_args!("{}", self.enumspd().bits()))
-            .field("errticerr", &format_args!("{}", self.errticerr().bit()))
-            .field("soffn", &format_args!("{}", self.soffn().bits()))
-            .field("devlnsts", &format_args!("{}", self.devlnsts().bits()))
+            .field("suspsts", &self.suspsts())
+            .field("enumspd", &self.enumspd())
+            .field("errticerr", &self.errticerr())
+            .field("soffn", &self.soffn())
+            .field("devlnsts", &self.devlnsts())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsts::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DSTS_SPEC;
 impl crate::RegisterSpec for DSTS_SPEC {
diff --git a/esp32s3/src/usb0/dthrctl.rs b/esp32s3/src/usb0/dthrctl.rs
index ad2ea373b4..af8212cee7 100644
--- a/esp32s3/src/usb0/dthrctl.rs
+++ b/esp32s3/src/usb0/dthrctl.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DTHRCTL")
-            .field("nonisothren", &format_args!("{}", self.nonisothren().bit()))
-            .field("isothren", &format_args!("{}", self.isothren().bit()))
-            .field("txthrlen", &format_args!("{}", self.txthrlen().bits()))
-            .field(
-                "ahbthrratio",
-                &format_args!("{}", self.ahbthrratio().bits()),
-            )
-            .field("rxthren", &format_args!("{}", self.rxthren().bit()))
-            .field("rxthrlen", &format_args!("{}", self.rxthrlen().bits()))
-            .field("arbprken", &format_args!("{}", self.arbprken().bit()))
+            .field("nonisothren", &self.nonisothren())
+            .field("isothren", &self.isothren())
+            .field("txthrlen", &self.txthrlen())
+            .field("ahbthrratio", &self.ahbthrratio())
+            .field("rxthren", &self.rxthren())
+            .field("rxthrlen", &self.rxthrlen())
+            .field("arbprken", &self.arbprken())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DTHRCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/dvbusdis.rs b/esp32s3/src/usb0/dvbusdis.rs
index 59a12d26ad..dc11f505a8 100644
--- a/esp32s3/src/usb0/dvbusdis.rs
+++ b/esp32s3/src/usb0/dvbusdis.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DVBUSDIS")
-            .field("dvbusdis", &format_args!("{}", self.dvbusdis().bits()))
+            .field("dvbusdis", &self.dvbusdis())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DVBUSDIS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/dvbuspulse.rs b/esp32s3/src/usb0/dvbuspulse.rs
index 946c9aafd7..ab2eb101bf 100644
--- a/esp32s3/src/usb0/dvbuspulse.rs
+++ b/esp32s3/src/usb0/dvbuspulse.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DVBUSPULSE")
-            .field("dvbuspulse", &format_args!("{}", self.dvbuspulse().bits()))
+            .field("dvbuspulse", &self.dvbuspulse())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DVBUSPULSE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:11"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/fifo.rs b/esp32s3/src/usb0/fifo.rs
index 9fc2d6e4c7..3c8c2acd66 100644
--- a/esp32s3/src/usb0/fifo.rs
+++ b/esp32s3/src/usb0/fifo.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("FIFO")
-            .field("word", &format_args!("{}", self.word().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FIFO_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("FIFO").field("word", &self.word()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/usb0/gahbcfg.rs b/esp32s3/src/usb0/gahbcfg.rs
index 8bb6e7d2ed..a32afaaae7 100644
--- a/esp32s3/src/usb0/gahbcfg.rs
+++ b/esp32s3/src/usb0/gahbcfg.rs
@@ -89,30 +89,18 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GAHBCFG")
-            .field("glbllntrmsk", &format_args!("{}", self.glbllntrmsk().bit()))
-            .field("hbstlen", &format_args!("{}", self.hbstlen().bits()))
-            .field("dmaen", &format_args!("{}", self.dmaen().bit()))
-            .field("nptxfemplvl", &format_args!("{}", self.nptxfemplvl().bit()))
-            .field("ptxfemplvl", &format_args!("{}", self.ptxfemplvl().bit()))
-            .field("remmemsupp", &format_args!("{}", self.remmemsupp().bit()))
-            .field(
-                "notialldmawrit",
-                &format_args!("{}", self.notialldmawrit().bit()),
-            )
-            .field("ahbsingle", &format_args!("{}", self.ahbsingle().bit()))
-            .field(
-                "invdescendianess",
-                &format_args!("{}", self.invdescendianess().bit()),
-            )
+            .field("glbllntrmsk", &self.glbllntrmsk())
+            .field("hbstlen", &self.hbstlen())
+            .field("dmaen", &self.dmaen())
+            .field("nptxfemplvl", &self.nptxfemplvl())
+            .field("ptxfemplvl", &self.ptxfemplvl())
+            .field("remmemsupp", &self.remmemsupp())
+            .field("notialldmawrit", &self.notialldmawrit())
+            .field("ahbsingle", &self.ahbsingle())
+            .field("invdescendianess", &self.invdescendianess())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GAHBCFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/gdfifocfg.rs b/esp32s3/src/usb0/gdfifocfg.rs
index d043bb7169..889b0d9e2e 100644
--- a/esp32s3/src/usb0/gdfifocfg.rs
+++ b/esp32s3/src/usb0/gdfifocfg.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GDFIFOCFG")
-            .field("gdfifocfg", &format_args!("{}", self.gdfifocfg().bits()))
-            .field(
-                "epinfobaseaddr",
-                &format_args!("{}", self.epinfobaseaddr().bits()),
-            )
+            .field("gdfifocfg", &self.gdfifocfg())
+            .field("epinfobaseaddr", &self.epinfobaseaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GDFIFOCFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/ghwcfg1.rs b/esp32s3/src/usb0/ghwcfg1.rs
index 2bac61c23d..e152bb4b40 100644
--- a/esp32s3/src/usb0/ghwcfg1.rs
+++ b/esp32s3/src/usb0/ghwcfg1.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GHWCFG1")
-            .field("epdir", &format_args!("{}", self.epdir().bits()))
+            .field("epdir", &self.epdir())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GHWCFG1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ghwcfg1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GHWCFG1_SPEC;
 impl crate::RegisterSpec for GHWCFG1_SPEC {
diff --git a/esp32s3/src/usb0/ghwcfg2.rs b/esp32s3/src/usb0/ghwcfg2.rs
index cdd8edf116..c6d0e0043f 100644
--- a/esp32s3/src/usb0/ghwcfg2.rs
+++ b/esp32s3/src/usb0/ghwcfg2.rs
@@ -104,41 +104,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GHWCFG2")
-            .field("otgmode", &format_args!("{}", self.otgmode().bits()))
-            .field("otgarch", &format_args!("{}", self.otgarch().bits()))
-            .field("singpnt", &format_args!("{}", self.singpnt().bit()))
-            .field("hsphytype", &format_args!("{}", self.hsphytype().bits()))
-            .field("fsphytype", &format_args!("{}", self.fsphytype().bits()))
-            .field("numdeveps", &format_args!("{}", self.numdeveps().bits()))
-            .field("numhstchnl", &format_args!("{}", self.numhstchnl().bits()))
-            .field(
-                "periosupport",
-                &format_args!("{}", self.periosupport().bit()),
-            )
-            .field(
-                "dynfifosizing",
-                &format_args!("{}", self.dynfifosizing().bit()),
-            )
-            .field(
-                "multiprocintrpt",
-                &format_args!("{}", self.multiprocintrpt().bit()),
-            )
-            .field("nptxqdepth", &format_args!("{}", self.nptxqdepth().bits()))
-            .field("ptxqdepth", &format_args!("{}", self.ptxqdepth().bits()))
-            .field("tknqdepth", &format_args!("{}", self.tknqdepth().bits()))
-            .field(
-                "otg_enable_ic_usb",
-                &format_args!("{}", self.otg_enable_ic_usb().bit()),
-            )
+            .field("otgmode", &self.otgmode())
+            .field("otgarch", &self.otgarch())
+            .field("singpnt", &self.singpnt())
+            .field("hsphytype", &self.hsphytype())
+            .field("fsphytype", &self.fsphytype())
+            .field("numdeveps", &self.numdeveps())
+            .field("numhstchnl", &self.numhstchnl())
+            .field("periosupport", &self.periosupport())
+            .field("dynfifosizing", &self.dynfifosizing())
+            .field("multiprocintrpt", &self.multiprocintrpt())
+            .field("nptxqdepth", &self.nptxqdepth())
+            .field("ptxqdepth", &self.ptxqdepth())
+            .field("tknqdepth", &self.tknqdepth())
+            .field("otg_enable_ic_usb", &self.otg_enable_ic_usb())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GHWCFG2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ghwcfg2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GHWCFG2_SPEC;
 impl crate::RegisterSpec for GHWCFG2_SPEC {
diff --git a/esp32s3/src/usb0/ghwcfg3.rs b/esp32s3/src/usb0/ghwcfg3.rs
index 01c36421d2..308a4745de 100644
--- a/esp32s3/src/usb0/ghwcfg3.rs
+++ b/esp32s3/src/usb0/ghwcfg3.rs
@@ -90,33 +90,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GHWCFG3")
-            .field(
-                "xfersizewidth",
-                &format_args!("{}", self.xfersizewidth().bits()),
-            )
-            .field(
-                "pktsizewidth",
-                &format_args!("{}", self.pktsizewidth().bits()),
-            )
-            .field("otgen", &format_args!("{}", self.otgen().bit()))
-            .field("i2cintsel", &format_args!("{}", self.i2cintsel().bit()))
-            .field("vndctlsupt", &format_args!("{}", self.vndctlsupt().bit()))
-            .field("optfeature", &format_args!("{}", self.optfeature().bit()))
-            .field("rsttype", &format_args!("{}", self.rsttype().bit()))
-            .field("adpsupport", &format_args!("{}", self.adpsupport().bit()))
-            .field("hsicmode", &format_args!("{}", self.hsicmode().bit()))
-            .field("bcsupport", &format_args!("{}", self.bcsupport().bit()))
-            .field("lpmmode", &format_args!("{}", self.lpmmode().bit()))
-            .field("dfifodepth", &format_args!("{}", self.dfifodepth().bits()))
+            .field("xfersizewidth", &self.xfersizewidth())
+            .field("pktsizewidth", &self.pktsizewidth())
+            .field("otgen", &self.otgen())
+            .field("i2cintsel", &self.i2cintsel())
+            .field("vndctlsupt", &self.vndctlsupt())
+            .field("optfeature", &self.optfeature())
+            .field("rsttype", &self.rsttype())
+            .field("adpsupport", &self.adpsupport())
+            .field("hsicmode", &self.hsicmode())
+            .field("bcsupport", &self.bcsupport())
+            .field("lpmmode", &self.lpmmode())
+            .field("dfifodepth", &self.dfifodepth())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GHWCFG3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ghwcfg3::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GHWCFG3_SPEC;
 impl crate::RegisterSpec for GHWCFG3_SPEC {
diff --git a/esp32s3/src/usb0/ghwcfg4.rs b/esp32s3/src/usb0/ghwcfg4.rs
index 806bbfd516..d1bc32ff09 100644
--- a/esp32s3/src/usb0/ghwcfg4.rs
+++ b/esp32s3/src/usb0/ghwcfg4.rs
@@ -132,72 +132,27 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GHWCFG4")
-            .field(
-                "g_numdevperioeps",
-                &format_args!("{}", self.g_numdevperioeps().bits()),
-            )
-            .field(
-                "g_partialpwrdn",
-                &format_args!("{}", self.g_partialpwrdn().bit()),
-            )
-            .field("g_ahbfreq", &format_args!("{}", self.g_ahbfreq().bit()))
-            .field(
-                "g_hibernation",
-                &format_args!("{}", self.g_hibernation().bit()),
-            )
-            .field(
-                "g_extendedhibernation",
-                &format_args!("{}", self.g_extendedhibernation().bit()),
-            )
-            .field("g_acgsupt", &format_args!("{}", self.g_acgsupt().bit()))
-            .field(
-                "g_enhancedlpmsupt",
-                &format_args!("{}", self.g_enhancedlpmsupt().bit()),
-            )
-            .field(
-                "g_phydatawidth",
-                &format_args!("{}", self.g_phydatawidth().bits()),
-            )
-            .field(
-                "g_numctleps",
-                &format_args!("{}", self.g_numctleps().bits()),
-            )
-            .field("g_iddqfltr", &format_args!("{}", self.g_iddqfltr().bit()))
-            .field(
-                "g_vbusvalidfltr",
-                &format_args!("{}", self.g_vbusvalidfltr().bit()),
-            )
-            .field(
-                "g_avalidfltr",
-                &format_args!("{}", self.g_avalidfltr().bit()),
-            )
-            .field(
-                "g_bvalidfltr",
-                &format_args!("{}", self.g_bvalidfltr().bit()),
-            )
-            .field(
-                "g_sessendfltr",
-                &format_args!("{}", self.g_sessendfltr().bit()),
-            )
-            .field(
-                "g_dedfifomode",
-                &format_args!("{}", self.g_dedfifomode().bit()),
-            )
-            .field("g_ineps", &format_args!("{}", self.g_ineps().bits()))
-            .field(
-                "g_descdmaenabled",
-                &format_args!("{}", self.g_descdmaenabled().bit()),
-            )
-            .field("g_descdma", &format_args!("{}", self.g_descdma().bit()))
+            .field("g_numdevperioeps", &self.g_numdevperioeps())
+            .field("g_partialpwrdn", &self.g_partialpwrdn())
+            .field("g_ahbfreq", &self.g_ahbfreq())
+            .field("g_hibernation", &self.g_hibernation())
+            .field("g_extendedhibernation", &self.g_extendedhibernation())
+            .field("g_acgsupt", &self.g_acgsupt())
+            .field("g_enhancedlpmsupt", &self.g_enhancedlpmsupt())
+            .field("g_phydatawidth", &self.g_phydatawidth())
+            .field("g_numctleps", &self.g_numctleps())
+            .field("g_iddqfltr", &self.g_iddqfltr())
+            .field("g_vbusvalidfltr", &self.g_vbusvalidfltr())
+            .field("g_avalidfltr", &self.g_avalidfltr())
+            .field("g_bvalidfltr", &self.g_bvalidfltr())
+            .field("g_sessendfltr", &self.g_sessendfltr())
+            .field("g_dedfifomode", &self.g_dedfifomode())
+            .field("g_ineps", &self.g_ineps())
+            .field("g_descdmaenabled", &self.g_descdmaenabled())
+            .field("g_descdma", &self.g_descdma())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GHWCFG4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ghwcfg4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GHWCFG4_SPEC;
 impl crate::RegisterSpec for GHWCFG4_SPEC {
diff --git a/esp32s3/src/usb0/gintmsk.rs b/esp32s3/src/usb0/gintmsk.rs
index 1944be2246..d605948abf 100644
--- a/esp32s3/src/usb0/gintmsk.rs
+++ b/esp32s3/src/usb0/gintmsk.rs
@@ -251,63 +251,36 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GINTMSK")
-            .field("modemismsk", &format_args!("{}", self.modemismsk().bit()))
-            .field("otgintmsk", &format_args!("{}", self.otgintmsk().bit()))
-            .field("sofmsk", &format_args!("{}", self.sofmsk().bit()))
-            .field("rxflvimsk", &format_args!("{}", self.rxflvimsk().bit()))
-            .field("nptxfempmsk", &format_args!("{}", self.nptxfempmsk().bit()))
-            .field(
-                "ginnakeffmsk",
-                &format_args!("{}", self.ginnakeffmsk().bit()),
-            )
-            .field(
-                "goutnackeffmsk",
-                &format_args!("{}", self.goutnackeffmsk().bit()),
-            )
-            .field("erlysuspmsk", &format_args!("{}", self.erlysuspmsk().bit()))
-            .field("usbsuspmsk", &format_args!("{}", self.usbsuspmsk().bit()))
-            .field("usbrstmsk", &format_args!("{}", self.usbrstmsk().bit()))
-            .field("enumdonemsk", &format_args!("{}", self.enumdonemsk().bit()))
-            .field(
-                "isooutdropmsk",
-                &format_args!("{}", self.isooutdropmsk().bit()),
-            )
-            .field("eopfmsk", &format_args!("{}", self.eopfmsk().bit()))
-            .field("epmismsk", &format_args!("{}", self.epmismsk().bit()))
-            .field("iepintmsk", &format_args!("{}", self.iepintmsk().bit()))
-            .field("oepintmsk", &format_args!("{}", self.oepintmsk().bit()))
-            .field(
-                "incompisoinmsk",
-                &format_args!("{}", self.incompisoinmsk().bit()),
-            )
-            .field("incompipmsk", &format_args!("{}", self.incompipmsk().bit()))
-            .field("fetsuspmsk", &format_args!("{}", self.fetsuspmsk().bit()))
-            .field("resetdetmsk", &format_args!("{}", self.resetdetmsk().bit()))
-            .field("prtlntmsk", &format_args!("{}", self.prtlntmsk().bit()))
-            .field("hchintmsk", &format_args!("{}", self.hchintmsk().bit()))
-            .field("ptxfempmsk", &format_args!("{}", self.ptxfempmsk().bit()))
-            .field(
-                "conidstschngmsk",
-                &format_args!("{}", self.conidstschngmsk().bit()),
-            )
-            .field(
-                "disconnintmsk",
-                &format_args!("{}", self.disconnintmsk().bit()),
-            )
-            .field(
-                "sessreqintmsk",
-                &format_args!("{}", self.sessreqintmsk().bit()),
-            )
-            .field("wkupintmsk", &format_args!("{}", self.wkupintmsk().bit()))
+            .field("modemismsk", &self.modemismsk())
+            .field("otgintmsk", &self.otgintmsk())
+            .field("sofmsk", &self.sofmsk())
+            .field("rxflvimsk", &self.rxflvimsk())
+            .field("nptxfempmsk", &self.nptxfempmsk())
+            .field("ginnakeffmsk", &self.ginnakeffmsk())
+            .field("goutnackeffmsk", &self.goutnackeffmsk())
+            .field("erlysuspmsk", &self.erlysuspmsk())
+            .field("usbsuspmsk", &self.usbsuspmsk())
+            .field("usbrstmsk", &self.usbrstmsk())
+            .field("enumdonemsk", &self.enumdonemsk())
+            .field("isooutdropmsk", &self.isooutdropmsk())
+            .field("eopfmsk", &self.eopfmsk())
+            .field("epmismsk", &self.epmismsk())
+            .field("iepintmsk", &self.iepintmsk())
+            .field("oepintmsk", &self.oepintmsk())
+            .field("incompisoinmsk", &self.incompisoinmsk())
+            .field("incompipmsk", &self.incompipmsk())
+            .field("fetsuspmsk", &self.fetsuspmsk())
+            .field("resetdetmsk", &self.resetdetmsk())
+            .field("prtlntmsk", &self.prtlntmsk())
+            .field("hchintmsk", &self.hchintmsk())
+            .field("ptxfempmsk", &self.ptxfempmsk())
+            .field("conidstschngmsk", &self.conidstschngmsk())
+            .field("disconnintmsk", &self.disconnintmsk())
+            .field("sessreqintmsk", &self.sessreqintmsk())
+            .field("wkupintmsk", &self.wkupintmsk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GINTMSK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/gintsts.rs b/esp32s3/src/usb0/gintsts.rs
index 7407593bc9..a5c124bae3 100644
--- a/esp32s3/src/usb0/gintsts.rs
+++ b/esp32s3/src/usb0/gintsts.rs
@@ -238,46 +238,37 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GINTSTS")
-            .field("curmod_int", &format_args!("{}", self.curmod_int().bit()))
-            .field("modemis", &format_args!("{}", self.modemis().bit()))
-            .field("otgint", &format_args!("{}", self.otgint().bit()))
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field("rxflvi", &format_args!("{}", self.rxflvi().bit()))
-            .field("nptxfemp", &format_args!("{}", self.nptxfemp().bit()))
-            .field("ginnakeff", &format_args!("{}", self.ginnakeff().bit()))
-            .field("goutnakeff", &format_args!("{}", self.goutnakeff().bit()))
-            .field("erlysusp", &format_args!("{}", self.erlysusp().bit()))
-            .field("usbsusp", &format_args!("{}", self.usbsusp().bit()))
-            .field("usbrst", &format_args!("{}", self.usbrst().bit()))
-            .field("enumdone", &format_args!("{}", self.enumdone().bit()))
-            .field("isooutdrop", &format_args!("{}", self.isooutdrop().bit()))
-            .field("eopf", &format_args!("{}", self.eopf().bit()))
-            .field("epmis", &format_args!("{}", self.epmis().bit()))
-            .field("iepint", &format_args!("{}", self.iepint().bit()))
-            .field("oepint", &format_args!("{}", self.oepint().bit()))
-            .field("incompisoin", &format_args!("{}", self.incompisoin().bit()))
-            .field("incompip", &format_args!("{}", self.incompip().bit()))
-            .field("fetsusp", &format_args!("{}", self.fetsusp().bit()))
-            .field("resetdet", &format_args!("{}", self.resetdet().bit()))
-            .field("prtlnt", &format_args!("{}", self.prtlnt().bit()))
-            .field("hchlnt", &format_args!("{}", self.hchlnt().bit()))
-            .field("ptxfemp", &format_args!("{}", self.ptxfemp().bit()))
-            .field(
-                "conidstschng",
-                &format_args!("{}", self.conidstschng().bit()),
-            )
-            .field("disconnint", &format_args!("{}", self.disconnint().bit()))
-            .field("sessreqint", &format_args!("{}", self.sessreqint().bit()))
-            .field("wkupint", &format_args!("{}", self.wkupint().bit()))
+            .field("curmod_int", &self.curmod_int())
+            .field("modemis", &self.modemis())
+            .field("otgint", &self.otgint())
+            .field("sof", &self.sof())
+            .field("rxflvi", &self.rxflvi())
+            .field("nptxfemp", &self.nptxfemp())
+            .field("ginnakeff", &self.ginnakeff())
+            .field("goutnakeff", &self.goutnakeff())
+            .field("erlysusp", &self.erlysusp())
+            .field("usbsusp", &self.usbsusp())
+            .field("usbrst", &self.usbrst())
+            .field("enumdone", &self.enumdone())
+            .field("isooutdrop", &self.isooutdrop())
+            .field("eopf", &self.eopf())
+            .field("epmis", &self.epmis())
+            .field("iepint", &self.iepint())
+            .field("oepint", &self.oepint())
+            .field("incompisoin", &self.incompisoin())
+            .field("incompip", &self.incompip())
+            .field("fetsusp", &self.fetsusp())
+            .field("resetdet", &self.resetdet())
+            .field("prtlnt", &self.prtlnt())
+            .field("hchlnt", &self.hchlnt())
+            .field("ptxfemp", &self.ptxfemp())
+            .field("conidstschng", &self.conidstschng())
+            .field("disconnint", &self.disconnint())
+            .field("sessreqint", &self.sessreqint())
+            .field("wkupint", &self.wkupint())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GINTSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/gnptxfsiz.rs b/esp32s3/src/usb0/gnptxfsiz.rs
index b07f94ff21..992154236e 100644
--- a/esp32s3/src/usb0/gnptxfsiz.rs
+++ b/esp32s3/src/usb0/gnptxfsiz.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GNPTXFSIZ")
-            .field(
-                "nptxfstaddr",
-                &format_args!("{}", self.nptxfstaddr().bits()),
-            )
-            .field("nptxfdep", &format_args!("{}", self.nptxfdep().bits()))
+            .field("nptxfstaddr", &self.nptxfstaddr())
+            .field("nptxfdep", &self.nptxfdep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GNPTXFSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/gnptxsts.rs b/esp32s3/src/usb0/gnptxsts.rs
index 9caec58773..a270d09ce2 100644
--- a/esp32s3/src/usb0/gnptxsts.rs
+++ b/esp32s3/src/usb0/gnptxsts.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GNPTXSTS")
-            .field(
-                "nptxfspcavail",
-                &format_args!("{}", self.nptxfspcavail().bits()),
-            )
-            .field(
-                "nptxqspcavail",
-                &format_args!("{}", self.nptxqspcavail().bits()),
-            )
-            .field("nptxqtop", &format_args!("{}", self.nptxqtop().bits()))
+            .field("nptxfspcavail", &self.nptxfspcavail())
+            .field("nptxqspcavail", &self.nptxqspcavail())
+            .field("nptxqtop", &self.nptxqtop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GNPTXSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gnptxsts::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GNPTXSTS_SPEC;
 impl crate::RegisterSpec for GNPTXSTS_SPEC {
diff --git a/esp32s3/src/usb0/gotgctl.rs b/esp32s3/src/usb0/gotgctl.rs
index 7e773ded31..63c89dacfc 100644
--- a/esp32s3/src/usb0/gotgctl.rs
+++ b/esp32s3/src/usb0/gotgctl.rs
@@ -174,41 +174,29 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GOTGCTL")
-            .field("sesreqscs", &format_args!("{}", self.sesreqscs().bit()))
-            .field("sesreq", &format_args!("{}", self.sesreq().bit()))
-            .field("vbvalidoven", &format_args!("{}", self.vbvalidoven().bit()))
-            .field(
-                "vbvalidovval",
-                &format_args!("{}", self.vbvalidovval().bit()),
-            )
-            .field("avalidoven", &format_args!("{}", self.avalidoven().bit()))
-            .field("avalidovval", &format_args!("{}", self.avalidovval().bit()))
-            .field("bvalidoven", &format_args!("{}", self.bvalidoven().bit()))
-            .field("bvalidovval", &format_args!("{}", self.bvalidovval().bit()))
-            .field("hstnegscs", &format_args!("{}", self.hstnegscs().bit()))
-            .field("hnpreq", &format_args!("{}", self.hnpreq().bit()))
-            .field("hstsethnpen", &format_args!("{}", self.hstsethnpen().bit()))
-            .field("devhnpen", &format_args!("{}", self.devhnpen().bit()))
-            .field("ehen", &format_args!("{}", self.ehen().bit()))
-            .field(
-                "dbncefltrbypass",
-                &format_args!("{}", self.dbncefltrbypass().bit()),
-            )
-            .field("conidsts", &format_args!("{}", self.conidsts().bit()))
-            .field("dbnctime", &format_args!("{}", self.dbnctime().bit()))
-            .field("asesvld", &format_args!("{}", self.asesvld().bit()))
-            .field("bsesvld", &format_args!("{}", self.bsesvld().bit()))
-            .field("otgver", &format_args!("{}", self.otgver().bit()))
-            .field("curmod", &format_args!("{}", self.curmod().bit()))
+            .field("sesreqscs", &self.sesreqscs())
+            .field("sesreq", &self.sesreq())
+            .field("vbvalidoven", &self.vbvalidoven())
+            .field("vbvalidovval", &self.vbvalidovval())
+            .field("avalidoven", &self.avalidoven())
+            .field("avalidovval", &self.avalidovval())
+            .field("bvalidoven", &self.bvalidoven())
+            .field("bvalidovval", &self.bvalidovval())
+            .field("hstnegscs", &self.hstnegscs())
+            .field("hnpreq", &self.hnpreq())
+            .field("hstsethnpen", &self.hstsethnpen())
+            .field("devhnpen", &self.devhnpen())
+            .field("ehen", &self.ehen())
+            .field("dbncefltrbypass", &self.dbncefltrbypass())
+            .field("conidsts", &self.conidsts())
+            .field("dbnctime", &self.dbnctime())
+            .field("asesvld", &self.asesvld())
+            .field("bsesvld", &self.bsesvld())
+            .field("otgver", &self.otgver())
+            .field("curmod", &self.curmod())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GOTGCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/gotgint.rs b/esp32s3/src/usb0/gotgint.rs
index 20fe583b45..fa602368dd 100644
--- a/esp32s3/src/usb0/gotgint.rs
+++ b/esp32s3/src/usb0/gotgint.rs
@@ -62,27 +62,15 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GOTGINT")
-            .field("sesenddet", &format_args!("{}", self.sesenddet().bit()))
-            .field(
-                "sesreqsucstschng",
-                &format_args!("{}", self.sesreqsucstschng().bit()),
-            )
-            .field(
-                "hstnegsucstschng",
-                &format_args!("{}", self.hstnegsucstschng().bit()),
-            )
-            .field("hstnegdet", &format_args!("{}", self.hstnegdet().bit()))
-            .field("adevtoutchg", &format_args!("{}", self.adevtoutchg().bit()))
-            .field("dbncedone", &format_args!("{}", self.dbncedone().bit()))
+            .field("sesenddet", &self.sesenddet())
+            .field("sesreqsucstschng", &self.sesreqsucstschng())
+            .field("hstnegsucstschng", &self.hstnegsucstschng())
+            .field("hstnegdet", &self.hstnegdet())
+            .field("adevtoutchg", &self.adevtoutchg())
+            .field("dbncedone", &self.dbncedone())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GOTGINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/grstctl.rs b/esp32s3/src/usb0/grstctl.rs
index 7ededc6ce0..9ce5d1e957 100644
--- a/esp32s3/src/usb0/grstctl.rs
+++ b/esp32s3/src/usb0/grstctl.rs
@@ -76,23 +76,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GRSTCTL")
-            .field("csftrst", &format_args!("{}", self.csftrst().bit()))
-            .field("piufssftrst", &format_args!("{}", self.piufssftrst().bit()))
-            .field("frmcntrrst", &format_args!("{}", self.frmcntrrst().bit()))
-            .field("rxfflsh", &format_args!("{}", self.rxfflsh().bit()))
-            .field("txfflsh", &format_args!("{}", self.txfflsh().bit()))
-            .field("txfnum", &format_args!("{}", self.txfnum().bits()))
-            .field("dmareq", &format_args!("{}", self.dmareq().bit()))
-            .field("ahbidle", &format_args!("{}", self.ahbidle().bit()))
+            .field("csftrst", &self.csftrst())
+            .field("piufssftrst", &self.piufssftrst())
+            .field("frmcntrrst", &self.frmcntrrst())
+            .field("rxfflsh", &self.rxfflsh())
+            .field("txfflsh", &self.txfflsh())
+            .field("txfnum", &self.txfnum())
+            .field("dmareq", &self.dmareq())
+            .field("ahbidle", &self.ahbidle())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GRSTCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/grxfsiz.rs b/esp32s3/src/usb0/grxfsiz.rs
index c2e6d7364b..6aae3678c2 100644
--- a/esp32s3/src/usb0/grxfsiz.rs
+++ b/esp32s3/src/usb0/grxfsiz.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GRXFSIZ")
-            .field("rxfdep", &format_args!("{}", self.rxfdep().bits()))
+            .field("rxfdep", &self.rxfdep())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GRXFSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/grxstsp.rs b/esp32s3/src/usb0/grxstsp.rs
index 0fc8c2deab..de9e260051 100644
--- a/esp32s3/src/usb0/grxstsp.rs
+++ b/esp32s3/src/usb0/grxstsp.rs
@@ -41,20 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GRXSTSP")
-            .field("chnum", &format_args!("{}", self.chnum().bits()))
-            .field("bcnt", &format_args!("{}", self.bcnt().bits()))
-            .field("dpid", &format_args!("{}", self.dpid().bits()))
-            .field("pktsts", &format_args!("{}", self.pktsts().bits()))
-            .field("fn_", &format_args!("{}", self.fn_().bits()))
+            .field("chnum", &self.chnum())
+            .field("bcnt", &self.bcnt())
+            .field("dpid", &self.dpid())
+            .field("pktsts", &self.pktsts())
+            .field("fn_", &self.fn_())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GRXSTSP_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsp::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GRXSTSP_SPEC;
 impl crate::RegisterSpec for GRXSTSP_SPEC {
diff --git a/esp32s3/src/usb0/grxstsr.rs b/esp32s3/src/usb0/grxstsr.rs
index eea4e03f41..da95a68786 100644
--- a/esp32s3/src/usb0/grxstsr.rs
+++ b/esp32s3/src/usb0/grxstsr.rs
@@ -41,20 +41,14 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GRXSTSR")
-            .field("g_chnum", &format_args!("{}", self.g_chnum().bits()))
-            .field("g_bcnt", &format_args!("{}", self.g_bcnt().bits()))
-            .field("g_dpid", &format_args!("{}", self.g_dpid().bits()))
-            .field("g_pktsts", &format_args!("{}", self.g_pktsts().bits()))
-            .field("g_fn", &format_args!("{}", self.g_fn().bits()))
+            .field("g_chnum", &self.g_chnum())
+            .field("g_bcnt", &self.g_bcnt())
+            .field("g_dpid", &self.g_dpid())
+            .field("g_pktsts", &self.g_pktsts())
+            .field("g_fn", &self.g_fn())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GRXSTSR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grxstsr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GRXSTSR_SPEC;
 impl crate::RegisterSpec for GRXSTSR_SPEC {
diff --git a/esp32s3/src/usb0/gsnpsid.rs b/esp32s3/src/usb0/gsnpsid.rs
index 0b414d8063..3b222edf14 100644
--- a/esp32s3/src/usb0/gsnpsid.rs
+++ b/esp32s3/src/usb0/gsnpsid.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GSNPSID")
-            .field("synopsysid", &format_args!("{}", self.synopsysid().bits()))
+            .field("synopsysid", &self.synopsysid())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GSNPSID_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gsnpsid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GSNPSID_SPEC;
 impl crate::RegisterSpec for GSNPSID_SPEC {
diff --git a/esp32s3/src/usb0/gusbcfg.rs b/esp32s3/src/usb0/gusbcfg.rs
index 20ef792b20..f390ebf6f4 100644
--- a/esp32s3/src/usb0/gusbcfg.rs
+++ b/esp32s3/src/usb0/gusbcfg.rs
@@ -121,43 +121,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("GUSBCFG")
-            .field("toutcal", &format_args!("{}", self.toutcal().bits()))
-            .field("phyif", &format_args!("{}", self.phyif().bit()))
-            .field(
-                "ulpi_utmi_sel",
-                &format_args!("{}", self.ulpi_utmi_sel().bit()),
-            )
-            .field("fsintf", &format_args!("{}", self.fsintf().bit()))
-            .field("physel", &format_args!("{}", self.physel().bit()))
-            .field("srpcap", &format_args!("{}", self.srpcap().bit()))
-            .field("hnpcap", &format_args!("{}", self.hnpcap().bit()))
-            .field("usbtrdtim", &format_args!("{}", self.usbtrdtim().bits()))
-            .field(
-                "termseldlpulse",
-                &format_args!("{}", self.termseldlpulse().bit()),
-            )
-            .field("txenddelay", &format_args!("{}", self.txenddelay().bit()))
-            .field(
-                "forcehstmode",
-                &format_args!("{}", self.forcehstmode().bit()),
-            )
-            .field(
-                "forcedevmode",
-                &format_args!("{}", self.forcedevmode().bit()),
-            )
-            .field(
-                "corrupttxpkt",
-                &format_args!("{}", self.corrupttxpkt().bit()),
-            )
+            .field("toutcal", &self.toutcal())
+            .field("phyif", &self.phyif())
+            .field("ulpi_utmi_sel", &self.ulpi_utmi_sel())
+            .field("fsintf", &self.fsintf())
+            .field("physel", &self.physel())
+            .field("srpcap", &self.srpcap())
+            .field("hnpcap", &self.hnpcap())
+            .field("usbtrdtim", &self.usbtrdtim())
+            .field("termseldlpulse", &self.termseldlpulse())
+            .field("txenddelay", &self.txenddelay())
+            .field("forcehstmode", &self.forcehstmode())
+            .field("forcedevmode", &self.forcedevmode())
+            .field("corrupttxpkt", &self.corrupttxpkt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<GUSBCFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/haint.rs b/esp32s3/src/usb0/haint.rs
index a020f476a9..b522b1a11e 100644
--- a/esp32s3/src/usb0/haint.rs
+++ b/esp32s3/src/usb0/haint.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HAINT")
-            .field("haint", &format_args!("{}", self.haint().bits()))
+            .field("haint", &self.haint())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HAINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haint::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HAINT_SPEC;
 impl crate::RegisterSpec for HAINT_SPEC {
diff --git a/esp32s3/src/usb0/haintmsk.rs b/esp32s3/src/usb0/haintmsk.rs
index 0788d2b5c9..eef6f48fea 100644
--- a/esp32s3/src/usb0/haintmsk.rs
+++ b/esp32s3/src/usb0/haintmsk.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HAINTMSK")
-            .field("haintmsk", &format_args!("{}", self.haintmsk().bits()))
+            .field("haintmsk", &self.haintmsk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HAINTMSK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/hc/char.rs b/esp32s3/src/usb0/hc/char.rs
index 0b875a066f..9e8b0e322a 100644
--- a/esp32s3/src/usb0/hc/char.rs
+++ b/esp32s3/src/usb0/hc/char.rs
@@ -98,25 +98,19 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CHAR")
-            .field("mps", &format_args!("{}", self.mps().bits()))
-            .field("epnum", &format_args!("{}", self.epnum().bits()))
-            .field("epdir", &format_args!("{}", self.epdir().bit()))
-            .field("lspddev", &format_args!("{}", self.lspddev().bit()))
-            .field("eptype", &format_args!("{}", self.eptype().bits()))
-            .field("ec", &format_args!("{}", self.ec().bit()))
-            .field("devaddr", &format_args!("{}", self.devaddr().bits()))
-            .field("oddfrm", &format_args!("{}", self.oddfrm().bit()))
-            .field("chdis", &format_args!("{}", self.chdis().bit()))
-            .field("chena", &format_args!("{}", self.chena().bit()))
+            .field("mps", &self.mps())
+            .field("epnum", &self.epnum())
+            .field("epdir", &self.epdir())
+            .field("lspddev", &self.lspddev())
+            .field("eptype", &self.eptype())
+            .field("ec", &self.ec())
+            .field("devaddr", &self.devaddr())
+            .field("oddfrm", &self.oddfrm())
+            .field("chdis", &self.chdis())
+            .field("chena", &self.chena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CHAR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/hc/dma.rs b/esp32s3/src/usb0/hc/dma.rs
index e99a603759..a4ceab159d 100644
--- a/esp32s3/src/usb0/hc/dma.rs
+++ b/esp32s3/src/usb0/hc/dma.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMA")
-            .field("dmaaddr", &format_args!("{}", self.dmaaddr().bits()))
+            .field("dmaaddr", &self.dmaaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/hc/dmab.rs b/esp32s3/src/usb0/hc/dmab.rs
index 2acd241d7b..935df7e5ac 100644
--- a/esp32s3/src/usb0/hc/dmab.rs
+++ b/esp32s3/src/usb0/hc/dmab.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DMAB")
-            .field("hcdmab", &format_args!("{}", self.hcdmab().bits()))
+            .field("hcdmab", &self.hcdmab())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DMAB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmab::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DMAB_SPEC;
 impl crate::RegisterSpec for DMAB_SPEC {
diff --git a/esp32s3/src/usb0/hc/int.rs b/esp32s3/src/usb0/hc/int.rs
index 4cc59dec73..803fa348ba 100644
--- a/esp32s3/src/usb0/hc/int.rs
+++ b/esp32s3/src/usb0/hc/int.rs
@@ -134,35 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT")
-            .field("xfercompl", &format_args!("{}", self.xfercompl().bit()))
-            .field("chhltd", &format_args!("{}", self.chhltd().bit()))
-            .field("ahberr", &format_args!("{}", self.ahberr().bit()))
-            .field("stall", &format_args!("{}", self.stall().bit()))
-            .field("nack", &format_args!("{}", self.nack().bit()))
-            .field("ack", &format_args!("{}", self.ack().bit()))
-            .field("nyet", &format_args!("{}", self.nyet().bit()))
-            .field("xacterr", &format_args!("{}", self.xacterr().bit()))
-            .field("bblerr", &format_args!("{}", self.bblerr().bit()))
-            .field("frmovrun", &format_args!("{}", self.frmovrun().bit()))
-            .field("datatglerr", &format_args!("{}", self.datatglerr().bit()))
-            .field("bnaintr", &format_args!("{}", self.bnaintr().bit()))
-            .field(
-                "xcs_xact_err",
-                &format_args!("{}", self.xcs_xact_err().bit()),
-            )
-            .field(
-                "desc_lst_rollintr",
-                &format_args!("{}", self.desc_lst_rollintr().bit()),
-            )
+            .field("xfercompl", &self.xfercompl())
+            .field("chhltd", &self.chhltd())
+            .field("ahberr", &self.ahberr())
+            .field("stall", &self.stall())
+            .field("nack", &self.nack())
+            .field("ack", &self.ack())
+            .field("nyet", &self.nyet())
+            .field("xacterr", &self.xacterr())
+            .field("bblerr", &self.bblerr())
+            .field("frmovrun", &self.frmovrun())
+            .field("datatglerr", &self.datatglerr())
+            .field("bnaintr", &self.bnaintr())
+            .field("xcs_xact_err", &self.xcs_xact_err())
+            .field("desc_lst_rollintr", &self.desc_lst_rollintr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/hc/intmsk.rs b/esp32s3/src/usb0/hc/intmsk.rs
index 7d9fdcd81f..81f899ce74 100644
--- a/esp32s3/src/usb0/hc/intmsk.rs
+++ b/esp32s3/src/usb0/hc/intmsk.rs
@@ -125,37 +125,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INTMSK")
-            .field(
-                "xfercomplmsk",
-                &format_args!("{}", self.xfercomplmsk().bit()),
-            )
-            .field("chhltdmsk", &format_args!("{}", self.chhltdmsk().bit()))
-            .field("ahberrmsk", &format_args!("{}", self.ahberrmsk().bit()))
-            .field("stallmsk", &format_args!("{}", self.stallmsk().bit()))
-            .field("nakmsk", &format_args!("{}", self.nakmsk().bit()))
-            .field("ackmsk", &format_args!("{}", self.ackmsk().bit()))
-            .field("nyetmsk", &format_args!("{}", self.nyetmsk().bit()))
-            .field("xacterrmsk", &format_args!("{}", self.xacterrmsk().bit()))
-            .field("bblerrmsk", &format_args!("{}", self.bblerrmsk().bit()))
-            .field("frmovrunmsk", &format_args!("{}", self.frmovrunmsk().bit()))
-            .field(
-                "datatglerrmsk",
-                &format_args!("{}", self.datatglerrmsk().bit()),
-            )
-            .field("bnaintrmsk", &format_args!("{}", self.bnaintrmsk().bit()))
-            .field(
-                "desc_lst_rollintrmsk",
-                &format_args!("{}", self.desc_lst_rollintrmsk().bit()),
-            )
+            .field("xfercomplmsk", &self.xfercomplmsk())
+            .field("chhltdmsk", &self.chhltdmsk())
+            .field("ahberrmsk", &self.ahberrmsk())
+            .field("stallmsk", &self.stallmsk())
+            .field("nakmsk", &self.nakmsk())
+            .field("ackmsk", &self.ackmsk())
+            .field("nyetmsk", &self.nyetmsk())
+            .field("xacterrmsk", &self.xacterrmsk())
+            .field("bblerrmsk", &self.bblerrmsk())
+            .field("frmovrunmsk", &self.frmovrunmsk())
+            .field("datatglerrmsk", &self.datatglerrmsk())
+            .field("bnaintrmsk", &self.bnaintrmsk())
+            .field("desc_lst_rollintrmsk", &self.desc_lst_rollintrmsk())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INTMSK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/hc/tsiz.rs b/esp32s3/src/usb0/hc/tsiz.rs
index 6cd06014ce..09ce558852 100644
--- a/esp32s3/src/usb0/hc/tsiz.rs
+++ b/esp32s3/src/usb0/hc/tsiz.rs
@@ -44,19 +44,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TSIZ")
-            .field("xfersize", &format_args!("{}", self.xfersize().bits()))
-            .field("pktcnt", &format_args!("{}", self.pktcnt().bits()))
-            .field("pid", &format_args!("{}", self.pid().bits()))
-            .field("dopng", &format_args!("{}", self.dopng().bit()))
+            .field("xfersize", &self.xfersize())
+            .field("pktcnt", &self.pktcnt())
+            .field("pid", &self.pid())
+            .field("dopng", &self.dopng())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:18"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/hcfg.rs b/esp32s3/src/usb0/hcfg.rs
index 172bddb690..8cac12f662 100644
--- a/esp32s3/src/usb0/hcfg.rs
+++ b/esp32s3/src/usb0/hcfg.rs
@@ -71,25 +71,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HCFG")
-            .field(
-                "fslspclksel",
-                &format_args!("{}", self.fslspclksel().bits()),
-            )
-            .field("fslssupp", &format_args!("{}", self.fslssupp().bit()))
-            .field("ena32khzs", &format_args!("{}", self.ena32khzs().bit()))
-            .field("descdma", &format_args!("{}", self.descdma().bit()))
-            .field("frlisten", &format_args!("{}", self.frlisten().bits()))
-            .field("perschedena", &format_args!("{}", self.perschedena().bit()))
-            .field("modechtimen", &format_args!("{}", self.modechtimen().bit()))
+            .field("fslspclksel", &self.fslspclksel())
+            .field("fslssupp", &self.fslssupp())
+            .field("ena32khzs", &self.ena32khzs())
+            .field("descdma", &self.descdma())
+            .field("frlisten", &self.frlisten())
+            .field("perschedena", &self.perschedena())
+            .field("modechtimen", &self.modechtimen())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HCFG_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/hfir.rs b/esp32s3/src/usb0/hfir.rs
index aa0909fc52..11f6b0b86a 100644
--- a/esp32s3/src/usb0/hfir.rs
+++ b/esp32s3/src/usb0/hfir.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HFIR")
-            .field("frint", &format_args!("{}", self.frint().bits()))
-            .field("hfirrldctrl", &format_args!("{}", self.hfirrldctrl().bit()))
+            .field("frint", &self.frint())
+            .field("hfirrldctrl", &self.hfirrldctrl())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HFIR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/hflbaddr.rs b/esp32s3/src/usb0/hflbaddr.rs
index 86a437b4d6..d8a3a493d8 100644
--- a/esp32s3/src/usb0/hflbaddr.rs
+++ b/esp32s3/src/usb0/hflbaddr.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HFLBADDR")
-            .field("hflbaddr", &format_args!("{}", self.hflbaddr().bits()))
+            .field("hflbaddr", &self.hflbaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HFLBADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/hfnum.rs b/esp32s3/src/usb0/hfnum.rs
index 38d292d619..3d07b021e4 100644
--- a/esp32s3/src/usb0/hfnum.rs
+++ b/esp32s3/src/usb0/hfnum.rs
@@ -20,17 +20,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HFNUM")
-            .field("frnum", &format_args!("{}", self.frnum().bits()))
-            .field("frrem", &format_args!("{}", self.frrem().bits()))
+            .field("frnum", &self.frnum())
+            .field("frrem", &self.frrem())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HFNUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hfnum::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HFNUM_SPEC;
 impl crate::RegisterSpec for HFNUM_SPEC {
diff --git a/esp32s3/src/usb0/hprt.rs b/esp32s3/src/usb0/hprt.rs
index 95ced3cf52..331e8bd01f 100644
--- a/esp32s3/src/usb0/hprt.rs
+++ b/esp32s3/src/usb0/hprt.rs
@@ -117,34 +117,22 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPRT")
-            .field("prtconnsts", &format_args!("{}", self.prtconnsts().bit()))
-            .field("prtconndet", &format_args!("{}", self.prtconndet().bit()))
-            .field("prtena", &format_args!("{}", self.prtena().bit()))
-            .field("prtenchng", &format_args!("{}", self.prtenchng().bit()))
-            .field(
-                "prtovrcurract",
-                &format_args!("{}", self.prtovrcurract().bit()),
-            )
-            .field(
-                "prtovrcurrchng",
-                &format_args!("{}", self.prtovrcurrchng().bit()),
-            )
-            .field("prtres", &format_args!("{}", self.prtres().bit()))
-            .field("prtsusp", &format_args!("{}", self.prtsusp().bit()))
-            .field("prtrst", &format_args!("{}", self.prtrst().bit()))
-            .field("prtlnsts", &format_args!("{}", self.prtlnsts().bits()))
-            .field("prtpwr", &format_args!("{}", self.prtpwr().bit()))
-            .field("prttstctl", &format_args!("{}", self.prttstctl().bits()))
-            .field("prtspd", &format_args!("{}", self.prtspd().bits()))
+            .field("prtconnsts", &self.prtconnsts())
+            .field("prtconndet", &self.prtconndet())
+            .field("prtena", &self.prtena())
+            .field("prtenchng", &self.prtenchng())
+            .field("prtovrcurract", &self.prtovrcurract())
+            .field("prtovrcurrchng", &self.prtovrcurrchng())
+            .field("prtres", &self.prtres())
+            .field("prtsusp", &self.prtsusp())
+            .field("prtrst", &self.prtrst())
+            .field("prtlnsts", &self.prtlnsts())
+            .field("prtpwr", &self.prtpwr())
+            .field("prttstctl", &self.prttstctl())
+            .field("prtspd", &self.prtspd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPRT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/hptxfsiz.rs b/esp32s3/src/usb0/hptxfsiz.rs
index c145c6dab5..a183199a75 100644
--- a/esp32s3/src/usb0/hptxfsiz.rs
+++ b/esp32s3/src/usb0/hptxfsiz.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPTXFSIZ")
-            .field("ptxfstaddr", &format_args!("{}", self.ptxfstaddr().bits()))
-            .field("ptxfsize", &format_args!("{}", self.ptxfsize().bits()))
+            .field("ptxfstaddr", &self.ptxfstaddr())
+            .field("ptxfsize", &self.ptxfsize())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPTXFSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/hptxsts.rs b/esp32s3/src/usb0/hptxsts.rs
index 841c4618e2..5618635fc7 100644
--- a/esp32s3/src/usb0/hptxsts.rs
+++ b/esp32s3/src/usb0/hptxsts.rs
@@ -27,24 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("HPTXSTS")
-            .field(
-                "ptxfspcavail",
-                &format_args!("{}", self.ptxfspcavail().bits()),
-            )
-            .field(
-                "ptxqspcavail",
-                &format_args!("{}", self.ptxqspcavail().bits()),
-            )
-            .field("ptxqtop", &format_args!("{}", self.ptxqtop().bits()))
+            .field("ptxfspcavail", &self.ptxfspcavail())
+            .field("ptxqspcavail", &self.ptxqspcavail())
+            .field("ptxqtop", &self.ptxqtop())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<HPTXSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hptxsts::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct HPTXSTS_SPEC;
 impl crate::RegisterSpec for HPTXSTS_SPEC {
diff --git a/esp32s3/src/usb0/in_ep/diepctl.rs b/esp32s3/src/usb0/in_ep/diepctl.rs
index fcd3ad47cc..f269337cce 100644
--- a/esp32s3/src/usb0/in_ep/diepctl.rs
+++ b/esp32s3/src/usb0/in_ep/diepctl.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPCTL")
-            .field("mps", &format_args!("{}", self.mps().bits()))
-            .field("usbactep", &format_args!("{}", self.usbactep().bit()))
-            .field("naksts", &format_args!("{}", self.naksts().bit()))
-            .field("eptype", &format_args!("{}", self.eptype().bits()))
-            .field("stall", &format_args!("{}", self.stall().bit()))
-            .field("txfnum", &format_args!("{}", self.txfnum().bits()))
-            .field("epdis", &format_args!("{}", self.epdis().bit()))
-            .field("epena", &format_args!("{}", self.epena().bit()))
+            .field("mps", &self.mps())
+            .field("usbactep", &self.usbactep())
+            .field("naksts", &self.naksts())
+            .field("eptype", &self.eptype())
+            .field("stall", &self.stall())
+            .field("txfnum", &self.txfnum())
+            .field("epdis", &self.epdis())
+            .field("epena", &self.epena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/in_ep/dieptsiz.rs b/esp32s3/src/usb0/in_ep/dieptsiz.rs
index e3d2e4d69a..cea3e21ed5 100644
--- a/esp32s3/src/usb0/in_ep/dieptsiz.rs
+++ b/esp32s3/src/usb0/in_ep/dieptsiz.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPTSIZ")
-            .field("xfersize", &format_args!("{}", self.xfersize().bits()))
-            .field("pktcnt", &format_args!("{}", self.pktcnt().bits()))
+            .field("xfersize", &self.xfersize())
+            .field("pktcnt", &self.pktcnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPTSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:18"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/in_ep0/diepctl.rs b/esp32s3/src/usb0/in_ep0/diepctl.rs
index b1a20a1e4c..1aaa2873b2 100644
--- a/esp32s3/src/usb0/in_ep0/diepctl.rs
+++ b/esp32s3/src/usb0/in_ep0/diepctl.rs
@@ -78,23 +78,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPCTL")
-            .field("mps", &format_args!("{}", self.mps().bits()))
-            .field("usbactep", &format_args!("{}", self.usbactep().bit()))
-            .field("naksts", &format_args!("{}", self.naksts().bit()))
-            .field("eptype", &format_args!("{}", self.eptype().bits()))
-            .field("stall", &format_args!("{}", self.stall().bit()))
-            .field("txfnum", &format_args!("{}", self.txfnum().bits()))
-            .field("epdis", &format_args!("{}", self.epdis().bit()))
-            .field("epena", &format_args!("{}", self.epena().bit()))
+            .field("mps", &self.mps())
+            .field("usbactep", &self.usbactep())
+            .field("naksts", &self.naksts())
+            .field("eptype", &self.eptype())
+            .field("stall", &self.stall())
+            .field("txfnum", &self.txfnum())
+            .field("epdis", &self.epdis())
+            .field("epena", &self.epena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/in_ep0/diepdma.rs b/esp32s3/src/usb0/in_ep0/diepdma.rs
index 91dd04b770..f959ce25ec 100644
--- a/esp32s3/src/usb0/in_ep0/diepdma.rs
+++ b/esp32s3/src/usb0/in_ep0/diepdma.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPDMA")
-            .field("dmaaddr", &format_args!("{}", self.dmaaddr().bits()))
+            .field("dmaaddr", &self.dmaaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPDMA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/in_ep0/diepdmab.rs b/esp32s3/src/usb0/in_ep0/diepdmab.rs
index 3b14652aab..930ae0b82d 100644
--- a/esp32s3/src/usb0/in_ep0/diepdmab.rs
+++ b/esp32s3/src/usb0/in_ep0/diepdmab.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPDMAB")
-            .field(
-                "dmabufferaddr",
-                &format_args!("{}", self.dmabufferaddr().bits()),
-            )
+            .field("dmabufferaddr", &self.dmabufferaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPDMAB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diepdmab::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIEPDMAB_SPEC;
 impl crate::RegisterSpec for DIEPDMAB_SPEC {
diff --git a/esp32s3/src/usb0/in_ep0/diepint.rs b/esp32s3/src/usb0/in_ep0/diepint.rs
index 4571ae668a..af7a0f9c52 100644
--- a/esp32s3/src/usb0/in_ep0/diepint.rs
+++ b/esp32s3/src/usb0/in_ep0/diepint.rs
@@ -132,29 +132,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPINT")
-            .field("xfercompl", &format_args!("{}", self.xfercompl().bit()))
-            .field("epdisbld", &format_args!("{}", self.epdisbld().bit()))
-            .field("ahberr", &format_args!("{}", self.ahberr().bit()))
-            .field("timeout", &format_args!("{}", self.timeout().bit()))
-            .field("intkntxfemp", &format_args!("{}", self.intkntxfemp().bit()))
-            .field("intknepmis", &format_args!("{}", self.intknepmis().bit()))
-            .field("inepnakeff", &format_args!("{}", self.inepnakeff().bit()))
-            .field("txfemp", &format_args!("{}", self.txfemp().bit()))
-            .field("txfifoundrn", &format_args!("{}", self.txfifoundrn().bit()))
-            .field("bnaintr", &format_args!("{}", self.bnaintr().bit()))
-            .field("pktdrpsts", &format_args!("{}", self.pktdrpsts().bit()))
-            .field("bbleerr", &format_args!("{}", self.bbleerr().bit()))
-            .field("nakintrpt", &format_args!("{}", self.nakintrpt().bit()))
-            .field("nyetintrpt", &format_args!("{}", self.nyetintrpt().bit()))
+            .field("xfercompl", &self.xfercompl())
+            .field("epdisbld", &self.epdisbld())
+            .field("ahberr", &self.ahberr())
+            .field("timeout", &self.timeout())
+            .field("intkntxfemp", &self.intkntxfemp())
+            .field("intknepmis", &self.intknepmis())
+            .field("inepnakeff", &self.inepnakeff())
+            .field("txfemp", &self.txfemp())
+            .field("txfifoundrn", &self.txfifoundrn())
+            .field("bnaintr", &self.bnaintr())
+            .field("pktdrpsts", &self.pktdrpsts())
+            .field("bbleerr", &self.bbleerr())
+            .field("nakintrpt", &self.nakintrpt())
+            .field("nyetintrpt", &self.nyetintrpt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/in_ep0/dieptsiz.rs b/esp32s3/src/usb0/in_ep0/dieptsiz.rs
index 213c0ab105..7a93c34199 100644
--- a/esp32s3/src/usb0/in_ep0/dieptsiz.rs
+++ b/esp32s3/src/usb0/in_ep0/dieptsiz.rs
@@ -26,17 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DIEPTSIZ")
-            .field("xfersize", &format_args!("{}", self.xfersize().bits()))
-            .field("pktcnt", &format_args!("{}", self.pktcnt().bits()))
+            .field("xfersize", &self.xfersize())
+            .field("pktcnt", &self.pktcnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DIEPTSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/in_ep0/dtxfsts.rs b/esp32s3/src/usb0/in_ep0/dtxfsts.rs
index 6dde2d4f48..6eaf8877b6 100644
--- a/esp32s3/src/usb0/in_ep0/dtxfsts.rs
+++ b/esp32s3/src/usb0/in_ep0/dtxfsts.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DTXFSTS")
-            .field(
-                "ineptxfspcavail",
-                &format_args!("{}", self.ineptxfspcavail().bits()),
-            )
+            .field("ineptxfspcavail", &self.ineptxfspcavail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DTXFSTS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtxfsts::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DTXFSTS_SPEC;
 impl crate::RegisterSpec for DTXFSTS_SPEC {
diff --git a/esp32s3/src/usb0/out_ep/doepctl.rs b/esp32s3/src/usb0/out_ep/doepctl.rs
index 7357f53efb..fd8a085bf5 100644
--- a/esp32s3/src/usb0/out_ep/doepctl.rs
+++ b/esp32s3/src/usb0/out_ep/doepctl.rs
@@ -86,23 +86,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPCTL")
-            .field("mps", &format_args!("{}", self.mps().bits()))
-            .field("usbactep", &format_args!("{}", self.usbactep().bit()))
-            .field("naksts", &format_args!("{}", self.naksts().bit()))
-            .field("eptype", &format_args!("{}", self.eptype().bits()))
-            .field("snp", &format_args!("{}", self.snp().bit()))
-            .field("stall", &format_args!("{}", self.stall().bit()))
-            .field("epdis", &format_args!("{}", self.epdis().bit()))
-            .field("epena", &format_args!("{}", self.epena().bit()))
+            .field("mps", &self.mps())
+            .field("usbactep", &self.usbactep())
+            .field("naksts", &self.naksts())
+            .field("eptype", &self.eptype())
+            .field("snp", &self.snp())
+            .field("stall", &self.stall())
+            .field("epdis", &self.epdis())
+            .field("epena", &self.epena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/out_ep/doeptsiz.rs b/esp32s3/src/usb0/out_ep/doeptsiz.rs
index 21c28d4811..1c54bb57b4 100644
--- a/esp32s3/src/usb0/out_ep/doeptsiz.rs
+++ b/esp32s3/src/usb0/out_ep/doeptsiz.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPTSIZ")
-            .field("xfersize", &format_args!("{}", self.xfersize().bits()))
-            .field("pktcnt", &format_args!("{}", self.pktcnt().bits()))
-            .field("supcnt", &format_args!("{}", self.supcnt().bits()))
+            .field("xfersize", &self.xfersize())
+            .field("pktcnt", &self.pktcnt())
+            .field("supcnt", &self.supcnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPTSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:18"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/out_ep0/doepctl.rs b/esp32s3/src/usb0/out_ep0/doepctl.rs
index 812ad522bb..afa8be57b1 100644
--- a/esp32s3/src/usb0/out_ep0/doepctl.rs
+++ b/esp32s3/src/usb0/out_ep0/doepctl.rs
@@ -74,23 +74,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPCTL")
-            .field("mps", &format_args!("{}", self.mps().bits()))
-            .field("usbactep", &format_args!("{}", self.usbactep().bit()))
-            .field("naksts", &format_args!("{}", self.naksts().bit()))
-            .field("eptype", &format_args!("{}", self.eptype().bits()))
-            .field("snp", &format_args!("{}", self.snp().bit()))
-            .field("stall", &format_args!("{}", self.stall().bit()))
-            .field("epdis", &format_args!("{}", self.epdis().bit()))
-            .field("epena", &format_args!("{}", self.epena().bit()))
+            .field("mps", &self.mps())
+            .field("usbactep", &self.usbactep())
+            .field("naksts", &self.naksts())
+            .field("eptype", &self.eptype())
+            .field("snp", &self.snp())
+            .field("stall", &self.stall())
+            .field("epdis", &self.epdis())
+            .field("epena", &self.epena())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 20"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/out_ep0/doepdma.rs b/esp32s3/src/usb0/out_ep0/doepdma.rs
index c5f70ea68b..056a1c29bd 100644
--- a/esp32s3/src/usb0/out_ep0/doepdma.rs
+++ b/esp32s3/src/usb0/out_ep0/doepdma.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPDMA")
-            .field("dmaaddr", &format_args!("{}", self.dmaaddr().bits()))
+            .field("dmaaddr", &self.dmaaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPDMA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/out_ep0/doepdmab.rs b/esp32s3/src/usb0/out_ep0/doepdmab.rs
index 1ac9ce383c..e9f98d5f4a 100644
--- a/esp32s3/src/usb0/out_ep0/doepdmab.rs
+++ b/esp32s3/src/usb0/out_ep0/doepdmab.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPDMAB")
-            .field(
-                "dmabufferaddr",
-                &format_args!("{}", self.dmabufferaddr().bits()),
-            )
+            .field("dmabufferaddr", &self.dmabufferaddr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPDMAB_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/out_ep0/doepint.rs b/esp32s3/src/usb0/out_ep0/doepint.rs
index c390e5f270..39486dfcbf 100644
--- a/esp32s3/src/usb0/out_ep0/doepint.rs
+++ b/esp32s3/src/usb0/out_ep0/doepint.rs
@@ -134,32 +134,23 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPINT")
-            .field("xfercompl", &format_args!("{}", self.xfercompl().bit()))
-            .field("epdisbld", &format_args!("{}", self.epdisbld().bit()))
-            .field("ahberr", &format_args!("{}", self.ahberr().bit()))
-            .field("setup", &format_args!("{}", self.setup().bit()))
-            .field("outtknepdis", &format_args!("{}", self.outtknepdis().bit()))
-            .field("stsphsercvd", &format_args!("{}", self.stsphsercvd().bit()))
-            .field(
-                "back2backsetup",
-                &format_args!("{}", self.back2backsetup().bit()),
-            )
-            .field("outpkterr", &format_args!("{}", self.outpkterr().bit()))
-            .field("bnaintr", &format_args!("{}", self.bnaintr().bit()))
-            .field("pktdrpsts", &format_args!("{}", self.pktdrpsts().bit()))
-            .field("bbleerr", &format_args!("{}", self.bbleerr().bit()))
-            .field("nakintrpt", &format_args!("{}", self.nakintrpt().bit()))
-            .field("nyepintrpt", &format_args!("{}", self.nyepintrpt().bit()))
-            .field("stuppktrcvd", &format_args!("{}", self.stuppktrcvd().bit()))
+            .field("xfercompl", &self.xfercompl())
+            .field("epdisbld", &self.epdisbld())
+            .field("ahberr", &self.ahberr())
+            .field("setup", &self.setup())
+            .field("outtknepdis", &self.outtknepdis())
+            .field("stsphsercvd", &self.stsphsercvd())
+            .field("back2backsetup", &self.back2backsetup())
+            .field("outpkterr", &self.outpkterr())
+            .field("bnaintr", &self.bnaintr())
+            .field("pktdrpsts", &self.pktdrpsts())
+            .field("bbleerr", &self.bbleerr())
+            .field("nakintrpt", &self.nakintrpt())
+            .field("nyepintrpt", &self.nyepintrpt())
+            .field("stuppktrcvd", &self.stuppktrcvd())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPINT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/out_ep0/doeptsiz.rs b/esp32s3/src/usb0/out_ep0/doeptsiz.rs
index 91af3ee81a..166dea70ae 100644
--- a/esp32s3/src/usb0/out_ep0/doeptsiz.rs
+++ b/esp32s3/src/usb0/out_ep0/doeptsiz.rs
@@ -35,18 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DOEPTSIZ")
-            .field("xfersize", &format_args!("{}", self.xfersize().bits()))
-            .field("pktcnt", &format_args!("{}", self.pktcnt().bit()))
-            .field("supcnt", &format_args!("{}", self.supcnt().bits()))
+            .field("xfersize", &self.xfersize())
+            .field("pktcnt", &self.pktcnt())
+            .field("supcnt", &self.supcnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DOEPTSIZ_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:6"]
     #[inline(always)]
diff --git a/esp32s3/src/usb0/pcgcctl.rs b/esp32s3/src/usb0/pcgcctl.rs
index 276690e5fc..f1b358e978 100644
--- a/esp32s3/src/usb0/pcgcctl.rs
+++ b/esp32s3/src/usb0/pcgcctl.rs
@@ -67,28 +67,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PCGCCTL")
-            .field("stoppclk", &format_args!("{}", self.stoppclk().bit()))
-            .field("gatehclk", &format_args!("{}", self.gatehclk().bit()))
-            .field("pwrclmp", &format_args!("{}", self.pwrclmp().bit()))
-            .field(
-                "rstpdwnmodule",
-                &format_args!("{}", self.rstpdwnmodule().bit()),
-            )
-            .field("physleep", &format_args!("{}", self.physleep().bit()))
-            .field("l1suspended", &format_args!("{}", self.l1suspended().bit()))
-            .field(
-                "resetaftersusp",
-                &format_args!("{}", self.resetaftersusp().bit()),
-            )
+            .field("stoppclk", &self.stoppclk())
+            .field("gatehclk", &self.gatehclk())
+            .field("pwrclmp", &self.pwrclmp())
+            .field("rstpdwnmodule", &self.rstpdwnmodule())
+            .field("physleep", &self.physleep())
+            .field("l1suspended", &self.l1suspended())
+            .field("resetaftersusp", &self.resetaftersusp())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PCGCCTL_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
diff --git a/esp32s3/src/usb_device/conf0.rs b/esp32s3/src/usb_device/conf0.rs
index 5d8abe677d..1d4a5594d6 100644
--- a/esp32s3/src/usb_device/conf0.rs
+++ b/esp32s3/src/usb_device/conf0.rs
@@ -143,51 +143,24 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("CONF0")
-            .field("phy_sel", &format_args!("{}", self.phy_sel().bit()))
-            .field(
-                "exchg_pins_override",
-                &format_args!("{}", self.exchg_pins_override().bit()),
-            )
-            .field("exchg_pins", &format_args!("{}", self.exchg_pins().bit()))
-            .field("vrefh", &format_args!("{}", self.vrefh().bits()))
-            .field("vrefl", &format_args!("{}", self.vrefl().bits()))
-            .field(
-                "vref_override",
-                &format_args!("{}", self.vref_override().bit()),
-            )
-            .field(
-                "pad_pull_override",
-                &format_args!("{}", self.pad_pull_override().bit()),
-            )
-            .field("dp_pullup", &format_args!("{}", self.dp_pullup().bit()))
-            .field("dp_pulldown", &format_args!("{}", self.dp_pulldown().bit()))
-            .field("dm_pullup", &format_args!("{}", self.dm_pullup().bit()))
-            .field("dm_pulldown", &format_args!("{}", self.dm_pulldown().bit()))
-            .field(
-                "pullup_value",
-                &format_args!("{}", self.pullup_value().bit()),
-            )
-            .field(
-                "usb_pad_enable",
-                &format_args!("{}", self.usb_pad_enable().bit()),
-            )
-            .field(
-                "phy_tx_edge_sel",
-                &format_args!("{}", self.phy_tx_edge_sel().bit()),
-            )
-            .field(
-                "usb_jtag_bridge_en",
-                &format_args!("{}", self.usb_jtag_bridge_en().bit()),
-            )
+            .field("phy_sel", &self.phy_sel())
+            .field("exchg_pins_override", &self.exchg_pins_override())
+            .field("exchg_pins", &self.exchg_pins())
+            .field("vrefh", &self.vrefh())
+            .field("vrefl", &self.vrefl())
+            .field("vref_override", &self.vref_override())
+            .field("pad_pull_override", &self.pad_pull_override())
+            .field("dp_pullup", &self.dp_pullup())
+            .field("dp_pulldown", &self.dp_pulldown())
+            .field("dm_pullup", &self.dm_pullup())
+            .field("dm_pulldown", &self.dm_pulldown())
+            .field("pullup_value", &self.pullup_value())
+            .field("usb_pad_enable", &self.usb_pad_enable())
+            .field("phy_tx_edge_sel", &self.phy_tx_edge_sel())
+            .field("usb_jtag_bridge_en", &self.usb_jtag_bridge_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Select internal/external PHY"]
     #[inline(always)]
diff --git a/esp32s3/src/usb_device/date.rs b/esp32s3/src/usb_device/date.rs
index 8db37bf059..054f91d9ab 100644
--- a/esp32s3/src/usb_device/date.rs
+++ b/esp32s3/src/usb_device/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/usb_device/ep1.rs b/esp32s3/src/usb_device/ep1.rs
index 006d94227a..ac925c6fd0 100644
--- a/esp32s3/src/usb_device/ep1.rs
+++ b/esp32s3/src/usb_device/ep1.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EP1")
-            .field("rdwr_byte", &format_args!("{}", self.rdwr_byte().bits()))
+            .field("rdwr_byte", &self.rdwr_byte())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EP1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:7 - Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO."]
     #[inline(always)]
diff --git a/esp32s3/src/usb_device/ep1_conf.rs b/esp32s3/src/usb_device/ep1_conf.rs
index c4720d2b85..1bc9186f7c 100644
--- a/esp32s3/src/usb_device/ep1_conf.rs
+++ b/esp32s3/src/usb_device/ep1_conf.rs
@@ -24,23 +24,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("EP1_CONF")
-            .field(
-                "serial_in_ep_data_free",
-                &format_args!("{}", self.serial_in_ep_data_free().bit()),
-            )
-            .field(
-                "serial_out_ep_data_avail",
-                &format_args!("{}", self.serial_out_ep_data_avail().bit()),
-            )
+            .field("serial_in_ep_data_free", &self.serial_in_ep_data_free())
+            .field("serial_out_ep_data_avail", &self.serial_out_ep_data_avail())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<EP1_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Set this bit to indicate writing byte data to UART Tx FIFO is done."]
     #[inline(always)]
diff --git a/esp32s3/src/usb_device/fram_num.rs b/esp32s3/src/usb_device/fram_num.rs
index f8d2a61811..49af9712de 100644
--- a/esp32s3/src/usb_device/fram_num.rs
+++ b/esp32s3/src/usb_device/fram_num.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("FRAM_NUM")
-            .field(
-                "sof_frame_index",
-                &format_args!("{}", self.sof_frame_index().bits()),
-            )
+            .field("sof_frame_index", &self.sof_frame_index())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<FRAM_NUM_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "SOF frame number\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fram_num::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FRAM_NUM_SPEC;
 impl crate::RegisterSpec for FRAM_NUM_SPEC {
diff --git a/esp32s3/src/usb_device/in_ep0_st.rs b/esp32s3/src/usb_device/in_ep0_st.rs
index 5001a124b7..7261ef5742 100644
--- a/esp32s3/src/usb_device/in_ep0_st.rs
+++ b/esp32s3/src/usb_device/in_ep0_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP0_ST")
-            .field(
-                "in_ep0_state",
-                &format_args!("{}", self.in_ep0_state().bits()),
-            )
-            .field(
-                "in_ep0_wr_addr",
-                &format_args!("{}", self.in_ep0_wr_addr().bits()),
-            )
-            .field(
-                "in_ep0_rd_addr",
-                &format_args!("{}", self.in_ep0_rd_addr().bits()),
-            )
+            .field("in_ep0_state", &self.in_ep0_state())
+            .field("in_ep0_wr_addr", &self.in_ep0_wr_addr())
+            .field("in_ep0_rd_addr", &self.in_ep0_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP0_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "IN Endpoint 0 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep0_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP0_ST_SPEC;
 impl crate::RegisterSpec for IN_EP0_ST_SPEC {
diff --git a/esp32s3/src/usb_device/in_ep1_st.rs b/esp32s3/src/usb_device/in_ep1_st.rs
index 83cecdf45b..f0d99286d0 100644
--- a/esp32s3/src/usb_device/in_ep1_st.rs
+++ b/esp32s3/src/usb_device/in_ep1_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP1_ST")
-            .field(
-                "in_ep1_state",
-                &format_args!("{}", self.in_ep1_state().bits()),
-            )
-            .field(
-                "in_ep1_wr_addr",
-                &format_args!("{}", self.in_ep1_wr_addr().bits()),
-            )
-            .field(
-                "in_ep1_rd_addr",
-                &format_args!("{}", self.in_ep1_rd_addr().bits()),
-            )
+            .field("in_ep1_state", &self.in_ep1_state())
+            .field("in_ep1_wr_addr", &self.in_ep1_wr_addr())
+            .field("in_ep1_rd_addr", &self.in_ep1_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP1_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "IN Endpoint 1 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep1_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP1_ST_SPEC;
 impl crate::RegisterSpec for IN_EP1_ST_SPEC {
diff --git a/esp32s3/src/usb_device/in_ep2_st.rs b/esp32s3/src/usb_device/in_ep2_st.rs
index 7d5b378276..a13d76f1e3 100644
--- a/esp32s3/src/usb_device/in_ep2_st.rs
+++ b/esp32s3/src/usb_device/in_ep2_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP2_ST")
-            .field(
-                "in_ep2_state",
-                &format_args!("{}", self.in_ep2_state().bits()),
-            )
-            .field(
-                "in_ep2_wr_addr",
-                &format_args!("{}", self.in_ep2_wr_addr().bits()),
-            )
-            .field(
-                "in_ep2_rd_addr",
-                &format_args!("{}", self.in_ep2_rd_addr().bits()),
-            )
+            .field("in_ep2_state", &self.in_ep2_state())
+            .field("in_ep2_wr_addr", &self.in_ep2_wr_addr())
+            .field("in_ep2_rd_addr", &self.in_ep2_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP2_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "IN Endpoint 2 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep2_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP2_ST_SPEC;
 impl crate::RegisterSpec for IN_EP2_ST_SPEC {
diff --git a/esp32s3/src/usb_device/in_ep3_st.rs b/esp32s3/src/usb_device/in_ep3_st.rs
index c33b5601ae..288abcec79 100644
--- a/esp32s3/src/usb_device/in_ep3_st.rs
+++ b/esp32s3/src/usb_device/in_ep3_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("IN_EP3_ST")
-            .field(
-                "in_ep3_state",
-                &format_args!("{}", self.in_ep3_state().bits()),
-            )
-            .field(
-                "in_ep3_wr_addr",
-                &format_args!("{}", self.in_ep3_wr_addr().bits()),
-            )
-            .field(
-                "in_ep3_rd_addr",
-                &format_args!("{}", self.in_ep3_rd_addr().bits()),
-            )
+            .field("in_ep3_state", &self.in_ep3_state())
+            .field("in_ep3_wr_addr", &self.in_ep3_wr_addr())
+            .field("in_ep3_rd_addr", &self.in_ep3_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<IN_EP3_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "IN Endpoint 3 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ep3_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IN_EP3_ST_SPEC;
 impl crate::RegisterSpec for IN_EP3_ST_SPEC {
diff --git a/esp32s3/src/usb_device/int_ena.rs b/esp32s3/src/usb_device/int_ena.rs
index d6f1f52eb6..1d413654b3 100644
--- a/esp32s3/src/usb_device/int_ena.rs
+++ b/esp32s3/src/usb_device/int_ena.rs
@@ -116,48 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ENA")
-            .field(
-                "jtag_in_flush",
-                &format_args!("{}", self.jtag_in_flush().bit()),
-            )
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field(
-                "serial_out_recv_pkt",
-                &format_args!("{}", self.serial_out_recv_pkt().bit()),
-            )
-            .field(
-                "serial_in_empty",
-                &format_args!("{}", self.serial_in_empty().bit()),
-            )
-            .field("pid_err", &format_args!("{}", self.pid_err().bit()))
-            .field("crc5_err", &format_args!("{}", self.crc5_err().bit()))
-            .field("crc16_err", &format_args!("{}", self.crc16_err().bit()))
-            .field("stuff_err", &format_args!("{}", self.stuff_err().bit()))
-            .field(
-                "in_token_rec_in_ep1",
-                &format_args!("{}", self.in_token_rec_in_ep1().bit()),
-            )
-            .field(
-                "usb_bus_reset",
-                &format_args!("{}", self.usb_bus_reset().bit()),
-            )
-            .field(
-                "out_ep1_zero_payload",
-                &format_args!("{}", self.out_ep1_zero_payload().bit()),
-            )
-            .field(
-                "out_ep2_zero_payload",
-                &format_args!("{}", self.out_ep2_zero_payload().bit()),
-            )
+            .field("jtag_in_flush", &self.jtag_in_flush())
+            .field("sof", &self.sof())
+            .field("serial_out_recv_pkt", &self.serial_out_recv_pkt())
+            .field("serial_in_empty", &self.serial_in_empty())
+            .field("pid_err", &self.pid_err())
+            .field("crc5_err", &self.crc5_err())
+            .field("crc16_err", &self.crc16_err())
+            .field("stuff_err", &self.stuff_err())
+            .field("in_token_rec_in_ep1", &self.in_token_rec_in_ep1())
+            .field("usb_bus_reset", &self.usb_bus_reset())
+            .field("out_ep1_zero_payload", &self.out_ep1_zero_payload())
+            .field("out_ep2_zero_payload", &self.out_ep2_zero_payload())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt."]
     #[inline(always)]
diff --git a/esp32s3/src/usb_device/int_raw.rs b/esp32s3/src/usb_device/int_raw.rs
index ae7706cbde..87c575378b 100644
--- a/esp32s3/src/usb_device/int_raw.rs
+++ b/esp32s3/src/usb_device/int_raw.rs
@@ -116,48 +116,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_RAW")
-            .field(
-                "jtag_in_flush",
-                &format_args!("{}", self.jtag_in_flush().bit()),
-            )
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field(
-                "serial_out_recv_pkt",
-                &format_args!("{}", self.serial_out_recv_pkt().bit()),
-            )
-            .field(
-                "serial_in_empty",
-                &format_args!("{}", self.serial_in_empty().bit()),
-            )
-            .field("pid_err", &format_args!("{}", self.pid_err().bit()))
-            .field("crc5_err", &format_args!("{}", self.crc5_err().bit()))
-            .field("crc16_err", &format_args!("{}", self.crc16_err().bit()))
-            .field("stuff_err", &format_args!("{}", self.stuff_err().bit()))
-            .field(
-                "in_token_rec_in_ep1",
-                &format_args!("{}", self.in_token_rec_in_ep1().bit()),
-            )
-            .field(
-                "usb_bus_reset",
-                &format_args!("{}", self.usb_bus_reset().bit()),
-            )
-            .field(
-                "out_ep1_zero_payload",
-                &format_args!("{}", self.out_ep1_zero_payload().bit()),
-            )
-            .field(
-                "out_ep2_zero_payload",
-                &format_args!("{}", self.out_ep2_zero_payload().bit()),
-            )
+            .field("jtag_in_flush", &self.jtag_in_flush())
+            .field("sof", &self.sof())
+            .field("serial_out_recv_pkt", &self.serial_out_recv_pkt())
+            .field("serial_in_empty", &self.serial_in_empty())
+            .field("pid_err", &self.pid_err())
+            .field("crc5_err", &self.crc5_err())
+            .field("crc16_err", &self.crc16_err())
+            .field("stuff_err", &self.stuff_err())
+            .field("in_token_rec_in_ep1", &self.in_token_rec_in_ep1())
+            .field("usb_bus_reset", &self.usb_bus_reset())
+            .field("out_ep1_zero_payload", &self.out_ep1_zero_payload())
+            .field("out_ep2_zero_payload", &self.out_ep2_zero_payload())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG."]
     #[inline(always)]
diff --git a/esp32s3/src/usb_device/int_st.rs b/esp32s3/src/usb_device/int_st.rs
index b566bba379..0395bd2c51 100644
--- a/esp32s3/src/usb_device/int_st.rs
+++ b/esp32s3/src/usb_device/int_st.rs
@@ -90,48 +90,21 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("INT_ST")
-            .field(
-                "jtag_in_flush",
-                &format_args!("{}", self.jtag_in_flush().bit()),
-            )
-            .field("sof", &format_args!("{}", self.sof().bit()))
-            .field(
-                "serial_out_recv_pkt",
-                &format_args!("{}", self.serial_out_recv_pkt().bit()),
-            )
-            .field(
-                "serial_in_empty",
-                &format_args!("{}", self.serial_in_empty().bit()),
-            )
-            .field("pid_err", &format_args!("{}", self.pid_err().bit()))
-            .field("crc5_err", &format_args!("{}", self.crc5_err().bit()))
-            .field("crc16_err", &format_args!("{}", self.crc16_err().bit()))
-            .field("stuff_err", &format_args!("{}", self.stuff_err().bit()))
-            .field(
-                "in_token_rec_in_ep1",
-                &format_args!("{}", self.in_token_rec_in_ep1().bit()),
-            )
-            .field(
-                "usb_bus_reset",
-                &format_args!("{}", self.usb_bus_reset().bit()),
-            )
-            .field(
-                "out_ep1_zero_payload",
-                &format_args!("{}", self.out_ep1_zero_payload().bit()),
-            )
-            .field(
-                "out_ep2_zero_payload",
-                &format_args!("{}", self.out_ep2_zero_payload().bit()),
-            )
+            .field("jtag_in_flush", &self.jtag_in_flush())
+            .field("sof", &self.sof())
+            .field("serial_out_recv_pkt", &self.serial_out_recv_pkt())
+            .field("serial_in_empty", &self.serial_in_empty())
+            .field("pid_err", &self.pid_err())
+            .field("crc5_err", &self.crc5_err())
+            .field("crc16_err", &self.crc16_err())
+            .field("stuff_err", &self.stuff_err())
+            .field("in_token_rec_in_ep1", &self.in_token_rec_in_ep1())
+            .field("usb_bus_reset", &self.usb_bus_reset())
+            .field("out_ep1_zero_payload", &self.out_ep1_zero_payload())
+            .field("out_ep2_zero_payload", &self.out_ep2_zero_payload())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Masked interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INT_ST_SPEC;
 impl crate::RegisterSpec for INT_ST_SPEC {
diff --git a/esp32s3/src/usb_device/jfifo_st.rs b/esp32s3/src/usb_device/jfifo_st.rs
index b577f17194..9f7a4de681 100644
--- a/esp32s3/src/usb_device/jfifo_st.rs
+++ b/esp32s3/src/usb_device/jfifo_st.rs
@@ -68,47 +68,17 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("JFIFO_ST")
-            .field(
-                "in_fifo_cnt",
-                &format_args!("{}", self.in_fifo_cnt().bits()),
-            )
-            .field(
-                "in_fifo_empty",
-                &format_args!("{}", self.in_fifo_empty().bit()),
-            )
-            .field(
-                "in_fifo_full",
-                &format_args!("{}", self.in_fifo_full().bit()),
-            )
-            .field(
-                "out_fifo_cnt",
-                &format_args!("{}", self.out_fifo_cnt().bits()),
-            )
-            .field(
-                "out_fifo_empty",
-                &format_args!("{}", self.out_fifo_empty().bit()),
-            )
-            .field(
-                "out_fifo_full",
-                &format_args!("{}", self.out_fifo_full().bit()),
-            )
-            .field(
-                "in_fifo_reset",
-                &format_args!("{}", self.in_fifo_reset().bit()),
-            )
-            .field(
-                "out_fifo_reset",
-                &format_args!("{}", self.out_fifo_reset().bit()),
-            )
+            .field("in_fifo_cnt", &self.in_fifo_cnt())
+            .field("in_fifo_empty", &self.in_fifo_empty())
+            .field("in_fifo_full", &self.in_fifo_full())
+            .field("out_fifo_cnt", &self.out_fifo_cnt())
+            .field("out_fifo_empty", &self.out_fifo_empty())
+            .field("out_fifo_full", &self.out_fifo_full())
+            .field("in_fifo_reset", &self.in_fifo_reset())
+            .field("out_fifo_reset", &self.out_fifo_reset())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<JFIFO_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 8 - Write 1 to reset JTAG in fifo."]
     #[inline(always)]
diff --git a/esp32s3/src/usb_device/mem_conf.rs b/esp32s3/src/usb_device/mem_conf.rs
index 742805d229..9aaff1a171 100644
--- a/esp32s3/src/usb_device/mem_conf.rs
+++ b/esp32s3/src/usb_device/mem_conf.rs
@@ -26,20 +26,11 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MEM_CONF")
-            .field("usb_mem_pd", &format_args!("{}", self.usb_mem_pd().bit()))
-            .field(
-                "usb_mem_clk_en",
-                &format_args!("{}", self.usb_mem_clk_en().bit()),
-            )
+            .field("usb_mem_pd", &self.usb_mem_pd())
+            .field("usb_mem_clk_en", &self.usb_mem_clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MEM_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1: power down usb memory."]
     #[inline(always)]
diff --git a/esp32s3/src/usb_device/misc_conf.rs b/esp32s3/src/usb_device/misc_conf.rs
index b4dce786ef..e600887527 100644
--- a/esp32s3/src/usb_device/misc_conf.rs
+++ b/esp32s3/src/usb_device/misc_conf.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("MISC_CONF")
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<MISC_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
     #[inline(always)]
diff --git a/esp32s3/src/usb_device/out_ep0_st.rs b/esp32s3/src/usb_device/out_ep0_st.rs
index 9d60130ddf..a52bcba05c 100644
--- a/esp32s3/src/usb_device/out_ep0_st.rs
+++ b/esp32s3/src/usb_device/out_ep0_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EP0_ST")
-            .field(
-                "out_ep0_state",
-                &format_args!("{}", self.out_ep0_state().bits()),
-            )
-            .field(
-                "out_ep0_wr_addr",
-                &format_args!("{}", self.out_ep0_wr_addr().bits()),
-            )
-            .field(
-                "out_ep0_rd_addr",
-                &format_args!("{}", self.out_ep0_rd_addr().bits()),
-            )
+            .field("out_ep0_state", &self.out_ep0_state())
+            .field("out_ep0_wr_addr", &self.out_ep0_wr_addr())
+            .field("out_ep0_rd_addr", &self.out_ep0_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EP0_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "OUT Endpoint 0 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep0_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EP0_ST_SPEC;
 impl crate::RegisterSpec for OUT_EP0_ST_SPEC {
diff --git a/esp32s3/src/usb_device/out_ep1_st.rs b/esp32s3/src/usb_device/out_ep1_st.rs
index 47d6e718c7..a785bd52f2 100644
--- a/esp32s3/src/usb_device/out_ep1_st.rs
+++ b/esp32s3/src/usb_device/out_ep1_st.rs
@@ -34,31 +34,13 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EP1_ST")
-            .field(
-                "out_ep1_state",
-                &format_args!("{}", self.out_ep1_state().bits()),
-            )
-            .field(
-                "out_ep1_wr_addr",
-                &format_args!("{}", self.out_ep1_wr_addr().bits()),
-            )
-            .field(
-                "out_ep1_rd_addr",
-                &format_args!("{}", self.out_ep1_rd_addr().bits()),
-            )
-            .field(
-                "out_ep1_rec_data_cnt",
-                &format_args!("{}", self.out_ep1_rec_data_cnt().bits()),
-            )
+            .field("out_ep1_state", &self.out_ep1_state())
+            .field("out_ep1_wr_addr", &self.out_ep1_wr_addr())
+            .field("out_ep1_rd_addr", &self.out_ep1_rd_addr())
+            .field("out_ep1_rec_data_cnt", &self.out_ep1_rec_data_cnt())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EP1_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "OUT Endpoint 1 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep1_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EP1_ST_SPEC;
 impl crate::RegisterSpec for OUT_EP1_ST_SPEC {
diff --git a/esp32s3/src/usb_device/out_ep2_st.rs b/esp32s3/src/usb_device/out_ep2_st.rs
index 670c913087..1debcb707f 100644
--- a/esp32s3/src/usb_device/out_ep2_st.rs
+++ b/esp32s3/src/usb_device/out_ep2_st.rs
@@ -27,27 +27,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OUT_EP2_ST")
-            .field(
-                "out_ep2_state",
-                &format_args!("{}", self.out_ep2_state().bits()),
-            )
-            .field(
-                "out_ep2_wr_addr",
-                &format_args!("{}", self.out_ep2_wr_addr().bits()),
-            )
-            .field(
-                "out_ep2_rd_addr",
-                &format_args!("{}", self.out_ep2_rd_addr().bits()),
-            )
+            .field("out_ep2_state", &self.out_ep2_state())
+            .field("out_ep2_wr_addr", &self.out_ep2_wr_addr())
+            .field("out_ep2_rd_addr", &self.out_ep2_rd_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OUT_EP2_ST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "OUT Endpoint 2 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ep2_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct OUT_EP2_ST_SPEC;
 impl crate::RegisterSpec for OUT_EP2_ST_SPEC {
diff --git a/esp32s3/src/usb_device/test.rs b/esp32s3/src/usb_device/test.rs
index 033552bc63..4ae898ea64 100644
--- a/esp32s3/src/usb_device/test.rs
+++ b/esp32s3/src/usb_device/test.rs
@@ -65,22 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEST")
-            .field("enable", &format_args!("{}", self.enable().bit()))
-            .field("usb_oe", &format_args!("{}", self.usb_oe().bit()))
-            .field("tx_dp", &format_args!("{}", self.tx_dp().bit()))
-            .field("tx_dm", &format_args!("{}", self.tx_dm().bit()))
-            .field("rx_rcv", &format_args!("{}", self.rx_rcv().bit()))
-            .field("rx_dp", &format_args!("{}", self.rx_dp().bit()))
-            .field("rx_dm", &format_args!("{}", self.rx_dm().bit()))
+            .field("enable", &self.enable())
+            .field("usb_oe", &self.usb_oe())
+            .field("tx_dp", &self.tx_dp())
+            .field("tx_dm", &self.tx_dm())
+            .field("rx_rcv", &self.rx_rcv())
+            .field("rx_dp", &self.rx_dp())
+            .field("rx_dm", &self.rx_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEST_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable test of the USB pad"]
     #[inline(always)]
diff --git a/esp32s3/src/usb_wrap/date.rs b/esp32s3/src/usb_wrap/date.rs
index c3bea7ca6c..aabca88dec 100644
--- a/esp32s3/src/usb_wrap/date.rs
+++ b/esp32s3/src/usb_wrap/date.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DATE")
-            .field(
-                "usb_wrap_date",
-                &format_args!("{}", self.usb_wrap_date().bits()),
-            )
+            .field("usb_wrap_date", &self.usb_wrap_date())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Date register"]
     #[inline(always)]
diff --git a/esp32s3/src/usb_wrap/otg_conf.rs b/esp32s3/src/usb_wrap/otg_conf.rs
index cf268b2795..b01340ca50 100644
--- a/esp32s3/src/usb_wrap/otg_conf.rs
+++ b/esp32s3/src/usb_wrap/otg_conf.rs
@@ -206,76 +206,31 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("OTG_CONF")
-            .field(
-                "srp_sessend_override",
-                &format_args!("{}", self.srp_sessend_override().bit()),
-            )
-            .field(
-                "srp_sessend_value",
-                &format_args!("{}", self.srp_sessend_value().bit()),
-            )
-            .field("phy_sel", &format_args!("{}", self.phy_sel().bit()))
-            .field(
-                "dfifo_force_pd",
-                &format_args!("{}", self.dfifo_force_pd().bit()),
-            )
-            .field(
-                "dbnce_fltr_bypass",
-                &format_args!("{}", self.dbnce_fltr_bypass().bit()),
-            )
-            .field(
-                "exchg_pins_override",
-                &format_args!("{}", self.exchg_pins_override().bit()),
-            )
-            .field("exchg_pins", &format_args!("{}", self.exchg_pins().bit()))
-            .field("vrefh", &format_args!("{}", self.vrefh().bits()))
-            .field("vrefl", &format_args!("{}", self.vrefl().bits()))
-            .field(
-                "vref_override",
-                &format_args!("{}", self.vref_override().bit()),
-            )
-            .field(
-                "pad_pull_override",
-                &format_args!("{}", self.pad_pull_override().bit()),
-            )
-            .field("dp_pullup", &format_args!("{}", self.dp_pullup().bit()))
-            .field("dp_pulldown", &format_args!("{}", self.dp_pulldown().bit()))
-            .field("dm_pullup", &format_args!("{}", self.dm_pullup().bit()))
-            .field("dm_pulldown", &format_args!("{}", self.dm_pulldown().bit()))
-            .field(
-                "pullup_value",
-                &format_args!("{}", self.pullup_value().bit()),
-            )
-            .field(
-                "usb_pad_enable",
-                &format_args!("{}", self.usb_pad_enable().bit()),
-            )
-            .field(
-                "ahb_clk_force_on",
-                &format_args!("{}", self.ahb_clk_force_on().bit()),
-            )
-            .field(
-                "phy_clk_force_on",
-                &format_args!("{}", self.phy_clk_force_on().bit()),
-            )
-            .field(
-                "phy_tx_edge_sel",
-                &format_args!("{}", self.phy_tx_edge_sel().bit()),
-            )
-            .field(
-                "dfifo_force_pu",
-                &format_args!("{}", self.dfifo_force_pu().bit()),
-            )
-            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
+            .field("srp_sessend_override", &self.srp_sessend_override())
+            .field("srp_sessend_value", &self.srp_sessend_value())
+            .field("phy_sel", &self.phy_sel())
+            .field("dfifo_force_pd", &self.dfifo_force_pd())
+            .field("dbnce_fltr_bypass", &self.dbnce_fltr_bypass())
+            .field("exchg_pins_override", &self.exchg_pins_override())
+            .field("exchg_pins", &self.exchg_pins())
+            .field("vrefh", &self.vrefh())
+            .field("vrefl", &self.vrefl())
+            .field("vref_override", &self.vref_override())
+            .field("pad_pull_override", &self.pad_pull_override())
+            .field("dp_pullup", &self.dp_pullup())
+            .field("dp_pulldown", &self.dp_pulldown())
+            .field("dm_pullup", &self.dm_pullup())
+            .field("dm_pulldown", &self.dm_pulldown())
+            .field("pullup_value", &self.pullup_value())
+            .field("usb_pad_enable", &self.usb_pad_enable())
+            .field("ahb_clk_force_on", &self.ahb_clk_force_on())
+            .field("phy_clk_force_on", &self.phy_clk_force_on())
+            .field("phy_tx_edge_sel", &self.phy_tx_edge_sel())
+            .field("dfifo_force_pu", &self.dfifo_force_pu())
+            .field("clk_en", &self.clk_en())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<OTG_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software."]
     #[inline(always)]
diff --git a/esp32s3/src/usb_wrap/test_conf.rs b/esp32s3/src/usb_wrap/test_conf.rs
index 1524639a60..8b557fcdc0 100644
--- a/esp32s3/src/usb_wrap/test_conf.rs
+++ b/esp32s3/src/usb_wrap/test_conf.rs
@@ -65,22 +65,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("TEST_CONF")
-            .field("test_enable", &format_args!("{}", self.test_enable().bit()))
-            .field("test_usb_oe", &format_args!("{}", self.test_usb_oe().bit()))
-            .field("test_tx_dp", &format_args!("{}", self.test_tx_dp().bit()))
-            .field("test_tx_dm", &format_args!("{}", self.test_tx_dm().bit()))
-            .field("test_rx_rcv", &format_args!("{}", self.test_rx_rcv().bit()))
-            .field("test_rx_dp", &format_args!("{}", self.test_rx_dp().bit()))
-            .field("test_rx_dm", &format_args!("{}", self.test_rx_dm().bit()))
+            .field("test_enable", &self.test_enable())
+            .field("test_usb_oe", &self.test_usb_oe())
+            .field("test_tx_dp", &self.test_tx_dp())
+            .field("test_tx_dm", &self.test_tx_dm())
+            .field("test_rx_rcv", &self.test_rx_rcv())
+            .field("test_rx_dp", &self.test_rx_dp())
+            .field("test_rx_dm", &self.test_rx_dm())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<TEST_CONF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Enable test of the USB pad"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_entry_10_addr.rs b/esp32s3/src/wcl/core_0_entry_10_addr.rs
index 5dc48bf67a..c8386efb52 100644
--- a/esp32s3/src/wcl/core_0_entry_10_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_10_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_ENTRY_10_ADDR")
-            .field(
-                "core_0_entry_10_addr",
-                &format_args!("{}", self.core_0_entry_10_addr().bits()),
-            )
+            .field("core_0_entry_10_addr", &self.core_0_entry_10_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_ENTRY_10_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 10 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_entry_11_addr.rs b/esp32s3/src/wcl/core_0_entry_11_addr.rs
index 560fde1fab..7b60d31008 100644
--- a/esp32s3/src/wcl/core_0_entry_11_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_11_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_ENTRY_11_ADDR")
-            .field(
-                "core_0_entry_11_addr",
-                &format_args!("{}", self.core_0_entry_11_addr().bits()),
-            )
+            .field("core_0_entry_11_addr", &self.core_0_entry_11_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_ENTRY_11_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 11 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_entry_12_addr.rs b/esp32s3/src/wcl/core_0_entry_12_addr.rs
index 3c21b3f3a3..6c25f84c15 100644
--- a/esp32s3/src/wcl/core_0_entry_12_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_12_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_ENTRY_12_ADDR")
-            .field(
-                "core_0_entry_12_addr",
-                &format_args!("{}", self.core_0_entry_12_addr().bits()),
-            )
+            .field("core_0_entry_12_addr", &self.core_0_entry_12_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_ENTRY_12_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 12 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_entry_13_addr.rs b/esp32s3/src/wcl/core_0_entry_13_addr.rs
index fa73a0c5af..41d89f72ea 100644
--- a/esp32s3/src/wcl/core_0_entry_13_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_13_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_ENTRY_13_ADDR")
-            .field(
-                "core_0_entry_13_addr",
-                &format_args!("{}", self.core_0_entry_13_addr().bits()),
-            )
+            .field("core_0_entry_13_addr", &self.core_0_entry_13_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_ENTRY_13_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 13 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_entry_1_addr.rs b/esp32s3/src/wcl/core_0_entry_1_addr.rs
index 1597920032..7763f59a27 100644
--- a/esp32s3/src/wcl/core_0_entry_1_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_1_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_ENTRY_1_ADDR")
-            .field(
-                "core_0_entry_1_addr",
-                &format_args!("{}", self.core_0_entry_1_addr().bits()),
-            )
+            .field("core_0_entry_1_addr", &self.core_0_entry_1_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_ENTRY_1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 1 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_entry_2_addr.rs b/esp32s3/src/wcl/core_0_entry_2_addr.rs
index 8ee4d383f4..b9871a0aa0 100644
--- a/esp32s3/src/wcl/core_0_entry_2_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_2_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_ENTRY_2_ADDR")
-            .field(
-                "core_0_entry_2_addr",
-                &format_args!("{}", self.core_0_entry_2_addr().bits()),
-            )
+            .field("core_0_entry_2_addr", &self.core_0_entry_2_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_ENTRY_2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 2 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_entry_3_addr.rs b/esp32s3/src/wcl/core_0_entry_3_addr.rs
index e696182b35..4b465a4d75 100644
--- a/esp32s3/src/wcl/core_0_entry_3_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_3_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_ENTRY_3_ADDR")
-            .field(
-                "core_0_entry_3_addr",
-                &format_args!("{}", self.core_0_entry_3_addr().bits()),
-            )
+            .field("core_0_entry_3_addr", &self.core_0_entry_3_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_ENTRY_3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 3 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_entry_4_addr.rs b/esp32s3/src/wcl/core_0_entry_4_addr.rs
index d4ab464a31..9e4a1c289f 100644
--- a/esp32s3/src/wcl/core_0_entry_4_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_4_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_ENTRY_4_ADDR")
-            .field(
-                "core_0_entry_4_addr",
-                &format_args!("{}", self.core_0_entry_4_addr().bits()),
-            )
+            .field("core_0_entry_4_addr", &self.core_0_entry_4_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_ENTRY_4_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 4 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_entry_5_addr.rs b/esp32s3/src/wcl/core_0_entry_5_addr.rs
index a51c28df05..782f0c3eda 100644
--- a/esp32s3/src/wcl/core_0_entry_5_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_5_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_ENTRY_5_ADDR")
-            .field(
-                "core_0_entry_5_addr",
-                &format_args!("{}", self.core_0_entry_5_addr().bits()),
-            )
+            .field("core_0_entry_5_addr", &self.core_0_entry_5_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_ENTRY_5_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 5 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_entry_6_addr.rs b/esp32s3/src/wcl/core_0_entry_6_addr.rs
index acad034bd2..00994c8ee8 100644
--- a/esp32s3/src/wcl/core_0_entry_6_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_6_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_ENTRY_6_ADDR")
-            .field(
-                "core_0_entry_6_addr",
-                &format_args!("{}", self.core_0_entry_6_addr().bits()),
-            )
+            .field("core_0_entry_6_addr", &self.core_0_entry_6_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_ENTRY_6_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 6 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_entry_7_addr.rs b/esp32s3/src/wcl/core_0_entry_7_addr.rs
index c1b30fea70..b0bd0ab2dc 100644
--- a/esp32s3/src/wcl/core_0_entry_7_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_7_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_ENTRY_7_ADDR")
-            .field(
-                "core_0_entry_7_addr",
-                &format_args!("{}", self.core_0_entry_7_addr().bits()),
-            )
+            .field("core_0_entry_7_addr", &self.core_0_entry_7_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_ENTRY_7_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 7 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_entry_8_addr.rs b/esp32s3/src/wcl/core_0_entry_8_addr.rs
index e9836ded6b..b87ff1b406 100644
--- a/esp32s3/src/wcl/core_0_entry_8_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_8_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_ENTRY_8_ADDR")
-            .field(
-                "core_0_entry_8_addr",
-                &format_args!("{}", self.core_0_entry_8_addr().bits()),
-            )
+            .field("core_0_entry_8_addr", &self.core_0_entry_8_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_ENTRY_8_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 8 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_entry_9_addr.rs b/esp32s3/src/wcl/core_0_entry_9_addr.rs
index 70a73112ec..c9b380215b 100644
--- a/esp32s3/src/wcl/core_0_entry_9_addr.rs
+++ b/esp32s3/src/wcl/core_0_entry_9_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_ENTRY_9_ADDR")
-            .field(
-                "core_0_entry_9_addr",
-                &format_args!("{}", self.core_0_entry_9_addr().bits()),
-            )
+            .field("core_0_entry_9_addr", &self.core_0_entry_9_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_ENTRY_9_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_0 Entry 9 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_entry_check.rs b/esp32s3/src/wcl/core_0_entry_check.rs
index 848d090763..549e5872ad 100644
--- a/esp32s3/src/wcl/core_0_entry_check.rs
+++ b/esp32s3/src/wcl/core_0_entry_check.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_ENTRY_CHECK")
-            .field(
-                "core_0_entry_check",
-                &format_args!("{}", self.core_0_entry_check().bits()),
-            )
+            .field("core_0_entry_check", &self.core_0_entry_check())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_ENTRY_CHECK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 1:13 - This filed is used to enable entry address check"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_message_addr.rs b/esp32s3/src/wcl/core_0_message_addr.rs
index b80fa53ea9..f320a98b56 100644
--- a/esp32s3/src/wcl/core_0_message_addr.rs
+++ b/esp32s3/src/wcl/core_0_message_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_MESSAGE_ADDR")
-            .field(
-                "core_0_message_addr",
-                &format_args!("{}", self.core_0_message_addr().bits()),
-            )
+            .field("core_0_message_addr", &self.core_0_message_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_MESSAGE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This field is used to set address that need to write when enter WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_message_max.rs b/esp32s3/src/wcl/core_0_message_max.rs
index c19cb7280e..3c0bf8e31e 100644
--- a/esp32s3/src/wcl/core_0_message_max.rs
+++ b/esp32s3/src/wcl/core_0_message_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_MESSAGE_MAX")
-            .field(
-                "core_0_message_max",
-                &format_args!("{}", self.core_0_message_max().bits()),
-            )
+            .field("core_0_message_max", &self.core_0_message_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_MESSAGE_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - This filed is used to set the max value of clear write_buffer"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_message_phase.rs b/esp32s3/src/wcl/core_0_message_phase.rs
index 448206df89..85288f8ca0 100644
--- a/esp32s3/src/wcl/core_0_message_phase.rs
+++ b/esp32s3/src/wcl/core_0_message_phase.rs
@@ -34,31 +34,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_MESSAGE_PHASE")
-            .field(
-                "core_0_message_match",
-                &format_args!("{}", self.core_0_message_match().bit()),
-            )
-            .field(
-                "core_0_message_expect",
-                &format_args!("{}", self.core_0_message_expect().bits()),
-            )
-            .field(
-                "core_0_message_dataphase",
-                &format_args!("{}", self.core_0_message_dataphase().bit()),
-            )
+            .field("core_0_message_match", &self.core_0_message_match())
+            .field("core_0_message_expect", &self.core_0_message_expect())
+            .field("core_0_message_dataphase", &self.core_0_message_dataphase())
             .field(
                 "core_0_message_addressphase",
-                &format_args!("{}", self.core_0_message_addressphase().bit()),
+                &self.core_0_message_addressphase(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_MESSAGE_PHASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Clear writer_buffer status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_message_phase::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_MESSAGE_PHASE_SPEC;
 impl crate::RegisterSpec for CORE_0_MESSAGE_PHASE_SPEC {
diff --git a/esp32s3/src/wcl/core_0_nmi_mask.rs b/esp32s3/src/wcl/core_0_nmi_mask.rs
index 7fe67e5edc..eb77195a3e 100644
--- a/esp32s3/src/wcl/core_0_nmi_mask.rs
+++ b/esp32s3/src/wcl/core_0_nmi_mask.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_NMI_MASK")
-            .field(
-                "core_0_nmi_mask",
-                &format_args!("{}", self.core_0_nmi_mask().bit()),
-            )
+            .field("core_0_nmi_mask", &self.core_0_nmi_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_NMI_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit is used to mask NMI interrupt,it can directly mask NMI interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_nmi_mask_phase.rs b/esp32s3/src/wcl/core_0_nmi_mask_phase.rs
index 3cbd829b54..5c5fdd9e80 100644
--- a/esp32s3/src/wcl/core_0_nmi_mask_phase.rs
+++ b/esp32s3/src/wcl/core_0_nmi_mask_phase.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_NMI_MASK_PHASE")
-            .field(
-                "core_0_nmi_mask_phase",
-                &format_args!("{}", self.core_0_nmi_mask_phase().bit()),
-            )
+            .field("core_0_nmi_mask_phase", &self.core_0_nmi_mask_phase())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_NMI_MASK_PHASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core_0 NMI mask phase register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_nmi_mask_phase::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_NMI_MASK_PHASE_SPEC;
 impl crate::RegisterSpec for CORE_0_NMI_MASK_PHASE_SPEC {
diff --git a/esp32s3/src/wcl/core_0_nmi_mask_trigger_addr.rs b/esp32s3/src/wcl/core_0_nmi_mask_trigger_addr.rs
index 8a1f32256e..1892e28f2f 100644
--- a/esp32s3/src/wcl/core_0_nmi_mask_trigger_addr.rs
+++ b/esp32s3/src/wcl/core_0_nmi_mask_trigger_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("Core_0_NMI_MASK_TRIGGER_ADDR")
             .field(
                 "core_0_nmi_mask_trigger_addr",
-                &format_args!("{}", self.core_0_nmi_mask_trigger_addr().bits()),
+                &self.core_0_nmi_mask_trigger_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_NMI_MASK_TRIGGER_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - this field to used to set trigger address, when CPU executes to this address,NMI mask automatically fails"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_statustable1.rs b/esp32s3/src/wcl/core_0_statustable1.rs
index d92a6dca9c..2df91a99b4 100644
--- a/esp32s3/src/wcl/core_0_statustable1.rs
+++ b/esp32s3/src/wcl/core_0_statustable1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_STATUSTABLE1")
-            .field(
-                "core_0_from_world_1",
-                &format_args!("{}", self.core_0_from_world_1().bit()),
-            )
-            .field(
-                "core_0_from_entry_1",
-                &format_args!("{}", self.core_0_from_entry_1().bits()),
-            )
-            .field(
-                "core_0_current_1",
-                &format_args!("{}", self.core_0_current_1().bit()),
-            )
+            .field("core_0_from_world_1", &self.core_0_from_world_1())
+            .field("core_0_from_entry_1", &self.core_0_from_entry_1())
+            .field("core_0_current_1", &self.core_0_current_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_STATUSTABLE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 1"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_statustable10.rs b/esp32s3/src/wcl/core_0_statustable10.rs
index 1d26c42fb4..7b2f67e760 100644
--- a/esp32s3/src/wcl/core_0_statustable10.rs
+++ b/esp32s3/src/wcl/core_0_statustable10.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_STATUSTABLE10")
-            .field(
-                "core_0_from_world_10",
-                &format_args!("{}", self.core_0_from_world_10().bit()),
-            )
-            .field(
-                "core_0_from_entry_10",
-                &format_args!("{}", self.core_0_from_entry_10().bits()),
-            )
-            .field(
-                "core_0_current_10",
-                &format_args!("{}", self.core_0_current_10().bit()),
-            )
+            .field("core_0_from_world_10", &self.core_0_from_world_10())
+            .field("core_0_from_entry_10", &self.core_0_from_entry_10())
+            .field("core_0_current_10", &self.core_0_current_10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_STATUSTABLE10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 10"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_statustable11.rs b/esp32s3/src/wcl/core_0_statustable11.rs
index 41d93913a5..3fa5d19912 100644
--- a/esp32s3/src/wcl/core_0_statustable11.rs
+++ b/esp32s3/src/wcl/core_0_statustable11.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_STATUSTABLE11")
-            .field(
-                "core_0_from_world_11",
-                &format_args!("{}", self.core_0_from_world_11().bit()),
-            )
-            .field(
-                "core_0_from_entry_11",
-                &format_args!("{}", self.core_0_from_entry_11().bits()),
-            )
-            .field(
-                "core_0_current_11",
-                &format_args!("{}", self.core_0_current_11().bit()),
-            )
+            .field("core_0_from_world_11", &self.core_0_from_world_11())
+            .field("core_0_from_entry_11", &self.core_0_from_entry_11())
+            .field("core_0_current_11", &self.core_0_current_11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_STATUSTABLE11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 11"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_statustable12.rs b/esp32s3/src/wcl/core_0_statustable12.rs
index 277245a714..84148c34ab 100644
--- a/esp32s3/src/wcl/core_0_statustable12.rs
+++ b/esp32s3/src/wcl/core_0_statustable12.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_STATUSTABLE12")
-            .field(
-                "core_0_from_world_12",
-                &format_args!("{}", self.core_0_from_world_12().bit()),
-            )
-            .field(
-                "core_0_from_entry_12",
-                &format_args!("{}", self.core_0_from_entry_12().bits()),
-            )
-            .field(
-                "core_0_current_12",
-                &format_args!("{}", self.core_0_current_12().bit()),
-            )
+            .field("core_0_from_world_12", &self.core_0_from_world_12())
+            .field("core_0_from_entry_12", &self.core_0_from_entry_12())
+            .field("core_0_current_12", &self.core_0_current_12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_STATUSTABLE12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 12"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_statustable13.rs b/esp32s3/src/wcl/core_0_statustable13.rs
index a3d28ef784..b233d1102d 100644
--- a/esp32s3/src/wcl/core_0_statustable13.rs
+++ b/esp32s3/src/wcl/core_0_statustable13.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_STATUSTABLE13")
-            .field(
-                "core_0_from_world_13",
-                &format_args!("{}", self.core_0_from_world_13().bit()),
-            )
-            .field(
-                "core_0_from_entry_13",
-                &format_args!("{}", self.core_0_from_entry_13().bits()),
-            )
-            .field(
-                "core_0_current_13",
-                &format_args!("{}", self.core_0_current_13().bit()),
-            )
+            .field("core_0_from_world_13", &self.core_0_from_world_13())
+            .field("core_0_from_entry_13", &self.core_0_from_entry_13())
+            .field("core_0_current_13", &self.core_0_current_13())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_STATUSTABLE13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 13"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_statustable2.rs b/esp32s3/src/wcl/core_0_statustable2.rs
index 24c63cca3d..b0ccca8cbe 100644
--- a/esp32s3/src/wcl/core_0_statustable2.rs
+++ b/esp32s3/src/wcl/core_0_statustable2.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_STATUSTABLE2")
-            .field(
-                "core_0_from_world_2",
-                &format_args!("{}", self.core_0_from_world_2().bit()),
-            )
-            .field(
-                "core_0_from_entry_2",
-                &format_args!("{}", self.core_0_from_entry_2().bits()),
-            )
-            .field(
-                "core_0_current_2",
-                &format_args!("{}", self.core_0_current_2().bit()),
-            )
+            .field("core_0_from_world_2", &self.core_0_from_world_2())
+            .field("core_0_from_entry_2", &self.core_0_from_entry_2())
+            .field("core_0_current_2", &self.core_0_current_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_STATUSTABLE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 2"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_statustable3.rs b/esp32s3/src/wcl/core_0_statustable3.rs
index 34ed28030c..83ab809fdf 100644
--- a/esp32s3/src/wcl/core_0_statustable3.rs
+++ b/esp32s3/src/wcl/core_0_statustable3.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_STATUSTABLE3")
-            .field(
-                "core_0_from_world_3",
-                &format_args!("{}", self.core_0_from_world_3().bit()),
-            )
-            .field(
-                "core_0_from_entry_3",
-                &format_args!("{}", self.core_0_from_entry_3().bits()),
-            )
-            .field(
-                "core_0_current_3",
-                &format_args!("{}", self.core_0_current_3().bit()),
-            )
+            .field("core_0_from_world_3", &self.core_0_from_world_3())
+            .field("core_0_from_entry_3", &self.core_0_from_entry_3())
+            .field("core_0_current_3", &self.core_0_current_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_STATUSTABLE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 3"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_statustable4.rs b/esp32s3/src/wcl/core_0_statustable4.rs
index c2729a1001..23b19bb447 100644
--- a/esp32s3/src/wcl/core_0_statustable4.rs
+++ b/esp32s3/src/wcl/core_0_statustable4.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_STATUSTABLE4")
-            .field(
-                "core_0_from_world_4",
-                &format_args!("{}", self.core_0_from_world_4().bit()),
-            )
-            .field(
-                "core_0_from_entry_4",
-                &format_args!("{}", self.core_0_from_entry_4().bits()),
-            )
-            .field(
-                "core_0_current_4",
-                &format_args!("{}", self.core_0_current_4().bit()),
-            )
+            .field("core_0_from_world_4", &self.core_0_from_world_4())
+            .field("core_0_from_entry_4", &self.core_0_from_entry_4())
+            .field("core_0_current_4", &self.core_0_current_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_STATUSTABLE4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 4"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_statustable5.rs b/esp32s3/src/wcl/core_0_statustable5.rs
index c61f810f65..37be2fac08 100644
--- a/esp32s3/src/wcl/core_0_statustable5.rs
+++ b/esp32s3/src/wcl/core_0_statustable5.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_STATUSTABLE5")
-            .field(
-                "core_0_from_world_5",
-                &format_args!("{}", self.core_0_from_world_5().bit()),
-            )
-            .field(
-                "core_0_from_entry_5",
-                &format_args!("{}", self.core_0_from_entry_5().bits()),
-            )
-            .field(
-                "core_0_current_5",
-                &format_args!("{}", self.core_0_current_5().bit()),
-            )
+            .field("core_0_from_world_5", &self.core_0_from_world_5())
+            .field("core_0_from_entry_5", &self.core_0_from_entry_5())
+            .field("core_0_current_5", &self.core_0_current_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_STATUSTABLE5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 5"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_statustable6.rs b/esp32s3/src/wcl/core_0_statustable6.rs
index 5cf57edacf..2fede6be1e 100644
--- a/esp32s3/src/wcl/core_0_statustable6.rs
+++ b/esp32s3/src/wcl/core_0_statustable6.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_STATUSTABLE6")
-            .field(
-                "core_0_from_world_6",
-                &format_args!("{}", self.core_0_from_world_6().bit()),
-            )
-            .field(
-                "core_0_from_entry_6",
-                &format_args!("{}", self.core_0_from_entry_6().bits()),
-            )
-            .field(
-                "core_0_current_6",
-                &format_args!("{}", self.core_0_current_6().bit()),
-            )
+            .field("core_0_from_world_6", &self.core_0_from_world_6())
+            .field("core_0_from_entry_6", &self.core_0_from_entry_6())
+            .field("core_0_current_6", &self.core_0_current_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_STATUSTABLE6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 6"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_statustable7.rs b/esp32s3/src/wcl/core_0_statustable7.rs
index 0f50a99760..3f4c3c5d20 100644
--- a/esp32s3/src/wcl/core_0_statustable7.rs
+++ b/esp32s3/src/wcl/core_0_statustable7.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_STATUSTABLE7")
-            .field(
-                "core_0_from_world_7",
-                &format_args!("{}", self.core_0_from_world_7().bit()),
-            )
-            .field(
-                "core_0_from_entry_7",
-                &format_args!("{}", self.core_0_from_entry_7().bits()),
-            )
-            .field(
-                "core_0_current_7",
-                &format_args!("{}", self.core_0_current_7().bit()),
-            )
+            .field("core_0_from_world_7", &self.core_0_from_world_7())
+            .field("core_0_from_entry_7", &self.core_0_from_entry_7())
+            .field("core_0_current_7", &self.core_0_current_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_STATUSTABLE7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 7"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_statustable8.rs b/esp32s3/src/wcl/core_0_statustable8.rs
index 9300161291..070e895baa 100644
--- a/esp32s3/src/wcl/core_0_statustable8.rs
+++ b/esp32s3/src/wcl/core_0_statustable8.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_STATUSTABLE8")
-            .field(
-                "core_0_from_world_8",
-                &format_args!("{}", self.core_0_from_world_8().bit()),
-            )
-            .field(
-                "core_0_from_entry_8",
-                &format_args!("{}", self.core_0_from_entry_8().bits()),
-            )
-            .field(
-                "core_0_current_8",
-                &format_args!("{}", self.core_0_current_8().bit()),
-            )
+            .field("core_0_from_world_8", &self.core_0_from_world_8())
+            .field("core_0_from_entry_8", &self.core_0_from_entry_8())
+            .field("core_0_current_8", &self.core_0_current_8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_STATUSTABLE8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 8"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_statustable9.rs b/esp32s3/src/wcl/core_0_statustable9.rs
index 5c314db352..e7f23bf8a5 100644
--- a/esp32s3/src/wcl/core_0_statustable9.rs
+++ b/esp32s3/src/wcl/core_0_statustable9.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_STATUSTABLE9")
-            .field(
-                "core_0_from_world_9",
-                &format_args!("{}", self.core_0_from_world_9().bit()),
-            )
-            .field(
-                "core_0_from_entry_9",
-                &format_args!("{}", self.core_0_from_entry_9().bits()),
-            )
-            .field(
-                "core_0_current_9",
-                &format_args!("{}", self.core_0_current_9().bit()),
-            )
+            .field("core_0_from_world_9", &self.core_0_from_world_9())
+            .field("core_0_from_entry_9", &self.core_0_from_entry_9())
+            .field("core_0_current_9", &self.core_0_current_9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_STATUSTABLE9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 9"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_statustable_current.rs b/esp32s3/src/wcl/core_0_statustable_current.rs
index 489d2c6beb..e8a53d8793 100644
--- a/esp32s3/src/wcl/core_0_statustable_current.rs
+++ b/esp32s3/src/wcl/core_0_statustable_current.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("Core_0_STATUSTABLE_CURRENT")
             .field(
                 "core_0_statustable_current",
-                &format_args!("{}", self.core_0_statustable_current().bits()),
+                &self.core_0_statustable_current(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_STATUSTABLE_CURRENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 1:13 - This field is used to quickly read and rewrite the current field of all STATUSTABLE registers,for example,bit 1 represents the current field of STATUSTABLE1,bit2 represents the current field of STATUSTABLE2"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_world_dram0_pif.rs b/esp32s3/src/wcl/core_0_world_dram0_pif.rs
index 059ba09354..cf3bac0d0e 100644
--- a/esp32s3/src/wcl/core_0_world_dram0_pif.rs
+++ b/esp32s3/src/wcl/core_0_world_dram0_pif.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_World_DRam0_PIF")
-            .field(
-                "core_0_world_dram0_pif",
-                &format_args!("{}", self.core_0_world_dram0_pif().bits()),
-            )
+            .field("core_0_world_dram0_pif", &self.core_0_world_dram0_pif())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_WORLD_DRAM0_PIF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - this field is used to read current world of Dram0 bus and PIF bus"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_world_iram0.rs b/esp32s3/src/wcl/core_0_world_iram0.rs
index 6cef2cdd94..8ae576519e 100644
--- a/esp32s3/src/wcl/core_0_world_iram0.rs
+++ b/esp32s3/src/wcl/core_0_world_iram0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_World_IRam0")
-            .field(
-                "core_0_world_iram0",
-                &format_args!("{}", self.core_0_world_iram0().bits()),
-            )
+            .field("core_0_world_iram0", &self.core_0_world_iram0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_WORLD_IRAM0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - this field is used to read current world of Iram0 bus"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_world_phase.rs b/esp32s3/src/wcl/core_0_world_phase.rs
index d29bc66c36..320f0af7fa 100644
--- a/esp32s3/src/wcl/core_0_world_phase.rs
+++ b/esp32s3/src/wcl/core_0_world_phase.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_World_Phase")
-            .field(
-                "core_0_world_phase",
-                &format_args!("{}", self.core_0_world_phase().bit()),
-            )
+            .field("core_0_world_phase", &self.core_0_world_phase())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_WORLD_PHASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core_0 world status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_0_world_phase::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_0_WORLD_PHASE_SPEC;
 impl crate::RegisterSpec for CORE_0_WORLD_PHASE_SPEC {
diff --git a/esp32s3/src/wcl/core_0_world_prepare.rs b/esp32s3/src/wcl/core_0_world_prepare.rs
index 7b020ac572..1ca44f6bc6 100644
--- a/esp32s3/src/wcl/core_0_world_prepare.rs
+++ b/esp32s3/src/wcl/core_0_world_prepare.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_0_World_PREPARE")
-            .field(
-                "core_0_world_prepare",
-                &format_args!("{}", self.core_0_world_prepare().bits()),
-            )
+            .field("core_0_world_prepare", &self.core_0_world_prepare())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_WORLD_PREPARE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field to used to set world to enter, 2'b01 means WORLD0, 2'b10 means WORLD1"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_0_world_trigger_addr.rs b/esp32s3/src/wcl/core_0_world_trigger_addr.rs
index 7a78548b2d..69fc9ca4be 100644
--- a/esp32s3/src/wcl/core_0_world_trigger_addr.rs
+++ b/esp32s3/src/wcl/core_0_world_trigger_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("Core_0_World_TRIGGER_ADDR")
             .field(
                 "core_0_world_trigger_addr",
-                &format_args!("{}", self.core_0_world_trigger_addr().bits()),
+                &self.core_0_world_trigger_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_0_WORLD_TRIGGER_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This field is used to configure the entry address from WORLD0 to WORLD1,when the CPU executes to this address,switch to WORLD1"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_entry_10_addr.rs b/esp32s3/src/wcl/core_1_entry_10_addr.rs
index de73ef39fd..0b9aa78961 100644
--- a/esp32s3/src/wcl/core_1_entry_10_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_10_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_ENTRY_10_ADDR")
-            .field(
-                "core_1_entry_10_addr",
-                &format_args!("{}", self.core_1_entry_10_addr().bits()),
-            )
+            .field("core_1_entry_10_addr", &self.core_1_entry_10_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_ENTRY_10_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 10 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_entry_11_addr.rs b/esp32s3/src/wcl/core_1_entry_11_addr.rs
index abd0b1fb61..3852d19ff6 100644
--- a/esp32s3/src/wcl/core_1_entry_11_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_11_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_ENTRY_11_ADDR")
-            .field(
-                "core_1_entry_11_addr",
-                &format_args!("{}", self.core_1_entry_11_addr().bits()),
-            )
+            .field("core_1_entry_11_addr", &self.core_1_entry_11_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_ENTRY_11_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 11 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_entry_12_addr.rs b/esp32s3/src/wcl/core_1_entry_12_addr.rs
index 6108538685..3e10c15202 100644
--- a/esp32s3/src/wcl/core_1_entry_12_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_12_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_ENTRY_12_ADDR")
-            .field(
-                "core_1_entry_12_addr",
-                &format_args!("{}", self.core_1_entry_12_addr().bits()),
-            )
+            .field("core_1_entry_12_addr", &self.core_1_entry_12_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_ENTRY_12_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 12 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_entry_13_addr.rs b/esp32s3/src/wcl/core_1_entry_13_addr.rs
index 5295f24cd3..92828c5c4e 100644
--- a/esp32s3/src/wcl/core_1_entry_13_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_13_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_ENTRY_13_ADDR")
-            .field(
-                "core_1_entry_13_addr",
-                &format_args!("{}", self.core_1_entry_13_addr().bits()),
-            )
+            .field("core_1_entry_13_addr", &self.core_1_entry_13_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_ENTRY_13_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 13 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_entry_1_addr.rs b/esp32s3/src/wcl/core_1_entry_1_addr.rs
index 8fb71a2aae..46405d9138 100644
--- a/esp32s3/src/wcl/core_1_entry_1_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_1_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_ENTRY_1_ADDR")
-            .field(
-                "core_1_entry_1_addr",
-                &format_args!("{}", self.core_1_entry_1_addr().bits()),
-            )
+            .field("core_1_entry_1_addr", &self.core_1_entry_1_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_ENTRY_1_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 1 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_entry_2_addr.rs b/esp32s3/src/wcl/core_1_entry_2_addr.rs
index c23b14939c..e0e6b89e7c 100644
--- a/esp32s3/src/wcl/core_1_entry_2_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_2_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_ENTRY_2_ADDR")
-            .field(
-                "core_1_entry_2_addr",
-                &format_args!("{}", self.core_1_entry_2_addr().bits()),
-            )
+            .field("core_1_entry_2_addr", &self.core_1_entry_2_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_ENTRY_2_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 2 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_entry_3_addr.rs b/esp32s3/src/wcl/core_1_entry_3_addr.rs
index 115150cf30..ee11618dfa 100644
--- a/esp32s3/src/wcl/core_1_entry_3_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_3_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_ENTRY_3_ADDR")
-            .field(
-                "core_1_entry_3_addr",
-                &format_args!("{}", self.core_1_entry_3_addr().bits()),
-            )
+            .field("core_1_entry_3_addr", &self.core_1_entry_3_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_ENTRY_3_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 3 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_entry_4_addr.rs b/esp32s3/src/wcl/core_1_entry_4_addr.rs
index 6dd614b913..e008432ec0 100644
--- a/esp32s3/src/wcl/core_1_entry_4_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_4_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_ENTRY_4_ADDR")
-            .field(
-                "core_1_entry_4_addr",
-                &format_args!("{}", self.core_1_entry_4_addr().bits()),
-            )
+            .field("core_1_entry_4_addr", &self.core_1_entry_4_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_ENTRY_4_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 4 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_entry_5_addr.rs b/esp32s3/src/wcl/core_1_entry_5_addr.rs
index 767d9d86c1..f14c0ea651 100644
--- a/esp32s3/src/wcl/core_1_entry_5_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_5_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_ENTRY_5_ADDR")
-            .field(
-                "core_1_entry_5_addr",
-                &format_args!("{}", self.core_1_entry_5_addr().bits()),
-            )
+            .field("core_1_entry_5_addr", &self.core_1_entry_5_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_ENTRY_5_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 5 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_entry_6_addr.rs b/esp32s3/src/wcl/core_1_entry_6_addr.rs
index 663bb9f1cd..fc934710d1 100644
--- a/esp32s3/src/wcl/core_1_entry_6_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_6_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_ENTRY_6_ADDR")
-            .field(
-                "core_1_entry_6_addr",
-                &format_args!("{}", self.core_1_entry_6_addr().bits()),
-            )
+            .field("core_1_entry_6_addr", &self.core_1_entry_6_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_ENTRY_6_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 6 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_entry_7_addr.rs b/esp32s3/src/wcl/core_1_entry_7_addr.rs
index 34a55f307b..ef25793f2d 100644
--- a/esp32s3/src/wcl/core_1_entry_7_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_7_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_ENTRY_7_ADDR")
-            .field(
-                "core_1_entry_7_addr",
-                &format_args!("{}", self.core_1_entry_7_addr().bits()),
-            )
+            .field("core_1_entry_7_addr", &self.core_1_entry_7_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_ENTRY_7_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 7 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_entry_8_addr.rs b/esp32s3/src/wcl/core_1_entry_8_addr.rs
index 2eee48a835..a7b1700b06 100644
--- a/esp32s3/src/wcl/core_1_entry_8_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_8_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_ENTRY_8_ADDR")
-            .field(
-                "core_1_entry_8_addr",
-                &format_args!("{}", self.core_1_entry_8_addr().bits()),
-            )
+            .field("core_1_entry_8_addr", &self.core_1_entry_8_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_ENTRY_8_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 8 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_entry_9_addr.rs b/esp32s3/src/wcl/core_1_entry_9_addr.rs
index da99c9a34b..93efb7906c 100644
--- a/esp32s3/src/wcl/core_1_entry_9_addr.rs
+++ b/esp32s3/src/wcl/core_1_entry_9_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_ENTRY_9_ADDR")
-            .field(
-                "core_1_entry_9_addr",
-                &format_args!("{}", self.core_1_entry_9_addr().bits()),
-            )
+            .field("core_1_entry_9_addr", &self.core_1_entry_9_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_ENTRY_9_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Core_1 Entry 9 address from WORLD1 to WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_entry_check.rs b/esp32s3/src/wcl/core_1_entry_check.rs
index 45d30bb346..8d8c1c125f 100644
--- a/esp32s3/src/wcl/core_1_entry_check.rs
+++ b/esp32s3/src/wcl/core_1_entry_check.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_ENTRY_CHECK")
-            .field(
-                "core_1_entry_check",
-                &format_args!("{}", self.core_1_entry_check().bits()),
-            )
+            .field("core_1_entry_check", &self.core_1_entry_check())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_ENTRY_CHECK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 1:13 - This filed is used to enable entry address check"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_message_addr.rs b/esp32s3/src/wcl/core_1_message_addr.rs
index dc9c6be7b4..32dd83a228 100644
--- a/esp32s3/src/wcl/core_1_message_addr.rs
+++ b/esp32s3/src/wcl/core_1_message_addr.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_MESSAGE_ADDR")
-            .field(
-                "core_1_message_addr",
-                &format_args!("{}", self.core_1_message_addr().bits()),
-            )
+            .field("core_1_message_addr", &self.core_1_message_addr())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_MESSAGE_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This field is used to set address that need to write when enter WORLD0"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_message_max.rs b/esp32s3/src/wcl/core_1_message_max.rs
index c56653d4cd..25c92823fb 100644
--- a/esp32s3/src/wcl/core_1_message_max.rs
+++ b/esp32s3/src/wcl/core_1_message_max.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_MESSAGE_MAX")
-            .field(
-                "core_1_message_max",
-                &format_args!("{}", self.core_1_message_max().bits()),
-            )
+            .field("core_1_message_max", &self.core_1_message_max())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_MESSAGE_MAX_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:3 - This filed is used to set the max value of clear write_buffer"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_message_phase.rs b/esp32s3/src/wcl/core_1_message_phase.rs
index 783f3e5a7b..671ab348f7 100644
--- a/esp32s3/src/wcl/core_1_message_phase.rs
+++ b/esp32s3/src/wcl/core_1_message_phase.rs
@@ -34,31 +34,16 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_MESSAGE_PHASE")
-            .field(
-                "core_1_message_match",
-                &format_args!("{}", self.core_1_message_match().bit()),
-            )
-            .field(
-                "core_1_message_expect",
-                &format_args!("{}", self.core_1_message_expect().bits()),
-            )
-            .field(
-                "core_1_message_dataphase",
-                &format_args!("{}", self.core_1_message_dataphase().bit()),
-            )
+            .field("core_1_message_match", &self.core_1_message_match())
+            .field("core_1_message_expect", &self.core_1_message_expect())
+            .field("core_1_message_dataphase", &self.core_1_message_dataphase())
             .field(
                 "core_1_message_addressphase",
-                &format_args!("{}", self.core_1_message_addressphase().bit()),
+                &self.core_1_message_addressphase(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_MESSAGE_PHASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Clear writer_buffer status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_message_phase::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_MESSAGE_PHASE_SPEC;
 impl crate::RegisterSpec for CORE_1_MESSAGE_PHASE_SPEC {
diff --git a/esp32s3/src/wcl/core_1_nmi_mask.rs b/esp32s3/src/wcl/core_1_nmi_mask.rs
index 6c68a11245..9063af7e77 100644
--- a/esp32s3/src/wcl/core_1_nmi_mask.rs
+++ b/esp32s3/src/wcl/core_1_nmi_mask.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_NMI_MASK")
-            .field(
-                "core_1_nmi_mask",
-                &format_args!("{}", self.core_1_nmi_mask().bit()),
-            )
+            .field("core_1_nmi_mask", &self.core_1_nmi_mask())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_NMI_MASK_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - this bit is used to mask NMI interrupt,it can directly mask NMI interrupt"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_nmi_mask_phase.rs b/esp32s3/src/wcl/core_1_nmi_mask_phase.rs
index bc92bbbf0c..c1c65db904 100644
--- a/esp32s3/src/wcl/core_1_nmi_mask_phase.rs
+++ b/esp32s3/src/wcl/core_1_nmi_mask_phase.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_NMI_MASK_PHASE")
-            .field(
-                "core_1_nmi_mask_phase",
-                &format_args!("{}", self.core_1_nmi_mask_phase().bit()),
-            )
+            .field("core_1_nmi_mask_phase", &self.core_1_nmi_mask_phase())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_NMI_MASK_PHASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core_1 NMI mask phase register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_nmi_mask_phase::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_NMI_MASK_PHASE_SPEC;
 impl crate::RegisterSpec for CORE_1_NMI_MASK_PHASE_SPEC {
diff --git a/esp32s3/src/wcl/core_1_nmi_mask_trigger_addr.rs b/esp32s3/src/wcl/core_1_nmi_mask_trigger_addr.rs
index 2611803d44..e8d9462760 100644
--- a/esp32s3/src/wcl/core_1_nmi_mask_trigger_addr.rs
+++ b/esp32s3/src/wcl/core_1_nmi_mask_trigger_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("Core_1_NMI_MASK_TRIGGER_ADDR")
             .field(
                 "core_1_nmi_mask_trigger_addr",
-                &format_args!("{}", self.core_1_nmi_mask_trigger_addr().bits()),
+                &self.core_1_nmi_mask_trigger_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_NMI_MASK_TRIGGER_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - this field to used to set trigger address"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_statustable1.rs b/esp32s3/src/wcl/core_1_statustable1.rs
index 9c80b62e42..8b44e34d22 100644
--- a/esp32s3/src/wcl/core_1_statustable1.rs
+++ b/esp32s3/src/wcl/core_1_statustable1.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_STATUSTABLE1")
-            .field(
-                "core_1_from_world_1",
-                &format_args!("{}", self.core_1_from_world_1().bit()),
-            )
-            .field(
-                "core_1_from_entry_1",
-                &format_args!("{}", self.core_1_from_entry_1().bits()),
-            )
-            .field(
-                "core_1_current_1",
-                &format_args!("{}", self.core_1_current_1().bit()),
-            )
+            .field("core_1_from_world_1", &self.core_1_from_world_1())
+            .field("core_1_from_entry_1", &self.core_1_from_entry_1())
+            .field("core_1_current_1", &self.core_1_current_1())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_STATUSTABLE1_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 1"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_statustable10.rs b/esp32s3/src/wcl/core_1_statustable10.rs
index a96e50a371..96ec6cb197 100644
--- a/esp32s3/src/wcl/core_1_statustable10.rs
+++ b/esp32s3/src/wcl/core_1_statustable10.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_STATUSTABLE10")
-            .field(
-                "core_1_from_world_10",
-                &format_args!("{}", self.core_1_from_world_10().bit()),
-            )
-            .field(
-                "core_1_from_entry_10",
-                &format_args!("{}", self.core_1_from_entry_10().bits()),
-            )
-            .field(
-                "core_1_current_10",
-                &format_args!("{}", self.core_1_current_10().bit()),
-            )
+            .field("core_1_from_world_10", &self.core_1_from_world_10())
+            .field("core_1_from_entry_10", &self.core_1_from_entry_10())
+            .field("core_1_current_10", &self.core_1_current_10())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_STATUSTABLE10_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 10"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_statustable11.rs b/esp32s3/src/wcl/core_1_statustable11.rs
index 9c9049f98b..a4f4eca2c8 100644
--- a/esp32s3/src/wcl/core_1_statustable11.rs
+++ b/esp32s3/src/wcl/core_1_statustable11.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_STATUSTABLE11")
-            .field(
-                "core_1_from_world_11",
-                &format_args!("{}", self.core_1_from_world_11().bit()),
-            )
-            .field(
-                "core_1_from_entry_11",
-                &format_args!("{}", self.core_1_from_entry_11().bits()),
-            )
-            .field(
-                "core_1_current_11",
-                &format_args!("{}", self.core_1_current_11().bit()),
-            )
+            .field("core_1_from_world_11", &self.core_1_from_world_11())
+            .field("core_1_from_entry_11", &self.core_1_from_entry_11())
+            .field("core_1_current_11", &self.core_1_current_11())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_STATUSTABLE11_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 11"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_statustable12.rs b/esp32s3/src/wcl/core_1_statustable12.rs
index 0ebe5e51cf..3bc3d1c902 100644
--- a/esp32s3/src/wcl/core_1_statustable12.rs
+++ b/esp32s3/src/wcl/core_1_statustable12.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_STATUSTABLE12")
-            .field(
-                "core_1_from_world_12",
-                &format_args!("{}", self.core_1_from_world_12().bit()),
-            )
-            .field(
-                "core_1_from_entry_12",
-                &format_args!("{}", self.core_1_from_entry_12().bits()),
-            )
-            .field(
-                "core_1_current_12",
-                &format_args!("{}", self.core_1_current_12().bit()),
-            )
+            .field("core_1_from_world_12", &self.core_1_from_world_12())
+            .field("core_1_from_entry_12", &self.core_1_from_entry_12())
+            .field("core_1_current_12", &self.core_1_current_12())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_STATUSTABLE12_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 12"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_statustable13.rs b/esp32s3/src/wcl/core_1_statustable13.rs
index 96fa09898f..1b9f0555ce 100644
--- a/esp32s3/src/wcl/core_1_statustable13.rs
+++ b/esp32s3/src/wcl/core_1_statustable13.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_STATUSTABLE13")
-            .field(
-                "core_1_from_world_13",
-                &format_args!("{}", self.core_1_from_world_13().bit()),
-            )
-            .field(
-                "core_1_from_entry_13",
-                &format_args!("{}", self.core_1_from_entry_13().bits()),
-            )
-            .field(
-                "core_1_current_13",
-                &format_args!("{}", self.core_1_current_13().bit()),
-            )
+            .field("core_1_from_world_13", &self.core_1_from_world_13())
+            .field("core_1_from_entry_13", &self.core_1_from_entry_13())
+            .field("core_1_current_13", &self.core_1_current_13())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_STATUSTABLE13_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 13"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_statustable2.rs b/esp32s3/src/wcl/core_1_statustable2.rs
index 6d60c5ad24..3ba6bd7c1d 100644
--- a/esp32s3/src/wcl/core_1_statustable2.rs
+++ b/esp32s3/src/wcl/core_1_statustable2.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_STATUSTABLE2")
-            .field(
-                "core_1_from_world_2",
-                &format_args!("{}", self.core_1_from_world_2().bit()),
-            )
-            .field(
-                "core_1_from_entry_2",
-                &format_args!("{}", self.core_1_from_entry_2().bits()),
-            )
-            .field(
-                "core_1_current_2",
-                &format_args!("{}", self.core_1_current_2().bit()),
-            )
+            .field("core_1_from_world_2", &self.core_1_from_world_2())
+            .field("core_1_from_entry_2", &self.core_1_from_entry_2())
+            .field("core_1_current_2", &self.core_1_current_2())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_STATUSTABLE2_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 2"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_statustable3.rs b/esp32s3/src/wcl/core_1_statustable3.rs
index 49f1aa3624..f281c763c7 100644
--- a/esp32s3/src/wcl/core_1_statustable3.rs
+++ b/esp32s3/src/wcl/core_1_statustable3.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_STATUSTABLE3")
-            .field(
-                "core_1_from_world_3",
-                &format_args!("{}", self.core_1_from_world_3().bit()),
-            )
-            .field(
-                "core_1_from_entry_3",
-                &format_args!("{}", self.core_1_from_entry_3().bits()),
-            )
-            .field(
-                "core_1_current_3",
-                &format_args!("{}", self.core_1_current_3().bit()),
-            )
+            .field("core_1_from_world_3", &self.core_1_from_world_3())
+            .field("core_1_from_entry_3", &self.core_1_from_entry_3())
+            .field("core_1_current_3", &self.core_1_current_3())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_STATUSTABLE3_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 3"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_statustable4.rs b/esp32s3/src/wcl/core_1_statustable4.rs
index da7d5aeb94..ccf51474c5 100644
--- a/esp32s3/src/wcl/core_1_statustable4.rs
+++ b/esp32s3/src/wcl/core_1_statustable4.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_STATUSTABLE4")
-            .field(
-                "core_1_from_world_4",
-                &format_args!("{}", self.core_1_from_world_4().bit()),
-            )
-            .field(
-                "core_1_from_entry_4",
-                &format_args!("{}", self.core_1_from_entry_4().bits()),
-            )
-            .field(
-                "core_1_current_4",
-                &format_args!("{}", self.core_1_current_4().bit()),
-            )
+            .field("core_1_from_world_4", &self.core_1_from_world_4())
+            .field("core_1_from_entry_4", &self.core_1_from_entry_4())
+            .field("core_1_current_4", &self.core_1_current_4())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_STATUSTABLE4_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 4"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_statustable5.rs b/esp32s3/src/wcl/core_1_statustable5.rs
index 49549e2343..d7d48b9134 100644
--- a/esp32s3/src/wcl/core_1_statustable5.rs
+++ b/esp32s3/src/wcl/core_1_statustable5.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_STATUSTABLE5")
-            .field(
-                "core_1_from_world_5",
-                &format_args!("{}", self.core_1_from_world_5().bit()),
-            )
-            .field(
-                "core_1_from_entry_5",
-                &format_args!("{}", self.core_1_from_entry_5().bits()),
-            )
-            .field(
-                "core_1_current_5",
-                &format_args!("{}", self.core_1_current_5().bit()),
-            )
+            .field("core_1_from_world_5", &self.core_1_from_world_5())
+            .field("core_1_from_entry_5", &self.core_1_from_entry_5())
+            .field("core_1_current_5", &self.core_1_current_5())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_STATUSTABLE5_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 5"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_statustable6.rs b/esp32s3/src/wcl/core_1_statustable6.rs
index 6bb461b5a3..1dc0f193d8 100644
--- a/esp32s3/src/wcl/core_1_statustable6.rs
+++ b/esp32s3/src/wcl/core_1_statustable6.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_STATUSTABLE6")
-            .field(
-                "core_1_from_world_6",
-                &format_args!("{}", self.core_1_from_world_6().bit()),
-            )
-            .field(
-                "core_1_from_entry_6",
-                &format_args!("{}", self.core_1_from_entry_6().bits()),
-            )
-            .field(
-                "core_1_current_6",
-                &format_args!("{}", self.core_1_current_6().bit()),
-            )
+            .field("core_1_from_world_6", &self.core_1_from_world_6())
+            .field("core_1_from_entry_6", &self.core_1_from_entry_6())
+            .field("core_1_current_6", &self.core_1_current_6())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_STATUSTABLE6_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 6"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_statustable7.rs b/esp32s3/src/wcl/core_1_statustable7.rs
index 899459c127..ad2b3d51fb 100644
--- a/esp32s3/src/wcl/core_1_statustable7.rs
+++ b/esp32s3/src/wcl/core_1_statustable7.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_STATUSTABLE7")
-            .field(
-                "core_1_from_world_7",
-                &format_args!("{}", self.core_1_from_world_7().bit()),
-            )
-            .field(
-                "core_1_from_entry_7",
-                &format_args!("{}", self.core_1_from_entry_7().bits()),
-            )
-            .field(
-                "core_1_current_7",
-                &format_args!("{}", self.core_1_current_7().bit()),
-            )
+            .field("core_1_from_world_7", &self.core_1_from_world_7())
+            .field("core_1_from_entry_7", &self.core_1_from_entry_7())
+            .field("core_1_current_7", &self.core_1_current_7())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_STATUSTABLE7_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 7"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_statustable8.rs b/esp32s3/src/wcl/core_1_statustable8.rs
index b24dd70a69..fe9ac2b45a 100644
--- a/esp32s3/src/wcl/core_1_statustable8.rs
+++ b/esp32s3/src/wcl/core_1_statustable8.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_STATUSTABLE8")
-            .field(
-                "core_1_from_world_8",
-                &format_args!("{}", self.core_1_from_world_8().bit()),
-            )
-            .field(
-                "core_1_from_entry_8",
-                &format_args!("{}", self.core_1_from_entry_8().bits()),
-            )
-            .field(
-                "core_1_current_8",
-                &format_args!("{}", self.core_1_current_8().bit()),
-            )
+            .field("core_1_from_world_8", &self.core_1_from_world_8())
+            .field("core_1_from_entry_8", &self.core_1_from_entry_8())
+            .field("core_1_current_8", &self.core_1_current_8())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_STATUSTABLE8_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 8"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_statustable9.rs b/esp32s3/src/wcl/core_1_statustable9.rs
index e49a2df682..cce23c8e8f 100644
--- a/esp32s3/src/wcl/core_1_statustable9.rs
+++ b/esp32s3/src/wcl/core_1_statustable9.rs
@@ -35,27 +35,12 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_STATUSTABLE9")
-            .field(
-                "core_1_from_world_9",
-                &format_args!("{}", self.core_1_from_world_9().bit()),
-            )
-            .field(
-                "core_1_from_entry_9",
-                &format_args!("{}", self.core_1_from_entry_9().bits()),
-            )
-            .field(
-                "core_1_current_9",
-                &format_args!("{}", self.core_1_current_9().bit()),
-            )
+            .field("core_1_from_world_9", &self.core_1_from_world_9())
+            .field("core_1_from_entry_9", &self.core_1_from_entry_9())
+            .field("core_1_current_9", &self.core_1_current_9())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_STATUSTABLE9_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - This bit is used to confirm world before enter entry 9"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_statustable_current.rs b/esp32s3/src/wcl/core_1_statustable_current.rs
index be5414c16d..1c7a9cc450 100644
--- a/esp32s3/src/wcl/core_1_statustable_current.rs
+++ b/esp32s3/src/wcl/core_1_statustable_current.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("Core_1_STATUSTABLE_CURRENT")
             .field(
                 "core_1_statustable_current",
-                &format_args!("{}", self.core_1_statustable_current().bits()),
+                &self.core_1_statustable_current(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_STATUSTABLE_CURRENT_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 1:13 - This field is used to quickly read and rewrite the current field of all STATUSTABLE registers,for example,bit 1 represents the current field of STATUSTABLE1"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_world_dram0_pif.rs b/esp32s3/src/wcl/core_1_world_dram0_pif.rs
index 038a7735d2..d6587326b4 100644
--- a/esp32s3/src/wcl/core_1_world_dram0_pif.rs
+++ b/esp32s3/src/wcl/core_1_world_dram0_pif.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_World_DRam0_PIF")
-            .field(
-                "core_1_world_dram0_pif",
-                &format_args!("{}", self.core_1_world_dram0_pif().bits()),
-            )
+            .field("core_1_world_dram0_pif", &self.core_1_world_dram0_pif())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_WORLD_DRAM0_PIF_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - this field is used to read current world of Dram0 bus and PIF bus"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_world_iram0.rs b/esp32s3/src/wcl/core_1_world_iram0.rs
index af8dbea591..5fbf6680ec 100644
--- a/esp32s3/src/wcl/core_1_world_iram0.rs
+++ b/esp32s3/src/wcl/core_1_world_iram0.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_World_IRam0")
-            .field(
-                "core_1_world_iram0",
-                &format_args!("{}", self.core_1_world_iram0().bits()),
-            )
+            .field("core_1_world_iram0", &self.core_1_world_iram0())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_WORLD_IRAM0_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - this field is used to read current world of Iram0 bus"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_world_phase.rs b/esp32s3/src/wcl/core_1_world_phase.rs
index 6e9e632de0..49f318da34 100644
--- a/esp32s3/src/wcl/core_1_world_phase.rs
+++ b/esp32s3/src/wcl/core_1_world_phase.rs
@@ -13,19 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_World_Phase")
-            .field(
-                "core_1_world_phase",
-                &format_args!("{}", self.core_1_world_phase().bit()),
-            )
+            .field("core_1_world_phase", &self.core_1_world_phase())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_WORLD_PHASE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "Core_0 world status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`core_1_world_phase::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CORE_1_WORLD_PHASE_SPEC;
 impl crate::RegisterSpec for CORE_1_WORLD_PHASE_SPEC {
diff --git a/esp32s3/src/wcl/core_1_world_prepare.rs b/esp32s3/src/wcl/core_1_world_prepare.rs
index 00ec6ef14e..a41882adb1 100644
--- a/esp32s3/src/wcl/core_1_world_prepare.rs
+++ b/esp32s3/src/wcl/core_1_world_prepare.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("Core_1_World_PREPARE")
-            .field(
-                "core_1_world_prepare",
-                &format_args!("{}", self.core_1_world_prepare().bits()),
-            )
+            .field("core_1_world_prepare", &self.core_1_world_prepare())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_WORLD_PREPARE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:1 - This field to used to set world to enter,2'b01 means WORLD0, 2'b10 means WORLD1"]
     #[inline(always)]
diff --git a/esp32s3/src/wcl/core_1_world_trigger_addr.rs b/esp32s3/src/wcl/core_1_world_trigger_addr.rs
index 033874529e..9d75f66adf 100644
--- a/esp32s3/src/wcl/core_1_world_trigger_addr.rs
+++ b/esp32s3/src/wcl/core_1_world_trigger_addr.rs
@@ -19,17 +19,11 @@ impl core::fmt::Debug for R {
         f.debug_struct("Core_1_World_TRIGGER_ADDR")
             .field(
                 "core_1_world_trigger_addr",
-                &format_args!("{}", self.core_1_world_trigger_addr().bits()),
+                &self.core_1_world_trigger_addr(),
             )
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<CORE_1_WORLD_TRIGGER_ADDR_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - This field is used to configure the entry address from WORLD0 to WORLD1,when the CPU executes to this address,switch to WORLD1"]
     #[inline(always)]
diff --git a/esp32s3/src/xts_aes/date.rs b/esp32s3/src/xts_aes/date.rs
index 18f5a54a74..3854dbc2ee 100644
--- a/esp32s3/src/xts_aes/date.rs
+++ b/esp32s3/src/xts_aes/date.rs
@@ -16,15 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("DATE")
-            .field("date", &format_args!("{}", self.date().bits()))
-            .finish()
-    }
-}
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
+        f.debug_struct("DATE").field("date", &self.date()).finish()
     }
 }
 impl W {
diff --git a/esp32s3/src/xts_aes/destination.rs b/esp32s3/src/xts_aes/destination.rs
index a0188ffb43..cf2fb31e65 100644
--- a/esp32s3/src/xts_aes/destination.rs
+++ b/esp32s3/src/xts_aes/destination.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("DESTINATION")
-            .field("destination", &format_args!("{}", self.destination().bit()))
+            .field("destination", &self.destination())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<DESTINATION_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occurs if users write 1. 0:flash. 1: external RAM."]
     #[inline(always)]
diff --git a/esp32s3/src/xts_aes/linesize.rs b/esp32s3/src/xts_aes/linesize.rs
index 742457c06e..c91bf34bf2 100644
--- a/esp32s3/src/xts_aes/linesize.rs
+++ b/esp32s3/src/xts_aes/linesize.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("LINESIZE")
-            .field("linesize", &format_args!("{}", self.linesize().bit()))
+            .field("linesize", &self.linesize())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<LINESIZE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bit 0 - Configures the data size of one encryption."]
     #[inline(always)]
diff --git a/esp32s3/src/xts_aes/physical_address.rs b/esp32s3/src/xts_aes/physical_address.rs
index 1988d0c35d..2901a4ff49 100644
--- a/esp32s3/src/xts_aes/physical_address.rs
+++ b/esp32s3/src/xts_aes/physical_address.rs
@@ -17,19 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PHYSICAL_ADDRESS")
-            .field(
-                "physical_address",
-                &format_args!("{}", self.physical_address().bits()),
-            )
+            .field("physical_address", &self.physical_address())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PHYSICAL_ADDRESS_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:29 - Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes. If linesize is 64-byte, the physical address should be aligned of 64 bytes."]
     #[inline(always)]
diff --git a/esp32s3/src/xts_aes/plain_.rs b/esp32s3/src/xts_aes/plain_.rs
index 69cff01b3c..15a2c22d87 100644
--- a/esp32s3/src/xts_aes/plain_.rs
+++ b/esp32s3/src/xts_aes/plain_.rs
@@ -17,16 +17,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("PLAIN_")
-            .field("plain", &format_args!("{}", self.plain().bits()))
+            .field("plain", &self.plain())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<PLAIN__SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 impl W {
     #[doc = "Bits 0:31 - Stores the nth 32-bit piece of plaintext."]
     #[inline(always)]
diff --git a/esp32s3/src/xts_aes/state.rs b/esp32s3/src/xts_aes/state.rs
index 26188c3f81..fc84108bc6 100644
--- a/esp32s3/src/xts_aes/state.rs
+++ b/esp32s3/src/xts_aes/state.rs
@@ -13,16 +13,10 @@ impl R {
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("STATE")
-            .field("state", &format_args!("{}", self.state().bits()))
+            .field("state", &self.state())
             .finish()
     }
 }
-#[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<STATE_SPEC> {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}
 #[doc = "XTS-AES status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
 impl crate::RegisterSpec for STATE_SPEC {
diff --git a/xtask/Cargo.lock b/xtask/Cargo.lock
index 4999e253bb..412bbd1003 100644
--- a/xtask/Cargo.lock
+++ b/xtask/Cargo.lock
@@ -13,47 +13,48 @@ dependencies = [
 
 [[package]]
 name = "anstream"
-version = "0.6.13"
+version = "0.6.14"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d96bd03f33fe50a863e394ee9718a706f988b9079b20c3784fb726e7678b62fb"
+checksum = "418c75fa768af9c03be99d17643f93f79bbba589895012a80e3452a19ddda15b"
 dependencies = [
  "anstyle",
  "anstyle-parse",
  "anstyle-query",
  "anstyle-wincon",
  "colorchoice",
+ "is_terminal_polyfill",
  "utf8parse",
 ]
 
 [[package]]
 name = "anstyle"
-version = "1.0.6"
+version = "1.0.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8901269c6307e8d93993578286ac0edf7f195079ffff5ebdeea6a59ffb7e36bc"
+checksum = "038dfcf04a5feb68e9c60b21c9625a54c2c0616e79b72b0fd87075a056ae1d1b"
 
 [[package]]
 name = "anstyle-parse"
-version = "0.2.3"
+version = "0.2.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c75ac65da39e5fe5ab759307499ddad880d724eed2f6ce5b5e8a26f4f387928c"
+checksum = "c03a11a9034d92058ceb6ee011ce58af4a9bf61491aa7e1e59ecd24bd40d22d4"
 dependencies = [
  "utf8parse",
 ]
 
 [[package]]
 name = "anstyle-query"
-version = "1.0.2"
+version = "1.0.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e28923312444cdd728e4738b3f9c9cac739500909bb3d3c94b43551b16517648"
+checksum = "a64c907d4e79225ac72e2a354c9ce84d50ebb4586dee56c82b3ee73004f537f5"
 dependencies = [
  "windows-sys",
 ]
 
 [[package]]
 name = "anstyle-wincon"
-version = "3.0.2"
+version = "3.0.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1cd54b81ec8d6180e24654d0b371ad22fc3dd083b6ff8ba325b72e00c87660a7"
+checksum = "61a38449feb7068f52bb06c12759005cf459ee52bb4adc1d5a7c4322d716fb19"
 dependencies = [
  "anstyle",
  "windows-sys",
@@ -61,9 +62,9 @@ dependencies = [
 
 [[package]]
 name = "anyhow"
-version = "1.0.81"
+version = "1.0.86"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0952808a6c2afd1aa8947271f3a60f1a6763c7b912d210184c5149b5cf147247"
+checksum = "b3d1d046238990b9cf5bcde22a3fb3584ee5cf65fb2765f454ed428c7a0063da"
 
 [[package]]
 name = "anymap2"
@@ -73,9 +74,9 @@ checksum = "d301b3b94cb4b2f23d7917810addbbaff90738e0ca2be692bd027e70d7e0330c"
 
 [[package]]
 name = "autocfg"
-version = "1.2.0"
+version = "1.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f1fdabc7756949593fe60f30ec81974b613357de856987752631dea1e3394c80"
+checksum = "0c4b4d0bd25bd0b74681c0ad21497610ce1b7c91b1022cd21c80c6fbdd9476b0"
 
 [[package]]
 name = "block-buffer"
@@ -133,7 +134,7 @@ dependencies = [
  "heck 0.5.0",
  "proc-macro2",
  "quote",
- "syn 2.0.58",
+ "syn",
 ]
 
 [[package]]
@@ -144,9 +145,9 @@ checksum = "98cc8fbded0c607b7ba9dd60cd98df59af97e84d24e49c8557331cfc26d301ce"
 
 [[package]]
 name = "colorchoice"
-version = "1.0.0"
+version = "1.0.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "acbf1af155f9b9ef647e42cdc158db4b64a1b61f743629225fde6f3e0be2a7c7"
+checksum = "0b6a852b24ab71dffc585bcb46eaf7959d175cb865a7152e35b348d1b2960422"
 
 [[package]]
 name = "commands"
@@ -193,9 +194,9 @@ dependencies = [
 
 [[package]]
 name = "crossbeam-utils"
-version = "0.8.19"
+version = "0.8.20"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "248e3bacc7dc6baa3b21e405ee045c3047101a49145e7e9eca583ab4c2ca5345"
+checksum = "22ec99545bb0ed0ea7bb9b8e1e9122ea386ff8a48c0922e43f36d45ab09e0e80"
 
 [[package]]
 name = "crypto-common"
@@ -234,9 +235,9 @@ checksum = "fea41bba32d969b513997752735605054bc0dfa92b4c56bf1189f2e174be7a10"
 
 [[package]]
 name = "either"
-version = "1.10.0"
+version = "1.12.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "11157ac094ffbdde99aa67b23417ebdd801842852b500e395a45a9c0aac03e4a"
+checksum = "3dca9240753cf90908d7e4aac30f630662b02aebaa1b58a3cadabdb23385b58b"
 
 [[package]]
 name = "env_filter"
@@ -282,17 +283,18 @@ checksum = "5443807d6dff69373d433ab9ef5378ad8df50ca6298caf15de6e52e24aaf54d5"
 
 [[package]]
 name = "form"
-version = "0.11.1"
+version = "0.12.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c6722a93a9407a430eda85fe2d0a1351136f69efd1aabf54a6c3c9ad2c1cd756"
+checksum = "93f9a8e6a78211e19eaec39d0ea551c23f85762d6dbe23f537f5c5f226e76402"
 dependencies = [
  "anyhow",
  "env_logger 0.10.2",
  "getopts",
  "log",
+ "prettyplease",
  "proc-macro2",
  "quote",
- "syn 1.0.109",
+ "syn",
 ]
 
 [[package]]
@@ -335,9 +337,9 @@ checksum = "8a9ee70c43aaf417c914396645a0fa852624801b24ebb7ae78fe8272889ac888"
 
 [[package]]
 name = "hashbrown"
-version = "0.14.3"
+version = "0.14.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "290f1a1d9242c78d09ce40a5e87e7554ee637af1351968159f4952f028f75604"
+checksum = "e5274423e17b7c9fc20b6e7e208532f9b19825d82dfd615708b70edd83df41f1"
 
 [[package]]
 name = "heck"
@@ -389,7 +391,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "168fb715dda47215e360912c096649d23d58bf392ac62f73919e831745e40f26"
 dependencies = [
  "equivalent",
- "hashbrown 0.14.3",
+ "hashbrown 0.14.5",
 ]
 
 [[package]]
@@ -409,6 +411,12 @@ dependencies = [
  "windows-sys",
 ]
 
+[[package]]
+name = "is_terminal_polyfill"
+version = "1.70.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f8478577c03552c21db0e2724ffb8986a5ce7af88107e6be5d2ee6e158c12800"
+
 [[package]]
 name = "itertools"
 version = "0.10.5"
@@ -445,9 +453,9 @@ dependencies = [
 
 [[package]]
 name = "libc"
-version = "0.2.153"
+version = "0.2.155"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9c198f91728a82281a64e1f4f9eeb25d82cb32a5de251c6bd1b5154d63a8e7bd"
+checksum = "97b3888a4aecf77e811145cadf6eef5901f4782c53886191b2f693f24761847c"
 
 [[package]]
 name = "linked-hash-map"
@@ -494,7 +502,7 @@ checksum = "fc2fb41a9bb4257a3803154bdf7e2df7d45197d1941c9b1a90ad815231630721"
 dependencies = [
  "proc-macro2",
  "quote",
- "syn 2.0.58",
+ "syn",
 ]
 
 [[package]]
@@ -541,9 +549,9 @@ checksum = "51d515d32fb182ee37cda2ccdcb92950d6a3c2893aa280e540671c2cd0f3b1d9"
 
 [[package]]
 name = "num-traits"
-version = "0.2.18"
+version = "0.2.19"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "da0df0e5185db44f69b44f26786fe401b6c293d1907744beaa7fa62b2e5a517a"
+checksum = "071dfc062690e90b734c0b2273ce72ad0ffa95f0c74596bc250dcfd960262841"
 dependencies = [
  "autocfg",
 ]
@@ -562,9 +570,9 @@ checksum = "e3148f5046208a5d56bcfc03053e3ca6334e51da8dfb19b6cdc8b306fae3283e"
 
 [[package]]
 name = "pest"
-version = "2.7.9"
+version = "2.7.10"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "311fb059dee1a7b802f036316d790138c613a4e8b180c822e3925a662e9f0c95"
+checksum = "560131c633294438da9f7c4b08189194b20946c8274c6b9e38881a7874dc8ee8"
 dependencies = [
  "memchr",
  "thiserror",
@@ -573,9 +581,9 @@ dependencies = [
 
 [[package]]
 name = "pest_derive"
-version = "2.7.9"
+version = "2.7.10"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f73541b156d32197eecda1a4014d7f868fd2bcb3c550d5386087cfba442bf69c"
+checksum = "26293c9193fbca7b1a3bf9b79dc1e388e927e6cacaa78b4a3ab705a1d3d41459"
 dependencies = [
  "pest",
  "pest_generator",
@@ -583,22 +591,22 @@ dependencies = [
 
 [[package]]
 name = "pest_generator"
-version = "2.7.9"
+version = "2.7.10"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c35eeed0a3fab112f75165fdc026b3913f4183133f19b49be773ac9ea966e8bd"
+checksum = "3ec22af7d3fb470a85dd2ca96b7c577a1eb4ef6f1683a9fe9a8c16e136c04687"
 dependencies = [
  "pest",
  "pest_meta",
  "proc-macro2",
  "quote",
- "syn 2.0.58",
+ "syn",
 ]
 
 [[package]]
 name = "pest_meta"
-version = "2.7.9"
+version = "2.7.10"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2adbf29bb9776f28caece835398781ab24435585fe0d4dc1374a61db5accedca"
+checksum = "d7a240022f37c361ec1878d646fc5b7d7c4d28d5946e1a80ad5a7a4f4ca0bdcd"
 dependencies = [
  "once_cell",
  "pest",
@@ -635,7 +643,7 @@ dependencies = [
  "phf_shared",
  "proc-macro2",
  "quote",
- "syn 2.0.58",
+ "syn",
 ]
 
 [[package]]
@@ -653,11 +661,21 @@ version = "0.2.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "439ee305def115ba05938db6eb1644ff94165c5ab5e9420d1c1bcedbba909391"
 
+[[package]]
+name = "prettyplease"
+version = "0.2.20"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5f12335488a2f3b0a83b14edad48dca9879ce89b2edd10e80237e4e852dd645e"
+dependencies = [
+ "proc-macro2",
+ "syn",
+]
+
 [[package]]
 name = "proc-macro2"
-version = "1.0.79"
+version = "1.0.84"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e835ff2298f5721608eb1a980ecaee1aef2c132bf95ecc026a11b7bf3c01c02e"
+checksum = "ec96c6a92621310b51366f1e28d05ef11489516e93be030060e5fc12024a49d6"
 dependencies = [
  "unicode-ident",
 ]
@@ -674,9 +692,9 @@ dependencies = [
 
 [[package]]
 name = "quote"
-version = "1.0.35"
+version = "1.0.36"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "291ec9ab5efd934aaf503a6466c5d5251535d108ee747472c3977cc5acc868ef"
+checksum = "0fa76aaf39101c457836aec0ce2316dbdc3ab723cdda1c6bd4e6ad4208acaca7"
 dependencies = [
  "proc-macro2",
 ]
@@ -753,47 +771,47 @@ checksum = "3cd14fd5e3b777a7422cca79358c57a8f6e3a703d9ac187448d0daf220c2407f"
 
 [[package]]
 name = "rustversion"
-version = "1.0.15"
+version = "1.0.17"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "80af6f9131f277a45a3fba6ce8e2258037bb0477a67e610d3c1fe046ab31de47"
+checksum = "955d28af4278de8121b7ebeb796b6a45735dc01436d898801014aced2773a3d6"
 
 [[package]]
 name = "ryu"
-version = "1.0.17"
+version = "1.0.18"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e86697c916019a8588c99b5fac3cead74ec0b4b819707a682fd4d23fa0ce1ba1"
+checksum = "f3cb5ba0dc43242ce17de99c180e96db90b235b8a9fdc9543c96d2209116bd9f"
 
 [[package]]
 name = "semver"
-version = "1.0.22"
+version = "1.0.23"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "92d43fe69e652f3df9bdc2b85b2854a0825b86e4fb76bc44d945137d053639ca"
+checksum = "61697e0a1c7e512e84a621326239844a24d8207b4669b41bc18b32ea5cbf988b"
 
 [[package]]
 name = "serde"
-version = "1.0.197"
+version = "1.0.203"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3fb1c873e1b9b056a4dc4c0c198b24c3ffa059243875552b2bd0933b1aee4ce2"
+checksum = "7253ab4de971e72fb7be983802300c30b5a7f0c2e56fab8abfc6a214307c0094"
 dependencies = [
  "serde_derive",
 ]
 
 [[package]]
 name = "serde_derive"
-version = "1.0.197"
+version = "1.0.203"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7eb0b34b42edc17f6b7cac84a52a1c5f0e1bb2227e997ca9011ea3dd34e8610b"
+checksum = "500cbc0ebeb6f46627f50f3f5811ccf6bf00643be300b4c3eabc0ef55dc5b5ba"
 dependencies = [
  "proc-macro2",
  "quote",
- "syn 2.0.58",
+ "syn",
 ]
 
 [[package]]
 name = "serde_json"
-version = "1.0.115"
+version = "1.0.117"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "12dc5c46daa8e9fdf4f5e71b6cf9a53f2487da0e86e55808e2d35539666497dd"
+checksum = "455182ea6142b14f93f4bc5320a2b31c1f266b66a4a5c858b013302a5d8cbfc3"
 dependencies = [
  "indexmap 2.2.6",
  "itoa",
@@ -861,7 +879,7 @@ dependencies = [
  "proc-macro2",
  "quote",
  "rustversion",
- "syn 2.0.58",
+ "syn",
 ]
 
 [[package]]
@@ -902,9 +920,9 @@ dependencies = [
 
 [[package]]
 name = "svd2rust"
-version = "0.33.0"
+version = "0.33.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "acf4421acea6bd4700755376c2dd57f4f9f9a92247dfa617a2c8df08730271b0"
+checksum = "e8dfe70c4081641a97bebb1ac7461d1ae271058dd75a90fbc575f0bfd0dea238"
 dependencies = [
  "anyhow",
  "html-escape",
@@ -915,7 +933,7 @@ dependencies = [
  "regex",
  "svd-parser",
  "svd-rs",
- "syn 2.0.58",
+ "syn",
  "thiserror",
 ]
 
@@ -952,20 +970,9 @@ dependencies = [
 
 [[package]]
 name = "syn"
-version = "1.0.109"
+version = "2.0.66"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "72b64191b275b66ffe2469e8af2c1cfe3bafa67b529ead792a6d0160888b4237"
-dependencies = [
- "proc-macro2",
- "quote",
- "unicode-ident",
-]
-
-[[package]]
-name = "syn"
-version = "2.0.58"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "44cfb93f38070beee36b3fef7d4f5a16f27751d94b187b666a5cc5e9b0d30687"
+checksum = "c42f3f41a2de00b01c0aaad383c5a45241efc8b2d1eda5661812fda5f3cdcff5"
 dependencies = [
  "proc-macro2",
  "quote",
@@ -983,29 +990,29 @@ dependencies = [
 
 [[package]]
 name = "thiserror"
-version = "1.0.58"
+version = "1.0.61"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "03468839009160513471e86a034bb2c5c0e4baae3b43f79ffc55c4a5427b3297"
+checksum = "c546c80d6be4bc6a00c0f01730c08df82eaa7a7a61f11d656526506112cc1709"
 dependencies = [
  "thiserror-impl",
 ]
 
 [[package]]
 name = "thiserror-impl"
-version = "1.0.58"
+version = "1.0.61"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c61f3ba182994efc43764a46c018c347bc492c79f024e705f46567b418f6d4f7"
+checksum = "46c3384250002a6d5af4d114f2845d37b57521033f30d5c3f46c4d70e1197533"
 dependencies = [
  "proc-macro2",
  "quote",
- "syn 2.0.58",
+ "syn",
 ]
 
 [[package]]
 name = "time"
-version = "0.3.34"
+version = "0.3.36"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c8248b6521bb14bc45b4067159b9b6ad792e2d6d754d6c41fb50e29fefe38749"
+checksum = "5dfd88e563464686c916c7e46e623e520ddc6d79fa6641390f2e3fa86e83e885"
 dependencies = [
  "deranged",
  "itoa",
@@ -1024,9 +1031,9 @@ checksum = "ef927ca75afb808a4d64dd374f00a2adf8d0fcff8e7b184af886c3c87ec4a3f3"
 
 [[package]]
 name = "time-macros"
-version = "0.2.17"
+version = "0.2.18"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7ba3a3ef41e6672a2f0f001392bb5dcd3ff0a9992d618ca761a11c3121547774"
+checksum = "3f252a68540fde3a3877aeea552b832b40ab9a69e318efd078774a01ddee1ccf"
 dependencies = [
  "num-conv",
  "time-core",
@@ -1034,15 +1041,15 @@ dependencies = [
 
 [[package]]
 name = "toml_datetime"
-version = "0.6.5"
+version = "0.6.6"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3550f4e9685620ac18a50ed434eb3aec30db8ba93b0287467bca5826ea25baf1"
+checksum = "4badfd56924ae69bcc9039335b2e017639ce3f9b001c393c1b2d1ef846ce2cbf"
 
 [[package]]
 name = "toml_edit"
-version = "0.22.9"
+version = "0.22.13"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8e40bb779c5187258fd7aad0eb68cb8706a0a81fa712fbea808ab43c4b8374c4"
+checksum = "c127785850e8c20836d49732ae6abfa47616e60bf9d9f57c43c250361a9db96c"
 dependencies = [
  "indexmap 2.2.6",
  "toml_datetime",
@@ -1075,9 +1082,9 @@ checksum = "d4c87d22b6e3f4a18d4d40ef354e97c90fcb14dd91d7dc0aa9d8a1172ebf7202"
 
 [[package]]
 name = "unicode-width"
-version = "0.1.11"
+version = "0.1.12"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e51733f11c9c4f72aa0c160008246859e340b00807569a0da0e7a1079b27ba85"
+checksum = "68f5e5f3158ecfd4b8ff6fe086db7c8467a2dfdac97fe420f2b7c4aa97af66d6"
 
 [[package]]
 name = "utf8-width"
@@ -1097,37 +1104,15 @@ version = "0.9.4"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "49874b5167b65d7193b8aba1567f5c7d93d001cafc34600cee003eda787e483f"
 
-[[package]]
-name = "winapi"
-version = "0.3.9"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5c839a674fcd7a98952e593242ea400abe93992746761e38641405d28b00f419"
-dependencies = [
- "winapi-i686-pc-windows-gnu",
- "winapi-x86_64-pc-windows-gnu",
-]
-
-[[package]]
-name = "winapi-i686-pc-windows-gnu"
-version = "0.4.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ac3b87c63620426dd9b991e5ce0329eff545bccbbb34f3be09ff6fb6ab51b7b6"
-
 [[package]]
 name = "winapi-util"
-version = "0.1.6"
+version = "0.1.8"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f29e6f9198ba0d26b4c9f07dbe6f9ed633e1f3d5b8b414090084349e46a52596"
+checksum = "4d4cc384e1e73b93bafa6fb4f1df8c41695c8a91cf9c4c64358067d15a7b6c6b"
 dependencies = [
- "winapi",
+ "windows-sys",
 ]
 
-[[package]]
-name = "winapi-x86_64-pc-windows-gnu"
-version = "0.4.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "712e227841d057c1ee1cd2fb22fa7e5a5461ae8e48fa2ca79ec42cfc1931183f"
-
 [[package]]
 name = "windows-sys"
 version = "0.52.0"
@@ -1139,13 +1124,14 @@ dependencies = [
 
 [[package]]
 name = "windows-targets"
-version = "0.52.4"
+version = "0.52.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7dd37b7e5ab9018759f893a1952c9420d060016fc19a472b4bb20d1bdd694d1b"
+checksum = "6f0713a46559409d202e70e28227288446bf7841d3211583a4b53e3f6d96e7eb"
 dependencies = [
  "windows_aarch64_gnullvm",
  "windows_aarch64_msvc",
  "windows_i686_gnu",
+ "windows_i686_gnullvm",
  "windows_i686_msvc",
  "windows_x86_64_gnu",
  "windows_x86_64_gnullvm",
@@ -1154,51 +1140,57 @@ dependencies = [
 
 [[package]]
 name = "windows_aarch64_gnullvm"
-version = "0.52.4"
+version = "0.52.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "bcf46cf4c365c6f2d1cc93ce535f2c8b244591df96ceee75d8e83deb70a9cac9"
+checksum = "7088eed71e8b8dda258ecc8bac5fb1153c5cffaf2578fc8ff5d61e23578d3263"
 
 [[package]]
 name = "windows_aarch64_msvc"
-version = "0.52.4"
+version = "0.52.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "da9f259dd3bcf6990b55bffd094c4f7235817ba4ceebde8e6d11cd0c5633b675"
+checksum = "9985fd1504e250c615ca5f281c3f7a6da76213ebd5ccc9561496568a2752afb6"
 
 [[package]]
 name = "windows_i686_gnu"
-version = "0.52.4"
+version = "0.52.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "88ba073cf16d5372720ec942a8ccbf61626074c6d4dd2e745299726ce8b89670"
+
+[[package]]
+name = "windows_i686_gnullvm"
+version = "0.52.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b474d8268f99e0995f25b9f095bc7434632601028cf86590aea5c8a5cb7801d3"
+checksum = "87f4261229030a858f36b459e748ae97545d6f1ec60e5e0d6a3d32e0dc232ee9"
 
 [[package]]
 name = "windows_i686_msvc"
-version = "0.52.4"
+version = "0.52.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1515e9a29e5bed743cb4415a9ecf5dfca648ce85ee42e15873c3cd8610ff8e02"
+checksum = "db3c2bf3d13d5b658be73463284eaf12830ac9a26a90c717b7f771dfe97487bf"
 
 [[package]]
 name = "windows_x86_64_gnu"
-version = "0.52.4"
+version = "0.52.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "5eee091590e89cc02ad514ffe3ead9eb6b660aedca2183455434b93546371a03"
+checksum = "4e4246f76bdeff09eb48875a0fd3e2af6aada79d409d33011886d3e1581517d9"
 
 [[package]]
 name = "windows_x86_64_gnullvm"
-version = "0.52.4"
+version = "0.52.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "77ca79f2451b49fa9e2af39f0747fe999fcda4f5e241b2898624dca97a1f2177"
+checksum = "852298e482cd67c356ddd9570386e2862b5673c85bd5f88df9ab6802b334c596"
 
 [[package]]
 name = "windows_x86_64_msvc"
-version = "0.52.4"
+version = "0.52.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "32b752e52a2da0ddfbdbcc6fceadfeede4c939ed16d13e648833a61dfb611ed8"
+checksum = "bec47e5bfd1bff0eeaf6d8b485cc1074891a197ab4225d504cb7a1ab88b02bf0"
 
 [[package]]
 name = "winnow"
-version = "0.6.5"
+version = "0.6.8"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "dffa400e67ed5a4dd237983829e66475f0a4a26938c4b04c21baede6262215b8"
+checksum = "c3c52e9c97a68071b23e836c9380edae937f17b9c4667bd021973efc689f618d"
 dependencies = [
  "memchr",
 ]
diff --git a/xtask/Cargo.toml b/xtask/Cargo.toml
index 36e5361e1c..df41f9753e 100644
--- a/xtask/Cargo.toml
+++ b/xtask/Cargo.toml
@@ -5,13 +5,13 @@ edition = "2021"
 publish = false
 
 [dependencies]
-anyhow     = "1.0.81"
+anyhow     = "1.0.86"
 clap       = { version = "4.5.4", features = ["derive"] }
 env_logger = "0.11.3"
-form       = "0.11.1"
+form       = "0.12.1"
 log        = "0.4.21"
-semver     = "1.0.22"
+semver     = "1.0.23"
 strum      = { version = "0.26.2", features = ["derive"] }
-svd2rust   = { version = "0.33.0", default-features = false }
+svd2rust   = { version = "0.33.3", default-features = false }
 svdtools   = "0.3.14"
-toml_edit  = "0.22.9"
+toml_edit  = "0.22.13"
diff --git a/xtask/src/main.rs b/xtask/src/main.rs
index 5fdb95edeb..1a4f5c64a7 100644
--- a/xtask/src/main.rs
+++ b/xtask/src/main.rs
@@ -375,7 +375,7 @@ fn format(path: &Path) -> Result<()> {
 
     let base_dir = path.join("src");
     let string_contents = fs::read_to_string(&lib_file)?;
-    form::create_directory_structure(base_dir, &string_contents).map_err(Error::msg)?;
+    form::create_directory_structure(base_dir, &string_contents, false).map_err(Error::msg)?;
 
     fs::remove_file(&lib_file)?;